bma253(4829).h 22 KB

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  1. /*
  2. * Licensed to the Apache Software Foundation (ASF) under one
  3. * or more contributor license agreements. See the NOTICE file
  4. * distributed with this work for additional information
  5. * regarding copyright ownership. The ASF licenses this file
  6. * to you under the Apache License, Version 2.0 (the
  7. * "License"); you may not use this file except in compliance
  8. * with the License. You may obtain a copy of the License at
  9. *
  10. * http://www.apache.org/licenses/LICENSE-2.0
  11. *
  12. * Unless required by applicable law or agreed to in writing,
  13. * software distributed under the License is distributed on an
  14. * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
  15. * KIND, either express or implied. See the License for the
  16. * specific language governing permissions and limitations
  17. * under the License.
  18. */
  19. #ifndef __BMA253_PRIV_H__
  20. #define __BMA253_PRIV_H__
  21. #include "main.h"
  22. #include <stdbool.h>
  23. #ifdef __cplusplus
  24. extern "C" {
  25. #endif
  26. /*
  27. * Full register map:
  28. */
  29. #define REG_ADDR_BGW_CHIPID 0x00 /* r */
  30. /* RESERVED */ /* */
  31. #define REG_ADDR_ACCD_X_LSB 0x02 /* r */
  32. #define REG_ADDR_ACCD_X_MSB 0x03 /* r */
  33. #define REG_ADDR_ACCD_Y_LSB 0x04 /* r */
  34. #define REG_ADDR_ACCD_Y_MSB 0x05 /* r */
  35. #define REG_ADDR_ACCD_Z_LSB 0x06 /* r */
  36. #define REG_ADDR_ACCD_Z_MSB 0x07 /* r */
  37. #define REG_ADDR_ACCD_TEMP 0x08 /* r */
  38. #define REG_ADDR_INT_STATUS_0 0x09 /* r */
  39. #define REG_ADDR_INT_STATUS_1 0x0A /* r */
  40. #define REG_ADDR_INT_STATUS_2 0x0B /* r */
  41. #define REG_ADDR_INT_STATUS_3 0x0C /* r */
  42. /* RESERVED */ /* */
  43. #define REG_ADDR_FIFO_STATUS 0x0E /* r */
  44. #define REG_ADDR_PMU_RANGE 0x0F /* rw */
  45. #define REG_ADDR_PMU_BW 0x10 /* rw */
  46. #define REG_ADDR_PMU_LPW 0x11 /* rw */
  47. #define REG_ADDR_PMU_LOW_POWER 0x12 /* rw */
  48. #define REG_ADDR_ACCD_HBW 0x13 /* rw */
  49. #define REG_ADDR_BGW_SOFTRESET 0x14 /* w */
  50. /* RESERVED */ /* */
  51. #define REG_ADDR_INT_EN_0 0x16 /* rw */
  52. #define REG_ADDR_INT_EN_1 0x17 /* rw */
  53. #define REG_ADDR_INT_EN_2 0x18 /* rw */
  54. #define REG_ADDR_INT_MAP_0 0x19 /* rw */
  55. #define REG_ADDR_INT_MAP_1 0x1A /* rw */
  56. #define REG_ADDR_INT_MAP_2 0x1B /* rw */
  57. /* RESERVED */ /* */
  58. /* RESERVED */ /* */
  59. #define REG_ADDR_INT_SRC 0x1E /* rw */
  60. /* RESERVED */ /* */
  61. #define REG_ADDR_INT_OUT_CTRL 0x20 /* rw */
  62. #define REG_ADDR_INT_RST_LATCH 0x21 /* rw */
  63. #define REG_ADDR_INT_0 0x22 /* rw */
  64. #define REG_ADDR_INT_1 0x23 /* rw */
  65. #define REG_ADDR_INT_2 0x24 /* rw */
  66. #define REG_ADDR_INT_3 0x25 /* rw */
  67. #define REG_ADDR_INT_4 0x26 /* rw */
  68. #define REG_ADDR_INT_5 0x27 /* rw */
  69. #define REG_ADDR_INT_6 0x28 /* rw */
  70. #define REG_ADDR_INT_7 0x29 /* rw */
  71. #define REG_ADDR_INT_8 0x2A /* rw */
  72. #define REG_ADDR_INT_9 0x2B /* rw */
  73. #define REG_ADDR_INT_A 0x2C /* rw */
  74. #define REG_ADDR_INT_B 0x2D /* rw */
  75. #define REG_ADDR_INT_C 0x2E /* rw */
  76. #define REG_ADDR_INT_D 0x2F /* rw */
  77. #define REG_ADDR_FIFO_CONFIG_0 0x30 /* rw */
  78. /* RESERVED */ /* */
  79. #define REG_ADDR_PMU_SELF_TEST 0x32 /* rw */
  80. #define REG_ADDR_TRIM_NVM_CTRL 0x33 /* rw */
  81. #define REG_ADDR_BGW_SPI3_WDT 0x34 /* rw */
  82. /* RESERVED */ /* */
  83. #define REG_ADDR_OFC_CTRL 0x36 /* rw */
  84. #define REG_ADDR_OFC_SETTING 0x37 /* rw */
  85. #define REG_ADDR_OFC_OFFSET_X 0x38 /* rw nvm */
  86. #define REG_ADDR_OFC_OFFSET_Y 0x39 /* rw nvm */
  87. #define REG_ADDR_OFC_OFFSET_Z 0x3A /* rw nvm */
  88. #define REG_ADDR_TRIM_GP0 0x3B /* rw nvm */
  89. #define REG_ADDR_TRIM_GP1 0x3C /* rw nvm */
  90. /* RESERVED */ /* */
  91. #define REG_ADDR_FIFO_CONFIG_1 0x3E /* rw */
  92. #define REG_ADDR_FIFO_DATA 0x3F /* r */
  93. /* Magical value that the chip always reports as its ID */
  94. #define REG_VALUE_CHIP_ID 0xFA
  95. /* Magical value that is used to initiate a full reset */
  96. #define REG_VALUE_SOFT_RESET 0xB6
  97. #define SPEC_MAX_FIFO_DEPTH 31
  98. #define BMA253_SPI_READ_CMD_BIT 0x80
  99. #define BMA253_SAMPLE_COUNT_TO_INVALIDATE 4
  100. /* variant specifc defines */
  101. #define BMA253_G_SCALE_2 (0.000977f)
  102. #define BMA253_G_SCALE_4 (0.001953f)
  103. #define BMA253_G_SCALE_8 (0.003906f)
  104. #define BMA253_G_SCALE_16 (0.007813f)
  105. #define BMA253_ACCEL_BIT_SHIFT 4
  106. #define BMA253_DATA_LSB_MASK 0xfc
  107. /* Get the chip ID */
  108. int
  109. bma253_get_chip_id(const struct bma253 * bma253,
  110. uint8_t * chip_id);
  111. /* All three axis types */
  112. enum axis {
  113. AXIS_X = 0,
  114. AXIS_Y = 1,
  115. AXIS_Z = 2,
  116. AXIS_ALL = 3,
  117. };
  118. /* A single accelerometer measurement for one axis */
  119. struct accel_data {
  120. float accel_g;
  121. bool new_data;
  122. };
  123. /* Get an accelerometer measurement for a single axis */
  124. int
  125. bma253_get_accel(const struct bma253 * bma253,
  126. enum bma253_g_range g_range,
  127. enum axis axis,
  128. struct accel_data * accel_data);
  129. /* Get a temperature measurement */
  130. int
  131. bma253_get_temp(const struct bma253 * bma253,
  132. float * temp_c);
  133. /* Which direction in an axis was this interrupt triggered on */
  134. enum axis_trigger_sign {
  135. AXIS_TRIGGER_SIGN_POS = 0,
  136. AXIS_TRIGGER_SIGN_NEG = 1,
  137. };
  138. /* Which axis was this interrupt triggered on */
  139. struct axis_trigger {
  140. /* value of type enum axis_trigger_sign */
  141. uint8_t sign :1;
  142. /* value of type enum axis */
  143. uint8_t axis :2;
  144. uint8_t axis_known :1;
  145. };
  146. /* Active status of all interrupts */
  147. typedef struct {
  148. union {
  149. struct {
  150. uint8_t low_g_int_active :1;
  151. uint8_t high_g_int_active :1;
  152. uint8_t slope_int_active :1;
  153. uint8_t slow_no_mot_int_active :1;
  154. uint8_t d_tap_int_active :1;
  155. uint8_t s_tap_int_active :1;
  156. uint8_t orient_int_active :1;
  157. uint8_t flat_int_active :1;
  158. } bits;
  159. uint8_t reg;
  160. } int_status_0;
  161. union {
  162. struct {
  163. uint8_t reserved_1 :5;
  164. uint8_t fifo_full_int_active :1;
  165. uint8_t fifo_wmark_int_active :1;
  166. uint8_t data_int_active :1;
  167. } bits;
  168. uint8_t reg;
  169. } int_status_1;
  170. uint8_t slope_first :3;
  171. uint8_t slope_sign :1;
  172. uint8_t tap_first :3;
  173. uint8_t tap_sign :1;
  174. uint8_t high_first :3;
  175. uint8_t high_sign :1;
  176. /* value of type: enum bma253_orient_xy */
  177. uint8_t device_orientation:2;
  178. uint8_t device_is_down :1;
  179. uint8_t device_is_flat :1;
  180. uint8_t stat_reg[4];
  181. } bma253_int_stat_t;
  182. #define BMA253_GET_VAL_BIT(val, bit) (((val)>>(bit)) & 0x01)
  183. #define BMA253_GET_VAL_BIT_BLOCK(val, start, end) (((val)>>(start)) & ((1<<(end - (start) + 1))-1))
  184. #define BMA253_SET_VAL_BIT(val, bit) (val | (1 << (bit)))
  185. /* Get the active status of all interrupts */
  186. int
  187. bma253_get_int_status(const struct bma253 * bma253,
  188. bma253_int_stat_t * int_status);
  189. /* Get the status and size of the FIFO */
  190. int
  191. bma253_get_fifo_status(const struct bma253 * bma253,
  192. bool * overrun,
  193. uint8_t * frame_counter);
  194. /* Get/Set the accelerometer range */
  195. int
  196. bma253_get_g_range(const struct bma253 * bma253,
  197. enum bma253_g_range * g_range);
  198. int
  199. bma253_set_g_range(const struct bma253 * bma253,
  200. enum bma253_g_range g_range);
  201. /* Get/Set the filter output bandwidth */
  202. int
  203. bma253_get_filter_bandwidth(const struct bma253 * bma253,
  204. enum bma253_filter_bandwidth * filter_bandwidth);
  205. int
  206. bma253_set_filter_bandwidth(const struct bma253 * bma253,
  207. enum bma253_filter_bandwidth filter_bandwidth);
  208. /* Whether the sleep timer is locked to events or to time */
  209. enum sleep_timer {
  210. SLEEP_TIMER_EVENT_DRIVEN = 0,
  211. SLEEP_TIMER_EQUIDISTANT_SAMPLING = 1,
  212. };
  213. /* Power settings of the device */
  214. /* Get/Set the power settings of the device */
  215. int
  216. bma253_get_power_settings(const struct bma253 * bma253,
  217. struct power_settings * power_settings);
  218. int
  219. bma253_set_power_settings(const struct bma253 * bma253,
  220. const struct power_settings * power_settings);
  221. /* Get/Set the data register settings */
  222. int
  223. bma253_get_data_acquisition(const struct bma253 * bma253,
  224. bool * unfiltered_reg_data,
  225. bool * disable_reg_shadow);
  226. int
  227. bma253_set_data_acquisition(const struct bma253 * bma253,
  228. bool unfiltered_reg_data,
  229. bool disable_reg_shadow);
  230. /* Kick off a full soft reset of the device */
  231. int
  232. bma253_set_softreset(const struct bma253 * bma253);
  233. /* Enable settings of all interupts */
  234. struct int_enable {
  235. bool flat_int_enable;
  236. bool orient_int_enable;
  237. bool s_tap_int_enable;
  238. bool d_tap_int_enable;
  239. bool slope_z_int_enable;
  240. bool slope_y_int_enable;
  241. bool slope_x_int_enable;
  242. bool fifo_wmark_int_enable;
  243. bool fifo_full_int_enable;
  244. bool data_int_enable;
  245. bool low_g_int_enable;
  246. bool high_g_z_int_enable;
  247. bool high_g_y_int_enable;
  248. bool high_g_x_int_enable;
  249. bool no_motion_select;
  250. bool slow_no_mot_z_int_enable;
  251. bool slow_no_mot_y_int_enable;
  252. bool slow_no_mot_x_int_enable;
  253. };
  254. /* Get/Set the enable settings of all interrupts */
  255. int
  256. bma253_get_int_enable(const struct bma253 * bma253,
  257. struct int_enable * int_enable);
  258. int
  259. bma253_set_int_enable(const struct bma253 * bma253,
  260. const struct int_enable * int_enable);
  261. /* Which physical device pin is a given interrupt routed to */
  262. enum int_route {
  263. INT_ROUTE_NONE = 0,
  264. INT_ROUTE_PIN_1 = 1,
  265. INT_ROUTE_PIN_2 = 2,
  266. INT_ROUTE_BOTH = 3,
  267. };
  268. enum bma253_int_num {
  269. INT1_PIN,
  270. INT2_PIN
  271. };
  272. /* Pin routing settings of all interrupts */
  273. struct int_routes {
  274. enum int_route flat_int_route;
  275. enum int_route orient_int_route;
  276. enum int_route s_tap_int_route;
  277. enum int_route d_tap_int_route;
  278. enum int_route slow_no_mot_int_route;
  279. enum int_route slope_int_route;
  280. enum int_route high_g_int_route;
  281. enum int_route low_g_int_route;
  282. enum int_route fifo_wmark_int_route;
  283. enum int_route fifo_full_int_route;
  284. enum int_route data_int_route;
  285. };
  286. /* Get/Set the pin routing settings of all interrupts */
  287. int
  288. bma253_get_int_routes(const struct bma253 * bma253,
  289. struct int_routes * int_routes);
  290. int
  291. bma253_set_int_routes(const struct bma253 * bma253,
  292. const struct int_routes * int_routes);
  293. /* Whether each interrupt uses filtered or unfiltered data */
  294. struct int_filters {
  295. bool unfiltered_data_int;
  296. bool unfiltered_tap_int;
  297. bool unfiltered_slow_no_mot_int;
  298. bool unfiltered_slope_int;
  299. bool unfiltered_high_g_int;
  300. bool unfiltered_low_g_int;
  301. };
  302. /* Get/Set the filtered data settings of all interrupts */
  303. int
  304. bma253_get_int_filters(const struct bma253 * bma253,
  305. struct int_filters * int_filters);
  306. int
  307. bma253_set_int_filters(const struct bma253 * bma253,
  308. const struct int_filters * int_filters);
  309. /* Drive mode of the interrupt pins */
  310. enum int_pin_output {
  311. INT_PIN_OUTPUT_PUSH_PULL = 0,
  312. INT_PIN_OUTPUT_OPEN_DRAIN = 1,
  313. };
  314. /* Active mode of the interrupt pins */
  315. enum int_pin_active {
  316. INT_PIN_ACTIVE_LOW = 0,
  317. INT_PIN_ACTIVE_HIGH = 1,
  318. };
  319. /* Electrical settings of both interrupt pins */
  320. struct int_pin_electrical {
  321. enum int_pin_output pin1_output;
  322. enum int_pin_active pin1_active;
  323. enum int_pin_output pin2_output;
  324. enum int_pin_active pin2_active;
  325. };
  326. /* Get/Set the electrical settings of both interrupt pins */
  327. int
  328. bma253_get_int_pin_electrical(const struct bma253 * bma253,
  329. struct int_pin_electrical * electrical);
  330. int
  331. bma253_set_int_pin_electrical(const struct bma253 * bma253,
  332. const struct int_pin_electrical * electrical);
  333. /* Length of time that an interrupt condition should be latched active */
  334. enum int_latch {
  335. INT_LATCH_NON_LATCHED = 0,
  336. INT_LATCH_LATCHED = 1,
  337. INT_LATCH_TEMPORARY_250_US = 2,
  338. INT_LATCH_TEMPORARY_500_US = 3,
  339. INT_LATCH_TEMPORARY_1_MS = 4,
  340. INT_LATCH_TEMPORARY_12_5_MS = 5,
  341. INT_LATCH_TEMPORARY_25_MS = 6,
  342. INT_LATCH_TEMPORARY_50_MS = 7,
  343. INT_LATCH_TEMPORARY_250_MS = 8,
  344. INT_LATCH_TEMPORARY_500_MS = 9,
  345. INT_LATCH_TEMPORARY_1_S = 10,
  346. INT_LATCH_TEMPORARY_2_S = 11,
  347. INT_LATCH_TEMPORARY_4_S = 12,
  348. INT_LATCH_TEMPORARY_8_S = 13,
  349. };
  350. /* Get/Set the interrupt condition latch time */
  351. int
  352. bma253_get_int_latch(const struct bma253 * bma253,
  353. enum int_latch * int_latch);
  354. int
  355. bma253_set_int_latch(const struct bma253 * bma253,
  356. bool reset_ints,
  357. enum int_latch int_latch);
  358. /* Settings for the low-g interrupt */
  359. struct low_g_int_cfg {
  360. uint16_t delay_ms;
  361. float thresh_g;
  362. float hyster_g;
  363. bool axis_summing;
  364. };
  365. /* Get/Set the low-g interrupt settings */
  366. int
  367. bma253_get_low_g_int_cfg(const struct bma253 * bma253,
  368. struct low_g_int_cfg * low_g_int_cfg);
  369. int
  370. bma253_set_low_g_int_cfg(const struct bma253 * bma253,
  371. const struct low_g_int_cfg * low_g_int_cfg);
  372. /* Settings for the high-g interrupt */
  373. struct high_g_int_cfg {
  374. float hyster_g;
  375. uint16_t delay_ms;
  376. float thresh_g;
  377. };
  378. /* Get/Set the high-g interrupt settings */
  379. int
  380. bma253_get_high_g_int_cfg(const struct bma253 * bma253,
  381. enum bma253_g_range g_range,
  382. struct high_g_int_cfg * high_g_int_cfg);
  383. int
  384. bma253_set_high_g_int_cfg(const struct bma253 * bma253,
  385. enum bma253_g_range g_range,
  386. const struct high_g_int_cfg * high_g_int_cfg);
  387. /* Settings for the slow/no-motion interrupt */
  388. struct slow_no_mot_int_cfg {
  389. uint16_t duration_p_or_s;
  390. float thresh_g;
  391. };
  392. /* Get/Set the slow/no-motion interrupt settings */
  393. int
  394. bma253_get_slow_no_mot_int_cfg(const struct bma253 * bma253,
  395. bool no_motion_select,
  396. enum bma253_g_range g_range,
  397. struct slow_no_mot_int_cfg * slow_no_mot_int_cfg);
  398. int
  399. bma253_set_slow_no_mot_int_cfg(const struct bma253 * bma253,
  400. bool no_motion_select,
  401. enum bma253_g_range g_range,
  402. const struct slow_no_mot_int_cfg * slow_no_mot_int_cfg);
  403. /* Settings for the slope interrupt */
  404. struct slope_int_cfg {
  405. uint8_t duration_p;
  406. float thresh_g;
  407. };
  408. /* Get/Set the slope interrupt settings */
  409. int
  410. bma253_get_slope_int_cfg(const struct bma253 * bma253,
  411. enum bma253_g_range g_range,
  412. struct slope_int_cfg * slope_int_cfg);
  413. int
  414. bma253_set_slope_int_cfg(const struct bma253 * bma253,
  415. enum bma253_g_range g_range,
  416. const struct slope_int_cfg * slope_int_cfg);
  417. /* Settings for the double/single tap interrupt */
  418. /* Get/Set the double/single tap interrupt settings */
  419. int
  420. bma253_get_tap_int_cfg(const struct bma253 * bma253,
  421. enum bma253_g_range g_range,
  422. struct tap_int_cfg * tap_int_cfg);
  423. int
  424. bma253_set_tap_int_cfg(const struct bma253 * bma253,
  425. enum bma253_g_range g_range,
  426. const struct tap_int_cfg * tap_int_cfg);
  427. /* Settings for the orientation interrupt */
  428. struct orient_int_cfg {
  429. float hyster_g;
  430. bool signal_up_dn;
  431. uint8_t blocking_angle;
  432. };
  433. /* Get/Set the orientation interrupt settings */
  434. int
  435. bma253_get_orient_int_cfg(const struct bma253 * bma253,
  436. struct orient_int_cfg * orient_int_cfg);
  437. int
  438. bma253_set_orient_int_cfg(const struct bma253 * bma253,
  439. const struct orient_int_cfg * orient_int_cfg);
  440. /* Hold time for flat condition */
  441. enum flat_hold {
  442. FLAT_HOLD_0_MS = 0,
  443. FLAT_HOLD_512_MS = 1,
  444. FLAT_HOLD_1024_MS = 2,
  445. FLAT_HOLD_2048_MS = 3,
  446. };
  447. /* Settings for the flat interrupt */
  448. struct flat_int_cfg {
  449. uint8_t flat_angle;
  450. enum flat_hold flat_hold;
  451. uint8_t flat_hyster;
  452. bool hyster_enable;
  453. };
  454. /* Get/Set the flat interrupt settings */
  455. int
  456. bma253_get_flat_int_cfg(const struct bma253 * bma253,
  457. struct flat_int_cfg * flat_int_cfg);
  458. int
  459. bma253_set_flat_int_cfg(const struct bma253 * bma253,
  460. const struct flat_int_cfg * flat_int_cfg);
  461. /* Get/Set the FIFO watermark level */
  462. int
  463. bma253_get_fifo_wmark_level(const struct bma253 * bma253,
  464. uint8_t * wmark_level);
  465. int
  466. bma253_set_fifo_wmark_level(const struct bma253 * bma253,
  467. uint8_t wmark_level);
  468. /* Amplitude of a self-test induced acceleration */
  469. enum self_test_ampl {
  470. SELF_TEST_AMPL_HIGH = 0,
  471. SELF_TEST_AMPL_LOW = 1,
  472. };
  473. /* Direction of a self-test induced acceleration */
  474. enum self_test_sign {
  475. SELF_TEST_SIGN_NEGATIVE = 0,
  476. SELF_TEST_SIGN_POSITIVE = 1,
  477. };
  478. /* Settings for the self-test functionality */
  479. struct self_test_cfg {
  480. enum self_test_ampl self_test_ampl;
  481. enum self_test_sign self_test_sign;
  482. enum axis self_test_axis;
  483. bool self_test_enabled;
  484. };
  485. /* Get/Set the self-test settings */
  486. int
  487. bma253_get_self_test_cfg(const struct bma253 * bma253,
  488. struct self_test_cfg * self_test_cfg);
  489. int
  490. bma253_set_self_test_cfg(const struct bma253 * bma253,
  491. const struct self_test_cfg * self_test_cfg);
  492. /* Get/Set the NVM reset/write control values */
  493. int
  494. bma253_get_nvm_control(const struct bma253 * bma253,
  495. uint8_t * remaining_cycles,
  496. bool * load_from_nvm,
  497. bool * nvm_is_ready,
  498. bool * nvm_unlocked);
  499. int
  500. bma253_set_nvm_control(const struct bma253 * bma253,
  501. bool load_from_nvm,
  502. bool store_into_nvm,
  503. bool nvm_unlocked);
  504. /* Length of time before the I2C watchdog fires */
  505. enum i2c_watchdog {
  506. I2C_WATCHDOG_DISABLED = 0,
  507. I2C_WATCHDOG_1_MS = 1,
  508. I2C_WATCHDOG_50_MS = 2,
  509. };
  510. /* Get/Set the I2C watchdog settings */
  511. int
  512. bma253_get_i2c_watchdog(const struct bma253 * bma253,
  513. enum i2c_watchdog * i2c_watchdog);
  514. int
  515. bma253_set_i2c_watchdog(const struct bma253 * bma253,
  516. enum i2c_watchdog i2c_watchdog);
  517. /* Offset compensation settings used in slow compensation mode */
  518. struct slow_ofc_cfg {
  519. bool ofc_z_enabled;
  520. bool ofc_y_enabled;
  521. bool ofc_x_enabled;
  522. bool high_bw_cut_off;
  523. };
  524. /* Get/Set the fast & slow offset compensation mode settings, and reset all
  525. * offset compensation values back to NVM defaults */
  526. int
  527. bma253_get_fast_ofc_cfg(const struct bma253 * bma253,
  528. bool * fast_ofc_ready,
  529. enum bma253_offset_comp_target * ofc_target_z,
  530. enum bma253_offset_comp_target * ofc_target_y,
  531. enum bma253_offset_comp_target * ofc_target_x);
  532. int
  533. bma253_set_fast_ofc_cfg(const struct bma253 * bma253,
  534. enum axis fast_ofc_axis,
  535. enum bma253_offset_comp_target fast_ofc_target,
  536. bool trigger_fast_ofc);
  537. int
  538. bma253_get_slow_ofc_cfg(const struct bma253 * bma253,
  539. struct slow_ofc_cfg * slow_ofc_cfg);
  540. int
  541. bma253_set_slow_ofc_cfg(const struct bma253 * bma253,
  542. const struct slow_ofc_cfg * slow_ofc_cfg);
  543. int
  544. bma253_set_ofc_reset(const struct bma253 * bma253);
  545. /* Get/Set the offset compensation value for a specific axis */
  546. int
  547. bma253_get_ofc_offset(const struct bma253 * bma253,
  548. enum axis axis,
  549. float * offset_g);
  550. int
  551. bma253_set_ofc_offset(const struct bma253 * bma253,
  552. enum axis axis,
  553. float offset_g);
  554. /* General purpose non-volatile data registers */
  555. enum saved_data_addr {
  556. SAVED_DATA_ADDR_0 = 0,
  557. SAVED_DATA_ADDR_1 = 1,
  558. };
  559. /* Get/Set the data stored in general purpose non-volatile registers */
  560. int
  561. bma253_get_saved_data(const struct bma253 * bma253,
  562. enum saved_data_addr saved_data_addr,
  563. uint8_t * saved_data_val);
  564. int
  565. bma253_set_saved_data(const struct bma253 * bma253,
  566. enum saved_data_addr saved_data_addr,
  567. uint8_t saved_data_val);
  568. /* Mode that the FIFO is running in */
  569. enum fifo_mode {
  570. FIFO_MODE_BYPASS = 0,
  571. FIFO_MODE_FIFO = 1,
  572. FIFO_MODE_STREAM = 2,
  573. };
  574. /* Measurements for which axis to capture into the FIFO */
  575. enum fifo_data {
  576. FIFO_DATA_X_AND_Y_AND_Z = 0,
  577. FIFO_DATA_X_ONLY = 1,
  578. FIFO_DATA_Y_ONLY = 2,
  579. FIFO_DATA_Z_ONLY = 3,
  580. };
  581. /* FIFO capture and behavior settings */
  582. struct fifo_cfg {
  583. enum fifo_mode fifo_mode;
  584. enum fifo_data fifo_data;
  585. };
  586. /* Get/Set the FIFO capture and behavior settings */
  587. int
  588. bma253_get_fifo_cfg(const struct bma253 * bma253,
  589. struct fifo_cfg * fifo_cfg);
  590. int
  591. bma253_set_fifo_cfg(const struct bma253 * bma253,
  592. const struct fifo_cfg * fifo_cfg);
  593. /* Read a single multi-axis data frame from the FIFO */
  594. int
  595. bma253_get_fifo(const struct bma253 * bma253,
  596. enum bma253_g_range g_range,
  597. enum fifo_data fifo_data,
  598. struct accel_data * accel_data);
  599. void bma253_dump_reg(struct bma253 * bma253);
  600. #ifdef __cplusplus
  601. }
  602. #endif
  603. #endif