bma253_defs(2957).h 30 KB

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  1. /**
  2. * @brief : this
  3. * @file : bma253_defs.h
  4. * @version : v0.0.1
  5. * @author : gang.cheng
  6. * @date : 2017-06-02
  7. * change logs :
  8. * Date Version Author Note
  9. * 2017-06-02 v0.0.1 gang.cheng first version
  10. */
  11. #ifndef __BMA253_DEFS_H__
  12. #define __BMA253_DEFS_H__
  13. #define BMA253_DEFAULT_ADDR 0x18
  14. #define BMA253_CHIP_ID 0xFA
  15. #define BMA253_RESET_BYTE 0xB6
  16. // NOTE: Reserved registers must not be written into. Reading
  17. // from them may return indeterminate values. Registers
  18. // containing reserved bitfields must be written as 0. Reading
  19. // reserved bitfields may return indeterminate values.
  20. /**
  21. * BMA253 registers
  22. */
  23. typedef enum
  24. {
  25. BMA253_REG_BGW_CHIPID = 0x00, // R
  26. // 0x01 reserved
  27. BMA253_REG_ACCD_X_LSB = 0x02, // R acc_x_lsb<3:0>:new_data_x
  28. BMA253_REG_ACCD_X_MSB = 0x03, // R acc_x_msb<11:4>
  29. BMA253_REG_ACCD_Y_LSB = 0x04, // R acc_y_lsb<3:0>:new_data_y
  30. BMA253_REG_ACCD_Y_MSB = 0x05, // R acc_y_msb<11:4>
  31. BMA253_REG_ACCD_Z_LSB = 0x06, // R acc_z_lsb<3:0>:new_data_z
  32. BMA253_REG_ACCD_Z_MSB = 0x07, // R acc_z_msb<11:4>
  33. BMA253_REG_ACCD_TEMP = 0x08, // R temp<7:0>
  34. BMA253_REG_INT_STATUS_0 = 0x09, // R falt:orient:s_tap:d_tap:slo_no_mot:slope:high:low
  35. BMA253_REG_INT_STATUS_1 = 0x0A, // R data:fifo_wm:fifo_full
  36. BMA253_REG_INT_STATUS_2 = 0x0B, // R tap_sign:tap_first_<z:y:x>:slope_sign:slope_first_<z:y:x>
  37. BMA253_REG_INT_STATUS_3 = 0x0C, // R flat:orient<2:0>:high_sign:high_first_<z:y:x>
  38. // 0x0d reserved
  39. BMA253_REG_FIFO_STATUS = 0x0E, // R fifo_overrun:fifo_frame_counter<6:0>
  40. BMA253_REG_PMU_RANGE = 0x0F, // R/W range<3:0>
  41. BMA253_REG_PMU_BW = 0x10, // R/W bw<3:0>
  42. BMA253_REG_PMU_LPW = 0x11, // R/W suspend:lowpower_en:deep_suspend:sleep_dur<3:0>
  43. BMA253_REG_PMU_LOW_POWER = 0x12, // R/W lowpower_mode:sleeptimer_mode
  44. BMA253_REG_ACCD_HBW = 0x13, // R/W data_high_bw:shadow_dis
  45. BMA253_REG_BGW_SOFTRESET = 0x14, // W softreset
  46. // 0x15 reserved
  47. BMA253_REG_INT_EN_0 = 0x16, // R/W falt:orient:s_tap:d_tap:slope_en_<z:y:x>
  48. BMA253_REG_INT_EN_1 = 0x17, // R/W int_fwm:int_ffull:data:low:high_en_<z:y:x>
  49. BMA253_REG_INT_EN_2 = 0x18, // R/W slo_no_mot:slo_no_mot_en_<z:y:x>
  50. BMA253_REG_INT_MAP_0 = 0x19, // R/W int1_flat:int1_orient:int1_s_tap:int1_d_tap:int1_slo_no_mot:int1_slope:int1_high:int1_low
  51. BMA253_REG_INT_MAP_1 = 0x1A, // R/W int2_data:int2_fwm:int2_ffull:int1_ffull:int1_fwm:int1_data
  52. BMA253_REG_INT_MAP_2 = 0x1B, // R/W int2_flat:int2_orient:int2_s_tap:int2_d_tap:int2_slo_no_mot:int2_slope:int2_high:int2_low
  53. // 0x1c-0x1d reserved
  54. BMA253_REG_INT_SRC = 0x1E, // R/W int_src_data:int_src_tap:int_src_slo_no_mot:int_src_slope:int_src_high:int_src_low
  55. // 0x1f reserved
  56. BMA253_REG_INT_OUT_CTRL = 0x20, // R/W int2_od:int2_lvl:int1_od:int1_lvl
  57. BMA253_REG_INT_RST_LATCH = 0x21, // R/W reset_int:latch_int<3:0>
  58. BMA253_REG_INT_0 = 0x22, // R/W low_dur<7:0>
  59. BMA253_REG_INT_1 = 0x23, // R/W low_th<7:0>
  60. BMA253_REG_INT_2 = 0x24, // R/W high_hy<1:0>:low_mode:low_hy<1:0>
  61. BMA253_REG_INT_3 = 0X25, // R/W high_dur<7:0>
  62. BMA253_REG_INT_4 = 0X26, // R/W high_th<7:0>
  63. BMA253_REG_INT_5 = 0X27, // R/W slot_no_mot_dur<5:0>
  64. BMA253_REG_INT_6 = 0X28, // R/W slope_th<7:0>
  65. BMA253_REG_INT_7 = 0X29, // R/W slo_no_mot_th<5:0>
  66. BMA253_REG_INT_8 = 0X2A, // R/W tap_quiet:tap_shock:tap_dur<2:0>
  67. BMA253_REG_INT_9 = 0X2B, // R/W tap_samp<1:0>:tap_th<4:0>
  68. BMA253_REG_INT_A = 0X2C, // R/W orient_hyst<2:0>:orient_blocking<1:0>:orient_mode<1:0>
  69. BMA253_REG_INT_B = 0X2D, // R/W orient_ud_en:orient_theta<5:0>
  70. BMA253_REG_INT_C = 0X2E, // R/W flat_theta<5:0>
  71. BMA253_REG_INT_D = 0X2F, // R/W flat_hold_time<1:0>:flat_hy<2:0>
  72. BMA253_REG_FIFO_CONFIG_0 = 0X30, // R/W fifo_water_mark_level_trigger_retain<5:0>
  73. // 0x31 reserved
  74. BMA253_REG_PMU_SELF_TEST = 0X32, // R/W self_test_amp:self_test_sign:self_test_axis<1:0>
  75. BMA253_REG_TRIM_NVM_CTRL = 0X33, // R/W nvm_remain<3:0>:nvm_load:nvm_rdy:nvm_prog_trig:nvm_prog_mode
  76. BMA253_REG_BGW_SPI3_WDT = 0X34, // R/W i2c_wdt_en:i2c_wdt_sel:spi3
  77. // 0x35 reserved
  78. BMA253_REG_OFC_CTRL = 0x36, // R/W offset_rest:cal_trigger<1:0>:cal_rdy:hp_<z:y:x>_en
  79. BMA253_REG_OFC_SETTING = 0x37, // R/W offset_target_<z:y:x><1:0>:cut_off
  80. BMA253_REG_OFC_OFFSET_X = 0x38, // R/W offset_x<7:0>
  81. BMA253_REG_OFC_OFFSET_Y = 0x39, // R/W offset_y<7:0>
  82. BMA253_REG_OFC_OFFSET_Z = 0x3A, // R/W offset_z<7:0>
  83. BMA253_REG_TRIM_GP0 = 0x3B, // R/W GP0<7:0>
  84. BMA253_REG_TRIM_GP1 = 0x3C, // R/W GP1<7:0>
  85. // 0x3d reserved
  86. BMA253_REG_FIFO_CONFIG_1 = 0x3E, // R/W fifo_mode<1:0>:fifo_data_select<1:0>
  87. BMA253_REG_FIFO_DATA = 0x3F, // R/W fifo_data_output_register<7:0>
  88. } BMA253_REGS_T;
  89. /**
  90. * REG_ACCD_*_LSB bits - handle X, Y, and Z LSB regs, for 10 bit
  91. * resolution
  92. */
  93. typedef enum
  94. {
  95. BMA253_ACCD10_LSB_NEW_DATA = 0x01, // data
  96. // updated
  97. // since last
  98. // read
  99. // 0x02-0x20 reserved
  100. BMA253_ACCD10_LSB0 = 0x40, // lower 2
  101. // bits of
  102. // LSB data
  103. BMA253_ACCD10_LSB1 = 0x80,
  104. _BMA253_ACCD10_LSB_MASK = 3,
  105. _BMA253_ACCD10_LSB_SHIFT = 6
  106. } BMA253_ACCD10_LSB_BITS_T;
  107. /**
  108. * REG_ACCD_*_LSB bits - handle X, Y, and Z LSB regs, for 12 bit
  109. * resolution
  110. */
  111. typedef enum
  112. {
  113. BMA253_ACCD12_LSB_NEW_DATA = 0x01, // data
  114. // updated
  115. // since last
  116. // read
  117. // 0x02-0x08 reserved
  118. BMA253_ACCD12_LSB0 = 0x10, // lower 4
  119. // bits of
  120. // LSB data
  121. BMA253_ACCD12_LSB1 = 0x20,
  122. BMA253_ACCD12_LSB2 = 0x40,
  123. BMA253_ACCD12_LSB3 = 0x80,
  124. _BMA253_ACCD12_LSB_MASK = 15,
  125. _BMA253_ACCD12_LSB_SHIFT = 4
  126. } BMA253_ACCD12_LSB_BITS_T;
  127. /**
  128. * REG_INT_STATUS_0 bits
  129. */
  130. typedef enum
  131. {
  132. BMA253_INT_STATUS_0_LOW = 0x01,
  133. BMA253_INT_STATUS_0_HIGH = 0x02,
  134. BMA253_INT_STATUS_0_SLOPE = 0x04,
  135. BMA253_INT_STATUS_0_SLO_NOT_MOT = 0x08,
  136. BMA253_INT_STATUS_0_D_TAP = 0x10,
  137. BMA253_INT_STATUS_0_S_TAP = 0x20,
  138. BMA253_INT_STATUS_0_ORIENT = 0x40,
  139. BMA253_INT_STATUS_0_FLAT = 0x80
  140. } BMA253_INT_STATUS_0_BITS_T;
  141. /**
  142. * REG_INT_STATUS_1 bits
  143. */
  144. typedef enum
  145. {
  146. _BMA253_INT_STATUS_1_RESERVED_BITS = 0x0f | 0x10,
  147. // 0x01-0x10 reserved
  148. BMA253_INT_STATUS_1_FIFO_FULL = 0x20,
  149. BMA253_INT_STATUS_1_FIFO_WM = 0x40,
  150. BMA253_INT_STATUS_1_DATA = 0x80 // data ready int
  151. } BMA253_INT_STATUS_1_BITS_T;
  152. /**
  153. * REG_INT_STATUS_2 bits
  154. */
  155. typedef enum
  156. {
  157. BMA253_INT_STATUS_2_SLOPE_FIRST_X = 0x01,
  158. BMA253_INT_STATUS_2_SLOPE_FIRST_Y = 0x02,
  159. BMA253_INT_STATUS_2_SLOPE_FIRST_Z = 0x04,
  160. BMA253_INT_STATUS_2_SLOPE_SIGN = 0x08,
  161. BMA253_INT_STATUS_2_TAP_FIRST_X = 0x10,
  162. BMA253_INT_STATUS_2_TAP_FIRST_Y = 0x20,
  163. BMA253_INT_STATUS_2_TAP_FIRST_Z = 0x40,
  164. BMA253_INT_STATUS_2_TAP_SIGN = 0x80
  165. } BMA253_INT_STATUS_2_BITS_T;
  166. /**
  167. * REG_INT_STATUS_3 bits
  168. */
  169. typedef enum
  170. {
  171. BMA253_INT_STATUS_3_HIGH_FIRST_X = 0x01,
  172. BMA253_INT_STATUS_3_HIGH_FIRST_Y = 0x02,
  173. BMA253_INT_STATUS_3_HIGH_FIRST_Z = 0x04,
  174. BMA253_INT_STATUS_3_HIGH_SIGN = 0x08,
  175. BMA253_INT_STATUS_3_ORIENT0 = 0x10,
  176. BMA253_INT_STATUS_3_ORIENT1 = 0x20,
  177. BMA253_INT_STATUS_3_ORIENT2 = 0x40,
  178. _BMA253_INT_STATUS_3_ORIENT_MASK = 7,
  179. _BMA253_INT_STATUS_3_ORIENT_SHIFT = 4,
  180. BMA253_INT_STATUS_3_FLAT = 0x80
  181. } INT_STATUS_3_BITS_T;
  182. /**
  183. * INT_STATUS_3_ORIENT values
  184. */
  185. typedef enum
  186. {
  187. BMA253_ORIENT_POTRAIT_UPRIGHT = 0,
  188. BMA253_ORIENT_POTRAIT_UPSIDE_DOWN = 1,
  189. BMA253_ORIENT_LANDSCAPE_LEFT = 2,
  190. BMA253_ORIENT_LANDSCAPE_RIGHT = 3,
  191. } BMA253_ORIENT_T;
  192. /**
  193. * REG_FIFO_STATUS bits
  194. */
  195. typedef enum
  196. {
  197. BMA253_FIFO_STATUS_FRAME_COUNTER0 = 0x01,
  198. BMA253_FIFO_STATUS_FRAME_COUNTER1 = 0x02,
  199. BMA253_FIFO_STATUS_FRAME_COUNTER2 = 0x04,
  200. BMA253_FIFO_STATUS_FRAME_COUNTER3 = 0x08,
  201. BMA253_FIFO_STATUS_FRAME_COUNTER4 = 0x10,
  202. BMA253_FIFO_STATUS_FRAME_COUNTER5 = 0x20,
  203. BMA253_FIFO_STATUS_FRAME_COUNTER6 = 0x40,
  204. _BMA253_FIFO_STATUS_FRAME_COUNTER_MASK = 127,
  205. _BMA253_FIFO_STATUS_FRAME_COUNTER_SHIFT = 0,
  206. BMA253_FIFO_STATUS_FIFO_OVERRUN = 0x80
  207. } BMA253_FIFO_STATUS_BITS_T;
  208. /**
  209. * REG_PMU_RANGE bits
  210. */
  211. typedef enum
  212. {
  213. BMA253_PMU_RANGE0 = 0x01,
  214. BMA253_PMU_RANGE1 = 0x02,
  215. BMA253_PMU_RANGE2 = 0x04,
  216. BMA253_PMU_RANGE3 = 0x08,
  217. _BMA253_PMU_RANGE_MASK = 15,
  218. _BMA253_PMU_RANGE_SHIFT = 0
  219. // 0x10-0x80 reserved
  220. } BMA253_PMU_RANGE_BITS_T;
  221. /**
  222. * PMU_RANGE (accelerometer g-range) values
  223. */
  224. typedef enum
  225. {
  226. BMA253_RANGE_2G = 3,
  227. BMA253_RANGE_4G = 5,
  228. BMA253_RANGE_8G = 8,
  229. BMA253_RANGE_16G = 12
  230. } BMA253_RANGE_T;
  231. #define RANGE_2G_MG_LSB (0.98)
  232. #define RANGE_4G_MG_LSB (1.95)
  233. #define RANGE_8G_MG_LSB (3.91)
  234. #define RANGE_16G_MG_LSB (7.81)
  235. /**
  236. * REG_PMU_BW bits
  237. */
  238. typedef enum
  239. {
  240. BMA253_PMU_BW0 = 0x01,
  241. BMA253_PMU_BW1 = 0x02,
  242. BMA253_PMU_BW2 = 0x04,
  243. BMA253_PMU_BW3 = 0x08,
  244. BMA253_PMU_BW4 = 0x10,
  245. _BMA253_PMU_BW_MASK = 31,
  246. _BMA253_PMU_BW_SHIFT = 0
  247. // 0x20-0x80 reserved
  248. } BMA253_PMU_BW_BITS_T;
  249. /**
  250. * PMU_BW (accelerometer filter bandwidth) values
  251. */
  252. typedef enum
  253. {
  254. BMA253_BW_7_81 = 8, // 7.81 Hz
  255. BMA253_BW_15_63 = 9,
  256. BMA253_BW_31_25 = 10,
  257. BMA253_BW_62_5 = 11,
  258. BMA253_BW_125 = 12,
  259. BMA253_BW_250 = 13,
  260. BMA253_BW_500 = 14,
  261. BMA253_BW_1000 = 15
  262. } BMA253_BW_T;
  263. /**
  264. * REG_PMU_LPW bits
  265. */
  266. typedef enum
  267. {
  268. // 0x01 reserved
  269. _BMA253_PMU_LPW_RESERVED_MASK = 0x01,
  270. BMA253_PMU_LPW_SLEEP_DUR0 = 0x02, // sleep dur
  271. // in low
  272. // power mode
  273. BMA253_PMU_LPW_SLEEP_DUR1 = 0x04,
  274. BMA253_PMU_LPW_SLEEP_DUR2 = 0x08,
  275. BMA253_PMU_LPW_SLEEP_DUR3 = 0x10,
  276. _BMA253_PMU_LPW_SLEEP_MASK = 15,
  277. _BMA253_PMU_LPW_SLEEP_SHIFT = 1,
  278. // These are separate bits, deep_suspend, lowpower_en and
  279. // suspend (and if all 0, normal). Since only specific
  280. // combinations are allowed, we will treat this as a 3 bit
  281. // bitfield called POWER_MODE.
  282. BMA253_PMU_LPW_POWER_MODE0 = 0x20, // deep_suspend
  283. BMA253_PMU_LPW_POWER_MODE1 = 0x40, // lowpower_en
  284. BMA253_PMU_LPW_POWER_MODE2 = 0x80, // suspend
  285. _BMA253_PMU_LPW_POWER_MODE_MASK = 7,
  286. _BMA253_PMU_LPW_POWER_MODE_SHIFT = 5
  287. } BMA253_PMU_LPW_BITS_T;
  288. /**
  289. * SLEEP_DUR values
  290. */
  291. typedef enum
  292. {
  293. BMA253_SLEEP_DUR_0_5 = 0, // 0.5ms
  294. BMA253_SLEEP_DUR_1 = 6,
  295. BMA253_SLEEP_DUR_2 = 7,
  296. BMA253_SLEEP_DUR_4 = 8,
  297. BMA253_SLEEP_DUR_6 = 9,
  298. BMA253_SLEEP_DUR_10 = 10,
  299. BMA253_SLEEP_DUR_25 = 11,
  300. BMA253_SLEEP_DUR_50 = 12,
  301. BMA253_SLEEP_DUR_100 = 13,
  302. BMA253_SLEEP_DUR_500 = 14,
  303. BMA253_SLEEP_DUR_1000 = 15
  304. } BMA253_SLEEP_DUR_T;
  305. /**
  306. * POWER_MODE values
  307. */
  308. typedef enum
  309. {
  310. BMA253_POWER_MODE_NORMAL = 0,
  311. BMA253_POWER_MODE_DEEP_SUSPEND = 1,
  312. BMA253_POWER_MODE_LOW_POWER = 2,
  313. BMA253_POWER_MODE_SUSPEND = 4
  314. } BMA253_POWER_MODE_T;
  315. /**
  316. * REG_PMU_LOW_POWER bits
  317. */
  318. typedef enum
  319. {
  320. _BMA253_LOW_POWER_RESERVED_BITS = 0x0f | 0x10 | 0x80,
  321. // 0x01-0x10 reserved
  322. BMA253_LOW_POWER_SLEEPTIMER_MODE = 0x20,
  323. BMA253_LOW_POWER_LOWPOWER_MODE = 0x40 // LPM1 or
  324. // LPM2
  325. // mode. see
  326. // DS.
  327. // 0x80 reserved
  328. } BMA253_LOW_POWER_BITS_T;
  329. /**
  330. * REG_ACC_HBW bits
  331. */
  332. typedef enum
  333. {
  334. _BMA253_ACC_HBW_RESERVED_BITS = 0x0f | 0x10 | 0x20,
  335. // 0x01-0x20 reserved
  336. BMA253_ACC_HBW_SHADOW_DIS = 0x40,
  337. BMA253_ACC_HBW_DATA_HIGH_BW = 0x80
  338. } BMA253_ACC_HBW_BITS_T;
  339. /**
  340. * REG_INT_EN_0 bits
  341. */
  342. typedef enum
  343. {
  344. _BMA253_INT_EN_0_RESERVED_BITS = 0x08,
  345. BMA253_INT_EN_0_SLOPE_EN_X = 0x01,
  346. BMA253_INT_EN_0_SLOPE_EN_Y = 0x02,
  347. BMA253_INT_EN_0_SLOPE_EN_Z = 0x04,
  348. // 0x08 reserved
  349. BMA253_INT_EN_0_D_TAP_EN = 0x10,
  350. BMA253_INT_EN_0_S_TAP_EN = 0x20,
  351. BMA253_INT_EN_0_ORIENT_EN = 0x40,
  352. BMA253_INT_EN_0_FLAT_EN = 0x80
  353. } BMA253_INT_EN_0_BITS_T;
  354. /**
  355. * REG_INT_EN_1 bits
  356. */
  357. typedef enum
  358. {
  359. _BMA253_INT_EN_1_RESERVED_BITS = 0x80,
  360. BMA253_INT_EN_1_HIGH_EN_X = 0x01,
  361. BMA253_INT_EN_1_HIGH_EN_Y = 0x02,
  362. BMA253_INT_EN_1_HIGH_EN_Z = 0x04,
  363. BMA253_INT_EN_1_LOW_EN = 0x08,
  364. BMA253_INT_EN_1_DATA_EN = 0x10,
  365. BMA253_INT_EN_1_INT_FFULL_EN = 0x20, // fifo full
  366. BMA253_INT_EN_1_INT_FWM_EN = 0x40 // fifo watermark
  367. // 0x80 reserved
  368. } BMA253_INT_EN_1_BITS_T;
  369. /**
  370. * REG_INT_EN_2 bits
  371. */
  372. typedef enum
  373. {
  374. _BMA253_INT_EN_2_RESERVED_BITS = 0xf0,
  375. BMA253_INT_EN_2_SLO_NO_MOT_EN_X = 0x01,
  376. BMA253_INT_EN_2_SLO_NO_MOT_EN_Y = 0x02,
  377. BMA253_INT_EN_2_SLO_NO_MOT_EN_Z = 0x04,
  378. BMA253_INT_EN_2_SLO_NO_MOT_SEL = 0x08
  379. // 0x10-0x80 reserved
  380. } BMA253_INT_EN_2_BITS_T;
  381. /**
  382. * REG_INT_MAP_0 bits
  383. */
  384. typedef enum
  385. {
  386. BMA253_INT_MAP_0_INT1_LOW = 0x01,
  387. BMA253_INT_MAP_0_INT1_HIGH = 0x02,
  388. BMA253_INT_MAP_0_INT1_SLOPE = 0x04,
  389. BMA253_INT_MAP_0_INT1_SLO_NO_MOT = 0x08,
  390. BMA253_INT_MAP_0_INT1_D_TAP = 0x10,
  391. BMA253_INT_MAP_0_INT1_S_TAP = 0x20,
  392. BMA253_INT_MAP_0_INT1_ORIENT = 0x40,
  393. BMA253_INT_MAP_0_INT1_FLAT = 0x80
  394. } BMA253_INT_MAP_0_BITS_T;
  395. /**
  396. * REG_INT_MAP_1 bits
  397. */
  398. typedef enum
  399. {
  400. _BMA253_INT_MAP_1_INT1_RESERVED_BITS = 0x08 | 0x10,
  401. BMA253_INT_MAP_1_INT1_DATA = 0x01,
  402. BMA253_INT_MAP_1_INT1_FWM = 0x02,
  403. BMA253_INT_MAP_1_INT1_FFULL = 0x04,
  404. // 0x08-0x10 reserved
  405. BMA253_INT_MAP_1_INT2_FFULL = 0x20,
  406. BMA253_INT_MAP_1_INT2_FWM = 0x40,
  407. BMA253_INT_MAP_1_INT2_DATA = 0x80
  408. } BMA253_INT_MAP_1_BITS_T;
  409. /**
  410. * REG_INT_MAP_2 bits
  411. */
  412. typedef enum
  413. {
  414. BMA253_INT_MAP_2_INT2_LOW = 0x01,
  415. BMA253_INT_MAP_2_INT2_HIGH = 0x02,
  416. BMA253_INT_MAP_2_INT2_SLOPE = 0x04,
  417. BMA253_INT_MAP_2_INT2_SLO_NO_MOT = 0x08,
  418. BMA253_INT_MAP_2_INT2_D_TAP = 0x10,
  419. BMA253_INT_MAP_2_INT2_S_TAP = 0x20,
  420. BMA253_INT_MAP_2_INT2_ORIENT = 0x40,
  421. BMA253_INT_MAP_2_INT2_FLAT = 0x80
  422. } BMA253_INT_MAP_2_BITS_T;
  423. /**
  424. * REG_INT_SRC bits
  425. */
  426. typedef enum
  427. {
  428. _BMA253_INT_SRC_RESERVED_BITS = 0x40 | 0x80,
  429. BMA253_INT_SRC_LOW = 0x01,
  430. BMA253_INT_SRC_HIGH = 0x02,
  431. BMA253_INT_SRC_SLO_NO_MOT = 0x04,
  432. BMA253_INT_SRC_SLOPE = 0x08,
  433. BMA253_INT_SRC_TAP = 0x10,
  434. BMA253_INT_SRC_DATA = 0x20
  435. // 0x40-0x80 reserved
  436. } BMA253_INT_SRC_BITS_T;
  437. /**
  438. * REG_INT_OUT_CTRL bits
  439. */
  440. typedef enum
  441. {
  442. _BMA253_INT_OUT_CTRL_INT1_RESERVED_BITS = 0xf0,
  443. BMA253_INT_OUT_CTRL_INT1_LVL = 0x01, // level or edge
  444. BMA253_INT_OUT_CTRL_INT1_OD = 0x02, // push-pull
  445. // or open
  446. // drain
  447. BMA253_INT_OUT_CTRL_INT2_LVL = 0x04,
  448. BMA253_INT_OUT_CTRL_INT2_OD = 0x08
  449. // 0x10-0x80 reserved
  450. } BMA253_INT_OUT_CTRL_BITS_T;
  451. /**
  452. * REG_INT_RST_LATCH bits
  453. */
  454. typedef enum
  455. {
  456. _BMA253_INT_RST_LATCH_RESERVED_BITS = 0x10 | 0x20 | 0x40,
  457. BMA253_INT_RST_LATCH0 = 0x01,
  458. BMA253_INT_RST_LATCH1 = 0x02,
  459. BMA253_INT_RST_LATCH2 = 0x04,
  460. BMA253_INT_RST_LATCH3 = 0x08,
  461. _BMA253_INT_RST_LATCH_MASK = 15,
  462. _BMA253_INT_RST_LATCH_SHIFT = 0,
  463. // 0x10-0x40 reserved
  464. BMA253_INT_RST_LATCH_RESET_INT = 0x80
  465. } BMA253_INT_RST_LATCH_BITS_T;
  466. /**
  467. * RST_LATCH values
  468. */
  469. typedef enum
  470. {
  471. BMA253_RST_LATCH_NON_LATCHED = 0,
  472. BMA253_RST_LATCH_TEMPORARY_250MS = 1,
  473. BMA253_RST_LATCH_TEMPORARY_500MS = 2,
  474. BMA253_RST_LATCH_TEMPORARY_1S = 3,
  475. BMA253_RST_LATCH_TEMPORARY_2S = 4,
  476. BMA253_RST_LATCH_TEMPORARY_4S = 5,
  477. BMA253_RST_LATCH_TEMPORARY_8S = 6,
  478. BMA253_RST_LATCH_LATCHED = 7,
  479. // 8 == non latched
  480. BMA253_RST_LATCH_TEMPORARY_250US = 9,
  481. BMA253_RST_LATCH_TEMPORARY_500US = 10,
  482. BMA253_RST_LATCH_TEMPORARY_1MS = 11,
  483. BMA253_RST_LATCH_TEMPORARY_12_5MS = 12,
  484. BMA253_RST_LATCH_TEMPORARY_25MS = 13,
  485. BMA253_RST_LATCH_TEMPORARY_50MS = 14
  486. // 15 == latched
  487. } BMA253_RST_LATCH_T;
  488. /**
  489. * REG_INT_2 bits
  490. */
  491. typedef enum
  492. {
  493. BMA253_INT_2_LOW_HY0 = 0x01,
  494. BMA253_INT_2_LOW_HY1 = 0x02,
  495. _BMA253_INT_2_LOW_HY_MASK = 3,
  496. _BMA253_INT_2_LOW_HY_SHIFT = 0,
  497. BMA253_INT_2_LOW_MODE = 0x04,
  498. // 0x08-0x20 reserved
  499. BMA253_INT_2_HIGH_HY0 = 0x40,
  500. BMA253_INT_2_HIGH_HY1 = 0x80,
  501. _BMA253_INT_2_HIGH_HY_MASK = 3,
  502. _BMA253_INT_2_HIGH_HY_SHIFT = 6
  503. } BMA253_INT_2_BITS_T;
  504. /**
  505. * REG_INT_5 bits
  506. */
  507. typedef enum
  508. {
  509. BMA253_INT_5_SLOPE_DUR0 = 0x01,
  510. BMA253_INT_5_SLOPE_DUR1 = 0x02,
  511. _BMA253_INT_5_SLOPE_DUR_MASK = 3,
  512. _BMA253_INT_5_SLOPE_DUR_SHIFT = 0,
  513. BMA253_INT_5_SLO_NO_MOT_DUR0 = 0x04,
  514. BMA253_INT_5_SLO_NO_MOT_DUR1 = 0x08,
  515. BMA253_INT_5_SLO_NO_MOT_DUR2 = 0x10,
  516. BMA253_INT_5_SLO_NO_MOT_DUR3 = 0x20,
  517. BMA253_INT_5_SLO_NO_MOT_DUR4 = 0x40,
  518. BMA253_INT_5_SLO_NO_MOT_DUR5 = 0x80,
  519. _BMA253_INT_5_SLO_NO_MOT_DUR_MASK = 63,
  520. _BMA253_INT_5_SLO_NO_MOT_DUR_SHIFT = 2
  521. } BMA253_INT_5_BITS_T;
  522. /**
  523. * REG_INT_8 bits
  524. */
  525. typedef enum
  526. {
  527. BMA253_INT_8_TAP_DUR0 = 0x01,
  528. BMA253_INT_8_TAP_DUR1 = 0x02,
  529. BMA253_INT_8_TAP_DUR2 = 0x04,
  530. _BMA253_INT_8_TAP_DUR_MASK = 7,
  531. _BMA253_INT_8_TAP_DUR_SHIFT = 0,
  532. // 0x08-0x20 reserved
  533. BMA253_INT_8_TAP_SHOCK = 0x40,
  534. BMA253_INT_8_TAP_QUIET = 0x80
  535. } BMA253_INT_8_BITS_T;
  536. /**
  537. * REG_INT_9 bits
  538. */
  539. typedef enum
  540. {
  541. BMA253_INT_9_TAP_TH0 = 0x01,
  542. BMA253_INT_9_TAP_TH1 = 0x02,
  543. BMA253_INT_9_TAP_TH2 = 0x04,
  544. BMA253_INT_9_TAP_TH3 = 0x08,
  545. BMA253_INT_9_TAP_TH4 = 0x10,
  546. _BMA253_INT_5_TAP_TH_MASK = 31,
  547. _BMA253_INT_5_TAP_TH_SHIFT = 0,
  548. // 0x20 reserved
  549. BMA253_INT_9_TAP_SAMP0 = 0x40,
  550. BMA253_INT_9_TAP_SAMP1 = 0x80,
  551. BMA253_INT_9_TAP_SAMP1_MASK = 3,
  552. BMA253_INT_9_TAP_SAMP1_SHIFT = 6
  553. } BMA253_INT_9_BITS_T;
  554. /**
  555. * REG_INT_A bits
  556. */
  557. typedef enum
  558. {
  559. BMA253_INT_A_ORIENT_MODE0 = 0x01,
  560. BMA253_INT_A_ORIENT_MODE1 = 0x02,
  561. _BMA253_INT_A_ORIENT_MODE_MASK = 3,
  562. _BMA253_INT_A_ORIENT_MODE_SHIFT = 0,
  563. BMA253_INT_A_ORIENT_BLOCKING0 = 0x04,
  564. BMA253_INT_A_ORIENT_BLOCKING1 = 0x08,
  565. _BMA253_INT_A_ORIENT_BLOCKING_MASK = 3,
  566. _BMA253_INT_A_ORIENT_BLOCKING_SHIFT = 2,
  567. BMA253_INT_A_ORIENT_HYST0 = 0x10,
  568. BMA253_INT_A_ORIENT_HYST1 = 0x20,
  569. BMA253_INT_A_ORIENT_HYST2 = 0x40,
  570. _BMA253_INT_A_ORIENT_HYST_MASK = 7,
  571. _BMA253_INT_A_ORIENT_HYST_SHIFT = 4
  572. // 0x80 reserved
  573. } BMA253_INT_A_BITS_T;
  574. /**
  575. * INT_A_ORIENT_MODE values
  576. */
  577. typedef enum
  578. {
  579. BMA253_ORIENT_MODE_SYMETRICAL = 0,
  580. BMA253_ORIENT_MODE_HIGH_ASYMETRICAL = 1,
  581. BMA253_ORIENT_MODE_LOW_ASYMETRICAL = 2
  582. } BMA253_ORIENT_MODE_T;
  583. /**
  584. * INT_A_ORIENT_BLOCKING values
  585. */
  586. typedef enum
  587. {
  588. BMA253_ORIENT_BLOCKING_NONE = 0,
  589. BMA253_ORIENT_BLOCKING_THETA_ACC_1_5G = 1,
  590. BMA253_ORIENT_BLOCKING_THETA_ACC_0_2G_1_5G = 2,
  591. BMA253_ORIENT_BLOCKING_THETA_ACC_0_4G_1_5G = 3
  592. } BMA253_ORIENT_BLOCKING_T;
  593. /**
  594. * REG_INT_B bits
  595. */
  596. typedef enum
  597. {
  598. BMA253_INT_B_ORIENT_THETA0 = 0x01,
  599. BMA253_INT_B_ORIENT_THETA1 = 0x02,
  600. BMA253_INT_B_ORIENT_THETA2 = 0x04,
  601. BMA253_INT_B_ORIENT_THETA3 = 0x08,
  602. BMA253_INT_B_ORIENT_THETA4 = 0x10,
  603. BMA253_INT_B_ORIENT_THETA5 = 0x20,
  604. _BMA253_INT_B_ORIENT_THETA_MASK = 63,
  605. _BMA253_INT_B_ORIENT_THETA_SHIFT = 0,
  606. BMA253_INT_B_ORIENT_UD_EN = 0x40
  607. // 0x80 reserved
  608. } BMA253_INT_B_BITS_T;
  609. /**
  610. * REG_INT_C bits
  611. */
  612. typedef enum
  613. {
  614. BMA253_INT_B_FLAT_THETA0 = 0x01,
  615. BMA253_INT_B_FLAT_THETA1 = 0x02,
  616. BMA253_INT_B_FLAT_THETA2 = 0x04,
  617. BMA253_INT_B_FLAT_THETA3 = 0x08,
  618. BMA253_INT_B_FLAT_THETA4 = 0x10,
  619. BMA253_INT_B_FLAT_THETA5 = 0x20,
  620. _BMA253_INT_B_FLAT_THETA_MASK = 63,
  621. _BMA253_INT_B_FLAT_THETA_SHIFT = 0,
  622. // 0x40-0x80 reserved
  623. } BMA253_INT_C_BITS_T;
  624. /**
  625. * REG_INT_D bits
  626. */
  627. typedef enum
  628. {
  629. BMA253_INT_D_FLAT_HY0 = 0x01,
  630. BMA253_INT_D_FLAT_HY1 = 0x02,
  631. BMA253_INT_D_FLAT_HY2 = 0x04,
  632. _BMA253_INT_B_FLAT_HY_MASK = 7,
  633. _BMA253_INT_B_FLAT_HY_SHIFT = 0,
  634. // 0x08 reserved
  635. BMA253_INT_D_FLAT_HOLD_TIME0 = 0x10,
  636. BMA253_INT_D_FLAT_HOLD_TIME1 = 0x20,
  637. _BMA253_INT_B_FLAT_HOLD_TIME_MASK = 3,
  638. _BMA253_INT_B_FLAT_HOLD_TIME_SHIFT = 4
  639. // 0x40-0x80 reserved
  640. } BMA253_INT_D_BITS_T;
  641. /**
  642. * REG_FIFO_CONFIG_0 bits
  643. */
  644. typedef enum
  645. {
  646. _BMA253_FIFO_CONFIG_0_RESERVED_BITS = 0x80 | 0x40,
  647. BMA253_FIFO_CONFIG_0_WATER_MARK0 = 0x01,
  648. BMA253_FIFO_CONFIG_0_WATER_MARK1 = 0x02,
  649. BMA253_FIFO_CONFIG_0_WATER_MARK2 = 0x04,
  650. BMA253_FIFO_CONFIG_0_WATER_MARK3 = 0x08,
  651. BMA253_FIFO_CONFIG_0_WATER_MARK4 = 0x10,
  652. BMA253_FIFO_CONFIG_0_WATER_MARK5 = 0x20,
  653. _BMA253_FIFO_CONFIG_0_WATER_MARK_MASK = 63,
  654. _BMA253_FIFO_CONFIG_0_WATER_MARK_SHIFT = 0
  655. } BMA253_FIFO_CONFIG_0_BITS_T;
  656. /**
  657. * REG_PMU_SELFTTEST bits
  658. */
  659. typedef enum
  660. {
  661. BMA253_PMU_SELFTTEST_AXIS0 = 0x01,
  662. BMA253_PMU_SELFTTEST_AXIS1 = 0x02,
  663. _BMA253_PMU_SELFTTEST_AXIS_MASK = 3,
  664. _BMA253_PMU_SELFTTEST_AXIS_SHIFT = 0,
  665. BMA253_PMU_SELFTTEST_SIGN = 0x04,
  666. // 0x08 reserved
  667. BMA253_PMU_SELFTTEST_AMP = 0x10,
  668. // 0x20-0x80 reserved
  669. } BMA253_PMU_SELFTTEST_BITS_T;
  670. /**
  671. * PMU_SELFTTEST_AXIS values
  672. */
  673. typedef enum
  674. {
  675. BMA253_SELFTTEST_AXIS_NONE = 0,
  676. BMA253_SELFTTEST_AXIS_X = 1,
  677. BMA253_SELFTTEST_AXIS_Y = 2,
  678. BMA253_SELFTTEST_AXIS_Z = 3,
  679. } BMA253_SELFTTEST_AXIS_T;
  680. /**
  681. * REG_TRIM_NVM_CTRL bits
  682. */
  683. typedef enum
  684. {
  685. BMA253_TRIM_NVM_CTRL_NVM_PROG_MODE = 0x01,
  686. BMA253_TRIM_NVM_CTRL_NVM_PROG_TRIG = 0x02,
  687. BMA253_TRIM_NVM_CTRL_NVM_PROG_RDY = 0x04,
  688. BMA253_TRIM_NVM_CTRL_NVM_PROG_LOAD = 0x08,
  689. BMA253_TRIM_NVM_CTRL_NVM_REMAIN0 = 0x10,
  690. BMA253_TRIM_NVM_CTRL_NVM_REMAIN1 = 0x20,
  691. BMA253_TRIM_NVM_CTRL_NVM_REMAIN2 = 0x40,
  692. BMA253_TRIM_NVM_CTRL_NVM_REMAIN3 = 0x80,
  693. _BMA253_TRIM_NVM_CTRL_NVM_REMAIN_MASK = 15,
  694. _BMA253_TRIM_NVM_CTRL_NVM_REMAIN_SHIFT = 4
  695. } BMA253_TRIM_NVM_CTRL_BITS_T;
  696. /**
  697. * REG_SPI3_WDT bits
  698. */
  699. typedef enum
  700. {
  701. _BMA253_SPI3_WDT_RESERVED_BITS = 0xf0 | 0x08,
  702. BMA253_SPI3_WDT_SPI3 = 0x01, // 3-wire SPI
  703. // - NOT
  704. // SUPPORTED
  705. BMA253_SPI3_WDT_I2C_WDT_SEL = 0x02,
  706. BMA253_SPI3_WDT_I2C_WDT_EN = 0x04
  707. // 0x08-0x80 reserved
  708. } BMA253_SPI3_WDT_BITS_T;
  709. /**
  710. * REG_OFC_CTRL bits
  711. */
  712. typedef enum
  713. {
  714. BMA253_OFC_CTRL_HP_X_EN = 0x01,
  715. BMA253_OFC_CTRL_HP_Y_EN = 0x02,
  716. BMA253_OFC_CTRL_HP_Z_EN = 0x04,
  717. // 0x08 reserved
  718. BMA253_OFC_CTRL_CAL_RDY = 0x10,
  719. BMA253_OFC_CTRL_CAL_TRIGGER0 = 0x20,
  720. BMA253_OFC_CTRL_CAL_TRIGGER1 = 0x40,
  721. _BMA253_OFC_CTRL_CAL_TRIGGER_MASK = 3,
  722. _BMA253_OFC_CTRL_CAL_TRIGGER_SHIFT = 5,
  723. BMA253_OFC_CTRL_OFFSET_RESET = 0x80
  724. } BMA253_OFC_CTRL_BITS_T;
  725. /**
  726. * OFC_CTRL_CAL_TRIGGER values
  727. */
  728. typedef enum
  729. {
  730. BMA253_CAL_TRIGGER_NONE = 0,
  731. BMA253_CAL_TRIGGER_X = 1,
  732. BMA253_CAL_TRIGGER_Y = 2,
  733. BMA253_CAL_TRIGGER_Z = 3
  734. } BMA253_CAL_TRIGGER_T;
  735. /**
  736. * REG_OFC_SETTING bits
  737. */
  738. typedef enum
  739. {
  740. BMA253_OFC_SETTING_CUT_OFF = 0x01,
  741. BMA253_OFC_SETTING_OFFSET_TARGET_X0 = 0x02,
  742. BMA253_OFC_SETTING_OFFSET_TARGET_X1 = 0x04,
  743. _BMA253_OFC_SETTING_OFFSET_TARGET_X_MASK = 3,
  744. _BMA253_OFC_SETTING_OFFSET_TARGET_X_SHIFT = 1,
  745. BMA253_OFC_SETTING_OFFSET_TARGET_Y0 = 0x08,
  746. BMA253_OFC_SETTING_OFFSET_TARGET_Y1 = 0x10,
  747. _BMA253_OFC_SETTING_OFFSET_TARGET_Y_MASK = 3,
  748. _BMA253_OFC_SETTING_OFFSET_TARGET_Y_SHIFT = 3,
  749. BMA253_OFC_SETTING_OFFSET_TARGET_Z0 = 0x20,
  750. BMA253_OFC_SETTING_OFFSET_TARGET_Z1 = 0x40,
  751. _BMA253_OFC_SETTING_OFFSET_TARGET_Z_MASK = 3,
  752. _BMA253_OFC_SETTING_OFFSET_TARGET_Z_SHIFT = 5
  753. // 0x80 reserved
  754. } BMA253_OFC_SETTING_BITS_T;
  755. /**
  756. * OFC_SETTING_OFFSET_TARGET (for X, Y and Z axis) values
  757. */
  758. typedef enum
  759. {
  760. BMA253_OFFSET_TARGET_0G = 0,
  761. BMA253_OFFSET_TARGET_PLUS_1G = 1,
  762. BMA253_OFFSET_TARGET_MINUS_1G = 2,
  763. // 3 == 0G
  764. } BMA253_OFFSET_TARGET_T;
  765. /**
  766. * REG_FIFO_CONFIG_1 bits
  767. */
  768. typedef enum
  769. {
  770. BMA253_FIFO_CONFIG_1_FIFO_DATA_SEL0 = 0x01,
  771. BMA253_FIFO_CONFIG_1_FIFO_DATA_SEL1 = 0x02,
  772. _BMA253_FIFO_CONFIG_1_FIFO_DATA_SEL = 3,
  773. _BMA253_FIFO_CONFIG_1_FIFO_DATA_SHIFT = 0,
  774. // 0x04-0x20 reserved
  775. BMA253_FIFO_CONFIG_1_FIFO_MODE0 = 0x40,
  776. BMA253_FIFO_CONFIG_1_FIFO_MODE1 = 0x80,
  777. _BMA253_FIFO_CONFIG_1_FIFO_MODE_MASK = 3,
  778. _BMA253_FIFO_CONFIG_1_FIFO_MODE_SHIFT = 6
  779. } BMA253_FIFO_CONFIG_1_BITS_T;
  780. /**
  781. * FIFO_DATA_SEL values
  782. */
  783. typedef enum
  784. {
  785. BMA253_FIFO_DATA_SEL_XYZ = 0,
  786. BMA253_FIFO_DATA_SEL_X = 1,
  787. BMA253_FIFO_DATA_SEL_Y = 2,
  788. BMA253_FIFO_DATA_SEL_Z = 3
  789. } BMA253_FIFO_DATA_SEL_T;
  790. /**
  791. * FIFO_MODE values
  792. */
  793. typedef enum
  794. {
  795. BMA253_FIFO_MODE_BYPASS = 0,
  796. BMA253_FIFO_MODE_FIFO = 1,
  797. BMA253_FIFO_MODE_STREAM = 2
  798. // 3 == reserved (execute self-destruct :)
  799. } BMA253_FIFO_MODE_T;
  800. // interrupt selection for installISR() and uninstallISR()
  801. typedef enum
  802. {
  803. BMA253_INTERRUPT_INT1,
  804. BMA253_INTERRUPT_INT2
  805. } BMA253_INTERRUPT_PINS_T;
  806. // Different variants of this chip support different resolutions.
  807. // The 0xf9 variant supports 10b, while the 0xfa variant (bmx055)
  808. // supports 12 bits.
  809. typedef enum
  810. {
  811. BMA253_RESOLUTION_10BITS,
  812. BMA253_RESOLUTION_12BITS
  813. } BMA253_RESOLUTION_T;
  814. #endif