STM32F410RB_PLLCtrl_Test.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000001c8 08000000 08000000 00010000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 00002e3c 080001c8 080001c8 000101c8 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 0000008c 08003004 08003004 00013004 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 08003090 08003090 0002009c 2**0 CONTENTS 4 .ARM 00000008 08003090 08003090 00013090 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .preinit_array 00000000 08003098 08003098 0002009c 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 08003098 08003098 00013098 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .fini_array 00000004 0800309c 0800309c 0001309c 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .data 0000009c 20000000 080030a0 00020000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 0000008c 2000009c 0800313c 0002009c 2**2 ALLOC 10 ._user_heap_stack 00000600 20000128 0800313c 00020128 2**0 ALLOC 11 .ARM.attributes 00000030 00000000 00000000 0002009c 2**0 CONTENTS, READONLY 12 .debug_info 00009ca6 00000000 00000000 000200cc 2**0 CONTENTS, READONLY, DEBUGGING 13 .debug_abbrev 00001b8a 00000000 00000000 00029d72 2**0 CONTENTS, READONLY, DEBUGGING 14 .debug_aranges 00000788 00000000 00000000 0002b900 2**3 CONTENTS, READONLY, DEBUGGING 15 .debug_ranges 000006b0 00000000 00000000 0002c088 2**3 CONTENTS, READONLY, DEBUGGING 16 .debug_macro 00014ecf 00000000 00000000 0002c738 2**0 CONTENTS, READONLY, DEBUGGING 17 .debug_line 00007477 00000000 00000000 00041607 2**0 CONTENTS, READONLY, DEBUGGING 18 .debug_str 00077d4d 00000000 00000000 00048a7e 2**0 CONTENTS, READONLY, DEBUGGING 19 .comment 0000007b 00000000 00000000 000c07cb 2**0 CONTENTS, READONLY 20 .debug_frame 0000235c 00000000 00000000 000c0848 2**2 CONTENTS, READONLY, DEBUGGING Disassembly of section .text: 080001c8 <__do_global_dtors_aux>: 80001c8: b510 push {r4, lr} 80001ca: 4c05 ldr r4, [pc, #20] ; (80001e0 <__do_global_dtors_aux+0x18>) 80001cc: 7823 ldrb r3, [r4, #0] 80001ce: b933 cbnz r3, 80001de <__do_global_dtors_aux+0x16> 80001d0: 4b04 ldr r3, [pc, #16] ; (80001e4 <__do_global_dtors_aux+0x1c>) 80001d2: b113 cbz r3, 80001da <__do_global_dtors_aux+0x12> 80001d4: 4804 ldr r0, [pc, #16] ; (80001e8 <__do_global_dtors_aux+0x20>) 80001d6: f3af 8000 nop.w 80001da: 2301 movs r3, #1 80001dc: 7023 strb r3, [r4, #0] 80001de: bd10 pop {r4, pc} 80001e0: 2000009c .word 0x2000009c 80001e4: 00000000 .word 0x00000000 80001e8: 08002fec .word 0x08002fec 080001ec : 80001ec: b508 push {r3, lr} 80001ee: 4b03 ldr r3, [pc, #12] ; (80001fc ) 80001f0: b11b cbz r3, 80001fa 80001f2: 4903 ldr r1, [pc, #12] ; (8000200 ) 80001f4: 4803 ldr r0, [pc, #12] ; (8000204 ) 80001f6: f3af 8000 nop.w 80001fa: bd08 pop {r3, pc} 80001fc: 00000000 .word 0x00000000 8000200: 200000a0 .word 0x200000a0 8000204: 08002fec .word 0x08002fec 08000208 <__aeabi_uldivmod>: 8000208: b953 cbnz r3, 8000220 <__aeabi_uldivmod+0x18> 800020a: b94a cbnz r2, 8000220 <__aeabi_uldivmod+0x18> 800020c: 2900 cmp r1, #0 800020e: bf08 it eq 8000210: 2800 cmpeq r0, #0 8000212: bf1c itt ne 8000214: f04f 31ff movne.w r1, #4294967295 8000218: f04f 30ff movne.w r0, #4294967295 800021c: f000 b972 b.w 8000504 <__aeabi_idiv0> 8000220: f1ad 0c08 sub.w ip, sp, #8 8000224: e96d ce04 strd ip, lr, [sp, #-16]! 8000228: f000 f806 bl 8000238 <__udivmoddi4> 800022c: f8dd e004 ldr.w lr, [sp, #4] 8000230: e9dd 2302 ldrd r2, r3, [sp, #8] 8000234: b004 add sp, #16 8000236: 4770 bx lr 08000238 <__udivmoddi4>: 8000238: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 800023c: 9e08 ldr r6, [sp, #32] 800023e: 4604 mov r4, r0 8000240: 4688 mov r8, r1 8000242: 2b00 cmp r3, #0 8000244: d14b bne.n 80002de <__udivmoddi4+0xa6> 8000246: 428a cmp r2, r1 8000248: 4615 mov r5, r2 800024a: d967 bls.n 800031c <__udivmoddi4+0xe4> 800024c: fab2 f282 clz r2, r2 8000250: b14a cbz r2, 8000266 <__udivmoddi4+0x2e> 8000252: f1c2 0720 rsb r7, r2, #32 8000256: fa01 f302 lsl.w r3, r1, r2 800025a: fa20 f707 lsr.w r7, r0, r7 800025e: 4095 lsls r5, r2 8000260: ea47 0803 orr.w r8, r7, r3 8000264: 4094 lsls r4, r2 8000266: ea4f 4e15 mov.w lr, r5, lsr #16 800026a: 0c23 lsrs r3, r4, #16 800026c: fbb8 f7fe udiv r7, r8, lr 8000270: fa1f fc85 uxth.w ip, r5 8000274: fb0e 8817 mls r8, lr, r7, r8 8000278: ea43 4308 orr.w r3, r3, r8, lsl #16 800027c: fb07 f10c mul.w r1, r7, ip 8000280: 4299 cmp r1, r3 8000282: d909 bls.n 8000298 <__udivmoddi4+0x60> 8000284: 18eb adds r3, r5, r3 8000286: f107 30ff add.w r0, r7, #4294967295 800028a: f080 811b bcs.w 80004c4 <__udivmoddi4+0x28c> 800028e: 4299 cmp r1, r3 8000290: f240 8118 bls.w 80004c4 <__udivmoddi4+0x28c> 8000294: 3f02 subs r7, #2 8000296: 442b add r3, r5 8000298: 1a5b subs r3, r3, r1 800029a: b2a4 uxth r4, r4 800029c: fbb3 f0fe udiv r0, r3, lr 80002a0: fb0e 3310 mls r3, lr, r0, r3 80002a4: ea44 4403 orr.w r4, r4, r3, lsl #16 80002a8: fb00 fc0c mul.w ip, r0, ip 80002ac: 45a4 cmp ip, r4 80002ae: d909 bls.n 80002c4 <__udivmoddi4+0x8c> 80002b0: 192c adds r4, r5, r4 80002b2: f100 33ff add.w r3, r0, #4294967295 80002b6: f080 8107 bcs.w 80004c8 <__udivmoddi4+0x290> 80002ba: 45a4 cmp ip, r4 80002bc: f240 8104 bls.w 80004c8 <__udivmoddi4+0x290> 80002c0: 3802 subs r0, #2 80002c2: 442c add r4, r5 80002c4: ea40 4007 orr.w r0, r0, r7, lsl #16 80002c8: eba4 040c sub.w r4, r4, ip 80002cc: 2700 movs r7, #0 80002ce: b11e cbz r6, 80002d8 <__udivmoddi4+0xa0> 80002d0: 40d4 lsrs r4, r2 80002d2: 2300 movs r3, #0 80002d4: e9c6 4300 strd r4, r3, [r6] 80002d8: 4639 mov r1, r7 80002da: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80002de: 428b cmp r3, r1 80002e0: d909 bls.n 80002f6 <__udivmoddi4+0xbe> 80002e2: 2e00 cmp r6, #0 80002e4: f000 80eb beq.w 80004be <__udivmoddi4+0x286> 80002e8: 2700 movs r7, #0 80002ea: e9c6 0100 strd r0, r1, [r6] 80002ee: 4638 mov r0, r7 80002f0: 4639 mov r1, r7 80002f2: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80002f6: fab3 f783 clz r7, r3 80002fa: 2f00 cmp r7, #0 80002fc: d147 bne.n 800038e <__udivmoddi4+0x156> 80002fe: 428b cmp r3, r1 8000300: d302 bcc.n 8000308 <__udivmoddi4+0xd0> 8000302: 4282 cmp r2, r0 8000304: f200 80fa bhi.w 80004fc <__udivmoddi4+0x2c4> 8000308: 1a84 subs r4, r0, r2 800030a: eb61 0303 sbc.w r3, r1, r3 800030e: 2001 movs r0, #1 8000310: 4698 mov r8, r3 8000312: 2e00 cmp r6, #0 8000314: d0e0 beq.n 80002d8 <__udivmoddi4+0xa0> 8000316: e9c6 4800 strd r4, r8, [r6] 800031a: e7dd b.n 80002d8 <__udivmoddi4+0xa0> 800031c: b902 cbnz r2, 8000320 <__udivmoddi4+0xe8> 800031e: deff udf #255 ; 0xff 8000320: fab2 f282 clz r2, r2 8000324: 2a00 cmp r2, #0 8000326: f040 808f bne.w 8000448 <__udivmoddi4+0x210> 800032a: 1b49 subs r1, r1, r5 800032c: ea4f 4e15 mov.w lr, r5, lsr #16 8000330: fa1f f885 uxth.w r8, r5 8000334: 2701 movs r7, #1 8000336: fbb1 fcfe udiv ip, r1, lr 800033a: 0c23 lsrs r3, r4, #16 800033c: fb0e 111c mls r1, lr, ip, r1 8000340: ea43 4301 orr.w r3, r3, r1, lsl #16 8000344: fb08 f10c mul.w r1, r8, ip 8000348: 4299 cmp r1, r3 800034a: d907 bls.n 800035c <__udivmoddi4+0x124> 800034c: 18eb adds r3, r5, r3 800034e: f10c 30ff add.w r0, ip, #4294967295 8000352: d202 bcs.n 800035a <__udivmoddi4+0x122> 8000354: 4299 cmp r1, r3 8000356: f200 80cd bhi.w 80004f4 <__udivmoddi4+0x2bc> 800035a: 4684 mov ip, r0 800035c: 1a59 subs r1, r3, r1 800035e: b2a3 uxth r3, r4 8000360: fbb1 f0fe udiv r0, r1, lr 8000364: fb0e 1410 mls r4, lr, r0, r1 8000368: ea43 4404 orr.w r4, r3, r4, lsl #16 800036c: fb08 f800 mul.w r8, r8, r0 8000370: 45a0 cmp r8, r4 8000372: d907 bls.n 8000384 <__udivmoddi4+0x14c> 8000374: 192c adds r4, r5, r4 8000376: f100 33ff add.w r3, r0, #4294967295 800037a: d202 bcs.n 8000382 <__udivmoddi4+0x14a> 800037c: 45a0 cmp r8, r4 800037e: f200 80b6 bhi.w 80004ee <__udivmoddi4+0x2b6> 8000382: 4618 mov r0, r3 8000384: eba4 0408 sub.w r4, r4, r8 8000388: ea40 400c orr.w r0, r0, ip, lsl #16 800038c: e79f b.n 80002ce <__udivmoddi4+0x96> 800038e: f1c7 0c20 rsb ip, r7, #32 8000392: 40bb lsls r3, r7 8000394: fa22 fe0c lsr.w lr, r2, ip 8000398: ea4e 0e03 orr.w lr, lr, r3 800039c: fa01 f407 lsl.w r4, r1, r7 80003a0: fa20 f50c lsr.w r5, r0, ip 80003a4: fa21 f30c lsr.w r3, r1, ip 80003a8: ea4f 481e mov.w r8, lr, lsr #16 80003ac: 4325 orrs r5, r4 80003ae: fbb3 f9f8 udiv r9, r3, r8 80003b2: 0c2c lsrs r4, r5, #16 80003b4: fb08 3319 mls r3, r8, r9, r3 80003b8: fa1f fa8e uxth.w sl, lr 80003bc: ea44 4303 orr.w r3, r4, r3, lsl #16 80003c0: fb09 f40a mul.w r4, r9, sl 80003c4: 429c cmp r4, r3 80003c6: fa02 f207 lsl.w r2, r2, r7 80003ca: fa00 f107 lsl.w r1, r0, r7 80003ce: d90b bls.n 80003e8 <__udivmoddi4+0x1b0> 80003d0: eb1e 0303 adds.w r3, lr, r3 80003d4: f109 30ff add.w r0, r9, #4294967295 80003d8: f080 8087 bcs.w 80004ea <__udivmoddi4+0x2b2> 80003dc: 429c cmp r4, r3 80003de: f240 8084 bls.w 80004ea <__udivmoddi4+0x2b2> 80003e2: f1a9 0902 sub.w r9, r9, #2 80003e6: 4473 add r3, lr 80003e8: 1b1b subs r3, r3, r4 80003ea: b2ad uxth r5, r5 80003ec: fbb3 f0f8 udiv r0, r3, r8 80003f0: fb08 3310 mls r3, r8, r0, r3 80003f4: ea45 4403 orr.w r4, r5, r3, lsl #16 80003f8: fb00 fa0a mul.w sl, r0, sl 80003fc: 45a2 cmp sl, r4 80003fe: d908 bls.n 8000412 <__udivmoddi4+0x1da> 8000400: eb1e 0404 adds.w r4, lr, r4 8000404: f100 33ff add.w r3, r0, #4294967295 8000408: d26b bcs.n 80004e2 <__udivmoddi4+0x2aa> 800040a: 45a2 cmp sl, r4 800040c: d969 bls.n 80004e2 <__udivmoddi4+0x2aa> 800040e: 3802 subs r0, #2 8000410: 4474 add r4, lr 8000412: ea40 4009 orr.w r0, r0, r9, lsl #16 8000416: fba0 8902 umull r8, r9, r0, r2 800041a: eba4 040a sub.w r4, r4, sl 800041e: 454c cmp r4, r9 8000420: 46c2 mov sl, r8 8000422: 464b mov r3, r9 8000424: d354 bcc.n 80004d0 <__udivmoddi4+0x298> 8000426: d051 beq.n 80004cc <__udivmoddi4+0x294> 8000428: 2e00 cmp r6, #0 800042a: d069 beq.n 8000500 <__udivmoddi4+0x2c8> 800042c: ebb1 050a subs.w r5, r1, sl 8000430: eb64 0403 sbc.w r4, r4, r3 8000434: fa04 fc0c lsl.w ip, r4, ip 8000438: 40fd lsrs r5, r7 800043a: 40fc lsrs r4, r7 800043c: ea4c 0505 orr.w r5, ip, r5 8000440: e9c6 5400 strd r5, r4, [r6] 8000444: 2700 movs r7, #0 8000446: e747 b.n 80002d8 <__udivmoddi4+0xa0> 8000448: f1c2 0320 rsb r3, r2, #32 800044c: fa20 f703 lsr.w r7, r0, r3 8000450: 4095 lsls r5, r2 8000452: fa01 f002 lsl.w r0, r1, r2 8000456: fa21 f303 lsr.w r3, r1, r3 800045a: ea4f 4e15 mov.w lr, r5, lsr #16 800045e: 4338 orrs r0, r7 8000460: 0c01 lsrs r1, r0, #16 8000462: fbb3 f7fe udiv r7, r3, lr 8000466: fa1f f885 uxth.w r8, r5 800046a: fb0e 3317 mls r3, lr, r7, r3 800046e: ea41 4103 orr.w r1, r1, r3, lsl #16 8000472: fb07 f308 mul.w r3, r7, r8 8000476: 428b cmp r3, r1 8000478: fa04 f402 lsl.w r4, r4, r2 800047c: d907 bls.n 800048e <__udivmoddi4+0x256> 800047e: 1869 adds r1, r5, r1 8000480: f107 3cff add.w ip, r7, #4294967295 8000484: d22f bcs.n 80004e6 <__udivmoddi4+0x2ae> 8000486: 428b cmp r3, r1 8000488: d92d bls.n 80004e6 <__udivmoddi4+0x2ae> 800048a: 3f02 subs r7, #2 800048c: 4429 add r1, r5 800048e: 1acb subs r3, r1, r3 8000490: b281 uxth r1, r0 8000492: fbb3 f0fe udiv r0, r3, lr 8000496: fb0e 3310 mls r3, lr, r0, r3 800049a: ea41 4103 orr.w r1, r1, r3, lsl #16 800049e: fb00 f308 mul.w r3, r0, r8 80004a2: 428b cmp r3, r1 80004a4: d907 bls.n 80004b6 <__udivmoddi4+0x27e> 80004a6: 1869 adds r1, r5, r1 80004a8: f100 3cff add.w ip, r0, #4294967295 80004ac: d217 bcs.n 80004de <__udivmoddi4+0x2a6> 80004ae: 428b cmp r3, r1 80004b0: d915 bls.n 80004de <__udivmoddi4+0x2a6> 80004b2: 3802 subs r0, #2 80004b4: 4429 add r1, r5 80004b6: 1ac9 subs r1, r1, r3 80004b8: ea40 4707 orr.w r7, r0, r7, lsl #16 80004bc: e73b b.n 8000336 <__udivmoddi4+0xfe> 80004be: 4637 mov r7, r6 80004c0: 4630 mov r0, r6 80004c2: e709 b.n 80002d8 <__udivmoddi4+0xa0> 80004c4: 4607 mov r7, r0 80004c6: e6e7 b.n 8000298 <__udivmoddi4+0x60> 80004c8: 4618 mov r0, r3 80004ca: e6fb b.n 80002c4 <__udivmoddi4+0x8c> 80004cc: 4541 cmp r1, r8 80004ce: d2ab bcs.n 8000428 <__udivmoddi4+0x1f0> 80004d0: ebb8 0a02 subs.w sl, r8, r2 80004d4: eb69 020e sbc.w r2, r9, lr 80004d8: 3801 subs r0, #1 80004da: 4613 mov r3, r2 80004dc: e7a4 b.n 8000428 <__udivmoddi4+0x1f0> 80004de: 4660 mov r0, ip 80004e0: e7e9 b.n 80004b6 <__udivmoddi4+0x27e> 80004e2: 4618 mov r0, r3 80004e4: e795 b.n 8000412 <__udivmoddi4+0x1da> 80004e6: 4667 mov r7, ip 80004e8: e7d1 b.n 800048e <__udivmoddi4+0x256> 80004ea: 4681 mov r9, r0 80004ec: e77c b.n 80003e8 <__udivmoddi4+0x1b0> 80004ee: 3802 subs r0, #2 80004f0: 442c add r4, r5 80004f2: e747 b.n 8000384 <__udivmoddi4+0x14c> 80004f4: f1ac 0c02 sub.w ip, ip, #2 80004f8: 442b add r3, r5 80004fa: e72f b.n 800035c <__udivmoddi4+0x124> 80004fc: 4638 mov r0, r7 80004fe: e708 b.n 8000312 <__udivmoddi4+0xda> 8000500: 4637 mov r7, r6 8000502: e6e9 b.n 80002d8 <__udivmoddi4+0xa0> 08000504 <__aeabi_idiv0>: 8000504: 4770 bx lr 8000506: bf00 nop 08000508 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8000508: b580 push {r7, lr} 800050a: af00 add r7, sp, #0 /* Configure Flash prefetch, Instruction cache, Data cache */ #if (INSTRUCTION_CACHE_ENABLE != 0U) __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); 800050c: 4b0e ldr r3, [pc, #56] ; (8000548 ) 800050e: 681b ldr r3, [r3, #0] 8000510: 4a0d ldr r2, [pc, #52] ; (8000548 ) 8000512: f443 7300 orr.w r3, r3, #512 ; 0x200 8000516: 6013 str r3, [r2, #0] #endif /* INSTRUCTION_CACHE_ENABLE */ #if (DATA_CACHE_ENABLE != 0U) __HAL_FLASH_DATA_CACHE_ENABLE(); 8000518: 4b0b ldr r3, [pc, #44] ; (8000548 ) 800051a: 681b ldr r3, [r3, #0] 800051c: 4a0a ldr r2, [pc, #40] ; (8000548 ) 800051e: f443 6380 orr.w r3, r3, #1024 ; 0x400 8000522: 6013 str r3, [r2, #0] #endif /* DATA_CACHE_ENABLE */ #if (PREFETCH_ENABLE != 0U) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 8000524: 4b08 ldr r3, [pc, #32] ; (8000548 ) 8000526: 681b ldr r3, [r3, #0] 8000528: 4a07 ldr r2, [pc, #28] ; (8000548 ) 800052a: f443 7380 orr.w r3, r3, #256 ; 0x100 800052e: 6013 str r3, [r2, #0] #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8000530: 2003 movs r0, #3 8000532: f000 f94d bl 80007d0 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 8000536: 2000 movs r0, #0 8000538: f000 f808 bl 800054c /* Init the low level hardware */ HAL_MspInit(); 800053c: f001 fe7a bl 8002234 /* Return function status */ return HAL_OK; 8000540: 2300 movs r3, #0 } 8000542: 4618 mov r0, r3 8000544: bd80 pop {r7, pc} 8000546: bf00 nop 8000548: 40023c00 .word 0x40023c00 0800054c : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 800054c: b580 push {r7, lr} 800054e: b082 sub sp, #8 8000550: af00 add r7, sp, #0 8000552: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 8000554: 4b12 ldr r3, [pc, #72] ; (80005a0 ) 8000556: 681a ldr r2, [r3, #0] 8000558: 4b12 ldr r3, [pc, #72] ; (80005a4 ) 800055a: 781b ldrb r3, [r3, #0] 800055c: 4619 mov r1, r3 800055e: f44f 737a mov.w r3, #1000 ; 0x3e8 8000562: fbb3 f3f1 udiv r3, r3, r1 8000566: fbb2 f3f3 udiv r3, r2, r3 800056a: 4618 mov r0, r3 800056c: f000 f965 bl 800083a 8000570: 4603 mov r3, r0 8000572: 2b00 cmp r3, #0 8000574: d001 beq.n 800057a { return HAL_ERROR; 8000576: 2301 movs r3, #1 8000578: e00e b.n 8000598 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 800057a: 687b ldr r3, [r7, #4] 800057c: 2b0f cmp r3, #15 800057e: d80a bhi.n 8000596 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 8000580: 2200 movs r2, #0 8000582: 6879 ldr r1, [r7, #4] 8000584: f04f 30ff mov.w r0, #4294967295 8000588: f000 f92d bl 80007e6 uwTickPrio = TickPriority; 800058c: 4a06 ldr r2, [pc, #24] ; (80005a8 ) 800058e: 687b ldr r3, [r7, #4] 8000590: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 8000592: 2300 movs r3, #0 8000594: e000 b.n 8000598 return HAL_ERROR; 8000596: 2301 movs r3, #1 } 8000598: 4618 mov r0, r3 800059a: 3708 adds r7, #8 800059c: 46bd mov sp, r7 800059e: bd80 pop {r7, pc} 80005a0: 20000034 .word 0x20000034 80005a4: 20000004 .word 0x20000004 80005a8: 20000000 .word 0x20000000 080005ac : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 80005ac: b480 push {r7} 80005ae: af00 add r7, sp, #0 uwTick += uwTickFreq; 80005b0: 4b06 ldr r3, [pc, #24] ; (80005cc ) 80005b2: 781b ldrb r3, [r3, #0] 80005b4: 461a mov r2, r3 80005b6: 4b06 ldr r3, [pc, #24] ; (80005d0 ) 80005b8: 681b ldr r3, [r3, #0] 80005ba: 4413 add r3, r2 80005bc: 4a04 ldr r2, [pc, #16] ; (80005d0 ) 80005be: 6013 str r3, [r2, #0] } 80005c0: bf00 nop 80005c2: 46bd mov sp, r7 80005c4: f85d 7b04 ldr.w r7, [sp], #4 80005c8: 4770 bx lr 80005ca: bf00 nop 80005cc: 20000004 .word 0x20000004 80005d0: 200000e0 .word 0x200000e0 080005d4 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 80005d4: b480 push {r7} 80005d6: af00 add r7, sp, #0 return uwTick; 80005d8: 4b03 ldr r3, [pc, #12] ; (80005e8 ) 80005da: 681b ldr r3, [r3, #0] } 80005dc: 4618 mov r0, r3 80005de: 46bd mov sp, r7 80005e0: f85d 7b04 ldr.w r7, [sp], #4 80005e4: 4770 bx lr 80005e6: bf00 nop 80005e8: 200000e0 .word 0x200000e0 080005ec : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 80005ec: b580 push {r7, lr} 80005ee: b084 sub sp, #16 80005f0: af00 add r7, sp, #0 80005f2: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 80005f4: f7ff ffee bl 80005d4 80005f8: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 80005fa: 687b ldr r3, [r7, #4] 80005fc: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 80005fe: 68fb ldr r3, [r7, #12] 8000600: f1b3 3fff cmp.w r3, #4294967295 8000604: d005 beq.n 8000612 { wait += (uint32_t)(uwTickFreq); 8000606: 4b09 ldr r3, [pc, #36] ; (800062c ) 8000608: 781b ldrb r3, [r3, #0] 800060a: 461a mov r2, r3 800060c: 68fb ldr r3, [r7, #12] 800060e: 4413 add r3, r2 8000610: 60fb str r3, [r7, #12] } while((HAL_GetTick() - tickstart) < wait) 8000612: bf00 nop 8000614: f7ff ffde bl 80005d4 8000618: 4602 mov r2, r0 800061a: 68bb ldr r3, [r7, #8] 800061c: 1ad3 subs r3, r2, r3 800061e: 68fa ldr r2, [r7, #12] 8000620: 429a cmp r2, r3 8000622: d8f7 bhi.n 8000614 { } } 8000624: bf00 nop 8000626: 3710 adds r7, #16 8000628: 46bd mov sp, r7 800062a: bd80 pop {r7, pc} 800062c: 20000004 .word 0x20000004 08000630 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8000630: b480 push {r7} 8000632: b085 sub sp, #20 8000634: af00 add r7, sp, #0 8000636: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8000638: 687b ldr r3, [r7, #4] 800063a: f003 0307 and.w r3, r3, #7 800063e: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 8000640: 4b0c ldr r3, [pc, #48] ; (8000674 <__NVIC_SetPriorityGrouping+0x44>) 8000642: 68db ldr r3, [r3, #12] 8000644: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8000646: 68ba ldr r2, [r7, #8] 8000648: f64f 03ff movw r3, #63743 ; 0xf8ff 800064c: 4013 ands r3, r2 800064e: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8000650: 68fb ldr r3, [r7, #12] 8000652: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8000654: 68bb ldr r3, [r7, #8] 8000656: 4313 orrs r3, r2 reg_value = (reg_value | 8000658: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 800065c: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8000660: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 8000662: 4a04 ldr r2, [pc, #16] ; (8000674 <__NVIC_SetPriorityGrouping+0x44>) 8000664: 68bb ldr r3, [r7, #8] 8000666: 60d3 str r3, [r2, #12] } 8000668: bf00 nop 800066a: 3714 adds r7, #20 800066c: 46bd mov sp, r7 800066e: f85d 7b04 ldr.w r7, [sp], #4 8000672: 4770 bx lr 8000674: e000ed00 .word 0xe000ed00 08000678 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 8000678: b480 push {r7} 800067a: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 800067c: 4b04 ldr r3, [pc, #16] ; (8000690 <__NVIC_GetPriorityGrouping+0x18>) 800067e: 68db ldr r3, [r3, #12] 8000680: 0a1b lsrs r3, r3, #8 8000682: f003 0307 and.w r3, r3, #7 } 8000686: 4618 mov r0, r3 8000688: 46bd mov sp, r7 800068a: f85d 7b04 ldr.w r7, [sp], #4 800068e: 4770 bx lr 8000690: e000ed00 .word 0xe000ed00 08000694 <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 8000694: b480 push {r7} 8000696: b083 sub sp, #12 8000698: af00 add r7, sp, #0 800069a: 4603 mov r3, r0 800069c: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 800069e: f997 3007 ldrsb.w r3, [r7, #7] 80006a2: 2b00 cmp r3, #0 80006a4: db0b blt.n 80006be <__NVIC_EnableIRQ+0x2a> { NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 80006a6: 79fb ldrb r3, [r7, #7] 80006a8: f003 021f and.w r2, r3, #31 80006ac: 4907 ldr r1, [pc, #28] ; (80006cc <__NVIC_EnableIRQ+0x38>) 80006ae: f997 3007 ldrsb.w r3, [r7, #7] 80006b2: 095b lsrs r3, r3, #5 80006b4: 2001 movs r0, #1 80006b6: fa00 f202 lsl.w r2, r0, r2 80006ba: f841 2023 str.w r2, [r1, r3, lsl #2] } } 80006be: bf00 nop 80006c0: 370c adds r7, #12 80006c2: 46bd mov sp, r7 80006c4: f85d 7b04 ldr.w r7, [sp], #4 80006c8: 4770 bx lr 80006ca: bf00 nop 80006cc: e000e100 .word 0xe000e100 080006d0 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 80006d0: b480 push {r7} 80006d2: b083 sub sp, #12 80006d4: af00 add r7, sp, #0 80006d6: 4603 mov r3, r0 80006d8: 6039 str r1, [r7, #0] 80006da: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 80006dc: f997 3007 ldrsb.w r3, [r7, #7] 80006e0: 2b00 cmp r3, #0 80006e2: db0a blt.n 80006fa <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80006e4: 683b ldr r3, [r7, #0] 80006e6: b2da uxtb r2, r3 80006e8: 490c ldr r1, [pc, #48] ; (800071c <__NVIC_SetPriority+0x4c>) 80006ea: f997 3007 ldrsb.w r3, [r7, #7] 80006ee: 0112 lsls r2, r2, #4 80006f0: b2d2 uxtb r2, r2 80006f2: 440b add r3, r1 80006f4: f883 2300 strb.w r2, [r3, #768] ; 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 80006f8: e00a b.n 8000710 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80006fa: 683b ldr r3, [r7, #0] 80006fc: b2da uxtb r2, r3 80006fe: 4908 ldr r1, [pc, #32] ; (8000720 <__NVIC_SetPriority+0x50>) 8000700: 79fb ldrb r3, [r7, #7] 8000702: f003 030f and.w r3, r3, #15 8000706: 3b04 subs r3, #4 8000708: 0112 lsls r2, r2, #4 800070a: b2d2 uxtb r2, r2 800070c: 440b add r3, r1 800070e: 761a strb r2, [r3, #24] } 8000710: bf00 nop 8000712: 370c adds r7, #12 8000714: 46bd mov sp, r7 8000716: f85d 7b04 ldr.w r7, [sp], #4 800071a: 4770 bx lr 800071c: e000e100 .word 0xe000e100 8000720: e000ed00 .word 0xe000ed00 08000724 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 8000724: b480 push {r7} 8000726: b089 sub sp, #36 ; 0x24 8000728: af00 add r7, sp, #0 800072a: 60f8 str r0, [r7, #12] 800072c: 60b9 str r1, [r7, #8] 800072e: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8000730: 68fb ldr r3, [r7, #12] 8000732: f003 0307 and.w r3, r3, #7 8000736: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8000738: 69fb ldr r3, [r7, #28] 800073a: f1c3 0307 rsb r3, r3, #7 800073e: 2b04 cmp r3, #4 8000740: bf28 it cs 8000742: 2304 movcs r3, #4 8000744: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8000746: 69fb ldr r3, [r7, #28] 8000748: 3304 adds r3, #4 800074a: 2b06 cmp r3, #6 800074c: d902 bls.n 8000754 800074e: 69fb ldr r3, [r7, #28] 8000750: 3b03 subs r3, #3 8000752: e000 b.n 8000756 8000754: 2300 movs r3, #0 8000756: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8000758: f04f 32ff mov.w r2, #4294967295 800075c: 69bb ldr r3, [r7, #24] 800075e: fa02 f303 lsl.w r3, r2, r3 8000762: 43da mvns r2, r3 8000764: 68bb ldr r3, [r7, #8] 8000766: 401a ands r2, r3 8000768: 697b ldr r3, [r7, #20] 800076a: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 800076c: f04f 31ff mov.w r1, #4294967295 8000770: 697b ldr r3, [r7, #20] 8000772: fa01 f303 lsl.w r3, r1, r3 8000776: 43d9 mvns r1, r3 8000778: 687b ldr r3, [r7, #4] 800077a: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 800077c: 4313 orrs r3, r2 ); } 800077e: 4618 mov r0, r3 8000780: 3724 adds r7, #36 ; 0x24 8000782: 46bd mov sp, r7 8000784: f85d 7b04 ldr.w r7, [sp], #4 8000788: 4770 bx lr ... 0800078c : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 800078c: b580 push {r7, lr} 800078e: b082 sub sp, #8 8000790: af00 add r7, sp, #0 8000792: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8000794: 687b ldr r3, [r7, #4] 8000796: 3b01 subs r3, #1 8000798: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 800079c: d301 bcc.n 80007a2 { return (1UL); /* Reload value impossible */ 800079e: 2301 movs r3, #1 80007a0: e00f b.n 80007c2 } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 80007a2: 4a0a ldr r2, [pc, #40] ; (80007cc ) 80007a4: 687b ldr r3, [r7, #4] 80007a6: 3b01 subs r3, #1 80007a8: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 80007aa: 210f movs r1, #15 80007ac: f04f 30ff mov.w r0, #4294967295 80007b0: f7ff ff8e bl 80006d0 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 80007b4: 4b05 ldr r3, [pc, #20] ; (80007cc ) 80007b6: 2200 movs r2, #0 80007b8: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 80007ba: 4b04 ldr r3, [pc, #16] ; (80007cc ) 80007bc: 2207 movs r2, #7 80007be: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 80007c0: 2300 movs r3, #0 } 80007c2: 4618 mov r0, r3 80007c4: 3708 adds r7, #8 80007c6: 46bd mov sp, r7 80007c8: bd80 pop {r7, pc} 80007ca: bf00 nop 80007cc: e000e010 .word 0xe000e010 080007d0 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 80007d0: b580 push {r7, lr} 80007d2: b082 sub sp, #8 80007d4: af00 add r7, sp, #0 80007d6: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 80007d8: 6878 ldr r0, [r7, #4] 80007da: f7ff ff29 bl 8000630 <__NVIC_SetPriorityGrouping> } 80007de: bf00 nop 80007e0: 3708 adds r7, #8 80007e2: 46bd mov sp, r7 80007e4: bd80 pop {r7, pc} 080007e6 : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 80007e6: b580 push {r7, lr} 80007e8: b086 sub sp, #24 80007ea: af00 add r7, sp, #0 80007ec: 4603 mov r3, r0 80007ee: 60b9 str r1, [r7, #8] 80007f0: 607a str r2, [r7, #4] 80007f2: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 80007f4: 2300 movs r3, #0 80007f6: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 80007f8: f7ff ff3e bl 8000678 <__NVIC_GetPriorityGrouping> 80007fc: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 80007fe: 687a ldr r2, [r7, #4] 8000800: 68b9 ldr r1, [r7, #8] 8000802: 6978 ldr r0, [r7, #20] 8000804: f7ff ff8e bl 8000724 8000808: 4602 mov r2, r0 800080a: f997 300f ldrsb.w r3, [r7, #15] 800080e: 4611 mov r1, r2 8000810: 4618 mov r0, r3 8000812: f7ff ff5d bl 80006d0 <__NVIC_SetPriority> } 8000816: bf00 nop 8000818: 3718 adds r7, #24 800081a: 46bd mov sp, r7 800081c: bd80 pop {r7, pc} 0800081e : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 800081e: b580 push {r7, lr} 8000820: b082 sub sp, #8 8000822: af00 add r7, sp, #0 8000824: 4603 mov r3, r0 8000826: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 8000828: f997 3007 ldrsb.w r3, [r7, #7] 800082c: 4618 mov r0, r3 800082e: f7ff ff31 bl 8000694 <__NVIC_EnableIRQ> } 8000832: bf00 nop 8000834: 3708 adds r7, #8 8000836: 46bd mov sp, r7 8000838: bd80 pop {r7, pc} 0800083a : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 800083a: b580 push {r7, lr} 800083c: b082 sub sp, #8 800083e: af00 add r7, sp, #0 8000840: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 8000842: 6878 ldr r0, [r7, #4] 8000844: f7ff ffa2 bl 800078c 8000848: 4603 mov r3, r0 } 800084a: 4618 mov r0, r3 800084c: 3708 adds r7, #8 800084e: 46bd mov sp, r7 8000850: bd80 pop {r7, pc} ... 08000854 : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8000854: b480 push {r7} 8000856: b089 sub sp, #36 ; 0x24 8000858: af00 add r7, sp, #0 800085a: 6078 str r0, [r7, #4] 800085c: 6039 str r1, [r7, #0] uint32_t position; uint32_t ioposition = 0x00U; 800085e: 2300 movs r3, #0 8000860: 617b str r3, [r7, #20] uint32_t iocurrent = 0x00U; 8000862: 2300 movs r3, #0 8000864: 613b str r3, [r7, #16] uint32_t temp = 0x00U; 8000866: 2300 movs r3, #0 8000868: 61bb str r3, [r7, #24] assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Configure the port pins */ for(position = 0U; position < GPIO_NUMBER; position++) 800086a: 2300 movs r3, #0 800086c: 61fb str r3, [r7, #28] 800086e: e14d b.n 8000b0c { /* Get the IO position */ ioposition = 0x01U << position; 8000870: 2201 movs r2, #1 8000872: 69fb ldr r3, [r7, #28] 8000874: fa02 f303 lsl.w r3, r2, r3 8000878: 617b str r3, [r7, #20] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 800087a: 683b ldr r3, [r7, #0] 800087c: 681b ldr r3, [r3, #0] 800087e: 697a ldr r2, [r7, #20] 8000880: 4013 ands r3, r2 8000882: 613b str r3, [r7, #16] if(iocurrent == ioposition) 8000884: 693a ldr r2, [r7, #16] 8000886: 697b ldr r3, [r7, #20] 8000888: 429a cmp r2, r3 800088a: f040 813c bne.w 8000b06 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Alternate function mode selection */ if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) 800088e: 683b ldr r3, [r7, #0] 8000890: 685b ldr r3, [r3, #4] 8000892: 2b02 cmp r3, #2 8000894: d003 beq.n 800089e 8000896: 683b ldr r3, [r7, #0] 8000898: 685b ldr r3, [r3, #4] 800089a: 2b12 cmp r3, #18 800089c: d123 bne.n 80008e6 { /* Check the Alternate function parameter */ assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3U]; 800089e: 69fb ldr r3, [r7, #28] 80008a0: 08da lsrs r2, r3, #3 80008a2: 687b ldr r3, [r7, #4] 80008a4: 3208 adds r2, #8 80008a6: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80008aa: 61bb str r3, [r7, #24] temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; 80008ac: 69fb ldr r3, [r7, #28] 80008ae: f003 0307 and.w r3, r3, #7 80008b2: 009b lsls r3, r3, #2 80008b4: 220f movs r2, #15 80008b6: fa02 f303 lsl.w r3, r2, r3 80008ba: 43db mvns r3, r3 80008bc: 69ba ldr r2, [r7, #24] 80008be: 4013 ands r3, r2 80008c0: 61bb str r3, [r7, #24] temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U)); 80008c2: 683b ldr r3, [r7, #0] 80008c4: 691a ldr r2, [r3, #16] 80008c6: 69fb ldr r3, [r7, #28] 80008c8: f003 0307 and.w r3, r3, #7 80008cc: 009b lsls r3, r3, #2 80008ce: fa02 f303 lsl.w r3, r2, r3 80008d2: 69ba ldr r2, [r7, #24] 80008d4: 4313 orrs r3, r2 80008d6: 61bb str r3, [r7, #24] GPIOx->AFR[position >> 3U] = temp; 80008d8: 69fb ldr r3, [r7, #28] 80008da: 08da lsrs r2, r3, #3 80008dc: 687b ldr r3, [r7, #4] 80008de: 3208 adds r2, #8 80008e0: 69b9 ldr r1, [r7, #24] 80008e2: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 80008e6: 687b ldr r3, [r7, #4] 80008e8: 681b ldr r3, [r3, #0] 80008ea: 61bb str r3, [r7, #24] temp &= ~(GPIO_MODER_MODER0 << (position * 2U)); 80008ec: 69fb ldr r3, [r7, #28] 80008ee: 005b lsls r3, r3, #1 80008f0: 2203 movs r2, #3 80008f2: fa02 f303 lsl.w r3, r2, r3 80008f6: 43db mvns r3, r3 80008f8: 69ba ldr r2, [r7, #24] 80008fa: 4013 ands r3, r2 80008fc: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); 80008fe: 683b ldr r3, [r7, #0] 8000900: 685b ldr r3, [r3, #4] 8000902: f003 0203 and.w r2, r3, #3 8000906: 69fb ldr r3, [r7, #28] 8000908: 005b lsls r3, r3, #1 800090a: fa02 f303 lsl.w r3, r2, r3 800090e: 69ba ldr r2, [r7, #24] 8000910: 4313 orrs r3, r2 8000912: 61bb str r3, [r7, #24] GPIOx->MODER = temp; 8000914: 687b ldr r3, [r7, #4] 8000916: 69ba ldr r2, [r7, #24] 8000918: 601a str r2, [r3, #0] /* In case of Output or Alternate function mode selection */ if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || 800091a: 683b ldr r3, [r7, #0] 800091c: 685b ldr r3, [r3, #4] 800091e: 2b01 cmp r3, #1 8000920: d00b beq.n 800093a 8000922: 683b ldr r3, [r7, #0] 8000924: 685b ldr r3, [r3, #4] 8000926: 2b02 cmp r3, #2 8000928: d007 beq.n 800093a (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) 800092a: 683b ldr r3, [r7, #0] 800092c: 685b ldr r3, [r3, #4] if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || 800092e: 2b11 cmp r3, #17 8000930: d003 beq.n 800093a (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) 8000932: 683b ldr r3, [r7, #0] 8000934: 685b ldr r3, [r3, #4] 8000936: 2b12 cmp r3, #18 8000938: d130 bne.n 800099c { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 800093a: 687b ldr r3, [r7, #4] 800093c: 689b ldr r3, [r3, #8] 800093e: 61bb str r3, [r7, #24] temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); 8000940: 69fb ldr r3, [r7, #28] 8000942: 005b lsls r3, r3, #1 8000944: 2203 movs r2, #3 8000946: fa02 f303 lsl.w r3, r2, r3 800094a: 43db mvns r3, r3 800094c: 69ba ldr r2, [r7, #24] 800094e: 4013 ands r3, r2 8000950: 61bb str r3, [r7, #24] temp |= (GPIO_Init->Speed << (position * 2U)); 8000952: 683b ldr r3, [r7, #0] 8000954: 68da ldr r2, [r3, #12] 8000956: 69fb ldr r3, [r7, #28] 8000958: 005b lsls r3, r3, #1 800095a: fa02 f303 lsl.w r3, r2, r3 800095e: 69ba ldr r2, [r7, #24] 8000960: 4313 orrs r3, r2 8000962: 61bb str r3, [r7, #24] GPIOx->OSPEEDR = temp; 8000964: 687b ldr r3, [r7, #4] 8000966: 69ba ldr r2, [r7, #24] 8000968: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 800096a: 687b ldr r3, [r7, #4] 800096c: 685b ldr r3, [r3, #4] 800096e: 61bb str r3, [r7, #24] temp &= ~(GPIO_OTYPER_OT_0 << position) ; 8000970: 2201 movs r2, #1 8000972: 69fb ldr r3, [r7, #28] 8000974: fa02 f303 lsl.w r3, r2, r3 8000978: 43db mvns r3, r3 800097a: 69ba ldr r2, [r7, #24] 800097c: 4013 ands r3, r2 800097e: 61bb str r3, [r7, #24] temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position); 8000980: 683b ldr r3, [r7, #0] 8000982: 685b ldr r3, [r3, #4] 8000984: 091b lsrs r3, r3, #4 8000986: f003 0201 and.w r2, r3, #1 800098a: 69fb ldr r3, [r7, #28] 800098c: fa02 f303 lsl.w r3, r2, r3 8000990: 69ba ldr r2, [r7, #24] 8000992: 4313 orrs r3, r2 8000994: 61bb str r3, [r7, #24] GPIOx->OTYPER = temp; 8000996: 687b ldr r3, [r7, #4] 8000998: 69ba ldr r2, [r7, #24] 800099a: 605a str r2, [r3, #4] } /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 800099c: 687b ldr r3, [r7, #4] 800099e: 68db ldr r3, [r3, #12] 80009a0: 61bb str r3, [r7, #24] temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); 80009a2: 69fb ldr r3, [r7, #28] 80009a4: 005b lsls r3, r3, #1 80009a6: 2203 movs r2, #3 80009a8: fa02 f303 lsl.w r3, r2, r3 80009ac: 43db mvns r3, r3 80009ae: 69ba ldr r2, [r7, #24] 80009b0: 4013 ands r3, r2 80009b2: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Pull) << (position * 2U)); 80009b4: 683b ldr r3, [r7, #0] 80009b6: 689a ldr r2, [r3, #8] 80009b8: 69fb ldr r3, [r7, #28] 80009ba: 005b lsls r3, r3, #1 80009bc: fa02 f303 lsl.w r3, r2, r3 80009c0: 69ba ldr r2, [r7, #24] 80009c2: 4313 orrs r3, r2 80009c4: 61bb str r3, [r7, #24] GPIOx->PUPDR = temp; 80009c6: 687b ldr r3, [r7, #4] 80009c8: 69ba ldr r2, [r7, #24] 80009ca: 60da str r2, [r3, #12] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 80009cc: 683b ldr r3, [r7, #0] 80009ce: 685b ldr r3, [r3, #4] 80009d0: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 80009d4: 2b00 cmp r3, #0 80009d6: f000 8096 beq.w 8000b06 { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 80009da: 2300 movs r3, #0 80009dc: 60fb str r3, [r7, #12] 80009de: 4b50 ldr r3, [pc, #320] ; (8000b20 ) 80009e0: 6c5b ldr r3, [r3, #68] ; 0x44 80009e2: 4a4f ldr r2, [pc, #316] ; (8000b20 ) 80009e4: f443 4380 orr.w r3, r3, #16384 ; 0x4000 80009e8: 6453 str r3, [r2, #68] ; 0x44 80009ea: 4b4d ldr r3, [pc, #308] ; (8000b20 ) 80009ec: 6c5b ldr r3, [r3, #68] ; 0x44 80009ee: f403 4380 and.w r3, r3, #16384 ; 0x4000 80009f2: 60fb str r3, [r7, #12] 80009f4: 68fb ldr r3, [r7, #12] temp = SYSCFG->EXTICR[position >> 2U]; 80009f6: 4a4b ldr r2, [pc, #300] ; (8000b24 ) 80009f8: 69fb ldr r3, [r7, #28] 80009fa: 089b lsrs r3, r3, #2 80009fc: 3302 adds r3, #2 80009fe: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8000a02: 61bb str r3, [r7, #24] temp &= ~(0x0FU << (4U * (position & 0x03U))); 8000a04: 69fb ldr r3, [r7, #28] 8000a06: f003 0303 and.w r3, r3, #3 8000a0a: 009b lsls r3, r3, #2 8000a0c: 220f movs r2, #15 8000a0e: fa02 f303 lsl.w r3, r2, r3 8000a12: 43db mvns r3, r3 8000a14: 69ba ldr r2, [r7, #24] 8000a16: 4013 ands r3, r2 8000a18: 61bb str r3, [r7, #24] temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); 8000a1a: 687b ldr r3, [r7, #4] 8000a1c: 4a42 ldr r2, [pc, #264] ; (8000b28 ) 8000a1e: 4293 cmp r3, r2 8000a20: d00d beq.n 8000a3e 8000a22: 687b ldr r3, [r7, #4] 8000a24: 4a41 ldr r2, [pc, #260] ; (8000b2c ) 8000a26: 4293 cmp r3, r2 8000a28: d007 beq.n 8000a3a 8000a2a: 687b ldr r3, [r7, #4] 8000a2c: 4a40 ldr r2, [pc, #256] ; (8000b30 ) 8000a2e: 4293 cmp r3, r2 8000a30: d101 bne.n 8000a36 8000a32: 2302 movs r3, #2 8000a34: e004 b.n 8000a40 8000a36: 2307 movs r3, #7 8000a38: e002 b.n 8000a40 8000a3a: 2301 movs r3, #1 8000a3c: e000 b.n 8000a40 8000a3e: 2300 movs r3, #0 8000a40: 69fa ldr r2, [r7, #28] 8000a42: f002 0203 and.w r2, r2, #3 8000a46: 0092 lsls r2, r2, #2 8000a48: 4093 lsls r3, r2 8000a4a: 69ba ldr r2, [r7, #24] 8000a4c: 4313 orrs r3, r2 8000a4e: 61bb str r3, [r7, #24] SYSCFG->EXTICR[position >> 2U] = temp; 8000a50: 4934 ldr r1, [pc, #208] ; (8000b24 ) 8000a52: 69fb ldr r3, [r7, #28] 8000a54: 089b lsrs r3, r3, #2 8000a56: 3302 adds r3, #2 8000a58: 69ba ldr r2, [r7, #24] 8000a5a: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear EXTI line configuration */ temp = EXTI->IMR; 8000a5e: 4b35 ldr r3, [pc, #212] ; (8000b34 ) 8000a60: 681b ldr r3, [r3, #0] 8000a62: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 8000a64: 693b ldr r3, [r7, #16] 8000a66: 43db mvns r3, r3 8000a68: 69ba ldr r2, [r7, #24] 8000a6a: 4013 ands r3, r2 8000a6c: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) 8000a6e: 683b ldr r3, [r7, #0] 8000a70: 685b ldr r3, [r3, #4] 8000a72: f403 3380 and.w r3, r3, #65536 ; 0x10000 8000a76: 2b00 cmp r3, #0 8000a78: d003 beq.n 8000a82 { temp |= iocurrent; 8000a7a: 69ba ldr r2, [r7, #24] 8000a7c: 693b ldr r3, [r7, #16] 8000a7e: 4313 orrs r3, r2 8000a80: 61bb str r3, [r7, #24] } EXTI->IMR = temp; 8000a82: 4a2c ldr r2, [pc, #176] ; (8000b34 ) 8000a84: 69bb ldr r3, [r7, #24] 8000a86: 6013 str r3, [r2, #0] temp = EXTI->EMR; 8000a88: 4b2a ldr r3, [pc, #168] ; (8000b34 ) 8000a8a: 685b ldr r3, [r3, #4] 8000a8c: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 8000a8e: 693b ldr r3, [r7, #16] 8000a90: 43db mvns r3, r3 8000a92: 69ba ldr r2, [r7, #24] 8000a94: 4013 ands r3, r2 8000a96: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) 8000a98: 683b ldr r3, [r7, #0] 8000a9a: 685b ldr r3, [r3, #4] 8000a9c: f403 3300 and.w r3, r3, #131072 ; 0x20000 8000aa0: 2b00 cmp r3, #0 8000aa2: d003 beq.n 8000aac { temp |= iocurrent; 8000aa4: 69ba ldr r2, [r7, #24] 8000aa6: 693b ldr r3, [r7, #16] 8000aa8: 4313 orrs r3, r2 8000aaa: 61bb str r3, [r7, #24] } EXTI->EMR = temp; 8000aac: 4a21 ldr r2, [pc, #132] ; (8000b34 ) 8000aae: 69bb ldr r3, [r7, #24] 8000ab0: 6053 str r3, [r2, #4] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR; 8000ab2: 4b20 ldr r3, [pc, #128] ; (8000b34 ) 8000ab4: 689b ldr r3, [r3, #8] 8000ab6: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 8000ab8: 693b ldr r3, [r7, #16] 8000aba: 43db mvns r3, r3 8000abc: 69ba ldr r2, [r7, #24] 8000abe: 4013 ands r3, r2 8000ac0: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) 8000ac2: 683b ldr r3, [r7, #0] 8000ac4: 685b ldr r3, [r3, #4] 8000ac6: f403 1380 and.w r3, r3, #1048576 ; 0x100000 8000aca: 2b00 cmp r3, #0 8000acc: d003 beq.n 8000ad6 { temp |= iocurrent; 8000ace: 69ba ldr r2, [r7, #24] 8000ad0: 693b ldr r3, [r7, #16] 8000ad2: 4313 orrs r3, r2 8000ad4: 61bb str r3, [r7, #24] } EXTI->RTSR = temp; 8000ad6: 4a17 ldr r2, [pc, #92] ; (8000b34 ) 8000ad8: 69bb ldr r3, [r7, #24] 8000ada: 6093 str r3, [r2, #8] temp = EXTI->FTSR; 8000adc: 4b15 ldr r3, [pc, #84] ; (8000b34 ) 8000ade: 68db ldr r3, [r3, #12] 8000ae0: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 8000ae2: 693b ldr r3, [r7, #16] 8000ae4: 43db mvns r3, r3 8000ae6: 69ba ldr r2, [r7, #24] 8000ae8: 4013 ands r3, r2 8000aea: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) 8000aec: 683b ldr r3, [r7, #0] 8000aee: 685b ldr r3, [r3, #4] 8000af0: f403 1300 and.w r3, r3, #2097152 ; 0x200000 8000af4: 2b00 cmp r3, #0 8000af6: d003 beq.n 8000b00 { temp |= iocurrent; 8000af8: 69ba ldr r2, [r7, #24] 8000afa: 693b ldr r3, [r7, #16] 8000afc: 4313 orrs r3, r2 8000afe: 61bb str r3, [r7, #24] } EXTI->FTSR = temp; 8000b00: 4a0c ldr r2, [pc, #48] ; (8000b34 ) 8000b02: 69bb ldr r3, [r7, #24] 8000b04: 60d3 str r3, [r2, #12] for(position = 0U; position < GPIO_NUMBER; position++) 8000b06: 69fb ldr r3, [r7, #28] 8000b08: 3301 adds r3, #1 8000b0a: 61fb str r3, [r7, #28] 8000b0c: 69fb ldr r3, [r7, #28] 8000b0e: 2b0f cmp r3, #15 8000b10: f67f aeae bls.w 8000870 } } } } 8000b14: bf00 nop 8000b16: 3724 adds r7, #36 ; 0x24 8000b18: 46bd mov sp, r7 8000b1a: f85d 7b04 ldr.w r7, [sp], #4 8000b1e: 4770 bx lr 8000b20: 40023800 .word 0x40023800 8000b24: 40013800 .word 0x40013800 8000b28: 40020000 .word 0x40020000 8000b2c: 40020400 .word 0x40020400 8000b30: 40020800 .word 0x40020800 8000b34: 40013c00 .word 0x40013c00 08000b38 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8000b38: b480 push {r7} 8000b3a: b083 sub sp, #12 8000b3c: af00 add r7, sp, #0 8000b3e: 6078 str r0, [r7, #4] 8000b40: 460b mov r3, r1 8000b42: 807b strh r3, [r7, #2] 8000b44: 4613 mov r3, r2 8000b46: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if(PinState != GPIO_PIN_RESET) 8000b48: 787b ldrb r3, [r7, #1] 8000b4a: 2b00 cmp r3, #0 8000b4c: d003 beq.n 8000b56 { GPIOx->BSRR = GPIO_Pin; 8000b4e: 887a ldrh r2, [r7, #2] 8000b50: 687b ldr r3, [r7, #4] 8000b52: 619a str r2, [r3, #24] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; } } 8000b54: e003 b.n 8000b5e GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; 8000b56: 887b ldrh r3, [r7, #2] 8000b58: 041a lsls r2, r3, #16 8000b5a: 687b ldr r3, [r7, #4] 8000b5c: 619a str r2, [r3, #24] } 8000b5e: bf00 nop 8000b60: 370c adds r7, #12 8000b62: 46bd mov sp, r7 8000b64: f85d 7b04 ldr.w r7, [sp], #4 8000b68: 4770 bx lr ... 08000b6c : * @brief This function handles EXTI interrupt request. * @param GPIO_Pin Specifies the pins connected EXTI line * @retval None */ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) { 8000b6c: b580 push {r7, lr} 8000b6e: b082 sub sp, #8 8000b70: af00 add r7, sp, #0 8000b72: 4603 mov r3, r0 8000b74: 80fb strh r3, [r7, #6] /* EXTI line interrupt detected */ if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) 8000b76: 4b08 ldr r3, [pc, #32] ; (8000b98 ) 8000b78: 695a ldr r2, [r3, #20] 8000b7a: 88fb ldrh r3, [r7, #6] 8000b7c: 4013 ands r3, r2 8000b7e: 2b00 cmp r3, #0 8000b80: d006 beq.n 8000b90 { __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); 8000b82: 4a05 ldr r2, [pc, #20] ; (8000b98 ) 8000b84: 88fb ldrh r3, [r7, #6] 8000b86: 6153 str r3, [r2, #20] HAL_GPIO_EXTI_Callback(GPIO_Pin); 8000b88: 88fb ldrh r3, [r7, #6] 8000b8a: 4618 mov r0, r3 8000b8c: f001 f9ac bl 8001ee8 } } 8000b90: bf00 nop 8000b92: 3708 adds r7, #8 8000b94: 46bd mov sp, r7 8000b96: bd80 pop {r7, pc} 8000b98: 40013c00 .word 0x40013c00 08000b9c : * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8000b9c: b580 push {r7, lr} 8000b9e: b084 sub sp, #16 8000ba0: af00 add r7, sp, #0 8000ba2: 6078 str r0, [r7, #4] 8000ba4: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if(RCC_ClkInitStruct == NULL) 8000ba6: 687b ldr r3, [r7, #4] 8000ba8: 2b00 cmp r3, #0 8000baa: d101 bne.n 8000bb0 { return HAL_ERROR; 8000bac: 2301 movs r3, #1 8000bae: e0ca b.n 8000d46 /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if(FLatency > __HAL_FLASH_GET_LATENCY()) 8000bb0: 4b67 ldr r3, [pc, #412] ; (8000d50 ) 8000bb2: 681b ldr r3, [r3, #0] 8000bb4: f003 030f and.w r3, r3, #15 8000bb8: 683a ldr r2, [r7, #0] 8000bba: 429a cmp r2, r3 8000bbc: d90c bls.n 8000bd8 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8000bbe: 4b64 ldr r3, [pc, #400] ; (8000d50 ) 8000bc0: 683a ldr r2, [r7, #0] 8000bc2: b2d2 uxtb r2, r2 8000bc4: 701a strb r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) 8000bc6: 4b62 ldr r3, [pc, #392] ; (8000d50 ) 8000bc8: 681b ldr r3, [r3, #0] 8000bca: f003 030f and.w r3, r3, #15 8000bce: 683a ldr r2, [r7, #0] 8000bd0: 429a cmp r2, r3 8000bd2: d001 beq.n 8000bd8 { return HAL_ERROR; 8000bd4: 2301 movs r3, #1 8000bd6: e0b6 b.n 8000d46 } } /*-------------------------- HCLK Configuration --------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8000bd8: 687b ldr r3, [r7, #4] 8000bda: 681b ldr r3, [r3, #0] 8000bdc: f003 0302 and.w r3, r3, #2 8000be0: 2b00 cmp r3, #0 8000be2: d020 beq.n 8000c26 { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8000be4: 687b ldr r3, [r7, #4] 8000be6: 681b ldr r3, [r3, #0] 8000be8: f003 0304 and.w r3, r3, #4 8000bec: 2b00 cmp r3, #0 8000bee: d005 beq.n 8000bfc { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 8000bf0: 4b58 ldr r3, [pc, #352] ; (8000d54 ) 8000bf2: 689b ldr r3, [r3, #8] 8000bf4: 4a57 ldr r2, [pc, #348] ; (8000d54 ) 8000bf6: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00 8000bfa: 6093 str r3, [r2, #8] } if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8000bfc: 687b ldr r3, [r7, #4] 8000bfe: 681b ldr r3, [r3, #0] 8000c00: f003 0308 and.w r3, r3, #8 8000c04: 2b00 cmp r3, #0 8000c06: d005 beq.n 8000c14 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); 8000c08: 4b52 ldr r3, [pc, #328] ; (8000d54 ) 8000c0a: 689b ldr r3, [r3, #8] 8000c0c: 4a51 ldr r2, [pc, #324] ; (8000d54 ) 8000c0e: f443 4360 orr.w r3, r3, #57344 ; 0xe000 8000c12: 6093 str r3, [r2, #8] } assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8000c14: 4b4f ldr r3, [pc, #316] ; (8000d54 ) 8000c16: 689b ldr r3, [r3, #8] 8000c18: f023 02f0 bic.w r2, r3, #240 ; 0xf0 8000c1c: 687b ldr r3, [r7, #4] 8000c1e: 689b ldr r3, [r3, #8] 8000c20: 494c ldr r1, [pc, #304] ; (8000d54 ) 8000c22: 4313 orrs r3, r2 8000c24: 608b str r3, [r1, #8] } /*------------------------- SYSCLK Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 8000c26: 687b ldr r3, [r7, #4] 8000c28: 681b ldr r3, [r3, #0] 8000c2a: f003 0301 and.w r3, r3, #1 8000c2e: 2b00 cmp r3, #0 8000c30: d044 beq.n 8000cbc { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8000c32: 687b ldr r3, [r7, #4] 8000c34: 685b ldr r3, [r3, #4] 8000c36: 2b01 cmp r3, #1 8000c38: d107 bne.n 8000c4a { /* Check the HSE ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8000c3a: 4b46 ldr r3, [pc, #280] ; (8000d54 ) 8000c3c: 681b ldr r3, [r3, #0] 8000c3e: f403 3300 and.w r3, r3, #131072 ; 0x20000 8000c42: 2b00 cmp r3, #0 8000c44: d119 bne.n 8000c7a { return HAL_ERROR; 8000c46: 2301 movs r3, #1 8000c48: e07d b.n 8000d46 } } /* PLL is selected as System Clock Source */ else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || 8000c4a: 687b ldr r3, [r7, #4] 8000c4c: 685b ldr r3, [r3, #4] 8000c4e: 2b02 cmp r3, #2 8000c50: d003 beq.n 8000c5a (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK)) 8000c52: 687b ldr r3, [r7, #4] 8000c54: 685b ldr r3, [r3, #4] else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || 8000c56: 2b03 cmp r3, #3 8000c58: d107 bne.n 8000c6a { /* Check the PLL ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8000c5a: 4b3e ldr r3, [pc, #248] ; (8000d54 ) 8000c5c: 681b ldr r3, [r3, #0] 8000c5e: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8000c62: 2b00 cmp r3, #0 8000c64: d109 bne.n 8000c7a { return HAL_ERROR; 8000c66: 2301 movs r3, #1 8000c68: e06d b.n 8000d46 } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8000c6a: 4b3a ldr r3, [pc, #232] ; (8000d54 ) 8000c6c: 681b ldr r3, [r3, #0] 8000c6e: f003 0302 and.w r3, r3, #2 8000c72: 2b00 cmp r3, #0 8000c74: d101 bne.n 8000c7a { return HAL_ERROR; 8000c76: 2301 movs r3, #1 8000c78: e065 b.n 8000d46 } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 8000c7a: 4b36 ldr r3, [pc, #216] ; (8000d54 ) 8000c7c: 689b ldr r3, [r3, #8] 8000c7e: f023 0203 bic.w r2, r3, #3 8000c82: 687b ldr r3, [r7, #4] 8000c84: 685b ldr r3, [r3, #4] 8000c86: 4933 ldr r1, [pc, #204] ; (8000d54 ) 8000c88: 4313 orrs r3, r2 8000c8a: 608b str r3, [r1, #8] /* Get Start Tick */ tickstart = HAL_GetTick(); 8000c8c: f7ff fca2 bl 80005d4 8000c90: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8000c92: e00a b.n 8000caa { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8000c94: f7ff fc9e bl 80005d4 8000c98: 4602 mov r2, r0 8000c9a: 68fb ldr r3, [r7, #12] 8000c9c: 1ad3 subs r3, r2, r3 8000c9e: f241 3288 movw r2, #5000 ; 0x1388 8000ca2: 4293 cmp r3, r2 8000ca4: d901 bls.n 8000caa { return HAL_TIMEOUT; 8000ca6: 2303 movs r3, #3 8000ca8: e04d b.n 8000d46 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8000caa: 4b2a ldr r3, [pc, #168] ; (8000d54 ) 8000cac: 689b ldr r3, [r3, #8] 8000cae: f003 020c and.w r2, r3, #12 8000cb2: 687b ldr r3, [r7, #4] 8000cb4: 685b ldr r3, [r3, #4] 8000cb6: 009b lsls r3, r3, #2 8000cb8: 429a cmp r2, r3 8000cba: d1eb bne.n 8000c94 } } } /* Decreasing the number of wait states because of lower CPU frequency */ if(FLatency < __HAL_FLASH_GET_LATENCY()) 8000cbc: 4b24 ldr r3, [pc, #144] ; (8000d50 ) 8000cbe: 681b ldr r3, [r3, #0] 8000cc0: f003 030f and.w r3, r3, #15 8000cc4: 683a ldr r2, [r7, #0] 8000cc6: 429a cmp r2, r3 8000cc8: d20c bcs.n 8000ce4 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8000cca: 4b21 ldr r3, [pc, #132] ; (8000d50 ) 8000ccc: 683a ldr r2, [r7, #0] 8000cce: b2d2 uxtb r2, r2 8000cd0: 701a strb r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) 8000cd2: 4b1f ldr r3, [pc, #124] ; (8000d50 ) 8000cd4: 681b ldr r3, [r3, #0] 8000cd6: f003 030f and.w r3, r3, #15 8000cda: 683a ldr r2, [r7, #0] 8000cdc: 429a cmp r2, r3 8000cde: d001 beq.n 8000ce4 { return HAL_ERROR; 8000ce0: 2301 movs r3, #1 8000ce2: e030 b.n 8000d46 } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8000ce4: 687b ldr r3, [r7, #4] 8000ce6: 681b ldr r3, [r3, #0] 8000ce8: f003 0304 and.w r3, r3, #4 8000cec: 2b00 cmp r3, #0 8000cee: d008 beq.n 8000d02 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 8000cf0: 4b18 ldr r3, [pc, #96] ; (8000d54 ) 8000cf2: 689b ldr r3, [r3, #8] 8000cf4: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00 8000cf8: 687b ldr r3, [r7, #4] 8000cfa: 68db ldr r3, [r3, #12] 8000cfc: 4915 ldr r1, [pc, #84] ; (8000d54 ) 8000cfe: 4313 orrs r3, r2 8000d00: 608b str r3, [r1, #8] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8000d02: 687b ldr r3, [r7, #4] 8000d04: 681b ldr r3, [r3, #0] 8000d06: f003 0308 and.w r3, r3, #8 8000d0a: 2b00 cmp r3, #0 8000d0c: d009 beq.n 8000d22 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); 8000d0e: 4b11 ldr r3, [pc, #68] ; (8000d54 ) 8000d10: 689b ldr r3, [r3, #8] 8000d12: f423 4260 bic.w r2, r3, #57344 ; 0xe000 8000d16: 687b ldr r3, [r7, #4] 8000d18: 691b ldr r3, [r3, #16] 8000d1a: 00db lsls r3, r3, #3 8000d1c: 490d ldr r1, [pc, #52] ; (8000d54 ) 8000d1e: 4313 orrs r3, r2 8000d20: 608b str r3, [r1, #8] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos]; 8000d22: f000 f81d bl 8000d60 8000d26: 4601 mov r1, r0 8000d28: 4b0a ldr r3, [pc, #40] ; (8000d54 ) 8000d2a: 689b ldr r3, [r3, #8] 8000d2c: 091b lsrs r3, r3, #4 8000d2e: f003 030f and.w r3, r3, #15 8000d32: 4a09 ldr r2, [pc, #36] ; (8000d58 ) 8000d34: 5cd3 ldrb r3, [r2, r3] 8000d36: fa21 f303 lsr.w r3, r1, r3 8000d3a: 4a08 ldr r2, [pc, #32] ; (8000d5c ) 8000d3c: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings */ HAL_InitTick (TICK_INT_PRIORITY); 8000d3e: 2000 movs r0, #0 8000d40: f7ff fc04 bl 800054c return HAL_OK; 8000d44: 2300 movs r3, #0 } 8000d46: 4618 mov r0, r3 8000d48: 3710 adds r7, #16 8000d4a: 46bd mov sp, r7 8000d4c: bd80 pop {r7, pc} 8000d4e: bf00 nop 8000d50: 40023c00 .word 0x40023c00 8000d54: 40023800 .word 0x40023800 8000d58: 08003014 .word 0x08003014 8000d5c: 20000034 .word 0x20000034 08000d60 : * * * @retval SYSCLK frequency */ __weak uint32_t HAL_RCC_GetSysClockFreq(void) { 8000d60: b5f0 push {r4, r5, r6, r7, lr} 8000d62: b085 sub sp, #20 8000d64: af00 add r7, sp, #0 uint32_t pllm = 0U, pllvco = 0U, pllp = 0U; 8000d66: 2300 movs r3, #0 8000d68: 607b str r3, [r7, #4] 8000d6a: 2300 movs r3, #0 8000d6c: 60fb str r3, [r7, #12] 8000d6e: 2300 movs r3, #0 8000d70: 603b str r3, [r7, #0] uint32_t sysclockfreq = 0U; 8000d72: 2300 movs r3, #0 8000d74: 60bb str r3, [r7, #8] /* Get SYSCLK source -------------------------------------------------------*/ switch (RCC->CFGR & RCC_CFGR_SWS) 8000d76: 4b63 ldr r3, [pc, #396] ; (8000f04 ) 8000d78: 689b ldr r3, [r3, #8] 8000d7a: f003 030c and.w r3, r3, #12 8000d7e: 2b04 cmp r3, #4 8000d80: d007 beq.n 8000d92 8000d82: 2b08 cmp r3, #8 8000d84: d008 beq.n 8000d98 8000d86: 2b00 cmp r3, #0 8000d88: f040 80b4 bne.w 8000ef4 { case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ { sysclockfreq = HSI_VALUE; 8000d8c: 4b5e ldr r3, [pc, #376] ; (8000f08 ) 8000d8e: 60bb str r3, [r7, #8] break; 8000d90: e0b3 b.n 8000efa } case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ { sysclockfreq = HSE_VALUE; 8000d92: 4b5e ldr r3, [pc, #376] ; (8000f0c ) 8000d94: 60bb str r3, [r7, #8] break; 8000d96: e0b0 b.n 8000efa } case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */ { /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN SYSCLK = PLL_VCO / PLLP */ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; 8000d98: 4b5a ldr r3, [pc, #360] ; (8000f04 ) 8000d9a: 685b ldr r3, [r3, #4] 8000d9c: f003 033f and.w r3, r3, #63 ; 0x3f 8000da0: 607b str r3, [r7, #4] if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) 8000da2: 4b58 ldr r3, [pc, #352] ; (8000f04 ) 8000da4: 685b ldr r3, [r3, #4] 8000da6: f403 0380 and.w r3, r3, #4194304 ; 0x400000 8000daa: 2b00 cmp r3, #0 8000dac: d04a beq.n 8000e44 { /* HSE used as PLL clock source */ pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 8000dae: 4b55 ldr r3, [pc, #340] ; (8000f04 ) 8000db0: 685b ldr r3, [r3, #4] 8000db2: 099b lsrs r3, r3, #6 8000db4: f04f 0400 mov.w r4, #0 8000db8: f240 11ff movw r1, #511 ; 0x1ff 8000dbc: f04f 0200 mov.w r2, #0 8000dc0: ea03 0501 and.w r5, r3, r1 8000dc4: ea04 0602 and.w r6, r4, r2 8000dc8: 4629 mov r1, r5 8000dca: 4632 mov r2, r6 8000dcc: f04f 0300 mov.w r3, #0 8000dd0: f04f 0400 mov.w r4, #0 8000dd4: 0154 lsls r4, r2, #5 8000dd6: ea44 64d1 orr.w r4, r4, r1, lsr #27 8000dda: 014b lsls r3, r1, #5 8000ddc: 4619 mov r1, r3 8000dde: 4622 mov r2, r4 8000de0: 1b49 subs r1, r1, r5 8000de2: eb62 0206 sbc.w r2, r2, r6 8000de6: f04f 0300 mov.w r3, #0 8000dea: f04f 0400 mov.w r4, #0 8000dee: 0194 lsls r4, r2, #6 8000df0: ea44 6491 orr.w r4, r4, r1, lsr #26 8000df4: 018b lsls r3, r1, #6 8000df6: 1a5b subs r3, r3, r1 8000df8: eb64 0402 sbc.w r4, r4, r2 8000dfc: f04f 0100 mov.w r1, #0 8000e00: f04f 0200 mov.w r2, #0 8000e04: 00e2 lsls r2, r4, #3 8000e06: ea42 7253 orr.w r2, r2, r3, lsr #29 8000e0a: 00d9 lsls r1, r3, #3 8000e0c: 460b mov r3, r1 8000e0e: 4614 mov r4, r2 8000e10: 195b adds r3, r3, r5 8000e12: eb44 0406 adc.w r4, r4, r6 8000e16: f04f 0100 mov.w r1, #0 8000e1a: f04f 0200 mov.w r2, #0 8000e1e: 0262 lsls r2, r4, #9 8000e20: ea42 52d3 orr.w r2, r2, r3, lsr #23 8000e24: 0259 lsls r1, r3, #9 8000e26: 460b mov r3, r1 8000e28: 4614 mov r4, r2 8000e2a: 4618 mov r0, r3 8000e2c: 4621 mov r1, r4 8000e2e: 687b ldr r3, [r7, #4] 8000e30: f04f 0400 mov.w r4, #0 8000e34: 461a mov r2, r3 8000e36: 4623 mov r3, r4 8000e38: f7ff f9e6 bl 8000208 <__aeabi_uldivmod> 8000e3c: 4603 mov r3, r0 8000e3e: 460c mov r4, r1 8000e40: 60fb str r3, [r7, #12] 8000e42: e049 b.n 8000ed8 } else { /* HSI used as PLL clock source */ pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 8000e44: 4b2f ldr r3, [pc, #188] ; (8000f04 ) 8000e46: 685b ldr r3, [r3, #4] 8000e48: 099b lsrs r3, r3, #6 8000e4a: f04f 0400 mov.w r4, #0 8000e4e: f240 11ff movw r1, #511 ; 0x1ff 8000e52: f04f 0200 mov.w r2, #0 8000e56: ea03 0501 and.w r5, r3, r1 8000e5a: ea04 0602 and.w r6, r4, r2 8000e5e: 4629 mov r1, r5 8000e60: 4632 mov r2, r6 8000e62: f04f 0300 mov.w r3, #0 8000e66: f04f 0400 mov.w r4, #0 8000e6a: 0154 lsls r4, r2, #5 8000e6c: ea44 64d1 orr.w r4, r4, r1, lsr #27 8000e70: 014b lsls r3, r1, #5 8000e72: 4619 mov r1, r3 8000e74: 4622 mov r2, r4 8000e76: 1b49 subs r1, r1, r5 8000e78: eb62 0206 sbc.w r2, r2, r6 8000e7c: f04f 0300 mov.w r3, #0 8000e80: f04f 0400 mov.w r4, #0 8000e84: 0194 lsls r4, r2, #6 8000e86: ea44 6491 orr.w r4, r4, r1, lsr #26 8000e8a: 018b lsls r3, r1, #6 8000e8c: 1a5b subs r3, r3, r1 8000e8e: eb64 0402 sbc.w r4, r4, r2 8000e92: f04f 0100 mov.w r1, #0 8000e96: f04f 0200 mov.w r2, #0 8000e9a: 00e2 lsls r2, r4, #3 8000e9c: ea42 7253 orr.w r2, r2, r3, lsr #29 8000ea0: 00d9 lsls r1, r3, #3 8000ea2: 460b mov r3, r1 8000ea4: 4614 mov r4, r2 8000ea6: 195b adds r3, r3, r5 8000ea8: eb44 0406 adc.w r4, r4, r6 8000eac: f04f 0100 mov.w r1, #0 8000eb0: f04f 0200 mov.w r2, #0 8000eb4: 02a2 lsls r2, r4, #10 8000eb6: ea42 5293 orr.w r2, r2, r3, lsr #22 8000eba: 0299 lsls r1, r3, #10 8000ebc: 460b mov r3, r1 8000ebe: 4614 mov r4, r2 8000ec0: 4618 mov r0, r3 8000ec2: 4621 mov r1, r4 8000ec4: 687b ldr r3, [r7, #4] 8000ec6: f04f 0400 mov.w r4, #0 8000eca: 461a mov r2, r3 8000ecc: 4623 mov r3, r4 8000ece: f7ff f99b bl 8000208 <__aeabi_uldivmod> 8000ed2: 4603 mov r3, r0 8000ed4: 460c mov r4, r1 8000ed6: 60fb str r3, [r7, #12] } pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U); 8000ed8: 4b0a ldr r3, [pc, #40] ; (8000f04 ) 8000eda: 685b ldr r3, [r3, #4] 8000edc: 0c1b lsrs r3, r3, #16 8000ede: f003 0303 and.w r3, r3, #3 8000ee2: 3301 adds r3, #1 8000ee4: 005b lsls r3, r3, #1 8000ee6: 603b str r3, [r7, #0] sysclockfreq = pllvco/pllp; 8000ee8: 68fa ldr r2, [r7, #12] 8000eea: 683b ldr r3, [r7, #0] 8000eec: fbb2 f3f3 udiv r3, r2, r3 8000ef0: 60bb str r3, [r7, #8] break; 8000ef2: e002 b.n 8000efa } default: { sysclockfreq = HSI_VALUE; 8000ef4: 4b04 ldr r3, [pc, #16] ; (8000f08 ) 8000ef6: 60bb str r3, [r7, #8] break; 8000ef8: bf00 nop } } return sysclockfreq; 8000efa: 68bb ldr r3, [r7, #8] } 8000efc: 4618 mov r0, r3 8000efe: 3714 adds r7, #20 8000f00: 46bd mov sp, r7 8000f02: bdf0 pop {r4, r5, r6, r7, pc} 8000f04: 40023800 .word 0x40023800 8000f08: 00f42400 .word 0x00f42400 8000f0c: 007a1200 .word 0x007a1200 08000f10 : * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 8000f10: b480 push {r7} 8000f12: af00 add r7, sp, #0 return SystemCoreClock; 8000f14: 4b03 ldr r3, [pc, #12] ; (8000f24 ) 8000f16: 681b ldr r3, [r3, #0] } 8000f18: 4618 mov r0, r3 8000f1a: 46bd mov sp, r7 8000f1c: f85d 7b04 ldr.w r7, [sp], #4 8000f20: 4770 bx lr 8000f22: bf00 nop 8000f24: 20000034 .word 0x20000034 08000f28 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 8000f28: b580 push {r7, lr} 8000f2a: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]); 8000f2c: f7ff fff0 bl 8000f10 8000f30: 4601 mov r1, r0 8000f32: 4b05 ldr r3, [pc, #20] ; (8000f48 ) 8000f34: 689b ldr r3, [r3, #8] 8000f36: 0a9b lsrs r3, r3, #10 8000f38: f003 0307 and.w r3, r3, #7 8000f3c: 4a03 ldr r2, [pc, #12] ; (8000f4c ) 8000f3e: 5cd3 ldrb r3, [r2, r3] 8000f40: fa21 f303 lsr.w r3, r1, r3 } 8000f44: 4618 mov r0, r3 8000f46: bd80 pop {r7, pc} 8000f48: 40023800 .word 0x40023800 8000f4c: 08003024 .word 0x08003024 08000f50 : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 8000f50: b580 push {r7, lr} 8000f52: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]); 8000f54: f7ff ffdc bl 8000f10 8000f58: 4601 mov r1, r0 8000f5a: 4b05 ldr r3, [pc, #20] ; (8000f70 ) 8000f5c: 689b ldr r3, [r3, #8] 8000f5e: 0b5b lsrs r3, r3, #13 8000f60: f003 0307 and.w r3, r3, #7 8000f64: 4a03 ldr r2, [pc, #12] ; (8000f74 ) 8000f66: 5cd3 ldrb r3, [r2, r3] 8000f68: fa21 f303 lsr.w r3, r1, r3 } 8000f6c: 4618 mov r0, r3 8000f6e: bd80 pop {r7, pc} 8000f70: 40023800 .word 0x40023800 8000f74: 08003024 .word 0x08003024 08000f78 : * @note This function add the PLL/PLLR factor management during PLL configuration this feature * is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 8000f78: b580 push {r7, lr} 8000f7a: b086 sub sp, #24 8000f7c: af00 add r7, sp, #0 8000f7e: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8000f80: 2300 movs r3, #0 8000f82: 613b str r3, [r7, #16] /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8000f84: 687b ldr r3, [r7, #4] 8000f86: 681b ldr r3, [r3, #0] 8000f88: f003 0301 and.w r3, r3, #1 8000f8c: 2b00 cmp r3, #0 8000f8e: d075 beq.n 800107c #if defined(STM32F446xx) if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) ||\ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) #else if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\ 8000f90: 4ba2 ldr r3, [pc, #648] ; (800121c ) 8000f92: 689b ldr r3, [r3, #8] 8000f94: f003 030c and.w r3, r3, #12 8000f98: 2b04 cmp r3, #4 8000f9a: d00c beq.n 8000fb6 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) 8000f9c: 4b9f ldr r3, [pc, #636] ; (800121c ) 8000f9e: 689b ldr r3, [r3, #8] 8000fa0: f003 030c and.w r3, r3, #12 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\ 8000fa4: 2b08 cmp r3, #8 8000fa6: d112 bne.n 8000fce ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) 8000fa8: 4b9c ldr r3, [pc, #624] ; (800121c ) 8000faa: 685b ldr r3, [r3, #4] 8000fac: f403 0380 and.w r3, r3, #4194304 ; 0x400000 8000fb0: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 8000fb4: d10b bne.n 8000fce #endif /* STM32F446xx */ { if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8000fb6: 4b99 ldr r3, [pc, #612] ; (800121c ) 8000fb8: 681b ldr r3, [r3, #0] 8000fba: f403 3300 and.w r3, r3, #131072 ; 0x20000 8000fbe: 2b00 cmp r3, #0 8000fc0: d05b beq.n 800107a 8000fc2: 687b ldr r3, [r7, #4] 8000fc4: 685b ldr r3, [r3, #4] 8000fc6: 2b00 cmp r3, #0 8000fc8: d157 bne.n 800107a { return HAL_ERROR; 8000fca: 2301 movs r3, #1 8000fcc: e20b b.n 80013e6 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8000fce: 687b ldr r3, [r7, #4] 8000fd0: 685b ldr r3, [r3, #4] 8000fd2: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8000fd6: d106 bne.n 8000fe6 8000fd8: 4b90 ldr r3, [pc, #576] ; (800121c ) 8000fda: 681b ldr r3, [r3, #0] 8000fdc: 4a8f ldr r2, [pc, #572] ; (800121c ) 8000fde: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8000fe2: 6013 str r3, [r2, #0] 8000fe4: e01d b.n 8001022 8000fe6: 687b ldr r3, [r7, #4] 8000fe8: 685b ldr r3, [r3, #4] 8000fea: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 8000fee: d10c bne.n 800100a 8000ff0: 4b8a ldr r3, [pc, #552] ; (800121c ) 8000ff2: 681b ldr r3, [r3, #0] 8000ff4: 4a89 ldr r2, [pc, #548] ; (800121c ) 8000ff6: f443 2380 orr.w r3, r3, #262144 ; 0x40000 8000ffa: 6013 str r3, [r2, #0] 8000ffc: 4b87 ldr r3, [pc, #540] ; (800121c ) 8000ffe: 681b ldr r3, [r3, #0] 8001000: 4a86 ldr r2, [pc, #536] ; (800121c ) 8001002: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8001006: 6013 str r3, [r2, #0] 8001008: e00b b.n 8001022 800100a: 4b84 ldr r3, [pc, #528] ; (800121c ) 800100c: 681b ldr r3, [r3, #0] 800100e: 4a83 ldr r2, [pc, #524] ; (800121c ) 8001010: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8001014: 6013 str r3, [r2, #0] 8001016: 4b81 ldr r3, [pc, #516] ; (800121c ) 8001018: 681b ldr r3, [r3, #0] 800101a: 4a80 ldr r2, [pc, #512] ; (800121c ) 800101c: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8001020: 6013 str r3, [r2, #0] /* Check the HSE State */ if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF) 8001022: 687b ldr r3, [r7, #4] 8001024: 685b ldr r3, [r3, #4] 8001026: 2b00 cmp r3, #0 8001028: d013 beq.n 8001052 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800102a: f7ff fad3 bl 80005d4 800102e: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8001030: e008 b.n 8001044 { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 8001032: f7ff facf bl 80005d4 8001036: 4602 mov r2, r0 8001038: 693b ldr r3, [r7, #16] 800103a: 1ad3 subs r3, r2, r3 800103c: 2b64 cmp r3, #100 ; 0x64 800103e: d901 bls.n 8001044 { return HAL_TIMEOUT; 8001040: 2303 movs r3, #3 8001042: e1d0 b.n 80013e6 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8001044: 4b75 ldr r3, [pc, #468] ; (800121c ) 8001046: 681b ldr r3, [r3, #0] 8001048: f403 3300 and.w r3, r3, #131072 ; 0x20000 800104c: 2b00 cmp r3, #0 800104e: d0f0 beq.n 8001032 8001050: e014 b.n 800107c } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8001052: f7ff fabf bl 80005d4 8001056: 6138 str r0, [r7, #16] /* Wait till HSE is bypassed or disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8001058: e008 b.n 800106c { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 800105a: f7ff fabb bl 80005d4 800105e: 4602 mov r2, r0 8001060: 693b ldr r3, [r7, #16] 8001062: 1ad3 subs r3, r2, r3 8001064: 2b64 cmp r3, #100 ; 0x64 8001066: d901 bls.n 800106c { return HAL_TIMEOUT; 8001068: 2303 movs r3, #3 800106a: e1bc b.n 80013e6 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 800106c: 4b6b ldr r3, [pc, #428] ; (800121c ) 800106e: 681b ldr r3, [r3, #0] 8001070: f403 3300 and.w r3, r3, #131072 ; 0x20000 8001074: 2b00 cmp r3, #0 8001076: d1f0 bne.n 800105a 8001078: e000 b.n 800107c if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 800107a: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 800107c: 687b ldr r3, [r7, #4] 800107e: 681b ldr r3, [r3, #0] 8001080: f003 0302 and.w r3, r3, #2 8001084: 2b00 cmp r3, #0 8001086: d063 beq.n 8001150 #if defined(STM32F446xx) if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) ||\ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) #else if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\ 8001088: 4b64 ldr r3, [pc, #400] ; (800121c ) 800108a: 689b ldr r3, [r3, #8] 800108c: f003 030c and.w r3, r3, #12 8001090: 2b00 cmp r3, #0 8001092: d00b beq.n 80010ac ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) 8001094: 4b61 ldr r3, [pc, #388] ; (800121c ) 8001096: 689b ldr r3, [r3, #8] 8001098: f003 030c and.w r3, r3, #12 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\ 800109c: 2b08 cmp r3, #8 800109e: d11c bne.n 80010da ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) 80010a0: 4b5e ldr r3, [pc, #376] ; (800121c ) 80010a2: 685b ldr r3, [r3, #4] 80010a4: f403 0380 and.w r3, r3, #4194304 ; 0x400000 80010a8: 2b00 cmp r3, #0 80010aa: d116 bne.n 80010da #endif /* STM32F446xx */ { /* When HSI is used as system clock it will not disabled */ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 80010ac: 4b5b ldr r3, [pc, #364] ; (800121c ) 80010ae: 681b ldr r3, [r3, #0] 80010b0: f003 0302 and.w r3, r3, #2 80010b4: 2b00 cmp r3, #0 80010b6: d005 beq.n 80010c4 80010b8: 687b ldr r3, [r7, #4] 80010ba: 68db ldr r3, [r3, #12] 80010bc: 2b01 cmp r3, #1 80010be: d001 beq.n 80010c4 { return HAL_ERROR; 80010c0: 2301 movs r3, #1 80010c2: e190 b.n 80013e6 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 80010c4: 4b55 ldr r3, [pc, #340] ; (800121c ) 80010c6: 681b ldr r3, [r3, #0] 80010c8: f023 02f8 bic.w r2, r3, #248 ; 0xf8 80010cc: 687b ldr r3, [r7, #4] 80010ce: 691b ldr r3, [r3, #16] 80010d0: 00db lsls r3, r3, #3 80010d2: 4952 ldr r1, [pc, #328] ; (800121c ) 80010d4: 4313 orrs r3, r2 80010d6: 600b str r3, [r1, #0] if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 80010d8: e03a b.n 8001150 } } else { /* Check the HSI State */ if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF) 80010da: 687b ldr r3, [r7, #4] 80010dc: 68db ldr r3, [r3, #12] 80010de: 2b00 cmp r3, #0 80010e0: d020 beq.n 8001124 { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 80010e2: 4b4f ldr r3, [pc, #316] ; (8001220 ) 80010e4: 2201 movs r2, #1 80010e6: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80010e8: f7ff fa74 bl 80005d4 80010ec: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 80010ee: e008 b.n 8001102 { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 80010f0: f7ff fa70 bl 80005d4 80010f4: 4602 mov r2, r0 80010f6: 693b ldr r3, [r7, #16] 80010f8: 1ad3 subs r3, r2, r3 80010fa: 2b02 cmp r3, #2 80010fc: d901 bls.n 8001102 { return HAL_TIMEOUT; 80010fe: 2303 movs r3, #3 8001100: e171 b.n 80013e6 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8001102: 4b46 ldr r3, [pc, #280] ; (800121c ) 8001104: 681b ldr r3, [r3, #0] 8001106: f003 0302 and.w r3, r3, #2 800110a: 2b00 cmp r3, #0 800110c: d0f0 beq.n 80010f0 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800110e: 4b43 ldr r3, [pc, #268] ; (800121c ) 8001110: 681b ldr r3, [r3, #0] 8001112: f023 02f8 bic.w r2, r3, #248 ; 0xf8 8001116: 687b ldr r3, [r7, #4] 8001118: 691b ldr r3, [r3, #16] 800111a: 00db lsls r3, r3, #3 800111c: 493f ldr r1, [pc, #252] ; (800121c ) 800111e: 4313 orrs r3, r2 8001120: 600b str r3, [r1, #0] 8001122: e015 b.n 8001150 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8001124: 4b3e ldr r3, [pc, #248] ; (8001220 ) 8001126: 2200 movs r2, #0 8001128: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800112a: f7ff fa53 bl 80005d4 800112e: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8001130: e008 b.n 8001144 { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 8001132: f7ff fa4f bl 80005d4 8001136: 4602 mov r2, r0 8001138: 693b ldr r3, [r7, #16] 800113a: 1ad3 subs r3, r2, r3 800113c: 2b02 cmp r3, #2 800113e: d901 bls.n 8001144 { return HAL_TIMEOUT; 8001140: 2303 movs r3, #3 8001142: e150 b.n 80013e6 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8001144: 4b35 ldr r3, [pc, #212] ; (800121c ) 8001146: 681b ldr r3, [r3, #0] 8001148: f003 0302 and.w r3, r3, #2 800114c: 2b00 cmp r3, #0 800114e: d1f0 bne.n 8001132 } } } } /*------------------------------ LSI Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8001150: 687b ldr r3, [r7, #4] 8001152: 681b ldr r3, [r3, #0] 8001154: f003 0308 and.w r3, r3, #8 8001158: 2b00 cmp r3, #0 800115a: d030 beq.n 80011be { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF) 800115c: 687b ldr r3, [r7, #4] 800115e: 695b ldr r3, [r3, #20] 8001160: 2b00 cmp r3, #0 8001162: d016 beq.n 8001192 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8001164: 4b2f ldr r3, [pc, #188] ; (8001224 ) 8001166: 2201 movs r2, #1 8001168: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800116a: f7ff fa33 bl 80005d4 800116e: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8001170: e008 b.n 8001184 { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 8001172: f7ff fa2f bl 80005d4 8001176: 4602 mov r2, r0 8001178: 693b ldr r3, [r7, #16] 800117a: 1ad3 subs r3, r2, r3 800117c: 2b02 cmp r3, #2 800117e: d901 bls.n 8001184 { return HAL_TIMEOUT; 8001180: 2303 movs r3, #3 8001182: e130 b.n 80013e6 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8001184: 4b25 ldr r3, [pc, #148] ; (800121c ) 8001186: 6f5b ldr r3, [r3, #116] ; 0x74 8001188: f003 0302 and.w r3, r3, #2 800118c: 2b00 cmp r3, #0 800118e: d0f0 beq.n 8001172 8001190: e015 b.n 80011be } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8001192: 4b24 ldr r3, [pc, #144] ; (8001224 ) 8001194: 2200 movs r2, #0 8001196: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8001198: f7ff fa1c bl 80005d4 800119c: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 800119e: e008 b.n 80011b2 { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 80011a0: f7ff fa18 bl 80005d4 80011a4: 4602 mov r2, r0 80011a6: 693b ldr r3, [r7, #16] 80011a8: 1ad3 subs r3, r2, r3 80011aa: 2b02 cmp r3, #2 80011ac: d901 bls.n 80011b2 { return HAL_TIMEOUT; 80011ae: 2303 movs r3, #3 80011b0: e119 b.n 80013e6 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 80011b2: 4b1a ldr r3, [pc, #104] ; (800121c ) 80011b4: 6f5b ldr r3, [r3, #116] ; 0x74 80011b6: f003 0302 and.w r3, r3, #2 80011ba: 2b00 cmp r3, #0 80011bc: d1f0 bne.n 80011a0 } } } } /*------------------------------ LSE Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 80011be: 687b ldr r3, [r7, #4] 80011c0: 681b ldr r3, [r3, #0] 80011c2: f003 0304 and.w r3, r3, #4 80011c6: 2b00 cmp r3, #0 80011c8: f000 809f beq.w 800130a { FlagStatus pwrclkchanged = RESET; 80011cc: 2300 movs r3, #0 80011ce: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if(__HAL_RCC_PWR_IS_CLK_DISABLED()) 80011d0: 4b12 ldr r3, [pc, #72] ; (800121c ) 80011d2: 6c1b ldr r3, [r3, #64] ; 0x40 80011d4: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 80011d8: 2b00 cmp r3, #0 80011da: d10f bne.n 80011fc { __HAL_RCC_PWR_CLK_ENABLE(); 80011dc: 2300 movs r3, #0 80011de: 60fb str r3, [r7, #12] 80011e0: 4b0e ldr r3, [pc, #56] ; (800121c ) 80011e2: 6c1b ldr r3, [r3, #64] ; 0x40 80011e4: 4a0d ldr r2, [pc, #52] ; (800121c ) 80011e6: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 80011ea: 6413 str r3, [r2, #64] ; 0x40 80011ec: 4b0b ldr r3, [pc, #44] ; (800121c ) 80011ee: 6c1b ldr r3, [r3, #64] ; 0x40 80011f0: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 80011f4: 60fb str r3, [r7, #12] 80011f6: 68fb ldr r3, [r7, #12] pwrclkchanged = SET; 80011f8: 2301 movs r3, #1 80011fa: 75fb strb r3, [r7, #23] } if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80011fc: 4b0a ldr r3, [pc, #40] ; (8001228 ) 80011fe: 681b ldr r3, [r3, #0] 8001200: f403 7380 and.w r3, r3, #256 ; 0x100 8001204: 2b00 cmp r3, #0 8001206: d120 bne.n 800124a { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8001208: 4b07 ldr r3, [pc, #28] ; (8001228 ) 800120a: 681b ldr r3, [r3, #0] 800120c: 4a06 ldr r2, [pc, #24] ; (8001228 ) 800120e: f443 7380 orr.w r3, r3, #256 ; 0x100 8001212: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8001214: f7ff f9de bl 80005d4 8001218: 6138 str r0, [r7, #16] while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 800121a: e010 b.n 800123e 800121c: 40023800 .word 0x40023800 8001220: 42470000 .word 0x42470000 8001224: 42470e80 .word 0x42470e80 8001228: 40007000 .word 0x40007000 { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 800122c: f7ff f9d2 bl 80005d4 8001230: 4602 mov r2, r0 8001232: 693b ldr r3, [r7, #16] 8001234: 1ad3 subs r3, r2, r3 8001236: 2b02 cmp r3, #2 8001238: d901 bls.n 800123e { return HAL_TIMEOUT; 800123a: 2303 movs r3, #3 800123c: e0d3 b.n 80013e6 while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 800123e: 4b6c ldr r3, [pc, #432] ; (80013f0 ) 8001240: 681b ldr r3, [r3, #0] 8001242: f403 7380 and.w r3, r3, #256 ; 0x100 8001246: 2b00 cmp r3, #0 8001248: d0f0 beq.n 800122c } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 800124a: 687b ldr r3, [r7, #4] 800124c: 689b ldr r3, [r3, #8] 800124e: 2b01 cmp r3, #1 8001250: d106 bne.n 8001260 8001252: 4b68 ldr r3, [pc, #416] ; (80013f4 ) 8001254: 6f1b ldr r3, [r3, #112] ; 0x70 8001256: 4a67 ldr r2, [pc, #412] ; (80013f4 ) 8001258: f043 0301 orr.w r3, r3, #1 800125c: 6713 str r3, [r2, #112] ; 0x70 800125e: e01c b.n 800129a 8001260: 687b ldr r3, [r7, #4] 8001262: 689b ldr r3, [r3, #8] 8001264: 2b05 cmp r3, #5 8001266: d10c bne.n 8001282 8001268: 4b62 ldr r3, [pc, #392] ; (80013f4 ) 800126a: 6f1b ldr r3, [r3, #112] ; 0x70 800126c: 4a61 ldr r2, [pc, #388] ; (80013f4 ) 800126e: f043 0304 orr.w r3, r3, #4 8001272: 6713 str r3, [r2, #112] ; 0x70 8001274: 4b5f ldr r3, [pc, #380] ; (80013f4 ) 8001276: 6f1b ldr r3, [r3, #112] ; 0x70 8001278: 4a5e ldr r2, [pc, #376] ; (80013f4 ) 800127a: f043 0301 orr.w r3, r3, #1 800127e: 6713 str r3, [r2, #112] ; 0x70 8001280: e00b b.n 800129a 8001282: 4b5c ldr r3, [pc, #368] ; (80013f4 ) 8001284: 6f1b ldr r3, [r3, #112] ; 0x70 8001286: 4a5b ldr r2, [pc, #364] ; (80013f4 ) 8001288: f023 0301 bic.w r3, r3, #1 800128c: 6713 str r3, [r2, #112] ; 0x70 800128e: 4b59 ldr r3, [pc, #356] ; (80013f4 ) 8001290: 6f1b ldr r3, [r3, #112] ; 0x70 8001292: 4a58 ldr r2, [pc, #352] ; (80013f4 ) 8001294: f023 0304 bic.w r3, r3, #4 8001298: 6713 str r3, [r2, #112] ; 0x70 /* Check the LSE State */ if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) 800129a: 687b ldr r3, [r7, #4] 800129c: 689b ldr r3, [r3, #8] 800129e: 2b00 cmp r3, #0 80012a0: d015 beq.n 80012ce { /* Get Start Tick*/ tickstart = HAL_GetTick(); 80012a2: f7ff f997 bl 80005d4 80012a6: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80012a8: e00a b.n 80012c0 { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 80012aa: f7ff f993 bl 80005d4 80012ae: 4602 mov r2, r0 80012b0: 693b ldr r3, [r7, #16] 80012b2: 1ad3 subs r3, r2, r3 80012b4: f241 3288 movw r2, #5000 ; 0x1388 80012b8: 4293 cmp r3, r2 80012ba: d901 bls.n 80012c0 { return HAL_TIMEOUT; 80012bc: 2303 movs r3, #3 80012be: e092 b.n 80013e6 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80012c0: 4b4c ldr r3, [pc, #304] ; (80013f4 ) 80012c2: 6f1b ldr r3, [r3, #112] ; 0x70 80012c4: f003 0302 and.w r3, r3, #2 80012c8: 2b00 cmp r3, #0 80012ca: d0ee beq.n 80012aa 80012cc: e014 b.n 80012f8 } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 80012ce: f7ff f981 bl 80005d4 80012d2: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 80012d4: e00a b.n 80012ec { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 80012d6: f7ff f97d bl 80005d4 80012da: 4602 mov r2, r0 80012dc: 693b ldr r3, [r7, #16] 80012de: 1ad3 subs r3, r2, r3 80012e0: f241 3288 movw r2, #5000 ; 0x1388 80012e4: 4293 cmp r3, r2 80012e6: d901 bls.n 80012ec { return HAL_TIMEOUT; 80012e8: 2303 movs r3, #3 80012ea: e07c b.n 80013e6 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 80012ec: 4b41 ldr r3, [pc, #260] ; (80013f4 ) 80012ee: 6f1b ldr r3, [r3, #112] ; 0x70 80012f0: f003 0302 and.w r3, r3, #2 80012f4: 2b00 cmp r3, #0 80012f6: d1ee bne.n 80012d6 } } } /* Restore clock configuration if changed */ if(pwrclkchanged == SET) 80012f8: 7dfb ldrb r3, [r7, #23] 80012fa: 2b01 cmp r3, #1 80012fc: d105 bne.n 800130a { __HAL_RCC_PWR_CLK_DISABLE(); 80012fe: 4b3d ldr r3, [pc, #244] ; (80013f4 ) 8001300: 6c1b ldr r3, [r3, #64] ; 0x40 8001302: 4a3c ldr r2, [pc, #240] ; (80013f4 ) 8001304: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 8001308: 6413 str r3, [r2, #64] ; 0x40 } } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 800130a: 687b ldr r3, [r7, #4] 800130c: 699b ldr r3, [r3, #24] 800130e: 2b00 cmp r3, #0 8001310: d068 beq.n 80013e4 { /* Check if the PLL is used as system clock or not */ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) 8001312: 4b38 ldr r3, [pc, #224] ; (80013f4 ) 8001314: 689b ldr r3, [r3, #8] 8001316: f003 030c and.w r3, r3, #12 800131a: 2b08 cmp r3, #8 800131c: d060 beq.n 80013e0 { if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 800131e: 687b ldr r3, [r7, #4] 8001320: 699b ldr r3, [r3, #24] 8001322: 2b02 cmp r3, #2 8001324: d145 bne.n 80013b2 assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8001326: 4b34 ldr r3, [pc, #208] ; (80013f8 ) 8001328: 2200 movs r2, #0 800132a: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800132c: f7ff f952 bl 80005d4 8001330: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8001332: e008 b.n 8001346 { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8001334: f7ff f94e bl 80005d4 8001338: 4602 mov r2, r0 800133a: 693b ldr r3, [r7, #16] 800133c: 1ad3 subs r3, r2, r3 800133e: 2b02 cmp r3, #2 8001340: d901 bls.n 8001346 { return HAL_TIMEOUT; 8001342: 2303 movs r3, #3 8001344: e04f b.n 80013e6 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8001346: 4b2b ldr r3, [pc, #172] ; (80013f4 ) 8001348: 681b ldr r3, [r3, #0] 800134a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 800134e: 2b00 cmp r3, #0 8001350: d1f0 bne.n 8001334 } } /* Configure the main PLL clock source, multiplication and division factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 8001352: 687b ldr r3, [r7, #4] 8001354: 69da ldr r2, [r3, #28] 8001356: 687b ldr r3, [r7, #4] 8001358: 6a1b ldr r3, [r3, #32] 800135a: 431a orrs r2, r3 800135c: 687b ldr r3, [r7, #4] 800135e: 6a5b ldr r3, [r3, #36] ; 0x24 8001360: 019b lsls r3, r3, #6 8001362: 431a orrs r2, r3 8001364: 687b ldr r3, [r7, #4] 8001366: 6a9b ldr r3, [r3, #40] ; 0x28 8001368: 085b lsrs r3, r3, #1 800136a: 3b01 subs r3, #1 800136c: 041b lsls r3, r3, #16 800136e: 431a orrs r2, r3 8001370: 687b ldr r3, [r7, #4] 8001372: 6adb ldr r3, [r3, #44] ; 0x2c 8001374: 061b lsls r3, r3, #24 8001376: 431a orrs r2, r3 8001378: 687b ldr r3, [r7, #4] 800137a: 6b1b ldr r3, [r3, #48] ; 0x30 800137c: 071b lsls r3, r3, #28 800137e: 491d ldr r1, [pc, #116] ; (80013f4 ) 8001380: 4313 orrs r3, r2 8001382: 604b str r3, [r1, #4] RCC_OscInitStruct->PLL.PLLP, RCC_OscInitStruct->PLL.PLLQ, RCC_OscInitStruct->PLL.PLLR); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 8001384: 4b1c ldr r3, [pc, #112] ; (80013f8 ) 8001386: 2201 movs r2, #1 8001388: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800138a: f7ff f923 bl 80005d4 800138e: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8001390: e008 b.n 80013a4 { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8001392: f7ff f91f bl 80005d4 8001396: 4602 mov r2, r0 8001398: 693b ldr r3, [r7, #16] 800139a: 1ad3 subs r3, r2, r3 800139c: 2b02 cmp r3, #2 800139e: d901 bls.n 80013a4 { return HAL_TIMEOUT; 80013a0: 2303 movs r3, #3 80013a2: e020 b.n 80013e6 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 80013a4: 4b13 ldr r3, [pc, #76] ; (80013f4 ) 80013a6: 681b ldr r3, [r3, #0] 80013a8: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 80013ac: 2b00 cmp r3, #0 80013ae: d0f0 beq.n 8001392 80013b0: e018 b.n 80013e4 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 80013b2: 4b11 ldr r3, [pc, #68] ; (80013f8 ) 80013b4: 2200 movs r2, #0 80013b6: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80013b8: f7ff f90c bl 80005d4 80013bc: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80013be: e008 b.n 80013d2 { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 80013c0: f7ff f908 bl 80005d4 80013c4: 4602 mov r2, r0 80013c6: 693b ldr r3, [r7, #16] 80013c8: 1ad3 subs r3, r2, r3 80013ca: 2b02 cmp r3, #2 80013cc: d901 bls.n 80013d2 { return HAL_TIMEOUT; 80013ce: 2303 movs r3, #3 80013d0: e009 b.n 80013e6 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80013d2: 4b08 ldr r3, [pc, #32] ; (80013f4 ) 80013d4: 681b ldr r3, [r3, #0] 80013d6: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 80013da: 2b00 cmp r3, #0 80013dc: d1f0 bne.n 80013c0 80013de: e001 b.n 80013e4 } } } else { return HAL_ERROR; 80013e0: 2301 movs r3, #1 80013e2: e000 b.n 80013e6 } } return HAL_OK; 80013e4: 2300 movs r3, #0 } 80013e6: 4618 mov r0, r3 80013e8: 3718 adds r7, #24 80013ea: 46bd mov sp, r7 80013ec: bd80 pop {r7, pc} 80013ee: bf00 nop 80013f0: 40007000 .word 0x40007000 80013f4: 40023800 .word 0x40023800 80013f8: 42470060 .word 0x42470060 080013fc : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 80013fc: b580 push {r7, lr} 80013fe: b082 sub sp, #8 8001400: af00 add r7, sp, #0 8001402: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 8001404: 687b ldr r3, [r7, #4] 8001406: 2b00 cmp r3, #0 8001408: d101 bne.n 800140e { return HAL_ERROR; 800140a: 2301 movs r3, #1 800140c: e03f b.n 800148e assert_param(IS_UART_INSTANCE(huart->Instance)); } assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); if (huart->gState == HAL_UART_STATE_RESET) 800140e: 687b ldr r3, [r7, #4] 8001410: f893 3039 ldrb.w r3, [r3, #57] ; 0x39 8001414: b2db uxtb r3, r3 8001416: 2b00 cmp r3, #0 8001418: d106 bne.n 8001428 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 800141a: 687b ldr r3, [r7, #4] 800141c: 2200 movs r2, #0 800141e: f883 2038 strb.w r2, [r3, #56] ; 0x38 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 8001422: 6878 ldr r0, [r7, #4] 8001424: f000 ff2e bl 8002284 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 8001428: 687b ldr r3, [r7, #4] 800142a: 2224 movs r2, #36 ; 0x24 800142c: f883 2039 strb.w r2, [r3, #57] ; 0x39 /* Disable the peripheral */ __HAL_UART_DISABLE(huart); 8001430: 687b ldr r3, [r7, #4] 8001432: 681b ldr r3, [r3, #0] 8001434: 68da ldr r2, [r3, #12] 8001436: 687b ldr r3, [r7, #4] 8001438: 681b ldr r3, [r3, #0] 800143a: f422 5200 bic.w r2, r2, #8192 ; 0x2000 800143e: 60da str r2, [r3, #12] /* Set the UART Communication parameters */ UART_SetConfig(huart); 8001440: 6878 ldr r0, [r7, #4] 8001442: f000 f90b bl 800165c /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 8001446: 687b ldr r3, [r7, #4] 8001448: 681b ldr r3, [r3, #0] 800144a: 691a ldr r2, [r3, #16] 800144c: 687b ldr r3, [r7, #4] 800144e: 681b ldr r3, [r3, #0] 8001450: f422 4290 bic.w r2, r2, #18432 ; 0x4800 8001454: 611a str r2, [r3, #16] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 8001456: 687b ldr r3, [r7, #4] 8001458: 681b ldr r3, [r3, #0] 800145a: 695a ldr r2, [r3, #20] 800145c: 687b ldr r3, [r7, #4] 800145e: 681b ldr r3, [r3, #0] 8001460: f022 022a bic.w r2, r2, #42 ; 0x2a 8001464: 615a str r2, [r3, #20] /* Enable the peripheral */ __HAL_UART_ENABLE(huart); 8001466: 687b ldr r3, [r7, #4] 8001468: 681b ldr r3, [r3, #0] 800146a: 68da ldr r2, [r3, #12] 800146c: 687b ldr r3, [r7, #4] 800146e: 681b ldr r3, [r3, #0] 8001470: f442 5200 orr.w r2, r2, #8192 ; 0x2000 8001474: 60da str r2, [r3, #12] /* Initialize the UART state */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8001476: 687b ldr r3, [r7, #4] 8001478: 2200 movs r2, #0 800147a: 63da str r2, [r3, #60] ; 0x3c huart->gState = HAL_UART_STATE_READY; 800147c: 687b ldr r3, [r7, #4] 800147e: 2220 movs r2, #32 8001480: f883 2039 strb.w r2, [r3, #57] ; 0x39 huart->RxState = HAL_UART_STATE_READY; 8001484: 687b ldr r3, [r7, #4] 8001486: 2220 movs r2, #32 8001488: f883 203a strb.w r2, [r3, #58] ; 0x3a return HAL_OK; 800148c: 2300 movs r3, #0 } 800148e: 4618 mov r0, r3 8001490: 3708 adds r7, #8 8001492: 46bd mov sp, r7 8001494: bd80 pop {r7, pc} 08001496 : * @param Size Amount of data to be sent * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) { 8001496: b580 push {r7, lr} 8001498: b088 sub sp, #32 800149a: af02 add r7, sp, #8 800149c: 60f8 str r0, [r7, #12] 800149e: 60b9 str r1, [r7, #8] 80014a0: 603b str r3, [r7, #0] 80014a2: 4613 mov r3, r2 80014a4: 80fb strh r3, [r7, #6] uint16_t *tmp; uint32_t tickstart = 0U; 80014a6: 2300 movs r3, #0 80014a8: 617b str r3, [r7, #20] /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 80014aa: 68fb ldr r3, [r7, #12] 80014ac: f893 3039 ldrb.w r3, [r3, #57] ; 0x39 80014b0: b2db uxtb r3, r3 80014b2: 2b20 cmp r3, #32 80014b4: f040 8083 bne.w 80015be { if ((pData == NULL) || (Size == 0U)) 80014b8: 68bb ldr r3, [r7, #8] 80014ba: 2b00 cmp r3, #0 80014bc: d002 beq.n 80014c4 80014be: 88fb ldrh r3, [r7, #6] 80014c0: 2b00 cmp r3, #0 80014c2: d101 bne.n 80014c8 { return HAL_ERROR; 80014c4: 2301 movs r3, #1 80014c6: e07b b.n 80015c0 } /* Process Locked */ __HAL_LOCK(huart); 80014c8: 68fb ldr r3, [r7, #12] 80014ca: f893 3038 ldrb.w r3, [r3, #56] ; 0x38 80014ce: 2b01 cmp r3, #1 80014d0: d101 bne.n 80014d6 80014d2: 2302 movs r3, #2 80014d4: e074 b.n 80015c0 80014d6: 68fb ldr r3, [r7, #12] 80014d8: 2201 movs r2, #1 80014da: f883 2038 strb.w r2, [r3, #56] ; 0x38 huart->ErrorCode = HAL_UART_ERROR_NONE; 80014de: 68fb ldr r3, [r7, #12] 80014e0: 2200 movs r2, #0 80014e2: 63da str r2, [r3, #60] ; 0x3c huart->gState = HAL_UART_STATE_BUSY_TX; 80014e4: 68fb ldr r3, [r7, #12] 80014e6: 2221 movs r2, #33 ; 0x21 80014e8: f883 2039 strb.w r2, [r3, #57] ; 0x39 /* Init tickstart for timeout managment */ tickstart = HAL_GetTick(); 80014ec: f7ff f872 bl 80005d4 80014f0: 6178 str r0, [r7, #20] huart->TxXferSize = Size; 80014f2: 68fb ldr r3, [r7, #12] 80014f4: 88fa ldrh r2, [r7, #6] 80014f6: 849a strh r2, [r3, #36] ; 0x24 huart->TxXferCount = Size; 80014f8: 68fb ldr r3, [r7, #12] 80014fa: 88fa ldrh r2, [r7, #6] 80014fc: 84da strh r2, [r3, #38] ; 0x26 while (huart->TxXferCount > 0U) 80014fe: e042 b.n 8001586 { huart->TxXferCount--; 8001500: 68fb ldr r3, [r7, #12] 8001502: 8cdb ldrh r3, [r3, #38] ; 0x26 8001504: b29b uxth r3, r3 8001506: 3b01 subs r3, #1 8001508: b29a uxth r2, r3 800150a: 68fb ldr r3, [r7, #12] 800150c: 84da strh r2, [r3, #38] ; 0x26 if (huart->Init.WordLength == UART_WORDLENGTH_9B) 800150e: 68fb ldr r3, [r7, #12] 8001510: 689b ldr r3, [r3, #8] 8001512: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8001516: d122 bne.n 800155e { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) 8001518: 683b ldr r3, [r7, #0] 800151a: 9300 str r3, [sp, #0] 800151c: 697b ldr r3, [r7, #20] 800151e: 2200 movs r2, #0 8001520: 2180 movs r1, #128 ; 0x80 8001522: 68f8 ldr r0, [r7, #12] 8001524: f000 f850 bl 80015c8 8001528: 4603 mov r3, r0 800152a: 2b00 cmp r3, #0 800152c: d001 beq.n 8001532 { return HAL_TIMEOUT; 800152e: 2303 movs r3, #3 8001530: e046 b.n 80015c0 } tmp = (uint16_t *) pData; 8001532: 68bb ldr r3, [r7, #8] 8001534: 613b str r3, [r7, #16] huart->Instance->DR = (*tmp & (uint16_t)0x01FF); 8001536: 693b ldr r3, [r7, #16] 8001538: 881b ldrh r3, [r3, #0] 800153a: 461a mov r2, r3 800153c: 68fb ldr r3, [r7, #12] 800153e: 681b ldr r3, [r3, #0] 8001540: f3c2 0208 ubfx r2, r2, #0, #9 8001544: 605a str r2, [r3, #4] if (huart->Init.Parity == UART_PARITY_NONE) 8001546: 68fb ldr r3, [r7, #12] 8001548: 691b ldr r3, [r3, #16] 800154a: 2b00 cmp r3, #0 800154c: d103 bne.n 8001556 { pData += 2U; 800154e: 68bb ldr r3, [r7, #8] 8001550: 3302 adds r3, #2 8001552: 60bb str r3, [r7, #8] 8001554: e017 b.n 8001586 } else { pData += 1U; 8001556: 68bb ldr r3, [r7, #8] 8001558: 3301 adds r3, #1 800155a: 60bb str r3, [r7, #8] 800155c: e013 b.n 8001586 } } else { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) 800155e: 683b ldr r3, [r7, #0] 8001560: 9300 str r3, [sp, #0] 8001562: 697b ldr r3, [r7, #20] 8001564: 2200 movs r2, #0 8001566: 2180 movs r1, #128 ; 0x80 8001568: 68f8 ldr r0, [r7, #12] 800156a: f000 f82d bl 80015c8 800156e: 4603 mov r3, r0 8001570: 2b00 cmp r3, #0 8001572: d001 beq.n 8001578 { return HAL_TIMEOUT; 8001574: 2303 movs r3, #3 8001576: e023 b.n 80015c0 } huart->Instance->DR = (*pData++ & (uint8_t)0xFF); 8001578: 68bb ldr r3, [r7, #8] 800157a: 1c5a adds r2, r3, #1 800157c: 60ba str r2, [r7, #8] 800157e: 781a ldrb r2, [r3, #0] 8001580: 68fb ldr r3, [r7, #12] 8001582: 681b ldr r3, [r3, #0] 8001584: 605a str r2, [r3, #4] while (huart->TxXferCount > 0U) 8001586: 68fb ldr r3, [r7, #12] 8001588: 8cdb ldrh r3, [r3, #38] ; 0x26 800158a: b29b uxth r3, r3 800158c: 2b00 cmp r3, #0 800158e: d1b7 bne.n 8001500 } } if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) 8001590: 683b ldr r3, [r7, #0] 8001592: 9300 str r3, [sp, #0] 8001594: 697b ldr r3, [r7, #20] 8001596: 2200 movs r2, #0 8001598: 2140 movs r1, #64 ; 0x40 800159a: 68f8 ldr r0, [r7, #12] 800159c: f000 f814 bl 80015c8 80015a0: 4603 mov r3, r0 80015a2: 2b00 cmp r3, #0 80015a4: d001 beq.n 80015aa { return HAL_TIMEOUT; 80015a6: 2303 movs r3, #3 80015a8: e00a b.n 80015c0 } /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 80015aa: 68fb ldr r3, [r7, #12] 80015ac: 2220 movs r2, #32 80015ae: f883 2039 strb.w r2, [r3, #57] ; 0x39 /* Process Unlocked */ __HAL_UNLOCK(huart); 80015b2: 68fb ldr r3, [r7, #12] 80015b4: 2200 movs r2, #0 80015b6: f883 2038 strb.w r2, [r3, #56] ; 0x38 return HAL_OK; 80015ba: 2300 movs r3, #0 80015bc: e000 b.n 80015c0 } else { return HAL_BUSY; 80015be: 2302 movs r3, #2 } } 80015c0: 4618 mov r0, r3 80015c2: 3718 adds r7, #24 80015c4: 46bd mov sp, r7 80015c6: bd80 pop {r7, pc} 080015c8 : * @param Tickstart Tick start value * @param Timeout Timeout duration * @retval HAL status */ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { 80015c8: b580 push {r7, lr} 80015ca: b084 sub sp, #16 80015cc: af00 add r7, sp, #0 80015ce: 60f8 str r0, [r7, #12] 80015d0: 60b9 str r1, [r7, #8] 80015d2: 603b str r3, [r7, #0] 80015d4: 4613 mov r3, r2 80015d6: 71fb strb r3, [r7, #7] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 80015d8: e02c b.n 8001634 { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 80015da: 69bb ldr r3, [r7, #24] 80015dc: f1b3 3fff cmp.w r3, #4294967295 80015e0: d028 beq.n 8001634 { if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) 80015e2: 69bb ldr r3, [r7, #24] 80015e4: 2b00 cmp r3, #0 80015e6: d007 beq.n 80015f8 80015e8: f7fe fff4 bl 80005d4 80015ec: 4602 mov r2, r0 80015ee: 683b ldr r3, [r7, #0] 80015f0: 1ad3 subs r3, r2, r3 80015f2: 69ba ldr r2, [r7, #24] 80015f4: 429a cmp r2, r3 80015f6: d21d bcs.n 8001634 { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); 80015f8: 68fb ldr r3, [r7, #12] 80015fa: 681b ldr r3, [r3, #0] 80015fc: 68da ldr r2, [r3, #12] 80015fe: 68fb ldr r3, [r7, #12] 8001600: 681b ldr r3, [r3, #0] 8001602: f422 72d0 bic.w r2, r2, #416 ; 0x1a0 8001606: 60da str r2, [r3, #12] CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8001608: 68fb ldr r3, [r7, #12] 800160a: 681b ldr r3, [r3, #0] 800160c: 695a ldr r2, [r3, #20] 800160e: 68fb ldr r3, [r7, #12] 8001610: 681b ldr r3, [r3, #0] 8001612: f022 0201 bic.w r2, r2, #1 8001616: 615a str r2, [r3, #20] huart->gState = HAL_UART_STATE_READY; 8001618: 68fb ldr r3, [r7, #12] 800161a: 2220 movs r2, #32 800161c: f883 2039 strb.w r2, [r3, #57] ; 0x39 huart->RxState = HAL_UART_STATE_READY; 8001620: 68fb ldr r3, [r7, #12] 8001622: 2220 movs r2, #32 8001624: f883 203a strb.w r2, [r3, #58] ; 0x3a /* Process Unlocked */ __HAL_UNLOCK(huart); 8001628: 68fb ldr r3, [r7, #12] 800162a: 2200 movs r2, #0 800162c: f883 2038 strb.w r2, [r3, #56] ; 0x38 return HAL_TIMEOUT; 8001630: 2303 movs r3, #3 8001632: e00f b.n 8001654 while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8001634: 68fb ldr r3, [r7, #12] 8001636: 681b ldr r3, [r3, #0] 8001638: 681a ldr r2, [r3, #0] 800163a: 68bb ldr r3, [r7, #8] 800163c: 4013 ands r3, r2 800163e: 68ba ldr r2, [r7, #8] 8001640: 429a cmp r2, r3 8001642: bf0c ite eq 8001644: 2301 moveq r3, #1 8001646: 2300 movne r3, #0 8001648: b2db uxtb r3, r3 800164a: 461a mov r2, r3 800164c: 79fb ldrb r3, [r7, #7] 800164e: 429a cmp r2, r3 8001650: d0c3 beq.n 80015da } } } return HAL_OK; 8001652: 2300 movs r3, #0 } 8001654: 4618 mov r0, r3 8001656: 3710 adds r7, #16 8001658: 46bd mov sp, r7 800165a: bd80 pop {r7, pc} 0800165c : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_SetConfig(UART_HandleTypeDef *huart) { 800165c: b5b0 push {r4, r5, r7, lr} 800165e: b084 sub sp, #16 8001660: af00 add r7, sp, #0 8001662: 6078 str r0, [r7, #4] assert_param(IS_UART_MODE(huart->Init.Mode)); /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 8001664: 687b ldr r3, [r7, #4] 8001666: 681b ldr r3, [r3, #0] 8001668: 691b ldr r3, [r3, #16] 800166a: f423 5140 bic.w r1, r3, #12288 ; 0x3000 800166e: 687b ldr r3, [r7, #4] 8001670: 68da ldr r2, [r3, #12] 8001672: 687b ldr r3, [r7, #4] 8001674: 681b ldr r3, [r3, #0] 8001676: 430a orrs r2, r1 8001678: 611a str r2, [r3, #16] Set the M bits according to huart->Init.WordLength value Set PCE and PS bits according to huart->Init.Parity value Set TE and RE bits according to huart->Init.Mode value Set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; 800167a: 687b ldr r3, [r7, #4] 800167c: 689a ldr r2, [r3, #8] 800167e: 687b ldr r3, [r7, #4] 8001680: 691b ldr r3, [r3, #16] 8001682: 431a orrs r2, r3 8001684: 687b ldr r3, [r7, #4] 8001686: 695b ldr r3, [r3, #20] 8001688: 431a orrs r2, r3 800168a: 687b ldr r3, [r7, #4] 800168c: 69db ldr r3, [r3, #28] 800168e: 4313 orrs r3, r2 8001690: 60fb str r3, [r7, #12] MODIFY_REG(huart->Instance->CR1, 8001692: 687b ldr r3, [r7, #4] 8001694: 681b ldr r3, [r3, #0] 8001696: 68db ldr r3, [r3, #12] 8001698: f423 4316 bic.w r3, r3, #38400 ; 0x9600 800169c: f023 030c bic.w r3, r3, #12 80016a0: 687a ldr r2, [r7, #4] 80016a2: 6812 ldr r2, [r2, #0] 80016a4: 68f9 ldr r1, [r7, #12] 80016a6: 430b orrs r3, r1 80016a8: 60d3 str r3, [r2, #12] (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), tmpreg); /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); 80016aa: 687b ldr r3, [r7, #4] 80016ac: 681b ldr r3, [r3, #0] 80016ae: 695b ldr r3, [r3, #20] 80016b0: f423 7140 bic.w r1, r3, #768 ; 0x300 80016b4: 687b ldr r3, [r7, #4] 80016b6: 699a ldr r2, [r3, #24] 80016b8: 687b ldr r3, [r7, #4] 80016ba: 681b ldr r3, [r3, #0] 80016bc: 430a orrs r2, r1 80016be: 615a str r2, [r3, #20] /* Check the Over Sampling */ if (huart->Init.OverSampling == UART_OVERSAMPLING_8) 80016c0: 687b ldr r3, [r7, #4] 80016c2: 69db ldr r3, [r3, #28] 80016c4: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 80016c8: f040 80e4 bne.w 8001894 { /*-------------------------- USART BRR Configuration ---------------------*/ #if defined(USART6) if ((huart->Instance == USART1) || (huart->Instance == USART6)) 80016cc: 687b ldr r3, [r7, #4] 80016ce: 681b ldr r3, [r3, #0] 80016d0: 4aab ldr r2, [pc, #684] ; (8001980 ) 80016d2: 4293 cmp r3, r2 80016d4: d004 beq.n 80016e0 80016d6: 687b ldr r3, [r7, #4] 80016d8: 681b ldr r3, [r3, #0] 80016da: 4aaa ldr r2, [pc, #680] ; (8001984 ) 80016dc: 4293 cmp r3, r2 80016de: d16c bne.n 80017ba { huart->Instance->BRR = UART_BRR_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate); 80016e0: f7ff fc36 bl 8000f50 80016e4: 4602 mov r2, r0 80016e6: 4613 mov r3, r2 80016e8: 009b lsls r3, r3, #2 80016ea: 4413 add r3, r2 80016ec: 009a lsls r2, r3, #2 80016ee: 441a add r2, r3 80016f0: 687b ldr r3, [r7, #4] 80016f2: 685b ldr r3, [r3, #4] 80016f4: 005b lsls r3, r3, #1 80016f6: fbb2 f3f3 udiv r3, r2, r3 80016fa: 4aa3 ldr r2, [pc, #652] ; (8001988 ) 80016fc: fba2 2303 umull r2, r3, r2, r3 8001700: 095b lsrs r3, r3, #5 8001702: 011c lsls r4, r3, #4 8001704: f7ff fc24 bl 8000f50 8001708: 4602 mov r2, r0 800170a: 4613 mov r3, r2 800170c: 009b lsls r3, r3, #2 800170e: 4413 add r3, r2 8001710: 009a lsls r2, r3, #2 8001712: 441a add r2, r3 8001714: 687b ldr r3, [r7, #4] 8001716: 685b ldr r3, [r3, #4] 8001718: 005b lsls r3, r3, #1 800171a: fbb2 f5f3 udiv r5, r2, r3 800171e: f7ff fc17 bl 8000f50 8001722: 4602 mov r2, r0 8001724: 4613 mov r3, r2 8001726: 009b lsls r3, r3, #2 8001728: 4413 add r3, r2 800172a: 009a lsls r2, r3, #2 800172c: 441a add r2, r3 800172e: 687b ldr r3, [r7, #4] 8001730: 685b ldr r3, [r3, #4] 8001732: 005b lsls r3, r3, #1 8001734: fbb2 f3f3 udiv r3, r2, r3 8001738: 4a93 ldr r2, [pc, #588] ; (8001988 ) 800173a: fba2 2303 umull r2, r3, r2, r3 800173e: 095b lsrs r3, r3, #5 8001740: 2264 movs r2, #100 ; 0x64 8001742: fb02 f303 mul.w r3, r2, r3 8001746: 1aeb subs r3, r5, r3 8001748: 00db lsls r3, r3, #3 800174a: 3332 adds r3, #50 ; 0x32 800174c: 4a8e ldr r2, [pc, #568] ; (8001988 ) 800174e: fba2 2303 umull r2, r3, r2, r3 8001752: 095b lsrs r3, r3, #5 8001754: 005b lsls r3, r3, #1 8001756: f403 73f8 and.w r3, r3, #496 ; 0x1f0 800175a: 441c add r4, r3 800175c: f7ff fbf8 bl 8000f50 8001760: 4602 mov r2, r0 8001762: 4613 mov r3, r2 8001764: 009b lsls r3, r3, #2 8001766: 4413 add r3, r2 8001768: 009a lsls r2, r3, #2 800176a: 441a add r2, r3 800176c: 687b ldr r3, [r7, #4] 800176e: 685b ldr r3, [r3, #4] 8001770: 005b lsls r3, r3, #1 8001772: fbb2 f5f3 udiv r5, r2, r3 8001776: f7ff fbeb bl 8000f50 800177a: 4602 mov r2, r0 800177c: 4613 mov r3, r2 800177e: 009b lsls r3, r3, #2 8001780: 4413 add r3, r2 8001782: 009a lsls r2, r3, #2 8001784: 441a add r2, r3 8001786: 687b ldr r3, [r7, #4] 8001788: 685b ldr r3, [r3, #4] 800178a: 005b lsls r3, r3, #1 800178c: fbb2 f3f3 udiv r3, r2, r3 8001790: 4a7d ldr r2, [pc, #500] ; (8001988 ) 8001792: fba2 2303 umull r2, r3, r2, r3 8001796: 095b lsrs r3, r3, #5 8001798: 2264 movs r2, #100 ; 0x64 800179a: fb02 f303 mul.w r3, r2, r3 800179e: 1aeb subs r3, r5, r3 80017a0: 00db lsls r3, r3, #3 80017a2: 3332 adds r3, #50 ; 0x32 80017a4: 4a78 ldr r2, [pc, #480] ; (8001988 ) 80017a6: fba2 2303 umull r2, r3, r2, r3 80017aa: 095b lsrs r3, r3, #5 80017ac: f003 0207 and.w r2, r3, #7 80017b0: 687b ldr r3, [r7, #4] 80017b2: 681b ldr r3, [r3, #0] 80017b4: 4422 add r2, r4 80017b6: 609a str r2, [r3, #8] 80017b8: e154 b.n 8001a64 huart->Instance->BRR = UART_BRR_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate); } #endif /* USART6 */ else { huart->Instance->BRR = UART_BRR_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate); 80017ba: f7ff fbb5 bl 8000f28 80017be: 4602 mov r2, r0 80017c0: 4613 mov r3, r2 80017c2: 009b lsls r3, r3, #2 80017c4: 4413 add r3, r2 80017c6: 009a lsls r2, r3, #2 80017c8: 441a add r2, r3 80017ca: 687b ldr r3, [r7, #4] 80017cc: 685b ldr r3, [r3, #4] 80017ce: 005b lsls r3, r3, #1 80017d0: fbb2 f3f3 udiv r3, r2, r3 80017d4: 4a6c ldr r2, [pc, #432] ; (8001988 ) 80017d6: fba2 2303 umull r2, r3, r2, r3 80017da: 095b lsrs r3, r3, #5 80017dc: 011c lsls r4, r3, #4 80017de: f7ff fba3 bl 8000f28 80017e2: 4602 mov r2, r0 80017e4: 4613 mov r3, r2 80017e6: 009b lsls r3, r3, #2 80017e8: 4413 add r3, r2 80017ea: 009a lsls r2, r3, #2 80017ec: 441a add r2, r3 80017ee: 687b ldr r3, [r7, #4] 80017f0: 685b ldr r3, [r3, #4] 80017f2: 005b lsls r3, r3, #1 80017f4: fbb2 f5f3 udiv r5, r2, r3 80017f8: f7ff fb96 bl 8000f28 80017fc: 4602 mov r2, r0 80017fe: 4613 mov r3, r2 8001800: 009b lsls r3, r3, #2 8001802: 4413 add r3, r2 8001804: 009a lsls r2, r3, #2 8001806: 441a add r2, r3 8001808: 687b ldr r3, [r7, #4] 800180a: 685b ldr r3, [r3, #4] 800180c: 005b lsls r3, r3, #1 800180e: fbb2 f3f3 udiv r3, r2, r3 8001812: 4a5d ldr r2, [pc, #372] ; (8001988 ) 8001814: fba2 2303 umull r2, r3, r2, r3 8001818: 095b lsrs r3, r3, #5 800181a: 2264 movs r2, #100 ; 0x64 800181c: fb02 f303 mul.w r3, r2, r3 8001820: 1aeb subs r3, r5, r3 8001822: 00db lsls r3, r3, #3 8001824: 3332 adds r3, #50 ; 0x32 8001826: 4a58 ldr r2, [pc, #352] ; (8001988 ) 8001828: fba2 2303 umull r2, r3, r2, r3 800182c: 095b lsrs r3, r3, #5 800182e: 005b lsls r3, r3, #1 8001830: f403 73f8 and.w r3, r3, #496 ; 0x1f0 8001834: 441c add r4, r3 8001836: f7ff fb77 bl 8000f28 800183a: 4602 mov r2, r0 800183c: 4613 mov r3, r2 800183e: 009b lsls r3, r3, #2 8001840: 4413 add r3, r2 8001842: 009a lsls r2, r3, #2 8001844: 441a add r2, r3 8001846: 687b ldr r3, [r7, #4] 8001848: 685b ldr r3, [r3, #4] 800184a: 005b lsls r3, r3, #1 800184c: fbb2 f5f3 udiv r5, r2, r3 8001850: f7ff fb6a bl 8000f28 8001854: 4602 mov r2, r0 8001856: 4613 mov r3, r2 8001858: 009b lsls r3, r3, #2 800185a: 4413 add r3, r2 800185c: 009a lsls r2, r3, #2 800185e: 441a add r2, r3 8001860: 687b ldr r3, [r7, #4] 8001862: 685b ldr r3, [r3, #4] 8001864: 005b lsls r3, r3, #1 8001866: fbb2 f3f3 udiv r3, r2, r3 800186a: 4a47 ldr r2, [pc, #284] ; (8001988 ) 800186c: fba2 2303 umull r2, r3, r2, r3 8001870: 095b lsrs r3, r3, #5 8001872: 2264 movs r2, #100 ; 0x64 8001874: fb02 f303 mul.w r3, r2, r3 8001878: 1aeb subs r3, r5, r3 800187a: 00db lsls r3, r3, #3 800187c: 3332 adds r3, #50 ; 0x32 800187e: 4a42 ldr r2, [pc, #264] ; (8001988 ) 8001880: fba2 2303 umull r2, r3, r2, r3 8001884: 095b lsrs r3, r3, #5 8001886: f003 0207 and.w r2, r3, #7 800188a: 687b ldr r3, [r7, #4] 800188c: 681b ldr r3, [r3, #0] 800188e: 4422 add r2, r4 8001890: 609a str r2, [r3, #8] else { huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate); } } } 8001892: e0e7 b.n 8001a64 if ((huart->Instance == USART1) || (huart->Instance == USART6)) 8001894: 687b ldr r3, [r7, #4] 8001896: 681b ldr r3, [r3, #0] 8001898: 4a39 ldr r2, [pc, #228] ; (8001980 ) 800189a: 4293 cmp r3, r2 800189c: d004 beq.n 80018a8 800189e: 687b ldr r3, [r7, #4] 80018a0: 681b ldr r3, [r3, #0] 80018a2: 4a38 ldr r2, [pc, #224] ; (8001984 ) 80018a4: 4293 cmp r3, r2 80018a6: d171 bne.n 800198c huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate); 80018a8: f7ff fb52 bl 8000f50 80018ac: 4602 mov r2, r0 80018ae: 4613 mov r3, r2 80018b0: 009b lsls r3, r3, #2 80018b2: 4413 add r3, r2 80018b4: 009a lsls r2, r3, #2 80018b6: 441a add r2, r3 80018b8: 687b ldr r3, [r7, #4] 80018ba: 685b ldr r3, [r3, #4] 80018bc: 009b lsls r3, r3, #2 80018be: fbb2 f3f3 udiv r3, r2, r3 80018c2: 4a31 ldr r2, [pc, #196] ; (8001988 ) 80018c4: fba2 2303 umull r2, r3, r2, r3 80018c8: 095b lsrs r3, r3, #5 80018ca: 011c lsls r4, r3, #4 80018cc: f7ff fb40 bl 8000f50 80018d0: 4602 mov r2, r0 80018d2: 4613 mov r3, r2 80018d4: 009b lsls r3, r3, #2 80018d6: 4413 add r3, r2 80018d8: 009a lsls r2, r3, #2 80018da: 441a add r2, r3 80018dc: 687b ldr r3, [r7, #4] 80018de: 685b ldr r3, [r3, #4] 80018e0: 009b lsls r3, r3, #2 80018e2: fbb2 f5f3 udiv r5, r2, r3 80018e6: f7ff fb33 bl 8000f50 80018ea: 4602 mov r2, r0 80018ec: 4613 mov r3, r2 80018ee: 009b lsls r3, r3, #2 80018f0: 4413 add r3, r2 80018f2: 009a lsls r2, r3, #2 80018f4: 441a add r2, r3 80018f6: 687b ldr r3, [r7, #4] 80018f8: 685b ldr r3, [r3, #4] 80018fa: 009b lsls r3, r3, #2 80018fc: fbb2 f3f3 udiv r3, r2, r3 8001900: 4a21 ldr r2, [pc, #132] ; (8001988 ) 8001902: fba2 2303 umull r2, r3, r2, r3 8001906: 095b lsrs r3, r3, #5 8001908: 2264 movs r2, #100 ; 0x64 800190a: fb02 f303 mul.w r3, r2, r3 800190e: 1aeb subs r3, r5, r3 8001910: 011b lsls r3, r3, #4 8001912: 3332 adds r3, #50 ; 0x32 8001914: 4a1c ldr r2, [pc, #112] ; (8001988 ) 8001916: fba2 2303 umull r2, r3, r2, r3 800191a: 095b lsrs r3, r3, #5 800191c: f003 03f0 and.w r3, r3, #240 ; 0xf0 8001920: 441c add r4, r3 8001922: f7ff fb15 bl 8000f50 8001926: 4602 mov r2, r0 8001928: 4613 mov r3, r2 800192a: 009b lsls r3, r3, #2 800192c: 4413 add r3, r2 800192e: 009a lsls r2, r3, #2 8001930: 441a add r2, r3 8001932: 687b ldr r3, [r7, #4] 8001934: 685b ldr r3, [r3, #4] 8001936: 009b lsls r3, r3, #2 8001938: fbb2 f5f3 udiv r5, r2, r3 800193c: f7ff fb08 bl 8000f50 8001940: 4602 mov r2, r0 8001942: 4613 mov r3, r2 8001944: 009b lsls r3, r3, #2 8001946: 4413 add r3, r2 8001948: 009a lsls r2, r3, #2 800194a: 441a add r2, r3 800194c: 687b ldr r3, [r7, #4] 800194e: 685b ldr r3, [r3, #4] 8001950: 009b lsls r3, r3, #2 8001952: fbb2 f3f3 udiv r3, r2, r3 8001956: 4a0c ldr r2, [pc, #48] ; (8001988 ) 8001958: fba2 2303 umull r2, r3, r2, r3 800195c: 095b lsrs r3, r3, #5 800195e: 2264 movs r2, #100 ; 0x64 8001960: fb02 f303 mul.w r3, r2, r3 8001964: 1aeb subs r3, r5, r3 8001966: 011b lsls r3, r3, #4 8001968: 3332 adds r3, #50 ; 0x32 800196a: 4a07 ldr r2, [pc, #28] ; (8001988 ) 800196c: fba2 2303 umull r2, r3, r2, r3 8001970: 095b lsrs r3, r3, #5 8001972: f003 020f and.w r2, r3, #15 8001976: 687b ldr r3, [r7, #4] 8001978: 681b ldr r3, [r3, #0] 800197a: 4422 add r2, r4 800197c: 609a str r2, [r3, #8] 800197e: e071 b.n 8001a64 8001980: 40011000 .word 0x40011000 8001984: 40011400 .word 0x40011400 8001988: 51eb851f .word 0x51eb851f huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate); 800198c: f7ff facc bl 8000f28 8001990: 4602 mov r2, r0 8001992: 4613 mov r3, r2 8001994: 009b lsls r3, r3, #2 8001996: 4413 add r3, r2 8001998: 009a lsls r2, r3, #2 800199a: 441a add r2, r3 800199c: 687b ldr r3, [r7, #4] 800199e: 685b ldr r3, [r3, #4] 80019a0: 009b lsls r3, r3, #2 80019a2: fbb2 f3f3 udiv r3, r2, r3 80019a6: 4a31 ldr r2, [pc, #196] ; (8001a6c ) 80019a8: fba2 2303 umull r2, r3, r2, r3 80019ac: 095b lsrs r3, r3, #5 80019ae: 011c lsls r4, r3, #4 80019b0: f7ff faba bl 8000f28 80019b4: 4602 mov r2, r0 80019b6: 4613 mov r3, r2 80019b8: 009b lsls r3, r3, #2 80019ba: 4413 add r3, r2 80019bc: 009a lsls r2, r3, #2 80019be: 441a add r2, r3 80019c0: 687b ldr r3, [r7, #4] 80019c2: 685b ldr r3, [r3, #4] 80019c4: 009b lsls r3, r3, #2 80019c6: fbb2 f5f3 udiv r5, r2, r3 80019ca: f7ff faad bl 8000f28 80019ce: 4602 mov r2, r0 80019d0: 4613 mov r3, r2 80019d2: 009b lsls r3, r3, #2 80019d4: 4413 add r3, r2 80019d6: 009a lsls r2, r3, #2 80019d8: 441a add r2, r3 80019da: 687b ldr r3, [r7, #4] 80019dc: 685b ldr r3, [r3, #4] 80019de: 009b lsls r3, r3, #2 80019e0: fbb2 f3f3 udiv r3, r2, r3 80019e4: 4a21 ldr r2, [pc, #132] ; (8001a6c ) 80019e6: fba2 2303 umull r2, r3, r2, r3 80019ea: 095b lsrs r3, r3, #5 80019ec: 2264 movs r2, #100 ; 0x64 80019ee: fb02 f303 mul.w r3, r2, r3 80019f2: 1aeb subs r3, r5, r3 80019f4: 011b lsls r3, r3, #4 80019f6: 3332 adds r3, #50 ; 0x32 80019f8: 4a1c ldr r2, [pc, #112] ; (8001a6c ) 80019fa: fba2 2303 umull r2, r3, r2, r3 80019fe: 095b lsrs r3, r3, #5 8001a00: f003 03f0 and.w r3, r3, #240 ; 0xf0 8001a04: 441c add r4, r3 8001a06: f7ff fa8f bl 8000f28 8001a0a: 4602 mov r2, r0 8001a0c: 4613 mov r3, r2 8001a0e: 009b lsls r3, r3, #2 8001a10: 4413 add r3, r2 8001a12: 009a lsls r2, r3, #2 8001a14: 441a add r2, r3 8001a16: 687b ldr r3, [r7, #4] 8001a18: 685b ldr r3, [r3, #4] 8001a1a: 009b lsls r3, r3, #2 8001a1c: fbb2 f5f3 udiv r5, r2, r3 8001a20: f7ff fa82 bl 8000f28 8001a24: 4602 mov r2, r0 8001a26: 4613 mov r3, r2 8001a28: 009b lsls r3, r3, #2 8001a2a: 4413 add r3, r2 8001a2c: 009a lsls r2, r3, #2 8001a2e: 441a add r2, r3 8001a30: 687b ldr r3, [r7, #4] 8001a32: 685b ldr r3, [r3, #4] 8001a34: 009b lsls r3, r3, #2 8001a36: fbb2 f3f3 udiv r3, r2, r3 8001a3a: 4a0c ldr r2, [pc, #48] ; (8001a6c ) 8001a3c: fba2 2303 umull r2, r3, r2, r3 8001a40: 095b lsrs r3, r3, #5 8001a42: 2264 movs r2, #100 ; 0x64 8001a44: fb02 f303 mul.w r3, r2, r3 8001a48: 1aeb subs r3, r5, r3 8001a4a: 011b lsls r3, r3, #4 8001a4c: 3332 adds r3, #50 ; 0x32 8001a4e: 4a07 ldr r2, [pc, #28] ; (8001a6c ) 8001a50: fba2 2303 umull r2, r3, r2, r3 8001a54: 095b lsrs r3, r3, #5 8001a56: f003 020f and.w r2, r3, #15 8001a5a: 687b ldr r3, [r7, #4] 8001a5c: 681b ldr r3, [r3, #0] 8001a5e: 4422 add r2, r4 8001a60: 609a str r2, [r3, #8] } 8001a62: e7ff b.n 8001a64 8001a64: bf00 nop 8001a66: 3710 adds r7, #16 8001a68: 46bd mov sp, r7 8001a6a: bdb0 pop {r4, r5, r7, pc} 8001a6c: 51eb851f .word 0x51eb851f 08001a70 : * registers * * @return success ******************************************************************************/ char ADF4153_Init(ADF4153_settings_t ADF4153_st) { 8001a70: b084 sub sp, #16 8001a72: b580 push {r7, lr} 8001a74: b082 sub sp, #8 8001a76: af00 add r7, sp, #0 8001a78: f107 0c10 add.w ip, r7, #16 8001a7c: e88c 000f stmia.w ip, {r0, r1, r2, r3} char status = -1; 8001a80: 23ff movs r3, #255 ; 0xff 8001a82: 71fb strb r3, [r7, #7] /* CPHA = 1; CPOL = 0; */ /* Set up the reference input frequency */ refIn = ADF4153_st.refIn; 8001a84: 693b ldr r3, [r7, #16] 8001a86: 4a65 ldr r2, [pc, #404] ; (8001c1c ) 8001a88: 6013 str r3, [r2, #0] channelSpacing = ADF4153_st.channelSpacing; 8001a8a: 697b ldr r3, [r7, #20] 8001a8c: 4a64 ldr r2, [pc, #400] ; (8001c20 ) 8001a8e: 6013 str r3, [r2, #0] R_Counter = ADF4153_st.rCounter; 8001a90: 7f7b ldrb r3, [r7, #29] 8001a92: f3c3 1303 ubfx r3, r3, #4, #4 8001a96: b2db uxtb r3, r3 8001a98: 461a mov r2, r3 8001a9a: 4b62 ldr r3, [pc, #392] ; (8001c24 ) 8001a9c: 701a strb r2, [r3, #0] /* Write all zeros to the noise and spur register */ ADF4153_UpdateLatch(ADF4153_CTRL_NOISE_SPUR | 8001a9e: 2003 movs r0, #3 8001aa0: f000 f8c6 bl 8001c30 0x0); /* selects the lowest noise mode by default */ ADF4153_UpdateLatch(ADF4153_CTRL_NOISE_SPUR | 8001aa4: f240 30c7 movw r0, #967 ; 0x3c7 8001aa8: f000 f8c2 bl 8001c30 0x3C7); /* Set up the control register and enable the counter reset */ ADF4153_UpdateLatch(ADF4153_CTRL_CONTROL | ADF4153_R2_COUNTER_RST(ADF4153_CR_ENABLED) | ADF4153_R2_CP_3STATE(ADF4153_st.cpThreeState) | 8001aac: 7fbb ldrb r3, [r7, #30] 8001aae: f3c3 1380 ubfx r3, r3, #6, #1 8001ab2: b2db uxtb r3, r3 8001ab4: 00db lsls r3, r3, #3 8001ab6: f003 0308 and.w r3, r3, #8 ADF4153_R2_COUNTER_RST(ADF4153_CR_ENABLED) | 8001aba: f043 0206 orr.w r2, r3, #6 ADF4153_R2_POWER_DOWN(ADF4153_st.powerDown) | 8001abe: 7fbb ldrb r3, [r7, #30] 8001ac0: f3c3 13c0 ubfx r3, r3, #7, #1 8001ac4: b2db uxtb r3, r3 8001ac6: 011b lsls r3, r3, #4 8001ac8: f003 0310 and.w r3, r3, #16 ADF4153_R2_CP_3STATE(ADF4153_st.cpThreeState) | 8001acc: 431a orrs r2, r3 ADF4153_R2_LDP(ADF4153_st.ldp) | 8001ace: 7ffb ldrb r3, [r7, #31] 8001ad0: f3c3 0300 ubfx r3, r3, #0, #1 8001ad4: b2db uxtb r3, r3 8001ad6: 015b lsls r3, r3, #5 8001ad8: f003 0320 and.w r3, r3, #32 ADF4153_R2_POWER_DOWN(ADF4153_st.powerDown) | 8001adc: 431a orrs r2, r3 ADF4153_R2_PD_POL(ADF4153_st.pdPolarity) | 8001ade: 7ffb ldrb r3, [r7, #31] 8001ae0: f3c3 0340 ubfx r3, r3, #1, #1 8001ae4: b2db uxtb r3, r3 8001ae6: 019b lsls r3, r3, #6 8001ae8: f003 0340 and.w r3, r3, #64 ; 0x40 ADF4153_R2_LDP(ADF4153_st.ldp) | 8001aec: 431a orrs r2, r3 ADF4153_R2_CP_CURRENT(ADF4153_st.cpCurrent) | 8001aee: 7ffb ldrb r3, [r7, #31] 8001af0: f3c3 0383 ubfx r3, r3, #2, #4 8001af4: b2db uxtb r3, r3 8001af6: 01db lsls r3, r3, #7 8001af8: f403 63f0 and.w r3, r3, #1920 ; 0x780 ADF4153_R2_PD_POL(ADF4153_st.pdPolarity) | 8001afc: 431a orrs r2, r3 ADF4153_R2_REF_DOUBLER(ADF4153_st.refDoubler) | 8001afe: 7ffb ldrb r3, [r7, #31] 8001b00: f3c3 1380 ubfx r3, r3, #6, #1 8001b04: b2db uxtb r3, r3 8001b06: 02db lsls r3, r3, #11 8001b08: f403 6300 and.w r3, r3, #2048 ; 0x800 ADF4153_R2_CP_CURRENT(ADF4153_st.cpCurrent) | 8001b0c: 431a orrs r2, r3 ADF4153_R2_RESYNC(ADF4153_st.resync) 8001b0e: f897 3020 ldrb.w r3, [r7, #32] 8001b12: f3c3 0303 ubfx r3, r3, #0, #4 8001b16: b2db uxtb r3, r3 8001b18: 031b lsls r3, r3, #12 8001b1a: f403 43e0 and.w r3, r3, #28672 ; 0x7000 ADF4153_R2_REF_DOUBLER(ADF4153_st.refDoubler) | 8001b1e: 4313 orrs r3, r2 ADF4153_UpdateLatch(ADF4153_CTRL_CONTROL | 8001b20: 4618 mov r0, r3 8001b22: f000 f885 bl 8001c30 ); /* If resync feature is enabled */ if(ADF4153_st.resync != 0x0) 8001b26: f897 3020 ldrb.w r3, [r7, #32] 8001b2a: f003 030f and.w r3, r3, #15 8001b2e: b2db uxtb r3, r3 8001b30: 2b00 cmp r3, #0 8001b32: d01d beq.n 8001b70 { /* Load the R divider register */ ADF4153_UpdateLatch(ADF4153_CTRL_R_DIVIDER | ADF4153_R1_MOD(10) | //Resync Delay ADF4153_R1_RCOUNTER(ADF4153_st.rCounter) | 8001b34: 7f7b ldrb r3, [r7, #29] 8001b36: f3c3 1303 ubfx r3, r3, #4, #4 8001b3a: b2db uxtb r3, r3 8001b3c: 039b lsls r3, r3, #14 8001b3e: f403 3370 and.w r3, r3, #245760 ; 0x3c000 ADF4153_R1_MOD(10) | //Resync Delay 8001b42: f043 0229 orr.w r2, r3, #41 ; 0x29 ADF4153_R1_PRESCALE(ADF4153_st.prescaler) | 8001b46: 7fbb ldrb r3, [r7, #30] 8001b48: f3c3 0300 ubfx r3, r3, #0, #1 8001b4c: b2db uxtb r3, r3 8001b4e: 049b lsls r3, r3, #18 8001b50: f403 2380 and.w r3, r3, #262144 ; 0x40000 ADF4153_R1_RCOUNTER(ADF4153_st.rCounter) | 8001b54: 431a orrs r2, r3 ADF4153_R1_MUXOUT(ADF4153_st.muxout) | 8001b56: 7fbb ldrb r3, [r7, #30] 8001b58: f3c3 0342 ubfx r3, r3, #1, #3 8001b5c: b2db uxtb r3, r3 8001b5e: 051b lsls r3, r3, #20 8001b60: f403 03e0 and.w r3, r3, #7340032 ; 0x700000 ADF4153_R1_PRESCALE(ADF4153_st.prescaler) | 8001b64: 4313 orrs r3, r2 ADF4153_R1_MUXOUT(ADF4153_st.muxout) | 8001b66: f443 0300 orr.w r3, r3, #8388608 ; 0x800000 ADF4153_UpdateLatch(ADF4153_CTRL_R_DIVIDER | 8001b6a: 4618 mov r0, r3 8001b6c: f000 f860 bl 8001c30 ADF4153_R1_LOAD(ADF4153_LOAD_RESYNC) ); } /* Load the R divider register */ ADF4153_UpdateLatch(ADF4153_CTRL_R_DIVIDER | ADF4153_R1_MOD(ADF4153_st.modValue) | 8001b70: 8bbb ldrh r3, [r7, #28] 8001b72: f3c3 030b ubfx r3, r3, #0, #12 8001b76: b29b uxth r3, r3 8001b78: 009a lsls r2, r3, #2 8001b7a: f643 73fc movw r3, #16380 ; 0x3ffc 8001b7e: 4013 ands r3, r2 ADF4153_UpdateLatch(ADF4153_CTRL_R_DIVIDER | 8001b80: f043 0201 orr.w r2, r3, #1 ADF4153_R1_RCOUNTER(ADF4153_st.rCounter) | 8001b84: 7f7b ldrb r3, [r7, #29] 8001b86: f3c3 1303 ubfx r3, r3, #4, #4 8001b8a: b2db uxtb r3, r3 8001b8c: 039b lsls r3, r3, #14 8001b8e: f403 3370 and.w r3, r3, #245760 ; 0x3c000 ADF4153_R1_MOD(ADF4153_st.modValue) | 8001b92: 431a orrs r2, r3 ADF4153_R1_PRESCALE(ADF4153_st.prescaler) | 8001b94: 7fbb ldrb r3, [r7, #30] 8001b96: f3c3 0300 ubfx r3, r3, #0, #1 8001b9a: b2db uxtb r3, r3 8001b9c: 049b lsls r3, r3, #18 8001b9e: f403 2380 and.w r3, r3, #262144 ; 0x40000 ADF4153_R1_RCOUNTER(ADF4153_st.rCounter) | 8001ba2: 431a orrs r2, r3 ADF4153_R1_MUXOUT(ADF4153_st.muxout) | 8001ba4: 7fbb ldrb r3, [r7, #30] 8001ba6: f3c3 0342 ubfx r3, r3, #1, #3 8001baa: b2db uxtb r3, r3 8001bac: 051b lsls r3, r3, #20 8001bae: f403 03e0 and.w r3, r3, #7340032 ; 0x700000 8001bb2: 4313 orrs r3, r2 ADF4153_UpdateLatch(ADF4153_CTRL_R_DIVIDER | 8001bb4: 4618 mov r0, r3 8001bb6: f000 f83b bl 8001c30 ADF4153_R1_LOAD(ADF4153_LOAD_NORMAL) ); /* Load the N divider register */ ADF4153_UpdateLatch(ADF4153_CTRL_N_DIVIDER | ADF4153_R0_FRAC(ADF4153_st.fracValue) | 8001bba: 8b3b ldrh r3, [r7, #24] 8001bbc: f3c3 030b ubfx r3, r3, #0, #12 8001bc0: b29b uxth r3, r3 8001bc2: 009b lsls r3, r3, #2 ADF4153_UpdateLatch(ADF4153_CTRL_N_DIVIDER | 8001bc4: f643 72fc movw r2, #16380 ; 0x3ffc 8001bc8: 401a ands r2, r3 ADF4153_R0_INT(ADF4153_st.intValue) | 8001bca: 8b7b ldrh r3, [r7, #26] 8001bcc: f3c3 0308 ubfx r3, r3, #0, #9 8001bd0: b29b uxth r3, r3 8001bd2: 0399 lsls r1, r3, #14 8001bd4: 4b14 ldr r3, [pc, #80] ; (8001c28 ) 8001bd6: 400b ands r3, r1 ADF4153_R0_FRAC(ADF4153_st.fracValue) | 8001bd8: 431a orrs r2, r3 ADF4153_R0_FASTLOCK(ADF4153_st.fastlock) 8001bda: 7efb ldrb r3, [r7, #27] 8001bdc: f3c3 0340 ubfx r3, r3, #1, #1 8001be0: b2db uxtb r3, r3 8001be2: 05db lsls r3, r3, #23 8001be4: f403 0300 and.w r3, r3, #8388608 ; 0x800000 ADF4153_R0_INT(ADF4153_st.intValue) | 8001be8: 4313 orrs r3, r2 ADF4153_UpdateLatch(ADF4153_CTRL_N_DIVIDER | 8001bea: 4618 mov r0, r3 8001bec: f000 f820 bl 8001c30 ); /* Disable the counter reset in the Control Register */ r2 &= ~ADF4153_R2_COUNTER_RST(ADF4153_R2_COUNTER_RST_MASK); 8001bf0: 4b0e ldr r3, [pc, #56] ; (8001c2c ) 8001bf2: 681b ldr r3, [r3, #0] 8001bf4: f023 0307 bic.w r3, r3, #7 8001bf8: 4a0c ldr r2, [pc, #48] ; (8001c2c ) 8001bfa: 6013 str r3, [r2, #0] ADF4153_UpdateLatch(ADF4153_CTRL_CONTROL | 8001bfc: 4b0b ldr r3, [pc, #44] ; (8001c2c ) 8001bfe: 681b ldr r3, [r3, #0] 8001c00: f043 0302 orr.w r3, r3, #2 8001c04: 4618 mov r0, r3 8001c06: f000 f813 bl 8001c30 r2 | ADF4153_R2_COUNTER_RST(ADF4153_CR_DISABLED) ); return status; 8001c0a: 79fb ldrb r3, [r7, #7] } 8001c0c: 4618 mov r0, r3 8001c0e: 3708 adds r7, #8 8001c10: 46bd mov sp, r7 8001c12: e8bd 4080 ldmia.w sp!, {r7, lr} 8001c16: b004 add sp, #16 8001c18: 4770 bx lr 8001c1a: bf00 nop 8001c1c: 200000b8 .word 0x200000b8 8001c20: 200000bc .word 0x200000bc 8001c24: 200000c0 .word 0x200000c0 8001c28: 007fc000 .word 0x007fc000 8001c2c: 200000cc .word 0x200000cc 08001c30 : * @param latchData - the data which will be written to the latch * * @return ******************************************************************************/ void ADF4153_UpdateLatch(unsigned long latchData) { 8001c30: b480 push {r7} 8001c32: b085 sub sp, #20 8001c34: af00 add r7, sp, #0 8001c36: 6078 str r0, [r7, #4] unsigned char dataBuffer[3] = {0,}; 8001c38: f107 030c add.w r3, r7, #12 8001c3c: 2100 movs r1, #0 8001c3e: 460a mov r2, r1 8001c40: 801a strh r2, [r3, #0] 8001c42: 460a mov r2, r1 8001c44: 709a strb r2, [r3, #2] unsigned char latchType = latchData & 0x3; 8001c46: 687b ldr r3, [r7, #4] 8001c48: b2db uxtb r3, r3 8001c4a: f003 0303 and.w r3, r3, #3 8001c4e: 73fb strb r3, [r7, #15] /* Update the internal buffers */ switch(latchType) 8001c50: 7bfb ldrb r3, [r7, #15] 8001c52: 2b03 cmp r3, #3 8001c54: d81a bhi.n 8001c8c 8001c56: a201 add r2, pc, #4 ; (adr r2, 8001c5c ) 8001c58: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8001c5c: 08001c6d .word 0x08001c6d 8001c60: 08001c75 .word 0x08001c75 8001c64: 08001c7d .word 0x08001c7d 8001c68: 08001c85 .word 0x08001c85 { case ADF4153_CTRL_N_DIVIDER : r0 = latchData; 8001c6c: 4a10 ldr r2, [pc, #64] ; (8001cb0 ) 8001c6e: 687b ldr r3, [r7, #4] 8001c70: 6013 str r3, [r2, #0] break; 8001c72: e00b b.n 8001c8c case ADF4153_CTRL_R_DIVIDER : r1 = latchData; 8001c74: 4a0f ldr r2, [pc, #60] ; (8001cb4 ) 8001c76: 687b ldr r3, [r7, #4] 8001c78: 6013 str r3, [r2, #0] break; 8001c7a: e007 b.n 8001c8c case ADF4153_CTRL_CONTROL : r2 = latchData; 8001c7c: 4a0e ldr r2, [pc, #56] ; (8001cb8 ) 8001c7e: 687b ldr r3, [r7, #4] 8001c80: 6013 str r3, [r2, #0] break; 8001c82: e003 b.n 8001c8c case ADF4153_CTRL_NOISE_SPUR : r3 = latchData; 8001c84: 4a0d ldr r2, [pc, #52] ; (8001cbc ) 8001c86: 687b ldr r3, [r7, #4] 8001c88: 6013 str r3, [r2, #0] break; 8001c8a: bf00 nop } dataBuffer[0] = (latchData & DATA_MASK_MSB8) >> DATA_OFFSET_MSB8; 8001c8c: 687b ldr r3, [r7, #4] 8001c8e: 0c1b lsrs r3, r3, #16 8001c90: b2db uxtb r3, r3 8001c92: 733b strb r3, [r7, #12] dataBuffer[1] = (latchData & DATA_MASK_MID8) >> DATA_OFFSET_MID8; 8001c94: 687b ldr r3, [r7, #4] 8001c96: 0a1b lsrs r3, r3, #8 8001c98: b2db uxtb r3, r3 8001c9a: 737b strb r3, [r7, #13] dataBuffer[2] = (latchData & DATA_MASK_LSB8) >> DATA_OFFSET_LSB8; 8001c9c: 687b ldr r3, [r7, #4] 8001c9e: b2db uxtb r3, r3 8001ca0: 73bb strb r3, [r7, #14] /* Generate a load pulse */ } 8001ca2: bf00 nop 8001ca4: 3714 adds r7, #20 8001ca6: 46bd mov sp, r7 8001ca8: f85d 7b04 ldr.w r7, [sp], #4 8001cac: 4770 bx lr 8001cae: bf00 nop 8001cb0: 200000c4 .word 0x200000c4 8001cb4: 200000c8 .word 0x200000c8 8001cb8: 200000cc .word 0x200000cc 8001cbc: 200000d0 .word 0x200000d0 08001cc0 : HAL_GPIO_WritePin(PLL_EN_GPIO_Port, PLL_EN_Pin, GPIO_PIN_SET); HAL_GPIO_WritePin(PLL_EN_GPIO_Port, PLL_EN_Pin, GPIO_PIN_RESET); } #else void ADF_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2,uint32_t R3){ 8001cc0: b084 sub sp, #16 8001cc2: b580 push {r7, lr} 8001cc4: b084 sub sp, #16 8001cc6: af00 add r7, sp, #0 8001cc8: f107 0c18 add.w ip, r7, #24 8001ccc: e88c 000f stmia.w ip, {r0, r1, r2, r3} R3 = R3 & 0x0007FF; 8001cd0: 6bfb ldr r3, [r7, #60] ; 0x3c 8001cd2: f3c3 030a ubfx r3, r3, #0, #11 8001cd6: 63fb str r3, [r7, #60] ; 0x3c R2 = R2 & 0x00FFFF; 8001cd8: 6bbb ldr r3, [r7, #56] ; 0x38 8001cda: b29b uxth r3, r3 8001cdc: 63bb str r3, [r7, #56] ; 0x38 R1 = R1 & 0xFFFFFF; 8001cde: 6b7b ldr r3, [r7, #52] ; 0x34 8001ce0: f023 437f bic.w r3, r3, #4278190080 ; 0xff000000 8001ce4: 637b str r3, [r7, #52] ; 0x34 R0 = R0 & 0xFFFFFF; 8001ce6: 6b3b ldr r3, [r7, #48] ; 0x30 8001ce8: f023 437f bic.w r3, r3, #4278190080 ; 0xff000000 8001cec: 633b str r3, [r7, #48] ; 0x30 HAL_GPIO_WritePin(PLL_CLK_GPIO_Port, PLL_CLK_Pin, GPIO_PIN_RESET); 8001cee: 2200 movs r2, #0 8001cf0: f44f 7180 mov.w r1, #256 ; 0x100 8001cf4: 4871 ldr r0, [pc, #452] ; (8001ebc ) 8001cf6: f7fe ff1f bl 8000b38 HAL_GPIO_WritePin(PLL_DATA_GPIO_Port, PLL_DATA_Pin, GPIO_PIN_RESET); 8001cfa: 2200 movs r2, #0 8001cfc: 2140 movs r1, #64 ; 0x40 8001cfe: 486f ldr r0, [pc, #444] ; (8001ebc ) 8001d00: f7fe ff1a bl 8000b38 HAL_GPIO_WritePin(PLL_EN_GPIO_Port, PLL_EN_Pin, GPIO_PIN_RESET); 8001d04: 2200 movs r2, #0 8001d06: 2120 movs r1, #32 8001d08: 486c ldr r0, [pc, #432] ; (8001ebc ) 8001d0a: f7fe ff15 bl 8000b38 /* R3 Ctrl */ for(int i =0; i < 11; i++){ 8001d0e: 2300 movs r3, #0 8001d10: 60fb str r3, [r7, #12] 8001d12: e023 b.n 8001d5c if(R3 & 0x000700) 8001d14: 6bfb ldr r3, [r7, #60] ; 0x3c 8001d16: f403 63e0 and.w r3, r3, #1792 ; 0x700 8001d1a: 2b00 cmp r3, #0 8001d1c: d005 beq.n 8001d2a HAL_GPIO_WritePin(PLL_DATA_GPIO_Port, PLL_DATA_Pin, GPIO_PIN_SET); 8001d1e: 2201 movs r2, #1 8001d20: 2140 movs r1, #64 ; 0x40 8001d22: 4866 ldr r0, [pc, #408] ; (8001ebc ) 8001d24: f7fe ff08 bl 8000b38 8001d28: e004 b.n 8001d34 else HAL_GPIO_WritePin(PLL_DATA_GPIO_Port, PLL_DATA_Pin, GPIO_PIN_RESET); 8001d2a: 2200 movs r2, #0 8001d2c: 2140 movs r1, #64 ; 0x40 8001d2e: 4863 ldr r0, [pc, #396] ; (8001ebc ) 8001d30: f7fe ff02 bl 8000b38 HAL_GPIO_WritePin(PLL_CLK_GPIO_Port, PLL_CLK_Pin, GPIO_PIN_SET); 8001d34: 2201 movs r2, #1 8001d36: f44f 7180 mov.w r1, #256 ; 0x100 8001d3a: 4860 ldr r0, [pc, #384] ; (8001ebc ) 8001d3c: f7fe fefc bl 8000b38 HAL_GPIO_WritePin(PLL_CLK_GPIO_Port, PLL_CLK_Pin, GPIO_PIN_RESET); 8001d40: 2200 movs r2, #0 8001d42: f44f 7180 mov.w r1, #256 ; 0x100 8001d46: 485d ldr r0, [pc, #372] ; (8001ebc ) 8001d48: f7fe fef6 bl 8000b38 R3 = ((R3 << 1) & 0x00000FFF); 8001d4c: 6bfb ldr r3, [r7, #60] ; 0x3c 8001d4e: 005b lsls r3, r3, #1 8001d50: f3c3 030b ubfx r3, r3, #0, #12 8001d54: 63fb str r3, [r7, #60] ; 0x3c for(int i =0; i < 11; i++){ 8001d56: 68fb ldr r3, [r7, #12] 8001d58: 3301 adds r3, #1 8001d5a: 60fb str r3, [r7, #12] 8001d5c: 68fb ldr r3, [r7, #12] 8001d5e: 2b0a cmp r3, #10 8001d60: ddd8 ble.n 8001d14 } HAL_GPIO_WritePin(PLL_EN_GPIO_Port, PLL_EN_Pin, GPIO_PIN_SET); 8001d62: 2201 movs r2, #1 8001d64: 2120 movs r1, #32 8001d66: 4855 ldr r0, [pc, #340] ; (8001ebc ) 8001d68: f7fe fee6 bl 8000b38 HAL_GPIO_WritePin(PLL_EN_GPIO_Port, PLL_EN_Pin, GPIO_PIN_RESET); 8001d6c: 2200 movs r2, #0 8001d6e: 2120 movs r1, #32 8001d70: 4852 ldr r0, [pc, #328] ; (8001ebc ) 8001d72: f7fe fee1 bl 8000b38 /* R2 Ctrl */ for(int i =0; i < 16; i++){ 8001d76: 2300 movs r3, #0 8001d78: 60bb str r3, [r7, #8] 8001d7a: e022 b.n 8001dc2 if(R2 & 0x008000) 8001d7c: 6bbb ldr r3, [r7, #56] ; 0x38 8001d7e: f403 4300 and.w r3, r3, #32768 ; 0x8000 8001d82: 2b00 cmp r3, #0 8001d84: d005 beq.n 8001d92 HAL_GPIO_WritePin(PLL_DATA_GPIO_Port, PLL_DATA_Pin, GPIO_PIN_SET); 8001d86: 2201 movs r2, #1 8001d88: 2140 movs r1, #64 ; 0x40 8001d8a: 484c ldr r0, [pc, #304] ; (8001ebc ) 8001d8c: f7fe fed4 bl 8000b38 8001d90: e004 b.n 8001d9c else HAL_GPIO_WritePin(PLL_DATA_GPIO_Port, PLL_DATA_Pin, GPIO_PIN_RESET); 8001d92: 2200 movs r2, #0 8001d94: 2140 movs r1, #64 ; 0x40 8001d96: 4849 ldr r0, [pc, #292] ; (8001ebc ) 8001d98: f7fe fece bl 8000b38 HAL_GPIO_WritePin(PLL_CLK_GPIO_Port, PLL_CLK_Pin, GPIO_PIN_SET); 8001d9c: 2201 movs r2, #1 8001d9e: f44f 7180 mov.w r1, #256 ; 0x100 8001da2: 4846 ldr r0, [pc, #280] ; (8001ebc ) 8001da4: f7fe fec8 bl 8000b38 HAL_GPIO_WritePin(PLL_CLK_GPIO_Port, PLL_CLK_Pin, GPIO_PIN_RESET); 8001da8: 2200 movs r2, #0 8001daa: f44f 7180 mov.w r1, #256 ; 0x100 8001dae: 4843 ldr r0, [pc, #268] ; (8001ebc ) 8001db0: f7fe fec2 bl 8000b38 R2 = ((R2 << 1) & 0x00FFFF); 8001db4: 6bbb ldr r3, [r7, #56] ; 0x38 8001db6: 005b lsls r3, r3, #1 8001db8: b29b uxth r3, r3 8001dba: 63bb str r3, [r7, #56] ; 0x38 for(int i =0; i < 16; i++){ 8001dbc: 68bb ldr r3, [r7, #8] 8001dbe: 3301 adds r3, #1 8001dc0: 60bb str r3, [r7, #8] 8001dc2: 68bb ldr r3, [r7, #8] 8001dc4: 2b0f cmp r3, #15 8001dc6: ddd9 ble.n 8001d7c } HAL_GPIO_WritePin(PLL_EN_GPIO_Port, PLL_EN_Pin, GPIO_PIN_SET); 8001dc8: 2201 movs r2, #1 8001dca: 2120 movs r1, #32 8001dcc: 483b ldr r0, [pc, #236] ; (8001ebc ) 8001dce: f7fe feb3 bl 8000b38 HAL_GPIO_WritePin(PLL_EN_GPIO_Port, PLL_EN_Pin, GPIO_PIN_RESET); 8001dd2: 2200 movs r2, #0 8001dd4: 2120 movs r1, #32 8001dd6: 4839 ldr r0, [pc, #228] ; (8001ebc ) 8001dd8: f7fe feae bl 8000b38 /* R1 Ctrl */ for(int i =0; i < 24; i++){ 8001ddc: 2300 movs r3, #0 8001dde: 607b str r3, [r7, #4] 8001de0: e023 b.n 8001e2a if(R1 & 0x800000) 8001de2: 6b7b ldr r3, [r7, #52] ; 0x34 8001de4: f403 0300 and.w r3, r3, #8388608 ; 0x800000 8001de8: 2b00 cmp r3, #0 8001dea: d005 beq.n 8001df8 HAL_GPIO_WritePin(PLL_DATA_GPIO_Port, PLL_DATA_Pin, GPIO_PIN_SET); 8001dec: 2201 movs r2, #1 8001dee: 2140 movs r1, #64 ; 0x40 8001df0: 4832 ldr r0, [pc, #200] ; (8001ebc ) 8001df2: f7fe fea1 bl 8000b38 8001df6: e004 b.n 8001e02 else HAL_GPIO_WritePin(PLL_DATA_GPIO_Port, PLL_DATA_Pin, GPIO_PIN_RESET); 8001df8: 2200 movs r2, #0 8001dfa: 2140 movs r1, #64 ; 0x40 8001dfc: 482f ldr r0, [pc, #188] ; (8001ebc ) 8001dfe: f7fe fe9b bl 8000b38 HAL_GPIO_WritePin(PLL_CLK_GPIO_Port, PLL_CLK_Pin, GPIO_PIN_SET); 8001e02: 2201 movs r2, #1 8001e04: f44f 7180 mov.w r1, #256 ; 0x100 8001e08: 482c ldr r0, [pc, #176] ; (8001ebc ) 8001e0a: f7fe fe95 bl 8000b38 HAL_GPIO_WritePin(PLL_CLK_GPIO_Port, PLL_CLK_Pin, GPIO_PIN_RESET); 8001e0e: 2200 movs r2, #0 8001e10: f44f 7180 mov.w r1, #256 ; 0x100 8001e14: 4829 ldr r0, [pc, #164] ; (8001ebc ) 8001e16: f7fe fe8f bl 8000b38 R1 = ((R1 << 1) & 0xFFFFFF); 8001e1a: 6b7b ldr r3, [r7, #52] ; 0x34 8001e1c: 005b lsls r3, r3, #1 8001e1e: f023 437f bic.w r3, r3, #4278190080 ; 0xff000000 8001e22: 637b str r3, [r7, #52] ; 0x34 for(int i =0; i < 24; i++){ 8001e24: 687b ldr r3, [r7, #4] 8001e26: 3301 adds r3, #1 8001e28: 607b str r3, [r7, #4] 8001e2a: 687b ldr r3, [r7, #4] 8001e2c: 2b17 cmp r3, #23 8001e2e: ddd8 ble.n 8001de2 } HAL_GPIO_WritePin(PLL_EN_GPIO_Port, PLL_EN_Pin, GPIO_PIN_SET); 8001e30: 2201 movs r2, #1 8001e32: 2120 movs r1, #32 8001e34: 4821 ldr r0, [pc, #132] ; (8001ebc ) 8001e36: f7fe fe7f bl 8000b38 HAL_GPIO_WritePin(PLL_EN_GPIO_Port, PLL_EN_Pin, GPIO_PIN_RESET); 8001e3a: 2200 movs r2, #0 8001e3c: 2120 movs r1, #32 8001e3e: 481f ldr r0, [pc, #124] ; (8001ebc ) 8001e40: f7fe fe7a bl 8000b38 /* R0 Ctrl */ for(int i =0; i < 24; i++){ 8001e44: 2300 movs r3, #0 8001e46: 603b str r3, [r7, #0] 8001e48: e023 b.n 8001e92 if(R0 & 0x800000) 8001e4a: 6b3b ldr r3, [r7, #48] ; 0x30 8001e4c: f403 0300 and.w r3, r3, #8388608 ; 0x800000 8001e50: 2b00 cmp r3, #0 8001e52: d005 beq.n 8001e60 HAL_GPIO_WritePin(PLL_DATA_GPIO_Port, PLL_DATA_Pin, GPIO_PIN_SET); 8001e54: 2201 movs r2, #1 8001e56: 2140 movs r1, #64 ; 0x40 8001e58: 4818 ldr r0, [pc, #96] ; (8001ebc ) 8001e5a: f7fe fe6d bl 8000b38 8001e5e: e004 b.n 8001e6a else HAL_GPIO_WritePin(PLL_DATA_GPIO_Port, PLL_DATA_Pin, GPIO_PIN_RESET); 8001e60: 2200 movs r2, #0 8001e62: 2140 movs r1, #64 ; 0x40 8001e64: 4815 ldr r0, [pc, #84] ; (8001ebc ) 8001e66: f7fe fe67 bl 8000b38 HAL_GPIO_WritePin(PLL_CLK_GPIO_Port, PLL_CLK_Pin, GPIO_PIN_SET); 8001e6a: 2201 movs r2, #1 8001e6c: f44f 7180 mov.w r1, #256 ; 0x100 8001e70: 4812 ldr r0, [pc, #72] ; (8001ebc ) 8001e72: f7fe fe61 bl 8000b38 HAL_GPIO_WritePin(PLL_CLK_GPIO_Port, PLL_CLK_Pin, GPIO_PIN_RESET); 8001e76: 2200 movs r2, #0 8001e78: f44f 7180 mov.w r1, #256 ; 0x100 8001e7c: 480f ldr r0, [pc, #60] ; (8001ebc ) 8001e7e: f7fe fe5b bl 8000b38 R0 = ((R0 << 1) & 0xFFFFFF); 8001e82: 6b3b ldr r3, [r7, #48] ; 0x30 8001e84: 005b lsls r3, r3, #1 8001e86: f023 437f bic.w r3, r3, #4278190080 ; 0xff000000 8001e8a: 633b str r3, [r7, #48] ; 0x30 for(int i =0; i < 24; i++){ 8001e8c: 683b ldr r3, [r7, #0] 8001e8e: 3301 adds r3, #1 8001e90: 603b str r3, [r7, #0] 8001e92: 683b ldr r3, [r7, #0] 8001e94: 2b17 cmp r3, #23 8001e96: ddd8 ble.n 8001e4a } HAL_GPIO_WritePin(PLL_EN_GPIO_Port, PLL_EN_Pin, GPIO_PIN_SET); 8001e98: 2201 movs r2, #1 8001e9a: 2120 movs r1, #32 8001e9c: 4807 ldr r0, [pc, #28] ; (8001ebc ) 8001e9e: f7fe fe4b bl 8000b38 HAL_GPIO_WritePin(PLL_EN_GPIO_Port, PLL_EN_Pin, GPIO_PIN_RESET); 8001ea2: 2200 movs r2, #0 8001ea4: 2120 movs r1, #32 8001ea6: 4805 ldr r0, [pc, #20] ; (8001ebc ) 8001ea8: f7fe fe46 bl 8000b38 } 8001eac: bf00 nop 8001eae: 3710 adds r7, #16 8001eb0: 46bd mov sp, r7 8001eb2: e8bd 4080 ldmia.w sp!, {r7, lr} 8001eb6: b004 add sp, #16 8001eb8: 4770 bx lr 8001eba: bf00 nop 8001ebc: 40020800 .word 0x40020800 08001ec0 <_write>: /* Private user code ---------------------------------------------------------*/ /* USER CODE BEGIN 0 */ int _write (int file, uint8_t *ptr, uint16_t len) { 8001ec0: b580 push {r7, lr} 8001ec2: b084 sub sp, #16 8001ec4: af00 add r7, sp, #0 8001ec6: 60f8 str r0, [r7, #12] 8001ec8: 60b9 str r1, [r7, #8] 8001eca: 4613 mov r3, r2 8001ecc: 80fb strh r3, [r7, #6] HAL_UART_Transmit (&huart2, ptr, len, 10); 8001ece: 88fa ldrh r2, [r7, #6] 8001ed0: 230a movs r3, #10 8001ed2: 68b9 ldr r1, [r7, #8] 8001ed4: 4803 ldr r0, [pc, #12] ; (8001ee4 <_write+0x24>) 8001ed6: f7ff fade bl 8001496 return len; 8001eda: 88fb ldrh r3, [r7, #6] } 8001edc: 4618 mov r0, r3 8001ede: 3710 adds r7, #16 8001ee0: 46bd mov sp, r7 8001ee2: bd80 pop {r7, pc} 8001ee4: 200000e4 .word 0x200000e4 08001ee8 : PLL_DATA_Pin, PLL_EN_GPIO_Port, PLL_EN_Pin, }; void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) { 8001ee8: b590 push {r4, r7, lr} 8001eea: b089 sub sp, #36 ; 0x24 8001eec: af06 add r7, sp, #24 8001eee: 4603 mov r3, r0 8001ef0: 80fb strh r3, [r7, #6] if(GPIO_Pin == GPIO_PIN_12){ 8001ef2: 88fb ldrh r3, [r7, #6] 8001ef4: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8001ef8: d115 bne.n 8001f26 ADF_Module_Ctrl(Pll_test,0x324000,0x144051,0x0017c2,0x0003c7); 8001efa: 4b0d ldr r3, [pc, #52] ; (8001f30 ) 8001efc: f240 32c7 movw r2, #967 ; 0x3c7 8001f00: 9205 str r2, [sp, #20] 8001f02: f241 72c2 movw r2, #6082 ; 0x17c2 8001f06: 9204 str r2, [sp, #16] 8001f08: 4a0a ldr r2, [pc, #40] ; (8001f34 ) 8001f0a: 9203 str r2, [sp, #12] 8001f0c: f44f 1249 mov.w r2, #3293184 ; 0x324000 8001f10: 9202 str r2, [sp, #8] 8001f12: 466c mov r4, sp 8001f14: f103 0210 add.w r2, r3, #16 8001f18: e892 0003 ldmia.w r2, {r0, r1} 8001f1c: e884 0003 stmia.w r4, {r0, r1} 8001f20: cb0f ldmia r3, {r0, r1, r2, r3} 8001f22: f7ff fecd bl 8001cc0 } } 8001f26: bf00 nop 8001f28: 370c adds r7, #12 8001f2a: 46bd mov sp, r7 8001f2c: bd90 pop {r4, r7, pc} 8001f2e: bf00 nop 8001f30: 2000001c .word 0x2000001c 8001f34: 00144051 .word 0x00144051 08001f38
: /** * @brief The application entry point. * @retval int */ int main(void) { 8001f38: b590 push {r4, r7, lr} 8001f3a: b087 sub sp, #28 8001f3c: af06 add r7, sp, #24 /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 8001f3e: f7fe fae3 bl 8000508 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8001f42: f000 f83b bl 8001fbc /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8001f46: f000 f8db bl 8002100 MX_USART2_UART_Init(); 8001f4a: f000 f8af bl 80020ac /* Initialize interrupts */ MX_NVIC_Init(); 8001f4e: f000 f8a1 bl 8002094 /* USER CODE BEGIN 2 */ setbuf(stdout, NULL); 8001f52: 4b15 ldr r3, [pc, #84] ; (8001fa8 ) 8001f54: 681b ldr r3, [r3, #0] 8001f56: 689b ldr r3, [r3, #8] 8001f58: 2100 movs r1, #0 8001f5a: 4618 mov r0, r3 8001f5c: f000 fb84 bl 8002668 printf("UART Start \r\n"); 8001f60: 4812 ldr r0, [pc, #72] ; (8001fac ) 8001f62: f000 fb79 bl 8002658 ADF4153_Init(ADF4153_st); 8001f66: 4b12 ldr r3, [pc, #72] ; (8001fb0 ) 8001f68: 691a ldr r2, [r3, #16] 8001f6a: 9200 str r2, [sp, #0] 8001f6c: cb0f ldmia r3, {r0, r1, r2, r3} 8001f6e: f7ff fd7f bl 8001a70 ADF_Module_Ctrl(Pll_test,0x324000,0x144051,0x0017c2,0x0003c7); 8001f72: 4b10 ldr r3, [pc, #64] ; (8001fb4 ) 8001f74: f240 32c7 movw r2, #967 ; 0x3c7 8001f78: 9205 str r2, [sp, #20] 8001f7a: f241 72c2 movw r2, #6082 ; 0x17c2 8001f7e: 9204 str r2, [sp, #16] 8001f80: 4a0d ldr r2, [pc, #52] ; (8001fb8 ) 8001f82: 9203 str r2, [sp, #12] 8001f84: f44f 1249 mov.w r2, #3293184 ; 0x324000 8001f88: 9202 str r2, [sp, #8] 8001f8a: 466c mov r4, sp 8001f8c: f103 0210 add.w r2, r3, #16 8001f90: e892 0003 ldmia.w r2, {r0, r1} 8001f94: e884 0003 stmia.w r4, {r0, r1} 8001f98: cb0f ldmia r3, {r0, r1, r2, r3} 8001f9a: f7ff fe91 bl 8001cc0 */ // if(HAL_GPIO_ReadPin(GPIOA,GPIO_PIN_12) == GPIO_PIN_SET){ // }else{ // ADF_Module_Ctrl(Pll_test,0x324000,0x144051,0x0017c2,0x0003c7); HAL_Delay(1); 8001f9e: 2001 movs r0, #1 8001fa0: f7fe fb24 bl 80005ec 8001fa4: e7fb b.n 8001f9e 8001fa6: bf00 nop 8001fa8: 20000038 .word 0x20000038 8001fac: 08003004 .word 0x08003004 8001fb0: 20000008 .word 0x20000008 8001fb4: 2000001c .word 0x2000001c 8001fb8: 00144051 .word 0x00144051 08001fbc : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8001fbc: b580 push {r7, lr} 8001fbe: b094 sub sp, #80 ; 0x50 8001fc0: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8001fc2: f107 031c add.w r3, r7, #28 8001fc6: 2234 movs r2, #52 ; 0x34 8001fc8: 2100 movs r1, #0 8001fca: 4618 mov r0, r3 8001fcc: f000 fae0 bl 8002590 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8001fd0: f107 0308 add.w r3, r7, #8 8001fd4: 2200 movs r2, #0 8001fd6: 601a str r2, [r3, #0] 8001fd8: 605a str r2, [r3, #4] 8001fda: 609a str r2, [r3, #8] 8001fdc: 60da str r2, [r3, #12] 8001fde: 611a str r2, [r3, #16] /** Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); 8001fe0: 2300 movs r3, #0 8001fe2: 607b str r3, [r7, #4] 8001fe4: 4b29 ldr r3, [pc, #164] ; (800208c ) 8001fe6: 6c1b ldr r3, [r3, #64] ; 0x40 8001fe8: 4a28 ldr r2, [pc, #160] ; (800208c ) 8001fea: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8001fee: 6413 str r3, [r2, #64] ; 0x40 8001ff0: 4b26 ldr r3, [pc, #152] ; (800208c ) 8001ff2: 6c1b ldr r3, [r3, #64] ; 0x40 8001ff4: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8001ff8: 607b str r3, [r7, #4] 8001ffa: 687b ldr r3, [r7, #4] __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 8001ffc: 2300 movs r3, #0 8001ffe: 603b str r3, [r7, #0] 8002000: 4b23 ldr r3, [pc, #140] ; (8002090 ) 8002002: 681b ldr r3, [r3, #0] 8002004: 4a22 ldr r2, [pc, #136] ; (8002090 ) 8002006: f443 4340 orr.w r3, r3, #49152 ; 0xc000 800200a: 6013 str r3, [r2, #0] 800200c: 4b20 ldr r3, [pc, #128] ; (8002090 ) 800200e: 681b ldr r3, [r3, #0] 8002010: f403 4340 and.w r3, r3, #49152 ; 0xc000 8002014: 603b str r3, [r7, #0] 8002016: 683b ldr r3, [r7, #0] /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; 8002018: 2302 movs r3, #2 800201a: 61fb str r3, [r7, #28] RCC_OscInitStruct.HSIState = RCC_HSI_ON; 800201c: 2301 movs r3, #1 800201e: 62bb str r3, [r7, #40] ; 0x28 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 8002020: 2310 movs r3, #16 8002022: 62fb str r3, [r7, #44] ; 0x2c RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 8002024: 2302 movs r3, #2 8002026: 637b str r3, [r7, #52] ; 0x34 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; 8002028: 2300 movs r3, #0 800202a: 63bb str r3, [r7, #56] ; 0x38 RCC_OscInitStruct.PLL.PLLM = 16; 800202c: 2310 movs r3, #16 800202e: 63fb str r3, [r7, #60] ; 0x3c RCC_OscInitStruct.PLL.PLLN = 336; 8002030: f44f 73a8 mov.w r3, #336 ; 0x150 8002034: 643b str r3, [r7, #64] ; 0x40 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; 8002036: 2304 movs r3, #4 8002038: 647b str r3, [r7, #68] ; 0x44 RCC_OscInitStruct.PLL.PLLQ = 4; 800203a: 2304 movs r3, #4 800203c: 64bb str r3, [r7, #72] ; 0x48 RCC_OscInitStruct.PLL.PLLR = 2; 800203e: 2302 movs r3, #2 8002040: 64fb str r3, [r7, #76] ; 0x4c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8002042: f107 031c add.w r3, r7, #28 8002046: 4618 mov r0, r3 8002048: f7fe ff96 bl 8000f78 800204c: 4603 mov r3, r0 800204e: 2b00 cmp r3, #0 8002050: d001 beq.n 8002056 { Error_Handler(); 8002052: f000 f8e7 bl 8002224 } /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8002056: 230f movs r3, #15 8002058: 60bb str r3, [r7, #8] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 800205a: 2302 movs r3, #2 800205c: 60fb str r3, [r7, #12] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 800205e: 2300 movs r3, #0 8002060: 613b str r3, [r7, #16] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 8002062: f44f 5380 mov.w r3, #4096 ; 0x1000 8002066: 617b str r3, [r7, #20] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 8002068: 2300 movs r3, #0 800206a: 61bb str r3, [r7, #24] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 800206c: f107 0308 add.w r3, r7, #8 8002070: 2102 movs r1, #2 8002072: 4618 mov r0, r3 8002074: f7fe fd92 bl 8000b9c 8002078: 4603 mov r3, r0 800207a: 2b00 cmp r3, #0 800207c: d001 beq.n 8002082 { Error_Handler(); 800207e: f000 f8d1 bl 8002224 } } 8002082: bf00 nop 8002084: 3750 adds r7, #80 ; 0x50 8002086: 46bd mov sp, r7 8002088: bd80 pop {r7, pc} 800208a: bf00 nop 800208c: 40023800 .word 0x40023800 8002090: 40007000 .word 0x40007000 08002094 : /** * @brief NVIC Configuration. * @retval None */ static void MX_NVIC_Init(void) { 8002094: b580 push {r7, lr} 8002096: af00 add r7, sp, #0 /* EXTI15_10_IRQn interrupt configuration */ HAL_NVIC_SetPriority(EXTI15_10_IRQn, 0, 0); 8002098: 2200 movs r2, #0 800209a: 2100 movs r1, #0 800209c: 2028 movs r0, #40 ; 0x28 800209e: f7fe fba2 bl 80007e6 HAL_NVIC_EnableIRQ(EXTI15_10_IRQn); 80020a2: 2028 movs r0, #40 ; 0x28 80020a4: f7fe fbbb bl 800081e } 80020a8: bf00 nop 80020aa: bd80 pop {r7, pc} 080020ac : * @brief USART2 Initialization Function * @param None * @retval None */ static void MX_USART2_UART_Init(void) { 80020ac: b580 push {r7, lr} 80020ae: af00 add r7, sp, #0 /* USER CODE END USART2_Init 0 */ /* USER CODE BEGIN USART2_Init 1 */ /* USER CODE END USART2_Init 1 */ huart2.Instance = USART2; 80020b0: 4b11 ldr r3, [pc, #68] ; (80020f8 ) 80020b2: 4a12 ldr r2, [pc, #72] ; (80020fc ) 80020b4: 601a str r2, [r3, #0] huart2.Init.BaudRate = 115200; 80020b6: 4b10 ldr r3, [pc, #64] ; (80020f8 ) 80020b8: f44f 32e1 mov.w r2, #115200 ; 0x1c200 80020bc: 605a str r2, [r3, #4] huart2.Init.WordLength = UART_WORDLENGTH_8B; 80020be: 4b0e ldr r3, [pc, #56] ; (80020f8 ) 80020c0: 2200 movs r2, #0 80020c2: 609a str r2, [r3, #8] huart2.Init.StopBits = UART_STOPBITS_1; 80020c4: 4b0c ldr r3, [pc, #48] ; (80020f8 ) 80020c6: 2200 movs r2, #0 80020c8: 60da str r2, [r3, #12] huart2.Init.Parity = UART_PARITY_NONE; 80020ca: 4b0b ldr r3, [pc, #44] ; (80020f8 ) 80020cc: 2200 movs r2, #0 80020ce: 611a str r2, [r3, #16] huart2.Init.Mode = UART_MODE_TX_RX; 80020d0: 4b09 ldr r3, [pc, #36] ; (80020f8 ) 80020d2: 220c movs r2, #12 80020d4: 615a str r2, [r3, #20] huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; 80020d6: 4b08 ldr r3, [pc, #32] ; (80020f8 ) 80020d8: 2200 movs r2, #0 80020da: 619a str r2, [r3, #24] huart2.Init.OverSampling = UART_OVERSAMPLING_16; 80020dc: 4b06 ldr r3, [pc, #24] ; (80020f8 ) 80020de: 2200 movs r2, #0 80020e0: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart2) != HAL_OK) 80020e2: 4805 ldr r0, [pc, #20] ; (80020f8 ) 80020e4: f7ff f98a bl 80013fc 80020e8: 4603 mov r3, r0 80020ea: 2b00 cmp r3, #0 80020ec: d001 beq.n 80020f2 { Error_Handler(); 80020ee: f000 f899 bl 8002224 } /* USER CODE BEGIN USART2_Init 2 */ /* USER CODE END USART2_Init 2 */ } 80020f2: bf00 nop 80020f4: bd80 pop {r7, pc} 80020f6: bf00 nop 80020f8: 200000e4 .word 0x200000e4 80020fc: 40004400 .word 0x40004400 08002100 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 8002100: b580 push {r7, lr} 8002102: b08a sub sp, #40 ; 0x28 8002104: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8002106: f107 0314 add.w r3, r7, #20 800210a: 2200 movs r2, #0 800210c: 601a str r2, [r3, #0] 800210e: 605a str r2, [r3, #4] 8002110: 609a str r2, [r3, #8] 8002112: 60da str r2, [r3, #12] 8002114: 611a str r2, [r3, #16] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); 8002116: 2300 movs r3, #0 8002118: 613b str r3, [r7, #16] 800211a: 4b3e ldr r3, [pc, #248] ; (8002214 ) 800211c: 6b1b ldr r3, [r3, #48] ; 0x30 800211e: 4a3d ldr r2, [pc, #244] ; (8002214 ) 8002120: f043 0304 orr.w r3, r3, #4 8002124: 6313 str r3, [r2, #48] ; 0x30 8002126: 4b3b ldr r3, [pc, #236] ; (8002214 ) 8002128: 6b1b ldr r3, [r3, #48] ; 0x30 800212a: f003 0304 and.w r3, r3, #4 800212e: 613b str r3, [r7, #16] 8002130: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOH_CLK_ENABLE(); 8002132: 2300 movs r3, #0 8002134: 60fb str r3, [r7, #12] 8002136: 4b37 ldr r3, [pc, #220] ; (8002214 ) 8002138: 6b1b ldr r3, [r3, #48] ; 0x30 800213a: 4a36 ldr r2, [pc, #216] ; (8002214 ) 800213c: f043 0380 orr.w r3, r3, #128 ; 0x80 8002140: 6313 str r3, [r2, #48] ; 0x30 8002142: 4b34 ldr r3, [pc, #208] ; (8002214 ) 8002144: 6b1b ldr r3, [r3, #48] ; 0x30 8002146: f003 0380 and.w r3, r3, #128 ; 0x80 800214a: 60fb str r3, [r7, #12] 800214c: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 800214e: 2300 movs r3, #0 8002150: 60bb str r3, [r7, #8] 8002152: 4b30 ldr r3, [pc, #192] ; (8002214 ) 8002154: 6b1b ldr r3, [r3, #48] ; 0x30 8002156: 4a2f ldr r2, [pc, #188] ; (8002214 ) 8002158: f043 0301 orr.w r3, r3, #1 800215c: 6313 str r3, [r2, #48] ; 0x30 800215e: 4b2d ldr r3, [pc, #180] ; (8002214 ) 8002160: 6b1b ldr r3, [r3, #48] ; 0x30 8002162: f003 0301 and.w r3, r3, #1 8002166: 60bb str r3, [r7, #8] 8002168: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOB_CLK_ENABLE(); 800216a: 2300 movs r3, #0 800216c: 607b str r3, [r7, #4] 800216e: 4b29 ldr r3, [pc, #164] ; (8002214 ) 8002170: 6b1b ldr r3, [r3, #48] ; 0x30 8002172: 4a28 ldr r2, [pc, #160] ; (8002214 ) 8002174: f043 0302 orr.w r3, r3, #2 8002178: 6313 str r3, [r2, #48] ; 0x30 800217a: 4b26 ldr r3, [pc, #152] ; (8002214 ) 800217c: 6b1b ldr r3, [r3, #48] ; 0x30 800217e: f003 0302 and.w r3, r3, #2 8002182: 607b str r3, [r7, #4] 8002184: 687b ldr r3, [r7, #4] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOC, GPIO_PIN_3|PLL_EN_Pin|PLL_DATA_Pin|PLL_CLK_Pin, GPIO_PIN_RESET); 8002186: 2200 movs r2, #0 8002188: f44f 71b4 mov.w r1, #360 ; 0x168 800218c: 4822 ldr r0, [pc, #136] ; (8002218 ) 800218e: f7fe fcd3 bl 8000b38 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET); 8002192: 2200 movs r2, #0 8002194: 2120 movs r1, #32 8002196: 4821 ldr r0, [pc, #132] ; (800221c ) 8002198: f7fe fcce bl 8000b38 /*Configure GPIO pin : B1_Pin */ GPIO_InitStruct.Pin = B1_Pin; 800219c: f44f 5300 mov.w r3, #8192 ; 0x2000 80021a0: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; 80021a2: 4b1f ldr r3, [pc, #124] ; (8002220 ) 80021a4: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80021a6: 2300 movs r3, #0 80021a8: 61fb str r3, [r7, #28] HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct); 80021aa: f107 0314 add.w r3, r7, #20 80021ae: 4619 mov r1, r3 80021b0: 4819 ldr r0, [pc, #100] ; (8002218 ) 80021b2: f7fe fb4f bl 8000854 /*Configure GPIO pins : PC3 PLL_EN_Pin PLL_DATA_Pin PLL_CLK_Pin */ GPIO_InitStruct.Pin = GPIO_PIN_3|PLL_EN_Pin|PLL_DATA_Pin|PLL_CLK_Pin; 80021b6: f44f 73b4 mov.w r3, #360 ; 0x168 80021ba: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80021bc: 2301 movs r3, #1 80021be: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80021c0: 2300 movs r3, #0 80021c2: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80021c4: 2300 movs r3, #0 80021c6: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 80021c8: f107 0314 add.w r3, r7, #20 80021cc: 4619 mov r1, r3 80021ce: 4812 ldr r0, [pc, #72] ; (8002218 ) 80021d0: f7fe fb40 bl 8000854 /*Configure GPIO pin : LD2_Pin */ GPIO_InitStruct.Pin = LD2_Pin; 80021d4: 2320 movs r3, #32 80021d6: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80021d8: 2301 movs r3, #1 80021da: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80021dc: 2300 movs r3, #0 80021de: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80021e0: 2300 movs r3, #0 80021e2: 623b str r3, [r7, #32] HAL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct); 80021e4: f107 0314 add.w r3, r7, #20 80021e8: 4619 mov r1, r3 80021ea: 480c ldr r0, [pc, #48] ; (800221c ) 80021ec: f7fe fb32 bl 8000854 /*Configure GPIO pin : PA12 */ GPIO_InitStruct.Pin = GPIO_PIN_12; 80021f0: f44f 5380 mov.w r3, #4096 ; 0x1000 80021f4: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80021f6: 2300 movs r3, #0 80021f8: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80021fa: 2300 movs r3, #0 80021fc: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80021fe: f107 0314 add.w r3, r7, #20 8002202: 4619 mov r1, r3 8002204: 4805 ldr r0, [pc, #20] ; (800221c ) 8002206: f7fe fb25 bl 8000854 } 800220a: bf00 nop 800220c: 3728 adds r7, #40 ; 0x28 800220e: 46bd mov sp, r7 8002210: bd80 pop {r7, pc} 8002212: bf00 nop 8002214: 40023800 .word 0x40023800 8002218: 40020800 .word 0x40020800 800221c: 40020000 .word 0x40020000 8002220: 10210000 .word 0x10210000 08002224 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8002224: b480 push {r7} 8002226: af00 add r7, sp, #0 /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ /* USER CODE END Error_Handler_Debug */ } 8002228: bf00 nop 800222a: 46bd mov sp, r7 800222c: f85d 7b04 ldr.w r7, [sp], #4 8002230: 4770 bx lr ... 08002234 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8002234: b580 push {r7, lr} 8002236: b082 sub sp, #8 8002238: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 800223a: 2300 movs r3, #0 800223c: 607b str r3, [r7, #4] 800223e: 4b10 ldr r3, [pc, #64] ; (8002280 ) 8002240: 6c5b ldr r3, [r3, #68] ; 0x44 8002242: 4a0f ldr r2, [pc, #60] ; (8002280 ) 8002244: f443 4380 orr.w r3, r3, #16384 ; 0x4000 8002248: 6453 str r3, [r2, #68] ; 0x44 800224a: 4b0d ldr r3, [pc, #52] ; (8002280 ) 800224c: 6c5b ldr r3, [r3, #68] ; 0x44 800224e: f403 4380 and.w r3, r3, #16384 ; 0x4000 8002252: 607b str r3, [r7, #4] 8002254: 687b ldr r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); 8002256: 2300 movs r3, #0 8002258: 603b str r3, [r7, #0] 800225a: 4b09 ldr r3, [pc, #36] ; (8002280 ) 800225c: 6c1b ldr r3, [r3, #64] ; 0x40 800225e: 4a08 ldr r2, [pc, #32] ; (8002280 ) 8002260: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8002264: 6413 str r3, [r2, #64] ; 0x40 8002266: 4b06 ldr r3, [pc, #24] ; (8002280 ) 8002268: 6c1b ldr r3, [r3, #64] ; 0x40 800226a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 800226e: 603b str r3, [r7, #0] 8002270: 683b ldr r3, [r7, #0] HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_0); 8002272: 2007 movs r0, #7 8002274: f7fe faac bl 80007d0 /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8002278: bf00 nop 800227a: 3708 adds r7, #8 800227c: 46bd mov sp, r7 800227e: bd80 pop {r7, pc} 8002280: 40023800 .word 0x40023800 08002284 : * This function configures the hardware resources used in this example * @param huart: UART handle pointer * @retval None */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { 8002284: b580 push {r7, lr} 8002286: b08a sub sp, #40 ; 0x28 8002288: af00 add r7, sp, #0 800228a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800228c: f107 0314 add.w r3, r7, #20 8002290: 2200 movs r2, #0 8002292: 601a str r2, [r3, #0] 8002294: 605a str r2, [r3, #4] 8002296: 609a str r2, [r3, #8] 8002298: 60da str r2, [r3, #12] 800229a: 611a str r2, [r3, #16] if(huart->Instance==USART2) 800229c: 687b ldr r3, [r7, #4] 800229e: 681b ldr r3, [r3, #0] 80022a0: 4a19 ldr r2, [pc, #100] ; (8002308 ) 80022a2: 4293 cmp r3, r2 80022a4: d12b bne.n 80022fe { /* USER CODE BEGIN USART2_MspInit 0 */ /* USER CODE END USART2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); 80022a6: 2300 movs r3, #0 80022a8: 613b str r3, [r7, #16] 80022aa: 4b18 ldr r3, [pc, #96] ; (800230c ) 80022ac: 6c1b ldr r3, [r3, #64] ; 0x40 80022ae: 4a17 ldr r2, [pc, #92] ; (800230c ) 80022b0: f443 3300 orr.w r3, r3, #131072 ; 0x20000 80022b4: 6413 str r3, [r2, #64] ; 0x40 80022b6: 4b15 ldr r3, [pc, #84] ; (800230c ) 80022b8: 6c1b ldr r3, [r3, #64] ; 0x40 80022ba: f403 3300 and.w r3, r3, #131072 ; 0x20000 80022be: 613b str r3, [r7, #16] 80022c0: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 80022c2: 2300 movs r3, #0 80022c4: 60fb str r3, [r7, #12] 80022c6: 4b11 ldr r3, [pc, #68] ; (800230c ) 80022c8: 6b1b ldr r3, [r3, #48] ; 0x30 80022ca: 4a10 ldr r2, [pc, #64] ; (800230c ) 80022cc: f043 0301 orr.w r3, r3, #1 80022d0: 6313 str r3, [r2, #48] ; 0x30 80022d2: 4b0e ldr r3, [pc, #56] ; (800230c ) 80022d4: 6b1b ldr r3, [r3, #48] ; 0x30 80022d6: f003 0301 and.w r3, r3, #1 80022da: 60fb str r3, [r7, #12] 80022dc: 68fb ldr r3, [r7, #12] /**USART2 GPIO Configuration PA2 ------> USART2_TX PA3 ------> USART2_RX */ GPIO_InitStruct.Pin = USART_TX_Pin|USART_RX_Pin; 80022de: 230c movs r3, #12 80022e0: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80022e2: 2302 movs r3, #2 80022e4: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_PULLUP; 80022e6: 2301 movs r3, #1 80022e8: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 80022ea: 2303 movs r3, #3 80022ec: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF7_USART2; 80022ee: 2307 movs r3, #7 80022f0: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80022f2: f107 0314 add.w r3, r7, #20 80022f6: 4619 mov r1, r3 80022f8: 4805 ldr r0, [pc, #20] ; (8002310 ) 80022fa: f7fe faab bl 8000854 /* USER CODE BEGIN USART2_MspInit 1 */ /* USER CODE END USART2_MspInit 1 */ } } 80022fe: bf00 nop 8002300: 3728 adds r7, #40 ; 0x28 8002302: 46bd mov sp, r7 8002304: bd80 pop {r7, pc} 8002306: bf00 nop 8002308: 40004400 .word 0x40004400 800230c: 40023800 .word 0x40023800 8002310: 40020000 .word 0x40020000 08002314 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8002314: b480 push {r7} 8002316: af00 add r7, sp, #0 /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ /* USER CODE END NonMaskableInt_IRQn 1 */ } 8002318: bf00 nop 800231a: 46bd mov sp, r7 800231c: f85d 7b04 ldr.w r7, [sp], #4 8002320: 4770 bx lr 08002322 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8002322: b480 push {r7} 8002324: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8002326: e7fe b.n 8002326 08002328 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8002328: b480 push {r7} 800232a: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 800232c: e7fe b.n 800232c 0800232e : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { 800232e: b480 push {r7} 8002330: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 8002332: e7fe b.n 8002332 08002334 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8002334: b480 push {r7} 8002336: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8002338: e7fe b.n 8002338 0800233a : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 800233a: b480 push {r7} 800233c: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 800233e: bf00 nop 8002340: 46bd mov sp, r7 8002342: f85d 7b04 ldr.w r7, [sp], #4 8002346: 4770 bx lr 08002348 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 8002348: b480 push {r7} 800234a: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 800234c: bf00 nop 800234e: 46bd mov sp, r7 8002350: f85d 7b04 ldr.w r7, [sp], #4 8002354: 4770 bx lr 08002356 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8002356: b480 push {r7} 8002358: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 800235a: bf00 nop 800235c: 46bd mov sp, r7 800235e: f85d 7b04 ldr.w r7, [sp], #4 8002362: 4770 bx lr 08002364 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 8002364: b580 push {r7, lr} 8002366: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 8002368: f7fe f920 bl 80005ac /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 800236c: bf00 nop 800236e: bd80 pop {r7, pc} 08002370 : /** * @brief This function handles EXTI line[15:10] interrupts. */ void EXTI15_10_IRQHandler(void) { 8002370: b580 push {r7, lr} 8002372: af00 add r7, sp, #0 /* USER CODE BEGIN EXTI15_10_IRQn 0 */ /* USER CODE END EXTI15_10_IRQn 0 */ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_13); 8002374: f44f 5000 mov.w r0, #8192 ; 0x2000 8002378: f7fe fbf8 bl 8000b6c /* USER CODE BEGIN EXTI15_10_IRQn 1 */ /* USER CODE END EXTI15_10_IRQn 1 */ } 800237c: bf00 nop 800237e: bd80 pop {r7, pc} 08002380 <_read>: _kill(status, -1); while (1) {} /* Make sure we hang here */ } __attribute__((weak)) int _read(int file, char *ptr, int len) { 8002380: b580 push {r7, lr} 8002382: b086 sub sp, #24 8002384: af00 add r7, sp, #0 8002386: 60f8 str r0, [r7, #12] 8002388: 60b9 str r1, [r7, #8] 800238a: 607a str r2, [r7, #4] int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 800238c: 2300 movs r3, #0 800238e: 617b str r3, [r7, #20] 8002390: e00a b.n 80023a8 <_read+0x28> { *ptr++ = __io_getchar(); 8002392: f3af 8000 nop.w 8002396: 4601 mov r1, r0 8002398: 68bb ldr r3, [r7, #8] 800239a: 1c5a adds r2, r3, #1 800239c: 60ba str r2, [r7, #8] 800239e: b2ca uxtb r2, r1 80023a0: 701a strb r2, [r3, #0] for (DataIdx = 0; DataIdx < len; DataIdx++) 80023a2: 697b ldr r3, [r7, #20] 80023a4: 3301 adds r3, #1 80023a6: 617b str r3, [r7, #20] 80023a8: 697a ldr r2, [r7, #20] 80023aa: 687b ldr r3, [r7, #4] 80023ac: 429a cmp r2, r3 80023ae: dbf0 blt.n 8002392 <_read+0x12> } return len; 80023b0: 687b ldr r3, [r7, #4] } 80023b2: 4618 mov r0, r3 80023b4: 3718 adds r7, #24 80023b6: 46bd mov sp, r7 80023b8: bd80 pop {r7, pc} 080023ba <_close>: } return len; } int _close(int file) { 80023ba: b480 push {r7} 80023bc: b083 sub sp, #12 80023be: af00 add r7, sp, #0 80023c0: 6078 str r0, [r7, #4] return -1; 80023c2: f04f 33ff mov.w r3, #4294967295 } 80023c6: 4618 mov r0, r3 80023c8: 370c adds r7, #12 80023ca: 46bd mov sp, r7 80023cc: f85d 7b04 ldr.w r7, [sp], #4 80023d0: 4770 bx lr 080023d2 <_fstat>: int _fstat(int file, struct stat *st) { 80023d2: b480 push {r7} 80023d4: b083 sub sp, #12 80023d6: af00 add r7, sp, #0 80023d8: 6078 str r0, [r7, #4] 80023da: 6039 str r1, [r7, #0] st->st_mode = S_IFCHR; 80023dc: 683b ldr r3, [r7, #0] 80023de: f44f 5200 mov.w r2, #8192 ; 0x2000 80023e2: 605a str r2, [r3, #4] return 0; 80023e4: 2300 movs r3, #0 } 80023e6: 4618 mov r0, r3 80023e8: 370c adds r7, #12 80023ea: 46bd mov sp, r7 80023ec: f85d 7b04 ldr.w r7, [sp], #4 80023f0: 4770 bx lr 080023f2 <_isatty>: int _isatty(int file) { 80023f2: b480 push {r7} 80023f4: b083 sub sp, #12 80023f6: af00 add r7, sp, #0 80023f8: 6078 str r0, [r7, #4] return 1; 80023fa: 2301 movs r3, #1 } 80023fc: 4618 mov r0, r3 80023fe: 370c adds r7, #12 8002400: 46bd mov sp, r7 8002402: f85d 7b04 ldr.w r7, [sp], #4 8002406: 4770 bx lr 08002408 <_lseek>: int _lseek(int file, int ptr, int dir) { 8002408: b480 push {r7} 800240a: b085 sub sp, #20 800240c: af00 add r7, sp, #0 800240e: 60f8 str r0, [r7, #12] 8002410: 60b9 str r1, [r7, #8] 8002412: 607a str r2, [r7, #4] return 0; 8002414: 2300 movs r3, #0 } 8002416: 4618 mov r0, r3 8002418: 3714 adds r7, #20 800241a: 46bd mov sp, r7 800241c: f85d 7b04 ldr.w r7, [sp], #4 8002420: 4770 bx lr ... 08002424 <_sbrk>: /** _sbrk Increase program data space. Malloc and related functions depend on this **/ caddr_t _sbrk(int incr) { 8002424: b580 push {r7, lr} 8002426: b084 sub sp, #16 8002428: af00 add r7, sp, #0 800242a: 6078 str r0, [r7, #4] extern char end asm("end"); static char *heap_end; char *prev_heap_end; if (heap_end == 0) 800242c: 4b11 ldr r3, [pc, #68] ; (8002474 <_sbrk+0x50>) 800242e: 681b ldr r3, [r3, #0] 8002430: 2b00 cmp r3, #0 8002432: d102 bne.n 800243a <_sbrk+0x16> heap_end = &end; 8002434: 4b0f ldr r3, [pc, #60] ; (8002474 <_sbrk+0x50>) 8002436: 4a10 ldr r2, [pc, #64] ; (8002478 <_sbrk+0x54>) 8002438: 601a str r2, [r3, #0] prev_heap_end = heap_end; 800243a: 4b0e ldr r3, [pc, #56] ; (8002474 <_sbrk+0x50>) 800243c: 681b ldr r3, [r3, #0] 800243e: 60fb str r3, [r7, #12] if (heap_end + incr > stack_ptr) 8002440: 4b0c ldr r3, [pc, #48] ; (8002474 <_sbrk+0x50>) 8002442: 681a ldr r2, [r3, #0] 8002444: 687b ldr r3, [r7, #4] 8002446: 4413 add r3, r2 8002448: 466a mov r2, sp 800244a: 4293 cmp r3, r2 800244c: d907 bls.n 800245e <_sbrk+0x3a> { errno = ENOMEM; 800244e: f000 f875 bl 800253c <__errno> 8002452: 4602 mov r2, r0 8002454: 230c movs r3, #12 8002456: 6013 str r3, [r2, #0] return (caddr_t) -1; 8002458: f04f 33ff mov.w r3, #4294967295 800245c: e006 b.n 800246c <_sbrk+0x48> } heap_end += incr; 800245e: 4b05 ldr r3, [pc, #20] ; (8002474 <_sbrk+0x50>) 8002460: 681a ldr r2, [r3, #0] 8002462: 687b ldr r3, [r7, #4] 8002464: 4413 add r3, r2 8002466: 4a03 ldr r2, [pc, #12] ; (8002474 <_sbrk+0x50>) 8002468: 6013 str r3, [r2, #0] return (caddr_t) prev_heap_end; 800246a: 68fb ldr r3, [r7, #12] } 800246c: 4618 mov r0, r3 800246e: 3710 adds r7, #16 8002470: 46bd mov sp, r7 8002472: bd80 pop {r7, pc} 8002474: 200000d4 .word 0x200000d4 8002478: 20000128 .word 0x20000128 0800247c : * configuration. * @param None * @retval None */ void SystemInit(void) { 800247c: b480 push {r7} 800247e: af00 add r7, sp, #0 /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ 8002480: 4b16 ldr r3, [pc, #88] ; (80024dc ) 8002482: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 8002486: 4a15 ldr r2, [pc, #84] ; (80024dc ) 8002488: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000 800248c: f8c2 3088 str.w r3, [r2, #136] ; 0x88 #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set HSION bit */ RCC->CR |= (uint32_t)0x00000001; 8002490: 4b13 ldr r3, [pc, #76] ; (80024e0 ) 8002492: 681b ldr r3, [r3, #0] 8002494: 4a12 ldr r2, [pc, #72] ; (80024e0 ) 8002496: f043 0301 orr.w r3, r3, #1 800249a: 6013 str r3, [r2, #0] /* Reset CFGR register */ RCC->CFGR = 0x00000000; 800249c: 4b10 ldr r3, [pc, #64] ; (80024e0 ) 800249e: 2200 movs r2, #0 80024a0: 609a str r2, [r3, #8] /* Reset HSEON, CSSON and PLLON bits */ RCC->CR &= (uint32_t)0xFEF6FFFF; 80024a2: 4b0f ldr r3, [pc, #60] ; (80024e0 ) 80024a4: 681b ldr r3, [r3, #0] 80024a6: 4a0e ldr r2, [pc, #56] ; (80024e0 ) 80024a8: f023 7384 bic.w r3, r3, #17301504 ; 0x1080000 80024ac: f423 3380 bic.w r3, r3, #65536 ; 0x10000 80024b0: 6013 str r3, [r2, #0] /* Reset PLLCFGR register */ RCC->PLLCFGR = 0x24003010; 80024b2: 4b0b ldr r3, [pc, #44] ; (80024e0 ) 80024b4: 4a0b ldr r2, [pc, #44] ; (80024e4 ) 80024b6: 605a str r2, [r3, #4] /* Reset HSEBYP bit */ RCC->CR &= (uint32_t)0xFFFBFFFF; 80024b8: 4b09 ldr r3, [pc, #36] ; (80024e0 ) 80024ba: 681b ldr r3, [r3, #0] 80024bc: 4a08 ldr r2, [pc, #32] ; (80024e0 ) 80024be: f423 2380 bic.w r3, r3, #262144 ; 0x40000 80024c2: 6013 str r3, [r2, #0] /* Disable all interrupts */ RCC->CIR = 0x00000000; 80024c4: 4b06 ldr r3, [pc, #24] ; (80024e0 ) 80024c6: 2200 movs r2, #0 80024c8: 60da str r2, [r3, #12] /* Configure the Vector Table location add offset address ------------------*/ #ifdef VECT_TAB_SRAM SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #else SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ 80024ca: 4b04 ldr r3, [pc, #16] ; (80024dc ) 80024cc: f04f 6200 mov.w r2, #134217728 ; 0x8000000 80024d0: 609a str r2, [r3, #8] #endif } 80024d2: bf00 nop 80024d4: 46bd mov sp, r7 80024d6: f85d 7b04 ldr.w r7, [sp], #4 80024da: 4770 bx lr 80024dc: e000ed00 .word 0xe000ed00 80024e0: 40023800 .word 0x40023800 80024e4: 24003010 .word 0x24003010 080024e8 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* set stack pointer */ 80024e8: f8df d034 ldr.w sp, [pc, #52] ; 8002520 /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 80024ec: 2100 movs r1, #0 b LoopCopyDataInit 80024ee: e003 b.n 80024f8 080024f0 : CopyDataInit: ldr r3, =_sidata 80024f0: 4b0c ldr r3, [pc, #48] ; (8002524 ) ldr r3, [r3, r1] 80024f2: 585b ldr r3, [r3, r1] str r3, [r0, r1] 80024f4: 5043 str r3, [r0, r1] adds r1, r1, #4 80024f6: 3104 adds r1, #4 080024f8 : LoopCopyDataInit: ldr r0, =_sdata 80024f8: 480b ldr r0, [pc, #44] ; (8002528 ) ldr r3, =_edata 80024fa: 4b0c ldr r3, [pc, #48] ; (800252c ) adds r2, r0, r1 80024fc: 1842 adds r2, r0, r1 cmp r2, r3 80024fe: 429a cmp r2, r3 bcc CopyDataInit 8002500: d3f6 bcc.n 80024f0 ldr r2, =_sbss 8002502: 4a0b ldr r2, [pc, #44] ; (8002530 ) b LoopFillZerobss 8002504: e002 b.n 800250c 08002506 : /* Zero fill the bss segment. */ FillZerobss: movs r3, #0 8002506: 2300 movs r3, #0 str r3, [r2], #4 8002508: f842 3b04 str.w r3, [r2], #4 0800250c : LoopFillZerobss: ldr r3, = _ebss 800250c: 4b09 ldr r3, [pc, #36] ; (8002534 ) cmp r2, r3 800250e: 429a cmp r2, r3 bcc FillZerobss 8002510: d3f9 bcc.n 8002506 /* Call the clock system intitialization function.*/ bl SystemInit 8002512: f7ff ffb3 bl 800247c /* Call static constructors */ bl __libc_init_array 8002516: f000 f817 bl 8002548 <__libc_init_array> /* Call the application's entry point.*/ bl main 800251a: f7ff fd0d bl 8001f38
bx lr 800251e: 4770 bx lr ldr sp, =_estack /* set stack pointer */ 8002520: 20008000 .word 0x20008000 ldr r3, =_sidata 8002524: 080030a0 .word 0x080030a0 ldr r0, =_sdata 8002528: 20000000 .word 0x20000000 ldr r3, =_edata 800252c: 2000009c .word 0x2000009c ldr r2, =_sbss 8002530: 2000009c .word 0x2000009c ldr r3, = _ebss 8002534: 20000128 .word 0x20000128 08002538 : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8002538: e7fe b.n 8002538 ... 0800253c <__errno>: 800253c: 4b01 ldr r3, [pc, #4] ; (8002544 <__errno+0x8>) 800253e: 6818 ldr r0, [r3, #0] 8002540: 4770 bx lr 8002542: bf00 nop 8002544: 20000038 .word 0x20000038 08002548 <__libc_init_array>: 8002548: b570 push {r4, r5, r6, lr} 800254a: 4e0d ldr r6, [pc, #52] ; (8002580 <__libc_init_array+0x38>) 800254c: 4c0d ldr r4, [pc, #52] ; (8002584 <__libc_init_array+0x3c>) 800254e: 1ba4 subs r4, r4, r6 8002550: 10a4 asrs r4, r4, #2 8002552: 2500 movs r5, #0 8002554: 42a5 cmp r5, r4 8002556: d109 bne.n 800256c <__libc_init_array+0x24> 8002558: 4e0b ldr r6, [pc, #44] ; (8002588 <__libc_init_array+0x40>) 800255a: 4c0c ldr r4, [pc, #48] ; (800258c <__libc_init_array+0x44>) 800255c: f000 fd46 bl 8002fec <_init> 8002560: 1ba4 subs r4, r4, r6 8002562: 10a4 asrs r4, r4, #2 8002564: 2500 movs r5, #0 8002566: 42a5 cmp r5, r4 8002568: d105 bne.n 8002576 <__libc_init_array+0x2e> 800256a: bd70 pop {r4, r5, r6, pc} 800256c: f856 3025 ldr.w r3, [r6, r5, lsl #2] 8002570: 4798 blx r3 8002572: 3501 adds r5, #1 8002574: e7ee b.n 8002554 <__libc_init_array+0xc> 8002576: f856 3025 ldr.w r3, [r6, r5, lsl #2] 800257a: 4798 blx r3 800257c: 3501 adds r5, #1 800257e: e7f2 b.n 8002566 <__libc_init_array+0x1e> 8002580: 08003098 .word 0x08003098 8002584: 08003098 .word 0x08003098 8002588: 08003098 .word 0x08003098 800258c: 0800309c .word 0x0800309c 08002590 : 8002590: 4402 add r2, r0 8002592: 4603 mov r3, r0 8002594: 4293 cmp r3, r2 8002596: d100 bne.n 800259a 8002598: 4770 bx lr 800259a: f803 1b01 strb.w r1, [r3], #1 800259e: e7f9 b.n 8002594 080025a0 <_puts_r>: 80025a0: b570 push {r4, r5, r6, lr} 80025a2: 460e mov r6, r1 80025a4: 4605 mov r5, r0 80025a6: b118 cbz r0, 80025b0 <_puts_r+0x10> 80025a8: 6983 ldr r3, [r0, #24] 80025aa: b90b cbnz r3, 80025b0 <_puts_r+0x10> 80025ac: f000 fac2 bl 8002b34 <__sinit> 80025b0: 69ab ldr r3, [r5, #24] 80025b2: 68ac ldr r4, [r5, #8] 80025b4: b913 cbnz r3, 80025bc <_puts_r+0x1c> 80025b6: 4628 mov r0, r5 80025b8: f000 fabc bl 8002b34 <__sinit> 80025bc: 4b23 ldr r3, [pc, #140] ; (800264c <_puts_r+0xac>) 80025be: 429c cmp r4, r3 80025c0: d117 bne.n 80025f2 <_puts_r+0x52> 80025c2: 686c ldr r4, [r5, #4] 80025c4: 89a3 ldrh r3, [r4, #12] 80025c6: 071b lsls r3, r3, #28 80025c8: d51d bpl.n 8002606 <_puts_r+0x66> 80025ca: 6923 ldr r3, [r4, #16] 80025cc: b1db cbz r3, 8002606 <_puts_r+0x66> 80025ce: 3e01 subs r6, #1 80025d0: 68a3 ldr r3, [r4, #8] 80025d2: f816 1f01 ldrb.w r1, [r6, #1]! 80025d6: 3b01 subs r3, #1 80025d8: 60a3 str r3, [r4, #8] 80025da: b9e9 cbnz r1, 8002618 <_puts_r+0x78> 80025dc: 2b00 cmp r3, #0 80025de: da2e bge.n 800263e <_puts_r+0x9e> 80025e0: 4622 mov r2, r4 80025e2: 210a movs r1, #10 80025e4: 4628 mov r0, r5 80025e6: f000 f8f5 bl 80027d4 <__swbuf_r> 80025ea: 3001 adds r0, #1 80025ec: d011 beq.n 8002612 <_puts_r+0x72> 80025ee: 200a movs r0, #10 80025f0: e011 b.n 8002616 <_puts_r+0x76> 80025f2: 4b17 ldr r3, [pc, #92] ; (8002650 <_puts_r+0xb0>) 80025f4: 429c cmp r4, r3 80025f6: d101 bne.n 80025fc <_puts_r+0x5c> 80025f8: 68ac ldr r4, [r5, #8] 80025fa: e7e3 b.n 80025c4 <_puts_r+0x24> 80025fc: 4b15 ldr r3, [pc, #84] ; (8002654 <_puts_r+0xb4>) 80025fe: 429c cmp r4, r3 8002600: bf08 it eq 8002602: 68ec ldreq r4, [r5, #12] 8002604: e7de b.n 80025c4 <_puts_r+0x24> 8002606: 4621 mov r1, r4 8002608: 4628 mov r0, r5 800260a: f000 f935 bl 8002878 <__swsetup_r> 800260e: 2800 cmp r0, #0 8002610: d0dd beq.n 80025ce <_puts_r+0x2e> 8002612: f04f 30ff mov.w r0, #4294967295 8002616: bd70 pop {r4, r5, r6, pc} 8002618: 2b00 cmp r3, #0 800261a: da04 bge.n 8002626 <_puts_r+0x86> 800261c: 69a2 ldr r2, [r4, #24] 800261e: 429a cmp r2, r3 8002620: dc06 bgt.n 8002630 <_puts_r+0x90> 8002622: 290a cmp r1, #10 8002624: d004 beq.n 8002630 <_puts_r+0x90> 8002626: 6823 ldr r3, [r4, #0] 8002628: 1c5a adds r2, r3, #1 800262a: 6022 str r2, [r4, #0] 800262c: 7019 strb r1, [r3, #0] 800262e: e7cf b.n 80025d0 <_puts_r+0x30> 8002630: 4622 mov r2, r4 8002632: 4628 mov r0, r5 8002634: f000 f8ce bl 80027d4 <__swbuf_r> 8002638: 3001 adds r0, #1 800263a: d1c9 bne.n 80025d0 <_puts_r+0x30> 800263c: e7e9 b.n 8002612 <_puts_r+0x72> 800263e: 6823 ldr r3, [r4, #0] 8002640: 200a movs r0, #10 8002642: 1c5a adds r2, r3, #1 8002644: 6022 str r2, [r4, #0] 8002646: 7018 strb r0, [r3, #0] 8002648: e7e5 b.n 8002616 <_puts_r+0x76> 800264a: bf00 nop 800264c: 08003050 .word 0x08003050 8002650: 08003070 .word 0x08003070 8002654: 08003030 .word 0x08003030 08002658 : 8002658: 4b02 ldr r3, [pc, #8] ; (8002664 ) 800265a: 4601 mov r1, r0 800265c: 6818 ldr r0, [r3, #0] 800265e: f7ff bf9f b.w 80025a0 <_puts_r> 8002662: bf00 nop 8002664: 20000038 .word 0x20000038 08002668 : 8002668: 2900 cmp r1, #0 800266a: f44f 6380 mov.w r3, #1024 ; 0x400 800266e: bf0c ite eq 8002670: 2202 moveq r2, #2 8002672: 2200 movne r2, #0 8002674: f000 b800 b.w 8002678 08002678 : 8002678: e92d 43f7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr} 800267c: 461d mov r5, r3 800267e: 4b51 ldr r3, [pc, #324] ; (80027c4 ) 8002680: 681e ldr r6, [r3, #0] 8002682: 4604 mov r4, r0 8002684: 460f mov r7, r1 8002686: 4690 mov r8, r2 8002688: b126 cbz r6, 8002694 800268a: 69b3 ldr r3, [r6, #24] 800268c: b913 cbnz r3, 8002694 800268e: 4630 mov r0, r6 8002690: f000 fa50 bl 8002b34 <__sinit> 8002694: 4b4c ldr r3, [pc, #304] ; (80027c8 ) 8002696: 429c cmp r4, r3 8002698: d152 bne.n 8002740 800269a: 6874 ldr r4, [r6, #4] 800269c: f1b8 0f02 cmp.w r8, #2 80026a0: d006 beq.n 80026b0 80026a2: f1b8 0f01 cmp.w r8, #1 80026a6: f200 8089 bhi.w 80027bc 80026aa: 2d00 cmp r5, #0 80026ac: f2c0 8086 blt.w 80027bc 80026b0: 4621 mov r1, r4 80026b2: 4630 mov r0, r6 80026b4: f000 f9d4 bl 8002a60 <_fflush_r> 80026b8: 6b61 ldr r1, [r4, #52] ; 0x34 80026ba: b141 cbz r1, 80026ce 80026bc: f104 0344 add.w r3, r4, #68 ; 0x44 80026c0: 4299 cmp r1, r3 80026c2: d002 beq.n 80026ca 80026c4: 4630 mov r0, r6 80026c6: f000 fb2b bl 8002d20 <_free_r> 80026ca: 2300 movs r3, #0 80026cc: 6363 str r3, [r4, #52] ; 0x34 80026ce: 2300 movs r3, #0 80026d0: 61a3 str r3, [r4, #24] 80026d2: 6063 str r3, [r4, #4] 80026d4: 89a3 ldrh r3, [r4, #12] 80026d6: 061b lsls r3, r3, #24 80026d8: d503 bpl.n 80026e2 80026da: 6921 ldr r1, [r4, #16] 80026dc: 4630 mov r0, r6 80026de: f000 fb1f bl 8002d20 <_free_r> 80026e2: 89a3 ldrh r3, [r4, #12] 80026e4: f423 634a bic.w r3, r3, #3232 ; 0xca0 80026e8: f023 0303 bic.w r3, r3, #3 80026ec: f1b8 0f02 cmp.w r8, #2 80026f0: 81a3 strh r3, [r4, #12] 80026f2: d05d beq.n 80027b0 80026f4: ab01 add r3, sp, #4 80026f6: 466a mov r2, sp 80026f8: 4621 mov r1, r4 80026fa: 4630 mov r0, r6 80026fc: f000 faa4 bl 8002c48 <__swhatbuf_r> 8002700: 89a3 ldrh r3, [r4, #12] 8002702: 4318 orrs r0, r3 8002704: 81a0 strh r0, [r4, #12] 8002706: bb2d cbnz r5, 8002754 8002708: 9d00 ldr r5, [sp, #0] 800270a: 4628 mov r0, r5 800270c: f000 fb00 bl 8002d10 8002710: 4607 mov r7, r0 8002712: 2800 cmp r0, #0 8002714: d14e bne.n 80027b4 8002716: f8dd 9000 ldr.w r9, [sp] 800271a: 45a9 cmp r9, r5 800271c: d13c bne.n 8002798 800271e: f04f 30ff mov.w r0, #4294967295 8002722: 89a3 ldrh r3, [r4, #12] 8002724: f043 0302 orr.w r3, r3, #2 8002728: 81a3 strh r3, [r4, #12] 800272a: 2300 movs r3, #0 800272c: 60a3 str r3, [r4, #8] 800272e: f104 0347 add.w r3, r4, #71 ; 0x47 8002732: 6023 str r3, [r4, #0] 8002734: 6123 str r3, [r4, #16] 8002736: 2301 movs r3, #1 8002738: 6163 str r3, [r4, #20] 800273a: b003 add sp, #12 800273c: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} 8002740: 4b22 ldr r3, [pc, #136] ; (80027cc ) 8002742: 429c cmp r4, r3 8002744: d101 bne.n 800274a 8002746: 68b4 ldr r4, [r6, #8] 8002748: e7a8 b.n 800269c 800274a: 4b21 ldr r3, [pc, #132] ; (80027d0 ) 800274c: 429c cmp r4, r3 800274e: bf08 it eq 8002750: 68f4 ldreq r4, [r6, #12] 8002752: e7a3 b.n 800269c 8002754: 2f00 cmp r7, #0 8002756: d0d8 beq.n 800270a 8002758: 69b3 ldr r3, [r6, #24] 800275a: b913 cbnz r3, 8002762 800275c: 4630 mov r0, r6 800275e: f000 f9e9 bl 8002b34 <__sinit> 8002762: f1b8 0f01 cmp.w r8, #1 8002766: bf08 it eq 8002768: 89a3 ldrheq r3, [r4, #12] 800276a: 6027 str r7, [r4, #0] 800276c: bf04 itt eq 800276e: f043 0301 orreq.w r3, r3, #1 8002772: 81a3 strheq r3, [r4, #12] 8002774: 89a3 ldrh r3, [r4, #12] 8002776: f013 0008 ands.w r0, r3, #8 800277a: e9c4 7504 strd r7, r5, [r4, #16] 800277e: d01b beq.n 80027b8 8002780: f013 0001 ands.w r0, r3, #1 8002784: bf18 it ne 8002786: 426d negne r5, r5 8002788: f04f 0300 mov.w r3, #0 800278c: bf1d ittte ne 800278e: 60a3 strne r3, [r4, #8] 8002790: 61a5 strne r5, [r4, #24] 8002792: 4618 movne r0, r3 8002794: 60a5 streq r5, [r4, #8] 8002796: e7d0 b.n 800273a 8002798: 4648 mov r0, r9 800279a: f000 fab9 bl 8002d10 800279e: 4607 mov r7, r0 80027a0: 2800 cmp r0, #0 80027a2: d0bc beq.n 800271e 80027a4: 89a3 ldrh r3, [r4, #12] 80027a6: f043 0380 orr.w r3, r3, #128 ; 0x80 80027aa: 81a3 strh r3, [r4, #12] 80027ac: 464d mov r5, r9 80027ae: e7d3 b.n 8002758 80027b0: 2000 movs r0, #0 80027b2: e7b6 b.n 8002722 80027b4: 46a9 mov r9, r5 80027b6: e7f5 b.n 80027a4 80027b8: 60a0 str r0, [r4, #8] 80027ba: e7be b.n 800273a 80027bc: f04f 30ff mov.w r0, #4294967295 80027c0: e7bb b.n 800273a 80027c2: bf00 nop 80027c4: 20000038 .word 0x20000038 80027c8: 08003050 .word 0x08003050 80027cc: 08003070 .word 0x08003070 80027d0: 08003030 .word 0x08003030 080027d4 <__swbuf_r>: 80027d4: b5f8 push {r3, r4, r5, r6, r7, lr} 80027d6: 460e mov r6, r1 80027d8: 4614 mov r4, r2 80027da: 4605 mov r5, r0 80027dc: b118 cbz r0, 80027e6 <__swbuf_r+0x12> 80027de: 6983 ldr r3, [r0, #24] 80027e0: b90b cbnz r3, 80027e6 <__swbuf_r+0x12> 80027e2: f000 f9a7 bl 8002b34 <__sinit> 80027e6: 4b21 ldr r3, [pc, #132] ; (800286c <__swbuf_r+0x98>) 80027e8: 429c cmp r4, r3 80027ea: d12a bne.n 8002842 <__swbuf_r+0x6e> 80027ec: 686c ldr r4, [r5, #4] 80027ee: 69a3 ldr r3, [r4, #24] 80027f0: 60a3 str r3, [r4, #8] 80027f2: 89a3 ldrh r3, [r4, #12] 80027f4: 071a lsls r2, r3, #28 80027f6: d52e bpl.n 8002856 <__swbuf_r+0x82> 80027f8: 6923 ldr r3, [r4, #16] 80027fa: b363 cbz r3, 8002856 <__swbuf_r+0x82> 80027fc: 6923 ldr r3, [r4, #16] 80027fe: 6820 ldr r0, [r4, #0] 8002800: 1ac0 subs r0, r0, r3 8002802: 6963 ldr r3, [r4, #20] 8002804: b2f6 uxtb r6, r6 8002806: 4283 cmp r3, r0 8002808: 4637 mov r7, r6 800280a: dc04 bgt.n 8002816 <__swbuf_r+0x42> 800280c: 4621 mov r1, r4 800280e: 4628 mov r0, r5 8002810: f000 f926 bl 8002a60 <_fflush_r> 8002814: bb28 cbnz r0, 8002862 <__swbuf_r+0x8e> 8002816: 68a3 ldr r3, [r4, #8] 8002818: 3b01 subs r3, #1 800281a: 60a3 str r3, [r4, #8] 800281c: 6823 ldr r3, [r4, #0] 800281e: 1c5a adds r2, r3, #1 8002820: 6022 str r2, [r4, #0] 8002822: 701e strb r6, [r3, #0] 8002824: 6963 ldr r3, [r4, #20] 8002826: 3001 adds r0, #1 8002828: 4283 cmp r3, r0 800282a: d004 beq.n 8002836 <__swbuf_r+0x62> 800282c: 89a3 ldrh r3, [r4, #12] 800282e: 07db lsls r3, r3, #31 8002830: d519 bpl.n 8002866 <__swbuf_r+0x92> 8002832: 2e0a cmp r6, #10 8002834: d117 bne.n 8002866 <__swbuf_r+0x92> 8002836: 4621 mov r1, r4 8002838: 4628 mov r0, r5 800283a: f000 f911 bl 8002a60 <_fflush_r> 800283e: b190 cbz r0, 8002866 <__swbuf_r+0x92> 8002840: e00f b.n 8002862 <__swbuf_r+0x8e> 8002842: 4b0b ldr r3, [pc, #44] ; (8002870 <__swbuf_r+0x9c>) 8002844: 429c cmp r4, r3 8002846: d101 bne.n 800284c <__swbuf_r+0x78> 8002848: 68ac ldr r4, [r5, #8] 800284a: e7d0 b.n 80027ee <__swbuf_r+0x1a> 800284c: 4b09 ldr r3, [pc, #36] ; (8002874 <__swbuf_r+0xa0>) 800284e: 429c cmp r4, r3 8002850: bf08 it eq 8002852: 68ec ldreq r4, [r5, #12] 8002854: e7cb b.n 80027ee <__swbuf_r+0x1a> 8002856: 4621 mov r1, r4 8002858: 4628 mov r0, r5 800285a: f000 f80d bl 8002878 <__swsetup_r> 800285e: 2800 cmp r0, #0 8002860: d0cc beq.n 80027fc <__swbuf_r+0x28> 8002862: f04f 37ff mov.w r7, #4294967295 8002866: 4638 mov r0, r7 8002868: bdf8 pop {r3, r4, r5, r6, r7, pc} 800286a: bf00 nop 800286c: 08003050 .word 0x08003050 8002870: 08003070 .word 0x08003070 8002874: 08003030 .word 0x08003030 08002878 <__swsetup_r>: 8002878: 4b32 ldr r3, [pc, #200] ; (8002944 <__swsetup_r+0xcc>) 800287a: b570 push {r4, r5, r6, lr} 800287c: 681d ldr r5, [r3, #0] 800287e: 4606 mov r6, r0 8002880: 460c mov r4, r1 8002882: b125 cbz r5, 800288e <__swsetup_r+0x16> 8002884: 69ab ldr r3, [r5, #24] 8002886: b913 cbnz r3, 800288e <__swsetup_r+0x16> 8002888: 4628 mov r0, r5 800288a: f000 f953 bl 8002b34 <__sinit> 800288e: 4b2e ldr r3, [pc, #184] ; (8002948 <__swsetup_r+0xd0>) 8002890: 429c cmp r4, r3 8002892: d10f bne.n 80028b4 <__swsetup_r+0x3c> 8002894: 686c ldr r4, [r5, #4] 8002896: f9b4 300c ldrsh.w r3, [r4, #12] 800289a: b29a uxth r2, r3 800289c: 0715 lsls r5, r2, #28 800289e: d42c bmi.n 80028fa <__swsetup_r+0x82> 80028a0: 06d0 lsls r0, r2, #27 80028a2: d411 bmi.n 80028c8 <__swsetup_r+0x50> 80028a4: 2209 movs r2, #9 80028a6: 6032 str r2, [r6, #0] 80028a8: f043 0340 orr.w r3, r3, #64 ; 0x40 80028ac: 81a3 strh r3, [r4, #12] 80028ae: f04f 30ff mov.w r0, #4294967295 80028b2: e03e b.n 8002932 <__swsetup_r+0xba> 80028b4: 4b25 ldr r3, [pc, #148] ; (800294c <__swsetup_r+0xd4>) 80028b6: 429c cmp r4, r3 80028b8: d101 bne.n 80028be <__swsetup_r+0x46> 80028ba: 68ac ldr r4, [r5, #8] 80028bc: e7eb b.n 8002896 <__swsetup_r+0x1e> 80028be: 4b24 ldr r3, [pc, #144] ; (8002950 <__swsetup_r+0xd8>) 80028c0: 429c cmp r4, r3 80028c2: bf08 it eq 80028c4: 68ec ldreq r4, [r5, #12] 80028c6: e7e6 b.n 8002896 <__swsetup_r+0x1e> 80028c8: 0751 lsls r1, r2, #29 80028ca: d512 bpl.n 80028f2 <__swsetup_r+0x7a> 80028cc: 6b61 ldr r1, [r4, #52] ; 0x34 80028ce: b141 cbz r1, 80028e2 <__swsetup_r+0x6a> 80028d0: f104 0344 add.w r3, r4, #68 ; 0x44 80028d4: 4299 cmp r1, r3 80028d6: d002 beq.n 80028de <__swsetup_r+0x66> 80028d8: 4630 mov r0, r6 80028da: f000 fa21 bl 8002d20 <_free_r> 80028de: 2300 movs r3, #0 80028e0: 6363 str r3, [r4, #52] ; 0x34 80028e2: 89a3 ldrh r3, [r4, #12] 80028e4: f023 0324 bic.w r3, r3, #36 ; 0x24 80028e8: 81a3 strh r3, [r4, #12] 80028ea: 2300 movs r3, #0 80028ec: 6063 str r3, [r4, #4] 80028ee: 6923 ldr r3, [r4, #16] 80028f0: 6023 str r3, [r4, #0] 80028f2: 89a3 ldrh r3, [r4, #12] 80028f4: f043 0308 orr.w r3, r3, #8 80028f8: 81a3 strh r3, [r4, #12] 80028fa: 6923 ldr r3, [r4, #16] 80028fc: b94b cbnz r3, 8002912 <__swsetup_r+0x9a> 80028fe: 89a3 ldrh r3, [r4, #12] 8002900: f403 7320 and.w r3, r3, #640 ; 0x280 8002904: f5b3 7f00 cmp.w r3, #512 ; 0x200 8002908: d003 beq.n 8002912 <__swsetup_r+0x9a> 800290a: 4621 mov r1, r4 800290c: 4630 mov r0, r6 800290e: f000 f9bf bl 8002c90 <__smakebuf_r> 8002912: 89a2 ldrh r2, [r4, #12] 8002914: f012 0301 ands.w r3, r2, #1 8002918: d00c beq.n 8002934 <__swsetup_r+0xbc> 800291a: 2300 movs r3, #0 800291c: 60a3 str r3, [r4, #8] 800291e: 6963 ldr r3, [r4, #20] 8002920: 425b negs r3, r3 8002922: 61a3 str r3, [r4, #24] 8002924: 6923 ldr r3, [r4, #16] 8002926: b953 cbnz r3, 800293e <__swsetup_r+0xc6> 8002928: f9b4 300c ldrsh.w r3, [r4, #12] 800292c: f013 0080 ands.w r0, r3, #128 ; 0x80 8002930: d1ba bne.n 80028a8 <__swsetup_r+0x30> 8002932: bd70 pop {r4, r5, r6, pc} 8002934: 0792 lsls r2, r2, #30 8002936: bf58 it pl 8002938: 6963 ldrpl r3, [r4, #20] 800293a: 60a3 str r3, [r4, #8] 800293c: e7f2 b.n 8002924 <__swsetup_r+0xac> 800293e: 2000 movs r0, #0 8002940: e7f7 b.n 8002932 <__swsetup_r+0xba> 8002942: bf00 nop 8002944: 20000038 .word 0x20000038 8002948: 08003050 .word 0x08003050 800294c: 08003070 .word 0x08003070 8002950: 08003030 .word 0x08003030 08002954 <__sflush_r>: 8002954: 898a ldrh r2, [r1, #12] 8002956: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 800295a: 4605 mov r5, r0 800295c: 0710 lsls r0, r2, #28 800295e: 460c mov r4, r1 8002960: d458 bmi.n 8002a14 <__sflush_r+0xc0> 8002962: 684b ldr r3, [r1, #4] 8002964: 2b00 cmp r3, #0 8002966: dc05 bgt.n 8002974 <__sflush_r+0x20> 8002968: 6c0b ldr r3, [r1, #64] ; 0x40 800296a: 2b00 cmp r3, #0 800296c: dc02 bgt.n 8002974 <__sflush_r+0x20> 800296e: 2000 movs r0, #0 8002970: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8002974: 6ae6 ldr r6, [r4, #44] ; 0x2c 8002976: 2e00 cmp r6, #0 8002978: d0f9 beq.n 800296e <__sflush_r+0x1a> 800297a: 2300 movs r3, #0 800297c: f412 5280 ands.w r2, r2, #4096 ; 0x1000 8002980: 682f ldr r7, [r5, #0] 8002982: 6a21 ldr r1, [r4, #32] 8002984: 602b str r3, [r5, #0] 8002986: d032 beq.n 80029ee <__sflush_r+0x9a> 8002988: 6d60 ldr r0, [r4, #84] ; 0x54 800298a: 89a3 ldrh r3, [r4, #12] 800298c: 075a lsls r2, r3, #29 800298e: d505 bpl.n 800299c <__sflush_r+0x48> 8002990: 6863 ldr r3, [r4, #4] 8002992: 1ac0 subs r0, r0, r3 8002994: 6b63 ldr r3, [r4, #52] ; 0x34 8002996: b10b cbz r3, 800299c <__sflush_r+0x48> 8002998: 6c23 ldr r3, [r4, #64] ; 0x40 800299a: 1ac0 subs r0, r0, r3 800299c: 2300 movs r3, #0 800299e: 4602 mov r2, r0 80029a0: 6ae6 ldr r6, [r4, #44] ; 0x2c 80029a2: 6a21 ldr r1, [r4, #32] 80029a4: 4628 mov r0, r5 80029a6: 47b0 blx r6 80029a8: 1c43 adds r3, r0, #1 80029aa: 89a3 ldrh r3, [r4, #12] 80029ac: d106 bne.n 80029bc <__sflush_r+0x68> 80029ae: 6829 ldr r1, [r5, #0] 80029b0: 291d cmp r1, #29 80029b2: d848 bhi.n 8002a46 <__sflush_r+0xf2> 80029b4: 4a29 ldr r2, [pc, #164] ; (8002a5c <__sflush_r+0x108>) 80029b6: 40ca lsrs r2, r1 80029b8: 07d6 lsls r6, r2, #31 80029ba: d544 bpl.n 8002a46 <__sflush_r+0xf2> 80029bc: 2200 movs r2, #0 80029be: 6062 str r2, [r4, #4] 80029c0: 04d9 lsls r1, r3, #19 80029c2: 6922 ldr r2, [r4, #16] 80029c4: 6022 str r2, [r4, #0] 80029c6: d504 bpl.n 80029d2 <__sflush_r+0x7e> 80029c8: 1c42 adds r2, r0, #1 80029ca: d101 bne.n 80029d0 <__sflush_r+0x7c> 80029cc: 682b ldr r3, [r5, #0] 80029ce: b903 cbnz r3, 80029d2 <__sflush_r+0x7e> 80029d0: 6560 str r0, [r4, #84] ; 0x54 80029d2: 6b61 ldr r1, [r4, #52] ; 0x34 80029d4: 602f str r7, [r5, #0] 80029d6: 2900 cmp r1, #0 80029d8: d0c9 beq.n 800296e <__sflush_r+0x1a> 80029da: f104 0344 add.w r3, r4, #68 ; 0x44 80029de: 4299 cmp r1, r3 80029e0: d002 beq.n 80029e8 <__sflush_r+0x94> 80029e2: 4628 mov r0, r5 80029e4: f000 f99c bl 8002d20 <_free_r> 80029e8: 2000 movs r0, #0 80029ea: 6360 str r0, [r4, #52] ; 0x34 80029ec: e7c0 b.n 8002970 <__sflush_r+0x1c> 80029ee: 2301 movs r3, #1 80029f0: 4628 mov r0, r5 80029f2: 47b0 blx r6 80029f4: 1c41 adds r1, r0, #1 80029f6: d1c8 bne.n 800298a <__sflush_r+0x36> 80029f8: 682b ldr r3, [r5, #0] 80029fa: 2b00 cmp r3, #0 80029fc: d0c5 beq.n 800298a <__sflush_r+0x36> 80029fe: 2b1d cmp r3, #29 8002a00: d001 beq.n 8002a06 <__sflush_r+0xb2> 8002a02: 2b16 cmp r3, #22 8002a04: d101 bne.n 8002a0a <__sflush_r+0xb6> 8002a06: 602f str r7, [r5, #0] 8002a08: e7b1 b.n 800296e <__sflush_r+0x1a> 8002a0a: 89a3 ldrh r3, [r4, #12] 8002a0c: f043 0340 orr.w r3, r3, #64 ; 0x40 8002a10: 81a3 strh r3, [r4, #12] 8002a12: e7ad b.n 8002970 <__sflush_r+0x1c> 8002a14: 690f ldr r7, [r1, #16] 8002a16: 2f00 cmp r7, #0 8002a18: d0a9 beq.n 800296e <__sflush_r+0x1a> 8002a1a: 0793 lsls r3, r2, #30 8002a1c: 680e ldr r6, [r1, #0] 8002a1e: bf08 it eq 8002a20: 694b ldreq r3, [r1, #20] 8002a22: 600f str r7, [r1, #0] 8002a24: bf18 it ne 8002a26: 2300 movne r3, #0 8002a28: eba6 0807 sub.w r8, r6, r7 8002a2c: 608b str r3, [r1, #8] 8002a2e: f1b8 0f00 cmp.w r8, #0 8002a32: dd9c ble.n 800296e <__sflush_r+0x1a> 8002a34: 4643 mov r3, r8 8002a36: 463a mov r2, r7 8002a38: 6a21 ldr r1, [r4, #32] 8002a3a: 6aa6 ldr r6, [r4, #40] ; 0x28 8002a3c: 4628 mov r0, r5 8002a3e: 47b0 blx r6 8002a40: 2800 cmp r0, #0 8002a42: dc06 bgt.n 8002a52 <__sflush_r+0xfe> 8002a44: 89a3 ldrh r3, [r4, #12] 8002a46: f043 0340 orr.w r3, r3, #64 ; 0x40 8002a4a: 81a3 strh r3, [r4, #12] 8002a4c: f04f 30ff mov.w r0, #4294967295 8002a50: e78e b.n 8002970 <__sflush_r+0x1c> 8002a52: 4407 add r7, r0 8002a54: eba8 0800 sub.w r8, r8, r0 8002a58: e7e9 b.n 8002a2e <__sflush_r+0xda> 8002a5a: bf00 nop 8002a5c: 20400001 .word 0x20400001 08002a60 <_fflush_r>: 8002a60: b538 push {r3, r4, r5, lr} 8002a62: 690b ldr r3, [r1, #16] 8002a64: 4605 mov r5, r0 8002a66: 460c mov r4, r1 8002a68: b1db cbz r3, 8002aa2 <_fflush_r+0x42> 8002a6a: b118 cbz r0, 8002a74 <_fflush_r+0x14> 8002a6c: 6983 ldr r3, [r0, #24] 8002a6e: b90b cbnz r3, 8002a74 <_fflush_r+0x14> 8002a70: f000 f860 bl 8002b34 <__sinit> 8002a74: 4b0c ldr r3, [pc, #48] ; (8002aa8 <_fflush_r+0x48>) 8002a76: 429c cmp r4, r3 8002a78: d109 bne.n 8002a8e <_fflush_r+0x2e> 8002a7a: 686c ldr r4, [r5, #4] 8002a7c: f9b4 300c ldrsh.w r3, [r4, #12] 8002a80: b17b cbz r3, 8002aa2 <_fflush_r+0x42> 8002a82: 4621 mov r1, r4 8002a84: 4628 mov r0, r5 8002a86: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 8002a8a: f7ff bf63 b.w 8002954 <__sflush_r> 8002a8e: 4b07 ldr r3, [pc, #28] ; (8002aac <_fflush_r+0x4c>) 8002a90: 429c cmp r4, r3 8002a92: d101 bne.n 8002a98 <_fflush_r+0x38> 8002a94: 68ac ldr r4, [r5, #8] 8002a96: e7f1 b.n 8002a7c <_fflush_r+0x1c> 8002a98: 4b05 ldr r3, [pc, #20] ; (8002ab0 <_fflush_r+0x50>) 8002a9a: 429c cmp r4, r3 8002a9c: bf08 it eq 8002a9e: 68ec ldreq r4, [r5, #12] 8002aa0: e7ec b.n 8002a7c <_fflush_r+0x1c> 8002aa2: 2000 movs r0, #0 8002aa4: bd38 pop {r3, r4, r5, pc} 8002aa6: bf00 nop 8002aa8: 08003050 .word 0x08003050 8002aac: 08003070 .word 0x08003070 8002ab0: 08003030 .word 0x08003030 08002ab4 : 8002ab4: 2300 movs r3, #0 8002ab6: b510 push {r4, lr} 8002ab8: 4604 mov r4, r0 8002aba: e9c0 3300 strd r3, r3, [r0] 8002abe: 6083 str r3, [r0, #8] 8002ac0: 8181 strh r1, [r0, #12] 8002ac2: 6643 str r3, [r0, #100] ; 0x64 8002ac4: 81c2 strh r2, [r0, #14] 8002ac6: e9c0 3304 strd r3, r3, [r0, #16] 8002aca: 6183 str r3, [r0, #24] 8002acc: 4619 mov r1, r3 8002ace: 2208 movs r2, #8 8002ad0: 305c adds r0, #92 ; 0x5c 8002ad2: f7ff fd5d bl 8002590 8002ad6: 4b05 ldr r3, [pc, #20] ; (8002aec ) 8002ad8: 6263 str r3, [r4, #36] ; 0x24 8002ada: 4b05 ldr r3, [pc, #20] ; (8002af0 ) 8002adc: 62a3 str r3, [r4, #40] ; 0x28 8002ade: 4b05 ldr r3, [pc, #20] ; (8002af4 ) 8002ae0: 62e3 str r3, [r4, #44] ; 0x2c 8002ae2: 4b05 ldr r3, [pc, #20] ; (8002af8 ) 8002ae4: 6224 str r4, [r4, #32] 8002ae6: 6323 str r3, [r4, #48] ; 0x30 8002ae8: bd10 pop {r4, pc} 8002aea: bf00 nop 8002aec: 08002e91 .word 0x08002e91 8002af0: 08002eb3 .word 0x08002eb3 8002af4: 08002eeb .word 0x08002eeb 8002af8: 08002f0f .word 0x08002f0f 08002afc <_cleanup_r>: 8002afc: 4901 ldr r1, [pc, #4] ; (8002b04 <_cleanup_r+0x8>) 8002afe: f000 b885 b.w 8002c0c <_fwalk_reent> 8002b02: bf00 nop 8002b04: 08002a61 .word 0x08002a61 08002b08 <__sfmoreglue>: 8002b08: b570 push {r4, r5, r6, lr} 8002b0a: 1e4a subs r2, r1, #1 8002b0c: 2568 movs r5, #104 ; 0x68 8002b0e: 4355 muls r5, r2 8002b10: 460e mov r6, r1 8002b12: f105 0174 add.w r1, r5, #116 ; 0x74 8002b16: f000 f951 bl 8002dbc <_malloc_r> 8002b1a: 4604 mov r4, r0 8002b1c: b140 cbz r0, 8002b30 <__sfmoreglue+0x28> 8002b1e: 2100 movs r1, #0 8002b20: e9c0 1600 strd r1, r6, [r0] 8002b24: 300c adds r0, #12 8002b26: 60a0 str r0, [r4, #8] 8002b28: f105 0268 add.w r2, r5, #104 ; 0x68 8002b2c: f7ff fd30 bl 8002590 8002b30: 4620 mov r0, r4 8002b32: bd70 pop {r4, r5, r6, pc} 08002b34 <__sinit>: 8002b34: 6983 ldr r3, [r0, #24] 8002b36: b510 push {r4, lr} 8002b38: 4604 mov r4, r0 8002b3a: bb33 cbnz r3, 8002b8a <__sinit+0x56> 8002b3c: e9c0 3312 strd r3, r3, [r0, #72] ; 0x48 8002b40: 6503 str r3, [r0, #80] ; 0x50 8002b42: 4b12 ldr r3, [pc, #72] ; (8002b8c <__sinit+0x58>) 8002b44: 4a12 ldr r2, [pc, #72] ; (8002b90 <__sinit+0x5c>) 8002b46: 681b ldr r3, [r3, #0] 8002b48: 6282 str r2, [r0, #40] ; 0x28 8002b4a: 4298 cmp r0, r3 8002b4c: bf04 itt eq 8002b4e: 2301 moveq r3, #1 8002b50: 6183 streq r3, [r0, #24] 8002b52: f000 f81f bl 8002b94 <__sfp> 8002b56: 6060 str r0, [r4, #4] 8002b58: 4620 mov r0, r4 8002b5a: f000 f81b bl 8002b94 <__sfp> 8002b5e: 60a0 str r0, [r4, #8] 8002b60: 4620 mov r0, r4 8002b62: f000 f817 bl 8002b94 <__sfp> 8002b66: 2200 movs r2, #0 8002b68: 60e0 str r0, [r4, #12] 8002b6a: 2104 movs r1, #4 8002b6c: 6860 ldr r0, [r4, #4] 8002b6e: f7ff ffa1 bl 8002ab4 8002b72: 2201 movs r2, #1 8002b74: 2109 movs r1, #9 8002b76: 68a0 ldr r0, [r4, #8] 8002b78: f7ff ff9c bl 8002ab4 8002b7c: 2202 movs r2, #2 8002b7e: 2112 movs r1, #18 8002b80: 68e0 ldr r0, [r4, #12] 8002b82: f7ff ff97 bl 8002ab4 8002b86: 2301 movs r3, #1 8002b88: 61a3 str r3, [r4, #24] 8002b8a: bd10 pop {r4, pc} 8002b8c: 0800302c .word 0x0800302c 8002b90: 08002afd .word 0x08002afd 08002b94 <__sfp>: 8002b94: b5f8 push {r3, r4, r5, r6, r7, lr} 8002b96: 4b1b ldr r3, [pc, #108] ; (8002c04 <__sfp+0x70>) 8002b98: 681e ldr r6, [r3, #0] 8002b9a: 69b3 ldr r3, [r6, #24] 8002b9c: 4607 mov r7, r0 8002b9e: b913 cbnz r3, 8002ba6 <__sfp+0x12> 8002ba0: 4630 mov r0, r6 8002ba2: f7ff ffc7 bl 8002b34 <__sinit> 8002ba6: 3648 adds r6, #72 ; 0x48 8002ba8: e9d6 3401 ldrd r3, r4, [r6, #4] 8002bac: 3b01 subs r3, #1 8002bae: d503 bpl.n 8002bb8 <__sfp+0x24> 8002bb0: 6833 ldr r3, [r6, #0] 8002bb2: b133 cbz r3, 8002bc2 <__sfp+0x2e> 8002bb4: 6836 ldr r6, [r6, #0] 8002bb6: e7f7 b.n 8002ba8 <__sfp+0x14> 8002bb8: f9b4 500c ldrsh.w r5, [r4, #12] 8002bbc: b16d cbz r5, 8002bda <__sfp+0x46> 8002bbe: 3468 adds r4, #104 ; 0x68 8002bc0: e7f4 b.n 8002bac <__sfp+0x18> 8002bc2: 2104 movs r1, #4 8002bc4: 4638 mov r0, r7 8002bc6: f7ff ff9f bl 8002b08 <__sfmoreglue> 8002bca: 6030 str r0, [r6, #0] 8002bcc: 2800 cmp r0, #0 8002bce: d1f1 bne.n 8002bb4 <__sfp+0x20> 8002bd0: 230c movs r3, #12 8002bd2: 603b str r3, [r7, #0] 8002bd4: 4604 mov r4, r0 8002bd6: 4620 mov r0, r4 8002bd8: bdf8 pop {r3, r4, r5, r6, r7, pc} 8002bda: 4b0b ldr r3, [pc, #44] ; (8002c08 <__sfp+0x74>) 8002bdc: 6665 str r5, [r4, #100] ; 0x64 8002bde: e9c4 5500 strd r5, r5, [r4] 8002be2: 60a5 str r5, [r4, #8] 8002be4: e9c4 3503 strd r3, r5, [r4, #12] 8002be8: e9c4 5505 strd r5, r5, [r4, #20] 8002bec: 2208 movs r2, #8 8002bee: 4629 mov r1, r5 8002bf0: f104 005c add.w r0, r4, #92 ; 0x5c 8002bf4: f7ff fccc bl 8002590 8002bf8: e9c4 550d strd r5, r5, [r4, #52] ; 0x34 8002bfc: e9c4 5512 strd r5, r5, [r4, #72] ; 0x48 8002c00: e7e9 b.n 8002bd6 <__sfp+0x42> 8002c02: bf00 nop 8002c04: 0800302c .word 0x0800302c 8002c08: ffff0001 .word 0xffff0001 08002c0c <_fwalk_reent>: 8002c0c: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 8002c10: 4680 mov r8, r0 8002c12: 4689 mov r9, r1 8002c14: f100 0448 add.w r4, r0, #72 ; 0x48 8002c18: 2600 movs r6, #0 8002c1a: b914 cbnz r4, 8002c22 <_fwalk_reent+0x16> 8002c1c: 4630 mov r0, r6 8002c1e: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 8002c22: e9d4 7501 ldrd r7, r5, [r4, #4] 8002c26: 3f01 subs r7, #1 8002c28: d501 bpl.n 8002c2e <_fwalk_reent+0x22> 8002c2a: 6824 ldr r4, [r4, #0] 8002c2c: e7f5 b.n 8002c1a <_fwalk_reent+0xe> 8002c2e: 89ab ldrh r3, [r5, #12] 8002c30: 2b01 cmp r3, #1 8002c32: d907 bls.n 8002c44 <_fwalk_reent+0x38> 8002c34: f9b5 300e ldrsh.w r3, [r5, #14] 8002c38: 3301 adds r3, #1 8002c3a: d003 beq.n 8002c44 <_fwalk_reent+0x38> 8002c3c: 4629 mov r1, r5 8002c3e: 4640 mov r0, r8 8002c40: 47c8 blx r9 8002c42: 4306 orrs r6, r0 8002c44: 3568 adds r5, #104 ; 0x68 8002c46: e7ee b.n 8002c26 <_fwalk_reent+0x1a> 08002c48 <__swhatbuf_r>: 8002c48: b570 push {r4, r5, r6, lr} 8002c4a: 460e mov r6, r1 8002c4c: f9b1 100e ldrsh.w r1, [r1, #14] 8002c50: 2900 cmp r1, #0 8002c52: b096 sub sp, #88 ; 0x58 8002c54: 4614 mov r4, r2 8002c56: 461d mov r5, r3 8002c58: da07 bge.n 8002c6a <__swhatbuf_r+0x22> 8002c5a: 2300 movs r3, #0 8002c5c: 602b str r3, [r5, #0] 8002c5e: 89b3 ldrh r3, [r6, #12] 8002c60: 061a lsls r2, r3, #24 8002c62: d410 bmi.n 8002c86 <__swhatbuf_r+0x3e> 8002c64: f44f 6380 mov.w r3, #1024 ; 0x400 8002c68: e00e b.n 8002c88 <__swhatbuf_r+0x40> 8002c6a: 466a mov r2, sp 8002c6c: f000 f976 bl 8002f5c <_fstat_r> 8002c70: 2800 cmp r0, #0 8002c72: dbf2 blt.n 8002c5a <__swhatbuf_r+0x12> 8002c74: 9a01 ldr r2, [sp, #4] 8002c76: f402 4270 and.w r2, r2, #61440 ; 0xf000 8002c7a: f5a2 5300 sub.w r3, r2, #8192 ; 0x2000 8002c7e: 425a negs r2, r3 8002c80: 415a adcs r2, r3 8002c82: 602a str r2, [r5, #0] 8002c84: e7ee b.n 8002c64 <__swhatbuf_r+0x1c> 8002c86: 2340 movs r3, #64 ; 0x40 8002c88: 2000 movs r0, #0 8002c8a: 6023 str r3, [r4, #0] 8002c8c: b016 add sp, #88 ; 0x58 8002c8e: bd70 pop {r4, r5, r6, pc} 08002c90 <__smakebuf_r>: 8002c90: 898b ldrh r3, [r1, #12] 8002c92: b573 push {r0, r1, r4, r5, r6, lr} 8002c94: 079d lsls r5, r3, #30 8002c96: 4606 mov r6, r0 8002c98: 460c mov r4, r1 8002c9a: d507 bpl.n 8002cac <__smakebuf_r+0x1c> 8002c9c: f104 0347 add.w r3, r4, #71 ; 0x47 8002ca0: 6023 str r3, [r4, #0] 8002ca2: 6123 str r3, [r4, #16] 8002ca4: 2301 movs r3, #1 8002ca6: 6163 str r3, [r4, #20] 8002ca8: b002 add sp, #8 8002caa: bd70 pop {r4, r5, r6, pc} 8002cac: ab01 add r3, sp, #4 8002cae: 466a mov r2, sp 8002cb0: f7ff ffca bl 8002c48 <__swhatbuf_r> 8002cb4: 9900 ldr r1, [sp, #0] 8002cb6: 4605 mov r5, r0 8002cb8: 4630 mov r0, r6 8002cba: f000 f87f bl 8002dbc <_malloc_r> 8002cbe: b948 cbnz r0, 8002cd4 <__smakebuf_r+0x44> 8002cc0: f9b4 300c ldrsh.w r3, [r4, #12] 8002cc4: 059a lsls r2, r3, #22 8002cc6: d4ef bmi.n 8002ca8 <__smakebuf_r+0x18> 8002cc8: f023 0303 bic.w r3, r3, #3 8002ccc: f043 0302 orr.w r3, r3, #2 8002cd0: 81a3 strh r3, [r4, #12] 8002cd2: e7e3 b.n 8002c9c <__smakebuf_r+0xc> 8002cd4: 4b0d ldr r3, [pc, #52] ; (8002d0c <__smakebuf_r+0x7c>) 8002cd6: 62b3 str r3, [r6, #40] ; 0x28 8002cd8: 89a3 ldrh r3, [r4, #12] 8002cda: 6020 str r0, [r4, #0] 8002cdc: f043 0380 orr.w r3, r3, #128 ; 0x80 8002ce0: 81a3 strh r3, [r4, #12] 8002ce2: 9b00 ldr r3, [sp, #0] 8002ce4: 6163 str r3, [r4, #20] 8002ce6: 9b01 ldr r3, [sp, #4] 8002ce8: 6120 str r0, [r4, #16] 8002cea: b15b cbz r3, 8002d04 <__smakebuf_r+0x74> 8002cec: f9b4 100e ldrsh.w r1, [r4, #14] 8002cf0: 4630 mov r0, r6 8002cf2: f000 f945 bl 8002f80 <_isatty_r> 8002cf6: b128 cbz r0, 8002d04 <__smakebuf_r+0x74> 8002cf8: 89a3 ldrh r3, [r4, #12] 8002cfa: f023 0303 bic.w r3, r3, #3 8002cfe: f043 0301 orr.w r3, r3, #1 8002d02: 81a3 strh r3, [r4, #12] 8002d04: 89a3 ldrh r3, [r4, #12] 8002d06: 431d orrs r5, r3 8002d08: 81a5 strh r5, [r4, #12] 8002d0a: e7cd b.n 8002ca8 <__smakebuf_r+0x18> 8002d0c: 08002afd .word 0x08002afd 08002d10 : 8002d10: 4b02 ldr r3, [pc, #8] ; (8002d1c ) 8002d12: 4601 mov r1, r0 8002d14: 6818 ldr r0, [r3, #0] 8002d16: f000 b851 b.w 8002dbc <_malloc_r> 8002d1a: bf00 nop 8002d1c: 20000038 .word 0x20000038 08002d20 <_free_r>: 8002d20: b538 push {r3, r4, r5, lr} 8002d22: 4605 mov r5, r0 8002d24: 2900 cmp r1, #0 8002d26: d045 beq.n 8002db4 <_free_r+0x94> 8002d28: f851 3c04 ldr.w r3, [r1, #-4] 8002d2c: 1f0c subs r4, r1, #4 8002d2e: 2b00 cmp r3, #0 8002d30: bfb8 it lt 8002d32: 18e4 addlt r4, r4, r3 8002d34: f000 f946 bl 8002fc4 <__malloc_lock> 8002d38: 4a1f ldr r2, [pc, #124] ; (8002db8 <_free_r+0x98>) 8002d3a: 6813 ldr r3, [r2, #0] 8002d3c: 4610 mov r0, r2 8002d3e: b933 cbnz r3, 8002d4e <_free_r+0x2e> 8002d40: 6063 str r3, [r4, #4] 8002d42: 6014 str r4, [r2, #0] 8002d44: 4628 mov r0, r5 8002d46: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 8002d4a: f000 b93c b.w 8002fc6 <__malloc_unlock> 8002d4e: 42a3 cmp r3, r4 8002d50: d90c bls.n 8002d6c <_free_r+0x4c> 8002d52: 6821 ldr r1, [r4, #0] 8002d54: 1862 adds r2, r4, r1 8002d56: 4293 cmp r3, r2 8002d58: bf04 itt eq 8002d5a: 681a ldreq r2, [r3, #0] 8002d5c: 685b ldreq r3, [r3, #4] 8002d5e: 6063 str r3, [r4, #4] 8002d60: bf04 itt eq 8002d62: 1852 addeq r2, r2, r1 8002d64: 6022 streq r2, [r4, #0] 8002d66: 6004 str r4, [r0, #0] 8002d68: e7ec b.n 8002d44 <_free_r+0x24> 8002d6a: 4613 mov r3, r2 8002d6c: 685a ldr r2, [r3, #4] 8002d6e: b10a cbz r2, 8002d74 <_free_r+0x54> 8002d70: 42a2 cmp r2, r4 8002d72: d9fa bls.n 8002d6a <_free_r+0x4a> 8002d74: 6819 ldr r1, [r3, #0] 8002d76: 1858 adds r0, r3, r1 8002d78: 42a0 cmp r0, r4 8002d7a: d10b bne.n 8002d94 <_free_r+0x74> 8002d7c: 6820 ldr r0, [r4, #0] 8002d7e: 4401 add r1, r0 8002d80: 1858 adds r0, r3, r1 8002d82: 4282 cmp r2, r0 8002d84: 6019 str r1, [r3, #0] 8002d86: d1dd bne.n 8002d44 <_free_r+0x24> 8002d88: 6810 ldr r0, [r2, #0] 8002d8a: 6852 ldr r2, [r2, #4] 8002d8c: 605a str r2, [r3, #4] 8002d8e: 4401 add r1, r0 8002d90: 6019 str r1, [r3, #0] 8002d92: e7d7 b.n 8002d44 <_free_r+0x24> 8002d94: d902 bls.n 8002d9c <_free_r+0x7c> 8002d96: 230c movs r3, #12 8002d98: 602b str r3, [r5, #0] 8002d9a: e7d3 b.n 8002d44 <_free_r+0x24> 8002d9c: 6820 ldr r0, [r4, #0] 8002d9e: 1821 adds r1, r4, r0 8002da0: 428a cmp r2, r1 8002da2: bf04 itt eq 8002da4: 6811 ldreq r1, [r2, #0] 8002da6: 6852 ldreq r2, [r2, #4] 8002da8: 6062 str r2, [r4, #4] 8002daa: bf04 itt eq 8002dac: 1809 addeq r1, r1, r0 8002dae: 6021 streq r1, [r4, #0] 8002db0: 605c str r4, [r3, #4] 8002db2: e7c7 b.n 8002d44 <_free_r+0x24> 8002db4: bd38 pop {r3, r4, r5, pc} 8002db6: bf00 nop 8002db8: 200000d8 .word 0x200000d8 08002dbc <_malloc_r>: 8002dbc: b570 push {r4, r5, r6, lr} 8002dbe: 1ccd adds r5, r1, #3 8002dc0: f025 0503 bic.w r5, r5, #3 8002dc4: 3508 adds r5, #8 8002dc6: 2d0c cmp r5, #12 8002dc8: bf38 it cc 8002dca: 250c movcc r5, #12 8002dcc: 2d00 cmp r5, #0 8002dce: 4606 mov r6, r0 8002dd0: db01 blt.n 8002dd6 <_malloc_r+0x1a> 8002dd2: 42a9 cmp r1, r5 8002dd4: d903 bls.n 8002dde <_malloc_r+0x22> 8002dd6: 230c movs r3, #12 8002dd8: 6033 str r3, [r6, #0] 8002dda: 2000 movs r0, #0 8002ddc: bd70 pop {r4, r5, r6, pc} 8002dde: f000 f8f1 bl 8002fc4 <__malloc_lock> 8002de2: 4a21 ldr r2, [pc, #132] ; (8002e68 <_malloc_r+0xac>) 8002de4: 6814 ldr r4, [r2, #0] 8002de6: 4621 mov r1, r4 8002de8: b991 cbnz r1, 8002e10 <_malloc_r+0x54> 8002dea: 4c20 ldr r4, [pc, #128] ; (8002e6c <_malloc_r+0xb0>) 8002dec: 6823 ldr r3, [r4, #0] 8002dee: b91b cbnz r3, 8002df8 <_malloc_r+0x3c> 8002df0: 4630 mov r0, r6 8002df2: f000 f83d bl 8002e70 <_sbrk_r> 8002df6: 6020 str r0, [r4, #0] 8002df8: 4629 mov r1, r5 8002dfa: 4630 mov r0, r6 8002dfc: f000 f838 bl 8002e70 <_sbrk_r> 8002e00: 1c43 adds r3, r0, #1 8002e02: d124 bne.n 8002e4e <_malloc_r+0x92> 8002e04: 230c movs r3, #12 8002e06: 6033 str r3, [r6, #0] 8002e08: 4630 mov r0, r6 8002e0a: f000 f8dc bl 8002fc6 <__malloc_unlock> 8002e0e: e7e4 b.n 8002dda <_malloc_r+0x1e> 8002e10: 680b ldr r3, [r1, #0] 8002e12: 1b5b subs r3, r3, r5 8002e14: d418 bmi.n 8002e48 <_malloc_r+0x8c> 8002e16: 2b0b cmp r3, #11 8002e18: d90f bls.n 8002e3a <_malloc_r+0x7e> 8002e1a: 600b str r3, [r1, #0] 8002e1c: 50cd str r5, [r1, r3] 8002e1e: 18cc adds r4, r1, r3 8002e20: 4630 mov r0, r6 8002e22: f000 f8d0 bl 8002fc6 <__malloc_unlock> 8002e26: f104 000b add.w r0, r4, #11 8002e2a: 1d23 adds r3, r4, #4 8002e2c: f020 0007 bic.w r0, r0, #7 8002e30: 1ac3 subs r3, r0, r3 8002e32: d0d3 beq.n 8002ddc <_malloc_r+0x20> 8002e34: 425a negs r2, r3 8002e36: 50e2 str r2, [r4, r3] 8002e38: e7d0 b.n 8002ddc <_malloc_r+0x20> 8002e3a: 428c cmp r4, r1 8002e3c: 684b ldr r3, [r1, #4] 8002e3e: bf16 itet ne 8002e40: 6063 strne r3, [r4, #4] 8002e42: 6013 streq r3, [r2, #0] 8002e44: 460c movne r4, r1 8002e46: e7eb b.n 8002e20 <_malloc_r+0x64> 8002e48: 460c mov r4, r1 8002e4a: 6849 ldr r1, [r1, #4] 8002e4c: e7cc b.n 8002de8 <_malloc_r+0x2c> 8002e4e: 1cc4 adds r4, r0, #3 8002e50: f024 0403 bic.w r4, r4, #3 8002e54: 42a0 cmp r0, r4 8002e56: d005 beq.n 8002e64 <_malloc_r+0xa8> 8002e58: 1a21 subs r1, r4, r0 8002e5a: 4630 mov r0, r6 8002e5c: f000 f808 bl 8002e70 <_sbrk_r> 8002e60: 3001 adds r0, #1 8002e62: d0cf beq.n 8002e04 <_malloc_r+0x48> 8002e64: 6025 str r5, [r4, #0] 8002e66: e7db b.n 8002e20 <_malloc_r+0x64> 8002e68: 200000d8 .word 0x200000d8 8002e6c: 200000dc .word 0x200000dc 08002e70 <_sbrk_r>: 8002e70: b538 push {r3, r4, r5, lr} 8002e72: 4c06 ldr r4, [pc, #24] ; (8002e8c <_sbrk_r+0x1c>) 8002e74: 2300 movs r3, #0 8002e76: 4605 mov r5, r0 8002e78: 4608 mov r0, r1 8002e7a: 6023 str r3, [r4, #0] 8002e7c: f7ff fad2 bl 8002424 <_sbrk> 8002e80: 1c43 adds r3, r0, #1 8002e82: d102 bne.n 8002e8a <_sbrk_r+0x1a> 8002e84: 6823 ldr r3, [r4, #0] 8002e86: b103 cbz r3, 8002e8a <_sbrk_r+0x1a> 8002e88: 602b str r3, [r5, #0] 8002e8a: bd38 pop {r3, r4, r5, pc} 8002e8c: 20000124 .word 0x20000124 08002e90 <__sread>: 8002e90: b510 push {r4, lr} 8002e92: 460c mov r4, r1 8002e94: f9b1 100e ldrsh.w r1, [r1, #14] 8002e98: f000 f896 bl 8002fc8 <_read_r> 8002e9c: 2800 cmp r0, #0 8002e9e: bfab itete ge 8002ea0: 6d63 ldrge r3, [r4, #84] ; 0x54 8002ea2: 89a3 ldrhlt r3, [r4, #12] 8002ea4: 181b addge r3, r3, r0 8002ea6: f423 5380 biclt.w r3, r3, #4096 ; 0x1000 8002eaa: bfac ite ge 8002eac: 6563 strge r3, [r4, #84] ; 0x54 8002eae: 81a3 strhlt r3, [r4, #12] 8002eb0: bd10 pop {r4, pc} 08002eb2 <__swrite>: 8002eb2: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 8002eb6: 461f mov r7, r3 8002eb8: 898b ldrh r3, [r1, #12] 8002eba: 05db lsls r3, r3, #23 8002ebc: 4605 mov r5, r0 8002ebe: 460c mov r4, r1 8002ec0: 4616 mov r6, r2 8002ec2: d505 bpl.n 8002ed0 <__swrite+0x1e> 8002ec4: 2302 movs r3, #2 8002ec6: 2200 movs r2, #0 8002ec8: f9b1 100e ldrsh.w r1, [r1, #14] 8002ecc: f000 f868 bl 8002fa0 <_lseek_r> 8002ed0: 89a3 ldrh r3, [r4, #12] 8002ed2: f9b4 100e ldrsh.w r1, [r4, #14] 8002ed6: f423 5380 bic.w r3, r3, #4096 ; 0x1000 8002eda: 81a3 strh r3, [r4, #12] 8002edc: 4632 mov r2, r6 8002ede: 463b mov r3, r7 8002ee0: 4628 mov r0, r5 8002ee2: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 8002ee6: f000 b817 b.w 8002f18 <_write_r> 08002eea <__sseek>: 8002eea: b510 push {r4, lr} 8002eec: 460c mov r4, r1 8002eee: f9b1 100e ldrsh.w r1, [r1, #14] 8002ef2: f000 f855 bl 8002fa0 <_lseek_r> 8002ef6: 1c43 adds r3, r0, #1 8002ef8: 89a3 ldrh r3, [r4, #12] 8002efa: bf15 itete ne 8002efc: 6560 strne r0, [r4, #84] ; 0x54 8002efe: f423 5380 biceq.w r3, r3, #4096 ; 0x1000 8002f02: f443 5380 orrne.w r3, r3, #4096 ; 0x1000 8002f06: 81a3 strheq r3, [r4, #12] 8002f08: bf18 it ne 8002f0a: 81a3 strhne r3, [r4, #12] 8002f0c: bd10 pop {r4, pc} 08002f0e <__sclose>: 8002f0e: f9b1 100e ldrsh.w r1, [r1, #14] 8002f12: f000 b813 b.w 8002f3c <_close_r> ... 08002f18 <_write_r>: 8002f18: b538 push {r3, r4, r5, lr} 8002f1a: 4c07 ldr r4, [pc, #28] ; (8002f38 <_write_r+0x20>) 8002f1c: 4605 mov r5, r0 8002f1e: 4608 mov r0, r1 8002f20: 4611 mov r1, r2 8002f22: 2200 movs r2, #0 8002f24: 6022 str r2, [r4, #0] 8002f26: 461a mov r2, r3 8002f28: f7fe ffca bl 8001ec0 <_write> 8002f2c: 1c43 adds r3, r0, #1 8002f2e: d102 bne.n 8002f36 <_write_r+0x1e> 8002f30: 6823 ldr r3, [r4, #0] 8002f32: b103 cbz r3, 8002f36 <_write_r+0x1e> 8002f34: 602b str r3, [r5, #0] 8002f36: bd38 pop {r3, r4, r5, pc} 8002f38: 20000124 .word 0x20000124 08002f3c <_close_r>: 8002f3c: b538 push {r3, r4, r5, lr} 8002f3e: 4c06 ldr r4, [pc, #24] ; (8002f58 <_close_r+0x1c>) 8002f40: 2300 movs r3, #0 8002f42: 4605 mov r5, r0 8002f44: 4608 mov r0, r1 8002f46: 6023 str r3, [r4, #0] 8002f48: f7ff fa37 bl 80023ba <_close> 8002f4c: 1c43 adds r3, r0, #1 8002f4e: d102 bne.n 8002f56 <_close_r+0x1a> 8002f50: 6823 ldr r3, [r4, #0] 8002f52: b103 cbz r3, 8002f56 <_close_r+0x1a> 8002f54: 602b str r3, [r5, #0] 8002f56: bd38 pop {r3, r4, r5, pc} 8002f58: 20000124 .word 0x20000124 08002f5c <_fstat_r>: 8002f5c: b538 push {r3, r4, r5, lr} 8002f5e: 4c07 ldr r4, [pc, #28] ; (8002f7c <_fstat_r+0x20>) 8002f60: 2300 movs r3, #0 8002f62: 4605 mov r5, r0 8002f64: 4608 mov r0, r1 8002f66: 4611 mov r1, r2 8002f68: 6023 str r3, [r4, #0] 8002f6a: f7ff fa32 bl 80023d2 <_fstat> 8002f6e: 1c43 adds r3, r0, #1 8002f70: d102 bne.n 8002f78 <_fstat_r+0x1c> 8002f72: 6823 ldr r3, [r4, #0] 8002f74: b103 cbz r3, 8002f78 <_fstat_r+0x1c> 8002f76: 602b str r3, [r5, #0] 8002f78: bd38 pop {r3, r4, r5, pc} 8002f7a: bf00 nop 8002f7c: 20000124 .word 0x20000124 08002f80 <_isatty_r>: 8002f80: b538 push {r3, r4, r5, lr} 8002f82: 4c06 ldr r4, [pc, #24] ; (8002f9c <_isatty_r+0x1c>) 8002f84: 2300 movs r3, #0 8002f86: 4605 mov r5, r0 8002f88: 4608 mov r0, r1 8002f8a: 6023 str r3, [r4, #0] 8002f8c: f7ff fa31 bl 80023f2 <_isatty> 8002f90: 1c43 adds r3, r0, #1 8002f92: d102 bne.n 8002f9a <_isatty_r+0x1a> 8002f94: 6823 ldr r3, [r4, #0] 8002f96: b103 cbz r3, 8002f9a <_isatty_r+0x1a> 8002f98: 602b str r3, [r5, #0] 8002f9a: bd38 pop {r3, r4, r5, pc} 8002f9c: 20000124 .word 0x20000124 08002fa0 <_lseek_r>: 8002fa0: b538 push {r3, r4, r5, lr} 8002fa2: 4c07 ldr r4, [pc, #28] ; (8002fc0 <_lseek_r+0x20>) 8002fa4: 4605 mov r5, r0 8002fa6: 4608 mov r0, r1 8002fa8: 4611 mov r1, r2 8002faa: 2200 movs r2, #0 8002fac: 6022 str r2, [r4, #0] 8002fae: 461a mov r2, r3 8002fb0: f7ff fa2a bl 8002408 <_lseek> 8002fb4: 1c43 adds r3, r0, #1 8002fb6: d102 bne.n 8002fbe <_lseek_r+0x1e> 8002fb8: 6823 ldr r3, [r4, #0] 8002fba: b103 cbz r3, 8002fbe <_lseek_r+0x1e> 8002fbc: 602b str r3, [r5, #0] 8002fbe: bd38 pop {r3, r4, r5, pc} 8002fc0: 20000124 .word 0x20000124 08002fc4 <__malloc_lock>: 8002fc4: 4770 bx lr 08002fc6 <__malloc_unlock>: 8002fc6: 4770 bx lr 08002fc8 <_read_r>: 8002fc8: b538 push {r3, r4, r5, lr} 8002fca: 4c07 ldr r4, [pc, #28] ; (8002fe8 <_read_r+0x20>) 8002fcc: 4605 mov r5, r0 8002fce: 4608 mov r0, r1 8002fd0: 4611 mov r1, r2 8002fd2: 2200 movs r2, #0 8002fd4: 6022 str r2, [r4, #0] 8002fd6: 461a mov r2, r3 8002fd8: f7ff f9d2 bl 8002380 <_read> 8002fdc: 1c43 adds r3, r0, #1 8002fde: d102 bne.n 8002fe6 <_read_r+0x1e> 8002fe0: 6823 ldr r3, [r4, #0] 8002fe2: b103 cbz r3, 8002fe6 <_read_r+0x1e> 8002fe4: 602b str r3, [r5, #0] 8002fe6: bd38 pop {r3, r4, r5, pc} 8002fe8: 20000124 .word 0x20000124 08002fec <_init>: 8002fec: b5f8 push {r3, r4, r5, r6, r7, lr} 8002fee: bf00 nop 8002ff0: bcf8 pop {r3, r4, r5, r6, r7} 8002ff2: bc08 pop {r3} 8002ff4: 469e mov lr, r3 8002ff6: 4770 bx lr 08002ff8 <_fini>: 8002ff8: b5f8 push {r3, r4, r5, r6, r7, lr} 8002ffa: bf00 nop 8002ffc: bcf8 pop {r3, r4, r5, r6, r7} 8002ffe: bc08 pop {r3} 8003000: 469e mov lr, r3 8003002: 4770 bx lr