STM32F103_WifiAttenCtrlTest/Debug/STM32F103_WifiAttenCtrlTest.list

STM32F103_WifiAttenCtrlTest.elf:     file format elf32-littlearm

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .isr_vector   000001e4  08008000  08008000  00008000  2**0
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  1 .text         00003410  080081e4  080081e4  000081e4  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  2 .rodata       00000178  0800b5f4  0800b5f4  0000b5f4  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  3 .init_array   00000004  0800b76c  0800b76c  0000b76c  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  4 .fini_array   00000004  0800b770  0800b770  0000b770  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  5 .data         00000270  20000000  0800b774  00010000  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  6 .bss          00000af4  20000270  0800b9e4  00010270  2**2
                  ALLOC
  7 ._user_heap_stack 00000600  20000d64  0800b9e4  00010d64  2**0
                  ALLOC
  8 .ARM.attributes 00000029  00000000  00000000  00010270  2**0
                  CONTENTS, READONLY
  9 .debug_info   00014162  00000000  00000000  00010299  2**0
                  CONTENTS, READONLY, DEBUGGING
 10 .debug_abbrev 00002e6e  00000000  00000000  000243fb  2**0
                  CONTENTS, READONLY, DEBUGGING
 11 .debug_loc    00007c7f  00000000  00000000  00027269  2**0
                  CONTENTS, READONLY, DEBUGGING
 12 .debug_aranges 00000bc8  00000000  00000000  0002eee8  2**3
                  CONTENTS, READONLY, DEBUGGING
 13 .debug_ranges 00000fc0  00000000  00000000  0002fab0  2**3
                  CONTENTS, READONLY, DEBUGGING
 14 .debug_line   00006d54  00000000  00000000  00030a70  2**0
                  CONTENTS, READONLY, DEBUGGING
 15 .debug_str    0000446e  00000000  00000000  000377c4  2**0
                  CONTENTS, READONLY, DEBUGGING
 16 .comment      0000007c  00000000  00000000  0003bc32  2**0
                  CONTENTS, READONLY
 17 .debug_frame  00002998  00000000  00000000  0003bcb0  2**2
                  CONTENTS, READONLY, DEBUGGING

Disassembly of section .text:

080081e4 <__do_global_dtors_aux>:
 80081e4:	b510      	push	{r4, lr}
 80081e6:	4c05      	ldr	r4, [pc, #20]	; (80081fc <__do_global_dtors_aux+0x18>)
 80081e8:	7823      	ldrb	r3, [r4, #0]
 80081ea:	b933      	cbnz	r3, 80081fa <__do_global_dtors_aux+0x16>
 80081ec:	4b04      	ldr	r3, [pc, #16]	; (8008200 <__do_global_dtors_aux+0x1c>)
 80081ee:	b113      	cbz	r3, 80081f6 <__do_global_dtors_aux+0x12>
 80081f0:	4804      	ldr	r0, [pc, #16]	; (8008204 <__do_global_dtors_aux+0x20>)
 80081f2:	f3af 8000 	nop.w
 80081f6:	2301      	movs	r3, #1
 80081f8:	7023      	strb	r3, [r4, #0]
 80081fa:	bd10      	pop	{r4, pc}
 80081fc:	20000270 	.word	0x20000270
 8008200:	00000000 	.word	0x00000000
 8008204:	0800b5dc 	.word	0x0800b5dc

08008208 <frame_dummy>:
 8008208:	b508      	push	{r3, lr}
 800820a:	4b03      	ldr	r3, [pc, #12]	; (8008218 <frame_dummy+0x10>)
 800820c:	b11b      	cbz	r3, 8008216 <frame_dummy+0xe>
 800820e:	4903      	ldr	r1, [pc, #12]	; (800821c <frame_dummy+0x14>)
 8008210:	4803      	ldr	r0, [pc, #12]	; (8008220 <frame_dummy+0x18>)
 8008212:	f3af 8000 	nop.w
 8008216:	bd08      	pop	{r3, pc}
 8008218:	00000000 	.word	0x00000000
 800821c:	20000274 	.word	0x20000274
 8008220:	0800b5dc 	.word	0x0800b5dc

08008224 <HAL_InitTick>:
  *       implementation  in user file.
  * @param TickPriority Tick interrupt priority.
  * @retval HAL status
  */
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
 8008224:	b538      	push	{r3, r4, r5, lr}
  /* Configure the SysTick to have interrupt in 1ms time basis*/
  if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
 8008226:	4b0e      	ldr	r3, [pc, #56]	; (8008260 <HAL_InitTick+0x3c>)
{
 8008228:	4605      	mov	r5, r0
  if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
 800822a:	7818      	ldrb	r0, [r3, #0]
 800822c:	f44f 737a 	mov.w	r3, #1000	; 0x3e8
 8008230:	fbb3 f3f0 	udiv	r3, r3, r0
 8008234:	4a0b      	ldr	r2, [pc, #44]	; (8008264 <HAL_InitTick+0x40>)
 8008236:	6810      	ldr	r0, [r2, #0]
 8008238:	fbb0 f0f3 	udiv	r0, r0, r3
 800823c:	f000 fa4a 	bl	80086d4 <HAL_SYSTICK_Config>
 8008240:	4604      	mov	r4, r0
 8008242:	b958      	cbnz	r0, 800825c <HAL_InitTick+0x38>
  {
    return HAL_ERROR;
  }

  /* Configure the SysTick IRQ priority */
  if (TickPriority < (1UL << __NVIC_PRIO_BITS))
 8008244:	2d0f      	cmp	r5, #15
 8008246:	d809      	bhi.n	800825c <HAL_InitTick+0x38>
  {
    HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
 8008248:	4602      	mov	r2, r0
 800824a:	4629      	mov	r1, r5
 800824c:	f04f 30ff 	mov.w	r0, #4294967295
 8008250:	f000 f9fe 	bl	8008650 <HAL_NVIC_SetPriority>
    uwTickPrio = TickPriority;
 8008254:	4b04      	ldr	r3, [pc, #16]	; (8008268 <HAL_InitTick+0x44>)
 8008256:	4620      	mov	r0, r4
 8008258:	601d      	str	r5, [r3, #0]
 800825a:	bd38      	pop	{r3, r4, r5, pc}
    return HAL_ERROR;
 800825c:	2001      	movs	r0, #1
    return HAL_ERROR;
  }

  /* Return function status */
  return HAL_OK;
}
 800825e:	bd38      	pop	{r3, r4, r5, pc}
 8008260:	20000000 	.word	0x20000000
 8008264:	20000208 	.word	0x20000208
 8008268:	20000004 	.word	0x20000004

0800826c <HAL_Init>:
  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
 800826c:	4a07      	ldr	r2, [pc, #28]	; (800828c <HAL_Init+0x20>)
{
 800826e:	b508      	push	{r3, lr}
  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
 8008270:	6813      	ldr	r3, [r2, #0]
  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
 8008272:	2003      	movs	r0, #3
  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
 8008274:	f043 0310 	orr.w	r3, r3, #16
 8008278:	6013      	str	r3, [r2, #0]
  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
 800827a:	f000 f9d7 	bl	800862c <HAL_NVIC_SetPriorityGrouping>
  HAL_InitTick(TICK_INT_PRIORITY);
 800827e:	2000      	movs	r0, #0
 8008280:	f7ff ffd0 	bl	8008224 <HAL_InitTick>
  HAL_MspInit();
 8008284:	f001 fe98 	bl	8009fb8 <HAL_MspInit>
}
 8008288:	2000      	movs	r0, #0
 800828a:	bd08      	pop	{r3, pc}
 800828c:	40022000 	.word	0x40022000

08008290 <HAL_IncTick>:
  *      implementations in user file.
  * @retval None
  */
__weak void HAL_IncTick(void)
{
  uwTick += uwTickFreq;
 8008290:	4a03      	ldr	r2, [pc, #12]	; (80082a0 <HAL_IncTick+0x10>)
 8008292:	4b04      	ldr	r3, [pc, #16]	; (80082a4 <HAL_IncTick+0x14>)
 8008294:	6811      	ldr	r1, [r2, #0]
 8008296:	781b      	ldrb	r3, [r3, #0]
 8008298:	440b      	add	r3, r1
 800829a:	6013      	str	r3, [r2, #0]
 800829c:	4770      	bx	lr
 800829e:	bf00      	nop
 80082a0:	200002a4 	.word	0x200002a4
 80082a4:	20000000 	.word	0x20000000

080082a8 <HAL_GetTick>:
  *       implementations in user file.
  * @retval tick value
  */
__weak uint32_t HAL_GetTick(void)
{
  return uwTick;
 80082a8:	4b01      	ldr	r3, [pc, #4]	; (80082b0 <HAL_GetTick+0x8>)
 80082aa:	6818      	ldr	r0, [r3, #0]
}
 80082ac:	4770      	bx	lr
 80082ae:	bf00      	nop
 80082b0:	200002a4 	.word	0x200002a4

080082b4 <HAL_Delay>:
  *       implementations in user file.
  * @param Delay specifies the delay time length, in milliseconds.
  * @retval None
  */
__weak void HAL_Delay(uint32_t Delay)
{
 80082b4:	b538      	push	{r3, r4, r5, lr}
 80082b6:	4604      	mov	r4, r0
  uint32_t tickstart = HAL_GetTick();
 80082b8:	f7ff fff6 	bl	80082a8 <HAL_GetTick>
 80082bc:	4605      	mov	r5, r0
  uint32_t wait = Delay;

  /* Add a freq to guarantee minimum wait */
  if (wait < HAL_MAX_DELAY)
 80082be:	1c63      	adds	r3, r4, #1
  {
    wait += (uint32_t)(uwTickFreq);
 80082c0:	bf1e      	ittt	ne
 80082c2:	4b04      	ldrne	r3, [pc, #16]	; (80082d4 <HAL_Delay+0x20>)
 80082c4:	781b      	ldrbne	r3, [r3, #0]
 80082c6:	18e4      	addne	r4, r4, r3
  }

  while ((HAL_GetTick() - tickstart) < wait)
 80082c8:	f7ff ffee 	bl	80082a8 <HAL_GetTick>
 80082cc:	1b40      	subs	r0, r0, r5
 80082ce:	4284      	cmp	r4, r0
 80082d0:	d8fa      	bhi.n	80082c8 <HAL_Delay+0x14>
  {
  }
}
 80082d2:	bd38      	pop	{r3, r4, r5, pc}
 80082d4:	20000000 	.word	0x20000000

080082d8 <HAL_ADC_ConvCpltCallback>:
 80082d8:	4770      	bx	lr

080082da <HAL_ADC_LevelOutOfWindowCallback>:
 80082da:	4770      	bx	lr

080082dc <HAL_ADC_IRQHandler>:
  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
  assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
  
  
  /* ========== Check End of Conversion flag for regular group ========== */
  if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC))
 80082dc:	6803      	ldr	r3, [r0, #0]
{
 80082de:	b510      	push	{r4, lr}
  if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC))
 80082e0:	685a      	ldr	r2, [r3, #4]
{
 80082e2:	4604      	mov	r4, r0
  if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC))
 80082e4:	0690      	lsls	r0, r2, #26
 80082e6:	d527      	bpl.n	8008338 <HAL_ADC_IRQHandler+0x5c>
  {
    if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) )
 80082e8:	681a      	ldr	r2, [r3, #0]
 80082ea:	0791      	lsls	r1, r2, #30
 80082ec:	d524      	bpl.n	8008338 <HAL_ADC_IRQHandler+0x5c>
    {
      /* Update state machine on conversion status if not in error state */
      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
 80082ee:	6aa2      	ldr	r2, [r4, #40]	; 0x28
 80082f0:	06d2      	lsls	r2, r2, #27
      {
        /* Set ADC state */
        SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 
 80082f2:	bf5e      	ittt	pl
 80082f4:	6aa2      	ldrpl	r2, [r4, #40]	; 0x28
 80082f6:	f442 7200 	orrpl.w	r2, r2, #512	; 0x200
 80082fa:	62a2      	strpl	r2, [r4, #40]	; 0x28
      /* Determine whether any further conversion upcoming on group regular   */
      /* by external trigger, continuous mode or scan sequence on going.      */
      /* Note: On STM32F1 devices, in case of sequencer enabled               */
      /*       (several ranks selected), end of conversion flag is raised     */
      /*       at the end of the sequence.                                    */
      if(ADC_IS_SOFTWARE_START_REGULAR(hadc)        && 
 80082fc:	689a      	ldr	r2, [r3, #8]
 80082fe:	f402 2260 	and.w	r2, r2, #917504	; 0xe0000
 8008302:	f5b2 2f60 	cmp.w	r2, #917504	; 0xe0000
 8008306:	d110      	bne.n	800832a <HAL_ADC_IRQHandler+0x4e>
 8008308:	7b22      	ldrb	r2, [r4, #12]
 800830a:	b972      	cbnz	r2, 800832a <HAL_ADC_IRQHandler+0x4e>
         (hadc->Init.ContinuousConvMode == DISABLE)   )
      {
        /* Disable ADC end of conversion interrupt on group regular */
        __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
 800830c:	685a      	ldr	r2, [r3, #4]
 800830e:	f022 0220 	bic.w	r2, r2, #32
 8008312:	605a      	str	r2, [r3, #4]
        
        /* Set ADC state */
        CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);   
 8008314:	6aa3      	ldr	r3, [r4, #40]	; 0x28
 8008316:	f423 7380 	bic.w	r3, r3, #256	; 0x100
 800831a:	62a3      	str	r3, [r4, #40]	; 0x28
        
        if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
 800831c:	6aa3      	ldr	r3, [r4, #40]	; 0x28
 800831e:	04db      	lsls	r3, r3, #19
        {
          SET_BIT(hadc->State, HAL_ADC_STATE_READY);
 8008320:	bf5e      	ittt	pl
 8008322:	6aa3      	ldrpl	r3, [r4, #40]	; 0x28
 8008324:	f043 0301 	orrpl.w	r3, r3, #1
 8008328:	62a3      	strpl	r3, [r4, #40]	; 0x28

      /* Conversion complete callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
      hadc->ConvCpltCallback(hadc);
#else
      HAL_ADC_ConvCpltCallback(hadc);
 800832a:	4620      	mov	r0, r4
 800832c:	f7ff ffd4 	bl	80082d8 <HAL_ADC_ConvCpltCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
      
      /* Clear regular group conversion flag */
      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
 8008330:	f06f 0212 	mvn.w	r2, #18
 8008334:	6823      	ldr	r3, [r4, #0]
 8008336:	601a      	str	r2, [r3, #0]
    }
  }
  
  /* ========== Check End of Conversion flag for injected group ========== */
  if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC))
 8008338:	6823      	ldr	r3, [r4, #0]
 800833a:	685a      	ldr	r2, [r3, #4]
 800833c:	0610      	lsls	r0, r2, #24
 800833e:	d530      	bpl.n	80083a2 <HAL_ADC_IRQHandler+0xc6>
  {
    if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC))
 8008340:	681a      	ldr	r2, [r3, #0]
 8008342:	0751      	lsls	r1, r2, #29
 8008344:	d52d      	bpl.n	80083a2 <HAL_ADC_IRQHandler+0xc6>
    {
      /* Update state machine on conversion status if not in error state */
      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
 8008346:	6aa2      	ldr	r2, [r4, #40]	; 0x28
 8008348:	06d2      	lsls	r2, r2, #27
      {
        /* Set ADC state */
        SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
 800834a:	bf5e      	ittt	pl
 800834c:	6aa2      	ldrpl	r2, [r4, #40]	; 0x28
 800834e:	f442 5200 	orrpl.w	r2, r2, #8192	; 0x2000
 8008352:	62a2      	strpl	r2, [r4, #40]	; 0x28
      /* conversion from group regular (same conditions as group regular      */
      /* interruption disabling above).                                       */
      /* Note: On STM32F1 devices, in case of sequencer enabled               */
      /*       (several ranks selected), end of conversion flag is raised     */
      /*       at the end of the sequence.                                    */
      if(ADC_IS_SOFTWARE_START_INJECTED(hadc)                     || 
 8008354:	689a      	ldr	r2, [r3, #8]
 8008356:	f402 42e0 	and.w	r2, r2, #28672	; 0x7000
 800835a:	f5b2 4fe0 	cmp.w	r2, #28672	; 0x7000
 800835e:	d00a      	beq.n	8008376 <HAL_ADC_IRQHandler+0x9a>
         (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&     
 8008360:	685a      	ldr	r2, [r3, #4]
      if(ADC_IS_SOFTWARE_START_INJECTED(hadc)                     || 
 8008362:	0550      	lsls	r0, r2, #21
 8008364:	d416      	bmi.n	8008394 <HAL_ADC_IRQHandler+0xb8>
         (ADC_IS_SOFTWARE_START_REGULAR(hadc)        &&
 8008366:	689a      	ldr	r2, [r3, #8]
 8008368:	f402 2260 	and.w	r2, r2, #917504	; 0xe0000
         (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&     
 800836c:	f5b2 2f60 	cmp.w	r2, #917504	; 0xe0000
 8008370:	d110      	bne.n	8008394 <HAL_ADC_IRQHandler+0xb8>
         (ADC_IS_SOFTWARE_START_REGULAR(hadc)        &&
 8008372:	7b22      	ldrb	r2, [r4, #12]
 8008374:	b972      	cbnz	r2, 8008394 <HAL_ADC_IRQHandler+0xb8>
          (hadc->Init.ContinuousConvMode == DISABLE)   )        )   )
      {
        /* Disable ADC end of conversion interrupt on group injected */
        __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
 8008376:	685a      	ldr	r2, [r3, #4]
 8008378:	f022 0280 	bic.w	r2, r2, #128	; 0x80
 800837c:	605a      	str	r2, [r3, #4]
        
        /* Set ADC state */
        CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);   
 800837e:	6aa3      	ldr	r3, [r4, #40]	; 0x28
 8008380:	f423 5380 	bic.w	r3, r3, #4096	; 0x1000
 8008384:	62a3      	str	r3, [r4, #40]	; 0x28

        if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
 8008386:	6aa3      	ldr	r3, [r4, #40]	; 0x28
 8008388:	05d9      	lsls	r1, r3, #23
        { 
          SET_BIT(hadc->State, HAL_ADC_STATE_READY);
 800838a:	bf5e      	ittt	pl
 800838c:	6aa3      	ldrpl	r3, [r4, #40]	; 0x28
 800838e:	f043 0301 	orrpl.w	r3, r3, #1
 8008392:	62a3      	strpl	r3, [r4, #40]	; 0x28

      /* Conversion complete callback */ 
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
      hadc->InjectedConvCpltCallback(hadc);
#else
      HAL_ADCEx_InjectedConvCpltCallback(hadc);
 8008394:	4620      	mov	r0, r4
 8008396:	f000 f947 	bl	8008628 <HAL_ADCEx_InjectedConvCpltCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
      
      /* Clear injected group conversion flag */
      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC));
 800839a:	f06f 020c 	mvn.w	r2, #12
 800839e:	6823      	ldr	r3, [r4, #0]
 80083a0:	601a      	str	r2, [r3, #0]
    }
  }
   
  /* ========== Check Analog watchdog flags ========== */
  if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD))
 80083a2:	6823      	ldr	r3, [r4, #0]
 80083a4:	685a      	ldr	r2, [r3, #4]
 80083a6:	0652      	lsls	r2, r2, #25
 80083a8:	d50d      	bpl.n	80083c6 <HAL_ADC_IRQHandler+0xea>
  {
    if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD))
 80083aa:	681b      	ldr	r3, [r3, #0]
 80083ac:	07db      	lsls	r3, r3, #31
 80083ae:	d50a      	bpl.n	80083c6 <HAL_ADC_IRQHandler+0xea>
    {
      /* Set ADC state */
      SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
 80083b0:	6aa3      	ldr	r3, [r4, #40]	; 0x28
      
      /* Level out of window callback */ 
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
      hadc->LevelOutOfWindowCallback(hadc);
#else
      HAL_ADC_LevelOutOfWindowCallback(hadc);
 80083b2:	4620      	mov	r0, r4
      SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
 80083b4:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
 80083b8:	62a3      	str	r3, [r4, #40]	; 0x28
      HAL_ADC_LevelOutOfWindowCallback(hadc);
 80083ba:	f7ff ff8e 	bl	80082da <HAL_ADC_LevelOutOfWindowCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
      
      /* Clear the ADC analog watchdog flag */
      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
 80083be:	f06f 0201 	mvn.w	r2, #1
 80083c2:	6823      	ldr	r3, [r4, #0]
 80083c4:	601a      	str	r2, [r3, #0]
 80083c6:	bd10      	pop	{r4, pc}

080083c8 <HAL_ADC_ConfigChannel>:
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
{ 
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
  __IO uint32_t wait_loop_index = 0U;
 80083c8:	2300      	movs	r3, #0
{ 
 80083ca:	b573      	push	{r0, r1, r4, r5, r6, lr}
  __IO uint32_t wait_loop_index = 0U;
 80083cc:	9301      	str	r3, [sp, #4]
  assert_param(IS_ADC_CHANNEL(sConfig->Channel));
  assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
  assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
  
  /* Process locked */
  __HAL_LOCK(hadc);
 80083ce:	f890 3024 	ldrb.w	r3, [r0, #36]	; 0x24
 80083d2:	2b01      	cmp	r3, #1
 80083d4:	d074      	beq.n	80084c0 <HAL_ADC_ConfigChannel+0xf8>
 80083d6:	2301      	movs	r3, #1
  
  
  /* Regular sequence configuration */
  /* For Rank 1 to 6 */
  if (sConfig->Rank < 7U)
 80083d8:	684d      	ldr	r5, [r1, #4]
  __HAL_LOCK(hadc);
 80083da:	f880 3024 	strb.w	r3, [r0, #36]	; 0x24
  if (sConfig->Rank < 7U)
 80083de:	2d06      	cmp	r5, #6
 80083e0:	6802      	ldr	r2, [r0, #0]
 80083e2:	ea4f 0385 	mov.w	r3, r5, lsl #2
 80083e6:	680c      	ldr	r4, [r1, #0]
 80083e8:	d825      	bhi.n	8008436 <HAL_ADC_ConfigChannel+0x6e>
  {
    MODIFY_REG(hadc->Instance->SQR3                        ,
 80083ea:	442b      	add	r3, r5
 80083ec:	251f      	movs	r5, #31
 80083ee:	6b56      	ldr	r6, [r2, #52]	; 0x34
 80083f0:	3b05      	subs	r3, #5
 80083f2:	409d      	lsls	r5, r3
 80083f4:	ea26 0505 	bic.w	r5, r6, r5
 80083f8:	fa04 f303 	lsl.w	r3, r4, r3
 80083fc:	432b      	orrs	r3, r5
 80083fe:	6353      	str	r3, [r2, #52]	; 0x34
  }
  
  
  /* Channel sampling time configuration */
  /* For channels 10 to 17 */
  if (sConfig->Channel >= ADC_CHANNEL_10)
 8008400:	2c09      	cmp	r4, #9
 8008402:	ea4f 0344 	mov.w	r3, r4, lsl #1
 8008406:	688d      	ldr	r5, [r1, #8]
 8008408:	d92f      	bls.n	800846a <HAL_ADC_ConfigChannel+0xa2>
  {
    MODIFY_REG(hadc->Instance->SMPR1                             ,
 800840a:	2607      	movs	r6, #7
 800840c:	4423      	add	r3, r4
 800840e:	68d1      	ldr	r1, [r2, #12]
 8008410:	3b1e      	subs	r3, #30
 8008412:	409e      	lsls	r6, r3
 8008414:	ea21 0106 	bic.w	r1, r1, r6
 8008418:	fa05 f303 	lsl.w	r3, r5, r3
 800841c:	430b      	orrs	r3, r1
 800841e:	60d3      	str	r3, [r2, #12]
               ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
  }
  
  /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor  */
  /* and VREFINT measurement path.                                            */
  if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
 8008420:	f1a4 0310 	sub.w	r3, r4, #16
 8008424:	2b01      	cmp	r3, #1
 8008426:	d92b      	bls.n	8008480 <HAL_ADC_ConfigChannel+0xb8>
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
 8008428:	2300      	movs	r3, #0
      tmp_hal_status = HAL_ERROR;
    }
  }
  
  /* Process unlocked */
  __HAL_UNLOCK(hadc);
 800842a:	2200      	movs	r2, #0
 800842c:	f880 2024 	strb.w	r2, [r0, #36]	; 0x24
  
  /* Return function status */
  return tmp_hal_status;
}
 8008430:	4618      	mov	r0, r3
 8008432:	b002      	add	sp, #8
 8008434:	bd70      	pop	{r4, r5, r6, pc}
  else if (sConfig->Rank < 13U)
 8008436:	2d0c      	cmp	r5, #12
 8008438:	d80b      	bhi.n	8008452 <HAL_ADC_ConfigChannel+0x8a>
    MODIFY_REG(hadc->Instance->SQR2                        ,
 800843a:	442b      	add	r3, r5
 800843c:	251f      	movs	r5, #31
 800843e:	6b16      	ldr	r6, [r2, #48]	; 0x30
 8008440:	3b23      	subs	r3, #35	; 0x23
 8008442:	409d      	lsls	r5, r3
 8008444:	ea26 0505 	bic.w	r5, r6, r5
 8008448:	fa04 f303 	lsl.w	r3, r4, r3
 800844c:	432b      	orrs	r3, r5
 800844e:	6313      	str	r3, [r2, #48]	; 0x30
 8008450:	e7d6      	b.n	8008400 <HAL_ADC_ConfigChannel+0x38>
    MODIFY_REG(hadc->Instance->SQR1                        ,
 8008452:	442b      	add	r3, r5
 8008454:	251f      	movs	r5, #31
 8008456:	6ad6      	ldr	r6, [r2, #44]	; 0x2c
 8008458:	3b41      	subs	r3, #65	; 0x41
 800845a:	409d      	lsls	r5, r3
 800845c:	ea26 0505 	bic.w	r5, r6, r5
 8008460:	fa04 f303 	lsl.w	r3, r4, r3
 8008464:	432b      	orrs	r3, r5
 8008466:	62d3      	str	r3, [r2, #44]	; 0x2c
 8008468:	e7ca      	b.n	8008400 <HAL_ADC_ConfigChannel+0x38>
    MODIFY_REG(hadc->Instance->SMPR2                             ,
 800846a:	2607      	movs	r6, #7
 800846c:	6911      	ldr	r1, [r2, #16]
 800846e:	4423      	add	r3, r4
 8008470:	409e      	lsls	r6, r3
 8008472:	ea21 0106 	bic.w	r1, r1, r6
 8008476:	fa05 f303 	lsl.w	r3, r5, r3
 800847a:	430b      	orrs	r3, r1
 800847c:	6113      	str	r3, [r2, #16]
 800847e:	e7cf      	b.n	8008420 <HAL_ADC_ConfigChannel+0x58>
    if (hadc->Instance == ADC1)
 8008480:	4b10      	ldr	r3, [pc, #64]	; (80084c4 <HAL_ADC_ConfigChannel+0xfc>)
 8008482:	429a      	cmp	r2, r3
 8008484:	d116      	bne.n	80084b4 <HAL_ADC_ConfigChannel+0xec>
      if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET)
 8008486:	6893      	ldr	r3, [r2, #8]
 8008488:	021b      	lsls	r3, r3, #8
 800848a:	d4cd      	bmi.n	8008428 <HAL_ADC_ConfigChannel+0x60>
        SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
 800848c:	6893      	ldr	r3, [r2, #8]
        if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
 800848e:	2c10      	cmp	r4, #16
        SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
 8008490:	f443 0300 	orr.w	r3, r3, #8388608	; 0x800000
 8008494:	6093      	str	r3, [r2, #8]
        if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
 8008496:	d1c7      	bne.n	8008428 <HAL_ADC_ConfigChannel+0x60>
          wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
 8008498:	4b0b      	ldr	r3, [pc, #44]	; (80084c8 <HAL_ADC_ConfigChannel+0x100>)
 800849a:	4a0c      	ldr	r2, [pc, #48]	; (80084cc <HAL_ADC_ConfigChannel+0x104>)
 800849c:	681b      	ldr	r3, [r3, #0]
 800849e:	fbb3 f2f2 	udiv	r2, r3, r2
 80084a2:	230a      	movs	r3, #10
 80084a4:	4353      	muls	r3, r2
            wait_loop_index--;
 80084a6:	9301      	str	r3, [sp, #4]
          while(wait_loop_index != 0U)
 80084a8:	9b01      	ldr	r3, [sp, #4]
 80084aa:	2b00      	cmp	r3, #0
 80084ac:	d0bc      	beq.n	8008428 <HAL_ADC_ConfigChannel+0x60>
            wait_loop_index--;
 80084ae:	9b01      	ldr	r3, [sp, #4]
 80084b0:	3b01      	subs	r3, #1
 80084b2:	e7f8      	b.n	80084a6 <HAL_ADC_ConfigChannel+0xde>
      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
 80084b4:	6a83      	ldr	r3, [r0, #40]	; 0x28
 80084b6:	f043 0320 	orr.w	r3, r3, #32
 80084ba:	6283      	str	r3, [r0, #40]	; 0x28
      tmp_hal_status = HAL_ERROR;
 80084bc:	2301      	movs	r3, #1
 80084be:	e7b4      	b.n	800842a <HAL_ADC_ConfigChannel+0x62>
  __HAL_LOCK(hadc);
 80084c0:	2302      	movs	r3, #2
 80084c2:	e7b5      	b.n	8008430 <HAL_ADC_ConfigChannel+0x68>
 80084c4:	40012400 	.word	0x40012400
 80084c8:	20000208 	.word	0x20000208
 80084cc:	000f4240 	.word	0x000f4240

080084d0 <ADC_ConversionStop_Disable>:
  *         stopped to disable the ADC.
  * @param  hadc: ADC handle
  * @retval HAL status.
  */
HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc)
{
 80084d0:	b538      	push	{r3, r4, r5, lr}
  uint32_t tickstart = 0U;
  
  /* Verification if ADC is not already disabled */
  if (ADC_IS_ENABLE(hadc) != RESET)
 80084d2:	6803      	ldr	r3, [r0, #0]
{
 80084d4:	4604      	mov	r4, r0
  if (ADC_IS_ENABLE(hadc) != RESET)
 80084d6:	689a      	ldr	r2, [r3, #8]
 80084d8:	07d2      	lsls	r2, r2, #31
 80084da:	d401      	bmi.n	80084e0 <ADC_ConversionStop_Disable+0x10>
      }
    }
  }
  
  /* Return HAL status */
  return HAL_OK;
 80084dc:	2000      	movs	r0, #0
 80084de:	bd38      	pop	{r3, r4, r5, pc}
    __HAL_ADC_DISABLE(hadc);
 80084e0:	689a      	ldr	r2, [r3, #8]
 80084e2:	f022 0201 	bic.w	r2, r2, #1
 80084e6:	609a      	str	r2, [r3, #8]
    tickstart = HAL_GetTick();
 80084e8:	f7ff fede 	bl	80082a8 <HAL_GetTick>
 80084ec:	4605      	mov	r5, r0
    while(ADC_IS_ENABLE(hadc) != RESET)
 80084ee:	6823      	ldr	r3, [r4, #0]
 80084f0:	689b      	ldr	r3, [r3, #8]
 80084f2:	07db      	lsls	r3, r3, #31
 80084f4:	d5f2      	bpl.n	80084dc <ADC_ConversionStop_Disable+0xc>
      if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
 80084f6:	f7ff fed7 	bl	80082a8 <HAL_GetTick>
 80084fa:	1b40      	subs	r0, r0, r5
 80084fc:	2802      	cmp	r0, #2
 80084fe:	d9f6      	bls.n	80084ee <ADC_ConversionStop_Disable+0x1e>
        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
 8008500:	6aa3      	ldr	r3, [r4, #40]	; 0x28
        SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
 8008502:	2001      	movs	r0, #1
        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
 8008504:	f043 0310 	orr.w	r3, r3, #16
 8008508:	62a3      	str	r3, [r4, #40]	; 0x28
        SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
 800850a:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
 800850c:	f043 0301 	orr.w	r3, r3, #1
 8008510:	62e3      	str	r3, [r4, #44]	; 0x2c
 8008512:	bd38      	pop	{r3, r4, r5, pc}

08008514 <HAL_ADC_Init>:
{
 8008514:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
  if(hadc == NULL)
 8008516:	4604      	mov	r4, r0
 8008518:	2800      	cmp	r0, #0
 800851a:	d077      	beq.n	800860c <HAL_ADC_Init+0xf8>
  if (hadc->State == HAL_ADC_STATE_RESET)
 800851c:	6a83      	ldr	r3, [r0, #40]	; 0x28
 800851e:	b923      	cbnz	r3, 800852a <HAL_ADC_Init+0x16>
    ADC_CLEAR_ERRORCODE(hadc);
 8008520:	62c3      	str	r3, [r0, #44]	; 0x2c
    hadc->Lock = HAL_UNLOCKED;
 8008522:	f880 3024 	strb.w	r3, [r0, #36]	; 0x24
    HAL_ADC_MspInit(hadc);
 8008526:	f001 fd69 	bl	8009ffc <HAL_ADC_MspInit>
  tmp_hal_status = ADC_ConversionStop_Disable(hadc);
 800852a:	4620      	mov	r0, r4
 800852c:	f7ff ffd0 	bl	80084d0 <ADC_ConversionStop_Disable>
  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
 8008530:	6aa3      	ldr	r3, [r4, #40]	; 0x28
 8008532:	f013 0310 	ands.w	r3, r3, #16
 8008536:	d16b      	bne.n	8008610 <HAL_ADC_Init+0xfc>
 8008538:	2800      	cmp	r0, #0
 800853a:	d169      	bne.n	8008610 <HAL_ADC_Init+0xfc>
    ADC_STATE_CLR_SET(hadc->State,
 800853c:	6aa2      	ldr	r2, [r4, #40]	; 0x28
                ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv)            |
 800853e:	4937      	ldr	r1, [pc, #220]	; (800861c <HAL_ADC_Init+0x108>)
    ADC_STATE_CLR_SET(hadc->State,
 8008540:	f422 5288 	bic.w	r2, r2, #4352	; 0x1100
 8008544:	f022 0202 	bic.w	r2, r2, #2
 8008548:	f042 0202 	orr.w	r2, r2, #2
 800854c:	62a2      	str	r2, [r4, #40]	; 0x28
                ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv)            |
 800854e:	e894 0024 	ldmia.w	r4, {r2, r5}
 8008552:	428a      	cmp	r2, r1
 8008554:	69e1      	ldr	r1, [r4, #28]
 8008556:	d104      	bne.n	8008562 <HAL_ADC_Init+0x4e>
 8008558:	f5b1 2f40 	cmp.w	r1, #786432	; 0xc0000
 800855c:	bf08      	it	eq
 800855e:	f44f 2100 	moveq.w	r1, #524288	; 0x80000
                ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode)   );
 8008562:	7b26      	ldrb	r6, [r4, #12]
                ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv)            |
 8008564:	ea45 0546 	orr.w	r5, r5, r6, lsl #1
 8008568:	4329      	orrs	r1, r5
    tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode));
 800856a:	68a5      	ldr	r5, [r4, #8]
 800856c:	f5b5 7f80 	cmp.w	r5, #256	; 0x100
 8008570:	d035      	beq.n	80085de <HAL_ADC_Init+0xca>
 8008572:	2d01      	cmp	r5, #1
 8008574:	bf08      	it	eq
 8008576:	f44f 7380 	moveq.w	r3, #256	; 0x100
    if (hadc->Init.DiscontinuousConvMode == ENABLE)
 800857a:	7d27      	ldrb	r7, [r4, #20]
 800857c:	2f01      	cmp	r7, #1
 800857e:	d106      	bne.n	800858e <HAL_ADC_Init+0x7a>
      if (hadc->Init.ContinuousConvMode == DISABLE)
 8008580:	bb7e      	cbnz	r6, 80085e2 <HAL_ADC_Init+0xce>
        SET_BIT(tmp_cr1, ADC_CR1_DISCEN                                            |
 8008582:	69a6      	ldr	r6, [r4, #24]
 8008584:	3e01      	subs	r6, #1
 8008586:	ea43 3346 	orr.w	r3, r3, r6, lsl #13
 800858a:	f443 6300 	orr.w	r3, r3, #2048	; 0x800
      MODIFY_REG(hadc->Instance->CR1,
 800858e:	6856      	ldr	r6, [r2, #4]
    if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE)
 8008590:	f5b5 7f80 	cmp.w	r5, #256	; 0x100
      MODIFY_REG(hadc->Instance->CR1,
 8008594:	f426 4669 	bic.w	r6, r6, #59648	; 0xe900
 8008598:	ea43 0306 	orr.w	r3, r3, r6
 800859c:	6053      	str	r3, [r2, #4]
      MODIFY_REG(hadc->Instance->CR2,
 800859e:	6896      	ldr	r6, [r2, #8]
 80085a0:	4b1f      	ldr	r3, [pc, #124]	; (8008620 <HAL_ADC_Init+0x10c>)
 80085a2:	ea03 0306 	and.w	r3, r3, r6
 80085a6:	ea43 0301 	orr.w	r3, r3, r1
 80085aa:	6093      	str	r3, [r2, #8]
    if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE)
 80085ac:	d001      	beq.n	80085b2 <HAL_ADC_Init+0x9e>
 80085ae:	2d01      	cmp	r5, #1
 80085b0:	d120      	bne.n	80085f4 <HAL_ADC_Init+0xe0>
      tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion);
 80085b2:	6923      	ldr	r3, [r4, #16]
 80085b4:	3b01      	subs	r3, #1
 80085b6:	051b      	lsls	r3, r3, #20
    MODIFY_REG(hadc->Instance->SQR1,
 80085b8:	6ad5      	ldr	r5, [r2, #44]	; 0x2c
 80085ba:	f425 0570 	bic.w	r5, r5, #15728640	; 0xf00000
 80085be:	432b      	orrs	r3, r5
 80085c0:	62d3      	str	r3, [r2, #44]	; 0x2c
    if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
 80085c2:	6892      	ldr	r2, [r2, #8]
 80085c4:	4b17      	ldr	r3, [pc, #92]	; (8008624 <HAL_ADC_Init+0x110>)
 80085c6:	4013      	ands	r3, r2
 80085c8:	4299      	cmp	r1, r3
 80085ca:	d115      	bne.n	80085f8 <HAL_ADC_Init+0xe4>
      ADC_CLEAR_ERRORCODE(hadc);
 80085cc:	2300      	movs	r3, #0
 80085ce:	62e3      	str	r3, [r4, #44]	; 0x2c
      ADC_STATE_CLR_SET(hadc->State,
 80085d0:	6aa3      	ldr	r3, [r4, #40]	; 0x28
 80085d2:	f023 0303 	bic.w	r3, r3, #3
 80085d6:	f043 0301 	orr.w	r3, r3, #1
 80085da:	62a3      	str	r3, [r4, #40]	; 0x28
 80085dc:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode));
 80085de:	462b      	mov	r3, r5
 80085e0:	e7cb      	b.n	800857a <HAL_ADC_Init+0x66>
        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
 80085e2:	6aa6      	ldr	r6, [r4, #40]	; 0x28
 80085e4:	f046 0620 	orr.w	r6, r6, #32
 80085e8:	62a6      	str	r6, [r4, #40]	; 0x28
        SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
 80085ea:	6ae6      	ldr	r6, [r4, #44]	; 0x2c
 80085ec:	f046 0601 	orr.w	r6, r6, #1
 80085f0:	62e6      	str	r6, [r4, #44]	; 0x2c
 80085f2:	e7cc      	b.n	800858e <HAL_ADC_Init+0x7a>
  uint32_t tmp_sqr1 = 0U;
 80085f4:	2300      	movs	r3, #0
 80085f6:	e7df      	b.n	80085b8 <HAL_ADC_Init+0xa4>
      ADC_STATE_CLR_SET(hadc->State,
 80085f8:	6aa3      	ldr	r3, [r4, #40]	; 0x28
 80085fa:	f023 0312 	bic.w	r3, r3, #18
 80085fe:	f043 0310 	orr.w	r3, r3, #16
 8008602:	62a3      	str	r3, [r4, #40]	; 0x28
      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
 8008604:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
 8008606:	f043 0301 	orr.w	r3, r3, #1
 800860a:	62e3      	str	r3, [r4, #44]	; 0x2c
    return HAL_ERROR;
 800860c:	2001      	movs	r0, #1
}
 800860e:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
 8008610:	6aa3      	ldr	r3, [r4, #40]	; 0x28
 8008612:	f043 0310 	orr.w	r3, r3, #16
 8008616:	62a3      	str	r3, [r4, #40]	; 0x28
 8008618:	e7f8      	b.n	800860c <HAL_ADC_Init+0xf8>
 800861a:	bf00      	nop
 800861c:	40013c00 	.word	0x40013c00
 8008620:	ffe1f7fd 	.word	0xffe1f7fd
 8008624:	ff1f0efe 	.word	0xff1f0efe

08008628 <HAL_ADCEx_InjectedConvCpltCallback>:
  * @brief  Injected conversion complete callback in non blocking mode 
  * @param  hadc: ADC handle
  * @retval None
  */
__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
{
 8008628:	4770      	bx	lr
	...

0800862c <HAL_NVIC_SetPriorityGrouping>:
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
  uint32_t reg_value;
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */

  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
 800862c:	4a07      	ldr	r2, [pc, #28]	; (800864c <HAL_NVIC_SetPriorityGrouping+0x20>)
  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
  reg_value  =  (reg_value                                   |
                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) );               /* Insert write key and priority group */
 800862e:	0200      	lsls	r0, r0, #8
  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
 8008630:	68d3      	ldr	r3, [r2, #12]
                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) );               /* Insert write key and priority group */
 8008632:	f400 60e0 	and.w	r0, r0, #1792	; 0x700
  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
 8008636:	f423 63e0 	bic.w	r3, r3, #1792	; 0x700
 800863a:	041b      	lsls	r3, r3, #16
 800863c:	0c1b      	lsrs	r3, r3, #16
 800863e:	f043 63bf 	orr.w	r3, r3, #100139008	; 0x5f80000
 8008642:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
  reg_value  =  (reg_value                                   |
 8008646:	4303      	orrs	r3, r0
  SCB->AIRCR =  reg_value;
 8008648:	60d3      	str	r3, [r2, #12]
 800864a:	4770      	bx	lr
 800864c:	e000ed00 	.word	0xe000ed00

08008650 <HAL_NVIC_SetPriority>:
  \details Reads the priority grouping field from the NVIC Interrupt Controller.
  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
 */
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
 8008650:	4b17      	ldr	r3, [pc, #92]	; (80086b0 <HAL_NVIC_SetPriority+0x60>)
  *         This parameter can be a value between 0 and 15
  *         A lower priority value indicates a higher priority.          
  * @retval None
  */
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{ 
 8008652:	b530      	push	{r4, r5, lr}
 8008654:	68dc      	ldr	r4, [r3, #12]
 8008656:	f3c4 2402 	ubfx	r4, r4, #8, #3
{
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
  uint32_t PreemptPriorityBits;
  uint32_t SubPriorityBits;

  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
 800865a:	f1c4 0307 	rsb	r3, r4, #7
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 800865e:	1d25      	adds	r5, r4, #4
  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
 8008660:	2b04      	cmp	r3, #4
 8008662:	bf28      	it	cs
 8008664:	2304      	movcs	r3, #4
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 8008666:	2d06      	cmp	r5, #6

  return (
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 8008668:	f04f 0501 	mov.w	r5, #1
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 800866c:	bf98      	it	ls
 800866e:	2400      	movls	r4, #0
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 8008670:	fa05 f303 	lsl.w	r3, r5, r3
 8008674:	f103 33ff 	add.w	r3, r3, #4294967295
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 8008678:	bf88      	it	hi
 800867a:	3c03      	subhi	r4, #3
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 800867c:	4019      	ands	r1, r3
 800867e:	40a1      	lsls	r1, r4
           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
 8008680:	fa05 f404 	lsl.w	r4, r5, r4
 8008684:	3c01      	subs	r4, #1
 8008686:	4022      	ands	r2, r4
  if ((int32_t)(IRQn) >= 0)
 8008688:	2800      	cmp	r0, #0
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 800868a:	ea42 0201 	orr.w	r2, r2, r1
 800868e:	ea4f 1202 	mov.w	r2, r2, lsl #4
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8008692:	bfa9      	itett	ge
 8008694:	f100 4060 	addge.w	r0, r0, #3758096384	; 0xe0000000
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8008698:	4b06      	ldrlt	r3, [pc, #24]	; (80086b4 <HAL_NVIC_SetPriority+0x64>)
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 800869a:	b2d2      	uxtbge	r2, r2
 800869c:	f500 4061 	addge.w	r0, r0, #57600	; 0xe100
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 80086a0:	bfbb      	ittet	lt
 80086a2:	f000 000f 	andlt.w	r0, r0, #15
 80086a6:	b2d2      	uxtblt	r2, r2
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 80086a8:	f880 2300 	strbge.w	r2, [r0, #768]	; 0x300
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 80086ac:	541a      	strblt	r2, [r3, r0]
 80086ae:	bd30      	pop	{r4, r5, pc}
 80086b0:	e000ed00 	.word	0xe000ed00
 80086b4:	e000ed14 	.word	0xe000ed14

080086b8 <HAL_NVIC_EnableIRQ>:
  if ((int32_t)(IRQn) >= 0)
 80086b8:	2800      	cmp	r0, #0
 80086ba:	db08      	blt.n	80086ce <HAL_NVIC_EnableIRQ+0x16>
    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
 80086bc:	2301      	movs	r3, #1
 80086be:	0942      	lsrs	r2, r0, #5
 80086c0:	f000 001f 	and.w	r0, r0, #31
 80086c4:	fa03 f000 	lsl.w	r0, r3, r0
 80086c8:	4b01      	ldr	r3, [pc, #4]	; (80086d0 <HAL_NVIC_EnableIRQ+0x18>)
 80086ca:	f843 0022 	str.w	r0, [r3, r2, lsl #2]
 80086ce:	4770      	bx	lr
 80086d0:	e000e100 	.word	0xe000e100

080086d4 <HAL_SYSTICK_Config>:
           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
           must contain a vendor-specific implementation of this function.
 */
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
 80086d4:	3801      	subs	r0, #1
 80086d6:	f1b0 7f80 	cmp.w	r0, #16777216	; 0x1000000
 80086da:	d20a      	bcs.n	80086f2 <HAL_SYSTICK_Config+0x1e>
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 80086dc:	21f0      	movs	r1, #240	; 0xf0
  {
    return (1UL);                                                   /* Reload value impossible */
  }

  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
 80086de:	4b06      	ldr	r3, [pc, #24]	; (80086f8 <HAL_SYSTICK_Config+0x24>)
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 80086e0:	4a06      	ldr	r2, [pc, #24]	; (80086fc <HAL_SYSTICK_Config+0x28>)
  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
 80086e2:	6058      	str	r0, [r3, #4]
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 80086e4:	f882 1023 	strb.w	r1, [r2, #35]	; 0x23
  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
 80086e8:	2000      	movs	r0, #0
  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
 80086ea:	2207      	movs	r2, #7
  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
 80086ec:	6098      	str	r0, [r3, #8]
  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
 80086ee:	601a      	str	r2, [r3, #0]
 80086f0:	4770      	bx	lr
    return (1UL);                                                   /* Reload value impossible */
 80086f2:	2001      	movs	r0, #1
  *                  - 1  Function failed.
  */
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
   return SysTick_Config(TicksNumb);
}
 80086f4:	4770      	bx	lr
 80086f6:	bf00      	nop
 80086f8:	e000e010 	.word	0xe000e010
 80086fc:	e000ed00 	.word	0xe000ed00

08008700 <HAL_DMA_Init>:
  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
  *               the configuration information for the specified DMA Channel.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
{
 8008700:	b510      	push	{r4, lr}
  uint32_t tmp = 0U;

  /* Check the DMA handle allocation */
  if(hdma == NULL)
 8008702:	2800      	cmp	r0, #0
 8008704:	d032      	beq.n	800876c <HAL_DMA_Init+0x6c>
  assert_param(IS_DMA_MODE(hdma->Init.Mode));
  assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));

#if defined (DMA2)
  /* calculation of the channel index */
  if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
 8008706:	6801      	ldr	r1, [r0, #0]
 8008708:	4b19      	ldr	r3, [pc, #100]	; (8008770 <HAL_DMA_Init+0x70>)
 800870a:	2414      	movs	r4, #20
 800870c:	4299      	cmp	r1, r3
 800870e:	d825      	bhi.n	800875c <HAL_DMA_Init+0x5c>
  {
    /* DMA1 */
    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
 8008710:	4a18      	ldr	r2, [pc, #96]	; (8008774 <HAL_DMA_Init+0x74>)
    hdma->DmaBaseAddress = DMA1;
 8008712:	f2a3 4307 	subw	r3, r3, #1031	; 0x407
    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
 8008716:	440a      	add	r2, r1
 8008718:	fbb2 f2f4 	udiv	r2, r2, r4
 800871c:	0092      	lsls	r2, r2, #2
 800871e:	6402      	str	r2, [r0, #64]	; 0x40
  tmp &= ((uint32_t)~(DMA_CCR_PL    | DMA_CCR_MSIZE  | DMA_CCR_PSIZE  | \
                      DMA_CCR_MINC  | DMA_CCR_PINC   | DMA_CCR_CIRC   | \
                      DMA_CCR_DIR));

  /* Prepare the DMA Channel configuration */
  tmp |=  hdma->Init.Direction        |
 8008720:	6884      	ldr	r4, [r0, #8]
    hdma->DmaBaseAddress = DMA2;
 8008722:	63c3      	str	r3, [r0, #60]	; 0x3c
  tmp |=  hdma->Init.Direction        |
 8008724:	6843      	ldr	r3, [r0, #4]
  tmp = hdma->Instance->CCR;
 8008726:	680a      	ldr	r2, [r1, #0]
  tmp |=  hdma->Init.Direction        |
 8008728:	4323      	orrs	r3, r4
          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
 800872a:	68c4      	ldr	r4, [r0, #12]
  tmp &= ((uint32_t)~(DMA_CCR_PL    | DMA_CCR_MSIZE  | DMA_CCR_PSIZE  | \
 800872c:	f422 527f 	bic.w	r2, r2, #16320	; 0x3fc0
          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
 8008730:	4323      	orrs	r3, r4
 8008732:	6904      	ldr	r4, [r0, #16]
  tmp &= ((uint32_t)~(DMA_CCR_PL    | DMA_CCR_MSIZE  | DMA_CCR_PSIZE  | \
 8008734:	f022 0230 	bic.w	r2, r2, #48	; 0x30
          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
 8008738:	4323      	orrs	r3, r4
          hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
 800873a:	6944      	ldr	r4, [r0, #20]
 800873c:	4323      	orrs	r3, r4
 800873e:	6984      	ldr	r4, [r0, #24]
 8008740:	4323      	orrs	r3, r4
          hdma->Init.Mode                | hdma->Init.Priority;
 8008742:	69c4      	ldr	r4, [r0, #28]
 8008744:	4323      	orrs	r3, r4
  tmp |=  hdma->Init.Direction        |
 8008746:	4313      	orrs	r3, r2

  /* Write to DMA Channel CR register */
  hdma->Instance->CCR = tmp;
 8008748:	600b      	str	r3, [r1, #0]

  /* Initialise the error code */
  hdma->ErrorCode = HAL_DMA_ERROR_NONE;

  /* Initialize the DMA state*/
  hdma->State = HAL_DMA_STATE_READY;
 800874a:	2201      	movs	r2, #1
  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
 800874c:	2300      	movs	r3, #0
  hdma->State = HAL_DMA_STATE_READY;
 800874e:	f880 2021 	strb.w	r2, [r0, #33]	; 0x21
  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
 8008752:	6383      	str	r3, [r0, #56]	; 0x38
  /* Allocate lock resource and initialize it */
  hdma->Lock = HAL_UNLOCKED;
 8008754:	f880 3020 	strb.w	r3, [r0, #32]

  return HAL_OK;
 8008758:	4618      	mov	r0, r3
 800875a:	bd10      	pop	{r4, pc}
    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
 800875c:	4b06      	ldr	r3, [pc, #24]	; (8008778 <HAL_DMA_Init+0x78>)
 800875e:	440b      	add	r3, r1
 8008760:	fbb3 f3f4 	udiv	r3, r3, r4
 8008764:	009b      	lsls	r3, r3, #2
 8008766:	6403      	str	r3, [r0, #64]	; 0x40
    hdma->DmaBaseAddress = DMA2;
 8008768:	4b04      	ldr	r3, [pc, #16]	; (800877c <HAL_DMA_Init+0x7c>)
 800876a:	e7d9      	b.n	8008720 <HAL_DMA_Init+0x20>
    return HAL_ERROR;
 800876c:	2001      	movs	r0, #1
}
 800876e:	bd10      	pop	{r4, pc}
 8008770:	40020407 	.word	0x40020407
 8008774:	bffdfff8 	.word	0xbffdfff8
 8008778:	bffdfbf8 	.word	0xbffdfbf8
 800877c:	40020400 	.word	0x40020400

08008780 <HAL_DMA_Start_IT>:
  * @param  DstAddress: The destination memory Buffer address
  * @param  DataLength: The length of data to be transferred from source to destination
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
 8008780:	b5f0      	push	{r4, r5, r6, r7, lr}

  /* Check the parameters */
  assert_param(IS_DMA_BUFFER_SIZE(DataLength));

  /* Process locked */
  __HAL_LOCK(hdma);
 8008782:	f890 4020 	ldrb.w	r4, [r0, #32]
 8008786:	2c01      	cmp	r4, #1
 8008788:	d035      	beq.n	80087f6 <HAL_DMA_Start_IT+0x76>
 800878a:	2401      	movs	r4, #1
  
  if(HAL_DMA_STATE_READY == hdma->State)
 800878c:	f890 5021 	ldrb.w	r5, [r0, #33]	; 0x21
  __HAL_LOCK(hdma);
 8008790:	f880 4020 	strb.w	r4, [r0, #32]
  if(HAL_DMA_STATE_READY == hdma->State)
 8008794:	42a5      	cmp	r5, r4
 8008796:	f04f 0600 	mov.w	r6, #0
 800879a:	f04f 0402 	mov.w	r4, #2
 800879e:	d128      	bne.n	80087f2 <HAL_DMA_Start_IT+0x72>
  {
    /* Change DMA peripheral state */
    hdma->State = HAL_DMA_STATE_BUSY;
 80087a0:	f880 4021 	strb.w	r4, [r0, #33]	; 0x21
    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
    
    /* Disable the peripheral */
    __HAL_DMA_DISABLE(hdma);
 80087a4:	6804      	ldr	r4, [r0, #0]
    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
 80087a6:	6386      	str	r6, [r0, #56]	; 0x38
    __HAL_DMA_DISABLE(hdma);
 80087a8:	6826      	ldr	r6, [r4, #0]
  * @retval HAL status
  */
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
  /* Clear all flags */
  hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
 80087aa:	6c07      	ldr	r7, [r0, #64]	; 0x40
    __HAL_DMA_DISABLE(hdma);
 80087ac:	f026 0601 	bic.w	r6, r6, #1
 80087b0:	6026      	str	r6, [r4, #0]
  hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
 80087b2:	6bc6      	ldr	r6, [r0, #60]	; 0x3c
 80087b4:	40bd      	lsls	r5, r7
 80087b6:	6075      	str	r5, [r6, #4]

  /* Configure DMA Channel data length */
  hdma->Instance->CNDTR = DataLength;
 80087b8:	6063      	str	r3, [r4, #4]

  /* Memory to Peripheral */
  if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
 80087ba:	6843      	ldr	r3, [r0, #4]
 80087bc:	6805      	ldr	r5, [r0, #0]
 80087be:	2b10      	cmp	r3, #16
    if(NULL != hdma->XferHalfCpltCallback)
 80087c0:	6ac3      	ldr	r3, [r0, #44]	; 0x2c
  {
    /* Configure DMA Channel destination address */
    hdma->Instance->CPAR = DstAddress;
 80087c2:	bf0b      	itete	eq
 80087c4:	60a2      	streq	r2, [r4, #8]
  }
  /* Peripheral to Memory */
  else
  {
    /* Configure DMA Channel source address */
    hdma->Instance->CPAR = SrcAddress;
 80087c6:	60a1      	strne	r1, [r4, #8]
    hdma->Instance->CMAR = SrcAddress;
 80087c8:	60e1      	streq	r1, [r4, #12]

    /* Configure DMA Channel destination address */
    hdma->Instance->CMAR = DstAddress;
 80087ca:	60e2      	strne	r2, [r4, #12]
    if(NULL != hdma->XferHalfCpltCallback)
 80087cc:	b14b      	cbz	r3, 80087e2 <HAL_DMA_Start_IT+0x62>
      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
 80087ce:	6823      	ldr	r3, [r4, #0]
 80087d0:	f043 030e 	orr.w	r3, r3, #14
      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
 80087d4:	6023      	str	r3, [r4, #0]
    __HAL_DMA_ENABLE(hdma);
 80087d6:	682b      	ldr	r3, [r5, #0]
  HAL_StatusTypeDef status = HAL_OK;
 80087d8:	2000      	movs	r0, #0
    __HAL_DMA_ENABLE(hdma);
 80087da:	f043 0301 	orr.w	r3, r3, #1
 80087de:	602b      	str	r3, [r5, #0]
 80087e0:	bdf0      	pop	{r4, r5, r6, r7, pc}
      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
 80087e2:	6823      	ldr	r3, [r4, #0]
 80087e4:	f023 0304 	bic.w	r3, r3, #4
 80087e8:	6023      	str	r3, [r4, #0]
      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
 80087ea:	6823      	ldr	r3, [r4, #0]
 80087ec:	f043 030a 	orr.w	r3, r3, #10
 80087f0:	e7f0      	b.n	80087d4 <HAL_DMA_Start_IT+0x54>
    __HAL_UNLOCK(hdma); 
 80087f2:	f880 6020 	strb.w	r6, [r0, #32]
  __HAL_LOCK(hdma);
 80087f6:	2002      	movs	r0, #2
}
 80087f8:	bdf0      	pop	{r4, r5, r6, r7, pc}
	...

080087fc <HAL_DMA_Abort_IT>:
  if(HAL_DMA_STATE_BUSY != hdma->State)
 80087fc:	f890 3021 	ldrb.w	r3, [r0, #33]	; 0x21
{  
 8008800:	b510      	push	{r4, lr}
  if(HAL_DMA_STATE_BUSY != hdma->State)
 8008802:	2b02      	cmp	r3, #2
 8008804:	d003      	beq.n	800880e <HAL_DMA_Abort_IT+0x12>
    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
 8008806:	2304      	movs	r3, #4
 8008808:	6383      	str	r3, [r0, #56]	; 0x38
    status = HAL_ERROR;
 800880a:	2001      	movs	r0, #1
 800880c:	bd10      	pop	{r4, pc}
    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
 800880e:	6803      	ldr	r3, [r0, #0]
 8008810:	681a      	ldr	r2, [r3, #0]
 8008812:	f022 020e 	bic.w	r2, r2, #14
 8008816:	601a      	str	r2, [r3, #0]
    __HAL_DMA_DISABLE(hdma);
 8008818:	681a      	ldr	r2, [r3, #0]
 800881a:	f022 0201 	bic.w	r2, r2, #1
 800881e:	601a      	str	r2, [r3, #0]
    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma));
 8008820:	4a29      	ldr	r2, [pc, #164]	; (80088c8 <HAL_DMA_Abort_IT+0xcc>)
 8008822:	4293      	cmp	r3, r2
 8008824:	d924      	bls.n	8008870 <HAL_DMA_Abort_IT+0x74>
 8008826:	f502 7262 	add.w	r2, r2, #904	; 0x388
 800882a:	4293      	cmp	r3, r2
 800882c:	d019      	beq.n	8008862 <HAL_DMA_Abort_IT+0x66>
 800882e:	3214      	adds	r2, #20
 8008830:	4293      	cmp	r3, r2
 8008832:	d018      	beq.n	8008866 <HAL_DMA_Abort_IT+0x6a>
 8008834:	3214      	adds	r2, #20
 8008836:	4293      	cmp	r3, r2
 8008838:	d017      	beq.n	800886a <HAL_DMA_Abort_IT+0x6e>
 800883a:	3214      	adds	r2, #20
 800883c:	4293      	cmp	r3, r2
 800883e:	bf0c      	ite	eq
 8008840:	f44f 5380 	moveq.w	r3, #4096	; 0x1000
 8008844:	f44f 3380 	movne.w	r3, #65536	; 0x10000
 8008848:	4a20      	ldr	r2, [pc, #128]	; (80088cc <HAL_DMA_Abort_IT+0xd0>)
 800884a:	6053      	str	r3, [r2, #4]
    hdma->State = HAL_DMA_STATE_READY;
 800884c:	2301      	movs	r3, #1
    __HAL_UNLOCK(hdma);
 800884e:	2400      	movs	r4, #0
    hdma->State = HAL_DMA_STATE_READY;
 8008850:	f880 3021 	strb.w	r3, [r0, #33]	; 0x21
    if(hdma->XferAbortCallback != NULL)
 8008854:	6b43      	ldr	r3, [r0, #52]	; 0x34
    __HAL_UNLOCK(hdma);
 8008856:	f880 4020 	strb.w	r4, [r0, #32]
    if(hdma->XferAbortCallback != NULL)
 800885a:	b39b      	cbz	r3, 80088c4 <HAL_DMA_Abort_IT+0xc8>
      hdma->XferAbortCallback(hdma);
 800885c:	4798      	blx	r3
  HAL_StatusTypeDef status = HAL_OK;
 800885e:	4620      	mov	r0, r4
 8008860:	bd10      	pop	{r4, pc}
    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma));
 8008862:	2301      	movs	r3, #1
 8008864:	e7f0      	b.n	8008848 <HAL_DMA_Abort_IT+0x4c>
 8008866:	2310      	movs	r3, #16
 8008868:	e7ee      	b.n	8008848 <HAL_DMA_Abort_IT+0x4c>
 800886a:	f44f 7380 	mov.w	r3, #256	; 0x100
 800886e:	e7eb      	b.n	8008848 <HAL_DMA_Abort_IT+0x4c>
 8008870:	4917      	ldr	r1, [pc, #92]	; (80088d0 <HAL_DMA_Abort_IT+0xd4>)
 8008872:	428b      	cmp	r3, r1
 8008874:	d016      	beq.n	80088a4 <HAL_DMA_Abort_IT+0xa8>
 8008876:	3114      	adds	r1, #20
 8008878:	428b      	cmp	r3, r1
 800887a:	d015      	beq.n	80088a8 <HAL_DMA_Abort_IT+0xac>
 800887c:	3114      	adds	r1, #20
 800887e:	428b      	cmp	r3, r1
 8008880:	d014      	beq.n	80088ac <HAL_DMA_Abort_IT+0xb0>
 8008882:	3114      	adds	r1, #20
 8008884:	428b      	cmp	r3, r1
 8008886:	d014      	beq.n	80088b2 <HAL_DMA_Abort_IT+0xb6>
 8008888:	3114      	adds	r1, #20
 800888a:	428b      	cmp	r3, r1
 800888c:	d014      	beq.n	80088b8 <HAL_DMA_Abort_IT+0xbc>
 800888e:	3114      	adds	r1, #20
 8008890:	428b      	cmp	r3, r1
 8008892:	d014      	beq.n	80088be <HAL_DMA_Abort_IT+0xc2>
 8008894:	4293      	cmp	r3, r2
 8008896:	bf14      	ite	ne
 8008898:	f44f 3380 	movne.w	r3, #65536	; 0x10000
 800889c:	f04f 7380 	moveq.w	r3, #16777216	; 0x1000000
 80088a0:	4a0c      	ldr	r2, [pc, #48]	; (80088d4 <HAL_DMA_Abort_IT+0xd8>)
 80088a2:	e7d2      	b.n	800884a <HAL_DMA_Abort_IT+0x4e>
 80088a4:	2301      	movs	r3, #1
 80088a6:	e7fb      	b.n	80088a0 <HAL_DMA_Abort_IT+0xa4>
 80088a8:	2310      	movs	r3, #16
 80088aa:	e7f9      	b.n	80088a0 <HAL_DMA_Abort_IT+0xa4>
 80088ac:	f44f 7380 	mov.w	r3, #256	; 0x100
 80088b0:	e7f6      	b.n	80088a0 <HAL_DMA_Abort_IT+0xa4>
 80088b2:	f44f 5380 	mov.w	r3, #4096	; 0x1000
 80088b6:	e7f3      	b.n	80088a0 <HAL_DMA_Abort_IT+0xa4>
 80088b8:	f44f 3380 	mov.w	r3, #65536	; 0x10000
 80088bc:	e7f0      	b.n	80088a0 <HAL_DMA_Abort_IT+0xa4>
 80088be:	f44f 1380 	mov.w	r3, #1048576	; 0x100000
 80088c2:	e7ed      	b.n	80088a0 <HAL_DMA_Abort_IT+0xa4>
  HAL_StatusTypeDef status = HAL_OK;
 80088c4:	4618      	mov	r0, r3
}
 80088c6:	bd10      	pop	{r4, pc}
 80088c8:	40020080 	.word	0x40020080
 80088cc:	40020400 	.word	0x40020400
 80088d0:	40020008 	.word	0x40020008
 80088d4:	40020000 	.word	0x40020000

080088d8 <HAL_DMA_IRQHandler>:
{
 80088d8:	b470      	push	{r4, r5, r6}
  if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET))
 80088da:	2504      	movs	r5, #4
  uint32_t flag_it = hdma->DmaBaseAddress->ISR;
 80088dc:	6bc6      	ldr	r6, [r0, #60]	; 0x3c
  if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET))
 80088de:	6c02      	ldr	r2, [r0, #64]	; 0x40
  uint32_t flag_it = hdma->DmaBaseAddress->ISR;
 80088e0:	6834      	ldr	r4, [r6, #0]
  uint32_t source_it = hdma->Instance->CCR;
 80088e2:	6803      	ldr	r3, [r0, #0]
  if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET))
 80088e4:	4095      	lsls	r5, r2
 80088e6:	4225      	tst	r5, r4
  uint32_t source_it = hdma->Instance->CCR;
 80088e8:	6819      	ldr	r1, [r3, #0]
  if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET))
 80088ea:	d055      	beq.n	8008998 <HAL_DMA_IRQHandler+0xc0>
 80088ec:	074d      	lsls	r5, r1, #29
 80088ee:	d553      	bpl.n	8008998 <HAL_DMA_IRQHandler+0xc0>
    if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
 80088f0:	681a      	ldr	r2, [r3, #0]
 80088f2:	0696      	lsls	r6, r2, #26
      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
 80088f4:	bf5e      	ittt	pl
 80088f6:	681a      	ldrpl	r2, [r3, #0]
 80088f8:	f022 0204 	bicpl.w	r2, r2, #4
 80088fc:	601a      	strpl	r2, [r3, #0]
    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
 80088fe:	4a60      	ldr	r2, [pc, #384]	; (8008a80 <HAL_DMA_IRQHandler+0x1a8>)
 8008900:	4293      	cmp	r3, r2
 8008902:	d91f      	bls.n	8008944 <HAL_DMA_IRQHandler+0x6c>
 8008904:	f502 7262 	add.w	r2, r2, #904	; 0x388
 8008908:	4293      	cmp	r3, r2
 800890a:	d014      	beq.n	8008936 <HAL_DMA_IRQHandler+0x5e>
 800890c:	3214      	adds	r2, #20
 800890e:	4293      	cmp	r3, r2
 8008910:	d013      	beq.n	800893a <HAL_DMA_IRQHandler+0x62>
 8008912:	3214      	adds	r2, #20
 8008914:	4293      	cmp	r3, r2
 8008916:	d012      	beq.n	800893e <HAL_DMA_IRQHandler+0x66>
 8008918:	3214      	adds	r2, #20
 800891a:	4293      	cmp	r3, r2
 800891c:	bf0c      	ite	eq
 800891e:	f44f 4380 	moveq.w	r3, #16384	; 0x4000
 8008922:	f44f 2380 	movne.w	r3, #262144	; 0x40000
 8008926:	4a57      	ldr	r2, [pc, #348]	; (8008a84 <HAL_DMA_IRQHandler+0x1ac>)
 8008928:	6053      	str	r3, [r2, #4]
    if(hdma->XferHalfCpltCallback != NULL)
 800892a:	6ac3      	ldr	r3, [r0, #44]	; 0x2c
    if (hdma->XferErrorCallback != NULL)
 800892c:	2b00      	cmp	r3, #0
 800892e:	f000 80a5 	beq.w	8008a7c <HAL_DMA_IRQHandler+0x1a4>
}
 8008932:	bc70      	pop	{r4, r5, r6}
      hdma->XferErrorCallback(hdma);
 8008934:	4718      	bx	r3
    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
 8008936:	2304      	movs	r3, #4
 8008938:	e7f5      	b.n	8008926 <HAL_DMA_IRQHandler+0x4e>
 800893a:	2340      	movs	r3, #64	; 0x40
 800893c:	e7f3      	b.n	8008926 <HAL_DMA_IRQHandler+0x4e>
 800893e:	f44f 6380 	mov.w	r3, #1024	; 0x400
 8008942:	e7f0      	b.n	8008926 <HAL_DMA_IRQHandler+0x4e>
 8008944:	4950      	ldr	r1, [pc, #320]	; (8008a88 <HAL_DMA_IRQHandler+0x1b0>)
 8008946:	428b      	cmp	r3, r1
 8008948:	d016      	beq.n	8008978 <HAL_DMA_IRQHandler+0xa0>
 800894a:	3114      	adds	r1, #20
 800894c:	428b      	cmp	r3, r1
 800894e:	d015      	beq.n	800897c <HAL_DMA_IRQHandler+0xa4>
 8008950:	3114      	adds	r1, #20
 8008952:	428b      	cmp	r3, r1
 8008954:	d014      	beq.n	8008980 <HAL_DMA_IRQHandler+0xa8>
 8008956:	3114      	adds	r1, #20
 8008958:	428b      	cmp	r3, r1
 800895a:	d014      	beq.n	8008986 <HAL_DMA_IRQHandler+0xae>
 800895c:	3114      	adds	r1, #20
 800895e:	428b      	cmp	r3, r1
 8008960:	d014      	beq.n	800898c <HAL_DMA_IRQHandler+0xb4>
 8008962:	3114      	adds	r1, #20
 8008964:	428b      	cmp	r3, r1
 8008966:	d014      	beq.n	8008992 <HAL_DMA_IRQHandler+0xba>
 8008968:	4293      	cmp	r3, r2
 800896a:	bf14      	ite	ne
 800896c:	f44f 2380 	movne.w	r3, #262144	; 0x40000
 8008970:	f04f 6380 	moveq.w	r3, #67108864	; 0x4000000
 8008974:	4a45      	ldr	r2, [pc, #276]	; (8008a8c <HAL_DMA_IRQHandler+0x1b4>)
 8008976:	e7d7      	b.n	8008928 <HAL_DMA_IRQHandler+0x50>
 8008978:	2304      	movs	r3, #4
 800897a:	e7fb      	b.n	8008974 <HAL_DMA_IRQHandler+0x9c>
 800897c:	2340      	movs	r3, #64	; 0x40
 800897e:	e7f9      	b.n	8008974 <HAL_DMA_IRQHandler+0x9c>
 8008980:	f44f 6380 	mov.w	r3, #1024	; 0x400
 8008984:	e7f6      	b.n	8008974 <HAL_DMA_IRQHandler+0x9c>
 8008986:	f44f 4380 	mov.w	r3, #16384	; 0x4000
 800898a:	e7f3      	b.n	8008974 <HAL_DMA_IRQHandler+0x9c>
 800898c:	f44f 2380 	mov.w	r3, #262144	; 0x40000
 8008990:	e7f0      	b.n	8008974 <HAL_DMA_IRQHandler+0x9c>
 8008992:	f44f 0380 	mov.w	r3, #4194304	; 0x400000
 8008996:	e7ed      	b.n	8008974 <HAL_DMA_IRQHandler+0x9c>
  else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET))
 8008998:	2502      	movs	r5, #2
 800899a:	4095      	lsls	r5, r2
 800899c:	4225      	tst	r5, r4
 800899e:	d057      	beq.n	8008a50 <HAL_DMA_IRQHandler+0x178>
 80089a0:	078d      	lsls	r5, r1, #30
 80089a2:	d555      	bpl.n	8008a50 <HAL_DMA_IRQHandler+0x178>
    if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
 80089a4:	681a      	ldr	r2, [r3, #0]
 80089a6:	0694      	lsls	r4, r2, #26
 80089a8:	d406      	bmi.n	80089b8 <HAL_DMA_IRQHandler+0xe0>
      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);  
 80089aa:	681a      	ldr	r2, [r3, #0]
 80089ac:	f022 020a 	bic.w	r2, r2, #10
 80089b0:	601a      	str	r2, [r3, #0]
      hdma->State = HAL_DMA_STATE_READY;
 80089b2:	2201      	movs	r2, #1
 80089b4:	f880 2021 	strb.w	r2, [r0, #33]	; 0x21
      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
 80089b8:	4a31      	ldr	r2, [pc, #196]	; (8008a80 <HAL_DMA_IRQHandler+0x1a8>)
 80089ba:	4293      	cmp	r3, r2
 80089bc:	d91e      	bls.n	80089fc <HAL_DMA_IRQHandler+0x124>
 80089be:	f502 7262 	add.w	r2, r2, #904	; 0x388
 80089c2:	4293      	cmp	r3, r2
 80089c4:	d013      	beq.n	80089ee <HAL_DMA_IRQHandler+0x116>
 80089c6:	3214      	adds	r2, #20
 80089c8:	4293      	cmp	r3, r2
 80089ca:	d012      	beq.n	80089f2 <HAL_DMA_IRQHandler+0x11a>
 80089cc:	3214      	adds	r2, #20
 80089ce:	4293      	cmp	r3, r2
 80089d0:	d011      	beq.n	80089f6 <HAL_DMA_IRQHandler+0x11e>
 80089d2:	3214      	adds	r2, #20
 80089d4:	4293      	cmp	r3, r2
 80089d6:	bf0c      	ite	eq
 80089d8:	f44f 5300 	moveq.w	r3, #8192	; 0x2000
 80089dc:	f44f 3300 	movne.w	r3, #131072	; 0x20000
 80089e0:	4a28      	ldr	r2, [pc, #160]	; (8008a84 <HAL_DMA_IRQHandler+0x1ac>)
 80089e2:	6053      	str	r3, [r2, #4]
    __HAL_UNLOCK(hdma);
 80089e4:	2300      	movs	r3, #0
 80089e6:	f880 3020 	strb.w	r3, [r0, #32]
    if(hdma->XferCpltCallback != NULL)
 80089ea:	6a83      	ldr	r3, [r0, #40]	; 0x28
 80089ec:	e79e      	b.n	800892c <HAL_DMA_IRQHandler+0x54>
      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
 80089ee:	2302      	movs	r3, #2
 80089f0:	e7f6      	b.n	80089e0 <HAL_DMA_IRQHandler+0x108>
 80089f2:	2320      	movs	r3, #32
 80089f4:	e7f4      	b.n	80089e0 <HAL_DMA_IRQHandler+0x108>
 80089f6:	f44f 7300 	mov.w	r3, #512	; 0x200
 80089fa:	e7f1      	b.n	80089e0 <HAL_DMA_IRQHandler+0x108>
 80089fc:	4922      	ldr	r1, [pc, #136]	; (8008a88 <HAL_DMA_IRQHandler+0x1b0>)
 80089fe:	428b      	cmp	r3, r1
 8008a00:	d016      	beq.n	8008a30 <HAL_DMA_IRQHandler+0x158>
 8008a02:	3114      	adds	r1, #20
 8008a04:	428b      	cmp	r3, r1
 8008a06:	d015      	beq.n	8008a34 <HAL_DMA_IRQHandler+0x15c>
 8008a08:	3114      	adds	r1, #20
 8008a0a:	428b      	cmp	r3, r1
 8008a0c:	d014      	beq.n	8008a38 <HAL_DMA_IRQHandler+0x160>
 8008a0e:	3114      	adds	r1, #20
 8008a10:	428b      	cmp	r3, r1
 8008a12:	d014      	beq.n	8008a3e <HAL_DMA_IRQHandler+0x166>
 8008a14:	3114      	adds	r1, #20
 8008a16:	428b      	cmp	r3, r1
 8008a18:	d014      	beq.n	8008a44 <HAL_DMA_IRQHandler+0x16c>
 8008a1a:	3114      	adds	r1, #20
 8008a1c:	428b      	cmp	r3, r1
 8008a1e:	d014      	beq.n	8008a4a <HAL_DMA_IRQHandler+0x172>
 8008a20:	4293      	cmp	r3, r2
 8008a22:	bf14      	ite	ne
 8008a24:	f44f 3300 	movne.w	r3, #131072	; 0x20000
 8008a28:	f04f 7300 	moveq.w	r3, #33554432	; 0x2000000
 8008a2c:	4a17      	ldr	r2, [pc, #92]	; (8008a8c <HAL_DMA_IRQHandler+0x1b4>)
 8008a2e:	e7d8      	b.n	80089e2 <HAL_DMA_IRQHandler+0x10a>
 8008a30:	2302      	movs	r3, #2
 8008a32:	e7fb      	b.n	8008a2c <HAL_DMA_IRQHandler+0x154>
 8008a34:	2320      	movs	r3, #32
 8008a36:	e7f9      	b.n	8008a2c <HAL_DMA_IRQHandler+0x154>
 8008a38:	f44f 7300 	mov.w	r3, #512	; 0x200
 8008a3c:	e7f6      	b.n	8008a2c <HAL_DMA_IRQHandler+0x154>
 8008a3e:	f44f 5300 	mov.w	r3, #8192	; 0x2000
 8008a42:	e7f3      	b.n	8008a2c <HAL_DMA_IRQHandler+0x154>
 8008a44:	f44f 3300 	mov.w	r3, #131072	; 0x20000
 8008a48:	e7f0      	b.n	8008a2c <HAL_DMA_IRQHandler+0x154>
 8008a4a:	f44f 1300 	mov.w	r3, #2097152	; 0x200000
 8008a4e:	e7ed      	b.n	8008a2c <HAL_DMA_IRQHandler+0x154>
  else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
 8008a50:	2508      	movs	r5, #8
 8008a52:	4095      	lsls	r5, r2
 8008a54:	4225      	tst	r5, r4
 8008a56:	d011      	beq.n	8008a7c <HAL_DMA_IRQHandler+0x1a4>
 8008a58:	0709      	lsls	r1, r1, #28
 8008a5a:	d50f      	bpl.n	8008a7c <HAL_DMA_IRQHandler+0x1a4>
    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
 8008a5c:	6819      	ldr	r1, [r3, #0]
 8008a5e:	f021 010e 	bic.w	r1, r1, #14
 8008a62:	6019      	str	r1, [r3, #0]
    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
 8008a64:	2301      	movs	r3, #1
 8008a66:	fa03 f202 	lsl.w	r2, r3, r2
 8008a6a:	6072      	str	r2, [r6, #4]
    hdma->ErrorCode = HAL_DMA_ERROR_TE;
 8008a6c:	6383      	str	r3, [r0, #56]	; 0x38
    hdma->State = HAL_DMA_STATE_READY;
 8008a6e:	f880 3021 	strb.w	r3, [r0, #33]	; 0x21
    __HAL_UNLOCK(hdma);
 8008a72:	2300      	movs	r3, #0
 8008a74:	f880 3020 	strb.w	r3, [r0, #32]
    if (hdma->XferErrorCallback != NULL)
 8008a78:	6b03      	ldr	r3, [r0, #48]	; 0x30
 8008a7a:	e757      	b.n	800892c <HAL_DMA_IRQHandler+0x54>
}
 8008a7c:	bc70      	pop	{r4, r5, r6}
 8008a7e:	4770      	bx	lr
 8008a80:	40020080 	.word	0x40020080
 8008a84:	40020400 	.word	0x40020400
 8008a88:	40020008 	.word	0x40020008
 8008a8c:	40020000 	.word	0x40020000

08008a90 <HAL_GPIO_Init>:
  * @param  GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
  *         the configuration information for the specified GPIO peripheral.
  * @retval None
  */
void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
 8008a90:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
  uint32_t position = 0x00u;
  uint32_t ioposition;
  uint32_t iocurrent;
  uint32_t temp;
  uint32_t config = 0x00u;
 8008a94:	2400      	movs	r4, #0
  uint32_t position = 0x00u;
 8008a96:	4626      	mov	r6, r4
      /*--------------------- EXTI Mode Configuration ------------------------*/
      /* Configure the External Interrupt or event for the current IO */
      if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
      {
        /* Enable AFIO Clock */
        __HAL_RCC_AFIO_CLK_ENABLE();
 8008a98:	4f6c      	ldr	r7, [pc, #432]	; (8008c4c <HAL_GPIO_Init+0x1bc>)
 8008a9a:	4b6d      	ldr	r3, [pc, #436]	; (8008c50 <HAL_GPIO_Init+0x1c0>)
        temp = AFIO->EXTICR[position >> 2u];
        CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u)));
        SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u)));
 8008a9c:	f8df e1b8 	ldr.w	lr, [pc, #440]	; 8008c58 <HAL_GPIO_Init+0x1c8>
      switch (GPIO_Init->Mode)
 8008aa0:	f8df c1b8 	ldr.w	ip, [pc, #440]	; 8008c5c <HAL_GPIO_Init+0x1cc>
  while (((GPIO_Init->Pin) >> position) != 0x00u)
 8008aa4:	680a      	ldr	r2, [r1, #0]
 8008aa6:	fa32 f506 	lsrs.w	r5, r2, r6
 8008aaa:	d102      	bne.n	8008ab2 <HAL_GPIO_Init+0x22>
      }
    }

	position++;
  }
}
 8008aac:	b003      	add	sp, #12
 8008aae:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    ioposition = (0x01uL << position);
 8008ab2:	f04f 0801 	mov.w	r8, #1
 8008ab6:	fa08 f806 	lsl.w	r8, r8, r6
    iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
 8008aba:	ea02 0208 	and.w	r2, r2, r8
    if (iocurrent == ioposition)
 8008abe:	4590      	cmp	r8, r2
 8008ac0:	f040 8084 	bne.w	8008bcc <HAL_GPIO_Init+0x13c>
      switch (GPIO_Init->Mode)
 8008ac4:	684d      	ldr	r5, [r1, #4]
 8008ac6:	2d12      	cmp	r5, #18
 8008ac8:	f000 80b1 	beq.w	8008c2e <HAL_GPIO_Init+0x19e>
 8008acc:	f200 8087 	bhi.w	8008bde <HAL_GPIO_Init+0x14e>
 8008ad0:	2d02      	cmp	r5, #2
 8008ad2:	f000 80a9 	beq.w	8008c28 <HAL_GPIO_Init+0x198>
 8008ad6:	d87b      	bhi.n	8008bd0 <HAL_GPIO_Init+0x140>
 8008ad8:	2d00      	cmp	r5, #0
 8008ada:	f000 808c 	beq.w	8008bf6 <HAL_GPIO_Init+0x166>
 8008ade:	2d01      	cmp	r5, #1
 8008ae0:	f000 80a0 	beq.w	8008c24 <HAL_GPIO_Init+0x194>
      MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
 8008ae4:	f04f 090f 	mov.w	r9, #15
      configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL     : &GPIOx->CRH;
 8008ae8:	2aff      	cmp	r2, #255	; 0xff
 8008aea:	bf93      	iteet	ls
 8008aec:	4682      	movls	sl, r0
 8008aee:	f106 4580 	addhi.w	r5, r6, #1073741824	; 0x40000000
 8008af2:	3d08      	subhi	r5, #8
 8008af4:	f8d0 b000 	ldrls.w	fp, [r0]
 8008af8:	bf92      	itee	ls
 8008afa:	00b5      	lslls	r5, r6, #2
 8008afc:	f8d0 b004 	ldrhi.w	fp, [r0, #4]
 8008b00:	00ad      	lslhi	r5, r5, #2
      MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
 8008b02:	fa09 f805 	lsl.w	r8, r9, r5
 8008b06:	ea2b 0808 	bic.w	r8, fp, r8
 8008b0a:	fa04 f505 	lsl.w	r5, r4, r5
      configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL     : &GPIOx->CRH;
 8008b0e:	bf88      	it	hi
 8008b10:	f100 0a04 	addhi.w	sl, r0, #4
      MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
 8008b14:	ea48 0505 	orr.w	r5, r8, r5
 8008b18:	f8ca 5000 	str.w	r5, [sl]
      if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
 8008b1c:	f8d1 a004 	ldr.w	sl, [r1, #4]
 8008b20:	f01a 5f80 	tst.w	sl, #268435456	; 0x10000000
 8008b24:	d052      	beq.n	8008bcc <HAL_GPIO_Init+0x13c>
        __HAL_RCC_AFIO_CLK_ENABLE();
 8008b26:	69bd      	ldr	r5, [r7, #24]
 8008b28:	f026 0803 	bic.w	r8, r6, #3
 8008b2c:	f045 0501 	orr.w	r5, r5, #1
 8008b30:	61bd      	str	r5, [r7, #24]
 8008b32:	69bd      	ldr	r5, [r7, #24]
 8008b34:	f108 4880 	add.w	r8, r8, #1073741824	; 0x40000000
 8008b38:	f005 0501 	and.w	r5, r5, #1
 8008b3c:	9501      	str	r5, [sp, #4]
 8008b3e:	f508 3880 	add.w	r8, r8, #65536	; 0x10000
        CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u)));
 8008b42:	f006 0b03 	and.w	fp, r6, #3
        __HAL_RCC_AFIO_CLK_ENABLE();
 8008b46:	9d01      	ldr	r5, [sp, #4]
        CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u)));
 8008b48:	ea4f 0b8b 	mov.w	fp, fp, lsl #2
        temp = AFIO->EXTICR[position >> 2u];
 8008b4c:	f8d8 5008 	ldr.w	r5, [r8, #8]
        CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u)));
 8008b50:	fa09 f90b 	lsl.w	r9, r9, fp
 8008b54:	ea25 0909 	bic.w	r9, r5, r9
        SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u)));
 8008b58:	4d3e      	ldr	r5, [pc, #248]	; (8008c54 <HAL_GPIO_Init+0x1c4>)
 8008b5a:	42a8      	cmp	r0, r5
 8008b5c:	d06c      	beq.n	8008c38 <HAL_GPIO_Init+0x1a8>
 8008b5e:	f505 6580 	add.w	r5, r5, #1024	; 0x400
 8008b62:	42a8      	cmp	r0, r5
 8008b64:	d06a      	beq.n	8008c3c <HAL_GPIO_Init+0x1ac>
 8008b66:	f505 6580 	add.w	r5, r5, #1024	; 0x400
 8008b6a:	42a8      	cmp	r0, r5
 8008b6c:	d068      	beq.n	8008c40 <HAL_GPIO_Init+0x1b0>
 8008b6e:	f505 6580 	add.w	r5, r5, #1024	; 0x400
 8008b72:	42a8      	cmp	r0, r5
 8008b74:	d066      	beq.n	8008c44 <HAL_GPIO_Init+0x1b4>
 8008b76:	f505 6580 	add.w	r5, r5, #1024	; 0x400
 8008b7a:	42a8      	cmp	r0, r5
 8008b7c:	d064      	beq.n	8008c48 <HAL_GPIO_Init+0x1b8>
 8008b7e:	4570      	cmp	r0, lr
 8008b80:	bf0c      	ite	eq
 8008b82:	2505      	moveq	r5, #5
 8008b84:	2506      	movne	r5, #6
 8008b86:	fa05 f50b 	lsl.w	r5, r5, fp
 8008b8a:	ea45 0509 	orr.w	r5, r5, r9
        AFIO->EXTICR[position >> 2u] = temp;
 8008b8e:	f8c8 5008 	str.w	r5, [r8, #8]
          SET_BIT(EXTI->IMR, iocurrent);
 8008b92:	681d      	ldr	r5, [r3, #0]
        if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
 8008b94:	f41a 3f80 	tst.w	sl, #65536	; 0x10000
          SET_BIT(EXTI->IMR, iocurrent);
 8008b98:	bf14      	ite	ne
 8008b9a:	4315      	orrne	r5, r2
          CLEAR_BIT(EXTI->IMR, iocurrent);
 8008b9c:	4395      	biceq	r5, r2
 8008b9e:	601d      	str	r5, [r3, #0]
          SET_BIT(EXTI->EMR, iocurrent);
 8008ba0:	685d      	ldr	r5, [r3, #4]
        if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
 8008ba2:	f41a 3f00 	tst.w	sl, #131072	; 0x20000
          SET_BIT(EXTI->EMR, iocurrent);
 8008ba6:	bf14      	ite	ne
 8008ba8:	4315      	orrne	r5, r2
          CLEAR_BIT(EXTI->EMR, iocurrent);
 8008baa:	4395      	biceq	r5, r2
 8008bac:	605d      	str	r5, [r3, #4]
          SET_BIT(EXTI->RTSR, iocurrent);
 8008bae:	689d      	ldr	r5, [r3, #8]
        if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
 8008bb0:	f41a 1f80 	tst.w	sl, #1048576	; 0x100000
          SET_BIT(EXTI->RTSR, iocurrent);
 8008bb4:	bf14      	ite	ne
 8008bb6:	4315      	orrne	r5, r2
          CLEAR_BIT(EXTI->RTSR, iocurrent);
 8008bb8:	4395      	biceq	r5, r2
 8008bba:	609d      	str	r5, [r3, #8]
          SET_BIT(EXTI->FTSR, iocurrent);
 8008bbc:	68dd      	ldr	r5, [r3, #12]
        if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
 8008bbe:	f41a 1f00 	tst.w	sl, #2097152	; 0x200000
          SET_BIT(EXTI->FTSR, iocurrent);
 8008bc2:	bf14      	ite	ne
 8008bc4:	432a      	orrne	r2, r5
          CLEAR_BIT(EXTI->FTSR, iocurrent);
 8008bc6:	ea25 0202 	biceq.w	r2, r5, r2
 8008bca:	60da      	str	r2, [r3, #12]
	position++;
 8008bcc:	3601      	adds	r6, #1
 8008bce:	e769      	b.n	8008aa4 <HAL_GPIO_Init+0x14>
      switch (GPIO_Init->Mode)
 8008bd0:	2d03      	cmp	r5, #3
 8008bd2:	d025      	beq.n	8008c20 <HAL_GPIO_Init+0x190>
 8008bd4:	2d11      	cmp	r5, #17
 8008bd6:	d185      	bne.n	8008ae4 <HAL_GPIO_Init+0x54>
          config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;
 8008bd8:	68cc      	ldr	r4, [r1, #12]
 8008bda:	3404      	adds	r4, #4
          break;
 8008bdc:	e782      	b.n	8008ae4 <HAL_GPIO_Init+0x54>
      switch (GPIO_Init->Mode)
 8008bde:	4565      	cmp	r5, ip
 8008be0:	d009      	beq.n	8008bf6 <HAL_GPIO_Init+0x166>
 8008be2:	d812      	bhi.n	8008c0a <HAL_GPIO_Init+0x17a>
 8008be4:	f8df 9078 	ldr.w	r9, [pc, #120]	; 8008c60 <HAL_GPIO_Init+0x1d0>
 8008be8:	454d      	cmp	r5, r9
 8008bea:	d004      	beq.n	8008bf6 <HAL_GPIO_Init+0x166>
 8008bec:	f509 3980 	add.w	r9, r9, #65536	; 0x10000
 8008bf0:	454d      	cmp	r5, r9
 8008bf2:	f47f af77 	bne.w	8008ae4 <HAL_GPIO_Init+0x54>
          if (GPIO_Init->Pull == GPIO_NOPULL)
 8008bf6:	688c      	ldr	r4, [r1, #8]
 8008bf8:	b1e4      	cbz	r4, 8008c34 <HAL_GPIO_Init+0x1a4>
          else if (GPIO_Init->Pull == GPIO_PULLUP)
 8008bfa:	2c01      	cmp	r4, #1
            GPIOx->BSRR = ioposition;
 8008bfc:	bf0c      	ite	eq
 8008bfe:	f8c0 8010 	streq.w	r8, [r0, #16]
            GPIOx->BRR = ioposition;
 8008c02:	f8c0 8014 	strne.w	r8, [r0, #20]
            config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
 8008c06:	2408      	movs	r4, #8
 8008c08:	e76c      	b.n	8008ae4 <HAL_GPIO_Init+0x54>
      switch (GPIO_Init->Mode)
 8008c0a:	f8df 9058 	ldr.w	r9, [pc, #88]	; 8008c64 <HAL_GPIO_Init+0x1d4>
 8008c0e:	454d      	cmp	r5, r9
 8008c10:	d0f1      	beq.n	8008bf6 <HAL_GPIO_Init+0x166>
 8008c12:	f509 3980 	add.w	r9, r9, #65536	; 0x10000
 8008c16:	454d      	cmp	r5, r9
 8008c18:	d0ed      	beq.n	8008bf6 <HAL_GPIO_Init+0x166>
 8008c1a:	f5a9 1980 	sub.w	r9, r9, #1048576	; 0x100000
 8008c1e:	e7e7      	b.n	8008bf0 <HAL_GPIO_Init+0x160>
          config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
 8008c20:	2400      	movs	r4, #0
 8008c22:	e75f      	b.n	8008ae4 <HAL_GPIO_Init+0x54>
          config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;
 8008c24:	68cc      	ldr	r4, [r1, #12]
          break;
 8008c26:	e75d      	b.n	8008ae4 <HAL_GPIO_Init+0x54>
          config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;
 8008c28:	68cc      	ldr	r4, [r1, #12]
 8008c2a:	3408      	adds	r4, #8
          break;
 8008c2c:	e75a      	b.n	8008ae4 <HAL_GPIO_Init+0x54>
          config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;
 8008c2e:	68cc      	ldr	r4, [r1, #12]
 8008c30:	340c      	adds	r4, #12
          break;
 8008c32:	e757      	b.n	8008ae4 <HAL_GPIO_Init+0x54>
            config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
 8008c34:	2404      	movs	r4, #4
 8008c36:	e755      	b.n	8008ae4 <HAL_GPIO_Init+0x54>
        SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u)));
 8008c38:	2500      	movs	r5, #0
 8008c3a:	e7a4      	b.n	8008b86 <HAL_GPIO_Init+0xf6>
 8008c3c:	2501      	movs	r5, #1
 8008c3e:	e7a2      	b.n	8008b86 <HAL_GPIO_Init+0xf6>
 8008c40:	2502      	movs	r5, #2
 8008c42:	e7a0      	b.n	8008b86 <HAL_GPIO_Init+0xf6>
 8008c44:	2503      	movs	r5, #3
 8008c46:	e79e      	b.n	8008b86 <HAL_GPIO_Init+0xf6>
 8008c48:	2504      	movs	r5, #4
 8008c4a:	e79c      	b.n	8008b86 <HAL_GPIO_Init+0xf6>
 8008c4c:	40021000 	.word	0x40021000
 8008c50:	40010400 	.word	0x40010400
 8008c54:	40010800 	.word	0x40010800
 8008c58:	40011c00 	.word	0x40011c00
 8008c5c:	10210000 	.word	0x10210000
 8008c60:	10110000 	.word	0x10110000
 8008c64:	10310000 	.word	0x10310000

08008c68 <HAL_GPIO_WritePin>:
{
  /* Check the parameters */
  assert_param(IS_GPIO_PIN(GPIO_Pin));
  assert_param(IS_GPIO_PIN_ACTION(PinState));

  if (PinState != GPIO_PIN_RESET)
 8008c68:	b10a      	cbz	r2, 8008c6e <HAL_GPIO_WritePin+0x6>
  {
    GPIOx->BSRR = GPIO_Pin;
  }
  else
  {
    GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u;
 8008c6a:	6101      	str	r1, [r0, #16]
 8008c6c:	4770      	bx	lr
 8008c6e:	0409      	lsls	r1, r1, #16
 8008c70:	e7fb      	b.n	8008c6a <HAL_GPIO_WritePin+0x2>

08008c72 <HAL_GPIO_TogglePin>:
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
  /* Check the parameters */
  assert_param(IS_GPIO_PIN(GPIO_Pin));

  if ((GPIOx->ODR & GPIO_Pin) != 0x00u)
 8008c72:	68c3      	ldr	r3, [r0, #12]
 8008c74:	420b      	tst	r3, r1
  {
    GPIOx->BRR = (uint32_t)GPIO_Pin;
 8008c76:	bf14      	ite	ne
 8008c78:	6141      	strne	r1, [r0, #20]
  }
  else
  {
    GPIOx->BSRR = (uint32_t)GPIO_Pin;
 8008c7a:	6101      	streq	r1, [r0, #16]
 8008c7c:	4770      	bx	lr
	...

08008c80 <HAL_RCC_OscConfig>:
  *         supported by this macro. User should request a transition to HSE Off
  *         first and then HSE On or HSE Bypass.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
{
 8008c80:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
  uint32_t tickstart;
  uint32_t pll_config;

  /* Check Null pointer */
  if (RCC_OscInitStruct == NULL)
 8008c84:	4605      	mov	r5, r0
 8008c86:	b908      	cbnz	r0, 8008c8c <HAL_RCC_OscConfig+0xc>
    else
    {
      /* Check if there is a request to disable the PLL used as System clock source */
      if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
      {
        return HAL_ERROR;
 8008c88:	2001      	movs	r0, #1
 8008c8a:	e03c      	b.n	8008d06 <HAL_RCC_OscConfig+0x86>
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
 8008c8c:	6803      	ldr	r3, [r0, #0]
 8008c8e:	07db      	lsls	r3, r3, #31
 8008c90:	d410      	bmi.n	8008cb4 <HAL_RCC_OscConfig+0x34>
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
 8008c92:	682b      	ldr	r3, [r5, #0]
 8008c94:	079f      	lsls	r7, r3, #30
 8008c96:	d45d      	bmi.n	8008d54 <HAL_RCC_OscConfig+0xd4>
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
 8008c98:	682b      	ldr	r3, [r5, #0]
 8008c9a:	0719      	lsls	r1, r3, #28
 8008c9c:	f100 8094 	bmi.w	8008dc8 <HAL_RCC_OscConfig+0x148>
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
 8008ca0:	682b      	ldr	r3, [r5, #0]
 8008ca2:	075a      	lsls	r2, r3, #29
 8008ca4:	f100 80be 	bmi.w	8008e24 <HAL_RCC_OscConfig+0x1a4>
  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
 8008ca8:	69e8      	ldr	r0, [r5, #28]
 8008caa:	2800      	cmp	r0, #0
 8008cac:	f040 812c 	bne.w	8008f08 <HAL_RCC_OscConfig+0x288>
        }
      }
    }
  }

  return HAL_OK;
 8008cb0:	2000      	movs	r0, #0
 8008cb2:	e028      	b.n	8008d06 <HAL_RCC_OscConfig+0x86>
    if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
 8008cb4:	4c8f      	ldr	r4, [pc, #572]	; (8008ef4 <HAL_RCC_OscConfig+0x274>)
 8008cb6:	6863      	ldr	r3, [r4, #4]
 8008cb8:	f003 030c 	and.w	r3, r3, #12
 8008cbc:	2b04      	cmp	r3, #4
 8008cbe:	d007      	beq.n	8008cd0 <HAL_RCC_OscConfig+0x50>
        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
 8008cc0:	6863      	ldr	r3, [r4, #4]
 8008cc2:	f003 030c 	and.w	r3, r3, #12
 8008cc6:	2b08      	cmp	r3, #8
 8008cc8:	d109      	bne.n	8008cde <HAL_RCC_OscConfig+0x5e>
 8008cca:	6863      	ldr	r3, [r4, #4]
 8008ccc:	03de      	lsls	r6, r3, #15
 8008cce:	d506      	bpl.n	8008cde <HAL_RCC_OscConfig+0x5e>
      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
 8008cd0:	6823      	ldr	r3, [r4, #0]
 8008cd2:	039c      	lsls	r4, r3, #14
 8008cd4:	d5dd      	bpl.n	8008c92 <HAL_RCC_OscConfig+0x12>
 8008cd6:	686b      	ldr	r3, [r5, #4]
 8008cd8:	2b00      	cmp	r3, #0
 8008cda:	d1da      	bne.n	8008c92 <HAL_RCC_OscConfig+0x12>
 8008cdc:	e7d4      	b.n	8008c88 <HAL_RCC_OscConfig+0x8>
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 8008cde:	686b      	ldr	r3, [r5, #4]
 8008ce0:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
 8008ce4:	d112      	bne.n	8008d0c <HAL_RCC_OscConfig+0x8c>
 8008ce6:	6823      	ldr	r3, [r4, #0]
 8008ce8:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
 8008cec:	6023      	str	r3, [r4, #0]
        tickstart = HAL_GetTick();
 8008cee:	f7ff fadb 	bl	80082a8 <HAL_GetTick>
 8008cf2:	4606      	mov	r6, r0
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 8008cf4:	6823      	ldr	r3, [r4, #0]
 8008cf6:	0398      	lsls	r0, r3, #14
 8008cf8:	d4cb      	bmi.n	8008c92 <HAL_RCC_OscConfig+0x12>
          if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
 8008cfa:	f7ff fad5 	bl	80082a8 <HAL_GetTick>
 8008cfe:	1b80      	subs	r0, r0, r6
 8008d00:	2864      	cmp	r0, #100	; 0x64
 8008d02:	d9f7      	bls.n	8008cf4 <HAL_RCC_OscConfig+0x74>
            return HAL_TIMEOUT;
 8008d04:	2003      	movs	r0, #3
}
 8008d06:	b002      	add	sp, #8
 8008d08:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 8008d0c:	b99b      	cbnz	r3, 8008d36 <HAL_RCC_OscConfig+0xb6>
 8008d0e:	6823      	ldr	r3, [r4, #0]
 8008d10:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
 8008d14:	6023      	str	r3, [r4, #0]
 8008d16:	6823      	ldr	r3, [r4, #0]
 8008d18:	f423 2380 	bic.w	r3, r3, #262144	; 0x40000
 8008d1c:	6023      	str	r3, [r4, #0]
        tickstart = HAL_GetTick();
 8008d1e:	f7ff fac3 	bl	80082a8 <HAL_GetTick>
 8008d22:	4606      	mov	r6, r0
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
 8008d24:	6823      	ldr	r3, [r4, #0]
 8008d26:	0399      	lsls	r1, r3, #14
 8008d28:	d5b3      	bpl.n	8008c92 <HAL_RCC_OscConfig+0x12>
          if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
 8008d2a:	f7ff fabd 	bl	80082a8 <HAL_GetTick>
 8008d2e:	1b80      	subs	r0, r0, r6
 8008d30:	2864      	cmp	r0, #100	; 0x64
 8008d32:	d9f7      	bls.n	8008d24 <HAL_RCC_OscConfig+0xa4>
 8008d34:	e7e6      	b.n	8008d04 <HAL_RCC_OscConfig+0x84>
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 8008d36:	f5b3 2fa0 	cmp.w	r3, #327680	; 0x50000
 8008d3a:	6823      	ldr	r3, [r4, #0]
 8008d3c:	d103      	bne.n	8008d46 <HAL_RCC_OscConfig+0xc6>
 8008d3e:	f443 2380 	orr.w	r3, r3, #262144	; 0x40000
 8008d42:	6023      	str	r3, [r4, #0]
 8008d44:	e7cf      	b.n	8008ce6 <HAL_RCC_OscConfig+0x66>
 8008d46:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
 8008d4a:	6023      	str	r3, [r4, #0]
 8008d4c:	6823      	ldr	r3, [r4, #0]
 8008d4e:	f423 2380 	bic.w	r3, r3, #262144	; 0x40000
 8008d52:	e7cb      	b.n	8008cec <HAL_RCC_OscConfig+0x6c>
    if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
 8008d54:	4c67      	ldr	r4, [pc, #412]	; (8008ef4 <HAL_RCC_OscConfig+0x274>)
 8008d56:	6863      	ldr	r3, [r4, #4]
 8008d58:	f013 0f0c 	tst.w	r3, #12
 8008d5c:	d007      	beq.n	8008d6e <HAL_RCC_OscConfig+0xee>
        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
 8008d5e:	6863      	ldr	r3, [r4, #4]
 8008d60:	f003 030c 	and.w	r3, r3, #12
 8008d64:	2b08      	cmp	r3, #8
 8008d66:	d110      	bne.n	8008d8a <HAL_RCC_OscConfig+0x10a>
 8008d68:	6863      	ldr	r3, [r4, #4]
 8008d6a:	03da      	lsls	r2, r3, #15
 8008d6c:	d40d      	bmi.n	8008d8a <HAL_RCC_OscConfig+0x10a>
      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
 8008d6e:	6823      	ldr	r3, [r4, #0]
 8008d70:	079b      	lsls	r3, r3, #30
 8008d72:	d502      	bpl.n	8008d7a <HAL_RCC_OscConfig+0xfa>
 8008d74:	692b      	ldr	r3, [r5, #16]
 8008d76:	2b01      	cmp	r3, #1
 8008d78:	d186      	bne.n	8008c88 <HAL_RCC_OscConfig+0x8>
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 8008d7a:	6823      	ldr	r3, [r4, #0]
 8008d7c:	696a      	ldr	r2, [r5, #20]
 8008d7e:	f023 03f8 	bic.w	r3, r3, #248	; 0xf8
 8008d82:	ea43 03c2 	orr.w	r3, r3, r2, lsl #3
 8008d86:	6023      	str	r3, [r4, #0]
 8008d88:	e786      	b.n	8008c98 <HAL_RCC_OscConfig+0x18>
      if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
 8008d8a:	692a      	ldr	r2, [r5, #16]
 8008d8c:	4b5a      	ldr	r3, [pc, #360]	; (8008ef8 <HAL_RCC_OscConfig+0x278>)
 8008d8e:	b16a      	cbz	r2, 8008dac <HAL_RCC_OscConfig+0x12c>
        __HAL_RCC_HSI_ENABLE();
 8008d90:	2201      	movs	r2, #1
 8008d92:	601a      	str	r2, [r3, #0]
        tickstart = HAL_GetTick();
 8008d94:	f7ff fa88 	bl	80082a8 <HAL_GetTick>
 8008d98:	4606      	mov	r6, r0
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 8008d9a:	6823      	ldr	r3, [r4, #0]
 8008d9c:	079f      	lsls	r7, r3, #30
 8008d9e:	d4ec      	bmi.n	8008d7a <HAL_RCC_OscConfig+0xfa>
          if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
 8008da0:	f7ff fa82 	bl	80082a8 <HAL_GetTick>
 8008da4:	1b80      	subs	r0, r0, r6
 8008da6:	2802      	cmp	r0, #2
 8008da8:	d9f7      	bls.n	8008d9a <HAL_RCC_OscConfig+0x11a>
 8008daa:	e7ab      	b.n	8008d04 <HAL_RCC_OscConfig+0x84>
        __HAL_RCC_HSI_DISABLE();
 8008dac:	601a      	str	r2, [r3, #0]
        tickstart = HAL_GetTick();
 8008dae:	f7ff fa7b 	bl	80082a8 <HAL_GetTick>
 8008db2:	4606      	mov	r6, r0
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
 8008db4:	6823      	ldr	r3, [r4, #0]
 8008db6:	0798      	lsls	r0, r3, #30
 8008db8:	f57f af6e 	bpl.w	8008c98 <HAL_RCC_OscConfig+0x18>
          if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
 8008dbc:	f7ff fa74 	bl	80082a8 <HAL_GetTick>
 8008dc0:	1b80      	subs	r0, r0, r6
 8008dc2:	2802      	cmp	r0, #2
 8008dc4:	d9f6      	bls.n	8008db4 <HAL_RCC_OscConfig+0x134>
 8008dc6:	e79d      	b.n	8008d04 <HAL_RCC_OscConfig+0x84>
    if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
 8008dc8:	69aa      	ldr	r2, [r5, #24]
 8008dca:	4c4a      	ldr	r4, [pc, #296]	; (8008ef4 <HAL_RCC_OscConfig+0x274>)
 8008dcc:	4b4b      	ldr	r3, [pc, #300]	; (8008efc <HAL_RCC_OscConfig+0x27c>)
 8008dce:	b1da      	cbz	r2, 8008e08 <HAL_RCC_OscConfig+0x188>
      __HAL_RCC_LSI_ENABLE();
 8008dd0:	2201      	movs	r2, #1
 8008dd2:	601a      	str	r2, [r3, #0]
      tickstart = HAL_GetTick();
 8008dd4:	f7ff fa68 	bl	80082a8 <HAL_GetTick>
 8008dd8:	4606      	mov	r6, r0
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
 8008dda:	6a63      	ldr	r3, [r4, #36]	; 0x24
 8008ddc:	079b      	lsls	r3, r3, #30
 8008dde:	d50d      	bpl.n	8008dfc <HAL_RCC_OscConfig+0x17c>
  * @param  mdelay: specifies the delay time length, in milliseconds.
  * @retval None
  */
static void RCC_Delay(uint32_t mdelay)
{
  __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
 8008de0:	f44f 52fa 	mov.w	r2, #8000	; 0x1f40
 8008de4:	4b46      	ldr	r3, [pc, #280]	; (8008f00 <HAL_RCC_OscConfig+0x280>)
 8008de6:	681b      	ldr	r3, [r3, #0]
 8008de8:	fbb3 f3f2 	udiv	r3, r3, r2
 8008dec:	9301      	str	r3, [sp, #4]
  do
  {
    __NOP();
 8008dee:	bf00      	nop
  }
  while (Delay --);
 8008df0:	9b01      	ldr	r3, [sp, #4]
 8008df2:	1e5a      	subs	r2, r3, #1
 8008df4:	9201      	str	r2, [sp, #4]
 8008df6:	2b00      	cmp	r3, #0
 8008df8:	d1f9      	bne.n	8008dee <HAL_RCC_OscConfig+0x16e>
 8008dfa:	e751      	b.n	8008ca0 <HAL_RCC_OscConfig+0x20>
        if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
 8008dfc:	f7ff fa54 	bl	80082a8 <HAL_GetTick>
 8008e00:	1b80      	subs	r0, r0, r6
 8008e02:	2802      	cmp	r0, #2
 8008e04:	d9e9      	bls.n	8008dda <HAL_RCC_OscConfig+0x15a>
 8008e06:	e77d      	b.n	8008d04 <HAL_RCC_OscConfig+0x84>
      __HAL_RCC_LSI_DISABLE();
 8008e08:	601a      	str	r2, [r3, #0]
      tickstart = HAL_GetTick();
 8008e0a:	f7ff fa4d 	bl	80082a8 <HAL_GetTick>
 8008e0e:	4606      	mov	r6, r0
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
 8008e10:	6a63      	ldr	r3, [r4, #36]	; 0x24
 8008e12:	079f      	lsls	r7, r3, #30
 8008e14:	f57f af44 	bpl.w	8008ca0 <HAL_RCC_OscConfig+0x20>
        if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
 8008e18:	f7ff fa46 	bl	80082a8 <HAL_GetTick>
 8008e1c:	1b80      	subs	r0, r0, r6
 8008e1e:	2802      	cmp	r0, #2
 8008e20:	d9f6      	bls.n	8008e10 <HAL_RCC_OscConfig+0x190>
 8008e22:	e76f      	b.n	8008d04 <HAL_RCC_OscConfig+0x84>
    if (__HAL_RCC_PWR_IS_CLK_DISABLED())
 8008e24:	4c33      	ldr	r4, [pc, #204]	; (8008ef4 <HAL_RCC_OscConfig+0x274>)
 8008e26:	69e3      	ldr	r3, [r4, #28]
 8008e28:	00d8      	lsls	r0, r3, #3
 8008e2a:	d424      	bmi.n	8008e76 <HAL_RCC_OscConfig+0x1f6>
      pwrclkchanged = SET;
 8008e2c:	2701      	movs	r7, #1
      __HAL_RCC_PWR_CLK_ENABLE();
 8008e2e:	69e3      	ldr	r3, [r4, #28]
 8008e30:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
 8008e34:	61e3      	str	r3, [r4, #28]
 8008e36:	69e3      	ldr	r3, [r4, #28]
 8008e38:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8008e3c:	9300      	str	r3, [sp, #0]
 8008e3e:	9b00      	ldr	r3, [sp, #0]
    if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 8008e40:	4e30      	ldr	r6, [pc, #192]	; (8008f04 <HAL_RCC_OscConfig+0x284>)
 8008e42:	6833      	ldr	r3, [r6, #0]
 8008e44:	05d9      	lsls	r1, r3, #23
 8008e46:	d518      	bpl.n	8008e7a <HAL_RCC_OscConfig+0x1fa>
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 8008e48:	68eb      	ldr	r3, [r5, #12]
 8008e4a:	2b01      	cmp	r3, #1
 8008e4c:	d126      	bne.n	8008e9c <HAL_RCC_OscConfig+0x21c>
 8008e4e:	6a23      	ldr	r3, [r4, #32]
 8008e50:	f043 0301 	orr.w	r3, r3, #1
 8008e54:	6223      	str	r3, [r4, #32]
      tickstart = HAL_GetTick();
 8008e56:	f7ff fa27 	bl	80082a8 <HAL_GetTick>
        if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 8008e5a:	f241 3688 	movw	r6, #5000	; 0x1388
      tickstart = HAL_GetTick();
 8008e5e:	4680      	mov	r8, r0
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
 8008e60:	6a23      	ldr	r3, [r4, #32]
 8008e62:	079b      	lsls	r3, r3, #30
 8008e64:	d53f      	bpl.n	8008ee6 <HAL_RCC_OscConfig+0x266>
    if (pwrclkchanged == SET)
 8008e66:	2f00      	cmp	r7, #0
 8008e68:	f43f af1e 	beq.w	8008ca8 <HAL_RCC_OscConfig+0x28>
      __HAL_RCC_PWR_CLK_DISABLE();
 8008e6c:	69e3      	ldr	r3, [r4, #28]
 8008e6e:	f023 5380 	bic.w	r3, r3, #268435456	; 0x10000000
 8008e72:	61e3      	str	r3, [r4, #28]
 8008e74:	e718      	b.n	8008ca8 <HAL_RCC_OscConfig+0x28>
    FlagStatus       pwrclkchanged = RESET;
 8008e76:	2700      	movs	r7, #0
 8008e78:	e7e2      	b.n	8008e40 <HAL_RCC_OscConfig+0x1c0>
      SET_BIT(PWR->CR, PWR_CR_DBP);
 8008e7a:	6833      	ldr	r3, [r6, #0]
 8008e7c:	f443 7380 	orr.w	r3, r3, #256	; 0x100
 8008e80:	6033      	str	r3, [r6, #0]
      tickstart = HAL_GetTick();
 8008e82:	f7ff fa11 	bl	80082a8 <HAL_GetTick>
 8008e86:	4680      	mov	r8, r0
      while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 8008e88:	6833      	ldr	r3, [r6, #0]
 8008e8a:	05da      	lsls	r2, r3, #23
 8008e8c:	d4dc      	bmi.n	8008e48 <HAL_RCC_OscConfig+0x1c8>
        if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
 8008e8e:	f7ff fa0b 	bl	80082a8 <HAL_GetTick>
 8008e92:	eba0 0008 	sub.w	r0, r0, r8
 8008e96:	2864      	cmp	r0, #100	; 0x64
 8008e98:	d9f6      	bls.n	8008e88 <HAL_RCC_OscConfig+0x208>
 8008e9a:	e733      	b.n	8008d04 <HAL_RCC_OscConfig+0x84>
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 8008e9c:	b9ab      	cbnz	r3, 8008eca <HAL_RCC_OscConfig+0x24a>
 8008e9e:	6a23      	ldr	r3, [r4, #32]
        if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 8008ea0:	f241 3888 	movw	r8, #5000	; 0x1388
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 8008ea4:	f023 0301 	bic.w	r3, r3, #1
 8008ea8:	6223      	str	r3, [r4, #32]
 8008eaa:	6a23      	ldr	r3, [r4, #32]
 8008eac:	f023 0304 	bic.w	r3, r3, #4
 8008eb0:	6223      	str	r3, [r4, #32]
      tickstart = HAL_GetTick();
 8008eb2:	f7ff f9f9 	bl	80082a8 <HAL_GetTick>
 8008eb6:	4606      	mov	r6, r0
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
 8008eb8:	6a23      	ldr	r3, [r4, #32]
 8008eba:	0798      	lsls	r0, r3, #30
 8008ebc:	d5d3      	bpl.n	8008e66 <HAL_RCC_OscConfig+0x1e6>
        if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 8008ebe:	f7ff f9f3 	bl	80082a8 <HAL_GetTick>
 8008ec2:	1b80      	subs	r0, r0, r6
 8008ec4:	4540      	cmp	r0, r8
 8008ec6:	d9f7      	bls.n	8008eb8 <HAL_RCC_OscConfig+0x238>
 8008ec8:	e71c      	b.n	8008d04 <HAL_RCC_OscConfig+0x84>
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 8008eca:	2b05      	cmp	r3, #5
 8008ecc:	6a23      	ldr	r3, [r4, #32]
 8008ece:	d103      	bne.n	8008ed8 <HAL_RCC_OscConfig+0x258>
 8008ed0:	f043 0304 	orr.w	r3, r3, #4
 8008ed4:	6223      	str	r3, [r4, #32]
 8008ed6:	e7ba      	b.n	8008e4e <HAL_RCC_OscConfig+0x1ce>
 8008ed8:	f023 0301 	bic.w	r3, r3, #1
 8008edc:	6223      	str	r3, [r4, #32]
 8008ede:	6a23      	ldr	r3, [r4, #32]
 8008ee0:	f023 0304 	bic.w	r3, r3, #4
 8008ee4:	e7b6      	b.n	8008e54 <HAL_RCC_OscConfig+0x1d4>
        if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 8008ee6:	f7ff f9df 	bl	80082a8 <HAL_GetTick>
 8008eea:	eba0 0008 	sub.w	r0, r0, r8
 8008eee:	42b0      	cmp	r0, r6
 8008ef0:	d9b6      	bls.n	8008e60 <HAL_RCC_OscConfig+0x1e0>
 8008ef2:	e707      	b.n	8008d04 <HAL_RCC_OscConfig+0x84>
 8008ef4:	40021000 	.word	0x40021000
 8008ef8:	42420000 	.word	0x42420000
 8008efc:	42420480 	.word	0x42420480
 8008f00:	20000208 	.word	0x20000208
 8008f04:	40007000 	.word	0x40007000
    if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
 8008f08:	4b2a      	ldr	r3, [pc, #168]	; (8008fb4 <HAL_RCC_OscConfig+0x334>)
 8008f0a:	685a      	ldr	r2, [r3, #4]
 8008f0c:	461c      	mov	r4, r3
 8008f0e:	f002 020c 	and.w	r2, r2, #12
 8008f12:	2a08      	cmp	r2, #8
 8008f14:	d03d      	beq.n	8008f92 <HAL_RCC_OscConfig+0x312>
 8008f16:	2300      	movs	r3, #0
 8008f18:	4e27      	ldr	r6, [pc, #156]	; (8008fb8 <HAL_RCC_OscConfig+0x338>)
      if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
 8008f1a:	2802      	cmp	r0, #2
        __HAL_RCC_PLL_DISABLE();
 8008f1c:	6033      	str	r3, [r6, #0]
      if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
 8008f1e:	d12b      	bne.n	8008f78 <HAL_RCC_OscConfig+0x2f8>
        tickstart = HAL_GetTick();
 8008f20:	f7ff f9c2 	bl	80082a8 <HAL_GetTick>
 8008f24:	4607      	mov	r7, r0
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
 8008f26:	6823      	ldr	r3, [r4, #0]
 8008f28:	0199      	lsls	r1, r3, #6
 8008f2a:	d41f      	bmi.n	8008f6c <HAL_RCC_OscConfig+0x2ec>
        if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
 8008f2c:	6a2b      	ldr	r3, [r5, #32]
 8008f2e:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
 8008f32:	d105      	bne.n	8008f40 <HAL_RCC_OscConfig+0x2c0>
          __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
 8008f34:	6862      	ldr	r2, [r4, #4]
 8008f36:	68a9      	ldr	r1, [r5, #8]
 8008f38:	f422 3200 	bic.w	r2, r2, #131072	; 0x20000
 8008f3c:	430a      	orrs	r2, r1
 8008f3e:	6062      	str	r2, [r4, #4]
        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
 8008f40:	6a69      	ldr	r1, [r5, #36]	; 0x24
 8008f42:	6862      	ldr	r2, [r4, #4]
 8008f44:	430b      	orrs	r3, r1
 8008f46:	f422 1274 	bic.w	r2, r2, #3997696	; 0x3d0000
 8008f4a:	4313      	orrs	r3, r2
 8008f4c:	6063      	str	r3, [r4, #4]
        __HAL_RCC_PLL_ENABLE();
 8008f4e:	2301      	movs	r3, #1
 8008f50:	6033      	str	r3, [r6, #0]
        tickstart = HAL_GetTick();
 8008f52:	f7ff f9a9 	bl	80082a8 <HAL_GetTick>
 8008f56:	4605      	mov	r5, r0
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  == RESET)
 8008f58:	6823      	ldr	r3, [r4, #0]
 8008f5a:	019a      	lsls	r2, r3, #6
 8008f5c:	f53f aea8 	bmi.w	8008cb0 <HAL_RCC_OscConfig+0x30>
          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
 8008f60:	f7ff f9a2 	bl	80082a8 <HAL_GetTick>
 8008f64:	1b40      	subs	r0, r0, r5
 8008f66:	2802      	cmp	r0, #2
 8008f68:	d9f6      	bls.n	8008f58 <HAL_RCC_OscConfig+0x2d8>
 8008f6a:	e6cb      	b.n	8008d04 <HAL_RCC_OscConfig+0x84>
          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
 8008f6c:	f7ff f99c 	bl	80082a8 <HAL_GetTick>
 8008f70:	1bc0      	subs	r0, r0, r7
 8008f72:	2802      	cmp	r0, #2
 8008f74:	d9d7      	bls.n	8008f26 <HAL_RCC_OscConfig+0x2a6>
 8008f76:	e6c5      	b.n	8008d04 <HAL_RCC_OscConfig+0x84>
        tickstart = HAL_GetTick();
 8008f78:	f7ff f996 	bl	80082a8 <HAL_GetTick>
 8008f7c:	4605      	mov	r5, r0
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
 8008f7e:	6823      	ldr	r3, [r4, #0]
 8008f80:	019b      	lsls	r3, r3, #6
 8008f82:	f57f ae95 	bpl.w	8008cb0 <HAL_RCC_OscConfig+0x30>
          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
 8008f86:	f7ff f98f 	bl	80082a8 <HAL_GetTick>
 8008f8a:	1b40      	subs	r0, r0, r5
 8008f8c:	2802      	cmp	r0, #2
 8008f8e:	d9f6      	bls.n	8008f7e <HAL_RCC_OscConfig+0x2fe>
 8008f90:	e6b8      	b.n	8008d04 <HAL_RCC_OscConfig+0x84>
      if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
 8008f92:	2801      	cmp	r0, #1
 8008f94:	f43f aeb7 	beq.w	8008d06 <HAL_RCC_OscConfig+0x86>
        pll_config = RCC->CFGR;
 8008f98:	6858      	ldr	r0, [r3, #4]
        if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
 8008f9a:	6a2b      	ldr	r3, [r5, #32]
 8008f9c:	f400 3280 	and.w	r2, r0, #65536	; 0x10000
 8008fa0:	429a      	cmp	r2, r3
 8008fa2:	f47f ae71 	bne.w	8008c88 <HAL_RCC_OscConfig+0x8>
 8008fa6:	6a6b      	ldr	r3, [r5, #36]	; 0x24
            (READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL))
 8008fa8:	f400 1070 	and.w	r0, r0, #3932160	; 0x3c0000
    return HAL_ERROR;
 8008fac:	1ac0      	subs	r0, r0, r3
 8008fae:	bf18      	it	ne
 8008fb0:	2001      	movne	r0, #1
 8008fb2:	e6a8      	b.n	8008d06 <HAL_RCC_OscConfig+0x86>
 8008fb4:	40021000 	.word	0x40021000
 8008fb8:	42420060 	.word	0x42420060

08008fbc <HAL_RCC_GetSysClockFreq>:
{
 8008fbc:	b530      	push	{r4, r5, lr}
  const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
 8008fbe:	4b19      	ldr	r3, [pc, #100]	; (8009024 <HAL_RCC_GetSysClockFreq+0x68>)
{
 8008fc0:	b087      	sub	sp, #28
  const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
 8008fc2:	ac02      	add	r4, sp, #8
 8008fc4:	f103 0510 	add.w	r5, r3, #16
 8008fc8:	4622      	mov	r2, r4
 8008fca:	6818      	ldr	r0, [r3, #0]
 8008fcc:	6859      	ldr	r1, [r3, #4]
 8008fce:	3308      	adds	r3, #8
 8008fd0:	c203      	stmia	r2!, {r0, r1}
 8008fd2:	42ab      	cmp	r3, r5
 8008fd4:	4614      	mov	r4, r2
 8008fd6:	d1f7      	bne.n	8008fc8 <HAL_RCC_GetSysClockFreq+0xc>
  const uint8_t aPredivFactorTable[2] = {1, 2};
 8008fd8:	2301      	movs	r3, #1
 8008fda:	f88d 3004 	strb.w	r3, [sp, #4]
 8008fde:	2302      	movs	r3, #2
  tmpreg = RCC->CFGR;
 8008fe0:	4911      	ldr	r1, [pc, #68]	; (8009028 <HAL_RCC_GetSysClockFreq+0x6c>)
  const uint8_t aPredivFactorTable[2] = {1, 2};
 8008fe2:	f88d 3005 	strb.w	r3, [sp, #5]
  tmpreg = RCC->CFGR;
 8008fe6:	684b      	ldr	r3, [r1, #4]
  switch (tmpreg & RCC_CFGR_SWS)
 8008fe8:	f003 020c 	and.w	r2, r3, #12
 8008fec:	2a08      	cmp	r2, #8
 8008fee:	d117      	bne.n	8009020 <HAL_RCC_GetSysClockFreq+0x64>
      pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
 8008ff0:	f3c3 4283 	ubfx	r2, r3, #18, #4
 8008ff4:	a806      	add	r0, sp, #24
 8008ff6:	4402      	add	r2, r0
      if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
 8008ff8:	03db      	lsls	r3, r3, #15
      pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
 8008ffa:	f812 2c10 	ldrb.w	r2, [r2, #-16]
      if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
 8008ffe:	d50c      	bpl.n	800901a <HAL_RCC_GetSysClockFreq+0x5e>
        prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
 8009000:	684b      	ldr	r3, [r1, #4]
        pllclk = (uint32_t)((HSE_VALUE  * pllmul) / prediv);
 8009002:	480a      	ldr	r0, [pc, #40]	; (800902c <HAL_RCC_GetSysClockFreq+0x70>)
        prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
 8009004:	f3c3 4340 	ubfx	r3, r3, #17, #1
        pllclk = (uint32_t)((HSE_VALUE  * pllmul) / prediv);
 8009008:	4350      	muls	r0, r2
        prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
 800900a:	aa06      	add	r2, sp, #24
 800900c:	4413      	add	r3, r2
 800900e:	f813 3c14 	ldrb.w	r3, [r3, #-20]
        pllclk = (uint32_t)((HSE_VALUE  * pllmul) / prediv);
 8009012:	fbb0 f0f3 	udiv	r0, r0, r3
}
 8009016:	b007      	add	sp, #28
 8009018:	bd30      	pop	{r4, r5, pc}
        pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
 800901a:	4805      	ldr	r0, [pc, #20]	; (8009030 <HAL_RCC_GetSysClockFreq+0x74>)
 800901c:	4350      	muls	r0, r2
 800901e:	e7fa      	b.n	8009016 <HAL_RCC_GetSysClockFreq+0x5a>
      sysclockfreq = HSE_VALUE;
 8009020:	4802      	ldr	r0, [pc, #8]	; (800902c <HAL_RCC_GetSysClockFreq+0x70>)
  return sysclockfreq;
 8009022:	e7f8      	b.n	8009016 <HAL_RCC_GetSysClockFreq+0x5a>
 8009024:	0800b5f4 	.word	0x0800b5f4
 8009028:	40021000 	.word	0x40021000
 800902c:	007a1200 	.word	0x007a1200
 8009030:	003d0900 	.word	0x003d0900

08009034 <HAL_RCC_ClockConfig>:
{
 8009034:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
 8009038:	460d      	mov	r5, r1
  if (RCC_ClkInitStruct == NULL)
 800903a:	4604      	mov	r4, r0
 800903c:	b910      	cbnz	r0, 8009044 <HAL_RCC_ClockConfig+0x10>
    return HAL_ERROR;
 800903e:	2001      	movs	r0, #1
 8009040:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
  if (FLatency > __HAL_FLASH_GET_LATENCY())
 8009044:	4a45      	ldr	r2, [pc, #276]	; (800915c <HAL_RCC_ClockConfig+0x128>)
 8009046:	6813      	ldr	r3, [r2, #0]
 8009048:	f003 0307 	and.w	r3, r3, #7
 800904c:	428b      	cmp	r3, r1
 800904e:	d329      	bcc.n	80090a4 <HAL_RCC_ClockConfig+0x70>
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
 8009050:	6821      	ldr	r1, [r4, #0]
 8009052:	078e      	lsls	r6, r1, #30
 8009054:	d431      	bmi.n	80090ba <HAL_RCC_ClockConfig+0x86>
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
 8009056:	07ca      	lsls	r2, r1, #31
 8009058:	d444      	bmi.n	80090e4 <HAL_RCC_ClockConfig+0xb0>
  if (FLatency < __HAL_FLASH_GET_LATENCY())
 800905a:	4a40      	ldr	r2, [pc, #256]	; (800915c <HAL_RCC_ClockConfig+0x128>)
 800905c:	6813      	ldr	r3, [r2, #0]
 800905e:	f003 0307 	and.w	r3, r3, #7
 8009062:	429d      	cmp	r5, r3
 8009064:	d367      	bcc.n	8009136 <HAL_RCC_ClockConfig+0x102>
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 8009066:	6822      	ldr	r2, [r4, #0]
 8009068:	4d3d      	ldr	r5, [pc, #244]	; (8009160 <HAL_RCC_ClockConfig+0x12c>)
 800906a:	f012 0f04 	tst.w	r2, #4
 800906e:	d16e      	bne.n	800914e <HAL_RCC_ClockConfig+0x11a>
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
 8009070:	0713      	lsls	r3, r2, #28
 8009072:	d506      	bpl.n	8009082 <HAL_RCC_ClockConfig+0x4e>
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
 8009074:	686b      	ldr	r3, [r5, #4]
 8009076:	6922      	ldr	r2, [r4, #16]
 8009078:	f423 5360 	bic.w	r3, r3, #14336	; 0x3800
 800907c:	ea43 03c2 	orr.w	r3, r3, r2, lsl #3
 8009080:	606b      	str	r3, [r5, #4]
  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
 8009082:	f7ff ff9b 	bl	8008fbc <HAL_RCC_GetSysClockFreq>
 8009086:	686b      	ldr	r3, [r5, #4]
 8009088:	4a36      	ldr	r2, [pc, #216]	; (8009164 <HAL_RCC_ClockConfig+0x130>)
 800908a:	f3c3 1303 	ubfx	r3, r3, #4, #4
 800908e:	5cd3      	ldrb	r3, [r2, r3]
 8009090:	40d8      	lsrs	r0, r3
 8009092:	4b35      	ldr	r3, [pc, #212]	; (8009168 <HAL_RCC_ClockConfig+0x134>)
 8009094:	6018      	str	r0, [r3, #0]
  HAL_InitTick(uwTickPrio);
 8009096:	4b35      	ldr	r3, [pc, #212]	; (800916c <HAL_RCC_ClockConfig+0x138>)
 8009098:	6818      	ldr	r0, [r3, #0]
 800909a:	f7ff f8c3 	bl	8008224 <HAL_InitTick>
  return HAL_OK;
 800909e:	2000      	movs	r0, #0
 80090a0:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    __HAL_FLASH_SET_LATENCY(FLatency);
 80090a4:	6813      	ldr	r3, [r2, #0]
 80090a6:	f023 0307 	bic.w	r3, r3, #7
 80090aa:	430b      	orrs	r3, r1
 80090ac:	6013      	str	r3, [r2, #0]
    if (__HAL_FLASH_GET_LATENCY() != FLatency)
 80090ae:	6813      	ldr	r3, [r2, #0]
 80090b0:	f003 0307 	and.w	r3, r3, #7
 80090b4:	4299      	cmp	r1, r3
 80090b6:	d1c2      	bne.n	800903e <HAL_RCC_ClockConfig+0xa>
 80090b8:	e7ca      	b.n	8009050 <HAL_RCC_ClockConfig+0x1c>
 80090ba:	4b29      	ldr	r3, [pc, #164]	; (8009160 <HAL_RCC_ClockConfig+0x12c>)
    if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 80090bc:	f011 0f04 	tst.w	r1, #4
      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
 80090c0:	bf1e      	ittt	ne
 80090c2:	685a      	ldrne	r2, [r3, #4]
 80090c4:	f442 62e0 	orrne.w	r2, r2, #1792	; 0x700
 80090c8:	605a      	strne	r2, [r3, #4]
    if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
 80090ca:	0708      	lsls	r0, r1, #28
      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
 80090cc:	bf42      	ittt	mi
 80090ce:	685a      	ldrmi	r2, [r3, #4]
 80090d0:	f442 5260 	orrmi.w	r2, r2, #14336	; 0x3800
 80090d4:	605a      	strmi	r2, [r3, #4]
    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
 80090d6:	685a      	ldr	r2, [r3, #4]
 80090d8:	68a0      	ldr	r0, [r4, #8]
 80090da:	f022 02f0 	bic.w	r2, r2, #240	; 0xf0
 80090de:	4302      	orrs	r2, r0
 80090e0:	605a      	str	r2, [r3, #4]
 80090e2:	e7b8      	b.n	8009056 <HAL_RCC_ClockConfig+0x22>
    if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 80090e4:	6862      	ldr	r2, [r4, #4]
 80090e6:	4e1e      	ldr	r6, [pc, #120]	; (8009160 <HAL_RCC_ClockConfig+0x12c>)
 80090e8:	2a01      	cmp	r2, #1
      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 80090ea:	6833      	ldr	r3, [r6, #0]
    if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 80090ec:	d11b      	bne.n	8009126 <HAL_RCC_ClockConfig+0xf2>
      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 80090ee:	f413 3f00 	tst.w	r3, #131072	; 0x20000
      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 80090f2:	d0a4      	beq.n	800903e <HAL_RCC_ClockConfig+0xa>
    __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
 80090f4:	6873      	ldr	r3, [r6, #4]
      if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
 80090f6:	f241 3888 	movw	r8, #5000	; 0x1388
    __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
 80090fa:	f023 0303 	bic.w	r3, r3, #3
 80090fe:	4313      	orrs	r3, r2
 8009100:	6073      	str	r3, [r6, #4]
    tickstart = HAL_GetTick();
 8009102:	f7ff f8d1 	bl	80082a8 <HAL_GetTick>
 8009106:	4607      	mov	r7, r0
    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
 8009108:	6873      	ldr	r3, [r6, #4]
 800910a:	6862      	ldr	r2, [r4, #4]
 800910c:	f003 030c 	and.w	r3, r3, #12
 8009110:	ebb3 0f82 	cmp.w	r3, r2, lsl #2
 8009114:	d0a1      	beq.n	800905a <HAL_RCC_ClockConfig+0x26>
      if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
 8009116:	f7ff f8c7 	bl	80082a8 <HAL_GetTick>
 800911a:	1bc0      	subs	r0, r0, r7
 800911c:	4540      	cmp	r0, r8
 800911e:	d9f3      	bls.n	8009108 <HAL_RCC_ClockConfig+0xd4>
        return HAL_TIMEOUT;
 8009120:	2003      	movs	r0, #3
}
 8009122:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
 8009126:	2a02      	cmp	r2, #2
 8009128:	d102      	bne.n	8009130 <HAL_RCC_ClockConfig+0xfc>
      if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
 800912a:	f013 7f00 	tst.w	r3, #33554432	; 0x2000000
 800912e:	e7e0      	b.n	80090f2 <HAL_RCC_ClockConfig+0xbe>
      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 8009130:	f013 0f02 	tst.w	r3, #2
 8009134:	e7dd      	b.n	80090f2 <HAL_RCC_ClockConfig+0xbe>
    __HAL_FLASH_SET_LATENCY(FLatency);
 8009136:	6813      	ldr	r3, [r2, #0]
 8009138:	f023 0307 	bic.w	r3, r3, #7
 800913c:	432b      	orrs	r3, r5
 800913e:	6013      	str	r3, [r2, #0]
    if (__HAL_FLASH_GET_LATENCY() != FLatency)
 8009140:	6813      	ldr	r3, [r2, #0]
 8009142:	f003 0307 	and.w	r3, r3, #7
 8009146:	429d      	cmp	r5, r3
 8009148:	f47f af79 	bne.w	800903e <HAL_RCC_ClockConfig+0xa>
 800914c:	e78b      	b.n	8009066 <HAL_RCC_ClockConfig+0x32>
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
 800914e:	686b      	ldr	r3, [r5, #4]
 8009150:	68e1      	ldr	r1, [r4, #12]
 8009152:	f423 63e0 	bic.w	r3, r3, #1792	; 0x700
 8009156:	430b      	orrs	r3, r1
 8009158:	606b      	str	r3, [r5, #4]
 800915a:	e789      	b.n	8009070 <HAL_RCC_ClockConfig+0x3c>
 800915c:	40022000 	.word	0x40022000
 8009160:	40021000 	.word	0x40021000
 8009164:	0800b694 	.word	0x0800b694
 8009168:	20000208 	.word	0x20000208
 800916c:	20000004 	.word	0x20000004

08009170 <HAL_RCC_GetPCLK1Freq>:
  return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
 8009170:	4b04      	ldr	r3, [pc, #16]	; (8009184 <HAL_RCC_GetPCLK1Freq+0x14>)
 8009172:	4a05      	ldr	r2, [pc, #20]	; (8009188 <HAL_RCC_GetPCLK1Freq+0x18>)
 8009174:	685b      	ldr	r3, [r3, #4]
 8009176:	f3c3 2302 	ubfx	r3, r3, #8, #3
 800917a:	5cd3      	ldrb	r3, [r2, r3]
 800917c:	4a03      	ldr	r2, [pc, #12]	; (800918c <HAL_RCC_GetPCLK1Freq+0x1c>)
 800917e:	6810      	ldr	r0, [r2, #0]
}
 8009180:	40d8      	lsrs	r0, r3
 8009182:	4770      	bx	lr
 8009184:	40021000 	.word	0x40021000
 8009188:	0800b6a4 	.word	0x0800b6a4
 800918c:	20000208 	.word	0x20000208

08009190 <HAL_RCC_GetPCLK2Freq>:
  return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
 8009190:	4b04      	ldr	r3, [pc, #16]	; (80091a4 <HAL_RCC_GetPCLK2Freq+0x14>)
 8009192:	4a05      	ldr	r2, [pc, #20]	; (80091a8 <HAL_RCC_GetPCLK2Freq+0x18>)
 8009194:	685b      	ldr	r3, [r3, #4]
 8009196:	f3c3 23c2 	ubfx	r3, r3, #11, #3
 800919a:	5cd3      	ldrb	r3, [r2, r3]
 800919c:	4a03      	ldr	r2, [pc, #12]	; (80091ac <HAL_RCC_GetPCLK2Freq+0x1c>)
 800919e:	6810      	ldr	r0, [r2, #0]
}
 80091a0:	40d8      	lsrs	r0, r3
 80091a2:	4770      	bx	lr
 80091a4:	40021000 	.word	0x40021000
 80091a8:	0800b6a4 	.word	0x0800b6a4
 80091ac:	20000208 	.word	0x20000208

080091b0 <HAL_RCCEx_PeriphCLKConfig>:

  /* Check the parameters */
  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));

  /*------------------------------- RTC/LCD Configuration ------------------------*/
  if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
 80091b0:	6803      	ldr	r3, [r0, #0]
{
 80091b2:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
  if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
 80091b6:	07d9      	lsls	r1, r3, #31
{
 80091b8:	4605      	mov	r5, r0
  if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
 80091ba:	d520      	bpl.n	80091fe <HAL_RCCEx_PeriphCLKConfig+0x4e>
    FlagStatus       pwrclkchanged = RESET;

    /* As soon as function is called to change RTC clock source, activation of the
       power domain is done. */
    /* Requires to enable write access to Backup Domain of necessary */
    if (__HAL_RCC_PWR_IS_CLK_DISABLED())
 80091bc:	4c35      	ldr	r4, [pc, #212]	; (8009294 <HAL_RCCEx_PeriphCLKConfig+0xe4>)
 80091be:	69e3      	ldr	r3, [r4, #28]
 80091c0:	00da      	lsls	r2, r3, #3
 80091c2:	d432      	bmi.n	800922a <HAL_RCCEx_PeriphCLKConfig+0x7a>
    {
      __HAL_RCC_PWR_CLK_ENABLE();
      pwrclkchanged = SET;
 80091c4:	2701      	movs	r7, #1
      __HAL_RCC_PWR_CLK_ENABLE();
 80091c6:	69e3      	ldr	r3, [r4, #28]
 80091c8:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
 80091cc:	61e3      	str	r3, [r4, #28]
 80091ce:	69e3      	ldr	r3, [r4, #28]
 80091d0:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 80091d4:	9301      	str	r3, [sp, #4]
 80091d6:	9b01      	ldr	r3, [sp, #4]
    }

    if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 80091d8:	4e2f      	ldr	r6, [pc, #188]	; (8009298 <HAL_RCCEx_PeriphCLKConfig+0xe8>)
 80091da:	6833      	ldr	r3, [r6, #0]
 80091dc:	05db      	lsls	r3, r3, #23
 80091de:	d526      	bpl.n	800922e <HAL_RCCEx_PeriphCLKConfig+0x7e>
        }
      }
    }

    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
    temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
 80091e0:	6a23      	ldr	r3, [r4, #32]
    if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
 80091e2:	f413 7340 	ands.w	r3, r3, #768	; 0x300
 80091e6:	d136      	bne.n	8009256 <HAL_RCCEx_PeriphCLKConfig+0xa6>
            return HAL_TIMEOUT;
          }
        }
      }
    }
    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
 80091e8:	6a23      	ldr	r3, [r4, #32]
 80091ea:	686a      	ldr	r2, [r5, #4]
 80091ec:	f423 7340 	bic.w	r3, r3, #768	; 0x300
 80091f0:	4313      	orrs	r3, r2
 80091f2:	6223      	str	r3, [r4, #32]

    /* Require to disable power clock if necessary */
    if (pwrclkchanged == SET)
 80091f4:	b11f      	cbz	r7, 80091fe <HAL_RCCEx_PeriphCLKConfig+0x4e>
    {
      __HAL_RCC_PWR_CLK_DISABLE();
 80091f6:	69e3      	ldr	r3, [r4, #28]
 80091f8:	f023 5380 	bic.w	r3, r3, #268435456	; 0x10000000
 80091fc:	61e3      	str	r3, [r4, #28]
    }
  }

  /*------------------------------ ADC clock Configuration ------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
 80091fe:	6828      	ldr	r0, [r5, #0]
 8009200:	0783      	lsls	r3, r0, #30
 8009202:	d506      	bpl.n	8009212 <HAL_RCCEx_PeriphCLKConfig+0x62>
  {
    /* Check the parameters */
    assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection));

    /* Configure the ADC clock source */
    __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
 8009204:	4a23      	ldr	r2, [pc, #140]	; (8009294 <HAL_RCCEx_PeriphCLKConfig+0xe4>)
 8009206:	68a9      	ldr	r1, [r5, #8]
 8009208:	6853      	ldr	r3, [r2, #4]
 800920a:	f423 4340 	bic.w	r3, r3, #49152	; 0xc000
 800920e:	430b      	orrs	r3, r1
 8009210:	6053      	str	r3, [r2, #4]

#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
 || defined(STM32F105xC) || defined(STM32F107xC)
  /*------------------------------ USB clock Configuration ------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
 8009212:	f010 0010 	ands.w	r0, r0, #16
 8009216:	d01b      	beq.n	8009250 <HAL_RCCEx_PeriphCLKConfig+0xa0>
  {
    /* Check the parameters */
    assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection));

    /* Configure the USB clock source */
    __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
 8009218:	4a1e      	ldr	r2, [pc, #120]	; (8009294 <HAL_RCCEx_PeriphCLKConfig+0xe4>)
 800921a:	6969      	ldr	r1, [r5, #20]
 800921c:	6853      	ldr	r3, [r2, #4]
  }
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */

  return HAL_OK;
 800921e:	2000      	movs	r0, #0
    __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
 8009220:	f423 0380 	bic.w	r3, r3, #4194304	; 0x400000
 8009224:	430b      	orrs	r3, r1
 8009226:	6053      	str	r3, [r2, #4]
 8009228:	e012      	b.n	8009250 <HAL_RCCEx_PeriphCLKConfig+0xa0>
    FlagStatus       pwrclkchanged = RESET;
 800922a:	2700      	movs	r7, #0
 800922c:	e7d4      	b.n	80091d8 <HAL_RCCEx_PeriphCLKConfig+0x28>
      SET_BIT(PWR->CR, PWR_CR_DBP);
 800922e:	6833      	ldr	r3, [r6, #0]
 8009230:	f443 7380 	orr.w	r3, r3, #256	; 0x100
 8009234:	6033      	str	r3, [r6, #0]
      tickstart = HAL_GetTick();
 8009236:	f7ff f837 	bl	80082a8 <HAL_GetTick>
 800923a:	4680      	mov	r8, r0
      while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 800923c:	6833      	ldr	r3, [r6, #0]
 800923e:	05d8      	lsls	r0, r3, #23
 8009240:	d4ce      	bmi.n	80091e0 <HAL_RCCEx_PeriphCLKConfig+0x30>
        if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
 8009242:	f7ff f831 	bl	80082a8 <HAL_GetTick>
 8009246:	eba0 0008 	sub.w	r0, r0, r8
 800924a:	2864      	cmp	r0, #100	; 0x64
 800924c:	d9f6      	bls.n	800923c <HAL_RCCEx_PeriphCLKConfig+0x8c>
          return HAL_TIMEOUT;
 800924e:	2003      	movs	r0, #3
}
 8009250:	b002      	add	sp, #8
 8009252:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
 8009256:	686a      	ldr	r2, [r5, #4]
 8009258:	f402 7240 	and.w	r2, r2, #768	; 0x300
 800925c:	4293      	cmp	r3, r2
 800925e:	d0c3      	beq.n	80091e8 <HAL_RCCEx_PeriphCLKConfig+0x38>
      __HAL_RCC_BACKUPRESET_FORCE();
 8009260:	2001      	movs	r0, #1
 8009262:	4a0e      	ldr	r2, [pc, #56]	; (800929c <HAL_RCCEx_PeriphCLKConfig+0xec>)
      temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
 8009264:	6a23      	ldr	r3, [r4, #32]
      __HAL_RCC_BACKUPRESET_FORCE();
 8009266:	6010      	str	r0, [r2, #0]
      __HAL_RCC_BACKUPRESET_RELEASE();
 8009268:	2000      	movs	r0, #0
      temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
 800926a:	f423 7140 	bic.w	r1, r3, #768	; 0x300
      __HAL_RCC_BACKUPRESET_RELEASE();
 800926e:	6010      	str	r0, [r2, #0]
      RCC->BDCR = temp_reg;
 8009270:	6221      	str	r1, [r4, #32]
      if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
 8009272:	07d9      	lsls	r1, r3, #31
 8009274:	d5b8      	bpl.n	80091e8 <HAL_RCCEx_PeriphCLKConfig+0x38>
        tickstart = HAL_GetTick();
 8009276:	f7ff f817 	bl	80082a8 <HAL_GetTick>
          if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 800927a:	f241 3888 	movw	r8, #5000	; 0x1388
        tickstart = HAL_GetTick();
 800927e:	4606      	mov	r6, r0
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
 8009280:	6a23      	ldr	r3, [r4, #32]
 8009282:	079a      	lsls	r2, r3, #30
 8009284:	d4b0      	bmi.n	80091e8 <HAL_RCCEx_PeriphCLKConfig+0x38>
          if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 8009286:	f7ff f80f 	bl	80082a8 <HAL_GetTick>
 800928a:	1b80      	subs	r0, r0, r6
 800928c:	4540      	cmp	r0, r8
 800928e:	d9f7      	bls.n	8009280 <HAL_RCCEx_PeriphCLKConfig+0xd0>
 8009290:	e7dd      	b.n	800924e <HAL_RCCEx_PeriphCLKConfig+0x9e>
 8009292:	bf00      	nop
 8009294:	40021000 	.word	0x40021000
 8009298:	40007000 	.word	0x40007000
 800929c:	42420440 	.word	0x42420440

080092a0 <HAL_TIM_Base_Start_IT>:

  /* Check the parameters */
  assert_param(IS_TIM_INSTANCE(htim->Instance));

  /* Enable the TIM Update interrupt */
  __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
 80092a0:	6803      	ldr	r3, [r0, #0]
    __HAL_TIM_ENABLE(htim);
  }

  /* Return function status */
  return HAL_OK;
}
 80092a2:	2000      	movs	r0, #0
  __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
 80092a4:	68da      	ldr	r2, [r3, #12]
 80092a6:	f042 0201 	orr.w	r2, r2, #1
 80092aa:	60da      	str	r2, [r3, #12]
  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
 80092ac:	689a      	ldr	r2, [r3, #8]
 80092ae:	f002 0207 	and.w	r2, r2, #7
  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
 80092b2:	2a06      	cmp	r2, #6
    __HAL_TIM_ENABLE(htim);
 80092b4:	bf1e      	ittt	ne
 80092b6:	681a      	ldrne	r2, [r3, #0]
 80092b8:	f042 0201 	orrne.w	r2, r2, #1
 80092bc:	601a      	strne	r2, [r3, #0]
}
 80092be:	4770      	bx	lr

080092c0 <HAL_TIM_OC_DelayElapsedCallback>:
 80092c0:	4770      	bx	lr

080092c2 <HAL_TIM_IC_CaptureCallback>:
 80092c2:	4770      	bx	lr

080092c4 <HAL_TIM_PWM_PulseFinishedCallback>:
 80092c4:	4770      	bx	lr

080092c6 <HAL_TIM_TriggerCallback>:
 80092c6:	4770      	bx	lr

080092c8 <HAL_TIM_IRQHandler>:
  * @retval None
  */
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
  /* Capture compare 1 event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
 80092c8:	6803      	ldr	r3, [r0, #0]
{
 80092ca:	b510      	push	{r4, lr}
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
 80092cc:	691a      	ldr	r2, [r3, #16]
{
 80092ce:	4604      	mov	r4, r0
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
 80092d0:	0791      	lsls	r1, r2, #30
 80092d2:	d50e      	bpl.n	80092f2 <HAL_TIM_IRQHandler+0x2a>
  {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
 80092d4:	68da      	ldr	r2, [r3, #12]
 80092d6:	0792      	lsls	r2, r2, #30
 80092d8:	d50b      	bpl.n	80092f2 <HAL_TIM_IRQHandler+0x2a>
    {
      {
        __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
 80092da:	f06f 0202 	mvn.w	r2, #2
 80092de:	611a      	str	r2, [r3, #16]
        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
 80092e0:	2201      	movs	r2, #1

        /* Input capture event */
        if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
 80092e2:	699b      	ldr	r3, [r3, #24]
        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
 80092e4:	7702      	strb	r2, [r0, #28]
        if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
 80092e6:	079b      	lsls	r3, r3, #30
 80092e8:	d077      	beq.n	80093da <HAL_TIM_IRQHandler+0x112>
        {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
          htim->IC_CaptureCallback(htim);
#else
          HAL_TIM_IC_CaptureCallback(htim);
 80092ea:	f7ff ffea 	bl	80092c2 <HAL_TIM_IC_CaptureCallback>
#else
          HAL_TIM_OC_DelayElapsedCallback(htim);
          HAL_TIM_PWM_PulseFinishedCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
        }
        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 80092ee:	2300      	movs	r3, #0
 80092f0:	7723      	strb	r3, [r4, #28]
      }
    }
  }
  /* Capture compare 2 event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
 80092f2:	6823      	ldr	r3, [r4, #0]
 80092f4:	691a      	ldr	r2, [r3, #16]
 80092f6:	0750      	lsls	r0, r2, #29
 80092f8:	d510      	bpl.n	800931c <HAL_TIM_IRQHandler+0x54>
  {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
 80092fa:	68da      	ldr	r2, [r3, #12]
 80092fc:	0751      	lsls	r1, r2, #29
 80092fe:	d50d      	bpl.n	800931c <HAL_TIM_IRQHandler+0x54>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
 8009300:	f06f 0204 	mvn.w	r2, #4
 8009304:	611a      	str	r2, [r3, #16]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
 8009306:	2202      	movs	r2, #2
      /* Input capture event */
      if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
 8009308:	699b      	ldr	r3, [r3, #24]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
 800930a:	7722      	strb	r2, [r4, #28]
      if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
 800930c:	f413 7f40 	tst.w	r3, #768	; 0x300
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->IC_CaptureCallback(htim);
#else
        HAL_TIM_IC_CaptureCallback(htim);
 8009310:	4620      	mov	r0, r4
      if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
 8009312:	d068      	beq.n	80093e6 <HAL_TIM_IRQHandler+0x11e>
        HAL_TIM_IC_CaptureCallback(htim);
 8009314:	f7ff ffd5 	bl	80092c2 <HAL_TIM_IC_CaptureCallback>
#else
        HAL_TIM_OC_DelayElapsedCallback(htim);
        HAL_TIM_PWM_PulseFinishedCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
      }
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 8009318:	2300      	movs	r3, #0
 800931a:	7723      	strb	r3, [r4, #28]
    }
  }
  /* Capture compare 3 event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
 800931c:	6823      	ldr	r3, [r4, #0]
 800931e:	691a      	ldr	r2, [r3, #16]
 8009320:	0712      	lsls	r2, r2, #28
 8009322:	d50f      	bpl.n	8009344 <HAL_TIM_IRQHandler+0x7c>
  {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
 8009324:	68da      	ldr	r2, [r3, #12]
 8009326:	0710      	lsls	r0, r2, #28
 8009328:	d50c      	bpl.n	8009344 <HAL_TIM_IRQHandler+0x7c>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
 800932a:	f06f 0208 	mvn.w	r2, #8
 800932e:	611a      	str	r2, [r3, #16]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
 8009330:	2204      	movs	r2, #4
      /* Input capture event */
      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
 8009332:	69db      	ldr	r3, [r3, #28]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
 8009334:	7722      	strb	r2, [r4, #28]
      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
 8009336:	0799      	lsls	r1, r3, #30
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->IC_CaptureCallback(htim);
#else
        HAL_TIM_IC_CaptureCallback(htim);
 8009338:	4620      	mov	r0, r4
      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
 800933a:	d05a      	beq.n	80093f2 <HAL_TIM_IRQHandler+0x12a>
        HAL_TIM_IC_CaptureCallback(htim);
 800933c:	f7ff ffc1 	bl	80092c2 <HAL_TIM_IC_CaptureCallback>
#else
        HAL_TIM_OC_DelayElapsedCallback(htim);
        HAL_TIM_PWM_PulseFinishedCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
      }
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 8009340:	2300      	movs	r3, #0
 8009342:	7723      	strb	r3, [r4, #28]
    }
  }
  /* Capture compare 4 event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
 8009344:	6823      	ldr	r3, [r4, #0]
 8009346:	691a      	ldr	r2, [r3, #16]
 8009348:	06d2      	lsls	r2, r2, #27
 800934a:	d510      	bpl.n	800936e <HAL_TIM_IRQHandler+0xa6>
  {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
 800934c:	68da      	ldr	r2, [r3, #12]
 800934e:	06d0      	lsls	r0, r2, #27
 8009350:	d50d      	bpl.n	800936e <HAL_TIM_IRQHandler+0xa6>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
 8009352:	f06f 0210 	mvn.w	r2, #16
 8009356:	611a      	str	r2, [r3, #16]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
 8009358:	2208      	movs	r2, #8
      /* Input capture event */
      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
 800935a:	69db      	ldr	r3, [r3, #28]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
 800935c:	7722      	strb	r2, [r4, #28]
      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
 800935e:	f413 7f40 	tst.w	r3, #768	; 0x300
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->IC_CaptureCallback(htim);
#else
        HAL_TIM_IC_CaptureCallback(htim);
 8009362:	4620      	mov	r0, r4
      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
 8009364:	d04b      	beq.n	80093fe <HAL_TIM_IRQHandler+0x136>
        HAL_TIM_IC_CaptureCallback(htim);
 8009366:	f7ff ffac 	bl	80092c2 <HAL_TIM_IC_CaptureCallback>
#else
        HAL_TIM_OC_DelayElapsedCallback(htim);
        HAL_TIM_PWM_PulseFinishedCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
      }
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 800936a:	2300      	movs	r3, #0
 800936c:	7723      	strb	r3, [r4, #28]
    }
  }
  /* TIM Update event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
 800936e:	6823      	ldr	r3, [r4, #0]
 8009370:	691a      	ldr	r2, [r3, #16]
 8009372:	07d1      	lsls	r1, r2, #31
 8009374:	d508      	bpl.n	8009388 <HAL_TIM_IRQHandler+0xc0>
  {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
 8009376:	68da      	ldr	r2, [r3, #12]
 8009378:	07d2      	lsls	r2, r2, #31
 800937a:	d505      	bpl.n	8009388 <HAL_TIM_IRQHandler+0xc0>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
 800937c:	f06f 0201 	mvn.w	r2, #1
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
      htim->PeriodElapsedCallback(htim);
#else
      HAL_TIM_PeriodElapsedCallback(htim);
 8009380:	4620      	mov	r0, r4
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
 8009382:	611a      	str	r2, [r3, #16]
      HAL_TIM_PeriodElapsedCallback(htim);
 8009384:	f000 fbb8 	bl	8009af8 <HAL_TIM_PeriodElapsedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
    }
  }
  /* TIM Break input event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
 8009388:	6823      	ldr	r3, [r4, #0]
 800938a:	691a      	ldr	r2, [r3, #16]
 800938c:	0610      	lsls	r0, r2, #24
 800938e:	d508      	bpl.n	80093a2 <HAL_TIM_IRQHandler+0xda>
  {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
 8009390:	68da      	ldr	r2, [r3, #12]
 8009392:	0611      	lsls	r1, r2, #24
 8009394:	d505      	bpl.n	80093a2 <HAL_TIM_IRQHandler+0xda>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
 8009396:	f06f 0280 	mvn.w	r2, #128	; 0x80
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
      htim->BreakCallback(htim);
#else
      HAL_TIMEx_BreakCallback(htim);
 800939a:	4620      	mov	r0, r4
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
 800939c:	611a      	str	r2, [r3, #16]
      HAL_TIMEx_BreakCallback(htim);
 800939e:	f000 f8ba 	bl	8009516 <HAL_TIMEx_BreakCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
    }
  }
  /* TIM Trigger detection event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
 80093a2:	6823      	ldr	r3, [r4, #0]
 80093a4:	691a      	ldr	r2, [r3, #16]
 80093a6:	0652      	lsls	r2, r2, #25
 80093a8:	d508      	bpl.n	80093bc <HAL_TIM_IRQHandler+0xf4>
  {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
 80093aa:	68da      	ldr	r2, [r3, #12]
 80093ac:	0650      	lsls	r0, r2, #25
 80093ae:	d505      	bpl.n	80093bc <HAL_TIM_IRQHandler+0xf4>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
 80093b0:	f06f 0240 	mvn.w	r2, #64	; 0x40
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
      htim->TriggerCallback(htim);
#else
      HAL_TIM_TriggerCallback(htim);
 80093b4:	4620      	mov	r0, r4
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
 80093b6:	611a      	str	r2, [r3, #16]
      HAL_TIM_TriggerCallback(htim);
 80093b8:	f7ff ff85 	bl	80092c6 <HAL_TIM_TriggerCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
    }
  }
  /* TIM commutation event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
 80093bc:	6823      	ldr	r3, [r4, #0]
 80093be:	691a      	ldr	r2, [r3, #16]
 80093c0:	0691      	lsls	r1, r2, #26
 80093c2:	d522      	bpl.n	800940a <HAL_TIM_IRQHandler+0x142>
  {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
 80093c4:	68da      	ldr	r2, [r3, #12]
 80093c6:	0692      	lsls	r2, r2, #26
 80093c8:	d51f      	bpl.n	800940a <HAL_TIM_IRQHandler+0x142>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
 80093ca:	f06f 0220 	mvn.w	r2, #32
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
      htim->CommutationCallback(htim);
#else
      HAL_TIMEx_CommutCallback(htim);
 80093ce:	4620      	mov	r0, r4
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
    }
  }
}
 80093d0:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
      __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
 80093d4:	611a      	str	r2, [r3, #16]
      HAL_TIMEx_CommutCallback(htim);
 80093d6:	f000 b89d 	b.w	8009514 <HAL_TIMEx_CommutCallback>
          HAL_TIM_OC_DelayElapsedCallback(htim);
 80093da:	f7ff ff71 	bl	80092c0 <HAL_TIM_OC_DelayElapsedCallback>
          HAL_TIM_PWM_PulseFinishedCallback(htim);
 80093de:	4620      	mov	r0, r4
 80093e0:	f7ff ff70 	bl	80092c4 <HAL_TIM_PWM_PulseFinishedCallback>
 80093e4:	e783      	b.n	80092ee <HAL_TIM_IRQHandler+0x26>
        HAL_TIM_OC_DelayElapsedCallback(htim);
 80093e6:	f7ff ff6b 	bl	80092c0 <HAL_TIM_OC_DelayElapsedCallback>
        HAL_TIM_PWM_PulseFinishedCallback(htim);
 80093ea:	4620      	mov	r0, r4
 80093ec:	f7ff ff6a 	bl	80092c4 <HAL_TIM_PWM_PulseFinishedCallback>
 80093f0:	e792      	b.n	8009318 <HAL_TIM_IRQHandler+0x50>
        HAL_TIM_OC_DelayElapsedCallback(htim);
 80093f2:	f7ff ff65 	bl	80092c0 <HAL_TIM_OC_DelayElapsedCallback>
        HAL_TIM_PWM_PulseFinishedCallback(htim);
 80093f6:	4620      	mov	r0, r4
 80093f8:	f7ff ff64 	bl	80092c4 <HAL_TIM_PWM_PulseFinishedCallback>
 80093fc:	e7a0      	b.n	8009340 <HAL_TIM_IRQHandler+0x78>
        HAL_TIM_OC_DelayElapsedCallback(htim);
 80093fe:	f7ff ff5f 	bl	80092c0 <HAL_TIM_OC_DelayElapsedCallback>
        HAL_TIM_PWM_PulseFinishedCallback(htim);
 8009402:	4620      	mov	r0, r4
 8009404:	f7ff ff5e 	bl	80092c4 <HAL_TIM_PWM_PulseFinishedCallback>
 8009408:	e7af      	b.n	800936a <HAL_TIM_IRQHandler+0xa2>
 800940a:	bd10      	pop	{r4, pc}

0800940c <TIM_Base_SetConfig>:
{
  uint32_t tmpcr1;
  tmpcr1 = TIMx->CR1;

  /* Set TIM Time Base Unit parameters ---------------------------------------*/
  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
 800940c:	4a24      	ldr	r2, [pc, #144]	; (80094a0 <TIM_Base_SetConfig+0x94>)
  tmpcr1 = TIMx->CR1;
 800940e:	6803      	ldr	r3, [r0, #0]
  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
 8009410:	4290      	cmp	r0, r2
 8009412:	d012      	beq.n	800943a <TIM_Base_SetConfig+0x2e>
 8009414:	f502 6200 	add.w	r2, r2, #2048	; 0x800
 8009418:	4290      	cmp	r0, r2
 800941a:	d00e      	beq.n	800943a <TIM_Base_SetConfig+0x2e>
 800941c:	f1b0 4f80 	cmp.w	r0, #1073741824	; 0x40000000
 8009420:	d00b      	beq.n	800943a <TIM_Base_SetConfig+0x2e>
 8009422:	f5a2 3298 	sub.w	r2, r2, #77824	; 0x13000
 8009426:	4290      	cmp	r0, r2
 8009428:	d007      	beq.n	800943a <TIM_Base_SetConfig+0x2e>
 800942a:	f502 6280 	add.w	r2, r2, #1024	; 0x400
 800942e:	4290      	cmp	r0, r2
 8009430:	d003      	beq.n	800943a <TIM_Base_SetConfig+0x2e>
 8009432:	f502 6280 	add.w	r2, r2, #1024	; 0x400
 8009436:	4290      	cmp	r0, r2
 8009438:	d11d      	bne.n	8009476 <TIM_Base_SetConfig+0x6a>
  {
    /* Select the Counter Mode */
    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
    tmpcr1 |= Structure->CounterMode;
 800943a:	684a      	ldr	r2, [r1, #4]
    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
 800943c:	f023 0370 	bic.w	r3, r3, #112	; 0x70
    tmpcr1 |= Structure->CounterMode;
 8009440:	4313      	orrs	r3, r2
  }

  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
 8009442:	4a17      	ldr	r2, [pc, #92]	; (80094a0 <TIM_Base_SetConfig+0x94>)
 8009444:	4290      	cmp	r0, r2
 8009446:	d012      	beq.n	800946e <TIM_Base_SetConfig+0x62>
 8009448:	f502 6200 	add.w	r2, r2, #2048	; 0x800
 800944c:	4290      	cmp	r0, r2
 800944e:	d00e      	beq.n	800946e <TIM_Base_SetConfig+0x62>
 8009450:	f1b0 4f80 	cmp.w	r0, #1073741824	; 0x40000000
 8009454:	d00b      	beq.n	800946e <TIM_Base_SetConfig+0x62>
 8009456:	f5a2 3298 	sub.w	r2, r2, #77824	; 0x13000
 800945a:	4290      	cmp	r0, r2
 800945c:	d007      	beq.n	800946e <TIM_Base_SetConfig+0x62>
 800945e:	f502 6280 	add.w	r2, r2, #1024	; 0x400
 8009462:	4290      	cmp	r0, r2
 8009464:	d003      	beq.n	800946e <TIM_Base_SetConfig+0x62>
 8009466:	f502 6280 	add.w	r2, r2, #1024	; 0x400
 800946a:	4290      	cmp	r0, r2
 800946c:	d103      	bne.n	8009476 <TIM_Base_SetConfig+0x6a>
  {
    /* Set the clock division */
    tmpcr1 &= ~TIM_CR1_CKD;
    tmpcr1 |= (uint32_t)Structure->ClockDivision;
 800946e:	68ca      	ldr	r2, [r1, #12]
    tmpcr1 &= ~TIM_CR1_CKD;
 8009470:	f423 7340 	bic.w	r3, r3, #768	; 0x300
    tmpcr1 |= (uint32_t)Structure->ClockDivision;
 8009474:	4313      	orrs	r3, r2
  }

  /* Set the auto-reload preload */
  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
 8009476:	694a      	ldr	r2, [r1, #20]
 8009478:	f023 0380 	bic.w	r3, r3, #128	; 0x80
 800947c:	4313      	orrs	r3, r2

  TIMx->CR1 = tmpcr1;
 800947e:	6003      	str	r3, [r0, #0]

  /* Set the Autoreload value */
  TIMx->ARR = (uint32_t)Structure->Period ;
 8009480:	688b      	ldr	r3, [r1, #8]
 8009482:	62c3      	str	r3, [r0, #44]	; 0x2c

  /* Set the Prescaler value */
  TIMx->PSC = Structure->Prescaler;
 8009484:	680b      	ldr	r3, [r1, #0]
 8009486:	6283      	str	r3, [r0, #40]	; 0x28

  if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
 8009488:	4b05      	ldr	r3, [pc, #20]	; (80094a0 <TIM_Base_SetConfig+0x94>)
 800948a:	4298      	cmp	r0, r3
 800948c:	d003      	beq.n	8009496 <TIM_Base_SetConfig+0x8a>
 800948e:	f503 6300 	add.w	r3, r3, #2048	; 0x800
 8009492:	4298      	cmp	r0, r3
 8009494:	d101      	bne.n	800949a <TIM_Base_SetConfig+0x8e>
  {
    /* Set the Repetition Counter value */
    TIMx->RCR = Structure->RepetitionCounter;
 8009496:	690b      	ldr	r3, [r1, #16]
 8009498:	6303      	str	r3, [r0, #48]	; 0x30
  }

  /* Generate an update event to reload the Prescaler
     and the repetition counter (only for advanced timer) value immediately */
  TIMx->EGR = TIM_EGR_UG;
 800949a:	2301      	movs	r3, #1
 800949c:	6143      	str	r3, [r0, #20]
 800949e:	4770      	bx	lr
 80094a0:	40012c00 	.word	0x40012c00

080094a4 <HAL_TIM_Base_Init>:
{
 80094a4:	b510      	push	{r4, lr}
  if (htim == NULL)
 80094a6:	4604      	mov	r4, r0
 80094a8:	b1a0      	cbz	r0, 80094d4 <HAL_TIM_Base_Init+0x30>
  if (htim->State == HAL_TIM_STATE_RESET)
 80094aa:	f890 303d 	ldrb.w	r3, [r0, #61]	; 0x3d
 80094ae:	f003 02ff 	and.w	r2, r3, #255	; 0xff
 80094b2:	b91b      	cbnz	r3, 80094bc <HAL_TIM_Base_Init+0x18>
    htim->Lock = HAL_UNLOCKED;
 80094b4:	f880 203c 	strb.w	r2, [r0, #60]	; 0x3c
    HAL_TIM_Base_MspInit(htim);
 80094b8:	f000 fe0a 	bl	800a0d0 <HAL_TIM_Base_MspInit>
  htim->State = HAL_TIM_STATE_BUSY;
 80094bc:	2302      	movs	r3, #2
  TIM_Base_SetConfig(htim->Instance, &htim->Init);
 80094be:	6820      	ldr	r0, [r4, #0]
  htim->State = HAL_TIM_STATE_BUSY;
 80094c0:	f884 303d 	strb.w	r3, [r4, #61]	; 0x3d
  TIM_Base_SetConfig(htim->Instance, &htim->Init);
 80094c4:	1d21      	adds	r1, r4, #4
 80094c6:	f7ff ffa1 	bl	800940c <TIM_Base_SetConfig>
  htim->State = HAL_TIM_STATE_READY;
 80094ca:	2301      	movs	r3, #1
  return HAL_OK;
 80094cc:	2000      	movs	r0, #0
  htim->State = HAL_TIM_STATE_READY;
 80094ce:	f884 303d 	strb.w	r3, [r4, #61]	; 0x3d
  return HAL_OK;
 80094d2:	bd10      	pop	{r4, pc}
    return HAL_ERROR;
 80094d4:	2001      	movs	r0, #1
}
 80094d6:	bd10      	pop	{r4, pc}

080094d8 <HAL_TIMEx_MasterConfigSynchronization>:
  assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));
  assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
  assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));

  /* Check input state */
  __HAL_LOCK(htim);
 80094d8:	f890 303c 	ldrb.w	r3, [r0, #60]	; 0x3c
{
 80094dc:	b530      	push	{r4, r5, lr}
  __HAL_LOCK(htim);
 80094de:	2b01      	cmp	r3, #1
 80094e0:	f04f 0302 	mov.w	r3, #2
 80094e4:	d014      	beq.n	8009510 <HAL_TIMEx_MasterConfigSynchronization+0x38>

  /* Change the handler state */
  htim->State = HAL_TIM_STATE_BUSY;

  /* Get the TIMx CR2 register value */
  tmpcr2 = htim->Instance->CR2;
 80094e6:	6804      	ldr	r4, [r0, #0]
  htim->State = HAL_TIM_STATE_BUSY;
 80094e8:	f880 303d 	strb.w	r3, [r0, #61]	; 0x3d
  tmpcr2 = htim->Instance->CR2;
 80094ec:	6862      	ldr	r2, [r4, #4]

  /* Get the TIMx SMCR register value */
  tmpsmcr = htim->Instance->SMCR;
 80094ee:	68a3      	ldr	r3, [r4, #8]

  /* Reset the MMS Bits */
  tmpcr2 &= ~TIM_CR2_MMS;
  /* Select the TRGO source */
  tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
 80094f0:	680d      	ldr	r5, [r1, #0]

  /* Reset the MSM Bit */
  tmpsmcr &= ~TIM_SMCR_MSM;
  /* Set master mode */
  tmpsmcr |= sMasterConfig->MasterSlaveMode;
 80094f2:	6849      	ldr	r1, [r1, #4]
  tmpcr2 &= ~TIM_CR2_MMS;
 80094f4:	f022 0270 	bic.w	r2, r2, #112	; 0x70
  tmpsmcr &= ~TIM_SMCR_MSM;
 80094f8:	f023 0380 	bic.w	r3, r3, #128	; 0x80
  tmpsmcr |= sMasterConfig->MasterSlaveMode;
 80094fc:	430b      	orrs	r3, r1
  tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
 80094fe:	432a      	orrs	r2, r5

  /* Update TIMx CR2 */
  htim->Instance->CR2 = tmpcr2;
 8009500:	6062      	str	r2, [r4, #4]

  /* Update TIMx SMCR */
  htim->Instance->SMCR = tmpsmcr;
 8009502:	60a3      	str	r3, [r4, #8]

  /* Change the htim state */
  htim->State = HAL_TIM_STATE_READY;
 8009504:	2301      	movs	r3, #1
 8009506:	f880 303d 	strb.w	r3, [r0, #61]	; 0x3d

  __HAL_UNLOCK(htim);
 800950a:	2300      	movs	r3, #0
 800950c:	f880 303c 	strb.w	r3, [r0, #60]	; 0x3c
  __HAL_LOCK(htim);
 8009510:	4618      	mov	r0, r3

  return HAL_OK;
}
 8009512:	bd30      	pop	{r4, r5, pc}

08009514 <HAL_TIMEx_CommutCallback>:
 8009514:	4770      	bx	lr

08009516 <HAL_TIMEx_BreakCallback>:
  * @brief  Hall Break detection callback in non-blocking mode
  * @param  htim TIM handle
  * @retval None
  */
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
{
 8009516:	4770      	bx	lr

08009518 <UART_EndRxTransfer>:
  * @retval None
  */
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
{
  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
 8009518:	6803      	ldr	r3, [r0, #0]
 800951a:	68da      	ldr	r2, [r3, #12]
 800951c:	f422 7290 	bic.w	r2, r2, #288	; 0x120
 8009520:	60da      	str	r2, [r3, #12]
  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 8009522:	695a      	ldr	r2, [r3, #20]
 8009524:	f022 0201 	bic.w	r2, r2, #1
 8009528:	615a      	str	r2, [r3, #20]

  /* At end of Rx process, restore huart->RxState to Ready */
  huart->RxState = HAL_UART_STATE_READY;
 800952a:	2320      	movs	r3, #32
 800952c:	f880 303a 	strb.w	r3, [r0, #58]	; 0x3a
 8009530:	4770      	bx	lr
	...

08009534 <UART_SetConfig>:
  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
  *                the configuration information for the specified UART module.
  * @retval None
  */
static void UART_SetConfig(UART_HandleTypeDef *huart)
{
 8009534:	b538      	push	{r3, r4, r5, lr}
 8009536:	4605      	mov	r5, r0
  assert_param(IS_UART_MODE(huart->Init.Mode));

  /*-------------------------- USART CR2 Configuration -----------------------*/
  /* Configure the UART Stop Bits: Set STOP[13:12] bits
     according to huart->Init.StopBits value */
  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
 8009538:	6803      	ldr	r3, [r0, #0]
 800953a:	68c1      	ldr	r1, [r0, #12]
 800953c:	691a      	ldr	r2, [r3, #16]
 800953e:	2419      	movs	r4, #25
 8009540:	f422 5240 	bic.w	r2, r2, #12288	; 0x3000
 8009544:	430a      	orrs	r2, r1
 8009546:	611a      	str	r2, [r3, #16]
  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
  MODIFY_REG(huart->Instance->CR1,
             (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
             tmpreg);
#else
  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
 8009548:	6882      	ldr	r2, [r0, #8]
 800954a:	6900      	ldr	r0, [r0, #16]
  MODIFY_REG(huart->Instance->CR1,
 800954c:	68d9      	ldr	r1, [r3, #12]
  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
 800954e:	4302      	orrs	r2, r0
 8009550:	6968      	ldr	r0, [r5, #20]
  MODIFY_REG(huart->Instance->CR1,
 8009552:	f421 51b0 	bic.w	r1, r1, #5632	; 0x1600
 8009556:	f021 010c 	bic.w	r1, r1, #12
  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
 800955a:	4302      	orrs	r2, r0
  MODIFY_REG(huart->Instance->CR1,
 800955c:	430a      	orrs	r2, r1
 800955e:	60da      	str	r2, [r3, #12]
             tmpreg);
#endif /* USART_CR1_OVER8 */

  /*-------------------------- USART CR3 Configuration -----------------------*/
  /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
  MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
 8009560:	695a      	ldr	r2, [r3, #20]
 8009562:	69a9      	ldr	r1, [r5, #24]
 8009564:	f422 7240 	bic.w	r2, r2, #768	; 0x300
 8009568:	430a      	orrs	r2, r1
 800956a:	615a      	str	r2, [r3, #20]
      huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
    }
  }
#else
  /*-------------------------- USART BRR Configuration ---------------------*/
  if(huart->Instance == USART1)
 800956c:	4a0d      	ldr	r2, [pc, #52]	; (80095a4 <UART_SetConfig+0x70>)
 800956e:	4293      	cmp	r3, r2
 8009570:	d114      	bne.n	800959c <UART_SetConfig+0x68>
  {
    pclk = HAL_RCC_GetPCLK2Freq();
 8009572:	f7ff fe0d 	bl	8009190 <HAL_RCC_GetPCLK2Freq>
    huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
  }
  else
  {
    pclk = HAL_RCC_GetPCLK1Freq();
    huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
 8009576:	4360      	muls	r0, r4
 8009578:	686c      	ldr	r4, [r5, #4]
 800957a:	2264      	movs	r2, #100	; 0x64
 800957c:	00a4      	lsls	r4, r4, #2
 800957e:	fbb0 f0f4 	udiv	r0, r0, r4
 8009582:	fbb0 f4f2 	udiv	r4, r0, r2
 8009586:	fb02 0314 	mls	r3, r2, r4, r0
 800958a:	011b      	lsls	r3, r3, #4
 800958c:	3332      	adds	r3, #50	; 0x32
 800958e:	fbb3 f3f2 	udiv	r3, r3, r2
 8009592:	6829      	ldr	r1, [r5, #0]
 8009594:	eb03 1304 	add.w	r3, r3, r4, lsl #4
 8009598:	608b      	str	r3, [r1, #8]
 800959a:	bd38      	pop	{r3, r4, r5, pc}
    pclk = HAL_RCC_GetPCLK1Freq();
 800959c:	f7ff fde8 	bl	8009170 <HAL_RCC_GetPCLK1Freq>
 80095a0:	e7e9      	b.n	8009576 <UART_SetConfig+0x42>
 80095a2:	bf00      	nop
 80095a4:	40013800 	.word	0x40013800

080095a8 <UART_WaitOnFlagUntilTimeout.constprop.3>:
static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
 80095a8:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 80095aa:	4604      	mov	r4, r0
 80095ac:	460e      	mov	r6, r1
 80095ae:	4617      	mov	r7, r2
 80095b0:	461d      	mov	r5, r3
  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
 80095b2:	6821      	ldr	r1, [r4, #0]
 80095b4:	680b      	ldr	r3, [r1, #0]
 80095b6:	ea36 0303 	bics.w	r3, r6, r3
 80095ba:	d101      	bne.n	80095c0 <UART_WaitOnFlagUntilTimeout.constprop.3+0x18>
  return HAL_OK;
 80095bc:	2000      	movs	r0, #0
}
 80095be:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    if (Timeout != HAL_MAX_DELAY)
 80095c0:	1c6b      	adds	r3, r5, #1
 80095c2:	d0f7      	beq.n	80095b4 <UART_WaitOnFlagUntilTimeout.constprop.3+0xc>
      if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
 80095c4:	b995      	cbnz	r5, 80095ec <UART_WaitOnFlagUntilTimeout.constprop.3+0x44>
        CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
 80095c6:	6823      	ldr	r3, [r4, #0]
        __HAL_UNLOCK(huart);
 80095c8:	2003      	movs	r0, #3
        CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
 80095ca:	68da      	ldr	r2, [r3, #12]
 80095cc:	f422 72d0 	bic.w	r2, r2, #416	; 0x1a0
 80095d0:	60da      	str	r2, [r3, #12]
        CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 80095d2:	695a      	ldr	r2, [r3, #20]
 80095d4:	f022 0201 	bic.w	r2, r2, #1
 80095d8:	615a      	str	r2, [r3, #20]
        huart->gState  = HAL_UART_STATE_READY;
 80095da:	2320      	movs	r3, #32
 80095dc:	f884 3039 	strb.w	r3, [r4, #57]	; 0x39
        huart->RxState = HAL_UART_STATE_READY;
 80095e0:	f884 303a 	strb.w	r3, [r4, #58]	; 0x3a
        __HAL_UNLOCK(huart);
 80095e4:	2300      	movs	r3, #0
 80095e6:	f884 3038 	strb.w	r3, [r4, #56]	; 0x38
 80095ea:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
      if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
 80095ec:	f7fe fe5c 	bl	80082a8 <HAL_GetTick>
 80095f0:	1bc0      	subs	r0, r0, r7
 80095f2:	4285      	cmp	r5, r0
 80095f4:	d2dd      	bcs.n	80095b2 <UART_WaitOnFlagUntilTimeout.constprop.3+0xa>
 80095f6:	e7e6      	b.n	80095c6 <UART_WaitOnFlagUntilTimeout.constprop.3+0x1e>

080095f8 <HAL_UART_Init>:
{
 80095f8:	b510      	push	{r4, lr}
  if (huart == NULL)
 80095fa:	4604      	mov	r4, r0
 80095fc:	b340      	cbz	r0, 8009650 <HAL_UART_Init+0x58>
  if (huart->gState == HAL_UART_STATE_RESET)
 80095fe:	f890 3039 	ldrb.w	r3, [r0, #57]	; 0x39
 8009602:	f003 02ff 	and.w	r2, r3, #255	; 0xff
 8009606:	b91b      	cbnz	r3, 8009610 <HAL_UART_Init+0x18>
    huart->Lock = HAL_UNLOCKED;
 8009608:	f880 2038 	strb.w	r2, [r0, #56]	; 0x38
    HAL_UART_MspInit(huart);
 800960c:	f000 fd74 	bl	800a0f8 <HAL_UART_MspInit>
  huart->gState = HAL_UART_STATE_BUSY;
 8009610:	2324      	movs	r3, #36	; 0x24
  __HAL_UART_DISABLE(huart);
 8009612:	6822      	ldr	r2, [r4, #0]
  huart->gState = HAL_UART_STATE_BUSY;
 8009614:	f884 3039 	strb.w	r3, [r4, #57]	; 0x39
  __HAL_UART_DISABLE(huart);
 8009618:	68d3      	ldr	r3, [r2, #12]
  UART_SetConfig(huart);
 800961a:	4620      	mov	r0, r4
  __HAL_UART_DISABLE(huart);
 800961c:	f423 5300 	bic.w	r3, r3, #8192	; 0x2000
 8009620:	60d3      	str	r3, [r2, #12]
  UART_SetConfig(huart);
 8009622:	f7ff ff87 	bl	8009534 <UART_SetConfig>
  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
 8009626:	6823      	ldr	r3, [r4, #0]
  huart->ErrorCode = HAL_UART_ERROR_NONE;
 8009628:	2000      	movs	r0, #0
  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
 800962a:	691a      	ldr	r2, [r3, #16]
 800962c:	f422 4290 	bic.w	r2, r2, #18432	; 0x4800
 8009630:	611a      	str	r2, [r3, #16]
  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
 8009632:	695a      	ldr	r2, [r3, #20]
 8009634:	f022 022a 	bic.w	r2, r2, #42	; 0x2a
 8009638:	615a      	str	r2, [r3, #20]
  __HAL_UART_ENABLE(huart);
 800963a:	68da      	ldr	r2, [r3, #12]
 800963c:	f442 5200 	orr.w	r2, r2, #8192	; 0x2000
 8009640:	60da      	str	r2, [r3, #12]
  huart->gState = HAL_UART_STATE_READY;
 8009642:	2320      	movs	r3, #32
  huart->ErrorCode = HAL_UART_ERROR_NONE;
 8009644:	63e0      	str	r0, [r4, #60]	; 0x3c
  huart->gState = HAL_UART_STATE_READY;
 8009646:	f884 3039 	strb.w	r3, [r4, #57]	; 0x39
  huart->RxState = HAL_UART_STATE_READY;
 800964a:	f884 303a 	strb.w	r3, [r4, #58]	; 0x3a
  return HAL_OK;
 800964e:	bd10      	pop	{r4, pc}
    return HAL_ERROR;
 8009650:	2001      	movs	r0, #1
}
 8009652:	bd10      	pop	{r4, pc}

08009654 <HAL_UART_Transmit>:
{
 8009654:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
 8009658:	461f      	mov	r7, r3
  if (huart->gState == HAL_UART_STATE_READY)
 800965a:	f890 3039 	ldrb.w	r3, [r0, #57]	; 0x39
{
 800965e:	4604      	mov	r4, r0
  if (huart->gState == HAL_UART_STATE_READY)
 8009660:	2b20      	cmp	r3, #32
{
 8009662:	460d      	mov	r5, r1
 8009664:	4690      	mov	r8, r2
  if (huart->gState == HAL_UART_STATE_READY)
 8009666:	d14e      	bne.n	8009706 <HAL_UART_Transmit+0xb2>
    if ((pData == NULL) || (Size == 0U))
 8009668:	2900      	cmp	r1, #0
 800966a:	d049      	beq.n	8009700 <HAL_UART_Transmit+0xac>
 800966c:	2a00      	cmp	r2, #0
 800966e:	d047      	beq.n	8009700 <HAL_UART_Transmit+0xac>
    __HAL_LOCK(huart);
 8009670:	f890 3038 	ldrb.w	r3, [r0, #56]	; 0x38
 8009674:	2b01      	cmp	r3, #1
 8009676:	d046      	beq.n	8009706 <HAL_UART_Transmit+0xb2>
 8009678:	2301      	movs	r3, #1
 800967a:	f880 3038 	strb.w	r3, [r0, #56]	; 0x38
    huart->ErrorCode = HAL_UART_ERROR_NONE;
 800967e:	2300      	movs	r3, #0
 8009680:	63c3      	str	r3, [r0, #60]	; 0x3c
    huart->gState = HAL_UART_STATE_BUSY_TX;
 8009682:	2321      	movs	r3, #33	; 0x21
 8009684:	f880 3039 	strb.w	r3, [r0, #57]	; 0x39
    tickstart = HAL_GetTick();
 8009688:	f7fe fe0e 	bl	80082a8 <HAL_GetTick>
 800968c:	4606      	mov	r6, r0
    huart->TxXferSize = Size;
 800968e:	f8a4 8024 	strh.w	r8, [r4, #36]	; 0x24
    huart->TxXferCount = Size;
 8009692:	f8a4 8026 	strh.w	r8, [r4, #38]	; 0x26
    while (huart->TxXferCount > 0U)
 8009696:	8ce3      	ldrh	r3, [r4, #38]	; 0x26
 8009698:	b29b      	uxth	r3, r3
 800969a:	b96b      	cbnz	r3, 80096b8 <HAL_UART_Transmit+0x64>
    if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
 800969c:	463b      	mov	r3, r7
 800969e:	4632      	mov	r2, r6
 80096a0:	2140      	movs	r1, #64	; 0x40
 80096a2:	4620      	mov	r0, r4
 80096a4:	f7ff ff80 	bl	80095a8 <UART_WaitOnFlagUntilTimeout.constprop.3>
 80096a8:	b9a8      	cbnz	r0, 80096d6 <HAL_UART_Transmit+0x82>
    huart->gState = HAL_UART_STATE_READY;
 80096aa:	2320      	movs	r3, #32
    __HAL_UNLOCK(huart);
 80096ac:	f884 0038 	strb.w	r0, [r4, #56]	; 0x38
    huart->gState = HAL_UART_STATE_READY;
 80096b0:	f884 3039 	strb.w	r3, [r4, #57]	; 0x39
    return HAL_OK;
 80096b4:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
      huart->TxXferCount--;
 80096b8:	8ce3      	ldrh	r3, [r4, #38]	; 0x26
        if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
 80096ba:	4632      	mov	r2, r6
      huart->TxXferCount--;
 80096bc:	3b01      	subs	r3, #1
 80096be:	b29b      	uxth	r3, r3
 80096c0:	84e3      	strh	r3, [r4, #38]	; 0x26
      if (huart->Init.WordLength == UART_WORDLENGTH_9B)
 80096c2:	68a3      	ldr	r3, [r4, #8]
        if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
 80096c4:	2180      	movs	r1, #128	; 0x80
      if (huart->Init.WordLength == UART_WORDLENGTH_9B)
 80096c6:	f5b3 5f80 	cmp.w	r3, #4096	; 0x1000
        if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
 80096ca:	4620      	mov	r0, r4
 80096cc:	463b      	mov	r3, r7
      if (huart->Init.WordLength == UART_WORDLENGTH_9B)
 80096ce:	d10e      	bne.n	80096ee <HAL_UART_Transmit+0x9a>
        if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
 80096d0:	f7ff ff6a 	bl	80095a8 <UART_WaitOnFlagUntilTimeout.constprop.3>
 80096d4:	b110      	cbz	r0, 80096dc <HAL_UART_Transmit+0x88>
          return HAL_TIMEOUT;
 80096d6:	2003      	movs	r0, #3
 80096d8:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
        huart->Instance->DR = (*tmp & (uint16_t)0x01FF);
 80096dc:	882b      	ldrh	r3, [r5, #0]
 80096de:	6822      	ldr	r2, [r4, #0]
 80096e0:	f3c3 0308 	ubfx	r3, r3, #0, #9
 80096e4:	6053      	str	r3, [r2, #4]
        if (huart->Init.Parity == UART_PARITY_NONE)
 80096e6:	6923      	ldr	r3, [r4, #16]
 80096e8:	b943      	cbnz	r3, 80096fc <HAL_UART_Transmit+0xa8>
          pData += 2U;
 80096ea:	3502      	adds	r5, #2
 80096ec:	e7d3      	b.n	8009696 <HAL_UART_Transmit+0x42>
        if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
 80096ee:	f7ff ff5b 	bl	80095a8 <UART_WaitOnFlagUntilTimeout.constprop.3>
 80096f2:	2800      	cmp	r0, #0
 80096f4:	d1ef      	bne.n	80096d6 <HAL_UART_Transmit+0x82>
        huart->Instance->DR = (*pData++ & (uint8_t)0xFF);
 80096f6:	6823      	ldr	r3, [r4, #0]
 80096f8:	782a      	ldrb	r2, [r5, #0]
 80096fa:	605a      	str	r2, [r3, #4]
 80096fc:	3501      	adds	r5, #1
 80096fe:	e7ca      	b.n	8009696 <HAL_UART_Transmit+0x42>
      return  HAL_ERROR;
 8009700:	2001      	movs	r0, #1
 8009702:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    return HAL_BUSY;
 8009706:	2002      	movs	r0, #2
}
 8009708:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

0800970c <HAL_UART_Transmit_DMA>:
{
 800970c:	b538      	push	{r3, r4, r5, lr}
 800970e:	4604      	mov	r4, r0
 8009710:	4613      	mov	r3, r2
  if (huart->gState == HAL_UART_STATE_READY)
 8009712:	f894 2039 	ldrb.w	r2, [r4, #57]	; 0x39
 8009716:	2a20      	cmp	r2, #32
 8009718:	d12a      	bne.n	8009770 <HAL_UART_Transmit_DMA+0x64>
    if ((pData == NULL) || (Size == 0U))
 800971a:	b339      	cbz	r1, 800976c <HAL_UART_Transmit_DMA+0x60>
 800971c:	b333      	cbz	r3, 800976c <HAL_UART_Transmit_DMA+0x60>
    __HAL_LOCK(huart);
 800971e:	f894 2038 	ldrb.w	r2, [r4, #56]	; 0x38
 8009722:	2a01      	cmp	r2, #1
 8009724:	d024      	beq.n	8009770 <HAL_UART_Transmit_DMA+0x64>
 8009726:	2201      	movs	r2, #1
    huart->ErrorCode = HAL_UART_ERROR_NONE;
 8009728:	2500      	movs	r5, #0
    __HAL_LOCK(huart);
 800972a:	f884 2038 	strb.w	r2, [r4, #56]	; 0x38
    huart->gState = HAL_UART_STATE_BUSY_TX;
 800972e:	2221      	movs	r2, #33	; 0x21
    huart->TxXferCount = Size;
 8009730:	84e3      	strh	r3, [r4, #38]	; 0x26
    huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
 8009732:	6b20      	ldr	r0, [r4, #48]	; 0x30
    huart->ErrorCode = HAL_UART_ERROR_NONE;
 8009734:	63e5      	str	r5, [r4, #60]	; 0x3c
    huart->gState = HAL_UART_STATE_BUSY_TX;
 8009736:	f884 2039 	strb.w	r2, [r4, #57]	; 0x39
    huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
 800973a:	4a0e      	ldr	r2, [pc, #56]	; (8009774 <HAL_UART_Transmit_DMA+0x68>)
    huart->TxXferSize = Size;
 800973c:	84a3      	strh	r3, [r4, #36]	; 0x24
    huart->pTxBuffPtr = pData;
 800973e:	6221      	str	r1, [r4, #32]
    huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
 8009740:	6282      	str	r2, [r0, #40]	; 0x28
    huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
 8009742:	4a0d      	ldr	r2, [pc, #52]	; (8009778 <HAL_UART_Transmit_DMA+0x6c>)
    huart->hdmatx->XferAbortCallback = NULL;
 8009744:	6345      	str	r5, [r0, #52]	; 0x34
    huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
 8009746:	62c2      	str	r2, [r0, #44]	; 0x2c
    huart->hdmatx->XferErrorCallback = UART_DMAError;
 8009748:	4a0c      	ldr	r2, [pc, #48]	; (800977c <HAL_UART_Transmit_DMA+0x70>)
 800974a:	6302      	str	r2, [r0, #48]	; 0x30
    HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t *)tmp, (uint32_t)&huart->Instance->DR, Size);
 800974c:	6822      	ldr	r2, [r4, #0]
 800974e:	3204      	adds	r2, #4
 8009750:	f7ff f816 	bl	8008780 <HAL_DMA_Start_IT>
    __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
 8009754:	f06f 0240 	mvn.w	r2, #64	; 0x40
 8009758:	6823      	ldr	r3, [r4, #0]
    return HAL_OK;
 800975a:	4628      	mov	r0, r5
    __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
 800975c:	601a      	str	r2, [r3, #0]
    SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
 800975e:	695a      	ldr	r2, [r3, #20]
    __HAL_UNLOCK(huart);
 8009760:	f884 5038 	strb.w	r5, [r4, #56]	; 0x38
    SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
 8009764:	f042 0280 	orr.w	r2, r2, #128	; 0x80
 8009768:	615a      	str	r2, [r3, #20]
    return HAL_OK;
 800976a:	bd38      	pop	{r3, r4, r5, pc}
      return HAL_ERROR;
 800976c:	2001      	movs	r0, #1
 800976e:	bd38      	pop	{r3, r4, r5, pc}
    return HAL_BUSY;
 8009770:	2002      	movs	r0, #2
}
 8009772:	bd38      	pop	{r3, r4, r5, pc}
 8009774:	08009813 	.word	0x08009813
 8009778:	08009841 	.word	0x08009841
 800977c:	0800990d 	.word	0x0800990d

08009780 <HAL_UART_Receive_DMA>:
{
 8009780:	4613      	mov	r3, r2
  if (huart->RxState == HAL_UART_STATE_READY)
 8009782:	f890 203a 	ldrb.w	r2, [r0, #58]	; 0x3a
{
 8009786:	b573      	push	{r0, r1, r4, r5, r6, lr}
  if (huart->RxState == HAL_UART_STATE_READY)
 8009788:	2a20      	cmp	r2, #32
{
 800978a:	4605      	mov	r5, r0
  if (huart->RxState == HAL_UART_STATE_READY)
 800978c:	d138      	bne.n	8009800 <HAL_UART_Receive_DMA+0x80>
    if ((pData == NULL) || (Size == 0U))
 800978e:	2900      	cmp	r1, #0
 8009790:	d034      	beq.n	80097fc <HAL_UART_Receive_DMA+0x7c>
 8009792:	2b00      	cmp	r3, #0
 8009794:	d032      	beq.n	80097fc <HAL_UART_Receive_DMA+0x7c>
    __HAL_LOCK(huart);
 8009796:	f890 2038 	ldrb.w	r2, [r0, #56]	; 0x38
 800979a:	2a01      	cmp	r2, #1
 800979c:	d030      	beq.n	8009800 <HAL_UART_Receive_DMA+0x80>
 800979e:	2201      	movs	r2, #1
    huart->ErrorCode = HAL_UART_ERROR_NONE;
 80097a0:	2400      	movs	r4, #0
    __HAL_LOCK(huart);
 80097a2:	f880 2038 	strb.w	r2, [r0, #56]	; 0x38
    huart->RxState = HAL_UART_STATE_BUSY_RX;
 80097a6:	2222      	movs	r2, #34	; 0x22
    huart->pRxBuffPtr = pData;
 80097a8:	6281      	str	r1, [r0, #40]	; 0x28
    huart->RxXferSize = Size;
 80097aa:	8583      	strh	r3, [r0, #44]	; 0x2c
    huart->ErrorCode = HAL_UART_ERROR_NONE;
 80097ac:	63c4      	str	r4, [r0, #60]	; 0x3c
    huart->RxState = HAL_UART_STATE_BUSY_RX;
 80097ae:	f880 203a 	strb.w	r2, [r0, #58]	; 0x3a
    huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
 80097b2:	6b40      	ldr	r0, [r0, #52]	; 0x34
 80097b4:	4a13      	ldr	r2, [pc, #76]	; (8009804 <HAL_UART_Receive_DMA+0x84>)
    HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t *)tmp, Size);
 80097b6:	682e      	ldr	r6, [r5, #0]
    huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
 80097b8:	6282      	str	r2, [r0, #40]	; 0x28
    huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
 80097ba:	4a13      	ldr	r2, [pc, #76]	; (8009808 <HAL_UART_Receive_DMA+0x88>)
    huart->hdmarx->XferAbortCallback = NULL;
 80097bc:	6344      	str	r4, [r0, #52]	; 0x34
    huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
 80097be:	62c2      	str	r2, [r0, #44]	; 0x2c
    huart->hdmarx->XferErrorCallback = UART_DMAError;
 80097c0:	4a12      	ldr	r2, [pc, #72]	; (800980c <HAL_UART_Receive_DMA+0x8c>)
 80097c2:	6302      	str	r2, [r0, #48]	; 0x30
    HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t *)tmp, Size);
 80097c4:	460a      	mov	r2, r1
 80097c6:	1d31      	adds	r1, r6, #4
 80097c8:	f7fe ffda 	bl	8008780 <HAL_DMA_Start_IT>
    return HAL_OK;
 80097cc:	4620      	mov	r0, r4
    __HAL_UART_CLEAR_OREFLAG(huart);
 80097ce:	682b      	ldr	r3, [r5, #0]
 80097d0:	9401      	str	r4, [sp, #4]
 80097d2:	681a      	ldr	r2, [r3, #0]
 80097d4:	9201      	str	r2, [sp, #4]
 80097d6:	685a      	ldr	r2, [r3, #4]
    __HAL_UNLOCK(huart);
 80097d8:	f885 4038 	strb.w	r4, [r5, #56]	; 0x38
    __HAL_UART_CLEAR_OREFLAG(huart);
 80097dc:	9201      	str	r2, [sp, #4]
 80097de:	9a01      	ldr	r2, [sp, #4]
    SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
 80097e0:	68da      	ldr	r2, [r3, #12]
 80097e2:	f442 7280 	orr.w	r2, r2, #256	; 0x100
 80097e6:	60da      	str	r2, [r3, #12]
    SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
 80097e8:	695a      	ldr	r2, [r3, #20]
 80097ea:	f042 0201 	orr.w	r2, r2, #1
 80097ee:	615a      	str	r2, [r3, #20]
    SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
 80097f0:	695a      	ldr	r2, [r3, #20]
 80097f2:	f042 0240 	orr.w	r2, r2, #64	; 0x40
 80097f6:	615a      	str	r2, [r3, #20]
}
 80097f8:	b002      	add	sp, #8
 80097fa:	bd70      	pop	{r4, r5, r6, pc}
      return HAL_ERROR;
 80097fc:	2001      	movs	r0, #1
 80097fe:	e7fb      	b.n	80097f8 <HAL_UART_Receive_DMA+0x78>
    return HAL_BUSY;
 8009800:	2002      	movs	r0, #2
 8009802:	e7f9      	b.n	80097f8 <HAL_UART_Receive_DMA+0x78>
 8009804:	0800984b 	.word	0x0800984b
 8009808:	08009901 	.word	0x08009901
 800980c:	0800990d 	.word	0x0800990d

08009810 <HAL_UART_TxCpltCallback>:
 8009810:	4770      	bx	lr

08009812 <UART_DMATransmitCplt>:
{
 8009812:	b508      	push	{r3, lr}
  if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
 8009814:	6803      	ldr	r3, [r0, #0]
  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 8009816:	6a42      	ldr	r2, [r0, #36]	; 0x24
  if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
 8009818:	681b      	ldr	r3, [r3, #0]
 800981a:	f013 0320 	ands.w	r3, r3, #32
 800981e:	d10a      	bne.n	8009836 <UART_DMATransmitCplt+0x24>
    huart->TxXferCount = 0x00U;
 8009820:	84d3      	strh	r3, [r2, #38]	; 0x26
    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
 8009822:	6813      	ldr	r3, [r2, #0]
 8009824:	695a      	ldr	r2, [r3, #20]
 8009826:	f022 0280 	bic.w	r2, r2, #128	; 0x80
 800982a:	615a      	str	r2, [r3, #20]
    SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
 800982c:	68da      	ldr	r2, [r3, #12]
 800982e:	f042 0240 	orr.w	r2, r2, #64	; 0x40
 8009832:	60da      	str	r2, [r3, #12]
 8009834:	bd08      	pop	{r3, pc}
    HAL_UART_TxCpltCallback(huart);
 8009836:	4610      	mov	r0, r2
 8009838:	f7ff ffea 	bl	8009810 <HAL_UART_TxCpltCallback>
 800983c:	bd08      	pop	{r3, pc}

0800983e <HAL_UART_TxHalfCpltCallback>:
 800983e:	4770      	bx	lr

08009840 <UART_DMATxHalfCplt>:
{
 8009840:	b508      	push	{r3, lr}
  HAL_UART_TxHalfCpltCallback(huart);
 8009842:	6a40      	ldr	r0, [r0, #36]	; 0x24
 8009844:	f7ff fffb 	bl	800983e <HAL_UART_TxHalfCpltCallback>
 8009848:	bd08      	pop	{r3, pc}

0800984a <UART_DMAReceiveCplt>:
{
 800984a:	b508      	push	{r3, lr}
  if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
 800984c:	6803      	ldr	r3, [r0, #0]
  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 800984e:	6a42      	ldr	r2, [r0, #36]	; 0x24
  if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
 8009850:	681b      	ldr	r3, [r3, #0]
 8009852:	f013 0320 	ands.w	r3, r3, #32
 8009856:	d110      	bne.n	800987a <UART_DMAReceiveCplt+0x30>
    huart->RxXferCount = 0U;
 8009858:	85d3      	strh	r3, [r2, #46]	; 0x2e
    CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
 800985a:	6813      	ldr	r3, [r2, #0]
 800985c:	68d9      	ldr	r1, [r3, #12]
 800985e:	f421 7180 	bic.w	r1, r1, #256	; 0x100
 8009862:	60d9      	str	r1, [r3, #12]
    CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 8009864:	6959      	ldr	r1, [r3, #20]
 8009866:	f021 0101 	bic.w	r1, r1, #1
 800986a:	6159      	str	r1, [r3, #20]
    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
 800986c:	6959      	ldr	r1, [r3, #20]
 800986e:	f021 0140 	bic.w	r1, r1, #64	; 0x40
 8009872:	6159      	str	r1, [r3, #20]
    huart->RxState = HAL_UART_STATE_READY;
 8009874:	2320      	movs	r3, #32
 8009876:	f882 303a 	strb.w	r3, [r2, #58]	; 0x3a
  HAL_UART_RxCpltCallback(huart);
 800987a:	4610      	mov	r0, r2
 800987c:	f000 fe10 	bl	800a4a0 <HAL_UART_RxCpltCallback>
 8009880:	bd08      	pop	{r3, pc}

08009882 <UART_Receive_IT>:
  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
 8009882:	f890 303a 	ldrb.w	r3, [r0, #58]	; 0x3a
{
 8009886:	b510      	push	{r4, lr}
  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
 8009888:	2b22      	cmp	r3, #34	; 0x22
 800988a:	d136      	bne.n	80098fa <UART_Receive_IT+0x78>
    if (huart->Init.WordLength == UART_WORDLENGTH_9B)
 800988c:	6883      	ldr	r3, [r0, #8]
 800988e:	6901      	ldr	r1, [r0, #16]
 8009890:	f5b3 5f80 	cmp.w	r3, #4096	; 0x1000
 8009894:	6802      	ldr	r2, [r0, #0]
 8009896:	6a83      	ldr	r3, [r0, #40]	; 0x28
 8009898:	d123      	bne.n	80098e2 <UART_Receive_IT+0x60>
        *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
 800989a:	6852      	ldr	r2, [r2, #4]
      if (huart->Init.Parity == UART_PARITY_NONE)
 800989c:	b9e9      	cbnz	r1, 80098da <UART_Receive_IT+0x58>
        *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
 800989e:	f3c2 0208 	ubfx	r2, r2, #0, #9
 80098a2:	f823 2b02 	strh.w	r2, [r3], #2
        huart->pRxBuffPtr += 1U;
 80098a6:	6283      	str	r3, [r0, #40]	; 0x28
    if (--huart->RxXferCount == 0U)
 80098a8:	8dc4      	ldrh	r4, [r0, #46]	; 0x2e
 80098aa:	3c01      	subs	r4, #1
 80098ac:	b2a4      	uxth	r4, r4
 80098ae:	85c4      	strh	r4, [r0, #46]	; 0x2e
 80098b0:	b98c      	cbnz	r4, 80098d6 <UART_Receive_IT+0x54>
      __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
 80098b2:	6803      	ldr	r3, [r0, #0]
 80098b4:	68da      	ldr	r2, [r3, #12]
 80098b6:	f022 0220 	bic.w	r2, r2, #32
 80098ba:	60da      	str	r2, [r3, #12]
      __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
 80098bc:	68da      	ldr	r2, [r3, #12]
 80098be:	f422 7280 	bic.w	r2, r2, #256	; 0x100
 80098c2:	60da      	str	r2, [r3, #12]
      __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
 80098c4:	695a      	ldr	r2, [r3, #20]
 80098c6:	f022 0201 	bic.w	r2, r2, #1
 80098ca:	615a      	str	r2, [r3, #20]
      huart->RxState = HAL_UART_STATE_READY;
 80098cc:	2320      	movs	r3, #32
 80098ce:	f880 303a 	strb.w	r3, [r0, #58]	; 0x3a
      HAL_UART_RxCpltCallback(huart);
 80098d2:	f000 fde5 	bl	800a4a0 <HAL_UART_RxCpltCallback>
    if (--huart->RxXferCount == 0U)
 80098d6:	2000      	movs	r0, #0
}
 80098d8:	bd10      	pop	{r4, pc}
        *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF);
 80098da:	b2d2      	uxtb	r2, r2
 80098dc:	f823 2b01 	strh.w	r2, [r3], #1
 80098e0:	e7e1      	b.n	80098a6 <UART_Receive_IT+0x24>
      if (huart->Init.Parity == UART_PARITY_NONE)
 80098e2:	b921      	cbnz	r1, 80098ee <UART_Receive_IT+0x6c>
        *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
 80098e4:	1c59      	adds	r1, r3, #1
 80098e6:	6852      	ldr	r2, [r2, #4]
 80098e8:	6281      	str	r1, [r0, #40]	; 0x28
        *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
 80098ea:	701a      	strb	r2, [r3, #0]
 80098ec:	e7dc      	b.n	80098a8 <UART_Receive_IT+0x26>
 80098ee:	6852      	ldr	r2, [r2, #4]
 80098f0:	1c59      	adds	r1, r3, #1
 80098f2:	6281      	str	r1, [r0, #40]	; 0x28
 80098f4:	f002 027f 	and.w	r2, r2, #127	; 0x7f
 80098f8:	e7f7      	b.n	80098ea <UART_Receive_IT+0x68>
    return HAL_BUSY;
 80098fa:	2002      	movs	r0, #2
 80098fc:	bd10      	pop	{r4, pc}

080098fe <HAL_UART_RxHalfCpltCallback>:
 80098fe:	4770      	bx	lr

08009900 <UART_DMARxHalfCplt>:
{
 8009900:	b508      	push	{r3, lr}
  HAL_UART_RxHalfCpltCallback(huart);
 8009902:	6a40      	ldr	r0, [r0, #36]	; 0x24
 8009904:	f7ff fffb 	bl	80098fe <HAL_UART_RxHalfCpltCallback>
 8009908:	bd08      	pop	{r3, pc}

0800990a <HAL_UART_ErrorCallback>:
 800990a:	4770      	bx	lr

0800990c <UART_DMAError>:
  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 800990c:	6a41      	ldr	r1, [r0, #36]	; 0x24
{
 800990e:	b508      	push	{r3, lr}
  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
 8009910:	680b      	ldr	r3, [r1, #0]
 8009912:	695a      	ldr	r2, [r3, #20]
  if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
 8009914:	f891 0039 	ldrb.w	r0, [r1, #57]	; 0x39
 8009918:	2821      	cmp	r0, #33	; 0x21
 800991a:	d10a      	bne.n	8009932 <UART_DMAError+0x26>
 800991c:	0612      	lsls	r2, r2, #24
 800991e:	d508      	bpl.n	8009932 <UART_DMAError+0x26>
    huart->TxXferCount = 0x00U;
 8009920:	2200      	movs	r2, #0
 8009922:	84ca      	strh	r2, [r1, #38]	; 0x26
  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
 8009924:	68da      	ldr	r2, [r3, #12]
 8009926:	f022 02c0 	bic.w	r2, r2, #192	; 0xc0
 800992a:	60da      	str	r2, [r3, #12]
  huart->gState = HAL_UART_STATE_READY;
 800992c:	2220      	movs	r2, #32
 800992e:	f881 2039 	strb.w	r2, [r1, #57]	; 0x39
  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
 8009932:	695b      	ldr	r3, [r3, #20]
  if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
 8009934:	f891 203a 	ldrb.w	r2, [r1, #58]	; 0x3a
 8009938:	2a22      	cmp	r2, #34	; 0x22
 800993a:	d106      	bne.n	800994a <UART_DMAError+0x3e>
 800993c:	065b      	lsls	r3, r3, #25
 800993e:	d504      	bpl.n	800994a <UART_DMAError+0x3e>
    huart->RxXferCount = 0x00U;
 8009940:	2300      	movs	r3, #0
    UART_EndRxTransfer(huart);
 8009942:	4608      	mov	r0, r1
    huart->RxXferCount = 0x00U;
 8009944:	85cb      	strh	r3, [r1, #46]	; 0x2e
    UART_EndRxTransfer(huart);
 8009946:	f7ff fde7 	bl	8009518 <UART_EndRxTransfer>
  huart->ErrorCode |= HAL_UART_ERROR_DMA;
 800994a:	6bcb      	ldr	r3, [r1, #60]	; 0x3c
  HAL_UART_ErrorCallback(huart);
 800994c:	4608      	mov	r0, r1
  huart->ErrorCode |= HAL_UART_ERROR_DMA;
 800994e:	f043 0310 	orr.w	r3, r3, #16
 8009952:	63cb      	str	r3, [r1, #60]	; 0x3c
  HAL_UART_ErrorCallback(huart);
 8009954:	f7ff ffd9 	bl	800990a <HAL_UART_ErrorCallback>
 8009958:	bd08      	pop	{r3, pc}
	...

0800995c <HAL_UART_IRQHandler>:
  uint32_t isrflags   = READ_REG(huart->Instance->SR);
 800995c:	6803      	ldr	r3, [r0, #0]
{
 800995e:	b570      	push	{r4, r5, r6, lr}
  uint32_t isrflags   = READ_REG(huart->Instance->SR);
 8009960:	681a      	ldr	r2, [r3, #0]
{
 8009962:	4604      	mov	r4, r0
  if (errorflags == RESET)
 8009964:	0716      	lsls	r6, r2, #28
  uint32_t cr1its     = READ_REG(huart->Instance->CR1);
 8009966:	68d9      	ldr	r1, [r3, #12]
  uint32_t cr3its     = READ_REG(huart->Instance->CR3);
 8009968:	695d      	ldr	r5, [r3, #20]
  if (errorflags == RESET)
 800996a:	d107      	bne.n	800997c <HAL_UART_IRQHandler+0x20>
    if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
 800996c:	0696      	lsls	r6, r2, #26
 800996e:	d55a      	bpl.n	8009a26 <HAL_UART_IRQHandler+0xca>
 8009970:	068d      	lsls	r5, r1, #26
 8009972:	d558      	bpl.n	8009a26 <HAL_UART_IRQHandler+0xca>
}
 8009974:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
      UART_Receive_IT(huart);
 8009978:	f7ff bf83 	b.w	8009882 <UART_Receive_IT>
  if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
 800997c:	f015 0501 	ands.w	r5, r5, #1
 8009980:	d102      	bne.n	8009988 <HAL_UART_IRQHandler+0x2c>
 8009982:	f411 7f90 	tst.w	r1, #288	; 0x120
 8009986:	d04e      	beq.n	8009a26 <HAL_UART_IRQHandler+0xca>
    if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
 8009988:	07d3      	lsls	r3, r2, #31
 800998a:	d505      	bpl.n	8009998 <HAL_UART_IRQHandler+0x3c>
 800998c:	05ce      	lsls	r6, r1, #23
      huart->ErrorCode |= HAL_UART_ERROR_PE;
 800998e:	bf42      	ittt	mi
 8009990:	6be3      	ldrmi	r3, [r4, #60]	; 0x3c
 8009992:	f043 0301 	orrmi.w	r3, r3, #1
 8009996:	63e3      	strmi	r3, [r4, #60]	; 0x3c
    if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
 8009998:	0750      	lsls	r0, r2, #29
 800999a:	d504      	bpl.n	80099a6 <HAL_UART_IRQHandler+0x4a>
 800999c:	b11d      	cbz	r5, 80099a6 <HAL_UART_IRQHandler+0x4a>
      huart->ErrorCode |= HAL_UART_ERROR_NE;
 800999e:	6be3      	ldr	r3, [r4, #60]	; 0x3c
 80099a0:	f043 0302 	orr.w	r3, r3, #2
 80099a4:	63e3      	str	r3, [r4, #60]	; 0x3c
    if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
 80099a6:	0793      	lsls	r3, r2, #30
 80099a8:	d504      	bpl.n	80099b4 <HAL_UART_IRQHandler+0x58>
 80099aa:	b11d      	cbz	r5, 80099b4 <HAL_UART_IRQHandler+0x58>
      huart->ErrorCode |= HAL_UART_ERROR_FE;
 80099ac:	6be3      	ldr	r3, [r4, #60]	; 0x3c
 80099ae:	f043 0304 	orr.w	r3, r3, #4
 80099b2:	63e3      	str	r3, [r4, #60]	; 0x3c
    if (((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
 80099b4:	0716      	lsls	r6, r2, #28
 80099b6:	d504      	bpl.n	80099c2 <HAL_UART_IRQHandler+0x66>
 80099b8:	b11d      	cbz	r5, 80099c2 <HAL_UART_IRQHandler+0x66>
      huart->ErrorCode |= HAL_UART_ERROR_ORE;
 80099ba:	6be3      	ldr	r3, [r4, #60]	; 0x3c
 80099bc:	f043 0308 	orr.w	r3, r3, #8
 80099c0:	63e3      	str	r3, [r4, #60]	; 0x3c
    if (huart->ErrorCode != HAL_UART_ERROR_NONE)
 80099c2:	6be3      	ldr	r3, [r4, #60]	; 0x3c
 80099c4:	2b00      	cmp	r3, #0
 80099c6:	d066      	beq.n	8009a96 <HAL_UART_IRQHandler+0x13a>
      if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
 80099c8:	0695      	lsls	r5, r2, #26
 80099ca:	d504      	bpl.n	80099d6 <HAL_UART_IRQHandler+0x7a>
 80099cc:	0688      	lsls	r0, r1, #26
 80099ce:	d502      	bpl.n	80099d6 <HAL_UART_IRQHandler+0x7a>
        UART_Receive_IT(huart);
 80099d0:	4620      	mov	r0, r4
 80099d2:	f7ff ff56 	bl	8009882 <UART_Receive_IT>
      dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
 80099d6:	6823      	ldr	r3, [r4, #0]
        UART_EndRxTransfer(huart);
 80099d8:	4620      	mov	r0, r4
      dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
 80099da:	695d      	ldr	r5, [r3, #20]
      if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest)
 80099dc:	6be2      	ldr	r2, [r4, #60]	; 0x3c
 80099de:	0711      	lsls	r1, r2, #28
 80099e0:	d402      	bmi.n	80099e8 <HAL_UART_IRQHandler+0x8c>
 80099e2:	f015 0540 	ands.w	r5, r5, #64	; 0x40
 80099e6:	d01a      	beq.n	8009a1e <HAL_UART_IRQHandler+0xc2>
        UART_EndRxTransfer(huart);
 80099e8:	f7ff fd96 	bl	8009518 <UART_EndRxTransfer>
        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
 80099ec:	6823      	ldr	r3, [r4, #0]
 80099ee:	695a      	ldr	r2, [r3, #20]
 80099f0:	0652      	lsls	r2, r2, #25
 80099f2:	d510      	bpl.n	8009a16 <HAL_UART_IRQHandler+0xba>
          CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
 80099f4:	695a      	ldr	r2, [r3, #20]
          if (huart->hdmarx != NULL)
 80099f6:	6b60      	ldr	r0, [r4, #52]	; 0x34
          CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
 80099f8:	f022 0240 	bic.w	r2, r2, #64	; 0x40
 80099fc:	615a      	str	r2, [r3, #20]
          if (huart->hdmarx != NULL)
 80099fe:	b150      	cbz	r0, 8009a16 <HAL_UART_IRQHandler+0xba>
            huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
 8009a00:	4b25      	ldr	r3, [pc, #148]	; (8009a98 <HAL_UART_IRQHandler+0x13c>)
 8009a02:	6343      	str	r3, [r0, #52]	; 0x34
            if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
 8009a04:	f7fe fefa 	bl	80087fc <HAL_DMA_Abort_IT>
 8009a08:	2800      	cmp	r0, #0
 8009a0a:	d044      	beq.n	8009a96 <HAL_UART_IRQHandler+0x13a>
              huart->hdmarx->XferAbortCallback(huart->hdmarx);
 8009a0c:	6b60      	ldr	r0, [r4, #52]	; 0x34
}
 8009a0e:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
              huart->hdmarx->XferAbortCallback(huart->hdmarx);
 8009a12:	6b43      	ldr	r3, [r0, #52]	; 0x34
 8009a14:	4718      	bx	r3
            HAL_UART_ErrorCallback(huart);
 8009a16:	4620      	mov	r0, r4
 8009a18:	f7ff ff77 	bl	800990a <HAL_UART_ErrorCallback>
 8009a1c:	bd70      	pop	{r4, r5, r6, pc}
        HAL_UART_ErrorCallback(huart);
 8009a1e:	f7ff ff74 	bl	800990a <HAL_UART_ErrorCallback>
        huart->ErrorCode = HAL_UART_ERROR_NONE;
 8009a22:	63e5      	str	r5, [r4, #60]	; 0x3c
 8009a24:	bd70      	pop	{r4, r5, r6, pc}
  if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
 8009a26:	0616      	lsls	r6, r2, #24
 8009a28:	d527      	bpl.n	8009a7a <HAL_UART_IRQHandler+0x11e>
 8009a2a:	060d      	lsls	r5, r1, #24
 8009a2c:	d525      	bpl.n	8009a7a <HAL_UART_IRQHandler+0x11e>
  if (huart->gState == HAL_UART_STATE_BUSY_TX)
 8009a2e:	f894 2039 	ldrb.w	r2, [r4, #57]	; 0x39
 8009a32:	2a21      	cmp	r2, #33	; 0x21
 8009a34:	d12f      	bne.n	8009a96 <HAL_UART_IRQHandler+0x13a>
    if (huart->Init.WordLength == UART_WORDLENGTH_9B)
 8009a36:	68a2      	ldr	r2, [r4, #8]
 8009a38:	f5b2 5f80 	cmp.w	r2, #4096	; 0x1000
 8009a3c:	6a22      	ldr	r2, [r4, #32]
 8009a3e:	d117      	bne.n	8009a70 <HAL_UART_IRQHandler+0x114>
      huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
 8009a40:	8811      	ldrh	r1, [r2, #0]
 8009a42:	f3c1 0108 	ubfx	r1, r1, #0, #9
 8009a46:	6059      	str	r1, [r3, #4]
      if (huart->Init.Parity == UART_PARITY_NONE)
 8009a48:	6921      	ldr	r1, [r4, #16]
 8009a4a:	b979      	cbnz	r1, 8009a6c <HAL_UART_IRQHandler+0x110>
        huart->pTxBuffPtr += 2U;
 8009a4c:	3202      	adds	r2, #2
        huart->pTxBuffPtr += 1U;
 8009a4e:	6222      	str	r2, [r4, #32]
    if (--huart->TxXferCount == 0U)
 8009a50:	8ce2      	ldrh	r2, [r4, #38]	; 0x26
 8009a52:	3a01      	subs	r2, #1
 8009a54:	b292      	uxth	r2, r2
 8009a56:	84e2      	strh	r2, [r4, #38]	; 0x26
 8009a58:	b9ea      	cbnz	r2, 8009a96 <HAL_UART_IRQHandler+0x13a>
      __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
 8009a5a:	68da      	ldr	r2, [r3, #12]
 8009a5c:	f022 0280 	bic.w	r2, r2, #128	; 0x80
 8009a60:	60da      	str	r2, [r3, #12]
      __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
 8009a62:	68da      	ldr	r2, [r3, #12]
 8009a64:	f042 0240 	orr.w	r2, r2, #64	; 0x40
 8009a68:	60da      	str	r2, [r3, #12]
 8009a6a:	bd70      	pop	{r4, r5, r6, pc}
        huart->pTxBuffPtr += 1U;
 8009a6c:	3201      	adds	r2, #1
 8009a6e:	e7ee      	b.n	8009a4e <HAL_UART_IRQHandler+0xf2>
      huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF);
 8009a70:	1c51      	adds	r1, r2, #1
 8009a72:	6221      	str	r1, [r4, #32]
 8009a74:	7812      	ldrb	r2, [r2, #0]
 8009a76:	605a      	str	r2, [r3, #4]
 8009a78:	e7ea      	b.n	8009a50 <HAL_UART_IRQHandler+0xf4>
  if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
 8009a7a:	0650      	lsls	r0, r2, #25
 8009a7c:	d50b      	bpl.n	8009a96 <HAL_UART_IRQHandler+0x13a>
 8009a7e:	064a      	lsls	r2, r1, #25
 8009a80:	d509      	bpl.n	8009a96 <HAL_UART_IRQHandler+0x13a>
  __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
 8009a82:	68da      	ldr	r2, [r3, #12]
  HAL_UART_TxCpltCallback(huart);
 8009a84:	4620      	mov	r0, r4
  __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
 8009a86:	f022 0240 	bic.w	r2, r2, #64	; 0x40
 8009a8a:	60da      	str	r2, [r3, #12]
  huart->gState = HAL_UART_STATE_READY;
 8009a8c:	2320      	movs	r3, #32
 8009a8e:	f884 3039 	strb.w	r3, [r4, #57]	; 0x39
  HAL_UART_TxCpltCallback(huart);
 8009a92:	f7ff febd 	bl	8009810 <HAL_UART_TxCpltCallback>
 8009a96:	bd70      	pop	{r4, r5, r6, pc}
 8009a98:	08009a9d 	.word	0x08009a9d

08009a9c <UART_DMAAbortOnError>:
{
 8009a9c:	b508      	push	{r3, lr}
  huart->RxXferCount = 0x00U;
 8009a9e:	2300      	movs	r3, #0
  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 8009aa0:	6a40      	ldr	r0, [r0, #36]	; 0x24
  huart->RxXferCount = 0x00U;
 8009aa2:	85c3      	strh	r3, [r0, #46]	; 0x2e
  huart->TxXferCount = 0x00U;
 8009aa4:	84c3      	strh	r3, [r0, #38]	; 0x26
  HAL_UART_ErrorCallback(huart);
 8009aa6:	f7ff ff30 	bl	800990a <HAL_UART_ErrorCallback>
 8009aaa:	bd08      	pop	{r3, pc}

08009aac <CRC16_Generate>:
{
	uint8_t dt = 0U;
	uint16_t crc16 = 0U;

	len *= 8;
	for(crc16 = (uint16_t)0x0000; len >= 8; len -= 8, buf_ptr++)
 8009aac:	2300      	movs	r3, #0
{
 8009aae:	b510      	push	{r4, lr}
	{
		crc16 = (uint16_t)(Table_CRC16[(crc16>>8) ^ (uint16_t)(*buf_ptr)] ^ (crc16<<8));
 8009ab0:	4c0f      	ldr	r4, [pc, #60]	; (8009af0 <CRC16_Generate+0x44>)
	len *= 8;
 8009ab2:	00c9      	lsls	r1, r1, #3
	for(crc16 = (uint16_t)0x0000; len >= 8; len -= 8, buf_ptr++)
 8009ab4:	2907      	cmp	r1, #7
 8009ab6:	dc0f      	bgt.n	8009ad8 <CRC16_Generate+0x2c>
	}

	if(len != 0)
 8009ab8:	b161      	cbz	r1, 8009ad4 <CRC16_Generate+0x28>
			len--;

			if(((crc16^dt) & ((uint16_t)1 << 15)) != 0)
			{
				crc16 =  (uint16_t)(crc16 << 1);
				crc16 = (uint16_t)(crc16 ^ 0x1021);
 8009aba:	f241 0221 	movw	r2, #4129	; 0x1021
			if(((crc16^dt) & ((uint16_t)1 << 15)) != 0)
 8009abe:	f413 4f00 	tst.w	r3, #32768	; 0x8000
 8009ac2:	ea4f 0343 	mov.w	r3, r3, lsl #1
				crc16 =  (uint16_t)(crc16 << 1);
 8009ac6:	b29b      	uxth	r3, r3
			len--;
 8009ac8:	f101 31ff 	add.w	r1, r1, #4294967295
				crc16 = (uint16_t)(crc16 ^ 0x1021);
 8009acc:	bf18      	it	ne
 8009ace:	4053      	eorne	r3, r2
		while(len != 0)
 8009ad0:	2900      	cmp	r1, #0
 8009ad2:	d1f4      	bne.n	8009abe <CRC16_Generate+0x12>
			}
			dt = (uint8_t)(dt << 1);
		}
	}
	return(crc16);
}
 8009ad4:	4618      	mov	r0, r3
 8009ad6:	bd10      	pop	{r4, pc}
		crc16 = (uint16_t)(Table_CRC16[(crc16>>8) ^ (uint16_t)(*buf_ptr)] ^ (crc16<<8));
 8009ad8:	f810 2b01 	ldrb.w	r2, [r0], #1
	for(crc16 = (uint16_t)0x0000; len >= 8; len -= 8, buf_ptr++)
 8009adc:	3908      	subs	r1, #8
		crc16 = (uint16_t)(Table_CRC16[(crc16>>8) ^ (uint16_t)(*buf_ptr)] ^ (crc16<<8));
 8009ade:	ea82 2213 	eor.w	r2, r2, r3, lsr #8
 8009ae2:	f834 2012 	ldrh.w	r2, [r4, r2, lsl #1]
 8009ae6:	ea82 2303 	eor.w	r3, r2, r3, lsl #8
 8009aea:	b29b      	uxth	r3, r3
 8009aec:	e7e2      	b.n	8009ab4 <CRC16_Generate+0x8>
 8009aee:	bf00      	nop
 8009af0:	20000008 	.word	0x20000008

08009af4 <ESP8266_Strindex>:
uint8_t ESP8266_Strindex(uint8_t* str){
    uint8_t val = 0;
    val = sizeof(str) - 1;

    return val;
}
 8009af4:	2003      	movs	r0, #3
 8009af6:	4770      	bx	lr

08009af8 <HAL_TIM_PeriodElapsedCallback>:
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{

    if(htim->Instance == TIM6){
 8009af8:	6802      	ldr	r2, [r0, #0]
 8009afa:	4b08      	ldr	r3, [pc, #32]	; (8009b1c <HAL_TIM_PeriodElapsedCallback+0x24>)
 8009afc:	429a      	cmp	r2, r3
 8009afe:	d10b      	bne.n	8009b18 <HAL_TIM_PeriodElapsedCallback+0x20>
        UartTimerCnt++;
 8009b00:	4a07      	ldr	r2, [pc, #28]	; (8009b20 <HAL_TIM_PeriodElapsedCallback+0x28>)
 8009b02:	6813      	ldr	r3, [r2, #0]
 8009b04:	3301      	adds	r3, #1
 8009b06:	6013      	str	r3, [r2, #0]
        LedTimerCnt++;
 8009b08:	4a06      	ldr	r2, [pc, #24]	; (8009b24 <HAL_TIM_PeriodElapsedCallback+0x2c>)
 8009b0a:	6813      	ldr	r3, [r2, #0]
 8009b0c:	3301      	adds	r3, #1
 8009b0e:	6013      	str	r3, [r2, #0]
        FirmwareTimerCnt++;
 8009b10:	4a05      	ldr	r2, [pc, #20]	; (8009b28 <HAL_TIM_PeriodElapsedCallback+0x30>)
 8009b12:	6813      	ldr	r3, [r2, #0]
 8009b14:	3301      	adds	r3, #1
 8009b16:	6013      	str	r3, [r2, #0]
 8009b18:	4770      	bx	lr
 8009b1a:	bf00      	nop
 8009b1c:	40001000 	.word	0x40001000
 8009b20:	20000294 	.word	0x20000294
 8009b24:	20000290 	.word	0x20000290
 8009b28:	2000028c 	.word	0x2000028c

08009b2c <_write>:
    }
}
int _write (int file, uint8_t *ptr, uint16_t len)
{
 8009b2c:	b510      	push	{r4, lr}
 8009b2e:	4614      	mov	r4, r2
    HAL_UART_Transmit (&huart1, ptr, len, 10);
 8009b30:	230a      	movs	r3, #10
 8009b32:	4802      	ldr	r0, [pc, #8]	; (8009b3c <_write+0x10>)
 8009b34:	f7ff fd8e 	bl	8009654 <HAL_UART_Transmit>
    return len;
}
 8009b38:	4620      	mov	r0, r4
 8009b3a:	bd10      	pop	{r4, pc}
 8009b3c:	20000448 	.word	0x20000448

08009b40 <SystemClock_Config>:
/**
  * @brief System Clock Configuration
  * @retval None
  */
void SystemClock_Config(void)
{
 8009b40:	b510      	push	{r4, lr}
 8009b42:	b096      	sub	sp, #88	; 0x58
  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
 8009b44:	2228      	movs	r2, #40	; 0x28
 8009b46:	2100      	movs	r1, #0
 8009b48:	a80c      	add	r0, sp, #48	; 0x30
 8009b4a:	f000 fd19 	bl	800a580 <memset>
  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 8009b4e:	2214      	movs	r2, #20
 8009b50:	2100      	movs	r1, #0
 8009b52:	a801      	add	r0, sp, #4
 8009b54:	f000 fd14 	bl	800a580 <memset>
  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 8009b58:	2218      	movs	r2, #24
 8009b5a:	2100      	movs	r1, #0
 8009b5c:	eb0d 0002 	add.w	r0, sp, r2
 8009b60:	f000 fd0e 	bl	800a580 <memset>

  /** Initializes the CPU, AHB and APB busses clocks 
  */
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
 8009b64:	2301      	movs	r3, #1
 8009b66:	9310      	str	r3, [sp, #64]	; 0x40
  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
 8009b68:	2310      	movs	r3, #16
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
 8009b6a:	2402      	movs	r4, #2
  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
 8009b6c:	9311      	str	r3, [sp, #68]	; 0x44
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2;
  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16;
 8009b6e:	f44f 1360 	mov.w	r3, #3670016	; 0x380000
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 8009b72:	a80c      	add	r0, sp, #48	; 0x30
  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16;
 8009b74:	9315      	str	r3, [sp, #84]	; 0x54
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
 8009b76:	940c      	str	r4, [sp, #48]	; 0x30
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
 8009b78:	9413      	str	r4, [sp, #76]	; 0x4c
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 8009b7a:	f7ff f881 	bl	8008c80 <HAL_RCC_OscConfig>
  {
    Error_Handler();
  }
  /** Initializes the CPU, AHB and APB busses clocks 
  */
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
 8009b7e:	230f      	movs	r3, #15
                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
 8009b80:	f44f 6280 	mov.w	r2, #1024	; 0x400
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
 8009b84:	9301      	str	r3, [sp, #4]
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
 8009b86:	2300      	movs	r3, #0
  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;

  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
 8009b88:	4621      	mov	r1, r4
 8009b8a:	a801      	add	r0, sp, #4
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
 8009b8c:	9303      	str	r3, [sp, #12]
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
 8009b8e:	9204      	str	r2, [sp, #16]
  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
 8009b90:	9305      	str	r3, [sp, #20]
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
 8009b92:	9402      	str	r4, [sp, #8]
  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
 8009b94:	f7ff fa4e 	bl	8009034 <HAL_RCC_ClockConfig>
  {
    Error_Handler();
  }
  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
  PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6;
 8009b98:	f44f 4300 	mov.w	r3, #32768	; 0x8000
  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
 8009b9c:	a806      	add	r0, sp, #24
  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
 8009b9e:	9406      	str	r4, [sp, #24]
  PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6;
 8009ba0:	9308      	str	r3, [sp, #32]
  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
 8009ba2:	f7ff fb05 	bl	80091b0 <HAL_RCCEx_PeriphCLKConfig>
  {
    Error_Handler();
  }
}
 8009ba6:	b016      	add	sp, #88	; 0x58
 8009ba8:	bd10      	pop	{r4, pc}
	...

08009bac <main>:
{
 8009bac:	b580      	push	{r7, lr}
	uint8_t tempdata[] = {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A};
 8009bae:	4ab7      	ldr	r2, [pc, #732]	; (8009e8c <main+0x2e0>)
{
 8009bb0:	b08c      	sub	sp, #48	; 0x30
	uint8_t tempdata[] = {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A};
 8009bb2:	6851      	ldr	r1, [r2, #4]
 8009bb4:	6810      	ldr	r0, [r2, #0]
 8009bb6:	ab05      	add	r3, sp, #20
 8009bb8:	c303      	stmia	r3!, {r0, r1}
 8009bba:	8911      	ldrh	r1, [r2, #8]
 8009bbc:	7a92      	ldrb	r2, [r2, #10]
static void MX_GPIO_Init(void)
{
  GPIO_InitTypeDef GPIO_InitStruct = {0};

  /* GPIO Ports Clock Enable */
  __HAL_RCC_GPIOC_CLK_ENABLE();
 8009bbe:	4db4      	ldr	r5, [pc, #720]	; (8009e90 <main+0x2e4>)
	uint8_t tempdata[] = {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A};
 8009bc0:	8019      	strh	r1, [r3, #0]
 8009bc2:	709a      	strb	r2, [r3, #2]
  HAL_Init();
 8009bc4:	f7fe fb52 	bl	800826c <HAL_Init>
  SystemClock_Config();
 8009bc8:	f7ff ffba 	bl	8009b40 <SystemClock_Config>
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8009bcc:	2210      	movs	r2, #16
 8009bce:	2100      	movs	r1, #0
 8009bd0:	a808      	add	r0, sp, #32
 8009bd2:	f000 fcd5 	bl	800a580 <memset>
  __HAL_RCC_GPIOC_CLK_ENABLE();
 8009bd6:	69ab      	ldr	r3, [r5, #24]
  __HAL_RCC_GPIOA_CLK_ENABLE();
  __HAL_RCC_GPIOB_CLK_ENABLE();
  __HAL_RCC_GPIOD_CLK_ENABLE();

  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(GPIOC, BOOT_LED_Pin|PLL_LD_B_Pin|PLL_EN_B_Pin, GPIO_PIN_RESET);
 8009bd8:	2200      	movs	r2, #0
  __HAL_RCC_GPIOC_CLK_ENABLE();
 8009bda:	f043 0310 	orr.w	r3, r3, #16
 8009bde:	61ab      	str	r3, [r5, #24]
 8009be0:	69ab      	ldr	r3, [r5, #24]
  HAL_GPIO_WritePin(GPIOC, BOOT_LED_Pin|PLL_LD_B_Pin|PLL_EN_B_Pin, GPIO_PIN_RESET);
 8009be2:	f249 0140 	movw	r1, #36928	; 0x9040
  __HAL_RCC_GPIOC_CLK_ENABLE();
 8009be6:	f003 0310 	and.w	r3, r3, #16
 8009bea:	9301      	str	r3, [sp, #4]
 8009bec:	9b01      	ldr	r3, [sp, #4]
  __HAL_RCC_GPIOA_CLK_ENABLE();
 8009bee:	69ab      	ldr	r3, [r5, #24]
  HAL_GPIO_WritePin(GPIOC, BOOT_LED_Pin|PLL_LD_B_Pin|PLL_EN_B_Pin, GPIO_PIN_RESET);
 8009bf0:	48a8      	ldr	r0, [pc, #672]	; (8009e94 <main+0x2e8>)
  __HAL_RCC_GPIOA_CLK_ENABLE();
 8009bf2:	f043 0304 	orr.w	r3, r3, #4
 8009bf6:	61ab      	str	r3, [r5, #24]
 8009bf8:	69ab      	ldr	r3, [r5, #24]
  HAL_GPIO_WritePin(ATT_CLK_B_GPIO_Port, ATT_CLK_B_Pin, GPIO_PIN_RESET);

  /*Configure GPIO pins : BOOT_LED_Pin PLL_LD_B_Pin PLL_EN_B_Pin */
  GPIO_InitStruct.Pin = BOOT_LED_Pin|PLL_LD_B_Pin|PLL_EN_B_Pin;
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8009bfa:	2400      	movs	r4, #0
  __HAL_RCC_GPIOA_CLK_ENABLE();
 8009bfc:	f003 0304 	and.w	r3, r3, #4
 8009c00:	9302      	str	r3, [sp, #8]
 8009c02:	9b02      	ldr	r3, [sp, #8]
  __HAL_RCC_GPIOB_CLK_ENABLE();
 8009c04:	69ab      	ldr	r3, [r5, #24]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 8009c06:	2601      	movs	r6, #1
  __HAL_RCC_GPIOB_CLK_ENABLE();
 8009c08:	f043 0308 	orr.w	r3, r3, #8
 8009c0c:	61ab      	str	r3, [r5, #24]
 8009c0e:	69ab      	ldr	r3, [r5, #24]
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8009c10:	2702      	movs	r7, #2
  __HAL_RCC_GPIOB_CLK_ENABLE();
 8009c12:	f003 0308 	and.w	r3, r3, #8
 8009c16:	9303      	str	r3, [sp, #12]
 8009c18:	9b03      	ldr	r3, [sp, #12]
  __HAL_RCC_GPIOD_CLK_ENABLE();
 8009c1a:	69ab      	ldr	r3, [r5, #24]
  sConfig.Channel = ADC_CHANNEL_9;
 8009c1c:	f04f 0909 	mov.w	r9, #9
  __HAL_RCC_GPIOD_CLK_ENABLE();
 8009c20:	f043 0320 	orr.w	r3, r3, #32
 8009c24:	61ab      	str	r3, [r5, #24]
 8009c26:	69ab      	ldr	r3, [r5, #24]
  sConfig.Channel = ADC_CHANNEL_11;
 8009c28:	f04f 080b 	mov.w	r8, #11
  __HAL_RCC_GPIOD_CLK_ENABLE();
 8009c2c:	f003 0320 	and.w	r3, r3, #32
 8009c30:	9304      	str	r3, [sp, #16]
 8009c32:	9b04      	ldr	r3, [sp, #16]
  HAL_GPIO_WritePin(GPIOC, BOOT_LED_Pin|PLL_LD_B_Pin|PLL_EN_B_Pin, GPIO_PIN_RESET);
 8009c34:	f7ff f818 	bl	8008c68 <HAL_GPIO_WritePin>
  HAL_GPIO_WritePin(GPIOA, LED_UL_G_B_Pin|LED_SD_R_B_Pin|PWR_LED_B_Pin|LED_DL_G_B_Pin 
 8009c38:	2200      	movs	r2, #0
 8009c3a:	f24e 01f2 	movw	r1, #57586	; 0xe0f2
 8009c3e:	4896      	ldr	r0, [pc, #600]	; (8009e98 <main+0x2ec>)
 8009c40:	f7ff f812 	bl	8008c68 <HAL_GPIO_WritePin>
  HAL_GPIO_WritePin(GPIOB, RST_WIFI_B_Pin|PA_EN_B_Pin|EXT_PA_EN_B_Pin|PLL_CLK_B_Pin 
 8009c44:	2200      	movs	r2, #0
 8009c46:	f248 01d8 	movw	r1, #32984	; 0x80d8
 8009c4a:	4894      	ldr	r0, [pc, #592]	; (8009e9c <main+0x2f0>)
 8009c4c:	f7ff f80c 	bl	8008c68 <HAL_GPIO_WritePin>
  HAL_GPIO_WritePin(ATT_CLK_B_GPIO_Port, ATT_CLK_B_Pin, GPIO_PIN_RESET);
 8009c50:	2200      	movs	r2, #0
 8009c52:	2104      	movs	r1, #4
 8009c54:	4892      	ldr	r0, [pc, #584]	; (8009ea0 <main+0x2f4>)
 8009c56:	f7ff f807 	bl	8008c68 <HAL_GPIO_WritePin>
  GPIO_InitStruct.Pin = BOOT_LED_Pin|PLL_LD_B_Pin|PLL_EN_B_Pin;
 8009c5a:	f249 0340 	movw	r3, #36928	; 0x9040
  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 8009c5e:	a908      	add	r1, sp, #32
 8009c60:	488c      	ldr	r0, [pc, #560]	; (8009e94 <main+0x2e8>)
  GPIO_InitStruct.Pin = BOOT_LED_Pin|PLL_LD_B_Pin|PLL_EN_B_Pin;
 8009c62:	9308      	str	r3, [sp, #32]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 8009c64:	9609      	str	r6, [sp, #36]	; 0x24
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8009c66:	940a      	str	r4, [sp, #40]	; 0x28
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8009c68:	970b      	str	r7, [sp, #44]	; 0x2c
  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 8009c6a:	f7fe ff11 	bl	8008a90 <HAL_GPIO_Init>

  /*Configure GPIO pins : LED_UL_G_B_Pin LED_SD_R_B_Pin PWR_LED_B_Pin LED_DL_G_B_Pin 
                           LED_DL_R_B_Pin ATT_DATA_B_Pin ATT_EN1_B_Pin ATT_EN2_B_Pin */
  GPIO_InitStruct.Pin = LED_UL_G_B_Pin|LED_SD_R_B_Pin|PWR_LED_B_Pin|LED_DL_G_B_Pin 
 8009c6e:	f24e 03f2 	movw	r3, #57586	; 0xe0f2
                          |LED_DL_R_B_Pin|ATT_DATA_B_Pin|ATT_EN1_B_Pin|ATT_EN2_B_Pin;
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  GPIO_InitStruct.Pull = GPIO_NOPULL;
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8009c72:	a908      	add	r1, sp, #32
 8009c74:	4888      	ldr	r0, [pc, #544]	; (8009e98 <main+0x2ec>)
  GPIO_InitStruct.Pin = LED_UL_G_B_Pin|LED_SD_R_B_Pin|PWR_LED_B_Pin|LED_DL_G_B_Pin 
 8009c76:	9308      	str	r3, [sp, #32]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 8009c78:	9609      	str	r6, [sp, #36]	; 0x24
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8009c7a:	940a      	str	r4, [sp, #40]	; 0x28
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8009c7c:	970b      	str	r7, [sp, #44]	; 0x2c
  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8009c7e:	f7fe ff07 	bl	8008a90 <HAL_GPIO_Init>

  /*Configure GPIO pins : RST_WIFI_B_Pin PA_EN_B_Pin EXT_PA_EN_B_Pin PLL_CLK_B_Pin 
                           PLL_DATA_B_Pin */
  GPIO_InitStruct.Pin = RST_WIFI_B_Pin|PA_EN_B_Pin|EXT_PA_EN_B_Pin|PLL_CLK_B_Pin 
 8009c82:	f248 03d8 	movw	r3, #32984	; 0x80d8
                          |PLL_DATA_B_Pin;
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  GPIO_InitStruct.Pull = GPIO_NOPULL;
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8009c86:	a908      	add	r1, sp, #32
 8009c88:	4884      	ldr	r0, [pc, #528]	; (8009e9c <main+0x2f0>)
  GPIO_InitStruct.Pin = RST_WIFI_B_Pin|PA_EN_B_Pin|EXT_PA_EN_B_Pin|PLL_CLK_B_Pin 
 8009c8a:	9308      	str	r3, [sp, #32]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 8009c8c:	9609      	str	r6, [sp, #36]	; 0x24
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8009c8e:	940a      	str	r4, [sp, #40]	; 0x28
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8009c90:	970b      	str	r7, [sp, #44]	; 0x2c
  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8009c92:	f7fe fefd 	bl	8008a90 <HAL_GPIO_Init>

  /*Configure GPIO pin : ATT_CLK_B_Pin */
  GPIO_InitStruct.Pin = ATT_CLK_B_Pin;
 8009c96:	2304      	movs	r3, #4
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  GPIO_InitStruct.Pull = GPIO_NOPULL;
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8009c98:	970b      	str	r7, [sp, #44]	; 0x2c
  hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
 8009c9a:	f44f 2760 	mov.w	r7, #917504	; 0xe0000
  HAL_GPIO_Init(ATT_CLK_B_GPIO_Port, &GPIO_InitStruct);
 8009c9e:	a908      	add	r1, sp, #32
 8009ca0:	487f      	ldr	r0, [pc, #508]	; (8009ea0 <main+0x2f4>)
  GPIO_InitStruct.Pin = ATT_CLK_B_Pin;
 8009ca2:	9308      	str	r3, [sp, #32]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 8009ca4:	9609      	str	r6, [sp, #36]	; 0x24
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8009ca6:	940a      	str	r4, [sp, #40]	; 0x28
  HAL_GPIO_Init(ATT_CLK_B_GPIO_Port, &GPIO_InitStruct);
 8009ca8:	f7fe fef2 	bl	8008a90 <HAL_GPIO_Init>
  __HAL_RCC_DMA1_CLK_ENABLE();
 8009cac:	696b      	ldr	r3, [r5, #20]
  HAL_NVIC_SetPriority(DMA1_Channel7_IRQn, 0, 0);
 8009cae:	4622      	mov	r2, r4
  __HAL_RCC_DMA1_CLK_ENABLE();
 8009cb0:	4333      	orrs	r3, r6
 8009cb2:	616b      	str	r3, [r5, #20]
 8009cb4:	696b      	ldr	r3, [r5, #20]
  HAL_NVIC_SetPriority(DMA1_Channel7_IRQn, 0, 0);
 8009cb6:	4621      	mov	r1, r4
  __HAL_RCC_DMA1_CLK_ENABLE();
 8009cb8:	4033      	ands	r3, r6
 8009cba:	9300      	str	r3, [sp, #0]
  HAL_NVIC_SetPriority(DMA1_Channel7_IRQn, 0, 0);
 8009cbc:	2011      	movs	r0, #17
  hadc1.Instance = ADC1;
 8009cbe:	4d79      	ldr	r5, [pc, #484]	; (8009ea4 <main+0x2f8>)
  __HAL_RCC_DMA1_CLK_ENABLE();
 8009cc0:	9b00      	ldr	r3, [sp, #0]
  HAL_NVIC_SetPriority(DMA1_Channel7_IRQn, 0, 0);
 8009cc2:	f7fe fcc5 	bl	8008650 <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(DMA1_Channel7_IRQn);
 8009cc6:	2011      	movs	r0, #17
 8009cc8:	f7fe fcf6 	bl	80086b8 <HAL_NVIC_EnableIRQ>
  hadc1.Instance = ADC1;
 8009ccc:	4b76      	ldr	r3, [pc, #472]	; (8009ea8 <main+0x2fc>)
  if (HAL_ADC_Init(&hadc1) != HAL_OK)
 8009cce:	4628      	mov	r0, r5
  hadc1.Instance = ADC1;
 8009cd0:	602b      	str	r3, [r5, #0]
  hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
 8009cd2:	60ac      	str	r4, [r5, #8]
  hadc1.Init.ContinuousConvMode = DISABLE;
 8009cd4:	732c      	strb	r4, [r5, #12]
  hadc1.Init.DiscontinuousConvMode = DISABLE;
 8009cd6:	752c      	strb	r4, [r5, #20]
  hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
 8009cd8:	61ef      	str	r7, [r5, #28]
  hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
 8009cda:	606c      	str	r4, [r5, #4]
  hadc1.Init.NbrOfConversion = 1;
 8009cdc:	612e      	str	r6, [r5, #16]
  ADC_ChannelConfTypeDef sConfig = {0};
 8009cde:	9408      	str	r4, [sp, #32]
 8009ce0:	9409      	str	r4, [sp, #36]	; 0x24
 8009ce2:	940a      	str	r4, [sp, #40]	; 0x28
  if (HAL_ADC_Init(&hadc1) != HAL_OK)
 8009ce4:	f7fe fc16 	bl	8008514 <HAL_ADC_Init>
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8009ce8:	a908      	add	r1, sp, #32
 8009cea:	4628      	mov	r0, r5
  hadc2.Instance = ADC2;
 8009cec:	4d6f      	ldr	r5, [pc, #444]	; (8009eac <main+0x300>)
  sConfig.Channel = ADC_CHANNEL_9;
 8009cee:	f8cd 9020 	str.w	r9, [sp, #32]
  sConfig.Rank = ADC_REGULAR_RANK_1;
 8009cf2:	9609      	str	r6, [sp, #36]	; 0x24
  sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
 8009cf4:	940a      	str	r4, [sp, #40]	; 0x28
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8009cf6:	f7fe fb67 	bl	80083c8 <HAL_ADC_ConfigChannel>
  hadc2.Instance = ADC2;
 8009cfa:	4b6d      	ldr	r3, [pc, #436]	; (8009eb0 <main+0x304>)
  if (HAL_ADC_Init(&hadc2) != HAL_OK)
 8009cfc:	4628      	mov	r0, r5
  hadc2.Instance = ADC2;
 8009cfe:	602b      	str	r3, [r5, #0]
  hadc2.Init.ScanConvMode = ADC_SCAN_DISABLE;
 8009d00:	60ac      	str	r4, [r5, #8]
  hadc2.Init.ContinuousConvMode = DISABLE;
 8009d02:	732c      	strb	r4, [r5, #12]
  hadc2.Init.DiscontinuousConvMode = DISABLE;
 8009d04:	752c      	strb	r4, [r5, #20]
  hadc2.Init.ExternalTrigConv = ADC_SOFTWARE_START;
 8009d06:	61ef      	str	r7, [r5, #28]
  hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT;
 8009d08:	606c      	str	r4, [r5, #4]
  hadc2.Init.NbrOfConversion = 1;
 8009d0a:	612e      	str	r6, [r5, #16]
  ADC_ChannelConfTypeDef sConfig = {0};
 8009d0c:	9408      	str	r4, [sp, #32]
 8009d0e:	9409      	str	r4, [sp, #36]	; 0x24
 8009d10:	940a      	str	r4, [sp, #40]	; 0x28
  if (HAL_ADC_Init(&hadc2) != HAL_OK)
 8009d12:	f7fe fbff 	bl	8008514 <HAL_ADC_Init>
  sConfig.Channel = ADC_CHANNEL_10;
 8009d16:	230a      	movs	r3, #10
  if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
 8009d18:	a908      	add	r1, sp, #32
 8009d1a:	4628      	mov	r0, r5
  hadc3.Instance = ADC3;
 8009d1c:	4d65      	ldr	r5, [pc, #404]	; (8009eb4 <main+0x308>)
  sConfig.Channel = ADC_CHANNEL_10;
 8009d1e:	9308      	str	r3, [sp, #32]
  sConfig.Rank = ADC_REGULAR_RANK_1;
 8009d20:	9609      	str	r6, [sp, #36]	; 0x24
  sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
 8009d22:	940a      	str	r4, [sp, #40]	; 0x28
  if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
 8009d24:	f7fe fb50 	bl	80083c8 <HAL_ADC_ConfigChannel>
  hadc3.Instance = ADC3;
 8009d28:	4b63      	ldr	r3, [pc, #396]	; (8009eb8 <main+0x30c>)
  if (HAL_ADC_Init(&hadc3) != HAL_OK)
 8009d2a:	4628      	mov	r0, r5
  hadc3.Instance = ADC3;
 8009d2c:	602b      	str	r3, [r5, #0]
  hadc3.Init.ScanConvMode = ADC_SCAN_DISABLE;
 8009d2e:	60ac      	str	r4, [r5, #8]
  hadc3.Init.ContinuousConvMode = DISABLE;
 8009d30:	732c      	strb	r4, [r5, #12]
  hadc3.Init.DiscontinuousConvMode = DISABLE;
 8009d32:	752c      	strb	r4, [r5, #20]
  hadc3.Init.ExternalTrigConv = ADC_SOFTWARE_START;
 8009d34:	61ef      	str	r7, [r5, #28]
  hadc3.Init.DataAlign = ADC_DATAALIGN_RIGHT;
 8009d36:	606c      	str	r4, [r5, #4]
  hadc3.Init.NbrOfConversion = 1;
 8009d38:	612e      	str	r6, [r5, #16]
  ADC_ChannelConfTypeDef sConfig = {0};
 8009d3a:	9408      	str	r4, [sp, #32]
 8009d3c:	9409      	str	r4, [sp, #36]	; 0x24
 8009d3e:	940a      	str	r4, [sp, #40]	; 0x28
  if (HAL_ADC_Init(&hadc3) != HAL_OK)
 8009d40:	f7fe fbe8 	bl	8008514 <HAL_ADC_Init>
  if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
 8009d44:	a908      	add	r1, sp, #32
 8009d46:	4628      	mov	r0, r5
  sConfig.Rank = ADC_REGULAR_RANK_1;
 8009d48:	9609      	str	r6, [sp, #36]	; 0x24
  sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
 8009d4a:	940a      	str	r4, [sp, #40]	; 0x28
  sConfig.Channel = ADC_CHANNEL_11;
 8009d4c:	f8cd 8020 	str.w	r8, [sp, #32]
  if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
 8009d50:	f7fe fb3a 	bl	80083c8 <HAL_ADC_ConfigChannel>
  htim6.Init.Prescaler = 6400-1;
 8009d54:	f641 03ff 	movw	r3, #6399	; 0x18ff
  htim6.Instance = TIM6;
 8009d58:	4e58      	ldr	r6, [pc, #352]	; (8009ebc <main+0x310>)
  huart1.Init.Mode = UART_MODE_TX_RX;
 8009d5a:	270c      	movs	r7, #12
  htim6.Init.Period = 10-1;
 8009d5c:	f8c6 900c 	str.w	r9, [r6, #12]
  huart1.Init.BaudRate = 115200;
 8009d60:	f44f 39e1 	mov.w	r9, #115200	; 0x1c200
  htim6.Init.Prescaler = 6400-1;
 8009d64:	4a56      	ldr	r2, [pc, #344]	; (8009ec0 <main+0x314>)
  if (HAL_TIM_Base_Init(&htim6) != HAL_OK)
 8009d66:	4630      	mov	r0, r6
  htim6.Init.Prescaler = 6400-1;
 8009d68:	e886 000c 	stmia.w	r6, {r2, r3}
  htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
 8009d6c:	60b4      	str	r4, [r6, #8]
  htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
 8009d6e:	61b4      	str	r4, [r6, #24]
  TIM_MasterConfigTypeDef sMasterConfig = {0};
 8009d70:	9408      	str	r4, [sp, #32]
 8009d72:	9409      	str	r4, [sp, #36]	; 0x24
  if (HAL_TIM_Base_Init(&htim6) != HAL_OK)
 8009d74:	f7ff fb96 	bl	80094a4 <HAL_TIM_Base_Init>
  if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK)
 8009d78:	a908      	add	r1, sp, #32
 8009d7a:	4630      	mov	r0, r6
  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
 8009d7c:	9408      	str	r4, [sp, #32]
  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
 8009d7e:	9409      	str	r4, [sp, #36]	; 0x24
  if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK)
 8009d80:	f7ff fbaa 	bl	80094d8 <HAL_TIMEx_MasterConfigSynchronization>
  huart1.Instance = USART1;
 8009d84:	484f      	ldr	r0, [pc, #316]	; (8009ec4 <main+0x318>)
  huart1.Init.BaudRate = 115200;
 8009d86:	4b50      	ldr	r3, [pc, #320]	; (8009ec8 <main+0x31c>)
  huart2.Instance = USART2;
 8009d88:	4d50      	ldr	r5, [pc, #320]	; (8009ecc <main+0x320>)
  huart1.Init.BaudRate = 115200;
 8009d8a:	e880 0208 	stmia.w	r0, {r3, r9}
  huart1.Init.WordLength = UART_WORDLENGTH_8B;
 8009d8e:	6084      	str	r4, [r0, #8]
  huart1.Init.StopBits = UART_STOPBITS_1;
 8009d90:	60c4      	str	r4, [r0, #12]
  huart1.Init.Parity = UART_PARITY_NONE;
 8009d92:	6104      	str	r4, [r0, #16]
  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
 8009d94:	6184      	str	r4, [r0, #24]
  huart1.Init.OverSampling = UART_OVERSAMPLING_16;
 8009d96:	61c4      	str	r4, [r0, #28]
  huart1.Init.Mode = UART_MODE_TX_RX;
 8009d98:	6147      	str	r7, [r0, #20]
  if (HAL_UART_Init(&huart1) != HAL_OK)
 8009d9a:	f7ff fc2d 	bl	80095f8 <HAL_UART_Init>
  huart2.Instance = USART2;
 8009d9e:	4b4c      	ldr	r3, [pc, #304]	; (8009ed0 <main+0x324>)
  if (HAL_UART_Init(&huart2) != HAL_OK)
 8009da0:	4628      	mov	r0, r5
  huart2.Init.BaudRate = 115200;
 8009da2:	e885 0208 	stmia.w	r5, {r3, r9}
  huart2.Init.WordLength = UART_WORDLENGTH_8B;
 8009da6:	60ac      	str	r4, [r5, #8]
  huart2.Init.StopBits = UART_STOPBITS_1;
 8009da8:	60ec      	str	r4, [r5, #12]
  huart2.Init.Parity = UART_PARITY_NONE;
 8009daa:	612c      	str	r4, [r5, #16]
  huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
 8009dac:	61ac      	str	r4, [r5, #24]
  huart2.Init.OverSampling = UART_OVERSAMPLING_16;
 8009dae:	61ec      	str	r4, [r5, #28]
  huart2.Init.Mode = UART_MODE_TX_RX;
 8009db0:	616f      	str	r7, [r5, #20]
  if (HAL_UART_Init(&huart2) != HAL_OK)
 8009db2:	f7ff fc21 	bl	80095f8 <HAL_UART_Init>
  huart4.Instance = UART4;
 8009db6:	4b47      	ldr	r3, [pc, #284]	; (8009ed4 <main+0x328>)
 8009db8:	4847      	ldr	r0, [pc, #284]	; (8009ed8 <main+0x32c>)
  huart4.Init.BaudRate = 115200;
 8009dba:	e880 0208 	stmia.w	r0, {r3, r9}
  huart4.Init.WordLength = UART_WORDLENGTH_8B;
 8009dbe:	6084      	str	r4, [r0, #8]
  huart4.Init.StopBits = UART_STOPBITS_1;
 8009dc0:	60c4      	str	r4, [r0, #12]
  huart4.Init.Parity = UART_PARITY_NONE;
 8009dc2:	6104      	str	r4, [r0, #16]
  huart4.Init.HwFlowCtl = UART_HWCONTROL_NONE;
 8009dc4:	6184      	str	r4, [r0, #24]
  huart4.Init.OverSampling = UART_OVERSAMPLING_16;
 8009dc6:	61c4      	str	r4, [r0, #28]
  huart4.Init.Mode = UART_MODE_TX_RX;
 8009dc8:	6147      	str	r7, [r0, #20]
  if (HAL_UART_Init(&huart4) != HAL_OK)
 8009dca:	f7ff fc15 	bl	80095f8 <HAL_UART_Init>
  HAL_NVIC_SetPriority(ADC3_IRQn, 0, 0);
 8009dce:	4622      	mov	r2, r4
 8009dd0:	4621      	mov	r1, r4
 8009dd2:	202f      	movs	r0, #47	; 0x2f
 8009dd4:	f7fe fc3c 	bl	8008650 <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(ADC3_IRQn);
 8009dd8:	202f      	movs	r0, #47	; 0x2f
 8009dda:	f7fe fc6d 	bl	80086b8 <HAL_NVIC_EnableIRQ>
  HAL_NVIC_SetPriority(UART4_IRQn, 0, 0);
 8009dde:	4622      	mov	r2, r4
 8009de0:	4621      	mov	r1, r4
 8009de2:	2034      	movs	r0, #52	; 0x34
 8009de4:	f7fe fc34 	bl	8008650 <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(UART4_IRQn);
 8009de8:	2034      	movs	r0, #52	; 0x34
 8009dea:	f7fe fc65 	bl	80086b8 <HAL_NVIC_EnableIRQ>
  HAL_NVIC_SetPriority(TIM6_IRQn, 0, 0);
 8009dee:	4622      	mov	r2, r4
 8009df0:	4621      	mov	r1, r4
 8009df2:	2036      	movs	r0, #54	; 0x36
 8009df4:	f7fe fc2c 	bl	8008650 <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(TIM6_IRQn);
 8009df8:	2036      	movs	r0, #54	; 0x36
 8009dfa:	f7fe fc5d 	bl	80086b8 <HAL_NVIC_EnableIRQ>
  HAL_NVIC_SetPriority(ADC1_2_IRQn, 0, 0);
 8009dfe:	4622      	mov	r2, r4
 8009e00:	4621      	mov	r1, r4
 8009e02:	2012      	movs	r0, #18
 8009e04:	f7fe fc24 	bl	8008650 <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(ADC1_2_IRQn);
 8009e08:	2012      	movs	r0, #18
 8009e0a:	f7fe fc55 	bl	80086b8 <HAL_NVIC_EnableIRQ>
  HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
 8009e0e:	4622      	mov	r2, r4
 8009e10:	4621      	mov	r1, r4
 8009e12:	2025      	movs	r0, #37	; 0x25
 8009e14:	f7fe fc1c 	bl	8008650 <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(USART1_IRQn);
 8009e18:	2025      	movs	r0, #37	; 0x25
 8009e1a:	f7fe fc4d 	bl	80086b8 <HAL_NVIC_EnableIRQ>
  HAL_NVIC_SetPriority(USART2_IRQn, 0, 0);
 8009e1e:	4622      	mov	r2, r4
 8009e20:	4621      	mov	r1, r4
 8009e22:	2026      	movs	r0, #38	; 0x26
 8009e24:	f7fe fc14 	bl	8008650 <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(USART2_IRQn);
 8009e28:	2026      	movs	r0, #38	; 0x26
 8009e2a:	f7fe fc45 	bl	80086b8 <HAL_NVIC_EnableIRQ>
  HAL_NVIC_SetPriority(DMA1_Channel6_IRQn, 0, 0);
 8009e2e:	4622      	mov	r2, r4
 8009e30:	4621      	mov	r1, r4
 8009e32:	2010      	movs	r0, #16
 8009e34:	f7fe fc0c 	bl	8008650 <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(DMA1_Channel6_IRQn);
 8009e38:	2010      	movs	r0, #16
 8009e3a:	f7fe fc3d 	bl	80086b8 <HAL_NVIC_EnableIRQ>
  HAL_NVIC_SetPriority(DMA1_Channel5_IRQn, 0, 0);
 8009e3e:	4622      	mov	r2, r4
 8009e40:	4621      	mov	r1, r4
 8009e42:	200f      	movs	r0, #15
 8009e44:	f7fe fc04 	bl	8008650 <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(DMA1_Channel5_IRQn);
 8009e48:	200f      	movs	r0, #15
 8009e4a:	f7fe fc35 	bl	80086b8 <HAL_NVIC_EnableIRQ>
  HAL_NVIC_SetPriority(DMA1_Channel4_IRQn, 0, 0);
 8009e4e:	4622      	mov	r2, r4
 8009e50:	4621      	mov	r1, r4
 8009e52:	200e      	movs	r0, #14
 8009e54:	f7fe fbfc 	bl	8008650 <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(DMA1_Channel4_IRQn);
 8009e58:	200e      	movs	r0, #14
 8009e5a:	f7fe fc2d 	bl	80086b8 <HAL_NVIC_EnableIRQ>
  HAL_TIM_Base_Start_IT(&htim6);
 8009e5e:	4630      	mov	r0, r6
 8009e60:	f7ff fa1e 	bl	80092a0 <HAL_TIM_Base_Start_IT>
  setbuf(stdout, NULL);
 8009e64:	4b1d      	ldr	r3, [pc, #116]	; (8009edc <main+0x330>)
 8009e66:	4621      	mov	r1, r4
 8009e68:	681b      	ldr	r3, [r3, #0]
	  if(LedTimerCnt > 100){
 8009e6a:	4c1d      	ldr	r4, [pc, #116]	; (8009ee0 <main+0x334>)
  setbuf(stdout, NULL);
 8009e6c:	6898      	ldr	r0, [r3, #8]
 8009e6e:	f000 fc0b 	bl	800a688 <setbuf>
  printf("Uart Start \r\n");
 8009e72:	481c      	ldr	r0, [pc, #112]	; (8009ee4 <main+0x338>)
 8009e74:	f000 fc00 	bl	800a678 <puts>
  printf("Crc generate %x \r\n",CRC16_Generate(tempdata,11));
 8009e78:	4641      	mov	r1, r8
 8009e7a:	a805      	add	r0, sp, #20
 8009e7c:	f7ff fe16 	bl	8009aac <CRC16_Generate>
 8009e80:	4601      	mov	r1, r0
 8009e82:	4819      	ldr	r0, [pc, #100]	; (8009ee8 <main+0x33c>)
 8009e84:	f000 fb84 	bl	800a590 <iprintf>
 8009e88:	e030      	b.n	8009eec <main+0x340>
 8009e8a:	bf00      	nop
 8009e8c:	0800b604 	.word	0x0800b604
 8009e90:	40021000 	.word	0x40021000
 8009e94:	40011000 	.word	0x40011000
 8009e98:	40010800 	.word	0x40010800
 8009e9c:	40010c00 	.word	0x40010c00
 8009ea0:	40011400 	.word	0x40011400
 8009ea4:	20000360 	.word	0x20000360
 8009ea8:	40012400 	.word	0x40012400
 8009eac:	200002ec 	.word	0x200002ec
 8009eb0:	40012800 	.word	0x40012800
 8009eb4:	20000390 	.word	0x20000390
 8009eb8:	40013c00 	.word	0x40013c00
 8009ebc:	20000488 	.word	0x20000488
 8009ec0:	40001000 	.word	0x40001000
 8009ec4:	20000448 	.word	0x20000448
 8009ec8:	40013800 	.word	0x40013800
 8009ecc:	20000508 	.word	0x20000508
 8009ed0:	40004400 	.word	0x40004400
 8009ed4:	40004c00 	.word	0x40004c00
 8009ed8:	200004c8 	.word	0x200004c8
 8009edc:	2000020c 	.word	0x2000020c
 8009ee0:	20000290 	.word	0x20000290
 8009ee4:	0800b60f 	.word	0x0800b60f
 8009ee8:	0800b61c 	.word	0x0800b61c
  InitUartQueue(&TerminalQueue);
 8009eec:	4827      	ldr	r0, [pc, #156]	; (8009f8c <main+0x3e0>)
 8009eee:	f000 fa91 	bl	800a414 <InitUartQueue>
  InitUartQueue(&WifiQueue);
 8009ef2:	4827      	ldr	r0, [pc, #156]	; (8009f90 <main+0x3e4>)
 8009ef4:	f000 fa8e 	bl	800a414 <InitUartQueue>
  HAL_UART_Transmit_DMA(&huart2, "AT+CWMODE=3\r\n", ESP8266_Strindex("AT+CWMODE=3\r\n"));
 8009ef8:	4826      	ldr	r0, [pc, #152]	; (8009f94 <main+0x3e8>)
 8009efa:	f7ff fdfb 	bl	8009af4 <ESP8266_Strindex>
 8009efe:	4925      	ldr	r1, [pc, #148]	; (8009f94 <main+0x3e8>)
 8009f00:	b282      	uxth	r2, r0
 8009f02:	4628      	mov	r0, r5
 8009f04:	f7ff fc02 	bl	800970c <HAL_UART_Transmit_DMA>
  HAL_Delay(5);
 8009f08:	2005      	movs	r0, #5
 8009f0a:	f7fe f9d3 	bl	80082b4 <HAL_Delay>
  HAL_UART_Transmit_DMA(&huart2, "AT+CIPMUX=1\r\n", ESP8266_Strindex("AT+CIPMUX=1\r\n"));
 8009f0e:	4822      	ldr	r0, [pc, #136]	; (8009f98 <main+0x3ec>)
 8009f10:	f7ff fdf0 	bl	8009af4 <ESP8266_Strindex>
 8009f14:	4920      	ldr	r1, [pc, #128]	; (8009f98 <main+0x3ec>)
 8009f16:	b282      	uxth	r2, r0
 8009f18:	4628      	mov	r0, r5
 8009f1a:	f7ff fbf7 	bl	800970c <HAL_UART_Transmit_DMA>
  HAL_Delay(5);
 8009f1e:	2005      	movs	r0, #5
 8009f20:	f7fe f9c8 	bl	80082b4 <HAL_Delay>
  HAL_UART_Transmit_DMA(&huart2, "AT+CWSAP=\"YJ_TEST\",\"\",5,0\r\n", ESP8266_Strindex("AT+CWSAP=\"YJ_TEST\",\"\",5,0\r\n"));
 8009f24:	481d      	ldr	r0, [pc, #116]	; (8009f9c <main+0x3f0>)
 8009f26:	f7ff fde5 	bl	8009af4 <ESP8266_Strindex>
 8009f2a:	491c      	ldr	r1, [pc, #112]	; (8009f9c <main+0x3f0>)
 8009f2c:	b282      	uxth	r2, r0
 8009f2e:	4628      	mov	r0, r5
 8009f30:	f7ff fbec 	bl	800970c <HAL_UART_Transmit_DMA>
  HAL_Delay(5);
 8009f34:	2005      	movs	r0, #5
 8009f36:	f7fe f9bd 	bl	80082b4 <HAL_Delay>
  HAL_UART_Transmit_DMA(&huart2, "AT+CIPSERVER=1,4000\r\n", ESP8266_Strindex("AT+CIPSERVER=1,4000\r\n"));
 8009f3a:	4819      	ldr	r0, [pc, #100]	; (8009fa0 <main+0x3f4>)
 8009f3c:	f7ff fdda 	bl	8009af4 <ESP8266_Strindex>
 8009f40:	4917      	ldr	r1, [pc, #92]	; (8009fa0 <main+0x3f4>)
 8009f42:	b282      	uxth	r2, r0
 8009f44:	4628      	mov	r0, r5
 8009f46:	f7ff fbe1 	bl	800970c <HAL_UART_Transmit_DMA>
  printf("ESP Setting Complete \r\n");
 8009f4a:	4816      	ldr	r0, [pc, #88]	; (8009fa4 <main+0x3f8>)
 8009f4c:	f000 fb94 	bl	800a678 <puts>
		  HAL_GPIO_TogglePin(LED_UL_G_B_GPIO_Port,LED_UL_G_B_Pin);
 8009f50:	4e15      	ldr	r6, [pc, #84]	; (8009fa8 <main+0x3fc>)
	   while (TerminalQueue.data > 0) GetDataFromUartQueue(&hTerminal);
 8009f52:	4d0e      	ldr	r5, [pc, #56]	; (8009f8c <main+0x3e0>)
	  if(LedTimerCnt > 100){
 8009f54:	6823      	ldr	r3, [r4, #0]
 8009f56:	2b64      	cmp	r3, #100	; 0x64
 8009f58:	d905      	bls.n	8009f66 <main+0x3ba>
		  HAL_GPIO_TogglePin(LED_UL_G_B_GPIO_Port,LED_UL_G_B_Pin);
 8009f5a:	2102      	movs	r1, #2
 8009f5c:	4630      	mov	r0, r6
 8009f5e:	f7fe fe88 	bl	8008c72 <HAL_GPIO_TogglePin>
		  LedTimerCnt = 0;
 8009f62:	2300      	movs	r3, #0
 8009f64:	6023      	str	r3, [r4, #0]
	   while (TerminalQueue.data > 0) GetDataFromUartQueue(&hTerminal);
 8009f66:	4f11      	ldr	r7, [pc, #68]	; (8009fac <main+0x400>)
 8009f68:	68ab      	ldr	r3, [r5, #8]
 8009f6a:	2b00      	cmp	r3, #0
 8009f6c:	dc09      	bgt.n	8009f82 <main+0x3d6>
	   while (WifiQueue.data > 0) GetDataFromUartQueue(&hWifi);
 8009f6e:	4f08      	ldr	r7, [pc, #32]	; (8009f90 <main+0x3e4>)
 8009f70:	f8df 803c 	ldr.w	r8, [pc, #60]	; 8009fb0 <main+0x404>
 8009f74:	68bb      	ldr	r3, [r7, #8]
 8009f76:	2b00      	cmp	r3, #0
 8009f78:	ddec      	ble.n	8009f54 <main+0x3a8>
 8009f7a:	4640      	mov	r0, r8
 8009f7c:	f000 fa58 	bl	800a430 <GetDataFromUartQueue>
 8009f80:	e7f8      	b.n	8009f74 <main+0x3c8>
	   while (TerminalQueue.data > 0) GetDataFromUartQueue(&hTerminal);
 8009f82:	4638      	mov	r0, r7
 8009f84:	f000 fa54 	bl	800a430 <GetDataFromUartQueue>
 8009f88:	e7ee      	b.n	8009f68 <main+0x3bc>
 8009f8a:	bf00      	nop
 8009f8c:	20000548 	.word	0x20000548
 8009f90:	20000954 	.word	0x20000954
 8009f94:	0800b62f 	.word	0x0800b62f
 8009f98:	0800b63d 	.word	0x0800b63d
 8009f9c:	0800b64b 	.word	0x0800b64b
 8009fa0:	0800b667 	.word	0x0800b667
 8009fa4:	0800b67d 	.word	0x0800b67d
 8009fa8:	40010800 	.word	0x40010800
 8009fac:	20000448 	.word	0x20000448
 8009fb0:	20000508 	.word	0x20000508

08009fb4 <Error_Handler>:
/**
  * @brief  This function is executed in case of error occurrence.
  * @retval None
  */
void Error_Handler(void)
{
 8009fb4:	4770      	bx	lr
	...

08009fb8 <HAL_MspInit>:
{
  /* USER CODE BEGIN MspInit 0 */

  /* USER CODE END MspInit 0 */

  __HAL_RCC_AFIO_CLK_ENABLE();
 8009fb8:	4b0e      	ldr	r3, [pc, #56]	; (8009ff4 <HAL_MspInit+0x3c>)
{
 8009fba:	b082      	sub	sp, #8
  __HAL_RCC_AFIO_CLK_ENABLE();
 8009fbc:	699a      	ldr	r2, [r3, #24]
 8009fbe:	f042 0201 	orr.w	r2, r2, #1
 8009fc2:	619a      	str	r2, [r3, #24]
 8009fc4:	699a      	ldr	r2, [r3, #24]
 8009fc6:	f002 0201 	and.w	r2, r2, #1
 8009fca:	9200      	str	r2, [sp, #0]
 8009fcc:	9a00      	ldr	r2, [sp, #0]
  __HAL_RCC_PWR_CLK_ENABLE();
 8009fce:	69da      	ldr	r2, [r3, #28]
 8009fd0:	f042 5280 	orr.w	r2, r2, #268435456	; 0x10000000
 8009fd4:	61da      	str	r2, [r3, #28]
 8009fd6:	69db      	ldr	r3, [r3, #28]

  /* System interrupt init*/

  /** DISABLE: JTAG-DP Disabled and SW-DP Disabled 
  */
  __HAL_AFIO_REMAP_SWJ_DISABLE();
 8009fd8:	4a07      	ldr	r2, [pc, #28]	; (8009ff8 <HAL_MspInit+0x40>)
  __HAL_RCC_PWR_CLK_ENABLE();
 8009fda:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8009fde:	9301      	str	r3, [sp, #4]
 8009fe0:	9b01      	ldr	r3, [sp, #4]
  __HAL_AFIO_REMAP_SWJ_DISABLE();
 8009fe2:	6853      	ldr	r3, [r2, #4]
 8009fe4:	f023 63e0 	bic.w	r3, r3, #117440512	; 0x7000000
 8009fe8:	f043 6380 	orr.w	r3, r3, #67108864	; 0x4000000
 8009fec:	6053      	str	r3, [r2, #4]

  /* USER CODE BEGIN MspInit 1 */

  /* USER CODE END MspInit 1 */
}
 8009fee:	b002      	add	sp, #8
 8009ff0:	4770      	bx	lr
 8009ff2:	bf00      	nop
 8009ff4:	40021000 	.word	0x40021000
 8009ff8:	40010000 	.word	0x40010000

08009ffc <HAL_ADC_MspInit>:
* This function configures the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
{
 8009ffc:	b510      	push	{r4, lr}
 8009ffe:	4604      	mov	r4, r0
 800a000:	b08a      	sub	sp, #40	; 0x28
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 800a002:	2210      	movs	r2, #16
 800a004:	2100      	movs	r1, #0
 800a006:	a806      	add	r0, sp, #24
 800a008:	f000 faba 	bl	800a580 <memset>
  if(hadc->Instance==ADC1)
 800a00c:	6823      	ldr	r3, [r4, #0]
 800a00e:	4a2a      	ldr	r2, [pc, #168]	; (800a0b8 <HAL_ADC_MspInit+0xbc>)
 800a010:	4293      	cmp	r3, r2
 800a012:	d11c      	bne.n	800a04e <HAL_ADC_MspInit+0x52>
  {
  /* USER CODE BEGIN ADC1_MspInit 0 */

  /* USER CODE END ADC1_MspInit 0 */
    /* Peripheral clock enable */
    __HAL_RCC_ADC1_CLK_ENABLE();
 800a014:	4b29      	ldr	r3, [pc, #164]	; (800a0bc <HAL_ADC_MspInit+0xc0>)
    /**ADC1 GPIO Configuration    
    PB1     ------> ADC1_IN9 
    */
    GPIO_InitStruct.Pin = RFU_TEMP_Pin;
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
    HAL_GPIO_Init(RFU_TEMP_GPIO_Port, &GPIO_InitStruct);
 800a016:	482a      	ldr	r0, [pc, #168]	; (800a0c0 <HAL_ADC_MspInit+0xc4>)
    __HAL_RCC_ADC1_CLK_ENABLE();
 800a018:	699a      	ldr	r2, [r3, #24]
    HAL_GPIO_Init(RFU_TEMP_GPIO_Port, &GPIO_InitStruct);
 800a01a:	a906      	add	r1, sp, #24
    __HAL_RCC_ADC1_CLK_ENABLE();
 800a01c:	f442 7200 	orr.w	r2, r2, #512	; 0x200
 800a020:	619a      	str	r2, [r3, #24]
 800a022:	699a      	ldr	r2, [r3, #24]
 800a024:	f402 7200 	and.w	r2, r2, #512	; 0x200
 800a028:	9200      	str	r2, [sp, #0]
 800a02a:	9a00      	ldr	r2, [sp, #0]
    __HAL_RCC_GPIOB_CLK_ENABLE();
 800a02c:	699a      	ldr	r2, [r3, #24]
 800a02e:	f042 0208 	orr.w	r2, r2, #8
 800a032:	619a      	str	r2, [r3, #24]
 800a034:	699b      	ldr	r3, [r3, #24]
 800a036:	f003 0308 	and.w	r3, r3, #8
 800a03a:	9301      	str	r3, [sp, #4]
 800a03c:	9b01      	ldr	r3, [sp, #4]
    GPIO_InitStruct.Pin = RFU_TEMP_Pin;
 800a03e:	2302      	movs	r3, #2
 800a040:	9306      	str	r3, [sp, #24]
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
 800a042:	2303      	movs	r3, #3
 800a044:	9307      	str	r3, [sp, #28]
    /**ADC3 GPIO Configuration    
    PC1     ------> ADC3_IN11 
    */
    GPIO_InitStruct.Pin = EXT_DET_B_Pin;
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
    HAL_GPIO_Init(EXT_DET_B_GPIO_Port, &GPIO_InitStruct);
 800a046:	f7fe fd23 	bl	8008a90 <HAL_GPIO_Init>
  /* USER CODE BEGIN ADC3_MspInit 1 */

  /* USER CODE END ADC3_MspInit 1 */
  }

}
 800a04a:	b00a      	add	sp, #40	; 0x28
 800a04c:	bd10      	pop	{r4, pc}
  else if(hadc->Instance==ADC2)
 800a04e:	4a1d      	ldr	r2, [pc, #116]	; (800a0c4 <HAL_ADC_MspInit+0xc8>)
 800a050:	4293      	cmp	r3, r2
 800a052:	d119      	bne.n	800a088 <HAL_ADC_MspInit+0x8c>
    __HAL_RCC_ADC2_CLK_ENABLE();
 800a054:	4b19      	ldr	r3, [pc, #100]	; (800a0bc <HAL_ADC_MspInit+0xc0>)
 800a056:	699a      	ldr	r2, [r3, #24]
 800a058:	f442 6280 	orr.w	r2, r2, #1024	; 0x400
 800a05c:	619a      	str	r2, [r3, #24]
 800a05e:	699a      	ldr	r2, [r3, #24]
 800a060:	f402 6280 	and.w	r2, r2, #1024	; 0x400
 800a064:	9202      	str	r2, [sp, #8]
 800a066:	9a02      	ldr	r2, [sp, #8]
    __HAL_RCC_GPIOC_CLK_ENABLE();
 800a068:	699a      	ldr	r2, [r3, #24]
 800a06a:	f042 0210 	orr.w	r2, r2, #16
 800a06e:	619a      	str	r2, [r3, #24]
 800a070:	699b      	ldr	r3, [r3, #24]
 800a072:	f003 0310 	and.w	r3, r3, #16
 800a076:	9303      	str	r3, [sp, #12]
 800a078:	9b03      	ldr	r3, [sp, #12]
    GPIO_InitStruct.Pin = DET_OUT_B_Pin;
 800a07a:	2301      	movs	r3, #1
    GPIO_InitStruct.Pin = EXT_DET_B_Pin;
 800a07c:	9306      	str	r3, [sp, #24]
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
 800a07e:	2303      	movs	r3, #3
    HAL_GPIO_Init(EXT_DET_B_GPIO_Port, &GPIO_InitStruct);
 800a080:	a906      	add	r1, sp, #24
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
 800a082:	9307      	str	r3, [sp, #28]
    HAL_GPIO_Init(EXT_DET_B_GPIO_Port, &GPIO_InitStruct);
 800a084:	4810      	ldr	r0, [pc, #64]	; (800a0c8 <HAL_ADC_MspInit+0xcc>)
 800a086:	e7de      	b.n	800a046 <HAL_ADC_MspInit+0x4a>
  else if(hadc->Instance==ADC3)
 800a088:	4a10      	ldr	r2, [pc, #64]	; (800a0cc <HAL_ADC_MspInit+0xd0>)
 800a08a:	4293      	cmp	r3, r2
 800a08c:	d1dd      	bne.n	800a04a <HAL_ADC_MspInit+0x4e>
    __HAL_RCC_ADC3_CLK_ENABLE();
 800a08e:	4b0b      	ldr	r3, [pc, #44]	; (800a0bc <HAL_ADC_MspInit+0xc0>)
 800a090:	699a      	ldr	r2, [r3, #24]
 800a092:	f442 4200 	orr.w	r2, r2, #32768	; 0x8000
 800a096:	619a      	str	r2, [r3, #24]
 800a098:	699a      	ldr	r2, [r3, #24]
 800a09a:	f402 4200 	and.w	r2, r2, #32768	; 0x8000
 800a09e:	9204      	str	r2, [sp, #16]
 800a0a0:	9a04      	ldr	r2, [sp, #16]
    __HAL_RCC_GPIOC_CLK_ENABLE();
 800a0a2:	699a      	ldr	r2, [r3, #24]
 800a0a4:	f042 0210 	orr.w	r2, r2, #16
 800a0a8:	619a      	str	r2, [r3, #24]
 800a0aa:	699b      	ldr	r3, [r3, #24]
 800a0ac:	f003 0310 	and.w	r3, r3, #16
 800a0b0:	9305      	str	r3, [sp, #20]
 800a0b2:	9b05      	ldr	r3, [sp, #20]
    GPIO_InitStruct.Pin = EXT_DET_B_Pin;
 800a0b4:	2302      	movs	r3, #2
 800a0b6:	e7e1      	b.n	800a07c <HAL_ADC_MspInit+0x80>
 800a0b8:	40012400 	.word	0x40012400
 800a0bc:	40021000 	.word	0x40021000
 800a0c0:	40010c00 	.word	0x40010c00
 800a0c4:	40012800 	.word	0x40012800
 800a0c8:	40011000 	.word	0x40011000
 800a0cc:	40013c00 	.word	0x40013c00

0800a0d0 <HAL_TIM_Base_MspInit>:
* @param htim_base: TIM_Base handle pointer
* @retval None
*/
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
{
  if(htim_base->Instance==TIM6)
 800a0d0:	6802      	ldr	r2, [r0, #0]
 800a0d2:	4b08      	ldr	r3, [pc, #32]	; (800a0f4 <HAL_TIM_Base_MspInit+0x24>)
{
 800a0d4:	b082      	sub	sp, #8
  if(htim_base->Instance==TIM6)
 800a0d6:	429a      	cmp	r2, r3
 800a0d8:	d10a      	bne.n	800a0f0 <HAL_TIM_Base_MspInit+0x20>
  {
  /* USER CODE BEGIN TIM6_MspInit 0 */

  /* USER CODE END TIM6_MspInit 0 */
    /* Peripheral clock enable */
    __HAL_RCC_TIM6_CLK_ENABLE();
 800a0da:	f503 3300 	add.w	r3, r3, #131072	; 0x20000
 800a0de:	69da      	ldr	r2, [r3, #28]
 800a0e0:	f042 0210 	orr.w	r2, r2, #16
 800a0e4:	61da      	str	r2, [r3, #28]
 800a0e6:	69db      	ldr	r3, [r3, #28]
 800a0e8:	f003 0310 	and.w	r3, r3, #16
 800a0ec:	9301      	str	r3, [sp, #4]
 800a0ee:	9b01      	ldr	r3, [sp, #4]
  /* USER CODE BEGIN TIM6_MspInit 1 */

  /* USER CODE END TIM6_MspInit 1 */
  }

}
 800a0f0:	b002      	add	sp, #8
 800a0f2:	4770      	bx	lr
 800a0f4:	40001000 	.word	0x40001000

0800a0f8 <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
 800a0f8:	b570      	push	{r4, r5, r6, lr}
 800a0fa:	4605      	mov	r5, r0
 800a0fc:	b08a      	sub	sp, #40	; 0x28
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 800a0fe:	2210      	movs	r2, #16
 800a100:	2100      	movs	r1, #0
 800a102:	a806      	add	r0, sp, #24
 800a104:	f000 fa3c 	bl	800a580 <memset>
  if(huart->Instance==UART4)
 800a108:	682b      	ldr	r3, [r5, #0]
 800a10a:	4a60      	ldr	r2, [pc, #384]	; (800a28c <HAL_UART_MspInit+0x194>)
 800a10c:	4293      	cmp	r3, r2
 800a10e:	d129      	bne.n	800a164 <HAL_UART_MspInit+0x6c>
  {
  /* USER CODE BEGIN UART4_MspInit 0 */

  /* USER CODE END UART4_MspInit 0 */
    /* Peripheral clock enable */
    __HAL_RCC_UART4_CLK_ENABLE();
 800a110:	4b5f      	ldr	r3, [pc, #380]	; (800a290 <HAL_UART_MspInit+0x198>)
    PC11     ------> UART4_RX 
    */
    GPIO_InitStruct.Pin = GPIO_PIN_10;
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 800a112:	a906      	add	r1, sp, #24
    __HAL_RCC_UART4_CLK_ENABLE();
 800a114:	69da      	ldr	r2, [r3, #28]
    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 800a116:	485f      	ldr	r0, [pc, #380]	; (800a294 <HAL_UART_MspInit+0x19c>)
    __HAL_RCC_UART4_CLK_ENABLE();
 800a118:	f442 2200 	orr.w	r2, r2, #524288	; 0x80000
 800a11c:	61da      	str	r2, [r3, #28]
 800a11e:	69da      	ldr	r2, [r3, #28]
 800a120:	f402 2200 	and.w	r2, r2, #524288	; 0x80000
 800a124:	9200      	str	r2, [sp, #0]
 800a126:	9a00      	ldr	r2, [sp, #0]
    __HAL_RCC_GPIOC_CLK_ENABLE();
 800a128:	699a      	ldr	r2, [r3, #24]
 800a12a:	f042 0210 	orr.w	r2, r2, #16
 800a12e:	619a      	str	r2, [r3, #24]
 800a130:	699b      	ldr	r3, [r3, #24]
 800a132:	f003 0310 	and.w	r3, r3, #16
 800a136:	9301      	str	r3, [sp, #4]
 800a138:	9b01      	ldr	r3, [sp, #4]
    GPIO_InitStruct.Pin = GPIO_PIN_10;
 800a13a:	f44f 6380 	mov.w	r3, #1024	; 0x400
 800a13e:	9306      	str	r3, [sp, #24]
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 800a140:	2302      	movs	r3, #2
 800a142:	9307      	str	r3, [sp, #28]
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
 800a144:	2303      	movs	r3, #3
 800a146:	9309      	str	r3, [sp, #36]	; 0x24
    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 800a148:	f7fe fca2 	bl	8008a90 <HAL_GPIO_Init>

    GPIO_InitStruct.Pin = GPIO_PIN_11;
 800a14c:	f44f 6300 	mov.w	r3, #2048	; 0x800
 800a150:	9306      	str	r3, [sp, #24]
    GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
 800a152:	2300      	movs	r3, #0
    GPIO_InitStruct.Pull = GPIO_NOPULL;
    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 800a154:	a906      	add	r1, sp, #24
 800a156:	484f      	ldr	r0, [pc, #316]	; (800a294 <HAL_UART_MspInit+0x19c>)
    GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
 800a158:	9307      	str	r3, [sp, #28]
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 800a15a:	9308      	str	r3, [sp, #32]
    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 800a15c:	f7fe fc98 	bl	8008a90 <HAL_GPIO_Init>
  /* USER CODE BEGIN USART2_MspInit 1 */

  /* USER CODE END USART2_MspInit 1 */
  }

}
 800a160:	b00a      	add	sp, #40	; 0x28
 800a162:	bd70      	pop	{r4, r5, r6, pc}
  else if(huart->Instance==USART1)
 800a164:	4a4c      	ldr	r2, [pc, #304]	; (800a298 <HAL_UART_MspInit+0x1a0>)
 800a166:	4293      	cmp	r3, r2
 800a168:	d150      	bne.n	800a20c <HAL_UART_MspInit+0x114>
    __HAL_RCC_USART1_CLK_ENABLE();
 800a16a:	4b49      	ldr	r3, [pc, #292]	; (800a290 <HAL_UART_MspInit+0x198>)
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 800a16c:	a906      	add	r1, sp, #24
    __HAL_RCC_USART1_CLK_ENABLE();
 800a16e:	699a      	ldr	r2, [r3, #24]
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 800a170:	484a      	ldr	r0, [pc, #296]	; (800a29c <HAL_UART_MspInit+0x1a4>)
    __HAL_RCC_USART1_CLK_ENABLE();
 800a172:	f442 4280 	orr.w	r2, r2, #16384	; 0x4000
 800a176:	619a      	str	r2, [r3, #24]
 800a178:	699a      	ldr	r2, [r3, #24]
    GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
 800a17a:	2600      	movs	r6, #0
    __HAL_RCC_USART1_CLK_ENABLE();
 800a17c:	f402 4280 	and.w	r2, r2, #16384	; 0x4000
 800a180:	9202      	str	r2, [sp, #8]
 800a182:	9a02      	ldr	r2, [sp, #8]
    __HAL_RCC_GPIOA_CLK_ENABLE();
 800a184:	699a      	ldr	r2, [r3, #24]
    hdma_usart1_rx.Instance = DMA1_Channel5;
 800a186:	4c46      	ldr	r4, [pc, #280]	; (800a2a0 <HAL_UART_MspInit+0x1a8>)
    __HAL_RCC_GPIOA_CLK_ENABLE();
 800a188:	f042 0204 	orr.w	r2, r2, #4
 800a18c:	619a      	str	r2, [r3, #24]
 800a18e:	699b      	ldr	r3, [r3, #24]
 800a190:	f003 0304 	and.w	r3, r3, #4
 800a194:	9303      	str	r3, [sp, #12]
 800a196:	9b03      	ldr	r3, [sp, #12]
    GPIO_InitStruct.Pin = GPIO_PIN_9;
 800a198:	f44f 7300 	mov.w	r3, #512	; 0x200
 800a19c:	9306      	str	r3, [sp, #24]
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 800a19e:	2302      	movs	r3, #2
 800a1a0:	9307      	str	r3, [sp, #28]
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
 800a1a2:	2303      	movs	r3, #3
 800a1a4:	9309      	str	r3, [sp, #36]	; 0x24
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 800a1a6:	f7fe fc73 	bl	8008a90 <HAL_GPIO_Init>
    GPIO_InitStruct.Pin = GPIO_PIN_10;
 800a1aa:	f44f 6380 	mov.w	r3, #1024	; 0x400
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 800a1ae:	483b      	ldr	r0, [pc, #236]	; (800a29c <HAL_UART_MspInit+0x1a4>)
 800a1b0:	a906      	add	r1, sp, #24
    GPIO_InitStruct.Pin = GPIO_PIN_10;
 800a1b2:	9306      	str	r3, [sp, #24]
    GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
 800a1b4:	9607      	str	r6, [sp, #28]
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 800a1b6:	9608      	str	r6, [sp, #32]
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 800a1b8:	f7fe fc6a 	bl	8008a90 <HAL_GPIO_Init>
    hdma_usart1_rx.Instance = DMA1_Channel5;
 800a1bc:	4b39      	ldr	r3, [pc, #228]	; (800a2a4 <HAL_UART_MspInit+0x1ac>)
    if (HAL_DMA_Init(&hdma_usart1_rx) != HAL_OK)
 800a1be:	4620      	mov	r0, r4
    hdma_usart1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
 800a1c0:	e884 0048 	stmia.w	r4, {r3, r6}
    hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE;
 800a1c4:	2380      	movs	r3, #128	; 0x80
    hdma_usart1_rx.Init.PeriphInc = DMA_PINC_DISABLE;
 800a1c6:	60a6      	str	r6, [r4, #8]
    hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE;
 800a1c8:	60e3      	str	r3, [r4, #12]
    hdma_usart1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
 800a1ca:	6126      	str	r6, [r4, #16]
    hdma_usart1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
 800a1cc:	6166      	str	r6, [r4, #20]
    hdma_usart1_rx.Init.Mode = DMA_NORMAL;
 800a1ce:	61a6      	str	r6, [r4, #24]
    hdma_usart1_rx.Init.Priority = DMA_PRIORITY_LOW;
 800a1d0:	61e6      	str	r6, [r4, #28]
    if (HAL_DMA_Init(&hdma_usart1_rx) != HAL_OK)
 800a1d2:	f7fe fa95 	bl	8008700 <HAL_DMA_Init>
 800a1d6:	b108      	cbz	r0, 800a1dc <HAL_UART_MspInit+0xe4>
      Error_Handler();
 800a1d8:	f7ff feec 	bl	8009fb4 <Error_Handler>
    __HAL_LINKDMA(huart,hdmarx,hdma_usart1_rx);
 800a1dc:	636c      	str	r4, [r5, #52]	; 0x34
 800a1de:	6265      	str	r5, [r4, #36]	; 0x24
    hdma_usart1_tx.Instance = DMA1_Channel4;
 800a1e0:	4b31      	ldr	r3, [pc, #196]	; (800a2a8 <HAL_UART_MspInit+0x1b0>)
 800a1e2:	4c32      	ldr	r4, [pc, #200]	; (800a2ac <HAL_UART_MspInit+0x1b4>)
    hdma_usart2_tx.Instance = DMA1_Channel7;
 800a1e4:	6023      	str	r3, [r4, #0]
    hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
 800a1e6:	2310      	movs	r3, #16
    hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE;
 800a1e8:	2280      	movs	r2, #128	; 0x80
    hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
 800a1ea:	6063      	str	r3, [r4, #4]
    hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE;
 800a1ec:	2300      	movs	r3, #0
    hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE;
 800a1ee:	60e2      	str	r2, [r4, #12]
    hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE;
 800a1f0:	60a3      	str	r3, [r4, #8]
    hdma_usart2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
 800a1f2:	6123      	str	r3, [r4, #16]
    hdma_usart2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
 800a1f4:	6163      	str	r3, [r4, #20]
    hdma_usart2_tx.Init.Mode = DMA_NORMAL;
 800a1f6:	61a3      	str	r3, [r4, #24]
    hdma_usart2_tx.Init.Priority = DMA_PRIORITY_LOW;
 800a1f8:	61e3      	str	r3, [r4, #28]
    if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK)
 800a1fa:	4620      	mov	r0, r4
 800a1fc:	f7fe fa80 	bl	8008700 <HAL_DMA_Init>
 800a200:	b108      	cbz	r0, 800a206 <HAL_UART_MspInit+0x10e>
      Error_Handler();
 800a202:	f7ff fed7 	bl	8009fb4 <Error_Handler>
    __HAL_LINKDMA(huart,hdmatx,hdma_usart2_tx);
 800a206:	632c      	str	r4, [r5, #48]	; 0x30
 800a208:	6265      	str	r5, [r4, #36]	; 0x24
}
 800a20a:	e7a9      	b.n	800a160 <HAL_UART_MspInit+0x68>
  else if(huart->Instance==USART2)
 800a20c:	4a28      	ldr	r2, [pc, #160]	; (800a2b0 <HAL_UART_MspInit+0x1b8>)
 800a20e:	4293      	cmp	r3, r2
 800a210:	d1a6      	bne.n	800a160 <HAL_UART_MspInit+0x68>
    __HAL_RCC_USART2_CLK_ENABLE();
 800a212:	4b1f      	ldr	r3, [pc, #124]	; (800a290 <HAL_UART_MspInit+0x198>)
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 800a214:	a906      	add	r1, sp, #24
    __HAL_RCC_USART2_CLK_ENABLE();
 800a216:	69da      	ldr	r2, [r3, #28]
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 800a218:	4820      	ldr	r0, [pc, #128]	; (800a29c <HAL_UART_MspInit+0x1a4>)
    __HAL_RCC_USART2_CLK_ENABLE();
 800a21a:	f442 3200 	orr.w	r2, r2, #131072	; 0x20000
 800a21e:	61da      	str	r2, [r3, #28]
 800a220:	69da      	ldr	r2, [r3, #28]
    GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
 800a222:	2600      	movs	r6, #0
    __HAL_RCC_USART2_CLK_ENABLE();
 800a224:	f402 3200 	and.w	r2, r2, #131072	; 0x20000
 800a228:	9204      	str	r2, [sp, #16]
 800a22a:	9a04      	ldr	r2, [sp, #16]
    __HAL_RCC_GPIOA_CLK_ENABLE();
 800a22c:	699a      	ldr	r2, [r3, #24]
    hdma_usart2_rx.Instance = DMA1_Channel6;
 800a22e:	4c21      	ldr	r4, [pc, #132]	; (800a2b4 <HAL_UART_MspInit+0x1bc>)
    __HAL_RCC_GPIOA_CLK_ENABLE();
 800a230:	f042 0204 	orr.w	r2, r2, #4
 800a234:	619a      	str	r2, [r3, #24]
 800a236:	699b      	ldr	r3, [r3, #24]
 800a238:	f003 0304 	and.w	r3, r3, #4
 800a23c:	9305      	str	r3, [sp, #20]
 800a23e:	9b05      	ldr	r3, [sp, #20]
    GPIO_InitStruct.Pin = GPIO_PIN_2;
 800a240:	2304      	movs	r3, #4
 800a242:	9306      	str	r3, [sp, #24]
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 800a244:	2302      	movs	r3, #2
 800a246:	9307      	str	r3, [sp, #28]
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
 800a248:	2303      	movs	r3, #3
 800a24a:	9309      	str	r3, [sp, #36]	; 0x24
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 800a24c:	f7fe fc20 	bl	8008a90 <HAL_GPIO_Init>
    GPIO_InitStruct.Pin = GPIO_PIN_3;
 800a250:	2308      	movs	r3, #8
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 800a252:	4812      	ldr	r0, [pc, #72]	; (800a29c <HAL_UART_MspInit+0x1a4>)
 800a254:	a906      	add	r1, sp, #24
    GPIO_InitStruct.Pin = GPIO_PIN_3;
 800a256:	9306      	str	r3, [sp, #24]
    GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
 800a258:	9607      	str	r6, [sp, #28]
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 800a25a:	9608      	str	r6, [sp, #32]
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 800a25c:	f7fe fc18 	bl	8008a90 <HAL_GPIO_Init>
    hdma_usart2_rx.Instance = DMA1_Channel6;
 800a260:	4b15      	ldr	r3, [pc, #84]	; (800a2b8 <HAL_UART_MspInit+0x1c0>)
    if (HAL_DMA_Init(&hdma_usart2_rx) != HAL_OK)
 800a262:	4620      	mov	r0, r4
    hdma_usart2_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
 800a264:	e884 0048 	stmia.w	r4, {r3, r6}
    hdma_usart2_rx.Init.MemInc = DMA_MINC_ENABLE;
 800a268:	2380      	movs	r3, #128	; 0x80
    hdma_usart2_rx.Init.PeriphInc = DMA_PINC_DISABLE;
 800a26a:	60a6      	str	r6, [r4, #8]
    hdma_usart2_rx.Init.MemInc = DMA_MINC_ENABLE;
 800a26c:	60e3      	str	r3, [r4, #12]
    hdma_usart2_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
 800a26e:	6126      	str	r6, [r4, #16]
    hdma_usart2_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
 800a270:	6166      	str	r6, [r4, #20]
    hdma_usart2_rx.Init.Mode = DMA_NORMAL;
 800a272:	61a6      	str	r6, [r4, #24]
    hdma_usart2_rx.Init.Priority = DMA_PRIORITY_LOW;
 800a274:	61e6      	str	r6, [r4, #28]
    if (HAL_DMA_Init(&hdma_usart2_rx) != HAL_OK)
 800a276:	f7fe fa43 	bl	8008700 <HAL_DMA_Init>
 800a27a:	b108      	cbz	r0, 800a280 <HAL_UART_MspInit+0x188>
      Error_Handler();
 800a27c:	f7ff fe9a 	bl	8009fb4 <Error_Handler>
    __HAL_LINKDMA(huart,hdmarx,hdma_usart2_rx);
 800a280:	636c      	str	r4, [r5, #52]	; 0x34
 800a282:	6265      	str	r5, [r4, #36]	; 0x24
    hdma_usart2_tx.Instance = DMA1_Channel7;
 800a284:	4b0d      	ldr	r3, [pc, #52]	; (800a2bc <HAL_UART_MspInit+0x1c4>)
 800a286:	4c0e      	ldr	r4, [pc, #56]	; (800a2c0 <HAL_UART_MspInit+0x1c8>)
 800a288:	e7ac      	b.n	800a1e4 <HAL_UART_MspInit+0xec>
 800a28a:	bf00      	nop
 800a28c:	40004c00 	.word	0x40004c00
 800a290:	40021000 	.word	0x40021000
 800a294:	40011000 	.word	0x40011000
 800a298:	40013800 	.word	0x40013800
 800a29c:	40010800 	.word	0x40010800
 800a2a0:	200003c0 	.word	0x200003c0
 800a2a4:	40020058 	.word	0x40020058
 800a2a8:	40020044 	.word	0x40020044
 800a2ac:	2000031c 	.word	0x2000031c
 800a2b0:	40004400 	.word	0x40004400
 800a2b4:	200002a8 	.word	0x200002a8
 800a2b8:	4002006c 	.word	0x4002006c
 800a2bc:	40020080 	.word	0x40020080
 800a2c0:	20000404 	.word	0x20000404

0800a2c4 <NMI_Handler>:
 800a2c4:	4770      	bx	lr

0800a2c6 <HardFault_Handler>:

/**
  * @brief This function handles Hard fault interrupt.
  */
void HardFault_Handler(void)
{
 800a2c6:	e7fe      	b.n	800a2c6 <HardFault_Handler>

0800a2c8 <MemManage_Handler>:

/**
  * @brief This function handles Memory management fault.
  */
void MemManage_Handler(void)
{
 800a2c8:	e7fe      	b.n	800a2c8 <MemManage_Handler>

0800a2ca <BusFault_Handler>:

/**
  * @brief This function handles Prefetch fault, memory access fault.
  */
void BusFault_Handler(void)
{
 800a2ca:	e7fe      	b.n	800a2ca <BusFault_Handler>

0800a2cc <UsageFault_Handler>:

/**
  * @brief This function handles Undefined instruction or illegal state.
  */
void UsageFault_Handler(void)
{
 800a2cc:	e7fe      	b.n	800a2cc <UsageFault_Handler>

0800a2ce <SVC_Handler>:
 800a2ce:	4770      	bx	lr

0800a2d0 <DebugMon_Handler>:
 800a2d0:	4770      	bx	lr

0800a2d2 <PendSV_Handler>:

/**
  * @brief This function handles Pendable request for system service.
  */
void PendSV_Handler(void)
{
 800a2d2:	4770      	bx	lr

0800a2d4 <SysTick_Handler>:
void SysTick_Handler(void)
{
  /* USER CODE BEGIN SysTick_IRQn 0 */

  /* USER CODE END SysTick_IRQn 0 */
  HAL_IncTick();
 800a2d4:	f7fd bfdc 	b.w	8008290 <HAL_IncTick>

0800a2d8 <DMA1_Channel4_IRQHandler>:
void DMA1_Channel4_IRQHandler(void)
{
  /* USER CODE BEGIN DMA1_Channel4_IRQn 0 */

  /* USER CODE END DMA1_Channel4_IRQn 0 */
  HAL_DMA_IRQHandler(&hdma_usart1_tx);
 800a2d8:	4801      	ldr	r0, [pc, #4]	; (800a2e0 <DMA1_Channel4_IRQHandler+0x8>)
 800a2da:	f7fe bafd 	b.w	80088d8 <HAL_DMA_IRQHandler>
 800a2de:	bf00      	nop
 800a2e0:	2000031c 	.word	0x2000031c

0800a2e4 <DMA1_Channel5_IRQHandler>:
void DMA1_Channel5_IRQHandler(void)
{
  /* USER CODE BEGIN DMA1_Channel5_IRQn 0 */

  /* USER CODE END DMA1_Channel5_IRQn 0 */
  HAL_DMA_IRQHandler(&hdma_usart1_rx);
 800a2e4:	4801      	ldr	r0, [pc, #4]	; (800a2ec <DMA1_Channel5_IRQHandler+0x8>)
 800a2e6:	f7fe baf7 	b.w	80088d8 <HAL_DMA_IRQHandler>
 800a2ea:	bf00      	nop
 800a2ec:	200003c0 	.word	0x200003c0

0800a2f0 <DMA1_Channel6_IRQHandler>:
void DMA1_Channel6_IRQHandler(void)
{
  /* USER CODE BEGIN DMA1_Channel6_IRQn 0 */

  /* USER CODE END DMA1_Channel6_IRQn 0 */
  HAL_DMA_IRQHandler(&hdma_usart2_rx);
 800a2f0:	4801      	ldr	r0, [pc, #4]	; (800a2f8 <DMA1_Channel6_IRQHandler+0x8>)
 800a2f2:	f7fe baf1 	b.w	80088d8 <HAL_DMA_IRQHandler>
 800a2f6:	bf00      	nop
 800a2f8:	200002a8 	.word	0x200002a8

0800a2fc <DMA1_Channel7_IRQHandler>:
void DMA1_Channel7_IRQHandler(void)
{
  /* USER CODE BEGIN DMA1_Channel7_IRQn 0 */

  /* USER CODE END DMA1_Channel7_IRQn 0 */
  HAL_DMA_IRQHandler(&hdma_usart2_tx);
 800a2fc:	4801      	ldr	r0, [pc, #4]	; (800a304 <DMA1_Channel7_IRQHandler+0x8>)
 800a2fe:	f7fe baeb 	b.w	80088d8 <HAL_DMA_IRQHandler>
 800a302:	bf00      	nop
 800a304:	20000404 	.word	0x20000404

0800a308 <ADC1_2_IRQHandler>:

/**
  * @brief This function handles ADC1 and ADC2 global interrupts.
  */
void ADC1_2_IRQHandler(void)
{
 800a308:	b508      	push	{r3, lr}
  /* USER CODE BEGIN ADC1_2_IRQn 0 */

  /* USER CODE END ADC1_2_IRQn 0 */
  HAL_ADC_IRQHandler(&hadc1);
 800a30a:	4804      	ldr	r0, [pc, #16]	; (800a31c <ADC1_2_IRQHandler+0x14>)
 800a30c:	f7fd ffe6 	bl	80082dc <HAL_ADC_IRQHandler>
  HAL_ADC_IRQHandler(&hadc2);
  /* USER CODE BEGIN ADC1_2_IRQn 1 */

  /* USER CODE END ADC1_2_IRQn 1 */
}
 800a310:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
  HAL_ADC_IRQHandler(&hadc2);
 800a314:	4802      	ldr	r0, [pc, #8]	; (800a320 <ADC1_2_IRQHandler+0x18>)
 800a316:	f7fd bfe1 	b.w	80082dc <HAL_ADC_IRQHandler>
 800a31a:	bf00      	nop
 800a31c:	20000360 	.word	0x20000360
 800a320:	200002ec 	.word	0x200002ec

0800a324 <USART1_IRQHandler>:
void USART1_IRQHandler(void)
{
  /* USER CODE BEGIN USART1_IRQn 0 */

  /* USER CODE END USART1_IRQn 0 */
  HAL_UART_IRQHandler(&huart1);
 800a324:	4801      	ldr	r0, [pc, #4]	; (800a32c <USART1_IRQHandler+0x8>)
 800a326:	f7ff bb19 	b.w	800995c <HAL_UART_IRQHandler>
 800a32a:	bf00      	nop
 800a32c:	20000448 	.word	0x20000448

0800a330 <USART2_IRQHandler>:
void USART2_IRQHandler(void)
{
  /* USER CODE BEGIN USART2_IRQn 0 */

  /* USER CODE END USART2_IRQn 0 */
  HAL_UART_IRQHandler(&huart2);
 800a330:	4801      	ldr	r0, [pc, #4]	; (800a338 <USART2_IRQHandler+0x8>)
 800a332:	f7ff bb13 	b.w	800995c <HAL_UART_IRQHandler>
 800a336:	bf00      	nop
 800a338:	20000508 	.word	0x20000508

0800a33c <ADC3_IRQHandler>:
void ADC3_IRQHandler(void)
{
  /* USER CODE BEGIN ADC3_IRQn 0 */

  /* USER CODE END ADC3_IRQn 0 */
  HAL_ADC_IRQHandler(&hadc3);
 800a33c:	4801      	ldr	r0, [pc, #4]	; (800a344 <ADC3_IRQHandler+0x8>)
 800a33e:	f7fd bfcd 	b.w	80082dc <HAL_ADC_IRQHandler>
 800a342:	bf00      	nop
 800a344:	20000390 	.word	0x20000390

0800a348 <UART4_IRQHandler>:
void UART4_IRQHandler(void)
{
  /* USER CODE BEGIN UART4_IRQn 0 */

  /* USER CODE END UART4_IRQn 0 */
  HAL_UART_IRQHandler(&huart4);
 800a348:	4801      	ldr	r0, [pc, #4]	; (800a350 <UART4_IRQHandler+0x8>)
 800a34a:	f7ff bb07 	b.w	800995c <HAL_UART_IRQHandler>
 800a34e:	bf00      	nop
 800a350:	200004c8 	.word	0x200004c8

0800a354 <TIM6_IRQHandler>:
void TIM6_IRQHandler(void)
{
  /* USER CODE BEGIN TIM6_IRQn 0 */

  /* USER CODE END TIM6_IRQn 0 */
  HAL_TIM_IRQHandler(&htim6);
 800a354:	4801      	ldr	r0, [pc, #4]	; (800a35c <TIM6_IRQHandler+0x8>)
 800a356:	f7fe bfb7 	b.w	80092c8 <HAL_TIM_IRQHandler>
 800a35a:	bf00      	nop
 800a35c:	20000488 	.word	0x20000488

0800a360 <_read>:
	_kill(status, -1);
	while (1) {}		/* Make sure we hang here */
}

__attribute__((weak)) int _read(int file, char *ptr, int len)
{
 800a360:	b570      	push	{r4, r5, r6, lr}
 800a362:	460e      	mov	r6, r1
 800a364:	4615      	mov	r5, r2
	int DataIdx;

	for (DataIdx = 0; DataIdx < len; DataIdx++)
 800a366:	460c      	mov	r4, r1
 800a368:	1ba3      	subs	r3, r4, r6
 800a36a:	429d      	cmp	r5, r3
 800a36c:	dc01      	bgt.n	800a372 <_read+0x12>
	{
		*ptr++ = __io_getchar();
	}

return len;
}
 800a36e:	4628      	mov	r0, r5
 800a370:	bd70      	pop	{r4, r5, r6, pc}
		*ptr++ = __io_getchar();
 800a372:	f3af 8000 	nop.w
 800a376:	f804 0b01 	strb.w	r0, [r4], #1
 800a37a:	e7f5      	b.n	800a368 <_read+0x8>

0800a37c <_sbrk>:
	}
	return len;
}

caddr_t _sbrk(int incr)
{
 800a37c:	b508      	push	{r3, lr}
	extern char end asm("end");
	static char *heap_end;
	char *prev_heap_end;

	if (heap_end == 0)
 800a37e:	4b0a      	ldr	r3, [pc, #40]	; (800a3a8 <_sbrk+0x2c>)
{
 800a380:	4602      	mov	r2, r0
	if (heap_end == 0)
 800a382:	6819      	ldr	r1, [r3, #0]
 800a384:	b909      	cbnz	r1, 800a38a <_sbrk+0xe>
		heap_end = &end;
 800a386:	4909      	ldr	r1, [pc, #36]	; (800a3ac <_sbrk+0x30>)
 800a388:	6019      	str	r1, [r3, #0]

	prev_heap_end = heap_end;
	if (heap_end + incr > stack_ptr)
 800a38a:	4669      	mov	r1, sp
	prev_heap_end = heap_end;
 800a38c:	6818      	ldr	r0, [r3, #0]
	if (heap_end + incr > stack_ptr)
 800a38e:	4402      	add	r2, r0
 800a390:	428a      	cmp	r2, r1
 800a392:	d906      	bls.n	800a3a2 <_sbrk+0x26>
	{
//		write(1, "Heap and stack collision\n", 25);
//		abort();
		errno = ENOMEM;
 800a394:	f000 f8ca 	bl	800a52c <__errno>
 800a398:	230c      	movs	r3, #12
 800a39a:	6003      	str	r3, [r0, #0]
		return (caddr_t) -1;
 800a39c:	f04f 30ff 	mov.w	r0, #4294967295
 800a3a0:	bd08      	pop	{r3, pc}
	}

	heap_end += incr;
 800a3a2:	601a      	str	r2, [r3, #0]

	return (caddr_t) prev_heap_end;
}
 800a3a4:	bd08      	pop	{r3, pc}
 800a3a6:	bf00      	nop
 800a3a8:	20000298 	.word	0x20000298
 800a3ac:	20000d64 	.word	0x20000d64

0800a3b0 <_close>:

int _close(int file)
{
	return -1;
}
 800a3b0:	f04f 30ff 	mov.w	r0, #4294967295
 800a3b4:	4770      	bx	lr

0800a3b6 <_fstat>:


int _fstat(int file, struct stat *st)
{
	st->st_mode = S_IFCHR;
 800a3b6:	f44f 5300 	mov.w	r3, #8192	; 0x2000
	return 0;
}
 800a3ba:	2000      	movs	r0, #0
	st->st_mode = S_IFCHR;
 800a3bc:	604b      	str	r3, [r1, #4]
}
 800a3be:	4770      	bx	lr

0800a3c0 <_isatty>:

int _isatty(int file)
{
	return 1;
}
 800a3c0:	2001      	movs	r0, #1
 800a3c2:	4770      	bx	lr

0800a3c4 <_lseek>:

int _lseek(int file, int ptr, int dir)
{
	return 0;
}
 800a3c4:	2000      	movs	r0, #0
 800a3c6:	4770      	bx	lr

0800a3c8 <SystemInit>:
  */
void SystemInit (void)
{
  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
  /* Set HSION bit */
  RCC->CR |= 0x00000001U;
 800a3c8:	4b0e      	ldr	r3, [pc, #56]	; (800a404 <SystemInit+0x3c>)
 800a3ca:	681a      	ldr	r2, [r3, #0]
 800a3cc:	f042 0201 	orr.w	r2, r2, #1
 800a3d0:	601a      	str	r2, [r3, #0]

  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
#if !defined(STM32F105xC) && !defined(STM32F107xC)
  RCC->CFGR &= 0xF8FF0000U;
 800a3d2:	6859      	ldr	r1, [r3, #4]
 800a3d4:	4a0c      	ldr	r2, [pc, #48]	; (800a408 <SystemInit+0x40>)
 800a3d6:	400a      	ands	r2, r1
 800a3d8:	605a      	str	r2, [r3, #4]
#else
  RCC->CFGR &= 0xF0FF0000U;
#endif /* STM32F105xC */   
  
  /* Reset HSEON, CSSON and PLLON bits */
  RCC->CR &= 0xFEF6FFFFU;
 800a3da:	681a      	ldr	r2, [r3, #0]
 800a3dc:	f022 7284 	bic.w	r2, r2, #17301504	; 0x1080000
 800a3e0:	f422 3280 	bic.w	r2, r2, #65536	; 0x10000
 800a3e4:	601a      	str	r2, [r3, #0]

  /* Reset HSEBYP bit */
  RCC->CR &= 0xFFFBFFFFU;
 800a3e6:	681a      	ldr	r2, [r3, #0]
 800a3e8:	f422 2280 	bic.w	r2, r2, #262144	; 0x40000
 800a3ec:	601a      	str	r2, [r3, #0]

  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
  RCC->CFGR &= 0xFF80FFFFU;
 800a3ee:	685a      	ldr	r2, [r3, #4]
 800a3f0:	f422 02fe 	bic.w	r2, r2, #8323072	; 0x7f0000
 800a3f4:	605a      	str	r2, [r3, #4]

  /* Reset CFGR2 register */
  RCC->CFGR2 = 0x00000000U;      
#else
  /* Disable all interrupts and clear pending bits  */
  RCC->CIR = 0x009F0000U;
 800a3f6:	f44f 021f 	mov.w	r2, #10420224	; 0x9f0000
 800a3fa:	609a      	str	r2, [r3, #8]
#endif 

#ifdef VECT_TAB_SRAM
  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#else
  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
 800a3fc:	4a03      	ldr	r2, [pc, #12]	; (800a40c <SystemInit+0x44>)
 800a3fe:	4b04      	ldr	r3, [pc, #16]	; (800a410 <SystemInit+0x48>)
 800a400:	609a      	str	r2, [r3, #8]
 800a402:	4770      	bx	lr
 800a404:	40021000 	.word	0x40021000
 800a408:	f8ff0000 	.word	0xf8ff0000
 800a40c:	08008000 	.word	0x08008000
 800a410:	e000ed00 	.word	0xe000ed00

0800a414 <InitUartQueue>:

UARTQUEUE TerminalQueue;
UARTQUEUE WifiQueue;
void InitUartQueue(pUARTQUEUE pQueue)
{
    pQueue->data = pQueue->head = pQueue->tail = 0;
 800a414:	2300      	movs	r3, #0

    if (HAL_UART_Receive_DMA(&hTerminal, TerminalQueue.Buffer, 1) != HAL_OK)
 800a416:	2201      	movs	r2, #1
    pQueue->data = pQueue->head = pQueue->tail = 0;
 800a418:	6043      	str	r3, [r0, #4]
 800a41a:	6003      	str	r3, [r0, #0]
 800a41c:	6083      	str	r3, [r0, #8]
    if (HAL_UART_Receive_DMA(&hTerminal, TerminalQueue.Buffer, 1) != HAL_OK)
 800a41e:	4902      	ldr	r1, [pc, #8]	; (800a428 <InitUartQueue+0x14>)
 800a420:	4802      	ldr	r0, [pc, #8]	; (800a42c <InitUartQueue+0x18>)
 800a422:	f7ff b9ad 	b.w	8009780 <HAL_UART_Receive_DMA>
 800a426:	bf00      	nop
 800a428:	20000554 	.word	0x20000554
 800a42c:	20000448 	.word	0x20000448

0800a430 <GetDataFromUartQueue>:
    if (pQueue->head == QUEUE_BUFFER_LENGTH) pQueue->head = 0;
    pQueue->data++;
   // HAL_UART_Receive_DMA(&hTerminal,  pQueue->Buffer + pQueue->head, 10);
}
void GetDataFromUartQueue(UART_HandleTypeDef *huart)
{
 800a430:	b538      	push	{r3, r4, r5, lr}
    UART_HandleTypeDef *dst = (huart->Instance == USART2 ? &hWifi:&hTerminal);
 800a432:	6801      	ldr	r1, [r0, #0]
 800a434:	4b13      	ldr	r3, [pc, #76]	; (800a484 <GetDataFromUartQueue+0x54>)
 800a436:	4a14      	ldr	r2, [pc, #80]	; (800a488 <GetDataFromUartQueue+0x58>)
 800a438:	4d14      	ldr	r5, [pc, #80]	; (800a48c <GetDataFromUartQueue+0x5c>)
    pUARTQUEUE pQueue = &TerminalQueue;
    printf("Function : %s : ",__func__);
    if (HAL_UART_Transmit(dst, pQueue->Buffer + pQueue->tail, 1, 3000) != HAL_OK)
 800a43a:	4c15      	ldr	r4, [pc, #84]	; (800a490 <GetDataFromUartQueue+0x60>)
    UART_HandleTypeDef *dst = (huart->Instance == USART2 ? &hWifi:&hTerminal);
 800a43c:	4291      	cmp	r1, r2
 800a43e:	bf18      	it	ne
 800a440:	461d      	movne	r5, r3
    printf("Function : %s : ",__func__);
 800a442:	4814      	ldr	r0, [pc, #80]	; (800a494 <GetDataFromUartQueue+0x64>)
 800a444:	4914      	ldr	r1, [pc, #80]	; (800a498 <GetDataFromUartQueue+0x68>)
 800a446:	f000 f8a3 	bl	800a590 <iprintf>
    if (HAL_UART_Transmit(dst, pQueue->Buffer + pQueue->tail, 1, 3000) != HAL_OK)
 800a44a:	6861      	ldr	r1, [r4, #4]
 800a44c:	f104 000c 	add.w	r0, r4, #12
 800a450:	f640 33b8 	movw	r3, #3000	; 0xbb8
 800a454:	4401      	add	r1, r0
 800a456:	2201      	movs	r2, #1
 800a458:	4628      	mov	r0, r5
 800a45a:	f7ff f8fb 	bl	8009654 <HAL_UART_Transmit>
    {
     //  _Error_Handler(__FILE__, __LINE__);
    }
    printf("\r\n");
 800a45e:	480f      	ldr	r0, [pc, #60]	; (800a49c <GetDataFromUartQueue+0x6c>)
 800a460:	f000 f90a 	bl	800a678 <puts>
    pQueue->tail++;
 800a464:	6863      	ldr	r3, [r4, #4]
    if (pQueue->tail >= QUEUE_BUFFER_LENGTH) pQueue->tail = 0;
    pQueue->data--;
    HAL_Delay(1);
 800a466:	2001      	movs	r0, #1
    pQueue->tail++;
 800a468:	3301      	adds	r3, #1
    if (pQueue->tail >= QUEUE_BUFFER_LENGTH) pQueue->tail = 0;
 800a46a:	f5b3 6f80 	cmp.w	r3, #1024	; 0x400
 800a46e:	bfa8      	it	ge
 800a470:	2300      	movge	r3, #0
 800a472:	6063      	str	r3, [r4, #4]
    pQueue->data--;
 800a474:	68a3      	ldr	r3, [r4, #8]
 800a476:	3b01      	subs	r3, #1
 800a478:	60a3      	str	r3, [r4, #8]
}
 800a47a:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
    HAL_Delay(1);
 800a47e:	f7fd bf19 	b.w	80082b4 <HAL_Delay>
 800a482:	bf00      	nop
 800a484:	20000448 	.word	0x20000448
 800a488:	40004400 	.word	0x40004400
 800a48c:	20000508 	.word	0x20000508
 800a490:	20000548 	.word	0x20000548
 800a494:	0800b6ac 	.word	0x0800b6ac
 800a498:	0800b6bd 	.word	0x0800b6bd
 800a49c:	0800b692 	.word	0x0800b692

0800a4a0 <HAL_UART_RxCpltCallback>:
{
 800a4a0:	b510      	push	{r4, lr}
    pQueue->head++;
 800a4a2:	4c0c      	ldr	r4, [pc, #48]	; (800a4d4 <HAL_UART_RxCpltCallback+0x34>)
 800a4a4:	6823      	ldr	r3, [r4, #0]
 800a4a6:	3301      	adds	r3, #1
    if (pQueue->head >= QUEUE_BUFFER_LENGTH) pQueue->head = 0;
 800a4a8:	f5b3 6f80 	cmp.w	r3, #1024	; 0x400
 800a4ac:	bfa8      	it	ge
 800a4ae:	2300      	movge	r3, #0
 800a4b0:	6023      	str	r3, [r4, #0]
    pQueue->data++;
 800a4b2:	68a3      	ldr	r3, [r4, #8]
 800a4b4:	3301      	adds	r3, #1
    if (pQueue->data >= QUEUE_BUFFER_LENGTH)
 800a4b6:	f5b3 6f80 	cmp.w	r3, #1024	; 0x400
    pQueue->data++;
 800a4ba:	60a3      	str	r3, [r4, #8]
    if (pQueue->data >= QUEUE_BUFFER_LENGTH)
 800a4bc:	db01      	blt.n	800a4c2 <HAL_UART_RxCpltCallback+0x22>
        GetDataFromUartQueue(huart);
 800a4be:	f7ff ffb7 	bl	800a430 <GetDataFromUartQueue>
    HAL_UART_Receive_DMA(&hTerminal, pQueue->Buffer + pQueue->head, 1);
 800a4c2:	6823      	ldr	r3, [r4, #0]
 800a4c4:	4904      	ldr	r1, [pc, #16]	; (800a4d8 <HAL_UART_RxCpltCallback+0x38>)
 800a4c6:	2201      	movs	r2, #1
}
 800a4c8:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
    HAL_UART_Receive_DMA(&hTerminal, pQueue->Buffer + pQueue->head, 1);
 800a4cc:	4419      	add	r1, r3
 800a4ce:	4803      	ldr	r0, [pc, #12]	; (800a4dc <HAL_UART_RxCpltCallback+0x3c>)
 800a4d0:	f7ff b956 	b.w	8009780 <HAL_UART_Receive_DMA>
 800a4d4:	20000548 	.word	0x20000548
 800a4d8:	20000554 	.word	0x20000554
 800a4dc:	20000448 	.word	0x20000448

0800a4e0 <Reset_Handler>:
  .weak Reset_Handler
  .type Reset_Handler, %function
Reset_Handler:

/* Copy the data segment initializers from flash to SRAM */
  movs r1, #0
 800a4e0:	2100      	movs	r1, #0
  b LoopCopyDataInit
 800a4e2:	e003      	b.n	800a4ec <LoopCopyDataInit>

0800a4e4 <CopyDataInit>:

CopyDataInit:
  ldr r3, =_sidata
 800a4e4:	4b0b      	ldr	r3, [pc, #44]	; (800a514 <LoopFillZerobss+0x14>)
  ldr r3, [r3, r1]
 800a4e6:	585b      	ldr	r3, [r3, r1]
  str r3, [r0, r1]
 800a4e8:	5043      	str	r3, [r0, r1]
  adds r1, r1, #4
 800a4ea:	3104      	adds	r1, #4

0800a4ec <LoopCopyDataInit>:

LoopCopyDataInit:
  ldr r0, =_sdata
 800a4ec:	480a      	ldr	r0, [pc, #40]	; (800a518 <LoopFillZerobss+0x18>)
  ldr r3, =_edata
 800a4ee:	4b0b      	ldr	r3, [pc, #44]	; (800a51c <LoopFillZerobss+0x1c>)
  adds r2, r0, r1
 800a4f0:	1842      	adds	r2, r0, r1
  cmp r2, r3
 800a4f2:	429a      	cmp	r2, r3
  bcc CopyDataInit
 800a4f4:	d3f6      	bcc.n	800a4e4 <CopyDataInit>
  ldr r2, =_sbss
 800a4f6:	4a0a      	ldr	r2, [pc, #40]	; (800a520 <LoopFillZerobss+0x20>)
  b LoopFillZerobss
 800a4f8:	e002      	b.n	800a500 <LoopFillZerobss>

0800a4fa <FillZerobss>:
/* Zero fill the bss segment. */
FillZerobss:
  movs r3, #0
 800a4fa:	2300      	movs	r3, #0
  str r3, [r2], #4
 800a4fc:	f842 3b04 	str.w	r3, [r2], #4

0800a500 <LoopFillZerobss>:

LoopFillZerobss:
  ldr r3, = _ebss
 800a500:	4b08      	ldr	r3, [pc, #32]	; (800a524 <LoopFillZerobss+0x24>)
  cmp r2, r3
 800a502:	429a      	cmp	r2, r3
  bcc FillZerobss
 800a504:	d3f9      	bcc.n	800a4fa <FillZerobss>

/* Call the clock system intitialization function.*/
    bl  SystemInit
 800a506:	f7ff ff5f 	bl	800a3c8 <SystemInit>
/* Call static constructors */
    bl __libc_init_array
 800a50a:	f000 f815 	bl	800a538 <__libc_init_array>
/* Call the application's entry point.*/
  bl main
 800a50e:	f7ff fb4d 	bl	8009bac <main>
  bx lr
 800a512:	4770      	bx	lr
  ldr r3, =_sidata
 800a514:	0800b774 	.word	0x0800b774
  ldr r0, =_sdata
 800a518:	20000000 	.word	0x20000000
  ldr r3, =_edata
 800a51c:	20000270 	.word	0x20000270
  ldr r2, =_sbss
 800a520:	20000270 	.word	0x20000270
  ldr r3, = _ebss
 800a524:	20000d64 	.word	0x20000d64

0800a528 <CAN1_RX1_IRQHandler>:
 * @retval : None
*/
    .section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
  b Infinite_Loop
 800a528:	e7fe      	b.n	800a528 <CAN1_RX1_IRQHandler>
	...

0800a52c <__errno>:
 800a52c:	4b01      	ldr	r3, [pc, #4]	; (800a534 <__errno+0x8>)
 800a52e:	6818      	ldr	r0, [r3, #0]
 800a530:	4770      	bx	lr
 800a532:	bf00      	nop
 800a534:	2000020c 	.word	0x2000020c

0800a538 <__libc_init_array>:
 800a538:	b570      	push	{r4, r5, r6, lr}
 800a53a:	2500      	movs	r5, #0
 800a53c:	4e0c      	ldr	r6, [pc, #48]	; (800a570 <__libc_init_array+0x38>)
 800a53e:	4c0d      	ldr	r4, [pc, #52]	; (800a574 <__libc_init_array+0x3c>)
 800a540:	1ba4      	subs	r4, r4, r6
 800a542:	10a4      	asrs	r4, r4, #2
 800a544:	42a5      	cmp	r5, r4
 800a546:	d109      	bne.n	800a55c <__libc_init_array+0x24>
 800a548:	f001 f848 	bl	800b5dc <_init>
 800a54c:	2500      	movs	r5, #0
 800a54e:	4e0a      	ldr	r6, [pc, #40]	; (800a578 <__libc_init_array+0x40>)
 800a550:	4c0a      	ldr	r4, [pc, #40]	; (800a57c <__libc_init_array+0x44>)
 800a552:	1ba4      	subs	r4, r4, r6
 800a554:	10a4      	asrs	r4, r4, #2
 800a556:	42a5      	cmp	r5, r4
 800a558:	d105      	bne.n	800a566 <__libc_init_array+0x2e>
 800a55a:	bd70      	pop	{r4, r5, r6, pc}
 800a55c:	f856 3025 	ldr.w	r3, [r6, r5, lsl #2]
 800a560:	4798      	blx	r3
 800a562:	3501      	adds	r5, #1
 800a564:	e7ee      	b.n	800a544 <__libc_init_array+0xc>
 800a566:	f856 3025 	ldr.w	r3, [r6, r5, lsl #2]
 800a56a:	4798      	blx	r3
 800a56c:	3501      	adds	r5, #1
 800a56e:	e7f2      	b.n	800a556 <__libc_init_array+0x1e>
 800a570:	0800b76c 	.word	0x0800b76c
 800a574:	0800b76c 	.word	0x0800b76c
 800a578:	0800b76c 	.word	0x0800b76c
 800a57c:	0800b770 	.word	0x0800b770

0800a580 <memset>:
 800a580:	4603      	mov	r3, r0
 800a582:	4402      	add	r2, r0
 800a584:	4293      	cmp	r3, r2
 800a586:	d100      	bne.n	800a58a <memset+0xa>
 800a588:	4770      	bx	lr
 800a58a:	f803 1b01 	strb.w	r1, [r3], #1
 800a58e:	e7f9      	b.n	800a584 <memset+0x4>

0800a590 <iprintf>:
 800a590:	b40f      	push	{r0, r1, r2, r3}
 800a592:	4b0a      	ldr	r3, [pc, #40]	; (800a5bc <iprintf+0x2c>)
 800a594:	b513      	push	{r0, r1, r4, lr}
 800a596:	681c      	ldr	r4, [r3, #0]
 800a598:	b124      	cbz	r4, 800a5a4 <iprintf+0x14>
 800a59a:	69a3      	ldr	r3, [r4, #24]
 800a59c:	b913      	cbnz	r3, 800a5a4 <iprintf+0x14>
 800a59e:	4620      	mov	r0, r4
 800a5a0:	f000 fada 	bl	800ab58 <__sinit>
 800a5a4:	ab05      	add	r3, sp, #20
 800a5a6:	9a04      	ldr	r2, [sp, #16]
 800a5a8:	68a1      	ldr	r1, [r4, #8]
 800a5aa:	4620      	mov	r0, r4
 800a5ac:	9301      	str	r3, [sp, #4]
 800a5ae:	f000 fc9b 	bl	800aee8 <_vfiprintf_r>
 800a5b2:	b002      	add	sp, #8
 800a5b4:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
 800a5b8:	b004      	add	sp, #16
 800a5ba:	4770      	bx	lr
 800a5bc:	2000020c 	.word	0x2000020c

0800a5c0 <_puts_r>:
 800a5c0:	b570      	push	{r4, r5, r6, lr}
 800a5c2:	460e      	mov	r6, r1
 800a5c4:	4605      	mov	r5, r0
 800a5c6:	b118      	cbz	r0, 800a5d0 <_puts_r+0x10>
 800a5c8:	6983      	ldr	r3, [r0, #24]
 800a5ca:	b90b      	cbnz	r3, 800a5d0 <_puts_r+0x10>
 800a5cc:	f000 fac4 	bl	800ab58 <__sinit>
 800a5d0:	69ab      	ldr	r3, [r5, #24]
 800a5d2:	68ac      	ldr	r4, [r5, #8]
 800a5d4:	b913      	cbnz	r3, 800a5dc <_puts_r+0x1c>
 800a5d6:	4628      	mov	r0, r5
 800a5d8:	f000 fabe 	bl	800ab58 <__sinit>
 800a5dc:	4b23      	ldr	r3, [pc, #140]	; (800a66c <_puts_r+0xac>)
 800a5de:	429c      	cmp	r4, r3
 800a5e0:	d117      	bne.n	800a612 <_puts_r+0x52>
 800a5e2:	686c      	ldr	r4, [r5, #4]
 800a5e4:	89a3      	ldrh	r3, [r4, #12]
 800a5e6:	071b      	lsls	r3, r3, #28
 800a5e8:	d51d      	bpl.n	800a626 <_puts_r+0x66>
 800a5ea:	6923      	ldr	r3, [r4, #16]
 800a5ec:	b1db      	cbz	r3, 800a626 <_puts_r+0x66>
 800a5ee:	3e01      	subs	r6, #1
 800a5f0:	68a3      	ldr	r3, [r4, #8]
 800a5f2:	f816 1f01 	ldrb.w	r1, [r6, #1]!
 800a5f6:	3b01      	subs	r3, #1
 800a5f8:	60a3      	str	r3, [r4, #8]
 800a5fa:	b9e9      	cbnz	r1, 800a638 <_puts_r+0x78>
 800a5fc:	2b00      	cmp	r3, #0
 800a5fe:	da2e      	bge.n	800a65e <_puts_r+0x9e>
 800a600:	4622      	mov	r2, r4
 800a602:	210a      	movs	r1, #10
 800a604:	4628      	mov	r0, r5
 800a606:	f000 f8f5 	bl	800a7f4 <__swbuf_r>
 800a60a:	3001      	adds	r0, #1
 800a60c:	d011      	beq.n	800a632 <_puts_r+0x72>
 800a60e:	200a      	movs	r0, #10
 800a610:	bd70      	pop	{r4, r5, r6, pc}
 800a612:	4b17      	ldr	r3, [pc, #92]	; (800a670 <_puts_r+0xb0>)
 800a614:	429c      	cmp	r4, r3
 800a616:	d101      	bne.n	800a61c <_puts_r+0x5c>
 800a618:	68ac      	ldr	r4, [r5, #8]
 800a61a:	e7e3      	b.n	800a5e4 <_puts_r+0x24>
 800a61c:	4b15      	ldr	r3, [pc, #84]	; (800a674 <_puts_r+0xb4>)
 800a61e:	429c      	cmp	r4, r3
 800a620:	bf08      	it	eq
 800a622:	68ec      	ldreq	r4, [r5, #12]
 800a624:	e7de      	b.n	800a5e4 <_puts_r+0x24>
 800a626:	4621      	mov	r1, r4
 800a628:	4628      	mov	r0, r5
 800a62a:	f000 f935 	bl	800a898 <__swsetup_r>
 800a62e:	2800      	cmp	r0, #0
 800a630:	d0dd      	beq.n	800a5ee <_puts_r+0x2e>
 800a632:	f04f 30ff 	mov.w	r0, #4294967295
 800a636:	bd70      	pop	{r4, r5, r6, pc}
 800a638:	2b00      	cmp	r3, #0
 800a63a:	da04      	bge.n	800a646 <_puts_r+0x86>
 800a63c:	69a2      	ldr	r2, [r4, #24]
 800a63e:	4293      	cmp	r3, r2
 800a640:	db06      	blt.n	800a650 <_puts_r+0x90>
 800a642:	290a      	cmp	r1, #10
 800a644:	d004      	beq.n	800a650 <_puts_r+0x90>
 800a646:	6823      	ldr	r3, [r4, #0]
 800a648:	1c5a      	adds	r2, r3, #1
 800a64a:	6022      	str	r2, [r4, #0]
 800a64c:	7019      	strb	r1, [r3, #0]
 800a64e:	e7cf      	b.n	800a5f0 <_puts_r+0x30>
 800a650:	4622      	mov	r2, r4
 800a652:	4628      	mov	r0, r5
 800a654:	f000 f8ce 	bl	800a7f4 <__swbuf_r>
 800a658:	3001      	adds	r0, #1
 800a65a:	d1c9      	bne.n	800a5f0 <_puts_r+0x30>
 800a65c:	e7e9      	b.n	800a632 <_puts_r+0x72>
 800a65e:	200a      	movs	r0, #10
 800a660:	6823      	ldr	r3, [r4, #0]
 800a662:	1c5a      	adds	r2, r3, #1
 800a664:	6022      	str	r2, [r4, #0]
 800a666:	7018      	strb	r0, [r3, #0]
 800a668:	bd70      	pop	{r4, r5, r6, pc}
 800a66a:	bf00      	nop
 800a66c:	0800b6f8 	.word	0x0800b6f8
 800a670:	0800b718 	.word	0x0800b718
 800a674:	0800b6d8 	.word	0x0800b6d8

0800a678 <puts>:
 800a678:	4b02      	ldr	r3, [pc, #8]	; (800a684 <puts+0xc>)
 800a67a:	4601      	mov	r1, r0
 800a67c:	6818      	ldr	r0, [r3, #0]
 800a67e:	f7ff bf9f 	b.w	800a5c0 <_puts_r>
 800a682:	bf00      	nop
 800a684:	2000020c 	.word	0x2000020c

0800a688 <setbuf>:
 800a688:	2900      	cmp	r1, #0
 800a68a:	f44f 6380 	mov.w	r3, #1024	; 0x400
 800a68e:	bf0c      	ite	eq
 800a690:	2202      	moveq	r2, #2
 800a692:	2200      	movne	r2, #0
 800a694:	f000 b800 	b.w	800a698 <setvbuf>

0800a698 <setvbuf>:
 800a698:	e92d 43f7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
 800a69c:	461d      	mov	r5, r3
 800a69e:	4b51      	ldr	r3, [pc, #324]	; (800a7e4 <setvbuf+0x14c>)
 800a6a0:	4604      	mov	r4, r0
 800a6a2:	681e      	ldr	r6, [r3, #0]
 800a6a4:	460f      	mov	r7, r1
 800a6a6:	4690      	mov	r8, r2
 800a6a8:	b126      	cbz	r6, 800a6b4 <setvbuf+0x1c>
 800a6aa:	69b3      	ldr	r3, [r6, #24]
 800a6ac:	b913      	cbnz	r3, 800a6b4 <setvbuf+0x1c>
 800a6ae:	4630      	mov	r0, r6
 800a6b0:	f000 fa52 	bl	800ab58 <__sinit>
 800a6b4:	4b4c      	ldr	r3, [pc, #304]	; (800a7e8 <setvbuf+0x150>)
 800a6b6:	429c      	cmp	r4, r3
 800a6b8:	d152      	bne.n	800a760 <setvbuf+0xc8>
 800a6ba:	6874      	ldr	r4, [r6, #4]
 800a6bc:	f1b8 0f02 	cmp.w	r8, #2
 800a6c0:	d006      	beq.n	800a6d0 <setvbuf+0x38>
 800a6c2:	f1b8 0f01 	cmp.w	r8, #1
 800a6c6:	f200 8089 	bhi.w	800a7dc <setvbuf+0x144>
 800a6ca:	2d00      	cmp	r5, #0
 800a6cc:	f2c0 8086 	blt.w	800a7dc <setvbuf+0x144>
 800a6d0:	4621      	mov	r1, r4
 800a6d2:	4630      	mov	r0, r6
 800a6d4:	f000 f9d6 	bl	800aa84 <_fflush_r>
 800a6d8:	6b61      	ldr	r1, [r4, #52]	; 0x34
 800a6da:	b141      	cbz	r1, 800a6ee <setvbuf+0x56>
 800a6dc:	f104 0344 	add.w	r3, r4, #68	; 0x44
 800a6e0:	4299      	cmp	r1, r3
 800a6e2:	d002      	beq.n	800a6ea <setvbuf+0x52>
 800a6e4:	4630      	mov	r0, r6
 800a6e6:	f000 fb2d 	bl	800ad44 <_free_r>
 800a6ea:	2300      	movs	r3, #0
 800a6ec:	6363      	str	r3, [r4, #52]	; 0x34
 800a6ee:	2300      	movs	r3, #0
 800a6f0:	61a3      	str	r3, [r4, #24]
 800a6f2:	6063      	str	r3, [r4, #4]
 800a6f4:	89a3      	ldrh	r3, [r4, #12]
 800a6f6:	061b      	lsls	r3, r3, #24
 800a6f8:	d503      	bpl.n	800a702 <setvbuf+0x6a>
 800a6fa:	6921      	ldr	r1, [r4, #16]
 800a6fc:	4630      	mov	r0, r6
 800a6fe:	f000 fb21 	bl	800ad44 <_free_r>
 800a702:	89a3      	ldrh	r3, [r4, #12]
 800a704:	f1b8 0f02 	cmp.w	r8, #2
 800a708:	f423 634a 	bic.w	r3, r3, #3232	; 0xca0
 800a70c:	f023 0303 	bic.w	r3, r3, #3
 800a710:	81a3      	strh	r3, [r4, #12]
 800a712:	d05d      	beq.n	800a7d0 <setvbuf+0x138>
 800a714:	ab01      	add	r3, sp, #4
 800a716:	466a      	mov	r2, sp
 800a718:	4621      	mov	r1, r4
 800a71a:	4630      	mov	r0, r6
 800a71c:	f000 faa6 	bl	800ac6c <__swhatbuf_r>
 800a720:	89a3      	ldrh	r3, [r4, #12]
 800a722:	4318      	orrs	r0, r3
 800a724:	81a0      	strh	r0, [r4, #12]
 800a726:	bb2d      	cbnz	r5, 800a774 <setvbuf+0xdc>
 800a728:	9d00      	ldr	r5, [sp, #0]
 800a72a:	4628      	mov	r0, r5
 800a72c:	f000 fb02 	bl	800ad34 <malloc>
 800a730:	4607      	mov	r7, r0
 800a732:	2800      	cmp	r0, #0
 800a734:	d14e      	bne.n	800a7d4 <setvbuf+0x13c>
 800a736:	f8dd 9000 	ldr.w	r9, [sp]
 800a73a:	45a9      	cmp	r9, r5
 800a73c:	d13c      	bne.n	800a7b8 <setvbuf+0x120>
 800a73e:	f04f 30ff 	mov.w	r0, #4294967295
 800a742:	89a3      	ldrh	r3, [r4, #12]
 800a744:	f043 0302 	orr.w	r3, r3, #2
 800a748:	81a3      	strh	r3, [r4, #12]
 800a74a:	2300      	movs	r3, #0
 800a74c:	60a3      	str	r3, [r4, #8]
 800a74e:	f104 0347 	add.w	r3, r4, #71	; 0x47
 800a752:	6023      	str	r3, [r4, #0]
 800a754:	6123      	str	r3, [r4, #16]
 800a756:	2301      	movs	r3, #1
 800a758:	6163      	str	r3, [r4, #20]
 800a75a:	b003      	add	sp, #12
 800a75c:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
 800a760:	4b22      	ldr	r3, [pc, #136]	; (800a7ec <setvbuf+0x154>)
 800a762:	429c      	cmp	r4, r3
 800a764:	d101      	bne.n	800a76a <setvbuf+0xd2>
 800a766:	68b4      	ldr	r4, [r6, #8]
 800a768:	e7a8      	b.n	800a6bc <setvbuf+0x24>
 800a76a:	4b21      	ldr	r3, [pc, #132]	; (800a7f0 <setvbuf+0x158>)
 800a76c:	429c      	cmp	r4, r3
 800a76e:	bf08      	it	eq
 800a770:	68f4      	ldreq	r4, [r6, #12]
 800a772:	e7a3      	b.n	800a6bc <setvbuf+0x24>
 800a774:	2f00      	cmp	r7, #0
 800a776:	d0d8      	beq.n	800a72a <setvbuf+0x92>
 800a778:	69b3      	ldr	r3, [r6, #24]
 800a77a:	b913      	cbnz	r3, 800a782 <setvbuf+0xea>
 800a77c:	4630      	mov	r0, r6
 800a77e:	f000 f9eb 	bl	800ab58 <__sinit>
 800a782:	f1b8 0f01 	cmp.w	r8, #1
 800a786:	bf08      	it	eq
 800a788:	89a3      	ldrheq	r3, [r4, #12]
 800a78a:	6027      	str	r7, [r4, #0]
 800a78c:	bf04      	itt	eq
 800a78e:	f043 0301 	orreq.w	r3, r3, #1
 800a792:	81a3      	strheq	r3, [r4, #12]
 800a794:	89a3      	ldrh	r3, [r4, #12]
 800a796:	6127      	str	r7, [r4, #16]
 800a798:	f013 0008 	ands.w	r0, r3, #8
 800a79c:	6165      	str	r5, [r4, #20]
 800a79e:	d01b      	beq.n	800a7d8 <setvbuf+0x140>
 800a7a0:	f013 0001 	ands.w	r0, r3, #1
 800a7a4:	f04f 0300 	mov.w	r3, #0
 800a7a8:	bf1f      	itttt	ne
 800a7aa:	426d      	negne	r5, r5
 800a7ac:	60a3      	strne	r3, [r4, #8]
 800a7ae:	61a5      	strne	r5, [r4, #24]
 800a7b0:	4618      	movne	r0, r3
 800a7b2:	bf08      	it	eq
 800a7b4:	60a5      	streq	r5, [r4, #8]
 800a7b6:	e7d0      	b.n	800a75a <setvbuf+0xc2>
 800a7b8:	4648      	mov	r0, r9
 800a7ba:	f000 fabb 	bl	800ad34 <malloc>
 800a7be:	4607      	mov	r7, r0
 800a7c0:	2800      	cmp	r0, #0
 800a7c2:	d0bc      	beq.n	800a73e <setvbuf+0xa6>
 800a7c4:	89a3      	ldrh	r3, [r4, #12]
 800a7c6:	464d      	mov	r5, r9
 800a7c8:	f043 0380 	orr.w	r3, r3, #128	; 0x80
 800a7cc:	81a3      	strh	r3, [r4, #12]
 800a7ce:	e7d3      	b.n	800a778 <setvbuf+0xe0>
 800a7d0:	2000      	movs	r0, #0
 800a7d2:	e7b6      	b.n	800a742 <setvbuf+0xaa>
 800a7d4:	46a9      	mov	r9, r5
 800a7d6:	e7f5      	b.n	800a7c4 <setvbuf+0x12c>
 800a7d8:	60a0      	str	r0, [r4, #8]
 800a7da:	e7be      	b.n	800a75a <setvbuf+0xc2>
 800a7dc:	f04f 30ff 	mov.w	r0, #4294967295
 800a7e0:	e7bb      	b.n	800a75a <setvbuf+0xc2>
 800a7e2:	bf00      	nop
 800a7e4:	2000020c 	.word	0x2000020c
 800a7e8:	0800b6f8 	.word	0x0800b6f8
 800a7ec:	0800b718 	.word	0x0800b718
 800a7f0:	0800b6d8 	.word	0x0800b6d8

0800a7f4 <__swbuf_r>:
 800a7f4:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 800a7f6:	460e      	mov	r6, r1
 800a7f8:	4614      	mov	r4, r2
 800a7fa:	4605      	mov	r5, r0
 800a7fc:	b118      	cbz	r0, 800a806 <__swbuf_r+0x12>
 800a7fe:	6983      	ldr	r3, [r0, #24]
 800a800:	b90b      	cbnz	r3, 800a806 <__swbuf_r+0x12>
 800a802:	f000 f9a9 	bl	800ab58 <__sinit>
 800a806:	4b21      	ldr	r3, [pc, #132]	; (800a88c <__swbuf_r+0x98>)
 800a808:	429c      	cmp	r4, r3
 800a80a:	d12a      	bne.n	800a862 <__swbuf_r+0x6e>
 800a80c:	686c      	ldr	r4, [r5, #4]
 800a80e:	69a3      	ldr	r3, [r4, #24]
 800a810:	60a3      	str	r3, [r4, #8]
 800a812:	89a3      	ldrh	r3, [r4, #12]
 800a814:	071a      	lsls	r2, r3, #28
 800a816:	d52e      	bpl.n	800a876 <__swbuf_r+0x82>
 800a818:	6923      	ldr	r3, [r4, #16]
 800a81a:	b363      	cbz	r3, 800a876 <__swbuf_r+0x82>
 800a81c:	6923      	ldr	r3, [r4, #16]
 800a81e:	6820      	ldr	r0, [r4, #0]
 800a820:	b2f6      	uxtb	r6, r6
 800a822:	1ac0      	subs	r0, r0, r3
 800a824:	6963      	ldr	r3, [r4, #20]
 800a826:	4637      	mov	r7, r6
 800a828:	4298      	cmp	r0, r3
 800a82a:	db04      	blt.n	800a836 <__swbuf_r+0x42>
 800a82c:	4621      	mov	r1, r4
 800a82e:	4628      	mov	r0, r5
 800a830:	f000 f928 	bl	800aa84 <_fflush_r>
 800a834:	bb28      	cbnz	r0, 800a882 <__swbuf_r+0x8e>
 800a836:	68a3      	ldr	r3, [r4, #8]
 800a838:	3001      	adds	r0, #1
 800a83a:	3b01      	subs	r3, #1
 800a83c:	60a3      	str	r3, [r4, #8]
 800a83e:	6823      	ldr	r3, [r4, #0]
 800a840:	1c5a      	adds	r2, r3, #1
 800a842:	6022      	str	r2, [r4, #0]
 800a844:	701e      	strb	r6, [r3, #0]
 800a846:	6963      	ldr	r3, [r4, #20]
 800a848:	4298      	cmp	r0, r3
 800a84a:	d004      	beq.n	800a856 <__swbuf_r+0x62>
 800a84c:	89a3      	ldrh	r3, [r4, #12]
 800a84e:	07db      	lsls	r3, r3, #31
 800a850:	d519      	bpl.n	800a886 <__swbuf_r+0x92>
 800a852:	2e0a      	cmp	r6, #10
 800a854:	d117      	bne.n	800a886 <__swbuf_r+0x92>
 800a856:	4621      	mov	r1, r4
 800a858:	4628      	mov	r0, r5
 800a85a:	f000 f913 	bl	800aa84 <_fflush_r>
 800a85e:	b190      	cbz	r0, 800a886 <__swbuf_r+0x92>
 800a860:	e00f      	b.n	800a882 <__swbuf_r+0x8e>
 800a862:	4b0b      	ldr	r3, [pc, #44]	; (800a890 <__swbuf_r+0x9c>)
 800a864:	429c      	cmp	r4, r3
 800a866:	d101      	bne.n	800a86c <__swbuf_r+0x78>
 800a868:	68ac      	ldr	r4, [r5, #8]
 800a86a:	e7d0      	b.n	800a80e <__swbuf_r+0x1a>
 800a86c:	4b09      	ldr	r3, [pc, #36]	; (800a894 <__swbuf_r+0xa0>)
 800a86e:	429c      	cmp	r4, r3
 800a870:	bf08      	it	eq
 800a872:	68ec      	ldreq	r4, [r5, #12]
 800a874:	e7cb      	b.n	800a80e <__swbuf_r+0x1a>
 800a876:	4621      	mov	r1, r4
 800a878:	4628      	mov	r0, r5
 800a87a:	f000 f80d 	bl	800a898 <__swsetup_r>
 800a87e:	2800      	cmp	r0, #0
 800a880:	d0cc      	beq.n	800a81c <__swbuf_r+0x28>
 800a882:	f04f 37ff 	mov.w	r7, #4294967295
 800a886:	4638      	mov	r0, r7
 800a888:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
 800a88a:	bf00      	nop
 800a88c:	0800b6f8 	.word	0x0800b6f8
 800a890:	0800b718 	.word	0x0800b718
 800a894:	0800b6d8 	.word	0x0800b6d8

0800a898 <__swsetup_r>:
 800a898:	4b32      	ldr	r3, [pc, #200]	; (800a964 <__swsetup_r+0xcc>)
 800a89a:	b570      	push	{r4, r5, r6, lr}
 800a89c:	681d      	ldr	r5, [r3, #0]
 800a89e:	4606      	mov	r6, r0
 800a8a0:	460c      	mov	r4, r1
 800a8a2:	b125      	cbz	r5, 800a8ae <__swsetup_r+0x16>
 800a8a4:	69ab      	ldr	r3, [r5, #24]
 800a8a6:	b913      	cbnz	r3, 800a8ae <__swsetup_r+0x16>
 800a8a8:	4628      	mov	r0, r5
 800a8aa:	f000 f955 	bl	800ab58 <__sinit>
 800a8ae:	4b2e      	ldr	r3, [pc, #184]	; (800a968 <__swsetup_r+0xd0>)
 800a8b0:	429c      	cmp	r4, r3
 800a8b2:	d10f      	bne.n	800a8d4 <__swsetup_r+0x3c>
 800a8b4:	686c      	ldr	r4, [r5, #4]
 800a8b6:	f9b4 300c 	ldrsh.w	r3, [r4, #12]
 800a8ba:	b29a      	uxth	r2, r3
 800a8bc:	0715      	lsls	r5, r2, #28
 800a8be:	d42c      	bmi.n	800a91a <__swsetup_r+0x82>
 800a8c0:	06d0      	lsls	r0, r2, #27
 800a8c2:	d411      	bmi.n	800a8e8 <__swsetup_r+0x50>
 800a8c4:	2209      	movs	r2, #9
 800a8c6:	6032      	str	r2, [r6, #0]
 800a8c8:	f043 0340 	orr.w	r3, r3, #64	; 0x40
 800a8cc:	81a3      	strh	r3, [r4, #12]
 800a8ce:	f04f 30ff 	mov.w	r0, #4294967295
 800a8d2:	bd70      	pop	{r4, r5, r6, pc}
 800a8d4:	4b25      	ldr	r3, [pc, #148]	; (800a96c <__swsetup_r+0xd4>)
 800a8d6:	429c      	cmp	r4, r3
 800a8d8:	d101      	bne.n	800a8de <__swsetup_r+0x46>
 800a8da:	68ac      	ldr	r4, [r5, #8]
 800a8dc:	e7eb      	b.n	800a8b6 <__swsetup_r+0x1e>
 800a8de:	4b24      	ldr	r3, [pc, #144]	; (800a970 <__swsetup_r+0xd8>)
 800a8e0:	429c      	cmp	r4, r3
 800a8e2:	bf08      	it	eq
 800a8e4:	68ec      	ldreq	r4, [r5, #12]
 800a8e6:	e7e6      	b.n	800a8b6 <__swsetup_r+0x1e>
 800a8e8:	0751      	lsls	r1, r2, #29
 800a8ea:	d512      	bpl.n	800a912 <__swsetup_r+0x7a>
 800a8ec:	6b61      	ldr	r1, [r4, #52]	; 0x34
 800a8ee:	b141      	cbz	r1, 800a902 <__swsetup_r+0x6a>
 800a8f0:	f104 0344 	add.w	r3, r4, #68	; 0x44
 800a8f4:	4299      	cmp	r1, r3
 800a8f6:	d002      	beq.n	800a8fe <__swsetup_r+0x66>
 800a8f8:	4630      	mov	r0, r6
 800a8fa:	f000 fa23 	bl	800ad44 <_free_r>
 800a8fe:	2300      	movs	r3, #0
 800a900:	6363      	str	r3, [r4, #52]	; 0x34
 800a902:	89a3      	ldrh	r3, [r4, #12]
 800a904:	f023 0324 	bic.w	r3, r3, #36	; 0x24
 800a908:	81a3      	strh	r3, [r4, #12]
 800a90a:	2300      	movs	r3, #0
 800a90c:	6063      	str	r3, [r4, #4]
 800a90e:	6923      	ldr	r3, [r4, #16]
 800a910:	6023      	str	r3, [r4, #0]
 800a912:	89a3      	ldrh	r3, [r4, #12]
 800a914:	f043 0308 	orr.w	r3, r3, #8
 800a918:	81a3      	strh	r3, [r4, #12]
 800a91a:	6923      	ldr	r3, [r4, #16]
 800a91c:	b94b      	cbnz	r3, 800a932 <__swsetup_r+0x9a>
 800a91e:	89a3      	ldrh	r3, [r4, #12]
 800a920:	f403 7320 	and.w	r3, r3, #640	; 0x280
 800a924:	f5b3 7f00 	cmp.w	r3, #512	; 0x200
 800a928:	d003      	beq.n	800a932 <__swsetup_r+0x9a>
 800a92a:	4621      	mov	r1, r4
 800a92c:	4630      	mov	r0, r6
 800a92e:	f000 f9c1 	bl	800acb4 <__smakebuf_r>
 800a932:	89a2      	ldrh	r2, [r4, #12]
 800a934:	f012 0301 	ands.w	r3, r2, #1
 800a938:	d00c      	beq.n	800a954 <__swsetup_r+0xbc>
 800a93a:	2300      	movs	r3, #0
 800a93c:	60a3      	str	r3, [r4, #8]
 800a93e:	6963      	ldr	r3, [r4, #20]
 800a940:	425b      	negs	r3, r3
 800a942:	61a3      	str	r3, [r4, #24]
 800a944:	6923      	ldr	r3, [r4, #16]
 800a946:	b953      	cbnz	r3, 800a95e <__swsetup_r+0xc6>
 800a948:	f9b4 300c 	ldrsh.w	r3, [r4, #12]
 800a94c:	f013 0080 	ands.w	r0, r3, #128	; 0x80
 800a950:	d1ba      	bne.n	800a8c8 <__swsetup_r+0x30>
 800a952:	bd70      	pop	{r4, r5, r6, pc}
 800a954:	0792      	lsls	r2, r2, #30
 800a956:	bf58      	it	pl
 800a958:	6963      	ldrpl	r3, [r4, #20]
 800a95a:	60a3      	str	r3, [r4, #8]
 800a95c:	e7f2      	b.n	800a944 <__swsetup_r+0xac>
 800a95e:	2000      	movs	r0, #0
 800a960:	e7f7      	b.n	800a952 <__swsetup_r+0xba>
 800a962:	bf00      	nop
 800a964:	2000020c 	.word	0x2000020c
 800a968:	0800b6f8 	.word	0x0800b6f8
 800a96c:	0800b718 	.word	0x0800b718
 800a970:	0800b6d8 	.word	0x0800b6d8

0800a974 <__sflush_r>:
 800a974:	898a      	ldrh	r2, [r1, #12]
 800a976:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
 800a97a:	4605      	mov	r5, r0
 800a97c:	0710      	lsls	r0, r2, #28
 800a97e:	460c      	mov	r4, r1
 800a980:	d45a      	bmi.n	800aa38 <__sflush_r+0xc4>
 800a982:	684b      	ldr	r3, [r1, #4]
 800a984:	2b00      	cmp	r3, #0
 800a986:	dc05      	bgt.n	800a994 <__sflush_r+0x20>
 800a988:	6c0b      	ldr	r3, [r1, #64]	; 0x40
 800a98a:	2b00      	cmp	r3, #0
 800a98c:	dc02      	bgt.n	800a994 <__sflush_r+0x20>
 800a98e:	2000      	movs	r0, #0
 800a990:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
 800a994:	6ae6      	ldr	r6, [r4, #44]	; 0x2c
 800a996:	2e00      	cmp	r6, #0
 800a998:	d0f9      	beq.n	800a98e <__sflush_r+0x1a>
 800a99a:	2300      	movs	r3, #0
 800a99c:	f412 5280 	ands.w	r2, r2, #4096	; 0x1000
 800a9a0:	682f      	ldr	r7, [r5, #0]
 800a9a2:	602b      	str	r3, [r5, #0]
 800a9a4:	d033      	beq.n	800aa0e <__sflush_r+0x9a>
 800a9a6:	6d60      	ldr	r0, [r4, #84]	; 0x54
 800a9a8:	89a3      	ldrh	r3, [r4, #12]
 800a9aa:	075a      	lsls	r2, r3, #29
 800a9ac:	d505      	bpl.n	800a9ba <__sflush_r+0x46>
 800a9ae:	6863      	ldr	r3, [r4, #4]
 800a9b0:	1ac0      	subs	r0, r0, r3
 800a9b2:	6b63      	ldr	r3, [r4, #52]	; 0x34
 800a9b4:	b10b      	cbz	r3, 800a9ba <__sflush_r+0x46>
 800a9b6:	6c23      	ldr	r3, [r4, #64]	; 0x40
 800a9b8:	1ac0      	subs	r0, r0, r3
 800a9ba:	2300      	movs	r3, #0
 800a9bc:	4602      	mov	r2, r0
 800a9be:	6ae6      	ldr	r6, [r4, #44]	; 0x2c
 800a9c0:	6a21      	ldr	r1, [r4, #32]
 800a9c2:	4628      	mov	r0, r5
 800a9c4:	47b0      	blx	r6
 800a9c6:	1c43      	adds	r3, r0, #1
 800a9c8:	89a3      	ldrh	r3, [r4, #12]
 800a9ca:	d106      	bne.n	800a9da <__sflush_r+0x66>
 800a9cc:	6829      	ldr	r1, [r5, #0]
 800a9ce:	291d      	cmp	r1, #29
 800a9d0:	d84b      	bhi.n	800aa6a <__sflush_r+0xf6>
 800a9d2:	4a2b      	ldr	r2, [pc, #172]	; (800aa80 <__sflush_r+0x10c>)
 800a9d4:	40ca      	lsrs	r2, r1
 800a9d6:	07d6      	lsls	r6, r2, #31
 800a9d8:	d547      	bpl.n	800aa6a <__sflush_r+0xf6>
 800a9da:	2200      	movs	r2, #0
 800a9dc:	6062      	str	r2, [r4, #4]
 800a9de:	6922      	ldr	r2, [r4, #16]
 800a9e0:	04d9      	lsls	r1, r3, #19
 800a9e2:	6022      	str	r2, [r4, #0]
 800a9e4:	d504      	bpl.n	800a9f0 <__sflush_r+0x7c>
 800a9e6:	1c42      	adds	r2, r0, #1
 800a9e8:	d101      	bne.n	800a9ee <__sflush_r+0x7a>
 800a9ea:	682b      	ldr	r3, [r5, #0]
 800a9ec:	b903      	cbnz	r3, 800a9f0 <__sflush_r+0x7c>
 800a9ee:	6560      	str	r0, [r4, #84]	; 0x54
 800a9f0:	6b61      	ldr	r1, [r4, #52]	; 0x34
 800a9f2:	602f      	str	r7, [r5, #0]
 800a9f4:	2900      	cmp	r1, #0
 800a9f6:	d0ca      	beq.n	800a98e <__sflush_r+0x1a>
 800a9f8:	f104 0344 	add.w	r3, r4, #68	; 0x44
 800a9fc:	4299      	cmp	r1, r3
 800a9fe:	d002      	beq.n	800aa06 <__sflush_r+0x92>
 800aa00:	4628      	mov	r0, r5
 800aa02:	f000 f99f 	bl	800ad44 <_free_r>
 800aa06:	2000      	movs	r0, #0
 800aa08:	6360      	str	r0, [r4, #52]	; 0x34
 800aa0a:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
 800aa0e:	6a21      	ldr	r1, [r4, #32]
 800aa10:	2301      	movs	r3, #1
 800aa12:	4628      	mov	r0, r5
 800aa14:	47b0      	blx	r6
 800aa16:	1c41      	adds	r1, r0, #1
 800aa18:	d1c6      	bne.n	800a9a8 <__sflush_r+0x34>
 800aa1a:	682b      	ldr	r3, [r5, #0]
 800aa1c:	2b00      	cmp	r3, #0
 800aa1e:	d0c3      	beq.n	800a9a8 <__sflush_r+0x34>
 800aa20:	2b1d      	cmp	r3, #29
 800aa22:	d001      	beq.n	800aa28 <__sflush_r+0xb4>
 800aa24:	2b16      	cmp	r3, #22
 800aa26:	d101      	bne.n	800aa2c <__sflush_r+0xb8>
 800aa28:	602f      	str	r7, [r5, #0]
 800aa2a:	e7b0      	b.n	800a98e <__sflush_r+0x1a>
 800aa2c:	89a3      	ldrh	r3, [r4, #12]
 800aa2e:	f043 0340 	orr.w	r3, r3, #64	; 0x40
 800aa32:	81a3      	strh	r3, [r4, #12]
 800aa34:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
 800aa38:	690f      	ldr	r7, [r1, #16]
 800aa3a:	2f00      	cmp	r7, #0
 800aa3c:	d0a7      	beq.n	800a98e <__sflush_r+0x1a>
 800aa3e:	0793      	lsls	r3, r2, #30
 800aa40:	bf18      	it	ne
 800aa42:	2300      	movne	r3, #0
 800aa44:	680e      	ldr	r6, [r1, #0]
 800aa46:	bf08      	it	eq
 800aa48:	694b      	ldreq	r3, [r1, #20]
 800aa4a:	eba6 0807 	sub.w	r8, r6, r7
 800aa4e:	600f      	str	r7, [r1, #0]
 800aa50:	608b      	str	r3, [r1, #8]
 800aa52:	f1b8 0f00 	cmp.w	r8, #0
 800aa56:	dd9a      	ble.n	800a98e <__sflush_r+0x1a>
 800aa58:	4643      	mov	r3, r8
 800aa5a:	463a      	mov	r2, r7
 800aa5c:	6a21      	ldr	r1, [r4, #32]
 800aa5e:	4628      	mov	r0, r5
 800aa60:	6aa6      	ldr	r6, [r4, #40]	; 0x28
 800aa62:	47b0      	blx	r6
 800aa64:	2800      	cmp	r0, #0
 800aa66:	dc07      	bgt.n	800aa78 <__sflush_r+0x104>
 800aa68:	89a3      	ldrh	r3, [r4, #12]
 800aa6a:	f043 0340 	orr.w	r3, r3, #64	; 0x40
 800aa6e:	81a3      	strh	r3, [r4, #12]
 800aa70:	f04f 30ff 	mov.w	r0, #4294967295
 800aa74:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
 800aa78:	4407      	add	r7, r0
 800aa7a:	eba8 0800 	sub.w	r8, r8, r0
 800aa7e:	e7e8      	b.n	800aa52 <__sflush_r+0xde>
 800aa80:	20400001 	.word	0x20400001

0800aa84 <_fflush_r>:
 800aa84:	b538      	push	{r3, r4, r5, lr}
 800aa86:	690b      	ldr	r3, [r1, #16]
 800aa88:	4605      	mov	r5, r0
 800aa8a:	460c      	mov	r4, r1
 800aa8c:	b1db      	cbz	r3, 800aac6 <_fflush_r+0x42>
 800aa8e:	b118      	cbz	r0, 800aa98 <_fflush_r+0x14>
 800aa90:	6983      	ldr	r3, [r0, #24]
 800aa92:	b90b      	cbnz	r3, 800aa98 <_fflush_r+0x14>
 800aa94:	f000 f860 	bl	800ab58 <__sinit>
 800aa98:	4b0c      	ldr	r3, [pc, #48]	; (800aacc <_fflush_r+0x48>)
 800aa9a:	429c      	cmp	r4, r3
 800aa9c:	d109      	bne.n	800aab2 <_fflush_r+0x2e>
 800aa9e:	686c      	ldr	r4, [r5, #4]
 800aaa0:	f9b4 300c 	ldrsh.w	r3, [r4, #12]
 800aaa4:	b17b      	cbz	r3, 800aac6 <_fflush_r+0x42>
 800aaa6:	4621      	mov	r1, r4
 800aaa8:	4628      	mov	r0, r5
 800aaaa:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
 800aaae:	f7ff bf61 	b.w	800a974 <__sflush_r>
 800aab2:	4b07      	ldr	r3, [pc, #28]	; (800aad0 <_fflush_r+0x4c>)
 800aab4:	429c      	cmp	r4, r3
 800aab6:	d101      	bne.n	800aabc <_fflush_r+0x38>
 800aab8:	68ac      	ldr	r4, [r5, #8]
 800aaba:	e7f1      	b.n	800aaa0 <_fflush_r+0x1c>
 800aabc:	4b05      	ldr	r3, [pc, #20]	; (800aad4 <_fflush_r+0x50>)
 800aabe:	429c      	cmp	r4, r3
 800aac0:	bf08      	it	eq
 800aac2:	68ec      	ldreq	r4, [r5, #12]
 800aac4:	e7ec      	b.n	800aaa0 <_fflush_r+0x1c>
 800aac6:	2000      	movs	r0, #0
 800aac8:	bd38      	pop	{r3, r4, r5, pc}
 800aaca:	bf00      	nop
 800aacc:	0800b6f8 	.word	0x0800b6f8
 800aad0:	0800b718 	.word	0x0800b718
 800aad4:	0800b6d8 	.word	0x0800b6d8

0800aad8 <_cleanup_r>:
 800aad8:	4901      	ldr	r1, [pc, #4]	; (800aae0 <_cleanup_r+0x8>)
 800aada:	f000 b8a9 	b.w	800ac30 <_fwalk_reent>
 800aade:	bf00      	nop
 800aae0:	0800aa85 	.word	0x0800aa85

0800aae4 <std.isra.0>:
 800aae4:	2300      	movs	r3, #0
 800aae6:	b510      	push	{r4, lr}
 800aae8:	4604      	mov	r4, r0
 800aaea:	6003      	str	r3, [r0, #0]
 800aaec:	6043      	str	r3, [r0, #4]
 800aaee:	6083      	str	r3, [r0, #8]
 800aaf0:	8181      	strh	r1, [r0, #12]
 800aaf2:	6643      	str	r3, [r0, #100]	; 0x64
 800aaf4:	81c2      	strh	r2, [r0, #14]
 800aaf6:	6103      	str	r3, [r0, #16]
 800aaf8:	6143      	str	r3, [r0, #20]
 800aafa:	6183      	str	r3, [r0, #24]
 800aafc:	4619      	mov	r1, r3
 800aafe:	2208      	movs	r2, #8
 800ab00:	305c      	adds	r0, #92	; 0x5c
 800ab02:	f7ff fd3d 	bl	800a580 <memset>
 800ab06:	4b05      	ldr	r3, [pc, #20]	; (800ab1c <std.isra.0+0x38>)
 800ab08:	6224      	str	r4, [r4, #32]
 800ab0a:	6263      	str	r3, [r4, #36]	; 0x24
 800ab0c:	4b04      	ldr	r3, [pc, #16]	; (800ab20 <std.isra.0+0x3c>)
 800ab0e:	62a3      	str	r3, [r4, #40]	; 0x28
 800ab10:	4b04      	ldr	r3, [pc, #16]	; (800ab24 <std.isra.0+0x40>)
 800ab12:	62e3      	str	r3, [r4, #44]	; 0x2c
 800ab14:	4b04      	ldr	r3, [pc, #16]	; (800ab28 <std.isra.0+0x44>)
 800ab16:	6323      	str	r3, [r4, #48]	; 0x30
 800ab18:	bd10      	pop	{r4, pc}
 800ab1a:	bf00      	nop
 800ab1c:	0800b465 	.word	0x0800b465
 800ab20:	0800b487 	.word	0x0800b487
 800ab24:	0800b4bf 	.word	0x0800b4bf
 800ab28:	0800b4e3 	.word	0x0800b4e3

0800ab2c <__sfmoreglue>:
 800ab2c:	b570      	push	{r4, r5, r6, lr}
 800ab2e:	2568      	movs	r5, #104	; 0x68
 800ab30:	1e4a      	subs	r2, r1, #1
 800ab32:	4355      	muls	r5, r2
 800ab34:	460e      	mov	r6, r1
 800ab36:	f105 0174 	add.w	r1, r5, #116	; 0x74
 800ab3a:	f000 f94f 	bl	800addc <_malloc_r>
 800ab3e:	4604      	mov	r4, r0
 800ab40:	b140      	cbz	r0, 800ab54 <__sfmoreglue+0x28>
 800ab42:	2100      	movs	r1, #0
 800ab44:	e880 0042 	stmia.w	r0, {r1, r6}
 800ab48:	300c      	adds	r0, #12
 800ab4a:	60a0      	str	r0, [r4, #8]
 800ab4c:	f105 0268 	add.w	r2, r5, #104	; 0x68
 800ab50:	f7ff fd16 	bl	800a580 <memset>
 800ab54:	4620      	mov	r0, r4
 800ab56:	bd70      	pop	{r4, r5, r6, pc}

0800ab58 <__sinit>:
 800ab58:	6983      	ldr	r3, [r0, #24]
 800ab5a:	b510      	push	{r4, lr}
 800ab5c:	4604      	mov	r4, r0
 800ab5e:	bb33      	cbnz	r3, 800abae <__sinit+0x56>
 800ab60:	6483      	str	r3, [r0, #72]	; 0x48
 800ab62:	64c3      	str	r3, [r0, #76]	; 0x4c
 800ab64:	6503      	str	r3, [r0, #80]	; 0x50
 800ab66:	4b12      	ldr	r3, [pc, #72]	; (800abb0 <__sinit+0x58>)
 800ab68:	4a12      	ldr	r2, [pc, #72]	; (800abb4 <__sinit+0x5c>)
 800ab6a:	681b      	ldr	r3, [r3, #0]
 800ab6c:	6282      	str	r2, [r0, #40]	; 0x28
 800ab6e:	4298      	cmp	r0, r3
 800ab70:	bf04      	itt	eq
 800ab72:	2301      	moveq	r3, #1
 800ab74:	6183      	streq	r3, [r0, #24]
 800ab76:	f000 f81f 	bl	800abb8 <__sfp>
 800ab7a:	6060      	str	r0, [r4, #4]
 800ab7c:	4620      	mov	r0, r4
 800ab7e:	f000 f81b 	bl	800abb8 <__sfp>
 800ab82:	60a0      	str	r0, [r4, #8]
 800ab84:	4620      	mov	r0, r4
 800ab86:	f000 f817 	bl	800abb8 <__sfp>
 800ab8a:	2200      	movs	r2, #0
 800ab8c:	60e0      	str	r0, [r4, #12]
 800ab8e:	2104      	movs	r1, #4
 800ab90:	6860      	ldr	r0, [r4, #4]
 800ab92:	f7ff ffa7 	bl	800aae4 <std.isra.0>
 800ab96:	2201      	movs	r2, #1
 800ab98:	2109      	movs	r1, #9
 800ab9a:	68a0      	ldr	r0, [r4, #8]
 800ab9c:	f7ff ffa2 	bl	800aae4 <std.isra.0>
 800aba0:	2202      	movs	r2, #2
 800aba2:	2112      	movs	r1, #18
 800aba4:	68e0      	ldr	r0, [r4, #12]
 800aba6:	f7ff ff9d 	bl	800aae4 <std.isra.0>
 800abaa:	2301      	movs	r3, #1
 800abac:	61a3      	str	r3, [r4, #24]
 800abae:	bd10      	pop	{r4, pc}
 800abb0:	0800b6d4 	.word	0x0800b6d4
 800abb4:	0800aad9 	.word	0x0800aad9

0800abb8 <__sfp>:
 800abb8:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 800abba:	4b1c      	ldr	r3, [pc, #112]	; (800ac2c <__sfp+0x74>)
 800abbc:	4607      	mov	r7, r0
 800abbe:	681e      	ldr	r6, [r3, #0]
 800abc0:	69b3      	ldr	r3, [r6, #24]
 800abc2:	b913      	cbnz	r3, 800abca <__sfp+0x12>
 800abc4:	4630      	mov	r0, r6
 800abc6:	f7ff ffc7 	bl	800ab58 <__sinit>
 800abca:	3648      	adds	r6, #72	; 0x48
 800abcc:	68b4      	ldr	r4, [r6, #8]
 800abce:	6873      	ldr	r3, [r6, #4]
 800abd0:	3b01      	subs	r3, #1
 800abd2:	d503      	bpl.n	800abdc <__sfp+0x24>
 800abd4:	6833      	ldr	r3, [r6, #0]
 800abd6:	b133      	cbz	r3, 800abe6 <__sfp+0x2e>
 800abd8:	6836      	ldr	r6, [r6, #0]
 800abda:	e7f7      	b.n	800abcc <__sfp+0x14>
 800abdc:	f9b4 500c 	ldrsh.w	r5, [r4, #12]
 800abe0:	b16d      	cbz	r5, 800abfe <__sfp+0x46>
 800abe2:	3468      	adds	r4, #104	; 0x68
 800abe4:	e7f4      	b.n	800abd0 <__sfp+0x18>
 800abe6:	2104      	movs	r1, #4
 800abe8:	4638      	mov	r0, r7
 800abea:	f7ff ff9f 	bl	800ab2c <__sfmoreglue>
 800abee:	6030      	str	r0, [r6, #0]
 800abf0:	2800      	cmp	r0, #0
 800abf2:	d1f1      	bne.n	800abd8 <__sfp+0x20>
 800abf4:	230c      	movs	r3, #12
 800abf6:	4604      	mov	r4, r0
 800abf8:	603b      	str	r3, [r7, #0]
 800abfa:	4620      	mov	r0, r4
 800abfc:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
 800abfe:	f64f 73ff 	movw	r3, #65535	; 0xffff
 800ac02:	81e3      	strh	r3, [r4, #14]
 800ac04:	2301      	movs	r3, #1
 800ac06:	6665      	str	r5, [r4, #100]	; 0x64
 800ac08:	81a3      	strh	r3, [r4, #12]
 800ac0a:	6025      	str	r5, [r4, #0]
 800ac0c:	60a5      	str	r5, [r4, #8]
 800ac0e:	6065      	str	r5, [r4, #4]
 800ac10:	6125      	str	r5, [r4, #16]
 800ac12:	6165      	str	r5, [r4, #20]
 800ac14:	61a5      	str	r5, [r4, #24]
 800ac16:	2208      	movs	r2, #8
 800ac18:	4629      	mov	r1, r5
 800ac1a:	f104 005c 	add.w	r0, r4, #92	; 0x5c
 800ac1e:	f7ff fcaf 	bl	800a580 <memset>
 800ac22:	6365      	str	r5, [r4, #52]	; 0x34
 800ac24:	63a5      	str	r5, [r4, #56]	; 0x38
 800ac26:	64a5      	str	r5, [r4, #72]	; 0x48
 800ac28:	64e5      	str	r5, [r4, #76]	; 0x4c
 800ac2a:	e7e6      	b.n	800abfa <__sfp+0x42>
 800ac2c:	0800b6d4 	.word	0x0800b6d4

0800ac30 <_fwalk_reent>:
 800ac30:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
 800ac34:	4680      	mov	r8, r0
 800ac36:	4689      	mov	r9, r1
 800ac38:	2600      	movs	r6, #0
 800ac3a:	f100 0448 	add.w	r4, r0, #72	; 0x48
 800ac3e:	b914      	cbnz	r4, 800ac46 <_fwalk_reent+0x16>
 800ac40:	4630      	mov	r0, r6
 800ac42:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
 800ac46:	68a5      	ldr	r5, [r4, #8]
 800ac48:	6867      	ldr	r7, [r4, #4]
 800ac4a:	3f01      	subs	r7, #1
 800ac4c:	d501      	bpl.n	800ac52 <_fwalk_reent+0x22>
 800ac4e:	6824      	ldr	r4, [r4, #0]
 800ac50:	e7f5      	b.n	800ac3e <_fwalk_reent+0xe>
 800ac52:	89ab      	ldrh	r3, [r5, #12]
 800ac54:	2b01      	cmp	r3, #1
 800ac56:	d907      	bls.n	800ac68 <_fwalk_reent+0x38>
 800ac58:	f9b5 300e 	ldrsh.w	r3, [r5, #14]
 800ac5c:	3301      	adds	r3, #1
 800ac5e:	d003      	beq.n	800ac68 <_fwalk_reent+0x38>
 800ac60:	4629      	mov	r1, r5
 800ac62:	4640      	mov	r0, r8
 800ac64:	47c8      	blx	r9
 800ac66:	4306      	orrs	r6, r0
 800ac68:	3568      	adds	r5, #104	; 0x68
 800ac6a:	e7ee      	b.n	800ac4a <_fwalk_reent+0x1a>

0800ac6c <__swhatbuf_r>:
 800ac6c:	b570      	push	{r4, r5, r6, lr}
 800ac6e:	460e      	mov	r6, r1
 800ac70:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 800ac74:	b090      	sub	sp, #64	; 0x40
 800ac76:	2900      	cmp	r1, #0
 800ac78:	4614      	mov	r4, r2
 800ac7a:	461d      	mov	r5, r3
 800ac7c:	da07      	bge.n	800ac8e <__swhatbuf_r+0x22>
 800ac7e:	2300      	movs	r3, #0
 800ac80:	602b      	str	r3, [r5, #0]
 800ac82:	89b3      	ldrh	r3, [r6, #12]
 800ac84:	061a      	lsls	r2, r3, #24
 800ac86:	d410      	bmi.n	800acaa <__swhatbuf_r+0x3e>
 800ac88:	f44f 6380 	mov.w	r3, #1024	; 0x400
 800ac8c:	e00e      	b.n	800acac <__swhatbuf_r+0x40>
 800ac8e:	aa01      	add	r2, sp, #4
 800ac90:	f000 fc4e 	bl	800b530 <_fstat_r>
 800ac94:	2800      	cmp	r0, #0
 800ac96:	dbf2      	blt.n	800ac7e <__swhatbuf_r+0x12>
 800ac98:	9a02      	ldr	r2, [sp, #8]
 800ac9a:	f402 4270 	and.w	r2, r2, #61440	; 0xf000
 800ac9e:	f5a2 5300 	sub.w	r3, r2, #8192	; 0x2000
 800aca2:	425a      	negs	r2, r3
 800aca4:	415a      	adcs	r2, r3
 800aca6:	602a      	str	r2, [r5, #0]
 800aca8:	e7ee      	b.n	800ac88 <__swhatbuf_r+0x1c>
 800acaa:	2340      	movs	r3, #64	; 0x40
 800acac:	2000      	movs	r0, #0
 800acae:	6023      	str	r3, [r4, #0]
 800acb0:	b010      	add	sp, #64	; 0x40
 800acb2:	bd70      	pop	{r4, r5, r6, pc}

0800acb4 <__smakebuf_r>:
 800acb4:	898b      	ldrh	r3, [r1, #12]
 800acb6:	b573      	push	{r0, r1, r4, r5, r6, lr}
 800acb8:	079d      	lsls	r5, r3, #30
 800acba:	4606      	mov	r6, r0
 800acbc:	460c      	mov	r4, r1
 800acbe:	d507      	bpl.n	800acd0 <__smakebuf_r+0x1c>
 800acc0:	f104 0347 	add.w	r3, r4, #71	; 0x47
 800acc4:	6023      	str	r3, [r4, #0]
 800acc6:	6123      	str	r3, [r4, #16]
 800acc8:	2301      	movs	r3, #1
 800acca:	6163      	str	r3, [r4, #20]
 800accc:	b002      	add	sp, #8
 800acce:	bd70      	pop	{r4, r5, r6, pc}
 800acd0:	ab01      	add	r3, sp, #4
 800acd2:	466a      	mov	r2, sp
 800acd4:	f7ff ffca 	bl	800ac6c <__swhatbuf_r>
 800acd8:	9900      	ldr	r1, [sp, #0]
 800acda:	4605      	mov	r5, r0
 800acdc:	4630      	mov	r0, r6
 800acde:	f000 f87d 	bl	800addc <_malloc_r>
 800ace2:	b948      	cbnz	r0, 800acf8 <__smakebuf_r+0x44>
 800ace4:	f9b4 300c 	ldrsh.w	r3, [r4, #12]
 800ace8:	059a      	lsls	r2, r3, #22
 800acea:	d4ef      	bmi.n	800accc <__smakebuf_r+0x18>
 800acec:	f023 0303 	bic.w	r3, r3, #3
 800acf0:	f043 0302 	orr.w	r3, r3, #2
 800acf4:	81a3      	strh	r3, [r4, #12]
 800acf6:	e7e3      	b.n	800acc0 <__smakebuf_r+0xc>
 800acf8:	4b0d      	ldr	r3, [pc, #52]	; (800ad30 <__smakebuf_r+0x7c>)
 800acfa:	62b3      	str	r3, [r6, #40]	; 0x28
 800acfc:	89a3      	ldrh	r3, [r4, #12]
 800acfe:	6020      	str	r0, [r4, #0]
 800ad00:	f043 0380 	orr.w	r3, r3, #128	; 0x80
 800ad04:	81a3      	strh	r3, [r4, #12]
 800ad06:	9b00      	ldr	r3, [sp, #0]
 800ad08:	6120      	str	r0, [r4, #16]
 800ad0a:	6163      	str	r3, [r4, #20]
 800ad0c:	9b01      	ldr	r3, [sp, #4]
 800ad0e:	b15b      	cbz	r3, 800ad28 <__smakebuf_r+0x74>
 800ad10:	f9b4 100e 	ldrsh.w	r1, [r4, #14]
 800ad14:	4630      	mov	r0, r6
 800ad16:	f000 fc1d 	bl	800b554 <_isatty_r>
 800ad1a:	b128      	cbz	r0, 800ad28 <__smakebuf_r+0x74>
 800ad1c:	89a3      	ldrh	r3, [r4, #12]
 800ad1e:	f023 0303 	bic.w	r3, r3, #3
 800ad22:	f043 0301 	orr.w	r3, r3, #1
 800ad26:	81a3      	strh	r3, [r4, #12]
 800ad28:	89a3      	ldrh	r3, [r4, #12]
 800ad2a:	431d      	orrs	r5, r3
 800ad2c:	81a5      	strh	r5, [r4, #12]
 800ad2e:	e7cd      	b.n	800accc <__smakebuf_r+0x18>
 800ad30:	0800aad9 	.word	0x0800aad9

0800ad34 <malloc>:
 800ad34:	4b02      	ldr	r3, [pc, #8]	; (800ad40 <malloc+0xc>)
 800ad36:	4601      	mov	r1, r0
 800ad38:	6818      	ldr	r0, [r3, #0]
 800ad3a:	f000 b84f 	b.w	800addc <_malloc_r>
 800ad3e:	bf00      	nop
 800ad40:	2000020c 	.word	0x2000020c

0800ad44 <_free_r>:
 800ad44:	b538      	push	{r3, r4, r5, lr}
 800ad46:	4605      	mov	r5, r0
 800ad48:	2900      	cmp	r1, #0
 800ad4a:	d043      	beq.n	800add4 <_free_r+0x90>
 800ad4c:	f851 3c04 	ldr.w	r3, [r1, #-4]
 800ad50:	1f0c      	subs	r4, r1, #4
 800ad52:	2b00      	cmp	r3, #0
 800ad54:	bfb8      	it	lt
 800ad56:	18e4      	addlt	r4, r4, r3
 800ad58:	f000 fc2c 	bl	800b5b4 <__malloc_lock>
 800ad5c:	4a1e      	ldr	r2, [pc, #120]	; (800add8 <_free_r+0x94>)
 800ad5e:	6813      	ldr	r3, [r2, #0]
 800ad60:	4610      	mov	r0, r2
 800ad62:	b933      	cbnz	r3, 800ad72 <_free_r+0x2e>
 800ad64:	6063      	str	r3, [r4, #4]
 800ad66:	6014      	str	r4, [r2, #0]
 800ad68:	4628      	mov	r0, r5
 800ad6a:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
 800ad6e:	f000 bc22 	b.w	800b5b6 <__malloc_unlock>
 800ad72:	42a3      	cmp	r3, r4
 800ad74:	d90b      	bls.n	800ad8e <_free_r+0x4a>
 800ad76:	6821      	ldr	r1, [r4, #0]
 800ad78:	1862      	adds	r2, r4, r1
 800ad7a:	4293      	cmp	r3, r2
 800ad7c:	bf01      	itttt	eq
 800ad7e:	681a      	ldreq	r2, [r3, #0]
 800ad80:	685b      	ldreq	r3, [r3, #4]
 800ad82:	1852      	addeq	r2, r2, r1
 800ad84:	6022      	streq	r2, [r4, #0]
 800ad86:	6063      	str	r3, [r4, #4]
 800ad88:	6004      	str	r4, [r0, #0]
 800ad8a:	e7ed      	b.n	800ad68 <_free_r+0x24>
 800ad8c:	4613      	mov	r3, r2
 800ad8e:	685a      	ldr	r2, [r3, #4]
 800ad90:	b10a      	cbz	r2, 800ad96 <_free_r+0x52>
 800ad92:	42a2      	cmp	r2, r4
 800ad94:	d9fa      	bls.n	800ad8c <_free_r+0x48>
 800ad96:	6819      	ldr	r1, [r3, #0]
 800ad98:	1858      	adds	r0, r3, r1
 800ad9a:	42a0      	cmp	r0, r4
 800ad9c:	d10b      	bne.n	800adb6 <_free_r+0x72>
 800ad9e:	6820      	ldr	r0, [r4, #0]
 800ada0:	4401      	add	r1, r0
 800ada2:	1858      	adds	r0, r3, r1
 800ada4:	4282      	cmp	r2, r0
 800ada6:	6019      	str	r1, [r3, #0]
 800ada8:	d1de      	bne.n	800ad68 <_free_r+0x24>
 800adaa:	6810      	ldr	r0, [r2, #0]
 800adac:	6852      	ldr	r2, [r2, #4]
 800adae:	4401      	add	r1, r0
 800adb0:	6019      	str	r1, [r3, #0]
 800adb2:	605a      	str	r2, [r3, #4]
 800adb4:	e7d8      	b.n	800ad68 <_free_r+0x24>
 800adb6:	d902      	bls.n	800adbe <_free_r+0x7a>
 800adb8:	230c      	movs	r3, #12
 800adba:	602b      	str	r3, [r5, #0]
 800adbc:	e7d4      	b.n	800ad68 <_free_r+0x24>
 800adbe:	6820      	ldr	r0, [r4, #0]
 800adc0:	1821      	adds	r1, r4, r0
 800adc2:	428a      	cmp	r2, r1
 800adc4:	bf01      	itttt	eq
 800adc6:	6811      	ldreq	r1, [r2, #0]
 800adc8:	6852      	ldreq	r2, [r2, #4]
 800adca:	1809      	addeq	r1, r1, r0
 800adcc:	6021      	streq	r1, [r4, #0]
 800adce:	6062      	str	r2, [r4, #4]
 800add0:	605c      	str	r4, [r3, #4]
 800add2:	e7c9      	b.n	800ad68 <_free_r+0x24>
 800add4:	bd38      	pop	{r3, r4, r5, pc}
 800add6:	bf00      	nop
 800add8:	2000029c 	.word	0x2000029c

0800addc <_malloc_r>:
 800addc:	b570      	push	{r4, r5, r6, lr}
 800adde:	1ccd      	adds	r5, r1, #3
 800ade0:	f025 0503 	bic.w	r5, r5, #3
 800ade4:	3508      	adds	r5, #8
 800ade6:	2d0c      	cmp	r5, #12
 800ade8:	bf38      	it	cc
 800adea:	250c      	movcc	r5, #12
 800adec:	2d00      	cmp	r5, #0
 800adee:	4606      	mov	r6, r0
 800adf0:	db01      	blt.n	800adf6 <_malloc_r+0x1a>
 800adf2:	42a9      	cmp	r1, r5
 800adf4:	d903      	bls.n	800adfe <_malloc_r+0x22>
 800adf6:	230c      	movs	r3, #12
 800adf8:	6033      	str	r3, [r6, #0]
 800adfa:	2000      	movs	r0, #0
 800adfc:	bd70      	pop	{r4, r5, r6, pc}
 800adfe:	f000 fbd9 	bl	800b5b4 <__malloc_lock>
 800ae02:	4a23      	ldr	r2, [pc, #140]	; (800ae90 <_malloc_r+0xb4>)
 800ae04:	6814      	ldr	r4, [r2, #0]
 800ae06:	4621      	mov	r1, r4
 800ae08:	b991      	cbnz	r1, 800ae30 <_malloc_r+0x54>
 800ae0a:	4c22      	ldr	r4, [pc, #136]	; (800ae94 <_malloc_r+0xb8>)
 800ae0c:	6823      	ldr	r3, [r4, #0]
 800ae0e:	b91b      	cbnz	r3, 800ae18 <_malloc_r+0x3c>
 800ae10:	4630      	mov	r0, r6
 800ae12:	f000 fb17 	bl	800b444 <_sbrk_r>
 800ae16:	6020      	str	r0, [r4, #0]
 800ae18:	4629      	mov	r1, r5
 800ae1a:	4630      	mov	r0, r6
 800ae1c:	f000 fb12 	bl	800b444 <_sbrk_r>
 800ae20:	1c43      	adds	r3, r0, #1
 800ae22:	d126      	bne.n	800ae72 <_malloc_r+0x96>
 800ae24:	230c      	movs	r3, #12
 800ae26:	4630      	mov	r0, r6
 800ae28:	6033      	str	r3, [r6, #0]
 800ae2a:	f000 fbc4 	bl	800b5b6 <__malloc_unlock>
 800ae2e:	e7e4      	b.n	800adfa <_malloc_r+0x1e>
 800ae30:	680b      	ldr	r3, [r1, #0]
 800ae32:	1b5b      	subs	r3, r3, r5
 800ae34:	d41a      	bmi.n	800ae6c <_malloc_r+0x90>
 800ae36:	2b0b      	cmp	r3, #11
 800ae38:	d90f      	bls.n	800ae5a <_malloc_r+0x7e>
 800ae3a:	600b      	str	r3, [r1, #0]
 800ae3c:	18cc      	adds	r4, r1, r3
 800ae3e:	50cd      	str	r5, [r1, r3]
 800ae40:	4630      	mov	r0, r6
 800ae42:	f000 fbb8 	bl	800b5b6 <__malloc_unlock>
 800ae46:	f104 000b 	add.w	r0, r4, #11
 800ae4a:	1d23      	adds	r3, r4, #4
 800ae4c:	f020 0007 	bic.w	r0, r0, #7
 800ae50:	1ac3      	subs	r3, r0, r3
 800ae52:	d01b      	beq.n	800ae8c <_malloc_r+0xb0>
 800ae54:	425a      	negs	r2, r3
 800ae56:	50e2      	str	r2, [r4, r3]
 800ae58:	bd70      	pop	{r4, r5, r6, pc}
 800ae5a:	428c      	cmp	r4, r1
 800ae5c:	bf0b      	itete	eq
 800ae5e:	6863      	ldreq	r3, [r4, #4]
 800ae60:	684b      	ldrne	r3, [r1, #4]
 800ae62:	6013      	streq	r3, [r2, #0]
 800ae64:	6063      	strne	r3, [r4, #4]
 800ae66:	bf18      	it	ne
 800ae68:	460c      	movne	r4, r1
 800ae6a:	e7e9      	b.n	800ae40 <_malloc_r+0x64>
 800ae6c:	460c      	mov	r4, r1
 800ae6e:	6849      	ldr	r1, [r1, #4]
 800ae70:	e7ca      	b.n	800ae08 <_malloc_r+0x2c>
 800ae72:	1cc4      	adds	r4, r0, #3
 800ae74:	f024 0403 	bic.w	r4, r4, #3
 800ae78:	42a0      	cmp	r0, r4
 800ae7a:	d005      	beq.n	800ae88 <_malloc_r+0xac>
 800ae7c:	1a21      	subs	r1, r4, r0
 800ae7e:	4630      	mov	r0, r6
 800ae80:	f000 fae0 	bl	800b444 <_sbrk_r>
 800ae84:	3001      	adds	r0, #1
 800ae86:	d0cd      	beq.n	800ae24 <_malloc_r+0x48>
 800ae88:	6025      	str	r5, [r4, #0]
 800ae8a:	e7d9      	b.n	800ae40 <_malloc_r+0x64>
 800ae8c:	bd70      	pop	{r4, r5, r6, pc}
 800ae8e:	bf00      	nop
 800ae90:	2000029c 	.word	0x2000029c
 800ae94:	200002a0 	.word	0x200002a0

0800ae98 <__sfputc_r>:
 800ae98:	6893      	ldr	r3, [r2, #8]
 800ae9a:	b410      	push	{r4}
 800ae9c:	3b01      	subs	r3, #1
 800ae9e:	2b00      	cmp	r3, #0
 800aea0:	6093      	str	r3, [r2, #8]
 800aea2:	da08      	bge.n	800aeb6 <__sfputc_r+0x1e>
 800aea4:	6994      	ldr	r4, [r2, #24]
 800aea6:	42a3      	cmp	r3, r4
 800aea8:	db02      	blt.n	800aeb0 <__sfputc_r+0x18>
 800aeaa:	b2cb      	uxtb	r3, r1
 800aeac:	2b0a      	cmp	r3, #10
 800aeae:	d102      	bne.n	800aeb6 <__sfputc_r+0x1e>
 800aeb0:	bc10      	pop	{r4}
 800aeb2:	f7ff bc9f 	b.w	800a7f4 <__swbuf_r>
 800aeb6:	6813      	ldr	r3, [r2, #0]
 800aeb8:	1c58      	adds	r0, r3, #1
 800aeba:	6010      	str	r0, [r2, #0]
 800aebc:	7019      	strb	r1, [r3, #0]
 800aebe:	b2c8      	uxtb	r0, r1
 800aec0:	bc10      	pop	{r4}
 800aec2:	4770      	bx	lr

0800aec4 <__sfputs_r>:
 800aec4:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 800aec6:	4606      	mov	r6, r0
 800aec8:	460f      	mov	r7, r1
 800aeca:	4614      	mov	r4, r2
 800aecc:	18d5      	adds	r5, r2, r3
 800aece:	42ac      	cmp	r4, r5
 800aed0:	d101      	bne.n	800aed6 <__sfputs_r+0x12>
 800aed2:	2000      	movs	r0, #0
 800aed4:	e007      	b.n	800aee6 <__sfputs_r+0x22>
 800aed6:	463a      	mov	r2, r7
 800aed8:	f814 1b01 	ldrb.w	r1, [r4], #1
 800aedc:	4630      	mov	r0, r6
 800aede:	f7ff ffdb 	bl	800ae98 <__sfputc_r>
 800aee2:	1c43      	adds	r3, r0, #1
 800aee4:	d1f3      	bne.n	800aece <__sfputs_r+0xa>
 800aee6:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}

0800aee8 <_vfiprintf_r>:
 800aee8:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
 800aeec:	b09d      	sub	sp, #116	; 0x74
 800aeee:	460c      	mov	r4, r1
 800aef0:	4617      	mov	r7, r2
 800aef2:	9303      	str	r3, [sp, #12]
 800aef4:	4606      	mov	r6, r0
 800aef6:	b118      	cbz	r0, 800af00 <_vfiprintf_r+0x18>
 800aef8:	6983      	ldr	r3, [r0, #24]
 800aefa:	b90b      	cbnz	r3, 800af00 <_vfiprintf_r+0x18>
 800aefc:	f7ff fe2c 	bl	800ab58 <__sinit>
 800af00:	4b7c      	ldr	r3, [pc, #496]	; (800b0f4 <_vfiprintf_r+0x20c>)
 800af02:	429c      	cmp	r4, r3
 800af04:	d157      	bne.n	800afb6 <_vfiprintf_r+0xce>
 800af06:	6874      	ldr	r4, [r6, #4]
 800af08:	89a3      	ldrh	r3, [r4, #12]
 800af0a:	0718      	lsls	r0, r3, #28
 800af0c:	d55d      	bpl.n	800afca <_vfiprintf_r+0xe2>
 800af0e:	6923      	ldr	r3, [r4, #16]
 800af10:	2b00      	cmp	r3, #0
 800af12:	d05a      	beq.n	800afca <_vfiprintf_r+0xe2>
 800af14:	2300      	movs	r3, #0
 800af16:	9309      	str	r3, [sp, #36]	; 0x24
 800af18:	2320      	movs	r3, #32
 800af1a:	f88d 3029 	strb.w	r3, [sp, #41]	; 0x29
 800af1e:	2330      	movs	r3, #48	; 0x30
 800af20:	f04f 0b01 	mov.w	fp, #1
 800af24:	f88d 302a 	strb.w	r3, [sp, #42]	; 0x2a
 800af28:	46b8      	mov	r8, r7
 800af2a:	4645      	mov	r5, r8
 800af2c:	f815 3b01 	ldrb.w	r3, [r5], #1
 800af30:	2b00      	cmp	r3, #0
 800af32:	d155      	bne.n	800afe0 <_vfiprintf_r+0xf8>
 800af34:	ebb8 0a07 	subs.w	sl, r8, r7
 800af38:	d00b      	beq.n	800af52 <_vfiprintf_r+0x6a>
 800af3a:	4653      	mov	r3, sl
 800af3c:	463a      	mov	r2, r7
 800af3e:	4621      	mov	r1, r4
 800af40:	4630      	mov	r0, r6
 800af42:	f7ff ffbf 	bl	800aec4 <__sfputs_r>
 800af46:	3001      	adds	r0, #1
 800af48:	f000 80c4 	beq.w	800b0d4 <_vfiprintf_r+0x1ec>
 800af4c:	9b09      	ldr	r3, [sp, #36]	; 0x24
 800af4e:	4453      	add	r3, sl
 800af50:	9309      	str	r3, [sp, #36]	; 0x24
 800af52:	f898 3000 	ldrb.w	r3, [r8]
 800af56:	2b00      	cmp	r3, #0
 800af58:	f000 80bc 	beq.w	800b0d4 <_vfiprintf_r+0x1ec>
 800af5c:	2300      	movs	r3, #0
 800af5e:	f04f 32ff 	mov.w	r2, #4294967295
 800af62:	9304      	str	r3, [sp, #16]
 800af64:	9307      	str	r3, [sp, #28]
 800af66:	9205      	str	r2, [sp, #20]
 800af68:	9306      	str	r3, [sp, #24]
 800af6a:	f88d 3053 	strb.w	r3, [sp, #83]	; 0x53
 800af6e:	931a      	str	r3, [sp, #104]	; 0x68
 800af70:	2205      	movs	r2, #5
 800af72:	7829      	ldrb	r1, [r5, #0]
 800af74:	4860      	ldr	r0, [pc, #384]	; (800b0f8 <_vfiprintf_r+0x210>)
 800af76:	f000 fb0f 	bl	800b598 <memchr>
 800af7a:	f105 0801 	add.w	r8, r5, #1
 800af7e:	9b04      	ldr	r3, [sp, #16]
 800af80:	2800      	cmp	r0, #0
 800af82:	d131      	bne.n	800afe8 <_vfiprintf_r+0x100>
 800af84:	06d9      	lsls	r1, r3, #27
 800af86:	bf44      	itt	mi
 800af88:	2220      	movmi	r2, #32
 800af8a:	f88d 2053 	strbmi.w	r2, [sp, #83]	; 0x53
 800af8e:	071a      	lsls	r2, r3, #28
 800af90:	bf44      	itt	mi
 800af92:	222b      	movmi	r2, #43	; 0x2b
 800af94:	f88d 2053 	strbmi.w	r2, [sp, #83]	; 0x53
 800af98:	782a      	ldrb	r2, [r5, #0]
 800af9a:	2a2a      	cmp	r2, #42	; 0x2a
 800af9c:	d02c      	beq.n	800aff8 <_vfiprintf_r+0x110>
 800af9e:	2100      	movs	r1, #0
 800afa0:	200a      	movs	r0, #10
 800afa2:	9a07      	ldr	r2, [sp, #28]
 800afa4:	46a8      	mov	r8, r5
 800afa6:	f898 3000 	ldrb.w	r3, [r8]
 800afaa:	3501      	adds	r5, #1
 800afac:	3b30      	subs	r3, #48	; 0x30
 800afae:	2b09      	cmp	r3, #9
 800afb0:	d96d      	bls.n	800b08e <_vfiprintf_r+0x1a6>
 800afb2:	b371      	cbz	r1, 800b012 <_vfiprintf_r+0x12a>
 800afb4:	e026      	b.n	800b004 <_vfiprintf_r+0x11c>
 800afb6:	4b51      	ldr	r3, [pc, #324]	; (800b0fc <_vfiprintf_r+0x214>)
 800afb8:	429c      	cmp	r4, r3
 800afba:	d101      	bne.n	800afc0 <_vfiprintf_r+0xd8>
 800afbc:	68b4      	ldr	r4, [r6, #8]
 800afbe:	e7a3      	b.n	800af08 <_vfiprintf_r+0x20>
 800afc0:	4b4f      	ldr	r3, [pc, #316]	; (800b100 <_vfiprintf_r+0x218>)
 800afc2:	429c      	cmp	r4, r3
 800afc4:	bf08      	it	eq
 800afc6:	68f4      	ldreq	r4, [r6, #12]
 800afc8:	e79e      	b.n	800af08 <_vfiprintf_r+0x20>
 800afca:	4621      	mov	r1, r4
 800afcc:	4630      	mov	r0, r6
 800afce:	f7ff fc63 	bl	800a898 <__swsetup_r>
 800afd2:	2800      	cmp	r0, #0
 800afd4:	d09e      	beq.n	800af14 <_vfiprintf_r+0x2c>
 800afd6:	f04f 30ff 	mov.w	r0, #4294967295
 800afda:	b01d      	add	sp, #116	; 0x74
 800afdc:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
 800afe0:	2b25      	cmp	r3, #37	; 0x25
 800afe2:	d0a7      	beq.n	800af34 <_vfiprintf_r+0x4c>
 800afe4:	46a8      	mov	r8, r5
 800afe6:	e7a0      	b.n	800af2a <_vfiprintf_r+0x42>
 800afe8:	4a43      	ldr	r2, [pc, #268]	; (800b0f8 <_vfiprintf_r+0x210>)
 800afea:	4645      	mov	r5, r8
 800afec:	1a80      	subs	r0, r0, r2
 800afee:	fa0b f000 	lsl.w	r0, fp, r0
 800aff2:	4318      	orrs	r0, r3
 800aff4:	9004      	str	r0, [sp, #16]
 800aff6:	e7bb      	b.n	800af70 <_vfiprintf_r+0x88>
 800aff8:	9a03      	ldr	r2, [sp, #12]
 800affa:	1d11      	adds	r1, r2, #4
 800affc:	6812      	ldr	r2, [r2, #0]
 800affe:	9103      	str	r1, [sp, #12]
 800b000:	2a00      	cmp	r2, #0
 800b002:	db01      	blt.n	800b008 <_vfiprintf_r+0x120>
 800b004:	9207      	str	r2, [sp, #28]
 800b006:	e004      	b.n	800b012 <_vfiprintf_r+0x12a>
 800b008:	4252      	negs	r2, r2
 800b00a:	f043 0302 	orr.w	r3, r3, #2
 800b00e:	9207      	str	r2, [sp, #28]
 800b010:	9304      	str	r3, [sp, #16]
 800b012:	f898 3000 	ldrb.w	r3, [r8]
 800b016:	2b2e      	cmp	r3, #46	; 0x2e
 800b018:	d110      	bne.n	800b03c <_vfiprintf_r+0x154>
 800b01a:	f898 3001 	ldrb.w	r3, [r8, #1]
 800b01e:	f108 0101 	add.w	r1, r8, #1
 800b022:	2b2a      	cmp	r3, #42	; 0x2a
 800b024:	d137      	bne.n	800b096 <_vfiprintf_r+0x1ae>
 800b026:	9b03      	ldr	r3, [sp, #12]
 800b028:	f108 0802 	add.w	r8, r8, #2
 800b02c:	1d1a      	adds	r2, r3, #4
 800b02e:	681b      	ldr	r3, [r3, #0]
 800b030:	9203      	str	r2, [sp, #12]
 800b032:	2b00      	cmp	r3, #0
 800b034:	bfb8      	it	lt
 800b036:	f04f 33ff 	movlt.w	r3, #4294967295
 800b03a:	9305      	str	r3, [sp, #20]
 800b03c:	4d31      	ldr	r5, [pc, #196]	; (800b104 <_vfiprintf_r+0x21c>)
 800b03e:	2203      	movs	r2, #3
 800b040:	f898 1000 	ldrb.w	r1, [r8]
 800b044:	4628      	mov	r0, r5
 800b046:	f000 faa7 	bl	800b598 <memchr>
 800b04a:	b140      	cbz	r0, 800b05e <_vfiprintf_r+0x176>
 800b04c:	2340      	movs	r3, #64	; 0x40
 800b04e:	1b40      	subs	r0, r0, r5
 800b050:	fa03 f000 	lsl.w	r0, r3, r0
 800b054:	9b04      	ldr	r3, [sp, #16]
 800b056:	f108 0801 	add.w	r8, r8, #1
 800b05a:	4303      	orrs	r3, r0
 800b05c:	9304      	str	r3, [sp, #16]
 800b05e:	f898 1000 	ldrb.w	r1, [r8]
 800b062:	2206      	movs	r2, #6
 800b064:	4828      	ldr	r0, [pc, #160]	; (800b108 <_vfiprintf_r+0x220>)
 800b066:	f108 0701 	add.w	r7, r8, #1
 800b06a:	f88d 1028 	strb.w	r1, [sp, #40]	; 0x28
 800b06e:	f000 fa93 	bl	800b598 <memchr>
 800b072:	2800      	cmp	r0, #0
 800b074:	d034      	beq.n	800b0e0 <_vfiprintf_r+0x1f8>
 800b076:	4b25      	ldr	r3, [pc, #148]	; (800b10c <_vfiprintf_r+0x224>)
 800b078:	bb03      	cbnz	r3, 800b0bc <_vfiprintf_r+0x1d4>
 800b07a:	9b03      	ldr	r3, [sp, #12]
 800b07c:	3307      	adds	r3, #7
 800b07e:	f023 0307 	bic.w	r3, r3, #7
 800b082:	3308      	adds	r3, #8
 800b084:	9303      	str	r3, [sp, #12]
 800b086:	9b09      	ldr	r3, [sp, #36]	; 0x24
 800b088:	444b      	add	r3, r9
 800b08a:	9309      	str	r3, [sp, #36]	; 0x24
 800b08c:	e74c      	b.n	800af28 <_vfiprintf_r+0x40>
 800b08e:	fb00 3202 	mla	r2, r0, r2, r3
 800b092:	2101      	movs	r1, #1
 800b094:	e786      	b.n	800afa4 <_vfiprintf_r+0xbc>
 800b096:	2300      	movs	r3, #0
 800b098:	250a      	movs	r5, #10
 800b09a:	4618      	mov	r0, r3
 800b09c:	9305      	str	r3, [sp, #20]
 800b09e:	4688      	mov	r8, r1
 800b0a0:	f898 2000 	ldrb.w	r2, [r8]
 800b0a4:	3101      	adds	r1, #1
 800b0a6:	3a30      	subs	r2, #48	; 0x30
 800b0a8:	2a09      	cmp	r2, #9
 800b0aa:	d903      	bls.n	800b0b4 <_vfiprintf_r+0x1cc>
 800b0ac:	2b00      	cmp	r3, #0
 800b0ae:	d0c5      	beq.n	800b03c <_vfiprintf_r+0x154>
 800b0b0:	9005      	str	r0, [sp, #20]
 800b0b2:	e7c3      	b.n	800b03c <_vfiprintf_r+0x154>
 800b0b4:	fb05 2000 	mla	r0, r5, r0, r2
 800b0b8:	2301      	movs	r3, #1
 800b0ba:	e7f0      	b.n	800b09e <_vfiprintf_r+0x1b6>
 800b0bc:	ab03      	add	r3, sp, #12
 800b0be:	9300      	str	r3, [sp, #0]
 800b0c0:	4622      	mov	r2, r4
 800b0c2:	4b13      	ldr	r3, [pc, #76]	; (800b110 <_vfiprintf_r+0x228>)
 800b0c4:	a904      	add	r1, sp, #16
 800b0c6:	4630      	mov	r0, r6
 800b0c8:	f3af 8000 	nop.w
 800b0cc:	f1b0 3fff 	cmp.w	r0, #4294967295
 800b0d0:	4681      	mov	r9, r0
 800b0d2:	d1d8      	bne.n	800b086 <_vfiprintf_r+0x19e>
 800b0d4:	89a3      	ldrh	r3, [r4, #12]
 800b0d6:	065b      	lsls	r3, r3, #25
 800b0d8:	f53f af7d 	bmi.w	800afd6 <_vfiprintf_r+0xee>
 800b0dc:	9809      	ldr	r0, [sp, #36]	; 0x24
 800b0de:	e77c      	b.n	800afda <_vfiprintf_r+0xf2>
 800b0e0:	ab03      	add	r3, sp, #12
 800b0e2:	9300      	str	r3, [sp, #0]
 800b0e4:	4622      	mov	r2, r4
 800b0e6:	4b0a      	ldr	r3, [pc, #40]	; (800b110 <_vfiprintf_r+0x228>)
 800b0e8:	a904      	add	r1, sp, #16
 800b0ea:	4630      	mov	r0, r6
 800b0ec:	f000 f88a 	bl	800b204 <_printf_i>
 800b0f0:	e7ec      	b.n	800b0cc <_vfiprintf_r+0x1e4>
 800b0f2:	bf00      	nop
 800b0f4:	0800b6f8 	.word	0x0800b6f8
 800b0f8:	0800b738 	.word	0x0800b738
 800b0fc:	0800b718 	.word	0x0800b718
 800b100:	0800b6d8 	.word	0x0800b6d8
 800b104:	0800b73e 	.word	0x0800b73e
 800b108:	0800b742 	.word	0x0800b742
 800b10c:	00000000 	.word	0x00000000
 800b110:	0800aec5 	.word	0x0800aec5

0800b114 <_printf_common>:
 800b114:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
 800b118:	4691      	mov	r9, r2
 800b11a:	461f      	mov	r7, r3
 800b11c:	688a      	ldr	r2, [r1, #8]
 800b11e:	690b      	ldr	r3, [r1, #16]
 800b120:	4606      	mov	r6, r0
 800b122:	4293      	cmp	r3, r2
 800b124:	bfb8      	it	lt
 800b126:	4613      	movlt	r3, r2
 800b128:	f8c9 3000 	str.w	r3, [r9]
 800b12c:	f891 2043 	ldrb.w	r2, [r1, #67]	; 0x43
 800b130:	460c      	mov	r4, r1
 800b132:	f8dd 8020 	ldr.w	r8, [sp, #32]
 800b136:	b112      	cbz	r2, 800b13e <_printf_common+0x2a>
 800b138:	3301      	adds	r3, #1
 800b13a:	f8c9 3000 	str.w	r3, [r9]
 800b13e:	6823      	ldr	r3, [r4, #0]
 800b140:	0699      	lsls	r1, r3, #26
 800b142:	bf42      	ittt	mi
 800b144:	f8d9 3000 	ldrmi.w	r3, [r9]
 800b148:	3302      	addmi	r3, #2
 800b14a:	f8c9 3000 	strmi.w	r3, [r9]
 800b14e:	6825      	ldr	r5, [r4, #0]
 800b150:	f015 0506 	ands.w	r5, r5, #6
 800b154:	d107      	bne.n	800b166 <_printf_common+0x52>
 800b156:	f104 0a19 	add.w	sl, r4, #25
 800b15a:	68e3      	ldr	r3, [r4, #12]
 800b15c:	f8d9 2000 	ldr.w	r2, [r9]
 800b160:	1a9b      	subs	r3, r3, r2
 800b162:	429d      	cmp	r5, r3
 800b164:	db2a      	blt.n	800b1bc <_printf_common+0xa8>
 800b166:	f894 3043 	ldrb.w	r3, [r4, #67]	; 0x43
 800b16a:	6822      	ldr	r2, [r4, #0]
 800b16c:	3300      	adds	r3, #0
 800b16e:	bf18      	it	ne
 800b170:	2301      	movne	r3, #1
 800b172:	0692      	lsls	r2, r2, #26
 800b174:	d42f      	bmi.n	800b1d6 <_printf_common+0xc2>
 800b176:	f104 0243 	add.w	r2, r4, #67	; 0x43
 800b17a:	4639      	mov	r1, r7
 800b17c:	4630      	mov	r0, r6
 800b17e:	47c0      	blx	r8
 800b180:	3001      	adds	r0, #1
 800b182:	d022      	beq.n	800b1ca <_printf_common+0xb6>
 800b184:	6823      	ldr	r3, [r4, #0]
 800b186:	68e5      	ldr	r5, [r4, #12]
 800b188:	f003 0306 	and.w	r3, r3, #6
 800b18c:	2b04      	cmp	r3, #4
 800b18e:	bf18      	it	ne
 800b190:	2500      	movne	r5, #0
 800b192:	f8d9 2000 	ldr.w	r2, [r9]
 800b196:	f04f 0900 	mov.w	r9, #0
 800b19a:	bf08      	it	eq
 800b19c:	1aad      	subeq	r5, r5, r2
 800b19e:	68a3      	ldr	r3, [r4, #8]
 800b1a0:	6922      	ldr	r2, [r4, #16]
 800b1a2:	bf08      	it	eq
 800b1a4:	ea25 75e5 	biceq.w	r5, r5, r5, asr #31
 800b1a8:	4293      	cmp	r3, r2
 800b1aa:	bfc4      	itt	gt
 800b1ac:	1a9b      	subgt	r3, r3, r2
 800b1ae:	18ed      	addgt	r5, r5, r3
 800b1b0:	341a      	adds	r4, #26
 800b1b2:	454d      	cmp	r5, r9
 800b1b4:	d11b      	bne.n	800b1ee <_printf_common+0xda>
 800b1b6:	2000      	movs	r0, #0
 800b1b8:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 800b1bc:	2301      	movs	r3, #1
 800b1be:	4652      	mov	r2, sl
 800b1c0:	4639      	mov	r1, r7
 800b1c2:	4630      	mov	r0, r6
 800b1c4:	47c0      	blx	r8
 800b1c6:	3001      	adds	r0, #1
 800b1c8:	d103      	bne.n	800b1d2 <_printf_common+0xbe>
 800b1ca:	f04f 30ff 	mov.w	r0, #4294967295
 800b1ce:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 800b1d2:	3501      	adds	r5, #1
 800b1d4:	e7c1      	b.n	800b15a <_printf_common+0x46>
 800b1d6:	2030      	movs	r0, #48	; 0x30
 800b1d8:	18e1      	adds	r1, r4, r3
 800b1da:	f881 0043 	strb.w	r0, [r1, #67]	; 0x43
 800b1de:	1c5a      	adds	r2, r3, #1
 800b1e0:	f894 1045 	ldrb.w	r1, [r4, #69]	; 0x45
 800b1e4:	4422      	add	r2, r4
 800b1e6:	3302      	adds	r3, #2
 800b1e8:	f882 1043 	strb.w	r1, [r2, #67]	; 0x43
 800b1ec:	e7c3      	b.n	800b176 <_printf_common+0x62>
 800b1ee:	2301      	movs	r3, #1
 800b1f0:	4622      	mov	r2, r4
 800b1f2:	4639      	mov	r1, r7
 800b1f4:	4630      	mov	r0, r6
 800b1f6:	47c0      	blx	r8
 800b1f8:	3001      	adds	r0, #1
 800b1fa:	d0e6      	beq.n	800b1ca <_printf_common+0xb6>
 800b1fc:	f109 0901 	add.w	r9, r9, #1
 800b200:	e7d7      	b.n	800b1b2 <_printf_common+0x9e>
	...

0800b204 <_printf_i>:
 800b204:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr}
 800b208:	4617      	mov	r7, r2
 800b20a:	7e0a      	ldrb	r2, [r1, #24]
 800b20c:	b085      	sub	sp, #20
 800b20e:	2a6e      	cmp	r2, #110	; 0x6e
 800b210:	4698      	mov	r8, r3
 800b212:	4606      	mov	r6, r0
 800b214:	460c      	mov	r4, r1
 800b216:	9b0c      	ldr	r3, [sp, #48]	; 0x30
 800b218:	f101 0e43 	add.w	lr, r1, #67	; 0x43
 800b21c:	f000 80bc 	beq.w	800b398 <_printf_i+0x194>
 800b220:	d81a      	bhi.n	800b258 <_printf_i+0x54>
 800b222:	2a63      	cmp	r2, #99	; 0x63
 800b224:	d02e      	beq.n	800b284 <_printf_i+0x80>
 800b226:	d80a      	bhi.n	800b23e <_printf_i+0x3a>
 800b228:	2a00      	cmp	r2, #0
 800b22a:	f000 80c8 	beq.w	800b3be <_printf_i+0x1ba>
 800b22e:	2a58      	cmp	r2, #88	; 0x58
 800b230:	f000 808a 	beq.w	800b348 <_printf_i+0x144>
 800b234:	f104 0542 	add.w	r5, r4, #66	; 0x42
 800b238:	f884 2042 	strb.w	r2, [r4, #66]	; 0x42
 800b23c:	e02a      	b.n	800b294 <_printf_i+0x90>
 800b23e:	2a64      	cmp	r2, #100	; 0x64
 800b240:	d001      	beq.n	800b246 <_printf_i+0x42>
 800b242:	2a69      	cmp	r2, #105	; 0x69
 800b244:	d1f6      	bne.n	800b234 <_printf_i+0x30>
 800b246:	6821      	ldr	r1, [r4, #0]
 800b248:	681a      	ldr	r2, [r3, #0]
 800b24a:	f011 0f80 	tst.w	r1, #128	; 0x80
 800b24e:	d023      	beq.n	800b298 <_printf_i+0x94>
 800b250:	1d11      	adds	r1, r2, #4
 800b252:	6019      	str	r1, [r3, #0]
 800b254:	6813      	ldr	r3, [r2, #0]
 800b256:	e027      	b.n	800b2a8 <_printf_i+0xa4>
 800b258:	2a73      	cmp	r2, #115	; 0x73
 800b25a:	f000 80b4 	beq.w	800b3c6 <_printf_i+0x1c2>
 800b25e:	d808      	bhi.n	800b272 <_printf_i+0x6e>
 800b260:	2a6f      	cmp	r2, #111	; 0x6f
 800b262:	d02a      	beq.n	800b2ba <_printf_i+0xb6>
 800b264:	2a70      	cmp	r2, #112	; 0x70
 800b266:	d1e5      	bne.n	800b234 <_printf_i+0x30>
 800b268:	680a      	ldr	r2, [r1, #0]
 800b26a:	f042 0220 	orr.w	r2, r2, #32
 800b26e:	600a      	str	r2, [r1, #0]
 800b270:	e003      	b.n	800b27a <_printf_i+0x76>
 800b272:	2a75      	cmp	r2, #117	; 0x75
 800b274:	d021      	beq.n	800b2ba <_printf_i+0xb6>
 800b276:	2a78      	cmp	r2, #120	; 0x78
 800b278:	d1dc      	bne.n	800b234 <_printf_i+0x30>
 800b27a:	2278      	movs	r2, #120	; 0x78
 800b27c:	496f      	ldr	r1, [pc, #444]	; (800b43c <_printf_i+0x238>)
 800b27e:	f884 2045 	strb.w	r2, [r4, #69]	; 0x45
 800b282:	e064      	b.n	800b34e <_printf_i+0x14a>
 800b284:	681a      	ldr	r2, [r3, #0]
 800b286:	f101 0542 	add.w	r5, r1, #66	; 0x42
 800b28a:	1d11      	adds	r1, r2, #4
 800b28c:	6019      	str	r1, [r3, #0]
 800b28e:	6813      	ldr	r3, [r2, #0]
 800b290:	f884 3042 	strb.w	r3, [r4, #66]	; 0x42
 800b294:	2301      	movs	r3, #1
 800b296:	e0a3      	b.n	800b3e0 <_printf_i+0x1dc>
 800b298:	f011 0f40 	tst.w	r1, #64	; 0x40
 800b29c:	f102 0104 	add.w	r1, r2, #4
 800b2a0:	6019      	str	r1, [r3, #0]
 800b2a2:	d0d7      	beq.n	800b254 <_printf_i+0x50>
 800b2a4:	f9b2 3000 	ldrsh.w	r3, [r2]
 800b2a8:	2b00      	cmp	r3, #0
 800b2aa:	da03      	bge.n	800b2b4 <_printf_i+0xb0>
 800b2ac:	222d      	movs	r2, #45	; 0x2d
 800b2ae:	425b      	negs	r3, r3
 800b2b0:	f884 2043 	strb.w	r2, [r4, #67]	; 0x43
 800b2b4:	4962      	ldr	r1, [pc, #392]	; (800b440 <_printf_i+0x23c>)
 800b2b6:	220a      	movs	r2, #10
 800b2b8:	e017      	b.n	800b2ea <_printf_i+0xe6>
 800b2ba:	6820      	ldr	r0, [r4, #0]
 800b2bc:	6819      	ldr	r1, [r3, #0]
 800b2be:	f010 0f80 	tst.w	r0, #128	; 0x80
 800b2c2:	d003      	beq.n	800b2cc <_printf_i+0xc8>
 800b2c4:	1d08      	adds	r0, r1, #4
 800b2c6:	6018      	str	r0, [r3, #0]
 800b2c8:	680b      	ldr	r3, [r1, #0]
 800b2ca:	e006      	b.n	800b2da <_printf_i+0xd6>
 800b2cc:	f010 0f40 	tst.w	r0, #64	; 0x40
 800b2d0:	f101 0004 	add.w	r0, r1, #4
 800b2d4:	6018      	str	r0, [r3, #0]
 800b2d6:	d0f7      	beq.n	800b2c8 <_printf_i+0xc4>
 800b2d8:	880b      	ldrh	r3, [r1, #0]
 800b2da:	2a6f      	cmp	r2, #111	; 0x6f
 800b2dc:	bf14      	ite	ne
 800b2de:	220a      	movne	r2, #10
 800b2e0:	2208      	moveq	r2, #8
 800b2e2:	4957      	ldr	r1, [pc, #348]	; (800b440 <_printf_i+0x23c>)
 800b2e4:	2000      	movs	r0, #0
 800b2e6:	f884 0043 	strb.w	r0, [r4, #67]	; 0x43
 800b2ea:	6865      	ldr	r5, [r4, #4]
 800b2ec:	2d00      	cmp	r5, #0
 800b2ee:	60a5      	str	r5, [r4, #8]
 800b2f0:	f2c0 809c 	blt.w	800b42c <_printf_i+0x228>
 800b2f4:	6820      	ldr	r0, [r4, #0]
 800b2f6:	f020 0004 	bic.w	r0, r0, #4
 800b2fa:	6020      	str	r0, [r4, #0]
 800b2fc:	2b00      	cmp	r3, #0
 800b2fe:	d13f      	bne.n	800b380 <_printf_i+0x17c>
 800b300:	2d00      	cmp	r5, #0
 800b302:	f040 8095 	bne.w	800b430 <_printf_i+0x22c>
 800b306:	4675      	mov	r5, lr
 800b308:	2a08      	cmp	r2, #8
 800b30a:	d10b      	bne.n	800b324 <_printf_i+0x120>
 800b30c:	6823      	ldr	r3, [r4, #0]
 800b30e:	07da      	lsls	r2, r3, #31
 800b310:	d508      	bpl.n	800b324 <_printf_i+0x120>
 800b312:	6923      	ldr	r3, [r4, #16]
 800b314:	6862      	ldr	r2, [r4, #4]
 800b316:	429a      	cmp	r2, r3
 800b318:	bfde      	ittt	le
 800b31a:	2330      	movle	r3, #48	; 0x30
 800b31c:	f805 3c01 	strble.w	r3, [r5, #-1]
 800b320:	f105 35ff 	addle.w	r5, r5, #4294967295
 800b324:	ebae 0305 	sub.w	r3, lr, r5
 800b328:	6123      	str	r3, [r4, #16]
 800b32a:	f8cd 8000 	str.w	r8, [sp]
 800b32e:	463b      	mov	r3, r7
 800b330:	aa03      	add	r2, sp, #12
 800b332:	4621      	mov	r1, r4
 800b334:	4630      	mov	r0, r6
 800b336:	f7ff feed 	bl	800b114 <_printf_common>
 800b33a:	3001      	adds	r0, #1
 800b33c:	d155      	bne.n	800b3ea <_printf_i+0x1e6>
 800b33e:	f04f 30ff 	mov.w	r0, #4294967295
 800b342:	b005      	add	sp, #20
 800b344:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
 800b348:	f881 2045 	strb.w	r2, [r1, #69]	; 0x45
 800b34c:	493c      	ldr	r1, [pc, #240]	; (800b440 <_printf_i+0x23c>)
 800b34e:	6822      	ldr	r2, [r4, #0]
 800b350:	6818      	ldr	r0, [r3, #0]
 800b352:	f012 0f80 	tst.w	r2, #128	; 0x80
 800b356:	f100 0504 	add.w	r5, r0, #4
 800b35a:	601d      	str	r5, [r3, #0]
 800b35c:	d001      	beq.n	800b362 <_printf_i+0x15e>
 800b35e:	6803      	ldr	r3, [r0, #0]
 800b360:	e002      	b.n	800b368 <_printf_i+0x164>
 800b362:	0655      	lsls	r5, r2, #25
 800b364:	d5fb      	bpl.n	800b35e <_printf_i+0x15a>
 800b366:	8803      	ldrh	r3, [r0, #0]
 800b368:	07d0      	lsls	r0, r2, #31
 800b36a:	bf44      	itt	mi
 800b36c:	f042 0220 	orrmi.w	r2, r2, #32
 800b370:	6022      	strmi	r2, [r4, #0]
 800b372:	b91b      	cbnz	r3, 800b37c <_printf_i+0x178>
 800b374:	6822      	ldr	r2, [r4, #0]
 800b376:	f022 0220 	bic.w	r2, r2, #32
 800b37a:	6022      	str	r2, [r4, #0]
 800b37c:	2210      	movs	r2, #16
 800b37e:	e7b1      	b.n	800b2e4 <_printf_i+0xe0>
 800b380:	4675      	mov	r5, lr
 800b382:	fbb3 f0f2 	udiv	r0, r3, r2
 800b386:	fb02 3310 	mls	r3, r2, r0, r3
 800b38a:	5ccb      	ldrb	r3, [r1, r3]
 800b38c:	f805 3d01 	strb.w	r3, [r5, #-1]!
 800b390:	4603      	mov	r3, r0
 800b392:	2800      	cmp	r0, #0
 800b394:	d1f5      	bne.n	800b382 <_printf_i+0x17e>
 800b396:	e7b7      	b.n	800b308 <_printf_i+0x104>
 800b398:	6808      	ldr	r0, [r1, #0]
 800b39a:	681a      	ldr	r2, [r3, #0]
 800b39c:	f010 0f80 	tst.w	r0, #128	; 0x80
 800b3a0:	6949      	ldr	r1, [r1, #20]
 800b3a2:	d004      	beq.n	800b3ae <_printf_i+0x1aa>
 800b3a4:	1d10      	adds	r0, r2, #4
 800b3a6:	6018      	str	r0, [r3, #0]
 800b3a8:	6813      	ldr	r3, [r2, #0]
 800b3aa:	6019      	str	r1, [r3, #0]
 800b3ac:	e007      	b.n	800b3be <_printf_i+0x1ba>
 800b3ae:	f010 0f40 	tst.w	r0, #64	; 0x40
 800b3b2:	f102 0004 	add.w	r0, r2, #4
 800b3b6:	6018      	str	r0, [r3, #0]
 800b3b8:	6813      	ldr	r3, [r2, #0]
 800b3ba:	d0f6      	beq.n	800b3aa <_printf_i+0x1a6>
 800b3bc:	8019      	strh	r1, [r3, #0]
 800b3be:	2300      	movs	r3, #0
 800b3c0:	4675      	mov	r5, lr
 800b3c2:	6123      	str	r3, [r4, #16]
 800b3c4:	e7b1      	b.n	800b32a <_printf_i+0x126>
 800b3c6:	681a      	ldr	r2, [r3, #0]
 800b3c8:	1d11      	adds	r1, r2, #4
 800b3ca:	6019      	str	r1, [r3, #0]
 800b3cc:	6815      	ldr	r5, [r2, #0]
 800b3ce:	2100      	movs	r1, #0
 800b3d0:	6862      	ldr	r2, [r4, #4]
 800b3d2:	4628      	mov	r0, r5
 800b3d4:	f000 f8e0 	bl	800b598 <memchr>
 800b3d8:	b108      	cbz	r0, 800b3de <_printf_i+0x1da>
 800b3da:	1b40      	subs	r0, r0, r5
 800b3dc:	6060      	str	r0, [r4, #4]
 800b3de:	6863      	ldr	r3, [r4, #4]
 800b3e0:	6123      	str	r3, [r4, #16]
 800b3e2:	2300      	movs	r3, #0
 800b3e4:	f884 3043 	strb.w	r3, [r4, #67]	; 0x43
 800b3e8:	e79f      	b.n	800b32a <_printf_i+0x126>
 800b3ea:	6923      	ldr	r3, [r4, #16]
 800b3ec:	462a      	mov	r2, r5
 800b3ee:	4639      	mov	r1, r7
 800b3f0:	4630      	mov	r0, r6
 800b3f2:	47c0      	blx	r8
 800b3f4:	3001      	adds	r0, #1
 800b3f6:	d0a2      	beq.n	800b33e <_printf_i+0x13a>
 800b3f8:	6823      	ldr	r3, [r4, #0]
 800b3fa:	079b      	lsls	r3, r3, #30
 800b3fc:	d507      	bpl.n	800b40e <_printf_i+0x20a>
 800b3fe:	2500      	movs	r5, #0
 800b400:	f104 0919 	add.w	r9, r4, #25
 800b404:	68e3      	ldr	r3, [r4, #12]
 800b406:	9a03      	ldr	r2, [sp, #12]
 800b408:	1a9b      	subs	r3, r3, r2
 800b40a:	429d      	cmp	r5, r3
 800b40c:	db05      	blt.n	800b41a <_printf_i+0x216>
 800b40e:	68e0      	ldr	r0, [r4, #12]
 800b410:	9b03      	ldr	r3, [sp, #12]
 800b412:	4298      	cmp	r0, r3
 800b414:	bfb8      	it	lt
 800b416:	4618      	movlt	r0, r3
 800b418:	e793      	b.n	800b342 <_printf_i+0x13e>
 800b41a:	2301      	movs	r3, #1
 800b41c:	464a      	mov	r2, r9
 800b41e:	4639      	mov	r1, r7
 800b420:	4630      	mov	r0, r6
 800b422:	47c0      	blx	r8
 800b424:	3001      	adds	r0, #1
 800b426:	d08a      	beq.n	800b33e <_printf_i+0x13a>
 800b428:	3501      	adds	r5, #1
 800b42a:	e7eb      	b.n	800b404 <_printf_i+0x200>
 800b42c:	2b00      	cmp	r3, #0
 800b42e:	d1a7      	bne.n	800b380 <_printf_i+0x17c>
 800b430:	780b      	ldrb	r3, [r1, #0]
 800b432:	f104 0542 	add.w	r5, r4, #66	; 0x42
 800b436:	f884 3042 	strb.w	r3, [r4, #66]	; 0x42
 800b43a:	e765      	b.n	800b308 <_printf_i+0x104>
 800b43c:	0800b75a 	.word	0x0800b75a
 800b440:	0800b749 	.word	0x0800b749

0800b444 <_sbrk_r>:
 800b444:	b538      	push	{r3, r4, r5, lr}
 800b446:	2300      	movs	r3, #0
 800b448:	4c05      	ldr	r4, [pc, #20]	; (800b460 <_sbrk_r+0x1c>)
 800b44a:	4605      	mov	r5, r0
 800b44c:	4608      	mov	r0, r1
 800b44e:	6023      	str	r3, [r4, #0]
 800b450:	f7fe ff94 	bl	800a37c <_sbrk>
 800b454:	1c43      	adds	r3, r0, #1
 800b456:	d102      	bne.n	800b45e <_sbrk_r+0x1a>
 800b458:	6823      	ldr	r3, [r4, #0]
 800b45a:	b103      	cbz	r3, 800b45e <_sbrk_r+0x1a>
 800b45c:	602b      	str	r3, [r5, #0]
 800b45e:	bd38      	pop	{r3, r4, r5, pc}
 800b460:	20000d60 	.word	0x20000d60

0800b464 <__sread>:
 800b464:	b510      	push	{r4, lr}
 800b466:	460c      	mov	r4, r1
 800b468:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 800b46c:	f000 f8a4 	bl	800b5b8 <_read_r>
 800b470:	2800      	cmp	r0, #0
 800b472:	bfab      	itete	ge
 800b474:	6d63      	ldrge	r3, [r4, #84]	; 0x54
 800b476:	89a3      	ldrhlt	r3, [r4, #12]
 800b478:	181b      	addge	r3, r3, r0
 800b47a:	f423 5380 	biclt.w	r3, r3, #4096	; 0x1000
 800b47e:	bfac      	ite	ge
 800b480:	6563      	strge	r3, [r4, #84]	; 0x54
 800b482:	81a3      	strhlt	r3, [r4, #12]
 800b484:	bd10      	pop	{r4, pc}

0800b486 <__swrite>:
 800b486:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
 800b48a:	461f      	mov	r7, r3
 800b48c:	898b      	ldrh	r3, [r1, #12]
 800b48e:	4605      	mov	r5, r0
 800b490:	05db      	lsls	r3, r3, #23
 800b492:	460c      	mov	r4, r1
 800b494:	4616      	mov	r6, r2
 800b496:	d505      	bpl.n	800b4a4 <__swrite+0x1e>
 800b498:	2302      	movs	r3, #2
 800b49a:	2200      	movs	r2, #0
 800b49c:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 800b4a0:	f000 f868 	bl	800b574 <_lseek_r>
 800b4a4:	89a3      	ldrh	r3, [r4, #12]
 800b4a6:	4632      	mov	r2, r6
 800b4a8:	f423 5380 	bic.w	r3, r3, #4096	; 0x1000
 800b4ac:	81a3      	strh	r3, [r4, #12]
 800b4ae:	f9b4 100e 	ldrsh.w	r1, [r4, #14]
 800b4b2:	463b      	mov	r3, r7
 800b4b4:	4628      	mov	r0, r5
 800b4b6:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
 800b4ba:	f000 b817 	b.w	800b4ec <_write_r>

0800b4be <__sseek>:
 800b4be:	b510      	push	{r4, lr}
 800b4c0:	460c      	mov	r4, r1
 800b4c2:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 800b4c6:	f000 f855 	bl	800b574 <_lseek_r>
 800b4ca:	1c43      	adds	r3, r0, #1
 800b4cc:	89a3      	ldrh	r3, [r4, #12]
 800b4ce:	bf15      	itete	ne
 800b4d0:	6560      	strne	r0, [r4, #84]	; 0x54
 800b4d2:	f423 5380 	biceq.w	r3, r3, #4096	; 0x1000
 800b4d6:	f443 5380 	orrne.w	r3, r3, #4096	; 0x1000
 800b4da:	81a3      	strheq	r3, [r4, #12]
 800b4dc:	bf18      	it	ne
 800b4de:	81a3      	strhne	r3, [r4, #12]
 800b4e0:	bd10      	pop	{r4, pc}

0800b4e2 <__sclose>:
 800b4e2:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 800b4e6:	f000 b813 	b.w	800b510 <_close_r>
	...

0800b4ec <_write_r>:
 800b4ec:	b538      	push	{r3, r4, r5, lr}
 800b4ee:	4605      	mov	r5, r0
 800b4f0:	4608      	mov	r0, r1
 800b4f2:	4611      	mov	r1, r2
 800b4f4:	2200      	movs	r2, #0
 800b4f6:	4c05      	ldr	r4, [pc, #20]	; (800b50c <_write_r+0x20>)
 800b4f8:	6022      	str	r2, [r4, #0]
 800b4fa:	461a      	mov	r2, r3
 800b4fc:	f7fe fb16 	bl	8009b2c <_write>
 800b500:	1c43      	adds	r3, r0, #1
 800b502:	d102      	bne.n	800b50a <_write_r+0x1e>
 800b504:	6823      	ldr	r3, [r4, #0]
 800b506:	b103      	cbz	r3, 800b50a <_write_r+0x1e>
 800b508:	602b      	str	r3, [r5, #0]
 800b50a:	bd38      	pop	{r3, r4, r5, pc}
 800b50c:	20000d60 	.word	0x20000d60

0800b510 <_close_r>:
 800b510:	b538      	push	{r3, r4, r5, lr}
 800b512:	2300      	movs	r3, #0
 800b514:	4c05      	ldr	r4, [pc, #20]	; (800b52c <_close_r+0x1c>)
 800b516:	4605      	mov	r5, r0
 800b518:	4608      	mov	r0, r1
 800b51a:	6023      	str	r3, [r4, #0]
 800b51c:	f7fe ff48 	bl	800a3b0 <_close>
 800b520:	1c43      	adds	r3, r0, #1
 800b522:	d102      	bne.n	800b52a <_close_r+0x1a>
 800b524:	6823      	ldr	r3, [r4, #0]
 800b526:	b103      	cbz	r3, 800b52a <_close_r+0x1a>
 800b528:	602b      	str	r3, [r5, #0]
 800b52a:	bd38      	pop	{r3, r4, r5, pc}
 800b52c:	20000d60 	.word	0x20000d60

0800b530 <_fstat_r>:
 800b530:	b538      	push	{r3, r4, r5, lr}
 800b532:	2300      	movs	r3, #0
 800b534:	4c06      	ldr	r4, [pc, #24]	; (800b550 <_fstat_r+0x20>)
 800b536:	4605      	mov	r5, r0
 800b538:	4608      	mov	r0, r1
 800b53a:	4611      	mov	r1, r2
 800b53c:	6023      	str	r3, [r4, #0]
 800b53e:	f7fe ff3a 	bl	800a3b6 <_fstat>
 800b542:	1c43      	adds	r3, r0, #1
 800b544:	d102      	bne.n	800b54c <_fstat_r+0x1c>
 800b546:	6823      	ldr	r3, [r4, #0]
 800b548:	b103      	cbz	r3, 800b54c <_fstat_r+0x1c>
 800b54a:	602b      	str	r3, [r5, #0]
 800b54c:	bd38      	pop	{r3, r4, r5, pc}
 800b54e:	bf00      	nop
 800b550:	20000d60 	.word	0x20000d60

0800b554 <_isatty_r>:
 800b554:	b538      	push	{r3, r4, r5, lr}
 800b556:	2300      	movs	r3, #0
 800b558:	4c05      	ldr	r4, [pc, #20]	; (800b570 <_isatty_r+0x1c>)
 800b55a:	4605      	mov	r5, r0
 800b55c:	4608      	mov	r0, r1
 800b55e:	6023      	str	r3, [r4, #0]
 800b560:	f7fe ff2e 	bl	800a3c0 <_isatty>
 800b564:	1c43      	adds	r3, r0, #1
 800b566:	d102      	bne.n	800b56e <_isatty_r+0x1a>
 800b568:	6823      	ldr	r3, [r4, #0]
 800b56a:	b103      	cbz	r3, 800b56e <_isatty_r+0x1a>
 800b56c:	602b      	str	r3, [r5, #0]
 800b56e:	bd38      	pop	{r3, r4, r5, pc}
 800b570:	20000d60 	.word	0x20000d60

0800b574 <_lseek_r>:
 800b574:	b538      	push	{r3, r4, r5, lr}
 800b576:	4605      	mov	r5, r0
 800b578:	4608      	mov	r0, r1
 800b57a:	4611      	mov	r1, r2
 800b57c:	2200      	movs	r2, #0
 800b57e:	4c05      	ldr	r4, [pc, #20]	; (800b594 <_lseek_r+0x20>)
 800b580:	6022      	str	r2, [r4, #0]
 800b582:	461a      	mov	r2, r3
 800b584:	f7fe ff1e 	bl	800a3c4 <_lseek>
 800b588:	1c43      	adds	r3, r0, #1
 800b58a:	d102      	bne.n	800b592 <_lseek_r+0x1e>
 800b58c:	6823      	ldr	r3, [r4, #0]
 800b58e:	b103      	cbz	r3, 800b592 <_lseek_r+0x1e>
 800b590:	602b      	str	r3, [r5, #0]
 800b592:	bd38      	pop	{r3, r4, r5, pc}
 800b594:	20000d60 	.word	0x20000d60

0800b598 <memchr>:
 800b598:	b510      	push	{r4, lr}
 800b59a:	b2c9      	uxtb	r1, r1
 800b59c:	4402      	add	r2, r0
 800b59e:	4290      	cmp	r0, r2
 800b5a0:	4603      	mov	r3, r0
 800b5a2:	d101      	bne.n	800b5a8 <memchr+0x10>
 800b5a4:	2000      	movs	r0, #0
 800b5a6:	bd10      	pop	{r4, pc}
 800b5a8:	781c      	ldrb	r4, [r3, #0]
 800b5aa:	3001      	adds	r0, #1
 800b5ac:	428c      	cmp	r4, r1
 800b5ae:	d1f6      	bne.n	800b59e <memchr+0x6>
 800b5b0:	4618      	mov	r0, r3
 800b5b2:	bd10      	pop	{r4, pc}

0800b5b4 <__malloc_lock>:
 800b5b4:	4770      	bx	lr

0800b5b6 <__malloc_unlock>:
 800b5b6:	4770      	bx	lr

0800b5b8 <_read_r>:
 800b5b8:	b538      	push	{r3, r4, r5, lr}
 800b5ba:	4605      	mov	r5, r0
 800b5bc:	4608      	mov	r0, r1
 800b5be:	4611      	mov	r1, r2
 800b5c0:	2200      	movs	r2, #0
 800b5c2:	4c05      	ldr	r4, [pc, #20]	; (800b5d8 <_read_r+0x20>)
 800b5c4:	6022      	str	r2, [r4, #0]
 800b5c6:	461a      	mov	r2, r3
 800b5c8:	f7fe feca 	bl	800a360 <_read>
 800b5cc:	1c43      	adds	r3, r0, #1
 800b5ce:	d102      	bne.n	800b5d6 <_read_r+0x1e>
 800b5d0:	6823      	ldr	r3, [r4, #0]
 800b5d2:	b103      	cbz	r3, 800b5d6 <_read_r+0x1e>
 800b5d4:	602b      	str	r3, [r5, #0]
 800b5d6:	bd38      	pop	{r3, r4, r5, pc}
 800b5d8:	20000d60 	.word	0x20000d60

0800b5dc <_init>:
 800b5dc:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 800b5de:	bf00      	nop
 800b5e0:	bcf8      	pop	{r3, r4, r5, r6, r7}
 800b5e2:	bc08      	pop	{r3}
 800b5e4:	469e      	mov	lr, r3
 800b5e6:	4770      	bx	lr

0800b5e8 <_fini>:
 800b5e8:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 800b5ea:	bf00      	nop
 800b5ec:	bcf8      	pop	{r3, r4, r5, r6, r7}
 800b5ee:	bc08      	pop	{r3}
 800b5f0:	469e      	mov	lr, r3
 800b5f2:	4770      	bx	lr