STM32F103_WifiAttenCtrlTest/Debug/STM32F103_WifiAttenCtrlTest.list

STM32F103_WifiAttenCtrlTest.elf:     file format elf32-littlearm

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .isr_vector   000001e4  08004000  08004000  00004000  2**0
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  1 .text         000034e8  080041e4  080041e4  000041e4  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  2 .rodata       00000160  080076cc  080076cc  000076cc  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  3 .init_array   00000004  0800782c  0800782c  0000782c  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  4 .fini_array   00000004  08007830  08007830  00007830  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  5 .data         00000270  20000000  08007834  00010000  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  6 .bss          00000af8  20000270  08007aa4  00010270  2**2
                  ALLOC
  7 ._user_heap_stack 00000600  20000d68  08007aa4  00010d68  2**0
                  ALLOC
  8 .ARM.attributes 00000029  00000000  00000000  00010270  2**0
                  CONTENTS, READONLY
  9 .debug_info   0001411f  00000000  00000000  00010299  2**0
                  CONTENTS, READONLY, DEBUGGING
 10 .debug_abbrev 00002f37  00000000  00000000  000243b8  2**0
                  CONTENTS, READONLY, DEBUGGING
 11 .debug_loc    00007d3e  00000000  00000000  000272ef  2**0
                  CONTENTS, READONLY, DEBUGGING
 12 .debug_aranges 00000bd8  00000000  00000000  0002f030  2**3
                  CONTENTS, READONLY, DEBUGGING
 13 .debug_ranges 00000fb8  00000000  00000000  0002fc08  2**3
                  CONTENTS, READONLY, DEBUGGING
 14 .debug_line   00006d9b  00000000  00000000  00030bc0  2**0
                  CONTENTS, READONLY, DEBUGGING
 15 .debug_str    000044a3  00000000  00000000  0003795b  2**0
                  CONTENTS, READONLY, DEBUGGING
 16 .comment      0000007c  00000000  00000000  0003bdfe  2**0
                  CONTENTS, READONLY
 17 .debug_frame  00002a70  00000000  00000000  0003be7c  2**2
                  CONTENTS, READONLY, DEBUGGING

Disassembly of section .text:

080041e4 <__do_global_dtors_aux>:
 80041e4:	b510      	push	{r4, lr}
 80041e6:	4c05      	ldr	r4, [pc, #20]	; (80041fc <__do_global_dtors_aux+0x18>)
 80041e8:	7823      	ldrb	r3, [r4, #0]
 80041ea:	b933      	cbnz	r3, 80041fa <__do_global_dtors_aux+0x16>
 80041ec:	4b04      	ldr	r3, [pc, #16]	; (8004200 <__do_global_dtors_aux+0x1c>)
 80041ee:	b113      	cbz	r3, 80041f6 <__do_global_dtors_aux+0x12>
 80041f0:	4804      	ldr	r0, [pc, #16]	; (8004204 <__do_global_dtors_aux+0x20>)
 80041f2:	f3af 8000 	nop.w
 80041f6:	2301      	movs	r3, #1
 80041f8:	7023      	strb	r3, [r4, #0]
 80041fa:	bd10      	pop	{r4, pc}
 80041fc:	20000270 	.word	0x20000270
 8004200:	00000000 	.word	0x00000000
 8004204:	080076b4 	.word	0x080076b4

08004208 <frame_dummy>:
 8004208:	b508      	push	{r3, lr}
 800420a:	4b03      	ldr	r3, [pc, #12]	; (8004218 <frame_dummy+0x10>)
 800420c:	b11b      	cbz	r3, 8004216 <frame_dummy+0xe>
 800420e:	4903      	ldr	r1, [pc, #12]	; (800421c <frame_dummy+0x14>)
 8004210:	4803      	ldr	r0, [pc, #12]	; (8004220 <frame_dummy+0x18>)
 8004212:	f3af 8000 	nop.w
 8004216:	bd08      	pop	{r3, pc}
 8004218:	00000000 	.word	0x00000000
 800421c:	20000274 	.word	0x20000274
 8004220:	080076b4 	.word	0x080076b4

08004224 <HAL_InitTick>:
  *       implementation  in user file.
  * @param TickPriority Tick interrupt priority.
  * @retval HAL status
  */
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
 8004224:	b538      	push	{r3, r4, r5, lr}
  /* Configure the SysTick to have interrupt in 1ms time basis*/
  if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
 8004226:	4b0e      	ldr	r3, [pc, #56]	; (8004260 <HAL_InitTick+0x3c>)
{
 8004228:	4605      	mov	r5, r0
  if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
 800422a:	7818      	ldrb	r0, [r3, #0]
 800422c:	f44f 737a 	mov.w	r3, #1000	; 0x3e8
 8004230:	fbb3 f3f0 	udiv	r3, r3, r0
 8004234:	4a0b      	ldr	r2, [pc, #44]	; (8004264 <HAL_InitTick+0x40>)
 8004236:	6810      	ldr	r0, [r2, #0]
 8004238:	fbb0 f0f3 	udiv	r0, r0, r3
 800423c:	f000 fa4a 	bl	80046d4 <HAL_SYSTICK_Config>
 8004240:	4604      	mov	r4, r0
 8004242:	b958      	cbnz	r0, 800425c <HAL_InitTick+0x38>
  {
    return HAL_ERROR;
  }

  /* Configure the SysTick IRQ priority */
  if (TickPriority < (1UL << __NVIC_PRIO_BITS))
 8004244:	2d0f      	cmp	r5, #15
 8004246:	d809      	bhi.n	800425c <HAL_InitTick+0x38>
  {
    HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
 8004248:	4602      	mov	r2, r0
 800424a:	4629      	mov	r1, r5
 800424c:	f04f 30ff 	mov.w	r0, #4294967295
 8004250:	f000 f9fe 	bl	8004650 <HAL_NVIC_SetPriority>
    uwTickPrio = TickPriority;
 8004254:	4b04      	ldr	r3, [pc, #16]	; (8004268 <HAL_InitTick+0x44>)
 8004256:	4620      	mov	r0, r4
 8004258:	601d      	str	r5, [r3, #0]
 800425a:	bd38      	pop	{r3, r4, r5, pc}
    return HAL_ERROR;
 800425c:	2001      	movs	r0, #1
    return HAL_ERROR;
  }

  /* Return function status */
  return HAL_OK;
}
 800425e:	bd38      	pop	{r3, r4, r5, pc}
 8004260:	20000000 	.word	0x20000000
 8004264:	20000208 	.word	0x20000208
 8004268:	20000004 	.word	0x20000004

0800426c <HAL_Init>:
  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
 800426c:	4a07      	ldr	r2, [pc, #28]	; (800428c <HAL_Init+0x20>)
{
 800426e:	b508      	push	{r3, lr}
  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
 8004270:	6813      	ldr	r3, [r2, #0]
  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
 8004272:	2003      	movs	r0, #3
  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
 8004274:	f043 0310 	orr.w	r3, r3, #16
 8004278:	6013      	str	r3, [r2, #0]
  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
 800427a:	f000 f9d7 	bl	800462c <HAL_NVIC_SetPriorityGrouping>
  HAL_InitTick(TICK_INT_PRIORITY);
 800427e:	2000      	movs	r0, #0
 8004280:	f7ff ffd0 	bl	8004224 <HAL_InitTick>
  HAL_MspInit();
 8004284:	f001 feb2 	bl	8005fec <HAL_MspInit>
}
 8004288:	2000      	movs	r0, #0
 800428a:	bd08      	pop	{r3, pc}
 800428c:	40022000 	.word	0x40022000

08004290 <HAL_IncTick>:
  *      implementations in user file.
  * @retval None
  */
__weak void HAL_IncTick(void)
{
  uwTick += uwTickFreq;
 8004290:	4a03      	ldr	r2, [pc, #12]	; (80042a0 <HAL_IncTick+0x10>)
 8004292:	4b04      	ldr	r3, [pc, #16]	; (80042a4 <HAL_IncTick+0x14>)
 8004294:	6811      	ldr	r1, [r2, #0]
 8004296:	781b      	ldrb	r3, [r3, #0]
 8004298:	440b      	add	r3, r1
 800429a:	6013      	str	r3, [r2, #0]
 800429c:	4770      	bx	lr
 800429e:	bf00      	nop
 80042a0:	200002a8 	.word	0x200002a8
 80042a4:	20000000 	.word	0x20000000

080042a8 <HAL_GetTick>:
  *       implementations in user file.
  * @retval tick value
  */
__weak uint32_t HAL_GetTick(void)
{
  return uwTick;
 80042a8:	4b01      	ldr	r3, [pc, #4]	; (80042b0 <HAL_GetTick+0x8>)
 80042aa:	6818      	ldr	r0, [r3, #0]
}
 80042ac:	4770      	bx	lr
 80042ae:	bf00      	nop
 80042b0:	200002a8 	.word	0x200002a8

080042b4 <HAL_Delay>:
  *       implementations in user file.
  * @param Delay specifies the delay time length, in milliseconds.
  * @retval None
  */
__weak void HAL_Delay(uint32_t Delay)
{
 80042b4:	b538      	push	{r3, r4, r5, lr}
 80042b6:	4604      	mov	r4, r0
  uint32_t tickstart = HAL_GetTick();
 80042b8:	f7ff fff6 	bl	80042a8 <HAL_GetTick>
 80042bc:	4605      	mov	r5, r0
  uint32_t wait = Delay;

  /* Add a freq to guarantee minimum wait */
  if (wait < HAL_MAX_DELAY)
 80042be:	1c63      	adds	r3, r4, #1
  {
    wait += (uint32_t)(uwTickFreq);
 80042c0:	bf1e      	ittt	ne
 80042c2:	4b04      	ldrne	r3, [pc, #16]	; (80042d4 <HAL_Delay+0x20>)
 80042c4:	781b      	ldrbne	r3, [r3, #0]
 80042c6:	18e4      	addne	r4, r4, r3
  }

  while ((HAL_GetTick() - tickstart) < wait)
 80042c8:	f7ff ffee 	bl	80042a8 <HAL_GetTick>
 80042cc:	1b40      	subs	r0, r0, r5
 80042ce:	4284      	cmp	r4, r0
 80042d0:	d8fa      	bhi.n	80042c8 <HAL_Delay+0x14>
  {
  }
}
 80042d2:	bd38      	pop	{r3, r4, r5, pc}
 80042d4:	20000000 	.word	0x20000000

080042d8 <HAL_ADC_ConvCpltCallback>:
 80042d8:	4770      	bx	lr

080042da <HAL_ADC_LevelOutOfWindowCallback>:
 80042da:	4770      	bx	lr

080042dc <HAL_ADC_IRQHandler>:
  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
  assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
  
  
  /* ========== Check End of Conversion flag for regular group ========== */
  if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC))
 80042dc:	6803      	ldr	r3, [r0, #0]
{
 80042de:	b510      	push	{r4, lr}
  if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC))
 80042e0:	685a      	ldr	r2, [r3, #4]
{
 80042e2:	4604      	mov	r4, r0
  if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC))
 80042e4:	0690      	lsls	r0, r2, #26
 80042e6:	d527      	bpl.n	8004338 <HAL_ADC_IRQHandler+0x5c>
  {
    if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) )
 80042e8:	681a      	ldr	r2, [r3, #0]
 80042ea:	0791      	lsls	r1, r2, #30
 80042ec:	d524      	bpl.n	8004338 <HAL_ADC_IRQHandler+0x5c>
    {
      /* Update state machine on conversion status if not in error state */
      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
 80042ee:	6aa2      	ldr	r2, [r4, #40]	; 0x28
 80042f0:	06d2      	lsls	r2, r2, #27
      {
        /* Set ADC state */
        SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 
 80042f2:	bf5e      	ittt	pl
 80042f4:	6aa2      	ldrpl	r2, [r4, #40]	; 0x28
 80042f6:	f442 7200 	orrpl.w	r2, r2, #512	; 0x200
 80042fa:	62a2      	strpl	r2, [r4, #40]	; 0x28
      /* Determine whether any further conversion upcoming on group regular   */
      /* by external trigger, continuous mode or scan sequence on going.      */
      /* Note: On STM32F1 devices, in case of sequencer enabled               */
      /*       (several ranks selected), end of conversion flag is raised     */
      /*       at the end of the sequence.                                    */
      if(ADC_IS_SOFTWARE_START_REGULAR(hadc)        && 
 80042fc:	689a      	ldr	r2, [r3, #8]
 80042fe:	f402 2260 	and.w	r2, r2, #917504	; 0xe0000
 8004302:	f5b2 2f60 	cmp.w	r2, #917504	; 0xe0000
 8004306:	d110      	bne.n	800432a <HAL_ADC_IRQHandler+0x4e>
 8004308:	7b22      	ldrb	r2, [r4, #12]
 800430a:	b972      	cbnz	r2, 800432a <HAL_ADC_IRQHandler+0x4e>
         (hadc->Init.ContinuousConvMode == DISABLE)   )
      {
        /* Disable ADC end of conversion interrupt on group regular */
        __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
 800430c:	685a      	ldr	r2, [r3, #4]
 800430e:	f022 0220 	bic.w	r2, r2, #32
 8004312:	605a      	str	r2, [r3, #4]
        
        /* Set ADC state */
        CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);   
 8004314:	6aa3      	ldr	r3, [r4, #40]	; 0x28
 8004316:	f423 7380 	bic.w	r3, r3, #256	; 0x100
 800431a:	62a3      	str	r3, [r4, #40]	; 0x28
        
        if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
 800431c:	6aa3      	ldr	r3, [r4, #40]	; 0x28
 800431e:	04db      	lsls	r3, r3, #19
        {
          SET_BIT(hadc->State, HAL_ADC_STATE_READY);
 8004320:	bf5e      	ittt	pl
 8004322:	6aa3      	ldrpl	r3, [r4, #40]	; 0x28
 8004324:	f043 0301 	orrpl.w	r3, r3, #1
 8004328:	62a3      	strpl	r3, [r4, #40]	; 0x28

      /* Conversion complete callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
      hadc->ConvCpltCallback(hadc);
#else
      HAL_ADC_ConvCpltCallback(hadc);
 800432a:	4620      	mov	r0, r4
 800432c:	f7ff ffd4 	bl	80042d8 <HAL_ADC_ConvCpltCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
      
      /* Clear regular group conversion flag */
      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
 8004330:	f06f 0212 	mvn.w	r2, #18
 8004334:	6823      	ldr	r3, [r4, #0]
 8004336:	601a      	str	r2, [r3, #0]
    }
  }
  
  /* ========== Check End of Conversion flag for injected group ========== */
  if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC))
 8004338:	6823      	ldr	r3, [r4, #0]
 800433a:	685a      	ldr	r2, [r3, #4]
 800433c:	0610      	lsls	r0, r2, #24
 800433e:	d530      	bpl.n	80043a2 <HAL_ADC_IRQHandler+0xc6>
  {
    if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC))
 8004340:	681a      	ldr	r2, [r3, #0]
 8004342:	0751      	lsls	r1, r2, #29
 8004344:	d52d      	bpl.n	80043a2 <HAL_ADC_IRQHandler+0xc6>
    {
      /* Update state machine on conversion status if not in error state */
      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
 8004346:	6aa2      	ldr	r2, [r4, #40]	; 0x28
 8004348:	06d2      	lsls	r2, r2, #27
      {
        /* Set ADC state */
        SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
 800434a:	bf5e      	ittt	pl
 800434c:	6aa2      	ldrpl	r2, [r4, #40]	; 0x28
 800434e:	f442 5200 	orrpl.w	r2, r2, #8192	; 0x2000
 8004352:	62a2      	strpl	r2, [r4, #40]	; 0x28
      /* conversion from group regular (same conditions as group regular      */
      /* interruption disabling above).                                       */
      /* Note: On STM32F1 devices, in case of sequencer enabled               */
      /*       (several ranks selected), end of conversion flag is raised     */
      /*       at the end of the sequence.                                    */
      if(ADC_IS_SOFTWARE_START_INJECTED(hadc)                     || 
 8004354:	689a      	ldr	r2, [r3, #8]
 8004356:	f402 42e0 	and.w	r2, r2, #28672	; 0x7000
 800435a:	f5b2 4fe0 	cmp.w	r2, #28672	; 0x7000
 800435e:	d00a      	beq.n	8004376 <HAL_ADC_IRQHandler+0x9a>
         (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&     
 8004360:	685a      	ldr	r2, [r3, #4]
      if(ADC_IS_SOFTWARE_START_INJECTED(hadc)                     || 
 8004362:	0550      	lsls	r0, r2, #21
 8004364:	d416      	bmi.n	8004394 <HAL_ADC_IRQHandler+0xb8>
         (ADC_IS_SOFTWARE_START_REGULAR(hadc)        &&
 8004366:	689a      	ldr	r2, [r3, #8]
 8004368:	f402 2260 	and.w	r2, r2, #917504	; 0xe0000
         (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&     
 800436c:	f5b2 2f60 	cmp.w	r2, #917504	; 0xe0000
 8004370:	d110      	bne.n	8004394 <HAL_ADC_IRQHandler+0xb8>
         (ADC_IS_SOFTWARE_START_REGULAR(hadc)        &&
 8004372:	7b22      	ldrb	r2, [r4, #12]
 8004374:	b972      	cbnz	r2, 8004394 <HAL_ADC_IRQHandler+0xb8>
          (hadc->Init.ContinuousConvMode == DISABLE)   )        )   )
      {
        /* Disable ADC end of conversion interrupt on group injected */
        __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
 8004376:	685a      	ldr	r2, [r3, #4]
 8004378:	f022 0280 	bic.w	r2, r2, #128	; 0x80
 800437c:	605a      	str	r2, [r3, #4]
        
        /* Set ADC state */
        CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);   
 800437e:	6aa3      	ldr	r3, [r4, #40]	; 0x28
 8004380:	f423 5380 	bic.w	r3, r3, #4096	; 0x1000
 8004384:	62a3      	str	r3, [r4, #40]	; 0x28

        if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
 8004386:	6aa3      	ldr	r3, [r4, #40]	; 0x28
 8004388:	05d9      	lsls	r1, r3, #23
        { 
          SET_BIT(hadc->State, HAL_ADC_STATE_READY);
 800438a:	bf5e      	ittt	pl
 800438c:	6aa3      	ldrpl	r3, [r4, #40]	; 0x28
 800438e:	f043 0301 	orrpl.w	r3, r3, #1
 8004392:	62a3      	strpl	r3, [r4, #40]	; 0x28

      /* Conversion complete callback */ 
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
      hadc->InjectedConvCpltCallback(hadc);
#else
      HAL_ADCEx_InjectedConvCpltCallback(hadc);
 8004394:	4620      	mov	r0, r4
 8004396:	f000 f947 	bl	8004628 <HAL_ADCEx_InjectedConvCpltCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
      
      /* Clear injected group conversion flag */
      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC));
 800439a:	f06f 020c 	mvn.w	r2, #12
 800439e:	6823      	ldr	r3, [r4, #0]
 80043a0:	601a      	str	r2, [r3, #0]
    }
  }
   
  /* ========== Check Analog watchdog flags ========== */
  if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD))
 80043a2:	6823      	ldr	r3, [r4, #0]
 80043a4:	685a      	ldr	r2, [r3, #4]
 80043a6:	0652      	lsls	r2, r2, #25
 80043a8:	d50d      	bpl.n	80043c6 <HAL_ADC_IRQHandler+0xea>
  {
    if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD))
 80043aa:	681b      	ldr	r3, [r3, #0]
 80043ac:	07db      	lsls	r3, r3, #31
 80043ae:	d50a      	bpl.n	80043c6 <HAL_ADC_IRQHandler+0xea>
    {
      /* Set ADC state */
      SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
 80043b0:	6aa3      	ldr	r3, [r4, #40]	; 0x28
      
      /* Level out of window callback */ 
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
      hadc->LevelOutOfWindowCallback(hadc);
#else
      HAL_ADC_LevelOutOfWindowCallback(hadc);
 80043b2:	4620      	mov	r0, r4
      SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
 80043b4:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
 80043b8:	62a3      	str	r3, [r4, #40]	; 0x28
      HAL_ADC_LevelOutOfWindowCallback(hadc);
 80043ba:	f7ff ff8e 	bl	80042da <HAL_ADC_LevelOutOfWindowCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
      
      /* Clear the ADC analog watchdog flag */
      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
 80043be:	f06f 0201 	mvn.w	r2, #1
 80043c2:	6823      	ldr	r3, [r4, #0]
 80043c4:	601a      	str	r2, [r3, #0]
 80043c6:	bd10      	pop	{r4, pc}

080043c8 <HAL_ADC_ConfigChannel>:
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
{ 
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
  __IO uint32_t wait_loop_index = 0U;
 80043c8:	2300      	movs	r3, #0
{ 
 80043ca:	b573      	push	{r0, r1, r4, r5, r6, lr}
  __IO uint32_t wait_loop_index = 0U;
 80043cc:	9301      	str	r3, [sp, #4]
  assert_param(IS_ADC_CHANNEL(sConfig->Channel));
  assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
  assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
  
  /* Process locked */
  __HAL_LOCK(hadc);
 80043ce:	f890 3024 	ldrb.w	r3, [r0, #36]	; 0x24
 80043d2:	2b01      	cmp	r3, #1
 80043d4:	d074      	beq.n	80044c0 <HAL_ADC_ConfigChannel+0xf8>
 80043d6:	2301      	movs	r3, #1
  
  
  /* Regular sequence configuration */
  /* For Rank 1 to 6 */
  if (sConfig->Rank < 7U)
 80043d8:	684d      	ldr	r5, [r1, #4]
  __HAL_LOCK(hadc);
 80043da:	f880 3024 	strb.w	r3, [r0, #36]	; 0x24
  if (sConfig->Rank < 7U)
 80043de:	2d06      	cmp	r5, #6
 80043e0:	6802      	ldr	r2, [r0, #0]
 80043e2:	ea4f 0385 	mov.w	r3, r5, lsl #2
 80043e6:	680c      	ldr	r4, [r1, #0]
 80043e8:	d825      	bhi.n	8004436 <HAL_ADC_ConfigChannel+0x6e>
  {
    MODIFY_REG(hadc->Instance->SQR3                        ,
 80043ea:	442b      	add	r3, r5
 80043ec:	251f      	movs	r5, #31
 80043ee:	6b56      	ldr	r6, [r2, #52]	; 0x34
 80043f0:	3b05      	subs	r3, #5
 80043f2:	409d      	lsls	r5, r3
 80043f4:	ea26 0505 	bic.w	r5, r6, r5
 80043f8:	fa04 f303 	lsl.w	r3, r4, r3
 80043fc:	432b      	orrs	r3, r5
 80043fe:	6353      	str	r3, [r2, #52]	; 0x34
  }
  
  
  /* Channel sampling time configuration */
  /* For channels 10 to 17 */
  if (sConfig->Channel >= ADC_CHANNEL_10)
 8004400:	2c09      	cmp	r4, #9
 8004402:	ea4f 0344 	mov.w	r3, r4, lsl #1
 8004406:	688d      	ldr	r5, [r1, #8]
 8004408:	d92f      	bls.n	800446a <HAL_ADC_ConfigChannel+0xa2>
  {
    MODIFY_REG(hadc->Instance->SMPR1                             ,
 800440a:	2607      	movs	r6, #7
 800440c:	4423      	add	r3, r4
 800440e:	68d1      	ldr	r1, [r2, #12]
 8004410:	3b1e      	subs	r3, #30
 8004412:	409e      	lsls	r6, r3
 8004414:	ea21 0106 	bic.w	r1, r1, r6
 8004418:	fa05 f303 	lsl.w	r3, r5, r3
 800441c:	430b      	orrs	r3, r1
 800441e:	60d3      	str	r3, [r2, #12]
               ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
  }
  
  /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor  */
  /* and VREFINT measurement path.                                            */
  if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
 8004420:	f1a4 0310 	sub.w	r3, r4, #16
 8004424:	2b01      	cmp	r3, #1
 8004426:	d92b      	bls.n	8004480 <HAL_ADC_ConfigChannel+0xb8>
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
 8004428:	2300      	movs	r3, #0
      tmp_hal_status = HAL_ERROR;
    }
  }
  
  /* Process unlocked */
  __HAL_UNLOCK(hadc);
 800442a:	2200      	movs	r2, #0
 800442c:	f880 2024 	strb.w	r2, [r0, #36]	; 0x24
  
  /* Return function status */
  return tmp_hal_status;
}
 8004430:	4618      	mov	r0, r3
 8004432:	b002      	add	sp, #8
 8004434:	bd70      	pop	{r4, r5, r6, pc}
  else if (sConfig->Rank < 13U)
 8004436:	2d0c      	cmp	r5, #12
 8004438:	d80b      	bhi.n	8004452 <HAL_ADC_ConfigChannel+0x8a>
    MODIFY_REG(hadc->Instance->SQR2                        ,
 800443a:	442b      	add	r3, r5
 800443c:	251f      	movs	r5, #31
 800443e:	6b16      	ldr	r6, [r2, #48]	; 0x30
 8004440:	3b23      	subs	r3, #35	; 0x23
 8004442:	409d      	lsls	r5, r3
 8004444:	ea26 0505 	bic.w	r5, r6, r5
 8004448:	fa04 f303 	lsl.w	r3, r4, r3
 800444c:	432b      	orrs	r3, r5
 800444e:	6313      	str	r3, [r2, #48]	; 0x30
 8004450:	e7d6      	b.n	8004400 <HAL_ADC_ConfigChannel+0x38>
    MODIFY_REG(hadc->Instance->SQR1                        ,
 8004452:	442b      	add	r3, r5
 8004454:	251f      	movs	r5, #31
 8004456:	6ad6      	ldr	r6, [r2, #44]	; 0x2c
 8004458:	3b41      	subs	r3, #65	; 0x41
 800445a:	409d      	lsls	r5, r3
 800445c:	ea26 0505 	bic.w	r5, r6, r5
 8004460:	fa04 f303 	lsl.w	r3, r4, r3
 8004464:	432b      	orrs	r3, r5
 8004466:	62d3      	str	r3, [r2, #44]	; 0x2c
 8004468:	e7ca      	b.n	8004400 <HAL_ADC_ConfigChannel+0x38>
    MODIFY_REG(hadc->Instance->SMPR2                             ,
 800446a:	2607      	movs	r6, #7
 800446c:	6911      	ldr	r1, [r2, #16]
 800446e:	4423      	add	r3, r4
 8004470:	409e      	lsls	r6, r3
 8004472:	ea21 0106 	bic.w	r1, r1, r6
 8004476:	fa05 f303 	lsl.w	r3, r5, r3
 800447a:	430b      	orrs	r3, r1
 800447c:	6113      	str	r3, [r2, #16]
 800447e:	e7cf      	b.n	8004420 <HAL_ADC_ConfigChannel+0x58>
    if (hadc->Instance == ADC1)
 8004480:	4b10      	ldr	r3, [pc, #64]	; (80044c4 <HAL_ADC_ConfigChannel+0xfc>)
 8004482:	429a      	cmp	r2, r3
 8004484:	d116      	bne.n	80044b4 <HAL_ADC_ConfigChannel+0xec>
      if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET)
 8004486:	6893      	ldr	r3, [r2, #8]
 8004488:	021b      	lsls	r3, r3, #8
 800448a:	d4cd      	bmi.n	8004428 <HAL_ADC_ConfigChannel+0x60>
        SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
 800448c:	6893      	ldr	r3, [r2, #8]
        if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
 800448e:	2c10      	cmp	r4, #16
        SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
 8004490:	f443 0300 	orr.w	r3, r3, #8388608	; 0x800000
 8004494:	6093      	str	r3, [r2, #8]
        if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
 8004496:	d1c7      	bne.n	8004428 <HAL_ADC_ConfigChannel+0x60>
          wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
 8004498:	4b0b      	ldr	r3, [pc, #44]	; (80044c8 <HAL_ADC_ConfigChannel+0x100>)
 800449a:	4a0c      	ldr	r2, [pc, #48]	; (80044cc <HAL_ADC_ConfigChannel+0x104>)
 800449c:	681b      	ldr	r3, [r3, #0]
 800449e:	fbb3 f2f2 	udiv	r2, r3, r2
 80044a2:	230a      	movs	r3, #10
 80044a4:	4353      	muls	r3, r2
            wait_loop_index--;
 80044a6:	9301      	str	r3, [sp, #4]
          while(wait_loop_index != 0U)
 80044a8:	9b01      	ldr	r3, [sp, #4]
 80044aa:	2b00      	cmp	r3, #0
 80044ac:	d0bc      	beq.n	8004428 <HAL_ADC_ConfigChannel+0x60>
            wait_loop_index--;
 80044ae:	9b01      	ldr	r3, [sp, #4]
 80044b0:	3b01      	subs	r3, #1
 80044b2:	e7f8      	b.n	80044a6 <HAL_ADC_ConfigChannel+0xde>
      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
 80044b4:	6a83      	ldr	r3, [r0, #40]	; 0x28
 80044b6:	f043 0320 	orr.w	r3, r3, #32
 80044ba:	6283      	str	r3, [r0, #40]	; 0x28
      tmp_hal_status = HAL_ERROR;
 80044bc:	2301      	movs	r3, #1
 80044be:	e7b4      	b.n	800442a <HAL_ADC_ConfigChannel+0x62>
  __HAL_LOCK(hadc);
 80044c0:	2302      	movs	r3, #2
 80044c2:	e7b5      	b.n	8004430 <HAL_ADC_ConfigChannel+0x68>
 80044c4:	40012400 	.word	0x40012400
 80044c8:	20000208 	.word	0x20000208
 80044cc:	000f4240 	.word	0x000f4240

080044d0 <ADC_ConversionStop_Disable>:
  *         stopped to disable the ADC.
  * @param  hadc: ADC handle
  * @retval HAL status.
  */
HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc)
{
 80044d0:	b538      	push	{r3, r4, r5, lr}
  uint32_t tickstart = 0U;
  
  /* Verification if ADC is not already disabled */
  if (ADC_IS_ENABLE(hadc) != RESET)
 80044d2:	6803      	ldr	r3, [r0, #0]
{
 80044d4:	4604      	mov	r4, r0
  if (ADC_IS_ENABLE(hadc) != RESET)
 80044d6:	689a      	ldr	r2, [r3, #8]
 80044d8:	07d2      	lsls	r2, r2, #31
 80044da:	d401      	bmi.n	80044e0 <ADC_ConversionStop_Disable+0x10>
      }
    }
  }
  
  /* Return HAL status */
  return HAL_OK;
 80044dc:	2000      	movs	r0, #0
 80044de:	bd38      	pop	{r3, r4, r5, pc}
    __HAL_ADC_DISABLE(hadc);
 80044e0:	689a      	ldr	r2, [r3, #8]
 80044e2:	f022 0201 	bic.w	r2, r2, #1
 80044e6:	609a      	str	r2, [r3, #8]
    tickstart = HAL_GetTick();
 80044e8:	f7ff fede 	bl	80042a8 <HAL_GetTick>
 80044ec:	4605      	mov	r5, r0
    while(ADC_IS_ENABLE(hadc) != RESET)
 80044ee:	6823      	ldr	r3, [r4, #0]
 80044f0:	689b      	ldr	r3, [r3, #8]
 80044f2:	07db      	lsls	r3, r3, #31
 80044f4:	d5f2      	bpl.n	80044dc <ADC_ConversionStop_Disable+0xc>
      if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
 80044f6:	f7ff fed7 	bl	80042a8 <HAL_GetTick>
 80044fa:	1b40      	subs	r0, r0, r5
 80044fc:	2802      	cmp	r0, #2
 80044fe:	d9f6      	bls.n	80044ee <ADC_ConversionStop_Disable+0x1e>
        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
 8004500:	6aa3      	ldr	r3, [r4, #40]	; 0x28
        SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
 8004502:	2001      	movs	r0, #1
        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
 8004504:	f043 0310 	orr.w	r3, r3, #16
 8004508:	62a3      	str	r3, [r4, #40]	; 0x28
        SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
 800450a:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
 800450c:	f043 0301 	orr.w	r3, r3, #1
 8004510:	62e3      	str	r3, [r4, #44]	; 0x2c
 8004512:	bd38      	pop	{r3, r4, r5, pc}

08004514 <HAL_ADC_Init>:
{
 8004514:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
  if(hadc == NULL)
 8004516:	4604      	mov	r4, r0
 8004518:	2800      	cmp	r0, #0
 800451a:	d077      	beq.n	800460c <HAL_ADC_Init+0xf8>
  if (hadc->State == HAL_ADC_STATE_RESET)
 800451c:	6a83      	ldr	r3, [r0, #40]	; 0x28
 800451e:	b923      	cbnz	r3, 800452a <HAL_ADC_Init+0x16>
    ADC_CLEAR_ERRORCODE(hadc);
 8004520:	62c3      	str	r3, [r0, #44]	; 0x2c
    hadc->Lock = HAL_UNLOCKED;
 8004522:	f880 3024 	strb.w	r3, [r0, #36]	; 0x24
    HAL_ADC_MspInit(hadc);
 8004526:	f001 fd83 	bl	8006030 <HAL_ADC_MspInit>
  tmp_hal_status = ADC_ConversionStop_Disable(hadc);
 800452a:	4620      	mov	r0, r4
 800452c:	f7ff ffd0 	bl	80044d0 <ADC_ConversionStop_Disable>
  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
 8004530:	6aa3      	ldr	r3, [r4, #40]	; 0x28
 8004532:	f013 0310 	ands.w	r3, r3, #16
 8004536:	d16b      	bne.n	8004610 <HAL_ADC_Init+0xfc>
 8004538:	2800      	cmp	r0, #0
 800453a:	d169      	bne.n	8004610 <HAL_ADC_Init+0xfc>
    ADC_STATE_CLR_SET(hadc->State,
 800453c:	6aa2      	ldr	r2, [r4, #40]	; 0x28
                ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv)            |
 800453e:	4937      	ldr	r1, [pc, #220]	; (800461c <HAL_ADC_Init+0x108>)
    ADC_STATE_CLR_SET(hadc->State,
 8004540:	f422 5288 	bic.w	r2, r2, #4352	; 0x1100
 8004544:	f022 0202 	bic.w	r2, r2, #2
 8004548:	f042 0202 	orr.w	r2, r2, #2
 800454c:	62a2      	str	r2, [r4, #40]	; 0x28
                ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv)            |
 800454e:	e894 0024 	ldmia.w	r4, {r2, r5}
 8004552:	428a      	cmp	r2, r1
 8004554:	69e1      	ldr	r1, [r4, #28]
 8004556:	d104      	bne.n	8004562 <HAL_ADC_Init+0x4e>
 8004558:	f5b1 2f40 	cmp.w	r1, #786432	; 0xc0000
 800455c:	bf08      	it	eq
 800455e:	f44f 2100 	moveq.w	r1, #524288	; 0x80000
                ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode)   );
 8004562:	7b26      	ldrb	r6, [r4, #12]
                ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv)            |
 8004564:	ea45 0546 	orr.w	r5, r5, r6, lsl #1
 8004568:	4329      	orrs	r1, r5
    tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode));
 800456a:	68a5      	ldr	r5, [r4, #8]
 800456c:	f5b5 7f80 	cmp.w	r5, #256	; 0x100
 8004570:	d035      	beq.n	80045de <HAL_ADC_Init+0xca>
 8004572:	2d01      	cmp	r5, #1
 8004574:	bf08      	it	eq
 8004576:	f44f 7380 	moveq.w	r3, #256	; 0x100
    if (hadc->Init.DiscontinuousConvMode == ENABLE)
 800457a:	7d27      	ldrb	r7, [r4, #20]
 800457c:	2f01      	cmp	r7, #1
 800457e:	d106      	bne.n	800458e <HAL_ADC_Init+0x7a>
      if (hadc->Init.ContinuousConvMode == DISABLE)
 8004580:	bb7e      	cbnz	r6, 80045e2 <HAL_ADC_Init+0xce>
        SET_BIT(tmp_cr1, ADC_CR1_DISCEN                                            |
 8004582:	69a6      	ldr	r6, [r4, #24]
 8004584:	3e01      	subs	r6, #1
 8004586:	ea43 3346 	orr.w	r3, r3, r6, lsl #13
 800458a:	f443 6300 	orr.w	r3, r3, #2048	; 0x800
      MODIFY_REG(hadc->Instance->CR1,
 800458e:	6856      	ldr	r6, [r2, #4]
    if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE)
 8004590:	f5b5 7f80 	cmp.w	r5, #256	; 0x100
      MODIFY_REG(hadc->Instance->CR1,
 8004594:	f426 4669 	bic.w	r6, r6, #59648	; 0xe900
 8004598:	ea43 0306 	orr.w	r3, r3, r6
 800459c:	6053      	str	r3, [r2, #4]
      MODIFY_REG(hadc->Instance->CR2,
 800459e:	6896      	ldr	r6, [r2, #8]
 80045a0:	4b1f      	ldr	r3, [pc, #124]	; (8004620 <HAL_ADC_Init+0x10c>)
 80045a2:	ea03 0306 	and.w	r3, r3, r6
 80045a6:	ea43 0301 	orr.w	r3, r3, r1
 80045aa:	6093      	str	r3, [r2, #8]
    if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE)
 80045ac:	d001      	beq.n	80045b2 <HAL_ADC_Init+0x9e>
 80045ae:	2d01      	cmp	r5, #1
 80045b0:	d120      	bne.n	80045f4 <HAL_ADC_Init+0xe0>
      tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion);
 80045b2:	6923      	ldr	r3, [r4, #16]
 80045b4:	3b01      	subs	r3, #1
 80045b6:	051b      	lsls	r3, r3, #20
    MODIFY_REG(hadc->Instance->SQR1,
 80045b8:	6ad5      	ldr	r5, [r2, #44]	; 0x2c
 80045ba:	f425 0570 	bic.w	r5, r5, #15728640	; 0xf00000
 80045be:	432b      	orrs	r3, r5
 80045c0:	62d3      	str	r3, [r2, #44]	; 0x2c
    if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
 80045c2:	6892      	ldr	r2, [r2, #8]
 80045c4:	4b17      	ldr	r3, [pc, #92]	; (8004624 <HAL_ADC_Init+0x110>)
 80045c6:	4013      	ands	r3, r2
 80045c8:	4299      	cmp	r1, r3
 80045ca:	d115      	bne.n	80045f8 <HAL_ADC_Init+0xe4>
      ADC_CLEAR_ERRORCODE(hadc);
 80045cc:	2300      	movs	r3, #0
 80045ce:	62e3      	str	r3, [r4, #44]	; 0x2c
      ADC_STATE_CLR_SET(hadc->State,
 80045d0:	6aa3      	ldr	r3, [r4, #40]	; 0x28
 80045d2:	f023 0303 	bic.w	r3, r3, #3
 80045d6:	f043 0301 	orr.w	r3, r3, #1
 80045da:	62a3      	str	r3, [r4, #40]	; 0x28
 80045dc:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode));
 80045de:	462b      	mov	r3, r5
 80045e0:	e7cb      	b.n	800457a <HAL_ADC_Init+0x66>
        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
 80045e2:	6aa6      	ldr	r6, [r4, #40]	; 0x28
 80045e4:	f046 0620 	orr.w	r6, r6, #32
 80045e8:	62a6      	str	r6, [r4, #40]	; 0x28
        SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
 80045ea:	6ae6      	ldr	r6, [r4, #44]	; 0x2c
 80045ec:	f046 0601 	orr.w	r6, r6, #1
 80045f0:	62e6      	str	r6, [r4, #44]	; 0x2c
 80045f2:	e7cc      	b.n	800458e <HAL_ADC_Init+0x7a>
  uint32_t tmp_sqr1 = 0U;
 80045f4:	2300      	movs	r3, #0
 80045f6:	e7df      	b.n	80045b8 <HAL_ADC_Init+0xa4>
      ADC_STATE_CLR_SET(hadc->State,
 80045f8:	6aa3      	ldr	r3, [r4, #40]	; 0x28
 80045fa:	f023 0312 	bic.w	r3, r3, #18
 80045fe:	f043 0310 	orr.w	r3, r3, #16
 8004602:	62a3      	str	r3, [r4, #40]	; 0x28
      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
 8004604:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
 8004606:	f043 0301 	orr.w	r3, r3, #1
 800460a:	62e3      	str	r3, [r4, #44]	; 0x2c
    return HAL_ERROR;
 800460c:	2001      	movs	r0, #1
}
 800460e:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
 8004610:	6aa3      	ldr	r3, [r4, #40]	; 0x28
 8004612:	f043 0310 	orr.w	r3, r3, #16
 8004616:	62a3      	str	r3, [r4, #40]	; 0x28
 8004618:	e7f8      	b.n	800460c <HAL_ADC_Init+0xf8>
 800461a:	bf00      	nop
 800461c:	40013c00 	.word	0x40013c00
 8004620:	ffe1f7fd 	.word	0xffe1f7fd
 8004624:	ff1f0efe 	.word	0xff1f0efe

08004628 <HAL_ADCEx_InjectedConvCpltCallback>:
  * @brief  Injected conversion complete callback in non blocking mode 
  * @param  hadc: ADC handle
  * @retval None
  */
__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
{
 8004628:	4770      	bx	lr
	...

0800462c <HAL_NVIC_SetPriorityGrouping>:
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
  uint32_t reg_value;
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */

  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
 800462c:	4a07      	ldr	r2, [pc, #28]	; (800464c <HAL_NVIC_SetPriorityGrouping+0x20>)
  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
  reg_value  =  (reg_value                                   |
                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) );               /* Insert write key and priority group */
 800462e:	0200      	lsls	r0, r0, #8
  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
 8004630:	68d3      	ldr	r3, [r2, #12]
                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) );               /* Insert write key and priority group */
 8004632:	f400 60e0 	and.w	r0, r0, #1792	; 0x700
  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
 8004636:	f423 63e0 	bic.w	r3, r3, #1792	; 0x700
 800463a:	041b      	lsls	r3, r3, #16
 800463c:	0c1b      	lsrs	r3, r3, #16
 800463e:	f043 63bf 	orr.w	r3, r3, #100139008	; 0x5f80000
 8004642:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
  reg_value  =  (reg_value                                   |
 8004646:	4303      	orrs	r3, r0
  SCB->AIRCR =  reg_value;
 8004648:	60d3      	str	r3, [r2, #12]
 800464a:	4770      	bx	lr
 800464c:	e000ed00 	.word	0xe000ed00

08004650 <HAL_NVIC_SetPriority>:
  \details Reads the priority grouping field from the NVIC Interrupt Controller.
  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
 */
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
 8004650:	4b17      	ldr	r3, [pc, #92]	; (80046b0 <HAL_NVIC_SetPriority+0x60>)
  *         This parameter can be a value between 0 and 15
  *         A lower priority value indicates a higher priority.          
  * @retval None
  */
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{ 
 8004652:	b530      	push	{r4, r5, lr}
 8004654:	68dc      	ldr	r4, [r3, #12]
 8004656:	f3c4 2402 	ubfx	r4, r4, #8, #3
{
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
  uint32_t PreemptPriorityBits;
  uint32_t SubPriorityBits;

  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
 800465a:	f1c4 0307 	rsb	r3, r4, #7
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 800465e:	1d25      	adds	r5, r4, #4
  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
 8004660:	2b04      	cmp	r3, #4
 8004662:	bf28      	it	cs
 8004664:	2304      	movcs	r3, #4
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 8004666:	2d06      	cmp	r5, #6

  return (
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 8004668:	f04f 0501 	mov.w	r5, #1
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 800466c:	bf98      	it	ls
 800466e:	2400      	movls	r4, #0
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 8004670:	fa05 f303 	lsl.w	r3, r5, r3
 8004674:	f103 33ff 	add.w	r3, r3, #4294967295
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 8004678:	bf88      	it	hi
 800467a:	3c03      	subhi	r4, #3
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 800467c:	4019      	ands	r1, r3
 800467e:	40a1      	lsls	r1, r4
           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
 8004680:	fa05 f404 	lsl.w	r4, r5, r4
 8004684:	3c01      	subs	r4, #1
 8004686:	4022      	ands	r2, r4
  if ((int32_t)(IRQn) >= 0)
 8004688:	2800      	cmp	r0, #0
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 800468a:	ea42 0201 	orr.w	r2, r2, r1
 800468e:	ea4f 1202 	mov.w	r2, r2, lsl #4
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8004692:	bfa9      	itett	ge
 8004694:	f100 4060 	addge.w	r0, r0, #3758096384	; 0xe0000000
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8004698:	4b06      	ldrlt	r3, [pc, #24]	; (80046b4 <HAL_NVIC_SetPriority+0x64>)
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 800469a:	b2d2      	uxtbge	r2, r2
 800469c:	f500 4061 	addge.w	r0, r0, #57600	; 0xe100
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 80046a0:	bfbb      	ittet	lt
 80046a2:	f000 000f 	andlt.w	r0, r0, #15
 80046a6:	b2d2      	uxtblt	r2, r2
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 80046a8:	f880 2300 	strbge.w	r2, [r0, #768]	; 0x300
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 80046ac:	541a      	strblt	r2, [r3, r0]
 80046ae:	bd30      	pop	{r4, r5, pc}
 80046b0:	e000ed00 	.word	0xe000ed00
 80046b4:	e000ed14 	.word	0xe000ed14

080046b8 <HAL_NVIC_EnableIRQ>:
  if ((int32_t)(IRQn) >= 0)
 80046b8:	2800      	cmp	r0, #0
 80046ba:	db08      	blt.n	80046ce <HAL_NVIC_EnableIRQ+0x16>
    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
 80046bc:	2301      	movs	r3, #1
 80046be:	0942      	lsrs	r2, r0, #5
 80046c0:	f000 001f 	and.w	r0, r0, #31
 80046c4:	fa03 f000 	lsl.w	r0, r3, r0
 80046c8:	4b01      	ldr	r3, [pc, #4]	; (80046d0 <HAL_NVIC_EnableIRQ+0x18>)
 80046ca:	f843 0022 	str.w	r0, [r3, r2, lsl #2]
 80046ce:	4770      	bx	lr
 80046d0:	e000e100 	.word	0xe000e100

080046d4 <HAL_SYSTICK_Config>:
           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
           must contain a vendor-specific implementation of this function.
 */
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
 80046d4:	3801      	subs	r0, #1
 80046d6:	f1b0 7f80 	cmp.w	r0, #16777216	; 0x1000000
 80046da:	d20a      	bcs.n	80046f2 <HAL_SYSTICK_Config+0x1e>
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 80046dc:	21f0      	movs	r1, #240	; 0xf0
  {
    return (1UL);                                                   /* Reload value impossible */
  }

  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
 80046de:	4b06      	ldr	r3, [pc, #24]	; (80046f8 <HAL_SYSTICK_Config+0x24>)
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 80046e0:	4a06      	ldr	r2, [pc, #24]	; (80046fc <HAL_SYSTICK_Config+0x28>)
  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
 80046e2:	6058      	str	r0, [r3, #4]
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 80046e4:	f882 1023 	strb.w	r1, [r2, #35]	; 0x23
  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
 80046e8:	2000      	movs	r0, #0
  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
 80046ea:	2207      	movs	r2, #7
  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
 80046ec:	6098      	str	r0, [r3, #8]
  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
 80046ee:	601a      	str	r2, [r3, #0]
 80046f0:	4770      	bx	lr
    return (1UL);                                                   /* Reload value impossible */
 80046f2:	2001      	movs	r0, #1
  *                  - 1  Function failed.
  */
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
   return SysTick_Config(TicksNumb);
}
 80046f4:	4770      	bx	lr
 80046f6:	bf00      	nop
 80046f8:	e000e010 	.word	0xe000e010
 80046fc:	e000ed00 	.word	0xe000ed00

08004700 <HAL_DMA_Init>:
  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
  *               the configuration information for the specified DMA Channel.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
{
 8004700:	b510      	push	{r4, lr}
  uint32_t tmp = 0U;

  /* Check the DMA handle allocation */
  if(hdma == NULL)
 8004702:	2800      	cmp	r0, #0
 8004704:	d032      	beq.n	800476c <HAL_DMA_Init+0x6c>
  assert_param(IS_DMA_MODE(hdma->Init.Mode));
  assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));

#if defined (DMA2)
  /* calculation of the channel index */
  if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
 8004706:	6801      	ldr	r1, [r0, #0]
 8004708:	4b19      	ldr	r3, [pc, #100]	; (8004770 <HAL_DMA_Init+0x70>)
 800470a:	2414      	movs	r4, #20
 800470c:	4299      	cmp	r1, r3
 800470e:	d825      	bhi.n	800475c <HAL_DMA_Init+0x5c>
  {
    /* DMA1 */
    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
 8004710:	4a18      	ldr	r2, [pc, #96]	; (8004774 <HAL_DMA_Init+0x74>)
    hdma->DmaBaseAddress = DMA1;
 8004712:	f2a3 4307 	subw	r3, r3, #1031	; 0x407
    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
 8004716:	440a      	add	r2, r1
 8004718:	fbb2 f2f4 	udiv	r2, r2, r4
 800471c:	0092      	lsls	r2, r2, #2
 800471e:	6402      	str	r2, [r0, #64]	; 0x40
  tmp &= ((uint32_t)~(DMA_CCR_PL    | DMA_CCR_MSIZE  | DMA_CCR_PSIZE  | \
                      DMA_CCR_MINC  | DMA_CCR_PINC   | DMA_CCR_CIRC   | \
                      DMA_CCR_DIR));

  /* Prepare the DMA Channel configuration */
  tmp |=  hdma->Init.Direction        |
 8004720:	6884      	ldr	r4, [r0, #8]
    hdma->DmaBaseAddress = DMA2;
 8004722:	63c3      	str	r3, [r0, #60]	; 0x3c
  tmp |=  hdma->Init.Direction        |
 8004724:	6843      	ldr	r3, [r0, #4]
  tmp = hdma->Instance->CCR;
 8004726:	680a      	ldr	r2, [r1, #0]
  tmp |=  hdma->Init.Direction        |
 8004728:	4323      	orrs	r3, r4
          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
 800472a:	68c4      	ldr	r4, [r0, #12]
  tmp &= ((uint32_t)~(DMA_CCR_PL    | DMA_CCR_MSIZE  | DMA_CCR_PSIZE  | \
 800472c:	f422 527f 	bic.w	r2, r2, #16320	; 0x3fc0
          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
 8004730:	4323      	orrs	r3, r4
 8004732:	6904      	ldr	r4, [r0, #16]
  tmp &= ((uint32_t)~(DMA_CCR_PL    | DMA_CCR_MSIZE  | DMA_CCR_PSIZE  | \
 8004734:	f022 0230 	bic.w	r2, r2, #48	; 0x30
          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
 8004738:	4323      	orrs	r3, r4
          hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
 800473a:	6944      	ldr	r4, [r0, #20]
 800473c:	4323      	orrs	r3, r4
 800473e:	6984      	ldr	r4, [r0, #24]
 8004740:	4323      	orrs	r3, r4
          hdma->Init.Mode                | hdma->Init.Priority;
 8004742:	69c4      	ldr	r4, [r0, #28]
 8004744:	4323      	orrs	r3, r4
  tmp |=  hdma->Init.Direction        |
 8004746:	4313      	orrs	r3, r2

  /* Write to DMA Channel CR register */
  hdma->Instance->CCR = tmp;
 8004748:	600b      	str	r3, [r1, #0]

  /* Initialise the error code */
  hdma->ErrorCode = HAL_DMA_ERROR_NONE;

  /* Initialize the DMA state*/
  hdma->State = HAL_DMA_STATE_READY;
 800474a:	2201      	movs	r2, #1
  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
 800474c:	2300      	movs	r3, #0
  hdma->State = HAL_DMA_STATE_READY;
 800474e:	f880 2021 	strb.w	r2, [r0, #33]	; 0x21
  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
 8004752:	6383      	str	r3, [r0, #56]	; 0x38
  /* Allocate lock resource and initialize it */
  hdma->Lock = HAL_UNLOCKED;
 8004754:	f880 3020 	strb.w	r3, [r0, #32]

  return HAL_OK;
 8004758:	4618      	mov	r0, r3
 800475a:	bd10      	pop	{r4, pc}
    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
 800475c:	4b06      	ldr	r3, [pc, #24]	; (8004778 <HAL_DMA_Init+0x78>)
 800475e:	440b      	add	r3, r1
 8004760:	fbb3 f3f4 	udiv	r3, r3, r4
 8004764:	009b      	lsls	r3, r3, #2
 8004766:	6403      	str	r3, [r0, #64]	; 0x40
    hdma->DmaBaseAddress = DMA2;
 8004768:	4b04      	ldr	r3, [pc, #16]	; (800477c <HAL_DMA_Init+0x7c>)
 800476a:	e7d9      	b.n	8004720 <HAL_DMA_Init+0x20>
    return HAL_ERROR;
 800476c:	2001      	movs	r0, #1
}
 800476e:	bd10      	pop	{r4, pc}
 8004770:	40020407 	.word	0x40020407
 8004774:	bffdfff8 	.word	0xbffdfff8
 8004778:	bffdfbf8 	.word	0xbffdfbf8
 800477c:	40020400 	.word	0x40020400

08004780 <HAL_DMA_Start_IT>:
  * @param  DstAddress: The destination memory Buffer address
  * @param  DataLength: The length of data to be transferred from source to destination
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
 8004780:	b5f0      	push	{r4, r5, r6, r7, lr}

  /* Check the parameters */
  assert_param(IS_DMA_BUFFER_SIZE(DataLength));

  /* Process locked */
  __HAL_LOCK(hdma);
 8004782:	f890 4020 	ldrb.w	r4, [r0, #32]
 8004786:	2c01      	cmp	r4, #1
 8004788:	d035      	beq.n	80047f6 <HAL_DMA_Start_IT+0x76>
 800478a:	2401      	movs	r4, #1
  
  if(HAL_DMA_STATE_READY == hdma->State)
 800478c:	f890 5021 	ldrb.w	r5, [r0, #33]	; 0x21
  __HAL_LOCK(hdma);
 8004790:	f880 4020 	strb.w	r4, [r0, #32]
  if(HAL_DMA_STATE_READY == hdma->State)
 8004794:	42a5      	cmp	r5, r4
 8004796:	f04f 0600 	mov.w	r6, #0
 800479a:	f04f 0402 	mov.w	r4, #2
 800479e:	d128      	bne.n	80047f2 <HAL_DMA_Start_IT+0x72>
  {
    /* Change DMA peripheral state */
    hdma->State = HAL_DMA_STATE_BUSY;
 80047a0:	f880 4021 	strb.w	r4, [r0, #33]	; 0x21
    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
    
    /* Disable the peripheral */
    __HAL_DMA_DISABLE(hdma);
 80047a4:	6804      	ldr	r4, [r0, #0]
    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
 80047a6:	6386      	str	r6, [r0, #56]	; 0x38
    __HAL_DMA_DISABLE(hdma);
 80047a8:	6826      	ldr	r6, [r4, #0]
  * @retval HAL status
  */
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
  /* Clear all flags */
  hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
 80047aa:	6c07      	ldr	r7, [r0, #64]	; 0x40
    __HAL_DMA_DISABLE(hdma);
 80047ac:	f026 0601 	bic.w	r6, r6, #1
 80047b0:	6026      	str	r6, [r4, #0]
  hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
 80047b2:	6bc6      	ldr	r6, [r0, #60]	; 0x3c
 80047b4:	40bd      	lsls	r5, r7
 80047b6:	6075      	str	r5, [r6, #4]

  /* Configure DMA Channel data length */
  hdma->Instance->CNDTR = DataLength;
 80047b8:	6063      	str	r3, [r4, #4]

  /* Memory to Peripheral */
  if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
 80047ba:	6843      	ldr	r3, [r0, #4]
 80047bc:	6805      	ldr	r5, [r0, #0]
 80047be:	2b10      	cmp	r3, #16
    if(NULL != hdma->XferHalfCpltCallback)
 80047c0:	6ac3      	ldr	r3, [r0, #44]	; 0x2c
  {
    /* Configure DMA Channel destination address */
    hdma->Instance->CPAR = DstAddress;
 80047c2:	bf0b      	itete	eq
 80047c4:	60a2      	streq	r2, [r4, #8]
  }
  /* Peripheral to Memory */
  else
  {
    /* Configure DMA Channel source address */
    hdma->Instance->CPAR = SrcAddress;
 80047c6:	60a1      	strne	r1, [r4, #8]
    hdma->Instance->CMAR = SrcAddress;
 80047c8:	60e1      	streq	r1, [r4, #12]

    /* Configure DMA Channel destination address */
    hdma->Instance->CMAR = DstAddress;
 80047ca:	60e2      	strne	r2, [r4, #12]
    if(NULL != hdma->XferHalfCpltCallback)
 80047cc:	b14b      	cbz	r3, 80047e2 <HAL_DMA_Start_IT+0x62>
      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
 80047ce:	6823      	ldr	r3, [r4, #0]
 80047d0:	f043 030e 	orr.w	r3, r3, #14
      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
 80047d4:	6023      	str	r3, [r4, #0]
    __HAL_DMA_ENABLE(hdma);
 80047d6:	682b      	ldr	r3, [r5, #0]
  HAL_StatusTypeDef status = HAL_OK;
 80047d8:	2000      	movs	r0, #0
    __HAL_DMA_ENABLE(hdma);
 80047da:	f043 0301 	orr.w	r3, r3, #1
 80047de:	602b      	str	r3, [r5, #0]
 80047e0:	bdf0      	pop	{r4, r5, r6, r7, pc}
      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
 80047e2:	6823      	ldr	r3, [r4, #0]
 80047e4:	f023 0304 	bic.w	r3, r3, #4
 80047e8:	6023      	str	r3, [r4, #0]
      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
 80047ea:	6823      	ldr	r3, [r4, #0]
 80047ec:	f043 030a 	orr.w	r3, r3, #10
 80047f0:	e7f0      	b.n	80047d4 <HAL_DMA_Start_IT+0x54>
    __HAL_UNLOCK(hdma); 
 80047f2:	f880 6020 	strb.w	r6, [r0, #32]
  __HAL_LOCK(hdma);
 80047f6:	2002      	movs	r0, #2
}
 80047f8:	bdf0      	pop	{r4, r5, r6, r7, pc}
	...

080047fc <HAL_DMA_Abort_IT>:
  if(HAL_DMA_STATE_BUSY != hdma->State)
 80047fc:	f890 3021 	ldrb.w	r3, [r0, #33]	; 0x21
{  
 8004800:	b510      	push	{r4, lr}
  if(HAL_DMA_STATE_BUSY != hdma->State)
 8004802:	2b02      	cmp	r3, #2
 8004804:	d003      	beq.n	800480e <HAL_DMA_Abort_IT+0x12>
    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
 8004806:	2304      	movs	r3, #4
 8004808:	6383      	str	r3, [r0, #56]	; 0x38
    status = HAL_ERROR;
 800480a:	2001      	movs	r0, #1
 800480c:	bd10      	pop	{r4, pc}
    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
 800480e:	6803      	ldr	r3, [r0, #0]
 8004810:	681a      	ldr	r2, [r3, #0]
 8004812:	f022 020e 	bic.w	r2, r2, #14
 8004816:	601a      	str	r2, [r3, #0]
    __HAL_DMA_DISABLE(hdma);
 8004818:	681a      	ldr	r2, [r3, #0]
 800481a:	f022 0201 	bic.w	r2, r2, #1
 800481e:	601a      	str	r2, [r3, #0]
    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma));
 8004820:	4a29      	ldr	r2, [pc, #164]	; (80048c8 <HAL_DMA_Abort_IT+0xcc>)
 8004822:	4293      	cmp	r3, r2
 8004824:	d924      	bls.n	8004870 <HAL_DMA_Abort_IT+0x74>
 8004826:	f502 7262 	add.w	r2, r2, #904	; 0x388
 800482a:	4293      	cmp	r3, r2
 800482c:	d019      	beq.n	8004862 <HAL_DMA_Abort_IT+0x66>
 800482e:	3214      	adds	r2, #20
 8004830:	4293      	cmp	r3, r2
 8004832:	d018      	beq.n	8004866 <HAL_DMA_Abort_IT+0x6a>
 8004834:	3214      	adds	r2, #20
 8004836:	4293      	cmp	r3, r2
 8004838:	d017      	beq.n	800486a <HAL_DMA_Abort_IT+0x6e>
 800483a:	3214      	adds	r2, #20
 800483c:	4293      	cmp	r3, r2
 800483e:	bf0c      	ite	eq
 8004840:	f44f 5380 	moveq.w	r3, #4096	; 0x1000
 8004844:	f44f 3380 	movne.w	r3, #65536	; 0x10000
 8004848:	4a20      	ldr	r2, [pc, #128]	; (80048cc <HAL_DMA_Abort_IT+0xd0>)
 800484a:	6053      	str	r3, [r2, #4]
    hdma->State = HAL_DMA_STATE_READY;
 800484c:	2301      	movs	r3, #1
    __HAL_UNLOCK(hdma);
 800484e:	2400      	movs	r4, #0
    hdma->State = HAL_DMA_STATE_READY;
 8004850:	f880 3021 	strb.w	r3, [r0, #33]	; 0x21
    if(hdma->XferAbortCallback != NULL)
 8004854:	6b43      	ldr	r3, [r0, #52]	; 0x34
    __HAL_UNLOCK(hdma);
 8004856:	f880 4020 	strb.w	r4, [r0, #32]
    if(hdma->XferAbortCallback != NULL)
 800485a:	b39b      	cbz	r3, 80048c4 <HAL_DMA_Abort_IT+0xc8>
      hdma->XferAbortCallback(hdma);
 800485c:	4798      	blx	r3
  HAL_StatusTypeDef status = HAL_OK;
 800485e:	4620      	mov	r0, r4
 8004860:	bd10      	pop	{r4, pc}
    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma));
 8004862:	2301      	movs	r3, #1
 8004864:	e7f0      	b.n	8004848 <HAL_DMA_Abort_IT+0x4c>
 8004866:	2310      	movs	r3, #16
 8004868:	e7ee      	b.n	8004848 <HAL_DMA_Abort_IT+0x4c>
 800486a:	f44f 7380 	mov.w	r3, #256	; 0x100
 800486e:	e7eb      	b.n	8004848 <HAL_DMA_Abort_IT+0x4c>
 8004870:	4917      	ldr	r1, [pc, #92]	; (80048d0 <HAL_DMA_Abort_IT+0xd4>)
 8004872:	428b      	cmp	r3, r1
 8004874:	d016      	beq.n	80048a4 <HAL_DMA_Abort_IT+0xa8>
 8004876:	3114      	adds	r1, #20
 8004878:	428b      	cmp	r3, r1
 800487a:	d015      	beq.n	80048a8 <HAL_DMA_Abort_IT+0xac>
 800487c:	3114      	adds	r1, #20
 800487e:	428b      	cmp	r3, r1
 8004880:	d014      	beq.n	80048ac <HAL_DMA_Abort_IT+0xb0>
 8004882:	3114      	adds	r1, #20
 8004884:	428b      	cmp	r3, r1
 8004886:	d014      	beq.n	80048b2 <HAL_DMA_Abort_IT+0xb6>
 8004888:	3114      	adds	r1, #20
 800488a:	428b      	cmp	r3, r1
 800488c:	d014      	beq.n	80048b8 <HAL_DMA_Abort_IT+0xbc>
 800488e:	3114      	adds	r1, #20
 8004890:	428b      	cmp	r3, r1
 8004892:	d014      	beq.n	80048be <HAL_DMA_Abort_IT+0xc2>
 8004894:	4293      	cmp	r3, r2
 8004896:	bf14      	ite	ne
 8004898:	f44f 3380 	movne.w	r3, #65536	; 0x10000
 800489c:	f04f 7380 	moveq.w	r3, #16777216	; 0x1000000
 80048a0:	4a0c      	ldr	r2, [pc, #48]	; (80048d4 <HAL_DMA_Abort_IT+0xd8>)
 80048a2:	e7d2      	b.n	800484a <HAL_DMA_Abort_IT+0x4e>
 80048a4:	2301      	movs	r3, #1
 80048a6:	e7fb      	b.n	80048a0 <HAL_DMA_Abort_IT+0xa4>
 80048a8:	2310      	movs	r3, #16
 80048aa:	e7f9      	b.n	80048a0 <HAL_DMA_Abort_IT+0xa4>
 80048ac:	f44f 7380 	mov.w	r3, #256	; 0x100
 80048b0:	e7f6      	b.n	80048a0 <HAL_DMA_Abort_IT+0xa4>
 80048b2:	f44f 5380 	mov.w	r3, #4096	; 0x1000
 80048b6:	e7f3      	b.n	80048a0 <HAL_DMA_Abort_IT+0xa4>
 80048b8:	f44f 3380 	mov.w	r3, #65536	; 0x10000
 80048bc:	e7f0      	b.n	80048a0 <HAL_DMA_Abort_IT+0xa4>
 80048be:	f44f 1380 	mov.w	r3, #1048576	; 0x100000
 80048c2:	e7ed      	b.n	80048a0 <HAL_DMA_Abort_IT+0xa4>
  HAL_StatusTypeDef status = HAL_OK;
 80048c4:	4618      	mov	r0, r3
}
 80048c6:	bd10      	pop	{r4, pc}
 80048c8:	40020080 	.word	0x40020080
 80048cc:	40020400 	.word	0x40020400
 80048d0:	40020008 	.word	0x40020008
 80048d4:	40020000 	.word	0x40020000

080048d8 <HAL_DMA_IRQHandler>:
{
 80048d8:	b470      	push	{r4, r5, r6}
  if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET))
 80048da:	2504      	movs	r5, #4
  uint32_t flag_it = hdma->DmaBaseAddress->ISR;
 80048dc:	6bc6      	ldr	r6, [r0, #60]	; 0x3c
  if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET))
 80048de:	6c02      	ldr	r2, [r0, #64]	; 0x40
  uint32_t flag_it = hdma->DmaBaseAddress->ISR;
 80048e0:	6834      	ldr	r4, [r6, #0]
  uint32_t source_it = hdma->Instance->CCR;
 80048e2:	6803      	ldr	r3, [r0, #0]
  if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET))
 80048e4:	4095      	lsls	r5, r2
 80048e6:	4225      	tst	r5, r4
  uint32_t source_it = hdma->Instance->CCR;
 80048e8:	6819      	ldr	r1, [r3, #0]
  if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET))
 80048ea:	d055      	beq.n	8004998 <HAL_DMA_IRQHandler+0xc0>
 80048ec:	074d      	lsls	r5, r1, #29
 80048ee:	d553      	bpl.n	8004998 <HAL_DMA_IRQHandler+0xc0>
    if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
 80048f0:	681a      	ldr	r2, [r3, #0]
 80048f2:	0696      	lsls	r6, r2, #26
      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
 80048f4:	bf5e      	ittt	pl
 80048f6:	681a      	ldrpl	r2, [r3, #0]
 80048f8:	f022 0204 	bicpl.w	r2, r2, #4
 80048fc:	601a      	strpl	r2, [r3, #0]
    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
 80048fe:	4a60      	ldr	r2, [pc, #384]	; (8004a80 <HAL_DMA_IRQHandler+0x1a8>)
 8004900:	4293      	cmp	r3, r2
 8004902:	d91f      	bls.n	8004944 <HAL_DMA_IRQHandler+0x6c>
 8004904:	f502 7262 	add.w	r2, r2, #904	; 0x388
 8004908:	4293      	cmp	r3, r2
 800490a:	d014      	beq.n	8004936 <HAL_DMA_IRQHandler+0x5e>
 800490c:	3214      	adds	r2, #20
 800490e:	4293      	cmp	r3, r2
 8004910:	d013      	beq.n	800493a <HAL_DMA_IRQHandler+0x62>
 8004912:	3214      	adds	r2, #20
 8004914:	4293      	cmp	r3, r2
 8004916:	d012      	beq.n	800493e <HAL_DMA_IRQHandler+0x66>
 8004918:	3214      	adds	r2, #20
 800491a:	4293      	cmp	r3, r2
 800491c:	bf0c      	ite	eq
 800491e:	f44f 4380 	moveq.w	r3, #16384	; 0x4000
 8004922:	f44f 2380 	movne.w	r3, #262144	; 0x40000
 8004926:	4a57      	ldr	r2, [pc, #348]	; (8004a84 <HAL_DMA_IRQHandler+0x1ac>)
 8004928:	6053      	str	r3, [r2, #4]
    if(hdma->XferHalfCpltCallback != NULL)
 800492a:	6ac3      	ldr	r3, [r0, #44]	; 0x2c
    if (hdma->XferErrorCallback != NULL)
 800492c:	2b00      	cmp	r3, #0
 800492e:	f000 80a5 	beq.w	8004a7c <HAL_DMA_IRQHandler+0x1a4>
}
 8004932:	bc70      	pop	{r4, r5, r6}
      hdma->XferErrorCallback(hdma);
 8004934:	4718      	bx	r3
    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
 8004936:	2304      	movs	r3, #4
 8004938:	e7f5      	b.n	8004926 <HAL_DMA_IRQHandler+0x4e>
 800493a:	2340      	movs	r3, #64	; 0x40
 800493c:	e7f3      	b.n	8004926 <HAL_DMA_IRQHandler+0x4e>
 800493e:	f44f 6380 	mov.w	r3, #1024	; 0x400
 8004942:	e7f0      	b.n	8004926 <HAL_DMA_IRQHandler+0x4e>
 8004944:	4950      	ldr	r1, [pc, #320]	; (8004a88 <HAL_DMA_IRQHandler+0x1b0>)
 8004946:	428b      	cmp	r3, r1
 8004948:	d016      	beq.n	8004978 <HAL_DMA_IRQHandler+0xa0>
 800494a:	3114      	adds	r1, #20
 800494c:	428b      	cmp	r3, r1
 800494e:	d015      	beq.n	800497c <HAL_DMA_IRQHandler+0xa4>
 8004950:	3114      	adds	r1, #20
 8004952:	428b      	cmp	r3, r1
 8004954:	d014      	beq.n	8004980 <HAL_DMA_IRQHandler+0xa8>
 8004956:	3114      	adds	r1, #20
 8004958:	428b      	cmp	r3, r1
 800495a:	d014      	beq.n	8004986 <HAL_DMA_IRQHandler+0xae>
 800495c:	3114      	adds	r1, #20
 800495e:	428b      	cmp	r3, r1
 8004960:	d014      	beq.n	800498c <HAL_DMA_IRQHandler+0xb4>
 8004962:	3114      	adds	r1, #20
 8004964:	428b      	cmp	r3, r1
 8004966:	d014      	beq.n	8004992 <HAL_DMA_IRQHandler+0xba>
 8004968:	4293      	cmp	r3, r2
 800496a:	bf14      	ite	ne
 800496c:	f44f 2380 	movne.w	r3, #262144	; 0x40000
 8004970:	f04f 6380 	moveq.w	r3, #67108864	; 0x4000000
 8004974:	4a45      	ldr	r2, [pc, #276]	; (8004a8c <HAL_DMA_IRQHandler+0x1b4>)
 8004976:	e7d7      	b.n	8004928 <HAL_DMA_IRQHandler+0x50>
 8004978:	2304      	movs	r3, #4
 800497a:	e7fb      	b.n	8004974 <HAL_DMA_IRQHandler+0x9c>
 800497c:	2340      	movs	r3, #64	; 0x40
 800497e:	e7f9      	b.n	8004974 <HAL_DMA_IRQHandler+0x9c>
 8004980:	f44f 6380 	mov.w	r3, #1024	; 0x400
 8004984:	e7f6      	b.n	8004974 <HAL_DMA_IRQHandler+0x9c>
 8004986:	f44f 4380 	mov.w	r3, #16384	; 0x4000
 800498a:	e7f3      	b.n	8004974 <HAL_DMA_IRQHandler+0x9c>
 800498c:	f44f 2380 	mov.w	r3, #262144	; 0x40000
 8004990:	e7f0      	b.n	8004974 <HAL_DMA_IRQHandler+0x9c>
 8004992:	f44f 0380 	mov.w	r3, #4194304	; 0x400000
 8004996:	e7ed      	b.n	8004974 <HAL_DMA_IRQHandler+0x9c>
  else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET))
 8004998:	2502      	movs	r5, #2
 800499a:	4095      	lsls	r5, r2
 800499c:	4225      	tst	r5, r4
 800499e:	d057      	beq.n	8004a50 <HAL_DMA_IRQHandler+0x178>
 80049a0:	078d      	lsls	r5, r1, #30
 80049a2:	d555      	bpl.n	8004a50 <HAL_DMA_IRQHandler+0x178>
    if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
 80049a4:	681a      	ldr	r2, [r3, #0]
 80049a6:	0694      	lsls	r4, r2, #26
 80049a8:	d406      	bmi.n	80049b8 <HAL_DMA_IRQHandler+0xe0>
      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);  
 80049aa:	681a      	ldr	r2, [r3, #0]
 80049ac:	f022 020a 	bic.w	r2, r2, #10
 80049b0:	601a      	str	r2, [r3, #0]
      hdma->State = HAL_DMA_STATE_READY;
 80049b2:	2201      	movs	r2, #1
 80049b4:	f880 2021 	strb.w	r2, [r0, #33]	; 0x21
      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
 80049b8:	4a31      	ldr	r2, [pc, #196]	; (8004a80 <HAL_DMA_IRQHandler+0x1a8>)
 80049ba:	4293      	cmp	r3, r2
 80049bc:	d91e      	bls.n	80049fc <HAL_DMA_IRQHandler+0x124>
 80049be:	f502 7262 	add.w	r2, r2, #904	; 0x388
 80049c2:	4293      	cmp	r3, r2
 80049c4:	d013      	beq.n	80049ee <HAL_DMA_IRQHandler+0x116>
 80049c6:	3214      	adds	r2, #20
 80049c8:	4293      	cmp	r3, r2
 80049ca:	d012      	beq.n	80049f2 <HAL_DMA_IRQHandler+0x11a>
 80049cc:	3214      	adds	r2, #20
 80049ce:	4293      	cmp	r3, r2
 80049d0:	d011      	beq.n	80049f6 <HAL_DMA_IRQHandler+0x11e>
 80049d2:	3214      	adds	r2, #20
 80049d4:	4293      	cmp	r3, r2
 80049d6:	bf0c      	ite	eq
 80049d8:	f44f 5300 	moveq.w	r3, #8192	; 0x2000
 80049dc:	f44f 3300 	movne.w	r3, #131072	; 0x20000
 80049e0:	4a28      	ldr	r2, [pc, #160]	; (8004a84 <HAL_DMA_IRQHandler+0x1ac>)
 80049e2:	6053      	str	r3, [r2, #4]
    __HAL_UNLOCK(hdma);
 80049e4:	2300      	movs	r3, #0
 80049e6:	f880 3020 	strb.w	r3, [r0, #32]
    if(hdma->XferCpltCallback != NULL)
 80049ea:	6a83      	ldr	r3, [r0, #40]	; 0x28
 80049ec:	e79e      	b.n	800492c <HAL_DMA_IRQHandler+0x54>
      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
 80049ee:	2302      	movs	r3, #2
 80049f0:	e7f6      	b.n	80049e0 <HAL_DMA_IRQHandler+0x108>
 80049f2:	2320      	movs	r3, #32
 80049f4:	e7f4      	b.n	80049e0 <HAL_DMA_IRQHandler+0x108>
 80049f6:	f44f 7300 	mov.w	r3, #512	; 0x200
 80049fa:	e7f1      	b.n	80049e0 <HAL_DMA_IRQHandler+0x108>
 80049fc:	4922      	ldr	r1, [pc, #136]	; (8004a88 <HAL_DMA_IRQHandler+0x1b0>)
 80049fe:	428b      	cmp	r3, r1
 8004a00:	d016      	beq.n	8004a30 <HAL_DMA_IRQHandler+0x158>
 8004a02:	3114      	adds	r1, #20
 8004a04:	428b      	cmp	r3, r1
 8004a06:	d015      	beq.n	8004a34 <HAL_DMA_IRQHandler+0x15c>
 8004a08:	3114      	adds	r1, #20
 8004a0a:	428b      	cmp	r3, r1
 8004a0c:	d014      	beq.n	8004a38 <HAL_DMA_IRQHandler+0x160>
 8004a0e:	3114      	adds	r1, #20
 8004a10:	428b      	cmp	r3, r1
 8004a12:	d014      	beq.n	8004a3e <HAL_DMA_IRQHandler+0x166>
 8004a14:	3114      	adds	r1, #20
 8004a16:	428b      	cmp	r3, r1
 8004a18:	d014      	beq.n	8004a44 <HAL_DMA_IRQHandler+0x16c>
 8004a1a:	3114      	adds	r1, #20
 8004a1c:	428b      	cmp	r3, r1
 8004a1e:	d014      	beq.n	8004a4a <HAL_DMA_IRQHandler+0x172>
 8004a20:	4293      	cmp	r3, r2
 8004a22:	bf14      	ite	ne
 8004a24:	f44f 3300 	movne.w	r3, #131072	; 0x20000
 8004a28:	f04f 7300 	moveq.w	r3, #33554432	; 0x2000000
 8004a2c:	4a17      	ldr	r2, [pc, #92]	; (8004a8c <HAL_DMA_IRQHandler+0x1b4>)
 8004a2e:	e7d8      	b.n	80049e2 <HAL_DMA_IRQHandler+0x10a>
 8004a30:	2302      	movs	r3, #2
 8004a32:	e7fb      	b.n	8004a2c <HAL_DMA_IRQHandler+0x154>
 8004a34:	2320      	movs	r3, #32
 8004a36:	e7f9      	b.n	8004a2c <HAL_DMA_IRQHandler+0x154>
 8004a38:	f44f 7300 	mov.w	r3, #512	; 0x200
 8004a3c:	e7f6      	b.n	8004a2c <HAL_DMA_IRQHandler+0x154>
 8004a3e:	f44f 5300 	mov.w	r3, #8192	; 0x2000
 8004a42:	e7f3      	b.n	8004a2c <HAL_DMA_IRQHandler+0x154>
 8004a44:	f44f 3300 	mov.w	r3, #131072	; 0x20000
 8004a48:	e7f0      	b.n	8004a2c <HAL_DMA_IRQHandler+0x154>
 8004a4a:	f44f 1300 	mov.w	r3, #2097152	; 0x200000
 8004a4e:	e7ed      	b.n	8004a2c <HAL_DMA_IRQHandler+0x154>
  else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
 8004a50:	2508      	movs	r5, #8
 8004a52:	4095      	lsls	r5, r2
 8004a54:	4225      	tst	r5, r4
 8004a56:	d011      	beq.n	8004a7c <HAL_DMA_IRQHandler+0x1a4>
 8004a58:	0709      	lsls	r1, r1, #28
 8004a5a:	d50f      	bpl.n	8004a7c <HAL_DMA_IRQHandler+0x1a4>
    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
 8004a5c:	6819      	ldr	r1, [r3, #0]
 8004a5e:	f021 010e 	bic.w	r1, r1, #14
 8004a62:	6019      	str	r1, [r3, #0]
    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
 8004a64:	2301      	movs	r3, #1
 8004a66:	fa03 f202 	lsl.w	r2, r3, r2
 8004a6a:	6072      	str	r2, [r6, #4]
    hdma->ErrorCode = HAL_DMA_ERROR_TE;
 8004a6c:	6383      	str	r3, [r0, #56]	; 0x38
    hdma->State = HAL_DMA_STATE_READY;
 8004a6e:	f880 3021 	strb.w	r3, [r0, #33]	; 0x21
    __HAL_UNLOCK(hdma);
 8004a72:	2300      	movs	r3, #0
 8004a74:	f880 3020 	strb.w	r3, [r0, #32]
    if (hdma->XferErrorCallback != NULL)
 8004a78:	6b03      	ldr	r3, [r0, #48]	; 0x30
 8004a7a:	e757      	b.n	800492c <HAL_DMA_IRQHandler+0x54>
}
 8004a7c:	bc70      	pop	{r4, r5, r6}
 8004a7e:	4770      	bx	lr
 8004a80:	40020080 	.word	0x40020080
 8004a84:	40020400 	.word	0x40020400
 8004a88:	40020008 	.word	0x40020008
 8004a8c:	40020000 	.word	0x40020000

08004a90 <HAL_GPIO_Init>:
  * @param  GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
  *         the configuration information for the specified GPIO peripheral.
  * @retval None
  */
void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
 8004a90:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
  uint32_t position = 0x00u;
  uint32_t ioposition;
  uint32_t iocurrent;
  uint32_t temp;
  uint32_t config = 0x00u;
 8004a94:	2400      	movs	r4, #0
  uint32_t position = 0x00u;
 8004a96:	4626      	mov	r6, r4
      /*--------------------- EXTI Mode Configuration ------------------------*/
      /* Configure the External Interrupt or event for the current IO */
      if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
      {
        /* Enable AFIO Clock */
        __HAL_RCC_AFIO_CLK_ENABLE();
 8004a98:	4f6c      	ldr	r7, [pc, #432]	; (8004c4c <HAL_GPIO_Init+0x1bc>)
 8004a9a:	4b6d      	ldr	r3, [pc, #436]	; (8004c50 <HAL_GPIO_Init+0x1c0>)
        temp = AFIO->EXTICR[position >> 2u];
        CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u)));
        SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u)));
 8004a9c:	f8df e1b8 	ldr.w	lr, [pc, #440]	; 8004c58 <HAL_GPIO_Init+0x1c8>
      switch (GPIO_Init->Mode)
 8004aa0:	f8df c1b8 	ldr.w	ip, [pc, #440]	; 8004c5c <HAL_GPIO_Init+0x1cc>
  while (((GPIO_Init->Pin) >> position) != 0x00u)
 8004aa4:	680a      	ldr	r2, [r1, #0]
 8004aa6:	fa32 f506 	lsrs.w	r5, r2, r6
 8004aaa:	d102      	bne.n	8004ab2 <HAL_GPIO_Init+0x22>
      }
    }

	position++;
  }
}
 8004aac:	b003      	add	sp, #12
 8004aae:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
    ioposition = (0x01uL << position);
 8004ab2:	f04f 0801 	mov.w	r8, #1
 8004ab6:	fa08 f806 	lsl.w	r8, r8, r6
    iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
 8004aba:	ea02 0208 	and.w	r2, r2, r8
    if (iocurrent == ioposition)
 8004abe:	4590      	cmp	r8, r2
 8004ac0:	f040 8084 	bne.w	8004bcc <HAL_GPIO_Init+0x13c>
      switch (GPIO_Init->Mode)
 8004ac4:	684d      	ldr	r5, [r1, #4]
 8004ac6:	2d12      	cmp	r5, #18
 8004ac8:	f000 80b1 	beq.w	8004c2e <HAL_GPIO_Init+0x19e>
 8004acc:	f200 8087 	bhi.w	8004bde <HAL_GPIO_Init+0x14e>
 8004ad0:	2d02      	cmp	r5, #2
 8004ad2:	f000 80a9 	beq.w	8004c28 <HAL_GPIO_Init+0x198>
 8004ad6:	d87b      	bhi.n	8004bd0 <HAL_GPIO_Init+0x140>
 8004ad8:	2d00      	cmp	r5, #0
 8004ada:	f000 808c 	beq.w	8004bf6 <HAL_GPIO_Init+0x166>
 8004ade:	2d01      	cmp	r5, #1
 8004ae0:	f000 80a0 	beq.w	8004c24 <HAL_GPIO_Init+0x194>
      MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
 8004ae4:	f04f 090f 	mov.w	r9, #15
      configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL     : &GPIOx->CRH;
 8004ae8:	2aff      	cmp	r2, #255	; 0xff
 8004aea:	bf93      	iteet	ls
 8004aec:	4682      	movls	sl, r0
 8004aee:	f106 4580 	addhi.w	r5, r6, #1073741824	; 0x40000000
 8004af2:	3d08      	subhi	r5, #8
 8004af4:	f8d0 b000 	ldrls.w	fp, [r0]
 8004af8:	bf92      	itee	ls
 8004afa:	00b5      	lslls	r5, r6, #2
 8004afc:	f8d0 b004 	ldrhi.w	fp, [r0, #4]
 8004b00:	00ad      	lslhi	r5, r5, #2
      MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
 8004b02:	fa09 f805 	lsl.w	r8, r9, r5
 8004b06:	ea2b 0808 	bic.w	r8, fp, r8
 8004b0a:	fa04 f505 	lsl.w	r5, r4, r5
      configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL     : &GPIOx->CRH;
 8004b0e:	bf88      	it	hi
 8004b10:	f100 0a04 	addhi.w	sl, r0, #4
      MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
 8004b14:	ea48 0505 	orr.w	r5, r8, r5
 8004b18:	f8ca 5000 	str.w	r5, [sl]
      if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
 8004b1c:	f8d1 a004 	ldr.w	sl, [r1, #4]
 8004b20:	f01a 5f80 	tst.w	sl, #268435456	; 0x10000000
 8004b24:	d052      	beq.n	8004bcc <HAL_GPIO_Init+0x13c>
        __HAL_RCC_AFIO_CLK_ENABLE();
 8004b26:	69bd      	ldr	r5, [r7, #24]
 8004b28:	f026 0803 	bic.w	r8, r6, #3
 8004b2c:	f045 0501 	orr.w	r5, r5, #1
 8004b30:	61bd      	str	r5, [r7, #24]
 8004b32:	69bd      	ldr	r5, [r7, #24]
 8004b34:	f108 4880 	add.w	r8, r8, #1073741824	; 0x40000000
 8004b38:	f005 0501 	and.w	r5, r5, #1
 8004b3c:	9501      	str	r5, [sp, #4]
 8004b3e:	f508 3880 	add.w	r8, r8, #65536	; 0x10000
        CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u)));
 8004b42:	f006 0b03 	and.w	fp, r6, #3
        __HAL_RCC_AFIO_CLK_ENABLE();
 8004b46:	9d01      	ldr	r5, [sp, #4]
        CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u)));
 8004b48:	ea4f 0b8b 	mov.w	fp, fp, lsl #2
        temp = AFIO->EXTICR[position >> 2u];
 8004b4c:	f8d8 5008 	ldr.w	r5, [r8, #8]
        CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u)));
 8004b50:	fa09 f90b 	lsl.w	r9, r9, fp
 8004b54:	ea25 0909 	bic.w	r9, r5, r9
        SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u)));
 8004b58:	4d3e      	ldr	r5, [pc, #248]	; (8004c54 <HAL_GPIO_Init+0x1c4>)
 8004b5a:	42a8      	cmp	r0, r5
 8004b5c:	d06c      	beq.n	8004c38 <HAL_GPIO_Init+0x1a8>
 8004b5e:	f505 6580 	add.w	r5, r5, #1024	; 0x400
 8004b62:	42a8      	cmp	r0, r5
 8004b64:	d06a      	beq.n	8004c3c <HAL_GPIO_Init+0x1ac>
 8004b66:	f505 6580 	add.w	r5, r5, #1024	; 0x400
 8004b6a:	42a8      	cmp	r0, r5
 8004b6c:	d068      	beq.n	8004c40 <HAL_GPIO_Init+0x1b0>
 8004b6e:	f505 6580 	add.w	r5, r5, #1024	; 0x400
 8004b72:	42a8      	cmp	r0, r5
 8004b74:	d066      	beq.n	8004c44 <HAL_GPIO_Init+0x1b4>
 8004b76:	f505 6580 	add.w	r5, r5, #1024	; 0x400
 8004b7a:	42a8      	cmp	r0, r5
 8004b7c:	d064      	beq.n	8004c48 <HAL_GPIO_Init+0x1b8>
 8004b7e:	4570      	cmp	r0, lr
 8004b80:	bf0c      	ite	eq
 8004b82:	2505      	moveq	r5, #5
 8004b84:	2506      	movne	r5, #6
 8004b86:	fa05 f50b 	lsl.w	r5, r5, fp
 8004b8a:	ea45 0509 	orr.w	r5, r5, r9
        AFIO->EXTICR[position >> 2u] = temp;
 8004b8e:	f8c8 5008 	str.w	r5, [r8, #8]
          SET_BIT(EXTI->IMR, iocurrent);
 8004b92:	681d      	ldr	r5, [r3, #0]
        if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
 8004b94:	f41a 3f80 	tst.w	sl, #65536	; 0x10000
          SET_BIT(EXTI->IMR, iocurrent);
 8004b98:	bf14      	ite	ne
 8004b9a:	4315      	orrne	r5, r2
          CLEAR_BIT(EXTI->IMR, iocurrent);
 8004b9c:	4395      	biceq	r5, r2
 8004b9e:	601d      	str	r5, [r3, #0]
          SET_BIT(EXTI->EMR, iocurrent);
 8004ba0:	685d      	ldr	r5, [r3, #4]
        if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
 8004ba2:	f41a 3f00 	tst.w	sl, #131072	; 0x20000
          SET_BIT(EXTI->EMR, iocurrent);
 8004ba6:	bf14      	ite	ne
 8004ba8:	4315      	orrne	r5, r2
          CLEAR_BIT(EXTI->EMR, iocurrent);
 8004baa:	4395      	biceq	r5, r2
 8004bac:	605d      	str	r5, [r3, #4]
          SET_BIT(EXTI->RTSR, iocurrent);
 8004bae:	689d      	ldr	r5, [r3, #8]
        if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
 8004bb0:	f41a 1f80 	tst.w	sl, #1048576	; 0x100000
          SET_BIT(EXTI->RTSR, iocurrent);
 8004bb4:	bf14      	ite	ne
 8004bb6:	4315      	orrne	r5, r2
          CLEAR_BIT(EXTI->RTSR, iocurrent);
 8004bb8:	4395      	biceq	r5, r2
 8004bba:	609d      	str	r5, [r3, #8]
          SET_BIT(EXTI->FTSR, iocurrent);
 8004bbc:	68dd      	ldr	r5, [r3, #12]
        if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
 8004bbe:	f41a 1f00 	tst.w	sl, #2097152	; 0x200000
          SET_BIT(EXTI->FTSR, iocurrent);
 8004bc2:	bf14      	ite	ne
 8004bc4:	432a      	orrne	r2, r5
          CLEAR_BIT(EXTI->FTSR, iocurrent);
 8004bc6:	ea25 0202 	biceq.w	r2, r5, r2
 8004bca:	60da      	str	r2, [r3, #12]
	position++;
 8004bcc:	3601      	adds	r6, #1
 8004bce:	e769      	b.n	8004aa4 <HAL_GPIO_Init+0x14>
      switch (GPIO_Init->Mode)
 8004bd0:	2d03      	cmp	r5, #3
 8004bd2:	d025      	beq.n	8004c20 <HAL_GPIO_Init+0x190>
 8004bd4:	2d11      	cmp	r5, #17
 8004bd6:	d185      	bne.n	8004ae4 <HAL_GPIO_Init+0x54>
          config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;
 8004bd8:	68cc      	ldr	r4, [r1, #12]
 8004bda:	3404      	adds	r4, #4
          break;
 8004bdc:	e782      	b.n	8004ae4 <HAL_GPIO_Init+0x54>
      switch (GPIO_Init->Mode)
 8004bde:	4565      	cmp	r5, ip
 8004be0:	d009      	beq.n	8004bf6 <HAL_GPIO_Init+0x166>
 8004be2:	d812      	bhi.n	8004c0a <HAL_GPIO_Init+0x17a>
 8004be4:	f8df 9078 	ldr.w	r9, [pc, #120]	; 8004c60 <HAL_GPIO_Init+0x1d0>
 8004be8:	454d      	cmp	r5, r9
 8004bea:	d004      	beq.n	8004bf6 <HAL_GPIO_Init+0x166>
 8004bec:	f509 3980 	add.w	r9, r9, #65536	; 0x10000
 8004bf0:	454d      	cmp	r5, r9
 8004bf2:	f47f af77 	bne.w	8004ae4 <HAL_GPIO_Init+0x54>
          if (GPIO_Init->Pull == GPIO_NOPULL)
 8004bf6:	688c      	ldr	r4, [r1, #8]
 8004bf8:	b1e4      	cbz	r4, 8004c34 <HAL_GPIO_Init+0x1a4>
          else if (GPIO_Init->Pull == GPIO_PULLUP)
 8004bfa:	2c01      	cmp	r4, #1
            GPIOx->BSRR = ioposition;
 8004bfc:	bf0c      	ite	eq
 8004bfe:	f8c0 8010 	streq.w	r8, [r0, #16]
            GPIOx->BRR = ioposition;
 8004c02:	f8c0 8014 	strne.w	r8, [r0, #20]
            config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
 8004c06:	2408      	movs	r4, #8
 8004c08:	e76c      	b.n	8004ae4 <HAL_GPIO_Init+0x54>
      switch (GPIO_Init->Mode)
 8004c0a:	f8df 9058 	ldr.w	r9, [pc, #88]	; 8004c64 <HAL_GPIO_Init+0x1d4>
 8004c0e:	454d      	cmp	r5, r9
 8004c10:	d0f1      	beq.n	8004bf6 <HAL_GPIO_Init+0x166>
 8004c12:	f509 3980 	add.w	r9, r9, #65536	; 0x10000
 8004c16:	454d      	cmp	r5, r9
 8004c18:	d0ed      	beq.n	8004bf6 <HAL_GPIO_Init+0x166>
 8004c1a:	f5a9 1980 	sub.w	r9, r9, #1048576	; 0x100000
 8004c1e:	e7e7      	b.n	8004bf0 <HAL_GPIO_Init+0x160>
          config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
 8004c20:	2400      	movs	r4, #0
 8004c22:	e75f      	b.n	8004ae4 <HAL_GPIO_Init+0x54>
          config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;
 8004c24:	68cc      	ldr	r4, [r1, #12]
          break;
 8004c26:	e75d      	b.n	8004ae4 <HAL_GPIO_Init+0x54>
          config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;
 8004c28:	68cc      	ldr	r4, [r1, #12]
 8004c2a:	3408      	adds	r4, #8
          break;
 8004c2c:	e75a      	b.n	8004ae4 <HAL_GPIO_Init+0x54>
          config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;
 8004c2e:	68cc      	ldr	r4, [r1, #12]
 8004c30:	340c      	adds	r4, #12
          break;
 8004c32:	e757      	b.n	8004ae4 <HAL_GPIO_Init+0x54>
            config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
 8004c34:	2404      	movs	r4, #4
 8004c36:	e755      	b.n	8004ae4 <HAL_GPIO_Init+0x54>
        SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u)));
 8004c38:	2500      	movs	r5, #0
 8004c3a:	e7a4      	b.n	8004b86 <HAL_GPIO_Init+0xf6>
 8004c3c:	2501      	movs	r5, #1
 8004c3e:	e7a2      	b.n	8004b86 <HAL_GPIO_Init+0xf6>
 8004c40:	2502      	movs	r5, #2
 8004c42:	e7a0      	b.n	8004b86 <HAL_GPIO_Init+0xf6>
 8004c44:	2503      	movs	r5, #3
 8004c46:	e79e      	b.n	8004b86 <HAL_GPIO_Init+0xf6>
 8004c48:	2504      	movs	r5, #4
 8004c4a:	e79c      	b.n	8004b86 <HAL_GPIO_Init+0xf6>
 8004c4c:	40021000 	.word	0x40021000
 8004c50:	40010400 	.word	0x40010400
 8004c54:	40010800 	.word	0x40010800
 8004c58:	40011c00 	.word	0x40011c00
 8004c5c:	10210000 	.word	0x10210000
 8004c60:	10110000 	.word	0x10110000
 8004c64:	10310000 	.word	0x10310000

08004c68 <HAL_GPIO_WritePin>:
{
  /* Check the parameters */
  assert_param(IS_GPIO_PIN(GPIO_Pin));
  assert_param(IS_GPIO_PIN_ACTION(PinState));

  if (PinState != GPIO_PIN_RESET)
 8004c68:	b10a      	cbz	r2, 8004c6e <HAL_GPIO_WritePin+0x6>
  {
    GPIOx->BSRR = GPIO_Pin;
  }
  else
  {
    GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u;
 8004c6a:	6101      	str	r1, [r0, #16]
 8004c6c:	4770      	bx	lr
 8004c6e:	0409      	lsls	r1, r1, #16
 8004c70:	e7fb      	b.n	8004c6a <HAL_GPIO_WritePin+0x2>

08004c72 <HAL_GPIO_TogglePin>:
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
  /* Check the parameters */
  assert_param(IS_GPIO_PIN(GPIO_Pin));

  if ((GPIOx->ODR & GPIO_Pin) != 0x00u)
 8004c72:	68c3      	ldr	r3, [r0, #12]
 8004c74:	420b      	tst	r3, r1
  {
    GPIOx->BRR = (uint32_t)GPIO_Pin;
 8004c76:	bf14      	ite	ne
 8004c78:	6141      	strne	r1, [r0, #20]
  }
  else
  {
    GPIOx->BSRR = (uint32_t)GPIO_Pin;
 8004c7a:	6101      	streq	r1, [r0, #16]
 8004c7c:	4770      	bx	lr
	...

08004c80 <HAL_RCC_OscConfig>:
  *         supported by this macro. User should request a transition to HSE Off
  *         first and then HSE On or HSE Bypass.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
{
 8004c80:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
  uint32_t tickstart;
  uint32_t pll_config;

  /* Check Null pointer */
  if (RCC_OscInitStruct == NULL)
 8004c84:	4605      	mov	r5, r0
 8004c86:	b908      	cbnz	r0, 8004c8c <HAL_RCC_OscConfig+0xc>
    else
    {
      /* Check if there is a request to disable the PLL used as System clock source */
      if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
      {
        return HAL_ERROR;
 8004c88:	2001      	movs	r0, #1
 8004c8a:	e03c      	b.n	8004d06 <HAL_RCC_OscConfig+0x86>
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
 8004c8c:	6803      	ldr	r3, [r0, #0]
 8004c8e:	07db      	lsls	r3, r3, #31
 8004c90:	d410      	bmi.n	8004cb4 <HAL_RCC_OscConfig+0x34>
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
 8004c92:	682b      	ldr	r3, [r5, #0]
 8004c94:	079f      	lsls	r7, r3, #30
 8004c96:	d45d      	bmi.n	8004d54 <HAL_RCC_OscConfig+0xd4>
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
 8004c98:	682b      	ldr	r3, [r5, #0]
 8004c9a:	0719      	lsls	r1, r3, #28
 8004c9c:	f100 8094 	bmi.w	8004dc8 <HAL_RCC_OscConfig+0x148>
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
 8004ca0:	682b      	ldr	r3, [r5, #0]
 8004ca2:	075a      	lsls	r2, r3, #29
 8004ca4:	f100 80be 	bmi.w	8004e24 <HAL_RCC_OscConfig+0x1a4>
  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
 8004ca8:	69e8      	ldr	r0, [r5, #28]
 8004caa:	2800      	cmp	r0, #0
 8004cac:	f040 812c 	bne.w	8004f08 <HAL_RCC_OscConfig+0x288>
        }
      }
    }
  }

  return HAL_OK;
 8004cb0:	2000      	movs	r0, #0
 8004cb2:	e028      	b.n	8004d06 <HAL_RCC_OscConfig+0x86>
    if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
 8004cb4:	4c8f      	ldr	r4, [pc, #572]	; (8004ef4 <HAL_RCC_OscConfig+0x274>)
 8004cb6:	6863      	ldr	r3, [r4, #4]
 8004cb8:	f003 030c 	and.w	r3, r3, #12
 8004cbc:	2b04      	cmp	r3, #4
 8004cbe:	d007      	beq.n	8004cd0 <HAL_RCC_OscConfig+0x50>
        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
 8004cc0:	6863      	ldr	r3, [r4, #4]
 8004cc2:	f003 030c 	and.w	r3, r3, #12
 8004cc6:	2b08      	cmp	r3, #8
 8004cc8:	d109      	bne.n	8004cde <HAL_RCC_OscConfig+0x5e>
 8004cca:	6863      	ldr	r3, [r4, #4]
 8004ccc:	03de      	lsls	r6, r3, #15
 8004cce:	d506      	bpl.n	8004cde <HAL_RCC_OscConfig+0x5e>
      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
 8004cd0:	6823      	ldr	r3, [r4, #0]
 8004cd2:	039c      	lsls	r4, r3, #14
 8004cd4:	d5dd      	bpl.n	8004c92 <HAL_RCC_OscConfig+0x12>
 8004cd6:	686b      	ldr	r3, [r5, #4]
 8004cd8:	2b00      	cmp	r3, #0
 8004cda:	d1da      	bne.n	8004c92 <HAL_RCC_OscConfig+0x12>
 8004cdc:	e7d4      	b.n	8004c88 <HAL_RCC_OscConfig+0x8>
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 8004cde:	686b      	ldr	r3, [r5, #4]
 8004ce0:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
 8004ce4:	d112      	bne.n	8004d0c <HAL_RCC_OscConfig+0x8c>
 8004ce6:	6823      	ldr	r3, [r4, #0]
 8004ce8:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
 8004cec:	6023      	str	r3, [r4, #0]
        tickstart = HAL_GetTick();
 8004cee:	f7ff fadb 	bl	80042a8 <HAL_GetTick>
 8004cf2:	4606      	mov	r6, r0
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 8004cf4:	6823      	ldr	r3, [r4, #0]
 8004cf6:	0398      	lsls	r0, r3, #14
 8004cf8:	d4cb      	bmi.n	8004c92 <HAL_RCC_OscConfig+0x12>
          if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
 8004cfa:	f7ff fad5 	bl	80042a8 <HAL_GetTick>
 8004cfe:	1b80      	subs	r0, r0, r6
 8004d00:	2864      	cmp	r0, #100	; 0x64
 8004d02:	d9f7      	bls.n	8004cf4 <HAL_RCC_OscConfig+0x74>
            return HAL_TIMEOUT;
 8004d04:	2003      	movs	r0, #3
}
 8004d06:	b002      	add	sp, #8
 8004d08:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 8004d0c:	b99b      	cbnz	r3, 8004d36 <HAL_RCC_OscConfig+0xb6>
 8004d0e:	6823      	ldr	r3, [r4, #0]
 8004d10:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
 8004d14:	6023      	str	r3, [r4, #0]
 8004d16:	6823      	ldr	r3, [r4, #0]
 8004d18:	f423 2380 	bic.w	r3, r3, #262144	; 0x40000
 8004d1c:	6023      	str	r3, [r4, #0]
        tickstart = HAL_GetTick();
 8004d1e:	f7ff fac3 	bl	80042a8 <HAL_GetTick>
 8004d22:	4606      	mov	r6, r0
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
 8004d24:	6823      	ldr	r3, [r4, #0]
 8004d26:	0399      	lsls	r1, r3, #14
 8004d28:	d5b3      	bpl.n	8004c92 <HAL_RCC_OscConfig+0x12>
          if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
 8004d2a:	f7ff fabd 	bl	80042a8 <HAL_GetTick>
 8004d2e:	1b80      	subs	r0, r0, r6
 8004d30:	2864      	cmp	r0, #100	; 0x64
 8004d32:	d9f7      	bls.n	8004d24 <HAL_RCC_OscConfig+0xa4>
 8004d34:	e7e6      	b.n	8004d04 <HAL_RCC_OscConfig+0x84>
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 8004d36:	f5b3 2fa0 	cmp.w	r3, #327680	; 0x50000
 8004d3a:	6823      	ldr	r3, [r4, #0]
 8004d3c:	d103      	bne.n	8004d46 <HAL_RCC_OscConfig+0xc6>
 8004d3e:	f443 2380 	orr.w	r3, r3, #262144	; 0x40000
 8004d42:	6023      	str	r3, [r4, #0]
 8004d44:	e7cf      	b.n	8004ce6 <HAL_RCC_OscConfig+0x66>
 8004d46:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
 8004d4a:	6023      	str	r3, [r4, #0]
 8004d4c:	6823      	ldr	r3, [r4, #0]
 8004d4e:	f423 2380 	bic.w	r3, r3, #262144	; 0x40000
 8004d52:	e7cb      	b.n	8004cec <HAL_RCC_OscConfig+0x6c>
    if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
 8004d54:	4c67      	ldr	r4, [pc, #412]	; (8004ef4 <HAL_RCC_OscConfig+0x274>)
 8004d56:	6863      	ldr	r3, [r4, #4]
 8004d58:	f013 0f0c 	tst.w	r3, #12
 8004d5c:	d007      	beq.n	8004d6e <HAL_RCC_OscConfig+0xee>
        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
 8004d5e:	6863      	ldr	r3, [r4, #4]
 8004d60:	f003 030c 	and.w	r3, r3, #12
 8004d64:	2b08      	cmp	r3, #8
 8004d66:	d110      	bne.n	8004d8a <HAL_RCC_OscConfig+0x10a>
 8004d68:	6863      	ldr	r3, [r4, #4]
 8004d6a:	03da      	lsls	r2, r3, #15
 8004d6c:	d40d      	bmi.n	8004d8a <HAL_RCC_OscConfig+0x10a>
      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
 8004d6e:	6823      	ldr	r3, [r4, #0]
 8004d70:	079b      	lsls	r3, r3, #30
 8004d72:	d502      	bpl.n	8004d7a <HAL_RCC_OscConfig+0xfa>
 8004d74:	692b      	ldr	r3, [r5, #16]
 8004d76:	2b01      	cmp	r3, #1
 8004d78:	d186      	bne.n	8004c88 <HAL_RCC_OscConfig+0x8>
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 8004d7a:	6823      	ldr	r3, [r4, #0]
 8004d7c:	696a      	ldr	r2, [r5, #20]
 8004d7e:	f023 03f8 	bic.w	r3, r3, #248	; 0xf8
 8004d82:	ea43 03c2 	orr.w	r3, r3, r2, lsl #3
 8004d86:	6023      	str	r3, [r4, #0]
 8004d88:	e786      	b.n	8004c98 <HAL_RCC_OscConfig+0x18>
      if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
 8004d8a:	692a      	ldr	r2, [r5, #16]
 8004d8c:	4b5a      	ldr	r3, [pc, #360]	; (8004ef8 <HAL_RCC_OscConfig+0x278>)
 8004d8e:	b16a      	cbz	r2, 8004dac <HAL_RCC_OscConfig+0x12c>
        __HAL_RCC_HSI_ENABLE();
 8004d90:	2201      	movs	r2, #1
 8004d92:	601a      	str	r2, [r3, #0]
        tickstart = HAL_GetTick();
 8004d94:	f7ff fa88 	bl	80042a8 <HAL_GetTick>
 8004d98:	4606      	mov	r6, r0
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 8004d9a:	6823      	ldr	r3, [r4, #0]
 8004d9c:	079f      	lsls	r7, r3, #30
 8004d9e:	d4ec      	bmi.n	8004d7a <HAL_RCC_OscConfig+0xfa>
          if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
 8004da0:	f7ff fa82 	bl	80042a8 <HAL_GetTick>
 8004da4:	1b80      	subs	r0, r0, r6
 8004da6:	2802      	cmp	r0, #2
 8004da8:	d9f7      	bls.n	8004d9a <HAL_RCC_OscConfig+0x11a>
 8004daa:	e7ab      	b.n	8004d04 <HAL_RCC_OscConfig+0x84>
        __HAL_RCC_HSI_DISABLE();
 8004dac:	601a      	str	r2, [r3, #0]
        tickstart = HAL_GetTick();
 8004dae:	f7ff fa7b 	bl	80042a8 <HAL_GetTick>
 8004db2:	4606      	mov	r6, r0
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
 8004db4:	6823      	ldr	r3, [r4, #0]
 8004db6:	0798      	lsls	r0, r3, #30
 8004db8:	f57f af6e 	bpl.w	8004c98 <HAL_RCC_OscConfig+0x18>
          if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
 8004dbc:	f7ff fa74 	bl	80042a8 <HAL_GetTick>
 8004dc0:	1b80      	subs	r0, r0, r6
 8004dc2:	2802      	cmp	r0, #2
 8004dc4:	d9f6      	bls.n	8004db4 <HAL_RCC_OscConfig+0x134>
 8004dc6:	e79d      	b.n	8004d04 <HAL_RCC_OscConfig+0x84>
    if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
 8004dc8:	69aa      	ldr	r2, [r5, #24]
 8004dca:	4c4a      	ldr	r4, [pc, #296]	; (8004ef4 <HAL_RCC_OscConfig+0x274>)
 8004dcc:	4b4b      	ldr	r3, [pc, #300]	; (8004efc <HAL_RCC_OscConfig+0x27c>)
 8004dce:	b1da      	cbz	r2, 8004e08 <HAL_RCC_OscConfig+0x188>
      __HAL_RCC_LSI_ENABLE();
 8004dd0:	2201      	movs	r2, #1
 8004dd2:	601a      	str	r2, [r3, #0]
      tickstart = HAL_GetTick();
 8004dd4:	f7ff fa68 	bl	80042a8 <HAL_GetTick>
 8004dd8:	4606      	mov	r6, r0
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
 8004dda:	6a63      	ldr	r3, [r4, #36]	; 0x24
 8004ddc:	079b      	lsls	r3, r3, #30
 8004dde:	d50d      	bpl.n	8004dfc <HAL_RCC_OscConfig+0x17c>
  * @param  mdelay: specifies the delay time length, in milliseconds.
  * @retval None
  */
static void RCC_Delay(uint32_t mdelay)
{
  __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
 8004de0:	f44f 52fa 	mov.w	r2, #8000	; 0x1f40
 8004de4:	4b46      	ldr	r3, [pc, #280]	; (8004f00 <HAL_RCC_OscConfig+0x280>)
 8004de6:	681b      	ldr	r3, [r3, #0]
 8004de8:	fbb3 f3f2 	udiv	r3, r3, r2
 8004dec:	9301      	str	r3, [sp, #4]
  do
  {
    __NOP();
 8004dee:	bf00      	nop
  }
  while (Delay --);
 8004df0:	9b01      	ldr	r3, [sp, #4]
 8004df2:	1e5a      	subs	r2, r3, #1
 8004df4:	9201      	str	r2, [sp, #4]
 8004df6:	2b00      	cmp	r3, #0
 8004df8:	d1f9      	bne.n	8004dee <HAL_RCC_OscConfig+0x16e>
 8004dfa:	e751      	b.n	8004ca0 <HAL_RCC_OscConfig+0x20>
        if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
 8004dfc:	f7ff fa54 	bl	80042a8 <HAL_GetTick>
 8004e00:	1b80      	subs	r0, r0, r6
 8004e02:	2802      	cmp	r0, #2
 8004e04:	d9e9      	bls.n	8004dda <HAL_RCC_OscConfig+0x15a>
 8004e06:	e77d      	b.n	8004d04 <HAL_RCC_OscConfig+0x84>
      __HAL_RCC_LSI_DISABLE();
 8004e08:	601a      	str	r2, [r3, #0]
      tickstart = HAL_GetTick();
 8004e0a:	f7ff fa4d 	bl	80042a8 <HAL_GetTick>
 8004e0e:	4606      	mov	r6, r0
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
 8004e10:	6a63      	ldr	r3, [r4, #36]	; 0x24
 8004e12:	079f      	lsls	r7, r3, #30
 8004e14:	f57f af44 	bpl.w	8004ca0 <HAL_RCC_OscConfig+0x20>
        if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
 8004e18:	f7ff fa46 	bl	80042a8 <HAL_GetTick>
 8004e1c:	1b80      	subs	r0, r0, r6
 8004e1e:	2802      	cmp	r0, #2
 8004e20:	d9f6      	bls.n	8004e10 <HAL_RCC_OscConfig+0x190>
 8004e22:	e76f      	b.n	8004d04 <HAL_RCC_OscConfig+0x84>
    if (__HAL_RCC_PWR_IS_CLK_DISABLED())
 8004e24:	4c33      	ldr	r4, [pc, #204]	; (8004ef4 <HAL_RCC_OscConfig+0x274>)
 8004e26:	69e3      	ldr	r3, [r4, #28]
 8004e28:	00d8      	lsls	r0, r3, #3
 8004e2a:	d424      	bmi.n	8004e76 <HAL_RCC_OscConfig+0x1f6>
      pwrclkchanged = SET;
 8004e2c:	2701      	movs	r7, #1
      __HAL_RCC_PWR_CLK_ENABLE();
 8004e2e:	69e3      	ldr	r3, [r4, #28]
 8004e30:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
 8004e34:	61e3      	str	r3, [r4, #28]
 8004e36:	69e3      	ldr	r3, [r4, #28]
 8004e38:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8004e3c:	9300      	str	r3, [sp, #0]
 8004e3e:	9b00      	ldr	r3, [sp, #0]
    if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 8004e40:	4e30      	ldr	r6, [pc, #192]	; (8004f04 <HAL_RCC_OscConfig+0x284>)
 8004e42:	6833      	ldr	r3, [r6, #0]
 8004e44:	05d9      	lsls	r1, r3, #23
 8004e46:	d518      	bpl.n	8004e7a <HAL_RCC_OscConfig+0x1fa>
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 8004e48:	68eb      	ldr	r3, [r5, #12]
 8004e4a:	2b01      	cmp	r3, #1
 8004e4c:	d126      	bne.n	8004e9c <HAL_RCC_OscConfig+0x21c>
 8004e4e:	6a23      	ldr	r3, [r4, #32]
 8004e50:	f043 0301 	orr.w	r3, r3, #1
 8004e54:	6223      	str	r3, [r4, #32]
      tickstart = HAL_GetTick();
 8004e56:	f7ff fa27 	bl	80042a8 <HAL_GetTick>
        if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 8004e5a:	f241 3688 	movw	r6, #5000	; 0x1388
      tickstart = HAL_GetTick();
 8004e5e:	4680      	mov	r8, r0
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
 8004e60:	6a23      	ldr	r3, [r4, #32]
 8004e62:	079b      	lsls	r3, r3, #30
 8004e64:	d53f      	bpl.n	8004ee6 <HAL_RCC_OscConfig+0x266>
    if (pwrclkchanged == SET)
 8004e66:	2f00      	cmp	r7, #0
 8004e68:	f43f af1e 	beq.w	8004ca8 <HAL_RCC_OscConfig+0x28>
      __HAL_RCC_PWR_CLK_DISABLE();
 8004e6c:	69e3      	ldr	r3, [r4, #28]
 8004e6e:	f023 5380 	bic.w	r3, r3, #268435456	; 0x10000000
 8004e72:	61e3      	str	r3, [r4, #28]
 8004e74:	e718      	b.n	8004ca8 <HAL_RCC_OscConfig+0x28>
    FlagStatus       pwrclkchanged = RESET;
 8004e76:	2700      	movs	r7, #0
 8004e78:	e7e2      	b.n	8004e40 <HAL_RCC_OscConfig+0x1c0>
      SET_BIT(PWR->CR, PWR_CR_DBP);
 8004e7a:	6833      	ldr	r3, [r6, #0]
 8004e7c:	f443 7380 	orr.w	r3, r3, #256	; 0x100
 8004e80:	6033      	str	r3, [r6, #0]
      tickstart = HAL_GetTick();
 8004e82:	f7ff fa11 	bl	80042a8 <HAL_GetTick>
 8004e86:	4680      	mov	r8, r0
      while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 8004e88:	6833      	ldr	r3, [r6, #0]
 8004e8a:	05da      	lsls	r2, r3, #23
 8004e8c:	d4dc      	bmi.n	8004e48 <HAL_RCC_OscConfig+0x1c8>
        if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
 8004e8e:	f7ff fa0b 	bl	80042a8 <HAL_GetTick>
 8004e92:	eba0 0008 	sub.w	r0, r0, r8
 8004e96:	2864      	cmp	r0, #100	; 0x64
 8004e98:	d9f6      	bls.n	8004e88 <HAL_RCC_OscConfig+0x208>
 8004e9a:	e733      	b.n	8004d04 <HAL_RCC_OscConfig+0x84>
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 8004e9c:	b9ab      	cbnz	r3, 8004eca <HAL_RCC_OscConfig+0x24a>
 8004e9e:	6a23      	ldr	r3, [r4, #32]
        if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 8004ea0:	f241 3888 	movw	r8, #5000	; 0x1388
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 8004ea4:	f023 0301 	bic.w	r3, r3, #1
 8004ea8:	6223      	str	r3, [r4, #32]
 8004eaa:	6a23      	ldr	r3, [r4, #32]
 8004eac:	f023 0304 	bic.w	r3, r3, #4
 8004eb0:	6223      	str	r3, [r4, #32]
      tickstart = HAL_GetTick();
 8004eb2:	f7ff f9f9 	bl	80042a8 <HAL_GetTick>
 8004eb6:	4606      	mov	r6, r0
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
 8004eb8:	6a23      	ldr	r3, [r4, #32]
 8004eba:	0798      	lsls	r0, r3, #30
 8004ebc:	d5d3      	bpl.n	8004e66 <HAL_RCC_OscConfig+0x1e6>
        if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 8004ebe:	f7ff f9f3 	bl	80042a8 <HAL_GetTick>
 8004ec2:	1b80      	subs	r0, r0, r6
 8004ec4:	4540      	cmp	r0, r8
 8004ec6:	d9f7      	bls.n	8004eb8 <HAL_RCC_OscConfig+0x238>
 8004ec8:	e71c      	b.n	8004d04 <HAL_RCC_OscConfig+0x84>
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 8004eca:	2b05      	cmp	r3, #5
 8004ecc:	6a23      	ldr	r3, [r4, #32]
 8004ece:	d103      	bne.n	8004ed8 <HAL_RCC_OscConfig+0x258>
 8004ed0:	f043 0304 	orr.w	r3, r3, #4
 8004ed4:	6223      	str	r3, [r4, #32]
 8004ed6:	e7ba      	b.n	8004e4e <HAL_RCC_OscConfig+0x1ce>
 8004ed8:	f023 0301 	bic.w	r3, r3, #1
 8004edc:	6223      	str	r3, [r4, #32]
 8004ede:	6a23      	ldr	r3, [r4, #32]
 8004ee0:	f023 0304 	bic.w	r3, r3, #4
 8004ee4:	e7b6      	b.n	8004e54 <HAL_RCC_OscConfig+0x1d4>
        if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 8004ee6:	f7ff f9df 	bl	80042a8 <HAL_GetTick>
 8004eea:	eba0 0008 	sub.w	r0, r0, r8
 8004eee:	42b0      	cmp	r0, r6
 8004ef0:	d9b6      	bls.n	8004e60 <HAL_RCC_OscConfig+0x1e0>
 8004ef2:	e707      	b.n	8004d04 <HAL_RCC_OscConfig+0x84>
 8004ef4:	40021000 	.word	0x40021000
 8004ef8:	42420000 	.word	0x42420000
 8004efc:	42420480 	.word	0x42420480
 8004f00:	20000208 	.word	0x20000208
 8004f04:	40007000 	.word	0x40007000
    if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
 8004f08:	4b2a      	ldr	r3, [pc, #168]	; (8004fb4 <HAL_RCC_OscConfig+0x334>)
 8004f0a:	685a      	ldr	r2, [r3, #4]
 8004f0c:	461c      	mov	r4, r3
 8004f0e:	f002 020c 	and.w	r2, r2, #12
 8004f12:	2a08      	cmp	r2, #8
 8004f14:	d03d      	beq.n	8004f92 <HAL_RCC_OscConfig+0x312>
 8004f16:	2300      	movs	r3, #0
 8004f18:	4e27      	ldr	r6, [pc, #156]	; (8004fb8 <HAL_RCC_OscConfig+0x338>)
      if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
 8004f1a:	2802      	cmp	r0, #2
        __HAL_RCC_PLL_DISABLE();
 8004f1c:	6033      	str	r3, [r6, #0]
      if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
 8004f1e:	d12b      	bne.n	8004f78 <HAL_RCC_OscConfig+0x2f8>
        tickstart = HAL_GetTick();
 8004f20:	f7ff f9c2 	bl	80042a8 <HAL_GetTick>
 8004f24:	4607      	mov	r7, r0
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
 8004f26:	6823      	ldr	r3, [r4, #0]
 8004f28:	0199      	lsls	r1, r3, #6
 8004f2a:	d41f      	bmi.n	8004f6c <HAL_RCC_OscConfig+0x2ec>
        if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
 8004f2c:	6a2b      	ldr	r3, [r5, #32]
 8004f2e:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
 8004f32:	d105      	bne.n	8004f40 <HAL_RCC_OscConfig+0x2c0>
          __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
 8004f34:	6862      	ldr	r2, [r4, #4]
 8004f36:	68a9      	ldr	r1, [r5, #8]
 8004f38:	f422 3200 	bic.w	r2, r2, #131072	; 0x20000
 8004f3c:	430a      	orrs	r2, r1
 8004f3e:	6062      	str	r2, [r4, #4]
        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
 8004f40:	6a69      	ldr	r1, [r5, #36]	; 0x24
 8004f42:	6862      	ldr	r2, [r4, #4]
 8004f44:	430b      	orrs	r3, r1
 8004f46:	f422 1274 	bic.w	r2, r2, #3997696	; 0x3d0000
 8004f4a:	4313      	orrs	r3, r2
 8004f4c:	6063      	str	r3, [r4, #4]
        __HAL_RCC_PLL_ENABLE();
 8004f4e:	2301      	movs	r3, #1
 8004f50:	6033      	str	r3, [r6, #0]
        tickstart = HAL_GetTick();
 8004f52:	f7ff f9a9 	bl	80042a8 <HAL_GetTick>
 8004f56:	4605      	mov	r5, r0
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  == RESET)
 8004f58:	6823      	ldr	r3, [r4, #0]
 8004f5a:	019a      	lsls	r2, r3, #6
 8004f5c:	f53f aea8 	bmi.w	8004cb0 <HAL_RCC_OscConfig+0x30>
          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
 8004f60:	f7ff f9a2 	bl	80042a8 <HAL_GetTick>
 8004f64:	1b40      	subs	r0, r0, r5
 8004f66:	2802      	cmp	r0, #2
 8004f68:	d9f6      	bls.n	8004f58 <HAL_RCC_OscConfig+0x2d8>
 8004f6a:	e6cb      	b.n	8004d04 <HAL_RCC_OscConfig+0x84>
          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
 8004f6c:	f7ff f99c 	bl	80042a8 <HAL_GetTick>
 8004f70:	1bc0      	subs	r0, r0, r7
 8004f72:	2802      	cmp	r0, #2
 8004f74:	d9d7      	bls.n	8004f26 <HAL_RCC_OscConfig+0x2a6>
 8004f76:	e6c5      	b.n	8004d04 <HAL_RCC_OscConfig+0x84>
        tickstart = HAL_GetTick();
 8004f78:	f7ff f996 	bl	80042a8 <HAL_GetTick>
 8004f7c:	4605      	mov	r5, r0
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
 8004f7e:	6823      	ldr	r3, [r4, #0]
 8004f80:	019b      	lsls	r3, r3, #6
 8004f82:	f57f ae95 	bpl.w	8004cb0 <HAL_RCC_OscConfig+0x30>
          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
 8004f86:	f7ff f98f 	bl	80042a8 <HAL_GetTick>
 8004f8a:	1b40      	subs	r0, r0, r5
 8004f8c:	2802      	cmp	r0, #2
 8004f8e:	d9f6      	bls.n	8004f7e <HAL_RCC_OscConfig+0x2fe>
 8004f90:	e6b8      	b.n	8004d04 <HAL_RCC_OscConfig+0x84>
      if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
 8004f92:	2801      	cmp	r0, #1
 8004f94:	f43f aeb7 	beq.w	8004d06 <HAL_RCC_OscConfig+0x86>
        pll_config = RCC->CFGR;
 8004f98:	6858      	ldr	r0, [r3, #4]
        if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
 8004f9a:	6a2b      	ldr	r3, [r5, #32]
 8004f9c:	f400 3280 	and.w	r2, r0, #65536	; 0x10000
 8004fa0:	429a      	cmp	r2, r3
 8004fa2:	f47f ae71 	bne.w	8004c88 <HAL_RCC_OscConfig+0x8>
 8004fa6:	6a6b      	ldr	r3, [r5, #36]	; 0x24
            (READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL))
 8004fa8:	f400 1070 	and.w	r0, r0, #3932160	; 0x3c0000
    return HAL_ERROR;
 8004fac:	1ac0      	subs	r0, r0, r3
 8004fae:	bf18      	it	ne
 8004fb0:	2001      	movne	r0, #1
 8004fb2:	e6a8      	b.n	8004d06 <HAL_RCC_OscConfig+0x86>
 8004fb4:	40021000 	.word	0x40021000
 8004fb8:	42420060 	.word	0x42420060

08004fbc <HAL_RCC_GetSysClockFreq>:
{
 8004fbc:	b530      	push	{r4, r5, lr}
  const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
 8004fbe:	4b19      	ldr	r3, [pc, #100]	; (8005024 <HAL_RCC_GetSysClockFreq+0x68>)
{
 8004fc0:	b087      	sub	sp, #28
  const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
 8004fc2:	ac02      	add	r4, sp, #8
 8004fc4:	f103 0510 	add.w	r5, r3, #16
 8004fc8:	4622      	mov	r2, r4
 8004fca:	6818      	ldr	r0, [r3, #0]
 8004fcc:	6859      	ldr	r1, [r3, #4]
 8004fce:	3308      	adds	r3, #8
 8004fd0:	c203      	stmia	r2!, {r0, r1}
 8004fd2:	42ab      	cmp	r3, r5
 8004fd4:	4614      	mov	r4, r2
 8004fd6:	d1f7      	bne.n	8004fc8 <HAL_RCC_GetSysClockFreq+0xc>
  const uint8_t aPredivFactorTable[2] = {1, 2};
 8004fd8:	2301      	movs	r3, #1
 8004fda:	f88d 3004 	strb.w	r3, [sp, #4]
 8004fde:	2302      	movs	r3, #2
  tmpreg = RCC->CFGR;
 8004fe0:	4911      	ldr	r1, [pc, #68]	; (8005028 <HAL_RCC_GetSysClockFreq+0x6c>)
  const uint8_t aPredivFactorTable[2] = {1, 2};
 8004fe2:	f88d 3005 	strb.w	r3, [sp, #5]
  tmpreg = RCC->CFGR;
 8004fe6:	684b      	ldr	r3, [r1, #4]
  switch (tmpreg & RCC_CFGR_SWS)
 8004fe8:	f003 020c 	and.w	r2, r3, #12
 8004fec:	2a08      	cmp	r2, #8
 8004fee:	d117      	bne.n	8005020 <HAL_RCC_GetSysClockFreq+0x64>
      pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
 8004ff0:	f3c3 4283 	ubfx	r2, r3, #18, #4
 8004ff4:	a806      	add	r0, sp, #24
 8004ff6:	4402      	add	r2, r0
      if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
 8004ff8:	03db      	lsls	r3, r3, #15
      pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
 8004ffa:	f812 2c10 	ldrb.w	r2, [r2, #-16]
      if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
 8004ffe:	d50c      	bpl.n	800501a <HAL_RCC_GetSysClockFreq+0x5e>
        prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
 8005000:	684b      	ldr	r3, [r1, #4]
        pllclk = (uint32_t)((HSE_VALUE  * pllmul) / prediv);
 8005002:	480a      	ldr	r0, [pc, #40]	; (800502c <HAL_RCC_GetSysClockFreq+0x70>)
        prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
 8005004:	f3c3 4340 	ubfx	r3, r3, #17, #1
        pllclk = (uint32_t)((HSE_VALUE  * pllmul) / prediv);
 8005008:	4350      	muls	r0, r2
        prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
 800500a:	aa06      	add	r2, sp, #24
 800500c:	4413      	add	r3, r2
 800500e:	f813 3c14 	ldrb.w	r3, [r3, #-20]
        pllclk = (uint32_t)((HSE_VALUE  * pllmul) / prediv);
 8005012:	fbb0 f0f3 	udiv	r0, r0, r3
}
 8005016:	b007      	add	sp, #28
 8005018:	bd30      	pop	{r4, r5, pc}
        pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
 800501a:	4805      	ldr	r0, [pc, #20]	; (8005030 <HAL_RCC_GetSysClockFreq+0x74>)
 800501c:	4350      	muls	r0, r2
 800501e:	e7fa      	b.n	8005016 <HAL_RCC_GetSysClockFreq+0x5a>
      sysclockfreq = HSE_VALUE;
 8005020:	4802      	ldr	r0, [pc, #8]	; (800502c <HAL_RCC_GetSysClockFreq+0x70>)
  return sysclockfreq;
 8005022:	e7f8      	b.n	8005016 <HAL_RCC_GetSysClockFreq+0x5a>
 8005024:	080076cc 	.word	0x080076cc
 8005028:	40021000 	.word	0x40021000
 800502c:	007a1200 	.word	0x007a1200
 8005030:	003d0900 	.word	0x003d0900

08005034 <HAL_RCC_ClockConfig>:
{
 8005034:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
 8005038:	460d      	mov	r5, r1
  if (RCC_ClkInitStruct == NULL)
 800503a:	4604      	mov	r4, r0
 800503c:	b910      	cbnz	r0, 8005044 <HAL_RCC_ClockConfig+0x10>
    return HAL_ERROR;
 800503e:	2001      	movs	r0, #1
 8005040:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
  if (FLatency > __HAL_FLASH_GET_LATENCY())
 8005044:	4a45      	ldr	r2, [pc, #276]	; (800515c <HAL_RCC_ClockConfig+0x128>)
 8005046:	6813      	ldr	r3, [r2, #0]
 8005048:	f003 0307 	and.w	r3, r3, #7
 800504c:	428b      	cmp	r3, r1
 800504e:	d329      	bcc.n	80050a4 <HAL_RCC_ClockConfig+0x70>
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
 8005050:	6821      	ldr	r1, [r4, #0]
 8005052:	078e      	lsls	r6, r1, #30
 8005054:	d431      	bmi.n	80050ba <HAL_RCC_ClockConfig+0x86>
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
 8005056:	07ca      	lsls	r2, r1, #31
 8005058:	d444      	bmi.n	80050e4 <HAL_RCC_ClockConfig+0xb0>
  if (FLatency < __HAL_FLASH_GET_LATENCY())
 800505a:	4a40      	ldr	r2, [pc, #256]	; (800515c <HAL_RCC_ClockConfig+0x128>)
 800505c:	6813      	ldr	r3, [r2, #0]
 800505e:	f003 0307 	and.w	r3, r3, #7
 8005062:	429d      	cmp	r5, r3
 8005064:	d367      	bcc.n	8005136 <HAL_RCC_ClockConfig+0x102>
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 8005066:	6822      	ldr	r2, [r4, #0]
 8005068:	4d3d      	ldr	r5, [pc, #244]	; (8005160 <HAL_RCC_ClockConfig+0x12c>)
 800506a:	f012 0f04 	tst.w	r2, #4
 800506e:	d16e      	bne.n	800514e <HAL_RCC_ClockConfig+0x11a>
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
 8005070:	0713      	lsls	r3, r2, #28
 8005072:	d506      	bpl.n	8005082 <HAL_RCC_ClockConfig+0x4e>
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
 8005074:	686b      	ldr	r3, [r5, #4]
 8005076:	6922      	ldr	r2, [r4, #16]
 8005078:	f423 5360 	bic.w	r3, r3, #14336	; 0x3800
 800507c:	ea43 03c2 	orr.w	r3, r3, r2, lsl #3
 8005080:	606b      	str	r3, [r5, #4]
  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
 8005082:	f7ff ff9b 	bl	8004fbc <HAL_RCC_GetSysClockFreq>
 8005086:	686b      	ldr	r3, [r5, #4]
 8005088:	4a36      	ldr	r2, [pc, #216]	; (8005164 <HAL_RCC_ClockConfig+0x130>)
 800508a:	f3c3 1303 	ubfx	r3, r3, #4, #4
 800508e:	5cd3      	ldrb	r3, [r2, r3]
 8005090:	40d8      	lsrs	r0, r3
 8005092:	4b35      	ldr	r3, [pc, #212]	; (8005168 <HAL_RCC_ClockConfig+0x134>)
 8005094:	6018      	str	r0, [r3, #0]
  HAL_InitTick(uwTickPrio);
 8005096:	4b35      	ldr	r3, [pc, #212]	; (800516c <HAL_RCC_ClockConfig+0x138>)
 8005098:	6818      	ldr	r0, [r3, #0]
 800509a:	f7ff f8c3 	bl	8004224 <HAL_InitTick>
  return HAL_OK;
 800509e:	2000      	movs	r0, #0
 80050a0:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    __HAL_FLASH_SET_LATENCY(FLatency);
 80050a4:	6813      	ldr	r3, [r2, #0]
 80050a6:	f023 0307 	bic.w	r3, r3, #7
 80050aa:	430b      	orrs	r3, r1
 80050ac:	6013      	str	r3, [r2, #0]
    if (__HAL_FLASH_GET_LATENCY() != FLatency)
 80050ae:	6813      	ldr	r3, [r2, #0]
 80050b0:	f003 0307 	and.w	r3, r3, #7
 80050b4:	4299      	cmp	r1, r3
 80050b6:	d1c2      	bne.n	800503e <HAL_RCC_ClockConfig+0xa>
 80050b8:	e7ca      	b.n	8005050 <HAL_RCC_ClockConfig+0x1c>
 80050ba:	4b29      	ldr	r3, [pc, #164]	; (8005160 <HAL_RCC_ClockConfig+0x12c>)
    if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 80050bc:	f011 0f04 	tst.w	r1, #4
      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
 80050c0:	bf1e      	ittt	ne
 80050c2:	685a      	ldrne	r2, [r3, #4]
 80050c4:	f442 62e0 	orrne.w	r2, r2, #1792	; 0x700
 80050c8:	605a      	strne	r2, [r3, #4]
    if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
 80050ca:	0708      	lsls	r0, r1, #28
      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
 80050cc:	bf42      	ittt	mi
 80050ce:	685a      	ldrmi	r2, [r3, #4]
 80050d0:	f442 5260 	orrmi.w	r2, r2, #14336	; 0x3800
 80050d4:	605a      	strmi	r2, [r3, #4]
    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
 80050d6:	685a      	ldr	r2, [r3, #4]
 80050d8:	68a0      	ldr	r0, [r4, #8]
 80050da:	f022 02f0 	bic.w	r2, r2, #240	; 0xf0
 80050de:	4302      	orrs	r2, r0
 80050e0:	605a      	str	r2, [r3, #4]
 80050e2:	e7b8      	b.n	8005056 <HAL_RCC_ClockConfig+0x22>
    if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 80050e4:	6862      	ldr	r2, [r4, #4]
 80050e6:	4e1e      	ldr	r6, [pc, #120]	; (8005160 <HAL_RCC_ClockConfig+0x12c>)
 80050e8:	2a01      	cmp	r2, #1
      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 80050ea:	6833      	ldr	r3, [r6, #0]
    if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 80050ec:	d11b      	bne.n	8005126 <HAL_RCC_ClockConfig+0xf2>
      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 80050ee:	f413 3f00 	tst.w	r3, #131072	; 0x20000
      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 80050f2:	d0a4      	beq.n	800503e <HAL_RCC_ClockConfig+0xa>
    __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
 80050f4:	6873      	ldr	r3, [r6, #4]
      if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
 80050f6:	f241 3888 	movw	r8, #5000	; 0x1388
    __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
 80050fa:	f023 0303 	bic.w	r3, r3, #3
 80050fe:	4313      	orrs	r3, r2
 8005100:	6073      	str	r3, [r6, #4]
    tickstart = HAL_GetTick();
 8005102:	f7ff f8d1 	bl	80042a8 <HAL_GetTick>
 8005106:	4607      	mov	r7, r0
    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
 8005108:	6873      	ldr	r3, [r6, #4]
 800510a:	6862      	ldr	r2, [r4, #4]
 800510c:	f003 030c 	and.w	r3, r3, #12
 8005110:	ebb3 0f82 	cmp.w	r3, r2, lsl #2
 8005114:	d0a1      	beq.n	800505a <HAL_RCC_ClockConfig+0x26>
      if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
 8005116:	f7ff f8c7 	bl	80042a8 <HAL_GetTick>
 800511a:	1bc0      	subs	r0, r0, r7
 800511c:	4540      	cmp	r0, r8
 800511e:	d9f3      	bls.n	8005108 <HAL_RCC_ClockConfig+0xd4>
        return HAL_TIMEOUT;
 8005120:	2003      	movs	r0, #3
}
 8005122:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
 8005126:	2a02      	cmp	r2, #2
 8005128:	d102      	bne.n	8005130 <HAL_RCC_ClockConfig+0xfc>
      if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
 800512a:	f013 7f00 	tst.w	r3, #33554432	; 0x2000000
 800512e:	e7e0      	b.n	80050f2 <HAL_RCC_ClockConfig+0xbe>
      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 8005130:	f013 0f02 	tst.w	r3, #2
 8005134:	e7dd      	b.n	80050f2 <HAL_RCC_ClockConfig+0xbe>
    __HAL_FLASH_SET_LATENCY(FLatency);
 8005136:	6813      	ldr	r3, [r2, #0]
 8005138:	f023 0307 	bic.w	r3, r3, #7
 800513c:	432b      	orrs	r3, r5
 800513e:	6013      	str	r3, [r2, #0]
    if (__HAL_FLASH_GET_LATENCY() != FLatency)
 8005140:	6813      	ldr	r3, [r2, #0]
 8005142:	f003 0307 	and.w	r3, r3, #7
 8005146:	429d      	cmp	r5, r3
 8005148:	f47f af79 	bne.w	800503e <HAL_RCC_ClockConfig+0xa>
 800514c:	e78b      	b.n	8005066 <HAL_RCC_ClockConfig+0x32>
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
 800514e:	686b      	ldr	r3, [r5, #4]
 8005150:	68e1      	ldr	r1, [r4, #12]
 8005152:	f423 63e0 	bic.w	r3, r3, #1792	; 0x700
 8005156:	430b      	orrs	r3, r1
 8005158:	606b      	str	r3, [r5, #4]
 800515a:	e789      	b.n	8005070 <HAL_RCC_ClockConfig+0x3c>
 800515c:	40022000 	.word	0x40022000
 8005160:	40021000 	.word	0x40021000
 8005164:	08007779 	.word	0x08007779
 8005168:	20000208 	.word	0x20000208
 800516c:	20000004 	.word	0x20000004

08005170 <HAL_RCC_GetPCLK1Freq>:
  return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
 8005170:	4b04      	ldr	r3, [pc, #16]	; (8005184 <HAL_RCC_GetPCLK1Freq+0x14>)
 8005172:	4a05      	ldr	r2, [pc, #20]	; (8005188 <HAL_RCC_GetPCLK1Freq+0x18>)
 8005174:	685b      	ldr	r3, [r3, #4]
 8005176:	f3c3 2302 	ubfx	r3, r3, #8, #3
 800517a:	5cd3      	ldrb	r3, [r2, r3]
 800517c:	4a03      	ldr	r2, [pc, #12]	; (800518c <HAL_RCC_GetPCLK1Freq+0x1c>)
 800517e:	6810      	ldr	r0, [r2, #0]
}
 8005180:	40d8      	lsrs	r0, r3
 8005182:	4770      	bx	lr
 8005184:	40021000 	.word	0x40021000
 8005188:	08007789 	.word	0x08007789
 800518c:	20000208 	.word	0x20000208

08005190 <HAL_RCC_GetPCLK2Freq>:
  return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
 8005190:	4b04      	ldr	r3, [pc, #16]	; (80051a4 <HAL_RCC_GetPCLK2Freq+0x14>)
 8005192:	4a05      	ldr	r2, [pc, #20]	; (80051a8 <HAL_RCC_GetPCLK2Freq+0x18>)
 8005194:	685b      	ldr	r3, [r3, #4]
 8005196:	f3c3 23c2 	ubfx	r3, r3, #11, #3
 800519a:	5cd3      	ldrb	r3, [r2, r3]
 800519c:	4a03      	ldr	r2, [pc, #12]	; (80051ac <HAL_RCC_GetPCLK2Freq+0x1c>)
 800519e:	6810      	ldr	r0, [r2, #0]
}
 80051a0:	40d8      	lsrs	r0, r3
 80051a2:	4770      	bx	lr
 80051a4:	40021000 	.word	0x40021000
 80051a8:	08007789 	.word	0x08007789
 80051ac:	20000208 	.word	0x20000208

080051b0 <HAL_RCCEx_PeriphCLKConfig>:

  /* Check the parameters */
  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));

  /*------------------------------- RTC/LCD Configuration ------------------------*/
  if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
 80051b0:	6803      	ldr	r3, [r0, #0]
{
 80051b2:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
  if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
 80051b6:	07d9      	lsls	r1, r3, #31
{
 80051b8:	4605      	mov	r5, r0
  if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
 80051ba:	d520      	bpl.n	80051fe <HAL_RCCEx_PeriphCLKConfig+0x4e>
    FlagStatus       pwrclkchanged = RESET;

    /* As soon as function is called to change RTC clock source, activation of the
       power domain is done. */
    /* Requires to enable write access to Backup Domain of necessary */
    if (__HAL_RCC_PWR_IS_CLK_DISABLED())
 80051bc:	4c35      	ldr	r4, [pc, #212]	; (8005294 <HAL_RCCEx_PeriphCLKConfig+0xe4>)
 80051be:	69e3      	ldr	r3, [r4, #28]
 80051c0:	00da      	lsls	r2, r3, #3
 80051c2:	d432      	bmi.n	800522a <HAL_RCCEx_PeriphCLKConfig+0x7a>
    {
      __HAL_RCC_PWR_CLK_ENABLE();
      pwrclkchanged = SET;
 80051c4:	2701      	movs	r7, #1
      __HAL_RCC_PWR_CLK_ENABLE();
 80051c6:	69e3      	ldr	r3, [r4, #28]
 80051c8:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
 80051cc:	61e3      	str	r3, [r4, #28]
 80051ce:	69e3      	ldr	r3, [r4, #28]
 80051d0:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 80051d4:	9301      	str	r3, [sp, #4]
 80051d6:	9b01      	ldr	r3, [sp, #4]
    }

    if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 80051d8:	4e2f      	ldr	r6, [pc, #188]	; (8005298 <HAL_RCCEx_PeriphCLKConfig+0xe8>)
 80051da:	6833      	ldr	r3, [r6, #0]
 80051dc:	05db      	lsls	r3, r3, #23
 80051de:	d526      	bpl.n	800522e <HAL_RCCEx_PeriphCLKConfig+0x7e>
        }
      }
    }

    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
    temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
 80051e0:	6a23      	ldr	r3, [r4, #32]
    if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
 80051e2:	f413 7340 	ands.w	r3, r3, #768	; 0x300
 80051e6:	d136      	bne.n	8005256 <HAL_RCCEx_PeriphCLKConfig+0xa6>
            return HAL_TIMEOUT;
          }
        }
      }
    }
    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
 80051e8:	6a23      	ldr	r3, [r4, #32]
 80051ea:	686a      	ldr	r2, [r5, #4]
 80051ec:	f423 7340 	bic.w	r3, r3, #768	; 0x300
 80051f0:	4313      	orrs	r3, r2
 80051f2:	6223      	str	r3, [r4, #32]

    /* Require to disable power clock if necessary */
    if (pwrclkchanged == SET)
 80051f4:	b11f      	cbz	r7, 80051fe <HAL_RCCEx_PeriphCLKConfig+0x4e>
    {
      __HAL_RCC_PWR_CLK_DISABLE();
 80051f6:	69e3      	ldr	r3, [r4, #28]
 80051f8:	f023 5380 	bic.w	r3, r3, #268435456	; 0x10000000
 80051fc:	61e3      	str	r3, [r4, #28]
    }
  }

  /*------------------------------ ADC clock Configuration ------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
 80051fe:	6828      	ldr	r0, [r5, #0]
 8005200:	0783      	lsls	r3, r0, #30
 8005202:	d506      	bpl.n	8005212 <HAL_RCCEx_PeriphCLKConfig+0x62>
  {
    /* Check the parameters */
    assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection));

    /* Configure the ADC clock source */
    __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
 8005204:	4a23      	ldr	r2, [pc, #140]	; (8005294 <HAL_RCCEx_PeriphCLKConfig+0xe4>)
 8005206:	68a9      	ldr	r1, [r5, #8]
 8005208:	6853      	ldr	r3, [r2, #4]
 800520a:	f423 4340 	bic.w	r3, r3, #49152	; 0xc000
 800520e:	430b      	orrs	r3, r1
 8005210:	6053      	str	r3, [r2, #4]

#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
 || defined(STM32F105xC) || defined(STM32F107xC)
  /*------------------------------ USB clock Configuration ------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
 8005212:	f010 0010 	ands.w	r0, r0, #16
 8005216:	d01b      	beq.n	8005250 <HAL_RCCEx_PeriphCLKConfig+0xa0>
  {
    /* Check the parameters */
    assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection));

    /* Configure the USB clock source */
    __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
 8005218:	4a1e      	ldr	r2, [pc, #120]	; (8005294 <HAL_RCCEx_PeriphCLKConfig+0xe4>)
 800521a:	6969      	ldr	r1, [r5, #20]
 800521c:	6853      	ldr	r3, [r2, #4]
  }
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */

  return HAL_OK;
 800521e:	2000      	movs	r0, #0
    __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
 8005220:	f423 0380 	bic.w	r3, r3, #4194304	; 0x400000
 8005224:	430b      	orrs	r3, r1
 8005226:	6053      	str	r3, [r2, #4]
 8005228:	e012      	b.n	8005250 <HAL_RCCEx_PeriphCLKConfig+0xa0>
    FlagStatus       pwrclkchanged = RESET;
 800522a:	2700      	movs	r7, #0
 800522c:	e7d4      	b.n	80051d8 <HAL_RCCEx_PeriphCLKConfig+0x28>
      SET_BIT(PWR->CR, PWR_CR_DBP);
 800522e:	6833      	ldr	r3, [r6, #0]
 8005230:	f443 7380 	orr.w	r3, r3, #256	; 0x100
 8005234:	6033      	str	r3, [r6, #0]
      tickstart = HAL_GetTick();
 8005236:	f7ff f837 	bl	80042a8 <HAL_GetTick>
 800523a:	4680      	mov	r8, r0
      while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 800523c:	6833      	ldr	r3, [r6, #0]
 800523e:	05d8      	lsls	r0, r3, #23
 8005240:	d4ce      	bmi.n	80051e0 <HAL_RCCEx_PeriphCLKConfig+0x30>
        if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
 8005242:	f7ff f831 	bl	80042a8 <HAL_GetTick>
 8005246:	eba0 0008 	sub.w	r0, r0, r8
 800524a:	2864      	cmp	r0, #100	; 0x64
 800524c:	d9f6      	bls.n	800523c <HAL_RCCEx_PeriphCLKConfig+0x8c>
          return HAL_TIMEOUT;
 800524e:	2003      	movs	r0, #3
}
 8005250:	b002      	add	sp, #8
 8005252:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
 8005256:	686a      	ldr	r2, [r5, #4]
 8005258:	f402 7240 	and.w	r2, r2, #768	; 0x300
 800525c:	4293      	cmp	r3, r2
 800525e:	d0c3      	beq.n	80051e8 <HAL_RCCEx_PeriphCLKConfig+0x38>
      __HAL_RCC_BACKUPRESET_FORCE();
 8005260:	2001      	movs	r0, #1
 8005262:	4a0e      	ldr	r2, [pc, #56]	; (800529c <HAL_RCCEx_PeriphCLKConfig+0xec>)
      temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
 8005264:	6a23      	ldr	r3, [r4, #32]
      __HAL_RCC_BACKUPRESET_FORCE();
 8005266:	6010      	str	r0, [r2, #0]
      __HAL_RCC_BACKUPRESET_RELEASE();
 8005268:	2000      	movs	r0, #0
      temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
 800526a:	f423 7140 	bic.w	r1, r3, #768	; 0x300
      __HAL_RCC_BACKUPRESET_RELEASE();
 800526e:	6010      	str	r0, [r2, #0]
      RCC->BDCR = temp_reg;
 8005270:	6221      	str	r1, [r4, #32]
      if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
 8005272:	07d9      	lsls	r1, r3, #31
 8005274:	d5b8      	bpl.n	80051e8 <HAL_RCCEx_PeriphCLKConfig+0x38>
        tickstart = HAL_GetTick();
 8005276:	f7ff f817 	bl	80042a8 <HAL_GetTick>
          if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 800527a:	f241 3888 	movw	r8, #5000	; 0x1388
        tickstart = HAL_GetTick();
 800527e:	4606      	mov	r6, r0
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
 8005280:	6a23      	ldr	r3, [r4, #32]
 8005282:	079a      	lsls	r2, r3, #30
 8005284:	d4b0      	bmi.n	80051e8 <HAL_RCCEx_PeriphCLKConfig+0x38>
          if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 8005286:	f7ff f80f 	bl	80042a8 <HAL_GetTick>
 800528a:	1b80      	subs	r0, r0, r6
 800528c:	4540      	cmp	r0, r8
 800528e:	d9f7      	bls.n	8005280 <HAL_RCCEx_PeriphCLKConfig+0xd0>
 8005290:	e7dd      	b.n	800524e <HAL_RCCEx_PeriphCLKConfig+0x9e>
 8005292:	bf00      	nop
 8005294:	40021000 	.word	0x40021000
 8005298:	40007000 	.word	0x40007000
 800529c:	42420440 	.word	0x42420440

080052a0 <HAL_TIM_Base_Start_IT>:

  /* Check the parameters */
  assert_param(IS_TIM_INSTANCE(htim->Instance));

  /* Enable the TIM Update interrupt */
  __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
 80052a0:	6803      	ldr	r3, [r0, #0]
    __HAL_TIM_ENABLE(htim);
  }

  /* Return function status */
  return HAL_OK;
}
 80052a2:	2000      	movs	r0, #0
  __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
 80052a4:	68da      	ldr	r2, [r3, #12]
 80052a6:	f042 0201 	orr.w	r2, r2, #1
 80052aa:	60da      	str	r2, [r3, #12]
  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
 80052ac:	689a      	ldr	r2, [r3, #8]
 80052ae:	f002 0207 	and.w	r2, r2, #7
  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
 80052b2:	2a06      	cmp	r2, #6
    __HAL_TIM_ENABLE(htim);
 80052b4:	bf1e      	ittt	ne
 80052b6:	681a      	ldrne	r2, [r3, #0]
 80052b8:	f042 0201 	orrne.w	r2, r2, #1
 80052bc:	601a      	strne	r2, [r3, #0]
}
 80052be:	4770      	bx	lr

080052c0 <HAL_TIM_OC_DelayElapsedCallback>:
 80052c0:	4770      	bx	lr

080052c2 <HAL_TIM_IC_CaptureCallback>:
 80052c2:	4770      	bx	lr

080052c4 <HAL_TIM_PWM_PulseFinishedCallback>:
 80052c4:	4770      	bx	lr

080052c6 <HAL_TIM_TriggerCallback>:
 80052c6:	4770      	bx	lr

080052c8 <HAL_TIM_IRQHandler>:
  * @retval None
  */
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
  /* Capture compare 1 event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
 80052c8:	6803      	ldr	r3, [r0, #0]
{
 80052ca:	b510      	push	{r4, lr}
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
 80052cc:	691a      	ldr	r2, [r3, #16]
{
 80052ce:	4604      	mov	r4, r0
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
 80052d0:	0791      	lsls	r1, r2, #30
 80052d2:	d50e      	bpl.n	80052f2 <HAL_TIM_IRQHandler+0x2a>
  {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
 80052d4:	68da      	ldr	r2, [r3, #12]
 80052d6:	0792      	lsls	r2, r2, #30
 80052d8:	d50b      	bpl.n	80052f2 <HAL_TIM_IRQHandler+0x2a>
    {
      {
        __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
 80052da:	f06f 0202 	mvn.w	r2, #2
 80052de:	611a      	str	r2, [r3, #16]
        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
 80052e0:	2201      	movs	r2, #1

        /* Input capture event */
        if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
 80052e2:	699b      	ldr	r3, [r3, #24]
        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
 80052e4:	7702      	strb	r2, [r0, #28]
        if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
 80052e6:	079b      	lsls	r3, r3, #30
 80052e8:	d077      	beq.n	80053da <HAL_TIM_IRQHandler+0x112>
        {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
          htim->IC_CaptureCallback(htim);
#else
          HAL_TIM_IC_CaptureCallback(htim);
 80052ea:	f7ff ffea 	bl	80052c2 <HAL_TIM_IC_CaptureCallback>
#else
          HAL_TIM_OC_DelayElapsedCallback(htim);
          HAL_TIM_PWM_PulseFinishedCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
        }
        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 80052ee:	2300      	movs	r3, #0
 80052f0:	7723      	strb	r3, [r4, #28]
      }
    }
  }
  /* Capture compare 2 event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
 80052f2:	6823      	ldr	r3, [r4, #0]
 80052f4:	691a      	ldr	r2, [r3, #16]
 80052f6:	0750      	lsls	r0, r2, #29
 80052f8:	d510      	bpl.n	800531c <HAL_TIM_IRQHandler+0x54>
  {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
 80052fa:	68da      	ldr	r2, [r3, #12]
 80052fc:	0751      	lsls	r1, r2, #29
 80052fe:	d50d      	bpl.n	800531c <HAL_TIM_IRQHandler+0x54>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
 8005300:	f06f 0204 	mvn.w	r2, #4
 8005304:	611a      	str	r2, [r3, #16]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
 8005306:	2202      	movs	r2, #2
      /* Input capture event */
      if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
 8005308:	699b      	ldr	r3, [r3, #24]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
 800530a:	7722      	strb	r2, [r4, #28]
      if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
 800530c:	f413 7f40 	tst.w	r3, #768	; 0x300
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->IC_CaptureCallback(htim);
#else
        HAL_TIM_IC_CaptureCallback(htim);
 8005310:	4620      	mov	r0, r4
      if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
 8005312:	d068      	beq.n	80053e6 <HAL_TIM_IRQHandler+0x11e>
        HAL_TIM_IC_CaptureCallback(htim);
 8005314:	f7ff ffd5 	bl	80052c2 <HAL_TIM_IC_CaptureCallback>
#else
        HAL_TIM_OC_DelayElapsedCallback(htim);
        HAL_TIM_PWM_PulseFinishedCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
      }
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 8005318:	2300      	movs	r3, #0
 800531a:	7723      	strb	r3, [r4, #28]
    }
  }
  /* Capture compare 3 event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
 800531c:	6823      	ldr	r3, [r4, #0]
 800531e:	691a      	ldr	r2, [r3, #16]
 8005320:	0712      	lsls	r2, r2, #28
 8005322:	d50f      	bpl.n	8005344 <HAL_TIM_IRQHandler+0x7c>
  {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
 8005324:	68da      	ldr	r2, [r3, #12]
 8005326:	0710      	lsls	r0, r2, #28
 8005328:	d50c      	bpl.n	8005344 <HAL_TIM_IRQHandler+0x7c>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
 800532a:	f06f 0208 	mvn.w	r2, #8
 800532e:	611a      	str	r2, [r3, #16]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
 8005330:	2204      	movs	r2, #4
      /* Input capture event */
      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
 8005332:	69db      	ldr	r3, [r3, #28]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
 8005334:	7722      	strb	r2, [r4, #28]
      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
 8005336:	0799      	lsls	r1, r3, #30
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->IC_CaptureCallback(htim);
#else
        HAL_TIM_IC_CaptureCallback(htim);
 8005338:	4620      	mov	r0, r4
      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
 800533a:	d05a      	beq.n	80053f2 <HAL_TIM_IRQHandler+0x12a>
        HAL_TIM_IC_CaptureCallback(htim);
 800533c:	f7ff ffc1 	bl	80052c2 <HAL_TIM_IC_CaptureCallback>
#else
        HAL_TIM_OC_DelayElapsedCallback(htim);
        HAL_TIM_PWM_PulseFinishedCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
      }
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 8005340:	2300      	movs	r3, #0
 8005342:	7723      	strb	r3, [r4, #28]
    }
  }
  /* Capture compare 4 event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
 8005344:	6823      	ldr	r3, [r4, #0]
 8005346:	691a      	ldr	r2, [r3, #16]
 8005348:	06d2      	lsls	r2, r2, #27
 800534a:	d510      	bpl.n	800536e <HAL_TIM_IRQHandler+0xa6>
  {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
 800534c:	68da      	ldr	r2, [r3, #12]
 800534e:	06d0      	lsls	r0, r2, #27
 8005350:	d50d      	bpl.n	800536e <HAL_TIM_IRQHandler+0xa6>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
 8005352:	f06f 0210 	mvn.w	r2, #16
 8005356:	611a      	str	r2, [r3, #16]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
 8005358:	2208      	movs	r2, #8
      /* Input capture event */
      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
 800535a:	69db      	ldr	r3, [r3, #28]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
 800535c:	7722      	strb	r2, [r4, #28]
      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
 800535e:	f413 7f40 	tst.w	r3, #768	; 0x300
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->IC_CaptureCallback(htim);
#else
        HAL_TIM_IC_CaptureCallback(htim);
 8005362:	4620      	mov	r0, r4
      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
 8005364:	d04b      	beq.n	80053fe <HAL_TIM_IRQHandler+0x136>
        HAL_TIM_IC_CaptureCallback(htim);
 8005366:	f7ff ffac 	bl	80052c2 <HAL_TIM_IC_CaptureCallback>
#else
        HAL_TIM_OC_DelayElapsedCallback(htim);
        HAL_TIM_PWM_PulseFinishedCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
      }
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 800536a:	2300      	movs	r3, #0
 800536c:	7723      	strb	r3, [r4, #28]
    }
  }
  /* TIM Update event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
 800536e:	6823      	ldr	r3, [r4, #0]
 8005370:	691a      	ldr	r2, [r3, #16]
 8005372:	07d1      	lsls	r1, r2, #31
 8005374:	d508      	bpl.n	8005388 <HAL_TIM_IRQHandler+0xc0>
  {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
 8005376:	68da      	ldr	r2, [r3, #12]
 8005378:	07d2      	lsls	r2, r2, #31
 800537a:	d505      	bpl.n	8005388 <HAL_TIM_IRQHandler+0xc0>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
 800537c:	f06f 0201 	mvn.w	r2, #1
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
      htim->PeriodElapsedCallback(htim);
#else
      HAL_TIM_PeriodElapsedCallback(htim);
 8005380:	4620      	mov	r0, r4
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
 8005382:	611a      	str	r2, [r3, #16]
      HAL_TIM_PeriodElapsedCallback(htim);
 8005384:	f000 fbf6 	bl	8005b74 <HAL_TIM_PeriodElapsedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
    }
  }
  /* TIM Break input event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
 8005388:	6823      	ldr	r3, [r4, #0]
 800538a:	691a      	ldr	r2, [r3, #16]
 800538c:	0610      	lsls	r0, r2, #24
 800538e:	d508      	bpl.n	80053a2 <HAL_TIM_IRQHandler+0xda>
  {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
 8005390:	68da      	ldr	r2, [r3, #12]
 8005392:	0611      	lsls	r1, r2, #24
 8005394:	d505      	bpl.n	80053a2 <HAL_TIM_IRQHandler+0xda>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
 8005396:	f06f 0280 	mvn.w	r2, #128	; 0x80
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
      htim->BreakCallback(htim);
#else
      HAL_TIMEx_BreakCallback(htim);
 800539a:	4620      	mov	r0, r4
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
 800539c:	611a      	str	r2, [r3, #16]
      HAL_TIMEx_BreakCallback(htim);
 800539e:	f000 f8ba 	bl	8005516 <HAL_TIMEx_BreakCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
    }
  }
  /* TIM Trigger detection event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
 80053a2:	6823      	ldr	r3, [r4, #0]
 80053a4:	691a      	ldr	r2, [r3, #16]
 80053a6:	0652      	lsls	r2, r2, #25
 80053a8:	d508      	bpl.n	80053bc <HAL_TIM_IRQHandler+0xf4>
  {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
 80053aa:	68da      	ldr	r2, [r3, #12]
 80053ac:	0650      	lsls	r0, r2, #25
 80053ae:	d505      	bpl.n	80053bc <HAL_TIM_IRQHandler+0xf4>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
 80053b0:	f06f 0240 	mvn.w	r2, #64	; 0x40
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
      htim->TriggerCallback(htim);
#else
      HAL_TIM_TriggerCallback(htim);
 80053b4:	4620      	mov	r0, r4
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
 80053b6:	611a      	str	r2, [r3, #16]
      HAL_TIM_TriggerCallback(htim);
 80053b8:	f7ff ff85 	bl	80052c6 <HAL_TIM_TriggerCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
    }
  }
  /* TIM commutation event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
 80053bc:	6823      	ldr	r3, [r4, #0]
 80053be:	691a      	ldr	r2, [r3, #16]
 80053c0:	0691      	lsls	r1, r2, #26
 80053c2:	d522      	bpl.n	800540a <HAL_TIM_IRQHandler+0x142>
  {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
 80053c4:	68da      	ldr	r2, [r3, #12]
 80053c6:	0692      	lsls	r2, r2, #26
 80053c8:	d51f      	bpl.n	800540a <HAL_TIM_IRQHandler+0x142>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
 80053ca:	f06f 0220 	mvn.w	r2, #32
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
      htim->CommutationCallback(htim);
#else
      HAL_TIMEx_CommutCallback(htim);
 80053ce:	4620      	mov	r0, r4
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
    }
  }
}
 80053d0:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
      __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
 80053d4:	611a      	str	r2, [r3, #16]
      HAL_TIMEx_CommutCallback(htim);
 80053d6:	f000 b89d 	b.w	8005514 <HAL_TIMEx_CommutCallback>
          HAL_TIM_OC_DelayElapsedCallback(htim);
 80053da:	f7ff ff71 	bl	80052c0 <HAL_TIM_OC_DelayElapsedCallback>
          HAL_TIM_PWM_PulseFinishedCallback(htim);
 80053de:	4620      	mov	r0, r4
 80053e0:	f7ff ff70 	bl	80052c4 <HAL_TIM_PWM_PulseFinishedCallback>
 80053e4:	e783      	b.n	80052ee <HAL_TIM_IRQHandler+0x26>
        HAL_TIM_OC_DelayElapsedCallback(htim);
 80053e6:	f7ff ff6b 	bl	80052c0 <HAL_TIM_OC_DelayElapsedCallback>
        HAL_TIM_PWM_PulseFinishedCallback(htim);
 80053ea:	4620      	mov	r0, r4
 80053ec:	f7ff ff6a 	bl	80052c4 <HAL_TIM_PWM_PulseFinishedCallback>
 80053f0:	e792      	b.n	8005318 <HAL_TIM_IRQHandler+0x50>
        HAL_TIM_OC_DelayElapsedCallback(htim);
 80053f2:	f7ff ff65 	bl	80052c0 <HAL_TIM_OC_DelayElapsedCallback>
        HAL_TIM_PWM_PulseFinishedCallback(htim);
 80053f6:	4620      	mov	r0, r4
 80053f8:	f7ff ff64 	bl	80052c4 <HAL_TIM_PWM_PulseFinishedCallback>
 80053fc:	e7a0      	b.n	8005340 <HAL_TIM_IRQHandler+0x78>
        HAL_TIM_OC_DelayElapsedCallback(htim);
 80053fe:	f7ff ff5f 	bl	80052c0 <HAL_TIM_OC_DelayElapsedCallback>
        HAL_TIM_PWM_PulseFinishedCallback(htim);
 8005402:	4620      	mov	r0, r4
 8005404:	f7ff ff5e 	bl	80052c4 <HAL_TIM_PWM_PulseFinishedCallback>
 8005408:	e7af      	b.n	800536a <HAL_TIM_IRQHandler+0xa2>
 800540a:	bd10      	pop	{r4, pc}

0800540c <TIM_Base_SetConfig>:
{
  uint32_t tmpcr1;
  tmpcr1 = TIMx->CR1;

  /* Set TIM Time Base Unit parameters ---------------------------------------*/
  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
 800540c:	4a24      	ldr	r2, [pc, #144]	; (80054a0 <TIM_Base_SetConfig+0x94>)
  tmpcr1 = TIMx->CR1;
 800540e:	6803      	ldr	r3, [r0, #0]
  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
 8005410:	4290      	cmp	r0, r2
 8005412:	d012      	beq.n	800543a <TIM_Base_SetConfig+0x2e>
 8005414:	f502 6200 	add.w	r2, r2, #2048	; 0x800
 8005418:	4290      	cmp	r0, r2
 800541a:	d00e      	beq.n	800543a <TIM_Base_SetConfig+0x2e>
 800541c:	f1b0 4f80 	cmp.w	r0, #1073741824	; 0x40000000
 8005420:	d00b      	beq.n	800543a <TIM_Base_SetConfig+0x2e>
 8005422:	f5a2 3298 	sub.w	r2, r2, #77824	; 0x13000
 8005426:	4290      	cmp	r0, r2
 8005428:	d007      	beq.n	800543a <TIM_Base_SetConfig+0x2e>
 800542a:	f502 6280 	add.w	r2, r2, #1024	; 0x400
 800542e:	4290      	cmp	r0, r2
 8005430:	d003      	beq.n	800543a <TIM_Base_SetConfig+0x2e>
 8005432:	f502 6280 	add.w	r2, r2, #1024	; 0x400
 8005436:	4290      	cmp	r0, r2
 8005438:	d11d      	bne.n	8005476 <TIM_Base_SetConfig+0x6a>
  {
    /* Select the Counter Mode */
    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
    tmpcr1 |= Structure->CounterMode;
 800543a:	684a      	ldr	r2, [r1, #4]
    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
 800543c:	f023 0370 	bic.w	r3, r3, #112	; 0x70
    tmpcr1 |= Structure->CounterMode;
 8005440:	4313      	orrs	r3, r2
  }

  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
 8005442:	4a17      	ldr	r2, [pc, #92]	; (80054a0 <TIM_Base_SetConfig+0x94>)
 8005444:	4290      	cmp	r0, r2
 8005446:	d012      	beq.n	800546e <TIM_Base_SetConfig+0x62>
 8005448:	f502 6200 	add.w	r2, r2, #2048	; 0x800
 800544c:	4290      	cmp	r0, r2
 800544e:	d00e      	beq.n	800546e <TIM_Base_SetConfig+0x62>
 8005450:	f1b0 4f80 	cmp.w	r0, #1073741824	; 0x40000000
 8005454:	d00b      	beq.n	800546e <TIM_Base_SetConfig+0x62>
 8005456:	f5a2 3298 	sub.w	r2, r2, #77824	; 0x13000
 800545a:	4290      	cmp	r0, r2
 800545c:	d007      	beq.n	800546e <TIM_Base_SetConfig+0x62>
 800545e:	f502 6280 	add.w	r2, r2, #1024	; 0x400
 8005462:	4290      	cmp	r0, r2
 8005464:	d003      	beq.n	800546e <TIM_Base_SetConfig+0x62>
 8005466:	f502 6280 	add.w	r2, r2, #1024	; 0x400
 800546a:	4290      	cmp	r0, r2
 800546c:	d103      	bne.n	8005476 <TIM_Base_SetConfig+0x6a>
  {
    /* Set the clock division */
    tmpcr1 &= ~TIM_CR1_CKD;
    tmpcr1 |= (uint32_t)Structure->ClockDivision;
 800546e:	68ca      	ldr	r2, [r1, #12]
    tmpcr1 &= ~TIM_CR1_CKD;
 8005470:	f423 7340 	bic.w	r3, r3, #768	; 0x300
    tmpcr1 |= (uint32_t)Structure->ClockDivision;
 8005474:	4313      	orrs	r3, r2
  }

  /* Set the auto-reload preload */
  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
 8005476:	694a      	ldr	r2, [r1, #20]
 8005478:	f023 0380 	bic.w	r3, r3, #128	; 0x80
 800547c:	4313      	orrs	r3, r2

  TIMx->CR1 = tmpcr1;
 800547e:	6003      	str	r3, [r0, #0]

  /* Set the Autoreload value */
  TIMx->ARR = (uint32_t)Structure->Period ;
 8005480:	688b      	ldr	r3, [r1, #8]
 8005482:	62c3      	str	r3, [r0, #44]	; 0x2c

  /* Set the Prescaler value */
  TIMx->PSC = Structure->Prescaler;
 8005484:	680b      	ldr	r3, [r1, #0]
 8005486:	6283      	str	r3, [r0, #40]	; 0x28

  if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
 8005488:	4b05      	ldr	r3, [pc, #20]	; (80054a0 <TIM_Base_SetConfig+0x94>)
 800548a:	4298      	cmp	r0, r3
 800548c:	d003      	beq.n	8005496 <TIM_Base_SetConfig+0x8a>
 800548e:	f503 6300 	add.w	r3, r3, #2048	; 0x800
 8005492:	4298      	cmp	r0, r3
 8005494:	d101      	bne.n	800549a <TIM_Base_SetConfig+0x8e>
  {
    /* Set the Repetition Counter value */
    TIMx->RCR = Structure->RepetitionCounter;
 8005496:	690b      	ldr	r3, [r1, #16]
 8005498:	6303      	str	r3, [r0, #48]	; 0x30
  }

  /* Generate an update event to reload the Prescaler
     and the repetition counter (only for advanced timer) value immediately */
  TIMx->EGR = TIM_EGR_UG;
 800549a:	2301      	movs	r3, #1
 800549c:	6143      	str	r3, [r0, #20]
 800549e:	4770      	bx	lr
 80054a0:	40012c00 	.word	0x40012c00

080054a4 <HAL_TIM_Base_Init>:
{
 80054a4:	b510      	push	{r4, lr}
  if (htim == NULL)
 80054a6:	4604      	mov	r4, r0
 80054a8:	b1a0      	cbz	r0, 80054d4 <HAL_TIM_Base_Init+0x30>
  if (htim->State == HAL_TIM_STATE_RESET)
 80054aa:	f890 303d 	ldrb.w	r3, [r0, #61]	; 0x3d
 80054ae:	f003 02ff 	and.w	r2, r3, #255	; 0xff
 80054b2:	b91b      	cbnz	r3, 80054bc <HAL_TIM_Base_Init+0x18>
    htim->Lock = HAL_UNLOCKED;
 80054b4:	f880 203c 	strb.w	r2, [r0, #60]	; 0x3c
    HAL_TIM_Base_MspInit(htim);
 80054b8:	f000 fe24 	bl	8006104 <HAL_TIM_Base_MspInit>
  htim->State = HAL_TIM_STATE_BUSY;
 80054bc:	2302      	movs	r3, #2
  TIM_Base_SetConfig(htim->Instance, &htim->Init);
 80054be:	6820      	ldr	r0, [r4, #0]
  htim->State = HAL_TIM_STATE_BUSY;
 80054c0:	f884 303d 	strb.w	r3, [r4, #61]	; 0x3d
  TIM_Base_SetConfig(htim->Instance, &htim->Init);
 80054c4:	1d21      	adds	r1, r4, #4
 80054c6:	f7ff ffa1 	bl	800540c <TIM_Base_SetConfig>
  htim->State = HAL_TIM_STATE_READY;
 80054ca:	2301      	movs	r3, #1
  return HAL_OK;
 80054cc:	2000      	movs	r0, #0
  htim->State = HAL_TIM_STATE_READY;
 80054ce:	f884 303d 	strb.w	r3, [r4, #61]	; 0x3d
  return HAL_OK;
 80054d2:	bd10      	pop	{r4, pc}
    return HAL_ERROR;
 80054d4:	2001      	movs	r0, #1
}
 80054d6:	bd10      	pop	{r4, pc}

080054d8 <HAL_TIMEx_MasterConfigSynchronization>:
  assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));
  assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
  assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));

  /* Check input state */
  __HAL_LOCK(htim);
 80054d8:	f890 303c 	ldrb.w	r3, [r0, #60]	; 0x3c
{
 80054dc:	b530      	push	{r4, r5, lr}
  __HAL_LOCK(htim);
 80054de:	2b01      	cmp	r3, #1
 80054e0:	f04f 0302 	mov.w	r3, #2
 80054e4:	d014      	beq.n	8005510 <HAL_TIMEx_MasterConfigSynchronization+0x38>

  /* Change the handler state */
  htim->State = HAL_TIM_STATE_BUSY;

  /* Get the TIMx CR2 register value */
  tmpcr2 = htim->Instance->CR2;
 80054e6:	6804      	ldr	r4, [r0, #0]
  htim->State = HAL_TIM_STATE_BUSY;
 80054e8:	f880 303d 	strb.w	r3, [r0, #61]	; 0x3d
  tmpcr2 = htim->Instance->CR2;
 80054ec:	6862      	ldr	r2, [r4, #4]

  /* Get the TIMx SMCR register value */
  tmpsmcr = htim->Instance->SMCR;
 80054ee:	68a3      	ldr	r3, [r4, #8]

  /* Reset the MMS Bits */
  tmpcr2 &= ~TIM_CR2_MMS;
  /* Select the TRGO source */
  tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
 80054f0:	680d      	ldr	r5, [r1, #0]

  /* Reset the MSM Bit */
  tmpsmcr &= ~TIM_SMCR_MSM;
  /* Set master mode */
  tmpsmcr |= sMasterConfig->MasterSlaveMode;
 80054f2:	6849      	ldr	r1, [r1, #4]
  tmpcr2 &= ~TIM_CR2_MMS;
 80054f4:	f022 0270 	bic.w	r2, r2, #112	; 0x70
  tmpsmcr &= ~TIM_SMCR_MSM;
 80054f8:	f023 0380 	bic.w	r3, r3, #128	; 0x80
  tmpsmcr |= sMasterConfig->MasterSlaveMode;
 80054fc:	430b      	orrs	r3, r1
  tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
 80054fe:	432a      	orrs	r2, r5

  /* Update TIMx CR2 */
  htim->Instance->CR2 = tmpcr2;
 8005500:	6062      	str	r2, [r4, #4]

  /* Update TIMx SMCR */
  htim->Instance->SMCR = tmpsmcr;
 8005502:	60a3      	str	r3, [r4, #8]

  /* Change the htim state */
  htim->State = HAL_TIM_STATE_READY;
 8005504:	2301      	movs	r3, #1
 8005506:	f880 303d 	strb.w	r3, [r0, #61]	; 0x3d

  __HAL_UNLOCK(htim);
 800550a:	2300      	movs	r3, #0
 800550c:	f880 303c 	strb.w	r3, [r0, #60]	; 0x3c
  __HAL_LOCK(htim);
 8005510:	4618      	mov	r0, r3

  return HAL_OK;
}
 8005512:	bd30      	pop	{r4, r5, pc}

08005514 <HAL_TIMEx_CommutCallback>:
 8005514:	4770      	bx	lr

08005516 <HAL_TIMEx_BreakCallback>:
  * @brief  Hall Break detection callback in non-blocking mode
  * @param  htim TIM handle
  * @retval None
  */
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
{
 8005516:	4770      	bx	lr

08005518 <UART_EndRxTransfer>:
  * @retval None
  */
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
{
  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
 8005518:	6803      	ldr	r3, [r0, #0]
 800551a:	68da      	ldr	r2, [r3, #12]
 800551c:	f422 7290 	bic.w	r2, r2, #288	; 0x120
 8005520:	60da      	str	r2, [r3, #12]
  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 8005522:	695a      	ldr	r2, [r3, #20]
 8005524:	f022 0201 	bic.w	r2, r2, #1
 8005528:	615a      	str	r2, [r3, #20]

  /* At end of Rx process, restore huart->RxState to Ready */
  huart->RxState = HAL_UART_STATE_READY;
 800552a:	2320      	movs	r3, #32
 800552c:	f880 303a 	strb.w	r3, [r0, #58]	; 0x3a
 8005530:	4770      	bx	lr
	...

08005534 <UART_SetConfig>:
  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
  *                the configuration information for the specified UART module.
  * @retval None
  */
static void UART_SetConfig(UART_HandleTypeDef *huart)
{
 8005534:	b538      	push	{r3, r4, r5, lr}
 8005536:	4605      	mov	r5, r0
  assert_param(IS_UART_MODE(huart->Init.Mode));

  /*-------------------------- USART CR2 Configuration -----------------------*/
  /* Configure the UART Stop Bits: Set STOP[13:12] bits
     according to huart->Init.StopBits value */
  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
 8005538:	6803      	ldr	r3, [r0, #0]
 800553a:	68c1      	ldr	r1, [r0, #12]
 800553c:	691a      	ldr	r2, [r3, #16]
 800553e:	2419      	movs	r4, #25
 8005540:	f422 5240 	bic.w	r2, r2, #12288	; 0x3000
 8005544:	430a      	orrs	r2, r1
 8005546:	611a      	str	r2, [r3, #16]
  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
  MODIFY_REG(huart->Instance->CR1,
             (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
             tmpreg);
#else
  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
 8005548:	6882      	ldr	r2, [r0, #8]
 800554a:	6900      	ldr	r0, [r0, #16]
  MODIFY_REG(huart->Instance->CR1,
 800554c:	68d9      	ldr	r1, [r3, #12]
  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
 800554e:	4302      	orrs	r2, r0
 8005550:	6968      	ldr	r0, [r5, #20]
  MODIFY_REG(huart->Instance->CR1,
 8005552:	f421 51b0 	bic.w	r1, r1, #5632	; 0x1600
 8005556:	f021 010c 	bic.w	r1, r1, #12
  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
 800555a:	4302      	orrs	r2, r0
  MODIFY_REG(huart->Instance->CR1,
 800555c:	430a      	orrs	r2, r1
 800555e:	60da      	str	r2, [r3, #12]
             tmpreg);
#endif /* USART_CR1_OVER8 */

  /*-------------------------- USART CR3 Configuration -----------------------*/
  /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
  MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
 8005560:	695a      	ldr	r2, [r3, #20]
 8005562:	69a9      	ldr	r1, [r5, #24]
 8005564:	f422 7240 	bic.w	r2, r2, #768	; 0x300
 8005568:	430a      	orrs	r2, r1
 800556a:	615a      	str	r2, [r3, #20]
      huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
    }
  }
#else
  /*-------------------------- USART BRR Configuration ---------------------*/
  if(huart->Instance == USART1)
 800556c:	4a0d      	ldr	r2, [pc, #52]	; (80055a4 <UART_SetConfig+0x70>)
 800556e:	4293      	cmp	r3, r2
 8005570:	d114      	bne.n	800559c <UART_SetConfig+0x68>
  {
    pclk = HAL_RCC_GetPCLK2Freq();
 8005572:	f7ff fe0d 	bl	8005190 <HAL_RCC_GetPCLK2Freq>
    huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
  }
  else
  {
    pclk = HAL_RCC_GetPCLK1Freq();
    huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
 8005576:	4360      	muls	r0, r4
 8005578:	686c      	ldr	r4, [r5, #4]
 800557a:	2264      	movs	r2, #100	; 0x64
 800557c:	00a4      	lsls	r4, r4, #2
 800557e:	fbb0 f0f4 	udiv	r0, r0, r4
 8005582:	fbb0 f4f2 	udiv	r4, r0, r2
 8005586:	fb02 0314 	mls	r3, r2, r4, r0
 800558a:	011b      	lsls	r3, r3, #4
 800558c:	3332      	adds	r3, #50	; 0x32
 800558e:	fbb3 f3f2 	udiv	r3, r3, r2
 8005592:	6829      	ldr	r1, [r5, #0]
 8005594:	eb03 1304 	add.w	r3, r3, r4, lsl #4
 8005598:	608b      	str	r3, [r1, #8]
 800559a:	bd38      	pop	{r3, r4, r5, pc}
    pclk = HAL_RCC_GetPCLK1Freq();
 800559c:	f7ff fde8 	bl	8005170 <HAL_RCC_GetPCLK1Freq>
 80055a0:	e7e9      	b.n	8005576 <UART_SetConfig+0x42>
 80055a2:	bf00      	nop
 80055a4:	40013800 	.word	0x40013800

080055a8 <UART_WaitOnFlagUntilTimeout.constprop.3>:
static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
 80055a8:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 80055aa:	4604      	mov	r4, r0
 80055ac:	460e      	mov	r6, r1
 80055ae:	4617      	mov	r7, r2
 80055b0:	461d      	mov	r5, r3
  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
 80055b2:	6821      	ldr	r1, [r4, #0]
 80055b4:	680b      	ldr	r3, [r1, #0]
 80055b6:	ea36 0303 	bics.w	r3, r6, r3
 80055ba:	d101      	bne.n	80055c0 <UART_WaitOnFlagUntilTimeout.constprop.3+0x18>
  return HAL_OK;
 80055bc:	2000      	movs	r0, #0
}
 80055be:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    if (Timeout != HAL_MAX_DELAY)
 80055c0:	1c6b      	adds	r3, r5, #1
 80055c2:	d0f7      	beq.n	80055b4 <UART_WaitOnFlagUntilTimeout.constprop.3+0xc>
      if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
 80055c4:	b995      	cbnz	r5, 80055ec <UART_WaitOnFlagUntilTimeout.constprop.3+0x44>
        CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
 80055c6:	6823      	ldr	r3, [r4, #0]
        __HAL_UNLOCK(huart);
 80055c8:	2003      	movs	r0, #3
        CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
 80055ca:	68da      	ldr	r2, [r3, #12]
 80055cc:	f422 72d0 	bic.w	r2, r2, #416	; 0x1a0
 80055d0:	60da      	str	r2, [r3, #12]
        CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 80055d2:	695a      	ldr	r2, [r3, #20]
 80055d4:	f022 0201 	bic.w	r2, r2, #1
 80055d8:	615a      	str	r2, [r3, #20]
        huart->gState  = HAL_UART_STATE_READY;
 80055da:	2320      	movs	r3, #32
 80055dc:	f884 3039 	strb.w	r3, [r4, #57]	; 0x39
        huart->RxState = HAL_UART_STATE_READY;
 80055e0:	f884 303a 	strb.w	r3, [r4, #58]	; 0x3a
        __HAL_UNLOCK(huart);
 80055e4:	2300      	movs	r3, #0
 80055e6:	f884 3038 	strb.w	r3, [r4, #56]	; 0x38
 80055ea:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
      if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
 80055ec:	f7fe fe5c 	bl	80042a8 <HAL_GetTick>
 80055f0:	1bc0      	subs	r0, r0, r7
 80055f2:	4285      	cmp	r5, r0
 80055f4:	d2dd      	bcs.n	80055b2 <UART_WaitOnFlagUntilTimeout.constprop.3+0xa>
 80055f6:	e7e6      	b.n	80055c6 <UART_WaitOnFlagUntilTimeout.constprop.3+0x1e>

080055f8 <HAL_UART_Init>:
{
 80055f8:	b510      	push	{r4, lr}
  if (huart == NULL)
 80055fa:	4604      	mov	r4, r0
 80055fc:	b340      	cbz	r0, 8005650 <HAL_UART_Init+0x58>
  if (huart->gState == HAL_UART_STATE_RESET)
 80055fe:	f890 3039 	ldrb.w	r3, [r0, #57]	; 0x39
 8005602:	f003 02ff 	and.w	r2, r3, #255	; 0xff
 8005606:	b91b      	cbnz	r3, 8005610 <HAL_UART_Init+0x18>
    huart->Lock = HAL_UNLOCKED;
 8005608:	f880 2038 	strb.w	r2, [r0, #56]	; 0x38
    HAL_UART_MspInit(huart);
 800560c:	f000 fd8e 	bl	800612c <HAL_UART_MspInit>
  huart->gState = HAL_UART_STATE_BUSY;
 8005610:	2324      	movs	r3, #36	; 0x24
  __HAL_UART_DISABLE(huart);
 8005612:	6822      	ldr	r2, [r4, #0]
  huart->gState = HAL_UART_STATE_BUSY;
 8005614:	f884 3039 	strb.w	r3, [r4, #57]	; 0x39
  __HAL_UART_DISABLE(huart);
 8005618:	68d3      	ldr	r3, [r2, #12]
  UART_SetConfig(huart);
 800561a:	4620      	mov	r0, r4
  __HAL_UART_DISABLE(huart);
 800561c:	f423 5300 	bic.w	r3, r3, #8192	; 0x2000
 8005620:	60d3      	str	r3, [r2, #12]
  UART_SetConfig(huart);
 8005622:	f7ff ff87 	bl	8005534 <UART_SetConfig>
  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
 8005626:	6823      	ldr	r3, [r4, #0]
  huart->ErrorCode = HAL_UART_ERROR_NONE;
 8005628:	2000      	movs	r0, #0
  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
 800562a:	691a      	ldr	r2, [r3, #16]
 800562c:	f422 4290 	bic.w	r2, r2, #18432	; 0x4800
 8005630:	611a      	str	r2, [r3, #16]
  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
 8005632:	695a      	ldr	r2, [r3, #20]
 8005634:	f022 022a 	bic.w	r2, r2, #42	; 0x2a
 8005638:	615a      	str	r2, [r3, #20]
  __HAL_UART_ENABLE(huart);
 800563a:	68da      	ldr	r2, [r3, #12]
 800563c:	f442 5200 	orr.w	r2, r2, #8192	; 0x2000
 8005640:	60da      	str	r2, [r3, #12]
  huart->gState = HAL_UART_STATE_READY;
 8005642:	2320      	movs	r3, #32
  huart->ErrorCode = HAL_UART_ERROR_NONE;
 8005644:	63e0      	str	r0, [r4, #60]	; 0x3c
  huart->gState = HAL_UART_STATE_READY;
 8005646:	f884 3039 	strb.w	r3, [r4, #57]	; 0x39
  huart->RxState = HAL_UART_STATE_READY;
 800564a:	f884 303a 	strb.w	r3, [r4, #58]	; 0x3a
  return HAL_OK;
 800564e:	bd10      	pop	{r4, pc}
    return HAL_ERROR;
 8005650:	2001      	movs	r0, #1
}
 8005652:	bd10      	pop	{r4, pc}

08005654 <HAL_UART_Transmit>:
{
 8005654:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
 8005658:	461f      	mov	r7, r3
  if (huart->gState == HAL_UART_STATE_READY)
 800565a:	f890 3039 	ldrb.w	r3, [r0, #57]	; 0x39
{
 800565e:	4604      	mov	r4, r0
  if (huart->gState == HAL_UART_STATE_READY)
 8005660:	2b20      	cmp	r3, #32
{
 8005662:	460d      	mov	r5, r1
 8005664:	4690      	mov	r8, r2
  if (huart->gState == HAL_UART_STATE_READY)
 8005666:	d14e      	bne.n	8005706 <HAL_UART_Transmit+0xb2>
    if ((pData == NULL) || (Size == 0U))
 8005668:	2900      	cmp	r1, #0
 800566a:	d049      	beq.n	8005700 <HAL_UART_Transmit+0xac>
 800566c:	2a00      	cmp	r2, #0
 800566e:	d047      	beq.n	8005700 <HAL_UART_Transmit+0xac>
    __HAL_LOCK(huart);
 8005670:	f890 3038 	ldrb.w	r3, [r0, #56]	; 0x38
 8005674:	2b01      	cmp	r3, #1
 8005676:	d046      	beq.n	8005706 <HAL_UART_Transmit+0xb2>
 8005678:	2301      	movs	r3, #1
 800567a:	f880 3038 	strb.w	r3, [r0, #56]	; 0x38
    huart->ErrorCode = HAL_UART_ERROR_NONE;
 800567e:	2300      	movs	r3, #0
 8005680:	63c3      	str	r3, [r0, #60]	; 0x3c
    huart->gState = HAL_UART_STATE_BUSY_TX;
 8005682:	2321      	movs	r3, #33	; 0x21
 8005684:	f880 3039 	strb.w	r3, [r0, #57]	; 0x39
    tickstart = HAL_GetTick();
 8005688:	f7fe fe0e 	bl	80042a8 <HAL_GetTick>
 800568c:	4606      	mov	r6, r0
    huart->TxXferSize = Size;
 800568e:	f8a4 8024 	strh.w	r8, [r4, #36]	; 0x24
    huart->TxXferCount = Size;
 8005692:	f8a4 8026 	strh.w	r8, [r4, #38]	; 0x26
    while (huart->TxXferCount > 0U)
 8005696:	8ce3      	ldrh	r3, [r4, #38]	; 0x26
 8005698:	b29b      	uxth	r3, r3
 800569a:	b96b      	cbnz	r3, 80056b8 <HAL_UART_Transmit+0x64>
    if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
 800569c:	463b      	mov	r3, r7
 800569e:	4632      	mov	r2, r6
 80056a0:	2140      	movs	r1, #64	; 0x40
 80056a2:	4620      	mov	r0, r4
 80056a4:	f7ff ff80 	bl	80055a8 <UART_WaitOnFlagUntilTimeout.constprop.3>
 80056a8:	b9a8      	cbnz	r0, 80056d6 <HAL_UART_Transmit+0x82>
    huart->gState = HAL_UART_STATE_READY;
 80056aa:	2320      	movs	r3, #32
    __HAL_UNLOCK(huart);
 80056ac:	f884 0038 	strb.w	r0, [r4, #56]	; 0x38
    huart->gState = HAL_UART_STATE_READY;
 80056b0:	f884 3039 	strb.w	r3, [r4, #57]	; 0x39
    return HAL_OK;
 80056b4:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
      huart->TxXferCount--;
 80056b8:	8ce3      	ldrh	r3, [r4, #38]	; 0x26
        if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
 80056ba:	4632      	mov	r2, r6
      huart->TxXferCount--;
 80056bc:	3b01      	subs	r3, #1
 80056be:	b29b      	uxth	r3, r3
 80056c0:	84e3      	strh	r3, [r4, #38]	; 0x26
      if (huart->Init.WordLength == UART_WORDLENGTH_9B)
 80056c2:	68a3      	ldr	r3, [r4, #8]
        if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
 80056c4:	2180      	movs	r1, #128	; 0x80
      if (huart->Init.WordLength == UART_WORDLENGTH_9B)
 80056c6:	f5b3 5f80 	cmp.w	r3, #4096	; 0x1000
        if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
 80056ca:	4620      	mov	r0, r4
 80056cc:	463b      	mov	r3, r7
      if (huart->Init.WordLength == UART_WORDLENGTH_9B)
 80056ce:	d10e      	bne.n	80056ee <HAL_UART_Transmit+0x9a>
        if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
 80056d0:	f7ff ff6a 	bl	80055a8 <UART_WaitOnFlagUntilTimeout.constprop.3>
 80056d4:	b110      	cbz	r0, 80056dc <HAL_UART_Transmit+0x88>
          return HAL_TIMEOUT;
 80056d6:	2003      	movs	r0, #3
 80056d8:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
        huart->Instance->DR = (*tmp & (uint16_t)0x01FF);
 80056dc:	882b      	ldrh	r3, [r5, #0]
 80056de:	6822      	ldr	r2, [r4, #0]
 80056e0:	f3c3 0308 	ubfx	r3, r3, #0, #9
 80056e4:	6053      	str	r3, [r2, #4]
        if (huart->Init.Parity == UART_PARITY_NONE)
 80056e6:	6923      	ldr	r3, [r4, #16]
 80056e8:	b943      	cbnz	r3, 80056fc <HAL_UART_Transmit+0xa8>
          pData += 2U;
 80056ea:	3502      	adds	r5, #2
 80056ec:	e7d3      	b.n	8005696 <HAL_UART_Transmit+0x42>
        if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
 80056ee:	f7ff ff5b 	bl	80055a8 <UART_WaitOnFlagUntilTimeout.constprop.3>
 80056f2:	2800      	cmp	r0, #0
 80056f4:	d1ef      	bne.n	80056d6 <HAL_UART_Transmit+0x82>
        huart->Instance->DR = (*pData++ & (uint8_t)0xFF);
 80056f6:	6823      	ldr	r3, [r4, #0]
 80056f8:	782a      	ldrb	r2, [r5, #0]
 80056fa:	605a      	str	r2, [r3, #4]
 80056fc:	3501      	adds	r5, #1
 80056fe:	e7ca      	b.n	8005696 <HAL_UART_Transmit+0x42>
      return  HAL_ERROR;
 8005700:	2001      	movs	r0, #1
 8005702:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    return HAL_BUSY;
 8005706:	2002      	movs	r0, #2
}
 8005708:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

0800570c <HAL_UART_Transmit_DMA>:
{
 800570c:	b538      	push	{r3, r4, r5, lr}
 800570e:	4604      	mov	r4, r0
 8005710:	4613      	mov	r3, r2
  if (huart->gState == HAL_UART_STATE_READY)
 8005712:	f894 2039 	ldrb.w	r2, [r4, #57]	; 0x39
 8005716:	2a20      	cmp	r2, #32
 8005718:	d12a      	bne.n	8005770 <HAL_UART_Transmit_DMA+0x64>
    if ((pData == NULL) || (Size == 0U))
 800571a:	b339      	cbz	r1, 800576c <HAL_UART_Transmit_DMA+0x60>
 800571c:	b333      	cbz	r3, 800576c <HAL_UART_Transmit_DMA+0x60>
    __HAL_LOCK(huart);
 800571e:	f894 2038 	ldrb.w	r2, [r4, #56]	; 0x38
 8005722:	2a01      	cmp	r2, #1
 8005724:	d024      	beq.n	8005770 <HAL_UART_Transmit_DMA+0x64>
 8005726:	2201      	movs	r2, #1
    huart->ErrorCode = HAL_UART_ERROR_NONE;
 8005728:	2500      	movs	r5, #0
    __HAL_LOCK(huart);
 800572a:	f884 2038 	strb.w	r2, [r4, #56]	; 0x38
    huart->gState = HAL_UART_STATE_BUSY_TX;
 800572e:	2221      	movs	r2, #33	; 0x21
    huart->TxXferCount = Size;
 8005730:	84e3      	strh	r3, [r4, #38]	; 0x26
    huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
 8005732:	6b20      	ldr	r0, [r4, #48]	; 0x30
    huart->ErrorCode = HAL_UART_ERROR_NONE;
 8005734:	63e5      	str	r5, [r4, #60]	; 0x3c
    huart->gState = HAL_UART_STATE_BUSY_TX;
 8005736:	f884 2039 	strb.w	r2, [r4, #57]	; 0x39
    huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
 800573a:	4a0e      	ldr	r2, [pc, #56]	; (8005774 <HAL_UART_Transmit_DMA+0x68>)
    huart->TxXferSize = Size;
 800573c:	84a3      	strh	r3, [r4, #36]	; 0x24
    huart->pTxBuffPtr = pData;
 800573e:	6221      	str	r1, [r4, #32]
    huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
 8005740:	6282      	str	r2, [r0, #40]	; 0x28
    huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
 8005742:	4a0d      	ldr	r2, [pc, #52]	; (8005778 <HAL_UART_Transmit_DMA+0x6c>)
    huart->hdmatx->XferAbortCallback = NULL;
 8005744:	6345      	str	r5, [r0, #52]	; 0x34
    huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
 8005746:	62c2      	str	r2, [r0, #44]	; 0x2c
    huart->hdmatx->XferErrorCallback = UART_DMAError;
 8005748:	4a0c      	ldr	r2, [pc, #48]	; (800577c <HAL_UART_Transmit_DMA+0x70>)
 800574a:	6302      	str	r2, [r0, #48]	; 0x30
    HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t *)tmp, (uint32_t)&huart->Instance->DR, Size);
 800574c:	6822      	ldr	r2, [r4, #0]
 800574e:	3204      	adds	r2, #4
 8005750:	f7ff f816 	bl	8004780 <HAL_DMA_Start_IT>
    __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
 8005754:	f06f 0240 	mvn.w	r2, #64	; 0x40
 8005758:	6823      	ldr	r3, [r4, #0]
    return HAL_OK;
 800575a:	4628      	mov	r0, r5
    __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
 800575c:	601a      	str	r2, [r3, #0]
    SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
 800575e:	695a      	ldr	r2, [r3, #20]
    __HAL_UNLOCK(huart);
 8005760:	f884 5038 	strb.w	r5, [r4, #56]	; 0x38
    SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
 8005764:	f042 0280 	orr.w	r2, r2, #128	; 0x80
 8005768:	615a      	str	r2, [r3, #20]
    return HAL_OK;
 800576a:	bd38      	pop	{r3, r4, r5, pc}
      return HAL_ERROR;
 800576c:	2001      	movs	r0, #1
 800576e:	bd38      	pop	{r3, r4, r5, pc}
    return HAL_BUSY;
 8005770:	2002      	movs	r0, #2
}
 8005772:	bd38      	pop	{r3, r4, r5, pc}
 8005774:	08005813 	.word	0x08005813
 8005778:	08005841 	.word	0x08005841
 800577c:	0800590d 	.word	0x0800590d

08005780 <HAL_UART_Receive_DMA>:
{
 8005780:	4613      	mov	r3, r2
  if (huart->RxState == HAL_UART_STATE_READY)
 8005782:	f890 203a 	ldrb.w	r2, [r0, #58]	; 0x3a
{
 8005786:	b573      	push	{r0, r1, r4, r5, r6, lr}
  if (huart->RxState == HAL_UART_STATE_READY)
 8005788:	2a20      	cmp	r2, #32
{
 800578a:	4605      	mov	r5, r0
  if (huart->RxState == HAL_UART_STATE_READY)
 800578c:	d138      	bne.n	8005800 <HAL_UART_Receive_DMA+0x80>
    if ((pData == NULL) || (Size == 0U))
 800578e:	2900      	cmp	r1, #0
 8005790:	d034      	beq.n	80057fc <HAL_UART_Receive_DMA+0x7c>
 8005792:	2b00      	cmp	r3, #0
 8005794:	d032      	beq.n	80057fc <HAL_UART_Receive_DMA+0x7c>
    __HAL_LOCK(huart);
 8005796:	f890 2038 	ldrb.w	r2, [r0, #56]	; 0x38
 800579a:	2a01      	cmp	r2, #1
 800579c:	d030      	beq.n	8005800 <HAL_UART_Receive_DMA+0x80>
 800579e:	2201      	movs	r2, #1
    huart->ErrorCode = HAL_UART_ERROR_NONE;
 80057a0:	2400      	movs	r4, #0
    __HAL_LOCK(huart);
 80057a2:	f880 2038 	strb.w	r2, [r0, #56]	; 0x38
    huart->RxState = HAL_UART_STATE_BUSY_RX;
 80057a6:	2222      	movs	r2, #34	; 0x22
    huart->pRxBuffPtr = pData;
 80057a8:	6281      	str	r1, [r0, #40]	; 0x28
    huart->RxXferSize = Size;
 80057aa:	8583      	strh	r3, [r0, #44]	; 0x2c
    huart->ErrorCode = HAL_UART_ERROR_NONE;
 80057ac:	63c4      	str	r4, [r0, #60]	; 0x3c
    huart->RxState = HAL_UART_STATE_BUSY_RX;
 80057ae:	f880 203a 	strb.w	r2, [r0, #58]	; 0x3a
    huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
 80057b2:	6b40      	ldr	r0, [r0, #52]	; 0x34
 80057b4:	4a13      	ldr	r2, [pc, #76]	; (8005804 <HAL_UART_Receive_DMA+0x84>)
    HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t *)tmp, Size);
 80057b6:	682e      	ldr	r6, [r5, #0]
    huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
 80057b8:	6282      	str	r2, [r0, #40]	; 0x28
    huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
 80057ba:	4a13      	ldr	r2, [pc, #76]	; (8005808 <HAL_UART_Receive_DMA+0x88>)
    huart->hdmarx->XferAbortCallback = NULL;
 80057bc:	6344      	str	r4, [r0, #52]	; 0x34
    huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
 80057be:	62c2      	str	r2, [r0, #44]	; 0x2c
    huart->hdmarx->XferErrorCallback = UART_DMAError;
 80057c0:	4a12      	ldr	r2, [pc, #72]	; (800580c <HAL_UART_Receive_DMA+0x8c>)
 80057c2:	6302      	str	r2, [r0, #48]	; 0x30
    HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t *)tmp, Size);
 80057c4:	460a      	mov	r2, r1
 80057c6:	1d31      	adds	r1, r6, #4
 80057c8:	f7fe ffda 	bl	8004780 <HAL_DMA_Start_IT>
    return HAL_OK;
 80057cc:	4620      	mov	r0, r4
    __HAL_UART_CLEAR_OREFLAG(huart);
 80057ce:	682b      	ldr	r3, [r5, #0]
 80057d0:	9401      	str	r4, [sp, #4]
 80057d2:	681a      	ldr	r2, [r3, #0]
 80057d4:	9201      	str	r2, [sp, #4]
 80057d6:	685a      	ldr	r2, [r3, #4]
    __HAL_UNLOCK(huart);
 80057d8:	f885 4038 	strb.w	r4, [r5, #56]	; 0x38
    __HAL_UART_CLEAR_OREFLAG(huart);
 80057dc:	9201      	str	r2, [sp, #4]
 80057de:	9a01      	ldr	r2, [sp, #4]
    SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
 80057e0:	68da      	ldr	r2, [r3, #12]
 80057e2:	f442 7280 	orr.w	r2, r2, #256	; 0x100
 80057e6:	60da      	str	r2, [r3, #12]
    SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
 80057e8:	695a      	ldr	r2, [r3, #20]
 80057ea:	f042 0201 	orr.w	r2, r2, #1
 80057ee:	615a      	str	r2, [r3, #20]
    SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
 80057f0:	695a      	ldr	r2, [r3, #20]
 80057f2:	f042 0240 	orr.w	r2, r2, #64	; 0x40
 80057f6:	615a      	str	r2, [r3, #20]
}
 80057f8:	b002      	add	sp, #8
 80057fa:	bd70      	pop	{r4, r5, r6, pc}
      return HAL_ERROR;
 80057fc:	2001      	movs	r0, #1
 80057fe:	e7fb      	b.n	80057f8 <HAL_UART_Receive_DMA+0x78>
    return HAL_BUSY;
 8005800:	2002      	movs	r0, #2
 8005802:	e7f9      	b.n	80057f8 <HAL_UART_Receive_DMA+0x78>
 8005804:	0800584b 	.word	0x0800584b
 8005808:	08005901 	.word	0x08005901
 800580c:	0800590d 	.word	0x0800590d

08005810 <HAL_UART_TxCpltCallback>:
 8005810:	4770      	bx	lr

08005812 <UART_DMATransmitCplt>:
{
 8005812:	b508      	push	{r3, lr}
  if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
 8005814:	6803      	ldr	r3, [r0, #0]
  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 8005816:	6a42      	ldr	r2, [r0, #36]	; 0x24
  if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
 8005818:	681b      	ldr	r3, [r3, #0]
 800581a:	f013 0320 	ands.w	r3, r3, #32
 800581e:	d10a      	bne.n	8005836 <UART_DMATransmitCplt+0x24>
    huart->TxXferCount = 0x00U;
 8005820:	84d3      	strh	r3, [r2, #38]	; 0x26
    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
 8005822:	6813      	ldr	r3, [r2, #0]
 8005824:	695a      	ldr	r2, [r3, #20]
 8005826:	f022 0280 	bic.w	r2, r2, #128	; 0x80
 800582a:	615a      	str	r2, [r3, #20]
    SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
 800582c:	68da      	ldr	r2, [r3, #12]
 800582e:	f042 0240 	orr.w	r2, r2, #64	; 0x40
 8005832:	60da      	str	r2, [r3, #12]
 8005834:	bd08      	pop	{r3, pc}
    HAL_UART_TxCpltCallback(huart);
 8005836:	4610      	mov	r0, r2
 8005838:	f7ff ffea 	bl	8005810 <HAL_UART_TxCpltCallback>
 800583c:	bd08      	pop	{r3, pc}

0800583e <HAL_UART_TxHalfCpltCallback>:
 800583e:	4770      	bx	lr

08005840 <UART_DMATxHalfCplt>:
{
 8005840:	b508      	push	{r3, lr}
  HAL_UART_TxHalfCpltCallback(huart);
 8005842:	6a40      	ldr	r0, [r0, #36]	; 0x24
 8005844:	f7ff fffb 	bl	800583e <HAL_UART_TxHalfCpltCallback>
 8005848:	bd08      	pop	{r3, pc}

0800584a <UART_DMAReceiveCplt>:
{
 800584a:	b508      	push	{r3, lr}
  if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
 800584c:	6803      	ldr	r3, [r0, #0]
  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 800584e:	6a42      	ldr	r2, [r0, #36]	; 0x24
  if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
 8005850:	681b      	ldr	r3, [r3, #0]
 8005852:	f013 0320 	ands.w	r3, r3, #32
 8005856:	d110      	bne.n	800587a <UART_DMAReceiveCplt+0x30>
    huart->RxXferCount = 0U;
 8005858:	85d3      	strh	r3, [r2, #46]	; 0x2e
    CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
 800585a:	6813      	ldr	r3, [r2, #0]
 800585c:	68d9      	ldr	r1, [r3, #12]
 800585e:	f421 7180 	bic.w	r1, r1, #256	; 0x100
 8005862:	60d9      	str	r1, [r3, #12]
    CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 8005864:	6959      	ldr	r1, [r3, #20]
 8005866:	f021 0101 	bic.w	r1, r1, #1
 800586a:	6159      	str	r1, [r3, #20]
    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
 800586c:	6959      	ldr	r1, [r3, #20]
 800586e:	f021 0140 	bic.w	r1, r1, #64	; 0x40
 8005872:	6159      	str	r1, [r3, #20]
    huart->RxState = HAL_UART_STATE_READY;
 8005874:	2320      	movs	r3, #32
 8005876:	f882 303a 	strb.w	r3, [r2, #58]	; 0x3a
  HAL_UART_RxCpltCallback(huart);
 800587a:	4610      	mov	r0, r2
 800587c:	f000 fe1a 	bl	80064b4 <HAL_UART_RxCpltCallback>
 8005880:	bd08      	pop	{r3, pc}

08005882 <UART_Receive_IT>:
  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
 8005882:	f890 303a 	ldrb.w	r3, [r0, #58]	; 0x3a
{
 8005886:	b510      	push	{r4, lr}
  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
 8005888:	2b22      	cmp	r3, #34	; 0x22
 800588a:	d136      	bne.n	80058fa <UART_Receive_IT+0x78>
    if (huart->Init.WordLength == UART_WORDLENGTH_9B)
 800588c:	6883      	ldr	r3, [r0, #8]
 800588e:	6901      	ldr	r1, [r0, #16]
 8005890:	f5b3 5f80 	cmp.w	r3, #4096	; 0x1000
 8005894:	6802      	ldr	r2, [r0, #0]
 8005896:	6a83      	ldr	r3, [r0, #40]	; 0x28
 8005898:	d123      	bne.n	80058e2 <UART_Receive_IT+0x60>
        *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
 800589a:	6852      	ldr	r2, [r2, #4]
      if (huart->Init.Parity == UART_PARITY_NONE)
 800589c:	b9e9      	cbnz	r1, 80058da <UART_Receive_IT+0x58>
        *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
 800589e:	f3c2 0208 	ubfx	r2, r2, #0, #9
 80058a2:	f823 2b02 	strh.w	r2, [r3], #2
        huart->pRxBuffPtr += 1U;
 80058a6:	6283      	str	r3, [r0, #40]	; 0x28
    if (--huart->RxXferCount == 0U)
 80058a8:	8dc4      	ldrh	r4, [r0, #46]	; 0x2e
 80058aa:	3c01      	subs	r4, #1
 80058ac:	b2a4      	uxth	r4, r4
 80058ae:	85c4      	strh	r4, [r0, #46]	; 0x2e
 80058b0:	b98c      	cbnz	r4, 80058d6 <UART_Receive_IT+0x54>
      __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
 80058b2:	6803      	ldr	r3, [r0, #0]
 80058b4:	68da      	ldr	r2, [r3, #12]
 80058b6:	f022 0220 	bic.w	r2, r2, #32
 80058ba:	60da      	str	r2, [r3, #12]
      __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
 80058bc:	68da      	ldr	r2, [r3, #12]
 80058be:	f422 7280 	bic.w	r2, r2, #256	; 0x100
 80058c2:	60da      	str	r2, [r3, #12]
      __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
 80058c4:	695a      	ldr	r2, [r3, #20]
 80058c6:	f022 0201 	bic.w	r2, r2, #1
 80058ca:	615a      	str	r2, [r3, #20]
      huart->RxState = HAL_UART_STATE_READY;
 80058cc:	2320      	movs	r3, #32
 80058ce:	f880 303a 	strb.w	r3, [r0, #58]	; 0x3a
      HAL_UART_RxCpltCallback(huart);
 80058d2:	f000 fdef 	bl	80064b4 <HAL_UART_RxCpltCallback>
    if (--huart->RxXferCount == 0U)
 80058d6:	2000      	movs	r0, #0
}
 80058d8:	bd10      	pop	{r4, pc}
        *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF);
 80058da:	b2d2      	uxtb	r2, r2
 80058dc:	f823 2b01 	strh.w	r2, [r3], #1
 80058e0:	e7e1      	b.n	80058a6 <UART_Receive_IT+0x24>
      if (huart->Init.Parity == UART_PARITY_NONE)
 80058e2:	b921      	cbnz	r1, 80058ee <UART_Receive_IT+0x6c>
        *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
 80058e4:	1c59      	adds	r1, r3, #1
 80058e6:	6852      	ldr	r2, [r2, #4]
 80058e8:	6281      	str	r1, [r0, #40]	; 0x28
        *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
 80058ea:	701a      	strb	r2, [r3, #0]
 80058ec:	e7dc      	b.n	80058a8 <UART_Receive_IT+0x26>
 80058ee:	6852      	ldr	r2, [r2, #4]
 80058f0:	1c59      	adds	r1, r3, #1
 80058f2:	6281      	str	r1, [r0, #40]	; 0x28
 80058f4:	f002 027f 	and.w	r2, r2, #127	; 0x7f
 80058f8:	e7f7      	b.n	80058ea <UART_Receive_IT+0x68>
    return HAL_BUSY;
 80058fa:	2002      	movs	r0, #2
 80058fc:	bd10      	pop	{r4, pc}

080058fe <HAL_UART_RxHalfCpltCallback>:
 80058fe:	4770      	bx	lr

08005900 <UART_DMARxHalfCplt>:
{
 8005900:	b508      	push	{r3, lr}
  HAL_UART_RxHalfCpltCallback(huart);
 8005902:	6a40      	ldr	r0, [r0, #36]	; 0x24
 8005904:	f7ff fffb 	bl	80058fe <HAL_UART_RxHalfCpltCallback>
 8005908:	bd08      	pop	{r3, pc}

0800590a <HAL_UART_ErrorCallback>:
 800590a:	4770      	bx	lr

0800590c <UART_DMAError>:
  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 800590c:	6a41      	ldr	r1, [r0, #36]	; 0x24
{
 800590e:	b508      	push	{r3, lr}
  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
 8005910:	680b      	ldr	r3, [r1, #0]
 8005912:	695a      	ldr	r2, [r3, #20]
  if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
 8005914:	f891 0039 	ldrb.w	r0, [r1, #57]	; 0x39
 8005918:	2821      	cmp	r0, #33	; 0x21
 800591a:	d10a      	bne.n	8005932 <UART_DMAError+0x26>
 800591c:	0612      	lsls	r2, r2, #24
 800591e:	d508      	bpl.n	8005932 <UART_DMAError+0x26>
    huart->TxXferCount = 0x00U;
 8005920:	2200      	movs	r2, #0
 8005922:	84ca      	strh	r2, [r1, #38]	; 0x26
  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
 8005924:	68da      	ldr	r2, [r3, #12]
 8005926:	f022 02c0 	bic.w	r2, r2, #192	; 0xc0
 800592a:	60da      	str	r2, [r3, #12]
  huart->gState = HAL_UART_STATE_READY;
 800592c:	2220      	movs	r2, #32
 800592e:	f881 2039 	strb.w	r2, [r1, #57]	; 0x39
  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
 8005932:	695b      	ldr	r3, [r3, #20]
  if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
 8005934:	f891 203a 	ldrb.w	r2, [r1, #58]	; 0x3a
 8005938:	2a22      	cmp	r2, #34	; 0x22
 800593a:	d106      	bne.n	800594a <UART_DMAError+0x3e>
 800593c:	065b      	lsls	r3, r3, #25
 800593e:	d504      	bpl.n	800594a <UART_DMAError+0x3e>
    huart->RxXferCount = 0x00U;
 8005940:	2300      	movs	r3, #0
    UART_EndRxTransfer(huart);
 8005942:	4608      	mov	r0, r1
    huart->RxXferCount = 0x00U;
 8005944:	85cb      	strh	r3, [r1, #46]	; 0x2e
    UART_EndRxTransfer(huart);
 8005946:	f7ff fde7 	bl	8005518 <UART_EndRxTransfer>
  huart->ErrorCode |= HAL_UART_ERROR_DMA;
 800594a:	6bcb      	ldr	r3, [r1, #60]	; 0x3c
  HAL_UART_ErrorCallback(huart);
 800594c:	4608      	mov	r0, r1
  huart->ErrorCode |= HAL_UART_ERROR_DMA;
 800594e:	f043 0310 	orr.w	r3, r3, #16
 8005952:	63cb      	str	r3, [r1, #60]	; 0x3c
  HAL_UART_ErrorCallback(huart);
 8005954:	f7ff ffd9 	bl	800590a <HAL_UART_ErrorCallback>
 8005958:	bd08      	pop	{r3, pc}
	...

0800595c <HAL_UART_IRQHandler>:
  uint32_t isrflags   = READ_REG(huart->Instance->SR);
 800595c:	6803      	ldr	r3, [r0, #0]
{
 800595e:	b570      	push	{r4, r5, r6, lr}
  uint32_t isrflags   = READ_REG(huart->Instance->SR);
 8005960:	681a      	ldr	r2, [r3, #0]
{
 8005962:	4604      	mov	r4, r0
  if (errorflags == RESET)
 8005964:	0716      	lsls	r6, r2, #28
  uint32_t cr1its     = READ_REG(huart->Instance->CR1);
 8005966:	68d9      	ldr	r1, [r3, #12]
  uint32_t cr3its     = READ_REG(huart->Instance->CR3);
 8005968:	695d      	ldr	r5, [r3, #20]
  if (errorflags == RESET)
 800596a:	d107      	bne.n	800597c <HAL_UART_IRQHandler+0x20>
    if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
 800596c:	0696      	lsls	r6, r2, #26
 800596e:	d55a      	bpl.n	8005a26 <HAL_UART_IRQHandler+0xca>
 8005970:	068d      	lsls	r5, r1, #26
 8005972:	d558      	bpl.n	8005a26 <HAL_UART_IRQHandler+0xca>
}
 8005974:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
      UART_Receive_IT(huart);
 8005978:	f7ff bf83 	b.w	8005882 <UART_Receive_IT>
  if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
 800597c:	f015 0501 	ands.w	r5, r5, #1
 8005980:	d102      	bne.n	8005988 <HAL_UART_IRQHandler+0x2c>
 8005982:	f411 7f90 	tst.w	r1, #288	; 0x120
 8005986:	d04e      	beq.n	8005a26 <HAL_UART_IRQHandler+0xca>
    if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
 8005988:	07d3      	lsls	r3, r2, #31
 800598a:	d505      	bpl.n	8005998 <HAL_UART_IRQHandler+0x3c>
 800598c:	05ce      	lsls	r6, r1, #23
      huart->ErrorCode |= HAL_UART_ERROR_PE;
 800598e:	bf42      	ittt	mi
 8005990:	6be3      	ldrmi	r3, [r4, #60]	; 0x3c
 8005992:	f043 0301 	orrmi.w	r3, r3, #1
 8005996:	63e3      	strmi	r3, [r4, #60]	; 0x3c
    if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
 8005998:	0750      	lsls	r0, r2, #29
 800599a:	d504      	bpl.n	80059a6 <HAL_UART_IRQHandler+0x4a>
 800599c:	b11d      	cbz	r5, 80059a6 <HAL_UART_IRQHandler+0x4a>
      huart->ErrorCode |= HAL_UART_ERROR_NE;
 800599e:	6be3      	ldr	r3, [r4, #60]	; 0x3c
 80059a0:	f043 0302 	orr.w	r3, r3, #2
 80059a4:	63e3      	str	r3, [r4, #60]	; 0x3c
    if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
 80059a6:	0793      	lsls	r3, r2, #30
 80059a8:	d504      	bpl.n	80059b4 <HAL_UART_IRQHandler+0x58>
 80059aa:	b11d      	cbz	r5, 80059b4 <HAL_UART_IRQHandler+0x58>
      huart->ErrorCode |= HAL_UART_ERROR_FE;
 80059ac:	6be3      	ldr	r3, [r4, #60]	; 0x3c
 80059ae:	f043 0304 	orr.w	r3, r3, #4
 80059b2:	63e3      	str	r3, [r4, #60]	; 0x3c
    if (((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
 80059b4:	0716      	lsls	r6, r2, #28
 80059b6:	d504      	bpl.n	80059c2 <HAL_UART_IRQHandler+0x66>
 80059b8:	b11d      	cbz	r5, 80059c2 <HAL_UART_IRQHandler+0x66>
      huart->ErrorCode |= HAL_UART_ERROR_ORE;
 80059ba:	6be3      	ldr	r3, [r4, #60]	; 0x3c
 80059bc:	f043 0308 	orr.w	r3, r3, #8
 80059c0:	63e3      	str	r3, [r4, #60]	; 0x3c
    if (huart->ErrorCode != HAL_UART_ERROR_NONE)
 80059c2:	6be3      	ldr	r3, [r4, #60]	; 0x3c
 80059c4:	2b00      	cmp	r3, #0
 80059c6:	d066      	beq.n	8005a96 <HAL_UART_IRQHandler+0x13a>
      if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
 80059c8:	0695      	lsls	r5, r2, #26
 80059ca:	d504      	bpl.n	80059d6 <HAL_UART_IRQHandler+0x7a>
 80059cc:	0688      	lsls	r0, r1, #26
 80059ce:	d502      	bpl.n	80059d6 <HAL_UART_IRQHandler+0x7a>
        UART_Receive_IT(huart);
 80059d0:	4620      	mov	r0, r4
 80059d2:	f7ff ff56 	bl	8005882 <UART_Receive_IT>
      dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
 80059d6:	6823      	ldr	r3, [r4, #0]
        UART_EndRxTransfer(huart);
 80059d8:	4620      	mov	r0, r4
      dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
 80059da:	695d      	ldr	r5, [r3, #20]
      if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest)
 80059dc:	6be2      	ldr	r2, [r4, #60]	; 0x3c
 80059de:	0711      	lsls	r1, r2, #28
 80059e0:	d402      	bmi.n	80059e8 <HAL_UART_IRQHandler+0x8c>
 80059e2:	f015 0540 	ands.w	r5, r5, #64	; 0x40
 80059e6:	d01a      	beq.n	8005a1e <HAL_UART_IRQHandler+0xc2>
        UART_EndRxTransfer(huart);
 80059e8:	f7ff fd96 	bl	8005518 <UART_EndRxTransfer>
        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
 80059ec:	6823      	ldr	r3, [r4, #0]
 80059ee:	695a      	ldr	r2, [r3, #20]
 80059f0:	0652      	lsls	r2, r2, #25
 80059f2:	d510      	bpl.n	8005a16 <HAL_UART_IRQHandler+0xba>
          CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
 80059f4:	695a      	ldr	r2, [r3, #20]
          if (huart->hdmarx != NULL)
 80059f6:	6b60      	ldr	r0, [r4, #52]	; 0x34
          CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
 80059f8:	f022 0240 	bic.w	r2, r2, #64	; 0x40
 80059fc:	615a      	str	r2, [r3, #20]
          if (huart->hdmarx != NULL)
 80059fe:	b150      	cbz	r0, 8005a16 <HAL_UART_IRQHandler+0xba>
            huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
 8005a00:	4b25      	ldr	r3, [pc, #148]	; (8005a98 <HAL_UART_IRQHandler+0x13c>)
 8005a02:	6343      	str	r3, [r0, #52]	; 0x34
            if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
 8005a04:	f7fe fefa 	bl	80047fc <HAL_DMA_Abort_IT>
 8005a08:	2800      	cmp	r0, #0
 8005a0a:	d044      	beq.n	8005a96 <HAL_UART_IRQHandler+0x13a>
              huart->hdmarx->XferAbortCallback(huart->hdmarx);
 8005a0c:	6b60      	ldr	r0, [r4, #52]	; 0x34
}
 8005a0e:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
              huart->hdmarx->XferAbortCallback(huart->hdmarx);
 8005a12:	6b43      	ldr	r3, [r0, #52]	; 0x34
 8005a14:	4718      	bx	r3
            HAL_UART_ErrorCallback(huart);
 8005a16:	4620      	mov	r0, r4
 8005a18:	f7ff ff77 	bl	800590a <HAL_UART_ErrorCallback>
 8005a1c:	bd70      	pop	{r4, r5, r6, pc}
        HAL_UART_ErrorCallback(huart);
 8005a1e:	f7ff ff74 	bl	800590a <HAL_UART_ErrorCallback>
        huart->ErrorCode = HAL_UART_ERROR_NONE;
 8005a22:	63e5      	str	r5, [r4, #60]	; 0x3c
 8005a24:	bd70      	pop	{r4, r5, r6, pc}
  if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
 8005a26:	0616      	lsls	r6, r2, #24
 8005a28:	d527      	bpl.n	8005a7a <HAL_UART_IRQHandler+0x11e>
 8005a2a:	060d      	lsls	r5, r1, #24
 8005a2c:	d525      	bpl.n	8005a7a <HAL_UART_IRQHandler+0x11e>
  if (huart->gState == HAL_UART_STATE_BUSY_TX)
 8005a2e:	f894 2039 	ldrb.w	r2, [r4, #57]	; 0x39
 8005a32:	2a21      	cmp	r2, #33	; 0x21
 8005a34:	d12f      	bne.n	8005a96 <HAL_UART_IRQHandler+0x13a>
    if (huart->Init.WordLength == UART_WORDLENGTH_9B)
 8005a36:	68a2      	ldr	r2, [r4, #8]
 8005a38:	f5b2 5f80 	cmp.w	r2, #4096	; 0x1000
 8005a3c:	6a22      	ldr	r2, [r4, #32]
 8005a3e:	d117      	bne.n	8005a70 <HAL_UART_IRQHandler+0x114>
      huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
 8005a40:	8811      	ldrh	r1, [r2, #0]
 8005a42:	f3c1 0108 	ubfx	r1, r1, #0, #9
 8005a46:	6059      	str	r1, [r3, #4]
      if (huart->Init.Parity == UART_PARITY_NONE)
 8005a48:	6921      	ldr	r1, [r4, #16]
 8005a4a:	b979      	cbnz	r1, 8005a6c <HAL_UART_IRQHandler+0x110>
        huart->pTxBuffPtr += 2U;
 8005a4c:	3202      	adds	r2, #2
        huart->pTxBuffPtr += 1U;
 8005a4e:	6222      	str	r2, [r4, #32]
    if (--huart->TxXferCount == 0U)
 8005a50:	8ce2      	ldrh	r2, [r4, #38]	; 0x26
 8005a52:	3a01      	subs	r2, #1
 8005a54:	b292      	uxth	r2, r2
 8005a56:	84e2      	strh	r2, [r4, #38]	; 0x26
 8005a58:	b9ea      	cbnz	r2, 8005a96 <HAL_UART_IRQHandler+0x13a>
      __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
 8005a5a:	68da      	ldr	r2, [r3, #12]
 8005a5c:	f022 0280 	bic.w	r2, r2, #128	; 0x80
 8005a60:	60da      	str	r2, [r3, #12]
      __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
 8005a62:	68da      	ldr	r2, [r3, #12]
 8005a64:	f042 0240 	orr.w	r2, r2, #64	; 0x40
 8005a68:	60da      	str	r2, [r3, #12]
 8005a6a:	bd70      	pop	{r4, r5, r6, pc}
        huart->pTxBuffPtr += 1U;
 8005a6c:	3201      	adds	r2, #1
 8005a6e:	e7ee      	b.n	8005a4e <HAL_UART_IRQHandler+0xf2>
      huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF);
 8005a70:	1c51      	adds	r1, r2, #1
 8005a72:	6221      	str	r1, [r4, #32]
 8005a74:	7812      	ldrb	r2, [r2, #0]
 8005a76:	605a      	str	r2, [r3, #4]
 8005a78:	e7ea      	b.n	8005a50 <HAL_UART_IRQHandler+0xf4>
  if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
 8005a7a:	0650      	lsls	r0, r2, #25
 8005a7c:	d50b      	bpl.n	8005a96 <HAL_UART_IRQHandler+0x13a>
 8005a7e:	064a      	lsls	r2, r1, #25
 8005a80:	d509      	bpl.n	8005a96 <HAL_UART_IRQHandler+0x13a>
  __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
 8005a82:	68da      	ldr	r2, [r3, #12]
  HAL_UART_TxCpltCallback(huart);
 8005a84:	4620      	mov	r0, r4
  __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
 8005a86:	f022 0240 	bic.w	r2, r2, #64	; 0x40
 8005a8a:	60da      	str	r2, [r3, #12]
  huart->gState = HAL_UART_STATE_READY;
 8005a8c:	2320      	movs	r3, #32
 8005a8e:	f884 3039 	strb.w	r3, [r4, #57]	; 0x39
  HAL_UART_TxCpltCallback(huart);
 8005a92:	f7ff febd 	bl	8005810 <HAL_UART_TxCpltCallback>
 8005a96:	bd70      	pop	{r4, r5, r6, pc}
 8005a98:	08005a9d 	.word	0x08005a9d

08005a9c <UART_DMAAbortOnError>:
{
 8005a9c:	b508      	push	{r3, lr}
  huart->RxXferCount = 0x00U;
 8005a9e:	2300      	movs	r3, #0
  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 8005aa0:	6a40      	ldr	r0, [r0, #36]	; 0x24
  huart->RxXferCount = 0x00U;
 8005aa2:	85c3      	strh	r3, [r0, #46]	; 0x2e
  huart->TxXferCount = 0x00U;
 8005aa4:	84c3      	strh	r3, [r0, #38]	; 0x26
  HAL_UART_ErrorCallback(huart);
 8005aa6:	f7ff ff30 	bl	800590a <HAL_UART_ErrorCallback>
 8005aaa:	bd08      	pop	{r3, pc}

08005aac <CRC16_Generate>:
{
	uint8_t dt = 0U;
	uint16_t crc16 = 0U;

	len *= 8;
	for(crc16 = (uint16_t)0x0000; len >= 8; len -= 8, buf_ptr++)
 8005aac:	2300      	movs	r3, #0
{
 8005aae:	b510      	push	{r4, lr}
	{
		crc16 = (uint16_t)(Table_CRC16[(crc16>>8) ^ (uint16_t)(*buf_ptr)] ^ (crc16<<8));
 8005ab0:	4c0f      	ldr	r4, [pc, #60]	; (8005af0 <CRC16_Generate+0x44>)
	len *= 8;
 8005ab2:	00c9      	lsls	r1, r1, #3
	for(crc16 = (uint16_t)0x0000; len >= 8; len -= 8, buf_ptr++)
 8005ab4:	2907      	cmp	r1, #7
 8005ab6:	dc0f      	bgt.n	8005ad8 <CRC16_Generate+0x2c>
	}

	if(len != 0)
 8005ab8:	b161      	cbz	r1, 8005ad4 <CRC16_Generate+0x28>
			len--;

			if(((crc16^dt) & ((uint16_t)1 << 15)) != 0)
			{
				crc16 =  (uint16_t)(crc16 << 1);
				crc16 = (uint16_t)(crc16 ^ 0x1021);
 8005aba:	f241 0221 	movw	r2, #4129	; 0x1021
			if(((crc16^dt) & ((uint16_t)1 << 15)) != 0)
 8005abe:	f413 4f00 	tst.w	r3, #32768	; 0x8000
 8005ac2:	ea4f 0343 	mov.w	r3, r3, lsl #1
				crc16 =  (uint16_t)(crc16 << 1);
 8005ac6:	b29b      	uxth	r3, r3
			len--;
 8005ac8:	f101 31ff 	add.w	r1, r1, #4294967295
				crc16 = (uint16_t)(crc16 ^ 0x1021);
 8005acc:	bf18      	it	ne
 8005ace:	4053      	eorne	r3, r2
		while(len != 0)
 8005ad0:	2900      	cmp	r1, #0
 8005ad2:	d1f4      	bne.n	8005abe <CRC16_Generate+0x12>
			}
			dt = (uint8_t)(dt << 1);
		}
	}
	return(crc16);
}
 8005ad4:	4618      	mov	r0, r3
 8005ad6:	bd10      	pop	{r4, pc}
		crc16 = (uint16_t)(Table_CRC16[(crc16>>8) ^ (uint16_t)(*buf_ptr)] ^ (crc16<<8));
 8005ad8:	f810 2b01 	ldrb.w	r2, [r0], #1
	for(crc16 = (uint16_t)0x0000; len >= 8; len -= 8, buf_ptr++)
 8005adc:	3908      	subs	r1, #8
		crc16 = (uint16_t)(Table_CRC16[(crc16>>8) ^ (uint16_t)(*buf_ptr)] ^ (crc16<<8));
 8005ade:	ea82 2213 	eor.w	r2, r2, r3, lsr #8
 8005ae2:	f834 2012 	ldrh.w	r2, [r4, r2, lsl #1]
 8005ae6:	ea82 2303 	eor.w	r3, r2, r3, lsl #8
 8005aea:	b29b      	uxth	r3, r3
 8005aec:	e7e2      	b.n	8005ab4 <CRC16_Generate+0x8>
 8005aee:	bf00      	nop
 8005af0:	20000008 	.word	0x20000008

08005af4 <ESP8266_Initialize>:


void ESP8266_Initialize(void){
	  volatile static bool init = false;
	  volatile static uint8_t seq = 0;
	  if(init == false ||  seq < 4){
 8005af4:	4b17      	ldr	r3, [pc, #92]	; (8005b54 <ESP8266_Initialize+0x60>)
void ESP8266_Initialize(void){
 8005af6:	b510      	push	{r4, lr}
	  if(init == false ||  seq < 4){
 8005af8:	781a      	ldrb	r2, [r3, #0]
 8005afa:	4c17      	ldr	r4, [pc, #92]	; (8005b58 <ESP8266_Initialize+0x64>)
 8005afc:	b112      	cbz	r2, 8005b04 <ESP8266_Initialize+0x10>
 8005afe:	7822      	ldrb	r2, [r4, #0]
 8005b00:	2a03      	cmp	r2, #3
 8005b02:	d810      	bhi.n	8005b26 <ESP8266_Initialize+0x32>
		  init = true;
 8005b04:	2201      	movs	r2, #1
 8005b06:	701a      	strb	r2, [r3, #0]
//          Uart2_Data_Send("AT+CIPSEND=1,1\r\n",ESP8266_Strindex("AT+CIPSEND=1,1\r\n"));
//          HAL_Delay(5); 
//          Uart2_Data_Send("1\r\n",ESP8266_Strindex("1\r\n"));              
        return;
	  }
	  switch(seq){
 8005b08:	7823      	ldrb	r3, [r4, #0]
 8005b0a:	2b03      	cmp	r3, #3
 8005b0c:	d80b      	bhi.n	8005b26 <ESP8266_Initialize+0x32>
 8005b0e:	e8df f003 	tbb	[pc, r3]
 8005b12:	0b02      	.short	0x0b02
 8005b14:	110e      	.short	0x110e
	  case 0:
          Uart2_Data_Send("AT+CWMODE=3\r\n",ESP8266_Strindex("AT+CWMODE=3\r\n"));
 8005b16:	210d      	movs	r1, #13
 8005b18:	4810      	ldr	r0, [pc, #64]	; (8005b5c <ESP8266_Initialize+0x68>)
	  case 1:
          Uart2_Data_Send("AT+CIPMUX=1\r\n",ESP8266_Strindex("AT+CIPMUX=1\r\n"));
		  seq++;
		  break;
	  case 2:
          Uart2_Data_Send("AT+CWSAP=\"BLUE_TEST\",\"\",5,0\r\n",ESP8266_Strindex("AT+CWSAP=\"BLUE_TEST\",\"\",5,0\r\n"));
 8005b1a:	f000 fcfb 	bl	8006514 <Uart2_Data_Send>
          Uart2_Data_Send("AT+CIFSR\r\n",ESP8266_Strindex("AT+CIFSR\r\n"));
      
          

		  printf("ESP Setting Complete \r\n");
		  seq++;
 8005b1e:	7823      	ldrb	r3, [r4, #0]
 8005b20:	3301      	adds	r3, #1
 8005b22:	b2db      	uxtb	r3, r3
 8005b24:	7023      	strb	r3, [r4, #0]
 8005b26:	bd10      	pop	{r4, pc}
          Uart2_Data_Send("AT+CIPMUX=1\r\n",ESP8266_Strindex("AT+CIPMUX=1\r\n"));
 8005b28:	210d      	movs	r1, #13
 8005b2a:	480d      	ldr	r0, [pc, #52]	; (8005b60 <ESP8266_Initialize+0x6c>)
 8005b2c:	e7f5      	b.n	8005b1a <ESP8266_Initialize+0x26>
          Uart2_Data_Send("AT+CWSAP=\"BLUE_TEST\",\"\",5,0\r\n",ESP8266_Strindex("AT+CWSAP=\"BLUE_TEST\",\"\",5,0\r\n"));
 8005b2e:	211d      	movs	r1, #29
 8005b30:	480c      	ldr	r0, [pc, #48]	; (8005b64 <ESP8266_Initialize+0x70>)
 8005b32:	e7f2      	b.n	8005b1a <ESP8266_Initialize+0x26>
          Uart2_Data_Send("AT+CIPSERVER=1,4000\r\n",ESP8266_Strindex("AT+CIPSERVER=1,4000\r\n"));
 8005b34:	2115      	movs	r1, #21
 8005b36:	480c      	ldr	r0, [pc, #48]	; (8005b68 <ESP8266_Initialize+0x74>)
 8005b38:	f000 fcec 	bl	8006514 <Uart2_Data_Send>
          HAL_Delay(5);
 8005b3c:	2005      	movs	r0, #5
 8005b3e:	f7fe fbb9 	bl	80042b4 <HAL_Delay>
          Uart2_Data_Send("AT+CIFSR\r\n",ESP8266_Strindex("AT+CIFSR\r\n"));
 8005b42:	210a      	movs	r1, #10
 8005b44:	4809      	ldr	r0, [pc, #36]	; (8005b6c <ESP8266_Initialize+0x78>)
 8005b46:	f000 fce5 	bl	8006514 <Uart2_Data_Send>
		  printf("ESP Setting Complete \r\n");
 8005b4a:	4809      	ldr	r0, [pc, #36]	; (8005b70 <ESP8266_Initialize+0x7c>)
 8005b4c:	f000 fdca 	bl	80066e4 <puts>
 8005b50:	e7e5      	b.n	8005b1e <ESP8266_Initialize+0x2a>
 8005b52:	bf00      	nop
 8005b54:	2000028c 	.word	0x2000028c
 8005b58:	2000028d 	.word	0x2000028d
 8005b5c:	080076e7 	.word	0x080076e7
 8005b60:	080076f5 	.word	0x080076f5
 8005b64:	08007703 	.word	0x08007703
 8005b68:	08007721 	.word	0x08007721
 8005b6c:	08007737 	.word	0x08007737
 8005b70:	08007742 	.word	0x08007742

08005b74 <HAL_TIM_PeriodElapsedCallback>:
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{

    if(htim->Instance == TIM6){
 8005b74:	6802      	ldr	r2, [r0, #0]
 8005b76:	4b08      	ldr	r3, [pc, #32]	; (8005b98 <HAL_TIM_PeriodElapsedCallback+0x24>)
 8005b78:	429a      	cmp	r2, r3
 8005b7a:	d10b      	bne.n	8005b94 <HAL_TIM_PeriodElapsedCallback+0x20>
        UartTimerCnt++;
 8005b7c:	4a07      	ldr	r2, [pc, #28]	; (8005b9c <HAL_TIM_PeriodElapsedCallback+0x28>)
 8005b7e:	6813      	ldr	r3, [r2, #0]
 8005b80:	3301      	adds	r3, #1
 8005b82:	6013      	str	r3, [r2, #0]
        LedTimerCnt++;
 8005b84:	4a06      	ldr	r2, [pc, #24]	; (8005ba0 <HAL_TIM_PeriodElapsedCallback+0x2c>)
 8005b86:	6813      	ldr	r3, [r2, #0]
 8005b88:	3301      	adds	r3, #1
 8005b8a:	6013      	str	r3, [r2, #0]
        InitTimerCnt++;
 8005b8c:	4a05      	ldr	r2, [pc, #20]	; (8005ba4 <HAL_TIM_PeriodElapsedCallback+0x30>)
 8005b8e:	6813      	ldr	r3, [r2, #0]
 8005b90:	3301      	adds	r3, #1
 8005b92:	6013      	str	r3, [r2, #0]
 8005b94:	4770      	bx	lr
 8005b96:	bf00      	nop
 8005b98:	40001000 	.word	0x40001000
 8005b9c:	20000298 	.word	0x20000298
 8005ba0:	20000294 	.word	0x20000294
 8005ba4:	20000290 	.word	0x20000290

08005ba8 <_write>:
    }
}
int _write (int file, uint8_t *ptr, uint16_t len)
{
 8005ba8:	b510      	push	{r4, lr}
 8005baa:	4614      	mov	r4, r2
    HAL_UART_Transmit (&huart1, ptr, len, 10);
 8005bac:	230a      	movs	r3, #10
 8005bae:	4802      	ldr	r0, [pc, #8]	; (8005bb8 <_write+0x10>)
 8005bb0:	f7ff fd50 	bl	8005654 <HAL_UART_Transmit>
    return len;
}
 8005bb4:	4620      	mov	r0, r4
 8005bb6:	bd10      	pop	{r4, pc}
 8005bb8:	2000044c 	.word	0x2000044c

08005bbc <SystemClock_Config>:
/**
  * @brief System Clock Configuration
  * @retval None
  */
void SystemClock_Config(void)
{
 8005bbc:	b510      	push	{r4, lr}
 8005bbe:	b096      	sub	sp, #88	; 0x58
  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
 8005bc0:	2228      	movs	r2, #40	; 0x28
 8005bc2:	2100      	movs	r1, #0
 8005bc4:	a80c      	add	r0, sp, #48	; 0x30
 8005bc6:	f000 fcfd 	bl	80065c4 <memset>
  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 8005bca:	2214      	movs	r2, #20
 8005bcc:	2100      	movs	r1, #0
 8005bce:	a801      	add	r0, sp, #4
 8005bd0:	f000 fcf8 	bl	80065c4 <memset>
  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 8005bd4:	2218      	movs	r2, #24
 8005bd6:	2100      	movs	r1, #0
 8005bd8:	eb0d 0002 	add.w	r0, sp, r2
 8005bdc:	f000 fcf2 	bl	80065c4 <memset>

  /** Initializes the CPU, AHB and APB busses clocks 
  */
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
 8005be0:	2301      	movs	r3, #1
 8005be2:	9310      	str	r3, [sp, #64]	; 0x40
  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
 8005be4:	2310      	movs	r3, #16
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
 8005be6:	2402      	movs	r4, #2
  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
 8005be8:	9311      	str	r3, [sp, #68]	; 0x44
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2;
  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16;
 8005bea:	f44f 1360 	mov.w	r3, #3670016	; 0x380000
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 8005bee:	a80c      	add	r0, sp, #48	; 0x30
  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16;
 8005bf0:	9315      	str	r3, [sp, #84]	; 0x54
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
 8005bf2:	940c      	str	r4, [sp, #48]	; 0x30
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
 8005bf4:	9413      	str	r4, [sp, #76]	; 0x4c
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 8005bf6:	f7ff f843 	bl	8004c80 <HAL_RCC_OscConfig>
  {
    Error_Handler();
  }
  /** Initializes the CPU, AHB and APB busses clocks 
  */
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
 8005bfa:	230f      	movs	r3, #15
                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
 8005bfc:	f44f 6280 	mov.w	r2, #1024	; 0x400
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
 8005c00:	9301      	str	r3, [sp, #4]
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
 8005c02:	2300      	movs	r3, #0
  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;

  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
 8005c04:	4621      	mov	r1, r4
 8005c06:	a801      	add	r0, sp, #4
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
 8005c08:	9303      	str	r3, [sp, #12]
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
 8005c0a:	9204      	str	r2, [sp, #16]
  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
 8005c0c:	9305      	str	r3, [sp, #20]
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
 8005c0e:	9402      	str	r4, [sp, #8]
  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
 8005c10:	f7ff fa10 	bl	8005034 <HAL_RCC_ClockConfig>
  {
    Error_Handler();
  }
  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
  PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6;
 8005c14:	f44f 4300 	mov.w	r3, #32768	; 0x8000
  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
 8005c18:	a806      	add	r0, sp, #24
  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
 8005c1a:	9406      	str	r4, [sp, #24]
  PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6;
 8005c1c:	9308      	str	r3, [sp, #32]
  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
 8005c1e:	f7ff fac7 	bl	80051b0 <HAL_RCCEx_PeriphCLKConfig>
  {
    Error_Handler();
  }
}
 8005c22:	b016      	add	sp, #88	; 0x58
 8005c24:	bd10      	pop	{r4, pc}
	...

08005c28 <main>:
{
 8005c28:	b580      	push	{r7, lr}
	uint8_t tempdata[] = {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A};
 8005c2a:	4aba      	ldr	r2, [pc, #744]	; (8005f14 <main+0x2ec>)
{
 8005c2c:	b08c      	sub	sp, #48	; 0x30
	uint8_t tempdata[] = {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A};
 8005c2e:	6851      	ldr	r1, [r2, #4]
 8005c30:	6810      	ldr	r0, [r2, #0]
 8005c32:	ab05      	add	r3, sp, #20
 8005c34:	c303      	stmia	r3!, {r0, r1}
 8005c36:	8911      	ldrh	r1, [r2, #8]
 8005c38:	7a92      	ldrb	r2, [r2, #10]
static void MX_GPIO_Init(void)
{
  GPIO_InitTypeDef GPIO_InitStruct = {0};

  /* GPIO Ports Clock Enable */
  __HAL_RCC_GPIOC_CLK_ENABLE();
 8005c3a:	4db7      	ldr	r5, [pc, #732]	; (8005f18 <main+0x2f0>)
	uint8_t tempdata[] = {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A};
 8005c3c:	8019      	strh	r1, [r3, #0]
 8005c3e:	709a      	strb	r2, [r3, #2]
  HAL_Init();
 8005c40:	f7fe fb14 	bl	800426c <HAL_Init>
  SystemClock_Config();
 8005c44:	f7ff ffba 	bl	8005bbc <SystemClock_Config>
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8005c48:	2210      	movs	r2, #16
 8005c4a:	2100      	movs	r1, #0
 8005c4c:	a808      	add	r0, sp, #32
 8005c4e:	f000 fcb9 	bl	80065c4 <memset>
  __HAL_RCC_GPIOC_CLK_ENABLE();
 8005c52:	69ab      	ldr	r3, [r5, #24]
  __HAL_RCC_GPIOA_CLK_ENABLE();
  __HAL_RCC_GPIOB_CLK_ENABLE();
  __HAL_RCC_GPIOD_CLK_ENABLE();

  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(GPIOC, BOOT_LED_Pin|PLL_LD_B_Pin|PLL_EN_B_Pin, GPIO_PIN_RESET);
 8005c54:	2200      	movs	r2, #0
  __HAL_RCC_GPIOC_CLK_ENABLE();
 8005c56:	f043 0310 	orr.w	r3, r3, #16
 8005c5a:	61ab      	str	r3, [r5, #24]
 8005c5c:	69ab      	ldr	r3, [r5, #24]
  HAL_GPIO_WritePin(GPIOC, BOOT_LED_Pin|PLL_LD_B_Pin|PLL_EN_B_Pin, GPIO_PIN_RESET);
 8005c5e:	f249 0140 	movw	r1, #36928	; 0x9040
  __HAL_RCC_GPIOC_CLK_ENABLE();
 8005c62:	f003 0310 	and.w	r3, r3, #16
 8005c66:	9301      	str	r3, [sp, #4]
 8005c68:	9b01      	ldr	r3, [sp, #4]
  __HAL_RCC_GPIOA_CLK_ENABLE();
 8005c6a:	69ab      	ldr	r3, [r5, #24]
  HAL_GPIO_WritePin(GPIOC, BOOT_LED_Pin|PLL_LD_B_Pin|PLL_EN_B_Pin, GPIO_PIN_RESET);
 8005c6c:	48ab      	ldr	r0, [pc, #684]	; (8005f1c <main+0x2f4>)
  __HAL_RCC_GPIOA_CLK_ENABLE();
 8005c6e:	f043 0304 	orr.w	r3, r3, #4
 8005c72:	61ab      	str	r3, [r5, #24]
 8005c74:	69ab      	ldr	r3, [r5, #24]
  HAL_GPIO_WritePin(ATT_CLK_B_GPIO_Port, ATT_CLK_B_Pin, GPIO_PIN_RESET);

  /*Configure GPIO pins : BOOT_LED_Pin PLL_LD_B_Pin PLL_EN_B_Pin */
  GPIO_InitStruct.Pin = BOOT_LED_Pin|PLL_LD_B_Pin|PLL_EN_B_Pin;
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8005c76:	2400      	movs	r4, #0
  __HAL_RCC_GPIOA_CLK_ENABLE();
 8005c78:	f003 0304 	and.w	r3, r3, #4
 8005c7c:	9302      	str	r3, [sp, #8]
 8005c7e:	9b02      	ldr	r3, [sp, #8]
  __HAL_RCC_GPIOB_CLK_ENABLE();
 8005c80:	69ab      	ldr	r3, [r5, #24]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 8005c82:	2601      	movs	r6, #1
  __HAL_RCC_GPIOB_CLK_ENABLE();
 8005c84:	f043 0308 	orr.w	r3, r3, #8
 8005c88:	61ab      	str	r3, [r5, #24]
 8005c8a:	69ab      	ldr	r3, [r5, #24]
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8005c8c:	2702      	movs	r7, #2
  __HAL_RCC_GPIOB_CLK_ENABLE();
 8005c8e:	f003 0308 	and.w	r3, r3, #8
 8005c92:	9303      	str	r3, [sp, #12]
 8005c94:	9b03      	ldr	r3, [sp, #12]
  __HAL_RCC_GPIOD_CLK_ENABLE();
 8005c96:	69ab      	ldr	r3, [r5, #24]
  sConfig.Channel = ADC_CHANNEL_9;
 8005c98:	f04f 0809 	mov.w	r8, #9
  __HAL_RCC_GPIOD_CLK_ENABLE();
 8005c9c:	f043 0320 	orr.w	r3, r3, #32
 8005ca0:	61ab      	str	r3, [r5, #24]
 8005ca2:	69ab      	ldr	r3, [r5, #24]
  sConfig.Channel = ADC_CHANNEL_11;
 8005ca4:	f04f 090b 	mov.w	r9, #11
  __HAL_RCC_GPIOD_CLK_ENABLE();
 8005ca8:	f003 0320 	and.w	r3, r3, #32
 8005cac:	9304      	str	r3, [sp, #16]
 8005cae:	9b04      	ldr	r3, [sp, #16]
  HAL_GPIO_WritePin(GPIOC, BOOT_LED_Pin|PLL_LD_B_Pin|PLL_EN_B_Pin, GPIO_PIN_RESET);
 8005cb0:	f7fe ffda 	bl	8004c68 <HAL_GPIO_WritePin>
  HAL_GPIO_WritePin(GPIOA, LED_UL_G_B_Pin|LED_SD_R_B_Pin|PWR_LED_B_Pin|LED_DL_G_B_Pin 
 8005cb4:	2200      	movs	r2, #0
 8005cb6:	f24e 01f2 	movw	r1, #57586	; 0xe0f2
 8005cba:	4899      	ldr	r0, [pc, #612]	; (8005f20 <main+0x2f8>)
 8005cbc:	f7fe ffd4 	bl	8004c68 <HAL_GPIO_WritePin>
  HAL_GPIO_WritePin(GPIOB, RST_WIFI_B_Pin|PA_EN_B_Pin|EXT_PA_EN_B_Pin|PLL_CLK_B_Pin 
 8005cc0:	2200      	movs	r2, #0
 8005cc2:	f248 01d8 	movw	r1, #32984	; 0x80d8
 8005cc6:	4897      	ldr	r0, [pc, #604]	; (8005f24 <main+0x2fc>)
 8005cc8:	f7fe ffce 	bl	8004c68 <HAL_GPIO_WritePin>
  HAL_GPIO_WritePin(ATT_CLK_B_GPIO_Port, ATT_CLK_B_Pin, GPIO_PIN_RESET);
 8005ccc:	2200      	movs	r2, #0
 8005cce:	2104      	movs	r1, #4
 8005cd0:	4895      	ldr	r0, [pc, #596]	; (8005f28 <main+0x300>)
 8005cd2:	f7fe ffc9 	bl	8004c68 <HAL_GPIO_WritePin>
  GPIO_InitStruct.Pin = BOOT_LED_Pin|PLL_LD_B_Pin|PLL_EN_B_Pin;
 8005cd6:	f249 0340 	movw	r3, #36928	; 0x9040
  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 8005cda:	a908      	add	r1, sp, #32
 8005cdc:	488f      	ldr	r0, [pc, #572]	; (8005f1c <main+0x2f4>)
  GPIO_InitStruct.Pin = BOOT_LED_Pin|PLL_LD_B_Pin|PLL_EN_B_Pin;
 8005cde:	9308      	str	r3, [sp, #32]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 8005ce0:	9609      	str	r6, [sp, #36]	; 0x24
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8005ce2:	940a      	str	r4, [sp, #40]	; 0x28
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8005ce4:	970b      	str	r7, [sp, #44]	; 0x2c
  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 8005ce6:	f7fe fed3 	bl	8004a90 <HAL_GPIO_Init>

  /*Configure GPIO pins : LED_UL_G_B_Pin LED_SD_R_B_Pin PWR_LED_B_Pin LED_DL_G_B_Pin 
                           LED_DL_R_B_Pin ATT_DATA_B_Pin ATT_EN1_B_Pin ATT_EN2_B_Pin */
  GPIO_InitStruct.Pin = LED_UL_G_B_Pin|LED_SD_R_B_Pin|PWR_LED_B_Pin|LED_DL_G_B_Pin 
 8005cea:	f24e 03f2 	movw	r3, #57586	; 0xe0f2
                          |LED_DL_R_B_Pin|ATT_DATA_B_Pin|ATT_EN1_B_Pin|ATT_EN2_B_Pin;
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  GPIO_InitStruct.Pull = GPIO_NOPULL;
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8005cee:	a908      	add	r1, sp, #32
 8005cf0:	488b      	ldr	r0, [pc, #556]	; (8005f20 <main+0x2f8>)
  GPIO_InitStruct.Pin = LED_UL_G_B_Pin|LED_SD_R_B_Pin|PWR_LED_B_Pin|LED_DL_G_B_Pin 
 8005cf2:	9308      	str	r3, [sp, #32]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 8005cf4:	9609      	str	r6, [sp, #36]	; 0x24
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8005cf6:	940a      	str	r4, [sp, #40]	; 0x28
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8005cf8:	970b      	str	r7, [sp, #44]	; 0x2c
  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8005cfa:	f7fe fec9 	bl	8004a90 <HAL_GPIO_Init>

  /*Configure GPIO pins : RST_WIFI_B_Pin PA_EN_B_Pin EXT_PA_EN_B_Pin PLL_CLK_B_Pin 
                           PLL_DATA_B_Pin */
  GPIO_InitStruct.Pin = RST_WIFI_B_Pin|PA_EN_B_Pin|EXT_PA_EN_B_Pin|PLL_CLK_B_Pin 
 8005cfe:	f248 03d8 	movw	r3, #32984	; 0x80d8
                          |PLL_DATA_B_Pin;
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  GPIO_InitStruct.Pull = GPIO_NOPULL;
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8005d02:	a908      	add	r1, sp, #32
 8005d04:	4887      	ldr	r0, [pc, #540]	; (8005f24 <main+0x2fc>)
  GPIO_InitStruct.Pin = RST_WIFI_B_Pin|PA_EN_B_Pin|EXT_PA_EN_B_Pin|PLL_CLK_B_Pin 
 8005d06:	9308      	str	r3, [sp, #32]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 8005d08:	9609      	str	r6, [sp, #36]	; 0x24
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8005d0a:	940a      	str	r4, [sp, #40]	; 0x28
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8005d0c:	970b      	str	r7, [sp, #44]	; 0x2c
  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8005d0e:	f7fe febf 	bl	8004a90 <HAL_GPIO_Init>

  /*Configure GPIO pin : ATT_CLK_B_Pin */
  GPIO_InitStruct.Pin = ATT_CLK_B_Pin;
 8005d12:	2304      	movs	r3, #4
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  GPIO_InitStruct.Pull = GPIO_NOPULL;
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8005d14:	970b      	str	r7, [sp, #44]	; 0x2c
  hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
 8005d16:	f44f 2760 	mov.w	r7, #917504	; 0xe0000
  HAL_GPIO_Init(ATT_CLK_B_GPIO_Port, &GPIO_InitStruct);
 8005d1a:	a908      	add	r1, sp, #32
 8005d1c:	4882      	ldr	r0, [pc, #520]	; (8005f28 <main+0x300>)
  GPIO_InitStruct.Pin = ATT_CLK_B_Pin;
 8005d1e:	9308      	str	r3, [sp, #32]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 8005d20:	9609      	str	r6, [sp, #36]	; 0x24
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8005d22:	940a      	str	r4, [sp, #40]	; 0x28
  HAL_GPIO_Init(ATT_CLK_B_GPIO_Port, &GPIO_InitStruct);
 8005d24:	f7fe feb4 	bl	8004a90 <HAL_GPIO_Init>
  __HAL_RCC_DMA1_CLK_ENABLE();
 8005d28:	696b      	ldr	r3, [r5, #20]
  huart1.Init.BaudRate = 115200;
 8005d2a:	f44f 3ae1 	mov.w	sl, #115200	; 0x1c200
  __HAL_RCC_DMA1_CLK_ENABLE();
 8005d2e:	4333      	orrs	r3, r6
 8005d30:	616b      	str	r3, [r5, #20]
 8005d32:	696b      	ldr	r3, [r5, #20]
  hadc1.Instance = ADC1;
 8005d34:	4d7d      	ldr	r5, [pc, #500]	; (8005f2c <main+0x304>)
  __HAL_RCC_DMA1_CLK_ENABLE();
 8005d36:	4033      	ands	r3, r6
 8005d38:	9300      	str	r3, [sp, #0]
 8005d3a:	9b00      	ldr	r3, [sp, #0]
  hadc1.Instance = ADC1;
 8005d3c:	4b7c      	ldr	r3, [pc, #496]	; (8005f30 <main+0x308>)
  if (HAL_ADC_Init(&hadc1) != HAL_OK)
 8005d3e:	4628      	mov	r0, r5
  hadc1.Instance = ADC1;
 8005d40:	602b      	str	r3, [r5, #0]
  hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
 8005d42:	60ac      	str	r4, [r5, #8]
  hadc1.Init.ContinuousConvMode = DISABLE;
 8005d44:	732c      	strb	r4, [r5, #12]
  hadc1.Init.DiscontinuousConvMode = DISABLE;
 8005d46:	752c      	strb	r4, [r5, #20]
  hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
 8005d48:	61ef      	str	r7, [r5, #28]
  hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
 8005d4a:	606c      	str	r4, [r5, #4]
  hadc1.Init.NbrOfConversion = 1;
 8005d4c:	612e      	str	r6, [r5, #16]
  ADC_ChannelConfTypeDef sConfig = {0};
 8005d4e:	9408      	str	r4, [sp, #32]
 8005d50:	9409      	str	r4, [sp, #36]	; 0x24
 8005d52:	940a      	str	r4, [sp, #40]	; 0x28
  if (HAL_ADC_Init(&hadc1) != HAL_OK)
 8005d54:	f7fe fbde 	bl	8004514 <HAL_ADC_Init>
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005d58:	a908      	add	r1, sp, #32
 8005d5a:	4628      	mov	r0, r5
  hadc2.Instance = ADC2;
 8005d5c:	4d75      	ldr	r5, [pc, #468]	; (8005f34 <main+0x30c>)
  sConfig.Channel = ADC_CHANNEL_9;
 8005d5e:	f8cd 8020 	str.w	r8, [sp, #32]
  sConfig.Rank = ADC_REGULAR_RANK_1;
 8005d62:	9609      	str	r6, [sp, #36]	; 0x24
  sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
 8005d64:	940a      	str	r4, [sp, #40]	; 0x28
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005d66:	f7fe fb2f 	bl	80043c8 <HAL_ADC_ConfigChannel>
  hadc2.Instance = ADC2;
 8005d6a:	4b73      	ldr	r3, [pc, #460]	; (8005f38 <main+0x310>)
  if (HAL_ADC_Init(&hadc2) != HAL_OK)
 8005d6c:	4628      	mov	r0, r5
  hadc2.Instance = ADC2;
 8005d6e:	602b      	str	r3, [r5, #0]
  hadc2.Init.ScanConvMode = ADC_SCAN_DISABLE;
 8005d70:	60ac      	str	r4, [r5, #8]
  hadc2.Init.ContinuousConvMode = DISABLE;
 8005d72:	732c      	strb	r4, [r5, #12]
  hadc2.Init.DiscontinuousConvMode = DISABLE;
 8005d74:	752c      	strb	r4, [r5, #20]
  hadc2.Init.ExternalTrigConv = ADC_SOFTWARE_START;
 8005d76:	61ef      	str	r7, [r5, #28]
  hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT;
 8005d78:	606c      	str	r4, [r5, #4]
  hadc2.Init.NbrOfConversion = 1;
 8005d7a:	612e      	str	r6, [r5, #16]
  ADC_ChannelConfTypeDef sConfig = {0};
 8005d7c:	9408      	str	r4, [sp, #32]
 8005d7e:	9409      	str	r4, [sp, #36]	; 0x24
 8005d80:	940a      	str	r4, [sp, #40]	; 0x28
  if (HAL_ADC_Init(&hadc2) != HAL_OK)
 8005d82:	f7fe fbc7 	bl	8004514 <HAL_ADC_Init>
  sConfig.Channel = ADC_CHANNEL_10;
 8005d86:	230a      	movs	r3, #10
  if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
 8005d88:	a908      	add	r1, sp, #32
 8005d8a:	4628      	mov	r0, r5
  hadc3.Instance = ADC3;
 8005d8c:	4d6b      	ldr	r5, [pc, #428]	; (8005f3c <main+0x314>)
  sConfig.Channel = ADC_CHANNEL_10;
 8005d8e:	9308      	str	r3, [sp, #32]
  sConfig.Rank = ADC_REGULAR_RANK_1;
 8005d90:	9609      	str	r6, [sp, #36]	; 0x24
  sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
 8005d92:	940a      	str	r4, [sp, #40]	; 0x28
  if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
 8005d94:	f7fe fb18 	bl	80043c8 <HAL_ADC_ConfigChannel>
  hadc3.Instance = ADC3;
 8005d98:	4b69      	ldr	r3, [pc, #420]	; (8005f40 <main+0x318>)
  if (HAL_ADC_Init(&hadc3) != HAL_OK)
 8005d9a:	4628      	mov	r0, r5
  hadc3.Instance = ADC3;
 8005d9c:	602b      	str	r3, [r5, #0]
  hadc3.Init.ScanConvMode = ADC_SCAN_DISABLE;
 8005d9e:	60ac      	str	r4, [r5, #8]
  hadc3.Init.ContinuousConvMode = DISABLE;
 8005da0:	732c      	strb	r4, [r5, #12]
  hadc3.Init.DiscontinuousConvMode = DISABLE;
 8005da2:	752c      	strb	r4, [r5, #20]
  hadc3.Init.ExternalTrigConv = ADC_SOFTWARE_START;
 8005da4:	61ef      	str	r7, [r5, #28]
  hadc3.Init.DataAlign = ADC_DATAALIGN_RIGHT;
 8005da6:	606c      	str	r4, [r5, #4]
  hadc3.Init.NbrOfConversion = 1;
 8005da8:	612e      	str	r6, [r5, #16]
  ADC_ChannelConfTypeDef sConfig = {0};
 8005daa:	9408      	str	r4, [sp, #32]
 8005dac:	9409      	str	r4, [sp, #36]	; 0x24
 8005dae:	940a      	str	r4, [sp, #40]	; 0x28
  if (HAL_ADC_Init(&hadc3) != HAL_OK)
 8005db0:	f7fe fbb0 	bl	8004514 <HAL_ADC_Init>
  if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
 8005db4:	a908      	add	r1, sp, #32
 8005db6:	4628      	mov	r0, r5
  sConfig.Rank = ADC_REGULAR_RANK_1;
 8005db8:	9609      	str	r6, [sp, #36]	; 0x24
  sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
 8005dba:	940a      	str	r4, [sp, #40]	; 0x28
  sConfig.Channel = ADC_CHANNEL_11;
 8005dbc:	f8cd 9020 	str.w	r9, [sp, #32]
  if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
 8005dc0:	f7fe fb02 	bl	80043c8 <HAL_ADC_ConfigChannel>
  htim6.Init.Prescaler = 6400-1;
 8005dc4:	f641 03ff 	movw	r3, #6399	; 0x18ff
  htim6.Instance = TIM6;
 8005dc8:	4f5e      	ldr	r7, [pc, #376]	; (8005f44 <main+0x31c>)
  htim6.Init.Prescaler = 6400-1;
 8005dca:	4a5f      	ldr	r2, [pc, #380]	; (8005f48 <main+0x320>)
  htim6.Init.Period = 10-1;
 8005dcc:	f8c7 800c 	str.w	r8, [r7, #12]
  huart1.Init.Mode = UART_MODE_TX_RX;
 8005dd0:	f04f 080c 	mov.w	r8, #12
  if (HAL_TIM_Base_Init(&htim6) != HAL_OK)
 8005dd4:	4638      	mov	r0, r7
  huart1.Instance = USART1;
 8005dd6:	4e5d      	ldr	r6, [pc, #372]	; (8005f4c <main+0x324>)
  htim6.Init.Prescaler = 6400-1;
 8005dd8:	e887 000c 	stmia.w	r7, {r2, r3}
  TIM_MasterConfigTypeDef sMasterConfig = {0};
 8005ddc:	9408      	str	r4, [sp, #32]
 8005dde:	9409      	str	r4, [sp, #36]	; 0x24
  htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
 8005de0:	60bc      	str	r4, [r7, #8]
  htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
 8005de2:	61bc      	str	r4, [r7, #24]
  if (HAL_TIM_Base_Init(&htim6) != HAL_OK)
 8005de4:	f7ff fb5e 	bl	80054a4 <HAL_TIM_Base_Init>
  if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK)
 8005de8:	a908      	add	r1, sp, #32
 8005dea:	4638      	mov	r0, r7
  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
 8005dec:	9408      	str	r4, [sp, #32]
  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
 8005dee:	9409      	str	r4, [sp, #36]	; 0x24
  if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK)
 8005df0:	f7ff fb72 	bl	80054d8 <HAL_TIMEx_MasterConfigSynchronization>
  huart1.Init.BaudRate = 115200;
 8005df4:	4b56      	ldr	r3, [pc, #344]	; (8005f50 <main+0x328>)
  huart2.Instance = USART2;
 8005df6:	4d57      	ldr	r5, [pc, #348]	; (8005f54 <main+0x32c>)
  if (HAL_UART_Init(&huart1) != HAL_OK)
 8005df8:	4630      	mov	r0, r6
  huart1.Init.BaudRate = 115200;
 8005dfa:	e886 0408 	stmia.w	r6, {r3, sl}
  huart1.Init.WordLength = UART_WORDLENGTH_8B;
 8005dfe:	60b4      	str	r4, [r6, #8]
  huart1.Init.StopBits = UART_STOPBITS_1;
 8005e00:	60f4      	str	r4, [r6, #12]
  huart1.Init.Parity = UART_PARITY_NONE;
 8005e02:	6134      	str	r4, [r6, #16]
  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
 8005e04:	61b4      	str	r4, [r6, #24]
  huart1.Init.OverSampling = UART_OVERSAMPLING_16;
 8005e06:	61f4      	str	r4, [r6, #28]
  huart1.Init.Mode = UART_MODE_TX_RX;
 8005e08:	f8c6 8014 	str.w	r8, [r6, #20]
  if (HAL_UART_Init(&huart1) != HAL_OK)
 8005e0c:	f7ff fbf4 	bl	80055f8 <HAL_UART_Init>
  huart2.Instance = USART2;
 8005e10:	4b51      	ldr	r3, [pc, #324]	; (8005f58 <main+0x330>)
  if (HAL_UART_Init(&huart2) != HAL_OK)
 8005e12:	4628      	mov	r0, r5
  huart2.Init.BaudRate = 115200;
 8005e14:	e885 0408 	stmia.w	r5, {r3, sl}
  huart2.Init.WordLength = UART_WORDLENGTH_8B;
 8005e18:	60ac      	str	r4, [r5, #8]
  huart2.Init.StopBits = UART_STOPBITS_1;
 8005e1a:	60ec      	str	r4, [r5, #12]
  huart2.Init.Parity = UART_PARITY_NONE;
 8005e1c:	612c      	str	r4, [r5, #16]
  huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
 8005e1e:	61ac      	str	r4, [r5, #24]
  huart2.Init.OverSampling = UART_OVERSAMPLING_16;
 8005e20:	61ec      	str	r4, [r5, #28]
  huart2.Init.Mode = UART_MODE_TX_RX;
 8005e22:	f8c5 8014 	str.w	r8, [r5, #20]
  if (HAL_UART_Init(&huart2) != HAL_OK)
 8005e26:	f7ff fbe7 	bl	80055f8 <HAL_UART_Init>
  huart4.Instance = UART4;
 8005e2a:	4b4c      	ldr	r3, [pc, #304]	; (8005f5c <main+0x334>)
 8005e2c:	484c      	ldr	r0, [pc, #304]	; (8005f60 <main+0x338>)
  huart4.Init.BaudRate = 115200;
 8005e2e:	e880 0408 	stmia.w	r0, {r3, sl}
  huart4.Init.WordLength = UART_WORDLENGTH_8B;
 8005e32:	6084      	str	r4, [r0, #8]
  huart4.Init.StopBits = UART_STOPBITS_1;
 8005e34:	60c4      	str	r4, [r0, #12]
  huart4.Init.Parity = UART_PARITY_NONE;
 8005e36:	6104      	str	r4, [r0, #16]
  huart4.Init.HwFlowCtl = UART_HWCONTROL_NONE;
 8005e38:	6184      	str	r4, [r0, #24]
  huart4.Init.OverSampling = UART_OVERSAMPLING_16;
 8005e3a:	61c4      	str	r4, [r0, #28]
  huart4.Init.Mode = UART_MODE_TX_RX;
 8005e3c:	f8c0 8014 	str.w	r8, [r0, #20]
  if (HAL_UART_Init(&huart4) != HAL_OK)
 8005e40:	f7ff fbda 	bl	80055f8 <HAL_UART_Init>
  HAL_NVIC_SetPriority(DMA1_Channel6_IRQn, 0, 0);
 8005e44:	4622      	mov	r2, r4
 8005e46:	4621      	mov	r1, r4
 8005e48:	2010      	movs	r0, #16
 8005e4a:	f7fe fc01 	bl	8004650 <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(DMA1_Channel6_IRQn);
 8005e4e:	2010      	movs	r0, #16
 8005e50:	f7fe fc32 	bl	80046b8 <HAL_NVIC_EnableIRQ>
  HAL_NVIC_SetPriority(DMA1_Channel5_IRQn, 0, 0);
 8005e54:	4622      	mov	r2, r4
 8005e56:	4621      	mov	r1, r4
 8005e58:	200f      	movs	r0, #15
 8005e5a:	f7fe fbf9 	bl	8004650 <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(DMA1_Channel5_IRQn);
 8005e5e:	200f      	movs	r0, #15
 8005e60:	f7fe fc2a 	bl	80046b8 <HAL_NVIC_EnableIRQ>
  HAL_NVIC_SetPriority(DMA1_Channel4_IRQn, 0, 0);
 8005e64:	4622      	mov	r2, r4
 8005e66:	4621      	mov	r1, r4
 8005e68:	200e      	movs	r0, #14
 8005e6a:	f7fe fbf1 	bl	8004650 <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(DMA1_Channel4_IRQn);
 8005e6e:	200e      	movs	r0, #14
 8005e70:	f7fe fc22 	bl	80046b8 <HAL_NVIC_EnableIRQ>
  HAL_NVIC_SetPriority(DMA1_Channel7_IRQn, 0, 0);
 8005e74:	4622      	mov	r2, r4
 8005e76:	4621      	mov	r1, r4
 8005e78:	2011      	movs	r0, #17
 8005e7a:	f7fe fbe9 	bl	8004650 <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(DMA1_Channel7_IRQn);
 8005e7e:	2011      	movs	r0, #17
 8005e80:	f7fe fc1a 	bl	80046b8 <HAL_NVIC_EnableIRQ>
  HAL_NVIC_SetPriority(ADC3_IRQn, 0, 0);
 8005e84:	4622      	mov	r2, r4
 8005e86:	4621      	mov	r1, r4
 8005e88:	202f      	movs	r0, #47	; 0x2f
 8005e8a:	f7fe fbe1 	bl	8004650 <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(ADC3_IRQn);
 8005e8e:	202f      	movs	r0, #47	; 0x2f
 8005e90:	f7fe fc12 	bl	80046b8 <HAL_NVIC_EnableIRQ>
  HAL_NVIC_SetPriority(UART4_IRQn, 0, 0);
 8005e94:	4622      	mov	r2, r4
 8005e96:	4621      	mov	r1, r4
 8005e98:	2034      	movs	r0, #52	; 0x34
 8005e9a:	f7fe fbd9 	bl	8004650 <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(UART4_IRQn);
 8005e9e:	2034      	movs	r0, #52	; 0x34
 8005ea0:	f7fe fc0a 	bl	80046b8 <HAL_NVIC_EnableIRQ>
  HAL_NVIC_SetPriority(TIM6_IRQn, 0, 0);
 8005ea4:	4622      	mov	r2, r4
 8005ea6:	4621      	mov	r1, r4
 8005ea8:	2036      	movs	r0, #54	; 0x36
 8005eaa:	f7fe fbd1 	bl	8004650 <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(TIM6_IRQn);
 8005eae:	2036      	movs	r0, #54	; 0x36
 8005eb0:	f7fe fc02 	bl	80046b8 <HAL_NVIC_EnableIRQ>
  HAL_NVIC_SetPriority(ADC1_2_IRQn, 0, 0);
 8005eb4:	4622      	mov	r2, r4
 8005eb6:	4621      	mov	r1, r4
 8005eb8:	2012      	movs	r0, #18
 8005eba:	f7fe fbc9 	bl	8004650 <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(ADC1_2_IRQn);
 8005ebe:	2012      	movs	r0, #18
 8005ec0:	f7fe fbfa 	bl	80046b8 <HAL_NVIC_EnableIRQ>
  HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
 8005ec4:	4622      	mov	r2, r4
 8005ec6:	4621      	mov	r1, r4
 8005ec8:	2025      	movs	r0, #37	; 0x25
 8005eca:	f7fe fbc1 	bl	8004650 <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(USART1_IRQn);
 8005ece:	2025      	movs	r0, #37	; 0x25
 8005ed0:	f7fe fbf2 	bl	80046b8 <HAL_NVIC_EnableIRQ>
  HAL_NVIC_SetPriority(USART2_IRQn, 0, 0);
 8005ed4:	4622      	mov	r2, r4
 8005ed6:	4621      	mov	r1, r4
 8005ed8:	2026      	movs	r0, #38	; 0x26
 8005eda:	f7fe fbb9 	bl	8004650 <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(USART2_IRQn);
 8005ede:	2026      	movs	r0, #38	; 0x26
 8005ee0:	f7fe fbea 	bl	80046b8 <HAL_NVIC_EnableIRQ>
  HAL_TIM_Base_Start_IT(&htim6);
 8005ee4:	4638      	mov	r0, r7
 8005ee6:	f7ff f9db 	bl	80052a0 <HAL_TIM_Base_Start_IT>
  setbuf(stdout, NULL);
 8005eea:	4b1e      	ldr	r3, [pc, #120]	; (8005f64 <main+0x33c>)
 8005eec:	4621      	mov	r1, r4
 8005eee:	681b      	ldr	r3, [r3, #0]
	  if(LedTimerCnt > 100){
 8005ef0:	4c1d      	ldr	r4, [pc, #116]	; (8005f68 <main+0x340>)
  setbuf(stdout, NULL);
 8005ef2:	6898      	ldr	r0, [r3, #8]
 8005ef4:	f000 fbfe 	bl	80066f4 <setbuf>
  printf("Uart Start \r\n");
 8005ef8:	481c      	ldr	r0, [pc, #112]	; (8005f6c <main+0x344>)
 8005efa:	f000 fbf3 	bl	80066e4 <puts>
  printf("Crc generate %x \r\n",CRC16_Generate(tempdata,11));
 8005efe:	4649      	mov	r1, r9
 8005f00:	a805      	add	r0, sp, #20
 8005f02:	f7ff fdd3 	bl	8005aac <CRC16_Generate>
 8005f06:	4601      	mov	r1, r0
 8005f08:	4819      	ldr	r0, [pc, #100]	; (8005f70 <main+0x348>)
 8005f0a:	f000 fb63 	bl	80065d4 <iprintf>
  InitUartQueue(&hTerminal,&TerminalQueue);
 8005f0e:	4630      	mov	r0, r6
 8005f10:	e030      	b.n	8005f74 <main+0x34c>
 8005f12:	bf00      	nop
 8005f14:	080076dc 	.word	0x080076dc
 8005f18:	40021000 	.word	0x40021000
 8005f1c:	40011000 	.word	0x40011000
 8005f20:	40010800 	.word	0x40010800
 8005f24:	40010c00 	.word	0x40010c00
 8005f28:	40011400 	.word	0x40011400
 8005f2c:	20000364 	.word	0x20000364
 8005f30:	40012400 	.word	0x40012400
 8005f34:	200002f0 	.word	0x200002f0
 8005f38:	40012800 	.word	0x40012800
 8005f3c:	20000394 	.word	0x20000394
 8005f40:	40013c00 	.word	0x40013c00
 8005f44:	2000048c 	.word	0x2000048c
 8005f48:	40001000 	.word	0x40001000
 8005f4c:	2000044c 	.word	0x2000044c
 8005f50:	40013800 	.word	0x40013800
 8005f54:	2000050c 	.word	0x2000050c
 8005f58:	40004400 	.word	0x40004400
 8005f5c:	40004c00 	.word	0x40004c00
 8005f60:	200004cc 	.word	0x200004cc
 8005f64:	2000020c 	.word	0x2000020c
 8005f68:	20000294 	.word	0x20000294
 8005f6c:	08007759 	.word	0x08007759
 8005f70:	08007766 	.word	0x08007766
 8005f74:	4916      	ldr	r1, [pc, #88]	; (8005fd0 <main+0x3a8>)
 8005f76:	f000 fa67 	bl	8006448 <InitUartQueue>
  InitUartQueue(&hWifi,&WifiQueue);
 8005f7a:	4628      	mov	r0, r5
 8005f7c:	4915      	ldr	r1, [pc, #84]	; (8005fd4 <main+0x3ac>)
 8005f7e:	f000 fa63 	bl	8006448 <InitUartQueue>
		  HAL_GPIO_TogglePin(LED_UL_G_B_GPIO_Port,LED_UL_G_B_Pin);
 8005f82:	4e15      	ldr	r6, [pc, #84]	; (8005fd8 <main+0x3b0>)
	  if(InitTimerCnt >1000){
 8005f84:	4d15      	ldr	r5, [pc, #84]	; (8005fdc <main+0x3b4>)
	  if(LedTimerCnt > 100){
 8005f86:	6823      	ldr	r3, [r4, #0]
 8005f88:	2b64      	cmp	r3, #100	; 0x64
 8005f8a:	d905      	bls.n	8005f98 <main+0x370>
		  HAL_GPIO_TogglePin(LED_UL_G_B_GPIO_Port,LED_UL_G_B_Pin);
 8005f8c:	2102      	movs	r1, #2
 8005f8e:	4630      	mov	r0, r6
 8005f90:	f7fe fe6f 	bl	8004c72 <HAL_GPIO_TogglePin>
		  LedTimerCnt = 0;
 8005f94:	2300      	movs	r3, #0
 8005f96:	6023      	str	r3, [r4, #0]
	  if(InitTimerCnt >1000){
 8005f98:	682b      	ldr	r3, [r5, #0]
 8005f9a:	f5b3 7f7a 	cmp.w	r3, #1000	; 0x3e8
 8005f9e:	d903      	bls.n	8005fa8 <main+0x380>
		  ESP8266_Initialize();
 8005fa0:	f7ff fda8 	bl	8005af4 <ESP8266_Initialize>
		  InitTimerCnt = 0;
 8005fa4:	2300      	movs	r3, #0
 8005fa6:	602b      	str	r3, [r5, #0]
	   while (TerminalQueue.data > 0) GetDataFromUartQueue(&hTerminal);
 8005fa8:	4f09      	ldr	r7, [pc, #36]	; (8005fd0 <main+0x3a8>)
 8005faa:	f8df 8034 	ldr.w	r8, [pc, #52]	; 8005fe0 <main+0x3b8>
 8005fae:	68bb      	ldr	r3, [r7, #8]
 8005fb0:	2b00      	cmp	r3, #0
 8005fb2:	dc09      	bgt.n	8005fc8 <main+0x3a0>
	   while (WifiQueue.data > 0) GetDataFromUartQueue(&hWifi);
 8005fb4:	4f07      	ldr	r7, [pc, #28]	; (8005fd4 <main+0x3ac>)
 8005fb6:	f8df 802c 	ldr.w	r8, [pc, #44]	; 8005fe4 <main+0x3bc>
 8005fba:	68bb      	ldr	r3, [r7, #8]
 8005fbc:	2b00      	cmp	r3, #0
 8005fbe:	dde2      	ble.n	8005f86 <main+0x35e>
 8005fc0:	4640      	mov	r0, r8
 8005fc2:	f000 fa59 	bl	8006478 <GetDataFromUartQueue>
 8005fc6:	e7f8      	b.n	8005fba <main+0x392>
	   while (TerminalQueue.data > 0) GetDataFromUartQueue(&hTerminal);
 8005fc8:	4640      	mov	r0, r8
 8005fca:	f000 fa55 	bl	8006478 <GetDataFromUartQueue>
 8005fce:	e7ee      	b.n	8005fae <main+0x386>
 8005fd0:	2000054c 	.word	0x2000054c
 8005fd4:	20000958 	.word	0x20000958
 8005fd8:	40010800 	.word	0x40010800
 8005fdc:	20000290 	.word	0x20000290
 8005fe0:	2000044c 	.word	0x2000044c
 8005fe4:	2000050c 	.word	0x2000050c

08005fe8 <Error_Handler>:
/**
  * @brief  This function is executed in case of error occurrence.
  * @retval None
  */
void Error_Handler(void)
{
 8005fe8:	4770      	bx	lr
	...

08005fec <HAL_MspInit>:
{
  /* USER CODE BEGIN MspInit 0 */

  /* USER CODE END MspInit 0 */

  __HAL_RCC_AFIO_CLK_ENABLE();
 8005fec:	4b0e      	ldr	r3, [pc, #56]	; (8006028 <HAL_MspInit+0x3c>)
{
 8005fee:	b082      	sub	sp, #8
  __HAL_RCC_AFIO_CLK_ENABLE();
 8005ff0:	699a      	ldr	r2, [r3, #24]
 8005ff2:	f042 0201 	orr.w	r2, r2, #1
 8005ff6:	619a      	str	r2, [r3, #24]
 8005ff8:	699a      	ldr	r2, [r3, #24]
 8005ffa:	f002 0201 	and.w	r2, r2, #1
 8005ffe:	9200      	str	r2, [sp, #0]
 8006000:	9a00      	ldr	r2, [sp, #0]
  __HAL_RCC_PWR_CLK_ENABLE();
 8006002:	69da      	ldr	r2, [r3, #28]
 8006004:	f042 5280 	orr.w	r2, r2, #268435456	; 0x10000000
 8006008:	61da      	str	r2, [r3, #28]
 800600a:	69db      	ldr	r3, [r3, #28]

  /* System interrupt init*/

  /** DISABLE: JTAG-DP Disabled and SW-DP Disabled 
  */
  __HAL_AFIO_REMAP_SWJ_DISABLE();
 800600c:	4a07      	ldr	r2, [pc, #28]	; (800602c <HAL_MspInit+0x40>)
  __HAL_RCC_PWR_CLK_ENABLE();
 800600e:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8006012:	9301      	str	r3, [sp, #4]
 8006014:	9b01      	ldr	r3, [sp, #4]
  __HAL_AFIO_REMAP_SWJ_DISABLE();
 8006016:	6853      	ldr	r3, [r2, #4]
 8006018:	f023 63e0 	bic.w	r3, r3, #117440512	; 0x7000000
 800601c:	f043 6380 	orr.w	r3, r3, #67108864	; 0x4000000
 8006020:	6053      	str	r3, [r2, #4]

  /* USER CODE BEGIN MspInit 1 */

  /* USER CODE END MspInit 1 */
}
 8006022:	b002      	add	sp, #8
 8006024:	4770      	bx	lr
 8006026:	bf00      	nop
 8006028:	40021000 	.word	0x40021000
 800602c:	40010000 	.word	0x40010000

08006030 <HAL_ADC_MspInit>:
* This function configures the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
{
 8006030:	b510      	push	{r4, lr}
 8006032:	4604      	mov	r4, r0
 8006034:	b08a      	sub	sp, #40	; 0x28
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8006036:	2210      	movs	r2, #16
 8006038:	2100      	movs	r1, #0
 800603a:	a806      	add	r0, sp, #24
 800603c:	f000 fac2 	bl	80065c4 <memset>
  if(hadc->Instance==ADC1)
 8006040:	6823      	ldr	r3, [r4, #0]
 8006042:	4a2a      	ldr	r2, [pc, #168]	; (80060ec <HAL_ADC_MspInit+0xbc>)
 8006044:	4293      	cmp	r3, r2
 8006046:	d11c      	bne.n	8006082 <HAL_ADC_MspInit+0x52>
  {
  /* USER CODE BEGIN ADC1_MspInit 0 */

  /* USER CODE END ADC1_MspInit 0 */
    /* Peripheral clock enable */
    __HAL_RCC_ADC1_CLK_ENABLE();
 8006048:	4b29      	ldr	r3, [pc, #164]	; (80060f0 <HAL_ADC_MspInit+0xc0>)
    /**ADC1 GPIO Configuration    
    PB1     ------> ADC1_IN9 
    */
    GPIO_InitStruct.Pin = RFU_TEMP_Pin;
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
    HAL_GPIO_Init(RFU_TEMP_GPIO_Port, &GPIO_InitStruct);
 800604a:	482a      	ldr	r0, [pc, #168]	; (80060f4 <HAL_ADC_MspInit+0xc4>)
    __HAL_RCC_ADC1_CLK_ENABLE();
 800604c:	699a      	ldr	r2, [r3, #24]
    HAL_GPIO_Init(RFU_TEMP_GPIO_Port, &GPIO_InitStruct);
 800604e:	a906      	add	r1, sp, #24
    __HAL_RCC_ADC1_CLK_ENABLE();
 8006050:	f442 7200 	orr.w	r2, r2, #512	; 0x200
 8006054:	619a      	str	r2, [r3, #24]
 8006056:	699a      	ldr	r2, [r3, #24]
 8006058:	f402 7200 	and.w	r2, r2, #512	; 0x200
 800605c:	9200      	str	r2, [sp, #0]
 800605e:	9a00      	ldr	r2, [sp, #0]
    __HAL_RCC_GPIOB_CLK_ENABLE();
 8006060:	699a      	ldr	r2, [r3, #24]
 8006062:	f042 0208 	orr.w	r2, r2, #8
 8006066:	619a      	str	r2, [r3, #24]
 8006068:	699b      	ldr	r3, [r3, #24]
 800606a:	f003 0308 	and.w	r3, r3, #8
 800606e:	9301      	str	r3, [sp, #4]
 8006070:	9b01      	ldr	r3, [sp, #4]
    GPIO_InitStruct.Pin = RFU_TEMP_Pin;
 8006072:	2302      	movs	r3, #2
 8006074:	9306      	str	r3, [sp, #24]
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
 8006076:	2303      	movs	r3, #3
 8006078:	9307      	str	r3, [sp, #28]
    /**ADC3 GPIO Configuration    
    PC1     ------> ADC3_IN11 
    */
    GPIO_InitStruct.Pin = EXT_DET_B_Pin;
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
    HAL_GPIO_Init(EXT_DET_B_GPIO_Port, &GPIO_InitStruct);
 800607a:	f7fe fd09 	bl	8004a90 <HAL_GPIO_Init>
  /* USER CODE BEGIN ADC3_MspInit 1 */

  /* USER CODE END ADC3_MspInit 1 */
  }

}
 800607e:	b00a      	add	sp, #40	; 0x28
 8006080:	bd10      	pop	{r4, pc}
  else if(hadc->Instance==ADC2)
 8006082:	4a1d      	ldr	r2, [pc, #116]	; (80060f8 <HAL_ADC_MspInit+0xc8>)
 8006084:	4293      	cmp	r3, r2
 8006086:	d119      	bne.n	80060bc <HAL_ADC_MspInit+0x8c>
    __HAL_RCC_ADC2_CLK_ENABLE();
 8006088:	4b19      	ldr	r3, [pc, #100]	; (80060f0 <HAL_ADC_MspInit+0xc0>)
 800608a:	699a      	ldr	r2, [r3, #24]
 800608c:	f442 6280 	orr.w	r2, r2, #1024	; 0x400
 8006090:	619a      	str	r2, [r3, #24]
 8006092:	699a      	ldr	r2, [r3, #24]
 8006094:	f402 6280 	and.w	r2, r2, #1024	; 0x400
 8006098:	9202      	str	r2, [sp, #8]
 800609a:	9a02      	ldr	r2, [sp, #8]
    __HAL_RCC_GPIOC_CLK_ENABLE();
 800609c:	699a      	ldr	r2, [r3, #24]
 800609e:	f042 0210 	orr.w	r2, r2, #16
 80060a2:	619a      	str	r2, [r3, #24]
 80060a4:	699b      	ldr	r3, [r3, #24]
 80060a6:	f003 0310 	and.w	r3, r3, #16
 80060aa:	9303      	str	r3, [sp, #12]
 80060ac:	9b03      	ldr	r3, [sp, #12]
    GPIO_InitStruct.Pin = DET_OUT_B_Pin;
 80060ae:	2301      	movs	r3, #1
    GPIO_InitStruct.Pin = EXT_DET_B_Pin;
 80060b0:	9306      	str	r3, [sp, #24]
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
 80060b2:	2303      	movs	r3, #3
    HAL_GPIO_Init(EXT_DET_B_GPIO_Port, &GPIO_InitStruct);
 80060b4:	a906      	add	r1, sp, #24
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
 80060b6:	9307      	str	r3, [sp, #28]
    HAL_GPIO_Init(EXT_DET_B_GPIO_Port, &GPIO_InitStruct);
 80060b8:	4810      	ldr	r0, [pc, #64]	; (80060fc <HAL_ADC_MspInit+0xcc>)
 80060ba:	e7de      	b.n	800607a <HAL_ADC_MspInit+0x4a>
  else if(hadc->Instance==ADC3)
 80060bc:	4a10      	ldr	r2, [pc, #64]	; (8006100 <HAL_ADC_MspInit+0xd0>)
 80060be:	4293      	cmp	r3, r2
 80060c0:	d1dd      	bne.n	800607e <HAL_ADC_MspInit+0x4e>
    __HAL_RCC_ADC3_CLK_ENABLE();
 80060c2:	4b0b      	ldr	r3, [pc, #44]	; (80060f0 <HAL_ADC_MspInit+0xc0>)
 80060c4:	699a      	ldr	r2, [r3, #24]
 80060c6:	f442 4200 	orr.w	r2, r2, #32768	; 0x8000
 80060ca:	619a      	str	r2, [r3, #24]
 80060cc:	699a      	ldr	r2, [r3, #24]
 80060ce:	f402 4200 	and.w	r2, r2, #32768	; 0x8000
 80060d2:	9204      	str	r2, [sp, #16]
 80060d4:	9a04      	ldr	r2, [sp, #16]
    __HAL_RCC_GPIOC_CLK_ENABLE();
 80060d6:	699a      	ldr	r2, [r3, #24]
 80060d8:	f042 0210 	orr.w	r2, r2, #16
 80060dc:	619a      	str	r2, [r3, #24]
 80060de:	699b      	ldr	r3, [r3, #24]
 80060e0:	f003 0310 	and.w	r3, r3, #16
 80060e4:	9305      	str	r3, [sp, #20]
 80060e6:	9b05      	ldr	r3, [sp, #20]
    GPIO_InitStruct.Pin = EXT_DET_B_Pin;
 80060e8:	2302      	movs	r3, #2
 80060ea:	e7e1      	b.n	80060b0 <HAL_ADC_MspInit+0x80>
 80060ec:	40012400 	.word	0x40012400
 80060f0:	40021000 	.word	0x40021000
 80060f4:	40010c00 	.word	0x40010c00
 80060f8:	40012800 	.word	0x40012800
 80060fc:	40011000 	.word	0x40011000
 8006100:	40013c00 	.word	0x40013c00

08006104 <HAL_TIM_Base_MspInit>:
* @param htim_base: TIM_Base handle pointer
* @retval None
*/
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
{
  if(htim_base->Instance==TIM6)
 8006104:	6802      	ldr	r2, [r0, #0]
 8006106:	4b08      	ldr	r3, [pc, #32]	; (8006128 <HAL_TIM_Base_MspInit+0x24>)
{
 8006108:	b082      	sub	sp, #8
  if(htim_base->Instance==TIM6)
 800610a:	429a      	cmp	r2, r3
 800610c:	d10a      	bne.n	8006124 <HAL_TIM_Base_MspInit+0x20>
  {
  /* USER CODE BEGIN TIM6_MspInit 0 */

  /* USER CODE END TIM6_MspInit 0 */
    /* Peripheral clock enable */
    __HAL_RCC_TIM6_CLK_ENABLE();
 800610e:	f503 3300 	add.w	r3, r3, #131072	; 0x20000
 8006112:	69da      	ldr	r2, [r3, #28]
 8006114:	f042 0210 	orr.w	r2, r2, #16
 8006118:	61da      	str	r2, [r3, #28]
 800611a:	69db      	ldr	r3, [r3, #28]
 800611c:	f003 0310 	and.w	r3, r3, #16
 8006120:	9301      	str	r3, [sp, #4]
 8006122:	9b01      	ldr	r3, [sp, #4]
  /* USER CODE BEGIN TIM6_MspInit 1 */

  /* USER CODE END TIM6_MspInit 1 */
  }

}
 8006124:	b002      	add	sp, #8
 8006126:	4770      	bx	lr
 8006128:	40001000 	.word	0x40001000

0800612c <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
 800612c:	b570      	push	{r4, r5, r6, lr}
 800612e:	4605      	mov	r5, r0
 8006130:	b08a      	sub	sp, #40	; 0x28
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8006132:	2210      	movs	r2, #16
 8006134:	2100      	movs	r1, #0
 8006136:	a806      	add	r0, sp, #24
 8006138:	f000 fa44 	bl	80065c4 <memset>
  if(huart->Instance==UART4)
 800613c:	682b      	ldr	r3, [r5, #0]
 800613e:	4a60      	ldr	r2, [pc, #384]	; (80062c0 <HAL_UART_MspInit+0x194>)
 8006140:	4293      	cmp	r3, r2
 8006142:	d129      	bne.n	8006198 <HAL_UART_MspInit+0x6c>
  {
  /* USER CODE BEGIN UART4_MspInit 0 */

  /* USER CODE END UART4_MspInit 0 */
    /* Peripheral clock enable */
    __HAL_RCC_UART4_CLK_ENABLE();
 8006144:	4b5f      	ldr	r3, [pc, #380]	; (80062c4 <HAL_UART_MspInit+0x198>)
    PC11     ------> UART4_RX 
    */
    GPIO_InitStruct.Pin = GPIO_PIN_10;
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 8006146:	a906      	add	r1, sp, #24
    __HAL_RCC_UART4_CLK_ENABLE();
 8006148:	69da      	ldr	r2, [r3, #28]
    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 800614a:	485f      	ldr	r0, [pc, #380]	; (80062c8 <HAL_UART_MspInit+0x19c>)
    __HAL_RCC_UART4_CLK_ENABLE();
 800614c:	f442 2200 	orr.w	r2, r2, #524288	; 0x80000
 8006150:	61da      	str	r2, [r3, #28]
 8006152:	69da      	ldr	r2, [r3, #28]
 8006154:	f402 2200 	and.w	r2, r2, #524288	; 0x80000
 8006158:	9200      	str	r2, [sp, #0]
 800615a:	9a00      	ldr	r2, [sp, #0]
    __HAL_RCC_GPIOC_CLK_ENABLE();
 800615c:	699a      	ldr	r2, [r3, #24]
 800615e:	f042 0210 	orr.w	r2, r2, #16
 8006162:	619a      	str	r2, [r3, #24]
 8006164:	699b      	ldr	r3, [r3, #24]
 8006166:	f003 0310 	and.w	r3, r3, #16
 800616a:	9301      	str	r3, [sp, #4]
 800616c:	9b01      	ldr	r3, [sp, #4]
    GPIO_InitStruct.Pin = GPIO_PIN_10;
 800616e:	f44f 6380 	mov.w	r3, #1024	; 0x400
 8006172:	9306      	str	r3, [sp, #24]
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 8006174:	2302      	movs	r3, #2
 8006176:	9307      	str	r3, [sp, #28]
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
 8006178:	2303      	movs	r3, #3
 800617a:	9309      	str	r3, [sp, #36]	; 0x24
    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 800617c:	f7fe fc88 	bl	8004a90 <HAL_GPIO_Init>

    GPIO_InitStruct.Pin = GPIO_PIN_11;
 8006180:	f44f 6300 	mov.w	r3, #2048	; 0x800
 8006184:	9306      	str	r3, [sp, #24]
    GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
 8006186:	2300      	movs	r3, #0
    GPIO_InitStruct.Pull = GPIO_NOPULL;
    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 8006188:	a906      	add	r1, sp, #24
 800618a:	484f      	ldr	r0, [pc, #316]	; (80062c8 <HAL_UART_MspInit+0x19c>)
    GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
 800618c:	9307      	str	r3, [sp, #28]
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 800618e:	9308      	str	r3, [sp, #32]
    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 8006190:	f7fe fc7e 	bl	8004a90 <HAL_GPIO_Init>
  /* USER CODE BEGIN USART2_MspInit 1 */

  /* USER CODE END USART2_MspInit 1 */
  }

}
 8006194:	b00a      	add	sp, #40	; 0x28
 8006196:	bd70      	pop	{r4, r5, r6, pc}
  else if(huart->Instance==USART1)
 8006198:	4a4c      	ldr	r2, [pc, #304]	; (80062cc <HAL_UART_MspInit+0x1a0>)
 800619a:	4293      	cmp	r3, r2
 800619c:	d150      	bne.n	8006240 <HAL_UART_MspInit+0x114>
    __HAL_RCC_USART1_CLK_ENABLE();
 800619e:	4b49      	ldr	r3, [pc, #292]	; (80062c4 <HAL_UART_MspInit+0x198>)
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 80061a0:	a906      	add	r1, sp, #24
    __HAL_RCC_USART1_CLK_ENABLE();
 80061a2:	699a      	ldr	r2, [r3, #24]
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 80061a4:	484a      	ldr	r0, [pc, #296]	; (80062d0 <HAL_UART_MspInit+0x1a4>)
    __HAL_RCC_USART1_CLK_ENABLE();
 80061a6:	f442 4280 	orr.w	r2, r2, #16384	; 0x4000
 80061aa:	619a      	str	r2, [r3, #24]
 80061ac:	699a      	ldr	r2, [r3, #24]
    GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
 80061ae:	2600      	movs	r6, #0
    __HAL_RCC_USART1_CLK_ENABLE();
 80061b0:	f402 4280 	and.w	r2, r2, #16384	; 0x4000
 80061b4:	9202      	str	r2, [sp, #8]
 80061b6:	9a02      	ldr	r2, [sp, #8]
    __HAL_RCC_GPIOA_CLK_ENABLE();
 80061b8:	699a      	ldr	r2, [r3, #24]
    hdma_usart1_rx.Instance = DMA1_Channel5;
 80061ba:	4c46      	ldr	r4, [pc, #280]	; (80062d4 <HAL_UART_MspInit+0x1a8>)
    __HAL_RCC_GPIOA_CLK_ENABLE();
 80061bc:	f042 0204 	orr.w	r2, r2, #4
 80061c0:	619a      	str	r2, [r3, #24]
 80061c2:	699b      	ldr	r3, [r3, #24]
 80061c4:	f003 0304 	and.w	r3, r3, #4
 80061c8:	9303      	str	r3, [sp, #12]
 80061ca:	9b03      	ldr	r3, [sp, #12]
    GPIO_InitStruct.Pin = GPIO_PIN_9;
 80061cc:	f44f 7300 	mov.w	r3, #512	; 0x200
 80061d0:	9306      	str	r3, [sp, #24]
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 80061d2:	2302      	movs	r3, #2
 80061d4:	9307      	str	r3, [sp, #28]
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
 80061d6:	2303      	movs	r3, #3
 80061d8:	9309      	str	r3, [sp, #36]	; 0x24
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 80061da:	f7fe fc59 	bl	8004a90 <HAL_GPIO_Init>
    GPIO_InitStruct.Pin = GPIO_PIN_10;
 80061de:	f44f 6380 	mov.w	r3, #1024	; 0x400
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 80061e2:	483b      	ldr	r0, [pc, #236]	; (80062d0 <HAL_UART_MspInit+0x1a4>)
 80061e4:	a906      	add	r1, sp, #24
    GPIO_InitStruct.Pin = GPIO_PIN_10;
 80061e6:	9306      	str	r3, [sp, #24]
    GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
 80061e8:	9607      	str	r6, [sp, #28]
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 80061ea:	9608      	str	r6, [sp, #32]
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 80061ec:	f7fe fc50 	bl	8004a90 <HAL_GPIO_Init>
    hdma_usart1_rx.Instance = DMA1_Channel5;
 80061f0:	4b39      	ldr	r3, [pc, #228]	; (80062d8 <HAL_UART_MspInit+0x1ac>)
    if (HAL_DMA_Init(&hdma_usart1_rx) != HAL_OK)
 80061f2:	4620      	mov	r0, r4
    hdma_usart1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
 80061f4:	e884 0048 	stmia.w	r4, {r3, r6}
    hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE;
 80061f8:	2380      	movs	r3, #128	; 0x80
    hdma_usart1_rx.Init.PeriphInc = DMA_PINC_DISABLE;
 80061fa:	60a6      	str	r6, [r4, #8]
    hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE;
 80061fc:	60e3      	str	r3, [r4, #12]
    hdma_usart1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
 80061fe:	6126      	str	r6, [r4, #16]
    hdma_usart1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
 8006200:	6166      	str	r6, [r4, #20]
    hdma_usart1_rx.Init.Mode = DMA_NORMAL;
 8006202:	61a6      	str	r6, [r4, #24]
    hdma_usart1_rx.Init.Priority = DMA_PRIORITY_LOW;
 8006204:	61e6      	str	r6, [r4, #28]
    if (HAL_DMA_Init(&hdma_usart1_rx) != HAL_OK)
 8006206:	f7fe fa7b 	bl	8004700 <HAL_DMA_Init>
 800620a:	b108      	cbz	r0, 8006210 <HAL_UART_MspInit+0xe4>
      Error_Handler();
 800620c:	f7ff feec 	bl	8005fe8 <Error_Handler>
    __HAL_LINKDMA(huart,hdmarx,hdma_usart1_rx);
 8006210:	636c      	str	r4, [r5, #52]	; 0x34
 8006212:	6265      	str	r5, [r4, #36]	; 0x24
    hdma_usart1_tx.Instance = DMA1_Channel4;
 8006214:	4b31      	ldr	r3, [pc, #196]	; (80062dc <HAL_UART_MspInit+0x1b0>)
 8006216:	4c32      	ldr	r4, [pc, #200]	; (80062e0 <HAL_UART_MspInit+0x1b4>)
    hdma_usart2_tx.Instance = DMA1_Channel7;
 8006218:	6023      	str	r3, [r4, #0]
    hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
 800621a:	2310      	movs	r3, #16
    hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE;
 800621c:	2280      	movs	r2, #128	; 0x80
    hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
 800621e:	6063      	str	r3, [r4, #4]
    hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE;
 8006220:	2300      	movs	r3, #0
    hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE;
 8006222:	60e2      	str	r2, [r4, #12]
    hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE;
 8006224:	60a3      	str	r3, [r4, #8]
    hdma_usart2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
 8006226:	6123      	str	r3, [r4, #16]
    hdma_usart2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
 8006228:	6163      	str	r3, [r4, #20]
    hdma_usart2_tx.Init.Mode = DMA_NORMAL;
 800622a:	61a3      	str	r3, [r4, #24]
    hdma_usart2_tx.Init.Priority = DMA_PRIORITY_LOW;
 800622c:	61e3      	str	r3, [r4, #28]
    if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK)
 800622e:	4620      	mov	r0, r4
 8006230:	f7fe fa66 	bl	8004700 <HAL_DMA_Init>
 8006234:	b108      	cbz	r0, 800623a <HAL_UART_MspInit+0x10e>
      Error_Handler();
 8006236:	f7ff fed7 	bl	8005fe8 <Error_Handler>
    __HAL_LINKDMA(huart,hdmatx,hdma_usart2_tx);
 800623a:	632c      	str	r4, [r5, #48]	; 0x30
 800623c:	6265      	str	r5, [r4, #36]	; 0x24
}
 800623e:	e7a9      	b.n	8006194 <HAL_UART_MspInit+0x68>
  else if(huart->Instance==USART2)
 8006240:	4a28      	ldr	r2, [pc, #160]	; (80062e4 <HAL_UART_MspInit+0x1b8>)
 8006242:	4293      	cmp	r3, r2
 8006244:	d1a6      	bne.n	8006194 <HAL_UART_MspInit+0x68>
    __HAL_RCC_USART2_CLK_ENABLE();
 8006246:	4b1f      	ldr	r3, [pc, #124]	; (80062c4 <HAL_UART_MspInit+0x198>)
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8006248:	a906      	add	r1, sp, #24
    __HAL_RCC_USART2_CLK_ENABLE();
 800624a:	69da      	ldr	r2, [r3, #28]
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 800624c:	4820      	ldr	r0, [pc, #128]	; (80062d0 <HAL_UART_MspInit+0x1a4>)
    __HAL_RCC_USART2_CLK_ENABLE();
 800624e:	f442 3200 	orr.w	r2, r2, #131072	; 0x20000
 8006252:	61da      	str	r2, [r3, #28]
 8006254:	69da      	ldr	r2, [r3, #28]
    GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
 8006256:	2600      	movs	r6, #0
    __HAL_RCC_USART2_CLK_ENABLE();
 8006258:	f402 3200 	and.w	r2, r2, #131072	; 0x20000
 800625c:	9204      	str	r2, [sp, #16]
 800625e:	9a04      	ldr	r2, [sp, #16]
    __HAL_RCC_GPIOA_CLK_ENABLE();
 8006260:	699a      	ldr	r2, [r3, #24]
    hdma_usart2_rx.Instance = DMA1_Channel6;
 8006262:	4c21      	ldr	r4, [pc, #132]	; (80062e8 <HAL_UART_MspInit+0x1bc>)
    __HAL_RCC_GPIOA_CLK_ENABLE();
 8006264:	f042 0204 	orr.w	r2, r2, #4
 8006268:	619a      	str	r2, [r3, #24]
 800626a:	699b      	ldr	r3, [r3, #24]
 800626c:	f003 0304 	and.w	r3, r3, #4
 8006270:	9305      	str	r3, [sp, #20]
 8006272:	9b05      	ldr	r3, [sp, #20]
    GPIO_InitStruct.Pin = GPIO_PIN_2;
 8006274:	2304      	movs	r3, #4
 8006276:	9306      	str	r3, [sp, #24]
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 8006278:	2302      	movs	r3, #2
 800627a:	9307      	str	r3, [sp, #28]
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
 800627c:	2303      	movs	r3, #3
 800627e:	9309      	str	r3, [sp, #36]	; 0x24
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8006280:	f7fe fc06 	bl	8004a90 <HAL_GPIO_Init>
    GPIO_InitStruct.Pin = GPIO_PIN_3;
 8006284:	2308      	movs	r3, #8
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8006286:	4812      	ldr	r0, [pc, #72]	; (80062d0 <HAL_UART_MspInit+0x1a4>)
 8006288:	a906      	add	r1, sp, #24
    GPIO_InitStruct.Pin = GPIO_PIN_3;
 800628a:	9306      	str	r3, [sp, #24]
    GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
 800628c:	9607      	str	r6, [sp, #28]
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 800628e:	9608      	str	r6, [sp, #32]
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8006290:	f7fe fbfe 	bl	8004a90 <HAL_GPIO_Init>
    hdma_usart2_rx.Instance = DMA1_Channel6;
 8006294:	4b15      	ldr	r3, [pc, #84]	; (80062ec <HAL_UART_MspInit+0x1c0>)
    if (HAL_DMA_Init(&hdma_usart2_rx) != HAL_OK)
 8006296:	4620      	mov	r0, r4
    hdma_usart2_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
 8006298:	e884 0048 	stmia.w	r4, {r3, r6}
    hdma_usart2_rx.Init.MemInc = DMA_MINC_ENABLE;
 800629c:	2380      	movs	r3, #128	; 0x80
    hdma_usart2_rx.Init.PeriphInc = DMA_PINC_DISABLE;
 800629e:	60a6      	str	r6, [r4, #8]
    hdma_usart2_rx.Init.MemInc = DMA_MINC_ENABLE;
 80062a0:	60e3      	str	r3, [r4, #12]
    hdma_usart2_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
 80062a2:	6126      	str	r6, [r4, #16]
    hdma_usart2_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
 80062a4:	6166      	str	r6, [r4, #20]
    hdma_usart2_rx.Init.Mode = DMA_NORMAL;
 80062a6:	61a6      	str	r6, [r4, #24]
    hdma_usart2_rx.Init.Priority = DMA_PRIORITY_LOW;
 80062a8:	61e6      	str	r6, [r4, #28]
    if (HAL_DMA_Init(&hdma_usart2_rx) != HAL_OK)
 80062aa:	f7fe fa29 	bl	8004700 <HAL_DMA_Init>
 80062ae:	b108      	cbz	r0, 80062b4 <HAL_UART_MspInit+0x188>
      Error_Handler();
 80062b0:	f7ff fe9a 	bl	8005fe8 <Error_Handler>
    __HAL_LINKDMA(huart,hdmarx,hdma_usart2_rx);
 80062b4:	636c      	str	r4, [r5, #52]	; 0x34
 80062b6:	6265      	str	r5, [r4, #36]	; 0x24
    hdma_usart2_tx.Instance = DMA1_Channel7;
 80062b8:	4b0d      	ldr	r3, [pc, #52]	; (80062f0 <HAL_UART_MspInit+0x1c4>)
 80062ba:	4c0e      	ldr	r4, [pc, #56]	; (80062f4 <HAL_UART_MspInit+0x1c8>)
 80062bc:	e7ac      	b.n	8006218 <HAL_UART_MspInit+0xec>
 80062be:	bf00      	nop
 80062c0:	40004c00 	.word	0x40004c00
 80062c4:	40021000 	.word	0x40021000
 80062c8:	40011000 	.word	0x40011000
 80062cc:	40013800 	.word	0x40013800
 80062d0:	40010800 	.word	0x40010800
 80062d4:	200003c4 	.word	0x200003c4
 80062d8:	40020058 	.word	0x40020058
 80062dc:	40020044 	.word	0x40020044
 80062e0:	20000320 	.word	0x20000320
 80062e4:	40004400 	.word	0x40004400
 80062e8:	200002ac 	.word	0x200002ac
 80062ec:	4002006c 	.word	0x4002006c
 80062f0:	40020080 	.word	0x40020080
 80062f4:	20000408 	.word	0x20000408

080062f8 <NMI_Handler>:
 80062f8:	4770      	bx	lr

080062fa <HardFault_Handler>:

/**
  * @brief This function handles Hard fault interrupt.
  */
void HardFault_Handler(void)
{
 80062fa:	e7fe      	b.n	80062fa <HardFault_Handler>

080062fc <MemManage_Handler>:

/**
  * @brief This function handles Memory management fault.
  */
void MemManage_Handler(void)
{
 80062fc:	e7fe      	b.n	80062fc <MemManage_Handler>

080062fe <BusFault_Handler>:

/**
  * @brief This function handles Prefetch fault, memory access fault.
  */
void BusFault_Handler(void)
{
 80062fe:	e7fe      	b.n	80062fe <BusFault_Handler>

08006300 <UsageFault_Handler>:

/**
  * @brief This function handles Undefined instruction or illegal state.
  */
void UsageFault_Handler(void)
{
 8006300:	e7fe      	b.n	8006300 <UsageFault_Handler>

08006302 <SVC_Handler>:
 8006302:	4770      	bx	lr

08006304 <DebugMon_Handler>:
 8006304:	4770      	bx	lr

08006306 <PendSV_Handler>:

/**
  * @brief This function handles Pendable request for system service.
  */
void PendSV_Handler(void)
{
 8006306:	4770      	bx	lr

08006308 <SysTick_Handler>:
void SysTick_Handler(void)
{
  /* USER CODE BEGIN SysTick_IRQn 0 */

  /* USER CODE END SysTick_IRQn 0 */
  HAL_IncTick();
 8006308:	f7fd bfc2 	b.w	8004290 <HAL_IncTick>

0800630c <DMA1_Channel4_IRQHandler>:
void DMA1_Channel4_IRQHandler(void)
{
  /* USER CODE BEGIN DMA1_Channel4_IRQn 0 */

  /* USER CODE END DMA1_Channel4_IRQn 0 */
  HAL_DMA_IRQHandler(&hdma_usart1_tx);
 800630c:	4801      	ldr	r0, [pc, #4]	; (8006314 <DMA1_Channel4_IRQHandler+0x8>)
 800630e:	f7fe bae3 	b.w	80048d8 <HAL_DMA_IRQHandler>
 8006312:	bf00      	nop
 8006314:	20000320 	.word	0x20000320

08006318 <DMA1_Channel5_IRQHandler>:
void DMA1_Channel5_IRQHandler(void)
{
  /* USER CODE BEGIN DMA1_Channel5_IRQn 0 */

  /* USER CODE END DMA1_Channel5_IRQn 0 */
  HAL_DMA_IRQHandler(&hdma_usart1_rx);
 8006318:	4801      	ldr	r0, [pc, #4]	; (8006320 <DMA1_Channel5_IRQHandler+0x8>)
 800631a:	f7fe badd 	b.w	80048d8 <HAL_DMA_IRQHandler>
 800631e:	bf00      	nop
 8006320:	200003c4 	.word	0x200003c4

08006324 <DMA1_Channel6_IRQHandler>:
void DMA1_Channel6_IRQHandler(void)
{
  /* USER CODE BEGIN DMA1_Channel6_IRQn 0 */

  /* USER CODE END DMA1_Channel6_IRQn 0 */
  HAL_DMA_IRQHandler(&hdma_usart2_rx);
 8006324:	4801      	ldr	r0, [pc, #4]	; (800632c <DMA1_Channel6_IRQHandler+0x8>)
 8006326:	f7fe bad7 	b.w	80048d8 <HAL_DMA_IRQHandler>
 800632a:	bf00      	nop
 800632c:	200002ac 	.word	0x200002ac

08006330 <DMA1_Channel7_IRQHandler>:
void DMA1_Channel7_IRQHandler(void)
{
  /* USER CODE BEGIN DMA1_Channel7_IRQn 0 */

  /* USER CODE END DMA1_Channel7_IRQn 0 */
  HAL_DMA_IRQHandler(&hdma_usart2_tx);
 8006330:	4801      	ldr	r0, [pc, #4]	; (8006338 <DMA1_Channel7_IRQHandler+0x8>)
 8006332:	f7fe bad1 	b.w	80048d8 <HAL_DMA_IRQHandler>
 8006336:	bf00      	nop
 8006338:	20000408 	.word	0x20000408

0800633c <ADC1_2_IRQHandler>:

/**
  * @brief This function handles ADC1 and ADC2 global interrupts.
  */
void ADC1_2_IRQHandler(void)
{
 800633c:	b508      	push	{r3, lr}
  /* USER CODE BEGIN ADC1_2_IRQn 0 */

  /* USER CODE END ADC1_2_IRQn 0 */
  HAL_ADC_IRQHandler(&hadc1);
 800633e:	4804      	ldr	r0, [pc, #16]	; (8006350 <ADC1_2_IRQHandler+0x14>)
 8006340:	f7fd ffcc 	bl	80042dc <HAL_ADC_IRQHandler>
  HAL_ADC_IRQHandler(&hadc2);
  /* USER CODE BEGIN ADC1_2_IRQn 1 */

  /* USER CODE END ADC1_2_IRQn 1 */
}
 8006344:	e8bd 4008 	ldmia.w	sp!, {r3, lr}
  HAL_ADC_IRQHandler(&hadc2);
 8006348:	4802      	ldr	r0, [pc, #8]	; (8006354 <ADC1_2_IRQHandler+0x18>)
 800634a:	f7fd bfc7 	b.w	80042dc <HAL_ADC_IRQHandler>
 800634e:	bf00      	nop
 8006350:	20000364 	.word	0x20000364
 8006354:	200002f0 	.word	0x200002f0

08006358 <USART1_IRQHandler>:
void USART1_IRQHandler(void)
{
  /* USER CODE BEGIN USART1_IRQn 0 */

  /* USER CODE END USART1_IRQn 0 */
  HAL_UART_IRQHandler(&huart1);
 8006358:	4801      	ldr	r0, [pc, #4]	; (8006360 <USART1_IRQHandler+0x8>)
 800635a:	f7ff baff 	b.w	800595c <HAL_UART_IRQHandler>
 800635e:	bf00      	nop
 8006360:	2000044c 	.word	0x2000044c

08006364 <USART2_IRQHandler>:
void USART2_IRQHandler(void)
{
  /* USER CODE BEGIN USART2_IRQn 0 */

  /* USER CODE END USART2_IRQn 0 */
  HAL_UART_IRQHandler(&huart2);
 8006364:	4801      	ldr	r0, [pc, #4]	; (800636c <USART2_IRQHandler+0x8>)
 8006366:	f7ff baf9 	b.w	800595c <HAL_UART_IRQHandler>
 800636a:	bf00      	nop
 800636c:	2000050c 	.word	0x2000050c

08006370 <ADC3_IRQHandler>:
void ADC3_IRQHandler(void)
{
  /* USER CODE BEGIN ADC3_IRQn 0 */

  /* USER CODE END ADC3_IRQn 0 */
  HAL_ADC_IRQHandler(&hadc3);
 8006370:	4801      	ldr	r0, [pc, #4]	; (8006378 <ADC3_IRQHandler+0x8>)
 8006372:	f7fd bfb3 	b.w	80042dc <HAL_ADC_IRQHandler>
 8006376:	bf00      	nop
 8006378:	20000394 	.word	0x20000394

0800637c <UART4_IRQHandler>:
void UART4_IRQHandler(void)
{
  /* USER CODE BEGIN UART4_IRQn 0 */

  /* USER CODE END UART4_IRQn 0 */
  HAL_UART_IRQHandler(&huart4);
 800637c:	4801      	ldr	r0, [pc, #4]	; (8006384 <UART4_IRQHandler+0x8>)
 800637e:	f7ff baed 	b.w	800595c <HAL_UART_IRQHandler>
 8006382:	bf00      	nop
 8006384:	200004cc 	.word	0x200004cc

08006388 <TIM6_IRQHandler>:
void TIM6_IRQHandler(void)
{
  /* USER CODE BEGIN TIM6_IRQn 0 */

  /* USER CODE END TIM6_IRQn 0 */
  HAL_TIM_IRQHandler(&htim6);
 8006388:	4801      	ldr	r0, [pc, #4]	; (8006390 <TIM6_IRQHandler+0x8>)
 800638a:	f7fe bf9d 	b.w	80052c8 <HAL_TIM_IRQHandler>
 800638e:	bf00      	nop
 8006390:	2000048c 	.word	0x2000048c

08006394 <_read>:
	_kill(status, -1);
	while (1) {}		/* Make sure we hang here */
}

__attribute__((weak)) int _read(int file, char *ptr, int len)
{
 8006394:	b570      	push	{r4, r5, r6, lr}
 8006396:	460e      	mov	r6, r1
 8006398:	4615      	mov	r5, r2
	int DataIdx;

	for (DataIdx = 0; DataIdx < len; DataIdx++)
 800639a:	460c      	mov	r4, r1
 800639c:	1ba3      	subs	r3, r4, r6
 800639e:	429d      	cmp	r5, r3
 80063a0:	dc01      	bgt.n	80063a6 <_read+0x12>
	{
		*ptr++ = __io_getchar();
	}

return len;
}
 80063a2:	4628      	mov	r0, r5
 80063a4:	bd70      	pop	{r4, r5, r6, pc}
		*ptr++ = __io_getchar();
 80063a6:	f3af 8000 	nop.w
 80063aa:	f804 0b01 	strb.w	r0, [r4], #1
 80063ae:	e7f5      	b.n	800639c <_read+0x8>

080063b0 <_sbrk>:
	}
	return len;
}

caddr_t _sbrk(int incr)
{
 80063b0:	b508      	push	{r3, lr}
	extern char end asm("end");
	static char *heap_end;
	char *prev_heap_end;

	if (heap_end == 0)
 80063b2:	4b0a      	ldr	r3, [pc, #40]	; (80063dc <_sbrk+0x2c>)
{
 80063b4:	4602      	mov	r2, r0
	if (heap_end == 0)
 80063b6:	6819      	ldr	r1, [r3, #0]
 80063b8:	b909      	cbnz	r1, 80063be <_sbrk+0xe>
		heap_end = &end;
 80063ba:	4909      	ldr	r1, [pc, #36]	; (80063e0 <_sbrk+0x30>)
 80063bc:	6019      	str	r1, [r3, #0]

	prev_heap_end = heap_end;
	if (heap_end + incr > stack_ptr)
 80063be:	4669      	mov	r1, sp
	prev_heap_end = heap_end;
 80063c0:	6818      	ldr	r0, [r3, #0]
	if (heap_end + incr > stack_ptr)
 80063c2:	4402      	add	r2, r0
 80063c4:	428a      	cmp	r2, r1
 80063c6:	d906      	bls.n	80063d6 <_sbrk+0x26>
	{
//		write(1, "Heap and stack collision\n", 25);
//		abort();
		errno = ENOMEM;
 80063c8:	f000 f8d2 	bl	8006570 <__errno>
 80063cc:	230c      	movs	r3, #12
 80063ce:	6003      	str	r3, [r0, #0]
		return (caddr_t) -1;
 80063d0:	f04f 30ff 	mov.w	r0, #4294967295
 80063d4:	bd08      	pop	{r3, pc}
	}

	heap_end += incr;
 80063d6:	601a      	str	r2, [r3, #0]

	return (caddr_t) prev_heap_end;
}
 80063d8:	bd08      	pop	{r3, pc}
 80063da:	bf00      	nop
 80063dc:	2000029c 	.word	0x2000029c
 80063e0:	20000d68 	.word	0x20000d68

080063e4 <_close>:

int _close(int file)
{
	return -1;
}
 80063e4:	f04f 30ff 	mov.w	r0, #4294967295
 80063e8:	4770      	bx	lr

080063ea <_fstat>:


int _fstat(int file, struct stat *st)
{
	st->st_mode = S_IFCHR;
 80063ea:	f44f 5300 	mov.w	r3, #8192	; 0x2000
	return 0;
}
 80063ee:	2000      	movs	r0, #0
	st->st_mode = S_IFCHR;
 80063f0:	604b      	str	r3, [r1, #4]
}
 80063f2:	4770      	bx	lr

080063f4 <_isatty>:

int _isatty(int file)
{
	return 1;
}
 80063f4:	2001      	movs	r0, #1
 80063f6:	4770      	bx	lr

080063f8 <_lseek>:

int _lseek(int file, int ptr, int dir)
{
	return 0;
}
 80063f8:	2000      	movs	r0, #0
 80063fa:	4770      	bx	lr

080063fc <SystemInit>:
  */
void SystemInit (void)
{
  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
  /* Set HSION bit */
  RCC->CR |= 0x00000001U;
 80063fc:	4b0e      	ldr	r3, [pc, #56]	; (8006438 <SystemInit+0x3c>)
 80063fe:	681a      	ldr	r2, [r3, #0]
 8006400:	f042 0201 	orr.w	r2, r2, #1
 8006404:	601a      	str	r2, [r3, #0]

  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
#if !defined(STM32F105xC) && !defined(STM32F107xC)
  RCC->CFGR &= 0xF8FF0000U;
 8006406:	6859      	ldr	r1, [r3, #4]
 8006408:	4a0c      	ldr	r2, [pc, #48]	; (800643c <SystemInit+0x40>)
 800640a:	400a      	ands	r2, r1
 800640c:	605a      	str	r2, [r3, #4]
#else
  RCC->CFGR &= 0xF0FF0000U;
#endif /* STM32F105xC */   
  
  /* Reset HSEON, CSSON and PLLON bits */
  RCC->CR &= 0xFEF6FFFFU;
 800640e:	681a      	ldr	r2, [r3, #0]
 8006410:	f022 7284 	bic.w	r2, r2, #17301504	; 0x1080000
 8006414:	f422 3280 	bic.w	r2, r2, #65536	; 0x10000
 8006418:	601a      	str	r2, [r3, #0]

  /* Reset HSEBYP bit */
  RCC->CR &= 0xFFFBFFFFU;
 800641a:	681a      	ldr	r2, [r3, #0]
 800641c:	f422 2280 	bic.w	r2, r2, #262144	; 0x40000
 8006420:	601a      	str	r2, [r3, #0]

  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
  RCC->CFGR &= 0xFF80FFFFU;
 8006422:	685a      	ldr	r2, [r3, #4]
 8006424:	f422 02fe 	bic.w	r2, r2, #8323072	; 0x7f0000
 8006428:	605a      	str	r2, [r3, #4]

  /* Reset CFGR2 register */
  RCC->CFGR2 = 0x00000000U;      
#else
  /* Disable all interrupts and clear pending bits  */
  RCC->CIR = 0x009F0000U;
 800642a:	f44f 021f 	mov.w	r2, #10420224	; 0x9f0000
 800642e:	609a      	str	r2, [r3, #8]
#endif 

#ifdef VECT_TAB_SRAM
  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#else
  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
 8006430:	4a03      	ldr	r2, [pc, #12]	; (8006440 <SystemInit+0x44>)
 8006432:	4b04      	ldr	r3, [pc, #16]	; (8006444 <SystemInit+0x48>)
 8006434:	609a      	str	r2, [r3, #8]
 8006436:	4770      	bx	lr
 8006438:	40021000 	.word	0x40021000
 800643c:	f8ff0000 	.word	0xf8ff0000
 8006440:	08004000 	.word	0x08004000
 8006444:	e000ed00 	.word	0xe000ed00

08006448 <InitUartQueue>:
UARTQUEUE TerminalQueue;
UARTQUEUE WifiQueue;
void InitUartQueue(UART_HandleTypeDef *huart,pUARTQUEUE pQueue)
{
    UART_HandleTypeDef *dst = (huart->Instance == USART2 ? &hWifi:&hTerminal);
    pQueue->data = pQueue->head = pQueue->tail = 0;
 8006448:	2300      	movs	r3, #0
{
 800644a:	b430      	push	{r4, r5}
    UART_HandleTypeDef *dst = (huart->Instance == USART2 ? &hWifi:&hTerminal);
 800644c:	6805      	ldr	r5, [r0, #0]

    if (HAL_UART_Receive_DMA(dst, pQueue->Buffer, 1) != HAL_OK)
 800644e:	4c07      	ldr	r4, [pc, #28]	; (800646c <InitUartQueue+0x24>)
    pQueue->data = pQueue->head = pQueue->tail = 0;
 8006450:	604b      	str	r3, [r1, #4]
 8006452:	600b      	str	r3, [r1, #0]
 8006454:	608b      	str	r3, [r1, #8]
    if (HAL_UART_Receive_DMA(dst, pQueue->Buffer, 1) != HAL_OK)
 8006456:	4806      	ldr	r0, [pc, #24]	; (8006470 <InitUartQueue+0x28>)
 8006458:	4b06      	ldr	r3, [pc, #24]	; (8006474 <InitUartQueue+0x2c>)
 800645a:	2201      	movs	r2, #1
 800645c:	4285      	cmp	r5, r0
 800645e:	bf0c      	ite	eq
 8006460:	4620      	moveq	r0, r4
 8006462:	4618      	movne	r0, r3
    {
//      _Error_Handler(__FILE__, __LINE__);
    }
    //HAL_UART_Receive_DMA(&hTerminal,  TerminalQueue.Buffer, 1);
    //HAL_UART_Receive_IT(hTerminal, pQueue->Buffer + pQueue->head, 1);
}
 8006464:	bc30      	pop	{r4, r5}
    if (HAL_UART_Receive_DMA(dst, pQueue->Buffer, 1) != HAL_OK)
 8006466:	310c      	adds	r1, #12
 8006468:	f7ff b98a 	b.w	8005780 <HAL_UART_Receive_DMA>
 800646c:	2000050c 	.word	0x2000050c
 8006470:	40004400 	.word	0x40004400
 8006474:	2000044c 	.word	0x2000044c

08006478 <GetDataFromUartQueue>:
    if (pQueue->head == QUEUE_BUFFER_LENGTH) pQueue->head = 0;
    pQueue->data++;
   // HAL_UART_Receive_DMA(&hTerminal,  pQueue->Buffer + pQueue->head, 10);
}
void GetDataFromUartQueue(UART_HandleTypeDef *huart)
{
 8006478:	b510      	push	{r4, lr}
    UART_HandleTypeDef *dst = (huart->Instance == USART2 ? &hWifi:&hTerminal);
    pUARTQUEUE pQueue = (huart->Instance == USART2 ? &WifiQueue:&TerminalQueue);
 800647a:	6801      	ldr	r1, [r0, #0]
 800647c:	4b0a      	ldr	r3, [pc, #40]	; (80064a8 <GetDataFromUartQueue+0x30>)
 800647e:	4a0b      	ldr	r2, [pc, #44]	; (80064ac <GetDataFromUartQueue+0x34>)
 8006480:	4c0b      	ldr	r4, [pc, #44]	; (80064b0 <GetDataFromUartQueue+0x38>)
 8006482:	4291      	cmp	r1, r2
 8006484:	bf18      	it	ne
 8006486:	461c      	movne	r4, r3
//    printf("Function : %s : ",__func__);
//    if (HAL_UART_Transmit_DMA(dst, pQueue->Buffer + pQueue->tail, 1) != HAL_OK)
    printf("%c",*(pQueue->Buffer + pQueue->tail));
 8006488:	6863      	ldr	r3, [r4, #4]
 800648a:	4423      	add	r3, r4
 800648c:	7b18      	ldrb	r0, [r3, #12]
 800648e:	f000 f8b9 	bl	8006604 <putchar>
    //if (HAL_UART_Transmit_DMA(&hTerminal, pQueue->Buffer + pQueue->tail, 1) != HAL_OK)
    //{
//       _Error_Handler(__FILE__, __LINE__);
    //}
//    printf("\r\n");
    pQueue->tail++;
 8006492:	6863      	ldr	r3, [r4, #4]
 8006494:	3301      	adds	r3, #1
    if (pQueue->tail >= QUEUE_BUFFER_LENGTH) pQueue->tail = 0;
 8006496:	f5b3 6f80 	cmp.w	r3, #1024	; 0x400
 800649a:	bfa8      	it	ge
 800649c:	2300      	movge	r3, #0
 800649e:	6063      	str	r3, [r4, #4]
    pQueue->data--;
 80064a0:	68a3      	ldr	r3, [r4, #8]
 80064a2:	3b01      	subs	r3, #1
 80064a4:	60a3      	str	r3, [r4, #8]
 80064a6:	bd10      	pop	{r4, pc}
 80064a8:	2000054c 	.word	0x2000054c
 80064ac:	40004400 	.word	0x40004400
 80064b0:	20000958 	.word	0x20000958

080064b4 <HAL_UART_RxCpltCallback>:
{
 80064b4:	b538      	push	{r3, r4, r5, lr}
    pUARTQUEUE pQueue = (huart->Instance == USART2 ? &WifiQueue:&TerminalQueue);
 80064b6:	6802      	ldr	r2, [r0, #0]
 80064b8:	4b11      	ldr	r3, [pc, #68]	; (8006500 <HAL_UART_RxCpltCallback+0x4c>)
 80064ba:	4c12      	ldr	r4, [pc, #72]	; (8006504 <HAL_UART_RxCpltCallback+0x50>)
 80064bc:	429a      	cmp	r2, r3
 80064be:	4b12      	ldr	r3, [pc, #72]	; (8006508 <HAL_UART_RxCpltCallback+0x54>)
 80064c0:	4d12      	ldr	r5, [pc, #72]	; (800650c <HAL_UART_RxCpltCallback+0x58>)
 80064c2:	bf08      	it	eq
 80064c4:	461c      	moveq	r4, r3
 80064c6:	4b12      	ldr	r3, [pc, #72]	; (8006510 <HAL_UART_RxCpltCallback+0x5c>)
 80064c8:	bf08      	it	eq
 80064ca:	461d      	moveq	r5, r3
    pQueue->head++;
 80064cc:	6823      	ldr	r3, [r4, #0]
 80064ce:	3301      	adds	r3, #1
    if (pQueue->head >= QUEUE_BUFFER_LENGTH) pQueue->head = 0;
 80064d0:	f5b3 6f80 	cmp.w	r3, #1024	; 0x400
 80064d4:	bfa8      	it	ge
 80064d6:	2300      	movge	r3, #0
 80064d8:	6023      	str	r3, [r4, #0]
    pQueue->data++;
 80064da:	68a3      	ldr	r3, [r4, #8]
 80064dc:	3301      	adds	r3, #1
    if (pQueue->data >= QUEUE_BUFFER_LENGTH)
 80064de:	f5b3 6f80 	cmp.w	r3, #1024	; 0x400
    pQueue->data++;
 80064e2:	60a3      	str	r3, [r4, #8]
    if (pQueue->data >= QUEUE_BUFFER_LENGTH)
 80064e4:	db01      	blt.n	80064ea <HAL_UART_RxCpltCallback+0x36>
        GetDataFromUartQueue(huart);
 80064e6:	f7ff ffc7 	bl	8006478 <GetDataFromUartQueue>
    HAL_UART_Receive_DMA(dst, pQueue->Buffer + pQueue->head, 1);
 80064ea:	6823      	ldr	r3, [r4, #0]
 80064ec:	f104 010c 	add.w	r1, r4, #12
 80064f0:	4419      	add	r1, r3
 80064f2:	4628      	mov	r0, r5
}
 80064f4:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
    HAL_UART_Receive_DMA(dst, pQueue->Buffer + pQueue->head, 1);
 80064f8:	2201      	movs	r2, #1
 80064fa:	f7ff b941 	b.w	8005780 <HAL_UART_Receive_DMA>
 80064fe:	bf00      	nop
 8006500:	40004400 	.word	0x40004400
 8006504:	2000054c 	.word	0x2000054c
 8006508:	20000958 	.word	0x20000958
 800650c:	2000044c 	.word	0x2000044c
 8006510:	2000050c 	.word	0x2000050c

08006514 <Uart2_Data_Send>:
}
void Uart1_Data_Send(uint8_t* data,uint8_t size){
    HAL_UART_Transmit_DMA(&huart1, data,size); 
}
void Uart2_Data_Send(uint8_t* data,uint8_t size){
    HAL_UART_Transmit_DMA(&huart2, data,size); 
 8006514:	460a      	mov	r2, r1
 8006516:	4601      	mov	r1, r0
 8006518:	4801      	ldr	r0, [pc, #4]	; (8006520 <Uart2_Data_Send+0xc>)
 800651a:	f7ff b8f7 	b.w	800570c <HAL_UART_Transmit_DMA>
 800651e:	bf00      	nop
 8006520:	2000050c 	.word	0x2000050c

08006524 <Reset_Handler>:
  .weak Reset_Handler
  .type Reset_Handler, %function
Reset_Handler:

/* Copy the data segment initializers from flash to SRAM */
  movs r1, #0
 8006524:	2100      	movs	r1, #0
  b LoopCopyDataInit
 8006526:	e003      	b.n	8006530 <LoopCopyDataInit>

08006528 <CopyDataInit>:

CopyDataInit:
  ldr r3, =_sidata
 8006528:	4b0b      	ldr	r3, [pc, #44]	; (8006558 <LoopFillZerobss+0x14>)
  ldr r3, [r3, r1]
 800652a:	585b      	ldr	r3, [r3, r1]
  str r3, [r0, r1]
 800652c:	5043      	str	r3, [r0, r1]
  adds r1, r1, #4
 800652e:	3104      	adds	r1, #4

08006530 <LoopCopyDataInit>:

LoopCopyDataInit:
  ldr r0, =_sdata
 8006530:	480a      	ldr	r0, [pc, #40]	; (800655c <LoopFillZerobss+0x18>)
  ldr r3, =_edata
 8006532:	4b0b      	ldr	r3, [pc, #44]	; (8006560 <LoopFillZerobss+0x1c>)
  adds r2, r0, r1
 8006534:	1842      	adds	r2, r0, r1
  cmp r2, r3
 8006536:	429a      	cmp	r2, r3
  bcc CopyDataInit
 8006538:	d3f6      	bcc.n	8006528 <CopyDataInit>
  ldr r2, =_sbss
 800653a:	4a0a      	ldr	r2, [pc, #40]	; (8006564 <LoopFillZerobss+0x20>)
  b LoopFillZerobss
 800653c:	e002      	b.n	8006544 <LoopFillZerobss>

0800653e <FillZerobss>:
/* Zero fill the bss segment. */
FillZerobss:
  movs r3, #0
 800653e:	2300      	movs	r3, #0
  str r3, [r2], #4
 8006540:	f842 3b04 	str.w	r3, [r2], #4

08006544 <LoopFillZerobss>:

LoopFillZerobss:
  ldr r3, = _ebss
 8006544:	4b08      	ldr	r3, [pc, #32]	; (8006568 <LoopFillZerobss+0x24>)
  cmp r2, r3
 8006546:	429a      	cmp	r2, r3
  bcc FillZerobss
 8006548:	d3f9      	bcc.n	800653e <FillZerobss>

/* Call the clock system intitialization function.*/
    bl  SystemInit
 800654a:	f7ff ff57 	bl	80063fc <SystemInit>
/* Call static constructors */
    bl __libc_init_array
 800654e:	f000 f815 	bl	800657c <__libc_init_array>
/* Call the application's entry point.*/
  bl main
 8006552:	f7ff fb69 	bl	8005c28 <main>
  bx lr
 8006556:	4770      	bx	lr
  ldr r3, =_sidata
 8006558:	08007834 	.word	0x08007834
  ldr r0, =_sdata
 800655c:	20000000 	.word	0x20000000
  ldr r3, =_edata
 8006560:	20000270 	.word	0x20000270
  ldr r2, =_sbss
 8006564:	20000270 	.word	0x20000270
  ldr r3, = _ebss
 8006568:	20000d68 	.word	0x20000d68

0800656c <CAN1_RX1_IRQHandler>:
 * @retval : None
*/
    .section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
  b Infinite_Loop
 800656c:	e7fe      	b.n	800656c <CAN1_RX1_IRQHandler>
	...

08006570 <__errno>:
 8006570:	4b01      	ldr	r3, [pc, #4]	; (8006578 <__errno+0x8>)
 8006572:	6818      	ldr	r0, [r3, #0]
 8006574:	4770      	bx	lr
 8006576:	bf00      	nop
 8006578:	2000020c 	.word	0x2000020c

0800657c <__libc_init_array>:
 800657c:	b570      	push	{r4, r5, r6, lr}
 800657e:	2500      	movs	r5, #0
 8006580:	4e0c      	ldr	r6, [pc, #48]	; (80065b4 <__libc_init_array+0x38>)
 8006582:	4c0d      	ldr	r4, [pc, #52]	; (80065b8 <__libc_init_array+0x3c>)
 8006584:	1ba4      	subs	r4, r4, r6
 8006586:	10a4      	asrs	r4, r4, #2
 8006588:	42a5      	cmp	r5, r4
 800658a:	d109      	bne.n	80065a0 <__libc_init_array+0x24>
 800658c:	f001 f892 	bl	80076b4 <_init>
 8006590:	2500      	movs	r5, #0
 8006592:	4e0a      	ldr	r6, [pc, #40]	; (80065bc <__libc_init_array+0x40>)
 8006594:	4c0a      	ldr	r4, [pc, #40]	; (80065c0 <__libc_init_array+0x44>)
 8006596:	1ba4      	subs	r4, r4, r6
 8006598:	10a4      	asrs	r4, r4, #2
 800659a:	42a5      	cmp	r5, r4
 800659c:	d105      	bne.n	80065aa <__libc_init_array+0x2e>
 800659e:	bd70      	pop	{r4, r5, r6, pc}
 80065a0:	f856 3025 	ldr.w	r3, [r6, r5, lsl #2]
 80065a4:	4798      	blx	r3
 80065a6:	3501      	adds	r5, #1
 80065a8:	e7ee      	b.n	8006588 <__libc_init_array+0xc>
 80065aa:	f856 3025 	ldr.w	r3, [r6, r5, lsl #2]
 80065ae:	4798      	blx	r3
 80065b0:	3501      	adds	r5, #1
 80065b2:	e7f2      	b.n	800659a <__libc_init_array+0x1e>
 80065b4:	0800782c 	.word	0x0800782c
 80065b8:	0800782c 	.word	0x0800782c
 80065bc:	0800782c 	.word	0x0800782c
 80065c0:	08007830 	.word	0x08007830

080065c4 <memset>:
 80065c4:	4603      	mov	r3, r0
 80065c6:	4402      	add	r2, r0
 80065c8:	4293      	cmp	r3, r2
 80065ca:	d100      	bne.n	80065ce <memset+0xa>
 80065cc:	4770      	bx	lr
 80065ce:	f803 1b01 	strb.w	r1, [r3], #1
 80065d2:	e7f9      	b.n	80065c8 <memset+0x4>

080065d4 <iprintf>:
 80065d4:	b40f      	push	{r0, r1, r2, r3}
 80065d6:	4b0a      	ldr	r3, [pc, #40]	; (8006600 <iprintf+0x2c>)
 80065d8:	b513      	push	{r0, r1, r4, lr}
 80065da:	681c      	ldr	r4, [r3, #0]
 80065dc:	b124      	cbz	r4, 80065e8 <iprintf+0x14>
 80065de:	69a3      	ldr	r3, [r4, #24]
 80065e0:	b913      	cbnz	r3, 80065e8 <iprintf+0x14>
 80065e2:	4620      	mov	r0, r4
 80065e4:	f000 faee 	bl	8006bc4 <__sinit>
 80065e8:	ab05      	add	r3, sp, #20
 80065ea:	9a04      	ldr	r2, [sp, #16]
 80065ec:	68a1      	ldr	r1, [r4, #8]
 80065ee:	4620      	mov	r0, r4
 80065f0:	9301      	str	r3, [sp, #4]
 80065f2:	f000 fcaf 	bl	8006f54 <_vfiprintf_r>
 80065f6:	b002      	add	sp, #8
 80065f8:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
 80065fc:	b004      	add	sp, #16
 80065fe:	4770      	bx	lr
 8006600:	2000020c 	.word	0x2000020c

08006604 <putchar>:
 8006604:	b538      	push	{r3, r4, r5, lr}
 8006606:	4b08      	ldr	r3, [pc, #32]	; (8006628 <putchar+0x24>)
 8006608:	4605      	mov	r5, r0
 800660a:	681c      	ldr	r4, [r3, #0]
 800660c:	b124      	cbz	r4, 8006618 <putchar+0x14>
 800660e:	69a3      	ldr	r3, [r4, #24]
 8006610:	b913      	cbnz	r3, 8006618 <putchar+0x14>
 8006612:	4620      	mov	r0, r4
 8006614:	f000 fad6 	bl	8006bc4 <__sinit>
 8006618:	68a2      	ldr	r2, [r4, #8]
 800661a:	4629      	mov	r1, r5
 800661c:	4620      	mov	r0, r4
 800661e:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
 8006622:	f000 bf45 	b.w	80074b0 <_putc_r>
 8006626:	bf00      	nop
 8006628:	2000020c 	.word	0x2000020c

0800662c <_puts_r>:
 800662c:	b570      	push	{r4, r5, r6, lr}
 800662e:	460e      	mov	r6, r1
 8006630:	4605      	mov	r5, r0
 8006632:	b118      	cbz	r0, 800663c <_puts_r+0x10>
 8006634:	6983      	ldr	r3, [r0, #24]
 8006636:	b90b      	cbnz	r3, 800663c <_puts_r+0x10>
 8006638:	f000 fac4 	bl	8006bc4 <__sinit>
 800663c:	69ab      	ldr	r3, [r5, #24]
 800663e:	68ac      	ldr	r4, [r5, #8]
 8006640:	b913      	cbnz	r3, 8006648 <_puts_r+0x1c>
 8006642:	4628      	mov	r0, r5
 8006644:	f000 fabe 	bl	8006bc4 <__sinit>
 8006648:	4b23      	ldr	r3, [pc, #140]	; (80066d8 <_puts_r+0xac>)
 800664a:	429c      	cmp	r4, r3
 800664c:	d117      	bne.n	800667e <_puts_r+0x52>
 800664e:	686c      	ldr	r4, [r5, #4]
 8006650:	89a3      	ldrh	r3, [r4, #12]
 8006652:	071b      	lsls	r3, r3, #28
 8006654:	d51d      	bpl.n	8006692 <_puts_r+0x66>
 8006656:	6923      	ldr	r3, [r4, #16]
 8006658:	b1db      	cbz	r3, 8006692 <_puts_r+0x66>
 800665a:	3e01      	subs	r6, #1
 800665c:	68a3      	ldr	r3, [r4, #8]
 800665e:	f816 1f01 	ldrb.w	r1, [r6, #1]!
 8006662:	3b01      	subs	r3, #1
 8006664:	60a3      	str	r3, [r4, #8]
 8006666:	b9e9      	cbnz	r1, 80066a4 <_puts_r+0x78>
 8006668:	2b00      	cmp	r3, #0
 800666a:	da2e      	bge.n	80066ca <_puts_r+0x9e>
 800666c:	4622      	mov	r2, r4
 800666e:	210a      	movs	r1, #10
 8006670:	4628      	mov	r0, r5
 8006672:	f000 f8f5 	bl	8006860 <__swbuf_r>
 8006676:	3001      	adds	r0, #1
 8006678:	d011      	beq.n	800669e <_puts_r+0x72>
 800667a:	200a      	movs	r0, #10
 800667c:	bd70      	pop	{r4, r5, r6, pc}
 800667e:	4b17      	ldr	r3, [pc, #92]	; (80066dc <_puts_r+0xb0>)
 8006680:	429c      	cmp	r4, r3
 8006682:	d101      	bne.n	8006688 <_puts_r+0x5c>
 8006684:	68ac      	ldr	r4, [r5, #8]
 8006686:	e7e3      	b.n	8006650 <_puts_r+0x24>
 8006688:	4b15      	ldr	r3, [pc, #84]	; (80066e0 <_puts_r+0xb4>)
 800668a:	429c      	cmp	r4, r3
 800668c:	bf08      	it	eq
 800668e:	68ec      	ldreq	r4, [r5, #12]
 8006690:	e7de      	b.n	8006650 <_puts_r+0x24>
 8006692:	4621      	mov	r1, r4
 8006694:	4628      	mov	r0, r5
 8006696:	f000 f935 	bl	8006904 <__swsetup_r>
 800669a:	2800      	cmp	r0, #0
 800669c:	d0dd      	beq.n	800665a <_puts_r+0x2e>
 800669e:	f04f 30ff 	mov.w	r0, #4294967295
 80066a2:	bd70      	pop	{r4, r5, r6, pc}
 80066a4:	2b00      	cmp	r3, #0
 80066a6:	da04      	bge.n	80066b2 <_puts_r+0x86>
 80066a8:	69a2      	ldr	r2, [r4, #24]
 80066aa:	4293      	cmp	r3, r2
 80066ac:	db06      	blt.n	80066bc <_puts_r+0x90>
 80066ae:	290a      	cmp	r1, #10
 80066b0:	d004      	beq.n	80066bc <_puts_r+0x90>
 80066b2:	6823      	ldr	r3, [r4, #0]
 80066b4:	1c5a      	adds	r2, r3, #1
 80066b6:	6022      	str	r2, [r4, #0]
 80066b8:	7019      	strb	r1, [r3, #0]
 80066ba:	e7cf      	b.n	800665c <_puts_r+0x30>
 80066bc:	4622      	mov	r2, r4
 80066be:	4628      	mov	r0, r5
 80066c0:	f000 f8ce 	bl	8006860 <__swbuf_r>
 80066c4:	3001      	adds	r0, #1
 80066c6:	d1c9      	bne.n	800665c <_puts_r+0x30>
 80066c8:	e7e9      	b.n	800669e <_puts_r+0x72>
 80066ca:	200a      	movs	r0, #10
 80066cc:	6823      	ldr	r3, [r4, #0]
 80066ce:	1c5a      	adds	r2, r3, #1
 80066d0:	6022      	str	r2, [r4, #0]
 80066d2:	7018      	strb	r0, [r3, #0]
 80066d4:	bd70      	pop	{r4, r5, r6, pc}
 80066d6:	bf00      	nop
 80066d8:	080077b8 	.word	0x080077b8
 80066dc:	080077d8 	.word	0x080077d8
 80066e0:	08007798 	.word	0x08007798

080066e4 <puts>:
 80066e4:	4b02      	ldr	r3, [pc, #8]	; (80066f0 <puts+0xc>)
 80066e6:	4601      	mov	r1, r0
 80066e8:	6818      	ldr	r0, [r3, #0]
 80066ea:	f7ff bf9f 	b.w	800662c <_puts_r>
 80066ee:	bf00      	nop
 80066f0:	2000020c 	.word	0x2000020c

080066f4 <setbuf>:
 80066f4:	2900      	cmp	r1, #0
 80066f6:	f44f 6380 	mov.w	r3, #1024	; 0x400
 80066fa:	bf0c      	ite	eq
 80066fc:	2202      	moveq	r2, #2
 80066fe:	2200      	movne	r2, #0
 8006700:	f000 b800 	b.w	8006704 <setvbuf>

08006704 <setvbuf>:
 8006704:	e92d 43f7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
 8006708:	461d      	mov	r5, r3
 800670a:	4b51      	ldr	r3, [pc, #324]	; (8006850 <setvbuf+0x14c>)
 800670c:	4604      	mov	r4, r0
 800670e:	681e      	ldr	r6, [r3, #0]
 8006710:	460f      	mov	r7, r1
 8006712:	4690      	mov	r8, r2
 8006714:	b126      	cbz	r6, 8006720 <setvbuf+0x1c>
 8006716:	69b3      	ldr	r3, [r6, #24]
 8006718:	b913      	cbnz	r3, 8006720 <setvbuf+0x1c>
 800671a:	4630      	mov	r0, r6
 800671c:	f000 fa52 	bl	8006bc4 <__sinit>
 8006720:	4b4c      	ldr	r3, [pc, #304]	; (8006854 <setvbuf+0x150>)
 8006722:	429c      	cmp	r4, r3
 8006724:	d152      	bne.n	80067cc <setvbuf+0xc8>
 8006726:	6874      	ldr	r4, [r6, #4]
 8006728:	f1b8 0f02 	cmp.w	r8, #2
 800672c:	d006      	beq.n	800673c <setvbuf+0x38>
 800672e:	f1b8 0f01 	cmp.w	r8, #1
 8006732:	f200 8089 	bhi.w	8006848 <setvbuf+0x144>
 8006736:	2d00      	cmp	r5, #0
 8006738:	f2c0 8086 	blt.w	8006848 <setvbuf+0x144>
 800673c:	4621      	mov	r1, r4
 800673e:	4630      	mov	r0, r6
 8006740:	f000 f9d6 	bl	8006af0 <_fflush_r>
 8006744:	6b61      	ldr	r1, [r4, #52]	; 0x34
 8006746:	b141      	cbz	r1, 800675a <setvbuf+0x56>
 8006748:	f104 0344 	add.w	r3, r4, #68	; 0x44
 800674c:	4299      	cmp	r1, r3
 800674e:	d002      	beq.n	8006756 <setvbuf+0x52>
 8006750:	4630      	mov	r0, r6
 8006752:	f000 fb2d 	bl	8006db0 <_free_r>
 8006756:	2300      	movs	r3, #0
 8006758:	6363      	str	r3, [r4, #52]	; 0x34
 800675a:	2300      	movs	r3, #0
 800675c:	61a3      	str	r3, [r4, #24]
 800675e:	6063      	str	r3, [r4, #4]
 8006760:	89a3      	ldrh	r3, [r4, #12]
 8006762:	061b      	lsls	r3, r3, #24
 8006764:	d503      	bpl.n	800676e <setvbuf+0x6a>
 8006766:	6921      	ldr	r1, [r4, #16]
 8006768:	4630      	mov	r0, r6
 800676a:	f000 fb21 	bl	8006db0 <_free_r>
 800676e:	89a3      	ldrh	r3, [r4, #12]
 8006770:	f1b8 0f02 	cmp.w	r8, #2
 8006774:	f423 634a 	bic.w	r3, r3, #3232	; 0xca0
 8006778:	f023 0303 	bic.w	r3, r3, #3
 800677c:	81a3      	strh	r3, [r4, #12]
 800677e:	d05d      	beq.n	800683c <setvbuf+0x138>
 8006780:	ab01      	add	r3, sp, #4
 8006782:	466a      	mov	r2, sp
 8006784:	4621      	mov	r1, r4
 8006786:	4630      	mov	r0, r6
 8006788:	f000 faa6 	bl	8006cd8 <__swhatbuf_r>
 800678c:	89a3      	ldrh	r3, [r4, #12]
 800678e:	4318      	orrs	r0, r3
 8006790:	81a0      	strh	r0, [r4, #12]
 8006792:	bb2d      	cbnz	r5, 80067e0 <setvbuf+0xdc>
 8006794:	9d00      	ldr	r5, [sp, #0]
 8006796:	4628      	mov	r0, r5
 8006798:	f000 fb02 	bl	8006da0 <malloc>
 800679c:	4607      	mov	r7, r0
 800679e:	2800      	cmp	r0, #0
 80067a0:	d14e      	bne.n	8006840 <setvbuf+0x13c>
 80067a2:	f8dd 9000 	ldr.w	r9, [sp]
 80067a6:	45a9      	cmp	r9, r5
 80067a8:	d13c      	bne.n	8006824 <setvbuf+0x120>
 80067aa:	f04f 30ff 	mov.w	r0, #4294967295
 80067ae:	89a3      	ldrh	r3, [r4, #12]
 80067b0:	f043 0302 	orr.w	r3, r3, #2
 80067b4:	81a3      	strh	r3, [r4, #12]
 80067b6:	2300      	movs	r3, #0
 80067b8:	60a3      	str	r3, [r4, #8]
 80067ba:	f104 0347 	add.w	r3, r4, #71	; 0x47
 80067be:	6023      	str	r3, [r4, #0]
 80067c0:	6123      	str	r3, [r4, #16]
 80067c2:	2301      	movs	r3, #1
 80067c4:	6163      	str	r3, [r4, #20]
 80067c6:	b003      	add	sp, #12
 80067c8:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
 80067cc:	4b22      	ldr	r3, [pc, #136]	; (8006858 <setvbuf+0x154>)
 80067ce:	429c      	cmp	r4, r3
 80067d0:	d101      	bne.n	80067d6 <setvbuf+0xd2>
 80067d2:	68b4      	ldr	r4, [r6, #8]
 80067d4:	e7a8      	b.n	8006728 <setvbuf+0x24>
 80067d6:	4b21      	ldr	r3, [pc, #132]	; (800685c <setvbuf+0x158>)
 80067d8:	429c      	cmp	r4, r3
 80067da:	bf08      	it	eq
 80067dc:	68f4      	ldreq	r4, [r6, #12]
 80067de:	e7a3      	b.n	8006728 <setvbuf+0x24>
 80067e0:	2f00      	cmp	r7, #0
 80067e2:	d0d8      	beq.n	8006796 <setvbuf+0x92>
 80067e4:	69b3      	ldr	r3, [r6, #24]
 80067e6:	b913      	cbnz	r3, 80067ee <setvbuf+0xea>
 80067e8:	4630      	mov	r0, r6
 80067ea:	f000 f9eb 	bl	8006bc4 <__sinit>
 80067ee:	f1b8 0f01 	cmp.w	r8, #1
 80067f2:	bf08      	it	eq
 80067f4:	89a3      	ldrheq	r3, [r4, #12]
 80067f6:	6027      	str	r7, [r4, #0]
 80067f8:	bf04      	itt	eq
 80067fa:	f043 0301 	orreq.w	r3, r3, #1
 80067fe:	81a3      	strheq	r3, [r4, #12]
 8006800:	89a3      	ldrh	r3, [r4, #12]
 8006802:	6127      	str	r7, [r4, #16]
 8006804:	f013 0008 	ands.w	r0, r3, #8
 8006808:	6165      	str	r5, [r4, #20]
 800680a:	d01b      	beq.n	8006844 <setvbuf+0x140>
 800680c:	f013 0001 	ands.w	r0, r3, #1
 8006810:	f04f 0300 	mov.w	r3, #0
 8006814:	bf1f      	itttt	ne
 8006816:	426d      	negne	r5, r5
 8006818:	60a3      	strne	r3, [r4, #8]
 800681a:	61a5      	strne	r5, [r4, #24]
 800681c:	4618      	movne	r0, r3
 800681e:	bf08      	it	eq
 8006820:	60a5      	streq	r5, [r4, #8]
 8006822:	e7d0      	b.n	80067c6 <setvbuf+0xc2>
 8006824:	4648      	mov	r0, r9
 8006826:	f000 fabb 	bl	8006da0 <malloc>
 800682a:	4607      	mov	r7, r0
 800682c:	2800      	cmp	r0, #0
 800682e:	d0bc      	beq.n	80067aa <setvbuf+0xa6>
 8006830:	89a3      	ldrh	r3, [r4, #12]
 8006832:	464d      	mov	r5, r9
 8006834:	f043 0380 	orr.w	r3, r3, #128	; 0x80
 8006838:	81a3      	strh	r3, [r4, #12]
 800683a:	e7d3      	b.n	80067e4 <setvbuf+0xe0>
 800683c:	2000      	movs	r0, #0
 800683e:	e7b6      	b.n	80067ae <setvbuf+0xaa>
 8006840:	46a9      	mov	r9, r5
 8006842:	e7f5      	b.n	8006830 <setvbuf+0x12c>
 8006844:	60a0      	str	r0, [r4, #8]
 8006846:	e7be      	b.n	80067c6 <setvbuf+0xc2>
 8006848:	f04f 30ff 	mov.w	r0, #4294967295
 800684c:	e7bb      	b.n	80067c6 <setvbuf+0xc2>
 800684e:	bf00      	nop
 8006850:	2000020c 	.word	0x2000020c
 8006854:	080077b8 	.word	0x080077b8
 8006858:	080077d8 	.word	0x080077d8
 800685c:	08007798 	.word	0x08007798

08006860 <__swbuf_r>:
 8006860:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 8006862:	460e      	mov	r6, r1
 8006864:	4614      	mov	r4, r2
 8006866:	4605      	mov	r5, r0
 8006868:	b118      	cbz	r0, 8006872 <__swbuf_r+0x12>
 800686a:	6983      	ldr	r3, [r0, #24]
 800686c:	b90b      	cbnz	r3, 8006872 <__swbuf_r+0x12>
 800686e:	f000 f9a9 	bl	8006bc4 <__sinit>
 8006872:	4b21      	ldr	r3, [pc, #132]	; (80068f8 <__swbuf_r+0x98>)
 8006874:	429c      	cmp	r4, r3
 8006876:	d12a      	bne.n	80068ce <__swbuf_r+0x6e>
 8006878:	686c      	ldr	r4, [r5, #4]
 800687a:	69a3      	ldr	r3, [r4, #24]
 800687c:	60a3      	str	r3, [r4, #8]
 800687e:	89a3      	ldrh	r3, [r4, #12]
 8006880:	071a      	lsls	r2, r3, #28
 8006882:	d52e      	bpl.n	80068e2 <__swbuf_r+0x82>
 8006884:	6923      	ldr	r3, [r4, #16]
 8006886:	b363      	cbz	r3, 80068e2 <__swbuf_r+0x82>
 8006888:	6923      	ldr	r3, [r4, #16]
 800688a:	6820      	ldr	r0, [r4, #0]
 800688c:	b2f6      	uxtb	r6, r6
 800688e:	1ac0      	subs	r0, r0, r3
 8006890:	6963      	ldr	r3, [r4, #20]
 8006892:	4637      	mov	r7, r6
 8006894:	4298      	cmp	r0, r3
 8006896:	db04      	blt.n	80068a2 <__swbuf_r+0x42>
 8006898:	4621      	mov	r1, r4
 800689a:	4628      	mov	r0, r5
 800689c:	f000 f928 	bl	8006af0 <_fflush_r>
 80068a0:	bb28      	cbnz	r0, 80068ee <__swbuf_r+0x8e>
 80068a2:	68a3      	ldr	r3, [r4, #8]
 80068a4:	3001      	adds	r0, #1
 80068a6:	3b01      	subs	r3, #1
 80068a8:	60a3      	str	r3, [r4, #8]
 80068aa:	6823      	ldr	r3, [r4, #0]
 80068ac:	1c5a      	adds	r2, r3, #1
 80068ae:	6022      	str	r2, [r4, #0]
 80068b0:	701e      	strb	r6, [r3, #0]
 80068b2:	6963      	ldr	r3, [r4, #20]
 80068b4:	4298      	cmp	r0, r3
 80068b6:	d004      	beq.n	80068c2 <__swbuf_r+0x62>
 80068b8:	89a3      	ldrh	r3, [r4, #12]
 80068ba:	07db      	lsls	r3, r3, #31
 80068bc:	d519      	bpl.n	80068f2 <__swbuf_r+0x92>
 80068be:	2e0a      	cmp	r6, #10
 80068c0:	d117      	bne.n	80068f2 <__swbuf_r+0x92>
 80068c2:	4621      	mov	r1, r4
 80068c4:	4628      	mov	r0, r5
 80068c6:	f000 f913 	bl	8006af0 <_fflush_r>
 80068ca:	b190      	cbz	r0, 80068f2 <__swbuf_r+0x92>
 80068cc:	e00f      	b.n	80068ee <__swbuf_r+0x8e>
 80068ce:	4b0b      	ldr	r3, [pc, #44]	; (80068fc <__swbuf_r+0x9c>)
 80068d0:	429c      	cmp	r4, r3
 80068d2:	d101      	bne.n	80068d8 <__swbuf_r+0x78>
 80068d4:	68ac      	ldr	r4, [r5, #8]
 80068d6:	e7d0      	b.n	800687a <__swbuf_r+0x1a>
 80068d8:	4b09      	ldr	r3, [pc, #36]	; (8006900 <__swbuf_r+0xa0>)
 80068da:	429c      	cmp	r4, r3
 80068dc:	bf08      	it	eq
 80068de:	68ec      	ldreq	r4, [r5, #12]
 80068e0:	e7cb      	b.n	800687a <__swbuf_r+0x1a>
 80068e2:	4621      	mov	r1, r4
 80068e4:	4628      	mov	r0, r5
 80068e6:	f000 f80d 	bl	8006904 <__swsetup_r>
 80068ea:	2800      	cmp	r0, #0
 80068ec:	d0cc      	beq.n	8006888 <__swbuf_r+0x28>
 80068ee:	f04f 37ff 	mov.w	r7, #4294967295
 80068f2:	4638      	mov	r0, r7
 80068f4:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
 80068f6:	bf00      	nop
 80068f8:	080077b8 	.word	0x080077b8
 80068fc:	080077d8 	.word	0x080077d8
 8006900:	08007798 	.word	0x08007798

08006904 <__swsetup_r>:
 8006904:	4b32      	ldr	r3, [pc, #200]	; (80069d0 <__swsetup_r+0xcc>)
 8006906:	b570      	push	{r4, r5, r6, lr}
 8006908:	681d      	ldr	r5, [r3, #0]
 800690a:	4606      	mov	r6, r0
 800690c:	460c      	mov	r4, r1
 800690e:	b125      	cbz	r5, 800691a <__swsetup_r+0x16>
 8006910:	69ab      	ldr	r3, [r5, #24]
 8006912:	b913      	cbnz	r3, 800691a <__swsetup_r+0x16>
 8006914:	4628      	mov	r0, r5
 8006916:	f000 f955 	bl	8006bc4 <__sinit>
 800691a:	4b2e      	ldr	r3, [pc, #184]	; (80069d4 <__swsetup_r+0xd0>)
 800691c:	429c      	cmp	r4, r3
 800691e:	d10f      	bne.n	8006940 <__swsetup_r+0x3c>
 8006920:	686c      	ldr	r4, [r5, #4]
 8006922:	f9b4 300c 	ldrsh.w	r3, [r4, #12]
 8006926:	b29a      	uxth	r2, r3
 8006928:	0715      	lsls	r5, r2, #28
 800692a:	d42c      	bmi.n	8006986 <__swsetup_r+0x82>
 800692c:	06d0      	lsls	r0, r2, #27
 800692e:	d411      	bmi.n	8006954 <__swsetup_r+0x50>
 8006930:	2209      	movs	r2, #9
 8006932:	6032      	str	r2, [r6, #0]
 8006934:	f043 0340 	orr.w	r3, r3, #64	; 0x40
 8006938:	81a3      	strh	r3, [r4, #12]
 800693a:	f04f 30ff 	mov.w	r0, #4294967295
 800693e:	bd70      	pop	{r4, r5, r6, pc}
 8006940:	4b25      	ldr	r3, [pc, #148]	; (80069d8 <__swsetup_r+0xd4>)
 8006942:	429c      	cmp	r4, r3
 8006944:	d101      	bne.n	800694a <__swsetup_r+0x46>
 8006946:	68ac      	ldr	r4, [r5, #8]
 8006948:	e7eb      	b.n	8006922 <__swsetup_r+0x1e>
 800694a:	4b24      	ldr	r3, [pc, #144]	; (80069dc <__swsetup_r+0xd8>)
 800694c:	429c      	cmp	r4, r3
 800694e:	bf08      	it	eq
 8006950:	68ec      	ldreq	r4, [r5, #12]
 8006952:	e7e6      	b.n	8006922 <__swsetup_r+0x1e>
 8006954:	0751      	lsls	r1, r2, #29
 8006956:	d512      	bpl.n	800697e <__swsetup_r+0x7a>
 8006958:	6b61      	ldr	r1, [r4, #52]	; 0x34
 800695a:	b141      	cbz	r1, 800696e <__swsetup_r+0x6a>
 800695c:	f104 0344 	add.w	r3, r4, #68	; 0x44
 8006960:	4299      	cmp	r1, r3
 8006962:	d002      	beq.n	800696a <__swsetup_r+0x66>
 8006964:	4630      	mov	r0, r6
 8006966:	f000 fa23 	bl	8006db0 <_free_r>
 800696a:	2300      	movs	r3, #0
 800696c:	6363      	str	r3, [r4, #52]	; 0x34
 800696e:	89a3      	ldrh	r3, [r4, #12]
 8006970:	f023 0324 	bic.w	r3, r3, #36	; 0x24
 8006974:	81a3      	strh	r3, [r4, #12]
 8006976:	2300      	movs	r3, #0
 8006978:	6063      	str	r3, [r4, #4]
 800697a:	6923      	ldr	r3, [r4, #16]
 800697c:	6023      	str	r3, [r4, #0]
 800697e:	89a3      	ldrh	r3, [r4, #12]
 8006980:	f043 0308 	orr.w	r3, r3, #8
 8006984:	81a3      	strh	r3, [r4, #12]
 8006986:	6923      	ldr	r3, [r4, #16]
 8006988:	b94b      	cbnz	r3, 800699e <__swsetup_r+0x9a>
 800698a:	89a3      	ldrh	r3, [r4, #12]
 800698c:	f403 7320 	and.w	r3, r3, #640	; 0x280
 8006990:	f5b3 7f00 	cmp.w	r3, #512	; 0x200
 8006994:	d003      	beq.n	800699e <__swsetup_r+0x9a>
 8006996:	4621      	mov	r1, r4
 8006998:	4630      	mov	r0, r6
 800699a:	f000 f9c1 	bl	8006d20 <__smakebuf_r>
 800699e:	89a2      	ldrh	r2, [r4, #12]
 80069a0:	f012 0301 	ands.w	r3, r2, #1
 80069a4:	d00c      	beq.n	80069c0 <__swsetup_r+0xbc>
 80069a6:	2300      	movs	r3, #0
 80069a8:	60a3      	str	r3, [r4, #8]
 80069aa:	6963      	ldr	r3, [r4, #20]
 80069ac:	425b      	negs	r3, r3
 80069ae:	61a3      	str	r3, [r4, #24]
 80069b0:	6923      	ldr	r3, [r4, #16]
 80069b2:	b953      	cbnz	r3, 80069ca <__swsetup_r+0xc6>
 80069b4:	f9b4 300c 	ldrsh.w	r3, [r4, #12]
 80069b8:	f013 0080 	ands.w	r0, r3, #128	; 0x80
 80069bc:	d1ba      	bne.n	8006934 <__swsetup_r+0x30>
 80069be:	bd70      	pop	{r4, r5, r6, pc}
 80069c0:	0792      	lsls	r2, r2, #30
 80069c2:	bf58      	it	pl
 80069c4:	6963      	ldrpl	r3, [r4, #20]
 80069c6:	60a3      	str	r3, [r4, #8]
 80069c8:	e7f2      	b.n	80069b0 <__swsetup_r+0xac>
 80069ca:	2000      	movs	r0, #0
 80069cc:	e7f7      	b.n	80069be <__swsetup_r+0xba>
 80069ce:	bf00      	nop
 80069d0:	2000020c 	.word	0x2000020c
 80069d4:	080077b8 	.word	0x080077b8
 80069d8:	080077d8 	.word	0x080077d8
 80069dc:	08007798 	.word	0x08007798

080069e0 <__sflush_r>:
 80069e0:	898a      	ldrh	r2, [r1, #12]
 80069e2:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
 80069e6:	4605      	mov	r5, r0
 80069e8:	0710      	lsls	r0, r2, #28
 80069ea:	460c      	mov	r4, r1
 80069ec:	d45a      	bmi.n	8006aa4 <__sflush_r+0xc4>
 80069ee:	684b      	ldr	r3, [r1, #4]
 80069f0:	2b00      	cmp	r3, #0
 80069f2:	dc05      	bgt.n	8006a00 <__sflush_r+0x20>
 80069f4:	6c0b      	ldr	r3, [r1, #64]	; 0x40
 80069f6:	2b00      	cmp	r3, #0
 80069f8:	dc02      	bgt.n	8006a00 <__sflush_r+0x20>
 80069fa:	2000      	movs	r0, #0
 80069fc:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
 8006a00:	6ae6      	ldr	r6, [r4, #44]	; 0x2c
 8006a02:	2e00      	cmp	r6, #0
 8006a04:	d0f9      	beq.n	80069fa <__sflush_r+0x1a>
 8006a06:	2300      	movs	r3, #0
 8006a08:	f412 5280 	ands.w	r2, r2, #4096	; 0x1000
 8006a0c:	682f      	ldr	r7, [r5, #0]
 8006a0e:	602b      	str	r3, [r5, #0]
 8006a10:	d033      	beq.n	8006a7a <__sflush_r+0x9a>
 8006a12:	6d60      	ldr	r0, [r4, #84]	; 0x54
 8006a14:	89a3      	ldrh	r3, [r4, #12]
 8006a16:	075a      	lsls	r2, r3, #29
 8006a18:	d505      	bpl.n	8006a26 <__sflush_r+0x46>
 8006a1a:	6863      	ldr	r3, [r4, #4]
 8006a1c:	1ac0      	subs	r0, r0, r3
 8006a1e:	6b63      	ldr	r3, [r4, #52]	; 0x34
 8006a20:	b10b      	cbz	r3, 8006a26 <__sflush_r+0x46>
 8006a22:	6c23      	ldr	r3, [r4, #64]	; 0x40
 8006a24:	1ac0      	subs	r0, r0, r3
 8006a26:	2300      	movs	r3, #0
 8006a28:	4602      	mov	r2, r0
 8006a2a:	6ae6      	ldr	r6, [r4, #44]	; 0x2c
 8006a2c:	6a21      	ldr	r1, [r4, #32]
 8006a2e:	4628      	mov	r0, r5
 8006a30:	47b0      	blx	r6
 8006a32:	1c43      	adds	r3, r0, #1
 8006a34:	89a3      	ldrh	r3, [r4, #12]
 8006a36:	d106      	bne.n	8006a46 <__sflush_r+0x66>
 8006a38:	6829      	ldr	r1, [r5, #0]
 8006a3a:	291d      	cmp	r1, #29
 8006a3c:	d84b      	bhi.n	8006ad6 <__sflush_r+0xf6>
 8006a3e:	4a2b      	ldr	r2, [pc, #172]	; (8006aec <__sflush_r+0x10c>)
 8006a40:	40ca      	lsrs	r2, r1
 8006a42:	07d6      	lsls	r6, r2, #31
 8006a44:	d547      	bpl.n	8006ad6 <__sflush_r+0xf6>
 8006a46:	2200      	movs	r2, #0
 8006a48:	6062      	str	r2, [r4, #4]
 8006a4a:	6922      	ldr	r2, [r4, #16]
 8006a4c:	04d9      	lsls	r1, r3, #19
 8006a4e:	6022      	str	r2, [r4, #0]
 8006a50:	d504      	bpl.n	8006a5c <__sflush_r+0x7c>
 8006a52:	1c42      	adds	r2, r0, #1
 8006a54:	d101      	bne.n	8006a5a <__sflush_r+0x7a>
 8006a56:	682b      	ldr	r3, [r5, #0]
 8006a58:	b903      	cbnz	r3, 8006a5c <__sflush_r+0x7c>
 8006a5a:	6560      	str	r0, [r4, #84]	; 0x54
 8006a5c:	6b61      	ldr	r1, [r4, #52]	; 0x34
 8006a5e:	602f      	str	r7, [r5, #0]
 8006a60:	2900      	cmp	r1, #0
 8006a62:	d0ca      	beq.n	80069fa <__sflush_r+0x1a>
 8006a64:	f104 0344 	add.w	r3, r4, #68	; 0x44
 8006a68:	4299      	cmp	r1, r3
 8006a6a:	d002      	beq.n	8006a72 <__sflush_r+0x92>
 8006a6c:	4628      	mov	r0, r5
 8006a6e:	f000 f99f 	bl	8006db0 <_free_r>
 8006a72:	2000      	movs	r0, #0
 8006a74:	6360      	str	r0, [r4, #52]	; 0x34
 8006a76:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
 8006a7a:	6a21      	ldr	r1, [r4, #32]
 8006a7c:	2301      	movs	r3, #1
 8006a7e:	4628      	mov	r0, r5
 8006a80:	47b0      	blx	r6
 8006a82:	1c41      	adds	r1, r0, #1
 8006a84:	d1c6      	bne.n	8006a14 <__sflush_r+0x34>
 8006a86:	682b      	ldr	r3, [r5, #0]
 8006a88:	2b00      	cmp	r3, #0
 8006a8a:	d0c3      	beq.n	8006a14 <__sflush_r+0x34>
 8006a8c:	2b1d      	cmp	r3, #29
 8006a8e:	d001      	beq.n	8006a94 <__sflush_r+0xb4>
 8006a90:	2b16      	cmp	r3, #22
 8006a92:	d101      	bne.n	8006a98 <__sflush_r+0xb8>
 8006a94:	602f      	str	r7, [r5, #0]
 8006a96:	e7b0      	b.n	80069fa <__sflush_r+0x1a>
 8006a98:	89a3      	ldrh	r3, [r4, #12]
 8006a9a:	f043 0340 	orr.w	r3, r3, #64	; 0x40
 8006a9e:	81a3      	strh	r3, [r4, #12]
 8006aa0:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
 8006aa4:	690f      	ldr	r7, [r1, #16]
 8006aa6:	2f00      	cmp	r7, #0
 8006aa8:	d0a7      	beq.n	80069fa <__sflush_r+0x1a>
 8006aaa:	0793      	lsls	r3, r2, #30
 8006aac:	bf18      	it	ne
 8006aae:	2300      	movne	r3, #0
 8006ab0:	680e      	ldr	r6, [r1, #0]
 8006ab2:	bf08      	it	eq
 8006ab4:	694b      	ldreq	r3, [r1, #20]
 8006ab6:	eba6 0807 	sub.w	r8, r6, r7
 8006aba:	600f      	str	r7, [r1, #0]
 8006abc:	608b      	str	r3, [r1, #8]
 8006abe:	f1b8 0f00 	cmp.w	r8, #0
 8006ac2:	dd9a      	ble.n	80069fa <__sflush_r+0x1a>
 8006ac4:	4643      	mov	r3, r8
 8006ac6:	463a      	mov	r2, r7
 8006ac8:	6a21      	ldr	r1, [r4, #32]
 8006aca:	4628      	mov	r0, r5
 8006acc:	6aa6      	ldr	r6, [r4, #40]	; 0x28
 8006ace:	47b0      	blx	r6
 8006ad0:	2800      	cmp	r0, #0
 8006ad2:	dc07      	bgt.n	8006ae4 <__sflush_r+0x104>
 8006ad4:	89a3      	ldrh	r3, [r4, #12]
 8006ad6:	f043 0340 	orr.w	r3, r3, #64	; 0x40
 8006ada:	81a3      	strh	r3, [r4, #12]
 8006adc:	f04f 30ff 	mov.w	r0, #4294967295
 8006ae0:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
 8006ae4:	4407      	add	r7, r0
 8006ae6:	eba8 0800 	sub.w	r8, r8, r0
 8006aea:	e7e8      	b.n	8006abe <__sflush_r+0xde>
 8006aec:	20400001 	.word	0x20400001

08006af0 <_fflush_r>:
 8006af0:	b538      	push	{r3, r4, r5, lr}
 8006af2:	690b      	ldr	r3, [r1, #16]
 8006af4:	4605      	mov	r5, r0
 8006af6:	460c      	mov	r4, r1
 8006af8:	b1db      	cbz	r3, 8006b32 <_fflush_r+0x42>
 8006afa:	b118      	cbz	r0, 8006b04 <_fflush_r+0x14>
 8006afc:	6983      	ldr	r3, [r0, #24]
 8006afe:	b90b      	cbnz	r3, 8006b04 <_fflush_r+0x14>
 8006b00:	f000 f860 	bl	8006bc4 <__sinit>
 8006b04:	4b0c      	ldr	r3, [pc, #48]	; (8006b38 <_fflush_r+0x48>)
 8006b06:	429c      	cmp	r4, r3
 8006b08:	d109      	bne.n	8006b1e <_fflush_r+0x2e>
 8006b0a:	686c      	ldr	r4, [r5, #4]
 8006b0c:	f9b4 300c 	ldrsh.w	r3, [r4, #12]
 8006b10:	b17b      	cbz	r3, 8006b32 <_fflush_r+0x42>
 8006b12:	4621      	mov	r1, r4
 8006b14:	4628      	mov	r0, r5
 8006b16:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
 8006b1a:	f7ff bf61 	b.w	80069e0 <__sflush_r>
 8006b1e:	4b07      	ldr	r3, [pc, #28]	; (8006b3c <_fflush_r+0x4c>)
 8006b20:	429c      	cmp	r4, r3
 8006b22:	d101      	bne.n	8006b28 <_fflush_r+0x38>
 8006b24:	68ac      	ldr	r4, [r5, #8]
 8006b26:	e7f1      	b.n	8006b0c <_fflush_r+0x1c>
 8006b28:	4b05      	ldr	r3, [pc, #20]	; (8006b40 <_fflush_r+0x50>)
 8006b2a:	429c      	cmp	r4, r3
 8006b2c:	bf08      	it	eq
 8006b2e:	68ec      	ldreq	r4, [r5, #12]
 8006b30:	e7ec      	b.n	8006b0c <_fflush_r+0x1c>
 8006b32:	2000      	movs	r0, #0
 8006b34:	bd38      	pop	{r3, r4, r5, pc}
 8006b36:	bf00      	nop
 8006b38:	080077b8 	.word	0x080077b8
 8006b3c:	080077d8 	.word	0x080077d8
 8006b40:	08007798 	.word	0x08007798

08006b44 <_cleanup_r>:
 8006b44:	4901      	ldr	r1, [pc, #4]	; (8006b4c <_cleanup_r+0x8>)
 8006b46:	f000 b8a9 	b.w	8006c9c <_fwalk_reent>
 8006b4a:	bf00      	nop
 8006b4c:	08006af1 	.word	0x08006af1

08006b50 <std.isra.0>:
 8006b50:	2300      	movs	r3, #0
 8006b52:	b510      	push	{r4, lr}
 8006b54:	4604      	mov	r4, r0
 8006b56:	6003      	str	r3, [r0, #0]
 8006b58:	6043      	str	r3, [r0, #4]
 8006b5a:	6083      	str	r3, [r0, #8]
 8006b5c:	8181      	strh	r1, [r0, #12]
 8006b5e:	6643      	str	r3, [r0, #100]	; 0x64
 8006b60:	81c2      	strh	r2, [r0, #14]
 8006b62:	6103      	str	r3, [r0, #16]
 8006b64:	6143      	str	r3, [r0, #20]
 8006b66:	6183      	str	r3, [r0, #24]
 8006b68:	4619      	mov	r1, r3
 8006b6a:	2208      	movs	r2, #8
 8006b6c:	305c      	adds	r0, #92	; 0x5c
 8006b6e:	f7ff fd29 	bl	80065c4 <memset>
 8006b72:	4b05      	ldr	r3, [pc, #20]	; (8006b88 <std.isra.0+0x38>)
 8006b74:	6224      	str	r4, [r4, #32]
 8006b76:	6263      	str	r3, [r4, #36]	; 0x24
 8006b78:	4b04      	ldr	r3, [pc, #16]	; (8006b8c <std.isra.0+0x3c>)
 8006b7a:	62a3      	str	r3, [r4, #40]	; 0x28
 8006b7c:	4b04      	ldr	r3, [pc, #16]	; (8006b90 <std.isra.0+0x40>)
 8006b7e:	62e3      	str	r3, [r4, #44]	; 0x2c
 8006b80:	4b04      	ldr	r3, [pc, #16]	; (8006b94 <std.isra.0+0x44>)
 8006b82:	6323      	str	r3, [r4, #48]	; 0x30
 8006b84:	bd10      	pop	{r4, pc}
 8006b86:	bf00      	nop
 8006b88:	0800753d 	.word	0x0800753d
 8006b8c:	0800755f 	.word	0x0800755f
 8006b90:	08007597 	.word	0x08007597
 8006b94:	080075bb 	.word	0x080075bb

08006b98 <__sfmoreglue>:
 8006b98:	b570      	push	{r4, r5, r6, lr}
 8006b9a:	2568      	movs	r5, #104	; 0x68
 8006b9c:	1e4a      	subs	r2, r1, #1
 8006b9e:	4355      	muls	r5, r2
 8006ba0:	460e      	mov	r6, r1
 8006ba2:	f105 0174 	add.w	r1, r5, #116	; 0x74
 8006ba6:	f000 f94f 	bl	8006e48 <_malloc_r>
 8006baa:	4604      	mov	r4, r0
 8006bac:	b140      	cbz	r0, 8006bc0 <__sfmoreglue+0x28>
 8006bae:	2100      	movs	r1, #0
 8006bb0:	e880 0042 	stmia.w	r0, {r1, r6}
 8006bb4:	300c      	adds	r0, #12
 8006bb6:	60a0      	str	r0, [r4, #8]
 8006bb8:	f105 0268 	add.w	r2, r5, #104	; 0x68
 8006bbc:	f7ff fd02 	bl	80065c4 <memset>
 8006bc0:	4620      	mov	r0, r4
 8006bc2:	bd70      	pop	{r4, r5, r6, pc}

08006bc4 <__sinit>:
 8006bc4:	6983      	ldr	r3, [r0, #24]
 8006bc6:	b510      	push	{r4, lr}
 8006bc8:	4604      	mov	r4, r0
 8006bca:	bb33      	cbnz	r3, 8006c1a <__sinit+0x56>
 8006bcc:	6483      	str	r3, [r0, #72]	; 0x48
 8006bce:	64c3      	str	r3, [r0, #76]	; 0x4c
 8006bd0:	6503      	str	r3, [r0, #80]	; 0x50
 8006bd2:	4b12      	ldr	r3, [pc, #72]	; (8006c1c <__sinit+0x58>)
 8006bd4:	4a12      	ldr	r2, [pc, #72]	; (8006c20 <__sinit+0x5c>)
 8006bd6:	681b      	ldr	r3, [r3, #0]
 8006bd8:	6282      	str	r2, [r0, #40]	; 0x28
 8006bda:	4298      	cmp	r0, r3
 8006bdc:	bf04      	itt	eq
 8006bde:	2301      	moveq	r3, #1
 8006be0:	6183      	streq	r3, [r0, #24]
 8006be2:	f000 f81f 	bl	8006c24 <__sfp>
 8006be6:	6060      	str	r0, [r4, #4]
 8006be8:	4620      	mov	r0, r4
 8006bea:	f000 f81b 	bl	8006c24 <__sfp>
 8006bee:	60a0      	str	r0, [r4, #8]
 8006bf0:	4620      	mov	r0, r4
 8006bf2:	f000 f817 	bl	8006c24 <__sfp>
 8006bf6:	2200      	movs	r2, #0
 8006bf8:	60e0      	str	r0, [r4, #12]
 8006bfa:	2104      	movs	r1, #4
 8006bfc:	6860      	ldr	r0, [r4, #4]
 8006bfe:	f7ff ffa7 	bl	8006b50 <std.isra.0>
 8006c02:	2201      	movs	r2, #1
 8006c04:	2109      	movs	r1, #9
 8006c06:	68a0      	ldr	r0, [r4, #8]
 8006c08:	f7ff ffa2 	bl	8006b50 <std.isra.0>
 8006c0c:	2202      	movs	r2, #2
 8006c0e:	2112      	movs	r1, #18
 8006c10:	68e0      	ldr	r0, [r4, #12]
 8006c12:	f7ff ff9d 	bl	8006b50 <std.isra.0>
 8006c16:	2301      	movs	r3, #1
 8006c18:	61a3      	str	r3, [r4, #24]
 8006c1a:	bd10      	pop	{r4, pc}
 8006c1c:	08007794 	.word	0x08007794
 8006c20:	08006b45 	.word	0x08006b45

08006c24 <__sfp>:
 8006c24:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 8006c26:	4b1c      	ldr	r3, [pc, #112]	; (8006c98 <__sfp+0x74>)
 8006c28:	4607      	mov	r7, r0
 8006c2a:	681e      	ldr	r6, [r3, #0]
 8006c2c:	69b3      	ldr	r3, [r6, #24]
 8006c2e:	b913      	cbnz	r3, 8006c36 <__sfp+0x12>
 8006c30:	4630      	mov	r0, r6
 8006c32:	f7ff ffc7 	bl	8006bc4 <__sinit>
 8006c36:	3648      	adds	r6, #72	; 0x48
 8006c38:	68b4      	ldr	r4, [r6, #8]
 8006c3a:	6873      	ldr	r3, [r6, #4]
 8006c3c:	3b01      	subs	r3, #1
 8006c3e:	d503      	bpl.n	8006c48 <__sfp+0x24>
 8006c40:	6833      	ldr	r3, [r6, #0]
 8006c42:	b133      	cbz	r3, 8006c52 <__sfp+0x2e>
 8006c44:	6836      	ldr	r6, [r6, #0]
 8006c46:	e7f7      	b.n	8006c38 <__sfp+0x14>
 8006c48:	f9b4 500c 	ldrsh.w	r5, [r4, #12]
 8006c4c:	b16d      	cbz	r5, 8006c6a <__sfp+0x46>
 8006c4e:	3468      	adds	r4, #104	; 0x68
 8006c50:	e7f4      	b.n	8006c3c <__sfp+0x18>
 8006c52:	2104      	movs	r1, #4
 8006c54:	4638      	mov	r0, r7
 8006c56:	f7ff ff9f 	bl	8006b98 <__sfmoreglue>
 8006c5a:	6030      	str	r0, [r6, #0]
 8006c5c:	2800      	cmp	r0, #0
 8006c5e:	d1f1      	bne.n	8006c44 <__sfp+0x20>
 8006c60:	230c      	movs	r3, #12
 8006c62:	4604      	mov	r4, r0
 8006c64:	603b      	str	r3, [r7, #0]
 8006c66:	4620      	mov	r0, r4
 8006c68:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
 8006c6a:	f64f 73ff 	movw	r3, #65535	; 0xffff
 8006c6e:	81e3      	strh	r3, [r4, #14]
 8006c70:	2301      	movs	r3, #1
 8006c72:	6665      	str	r5, [r4, #100]	; 0x64
 8006c74:	81a3      	strh	r3, [r4, #12]
 8006c76:	6025      	str	r5, [r4, #0]
 8006c78:	60a5      	str	r5, [r4, #8]
 8006c7a:	6065      	str	r5, [r4, #4]
 8006c7c:	6125      	str	r5, [r4, #16]
 8006c7e:	6165      	str	r5, [r4, #20]
 8006c80:	61a5      	str	r5, [r4, #24]
 8006c82:	2208      	movs	r2, #8
 8006c84:	4629      	mov	r1, r5
 8006c86:	f104 005c 	add.w	r0, r4, #92	; 0x5c
 8006c8a:	f7ff fc9b 	bl	80065c4 <memset>
 8006c8e:	6365      	str	r5, [r4, #52]	; 0x34
 8006c90:	63a5      	str	r5, [r4, #56]	; 0x38
 8006c92:	64a5      	str	r5, [r4, #72]	; 0x48
 8006c94:	64e5      	str	r5, [r4, #76]	; 0x4c
 8006c96:	e7e6      	b.n	8006c66 <__sfp+0x42>
 8006c98:	08007794 	.word	0x08007794

08006c9c <_fwalk_reent>:
 8006c9c:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
 8006ca0:	4680      	mov	r8, r0
 8006ca2:	4689      	mov	r9, r1
 8006ca4:	2600      	movs	r6, #0
 8006ca6:	f100 0448 	add.w	r4, r0, #72	; 0x48
 8006caa:	b914      	cbnz	r4, 8006cb2 <_fwalk_reent+0x16>
 8006cac:	4630      	mov	r0, r6
 8006cae:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
 8006cb2:	68a5      	ldr	r5, [r4, #8]
 8006cb4:	6867      	ldr	r7, [r4, #4]
 8006cb6:	3f01      	subs	r7, #1
 8006cb8:	d501      	bpl.n	8006cbe <_fwalk_reent+0x22>
 8006cba:	6824      	ldr	r4, [r4, #0]
 8006cbc:	e7f5      	b.n	8006caa <_fwalk_reent+0xe>
 8006cbe:	89ab      	ldrh	r3, [r5, #12]
 8006cc0:	2b01      	cmp	r3, #1
 8006cc2:	d907      	bls.n	8006cd4 <_fwalk_reent+0x38>
 8006cc4:	f9b5 300e 	ldrsh.w	r3, [r5, #14]
 8006cc8:	3301      	adds	r3, #1
 8006cca:	d003      	beq.n	8006cd4 <_fwalk_reent+0x38>
 8006ccc:	4629      	mov	r1, r5
 8006cce:	4640      	mov	r0, r8
 8006cd0:	47c8      	blx	r9
 8006cd2:	4306      	orrs	r6, r0
 8006cd4:	3568      	adds	r5, #104	; 0x68
 8006cd6:	e7ee      	b.n	8006cb6 <_fwalk_reent+0x1a>

08006cd8 <__swhatbuf_r>:
 8006cd8:	b570      	push	{r4, r5, r6, lr}
 8006cda:	460e      	mov	r6, r1
 8006cdc:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 8006ce0:	b090      	sub	sp, #64	; 0x40
 8006ce2:	2900      	cmp	r1, #0
 8006ce4:	4614      	mov	r4, r2
 8006ce6:	461d      	mov	r5, r3
 8006ce8:	da07      	bge.n	8006cfa <__swhatbuf_r+0x22>
 8006cea:	2300      	movs	r3, #0
 8006cec:	602b      	str	r3, [r5, #0]
 8006cee:	89b3      	ldrh	r3, [r6, #12]
 8006cf0:	061a      	lsls	r2, r3, #24
 8006cf2:	d410      	bmi.n	8006d16 <__swhatbuf_r+0x3e>
 8006cf4:	f44f 6380 	mov.w	r3, #1024	; 0x400
 8006cf8:	e00e      	b.n	8006d18 <__swhatbuf_r+0x40>
 8006cfa:	aa01      	add	r2, sp, #4
 8006cfc:	f000 fc84 	bl	8007608 <_fstat_r>
 8006d00:	2800      	cmp	r0, #0
 8006d02:	dbf2      	blt.n	8006cea <__swhatbuf_r+0x12>
 8006d04:	9a02      	ldr	r2, [sp, #8]
 8006d06:	f402 4270 	and.w	r2, r2, #61440	; 0xf000
 8006d0a:	f5a2 5300 	sub.w	r3, r2, #8192	; 0x2000
 8006d0e:	425a      	negs	r2, r3
 8006d10:	415a      	adcs	r2, r3
 8006d12:	602a      	str	r2, [r5, #0]
 8006d14:	e7ee      	b.n	8006cf4 <__swhatbuf_r+0x1c>
 8006d16:	2340      	movs	r3, #64	; 0x40
 8006d18:	2000      	movs	r0, #0
 8006d1a:	6023      	str	r3, [r4, #0]
 8006d1c:	b010      	add	sp, #64	; 0x40
 8006d1e:	bd70      	pop	{r4, r5, r6, pc}

08006d20 <__smakebuf_r>:
 8006d20:	898b      	ldrh	r3, [r1, #12]
 8006d22:	b573      	push	{r0, r1, r4, r5, r6, lr}
 8006d24:	079d      	lsls	r5, r3, #30
 8006d26:	4606      	mov	r6, r0
 8006d28:	460c      	mov	r4, r1
 8006d2a:	d507      	bpl.n	8006d3c <__smakebuf_r+0x1c>
 8006d2c:	f104 0347 	add.w	r3, r4, #71	; 0x47
 8006d30:	6023      	str	r3, [r4, #0]
 8006d32:	6123      	str	r3, [r4, #16]
 8006d34:	2301      	movs	r3, #1
 8006d36:	6163      	str	r3, [r4, #20]
 8006d38:	b002      	add	sp, #8
 8006d3a:	bd70      	pop	{r4, r5, r6, pc}
 8006d3c:	ab01      	add	r3, sp, #4
 8006d3e:	466a      	mov	r2, sp
 8006d40:	f7ff ffca 	bl	8006cd8 <__swhatbuf_r>
 8006d44:	9900      	ldr	r1, [sp, #0]
 8006d46:	4605      	mov	r5, r0
 8006d48:	4630      	mov	r0, r6
 8006d4a:	f000 f87d 	bl	8006e48 <_malloc_r>
 8006d4e:	b948      	cbnz	r0, 8006d64 <__smakebuf_r+0x44>
 8006d50:	f9b4 300c 	ldrsh.w	r3, [r4, #12]
 8006d54:	059a      	lsls	r2, r3, #22
 8006d56:	d4ef      	bmi.n	8006d38 <__smakebuf_r+0x18>
 8006d58:	f023 0303 	bic.w	r3, r3, #3
 8006d5c:	f043 0302 	orr.w	r3, r3, #2
 8006d60:	81a3      	strh	r3, [r4, #12]
 8006d62:	e7e3      	b.n	8006d2c <__smakebuf_r+0xc>
 8006d64:	4b0d      	ldr	r3, [pc, #52]	; (8006d9c <__smakebuf_r+0x7c>)
 8006d66:	62b3      	str	r3, [r6, #40]	; 0x28
 8006d68:	89a3      	ldrh	r3, [r4, #12]
 8006d6a:	6020      	str	r0, [r4, #0]
 8006d6c:	f043 0380 	orr.w	r3, r3, #128	; 0x80
 8006d70:	81a3      	strh	r3, [r4, #12]
 8006d72:	9b00      	ldr	r3, [sp, #0]
 8006d74:	6120      	str	r0, [r4, #16]
 8006d76:	6163      	str	r3, [r4, #20]
 8006d78:	9b01      	ldr	r3, [sp, #4]
 8006d7a:	b15b      	cbz	r3, 8006d94 <__smakebuf_r+0x74>
 8006d7c:	f9b4 100e 	ldrsh.w	r1, [r4, #14]
 8006d80:	4630      	mov	r0, r6
 8006d82:	f000 fc53 	bl	800762c <_isatty_r>
 8006d86:	b128      	cbz	r0, 8006d94 <__smakebuf_r+0x74>
 8006d88:	89a3      	ldrh	r3, [r4, #12]
 8006d8a:	f023 0303 	bic.w	r3, r3, #3
 8006d8e:	f043 0301 	orr.w	r3, r3, #1
 8006d92:	81a3      	strh	r3, [r4, #12]
 8006d94:	89a3      	ldrh	r3, [r4, #12]
 8006d96:	431d      	orrs	r5, r3
 8006d98:	81a5      	strh	r5, [r4, #12]
 8006d9a:	e7cd      	b.n	8006d38 <__smakebuf_r+0x18>
 8006d9c:	08006b45 	.word	0x08006b45

08006da0 <malloc>:
 8006da0:	4b02      	ldr	r3, [pc, #8]	; (8006dac <malloc+0xc>)
 8006da2:	4601      	mov	r1, r0
 8006da4:	6818      	ldr	r0, [r3, #0]
 8006da6:	f000 b84f 	b.w	8006e48 <_malloc_r>
 8006daa:	bf00      	nop
 8006dac:	2000020c 	.word	0x2000020c

08006db0 <_free_r>:
 8006db0:	b538      	push	{r3, r4, r5, lr}
 8006db2:	4605      	mov	r5, r0
 8006db4:	2900      	cmp	r1, #0
 8006db6:	d043      	beq.n	8006e40 <_free_r+0x90>
 8006db8:	f851 3c04 	ldr.w	r3, [r1, #-4]
 8006dbc:	1f0c      	subs	r4, r1, #4
 8006dbe:	2b00      	cmp	r3, #0
 8006dc0:	bfb8      	it	lt
 8006dc2:	18e4      	addlt	r4, r4, r3
 8006dc4:	f000 fc62 	bl	800768c <__malloc_lock>
 8006dc8:	4a1e      	ldr	r2, [pc, #120]	; (8006e44 <_free_r+0x94>)
 8006dca:	6813      	ldr	r3, [r2, #0]
 8006dcc:	4610      	mov	r0, r2
 8006dce:	b933      	cbnz	r3, 8006dde <_free_r+0x2e>
 8006dd0:	6063      	str	r3, [r4, #4]
 8006dd2:	6014      	str	r4, [r2, #0]
 8006dd4:	4628      	mov	r0, r5
 8006dd6:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
 8006dda:	f000 bc58 	b.w	800768e <__malloc_unlock>
 8006dde:	42a3      	cmp	r3, r4
 8006de0:	d90b      	bls.n	8006dfa <_free_r+0x4a>
 8006de2:	6821      	ldr	r1, [r4, #0]
 8006de4:	1862      	adds	r2, r4, r1
 8006de6:	4293      	cmp	r3, r2
 8006de8:	bf01      	itttt	eq
 8006dea:	681a      	ldreq	r2, [r3, #0]
 8006dec:	685b      	ldreq	r3, [r3, #4]
 8006dee:	1852      	addeq	r2, r2, r1
 8006df0:	6022      	streq	r2, [r4, #0]
 8006df2:	6063      	str	r3, [r4, #4]
 8006df4:	6004      	str	r4, [r0, #0]
 8006df6:	e7ed      	b.n	8006dd4 <_free_r+0x24>
 8006df8:	4613      	mov	r3, r2
 8006dfa:	685a      	ldr	r2, [r3, #4]
 8006dfc:	b10a      	cbz	r2, 8006e02 <_free_r+0x52>
 8006dfe:	42a2      	cmp	r2, r4
 8006e00:	d9fa      	bls.n	8006df8 <_free_r+0x48>
 8006e02:	6819      	ldr	r1, [r3, #0]
 8006e04:	1858      	adds	r0, r3, r1
 8006e06:	42a0      	cmp	r0, r4
 8006e08:	d10b      	bne.n	8006e22 <_free_r+0x72>
 8006e0a:	6820      	ldr	r0, [r4, #0]
 8006e0c:	4401      	add	r1, r0
 8006e0e:	1858      	adds	r0, r3, r1
 8006e10:	4282      	cmp	r2, r0
 8006e12:	6019      	str	r1, [r3, #0]
 8006e14:	d1de      	bne.n	8006dd4 <_free_r+0x24>
 8006e16:	6810      	ldr	r0, [r2, #0]
 8006e18:	6852      	ldr	r2, [r2, #4]
 8006e1a:	4401      	add	r1, r0
 8006e1c:	6019      	str	r1, [r3, #0]
 8006e1e:	605a      	str	r2, [r3, #4]
 8006e20:	e7d8      	b.n	8006dd4 <_free_r+0x24>
 8006e22:	d902      	bls.n	8006e2a <_free_r+0x7a>
 8006e24:	230c      	movs	r3, #12
 8006e26:	602b      	str	r3, [r5, #0]
 8006e28:	e7d4      	b.n	8006dd4 <_free_r+0x24>
 8006e2a:	6820      	ldr	r0, [r4, #0]
 8006e2c:	1821      	adds	r1, r4, r0
 8006e2e:	428a      	cmp	r2, r1
 8006e30:	bf01      	itttt	eq
 8006e32:	6811      	ldreq	r1, [r2, #0]
 8006e34:	6852      	ldreq	r2, [r2, #4]
 8006e36:	1809      	addeq	r1, r1, r0
 8006e38:	6021      	streq	r1, [r4, #0]
 8006e3a:	6062      	str	r2, [r4, #4]
 8006e3c:	605c      	str	r4, [r3, #4]
 8006e3e:	e7c9      	b.n	8006dd4 <_free_r+0x24>
 8006e40:	bd38      	pop	{r3, r4, r5, pc}
 8006e42:	bf00      	nop
 8006e44:	200002a0 	.word	0x200002a0

08006e48 <_malloc_r>:
 8006e48:	b570      	push	{r4, r5, r6, lr}
 8006e4a:	1ccd      	adds	r5, r1, #3
 8006e4c:	f025 0503 	bic.w	r5, r5, #3
 8006e50:	3508      	adds	r5, #8
 8006e52:	2d0c      	cmp	r5, #12
 8006e54:	bf38      	it	cc
 8006e56:	250c      	movcc	r5, #12
 8006e58:	2d00      	cmp	r5, #0
 8006e5a:	4606      	mov	r6, r0
 8006e5c:	db01      	blt.n	8006e62 <_malloc_r+0x1a>
 8006e5e:	42a9      	cmp	r1, r5
 8006e60:	d903      	bls.n	8006e6a <_malloc_r+0x22>
 8006e62:	230c      	movs	r3, #12
 8006e64:	6033      	str	r3, [r6, #0]
 8006e66:	2000      	movs	r0, #0
 8006e68:	bd70      	pop	{r4, r5, r6, pc}
 8006e6a:	f000 fc0f 	bl	800768c <__malloc_lock>
 8006e6e:	4a23      	ldr	r2, [pc, #140]	; (8006efc <_malloc_r+0xb4>)
 8006e70:	6814      	ldr	r4, [r2, #0]
 8006e72:	4621      	mov	r1, r4
 8006e74:	b991      	cbnz	r1, 8006e9c <_malloc_r+0x54>
 8006e76:	4c22      	ldr	r4, [pc, #136]	; (8006f00 <_malloc_r+0xb8>)
 8006e78:	6823      	ldr	r3, [r4, #0]
 8006e7a:	b91b      	cbnz	r3, 8006e84 <_malloc_r+0x3c>
 8006e7c:	4630      	mov	r0, r6
 8006e7e:	f000 fb4d 	bl	800751c <_sbrk_r>
 8006e82:	6020      	str	r0, [r4, #0]
 8006e84:	4629      	mov	r1, r5
 8006e86:	4630      	mov	r0, r6
 8006e88:	f000 fb48 	bl	800751c <_sbrk_r>
 8006e8c:	1c43      	adds	r3, r0, #1
 8006e8e:	d126      	bne.n	8006ede <_malloc_r+0x96>
 8006e90:	230c      	movs	r3, #12
 8006e92:	4630      	mov	r0, r6
 8006e94:	6033      	str	r3, [r6, #0]
 8006e96:	f000 fbfa 	bl	800768e <__malloc_unlock>
 8006e9a:	e7e4      	b.n	8006e66 <_malloc_r+0x1e>
 8006e9c:	680b      	ldr	r3, [r1, #0]
 8006e9e:	1b5b      	subs	r3, r3, r5
 8006ea0:	d41a      	bmi.n	8006ed8 <_malloc_r+0x90>
 8006ea2:	2b0b      	cmp	r3, #11
 8006ea4:	d90f      	bls.n	8006ec6 <_malloc_r+0x7e>
 8006ea6:	600b      	str	r3, [r1, #0]
 8006ea8:	18cc      	adds	r4, r1, r3
 8006eaa:	50cd      	str	r5, [r1, r3]
 8006eac:	4630      	mov	r0, r6
 8006eae:	f000 fbee 	bl	800768e <__malloc_unlock>
 8006eb2:	f104 000b 	add.w	r0, r4, #11
 8006eb6:	1d23      	adds	r3, r4, #4
 8006eb8:	f020 0007 	bic.w	r0, r0, #7
 8006ebc:	1ac3      	subs	r3, r0, r3
 8006ebe:	d01b      	beq.n	8006ef8 <_malloc_r+0xb0>
 8006ec0:	425a      	negs	r2, r3
 8006ec2:	50e2      	str	r2, [r4, r3]
 8006ec4:	bd70      	pop	{r4, r5, r6, pc}
 8006ec6:	428c      	cmp	r4, r1
 8006ec8:	bf0b      	itete	eq
 8006eca:	6863      	ldreq	r3, [r4, #4]
 8006ecc:	684b      	ldrne	r3, [r1, #4]
 8006ece:	6013      	streq	r3, [r2, #0]
 8006ed0:	6063      	strne	r3, [r4, #4]
 8006ed2:	bf18      	it	ne
 8006ed4:	460c      	movne	r4, r1
 8006ed6:	e7e9      	b.n	8006eac <_malloc_r+0x64>
 8006ed8:	460c      	mov	r4, r1
 8006eda:	6849      	ldr	r1, [r1, #4]
 8006edc:	e7ca      	b.n	8006e74 <_malloc_r+0x2c>
 8006ede:	1cc4      	adds	r4, r0, #3
 8006ee0:	f024 0403 	bic.w	r4, r4, #3
 8006ee4:	42a0      	cmp	r0, r4
 8006ee6:	d005      	beq.n	8006ef4 <_malloc_r+0xac>
 8006ee8:	1a21      	subs	r1, r4, r0
 8006eea:	4630      	mov	r0, r6
 8006eec:	f000 fb16 	bl	800751c <_sbrk_r>
 8006ef0:	3001      	adds	r0, #1
 8006ef2:	d0cd      	beq.n	8006e90 <_malloc_r+0x48>
 8006ef4:	6025      	str	r5, [r4, #0]
 8006ef6:	e7d9      	b.n	8006eac <_malloc_r+0x64>
 8006ef8:	bd70      	pop	{r4, r5, r6, pc}
 8006efa:	bf00      	nop
 8006efc:	200002a0 	.word	0x200002a0
 8006f00:	200002a4 	.word	0x200002a4

08006f04 <__sfputc_r>:
 8006f04:	6893      	ldr	r3, [r2, #8]
 8006f06:	b410      	push	{r4}
 8006f08:	3b01      	subs	r3, #1
 8006f0a:	2b00      	cmp	r3, #0
 8006f0c:	6093      	str	r3, [r2, #8]
 8006f0e:	da08      	bge.n	8006f22 <__sfputc_r+0x1e>
 8006f10:	6994      	ldr	r4, [r2, #24]
 8006f12:	42a3      	cmp	r3, r4
 8006f14:	db02      	blt.n	8006f1c <__sfputc_r+0x18>
 8006f16:	b2cb      	uxtb	r3, r1
 8006f18:	2b0a      	cmp	r3, #10
 8006f1a:	d102      	bne.n	8006f22 <__sfputc_r+0x1e>
 8006f1c:	bc10      	pop	{r4}
 8006f1e:	f7ff bc9f 	b.w	8006860 <__swbuf_r>
 8006f22:	6813      	ldr	r3, [r2, #0]
 8006f24:	1c58      	adds	r0, r3, #1
 8006f26:	6010      	str	r0, [r2, #0]
 8006f28:	7019      	strb	r1, [r3, #0]
 8006f2a:	b2c8      	uxtb	r0, r1
 8006f2c:	bc10      	pop	{r4}
 8006f2e:	4770      	bx	lr

08006f30 <__sfputs_r>:
 8006f30:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 8006f32:	4606      	mov	r6, r0
 8006f34:	460f      	mov	r7, r1
 8006f36:	4614      	mov	r4, r2
 8006f38:	18d5      	adds	r5, r2, r3
 8006f3a:	42ac      	cmp	r4, r5
 8006f3c:	d101      	bne.n	8006f42 <__sfputs_r+0x12>
 8006f3e:	2000      	movs	r0, #0
 8006f40:	e007      	b.n	8006f52 <__sfputs_r+0x22>
 8006f42:	463a      	mov	r2, r7
 8006f44:	f814 1b01 	ldrb.w	r1, [r4], #1
 8006f48:	4630      	mov	r0, r6
 8006f4a:	f7ff ffdb 	bl	8006f04 <__sfputc_r>
 8006f4e:	1c43      	adds	r3, r0, #1
 8006f50:	d1f3      	bne.n	8006f3a <__sfputs_r+0xa>
 8006f52:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}

08006f54 <_vfiprintf_r>:
 8006f54:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
 8006f58:	b09d      	sub	sp, #116	; 0x74
 8006f5a:	460c      	mov	r4, r1
 8006f5c:	4617      	mov	r7, r2
 8006f5e:	9303      	str	r3, [sp, #12]
 8006f60:	4606      	mov	r6, r0
 8006f62:	b118      	cbz	r0, 8006f6c <_vfiprintf_r+0x18>
 8006f64:	6983      	ldr	r3, [r0, #24]
 8006f66:	b90b      	cbnz	r3, 8006f6c <_vfiprintf_r+0x18>
 8006f68:	f7ff fe2c 	bl	8006bc4 <__sinit>
 8006f6c:	4b7c      	ldr	r3, [pc, #496]	; (8007160 <_vfiprintf_r+0x20c>)
 8006f6e:	429c      	cmp	r4, r3
 8006f70:	d157      	bne.n	8007022 <_vfiprintf_r+0xce>
 8006f72:	6874      	ldr	r4, [r6, #4]
 8006f74:	89a3      	ldrh	r3, [r4, #12]
 8006f76:	0718      	lsls	r0, r3, #28
 8006f78:	d55d      	bpl.n	8007036 <_vfiprintf_r+0xe2>
 8006f7a:	6923      	ldr	r3, [r4, #16]
 8006f7c:	2b00      	cmp	r3, #0
 8006f7e:	d05a      	beq.n	8007036 <_vfiprintf_r+0xe2>
 8006f80:	2300      	movs	r3, #0
 8006f82:	9309      	str	r3, [sp, #36]	; 0x24
 8006f84:	2320      	movs	r3, #32
 8006f86:	f88d 3029 	strb.w	r3, [sp, #41]	; 0x29
 8006f8a:	2330      	movs	r3, #48	; 0x30
 8006f8c:	f04f 0b01 	mov.w	fp, #1
 8006f90:	f88d 302a 	strb.w	r3, [sp, #42]	; 0x2a
 8006f94:	46b8      	mov	r8, r7
 8006f96:	4645      	mov	r5, r8
 8006f98:	f815 3b01 	ldrb.w	r3, [r5], #1
 8006f9c:	2b00      	cmp	r3, #0
 8006f9e:	d155      	bne.n	800704c <_vfiprintf_r+0xf8>
 8006fa0:	ebb8 0a07 	subs.w	sl, r8, r7
 8006fa4:	d00b      	beq.n	8006fbe <_vfiprintf_r+0x6a>
 8006fa6:	4653      	mov	r3, sl
 8006fa8:	463a      	mov	r2, r7
 8006faa:	4621      	mov	r1, r4
 8006fac:	4630      	mov	r0, r6
 8006fae:	f7ff ffbf 	bl	8006f30 <__sfputs_r>
 8006fb2:	3001      	adds	r0, #1
 8006fb4:	f000 80c4 	beq.w	8007140 <_vfiprintf_r+0x1ec>
 8006fb8:	9b09      	ldr	r3, [sp, #36]	; 0x24
 8006fba:	4453      	add	r3, sl
 8006fbc:	9309      	str	r3, [sp, #36]	; 0x24
 8006fbe:	f898 3000 	ldrb.w	r3, [r8]
 8006fc2:	2b00      	cmp	r3, #0
 8006fc4:	f000 80bc 	beq.w	8007140 <_vfiprintf_r+0x1ec>
 8006fc8:	2300      	movs	r3, #0
 8006fca:	f04f 32ff 	mov.w	r2, #4294967295
 8006fce:	9304      	str	r3, [sp, #16]
 8006fd0:	9307      	str	r3, [sp, #28]
 8006fd2:	9205      	str	r2, [sp, #20]
 8006fd4:	9306      	str	r3, [sp, #24]
 8006fd6:	f88d 3053 	strb.w	r3, [sp, #83]	; 0x53
 8006fda:	931a      	str	r3, [sp, #104]	; 0x68
 8006fdc:	2205      	movs	r2, #5
 8006fde:	7829      	ldrb	r1, [r5, #0]
 8006fe0:	4860      	ldr	r0, [pc, #384]	; (8007164 <_vfiprintf_r+0x210>)
 8006fe2:	f000 fb45 	bl	8007670 <memchr>
 8006fe6:	f105 0801 	add.w	r8, r5, #1
 8006fea:	9b04      	ldr	r3, [sp, #16]
 8006fec:	2800      	cmp	r0, #0
 8006fee:	d131      	bne.n	8007054 <_vfiprintf_r+0x100>
 8006ff0:	06d9      	lsls	r1, r3, #27
 8006ff2:	bf44      	itt	mi
 8006ff4:	2220      	movmi	r2, #32
 8006ff6:	f88d 2053 	strbmi.w	r2, [sp, #83]	; 0x53
 8006ffa:	071a      	lsls	r2, r3, #28
 8006ffc:	bf44      	itt	mi
 8006ffe:	222b      	movmi	r2, #43	; 0x2b
 8007000:	f88d 2053 	strbmi.w	r2, [sp, #83]	; 0x53
 8007004:	782a      	ldrb	r2, [r5, #0]
 8007006:	2a2a      	cmp	r2, #42	; 0x2a
 8007008:	d02c      	beq.n	8007064 <_vfiprintf_r+0x110>
 800700a:	2100      	movs	r1, #0
 800700c:	200a      	movs	r0, #10
 800700e:	9a07      	ldr	r2, [sp, #28]
 8007010:	46a8      	mov	r8, r5
 8007012:	f898 3000 	ldrb.w	r3, [r8]
 8007016:	3501      	adds	r5, #1
 8007018:	3b30      	subs	r3, #48	; 0x30
 800701a:	2b09      	cmp	r3, #9
 800701c:	d96d      	bls.n	80070fa <_vfiprintf_r+0x1a6>
 800701e:	b371      	cbz	r1, 800707e <_vfiprintf_r+0x12a>
 8007020:	e026      	b.n	8007070 <_vfiprintf_r+0x11c>
 8007022:	4b51      	ldr	r3, [pc, #324]	; (8007168 <_vfiprintf_r+0x214>)
 8007024:	429c      	cmp	r4, r3
 8007026:	d101      	bne.n	800702c <_vfiprintf_r+0xd8>
 8007028:	68b4      	ldr	r4, [r6, #8]
 800702a:	e7a3      	b.n	8006f74 <_vfiprintf_r+0x20>
 800702c:	4b4f      	ldr	r3, [pc, #316]	; (800716c <_vfiprintf_r+0x218>)
 800702e:	429c      	cmp	r4, r3
 8007030:	bf08      	it	eq
 8007032:	68f4      	ldreq	r4, [r6, #12]
 8007034:	e79e      	b.n	8006f74 <_vfiprintf_r+0x20>
 8007036:	4621      	mov	r1, r4
 8007038:	4630      	mov	r0, r6
 800703a:	f7ff fc63 	bl	8006904 <__swsetup_r>
 800703e:	2800      	cmp	r0, #0
 8007040:	d09e      	beq.n	8006f80 <_vfiprintf_r+0x2c>
 8007042:	f04f 30ff 	mov.w	r0, #4294967295
 8007046:	b01d      	add	sp, #116	; 0x74
 8007048:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
 800704c:	2b25      	cmp	r3, #37	; 0x25
 800704e:	d0a7      	beq.n	8006fa0 <_vfiprintf_r+0x4c>
 8007050:	46a8      	mov	r8, r5
 8007052:	e7a0      	b.n	8006f96 <_vfiprintf_r+0x42>
 8007054:	4a43      	ldr	r2, [pc, #268]	; (8007164 <_vfiprintf_r+0x210>)
 8007056:	4645      	mov	r5, r8
 8007058:	1a80      	subs	r0, r0, r2
 800705a:	fa0b f000 	lsl.w	r0, fp, r0
 800705e:	4318      	orrs	r0, r3
 8007060:	9004      	str	r0, [sp, #16]
 8007062:	e7bb      	b.n	8006fdc <_vfiprintf_r+0x88>
 8007064:	9a03      	ldr	r2, [sp, #12]
 8007066:	1d11      	adds	r1, r2, #4
 8007068:	6812      	ldr	r2, [r2, #0]
 800706a:	9103      	str	r1, [sp, #12]
 800706c:	2a00      	cmp	r2, #0
 800706e:	db01      	blt.n	8007074 <_vfiprintf_r+0x120>
 8007070:	9207      	str	r2, [sp, #28]
 8007072:	e004      	b.n	800707e <_vfiprintf_r+0x12a>
 8007074:	4252      	negs	r2, r2
 8007076:	f043 0302 	orr.w	r3, r3, #2
 800707a:	9207      	str	r2, [sp, #28]
 800707c:	9304      	str	r3, [sp, #16]
 800707e:	f898 3000 	ldrb.w	r3, [r8]
 8007082:	2b2e      	cmp	r3, #46	; 0x2e
 8007084:	d110      	bne.n	80070a8 <_vfiprintf_r+0x154>
 8007086:	f898 3001 	ldrb.w	r3, [r8, #1]
 800708a:	f108 0101 	add.w	r1, r8, #1
 800708e:	2b2a      	cmp	r3, #42	; 0x2a
 8007090:	d137      	bne.n	8007102 <_vfiprintf_r+0x1ae>
 8007092:	9b03      	ldr	r3, [sp, #12]
 8007094:	f108 0802 	add.w	r8, r8, #2
 8007098:	1d1a      	adds	r2, r3, #4
 800709a:	681b      	ldr	r3, [r3, #0]
 800709c:	9203      	str	r2, [sp, #12]
 800709e:	2b00      	cmp	r3, #0
 80070a0:	bfb8      	it	lt
 80070a2:	f04f 33ff 	movlt.w	r3, #4294967295
 80070a6:	9305      	str	r3, [sp, #20]
 80070a8:	4d31      	ldr	r5, [pc, #196]	; (8007170 <_vfiprintf_r+0x21c>)
 80070aa:	2203      	movs	r2, #3
 80070ac:	f898 1000 	ldrb.w	r1, [r8]
 80070b0:	4628      	mov	r0, r5
 80070b2:	f000 fadd 	bl	8007670 <memchr>
 80070b6:	b140      	cbz	r0, 80070ca <_vfiprintf_r+0x176>
 80070b8:	2340      	movs	r3, #64	; 0x40
 80070ba:	1b40      	subs	r0, r0, r5
 80070bc:	fa03 f000 	lsl.w	r0, r3, r0
 80070c0:	9b04      	ldr	r3, [sp, #16]
 80070c2:	f108 0801 	add.w	r8, r8, #1
 80070c6:	4303      	orrs	r3, r0
 80070c8:	9304      	str	r3, [sp, #16]
 80070ca:	f898 1000 	ldrb.w	r1, [r8]
 80070ce:	2206      	movs	r2, #6
 80070d0:	4828      	ldr	r0, [pc, #160]	; (8007174 <_vfiprintf_r+0x220>)
 80070d2:	f108 0701 	add.w	r7, r8, #1
 80070d6:	f88d 1028 	strb.w	r1, [sp, #40]	; 0x28
 80070da:	f000 fac9 	bl	8007670 <memchr>
 80070de:	2800      	cmp	r0, #0
 80070e0:	d034      	beq.n	800714c <_vfiprintf_r+0x1f8>
 80070e2:	4b25      	ldr	r3, [pc, #148]	; (8007178 <_vfiprintf_r+0x224>)
 80070e4:	bb03      	cbnz	r3, 8007128 <_vfiprintf_r+0x1d4>
 80070e6:	9b03      	ldr	r3, [sp, #12]
 80070e8:	3307      	adds	r3, #7
 80070ea:	f023 0307 	bic.w	r3, r3, #7
 80070ee:	3308      	adds	r3, #8
 80070f0:	9303      	str	r3, [sp, #12]
 80070f2:	9b09      	ldr	r3, [sp, #36]	; 0x24
 80070f4:	444b      	add	r3, r9
 80070f6:	9309      	str	r3, [sp, #36]	; 0x24
 80070f8:	e74c      	b.n	8006f94 <_vfiprintf_r+0x40>
 80070fa:	fb00 3202 	mla	r2, r0, r2, r3
 80070fe:	2101      	movs	r1, #1
 8007100:	e786      	b.n	8007010 <_vfiprintf_r+0xbc>
 8007102:	2300      	movs	r3, #0
 8007104:	250a      	movs	r5, #10
 8007106:	4618      	mov	r0, r3
 8007108:	9305      	str	r3, [sp, #20]
 800710a:	4688      	mov	r8, r1
 800710c:	f898 2000 	ldrb.w	r2, [r8]
 8007110:	3101      	adds	r1, #1
 8007112:	3a30      	subs	r2, #48	; 0x30
 8007114:	2a09      	cmp	r2, #9
 8007116:	d903      	bls.n	8007120 <_vfiprintf_r+0x1cc>
 8007118:	2b00      	cmp	r3, #0
 800711a:	d0c5      	beq.n	80070a8 <_vfiprintf_r+0x154>
 800711c:	9005      	str	r0, [sp, #20]
 800711e:	e7c3      	b.n	80070a8 <_vfiprintf_r+0x154>
 8007120:	fb05 2000 	mla	r0, r5, r0, r2
 8007124:	2301      	movs	r3, #1
 8007126:	e7f0      	b.n	800710a <_vfiprintf_r+0x1b6>
 8007128:	ab03      	add	r3, sp, #12
 800712a:	9300      	str	r3, [sp, #0]
 800712c:	4622      	mov	r2, r4
 800712e:	4b13      	ldr	r3, [pc, #76]	; (800717c <_vfiprintf_r+0x228>)
 8007130:	a904      	add	r1, sp, #16
 8007132:	4630      	mov	r0, r6
 8007134:	f3af 8000 	nop.w
 8007138:	f1b0 3fff 	cmp.w	r0, #4294967295
 800713c:	4681      	mov	r9, r0
 800713e:	d1d8      	bne.n	80070f2 <_vfiprintf_r+0x19e>
 8007140:	89a3      	ldrh	r3, [r4, #12]
 8007142:	065b      	lsls	r3, r3, #25
 8007144:	f53f af7d 	bmi.w	8007042 <_vfiprintf_r+0xee>
 8007148:	9809      	ldr	r0, [sp, #36]	; 0x24
 800714a:	e77c      	b.n	8007046 <_vfiprintf_r+0xf2>
 800714c:	ab03      	add	r3, sp, #12
 800714e:	9300      	str	r3, [sp, #0]
 8007150:	4622      	mov	r2, r4
 8007152:	4b0a      	ldr	r3, [pc, #40]	; (800717c <_vfiprintf_r+0x228>)
 8007154:	a904      	add	r1, sp, #16
 8007156:	4630      	mov	r0, r6
 8007158:	f000 f88a 	bl	8007270 <_printf_i>
 800715c:	e7ec      	b.n	8007138 <_vfiprintf_r+0x1e4>
 800715e:	bf00      	nop
 8007160:	080077b8 	.word	0x080077b8
 8007164:	080077f8 	.word	0x080077f8
 8007168:	080077d8 	.word	0x080077d8
 800716c:	08007798 	.word	0x08007798
 8007170:	080077fe 	.word	0x080077fe
 8007174:	08007802 	.word	0x08007802
 8007178:	00000000 	.word	0x00000000
 800717c:	08006f31 	.word	0x08006f31

08007180 <_printf_common>:
 8007180:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
 8007184:	4691      	mov	r9, r2
 8007186:	461f      	mov	r7, r3
 8007188:	688a      	ldr	r2, [r1, #8]
 800718a:	690b      	ldr	r3, [r1, #16]
 800718c:	4606      	mov	r6, r0
 800718e:	4293      	cmp	r3, r2
 8007190:	bfb8      	it	lt
 8007192:	4613      	movlt	r3, r2
 8007194:	f8c9 3000 	str.w	r3, [r9]
 8007198:	f891 2043 	ldrb.w	r2, [r1, #67]	; 0x43
 800719c:	460c      	mov	r4, r1
 800719e:	f8dd 8020 	ldr.w	r8, [sp, #32]
 80071a2:	b112      	cbz	r2, 80071aa <_printf_common+0x2a>
 80071a4:	3301      	adds	r3, #1
 80071a6:	f8c9 3000 	str.w	r3, [r9]
 80071aa:	6823      	ldr	r3, [r4, #0]
 80071ac:	0699      	lsls	r1, r3, #26
 80071ae:	bf42      	ittt	mi
 80071b0:	f8d9 3000 	ldrmi.w	r3, [r9]
 80071b4:	3302      	addmi	r3, #2
 80071b6:	f8c9 3000 	strmi.w	r3, [r9]
 80071ba:	6825      	ldr	r5, [r4, #0]
 80071bc:	f015 0506 	ands.w	r5, r5, #6
 80071c0:	d107      	bne.n	80071d2 <_printf_common+0x52>
 80071c2:	f104 0a19 	add.w	sl, r4, #25
 80071c6:	68e3      	ldr	r3, [r4, #12]
 80071c8:	f8d9 2000 	ldr.w	r2, [r9]
 80071cc:	1a9b      	subs	r3, r3, r2
 80071ce:	429d      	cmp	r5, r3
 80071d0:	db2a      	blt.n	8007228 <_printf_common+0xa8>
 80071d2:	f894 3043 	ldrb.w	r3, [r4, #67]	; 0x43
 80071d6:	6822      	ldr	r2, [r4, #0]
 80071d8:	3300      	adds	r3, #0
 80071da:	bf18      	it	ne
 80071dc:	2301      	movne	r3, #1
 80071de:	0692      	lsls	r2, r2, #26
 80071e0:	d42f      	bmi.n	8007242 <_printf_common+0xc2>
 80071e2:	f104 0243 	add.w	r2, r4, #67	; 0x43
 80071e6:	4639      	mov	r1, r7
 80071e8:	4630      	mov	r0, r6
 80071ea:	47c0      	blx	r8
 80071ec:	3001      	adds	r0, #1
 80071ee:	d022      	beq.n	8007236 <_printf_common+0xb6>
 80071f0:	6823      	ldr	r3, [r4, #0]
 80071f2:	68e5      	ldr	r5, [r4, #12]
 80071f4:	f003 0306 	and.w	r3, r3, #6
 80071f8:	2b04      	cmp	r3, #4
 80071fa:	bf18      	it	ne
 80071fc:	2500      	movne	r5, #0
 80071fe:	f8d9 2000 	ldr.w	r2, [r9]
 8007202:	f04f 0900 	mov.w	r9, #0
 8007206:	bf08      	it	eq
 8007208:	1aad      	subeq	r5, r5, r2
 800720a:	68a3      	ldr	r3, [r4, #8]
 800720c:	6922      	ldr	r2, [r4, #16]
 800720e:	bf08      	it	eq
 8007210:	ea25 75e5 	biceq.w	r5, r5, r5, asr #31
 8007214:	4293      	cmp	r3, r2
 8007216:	bfc4      	itt	gt
 8007218:	1a9b      	subgt	r3, r3, r2
 800721a:	18ed      	addgt	r5, r5, r3
 800721c:	341a      	adds	r4, #26
 800721e:	454d      	cmp	r5, r9
 8007220:	d11b      	bne.n	800725a <_printf_common+0xda>
 8007222:	2000      	movs	r0, #0
 8007224:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 8007228:	2301      	movs	r3, #1
 800722a:	4652      	mov	r2, sl
 800722c:	4639      	mov	r1, r7
 800722e:	4630      	mov	r0, r6
 8007230:	47c0      	blx	r8
 8007232:	3001      	adds	r0, #1
 8007234:	d103      	bne.n	800723e <_printf_common+0xbe>
 8007236:	f04f 30ff 	mov.w	r0, #4294967295
 800723a:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 800723e:	3501      	adds	r5, #1
 8007240:	e7c1      	b.n	80071c6 <_printf_common+0x46>
 8007242:	2030      	movs	r0, #48	; 0x30
 8007244:	18e1      	adds	r1, r4, r3
 8007246:	f881 0043 	strb.w	r0, [r1, #67]	; 0x43
 800724a:	1c5a      	adds	r2, r3, #1
 800724c:	f894 1045 	ldrb.w	r1, [r4, #69]	; 0x45
 8007250:	4422      	add	r2, r4
 8007252:	3302      	adds	r3, #2
 8007254:	f882 1043 	strb.w	r1, [r2, #67]	; 0x43
 8007258:	e7c3      	b.n	80071e2 <_printf_common+0x62>
 800725a:	2301      	movs	r3, #1
 800725c:	4622      	mov	r2, r4
 800725e:	4639      	mov	r1, r7
 8007260:	4630      	mov	r0, r6
 8007262:	47c0      	blx	r8
 8007264:	3001      	adds	r0, #1
 8007266:	d0e6      	beq.n	8007236 <_printf_common+0xb6>
 8007268:	f109 0901 	add.w	r9, r9, #1
 800726c:	e7d7      	b.n	800721e <_printf_common+0x9e>
	...

08007270 <_printf_i>:
 8007270:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr}
 8007274:	4617      	mov	r7, r2
 8007276:	7e0a      	ldrb	r2, [r1, #24]
 8007278:	b085      	sub	sp, #20
 800727a:	2a6e      	cmp	r2, #110	; 0x6e
 800727c:	4698      	mov	r8, r3
 800727e:	4606      	mov	r6, r0
 8007280:	460c      	mov	r4, r1
 8007282:	9b0c      	ldr	r3, [sp, #48]	; 0x30
 8007284:	f101 0e43 	add.w	lr, r1, #67	; 0x43
 8007288:	f000 80bc 	beq.w	8007404 <_printf_i+0x194>
 800728c:	d81a      	bhi.n	80072c4 <_printf_i+0x54>
 800728e:	2a63      	cmp	r2, #99	; 0x63
 8007290:	d02e      	beq.n	80072f0 <_printf_i+0x80>
 8007292:	d80a      	bhi.n	80072aa <_printf_i+0x3a>
 8007294:	2a00      	cmp	r2, #0
 8007296:	f000 80c8 	beq.w	800742a <_printf_i+0x1ba>
 800729a:	2a58      	cmp	r2, #88	; 0x58
 800729c:	f000 808a 	beq.w	80073b4 <_printf_i+0x144>
 80072a0:	f104 0542 	add.w	r5, r4, #66	; 0x42
 80072a4:	f884 2042 	strb.w	r2, [r4, #66]	; 0x42
 80072a8:	e02a      	b.n	8007300 <_printf_i+0x90>
 80072aa:	2a64      	cmp	r2, #100	; 0x64
 80072ac:	d001      	beq.n	80072b2 <_printf_i+0x42>
 80072ae:	2a69      	cmp	r2, #105	; 0x69
 80072b0:	d1f6      	bne.n	80072a0 <_printf_i+0x30>
 80072b2:	6821      	ldr	r1, [r4, #0]
 80072b4:	681a      	ldr	r2, [r3, #0]
 80072b6:	f011 0f80 	tst.w	r1, #128	; 0x80
 80072ba:	d023      	beq.n	8007304 <_printf_i+0x94>
 80072bc:	1d11      	adds	r1, r2, #4
 80072be:	6019      	str	r1, [r3, #0]
 80072c0:	6813      	ldr	r3, [r2, #0]
 80072c2:	e027      	b.n	8007314 <_printf_i+0xa4>
 80072c4:	2a73      	cmp	r2, #115	; 0x73
 80072c6:	f000 80b4 	beq.w	8007432 <_printf_i+0x1c2>
 80072ca:	d808      	bhi.n	80072de <_printf_i+0x6e>
 80072cc:	2a6f      	cmp	r2, #111	; 0x6f
 80072ce:	d02a      	beq.n	8007326 <_printf_i+0xb6>
 80072d0:	2a70      	cmp	r2, #112	; 0x70
 80072d2:	d1e5      	bne.n	80072a0 <_printf_i+0x30>
 80072d4:	680a      	ldr	r2, [r1, #0]
 80072d6:	f042 0220 	orr.w	r2, r2, #32
 80072da:	600a      	str	r2, [r1, #0]
 80072dc:	e003      	b.n	80072e6 <_printf_i+0x76>
 80072de:	2a75      	cmp	r2, #117	; 0x75
 80072e0:	d021      	beq.n	8007326 <_printf_i+0xb6>
 80072e2:	2a78      	cmp	r2, #120	; 0x78
 80072e4:	d1dc      	bne.n	80072a0 <_printf_i+0x30>
 80072e6:	2278      	movs	r2, #120	; 0x78
 80072e8:	496f      	ldr	r1, [pc, #444]	; (80074a8 <_printf_i+0x238>)
 80072ea:	f884 2045 	strb.w	r2, [r4, #69]	; 0x45
 80072ee:	e064      	b.n	80073ba <_printf_i+0x14a>
 80072f0:	681a      	ldr	r2, [r3, #0]
 80072f2:	f101 0542 	add.w	r5, r1, #66	; 0x42
 80072f6:	1d11      	adds	r1, r2, #4
 80072f8:	6019      	str	r1, [r3, #0]
 80072fa:	6813      	ldr	r3, [r2, #0]
 80072fc:	f884 3042 	strb.w	r3, [r4, #66]	; 0x42
 8007300:	2301      	movs	r3, #1
 8007302:	e0a3      	b.n	800744c <_printf_i+0x1dc>
 8007304:	f011 0f40 	tst.w	r1, #64	; 0x40
 8007308:	f102 0104 	add.w	r1, r2, #4
 800730c:	6019      	str	r1, [r3, #0]
 800730e:	d0d7      	beq.n	80072c0 <_printf_i+0x50>
 8007310:	f9b2 3000 	ldrsh.w	r3, [r2]
 8007314:	2b00      	cmp	r3, #0
 8007316:	da03      	bge.n	8007320 <_printf_i+0xb0>
 8007318:	222d      	movs	r2, #45	; 0x2d
 800731a:	425b      	negs	r3, r3
 800731c:	f884 2043 	strb.w	r2, [r4, #67]	; 0x43
 8007320:	4962      	ldr	r1, [pc, #392]	; (80074ac <_printf_i+0x23c>)
 8007322:	220a      	movs	r2, #10
 8007324:	e017      	b.n	8007356 <_printf_i+0xe6>
 8007326:	6820      	ldr	r0, [r4, #0]
 8007328:	6819      	ldr	r1, [r3, #0]
 800732a:	f010 0f80 	tst.w	r0, #128	; 0x80
 800732e:	d003      	beq.n	8007338 <_printf_i+0xc8>
 8007330:	1d08      	adds	r0, r1, #4
 8007332:	6018      	str	r0, [r3, #0]
 8007334:	680b      	ldr	r3, [r1, #0]
 8007336:	e006      	b.n	8007346 <_printf_i+0xd6>
 8007338:	f010 0f40 	tst.w	r0, #64	; 0x40
 800733c:	f101 0004 	add.w	r0, r1, #4
 8007340:	6018      	str	r0, [r3, #0]
 8007342:	d0f7      	beq.n	8007334 <_printf_i+0xc4>
 8007344:	880b      	ldrh	r3, [r1, #0]
 8007346:	2a6f      	cmp	r2, #111	; 0x6f
 8007348:	bf14      	ite	ne
 800734a:	220a      	movne	r2, #10
 800734c:	2208      	moveq	r2, #8
 800734e:	4957      	ldr	r1, [pc, #348]	; (80074ac <_printf_i+0x23c>)
 8007350:	2000      	movs	r0, #0
 8007352:	f884 0043 	strb.w	r0, [r4, #67]	; 0x43
 8007356:	6865      	ldr	r5, [r4, #4]
 8007358:	2d00      	cmp	r5, #0
 800735a:	60a5      	str	r5, [r4, #8]
 800735c:	f2c0 809c 	blt.w	8007498 <_printf_i+0x228>
 8007360:	6820      	ldr	r0, [r4, #0]
 8007362:	f020 0004 	bic.w	r0, r0, #4
 8007366:	6020      	str	r0, [r4, #0]
 8007368:	2b00      	cmp	r3, #0
 800736a:	d13f      	bne.n	80073ec <_printf_i+0x17c>
 800736c:	2d00      	cmp	r5, #0
 800736e:	f040 8095 	bne.w	800749c <_printf_i+0x22c>
 8007372:	4675      	mov	r5, lr
 8007374:	2a08      	cmp	r2, #8
 8007376:	d10b      	bne.n	8007390 <_printf_i+0x120>
 8007378:	6823      	ldr	r3, [r4, #0]
 800737a:	07da      	lsls	r2, r3, #31
 800737c:	d508      	bpl.n	8007390 <_printf_i+0x120>
 800737e:	6923      	ldr	r3, [r4, #16]
 8007380:	6862      	ldr	r2, [r4, #4]
 8007382:	429a      	cmp	r2, r3
 8007384:	bfde      	ittt	le
 8007386:	2330      	movle	r3, #48	; 0x30
 8007388:	f805 3c01 	strble.w	r3, [r5, #-1]
 800738c:	f105 35ff 	addle.w	r5, r5, #4294967295
 8007390:	ebae 0305 	sub.w	r3, lr, r5
 8007394:	6123      	str	r3, [r4, #16]
 8007396:	f8cd 8000 	str.w	r8, [sp]
 800739a:	463b      	mov	r3, r7
 800739c:	aa03      	add	r2, sp, #12
 800739e:	4621      	mov	r1, r4
 80073a0:	4630      	mov	r0, r6
 80073a2:	f7ff feed 	bl	8007180 <_printf_common>
 80073a6:	3001      	adds	r0, #1
 80073a8:	d155      	bne.n	8007456 <_printf_i+0x1e6>
 80073aa:	f04f 30ff 	mov.w	r0, #4294967295
 80073ae:	b005      	add	sp, #20
 80073b0:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
 80073b4:	f881 2045 	strb.w	r2, [r1, #69]	; 0x45
 80073b8:	493c      	ldr	r1, [pc, #240]	; (80074ac <_printf_i+0x23c>)
 80073ba:	6822      	ldr	r2, [r4, #0]
 80073bc:	6818      	ldr	r0, [r3, #0]
 80073be:	f012 0f80 	tst.w	r2, #128	; 0x80
 80073c2:	f100 0504 	add.w	r5, r0, #4
 80073c6:	601d      	str	r5, [r3, #0]
 80073c8:	d001      	beq.n	80073ce <_printf_i+0x15e>
 80073ca:	6803      	ldr	r3, [r0, #0]
 80073cc:	e002      	b.n	80073d4 <_printf_i+0x164>
 80073ce:	0655      	lsls	r5, r2, #25
 80073d0:	d5fb      	bpl.n	80073ca <_printf_i+0x15a>
 80073d2:	8803      	ldrh	r3, [r0, #0]
 80073d4:	07d0      	lsls	r0, r2, #31
 80073d6:	bf44      	itt	mi
 80073d8:	f042 0220 	orrmi.w	r2, r2, #32
 80073dc:	6022      	strmi	r2, [r4, #0]
 80073de:	b91b      	cbnz	r3, 80073e8 <_printf_i+0x178>
 80073e0:	6822      	ldr	r2, [r4, #0]
 80073e2:	f022 0220 	bic.w	r2, r2, #32
 80073e6:	6022      	str	r2, [r4, #0]
 80073e8:	2210      	movs	r2, #16
 80073ea:	e7b1      	b.n	8007350 <_printf_i+0xe0>
 80073ec:	4675      	mov	r5, lr
 80073ee:	fbb3 f0f2 	udiv	r0, r3, r2
 80073f2:	fb02 3310 	mls	r3, r2, r0, r3
 80073f6:	5ccb      	ldrb	r3, [r1, r3]
 80073f8:	f805 3d01 	strb.w	r3, [r5, #-1]!
 80073fc:	4603      	mov	r3, r0
 80073fe:	2800      	cmp	r0, #0
 8007400:	d1f5      	bne.n	80073ee <_printf_i+0x17e>
 8007402:	e7b7      	b.n	8007374 <_printf_i+0x104>
 8007404:	6808      	ldr	r0, [r1, #0]
 8007406:	681a      	ldr	r2, [r3, #0]
 8007408:	f010 0f80 	tst.w	r0, #128	; 0x80
 800740c:	6949      	ldr	r1, [r1, #20]
 800740e:	d004      	beq.n	800741a <_printf_i+0x1aa>
 8007410:	1d10      	adds	r0, r2, #4
 8007412:	6018      	str	r0, [r3, #0]
 8007414:	6813      	ldr	r3, [r2, #0]
 8007416:	6019      	str	r1, [r3, #0]
 8007418:	e007      	b.n	800742a <_printf_i+0x1ba>
 800741a:	f010 0f40 	tst.w	r0, #64	; 0x40
 800741e:	f102 0004 	add.w	r0, r2, #4
 8007422:	6018      	str	r0, [r3, #0]
 8007424:	6813      	ldr	r3, [r2, #0]
 8007426:	d0f6      	beq.n	8007416 <_printf_i+0x1a6>
 8007428:	8019      	strh	r1, [r3, #0]
 800742a:	2300      	movs	r3, #0
 800742c:	4675      	mov	r5, lr
 800742e:	6123      	str	r3, [r4, #16]
 8007430:	e7b1      	b.n	8007396 <_printf_i+0x126>
 8007432:	681a      	ldr	r2, [r3, #0]
 8007434:	1d11      	adds	r1, r2, #4
 8007436:	6019      	str	r1, [r3, #0]
 8007438:	6815      	ldr	r5, [r2, #0]
 800743a:	2100      	movs	r1, #0
 800743c:	6862      	ldr	r2, [r4, #4]
 800743e:	4628      	mov	r0, r5
 8007440:	f000 f916 	bl	8007670 <memchr>
 8007444:	b108      	cbz	r0, 800744a <_printf_i+0x1da>
 8007446:	1b40      	subs	r0, r0, r5
 8007448:	6060      	str	r0, [r4, #4]
 800744a:	6863      	ldr	r3, [r4, #4]
 800744c:	6123      	str	r3, [r4, #16]
 800744e:	2300      	movs	r3, #0
 8007450:	f884 3043 	strb.w	r3, [r4, #67]	; 0x43
 8007454:	e79f      	b.n	8007396 <_printf_i+0x126>
 8007456:	6923      	ldr	r3, [r4, #16]
 8007458:	462a      	mov	r2, r5
 800745a:	4639      	mov	r1, r7
 800745c:	4630      	mov	r0, r6
 800745e:	47c0      	blx	r8
 8007460:	3001      	adds	r0, #1
 8007462:	d0a2      	beq.n	80073aa <_printf_i+0x13a>
 8007464:	6823      	ldr	r3, [r4, #0]
 8007466:	079b      	lsls	r3, r3, #30
 8007468:	d507      	bpl.n	800747a <_printf_i+0x20a>
 800746a:	2500      	movs	r5, #0
 800746c:	f104 0919 	add.w	r9, r4, #25
 8007470:	68e3      	ldr	r3, [r4, #12]
 8007472:	9a03      	ldr	r2, [sp, #12]
 8007474:	1a9b      	subs	r3, r3, r2
 8007476:	429d      	cmp	r5, r3
 8007478:	db05      	blt.n	8007486 <_printf_i+0x216>
 800747a:	68e0      	ldr	r0, [r4, #12]
 800747c:	9b03      	ldr	r3, [sp, #12]
 800747e:	4298      	cmp	r0, r3
 8007480:	bfb8      	it	lt
 8007482:	4618      	movlt	r0, r3
 8007484:	e793      	b.n	80073ae <_printf_i+0x13e>
 8007486:	2301      	movs	r3, #1
 8007488:	464a      	mov	r2, r9
 800748a:	4639      	mov	r1, r7
 800748c:	4630      	mov	r0, r6
 800748e:	47c0      	blx	r8
 8007490:	3001      	adds	r0, #1
 8007492:	d08a      	beq.n	80073aa <_printf_i+0x13a>
 8007494:	3501      	adds	r5, #1
 8007496:	e7eb      	b.n	8007470 <_printf_i+0x200>
 8007498:	2b00      	cmp	r3, #0
 800749a:	d1a7      	bne.n	80073ec <_printf_i+0x17c>
 800749c:	780b      	ldrb	r3, [r1, #0]
 800749e:	f104 0542 	add.w	r5, r4, #66	; 0x42
 80074a2:	f884 3042 	strb.w	r3, [r4, #66]	; 0x42
 80074a6:	e765      	b.n	8007374 <_printf_i+0x104>
 80074a8:	0800781a 	.word	0x0800781a
 80074ac:	08007809 	.word	0x08007809

080074b0 <_putc_r>:
 80074b0:	b570      	push	{r4, r5, r6, lr}
 80074b2:	460d      	mov	r5, r1
 80074b4:	4614      	mov	r4, r2
 80074b6:	4606      	mov	r6, r0
 80074b8:	b118      	cbz	r0, 80074c2 <_putc_r+0x12>
 80074ba:	6983      	ldr	r3, [r0, #24]
 80074bc:	b90b      	cbnz	r3, 80074c2 <_putc_r+0x12>
 80074be:	f7ff fb81 	bl	8006bc4 <__sinit>
 80074c2:	4b13      	ldr	r3, [pc, #76]	; (8007510 <_putc_r+0x60>)
 80074c4:	429c      	cmp	r4, r3
 80074c6:	d112      	bne.n	80074ee <_putc_r+0x3e>
 80074c8:	6874      	ldr	r4, [r6, #4]
 80074ca:	68a3      	ldr	r3, [r4, #8]
 80074cc:	3b01      	subs	r3, #1
 80074ce:	2b00      	cmp	r3, #0
 80074d0:	60a3      	str	r3, [r4, #8]
 80074d2:	da16      	bge.n	8007502 <_putc_r+0x52>
 80074d4:	69a2      	ldr	r2, [r4, #24]
 80074d6:	4293      	cmp	r3, r2
 80074d8:	db02      	blt.n	80074e0 <_putc_r+0x30>
 80074da:	b2eb      	uxtb	r3, r5
 80074dc:	2b0a      	cmp	r3, #10
 80074de:	d110      	bne.n	8007502 <_putc_r+0x52>
 80074e0:	4622      	mov	r2, r4
 80074e2:	4629      	mov	r1, r5
 80074e4:	4630      	mov	r0, r6
 80074e6:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
 80074ea:	f7ff b9b9 	b.w	8006860 <__swbuf_r>
 80074ee:	4b09      	ldr	r3, [pc, #36]	; (8007514 <_putc_r+0x64>)
 80074f0:	429c      	cmp	r4, r3
 80074f2:	d101      	bne.n	80074f8 <_putc_r+0x48>
 80074f4:	68b4      	ldr	r4, [r6, #8]
 80074f6:	e7e8      	b.n	80074ca <_putc_r+0x1a>
 80074f8:	4b07      	ldr	r3, [pc, #28]	; (8007518 <_putc_r+0x68>)
 80074fa:	429c      	cmp	r4, r3
 80074fc:	bf08      	it	eq
 80074fe:	68f4      	ldreq	r4, [r6, #12]
 8007500:	e7e3      	b.n	80074ca <_putc_r+0x1a>
 8007502:	6823      	ldr	r3, [r4, #0]
 8007504:	b2e8      	uxtb	r0, r5
 8007506:	1c5a      	adds	r2, r3, #1
 8007508:	6022      	str	r2, [r4, #0]
 800750a:	701d      	strb	r5, [r3, #0]
 800750c:	bd70      	pop	{r4, r5, r6, pc}
 800750e:	bf00      	nop
 8007510:	080077b8 	.word	0x080077b8
 8007514:	080077d8 	.word	0x080077d8
 8007518:	08007798 	.word	0x08007798

0800751c <_sbrk_r>:
 800751c:	b538      	push	{r3, r4, r5, lr}
 800751e:	2300      	movs	r3, #0
 8007520:	4c05      	ldr	r4, [pc, #20]	; (8007538 <_sbrk_r+0x1c>)
 8007522:	4605      	mov	r5, r0
 8007524:	4608      	mov	r0, r1
 8007526:	6023      	str	r3, [r4, #0]
 8007528:	f7fe ff42 	bl	80063b0 <_sbrk>
 800752c:	1c43      	adds	r3, r0, #1
 800752e:	d102      	bne.n	8007536 <_sbrk_r+0x1a>
 8007530:	6823      	ldr	r3, [r4, #0]
 8007532:	b103      	cbz	r3, 8007536 <_sbrk_r+0x1a>
 8007534:	602b      	str	r3, [r5, #0]
 8007536:	bd38      	pop	{r3, r4, r5, pc}
 8007538:	20000d64 	.word	0x20000d64

0800753c <__sread>:
 800753c:	b510      	push	{r4, lr}
 800753e:	460c      	mov	r4, r1
 8007540:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 8007544:	f000 f8a4 	bl	8007690 <_read_r>
 8007548:	2800      	cmp	r0, #0
 800754a:	bfab      	itete	ge
 800754c:	6d63      	ldrge	r3, [r4, #84]	; 0x54
 800754e:	89a3      	ldrhlt	r3, [r4, #12]
 8007550:	181b      	addge	r3, r3, r0
 8007552:	f423 5380 	biclt.w	r3, r3, #4096	; 0x1000
 8007556:	bfac      	ite	ge
 8007558:	6563      	strge	r3, [r4, #84]	; 0x54
 800755a:	81a3      	strhlt	r3, [r4, #12]
 800755c:	bd10      	pop	{r4, pc}

0800755e <__swrite>:
 800755e:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
 8007562:	461f      	mov	r7, r3
 8007564:	898b      	ldrh	r3, [r1, #12]
 8007566:	4605      	mov	r5, r0
 8007568:	05db      	lsls	r3, r3, #23
 800756a:	460c      	mov	r4, r1
 800756c:	4616      	mov	r6, r2
 800756e:	d505      	bpl.n	800757c <__swrite+0x1e>
 8007570:	2302      	movs	r3, #2
 8007572:	2200      	movs	r2, #0
 8007574:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 8007578:	f000 f868 	bl	800764c <_lseek_r>
 800757c:	89a3      	ldrh	r3, [r4, #12]
 800757e:	4632      	mov	r2, r6
 8007580:	f423 5380 	bic.w	r3, r3, #4096	; 0x1000
 8007584:	81a3      	strh	r3, [r4, #12]
 8007586:	f9b4 100e 	ldrsh.w	r1, [r4, #14]
 800758a:	463b      	mov	r3, r7
 800758c:	4628      	mov	r0, r5
 800758e:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
 8007592:	f000 b817 	b.w	80075c4 <_write_r>

08007596 <__sseek>:
 8007596:	b510      	push	{r4, lr}
 8007598:	460c      	mov	r4, r1
 800759a:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 800759e:	f000 f855 	bl	800764c <_lseek_r>
 80075a2:	1c43      	adds	r3, r0, #1
 80075a4:	89a3      	ldrh	r3, [r4, #12]
 80075a6:	bf15      	itete	ne
 80075a8:	6560      	strne	r0, [r4, #84]	; 0x54
 80075aa:	f423 5380 	biceq.w	r3, r3, #4096	; 0x1000
 80075ae:	f443 5380 	orrne.w	r3, r3, #4096	; 0x1000
 80075b2:	81a3      	strheq	r3, [r4, #12]
 80075b4:	bf18      	it	ne
 80075b6:	81a3      	strhne	r3, [r4, #12]
 80075b8:	bd10      	pop	{r4, pc}

080075ba <__sclose>:
 80075ba:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 80075be:	f000 b813 	b.w	80075e8 <_close_r>
	...

080075c4 <_write_r>:
 80075c4:	b538      	push	{r3, r4, r5, lr}
 80075c6:	4605      	mov	r5, r0
 80075c8:	4608      	mov	r0, r1
 80075ca:	4611      	mov	r1, r2
 80075cc:	2200      	movs	r2, #0
 80075ce:	4c05      	ldr	r4, [pc, #20]	; (80075e4 <_write_r+0x20>)
 80075d0:	6022      	str	r2, [r4, #0]
 80075d2:	461a      	mov	r2, r3
 80075d4:	f7fe fae8 	bl	8005ba8 <_write>
 80075d8:	1c43      	adds	r3, r0, #1
 80075da:	d102      	bne.n	80075e2 <_write_r+0x1e>
 80075dc:	6823      	ldr	r3, [r4, #0]
 80075de:	b103      	cbz	r3, 80075e2 <_write_r+0x1e>
 80075e0:	602b      	str	r3, [r5, #0]
 80075e2:	bd38      	pop	{r3, r4, r5, pc}
 80075e4:	20000d64 	.word	0x20000d64

080075e8 <_close_r>:
 80075e8:	b538      	push	{r3, r4, r5, lr}
 80075ea:	2300      	movs	r3, #0
 80075ec:	4c05      	ldr	r4, [pc, #20]	; (8007604 <_close_r+0x1c>)
 80075ee:	4605      	mov	r5, r0
 80075f0:	4608      	mov	r0, r1
 80075f2:	6023      	str	r3, [r4, #0]
 80075f4:	f7fe fef6 	bl	80063e4 <_close>
 80075f8:	1c43      	adds	r3, r0, #1
 80075fa:	d102      	bne.n	8007602 <_close_r+0x1a>
 80075fc:	6823      	ldr	r3, [r4, #0]
 80075fe:	b103      	cbz	r3, 8007602 <_close_r+0x1a>
 8007600:	602b      	str	r3, [r5, #0]
 8007602:	bd38      	pop	{r3, r4, r5, pc}
 8007604:	20000d64 	.word	0x20000d64

08007608 <_fstat_r>:
 8007608:	b538      	push	{r3, r4, r5, lr}
 800760a:	2300      	movs	r3, #0
 800760c:	4c06      	ldr	r4, [pc, #24]	; (8007628 <_fstat_r+0x20>)
 800760e:	4605      	mov	r5, r0
 8007610:	4608      	mov	r0, r1
 8007612:	4611      	mov	r1, r2
 8007614:	6023      	str	r3, [r4, #0]
 8007616:	f7fe fee8 	bl	80063ea <_fstat>
 800761a:	1c43      	adds	r3, r0, #1
 800761c:	d102      	bne.n	8007624 <_fstat_r+0x1c>
 800761e:	6823      	ldr	r3, [r4, #0]
 8007620:	b103      	cbz	r3, 8007624 <_fstat_r+0x1c>
 8007622:	602b      	str	r3, [r5, #0]
 8007624:	bd38      	pop	{r3, r4, r5, pc}
 8007626:	bf00      	nop
 8007628:	20000d64 	.word	0x20000d64

0800762c <_isatty_r>:
 800762c:	b538      	push	{r3, r4, r5, lr}
 800762e:	2300      	movs	r3, #0
 8007630:	4c05      	ldr	r4, [pc, #20]	; (8007648 <_isatty_r+0x1c>)
 8007632:	4605      	mov	r5, r0
 8007634:	4608      	mov	r0, r1
 8007636:	6023      	str	r3, [r4, #0]
 8007638:	f7fe fedc 	bl	80063f4 <_isatty>
 800763c:	1c43      	adds	r3, r0, #1
 800763e:	d102      	bne.n	8007646 <_isatty_r+0x1a>
 8007640:	6823      	ldr	r3, [r4, #0]
 8007642:	b103      	cbz	r3, 8007646 <_isatty_r+0x1a>
 8007644:	602b      	str	r3, [r5, #0]
 8007646:	bd38      	pop	{r3, r4, r5, pc}
 8007648:	20000d64 	.word	0x20000d64

0800764c <_lseek_r>:
 800764c:	b538      	push	{r3, r4, r5, lr}
 800764e:	4605      	mov	r5, r0
 8007650:	4608      	mov	r0, r1
 8007652:	4611      	mov	r1, r2
 8007654:	2200      	movs	r2, #0
 8007656:	4c05      	ldr	r4, [pc, #20]	; (800766c <_lseek_r+0x20>)
 8007658:	6022      	str	r2, [r4, #0]
 800765a:	461a      	mov	r2, r3
 800765c:	f7fe fecc 	bl	80063f8 <_lseek>
 8007660:	1c43      	adds	r3, r0, #1
 8007662:	d102      	bne.n	800766a <_lseek_r+0x1e>
 8007664:	6823      	ldr	r3, [r4, #0]
 8007666:	b103      	cbz	r3, 800766a <_lseek_r+0x1e>
 8007668:	602b      	str	r3, [r5, #0]
 800766a:	bd38      	pop	{r3, r4, r5, pc}
 800766c:	20000d64 	.word	0x20000d64

08007670 <memchr>:
 8007670:	b510      	push	{r4, lr}
 8007672:	b2c9      	uxtb	r1, r1
 8007674:	4402      	add	r2, r0
 8007676:	4290      	cmp	r0, r2
 8007678:	4603      	mov	r3, r0
 800767a:	d101      	bne.n	8007680 <memchr+0x10>
 800767c:	2000      	movs	r0, #0
 800767e:	bd10      	pop	{r4, pc}
 8007680:	781c      	ldrb	r4, [r3, #0]
 8007682:	3001      	adds	r0, #1
 8007684:	428c      	cmp	r4, r1
 8007686:	d1f6      	bne.n	8007676 <memchr+0x6>
 8007688:	4618      	mov	r0, r3
 800768a:	bd10      	pop	{r4, pc}

0800768c <__malloc_lock>:
 800768c:	4770      	bx	lr

0800768e <__malloc_unlock>:
 800768e:	4770      	bx	lr

08007690 <_read_r>:
 8007690:	b538      	push	{r3, r4, r5, lr}
 8007692:	4605      	mov	r5, r0
 8007694:	4608      	mov	r0, r1
 8007696:	4611      	mov	r1, r2
 8007698:	2200      	movs	r2, #0
 800769a:	4c05      	ldr	r4, [pc, #20]	; (80076b0 <_read_r+0x20>)
 800769c:	6022      	str	r2, [r4, #0]
 800769e:	461a      	mov	r2, r3
 80076a0:	f7fe fe78 	bl	8006394 <_read>
 80076a4:	1c43      	adds	r3, r0, #1
 80076a6:	d102      	bne.n	80076ae <_read_r+0x1e>
 80076a8:	6823      	ldr	r3, [r4, #0]
 80076aa:	b103      	cbz	r3, 80076ae <_read_r+0x1e>
 80076ac:	602b      	str	r3, [r5, #0]
 80076ae:	bd38      	pop	{r3, r4, r5, pc}
 80076b0:	20000d64 	.word	0x20000d64

080076b4 <_init>:
 80076b4:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 80076b6:	bf00      	nop
 80076b8:	bcf8      	pop	{r3, r4, r5, r6, r7}
 80076ba:	bc08      	pop	{r3}
 80076bc:	469e      	mov	lr, r3
 80076be:	4770      	bx	lr

080076c0 <_fini>:
 80076c0:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 80076c2:	bf00      	nop
 80076c4:	bcf8      	pop	{r3, r4, r5, r6, r7}
 80076c6:	bc08      	pop	{r3}
 80076c8:	469e      	mov	lr, r3
 80076ca:	4770      	bx	lr