STM32F103_ATTEN_PLL_Zig/Inc/zig_operate.h

/*
 * zig_operate.h
 *
 *  Created on: 2019. 7. 26.
 *      Author: parkyj
 */

#ifndef ZIG_OPERATE_H_
#define ZIG_OPERATE_H_
#include <stdbool.h>
#include "main.h"
bool RF_Ctrl_Main(uint8_t* data_buf);

void RF_Status_Get(void);
typedef enum{
    Header = 0,
    Type,
    Length,
    Crcindex,
}Bluecell_Prot_p;

typedef enum {
    TYPE_BLUECELL_RESET = 0,
    TYPE_BLUECELL_SET   = 1,
    TYPE_BLUECELL_GET   = 2,
    TYPE_BLUECELL_SAVE   = 3,   
    TYPE_BLUECELL_ACK    = 4,
    TYPE_BLUECELL_ERROR    = 5,    
}Bluecell_Prot_t;

typedef enum{
    INDEX_BLUE_HEADER = 0,
    INDEX_BLUE_TYPE,
    INDEX_BLUE_LENGTH,
    INDEX_BLUE_CRCINDEX,
    INDEX_ATT_1_8G_DL1 ,
    INDEX_ATT_1_8G_DL2 ,
    INDEX_ATT_1_8G_UL1 ,
    INDEX_ATT_1_8G_UL2 ,
    INDEX_ATT_1_8G_UL3 ,
    INDEX_ATT_1_8G_UL4 , 
    INDEX_ATT_2_1G_DL1  = 10,
    INDEX_ATT_2_1G_DL2 ,
    INDEX_ATT_2_1G_UL1 ,
    INDEX_ATT_2_1G_UL2 ,
    INDEX_ATT_2_1G_UL3 , 
    INDEX_ATT_2_1G_UL4 ,
    INDEX_ATT_3_5G_LOW1  ,
    INDEX_ATT_3_5G_HIGH1  ,
    INDEX_ATT_3_5G_COM1,
    INDEX_ATT_3_5G_LOW2  ,
    INDEX_ATT_3_5G_HIGH2= 20  ,    
    INDEX_ATT_3_5G_COM2,
    INDEX_PLL_1_8G_DL_H,
    INDEX_PLL_1_8G_DL_L,
    INDEX_PLL_1_8G_UL_H,
    INDEX_PLL_1_8G_UL_L,
    INDEX_PLL_2_1G_DL_H,
    INDEX_PLL_2_1G_DL_L,
    INDEX_PLL_2_1G_UL_H,
    INDEX_PLL_2_1G_UL_L,
    INDEX_PLL_3_5G_LOW_H ,//30
    INDEX_PLL_3_5G_LOW_M ,    
    INDEX_PLL_3_5G_LOW_L , 
    INDEX_PLL_3_5G_HIGH_H ,
    INDEX_PLL_3_5G_HIGH_M ,    
    INDEX_PLL_3_5G_HIGH_L ,
    INDEX_PLL_LD_6_BIT  ,
    INDEX_DET_1_8G_DL_IN_H  ,
    INDEX_DET_1_8G_DL_IN_L  ,
    INDEX_DET_1_8G_DL_OUT_H ,
    INDEX_DET_1_8G_DL_OUT_L ,
    INDEX_DET_1_8G_UL_IN_H  ,//40
    INDEX_DET_1_8G_UL_IN_L  ,
    INDEX_DET_1_8G_UL_OUT_H ,
    INDEX_DET_1_8G_UL_OUT_L ,
    INDEX_DET_2_1G_DL_IN_H  ,
    INDEX_DET_2_1G_DL_IN_L  ,
    INDEX_DET_2_1G_DL_OUT_H ,
    INDEX_DET_2_1G_DL_OUT_L ,
    INDEX_DET_2_1G_UL_IN_H  ,
    INDEX_DET_2_1G_UL_IN_L  ,
    INDEX_DET_2_1G_UL_OUT_H ,//50
    INDEX_DET_2_1G_UL_OUT_L ,
    INDEX_DET_3_5G_DL_IN_H  ,
    INDEX_DET_3_5G_DL_IN_L  ,
    INDEX_DET_3_5G_DL_OUT_H ,
    INDEX_DET_3_5G_DL_OUT_L ,
    INDEX_DET_3_5G_UL_IN_H  ,
    INDEX_DET_3_5G_UL_IN_L  ,
    INDEX_DET_3_5G_UL_OUT_H ,
    INDEX_DET_3_5G_UL_OUT_L ,
    INDEX_RFU_TEMP_H    ,//60
    INDEX_RFU_TEMP_L    ,
    INDEX__28V_DET_H    ,
    INDEX__28V_DET_L    ,
    INDEX_ALARM_AC      ,
    INDEX_ALARM_DC      ,
    INDEX_PATH_EN_1_8G_DL   ,
    INDEX_PATH_EN_1_8G_UL   ,
    INDEX_PATH_EN_2_1G_DL   ,
    INDEX_PATH_EN_2_1G_UL   ,
    INDEX_PATH_EN_3_5G_DL,//70
    INDEX_PATH_EN_3_5G_UL   ,
    INDEX_PATH_EN_3_5G_H ,
    INDEX_PATH_EN_3_5G_L,
    INDEX_PLL_ON_OFF_3_5G_H ,
    INDEX_PLL_ON_OFF_3_5G_L ,
    INDEX_T_SYNC_DL,
    INDEX__T_SYNC_DL,
    INDEX_T_SYNC_UL,
    INDEX__T_SYNC_UL,    
    INDEX_DAC_VCtrl_A_H,
    INDEX_DAC_VCtrl_A_L,//80
    INDEX_DAC_VCtrl_B_H, 
    INDEX_DAC_VCtrl_B_L,
    INDEX_DAC_VCtrl_C_H,
    INDEX_DAC_VCtrl_C_L,
    INDEX_DAC_VCtrl_D_H,
    INDEX_DAC_VCtrl_D_L,
    INDEX_DAC_VCtrl_E_H,
    INDEX_DAC_VCtrl_E_L,
    INDEX_DAC_VCtrl_F_H,//90
    INDEX_DAC_VCtrl_F_L,
    INDEX_DAC_VCtrl_G_H ,
    INDEX_DAC_VCtrl_G_L,
    INDEX_DAC_VCtrl_H_H,
    INDEX_DAC_VCtrl_H_L,   
    INDEX_BLUE_CRC,//96 
    INDEX_BLUE_EOF,//97
}Bluecell_Prot_Index;
uint8_t Prev_data[INDEX_BLUE_EOF + 1];
uint8_t Flash_Save_data[INDEX_BLUE_EOF + 1];


//extern PLL_Setting_st Pll_3_5_H;
//extern PLL_Setting_st Pll_3_5_L;


#endif /* ZIG_OPERATE_H_ */