zig_operate.c 6.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269
  1. /*
  2. * zig_operate.c
  3. *
  4. * Created on: 2019. 7. 26.
  5. * Author: parkyj
  6. */
  7. #include "zig_operate.h"
  8. /* * * * * * * #define Struct* * * * * * * */
  9. PLL_Setting_st Pll_1_8GHz_DL = {
  10. PLL_CLK_GPIO_Port,
  11. PLL_CLK_Pin,
  12. PLL_DATA_GPIO_Port,
  13. PLL_DATA_Pin,
  14. PLL_EN_1_8G_DL_GPIO_Port,
  15. PLL_EN_1_8G_DL_Pin,
  16. };
  17. PLL_Setting_st Pll_1_8GHz_UL = {
  18. PLL_CLK_GPIO_Port,
  19. PLL_CLK_Pin,
  20. PLL_DATA_GPIO_Port,
  21. PLL_DATA_Pin,
  22. PLL_EN_1_8G_UL_GPIO_Port,
  23. PLL_EN_1_8G_UL_Pin,
  24. };
  25. PLL_Setting_st Pll_2_1GHz_DL = {
  26. PLL_CLK_GPIO_Port,
  27. PLL_CLK_Pin,
  28. PLL_DATA_GPIO_Port,
  29. PLL_DATA_Pin,
  30. PLL_EN_2_1G_DL_GPIO_Port,
  31. PLL_EN_2_1G_DL_Pin,
  32. };
  33. PLL_Setting_st Pll_2_1GHz_UL = {
  34. PLL_CLK_GPIO_Port,
  35. PLL_CLK_Pin,
  36. PLL_DATA_GPIO_Port,
  37. PLL_DATA_Pin,
  38. PLL_EN_2_1G_UL_GPIO_Port,
  39. PLL_EN_2_1G_UL_Pin,
  40. };
  41. /* * * * * * * * NOT YET * * * * * * * */
  42. PLL_Setting_st Pll_3_5GHz_DL = {
  43. ATT_CLK_3_5G_GPIO_Port,
  44. ATT_EN_3_5G_Pin,
  45. PLL_DATA_GPIO_Port,
  46. PLL_DATA_Pin,
  47. PLL_EN_2_1G_DL_GPIO_Port,
  48. PLL_EN_2_1G_DL_Pin,
  49. };
  50. PLL_Setting_st Pll_3_5GHz_UL = {
  51. PLL_CLK_GPIO_Port,
  52. PLL_CLK_Pin,
  53. PLL_DATA_GPIO_Port,
  54. PLL_DATA_Pin,
  55. PLL_EN_2_1G_UL_GPIO_Port,
  56. PLL_EN_2_1G_UL_Pin,
  57. };
  58. /* * * * * * * * ATTEN * * * * * * * */
  59. ATTEN_Setting_st Atten_1_8Ghz_DL1 ={
  60. ATT_CLK_GPIO_Port,
  61. ATT_CLK_Pin,
  62. ATT_DATA_GPIO_Port,
  63. ATT_DATA_Pin,
  64. ATT_EN_1_8G_DL1_GPIO_Port,
  65. ATT_EN_1_8G_DL1_Pin,
  66. PATH_EN_1_8G_DL_GPIO_Port,
  67. PATH_EN_1_8G_DL_Pin,
  68. };
  69. ATTEN_Setting_st Atten_1_8Ghz_DL2 ={
  70. ATT_CLK_GPIO_Port,
  71. ATT_CLK_Pin,
  72. ATT_DATA_GPIO_Port,
  73. ATT_DATA_Pin,
  74. ATT_EN_1_8G_DL2_GPIO_Port,
  75. ATT_EN_1_8G_DL2_Pin,
  76. PATH_EN_1_8G_DL_GPIO_Port,
  77. PATH_EN_1_8G_DL_Pin,
  78. };
  79. ATTEN_Setting_st Atten_1_8Ghz_UL1 ={
  80. ATT_CLK_GPIO_Port,
  81. ATT_CLK_Pin,
  82. ATT_DATA_GPIO_Port,
  83. ATT_DATA_Pin,
  84. ATT_EN_1_8G_UL1_GPIO_Port,
  85. ATT_EN_1_8G_UL1_Pin,
  86. PATH_EN_1_8G_UL_GPIO_Port,
  87. PATH_EN_1_8G_UL_Pin,
  88. };
  89. ATTEN_Setting_st Atten_1_8Ghz_UL2 ={
  90. ATT_CLK_GPIO_Port,
  91. ATT_CLK_Pin,
  92. ATT_DATA_GPIO_Port,
  93. ATT_DATA_Pin,
  94. ATT_EN_1_8G_UL2_GPIO_Port,
  95. ATT_EN_1_8G_UL2_Pin,
  96. PATH_EN_1_8G_UL_GPIO_Port,
  97. PATH_EN_1_8G_UL_Pin,
  98. };
  99. ATTEN_Setting_st Atten_1_8Ghz_UL3 ={
  100. ATT_CLK_GPIO_Port,
  101. ATT_CLK_Pin,
  102. ATT_DATA_GPIO_Port,
  103. ATT_DATA_Pin,
  104. ATT_EN_1_8G_UL3_GPIO_Port,
  105. ATT_EN_1_8G_UL3_Pin,
  106. PATH_EN_1_8G_UL_GPIO_Port,
  107. PATH_EN_1_8G_UL_Pin,
  108. };
  109. ATTEN_Setting_st Atten_1_8Ghz_UL4 ={
  110. ATT_CLK_GPIO_Port,
  111. ATT_CLK_Pin,
  112. ATT_DATA_GPIO_Port,
  113. ATT_DATA_Pin,
  114. ATT_EN_1_8G_UL4_GPIO_Port,
  115. ATT_EN_1_8G_UL4_Pin,
  116. PATH_EN_1_8G_UL_GPIO_Port,
  117. PATH_EN_1_8G_UL_Pin,
  118. };
  119. ATTEN_Setting_st Atten_2_1Ghz_DL1 ={
  120. ATT_CLK_GPIO_Port,
  121. ATT_CLK_Pin,
  122. ATT_DATA_GPIO_Port,
  123. ATT_DATA_Pin,
  124. ATT_EN_2_1G_DL1_GPIO_Port,
  125. ATT_EN_2_1G_DL1_Pin,
  126. PATH_EN_2_1G_DL_GPIO_Port,
  127. PATH_EN_2_1G_DL_Pin,
  128. };
  129. ATTEN_Setting_st Atten_2_1Ghz_DL2 ={
  130. ATT_CLK_GPIO_Port,
  131. ATT_CLK_Pin,
  132. ATT_DATA_GPIO_Port,
  133. ATT_DATA_Pin,
  134. ATT_EN_2_1G_DL2_GPIO_Port,
  135. ATT_EN_2_1G_DL2_Pin,
  136. PATH_EN_2_1G_DL_GPIO_Port,
  137. PATH_EN_2_1G_DL_Pin,
  138. };
  139. ATTEN_Setting_st Atten_2_1Ghz_UL1 ={
  140. ATT_CLK_GPIO_Port,
  141. ATT_CLK_Pin,
  142. ATT_DATA_GPIO_Port,
  143. ATT_DATA_Pin,
  144. ATT_EN_2_1G_UL1_GPIO_Port,
  145. ATT_EN_2_1G_UL1_Pin,
  146. PATH_EN_2_1G_UL_GPIO_Port,
  147. PATH_EN_2_1G_UL_Pin,
  148. };
  149. ATTEN_Setting_st Atten_2_1Ghz_UL2 ={
  150. ATT_CLK_GPIO_Port,
  151. ATT_CLK_Pin,
  152. ATT_DATA_GPIO_Port,
  153. ATT_DATA_Pin,
  154. ATT_EN_2_1G_UL2_GPIO_Port,
  155. ATT_EN_2_1G_UL2_Pin,
  156. PATH_EN_2_1G_UL_GPIO_Port,
  157. PATH_EN_2_1G_UL_Pin,
  158. };
  159. ATTEN_Setting_st Atten_2_1Ghz_UL3 ={
  160. ATT_CLK_GPIO_Port,
  161. ATT_CLK_Pin,
  162. ATT_DATA_GPIO_Port,
  163. ATT_DATA_Pin,
  164. ATT_EN_2_1G_UL3_GPIO_Port,
  165. ATT_EN_2_1G_UL3_Pin,
  166. PATH_EN_2_1G_UL_GPIO_Port,
  167. PATH_EN_2_1G_UL_Pin,
  168. };
  169. ATTEN_Setting_st Atten_2_1Ghz_UL4 ={
  170. ATT_CLK_GPIO_Port,
  171. ATT_CLK_Pin,
  172. ATT_DATA_GPIO_Port,
  173. ATT_DATA_Pin,
  174. ATT_EN_2_1G_UL4_GPIO_Port,
  175. ATT_EN_2_1G_UL4_Pin,
  176. PATH_EN_2_1G_UL_GPIO_Port,
  177. PATH_EN_2_1G_UL_Pin,
  178. };
  179. typedef enum{
  180. TYPE_BLUECELL_RESET = 0,
  181. TYPE_ATT_1_8GHz_DL1 = 1,
  182. TYPE_ATT_1_8GHz_DL2,
  183. TYPE_ATT_1_8GHz_UL1,
  184. TYPE_ATT_1_8GHz_UL2,
  185. TYPE_ATT_1_8GHz_UL3, //5
  186. TYPE_ATT_1_8GHz_UL4,
  187. TYPE_ATT_2_1GHz_DL1,
  188. TYPE_ATT_2_1GHz_DL2,
  189. TYPE_ATT_2_1GHz_UL1,
  190. TYPE_ATT_2_1GHz_UL2, // 10
  191. TYPE_ATT_2_1GHz_UL3,
  192. TYPE_ATT_2_1GHz_UL4,
  193. TYPE_ATT_3_5GHz_DL,
  194. TYPE_ATT_3_5GHz_UL,
  195. TYPE_ATT_3_5GHz_COM1, // 15
  196. TYPE_ATT_3_5GHz_COM2,
  197. TYPE_ATT_3_5GHz_COM3,
  198. }Bluecell_Prot_t;
  199. typedef enum{
  200. Header = 0,
  201. Length,
  202. Type,
  203. Crcindex,
  204. }Bluecell_Prot_p;
  205. bool RF_Data_Check(uint8_t* data_buf){
  206. bool ret = false;
  207. bool crcret = STH30_CheckCrc(&data_buf[Type], data_buf[Length], data_buf[Crcindex]);
  208. if(data_buf[Header] == BLUECELL_HEADER){ /*HEADER CHECK*/
  209. ret= true;
  210. }
  211. if(crcret == true){/*CRC CHECK*/
  212. ret = true;
  213. }
  214. return ret;
  215. }
  216. bool RF_Ctrl_Main(uint8_t* data_buf){
  217. bool ret = false;
  218. Bluecell_Prot_t type = data_buf[Type];
  219. RF_Data_Check(&data_buf[Header]); /* ERROR CHECK */
  220. switch(type){
  221. case TYPE_BLUECELL_RESET:
  222. // printf("Reset Start \r\n");
  223. NVIC_SystemReset();
  224. break;
  225. case TYPE_ATT_1_8GHz_DL1:
  226. printf(" ");
  227. break;
  228. case TYPE_ATT_1_8GHz_DL2: break;
  229. case TYPE_ATT_1_8GHz_UL1: break;
  230. case TYPE_ATT_1_8GHz_UL2: break;
  231. case TYPE_ATT_1_8GHz_UL3: break;//5
  232. case TYPE_ATT_1_8GHz_UL4:break;
  233. case TYPE_ATT_2_1GHz_DL1:break;
  234. case TYPE_ATT_2_1GHz_DL2:break;
  235. case TYPE_ATT_2_1GHz_UL1:break;
  236. case TYPE_ATT_2_1GHz_UL2: break;// 10
  237. case TYPE_ATT_2_1GHz_UL3:break;
  238. case TYPE_ATT_2_1GHz_UL4: break;
  239. case TYPE_ATT_3_5GHz_DL:break;
  240. case TYPE_ATT_3_5GHz_UL:break;
  241. case TYPE_ATT_3_5GHz_COM1: break;// 15
  242. case TYPE_ATT_3_5GHz_COM2:break;
  243. case TYPE_ATT_3_5GHz_COM3: break;
  244. default:
  245. printf("Function : %s LINE : %d type : %d \r\n",__func__,__LINE__,type);
  246. break;
  247. }
  248. return ret;
  249. }