june9152
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STM32F103_ATTEN_PLL_Zig


			
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STM32F103_ATTEN_PLL_Zig.elf:     file format elf32-littlearm

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .isr_vector   000001e4  08004000  08004000  00004000  2**0
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  1 .text         000032fc  080041e4  080041e4  000041e4  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  2 .rodata       00000104  080074e0  080074e0  000074e0  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  3 .init_array   00000004  080075e4  080075e4  000075e4  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  4 .fini_array   00000004  080075e8  080075e8  000075e8  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  5 .data         00000070  20000000  080075ec  00010000  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  6 .bss          00001dc8  20000070  0800765c  00010070  2**2
                  ALLOC
  7 ._user_heap_stack 00000600  20001e38  0800765c  00011e38  2**0
                  ALLOC
  8 .ARM.attributes 00000029  00000000  00000000  00010070  2**0
                  CONTENTS, READONLY
  9 .debug_info   00018d07  00000000  00000000  00010099  2**0
                  CONTENTS, READONLY, DEBUGGING
 10 .debug_abbrev 000033fb  00000000  00000000  00028da0  2**0
                  CONTENTS, READONLY, DEBUGGING
 11 .debug_loc    00007578  00000000  00000000  0002c19b  2**0
                  CONTENTS, READONLY, DEBUGGING
 12 .debug_aranges 00000ae8  00000000  00000000  00033718  2**3
                  CONTENTS, READONLY, DEBUGGING
 13 .debug_ranges 00000e68  00000000  00000000  00034200  2**3
                  CONTENTS, READONLY, DEBUGGING
 14 .debug_line   00006b9d  00000000  00000000  00035068  2**0
                  CONTENTS, READONLY, DEBUGGING
 15 .debug_str    0000427d  00000000  00000000  0003bc05  2**0
                  CONTENTS, READONLY, DEBUGGING
 16 .comment      0000007c  00000000  00000000  0003fe82  2**0
                  CONTENTS, READONLY
 17 .debug_frame  00002770  00000000  00000000  0003ff00  2**2
                  CONTENTS, READONLY, DEBUGGING

Disassembly of section .text:

080041e4 <__do_global_dtors_aux>:
 80041e4:	b510      	push	{r4, lr}
 80041e6:	4c05      	ldr	r4, [pc, #20]	; (80041fc <__do_global_dtors_aux+0x18>)
 80041e8:	7823      	ldrb	r3, [r4, #0]
 80041ea:	b933      	cbnz	r3, 80041fa <__do_global_dtors_aux+0x16>
 80041ec:	4b04      	ldr	r3, [pc, #16]	; (8004200 <__do_global_dtors_aux+0x1c>)
 80041ee:	b113      	cbz	r3, 80041f6 <__do_global_dtors_aux+0x12>
 80041f0:	4804      	ldr	r0, [pc, #16]	; (8004204 <__do_global_dtors_aux+0x20>)
 80041f2:	f3af 8000 	nop.w
 80041f6:	2301      	movs	r3, #1
 80041f8:	7023      	strb	r3, [r4, #0]
 80041fa:	bd10      	pop	{r4, pc}
 80041fc:	20000070 	.word	0x20000070
 8004200:	00000000 	.word	0x00000000
 8004204:	080074c8 	.word	0x080074c8

08004208 <frame_dummy>:
 8004208:	b508      	push	{r3, lr}
 800420a:	4b03      	ldr	r3, [pc, #12]	; (8004218 <frame_dummy+0x10>)
 800420c:	b11b      	cbz	r3, 8004216 <frame_dummy+0xe>
 800420e:	4903      	ldr	r1, [pc, #12]	; (800421c <frame_dummy+0x14>)
 8004210:	4803      	ldr	r0, [pc, #12]	; (8004220 <frame_dummy+0x18>)
 8004212:	f3af 8000 	nop.w
 8004216:	bd08      	pop	{r3, pc}
 8004218:	00000000 	.word	0x00000000
 800421c:	20000074 	.word	0x20000074
 8004220:	080074c8 	.word	0x080074c8

08004224 <HAL_InitTick>:
  *       implementation  in user file.
  * @param TickPriority Tick interrupt priority.
  * @retval HAL status
  */
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
 8004224:	b538      	push	{r3, r4, r5, lr}
  /* Configure the SysTick to have interrupt in 1ms time basis*/
  if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
 8004226:	4b0e      	ldr	r3, [pc, #56]	; (8004260 <HAL_InitTick+0x3c>)
{
 8004228:	4605      	mov	r5, r0
  if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
 800422a:	7818      	ldrb	r0, [r3, #0]
 800422c:	f44f 737a 	mov.w	r3, #1000	; 0x3e8
 8004230:	fbb3 f3f0 	udiv	r3, r3, r0
 8004234:	4a0b      	ldr	r2, [pc, #44]	; (8004264 <HAL_InitTick+0x40>)
 8004236:	6810      	ldr	r0, [r2, #0]
 8004238:	fbb0 f0f3 	udiv	r0, r0, r3
 800423c:	f000 f9ce 	bl	80045dc <HAL_SYSTICK_Config>
 8004240:	4604      	mov	r4, r0
 8004242:	b958      	cbnz	r0, 800425c <HAL_InitTick+0x38>
  {
    return HAL_ERROR;
  }

  /* Configure the SysTick IRQ priority */
  if (TickPriority < (1UL << __NVIC_PRIO_BITS))
 8004244:	2d0f      	cmp	r5, #15
 8004246:	d809      	bhi.n	800425c <HAL_InitTick+0x38>
  {
    HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
 8004248:	4602      	mov	r2, r0
 800424a:	4629      	mov	r1, r5
 800424c:	f04f 30ff 	mov.w	r0, #4294967295
 8004250:	f000 f984 	bl	800455c <HAL_NVIC_SetPriority>
    uwTickPrio = TickPriority;
 8004254:	4b04      	ldr	r3, [pc, #16]	; (8004268 <HAL_InitTick+0x44>)
 8004256:	4620      	mov	r0, r4
 8004258:	601d      	str	r5, [r3, #0]
 800425a:	bd38      	pop	{r3, r4, r5, pc}
    return HAL_ERROR;
 800425c:	2001      	movs	r0, #1
    return HAL_ERROR;
  }

  /* Return function status */
  return HAL_OK;
}
 800425e:	bd38      	pop	{r3, r4, r5, pc}
 8004260:	20000000 	.word	0x20000000
 8004264:	20000008 	.word	0x20000008
 8004268:	20000004 	.word	0x20000004

0800426c <HAL_Init>:
  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
 800426c:	4a07      	ldr	r2, [pc, #28]	; (800428c <HAL_Init+0x20>)
{
 800426e:	b508      	push	{r3, lr}
  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
 8004270:	6813      	ldr	r3, [r2, #0]
  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
 8004272:	2003      	movs	r0, #3
  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
 8004274:	f043 0310 	orr.w	r3, r3, #16
 8004278:	6013      	str	r3, [r2, #0]
  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
 800427a:	f000 f95d 	bl	8004538 <HAL_NVIC_SetPriorityGrouping>
  HAL_InitTick(TICK_INT_PRIORITY);
 800427e:	2000      	movs	r0, #0
 8004280:	f7ff ffd0 	bl	8004224 <HAL_InitTick>
  HAL_MspInit();
 8004284:	f001 fe10 	bl	8005ea8 <HAL_MspInit>
}
 8004288:	2000      	movs	r0, #0
 800428a:	bd08      	pop	{r3, pc}
 800428c:	40022000 	.word	0x40022000

08004290 <HAL_IncTick>:
  *      implementations in user file.
  * @retval None
  */
__weak void HAL_IncTick(void)
{
  uwTick += uwTickFreq;
 8004290:	4a03      	ldr	r2, [pc, #12]	; (80042a0 <HAL_IncTick+0x10>)
 8004292:	4b04      	ldr	r3, [pc, #16]	; (80042a4 <HAL_IncTick+0x14>)
 8004294:	6811      	ldr	r1, [r2, #0]
 8004296:	781b      	ldrb	r3, [r3, #0]
 8004298:	440b      	add	r3, r1
 800429a:	6013      	str	r3, [r2, #0]
 800429c:	4770      	bx	lr
 800429e:	bf00      	nop
 80042a0:	200010a4 	.word	0x200010a4
 80042a4:	20000000 	.word	0x20000000

080042a8 <HAL_GetTick>:
  *       implementations in user file.
  * @retval tick value
  */
__weak uint32_t HAL_GetTick(void)
{
  return uwTick;
 80042a8:	4b01      	ldr	r3, [pc, #4]	; (80042b0 <HAL_GetTick+0x8>)
 80042aa:	6818      	ldr	r0, [r3, #0]
}
 80042ac:	4770      	bx	lr
 80042ae:	bf00      	nop
 80042b0:	200010a4 	.word	0x200010a4

080042b4 <HAL_Delay>:
  *       implementations in user file.
  * @param Delay specifies the delay time length, in milliseconds.
  * @retval None
  */
__weak void HAL_Delay(uint32_t Delay)
{
 80042b4:	b538      	push	{r3, r4, r5, lr}
 80042b6:	4604      	mov	r4, r0
  uint32_t tickstart = HAL_GetTick();
 80042b8:	f7ff fff6 	bl	80042a8 <HAL_GetTick>
 80042bc:	4605      	mov	r5, r0
  uint32_t wait = Delay;

  /* Add a freq to guarantee minimum wait */
  if (wait < HAL_MAX_DELAY)
 80042be:	1c63      	adds	r3, r4, #1
  {
    wait += (uint32_t)(uwTickFreq);
 80042c0:	bf1e      	ittt	ne
 80042c2:	4b04      	ldrne	r3, [pc, #16]	; (80042d4 <HAL_Delay+0x20>)
 80042c4:	781b      	ldrbne	r3, [r3, #0]
 80042c6:	18e4      	addne	r4, r4, r3
  }

  while ((HAL_GetTick() - tickstart) < wait)
 80042c8:	f7ff ffee 	bl	80042a8 <HAL_GetTick>
 80042cc:	1b40      	subs	r0, r0, r5
 80042ce:	4284      	cmp	r4, r0
 80042d0:	d8fa      	bhi.n	80042c8 <HAL_Delay+0x14>
  {
  }
}
 80042d2:	bd38      	pop	{r3, r4, r5, pc}
 80042d4:	20000000 	.word	0x20000000

080042d8 <HAL_ADC_ConfigChannel>:
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
{ 
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
  __IO uint32_t wait_loop_index = 0U;
 80042d8:	2300      	movs	r3, #0
{ 
 80042da:	b573      	push	{r0, r1, r4, r5, r6, lr}
  __IO uint32_t wait_loop_index = 0U;
 80042dc:	9301      	str	r3, [sp, #4]
  assert_param(IS_ADC_CHANNEL(sConfig->Channel));
  assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
  assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
  
  /* Process locked */
  __HAL_LOCK(hadc);
 80042de:	f890 3024 	ldrb.w	r3, [r0, #36]	; 0x24
 80042e2:	2b01      	cmp	r3, #1
 80042e4:	d074      	beq.n	80043d0 <HAL_ADC_ConfigChannel+0xf8>
 80042e6:	2301      	movs	r3, #1
  
  
  /* Regular sequence configuration */
  /* For Rank 1 to 6 */
  if (sConfig->Rank < 7U)
 80042e8:	684d      	ldr	r5, [r1, #4]
  __HAL_LOCK(hadc);
 80042ea:	f880 3024 	strb.w	r3, [r0, #36]	; 0x24
  if (sConfig->Rank < 7U)
 80042ee:	2d06      	cmp	r5, #6
 80042f0:	6802      	ldr	r2, [r0, #0]
 80042f2:	ea4f 0385 	mov.w	r3, r5, lsl #2
 80042f6:	680c      	ldr	r4, [r1, #0]
 80042f8:	d825      	bhi.n	8004346 <HAL_ADC_ConfigChannel+0x6e>
  {
    MODIFY_REG(hadc->Instance->SQR3                        ,
 80042fa:	442b      	add	r3, r5
 80042fc:	251f      	movs	r5, #31
 80042fe:	6b56      	ldr	r6, [r2, #52]	; 0x34
 8004300:	3b05      	subs	r3, #5
 8004302:	409d      	lsls	r5, r3
 8004304:	ea26 0505 	bic.w	r5, r6, r5
 8004308:	fa04 f303 	lsl.w	r3, r4, r3
 800430c:	432b      	orrs	r3, r5
 800430e:	6353      	str	r3, [r2, #52]	; 0x34
  }
  
  
  /* Channel sampling time configuration */
  /* For channels 10 to 17 */
  if (sConfig->Channel >= ADC_CHANNEL_10)
 8004310:	2c09      	cmp	r4, #9
 8004312:	ea4f 0344 	mov.w	r3, r4, lsl #1
 8004316:	688d      	ldr	r5, [r1, #8]
 8004318:	d92f      	bls.n	800437a <HAL_ADC_ConfigChannel+0xa2>
  {
    MODIFY_REG(hadc->Instance->SMPR1                             ,
 800431a:	2607      	movs	r6, #7
 800431c:	4423      	add	r3, r4
 800431e:	68d1      	ldr	r1, [r2, #12]
 8004320:	3b1e      	subs	r3, #30
 8004322:	409e      	lsls	r6, r3
 8004324:	ea21 0106 	bic.w	r1, r1, r6
 8004328:	fa05 f303 	lsl.w	r3, r5, r3
 800432c:	430b      	orrs	r3, r1
 800432e:	60d3      	str	r3, [r2, #12]
               ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
  }
  
  /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor  */
  /* and VREFINT measurement path.                                            */
  if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
 8004330:	f1a4 0310 	sub.w	r3, r4, #16
 8004334:	2b01      	cmp	r3, #1
 8004336:	d92b      	bls.n	8004390 <HAL_ADC_ConfigChannel+0xb8>
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
 8004338:	2300      	movs	r3, #0
      tmp_hal_status = HAL_ERROR;
    }
  }
  
  /* Process unlocked */
  __HAL_UNLOCK(hadc);
 800433a:	2200      	movs	r2, #0
 800433c:	f880 2024 	strb.w	r2, [r0, #36]	; 0x24
  
  /* Return function status */
  return tmp_hal_status;
}
 8004340:	4618      	mov	r0, r3
 8004342:	b002      	add	sp, #8
 8004344:	bd70      	pop	{r4, r5, r6, pc}
  else if (sConfig->Rank < 13U)
 8004346:	2d0c      	cmp	r5, #12
 8004348:	d80b      	bhi.n	8004362 <HAL_ADC_ConfigChannel+0x8a>
    MODIFY_REG(hadc->Instance->SQR2                        ,
 800434a:	442b      	add	r3, r5
 800434c:	251f      	movs	r5, #31
 800434e:	6b16      	ldr	r6, [r2, #48]	; 0x30
 8004350:	3b23      	subs	r3, #35	; 0x23
 8004352:	409d      	lsls	r5, r3
 8004354:	ea26 0505 	bic.w	r5, r6, r5
 8004358:	fa04 f303 	lsl.w	r3, r4, r3
 800435c:	432b      	orrs	r3, r5
 800435e:	6313      	str	r3, [r2, #48]	; 0x30
 8004360:	e7d6      	b.n	8004310 <HAL_ADC_ConfigChannel+0x38>
    MODIFY_REG(hadc->Instance->SQR1                        ,
 8004362:	442b      	add	r3, r5
 8004364:	251f      	movs	r5, #31
 8004366:	6ad6      	ldr	r6, [r2, #44]	; 0x2c
 8004368:	3b41      	subs	r3, #65	; 0x41
 800436a:	409d      	lsls	r5, r3
 800436c:	ea26 0505 	bic.w	r5, r6, r5
 8004370:	fa04 f303 	lsl.w	r3, r4, r3
 8004374:	432b      	orrs	r3, r5
 8004376:	62d3      	str	r3, [r2, #44]	; 0x2c
 8004378:	e7ca      	b.n	8004310 <HAL_ADC_ConfigChannel+0x38>
    MODIFY_REG(hadc->Instance->SMPR2                             ,
 800437a:	2607      	movs	r6, #7
 800437c:	6911      	ldr	r1, [r2, #16]
 800437e:	4423      	add	r3, r4
 8004380:	409e      	lsls	r6, r3
 8004382:	ea21 0106 	bic.w	r1, r1, r6
 8004386:	fa05 f303 	lsl.w	r3, r5, r3
 800438a:	430b      	orrs	r3, r1
 800438c:	6113      	str	r3, [r2, #16]
 800438e:	e7cf      	b.n	8004330 <HAL_ADC_ConfigChannel+0x58>
    if (hadc->Instance == ADC1)
 8004390:	4b10      	ldr	r3, [pc, #64]	; (80043d4 <HAL_ADC_ConfigChannel+0xfc>)
 8004392:	429a      	cmp	r2, r3
 8004394:	d116      	bne.n	80043c4 <HAL_ADC_ConfigChannel+0xec>
      if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET)
 8004396:	6893      	ldr	r3, [r2, #8]
 8004398:	021b      	lsls	r3, r3, #8
 800439a:	d4cd      	bmi.n	8004338 <HAL_ADC_ConfigChannel+0x60>
        SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
 800439c:	6893      	ldr	r3, [r2, #8]
        if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
 800439e:	2c10      	cmp	r4, #16
        SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
 80043a0:	f443 0300 	orr.w	r3, r3, #8388608	; 0x800000
 80043a4:	6093      	str	r3, [r2, #8]
        if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
 80043a6:	d1c7      	bne.n	8004338 <HAL_ADC_ConfigChannel+0x60>
          wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
 80043a8:	4b0b      	ldr	r3, [pc, #44]	; (80043d8 <HAL_ADC_ConfigChannel+0x100>)
 80043aa:	4a0c      	ldr	r2, [pc, #48]	; (80043dc <HAL_ADC_ConfigChannel+0x104>)
 80043ac:	681b      	ldr	r3, [r3, #0]
 80043ae:	fbb3 f2f2 	udiv	r2, r3, r2
 80043b2:	230a      	movs	r3, #10
 80043b4:	4353      	muls	r3, r2
            wait_loop_index--;
 80043b6:	9301      	str	r3, [sp, #4]
          while(wait_loop_index != 0U)
 80043b8:	9b01      	ldr	r3, [sp, #4]
 80043ba:	2b00      	cmp	r3, #0
 80043bc:	d0bc      	beq.n	8004338 <HAL_ADC_ConfigChannel+0x60>
            wait_loop_index--;
 80043be:	9b01      	ldr	r3, [sp, #4]
 80043c0:	3b01      	subs	r3, #1
 80043c2:	e7f8      	b.n	80043b6 <HAL_ADC_ConfigChannel+0xde>
      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
 80043c4:	6a83      	ldr	r3, [r0, #40]	; 0x28
 80043c6:	f043 0320 	orr.w	r3, r3, #32
 80043ca:	6283      	str	r3, [r0, #40]	; 0x28
      tmp_hal_status = HAL_ERROR;
 80043cc:	2301      	movs	r3, #1
 80043ce:	e7b4      	b.n	800433a <HAL_ADC_ConfigChannel+0x62>
  __HAL_LOCK(hadc);
 80043d0:	2302      	movs	r3, #2
 80043d2:	e7b5      	b.n	8004340 <HAL_ADC_ConfigChannel+0x68>
 80043d4:	40012400 	.word	0x40012400
 80043d8:	20000008 	.word	0x20000008
 80043dc:	000f4240 	.word	0x000f4240

080043e0 <ADC_ConversionStop_Disable>:
  *         stopped to disable the ADC.
  * @param  hadc: ADC handle
  * @retval HAL status.
  */
HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc)
{
 80043e0:	b538      	push	{r3, r4, r5, lr}
  uint32_t tickstart = 0U;
  
  /* Verification if ADC is not already disabled */
  if (ADC_IS_ENABLE(hadc) != RESET)
 80043e2:	6803      	ldr	r3, [r0, #0]
{
 80043e4:	4604      	mov	r4, r0
  if (ADC_IS_ENABLE(hadc) != RESET)
 80043e6:	689a      	ldr	r2, [r3, #8]
 80043e8:	07d2      	lsls	r2, r2, #31
 80043ea:	d401      	bmi.n	80043f0 <ADC_ConversionStop_Disable+0x10>
      }
    }
  }
  
  /* Return HAL status */
  return HAL_OK;
 80043ec:	2000      	movs	r0, #0
 80043ee:	bd38      	pop	{r3, r4, r5, pc}
    __HAL_ADC_DISABLE(hadc);
 80043f0:	689a      	ldr	r2, [r3, #8]
 80043f2:	f022 0201 	bic.w	r2, r2, #1
 80043f6:	609a      	str	r2, [r3, #8]
    tickstart = HAL_GetTick();
 80043f8:	f7ff ff56 	bl	80042a8 <HAL_GetTick>
 80043fc:	4605      	mov	r5, r0
    while(ADC_IS_ENABLE(hadc) != RESET)
 80043fe:	6823      	ldr	r3, [r4, #0]
 8004400:	689b      	ldr	r3, [r3, #8]
 8004402:	07db      	lsls	r3, r3, #31
 8004404:	d5f2      	bpl.n	80043ec <ADC_ConversionStop_Disable+0xc>
      if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
 8004406:	f7ff ff4f 	bl	80042a8 <HAL_GetTick>
 800440a:	1b40      	subs	r0, r0, r5
 800440c:	2802      	cmp	r0, #2
 800440e:	d9f6      	bls.n	80043fe <ADC_ConversionStop_Disable+0x1e>
        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
 8004410:	6aa3      	ldr	r3, [r4, #40]	; 0x28
        SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
 8004412:	2001      	movs	r0, #1
        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
 8004414:	f043 0310 	orr.w	r3, r3, #16
 8004418:	62a3      	str	r3, [r4, #40]	; 0x28
        SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
 800441a:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
 800441c:	f043 0301 	orr.w	r3, r3, #1
 8004420:	62e3      	str	r3, [r4, #44]	; 0x2c
 8004422:	bd38      	pop	{r3, r4, r5, pc}

08004424 <HAL_ADC_Init>:
{
 8004424:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
  if(hadc == NULL)
 8004426:	4604      	mov	r4, r0
 8004428:	2800      	cmp	r0, #0
 800442a:	d077      	beq.n	800451c <HAL_ADC_Init+0xf8>
  if (hadc->State == HAL_ADC_STATE_RESET)
 800442c:	6a83      	ldr	r3, [r0, #40]	; 0x28
 800442e:	b923      	cbnz	r3, 800443a <HAL_ADC_Init+0x16>
    ADC_CLEAR_ERRORCODE(hadc);
 8004430:	62c3      	str	r3, [r0, #44]	; 0x2c
    hadc->Lock = HAL_UNLOCKED;
 8004432:	f880 3024 	strb.w	r3, [r0, #36]	; 0x24
    HAL_ADC_MspInit(hadc);
 8004436:	f001 fd59 	bl	8005eec <HAL_ADC_MspInit>
  tmp_hal_status = ADC_ConversionStop_Disable(hadc);
 800443a:	4620      	mov	r0, r4
 800443c:	f7ff ffd0 	bl	80043e0 <ADC_ConversionStop_Disable>
  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
 8004440:	6aa3      	ldr	r3, [r4, #40]	; 0x28
 8004442:	f013 0310 	ands.w	r3, r3, #16
 8004446:	d16b      	bne.n	8004520 <HAL_ADC_Init+0xfc>
 8004448:	2800      	cmp	r0, #0
 800444a:	d169      	bne.n	8004520 <HAL_ADC_Init+0xfc>
    ADC_STATE_CLR_SET(hadc->State,
 800444c:	6aa2      	ldr	r2, [r4, #40]	; 0x28
                ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) |
 800444e:	4937      	ldr	r1, [pc, #220]	; (800452c <HAL_ADC_Init+0x108>)
    ADC_STATE_CLR_SET(hadc->State,
 8004450:	f422 5288 	bic.w	r2, r2, #4352	; 0x1100
 8004454:	f022 0202 	bic.w	r2, r2, #2
 8004458:	f042 0202 	orr.w	r2, r2, #2
 800445c:	62a2      	str	r2, [r4, #40]	; 0x28
                ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) |
 800445e:	e894 0024 	ldmia.w	r4, {r2, r5}
 8004462:	428a      	cmp	r2, r1
 8004464:	69e1      	ldr	r1, [r4, #28]
 8004466:	d104      	bne.n	8004472 <HAL_ADC_Init+0x4e>
 8004468:	f5b1 2f40 	cmp.w	r1, #786432	; 0xc0000
 800446c:	bf08      	it	eq
 800446e:	f44f 2100 	moveq.w	r1, #524288	; 0x80000
                ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode)   );
 8004472:	68e6      	ldr	r6, [r4, #12]
                ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) |
 8004474:	ea45 0546 	orr.w	r5, r5, r6, lsl #1
 8004478:	4329      	orrs	r1, r5
    tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode));
 800447a:	68a5      	ldr	r5, [r4, #8]
 800447c:	f5b5 7f80 	cmp.w	r5, #256	; 0x100
 8004480:	d035      	beq.n	80044ee <HAL_ADC_Init+0xca>
 8004482:	2d01      	cmp	r5, #1
 8004484:	bf08      	it	eq
 8004486:	f44f 7380 	moveq.w	r3, #256	; 0x100
    if (hadc->Init.DiscontinuousConvMode == ENABLE)
 800448a:	6967      	ldr	r7, [r4, #20]
 800448c:	2f01      	cmp	r7, #1
 800448e:	d106      	bne.n	800449e <HAL_ADC_Init+0x7a>
      if (hadc->Init.ContinuousConvMode == DISABLE)
 8004490:	bb7e      	cbnz	r6, 80044f2 <HAL_ADC_Init+0xce>
        SET_BIT(tmp_cr1, ADC_CR1_DISCEN                                            |
 8004492:	69a6      	ldr	r6, [r4, #24]
 8004494:	3e01      	subs	r6, #1
 8004496:	ea43 3346 	orr.w	r3, r3, r6, lsl #13
 800449a:	f443 6300 	orr.w	r3, r3, #2048	; 0x800
      MODIFY_REG(hadc->Instance->CR1,
 800449e:	6856      	ldr	r6, [r2, #4]
    if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE)
 80044a0:	f5b5 7f80 	cmp.w	r5, #256	; 0x100
      MODIFY_REG(hadc->Instance->CR1,
 80044a4:	f426 4669 	bic.w	r6, r6, #59648	; 0xe900
 80044a8:	ea43 0306 	orr.w	r3, r3, r6
 80044ac:	6053      	str	r3, [r2, #4]
      MODIFY_REG(hadc->Instance->CR2,
 80044ae:	6896      	ldr	r6, [r2, #8]
 80044b0:	4b1f      	ldr	r3, [pc, #124]	; (8004530 <HAL_ADC_Init+0x10c>)
 80044b2:	ea03 0306 	and.w	r3, r3, r6
 80044b6:	ea43 0301 	orr.w	r3, r3, r1
 80044ba:	6093      	str	r3, [r2, #8]
    if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE)
 80044bc:	d001      	beq.n	80044c2 <HAL_ADC_Init+0x9e>
 80044be:	2d01      	cmp	r5, #1
 80044c0:	d120      	bne.n	8004504 <HAL_ADC_Init+0xe0>
      tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion);
 80044c2:	6923      	ldr	r3, [r4, #16]
 80044c4:	3b01      	subs	r3, #1
 80044c6:	051b      	lsls	r3, r3, #20
    MODIFY_REG(hadc->Instance->SQR1,
 80044c8:	6ad5      	ldr	r5, [r2, #44]	; 0x2c
 80044ca:	f425 0570 	bic.w	r5, r5, #15728640	; 0xf00000
 80044ce:	432b      	orrs	r3, r5
 80044d0:	62d3      	str	r3, [r2, #44]	; 0x2c
    if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
 80044d2:	6892      	ldr	r2, [r2, #8]
 80044d4:	4b17      	ldr	r3, [pc, #92]	; (8004534 <HAL_ADC_Init+0x110>)
 80044d6:	4013      	ands	r3, r2
 80044d8:	4299      	cmp	r1, r3
 80044da:	d115      	bne.n	8004508 <HAL_ADC_Init+0xe4>
      ADC_CLEAR_ERRORCODE(hadc);
 80044dc:	2300      	movs	r3, #0
 80044de:	62e3      	str	r3, [r4, #44]	; 0x2c
      ADC_STATE_CLR_SET(hadc->State,
 80044e0:	6aa3      	ldr	r3, [r4, #40]	; 0x28
 80044e2:	f023 0303 	bic.w	r3, r3, #3
 80044e6:	f043 0301 	orr.w	r3, r3, #1
 80044ea:	62a3      	str	r3, [r4, #40]	; 0x28
 80044ec:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode));
 80044ee:	462b      	mov	r3, r5
 80044f0:	e7cb      	b.n	800448a <HAL_ADC_Init+0x66>
        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
 80044f2:	6aa6      	ldr	r6, [r4, #40]	; 0x28
 80044f4:	f046 0620 	orr.w	r6, r6, #32
 80044f8:	62a6      	str	r6, [r4, #40]	; 0x28
        SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
 80044fa:	6ae6      	ldr	r6, [r4, #44]	; 0x2c
 80044fc:	f046 0601 	orr.w	r6, r6, #1
 8004500:	62e6      	str	r6, [r4, #44]	; 0x2c
 8004502:	e7cc      	b.n	800449e <HAL_ADC_Init+0x7a>
  uint32_t tmp_sqr1 = 0U;
 8004504:	2300      	movs	r3, #0
 8004506:	e7df      	b.n	80044c8 <HAL_ADC_Init+0xa4>
      ADC_STATE_CLR_SET(hadc->State,
 8004508:	6aa3      	ldr	r3, [r4, #40]	; 0x28
 800450a:	f023 0312 	bic.w	r3, r3, #18
 800450e:	f043 0310 	orr.w	r3, r3, #16
 8004512:	62a3      	str	r3, [r4, #40]	; 0x28
      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
 8004514:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
 8004516:	f043 0301 	orr.w	r3, r3, #1
 800451a:	62e3      	str	r3, [r4, #44]	; 0x2c
    return HAL_ERROR;
 800451c:	2001      	movs	r0, #1
}
 800451e:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
 8004520:	6aa3      	ldr	r3, [r4, #40]	; 0x28
 8004522:	f043 0310 	orr.w	r3, r3, #16
 8004526:	62a3      	str	r3, [r4, #40]	; 0x28
 8004528:	e7f8      	b.n	800451c <HAL_ADC_Init+0xf8>
 800452a:	bf00      	nop
 800452c:	40013c00 	.word	0x40013c00
 8004530:	ffe1f7fd 	.word	0xffe1f7fd
 8004534:	ff1f0efe 	.word	0xff1f0efe

08004538 <HAL_NVIC_SetPriorityGrouping>:
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
  uint32_t reg_value;
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */

  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
 8004538:	4a07      	ldr	r2, [pc, #28]	; (8004558 <HAL_NVIC_SetPriorityGrouping+0x20>)
  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
  reg_value  =  (reg_value                                   |
                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
 800453a:	0200      	lsls	r0, r0, #8
  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
 800453c:	68d3      	ldr	r3, [r2, #12]
                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
 800453e:	f400 60e0 	and.w	r0, r0, #1792	; 0x700
  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
 8004542:	f423 63e0 	bic.w	r3, r3, #1792	; 0x700
 8004546:	041b      	lsls	r3, r3, #16
 8004548:	0c1b      	lsrs	r3, r3, #16
 800454a:	f043 63bf 	orr.w	r3, r3, #100139008	; 0x5f80000
 800454e:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
  reg_value  =  (reg_value                                   |
 8004552:	4303      	orrs	r3, r0
  SCB->AIRCR =  reg_value;
 8004554:	60d3      	str	r3, [r2, #12]
 8004556:	4770      	bx	lr
 8004558:	e000ed00 	.word	0xe000ed00

0800455c <HAL_NVIC_SetPriority>:
  \details Reads the priority grouping field from the NVIC Interrupt Controller.
  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
 */
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
{
  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
 800455c:	4b17      	ldr	r3, [pc, #92]	; (80045bc <HAL_NVIC_SetPriority+0x60>)
  *         This parameter can be a value between 0 and 15
  *         A lower priority value indicates a higher priority.          
  * @retval None
  */
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{ 
 800455e:	b530      	push	{r4, r5, lr}
 8004560:	68dc      	ldr	r4, [r3, #12]
 8004562:	f3c4 2402 	ubfx	r4, r4, #8, #3
{
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
  uint32_t PreemptPriorityBits;
  uint32_t SubPriorityBits;

  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
 8004566:	f1c4 0307 	rsb	r3, r4, #7
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 800456a:	1d25      	adds	r5, r4, #4
  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
 800456c:	2b04      	cmp	r3, #4
 800456e:	bf28      	it	cs
 8004570:	2304      	movcs	r3, #4
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 8004572:	2d06      	cmp	r5, #6

  return (
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 8004574:	f04f 0501 	mov.w	r5, #1
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 8004578:	bf98      	it	ls
 800457a:	2400      	movls	r4, #0
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 800457c:	fa05 f303 	lsl.w	r3, r5, r3
 8004580:	f103 33ff 	add.w	r3, r3, #4294967295
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 8004584:	bf88      	it	hi
 8004586:	3c03      	subhi	r4, #3
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 8004588:	4019      	ands	r1, r3
 800458a:	40a1      	lsls	r1, r4
           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
 800458c:	fa05 f404 	lsl.w	r4, r5, r4
 8004590:	3c01      	subs	r4, #1
 8004592:	4022      	ands	r2, r4
  if ((int32_t)(IRQn) < 0)
 8004594:	2800      	cmp	r0, #0
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 8004596:	ea42 0201 	orr.w	r2, r2, r1
 800459a:	ea4f 1202 	mov.w	r2, r2, lsl #4
    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 800459e:	bfaf      	iteee	ge
 80045a0:	f100 4060 	addge.w	r0, r0, #3758096384	; 0xe0000000
    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 80045a4:	4b06      	ldrlt	r3, [pc, #24]	; (80045c0 <HAL_NVIC_SetPriority+0x64>)
 80045a6:	f000 000f 	andlt.w	r0, r0, #15
 80045aa:	b2d2      	uxtblt	r2, r2
    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 80045ac:	bfa5      	ittet	ge
 80045ae:	b2d2      	uxtbge	r2, r2
 80045b0:	f500 4061 	addge.w	r0, r0, #57600	; 0xe100
    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 80045b4:	541a      	strblt	r2, [r3, r0]
    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 80045b6:	f880 2300 	strbge.w	r2, [r0, #768]	; 0x300
 80045ba:	bd30      	pop	{r4, r5, pc}
 80045bc:	e000ed00 	.word	0xe000ed00
 80045c0:	e000ed14 	.word	0xe000ed14

080045c4 <HAL_NVIC_EnableIRQ>:
  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
 80045c4:	2301      	movs	r3, #1
 80045c6:	0942      	lsrs	r2, r0, #5
 80045c8:	f000 001f 	and.w	r0, r0, #31
 80045cc:	fa03 f000 	lsl.w	r0, r3, r0
 80045d0:	4b01      	ldr	r3, [pc, #4]	; (80045d8 <HAL_NVIC_EnableIRQ+0x14>)
 80045d2:	f843 0022 	str.w	r0, [r3, r2, lsl #2]
 80045d6:	4770      	bx	lr
 80045d8:	e000e100 	.word	0xe000e100

080045dc <HAL_SYSTICK_Config>:
           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
           must contain a vendor-specific implementation of this function.
 */
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
 80045dc:	3801      	subs	r0, #1
 80045de:	f1b0 7f80 	cmp.w	r0, #16777216	; 0x1000000
 80045e2:	d20a      	bcs.n	80045fa <HAL_SYSTICK_Config+0x1e>
    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 80045e4:	21f0      	movs	r1, #240	; 0xf0
  {
    return (1UL);                                                   /* Reload value impossible */
  }

  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
 80045e6:	4b06      	ldr	r3, [pc, #24]	; (8004600 <HAL_SYSTICK_Config+0x24>)
    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 80045e8:	4a06      	ldr	r2, [pc, #24]	; (8004604 <HAL_SYSTICK_Config+0x28>)
  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
 80045ea:	6058      	str	r0, [r3, #4]
    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 80045ec:	f882 1023 	strb.w	r1, [r2, #35]	; 0x23
  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
 80045f0:	2000      	movs	r0, #0
  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
 80045f2:	2207      	movs	r2, #7
  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
 80045f4:	6098      	str	r0, [r3, #8]
  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
 80045f6:	601a      	str	r2, [r3, #0]
 80045f8:	4770      	bx	lr
    return (1UL);                                                   /* Reload value impossible */
 80045fa:	2001      	movs	r0, #1
  *                  - 1  Function failed.
  */
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
   return SysTick_Config(TicksNumb);
}
 80045fc:	4770      	bx	lr
 80045fe:	bf00      	nop
 8004600:	e000e010 	.word	0xe000e010
 8004604:	e000ed00 	.word	0xe000ed00

08004608 <HAL_DMA_Init>:
  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
  *               the configuration information for the specified DMA Channel.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
{
 8004608:	b510      	push	{r4, lr}
  uint32_t tmp = 0U;

  /* Check the DMA handle allocation */
  if(hdma == NULL)
 800460a:	2800      	cmp	r0, #0
 800460c:	d032      	beq.n	8004674 <HAL_DMA_Init+0x6c>
  assert_param(IS_DMA_MODE(hdma->Init.Mode));
  assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));

#if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F100xE) || defined (STM32F105xC) || defined (STM32F107xC)
  /* calculation of the channel index */
  if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
 800460e:	6801      	ldr	r1, [r0, #0]
 8004610:	4b19      	ldr	r3, [pc, #100]	; (8004678 <HAL_DMA_Init+0x70>)
 8004612:	2414      	movs	r4, #20
 8004614:	4299      	cmp	r1, r3
 8004616:	d825      	bhi.n	8004664 <HAL_DMA_Init+0x5c>
  {
    /* DMA1 */
    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
 8004618:	4a18      	ldr	r2, [pc, #96]	; (800467c <HAL_DMA_Init+0x74>)
    hdma->DmaBaseAddress = DMA1;
 800461a:	f2a3 4307 	subw	r3, r3, #1031	; 0x407
    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
 800461e:	440a      	add	r2, r1
 8004620:	fbb2 f2f4 	udiv	r2, r2, r4
 8004624:	0092      	lsls	r2, r2, #2
 8004626:	6402      	str	r2, [r0, #64]	; 0x40
  tmp &= ((uint32_t)~(DMA_CCR_PL    | DMA_CCR_MSIZE  | DMA_CCR_PSIZE  | \
                      DMA_CCR_MINC  | DMA_CCR_PINC   | DMA_CCR_CIRC   | \
                      DMA_CCR_DIR));

  /* Prepare the DMA Channel configuration */
  tmp |=  hdma->Init.Direction        |
 8004628:	6884      	ldr	r4, [r0, #8]
    hdma->DmaBaseAddress = DMA2;
 800462a:	63c3      	str	r3, [r0, #60]	; 0x3c
  tmp |=  hdma->Init.Direction        |
 800462c:	6843      	ldr	r3, [r0, #4]
  tmp = hdma->Instance->CCR;
 800462e:	680a      	ldr	r2, [r1, #0]
  tmp |=  hdma->Init.Direction        |
 8004630:	4323      	orrs	r3, r4
          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
 8004632:	68c4      	ldr	r4, [r0, #12]
  tmp &= ((uint32_t)~(DMA_CCR_PL    | DMA_CCR_MSIZE  | DMA_CCR_PSIZE  | \
 8004634:	f422 527f 	bic.w	r2, r2, #16320	; 0x3fc0
          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
 8004638:	4323      	orrs	r3, r4
 800463a:	6904      	ldr	r4, [r0, #16]
  tmp &= ((uint32_t)~(DMA_CCR_PL    | DMA_CCR_MSIZE  | DMA_CCR_PSIZE  | \
 800463c:	f022 0230 	bic.w	r2, r2, #48	; 0x30
          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
 8004640:	4323      	orrs	r3, r4
          hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
 8004642:	6944      	ldr	r4, [r0, #20]
 8004644:	4323      	orrs	r3, r4
 8004646:	6984      	ldr	r4, [r0, #24]
 8004648:	4323      	orrs	r3, r4
          hdma->Init.Mode                | hdma->Init.Priority;
 800464a:	69c4      	ldr	r4, [r0, #28]
 800464c:	4323      	orrs	r3, r4
  tmp |=  hdma->Init.Direction        |
 800464e:	4313      	orrs	r3, r2

  /* Write to DMA Channel CR register */
  hdma->Instance->CCR = tmp;
 8004650:	600b      	str	r3, [r1, #0]

  /* Initialise the error code */
  hdma->ErrorCode = HAL_DMA_ERROR_NONE;

  /* Initialize the DMA state*/
  hdma->State = HAL_DMA_STATE_READY;
 8004652:	2201      	movs	r2, #1
  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
 8004654:	2300      	movs	r3, #0
  hdma->State = HAL_DMA_STATE_READY;
 8004656:	f880 2021 	strb.w	r2, [r0, #33]	; 0x21
  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
 800465a:	6383      	str	r3, [r0, #56]	; 0x38
  /* Allocate lock resource and initialize it */
  hdma->Lock = HAL_UNLOCKED;
 800465c:	f880 3020 	strb.w	r3, [r0, #32]

  return HAL_OK;
 8004660:	4618      	mov	r0, r3
 8004662:	bd10      	pop	{r4, pc}
    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
 8004664:	4b06      	ldr	r3, [pc, #24]	; (8004680 <HAL_DMA_Init+0x78>)
 8004666:	440b      	add	r3, r1
 8004668:	fbb3 f3f4 	udiv	r3, r3, r4
 800466c:	009b      	lsls	r3, r3, #2
 800466e:	6403      	str	r3, [r0, #64]	; 0x40
    hdma->DmaBaseAddress = DMA2;
 8004670:	4b04      	ldr	r3, [pc, #16]	; (8004684 <HAL_DMA_Init+0x7c>)
 8004672:	e7d9      	b.n	8004628 <HAL_DMA_Init+0x20>
    return HAL_ERROR;
 8004674:	2001      	movs	r0, #1
}
 8004676:	bd10      	pop	{r4, pc}
 8004678:	40020407 	.word	0x40020407
 800467c:	bffdfff8 	.word	0xbffdfff8
 8004680:	bffdfbf8 	.word	0xbffdfbf8
 8004684:	40020400 	.word	0x40020400

08004688 <HAL_DMA_Start_IT>:
  * @param  DstAddress: The destination memory Buffer address
  * @param  DataLength: The length of data to be transferred from source to destination
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
 8004688:	b5f0      	push	{r4, r5, r6, r7, lr}

  /* Check the parameters */
  assert_param(IS_DMA_BUFFER_SIZE(DataLength));

  /* Process locked */
  __HAL_LOCK(hdma);
 800468a:	f890 4020 	ldrb.w	r4, [r0, #32]
 800468e:	2c01      	cmp	r4, #1
 8004690:	d035      	beq.n	80046fe <HAL_DMA_Start_IT+0x76>
 8004692:	2401      	movs	r4, #1
  
  if(HAL_DMA_STATE_READY == hdma->State)
 8004694:	f890 5021 	ldrb.w	r5, [r0, #33]	; 0x21
  __HAL_LOCK(hdma);
 8004698:	f880 4020 	strb.w	r4, [r0, #32]
  if(HAL_DMA_STATE_READY == hdma->State)
 800469c:	42a5      	cmp	r5, r4
 800469e:	f04f 0600 	mov.w	r6, #0
 80046a2:	f04f 0402 	mov.w	r4, #2
 80046a6:	d128      	bne.n	80046fa <HAL_DMA_Start_IT+0x72>
  {
    /* Change DMA peripheral state */
    hdma->State = HAL_DMA_STATE_BUSY;
 80046a8:	f880 4021 	strb.w	r4, [r0, #33]	; 0x21
    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
    
    /* Disable the peripheral */
    __HAL_DMA_DISABLE(hdma);
 80046ac:	6804      	ldr	r4, [r0, #0]
    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
 80046ae:	6386      	str	r6, [r0, #56]	; 0x38
    __HAL_DMA_DISABLE(hdma);
 80046b0:	6826      	ldr	r6, [r4, #0]
  * @retval HAL status
  */
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
  /* Clear all flags */
  hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
 80046b2:	6c07      	ldr	r7, [r0, #64]	; 0x40
    __HAL_DMA_DISABLE(hdma);
 80046b4:	f026 0601 	bic.w	r6, r6, #1
 80046b8:	6026      	str	r6, [r4, #0]
  hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
 80046ba:	6bc6      	ldr	r6, [r0, #60]	; 0x3c
 80046bc:	40bd      	lsls	r5, r7
 80046be:	6075      	str	r5, [r6, #4]

  /* Configure DMA Channel data length */
  hdma->Instance->CNDTR = DataLength;
 80046c0:	6063      	str	r3, [r4, #4]

  /* Memory to Peripheral */
  if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
 80046c2:	6843      	ldr	r3, [r0, #4]
 80046c4:	6805      	ldr	r5, [r0, #0]
 80046c6:	2b10      	cmp	r3, #16
    if(NULL != hdma->XferHalfCpltCallback)
 80046c8:	6ac3      	ldr	r3, [r0, #44]	; 0x2c
  {
    /* Configure DMA Channel destination address */
    hdma->Instance->CPAR = DstAddress;
 80046ca:	bf0b      	itete	eq
 80046cc:	60a2      	streq	r2, [r4, #8]
  }
  /* Peripheral to Memory */
  else
  {
    /* Configure DMA Channel source address */
    hdma->Instance->CPAR = SrcAddress;
 80046ce:	60a1      	strne	r1, [r4, #8]
    hdma->Instance->CMAR = SrcAddress;
 80046d0:	60e1      	streq	r1, [r4, #12]

    /* Configure DMA Channel destination address */
    hdma->Instance->CMAR = DstAddress;
 80046d2:	60e2      	strne	r2, [r4, #12]
    if(NULL != hdma->XferHalfCpltCallback)
 80046d4:	b14b      	cbz	r3, 80046ea <HAL_DMA_Start_IT+0x62>
      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
 80046d6:	6823      	ldr	r3, [r4, #0]
 80046d8:	f043 030e 	orr.w	r3, r3, #14
      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
 80046dc:	6023      	str	r3, [r4, #0]
    __HAL_DMA_ENABLE(hdma);
 80046de:	682b      	ldr	r3, [r5, #0]
  HAL_StatusTypeDef status = HAL_OK;
 80046e0:	2000      	movs	r0, #0
    __HAL_DMA_ENABLE(hdma);
 80046e2:	f043 0301 	orr.w	r3, r3, #1
 80046e6:	602b      	str	r3, [r5, #0]
 80046e8:	bdf0      	pop	{r4, r5, r6, r7, pc}
      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
 80046ea:	6823      	ldr	r3, [r4, #0]
 80046ec:	f023 0304 	bic.w	r3, r3, #4
 80046f0:	6023      	str	r3, [r4, #0]
      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
 80046f2:	6823      	ldr	r3, [r4, #0]
 80046f4:	f043 030a 	orr.w	r3, r3, #10
 80046f8:	e7f0      	b.n	80046dc <HAL_DMA_Start_IT+0x54>
    __HAL_UNLOCK(hdma); 
 80046fa:	f880 6020 	strb.w	r6, [r0, #32]
  __HAL_LOCK(hdma);
 80046fe:	2002      	movs	r0, #2
}
 8004700:	bdf0      	pop	{r4, r5, r6, r7, pc}
	...

08004704 <HAL_DMA_Abort_IT>:
  if(HAL_DMA_STATE_BUSY != hdma->State)
 8004704:	f890 3021 	ldrb.w	r3, [r0, #33]	; 0x21
{  
 8004708:	b510      	push	{r4, lr}
  if(HAL_DMA_STATE_BUSY != hdma->State)
 800470a:	2b02      	cmp	r3, #2
 800470c:	d003      	beq.n	8004716 <HAL_DMA_Abort_IT+0x12>
    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
 800470e:	2304      	movs	r3, #4
 8004710:	6383      	str	r3, [r0, #56]	; 0x38
    status = HAL_ERROR;
 8004712:	2001      	movs	r0, #1
 8004714:	bd10      	pop	{r4, pc}
    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
 8004716:	6803      	ldr	r3, [r0, #0]
 8004718:	681a      	ldr	r2, [r3, #0]
 800471a:	f022 020e 	bic.w	r2, r2, #14
 800471e:	601a      	str	r2, [r3, #0]
    __HAL_DMA_DISABLE(hdma);
 8004720:	681a      	ldr	r2, [r3, #0]
 8004722:	f022 0201 	bic.w	r2, r2, #1
 8004726:	601a      	str	r2, [r3, #0]
    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma));
 8004728:	4a29      	ldr	r2, [pc, #164]	; (80047d0 <HAL_DMA_Abort_IT+0xcc>)
 800472a:	4293      	cmp	r3, r2
 800472c:	d924      	bls.n	8004778 <HAL_DMA_Abort_IT+0x74>
 800472e:	f502 7262 	add.w	r2, r2, #904	; 0x388
 8004732:	4293      	cmp	r3, r2
 8004734:	d019      	beq.n	800476a <HAL_DMA_Abort_IT+0x66>
 8004736:	3214      	adds	r2, #20
 8004738:	4293      	cmp	r3, r2
 800473a:	d018      	beq.n	800476e <HAL_DMA_Abort_IT+0x6a>
 800473c:	3214      	adds	r2, #20
 800473e:	4293      	cmp	r3, r2
 8004740:	d017      	beq.n	8004772 <HAL_DMA_Abort_IT+0x6e>
 8004742:	3214      	adds	r2, #20
 8004744:	4293      	cmp	r3, r2
 8004746:	bf0c      	ite	eq
 8004748:	f44f 5380 	moveq.w	r3, #4096	; 0x1000
 800474c:	f44f 3380 	movne.w	r3, #65536	; 0x10000
 8004750:	4a20      	ldr	r2, [pc, #128]	; (80047d4 <HAL_DMA_Abort_IT+0xd0>)
 8004752:	6053      	str	r3, [r2, #4]
    hdma->State = HAL_DMA_STATE_READY;
 8004754:	2301      	movs	r3, #1
    __HAL_UNLOCK(hdma);
 8004756:	2400      	movs	r4, #0
    hdma->State = HAL_DMA_STATE_READY;
 8004758:	f880 3021 	strb.w	r3, [r0, #33]	; 0x21
    if(hdma->XferAbortCallback != NULL)
 800475c:	6b43      	ldr	r3, [r0, #52]	; 0x34
    __HAL_UNLOCK(hdma);
 800475e:	f880 4020 	strb.w	r4, [r0, #32]
    if(hdma->XferAbortCallback != NULL)
 8004762:	b39b      	cbz	r3, 80047cc <HAL_DMA_Abort_IT+0xc8>
      hdma->XferAbortCallback(hdma);
 8004764:	4798      	blx	r3
  HAL_StatusTypeDef status = HAL_OK;
 8004766:	4620      	mov	r0, r4
 8004768:	bd10      	pop	{r4, pc}
    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma));
 800476a:	2301      	movs	r3, #1
 800476c:	e7f0      	b.n	8004750 <HAL_DMA_Abort_IT+0x4c>
 800476e:	2310      	movs	r3, #16
 8004770:	e7ee      	b.n	8004750 <HAL_DMA_Abort_IT+0x4c>
 8004772:	f44f 7380 	mov.w	r3, #256	; 0x100
 8004776:	e7eb      	b.n	8004750 <HAL_DMA_Abort_IT+0x4c>
 8004778:	4917      	ldr	r1, [pc, #92]	; (80047d8 <HAL_DMA_Abort_IT+0xd4>)
 800477a:	428b      	cmp	r3, r1
 800477c:	d016      	beq.n	80047ac <HAL_DMA_Abort_IT+0xa8>
 800477e:	3114      	adds	r1, #20
 8004780:	428b      	cmp	r3, r1
 8004782:	d015      	beq.n	80047b0 <HAL_DMA_Abort_IT+0xac>
 8004784:	3114      	adds	r1, #20
 8004786:	428b      	cmp	r3, r1
 8004788:	d014      	beq.n	80047b4 <HAL_DMA_Abort_IT+0xb0>
 800478a:	3114      	adds	r1, #20
 800478c:	428b      	cmp	r3, r1
 800478e:	d014      	beq.n	80047ba <HAL_DMA_Abort_IT+0xb6>
 8004790:	3114      	adds	r1, #20
 8004792:	428b      	cmp	r3, r1
 8004794:	d014      	beq.n	80047c0 <HAL_DMA_Abort_IT+0xbc>
 8004796:	3114      	adds	r1, #20
 8004798:	428b      	cmp	r3, r1
 800479a:	d014      	beq.n	80047c6 <HAL_DMA_Abort_IT+0xc2>
 800479c:	4293      	cmp	r3, r2
 800479e:	bf14      	ite	ne
 80047a0:	f44f 3380 	movne.w	r3, #65536	; 0x10000
 80047a4:	f04f 7380 	moveq.w	r3, #16777216	; 0x1000000
 80047a8:	4a0c      	ldr	r2, [pc, #48]	; (80047dc <HAL_DMA_Abort_IT+0xd8>)
 80047aa:	e7d2      	b.n	8004752 <HAL_DMA_Abort_IT+0x4e>
 80047ac:	2301      	movs	r3, #1
 80047ae:	e7fb      	b.n	80047a8 <HAL_DMA_Abort_IT+0xa4>
 80047b0:	2310      	movs	r3, #16
 80047b2:	e7f9      	b.n	80047a8 <HAL_DMA_Abort_IT+0xa4>
 80047b4:	f44f 7380 	mov.w	r3, #256	; 0x100
 80047b8:	e7f6      	b.n	80047a8 <HAL_DMA_Abort_IT+0xa4>
 80047ba:	f44f 5380 	mov.w	r3, #4096	; 0x1000
 80047be:	e7f3      	b.n	80047a8 <HAL_DMA_Abort_IT+0xa4>
 80047c0:	f44f 3380 	mov.w	r3, #65536	; 0x10000
 80047c4:	e7f0      	b.n	80047a8 <HAL_DMA_Abort_IT+0xa4>
 80047c6:	f44f 1380 	mov.w	r3, #1048576	; 0x100000
 80047ca:	e7ed      	b.n	80047a8 <HAL_DMA_Abort_IT+0xa4>
  HAL_StatusTypeDef status = HAL_OK;
 80047cc:	4618      	mov	r0, r3
}
 80047ce:	bd10      	pop	{r4, pc}
 80047d0:	40020080 	.word	0x40020080
 80047d4:	40020400 	.word	0x40020400
 80047d8:	40020008 	.word	0x40020008
 80047dc:	40020000 	.word	0x40020000

080047e0 <HAL_DMA_IRQHandler>:
{
 80047e0:	b470      	push	{r4, r5, r6}
  if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET))
 80047e2:	2504      	movs	r5, #4
  uint32_t flag_it = hdma->DmaBaseAddress->ISR;
 80047e4:	6bc6      	ldr	r6, [r0, #60]	; 0x3c
  if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET))
 80047e6:	6c02      	ldr	r2, [r0, #64]	; 0x40
  uint32_t flag_it = hdma->DmaBaseAddress->ISR;
 80047e8:	6834      	ldr	r4, [r6, #0]
  uint32_t source_it = hdma->Instance->CCR;
 80047ea:	6803      	ldr	r3, [r0, #0]
  if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET))
 80047ec:	4095      	lsls	r5, r2
 80047ee:	4225      	tst	r5, r4
  uint32_t source_it = hdma->Instance->CCR;
 80047f0:	6819      	ldr	r1, [r3, #0]
  if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET))
 80047f2:	d055      	beq.n	80048a0 <HAL_DMA_IRQHandler+0xc0>
 80047f4:	074d      	lsls	r5, r1, #29
 80047f6:	d553      	bpl.n	80048a0 <HAL_DMA_IRQHandler+0xc0>
    if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
 80047f8:	681a      	ldr	r2, [r3, #0]
 80047fa:	0696      	lsls	r6, r2, #26
      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
 80047fc:	bf5e      	ittt	pl
 80047fe:	681a      	ldrpl	r2, [r3, #0]
 8004800:	f022 0204 	bicpl.w	r2, r2, #4
 8004804:	601a      	strpl	r2, [r3, #0]
    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
 8004806:	4a60      	ldr	r2, [pc, #384]	; (8004988 <HAL_DMA_IRQHandler+0x1a8>)
 8004808:	4293      	cmp	r3, r2
 800480a:	d91f      	bls.n	800484c <HAL_DMA_IRQHandler+0x6c>
 800480c:	f502 7262 	add.w	r2, r2, #904	; 0x388
 8004810:	4293      	cmp	r3, r2
 8004812:	d014      	beq.n	800483e <HAL_DMA_IRQHandler+0x5e>
 8004814:	3214      	adds	r2, #20
 8004816:	4293      	cmp	r3, r2
 8004818:	d013      	beq.n	8004842 <HAL_DMA_IRQHandler+0x62>
 800481a:	3214      	adds	r2, #20
 800481c:	4293      	cmp	r3, r2
 800481e:	d012      	beq.n	8004846 <HAL_DMA_IRQHandler+0x66>
 8004820:	3214      	adds	r2, #20
 8004822:	4293      	cmp	r3, r2
 8004824:	bf0c      	ite	eq
 8004826:	f44f 4380 	moveq.w	r3, #16384	; 0x4000
 800482a:	f44f 2380 	movne.w	r3, #262144	; 0x40000
 800482e:	4a57      	ldr	r2, [pc, #348]	; (800498c <HAL_DMA_IRQHandler+0x1ac>)
 8004830:	6053      	str	r3, [r2, #4]
    if(hdma->XferHalfCpltCallback != NULL)
 8004832:	6ac3      	ldr	r3, [r0, #44]	; 0x2c
    if (hdma->XferErrorCallback != NULL)
 8004834:	2b00      	cmp	r3, #0
 8004836:	f000 80a5 	beq.w	8004984 <HAL_DMA_IRQHandler+0x1a4>
}
 800483a:	bc70      	pop	{r4, r5, r6}
      hdma->XferErrorCallback(hdma);
 800483c:	4718      	bx	r3
    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
 800483e:	2304      	movs	r3, #4
 8004840:	e7f5      	b.n	800482e <HAL_DMA_IRQHandler+0x4e>
 8004842:	2340      	movs	r3, #64	; 0x40
 8004844:	e7f3      	b.n	800482e <HAL_DMA_IRQHandler+0x4e>
 8004846:	f44f 6380 	mov.w	r3, #1024	; 0x400
 800484a:	e7f0      	b.n	800482e <HAL_DMA_IRQHandler+0x4e>
 800484c:	4950      	ldr	r1, [pc, #320]	; (8004990 <HAL_DMA_IRQHandler+0x1b0>)
 800484e:	428b      	cmp	r3, r1
 8004850:	d016      	beq.n	8004880 <HAL_DMA_IRQHandler+0xa0>
 8004852:	3114      	adds	r1, #20
 8004854:	428b      	cmp	r3, r1
 8004856:	d015      	beq.n	8004884 <HAL_DMA_IRQHandler+0xa4>
 8004858:	3114      	adds	r1, #20
 800485a:	428b      	cmp	r3, r1
 800485c:	d014      	beq.n	8004888 <HAL_DMA_IRQHandler+0xa8>
 800485e:	3114      	adds	r1, #20
 8004860:	428b      	cmp	r3, r1
 8004862:	d014      	beq.n	800488e <HAL_DMA_IRQHandler+0xae>
 8004864:	3114      	adds	r1, #20
 8004866:	428b      	cmp	r3, r1
 8004868:	d014      	beq.n	8004894 <HAL_DMA_IRQHandler+0xb4>
 800486a:	3114      	adds	r1, #20
 800486c:	428b      	cmp	r3, r1
 800486e:	d014      	beq.n	800489a <HAL_DMA_IRQHandler+0xba>
 8004870:	4293      	cmp	r3, r2
 8004872:	bf14      	ite	ne
 8004874:	f44f 2380 	movne.w	r3, #262144	; 0x40000
 8004878:	f04f 6380 	moveq.w	r3, #67108864	; 0x4000000
 800487c:	4a45      	ldr	r2, [pc, #276]	; (8004994 <HAL_DMA_IRQHandler+0x1b4>)
 800487e:	e7d7      	b.n	8004830 <HAL_DMA_IRQHandler+0x50>
 8004880:	2304      	movs	r3, #4
 8004882:	e7fb      	b.n	800487c <HAL_DMA_IRQHandler+0x9c>
 8004884:	2340      	movs	r3, #64	; 0x40
 8004886:	e7f9      	b.n	800487c <HAL_DMA_IRQHandler+0x9c>
 8004888:	f44f 6380 	mov.w	r3, #1024	; 0x400
 800488c:	e7f6      	b.n	800487c <HAL_DMA_IRQHandler+0x9c>
 800488e:	f44f 4380 	mov.w	r3, #16384	; 0x4000
 8004892:	e7f3      	b.n	800487c <HAL_DMA_IRQHandler+0x9c>
 8004894:	f44f 2380 	mov.w	r3, #262144	; 0x40000
 8004898:	e7f0      	b.n	800487c <HAL_DMA_IRQHandler+0x9c>
 800489a:	f44f 0380 	mov.w	r3, #4194304	; 0x400000
 800489e:	e7ed      	b.n	800487c <HAL_DMA_IRQHandler+0x9c>
  else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET))
 80048a0:	2502      	movs	r5, #2
 80048a2:	4095      	lsls	r5, r2
 80048a4:	4225      	tst	r5, r4
 80048a6:	d057      	beq.n	8004958 <HAL_DMA_IRQHandler+0x178>
 80048a8:	078d      	lsls	r5, r1, #30
 80048aa:	d555      	bpl.n	8004958 <HAL_DMA_IRQHandler+0x178>
    if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
 80048ac:	681a      	ldr	r2, [r3, #0]
 80048ae:	0694      	lsls	r4, r2, #26
 80048b0:	d406      	bmi.n	80048c0 <HAL_DMA_IRQHandler+0xe0>
      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);  
 80048b2:	681a      	ldr	r2, [r3, #0]
 80048b4:	f022 020a 	bic.w	r2, r2, #10
 80048b8:	601a      	str	r2, [r3, #0]
      hdma->State = HAL_DMA_STATE_READY;
 80048ba:	2201      	movs	r2, #1
 80048bc:	f880 2021 	strb.w	r2, [r0, #33]	; 0x21
      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
 80048c0:	4a31      	ldr	r2, [pc, #196]	; (8004988 <HAL_DMA_IRQHandler+0x1a8>)
 80048c2:	4293      	cmp	r3, r2
 80048c4:	d91e      	bls.n	8004904 <HAL_DMA_IRQHandler+0x124>
 80048c6:	f502 7262 	add.w	r2, r2, #904	; 0x388
 80048ca:	4293      	cmp	r3, r2
 80048cc:	d013      	beq.n	80048f6 <HAL_DMA_IRQHandler+0x116>
 80048ce:	3214      	adds	r2, #20
 80048d0:	4293      	cmp	r3, r2
 80048d2:	d012      	beq.n	80048fa <HAL_DMA_IRQHandler+0x11a>
 80048d4:	3214      	adds	r2, #20
 80048d6:	4293      	cmp	r3, r2
 80048d8:	d011      	beq.n	80048fe <HAL_DMA_IRQHandler+0x11e>
 80048da:	3214      	adds	r2, #20
 80048dc:	4293      	cmp	r3, r2
 80048de:	bf0c      	ite	eq
 80048e0:	f44f 5300 	moveq.w	r3, #8192	; 0x2000
 80048e4:	f44f 3300 	movne.w	r3, #131072	; 0x20000
 80048e8:	4a28      	ldr	r2, [pc, #160]	; (800498c <HAL_DMA_IRQHandler+0x1ac>)
 80048ea:	6053      	str	r3, [r2, #4]
    __HAL_UNLOCK(hdma);
 80048ec:	2300      	movs	r3, #0
 80048ee:	f880 3020 	strb.w	r3, [r0, #32]
    if(hdma->XferCpltCallback != NULL)
 80048f2:	6a83      	ldr	r3, [r0, #40]	; 0x28
 80048f4:	e79e      	b.n	8004834 <HAL_DMA_IRQHandler+0x54>
      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
 80048f6:	2302      	movs	r3, #2
 80048f8:	e7f6      	b.n	80048e8 <HAL_DMA_IRQHandler+0x108>
 80048fa:	2320      	movs	r3, #32
 80048fc:	e7f4      	b.n	80048e8 <HAL_DMA_IRQHandler+0x108>
 80048fe:	f44f 7300 	mov.w	r3, #512	; 0x200
 8004902:	e7f1      	b.n	80048e8 <HAL_DMA_IRQHandler+0x108>
 8004904:	4922      	ldr	r1, [pc, #136]	; (8004990 <HAL_DMA_IRQHandler+0x1b0>)
 8004906:	428b      	cmp	r3, r1
 8004908:	d016      	beq.n	8004938 <HAL_DMA_IRQHandler+0x158>
 800490a:	3114      	adds	r1, #20
 800490c:	428b      	cmp	r3, r1
 800490e:	d015      	beq.n	800493c <HAL_DMA_IRQHandler+0x15c>
 8004910:	3114      	adds	r1, #20
 8004912:	428b      	cmp	r3, r1
 8004914:	d014      	beq.n	8004940 <HAL_DMA_IRQHandler+0x160>
 8004916:	3114      	adds	r1, #20
 8004918:	428b      	cmp	r3, r1
 800491a:	d014      	beq.n	8004946 <HAL_DMA_IRQHandler+0x166>
 800491c:	3114      	adds	r1, #20
 800491e:	428b      	cmp	r3, r1
 8004920:	d014      	beq.n	800494c <HAL_DMA_IRQHandler+0x16c>
 8004922:	3114      	adds	r1, #20
 8004924:	428b      	cmp	r3, r1
 8004926:	d014      	beq.n	8004952 <HAL_DMA_IRQHandler+0x172>
 8004928:	4293      	cmp	r3, r2
 800492a:	bf14      	ite	ne
 800492c:	f44f 3300 	movne.w	r3, #131072	; 0x20000
 8004930:	f04f 7300 	moveq.w	r3, #33554432	; 0x2000000
 8004934:	4a17      	ldr	r2, [pc, #92]	; (8004994 <HAL_DMA_IRQHandler+0x1b4>)
 8004936:	e7d8      	b.n	80048ea <HAL_DMA_IRQHandler+0x10a>
 8004938:	2302      	movs	r3, #2
 800493a:	e7fb      	b.n	8004934 <HAL_DMA_IRQHandler+0x154>
 800493c:	2320      	movs	r3, #32
 800493e:	e7f9      	b.n	8004934 <HAL_DMA_IRQHandler+0x154>
 8004940:	f44f 7300 	mov.w	r3, #512	; 0x200
 8004944:	e7f6      	b.n	8004934 <HAL_DMA_IRQHandler+0x154>
 8004946:	f44f 5300 	mov.w	r3, #8192	; 0x2000
 800494a:	e7f3      	b.n	8004934 <HAL_DMA_IRQHandler+0x154>
 800494c:	f44f 3300 	mov.w	r3, #131072	; 0x20000
 8004950:	e7f0      	b.n	8004934 <HAL_DMA_IRQHandler+0x154>
 8004952:	f44f 1300 	mov.w	r3, #2097152	; 0x200000
 8004956:	e7ed      	b.n	8004934 <HAL_DMA_IRQHandler+0x154>
  else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
 8004958:	2508      	movs	r5, #8
 800495a:	4095      	lsls	r5, r2
 800495c:	4225      	tst	r5, r4
 800495e:	d011      	beq.n	8004984 <HAL_DMA_IRQHandler+0x1a4>
 8004960:	0709      	lsls	r1, r1, #28
 8004962:	d50f      	bpl.n	8004984 <HAL_DMA_IRQHandler+0x1a4>
    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
 8004964:	6819      	ldr	r1, [r3, #0]
 8004966:	f021 010e 	bic.w	r1, r1, #14
 800496a:	6019      	str	r1, [r3, #0]
    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
 800496c:	2301      	movs	r3, #1
 800496e:	fa03 f202 	lsl.w	r2, r3, r2
 8004972:	6072      	str	r2, [r6, #4]
    hdma->ErrorCode = HAL_DMA_ERROR_TE;
 8004974:	6383      	str	r3, [r0, #56]	; 0x38
    hdma->State = HAL_DMA_STATE_READY;
 8004976:	f880 3021 	strb.w	r3, [r0, #33]	; 0x21
    __HAL_UNLOCK(hdma);
 800497a:	2300      	movs	r3, #0
 800497c:	f880 3020 	strb.w	r3, [r0, #32]
    if (hdma->XferErrorCallback != NULL)
 8004980:	6b03      	ldr	r3, [r0, #48]	; 0x30
 8004982:	e757      	b.n	8004834 <HAL_DMA_IRQHandler+0x54>
}
 8004984:	bc70      	pop	{r4, r5, r6}
 8004986:	4770      	bx	lr
 8004988:	40020080 	.word	0x40020080
 800498c:	40020400 	.word	0x40020400
 8004990:	40020008 	.word	0x40020008
 8004994:	40020000 	.word	0x40020000

08004998 <HAL_GPIO_Init>:
  * @param  GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
  *         the configuration information for the specified GPIO peripheral.
  * @retval None
  */
void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
 8004998:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
  uint32_t position;
  uint32_t ioposition = 0x00U;
  uint32_t iocurrent = 0x00U;
  uint32_t temp = 0x00U;
  uint32_t config = 0x00U;
 800499c:	2200      	movs	r2, #0
  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));

  /* Configure the port pins */
  for (position = 0U; position < GPIO_NUMBER; position++)
 800499e:	4616      	mov	r6, r2
      /*--------------------- EXTI Mode Configuration ------------------------*/
      /* Configure the External Interrupt or event for the current IO */
      if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
      {
        /* Enable AFIO Clock */
        __HAL_RCC_AFIO_CLK_ENABLE();
 80049a0:	4f6c      	ldr	r7, [pc, #432]	; (8004b54 <HAL_GPIO_Init+0x1bc>)
 80049a2:	4b6d      	ldr	r3, [pc, #436]	; (8004b58 <HAL_GPIO_Init+0x1c0>)
        temp = AFIO->EXTICR[position >> 2U];
        CLEAR_BIT(temp, (0x0FU) << (4U * (position & 0x03U)));
        SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
 80049a4:	f8df e1b8 	ldr.w	lr, [pc, #440]	; 8004b60 <HAL_GPIO_Init+0x1c8>
      switch (GPIO_Init->Mode)
 80049a8:	f8df c1b8 	ldr.w	ip, [pc, #440]	; 8004b64 <HAL_GPIO_Init+0x1cc>
    ioposition = (0x01U << position);
 80049ac:	f04f 0801 	mov.w	r8, #1
    iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
 80049b0:	680c      	ldr	r4, [r1, #0]
    ioposition = (0x01U << position);
 80049b2:	fa08 f806 	lsl.w	r8, r8, r6
    iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
 80049b6:	ea08 0404 	and.w	r4, r8, r4
    if (iocurrent == ioposition)
 80049ba:	45a0      	cmp	r8, r4
 80049bc:	f040 8085 	bne.w	8004aca <HAL_GPIO_Init+0x132>
      switch (GPIO_Init->Mode)
 80049c0:	684d      	ldr	r5, [r1, #4]
 80049c2:	2d12      	cmp	r5, #18
 80049c4:	f000 80b7 	beq.w	8004b36 <HAL_GPIO_Init+0x19e>
 80049c8:	f200 808d 	bhi.w	8004ae6 <HAL_GPIO_Init+0x14e>
 80049cc:	2d02      	cmp	r5, #2
 80049ce:	f000 80af 	beq.w	8004b30 <HAL_GPIO_Init+0x198>
 80049d2:	f200 8081 	bhi.w	8004ad8 <HAL_GPIO_Init+0x140>
 80049d6:	2d00      	cmp	r5, #0
 80049d8:	f000 8091 	beq.w	8004afe <HAL_GPIO_Init+0x166>
 80049dc:	2d01      	cmp	r5, #1
 80049de:	f000 80a5 	beq.w	8004b2c <HAL_GPIO_Init+0x194>
      MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
 80049e2:	f04f 090f 	mov.w	r9, #15
      configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL     : &GPIOx->CRH;
 80049e6:	2cff      	cmp	r4, #255	; 0xff
 80049e8:	bf93      	iteet	ls
 80049ea:	4682      	movls	sl, r0
 80049ec:	f106 4580 	addhi.w	r5, r6, #1073741824	; 0x40000000
 80049f0:	3d08      	subhi	r5, #8
 80049f2:	f8d0 b000 	ldrls.w	fp, [r0]
 80049f6:	bf92      	itee	ls
 80049f8:	00b5      	lslls	r5, r6, #2
 80049fa:	f8d0 b004 	ldrhi.w	fp, [r0, #4]
 80049fe:	00ad      	lslhi	r5, r5, #2
      MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
 8004a00:	fa09 f805 	lsl.w	r8, r9, r5
 8004a04:	ea2b 0808 	bic.w	r8, fp, r8
 8004a08:	fa02 f505 	lsl.w	r5, r2, r5
      configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL     : &GPIOx->CRH;
 8004a0c:	bf88      	it	hi
 8004a0e:	f100 0a04 	addhi.w	sl, r0, #4
      MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
 8004a12:	ea48 0505 	orr.w	r5, r8, r5
 8004a16:	f8ca 5000 	str.w	r5, [sl]
      if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
 8004a1a:	f8d1 a004 	ldr.w	sl, [r1, #4]
 8004a1e:	f01a 5f80 	tst.w	sl, #268435456	; 0x10000000
 8004a22:	d052      	beq.n	8004aca <HAL_GPIO_Init+0x132>
        __HAL_RCC_AFIO_CLK_ENABLE();
 8004a24:	69bd      	ldr	r5, [r7, #24]
 8004a26:	f026 0803 	bic.w	r8, r6, #3
 8004a2a:	f045 0501 	orr.w	r5, r5, #1
 8004a2e:	61bd      	str	r5, [r7, #24]
 8004a30:	69bd      	ldr	r5, [r7, #24]
 8004a32:	f108 4880 	add.w	r8, r8, #1073741824	; 0x40000000
 8004a36:	f005 0501 	and.w	r5, r5, #1
 8004a3a:	9501      	str	r5, [sp, #4]
 8004a3c:	f508 3880 	add.w	r8, r8, #65536	; 0x10000
        CLEAR_BIT(temp, (0x0FU) << (4U * (position & 0x03U)));
 8004a40:	f006 0b03 	and.w	fp, r6, #3
        __HAL_RCC_AFIO_CLK_ENABLE();
 8004a44:	9d01      	ldr	r5, [sp, #4]
        CLEAR_BIT(temp, (0x0FU) << (4U * (position & 0x03U)));
 8004a46:	ea4f 0b8b 	mov.w	fp, fp, lsl #2
        temp = AFIO->EXTICR[position >> 2U];
 8004a4a:	f8d8 5008 	ldr.w	r5, [r8, #8]
        CLEAR_BIT(temp, (0x0FU) << (4U * (position & 0x03U)));
 8004a4e:	fa09 f90b 	lsl.w	r9, r9, fp
 8004a52:	ea25 0909 	bic.w	r9, r5, r9
        SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
 8004a56:	4d41      	ldr	r5, [pc, #260]	; (8004b5c <HAL_GPIO_Init+0x1c4>)
 8004a58:	42a8      	cmp	r0, r5
 8004a5a:	d071      	beq.n	8004b40 <HAL_GPIO_Init+0x1a8>
 8004a5c:	f505 6580 	add.w	r5, r5, #1024	; 0x400
 8004a60:	42a8      	cmp	r0, r5
 8004a62:	d06f      	beq.n	8004b44 <HAL_GPIO_Init+0x1ac>
 8004a64:	f505 6580 	add.w	r5, r5, #1024	; 0x400
 8004a68:	42a8      	cmp	r0, r5
 8004a6a:	d06d      	beq.n	8004b48 <HAL_GPIO_Init+0x1b0>
 8004a6c:	f505 6580 	add.w	r5, r5, #1024	; 0x400
 8004a70:	42a8      	cmp	r0, r5
 8004a72:	d06b      	beq.n	8004b4c <HAL_GPIO_Init+0x1b4>
 8004a74:	f505 6580 	add.w	r5, r5, #1024	; 0x400
 8004a78:	42a8      	cmp	r0, r5
 8004a7a:	d069      	beq.n	8004b50 <HAL_GPIO_Init+0x1b8>
 8004a7c:	4570      	cmp	r0, lr
 8004a7e:	bf0c      	ite	eq
 8004a80:	2505      	moveq	r5, #5
 8004a82:	2506      	movne	r5, #6
 8004a84:	fa05 f50b 	lsl.w	r5, r5, fp
 8004a88:	ea45 0509 	orr.w	r5, r5, r9
        AFIO->EXTICR[position >> 2U] = temp;
 8004a8c:	f8c8 5008 	str.w	r5, [r8, #8]


        /* Configure the interrupt mask */
        if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
        {
          SET_BIT(EXTI->IMR, iocurrent);
 8004a90:	681d      	ldr	r5, [r3, #0]
        if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
 8004a92:	f41a 3f80 	tst.w	sl, #65536	; 0x10000
          SET_BIT(EXTI->IMR, iocurrent);
 8004a96:	bf14      	ite	ne
 8004a98:	4325      	orrne	r5, r4
        }
        else
        {
          CLEAR_BIT(EXTI->IMR, iocurrent);
 8004a9a:	43a5      	biceq	r5, r4
 8004a9c:	601d      	str	r5, [r3, #0]
        }

        /* Configure the event mask */
        if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
        {
          SET_BIT(EXTI->EMR, iocurrent);
 8004a9e:	685d      	ldr	r5, [r3, #4]
        if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
 8004aa0:	f41a 3f00 	tst.w	sl, #131072	; 0x20000
          SET_BIT(EXTI->EMR, iocurrent);
 8004aa4:	bf14      	ite	ne
 8004aa6:	4325      	orrne	r5, r4
        }
        else
        {
          CLEAR_BIT(EXTI->EMR, iocurrent);
 8004aa8:	43a5      	biceq	r5, r4
 8004aaa:	605d      	str	r5, [r3, #4]
        }

        /* Enable or disable the rising trigger */
        if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
        {
          SET_BIT(EXTI->RTSR, iocurrent);
 8004aac:	689d      	ldr	r5, [r3, #8]
        if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
 8004aae:	f41a 1f80 	tst.w	sl, #1048576	; 0x100000
          SET_BIT(EXTI->RTSR, iocurrent);
 8004ab2:	bf14      	ite	ne
 8004ab4:	4325      	orrne	r5, r4
        }
        else
        {
          CLEAR_BIT(EXTI->RTSR, iocurrent);
 8004ab6:	43a5      	biceq	r5, r4
 8004ab8:	609d      	str	r5, [r3, #8]
        }

        /* Enable or disable the falling trigger */
        if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
        {
          SET_BIT(EXTI->FTSR, iocurrent);
 8004aba:	68dd      	ldr	r5, [r3, #12]
        if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
 8004abc:	f41a 1f00 	tst.w	sl, #2097152	; 0x200000
          SET_BIT(EXTI->FTSR, iocurrent);
 8004ac0:	bf14      	ite	ne
 8004ac2:	432c      	orrne	r4, r5
        }
        else
        {
          CLEAR_BIT(EXTI->FTSR, iocurrent);
 8004ac4:	ea25 0404 	biceq.w	r4, r5, r4
 8004ac8:	60dc      	str	r4, [r3, #12]
  for (position = 0U; position < GPIO_NUMBER; position++)
 8004aca:	3601      	adds	r6, #1
 8004acc:	2e10      	cmp	r6, #16
 8004ace:	f47f af6d 	bne.w	80049ac <HAL_GPIO_Init+0x14>
        }
      }
    }
  }
}
 8004ad2:	b003      	add	sp, #12
 8004ad4:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
      switch (GPIO_Init->Mode)
 8004ad8:	2d03      	cmp	r5, #3
 8004ada:	d025      	beq.n	8004b28 <HAL_GPIO_Init+0x190>
 8004adc:	2d11      	cmp	r5, #17
 8004ade:	d180      	bne.n	80049e2 <HAL_GPIO_Init+0x4a>
          config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;
 8004ae0:	68ca      	ldr	r2, [r1, #12]
 8004ae2:	3204      	adds	r2, #4
          break;
 8004ae4:	e77d      	b.n	80049e2 <HAL_GPIO_Init+0x4a>
      switch (GPIO_Init->Mode)
 8004ae6:	4565      	cmp	r5, ip
 8004ae8:	d009      	beq.n	8004afe <HAL_GPIO_Init+0x166>
 8004aea:	d812      	bhi.n	8004b12 <HAL_GPIO_Init+0x17a>
 8004aec:	f8df 9078 	ldr.w	r9, [pc, #120]	; 8004b68 <HAL_GPIO_Init+0x1d0>
 8004af0:	454d      	cmp	r5, r9
 8004af2:	d004      	beq.n	8004afe <HAL_GPIO_Init+0x166>
 8004af4:	f509 3980 	add.w	r9, r9, #65536	; 0x10000
 8004af8:	454d      	cmp	r5, r9
 8004afa:	f47f af72 	bne.w	80049e2 <HAL_GPIO_Init+0x4a>
          if (GPIO_Init->Pull == GPIO_NOPULL)
 8004afe:	688a      	ldr	r2, [r1, #8]
 8004b00:	b1e2      	cbz	r2, 8004b3c <HAL_GPIO_Init+0x1a4>
          else if (GPIO_Init->Pull == GPIO_PULLUP)
 8004b02:	2a01      	cmp	r2, #1
            GPIOx->BSRR = ioposition;
 8004b04:	bf0c      	ite	eq
 8004b06:	f8c0 8010 	streq.w	r8, [r0, #16]
            GPIOx->BRR = ioposition;
 8004b0a:	f8c0 8014 	strne.w	r8, [r0, #20]
            config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
 8004b0e:	2208      	movs	r2, #8
 8004b10:	e767      	b.n	80049e2 <HAL_GPIO_Init+0x4a>
      switch (GPIO_Init->Mode)
 8004b12:	f8df 9058 	ldr.w	r9, [pc, #88]	; 8004b6c <HAL_GPIO_Init+0x1d4>
 8004b16:	454d      	cmp	r5, r9
 8004b18:	d0f1      	beq.n	8004afe <HAL_GPIO_Init+0x166>
 8004b1a:	f509 3980 	add.w	r9, r9, #65536	; 0x10000
 8004b1e:	454d      	cmp	r5, r9
 8004b20:	d0ed      	beq.n	8004afe <HAL_GPIO_Init+0x166>
 8004b22:	f5a9 1980 	sub.w	r9, r9, #1048576	; 0x100000
 8004b26:	e7e7      	b.n	8004af8 <HAL_GPIO_Init+0x160>
          config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
 8004b28:	2200      	movs	r2, #0
 8004b2a:	e75a      	b.n	80049e2 <HAL_GPIO_Init+0x4a>
          config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;
 8004b2c:	68ca      	ldr	r2, [r1, #12]
          break;
 8004b2e:	e758      	b.n	80049e2 <HAL_GPIO_Init+0x4a>
          config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;
 8004b30:	68ca      	ldr	r2, [r1, #12]
 8004b32:	3208      	adds	r2, #8
          break;
 8004b34:	e755      	b.n	80049e2 <HAL_GPIO_Init+0x4a>
          config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;
 8004b36:	68ca      	ldr	r2, [r1, #12]
 8004b38:	320c      	adds	r2, #12
          break;
 8004b3a:	e752      	b.n	80049e2 <HAL_GPIO_Init+0x4a>
            config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
 8004b3c:	2204      	movs	r2, #4
 8004b3e:	e750      	b.n	80049e2 <HAL_GPIO_Init+0x4a>
        SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
 8004b40:	2500      	movs	r5, #0
 8004b42:	e79f      	b.n	8004a84 <HAL_GPIO_Init+0xec>
 8004b44:	2501      	movs	r5, #1
 8004b46:	e79d      	b.n	8004a84 <HAL_GPIO_Init+0xec>
 8004b48:	2502      	movs	r5, #2
 8004b4a:	e79b      	b.n	8004a84 <HAL_GPIO_Init+0xec>
 8004b4c:	2503      	movs	r5, #3
 8004b4e:	e799      	b.n	8004a84 <HAL_GPIO_Init+0xec>
 8004b50:	2504      	movs	r5, #4
 8004b52:	e797      	b.n	8004a84 <HAL_GPIO_Init+0xec>
 8004b54:	40021000 	.word	0x40021000
 8004b58:	40010400 	.word	0x40010400
 8004b5c:	40010800 	.word	0x40010800
 8004b60:	40011c00 	.word	0x40011c00
 8004b64:	10210000 	.word	0x10210000
 8004b68:	10110000 	.word	0x10110000
 8004b6c:	10310000 	.word	0x10310000

08004b70 <HAL_GPIO_WritePin>:
{
  /* Check the parameters */
  assert_param(IS_GPIO_PIN(GPIO_Pin));
  assert_param(IS_GPIO_PIN_ACTION(PinState));

  if (PinState != GPIO_PIN_RESET)
 8004b70:	b10a      	cbz	r2, 8004b76 <HAL_GPIO_WritePin+0x6>
  {
    GPIOx->BSRR = GPIO_Pin;
  }
  else
  {
    GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
 8004b72:	6101      	str	r1, [r0, #16]
 8004b74:	4770      	bx	lr
 8004b76:	0409      	lsls	r1, r1, #16
 8004b78:	e7fb      	b.n	8004b72 <HAL_GPIO_WritePin+0x2>

08004b7a <HAL_GPIO_TogglePin>:
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
  /* Check the parameters */
  assert_param(IS_GPIO_PIN(GPIO_Pin));

  GPIOx->ODR ^= GPIO_Pin;
 8004b7a:	68c3      	ldr	r3, [r0, #12]
 8004b7c:	4059      	eors	r1, r3
 8004b7e:	60c1      	str	r1, [r0, #12]
 8004b80:	4770      	bx	lr
	...

08004b84 <HAL_RCC_OscConfig>:
  /* Check the parameters */
  assert_param(RCC_OscInitStruct != NULL);
  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
  
  /*------------------------------- HSE Configuration ------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
 8004b84:	6803      	ldr	r3, [r0, #0]
{
 8004b86:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
 8004b8a:	07db      	lsls	r3, r3, #31
{
 8004b8c:	4605      	mov	r5, r0
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
 8004b8e:	d410      	bmi.n	8004bb2 <HAL_RCC_OscConfig+0x2e>
        }
      }
    }
  }
  /*----------------------------- HSI Configuration --------------------------*/ 
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
 8004b90:	682b      	ldr	r3, [r5, #0]
 8004b92:	079f      	lsls	r7, r3, #30
 8004b94:	d45e      	bmi.n	8004c54 <HAL_RCC_OscConfig+0xd0>
        }
      }
    }
  }
  /*------------------------------ LSI Configuration -------------------------*/ 
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
 8004b96:	682b      	ldr	r3, [r5, #0]
 8004b98:	0719      	lsls	r1, r3, #28
 8004b9a:	f100 8095 	bmi.w	8004cc8 <HAL_RCC_OscConfig+0x144>
        }
      }
    }
  }
  /*------------------------------ LSE Configuration -------------------------*/ 
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
 8004b9e:	682b      	ldr	r3, [r5, #0]
 8004ba0:	075a      	lsls	r2, r3, #29
 8004ba2:	f100 80bf 	bmi.w	8004d24 <HAL_RCC_OscConfig+0x1a0>

#endif /* RCC_CR_PLL2ON */
  /*-------------------------------- PLL Configuration -----------------------*/
  /* Check the parameters */
  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
 8004ba6:	69ea      	ldr	r2, [r5, #28]
 8004ba8:	2a00      	cmp	r2, #0
 8004baa:	f040 812d 	bne.w	8004e08 <HAL_RCC_OscConfig+0x284>
    {
      return HAL_ERROR;
    }
  }
  
  return HAL_OK;
 8004bae:	2000      	movs	r0, #0
 8004bb0:	e014      	b.n	8004bdc <HAL_RCC_OscConfig+0x58>
    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 
 8004bb2:	4c90      	ldr	r4, [pc, #576]	; (8004df4 <HAL_RCC_OscConfig+0x270>)
 8004bb4:	6863      	ldr	r3, [r4, #4]
 8004bb6:	f003 030c 	and.w	r3, r3, #12
 8004bba:	2b04      	cmp	r3, #4
 8004bbc:	d007      	beq.n	8004bce <HAL_RCC_OscConfig+0x4a>
       || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
 8004bbe:	6863      	ldr	r3, [r4, #4]
 8004bc0:	f003 030c 	and.w	r3, r3, #12
 8004bc4:	2b08      	cmp	r3, #8
 8004bc6:	d10c      	bne.n	8004be2 <HAL_RCC_OscConfig+0x5e>
 8004bc8:	6863      	ldr	r3, [r4, #4]
 8004bca:	03de      	lsls	r6, r3, #15
 8004bcc:	d509      	bpl.n	8004be2 <HAL_RCC_OscConfig+0x5e>
      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
 8004bce:	6823      	ldr	r3, [r4, #0]
 8004bd0:	039c      	lsls	r4, r3, #14
 8004bd2:	d5dd      	bpl.n	8004b90 <HAL_RCC_OscConfig+0xc>
 8004bd4:	686b      	ldr	r3, [r5, #4]
 8004bd6:	2b00      	cmp	r3, #0
 8004bd8:	d1da      	bne.n	8004b90 <HAL_RCC_OscConfig+0xc>
        return HAL_ERROR;
 8004bda:	2001      	movs	r0, #1
}
 8004bdc:	b002      	add	sp, #8
 8004bde:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 8004be2:	686b      	ldr	r3, [r5, #4]
 8004be4:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
 8004be8:	d110      	bne.n	8004c0c <HAL_RCC_OscConfig+0x88>
 8004bea:	6823      	ldr	r3, [r4, #0]
 8004bec:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
 8004bf0:	6023      	str	r3, [r4, #0]
        tickstart = HAL_GetTick();
 8004bf2:	f7ff fb59 	bl	80042a8 <HAL_GetTick>
 8004bf6:	4606      	mov	r6, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 8004bf8:	6823      	ldr	r3, [r4, #0]
 8004bfa:	0398      	lsls	r0, r3, #14
 8004bfc:	d4c8      	bmi.n	8004b90 <HAL_RCC_OscConfig+0xc>
          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
 8004bfe:	f7ff fb53 	bl	80042a8 <HAL_GetTick>
 8004c02:	1b80      	subs	r0, r0, r6
 8004c04:	2864      	cmp	r0, #100	; 0x64
 8004c06:	d9f7      	bls.n	8004bf8 <HAL_RCC_OscConfig+0x74>
            return HAL_TIMEOUT;
 8004c08:	2003      	movs	r0, #3
 8004c0a:	e7e7      	b.n	8004bdc <HAL_RCC_OscConfig+0x58>
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 8004c0c:	b99b      	cbnz	r3, 8004c36 <HAL_RCC_OscConfig+0xb2>
 8004c0e:	6823      	ldr	r3, [r4, #0]
 8004c10:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
 8004c14:	6023      	str	r3, [r4, #0]
 8004c16:	6823      	ldr	r3, [r4, #0]
 8004c18:	f423 2380 	bic.w	r3, r3, #262144	; 0x40000
 8004c1c:	6023      	str	r3, [r4, #0]
        tickstart = HAL_GetTick();
 8004c1e:	f7ff fb43 	bl	80042a8 <HAL_GetTick>
 8004c22:	4606      	mov	r6, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
 8004c24:	6823      	ldr	r3, [r4, #0]
 8004c26:	0399      	lsls	r1, r3, #14
 8004c28:	d5b2      	bpl.n	8004b90 <HAL_RCC_OscConfig+0xc>
           if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
 8004c2a:	f7ff fb3d 	bl	80042a8 <HAL_GetTick>
 8004c2e:	1b80      	subs	r0, r0, r6
 8004c30:	2864      	cmp	r0, #100	; 0x64
 8004c32:	d9f7      	bls.n	8004c24 <HAL_RCC_OscConfig+0xa0>
 8004c34:	e7e8      	b.n	8004c08 <HAL_RCC_OscConfig+0x84>
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 8004c36:	f5b3 2fa0 	cmp.w	r3, #327680	; 0x50000
 8004c3a:	6823      	ldr	r3, [r4, #0]
 8004c3c:	d103      	bne.n	8004c46 <HAL_RCC_OscConfig+0xc2>
 8004c3e:	f443 2380 	orr.w	r3, r3, #262144	; 0x40000
 8004c42:	6023      	str	r3, [r4, #0]
 8004c44:	e7d1      	b.n	8004bea <HAL_RCC_OscConfig+0x66>
 8004c46:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
 8004c4a:	6023      	str	r3, [r4, #0]
 8004c4c:	6823      	ldr	r3, [r4, #0]
 8004c4e:	f423 2380 	bic.w	r3, r3, #262144	; 0x40000
 8004c52:	e7cd      	b.n	8004bf0 <HAL_RCC_OscConfig+0x6c>
    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 
 8004c54:	4c67      	ldr	r4, [pc, #412]	; (8004df4 <HAL_RCC_OscConfig+0x270>)
 8004c56:	6863      	ldr	r3, [r4, #4]
 8004c58:	f013 0f0c 	tst.w	r3, #12
 8004c5c:	d007      	beq.n	8004c6e <HAL_RCC_OscConfig+0xea>
       || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
 8004c5e:	6863      	ldr	r3, [r4, #4]
 8004c60:	f003 030c 	and.w	r3, r3, #12
 8004c64:	2b08      	cmp	r3, #8
 8004c66:	d110      	bne.n	8004c8a <HAL_RCC_OscConfig+0x106>
 8004c68:	6863      	ldr	r3, [r4, #4]
 8004c6a:	03da      	lsls	r2, r3, #15
 8004c6c:	d40d      	bmi.n	8004c8a <HAL_RCC_OscConfig+0x106>
      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
 8004c6e:	6823      	ldr	r3, [r4, #0]
 8004c70:	079b      	lsls	r3, r3, #30
 8004c72:	d502      	bpl.n	8004c7a <HAL_RCC_OscConfig+0xf6>
 8004c74:	692b      	ldr	r3, [r5, #16]
 8004c76:	2b01      	cmp	r3, #1
 8004c78:	d1af      	bne.n	8004bda <HAL_RCC_OscConfig+0x56>
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 8004c7a:	6823      	ldr	r3, [r4, #0]
 8004c7c:	696a      	ldr	r2, [r5, #20]
 8004c7e:	f023 03f8 	bic.w	r3, r3, #248	; 0xf8
 8004c82:	ea43 03c2 	orr.w	r3, r3, r2, lsl #3
 8004c86:	6023      	str	r3, [r4, #0]
 8004c88:	e785      	b.n	8004b96 <HAL_RCC_OscConfig+0x12>
      if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
 8004c8a:	692a      	ldr	r2, [r5, #16]
 8004c8c:	4b5a      	ldr	r3, [pc, #360]	; (8004df8 <HAL_RCC_OscConfig+0x274>)
 8004c8e:	b16a      	cbz	r2, 8004cac <HAL_RCC_OscConfig+0x128>
        __HAL_RCC_HSI_ENABLE();
 8004c90:	2201      	movs	r2, #1
 8004c92:	601a      	str	r2, [r3, #0]
        tickstart = HAL_GetTick();
 8004c94:	f7ff fb08 	bl	80042a8 <HAL_GetTick>
 8004c98:	4606      	mov	r6, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 8004c9a:	6823      	ldr	r3, [r4, #0]
 8004c9c:	079f      	lsls	r7, r3, #30
 8004c9e:	d4ec      	bmi.n	8004c7a <HAL_RCC_OscConfig+0xf6>
          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
 8004ca0:	f7ff fb02 	bl	80042a8 <HAL_GetTick>
 8004ca4:	1b80      	subs	r0, r0, r6
 8004ca6:	2802      	cmp	r0, #2
 8004ca8:	d9f7      	bls.n	8004c9a <HAL_RCC_OscConfig+0x116>
 8004caa:	e7ad      	b.n	8004c08 <HAL_RCC_OscConfig+0x84>
        __HAL_RCC_HSI_DISABLE();
 8004cac:	601a      	str	r2, [r3, #0]
        tickstart = HAL_GetTick();
 8004cae:	f7ff fafb 	bl	80042a8 <HAL_GetTick>
 8004cb2:	4606      	mov	r6, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
 8004cb4:	6823      	ldr	r3, [r4, #0]
 8004cb6:	0798      	lsls	r0, r3, #30
 8004cb8:	f57f af6d 	bpl.w	8004b96 <HAL_RCC_OscConfig+0x12>
          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
 8004cbc:	f7ff faf4 	bl	80042a8 <HAL_GetTick>
 8004cc0:	1b80      	subs	r0, r0, r6
 8004cc2:	2802      	cmp	r0, #2
 8004cc4:	d9f6      	bls.n	8004cb4 <HAL_RCC_OscConfig+0x130>
 8004cc6:	e79f      	b.n	8004c08 <HAL_RCC_OscConfig+0x84>
    if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
 8004cc8:	69aa      	ldr	r2, [r5, #24]
 8004cca:	4c4a      	ldr	r4, [pc, #296]	; (8004df4 <HAL_RCC_OscConfig+0x270>)
 8004ccc:	4b4b      	ldr	r3, [pc, #300]	; (8004dfc <HAL_RCC_OscConfig+0x278>)
 8004cce:	b1da      	cbz	r2, 8004d08 <HAL_RCC_OscConfig+0x184>
      __HAL_RCC_LSI_ENABLE();
 8004cd0:	2201      	movs	r2, #1
 8004cd2:	601a      	str	r2, [r3, #0]
      tickstart = HAL_GetTick();
 8004cd4:	f7ff fae8 	bl	80042a8 <HAL_GetTick>
 8004cd8:	4606      	mov	r6, r0
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
 8004cda:	6a63      	ldr	r3, [r4, #36]	; 0x24
 8004cdc:	079b      	lsls	r3, r3, #30
 8004cde:	d50d      	bpl.n	8004cfc <HAL_RCC_OscConfig+0x178>
  * @param  mdelay: specifies the delay time length, in milliseconds.
  * @retval None
  */
static void RCC_Delay(uint32_t mdelay)
{
  __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
 8004ce0:	f44f 52fa 	mov.w	r2, #8000	; 0x1f40
 8004ce4:	4b46      	ldr	r3, [pc, #280]	; (8004e00 <HAL_RCC_OscConfig+0x27c>)
 8004ce6:	681b      	ldr	r3, [r3, #0]
 8004ce8:	fbb3 f3f2 	udiv	r3, r3, r2
 8004cec:	9301      	str	r3, [sp, #4]
  \brief   No Operation
  \details No Operation does nothing. This instruction can be used for code alignment purposes.
 */
__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
{
  __ASM volatile ("nop");
 8004cee:	bf00      	nop
  do 
  {
    __NOP();
  } 
  while (Delay --);
 8004cf0:	9b01      	ldr	r3, [sp, #4]
 8004cf2:	1e5a      	subs	r2, r3, #1
 8004cf4:	9201      	str	r2, [sp, #4]
 8004cf6:	2b00      	cmp	r3, #0
 8004cf8:	d1f9      	bne.n	8004cee <HAL_RCC_OscConfig+0x16a>
 8004cfa:	e750      	b.n	8004b9e <HAL_RCC_OscConfig+0x1a>
        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
 8004cfc:	f7ff fad4 	bl	80042a8 <HAL_GetTick>
 8004d00:	1b80      	subs	r0, r0, r6
 8004d02:	2802      	cmp	r0, #2
 8004d04:	d9e9      	bls.n	8004cda <HAL_RCC_OscConfig+0x156>
 8004d06:	e77f      	b.n	8004c08 <HAL_RCC_OscConfig+0x84>
      __HAL_RCC_LSI_DISABLE();
 8004d08:	601a      	str	r2, [r3, #0]
      tickstart = HAL_GetTick();
 8004d0a:	f7ff facd 	bl	80042a8 <HAL_GetTick>
 8004d0e:	4606      	mov	r6, r0
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
 8004d10:	6a63      	ldr	r3, [r4, #36]	; 0x24
 8004d12:	079f      	lsls	r7, r3, #30
 8004d14:	f57f af43 	bpl.w	8004b9e <HAL_RCC_OscConfig+0x1a>
        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
 8004d18:	f7ff fac6 	bl	80042a8 <HAL_GetTick>
 8004d1c:	1b80      	subs	r0, r0, r6
 8004d1e:	2802      	cmp	r0, #2
 8004d20:	d9f6      	bls.n	8004d10 <HAL_RCC_OscConfig+0x18c>
 8004d22:	e771      	b.n	8004c08 <HAL_RCC_OscConfig+0x84>
    if(__HAL_RCC_PWR_IS_CLK_DISABLED())
 8004d24:	4c33      	ldr	r4, [pc, #204]	; (8004df4 <HAL_RCC_OscConfig+0x270>)
 8004d26:	69e3      	ldr	r3, [r4, #28]
 8004d28:	00d8      	lsls	r0, r3, #3
 8004d2a:	d424      	bmi.n	8004d76 <HAL_RCC_OscConfig+0x1f2>
      pwrclkchanged = SET;
 8004d2c:	2701      	movs	r7, #1
      __HAL_RCC_PWR_CLK_ENABLE();
 8004d2e:	69e3      	ldr	r3, [r4, #28]
 8004d30:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
 8004d34:	61e3      	str	r3, [r4, #28]
 8004d36:	69e3      	ldr	r3, [r4, #28]
 8004d38:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8004d3c:	9300      	str	r3, [sp, #0]
 8004d3e:	9b00      	ldr	r3, [sp, #0]
    if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 8004d40:	4e30      	ldr	r6, [pc, #192]	; (8004e04 <HAL_RCC_OscConfig+0x280>)
 8004d42:	6833      	ldr	r3, [r6, #0]
 8004d44:	05d9      	lsls	r1, r3, #23
 8004d46:	d518      	bpl.n	8004d7a <HAL_RCC_OscConfig+0x1f6>
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 8004d48:	68eb      	ldr	r3, [r5, #12]
 8004d4a:	2b01      	cmp	r3, #1
 8004d4c:	d126      	bne.n	8004d9c <HAL_RCC_OscConfig+0x218>
 8004d4e:	6a23      	ldr	r3, [r4, #32]
 8004d50:	f043 0301 	orr.w	r3, r3, #1
 8004d54:	6223      	str	r3, [r4, #32]
      tickstart = HAL_GetTick();
 8004d56:	f7ff faa7 	bl	80042a8 <HAL_GetTick>
        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
 8004d5a:	f241 3688 	movw	r6, #5000	; 0x1388
      tickstart = HAL_GetTick();
 8004d5e:	4680      	mov	r8, r0
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
 8004d60:	6a23      	ldr	r3, [r4, #32]
 8004d62:	079b      	lsls	r3, r3, #30
 8004d64:	d53f      	bpl.n	8004de6 <HAL_RCC_OscConfig+0x262>
    if(pwrclkchanged == SET)
 8004d66:	2f00      	cmp	r7, #0
 8004d68:	f43f af1d 	beq.w	8004ba6 <HAL_RCC_OscConfig+0x22>
      __HAL_RCC_PWR_CLK_DISABLE();
 8004d6c:	69e3      	ldr	r3, [r4, #28]
 8004d6e:	f023 5380 	bic.w	r3, r3, #268435456	; 0x10000000
 8004d72:	61e3      	str	r3, [r4, #28]
 8004d74:	e717      	b.n	8004ba6 <HAL_RCC_OscConfig+0x22>
    FlagStatus       pwrclkchanged = RESET;
 8004d76:	2700      	movs	r7, #0
 8004d78:	e7e2      	b.n	8004d40 <HAL_RCC_OscConfig+0x1bc>
      SET_BIT(PWR->CR, PWR_CR_DBP);
 8004d7a:	6833      	ldr	r3, [r6, #0]
 8004d7c:	f443 7380 	orr.w	r3, r3, #256	; 0x100
 8004d80:	6033      	str	r3, [r6, #0]
      tickstart = HAL_GetTick();
 8004d82:	f7ff fa91 	bl	80042a8 <HAL_GetTick>
 8004d86:	4680      	mov	r8, r0
      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 8004d88:	6833      	ldr	r3, [r6, #0]
 8004d8a:	05da      	lsls	r2, r3, #23
 8004d8c:	d4dc      	bmi.n	8004d48 <HAL_RCC_OscConfig+0x1c4>
        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
 8004d8e:	f7ff fa8b 	bl	80042a8 <HAL_GetTick>
 8004d92:	eba0 0008 	sub.w	r0, r0, r8
 8004d96:	2864      	cmp	r0, #100	; 0x64
 8004d98:	d9f6      	bls.n	8004d88 <HAL_RCC_OscConfig+0x204>
 8004d9a:	e735      	b.n	8004c08 <HAL_RCC_OscConfig+0x84>
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 8004d9c:	b9ab      	cbnz	r3, 8004dca <HAL_RCC_OscConfig+0x246>
 8004d9e:	6a23      	ldr	r3, [r4, #32]
        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
 8004da0:	f241 3888 	movw	r8, #5000	; 0x1388
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 8004da4:	f023 0301 	bic.w	r3, r3, #1
 8004da8:	6223      	str	r3, [r4, #32]
 8004daa:	6a23      	ldr	r3, [r4, #32]
 8004dac:	f023 0304 	bic.w	r3, r3, #4
 8004db0:	6223      	str	r3, [r4, #32]
      tickstart = HAL_GetTick();
 8004db2:	f7ff fa79 	bl	80042a8 <HAL_GetTick>
 8004db6:	4606      	mov	r6, r0
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
 8004db8:	6a23      	ldr	r3, [r4, #32]
 8004dba:	0798      	lsls	r0, r3, #30
 8004dbc:	d5d3      	bpl.n	8004d66 <HAL_RCC_OscConfig+0x1e2>
        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
 8004dbe:	f7ff fa73 	bl	80042a8 <HAL_GetTick>
 8004dc2:	1b80      	subs	r0, r0, r6
 8004dc4:	4540      	cmp	r0, r8
 8004dc6:	d9f7      	bls.n	8004db8 <HAL_RCC_OscConfig+0x234>
 8004dc8:	e71e      	b.n	8004c08 <HAL_RCC_OscConfig+0x84>
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 8004dca:	2b05      	cmp	r3, #5
 8004dcc:	6a23      	ldr	r3, [r4, #32]
 8004dce:	d103      	bne.n	8004dd8 <HAL_RCC_OscConfig+0x254>
 8004dd0:	f043 0304 	orr.w	r3, r3, #4
 8004dd4:	6223      	str	r3, [r4, #32]
 8004dd6:	e7ba      	b.n	8004d4e <HAL_RCC_OscConfig+0x1ca>
 8004dd8:	f023 0301 	bic.w	r3, r3, #1
 8004ddc:	6223      	str	r3, [r4, #32]
 8004dde:	6a23      	ldr	r3, [r4, #32]
 8004de0:	f023 0304 	bic.w	r3, r3, #4
 8004de4:	e7b6      	b.n	8004d54 <HAL_RCC_OscConfig+0x1d0>
        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
 8004de6:	f7ff fa5f 	bl	80042a8 <HAL_GetTick>
 8004dea:	eba0 0008 	sub.w	r0, r0, r8
 8004dee:	42b0      	cmp	r0, r6
 8004df0:	d9b6      	bls.n	8004d60 <HAL_RCC_OscConfig+0x1dc>
 8004df2:	e709      	b.n	8004c08 <HAL_RCC_OscConfig+0x84>
 8004df4:	40021000 	.word	0x40021000
 8004df8:	42420000 	.word	0x42420000
 8004dfc:	42420480 	.word	0x42420480
 8004e00:	20000008 	.word	0x20000008
 8004e04:	40007000 	.word	0x40007000
    if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
 8004e08:	4c22      	ldr	r4, [pc, #136]	; (8004e94 <HAL_RCC_OscConfig+0x310>)
 8004e0a:	6863      	ldr	r3, [r4, #4]
 8004e0c:	f003 030c 	and.w	r3, r3, #12
 8004e10:	2b08      	cmp	r3, #8
 8004e12:	f43f aee2 	beq.w	8004bda <HAL_RCC_OscConfig+0x56>
 8004e16:	2300      	movs	r3, #0
 8004e18:	4e1f      	ldr	r6, [pc, #124]	; (8004e98 <HAL_RCC_OscConfig+0x314>)
      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
 8004e1a:	2a02      	cmp	r2, #2
        __HAL_RCC_PLL_DISABLE();
 8004e1c:	6033      	str	r3, [r6, #0]
      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
 8004e1e:	d12b      	bne.n	8004e78 <HAL_RCC_OscConfig+0x2f4>
        tickstart = HAL_GetTick();
 8004e20:	f7ff fa42 	bl	80042a8 <HAL_GetTick>
 8004e24:	4607      	mov	r7, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
 8004e26:	6823      	ldr	r3, [r4, #0]
 8004e28:	0199      	lsls	r1, r3, #6
 8004e2a:	d41f      	bmi.n	8004e6c <HAL_RCC_OscConfig+0x2e8>
        if(RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
 8004e2c:	6a2b      	ldr	r3, [r5, #32]
 8004e2e:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
 8004e32:	d105      	bne.n	8004e40 <HAL_RCC_OscConfig+0x2bc>
          __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
 8004e34:	6862      	ldr	r2, [r4, #4]
 8004e36:	68a9      	ldr	r1, [r5, #8]
 8004e38:	f422 3200 	bic.w	r2, r2, #131072	; 0x20000
 8004e3c:	430a      	orrs	r2, r1
 8004e3e:	6062      	str	r2, [r4, #4]
        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
 8004e40:	6a69      	ldr	r1, [r5, #36]	; 0x24
 8004e42:	6862      	ldr	r2, [r4, #4]
 8004e44:	430b      	orrs	r3, r1
 8004e46:	f422 1274 	bic.w	r2, r2, #3997696	; 0x3d0000
 8004e4a:	4313      	orrs	r3, r2
 8004e4c:	6063      	str	r3, [r4, #4]
        __HAL_RCC_PLL_ENABLE();
 8004e4e:	2301      	movs	r3, #1
 8004e50:	6033      	str	r3, [r6, #0]
        tickstart = HAL_GetTick();
 8004e52:	f7ff fa29 	bl	80042a8 <HAL_GetTick>
 8004e56:	4605      	mov	r5, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  == RESET)
 8004e58:	6823      	ldr	r3, [r4, #0]
 8004e5a:	019a      	lsls	r2, r3, #6
 8004e5c:	f53f aea7 	bmi.w	8004bae <HAL_RCC_OscConfig+0x2a>
          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
 8004e60:	f7ff fa22 	bl	80042a8 <HAL_GetTick>
 8004e64:	1b40      	subs	r0, r0, r5
 8004e66:	2802      	cmp	r0, #2
 8004e68:	d9f6      	bls.n	8004e58 <HAL_RCC_OscConfig+0x2d4>
 8004e6a:	e6cd      	b.n	8004c08 <HAL_RCC_OscConfig+0x84>
          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
 8004e6c:	f7ff fa1c 	bl	80042a8 <HAL_GetTick>
 8004e70:	1bc0      	subs	r0, r0, r7
 8004e72:	2802      	cmp	r0, #2
 8004e74:	d9d7      	bls.n	8004e26 <HAL_RCC_OscConfig+0x2a2>
 8004e76:	e6c7      	b.n	8004c08 <HAL_RCC_OscConfig+0x84>
        tickstart = HAL_GetTick();
 8004e78:	f7ff fa16 	bl	80042a8 <HAL_GetTick>
 8004e7c:	4605      	mov	r5, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
 8004e7e:	6823      	ldr	r3, [r4, #0]
 8004e80:	019b      	lsls	r3, r3, #6
 8004e82:	f57f ae94 	bpl.w	8004bae <HAL_RCC_OscConfig+0x2a>
          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
 8004e86:	f7ff fa0f 	bl	80042a8 <HAL_GetTick>
 8004e8a:	1b40      	subs	r0, r0, r5
 8004e8c:	2802      	cmp	r0, #2
 8004e8e:	d9f6      	bls.n	8004e7e <HAL_RCC_OscConfig+0x2fa>
 8004e90:	e6ba      	b.n	8004c08 <HAL_RCC_OscConfig+0x84>
 8004e92:	bf00      	nop
 8004e94:	40021000 	.word	0x40021000
 8004e98:	42420060 	.word	0x42420060

08004e9c <HAL_RCC_GetSysClockFreq>:
{
 8004e9c:	b530      	push	{r4, r5, lr}
  const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
 8004e9e:	4b19      	ldr	r3, [pc, #100]	; (8004f04 <HAL_RCC_GetSysClockFreq+0x68>)
{
 8004ea0:	b087      	sub	sp, #28
  const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
 8004ea2:	ac02      	add	r4, sp, #8
 8004ea4:	f103 0510 	add.w	r5, r3, #16
 8004ea8:	4622      	mov	r2, r4
 8004eaa:	6818      	ldr	r0, [r3, #0]
 8004eac:	6859      	ldr	r1, [r3, #4]
 8004eae:	3308      	adds	r3, #8
 8004eb0:	c203      	stmia	r2!, {r0, r1}
 8004eb2:	42ab      	cmp	r3, r5
 8004eb4:	4614      	mov	r4, r2
 8004eb6:	d1f7      	bne.n	8004ea8 <HAL_RCC_GetSysClockFreq+0xc>
  const uint8_t aPredivFactorTable[2] = {1, 2};
 8004eb8:	2301      	movs	r3, #1
 8004eba:	f88d 3004 	strb.w	r3, [sp, #4]
 8004ebe:	2302      	movs	r3, #2
  tmpreg = RCC->CFGR;
 8004ec0:	4911      	ldr	r1, [pc, #68]	; (8004f08 <HAL_RCC_GetSysClockFreq+0x6c>)
  const uint8_t aPredivFactorTable[2] = {1, 2};
 8004ec2:	f88d 3005 	strb.w	r3, [sp, #5]
  tmpreg = RCC->CFGR;
 8004ec6:	684b      	ldr	r3, [r1, #4]
  switch (tmpreg & RCC_CFGR_SWS)
 8004ec8:	f003 020c 	and.w	r2, r3, #12
 8004ecc:	2a08      	cmp	r2, #8
 8004ece:	d117      	bne.n	8004f00 <HAL_RCC_GetSysClockFreq+0x64>
      pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
 8004ed0:	f3c3 4283 	ubfx	r2, r3, #18, #4
 8004ed4:	a806      	add	r0, sp, #24
 8004ed6:	4402      	add	r2, r0
      if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
 8004ed8:	03db      	lsls	r3, r3, #15
      pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
 8004eda:	f812 2c10 	ldrb.w	r2, [r2, #-16]
      if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
 8004ede:	d50c      	bpl.n	8004efa <HAL_RCC_GetSysClockFreq+0x5e>
        prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
 8004ee0:	684b      	ldr	r3, [r1, #4]
        pllclk = (uint32_t)((HSE_VALUE  * pllmul) / prediv);
 8004ee2:	480a      	ldr	r0, [pc, #40]	; (8004f0c <HAL_RCC_GetSysClockFreq+0x70>)
        prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
 8004ee4:	f3c3 4340 	ubfx	r3, r3, #17, #1
        pllclk = (uint32_t)((HSE_VALUE  * pllmul) / prediv);
 8004ee8:	4350      	muls	r0, r2
        prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
 8004eea:	aa06      	add	r2, sp, #24
 8004eec:	4413      	add	r3, r2
 8004eee:	f813 3c14 	ldrb.w	r3, [r3, #-20]
        pllclk = (uint32_t)((HSE_VALUE  * pllmul) / prediv);
 8004ef2:	fbb0 f0f3 	udiv	r0, r0, r3
}
 8004ef6:	b007      	add	sp, #28
 8004ef8:	bd30      	pop	{r4, r5, pc}
        pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
 8004efa:	4805      	ldr	r0, [pc, #20]	; (8004f10 <HAL_RCC_GetSysClockFreq+0x74>)
 8004efc:	4350      	muls	r0, r2
 8004efe:	e7fa      	b.n	8004ef6 <HAL_RCC_GetSysClockFreq+0x5a>
      sysclockfreq = HSE_VALUE;
 8004f00:	4802      	ldr	r0, [pc, #8]	; (8004f0c <HAL_RCC_GetSysClockFreq+0x70>)
  return sysclockfreq;
 8004f02:	e7f8      	b.n	8004ef6 <HAL_RCC_GetSysClockFreq+0x5a>
 8004f04:	080074e0 	.word	0x080074e0
 8004f08:	40021000 	.word	0x40021000
 8004f0c:	007a1200 	.word	0x007a1200
 8004f10:	003d0900 	.word	0x003d0900

08004f14 <HAL_RCC_ClockConfig>:
  if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
 8004f14:	4a54      	ldr	r2, [pc, #336]	; (8005068 <HAL_RCC_ClockConfig+0x154>)
{
 8004f16:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
  if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
 8004f1a:	6813      	ldr	r3, [r2, #0]
{
 8004f1c:	4605      	mov	r5, r0
  if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
 8004f1e:	f003 0307 	and.w	r3, r3, #7
 8004f22:	428b      	cmp	r3, r1
{
 8004f24:	460e      	mov	r6, r1
  if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
 8004f26:	d32a      	bcc.n	8004f7e <HAL_RCC_ClockConfig+0x6a>
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
 8004f28:	6829      	ldr	r1, [r5, #0]
 8004f2a:	078c      	lsls	r4, r1, #30
 8004f2c:	d434      	bmi.n	8004f98 <HAL_RCC_ClockConfig+0x84>
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
 8004f2e:	07ca      	lsls	r2, r1, #31
 8004f30:	d447      	bmi.n	8004fc2 <HAL_RCC_ClockConfig+0xae>
  if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
 8004f32:	4a4d      	ldr	r2, [pc, #308]	; (8005068 <HAL_RCC_ClockConfig+0x154>)
 8004f34:	6813      	ldr	r3, [r2, #0]
 8004f36:	f003 0307 	and.w	r3, r3, #7
 8004f3a:	429e      	cmp	r6, r3
 8004f3c:	f0c0 8082 	bcc.w	8005044 <HAL_RCC_ClockConfig+0x130>
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 8004f40:	682a      	ldr	r2, [r5, #0]
 8004f42:	4c4a      	ldr	r4, [pc, #296]	; (800506c <HAL_RCC_ClockConfig+0x158>)
 8004f44:	f012 0f04 	tst.w	r2, #4
 8004f48:	f040 8087 	bne.w	800505a <HAL_RCC_ClockConfig+0x146>
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
 8004f4c:	0713      	lsls	r3, r2, #28
 8004f4e:	d506      	bpl.n	8004f5e <HAL_RCC_ClockConfig+0x4a>
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
 8004f50:	6863      	ldr	r3, [r4, #4]
 8004f52:	692a      	ldr	r2, [r5, #16]
 8004f54:	f423 5360 	bic.w	r3, r3, #14336	; 0x3800
 8004f58:	ea43 03c2 	orr.w	r3, r3, r2, lsl #3
 8004f5c:	6063      	str	r3, [r4, #4]
  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
 8004f5e:	f7ff ff9d 	bl	8004e9c <HAL_RCC_GetSysClockFreq>
 8004f62:	6863      	ldr	r3, [r4, #4]
 8004f64:	4a42      	ldr	r2, [pc, #264]	; (8005070 <HAL_RCC_ClockConfig+0x15c>)
 8004f66:	f3c3 1303 	ubfx	r3, r3, #4, #4
 8004f6a:	5cd3      	ldrb	r3, [r2, r3]
 8004f6c:	40d8      	lsrs	r0, r3
 8004f6e:	4b41      	ldr	r3, [pc, #260]	; (8005074 <HAL_RCC_ClockConfig+0x160>)
 8004f70:	6018      	str	r0, [r3, #0]
  HAL_InitTick (TICK_INT_PRIORITY);
 8004f72:	2000      	movs	r0, #0
 8004f74:	f7ff f956 	bl	8004224 <HAL_InitTick>
  return HAL_OK;
 8004f78:	2000      	movs	r0, #0
}
 8004f7a:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    __HAL_FLASH_SET_LATENCY(FLatency);
 8004f7e:	6813      	ldr	r3, [r2, #0]
 8004f80:	f023 0307 	bic.w	r3, r3, #7
 8004f84:	430b      	orrs	r3, r1
 8004f86:	6013      	str	r3, [r2, #0]
    if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
 8004f88:	6813      	ldr	r3, [r2, #0]
 8004f8a:	f003 0307 	and.w	r3, r3, #7
 8004f8e:	4299      	cmp	r1, r3
 8004f90:	d0ca      	beq.n	8004f28 <HAL_RCC_ClockConfig+0x14>
      return HAL_ERROR;
 8004f92:	2001      	movs	r0, #1
 8004f94:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
 8004f98:	4b34      	ldr	r3, [pc, #208]	; (800506c <HAL_RCC_ClockConfig+0x158>)
    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 8004f9a:	f011 0f04 	tst.w	r1, #4
      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
 8004f9e:	bf1e      	ittt	ne
 8004fa0:	685a      	ldrne	r2, [r3, #4]
 8004fa2:	f442 62e0 	orrne.w	r2, r2, #1792	; 0x700
 8004fa6:	605a      	strne	r2, [r3, #4]
    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
 8004fa8:	0708      	lsls	r0, r1, #28
      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
 8004faa:	bf42      	ittt	mi
 8004fac:	685a      	ldrmi	r2, [r3, #4]
 8004fae:	f442 5260 	orrmi.w	r2, r2, #14336	; 0x3800
 8004fb2:	605a      	strmi	r2, [r3, #4]
    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
 8004fb4:	685a      	ldr	r2, [r3, #4]
 8004fb6:	68a8      	ldr	r0, [r5, #8]
 8004fb8:	f022 02f0 	bic.w	r2, r2, #240	; 0xf0
 8004fbc:	4302      	orrs	r2, r0
 8004fbe:	605a      	str	r2, [r3, #4]
 8004fc0:	e7b5      	b.n	8004f2e <HAL_RCC_ClockConfig+0x1a>
    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 8004fc2:	686a      	ldr	r2, [r5, #4]
 8004fc4:	4c29      	ldr	r4, [pc, #164]	; (800506c <HAL_RCC_ClockConfig+0x158>)
 8004fc6:	2a01      	cmp	r2, #1
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 8004fc8:	6823      	ldr	r3, [r4, #0]
    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 8004fca:	d11c      	bne.n	8005006 <HAL_RCC_ClockConfig+0xf2>
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 8004fcc:	f413 3f00 	tst.w	r3, #131072	; 0x20000
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 8004fd0:	d0df      	beq.n	8004f92 <HAL_RCC_ClockConfig+0x7e>
    __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
 8004fd2:	6863      	ldr	r3, [r4, #4]
        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
 8004fd4:	f241 3888 	movw	r8, #5000	; 0x1388
    __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
 8004fd8:	f023 0303 	bic.w	r3, r3, #3
 8004fdc:	4313      	orrs	r3, r2
 8004fde:	6063      	str	r3, [r4, #4]
    tickstart = HAL_GetTick();
 8004fe0:	f7ff f962 	bl	80042a8 <HAL_GetTick>
    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 8004fe4:	686b      	ldr	r3, [r5, #4]
    tickstart = HAL_GetTick();
 8004fe6:	4607      	mov	r7, r0
    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 8004fe8:	2b01      	cmp	r3, #1
 8004fea:	d114      	bne.n	8005016 <HAL_RCC_ClockConfig+0x102>
      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
 8004fec:	6863      	ldr	r3, [r4, #4]
 8004fee:	f003 030c 	and.w	r3, r3, #12
 8004ff2:	2b04      	cmp	r3, #4
 8004ff4:	d09d      	beq.n	8004f32 <HAL_RCC_ClockConfig+0x1e>
        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
 8004ff6:	f7ff f957 	bl	80042a8 <HAL_GetTick>
 8004ffa:	1bc0      	subs	r0, r0, r7
 8004ffc:	4540      	cmp	r0, r8
 8004ffe:	d9f5      	bls.n	8004fec <HAL_RCC_ClockConfig+0xd8>
          return HAL_TIMEOUT;
 8005000:	2003      	movs	r0, #3
 8005002:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
 8005006:	2a02      	cmp	r2, #2
 8005008:	d102      	bne.n	8005010 <HAL_RCC_ClockConfig+0xfc>
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
 800500a:	f013 7f00 	tst.w	r3, #33554432	; 0x2000000
 800500e:	e7df      	b.n	8004fd0 <HAL_RCC_ClockConfig+0xbc>
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 8005010:	f013 0f02 	tst.w	r3, #2
 8005014:	e7dc      	b.n	8004fd0 <HAL_RCC_ClockConfig+0xbc>
    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
 8005016:	2b02      	cmp	r3, #2
 8005018:	d10f      	bne.n	800503a <HAL_RCC_ClockConfig+0x126>
      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
 800501a:	6863      	ldr	r3, [r4, #4]
 800501c:	f003 030c 	and.w	r3, r3, #12
 8005020:	2b08      	cmp	r3, #8
 8005022:	d086      	beq.n	8004f32 <HAL_RCC_ClockConfig+0x1e>
        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
 8005024:	f7ff f940 	bl	80042a8 <HAL_GetTick>
 8005028:	1bc0      	subs	r0, r0, r7
 800502a:	4540      	cmp	r0, r8
 800502c:	d9f5      	bls.n	800501a <HAL_RCC_ClockConfig+0x106>
 800502e:	e7e7      	b.n	8005000 <HAL_RCC_ClockConfig+0xec>
        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
 8005030:	f7ff f93a 	bl	80042a8 <HAL_GetTick>
 8005034:	1bc0      	subs	r0, r0, r7
 8005036:	4540      	cmp	r0, r8
 8005038:	d8e2      	bhi.n	8005000 <HAL_RCC_ClockConfig+0xec>
      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
 800503a:	6863      	ldr	r3, [r4, #4]
 800503c:	f013 0f0c 	tst.w	r3, #12
 8005040:	d1f6      	bne.n	8005030 <HAL_RCC_ClockConfig+0x11c>
 8005042:	e776      	b.n	8004f32 <HAL_RCC_ClockConfig+0x1e>
    __HAL_FLASH_SET_LATENCY(FLatency);
 8005044:	6813      	ldr	r3, [r2, #0]
 8005046:	f023 0307 	bic.w	r3, r3, #7
 800504a:	4333      	orrs	r3, r6
 800504c:	6013      	str	r3, [r2, #0]
    if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
 800504e:	6813      	ldr	r3, [r2, #0]
 8005050:	f003 0307 	and.w	r3, r3, #7
 8005054:	429e      	cmp	r6, r3
 8005056:	d19c      	bne.n	8004f92 <HAL_RCC_ClockConfig+0x7e>
 8005058:	e772      	b.n	8004f40 <HAL_RCC_ClockConfig+0x2c>
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
 800505a:	6863      	ldr	r3, [r4, #4]
 800505c:	68e9      	ldr	r1, [r5, #12]
 800505e:	f423 63e0 	bic.w	r3, r3, #1792	; 0x700
 8005062:	430b      	orrs	r3, r1
 8005064:	6063      	str	r3, [r4, #4]
 8005066:	e771      	b.n	8004f4c <HAL_RCC_ClockConfig+0x38>
 8005068:	40022000 	.word	0x40022000
 800506c:	40021000 	.word	0x40021000
 8005070:	080074fd 	.word	0x080074fd
 8005074:	20000008 	.word	0x20000008

08005078 <HAL_RCC_GetPCLK1Freq>:
  return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
 8005078:	4b04      	ldr	r3, [pc, #16]	; (800508c <HAL_RCC_GetPCLK1Freq+0x14>)
 800507a:	4a05      	ldr	r2, [pc, #20]	; (8005090 <HAL_RCC_GetPCLK1Freq+0x18>)
 800507c:	685b      	ldr	r3, [r3, #4]
 800507e:	f3c3 2302 	ubfx	r3, r3, #8, #3
 8005082:	5cd3      	ldrb	r3, [r2, r3]
 8005084:	4a03      	ldr	r2, [pc, #12]	; (8005094 <HAL_RCC_GetPCLK1Freq+0x1c>)
 8005086:	6810      	ldr	r0, [r2, #0]
}    
 8005088:	40d8      	lsrs	r0, r3
 800508a:	4770      	bx	lr
 800508c:	40021000 	.word	0x40021000
 8005090:	0800750d 	.word	0x0800750d
 8005094:	20000008 	.word	0x20000008

08005098 <HAL_RCC_GetPCLK2Freq>:
  return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
 8005098:	4b04      	ldr	r3, [pc, #16]	; (80050ac <HAL_RCC_GetPCLK2Freq+0x14>)
 800509a:	4a05      	ldr	r2, [pc, #20]	; (80050b0 <HAL_RCC_GetPCLK2Freq+0x18>)
 800509c:	685b      	ldr	r3, [r3, #4]
 800509e:	f3c3 23c2 	ubfx	r3, r3, #11, #3
 80050a2:	5cd3      	ldrb	r3, [r2, r3]
 80050a4:	4a03      	ldr	r2, [pc, #12]	; (80050b4 <HAL_RCC_GetPCLK2Freq+0x1c>)
 80050a6:	6810      	ldr	r0, [r2, #0]
} 
 80050a8:	40d8      	lsrs	r0, r3
 80050aa:	4770      	bx	lr
 80050ac:	40021000 	.word	0x40021000
 80050b0:	0800750d 	.word	0x0800750d
 80050b4:	20000008 	.word	0x20000008

080050b8 <HAL_RCCEx_PeriphCLKConfig>:

  /* Check the parameters */
  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
  
  /*------------------------------- RTC/LCD Configuration ------------------------*/ 
  if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
 80050b8:	6803      	ldr	r3, [r0, #0]
{
 80050ba:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
  if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
 80050be:	07d9      	lsls	r1, r3, #31
{
 80050c0:	4605      	mov	r5, r0
  if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
 80050c2:	d520      	bpl.n	8005106 <HAL_RCCEx_PeriphCLKConfig+0x4e>
    FlagStatus       pwrclkchanged = RESET;

    /* As soon as function is called to change RTC clock source, activation of the 
       power domain is done. */
    /* Requires to enable write access to Backup Domain of necessary */
    if(__HAL_RCC_PWR_IS_CLK_DISABLED())
 80050c4:	4c35      	ldr	r4, [pc, #212]	; (800519c <HAL_RCCEx_PeriphCLKConfig+0xe4>)
 80050c6:	69e3      	ldr	r3, [r4, #28]
 80050c8:	00da      	lsls	r2, r3, #3
 80050ca:	d432      	bmi.n	8005132 <HAL_RCCEx_PeriphCLKConfig+0x7a>
    {
    __HAL_RCC_PWR_CLK_ENABLE();
      pwrclkchanged = SET;
 80050cc:	2701      	movs	r7, #1
    __HAL_RCC_PWR_CLK_ENABLE();
 80050ce:	69e3      	ldr	r3, [r4, #28]
 80050d0:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
 80050d4:	61e3      	str	r3, [r4, #28]
 80050d6:	69e3      	ldr	r3, [r4, #28]
 80050d8:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 80050dc:	9301      	str	r3, [sp, #4]
 80050de:	9b01      	ldr	r3, [sp, #4]
    }
    
    if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 80050e0:	4e2f      	ldr	r6, [pc, #188]	; (80051a0 <HAL_RCCEx_PeriphCLKConfig+0xe8>)
 80050e2:	6833      	ldr	r3, [r6, #0]
 80050e4:	05db      	lsls	r3, r3, #23
 80050e6:	d526      	bpl.n	8005136 <HAL_RCCEx_PeriphCLKConfig+0x7e>
        }
      }
    }
      
    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ 
    temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
 80050e8:	6a23      	ldr	r3, [r4, #32]
    if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
 80050ea:	f413 7340 	ands.w	r3, r3, #768	; 0x300
 80050ee:	d136      	bne.n	800515e <HAL_RCCEx_PeriphCLKConfig+0xa6>
            return HAL_TIMEOUT;
          }      
        }  
      }
    }
    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 
 80050f0:	6a23      	ldr	r3, [r4, #32]
 80050f2:	686a      	ldr	r2, [r5, #4]
 80050f4:	f423 7340 	bic.w	r3, r3, #768	; 0x300
 80050f8:	4313      	orrs	r3, r2
 80050fa:	6223      	str	r3, [r4, #32]

    /* Require to disable power clock if necessary */
    if(pwrclkchanged == SET)
 80050fc:	b11f      	cbz	r7, 8005106 <HAL_RCCEx_PeriphCLKConfig+0x4e>
    {
      __HAL_RCC_PWR_CLK_DISABLE();
 80050fe:	69e3      	ldr	r3, [r4, #28]
 8005100:	f023 5380 	bic.w	r3, r3, #268435456	; 0x10000000
 8005104:	61e3      	str	r3, [r4, #28]
    }
  }

  /*------------------------------ ADC clock Configuration ------------------*/ 
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
 8005106:	6828      	ldr	r0, [r5, #0]
 8005108:	0783      	lsls	r3, r0, #30
 800510a:	d506      	bpl.n	800511a <HAL_RCCEx_PeriphCLKConfig+0x62>
  {
    /* Check the parameters */
    assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection));
    
    /* Configure the ADC clock source */
    __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
 800510c:	4a23      	ldr	r2, [pc, #140]	; (800519c <HAL_RCCEx_PeriphCLKConfig+0xe4>)
 800510e:	68a9      	ldr	r1, [r5, #8]
 8005110:	6853      	ldr	r3, [r2, #4]
 8005112:	f423 4340 	bic.w	r3, r3, #49152	; 0xc000
 8005116:	430b      	orrs	r3, r1
 8005118:	6053      	str	r3, [r2, #4]

#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
 || defined(STM32F105xC) || defined(STM32F107xC)
  /*------------------------------ USB clock Configuration ------------------*/ 
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
 800511a:	f010 0010 	ands.w	r0, r0, #16
 800511e:	d01b      	beq.n	8005158 <HAL_RCCEx_PeriphCLKConfig+0xa0>
  {
    /* Check the parameters */
    assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection));
    
    /* Configure the USB clock source */
    __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
 8005120:	4a1e      	ldr	r2, [pc, #120]	; (800519c <HAL_RCCEx_PeriphCLKConfig+0xe4>)
 8005122:	6969      	ldr	r1, [r5, #20]
 8005124:	6853      	ldr	r3, [r2, #4]
  }
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */

  return HAL_OK;
 8005126:	2000      	movs	r0, #0
    __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
 8005128:	f423 0380 	bic.w	r3, r3, #4194304	; 0x400000
 800512c:	430b      	orrs	r3, r1
 800512e:	6053      	str	r3, [r2, #4]
 8005130:	e012      	b.n	8005158 <HAL_RCCEx_PeriphCLKConfig+0xa0>
    FlagStatus       pwrclkchanged = RESET;
 8005132:	2700      	movs	r7, #0
 8005134:	e7d4      	b.n	80050e0 <HAL_RCCEx_PeriphCLKConfig+0x28>
      SET_BIT(PWR->CR, PWR_CR_DBP);
 8005136:	6833      	ldr	r3, [r6, #0]
 8005138:	f443 7380 	orr.w	r3, r3, #256	; 0x100
 800513c:	6033      	str	r3, [r6, #0]
      tickstart = HAL_GetTick();
 800513e:	f7ff f8b3 	bl	80042a8 <HAL_GetTick>
 8005142:	4680      	mov	r8, r0
      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 8005144:	6833      	ldr	r3, [r6, #0]
 8005146:	05d8      	lsls	r0, r3, #23
 8005148:	d4ce      	bmi.n	80050e8 <HAL_RCCEx_PeriphCLKConfig+0x30>
        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
 800514a:	f7ff f8ad 	bl	80042a8 <HAL_GetTick>
 800514e:	eba0 0008 	sub.w	r0, r0, r8
 8005152:	2864      	cmp	r0, #100	; 0x64
 8005154:	d9f6      	bls.n	8005144 <HAL_RCCEx_PeriphCLKConfig+0x8c>
          return HAL_TIMEOUT;
 8005156:	2003      	movs	r0, #3
}
 8005158:	b002      	add	sp, #8
 800515a:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
 800515e:	686a      	ldr	r2, [r5, #4]
 8005160:	f402 7240 	and.w	r2, r2, #768	; 0x300
 8005164:	4293      	cmp	r3, r2
 8005166:	d0c3      	beq.n	80050f0 <HAL_RCCEx_PeriphCLKConfig+0x38>
      __HAL_RCC_BACKUPRESET_FORCE();
 8005168:	2001      	movs	r0, #1
 800516a:	4a0e      	ldr	r2, [pc, #56]	; (80051a4 <HAL_RCCEx_PeriphCLKConfig+0xec>)
      temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
 800516c:	6a23      	ldr	r3, [r4, #32]
      __HAL_RCC_BACKUPRESET_FORCE();
 800516e:	6010      	str	r0, [r2, #0]
      __HAL_RCC_BACKUPRESET_RELEASE();
 8005170:	2000      	movs	r0, #0
      temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
 8005172:	f423 7140 	bic.w	r1, r3, #768	; 0x300
      __HAL_RCC_BACKUPRESET_RELEASE();
 8005176:	6010      	str	r0, [r2, #0]
      RCC->BDCR = temp_reg;
 8005178:	6221      	str	r1, [r4, #32]
      if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
 800517a:	07d9      	lsls	r1, r3, #31
 800517c:	d5b8      	bpl.n	80050f0 <HAL_RCCEx_PeriphCLKConfig+0x38>
        tickstart = HAL_GetTick();
 800517e:	f7ff f893 	bl	80042a8 <HAL_GetTick>
          if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 8005182:	f241 3888 	movw	r8, #5000	; 0x1388
        tickstart = HAL_GetTick();
 8005186:	4606      	mov	r6, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
 8005188:	6a23      	ldr	r3, [r4, #32]
 800518a:	079a      	lsls	r2, r3, #30
 800518c:	d4b0      	bmi.n	80050f0 <HAL_RCCEx_PeriphCLKConfig+0x38>
          if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 800518e:	f7ff f88b 	bl	80042a8 <HAL_GetTick>
 8005192:	1b80      	subs	r0, r0, r6
 8005194:	4540      	cmp	r0, r8
 8005196:	d9f7      	bls.n	8005188 <HAL_RCCEx_PeriphCLKConfig+0xd0>
 8005198:	e7dd      	b.n	8005156 <HAL_RCCEx_PeriphCLKConfig+0x9e>
 800519a:	bf00      	nop
 800519c:	40021000 	.word	0x40021000
 80051a0:	40007000 	.word	0x40007000
 80051a4:	42420440 	.word	0x42420440

080051a8 <HAL_TIM_OC_DelayElapsedCallback>:
 80051a8:	4770      	bx	lr

080051aa <HAL_TIM_IC_CaptureCallback>:
 80051aa:	4770      	bx	lr

080051ac <HAL_TIM_PWM_PulseFinishedCallback>:
 80051ac:	4770      	bx	lr

080051ae <HAL_TIM_TriggerCallback>:
 80051ae:	4770      	bx	lr

080051b0 <HAL_TIM_IRQHandler>:
  * @retval None
  */
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
  /* Capture compare 1 event */
  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
 80051b0:	6803      	ldr	r3, [r0, #0]
{
 80051b2:	b510      	push	{r4, lr}
  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
 80051b4:	691a      	ldr	r2, [r3, #16]
{
 80051b6:	4604      	mov	r4, r0
  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
 80051b8:	0791      	lsls	r1, r2, #30
 80051ba:	d50e      	bpl.n	80051da <HAL_TIM_IRQHandler+0x2a>
  {
    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
 80051bc:	68da      	ldr	r2, [r3, #12]
 80051be:	0792      	lsls	r2, r2, #30
 80051c0:	d50b      	bpl.n	80051da <HAL_TIM_IRQHandler+0x2a>
    {
      {
        __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
 80051c2:	f06f 0202 	mvn.w	r2, #2
 80051c6:	611a      	str	r2, [r3, #16]
        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
 80051c8:	2201      	movs	r2, #1

        /* Input capture event */
        if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
 80051ca:	699b      	ldr	r3, [r3, #24]
        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
 80051cc:	7702      	strb	r2, [r0, #28]
        if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
 80051ce:	079b      	lsls	r3, r3, #30
 80051d0:	d077      	beq.n	80052c2 <HAL_TIM_IRQHandler+0x112>
        {
          HAL_TIM_IC_CaptureCallback(htim);
 80051d2:	f7ff ffea 	bl	80051aa <HAL_TIM_IC_CaptureCallback>
        else
        {
          HAL_TIM_OC_DelayElapsedCallback(htim);
          HAL_TIM_PWM_PulseFinishedCallback(htim);
        }
        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 80051d6:	2300      	movs	r3, #0
 80051d8:	7723      	strb	r3, [r4, #28]
      }
    }
  }
  /* Capture compare 2 event */
  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
 80051da:	6823      	ldr	r3, [r4, #0]
 80051dc:	691a      	ldr	r2, [r3, #16]
 80051de:	0750      	lsls	r0, r2, #29
 80051e0:	d510      	bpl.n	8005204 <HAL_TIM_IRQHandler+0x54>
  {
    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
 80051e2:	68da      	ldr	r2, [r3, #12]
 80051e4:	0751      	lsls	r1, r2, #29
 80051e6:	d50d      	bpl.n	8005204 <HAL_TIM_IRQHandler+0x54>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
 80051e8:	f06f 0204 	mvn.w	r2, #4
 80051ec:	611a      	str	r2, [r3, #16]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
 80051ee:	2202      	movs	r2, #2
      /* Input capture event */
      if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
 80051f0:	699b      	ldr	r3, [r3, #24]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
 80051f2:	7722      	strb	r2, [r4, #28]
      if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
 80051f4:	f413 7f40 	tst.w	r3, #768	; 0x300
      {
        HAL_TIM_IC_CaptureCallback(htim);
 80051f8:	4620      	mov	r0, r4
      if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
 80051fa:	d068      	beq.n	80052ce <HAL_TIM_IRQHandler+0x11e>
        HAL_TIM_IC_CaptureCallback(htim);
 80051fc:	f7ff ffd5 	bl	80051aa <HAL_TIM_IC_CaptureCallback>
      else
      {
        HAL_TIM_OC_DelayElapsedCallback(htim);
        HAL_TIM_PWM_PulseFinishedCallback(htim);
      }
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 8005200:	2300      	movs	r3, #0
 8005202:	7723      	strb	r3, [r4, #28]
    }
  }
  /* Capture compare 3 event */
  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
 8005204:	6823      	ldr	r3, [r4, #0]
 8005206:	691a      	ldr	r2, [r3, #16]
 8005208:	0712      	lsls	r2, r2, #28
 800520a:	d50f      	bpl.n	800522c <HAL_TIM_IRQHandler+0x7c>
  {
    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
 800520c:	68da      	ldr	r2, [r3, #12]
 800520e:	0710      	lsls	r0, r2, #28
 8005210:	d50c      	bpl.n	800522c <HAL_TIM_IRQHandler+0x7c>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
 8005212:	f06f 0208 	mvn.w	r2, #8
 8005216:	611a      	str	r2, [r3, #16]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
 8005218:	2204      	movs	r2, #4
      /* Input capture event */
      if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
 800521a:	69db      	ldr	r3, [r3, #28]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
 800521c:	7722      	strb	r2, [r4, #28]
      if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
 800521e:	0799      	lsls	r1, r3, #30
      {
        HAL_TIM_IC_CaptureCallback(htim);
 8005220:	4620      	mov	r0, r4
      if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
 8005222:	d05a      	beq.n	80052da <HAL_TIM_IRQHandler+0x12a>
        HAL_TIM_IC_CaptureCallback(htim);
 8005224:	f7ff ffc1 	bl	80051aa <HAL_TIM_IC_CaptureCallback>
      else
      {
        HAL_TIM_OC_DelayElapsedCallback(htim);
        HAL_TIM_PWM_PulseFinishedCallback(htim);
      }
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 8005228:	2300      	movs	r3, #0
 800522a:	7723      	strb	r3, [r4, #28]
    }
  }
  /* Capture compare 4 event */
  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
 800522c:	6823      	ldr	r3, [r4, #0]
 800522e:	691a      	ldr	r2, [r3, #16]
 8005230:	06d2      	lsls	r2, r2, #27
 8005232:	d510      	bpl.n	8005256 <HAL_TIM_IRQHandler+0xa6>
  {
    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
 8005234:	68da      	ldr	r2, [r3, #12]
 8005236:	06d0      	lsls	r0, r2, #27
 8005238:	d50d      	bpl.n	8005256 <HAL_TIM_IRQHandler+0xa6>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
 800523a:	f06f 0210 	mvn.w	r2, #16
 800523e:	611a      	str	r2, [r3, #16]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
 8005240:	2208      	movs	r2, #8
      /* Input capture event */
      if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
 8005242:	69db      	ldr	r3, [r3, #28]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
 8005244:	7722      	strb	r2, [r4, #28]
      if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
 8005246:	f413 7f40 	tst.w	r3, #768	; 0x300
      {
        HAL_TIM_IC_CaptureCallback(htim);
 800524a:	4620      	mov	r0, r4
      if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
 800524c:	d04b      	beq.n	80052e6 <HAL_TIM_IRQHandler+0x136>
        HAL_TIM_IC_CaptureCallback(htim);
 800524e:	f7ff ffac 	bl	80051aa <HAL_TIM_IC_CaptureCallback>
      else
      {
        HAL_TIM_OC_DelayElapsedCallback(htim);
        HAL_TIM_PWM_PulseFinishedCallback(htim);
      }
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 8005252:	2300      	movs	r3, #0
 8005254:	7723      	strb	r3, [r4, #28]
    }
  }
  /* TIM Update event */
  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
 8005256:	6823      	ldr	r3, [r4, #0]
 8005258:	691a      	ldr	r2, [r3, #16]
 800525a:	07d1      	lsls	r1, r2, #31
 800525c:	d508      	bpl.n	8005270 <HAL_TIM_IRQHandler+0xc0>
  {
    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
 800525e:	68da      	ldr	r2, [r3, #12]
 8005260:	07d2      	lsls	r2, r2, #31
 8005262:	d505      	bpl.n	8005270 <HAL_TIM_IRQHandler+0xc0>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
 8005264:	f06f 0201 	mvn.w	r2, #1
      HAL_TIM_PeriodElapsedCallback(htim);
 8005268:	4620      	mov	r0, r4
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
 800526a:	611a      	str	r2, [r3, #16]
      HAL_TIM_PeriodElapsedCallback(htim);
 800526c:	f000 fbe0 	bl	8005a30 <HAL_TIM_PeriodElapsedCallback>
    }
  }
  /* TIM Break input event */
  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
 8005270:	6823      	ldr	r3, [r4, #0]
 8005272:	691a      	ldr	r2, [r3, #16]
 8005274:	0610      	lsls	r0, r2, #24
 8005276:	d508      	bpl.n	800528a <HAL_TIM_IRQHandler+0xda>
  {
    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
 8005278:	68da      	ldr	r2, [r3, #12]
 800527a:	0611      	lsls	r1, r2, #24
 800527c:	d505      	bpl.n	800528a <HAL_TIM_IRQHandler+0xda>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
 800527e:	f06f 0280 	mvn.w	r2, #128	; 0x80
      HAL_TIMEx_BreakCallback(htim);
 8005282:	4620      	mov	r0, r4
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
 8005284:	611a      	str	r2, [r3, #16]
      HAL_TIMEx_BreakCallback(htim);
 8005286:	f000 f8be 	bl	8005406 <HAL_TIMEx_BreakCallback>
    }
  }
  /* TIM Trigger detection event */
  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
 800528a:	6823      	ldr	r3, [r4, #0]
 800528c:	691a      	ldr	r2, [r3, #16]
 800528e:	0652      	lsls	r2, r2, #25
 8005290:	d508      	bpl.n	80052a4 <HAL_TIM_IRQHandler+0xf4>
  {
    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
 8005292:	68da      	ldr	r2, [r3, #12]
 8005294:	0650      	lsls	r0, r2, #25
 8005296:	d505      	bpl.n	80052a4 <HAL_TIM_IRQHandler+0xf4>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
 8005298:	f06f 0240 	mvn.w	r2, #64	; 0x40
      HAL_TIM_TriggerCallback(htim);
 800529c:	4620      	mov	r0, r4
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
 800529e:	611a      	str	r2, [r3, #16]
      HAL_TIM_TriggerCallback(htim);
 80052a0:	f7ff ff85 	bl	80051ae <HAL_TIM_TriggerCallback>
    }
  }
  /* TIM commutation event */
  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
 80052a4:	6823      	ldr	r3, [r4, #0]
 80052a6:	691a      	ldr	r2, [r3, #16]
 80052a8:	0691      	lsls	r1, r2, #26
 80052aa:	d522      	bpl.n	80052f2 <HAL_TIM_IRQHandler+0x142>
  {
    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
 80052ac:	68da      	ldr	r2, [r3, #12]
 80052ae:	0692      	lsls	r2, r2, #26
 80052b0:	d51f      	bpl.n	80052f2 <HAL_TIM_IRQHandler+0x142>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
 80052b2:	f06f 0220 	mvn.w	r2, #32
      HAL_TIMEx_CommutationCallback(htim);
 80052b6:	4620      	mov	r0, r4
    }
  }
}
 80052b8:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
      __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
 80052bc:	611a      	str	r2, [r3, #16]
      HAL_TIMEx_CommutationCallback(htim);
 80052be:	f000 b8a1 	b.w	8005404 <HAL_TIMEx_CommutationCallback>
          HAL_TIM_OC_DelayElapsedCallback(htim);
 80052c2:	f7ff ff71 	bl	80051a8 <HAL_TIM_OC_DelayElapsedCallback>
          HAL_TIM_PWM_PulseFinishedCallback(htim);
 80052c6:	4620      	mov	r0, r4
 80052c8:	f7ff ff70 	bl	80051ac <HAL_TIM_PWM_PulseFinishedCallback>
 80052cc:	e783      	b.n	80051d6 <HAL_TIM_IRQHandler+0x26>
        HAL_TIM_OC_DelayElapsedCallback(htim);
 80052ce:	f7ff ff6b 	bl	80051a8 <HAL_TIM_OC_DelayElapsedCallback>
        HAL_TIM_PWM_PulseFinishedCallback(htim);
 80052d2:	4620      	mov	r0, r4
 80052d4:	f7ff ff6a 	bl	80051ac <HAL_TIM_PWM_PulseFinishedCallback>
 80052d8:	e792      	b.n	8005200 <HAL_TIM_IRQHandler+0x50>
        HAL_TIM_OC_DelayElapsedCallback(htim);
 80052da:	f7ff ff65 	bl	80051a8 <HAL_TIM_OC_DelayElapsedCallback>
        HAL_TIM_PWM_PulseFinishedCallback(htim);
 80052de:	4620      	mov	r0, r4
 80052e0:	f7ff ff64 	bl	80051ac <HAL_TIM_PWM_PulseFinishedCallback>
 80052e4:	e7a0      	b.n	8005228 <HAL_TIM_IRQHandler+0x78>
        HAL_TIM_OC_DelayElapsedCallback(htim);
 80052e6:	f7ff ff5f 	bl	80051a8 <HAL_TIM_OC_DelayElapsedCallback>
        HAL_TIM_PWM_PulseFinishedCallback(htim);
 80052ea:	4620      	mov	r0, r4
 80052ec:	f7ff ff5e 	bl	80051ac <HAL_TIM_PWM_PulseFinishedCallback>
 80052f0:	e7af      	b.n	8005252 <HAL_TIM_IRQHandler+0xa2>
 80052f2:	bd10      	pop	{r4, pc}

080052f4 <TIM_Base_SetConfig>:
{
  uint32_t tmpcr1 = 0U;
  tmpcr1 = TIMx->CR1;

  /* Set TIM Time Base Unit parameters ---------------------------------------*/
  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
 80052f4:	4a24      	ldr	r2, [pc, #144]	; (8005388 <TIM_Base_SetConfig+0x94>)
  tmpcr1 = TIMx->CR1;
 80052f6:	6803      	ldr	r3, [r0, #0]
  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
 80052f8:	4290      	cmp	r0, r2
 80052fa:	d012      	beq.n	8005322 <TIM_Base_SetConfig+0x2e>
 80052fc:	f502 6200 	add.w	r2, r2, #2048	; 0x800
 8005300:	4290      	cmp	r0, r2
 8005302:	d00e      	beq.n	8005322 <TIM_Base_SetConfig+0x2e>
 8005304:	f1b0 4f80 	cmp.w	r0, #1073741824	; 0x40000000
 8005308:	d00b      	beq.n	8005322 <TIM_Base_SetConfig+0x2e>
 800530a:	f5a2 3298 	sub.w	r2, r2, #77824	; 0x13000
 800530e:	4290      	cmp	r0, r2
 8005310:	d007      	beq.n	8005322 <TIM_Base_SetConfig+0x2e>
 8005312:	f502 6280 	add.w	r2, r2, #1024	; 0x400
 8005316:	4290      	cmp	r0, r2
 8005318:	d003      	beq.n	8005322 <TIM_Base_SetConfig+0x2e>
 800531a:	f502 6280 	add.w	r2, r2, #1024	; 0x400
 800531e:	4290      	cmp	r0, r2
 8005320:	d11d      	bne.n	800535e <TIM_Base_SetConfig+0x6a>
  {
    /* Select the Counter Mode */
    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
    tmpcr1 |= Structure->CounterMode;
 8005322:	684a      	ldr	r2, [r1, #4]
    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
 8005324:	f023 0370 	bic.w	r3, r3, #112	; 0x70
    tmpcr1 |= Structure->CounterMode;
 8005328:	4313      	orrs	r3, r2
  }

  if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
 800532a:	4a17      	ldr	r2, [pc, #92]	; (8005388 <TIM_Base_SetConfig+0x94>)
 800532c:	4290      	cmp	r0, r2
 800532e:	d012      	beq.n	8005356 <TIM_Base_SetConfig+0x62>
 8005330:	f502 6200 	add.w	r2, r2, #2048	; 0x800
 8005334:	4290      	cmp	r0, r2
 8005336:	d00e      	beq.n	8005356 <TIM_Base_SetConfig+0x62>
 8005338:	f1b0 4f80 	cmp.w	r0, #1073741824	; 0x40000000
 800533c:	d00b      	beq.n	8005356 <TIM_Base_SetConfig+0x62>
 800533e:	f5a2 3298 	sub.w	r2, r2, #77824	; 0x13000
 8005342:	4290      	cmp	r0, r2
 8005344:	d007      	beq.n	8005356 <TIM_Base_SetConfig+0x62>
 8005346:	f502 6280 	add.w	r2, r2, #1024	; 0x400
 800534a:	4290      	cmp	r0, r2
 800534c:	d003      	beq.n	8005356 <TIM_Base_SetConfig+0x62>
 800534e:	f502 6280 	add.w	r2, r2, #1024	; 0x400
 8005352:	4290      	cmp	r0, r2
 8005354:	d103      	bne.n	800535e <TIM_Base_SetConfig+0x6a>
  {
    /* Set the clock division */
    tmpcr1 &= ~TIM_CR1_CKD;
    tmpcr1 |= (uint32_t)Structure->ClockDivision;
 8005356:	68ca      	ldr	r2, [r1, #12]
    tmpcr1 &= ~TIM_CR1_CKD;
 8005358:	f423 7340 	bic.w	r3, r3, #768	; 0x300
    tmpcr1 |= (uint32_t)Structure->ClockDivision;
 800535c:	4313      	orrs	r3, r2
  }

  /* Set the auto-reload preload */
  tmpcr1 &= ~TIM_CR1_ARPE;
  tmpcr1 |= (uint32_t)Structure->AutoReloadPreload;
 800535e:	694a      	ldr	r2, [r1, #20]
  tmpcr1 &= ~TIM_CR1_ARPE;
 8005360:	f023 0380 	bic.w	r3, r3, #128	; 0x80
  tmpcr1 |= (uint32_t)Structure->AutoReloadPreload;
 8005364:	4313      	orrs	r3, r2

  TIMx->CR1 = tmpcr1;
 8005366:	6003      	str	r3, [r0, #0]

  /* Set the Autoreload value */
  TIMx->ARR = (uint32_t)Structure->Period ;
 8005368:	688b      	ldr	r3, [r1, #8]
 800536a:	62c3      	str	r3, [r0, #44]	; 0x2c

  /* Set the Prescaler value */
  TIMx->PSC = (uint32_t)Structure->Prescaler;
 800536c:	680b      	ldr	r3, [r1, #0]
 800536e:	6283      	str	r3, [r0, #40]	; 0x28

  if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
 8005370:	4b05      	ldr	r3, [pc, #20]	; (8005388 <TIM_Base_SetConfig+0x94>)
 8005372:	4298      	cmp	r0, r3
 8005374:	d003      	beq.n	800537e <TIM_Base_SetConfig+0x8a>
 8005376:	f503 6300 	add.w	r3, r3, #2048	; 0x800
 800537a:	4298      	cmp	r0, r3
 800537c:	d101      	bne.n	8005382 <TIM_Base_SetConfig+0x8e>
  {
    /* Set the Repetition Counter value */
    TIMx->RCR = Structure->RepetitionCounter;
 800537e:	690b      	ldr	r3, [r1, #16]
 8005380:	6303      	str	r3, [r0, #48]	; 0x30
  }

  /* Generate an update event to reload the Prescaler 
     and the repetition counter(only for TIM1 and TIM8) value immediatly */
  TIMx->EGR = TIM_EGR_UG;
 8005382:	2301      	movs	r3, #1
 8005384:	6143      	str	r3, [r0, #20]
 8005386:	4770      	bx	lr
 8005388:	40012c00 	.word	0x40012c00

0800538c <HAL_TIM_Base_Init>:
{
 800538c:	b510      	push	{r4, lr}
  if(htim == NULL)
 800538e:	4604      	mov	r4, r0
 8005390:	b1a0      	cbz	r0, 80053bc <HAL_TIM_Base_Init+0x30>
  if(htim->State == HAL_TIM_STATE_RESET)
 8005392:	f890 303d 	ldrb.w	r3, [r0, #61]	; 0x3d
 8005396:	f003 02ff 	and.w	r2, r3, #255	; 0xff
 800539a:	b91b      	cbnz	r3, 80053a4 <HAL_TIM_Base_Init+0x18>
    htim->Lock = HAL_UNLOCKED;
 800539c:	f880 203c 	strb.w	r2, [r0, #60]	; 0x3c
    HAL_TIM_Base_MspInit(htim);
 80053a0:	f000 fe12 	bl	8005fc8 <HAL_TIM_Base_MspInit>
  htim->State= HAL_TIM_STATE_BUSY;
 80053a4:	2302      	movs	r3, #2
  TIM_Base_SetConfig(htim->Instance, &htim->Init);
 80053a6:	6820      	ldr	r0, [r4, #0]
  htim->State= HAL_TIM_STATE_BUSY;
 80053a8:	f884 303d 	strb.w	r3, [r4, #61]	; 0x3d
  TIM_Base_SetConfig(htim->Instance, &htim->Init);
 80053ac:	1d21      	adds	r1, r4, #4
 80053ae:	f7ff ffa1 	bl	80052f4 <TIM_Base_SetConfig>
  htim->State= HAL_TIM_STATE_READY;
 80053b2:	2301      	movs	r3, #1
  return HAL_OK;
 80053b4:	2000      	movs	r0, #0
  htim->State= HAL_TIM_STATE_READY;
 80053b6:	f884 303d 	strb.w	r3, [r4, #61]	; 0x3d
  return HAL_OK;
 80053ba:	bd10      	pop	{r4, pc}
    return HAL_ERROR;
 80053bc:	2001      	movs	r0, #1
}
 80053be:	bd10      	pop	{r4, pc}

080053c0 <HAL_TIMEx_MasterConfigSynchronization>:
  /* Check the parameters */
  assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
  assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
  assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));

  __HAL_LOCK(htim);
 80053c0:	f890 303c 	ldrb.w	r3, [r0, #60]	; 0x3c
{
 80053c4:	b510      	push	{r4, lr}
  __HAL_LOCK(htim);
 80053c6:	2b01      	cmp	r3, #1
 80053c8:	f04f 0302 	mov.w	r3, #2
 80053cc:	d018      	beq.n	8005400 <HAL_TIMEx_MasterConfigSynchronization+0x40>

  htim->State = HAL_TIM_STATE_BUSY;
 80053ce:	f880 303d 	strb.w	r3, [r0, #61]	; 0x3d

  /* Reset the MMS Bits */
  htim->Instance->CR2 &= ~TIM_CR2_MMS;
 80053d2:	6803      	ldr	r3, [r0, #0]
  /* Select the TRGO source */
  htim->Instance->CR2 |=  sMasterConfig->MasterOutputTrigger;
 80053d4:	680c      	ldr	r4, [r1, #0]
  htim->Instance->CR2 &= ~TIM_CR2_MMS;
 80053d6:	685a      	ldr	r2, [r3, #4]

  /* Reset the MSM Bit */
  htim->Instance->SMCR &= ~TIM_SMCR_MSM;
  /* Set or Reset the MSM Bit */
  htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode;
 80053d8:	6849      	ldr	r1, [r1, #4]
  htim->Instance->CR2 &= ~TIM_CR2_MMS;
 80053da:	f022 0270 	bic.w	r2, r2, #112	; 0x70
 80053de:	605a      	str	r2, [r3, #4]
  htim->Instance->CR2 |=  sMasterConfig->MasterOutputTrigger;
 80053e0:	685a      	ldr	r2, [r3, #4]
 80053e2:	4322      	orrs	r2, r4
 80053e4:	605a      	str	r2, [r3, #4]
  htim->Instance->SMCR &= ~TIM_SMCR_MSM;
 80053e6:	689a      	ldr	r2, [r3, #8]
 80053e8:	f022 0280 	bic.w	r2, r2, #128	; 0x80
 80053ec:	609a      	str	r2, [r3, #8]
  htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode;
 80053ee:	689a      	ldr	r2, [r3, #8]
 80053f0:	430a      	orrs	r2, r1
 80053f2:	609a      	str	r2, [r3, #8]

  htim->State = HAL_TIM_STATE_READY;
 80053f4:	2301      	movs	r3, #1
 80053f6:	f880 303d 	strb.w	r3, [r0, #61]	; 0x3d

  __HAL_UNLOCK(htim);
 80053fa:	2300      	movs	r3, #0
 80053fc:	f880 303c 	strb.w	r3, [r0, #60]	; 0x3c
  __HAL_LOCK(htim);
 8005400:	4618      	mov	r0, r3

  return HAL_OK;
}
 8005402:	bd10      	pop	{r4, pc}

08005404 <HAL_TIMEx_CommutationCallback>:
 8005404:	4770      	bx	lr

08005406 <HAL_TIMEx_BreakCallback>:
  * @brief  Hall Break detection callback in non blocking mode
  * @param  htim : TIM handle
  * @retval None
  */
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
{
 8005406:	4770      	bx	lr

08005408 <UART_EndRxTransfer>:
  * @retval None
  */
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
{
  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
 8005408:	6803      	ldr	r3, [r0, #0]
 800540a:	68da      	ldr	r2, [r3, #12]
 800540c:	f422 7290 	bic.w	r2, r2, #288	; 0x120
 8005410:	60da      	str	r2, [r3, #12]
  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 8005412:	695a      	ldr	r2, [r3, #20]
 8005414:	f022 0201 	bic.w	r2, r2, #1
 8005418:	615a      	str	r2, [r3, #20]

  /* At end of Rx process, restore huart->RxState to Ready */
  huart->RxState = HAL_UART_STATE_READY;
 800541a:	2320      	movs	r3, #32
 800541c:	f880 303a 	strb.w	r3, [r0, #58]	; 0x3a
 8005420:	4770      	bx	lr
	...

08005424 <UART_SetConfig>:
  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
  *                the configuration information for the specified UART module.
  * @retval None
  */
static void UART_SetConfig(UART_HandleTypeDef *huart)
{
 8005424:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
  assert_param(IS_UART_MODE(huart->Init.Mode));

  /*------- UART-associated USART registers setting : CR2 Configuration ------*/
  /* Configure the UART Stop Bits: Set STOP[13:12] bits according 
   * to huart->Init.StopBits value */
  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
 8005428:	6805      	ldr	r5, [r0, #0]
 800542a:	68c2      	ldr	r2, [r0, #12]
 800542c:	692b      	ldr	r3, [r5, #16]
  tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
  MODIFY_REG(huart->Instance->CR1, 
             (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), 
             tmpreg);
#else
  tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
 800542e:	6901      	ldr	r1, [r0, #16]
  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
 8005430:	f423 5340 	bic.w	r3, r3, #12288	; 0x3000
 8005434:	4313      	orrs	r3, r2
 8005436:	612b      	str	r3, [r5, #16]
  tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
 8005438:	6883      	ldr	r3, [r0, #8]
  MODIFY_REG(huart->Instance->CR1, 
 800543a:	68ea      	ldr	r2, [r5, #12]
  tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
 800543c:	430b      	orrs	r3, r1
 800543e:	6941      	ldr	r1, [r0, #20]
  MODIFY_REG(huart->Instance->CR1, 
 8005440:	f422 52b0 	bic.w	r2, r2, #5632	; 0x1600
 8005444:	f022 020c 	bic.w	r2, r2, #12
  tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
 8005448:	430b      	orrs	r3, r1
  MODIFY_REG(huart->Instance->CR1, 
 800544a:	4313      	orrs	r3, r2
 800544c:	60eb      	str	r3, [r5, #12]
             tmpreg);
#endif /* USART_CR1_OVER8 */

  /*------- UART-associated USART registers setting : CR3 Configuration ------*/
  /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
  MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
 800544e:	696b      	ldr	r3, [r5, #20]
 8005450:	6982      	ldr	r2, [r0, #24]
 8005452:	f423 7340 	bic.w	r3, r3, #768	; 0x300
 8005456:	4313      	orrs	r3, r2
 8005458:	616b      	str	r3, [r5, #20]
      huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
    }
  }
#else
  /*-------------------------- USART BRR Configuration ---------------------*/
  if(huart->Instance == USART1)
 800545a:	4b40      	ldr	r3, [pc, #256]	; (800555c <UART_SetConfig+0x138>)
{
 800545c:	4681      	mov	r9, r0
  if(huart->Instance == USART1)
 800545e:	429d      	cmp	r5, r3
 8005460:	f04f 0419 	mov.w	r4, #25
 8005464:	d146      	bne.n	80054f4 <UART_SetConfig+0xd0>
  {
    huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
 8005466:	f7ff fe17 	bl	8005098 <HAL_RCC_GetPCLK2Freq>
 800546a:	fb04 f300 	mul.w	r3, r4, r0
 800546e:	f8d9 6004 	ldr.w	r6, [r9, #4]
 8005472:	f04f 0864 	mov.w	r8, #100	; 0x64
 8005476:	00b6      	lsls	r6, r6, #2
 8005478:	fbb3 f3f6 	udiv	r3, r3, r6
 800547c:	fbb3 f3f8 	udiv	r3, r3, r8
 8005480:	011e      	lsls	r6, r3, #4
 8005482:	f7ff fe09 	bl	8005098 <HAL_RCC_GetPCLK2Freq>
 8005486:	4360      	muls	r0, r4
 8005488:	f8d9 3004 	ldr.w	r3, [r9, #4]
 800548c:	009b      	lsls	r3, r3, #2
 800548e:	fbb0 f7f3 	udiv	r7, r0, r3
 8005492:	f7ff fe01 	bl	8005098 <HAL_RCC_GetPCLK2Freq>
 8005496:	4360      	muls	r0, r4
 8005498:	f8d9 3004 	ldr.w	r3, [r9, #4]
 800549c:	009b      	lsls	r3, r3, #2
 800549e:	fbb0 f3f3 	udiv	r3, r0, r3
 80054a2:	fbb3 f3f8 	udiv	r3, r3, r8
 80054a6:	fb08 7313 	mls	r3, r8, r3, r7
 80054aa:	011b      	lsls	r3, r3, #4
 80054ac:	3332      	adds	r3, #50	; 0x32
 80054ae:	fbb3 f3f8 	udiv	r3, r3, r8
 80054b2:	f003 07f0 	and.w	r7, r3, #240	; 0xf0
 80054b6:	f7ff fdef 	bl	8005098 <HAL_RCC_GetPCLK2Freq>
 80054ba:	4360      	muls	r0, r4
 80054bc:	f8d9 2004 	ldr.w	r2, [r9, #4]
 80054c0:	0092      	lsls	r2, r2, #2
 80054c2:	fbb0 faf2 	udiv	sl, r0, r2
 80054c6:	f7ff fde7 	bl	8005098 <HAL_RCC_GetPCLK2Freq>
  }
  else
  {
    huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
 80054ca:	4360      	muls	r0, r4
 80054cc:	f8d9 3004 	ldr.w	r3, [r9, #4]
 80054d0:	009b      	lsls	r3, r3, #2
 80054d2:	fbb0 f3f3 	udiv	r3, r0, r3
 80054d6:	fbb3 f3f8 	udiv	r3, r3, r8
 80054da:	fb08 a313 	mls	r3, r8, r3, sl
 80054de:	011b      	lsls	r3, r3, #4
 80054e0:	3332      	adds	r3, #50	; 0x32
 80054e2:	fbb3 f3f8 	udiv	r3, r3, r8
 80054e6:	f003 030f 	and.w	r3, r3, #15
 80054ea:	433b      	orrs	r3, r7
 80054ec:	4433      	add	r3, r6
 80054ee:	60ab      	str	r3, [r5, #8]
 80054f0:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 80054f4:	f7ff fdc0 	bl	8005078 <HAL_RCC_GetPCLK1Freq>
 80054f8:	fb04 f300 	mul.w	r3, r4, r0
 80054fc:	f8d9 6004 	ldr.w	r6, [r9, #4]
 8005500:	f04f 0864 	mov.w	r8, #100	; 0x64
 8005504:	00b6      	lsls	r6, r6, #2
 8005506:	fbb3 f3f6 	udiv	r3, r3, r6
 800550a:	fbb3 f3f8 	udiv	r3, r3, r8
 800550e:	011e      	lsls	r6, r3, #4
 8005510:	f7ff fdb2 	bl	8005078 <HAL_RCC_GetPCLK1Freq>
 8005514:	4360      	muls	r0, r4
 8005516:	f8d9 3004 	ldr.w	r3, [r9, #4]
 800551a:	009b      	lsls	r3, r3, #2
 800551c:	fbb0 f7f3 	udiv	r7, r0, r3
 8005520:	f7ff fdaa 	bl	8005078 <HAL_RCC_GetPCLK1Freq>
 8005524:	4360      	muls	r0, r4
 8005526:	f8d9 3004 	ldr.w	r3, [r9, #4]
 800552a:	009b      	lsls	r3, r3, #2
 800552c:	fbb0 f3f3 	udiv	r3, r0, r3
 8005530:	fbb3 f3f8 	udiv	r3, r3, r8
 8005534:	fb08 7313 	mls	r3, r8, r3, r7
 8005538:	011b      	lsls	r3, r3, #4
 800553a:	3332      	adds	r3, #50	; 0x32
 800553c:	fbb3 f3f8 	udiv	r3, r3, r8
 8005540:	f003 07f0 	and.w	r7, r3, #240	; 0xf0
 8005544:	f7ff fd98 	bl	8005078 <HAL_RCC_GetPCLK1Freq>
 8005548:	4360      	muls	r0, r4
 800554a:	f8d9 2004 	ldr.w	r2, [r9, #4]
 800554e:	0092      	lsls	r2, r2, #2
 8005550:	fbb0 faf2 	udiv	sl, r0, r2
 8005554:	f7ff fd90 	bl	8005078 <HAL_RCC_GetPCLK1Freq>
 8005558:	e7b7      	b.n	80054ca <UART_SetConfig+0xa6>
 800555a:	bf00      	nop
 800555c:	40013800 	.word	0x40013800

08005560 <UART_WaitOnFlagUntilTimeout.constprop.3>:
static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
 8005560:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 8005562:	4604      	mov	r4, r0
 8005564:	460e      	mov	r6, r1
 8005566:	4617      	mov	r7, r2
 8005568:	461d      	mov	r5, r3
  while((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 
 800556a:	6821      	ldr	r1, [r4, #0]
 800556c:	680b      	ldr	r3, [r1, #0]
 800556e:	ea36 0303 	bics.w	r3, r6, r3
 8005572:	d101      	bne.n	8005578 <UART_WaitOnFlagUntilTimeout.constprop.3+0x18>
  return HAL_OK;
 8005574:	2000      	movs	r0, #0
}
 8005576:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    if(Timeout != HAL_MAX_DELAY)
 8005578:	1c6b      	adds	r3, r5, #1
 800557a:	d0f7      	beq.n	800556c <UART_WaitOnFlagUntilTimeout.constprop.3+0xc>
      if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
 800557c:	b995      	cbnz	r5, 80055a4 <UART_WaitOnFlagUntilTimeout.constprop.3+0x44>
        CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
 800557e:	6823      	ldr	r3, [r4, #0]
        __HAL_UNLOCK(huart);
 8005580:	2003      	movs	r0, #3
        CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
 8005582:	68da      	ldr	r2, [r3, #12]
 8005584:	f422 72d0 	bic.w	r2, r2, #416	; 0x1a0
 8005588:	60da      	str	r2, [r3, #12]
        CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 800558a:	695a      	ldr	r2, [r3, #20]
 800558c:	f022 0201 	bic.w	r2, r2, #1
 8005590:	615a      	str	r2, [r3, #20]
        huart->gState  = HAL_UART_STATE_READY;
 8005592:	2320      	movs	r3, #32
 8005594:	f884 3039 	strb.w	r3, [r4, #57]	; 0x39
        huart->RxState = HAL_UART_STATE_READY;
 8005598:	f884 303a 	strb.w	r3, [r4, #58]	; 0x3a
        __HAL_UNLOCK(huart);
 800559c:	2300      	movs	r3, #0
 800559e:	f884 3038 	strb.w	r3, [r4, #56]	; 0x38
 80055a2:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
      if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
 80055a4:	f7fe fe80 	bl	80042a8 <HAL_GetTick>
 80055a8:	1bc0      	subs	r0, r0, r7
 80055aa:	4285      	cmp	r5, r0
 80055ac:	d2dd      	bcs.n	800556a <UART_WaitOnFlagUntilTimeout.constprop.3+0xa>
 80055ae:	e7e6      	b.n	800557e <UART_WaitOnFlagUntilTimeout.constprop.3+0x1e>

080055b0 <HAL_UART_Init>:
{
 80055b0:	b510      	push	{r4, lr}
  if(huart == NULL)
 80055b2:	4604      	mov	r4, r0
 80055b4:	b340      	cbz	r0, 8005608 <HAL_UART_Init+0x58>
  if(huart->gState == HAL_UART_STATE_RESET)
 80055b6:	f890 3039 	ldrb.w	r3, [r0, #57]	; 0x39
 80055ba:	f003 02ff 	and.w	r2, r3, #255	; 0xff
 80055be:	b91b      	cbnz	r3, 80055c8 <HAL_UART_Init+0x18>
    huart->Lock = HAL_UNLOCKED;
 80055c0:	f880 2038 	strb.w	r2, [r0, #56]	; 0x38
    HAL_UART_MspInit(huart);
 80055c4:	f000 fd14 	bl	8005ff0 <HAL_UART_MspInit>
  huart->gState = HAL_UART_STATE_BUSY;
 80055c8:	2324      	movs	r3, #36	; 0x24
  __HAL_UART_DISABLE(huart);
 80055ca:	6822      	ldr	r2, [r4, #0]
  huart->gState = HAL_UART_STATE_BUSY;
 80055cc:	f884 3039 	strb.w	r3, [r4, #57]	; 0x39
  __HAL_UART_DISABLE(huart);
 80055d0:	68d3      	ldr	r3, [r2, #12]
  UART_SetConfig(huart);
 80055d2:	4620      	mov	r0, r4
  __HAL_UART_DISABLE(huart);
 80055d4:	f423 5300 	bic.w	r3, r3, #8192	; 0x2000
 80055d8:	60d3      	str	r3, [r2, #12]
  UART_SetConfig(huart);
 80055da:	f7ff ff23 	bl	8005424 <UART_SetConfig>
  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
 80055de:	6823      	ldr	r3, [r4, #0]
  huart->ErrorCode = HAL_UART_ERROR_NONE;
 80055e0:	2000      	movs	r0, #0
  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
 80055e2:	691a      	ldr	r2, [r3, #16]
 80055e4:	f422 4290 	bic.w	r2, r2, #18432	; 0x4800
 80055e8:	611a      	str	r2, [r3, #16]
  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
 80055ea:	695a      	ldr	r2, [r3, #20]
 80055ec:	f022 022a 	bic.w	r2, r2, #42	; 0x2a
 80055f0:	615a      	str	r2, [r3, #20]
  __HAL_UART_ENABLE(huart);
 80055f2:	68da      	ldr	r2, [r3, #12]
 80055f4:	f442 5200 	orr.w	r2, r2, #8192	; 0x2000
 80055f8:	60da      	str	r2, [r3, #12]
  huart->gState= HAL_UART_STATE_READY;
 80055fa:	2320      	movs	r3, #32
  huart->ErrorCode = HAL_UART_ERROR_NONE;
 80055fc:	63e0      	str	r0, [r4, #60]	; 0x3c
  huart->gState= HAL_UART_STATE_READY;
 80055fe:	f884 3039 	strb.w	r3, [r4, #57]	; 0x39
  huart->RxState= HAL_UART_STATE_READY;
 8005602:	f884 303a 	strb.w	r3, [r4, #58]	; 0x3a
  return HAL_OK;
 8005606:	bd10      	pop	{r4, pc}
    return HAL_ERROR;
 8005608:	2001      	movs	r0, #1
}
 800560a:	bd10      	pop	{r4, pc}

0800560c <HAL_UART_Transmit>:
{
 800560c:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
 8005610:	461f      	mov	r7, r3
  if(huart->gState == HAL_UART_STATE_READY)
 8005612:	f890 3039 	ldrb.w	r3, [r0, #57]	; 0x39
{
 8005616:	4604      	mov	r4, r0
  if(huart->gState == HAL_UART_STATE_READY)
 8005618:	2b20      	cmp	r3, #32
{
 800561a:	460d      	mov	r5, r1
 800561c:	4690      	mov	r8, r2
  if(huart->gState == HAL_UART_STATE_READY)
 800561e:	d14e      	bne.n	80056be <HAL_UART_Transmit+0xb2>
    if((pData == NULL) || (Size == 0U))
 8005620:	2900      	cmp	r1, #0
 8005622:	d049      	beq.n	80056b8 <HAL_UART_Transmit+0xac>
 8005624:	2a00      	cmp	r2, #0
 8005626:	d047      	beq.n	80056b8 <HAL_UART_Transmit+0xac>
    __HAL_LOCK(huart);
 8005628:	f890 3038 	ldrb.w	r3, [r0, #56]	; 0x38
 800562c:	2b01      	cmp	r3, #1
 800562e:	d046      	beq.n	80056be <HAL_UART_Transmit+0xb2>
 8005630:	2301      	movs	r3, #1
 8005632:	f880 3038 	strb.w	r3, [r0, #56]	; 0x38
    huart->ErrorCode = HAL_UART_ERROR_NONE;
 8005636:	2300      	movs	r3, #0
 8005638:	63c3      	str	r3, [r0, #60]	; 0x3c
    huart->gState = HAL_UART_STATE_BUSY_TX;
 800563a:	2321      	movs	r3, #33	; 0x21
 800563c:	f880 3039 	strb.w	r3, [r0, #57]	; 0x39
    tickstart = HAL_GetTick();
 8005640:	f7fe fe32 	bl	80042a8 <HAL_GetTick>
 8005644:	4606      	mov	r6, r0
    huart->TxXferSize = Size;
 8005646:	f8a4 8024 	strh.w	r8, [r4, #36]	; 0x24
    huart->TxXferCount = Size;
 800564a:	f8a4 8026 	strh.w	r8, [r4, #38]	; 0x26
    while(huart->TxXferCount > 0U)
 800564e:	8ce3      	ldrh	r3, [r4, #38]	; 0x26
 8005650:	b29b      	uxth	r3, r3
 8005652:	b96b      	cbnz	r3, 8005670 <HAL_UART_Transmit+0x64>
    if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
 8005654:	463b      	mov	r3, r7
 8005656:	4632      	mov	r2, r6
 8005658:	2140      	movs	r1, #64	; 0x40
 800565a:	4620      	mov	r0, r4
 800565c:	f7ff ff80 	bl	8005560 <UART_WaitOnFlagUntilTimeout.constprop.3>
 8005660:	b9a8      	cbnz	r0, 800568e <HAL_UART_Transmit+0x82>
    huart->gState = HAL_UART_STATE_READY;
 8005662:	2320      	movs	r3, #32
    __HAL_UNLOCK(huart);
 8005664:	f884 0038 	strb.w	r0, [r4, #56]	; 0x38
    huart->gState = HAL_UART_STATE_READY;
 8005668:	f884 3039 	strb.w	r3, [r4, #57]	; 0x39
    return HAL_OK;
 800566c:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
      huart->TxXferCount--;
 8005670:	8ce3      	ldrh	r3, [r4, #38]	; 0x26
        if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
 8005672:	4632      	mov	r2, r6
      huart->TxXferCount--;
 8005674:	3b01      	subs	r3, #1
 8005676:	b29b      	uxth	r3, r3
 8005678:	84e3      	strh	r3, [r4, #38]	; 0x26
      if(huart->Init.WordLength == UART_WORDLENGTH_9B)
 800567a:	68a3      	ldr	r3, [r4, #8]
        if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
 800567c:	2180      	movs	r1, #128	; 0x80
      if(huart->Init.WordLength == UART_WORDLENGTH_9B)
 800567e:	f5b3 5f80 	cmp.w	r3, #4096	; 0x1000
        if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
 8005682:	4620      	mov	r0, r4
 8005684:	463b      	mov	r3, r7
      if(huart->Init.WordLength == UART_WORDLENGTH_9B)
 8005686:	d10e      	bne.n	80056a6 <HAL_UART_Transmit+0x9a>
        if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
 8005688:	f7ff ff6a 	bl	8005560 <UART_WaitOnFlagUntilTimeout.constprop.3>
 800568c:	b110      	cbz	r0, 8005694 <HAL_UART_Transmit+0x88>
          return HAL_TIMEOUT;
 800568e:	2003      	movs	r0, #3
 8005690:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
        huart->Instance->DR = (*tmp & (uint16_t)0x01FF);
 8005694:	882b      	ldrh	r3, [r5, #0]
 8005696:	6822      	ldr	r2, [r4, #0]
 8005698:	f3c3 0308 	ubfx	r3, r3, #0, #9
 800569c:	6053      	str	r3, [r2, #4]
        if(huart->Init.Parity == UART_PARITY_NONE)
 800569e:	6923      	ldr	r3, [r4, #16]
 80056a0:	b943      	cbnz	r3, 80056b4 <HAL_UART_Transmit+0xa8>
          pData +=2U;
 80056a2:	3502      	adds	r5, #2
 80056a4:	e7d3      	b.n	800564e <HAL_UART_Transmit+0x42>
        if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
 80056a6:	f7ff ff5b 	bl	8005560 <UART_WaitOnFlagUntilTimeout.constprop.3>
 80056aa:	2800      	cmp	r0, #0
 80056ac:	d1ef      	bne.n	800568e <HAL_UART_Transmit+0x82>
        huart->Instance->DR = (*pData++ & (uint8_t)0xFF);
 80056ae:	6823      	ldr	r3, [r4, #0]
 80056b0:	782a      	ldrb	r2, [r5, #0]
 80056b2:	605a      	str	r2, [r3, #4]
 80056b4:	3501      	adds	r5, #1
 80056b6:	e7ca      	b.n	800564e <HAL_UART_Transmit+0x42>
      return  HAL_ERROR;
 80056b8:	2001      	movs	r0, #1
 80056ba:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    return HAL_BUSY;
 80056be:	2002      	movs	r0, #2
}
 80056c0:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

080056c4 <HAL_UART_Transmit_IT>:
  if(huart->gState == HAL_UART_STATE_READY)
 80056c4:	f890 3039 	ldrb.w	r3, [r0, #57]	; 0x39
 80056c8:	2b20      	cmp	r3, #32
 80056ca:	d118      	bne.n	80056fe <HAL_UART_Transmit_IT+0x3a>
    if((pData == NULL) || (Size == 0U)) 
 80056cc:	b1a9      	cbz	r1, 80056fa <HAL_UART_Transmit_IT+0x36>
 80056ce:	b1a2      	cbz	r2, 80056fa <HAL_UART_Transmit_IT+0x36>
    __HAL_LOCK(huart);
 80056d0:	f890 3038 	ldrb.w	r3, [r0, #56]	; 0x38
 80056d4:	2b01      	cmp	r3, #1
 80056d6:	d012      	beq.n	80056fe <HAL_UART_Transmit_IT+0x3a>
    huart->TxXferCount = Size;
 80056d8:	84c2      	strh	r2, [r0, #38]	; 0x26
    huart->TxXferSize = Size;
 80056da:	8482      	strh	r2, [r0, #36]	; 0x24
    huart->ErrorCode = HAL_UART_ERROR_NONE;
 80056dc:	2300      	movs	r3, #0
    huart->gState = HAL_UART_STATE_BUSY_TX;
 80056de:	2221      	movs	r2, #33	; 0x21
    huart->pTxBuffPtr = pData;
 80056e0:	6201      	str	r1, [r0, #32]
    __HAL_UART_ENABLE_IT(huart, UART_IT_TXE);
 80056e2:	6801      	ldr	r1, [r0, #0]
    huart->ErrorCode = HAL_UART_ERROR_NONE;
 80056e4:	63c3      	str	r3, [r0, #60]	; 0x3c
    huart->gState = HAL_UART_STATE_BUSY_TX;
 80056e6:	f880 2039 	strb.w	r2, [r0, #57]	; 0x39
    __HAL_UART_ENABLE_IT(huart, UART_IT_TXE);
 80056ea:	68ca      	ldr	r2, [r1, #12]
    __HAL_UNLOCK(huart);
 80056ec:	f880 3038 	strb.w	r3, [r0, #56]	; 0x38
    __HAL_UART_ENABLE_IT(huart, UART_IT_TXE);
 80056f0:	f042 0280 	orr.w	r2, r2, #128	; 0x80
 80056f4:	60ca      	str	r2, [r1, #12]
    return HAL_OK;
 80056f6:	4618      	mov	r0, r3
 80056f8:	4770      	bx	lr
      return HAL_ERROR;
 80056fa:	2001      	movs	r0, #1
 80056fc:	4770      	bx	lr
    return HAL_BUSY;
 80056fe:	2002      	movs	r0, #2
}
 8005700:	4770      	bx	lr
	...

08005704 <HAL_UART_Receive_DMA>:
{
 8005704:	4613      	mov	r3, r2
  if(huart->RxState == HAL_UART_STATE_READY) 
 8005706:	f890 203a 	ldrb.w	r2, [r0, #58]	; 0x3a
{
 800570a:	b573      	push	{r0, r1, r4, r5, r6, lr}
  if(huart->RxState == HAL_UART_STATE_READY) 
 800570c:	2a20      	cmp	r2, #32
{
 800570e:	4605      	mov	r5, r0
  if(huart->RxState == HAL_UART_STATE_READY) 
 8005710:	d138      	bne.n	8005784 <HAL_UART_Receive_DMA+0x80>
    if((pData == NULL) || (Size == 0U))
 8005712:	2900      	cmp	r1, #0
 8005714:	d034      	beq.n	8005780 <HAL_UART_Receive_DMA+0x7c>
 8005716:	2b00      	cmp	r3, #0
 8005718:	d032      	beq.n	8005780 <HAL_UART_Receive_DMA+0x7c>
    __HAL_LOCK(huart);
 800571a:	f890 2038 	ldrb.w	r2, [r0, #56]	; 0x38
 800571e:	2a01      	cmp	r2, #1
 8005720:	d030      	beq.n	8005784 <HAL_UART_Receive_DMA+0x80>
 8005722:	2201      	movs	r2, #1
    huart->ErrorCode = HAL_UART_ERROR_NONE;
 8005724:	2400      	movs	r4, #0
    __HAL_LOCK(huart);
 8005726:	f880 2038 	strb.w	r2, [r0, #56]	; 0x38
    huart->RxState = HAL_UART_STATE_BUSY_RX;
 800572a:	2222      	movs	r2, #34	; 0x22
    huart->pRxBuffPtr = pData;
 800572c:	6281      	str	r1, [r0, #40]	; 0x28
    huart->RxXferSize = Size;
 800572e:	8583      	strh	r3, [r0, #44]	; 0x2c
    huart->ErrorCode = HAL_UART_ERROR_NONE;
 8005730:	63c4      	str	r4, [r0, #60]	; 0x3c
    huart->RxState = HAL_UART_STATE_BUSY_RX;
 8005732:	f880 203a 	strb.w	r2, [r0, #58]	; 0x3a
    huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
 8005736:	6b40      	ldr	r0, [r0, #52]	; 0x34
 8005738:	4a13      	ldr	r2, [pc, #76]	; (8005788 <HAL_UART_Receive_DMA+0x84>)
    HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t*)tmp, Size);
 800573a:	682e      	ldr	r6, [r5, #0]
    huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
 800573c:	6282      	str	r2, [r0, #40]	; 0x28
    huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
 800573e:	4a13      	ldr	r2, [pc, #76]	; (800578c <HAL_UART_Receive_DMA+0x88>)
    huart->hdmarx->XferAbortCallback = NULL;
 8005740:	6344      	str	r4, [r0, #52]	; 0x34
    huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
 8005742:	62c2      	str	r2, [r0, #44]	; 0x2c
    huart->hdmarx->XferErrorCallback = UART_DMAError;
 8005744:	4a12      	ldr	r2, [pc, #72]	; (8005790 <HAL_UART_Receive_DMA+0x8c>)
 8005746:	6302      	str	r2, [r0, #48]	; 0x30
    HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t*)tmp, Size);
 8005748:	460a      	mov	r2, r1
 800574a:	1d31      	adds	r1, r6, #4
 800574c:	f7fe ff9c 	bl	8004688 <HAL_DMA_Start_IT>
    return HAL_OK;
 8005750:	4620      	mov	r0, r4
    __HAL_UART_CLEAR_OREFLAG(huart);
 8005752:	682b      	ldr	r3, [r5, #0]
 8005754:	9401      	str	r4, [sp, #4]
 8005756:	681a      	ldr	r2, [r3, #0]
 8005758:	9201      	str	r2, [sp, #4]
 800575a:	685a      	ldr	r2, [r3, #4]
    __HAL_UNLOCK(huart);
 800575c:	f885 4038 	strb.w	r4, [r5, #56]	; 0x38
    __HAL_UART_CLEAR_OREFLAG(huart);
 8005760:	9201      	str	r2, [sp, #4]
 8005762:	9a01      	ldr	r2, [sp, #4]
    SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
 8005764:	68da      	ldr	r2, [r3, #12]
 8005766:	f442 7280 	orr.w	r2, r2, #256	; 0x100
 800576a:	60da      	str	r2, [r3, #12]
    SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
 800576c:	695a      	ldr	r2, [r3, #20]
 800576e:	f042 0201 	orr.w	r2, r2, #1
 8005772:	615a      	str	r2, [r3, #20]
    SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
 8005774:	695a      	ldr	r2, [r3, #20]
 8005776:	f042 0240 	orr.w	r2, r2, #64	; 0x40
 800577a:	615a      	str	r2, [r3, #20]
}
 800577c:	b002      	add	sp, #8
 800577e:	bd70      	pop	{r4, r5, r6, pc}
      return HAL_ERROR;
 8005780:	2001      	movs	r0, #1
 8005782:	e7fb      	b.n	800577c <HAL_UART_Receive_DMA+0x78>
    return HAL_BUSY;
 8005784:	2002      	movs	r0, #2
 8005786:	e7f9      	b.n	800577c <HAL_UART_Receive_DMA+0x78>
 8005788:	08005795 	.word	0x08005795
 800578c:	0800584b 	.word	0x0800584b
 8005790:	08005857 	.word	0x08005857

08005794 <UART_DMAReceiveCplt>:
{
 8005794:	b508      	push	{r3, lr}
  if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
 8005796:	6803      	ldr	r3, [r0, #0]
  UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
 8005798:	6a42      	ldr	r2, [r0, #36]	; 0x24
  if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
 800579a:	681b      	ldr	r3, [r3, #0]
 800579c:	f013 0320 	ands.w	r3, r3, #32
 80057a0:	d110      	bne.n	80057c4 <UART_DMAReceiveCplt+0x30>
    huart->RxXferCount = 0U;
 80057a2:	85d3      	strh	r3, [r2, #46]	; 0x2e
    CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
 80057a4:	6813      	ldr	r3, [r2, #0]
 80057a6:	68d9      	ldr	r1, [r3, #12]
 80057a8:	f421 7180 	bic.w	r1, r1, #256	; 0x100
 80057ac:	60d9      	str	r1, [r3, #12]
    CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 80057ae:	6959      	ldr	r1, [r3, #20]
 80057b0:	f021 0101 	bic.w	r1, r1, #1
 80057b4:	6159      	str	r1, [r3, #20]
    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
 80057b6:	6959      	ldr	r1, [r3, #20]
 80057b8:	f021 0140 	bic.w	r1, r1, #64	; 0x40
 80057bc:	6159      	str	r1, [r3, #20]
    huart->RxState = HAL_UART_STATE_READY;
 80057be:	2320      	movs	r3, #32
 80057c0:	f882 303a 	strb.w	r3, [r2, #58]	; 0x3a
  HAL_UART_RxCpltCallback(huart);
 80057c4:	4610      	mov	r0, r2
 80057c6:	f000 fd55 	bl	8006274 <HAL_UART_RxCpltCallback>
 80057ca:	bd08      	pop	{r3, pc}

080057cc <UART_Receive_IT>:
  if(huart->RxState == HAL_UART_STATE_BUSY_RX) 
 80057cc:	f890 303a 	ldrb.w	r3, [r0, #58]	; 0x3a
{
 80057d0:	b510      	push	{r4, lr}
  if(huart->RxState == HAL_UART_STATE_BUSY_RX) 
 80057d2:	2b22      	cmp	r3, #34	; 0x22
 80057d4:	d136      	bne.n	8005844 <UART_Receive_IT+0x78>
    if(huart->Init.WordLength == UART_WORDLENGTH_9B)
 80057d6:	6883      	ldr	r3, [r0, #8]
 80057d8:	6901      	ldr	r1, [r0, #16]
 80057da:	f5b3 5f80 	cmp.w	r3, #4096	; 0x1000
 80057de:	6802      	ldr	r2, [r0, #0]
 80057e0:	6a83      	ldr	r3, [r0, #40]	; 0x28
 80057e2:	d123      	bne.n	800582c <UART_Receive_IT+0x60>
        *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
 80057e4:	6852      	ldr	r2, [r2, #4]
      if(huart->Init.Parity == UART_PARITY_NONE)
 80057e6:	b9e9      	cbnz	r1, 8005824 <UART_Receive_IT+0x58>
        *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
 80057e8:	f3c2 0208 	ubfx	r2, r2, #0, #9
 80057ec:	f823 2b02 	strh.w	r2, [r3], #2
        huart->pRxBuffPtr += 1U;
 80057f0:	6283      	str	r3, [r0, #40]	; 0x28
    if(--huart->RxXferCount == 0U)
 80057f2:	8dc4      	ldrh	r4, [r0, #46]	; 0x2e
 80057f4:	3c01      	subs	r4, #1
 80057f6:	b2a4      	uxth	r4, r4
 80057f8:	85c4      	strh	r4, [r0, #46]	; 0x2e
 80057fa:	b98c      	cbnz	r4, 8005820 <UART_Receive_IT+0x54>
      __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
 80057fc:	6803      	ldr	r3, [r0, #0]
 80057fe:	68da      	ldr	r2, [r3, #12]
 8005800:	f022 0220 	bic.w	r2, r2, #32
 8005804:	60da      	str	r2, [r3, #12]
      __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
 8005806:	68da      	ldr	r2, [r3, #12]
 8005808:	f422 7280 	bic.w	r2, r2, #256	; 0x100
 800580c:	60da      	str	r2, [r3, #12]
        __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
 800580e:	695a      	ldr	r2, [r3, #20]
 8005810:	f022 0201 	bic.w	r2, r2, #1
 8005814:	615a      	str	r2, [r3, #20]
      huart->RxState = HAL_UART_STATE_READY;
 8005816:	2320      	movs	r3, #32
 8005818:	f880 303a 	strb.w	r3, [r0, #58]	; 0x3a
      HAL_UART_RxCpltCallback(huart);
 800581c:	f000 fd2a 	bl	8006274 <HAL_UART_RxCpltCallback>
    if(--huart->RxXferCount == 0U)
 8005820:	2000      	movs	r0, #0
}
 8005822:	bd10      	pop	{r4, pc}
        *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF);
 8005824:	b2d2      	uxtb	r2, r2
 8005826:	f823 2b01 	strh.w	r2, [r3], #1
 800582a:	e7e1      	b.n	80057f0 <UART_Receive_IT+0x24>
      if(huart->Init.Parity == UART_PARITY_NONE)
 800582c:	b921      	cbnz	r1, 8005838 <UART_Receive_IT+0x6c>
        *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
 800582e:	1c59      	adds	r1, r3, #1
 8005830:	6852      	ldr	r2, [r2, #4]
 8005832:	6281      	str	r1, [r0, #40]	; 0x28
        *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
 8005834:	701a      	strb	r2, [r3, #0]
 8005836:	e7dc      	b.n	80057f2 <UART_Receive_IT+0x26>
 8005838:	6852      	ldr	r2, [r2, #4]
 800583a:	1c59      	adds	r1, r3, #1
 800583c:	6281      	str	r1, [r0, #40]	; 0x28
 800583e:	f002 027f 	and.w	r2, r2, #127	; 0x7f
 8005842:	e7f7      	b.n	8005834 <UART_Receive_IT+0x68>
    return HAL_BUSY;
 8005844:	2002      	movs	r0, #2
 8005846:	bd10      	pop	{r4, pc}

08005848 <HAL_UART_RxHalfCpltCallback>:
 8005848:	4770      	bx	lr

0800584a <UART_DMARxHalfCplt>:
{
 800584a:	b508      	push	{r3, lr}
  HAL_UART_RxHalfCpltCallback(huart); 
 800584c:	6a40      	ldr	r0, [r0, #36]	; 0x24
 800584e:	f7ff fffb 	bl	8005848 <HAL_UART_RxHalfCpltCallback>
 8005852:	bd08      	pop	{r3, pc}

08005854 <HAL_UART_ErrorCallback>:
 8005854:	4770      	bx	lr

08005856 <UART_DMAError>:
  UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
 8005856:	6a41      	ldr	r1, [r0, #36]	; 0x24
{
 8005858:	b508      	push	{r3, lr}
  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
 800585a:	680b      	ldr	r3, [r1, #0]
 800585c:	695a      	ldr	r2, [r3, #20]
  if((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
 800585e:	f891 0039 	ldrb.w	r0, [r1, #57]	; 0x39
 8005862:	2821      	cmp	r0, #33	; 0x21
 8005864:	d10a      	bne.n	800587c <UART_DMAError+0x26>
 8005866:	0612      	lsls	r2, r2, #24
 8005868:	d508      	bpl.n	800587c <UART_DMAError+0x26>
    huart->TxXferCount = 0U;
 800586a:	2200      	movs	r2, #0
 800586c:	84ca      	strh	r2, [r1, #38]	; 0x26
  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
 800586e:	68da      	ldr	r2, [r3, #12]
 8005870:	f022 02c0 	bic.w	r2, r2, #192	; 0xc0
 8005874:	60da      	str	r2, [r3, #12]
  huart->gState = HAL_UART_STATE_READY;
 8005876:	2220      	movs	r2, #32
 8005878:	f881 2039 	strb.w	r2, [r1, #57]	; 0x39
  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 
 800587c:	695b      	ldr	r3, [r3, #20]
  if((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
 800587e:	f891 203a 	ldrb.w	r2, [r1, #58]	; 0x3a
 8005882:	2a22      	cmp	r2, #34	; 0x22
 8005884:	d106      	bne.n	8005894 <UART_DMAError+0x3e>
 8005886:	065b      	lsls	r3, r3, #25
 8005888:	d504      	bpl.n	8005894 <UART_DMAError+0x3e>
    huart->RxXferCount = 0U;
 800588a:	2300      	movs	r3, #0
    UART_EndRxTransfer(huart);
 800588c:	4608      	mov	r0, r1
    huart->RxXferCount = 0U;
 800588e:	85cb      	strh	r3, [r1, #46]	; 0x2e
    UART_EndRxTransfer(huart);
 8005890:	f7ff fdba 	bl	8005408 <UART_EndRxTransfer>
  huart->ErrorCode |= HAL_UART_ERROR_DMA;
 8005894:	6bcb      	ldr	r3, [r1, #60]	; 0x3c
  HAL_UART_ErrorCallback(huart);
 8005896:	4608      	mov	r0, r1
  huart->ErrorCode |= HAL_UART_ERROR_DMA;
 8005898:	f043 0310 	orr.w	r3, r3, #16
 800589c:	63cb      	str	r3, [r1, #60]	; 0x3c
  HAL_UART_ErrorCallback(huart);
 800589e:	f7ff ffd9 	bl	8005854 <HAL_UART_ErrorCallback>
 80058a2:	bd08      	pop	{r3, pc}

080058a4 <HAL_UART_IRQHandler>:
   uint32_t isrflags   = READ_REG(huart->Instance->SR);
 80058a4:	6803      	ldr	r3, [r0, #0]
{
 80058a6:	b570      	push	{r4, r5, r6, lr}
   uint32_t isrflags   = READ_REG(huart->Instance->SR);
 80058a8:	681a      	ldr	r2, [r3, #0]
{
 80058aa:	4604      	mov	r4, r0
  if(errorflags == RESET)
 80058ac:	0716      	lsls	r6, r2, #28
   uint32_t cr1its     = READ_REG(huart->Instance->CR1);
 80058ae:	68d9      	ldr	r1, [r3, #12]
   uint32_t cr3its     = READ_REG(huart->Instance->CR3);
 80058b0:	695d      	ldr	r5, [r3, #20]
  if(errorflags == RESET)
 80058b2:	d107      	bne.n	80058c4 <HAL_UART_IRQHandler+0x20>
    if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
 80058b4:	0696      	lsls	r6, r2, #26
 80058b6:	d55a      	bpl.n	800596e <HAL_UART_IRQHandler+0xca>
 80058b8:	068d      	lsls	r5, r1, #26
 80058ba:	d558      	bpl.n	800596e <HAL_UART_IRQHandler+0xca>
}
 80058bc:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
      UART_Receive_IT(huart);
 80058c0:	f7ff bf84 	b.w	80057cc <UART_Receive_IT>
  if((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
 80058c4:	f015 0501 	ands.w	r5, r5, #1
 80058c8:	d102      	bne.n	80058d0 <HAL_UART_IRQHandler+0x2c>
 80058ca:	f411 7f90 	tst.w	r1, #288	; 0x120
 80058ce:	d04e      	beq.n	800596e <HAL_UART_IRQHandler+0xca>
    if(((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
 80058d0:	07d3      	lsls	r3, r2, #31
 80058d2:	d505      	bpl.n	80058e0 <HAL_UART_IRQHandler+0x3c>
 80058d4:	05ce      	lsls	r6, r1, #23
      huart->ErrorCode |= HAL_UART_ERROR_PE;
 80058d6:	bf42      	ittt	mi
 80058d8:	6be3      	ldrmi	r3, [r4, #60]	; 0x3c
 80058da:	f043 0301 	orrmi.w	r3, r3, #1
 80058de:	63e3      	strmi	r3, [r4, #60]	; 0x3c
    if(((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
 80058e0:	0750      	lsls	r0, r2, #29
 80058e2:	d504      	bpl.n	80058ee <HAL_UART_IRQHandler+0x4a>
 80058e4:	b11d      	cbz	r5, 80058ee <HAL_UART_IRQHandler+0x4a>
      huart->ErrorCode |= HAL_UART_ERROR_NE;
 80058e6:	6be3      	ldr	r3, [r4, #60]	; 0x3c
 80058e8:	f043 0302 	orr.w	r3, r3, #2
 80058ec:	63e3      	str	r3, [r4, #60]	; 0x3c
    if(((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
 80058ee:	0793      	lsls	r3, r2, #30
 80058f0:	d504      	bpl.n	80058fc <HAL_UART_IRQHandler+0x58>
 80058f2:	b11d      	cbz	r5, 80058fc <HAL_UART_IRQHandler+0x58>
      huart->ErrorCode |= HAL_UART_ERROR_FE;
 80058f4:	6be3      	ldr	r3, [r4, #60]	; 0x3c
 80058f6:	f043 0304 	orr.w	r3, r3, #4
 80058fa:	63e3      	str	r3, [r4, #60]	; 0x3c
    if(((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
 80058fc:	0716      	lsls	r6, r2, #28
 80058fe:	d504      	bpl.n	800590a <HAL_UART_IRQHandler+0x66>
 8005900:	b11d      	cbz	r5, 800590a <HAL_UART_IRQHandler+0x66>
      huart->ErrorCode |= HAL_UART_ERROR_ORE;
 8005902:	6be3      	ldr	r3, [r4, #60]	; 0x3c
 8005904:	f043 0308 	orr.w	r3, r3, #8
 8005908:	63e3      	str	r3, [r4, #60]	; 0x3c
    if(huart->ErrorCode != HAL_UART_ERROR_NONE)
 800590a:	6be3      	ldr	r3, [r4, #60]	; 0x3c
 800590c:	2b00      	cmp	r3, #0
 800590e:	d066      	beq.n	80059de <HAL_UART_IRQHandler+0x13a>
      if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
 8005910:	0695      	lsls	r5, r2, #26
 8005912:	d504      	bpl.n	800591e <HAL_UART_IRQHandler+0x7a>
 8005914:	0688      	lsls	r0, r1, #26
 8005916:	d502      	bpl.n	800591e <HAL_UART_IRQHandler+0x7a>
        UART_Receive_IT(huart);
 8005918:	4620      	mov	r0, r4
 800591a:	f7ff ff57 	bl	80057cc <UART_Receive_IT>
      dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
 800591e:	6823      	ldr	r3, [r4, #0]
        UART_EndRxTransfer(huart);
 8005920:	4620      	mov	r0, r4
      dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
 8005922:	695d      	ldr	r5, [r3, #20]
      if(((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest)
 8005924:	6be2      	ldr	r2, [r4, #60]	; 0x3c
 8005926:	0711      	lsls	r1, r2, #28
 8005928:	d402      	bmi.n	8005930 <HAL_UART_IRQHandler+0x8c>
 800592a:	f015 0540 	ands.w	r5, r5, #64	; 0x40
 800592e:	d01a      	beq.n	8005966 <HAL_UART_IRQHandler+0xc2>
        UART_EndRxTransfer(huart);
 8005930:	f7ff fd6a 	bl	8005408 <UART_EndRxTransfer>
        if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
 8005934:	6823      	ldr	r3, [r4, #0]
 8005936:	695a      	ldr	r2, [r3, #20]
 8005938:	0652      	lsls	r2, r2, #25
 800593a:	d510      	bpl.n	800595e <HAL_UART_IRQHandler+0xba>
          CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
 800593c:	695a      	ldr	r2, [r3, #20]
          if(huart->hdmarx != NULL)
 800593e:	6b60      	ldr	r0, [r4, #52]	; 0x34
          CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
 8005940:	f022 0240 	bic.w	r2, r2, #64	; 0x40
 8005944:	615a      	str	r2, [r3, #20]
          if(huart->hdmarx != NULL)
 8005946:	b150      	cbz	r0, 800595e <HAL_UART_IRQHandler+0xba>
            huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
 8005948:	4b25      	ldr	r3, [pc, #148]	; (80059e0 <HAL_UART_IRQHandler+0x13c>)
 800594a:	6343      	str	r3, [r0, #52]	; 0x34
            if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
 800594c:	f7fe feda 	bl	8004704 <HAL_DMA_Abort_IT>
 8005950:	2800      	cmp	r0, #0
 8005952:	d044      	beq.n	80059de <HAL_UART_IRQHandler+0x13a>
              huart->hdmarx->XferAbortCallback(huart->hdmarx);
 8005954:	6b60      	ldr	r0, [r4, #52]	; 0x34
}
 8005956:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
              huart->hdmarx->XferAbortCallback(huart->hdmarx);
 800595a:	6b43      	ldr	r3, [r0, #52]	; 0x34
 800595c:	4718      	bx	r3
            HAL_UART_ErrorCallback(huart);
 800595e:	4620      	mov	r0, r4
 8005960:	f7ff ff78 	bl	8005854 <HAL_UART_ErrorCallback>
 8005964:	bd70      	pop	{r4, r5, r6, pc}
        HAL_UART_ErrorCallback(huart);
 8005966:	f7ff ff75 	bl	8005854 <HAL_UART_ErrorCallback>
        huart->ErrorCode = HAL_UART_ERROR_NONE;
 800596a:	63e5      	str	r5, [r4, #60]	; 0x3c
 800596c:	bd70      	pop	{r4, r5, r6, pc}
  if(((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
 800596e:	0616      	lsls	r6, r2, #24
 8005970:	d527      	bpl.n	80059c2 <HAL_UART_IRQHandler+0x11e>
 8005972:	060d      	lsls	r5, r1, #24
 8005974:	d525      	bpl.n	80059c2 <HAL_UART_IRQHandler+0x11e>
  if(huart->gState == HAL_UART_STATE_BUSY_TX)
 8005976:	f894 2039 	ldrb.w	r2, [r4, #57]	; 0x39
 800597a:	2a21      	cmp	r2, #33	; 0x21
 800597c:	d12f      	bne.n	80059de <HAL_UART_IRQHandler+0x13a>
    if(huart->Init.WordLength == UART_WORDLENGTH_9B)
 800597e:	68a2      	ldr	r2, [r4, #8]
 8005980:	f5b2 5f80 	cmp.w	r2, #4096	; 0x1000
 8005984:	6a22      	ldr	r2, [r4, #32]
 8005986:	d117      	bne.n	80059b8 <HAL_UART_IRQHandler+0x114>
      huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
 8005988:	8811      	ldrh	r1, [r2, #0]
 800598a:	f3c1 0108 	ubfx	r1, r1, #0, #9
 800598e:	6059      	str	r1, [r3, #4]
      if(huart->Init.Parity == UART_PARITY_NONE)
 8005990:	6921      	ldr	r1, [r4, #16]
 8005992:	b979      	cbnz	r1, 80059b4 <HAL_UART_IRQHandler+0x110>
        huart->pTxBuffPtr += 2U;
 8005994:	3202      	adds	r2, #2
        huart->pTxBuffPtr += 1U;
 8005996:	6222      	str	r2, [r4, #32]
    if(--huart->TxXferCount == 0U)
 8005998:	8ce2      	ldrh	r2, [r4, #38]	; 0x26
 800599a:	3a01      	subs	r2, #1
 800599c:	b292      	uxth	r2, r2
 800599e:	84e2      	strh	r2, [r4, #38]	; 0x26
 80059a0:	b9ea      	cbnz	r2, 80059de <HAL_UART_IRQHandler+0x13a>
      __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
 80059a2:	68da      	ldr	r2, [r3, #12]
 80059a4:	f022 0280 	bic.w	r2, r2, #128	; 0x80
 80059a8:	60da      	str	r2, [r3, #12]
      __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
 80059aa:	68da      	ldr	r2, [r3, #12]
 80059ac:	f042 0240 	orr.w	r2, r2, #64	; 0x40
 80059b0:	60da      	str	r2, [r3, #12]
 80059b2:	bd70      	pop	{r4, r5, r6, pc}
        huart->pTxBuffPtr += 1U;
 80059b4:	3201      	adds	r2, #1
 80059b6:	e7ee      	b.n	8005996 <HAL_UART_IRQHandler+0xf2>
      huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF);
 80059b8:	1c51      	adds	r1, r2, #1
 80059ba:	6221      	str	r1, [r4, #32]
 80059bc:	7812      	ldrb	r2, [r2, #0]
 80059be:	605a      	str	r2, [r3, #4]
 80059c0:	e7ea      	b.n	8005998 <HAL_UART_IRQHandler+0xf4>
  if(((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
 80059c2:	0650      	lsls	r0, r2, #25
 80059c4:	d50b      	bpl.n	80059de <HAL_UART_IRQHandler+0x13a>
 80059c6:	064a      	lsls	r2, r1, #25
 80059c8:	d509      	bpl.n	80059de <HAL_UART_IRQHandler+0x13a>
  __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
 80059ca:	68da      	ldr	r2, [r3, #12]
  HAL_UART_TxCpltCallback(huart);
 80059cc:	4620      	mov	r0, r4
  __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
 80059ce:	f022 0240 	bic.w	r2, r2, #64	; 0x40
 80059d2:	60da      	str	r2, [r3, #12]
  huart->gState = HAL_UART_STATE_READY;
 80059d4:	2320      	movs	r3, #32
 80059d6:	f884 3039 	strb.w	r3, [r4, #57]	; 0x39
  HAL_UART_TxCpltCallback(huart);
 80059da:	f000 fbd7 	bl	800618c <HAL_UART_TxCpltCallback>
 80059de:	bd70      	pop	{r4, r5, r6, pc}
 80059e0:	080059e5 	.word	0x080059e5

080059e4 <UART_DMAAbortOnError>:
{
 80059e4:	b508      	push	{r3, lr}
  huart->RxXferCount = 0x00U;
 80059e6:	2300      	movs	r3, #0
  UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
 80059e8:	6a40      	ldr	r0, [r0, #36]	; 0x24
  huart->RxXferCount = 0x00U;
 80059ea:	85c3      	strh	r3, [r0, #46]	; 0x2e
  huart->TxXferCount = 0x00U;
 80059ec:	84c3      	strh	r3, [r0, #38]	; 0x26
  HAL_UART_ErrorCallback(huart);
 80059ee:	f7ff ff31 	bl	8005854 <HAL_UART_ErrorCallback>
 80059f2:	bd08      	pop	{r3, pc}

080059f4 <STH30_CheckCrc>:
    }
  }
  return crc;
}
etError STH30_CheckCrc(uint8_t *data, uint8_t nbrOfBytes, uint8_t checksum)
{
 80059f4:	b530      	push	{r4, r5, lr}
  uint8_t bit;        // bit mask
  uint8_t crc = 0xFF; // calculated checksum
 80059f6:	23ff      	movs	r3, #255	; 0xff
  uint8_t byteCtr;    // byte counter

  // calculates 8-Bit checksum with given polynomial
  for(byteCtr = 0; byteCtr < nbrOfBytes; byteCtr++)
 80059f8:	4605      	mov	r5, r0
 80059fa:	1a2c      	subs	r4, r5, r0
 80059fc:	b2e4      	uxtb	r4, r4
 80059fe:	42a1      	cmp	r1, r4
 8005a00:	d803      	bhi.n	8005a0a <STH30_CheckCrc+0x16>
      else           crc = (crc << 1);
    }
  }
  if(crc != checksum) return CHECKSUM_ERROR;
  else                return NO_ERROR;
}
 8005a02:	1a9b      	subs	r3, r3, r2
 8005a04:	4258      	negs	r0, r3
 8005a06:	4158      	adcs	r0, r3
 8005a08:	bd30      	pop	{r4, r5, pc}
    crc ^= (data[byteCtr]);
 8005a0a:	f815 4b01 	ldrb.w	r4, [r5], #1
 8005a0e:	4063      	eors	r3, r4
 8005a10:	2408      	movs	r4, #8
      if(crc & 0x80) crc = (crc << 1) ^ POLYNOMIAL;
 8005a12:	f013 0f80 	tst.w	r3, #128	; 0x80
 8005a16:	f104 34ff 	add.w	r4, r4, #4294967295
 8005a1a:	ea4f 0343 	mov.w	r3, r3, lsl #1
 8005a1e:	bf18      	it	ne
 8005a20:	f083 0331 	eorne.w	r3, r3, #49	; 0x31
    for(bit = 8; bit > 0; --bit)
 8005a24:	f014 04ff 	ands.w	r4, r4, #255	; 0xff
      else           crc = (crc << 1);
 8005a28:	b2db      	uxtb	r3, r3
    for(bit = 8; bit > 0; --bit)
 8005a2a:	d1f2      	bne.n	8005a12 <STH30_CheckCrc+0x1e>
 8005a2c:	e7e5      	b.n	80059fa <STH30_CheckCrc+0x6>
	...

08005a30 <HAL_TIM_PeriodElapsedCallback>:
__IO uint32_t ADCvalue[ADC_EA];
#if 1 // PYJ.2019.07.26_BEGIN --

void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
    if(htim->Instance == TIM6){
 8005a30:	6802      	ldr	r2, [r0, #0]
 8005a32:	4b06      	ldr	r3, [pc, #24]	; (8005a4c <HAL_TIM_PeriodElapsedCallback+0x1c>)
 8005a34:	429a      	cmp	r2, r3
 8005a36:	d107      	bne.n	8005a48 <HAL_TIM_PeriodElapsedCallback+0x18>
        UartTimerCnt++;
 8005a38:	4a05      	ldr	r2, [pc, #20]	; (8005a50 <HAL_TIM_PeriodElapsedCallback+0x20>)
 8005a3a:	6813      	ldr	r3, [r2, #0]
 8005a3c:	3301      	adds	r3, #1
 8005a3e:	6013      	str	r3, [r2, #0]
        LedTimerCnt++;
 8005a40:	4a04      	ldr	r2, [pc, #16]	; (8005a54 <HAL_TIM_PeriodElapsedCallback+0x24>)
 8005a42:	6813      	ldr	r3, [r2, #0]
 8005a44:	3301      	adds	r3, #1
 8005a46:	6013      	str	r3, [r2, #0]
 8005a48:	4770      	bx	lr
 8005a4a:	bf00      	nop
 8005a4c:	40001000 	.word	0x40001000
 8005a50:	20000090 	.word	0x20000090
 8005a54:	2000008c 	.word	0x2000008c

08005a58 <_write>:
    }
} 
#endif // PYJ.2019.07.26_END -- 
int _write (int file, uint8_t *ptr, uint16_t len)
{
 8005a58:	b510      	push	{r4, lr}
 8005a5a:	4614      	mov	r4, r2
    HAL_UART_Transmit(&huart1, ptr, len,10);
 8005a5c:	230a      	movs	r3, #10
 8005a5e:	4802      	ldr	r0, [pc, #8]	; (8005a68 <_write+0x10>)
 8005a60:	f7ff fdd4 	bl	800560c <HAL_UART_Transmit>
    return len;
}
 8005a64:	4620      	mov	r0, r4
 8005a66:	bd10      	pop	{r4, pc}
 8005a68:	2000111c 	.word	0x2000111c

08005a6c <SystemClock_Config>:
/**
  * @brief System Clock Configuration
  * @retval None
  */
void SystemClock_Config(void)
{
 8005a6c:	b510      	push	{r4, lr}
 8005a6e:	b096      	sub	sp, #88	; 0x58
  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
 8005a70:	2228      	movs	r2, #40	; 0x28
 8005a72:	2100      	movs	r1, #0
 8005a74:	a80c      	add	r0, sp, #48	; 0x30
 8005a76:	f000 fcaf 	bl	80063d8 <memset>
  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 8005a7a:	2214      	movs	r2, #20
 8005a7c:	2100      	movs	r1, #0
 8005a7e:	a801      	add	r0, sp, #4
 8005a80:	f000 fcaa 	bl	80063d8 <memset>
  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 8005a84:	2218      	movs	r2, #24
 8005a86:	2100      	movs	r1, #0
 8005a88:	eb0d 0002 	add.w	r0, sp, r2
 8005a8c:	f000 fca4 	bl	80063d8 <memset>

  /** Initializes the CPU, AHB and APB busses clocks 
  */
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
 8005a90:	2301      	movs	r3, #1
 8005a92:	9310      	str	r3, [sp, #64]	; 0x40
  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
 8005a94:	2310      	movs	r3, #16
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
 8005a96:	2402      	movs	r4, #2
  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
 8005a98:	9311      	str	r3, [sp, #68]	; 0x44
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2;
  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL15;
 8005a9a:	f44f 1350 	mov.w	r3, #3407872	; 0x340000
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 8005a9e:	a80c      	add	r0, sp, #48	; 0x30
  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL15;
 8005aa0:	9315      	str	r3, [sp, #84]	; 0x54
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
 8005aa2:	940c      	str	r4, [sp, #48]	; 0x30
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
 8005aa4:	9413      	str	r4, [sp, #76]	; 0x4c
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 8005aa6:	f7ff f86d 	bl	8004b84 <HAL_RCC_OscConfig>
  {
    Error_Handler();
  }
  /** Initializes the CPU, AHB and APB busses clocks 
  */
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
 8005aaa:	230f      	movs	r3, #15
                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
 8005aac:	f44f 6280 	mov.w	r2, #1024	; 0x400
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
 8005ab0:	9301      	str	r3, [sp, #4]
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
 8005ab2:	2300      	movs	r3, #0
  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;

  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
 8005ab4:	4621      	mov	r1, r4
 8005ab6:	a801      	add	r0, sp, #4
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
 8005ab8:	9303      	str	r3, [sp, #12]
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
 8005aba:	9204      	str	r2, [sp, #16]
  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
 8005abc:	9305      	str	r3, [sp, #20]
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
 8005abe:	9402      	str	r4, [sp, #8]
  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
 8005ac0:	f7ff fa28 	bl	8004f14 <HAL_RCC_ClockConfig>
  {
    Error_Handler();
  }
  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
  PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6;
 8005ac4:	f44f 4300 	mov.w	r3, #32768	; 0x8000
  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
 8005ac8:	a806      	add	r0, sp, #24
  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
 8005aca:	9406      	str	r4, [sp, #24]
  PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6;
 8005acc:	9308      	str	r3, [sp, #32]
  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
 8005ace:	f7ff faf3 	bl	80050b8 <HAL_RCCEx_PeriphCLKConfig>
  {
    Error_Handler();
  }
}
 8005ad2:	b016      	add	sp, #88	; 0x58
 8005ad4:	bd10      	pop	{r4, pc}
	...

08005ad8 <main>:
{
 8005ad8:	b580      	push	{r7, lr}
static void MX_GPIO_Init(void)
{
  GPIO_InitTypeDef GPIO_InitStruct = {0};

  /* GPIO Ports Clock Enable */
  __HAL_RCC_GPIOE_CLK_ENABLE();
 8005ada:	4db4      	ldr	r5, [pc, #720]	; (8005dac <main+0x2d4>)
{
 8005adc:	b08c      	sub	sp, #48	; 0x30
  HAL_Init();
 8005ade:	f7fe fbc5 	bl	800426c <HAL_Init>
  SystemClock_Config();
 8005ae2:	f7ff ffc3 	bl	8005a6c <SystemClock_Config>
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8005ae6:	2210      	movs	r2, #16
 8005ae8:	2100      	movs	r1, #0
 8005aea:	a808      	add	r0, sp, #32
 8005aec:	f000 fc74 	bl	80063d8 <memset>
  __HAL_RCC_GPIOE_CLK_ENABLE();
 8005af0:	69ab      	ldr	r3, [r5, #24]
  __HAL_RCC_GPIOB_CLK_ENABLE();
  __HAL_RCC_GPIOD_CLK_ENABLE();
  __HAL_RCC_GPIOG_CLK_ENABLE();

  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(GPIOE, ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin 
 8005af2:	2200      	movs	r2, #0
  __HAL_RCC_GPIOE_CLK_ENABLE();
 8005af4:	f043 0340 	orr.w	r3, r3, #64	; 0x40
 8005af8:	61ab      	str	r3, [r5, #24]
 8005afa:	69ab      	ldr	r3, [r5, #24]
  HAL_GPIO_WritePin(GPIOE, ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin 
 8005afc:	217f      	movs	r1, #127	; 0x7f
  __HAL_RCC_GPIOE_CLK_ENABLE();
 8005afe:	f003 0340 	and.w	r3, r3, #64	; 0x40
 8005b02:	9301      	str	r3, [sp, #4]
 8005b04:	9b01      	ldr	r3, [sp, #4]
  __HAL_RCC_GPIOC_CLK_ENABLE();
 8005b06:	69ab      	ldr	r3, [r5, #24]
  HAL_GPIO_WritePin(GPIOE, ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin 
 8005b08:	48a9      	ldr	r0, [pc, #676]	; (8005db0 <main+0x2d8>)
  __HAL_RCC_GPIOC_CLK_ENABLE();
 8005b0a:	f043 0310 	orr.w	r3, r3, #16
 8005b0e:	61ab      	str	r3, [r5, #24]
 8005b10:	69ab      	ldr	r3, [r5, #24]
  /*Configure GPIO pins : ATT_EN_1_8G_DL1_Pin ATT_EN_1_8G_DL2_Pin ATT_EN_1_8G_UL1_Pin ATT_EN_1_8G_UL2_Pin 
                           ATT_EN_1_8G_UL3_Pin PATH_EN_2_1G_DL_Pin PATH_EN_2_1G_UL_Pin */
  GPIO_InitStruct.Pin = ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin 
                          |ATT_EN_1_8G_UL3_Pin|PATH_EN_2_1G_DL_Pin|PATH_EN_2_1G_UL_Pin;
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8005b12:	2400      	movs	r4, #0
  __HAL_RCC_GPIOC_CLK_ENABLE();
 8005b14:	f003 0310 	and.w	r3, r3, #16
 8005b18:	9302      	str	r3, [sp, #8]
 8005b1a:	9b02      	ldr	r3, [sp, #8]
  __HAL_RCC_GPIOF_CLK_ENABLE();
 8005b1c:	69ab      	ldr	r3, [r5, #24]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 8005b1e:	2601      	movs	r6, #1
  __HAL_RCC_GPIOF_CLK_ENABLE();
 8005b20:	f043 0380 	orr.w	r3, r3, #128	; 0x80
 8005b24:	61ab      	str	r3, [r5, #24]
 8005b26:	69ab      	ldr	r3, [r5, #24]
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8005b28:	2702      	movs	r7, #2
  __HAL_RCC_GPIOF_CLK_ENABLE();
 8005b2a:	f003 0380 	and.w	r3, r3, #128	; 0x80
 8005b2e:	9303      	str	r3, [sp, #12]
 8005b30:	9b03      	ldr	r3, [sp, #12]
  __HAL_RCC_GPIOA_CLK_ENABLE();
 8005b32:	69ab      	ldr	r3, [r5, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
  HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);

  /*Configure GPIO pins : PLL_LD_1_8G_DL_Pin PLL_LD_1_8G_UL_Pin */
  GPIO_InitStruct.Pin = PLL_LD_1_8G_DL_Pin|PLL_LD_1_8G_UL_Pin;
 8005b34:	f04f 080c 	mov.w	r8, #12
  __HAL_RCC_GPIOA_CLK_ENABLE();
 8005b38:	f043 0304 	orr.w	r3, r3, #4
 8005b3c:	61ab      	str	r3, [r5, #24]
 8005b3e:	69ab      	ldr	r3, [r5, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);

  /*Configure GPIO pin : PATH_EN_3_5G_H_Pin */
  GPIO_InitStruct.Pin = PATH_EN_3_5G_H_Pin;
  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
 8005b40:	f04f 0903 	mov.w	r9, #3
  __HAL_RCC_GPIOA_CLK_ENABLE();
 8005b44:	f003 0304 	and.w	r3, r3, #4
 8005b48:	9304      	str	r3, [sp, #16]
 8005b4a:	9b04      	ldr	r3, [sp, #16]
  __HAL_RCC_GPIOB_CLK_ENABLE();
 8005b4c:	69ab      	ldr	r3, [r5, #24]
  hadc1.Init.NbrOfConversion = 14;
 8005b4e:	f04f 0a0e 	mov.w	sl, #14
  __HAL_RCC_GPIOB_CLK_ENABLE();
 8005b52:	f043 0308 	orr.w	r3, r3, #8
 8005b56:	61ab      	str	r3, [r5, #24]
 8005b58:	69ab      	ldr	r3, [r5, #24]
 8005b5a:	f003 0308 	and.w	r3, r3, #8
 8005b5e:	9305      	str	r3, [sp, #20]
 8005b60:	9b05      	ldr	r3, [sp, #20]
  __HAL_RCC_GPIOD_CLK_ENABLE();
 8005b62:	69ab      	ldr	r3, [r5, #24]
 8005b64:	f043 0320 	orr.w	r3, r3, #32
 8005b68:	61ab      	str	r3, [r5, #24]
 8005b6a:	69ab      	ldr	r3, [r5, #24]
 8005b6c:	f003 0320 	and.w	r3, r3, #32
 8005b70:	9306      	str	r3, [sp, #24]
 8005b72:	9b06      	ldr	r3, [sp, #24]
  __HAL_RCC_GPIOG_CLK_ENABLE();
 8005b74:	69ab      	ldr	r3, [r5, #24]
 8005b76:	f443 7380 	orr.w	r3, r3, #256	; 0x100
 8005b7a:	61ab      	str	r3, [r5, #24]
 8005b7c:	69ab      	ldr	r3, [r5, #24]
 8005b7e:	f403 7380 	and.w	r3, r3, #256	; 0x100
 8005b82:	9307      	str	r3, [sp, #28]
 8005b84:	9b07      	ldr	r3, [sp, #28]
  HAL_GPIO_WritePin(GPIOE, ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin 
 8005b86:	f7fe fff3 	bl	8004b70 <HAL_GPIO_WritePin>
  HAL_GPIO_WritePin(GPIOC, ATT_EN_1_8G_UL4_Pin|PATH_EN_1_8G_DL_Pin|PATH_EN_1_8G_UL_Pin|PLL_EN_3_5G_L_Pin 
 8005b8a:	2200      	movs	r2, #0
 8005b8c:	f24e 01c0 	movw	r1, #57536	; 0xe0c0
 8005b90:	4888      	ldr	r0, [pc, #544]	; (8005db4 <main+0x2dc>)
 8005b92:	f7fe ffed 	bl	8004b70 <HAL_GPIO_WritePin>
  HAL_GPIO_WritePin(GPIOF, PLL_EN_1_8G_DL_Pin|PLL_EN_1_8G_UL_Pin|ATT_EN_2_1G_DL1_Pin|ATT_EN_2_1G_DL2_Pin 
 8005b96:	2200      	movs	r2, #0
 8005b98:	f240 31f3 	movw	r1, #1011	; 0x3f3
 8005b9c:	4886      	ldr	r0, [pc, #536]	; (8005db8 <main+0x2e0>)
 8005b9e:	f7fe ffe7 	bl	8004b70 <HAL_GPIO_WritePin>
  HAL_GPIO_WritePin(GPIOD, PLL_DATA_Pin|PLL_CLK_Pin|ATT_DATA_Pin|ATT_CLK_Pin 
 8005ba2:	2200      	movs	r2, #0
 8005ba4:	f648 71ff 	movw	r1, #36863	; 0x8fff
 8005ba8:	4884      	ldr	r0, [pc, #528]	; (8005dbc <main+0x2e4>)
 8005baa:	f7fe ffe1 	bl	8004b70 <HAL_GPIO_WritePin>
  HAL_GPIO_WritePin(GPIOG, DA_SYNC_Pin|DA_SCLK_Pin|DA_DIN_Pin|_T_SYNC_UL_Pin 
 8005bae:	2200      	movs	r2, #0
 8005bb0:	f647 51fc 	movw	r1, #32252	; 0x7dfc
 8005bb4:	4882      	ldr	r0, [pc, #520]	; (8005dc0 <main+0x2e8>)
 8005bb6:	f7fe ffdb 	bl	8004b70 <HAL_GPIO_WritePin>
  HAL_GPIO_WritePin(GPIOB, PLL_EN_2_1G_DL_Pin|PLL_EN_2_1G_UL_Pin, GPIO_PIN_RESET);
 8005bba:	2200      	movs	r2, #0
 8005bbc:	2118      	movs	r1, #24
 8005bbe:	4881      	ldr	r0, [pc, #516]	; (8005dc4 <main+0x2ec>)
 8005bc0:	f7fe ffd6 	bl	8004b70 <HAL_GPIO_WritePin>
  GPIO_InitStruct.Pin = ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin 
 8005bc4:	237f      	movs	r3, #127	; 0x7f
  HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
 8005bc6:	a908      	add	r1, sp, #32
 8005bc8:	4879      	ldr	r0, [pc, #484]	; (8005db0 <main+0x2d8>)
  GPIO_InitStruct.Pin = ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin 
 8005bca:	9308      	str	r3, [sp, #32]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 8005bcc:	9609      	str	r6, [sp, #36]	; 0x24
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8005bce:	970b      	str	r7, [sp, #44]	; 0x2c
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8005bd0:	940a      	str	r4, [sp, #40]	; 0x28
  HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
 8005bd2:	f7fe fee1 	bl	8004998 <HAL_GPIO_Init>
  GPIO_InitStruct.Pin = ATT_EN_1_8G_UL4_Pin|PATH_EN_1_8G_DL_Pin|PATH_EN_1_8G_UL_Pin|PLL_EN_3_5G_L_Pin 
 8005bd6:	f24e 03c0 	movw	r3, #57536	; 0xe0c0
  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 8005bda:	a908      	add	r1, sp, #32
 8005bdc:	4875      	ldr	r0, [pc, #468]	; (8005db4 <main+0x2dc>)
  GPIO_InitStruct.Pin = ATT_EN_1_8G_UL4_Pin|PATH_EN_1_8G_DL_Pin|PATH_EN_1_8G_UL_Pin|PLL_EN_3_5G_L_Pin 
 8005bde:	9308      	str	r3, [sp, #32]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 8005be0:	9609      	str	r6, [sp, #36]	; 0x24
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8005be2:	970b      	str	r7, [sp, #44]	; 0x2c
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8005be4:	940a      	str	r4, [sp, #40]	; 0x28
  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 8005be6:	f7fe fed7 	bl	8004998 <HAL_GPIO_Init>
  GPIO_InitStruct.Pin = PLL_EN_1_8G_DL_Pin|PLL_EN_1_8G_UL_Pin|ATT_EN_2_1G_DL1_Pin|ATT_EN_2_1G_DL2_Pin 
 8005bea:	f240 33f3 	movw	r3, #1011	; 0x3f3
  HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
 8005bee:	a908      	add	r1, sp, #32
 8005bf0:	4871      	ldr	r0, [pc, #452]	; (8005db8 <main+0x2e0>)
  GPIO_InitStruct.Pin = PLL_EN_1_8G_DL_Pin|PLL_EN_1_8G_UL_Pin|ATT_EN_2_1G_DL1_Pin|ATT_EN_2_1G_DL2_Pin 
 8005bf2:	9308      	str	r3, [sp, #32]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 8005bf4:	9609      	str	r6, [sp, #36]	; 0x24
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8005bf6:	970b      	str	r7, [sp, #44]	; 0x2c
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8005bf8:	940a      	str	r4, [sp, #40]	; 0x28
  HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
 8005bfa:	f7fe fecd 	bl	8004998 <HAL_GPIO_Init>
  HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
 8005bfe:	a908      	add	r1, sp, #32
 8005c00:	486d      	ldr	r0, [pc, #436]	; (8005db8 <main+0x2e0>)
  GPIO_InitStruct.Pin = PLL_LD_1_8G_DL_Pin|PLL_LD_1_8G_UL_Pin;
 8005c02:	f8cd 8020 	str.w	r8, [sp, #32]
  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
 8005c06:	9409      	str	r4, [sp, #36]	; 0x24
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8005c08:	940a      	str	r4, [sp, #40]	; 0x28
  HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
 8005c0a:	f7fe fec5 	bl	8004998 <HAL_GPIO_Init>
  GPIO_InitStruct.Pin = PLL_DATA_Pin|PLL_CLK_Pin|ATT_DATA_Pin|ATT_CLK_Pin 
 8005c0e:	f648 73ff 	movw	r3, #36863	; 0x8fff
  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
 8005c12:	a908      	add	r1, sp, #32
 8005c14:	4869      	ldr	r0, [pc, #420]	; (8005dbc <main+0x2e4>)
  GPIO_InitStruct.Pin = PLL_DATA_Pin|PLL_CLK_Pin|ATT_DATA_Pin|ATT_CLK_Pin 
 8005c16:	9308      	str	r3, [sp, #32]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 8005c18:	9609      	str	r6, [sp, #36]	; 0x24
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8005c1a:	970b      	str	r7, [sp, #44]	; 0x2c
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8005c1c:	940a      	str	r4, [sp, #40]	; 0x28
  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
 8005c1e:	f7fe febb 	bl	8004998 <HAL_GPIO_Init>
  GPIO_InitStruct.Pin = ALARM_DC_Pin|ALARM_AC_Pin;
 8005c22:	f44f 5340 	mov.w	r3, #12288	; 0x3000
  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
 8005c26:	a908      	add	r1, sp, #32
 8005c28:	4864      	ldr	r0, [pc, #400]	; (8005dbc <main+0x2e4>)
  GPIO_InitStruct.Pin = ALARM_DC_Pin|ALARM_AC_Pin;
 8005c2a:	9308      	str	r3, [sp, #32]
  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
 8005c2c:	9409      	str	r4, [sp, #36]	; 0x24
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8005c2e:	940a      	str	r4, [sp, #40]	; 0x28
  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
 8005c30:	f7fe feb2 	bl	8004998 <HAL_GPIO_Init>
  GPIO_InitStruct.Pin = DA_SYNC_Pin|DA_SCLK_Pin|DA_DIN_Pin|_T_SYNC_UL_Pin 
 8005c34:	f647 53fc 	movw	r3, #32252	; 0x7dfc
  HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
 8005c38:	a908      	add	r1, sp, #32
 8005c3a:	4861      	ldr	r0, [pc, #388]	; (8005dc0 <main+0x2e8>)
  GPIO_InitStruct.Pin = DA_SYNC_Pin|DA_SCLK_Pin|DA_DIN_Pin|_T_SYNC_UL_Pin 
 8005c3c:	9308      	str	r3, [sp, #32]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 8005c3e:	9609      	str	r6, [sp, #36]	; 0x24
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8005c40:	970b      	str	r7, [sp, #44]	; 0x2c
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8005c42:	940a      	str	r4, [sp, #40]	; 0x28
  HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
 8005c44:	f7fe fea8 	bl	8004998 <HAL_GPIO_Init>
  GPIO_InitStruct.Pin = PLL_LD_3_5G_L_Pin|PLL_LD_3_5G_H_Pin;
 8005c48:	f44f 7340 	mov.w	r3, #768	; 0x300
  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 8005c4c:	a908      	add	r1, sp, #32
 8005c4e:	4859      	ldr	r0, [pc, #356]	; (8005db4 <main+0x2dc>)
  GPIO_InitStruct.Pin = PLL_LD_3_5G_L_Pin|PLL_LD_3_5G_H_Pin;
 8005c50:	9308      	str	r3, [sp, #32]
  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
 8005c52:	9409      	str	r4, [sp, #36]	; 0x24
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8005c54:	940a      	str	r4, [sp, #40]	; 0x28
  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 8005c56:	f7fe fe9f 	bl	8004998 <HAL_GPIO_Init>
  GPIO_InitStruct.Pin = PATH_EN_3_5G_H_Pin;
 8005c5a:	f44f 7300 	mov.w	r3, #512	; 0x200
  HAL_GPIO_Init(PATH_EN_3_5G_H_GPIO_Port, &GPIO_InitStruct);
 8005c5e:	a908      	add	r1, sp, #32
 8005c60:	4857      	ldr	r0, [pc, #348]	; (8005dc0 <main+0x2e8>)
  GPIO_InitStruct.Pin = PATH_EN_3_5G_H_Pin;
 8005c62:	9308      	str	r3, [sp, #32]
  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
 8005c64:	f8cd 9024 	str.w	r9, [sp, #36]	; 0x24
  HAL_GPIO_Init(PATH_EN_3_5G_H_GPIO_Port, &GPIO_InitStruct);
 8005c68:	f7fe fe96 	bl	8004998 <HAL_GPIO_Init>

  /*Configure GPIO pins : PLL_EN_2_1G_DL_Pin PLL_EN_2_1G_UL_Pin */
  GPIO_InitStruct.Pin = PLL_EN_2_1G_DL_Pin|PLL_EN_2_1G_UL_Pin;
 8005c6c:	2318      	movs	r3, #24
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  GPIO_InitStruct.Pull = GPIO_NOPULL;
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8005c6e:	a908      	add	r1, sp, #32
 8005c70:	4854      	ldr	r0, [pc, #336]	; (8005dc4 <main+0x2ec>)
  GPIO_InitStruct.Pin = PLL_EN_2_1G_DL_Pin|PLL_EN_2_1G_UL_Pin;
 8005c72:	9308      	str	r3, [sp, #32]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 8005c74:	9609      	str	r6, [sp, #36]	; 0x24
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8005c76:	970b      	str	r7, [sp, #44]	; 0x2c
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8005c78:	940a      	str	r4, [sp, #40]	; 0x28
  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8005c7a:	f7fe fe8d 	bl	8004998 <HAL_GPIO_Init>

  /*Configure GPIO pins : PLL_LD_2_1G_DL_Pin PLL_LD_2_1G_UL_Pin */
  GPIO_InitStruct.Pin = PLL_LD_2_1G_DL_Pin|PLL_LD_2_1G_UL_Pin;
 8005c7e:	2360      	movs	r3, #96	; 0x60
  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
  GPIO_InitStruct.Pull = GPIO_NOPULL;
  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8005c80:	a908      	add	r1, sp, #32
 8005c82:	4850      	ldr	r0, [pc, #320]	; (8005dc4 <main+0x2ec>)
  GPIO_InitStruct.Pin = PLL_LD_2_1G_DL_Pin|PLL_LD_2_1G_UL_Pin;
 8005c84:	9308      	str	r3, [sp, #32]
  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
 8005c86:	9409      	str	r4, [sp, #36]	; 0x24
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8005c88:	940a      	str	r4, [sp, #40]	; 0x28
  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8005c8a:	f7fe fe85 	bl	8004998 <HAL_GPIO_Init>
  __HAL_RCC_DMA1_CLK_ENABLE();
 8005c8e:	696b      	ldr	r3, [r5, #20]
  HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
 8005c90:	4622      	mov	r2, r4
  __HAL_RCC_DMA1_CLK_ENABLE();
 8005c92:	4333      	orrs	r3, r6
 8005c94:	616b      	str	r3, [r5, #20]
 8005c96:	696b      	ldr	r3, [r5, #20]
  HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
 8005c98:	4621      	mov	r1, r4
  __HAL_RCC_DMA1_CLK_ENABLE();
 8005c9a:	4033      	ands	r3, r6
 8005c9c:	9300      	str	r3, [sp, #0]
  HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
 8005c9e:	200b      	movs	r0, #11
  __HAL_RCC_DMA1_CLK_ENABLE();
 8005ca0:	9b00      	ldr	r3, [sp, #0]
  HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
 8005ca2:	f7fe fc5b 	bl	800455c <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
 8005ca6:	200b      	movs	r0, #11
 8005ca8:	f7fe fc8c 	bl	80045c4 <HAL_NVIC_EnableIRQ>
  HAL_NVIC_SetPriority(DMA1_Channel5_IRQn, 0, 0);
 8005cac:	4622      	mov	r2, r4
 8005cae:	4621      	mov	r1, r4
 8005cb0:	200f      	movs	r0, #15
 8005cb2:	f7fe fc53 	bl	800455c <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(DMA1_Channel5_IRQn);
 8005cb6:	200f      	movs	r0, #15
  hadc1.Instance = ADC1;
 8005cb8:	4d43      	ldr	r5, [pc, #268]	; (8005dc8 <main+0x2f0>)
  HAL_NVIC_EnableIRQ(DMA1_Channel5_IRQn);
 8005cba:	f7fe fc83 	bl	80045c4 <HAL_NVIC_EnableIRQ>
  hadc1.Instance = ADC1;
 8005cbe:	4b43      	ldr	r3, [pc, #268]	; (8005dcc <main+0x2f4>)
  if (HAL_ADC_Init(&hadc1) != HAL_OK)
 8005cc0:	4628      	mov	r0, r5
  hadc1.Instance = ADC1;
 8005cc2:	602b      	str	r3, [r5, #0]
  hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE;
 8005cc4:	f44f 7380 	mov.w	r3, #256	; 0x100
 8005cc8:	60ab      	str	r3, [r5, #8]
  hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
 8005cca:	f44f 2360 	mov.w	r3, #917504	; 0xe0000
  hadc1.Init.ContinuousConvMode = ENABLE;
 8005cce:	60ee      	str	r6, [r5, #12]
  hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
 8005cd0:	61eb      	str	r3, [r5, #28]
  hadc1.Init.DiscontinuousConvMode = DISABLE;
 8005cd2:	616c      	str	r4, [r5, #20]
  hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
 8005cd4:	606c      	str	r4, [r5, #4]
  hadc1.Init.NbrOfConversion = 14;
 8005cd6:	f8c5 a010 	str.w	sl, [r5, #16]
  ADC_ChannelConfTypeDef sConfig = {0};
 8005cda:	9408      	str	r4, [sp, #32]
 8005cdc:	9409      	str	r4, [sp, #36]	; 0x24
 8005cde:	940a      	str	r4, [sp, #40]	; 0x28
  if (HAL_ADC_Init(&hadc1) != HAL_OK)
 8005ce0:	f7fe fba0 	bl	8004424 <HAL_ADC_Init>
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005ce4:	a908      	add	r1, sp, #32
 8005ce6:	4628      	mov	r0, r5
  sConfig.Rank = ADC_REGULAR_RANK_1;
 8005ce8:	9609      	str	r6, [sp, #36]	; 0x24
  sConfig.Channel = ADC_CHANNEL_0;
 8005cea:	9408      	str	r4, [sp, #32]
  sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
 8005cec:	940a      	str	r4, [sp, #40]	; 0x28
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005cee:	f7fe faf3 	bl	80042d8 <HAL_ADC_ConfigChannel>
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005cf2:	a908      	add	r1, sp, #32
 8005cf4:	4628      	mov	r0, r5
  sConfig.Rank = ADC_REGULAR_RANK_2;
 8005cf6:	9709      	str	r7, [sp, #36]	; 0x24
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005cf8:	f7fe faee 	bl	80042d8 <HAL_ADC_ConfigChannel>
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005cfc:	a908      	add	r1, sp, #32
 8005cfe:	4628      	mov	r0, r5
  sConfig.Rank = ADC_REGULAR_RANK_3;
 8005d00:	f8cd 9024 	str.w	r9, [sp, #36]	; 0x24
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005d04:	f7fe fae8 	bl	80042d8 <HAL_ADC_ConfigChannel>
  sConfig.Rank = ADC_REGULAR_RANK_4;
 8005d08:	2304      	movs	r3, #4
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005d0a:	a908      	add	r1, sp, #32
 8005d0c:	4628      	mov	r0, r5
  sConfig.Rank = ADC_REGULAR_RANK_4;
 8005d0e:	9309      	str	r3, [sp, #36]	; 0x24
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005d10:	f7fe fae2 	bl	80042d8 <HAL_ADC_ConfigChannel>
  sConfig.Rank = ADC_REGULAR_RANK_5;
 8005d14:	2305      	movs	r3, #5
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005d16:	a908      	add	r1, sp, #32
 8005d18:	4628      	mov	r0, r5
  sConfig.Rank = ADC_REGULAR_RANK_5;
 8005d1a:	9309      	str	r3, [sp, #36]	; 0x24
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005d1c:	f7fe fadc 	bl	80042d8 <HAL_ADC_ConfigChannel>
  sConfig.Rank = ADC_REGULAR_RANK_6;
 8005d20:	2306      	movs	r3, #6
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005d22:	a908      	add	r1, sp, #32
 8005d24:	4628      	mov	r0, r5
  sConfig.Rank = ADC_REGULAR_RANK_6;
 8005d26:	9309      	str	r3, [sp, #36]	; 0x24
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005d28:	f7fe fad6 	bl	80042d8 <HAL_ADC_ConfigChannel>
  sConfig.Rank = ADC_REGULAR_RANK_7;
 8005d2c:	2307      	movs	r3, #7
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005d2e:	a908      	add	r1, sp, #32
 8005d30:	4628      	mov	r0, r5
  sConfig.Rank = ADC_REGULAR_RANK_7;
 8005d32:	9309      	str	r3, [sp, #36]	; 0x24
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005d34:	f7fe fad0 	bl	80042d8 <HAL_ADC_ConfigChannel>
  sConfig.Rank = ADC_REGULAR_RANK_8;
 8005d38:	2308      	movs	r3, #8
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005d3a:	a908      	add	r1, sp, #32
 8005d3c:	4628      	mov	r0, r5
  sConfig.Rank = ADC_REGULAR_RANK_8;
 8005d3e:	9309      	str	r3, [sp, #36]	; 0x24
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005d40:	f7fe faca 	bl	80042d8 <HAL_ADC_ConfigChannel>
  sConfig.Rank = ADC_REGULAR_RANK_9;
 8005d44:	2309      	movs	r3, #9
  sConfig.Rank = ADC_REGULAR_RANK_10;
 8005d46:	f04f 090a 	mov.w	r9, #10
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005d4a:	a908      	add	r1, sp, #32
 8005d4c:	4628      	mov	r0, r5
  sConfig.Rank = ADC_REGULAR_RANK_9;
 8005d4e:	9309      	str	r3, [sp, #36]	; 0x24
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005d50:	f7fe fac2 	bl	80042d8 <HAL_ADC_ConfigChannel>
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005d54:	a908      	add	r1, sp, #32
 8005d56:	4628      	mov	r0, r5
  sConfig.Rank = ADC_REGULAR_RANK_10;
 8005d58:	f8cd 9024 	str.w	r9, [sp, #36]	; 0x24
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005d5c:	f7fe fabc 	bl	80042d8 <HAL_ADC_ConfigChannel>
  sConfig.Rank = ADC_REGULAR_RANK_11;
 8005d60:	230b      	movs	r3, #11
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005d62:	a908      	add	r1, sp, #32
 8005d64:	4628      	mov	r0, r5
  sConfig.Rank = ADC_REGULAR_RANK_11;
 8005d66:	9309      	str	r3, [sp, #36]	; 0x24
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005d68:	f7fe fab6 	bl	80042d8 <HAL_ADC_ConfigChannel>
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005d6c:	a908      	add	r1, sp, #32
 8005d6e:	4628      	mov	r0, r5
  sConfig.Rank = ADC_REGULAR_RANK_12;
 8005d70:	f8cd 8024 	str.w	r8, [sp, #36]	; 0x24
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005d74:	f7fe fab0 	bl	80042d8 <HAL_ADC_ConfigChannel>
  sConfig.Rank = ADC_REGULAR_RANK_13;
 8005d78:	230d      	movs	r3, #13
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005d7a:	a908      	add	r1, sp, #32
 8005d7c:	4628      	mov	r0, r5
  sConfig.Rank = ADC_REGULAR_RANK_13;
 8005d7e:	9309      	str	r3, [sp, #36]	; 0x24
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005d80:	f7fe faaa 	bl	80042d8 <HAL_ADC_ConfigChannel>
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005d84:	a908      	add	r1, sp, #32
 8005d86:	4628      	mov	r0, r5
  sConfig.Rank = ADC_REGULAR_RANK_14;
 8005d88:	f8cd a024 	str.w	sl, [sp, #36]	; 0x24
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005d8c:	f7fe faa4 	bl	80042d8 <HAL_ADC_ConfigChannel>
  huart1.Init.BaudRate = 115200;
 8005d90:	f44f 33e1 	mov.w	r3, #115200	; 0x1c200
  huart1.Instance = USART1;
 8005d94:	4d0e      	ldr	r5, [pc, #56]	; (8005dd0 <main+0x2f8>)
  huart1.Init.BaudRate = 115200;
 8005d96:	4a0f      	ldr	r2, [pc, #60]	; (8005dd4 <main+0x2fc>)
  if (HAL_UART_Init(&huart1) != HAL_OK)
 8005d98:	4628      	mov	r0, r5
  huart1.Init.BaudRate = 115200;
 8005d9a:	e885 000c 	stmia.w	r5, {r2, r3}
  huart1.Init.WordLength = UART_WORDLENGTH_8B;
 8005d9e:	60ac      	str	r4, [r5, #8]
  huart1.Init.StopBits = UART_STOPBITS_1;
 8005da0:	60ec      	str	r4, [r5, #12]
  huart1.Init.Parity = UART_PARITY_NONE;
 8005da2:	612c      	str	r4, [r5, #16]
  huart1.Init.Mode = UART_MODE_TX_RX;
 8005da4:	f8c5 8014 	str.w	r8, [r5, #20]
 8005da8:	e016      	b.n	8005dd8 <main+0x300>
 8005daa:	bf00      	nop
 8005dac:	40021000 	.word	0x40021000
 8005db0:	40011800 	.word	0x40011800
 8005db4:	40011000 	.word	0x40011000
 8005db8:	40011c00 	.word	0x40011c00
 8005dbc:	40011400 	.word	0x40011400
 8005dc0:	40012000 	.word	0x40012000
 8005dc4:	40010c00 	.word	0x40010c00
 8005dc8:	200010a8 	.word	0x200010a8
 8005dcc:	40012400 	.word	0x40012400
 8005dd0:	2000111c 	.word	0x2000111c
 8005dd4:	40013800 	.word	0x40013800
  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
 8005dd8:	61ac      	str	r4, [r5, #24]
  huart1.Init.OverSampling = UART_OVERSAMPLING_16;
 8005dda:	61ec      	str	r4, [r5, #28]
  if (HAL_UART_Init(&huart1) != HAL_OK)
 8005ddc:	f7ff fbe8 	bl	80055b0 <HAL_UART_Init>
  htim6.Init.Prescaler = 6000-1;
 8005de0:	f241 736f 	movw	r3, #5999	; 0x176f
  htim6.Instance = TIM6;
 8005de4:	4f25      	ldr	r7, [pc, #148]	; (8005e7c <main+0x3a4>)
  htim6.Init.Prescaler = 6000-1;
 8005de6:	4926      	ldr	r1, [pc, #152]	; (8005e80 <main+0x3a8>)
  if (HAL_TIM_Base_Init(&htim6) != HAL_OK)
 8005de8:	4638      	mov	r0, r7
  htim6.Init.Prescaler = 6000-1;
 8005dea:	e887 000a 	stmia.w	r7, {r1, r3}
  TIM_MasterConfigTypeDef sMasterConfig = {0};
 8005dee:	9408      	str	r4, [sp, #32]
 8005df0:	9409      	str	r4, [sp, #36]	; 0x24
  htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
 8005df2:	60bc      	str	r4, [r7, #8]
  htim6.Init.Period = 10;
 8005df4:	f8c7 900c 	str.w	r9, [r7, #12]
  htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
 8005df8:	61bc      	str	r4, [r7, #24]
  if (HAL_TIM_Base_Init(&htim6) != HAL_OK)
 8005dfa:	f7ff fac7 	bl	800538c <HAL_TIM_Base_Init>
  if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK)
 8005dfe:	a908      	add	r1, sp, #32
 8005e00:	4638      	mov	r0, r7
  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
 8005e02:	9408      	str	r4, [sp, #32]
  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
 8005e04:	9409      	str	r4, [sp, #36]	; 0x24
  if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK)
 8005e06:	f7ff fadb 	bl	80053c0 <HAL_TIMEx_MasterConfigSynchronization>
  HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
 8005e0a:	4622      	mov	r2, r4
 8005e0c:	4621      	mov	r1, r4
 8005e0e:	2025      	movs	r0, #37	; 0x25
 8005e10:	f7fe fba4 	bl	800455c <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(USART1_IRQn);
 8005e14:	2025      	movs	r0, #37	; 0x25
 8005e16:	f7fe fbd5 	bl	80045c4 <HAL_NVIC_EnableIRQ>
  HAL_NVIC_SetPriority(TIM6_IRQn, 0, 0);
 8005e1a:	4622      	mov	r2, r4
 8005e1c:	4621      	mov	r1, r4
 8005e1e:	2036      	movs	r0, #54	; 0x36
 8005e20:	f7fe fb9c 	bl	800455c <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(TIM6_IRQn);
 8005e24:	2036      	movs	r0, #54	; 0x36
 8005e26:	f7fe fbcd 	bl	80045c4 <HAL_NVIC_EnableIRQ>
  setbuf(stdout, NULL);
 8005e2a:	4b16      	ldr	r3, [pc, #88]	; (8005e84 <main+0x3ac>)
 8005e2c:	4621      	mov	r1, r4
 8005e2e:	681b      	ldr	r3, [r3, #0]
 8005e30:	6898      	ldr	r0, [r3, #8]
 8005e32:	f000 fb69 	bl	8006508 <setbuf>
  printf("UART Start \r\n");
 8005e36:	4814      	ldr	r0, [pc, #80]	; (8005e88 <main+0x3b0>)
 8005e38:	f000 fb5e 	bl	80064f8 <puts>
  HAL_UART_Receive_DMA(&huart1, &TerminalQueue.Buffer[0], 1);
 8005e3c:	4632      	mov	r2, r6
 8005e3e:	4628      	mov	r0, r5
 8005e40:	4912      	ldr	r1, [pc, #72]	; (8005e8c <main+0x3b4>)
 8005e42:	f7ff fc5f 	bl	8005704 <HAL_UART_Receive_DMA>
    if(LedTimerCnt > 500){HAL_GPIO_TogglePin(BOOT_LED_GPIO_Port,GPIO_PIN_14);LedTimerCnt = 0;}
 8005e46:	4e12      	ldr	r6, [pc, #72]	; (8005e90 <main+0x3b8>)
    while (TerminalQueue.data > 0 && UartTimerCnt > 100) GetDataFromUartQueue(&hTerminal);
 8005e48:	4d12      	ldr	r5, [pc, #72]	; (8005e94 <main+0x3bc>)
    if(LedTimerCnt > 500){HAL_GPIO_TogglePin(BOOT_LED_GPIO_Port,GPIO_PIN_14);LedTimerCnt = 0;}
 8005e4a:	4c13      	ldr	r4, [pc, #76]	; (8005e98 <main+0x3c0>)
 8005e4c:	6823      	ldr	r3, [r4, #0]
 8005e4e:	f5b3 7ffa 	cmp.w	r3, #500	; 0x1f4
 8005e52:	d906      	bls.n	8005e62 <main+0x38a>
 8005e54:	f44f 4180 	mov.w	r1, #16384	; 0x4000
 8005e58:	4630      	mov	r0, r6
 8005e5a:	f7fe fe8e 	bl	8004b7a <HAL_GPIO_TogglePin>
 8005e5e:	2300      	movs	r3, #0
 8005e60:	6023      	str	r3, [r4, #0]
    while (TerminalQueue.data > 0 && UartTimerCnt > 100) GetDataFromUartQueue(&hTerminal);
 8005e62:	4c0e      	ldr	r4, [pc, #56]	; (8005e9c <main+0x3c4>)
 8005e64:	4f0e      	ldr	r7, [pc, #56]	; (8005ea0 <main+0x3c8>)
 8005e66:	68a3      	ldr	r3, [r4, #8]
 8005e68:	2b00      	cmp	r3, #0
 8005e6a:	ddee      	ble.n	8005e4a <main+0x372>
 8005e6c:	682b      	ldr	r3, [r5, #0]
 8005e6e:	2b64      	cmp	r3, #100	; 0x64
 8005e70:	d9eb      	bls.n	8005e4a <main+0x372>
 8005e72:	4638      	mov	r0, r7
 8005e74:	f000 f9ca 	bl	800620c <GetDataFromUartQueue>
 8005e78:	e7f5      	b.n	8005e66 <main+0x38e>
 8005e7a:	bf00      	nop
 8005e7c:	200011a0 	.word	0x200011a0
 8005e80:	40001000 	.word	0x40001000
 8005e84:	2000000c 	.word	0x2000000c
 8005e88:	080074f0 	.word	0x080074f0
 8005e8c:	20001224 	.word	0x20001224
 8005e90:	40012000 	.word	0x40012000
 8005e94:	20000090 	.word	0x20000090
 8005e98:	2000008c 	.word	0x2000008c
 8005e9c:	20001218 	.word	0x20001218
 8005ea0:	2000111c 	.word	0x2000111c

08005ea4 <Error_Handler>:
/**
  * @brief  This function is executed in case of error occurrence.
  * @retval None
  */
void Error_Handler(void)
{
 8005ea4:	4770      	bx	lr
	...

08005ea8 <HAL_MspInit>:
{
  /* USER CODE BEGIN MspInit 0 */

  /* USER CODE END MspInit 0 */

  __HAL_RCC_AFIO_CLK_ENABLE();
 8005ea8:	4b0e      	ldr	r3, [pc, #56]	; (8005ee4 <HAL_MspInit+0x3c>)
{
 8005eaa:	b082      	sub	sp, #8
  __HAL_RCC_AFIO_CLK_ENABLE();
 8005eac:	699a      	ldr	r2, [r3, #24]
 8005eae:	f042 0201 	orr.w	r2, r2, #1
 8005eb2:	619a      	str	r2, [r3, #24]
 8005eb4:	699a      	ldr	r2, [r3, #24]
 8005eb6:	f002 0201 	and.w	r2, r2, #1
 8005eba:	9200      	str	r2, [sp, #0]
 8005ebc:	9a00      	ldr	r2, [sp, #0]
  __HAL_RCC_PWR_CLK_ENABLE();
 8005ebe:	69da      	ldr	r2, [r3, #28]
 8005ec0:	f042 5280 	orr.w	r2, r2, #268435456	; 0x10000000
 8005ec4:	61da      	str	r2, [r3, #28]
 8005ec6:	69db      	ldr	r3, [r3, #28]

  /* System interrupt init*/

  /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled 
  */
  __HAL_AFIO_REMAP_SWJ_NOJTAG();
 8005ec8:	4a07      	ldr	r2, [pc, #28]	; (8005ee8 <HAL_MspInit+0x40>)
  __HAL_RCC_PWR_CLK_ENABLE();
 8005eca:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8005ece:	9301      	str	r3, [sp, #4]
 8005ed0:	9b01      	ldr	r3, [sp, #4]
  __HAL_AFIO_REMAP_SWJ_NOJTAG();
 8005ed2:	6853      	ldr	r3, [r2, #4]
 8005ed4:	f023 63e0 	bic.w	r3, r3, #117440512	; 0x7000000
 8005ed8:	f043 7300 	orr.w	r3, r3, #33554432	; 0x2000000
 8005edc:	6053      	str	r3, [r2, #4]

  /* USER CODE BEGIN MspInit 1 */

  /* USER CODE END MspInit 1 */
}
 8005ede:	b002      	add	sp, #8
 8005ee0:	4770      	bx	lr
 8005ee2:	bf00      	nop
 8005ee4:	40021000 	.word	0x40021000
 8005ee8:	40010000 	.word	0x40010000

08005eec <HAL_ADC_MspInit>:
* @param hadc: ADC handle pointer
* @retval None
*/
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
{
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8005eec:	2210      	movs	r2, #16
{
 8005eee:	b530      	push	{r4, r5, lr}
 8005ef0:	4605      	mov	r5, r0
 8005ef2:	b089      	sub	sp, #36	; 0x24
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8005ef4:	eb0d 0002 	add.w	r0, sp, r2
 8005ef8:	2100      	movs	r1, #0
 8005efa:	f000 fa6d 	bl	80063d8 <memset>
  if(hadc->Instance==ADC1)
 8005efe:	682a      	ldr	r2, [r5, #0]
 8005f00:	4b2b      	ldr	r3, [pc, #172]	; (8005fb0 <HAL_ADC_MspInit+0xc4>)
 8005f02:	429a      	cmp	r2, r3
 8005f04:	d152      	bne.n	8005fac <HAL_ADC_MspInit+0xc0>
  {
  /* USER CODE BEGIN ADC1_MspInit 0 */

  /* USER CODE END ADC1_MspInit 0 */
    /* Peripheral clock enable */
    __HAL_RCC_ADC1_CLK_ENABLE();
 8005f06:	f503 436c 	add.w	r3, r3, #60416	; 0xec00
 8005f0a:	699a      	ldr	r2, [r3, #24]
    PA7     ------> ADC1_IN7
    PB0     ------> ADC1_IN8
    PB1     ------> ADC1_IN9 
    */
    GPIO_InitStruct.Pin = DET_3_5G_UL_IN_Pin|DET_3_5G_UL_OUT_Pin|RFU_TEMP_Pin|_28V_DET_Pin;
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
 8005f0c:	2403      	movs	r4, #3
    __HAL_RCC_ADC1_CLK_ENABLE();
 8005f0e:	f442 7200 	orr.w	r2, r2, #512	; 0x200
 8005f12:	619a      	str	r2, [r3, #24]
 8005f14:	699a      	ldr	r2, [r3, #24]
    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 8005f16:	a904      	add	r1, sp, #16
    __HAL_RCC_ADC1_CLK_ENABLE();
 8005f18:	f402 7200 	and.w	r2, r2, #512	; 0x200
 8005f1c:	9200      	str	r2, [sp, #0]
 8005f1e:	9a00      	ldr	r2, [sp, #0]
    __HAL_RCC_GPIOC_CLK_ENABLE();
 8005f20:	699a      	ldr	r2, [r3, #24]
    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 8005f22:	4824      	ldr	r0, [pc, #144]	; (8005fb4 <HAL_ADC_MspInit+0xc8>)
    __HAL_RCC_GPIOC_CLK_ENABLE();
 8005f24:	f042 0210 	orr.w	r2, r2, #16
 8005f28:	619a      	str	r2, [r3, #24]
 8005f2a:	699a      	ldr	r2, [r3, #24]
 8005f2c:	f002 0210 	and.w	r2, r2, #16
 8005f30:	9201      	str	r2, [sp, #4]
 8005f32:	9a01      	ldr	r2, [sp, #4]
    __HAL_RCC_GPIOA_CLK_ENABLE();
 8005f34:	699a      	ldr	r2, [r3, #24]
 8005f36:	f042 0204 	orr.w	r2, r2, #4
 8005f3a:	619a      	str	r2, [r3, #24]
 8005f3c:	699a      	ldr	r2, [r3, #24]
 8005f3e:	f002 0204 	and.w	r2, r2, #4
 8005f42:	9202      	str	r2, [sp, #8]
 8005f44:	9a02      	ldr	r2, [sp, #8]
    __HAL_RCC_GPIOB_CLK_ENABLE();
 8005f46:	699a      	ldr	r2, [r3, #24]
 8005f48:	f042 0208 	orr.w	r2, r2, #8
 8005f4c:	619a      	str	r2, [r3, #24]
 8005f4e:	699b      	ldr	r3, [r3, #24]
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
 8005f50:	9405      	str	r4, [sp, #20]
    __HAL_RCC_GPIOB_CLK_ENABLE();
 8005f52:	f003 0308 	and.w	r3, r3, #8
 8005f56:	9303      	str	r3, [sp, #12]
 8005f58:	9b03      	ldr	r3, [sp, #12]
    GPIO_InitStruct.Pin = DET_3_5G_UL_IN_Pin|DET_3_5G_UL_OUT_Pin|RFU_TEMP_Pin|_28V_DET_Pin;
 8005f5a:	230f      	movs	r3, #15
 8005f5c:	9304      	str	r3, [sp, #16]
    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 8005f5e:	f7fe fd1b 	bl	8004998 <HAL_GPIO_Init>

    GPIO_InitStruct.Pin = DET_1_8G_DL_IN_Pin|DET_1_8G_DL_OUT_Pin|DET_1_8G_UL_IN_Pin|DET_1_8G_UL_OUT_Pin 
 8005f62:	23ff      	movs	r3, #255	; 0xff
                          |DET_2_1G_DL_IN_Pin|DET_2_1G_DL_OUT_Pin|DET_2_1G_UL_IN_Pin|DET_2_1G_UL_OUT_Pin;
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8005f64:	a904      	add	r1, sp, #16
 8005f66:	4814      	ldr	r0, [pc, #80]	; (8005fb8 <HAL_ADC_MspInit+0xcc>)
    GPIO_InitStruct.Pin = DET_1_8G_DL_IN_Pin|DET_1_8G_DL_OUT_Pin|DET_1_8G_UL_IN_Pin|DET_1_8G_UL_OUT_Pin 
 8005f68:	9304      	str	r3, [sp, #16]
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
 8005f6a:	9405      	str	r4, [sp, #20]
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8005f6c:	f7fe fd14 	bl	8004998 <HAL_GPIO_Init>

    GPIO_InitStruct.Pin = DET_3_5G_DL_IN_Pin|DET_3_5G_DL_OUT_Pin;
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8005f70:	4812      	ldr	r0, [pc, #72]	; (8005fbc <HAL_ADC_MspInit+0xd0>)
 8005f72:	a904      	add	r1, sp, #16
    GPIO_InitStruct.Pin = DET_3_5G_DL_IN_Pin|DET_3_5G_DL_OUT_Pin;
 8005f74:	9404      	str	r4, [sp, #16]
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
 8005f76:	9405      	str	r4, [sp, #20]
    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8005f78:	f7fe fd0e 	bl	8004998 <HAL_GPIO_Init>
    /* ADC1 DMA Init */
    /* ADC1 Init */
    hdma_adc1.Instance = DMA1_Channel1;
    hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY;
    hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE;
    hdma_adc1.Init.MemInc = DMA_MINC_ENABLE;
 8005f7c:	2280      	movs	r2, #128	; 0x80
    hdma_adc1.Instance = DMA1_Channel1;
 8005f7e:	4c10      	ldr	r4, [pc, #64]	; (8005fc0 <HAL_ADC_MspInit+0xd4>)
 8005f80:	4b10      	ldr	r3, [pc, #64]	; (8005fc4 <HAL_ADC_MspInit+0xd8>)
    hdma_adc1.Init.MemInc = DMA_MINC_ENABLE;
 8005f82:	60e2      	str	r2, [r4, #12]
    hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
 8005f84:	f44f 7200 	mov.w	r2, #512	; 0x200
    hdma_adc1.Instance = DMA1_Channel1;
 8005f88:	6023      	str	r3, [r4, #0]
    hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
 8005f8a:	6122      	str	r2, [r4, #16]
    hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY;
 8005f8c:	2300      	movs	r3, #0
    hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
 8005f8e:	f44f 6200 	mov.w	r2, #2048	; 0x800
    hdma_adc1.Init.Mode = DMA_NORMAL;
    hdma_adc1.Init.Priority = DMA_PRIORITY_LOW;
    if (HAL_DMA_Init(&hdma_adc1) != HAL_OK)
 8005f92:	4620      	mov	r0, r4
    hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY;
 8005f94:	6063      	str	r3, [r4, #4]
    hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE;
 8005f96:	60a3      	str	r3, [r4, #8]
    hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
 8005f98:	6162      	str	r2, [r4, #20]
    hdma_adc1.Init.Mode = DMA_NORMAL;
 8005f9a:	61a3      	str	r3, [r4, #24]
    hdma_adc1.Init.Priority = DMA_PRIORITY_LOW;
 8005f9c:	61e3      	str	r3, [r4, #28]
    if (HAL_DMA_Init(&hdma_adc1) != HAL_OK)
 8005f9e:	f7fe fb33 	bl	8004608 <HAL_DMA_Init>
 8005fa2:	b108      	cbz	r0, 8005fa8 <HAL_ADC_MspInit+0xbc>
    {
      Error_Handler();
 8005fa4:	f7ff ff7e 	bl	8005ea4 <Error_Handler>
    }

    __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc1);
 8005fa8:	622c      	str	r4, [r5, #32]
 8005faa:	6265      	str	r5, [r4, #36]	; 0x24
  /* USER CODE BEGIN ADC1_MspInit 1 */

  /* USER CODE END ADC1_MspInit 1 */
  }

}
 8005fac:	b009      	add	sp, #36	; 0x24
 8005fae:	bd30      	pop	{r4, r5, pc}
 8005fb0:	40012400 	.word	0x40012400
 8005fb4:	40011000 	.word	0x40011000
 8005fb8:	40010800 	.word	0x40010800
 8005fbc:	40010c00 	.word	0x40010c00
 8005fc0:	2000115c 	.word	0x2000115c
 8005fc4:	40020008 	.word	0x40020008

08005fc8 <HAL_TIM_Base_MspInit>:
* @param htim_base: TIM_Base handle pointer
* @retval None
*/
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
{
  if(htim_base->Instance==TIM6)
 8005fc8:	6802      	ldr	r2, [r0, #0]
 8005fca:	4b08      	ldr	r3, [pc, #32]	; (8005fec <HAL_TIM_Base_MspInit+0x24>)
{
 8005fcc:	b082      	sub	sp, #8
  if(htim_base->Instance==TIM6)
 8005fce:	429a      	cmp	r2, r3
 8005fd0:	d10a      	bne.n	8005fe8 <HAL_TIM_Base_MspInit+0x20>
  {
  /* USER CODE BEGIN TIM6_MspInit 0 */

  /* USER CODE END TIM6_MspInit 0 */
    /* Peripheral clock enable */
    __HAL_RCC_TIM6_CLK_ENABLE();
 8005fd2:	f503 3300 	add.w	r3, r3, #131072	; 0x20000
 8005fd6:	69da      	ldr	r2, [r3, #28]
 8005fd8:	f042 0210 	orr.w	r2, r2, #16
 8005fdc:	61da      	str	r2, [r3, #28]
 8005fde:	69db      	ldr	r3, [r3, #28]
 8005fe0:	f003 0310 	and.w	r3, r3, #16
 8005fe4:	9301      	str	r3, [sp, #4]
 8005fe6:	9b01      	ldr	r3, [sp, #4]
  /* USER CODE BEGIN TIM6_MspInit 1 */

  /* USER CODE END TIM6_MspInit 1 */
  }

}
 8005fe8:	b002      	add	sp, #8
 8005fea:	4770      	bx	lr
 8005fec:	40001000 	.word	0x40001000

08005ff0 <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
 8005ff0:	b570      	push	{r4, r5, r6, lr}
 8005ff2:	4606      	mov	r6, r0
 8005ff4:	b086      	sub	sp, #24
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8005ff6:	2210      	movs	r2, #16
 8005ff8:	2100      	movs	r1, #0
 8005ffa:	a802      	add	r0, sp, #8
 8005ffc:	f000 f9ec 	bl	80063d8 <memset>
  if(huart->Instance==USART1)
 8006000:	6832      	ldr	r2, [r6, #0]
 8006002:	4b20      	ldr	r3, [pc, #128]	; (8006084 <HAL_UART_MspInit+0x94>)
 8006004:	429a      	cmp	r2, r3
 8006006:	d13b      	bne.n	8006080 <HAL_UART_MspInit+0x90>
  {
  /* USER CODE BEGIN USART1_MspInit 0 */

  /* USER CODE END USART1_MspInit 0 */
    /* Peripheral clock enable */
    __HAL_RCC_USART1_CLK_ENABLE();
 8006008:	f503 4358 	add.w	r3, r3, #55296	; 0xd800
 800600c:	699a      	ldr	r2, [r3, #24]
    PA10     ------> USART1_RX 
    */
    GPIO_InitStruct.Pin = GPIO_PIN_9;
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 800600e:	a902      	add	r1, sp, #8
    __HAL_RCC_USART1_CLK_ENABLE();
 8006010:	f442 4280 	orr.w	r2, r2, #16384	; 0x4000
 8006014:	619a      	str	r2, [r3, #24]
 8006016:	699a      	ldr	r2, [r3, #24]
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8006018:	481b      	ldr	r0, [pc, #108]	; (8006088 <HAL_UART_MspInit+0x98>)
    __HAL_RCC_USART1_CLK_ENABLE();
 800601a:	f402 4280 	and.w	r2, r2, #16384	; 0x4000
 800601e:	9200      	str	r2, [sp, #0]
 8006020:	9a00      	ldr	r2, [sp, #0]
    __HAL_RCC_GPIOA_CLK_ENABLE();
 8006022:	699a      	ldr	r2, [r3, #24]

    GPIO_InitStruct.Pin = GPIO_PIN_10;
    GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
 8006024:	2500      	movs	r5, #0
    __HAL_RCC_GPIOA_CLK_ENABLE();
 8006026:	f042 0204 	orr.w	r2, r2, #4
 800602a:	619a      	str	r2, [r3, #24]
 800602c:	699b      	ldr	r3, [r3, #24]
    GPIO_InitStruct.Pull = GPIO_NOPULL;
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);

    /* USART1 DMA Init */
    /* USART1_RX Init */
    hdma_usart1_rx.Instance = DMA1_Channel5;
 800602e:	4c17      	ldr	r4, [pc, #92]	; (800608c <HAL_UART_MspInit+0x9c>)
    __HAL_RCC_GPIOA_CLK_ENABLE();
 8006030:	f003 0304 	and.w	r3, r3, #4
 8006034:	9301      	str	r3, [sp, #4]
 8006036:	9b01      	ldr	r3, [sp, #4]
    GPIO_InitStruct.Pin = GPIO_PIN_9;
 8006038:	f44f 7300 	mov.w	r3, #512	; 0x200
 800603c:	9302      	str	r3, [sp, #8]
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 800603e:	2302      	movs	r3, #2
 8006040:	9303      	str	r3, [sp, #12]
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
 8006042:	2303      	movs	r3, #3
 8006044:	9305      	str	r3, [sp, #20]
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8006046:	f7fe fca7 	bl	8004998 <HAL_GPIO_Init>
    GPIO_InitStruct.Pin = GPIO_PIN_10;
 800604a:	f44f 6380 	mov.w	r3, #1024	; 0x400
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 800604e:	480e      	ldr	r0, [pc, #56]	; (8006088 <HAL_UART_MspInit+0x98>)
 8006050:	a902      	add	r1, sp, #8
    GPIO_InitStruct.Pin = GPIO_PIN_10;
 8006052:	9302      	str	r3, [sp, #8]
    GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
 8006054:	9503      	str	r5, [sp, #12]
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 8006056:	9504      	str	r5, [sp, #16]
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8006058:	f7fe fc9e 	bl	8004998 <HAL_GPIO_Init>
    hdma_usart1_rx.Instance = DMA1_Channel5;
 800605c:	4b0c      	ldr	r3, [pc, #48]	; (8006090 <HAL_UART_MspInit+0xa0>)
    hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE;
    hdma_usart1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
    hdma_usart1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
    hdma_usart1_rx.Init.Mode = DMA_NORMAL;
    hdma_usart1_rx.Init.Priority = DMA_PRIORITY_LOW;
    if (HAL_DMA_Init(&hdma_usart1_rx) != HAL_OK)
 800605e:	4620      	mov	r0, r4
    hdma_usart1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
 8006060:	e884 0028 	stmia.w	r4, {r3, r5}
    hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE;
 8006064:	2380      	movs	r3, #128	; 0x80
    hdma_usart1_rx.Init.PeriphInc = DMA_PINC_DISABLE;
 8006066:	60a5      	str	r5, [r4, #8]
    hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE;
 8006068:	60e3      	str	r3, [r4, #12]
    hdma_usart1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
 800606a:	6125      	str	r5, [r4, #16]
    hdma_usart1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
 800606c:	6165      	str	r5, [r4, #20]
    hdma_usart1_rx.Init.Mode = DMA_NORMAL;
 800606e:	61a5      	str	r5, [r4, #24]
    hdma_usart1_rx.Init.Priority = DMA_PRIORITY_LOW;
 8006070:	61e5      	str	r5, [r4, #28]
    if (HAL_DMA_Init(&hdma_usart1_rx) != HAL_OK)
 8006072:	f7fe fac9 	bl	8004608 <HAL_DMA_Init>
 8006076:	b108      	cbz	r0, 800607c <HAL_UART_MspInit+0x8c>
    {
      Error_Handler();
 8006078:	f7ff ff14 	bl	8005ea4 <Error_Handler>
    }

    __HAL_LINKDMA(huart,hdmarx,hdma_usart1_rx);
 800607c:	6374      	str	r4, [r6, #52]	; 0x34
 800607e:	6266      	str	r6, [r4, #36]	; 0x24
  /* USER CODE BEGIN USART1_MspInit 1 */

  /* USER CODE END USART1_MspInit 1 */
  }

}
 8006080:	b006      	add	sp, #24
 8006082:	bd70      	pop	{r4, r5, r6, pc}
 8006084:	40013800 	.word	0x40013800
 8006088:	40010800 	.word	0x40010800
 800608c:	200010d8 	.word	0x200010d8
 8006090:	40020058 	.word	0x40020058

08006094 <NMI_Handler>:
 8006094:	4770      	bx	lr

08006096 <HardFault_Handler>:

/**
  * @brief This function handles Hard fault interrupt.
  */
void HardFault_Handler(void)
{
 8006096:	e7fe      	b.n	8006096 <HardFault_Handler>

08006098 <MemManage_Handler>:

/**
  * @brief This function handles Memory management fault.
  */
void MemManage_Handler(void)
{
 8006098:	e7fe      	b.n	8006098 <MemManage_Handler>

0800609a <BusFault_Handler>:

/**
  * @brief This function handles Prefetch fault, memory access fault.
  */
void BusFault_Handler(void)
{
 800609a:	e7fe      	b.n	800609a <BusFault_Handler>

0800609c <UsageFault_Handler>:

/**
  * @brief This function handles Undefined instruction or illegal state.
  */
void UsageFault_Handler(void)
{
 800609c:	e7fe      	b.n	800609c <UsageFault_Handler>

0800609e <SVC_Handler>:
 800609e:	4770      	bx	lr

080060a0 <DebugMon_Handler>:
 80060a0:	4770      	bx	lr

080060a2 <PendSV_Handler>:

/**
  * @brief This function handles Pendable request for system service.
  */
void PendSV_Handler(void)
{
 80060a2:	4770      	bx	lr

080060a4 <SysTick_Handler>:
void SysTick_Handler(void)
{
  /* USER CODE BEGIN SysTick_IRQn 0 */

  /* USER CODE END SysTick_IRQn 0 */
  HAL_IncTick();
 80060a4:	f7fe b8f4 	b.w	8004290 <HAL_IncTick>

080060a8 <DMA1_Channel1_IRQHandler>:
void DMA1_Channel1_IRQHandler(void)
{
  /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */

  /* USER CODE END DMA1_Channel1_IRQn 0 */
  HAL_DMA_IRQHandler(&hdma_adc1);
 80060a8:	4801      	ldr	r0, [pc, #4]	; (80060b0 <DMA1_Channel1_IRQHandler+0x8>)
 80060aa:	f7fe bb99 	b.w	80047e0 <HAL_DMA_IRQHandler>
 80060ae:	bf00      	nop
 80060b0:	2000115c 	.word	0x2000115c

080060b4 <DMA1_Channel5_IRQHandler>:
void DMA1_Channel5_IRQHandler(void)
{
  /* USER CODE BEGIN DMA1_Channel5_IRQn 0 */

  /* USER CODE END DMA1_Channel5_IRQn 0 */
  HAL_DMA_IRQHandler(&hdma_usart1_rx);
 80060b4:	4801      	ldr	r0, [pc, #4]	; (80060bc <DMA1_Channel5_IRQHandler+0x8>)
 80060b6:	f7fe bb93 	b.w	80047e0 <HAL_DMA_IRQHandler>
 80060ba:	bf00      	nop
 80060bc:	200010d8 	.word	0x200010d8

080060c0 <USART1_IRQHandler>:
void USART1_IRQHandler(void)
{
  /* USER CODE BEGIN USART1_IRQn 0 */

  /* USER CODE END USART1_IRQn 0 */
  HAL_UART_IRQHandler(&huart1);
 80060c0:	4801      	ldr	r0, [pc, #4]	; (80060c8 <USART1_IRQHandler+0x8>)
 80060c2:	f7ff bbef 	b.w	80058a4 <HAL_UART_IRQHandler>
 80060c6:	bf00      	nop
 80060c8:	2000111c 	.word	0x2000111c

080060cc <TIM6_IRQHandler>:
void TIM6_IRQHandler(void)
{
  /* USER CODE BEGIN TIM6_IRQn 0 */

  /* USER CODE END TIM6_IRQn 0 */
  HAL_TIM_IRQHandler(&htim6);
 80060cc:	4801      	ldr	r0, [pc, #4]	; (80060d4 <TIM6_IRQHandler+0x8>)
 80060ce:	f7ff b86f 	b.w	80051b0 <HAL_TIM_IRQHandler>
 80060d2:	bf00      	nop
 80060d4:	200011a0 	.word	0x200011a0

080060d8 <_read>:
	_kill(status, -1);
	while (1) {}		/* Make sure we hang here */
}

__attribute__((weak)) int _read(int file, char *ptr, int len)
{
 80060d8:	b570      	push	{r4, r5, r6, lr}
 80060da:	460e      	mov	r6, r1
 80060dc:	4615      	mov	r5, r2
	int DataIdx;

	for (DataIdx = 0; DataIdx < len; DataIdx++)
 80060de:	460c      	mov	r4, r1
 80060e0:	1ba3      	subs	r3, r4, r6
 80060e2:	429d      	cmp	r5, r3
 80060e4:	dc01      	bgt.n	80060ea <_read+0x12>
	{
		*ptr++ = __io_getchar();
	}

return len;
}
 80060e6:	4628      	mov	r0, r5
 80060e8:	bd70      	pop	{r4, r5, r6, pc}
		*ptr++ = __io_getchar();
 80060ea:	f3af 8000 	nop.w
 80060ee:	f804 0b01 	strb.w	r0, [r4], #1
 80060f2:	e7f5      	b.n	80060e0 <_read+0x8>

080060f4 <_sbrk>:
	}
	return len;
}

caddr_t _sbrk(int incr)
{
 80060f4:	b508      	push	{r3, lr}
	extern char end asm("end");
	static char *heap_end;
	char *prev_heap_end;

	if (heap_end == 0)
 80060f6:	4b0a      	ldr	r3, [pc, #40]	; (8006120 <_sbrk+0x2c>)
{
 80060f8:	4602      	mov	r2, r0
	if (heap_end == 0)
 80060fa:	6819      	ldr	r1, [r3, #0]
 80060fc:	b909      	cbnz	r1, 8006102 <_sbrk+0xe>
		heap_end = &end;
 80060fe:	4909      	ldr	r1, [pc, #36]	; (8006124 <_sbrk+0x30>)
 8006100:	6019      	str	r1, [r3, #0]

	prev_heap_end = heap_end;
	if (heap_end + incr > stack_ptr)
 8006102:	4669      	mov	r1, sp
	prev_heap_end = heap_end;
 8006104:	6818      	ldr	r0, [r3, #0]
	if (heap_end + incr > stack_ptr)
 8006106:	4402      	add	r2, r0
 8006108:	428a      	cmp	r2, r1
 800610a:	d906      	bls.n	800611a <_sbrk+0x26>
	{
//		write(1, "Heap and stack collision\n", 25);
//		abort();
		errno = ENOMEM;
 800610c:	f000 f93a 	bl	8006384 <__errno>
 8006110:	230c      	movs	r3, #12
 8006112:	6003      	str	r3, [r0, #0]
		return (caddr_t) -1;
 8006114:	f04f 30ff 	mov.w	r0, #4294967295
 8006118:	bd08      	pop	{r3, pc}
	}

	heap_end += incr;
 800611a:	601a      	str	r2, [r3, #0]

	return (caddr_t) prev_heap_end;
}
 800611c:	bd08      	pop	{r3, pc}
 800611e:	bf00      	nop
 8006120:	20000094 	.word	0x20000094
 8006124:	20001e38 	.word	0x20001e38

08006128 <_close>:

int _close(int file)
{
	return -1;
}
 8006128:	f04f 30ff 	mov.w	r0, #4294967295
 800612c:	4770      	bx	lr

0800612e <_fstat>:


int _fstat(int file, struct stat *st)
{
	st->st_mode = S_IFCHR;
 800612e:	f44f 5300 	mov.w	r3, #8192	; 0x2000
	return 0;
}
 8006132:	2000      	movs	r0, #0
	st->st_mode = S_IFCHR;
 8006134:	604b      	str	r3, [r1, #4]
}
 8006136:	4770      	bx	lr

08006138 <_isatty>:

int _isatty(int file)
{
	return 1;
}
 8006138:	2001      	movs	r0, #1
 800613a:	4770      	bx	lr

0800613c <_lseek>:

int _lseek(int file, int ptr, int dir)
{
	return 0;
}
 800613c:	2000      	movs	r0, #0
 800613e:	4770      	bx	lr

08006140 <SystemInit>:
  */
void SystemInit (void)
{
  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
  /* Set HSION bit */
  RCC->CR |= 0x00000001U;
 8006140:	4b0e      	ldr	r3, [pc, #56]	; (800617c <SystemInit+0x3c>)
 8006142:	681a      	ldr	r2, [r3, #0]
 8006144:	f042 0201 	orr.w	r2, r2, #1
 8006148:	601a      	str	r2, [r3, #0]

  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
#if !defined(STM32F105xC) && !defined(STM32F107xC)
  RCC->CFGR &= 0xF8FF0000U;
 800614a:	6859      	ldr	r1, [r3, #4]
 800614c:	4a0c      	ldr	r2, [pc, #48]	; (8006180 <SystemInit+0x40>)
 800614e:	400a      	ands	r2, r1
 8006150:	605a      	str	r2, [r3, #4]
#else
  RCC->CFGR &= 0xF0FF0000U;
#endif /* STM32F105xC */   
  
  /* Reset HSEON, CSSON and PLLON bits */
  RCC->CR &= 0xFEF6FFFFU;
 8006152:	681a      	ldr	r2, [r3, #0]
 8006154:	f022 7284 	bic.w	r2, r2, #17301504	; 0x1080000
 8006158:	f422 3280 	bic.w	r2, r2, #65536	; 0x10000
 800615c:	601a      	str	r2, [r3, #0]

  /* Reset HSEBYP bit */
  RCC->CR &= 0xFFFBFFFFU;
 800615e:	681a      	ldr	r2, [r3, #0]
 8006160:	f422 2280 	bic.w	r2, r2, #262144	; 0x40000
 8006164:	601a      	str	r2, [r3, #0]

  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
  RCC->CFGR &= 0xFF80FFFFU;
 8006166:	685a      	ldr	r2, [r3, #4]
 8006168:	f422 02fe 	bic.w	r2, r2, #8323072	; 0x7f0000
 800616c:	605a      	str	r2, [r3, #4]

  /* Reset CFGR2 register */
  RCC->CFGR2 = 0x00000000U;      
#else
  /* Disable all interrupts and clear pending bits  */
  RCC->CIR = 0x009F0000U;
 800616e:	f44f 021f 	mov.w	r2, #10420224	; 0x9f0000
 8006172:	609a      	str	r2, [r3, #8]
#endif 

#ifdef VECT_TAB_SRAM
  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#else
  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
 8006174:	4a03      	ldr	r2, [pc, #12]	; (8006184 <SystemInit+0x44>)
 8006176:	4b04      	ldr	r3, [pc, #16]	; (8006188 <SystemInit+0x48>)
 8006178:	609a      	str	r2, [r3, #8]
 800617a:	4770      	bx	lr
 800617c:	40021000 	.word	0x40021000
 8006180:	f8ff0000 	.word	0xf8ff0000
 8006184:	08004000 	.word	0x08004000
 8006188:	e000ed00 	.word	0xe000ed00

0800618c <HAL_UART_TxCpltCallback>:
}
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
{
   uint16_t size;

   if(huart->Instance == USART1)
 800618c:	6802      	ldr	r2, [r0, #0]
 800618e:	4b1d      	ldr	r3, [pc, #116]	; (8006204 <HAL_UART_TxCpltCallback+0x78>)
 8006190:	429a      	cmp	r2, r3
 8006192:	d135      	bne.n	8006200 <HAL_UART_TxCpltCallback+0x74>
   {
      uart_hal_tx.output_p += huart->TxXferSize;
 8006194:	4b1c      	ldr	r3, [pc, #112]	; (8006208 <HAL_UART_TxCpltCallback+0x7c>)
 8006196:	8c81      	ldrh	r1, [r0, #36]	; 0x24
 8006198:	f8b3 2402 	ldrh.w	r2, [r3, #1026]	; 0x402
 800619c:	440a      	add	r2, r1
 800619e:	b292      	uxth	r2, r2
 80061a0:	f8a3 2402 	strh.w	r2, [r3, #1026]	; 0x402
      if(uart_hal_tx.output_p >= QUEUE_BUFFER_LENGTH)
 80061a4:	f8b3 2402 	ldrh.w	r2, [r3, #1026]	; 0x402
 80061a8:	b292      	uxth	r2, r2
 80061aa:	f5b2 6f80 	cmp.w	r2, #1024	; 0x400
      {
         uart_hal_tx.output_p -= QUEUE_BUFFER_LENGTH;
 80061ae:	bf21      	itttt	cs
 80061b0:	f8b3 2402 	ldrhcs.w	r2, [r3, #1026]	; 0x402
 80061b4:	f5a2 6280 	subcs.w	r2, r2, #1024	; 0x400
 80061b8:	b292      	uxthcs	r2, r2
 80061ba:	f8a3 2402 	strhcs.w	r2, [r3, #1026]	; 0x402
      }
      if(uart_hal_tx.input_p != uart_hal_tx.output_p)
 80061be:	f8b3 1400 	ldrh.w	r1, [r3, #1024]	; 0x400
 80061c2:	f8b3 2402 	ldrh.w	r2, [r3, #1026]	; 0x402
 80061c6:	b289      	uxth	r1, r1
 80061c8:	b292      	uxth	r2, r2
 80061ca:	4291      	cmp	r1, r2
 80061cc:	d018      	beq.n	8006200 <HAL_UART_TxCpltCallback+0x74>
      {
         if(uart_hal_tx.input_p > uart_hal_tx.output_p)
 80061ce:	f8b3 1400 	ldrh.w	r1, [r3, #1024]	; 0x400
 80061d2:	f8b3 2402 	ldrh.w	r2, [r3, #1026]	; 0x402
 80061d6:	b289      	uxth	r1, r1
 80061d8:	b292      	uxth	r2, r2
 80061da:	4291      	cmp	r1, r2
         {
            size = uart_hal_tx.input_p - uart_hal_tx.output_p;
 80061dc:	bf85      	ittet	hi
 80061de:	f8b3 2400 	ldrhhi.w	r2, [r3, #1024]	; 0x400
 80061e2:	f8b3 1402 	ldrhhi.w	r1, [r3, #1026]	; 0x402
         }
         else
         {
            size = QUEUE_BUFFER_LENGTH - uart_hal_tx.output_p;
 80061e6:	f8b3 2402 	ldrhls.w	r2, [r3, #1026]	; 0x402
            size = uart_hal_tx.input_p - uart_hal_tx.output_p;
 80061ea:	1a52      	subhi	r2, r2, r1
         }
         HAL_UART_Transmit_IT(huart, &uart_hal_tx.buffer[uart_hal_tx.output_p], size);
 80061ec:	f8b3 1402 	ldrh.w	r1, [r3, #1026]	; 0x402
            size = QUEUE_BUFFER_LENGTH - uart_hal_tx.output_p;
 80061f0:	bf98      	it	ls
 80061f2:	f5c2 6280 	rsbls	r2, r2, #1024	; 0x400
         HAL_UART_Transmit_IT(huart, &uart_hal_tx.buffer[uart_hal_tx.output_p], size);
 80061f6:	b289      	uxth	r1, r1
            size = QUEUE_BUFFER_LENGTH - uart_hal_tx.output_p;
 80061f8:	b292      	uxth	r2, r2
         HAL_UART_Transmit_IT(huart, &uart_hal_tx.buffer[uart_hal_tx.output_p], size);
 80061fa:	4419      	add	r1, r3
 80061fc:	f7ff ba62 	b.w	80056c4 <HAL_UART_Transmit_IT>
 8006200:	4770      	bx	lr
 8006202:	bf00      	nop
 8006204:	40013800 	.word	0x40013800
 8006208:	20001624 	.word	0x20001624

0800620c <GetDataFromUartQueue>:
    pUARTQUEUE pQueue = &TerminalQueue;
//    if (HAL_UART_Transmit(dst, pQueue->Buffer + pQueue->tail, 1, 3000) != HAL_OK)
//    {
//       _Error_Handler(__FILE__, __LINE__);
//    }
    uart_buf[cnt++] = *(pQueue->Buffer + pQueue->tail); 
 800620c:	4a16      	ldr	r2, [pc, #88]	; (8006268 <GetDataFromUartQueue+0x5c>)
{
 800620e:	b570      	push	{r4, r5, r6, lr}
    uart_buf[cnt++] = *(pQueue->Buffer + pQueue->tail); 
 8006210:	6814      	ldr	r4, [r2, #0]
 8006212:	4e16      	ldr	r6, [pc, #88]	; (800626c <GetDataFromUartQueue+0x60>)
 8006214:	1c63      	adds	r3, r4, #1
 8006216:	6013      	str	r3, [r2, #0]
 8006218:	4b15      	ldr	r3, [pc, #84]	; (8006270 <GetDataFromUartQueue+0x64>)
 800621a:	6859      	ldr	r1, [r3, #4]
 800621c:	f103 000c 	add.w	r0, r3, #12
 8006220:	5c0d      	ldrb	r5, [r1, r0]

    pQueue->tail++;
 8006222:	3101      	adds	r1, #1
    if (pQueue->tail >= QUEUE_BUFFER_LENGTH) pQueue->tail = 0;
 8006224:	f5b1 6f80 	cmp.w	r1, #1024	; 0x400
    uart_buf[cnt++] = *(pQueue->Buffer + pQueue->tail); 
 8006228:	f846 5024 	str.w	r5, [r6, r4, lsl #2]
 800622c:	4615      	mov	r5, r2
    if (pQueue->tail >= QUEUE_BUFFER_LENGTH) pQueue->tail = 0;
 800622e:	bfa8      	it	ge
 8006230:	2200      	movge	r2, #0
    pQueue->data--;
 8006232:	689c      	ldr	r4, [r3, #8]
    pQueue->tail++;
 8006234:	bfb8      	it	lt
 8006236:	6059      	strlt	r1, [r3, #4]
    pQueue->data--;
 8006238:	f104 34ff 	add.w	r4, r4, #4294967295
    if (pQueue->tail >= QUEUE_BUFFER_LENGTH) pQueue->tail = 0;
 800623c:	bfa8      	it	ge
 800623e:	605a      	strge	r2, [r3, #4]
    pQueue->data--;
 8006240:	609c      	str	r4, [r3, #8]
    
    if(pQueue->data == 0){
 8006242:	b97c      	cbnz	r4, 8006264 <GetDataFromUartQueue+0x58>
        RF_Ctrl_Main(&uart_buf[0]);
 8006244:	4809      	ldr	r0, [pc, #36]	; (800626c <GetDataFromUartQueue+0x60>)
 8006246:	f000 f84b 	bl	80062e0 <RF_Ctrl_Main>
            }
#endif // PYJ.2019.07.15_END -- 
        cnt = 0;
        
        for(int i  = 0; i < QUEUE_BUFFER_LENGTH; i++)
            uart_buf[i] = 0;
 800624a:	4623      	mov	r3, r4
        cnt = 0;
 800624c:	602c      	str	r4, [r5, #0]
            uart_buf[i] = 0;
 800624e:	f846 3024 	str.w	r3, [r6, r4, lsl #2]
        for(int i  = 0; i < QUEUE_BUFFER_LENGTH; i++)
 8006252:	3401      	adds	r4, #1
 8006254:	f5b4 6f80 	cmp.w	r4, #1024	; 0x400
 8006258:	d1f9      	bne.n	800624e <GetDataFromUartQueue+0x42>
        
        HAL_Delay(1);
 800625a:	2001      	movs	r0, #1
    }

}
 800625c:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
        HAL_Delay(1);
 8006260:	f7fe b828 	b.w	80042b4 <HAL_Delay>
 8006264:	bd70      	pop	{r4, r5, r6, pc}
 8006266:	bf00      	nop
 8006268:	20000098 	.word	0x20000098
 800626c:	2000009c 	.word	0x2000009c
 8006270:	20001218 	.word	0x20001218

08006274 <HAL_UART_RxCpltCallback>:
    UartTimerCnt = 0;
 8006274:	2300      	movs	r3, #0
{
 8006276:	b510      	push	{r4, lr}
    UartTimerCnt = 0;
 8006278:	4a0d      	ldr	r2, [pc, #52]	; (80062b0 <HAL_UART_RxCpltCallback+0x3c>)
    pQueue->head++;
 800627a:	4c0e      	ldr	r4, [pc, #56]	; (80062b4 <HAL_UART_RxCpltCallback+0x40>)
    UartTimerCnt = 0;
 800627c:	6013      	str	r3, [r2, #0]
    pQueue->head++;
 800627e:	6822      	ldr	r2, [r4, #0]
 8006280:	3201      	adds	r2, #1
 8006282:	f5b2 6f80 	cmp.w	r2, #1024	; 0x400
 8006286:	bfb8      	it	lt
 8006288:	4613      	movlt	r3, r2
 800628a:	6023      	str	r3, [r4, #0]
    pQueue->data++;
 800628c:	68a3      	ldr	r3, [r4, #8]
 800628e:	3301      	adds	r3, #1
    if (pQueue->data >= QUEUE_BUFFER_LENGTH)
 8006290:	f5b3 6f80 	cmp.w	r3, #1024	; 0x400
    pQueue->data++;
 8006294:	60a3      	str	r3, [r4, #8]
    if (pQueue->data >= QUEUE_BUFFER_LENGTH)
 8006296:	db01      	blt.n	800629c <HAL_UART_RxCpltCallback+0x28>
        GetDataFromUartQueue(huart);
 8006298:	f7ff ffb8 	bl	800620c <GetDataFromUartQueue>
    HAL_UART_Receive_DMA(&hTerminal, pQueue->Buffer + pQueue->head, 1);
 800629c:	6823      	ldr	r3, [r4, #0]
 800629e:	4906      	ldr	r1, [pc, #24]	; (80062b8 <HAL_UART_RxCpltCallback+0x44>)
 80062a0:	2201      	movs	r2, #1
}
 80062a2:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
    HAL_UART_Receive_DMA(&hTerminal, pQueue->Buffer + pQueue->head, 1);
 80062a6:	4419      	add	r1, r3
 80062a8:	4804      	ldr	r0, [pc, #16]	; (80062bc <HAL_UART_RxCpltCallback+0x48>)
 80062aa:	f7ff ba2b 	b.w	8005704 <HAL_UART_Receive_DMA>
 80062ae:	bf00      	nop
 80062b0:	20000090 	.word	0x20000090
 80062b4:	20001218 	.word	0x20001218
 80062b8:	20001224 	.word	0x20001224
 80062bc:	2000111c 	.word	0x2000111c

080062c0 <RF_Data_Check>:
    Length,
    Type,
    Crcindex,
}Bluecell_Prot_p;

bool RF_Data_Check(uint8_t* data_buf){
 80062c0:	b510      	push	{r4, lr}
 80062c2:	4604      	mov	r4, r0
    bool ret = false;
    bool crcret = STH30_CheckCrc(&data_buf[Type], data_buf[Length], data_buf[Crcindex]);
 80062c4:	78c2      	ldrb	r2, [r0, #3]
 80062c6:	7841      	ldrb	r1, [r0, #1]
 80062c8:	3002      	adds	r0, #2
 80062ca:	f7ff fb93 	bl	80059f4 <STH30_CheckCrc>
    
    if(data_buf[Header] == BLUECELL_HEADER){ /*HEADER CHECK*/
 80062ce:	7823      	ldrb	r3, [r4, #0]
        ret= true;
    }
    if(crcret == true){/*CRC CHECK*/
 80062d0:	b918      	cbnz	r0, 80062da <RF_Data_Check+0x1a>
    if(data_buf[Header] == BLUECELL_HEADER){ /*HEADER CHECK*/
 80062d2:	3bbe      	subs	r3, #190	; 0xbe
 80062d4:	4258      	negs	r0, r3
 80062d6:	4158      	adcs	r0, r3
 80062d8:	bd10      	pop	{r4, pc}
        ret = true;
 80062da:	2001      	movs	r0, #1
    }

    return ret;

}
 80062dc:	bd10      	pop	{r4, pc}
	...

080062e0 <RF_Ctrl_Main>:
bool RF_Ctrl_Main(uint8_t* data_buf){
 80062e0:	b510      	push	{r4, lr}
    bool ret = false;
    Bluecell_Prot_t type = data_buf[Type];
 80062e2:	7884      	ldrb	r4, [r0, #2]
    RF_Data_Check(&data_buf[Header]); /* ERROR CHECK */
 80062e4:	f7ff ffec 	bl	80062c0 <RF_Data_Check>


    switch(type){
 80062e8:	2c01      	cmp	r4, #1
 80062ea:	d011      	beq.n	8006310 <RF_Ctrl_Main+0x30>
 80062ec:	d303      	bcc.n	80062f6 <RF_Ctrl_Main+0x16>
 80062ee:	2c11      	cmp	r4, #17
 80062f0:	d812      	bhi.n	8006318 <RF_Ctrl_Main+0x38>
        default:
            printf("Function : %s   LINE : %d    type : %d \r\n",__func__,__LINE__,type);
            break;
    }
    return ret;
}
 80062f2:	2000      	movs	r0, #0
 80062f4:	bd10      	pop	{r4, pc}
  \details Acts as a special kind of Data Memory Barrier.
           It completes when all explicit memory accesses before this instruction complete.
 */
__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
{
  __ASM volatile ("dsb 0xF":::"memory");
 80062f6:	f3bf 8f4f 	dsb	sy
                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
 80062fa:	490b      	ldr	r1, [pc, #44]	; (8006328 <RF_Ctrl_Main+0x48>)
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
 80062fc:	4b0b      	ldr	r3, [pc, #44]	; (800632c <RF_Ctrl_Main+0x4c>)
                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
 80062fe:	68ca      	ldr	r2, [r1, #12]
 8006300:	f402 62e0 	and.w	r2, r2, #1792	; 0x700
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
 8006304:	4313      	orrs	r3, r2
 8006306:	60cb      	str	r3, [r1, #12]
 8006308:	f3bf 8f4f 	dsb	sy
  __ASM volatile ("nop");
 800630c:	bf00      	nop
 800630e:	e7fd      	b.n	800630c <RF_Ctrl_Main+0x2c>
        printf(" ");
 8006310:	2020      	movs	r0, #32
 8006312:	f000 f881 	bl	8006418 <putchar>
        break;
 8006316:	e7ec      	b.n	80062f2 <RF_Ctrl_Main+0x12>
            printf("Function : %s   LINE : %d    type : %d \r\n",__func__,__LINE__,type);
 8006318:	4623      	mov	r3, r4
 800631a:	f44f 7284 	mov.w	r2, #264	; 0x108
 800631e:	4904      	ldr	r1, [pc, #16]	; (8006330 <RF_Ctrl_Main+0x50>)
 8006320:	4804      	ldr	r0, [pc, #16]	; (8006334 <RF_Ctrl_Main+0x54>)
 8006322:	f000 f861 	bl	80063e8 <iprintf>
            break;
 8006326:	e7e4      	b.n	80062f2 <RF_Ctrl_Main+0x12>
 8006328:	e000ed00 	.word	0xe000ed00
 800632c:	05fa0004 	.word	0x05fa0004
 8006330:	0800753f 	.word	0x0800753f
 8006334:	08007515 	.word	0x08007515

08006338 <Reset_Handler>:
  .weak Reset_Handler
  .type Reset_Handler, %function
Reset_Handler:

/* Copy the data segment initializers from flash to SRAM */
  movs r1, #0
 8006338:	2100      	movs	r1, #0
  b LoopCopyDataInit
 800633a:	e003      	b.n	8006344 <LoopCopyDataInit>

0800633c <CopyDataInit>:

CopyDataInit:
  ldr r3, =_sidata
 800633c:	4b0b      	ldr	r3, [pc, #44]	; (800636c <LoopFillZerobss+0x14>)
  ldr r3, [r3, r1]
 800633e:	585b      	ldr	r3, [r3, r1]
  str r3, [r0, r1]
 8006340:	5043      	str	r3, [r0, r1]
  adds r1, r1, #4
 8006342:	3104      	adds	r1, #4

08006344 <LoopCopyDataInit>:

LoopCopyDataInit:
  ldr r0, =_sdata
 8006344:	480a      	ldr	r0, [pc, #40]	; (8006370 <LoopFillZerobss+0x18>)
  ldr r3, =_edata
 8006346:	4b0b      	ldr	r3, [pc, #44]	; (8006374 <LoopFillZerobss+0x1c>)
  adds r2, r0, r1
 8006348:	1842      	adds	r2, r0, r1
  cmp r2, r3
 800634a:	429a      	cmp	r2, r3
  bcc CopyDataInit
 800634c:	d3f6      	bcc.n	800633c <CopyDataInit>
  ldr r2, =_sbss
 800634e:	4a0a      	ldr	r2, [pc, #40]	; (8006378 <LoopFillZerobss+0x20>)
  b LoopFillZerobss
 8006350:	e002      	b.n	8006358 <LoopFillZerobss>

08006352 <FillZerobss>:
/* Zero fill the bss segment. */
FillZerobss:
  movs r3, #0
 8006352:	2300      	movs	r3, #0
  str r3, [r2], #4
 8006354:	f842 3b04 	str.w	r3, [r2], #4

08006358 <LoopFillZerobss>:

LoopFillZerobss:
  ldr r3, = _ebss
 8006358:	4b08      	ldr	r3, [pc, #32]	; (800637c <LoopFillZerobss+0x24>)
  cmp r2, r3
 800635a:	429a      	cmp	r2, r3
  bcc FillZerobss
 800635c:	d3f9      	bcc.n	8006352 <FillZerobss>

/* Call the clock system intitialization function.*/
    bl  SystemInit
 800635e:	f7ff feef 	bl	8006140 <SystemInit>
/* Call static constructors */
    bl __libc_init_array
 8006362:	f000 f815 	bl	8006390 <__libc_init_array>
/* Call the application's entry point.*/
  bl main
 8006366:	f7ff fbb7 	bl	8005ad8 <main>
  bx lr
 800636a:	4770      	bx	lr
  ldr r3, =_sidata
 800636c:	080075ec 	.word	0x080075ec
  ldr r0, =_sdata
 8006370:	20000000 	.word	0x20000000
  ldr r3, =_edata
 8006374:	20000070 	.word	0x20000070
  ldr r2, =_sbss
 8006378:	20000070 	.word	0x20000070
  ldr r3, = _ebss
 800637c:	20001e38 	.word	0x20001e38

08006380 <ADC1_2_IRQHandler>:
 * @retval : None
*/
    .section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
  b Infinite_Loop
 8006380:	e7fe      	b.n	8006380 <ADC1_2_IRQHandler>
	...

08006384 <__errno>:
 8006384:	4b01      	ldr	r3, [pc, #4]	; (800638c <__errno+0x8>)
 8006386:	6818      	ldr	r0, [r3, #0]
 8006388:	4770      	bx	lr
 800638a:	bf00      	nop
 800638c:	2000000c 	.word	0x2000000c

08006390 <__libc_init_array>:
 8006390:	b570      	push	{r4, r5, r6, lr}
 8006392:	2500      	movs	r5, #0
 8006394:	4e0c      	ldr	r6, [pc, #48]	; (80063c8 <__libc_init_array+0x38>)
 8006396:	4c0d      	ldr	r4, [pc, #52]	; (80063cc <__libc_init_array+0x3c>)
 8006398:	1ba4      	subs	r4, r4, r6
 800639a:	10a4      	asrs	r4, r4, #2
 800639c:	42a5      	cmp	r5, r4
 800639e:	d109      	bne.n	80063b4 <__libc_init_array+0x24>
 80063a0:	f001 f892 	bl	80074c8 <_init>
 80063a4:	2500      	movs	r5, #0
 80063a6:	4e0a      	ldr	r6, [pc, #40]	; (80063d0 <__libc_init_array+0x40>)
 80063a8:	4c0a      	ldr	r4, [pc, #40]	; (80063d4 <__libc_init_array+0x44>)
 80063aa:	1ba4      	subs	r4, r4, r6
 80063ac:	10a4      	asrs	r4, r4, #2
 80063ae:	42a5      	cmp	r5, r4
 80063b0:	d105      	bne.n	80063be <__libc_init_array+0x2e>
 80063b2:	bd70      	pop	{r4, r5, r6, pc}
 80063b4:	f856 3025 	ldr.w	r3, [r6, r5, lsl #2]
 80063b8:	4798      	blx	r3
 80063ba:	3501      	adds	r5, #1
 80063bc:	e7ee      	b.n	800639c <__libc_init_array+0xc>
 80063be:	f856 3025 	ldr.w	r3, [r6, r5, lsl #2]
 80063c2:	4798      	blx	r3
 80063c4:	3501      	adds	r5, #1
 80063c6:	e7f2      	b.n	80063ae <__libc_init_array+0x1e>
 80063c8:	080075e4 	.word	0x080075e4
 80063cc:	080075e4 	.word	0x080075e4
 80063d0:	080075e4 	.word	0x080075e4
 80063d4:	080075e8 	.word	0x080075e8

080063d8 <memset>:
 80063d8:	4603      	mov	r3, r0
 80063da:	4402      	add	r2, r0
 80063dc:	4293      	cmp	r3, r2
 80063de:	d100      	bne.n	80063e2 <memset+0xa>
 80063e0:	4770      	bx	lr
 80063e2:	f803 1b01 	strb.w	r1, [r3], #1
 80063e6:	e7f9      	b.n	80063dc <memset+0x4>

080063e8 <iprintf>:
 80063e8:	b40f      	push	{r0, r1, r2, r3}
 80063ea:	4b0a      	ldr	r3, [pc, #40]	; (8006414 <iprintf+0x2c>)
 80063ec:	b513      	push	{r0, r1, r4, lr}
 80063ee:	681c      	ldr	r4, [r3, #0]
 80063f0:	b124      	cbz	r4, 80063fc <iprintf+0x14>
 80063f2:	69a3      	ldr	r3, [r4, #24]
 80063f4:	b913      	cbnz	r3, 80063fc <iprintf+0x14>
 80063f6:	4620      	mov	r0, r4
 80063f8:	f000 faee 	bl	80069d8 <__sinit>
 80063fc:	ab05      	add	r3, sp, #20
 80063fe:	9a04      	ldr	r2, [sp, #16]
 8006400:	68a1      	ldr	r1, [r4, #8]
 8006402:	4620      	mov	r0, r4
 8006404:	9301      	str	r3, [sp, #4]
 8006406:	f000 fcaf 	bl	8006d68 <_vfiprintf_r>
 800640a:	b002      	add	sp, #8
 800640c:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
 8006410:	b004      	add	sp, #16
 8006412:	4770      	bx	lr
 8006414:	2000000c 	.word	0x2000000c

08006418 <putchar>:
 8006418:	b538      	push	{r3, r4, r5, lr}
 800641a:	4b08      	ldr	r3, [pc, #32]	; (800643c <putchar+0x24>)
 800641c:	4605      	mov	r5, r0
 800641e:	681c      	ldr	r4, [r3, #0]
 8006420:	b124      	cbz	r4, 800642c <putchar+0x14>
 8006422:	69a3      	ldr	r3, [r4, #24]
 8006424:	b913      	cbnz	r3, 800642c <putchar+0x14>
 8006426:	4620      	mov	r0, r4
 8006428:	f000 fad6 	bl	80069d8 <__sinit>
 800642c:	68a2      	ldr	r2, [r4, #8]
 800642e:	4629      	mov	r1, r5
 8006430:	4620      	mov	r0, r4
 8006432:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
 8006436:	f000 bf45 	b.w	80072c4 <_putc_r>
 800643a:	bf00      	nop
 800643c:	2000000c 	.word	0x2000000c

08006440 <_puts_r>:
 8006440:	b570      	push	{r4, r5, r6, lr}
 8006442:	460e      	mov	r6, r1
 8006444:	4605      	mov	r5, r0
 8006446:	b118      	cbz	r0, 8006450 <_puts_r+0x10>
 8006448:	6983      	ldr	r3, [r0, #24]
 800644a:	b90b      	cbnz	r3, 8006450 <_puts_r+0x10>
 800644c:	f000 fac4 	bl	80069d8 <__sinit>
 8006450:	69ab      	ldr	r3, [r5, #24]
 8006452:	68ac      	ldr	r4, [r5, #8]
 8006454:	b913      	cbnz	r3, 800645c <_puts_r+0x1c>
 8006456:	4628      	mov	r0, r5
 8006458:	f000 fabe 	bl	80069d8 <__sinit>
 800645c:	4b23      	ldr	r3, [pc, #140]	; (80064ec <_puts_r+0xac>)
 800645e:	429c      	cmp	r4, r3
 8006460:	d117      	bne.n	8006492 <_puts_r+0x52>
 8006462:	686c      	ldr	r4, [r5, #4]
 8006464:	89a3      	ldrh	r3, [r4, #12]
 8006466:	071b      	lsls	r3, r3, #28
 8006468:	d51d      	bpl.n	80064a6 <_puts_r+0x66>
 800646a:	6923      	ldr	r3, [r4, #16]
 800646c:	b1db      	cbz	r3, 80064a6 <_puts_r+0x66>
 800646e:	3e01      	subs	r6, #1
 8006470:	68a3      	ldr	r3, [r4, #8]
 8006472:	f816 1f01 	ldrb.w	r1, [r6, #1]!
 8006476:	3b01      	subs	r3, #1
 8006478:	60a3      	str	r3, [r4, #8]
 800647a:	b9e9      	cbnz	r1, 80064b8 <_puts_r+0x78>
 800647c:	2b00      	cmp	r3, #0
 800647e:	da2e      	bge.n	80064de <_puts_r+0x9e>
 8006480:	4622      	mov	r2, r4
 8006482:	210a      	movs	r1, #10
 8006484:	4628      	mov	r0, r5
 8006486:	f000 f8f5 	bl	8006674 <__swbuf_r>
 800648a:	3001      	adds	r0, #1
 800648c:	d011      	beq.n	80064b2 <_puts_r+0x72>
 800648e:	200a      	movs	r0, #10
 8006490:	bd70      	pop	{r4, r5, r6, pc}
 8006492:	4b17      	ldr	r3, [pc, #92]	; (80064f0 <_puts_r+0xb0>)
 8006494:	429c      	cmp	r4, r3
 8006496:	d101      	bne.n	800649c <_puts_r+0x5c>
 8006498:	68ac      	ldr	r4, [r5, #8]
 800649a:	e7e3      	b.n	8006464 <_puts_r+0x24>
 800649c:	4b15      	ldr	r3, [pc, #84]	; (80064f4 <_puts_r+0xb4>)
 800649e:	429c      	cmp	r4, r3
 80064a0:	bf08      	it	eq
 80064a2:	68ec      	ldreq	r4, [r5, #12]
 80064a4:	e7de      	b.n	8006464 <_puts_r+0x24>
 80064a6:	4621      	mov	r1, r4
 80064a8:	4628      	mov	r0, r5
 80064aa:	f000 f935 	bl	8006718 <__swsetup_r>
 80064ae:	2800      	cmp	r0, #0
 80064b0:	d0dd      	beq.n	800646e <_puts_r+0x2e>
 80064b2:	f04f 30ff 	mov.w	r0, #4294967295
 80064b6:	bd70      	pop	{r4, r5, r6, pc}
 80064b8:	2b00      	cmp	r3, #0
 80064ba:	da04      	bge.n	80064c6 <_puts_r+0x86>
 80064bc:	69a2      	ldr	r2, [r4, #24]
 80064be:	4293      	cmp	r3, r2
 80064c0:	db06      	blt.n	80064d0 <_puts_r+0x90>
 80064c2:	290a      	cmp	r1, #10
 80064c4:	d004      	beq.n	80064d0 <_puts_r+0x90>
 80064c6:	6823      	ldr	r3, [r4, #0]
 80064c8:	1c5a      	adds	r2, r3, #1
 80064ca:	6022      	str	r2, [r4, #0]
 80064cc:	7019      	strb	r1, [r3, #0]
 80064ce:	e7cf      	b.n	8006470 <_puts_r+0x30>
 80064d0:	4622      	mov	r2, r4
 80064d2:	4628      	mov	r0, r5
 80064d4:	f000 f8ce 	bl	8006674 <__swbuf_r>
 80064d8:	3001      	adds	r0, #1
 80064da:	d1c9      	bne.n	8006470 <_puts_r+0x30>
 80064dc:	e7e9      	b.n	80064b2 <_puts_r+0x72>
 80064de:	200a      	movs	r0, #10
 80064e0:	6823      	ldr	r3, [r4, #0]
 80064e2:	1c5a      	adds	r2, r3, #1
 80064e4:	6022      	str	r2, [r4, #0]
 80064e6:	7018      	strb	r0, [r3, #0]
 80064e8:	bd70      	pop	{r4, r5, r6, pc}
 80064ea:	bf00      	nop
 80064ec:	08007570 	.word	0x08007570
 80064f0:	08007590 	.word	0x08007590
 80064f4:	08007550 	.word	0x08007550

080064f8 <puts>:
 80064f8:	4b02      	ldr	r3, [pc, #8]	; (8006504 <puts+0xc>)
 80064fa:	4601      	mov	r1, r0
 80064fc:	6818      	ldr	r0, [r3, #0]
 80064fe:	f7ff bf9f 	b.w	8006440 <_puts_r>
 8006502:	bf00      	nop
 8006504:	2000000c 	.word	0x2000000c

08006508 <setbuf>:
 8006508:	2900      	cmp	r1, #0
 800650a:	f44f 6380 	mov.w	r3, #1024	; 0x400
 800650e:	bf0c      	ite	eq
 8006510:	2202      	moveq	r2, #2
 8006512:	2200      	movne	r2, #0
 8006514:	f000 b800 	b.w	8006518 <setvbuf>

08006518 <setvbuf>:
 8006518:	e92d 43f7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
 800651c:	461d      	mov	r5, r3
 800651e:	4b51      	ldr	r3, [pc, #324]	; (8006664 <setvbuf+0x14c>)
 8006520:	4604      	mov	r4, r0
 8006522:	681e      	ldr	r6, [r3, #0]
 8006524:	460f      	mov	r7, r1
 8006526:	4690      	mov	r8, r2
 8006528:	b126      	cbz	r6, 8006534 <setvbuf+0x1c>
 800652a:	69b3      	ldr	r3, [r6, #24]
 800652c:	b913      	cbnz	r3, 8006534 <setvbuf+0x1c>
 800652e:	4630      	mov	r0, r6
 8006530:	f000 fa52 	bl	80069d8 <__sinit>
 8006534:	4b4c      	ldr	r3, [pc, #304]	; (8006668 <setvbuf+0x150>)
 8006536:	429c      	cmp	r4, r3
 8006538:	d152      	bne.n	80065e0 <setvbuf+0xc8>
 800653a:	6874      	ldr	r4, [r6, #4]
 800653c:	f1b8 0f02 	cmp.w	r8, #2
 8006540:	d006      	beq.n	8006550 <setvbuf+0x38>
 8006542:	f1b8 0f01 	cmp.w	r8, #1
 8006546:	f200 8089 	bhi.w	800665c <setvbuf+0x144>
 800654a:	2d00      	cmp	r5, #0
 800654c:	f2c0 8086 	blt.w	800665c <setvbuf+0x144>
 8006550:	4621      	mov	r1, r4
 8006552:	4630      	mov	r0, r6
 8006554:	f000 f9d6 	bl	8006904 <_fflush_r>
 8006558:	6b61      	ldr	r1, [r4, #52]	; 0x34
 800655a:	b141      	cbz	r1, 800656e <setvbuf+0x56>
 800655c:	f104 0344 	add.w	r3, r4, #68	; 0x44
 8006560:	4299      	cmp	r1, r3
 8006562:	d002      	beq.n	800656a <setvbuf+0x52>
 8006564:	4630      	mov	r0, r6
 8006566:	f000 fb2d 	bl	8006bc4 <_free_r>
 800656a:	2300      	movs	r3, #0
 800656c:	6363      	str	r3, [r4, #52]	; 0x34
 800656e:	2300      	movs	r3, #0
 8006570:	61a3      	str	r3, [r4, #24]
 8006572:	6063      	str	r3, [r4, #4]
 8006574:	89a3      	ldrh	r3, [r4, #12]
 8006576:	061b      	lsls	r3, r3, #24
 8006578:	d503      	bpl.n	8006582 <setvbuf+0x6a>
 800657a:	6921      	ldr	r1, [r4, #16]
 800657c:	4630      	mov	r0, r6
 800657e:	f000 fb21 	bl	8006bc4 <_free_r>
 8006582:	89a3      	ldrh	r3, [r4, #12]
 8006584:	f1b8 0f02 	cmp.w	r8, #2
 8006588:	f423 634a 	bic.w	r3, r3, #3232	; 0xca0
 800658c:	f023 0303 	bic.w	r3, r3, #3
 8006590:	81a3      	strh	r3, [r4, #12]
 8006592:	d05d      	beq.n	8006650 <setvbuf+0x138>
 8006594:	ab01      	add	r3, sp, #4
 8006596:	466a      	mov	r2, sp
 8006598:	4621      	mov	r1, r4
 800659a:	4630      	mov	r0, r6
 800659c:	f000 faa6 	bl	8006aec <__swhatbuf_r>
 80065a0:	89a3      	ldrh	r3, [r4, #12]
 80065a2:	4318      	orrs	r0, r3
 80065a4:	81a0      	strh	r0, [r4, #12]
 80065a6:	bb2d      	cbnz	r5, 80065f4 <setvbuf+0xdc>
 80065a8:	9d00      	ldr	r5, [sp, #0]
 80065aa:	4628      	mov	r0, r5
 80065ac:	f000 fb02 	bl	8006bb4 <malloc>
 80065b0:	4607      	mov	r7, r0
 80065b2:	2800      	cmp	r0, #0
 80065b4:	d14e      	bne.n	8006654 <setvbuf+0x13c>
 80065b6:	f8dd 9000 	ldr.w	r9, [sp]
 80065ba:	45a9      	cmp	r9, r5
 80065bc:	d13c      	bne.n	8006638 <setvbuf+0x120>
 80065be:	f04f 30ff 	mov.w	r0, #4294967295
 80065c2:	89a3      	ldrh	r3, [r4, #12]
 80065c4:	f043 0302 	orr.w	r3, r3, #2
 80065c8:	81a3      	strh	r3, [r4, #12]
 80065ca:	2300      	movs	r3, #0
 80065cc:	60a3      	str	r3, [r4, #8]
 80065ce:	f104 0347 	add.w	r3, r4, #71	; 0x47
 80065d2:	6023      	str	r3, [r4, #0]
 80065d4:	6123      	str	r3, [r4, #16]
 80065d6:	2301      	movs	r3, #1
 80065d8:	6163      	str	r3, [r4, #20]
 80065da:	b003      	add	sp, #12
 80065dc:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
 80065e0:	4b22      	ldr	r3, [pc, #136]	; (800666c <setvbuf+0x154>)
 80065e2:	429c      	cmp	r4, r3
 80065e4:	d101      	bne.n	80065ea <setvbuf+0xd2>
 80065e6:	68b4      	ldr	r4, [r6, #8]
 80065e8:	e7a8      	b.n	800653c <setvbuf+0x24>
 80065ea:	4b21      	ldr	r3, [pc, #132]	; (8006670 <setvbuf+0x158>)
 80065ec:	429c      	cmp	r4, r3
 80065ee:	bf08      	it	eq
 80065f0:	68f4      	ldreq	r4, [r6, #12]
 80065f2:	e7a3      	b.n	800653c <setvbuf+0x24>
 80065f4:	2f00      	cmp	r7, #0
 80065f6:	d0d8      	beq.n	80065aa <setvbuf+0x92>
 80065f8:	69b3      	ldr	r3, [r6, #24]
 80065fa:	b913      	cbnz	r3, 8006602 <setvbuf+0xea>
 80065fc:	4630      	mov	r0, r6
 80065fe:	f000 f9eb 	bl	80069d8 <__sinit>
 8006602:	f1b8 0f01 	cmp.w	r8, #1
 8006606:	bf08      	it	eq
 8006608:	89a3      	ldrheq	r3, [r4, #12]
 800660a:	6027      	str	r7, [r4, #0]
 800660c:	bf04      	itt	eq
 800660e:	f043 0301 	orreq.w	r3, r3, #1
 8006612:	81a3      	strheq	r3, [r4, #12]
 8006614:	89a3      	ldrh	r3, [r4, #12]
 8006616:	6127      	str	r7, [r4, #16]
 8006618:	f013 0008 	ands.w	r0, r3, #8
 800661c:	6165      	str	r5, [r4, #20]
 800661e:	d01b      	beq.n	8006658 <setvbuf+0x140>
 8006620:	f013 0001 	ands.w	r0, r3, #1
 8006624:	f04f 0300 	mov.w	r3, #0
 8006628:	bf1f      	itttt	ne
 800662a:	426d      	negne	r5, r5
 800662c:	60a3      	strne	r3, [r4, #8]
 800662e:	61a5      	strne	r5, [r4, #24]
 8006630:	4618      	movne	r0, r3
 8006632:	bf08      	it	eq
 8006634:	60a5      	streq	r5, [r4, #8]
 8006636:	e7d0      	b.n	80065da <setvbuf+0xc2>
 8006638:	4648      	mov	r0, r9
 800663a:	f000 fabb 	bl	8006bb4 <malloc>
 800663e:	4607      	mov	r7, r0
 8006640:	2800      	cmp	r0, #0
 8006642:	d0bc      	beq.n	80065be <setvbuf+0xa6>
 8006644:	89a3      	ldrh	r3, [r4, #12]
 8006646:	464d      	mov	r5, r9
 8006648:	f043 0380 	orr.w	r3, r3, #128	; 0x80
 800664c:	81a3      	strh	r3, [r4, #12]
 800664e:	e7d3      	b.n	80065f8 <setvbuf+0xe0>
 8006650:	2000      	movs	r0, #0
 8006652:	e7b6      	b.n	80065c2 <setvbuf+0xaa>
 8006654:	46a9      	mov	r9, r5
 8006656:	e7f5      	b.n	8006644 <setvbuf+0x12c>
 8006658:	60a0      	str	r0, [r4, #8]
 800665a:	e7be      	b.n	80065da <setvbuf+0xc2>
 800665c:	f04f 30ff 	mov.w	r0, #4294967295
 8006660:	e7bb      	b.n	80065da <setvbuf+0xc2>
 8006662:	bf00      	nop
 8006664:	2000000c 	.word	0x2000000c
 8006668:	08007570 	.word	0x08007570
 800666c:	08007590 	.word	0x08007590
 8006670:	08007550 	.word	0x08007550

08006674 <__swbuf_r>:
 8006674:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 8006676:	460e      	mov	r6, r1
 8006678:	4614      	mov	r4, r2
 800667a:	4605      	mov	r5, r0
 800667c:	b118      	cbz	r0, 8006686 <__swbuf_r+0x12>
 800667e:	6983      	ldr	r3, [r0, #24]
 8006680:	b90b      	cbnz	r3, 8006686 <__swbuf_r+0x12>
 8006682:	f000 f9a9 	bl	80069d8 <__sinit>
 8006686:	4b21      	ldr	r3, [pc, #132]	; (800670c <__swbuf_r+0x98>)
 8006688:	429c      	cmp	r4, r3
 800668a:	d12a      	bne.n	80066e2 <__swbuf_r+0x6e>
 800668c:	686c      	ldr	r4, [r5, #4]
 800668e:	69a3      	ldr	r3, [r4, #24]
 8006690:	60a3      	str	r3, [r4, #8]
 8006692:	89a3      	ldrh	r3, [r4, #12]
 8006694:	071a      	lsls	r2, r3, #28
 8006696:	d52e      	bpl.n	80066f6 <__swbuf_r+0x82>
 8006698:	6923      	ldr	r3, [r4, #16]
 800669a:	b363      	cbz	r3, 80066f6 <__swbuf_r+0x82>
 800669c:	6923      	ldr	r3, [r4, #16]
 800669e:	6820      	ldr	r0, [r4, #0]
 80066a0:	b2f6      	uxtb	r6, r6
 80066a2:	1ac0      	subs	r0, r0, r3
 80066a4:	6963      	ldr	r3, [r4, #20]
 80066a6:	4637      	mov	r7, r6
 80066a8:	4298      	cmp	r0, r3
 80066aa:	db04      	blt.n	80066b6 <__swbuf_r+0x42>
 80066ac:	4621      	mov	r1, r4
 80066ae:	4628      	mov	r0, r5
 80066b0:	f000 f928 	bl	8006904 <_fflush_r>
 80066b4:	bb28      	cbnz	r0, 8006702 <__swbuf_r+0x8e>
 80066b6:	68a3      	ldr	r3, [r4, #8]
 80066b8:	3001      	adds	r0, #1
 80066ba:	3b01      	subs	r3, #1
 80066bc:	60a3      	str	r3, [r4, #8]
 80066be:	6823      	ldr	r3, [r4, #0]
 80066c0:	1c5a      	adds	r2, r3, #1
 80066c2:	6022      	str	r2, [r4, #0]
 80066c4:	701e      	strb	r6, [r3, #0]
 80066c6:	6963      	ldr	r3, [r4, #20]
 80066c8:	4298      	cmp	r0, r3
 80066ca:	d004      	beq.n	80066d6 <__swbuf_r+0x62>
 80066cc:	89a3      	ldrh	r3, [r4, #12]
 80066ce:	07db      	lsls	r3, r3, #31
 80066d0:	d519      	bpl.n	8006706 <__swbuf_r+0x92>
 80066d2:	2e0a      	cmp	r6, #10
 80066d4:	d117      	bne.n	8006706 <__swbuf_r+0x92>
 80066d6:	4621      	mov	r1, r4
 80066d8:	4628      	mov	r0, r5
 80066da:	f000 f913 	bl	8006904 <_fflush_r>
 80066de:	b190      	cbz	r0, 8006706 <__swbuf_r+0x92>
 80066e0:	e00f      	b.n	8006702 <__swbuf_r+0x8e>
 80066e2:	4b0b      	ldr	r3, [pc, #44]	; (8006710 <__swbuf_r+0x9c>)
 80066e4:	429c      	cmp	r4, r3
 80066e6:	d101      	bne.n	80066ec <__swbuf_r+0x78>
 80066e8:	68ac      	ldr	r4, [r5, #8]
 80066ea:	e7d0      	b.n	800668e <__swbuf_r+0x1a>
 80066ec:	4b09      	ldr	r3, [pc, #36]	; (8006714 <__swbuf_r+0xa0>)
 80066ee:	429c      	cmp	r4, r3
 80066f0:	bf08      	it	eq
 80066f2:	68ec      	ldreq	r4, [r5, #12]
 80066f4:	e7cb      	b.n	800668e <__swbuf_r+0x1a>
 80066f6:	4621      	mov	r1, r4
 80066f8:	4628      	mov	r0, r5
 80066fa:	f000 f80d 	bl	8006718 <__swsetup_r>
 80066fe:	2800      	cmp	r0, #0
 8006700:	d0cc      	beq.n	800669c <__swbuf_r+0x28>
 8006702:	f04f 37ff 	mov.w	r7, #4294967295
 8006706:	4638      	mov	r0, r7
 8006708:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
 800670a:	bf00      	nop
 800670c:	08007570 	.word	0x08007570
 8006710:	08007590 	.word	0x08007590
 8006714:	08007550 	.word	0x08007550

08006718 <__swsetup_r>:
 8006718:	4b32      	ldr	r3, [pc, #200]	; (80067e4 <__swsetup_r+0xcc>)
 800671a:	b570      	push	{r4, r5, r6, lr}
 800671c:	681d      	ldr	r5, [r3, #0]
 800671e:	4606      	mov	r6, r0
 8006720:	460c      	mov	r4, r1
 8006722:	b125      	cbz	r5, 800672e <__swsetup_r+0x16>
 8006724:	69ab      	ldr	r3, [r5, #24]
 8006726:	b913      	cbnz	r3, 800672e <__swsetup_r+0x16>
 8006728:	4628      	mov	r0, r5
 800672a:	f000 f955 	bl	80069d8 <__sinit>
 800672e:	4b2e      	ldr	r3, [pc, #184]	; (80067e8 <__swsetup_r+0xd0>)
 8006730:	429c      	cmp	r4, r3
 8006732:	d10f      	bne.n	8006754 <__swsetup_r+0x3c>
 8006734:	686c      	ldr	r4, [r5, #4]
 8006736:	f9b4 300c 	ldrsh.w	r3, [r4, #12]
 800673a:	b29a      	uxth	r2, r3
 800673c:	0715      	lsls	r5, r2, #28
 800673e:	d42c      	bmi.n	800679a <__swsetup_r+0x82>
 8006740:	06d0      	lsls	r0, r2, #27
 8006742:	d411      	bmi.n	8006768 <__swsetup_r+0x50>
 8006744:	2209      	movs	r2, #9
 8006746:	6032      	str	r2, [r6, #0]
 8006748:	f043 0340 	orr.w	r3, r3, #64	; 0x40
 800674c:	81a3      	strh	r3, [r4, #12]
 800674e:	f04f 30ff 	mov.w	r0, #4294967295
 8006752:	bd70      	pop	{r4, r5, r6, pc}
 8006754:	4b25      	ldr	r3, [pc, #148]	; (80067ec <__swsetup_r+0xd4>)
 8006756:	429c      	cmp	r4, r3
 8006758:	d101      	bne.n	800675e <__swsetup_r+0x46>
 800675a:	68ac      	ldr	r4, [r5, #8]
 800675c:	e7eb      	b.n	8006736 <__swsetup_r+0x1e>
 800675e:	4b24      	ldr	r3, [pc, #144]	; (80067f0 <__swsetup_r+0xd8>)
 8006760:	429c      	cmp	r4, r3
 8006762:	bf08      	it	eq
 8006764:	68ec      	ldreq	r4, [r5, #12]
 8006766:	e7e6      	b.n	8006736 <__swsetup_r+0x1e>
 8006768:	0751      	lsls	r1, r2, #29
 800676a:	d512      	bpl.n	8006792 <__swsetup_r+0x7a>
 800676c:	6b61      	ldr	r1, [r4, #52]	; 0x34
 800676e:	b141      	cbz	r1, 8006782 <__swsetup_r+0x6a>
 8006770:	f104 0344 	add.w	r3, r4, #68	; 0x44
 8006774:	4299      	cmp	r1, r3
 8006776:	d002      	beq.n	800677e <__swsetup_r+0x66>
 8006778:	4630      	mov	r0, r6
 800677a:	f000 fa23 	bl	8006bc4 <_free_r>
 800677e:	2300      	movs	r3, #0
 8006780:	6363      	str	r3, [r4, #52]	; 0x34
 8006782:	89a3      	ldrh	r3, [r4, #12]
 8006784:	f023 0324 	bic.w	r3, r3, #36	; 0x24
 8006788:	81a3      	strh	r3, [r4, #12]
 800678a:	2300      	movs	r3, #0
 800678c:	6063      	str	r3, [r4, #4]
 800678e:	6923      	ldr	r3, [r4, #16]
 8006790:	6023      	str	r3, [r4, #0]
 8006792:	89a3      	ldrh	r3, [r4, #12]
 8006794:	f043 0308 	orr.w	r3, r3, #8
 8006798:	81a3      	strh	r3, [r4, #12]
 800679a:	6923      	ldr	r3, [r4, #16]
 800679c:	b94b      	cbnz	r3, 80067b2 <__swsetup_r+0x9a>
 800679e:	89a3      	ldrh	r3, [r4, #12]
 80067a0:	f403 7320 	and.w	r3, r3, #640	; 0x280
 80067a4:	f5b3 7f00 	cmp.w	r3, #512	; 0x200
 80067a8:	d003      	beq.n	80067b2 <__swsetup_r+0x9a>
 80067aa:	4621      	mov	r1, r4
 80067ac:	4630      	mov	r0, r6
 80067ae:	f000 f9c1 	bl	8006b34 <__smakebuf_r>
 80067b2:	89a2      	ldrh	r2, [r4, #12]
 80067b4:	f012 0301 	ands.w	r3, r2, #1
 80067b8:	d00c      	beq.n	80067d4 <__swsetup_r+0xbc>
 80067ba:	2300      	movs	r3, #0
 80067bc:	60a3      	str	r3, [r4, #8]
 80067be:	6963      	ldr	r3, [r4, #20]
 80067c0:	425b      	negs	r3, r3
 80067c2:	61a3      	str	r3, [r4, #24]
 80067c4:	6923      	ldr	r3, [r4, #16]
 80067c6:	b953      	cbnz	r3, 80067de <__swsetup_r+0xc6>
 80067c8:	f9b4 300c 	ldrsh.w	r3, [r4, #12]
 80067cc:	f013 0080 	ands.w	r0, r3, #128	; 0x80
 80067d0:	d1ba      	bne.n	8006748 <__swsetup_r+0x30>
 80067d2:	bd70      	pop	{r4, r5, r6, pc}
 80067d4:	0792      	lsls	r2, r2, #30
 80067d6:	bf58      	it	pl
 80067d8:	6963      	ldrpl	r3, [r4, #20]
 80067da:	60a3      	str	r3, [r4, #8]
 80067dc:	e7f2      	b.n	80067c4 <__swsetup_r+0xac>
 80067de:	2000      	movs	r0, #0
 80067e0:	e7f7      	b.n	80067d2 <__swsetup_r+0xba>
 80067e2:	bf00      	nop
 80067e4:	2000000c 	.word	0x2000000c
 80067e8:	08007570 	.word	0x08007570
 80067ec:	08007590 	.word	0x08007590
 80067f0:	08007550 	.word	0x08007550

080067f4 <__sflush_r>:
 80067f4:	898a      	ldrh	r2, [r1, #12]
 80067f6:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
 80067fa:	4605      	mov	r5, r0
 80067fc:	0710      	lsls	r0, r2, #28
 80067fe:	460c      	mov	r4, r1
 8006800:	d45a      	bmi.n	80068b8 <__sflush_r+0xc4>
 8006802:	684b      	ldr	r3, [r1, #4]
 8006804:	2b00      	cmp	r3, #0
 8006806:	dc05      	bgt.n	8006814 <__sflush_r+0x20>
 8006808:	6c0b      	ldr	r3, [r1, #64]	; 0x40
 800680a:	2b00      	cmp	r3, #0
 800680c:	dc02      	bgt.n	8006814 <__sflush_r+0x20>
 800680e:	2000      	movs	r0, #0
 8006810:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
 8006814:	6ae6      	ldr	r6, [r4, #44]	; 0x2c
 8006816:	2e00      	cmp	r6, #0
 8006818:	d0f9      	beq.n	800680e <__sflush_r+0x1a>
 800681a:	2300      	movs	r3, #0
 800681c:	f412 5280 	ands.w	r2, r2, #4096	; 0x1000
 8006820:	682f      	ldr	r7, [r5, #0]
 8006822:	602b      	str	r3, [r5, #0]
 8006824:	d033      	beq.n	800688e <__sflush_r+0x9a>
 8006826:	6d60      	ldr	r0, [r4, #84]	; 0x54
 8006828:	89a3      	ldrh	r3, [r4, #12]
 800682a:	075a      	lsls	r2, r3, #29
 800682c:	d505      	bpl.n	800683a <__sflush_r+0x46>
 800682e:	6863      	ldr	r3, [r4, #4]
 8006830:	1ac0      	subs	r0, r0, r3
 8006832:	6b63      	ldr	r3, [r4, #52]	; 0x34
 8006834:	b10b      	cbz	r3, 800683a <__sflush_r+0x46>
 8006836:	6c23      	ldr	r3, [r4, #64]	; 0x40
 8006838:	1ac0      	subs	r0, r0, r3
 800683a:	2300      	movs	r3, #0
 800683c:	4602      	mov	r2, r0
 800683e:	6ae6      	ldr	r6, [r4, #44]	; 0x2c
 8006840:	6a21      	ldr	r1, [r4, #32]
 8006842:	4628      	mov	r0, r5
 8006844:	47b0      	blx	r6
 8006846:	1c43      	adds	r3, r0, #1
 8006848:	89a3      	ldrh	r3, [r4, #12]
 800684a:	d106      	bne.n	800685a <__sflush_r+0x66>
 800684c:	6829      	ldr	r1, [r5, #0]
 800684e:	291d      	cmp	r1, #29
 8006850:	d84b      	bhi.n	80068ea <__sflush_r+0xf6>
 8006852:	4a2b      	ldr	r2, [pc, #172]	; (8006900 <__sflush_r+0x10c>)
 8006854:	40ca      	lsrs	r2, r1
 8006856:	07d6      	lsls	r6, r2, #31
 8006858:	d547      	bpl.n	80068ea <__sflush_r+0xf6>
 800685a:	2200      	movs	r2, #0
 800685c:	6062      	str	r2, [r4, #4]
 800685e:	6922      	ldr	r2, [r4, #16]
 8006860:	04d9      	lsls	r1, r3, #19
 8006862:	6022      	str	r2, [r4, #0]
 8006864:	d504      	bpl.n	8006870 <__sflush_r+0x7c>
 8006866:	1c42      	adds	r2, r0, #1
 8006868:	d101      	bne.n	800686e <__sflush_r+0x7a>
 800686a:	682b      	ldr	r3, [r5, #0]
 800686c:	b903      	cbnz	r3, 8006870 <__sflush_r+0x7c>
 800686e:	6560      	str	r0, [r4, #84]	; 0x54
 8006870:	6b61      	ldr	r1, [r4, #52]	; 0x34
 8006872:	602f      	str	r7, [r5, #0]
 8006874:	2900      	cmp	r1, #0
 8006876:	d0ca      	beq.n	800680e <__sflush_r+0x1a>
 8006878:	f104 0344 	add.w	r3, r4, #68	; 0x44
 800687c:	4299      	cmp	r1, r3
 800687e:	d002      	beq.n	8006886 <__sflush_r+0x92>
 8006880:	4628      	mov	r0, r5
 8006882:	f000 f99f 	bl	8006bc4 <_free_r>
 8006886:	2000      	movs	r0, #0
 8006888:	6360      	str	r0, [r4, #52]	; 0x34
 800688a:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
 800688e:	6a21      	ldr	r1, [r4, #32]
 8006890:	2301      	movs	r3, #1
 8006892:	4628      	mov	r0, r5
 8006894:	47b0      	blx	r6
 8006896:	1c41      	adds	r1, r0, #1
 8006898:	d1c6      	bne.n	8006828 <__sflush_r+0x34>
 800689a:	682b      	ldr	r3, [r5, #0]
 800689c:	2b00      	cmp	r3, #0
 800689e:	d0c3      	beq.n	8006828 <__sflush_r+0x34>
 80068a0:	2b1d      	cmp	r3, #29
 80068a2:	d001      	beq.n	80068a8 <__sflush_r+0xb4>
 80068a4:	2b16      	cmp	r3, #22
 80068a6:	d101      	bne.n	80068ac <__sflush_r+0xb8>
 80068a8:	602f      	str	r7, [r5, #0]
 80068aa:	e7b0      	b.n	800680e <__sflush_r+0x1a>
 80068ac:	89a3      	ldrh	r3, [r4, #12]
 80068ae:	f043 0340 	orr.w	r3, r3, #64	; 0x40
 80068b2:	81a3      	strh	r3, [r4, #12]
 80068b4:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
 80068b8:	690f      	ldr	r7, [r1, #16]
 80068ba:	2f00      	cmp	r7, #0
 80068bc:	d0a7      	beq.n	800680e <__sflush_r+0x1a>
 80068be:	0793      	lsls	r3, r2, #30
 80068c0:	bf18      	it	ne
 80068c2:	2300      	movne	r3, #0
 80068c4:	680e      	ldr	r6, [r1, #0]
 80068c6:	bf08      	it	eq
 80068c8:	694b      	ldreq	r3, [r1, #20]
 80068ca:	eba6 0807 	sub.w	r8, r6, r7
 80068ce:	600f      	str	r7, [r1, #0]
 80068d0:	608b      	str	r3, [r1, #8]
 80068d2:	f1b8 0f00 	cmp.w	r8, #0
 80068d6:	dd9a      	ble.n	800680e <__sflush_r+0x1a>
 80068d8:	4643      	mov	r3, r8
 80068da:	463a      	mov	r2, r7
 80068dc:	6a21      	ldr	r1, [r4, #32]
 80068de:	4628      	mov	r0, r5
 80068e0:	6aa6      	ldr	r6, [r4, #40]	; 0x28
 80068e2:	47b0      	blx	r6
 80068e4:	2800      	cmp	r0, #0
 80068e6:	dc07      	bgt.n	80068f8 <__sflush_r+0x104>
 80068e8:	89a3      	ldrh	r3, [r4, #12]
 80068ea:	f043 0340 	orr.w	r3, r3, #64	; 0x40
 80068ee:	81a3      	strh	r3, [r4, #12]
 80068f0:	f04f 30ff 	mov.w	r0, #4294967295
 80068f4:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
 80068f8:	4407      	add	r7, r0
 80068fa:	eba8 0800 	sub.w	r8, r8, r0
 80068fe:	e7e8      	b.n	80068d2 <__sflush_r+0xde>
 8006900:	20400001 	.word	0x20400001

08006904 <_fflush_r>:
 8006904:	b538      	push	{r3, r4, r5, lr}
 8006906:	690b      	ldr	r3, [r1, #16]
 8006908:	4605      	mov	r5, r0
 800690a:	460c      	mov	r4, r1
 800690c:	b1db      	cbz	r3, 8006946 <_fflush_r+0x42>
 800690e:	b118      	cbz	r0, 8006918 <_fflush_r+0x14>
 8006910:	6983      	ldr	r3, [r0, #24]
 8006912:	b90b      	cbnz	r3, 8006918 <_fflush_r+0x14>
 8006914:	f000 f860 	bl	80069d8 <__sinit>
 8006918:	4b0c      	ldr	r3, [pc, #48]	; (800694c <_fflush_r+0x48>)
 800691a:	429c      	cmp	r4, r3
 800691c:	d109      	bne.n	8006932 <_fflush_r+0x2e>
 800691e:	686c      	ldr	r4, [r5, #4]
 8006920:	f9b4 300c 	ldrsh.w	r3, [r4, #12]
 8006924:	b17b      	cbz	r3, 8006946 <_fflush_r+0x42>
 8006926:	4621      	mov	r1, r4
 8006928:	4628      	mov	r0, r5
 800692a:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
 800692e:	f7ff bf61 	b.w	80067f4 <__sflush_r>
 8006932:	4b07      	ldr	r3, [pc, #28]	; (8006950 <_fflush_r+0x4c>)
 8006934:	429c      	cmp	r4, r3
 8006936:	d101      	bne.n	800693c <_fflush_r+0x38>
 8006938:	68ac      	ldr	r4, [r5, #8]
 800693a:	e7f1      	b.n	8006920 <_fflush_r+0x1c>
 800693c:	4b05      	ldr	r3, [pc, #20]	; (8006954 <_fflush_r+0x50>)
 800693e:	429c      	cmp	r4, r3
 8006940:	bf08      	it	eq
 8006942:	68ec      	ldreq	r4, [r5, #12]
 8006944:	e7ec      	b.n	8006920 <_fflush_r+0x1c>
 8006946:	2000      	movs	r0, #0
 8006948:	bd38      	pop	{r3, r4, r5, pc}
 800694a:	bf00      	nop
 800694c:	08007570 	.word	0x08007570
 8006950:	08007590 	.word	0x08007590
 8006954:	08007550 	.word	0x08007550

08006958 <_cleanup_r>:
 8006958:	4901      	ldr	r1, [pc, #4]	; (8006960 <_cleanup_r+0x8>)
 800695a:	f000 b8a9 	b.w	8006ab0 <_fwalk_reent>
 800695e:	bf00      	nop
 8006960:	08006905 	.word	0x08006905

08006964 <std.isra.0>:
 8006964:	2300      	movs	r3, #0
 8006966:	b510      	push	{r4, lr}
 8006968:	4604      	mov	r4, r0
 800696a:	6003      	str	r3, [r0, #0]
 800696c:	6043      	str	r3, [r0, #4]
 800696e:	6083      	str	r3, [r0, #8]
 8006970:	8181      	strh	r1, [r0, #12]
 8006972:	6643      	str	r3, [r0, #100]	; 0x64
 8006974:	81c2      	strh	r2, [r0, #14]
 8006976:	6103      	str	r3, [r0, #16]
 8006978:	6143      	str	r3, [r0, #20]
 800697a:	6183      	str	r3, [r0, #24]
 800697c:	4619      	mov	r1, r3
 800697e:	2208      	movs	r2, #8
 8006980:	305c      	adds	r0, #92	; 0x5c
 8006982:	f7ff fd29 	bl	80063d8 <memset>
 8006986:	4b05      	ldr	r3, [pc, #20]	; (800699c <std.isra.0+0x38>)
 8006988:	6224      	str	r4, [r4, #32]
 800698a:	6263      	str	r3, [r4, #36]	; 0x24
 800698c:	4b04      	ldr	r3, [pc, #16]	; (80069a0 <std.isra.0+0x3c>)
 800698e:	62a3      	str	r3, [r4, #40]	; 0x28
 8006990:	4b04      	ldr	r3, [pc, #16]	; (80069a4 <std.isra.0+0x40>)
 8006992:	62e3      	str	r3, [r4, #44]	; 0x2c
 8006994:	4b04      	ldr	r3, [pc, #16]	; (80069a8 <std.isra.0+0x44>)
 8006996:	6323      	str	r3, [r4, #48]	; 0x30
 8006998:	bd10      	pop	{r4, pc}
 800699a:	bf00      	nop
 800699c:	08007351 	.word	0x08007351
 80069a0:	08007373 	.word	0x08007373
 80069a4:	080073ab 	.word	0x080073ab
 80069a8:	080073cf 	.word	0x080073cf

080069ac <__sfmoreglue>:
 80069ac:	b570      	push	{r4, r5, r6, lr}
 80069ae:	2568      	movs	r5, #104	; 0x68
 80069b0:	1e4a      	subs	r2, r1, #1
 80069b2:	4355      	muls	r5, r2
 80069b4:	460e      	mov	r6, r1
 80069b6:	f105 0174 	add.w	r1, r5, #116	; 0x74
 80069ba:	f000 f94f 	bl	8006c5c <_malloc_r>
 80069be:	4604      	mov	r4, r0
 80069c0:	b140      	cbz	r0, 80069d4 <__sfmoreglue+0x28>
 80069c2:	2100      	movs	r1, #0
 80069c4:	e880 0042 	stmia.w	r0, {r1, r6}
 80069c8:	300c      	adds	r0, #12
 80069ca:	60a0      	str	r0, [r4, #8]
 80069cc:	f105 0268 	add.w	r2, r5, #104	; 0x68
 80069d0:	f7ff fd02 	bl	80063d8 <memset>
 80069d4:	4620      	mov	r0, r4
 80069d6:	bd70      	pop	{r4, r5, r6, pc}

080069d8 <__sinit>:
 80069d8:	6983      	ldr	r3, [r0, #24]
 80069da:	b510      	push	{r4, lr}
 80069dc:	4604      	mov	r4, r0
 80069de:	bb33      	cbnz	r3, 8006a2e <__sinit+0x56>
 80069e0:	6483      	str	r3, [r0, #72]	; 0x48
 80069e2:	64c3      	str	r3, [r0, #76]	; 0x4c
 80069e4:	6503      	str	r3, [r0, #80]	; 0x50
 80069e6:	4b12      	ldr	r3, [pc, #72]	; (8006a30 <__sinit+0x58>)
 80069e8:	4a12      	ldr	r2, [pc, #72]	; (8006a34 <__sinit+0x5c>)
 80069ea:	681b      	ldr	r3, [r3, #0]
 80069ec:	6282      	str	r2, [r0, #40]	; 0x28
 80069ee:	4298      	cmp	r0, r3
 80069f0:	bf04      	itt	eq
 80069f2:	2301      	moveq	r3, #1
 80069f4:	6183      	streq	r3, [r0, #24]
 80069f6:	f000 f81f 	bl	8006a38 <__sfp>
 80069fa:	6060      	str	r0, [r4, #4]
 80069fc:	4620      	mov	r0, r4
 80069fe:	f000 f81b 	bl	8006a38 <__sfp>
 8006a02:	60a0      	str	r0, [r4, #8]
 8006a04:	4620      	mov	r0, r4
 8006a06:	f000 f817 	bl	8006a38 <__sfp>
 8006a0a:	2200      	movs	r2, #0
 8006a0c:	60e0      	str	r0, [r4, #12]
 8006a0e:	2104      	movs	r1, #4
 8006a10:	6860      	ldr	r0, [r4, #4]
 8006a12:	f7ff ffa7 	bl	8006964 <std.isra.0>
 8006a16:	2201      	movs	r2, #1
 8006a18:	2109      	movs	r1, #9
 8006a1a:	68a0      	ldr	r0, [r4, #8]
 8006a1c:	f7ff ffa2 	bl	8006964 <std.isra.0>
 8006a20:	2202      	movs	r2, #2
 8006a22:	2112      	movs	r1, #18
 8006a24:	68e0      	ldr	r0, [r4, #12]
 8006a26:	f7ff ff9d 	bl	8006964 <std.isra.0>
 8006a2a:	2301      	movs	r3, #1
 8006a2c:	61a3      	str	r3, [r4, #24]
 8006a2e:	bd10      	pop	{r4, pc}
 8006a30:	0800754c 	.word	0x0800754c
 8006a34:	08006959 	.word	0x08006959

08006a38 <__sfp>:
 8006a38:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 8006a3a:	4b1c      	ldr	r3, [pc, #112]	; (8006aac <__sfp+0x74>)
 8006a3c:	4607      	mov	r7, r0
 8006a3e:	681e      	ldr	r6, [r3, #0]
 8006a40:	69b3      	ldr	r3, [r6, #24]
 8006a42:	b913      	cbnz	r3, 8006a4a <__sfp+0x12>
 8006a44:	4630      	mov	r0, r6
 8006a46:	f7ff ffc7 	bl	80069d8 <__sinit>
 8006a4a:	3648      	adds	r6, #72	; 0x48
 8006a4c:	68b4      	ldr	r4, [r6, #8]
 8006a4e:	6873      	ldr	r3, [r6, #4]
 8006a50:	3b01      	subs	r3, #1
 8006a52:	d503      	bpl.n	8006a5c <__sfp+0x24>
 8006a54:	6833      	ldr	r3, [r6, #0]
 8006a56:	b133      	cbz	r3, 8006a66 <__sfp+0x2e>
 8006a58:	6836      	ldr	r6, [r6, #0]
 8006a5a:	e7f7      	b.n	8006a4c <__sfp+0x14>
 8006a5c:	f9b4 500c 	ldrsh.w	r5, [r4, #12]
 8006a60:	b16d      	cbz	r5, 8006a7e <__sfp+0x46>
 8006a62:	3468      	adds	r4, #104	; 0x68
 8006a64:	e7f4      	b.n	8006a50 <__sfp+0x18>
 8006a66:	2104      	movs	r1, #4
 8006a68:	4638      	mov	r0, r7
 8006a6a:	f7ff ff9f 	bl	80069ac <__sfmoreglue>
 8006a6e:	6030      	str	r0, [r6, #0]
 8006a70:	2800      	cmp	r0, #0
 8006a72:	d1f1      	bne.n	8006a58 <__sfp+0x20>
 8006a74:	230c      	movs	r3, #12
 8006a76:	4604      	mov	r4, r0
 8006a78:	603b      	str	r3, [r7, #0]
 8006a7a:	4620      	mov	r0, r4
 8006a7c:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
 8006a7e:	f64f 73ff 	movw	r3, #65535	; 0xffff
 8006a82:	81e3      	strh	r3, [r4, #14]
 8006a84:	2301      	movs	r3, #1
 8006a86:	6665      	str	r5, [r4, #100]	; 0x64
 8006a88:	81a3      	strh	r3, [r4, #12]
 8006a8a:	6025      	str	r5, [r4, #0]
 8006a8c:	60a5      	str	r5, [r4, #8]
 8006a8e:	6065      	str	r5, [r4, #4]
 8006a90:	6125      	str	r5, [r4, #16]
 8006a92:	6165      	str	r5, [r4, #20]
 8006a94:	61a5      	str	r5, [r4, #24]
 8006a96:	2208      	movs	r2, #8
 8006a98:	4629      	mov	r1, r5
 8006a9a:	f104 005c 	add.w	r0, r4, #92	; 0x5c
 8006a9e:	f7ff fc9b 	bl	80063d8 <memset>
 8006aa2:	6365      	str	r5, [r4, #52]	; 0x34
 8006aa4:	63a5      	str	r5, [r4, #56]	; 0x38
 8006aa6:	64a5      	str	r5, [r4, #72]	; 0x48
 8006aa8:	64e5      	str	r5, [r4, #76]	; 0x4c
 8006aaa:	e7e6      	b.n	8006a7a <__sfp+0x42>
 8006aac:	0800754c 	.word	0x0800754c

08006ab0 <_fwalk_reent>:
 8006ab0:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
 8006ab4:	4680      	mov	r8, r0
 8006ab6:	4689      	mov	r9, r1
 8006ab8:	2600      	movs	r6, #0
 8006aba:	f100 0448 	add.w	r4, r0, #72	; 0x48
 8006abe:	b914      	cbnz	r4, 8006ac6 <_fwalk_reent+0x16>
 8006ac0:	4630      	mov	r0, r6
 8006ac2:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
 8006ac6:	68a5      	ldr	r5, [r4, #8]
 8006ac8:	6867      	ldr	r7, [r4, #4]
 8006aca:	3f01      	subs	r7, #1
 8006acc:	d501      	bpl.n	8006ad2 <_fwalk_reent+0x22>
 8006ace:	6824      	ldr	r4, [r4, #0]
 8006ad0:	e7f5      	b.n	8006abe <_fwalk_reent+0xe>
 8006ad2:	89ab      	ldrh	r3, [r5, #12]
 8006ad4:	2b01      	cmp	r3, #1
 8006ad6:	d907      	bls.n	8006ae8 <_fwalk_reent+0x38>
 8006ad8:	f9b5 300e 	ldrsh.w	r3, [r5, #14]
 8006adc:	3301      	adds	r3, #1
 8006ade:	d003      	beq.n	8006ae8 <_fwalk_reent+0x38>
 8006ae0:	4629      	mov	r1, r5
 8006ae2:	4640      	mov	r0, r8
 8006ae4:	47c8      	blx	r9
 8006ae6:	4306      	orrs	r6, r0
 8006ae8:	3568      	adds	r5, #104	; 0x68
 8006aea:	e7ee      	b.n	8006aca <_fwalk_reent+0x1a>

08006aec <__swhatbuf_r>:
 8006aec:	b570      	push	{r4, r5, r6, lr}
 8006aee:	460e      	mov	r6, r1
 8006af0:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 8006af4:	b090      	sub	sp, #64	; 0x40
 8006af6:	2900      	cmp	r1, #0
 8006af8:	4614      	mov	r4, r2
 8006afa:	461d      	mov	r5, r3
 8006afc:	da07      	bge.n	8006b0e <__swhatbuf_r+0x22>
 8006afe:	2300      	movs	r3, #0
 8006b00:	602b      	str	r3, [r5, #0]
 8006b02:	89b3      	ldrh	r3, [r6, #12]
 8006b04:	061a      	lsls	r2, r3, #24
 8006b06:	d410      	bmi.n	8006b2a <__swhatbuf_r+0x3e>
 8006b08:	f44f 6380 	mov.w	r3, #1024	; 0x400
 8006b0c:	e00e      	b.n	8006b2c <__swhatbuf_r+0x40>
 8006b0e:	aa01      	add	r2, sp, #4
 8006b10:	f000 fc84 	bl	800741c <_fstat_r>
 8006b14:	2800      	cmp	r0, #0
 8006b16:	dbf2      	blt.n	8006afe <__swhatbuf_r+0x12>
 8006b18:	9a02      	ldr	r2, [sp, #8]
 8006b1a:	f402 4270 	and.w	r2, r2, #61440	; 0xf000
 8006b1e:	f5a2 5300 	sub.w	r3, r2, #8192	; 0x2000
 8006b22:	425a      	negs	r2, r3
 8006b24:	415a      	adcs	r2, r3
 8006b26:	602a      	str	r2, [r5, #0]
 8006b28:	e7ee      	b.n	8006b08 <__swhatbuf_r+0x1c>
 8006b2a:	2340      	movs	r3, #64	; 0x40
 8006b2c:	2000      	movs	r0, #0
 8006b2e:	6023      	str	r3, [r4, #0]
 8006b30:	b010      	add	sp, #64	; 0x40
 8006b32:	bd70      	pop	{r4, r5, r6, pc}

08006b34 <__smakebuf_r>:
 8006b34:	898b      	ldrh	r3, [r1, #12]
 8006b36:	b573      	push	{r0, r1, r4, r5, r6, lr}
 8006b38:	079d      	lsls	r5, r3, #30
 8006b3a:	4606      	mov	r6, r0
 8006b3c:	460c      	mov	r4, r1
 8006b3e:	d507      	bpl.n	8006b50 <__smakebuf_r+0x1c>
 8006b40:	f104 0347 	add.w	r3, r4, #71	; 0x47
 8006b44:	6023      	str	r3, [r4, #0]
 8006b46:	6123      	str	r3, [r4, #16]
 8006b48:	2301      	movs	r3, #1
 8006b4a:	6163      	str	r3, [r4, #20]
 8006b4c:	b002      	add	sp, #8
 8006b4e:	bd70      	pop	{r4, r5, r6, pc}
 8006b50:	ab01      	add	r3, sp, #4
 8006b52:	466a      	mov	r2, sp
 8006b54:	f7ff ffca 	bl	8006aec <__swhatbuf_r>
 8006b58:	9900      	ldr	r1, [sp, #0]
 8006b5a:	4605      	mov	r5, r0
 8006b5c:	4630      	mov	r0, r6
 8006b5e:	f000 f87d 	bl	8006c5c <_malloc_r>
 8006b62:	b948      	cbnz	r0, 8006b78 <__smakebuf_r+0x44>
 8006b64:	f9b4 300c 	ldrsh.w	r3, [r4, #12]
 8006b68:	059a      	lsls	r2, r3, #22
 8006b6a:	d4ef      	bmi.n	8006b4c <__smakebuf_r+0x18>
 8006b6c:	f023 0303 	bic.w	r3, r3, #3
 8006b70:	f043 0302 	orr.w	r3, r3, #2
 8006b74:	81a3      	strh	r3, [r4, #12]
 8006b76:	e7e3      	b.n	8006b40 <__smakebuf_r+0xc>
 8006b78:	4b0d      	ldr	r3, [pc, #52]	; (8006bb0 <__smakebuf_r+0x7c>)
 8006b7a:	62b3      	str	r3, [r6, #40]	; 0x28
 8006b7c:	89a3      	ldrh	r3, [r4, #12]
 8006b7e:	6020      	str	r0, [r4, #0]
 8006b80:	f043 0380 	orr.w	r3, r3, #128	; 0x80
 8006b84:	81a3      	strh	r3, [r4, #12]
 8006b86:	9b00      	ldr	r3, [sp, #0]
 8006b88:	6120      	str	r0, [r4, #16]
 8006b8a:	6163      	str	r3, [r4, #20]
 8006b8c:	9b01      	ldr	r3, [sp, #4]
 8006b8e:	b15b      	cbz	r3, 8006ba8 <__smakebuf_r+0x74>
 8006b90:	f9b4 100e 	ldrsh.w	r1, [r4, #14]
 8006b94:	4630      	mov	r0, r6
 8006b96:	f000 fc53 	bl	8007440 <_isatty_r>
 8006b9a:	b128      	cbz	r0, 8006ba8 <__smakebuf_r+0x74>
 8006b9c:	89a3      	ldrh	r3, [r4, #12]
 8006b9e:	f023 0303 	bic.w	r3, r3, #3
 8006ba2:	f043 0301 	orr.w	r3, r3, #1
 8006ba6:	81a3      	strh	r3, [r4, #12]
 8006ba8:	89a3      	ldrh	r3, [r4, #12]
 8006baa:	431d      	orrs	r5, r3
 8006bac:	81a5      	strh	r5, [r4, #12]
 8006bae:	e7cd      	b.n	8006b4c <__smakebuf_r+0x18>
 8006bb0:	08006959 	.word	0x08006959

08006bb4 <malloc>:
 8006bb4:	4b02      	ldr	r3, [pc, #8]	; (8006bc0 <malloc+0xc>)
 8006bb6:	4601      	mov	r1, r0
 8006bb8:	6818      	ldr	r0, [r3, #0]
 8006bba:	f000 b84f 	b.w	8006c5c <_malloc_r>
 8006bbe:	bf00      	nop
 8006bc0:	2000000c 	.word	0x2000000c

08006bc4 <_free_r>:
 8006bc4:	b538      	push	{r3, r4, r5, lr}
 8006bc6:	4605      	mov	r5, r0
 8006bc8:	2900      	cmp	r1, #0
 8006bca:	d043      	beq.n	8006c54 <_free_r+0x90>
 8006bcc:	f851 3c04 	ldr.w	r3, [r1, #-4]
 8006bd0:	1f0c      	subs	r4, r1, #4
 8006bd2:	2b00      	cmp	r3, #0
 8006bd4:	bfb8      	it	lt
 8006bd6:	18e4      	addlt	r4, r4, r3
 8006bd8:	f000 fc62 	bl	80074a0 <__malloc_lock>
 8006bdc:	4a1e      	ldr	r2, [pc, #120]	; (8006c58 <_free_r+0x94>)
 8006bde:	6813      	ldr	r3, [r2, #0]
 8006be0:	4610      	mov	r0, r2
 8006be2:	b933      	cbnz	r3, 8006bf2 <_free_r+0x2e>
 8006be4:	6063      	str	r3, [r4, #4]
 8006be6:	6014      	str	r4, [r2, #0]
 8006be8:	4628      	mov	r0, r5
 8006bea:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
 8006bee:	f000 bc58 	b.w	80074a2 <__malloc_unlock>
 8006bf2:	42a3      	cmp	r3, r4
 8006bf4:	d90b      	bls.n	8006c0e <_free_r+0x4a>
 8006bf6:	6821      	ldr	r1, [r4, #0]
 8006bf8:	1862      	adds	r2, r4, r1
 8006bfa:	4293      	cmp	r3, r2
 8006bfc:	bf01      	itttt	eq
 8006bfe:	681a      	ldreq	r2, [r3, #0]
 8006c00:	685b      	ldreq	r3, [r3, #4]
 8006c02:	1852      	addeq	r2, r2, r1
 8006c04:	6022      	streq	r2, [r4, #0]
 8006c06:	6063      	str	r3, [r4, #4]
 8006c08:	6004      	str	r4, [r0, #0]
 8006c0a:	e7ed      	b.n	8006be8 <_free_r+0x24>
 8006c0c:	4613      	mov	r3, r2
 8006c0e:	685a      	ldr	r2, [r3, #4]
 8006c10:	b10a      	cbz	r2, 8006c16 <_free_r+0x52>
 8006c12:	42a2      	cmp	r2, r4
 8006c14:	d9fa      	bls.n	8006c0c <_free_r+0x48>
 8006c16:	6819      	ldr	r1, [r3, #0]
 8006c18:	1858      	adds	r0, r3, r1
 8006c1a:	42a0      	cmp	r0, r4
 8006c1c:	d10b      	bne.n	8006c36 <_free_r+0x72>
 8006c1e:	6820      	ldr	r0, [r4, #0]
 8006c20:	4401      	add	r1, r0
 8006c22:	1858      	adds	r0, r3, r1
 8006c24:	4282      	cmp	r2, r0
 8006c26:	6019      	str	r1, [r3, #0]
 8006c28:	d1de      	bne.n	8006be8 <_free_r+0x24>
 8006c2a:	6810      	ldr	r0, [r2, #0]
 8006c2c:	6852      	ldr	r2, [r2, #4]
 8006c2e:	4401      	add	r1, r0
 8006c30:	6019      	str	r1, [r3, #0]
 8006c32:	605a      	str	r2, [r3, #4]
 8006c34:	e7d8      	b.n	8006be8 <_free_r+0x24>
 8006c36:	d902      	bls.n	8006c3e <_free_r+0x7a>
 8006c38:	230c      	movs	r3, #12
 8006c3a:	602b      	str	r3, [r5, #0]
 8006c3c:	e7d4      	b.n	8006be8 <_free_r+0x24>
 8006c3e:	6820      	ldr	r0, [r4, #0]
 8006c40:	1821      	adds	r1, r4, r0
 8006c42:	428a      	cmp	r2, r1
 8006c44:	bf01      	itttt	eq
 8006c46:	6811      	ldreq	r1, [r2, #0]
 8006c48:	6852      	ldreq	r2, [r2, #4]
 8006c4a:	1809      	addeq	r1, r1, r0
 8006c4c:	6021      	streq	r1, [r4, #0]
 8006c4e:	6062      	str	r2, [r4, #4]
 8006c50:	605c      	str	r4, [r3, #4]
 8006c52:	e7c9      	b.n	8006be8 <_free_r+0x24>
 8006c54:	bd38      	pop	{r3, r4, r5, pc}
 8006c56:	bf00      	nop
 8006c58:	2000109c 	.word	0x2000109c

08006c5c <_malloc_r>:
 8006c5c:	b570      	push	{r4, r5, r6, lr}
 8006c5e:	1ccd      	adds	r5, r1, #3
 8006c60:	f025 0503 	bic.w	r5, r5, #3
 8006c64:	3508      	adds	r5, #8
 8006c66:	2d0c      	cmp	r5, #12
 8006c68:	bf38      	it	cc
 8006c6a:	250c      	movcc	r5, #12
 8006c6c:	2d00      	cmp	r5, #0
 8006c6e:	4606      	mov	r6, r0
 8006c70:	db01      	blt.n	8006c76 <_malloc_r+0x1a>
 8006c72:	42a9      	cmp	r1, r5
 8006c74:	d903      	bls.n	8006c7e <_malloc_r+0x22>
 8006c76:	230c      	movs	r3, #12
 8006c78:	6033      	str	r3, [r6, #0]
 8006c7a:	2000      	movs	r0, #0
 8006c7c:	bd70      	pop	{r4, r5, r6, pc}
 8006c7e:	f000 fc0f 	bl	80074a0 <__malloc_lock>
 8006c82:	4a23      	ldr	r2, [pc, #140]	; (8006d10 <_malloc_r+0xb4>)
 8006c84:	6814      	ldr	r4, [r2, #0]
 8006c86:	4621      	mov	r1, r4
 8006c88:	b991      	cbnz	r1, 8006cb0 <_malloc_r+0x54>
 8006c8a:	4c22      	ldr	r4, [pc, #136]	; (8006d14 <_malloc_r+0xb8>)
 8006c8c:	6823      	ldr	r3, [r4, #0]
 8006c8e:	b91b      	cbnz	r3, 8006c98 <_malloc_r+0x3c>
 8006c90:	4630      	mov	r0, r6
 8006c92:	f000 fb4d 	bl	8007330 <_sbrk_r>
 8006c96:	6020      	str	r0, [r4, #0]
 8006c98:	4629      	mov	r1, r5
 8006c9a:	4630      	mov	r0, r6
 8006c9c:	f000 fb48 	bl	8007330 <_sbrk_r>
 8006ca0:	1c43      	adds	r3, r0, #1
 8006ca2:	d126      	bne.n	8006cf2 <_malloc_r+0x96>
 8006ca4:	230c      	movs	r3, #12
 8006ca6:	4630      	mov	r0, r6
 8006ca8:	6033      	str	r3, [r6, #0]
 8006caa:	f000 fbfa 	bl	80074a2 <__malloc_unlock>
 8006cae:	e7e4      	b.n	8006c7a <_malloc_r+0x1e>
 8006cb0:	680b      	ldr	r3, [r1, #0]
 8006cb2:	1b5b      	subs	r3, r3, r5
 8006cb4:	d41a      	bmi.n	8006cec <_malloc_r+0x90>
 8006cb6:	2b0b      	cmp	r3, #11
 8006cb8:	d90f      	bls.n	8006cda <_malloc_r+0x7e>
 8006cba:	600b      	str	r3, [r1, #0]
 8006cbc:	18cc      	adds	r4, r1, r3
 8006cbe:	50cd      	str	r5, [r1, r3]
 8006cc0:	4630      	mov	r0, r6
 8006cc2:	f000 fbee 	bl	80074a2 <__malloc_unlock>
 8006cc6:	f104 000b 	add.w	r0, r4, #11
 8006cca:	1d23      	adds	r3, r4, #4
 8006ccc:	f020 0007 	bic.w	r0, r0, #7
 8006cd0:	1ac3      	subs	r3, r0, r3
 8006cd2:	d01b      	beq.n	8006d0c <_malloc_r+0xb0>
 8006cd4:	425a      	negs	r2, r3
 8006cd6:	50e2      	str	r2, [r4, r3]
 8006cd8:	bd70      	pop	{r4, r5, r6, pc}
 8006cda:	428c      	cmp	r4, r1
 8006cdc:	bf0b      	itete	eq
 8006cde:	6863      	ldreq	r3, [r4, #4]
 8006ce0:	684b      	ldrne	r3, [r1, #4]
 8006ce2:	6013      	streq	r3, [r2, #0]
 8006ce4:	6063      	strne	r3, [r4, #4]
 8006ce6:	bf18      	it	ne
 8006ce8:	460c      	movne	r4, r1
 8006cea:	e7e9      	b.n	8006cc0 <_malloc_r+0x64>
 8006cec:	460c      	mov	r4, r1
 8006cee:	6849      	ldr	r1, [r1, #4]
 8006cf0:	e7ca      	b.n	8006c88 <_malloc_r+0x2c>
 8006cf2:	1cc4      	adds	r4, r0, #3
 8006cf4:	f024 0403 	bic.w	r4, r4, #3
 8006cf8:	42a0      	cmp	r0, r4
 8006cfa:	d005      	beq.n	8006d08 <_malloc_r+0xac>
 8006cfc:	1a21      	subs	r1, r4, r0
 8006cfe:	4630      	mov	r0, r6
 8006d00:	f000 fb16 	bl	8007330 <_sbrk_r>
 8006d04:	3001      	adds	r0, #1
 8006d06:	d0cd      	beq.n	8006ca4 <_malloc_r+0x48>
 8006d08:	6025      	str	r5, [r4, #0]
 8006d0a:	e7d9      	b.n	8006cc0 <_malloc_r+0x64>
 8006d0c:	bd70      	pop	{r4, r5, r6, pc}
 8006d0e:	bf00      	nop
 8006d10:	2000109c 	.word	0x2000109c
 8006d14:	200010a0 	.word	0x200010a0

08006d18 <__sfputc_r>:
 8006d18:	6893      	ldr	r3, [r2, #8]
 8006d1a:	b410      	push	{r4}
 8006d1c:	3b01      	subs	r3, #1
 8006d1e:	2b00      	cmp	r3, #0
 8006d20:	6093      	str	r3, [r2, #8]
 8006d22:	da08      	bge.n	8006d36 <__sfputc_r+0x1e>
 8006d24:	6994      	ldr	r4, [r2, #24]
 8006d26:	42a3      	cmp	r3, r4
 8006d28:	db02      	blt.n	8006d30 <__sfputc_r+0x18>
 8006d2a:	b2cb      	uxtb	r3, r1
 8006d2c:	2b0a      	cmp	r3, #10
 8006d2e:	d102      	bne.n	8006d36 <__sfputc_r+0x1e>
 8006d30:	bc10      	pop	{r4}
 8006d32:	f7ff bc9f 	b.w	8006674 <__swbuf_r>
 8006d36:	6813      	ldr	r3, [r2, #0]
 8006d38:	1c58      	adds	r0, r3, #1
 8006d3a:	6010      	str	r0, [r2, #0]
 8006d3c:	7019      	strb	r1, [r3, #0]
 8006d3e:	b2c8      	uxtb	r0, r1
 8006d40:	bc10      	pop	{r4}
 8006d42:	4770      	bx	lr

08006d44 <__sfputs_r>:
 8006d44:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 8006d46:	4606      	mov	r6, r0
 8006d48:	460f      	mov	r7, r1
 8006d4a:	4614      	mov	r4, r2
 8006d4c:	18d5      	adds	r5, r2, r3
 8006d4e:	42ac      	cmp	r4, r5
 8006d50:	d101      	bne.n	8006d56 <__sfputs_r+0x12>
 8006d52:	2000      	movs	r0, #0
 8006d54:	e007      	b.n	8006d66 <__sfputs_r+0x22>
 8006d56:	463a      	mov	r2, r7
 8006d58:	f814 1b01 	ldrb.w	r1, [r4], #1
 8006d5c:	4630      	mov	r0, r6
 8006d5e:	f7ff ffdb 	bl	8006d18 <__sfputc_r>
 8006d62:	1c43      	adds	r3, r0, #1
 8006d64:	d1f3      	bne.n	8006d4e <__sfputs_r+0xa>
 8006d66:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}

08006d68 <_vfiprintf_r>:
 8006d68:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
 8006d6c:	b09d      	sub	sp, #116	; 0x74
 8006d6e:	460c      	mov	r4, r1
 8006d70:	4617      	mov	r7, r2
 8006d72:	9303      	str	r3, [sp, #12]
 8006d74:	4606      	mov	r6, r0
 8006d76:	b118      	cbz	r0, 8006d80 <_vfiprintf_r+0x18>
 8006d78:	6983      	ldr	r3, [r0, #24]
 8006d7a:	b90b      	cbnz	r3, 8006d80 <_vfiprintf_r+0x18>
 8006d7c:	f7ff fe2c 	bl	80069d8 <__sinit>
 8006d80:	4b7c      	ldr	r3, [pc, #496]	; (8006f74 <_vfiprintf_r+0x20c>)
 8006d82:	429c      	cmp	r4, r3
 8006d84:	d157      	bne.n	8006e36 <_vfiprintf_r+0xce>
 8006d86:	6874      	ldr	r4, [r6, #4]
 8006d88:	89a3      	ldrh	r3, [r4, #12]
 8006d8a:	0718      	lsls	r0, r3, #28
 8006d8c:	d55d      	bpl.n	8006e4a <_vfiprintf_r+0xe2>
 8006d8e:	6923      	ldr	r3, [r4, #16]
 8006d90:	2b00      	cmp	r3, #0
 8006d92:	d05a      	beq.n	8006e4a <_vfiprintf_r+0xe2>
 8006d94:	2300      	movs	r3, #0
 8006d96:	9309      	str	r3, [sp, #36]	; 0x24
 8006d98:	2320      	movs	r3, #32
 8006d9a:	f88d 3029 	strb.w	r3, [sp, #41]	; 0x29
 8006d9e:	2330      	movs	r3, #48	; 0x30
 8006da0:	f04f 0b01 	mov.w	fp, #1
 8006da4:	f88d 302a 	strb.w	r3, [sp, #42]	; 0x2a
 8006da8:	46b8      	mov	r8, r7
 8006daa:	4645      	mov	r5, r8
 8006dac:	f815 3b01 	ldrb.w	r3, [r5], #1
 8006db0:	2b00      	cmp	r3, #0
 8006db2:	d155      	bne.n	8006e60 <_vfiprintf_r+0xf8>
 8006db4:	ebb8 0a07 	subs.w	sl, r8, r7
 8006db8:	d00b      	beq.n	8006dd2 <_vfiprintf_r+0x6a>
 8006dba:	4653      	mov	r3, sl
 8006dbc:	463a      	mov	r2, r7
 8006dbe:	4621      	mov	r1, r4
 8006dc0:	4630      	mov	r0, r6
 8006dc2:	f7ff ffbf 	bl	8006d44 <__sfputs_r>
 8006dc6:	3001      	adds	r0, #1
 8006dc8:	f000 80c4 	beq.w	8006f54 <_vfiprintf_r+0x1ec>
 8006dcc:	9b09      	ldr	r3, [sp, #36]	; 0x24
 8006dce:	4453      	add	r3, sl
 8006dd0:	9309      	str	r3, [sp, #36]	; 0x24
 8006dd2:	f898 3000 	ldrb.w	r3, [r8]
 8006dd6:	2b00      	cmp	r3, #0
 8006dd8:	f000 80bc 	beq.w	8006f54 <_vfiprintf_r+0x1ec>
 8006ddc:	2300      	movs	r3, #0
 8006dde:	f04f 32ff 	mov.w	r2, #4294967295
 8006de2:	9304      	str	r3, [sp, #16]
 8006de4:	9307      	str	r3, [sp, #28]
 8006de6:	9205      	str	r2, [sp, #20]
 8006de8:	9306      	str	r3, [sp, #24]
 8006dea:	f88d 3053 	strb.w	r3, [sp, #83]	; 0x53
 8006dee:	931a      	str	r3, [sp, #104]	; 0x68
 8006df0:	2205      	movs	r2, #5
 8006df2:	7829      	ldrb	r1, [r5, #0]
 8006df4:	4860      	ldr	r0, [pc, #384]	; (8006f78 <_vfiprintf_r+0x210>)
 8006df6:	f000 fb45 	bl	8007484 <memchr>
 8006dfa:	f105 0801 	add.w	r8, r5, #1
 8006dfe:	9b04      	ldr	r3, [sp, #16]
 8006e00:	2800      	cmp	r0, #0
 8006e02:	d131      	bne.n	8006e68 <_vfiprintf_r+0x100>
 8006e04:	06d9      	lsls	r1, r3, #27
 8006e06:	bf44      	itt	mi
 8006e08:	2220      	movmi	r2, #32
 8006e0a:	f88d 2053 	strbmi.w	r2, [sp, #83]	; 0x53
 8006e0e:	071a      	lsls	r2, r3, #28
 8006e10:	bf44      	itt	mi
 8006e12:	222b      	movmi	r2, #43	; 0x2b
 8006e14:	f88d 2053 	strbmi.w	r2, [sp, #83]	; 0x53
 8006e18:	782a      	ldrb	r2, [r5, #0]
 8006e1a:	2a2a      	cmp	r2, #42	; 0x2a
 8006e1c:	d02c      	beq.n	8006e78 <_vfiprintf_r+0x110>
 8006e1e:	2100      	movs	r1, #0
 8006e20:	200a      	movs	r0, #10
 8006e22:	9a07      	ldr	r2, [sp, #28]
 8006e24:	46a8      	mov	r8, r5
 8006e26:	f898 3000 	ldrb.w	r3, [r8]
 8006e2a:	3501      	adds	r5, #1
 8006e2c:	3b30      	subs	r3, #48	; 0x30
 8006e2e:	2b09      	cmp	r3, #9
 8006e30:	d96d      	bls.n	8006f0e <_vfiprintf_r+0x1a6>
 8006e32:	b371      	cbz	r1, 8006e92 <_vfiprintf_r+0x12a>
 8006e34:	e026      	b.n	8006e84 <_vfiprintf_r+0x11c>
 8006e36:	4b51      	ldr	r3, [pc, #324]	; (8006f7c <_vfiprintf_r+0x214>)
 8006e38:	429c      	cmp	r4, r3
 8006e3a:	d101      	bne.n	8006e40 <_vfiprintf_r+0xd8>
 8006e3c:	68b4      	ldr	r4, [r6, #8]
 8006e3e:	e7a3      	b.n	8006d88 <_vfiprintf_r+0x20>
 8006e40:	4b4f      	ldr	r3, [pc, #316]	; (8006f80 <_vfiprintf_r+0x218>)
 8006e42:	429c      	cmp	r4, r3
 8006e44:	bf08      	it	eq
 8006e46:	68f4      	ldreq	r4, [r6, #12]
 8006e48:	e79e      	b.n	8006d88 <_vfiprintf_r+0x20>
 8006e4a:	4621      	mov	r1, r4
 8006e4c:	4630      	mov	r0, r6
 8006e4e:	f7ff fc63 	bl	8006718 <__swsetup_r>
 8006e52:	2800      	cmp	r0, #0
 8006e54:	d09e      	beq.n	8006d94 <_vfiprintf_r+0x2c>
 8006e56:	f04f 30ff 	mov.w	r0, #4294967295
 8006e5a:	b01d      	add	sp, #116	; 0x74
 8006e5c:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
 8006e60:	2b25      	cmp	r3, #37	; 0x25
 8006e62:	d0a7      	beq.n	8006db4 <_vfiprintf_r+0x4c>
 8006e64:	46a8      	mov	r8, r5
 8006e66:	e7a0      	b.n	8006daa <_vfiprintf_r+0x42>
 8006e68:	4a43      	ldr	r2, [pc, #268]	; (8006f78 <_vfiprintf_r+0x210>)
 8006e6a:	4645      	mov	r5, r8
 8006e6c:	1a80      	subs	r0, r0, r2
 8006e6e:	fa0b f000 	lsl.w	r0, fp, r0
 8006e72:	4318      	orrs	r0, r3
 8006e74:	9004      	str	r0, [sp, #16]
 8006e76:	e7bb      	b.n	8006df0 <_vfiprintf_r+0x88>
 8006e78:	9a03      	ldr	r2, [sp, #12]
 8006e7a:	1d11      	adds	r1, r2, #4
 8006e7c:	6812      	ldr	r2, [r2, #0]
 8006e7e:	9103      	str	r1, [sp, #12]
 8006e80:	2a00      	cmp	r2, #0
 8006e82:	db01      	blt.n	8006e88 <_vfiprintf_r+0x120>
 8006e84:	9207      	str	r2, [sp, #28]
 8006e86:	e004      	b.n	8006e92 <_vfiprintf_r+0x12a>
 8006e88:	4252      	negs	r2, r2
 8006e8a:	f043 0302 	orr.w	r3, r3, #2
 8006e8e:	9207      	str	r2, [sp, #28]
 8006e90:	9304      	str	r3, [sp, #16]
 8006e92:	f898 3000 	ldrb.w	r3, [r8]
 8006e96:	2b2e      	cmp	r3, #46	; 0x2e
 8006e98:	d110      	bne.n	8006ebc <_vfiprintf_r+0x154>
 8006e9a:	f898 3001 	ldrb.w	r3, [r8, #1]
 8006e9e:	f108 0101 	add.w	r1, r8, #1
 8006ea2:	2b2a      	cmp	r3, #42	; 0x2a
 8006ea4:	d137      	bne.n	8006f16 <_vfiprintf_r+0x1ae>
 8006ea6:	9b03      	ldr	r3, [sp, #12]
 8006ea8:	f108 0802 	add.w	r8, r8, #2
 8006eac:	1d1a      	adds	r2, r3, #4
 8006eae:	681b      	ldr	r3, [r3, #0]
 8006eb0:	9203      	str	r2, [sp, #12]
 8006eb2:	2b00      	cmp	r3, #0
 8006eb4:	bfb8      	it	lt
 8006eb6:	f04f 33ff 	movlt.w	r3, #4294967295
 8006eba:	9305      	str	r3, [sp, #20]
 8006ebc:	4d31      	ldr	r5, [pc, #196]	; (8006f84 <_vfiprintf_r+0x21c>)
 8006ebe:	2203      	movs	r2, #3
 8006ec0:	f898 1000 	ldrb.w	r1, [r8]
 8006ec4:	4628      	mov	r0, r5
 8006ec6:	f000 fadd 	bl	8007484 <memchr>
 8006eca:	b140      	cbz	r0, 8006ede <_vfiprintf_r+0x176>
 8006ecc:	2340      	movs	r3, #64	; 0x40
 8006ece:	1b40      	subs	r0, r0, r5
 8006ed0:	fa03 f000 	lsl.w	r0, r3, r0
 8006ed4:	9b04      	ldr	r3, [sp, #16]
 8006ed6:	f108 0801 	add.w	r8, r8, #1
 8006eda:	4303      	orrs	r3, r0
 8006edc:	9304      	str	r3, [sp, #16]
 8006ede:	f898 1000 	ldrb.w	r1, [r8]
 8006ee2:	2206      	movs	r2, #6
 8006ee4:	4828      	ldr	r0, [pc, #160]	; (8006f88 <_vfiprintf_r+0x220>)
 8006ee6:	f108 0701 	add.w	r7, r8, #1
 8006eea:	f88d 1028 	strb.w	r1, [sp, #40]	; 0x28
 8006eee:	f000 fac9 	bl	8007484 <memchr>
 8006ef2:	2800      	cmp	r0, #0
 8006ef4:	d034      	beq.n	8006f60 <_vfiprintf_r+0x1f8>
 8006ef6:	4b25      	ldr	r3, [pc, #148]	; (8006f8c <_vfiprintf_r+0x224>)
 8006ef8:	bb03      	cbnz	r3, 8006f3c <_vfiprintf_r+0x1d4>
 8006efa:	9b03      	ldr	r3, [sp, #12]
 8006efc:	3307      	adds	r3, #7
 8006efe:	f023 0307 	bic.w	r3, r3, #7
 8006f02:	3308      	adds	r3, #8
 8006f04:	9303      	str	r3, [sp, #12]
 8006f06:	9b09      	ldr	r3, [sp, #36]	; 0x24
 8006f08:	444b      	add	r3, r9
 8006f0a:	9309      	str	r3, [sp, #36]	; 0x24
 8006f0c:	e74c      	b.n	8006da8 <_vfiprintf_r+0x40>
 8006f0e:	fb00 3202 	mla	r2, r0, r2, r3
 8006f12:	2101      	movs	r1, #1
 8006f14:	e786      	b.n	8006e24 <_vfiprintf_r+0xbc>
 8006f16:	2300      	movs	r3, #0
 8006f18:	250a      	movs	r5, #10
 8006f1a:	4618      	mov	r0, r3
 8006f1c:	9305      	str	r3, [sp, #20]
 8006f1e:	4688      	mov	r8, r1
 8006f20:	f898 2000 	ldrb.w	r2, [r8]
 8006f24:	3101      	adds	r1, #1
 8006f26:	3a30      	subs	r2, #48	; 0x30
 8006f28:	2a09      	cmp	r2, #9
 8006f2a:	d903      	bls.n	8006f34 <_vfiprintf_r+0x1cc>
 8006f2c:	2b00      	cmp	r3, #0
 8006f2e:	d0c5      	beq.n	8006ebc <_vfiprintf_r+0x154>
 8006f30:	9005      	str	r0, [sp, #20]
 8006f32:	e7c3      	b.n	8006ebc <_vfiprintf_r+0x154>
 8006f34:	fb05 2000 	mla	r0, r5, r0, r2
 8006f38:	2301      	movs	r3, #1
 8006f3a:	e7f0      	b.n	8006f1e <_vfiprintf_r+0x1b6>
 8006f3c:	ab03      	add	r3, sp, #12
 8006f3e:	9300      	str	r3, [sp, #0]
 8006f40:	4622      	mov	r2, r4
 8006f42:	4b13      	ldr	r3, [pc, #76]	; (8006f90 <_vfiprintf_r+0x228>)
 8006f44:	a904      	add	r1, sp, #16
 8006f46:	4630      	mov	r0, r6
 8006f48:	f3af 8000 	nop.w
 8006f4c:	f1b0 3fff 	cmp.w	r0, #4294967295
 8006f50:	4681      	mov	r9, r0
 8006f52:	d1d8      	bne.n	8006f06 <_vfiprintf_r+0x19e>
 8006f54:	89a3      	ldrh	r3, [r4, #12]
 8006f56:	065b      	lsls	r3, r3, #25
 8006f58:	f53f af7d 	bmi.w	8006e56 <_vfiprintf_r+0xee>
 8006f5c:	9809      	ldr	r0, [sp, #36]	; 0x24
 8006f5e:	e77c      	b.n	8006e5a <_vfiprintf_r+0xf2>
 8006f60:	ab03      	add	r3, sp, #12
 8006f62:	9300      	str	r3, [sp, #0]
 8006f64:	4622      	mov	r2, r4
 8006f66:	4b0a      	ldr	r3, [pc, #40]	; (8006f90 <_vfiprintf_r+0x228>)
 8006f68:	a904      	add	r1, sp, #16
 8006f6a:	4630      	mov	r0, r6
 8006f6c:	f000 f88a 	bl	8007084 <_printf_i>
 8006f70:	e7ec      	b.n	8006f4c <_vfiprintf_r+0x1e4>
 8006f72:	bf00      	nop
 8006f74:	08007570 	.word	0x08007570
 8006f78:	080075b0 	.word	0x080075b0
 8006f7c:	08007590 	.word	0x08007590
 8006f80:	08007550 	.word	0x08007550
 8006f84:	080075b6 	.word	0x080075b6
 8006f88:	080075ba 	.word	0x080075ba
 8006f8c:	00000000 	.word	0x00000000
 8006f90:	08006d45 	.word	0x08006d45

08006f94 <_printf_common>:
 8006f94:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
 8006f98:	4691      	mov	r9, r2
 8006f9a:	461f      	mov	r7, r3
 8006f9c:	688a      	ldr	r2, [r1, #8]
 8006f9e:	690b      	ldr	r3, [r1, #16]
 8006fa0:	4606      	mov	r6, r0
 8006fa2:	4293      	cmp	r3, r2
 8006fa4:	bfb8      	it	lt
 8006fa6:	4613      	movlt	r3, r2
 8006fa8:	f8c9 3000 	str.w	r3, [r9]
 8006fac:	f891 2043 	ldrb.w	r2, [r1, #67]	; 0x43
 8006fb0:	460c      	mov	r4, r1
 8006fb2:	f8dd 8020 	ldr.w	r8, [sp, #32]
 8006fb6:	b112      	cbz	r2, 8006fbe <_printf_common+0x2a>
 8006fb8:	3301      	adds	r3, #1
 8006fba:	f8c9 3000 	str.w	r3, [r9]
 8006fbe:	6823      	ldr	r3, [r4, #0]
 8006fc0:	0699      	lsls	r1, r3, #26
 8006fc2:	bf42      	ittt	mi
 8006fc4:	f8d9 3000 	ldrmi.w	r3, [r9]
 8006fc8:	3302      	addmi	r3, #2
 8006fca:	f8c9 3000 	strmi.w	r3, [r9]
 8006fce:	6825      	ldr	r5, [r4, #0]
 8006fd0:	f015 0506 	ands.w	r5, r5, #6
 8006fd4:	d107      	bne.n	8006fe6 <_printf_common+0x52>
 8006fd6:	f104 0a19 	add.w	sl, r4, #25
 8006fda:	68e3      	ldr	r3, [r4, #12]
 8006fdc:	f8d9 2000 	ldr.w	r2, [r9]
 8006fe0:	1a9b      	subs	r3, r3, r2
 8006fe2:	429d      	cmp	r5, r3
 8006fe4:	db2a      	blt.n	800703c <_printf_common+0xa8>
 8006fe6:	f894 3043 	ldrb.w	r3, [r4, #67]	; 0x43
 8006fea:	6822      	ldr	r2, [r4, #0]
 8006fec:	3300      	adds	r3, #0
 8006fee:	bf18      	it	ne
 8006ff0:	2301      	movne	r3, #1
 8006ff2:	0692      	lsls	r2, r2, #26
 8006ff4:	d42f      	bmi.n	8007056 <_printf_common+0xc2>
 8006ff6:	f104 0243 	add.w	r2, r4, #67	; 0x43
 8006ffa:	4639      	mov	r1, r7
 8006ffc:	4630      	mov	r0, r6
 8006ffe:	47c0      	blx	r8
 8007000:	3001      	adds	r0, #1
 8007002:	d022      	beq.n	800704a <_printf_common+0xb6>
 8007004:	6823      	ldr	r3, [r4, #0]
 8007006:	68e5      	ldr	r5, [r4, #12]
 8007008:	f003 0306 	and.w	r3, r3, #6
 800700c:	2b04      	cmp	r3, #4
 800700e:	bf18      	it	ne
 8007010:	2500      	movne	r5, #0
 8007012:	f8d9 2000 	ldr.w	r2, [r9]
 8007016:	f04f 0900 	mov.w	r9, #0
 800701a:	bf08      	it	eq
 800701c:	1aad      	subeq	r5, r5, r2
 800701e:	68a3      	ldr	r3, [r4, #8]
 8007020:	6922      	ldr	r2, [r4, #16]
 8007022:	bf08      	it	eq
 8007024:	ea25 75e5 	biceq.w	r5, r5, r5, asr #31
 8007028:	4293      	cmp	r3, r2
 800702a:	bfc4      	itt	gt
 800702c:	1a9b      	subgt	r3, r3, r2
 800702e:	18ed      	addgt	r5, r5, r3
 8007030:	341a      	adds	r4, #26
 8007032:	454d      	cmp	r5, r9
 8007034:	d11b      	bne.n	800706e <_printf_common+0xda>
 8007036:	2000      	movs	r0, #0
 8007038:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 800703c:	2301      	movs	r3, #1
 800703e:	4652      	mov	r2, sl
 8007040:	4639      	mov	r1, r7
 8007042:	4630      	mov	r0, r6
 8007044:	47c0      	blx	r8
 8007046:	3001      	adds	r0, #1
 8007048:	d103      	bne.n	8007052 <_printf_common+0xbe>
 800704a:	f04f 30ff 	mov.w	r0, #4294967295
 800704e:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 8007052:	3501      	adds	r5, #1
 8007054:	e7c1      	b.n	8006fda <_printf_common+0x46>
 8007056:	2030      	movs	r0, #48	; 0x30
 8007058:	18e1      	adds	r1, r4, r3
 800705a:	f881 0043 	strb.w	r0, [r1, #67]	; 0x43
 800705e:	1c5a      	adds	r2, r3, #1
 8007060:	f894 1045 	ldrb.w	r1, [r4, #69]	; 0x45
 8007064:	4422      	add	r2, r4
 8007066:	3302      	adds	r3, #2
 8007068:	f882 1043 	strb.w	r1, [r2, #67]	; 0x43
 800706c:	e7c3      	b.n	8006ff6 <_printf_common+0x62>
 800706e:	2301      	movs	r3, #1
 8007070:	4622      	mov	r2, r4
 8007072:	4639      	mov	r1, r7
 8007074:	4630      	mov	r0, r6
 8007076:	47c0      	blx	r8
 8007078:	3001      	adds	r0, #1
 800707a:	d0e6      	beq.n	800704a <_printf_common+0xb6>
 800707c:	f109 0901 	add.w	r9, r9, #1
 8007080:	e7d7      	b.n	8007032 <_printf_common+0x9e>
	...

08007084 <_printf_i>:
 8007084:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr}
 8007088:	4617      	mov	r7, r2
 800708a:	7e0a      	ldrb	r2, [r1, #24]
 800708c:	b085      	sub	sp, #20
 800708e:	2a6e      	cmp	r2, #110	; 0x6e
 8007090:	4698      	mov	r8, r3
 8007092:	4606      	mov	r6, r0
 8007094:	460c      	mov	r4, r1
 8007096:	9b0c      	ldr	r3, [sp, #48]	; 0x30
 8007098:	f101 0e43 	add.w	lr, r1, #67	; 0x43
 800709c:	f000 80bc 	beq.w	8007218 <_printf_i+0x194>
 80070a0:	d81a      	bhi.n	80070d8 <_printf_i+0x54>
 80070a2:	2a63      	cmp	r2, #99	; 0x63
 80070a4:	d02e      	beq.n	8007104 <_printf_i+0x80>
 80070a6:	d80a      	bhi.n	80070be <_printf_i+0x3a>
 80070a8:	2a00      	cmp	r2, #0
 80070aa:	f000 80c8 	beq.w	800723e <_printf_i+0x1ba>
 80070ae:	2a58      	cmp	r2, #88	; 0x58
 80070b0:	f000 808a 	beq.w	80071c8 <_printf_i+0x144>
 80070b4:	f104 0542 	add.w	r5, r4, #66	; 0x42
 80070b8:	f884 2042 	strb.w	r2, [r4, #66]	; 0x42
 80070bc:	e02a      	b.n	8007114 <_printf_i+0x90>
 80070be:	2a64      	cmp	r2, #100	; 0x64
 80070c0:	d001      	beq.n	80070c6 <_printf_i+0x42>
 80070c2:	2a69      	cmp	r2, #105	; 0x69
 80070c4:	d1f6      	bne.n	80070b4 <_printf_i+0x30>
 80070c6:	6821      	ldr	r1, [r4, #0]
 80070c8:	681a      	ldr	r2, [r3, #0]
 80070ca:	f011 0f80 	tst.w	r1, #128	; 0x80
 80070ce:	d023      	beq.n	8007118 <_printf_i+0x94>
 80070d0:	1d11      	adds	r1, r2, #4
 80070d2:	6019      	str	r1, [r3, #0]
 80070d4:	6813      	ldr	r3, [r2, #0]
 80070d6:	e027      	b.n	8007128 <_printf_i+0xa4>
 80070d8:	2a73      	cmp	r2, #115	; 0x73
 80070da:	f000 80b4 	beq.w	8007246 <_printf_i+0x1c2>
 80070de:	d808      	bhi.n	80070f2 <_printf_i+0x6e>
 80070e0:	2a6f      	cmp	r2, #111	; 0x6f
 80070e2:	d02a      	beq.n	800713a <_printf_i+0xb6>
 80070e4:	2a70      	cmp	r2, #112	; 0x70
 80070e6:	d1e5      	bne.n	80070b4 <_printf_i+0x30>
 80070e8:	680a      	ldr	r2, [r1, #0]
 80070ea:	f042 0220 	orr.w	r2, r2, #32
 80070ee:	600a      	str	r2, [r1, #0]
 80070f0:	e003      	b.n	80070fa <_printf_i+0x76>
 80070f2:	2a75      	cmp	r2, #117	; 0x75
 80070f4:	d021      	beq.n	800713a <_printf_i+0xb6>
 80070f6:	2a78      	cmp	r2, #120	; 0x78
 80070f8:	d1dc      	bne.n	80070b4 <_printf_i+0x30>
 80070fa:	2278      	movs	r2, #120	; 0x78
 80070fc:	496f      	ldr	r1, [pc, #444]	; (80072bc <_printf_i+0x238>)
 80070fe:	f884 2045 	strb.w	r2, [r4, #69]	; 0x45
 8007102:	e064      	b.n	80071ce <_printf_i+0x14a>
 8007104:	681a      	ldr	r2, [r3, #0]
 8007106:	f101 0542 	add.w	r5, r1, #66	; 0x42
 800710a:	1d11      	adds	r1, r2, #4
 800710c:	6019      	str	r1, [r3, #0]
 800710e:	6813      	ldr	r3, [r2, #0]
 8007110:	f884 3042 	strb.w	r3, [r4, #66]	; 0x42
 8007114:	2301      	movs	r3, #1
 8007116:	e0a3      	b.n	8007260 <_printf_i+0x1dc>
 8007118:	f011 0f40 	tst.w	r1, #64	; 0x40
 800711c:	f102 0104 	add.w	r1, r2, #4
 8007120:	6019      	str	r1, [r3, #0]
 8007122:	d0d7      	beq.n	80070d4 <_printf_i+0x50>
 8007124:	f9b2 3000 	ldrsh.w	r3, [r2]
 8007128:	2b00      	cmp	r3, #0
 800712a:	da03      	bge.n	8007134 <_printf_i+0xb0>
 800712c:	222d      	movs	r2, #45	; 0x2d
 800712e:	425b      	negs	r3, r3
 8007130:	f884 2043 	strb.w	r2, [r4, #67]	; 0x43
 8007134:	4962      	ldr	r1, [pc, #392]	; (80072c0 <_printf_i+0x23c>)
 8007136:	220a      	movs	r2, #10
 8007138:	e017      	b.n	800716a <_printf_i+0xe6>
 800713a:	6820      	ldr	r0, [r4, #0]
 800713c:	6819      	ldr	r1, [r3, #0]
 800713e:	f010 0f80 	tst.w	r0, #128	; 0x80
 8007142:	d003      	beq.n	800714c <_printf_i+0xc8>
 8007144:	1d08      	adds	r0, r1, #4
 8007146:	6018      	str	r0, [r3, #0]
 8007148:	680b      	ldr	r3, [r1, #0]
 800714a:	e006      	b.n	800715a <_printf_i+0xd6>
 800714c:	f010 0f40 	tst.w	r0, #64	; 0x40
 8007150:	f101 0004 	add.w	r0, r1, #4
 8007154:	6018      	str	r0, [r3, #0]
 8007156:	d0f7      	beq.n	8007148 <_printf_i+0xc4>
 8007158:	880b      	ldrh	r3, [r1, #0]
 800715a:	2a6f      	cmp	r2, #111	; 0x6f
 800715c:	bf14      	ite	ne
 800715e:	220a      	movne	r2, #10
 8007160:	2208      	moveq	r2, #8
 8007162:	4957      	ldr	r1, [pc, #348]	; (80072c0 <_printf_i+0x23c>)
 8007164:	2000      	movs	r0, #0
 8007166:	f884 0043 	strb.w	r0, [r4, #67]	; 0x43
 800716a:	6865      	ldr	r5, [r4, #4]
 800716c:	2d00      	cmp	r5, #0
 800716e:	60a5      	str	r5, [r4, #8]
 8007170:	f2c0 809c 	blt.w	80072ac <_printf_i+0x228>
 8007174:	6820      	ldr	r0, [r4, #0]
 8007176:	f020 0004 	bic.w	r0, r0, #4
 800717a:	6020      	str	r0, [r4, #0]
 800717c:	2b00      	cmp	r3, #0
 800717e:	d13f      	bne.n	8007200 <_printf_i+0x17c>
 8007180:	2d00      	cmp	r5, #0
 8007182:	f040 8095 	bne.w	80072b0 <_printf_i+0x22c>
 8007186:	4675      	mov	r5, lr
 8007188:	2a08      	cmp	r2, #8
 800718a:	d10b      	bne.n	80071a4 <_printf_i+0x120>
 800718c:	6823      	ldr	r3, [r4, #0]
 800718e:	07da      	lsls	r2, r3, #31
 8007190:	d508      	bpl.n	80071a4 <_printf_i+0x120>
 8007192:	6923      	ldr	r3, [r4, #16]
 8007194:	6862      	ldr	r2, [r4, #4]
 8007196:	429a      	cmp	r2, r3
 8007198:	bfde      	ittt	le
 800719a:	2330      	movle	r3, #48	; 0x30
 800719c:	f805 3c01 	strble.w	r3, [r5, #-1]
 80071a0:	f105 35ff 	addle.w	r5, r5, #4294967295
 80071a4:	ebae 0305 	sub.w	r3, lr, r5
 80071a8:	6123      	str	r3, [r4, #16]
 80071aa:	f8cd 8000 	str.w	r8, [sp]
 80071ae:	463b      	mov	r3, r7
 80071b0:	aa03      	add	r2, sp, #12
 80071b2:	4621      	mov	r1, r4
 80071b4:	4630      	mov	r0, r6
 80071b6:	f7ff feed 	bl	8006f94 <_printf_common>
 80071ba:	3001      	adds	r0, #1
 80071bc:	d155      	bne.n	800726a <_printf_i+0x1e6>
 80071be:	f04f 30ff 	mov.w	r0, #4294967295
 80071c2:	b005      	add	sp, #20
 80071c4:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
 80071c8:	f881 2045 	strb.w	r2, [r1, #69]	; 0x45
 80071cc:	493c      	ldr	r1, [pc, #240]	; (80072c0 <_printf_i+0x23c>)
 80071ce:	6822      	ldr	r2, [r4, #0]
 80071d0:	6818      	ldr	r0, [r3, #0]
 80071d2:	f012 0f80 	tst.w	r2, #128	; 0x80
 80071d6:	f100 0504 	add.w	r5, r0, #4
 80071da:	601d      	str	r5, [r3, #0]
 80071dc:	d001      	beq.n	80071e2 <_printf_i+0x15e>
 80071de:	6803      	ldr	r3, [r0, #0]
 80071e0:	e002      	b.n	80071e8 <_printf_i+0x164>
 80071e2:	0655      	lsls	r5, r2, #25
 80071e4:	d5fb      	bpl.n	80071de <_printf_i+0x15a>
 80071e6:	8803      	ldrh	r3, [r0, #0]
 80071e8:	07d0      	lsls	r0, r2, #31
 80071ea:	bf44      	itt	mi
 80071ec:	f042 0220 	orrmi.w	r2, r2, #32
 80071f0:	6022      	strmi	r2, [r4, #0]
 80071f2:	b91b      	cbnz	r3, 80071fc <_printf_i+0x178>
 80071f4:	6822      	ldr	r2, [r4, #0]
 80071f6:	f022 0220 	bic.w	r2, r2, #32
 80071fa:	6022      	str	r2, [r4, #0]
 80071fc:	2210      	movs	r2, #16
 80071fe:	e7b1      	b.n	8007164 <_printf_i+0xe0>
 8007200:	4675      	mov	r5, lr
 8007202:	fbb3 f0f2 	udiv	r0, r3, r2
 8007206:	fb02 3310 	mls	r3, r2, r0, r3
 800720a:	5ccb      	ldrb	r3, [r1, r3]
 800720c:	f805 3d01 	strb.w	r3, [r5, #-1]!
 8007210:	4603      	mov	r3, r0
 8007212:	2800      	cmp	r0, #0
 8007214:	d1f5      	bne.n	8007202 <_printf_i+0x17e>
 8007216:	e7b7      	b.n	8007188 <_printf_i+0x104>
 8007218:	6808      	ldr	r0, [r1, #0]
 800721a:	681a      	ldr	r2, [r3, #0]
 800721c:	f010 0f80 	tst.w	r0, #128	; 0x80
 8007220:	6949      	ldr	r1, [r1, #20]
 8007222:	d004      	beq.n	800722e <_printf_i+0x1aa>
 8007224:	1d10      	adds	r0, r2, #4
 8007226:	6018      	str	r0, [r3, #0]
 8007228:	6813      	ldr	r3, [r2, #0]
 800722a:	6019      	str	r1, [r3, #0]
 800722c:	e007      	b.n	800723e <_printf_i+0x1ba>
 800722e:	f010 0f40 	tst.w	r0, #64	; 0x40
 8007232:	f102 0004 	add.w	r0, r2, #4
 8007236:	6018      	str	r0, [r3, #0]
 8007238:	6813      	ldr	r3, [r2, #0]
 800723a:	d0f6      	beq.n	800722a <_printf_i+0x1a6>
 800723c:	8019      	strh	r1, [r3, #0]
 800723e:	2300      	movs	r3, #0
 8007240:	4675      	mov	r5, lr
 8007242:	6123      	str	r3, [r4, #16]
 8007244:	e7b1      	b.n	80071aa <_printf_i+0x126>
 8007246:	681a      	ldr	r2, [r3, #0]
 8007248:	1d11      	adds	r1, r2, #4
 800724a:	6019      	str	r1, [r3, #0]
 800724c:	6815      	ldr	r5, [r2, #0]
 800724e:	2100      	movs	r1, #0
 8007250:	6862      	ldr	r2, [r4, #4]
 8007252:	4628      	mov	r0, r5
 8007254:	f000 f916 	bl	8007484 <memchr>
 8007258:	b108      	cbz	r0, 800725e <_printf_i+0x1da>
 800725a:	1b40      	subs	r0, r0, r5
 800725c:	6060      	str	r0, [r4, #4]
 800725e:	6863      	ldr	r3, [r4, #4]
 8007260:	6123      	str	r3, [r4, #16]
 8007262:	2300      	movs	r3, #0
 8007264:	f884 3043 	strb.w	r3, [r4, #67]	; 0x43
 8007268:	e79f      	b.n	80071aa <_printf_i+0x126>
 800726a:	6923      	ldr	r3, [r4, #16]
 800726c:	462a      	mov	r2, r5
 800726e:	4639      	mov	r1, r7
 8007270:	4630      	mov	r0, r6
 8007272:	47c0      	blx	r8
 8007274:	3001      	adds	r0, #1
 8007276:	d0a2      	beq.n	80071be <_printf_i+0x13a>
 8007278:	6823      	ldr	r3, [r4, #0]
 800727a:	079b      	lsls	r3, r3, #30
 800727c:	d507      	bpl.n	800728e <_printf_i+0x20a>
 800727e:	2500      	movs	r5, #0
 8007280:	f104 0919 	add.w	r9, r4, #25
 8007284:	68e3      	ldr	r3, [r4, #12]
 8007286:	9a03      	ldr	r2, [sp, #12]
 8007288:	1a9b      	subs	r3, r3, r2
 800728a:	429d      	cmp	r5, r3
 800728c:	db05      	blt.n	800729a <_printf_i+0x216>
 800728e:	68e0      	ldr	r0, [r4, #12]
 8007290:	9b03      	ldr	r3, [sp, #12]
 8007292:	4298      	cmp	r0, r3
 8007294:	bfb8      	it	lt
 8007296:	4618      	movlt	r0, r3
 8007298:	e793      	b.n	80071c2 <_printf_i+0x13e>
 800729a:	2301      	movs	r3, #1
 800729c:	464a      	mov	r2, r9
 800729e:	4639      	mov	r1, r7
 80072a0:	4630      	mov	r0, r6
 80072a2:	47c0      	blx	r8
 80072a4:	3001      	adds	r0, #1
 80072a6:	d08a      	beq.n	80071be <_printf_i+0x13a>
 80072a8:	3501      	adds	r5, #1
 80072aa:	e7eb      	b.n	8007284 <_printf_i+0x200>
 80072ac:	2b00      	cmp	r3, #0
 80072ae:	d1a7      	bne.n	8007200 <_printf_i+0x17c>
 80072b0:	780b      	ldrb	r3, [r1, #0]
 80072b2:	f104 0542 	add.w	r5, r4, #66	; 0x42
 80072b6:	f884 3042 	strb.w	r3, [r4, #66]	; 0x42
 80072ba:	e765      	b.n	8007188 <_printf_i+0x104>
 80072bc:	080075d2 	.word	0x080075d2
 80072c0:	080075c1 	.word	0x080075c1

080072c4 <_putc_r>:
 80072c4:	b570      	push	{r4, r5, r6, lr}
 80072c6:	460d      	mov	r5, r1
 80072c8:	4614      	mov	r4, r2
 80072ca:	4606      	mov	r6, r0
 80072cc:	b118      	cbz	r0, 80072d6 <_putc_r+0x12>
 80072ce:	6983      	ldr	r3, [r0, #24]
 80072d0:	b90b      	cbnz	r3, 80072d6 <_putc_r+0x12>
 80072d2:	f7ff fb81 	bl	80069d8 <__sinit>
 80072d6:	4b13      	ldr	r3, [pc, #76]	; (8007324 <_putc_r+0x60>)
 80072d8:	429c      	cmp	r4, r3
 80072da:	d112      	bne.n	8007302 <_putc_r+0x3e>
 80072dc:	6874      	ldr	r4, [r6, #4]
 80072de:	68a3      	ldr	r3, [r4, #8]
 80072e0:	3b01      	subs	r3, #1
 80072e2:	2b00      	cmp	r3, #0
 80072e4:	60a3      	str	r3, [r4, #8]
 80072e6:	da16      	bge.n	8007316 <_putc_r+0x52>
 80072e8:	69a2      	ldr	r2, [r4, #24]
 80072ea:	4293      	cmp	r3, r2
 80072ec:	db02      	blt.n	80072f4 <_putc_r+0x30>
 80072ee:	b2eb      	uxtb	r3, r5
 80072f0:	2b0a      	cmp	r3, #10
 80072f2:	d110      	bne.n	8007316 <_putc_r+0x52>
 80072f4:	4622      	mov	r2, r4
 80072f6:	4629      	mov	r1, r5
 80072f8:	4630      	mov	r0, r6
 80072fa:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
 80072fe:	f7ff b9b9 	b.w	8006674 <__swbuf_r>
 8007302:	4b09      	ldr	r3, [pc, #36]	; (8007328 <_putc_r+0x64>)
 8007304:	429c      	cmp	r4, r3
 8007306:	d101      	bne.n	800730c <_putc_r+0x48>
 8007308:	68b4      	ldr	r4, [r6, #8]
 800730a:	e7e8      	b.n	80072de <_putc_r+0x1a>
 800730c:	4b07      	ldr	r3, [pc, #28]	; (800732c <_putc_r+0x68>)
 800730e:	429c      	cmp	r4, r3
 8007310:	bf08      	it	eq
 8007312:	68f4      	ldreq	r4, [r6, #12]
 8007314:	e7e3      	b.n	80072de <_putc_r+0x1a>
 8007316:	6823      	ldr	r3, [r4, #0]
 8007318:	b2e8      	uxtb	r0, r5
 800731a:	1c5a      	adds	r2, r3, #1
 800731c:	6022      	str	r2, [r4, #0]
 800731e:	701d      	strb	r5, [r3, #0]
 8007320:	bd70      	pop	{r4, r5, r6, pc}
 8007322:	bf00      	nop
 8007324:	08007570 	.word	0x08007570
 8007328:	08007590 	.word	0x08007590
 800732c:	08007550 	.word	0x08007550

08007330 <_sbrk_r>:
 8007330:	b538      	push	{r3, r4, r5, lr}
 8007332:	2300      	movs	r3, #0
 8007334:	4c05      	ldr	r4, [pc, #20]	; (800734c <_sbrk_r+0x1c>)
 8007336:	4605      	mov	r5, r0
 8007338:	4608      	mov	r0, r1
 800733a:	6023      	str	r3, [r4, #0]
 800733c:	f7fe feda 	bl	80060f4 <_sbrk>
 8007340:	1c43      	adds	r3, r0, #1
 8007342:	d102      	bne.n	800734a <_sbrk_r+0x1a>
 8007344:	6823      	ldr	r3, [r4, #0]
 8007346:	b103      	cbz	r3, 800734a <_sbrk_r+0x1a>
 8007348:	602b      	str	r3, [r5, #0]
 800734a:	bd38      	pop	{r3, r4, r5, pc}
 800734c:	20001e34 	.word	0x20001e34

08007350 <__sread>:
 8007350:	b510      	push	{r4, lr}
 8007352:	460c      	mov	r4, r1
 8007354:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 8007358:	f000 f8a4 	bl	80074a4 <_read_r>
 800735c:	2800      	cmp	r0, #0
 800735e:	bfab      	itete	ge
 8007360:	6d63      	ldrge	r3, [r4, #84]	; 0x54
 8007362:	89a3      	ldrhlt	r3, [r4, #12]
 8007364:	181b      	addge	r3, r3, r0
 8007366:	f423 5380 	biclt.w	r3, r3, #4096	; 0x1000
 800736a:	bfac      	ite	ge
 800736c:	6563      	strge	r3, [r4, #84]	; 0x54
 800736e:	81a3      	strhlt	r3, [r4, #12]
 8007370:	bd10      	pop	{r4, pc}

08007372 <__swrite>:
 8007372:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
 8007376:	461f      	mov	r7, r3
 8007378:	898b      	ldrh	r3, [r1, #12]
 800737a:	4605      	mov	r5, r0
 800737c:	05db      	lsls	r3, r3, #23
 800737e:	460c      	mov	r4, r1
 8007380:	4616      	mov	r6, r2
 8007382:	d505      	bpl.n	8007390 <__swrite+0x1e>
 8007384:	2302      	movs	r3, #2
 8007386:	2200      	movs	r2, #0
 8007388:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 800738c:	f000 f868 	bl	8007460 <_lseek_r>
 8007390:	89a3      	ldrh	r3, [r4, #12]
 8007392:	4632      	mov	r2, r6
 8007394:	f423 5380 	bic.w	r3, r3, #4096	; 0x1000
 8007398:	81a3      	strh	r3, [r4, #12]
 800739a:	f9b4 100e 	ldrsh.w	r1, [r4, #14]
 800739e:	463b      	mov	r3, r7
 80073a0:	4628      	mov	r0, r5
 80073a2:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
 80073a6:	f000 b817 	b.w	80073d8 <_write_r>

080073aa <__sseek>:
 80073aa:	b510      	push	{r4, lr}
 80073ac:	460c      	mov	r4, r1
 80073ae:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 80073b2:	f000 f855 	bl	8007460 <_lseek_r>
 80073b6:	1c43      	adds	r3, r0, #1
 80073b8:	89a3      	ldrh	r3, [r4, #12]
 80073ba:	bf15      	itete	ne
 80073bc:	6560      	strne	r0, [r4, #84]	; 0x54
 80073be:	f423 5380 	biceq.w	r3, r3, #4096	; 0x1000
 80073c2:	f443 5380 	orrne.w	r3, r3, #4096	; 0x1000
 80073c6:	81a3      	strheq	r3, [r4, #12]
 80073c8:	bf18      	it	ne
 80073ca:	81a3      	strhne	r3, [r4, #12]
 80073cc:	bd10      	pop	{r4, pc}

080073ce <__sclose>:
 80073ce:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 80073d2:	f000 b813 	b.w	80073fc <_close_r>
	...

080073d8 <_write_r>:
 80073d8:	b538      	push	{r3, r4, r5, lr}
 80073da:	4605      	mov	r5, r0
 80073dc:	4608      	mov	r0, r1
 80073de:	4611      	mov	r1, r2
 80073e0:	2200      	movs	r2, #0
 80073e2:	4c05      	ldr	r4, [pc, #20]	; (80073f8 <_write_r+0x20>)
 80073e4:	6022      	str	r2, [r4, #0]
 80073e6:	461a      	mov	r2, r3
 80073e8:	f7fe fb36 	bl	8005a58 <_write>
 80073ec:	1c43      	adds	r3, r0, #1
 80073ee:	d102      	bne.n	80073f6 <_write_r+0x1e>
 80073f0:	6823      	ldr	r3, [r4, #0]
 80073f2:	b103      	cbz	r3, 80073f6 <_write_r+0x1e>
 80073f4:	602b      	str	r3, [r5, #0]
 80073f6:	bd38      	pop	{r3, r4, r5, pc}
 80073f8:	20001e34 	.word	0x20001e34

080073fc <_close_r>:
 80073fc:	b538      	push	{r3, r4, r5, lr}
 80073fe:	2300      	movs	r3, #0
 8007400:	4c05      	ldr	r4, [pc, #20]	; (8007418 <_close_r+0x1c>)
 8007402:	4605      	mov	r5, r0
 8007404:	4608      	mov	r0, r1
 8007406:	6023      	str	r3, [r4, #0]
 8007408:	f7fe fe8e 	bl	8006128 <_close>
 800740c:	1c43      	adds	r3, r0, #1
 800740e:	d102      	bne.n	8007416 <_close_r+0x1a>
 8007410:	6823      	ldr	r3, [r4, #0]
 8007412:	b103      	cbz	r3, 8007416 <_close_r+0x1a>
 8007414:	602b      	str	r3, [r5, #0]
 8007416:	bd38      	pop	{r3, r4, r5, pc}
 8007418:	20001e34 	.word	0x20001e34

0800741c <_fstat_r>:
 800741c:	b538      	push	{r3, r4, r5, lr}
 800741e:	2300      	movs	r3, #0
 8007420:	4c06      	ldr	r4, [pc, #24]	; (800743c <_fstat_r+0x20>)
 8007422:	4605      	mov	r5, r0
 8007424:	4608      	mov	r0, r1
 8007426:	4611      	mov	r1, r2
 8007428:	6023      	str	r3, [r4, #0]
 800742a:	f7fe fe80 	bl	800612e <_fstat>
 800742e:	1c43      	adds	r3, r0, #1
 8007430:	d102      	bne.n	8007438 <_fstat_r+0x1c>
 8007432:	6823      	ldr	r3, [r4, #0]
 8007434:	b103      	cbz	r3, 8007438 <_fstat_r+0x1c>
 8007436:	602b      	str	r3, [r5, #0]
 8007438:	bd38      	pop	{r3, r4, r5, pc}
 800743a:	bf00      	nop
 800743c:	20001e34 	.word	0x20001e34

08007440 <_isatty_r>:
 8007440:	b538      	push	{r3, r4, r5, lr}
 8007442:	2300      	movs	r3, #0
 8007444:	4c05      	ldr	r4, [pc, #20]	; (800745c <_isatty_r+0x1c>)
 8007446:	4605      	mov	r5, r0
 8007448:	4608      	mov	r0, r1
 800744a:	6023      	str	r3, [r4, #0]
 800744c:	f7fe fe74 	bl	8006138 <_isatty>
 8007450:	1c43      	adds	r3, r0, #1
 8007452:	d102      	bne.n	800745a <_isatty_r+0x1a>
 8007454:	6823      	ldr	r3, [r4, #0]
 8007456:	b103      	cbz	r3, 800745a <_isatty_r+0x1a>
 8007458:	602b      	str	r3, [r5, #0]
 800745a:	bd38      	pop	{r3, r4, r5, pc}
 800745c:	20001e34 	.word	0x20001e34

08007460 <_lseek_r>:
 8007460:	b538      	push	{r3, r4, r5, lr}
 8007462:	4605      	mov	r5, r0
 8007464:	4608      	mov	r0, r1
 8007466:	4611      	mov	r1, r2
 8007468:	2200      	movs	r2, #0
 800746a:	4c05      	ldr	r4, [pc, #20]	; (8007480 <_lseek_r+0x20>)
 800746c:	6022      	str	r2, [r4, #0]
 800746e:	461a      	mov	r2, r3
 8007470:	f7fe fe64 	bl	800613c <_lseek>
 8007474:	1c43      	adds	r3, r0, #1
 8007476:	d102      	bne.n	800747e <_lseek_r+0x1e>
 8007478:	6823      	ldr	r3, [r4, #0]
 800747a:	b103      	cbz	r3, 800747e <_lseek_r+0x1e>
 800747c:	602b      	str	r3, [r5, #0]
 800747e:	bd38      	pop	{r3, r4, r5, pc}
 8007480:	20001e34 	.word	0x20001e34

08007484 <memchr>:
 8007484:	b510      	push	{r4, lr}
 8007486:	b2c9      	uxtb	r1, r1
 8007488:	4402      	add	r2, r0
 800748a:	4290      	cmp	r0, r2
 800748c:	4603      	mov	r3, r0
 800748e:	d101      	bne.n	8007494 <memchr+0x10>
 8007490:	2000      	movs	r0, #0
 8007492:	bd10      	pop	{r4, pc}
 8007494:	781c      	ldrb	r4, [r3, #0]
 8007496:	3001      	adds	r0, #1
 8007498:	428c      	cmp	r4, r1
 800749a:	d1f6      	bne.n	800748a <memchr+0x6>
 800749c:	4618      	mov	r0, r3
 800749e:	bd10      	pop	{r4, pc}

080074a0 <__malloc_lock>:
 80074a0:	4770      	bx	lr

080074a2 <__malloc_unlock>:
 80074a2:	4770      	bx	lr

080074a4 <_read_r>:
 80074a4:	b538      	push	{r3, r4, r5, lr}
 80074a6:	4605      	mov	r5, r0
 80074a8:	4608      	mov	r0, r1
 80074aa:	4611      	mov	r1, r2
 80074ac:	2200      	movs	r2, #0
 80074ae:	4c05      	ldr	r4, [pc, #20]	; (80074c4 <_read_r+0x20>)
 80074b0:	6022      	str	r2, [r4, #0]
 80074b2:	461a      	mov	r2, r3
 80074b4:	f7fe fe10 	bl	80060d8 <_read>
 80074b8:	1c43      	adds	r3, r0, #1
 80074ba:	d102      	bne.n	80074c2 <_read_r+0x1e>
 80074bc:	6823      	ldr	r3, [r4, #0]
 80074be:	b103      	cbz	r3, 80074c2 <_read_r+0x1e>
 80074c0:	602b      	str	r3, [r5, #0]
 80074c2:	bd38      	pop	{r3, r4, r5, pc}
 80074c4:	20001e34 	.word	0x20001e34

080074c8 <_init>:
 80074c8:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 80074ca:	bf00      	nop
 80074cc:	bcf8      	pop	{r3, r4, r5, r6, r7}
 80074ce:	bc08      	pop	{r3}
 80074d0:	469e      	mov	lr, r3
 80074d2:	4770      	bx	lr

080074d4 <_fini>:
 80074d4:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 80074d6:	bf00      	nop
 80074d8:	bcf8      	pop	{r3, r4, r5, r6, r7}
 80074da:	bc08      	pop	{r3}
 80074dc:	469e      	mov	lr, r3
 80074de:	4770      	bx	lr