STM32F103_ATTEN_PLL_Zig.list 668 KB

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  1. STM32F103_ATTEN_PLL_Zig.elf: file format elf32-littlearm
  2. Sections:
  3. Idx Name Size VMA LMA File off Algn
  4. 0 .isr_vector 000001e4 08004000 08004000 00004000 2**0
  5. CONTENTS, ALLOC, LOAD, READONLY, DATA
  6. 1 .text 00007a5c 080041e8 080041e8 000041e8 2**3
  7. CONTENTS, ALLOC, LOAD, READONLY, CODE
  8. 2 .rodata 00000390 0800bc48 0800bc48 0000bc48 2**3
  9. CONTENTS, ALLOC, LOAD, READONLY, DATA
  10. 3 .ARM 00000008 0800bfd8 0800bfd8 0000bfd8 2**2
  11. CONTENTS, ALLOC, LOAD, READONLY, DATA
  12. 4 .init_array 00000004 0800bfe0 0800bfe0 0000bfe0 2**2
  13. CONTENTS, ALLOC, LOAD, DATA
  14. 5 .fini_array 00000004 0800bfe4 0800bfe4 0000bfe4 2**2
  15. CONTENTS, ALLOC, LOAD, DATA
  16. 6 .data 00000404 20000000 0800bfe8 00010000 2**2
  17. CONTENTS, ALLOC, LOAD, DATA
  18. 7 .bss 000013a0 20000408 0800c3ec 00010408 2**3
  19. ALLOC
  20. 8 ._user_heap_stack 00000600 200017a8 0800c3ec 000117a8 2**0
  21. ALLOC
  22. 9 .ARM.attributes 00000029 00000000 00000000 00010404 2**0
  23. CONTENTS, READONLY
  24. 10 .debug_info 0002a859 00000000 00000000 0001042d 2**0
  25. CONTENTS, READONLY, DEBUGGING
  26. 11 .debug_abbrev 000051b2 00000000 00000000 0003ac86 2**0
  27. CONTENTS, READONLY, DEBUGGING
  28. 12 .debug_loc 00009d27 00000000 00000000 0003fe38 2**0
  29. CONTENTS, READONLY, DEBUGGING
  30. 13 .debug_aranges 00000e38 00000000 00000000 00049b60 2**3
  31. CONTENTS, READONLY, DEBUGGING
  32. 14 .debug_ranges 00001230 00000000 00000000 0004a998 2**3
  33. CONTENTS, READONLY, DEBUGGING
  34. 15 .debug_line 00009e6c 00000000 00000000 0004bbc8 2**0
  35. CONTENTS, READONLY, DEBUGGING
  36. 16 .debug_str 00005856 00000000 00000000 00055a34 2**0
  37. CONTENTS, READONLY, DEBUGGING
  38. 17 .comment 0000007c 00000000 00000000 0005b28a 2**0
  39. CONTENTS, READONLY
  40. 18 .debug_frame 00003870 00000000 00000000 0005b308 2**2
  41. CONTENTS, READONLY, DEBUGGING
  42. Disassembly of section .text:
  43. 080041e8 <__do_global_dtors_aux>:
  44. 80041e8: b510 push {r4, lr}
  45. 80041ea: 4c05 ldr r4, [pc, #20] ; (8004200 <__do_global_dtors_aux+0x18>)
  46. 80041ec: 7823 ldrb r3, [r4, #0]
  47. 80041ee: b933 cbnz r3, 80041fe <__do_global_dtors_aux+0x16>
  48. 80041f0: 4b04 ldr r3, [pc, #16] ; (8004204 <__do_global_dtors_aux+0x1c>)
  49. 80041f2: b113 cbz r3, 80041fa <__do_global_dtors_aux+0x12>
  50. 80041f4: 4804 ldr r0, [pc, #16] ; (8004208 <__do_global_dtors_aux+0x20>)
  51. 80041f6: f3af 8000 nop.w
  52. 80041fa: 2301 movs r3, #1
  53. 80041fc: 7023 strb r3, [r4, #0]
  54. 80041fe: bd10 pop {r4, pc}
  55. 8004200: 20000408 .word 0x20000408
  56. 8004204: 00000000 .word 0x00000000
  57. 8004208: 0800bc2c .word 0x0800bc2c
  58. 0800420c <frame_dummy>:
  59. 800420c: b508 push {r3, lr}
  60. 800420e: 4b03 ldr r3, [pc, #12] ; (800421c <frame_dummy+0x10>)
  61. 8004210: b11b cbz r3, 800421a <frame_dummy+0xe>
  62. 8004212: 4903 ldr r1, [pc, #12] ; (8004220 <frame_dummy+0x14>)
  63. 8004214: 4803 ldr r0, [pc, #12] ; (8004224 <frame_dummy+0x18>)
  64. 8004216: f3af 8000 nop.w
  65. 800421a: bd08 pop {r3, pc}
  66. 800421c: 00000000 .word 0x00000000
  67. 8004220: 2000040c .word 0x2000040c
  68. 8004224: 0800bc2c .word 0x0800bc2c
  69. 08004228 <strlen>:
  70. 8004228: 4603 mov r3, r0
  71. 800422a: f813 2b01 ldrb.w r2, [r3], #1
  72. 800422e: 2a00 cmp r2, #0
  73. 8004230: d1fb bne.n 800422a <strlen+0x2>
  74. 8004232: 1a18 subs r0, r3, r0
  75. 8004234: 3801 subs r0, #1
  76. 8004236: 4770 bx lr
  77. 08004238 <__aeabi_llsr>:
  78. 8004238: 40d0 lsrs r0, r2
  79. 800423a: 1c0b adds r3, r1, #0
  80. 800423c: 40d1 lsrs r1, r2
  81. 800423e: 469c mov ip, r3
  82. 8004240: 3a20 subs r2, #32
  83. 8004242: 40d3 lsrs r3, r2
  84. 8004244: 4318 orrs r0, r3
  85. 8004246: 4252 negs r2, r2
  86. 8004248: 4663 mov r3, ip
  87. 800424a: 4093 lsls r3, r2
  88. 800424c: 4318 orrs r0, r3
  89. 800424e: 4770 bx lr
  90. 08004250 <__aeabi_drsub>:
  91. 8004250: f081 4100 eor.w r1, r1, #2147483648 ; 0x80000000
  92. 8004254: e002 b.n 800425c <__adddf3>
  93. 8004256: bf00 nop
  94. 08004258 <__aeabi_dsub>:
  95. 8004258: f083 4300 eor.w r3, r3, #2147483648 ; 0x80000000
  96. 0800425c <__adddf3>:
  97. 800425c: b530 push {r4, r5, lr}
  98. 800425e: ea4f 0441 mov.w r4, r1, lsl #1
  99. 8004262: ea4f 0543 mov.w r5, r3, lsl #1
  100. 8004266: ea94 0f05 teq r4, r5
  101. 800426a: bf08 it eq
  102. 800426c: ea90 0f02 teqeq r0, r2
  103. 8004270: bf1f itttt ne
  104. 8004272: ea54 0c00 orrsne.w ip, r4, r0
  105. 8004276: ea55 0c02 orrsne.w ip, r5, r2
  106. 800427a: ea7f 5c64 mvnsne.w ip, r4, asr #21
  107. 800427e: ea7f 5c65 mvnsne.w ip, r5, asr #21
  108. 8004282: f000 80e2 beq.w 800444a <__adddf3+0x1ee>
  109. 8004286: ea4f 5454 mov.w r4, r4, lsr #21
  110. 800428a: ebd4 5555 rsbs r5, r4, r5, lsr #21
  111. 800428e: bfb8 it lt
  112. 8004290: 426d neglt r5, r5
  113. 8004292: dd0c ble.n 80042ae <__adddf3+0x52>
  114. 8004294: 442c add r4, r5
  115. 8004296: ea80 0202 eor.w r2, r0, r2
  116. 800429a: ea81 0303 eor.w r3, r1, r3
  117. 800429e: ea82 0000 eor.w r0, r2, r0
  118. 80042a2: ea83 0101 eor.w r1, r3, r1
  119. 80042a6: ea80 0202 eor.w r2, r0, r2
  120. 80042aa: ea81 0303 eor.w r3, r1, r3
  121. 80042ae: 2d36 cmp r5, #54 ; 0x36
  122. 80042b0: bf88 it hi
  123. 80042b2: bd30 pophi {r4, r5, pc}
  124. 80042b4: f011 4f00 tst.w r1, #2147483648 ; 0x80000000
  125. 80042b8: ea4f 3101 mov.w r1, r1, lsl #12
  126. 80042bc: f44f 1c80 mov.w ip, #1048576 ; 0x100000
  127. 80042c0: ea4c 3111 orr.w r1, ip, r1, lsr #12
  128. 80042c4: d002 beq.n 80042cc <__adddf3+0x70>
  129. 80042c6: 4240 negs r0, r0
  130. 80042c8: eb61 0141 sbc.w r1, r1, r1, lsl #1
  131. 80042cc: f013 4f00 tst.w r3, #2147483648 ; 0x80000000
  132. 80042d0: ea4f 3303 mov.w r3, r3, lsl #12
  133. 80042d4: ea4c 3313 orr.w r3, ip, r3, lsr #12
  134. 80042d8: d002 beq.n 80042e0 <__adddf3+0x84>
  135. 80042da: 4252 negs r2, r2
  136. 80042dc: eb63 0343 sbc.w r3, r3, r3, lsl #1
  137. 80042e0: ea94 0f05 teq r4, r5
  138. 80042e4: f000 80a7 beq.w 8004436 <__adddf3+0x1da>
  139. 80042e8: f1a4 0401 sub.w r4, r4, #1
  140. 80042ec: f1d5 0e20 rsbs lr, r5, #32
  141. 80042f0: db0d blt.n 800430e <__adddf3+0xb2>
  142. 80042f2: fa02 fc0e lsl.w ip, r2, lr
  143. 80042f6: fa22 f205 lsr.w r2, r2, r5
  144. 80042fa: 1880 adds r0, r0, r2
  145. 80042fc: f141 0100 adc.w r1, r1, #0
  146. 8004300: fa03 f20e lsl.w r2, r3, lr
  147. 8004304: 1880 adds r0, r0, r2
  148. 8004306: fa43 f305 asr.w r3, r3, r5
  149. 800430a: 4159 adcs r1, r3
  150. 800430c: e00e b.n 800432c <__adddf3+0xd0>
  151. 800430e: f1a5 0520 sub.w r5, r5, #32
  152. 8004312: f10e 0e20 add.w lr, lr, #32
  153. 8004316: 2a01 cmp r2, #1
  154. 8004318: fa03 fc0e lsl.w ip, r3, lr
  155. 800431c: bf28 it cs
  156. 800431e: f04c 0c02 orrcs.w ip, ip, #2
  157. 8004322: fa43 f305 asr.w r3, r3, r5
  158. 8004326: 18c0 adds r0, r0, r3
  159. 8004328: eb51 71e3 adcs.w r1, r1, r3, asr #31
  160. 800432c: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000
  161. 8004330: d507 bpl.n 8004342 <__adddf3+0xe6>
  162. 8004332: f04f 0e00 mov.w lr, #0
  163. 8004336: f1dc 0c00 rsbs ip, ip, #0
  164. 800433a: eb7e 0000 sbcs.w r0, lr, r0
  165. 800433e: eb6e 0101 sbc.w r1, lr, r1
  166. 8004342: f5b1 1f80 cmp.w r1, #1048576 ; 0x100000
  167. 8004346: d31b bcc.n 8004380 <__adddf3+0x124>
  168. 8004348: f5b1 1f00 cmp.w r1, #2097152 ; 0x200000
  169. 800434c: d30c bcc.n 8004368 <__adddf3+0x10c>
  170. 800434e: 0849 lsrs r1, r1, #1
  171. 8004350: ea5f 0030 movs.w r0, r0, rrx
  172. 8004354: ea4f 0c3c mov.w ip, ip, rrx
  173. 8004358: f104 0401 add.w r4, r4, #1
  174. 800435c: ea4f 5244 mov.w r2, r4, lsl #21
  175. 8004360: f512 0f80 cmn.w r2, #4194304 ; 0x400000
  176. 8004364: f080 809a bcs.w 800449c <__adddf3+0x240>
  177. 8004368: f1bc 4f00 cmp.w ip, #2147483648 ; 0x80000000
  178. 800436c: bf08 it eq
  179. 800436e: ea5f 0c50 movseq.w ip, r0, lsr #1
  180. 8004372: f150 0000 adcs.w r0, r0, #0
  181. 8004376: eb41 5104 adc.w r1, r1, r4, lsl #20
  182. 800437a: ea41 0105 orr.w r1, r1, r5
  183. 800437e: bd30 pop {r4, r5, pc}
  184. 8004380: ea5f 0c4c movs.w ip, ip, lsl #1
  185. 8004384: 4140 adcs r0, r0
  186. 8004386: eb41 0101 adc.w r1, r1, r1
  187. 800438a: f411 1f80 tst.w r1, #1048576 ; 0x100000
  188. 800438e: f1a4 0401 sub.w r4, r4, #1
  189. 8004392: d1e9 bne.n 8004368 <__adddf3+0x10c>
  190. 8004394: f091 0f00 teq r1, #0
  191. 8004398: bf04 itt eq
  192. 800439a: 4601 moveq r1, r0
  193. 800439c: 2000 moveq r0, #0
  194. 800439e: fab1 f381 clz r3, r1
  195. 80043a2: bf08 it eq
  196. 80043a4: 3320 addeq r3, #32
  197. 80043a6: f1a3 030b sub.w r3, r3, #11
  198. 80043aa: f1b3 0220 subs.w r2, r3, #32
  199. 80043ae: da0c bge.n 80043ca <__adddf3+0x16e>
  200. 80043b0: 320c adds r2, #12
  201. 80043b2: dd08 ble.n 80043c6 <__adddf3+0x16a>
  202. 80043b4: f102 0c14 add.w ip, r2, #20
  203. 80043b8: f1c2 020c rsb r2, r2, #12
  204. 80043bc: fa01 f00c lsl.w r0, r1, ip
  205. 80043c0: fa21 f102 lsr.w r1, r1, r2
  206. 80043c4: e00c b.n 80043e0 <__adddf3+0x184>
  207. 80043c6: f102 0214 add.w r2, r2, #20
  208. 80043ca: bfd8 it le
  209. 80043cc: f1c2 0c20 rsble ip, r2, #32
  210. 80043d0: fa01 f102 lsl.w r1, r1, r2
  211. 80043d4: fa20 fc0c lsr.w ip, r0, ip
  212. 80043d8: bfdc itt le
  213. 80043da: ea41 010c orrle.w r1, r1, ip
  214. 80043de: 4090 lslle r0, r2
  215. 80043e0: 1ae4 subs r4, r4, r3
  216. 80043e2: bfa2 ittt ge
  217. 80043e4: eb01 5104 addge.w r1, r1, r4, lsl #20
  218. 80043e8: 4329 orrge r1, r5
  219. 80043ea: bd30 popge {r4, r5, pc}
  220. 80043ec: ea6f 0404 mvn.w r4, r4
  221. 80043f0: 3c1f subs r4, #31
  222. 80043f2: da1c bge.n 800442e <__adddf3+0x1d2>
  223. 80043f4: 340c adds r4, #12
  224. 80043f6: dc0e bgt.n 8004416 <__adddf3+0x1ba>
  225. 80043f8: f104 0414 add.w r4, r4, #20
  226. 80043fc: f1c4 0220 rsb r2, r4, #32
  227. 8004400: fa20 f004 lsr.w r0, r0, r4
  228. 8004404: fa01 f302 lsl.w r3, r1, r2
  229. 8004408: ea40 0003 orr.w r0, r0, r3
  230. 800440c: fa21 f304 lsr.w r3, r1, r4
  231. 8004410: ea45 0103 orr.w r1, r5, r3
  232. 8004414: bd30 pop {r4, r5, pc}
  233. 8004416: f1c4 040c rsb r4, r4, #12
  234. 800441a: f1c4 0220 rsb r2, r4, #32
  235. 800441e: fa20 f002 lsr.w r0, r0, r2
  236. 8004422: fa01 f304 lsl.w r3, r1, r4
  237. 8004426: ea40 0003 orr.w r0, r0, r3
  238. 800442a: 4629 mov r1, r5
  239. 800442c: bd30 pop {r4, r5, pc}
  240. 800442e: fa21 f004 lsr.w r0, r1, r4
  241. 8004432: 4629 mov r1, r5
  242. 8004434: bd30 pop {r4, r5, pc}
  243. 8004436: f094 0f00 teq r4, #0
  244. 800443a: f483 1380 eor.w r3, r3, #1048576 ; 0x100000
  245. 800443e: bf06 itte eq
  246. 8004440: f481 1180 eoreq.w r1, r1, #1048576 ; 0x100000
  247. 8004444: 3401 addeq r4, #1
  248. 8004446: 3d01 subne r5, #1
  249. 8004448: e74e b.n 80042e8 <__adddf3+0x8c>
  250. 800444a: ea7f 5c64 mvns.w ip, r4, asr #21
  251. 800444e: bf18 it ne
  252. 8004450: ea7f 5c65 mvnsne.w ip, r5, asr #21
  253. 8004454: d029 beq.n 80044aa <__adddf3+0x24e>
  254. 8004456: ea94 0f05 teq r4, r5
  255. 800445a: bf08 it eq
  256. 800445c: ea90 0f02 teqeq r0, r2
  257. 8004460: d005 beq.n 800446e <__adddf3+0x212>
  258. 8004462: ea54 0c00 orrs.w ip, r4, r0
  259. 8004466: bf04 itt eq
  260. 8004468: 4619 moveq r1, r3
  261. 800446a: 4610 moveq r0, r2
  262. 800446c: bd30 pop {r4, r5, pc}
  263. 800446e: ea91 0f03 teq r1, r3
  264. 8004472: bf1e ittt ne
  265. 8004474: 2100 movne r1, #0
  266. 8004476: 2000 movne r0, #0
  267. 8004478: bd30 popne {r4, r5, pc}
  268. 800447a: ea5f 5c54 movs.w ip, r4, lsr #21
  269. 800447e: d105 bne.n 800448c <__adddf3+0x230>
  270. 8004480: 0040 lsls r0, r0, #1
  271. 8004482: 4149 adcs r1, r1
  272. 8004484: bf28 it cs
  273. 8004486: f041 4100 orrcs.w r1, r1, #2147483648 ; 0x80000000
  274. 800448a: bd30 pop {r4, r5, pc}
  275. 800448c: f514 0480 adds.w r4, r4, #4194304 ; 0x400000
  276. 8004490: bf3c itt cc
  277. 8004492: f501 1180 addcc.w r1, r1, #1048576 ; 0x100000
  278. 8004496: bd30 popcc {r4, r5, pc}
  279. 8004498: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000
  280. 800449c: f045 41fe orr.w r1, r5, #2130706432 ; 0x7f000000
  281. 80044a0: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000
  282. 80044a4: f04f 0000 mov.w r0, #0
  283. 80044a8: bd30 pop {r4, r5, pc}
  284. 80044aa: ea7f 5c64 mvns.w ip, r4, asr #21
  285. 80044ae: bf1a itte ne
  286. 80044b0: 4619 movne r1, r3
  287. 80044b2: 4610 movne r0, r2
  288. 80044b4: ea7f 5c65 mvnseq.w ip, r5, asr #21
  289. 80044b8: bf1c itt ne
  290. 80044ba: 460b movne r3, r1
  291. 80044bc: 4602 movne r2, r0
  292. 80044be: ea50 3401 orrs.w r4, r0, r1, lsl #12
  293. 80044c2: bf06 itte eq
  294. 80044c4: ea52 3503 orrseq.w r5, r2, r3, lsl #12
  295. 80044c8: ea91 0f03 teqeq r1, r3
  296. 80044cc: f441 2100 orrne.w r1, r1, #524288 ; 0x80000
  297. 80044d0: bd30 pop {r4, r5, pc}
  298. 80044d2: bf00 nop
  299. 080044d4 <__aeabi_ui2d>:
  300. 80044d4: f090 0f00 teq r0, #0
  301. 80044d8: bf04 itt eq
  302. 80044da: 2100 moveq r1, #0
  303. 80044dc: 4770 bxeq lr
  304. 80044de: b530 push {r4, r5, lr}
  305. 80044e0: f44f 6480 mov.w r4, #1024 ; 0x400
  306. 80044e4: f104 0432 add.w r4, r4, #50 ; 0x32
  307. 80044e8: f04f 0500 mov.w r5, #0
  308. 80044ec: f04f 0100 mov.w r1, #0
  309. 80044f0: e750 b.n 8004394 <__adddf3+0x138>
  310. 80044f2: bf00 nop
  311. 080044f4 <__aeabi_i2d>:
  312. 80044f4: f090 0f00 teq r0, #0
  313. 80044f8: bf04 itt eq
  314. 80044fa: 2100 moveq r1, #0
  315. 80044fc: 4770 bxeq lr
  316. 80044fe: b530 push {r4, r5, lr}
  317. 8004500: f44f 6480 mov.w r4, #1024 ; 0x400
  318. 8004504: f104 0432 add.w r4, r4, #50 ; 0x32
  319. 8004508: f010 4500 ands.w r5, r0, #2147483648 ; 0x80000000
  320. 800450c: bf48 it mi
  321. 800450e: 4240 negmi r0, r0
  322. 8004510: f04f 0100 mov.w r1, #0
  323. 8004514: e73e b.n 8004394 <__adddf3+0x138>
  324. 8004516: bf00 nop
  325. 08004518 <__aeabi_f2d>:
  326. 8004518: 0042 lsls r2, r0, #1
  327. 800451a: ea4f 01e2 mov.w r1, r2, asr #3
  328. 800451e: ea4f 0131 mov.w r1, r1, rrx
  329. 8004522: ea4f 7002 mov.w r0, r2, lsl #28
  330. 8004526: bf1f itttt ne
  331. 8004528: f012 437f andsne.w r3, r2, #4278190080 ; 0xff000000
  332. 800452c: f093 4f7f teqne r3, #4278190080 ; 0xff000000
  333. 8004530: f081 5160 eorne.w r1, r1, #939524096 ; 0x38000000
  334. 8004534: 4770 bxne lr
  335. 8004536: f092 0f00 teq r2, #0
  336. 800453a: bf14 ite ne
  337. 800453c: f093 4f7f teqne r3, #4278190080 ; 0xff000000
  338. 8004540: 4770 bxeq lr
  339. 8004542: b530 push {r4, r5, lr}
  340. 8004544: f44f 7460 mov.w r4, #896 ; 0x380
  341. 8004548: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000
  342. 800454c: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000
  343. 8004550: e720 b.n 8004394 <__adddf3+0x138>
  344. 8004552: bf00 nop
  345. 08004554 <__aeabi_ul2d>:
  346. 8004554: ea50 0201 orrs.w r2, r0, r1
  347. 8004558: bf08 it eq
  348. 800455a: 4770 bxeq lr
  349. 800455c: b530 push {r4, r5, lr}
  350. 800455e: f04f 0500 mov.w r5, #0
  351. 8004562: e00a b.n 800457a <__aeabi_l2d+0x16>
  352. 08004564 <__aeabi_l2d>:
  353. 8004564: ea50 0201 orrs.w r2, r0, r1
  354. 8004568: bf08 it eq
  355. 800456a: 4770 bxeq lr
  356. 800456c: b530 push {r4, r5, lr}
  357. 800456e: f011 4500 ands.w r5, r1, #2147483648 ; 0x80000000
  358. 8004572: d502 bpl.n 800457a <__aeabi_l2d+0x16>
  359. 8004574: 4240 negs r0, r0
  360. 8004576: eb61 0141 sbc.w r1, r1, r1, lsl #1
  361. 800457a: f44f 6480 mov.w r4, #1024 ; 0x400
  362. 800457e: f104 0432 add.w r4, r4, #50 ; 0x32
  363. 8004582: ea5f 5c91 movs.w ip, r1, lsr #22
  364. 8004586: f43f aedc beq.w 8004342 <__adddf3+0xe6>
  365. 800458a: f04f 0203 mov.w r2, #3
  366. 800458e: ea5f 0cdc movs.w ip, ip, lsr #3
  367. 8004592: bf18 it ne
  368. 8004594: 3203 addne r2, #3
  369. 8004596: ea5f 0cdc movs.w ip, ip, lsr #3
  370. 800459a: bf18 it ne
  371. 800459c: 3203 addne r2, #3
  372. 800459e: eb02 02dc add.w r2, r2, ip, lsr #3
  373. 80045a2: f1c2 0320 rsb r3, r2, #32
  374. 80045a6: fa00 fc03 lsl.w ip, r0, r3
  375. 80045aa: fa20 f002 lsr.w r0, r0, r2
  376. 80045ae: fa01 fe03 lsl.w lr, r1, r3
  377. 80045b2: ea40 000e orr.w r0, r0, lr
  378. 80045b6: fa21 f102 lsr.w r1, r1, r2
  379. 80045ba: 4414 add r4, r2
  380. 80045bc: e6c1 b.n 8004342 <__adddf3+0xe6>
  381. 80045be: bf00 nop
  382. 080045c0 <__aeabi_dmul>:
  383. 80045c0: b570 push {r4, r5, r6, lr}
  384. 80045c2: f04f 0cff mov.w ip, #255 ; 0xff
  385. 80045c6: f44c 6ce0 orr.w ip, ip, #1792 ; 0x700
  386. 80045ca: ea1c 5411 ands.w r4, ip, r1, lsr #20
  387. 80045ce: bf1d ittte ne
  388. 80045d0: ea1c 5513 andsne.w r5, ip, r3, lsr #20
  389. 80045d4: ea94 0f0c teqne r4, ip
  390. 80045d8: ea95 0f0c teqne r5, ip
  391. 80045dc: f000 f8de bleq 800479c <__aeabi_dmul+0x1dc>
  392. 80045e0: 442c add r4, r5
  393. 80045e2: ea81 0603 eor.w r6, r1, r3
  394. 80045e6: ea21 514c bic.w r1, r1, ip, lsl #21
  395. 80045ea: ea23 534c bic.w r3, r3, ip, lsl #21
  396. 80045ee: ea50 3501 orrs.w r5, r0, r1, lsl #12
  397. 80045f2: bf18 it ne
  398. 80045f4: ea52 3503 orrsne.w r5, r2, r3, lsl #12
  399. 80045f8: f441 1180 orr.w r1, r1, #1048576 ; 0x100000
  400. 80045fc: f443 1380 orr.w r3, r3, #1048576 ; 0x100000
  401. 8004600: d038 beq.n 8004674 <__aeabi_dmul+0xb4>
  402. 8004602: fba0 ce02 umull ip, lr, r0, r2
  403. 8004606: f04f 0500 mov.w r5, #0
  404. 800460a: fbe1 e502 umlal lr, r5, r1, r2
  405. 800460e: f006 4200 and.w r2, r6, #2147483648 ; 0x80000000
  406. 8004612: fbe0 e503 umlal lr, r5, r0, r3
  407. 8004616: f04f 0600 mov.w r6, #0
  408. 800461a: fbe1 5603 umlal r5, r6, r1, r3
  409. 800461e: f09c 0f00 teq ip, #0
  410. 8004622: bf18 it ne
  411. 8004624: f04e 0e01 orrne.w lr, lr, #1
  412. 8004628: f1a4 04ff sub.w r4, r4, #255 ; 0xff
  413. 800462c: f5b6 7f00 cmp.w r6, #512 ; 0x200
  414. 8004630: f564 7440 sbc.w r4, r4, #768 ; 0x300
  415. 8004634: d204 bcs.n 8004640 <__aeabi_dmul+0x80>
  416. 8004636: ea5f 0e4e movs.w lr, lr, lsl #1
  417. 800463a: 416d adcs r5, r5
  418. 800463c: eb46 0606 adc.w r6, r6, r6
  419. 8004640: ea42 21c6 orr.w r1, r2, r6, lsl #11
  420. 8004644: ea41 5155 orr.w r1, r1, r5, lsr #21
  421. 8004648: ea4f 20c5 mov.w r0, r5, lsl #11
  422. 800464c: ea40 505e orr.w r0, r0, lr, lsr #21
  423. 8004650: ea4f 2ece mov.w lr, lr, lsl #11
  424. 8004654: f1b4 0cfd subs.w ip, r4, #253 ; 0xfd
  425. 8004658: bf88 it hi
  426. 800465a: f5bc 6fe0 cmphi.w ip, #1792 ; 0x700
  427. 800465e: d81e bhi.n 800469e <__aeabi_dmul+0xde>
  428. 8004660: f1be 4f00 cmp.w lr, #2147483648 ; 0x80000000
  429. 8004664: bf08 it eq
  430. 8004666: ea5f 0e50 movseq.w lr, r0, lsr #1
  431. 800466a: f150 0000 adcs.w r0, r0, #0
  432. 800466e: eb41 5104 adc.w r1, r1, r4, lsl #20
  433. 8004672: bd70 pop {r4, r5, r6, pc}
  434. 8004674: f006 4600 and.w r6, r6, #2147483648 ; 0x80000000
  435. 8004678: ea46 0101 orr.w r1, r6, r1
  436. 800467c: ea40 0002 orr.w r0, r0, r2
  437. 8004680: ea81 0103 eor.w r1, r1, r3
  438. 8004684: ebb4 045c subs.w r4, r4, ip, lsr #1
  439. 8004688: bfc2 ittt gt
  440. 800468a: ebd4 050c rsbsgt r5, r4, ip
  441. 800468e: ea41 5104 orrgt.w r1, r1, r4, lsl #20
  442. 8004692: bd70 popgt {r4, r5, r6, pc}
  443. 8004694: f441 1180 orr.w r1, r1, #1048576 ; 0x100000
  444. 8004698: f04f 0e00 mov.w lr, #0
  445. 800469c: 3c01 subs r4, #1
  446. 800469e: f300 80ab bgt.w 80047f8 <__aeabi_dmul+0x238>
  447. 80046a2: f114 0f36 cmn.w r4, #54 ; 0x36
  448. 80046a6: bfde ittt le
  449. 80046a8: 2000 movle r0, #0
  450. 80046aa: f001 4100 andle.w r1, r1, #2147483648 ; 0x80000000
  451. 80046ae: bd70 pople {r4, r5, r6, pc}
  452. 80046b0: f1c4 0400 rsb r4, r4, #0
  453. 80046b4: 3c20 subs r4, #32
  454. 80046b6: da35 bge.n 8004724 <__aeabi_dmul+0x164>
  455. 80046b8: 340c adds r4, #12
  456. 80046ba: dc1b bgt.n 80046f4 <__aeabi_dmul+0x134>
  457. 80046bc: f104 0414 add.w r4, r4, #20
  458. 80046c0: f1c4 0520 rsb r5, r4, #32
  459. 80046c4: fa00 f305 lsl.w r3, r0, r5
  460. 80046c8: fa20 f004 lsr.w r0, r0, r4
  461. 80046cc: fa01 f205 lsl.w r2, r1, r5
  462. 80046d0: ea40 0002 orr.w r0, r0, r2
  463. 80046d4: f001 4200 and.w r2, r1, #2147483648 ; 0x80000000
  464. 80046d8: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000
  465. 80046dc: eb10 70d3 adds.w r0, r0, r3, lsr #31
  466. 80046e0: fa21 f604 lsr.w r6, r1, r4
  467. 80046e4: eb42 0106 adc.w r1, r2, r6
  468. 80046e8: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
  469. 80046ec: bf08 it eq
  470. 80046ee: ea20 70d3 biceq.w r0, r0, r3, lsr #31
  471. 80046f2: bd70 pop {r4, r5, r6, pc}
  472. 80046f4: f1c4 040c rsb r4, r4, #12
  473. 80046f8: f1c4 0520 rsb r5, r4, #32
  474. 80046fc: fa00 f304 lsl.w r3, r0, r4
  475. 8004700: fa20 f005 lsr.w r0, r0, r5
  476. 8004704: fa01 f204 lsl.w r2, r1, r4
  477. 8004708: ea40 0002 orr.w r0, r0, r2
  478. 800470c: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000
  479. 8004710: eb10 70d3 adds.w r0, r0, r3, lsr #31
  480. 8004714: f141 0100 adc.w r1, r1, #0
  481. 8004718: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
  482. 800471c: bf08 it eq
  483. 800471e: ea20 70d3 biceq.w r0, r0, r3, lsr #31
  484. 8004722: bd70 pop {r4, r5, r6, pc}
  485. 8004724: f1c4 0520 rsb r5, r4, #32
  486. 8004728: fa00 f205 lsl.w r2, r0, r5
  487. 800472c: ea4e 0e02 orr.w lr, lr, r2
  488. 8004730: fa20 f304 lsr.w r3, r0, r4
  489. 8004734: fa01 f205 lsl.w r2, r1, r5
  490. 8004738: ea43 0302 orr.w r3, r3, r2
  491. 800473c: fa21 f004 lsr.w r0, r1, r4
  492. 8004740: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000
  493. 8004744: fa21 f204 lsr.w r2, r1, r4
  494. 8004748: ea20 0002 bic.w r0, r0, r2
  495. 800474c: eb00 70d3 add.w r0, r0, r3, lsr #31
  496. 8004750: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
  497. 8004754: bf08 it eq
  498. 8004756: ea20 70d3 biceq.w r0, r0, r3, lsr #31
  499. 800475a: bd70 pop {r4, r5, r6, pc}
  500. 800475c: f094 0f00 teq r4, #0
  501. 8004760: d10f bne.n 8004782 <__aeabi_dmul+0x1c2>
  502. 8004762: f001 4600 and.w r6, r1, #2147483648 ; 0x80000000
  503. 8004766: 0040 lsls r0, r0, #1
  504. 8004768: eb41 0101 adc.w r1, r1, r1
  505. 800476c: f411 1f80 tst.w r1, #1048576 ; 0x100000
  506. 8004770: bf08 it eq
  507. 8004772: 3c01 subeq r4, #1
  508. 8004774: d0f7 beq.n 8004766 <__aeabi_dmul+0x1a6>
  509. 8004776: ea41 0106 orr.w r1, r1, r6
  510. 800477a: f095 0f00 teq r5, #0
  511. 800477e: bf18 it ne
  512. 8004780: 4770 bxne lr
  513. 8004782: f003 4600 and.w r6, r3, #2147483648 ; 0x80000000
  514. 8004786: 0052 lsls r2, r2, #1
  515. 8004788: eb43 0303 adc.w r3, r3, r3
  516. 800478c: f413 1f80 tst.w r3, #1048576 ; 0x100000
  517. 8004790: bf08 it eq
  518. 8004792: 3d01 subeq r5, #1
  519. 8004794: d0f7 beq.n 8004786 <__aeabi_dmul+0x1c6>
  520. 8004796: ea43 0306 orr.w r3, r3, r6
  521. 800479a: 4770 bx lr
  522. 800479c: ea94 0f0c teq r4, ip
  523. 80047a0: ea0c 5513 and.w r5, ip, r3, lsr #20
  524. 80047a4: bf18 it ne
  525. 80047a6: ea95 0f0c teqne r5, ip
  526. 80047aa: d00c beq.n 80047c6 <__aeabi_dmul+0x206>
  527. 80047ac: ea50 0641 orrs.w r6, r0, r1, lsl #1
  528. 80047b0: bf18 it ne
  529. 80047b2: ea52 0643 orrsne.w r6, r2, r3, lsl #1
  530. 80047b6: d1d1 bne.n 800475c <__aeabi_dmul+0x19c>
  531. 80047b8: ea81 0103 eor.w r1, r1, r3
  532. 80047bc: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000
  533. 80047c0: f04f 0000 mov.w r0, #0
  534. 80047c4: bd70 pop {r4, r5, r6, pc}
  535. 80047c6: ea50 0641 orrs.w r6, r0, r1, lsl #1
  536. 80047ca: bf06 itte eq
  537. 80047cc: 4610 moveq r0, r2
  538. 80047ce: 4619 moveq r1, r3
  539. 80047d0: ea52 0643 orrsne.w r6, r2, r3, lsl #1
  540. 80047d4: d019 beq.n 800480a <__aeabi_dmul+0x24a>
  541. 80047d6: ea94 0f0c teq r4, ip
  542. 80047da: d102 bne.n 80047e2 <__aeabi_dmul+0x222>
  543. 80047dc: ea50 3601 orrs.w r6, r0, r1, lsl #12
  544. 80047e0: d113 bne.n 800480a <__aeabi_dmul+0x24a>
  545. 80047e2: ea95 0f0c teq r5, ip
  546. 80047e6: d105 bne.n 80047f4 <__aeabi_dmul+0x234>
  547. 80047e8: ea52 3603 orrs.w r6, r2, r3, lsl #12
  548. 80047ec: bf1c itt ne
  549. 80047ee: 4610 movne r0, r2
  550. 80047f0: 4619 movne r1, r3
  551. 80047f2: d10a bne.n 800480a <__aeabi_dmul+0x24a>
  552. 80047f4: ea81 0103 eor.w r1, r1, r3
  553. 80047f8: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000
  554. 80047fc: f041 41fe orr.w r1, r1, #2130706432 ; 0x7f000000
  555. 8004800: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000
  556. 8004804: f04f 0000 mov.w r0, #0
  557. 8004808: bd70 pop {r4, r5, r6, pc}
  558. 800480a: f041 41fe orr.w r1, r1, #2130706432 ; 0x7f000000
  559. 800480e: f441 0178 orr.w r1, r1, #16252928 ; 0xf80000
  560. 8004812: bd70 pop {r4, r5, r6, pc}
  561. 08004814 <__aeabi_ddiv>:
  562. 8004814: b570 push {r4, r5, r6, lr}
  563. 8004816: f04f 0cff mov.w ip, #255 ; 0xff
  564. 800481a: f44c 6ce0 orr.w ip, ip, #1792 ; 0x700
  565. 800481e: ea1c 5411 ands.w r4, ip, r1, lsr #20
  566. 8004822: bf1d ittte ne
  567. 8004824: ea1c 5513 andsne.w r5, ip, r3, lsr #20
  568. 8004828: ea94 0f0c teqne r4, ip
  569. 800482c: ea95 0f0c teqne r5, ip
  570. 8004830: f000 f8a7 bleq 8004982 <__aeabi_ddiv+0x16e>
  571. 8004834: eba4 0405 sub.w r4, r4, r5
  572. 8004838: ea81 0e03 eor.w lr, r1, r3
  573. 800483c: ea52 3503 orrs.w r5, r2, r3, lsl #12
  574. 8004840: ea4f 3101 mov.w r1, r1, lsl #12
  575. 8004844: f000 8088 beq.w 8004958 <__aeabi_ddiv+0x144>
  576. 8004848: ea4f 3303 mov.w r3, r3, lsl #12
  577. 800484c: f04f 5580 mov.w r5, #268435456 ; 0x10000000
  578. 8004850: ea45 1313 orr.w r3, r5, r3, lsr #4
  579. 8004854: ea43 6312 orr.w r3, r3, r2, lsr #24
  580. 8004858: ea4f 2202 mov.w r2, r2, lsl #8
  581. 800485c: ea45 1511 orr.w r5, r5, r1, lsr #4
  582. 8004860: ea45 6510 orr.w r5, r5, r0, lsr #24
  583. 8004864: ea4f 2600 mov.w r6, r0, lsl #8
  584. 8004868: f00e 4100 and.w r1, lr, #2147483648 ; 0x80000000
  585. 800486c: 429d cmp r5, r3
  586. 800486e: bf08 it eq
  587. 8004870: 4296 cmpeq r6, r2
  588. 8004872: f144 04fd adc.w r4, r4, #253 ; 0xfd
  589. 8004876: f504 7440 add.w r4, r4, #768 ; 0x300
  590. 800487a: d202 bcs.n 8004882 <__aeabi_ddiv+0x6e>
  591. 800487c: 085b lsrs r3, r3, #1
  592. 800487e: ea4f 0232 mov.w r2, r2, rrx
  593. 8004882: 1ab6 subs r6, r6, r2
  594. 8004884: eb65 0503 sbc.w r5, r5, r3
  595. 8004888: 085b lsrs r3, r3, #1
  596. 800488a: ea4f 0232 mov.w r2, r2, rrx
  597. 800488e: f44f 1080 mov.w r0, #1048576 ; 0x100000
  598. 8004892: f44f 2c00 mov.w ip, #524288 ; 0x80000
  599. 8004896: ebb6 0e02 subs.w lr, r6, r2
  600. 800489a: eb75 0e03 sbcs.w lr, r5, r3
  601. 800489e: bf22 ittt cs
  602. 80048a0: 1ab6 subcs r6, r6, r2
  603. 80048a2: 4675 movcs r5, lr
  604. 80048a4: ea40 000c orrcs.w r0, r0, ip
  605. 80048a8: 085b lsrs r3, r3, #1
  606. 80048aa: ea4f 0232 mov.w r2, r2, rrx
  607. 80048ae: ebb6 0e02 subs.w lr, r6, r2
  608. 80048b2: eb75 0e03 sbcs.w lr, r5, r3
  609. 80048b6: bf22 ittt cs
  610. 80048b8: 1ab6 subcs r6, r6, r2
  611. 80048ba: 4675 movcs r5, lr
  612. 80048bc: ea40 005c orrcs.w r0, r0, ip, lsr #1
  613. 80048c0: 085b lsrs r3, r3, #1
  614. 80048c2: ea4f 0232 mov.w r2, r2, rrx
  615. 80048c6: ebb6 0e02 subs.w lr, r6, r2
  616. 80048ca: eb75 0e03 sbcs.w lr, r5, r3
  617. 80048ce: bf22 ittt cs
  618. 80048d0: 1ab6 subcs r6, r6, r2
  619. 80048d2: 4675 movcs r5, lr
  620. 80048d4: ea40 009c orrcs.w r0, r0, ip, lsr #2
  621. 80048d8: 085b lsrs r3, r3, #1
  622. 80048da: ea4f 0232 mov.w r2, r2, rrx
  623. 80048de: ebb6 0e02 subs.w lr, r6, r2
  624. 80048e2: eb75 0e03 sbcs.w lr, r5, r3
  625. 80048e6: bf22 ittt cs
  626. 80048e8: 1ab6 subcs r6, r6, r2
  627. 80048ea: 4675 movcs r5, lr
  628. 80048ec: ea40 00dc orrcs.w r0, r0, ip, lsr #3
  629. 80048f0: ea55 0e06 orrs.w lr, r5, r6
  630. 80048f4: d018 beq.n 8004928 <__aeabi_ddiv+0x114>
  631. 80048f6: ea4f 1505 mov.w r5, r5, lsl #4
  632. 80048fa: ea45 7516 orr.w r5, r5, r6, lsr #28
  633. 80048fe: ea4f 1606 mov.w r6, r6, lsl #4
  634. 8004902: ea4f 03c3 mov.w r3, r3, lsl #3
  635. 8004906: ea43 7352 orr.w r3, r3, r2, lsr #29
  636. 800490a: ea4f 02c2 mov.w r2, r2, lsl #3
  637. 800490e: ea5f 1c1c movs.w ip, ip, lsr #4
  638. 8004912: d1c0 bne.n 8004896 <__aeabi_ddiv+0x82>
  639. 8004914: f411 1f80 tst.w r1, #1048576 ; 0x100000
  640. 8004918: d10b bne.n 8004932 <__aeabi_ddiv+0x11e>
  641. 800491a: ea41 0100 orr.w r1, r1, r0
  642. 800491e: f04f 0000 mov.w r0, #0
  643. 8004922: f04f 4c00 mov.w ip, #2147483648 ; 0x80000000
  644. 8004926: e7b6 b.n 8004896 <__aeabi_ddiv+0x82>
  645. 8004928: f411 1f80 tst.w r1, #1048576 ; 0x100000
  646. 800492c: bf04 itt eq
  647. 800492e: 4301 orreq r1, r0
  648. 8004930: 2000 moveq r0, #0
  649. 8004932: f1b4 0cfd subs.w ip, r4, #253 ; 0xfd
  650. 8004936: bf88 it hi
  651. 8004938: f5bc 6fe0 cmphi.w ip, #1792 ; 0x700
  652. 800493c: f63f aeaf bhi.w 800469e <__aeabi_dmul+0xde>
  653. 8004940: ebb5 0c03 subs.w ip, r5, r3
  654. 8004944: bf04 itt eq
  655. 8004946: ebb6 0c02 subseq.w ip, r6, r2
  656. 800494a: ea5f 0c50 movseq.w ip, r0, lsr #1
  657. 800494e: f150 0000 adcs.w r0, r0, #0
  658. 8004952: eb41 5104 adc.w r1, r1, r4, lsl #20
  659. 8004956: bd70 pop {r4, r5, r6, pc}
  660. 8004958: f00e 4e00 and.w lr, lr, #2147483648 ; 0x80000000
  661. 800495c: ea4e 3111 orr.w r1, lr, r1, lsr #12
  662. 8004960: eb14 045c adds.w r4, r4, ip, lsr #1
  663. 8004964: bfc2 ittt gt
  664. 8004966: ebd4 050c rsbsgt r5, r4, ip
  665. 800496a: ea41 5104 orrgt.w r1, r1, r4, lsl #20
  666. 800496e: bd70 popgt {r4, r5, r6, pc}
  667. 8004970: f441 1180 orr.w r1, r1, #1048576 ; 0x100000
  668. 8004974: f04f 0e00 mov.w lr, #0
  669. 8004978: 3c01 subs r4, #1
  670. 800497a: e690 b.n 800469e <__aeabi_dmul+0xde>
  671. 800497c: ea45 0e06 orr.w lr, r5, r6
  672. 8004980: e68d b.n 800469e <__aeabi_dmul+0xde>
  673. 8004982: ea0c 5513 and.w r5, ip, r3, lsr #20
  674. 8004986: ea94 0f0c teq r4, ip
  675. 800498a: bf08 it eq
  676. 800498c: ea95 0f0c teqeq r5, ip
  677. 8004990: f43f af3b beq.w 800480a <__aeabi_dmul+0x24a>
  678. 8004994: ea94 0f0c teq r4, ip
  679. 8004998: d10a bne.n 80049b0 <__aeabi_ddiv+0x19c>
  680. 800499a: ea50 3401 orrs.w r4, r0, r1, lsl #12
  681. 800499e: f47f af34 bne.w 800480a <__aeabi_dmul+0x24a>
  682. 80049a2: ea95 0f0c teq r5, ip
  683. 80049a6: f47f af25 bne.w 80047f4 <__aeabi_dmul+0x234>
  684. 80049aa: 4610 mov r0, r2
  685. 80049ac: 4619 mov r1, r3
  686. 80049ae: e72c b.n 800480a <__aeabi_dmul+0x24a>
  687. 80049b0: ea95 0f0c teq r5, ip
  688. 80049b4: d106 bne.n 80049c4 <__aeabi_ddiv+0x1b0>
  689. 80049b6: ea52 3503 orrs.w r5, r2, r3, lsl #12
  690. 80049ba: f43f aefd beq.w 80047b8 <__aeabi_dmul+0x1f8>
  691. 80049be: 4610 mov r0, r2
  692. 80049c0: 4619 mov r1, r3
  693. 80049c2: e722 b.n 800480a <__aeabi_dmul+0x24a>
  694. 80049c4: ea50 0641 orrs.w r6, r0, r1, lsl #1
  695. 80049c8: bf18 it ne
  696. 80049ca: ea52 0643 orrsne.w r6, r2, r3, lsl #1
  697. 80049ce: f47f aec5 bne.w 800475c <__aeabi_dmul+0x19c>
  698. 80049d2: ea50 0441 orrs.w r4, r0, r1, lsl #1
  699. 80049d6: f47f af0d bne.w 80047f4 <__aeabi_dmul+0x234>
  700. 80049da: ea52 0543 orrs.w r5, r2, r3, lsl #1
  701. 80049de: f47f aeeb bne.w 80047b8 <__aeabi_dmul+0x1f8>
  702. 80049e2: e712 b.n 800480a <__aeabi_dmul+0x24a>
  703. 080049e4 <__gedf2>:
  704. 80049e4: f04f 3cff mov.w ip, #4294967295
  705. 80049e8: e006 b.n 80049f8 <__cmpdf2+0x4>
  706. 80049ea: bf00 nop
  707. 080049ec <__ledf2>:
  708. 80049ec: f04f 0c01 mov.w ip, #1
  709. 80049f0: e002 b.n 80049f8 <__cmpdf2+0x4>
  710. 80049f2: bf00 nop
  711. 080049f4 <__cmpdf2>:
  712. 80049f4: f04f 0c01 mov.w ip, #1
  713. 80049f8: f84d cd04 str.w ip, [sp, #-4]!
  714. 80049fc: ea4f 0c41 mov.w ip, r1, lsl #1
  715. 8004a00: ea7f 5c6c mvns.w ip, ip, asr #21
  716. 8004a04: ea4f 0c43 mov.w ip, r3, lsl #1
  717. 8004a08: bf18 it ne
  718. 8004a0a: ea7f 5c6c mvnsne.w ip, ip, asr #21
  719. 8004a0e: d01b beq.n 8004a48 <__cmpdf2+0x54>
  720. 8004a10: b001 add sp, #4
  721. 8004a12: ea50 0c41 orrs.w ip, r0, r1, lsl #1
  722. 8004a16: bf0c ite eq
  723. 8004a18: ea52 0c43 orrseq.w ip, r2, r3, lsl #1
  724. 8004a1c: ea91 0f03 teqne r1, r3
  725. 8004a20: bf02 ittt eq
  726. 8004a22: ea90 0f02 teqeq r0, r2
  727. 8004a26: 2000 moveq r0, #0
  728. 8004a28: 4770 bxeq lr
  729. 8004a2a: f110 0f00 cmn.w r0, #0
  730. 8004a2e: ea91 0f03 teq r1, r3
  731. 8004a32: bf58 it pl
  732. 8004a34: 4299 cmppl r1, r3
  733. 8004a36: bf08 it eq
  734. 8004a38: 4290 cmpeq r0, r2
  735. 8004a3a: bf2c ite cs
  736. 8004a3c: 17d8 asrcs r0, r3, #31
  737. 8004a3e: ea6f 70e3 mvncc.w r0, r3, asr #31
  738. 8004a42: f040 0001 orr.w r0, r0, #1
  739. 8004a46: 4770 bx lr
  740. 8004a48: ea4f 0c41 mov.w ip, r1, lsl #1
  741. 8004a4c: ea7f 5c6c mvns.w ip, ip, asr #21
  742. 8004a50: d102 bne.n 8004a58 <__cmpdf2+0x64>
  743. 8004a52: ea50 3c01 orrs.w ip, r0, r1, lsl #12
  744. 8004a56: d107 bne.n 8004a68 <__cmpdf2+0x74>
  745. 8004a58: ea4f 0c43 mov.w ip, r3, lsl #1
  746. 8004a5c: ea7f 5c6c mvns.w ip, ip, asr #21
  747. 8004a60: d1d6 bne.n 8004a10 <__cmpdf2+0x1c>
  748. 8004a62: ea52 3c03 orrs.w ip, r2, r3, lsl #12
  749. 8004a66: d0d3 beq.n 8004a10 <__cmpdf2+0x1c>
  750. 8004a68: f85d 0b04 ldr.w r0, [sp], #4
  751. 8004a6c: 4770 bx lr
  752. 8004a6e: bf00 nop
  753. 08004a70 <__aeabi_cdrcmple>:
  754. 8004a70: 4684 mov ip, r0
  755. 8004a72: 4610 mov r0, r2
  756. 8004a74: 4662 mov r2, ip
  757. 8004a76: 468c mov ip, r1
  758. 8004a78: 4619 mov r1, r3
  759. 8004a7a: 4663 mov r3, ip
  760. 8004a7c: e000 b.n 8004a80 <__aeabi_cdcmpeq>
  761. 8004a7e: bf00 nop
  762. 08004a80 <__aeabi_cdcmpeq>:
  763. 8004a80: b501 push {r0, lr}
  764. 8004a82: f7ff ffb7 bl 80049f4 <__cmpdf2>
  765. 8004a86: 2800 cmp r0, #0
  766. 8004a88: bf48 it mi
  767. 8004a8a: f110 0f00 cmnmi.w r0, #0
  768. 8004a8e: bd01 pop {r0, pc}
  769. 08004a90 <__aeabi_dcmpeq>:
  770. 8004a90: f84d ed08 str.w lr, [sp, #-8]!
  771. 8004a94: f7ff fff4 bl 8004a80 <__aeabi_cdcmpeq>
  772. 8004a98: bf0c ite eq
  773. 8004a9a: 2001 moveq r0, #1
  774. 8004a9c: 2000 movne r0, #0
  775. 8004a9e: f85d fb08 ldr.w pc, [sp], #8
  776. 8004aa2: bf00 nop
  777. 08004aa4 <__aeabi_dcmplt>:
  778. 8004aa4: f84d ed08 str.w lr, [sp, #-8]!
  779. 8004aa8: f7ff ffea bl 8004a80 <__aeabi_cdcmpeq>
  780. 8004aac: bf34 ite cc
  781. 8004aae: 2001 movcc r0, #1
  782. 8004ab0: 2000 movcs r0, #0
  783. 8004ab2: f85d fb08 ldr.w pc, [sp], #8
  784. 8004ab6: bf00 nop
  785. 08004ab8 <__aeabi_dcmple>:
  786. 8004ab8: f84d ed08 str.w lr, [sp, #-8]!
  787. 8004abc: f7ff ffe0 bl 8004a80 <__aeabi_cdcmpeq>
  788. 8004ac0: bf94 ite ls
  789. 8004ac2: 2001 movls r0, #1
  790. 8004ac4: 2000 movhi r0, #0
  791. 8004ac6: f85d fb08 ldr.w pc, [sp], #8
  792. 8004aca: bf00 nop
  793. 08004acc <__aeabi_dcmpge>:
  794. 8004acc: f84d ed08 str.w lr, [sp, #-8]!
  795. 8004ad0: f7ff ffce bl 8004a70 <__aeabi_cdrcmple>
  796. 8004ad4: bf94 ite ls
  797. 8004ad6: 2001 movls r0, #1
  798. 8004ad8: 2000 movhi r0, #0
  799. 8004ada: f85d fb08 ldr.w pc, [sp], #8
  800. 8004ade: bf00 nop
  801. 08004ae0 <__aeabi_dcmpgt>:
  802. 8004ae0: f84d ed08 str.w lr, [sp, #-8]!
  803. 8004ae4: f7ff ffc4 bl 8004a70 <__aeabi_cdrcmple>
  804. 8004ae8: bf34 ite cc
  805. 8004aea: 2001 movcc r0, #1
  806. 8004aec: 2000 movcs r0, #0
  807. 8004aee: f85d fb08 ldr.w pc, [sp], #8
  808. 8004af2: bf00 nop
  809. 08004af4 <__aeabi_dcmpun>:
  810. 8004af4: ea4f 0c41 mov.w ip, r1, lsl #1
  811. 8004af8: ea7f 5c6c mvns.w ip, ip, asr #21
  812. 8004afc: d102 bne.n 8004b04 <__aeabi_dcmpun+0x10>
  813. 8004afe: ea50 3c01 orrs.w ip, r0, r1, lsl #12
  814. 8004b02: d10a bne.n 8004b1a <__aeabi_dcmpun+0x26>
  815. 8004b04: ea4f 0c43 mov.w ip, r3, lsl #1
  816. 8004b08: ea7f 5c6c mvns.w ip, ip, asr #21
  817. 8004b0c: d102 bne.n 8004b14 <__aeabi_dcmpun+0x20>
  818. 8004b0e: ea52 3c03 orrs.w ip, r2, r3, lsl #12
  819. 8004b12: d102 bne.n 8004b1a <__aeabi_dcmpun+0x26>
  820. 8004b14: f04f 0000 mov.w r0, #0
  821. 8004b18: 4770 bx lr
  822. 8004b1a: f04f 0001 mov.w r0, #1
  823. 8004b1e: 4770 bx lr
  824. 08004b20 <__aeabi_d2iz>:
  825. 8004b20: ea4f 0241 mov.w r2, r1, lsl #1
  826. 8004b24: f512 1200 adds.w r2, r2, #2097152 ; 0x200000
  827. 8004b28: d215 bcs.n 8004b56 <__aeabi_d2iz+0x36>
  828. 8004b2a: d511 bpl.n 8004b50 <__aeabi_d2iz+0x30>
  829. 8004b2c: f46f 7378 mvn.w r3, #992 ; 0x3e0
  830. 8004b30: ebb3 5262 subs.w r2, r3, r2, asr #21
  831. 8004b34: d912 bls.n 8004b5c <__aeabi_d2iz+0x3c>
  832. 8004b36: ea4f 23c1 mov.w r3, r1, lsl #11
  833. 8004b3a: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000
  834. 8004b3e: ea43 5350 orr.w r3, r3, r0, lsr #21
  835. 8004b42: f011 4f00 tst.w r1, #2147483648 ; 0x80000000
  836. 8004b46: fa23 f002 lsr.w r0, r3, r2
  837. 8004b4a: bf18 it ne
  838. 8004b4c: 4240 negne r0, r0
  839. 8004b4e: 4770 bx lr
  840. 8004b50: f04f 0000 mov.w r0, #0
  841. 8004b54: 4770 bx lr
  842. 8004b56: ea50 3001 orrs.w r0, r0, r1, lsl #12
  843. 8004b5a: d105 bne.n 8004b68 <__aeabi_d2iz+0x48>
  844. 8004b5c: f011 4000 ands.w r0, r1, #2147483648 ; 0x80000000
  845. 8004b60: bf08 it eq
  846. 8004b62: f06f 4000 mvneq.w r0, #2147483648 ; 0x80000000
  847. 8004b66: 4770 bx lr
  848. 8004b68: f04f 0000 mov.w r0, #0
  849. 8004b6c: 4770 bx lr
  850. 8004b6e: bf00 nop
  851. 08004b70 <__aeabi_d2uiz>:
  852. 8004b70: 004a lsls r2, r1, #1
  853. 8004b72: d211 bcs.n 8004b98 <__aeabi_d2uiz+0x28>
  854. 8004b74: f512 1200 adds.w r2, r2, #2097152 ; 0x200000
  855. 8004b78: d211 bcs.n 8004b9e <__aeabi_d2uiz+0x2e>
  856. 8004b7a: d50d bpl.n 8004b98 <__aeabi_d2uiz+0x28>
  857. 8004b7c: f46f 7378 mvn.w r3, #992 ; 0x3e0
  858. 8004b80: ebb3 5262 subs.w r2, r3, r2, asr #21
  859. 8004b84: d40e bmi.n 8004ba4 <__aeabi_d2uiz+0x34>
  860. 8004b86: ea4f 23c1 mov.w r3, r1, lsl #11
  861. 8004b8a: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000
  862. 8004b8e: ea43 5350 orr.w r3, r3, r0, lsr #21
  863. 8004b92: fa23 f002 lsr.w r0, r3, r2
  864. 8004b96: 4770 bx lr
  865. 8004b98: f04f 0000 mov.w r0, #0
  866. 8004b9c: 4770 bx lr
  867. 8004b9e: ea50 3001 orrs.w r0, r0, r1, lsl #12
  868. 8004ba2: d102 bne.n 8004baa <__aeabi_d2uiz+0x3a>
  869. 8004ba4: f04f 30ff mov.w r0, #4294967295
  870. 8004ba8: 4770 bx lr
  871. 8004baa: f04f 0000 mov.w r0, #0
  872. 8004bae: 4770 bx lr
  873. 08004bb0 <__aeabi_d2f>:
  874. 8004bb0: ea4f 0241 mov.w r2, r1, lsl #1
  875. 8004bb4: f1b2 43e0 subs.w r3, r2, #1879048192 ; 0x70000000
  876. 8004bb8: bf24 itt cs
  877. 8004bba: f5b3 1c00 subscs.w ip, r3, #2097152 ; 0x200000
  878. 8004bbe: f1dc 5cfe rsbscs ip, ip, #532676608 ; 0x1fc00000
  879. 8004bc2: d90d bls.n 8004be0 <__aeabi_d2f+0x30>
  880. 8004bc4: f001 4c00 and.w ip, r1, #2147483648 ; 0x80000000
  881. 8004bc8: ea4f 02c0 mov.w r2, r0, lsl #3
  882. 8004bcc: ea4c 7050 orr.w r0, ip, r0, lsr #29
  883. 8004bd0: f1b2 4f00 cmp.w r2, #2147483648 ; 0x80000000
  884. 8004bd4: eb40 0083 adc.w r0, r0, r3, lsl #2
  885. 8004bd8: bf08 it eq
  886. 8004bda: f020 0001 biceq.w r0, r0, #1
  887. 8004bde: 4770 bx lr
  888. 8004be0: f011 4f80 tst.w r1, #1073741824 ; 0x40000000
  889. 8004be4: d121 bne.n 8004c2a <__aeabi_d2f+0x7a>
  890. 8004be6: f113 7238 adds.w r2, r3, #48234496 ; 0x2e00000
  891. 8004bea: bfbc itt lt
  892. 8004bec: f001 4000 andlt.w r0, r1, #2147483648 ; 0x80000000
  893. 8004bf0: 4770 bxlt lr
  894. 8004bf2: f441 1180 orr.w r1, r1, #1048576 ; 0x100000
  895. 8004bf6: ea4f 5252 mov.w r2, r2, lsr #21
  896. 8004bfa: f1c2 0218 rsb r2, r2, #24
  897. 8004bfe: f1c2 0c20 rsb ip, r2, #32
  898. 8004c02: fa10 f30c lsls.w r3, r0, ip
  899. 8004c06: fa20 f002 lsr.w r0, r0, r2
  900. 8004c0a: bf18 it ne
  901. 8004c0c: f040 0001 orrne.w r0, r0, #1
  902. 8004c10: ea4f 23c1 mov.w r3, r1, lsl #11
  903. 8004c14: ea4f 23d3 mov.w r3, r3, lsr #11
  904. 8004c18: fa03 fc0c lsl.w ip, r3, ip
  905. 8004c1c: ea40 000c orr.w r0, r0, ip
  906. 8004c20: fa23 f302 lsr.w r3, r3, r2
  907. 8004c24: ea4f 0343 mov.w r3, r3, lsl #1
  908. 8004c28: e7cc b.n 8004bc4 <__aeabi_d2f+0x14>
  909. 8004c2a: ea7f 5362 mvns.w r3, r2, asr #21
  910. 8004c2e: d107 bne.n 8004c40 <__aeabi_d2f+0x90>
  911. 8004c30: ea50 3301 orrs.w r3, r0, r1, lsl #12
  912. 8004c34: bf1e ittt ne
  913. 8004c36: f04f 40fe movne.w r0, #2130706432 ; 0x7f000000
  914. 8004c3a: f440 0040 orrne.w r0, r0, #12582912 ; 0xc00000
  915. 8004c3e: 4770 bxne lr
  916. 8004c40: f001 4000 and.w r0, r1, #2147483648 ; 0x80000000
  917. 8004c44: f040 40fe orr.w r0, r0, #2130706432 ; 0x7f000000
  918. 8004c48: f440 0000 orr.w r0, r0, #8388608 ; 0x800000
  919. 8004c4c: 4770 bx lr
  920. 8004c4e: bf00 nop
  921. 08004c50 <__aeabi_frsub>:
  922. 8004c50: f080 4000 eor.w r0, r0, #2147483648 ; 0x80000000
  923. 8004c54: e002 b.n 8004c5c <__addsf3>
  924. 8004c56: bf00 nop
  925. 08004c58 <__aeabi_fsub>:
  926. 8004c58: f081 4100 eor.w r1, r1, #2147483648 ; 0x80000000
  927. 08004c5c <__addsf3>:
  928. 8004c5c: 0042 lsls r2, r0, #1
  929. 8004c5e: bf1f itttt ne
  930. 8004c60: ea5f 0341 movsne.w r3, r1, lsl #1
  931. 8004c64: ea92 0f03 teqne r2, r3
  932. 8004c68: ea7f 6c22 mvnsne.w ip, r2, asr #24
  933. 8004c6c: ea7f 6c23 mvnsne.w ip, r3, asr #24
  934. 8004c70: d06a beq.n 8004d48 <__addsf3+0xec>
  935. 8004c72: ea4f 6212 mov.w r2, r2, lsr #24
  936. 8004c76: ebd2 6313 rsbs r3, r2, r3, lsr #24
  937. 8004c7a: bfc1 itttt gt
  938. 8004c7c: 18d2 addgt r2, r2, r3
  939. 8004c7e: 4041 eorgt r1, r0
  940. 8004c80: 4048 eorgt r0, r1
  941. 8004c82: 4041 eorgt r1, r0
  942. 8004c84: bfb8 it lt
  943. 8004c86: 425b neglt r3, r3
  944. 8004c88: 2b19 cmp r3, #25
  945. 8004c8a: bf88 it hi
  946. 8004c8c: 4770 bxhi lr
  947. 8004c8e: f010 4f00 tst.w r0, #2147483648 ; 0x80000000
  948. 8004c92: f440 0000 orr.w r0, r0, #8388608 ; 0x800000
  949. 8004c96: f020 407f bic.w r0, r0, #4278190080 ; 0xff000000
  950. 8004c9a: bf18 it ne
  951. 8004c9c: 4240 negne r0, r0
  952. 8004c9e: f011 4f00 tst.w r1, #2147483648 ; 0x80000000
  953. 8004ca2: f441 0100 orr.w r1, r1, #8388608 ; 0x800000
  954. 8004ca6: f021 417f bic.w r1, r1, #4278190080 ; 0xff000000
  955. 8004caa: bf18 it ne
  956. 8004cac: 4249 negne r1, r1
  957. 8004cae: ea92 0f03 teq r2, r3
  958. 8004cb2: d03f beq.n 8004d34 <__addsf3+0xd8>
  959. 8004cb4: f1a2 0201 sub.w r2, r2, #1
  960. 8004cb8: fa41 fc03 asr.w ip, r1, r3
  961. 8004cbc: eb10 000c adds.w r0, r0, ip
  962. 8004cc0: f1c3 0320 rsb r3, r3, #32
  963. 8004cc4: fa01 f103 lsl.w r1, r1, r3
  964. 8004cc8: f000 4300 and.w r3, r0, #2147483648 ; 0x80000000
  965. 8004ccc: d502 bpl.n 8004cd4 <__addsf3+0x78>
  966. 8004cce: 4249 negs r1, r1
  967. 8004cd0: eb60 0040 sbc.w r0, r0, r0, lsl #1
  968. 8004cd4: f5b0 0f00 cmp.w r0, #8388608 ; 0x800000
  969. 8004cd8: d313 bcc.n 8004d02 <__addsf3+0xa6>
  970. 8004cda: f1b0 7f80 cmp.w r0, #16777216 ; 0x1000000
  971. 8004cde: d306 bcc.n 8004cee <__addsf3+0x92>
  972. 8004ce0: 0840 lsrs r0, r0, #1
  973. 8004ce2: ea4f 0131 mov.w r1, r1, rrx
  974. 8004ce6: f102 0201 add.w r2, r2, #1
  975. 8004cea: 2afe cmp r2, #254 ; 0xfe
  976. 8004cec: d251 bcs.n 8004d92 <__addsf3+0x136>
  977. 8004cee: f1b1 4f00 cmp.w r1, #2147483648 ; 0x80000000
  978. 8004cf2: eb40 50c2 adc.w r0, r0, r2, lsl #23
  979. 8004cf6: bf08 it eq
  980. 8004cf8: f020 0001 biceq.w r0, r0, #1
  981. 8004cfc: ea40 0003 orr.w r0, r0, r3
  982. 8004d00: 4770 bx lr
  983. 8004d02: 0049 lsls r1, r1, #1
  984. 8004d04: eb40 0000 adc.w r0, r0, r0
  985. 8004d08: f410 0f00 tst.w r0, #8388608 ; 0x800000
  986. 8004d0c: f1a2 0201 sub.w r2, r2, #1
  987. 8004d10: d1ed bne.n 8004cee <__addsf3+0x92>
  988. 8004d12: fab0 fc80 clz ip, r0
  989. 8004d16: f1ac 0c08 sub.w ip, ip, #8
  990. 8004d1a: ebb2 020c subs.w r2, r2, ip
  991. 8004d1e: fa00 f00c lsl.w r0, r0, ip
  992. 8004d22: bfaa itet ge
  993. 8004d24: eb00 50c2 addge.w r0, r0, r2, lsl #23
  994. 8004d28: 4252 neglt r2, r2
  995. 8004d2a: 4318 orrge r0, r3
  996. 8004d2c: bfbc itt lt
  997. 8004d2e: 40d0 lsrlt r0, r2
  998. 8004d30: 4318 orrlt r0, r3
  999. 8004d32: 4770 bx lr
  1000. 8004d34: f092 0f00 teq r2, #0
  1001. 8004d38: f481 0100 eor.w r1, r1, #8388608 ; 0x800000
  1002. 8004d3c: bf06 itte eq
  1003. 8004d3e: f480 0000 eoreq.w r0, r0, #8388608 ; 0x800000
  1004. 8004d42: 3201 addeq r2, #1
  1005. 8004d44: 3b01 subne r3, #1
  1006. 8004d46: e7b5 b.n 8004cb4 <__addsf3+0x58>
  1007. 8004d48: ea4f 0341 mov.w r3, r1, lsl #1
  1008. 8004d4c: ea7f 6c22 mvns.w ip, r2, asr #24
  1009. 8004d50: bf18 it ne
  1010. 8004d52: ea7f 6c23 mvnsne.w ip, r3, asr #24
  1011. 8004d56: d021 beq.n 8004d9c <__addsf3+0x140>
  1012. 8004d58: ea92 0f03 teq r2, r3
  1013. 8004d5c: d004 beq.n 8004d68 <__addsf3+0x10c>
  1014. 8004d5e: f092 0f00 teq r2, #0
  1015. 8004d62: bf08 it eq
  1016. 8004d64: 4608 moveq r0, r1
  1017. 8004d66: 4770 bx lr
  1018. 8004d68: ea90 0f01 teq r0, r1
  1019. 8004d6c: bf1c itt ne
  1020. 8004d6e: 2000 movne r0, #0
  1021. 8004d70: 4770 bxne lr
  1022. 8004d72: f012 4f7f tst.w r2, #4278190080 ; 0xff000000
  1023. 8004d76: d104 bne.n 8004d82 <__addsf3+0x126>
  1024. 8004d78: 0040 lsls r0, r0, #1
  1025. 8004d7a: bf28 it cs
  1026. 8004d7c: f040 4000 orrcs.w r0, r0, #2147483648 ; 0x80000000
  1027. 8004d80: 4770 bx lr
  1028. 8004d82: f112 7200 adds.w r2, r2, #33554432 ; 0x2000000
  1029. 8004d86: bf3c itt cc
  1030. 8004d88: f500 0000 addcc.w r0, r0, #8388608 ; 0x800000
  1031. 8004d8c: 4770 bxcc lr
  1032. 8004d8e: f000 4300 and.w r3, r0, #2147483648 ; 0x80000000
  1033. 8004d92: f043 40fe orr.w r0, r3, #2130706432 ; 0x7f000000
  1034. 8004d96: f440 0000 orr.w r0, r0, #8388608 ; 0x800000
  1035. 8004d9a: 4770 bx lr
  1036. 8004d9c: ea7f 6222 mvns.w r2, r2, asr #24
  1037. 8004da0: bf16 itet ne
  1038. 8004da2: 4608 movne r0, r1
  1039. 8004da4: ea7f 6323 mvnseq.w r3, r3, asr #24
  1040. 8004da8: 4601 movne r1, r0
  1041. 8004daa: 0242 lsls r2, r0, #9
  1042. 8004dac: bf06 itte eq
  1043. 8004dae: ea5f 2341 movseq.w r3, r1, lsl #9
  1044. 8004db2: ea90 0f01 teqeq r0, r1
  1045. 8004db6: f440 0080 orrne.w r0, r0, #4194304 ; 0x400000
  1046. 8004dba: 4770 bx lr
  1047. 08004dbc <__aeabi_ui2f>:
  1048. 8004dbc: f04f 0300 mov.w r3, #0
  1049. 8004dc0: e004 b.n 8004dcc <__aeabi_i2f+0x8>
  1050. 8004dc2: bf00 nop
  1051. 08004dc4 <__aeabi_i2f>:
  1052. 8004dc4: f010 4300 ands.w r3, r0, #2147483648 ; 0x80000000
  1053. 8004dc8: bf48 it mi
  1054. 8004dca: 4240 negmi r0, r0
  1055. 8004dcc: ea5f 0c00 movs.w ip, r0
  1056. 8004dd0: bf08 it eq
  1057. 8004dd2: 4770 bxeq lr
  1058. 8004dd4: f043 4396 orr.w r3, r3, #1258291200 ; 0x4b000000
  1059. 8004dd8: 4601 mov r1, r0
  1060. 8004dda: f04f 0000 mov.w r0, #0
  1061. 8004dde: e01c b.n 8004e1a <__aeabi_l2f+0x2a>
  1062. 08004de0 <__aeabi_ul2f>:
  1063. 8004de0: ea50 0201 orrs.w r2, r0, r1
  1064. 8004de4: bf08 it eq
  1065. 8004de6: 4770 bxeq lr
  1066. 8004de8: f04f 0300 mov.w r3, #0
  1067. 8004dec: e00a b.n 8004e04 <__aeabi_l2f+0x14>
  1068. 8004dee: bf00 nop
  1069. 08004df0 <__aeabi_l2f>:
  1070. 8004df0: ea50 0201 orrs.w r2, r0, r1
  1071. 8004df4: bf08 it eq
  1072. 8004df6: 4770 bxeq lr
  1073. 8004df8: f011 4300 ands.w r3, r1, #2147483648 ; 0x80000000
  1074. 8004dfc: d502 bpl.n 8004e04 <__aeabi_l2f+0x14>
  1075. 8004dfe: 4240 negs r0, r0
  1076. 8004e00: eb61 0141 sbc.w r1, r1, r1, lsl #1
  1077. 8004e04: ea5f 0c01 movs.w ip, r1
  1078. 8004e08: bf02 ittt eq
  1079. 8004e0a: 4684 moveq ip, r0
  1080. 8004e0c: 4601 moveq r1, r0
  1081. 8004e0e: 2000 moveq r0, #0
  1082. 8004e10: f043 43b6 orr.w r3, r3, #1526726656 ; 0x5b000000
  1083. 8004e14: bf08 it eq
  1084. 8004e16: f1a3 5380 subeq.w r3, r3, #268435456 ; 0x10000000
  1085. 8004e1a: f5a3 0300 sub.w r3, r3, #8388608 ; 0x800000
  1086. 8004e1e: fabc f28c clz r2, ip
  1087. 8004e22: 3a08 subs r2, #8
  1088. 8004e24: eba3 53c2 sub.w r3, r3, r2, lsl #23
  1089. 8004e28: db10 blt.n 8004e4c <__aeabi_l2f+0x5c>
  1090. 8004e2a: fa01 fc02 lsl.w ip, r1, r2
  1091. 8004e2e: 4463 add r3, ip
  1092. 8004e30: fa00 fc02 lsl.w ip, r0, r2
  1093. 8004e34: f1c2 0220 rsb r2, r2, #32
  1094. 8004e38: f1bc 4f00 cmp.w ip, #2147483648 ; 0x80000000
  1095. 8004e3c: fa20 f202 lsr.w r2, r0, r2
  1096. 8004e40: eb43 0002 adc.w r0, r3, r2
  1097. 8004e44: bf08 it eq
  1098. 8004e46: f020 0001 biceq.w r0, r0, #1
  1099. 8004e4a: 4770 bx lr
  1100. 8004e4c: f102 0220 add.w r2, r2, #32
  1101. 8004e50: fa01 fc02 lsl.w ip, r1, r2
  1102. 8004e54: f1c2 0220 rsb r2, r2, #32
  1103. 8004e58: ea50 004c orrs.w r0, r0, ip, lsl #1
  1104. 8004e5c: fa21 f202 lsr.w r2, r1, r2
  1105. 8004e60: eb43 0002 adc.w r0, r3, r2
  1106. 8004e64: bf08 it eq
  1107. 8004e66: ea20 70dc biceq.w r0, r0, ip, lsr #31
  1108. 8004e6a: 4770 bx lr
  1109. 08004e6c <__aeabi_fmul>:
  1110. 8004e6c: f04f 0cff mov.w ip, #255 ; 0xff
  1111. 8004e70: ea1c 52d0 ands.w r2, ip, r0, lsr #23
  1112. 8004e74: bf1e ittt ne
  1113. 8004e76: ea1c 53d1 andsne.w r3, ip, r1, lsr #23
  1114. 8004e7a: ea92 0f0c teqne r2, ip
  1115. 8004e7e: ea93 0f0c teqne r3, ip
  1116. 8004e82: d06f beq.n 8004f64 <__aeabi_fmul+0xf8>
  1117. 8004e84: 441a add r2, r3
  1118. 8004e86: ea80 0c01 eor.w ip, r0, r1
  1119. 8004e8a: 0240 lsls r0, r0, #9
  1120. 8004e8c: bf18 it ne
  1121. 8004e8e: ea5f 2141 movsne.w r1, r1, lsl #9
  1122. 8004e92: d01e beq.n 8004ed2 <__aeabi_fmul+0x66>
  1123. 8004e94: f04f 6300 mov.w r3, #134217728 ; 0x8000000
  1124. 8004e98: ea43 1050 orr.w r0, r3, r0, lsr #5
  1125. 8004e9c: ea43 1151 orr.w r1, r3, r1, lsr #5
  1126. 8004ea0: fba0 3101 umull r3, r1, r0, r1
  1127. 8004ea4: f00c 4000 and.w r0, ip, #2147483648 ; 0x80000000
  1128. 8004ea8: f5b1 0f00 cmp.w r1, #8388608 ; 0x800000
  1129. 8004eac: bf3e ittt cc
  1130. 8004eae: 0049 lslcc r1, r1, #1
  1131. 8004eb0: ea41 71d3 orrcc.w r1, r1, r3, lsr #31
  1132. 8004eb4: 005b lslcc r3, r3, #1
  1133. 8004eb6: ea40 0001 orr.w r0, r0, r1
  1134. 8004eba: f162 027f sbc.w r2, r2, #127 ; 0x7f
  1135. 8004ebe: 2afd cmp r2, #253 ; 0xfd
  1136. 8004ec0: d81d bhi.n 8004efe <__aeabi_fmul+0x92>
  1137. 8004ec2: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000
  1138. 8004ec6: eb40 50c2 adc.w r0, r0, r2, lsl #23
  1139. 8004eca: bf08 it eq
  1140. 8004ecc: f020 0001 biceq.w r0, r0, #1
  1141. 8004ed0: 4770 bx lr
  1142. 8004ed2: f090 0f00 teq r0, #0
  1143. 8004ed6: f00c 4c00 and.w ip, ip, #2147483648 ; 0x80000000
  1144. 8004eda: bf08 it eq
  1145. 8004edc: 0249 lsleq r1, r1, #9
  1146. 8004ede: ea4c 2050 orr.w r0, ip, r0, lsr #9
  1147. 8004ee2: ea40 2051 orr.w r0, r0, r1, lsr #9
  1148. 8004ee6: 3a7f subs r2, #127 ; 0x7f
  1149. 8004ee8: bfc2 ittt gt
  1150. 8004eea: f1d2 03ff rsbsgt r3, r2, #255 ; 0xff
  1151. 8004eee: ea40 50c2 orrgt.w r0, r0, r2, lsl #23
  1152. 8004ef2: 4770 bxgt lr
  1153. 8004ef4: f440 0000 orr.w r0, r0, #8388608 ; 0x800000
  1154. 8004ef8: f04f 0300 mov.w r3, #0
  1155. 8004efc: 3a01 subs r2, #1
  1156. 8004efe: dc5d bgt.n 8004fbc <__aeabi_fmul+0x150>
  1157. 8004f00: f112 0f19 cmn.w r2, #25
  1158. 8004f04: bfdc itt le
  1159. 8004f06: f000 4000 andle.w r0, r0, #2147483648 ; 0x80000000
  1160. 8004f0a: 4770 bxle lr
  1161. 8004f0c: f1c2 0200 rsb r2, r2, #0
  1162. 8004f10: 0041 lsls r1, r0, #1
  1163. 8004f12: fa21 f102 lsr.w r1, r1, r2
  1164. 8004f16: f1c2 0220 rsb r2, r2, #32
  1165. 8004f1a: fa00 fc02 lsl.w ip, r0, r2
  1166. 8004f1e: ea5f 0031 movs.w r0, r1, rrx
  1167. 8004f22: f140 0000 adc.w r0, r0, #0
  1168. 8004f26: ea53 034c orrs.w r3, r3, ip, lsl #1
  1169. 8004f2a: bf08 it eq
  1170. 8004f2c: ea20 70dc biceq.w r0, r0, ip, lsr #31
  1171. 8004f30: 4770 bx lr
  1172. 8004f32: f092 0f00 teq r2, #0
  1173. 8004f36: f000 4c00 and.w ip, r0, #2147483648 ; 0x80000000
  1174. 8004f3a: bf02 ittt eq
  1175. 8004f3c: 0040 lsleq r0, r0, #1
  1176. 8004f3e: f410 0f00 tsteq.w r0, #8388608 ; 0x800000
  1177. 8004f42: 3a01 subeq r2, #1
  1178. 8004f44: d0f9 beq.n 8004f3a <__aeabi_fmul+0xce>
  1179. 8004f46: ea40 000c orr.w r0, r0, ip
  1180. 8004f4a: f093 0f00 teq r3, #0
  1181. 8004f4e: f001 4c00 and.w ip, r1, #2147483648 ; 0x80000000
  1182. 8004f52: bf02 ittt eq
  1183. 8004f54: 0049 lsleq r1, r1, #1
  1184. 8004f56: f411 0f00 tsteq.w r1, #8388608 ; 0x800000
  1185. 8004f5a: 3b01 subeq r3, #1
  1186. 8004f5c: d0f9 beq.n 8004f52 <__aeabi_fmul+0xe6>
  1187. 8004f5e: ea41 010c orr.w r1, r1, ip
  1188. 8004f62: e78f b.n 8004e84 <__aeabi_fmul+0x18>
  1189. 8004f64: ea0c 53d1 and.w r3, ip, r1, lsr #23
  1190. 8004f68: ea92 0f0c teq r2, ip
  1191. 8004f6c: bf18 it ne
  1192. 8004f6e: ea93 0f0c teqne r3, ip
  1193. 8004f72: d00a beq.n 8004f8a <__aeabi_fmul+0x11e>
  1194. 8004f74: f030 4c00 bics.w ip, r0, #2147483648 ; 0x80000000
  1195. 8004f78: bf18 it ne
  1196. 8004f7a: f031 4c00 bicsne.w ip, r1, #2147483648 ; 0x80000000
  1197. 8004f7e: d1d8 bne.n 8004f32 <__aeabi_fmul+0xc6>
  1198. 8004f80: ea80 0001 eor.w r0, r0, r1
  1199. 8004f84: f000 4000 and.w r0, r0, #2147483648 ; 0x80000000
  1200. 8004f88: 4770 bx lr
  1201. 8004f8a: f090 0f00 teq r0, #0
  1202. 8004f8e: bf17 itett ne
  1203. 8004f90: f090 4f00 teqne r0, #2147483648 ; 0x80000000
  1204. 8004f94: 4608 moveq r0, r1
  1205. 8004f96: f091 0f00 teqne r1, #0
  1206. 8004f9a: f091 4f00 teqne r1, #2147483648 ; 0x80000000
  1207. 8004f9e: d014 beq.n 8004fca <__aeabi_fmul+0x15e>
  1208. 8004fa0: ea92 0f0c teq r2, ip
  1209. 8004fa4: d101 bne.n 8004faa <__aeabi_fmul+0x13e>
  1210. 8004fa6: 0242 lsls r2, r0, #9
  1211. 8004fa8: d10f bne.n 8004fca <__aeabi_fmul+0x15e>
  1212. 8004faa: ea93 0f0c teq r3, ip
  1213. 8004fae: d103 bne.n 8004fb8 <__aeabi_fmul+0x14c>
  1214. 8004fb0: 024b lsls r3, r1, #9
  1215. 8004fb2: bf18 it ne
  1216. 8004fb4: 4608 movne r0, r1
  1217. 8004fb6: d108 bne.n 8004fca <__aeabi_fmul+0x15e>
  1218. 8004fb8: ea80 0001 eor.w r0, r0, r1
  1219. 8004fbc: f000 4000 and.w r0, r0, #2147483648 ; 0x80000000
  1220. 8004fc0: f040 40fe orr.w r0, r0, #2130706432 ; 0x7f000000
  1221. 8004fc4: f440 0000 orr.w r0, r0, #8388608 ; 0x800000
  1222. 8004fc8: 4770 bx lr
  1223. 8004fca: f040 40fe orr.w r0, r0, #2130706432 ; 0x7f000000
  1224. 8004fce: f440 0040 orr.w r0, r0, #12582912 ; 0xc00000
  1225. 8004fd2: 4770 bx lr
  1226. 08004fd4 <__aeabi_fdiv>:
  1227. 8004fd4: f04f 0cff mov.w ip, #255 ; 0xff
  1228. 8004fd8: ea1c 52d0 ands.w r2, ip, r0, lsr #23
  1229. 8004fdc: bf1e ittt ne
  1230. 8004fde: ea1c 53d1 andsne.w r3, ip, r1, lsr #23
  1231. 8004fe2: ea92 0f0c teqne r2, ip
  1232. 8004fe6: ea93 0f0c teqne r3, ip
  1233. 8004fea: d069 beq.n 80050c0 <__aeabi_fdiv+0xec>
  1234. 8004fec: eba2 0203 sub.w r2, r2, r3
  1235. 8004ff0: ea80 0c01 eor.w ip, r0, r1
  1236. 8004ff4: 0249 lsls r1, r1, #9
  1237. 8004ff6: ea4f 2040 mov.w r0, r0, lsl #9
  1238. 8004ffa: d037 beq.n 800506c <__aeabi_fdiv+0x98>
  1239. 8004ffc: f04f 5380 mov.w r3, #268435456 ; 0x10000000
  1240. 8005000: ea43 1111 orr.w r1, r3, r1, lsr #4
  1241. 8005004: ea43 1310 orr.w r3, r3, r0, lsr #4
  1242. 8005008: f00c 4000 and.w r0, ip, #2147483648 ; 0x80000000
  1243. 800500c: 428b cmp r3, r1
  1244. 800500e: bf38 it cc
  1245. 8005010: 005b lslcc r3, r3, #1
  1246. 8005012: f142 027d adc.w r2, r2, #125 ; 0x7d
  1247. 8005016: f44f 0c00 mov.w ip, #8388608 ; 0x800000
  1248. 800501a: 428b cmp r3, r1
  1249. 800501c: bf24 itt cs
  1250. 800501e: 1a5b subcs r3, r3, r1
  1251. 8005020: ea40 000c orrcs.w r0, r0, ip
  1252. 8005024: ebb3 0f51 cmp.w r3, r1, lsr #1
  1253. 8005028: bf24 itt cs
  1254. 800502a: eba3 0351 subcs.w r3, r3, r1, lsr #1
  1255. 800502e: ea40 005c orrcs.w r0, r0, ip, lsr #1
  1256. 8005032: ebb3 0f91 cmp.w r3, r1, lsr #2
  1257. 8005036: bf24 itt cs
  1258. 8005038: eba3 0391 subcs.w r3, r3, r1, lsr #2
  1259. 800503c: ea40 009c orrcs.w r0, r0, ip, lsr #2
  1260. 8005040: ebb3 0fd1 cmp.w r3, r1, lsr #3
  1261. 8005044: bf24 itt cs
  1262. 8005046: eba3 03d1 subcs.w r3, r3, r1, lsr #3
  1263. 800504a: ea40 00dc orrcs.w r0, r0, ip, lsr #3
  1264. 800504e: 011b lsls r3, r3, #4
  1265. 8005050: bf18 it ne
  1266. 8005052: ea5f 1c1c movsne.w ip, ip, lsr #4
  1267. 8005056: d1e0 bne.n 800501a <__aeabi_fdiv+0x46>
  1268. 8005058: 2afd cmp r2, #253 ; 0xfd
  1269. 800505a: f63f af50 bhi.w 8004efe <__aeabi_fmul+0x92>
  1270. 800505e: 428b cmp r3, r1
  1271. 8005060: eb40 50c2 adc.w r0, r0, r2, lsl #23
  1272. 8005064: bf08 it eq
  1273. 8005066: f020 0001 biceq.w r0, r0, #1
  1274. 800506a: 4770 bx lr
  1275. 800506c: f00c 4c00 and.w ip, ip, #2147483648 ; 0x80000000
  1276. 8005070: ea4c 2050 orr.w r0, ip, r0, lsr #9
  1277. 8005074: 327f adds r2, #127 ; 0x7f
  1278. 8005076: bfc2 ittt gt
  1279. 8005078: f1d2 03ff rsbsgt r3, r2, #255 ; 0xff
  1280. 800507c: ea40 50c2 orrgt.w r0, r0, r2, lsl #23
  1281. 8005080: 4770 bxgt lr
  1282. 8005082: f440 0000 orr.w r0, r0, #8388608 ; 0x800000
  1283. 8005086: f04f 0300 mov.w r3, #0
  1284. 800508a: 3a01 subs r2, #1
  1285. 800508c: e737 b.n 8004efe <__aeabi_fmul+0x92>
  1286. 800508e: f092 0f00 teq r2, #0
  1287. 8005092: f000 4c00 and.w ip, r0, #2147483648 ; 0x80000000
  1288. 8005096: bf02 ittt eq
  1289. 8005098: 0040 lsleq r0, r0, #1
  1290. 800509a: f410 0f00 tsteq.w r0, #8388608 ; 0x800000
  1291. 800509e: 3a01 subeq r2, #1
  1292. 80050a0: d0f9 beq.n 8005096 <__aeabi_fdiv+0xc2>
  1293. 80050a2: ea40 000c orr.w r0, r0, ip
  1294. 80050a6: f093 0f00 teq r3, #0
  1295. 80050aa: f001 4c00 and.w ip, r1, #2147483648 ; 0x80000000
  1296. 80050ae: bf02 ittt eq
  1297. 80050b0: 0049 lsleq r1, r1, #1
  1298. 80050b2: f411 0f00 tsteq.w r1, #8388608 ; 0x800000
  1299. 80050b6: 3b01 subeq r3, #1
  1300. 80050b8: d0f9 beq.n 80050ae <__aeabi_fdiv+0xda>
  1301. 80050ba: ea41 010c orr.w r1, r1, ip
  1302. 80050be: e795 b.n 8004fec <__aeabi_fdiv+0x18>
  1303. 80050c0: ea0c 53d1 and.w r3, ip, r1, lsr #23
  1304. 80050c4: ea92 0f0c teq r2, ip
  1305. 80050c8: d108 bne.n 80050dc <__aeabi_fdiv+0x108>
  1306. 80050ca: 0242 lsls r2, r0, #9
  1307. 80050cc: f47f af7d bne.w 8004fca <__aeabi_fmul+0x15e>
  1308. 80050d0: ea93 0f0c teq r3, ip
  1309. 80050d4: f47f af70 bne.w 8004fb8 <__aeabi_fmul+0x14c>
  1310. 80050d8: 4608 mov r0, r1
  1311. 80050da: e776 b.n 8004fca <__aeabi_fmul+0x15e>
  1312. 80050dc: ea93 0f0c teq r3, ip
  1313. 80050e0: d104 bne.n 80050ec <__aeabi_fdiv+0x118>
  1314. 80050e2: 024b lsls r3, r1, #9
  1315. 80050e4: f43f af4c beq.w 8004f80 <__aeabi_fmul+0x114>
  1316. 80050e8: 4608 mov r0, r1
  1317. 80050ea: e76e b.n 8004fca <__aeabi_fmul+0x15e>
  1318. 80050ec: f030 4c00 bics.w ip, r0, #2147483648 ; 0x80000000
  1319. 80050f0: bf18 it ne
  1320. 80050f2: f031 4c00 bicsne.w ip, r1, #2147483648 ; 0x80000000
  1321. 80050f6: d1ca bne.n 800508e <__aeabi_fdiv+0xba>
  1322. 80050f8: f030 4200 bics.w r2, r0, #2147483648 ; 0x80000000
  1323. 80050fc: f47f af5c bne.w 8004fb8 <__aeabi_fmul+0x14c>
  1324. 8005100: f031 4300 bics.w r3, r1, #2147483648 ; 0x80000000
  1325. 8005104: f47f af3c bne.w 8004f80 <__aeabi_fmul+0x114>
  1326. 8005108: e75f b.n 8004fca <__aeabi_fmul+0x15e>
  1327. 800510a: bf00 nop
  1328. 0800510c <__aeabi_f2uiz>:
  1329. 800510c: 0042 lsls r2, r0, #1
  1330. 800510e: d20e bcs.n 800512e <__aeabi_f2uiz+0x22>
  1331. 8005110: f1b2 4ffe cmp.w r2, #2130706432 ; 0x7f000000
  1332. 8005114: d30b bcc.n 800512e <__aeabi_f2uiz+0x22>
  1333. 8005116: f04f 039e mov.w r3, #158 ; 0x9e
  1334. 800511a: ebb3 6212 subs.w r2, r3, r2, lsr #24
  1335. 800511e: d409 bmi.n 8005134 <__aeabi_f2uiz+0x28>
  1336. 8005120: ea4f 2300 mov.w r3, r0, lsl #8
  1337. 8005124: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000
  1338. 8005128: fa23 f002 lsr.w r0, r3, r2
  1339. 800512c: 4770 bx lr
  1340. 800512e: f04f 0000 mov.w r0, #0
  1341. 8005132: 4770 bx lr
  1342. 8005134: f112 0f61 cmn.w r2, #97 ; 0x61
  1343. 8005138: d101 bne.n 800513e <__aeabi_f2uiz+0x32>
  1344. 800513a: 0242 lsls r2, r0, #9
  1345. 800513c: d102 bne.n 8005144 <__aeabi_f2uiz+0x38>
  1346. 800513e: f04f 30ff mov.w r0, #4294967295
  1347. 8005142: 4770 bx lr
  1348. 8005144: f04f 0000 mov.w r0, #0
  1349. 8005148: 4770 bx lr
  1350. 800514a: bf00 nop
  1351. 0800514c <__aeabi_uldivmod>:
  1352. 800514c: b953 cbnz r3, 8005164 <__aeabi_uldivmod+0x18>
  1353. 800514e: b94a cbnz r2, 8005164 <__aeabi_uldivmod+0x18>
  1354. 8005150: 2900 cmp r1, #0
  1355. 8005152: bf08 it eq
  1356. 8005154: 2800 cmpeq r0, #0
  1357. 8005156: bf1c itt ne
  1358. 8005158: f04f 31ff movne.w r1, #4294967295
  1359. 800515c: f04f 30ff movne.w r0, #4294967295
  1360. 8005160: f000 b97a b.w 8005458 <__aeabi_idiv0>
  1361. 8005164: f1ad 0c08 sub.w ip, sp, #8
  1362. 8005168: e96d ce04 strd ip, lr, [sp, #-16]!
  1363. 800516c: f000 f806 bl 800517c <__udivmoddi4>
  1364. 8005170: f8dd e004 ldr.w lr, [sp, #4]
  1365. 8005174: e9dd 2302 ldrd r2, r3, [sp, #8]
  1366. 8005178: b004 add sp, #16
  1367. 800517a: 4770 bx lr
  1368. 0800517c <__udivmoddi4>:
  1369. 800517c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
  1370. 8005180: 468c mov ip, r1
  1371. 8005182: 460e mov r6, r1
  1372. 8005184: 4604 mov r4, r0
  1373. 8005186: 9d08 ldr r5, [sp, #32]
  1374. 8005188: 2b00 cmp r3, #0
  1375. 800518a: d150 bne.n 800522e <__udivmoddi4+0xb2>
  1376. 800518c: 428a cmp r2, r1
  1377. 800518e: 4617 mov r7, r2
  1378. 8005190: d96c bls.n 800526c <__udivmoddi4+0xf0>
  1379. 8005192: fab2 fe82 clz lr, r2
  1380. 8005196: f1be 0f00 cmp.w lr, #0
  1381. 800519a: d00b beq.n 80051b4 <__udivmoddi4+0x38>
  1382. 800519c: f1ce 0c20 rsb ip, lr, #32
  1383. 80051a0: fa01 f60e lsl.w r6, r1, lr
  1384. 80051a4: fa20 fc0c lsr.w ip, r0, ip
  1385. 80051a8: fa02 f70e lsl.w r7, r2, lr
  1386. 80051ac: ea4c 0c06 orr.w ip, ip, r6
  1387. 80051b0: fa00 f40e lsl.w r4, r0, lr
  1388. 80051b4: 0c3a lsrs r2, r7, #16
  1389. 80051b6: fbbc f9f2 udiv r9, ip, r2
  1390. 80051ba: b2bb uxth r3, r7
  1391. 80051bc: fb02 cc19 mls ip, r2, r9, ip
  1392. 80051c0: fb09 fa03 mul.w sl, r9, r3
  1393. 80051c4: ea4f 4814 mov.w r8, r4, lsr #16
  1394. 80051c8: ea48 460c orr.w r6, r8, ip, lsl #16
  1395. 80051cc: 45b2 cmp sl, r6
  1396. 80051ce: d90a bls.n 80051e6 <__udivmoddi4+0x6a>
  1397. 80051d0: 19f6 adds r6, r6, r7
  1398. 80051d2: f109 31ff add.w r1, r9, #4294967295
  1399. 80051d6: f080 8125 bcs.w 8005424 <__udivmoddi4+0x2a8>
  1400. 80051da: 45b2 cmp sl, r6
  1401. 80051dc: f240 8122 bls.w 8005424 <__udivmoddi4+0x2a8>
  1402. 80051e0: f1a9 0902 sub.w r9, r9, #2
  1403. 80051e4: 443e add r6, r7
  1404. 80051e6: eba6 060a sub.w r6, r6, sl
  1405. 80051ea: fbb6 f0f2 udiv r0, r6, r2
  1406. 80051ee: fb02 6610 mls r6, r2, r0, r6
  1407. 80051f2: fb00 f303 mul.w r3, r0, r3
  1408. 80051f6: b2a4 uxth r4, r4
  1409. 80051f8: ea44 4406 orr.w r4, r4, r6, lsl #16
  1410. 80051fc: 42a3 cmp r3, r4
  1411. 80051fe: d909 bls.n 8005214 <__udivmoddi4+0x98>
  1412. 8005200: 19e4 adds r4, r4, r7
  1413. 8005202: f100 32ff add.w r2, r0, #4294967295
  1414. 8005206: f080 810b bcs.w 8005420 <__udivmoddi4+0x2a4>
  1415. 800520a: 42a3 cmp r3, r4
  1416. 800520c: f240 8108 bls.w 8005420 <__udivmoddi4+0x2a4>
  1417. 8005210: 3802 subs r0, #2
  1418. 8005212: 443c add r4, r7
  1419. 8005214: 2100 movs r1, #0
  1420. 8005216: 1ae4 subs r4, r4, r3
  1421. 8005218: ea40 4009 orr.w r0, r0, r9, lsl #16
  1422. 800521c: 2d00 cmp r5, #0
  1423. 800521e: d062 beq.n 80052e6 <__udivmoddi4+0x16a>
  1424. 8005220: 2300 movs r3, #0
  1425. 8005222: fa24 f40e lsr.w r4, r4, lr
  1426. 8005226: 602c str r4, [r5, #0]
  1427. 8005228: 606b str r3, [r5, #4]
  1428. 800522a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
  1429. 800522e: 428b cmp r3, r1
  1430. 8005230: d907 bls.n 8005242 <__udivmoddi4+0xc6>
  1431. 8005232: 2d00 cmp r5, #0
  1432. 8005234: d055 beq.n 80052e2 <__udivmoddi4+0x166>
  1433. 8005236: 2100 movs r1, #0
  1434. 8005238: e885 0041 stmia.w r5, {r0, r6}
  1435. 800523c: 4608 mov r0, r1
  1436. 800523e: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
  1437. 8005242: fab3 f183 clz r1, r3
  1438. 8005246: 2900 cmp r1, #0
  1439. 8005248: f040 808f bne.w 800536a <__udivmoddi4+0x1ee>
  1440. 800524c: 42b3 cmp r3, r6
  1441. 800524e: d302 bcc.n 8005256 <__udivmoddi4+0xda>
  1442. 8005250: 4282 cmp r2, r0
  1443. 8005252: f200 80fc bhi.w 800544e <__udivmoddi4+0x2d2>
  1444. 8005256: 1a84 subs r4, r0, r2
  1445. 8005258: eb66 0603 sbc.w r6, r6, r3
  1446. 800525c: 2001 movs r0, #1
  1447. 800525e: 46b4 mov ip, r6
  1448. 8005260: 2d00 cmp r5, #0
  1449. 8005262: d040 beq.n 80052e6 <__udivmoddi4+0x16a>
  1450. 8005264: e885 1010 stmia.w r5, {r4, ip}
  1451. 8005268: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
  1452. 800526c: b912 cbnz r2, 8005274 <__udivmoddi4+0xf8>
  1453. 800526e: 2701 movs r7, #1
  1454. 8005270: fbb7 f7f2 udiv r7, r7, r2
  1455. 8005274: fab7 fe87 clz lr, r7
  1456. 8005278: f1be 0f00 cmp.w lr, #0
  1457. 800527c: d135 bne.n 80052ea <__udivmoddi4+0x16e>
  1458. 800527e: 2101 movs r1, #1
  1459. 8005280: 1bf6 subs r6, r6, r7
  1460. 8005282: ea4f 4c17 mov.w ip, r7, lsr #16
  1461. 8005286: fa1f f887 uxth.w r8, r7
  1462. 800528a: fbb6 f2fc udiv r2, r6, ip
  1463. 800528e: fb0c 6612 mls r6, ip, r2, r6
  1464. 8005292: fb08 f002 mul.w r0, r8, r2
  1465. 8005296: 0c23 lsrs r3, r4, #16
  1466. 8005298: ea43 4606 orr.w r6, r3, r6, lsl #16
  1467. 800529c: 42b0 cmp r0, r6
  1468. 800529e: d907 bls.n 80052b0 <__udivmoddi4+0x134>
  1469. 80052a0: 19f6 adds r6, r6, r7
  1470. 80052a2: f102 33ff add.w r3, r2, #4294967295
  1471. 80052a6: d202 bcs.n 80052ae <__udivmoddi4+0x132>
  1472. 80052a8: 42b0 cmp r0, r6
  1473. 80052aa: f200 80d2 bhi.w 8005452 <__udivmoddi4+0x2d6>
  1474. 80052ae: 461a mov r2, r3
  1475. 80052b0: 1a36 subs r6, r6, r0
  1476. 80052b2: fbb6 f0fc udiv r0, r6, ip
  1477. 80052b6: fb0c 6610 mls r6, ip, r0, r6
  1478. 80052ba: fb08 f800 mul.w r8, r8, r0
  1479. 80052be: b2a3 uxth r3, r4
  1480. 80052c0: ea43 4406 orr.w r4, r3, r6, lsl #16
  1481. 80052c4: 45a0 cmp r8, r4
  1482. 80052c6: d907 bls.n 80052d8 <__udivmoddi4+0x15c>
  1483. 80052c8: 19e4 adds r4, r4, r7
  1484. 80052ca: f100 33ff add.w r3, r0, #4294967295
  1485. 80052ce: d202 bcs.n 80052d6 <__udivmoddi4+0x15a>
  1486. 80052d0: 45a0 cmp r8, r4
  1487. 80052d2: f200 80b9 bhi.w 8005448 <__udivmoddi4+0x2cc>
  1488. 80052d6: 4618 mov r0, r3
  1489. 80052d8: eba4 0408 sub.w r4, r4, r8
  1490. 80052dc: ea40 4002 orr.w r0, r0, r2, lsl #16
  1491. 80052e0: e79c b.n 800521c <__udivmoddi4+0xa0>
  1492. 80052e2: 4629 mov r1, r5
  1493. 80052e4: 4628 mov r0, r5
  1494. 80052e6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
  1495. 80052ea: fa07 f70e lsl.w r7, r7, lr
  1496. 80052ee: f1ce 0320 rsb r3, lr, #32
  1497. 80052f2: fa26 f203 lsr.w r2, r6, r3
  1498. 80052f6: ea4f 4c17 mov.w ip, r7, lsr #16
  1499. 80052fa: fbb2 f1fc udiv r1, r2, ip
  1500. 80052fe: fa1f f887 uxth.w r8, r7
  1501. 8005302: fb0c 2211 mls r2, ip, r1, r2
  1502. 8005306: fa06 f60e lsl.w r6, r6, lr
  1503. 800530a: fa20 f303 lsr.w r3, r0, r3
  1504. 800530e: fb01 f908 mul.w r9, r1, r8
  1505. 8005312: 4333 orrs r3, r6
  1506. 8005314: 0c1e lsrs r6, r3, #16
  1507. 8005316: ea46 4602 orr.w r6, r6, r2, lsl #16
  1508. 800531a: 45b1 cmp r9, r6
  1509. 800531c: fa00 f40e lsl.w r4, r0, lr
  1510. 8005320: d909 bls.n 8005336 <__udivmoddi4+0x1ba>
  1511. 8005322: 19f6 adds r6, r6, r7
  1512. 8005324: f101 32ff add.w r2, r1, #4294967295
  1513. 8005328: f080 808c bcs.w 8005444 <__udivmoddi4+0x2c8>
  1514. 800532c: 45b1 cmp r9, r6
  1515. 800532e: f240 8089 bls.w 8005444 <__udivmoddi4+0x2c8>
  1516. 8005332: 3902 subs r1, #2
  1517. 8005334: 443e add r6, r7
  1518. 8005336: eba6 0609 sub.w r6, r6, r9
  1519. 800533a: fbb6 f0fc udiv r0, r6, ip
  1520. 800533e: fb0c 6210 mls r2, ip, r0, r6
  1521. 8005342: fb00 f908 mul.w r9, r0, r8
  1522. 8005346: b29e uxth r6, r3
  1523. 8005348: ea46 4602 orr.w r6, r6, r2, lsl #16
  1524. 800534c: 45b1 cmp r9, r6
  1525. 800534e: d907 bls.n 8005360 <__udivmoddi4+0x1e4>
  1526. 8005350: 19f6 adds r6, r6, r7
  1527. 8005352: f100 33ff add.w r3, r0, #4294967295
  1528. 8005356: d271 bcs.n 800543c <__udivmoddi4+0x2c0>
  1529. 8005358: 45b1 cmp r9, r6
  1530. 800535a: d96f bls.n 800543c <__udivmoddi4+0x2c0>
  1531. 800535c: 3802 subs r0, #2
  1532. 800535e: 443e add r6, r7
  1533. 8005360: eba6 0609 sub.w r6, r6, r9
  1534. 8005364: ea40 4101 orr.w r1, r0, r1, lsl #16
  1535. 8005368: e78f b.n 800528a <__udivmoddi4+0x10e>
  1536. 800536a: f1c1 0720 rsb r7, r1, #32
  1537. 800536e: fa22 f807 lsr.w r8, r2, r7
  1538. 8005372: 408b lsls r3, r1
  1539. 8005374: ea48 0303 orr.w r3, r8, r3
  1540. 8005378: fa26 f407 lsr.w r4, r6, r7
  1541. 800537c: ea4f 4e13 mov.w lr, r3, lsr #16
  1542. 8005380: fbb4 f9fe udiv r9, r4, lr
  1543. 8005384: fa1f fc83 uxth.w ip, r3
  1544. 8005388: fb0e 4419 mls r4, lr, r9, r4
  1545. 800538c: 408e lsls r6, r1
  1546. 800538e: fa20 f807 lsr.w r8, r0, r7
  1547. 8005392: fb09 fa0c mul.w sl, r9, ip
  1548. 8005396: ea48 0806 orr.w r8, r8, r6
  1549. 800539a: ea4f 4618 mov.w r6, r8, lsr #16
  1550. 800539e: ea46 4404 orr.w r4, r6, r4, lsl #16
  1551. 80053a2: 45a2 cmp sl, r4
  1552. 80053a4: fa02 f201 lsl.w r2, r2, r1
  1553. 80053a8: fa00 f601 lsl.w r6, r0, r1
  1554. 80053ac: d908 bls.n 80053c0 <__udivmoddi4+0x244>
  1555. 80053ae: 18e4 adds r4, r4, r3
  1556. 80053b0: f109 30ff add.w r0, r9, #4294967295
  1557. 80053b4: d244 bcs.n 8005440 <__udivmoddi4+0x2c4>
  1558. 80053b6: 45a2 cmp sl, r4
  1559. 80053b8: d942 bls.n 8005440 <__udivmoddi4+0x2c4>
  1560. 80053ba: f1a9 0902 sub.w r9, r9, #2
  1561. 80053be: 441c add r4, r3
  1562. 80053c0: eba4 040a sub.w r4, r4, sl
  1563. 80053c4: fbb4 f0fe udiv r0, r4, lr
  1564. 80053c8: fb0e 4410 mls r4, lr, r0, r4
  1565. 80053cc: fb00 fc0c mul.w ip, r0, ip
  1566. 80053d0: fa1f f888 uxth.w r8, r8
  1567. 80053d4: ea48 4404 orr.w r4, r8, r4, lsl #16
  1568. 80053d8: 45a4 cmp ip, r4
  1569. 80053da: d907 bls.n 80053ec <__udivmoddi4+0x270>
  1570. 80053dc: 18e4 adds r4, r4, r3
  1571. 80053de: f100 3eff add.w lr, r0, #4294967295
  1572. 80053e2: d229 bcs.n 8005438 <__udivmoddi4+0x2bc>
  1573. 80053e4: 45a4 cmp ip, r4
  1574. 80053e6: d927 bls.n 8005438 <__udivmoddi4+0x2bc>
  1575. 80053e8: 3802 subs r0, #2
  1576. 80053ea: 441c add r4, r3
  1577. 80053ec: ea40 4009 orr.w r0, r0, r9, lsl #16
  1578. 80053f0: fba0 8902 umull r8, r9, r0, r2
  1579. 80053f4: eba4 0c0c sub.w ip, r4, ip
  1580. 80053f8: 45cc cmp ip, r9
  1581. 80053fa: 46c2 mov sl, r8
  1582. 80053fc: 46ce mov lr, r9
  1583. 80053fe: d315 bcc.n 800542c <__udivmoddi4+0x2b0>
  1584. 8005400: d012 beq.n 8005428 <__udivmoddi4+0x2ac>
  1585. 8005402: b155 cbz r5, 800541a <__udivmoddi4+0x29e>
  1586. 8005404: ebb6 030a subs.w r3, r6, sl
  1587. 8005408: eb6c 060e sbc.w r6, ip, lr
  1588. 800540c: fa06 f707 lsl.w r7, r6, r7
  1589. 8005410: 40cb lsrs r3, r1
  1590. 8005412: 431f orrs r7, r3
  1591. 8005414: 40ce lsrs r6, r1
  1592. 8005416: 602f str r7, [r5, #0]
  1593. 8005418: 606e str r6, [r5, #4]
  1594. 800541a: 2100 movs r1, #0
  1595. 800541c: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
  1596. 8005420: 4610 mov r0, r2
  1597. 8005422: e6f7 b.n 8005214 <__udivmoddi4+0x98>
  1598. 8005424: 4689 mov r9, r1
  1599. 8005426: e6de b.n 80051e6 <__udivmoddi4+0x6a>
  1600. 8005428: 4546 cmp r6, r8
  1601. 800542a: d2ea bcs.n 8005402 <__udivmoddi4+0x286>
  1602. 800542c: ebb8 0a02 subs.w sl, r8, r2
  1603. 8005430: eb69 0e03 sbc.w lr, r9, r3
  1604. 8005434: 3801 subs r0, #1
  1605. 8005436: e7e4 b.n 8005402 <__udivmoddi4+0x286>
  1606. 8005438: 4670 mov r0, lr
  1607. 800543a: e7d7 b.n 80053ec <__udivmoddi4+0x270>
  1608. 800543c: 4618 mov r0, r3
  1609. 800543e: e78f b.n 8005360 <__udivmoddi4+0x1e4>
  1610. 8005440: 4681 mov r9, r0
  1611. 8005442: e7bd b.n 80053c0 <__udivmoddi4+0x244>
  1612. 8005444: 4611 mov r1, r2
  1613. 8005446: e776 b.n 8005336 <__udivmoddi4+0x1ba>
  1614. 8005448: 3802 subs r0, #2
  1615. 800544a: 443c add r4, r7
  1616. 800544c: e744 b.n 80052d8 <__udivmoddi4+0x15c>
  1617. 800544e: 4608 mov r0, r1
  1618. 8005450: e706 b.n 8005260 <__udivmoddi4+0xe4>
  1619. 8005452: 3a02 subs r2, #2
  1620. 8005454: 443e add r6, r7
  1621. 8005456: e72b b.n 80052b0 <__udivmoddi4+0x134>
  1622. 08005458 <__aeabi_idiv0>:
  1623. 8005458: 4770 bx lr
  1624. 800545a: bf00 nop
  1625. 0800545c <HAL_InitTick>:
  1626. * implementation in user file.
  1627. * @param TickPriority Tick interrupt priority.
  1628. * @retval HAL status
  1629. */
  1630. __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
  1631. {
  1632. 800545c: b538 push {r3, r4, r5, lr}
  1633. /* Configure the SysTick to have interrupt in 1ms time basis*/
  1634. if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
  1635. 800545e: 4b0e ldr r3, [pc, #56] ; (8005498 <HAL_InitTick+0x3c>)
  1636. {
  1637. 8005460: 4605 mov r5, r0
  1638. if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
  1639. 8005462: 7818 ldrb r0, [r3, #0]
  1640. 8005464: f44f 737a mov.w r3, #1000 ; 0x3e8
  1641. 8005468: fbb3 f3f0 udiv r3, r3, r0
  1642. 800546c: 4a0b ldr r2, [pc, #44] ; (800549c <HAL_InitTick+0x40>)
  1643. 800546e: 6810 ldr r0, [r2, #0]
  1644. 8005470: fbb0 f0f3 udiv r0, r0, r3
  1645. 8005474: f000 fb38 bl 8005ae8 <HAL_SYSTICK_Config>
  1646. 8005478: 4604 mov r4, r0
  1647. 800547a: b958 cbnz r0, 8005494 <HAL_InitTick+0x38>
  1648. {
  1649. return HAL_ERROR;
  1650. }
  1651. /* Configure the SysTick IRQ priority */
  1652. if (TickPriority < (1UL << __NVIC_PRIO_BITS))
  1653. 800547c: 2d0f cmp r5, #15
  1654. 800547e: d809 bhi.n 8005494 <HAL_InitTick+0x38>
  1655. {
  1656. HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
  1657. 8005480: 4602 mov r2, r0
  1658. 8005482: 4629 mov r1, r5
  1659. 8005484: f04f 30ff mov.w r0, #4294967295
  1660. 8005488: f000 faee bl 8005a68 <HAL_NVIC_SetPriority>
  1661. uwTickPrio = TickPriority;
  1662. 800548c: 4b04 ldr r3, [pc, #16] ; (80054a0 <HAL_InitTick+0x44>)
  1663. 800548e: 4620 mov r0, r4
  1664. 8005490: 601d str r5, [r3, #0]
  1665. 8005492: bd38 pop {r3, r4, r5, pc}
  1666. return HAL_ERROR;
  1667. 8005494: 2001 movs r0, #1
  1668. return HAL_ERROR;
  1669. }
  1670. /* Return function status */
  1671. return HAL_OK;
  1672. }
  1673. 8005496: bd38 pop {r3, r4, r5, pc}
  1674. 8005498: 20000000 .word 0x20000000
  1675. 800549c: 20000200 .word 0x20000200
  1676. 80054a0: 20000004 .word 0x20000004
  1677. 080054a4 <HAL_Init>:
  1678. __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
  1679. 80054a4: 4a07 ldr r2, [pc, #28] ; (80054c4 <HAL_Init+0x20>)
  1680. {
  1681. 80054a6: b508 push {r3, lr}
  1682. __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
  1683. 80054a8: 6813 ldr r3, [r2, #0]
  1684. HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
  1685. 80054aa: 2003 movs r0, #3
  1686. __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
  1687. 80054ac: f043 0310 orr.w r3, r3, #16
  1688. 80054b0: 6013 str r3, [r2, #0]
  1689. HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
  1690. 80054b2: f000 fac7 bl 8005a44 <HAL_NVIC_SetPriorityGrouping>
  1691. HAL_InitTick(TICK_INT_PRIORITY);
  1692. 80054b6: 2000 movs r0, #0
  1693. 80054b8: f7ff ffd0 bl 800545c <HAL_InitTick>
  1694. HAL_MspInit();
  1695. 80054bc: f003 f838 bl 8008530 <HAL_MspInit>
  1696. }
  1697. 80054c0: 2000 movs r0, #0
  1698. 80054c2: bd08 pop {r3, pc}
  1699. 80054c4: 40022000 .word 0x40022000
  1700. 080054c8 <HAL_IncTick>:
  1701. * implementations in user file.
  1702. * @retval None
  1703. */
  1704. __weak void HAL_IncTick(void)
  1705. {
  1706. uwTick += uwTickFreq;
  1707. 80054c8: 4a03 ldr r2, [pc, #12] ; (80054d8 <HAL_IncTick+0x10>)
  1708. 80054ca: 4b04 ldr r3, [pc, #16] ; (80054dc <HAL_IncTick+0x14>)
  1709. 80054cc: 6811 ldr r1, [r2, #0]
  1710. 80054ce: 781b ldrb r3, [r3, #0]
  1711. 80054d0: 440b add r3, r1
  1712. 80054d2: 6013 str r3, [r2, #0]
  1713. 80054d4: 4770 bx lr
  1714. 80054d6: bf00 nop
  1715. 80054d8: 20000460 .word 0x20000460
  1716. 80054dc: 20000000 .word 0x20000000
  1717. 080054e0 <HAL_GetTick>:
  1718. * implementations in user file.
  1719. * @retval tick value
  1720. */
  1721. __weak uint32_t HAL_GetTick(void)
  1722. {
  1723. return uwTick;
  1724. 80054e0: 4b01 ldr r3, [pc, #4] ; (80054e8 <HAL_GetTick+0x8>)
  1725. 80054e2: 6818 ldr r0, [r3, #0]
  1726. }
  1727. 80054e4: 4770 bx lr
  1728. 80054e6: bf00 nop
  1729. 80054e8: 20000460 .word 0x20000460
  1730. 080054ec <HAL_Delay>:
  1731. * implementations in user file.
  1732. * @param Delay specifies the delay time length, in milliseconds.
  1733. * @retval None
  1734. */
  1735. __weak void HAL_Delay(uint32_t Delay)
  1736. {
  1737. 80054ec: b538 push {r3, r4, r5, lr}
  1738. 80054ee: 4604 mov r4, r0
  1739. uint32_t tickstart = HAL_GetTick();
  1740. 80054f0: f7ff fff6 bl 80054e0 <HAL_GetTick>
  1741. 80054f4: 4605 mov r5, r0
  1742. uint32_t wait = Delay;
  1743. /* Add a freq to guarantee minimum wait */
  1744. if (wait < HAL_MAX_DELAY)
  1745. 80054f6: 1c63 adds r3, r4, #1
  1746. {
  1747. wait += (uint32_t)(uwTickFreq);
  1748. 80054f8: bf1e ittt ne
  1749. 80054fa: 4b04 ldrne r3, [pc, #16] ; (800550c <HAL_Delay+0x20>)
  1750. 80054fc: 781b ldrbne r3, [r3, #0]
  1751. 80054fe: 18e4 addne r4, r4, r3
  1752. }
  1753. while ((HAL_GetTick() - tickstart) < wait)
  1754. 8005500: f7ff ffee bl 80054e0 <HAL_GetTick>
  1755. 8005504: 1b40 subs r0, r0, r5
  1756. 8005506: 4284 cmp r4, r0
  1757. 8005508: d8fa bhi.n 8005500 <HAL_Delay+0x14>
  1758. {
  1759. }
  1760. }
  1761. 800550a: bd38 pop {r3, r4, r5, pc}
  1762. 800550c: 20000000 .word 0x20000000
  1763. 08005510 <HAL_ADC_ConvCpltCallback>:
  1764. 8005510: 4770 bx lr
  1765. 08005512 <ADC_DMAConvCplt>:
  1766. * @retval None
  1767. */
  1768. void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
  1769. {
  1770. /* Retrieve ADC handle corresponding to current DMA handle */
  1771. ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
  1772. 8005512: 6a43 ldr r3, [r0, #36] ; 0x24
  1773. {
  1774. 8005514: b510 push {r4, lr}
  1775. /* Update state machine on conversion status if not in error state */
  1776. if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
  1777. 8005516: 6a9a ldr r2, [r3, #40] ; 0x28
  1778. 8005518: f012 0f50 tst.w r2, #80 ; 0x50
  1779. 800551c: d11b bne.n 8005556 <ADC_DMAConvCplt+0x44>
  1780. {
  1781. /* Update ADC state machine */
  1782. SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
  1783. 800551e: 6a9a ldr r2, [r3, #40] ; 0x28
  1784. 8005520: f442 7200 orr.w r2, r2, #512 ; 0x200
  1785. 8005524: 629a str r2, [r3, #40] ; 0x28
  1786. /* Determine whether any further conversion upcoming on group regular */
  1787. /* by external trigger, continuous mode or scan sequence on going. */
  1788. /* Note: On STM32F1 devices, in case of sequencer enabled */
  1789. /* (several ranks selected), end of conversion flag is raised */
  1790. /* at the end of the sequence. */
  1791. if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
  1792. 8005526: 681a ldr r2, [r3, #0]
  1793. 8005528: 6892 ldr r2, [r2, #8]
  1794. 800552a: f402 2260 and.w r2, r2, #917504 ; 0xe0000
  1795. 800552e: f5b2 2f60 cmp.w r2, #917504 ; 0xe0000
  1796. 8005532: d10c bne.n 800554e <ADC_DMAConvCplt+0x3c>
  1797. 8005534: 68da ldr r2, [r3, #12]
  1798. 8005536: b952 cbnz r2, 800554e <ADC_DMAConvCplt+0x3c>
  1799. (hadc->Init.ContinuousConvMode == DISABLE) )
  1800. {
  1801. /* Set ADC state */
  1802. CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
  1803. 8005538: 6a9a ldr r2, [r3, #40] ; 0x28
  1804. 800553a: f422 7280 bic.w r2, r2, #256 ; 0x100
  1805. 800553e: 629a str r2, [r3, #40] ; 0x28
  1806. if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
  1807. 8005540: 6a9a ldr r2, [r3, #40] ; 0x28
  1808. 8005542: 04d2 lsls r2, r2, #19
  1809. {
  1810. SET_BIT(hadc->State, HAL_ADC_STATE_READY);
  1811. 8005544: bf5e ittt pl
  1812. 8005546: 6a9a ldrpl r2, [r3, #40] ; 0x28
  1813. 8005548: f042 0201 orrpl.w r2, r2, #1
  1814. 800554c: 629a strpl r2, [r3, #40] ; 0x28
  1815. }
  1816. }
  1817. /* Conversion complete callback */
  1818. HAL_ADC_ConvCpltCallback(hadc);
  1819. 800554e: 4618 mov r0, r3
  1820. 8005550: f7ff ffde bl 8005510 <HAL_ADC_ConvCpltCallback>
  1821. 8005554: bd10 pop {r4, pc}
  1822. }
  1823. else
  1824. {
  1825. /* Call DMA error callback */
  1826. hadc->DMA_Handle->XferErrorCallback(hdma);
  1827. 8005556: 6a1b ldr r3, [r3, #32]
  1828. }
  1829. }
  1830. 8005558: e8bd 4010 ldmia.w sp!, {r4, lr}
  1831. hadc->DMA_Handle->XferErrorCallback(hdma);
  1832. 800555c: 6b1b ldr r3, [r3, #48] ; 0x30
  1833. 800555e: 4718 bx r3
  1834. 08005560 <HAL_ADC_ConvHalfCpltCallback>:
  1835. 8005560: 4770 bx lr
  1836. 08005562 <ADC_DMAHalfConvCplt>:
  1837. * @brief DMA half transfer complete callback.
  1838. * @param hdma: pointer to DMA handle.
  1839. * @retval None
  1840. */
  1841. void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
  1842. {
  1843. 8005562: b508 push {r3, lr}
  1844. /* Retrieve ADC handle corresponding to current DMA handle */
  1845. ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
  1846. /* Half conversion callback */
  1847. HAL_ADC_ConvHalfCpltCallback(hadc);
  1848. 8005564: 6a40 ldr r0, [r0, #36] ; 0x24
  1849. 8005566: f7ff fffb bl 8005560 <HAL_ADC_ConvHalfCpltCallback>
  1850. 800556a: bd08 pop {r3, pc}
  1851. 0800556c <HAL_ADC_ErrorCallback>:
  1852. {
  1853. 800556c: 4770 bx lr
  1854. 0800556e <ADC_DMAError>:
  1855. * @retval None
  1856. */
  1857. void ADC_DMAError(DMA_HandleTypeDef *hdma)
  1858. {
  1859. /* Retrieve ADC handle corresponding to current DMA handle */
  1860. ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
  1861. 800556e: 6a40 ldr r0, [r0, #36] ; 0x24
  1862. {
  1863. 8005570: b508 push {r3, lr}
  1864. /* Set ADC state */
  1865. SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
  1866. 8005572: 6a83 ldr r3, [r0, #40] ; 0x28
  1867. 8005574: f043 0340 orr.w r3, r3, #64 ; 0x40
  1868. 8005578: 6283 str r3, [r0, #40] ; 0x28
  1869. /* Set ADC error code to DMA error */
  1870. SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
  1871. 800557a: 6ac3 ldr r3, [r0, #44] ; 0x2c
  1872. 800557c: f043 0304 orr.w r3, r3, #4
  1873. 8005580: 62c3 str r3, [r0, #44] ; 0x2c
  1874. /* Error callback */
  1875. HAL_ADC_ErrorCallback(hadc);
  1876. 8005582: f7ff fff3 bl 800556c <HAL_ADC_ErrorCallback>
  1877. 8005586: bd08 pop {r3, pc}
  1878. 08005588 <HAL_ADC_ConfigChannel>:
  1879. __IO uint32_t wait_loop_index = 0U;
  1880. 8005588: 2300 movs r3, #0
  1881. {
  1882. 800558a: b573 push {r0, r1, r4, r5, r6, lr}
  1883. __IO uint32_t wait_loop_index = 0U;
  1884. 800558c: 9301 str r3, [sp, #4]
  1885. __HAL_LOCK(hadc);
  1886. 800558e: f890 3024 ldrb.w r3, [r0, #36] ; 0x24
  1887. 8005592: 2b01 cmp r3, #1
  1888. 8005594: d074 beq.n 8005680 <HAL_ADC_ConfigChannel+0xf8>
  1889. 8005596: 2301 movs r3, #1
  1890. if (sConfig->Rank < 7U)
  1891. 8005598: 684d ldr r5, [r1, #4]
  1892. __HAL_LOCK(hadc);
  1893. 800559a: f880 3024 strb.w r3, [r0, #36] ; 0x24
  1894. if (sConfig->Rank < 7U)
  1895. 800559e: 2d06 cmp r5, #6
  1896. 80055a0: 6802 ldr r2, [r0, #0]
  1897. 80055a2: ea4f 0385 mov.w r3, r5, lsl #2
  1898. 80055a6: 680c ldr r4, [r1, #0]
  1899. 80055a8: d825 bhi.n 80055f6 <HAL_ADC_ConfigChannel+0x6e>
  1900. MODIFY_REG(hadc->Instance->SQR3 ,
  1901. 80055aa: 442b add r3, r5
  1902. 80055ac: 251f movs r5, #31
  1903. 80055ae: 6b56 ldr r6, [r2, #52] ; 0x34
  1904. 80055b0: 3b05 subs r3, #5
  1905. 80055b2: 409d lsls r5, r3
  1906. 80055b4: ea26 0505 bic.w r5, r6, r5
  1907. 80055b8: fa04 f303 lsl.w r3, r4, r3
  1908. 80055bc: 432b orrs r3, r5
  1909. 80055be: 6353 str r3, [r2, #52] ; 0x34
  1910. if (sConfig->Channel >= ADC_CHANNEL_10)
  1911. 80055c0: 2c09 cmp r4, #9
  1912. 80055c2: ea4f 0344 mov.w r3, r4, lsl #1
  1913. 80055c6: 688d ldr r5, [r1, #8]
  1914. 80055c8: d92f bls.n 800562a <HAL_ADC_ConfigChannel+0xa2>
  1915. MODIFY_REG(hadc->Instance->SMPR1 ,
  1916. 80055ca: 2607 movs r6, #7
  1917. 80055cc: 4423 add r3, r4
  1918. 80055ce: 68d1 ldr r1, [r2, #12]
  1919. 80055d0: 3b1e subs r3, #30
  1920. 80055d2: 409e lsls r6, r3
  1921. 80055d4: ea21 0106 bic.w r1, r1, r6
  1922. 80055d8: fa05 f303 lsl.w r3, r5, r3
  1923. 80055dc: 430b orrs r3, r1
  1924. 80055de: 60d3 str r3, [r2, #12]
  1925. if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
  1926. 80055e0: f1a4 0310 sub.w r3, r4, #16
  1927. 80055e4: 2b01 cmp r3, #1
  1928. 80055e6: d92b bls.n 8005640 <HAL_ADC_ConfigChannel+0xb8>
  1929. HAL_StatusTypeDef tmp_hal_status = HAL_OK;
  1930. 80055e8: 2300 movs r3, #0
  1931. __HAL_UNLOCK(hadc);
  1932. 80055ea: 2200 movs r2, #0
  1933. 80055ec: f880 2024 strb.w r2, [r0, #36] ; 0x24
  1934. }
  1935. 80055f0: 4618 mov r0, r3
  1936. 80055f2: b002 add sp, #8
  1937. 80055f4: bd70 pop {r4, r5, r6, pc}
  1938. else if (sConfig->Rank < 13U)
  1939. 80055f6: 2d0c cmp r5, #12
  1940. 80055f8: d80b bhi.n 8005612 <HAL_ADC_ConfigChannel+0x8a>
  1941. MODIFY_REG(hadc->Instance->SQR2 ,
  1942. 80055fa: 442b add r3, r5
  1943. 80055fc: 251f movs r5, #31
  1944. 80055fe: 6b16 ldr r6, [r2, #48] ; 0x30
  1945. 8005600: 3b23 subs r3, #35 ; 0x23
  1946. 8005602: 409d lsls r5, r3
  1947. 8005604: ea26 0505 bic.w r5, r6, r5
  1948. 8005608: fa04 f303 lsl.w r3, r4, r3
  1949. 800560c: 432b orrs r3, r5
  1950. 800560e: 6313 str r3, [r2, #48] ; 0x30
  1951. 8005610: e7d6 b.n 80055c0 <HAL_ADC_ConfigChannel+0x38>
  1952. MODIFY_REG(hadc->Instance->SQR1 ,
  1953. 8005612: 442b add r3, r5
  1954. 8005614: 251f movs r5, #31
  1955. 8005616: 6ad6 ldr r6, [r2, #44] ; 0x2c
  1956. 8005618: 3b41 subs r3, #65 ; 0x41
  1957. 800561a: 409d lsls r5, r3
  1958. 800561c: ea26 0505 bic.w r5, r6, r5
  1959. 8005620: fa04 f303 lsl.w r3, r4, r3
  1960. 8005624: 432b orrs r3, r5
  1961. 8005626: 62d3 str r3, [r2, #44] ; 0x2c
  1962. 8005628: e7ca b.n 80055c0 <HAL_ADC_ConfigChannel+0x38>
  1963. MODIFY_REG(hadc->Instance->SMPR2 ,
  1964. 800562a: 2607 movs r6, #7
  1965. 800562c: 6911 ldr r1, [r2, #16]
  1966. 800562e: 4423 add r3, r4
  1967. 8005630: 409e lsls r6, r3
  1968. 8005632: ea21 0106 bic.w r1, r1, r6
  1969. 8005636: fa05 f303 lsl.w r3, r5, r3
  1970. 800563a: 430b orrs r3, r1
  1971. 800563c: 6113 str r3, [r2, #16]
  1972. 800563e: e7cf b.n 80055e0 <HAL_ADC_ConfigChannel+0x58>
  1973. if (hadc->Instance == ADC1)
  1974. 8005640: 4b10 ldr r3, [pc, #64] ; (8005684 <HAL_ADC_ConfigChannel+0xfc>)
  1975. 8005642: 429a cmp r2, r3
  1976. 8005644: d116 bne.n 8005674 <HAL_ADC_ConfigChannel+0xec>
  1977. if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET)
  1978. 8005646: 6893 ldr r3, [r2, #8]
  1979. 8005648: 021b lsls r3, r3, #8
  1980. 800564a: d4cd bmi.n 80055e8 <HAL_ADC_ConfigChannel+0x60>
  1981. SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
  1982. 800564c: 6893 ldr r3, [r2, #8]
  1983. if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
  1984. 800564e: 2c10 cmp r4, #16
  1985. SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
  1986. 8005650: f443 0300 orr.w r3, r3, #8388608 ; 0x800000
  1987. 8005654: 6093 str r3, [r2, #8]
  1988. if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
  1989. 8005656: d1c7 bne.n 80055e8 <HAL_ADC_ConfigChannel+0x60>
  1990. wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
  1991. 8005658: 4b0b ldr r3, [pc, #44] ; (8005688 <HAL_ADC_ConfigChannel+0x100>)
  1992. 800565a: 4a0c ldr r2, [pc, #48] ; (800568c <HAL_ADC_ConfigChannel+0x104>)
  1993. 800565c: 681b ldr r3, [r3, #0]
  1994. 800565e: fbb3 f2f2 udiv r2, r3, r2
  1995. 8005662: 230a movs r3, #10
  1996. 8005664: 4353 muls r3, r2
  1997. wait_loop_index--;
  1998. 8005666: 9301 str r3, [sp, #4]
  1999. while(wait_loop_index != 0U)
  2000. 8005668: 9b01 ldr r3, [sp, #4]
  2001. 800566a: 2b00 cmp r3, #0
  2002. 800566c: d0bc beq.n 80055e8 <HAL_ADC_ConfigChannel+0x60>
  2003. wait_loop_index--;
  2004. 800566e: 9b01 ldr r3, [sp, #4]
  2005. 8005670: 3b01 subs r3, #1
  2006. 8005672: e7f8 b.n 8005666 <HAL_ADC_ConfigChannel+0xde>
  2007. SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
  2008. 8005674: 6a83 ldr r3, [r0, #40] ; 0x28
  2009. 8005676: f043 0320 orr.w r3, r3, #32
  2010. 800567a: 6283 str r3, [r0, #40] ; 0x28
  2011. tmp_hal_status = HAL_ERROR;
  2012. 800567c: 2301 movs r3, #1
  2013. 800567e: e7b4 b.n 80055ea <HAL_ADC_ConfigChannel+0x62>
  2014. __HAL_LOCK(hadc);
  2015. 8005680: 2302 movs r3, #2
  2016. 8005682: e7b5 b.n 80055f0 <HAL_ADC_ConfigChannel+0x68>
  2017. 8005684: 40012400 .word 0x40012400
  2018. 8005688: 20000200 .word 0x20000200
  2019. 800568c: 000f4240 .word 0x000f4240
  2020. 08005690 <ADC_Enable>:
  2021. __IO uint32_t wait_loop_index = 0U;
  2022. 8005690: 2300 movs r3, #0
  2023. {
  2024. 8005692: b573 push {r0, r1, r4, r5, r6, lr}
  2025. __IO uint32_t wait_loop_index = 0U;
  2026. 8005694: 9301 str r3, [sp, #4]
  2027. if (ADC_IS_ENABLE(hadc) == RESET)
  2028. 8005696: 6803 ldr r3, [r0, #0]
  2029. {
  2030. 8005698: 4604 mov r4, r0
  2031. if (ADC_IS_ENABLE(hadc) == RESET)
  2032. 800569a: 689a ldr r2, [r3, #8]
  2033. 800569c: 07d2 lsls r2, r2, #31
  2034. 800569e: d502 bpl.n 80056a6 <ADC_Enable+0x16>
  2035. return HAL_OK;
  2036. 80056a0: 2000 movs r0, #0
  2037. }
  2038. 80056a2: b002 add sp, #8
  2039. 80056a4: bd70 pop {r4, r5, r6, pc}
  2040. __HAL_ADC_ENABLE(hadc);
  2041. 80056a6: 689a ldr r2, [r3, #8]
  2042. 80056a8: f042 0201 orr.w r2, r2, #1
  2043. 80056ac: 609a str r2, [r3, #8]
  2044. wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
  2045. 80056ae: 4b12 ldr r3, [pc, #72] ; (80056f8 <ADC_Enable+0x68>)
  2046. 80056b0: 4a12 ldr r2, [pc, #72] ; (80056fc <ADC_Enable+0x6c>)
  2047. 80056b2: 681b ldr r3, [r3, #0]
  2048. 80056b4: fbb3 f3f2 udiv r3, r3, r2
  2049. wait_loop_index--;
  2050. 80056b8: 9301 str r3, [sp, #4]
  2051. while(wait_loop_index != 0U)
  2052. 80056ba: 9b01 ldr r3, [sp, #4]
  2053. 80056bc: b9c3 cbnz r3, 80056f0 <ADC_Enable+0x60>
  2054. tickstart = HAL_GetTick();
  2055. 80056be: f7ff ff0f bl 80054e0 <HAL_GetTick>
  2056. 80056c2: 4606 mov r6, r0
  2057. while(ADC_IS_ENABLE(hadc) == RESET)
  2058. 80056c4: 6823 ldr r3, [r4, #0]
  2059. 80056c6: 689d ldr r5, [r3, #8]
  2060. 80056c8: f015 0501 ands.w r5, r5, #1
  2061. 80056cc: d1e8 bne.n 80056a0 <ADC_Enable+0x10>
  2062. if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
  2063. 80056ce: f7ff ff07 bl 80054e0 <HAL_GetTick>
  2064. 80056d2: 1b80 subs r0, r0, r6
  2065. 80056d4: 2802 cmp r0, #2
  2066. 80056d6: d9f5 bls.n 80056c4 <ADC_Enable+0x34>
  2067. SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
  2068. 80056d8: 6aa3 ldr r3, [r4, #40] ; 0x28
  2069. __HAL_UNLOCK(hadc);
  2070. 80056da: f884 5024 strb.w r5, [r4, #36] ; 0x24
  2071. SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
  2072. 80056de: f043 0310 orr.w r3, r3, #16
  2073. 80056e2: 62a3 str r3, [r4, #40] ; 0x28
  2074. SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
  2075. 80056e4: 6ae3 ldr r3, [r4, #44] ; 0x2c
  2076. __HAL_UNLOCK(hadc);
  2077. 80056e6: 2001 movs r0, #1
  2078. SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
  2079. 80056e8: f043 0301 orr.w r3, r3, #1
  2080. 80056ec: 62e3 str r3, [r4, #44] ; 0x2c
  2081. 80056ee: e7d8 b.n 80056a2 <ADC_Enable+0x12>
  2082. wait_loop_index--;
  2083. 80056f0: 9b01 ldr r3, [sp, #4]
  2084. 80056f2: 3b01 subs r3, #1
  2085. 80056f4: e7e0 b.n 80056b8 <ADC_Enable+0x28>
  2086. 80056f6: bf00 nop
  2087. 80056f8: 20000200 .word 0x20000200
  2088. 80056fc: 000f4240 .word 0x000f4240
  2089. 08005700 <HAL_ADC_Start_DMA>:
  2090. {
  2091. 8005700: e92d 41d8 stmdb sp!, {r3, r4, r6, r7, r8, lr}
  2092. 8005704: 4690 mov r8, r2
  2093. if(ADC_MULTIMODE_IS_ENABLE(hadc) == RESET)
  2094. 8005706: 4b40 ldr r3, [pc, #256] ; (8005808 <HAL_ADC_Start_DMA+0x108>)
  2095. 8005708: 6802 ldr r2, [r0, #0]
  2096. {
  2097. 800570a: 4604 mov r4, r0
  2098. if(ADC_MULTIMODE_IS_ENABLE(hadc) == RESET)
  2099. 800570c: 429a cmp r2, r3
  2100. {
  2101. 800570e: 460f mov r7, r1
  2102. if(ADC_MULTIMODE_IS_ENABLE(hadc) == RESET)
  2103. 8005710: d002 beq.n 8005718 <HAL_ADC_Start_DMA+0x18>
  2104. 8005712: 493e ldr r1, [pc, #248] ; (800580c <HAL_ADC_Start_DMA+0x10c>)
  2105. 8005714: 428a cmp r2, r1
  2106. 8005716: d103 bne.n 8005720 <HAL_ADC_Start_DMA+0x20>
  2107. 8005718: 685b ldr r3, [r3, #4]
  2108. 800571a: f413 2f70 tst.w r3, #983040 ; 0xf0000
  2109. 800571e: d16e bne.n 80057fe <HAL_ADC_Start_DMA+0xfe>
  2110. __HAL_LOCK(hadc);
  2111. 8005720: f894 3024 ldrb.w r3, [r4, #36] ; 0x24
  2112. 8005724: 2b01 cmp r3, #1
  2113. 8005726: d06c beq.n 8005802 <HAL_ADC_Start_DMA+0x102>
  2114. 8005728: 2301 movs r3, #1
  2115. tmp_hal_status = ADC_Enable(hadc);
  2116. 800572a: 4620 mov r0, r4
  2117. __HAL_LOCK(hadc);
  2118. 800572c: f884 3024 strb.w r3, [r4, #36] ; 0x24
  2119. tmp_hal_status = ADC_Enable(hadc);
  2120. 8005730: f7ff ffae bl 8005690 <ADC_Enable>
  2121. if (tmp_hal_status == HAL_OK)
  2122. 8005734: 4606 mov r6, r0
  2123. 8005736: 2800 cmp r0, #0
  2124. 8005738: d15d bne.n 80057f6 <HAL_ADC_Start_DMA+0xf6>
  2125. ADC_STATE_CLR_SET(hadc->State,
  2126. 800573a: 6aa0 ldr r0, [r4, #40] ; 0x28
  2127. if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
  2128. 800573c: 6821 ldr r1, [r4, #0]
  2129. ADC_STATE_CLR_SET(hadc->State,
  2130. 800573e: f420 6070 bic.w r0, r0, #3840 ; 0xf00
  2131. if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
  2132. 8005742: 4b32 ldr r3, [pc, #200] ; (800580c <HAL_ADC_Start_DMA+0x10c>)
  2133. ADC_STATE_CLR_SET(hadc->State,
  2134. 8005744: f020 0001 bic.w r0, r0, #1
  2135. 8005748: f440 7080 orr.w r0, r0, #256 ; 0x100
  2136. if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
  2137. 800574c: 4299 cmp r1, r3
  2138. ADC_STATE_CLR_SET(hadc->State,
  2139. 800574e: 62a0 str r0, [r4, #40] ; 0x28
  2140. if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
  2141. 8005750: d104 bne.n 800575c <HAL_ADC_Start_DMA+0x5c>
  2142. 8005752: 4a2d ldr r2, [pc, #180] ; (8005808 <HAL_ADC_Start_DMA+0x108>)
  2143. 8005754: 6853 ldr r3, [r2, #4]
  2144. 8005756: f413 2f70 tst.w r3, #983040 ; 0xf0000
  2145. 800575a: d13e bne.n 80057da <HAL_ADC_Start_DMA+0xda>
  2146. CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
  2147. 800575c: 6aa3 ldr r3, [r4, #40] ; 0x28
  2148. 800575e: f423 1380 bic.w r3, r3, #1048576 ; 0x100000
  2149. 8005762: 62a3 str r3, [r4, #40] ; 0x28
  2150. if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
  2151. 8005764: 684b ldr r3, [r1, #4]
  2152. 8005766: 055a lsls r2, r3, #21
  2153. 8005768: d505 bpl.n 8005776 <HAL_ADC_Start_DMA+0x76>
  2154. ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
  2155. 800576a: 6aa3 ldr r3, [r4, #40] ; 0x28
  2156. 800576c: f423 5340 bic.w r3, r3, #12288 ; 0x3000
  2157. 8005770: f443 5380 orr.w r3, r3, #4096 ; 0x1000
  2158. 8005774: 62a3 str r3, [r4, #40] ; 0x28
  2159. if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
  2160. 8005776: 6aa3 ldr r3, [r4, #40] ; 0x28
  2161. hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
  2162. 8005778: 6a20 ldr r0, [r4, #32]
  2163. if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
  2164. 800577a: f413 5380 ands.w r3, r3, #4096 ; 0x1000
  2165. CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
  2166. 800577e: bf18 it ne
  2167. 8005780: 6ae3 ldrne r3, [r4, #44] ; 0x2c
  2168. HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
  2169. 8005782: 463a mov r2, r7
  2170. CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
  2171. 8005784: bf18 it ne
  2172. 8005786: f023 0306 bicne.w r3, r3, #6
  2173. ADC_CLEAR_ERRORCODE(hadc);
  2174. 800578a: 62e3 str r3, [r4, #44] ; 0x2c
  2175. __HAL_UNLOCK(hadc);
  2176. 800578c: 2300 movs r3, #0
  2177. 800578e: f884 3024 strb.w r3, [r4, #36] ; 0x24
  2178. hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
  2179. 8005792: 4b1f ldr r3, [pc, #124] ; (8005810 <HAL_ADC_Start_DMA+0x110>)
  2180. HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
  2181. 8005794: 314c adds r1, #76 ; 0x4c
  2182. hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
  2183. 8005796: 6283 str r3, [r0, #40] ; 0x28
  2184. hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
  2185. 8005798: 4b1e ldr r3, [pc, #120] ; (8005814 <HAL_ADC_Start_DMA+0x114>)
  2186. 800579a: 62c3 str r3, [r0, #44] ; 0x2c
  2187. hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
  2188. 800579c: 4b1e ldr r3, [pc, #120] ; (8005818 <HAL_ADC_Start_DMA+0x118>)
  2189. 800579e: 6303 str r3, [r0, #48] ; 0x30
  2190. __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
  2191. 80057a0: f06f 0302 mvn.w r3, #2
  2192. 80057a4: f841 3c4c str.w r3, [r1, #-76]
  2193. SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA);
  2194. 80057a8: f851 3c44 ldr.w r3, [r1, #-68]
  2195. 80057ac: f443 7380 orr.w r3, r3, #256 ; 0x100
  2196. 80057b0: f841 3c44 str.w r3, [r1, #-68]
  2197. HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
  2198. 80057b4: 4643 mov r3, r8
  2199. 80057b6: f000 f9ed bl 8005b94 <HAL_DMA_Start_IT>
  2200. if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
  2201. 80057ba: 6823 ldr r3, [r4, #0]
  2202. 80057bc: 689a ldr r2, [r3, #8]
  2203. 80057be: f402 2260 and.w r2, r2, #917504 ; 0xe0000
  2204. 80057c2: f5b2 2f60 cmp.w r2, #917504 ; 0xe0000
  2205. SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
  2206. 80057c6: 689a ldr r2, [r3, #8]
  2207. 80057c8: bf0c ite eq
  2208. 80057ca: f442 02a0 orreq.w r2, r2, #5242880 ; 0x500000
  2209. SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
  2210. 80057ce: f442 1280 orrne.w r2, r2, #1048576 ; 0x100000
  2211. 80057d2: 609a str r2, [r3, #8]
  2212. }
  2213. 80057d4: 4630 mov r0, r6
  2214. 80057d6: e8bd 81d8 ldmia.w sp!, {r3, r4, r6, r7, r8, pc}
  2215. SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
  2216. 80057da: 6aa3 ldr r3, [r4, #40] ; 0x28
  2217. 80057dc: f443 1380 orr.w r3, r3, #1048576 ; 0x100000
  2218. 80057e0: 62a3 str r3, [r4, #40] ; 0x28
  2219. if (ADC_MULTIMODE_AUTO_INJECTED(hadc))
  2220. 80057e2: 6853 ldr r3, [r2, #4]
  2221. 80057e4: 055b lsls r3, r3, #21
  2222. ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
  2223. 80057e6: bf41 itttt mi
  2224. 80057e8: 6aa0 ldrmi r0, [r4, #40] ; 0x28
  2225. 80057ea: f420 5040 bicmi.w r0, r0, #12288 ; 0x3000
  2226. 80057ee: f440 5080 orrmi.w r0, r0, #4096 ; 0x1000
  2227. 80057f2: 62a0 strmi r0, [r4, #40] ; 0x28
  2228. 80057f4: e7bf b.n 8005776 <HAL_ADC_Start_DMA+0x76>
  2229. __HAL_UNLOCK(hadc);
  2230. 80057f6: 2300 movs r3, #0
  2231. 80057f8: f884 3024 strb.w r3, [r4, #36] ; 0x24
  2232. 80057fc: e7ea b.n 80057d4 <HAL_ADC_Start_DMA+0xd4>
  2233. tmp_hal_status = HAL_ERROR;
  2234. 80057fe: 2601 movs r6, #1
  2235. 8005800: e7e8 b.n 80057d4 <HAL_ADC_Start_DMA+0xd4>
  2236. __HAL_LOCK(hadc);
  2237. 8005802: 2602 movs r6, #2
  2238. 8005804: e7e6 b.n 80057d4 <HAL_ADC_Start_DMA+0xd4>
  2239. 8005806: bf00 nop
  2240. 8005808: 40012400 .word 0x40012400
  2241. 800580c: 40012800 .word 0x40012800
  2242. 8005810: 08005513 .word 0x08005513
  2243. 8005814: 08005563 .word 0x08005563
  2244. 8005818: 0800556f .word 0x0800556f
  2245. 0800581c <ADC_ConversionStop_Disable>:
  2246. {
  2247. 800581c: b538 push {r3, r4, r5, lr}
  2248. if (ADC_IS_ENABLE(hadc) != RESET)
  2249. 800581e: 6803 ldr r3, [r0, #0]
  2250. {
  2251. 8005820: 4604 mov r4, r0
  2252. if (ADC_IS_ENABLE(hadc) != RESET)
  2253. 8005822: 689a ldr r2, [r3, #8]
  2254. 8005824: 07d2 lsls r2, r2, #31
  2255. 8005826: d401 bmi.n 800582c <ADC_ConversionStop_Disable+0x10>
  2256. return HAL_OK;
  2257. 8005828: 2000 movs r0, #0
  2258. 800582a: bd38 pop {r3, r4, r5, pc}
  2259. __HAL_ADC_DISABLE(hadc);
  2260. 800582c: 689a ldr r2, [r3, #8]
  2261. 800582e: f022 0201 bic.w r2, r2, #1
  2262. 8005832: 609a str r2, [r3, #8]
  2263. tickstart = HAL_GetTick();
  2264. 8005834: f7ff fe54 bl 80054e0 <HAL_GetTick>
  2265. 8005838: 4605 mov r5, r0
  2266. while(ADC_IS_ENABLE(hadc) != RESET)
  2267. 800583a: 6823 ldr r3, [r4, #0]
  2268. 800583c: 689b ldr r3, [r3, #8]
  2269. 800583e: 07db lsls r3, r3, #31
  2270. 8005840: d5f2 bpl.n 8005828 <ADC_ConversionStop_Disable+0xc>
  2271. if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
  2272. 8005842: f7ff fe4d bl 80054e0 <HAL_GetTick>
  2273. 8005846: 1b40 subs r0, r0, r5
  2274. 8005848: 2802 cmp r0, #2
  2275. 800584a: d9f6 bls.n 800583a <ADC_ConversionStop_Disable+0x1e>
  2276. SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
  2277. 800584c: 6aa3 ldr r3, [r4, #40] ; 0x28
  2278. SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
  2279. 800584e: 2001 movs r0, #1
  2280. SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
  2281. 8005850: f043 0310 orr.w r3, r3, #16
  2282. 8005854: 62a3 str r3, [r4, #40] ; 0x28
  2283. SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
  2284. 8005856: 6ae3 ldr r3, [r4, #44] ; 0x2c
  2285. 8005858: f043 0301 orr.w r3, r3, #1
  2286. 800585c: 62e3 str r3, [r4, #44] ; 0x2c
  2287. 800585e: bd38 pop {r3, r4, r5, pc}
  2288. 08005860 <HAL_ADC_Init>:
  2289. {
  2290. 8005860: b5f8 push {r3, r4, r5, r6, r7, lr}
  2291. if(hadc == NULL)
  2292. 8005862: 4604 mov r4, r0
  2293. 8005864: 2800 cmp r0, #0
  2294. 8005866: d077 beq.n 8005958 <HAL_ADC_Init+0xf8>
  2295. if (hadc->State == HAL_ADC_STATE_RESET)
  2296. 8005868: 6a83 ldr r3, [r0, #40] ; 0x28
  2297. 800586a: b923 cbnz r3, 8005876 <HAL_ADC_Init+0x16>
  2298. ADC_CLEAR_ERRORCODE(hadc);
  2299. 800586c: 62c3 str r3, [r0, #44] ; 0x2c
  2300. hadc->Lock = HAL_UNLOCKED;
  2301. 800586e: f880 3024 strb.w r3, [r0, #36] ; 0x24
  2302. HAL_ADC_MspInit(hadc);
  2303. 8005872: f002 fe7f bl 8008574 <HAL_ADC_MspInit>
  2304. tmp_hal_status = ADC_ConversionStop_Disable(hadc);
  2305. 8005876: 4620 mov r0, r4
  2306. 8005878: f7ff ffd0 bl 800581c <ADC_ConversionStop_Disable>
  2307. if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
  2308. 800587c: 6aa3 ldr r3, [r4, #40] ; 0x28
  2309. 800587e: f013 0310 ands.w r3, r3, #16
  2310. 8005882: d16b bne.n 800595c <HAL_ADC_Init+0xfc>
  2311. 8005884: 2800 cmp r0, #0
  2312. 8005886: d169 bne.n 800595c <HAL_ADC_Init+0xfc>
  2313. ADC_STATE_CLR_SET(hadc->State,
  2314. 8005888: 6aa2 ldr r2, [r4, #40] ; 0x28
  2315. ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) |
  2316. 800588a: 4937 ldr r1, [pc, #220] ; (8005968 <HAL_ADC_Init+0x108>)
  2317. ADC_STATE_CLR_SET(hadc->State,
  2318. 800588c: f422 5288 bic.w r2, r2, #4352 ; 0x1100
  2319. 8005890: f022 0202 bic.w r2, r2, #2
  2320. 8005894: f042 0202 orr.w r2, r2, #2
  2321. 8005898: 62a2 str r2, [r4, #40] ; 0x28
  2322. ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) |
  2323. 800589a: e894 0024 ldmia.w r4, {r2, r5}
  2324. 800589e: 428a cmp r2, r1
  2325. 80058a0: 69e1 ldr r1, [r4, #28]
  2326. 80058a2: d104 bne.n 80058ae <HAL_ADC_Init+0x4e>
  2327. 80058a4: f5b1 2f40 cmp.w r1, #786432 ; 0xc0000
  2328. 80058a8: bf08 it eq
  2329. 80058aa: f44f 2100 moveq.w r1, #524288 ; 0x80000
  2330. ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode) );
  2331. 80058ae: 68e6 ldr r6, [r4, #12]
  2332. ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) |
  2333. 80058b0: ea45 0546 orr.w r5, r5, r6, lsl #1
  2334. 80058b4: 4329 orrs r1, r5
  2335. tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode));
  2336. 80058b6: 68a5 ldr r5, [r4, #8]
  2337. 80058b8: f5b5 7f80 cmp.w r5, #256 ; 0x100
  2338. 80058bc: d035 beq.n 800592a <HAL_ADC_Init+0xca>
  2339. 80058be: 2d01 cmp r5, #1
  2340. 80058c0: bf08 it eq
  2341. 80058c2: f44f 7380 moveq.w r3, #256 ; 0x100
  2342. if (hadc->Init.DiscontinuousConvMode == ENABLE)
  2343. 80058c6: 6967 ldr r7, [r4, #20]
  2344. 80058c8: 2f01 cmp r7, #1
  2345. 80058ca: d106 bne.n 80058da <HAL_ADC_Init+0x7a>
  2346. if (hadc->Init.ContinuousConvMode == DISABLE)
  2347. 80058cc: bb7e cbnz r6, 800592e <HAL_ADC_Init+0xce>
  2348. SET_BIT(tmp_cr1, ADC_CR1_DISCEN |
  2349. 80058ce: 69a6 ldr r6, [r4, #24]
  2350. 80058d0: 3e01 subs r6, #1
  2351. 80058d2: ea43 3346 orr.w r3, r3, r6, lsl #13
  2352. 80058d6: f443 6300 orr.w r3, r3, #2048 ; 0x800
  2353. MODIFY_REG(hadc->Instance->CR1,
  2354. 80058da: 6856 ldr r6, [r2, #4]
  2355. if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE)
  2356. 80058dc: f5b5 7f80 cmp.w r5, #256 ; 0x100
  2357. MODIFY_REG(hadc->Instance->CR1,
  2358. 80058e0: f426 4669 bic.w r6, r6, #59648 ; 0xe900
  2359. 80058e4: ea43 0306 orr.w r3, r3, r6
  2360. 80058e8: 6053 str r3, [r2, #4]
  2361. MODIFY_REG(hadc->Instance->CR2,
  2362. 80058ea: 6896 ldr r6, [r2, #8]
  2363. 80058ec: 4b1f ldr r3, [pc, #124] ; (800596c <HAL_ADC_Init+0x10c>)
  2364. 80058ee: ea03 0306 and.w r3, r3, r6
  2365. 80058f2: ea43 0301 orr.w r3, r3, r1
  2366. 80058f6: 6093 str r3, [r2, #8]
  2367. if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE)
  2368. 80058f8: d001 beq.n 80058fe <HAL_ADC_Init+0x9e>
  2369. 80058fa: 2d01 cmp r5, #1
  2370. 80058fc: d120 bne.n 8005940 <HAL_ADC_Init+0xe0>
  2371. tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion);
  2372. 80058fe: 6923 ldr r3, [r4, #16]
  2373. 8005900: 3b01 subs r3, #1
  2374. 8005902: 051b lsls r3, r3, #20
  2375. MODIFY_REG(hadc->Instance->SQR1,
  2376. 8005904: 6ad5 ldr r5, [r2, #44] ; 0x2c
  2377. 8005906: f425 0570 bic.w r5, r5, #15728640 ; 0xf00000
  2378. 800590a: 432b orrs r3, r5
  2379. 800590c: 62d3 str r3, [r2, #44] ; 0x2c
  2380. if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
  2381. 800590e: 6892 ldr r2, [r2, #8]
  2382. 8005910: 4b17 ldr r3, [pc, #92] ; (8005970 <HAL_ADC_Init+0x110>)
  2383. 8005912: 4013 ands r3, r2
  2384. 8005914: 4299 cmp r1, r3
  2385. 8005916: d115 bne.n 8005944 <HAL_ADC_Init+0xe4>
  2386. ADC_CLEAR_ERRORCODE(hadc);
  2387. 8005918: 2300 movs r3, #0
  2388. 800591a: 62e3 str r3, [r4, #44] ; 0x2c
  2389. ADC_STATE_CLR_SET(hadc->State,
  2390. 800591c: 6aa3 ldr r3, [r4, #40] ; 0x28
  2391. 800591e: f023 0303 bic.w r3, r3, #3
  2392. 8005922: f043 0301 orr.w r3, r3, #1
  2393. 8005926: 62a3 str r3, [r4, #40] ; 0x28
  2394. 8005928: bdf8 pop {r3, r4, r5, r6, r7, pc}
  2395. tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode));
  2396. 800592a: 462b mov r3, r5
  2397. 800592c: e7cb b.n 80058c6 <HAL_ADC_Init+0x66>
  2398. SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
  2399. 800592e: 6aa6 ldr r6, [r4, #40] ; 0x28
  2400. 8005930: f046 0620 orr.w r6, r6, #32
  2401. 8005934: 62a6 str r6, [r4, #40] ; 0x28
  2402. SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
  2403. 8005936: 6ae6 ldr r6, [r4, #44] ; 0x2c
  2404. 8005938: f046 0601 orr.w r6, r6, #1
  2405. 800593c: 62e6 str r6, [r4, #44] ; 0x2c
  2406. 800593e: e7cc b.n 80058da <HAL_ADC_Init+0x7a>
  2407. uint32_t tmp_sqr1 = 0U;
  2408. 8005940: 2300 movs r3, #0
  2409. 8005942: e7df b.n 8005904 <HAL_ADC_Init+0xa4>
  2410. ADC_STATE_CLR_SET(hadc->State,
  2411. 8005944: 6aa3 ldr r3, [r4, #40] ; 0x28
  2412. 8005946: f023 0312 bic.w r3, r3, #18
  2413. 800594a: f043 0310 orr.w r3, r3, #16
  2414. 800594e: 62a3 str r3, [r4, #40] ; 0x28
  2415. SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
  2416. 8005950: 6ae3 ldr r3, [r4, #44] ; 0x2c
  2417. 8005952: f043 0301 orr.w r3, r3, #1
  2418. 8005956: 62e3 str r3, [r4, #44] ; 0x2c
  2419. return HAL_ERROR;
  2420. 8005958: 2001 movs r0, #1
  2421. }
  2422. 800595a: bdf8 pop {r3, r4, r5, r6, r7, pc}
  2423. SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
  2424. 800595c: 6aa3 ldr r3, [r4, #40] ; 0x28
  2425. 800595e: f043 0310 orr.w r3, r3, #16
  2426. 8005962: 62a3 str r3, [r4, #40] ; 0x28
  2427. 8005964: e7f8 b.n 8005958 <HAL_ADC_Init+0xf8>
  2428. 8005966: bf00 nop
  2429. 8005968: 40013c00 .word 0x40013c00
  2430. 800596c: ffe1f7fd .word 0xffe1f7fd
  2431. 8005970: ff1f0efe .word 0xff1f0efe
  2432. 08005974 <HAL_ADCEx_Calibration_Start>:
  2433. */
  2434. HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc)
  2435. {
  2436. HAL_StatusTypeDef tmp_hal_status = HAL_OK;
  2437. uint32_t tickstart;
  2438. __IO uint32_t wait_loop_index = 0U;
  2439. 8005974: 2300 movs r3, #0
  2440. {
  2441. 8005976: b573 push {r0, r1, r4, r5, r6, lr}
  2442. __IO uint32_t wait_loop_index = 0U;
  2443. 8005978: 9301 str r3, [sp, #4]
  2444. /* Check the parameters */
  2445. assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
  2446. /* Process locked */
  2447. __HAL_LOCK(hadc);
  2448. 800597a: f890 3024 ldrb.w r3, [r0, #36] ; 0x24
  2449. {
  2450. 800597e: 4604 mov r4, r0
  2451. __HAL_LOCK(hadc);
  2452. 8005980: 2b01 cmp r3, #1
  2453. 8005982: d05a beq.n 8005a3a <HAL_ADCEx_Calibration_Start+0xc6>
  2454. 8005984: 2301 movs r3, #1
  2455. 8005986: f880 3024 strb.w r3, [r0, #36] ; 0x24
  2456. /* 1. Calibration prerequisite: */
  2457. /* - ADC must be disabled for at least two ADC clock cycles in disable */
  2458. /* mode before ADC enable */
  2459. /* Stop potential conversion on going, on regular and injected groups */
  2460. /* Disable ADC peripheral */
  2461. tmp_hal_status = ADC_ConversionStop_Disable(hadc);
  2462. 800598a: f7ff ff47 bl 800581c <ADC_ConversionStop_Disable>
  2463. /* Check if ADC is effectively disabled */
  2464. if (tmp_hal_status == HAL_OK)
  2465. 800598e: 4605 mov r5, r0
  2466. 8005990: 2800 cmp r0, #0
  2467. 8005992: d132 bne.n 80059fa <HAL_ADCEx_Calibration_Start+0x86>
  2468. {
  2469. /* Set ADC state */
  2470. ADC_STATE_CLR_SET(hadc->State,
  2471. 8005994: 6aa3 ldr r3, [r4, #40] ; 0x28
  2472. /* Hardware prerequisite: delay before starting the calibration. */
  2473. /* - Computation of CPU clock cycles corresponding to ADC clock cycles. */
  2474. /* - Wait for the expected ADC clock cycles delay */
  2475. wait_loop_index = ((SystemCoreClock
  2476. / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC))
  2477. 8005996: 2002 movs r0, #2
  2478. ADC_STATE_CLR_SET(hadc->State,
  2479. 8005998: f423 5388 bic.w r3, r3, #4352 ; 0x1100
  2480. 800599c: f023 0302 bic.w r3, r3, #2
  2481. 80059a0: f043 0302 orr.w r3, r3, #2
  2482. 80059a4: 62a3 str r3, [r4, #40] ; 0x28
  2483. / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC))
  2484. 80059a6: 4b26 ldr r3, [pc, #152] ; (8005a40 <HAL_ADCEx_Calibration_Start+0xcc>)
  2485. 80059a8: 681e ldr r6, [r3, #0]
  2486. 80059aa: f000 ffaf bl 800690c <HAL_RCCEx_GetPeriphCLKFreq>
  2487. 80059ae: fbb6 f0f0 udiv r0, r6, r0
  2488. * ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES );
  2489. 80059b2: 0040 lsls r0, r0, #1
  2490. wait_loop_index = ((SystemCoreClock
  2491. 80059b4: 9001 str r0, [sp, #4]
  2492. while(wait_loop_index != 0U)
  2493. 80059b6: 9b01 ldr r3, [sp, #4]
  2494. 80059b8: bb1b cbnz r3, 8005a02 <HAL_ADCEx_Calibration_Start+0x8e>
  2495. {
  2496. wait_loop_index--;
  2497. }
  2498. /* 2. Enable the ADC peripheral */
  2499. ADC_Enable(hadc);
  2500. 80059ba: 4620 mov r0, r4
  2501. 80059bc: f7ff fe68 bl 8005690 <ADC_Enable>
  2502. /* 3. Resets ADC calibration registers */
  2503. SET_BIT(hadc->Instance->CR2, ADC_CR2_RSTCAL);
  2504. 80059c0: 6822 ldr r2, [r4, #0]
  2505. 80059c2: 6893 ldr r3, [r2, #8]
  2506. 80059c4: f043 0308 orr.w r3, r3, #8
  2507. 80059c8: 6093 str r3, [r2, #8]
  2508. tickstart = HAL_GetTick();
  2509. 80059ca: f7ff fd89 bl 80054e0 <HAL_GetTick>
  2510. 80059ce: 4606 mov r6, r0
  2511. /* Wait for calibration reset completion */
  2512. while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL))
  2513. 80059d0: 6823 ldr r3, [r4, #0]
  2514. 80059d2: 689a ldr r2, [r3, #8]
  2515. 80059d4: 0712 lsls r2, r2, #28
  2516. 80059d6: d418 bmi.n 8005a0a <HAL_ADCEx_Calibration_Start+0x96>
  2517. }
  2518. }
  2519. /* 4. Start ADC calibration */
  2520. SET_BIT(hadc->Instance->CR2, ADC_CR2_CAL);
  2521. 80059d8: 689a ldr r2, [r3, #8]
  2522. 80059da: f042 0204 orr.w r2, r2, #4
  2523. 80059de: 609a str r2, [r3, #8]
  2524. tickstart = HAL_GetTick();
  2525. 80059e0: f7ff fd7e bl 80054e0 <HAL_GetTick>
  2526. 80059e4: 4606 mov r6, r0
  2527. /* Wait for calibration completion */
  2528. while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL))
  2529. 80059e6: 6823 ldr r3, [r4, #0]
  2530. 80059e8: 689b ldr r3, [r3, #8]
  2531. 80059ea: 075b lsls r3, r3, #29
  2532. 80059ec: d41f bmi.n 8005a2e <HAL_ADCEx_Calibration_Start+0xba>
  2533. return HAL_ERROR;
  2534. }
  2535. }
  2536. /* Set ADC state */
  2537. ADC_STATE_CLR_SET(hadc->State,
  2538. 80059ee: 6aa3 ldr r3, [r4, #40] ; 0x28
  2539. 80059f0: f023 0303 bic.w r3, r3, #3
  2540. 80059f4: f043 0301 orr.w r3, r3, #1
  2541. 80059f8: 62a3 str r3, [r4, #40] ; 0x28
  2542. HAL_ADC_STATE_BUSY_INTERNAL,
  2543. HAL_ADC_STATE_READY);
  2544. }
  2545. /* Process unlocked */
  2546. __HAL_UNLOCK(hadc);
  2547. 80059fa: 2300 movs r3, #0
  2548. 80059fc: f884 3024 strb.w r3, [r4, #36] ; 0x24
  2549. /* Return function status */
  2550. return tmp_hal_status;
  2551. 8005a00: e012 b.n 8005a28 <HAL_ADCEx_Calibration_Start+0xb4>
  2552. wait_loop_index--;
  2553. 8005a02: 9b01 ldr r3, [sp, #4]
  2554. 8005a04: 3b01 subs r3, #1
  2555. 8005a06: 9301 str r3, [sp, #4]
  2556. 8005a08: e7d5 b.n 80059b6 <HAL_ADCEx_Calibration_Start+0x42>
  2557. if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
  2558. 8005a0a: f7ff fd69 bl 80054e0 <HAL_GetTick>
  2559. 8005a0e: 1b80 subs r0, r0, r6
  2560. 8005a10: 280a cmp r0, #10
  2561. 8005a12: d9dd bls.n 80059d0 <HAL_ADCEx_Calibration_Start+0x5c>
  2562. ADC_STATE_CLR_SET(hadc->State,
  2563. 8005a14: 6aa3 ldr r3, [r4, #40] ; 0x28
  2564. return HAL_ERROR;
  2565. 8005a16: 2501 movs r5, #1
  2566. ADC_STATE_CLR_SET(hadc->State,
  2567. 8005a18: f023 0312 bic.w r3, r3, #18
  2568. 8005a1c: f043 0310 orr.w r3, r3, #16
  2569. 8005a20: 62a3 str r3, [r4, #40] ; 0x28
  2570. __HAL_UNLOCK(hadc);
  2571. 8005a22: 2300 movs r3, #0
  2572. 8005a24: f884 3024 strb.w r3, [r4, #36] ; 0x24
  2573. }
  2574. 8005a28: 4628 mov r0, r5
  2575. 8005a2a: b002 add sp, #8
  2576. 8005a2c: bd70 pop {r4, r5, r6, pc}
  2577. if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
  2578. 8005a2e: f7ff fd57 bl 80054e0 <HAL_GetTick>
  2579. 8005a32: 1b80 subs r0, r0, r6
  2580. 8005a34: 280a cmp r0, #10
  2581. 8005a36: d9d6 bls.n 80059e6 <HAL_ADCEx_Calibration_Start+0x72>
  2582. 8005a38: e7ec b.n 8005a14 <HAL_ADCEx_Calibration_Start+0xa0>
  2583. __HAL_LOCK(hadc);
  2584. 8005a3a: 2502 movs r5, #2
  2585. 8005a3c: e7f4 b.n 8005a28 <HAL_ADCEx_Calibration_Start+0xb4>
  2586. 8005a3e: bf00 nop
  2587. 8005a40: 20000200 .word 0x20000200
  2588. 08005a44 <HAL_NVIC_SetPriorityGrouping>:
  2589. __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
  2590. {
  2591. uint32_t reg_value;
  2592. uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
  2593. reg_value = SCB->AIRCR; /* read old register configuration */
  2594. 8005a44: 4a07 ldr r2, [pc, #28] ; (8005a64 <HAL_NVIC_SetPriorityGrouping+0x20>)
  2595. reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
  2596. reg_value = (reg_value |
  2597. ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
  2598. (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
  2599. 8005a46: 0200 lsls r0, r0, #8
  2600. reg_value = SCB->AIRCR; /* read old register configuration */
  2601. 8005a48: 68d3 ldr r3, [r2, #12]
  2602. (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
  2603. 8005a4a: f400 60e0 and.w r0, r0, #1792 ; 0x700
  2604. reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
  2605. 8005a4e: f423 63e0 bic.w r3, r3, #1792 ; 0x700
  2606. 8005a52: 041b lsls r3, r3, #16
  2607. 8005a54: 0c1b lsrs r3, r3, #16
  2608. 8005a56: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000
  2609. 8005a5a: f443 3300 orr.w r3, r3, #131072 ; 0x20000
  2610. reg_value = (reg_value |
  2611. 8005a5e: 4303 orrs r3, r0
  2612. SCB->AIRCR = reg_value;
  2613. 8005a60: 60d3 str r3, [r2, #12]
  2614. 8005a62: 4770 bx lr
  2615. 8005a64: e000ed00 .word 0xe000ed00
  2616. 08005a68 <HAL_NVIC_SetPriority>:
  2617. \details Reads the priority grouping field from the NVIC Interrupt Controller.
  2618. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
  2619. */
  2620. __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
  2621. {
  2622. return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
  2623. 8005a68: 4b17 ldr r3, [pc, #92] ; (8005ac8 <HAL_NVIC_SetPriority+0x60>)
  2624. * This parameter can be a value between 0 and 15
  2625. * A lower priority value indicates a higher priority.
  2626. * @retval None
  2627. */
  2628. void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
  2629. {
  2630. 8005a6a: b530 push {r4, r5, lr}
  2631. 8005a6c: 68dc ldr r4, [r3, #12]
  2632. 8005a6e: f3c4 2402 ubfx r4, r4, #8, #3
  2633. {
  2634. uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
  2635. uint32_t PreemptPriorityBits;
  2636. uint32_t SubPriorityBits;
  2637. PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
  2638. 8005a72: f1c4 0307 rsb r3, r4, #7
  2639. SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
  2640. 8005a76: 1d25 adds r5, r4, #4
  2641. PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
  2642. 8005a78: 2b04 cmp r3, #4
  2643. 8005a7a: bf28 it cs
  2644. 8005a7c: 2304 movcs r3, #4
  2645. SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
  2646. 8005a7e: 2d06 cmp r5, #6
  2647. return (
  2648. ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
  2649. 8005a80: f04f 0501 mov.w r5, #1
  2650. SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
  2651. 8005a84: bf98 it ls
  2652. 8005a86: 2400 movls r4, #0
  2653. ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
  2654. 8005a88: fa05 f303 lsl.w r3, r5, r3
  2655. 8005a8c: f103 33ff add.w r3, r3, #4294967295
  2656. SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
  2657. 8005a90: bf88 it hi
  2658. 8005a92: 3c03 subhi r4, #3
  2659. ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
  2660. 8005a94: 4019 ands r1, r3
  2661. 8005a96: 40a1 lsls r1, r4
  2662. ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
  2663. 8005a98: fa05 f404 lsl.w r4, r5, r4
  2664. 8005a9c: 3c01 subs r4, #1
  2665. 8005a9e: 4022 ands r2, r4
  2666. if ((int32_t)(IRQn) < 0)
  2667. 8005aa0: 2800 cmp r0, #0
  2668. ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
  2669. 8005aa2: ea42 0201 orr.w r2, r2, r1
  2670. 8005aa6: ea4f 1202 mov.w r2, r2, lsl #4
  2671. NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
  2672. 8005aaa: bfaf iteee ge
  2673. 8005aac: f100 4060 addge.w r0, r0, #3758096384 ; 0xe0000000
  2674. SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
  2675. 8005ab0: 4b06 ldrlt r3, [pc, #24] ; (8005acc <HAL_NVIC_SetPriority+0x64>)
  2676. 8005ab2: f000 000f andlt.w r0, r0, #15
  2677. 8005ab6: b2d2 uxtblt r2, r2
  2678. NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
  2679. 8005ab8: bfa5 ittet ge
  2680. 8005aba: b2d2 uxtbge r2, r2
  2681. 8005abc: f500 4061 addge.w r0, r0, #57600 ; 0xe100
  2682. SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
  2683. 8005ac0: 541a strblt r2, [r3, r0]
  2684. NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
  2685. 8005ac2: f880 2300 strbge.w r2, [r0, #768] ; 0x300
  2686. 8005ac6: bd30 pop {r4, r5, pc}
  2687. 8005ac8: e000ed00 .word 0xe000ed00
  2688. 8005acc: e000ed14 .word 0xe000ed14
  2689. 08005ad0 <HAL_NVIC_EnableIRQ>:
  2690. NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
  2691. 8005ad0: 2301 movs r3, #1
  2692. 8005ad2: 0942 lsrs r2, r0, #5
  2693. 8005ad4: f000 001f and.w r0, r0, #31
  2694. 8005ad8: fa03 f000 lsl.w r0, r3, r0
  2695. 8005adc: 4b01 ldr r3, [pc, #4] ; (8005ae4 <HAL_NVIC_EnableIRQ+0x14>)
  2696. 8005ade: f843 0022 str.w r0, [r3, r2, lsl #2]
  2697. 8005ae2: 4770 bx lr
  2698. 8005ae4: e000e100 .word 0xe000e100
  2699. 08005ae8 <HAL_SYSTICK_Config>:
  2700. function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
  2701. must contain a vendor-specific implementation of this function.
  2702. */
  2703. __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
  2704. {
  2705. if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
  2706. 8005ae8: 3801 subs r0, #1
  2707. 8005aea: f1b0 7f80 cmp.w r0, #16777216 ; 0x1000000
  2708. 8005aee: d20a bcs.n 8005b06 <HAL_SYSTICK_Config+0x1e>
  2709. SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
  2710. 8005af0: 21f0 movs r1, #240 ; 0xf0
  2711. {
  2712. return (1UL); /* Reload value impossible */
  2713. }
  2714. SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
  2715. 8005af2: 4b06 ldr r3, [pc, #24] ; (8005b0c <HAL_SYSTICK_Config+0x24>)
  2716. SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
  2717. 8005af4: 4a06 ldr r2, [pc, #24] ; (8005b10 <HAL_SYSTICK_Config+0x28>)
  2718. SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
  2719. 8005af6: 6058 str r0, [r3, #4]
  2720. SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
  2721. 8005af8: f882 1023 strb.w r1, [r2, #35] ; 0x23
  2722. NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
  2723. SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
  2724. 8005afc: 2000 movs r0, #0
  2725. SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
  2726. 8005afe: 2207 movs r2, #7
  2727. SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
  2728. 8005b00: 6098 str r0, [r3, #8]
  2729. SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
  2730. 8005b02: 601a str r2, [r3, #0]
  2731. 8005b04: 4770 bx lr
  2732. return (1UL); /* Reload value impossible */
  2733. 8005b06: 2001 movs r0, #1
  2734. * - 1 Function failed.
  2735. */
  2736. uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
  2737. {
  2738. return SysTick_Config(TicksNumb);
  2739. }
  2740. 8005b08: 4770 bx lr
  2741. 8005b0a: bf00 nop
  2742. 8005b0c: e000e010 .word 0xe000e010
  2743. 8005b10: e000ed00 .word 0xe000ed00
  2744. 08005b14 <HAL_DMA_Init>:
  2745. * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
  2746. * the configuration information for the specified DMA Channel.
  2747. * @retval HAL status
  2748. */
  2749. HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
  2750. {
  2751. 8005b14: b510 push {r4, lr}
  2752. uint32_t tmp = 0U;
  2753. /* Check the DMA handle allocation */
  2754. if(hdma == NULL)
  2755. 8005b16: 2800 cmp r0, #0
  2756. 8005b18: d032 beq.n 8005b80 <HAL_DMA_Init+0x6c>
  2757. assert_param(IS_DMA_MODE(hdma->Init.Mode));
  2758. assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
  2759. #if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F100xE) || defined (STM32F105xC) || defined (STM32F107xC)
  2760. /* calculation of the channel index */
  2761. if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
  2762. 8005b1a: 6801 ldr r1, [r0, #0]
  2763. 8005b1c: 4b19 ldr r3, [pc, #100] ; (8005b84 <HAL_DMA_Init+0x70>)
  2764. 8005b1e: 2414 movs r4, #20
  2765. 8005b20: 4299 cmp r1, r3
  2766. 8005b22: d825 bhi.n 8005b70 <HAL_DMA_Init+0x5c>
  2767. {
  2768. /* DMA1 */
  2769. hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
  2770. 8005b24: 4a18 ldr r2, [pc, #96] ; (8005b88 <HAL_DMA_Init+0x74>)
  2771. hdma->DmaBaseAddress = DMA1;
  2772. 8005b26: f2a3 4307 subw r3, r3, #1031 ; 0x407
  2773. hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
  2774. 8005b2a: 440a add r2, r1
  2775. 8005b2c: fbb2 f2f4 udiv r2, r2, r4
  2776. 8005b30: 0092 lsls r2, r2, #2
  2777. 8005b32: 6402 str r2, [r0, #64] ; 0x40
  2778. tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
  2779. DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
  2780. DMA_CCR_DIR));
  2781. /* Prepare the DMA Channel configuration */
  2782. tmp |= hdma->Init.Direction |
  2783. 8005b34: 6884 ldr r4, [r0, #8]
  2784. hdma->DmaBaseAddress = DMA2;
  2785. 8005b36: 63c3 str r3, [r0, #60] ; 0x3c
  2786. tmp |= hdma->Init.Direction |
  2787. 8005b38: 6843 ldr r3, [r0, #4]
  2788. tmp = hdma->Instance->CCR;
  2789. 8005b3a: 680a ldr r2, [r1, #0]
  2790. tmp |= hdma->Init.Direction |
  2791. 8005b3c: 4323 orrs r3, r4
  2792. hdma->Init.PeriphInc | hdma->Init.MemInc |
  2793. 8005b3e: 68c4 ldr r4, [r0, #12]
  2794. tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
  2795. 8005b40: f422 527f bic.w r2, r2, #16320 ; 0x3fc0
  2796. hdma->Init.PeriphInc | hdma->Init.MemInc |
  2797. 8005b44: 4323 orrs r3, r4
  2798. 8005b46: 6904 ldr r4, [r0, #16]
  2799. tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
  2800. 8005b48: f022 0230 bic.w r2, r2, #48 ; 0x30
  2801. hdma->Init.PeriphInc | hdma->Init.MemInc |
  2802. 8005b4c: 4323 orrs r3, r4
  2803. hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
  2804. 8005b4e: 6944 ldr r4, [r0, #20]
  2805. 8005b50: 4323 orrs r3, r4
  2806. 8005b52: 6984 ldr r4, [r0, #24]
  2807. 8005b54: 4323 orrs r3, r4
  2808. hdma->Init.Mode | hdma->Init.Priority;
  2809. 8005b56: 69c4 ldr r4, [r0, #28]
  2810. 8005b58: 4323 orrs r3, r4
  2811. tmp |= hdma->Init.Direction |
  2812. 8005b5a: 4313 orrs r3, r2
  2813. /* Write to DMA Channel CR register */
  2814. hdma->Instance->CCR = tmp;
  2815. 8005b5c: 600b str r3, [r1, #0]
  2816. /* Initialise the error code */
  2817. hdma->ErrorCode = HAL_DMA_ERROR_NONE;
  2818. /* Initialize the DMA state*/
  2819. hdma->State = HAL_DMA_STATE_READY;
  2820. 8005b5e: 2201 movs r2, #1
  2821. hdma->ErrorCode = HAL_DMA_ERROR_NONE;
  2822. 8005b60: 2300 movs r3, #0
  2823. hdma->State = HAL_DMA_STATE_READY;
  2824. 8005b62: f880 2021 strb.w r2, [r0, #33] ; 0x21
  2825. hdma->ErrorCode = HAL_DMA_ERROR_NONE;
  2826. 8005b66: 6383 str r3, [r0, #56] ; 0x38
  2827. /* Allocate lock resource and initialize it */
  2828. hdma->Lock = HAL_UNLOCKED;
  2829. 8005b68: f880 3020 strb.w r3, [r0, #32]
  2830. return HAL_OK;
  2831. 8005b6c: 4618 mov r0, r3
  2832. 8005b6e: bd10 pop {r4, pc}
  2833. hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
  2834. 8005b70: 4b06 ldr r3, [pc, #24] ; (8005b8c <HAL_DMA_Init+0x78>)
  2835. 8005b72: 440b add r3, r1
  2836. 8005b74: fbb3 f3f4 udiv r3, r3, r4
  2837. 8005b78: 009b lsls r3, r3, #2
  2838. 8005b7a: 6403 str r3, [r0, #64] ; 0x40
  2839. hdma->DmaBaseAddress = DMA2;
  2840. 8005b7c: 4b04 ldr r3, [pc, #16] ; (8005b90 <HAL_DMA_Init+0x7c>)
  2841. 8005b7e: e7d9 b.n 8005b34 <HAL_DMA_Init+0x20>
  2842. return HAL_ERROR;
  2843. 8005b80: 2001 movs r0, #1
  2844. }
  2845. 8005b82: bd10 pop {r4, pc}
  2846. 8005b84: 40020407 .word 0x40020407
  2847. 8005b88: bffdfff8 .word 0xbffdfff8
  2848. 8005b8c: bffdfbf8 .word 0xbffdfbf8
  2849. 8005b90: 40020400 .word 0x40020400
  2850. 08005b94 <HAL_DMA_Start_IT>:
  2851. * @param DstAddress: The destination memory Buffer address
  2852. * @param DataLength: The length of data to be transferred from source to destination
  2853. * @retval HAL status
  2854. */
  2855. HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
  2856. {
  2857. 8005b94: b5f0 push {r4, r5, r6, r7, lr}
  2858. /* Check the parameters */
  2859. assert_param(IS_DMA_BUFFER_SIZE(DataLength));
  2860. /* Process locked */
  2861. __HAL_LOCK(hdma);
  2862. 8005b96: f890 4020 ldrb.w r4, [r0, #32]
  2863. 8005b9a: 2c01 cmp r4, #1
  2864. 8005b9c: d035 beq.n 8005c0a <HAL_DMA_Start_IT+0x76>
  2865. 8005b9e: 2401 movs r4, #1
  2866. if(HAL_DMA_STATE_READY == hdma->State)
  2867. 8005ba0: f890 5021 ldrb.w r5, [r0, #33] ; 0x21
  2868. __HAL_LOCK(hdma);
  2869. 8005ba4: f880 4020 strb.w r4, [r0, #32]
  2870. if(HAL_DMA_STATE_READY == hdma->State)
  2871. 8005ba8: 42a5 cmp r5, r4
  2872. 8005baa: f04f 0600 mov.w r6, #0
  2873. 8005bae: f04f 0402 mov.w r4, #2
  2874. 8005bb2: d128 bne.n 8005c06 <HAL_DMA_Start_IT+0x72>
  2875. {
  2876. /* Change DMA peripheral state */
  2877. hdma->State = HAL_DMA_STATE_BUSY;
  2878. 8005bb4: f880 4021 strb.w r4, [r0, #33] ; 0x21
  2879. hdma->ErrorCode = HAL_DMA_ERROR_NONE;
  2880. /* Disable the peripheral */
  2881. __HAL_DMA_DISABLE(hdma);
  2882. 8005bb8: 6804 ldr r4, [r0, #0]
  2883. hdma->ErrorCode = HAL_DMA_ERROR_NONE;
  2884. 8005bba: 6386 str r6, [r0, #56] ; 0x38
  2885. __HAL_DMA_DISABLE(hdma);
  2886. 8005bbc: 6826 ldr r6, [r4, #0]
  2887. * @retval HAL status
  2888. */
  2889. static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
  2890. {
  2891. /* Clear all flags */
  2892. hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
  2893. 8005bbe: 6c07 ldr r7, [r0, #64] ; 0x40
  2894. __HAL_DMA_DISABLE(hdma);
  2895. 8005bc0: f026 0601 bic.w r6, r6, #1
  2896. 8005bc4: 6026 str r6, [r4, #0]
  2897. hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
  2898. 8005bc6: 6bc6 ldr r6, [r0, #60] ; 0x3c
  2899. 8005bc8: 40bd lsls r5, r7
  2900. 8005bca: 6075 str r5, [r6, #4]
  2901. /* Configure DMA Channel data length */
  2902. hdma->Instance->CNDTR = DataLength;
  2903. 8005bcc: 6063 str r3, [r4, #4]
  2904. /* Memory to Peripheral */
  2905. if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
  2906. 8005bce: 6843 ldr r3, [r0, #4]
  2907. 8005bd0: 6805 ldr r5, [r0, #0]
  2908. 8005bd2: 2b10 cmp r3, #16
  2909. if(NULL != hdma->XferHalfCpltCallback)
  2910. 8005bd4: 6ac3 ldr r3, [r0, #44] ; 0x2c
  2911. {
  2912. /* Configure DMA Channel destination address */
  2913. hdma->Instance->CPAR = DstAddress;
  2914. 8005bd6: bf0b itete eq
  2915. 8005bd8: 60a2 streq r2, [r4, #8]
  2916. }
  2917. /* Peripheral to Memory */
  2918. else
  2919. {
  2920. /* Configure DMA Channel source address */
  2921. hdma->Instance->CPAR = SrcAddress;
  2922. 8005bda: 60a1 strne r1, [r4, #8]
  2923. hdma->Instance->CMAR = SrcAddress;
  2924. 8005bdc: 60e1 streq r1, [r4, #12]
  2925. /* Configure DMA Channel destination address */
  2926. hdma->Instance->CMAR = DstAddress;
  2927. 8005bde: 60e2 strne r2, [r4, #12]
  2928. if(NULL != hdma->XferHalfCpltCallback)
  2929. 8005be0: b14b cbz r3, 8005bf6 <HAL_DMA_Start_IT+0x62>
  2930. __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
  2931. 8005be2: 6823 ldr r3, [r4, #0]
  2932. 8005be4: f043 030e orr.w r3, r3, #14
  2933. __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
  2934. 8005be8: 6023 str r3, [r4, #0]
  2935. __HAL_DMA_ENABLE(hdma);
  2936. 8005bea: 682b ldr r3, [r5, #0]
  2937. HAL_StatusTypeDef status = HAL_OK;
  2938. 8005bec: 2000 movs r0, #0
  2939. __HAL_DMA_ENABLE(hdma);
  2940. 8005bee: f043 0301 orr.w r3, r3, #1
  2941. 8005bf2: 602b str r3, [r5, #0]
  2942. 8005bf4: bdf0 pop {r4, r5, r6, r7, pc}
  2943. __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
  2944. 8005bf6: 6823 ldr r3, [r4, #0]
  2945. 8005bf8: f023 0304 bic.w r3, r3, #4
  2946. 8005bfc: 6023 str r3, [r4, #0]
  2947. __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
  2948. 8005bfe: 6823 ldr r3, [r4, #0]
  2949. 8005c00: f043 030a orr.w r3, r3, #10
  2950. 8005c04: e7f0 b.n 8005be8 <HAL_DMA_Start_IT+0x54>
  2951. __HAL_UNLOCK(hdma);
  2952. 8005c06: f880 6020 strb.w r6, [r0, #32]
  2953. __HAL_LOCK(hdma);
  2954. 8005c0a: 2002 movs r0, #2
  2955. }
  2956. 8005c0c: bdf0 pop {r4, r5, r6, r7, pc}
  2957. ...
  2958. 08005c10 <HAL_DMA_Abort_IT>:
  2959. if(HAL_DMA_STATE_BUSY != hdma->State)
  2960. 8005c10: f890 3021 ldrb.w r3, [r0, #33] ; 0x21
  2961. {
  2962. 8005c14: b510 push {r4, lr}
  2963. if(HAL_DMA_STATE_BUSY != hdma->State)
  2964. 8005c16: 2b02 cmp r3, #2
  2965. 8005c18: d003 beq.n 8005c22 <HAL_DMA_Abort_IT+0x12>
  2966. hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
  2967. 8005c1a: 2304 movs r3, #4
  2968. 8005c1c: 6383 str r3, [r0, #56] ; 0x38
  2969. status = HAL_ERROR;
  2970. 8005c1e: 2001 movs r0, #1
  2971. 8005c20: bd10 pop {r4, pc}
  2972. __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
  2973. 8005c22: 6803 ldr r3, [r0, #0]
  2974. 8005c24: 681a ldr r2, [r3, #0]
  2975. 8005c26: f022 020e bic.w r2, r2, #14
  2976. 8005c2a: 601a str r2, [r3, #0]
  2977. __HAL_DMA_DISABLE(hdma);
  2978. 8005c2c: 681a ldr r2, [r3, #0]
  2979. 8005c2e: f022 0201 bic.w r2, r2, #1
  2980. 8005c32: 601a str r2, [r3, #0]
  2981. __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma));
  2982. 8005c34: 4a29 ldr r2, [pc, #164] ; (8005cdc <HAL_DMA_Abort_IT+0xcc>)
  2983. 8005c36: 4293 cmp r3, r2
  2984. 8005c38: d924 bls.n 8005c84 <HAL_DMA_Abort_IT+0x74>
  2985. 8005c3a: f502 7262 add.w r2, r2, #904 ; 0x388
  2986. 8005c3e: 4293 cmp r3, r2
  2987. 8005c40: d019 beq.n 8005c76 <HAL_DMA_Abort_IT+0x66>
  2988. 8005c42: 3214 adds r2, #20
  2989. 8005c44: 4293 cmp r3, r2
  2990. 8005c46: d018 beq.n 8005c7a <HAL_DMA_Abort_IT+0x6a>
  2991. 8005c48: 3214 adds r2, #20
  2992. 8005c4a: 4293 cmp r3, r2
  2993. 8005c4c: d017 beq.n 8005c7e <HAL_DMA_Abort_IT+0x6e>
  2994. 8005c4e: 3214 adds r2, #20
  2995. 8005c50: 4293 cmp r3, r2
  2996. 8005c52: bf0c ite eq
  2997. 8005c54: f44f 5380 moveq.w r3, #4096 ; 0x1000
  2998. 8005c58: f44f 3380 movne.w r3, #65536 ; 0x10000
  2999. 8005c5c: 4a20 ldr r2, [pc, #128] ; (8005ce0 <HAL_DMA_Abort_IT+0xd0>)
  3000. 8005c5e: 6053 str r3, [r2, #4]
  3001. hdma->State = HAL_DMA_STATE_READY;
  3002. 8005c60: 2301 movs r3, #1
  3003. __HAL_UNLOCK(hdma);
  3004. 8005c62: 2400 movs r4, #0
  3005. hdma->State = HAL_DMA_STATE_READY;
  3006. 8005c64: f880 3021 strb.w r3, [r0, #33] ; 0x21
  3007. if(hdma->XferAbortCallback != NULL)
  3008. 8005c68: 6b43 ldr r3, [r0, #52] ; 0x34
  3009. __HAL_UNLOCK(hdma);
  3010. 8005c6a: f880 4020 strb.w r4, [r0, #32]
  3011. if(hdma->XferAbortCallback != NULL)
  3012. 8005c6e: b39b cbz r3, 8005cd8 <HAL_DMA_Abort_IT+0xc8>
  3013. hdma->XferAbortCallback(hdma);
  3014. 8005c70: 4798 blx r3
  3015. HAL_StatusTypeDef status = HAL_OK;
  3016. 8005c72: 4620 mov r0, r4
  3017. 8005c74: bd10 pop {r4, pc}
  3018. __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma));
  3019. 8005c76: 2301 movs r3, #1
  3020. 8005c78: e7f0 b.n 8005c5c <HAL_DMA_Abort_IT+0x4c>
  3021. 8005c7a: 2310 movs r3, #16
  3022. 8005c7c: e7ee b.n 8005c5c <HAL_DMA_Abort_IT+0x4c>
  3023. 8005c7e: f44f 7380 mov.w r3, #256 ; 0x100
  3024. 8005c82: e7eb b.n 8005c5c <HAL_DMA_Abort_IT+0x4c>
  3025. 8005c84: 4917 ldr r1, [pc, #92] ; (8005ce4 <HAL_DMA_Abort_IT+0xd4>)
  3026. 8005c86: 428b cmp r3, r1
  3027. 8005c88: d016 beq.n 8005cb8 <HAL_DMA_Abort_IT+0xa8>
  3028. 8005c8a: 3114 adds r1, #20
  3029. 8005c8c: 428b cmp r3, r1
  3030. 8005c8e: d015 beq.n 8005cbc <HAL_DMA_Abort_IT+0xac>
  3031. 8005c90: 3114 adds r1, #20
  3032. 8005c92: 428b cmp r3, r1
  3033. 8005c94: d014 beq.n 8005cc0 <HAL_DMA_Abort_IT+0xb0>
  3034. 8005c96: 3114 adds r1, #20
  3035. 8005c98: 428b cmp r3, r1
  3036. 8005c9a: d014 beq.n 8005cc6 <HAL_DMA_Abort_IT+0xb6>
  3037. 8005c9c: 3114 adds r1, #20
  3038. 8005c9e: 428b cmp r3, r1
  3039. 8005ca0: d014 beq.n 8005ccc <HAL_DMA_Abort_IT+0xbc>
  3040. 8005ca2: 3114 adds r1, #20
  3041. 8005ca4: 428b cmp r3, r1
  3042. 8005ca6: d014 beq.n 8005cd2 <HAL_DMA_Abort_IT+0xc2>
  3043. 8005ca8: 4293 cmp r3, r2
  3044. 8005caa: bf14 ite ne
  3045. 8005cac: f44f 3380 movne.w r3, #65536 ; 0x10000
  3046. 8005cb0: f04f 7380 moveq.w r3, #16777216 ; 0x1000000
  3047. 8005cb4: 4a0c ldr r2, [pc, #48] ; (8005ce8 <HAL_DMA_Abort_IT+0xd8>)
  3048. 8005cb6: e7d2 b.n 8005c5e <HAL_DMA_Abort_IT+0x4e>
  3049. 8005cb8: 2301 movs r3, #1
  3050. 8005cba: e7fb b.n 8005cb4 <HAL_DMA_Abort_IT+0xa4>
  3051. 8005cbc: 2310 movs r3, #16
  3052. 8005cbe: e7f9 b.n 8005cb4 <HAL_DMA_Abort_IT+0xa4>
  3053. 8005cc0: f44f 7380 mov.w r3, #256 ; 0x100
  3054. 8005cc4: e7f6 b.n 8005cb4 <HAL_DMA_Abort_IT+0xa4>
  3055. 8005cc6: f44f 5380 mov.w r3, #4096 ; 0x1000
  3056. 8005cca: e7f3 b.n 8005cb4 <HAL_DMA_Abort_IT+0xa4>
  3057. 8005ccc: f44f 3380 mov.w r3, #65536 ; 0x10000
  3058. 8005cd0: e7f0 b.n 8005cb4 <HAL_DMA_Abort_IT+0xa4>
  3059. 8005cd2: f44f 1380 mov.w r3, #1048576 ; 0x100000
  3060. 8005cd6: e7ed b.n 8005cb4 <HAL_DMA_Abort_IT+0xa4>
  3061. HAL_StatusTypeDef status = HAL_OK;
  3062. 8005cd8: 4618 mov r0, r3
  3063. }
  3064. 8005cda: bd10 pop {r4, pc}
  3065. 8005cdc: 40020080 .word 0x40020080
  3066. 8005ce0: 40020400 .word 0x40020400
  3067. 8005ce4: 40020008 .word 0x40020008
  3068. 8005ce8: 40020000 .word 0x40020000
  3069. 08005cec <HAL_DMA_IRQHandler>:
  3070. {
  3071. 8005cec: b470 push {r4, r5, r6}
  3072. if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET))
  3073. 8005cee: 2504 movs r5, #4
  3074. uint32_t flag_it = hdma->DmaBaseAddress->ISR;
  3075. 8005cf0: 6bc6 ldr r6, [r0, #60] ; 0x3c
  3076. if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET))
  3077. 8005cf2: 6c02 ldr r2, [r0, #64] ; 0x40
  3078. uint32_t flag_it = hdma->DmaBaseAddress->ISR;
  3079. 8005cf4: 6834 ldr r4, [r6, #0]
  3080. uint32_t source_it = hdma->Instance->CCR;
  3081. 8005cf6: 6803 ldr r3, [r0, #0]
  3082. if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET))
  3083. 8005cf8: 4095 lsls r5, r2
  3084. 8005cfa: 4225 tst r5, r4
  3085. uint32_t source_it = hdma->Instance->CCR;
  3086. 8005cfc: 6819 ldr r1, [r3, #0]
  3087. if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET))
  3088. 8005cfe: d055 beq.n 8005dac <HAL_DMA_IRQHandler+0xc0>
  3089. 8005d00: 074d lsls r5, r1, #29
  3090. 8005d02: d553 bpl.n 8005dac <HAL_DMA_IRQHandler+0xc0>
  3091. if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
  3092. 8005d04: 681a ldr r2, [r3, #0]
  3093. 8005d06: 0696 lsls r6, r2, #26
  3094. __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
  3095. 8005d08: bf5e ittt pl
  3096. 8005d0a: 681a ldrpl r2, [r3, #0]
  3097. 8005d0c: f022 0204 bicpl.w r2, r2, #4
  3098. 8005d10: 601a strpl r2, [r3, #0]
  3099. __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
  3100. 8005d12: 4a60 ldr r2, [pc, #384] ; (8005e94 <HAL_DMA_IRQHandler+0x1a8>)
  3101. 8005d14: 4293 cmp r3, r2
  3102. 8005d16: d91f bls.n 8005d58 <HAL_DMA_IRQHandler+0x6c>
  3103. 8005d18: f502 7262 add.w r2, r2, #904 ; 0x388
  3104. 8005d1c: 4293 cmp r3, r2
  3105. 8005d1e: d014 beq.n 8005d4a <HAL_DMA_IRQHandler+0x5e>
  3106. 8005d20: 3214 adds r2, #20
  3107. 8005d22: 4293 cmp r3, r2
  3108. 8005d24: d013 beq.n 8005d4e <HAL_DMA_IRQHandler+0x62>
  3109. 8005d26: 3214 adds r2, #20
  3110. 8005d28: 4293 cmp r3, r2
  3111. 8005d2a: d012 beq.n 8005d52 <HAL_DMA_IRQHandler+0x66>
  3112. 8005d2c: 3214 adds r2, #20
  3113. 8005d2e: 4293 cmp r3, r2
  3114. 8005d30: bf0c ite eq
  3115. 8005d32: f44f 4380 moveq.w r3, #16384 ; 0x4000
  3116. 8005d36: f44f 2380 movne.w r3, #262144 ; 0x40000
  3117. 8005d3a: 4a57 ldr r2, [pc, #348] ; (8005e98 <HAL_DMA_IRQHandler+0x1ac>)
  3118. 8005d3c: 6053 str r3, [r2, #4]
  3119. if(hdma->XferHalfCpltCallback != NULL)
  3120. 8005d3e: 6ac3 ldr r3, [r0, #44] ; 0x2c
  3121. if (hdma->XferErrorCallback != NULL)
  3122. 8005d40: 2b00 cmp r3, #0
  3123. 8005d42: f000 80a5 beq.w 8005e90 <HAL_DMA_IRQHandler+0x1a4>
  3124. }
  3125. 8005d46: bc70 pop {r4, r5, r6}
  3126. hdma->XferErrorCallback(hdma);
  3127. 8005d48: 4718 bx r3
  3128. __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
  3129. 8005d4a: 2304 movs r3, #4
  3130. 8005d4c: e7f5 b.n 8005d3a <HAL_DMA_IRQHandler+0x4e>
  3131. 8005d4e: 2340 movs r3, #64 ; 0x40
  3132. 8005d50: e7f3 b.n 8005d3a <HAL_DMA_IRQHandler+0x4e>
  3133. 8005d52: f44f 6380 mov.w r3, #1024 ; 0x400
  3134. 8005d56: e7f0 b.n 8005d3a <HAL_DMA_IRQHandler+0x4e>
  3135. 8005d58: 4950 ldr r1, [pc, #320] ; (8005e9c <HAL_DMA_IRQHandler+0x1b0>)
  3136. 8005d5a: 428b cmp r3, r1
  3137. 8005d5c: d016 beq.n 8005d8c <HAL_DMA_IRQHandler+0xa0>
  3138. 8005d5e: 3114 adds r1, #20
  3139. 8005d60: 428b cmp r3, r1
  3140. 8005d62: d015 beq.n 8005d90 <HAL_DMA_IRQHandler+0xa4>
  3141. 8005d64: 3114 adds r1, #20
  3142. 8005d66: 428b cmp r3, r1
  3143. 8005d68: d014 beq.n 8005d94 <HAL_DMA_IRQHandler+0xa8>
  3144. 8005d6a: 3114 adds r1, #20
  3145. 8005d6c: 428b cmp r3, r1
  3146. 8005d6e: d014 beq.n 8005d9a <HAL_DMA_IRQHandler+0xae>
  3147. 8005d70: 3114 adds r1, #20
  3148. 8005d72: 428b cmp r3, r1
  3149. 8005d74: d014 beq.n 8005da0 <HAL_DMA_IRQHandler+0xb4>
  3150. 8005d76: 3114 adds r1, #20
  3151. 8005d78: 428b cmp r3, r1
  3152. 8005d7a: d014 beq.n 8005da6 <HAL_DMA_IRQHandler+0xba>
  3153. 8005d7c: 4293 cmp r3, r2
  3154. 8005d7e: bf14 ite ne
  3155. 8005d80: f44f 2380 movne.w r3, #262144 ; 0x40000
  3156. 8005d84: f04f 6380 moveq.w r3, #67108864 ; 0x4000000
  3157. 8005d88: 4a45 ldr r2, [pc, #276] ; (8005ea0 <HAL_DMA_IRQHandler+0x1b4>)
  3158. 8005d8a: e7d7 b.n 8005d3c <HAL_DMA_IRQHandler+0x50>
  3159. 8005d8c: 2304 movs r3, #4
  3160. 8005d8e: e7fb b.n 8005d88 <HAL_DMA_IRQHandler+0x9c>
  3161. 8005d90: 2340 movs r3, #64 ; 0x40
  3162. 8005d92: e7f9 b.n 8005d88 <HAL_DMA_IRQHandler+0x9c>
  3163. 8005d94: f44f 6380 mov.w r3, #1024 ; 0x400
  3164. 8005d98: e7f6 b.n 8005d88 <HAL_DMA_IRQHandler+0x9c>
  3165. 8005d9a: f44f 4380 mov.w r3, #16384 ; 0x4000
  3166. 8005d9e: e7f3 b.n 8005d88 <HAL_DMA_IRQHandler+0x9c>
  3167. 8005da0: f44f 2380 mov.w r3, #262144 ; 0x40000
  3168. 8005da4: e7f0 b.n 8005d88 <HAL_DMA_IRQHandler+0x9c>
  3169. 8005da6: f44f 0380 mov.w r3, #4194304 ; 0x400000
  3170. 8005daa: e7ed b.n 8005d88 <HAL_DMA_IRQHandler+0x9c>
  3171. else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET))
  3172. 8005dac: 2502 movs r5, #2
  3173. 8005dae: 4095 lsls r5, r2
  3174. 8005db0: 4225 tst r5, r4
  3175. 8005db2: d057 beq.n 8005e64 <HAL_DMA_IRQHandler+0x178>
  3176. 8005db4: 078d lsls r5, r1, #30
  3177. 8005db6: d555 bpl.n 8005e64 <HAL_DMA_IRQHandler+0x178>
  3178. if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
  3179. 8005db8: 681a ldr r2, [r3, #0]
  3180. 8005dba: 0694 lsls r4, r2, #26
  3181. 8005dbc: d406 bmi.n 8005dcc <HAL_DMA_IRQHandler+0xe0>
  3182. __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
  3183. 8005dbe: 681a ldr r2, [r3, #0]
  3184. 8005dc0: f022 020a bic.w r2, r2, #10
  3185. 8005dc4: 601a str r2, [r3, #0]
  3186. hdma->State = HAL_DMA_STATE_READY;
  3187. 8005dc6: 2201 movs r2, #1
  3188. 8005dc8: f880 2021 strb.w r2, [r0, #33] ; 0x21
  3189. __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
  3190. 8005dcc: 4a31 ldr r2, [pc, #196] ; (8005e94 <HAL_DMA_IRQHandler+0x1a8>)
  3191. 8005dce: 4293 cmp r3, r2
  3192. 8005dd0: d91e bls.n 8005e10 <HAL_DMA_IRQHandler+0x124>
  3193. 8005dd2: f502 7262 add.w r2, r2, #904 ; 0x388
  3194. 8005dd6: 4293 cmp r3, r2
  3195. 8005dd8: d013 beq.n 8005e02 <HAL_DMA_IRQHandler+0x116>
  3196. 8005dda: 3214 adds r2, #20
  3197. 8005ddc: 4293 cmp r3, r2
  3198. 8005dde: d012 beq.n 8005e06 <HAL_DMA_IRQHandler+0x11a>
  3199. 8005de0: 3214 adds r2, #20
  3200. 8005de2: 4293 cmp r3, r2
  3201. 8005de4: d011 beq.n 8005e0a <HAL_DMA_IRQHandler+0x11e>
  3202. 8005de6: 3214 adds r2, #20
  3203. 8005de8: 4293 cmp r3, r2
  3204. 8005dea: bf0c ite eq
  3205. 8005dec: f44f 5300 moveq.w r3, #8192 ; 0x2000
  3206. 8005df0: f44f 3300 movne.w r3, #131072 ; 0x20000
  3207. 8005df4: 4a28 ldr r2, [pc, #160] ; (8005e98 <HAL_DMA_IRQHandler+0x1ac>)
  3208. 8005df6: 6053 str r3, [r2, #4]
  3209. __HAL_UNLOCK(hdma);
  3210. 8005df8: 2300 movs r3, #0
  3211. 8005dfa: f880 3020 strb.w r3, [r0, #32]
  3212. if(hdma->XferCpltCallback != NULL)
  3213. 8005dfe: 6a83 ldr r3, [r0, #40] ; 0x28
  3214. 8005e00: e79e b.n 8005d40 <HAL_DMA_IRQHandler+0x54>
  3215. __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
  3216. 8005e02: 2302 movs r3, #2
  3217. 8005e04: e7f6 b.n 8005df4 <HAL_DMA_IRQHandler+0x108>
  3218. 8005e06: 2320 movs r3, #32
  3219. 8005e08: e7f4 b.n 8005df4 <HAL_DMA_IRQHandler+0x108>
  3220. 8005e0a: f44f 7300 mov.w r3, #512 ; 0x200
  3221. 8005e0e: e7f1 b.n 8005df4 <HAL_DMA_IRQHandler+0x108>
  3222. 8005e10: 4922 ldr r1, [pc, #136] ; (8005e9c <HAL_DMA_IRQHandler+0x1b0>)
  3223. 8005e12: 428b cmp r3, r1
  3224. 8005e14: d016 beq.n 8005e44 <HAL_DMA_IRQHandler+0x158>
  3225. 8005e16: 3114 adds r1, #20
  3226. 8005e18: 428b cmp r3, r1
  3227. 8005e1a: d015 beq.n 8005e48 <HAL_DMA_IRQHandler+0x15c>
  3228. 8005e1c: 3114 adds r1, #20
  3229. 8005e1e: 428b cmp r3, r1
  3230. 8005e20: d014 beq.n 8005e4c <HAL_DMA_IRQHandler+0x160>
  3231. 8005e22: 3114 adds r1, #20
  3232. 8005e24: 428b cmp r3, r1
  3233. 8005e26: d014 beq.n 8005e52 <HAL_DMA_IRQHandler+0x166>
  3234. 8005e28: 3114 adds r1, #20
  3235. 8005e2a: 428b cmp r3, r1
  3236. 8005e2c: d014 beq.n 8005e58 <HAL_DMA_IRQHandler+0x16c>
  3237. 8005e2e: 3114 adds r1, #20
  3238. 8005e30: 428b cmp r3, r1
  3239. 8005e32: d014 beq.n 8005e5e <HAL_DMA_IRQHandler+0x172>
  3240. 8005e34: 4293 cmp r3, r2
  3241. 8005e36: bf14 ite ne
  3242. 8005e38: f44f 3300 movne.w r3, #131072 ; 0x20000
  3243. 8005e3c: f04f 7300 moveq.w r3, #33554432 ; 0x2000000
  3244. 8005e40: 4a17 ldr r2, [pc, #92] ; (8005ea0 <HAL_DMA_IRQHandler+0x1b4>)
  3245. 8005e42: e7d8 b.n 8005df6 <HAL_DMA_IRQHandler+0x10a>
  3246. 8005e44: 2302 movs r3, #2
  3247. 8005e46: e7fb b.n 8005e40 <HAL_DMA_IRQHandler+0x154>
  3248. 8005e48: 2320 movs r3, #32
  3249. 8005e4a: e7f9 b.n 8005e40 <HAL_DMA_IRQHandler+0x154>
  3250. 8005e4c: f44f 7300 mov.w r3, #512 ; 0x200
  3251. 8005e50: e7f6 b.n 8005e40 <HAL_DMA_IRQHandler+0x154>
  3252. 8005e52: f44f 5300 mov.w r3, #8192 ; 0x2000
  3253. 8005e56: e7f3 b.n 8005e40 <HAL_DMA_IRQHandler+0x154>
  3254. 8005e58: f44f 3300 mov.w r3, #131072 ; 0x20000
  3255. 8005e5c: e7f0 b.n 8005e40 <HAL_DMA_IRQHandler+0x154>
  3256. 8005e5e: f44f 1300 mov.w r3, #2097152 ; 0x200000
  3257. 8005e62: e7ed b.n 8005e40 <HAL_DMA_IRQHandler+0x154>
  3258. else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
  3259. 8005e64: 2508 movs r5, #8
  3260. 8005e66: 4095 lsls r5, r2
  3261. 8005e68: 4225 tst r5, r4
  3262. 8005e6a: d011 beq.n 8005e90 <HAL_DMA_IRQHandler+0x1a4>
  3263. 8005e6c: 0709 lsls r1, r1, #28
  3264. 8005e6e: d50f bpl.n 8005e90 <HAL_DMA_IRQHandler+0x1a4>
  3265. __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
  3266. 8005e70: 6819 ldr r1, [r3, #0]
  3267. 8005e72: f021 010e bic.w r1, r1, #14
  3268. 8005e76: 6019 str r1, [r3, #0]
  3269. hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
  3270. 8005e78: 2301 movs r3, #1
  3271. 8005e7a: fa03 f202 lsl.w r2, r3, r2
  3272. 8005e7e: 6072 str r2, [r6, #4]
  3273. hdma->ErrorCode = HAL_DMA_ERROR_TE;
  3274. 8005e80: 6383 str r3, [r0, #56] ; 0x38
  3275. hdma->State = HAL_DMA_STATE_READY;
  3276. 8005e82: f880 3021 strb.w r3, [r0, #33] ; 0x21
  3277. __HAL_UNLOCK(hdma);
  3278. 8005e86: 2300 movs r3, #0
  3279. 8005e88: f880 3020 strb.w r3, [r0, #32]
  3280. if (hdma->XferErrorCallback != NULL)
  3281. 8005e8c: 6b03 ldr r3, [r0, #48] ; 0x30
  3282. 8005e8e: e757 b.n 8005d40 <HAL_DMA_IRQHandler+0x54>
  3283. }
  3284. 8005e90: bc70 pop {r4, r5, r6}
  3285. 8005e92: 4770 bx lr
  3286. 8005e94: 40020080 .word 0x40020080
  3287. 8005e98: 40020400 .word 0x40020400
  3288. 8005e9c: 40020008 .word 0x40020008
  3289. 8005ea0: 40020000 .word 0x40020000
  3290. 08005ea4 <FLASH_SetErrorCode>:
  3291. uint32_t flags = 0U;
  3292. #if defined(FLASH_BANK2_END)
  3293. if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2))
  3294. #else
  3295. if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
  3296. 8005ea4: 4a11 ldr r2, [pc, #68] ; (8005eec <FLASH_SetErrorCode+0x48>)
  3297. 8005ea6: 68d3 ldr r3, [r2, #12]
  3298. 8005ea8: f013 0310 ands.w r3, r3, #16
  3299. 8005eac: d005 beq.n 8005eba <FLASH_SetErrorCode+0x16>
  3300. #endif /* FLASH_BANK2_END */
  3301. {
  3302. pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
  3303. 8005eae: 4910 ldr r1, [pc, #64] ; (8005ef0 <FLASH_SetErrorCode+0x4c>)
  3304. 8005eb0: 69cb ldr r3, [r1, #28]
  3305. 8005eb2: f043 0302 orr.w r3, r3, #2
  3306. 8005eb6: 61cb str r3, [r1, #28]
  3307. #if defined(FLASH_BANK2_END)
  3308. flags |= FLASH_FLAG_WRPERR | FLASH_FLAG_WRPERR_BANK2;
  3309. #else
  3310. flags |= FLASH_FLAG_WRPERR;
  3311. 8005eb8: 2310 movs r3, #16
  3312. #endif /* FLASH_BANK2_END */
  3313. }
  3314. #if defined(FLASH_BANK2_END)
  3315. if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2))
  3316. #else
  3317. if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
  3318. 8005eba: 68d2 ldr r2, [r2, #12]
  3319. 8005ebc: 0750 lsls r0, r2, #29
  3320. 8005ebe: d506 bpl.n 8005ece <FLASH_SetErrorCode+0x2a>
  3321. #endif /* FLASH_BANK2_END */
  3322. {
  3323. pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG;
  3324. 8005ec0: 490b ldr r1, [pc, #44] ; (8005ef0 <FLASH_SetErrorCode+0x4c>)
  3325. #if defined(FLASH_BANK2_END)
  3326. flags |= FLASH_FLAG_PGERR | FLASH_FLAG_PGERR_BANK2;
  3327. #else
  3328. flags |= FLASH_FLAG_PGERR;
  3329. 8005ec2: f043 0304 orr.w r3, r3, #4
  3330. pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG;
  3331. 8005ec6: 69ca ldr r2, [r1, #28]
  3332. 8005ec8: f042 0201 orr.w r2, r2, #1
  3333. 8005ecc: 61ca str r2, [r1, #28]
  3334. #endif /* FLASH_BANK2_END */
  3335. }
  3336. if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR))
  3337. 8005ece: 4a07 ldr r2, [pc, #28] ; (8005eec <FLASH_SetErrorCode+0x48>)
  3338. 8005ed0: 69d1 ldr r1, [r2, #28]
  3339. 8005ed2: 07c9 lsls r1, r1, #31
  3340. 8005ed4: d508 bpl.n 8005ee8 <FLASH_SetErrorCode+0x44>
  3341. {
  3342. pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV;
  3343. 8005ed6: 4806 ldr r0, [pc, #24] ; (8005ef0 <FLASH_SetErrorCode+0x4c>)
  3344. 8005ed8: 69c1 ldr r1, [r0, #28]
  3345. 8005eda: f041 0104 orr.w r1, r1, #4
  3346. 8005ede: 61c1 str r1, [r0, #28]
  3347. __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR);
  3348. 8005ee0: 69d1 ldr r1, [r2, #28]
  3349. 8005ee2: f021 0101 bic.w r1, r1, #1
  3350. 8005ee6: 61d1 str r1, [r2, #28]
  3351. }
  3352. /* Clear FLASH error pending bits */
  3353. __HAL_FLASH_CLEAR_FLAG(flags);
  3354. 8005ee8: 60d3 str r3, [r2, #12]
  3355. 8005eea: 4770 bx lr
  3356. 8005eec: 40022000 .word 0x40022000
  3357. 8005ef0: 20000468 .word 0x20000468
  3358. 08005ef4 <HAL_FLASH_Unlock>:
  3359. if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
  3360. 8005ef4: 4b06 ldr r3, [pc, #24] ; (8005f10 <HAL_FLASH_Unlock+0x1c>)
  3361. 8005ef6: 6918 ldr r0, [r3, #16]
  3362. 8005ef8: f010 0080 ands.w r0, r0, #128 ; 0x80
  3363. 8005efc: d007 beq.n 8005f0e <HAL_FLASH_Unlock+0x1a>
  3364. WRITE_REG(FLASH->KEYR, FLASH_KEY1);
  3365. 8005efe: 4a05 ldr r2, [pc, #20] ; (8005f14 <HAL_FLASH_Unlock+0x20>)
  3366. 8005f00: 605a str r2, [r3, #4]
  3367. WRITE_REG(FLASH->KEYR, FLASH_KEY2);
  3368. 8005f02: f102 3288 add.w r2, r2, #2290649224 ; 0x88888888
  3369. 8005f06: 605a str r2, [r3, #4]
  3370. if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
  3371. 8005f08: 6918 ldr r0, [r3, #16]
  3372. HAL_StatusTypeDef status = HAL_OK;
  3373. 8005f0a: f3c0 10c0 ubfx r0, r0, #7, #1
  3374. }
  3375. 8005f0e: 4770 bx lr
  3376. 8005f10: 40022000 .word 0x40022000
  3377. 8005f14: 45670123 .word 0x45670123
  3378. 08005f18 <HAL_FLASH_Lock>:
  3379. SET_BIT(FLASH->CR, FLASH_CR_LOCK);
  3380. 8005f18: 4a03 ldr r2, [pc, #12] ; (8005f28 <HAL_FLASH_Lock+0x10>)
  3381. }
  3382. 8005f1a: 2000 movs r0, #0
  3383. SET_BIT(FLASH->CR, FLASH_CR_LOCK);
  3384. 8005f1c: 6913 ldr r3, [r2, #16]
  3385. 8005f1e: f043 0380 orr.w r3, r3, #128 ; 0x80
  3386. 8005f22: 6113 str r3, [r2, #16]
  3387. }
  3388. 8005f24: 4770 bx lr
  3389. 8005f26: bf00 nop
  3390. 8005f28: 40022000 .word 0x40022000
  3391. 08005f2c <FLASH_WaitForLastOperation>:
  3392. {
  3393. 8005f2c: b5f8 push {r3, r4, r5, r6, r7, lr}
  3394. 8005f2e: 4606 mov r6, r0
  3395. uint32_t tickstart = HAL_GetTick();
  3396. 8005f30: f7ff fad6 bl 80054e0 <HAL_GetTick>
  3397. while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
  3398. 8005f34: 4c11 ldr r4, [pc, #68] ; (8005f7c <FLASH_WaitForLastOperation+0x50>)
  3399. uint32_t tickstart = HAL_GetTick();
  3400. 8005f36: 4607 mov r7, r0
  3401. 8005f38: 4625 mov r5, r4
  3402. while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
  3403. 8005f3a: 68e3 ldr r3, [r4, #12]
  3404. 8005f3c: 07d8 lsls r0, r3, #31
  3405. 8005f3e: d412 bmi.n 8005f66 <FLASH_WaitForLastOperation+0x3a>
  3406. if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
  3407. 8005f40: 68e3 ldr r3, [r4, #12]
  3408. 8005f42: 0699 lsls r1, r3, #26
  3409. __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
  3410. 8005f44: bf44 itt mi
  3411. 8005f46: 2320 movmi r3, #32
  3412. 8005f48: 60e3 strmi r3, [r4, #12]
  3413. if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||
  3414. 8005f4a: 68eb ldr r3, [r5, #12]
  3415. 8005f4c: 06da lsls r2, r3, #27
  3416. 8005f4e: d406 bmi.n 8005f5e <FLASH_WaitForLastOperation+0x32>
  3417. __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) ||
  3418. 8005f50: 69eb ldr r3, [r5, #28]
  3419. if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||
  3420. 8005f52: 07db lsls r3, r3, #31
  3421. 8005f54: d403 bmi.n 8005f5e <FLASH_WaitForLastOperation+0x32>
  3422. __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
  3423. 8005f56: 68e8 ldr r0, [r5, #12]
  3424. __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) ||
  3425. 8005f58: f010 0004 ands.w r0, r0, #4
  3426. 8005f5c: d002 beq.n 8005f64 <FLASH_WaitForLastOperation+0x38>
  3427. FLASH_SetErrorCode();
  3428. 8005f5e: f7ff ffa1 bl 8005ea4 <FLASH_SetErrorCode>
  3429. return HAL_ERROR;
  3430. 8005f62: 2001 movs r0, #1
  3431. }
  3432. 8005f64: bdf8 pop {r3, r4, r5, r6, r7, pc}
  3433. if (Timeout != HAL_MAX_DELAY)
  3434. 8005f66: 1c73 adds r3, r6, #1
  3435. 8005f68: d0e7 beq.n 8005f3a <FLASH_WaitForLastOperation+0xe>
  3436. if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
  3437. 8005f6a: b90e cbnz r6, 8005f70 <FLASH_WaitForLastOperation+0x44>
  3438. return HAL_TIMEOUT;
  3439. 8005f6c: 2003 movs r0, #3
  3440. 8005f6e: bdf8 pop {r3, r4, r5, r6, r7, pc}
  3441. if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
  3442. 8005f70: f7ff fab6 bl 80054e0 <HAL_GetTick>
  3443. 8005f74: 1bc0 subs r0, r0, r7
  3444. 8005f76: 4286 cmp r6, r0
  3445. 8005f78: d2df bcs.n 8005f3a <FLASH_WaitForLastOperation+0xe>
  3446. 8005f7a: e7f7 b.n 8005f6c <FLASH_WaitForLastOperation+0x40>
  3447. 8005f7c: 40022000 .word 0x40022000
  3448. 08005f80 <HAL_FLASH_Program>:
  3449. {
  3450. 8005f80: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
  3451. __HAL_LOCK(&pFlash);
  3452. 8005f84: 4c1f ldr r4, [pc, #124] ; (8006004 <HAL_FLASH_Program+0x84>)
  3453. {
  3454. 8005f86: 4699 mov r9, r3
  3455. __HAL_LOCK(&pFlash);
  3456. 8005f88: 7e23 ldrb r3, [r4, #24]
  3457. {
  3458. 8005f8a: 4605 mov r5, r0
  3459. __HAL_LOCK(&pFlash);
  3460. 8005f8c: 2b01 cmp r3, #1
  3461. {
  3462. 8005f8e: 460f mov r7, r1
  3463. 8005f90: 4690 mov r8, r2
  3464. __HAL_LOCK(&pFlash);
  3465. 8005f92: d033 beq.n 8005ffc <HAL_FLASH_Program+0x7c>
  3466. 8005f94: 2301 movs r3, #1
  3467. status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
  3468. 8005f96: f24c 3050 movw r0, #50000 ; 0xc350
  3469. __HAL_LOCK(&pFlash);
  3470. 8005f9a: 7623 strb r3, [r4, #24]
  3471. status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
  3472. 8005f9c: f7ff ffc6 bl 8005f2c <FLASH_WaitForLastOperation>
  3473. if(status == HAL_OK)
  3474. 8005fa0: bb40 cbnz r0, 8005ff4 <HAL_FLASH_Program+0x74>
  3475. if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
  3476. 8005fa2: 2d01 cmp r5, #1
  3477. 8005fa4: d003 beq.n 8005fae <HAL_FLASH_Program+0x2e>
  3478. nbiterations = 4U;
  3479. 8005fa6: 2d02 cmp r5, #2
  3480. 8005fa8: bf0c ite eq
  3481. 8005faa: 2502 moveq r5, #2
  3482. 8005fac: 2504 movne r5, #4
  3483. 8005fae: 2600 movs r6, #0
  3484. pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
  3485. 8005fb0: 46b2 mov sl, r6
  3486. SET_BIT(FLASH->CR, FLASH_CR_PG);
  3487. 8005fb2: f8df b054 ldr.w fp, [pc, #84] ; 8006008 <HAL_FLASH_Program+0x88>
  3488. FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index)));
  3489. 8005fb6: 0132 lsls r2, r6, #4
  3490. 8005fb8: 4640 mov r0, r8
  3491. 8005fba: 4649 mov r1, r9
  3492. 8005fbc: f7fe f93c bl 8004238 <__aeabi_llsr>
  3493. pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
  3494. 8005fc0: f8c4 a01c str.w sl, [r4, #28]
  3495. SET_BIT(FLASH->CR, FLASH_CR_PG);
  3496. 8005fc4: f8db 3010 ldr.w r3, [fp, #16]
  3497. FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index)));
  3498. 8005fc8: b280 uxth r0, r0
  3499. SET_BIT(FLASH->CR, FLASH_CR_PG);
  3500. 8005fca: f043 0301 orr.w r3, r3, #1
  3501. 8005fce: f8cb 3010 str.w r3, [fp, #16]
  3502. *(__IO uint16_t*)Address = Data;
  3503. 8005fd2: f827 0016 strh.w r0, [r7, r6, lsl #1]
  3504. status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
  3505. 8005fd6: f24c 3050 movw r0, #50000 ; 0xc350
  3506. 8005fda: f7ff ffa7 bl 8005f2c <FLASH_WaitForLastOperation>
  3507. CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
  3508. 8005fde: f8db 3010 ldr.w r3, [fp, #16]
  3509. 8005fe2: f023 0301 bic.w r3, r3, #1
  3510. 8005fe6: f8cb 3010 str.w r3, [fp, #16]
  3511. if (status != HAL_OK)
  3512. 8005fea: b918 cbnz r0, 8005ff4 <HAL_FLASH_Program+0x74>
  3513. 8005fec: 3601 adds r6, #1
  3514. for (index = 0U; index < nbiterations; index++)
  3515. 8005fee: b2f3 uxtb r3, r6
  3516. 8005ff0: 429d cmp r5, r3
  3517. 8005ff2: d8e0 bhi.n 8005fb6 <HAL_FLASH_Program+0x36>
  3518. __HAL_UNLOCK(&pFlash);
  3519. 8005ff4: 2300 movs r3, #0
  3520. 8005ff6: 7623 strb r3, [r4, #24]
  3521. return status;
  3522. 8005ff8: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
  3523. __HAL_LOCK(&pFlash);
  3524. 8005ffc: 2002 movs r0, #2
  3525. }
  3526. 8005ffe: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
  3527. 8006002: bf00 nop
  3528. 8006004: 20000468 .word 0x20000468
  3529. 8006008: 40022000 .word 0x40022000
  3530. 0800600c <FLASH_MassErase.isra.0>:
  3531. {
  3532. /* Check the parameters */
  3533. assert_param(IS_FLASH_BANK(Banks));
  3534. /* Clean the error context */
  3535. pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
  3536. 800600c: 2200 movs r2, #0
  3537. 800600e: 4b06 ldr r3, [pc, #24] ; (8006028 <FLASH_MassErase.isra.0+0x1c>)
  3538. 8006010: 61da str r2, [r3, #28]
  3539. #if !defined(FLASH_BANK2_END)
  3540. /* Prevent unused argument(s) compilation warning */
  3541. UNUSED(Banks);
  3542. #endif /* FLASH_BANK2_END */
  3543. /* Only bank1 will be erased*/
  3544. SET_BIT(FLASH->CR, FLASH_CR_MER);
  3545. 8006012: 4b06 ldr r3, [pc, #24] ; (800602c <FLASH_MassErase.isra.0+0x20>)
  3546. 8006014: 691a ldr r2, [r3, #16]
  3547. 8006016: f042 0204 orr.w r2, r2, #4
  3548. 800601a: 611a str r2, [r3, #16]
  3549. SET_BIT(FLASH->CR, FLASH_CR_STRT);
  3550. 800601c: 691a ldr r2, [r3, #16]
  3551. 800601e: f042 0240 orr.w r2, r2, #64 ; 0x40
  3552. 8006022: 611a str r2, [r3, #16]
  3553. 8006024: 4770 bx lr
  3554. 8006026: bf00 nop
  3555. 8006028: 20000468 .word 0x20000468
  3556. 800602c: 40022000 .word 0x40022000
  3557. 08006030 <FLASH_PageErase>:
  3558. * @retval None
  3559. */
  3560. void FLASH_PageErase(uint32_t PageAddress)
  3561. {
  3562. /* Clean the error context */
  3563. pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
  3564. 8006030: 2200 movs r2, #0
  3565. 8006032: 4b06 ldr r3, [pc, #24] ; (800604c <FLASH_PageErase+0x1c>)
  3566. 8006034: 61da str r2, [r3, #28]
  3567. }
  3568. else
  3569. {
  3570. #endif /* FLASH_BANK2_END */
  3571. /* Proceed to erase the page */
  3572. SET_BIT(FLASH->CR, FLASH_CR_PER);
  3573. 8006036: 4b06 ldr r3, [pc, #24] ; (8006050 <FLASH_PageErase+0x20>)
  3574. 8006038: 691a ldr r2, [r3, #16]
  3575. 800603a: f042 0202 orr.w r2, r2, #2
  3576. 800603e: 611a str r2, [r3, #16]
  3577. WRITE_REG(FLASH->AR, PageAddress);
  3578. 8006040: 6158 str r0, [r3, #20]
  3579. SET_BIT(FLASH->CR, FLASH_CR_STRT);
  3580. 8006042: 691a ldr r2, [r3, #16]
  3581. 8006044: f042 0240 orr.w r2, r2, #64 ; 0x40
  3582. 8006048: 611a str r2, [r3, #16]
  3583. 800604a: 4770 bx lr
  3584. 800604c: 20000468 .word 0x20000468
  3585. 8006050: 40022000 .word 0x40022000
  3586. 08006054 <HAL_FLASHEx_Erase>:
  3587. {
  3588. 8006054: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
  3589. __HAL_LOCK(&pFlash);
  3590. 8006058: 4d23 ldr r5, [pc, #140] ; (80060e8 <HAL_FLASHEx_Erase+0x94>)
  3591. {
  3592. 800605a: 4607 mov r7, r0
  3593. __HAL_LOCK(&pFlash);
  3594. 800605c: 7e2b ldrb r3, [r5, #24]
  3595. {
  3596. 800605e: 4688 mov r8, r1
  3597. __HAL_LOCK(&pFlash);
  3598. 8006060: 2b01 cmp r3, #1
  3599. 8006062: d03d beq.n 80060e0 <HAL_FLASHEx_Erase+0x8c>
  3600. 8006064: 2401 movs r4, #1
  3601. if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
  3602. 8006066: 6803 ldr r3, [r0, #0]
  3603. __HAL_LOCK(&pFlash);
  3604. 8006068: 762c strb r4, [r5, #24]
  3605. if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
  3606. 800606a: 2b02 cmp r3, #2
  3607. if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
  3608. 800606c: f24c 3050 movw r0, #50000 ; 0xc350
  3609. if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
  3610. 8006070: d113 bne.n 800609a <HAL_FLASHEx_Erase+0x46>
  3611. if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
  3612. 8006072: f7ff ff5b bl 8005f2c <FLASH_WaitForLastOperation>
  3613. 8006076: b120 cbz r0, 8006082 <HAL_FLASHEx_Erase+0x2e>
  3614. HAL_StatusTypeDef status = HAL_ERROR;
  3615. 8006078: 2001 movs r0, #1
  3616. __HAL_UNLOCK(&pFlash);
  3617. 800607a: 2300 movs r3, #0
  3618. 800607c: 762b strb r3, [r5, #24]
  3619. return status;
  3620. 800607e: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
  3621. FLASH_MassErase(FLASH_BANK_1);
  3622. 8006082: f7ff ffc3 bl 800600c <FLASH_MassErase.isra.0>
  3623. status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
  3624. 8006086: f24c 3050 movw r0, #50000 ; 0xc350
  3625. 800608a: f7ff ff4f bl 8005f2c <FLASH_WaitForLastOperation>
  3626. CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
  3627. 800608e: 4a17 ldr r2, [pc, #92] ; (80060ec <HAL_FLASHEx_Erase+0x98>)
  3628. 8006090: 6913 ldr r3, [r2, #16]
  3629. 8006092: f023 0304 bic.w r3, r3, #4
  3630. 8006096: 6113 str r3, [r2, #16]
  3631. 8006098: e7ef b.n 800607a <HAL_FLASHEx_Erase+0x26>
  3632. if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
  3633. 800609a: f7ff ff47 bl 8005f2c <FLASH_WaitForLastOperation>
  3634. 800609e: 2800 cmp r0, #0
  3635. 80060a0: d1ea bne.n 8006078 <HAL_FLASHEx_Erase+0x24>
  3636. *PageError = 0xFFFFFFFFU;
  3637. 80060a2: f04f 33ff mov.w r3, #4294967295
  3638. 80060a6: f8c8 3000 str.w r3, [r8]
  3639. HAL_StatusTypeDef status = HAL_ERROR;
  3640. 80060aa: 4620 mov r0, r4
  3641. for(address = pEraseInit->PageAddress;
  3642. 80060ac: 68be ldr r6, [r7, #8]
  3643. CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
  3644. 80060ae: 4c0f ldr r4, [pc, #60] ; (80060ec <HAL_FLASHEx_Erase+0x98>)
  3645. address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress);
  3646. 80060b0: 68fa ldr r2, [r7, #12]
  3647. 80060b2: 68bb ldr r3, [r7, #8]
  3648. 80060b4: eb03 23c2 add.w r3, r3, r2, lsl #11
  3649. for(address = pEraseInit->PageAddress;
  3650. 80060b8: 429e cmp r6, r3
  3651. 80060ba: d2de bcs.n 800607a <HAL_FLASHEx_Erase+0x26>
  3652. FLASH_PageErase(address);
  3653. 80060bc: 4630 mov r0, r6
  3654. 80060be: f7ff ffb7 bl 8006030 <FLASH_PageErase>
  3655. status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
  3656. 80060c2: f24c 3050 movw r0, #50000 ; 0xc350
  3657. 80060c6: f7ff ff31 bl 8005f2c <FLASH_WaitForLastOperation>
  3658. CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
  3659. 80060ca: 6923 ldr r3, [r4, #16]
  3660. 80060cc: f023 0302 bic.w r3, r3, #2
  3661. 80060d0: 6123 str r3, [r4, #16]
  3662. if (status != HAL_OK)
  3663. 80060d2: b110 cbz r0, 80060da <HAL_FLASHEx_Erase+0x86>
  3664. *PageError = address;
  3665. 80060d4: f8c8 6000 str.w r6, [r8]
  3666. break;
  3667. 80060d8: e7cf b.n 800607a <HAL_FLASHEx_Erase+0x26>
  3668. address += FLASH_PAGE_SIZE)
  3669. 80060da: f506 6600 add.w r6, r6, #2048 ; 0x800
  3670. 80060de: e7e7 b.n 80060b0 <HAL_FLASHEx_Erase+0x5c>
  3671. __HAL_LOCK(&pFlash);
  3672. 80060e0: 2002 movs r0, #2
  3673. }
  3674. 80060e2: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
  3675. 80060e6: bf00 nop
  3676. 80060e8: 20000468 .word 0x20000468
  3677. 80060ec: 40022000 .word 0x40022000
  3678. 080060f0 <HAL_GPIO_Init>:
  3679. * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
  3680. * the configuration information for the specified GPIO peripheral.
  3681. * @retval None
  3682. */
  3683. void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
  3684. {
  3685. 80060f0: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
  3686. uint32_t position;
  3687. uint32_t ioposition = 0x00U;
  3688. uint32_t iocurrent = 0x00U;
  3689. uint32_t temp = 0x00U;
  3690. uint32_t config = 0x00U;
  3691. 80060f4: 2200 movs r2, #0
  3692. assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
  3693. assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
  3694. assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
  3695. /* Configure the port pins */
  3696. for (position = 0U; position < GPIO_NUMBER; position++)
  3697. 80060f6: 4616 mov r6, r2
  3698. /*--------------------- EXTI Mode Configuration ------------------------*/
  3699. /* Configure the External Interrupt or event for the current IO */
  3700. if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
  3701. {
  3702. /* Enable AFIO Clock */
  3703. __HAL_RCC_AFIO_CLK_ENABLE();
  3704. 80060f8: 4f6c ldr r7, [pc, #432] ; (80062ac <HAL_GPIO_Init+0x1bc>)
  3705. 80060fa: 4b6d ldr r3, [pc, #436] ; (80062b0 <HAL_GPIO_Init+0x1c0>)
  3706. temp = AFIO->EXTICR[position >> 2U];
  3707. CLEAR_BIT(temp, (0x0FU) << (4U * (position & 0x03U)));
  3708. SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
  3709. 80060fc: f8df e1b8 ldr.w lr, [pc, #440] ; 80062b8 <HAL_GPIO_Init+0x1c8>
  3710. switch (GPIO_Init->Mode)
  3711. 8006100: f8df c1b8 ldr.w ip, [pc, #440] ; 80062bc <HAL_GPIO_Init+0x1cc>
  3712. ioposition = (0x01U << position);
  3713. 8006104: f04f 0801 mov.w r8, #1
  3714. iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
  3715. 8006108: 680c ldr r4, [r1, #0]
  3716. ioposition = (0x01U << position);
  3717. 800610a: fa08 f806 lsl.w r8, r8, r6
  3718. iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
  3719. 800610e: ea08 0404 and.w r4, r8, r4
  3720. if (iocurrent == ioposition)
  3721. 8006112: 45a0 cmp r8, r4
  3722. 8006114: f040 8085 bne.w 8006222 <HAL_GPIO_Init+0x132>
  3723. switch (GPIO_Init->Mode)
  3724. 8006118: 684d ldr r5, [r1, #4]
  3725. 800611a: 2d12 cmp r5, #18
  3726. 800611c: f000 80b7 beq.w 800628e <HAL_GPIO_Init+0x19e>
  3727. 8006120: f200 808d bhi.w 800623e <HAL_GPIO_Init+0x14e>
  3728. 8006124: 2d02 cmp r5, #2
  3729. 8006126: f000 80af beq.w 8006288 <HAL_GPIO_Init+0x198>
  3730. 800612a: f200 8081 bhi.w 8006230 <HAL_GPIO_Init+0x140>
  3731. 800612e: 2d00 cmp r5, #0
  3732. 8006130: f000 8091 beq.w 8006256 <HAL_GPIO_Init+0x166>
  3733. 8006134: 2d01 cmp r5, #1
  3734. 8006136: f000 80a5 beq.w 8006284 <HAL_GPIO_Init+0x194>
  3735. MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
  3736. 800613a: f04f 090f mov.w r9, #15
  3737. configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;
  3738. 800613e: 2cff cmp r4, #255 ; 0xff
  3739. 8006140: bf93 iteet ls
  3740. 8006142: 4682 movls sl, r0
  3741. 8006144: f106 4580 addhi.w r5, r6, #1073741824 ; 0x40000000
  3742. 8006148: 3d08 subhi r5, #8
  3743. 800614a: f8d0 b000 ldrls.w fp, [r0]
  3744. 800614e: bf92 itee ls
  3745. 8006150: 00b5 lslls r5, r6, #2
  3746. 8006152: f8d0 b004 ldrhi.w fp, [r0, #4]
  3747. 8006156: 00ad lslhi r5, r5, #2
  3748. MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
  3749. 8006158: fa09 f805 lsl.w r8, r9, r5
  3750. 800615c: ea2b 0808 bic.w r8, fp, r8
  3751. 8006160: fa02 f505 lsl.w r5, r2, r5
  3752. configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;
  3753. 8006164: bf88 it hi
  3754. 8006166: f100 0a04 addhi.w sl, r0, #4
  3755. MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
  3756. 800616a: ea48 0505 orr.w r5, r8, r5
  3757. 800616e: f8ca 5000 str.w r5, [sl]
  3758. if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
  3759. 8006172: f8d1 a004 ldr.w sl, [r1, #4]
  3760. 8006176: f01a 5f80 tst.w sl, #268435456 ; 0x10000000
  3761. 800617a: d052 beq.n 8006222 <HAL_GPIO_Init+0x132>
  3762. __HAL_RCC_AFIO_CLK_ENABLE();
  3763. 800617c: 69bd ldr r5, [r7, #24]
  3764. 800617e: f026 0803 bic.w r8, r6, #3
  3765. 8006182: f045 0501 orr.w r5, r5, #1
  3766. 8006186: 61bd str r5, [r7, #24]
  3767. 8006188: 69bd ldr r5, [r7, #24]
  3768. 800618a: f108 4880 add.w r8, r8, #1073741824 ; 0x40000000
  3769. 800618e: f005 0501 and.w r5, r5, #1
  3770. 8006192: 9501 str r5, [sp, #4]
  3771. 8006194: f508 3880 add.w r8, r8, #65536 ; 0x10000
  3772. CLEAR_BIT(temp, (0x0FU) << (4U * (position & 0x03U)));
  3773. 8006198: f006 0b03 and.w fp, r6, #3
  3774. __HAL_RCC_AFIO_CLK_ENABLE();
  3775. 800619c: 9d01 ldr r5, [sp, #4]
  3776. CLEAR_BIT(temp, (0x0FU) << (4U * (position & 0x03U)));
  3777. 800619e: ea4f 0b8b mov.w fp, fp, lsl #2
  3778. temp = AFIO->EXTICR[position >> 2U];
  3779. 80061a2: f8d8 5008 ldr.w r5, [r8, #8]
  3780. CLEAR_BIT(temp, (0x0FU) << (4U * (position & 0x03U)));
  3781. 80061a6: fa09 f90b lsl.w r9, r9, fp
  3782. 80061aa: ea25 0909 bic.w r9, r5, r9
  3783. SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
  3784. 80061ae: 4d41 ldr r5, [pc, #260] ; (80062b4 <HAL_GPIO_Init+0x1c4>)
  3785. 80061b0: 42a8 cmp r0, r5
  3786. 80061b2: d071 beq.n 8006298 <HAL_GPIO_Init+0x1a8>
  3787. 80061b4: f505 6580 add.w r5, r5, #1024 ; 0x400
  3788. 80061b8: 42a8 cmp r0, r5
  3789. 80061ba: d06f beq.n 800629c <HAL_GPIO_Init+0x1ac>
  3790. 80061bc: f505 6580 add.w r5, r5, #1024 ; 0x400
  3791. 80061c0: 42a8 cmp r0, r5
  3792. 80061c2: d06d beq.n 80062a0 <HAL_GPIO_Init+0x1b0>
  3793. 80061c4: f505 6580 add.w r5, r5, #1024 ; 0x400
  3794. 80061c8: 42a8 cmp r0, r5
  3795. 80061ca: d06b beq.n 80062a4 <HAL_GPIO_Init+0x1b4>
  3796. 80061cc: f505 6580 add.w r5, r5, #1024 ; 0x400
  3797. 80061d0: 42a8 cmp r0, r5
  3798. 80061d2: d069 beq.n 80062a8 <HAL_GPIO_Init+0x1b8>
  3799. 80061d4: 4570 cmp r0, lr
  3800. 80061d6: bf0c ite eq
  3801. 80061d8: 2505 moveq r5, #5
  3802. 80061da: 2506 movne r5, #6
  3803. 80061dc: fa05 f50b lsl.w r5, r5, fp
  3804. 80061e0: ea45 0509 orr.w r5, r5, r9
  3805. AFIO->EXTICR[position >> 2U] = temp;
  3806. 80061e4: f8c8 5008 str.w r5, [r8, #8]
  3807. /* Configure the interrupt mask */
  3808. if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
  3809. {
  3810. SET_BIT(EXTI->IMR, iocurrent);
  3811. 80061e8: 681d ldr r5, [r3, #0]
  3812. if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
  3813. 80061ea: f41a 3f80 tst.w sl, #65536 ; 0x10000
  3814. SET_BIT(EXTI->IMR, iocurrent);
  3815. 80061ee: bf14 ite ne
  3816. 80061f0: 4325 orrne r5, r4
  3817. }
  3818. else
  3819. {
  3820. CLEAR_BIT(EXTI->IMR, iocurrent);
  3821. 80061f2: 43a5 biceq r5, r4
  3822. 80061f4: 601d str r5, [r3, #0]
  3823. }
  3824. /* Configure the event mask */
  3825. if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
  3826. {
  3827. SET_BIT(EXTI->EMR, iocurrent);
  3828. 80061f6: 685d ldr r5, [r3, #4]
  3829. if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
  3830. 80061f8: f41a 3f00 tst.w sl, #131072 ; 0x20000
  3831. SET_BIT(EXTI->EMR, iocurrent);
  3832. 80061fc: bf14 ite ne
  3833. 80061fe: 4325 orrne r5, r4
  3834. }
  3835. else
  3836. {
  3837. CLEAR_BIT(EXTI->EMR, iocurrent);
  3838. 8006200: 43a5 biceq r5, r4
  3839. 8006202: 605d str r5, [r3, #4]
  3840. }
  3841. /* Enable or disable the rising trigger */
  3842. if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
  3843. {
  3844. SET_BIT(EXTI->RTSR, iocurrent);
  3845. 8006204: 689d ldr r5, [r3, #8]
  3846. if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
  3847. 8006206: f41a 1f80 tst.w sl, #1048576 ; 0x100000
  3848. SET_BIT(EXTI->RTSR, iocurrent);
  3849. 800620a: bf14 ite ne
  3850. 800620c: 4325 orrne r5, r4
  3851. }
  3852. else
  3853. {
  3854. CLEAR_BIT(EXTI->RTSR, iocurrent);
  3855. 800620e: 43a5 biceq r5, r4
  3856. 8006210: 609d str r5, [r3, #8]
  3857. }
  3858. /* Enable or disable the falling trigger */
  3859. if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
  3860. {
  3861. SET_BIT(EXTI->FTSR, iocurrent);
  3862. 8006212: 68dd ldr r5, [r3, #12]
  3863. if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
  3864. 8006214: f41a 1f00 tst.w sl, #2097152 ; 0x200000
  3865. SET_BIT(EXTI->FTSR, iocurrent);
  3866. 8006218: bf14 ite ne
  3867. 800621a: 432c orrne r4, r5
  3868. }
  3869. else
  3870. {
  3871. CLEAR_BIT(EXTI->FTSR, iocurrent);
  3872. 800621c: ea25 0404 biceq.w r4, r5, r4
  3873. 8006220: 60dc str r4, [r3, #12]
  3874. for (position = 0U; position < GPIO_NUMBER; position++)
  3875. 8006222: 3601 adds r6, #1
  3876. 8006224: 2e10 cmp r6, #16
  3877. 8006226: f47f af6d bne.w 8006104 <HAL_GPIO_Init+0x14>
  3878. }
  3879. }
  3880. }
  3881. }
  3882. }
  3883. 800622a: b003 add sp, #12
  3884. 800622c: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
  3885. switch (GPIO_Init->Mode)
  3886. 8006230: 2d03 cmp r5, #3
  3887. 8006232: d025 beq.n 8006280 <HAL_GPIO_Init+0x190>
  3888. 8006234: 2d11 cmp r5, #17
  3889. 8006236: d180 bne.n 800613a <HAL_GPIO_Init+0x4a>
  3890. config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;
  3891. 8006238: 68ca ldr r2, [r1, #12]
  3892. 800623a: 3204 adds r2, #4
  3893. break;
  3894. 800623c: e77d b.n 800613a <HAL_GPIO_Init+0x4a>
  3895. switch (GPIO_Init->Mode)
  3896. 800623e: 4565 cmp r5, ip
  3897. 8006240: d009 beq.n 8006256 <HAL_GPIO_Init+0x166>
  3898. 8006242: d812 bhi.n 800626a <HAL_GPIO_Init+0x17a>
  3899. 8006244: f8df 9078 ldr.w r9, [pc, #120] ; 80062c0 <HAL_GPIO_Init+0x1d0>
  3900. 8006248: 454d cmp r5, r9
  3901. 800624a: d004 beq.n 8006256 <HAL_GPIO_Init+0x166>
  3902. 800624c: f509 3980 add.w r9, r9, #65536 ; 0x10000
  3903. 8006250: 454d cmp r5, r9
  3904. 8006252: f47f af72 bne.w 800613a <HAL_GPIO_Init+0x4a>
  3905. if (GPIO_Init->Pull == GPIO_NOPULL)
  3906. 8006256: 688a ldr r2, [r1, #8]
  3907. 8006258: b1e2 cbz r2, 8006294 <HAL_GPIO_Init+0x1a4>
  3908. else if (GPIO_Init->Pull == GPIO_PULLUP)
  3909. 800625a: 2a01 cmp r2, #1
  3910. GPIOx->BSRR = ioposition;
  3911. 800625c: bf0c ite eq
  3912. 800625e: f8c0 8010 streq.w r8, [r0, #16]
  3913. GPIOx->BRR = ioposition;
  3914. 8006262: f8c0 8014 strne.w r8, [r0, #20]
  3915. config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
  3916. 8006266: 2208 movs r2, #8
  3917. 8006268: e767 b.n 800613a <HAL_GPIO_Init+0x4a>
  3918. switch (GPIO_Init->Mode)
  3919. 800626a: f8df 9058 ldr.w r9, [pc, #88] ; 80062c4 <HAL_GPIO_Init+0x1d4>
  3920. 800626e: 454d cmp r5, r9
  3921. 8006270: d0f1 beq.n 8006256 <HAL_GPIO_Init+0x166>
  3922. 8006272: f509 3980 add.w r9, r9, #65536 ; 0x10000
  3923. 8006276: 454d cmp r5, r9
  3924. 8006278: d0ed beq.n 8006256 <HAL_GPIO_Init+0x166>
  3925. 800627a: f5a9 1980 sub.w r9, r9, #1048576 ; 0x100000
  3926. 800627e: e7e7 b.n 8006250 <HAL_GPIO_Init+0x160>
  3927. config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
  3928. 8006280: 2200 movs r2, #0
  3929. 8006282: e75a b.n 800613a <HAL_GPIO_Init+0x4a>
  3930. config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;
  3931. 8006284: 68ca ldr r2, [r1, #12]
  3932. break;
  3933. 8006286: e758 b.n 800613a <HAL_GPIO_Init+0x4a>
  3934. config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;
  3935. 8006288: 68ca ldr r2, [r1, #12]
  3936. 800628a: 3208 adds r2, #8
  3937. break;
  3938. 800628c: e755 b.n 800613a <HAL_GPIO_Init+0x4a>
  3939. config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;
  3940. 800628e: 68ca ldr r2, [r1, #12]
  3941. 8006290: 320c adds r2, #12
  3942. break;
  3943. 8006292: e752 b.n 800613a <HAL_GPIO_Init+0x4a>
  3944. config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
  3945. 8006294: 2204 movs r2, #4
  3946. 8006296: e750 b.n 800613a <HAL_GPIO_Init+0x4a>
  3947. SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
  3948. 8006298: 2500 movs r5, #0
  3949. 800629a: e79f b.n 80061dc <HAL_GPIO_Init+0xec>
  3950. 800629c: 2501 movs r5, #1
  3951. 800629e: e79d b.n 80061dc <HAL_GPIO_Init+0xec>
  3952. 80062a0: 2502 movs r5, #2
  3953. 80062a2: e79b b.n 80061dc <HAL_GPIO_Init+0xec>
  3954. 80062a4: 2503 movs r5, #3
  3955. 80062a6: e799 b.n 80061dc <HAL_GPIO_Init+0xec>
  3956. 80062a8: 2504 movs r5, #4
  3957. 80062aa: e797 b.n 80061dc <HAL_GPIO_Init+0xec>
  3958. 80062ac: 40021000 .word 0x40021000
  3959. 80062b0: 40010400 .word 0x40010400
  3960. 80062b4: 40010800 .word 0x40010800
  3961. 80062b8: 40011c00 .word 0x40011c00
  3962. 80062bc: 10210000 .word 0x10210000
  3963. 80062c0: 10110000 .word 0x10110000
  3964. 80062c4: 10310000 .word 0x10310000
  3965. 080062c8 <HAL_GPIO_ReadPin>:
  3966. GPIO_PinState bitstatus;
  3967. /* Check the parameters */
  3968. assert_param(IS_GPIO_PIN(GPIO_Pin));
  3969. if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
  3970. 80062c8: 6883 ldr r3, [r0, #8]
  3971. 80062ca: 4219 tst r1, r3
  3972. else
  3973. {
  3974. bitstatus = GPIO_PIN_RESET;
  3975. }
  3976. return bitstatus;
  3977. }
  3978. 80062cc: bf14 ite ne
  3979. 80062ce: 2001 movne r0, #1
  3980. 80062d0: 2000 moveq r0, #0
  3981. 80062d2: 4770 bx lr
  3982. 080062d4 <HAL_GPIO_WritePin>:
  3983. {
  3984. /* Check the parameters */
  3985. assert_param(IS_GPIO_PIN(GPIO_Pin));
  3986. assert_param(IS_GPIO_PIN_ACTION(PinState));
  3987. if (PinState != GPIO_PIN_RESET)
  3988. 80062d4: b10a cbz r2, 80062da <HAL_GPIO_WritePin+0x6>
  3989. {
  3990. GPIOx->BSRR = GPIO_Pin;
  3991. }
  3992. else
  3993. {
  3994. GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
  3995. 80062d6: 6101 str r1, [r0, #16]
  3996. 80062d8: 4770 bx lr
  3997. 80062da: 0409 lsls r1, r1, #16
  3998. 80062dc: e7fb b.n 80062d6 <HAL_GPIO_WritePin+0x2>
  3999. 080062de <HAL_GPIO_TogglePin>:
  4000. void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
  4001. {
  4002. /* Check the parameters */
  4003. assert_param(IS_GPIO_PIN(GPIO_Pin));
  4004. GPIOx->ODR ^= GPIO_Pin;
  4005. 80062de: 68c3 ldr r3, [r0, #12]
  4006. 80062e0: 4059 eors r1, r3
  4007. 80062e2: 60c1 str r1, [r0, #12]
  4008. 80062e4: 4770 bx lr
  4009. ...
  4010. 080062e8 <HAL_RCC_OscConfig>:
  4011. /* Check the parameters */
  4012. assert_param(RCC_OscInitStruct != NULL);
  4013. assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
  4014. /*------------------------------- HSE Configuration ------------------------*/
  4015. if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
  4016. 80062e8: 6803 ldr r3, [r0, #0]
  4017. {
  4018. 80062ea: e92d 41f3 stmdb sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
  4019. if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
  4020. 80062ee: 07db lsls r3, r3, #31
  4021. {
  4022. 80062f0: 4605 mov r5, r0
  4023. if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
  4024. 80062f2: d410 bmi.n 8006316 <HAL_RCC_OscConfig+0x2e>
  4025. }
  4026. }
  4027. }
  4028. }
  4029. /*----------------------------- HSI Configuration --------------------------*/
  4030. if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
  4031. 80062f4: 682b ldr r3, [r5, #0]
  4032. 80062f6: 079f lsls r7, r3, #30
  4033. 80062f8: d45e bmi.n 80063b8 <HAL_RCC_OscConfig+0xd0>
  4034. }
  4035. }
  4036. }
  4037. }
  4038. /*------------------------------ LSI Configuration -------------------------*/
  4039. if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
  4040. 80062fa: 682b ldr r3, [r5, #0]
  4041. 80062fc: 0719 lsls r1, r3, #28
  4042. 80062fe: f100 8095 bmi.w 800642c <HAL_RCC_OscConfig+0x144>
  4043. }
  4044. }
  4045. }
  4046. }
  4047. /*------------------------------ LSE Configuration -------------------------*/
  4048. if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
  4049. 8006302: 682b ldr r3, [r5, #0]
  4050. 8006304: 075a lsls r2, r3, #29
  4051. 8006306: f100 80bf bmi.w 8006488 <HAL_RCC_OscConfig+0x1a0>
  4052. #endif /* RCC_CR_PLL2ON */
  4053. /*-------------------------------- PLL Configuration -----------------------*/
  4054. /* Check the parameters */
  4055. assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
  4056. if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
  4057. 800630a: 69ea ldr r2, [r5, #28]
  4058. 800630c: 2a00 cmp r2, #0
  4059. 800630e: f040 812d bne.w 800656c <HAL_RCC_OscConfig+0x284>
  4060. {
  4061. return HAL_ERROR;
  4062. }
  4063. }
  4064. return HAL_OK;
  4065. 8006312: 2000 movs r0, #0
  4066. 8006314: e014 b.n 8006340 <HAL_RCC_OscConfig+0x58>
  4067. if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
  4068. 8006316: 4c90 ldr r4, [pc, #576] ; (8006558 <HAL_RCC_OscConfig+0x270>)
  4069. 8006318: 6863 ldr r3, [r4, #4]
  4070. 800631a: f003 030c and.w r3, r3, #12
  4071. 800631e: 2b04 cmp r3, #4
  4072. 8006320: d007 beq.n 8006332 <HAL_RCC_OscConfig+0x4a>
  4073. || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
  4074. 8006322: 6863 ldr r3, [r4, #4]
  4075. 8006324: f003 030c and.w r3, r3, #12
  4076. 8006328: 2b08 cmp r3, #8
  4077. 800632a: d10c bne.n 8006346 <HAL_RCC_OscConfig+0x5e>
  4078. 800632c: 6863 ldr r3, [r4, #4]
  4079. 800632e: 03de lsls r6, r3, #15
  4080. 8006330: d509 bpl.n 8006346 <HAL_RCC_OscConfig+0x5e>
  4081. if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
  4082. 8006332: 6823 ldr r3, [r4, #0]
  4083. 8006334: 039c lsls r4, r3, #14
  4084. 8006336: d5dd bpl.n 80062f4 <HAL_RCC_OscConfig+0xc>
  4085. 8006338: 686b ldr r3, [r5, #4]
  4086. 800633a: 2b00 cmp r3, #0
  4087. 800633c: d1da bne.n 80062f4 <HAL_RCC_OscConfig+0xc>
  4088. return HAL_ERROR;
  4089. 800633e: 2001 movs r0, #1
  4090. }
  4091. 8006340: b002 add sp, #8
  4092. 8006342: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
  4093. __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
  4094. 8006346: 686b ldr r3, [r5, #4]
  4095. 8006348: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
  4096. 800634c: d110 bne.n 8006370 <HAL_RCC_OscConfig+0x88>
  4097. 800634e: 6823 ldr r3, [r4, #0]
  4098. 8006350: f443 3380 orr.w r3, r3, #65536 ; 0x10000
  4099. 8006354: 6023 str r3, [r4, #0]
  4100. tickstart = HAL_GetTick();
  4101. 8006356: f7ff f8c3 bl 80054e0 <HAL_GetTick>
  4102. 800635a: 4606 mov r6, r0
  4103. while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
  4104. 800635c: 6823 ldr r3, [r4, #0]
  4105. 800635e: 0398 lsls r0, r3, #14
  4106. 8006360: d4c8 bmi.n 80062f4 <HAL_RCC_OscConfig+0xc>
  4107. if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
  4108. 8006362: f7ff f8bd bl 80054e0 <HAL_GetTick>
  4109. 8006366: 1b80 subs r0, r0, r6
  4110. 8006368: 2864 cmp r0, #100 ; 0x64
  4111. 800636a: d9f7 bls.n 800635c <HAL_RCC_OscConfig+0x74>
  4112. return HAL_TIMEOUT;
  4113. 800636c: 2003 movs r0, #3
  4114. 800636e: e7e7 b.n 8006340 <HAL_RCC_OscConfig+0x58>
  4115. __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
  4116. 8006370: b99b cbnz r3, 800639a <HAL_RCC_OscConfig+0xb2>
  4117. 8006372: 6823 ldr r3, [r4, #0]
  4118. 8006374: f423 3380 bic.w r3, r3, #65536 ; 0x10000
  4119. 8006378: 6023 str r3, [r4, #0]
  4120. 800637a: 6823 ldr r3, [r4, #0]
  4121. 800637c: f423 2380 bic.w r3, r3, #262144 ; 0x40000
  4122. 8006380: 6023 str r3, [r4, #0]
  4123. tickstart = HAL_GetTick();
  4124. 8006382: f7ff f8ad bl 80054e0 <HAL_GetTick>
  4125. 8006386: 4606 mov r6, r0
  4126. while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
  4127. 8006388: 6823 ldr r3, [r4, #0]
  4128. 800638a: 0399 lsls r1, r3, #14
  4129. 800638c: d5b2 bpl.n 80062f4 <HAL_RCC_OscConfig+0xc>
  4130. if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
  4131. 800638e: f7ff f8a7 bl 80054e0 <HAL_GetTick>
  4132. 8006392: 1b80 subs r0, r0, r6
  4133. 8006394: 2864 cmp r0, #100 ; 0x64
  4134. 8006396: d9f7 bls.n 8006388 <HAL_RCC_OscConfig+0xa0>
  4135. 8006398: e7e8 b.n 800636c <HAL_RCC_OscConfig+0x84>
  4136. __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
  4137. 800639a: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
  4138. 800639e: 6823 ldr r3, [r4, #0]
  4139. 80063a0: d103 bne.n 80063aa <HAL_RCC_OscConfig+0xc2>
  4140. 80063a2: f443 2380 orr.w r3, r3, #262144 ; 0x40000
  4141. 80063a6: 6023 str r3, [r4, #0]
  4142. 80063a8: e7d1 b.n 800634e <HAL_RCC_OscConfig+0x66>
  4143. 80063aa: f423 3380 bic.w r3, r3, #65536 ; 0x10000
  4144. 80063ae: 6023 str r3, [r4, #0]
  4145. 80063b0: 6823 ldr r3, [r4, #0]
  4146. 80063b2: f423 2380 bic.w r3, r3, #262144 ; 0x40000
  4147. 80063b6: e7cd b.n 8006354 <HAL_RCC_OscConfig+0x6c>
  4148. if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
  4149. 80063b8: 4c67 ldr r4, [pc, #412] ; (8006558 <HAL_RCC_OscConfig+0x270>)
  4150. 80063ba: 6863 ldr r3, [r4, #4]
  4151. 80063bc: f013 0f0c tst.w r3, #12
  4152. 80063c0: d007 beq.n 80063d2 <HAL_RCC_OscConfig+0xea>
  4153. || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
  4154. 80063c2: 6863 ldr r3, [r4, #4]
  4155. 80063c4: f003 030c and.w r3, r3, #12
  4156. 80063c8: 2b08 cmp r3, #8
  4157. 80063ca: d110 bne.n 80063ee <HAL_RCC_OscConfig+0x106>
  4158. 80063cc: 6863 ldr r3, [r4, #4]
  4159. 80063ce: 03da lsls r2, r3, #15
  4160. 80063d0: d40d bmi.n 80063ee <HAL_RCC_OscConfig+0x106>
  4161. if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
  4162. 80063d2: 6823 ldr r3, [r4, #0]
  4163. 80063d4: 079b lsls r3, r3, #30
  4164. 80063d6: d502 bpl.n 80063de <HAL_RCC_OscConfig+0xf6>
  4165. 80063d8: 692b ldr r3, [r5, #16]
  4166. 80063da: 2b01 cmp r3, #1
  4167. 80063dc: d1af bne.n 800633e <HAL_RCC_OscConfig+0x56>
  4168. __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
  4169. 80063de: 6823 ldr r3, [r4, #0]
  4170. 80063e0: 696a ldr r2, [r5, #20]
  4171. 80063e2: f023 03f8 bic.w r3, r3, #248 ; 0xf8
  4172. 80063e6: ea43 03c2 orr.w r3, r3, r2, lsl #3
  4173. 80063ea: 6023 str r3, [r4, #0]
  4174. 80063ec: e785 b.n 80062fa <HAL_RCC_OscConfig+0x12>
  4175. if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
  4176. 80063ee: 692a ldr r2, [r5, #16]
  4177. 80063f0: 4b5a ldr r3, [pc, #360] ; (800655c <HAL_RCC_OscConfig+0x274>)
  4178. 80063f2: b16a cbz r2, 8006410 <HAL_RCC_OscConfig+0x128>
  4179. __HAL_RCC_HSI_ENABLE();
  4180. 80063f4: 2201 movs r2, #1
  4181. 80063f6: 601a str r2, [r3, #0]
  4182. tickstart = HAL_GetTick();
  4183. 80063f8: f7ff f872 bl 80054e0 <HAL_GetTick>
  4184. 80063fc: 4606 mov r6, r0
  4185. while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
  4186. 80063fe: 6823 ldr r3, [r4, #0]
  4187. 8006400: 079f lsls r7, r3, #30
  4188. 8006402: d4ec bmi.n 80063de <HAL_RCC_OscConfig+0xf6>
  4189. if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
  4190. 8006404: f7ff f86c bl 80054e0 <HAL_GetTick>
  4191. 8006408: 1b80 subs r0, r0, r6
  4192. 800640a: 2802 cmp r0, #2
  4193. 800640c: d9f7 bls.n 80063fe <HAL_RCC_OscConfig+0x116>
  4194. 800640e: e7ad b.n 800636c <HAL_RCC_OscConfig+0x84>
  4195. __HAL_RCC_HSI_DISABLE();
  4196. 8006410: 601a str r2, [r3, #0]
  4197. tickstart = HAL_GetTick();
  4198. 8006412: f7ff f865 bl 80054e0 <HAL_GetTick>
  4199. 8006416: 4606 mov r6, r0
  4200. while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
  4201. 8006418: 6823 ldr r3, [r4, #0]
  4202. 800641a: 0798 lsls r0, r3, #30
  4203. 800641c: f57f af6d bpl.w 80062fa <HAL_RCC_OscConfig+0x12>
  4204. if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
  4205. 8006420: f7ff f85e bl 80054e0 <HAL_GetTick>
  4206. 8006424: 1b80 subs r0, r0, r6
  4207. 8006426: 2802 cmp r0, #2
  4208. 8006428: d9f6 bls.n 8006418 <HAL_RCC_OscConfig+0x130>
  4209. 800642a: e79f b.n 800636c <HAL_RCC_OscConfig+0x84>
  4210. if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
  4211. 800642c: 69aa ldr r2, [r5, #24]
  4212. 800642e: 4c4a ldr r4, [pc, #296] ; (8006558 <HAL_RCC_OscConfig+0x270>)
  4213. 8006430: 4b4b ldr r3, [pc, #300] ; (8006560 <HAL_RCC_OscConfig+0x278>)
  4214. 8006432: b1da cbz r2, 800646c <HAL_RCC_OscConfig+0x184>
  4215. __HAL_RCC_LSI_ENABLE();
  4216. 8006434: 2201 movs r2, #1
  4217. 8006436: 601a str r2, [r3, #0]
  4218. tickstart = HAL_GetTick();
  4219. 8006438: f7ff f852 bl 80054e0 <HAL_GetTick>
  4220. 800643c: 4606 mov r6, r0
  4221. while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
  4222. 800643e: 6a63 ldr r3, [r4, #36] ; 0x24
  4223. 8006440: 079b lsls r3, r3, #30
  4224. 8006442: d50d bpl.n 8006460 <HAL_RCC_OscConfig+0x178>
  4225. * @param mdelay: specifies the delay time length, in milliseconds.
  4226. * @retval None
  4227. */
  4228. static void RCC_Delay(uint32_t mdelay)
  4229. {
  4230. __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
  4231. 8006444: f44f 52fa mov.w r2, #8000 ; 0x1f40
  4232. 8006448: 4b46 ldr r3, [pc, #280] ; (8006564 <HAL_RCC_OscConfig+0x27c>)
  4233. 800644a: 681b ldr r3, [r3, #0]
  4234. 800644c: fbb3 f3f2 udiv r3, r3, r2
  4235. 8006450: 9301 str r3, [sp, #4]
  4236. \brief No Operation
  4237. \details No Operation does nothing. This instruction can be used for code alignment purposes.
  4238. */
  4239. __attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
  4240. {
  4241. __ASM volatile ("nop");
  4242. 8006452: bf00 nop
  4243. do
  4244. {
  4245. __NOP();
  4246. }
  4247. while (Delay --);
  4248. 8006454: 9b01 ldr r3, [sp, #4]
  4249. 8006456: 1e5a subs r2, r3, #1
  4250. 8006458: 9201 str r2, [sp, #4]
  4251. 800645a: 2b00 cmp r3, #0
  4252. 800645c: d1f9 bne.n 8006452 <HAL_RCC_OscConfig+0x16a>
  4253. 800645e: e750 b.n 8006302 <HAL_RCC_OscConfig+0x1a>
  4254. if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
  4255. 8006460: f7ff f83e bl 80054e0 <HAL_GetTick>
  4256. 8006464: 1b80 subs r0, r0, r6
  4257. 8006466: 2802 cmp r0, #2
  4258. 8006468: d9e9 bls.n 800643e <HAL_RCC_OscConfig+0x156>
  4259. 800646a: e77f b.n 800636c <HAL_RCC_OscConfig+0x84>
  4260. __HAL_RCC_LSI_DISABLE();
  4261. 800646c: 601a str r2, [r3, #0]
  4262. tickstart = HAL_GetTick();
  4263. 800646e: f7ff f837 bl 80054e0 <HAL_GetTick>
  4264. 8006472: 4606 mov r6, r0
  4265. while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
  4266. 8006474: 6a63 ldr r3, [r4, #36] ; 0x24
  4267. 8006476: 079f lsls r7, r3, #30
  4268. 8006478: f57f af43 bpl.w 8006302 <HAL_RCC_OscConfig+0x1a>
  4269. if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
  4270. 800647c: f7ff f830 bl 80054e0 <HAL_GetTick>
  4271. 8006480: 1b80 subs r0, r0, r6
  4272. 8006482: 2802 cmp r0, #2
  4273. 8006484: d9f6 bls.n 8006474 <HAL_RCC_OscConfig+0x18c>
  4274. 8006486: e771 b.n 800636c <HAL_RCC_OscConfig+0x84>
  4275. if(__HAL_RCC_PWR_IS_CLK_DISABLED())
  4276. 8006488: 4c33 ldr r4, [pc, #204] ; (8006558 <HAL_RCC_OscConfig+0x270>)
  4277. 800648a: 69e3 ldr r3, [r4, #28]
  4278. 800648c: 00d8 lsls r0, r3, #3
  4279. 800648e: d424 bmi.n 80064da <HAL_RCC_OscConfig+0x1f2>
  4280. pwrclkchanged = SET;
  4281. 8006490: 2701 movs r7, #1
  4282. __HAL_RCC_PWR_CLK_ENABLE();
  4283. 8006492: 69e3 ldr r3, [r4, #28]
  4284. 8006494: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
  4285. 8006498: 61e3 str r3, [r4, #28]
  4286. 800649a: 69e3 ldr r3, [r4, #28]
  4287. 800649c: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
  4288. 80064a0: 9300 str r3, [sp, #0]
  4289. 80064a2: 9b00 ldr r3, [sp, #0]
  4290. if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
  4291. 80064a4: 4e30 ldr r6, [pc, #192] ; (8006568 <HAL_RCC_OscConfig+0x280>)
  4292. 80064a6: 6833 ldr r3, [r6, #0]
  4293. 80064a8: 05d9 lsls r1, r3, #23
  4294. 80064aa: d518 bpl.n 80064de <HAL_RCC_OscConfig+0x1f6>
  4295. __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
  4296. 80064ac: 68eb ldr r3, [r5, #12]
  4297. 80064ae: 2b01 cmp r3, #1
  4298. 80064b0: d126 bne.n 8006500 <HAL_RCC_OscConfig+0x218>
  4299. 80064b2: 6a23 ldr r3, [r4, #32]
  4300. 80064b4: f043 0301 orr.w r3, r3, #1
  4301. 80064b8: 6223 str r3, [r4, #32]
  4302. tickstart = HAL_GetTick();
  4303. 80064ba: f7ff f811 bl 80054e0 <HAL_GetTick>
  4304. if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
  4305. 80064be: f241 3688 movw r6, #5000 ; 0x1388
  4306. tickstart = HAL_GetTick();
  4307. 80064c2: 4680 mov r8, r0
  4308. while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
  4309. 80064c4: 6a23 ldr r3, [r4, #32]
  4310. 80064c6: 079b lsls r3, r3, #30
  4311. 80064c8: d53f bpl.n 800654a <HAL_RCC_OscConfig+0x262>
  4312. if(pwrclkchanged == SET)
  4313. 80064ca: 2f00 cmp r7, #0
  4314. 80064cc: f43f af1d beq.w 800630a <HAL_RCC_OscConfig+0x22>
  4315. __HAL_RCC_PWR_CLK_DISABLE();
  4316. 80064d0: 69e3 ldr r3, [r4, #28]
  4317. 80064d2: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
  4318. 80064d6: 61e3 str r3, [r4, #28]
  4319. 80064d8: e717 b.n 800630a <HAL_RCC_OscConfig+0x22>
  4320. FlagStatus pwrclkchanged = RESET;
  4321. 80064da: 2700 movs r7, #0
  4322. 80064dc: e7e2 b.n 80064a4 <HAL_RCC_OscConfig+0x1bc>
  4323. SET_BIT(PWR->CR, PWR_CR_DBP);
  4324. 80064de: 6833 ldr r3, [r6, #0]
  4325. 80064e0: f443 7380 orr.w r3, r3, #256 ; 0x100
  4326. 80064e4: 6033 str r3, [r6, #0]
  4327. tickstart = HAL_GetTick();
  4328. 80064e6: f7fe fffb bl 80054e0 <HAL_GetTick>
  4329. 80064ea: 4680 mov r8, r0
  4330. while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
  4331. 80064ec: 6833 ldr r3, [r6, #0]
  4332. 80064ee: 05da lsls r2, r3, #23
  4333. 80064f0: d4dc bmi.n 80064ac <HAL_RCC_OscConfig+0x1c4>
  4334. if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
  4335. 80064f2: f7fe fff5 bl 80054e0 <HAL_GetTick>
  4336. 80064f6: eba0 0008 sub.w r0, r0, r8
  4337. 80064fa: 2864 cmp r0, #100 ; 0x64
  4338. 80064fc: d9f6 bls.n 80064ec <HAL_RCC_OscConfig+0x204>
  4339. 80064fe: e735 b.n 800636c <HAL_RCC_OscConfig+0x84>
  4340. __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
  4341. 8006500: b9ab cbnz r3, 800652e <HAL_RCC_OscConfig+0x246>
  4342. 8006502: 6a23 ldr r3, [r4, #32]
  4343. if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
  4344. 8006504: f241 3888 movw r8, #5000 ; 0x1388
  4345. __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
  4346. 8006508: f023 0301 bic.w r3, r3, #1
  4347. 800650c: 6223 str r3, [r4, #32]
  4348. 800650e: 6a23 ldr r3, [r4, #32]
  4349. 8006510: f023 0304 bic.w r3, r3, #4
  4350. 8006514: 6223 str r3, [r4, #32]
  4351. tickstart = HAL_GetTick();
  4352. 8006516: f7fe ffe3 bl 80054e0 <HAL_GetTick>
  4353. 800651a: 4606 mov r6, r0
  4354. while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
  4355. 800651c: 6a23 ldr r3, [r4, #32]
  4356. 800651e: 0798 lsls r0, r3, #30
  4357. 8006520: d5d3 bpl.n 80064ca <HAL_RCC_OscConfig+0x1e2>
  4358. if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
  4359. 8006522: f7fe ffdd bl 80054e0 <HAL_GetTick>
  4360. 8006526: 1b80 subs r0, r0, r6
  4361. 8006528: 4540 cmp r0, r8
  4362. 800652a: d9f7 bls.n 800651c <HAL_RCC_OscConfig+0x234>
  4363. 800652c: e71e b.n 800636c <HAL_RCC_OscConfig+0x84>
  4364. __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
  4365. 800652e: 2b05 cmp r3, #5
  4366. 8006530: 6a23 ldr r3, [r4, #32]
  4367. 8006532: d103 bne.n 800653c <HAL_RCC_OscConfig+0x254>
  4368. 8006534: f043 0304 orr.w r3, r3, #4
  4369. 8006538: 6223 str r3, [r4, #32]
  4370. 800653a: e7ba b.n 80064b2 <HAL_RCC_OscConfig+0x1ca>
  4371. 800653c: f023 0301 bic.w r3, r3, #1
  4372. 8006540: 6223 str r3, [r4, #32]
  4373. 8006542: 6a23 ldr r3, [r4, #32]
  4374. 8006544: f023 0304 bic.w r3, r3, #4
  4375. 8006548: e7b6 b.n 80064b8 <HAL_RCC_OscConfig+0x1d0>
  4376. if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
  4377. 800654a: f7fe ffc9 bl 80054e0 <HAL_GetTick>
  4378. 800654e: eba0 0008 sub.w r0, r0, r8
  4379. 8006552: 42b0 cmp r0, r6
  4380. 8006554: d9b6 bls.n 80064c4 <HAL_RCC_OscConfig+0x1dc>
  4381. 8006556: e709 b.n 800636c <HAL_RCC_OscConfig+0x84>
  4382. 8006558: 40021000 .word 0x40021000
  4383. 800655c: 42420000 .word 0x42420000
  4384. 8006560: 42420480 .word 0x42420480
  4385. 8006564: 20000200 .word 0x20000200
  4386. 8006568: 40007000 .word 0x40007000
  4387. if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
  4388. 800656c: 4c22 ldr r4, [pc, #136] ; (80065f8 <HAL_RCC_OscConfig+0x310>)
  4389. 800656e: 6863 ldr r3, [r4, #4]
  4390. 8006570: f003 030c and.w r3, r3, #12
  4391. 8006574: 2b08 cmp r3, #8
  4392. 8006576: f43f aee2 beq.w 800633e <HAL_RCC_OscConfig+0x56>
  4393. 800657a: 2300 movs r3, #0
  4394. 800657c: 4e1f ldr r6, [pc, #124] ; (80065fc <HAL_RCC_OscConfig+0x314>)
  4395. if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
  4396. 800657e: 2a02 cmp r2, #2
  4397. __HAL_RCC_PLL_DISABLE();
  4398. 8006580: 6033 str r3, [r6, #0]
  4399. if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
  4400. 8006582: d12b bne.n 80065dc <HAL_RCC_OscConfig+0x2f4>
  4401. tickstart = HAL_GetTick();
  4402. 8006584: f7fe ffac bl 80054e0 <HAL_GetTick>
  4403. 8006588: 4607 mov r7, r0
  4404. while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
  4405. 800658a: 6823 ldr r3, [r4, #0]
  4406. 800658c: 0199 lsls r1, r3, #6
  4407. 800658e: d41f bmi.n 80065d0 <HAL_RCC_OscConfig+0x2e8>
  4408. if(RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
  4409. 8006590: 6a2b ldr r3, [r5, #32]
  4410. 8006592: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
  4411. 8006596: d105 bne.n 80065a4 <HAL_RCC_OscConfig+0x2bc>
  4412. __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
  4413. 8006598: 6862 ldr r2, [r4, #4]
  4414. 800659a: 68a9 ldr r1, [r5, #8]
  4415. 800659c: f422 3200 bic.w r2, r2, #131072 ; 0x20000
  4416. 80065a0: 430a orrs r2, r1
  4417. 80065a2: 6062 str r2, [r4, #4]
  4418. __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
  4419. 80065a4: 6a69 ldr r1, [r5, #36] ; 0x24
  4420. 80065a6: 6862 ldr r2, [r4, #4]
  4421. 80065a8: 430b orrs r3, r1
  4422. 80065aa: f422 1274 bic.w r2, r2, #3997696 ; 0x3d0000
  4423. 80065ae: 4313 orrs r3, r2
  4424. 80065b0: 6063 str r3, [r4, #4]
  4425. __HAL_RCC_PLL_ENABLE();
  4426. 80065b2: 2301 movs r3, #1
  4427. 80065b4: 6033 str r3, [r6, #0]
  4428. tickstart = HAL_GetTick();
  4429. 80065b6: f7fe ff93 bl 80054e0 <HAL_GetTick>
  4430. 80065ba: 4605 mov r5, r0
  4431. while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
  4432. 80065bc: 6823 ldr r3, [r4, #0]
  4433. 80065be: 019a lsls r2, r3, #6
  4434. 80065c0: f53f aea7 bmi.w 8006312 <HAL_RCC_OscConfig+0x2a>
  4435. if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
  4436. 80065c4: f7fe ff8c bl 80054e0 <HAL_GetTick>
  4437. 80065c8: 1b40 subs r0, r0, r5
  4438. 80065ca: 2802 cmp r0, #2
  4439. 80065cc: d9f6 bls.n 80065bc <HAL_RCC_OscConfig+0x2d4>
  4440. 80065ce: e6cd b.n 800636c <HAL_RCC_OscConfig+0x84>
  4441. if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
  4442. 80065d0: f7fe ff86 bl 80054e0 <HAL_GetTick>
  4443. 80065d4: 1bc0 subs r0, r0, r7
  4444. 80065d6: 2802 cmp r0, #2
  4445. 80065d8: d9d7 bls.n 800658a <HAL_RCC_OscConfig+0x2a2>
  4446. 80065da: e6c7 b.n 800636c <HAL_RCC_OscConfig+0x84>
  4447. tickstart = HAL_GetTick();
  4448. 80065dc: f7fe ff80 bl 80054e0 <HAL_GetTick>
  4449. 80065e0: 4605 mov r5, r0
  4450. while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
  4451. 80065e2: 6823 ldr r3, [r4, #0]
  4452. 80065e4: 019b lsls r3, r3, #6
  4453. 80065e6: f57f ae94 bpl.w 8006312 <HAL_RCC_OscConfig+0x2a>
  4454. if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
  4455. 80065ea: f7fe ff79 bl 80054e0 <HAL_GetTick>
  4456. 80065ee: 1b40 subs r0, r0, r5
  4457. 80065f0: 2802 cmp r0, #2
  4458. 80065f2: d9f6 bls.n 80065e2 <HAL_RCC_OscConfig+0x2fa>
  4459. 80065f4: e6ba b.n 800636c <HAL_RCC_OscConfig+0x84>
  4460. 80065f6: bf00 nop
  4461. 80065f8: 40021000 .word 0x40021000
  4462. 80065fc: 42420060 .word 0x42420060
  4463. 08006600 <HAL_RCC_GetSysClockFreq>:
  4464. {
  4465. 8006600: b530 push {r4, r5, lr}
  4466. const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
  4467. 8006602: 4b19 ldr r3, [pc, #100] ; (8006668 <HAL_RCC_GetSysClockFreq+0x68>)
  4468. {
  4469. 8006604: b087 sub sp, #28
  4470. const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
  4471. 8006606: ac02 add r4, sp, #8
  4472. 8006608: f103 0510 add.w r5, r3, #16
  4473. 800660c: 4622 mov r2, r4
  4474. 800660e: 6818 ldr r0, [r3, #0]
  4475. 8006610: 6859 ldr r1, [r3, #4]
  4476. 8006612: 3308 adds r3, #8
  4477. 8006614: c203 stmia r2!, {r0, r1}
  4478. 8006616: 42ab cmp r3, r5
  4479. 8006618: 4614 mov r4, r2
  4480. 800661a: d1f7 bne.n 800660c <HAL_RCC_GetSysClockFreq+0xc>
  4481. const uint8_t aPredivFactorTable[2] = {1, 2};
  4482. 800661c: 2301 movs r3, #1
  4483. 800661e: f88d 3004 strb.w r3, [sp, #4]
  4484. 8006622: 2302 movs r3, #2
  4485. tmpreg = RCC->CFGR;
  4486. 8006624: 4911 ldr r1, [pc, #68] ; (800666c <HAL_RCC_GetSysClockFreq+0x6c>)
  4487. const uint8_t aPredivFactorTable[2] = {1, 2};
  4488. 8006626: f88d 3005 strb.w r3, [sp, #5]
  4489. tmpreg = RCC->CFGR;
  4490. 800662a: 684b ldr r3, [r1, #4]
  4491. switch (tmpreg & RCC_CFGR_SWS)
  4492. 800662c: f003 020c and.w r2, r3, #12
  4493. 8006630: 2a08 cmp r2, #8
  4494. 8006632: d117 bne.n 8006664 <HAL_RCC_GetSysClockFreq+0x64>
  4495. pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
  4496. 8006634: f3c3 4283 ubfx r2, r3, #18, #4
  4497. 8006638: a806 add r0, sp, #24
  4498. 800663a: 4402 add r2, r0
  4499. if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
  4500. 800663c: 03db lsls r3, r3, #15
  4501. pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
  4502. 800663e: f812 2c10 ldrb.w r2, [r2, #-16]
  4503. if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
  4504. 8006642: d50c bpl.n 800665e <HAL_RCC_GetSysClockFreq+0x5e>
  4505. prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
  4506. 8006644: 684b ldr r3, [r1, #4]
  4507. pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv);
  4508. 8006646: 480a ldr r0, [pc, #40] ; (8006670 <HAL_RCC_GetSysClockFreq+0x70>)
  4509. prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
  4510. 8006648: f3c3 4340 ubfx r3, r3, #17, #1
  4511. pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv);
  4512. 800664c: 4350 muls r0, r2
  4513. prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
  4514. 800664e: aa06 add r2, sp, #24
  4515. 8006650: 4413 add r3, r2
  4516. 8006652: f813 3c14 ldrb.w r3, [r3, #-20]
  4517. pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv);
  4518. 8006656: fbb0 f0f3 udiv r0, r0, r3
  4519. }
  4520. 800665a: b007 add sp, #28
  4521. 800665c: bd30 pop {r4, r5, pc}
  4522. pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
  4523. 800665e: 4805 ldr r0, [pc, #20] ; (8006674 <HAL_RCC_GetSysClockFreq+0x74>)
  4524. 8006660: 4350 muls r0, r2
  4525. 8006662: e7fa b.n 800665a <HAL_RCC_GetSysClockFreq+0x5a>
  4526. sysclockfreq = HSE_VALUE;
  4527. 8006664: 4802 ldr r0, [pc, #8] ; (8006670 <HAL_RCC_GetSysClockFreq+0x70>)
  4528. return sysclockfreq;
  4529. 8006666: e7f8 b.n 800665a <HAL_RCC_GetSysClockFreq+0x5a>
  4530. 8006668: 0800bc48 .word 0x0800bc48
  4531. 800666c: 40021000 .word 0x40021000
  4532. 8006670: 007a1200 .word 0x007a1200
  4533. 8006674: 003d0900 .word 0x003d0900
  4534. 08006678 <HAL_RCC_ClockConfig>:
  4535. if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
  4536. 8006678: 4a54 ldr r2, [pc, #336] ; (80067cc <HAL_RCC_ClockConfig+0x154>)
  4537. {
  4538. 800667a: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
  4539. if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
  4540. 800667e: 6813 ldr r3, [r2, #0]
  4541. {
  4542. 8006680: 4605 mov r5, r0
  4543. if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
  4544. 8006682: f003 0307 and.w r3, r3, #7
  4545. 8006686: 428b cmp r3, r1
  4546. {
  4547. 8006688: 460e mov r6, r1
  4548. if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
  4549. 800668a: d32a bcc.n 80066e2 <HAL_RCC_ClockConfig+0x6a>
  4550. if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
  4551. 800668c: 6829 ldr r1, [r5, #0]
  4552. 800668e: 078c lsls r4, r1, #30
  4553. 8006690: d434 bmi.n 80066fc <HAL_RCC_ClockConfig+0x84>
  4554. if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
  4555. 8006692: 07ca lsls r2, r1, #31
  4556. 8006694: d447 bmi.n 8006726 <HAL_RCC_ClockConfig+0xae>
  4557. if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
  4558. 8006696: 4a4d ldr r2, [pc, #308] ; (80067cc <HAL_RCC_ClockConfig+0x154>)
  4559. 8006698: 6813 ldr r3, [r2, #0]
  4560. 800669a: f003 0307 and.w r3, r3, #7
  4561. 800669e: 429e cmp r6, r3
  4562. 80066a0: f0c0 8082 bcc.w 80067a8 <HAL_RCC_ClockConfig+0x130>
  4563. if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
  4564. 80066a4: 682a ldr r2, [r5, #0]
  4565. 80066a6: 4c4a ldr r4, [pc, #296] ; (80067d0 <HAL_RCC_ClockConfig+0x158>)
  4566. 80066a8: f012 0f04 tst.w r2, #4
  4567. 80066ac: f040 8087 bne.w 80067be <HAL_RCC_ClockConfig+0x146>
  4568. if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
  4569. 80066b0: 0713 lsls r3, r2, #28
  4570. 80066b2: d506 bpl.n 80066c2 <HAL_RCC_ClockConfig+0x4a>
  4571. MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
  4572. 80066b4: 6863 ldr r3, [r4, #4]
  4573. 80066b6: 692a ldr r2, [r5, #16]
  4574. 80066b8: f423 5360 bic.w r3, r3, #14336 ; 0x3800
  4575. 80066bc: ea43 03c2 orr.w r3, r3, r2, lsl #3
  4576. 80066c0: 6063 str r3, [r4, #4]
  4577. SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
  4578. 80066c2: f7ff ff9d bl 8006600 <HAL_RCC_GetSysClockFreq>
  4579. 80066c6: 6863 ldr r3, [r4, #4]
  4580. 80066c8: 4a42 ldr r2, [pc, #264] ; (80067d4 <HAL_RCC_ClockConfig+0x15c>)
  4581. 80066ca: f3c3 1303 ubfx r3, r3, #4, #4
  4582. 80066ce: 5cd3 ldrb r3, [r2, r3]
  4583. 80066d0: 40d8 lsrs r0, r3
  4584. 80066d2: 4b41 ldr r3, [pc, #260] ; (80067d8 <HAL_RCC_ClockConfig+0x160>)
  4585. 80066d4: 6018 str r0, [r3, #0]
  4586. HAL_InitTick (TICK_INT_PRIORITY);
  4587. 80066d6: 2000 movs r0, #0
  4588. 80066d8: f7fe fec0 bl 800545c <HAL_InitTick>
  4589. return HAL_OK;
  4590. 80066dc: 2000 movs r0, #0
  4591. }
  4592. 80066de: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
  4593. __HAL_FLASH_SET_LATENCY(FLatency);
  4594. 80066e2: 6813 ldr r3, [r2, #0]
  4595. 80066e4: f023 0307 bic.w r3, r3, #7
  4596. 80066e8: 430b orrs r3, r1
  4597. 80066ea: 6013 str r3, [r2, #0]
  4598. if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
  4599. 80066ec: 6813 ldr r3, [r2, #0]
  4600. 80066ee: f003 0307 and.w r3, r3, #7
  4601. 80066f2: 4299 cmp r1, r3
  4602. 80066f4: d0ca beq.n 800668c <HAL_RCC_ClockConfig+0x14>
  4603. return HAL_ERROR;
  4604. 80066f6: 2001 movs r0, #1
  4605. 80066f8: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
  4606. 80066fc: 4b34 ldr r3, [pc, #208] ; (80067d0 <HAL_RCC_ClockConfig+0x158>)
  4607. if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
  4608. 80066fe: f011 0f04 tst.w r1, #4
  4609. MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
  4610. 8006702: bf1e ittt ne
  4611. 8006704: 685a ldrne r2, [r3, #4]
  4612. 8006706: f442 62e0 orrne.w r2, r2, #1792 ; 0x700
  4613. 800670a: 605a strne r2, [r3, #4]
  4614. if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
  4615. 800670c: 0708 lsls r0, r1, #28
  4616. MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
  4617. 800670e: bf42 ittt mi
  4618. 8006710: 685a ldrmi r2, [r3, #4]
  4619. 8006712: f442 5260 orrmi.w r2, r2, #14336 ; 0x3800
  4620. 8006716: 605a strmi r2, [r3, #4]
  4621. MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
  4622. 8006718: 685a ldr r2, [r3, #4]
  4623. 800671a: 68a8 ldr r0, [r5, #8]
  4624. 800671c: f022 02f0 bic.w r2, r2, #240 ; 0xf0
  4625. 8006720: 4302 orrs r2, r0
  4626. 8006722: 605a str r2, [r3, #4]
  4627. 8006724: e7b5 b.n 8006692 <HAL_RCC_ClockConfig+0x1a>
  4628. if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
  4629. 8006726: 686a ldr r2, [r5, #4]
  4630. 8006728: 4c29 ldr r4, [pc, #164] ; (80067d0 <HAL_RCC_ClockConfig+0x158>)
  4631. 800672a: 2a01 cmp r2, #1
  4632. if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
  4633. 800672c: 6823 ldr r3, [r4, #0]
  4634. if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
  4635. 800672e: d11c bne.n 800676a <HAL_RCC_ClockConfig+0xf2>
  4636. if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
  4637. 8006730: f413 3f00 tst.w r3, #131072 ; 0x20000
  4638. if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
  4639. 8006734: d0df beq.n 80066f6 <HAL_RCC_ClockConfig+0x7e>
  4640. __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
  4641. 8006736: 6863 ldr r3, [r4, #4]
  4642. if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
  4643. 8006738: f241 3888 movw r8, #5000 ; 0x1388
  4644. __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
  4645. 800673c: f023 0303 bic.w r3, r3, #3
  4646. 8006740: 4313 orrs r3, r2
  4647. 8006742: 6063 str r3, [r4, #4]
  4648. tickstart = HAL_GetTick();
  4649. 8006744: f7fe fecc bl 80054e0 <HAL_GetTick>
  4650. if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
  4651. 8006748: 686b ldr r3, [r5, #4]
  4652. tickstart = HAL_GetTick();
  4653. 800674a: 4607 mov r7, r0
  4654. if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
  4655. 800674c: 2b01 cmp r3, #1
  4656. 800674e: d114 bne.n 800677a <HAL_RCC_ClockConfig+0x102>
  4657. while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
  4658. 8006750: 6863 ldr r3, [r4, #4]
  4659. 8006752: f003 030c and.w r3, r3, #12
  4660. 8006756: 2b04 cmp r3, #4
  4661. 8006758: d09d beq.n 8006696 <HAL_RCC_ClockConfig+0x1e>
  4662. if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
  4663. 800675a: f7fe fec1 bl 80054e0 <HAL_GetTick>
  4664. 800675e: 1bc0 subs r0, r0, r7
  4665. 8006760: 4540 cmp r0, r8
  4666. 8006762: d9f5 bls.n 8006750 <HAL_RCC_ClockConfig+0xd8>
  4667. return HAL_TIMEOUT;
  4668. 8006764: 2003 movs r0, #3
  4669. 8006766: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
  4670. else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
  4671. 800676a: 2a02 cmp r2, #2
  4672. 800676c: d102 bne.n 8006774 <HAL_RCC_ClockConfig+0xfc>
  4673. if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
  4674. 800676e: f013 7f00 tst.w r3, #33554432 ; 0x2000000
  4675. 8006772: e7df b.n 8006734 <HAL_RCC_ClockConfig+0xbc>
  4676. if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
  4677. 8006774: f013 0f02 tst.w r3, #2
  4678. 8006778: e7dc b.n 8006734 <HAL_RCC_ClockConfig+0xbc>
  4679. else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
  4680. 800677a: 2b02 cmp r3, #2
  4681. 800677c: d10f bne.n 800679e <HAL_RCC_ClockConfig+0x126>
  4682. while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
  4683. 800677e: 6863 ldr r3, [r4, #4]
  4684. 8006780: f003 030c and.w r3, r3, #12
  4685. 8006784: 2b08 cmp r3, #8
  4686. 8006786: d086 beq.n 8006696 <HAL_RCC_ClockConfig+0x1e>
  4687. if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
  4688. 8006788: f7fe feaa bl 80054e0 <HAL_GetTick>
  4689. 800678c: 1bc0 subs r0, r0, r7
  4690. 800678e: 4540 cmp r0, r8
  4691. 8006790: d9f5 bls.n 800677e <HAL_RCC_ClockConfig+0x106>
  4692. 8006792: e7e7 b.n 8006764 <HAL_RCC_ClockConfig+0xec>
  4693. if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
  4694. 8006794: f7fe fea4 bl 80054e0 <HAL_GetTick>
  4695. 8006798: 1bc0 subs r0, r0, r7
  4696. 800679a: 4540 cmp r0, r8
  4697. 800679c: d8e2 bhi.n 8006764 <HAL_RCC_ClockConfig+0xec>
  4698. while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
  4699. 800679e: 6863 ldr r3, [r4, #4]
  4700. 80067a0: f013 0f0c tst.w r3, #12
  4701. 80067a4: d1f6 bne.n 8006794 <HAL_RCC_ClockConfig+0x11c>
  4702. 80067a6: e776 b.n 8006696 <HAL_RCC_ClockConfig+0x1e>
  4703. __HAL_FLASH_SET_LATENCY(FLatency);
  4704. 80067a8: 6813 ldr r3, [r2, #0]
  4705. 80067aa: f023 0307 bic.w r3, r3, #7
  4706. 80067ae: 4333 orrs r3, r6
  4707. 80067b0: 6013 str r3, [r2, #0]
  4708. if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
  4709. 80067b2: 6813 ldr r3, [r2, #0]
  4710. 80067b4: f003 0307 and.w r3, r3, #7
  4711. 80067b8: 429e cmp r6, r3
  4712. 80067ba: d19c bne.n 80066f6 <HAL_RCC_ClockConfig+0x7e>
  4713. 80067bc: e772 b.n 80066a4 <HAL_RCC_ClockConfig+0x2c>
  4714. MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
  4715. 80067be: 6863 ldr r3, [r4, #4]
  4716. 80067c0: 68e9 ldr r1, [r5, #12]
  4717. 80067c2: f423 63e0 bic.w r3, r3, #1792 ; 0x700
  4718. 80067c6: 430b orrs r3, r1
  4719. 80067c8: 6063 str r3, [r4, #4]
  4720. 80067ca: e771 b.n 80066b0 <HAL_RCC_ClockConfig+0x38>
  4721. 80067cc: 40022000 .word 0x40022000
  4722. 80067d0: 40021000 .word 0x40021000
  4723. 80067d4: 0800bcc7 .word 0x0800bcc7
  4724. 80067d8: 20000200 .word 0x20000200
  4725. 080067dc <HAL_RCC_GetPCLK1Freq>:
  4726. return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
  4727. 80067dc: 4b04 ldr r3, [pc, #16] ; (80067f0 <HAL_RCC_GetPCLK1Freq+0x14>)
  4728. 80067de: 4a05 ldr r2, [pc, #20] ; (80067f4 <HAL_RCC_GetPCLK1Freq+0x18>)
  4729. 80067e0: 685b ldr r3, [r3, #4]
  4730. 80067e2: f3c3 2302 ubfx r3, r3, #8, #3
  4731. 80067e6: 5cd3 ldrb r3, [r2, r3]
  4732. 80067e8: 4a03 ldr r2, [pc, #12] ; (80067f8 <HAL_RCC_GetPCLK1Freq+0x1c>)
  4733. 80067ea: 6810 ldr r0, [r2, #0]
  4734. }
  4735. 80067ec: 40d8 lsrs r0, r3
  4736. 80067ee: 4770 bx lr
  4737. 80067f0: 40021000 .word 0x40021000
  4738. 80067f4: 0800bcd7 .word 0x0800bcd7
  4739. 80067f8: 20000200 .word 0x20000200
  4740. 080067fc <HAL_RCC_GetPCLK2Freq>:
  4741. return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
  4742. 80067fc: 4b04 ldr r3, [pc, #16] ; (8006810 <HAL_RCC_GetPCLK2Freq+0x14>)
  4743. 80067fe: 4a05 ldr r2, [pc, #20] ; (8006814 <HAL_RCC_GetPCLK2Freq+0x18>)
  4744. 8006800: 685b ldr r3, [r3, #4]
  4745. 8006802: f3c3 23c2 ubfx r3, r3, #11, #3
  4746. 8006806: 5cd3 ldrb r3, [r2, r3]
  4747. 8006808: 4a03 ldr r2, [pc, #12] ; (8006818 <HAL_RCC_GetPCLK2Freq+0x1c>)
  4748. 800680a: 6810 ldr r0, [r2, #0]
  4749. }
  4750. 800680c: 40d8 lsrs r0, r3
  4751. 800680e: 4770 bx lr
  4752. 8006810: 40021000 .word 0x40021000
  4753. 8006814: 0800bcd7 .word 0x0800bcd7
  4754. 8006818: 20000200 .word 0x20000200
  4755. 0800681c <HAL_RCCEx_PeriphCLKConfig>:
  4756. /* Check the parameters */
  4757. assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
  4758. /*------------------------------- RTC/LCD Configuration ------------------------*/
  4759. if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
  4760. 800681c: 6803 ldr r3, [r0, #0]
  4761. {
  4762. 800681e: e92d 41f3 stmdb sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
  4763. if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
  4764. 8006822: 07d9 lsls r1, r3, #31
  4765. {
  4766. 8006824: 4605 mov r5, r0
  4767. if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
  4768. 8006826: d520 bpl.n 800686a <HAL_RCCEx_PeriphCLKConfig+0x4e>
  4769. FlagStatus pwrclkchanged = RESET;
  4770. /* As soon as function is called to change RTC clock source, activation of the
  4771. power domain is done. */
  4772. /* Requires to enable write access to Backup Domain of necessary */
  4773. if(__HAL_RCC_PWR_IS_CLK_DISABLED())
  4774. 8006828: 4c35 ldr r4, [pc, #212] ; (8006900 <HAL_RCCEx_PeriphCLKConfig+0xe4>)
  4775. 800682a: 69e3 ldr r3, [r4, #28]
  4776. 800682c: 00da lsls r2, r3, #3
  4777. 800682e: d432 bmi.n 8006896 <HAL_RCCEx_PeriphCLKConfig+0x7a>
  4778. {
  4779. __HAL_RCC_PWR_CLK_ENABLE();
  4780. pwrclkchanged = SET;
  4781. 8006830: 2701 movs r7, #1
  4782. __HAL_RCC_PWR_CLK_ENABLE();
  4783. 8006832: 69e3 ldr r3, [r4, #28]
  4784. 8006834: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
  4785. 8006838: 61e3 str r3, [r4, #28]
  4786. 800683a: 69e3 ldr r3, [r4, #28]
  4787. 800683c: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
  4788. 8006840: 9301 str r3, [sp, #4]
  4789. 8006842: 9b01 ldr r3, [sp, #4]
  4790. }
  4791. if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
  4792. 8006844: 4e2f ldr r6, [pc, #188] ; (8006904 <HAL_RCCEx_PeriphCLKConfig+0xe8>)
  4793. 8006846: 6833 ldr r3, [r6, #0]
  4794. 8006848: 05db lsls r3, r3, #23
  4795. 800684a: d526 bpl.n 800689a <HAL_RCCEx_PeriphCLKConfig+0x7e>
  4796. }
  4797. }
  4798. }
  4799. /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
  4800. temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
  4801. 800684c: 6a23 ldr r3, [r4, #32]
  4802. if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
  4803. 800684e: f413 7340 ands.w r3, r3, #768 ; 0x300
  4804. 8006852: d136 bne.n 80068c2 <HAL_RCCEx_PeriphCLKConfig+0xa6>
  4805. return HAL_TIMEOUT;
  4806. }
  4807. }
  4808. }
  4809. }
  4810. __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
  4811. 8006854: 6a23 ldr r3, [r4, #32]
  4812. 8006856: 686a ldr r2, [r5, #4]
  4813. 8006858: f423 7340 bic.w r3, r3, #768 ; 0x300
  4814. 800685c: 4313 orrs r3, r2
  4815. 800685e: 6223 str r3, [r4, #32]
  4816. /* Require to disable power clock if necessary */
  4817. if(pwrclkchanged == SET)
  4818. 8006860: b11f cbz r7, 800686a <HAL_RCCEx_PeriphCLKConfig+0x4e>
  4819. {
  4820. __HAL_RCC_PWR_CLK_DISABLE();
  4821. 8006862: 69e3 ldr r3, [r4, #28]
  4822. 8006864: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
  4823. 8006868: 61e3 str r3, [r4, #28]
  4824. }
  4825. }
  4826. /*------------------------------ ADC clock Configuration ------------------*/
  4827. if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
  4828. 800686a: 6828 ldr r0, [r5, #0]
  4829. 800686c: 0783 lsls r3, r0, #30
  4830. 800686e: d506 bpl.n 800687e <HAL_RCCEx_PeriphCLKConfig+0x62>
  4831. {
  4832. /* Check the parameters */
  4833. assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection));
  4834. /* Configure the ADC clock source */
  4835. __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
  4836. 8006870: 4a23 ldr r2, [pc, #140] ; (8006900 <HAL_RCCEx_PeriphCLKConfig+0xe4>)
  4837. 8006872: 68a9 ldr r1, [r5, #8]
  4838. 8006874: 6853 ldr r3, [r2, #4]
  4839. 8006876: f423 4340 bic.w r3, r3, #49152 ; 0xc000
  4840. 800687a: 430b orrs r3, r1
  4841. 800687c: 6053 str r3, [r2, #4]
  4842. #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
  4843. || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
  4844. || defined(STM32F105xC) || defined(STM32F107xC)
  4845. /*------------------------------ USB clock Configuration ------------------*/
  4846. if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
  4847. 800687e: f010 0010 ands.w r0, r0, #16
  4848. 8006882: d01b beq.n 80068bc <HAL_RCCEx_PeriphCLKConfig+0xa0>
  4849. {
  4850. /* Check the parameters */
  4851. assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection));
  4852. /* Configure the USB clock source */
  4853. __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
  4854. 8006884: 4a1e ldr r2, [pc, #120] ; (8006900 <HAL_RCCEx_PeriphCLKConfig+0xe4>)
  4855. 8006886: 6969 ldr r1, [r5, #20]
  4856. 8006888: 6853 ldr r3, [r2, #4]
  4857. }
  4858. #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
  4859. return HAL_OK;
  4860. 800688a: 2000 movs r0, #0
  4861. __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
  4862. 800688c: f423 0380 bic.w r3, r3, #4194304 ; 0x400000
  4863. 8006890: 430b orrs r3, r1
  4864. 8006892: 6053 str r3, [r2, #4]
  4865. 8006894: e012 b.n 80068bc <HAL_RCCEx_PeriphCLKConfig+0xa0>
  4866. FlagStatus pwrclkchanged = RESET;
  4867. 8006896: 2700 movs r7, #0
  4868. 8006898: e7d4 b.n 8006844 <HAL_RCCEx_PeriphCLKConfig+0x28>
  4869. SET_BIT(PWR->CR, PWR_CR_DBP);
  4870. 800689a: 6833 ldr r3, [r6, #0]
  4871. 800689c: f443 7380 orr.w r3, r3, #256 ; 0x100
  4872. 80068a0: 6033 str r3, [r6, #0]
  4873. tickstart = HAL_GetTick();
  4874. 80068a2: f7fe fe1d bl 80054e0 <HAL_GetTick>
  4875. 80068a6: 4680 mov r8, r0
  4876. while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
  4877. 80068a8: 6833 ldr r3, [r6, #0]
  4878. 80068aa: 05d8 lsls r0, r3, #23
  4879. 80068ac: d4ce bmi.n 800684c <HAL_RCCEx_PeriphCLKConfig+0x30>
  4880. if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
  4881. 80068ae: f7fe fe17 bl 80054e0 <HAL_GetTick>
  4882. 80068b2: eba0 0008 sub.w r0, r0, r8
  4883. 80068b6: 2864 cmp r0, #100 ; 0x64
  4884. 80068b8: d9f6 bls.n 80068a8 <HAL_RCCEx_PeriphCLKConfig+0x8c>
  4885. return HAL_TIMEOUT;
  4886. 80068ba: 2003 movs r0, #3
  4887. }
  4888. 80068bc: b002 add sp, #8
  4889. 80068be: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
  4890. if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
  4891. 80068c2: 686a ldr r2, [r5, #4]
  4892. 80068c4: f402 7240 and.w r2, r2, #768 ; 0x300
  4893. 80068c8: 4293 cmp r3, r2
  4894. 80068ca: d0c3 beq.n 8006854 <HAL_RCCEx_PeriphCLKConfig+0x38>
  4895. __HAL_RCC_BACKUPRESET_FORCE();
  4896. 80068cc: 2001 movs r0, #1
  4897. 80068ce: 4a0e ldr r2, [pc, #56] ; (8006908 <HAL_RCCEx_PeriphCLKConfig+0xec>)
  4898. temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
  4899. 80068d0: 6a23 ldr r3, [r4, #32]
  4900. __HAL_RCC_BACKUPRESET_FORCE();
  4901. 80068d2: 6010 str r0, [r2, #0]
  4902. __HAL_RCC_BACKUPRESET_RELEASE();
  4903. 80068d4: 2000 movs r0, #0
  4904. temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
  4905. 80068d6: f423 7140 bic.w r1, r3, #768 ; 0x300
  4906. __HAL_RCC_BACKUPRESET_RELEASE();
  4907. 80068da: 6010 str r0, [r2, #0]
  4908. RCC->BDCR = temp_reg;
  4909. 80068dc: 6221 str r1, [r4, #32]
  4910. if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
  4911. 80068de: 07d9 lsls r1, r3, #31
  4912. 80068e0: d5b8 bpl.n 8006854 <HAL_RCCEx_PeriphCLKConfig+0x38>
  4913. tickstart = HAL_GetTick();
  4914. 80068e2: f7fe fdfd bl 80054e0 <HAL_GetTick>
  4915. if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
  4916. 80068e6: f241 3888 movw r8, #5000 ; 0x1388
  4917. tickstart = HAL_GetTick();
  4918. 80068ea: 4606 mov r6, r0
  4919. while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
  4920. 80068ec: 6a23 ldr r3, [r4, #32]
  4921. 80068ee: 079a lsls r2, r3, #30
  4922. 80068f0: d4b0 bmi.n 8006854 <HAL_RCCEx_PeriphCLKConfig+0x38>
  4923. if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
  4924. 80068f2: f7fe fdf5 bl 80054e0 <HAL_GetTick>
  4925. 80068f6: 1b80 subs r0, r0, r6
  4926. 80068f8: 4540 cmp r0, r8
  4927. 80068fa: d9f7 bls.n 80068ec <HAL_RCCEx_PeriphCLKConfig+0xd0>
  4928. 80068fc: e7dd b.n 80068ba <HAL_RCCEx_PeriphCLKConfig+0x9e>
  4929. 80068fe: bf00 nop
  4930. 8006900: 40021000 .word 0x40021000
  4931. 8006904: 40007000 .word 0x40007000
  4932. 8006908: 42420440 .word 0x42420440
  4933. 0800690c <HAL_RCCEx_GetPeriphCLKFreq>:
  4934. * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
  4935. @endif
  4936. * @retval Frequency in Hz (0: means that no available frequency for the peripheral)
  4937. */
  4938. uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
  4939. {
  4940. 800690c: 4602 mov r2, r0
  4941. 800690e: b570 push {r4, r5, r6, lr}
  4942. uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U;
  4943. uint32_t pll2mul = 0U, pll3mul = 0U, prediv2 = 0U;
  4944. #endif /* STM32F105xC || STM32F107xC */
  4945. #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || \
  4946. defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
  4947. const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
  4948. 8006910: 4b3b ldr r3, [pc, #236] ; (8006a00 <HAL_RCCEx_GetPeriphCLKFreq+0xf4>)
  4949. {
  4950. 8006912: b086 sub sp, #24
  4951. const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
  4952. 8006914: ad02 add r5, sp, #8
  4953. 8006916: f103 0610 add.w r6, r3, #16
  4954. 800691a: 462c mov r4, r5
  4955. 800691c: 6818 ldr r0, [r3, #0]
  4956. 800691e: 6859 ldr r1, [r3, #4]
  4957. 8006920: 3308 adds r3, #8
  4958. 8006922: c403 stmia r4!, {r0, r1}
  4959. 8006924: 42b3 cmp r3, r6
  4960. 8006926: 4625 mov r5, r4
  4961. 8006928: d1f7 bne.n 800691a <HAL_RCCEx_GetPeriphCLKFreq+0xe>
  4962. const uint8_t aPredivFactorTable[2] = {1, 2};
  4963. 800692a: 2301 movs r3, #1
  4964. 800692c: f88d 3004 strb.w r3, [sp, #4]
  4965. 8006930: 2302 movs r3, #2
  4966. uint32_t temp_reg = 0U, frequency = 0U;
  4967. /* Check the parameters */
  4968. assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
  4969. switch (PeriphClk)
  4970. 8006932: 1e50 subs r0, r2, #1
  4971. const uint8_t aPredivFactorTable[2] = {1, 2};
  4972. 8006934: f88d 3005 strb.w r3, [sp, #5]
  4973. switch (PeriphClk)
  4974. 8006938: 280f cmp r0, #15
  4975. 800693a: d85e bhi.n 80069fa <HAL_RCCEx_GetPeriphCLKFreq+0xee>
  4976. 800693c: e8df f000 tbb [pc, r0]
  4977. 8006940: 2d5d5132 .word 0x2d5d5132
  4978. 8006944: 2d5d5d5d .word 0x2d5d5d5d
  4979. 8006948: 5d5d5d5d .word 0x5d5d5d5d
  4980. 800694c: 085d5d5d .word 0x085d5d5d
  4981. || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
  4982. || defined(STM32F105xC) || defined(STM32F107xC)
  4983. case RCC_PERIPHCLK_USB:
  4984. {
  4985. /* Get RCC configuration ------------------------------------------------------*/
  4986. temp_reg = RCC->CFGR;
  4987. 8006950: 4b2c ldr r3, [pc, #176] ; (8006a04 <HAL_RCCEx_GetPeriphCLKFreq+0xf8>)
  4988. 8006952: 6859 ldr r1, [r3, #4]
  4989. /* Check if PLL is enabled */
  4990. if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLLON))
  4991. 8006954: 6818 ldr r0, [r3, #0]
  4992. 8006956: f010 7080 ands.w r0, r0, #16777216 ; 0x1000000
  4993. 800695a: d037 beq.n 80069cc <HAL_RCCEx_GetPeriphCLKFreq+0xc0>
  4994. {
  4995. pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
  4996. 800695c: f3c1 4283 ubfx r2, r1, #18, #4
  4997. 8006960: a806 add r0, sp, #24
  4998. 8006962: 4402 add r2, r0
  4999. 8006964: f812 0c10 ldrb.w r0, [r2, #-16]
  5000. if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
  5001. 8006968: 03ca lsls r2, r1, #15
  5002. {
  5003. #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
  5004. || defined(STM32F100xE)
  5005. prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
  5006. #else
  5007. prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
  5008. 800696a: bf41 itttt mi
  5009. 800696c: 685a ldrmi r2, [r3, #4]
  5010. 800696e: a906 addmi r1, sp, #24
  5011. 8006970: f3c2 4240 ubfxmi r2, r2, #17, #1
  5012. 8006974: 1852 addmi r2, r2, r1
  5013. 8006976: bf44 itt mi
  5014. 8006978: f812 1c14 ldrbmi.w r1, [r2, #-20]
  5015. }
  5016. #else
  5017. if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
  5018. {
  5019. /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
  5020. pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
  5021. 800697c: 4a22 ldrmi r2, [pc, #136] ; (8006a08 <HAL_RCCEx_GetPeriphCLKFreq+0xfc>)
  5022. /* Prescaler of 3 selected for USB */
  5023. frequency = (2 * pllclk) / 3;
  5024. }
  5025. #else
  5026. /* USBCLK = PLLCLK / USB prescaler */
  5027. if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL)
  5028. 800697e: 685b ldr r3, [r3, #4]
  5029. pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
  5030. 8006980: bf4c ite mi
  5031. 8006982: fbb2 f2f1 udivmi r2, r2, r1
  5032. pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
  5033. 8006986: 4a21 ldrpl r2, [pc, #132] ; (8006a0c <HAL_RCCEx_GetPeriphCLKFreq+0x100>)
  5034. if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL)
  5035. 8006988: 025b lsls r3, r3, #9
  5036. pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
  5037. 800698a: fb02 f000 mul.w r0, r2, r0
  5038. if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL)
  5039. 800698e: d41d bmi.n 80069cc <HAL_RCCEx_GetPeriphCLKFreq+0xc0>
  5040. frequency = pllclk;
  5041. }
  5042. else
  5043. {
  5044. /* Prescaler of 1.5 selected for USB */
  5045. frequency = (pllclk * 2) / 3;
  5046. 8006990: 2303 movs r3, #3
  5047. 8006992: 0040 lsls r0, r0, #1
  5048. }
  5049. break;
  5050. }
  5051. case RCC_PERIPHCLK_ADC:
  5052. {
  5053. frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2);
  5054. 8006994: fbb0 f0f3 udiv r0, r0, r3
  5055. break;
  5056. 8006998: e018 b.n 80069cc <HAL_RCCEx_GetPeriphCLKFreq+0xc0>
  5057. {
  5058. break;
  5059. }
  5060. }
  5061. return(frequency);
  5062. }
  5063. 800699a: b006 add sp, #24
  5064. 800699c: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr}
  5065. frequency = HAL_RCC_GetSysClockFreq();
  5066. 80069a0: f7ff be2e b.w 8006600 <HAL_RCC_GetSysClockFreq>
  5067. if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY)))
  5068. 80069a4: f240 3102 movw r1, #770 ; 0x302
  5069. temp_reg = RCC->BDCR;
  5070. 80069a8: 4a16 ldr r2, [pc, #88] ; (8006a04 <HAL_RCCEx_GetPeriphCLKFreq+0xf8>)
  5071. 80069aa: 6a13 ldr r3, [r2, #32]
  5072. if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY)))
  5073. 80069ac: 4019 ands r1, r3
  5074. 80069ae: f5b1 7f81 cmp.w r1, #258 ; 0x102
  5075. 80069b2: d01f beq.n 80069f4 <HAL_RCCEx_GetPeriphCLKFreq+0xe8>
  5076. else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
  5077. 80069b4: f403 7340 and.w r3, r3, #768 ; 0x300
  5078. 80069b8: f5b3 7f00 cmp.w r3, #512 ; 0x200
  5079. 80069bc: d108 bne.n 80069d0 <HAL_RCCEx_GetPeriphCLKFreq+0xc4>
  5080. frequency = LSI_VALUE;
  5081. 80069be: f649 4040 movw r0, #40000 ; 0x9c40
  5082. else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
  5083. 80069c2: 6a53 ldr r3, [r2, #36] ; 0x24
  5084. frequency = LSI_VALUE;
  5085. 80069c4: f013 0f02 tst.w r3, #2
  5086. frequency = HSE_VALUE / 128U;
  5087. 80069c8: bf08 it eq
  5088. 80069ca: 2000 moveq r0, #0
  5089. }
  5090. 80069cc: b006 add sp, #24
  5091. 80069ce: bd70 pop {r4, r5, r6, pc}
  5092. else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)))
  5093. 80069d0: f5b3 7f40 cmp.w r3, #768 ; 0x300
  5094. 80069d4: d111 bne.n 80069fa <HAL_RCCEx_GetPeriphCLKFreq+0xee>
  5095. 80069d6: 6813 ldr r3, [r2, #0]
  5096. frequency = HSE_VALUE / 128U;
  5097. 80069d8: f24f 4024 movw r0, #62500 ; 0xf424
  5098. 80069dc: f413 3f00 tst.w r3, #131072 ; 0x20000
  5099. 80069e0: e7f2 b.n 80069c8 <HAL_RCCEx_GetPeriphCLKFreq+0xbc>
  5100. frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2);
  5101. 80069e2: f7ff ff0b bl 80067fc <HAL_RCC_GetPCLK2Freq>
  5102. 80069e6: 4b07 ldr r3, [pc, #28] ; (8006a04 <HAL_RCCEx_GetPeriphCLKFreq+0xf8>)
  5103. 80069e8: 685b ldr r3, [r3, #4]
  5104. 80069ea: f3c3 3381 ubfx r3, r3, #14, #2
  5105. 80069ee: 3301 adds r3, #1
  5106. 80069f0: 005b lsls r3, r3, #1
  5107. 80069f2: e7cf b.n 8006994 <HAL_RCCEx_GetPeriphCLKFreq+0x88>
  5108. frequency = LSE_VALUE;
  5109. 80069f4: f44f 4000 mov.w r0, #32768 ; 0x8000
  5110. 80069f8: e7e8 b.n 80069cc <HAL_RCCEx_GetPeriphCLKFreq+0xc0>
  5111. frequency = 0U;
  5112. 80069fa: 2000 movs r0, #0
  5113. 80069fc: e7e6 b.n 80069cc <HAL_RCCEx_GetPeriphCLKFreq+0xc0>
  5114. 80069fe: bf00 nop
  5115. 8006a00: 0800bc58 .word 0x0800bc58
  5116. 8006a04: 40021000 .word 0x40021000
  5117. 8006a08: 007a1200 .word 0x007a1200
  5118. 8006a0c: 003d0900 .word 0x003d0900
  5119. 08006a10 <HAL_TIM_OC_DelayElapsedCallback>:
  5120. 8006a10: 4770 bx lr
  5121. 08006a12 <HAL_TIM_IC_CaptureCallback>:
  5122. 8006a12: 4770 bx lr
  5123. 08006a14 <HAL_TIM_PWM_PulseFinishedCallback>:
  5124. 8006a14: 4770 bx lr
  5125. 08006a16 <HAL_TIM_TriggerCallback>:
  5126. 8006a16: 4770 bx lr
  5127. 08006a18 <HAL_TIM_IRQHandler>:
  5128. * @retval None
  5129. */
  5130. void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
  5131. {
  5132. /* Capture compare 1 event */
  5133. if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
  5134. 8006a18: 6803 ldr r3, [r0, #0]
  5135. {
  5136. 8006a1a: b510 push {r4, lr}
  5137. if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
  5138. 8006a1c: 691a ldr r2, [r3, #16]
  5139. {
  5140. 8006a1e: 4604 mov r4, r0
  5141. if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
  5142. 8006a20: 0791 lsls r1, r2, #30
  5143. 8006a22: d50e bpl.n 8006a42 <HAL_TIM_IRQHandler+0x2a>
  5144. {
  5145. if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
  5146. 8006a24: 68da ldr r2, [r3, #12]
  5147. 8006a26: 0792 lsls r2, r2, #30
  5148. 8006a28: d50b bpl.n 8006a42 <HAL_TIM_IRQHandler+0x2a>
  5149. {
  5150. {
  5151. __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
  5152. 8006a2a: f06f 0202 mvn.w r2, #2
  5153. 8006a2e: 611a str r2, [r3, #16]
  5154. htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
  5155. 8006a30: 2201 movs r2, #1
  5156. /* Input capture event */
  5157. if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
  5158. 8006a32: 699b ldr r3, [r3, #24]
  5159. htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
  5160. 8006a34: 7702 strb r2, [r0, #28]
  5161. if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
  5162. 8006a36: 079b lsls r3, r3, #30
  5163. 8006a38: d077 beq.n 8006b2a <HAL_TIM_IRQHandler+0x112>
  5164. {
  5165. HAL_TIM_IC_CaptureCallback(htim);
  5166. 8006a3a: f7ff ffea bl 8006a12 <HAL_TIM_IC_CaptureCallback>
  5167. else
  5168. {
  5169. HAL_TIM_OC_DelayElapsedCallback(htim);
  5170. HAL_TIM_PWM_PulseFinishedCallback(htim);
  5171. }
  5172. htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  5173. 8006a3e: 2300 movs r3, #0
  5174. 8006a40: 7723 strb r3, [r4, #28]
  5175. }
  5176. }
  5177. }
  5178. /* Capture compare 2 event */
  5179. if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
  5180. 8006a42: 6823 ldr r3, [r4, #0]
  5181. 8006a44: 691a ldr r2, [r3, #16]
  5182. 8006a46: 0750 lsls r0, r2, #29
  5183. 8006a48: d510 bpl.n 8006a6c <HAL_TIM_IRQHandler+0x54>
  5184. {
  5185. if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
  5186. 8006a4a: 68da ldr r2, [r3, #12]
  5187. 8006a4c: 0751 lsls r1, r2, #29
  5188. 8006a4e: d50d bpl.n 8006a6c <HAL_TIM_IRQHandler+0x54>
  5189. {
  5190. __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
  5191. 8006a50: f06f 0204 mvn.w r2, #4
  5192. 8006a54: 611a str r2, [r3, #16]
  5193. htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
  5194. 8006a56: 2202 movs r2, #2
  5195. /* Input capture event */
  5196. if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
  5197. 8006a58: 699b ldr r3, [r3, #24]
  5198. htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
  5199. 8006a5a: 7722 strb r2, [r4, #28]
  5200. if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
  5201. 8006a5c: f413 7f40 tst.w r3, #768 ; 0x300
  5202. {
  5203. HAL_TIM_IC_CaptureCallback(htim);
  5204. 8006a60: 4620 mov r0, r4
  5205. if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
  5206. 8006a62: d068 beq.n 8006b36 <HAL_TIM_IRQHandler+0x11e>
  5207. HAL_TIM_IC_CaptureCallback(htim);
  5208. 8006a64: f7ff ffd5 bl 8006a12 <HAL_TIM_IC_CaptureCallback>
  5209. else
  5210. {
  5211. HAL_TIM_OC_DelayElapsedCallback(htim);
  5212. HAL_TIM_PWM_PulseFinishedCallback(htim);
  5213. }
  5214. htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  5215. 8006a68: 2300 movs r3, #0
  5216. 8006a6a: 7723 strb r3, [r4, #28]
  5217. }
  5218. }
  5219. /* Capture compare 3 event */
  5220. if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
  5221. 8006a6c: 6823 ldr r3, [r4, #0]
  5222. 8006a6e: 691a ldr r2, [r3, #16]
  5223. 8006a70: 0712 lsls r2, r2, #28
  5224. 8006a72: d50f bpl.n 8006a94 <HAL_TIM_IRQHandler+0x7c>
  5225. {
  5226. if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
  5227. 8006a74: 68da ldr r2, [r3, #12]
  5228. 8006a76: 0710 lsls r0, r2, #28
  5229. 8006a78: d50c bpl.n 8006a94 <HAL_TIM_IRQHandler+0x7c>
  5230. {
  5231. __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
  5232. 8006a7a: f06f 0208 mvn.w r2, #8
  5233. 8006a7e: 611a str r2, [r3, #16]
  5234. htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
  5235. 8006a80: 2204 movs r2, #4
  5236. /* Input capture event */
  5237. if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
  5238. 8006a82: 69db ldr r3, [r3, #28]
  5239. htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
  5240. 8006a84: 7722 strb r2, [r4, #28]
  5241. if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
  5242. 8006a86: 0799 lsls r1, r3, #30
  5243. {
  5244. HAL_TIM_IC_CaptureCallback(htim);
  5245. 8006a88: 4620 mov r0, r4
  5246. if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
  5247. 8006a8a: d05a beq.n 8006b42 <HAL_TIM_IRQHandler+0x12a>
  5248. HAL_TIM_IC_CaptureCallback(htim);
  5249. 8006a8c: f7ff ffc1 bl 8006a12 <HAL_TIM_IC_CaptureCallback>
  5250. else
  5251. {
  5252. HAL_TIM_OC_DelayElapsedCallback(htim);
  5253. HAL_TIM_PWM_PulseFinishedCallback(htim);
  5254. }
  5255. htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  5256. 8006a90: 2300 movs r3, #0
  5257. 8006a92: 7723 strb r3, [r4, #28]
  5258. }
  5259. }
  5260. /* Capture compare 4 event */
  5261. if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
  5262. 8006a94: 6823 ldr r3, [r4, #0]
  5263. 8006a96: 691a ldr r2, [r3, #16]
  5264. 8006a98: 06d2 lsls r2, r2, #27
  5265. 8006a9a: d510 bpl.n 8006abe <HAL_TIM_IRQHandler+0xa6>
  5266. {
  5267. if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
  5268. 8006a9c: 68da ldr r2, [r3, #12]
  5269. 8006a9e: 06d0 lsls r0, r2, #27
  5270. 8006aa0: d50d bpl.n 8006abe <HAL_TIM_IRQHandler+0xa6>
  5271. {
  5272. __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
  5273. 8006aa2: f06f 0210 mvn.w r2, #16
  5274. 8006aa6: 611a str r2, [r3, #16]
  5275. htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
  5276. 8006aa8: 2208 movs r2, #8
  5277. /* Input capture event */
  5278. if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
  5279. 8006aaa: 69db ldr r3, [r3, #28]
  5280. htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
  5281. 8006aac: 7722 strb r2, [r4, #28]
  5282. if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
  5283. 8006aae: f413 7f40 tst.w r3, #768 ; 0x300
  5284. {
  5285. HAL_TIM_IC_CaptureCallback(htim);
  5286. 8006ab2: 4620 mov r0, r4
  5287. if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
  5288. 8006ab4: d04b beq.n 8006b4e <HAL_TIM_IRQHandler+0x136>
  5289. HAL_TIM_IC_CaptureCallback(htim);
  5290. 8006ab6: f7ff ffac bl 8006a12 <HAL_TIM_IC_CaptureCallback>
  5291. else
  5292. {
  5293. HAL_TIM_OC_DelayElapsedCallback(htim);
  5294. HAL_TIM_PWM_PulseFinishedCallback(htim);
  5295. }
  5296. htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
  5297. 8006aba: 2300 movs r3, #0
  5298. 8006abc: 7723 strb r3, [r4, #28]
  5299. }
  5300. }
  5301. /* TIM Update event */
  5302. if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
  5303. 8006abe: 6823 ldr r3, [r4, #0]
  5304. 8006ac0: 691a ldr r2, [r3, #16]
  5305. 8006ac2: 07d1 lsls r1, r2, #31
  5306. 8006ac4: d508 bpl.n 8006ad8 <HAL_TIM_IRQHandler+0xc0>
  5307. {
  5308. if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
  5309. 8006ac6: 68da ldr r2, [r3, #12]
  5310. 8006ac8: 07d2 lsls r2, r2, #31
  5311. 8006aca: d505 bpl.n 8006ad8 <HAL_TIM_IRQHandler+0xc0>
  5312. {
  5313. __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
  5314. 8006acc: f06f 0201 mvn.w r2, #1
  5315. HAL_TIM_PeriodElapsedCallback(htim);
  5316. 8006ad0: 4620 mov r0, r4
  5317. __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
  5318. 8006ad2: 611a str r2, [r3, #16]
  5319. HAL_TIM_PeriodElapsedCallback(htim);
  5320. 8006ad4: f001 f9a6 bl 8007e24 <HAL_TIM_PeriodElapsedCallback>
  5321. }
  5322. }
  5323. /* TIM Break input event */
  5324. if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
  5325. 8006ad8: 6823 ldr r3, [r4, #0]
  5326. 8006ada: 691a ldr r2, [r3, #16]
  5327. 8006adc: 0610 lsls r0, r2, #24
  5328. 8006ade: d508 bpl.n 8006af2 <HAL_TIM_IRQHandler+0xda>
  5329. {
  5330. if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
  5331. 8006ae0: 68da ldr r2, [r3, #12]
  5332. 8006ae2: 0611 lsls r1, r2, #24
  5333. 8006ae4: d505 bpl.n 8006af2 <HAL_TIM_IRQHandler+0xda>
  5334. {
  5335. __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
  5336. 8006ae6: f06f 0280 mvn.w r2, #128 ; 0x80
  5337. HAL_TIMEx_BreakCallback(htim);
  5338. 8006aea: 4620 mov r0, r4
  5339. __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
  5340. 8006aec: 611a str r2, [r3, #16]
  5341. HAL_TIMEx_BreakCallback(htim);
  5342. 8006aee: f000 f8be bl 8006c6e <HAL_TIMEx_BreakCallback>
  5343. }
  5344. }
  5345. /* TIM Trigger detection event */
  5346. if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
  5347. 8006af2: 6823 ldr r3, [r4, #0]
  5348. 8006af4: 691a ldr r2, [r3, #16]
  5349. 8006af6: 0652 lsls r2, r2, #25
  5350. 8006af8: d508 bpl.n 8006b0c <HAL_TIM_IRQHandler+0xf4>
  5351. {
  5352. if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
  5353. 8006afa: 68da ldr r2, [r3, #12]
  5354. 8006afc: 0650 lsls r0, r2, #25
  5355. 8006afe: d505 bpl.n 8006b0c <HAL_TIM_IRQHandler+0xf4>
  5356. {
  5357. __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
  5358. 8006b00: f06f 0240 mvn.w r2, #64 ; 0x40
  5359. HAL_TIM_TriggerCallback(htim);
  5360. 8006b04: 4620 mov r0, r4
  5361. __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
  5362. 8006b06: 611a str r2, [r3, #16]
  5363. HAL_TIM_TriggerCallback(htim);
  5364. 8006b08: f7ff ff85 bl 8006a16 <HAL_TIM_TriggerCallback>
  5365. }
  5366. }
  5367. /* TIM commutation event */
  5368. if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
  5369. 8006b0c: 6823 ldr r3, [r4, #0]
  5370. 8006b0e: 691a ldr r2, [r3, #16]
  5371. 8006b10: 0691 lsls r1, r2, #26
  5372. 8006b12: d522 bpl.n 8006b5a <HAL_TIM_IRQHandler+0x142>
  5373. {
  5374. if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
  5375. 8006b14: 68da ldr r2, [r3, #12]
  5376. 8006b16: 0692 lsls r2, r2, #26
  5377. 8006b18: d51f bpl.n 8006b5a <HAL_TIM_IRQHandler+0x142>
  5378. {
  5379. __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
  5380. 8006b1a: f06f 0220 mvn.w r2, #32
  5381. HAL_TIMEx_CommutationCallback(htim);
  5382. 8006b1e: 4620 mov r0, r4
  5383. }
  5384. }
  5385. }
  5386. 8006b20: e8bd 4010 ldmia.w sp!, {r4, lr}
  5387. __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
  5388. 8006b24: 611a str r2, [r3, #16]
  5389. HAL_TIMEx_CommutationCallback(htim);
  5390. 8006b26: f000 b8a1 b.w 8006c6c <HAL_TIMEx_CommutationCallback>
  5391. HAL_TIM_OC_DelayElapsedCallback(htim);
  5392. 8006b2a: f7ff ff71 bl 8006a10 <HAL_TIM_OC_DelayElapsedCallback>
  5393. HAL_TIM_PWM_PulseFinishedCallback(htim);
  5394. 8006b2e: 4620 mov r0, r4
  5395. 8006b30: f7ff ff70 bl 8006a14 <HAL_TIM_PWM_PulseFinishedCallback>
  5396. 8006b34: e783 b.n 8006a3e <HAL_TIM_IRQHandler+0x26>
  5397. HAL_TIM_OC_DelayElapsedCallback(htim);
  5398. 8006b36: f7ff ff6b bl 8006a10 <HAL_TIM_OC_DelayElapsedCallback>
  5399. HAL_TIM_PWM_PulseFinishedCallback(htim);
  5400. 8006b3a: 4620 mov r0, r4
  5401. 8006b3c: f7ff ff6a bl 8006a14 <HAL_TIM_PWM_PulseFinishedCallback>
  5402. 8006b40: e792 b.n 8006a68 <HAL_TIM_IRQHandler+0x50>
  5403. HAL_TIM_OC_DelayElapsedCallback(htim);
  5404. 8006b42: f7ff ff65 bl 8006a10 <HAL_TIM_OC_DelayElapsedCallback>
  5405. HAL_TIM_PWM_PulseFinishedCallback(htim);
  5406. 8006b46: 4620 mov r0, r4
  5407. 8006b48: f7ff ff64 bl 8006a14 <HAL_TIM_PWM_PulseFinishedCallback>
  5408. 8006b4c: e7a0 b.n 8006a90 <HAL_TIM_IRQHandler+0x78>
  5409. HAL_TIM_OC_DelayElapsedCallback(htim);
  5410. 8006b4e: f7ff ff5f bl 8006a10 <HAL_TIM_OC_DelayElapsedCallback>
  5411. HAL_TIM_PWM_PulseFinishedCallback(htim);
  5412. 8006b52: 4620 mov r0, r4
  5413. 8006b54: f7ff ff5e bl 8006a14 <HAL_TIM_PWM_PulseFinishedCallback>
  5414. 8006b58: e7af b.n 8006aba <HAL_TIM_IRQHandler+0xa2>
  5415. 8006b5a: bd10 pop {r4, pc}
  5416. 08006b5c <TIM_Base_SetConfig>:
  5417. {
  5418. uint32_t tmpcr1 = 0U;
  5419. tmpcr1 = TIMx->CR1;
  5420. /* Set TIM Time Base Unit parameters ---------------------------------------*/
  5421. if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
  5422. 8006b5c: 4a24 ldr r2, [pc, #144] ; (8006bf0 <TIM_Base_SetConfig+0x94>)
  5423. tmpcr1 = TIMx->CR1;
  5424. 8006b5e: 6803 ldr r3, [r0, #0]
  5425. if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
  5426. 8006b60: 4290 cmp r0, r2
  5427. 8006b62: d012 beq.n 8006b8a <TIM_Base_SetConfig+0x2e>
  5428. 8006b64: f502 6200 add.w r2, r2, #2048 ; 0x800
  5429. 8006b68: 4290 cmp r0, r2
  5430. 8006b6a: d00e beq.n 8006b8a <TIM_Base_SetConfig+0x2e>
  5431. 8006b6c: f1b0 4f80 cmp.w r0, #1073741824 ; 0x40000000
  5432. 8006b70: d00b beq.n 8006b8a <TIM_Base_SetConfig+0x2e>
  5433. 8006b72: f5a2 3298 sub.w r2, r2, #77824 ; 0x13000
  5434. 8006b76: 4290 cmp r0, r2
  5435. 8006b78: d007 beq.n 8006b8a <TIM_Base_SetConfig+0x2e>
  5436. 8006b7a: f502 6280 add.w r2, r2, #1024 ; 0x400
  5437. 8006b7e: 4290 cmp r0, r2
  5438. 8006b80: d003 beq.n 8006b8a <TIM_Base_SetConfig+0x2e>
  5439. 8006b82: f502 6280 add.w r2, r2, #1024 ; 0x400
  5440. 8006b86: 4290 cmp r0, r2
  5441. 8006b88: d11d bne.n 8006bc6 <TIM_Base_SetConfig+0x6a>
  5442. {
  5443. /* Select the Counter Mode */
  5444. tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
  5445. tmpcr1 |= Structure->CounterMode;
  5446. 8006b8a: 684a ldr r2, [r1, #4]
  5447. tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
  5448. 8006b8c: f023 0370 bic.w r3, r3, #112 ; 0x70
  5449. tmpcr1 |= Structure->CounterMode;
  5450. 8006b90: 4313 orrs r3, r2
  5451. }
  5452. if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
  5453. 8006b92: 4a17 ldr r2, [pc, #92] ; (8006bf0 <TIM_Base_SetConfig+0x94>)
  5454. 8006b94: 4290 cmp r0, r2
  5455. 8006b96: d012 beq.n 8006bbe <TIM_Base_SetConfig+0x62>
  5456. 8006b98: f502 6200 add.w r2, r2, #2048 ; 0x800
  5457. 8006b9c: 4290 cmp r0, r2
  5458. 8006b9e: d00e beq.n 8006bbe <TIM_Base_SetConfig+0x62>
  5459. 8006ba0: f1b0 4f80 cmp.w r0, #1073741824 ; 0x40000000
  5460. 8006ba4: d00b beq.n 8006bbe <TIM_Base_SetConfig+0x62>
  5461. 8006ba6: f5a2 3298 sub.w r2, r2, #77824 ; 0x13000
  5462. 8006baa: 4290 cmp r0, r2
  5463. 8006bac: d007 beq.n 8006bbe <TIM_Base_SetConfig+0x62>
  5464. 8006bae: f502 6280 add.w r2, r2, #1024 ; 0x400
  5465. 8006bb2: 4290 cmp r0, r2
  5466. 8006bb4: d003 beq.n 8006bbe <TIM_Base_SetConfig+0x62>
  5467. 8006bb6: f502 6280 add.w r2, r2, #1024 ; 0x400
  5468. 8006bba: 4290 cmp r0, r2
  5469. 8006bbc: d103 bne.n 8006bc6 <TIM_Base_SetConfig+0x6a>
  5470. {
  5471. /* Set the clock division */
  5472. tmpcr1 &= ~TIM_CR1_CKD;
  5473. tmpcr1 |= (uint32_t)Structure->ClockDivision;
  5474. 8006bbe: 68ca ldr r2, [r1, #12]
  5475. tmpcr1 &= ~TIM_CR1_CKD;
  5476. 8006bc0: f423 7340 bic.w r3, r3, #768 ; 0x300
  5477. tmpcr1 |= (uint32_t)Structure->ClockDivision;
  5478. 8006bc4: 4313 orrs r3, r2
  5479. }
  5480. /* Set the auto-reload preload */
  5481. tmpcr1 &= ~TIM_CR1_ARPE;
  5482. tmpcr1 |= (uint32_t)Structure->AutoReloadPreload;
  5483. 8006bc6: 694a ldr r2, [r1, #20]
  5484. tmpcr1 &= ~TIM_CR1_ARPE;
  5485. 8006bc8: f023 0380 bic.w r3, r3, #128 ; 0x80
  5486. tmpcr1 |= (uint32_t)Structure->AutoReloadPreload;
  5487. 8006bcc: 4313 orrs r3, r2
  5488. TIMx->CR1 = tmpcr1;
  5489. 8006bce: 6003 str r3, [r0, #0]
  5490. /* Set the Autoreload value */
  5491. TIMx->ARR = (uint32_t)Structure->Period ;
  5492. 8006bd0: 688b ldr r3, [r1, #8]
  5493. 8006bd2: 62c3 str r3, [r0, #44] ; 0x2c
  5494. /* Set the Prescaler value */
  5495. TIMx->PSC = (uint32_t)Structure->Prescaler;
  5496. 8006bd4: 680b ldr r3, [r1, #0]
  5497. 8006bd6: 6283 str r3, [r0, #40] ; 0x28
  5498. if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
  5499. 8006bd8: 4b05 ldr r3, [pc, #20] ; (8006bf0 <TIM_Base_SetConfig+0x94>)
  5500. 8006bda: 4298 cmp r0, r3
  5501. 8006bdc: d003 beq.n 8006be6 <TIM_Base_SetConfig+0x8a>
  5502. 8006bde: f503 6300 add.w r3, r3, #2048 ; 0x800
  5503. 8006be2: 4298 cmp r0, r3
  5504. 8006be4: d101 bne.n 8006bea <TIM_Base_SetConfig+0x8e>
  5505. {
  5506. /* Set the Repetition Counter value */
  5507. TIMx->RCR = Structure->RepetitionCounter;
  5508. 8006be6: 690b ldr r3, [r1, #16]
  5509. 8006be8: 6303 str r3, [r0, #48] ; 0x30
  5510. }
  5511. /* Generate an update event to reload the Prescaler
  5512. and the repetition counter(only for TIM1 and TIM8) value immediatly */
  5513. TIMx->EGR = TIM_EGR_UG;
  5514. 8006bea: 2301 movs r3, #1
  5515. 8006bec: 6143 str r3, [r0, #20]
  5516. 8006bee: 4770 bx lr
  5517. 8006bf0: 40012c00 .word 0x40012c00
  5518. 08006bf4 <HAL_TIM_Base_Init>:
  5519. {
  5520. 8006bf4: b510 push {r4, lr}
  5521. if(htim == NULL)
  5522. 8006bf6: 4604 mov r4, r0
  5523. 8006bf8: b1a0 cbz r0, 8006c24 <HAL_TIM_Base_Init+0x30>
  5524. if(htim->State == HAL_TIM_STATE_RESET)
  5525. 8006bfa: f890 303d ldrb.w r3, [r0, #61] ; 0x3d
  5526. 8006bfe: f003 02ff and.w r2, r3, #255 ; 0xff
  5527. 8006c02: b91b cbnz r3, 8006c0c <HAL_TIM_Base_Init+0x18>
  5528. htim->Lock = HAL_UNLOCKED;
  5529. 8006c04: f880 203c strb.w r2, [r0, #60] ; 0x3c
  5530. HAL_TIM_Base_MspInit(htim);
  5531. 8006c08: f001 fd24 bl 8008654 <HAL_TIM_Base_MspInit>
  5532. htim->State= HAL_TIM_STATE_BUSY;
  5533. 8006c0c: 2302 movs r3, #2
  5534. TIM_Base_SetConfig(htim->Instance, &htim->Init);
  5535. 8006c0e: 6820 ldr r0, [r4, #0]
  5536. htim->State= HAL_TIM_STATE_BUSY;
  5537. 8006c10: f884 303d strb.w r3, [r4, #61] ; 0x3d
  5538. TIM_Base_SetConfig(htim->Instance, &htim->Init);
  5539. 8006c14: 1d21 adds r1, r4, #4
  5540. 8006c16: f7ff ffa1 bl 8006b5c <TIM_Base_SetConfig>
  5541. htim->State= HAL_TIM_STATE_READY;
  5542. 8006c1a: 2301 movs r3, #1
  5543. return HAL_OK;
  5544. 8006c1c: 2000 movs r0, #0
  5545. htim->State= HAL_TIM_STATE_READY;
  5546. 8006c1e: f884 303d strb.w r3, [r4, #61] ; 0x3d
  5547. return HAL_OK;
  5548. 8006c22: bd10 pop {r4, pc}
  5549. return HAL_ERROR;
  5550. 8006c24: 2001 movs r0, #1
  5551. }
  5552. 8006c26: bd10 pop {r4, pc}
  5553. 08006c28 <HAL_TIMEx_MasterConfigSynchronization>:
  5554. /* Check the parameters */
  5555. assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
  5556. assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
  5557. assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
  5558. __HAL_LOCK(htim);
  5559. 8006c28: f890 303c ldrb.w r3, [r0, #60] ; 0x3c
  5560. {
  5561. 8006c2c: b510 push {r4, lr}
  5562. __HAL_LOCK(htim);
  5563. 8006c2e: 2b01 cmp r3, #1
  5564. 8006c30: f04f 0302 mov.w r3, #2
  5565. 8006c34: d018 beq.n 8006c68 <HAL_TIMEx_MasterConfigSynchronization+0x40>
  5566. htim->State = HAL_TIM_STATE_BUSY;
  5567. 8006c36: f880 303d strb.w r3, [r0, #61] ; 0x3d
  5568. /* Reset the MMS Bits */
  5569. htim->Instance->CR2 &= ~TIM_CR2_MMS;
  5570. 8006c3a: 6803 ldr r3, [r0, #0]
  5571. /* Select the TRGO source */
  5572. htim->Instance->CR2 |= sMasterConfig->MasterOutputTrigger;
  5573. 8006c3c: 680c ldr r4, [r1, #0]
  5574. htim->Instance->CR2 &= ~TIM_CR2_MMS;
  5575. 8006c3e: 685a ldr r2, [r3, #4]
  5576. /* Reset the MSM Bit */
  5577. htim->Instance->SMCR &= ~TIM_SMCR_MSM;
  5578. /* Set or Reset the MSM Bit */
  5579. htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode;
  5580. 8006c40: 6849 ldr r1, [r1, #4]
  5581. htim->Instance->CR2 &= ~TIM_CR2_MMS;
  5582. 8006c42: f022 0270 bic.w r2, r2, #112 ; 0x70
  5583. 8006c46: 605a str r2, [r3, #4]
  5584. htim->Instance->CR2 |= sMasterConfig->MasterOutputTrigger;
  5585. 8006c48: 685a ldr r2, [r3, #4]
  5586. 8006c4a: 4322 orrs r2, r4
  5587. 8006c4c: 605a str r2, [r3, #4]
  5588. htim->Instance->SMCR &= ~TIM_SMCR_MSM;
  5589. 8006c4e: 689a ldr r2, [r3, #8]
  5590. 8006c50: f022 0280 bic.w r2, r2, #128 ; 0x80
  5591. 8006c54: 609a str r2, [r3, #8]
  5592. htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode;
  5593. 8006c56: 689a ldr r2, [r3, #8]
  5594. 8006c58: 430a orrs r2, r1
  5595. 8006c5a: 609a str r2, [r3, #8]
  5596. htim->State = HAL_TIM_STATE_READY;
  5597. 8006c5c: 2301 movs r3, #1
  5598. 8006c5e: f880 303d strb.w r3, [r0, #61] ; 0x3d
  5599. __HAL_UNLOCK(htim);
  5600. 8006c62: 2300 movs r3, #0
  5601. 8006c64: f880 303c strb.w r3, [r0, #60] ; 0x3c
  5602. __HAL_LOCK(htim);
  5603. 8006c68: 4618 mov r0, r3
  5604. return HAL_OK;
  5605. }
  5606. 8006c6a: bd10 pop {r4, pc}
  5607. 08006c6c <HAL_TIMEx_CommutationCallback>:
  5608. 8006c6c: 4770 bx lr
  5609. 08006c6e <HAL_TIMEx_BreakCallback>:
  5610. * @brief Hall Break detection callback in non blocking mode
  5611. * @param htim : TIM handle
  5612. * @retval None
  5613. */
  5614. __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
  5615. {
  5616. 8006c6e: 4770 bx lr
  5617. 08006c70 <UART_EndRxTransfer>:
  5618. * @retval None
  5619. */
  5620. static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
  5621. {
  5622. /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
  5623. CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
  5624. 8006c70: 6803 ldr r3, [r0, #0]
  5625. 8006c72: 68da ldr r2, [r3, #12]
  5626. 8006c74: f422 7290 bic.w r2, r2, #288 ; 0x120
  5627. 8006c78: 60da str r2, [r3, #12]
  5628. CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
  5629. 8006c7a: 695a ldr r2, [r3, #20]
  5630. 8006c7c: f022 0201 bic.w r2, r2, #1
  5631. 8006c80: 615a str r2, [r3, #20]
  5632. /* At end of Rx process, restore huart->RxState to Ready */
  5633. huart->RxState = HAL_UART_STATE_READY;
  5634. 8006c82: 2320 movs r3, #32
  5635. 8006c84: f880 303a strb.w r3, [r0, #58] ; 0x3a
  5636. 8006c88: 4770 bx lr
  5637. ...
  5638. 08006c8c <UART_SetConfig>:
  5639. * @param huart: pointer to a UART_HandleTypeDef structure that contains
  5640. * the configuration information for the specified UART module.
  5641. * @retval None
  5642. */
  5643. static void UART_SetConfig(UART_HandleTypeDef *huart)
  5644. {
  5645. 8006c8c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
  5646. assert_param(IS_UART_MODE(huart->Init.Mode));
  5647. /*------- UART-associated USART registers setting : CR2 Configuration ------*/
  5648. /* Configure the UART Stop Bits: Set STOP[13:12] bits according
  5649. * to huart->Init.StopBits value */
  5650. MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
  5651. 8006c90: 6805 ldr r5, [r0, #0]
  5652. 8006c92: 68c2 ldr r2, [r0, #12]
  5653. 8006c94: 692b ldr r3, [r5, #16]
  5654. tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
  5655. MODIFY_REG(huart->Instance->CR1,
  5656. (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
  5657. tmpreg);
  5658. #else
  5659. tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
  5660. 8006c96: 6901 ldr r1, [r0, #16]
  5661. MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
  5662. 8006c98: f423 5340 bic.w r3, r3, #12288 ; 0x3000
  5663. 8006c9c: 4313 orrs r3, r2
  5664. 8006c9e: 612b str r3, [r5, #16]
  5665. tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
  5666. 8006ca0: 6883 ldr r3, [r0, #8]
  5667. MODIFY_REG(huart->Instance->CR1,
  5668. 8006ca2: 68ea ldr r2, [r5, #12]
  5669. tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
  5670. 8006ca4: 430b orrs r3, r1
  5671. 8006ca6: 6941 ldr r1, [r0, #20]
  5672. MODIFY_REG(huart->Instance->CR1,
  5673. 8006ca8: f422 52b0 bic.w r2, r2, #5632 ; 0x1600
  5674. 8006cac: f022 020c bic.w r2, r2, #12
  5675. tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
  5676. 8006cb0: 430b orrs r3, r1
  5677. MODIFY_REG(huart->Instance->CR1,
  5678. 8006cb2: 4313 orrs r3, r2
  5679. 8006cb4: 60eb str r3, [r5, #12]
  5680. tmpreg);
  5681. #endif /* USART_CR1_OVER8 */
  5682. /*------- UART-associated USART registers setting : CR3 Configuration ------*/
  5683. /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
  5684. MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
  5685. 8006cb6: 696b ldr r3, [r5, #20]
  5686. 8006cb8: 6982 ldr r2, [r0, #24]
  5687. 8006cba: f423 7340 bic.w r3, r3, #768 ; 0x300
  5688. 8006cbe: 4313 orrs r3, r2
  5689. 8006cc0: 616b str r3, [r5, #20]
  5690. huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
  5691. }
  5692. }
  5693. #else
  5694. /*-------------------------- USART BRR Configuration ---------------------*/
  5695. if(huart->Instance == USART1)
  5696. 8006cc2: 4b40 ldr r3, [pc, #256] ; (8006dc4 <UART_SetConfig+0x138>)
  5697. {
  5698. 8006cc4: 4681 mov r9, r0
  5699. if(huart->Instance == USART1)
  5700. 8006cc6: 429d cmp r5, r3
  5701. 8006cc8: f04f 0419 mov.w r4, #25
  5702. 8006ccc: d146 bne.n 8006d5c <UART_SetConfig+0xd0>
  5703. {
  5704. huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
  5705. 8006cce: f7ff fd95 bl 80067fc <HAL_RCC_GetPCLK2Freq>
  5706. 8006cd2: fb04 f300 mul.w r3, r4, r0
  5707. 8006cd6: f8d9 6004 ldr.w r6, [r9, #4]
  5708. 8006cda: f04f 0864 mov.w r8, #100 ; 0x64
  5709. 8006cde: 00b6 lsls r6, r6, #2
  5710. 8006ce0: fbb3 f3f6 udiv r3, r3, r6
  5711. 8006ce4: fbb3 f3f8 udiv r3, r3, r8
  5712. 8006ce8: 011e lsls r6, r3, #4
  5713. 8006cea: f7ff fd87 bl 80067fc <HAL_RCC_GetPCLK2Freq>
  5714. 8006cee: 4360 muls r0, r4
  5715. 8006cf0: f8d9 3004 ldr.w r3, [r9, #4]
  5716. 8006cf4: 009b lsls r3, r3, #2
  5717. 8006cf6: fbb0 f7f3 udiv r7, r0, r3
  5718. 8006cfa: f7ff fd7f bl 80067fc <HAL_RCC_GetPCLK2Freq>
  5719. 8006cfe: 4360 muls r0, r4
  5720. 8006d00: f8d9 3004 ldr.w r3, [r9, #4]
  5721. 8006d04: 009b lsls r3, r3, #2
  5722. 8006d06: fbb0 f3f3 udiv r3, r0, r3
  5723. 8006d0a: fbb3 f3f8 udiv r3, r3, r8
  5724. 8006d0e: fb08 7313 mls r3, r8, r3, r7
  5725. 8006d12: 011b lsls r3, r3, #4
  5726. 8006d14: 3332 adds r3, #50 ; 0x32
  5727. 8006d16: fbb3 f3f8 udiv r3, r3, r8
  5728. 8006d1a: f003 07f0 and.w r7, r3, #240 ; 0xf0
  5729. 8006d1e: f7ff fd6d bl 80067fc <HAL_RCC_GetPCLK2Freq>
  5730. 8006d22: 4360 muls r0, r4
  5731. 8006d24: f8d9 2004 ldr.w r2, [r9, #4]
  5732. 8006d28: 0092 lsls r2, r2, #2
  5733. 8006d2a: fbb0 faf2 udiv sl, r0, r2
  5734. 8006d2e: f7ff fd65 bl 80067fc <HAL_RCC_GetPCLK2Freq>
  5735. }
  5736. else
  5737. {
  5738. huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
  5739. 8006d32: 4360 muls r0, r4
  5740. 8006d34: f8d9 3004 ldr.w r3, [r9, #4]
  5741. 8006d38: 009b lsls r3, r3, #2
  5742. 8006d3a: fbb0 f3f3 udiv r3, r0, r3
  5743. 8006d3e: fbb3 f3f8 udiv r3, r3, r8
  5744. 8006d42: fb08 a313 mls r3, r8, r3, sl
  5745. 8006d46: 011b lsls r3, r3, #4
  5746. 8006d48: 3332 adds r3, #50 ; 0x32
  5747. 8006d4a: fbb3 f3f8 udiv r3, r3, r8
  5748. 8006d4e: f003 030f and.w r3, r3, #15
  5749. 8006d52: 433b orrs r3, r7
  5750. 8006d54: 4433 add r3, r6
  5751. 8006d56: 60ab str r3, [r5, #8]
  5752. 8006d58: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
  5753. 8006d5c: f7ff fd3e bl 80067dc <HAL_RCC_GetPCLK1Freq>
  5754. 8006d60: fb04 f300 mul.w r3, r4, r0
  5755. 8006d64: f8d9 6004 ldr.w r6, [r9, #4]
  5756. 8006d68: f04f 0864 mov.w r8, #100 ; 0x64
  5757. 8006d6c: 00b6 lsls r6, r6, #2
  5758. 8006d6e: fbb3 f3f6 udiv r3, r3, r6
  5759. 8006d72: fbb3 f3f8 udiv r3, r3, r8
  5760. 8006d76: 011e lsls r6, r3, #4
  5761. 8006d78: f7ff fd30 bl 80067dc <HAL_RCC_GetPCLK1Freq>
  5762. 8006d7c: 4360 muls r0, r4
  5763. 8006d7e: f8d9 3004 ldr.w r3, [r9, #4]
  5764. 8006d82: 009b lsls r3, r3, #2
  5765. 8006d84: fbb0 f7f3 udiv r7, r0, r3
  5766. 8006d88: f7ff fd28 bl 80067dc <HAL_RCC_GetPCLK1Freq>
  5767. 8006d8c: 4360 muls r0, r4
  5768. 8006d8e: f8d9 3004 ldr.w r3, [r9, #4]
  5769. 8006d92: 009b lsls r3, r3, #2
  5770. 8006d94: fbb0 f3f3 udiv r3, r0, r3
  5771. 8006d98: fbb3 f3f8 udiv r3, r3, r8
  5772. 8006d9c: fb08 7313 mls r3, r8, r3, r7
  5773. 8006da0: 011b lsls r3, r3, #4
  5774. 8006da2: 3332 adds r3, #50 ; 0x32
  5775. 8006da4: fbb3 f3f8 udiv r3, r3, r8
  5776. 8006da8: f003 07f0 and.w r7, r3, #240 ; 0xf0
  5777. 8006dac: f7ff fd16 bl 80067dc <HAL_RCC_GetPCLK1Freq>
  5778. 8006db0: 4360 muls r0, r4
  5779. 8006db2: f8d9 2004 ldr.w r2, [r9, #4]
  5780. 8006db6: 0092 lsls r2, r2, #2
  5781. 8006db8: fbb0 faf2 udiv sl, r0, r2
  5782. 8006dbc: f7ff fd0e bl 80067dc <HAL_RCC_GetPCLK1Freq>
  5783. 8006dc0: e7b7 b.n 8006d32 <UART_SetConfig+0xa6>
  5784. 8006dc2: bf00 nop
  5785. 8006dc4: 40013800 .word 0x40013800
  5786. 08006dc8 <UART_WaitOnFlagUntilTimeout.constprop.3>:
  5787. static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
  5788. 8006dc8: b5f8 push {r3, r4, r5, r6, r7, lr}
  5789. 8006dca: 4604 mov r4, r0
  5790. 8006dcc: 460e mov r6, r1
  5791. 8006dce: 4617 mov r7, r2
  5792. 8006dd0: 461d mov r5, r3
  5793. while((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
  5794. 8006dd2: 6821 ldr r1, [r4, #0]
  5795. 8006dd4: 680b ldr r3, [r1, #0]
  5796. 8006dd6: ea36 0303 bics.w r3, r6, r3
  5797. 8006dda: d101 bne.n 8006de0 <UART_WaitOnFlagUntilTimeout.constprop.3+0x18>
  5798. return HAL_OK;
  5799. 8006ddc: 2000 movs r0, #0
  5800. }
  5801. 8006dde: bdf8 pop {r3, r4, r5, r6, r7, pc}
  5802. if(Timeout != HAL_MAX_DELAY)
  5803. 8006de0: 1c6b adds r3, r5, #1
  5804. 8006de2: d0f7 beq.n 8006dd4 <UART_WaitOnFlagUntilTimeout.constprop.3+0xc>
  5805. if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
  5806. 8006de4: b995 cbnz r5, 8006e0c <UART_WaitOnFlagUntilTimeout.constprop.3+0x44>
  5807. CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
  5808. 8006de6: 6823 ldr r3, [r4, #0]
  5809. __HAL_UNLOCK(huart);
  5810. 8006de8: 2003 movs r0, #3
  5811. CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
  5812. 8006dea: 68da ldr r2, [r3, #12]
  5813. 8006dec: f422 72d0 bic.w r2, r2, #416 ; 0x1a0
  5814. 8006df0: 60da str r2, [r3, #12]
  5815. CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
  5816. 8006df2: 695a ldr r2, [r3, #20]
  5817. 8006df4: f022 0201 bic.w r2, r2, #1
  5818. 8006df8: 615a str r2, [r3, #20]
  5819. huart->gState = HAL_UART_STATE_READY;
  5820. 8006dfa: 2320 movs r3, #32
  5821. 8006dfc: f884 3039 strb.w r3, [r4, #57] ; 0x39
  5822. huart->RxState = HAL_UART_STATE_READY;
  5823. 8006e00: f884 303a strb.w r3, [r4, #58] ; 0x3a
  5824. __HAL_UNLOCK(huart);
  5825. 8006e04: 2300 movs r3, #0
  5826. 8006e06: f884 3038 strb.w r3, [r4, #56] ; 0x38
  5827. 8006e0a: bdf8 pop {r3, r4, r5, r6, r7, pc}
  5828. if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
  5829. 8006e0c: f7fe fb68 bl 80054e0 <HAL_GetTick>
  5830. 8006e10: 1bc0 subs r0, r0, r7
  5831. 8006e12: 4285 cmp r5, r0
  5832. 8006e14: d2dd bcs.n 8006dd2 <UART_WaitOnFlagUntilTimeout.constprop.3+0xa>
  5833. 8006e16: e7e6 b.n 8006de6 <UART_WaitOnFlagUntilTimeout.constprop.3+0x1e>
  5834. 08006e18 <HAL_UART_Init>:
  5835. {
  5836. 8006e18: b510 push {r4, lr}
  5837. if(huart == NULL)
  5838. 8006e1a: 4604 mov r4, r0
  5839. 8006e1c: b340 cbz r0, 8006e70 <HAL_UART_Init+0x58>
  5840. if(huart->gState == HAL_UART_STATE_RESET)
  5841. 8006e1e: f890 3039 ldrb.w r3, [r0, #57] ; 0x39
  5842. 8006e22: f003 02ff and.w r2, r3, #255 ; 0xff
  5843. 8006e26: b91b cbnz r3, 8006e30 <HAL_UART_Init+0x18>
  5844. huart->Lock = HAL_UNLOCKED;
  5845. 8006e28: f880 2038 strb.w r2, [r0, #56] ; 0x38
  5846. HAL_UART_MspInit(huart);
  5847. 8006e2c: f001 fc26 bl 800867c <HAL_UART_MspInit>
  5848. huart->gState = HAL_UART_STATE_BUSY;
  5849. 8006e30: 2324 movs r3, #36 ; 0x24
  5850. __HAL_UART_DISABLE(huart);
  5851. 8006e32: 6822 ldr r2, [r4, #0]
  5852. huart->gState = HAL_UART_STATE_BUSY;
  5853. 8006e34: f884 3039 strb.w r3, [r4, #57] ; 0x39
  5854. __HAL_UART_DISABLE(huart);
  5855. 8006e38: 68d3 ldr r3, [r2, #12]
  5856. UART_SetConfig(huart);
  5857. 8006e3a: 4620 mov r0, r4
  5858. __HAL_UART_DISABLE(huart);
  5859. 8006e3c: f423 5300 bic.w r3, r3, #8192 ; 0x2000
  5860. 8006e40: 60d3 str r3, [r2, #12]
  5861. UART_SetConfig(huart);
  5862. 8006e42: f7ff ff23 bl 8006c8c <UART_SetConfig>
  5863. CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
  5864. 8006e46: 6823 ldr r3, [r4, #0]
  5865. huart->ErrorCode = HAL_UART_ERROR_NONE;
  5866. 8006e48: 2000 movs r0, #0
  5867. CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
  5868. 8006e4a: 691a ldr r2, [r3, #16]
  5869. 8006e4c: f422 4290 bic.w r2, r2, #18432 ; 0x4800
  5870. 8006e50: 611a str r2, [r3, #16]
  5871. CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
  5872. 8006e52: 695a ldr r2, [r3, #20]
  5873. 8006e54: f022 022a bic.w r2, r2, #42 ; 0x2a
  5874. 8006e58: 615a str r2, [r3, #20]
  5875. __HAL_UART_ENABLE(huart);
  5876. 8006e5a: 68da ldr r2, [r3, #12]
  5877. 8006e5c: f442 5200 orr.w r2, r2, #8192 ; 0x2000
  5878. 8006e60: 60da str r2, [r3, #12]
  5879. huart->gState= HAL_UART_STATE_READY;
  5880. 8006e62: 2320 movs r3, #32
  5881. huart->ErrorCode = HAL_UART_ERROR_NONE;
  5882. 8006e64: 63e0 str r0, [r4, #60] ; 0x3c
  5883. huart->gState= HAL_UART_STATE_READY;
  5884. 8006e66: f884 3039 strb.w r3, [r4, #57] ; 0x39
  5885. huart->RxState= HAL_UART_STATE_READY;
  5886. 8006e6a: f884 303a strb.w r3, [r4, #58] ; 0x3a
  5887. return HAL_OK;
  5888. 8006e6e: bd10 pop {r4, pc}
  5889. return HAL_ERROR;
  5890. 8006e70: 2001 movs r0, #1
  5891. }
  5892. 8006e72: bd10 pop {r4, pc}
  5893. 08006e74 <HAL_UART_Transmit>:
  5894. {
  5895. 8006e74: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
  5896. 8006e78: 461f mov r7, r3
  5897. if(huart->gState == HAL_UART_STATE_READY)
  5898. 8006e7a: f890 3039 ldrb.w r3, [r0, #57] ; 0x39
  5899. {
  5900. 8006e7e: 4604 mov r4, r0
  5901. if(huart->gState == HAL_UART_STATE_READY)
  5902. 8006e80: 2b20 cmp r3, #32
  5903. {
  5904. 8006e82: 460d mov r5, r1
  5905. 8006e84: 4690 mov r8, r2
  5906. if(huart->gState == HAL_UART_STATE_READY)
  5907. 8006e86: d14e bne.n 8006f26 <HAL_UART_Transmit+0xb2>
  5908. if((pData == NULL) || (Size == 0U))
  5909. 8006e88: 2900 cmp r1, #0
  5910. 8006e8a: d049 beq.n 8006f20 <HAL_UART_Transmit+0xac>
  5911. 8006e8c: 2a00 cmp r2, #0
  5912. 8006e8e: d047 beq.n 8006f20 <HAL_UART_Transmit+0xac>
  5913. __HAL_LOCK(huart);
  5914. 8006e90: f890 3038 ldrb.w r3, [r0, #56] ; 0x38
  5915. 8006e94: 2b01 cmp r3, #1
  5916. 8006e96: d046 beq.n 8006f26 <HAL_UART_Transmit+0xb2>
  5917. 8006e98: 2301 movs r3, #1
  5918. 8006e9a: f880 3038 strb.w r3, [r0, #56] ; 0x38
  5919. huart->ErrorCode = HAL_UART_ERROR_NONE;
  5920. 8006e9e: 2300 movs r3, #0
  5921. 8006ea0: 63c3 str r3, [r0, #60] ; 0x3c
  5922. huart->gState = HAL_UART_STATE_BUSY_TX;
  5923. 8006ea2: 2321 movs r3, #33 ; 0x21
  5924. 8006ea4: f880 3039 strb.w r3, [r0, #57] ; 0x39
  5925. tickstart = HAL_GetTick();
  5926. 8006ea8: f7fe fb1a bl 80054e0 <HAL_GetTick>
  5927. 8006eac: 4606 mov r6, r0
  5928. huart->TxXferSize = Size;
  5929. 8006eae: f8a4 8024 strh.w r8, [r4, #36] ; 0x24
  5930. huart->TxXferCount = Size;
  5931. 8006eb2: f8a4 8026 strh.w r8, [r4, #38] ; 0x26
  5932. while(huart->TxXferCount > 0U)
  5933. 8006eb6: 8ce3 ldrh r3, [r4, #38] ; 0x26
  5934. 8006eb8: b29b uxth r3, r3
  5935. 8006eba: b96b cbnz r3, 8006ed8 <HAL_UART_Transmit+0x64>
  5936. if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
  5937. 8006ebc: 463b mov r3, r7
  5938. 8006ebe: 4632 mov r2, r6
  5939. 8006ec0: 2140 movs r1, #64 ; 0x40
  5940. 8006ec2: 4620 mov r0, r4
  5941. 8006ec4: f7ff ff80 bl 8006dc8 <UART_WaitOnFlagUntilTimeout.constprop.3>
  5942. 8006ec8: b9a8 cbnz r0, 8006ef6 <HAL_UART_Transmit+0x82>
  5943. huart->gState = HAL_UART_STATE_READY;
  5944. 8006eca: 2320 movs r3, #32
  5945. __HAL_UNLOCK(huart);
  5946. 8006ecc: f884 0038 strb.w r0, [r4, #56] ; 0x38
  5947. huart->gState = HAL_UART_STATE_READY;
  5948. 8006ed0: f884 3039 strb.w r3, [r4, #57] ; 0x39
  5949. return HAL_OK;
  5950. 8006ed4: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
  5951. huart->TxXferCount--;
  5952. 8006ed8: 8ce3 ldrh r3, [r4, #38] ; 0x26
  5953. if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
  5954. 8006eda: 4632 mov r2, r6
  5955. huart->TxXferCount--;
  5956. 8006edc: 3b01 subs r3, #1
  5957. 8006ede: b29b uxth r3, r3
  5958. 8006ee0: 84e3 strh r3, [r4, #38] ; 0x26
  5959. if(huart->Init.WordLength == UART_WORDLENGTH_9B)
  5960. 8006ee2: 68a3 ldr r3, [r4, #8]
  5961. if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
  5962. 8006ee4: 2180 movs r1, #128 ; 0x80
  5963. if(huart->Init.WordLength == UART_WORDLENGTH_9B)
  5964. 8006ee6: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
  5965. if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
  5966. 8006eea: 4620 mov r0, r4
  5967. 8006eec: 463b mov r3, r7
  5968. if(huart->Init.WordLength == UART_WORDLENGTH_9B)
  5969. 8006eee: d10e bne.n 8006f0e <HAL_UART_Transmit+0x9a>
  5970. if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
  5971. 8006ef0: f7ff ff6a bl 8006dc8 <UART_WaitOnFlagUntilTimeout.constprop.3>
  5972. 8006ef4: b110 cbz r0, 8006efc <HAL_UART_Transmit+0x88>
  5973. return HAL_TIMEOUT;
  5974. 8006ef6: 2003 movs r0, #3
  5975. 8006ef8: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
  5976. huart->Instance->DR = (*tmp & (uint16_t)0x01FF);
  5977. 8006efc: 882b ldrh r3, [r5, #0]
  5978. 8006efe: 6822 ldr r2, [r4, #0]
  5979. 8006f00: f3c3 0308 ubfx r3, r3, #0, #9
  5980. 8006f04: 6053 str r3, [r2, #4]
  5981. if(huart->Init.Parity == UART_PARITY_NONE)
  5982. 8006f06: 6923 ldr r3, [r4, #16]
  5983. 8006f08: b943 cbnz r3, 8006f1c <HAL_UART_Transmit+0xa8>
  5984. pData +=2U;
  5985. 8006f0a: 3502 adds r5, #2
  5986. 8006f0c: e7d3 b.n 8006eb6 <HAL_UART_Transmit+0x42>
  5987. if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
  5988. 8006f0e: f7ff ff5b bl 8006dc8 <UART_WaitOnFlagUntilTimeout.constprop.3>
  5989. 8006f12: 2800 cmp r0, #0
  5990. 8006f14: d1ef bne.n 8006ef6 <HAL_UART_Transmit+0x82>
  5991. huart->Instance->DR = (*pData++ & (uint8_t)0xFF);
  5992. 8006f16: 6823 ldr r3, [r4, #0]
  5993. 8006f18: 782a ldrb r2, [r5, #0]
  5994. 8006f1a: 605a str r2, [r3, #4]
  5995. 8006f1c: 3501 adds r5, #1
  5996. 8006f1e: e7ca b.n 8006eb6 <HAL_UART_Transmit+0x42>
  5997. return HAL_ERROR;
  5998. 8006f20: 2001 movs r0, #1
  5999. 8006f22: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
  6000. return HAL_BUSY;
  6001. 8006f26: 2002 movs r0, #2
  6002. }
  6003. 8006f28: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
  6004. 08006f2c <HAL_UART_Transmit_DMA>:
  6005. {
  6006. 8006f2c: b538 push {r3, r4, r5, lr}
  6007. 8006f2e: 4604 mov r4, r0
  6008. 8006f30: 4613 mov r3, r2
  6009. if(huart->gState == HAL_UART_STATE_READY)
  6010. 8006f32: f894 2039 ldrb.w r2, [r4, #57] ; 0x39
  6011. 8006f36: 2a20 cmp r2, #32
  6012. 8006f38: d12a bne.n 8006f90 <HAL_UART_Transmit_DMA+0x64>
  6013. if((pData == NULL) || (Size == 0U))
  6014. 8006f3a: b339 cbz r1, 8006f8c <HAL_UART_Transmit_DMA+0x60>
  6015. 8006f3c: b333 cbz r3, 8006f8c <HAL_UART_Transmit_DMA+0x60>
  6016. __HAL_LOCK(huart);
  6017. 8006f3e: f894 2038 ldrb.w r2, [r4, #56] ; 0x38
  6018. 8006f42: 2a01 cmp r2, #1
  6019. 8006f44: d024 beq.n 8006f90 <HAL_UART_Transmit_DMA+0x64>
  6020. 8006f46: 2201 movs r2, #1
  6021. huart->ErrorCode = HAL_UART_ERROR_NONE;
  6022. 8006f48: 2500 movs r5, #0
  6023. __HAL_LOCK(huart);
  6024. 8006f4a: f884 2038 strb.w r2, [r4, #56] ; 0x38
  6025. huart->gState = HAL_UART_STATE_BUSY_TX;
  6026. 8006f4e: 2221 movs r2, #33 ; 0x21
  6027. huart->TxXferCount = Size;
  6028. 8006f50: 84e3 strh r3, [r4, #38] ; 0x26
  6029. huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
  6030. 8006f52: 6b20 ldr r0, [r4, #48] ; 0x30
  6031. huart->ErrorCode = HAL_UART_ERROR_NONE;
  6032. 8006f54: 63e5 str r5, [r4, #60] ; 0x3c
  6033. huart->gState = HAL_UART_STATE_BUSY_TX;
  6034. 8006f56: f884 2039 strb.w r2, [r4, #57] ; 0x39
  6035. huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
  6036. 8006f5a: 4a0e ldr r2, [pc, #56] ; (8006f94 <HAL_UART_Transmit_DMA+0x68>)
  6037. huart->TxXferSize = Size;
  6038. 8006f5c: 84a3 strh r3, [r4, #36] ; 0x24
  6039. huart->pTxBuffPtr = pData;
  6040. 8006f5e: 6221 str r1, [r4, #32]
  6041. huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
  6042. 8006f60: 6282 str r2, [r0, #40] ; 0x28
  6043. huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
  6044. 8006f62: 4a0d ldr r2, [pc, #52] ; (8006f98 <HAL_UART_Transmit_DMA+0x6c>)
  6045. huart->hdmatx->XferAbortCallback = NULL;
  6046. 8006f64: 6345 str r5, [r0, #52] ; 0x34
  6047. huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
  6048. 8006f66: 62c2 str r2, [r0, #44] ; 0x2c
  6049. huart->hdmatx->XferErrorCallback = UART_DMAError;
  6050. 8006f68: 4a0c ldr r2, [pc, #48] ; (8006f9c <HAL_UART_Transmit_DMA+0x70>)
  6051. 8006f6a: 6302 str r2, [r0, #48] ; 0x30
  6052. HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t*)tmp, (uint32_t)&huart->Instance->DR, Size);
  6053. 8006f6c: 6822 ldr r2, [r4, #0]
  6054. 8006f6e: 3204 adds r2, #4
  6055. 8006f70: f7fe fe10 bl 8005b94 <HAL_DMA_Start_IT>
  6056. __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
  6057. 8006f74: f06f 0240 mvn.w r2, #64 ; 0x40
  6058. 8006f78: 6823 ldr r3, [r4, #0]
  6059. return HAL_OK;
  6060. 8006f7a: 4628 mov r0, r5
  6061. __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
  6062. 8006f7c: 601a str r2, [r3, #0]
  6063. SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
  6064. 8006f7e: 695a ldr r2, [r3, #20]
  6065. __HAL_UNLOCK(huart);
  6066. 8006f80: f884 5038 strb.w r5, [r4, #56] ; 0x38
  6067. SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
  6068. 8006f84: f042 0280 orr.w r2, r2, #128 ; 0x80
  6069. 8006f88: 615a str r2, [r3, #20]
  6070. return HAL_OK;
  6071. 8006f8a: bd38 pop {r3, r4, r5, pc}
  6072. return HAL_ERROR;
  6073. 8006f8c: 2001 movs r0, #1
  6074. 8006f8e: bd38 pop {r3, r4, r5, pc}
  6075. return HAL_BUSY;
  6076. 8006f90: 2002 movs r0, #2
  6077. }
  6078. 8006f92: bd38 pop {r3, r4, r5, pc}
  6079. 8006f94: 08007033 .word 0x08007033
  6080. 8006f98: 08007061 .word 0x08007061
  6081. 8006f9c: 0800712d .word 0x0800712d
  6082. 08006fa0 <HAL_UART_Receive_DMA>:
  6083. {
  6084. 8006fa0: 4613 mov r3, r2
  6085. if(huart->RxState == HAL_UART_STATE_READY)
  6086. 8006fa2: f890 203a ldrb.w r2, [r0, #58] ; 0x3a
  6087. {
  6088. 8006fa6: b573 push {r0, r1, r4, r5, r6, lr}
  6089. if(huart->RxState == HAL_UART_STATE_READY)
  6090. 8006fa8: 2a20 cmp r2, #32
  6091. {
  6092. 8006faa: 4605 mov r5, r0
  6093. if(huart->RxState == HAL_UART_STATE_READY)
  6094. 8006fac: d138 bne.n 8007020 <HAL_UART_Receive_DMA+0x80>
  6095. if((pData == NULL) || (Size == 0U))
  6096. 8006fae: 2900 cmp r1, #0
  6097. 8006fb0: d034 beq.n 800701c <HAL_UART_Receive_DMA+0x7c>
  6098. 8006fb2: 2b00 cmp r3, #0
  6099. 8006fb4: d032 beq.n 800701c <HAL_UART_Receive_DMA+0x7c>
  6100. __HAL_LOCK(huart);
  6101. 8006fb6: f890 2038 ldrb.w r2, [r0, #56] ; 0x38
  6102. 8006fba: 2a01 cmp r2, #1
  6103. 8006fbc: d030 beq.n 8007020 <HAL_UART_Receive_DMA+0x80>
  6104. 8006fbe: 2201 movs r2, #1
  6105. huart->ErrorCode = HAL_UART_ERROR_NONE;
  6106. 8006fc0: 2400 movs r4, #0
  6107. __HAL_LOCK(huart);
  6108. 8006fc2: f880 2038 strb.w r2, [r0, #56] ; 0x38
  6109. huart->RxState = HAL_UART_STATE_BUSY_RX;
  6110. 8006fc6: 2222 movs r2, #34 ; 0x22
  6111. huart->pRxBuffPtr = pData;
  6112. 8006fc8: 6281 str r1, [r0, #40] ; 0x28
  6113. huart->RxXferSize = Size;
  6114. 8006fca: 8583 strh r3, [r0, #44] ; 0x2c
  6115. huart->ErrorCode = HAL_UART_ERROR_NONE;
  6116. 8006fcc: 63c4 str r4, [r0, #60] ; 0x3c
  6117. huart->RxState = HAL_UART_STATE_BUSY_RX;
  6118. 8006fce: f880 203a strb.w r2, [r0, #58] ; 0x3a
  6119. huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
  6120. 8006fd2: 6b40 ldr r0, [r0, #52] ; 0x34
  6121. 8006fd4: 4a13 ldr r2, [pc, #76] ; (8007024 <HAL_UART_Receive_DMA+0x84>)
  6122. HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t*)tmp, Size);
  6123. 8006fd6: 682e ldr r6, [r5, #0]
  6124. huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
  6125. 8006fd8: 6282 str r2, [r0, #40] ; 0x28
  6126. huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
  6127. 8006fda: 4a13 ldr r2, [pc, #76] ; (8007028 <HAL_UART_Receive_DMA+0x88>)
  6128. huart->hdmarx->XferAbortCallback = NULL;
  6129. 8006fdc: 6344 str r4, [r0, #52] ; 0x34
  6130. huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
  6131. 8006fde: 62c2 str r2, [r0, #44] ; 0x2c
  6132. huart->hdmarx->XferErrorCallback = UART_DMAError;
  6133. 8006fe0: 4a12 ldr r2, [pc, #72] ; (800702c <HAL_UART_Receive_DMA+0x8c>)
  6134. 8006fe2: 6302 str r2, [r0, #48] ; 0x30
  6135. HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t*)tmp, Size);
  6136. 8006fe4: 460a mov r2, r1
  6137. 8006fe6: 1d31 adds r1, r6, #4
  6138. 8006fe8: f7fe fdd4 bl 8005b94 <HAL_DMA_Start_IT>
  6139. return HAL_OK;
  6140. 8006fec: 4620 mov r0, r4
  6141. __HAL_UART_CLEAR_OREFLAG(huart);
  6142. 8006fee: 682b ldr r3, [r5, #0]
  6143. 8006ff0: 9401 str r4, [sp, #4]
  6144. 8006ff2: 681a ldr r2, [r3, #0]
  6145. 8006ff4: 9201 str r2, [sp, #4]
  6146. 8006ff6: 685a ldr r2, [r3, #4]
  6147. __HAL_UNLOCK(huart);
  6148. 8006ff8: f885 4038 strb.w r4, [r5, #56] ; 0x38
  6149. __HAL_UART_CLEAR_OREFLAG(huart);
  6150. 8006ffc: 9201 str r2, [sp, #4]
  6151. 8006ffe: 9a01 ldr r2, [sp, #4]
  6152. SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
  6153. 8007000: 68da ldr r2, [r3, #12]
  6154. 8007002: f442 7280 orr.w r2, r2, #256 ; 0x100
  6155. 8007006: 60da str r2, [r3, #12]
  6156. SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
  6157. 8007008: 695a ldr r2, [r3, #20]
  6158. 800700a: f042 0201 orr.w r2, r2, #1
  6159. 800700e: 615a str r2, [r3, #20]
  6160. SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
  6161. 8007010: 695a ldr r2, [r3, #20]
  6162. 8007012: f042 0240 orr.w r2, r2, #64 ; 0x40
  6163. 8007016: 615a str r2, [r3, #20]
  6164. }
  6165. 8007018: b002 add sp, #8
  6166. 800701a: bd70 pop {r4, r5, r6, pc}
  6167. return HAL_ERROR;
  6168. 800701c: 2001 movs r0, #1
  6169. 800701e: e7fb b.n 8007018 <HAL_UART_Receive_DMA+0x78>
  6170. return HAL_BUSY;
  6171. 8007020: 2002 movs r0, #2
  6172. 8007022: e7f9 b.n 8007018 <HAL_UART_Receive_DMA+0x78>
  6173. 8007024: 0800706b .word 0x0800706b
  6174. 8007028: 08007121 .word 0x08007121
  6175. 800702c: 0800712d .word 0x0800712d
  6176. 08007030 <HAL_UART_TxCpltCallback>:
  6177. 8007030: 4770 bx lr
  6178. 08007032 <UART_DMATransmitCplt>:
  6179. {
  6180. 8007032: b508 push {r3, lr}
  6181. if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
  6182. 8007034: 6803 ldr r3, [r0, #0]
  6183. UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
  6184. 8007036: 6a42 ldr r2, [r0, #36] ; 0x24
  6185. if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
  6186. 8007038: 681b ldr r3, [r3, #0]
  6187. 800703a: f013 0320 ands.w r3, r3, #32
  6188. 800703e: d10a bne.n 8007056 <UART_DMATransmitCplt+0x24>
  6189. huart->TxXferCount = 0U;
  6190. 8007040: 84d3 strh r3, [r2, #38] ; 0x26
  6191. CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
  6192. 8007042: 6813 ldr r3, [r2, #0]
  6193. 8007044: 695a ldr r2, [r3, #20]
  6194. 8007046: f022 0280 bic.w r2, r2, #128 ; 0x80
  6195. 800704a: 615a str r2, [r3, #20]
  6196. SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
  6197. 800704c: 68da ldr r2, [r3, #12]
  6198. 800704e: f042 0240 orr.w r2, r2, #64 ; 0x40
  6199. 8007052: 60da str r2, [r3, #12]
  6200. 8007054: bd08 pop {r3, pc}
  6201. HAL_UART_TxCpltCallback(huart);
  6202. 8007056: 4610 mov r0, r2
  6203. 8007058: f7ff ffea bl 8007030 <HAL_UART_TxCpltCallback>
  6204. 800705c: bd08 pop {r3, pc}
  6205. 0800705e <HAL_UART_TxHalfCpltCallback>:
  6206. 800705e: 4770 bx lr
  6207. 08007060 <UART_DMATxHalfCplt>:
  6208. {
  6209. 8007060: b508 push {r3, lr}
  6210. HAL_UART_TxHalfCpltCallback(huart);
  6211. 8007062: 6a40 ldr r0, [r0, #36] ; 0x24
  6212. 8007064: f7ff fffb bl 800705e <HAL_UART_TxHalfCpltCallback>
  6213. 8007068: bd08 pop {r3, pc}
  6214. 0800706a <UART_DMAReceiveCplt>:
  6215. {
  6216. 800706a: b508 push {r3, lr}
  6217. if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
  6218. 800706c: 6803 ldr r3, [r0, #0]
  6219. UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
  6220. 800706e: 6a42 ldr r2, [r0, #36] ; 0x24
  6221. if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
  6222. 8007070: 681b ldr r3, [r3, #0]
  6223. 8007072: f013 0320 ands.w r3, r3, #32
  6224. 8007076: d110 bne.n 800709a <UART_DMAReceiveCplt+0x30>
  6225. huart->RxXferCount = 0U;
  6226. 8007078: 85d3 strh r3, [r2, #46] ; 0x2e
  6227. CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
  6228. 800707a: 6813 ldr r3, [r2, #0]
  6229. 800707c: 68d9 ldr r1, [r3, #12]
  6230. 800707e: f421 7180 bic.w r1, r1, #256 ; 0x100
  6231. 8007082: 60d9 str r1, [r3, #12]
  6232. CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
  6233. 8007084: 6959 ldr r1, [r3, #20]
  6234. 8007086: f021 0101 bic.w r1, r1, #1
  6235. 800708a: 6159 str r1, [r3, #20]
  6236. CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
  6237. 800708c: 6959 ldr r1, [r3, #20]
  6238. 800708e: f021 0140 bic.w r1, r1, #64 ; 0x40
  6239. 8007092: 6159 str r1, [r3, #20]
  6240. huart->RxState = HAL_UART_STATE_READY;
  6241. 8007094: 2320 movs r3, #32
  6242. 8007096: f882 303a strb.w r3, [r2, #58] ; 0x3a
  6243. HAL_UART_RxCpltCallback(huart);
  6244. 800709a: 4610 mov r0, r2
  6245. 800709c: f001 fc2c bl 80088f8 <HAL_UART_RxCpltCallback>
  6246. 80070a0: bd08 pop {r3, pc}
  6247. 080070a2 <UART_Receive_IT>:
  6248. if(huart->RxState == HAL_UART_STATE_BUSY_RX)
  6249. 80070a2: f890 303a ldrb.w r3, [r0, #58] ; 0x3a
  6250. {
  6251. 80070a6: b510 push {r4, lr}
  6252. if(huart->RxState == HAL_UART_STATE_BUSY_RX)
  6253. 80070a8: 2b22 cmp r3, #34 ; 0x22
  6254. 80070aa: d136 bne.n 800711a <UART_Receive_IT+0x78>
  6255. if(huart->Init.WordLength == UART_WORDLENGTH_9B)
  6256. 80070ac: 6883 ldr r3, [r0, #8]
  6257. 80070ae: 6901 ldr r1, [r0, #16]
  6258. 80070b0: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
  6259. 80070b4: 6802 ldr r2, [r0, #0]
  6260. 80070b6: 6a83 ldr r3, [r0, #40] ; 0x28
  6261. 80070b8: d123 bne.n 8007102 <UART_Receive_IT+0x60>
  6262. *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
  6263. 80070ba: 6852 ldr r2, [r2, #4]
  6264. if(huart->Init.Parity == UART_PARITY_NONE)
  6265. 80070bc: b9e9 cbnz r1, 80070fa <UART_Receive_IT+0x58>
  6266. *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
  6267. 80070be: f3c2 0208 ubfx r2, r2, #0, #9
  6268. 80070c2: f823 2b02 strh.w r2, [r3], #2
  6269. huart->pRxBuffPtr += 1U;
  6270. 80070c6: 6283 str r3, [r0, #40] ; 0x28
  6271. if(--huart->RxXferCount == 0U)
  6272. 80070c8: 8dc4 ldrh r4, [r0, #46] ; 0x2e
  6273. 80070ca: 3c01 subs r4, #1
  6274. 80070cc: b2a4 uxth r4, r4
  6275. 80070ce: 85c4 strh r4, [r0, #46] ; 0x2e
  6276. 80070d0: b98c cbnz r4, 80070f6 <UART_Receive_IT+0x54>
  6277. __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
  6278. 80070d2: 6803 ldr r3, [r0, #0]
  6279. 80070d4: 68da ldr r2, [r3, #12]
  6280. 80070d6: f022 0220 bic.w r2, r2, #32
  6281. 80070da: 60da str r2, [r3, #12]
  6282. __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
  6283. 80070dc: 68da ldr r2, [r3, #12]
  6284. 80070de: f422 7280 bic.w r2, r2, #256 ; 0x100
  6285. 80070e2: 60da str r2, [r3, #12]
  6286. __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
  6287. 80070e4: 695a ldr r2, [r3, #20]
  6288. 80070e6: f022 0201 bic.w r2, r2, #1
  6289. 80070ea: 615a str r2, [r3, #20]
  6290. huart->RxState = HAL_UART_STATE_READY;
  6291. 80070ec: 2320 movs r3, #32
  6292. 80070ee: f880 303a strb.w r3, [r0, #58] ; 0x3a
  6293. HAL_UART_RxCpltCallback(huart);
  6294. 80070f2: f001 fc01 bl 80088f8 <HAL_UART_RxCpltCallback>
  6295. if(--huart->RxXferCount == 0U)
  6296. 80070f6: 2000 movs r0, #0
  6297. }
  6298. 80070f8: bd10 pop {r4, pc}
  6299. *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF);
  6300. 80070fa: b2d2 uxtb r2, r2
  6301. 80070fc: f823 2b01 strh.w r2, [r3], #1
  6302. 8007100: e7e1 b.n 80070c6 <UART_Receive_IT+0x24>
  6303. if(huart->Init.Parity == UART_PARITY_NONE)
  6304. 8007102: b921 cbnz r1, 800710e <UART_Receive_IT+0x6c>
  6305. *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
  6306. 8007104: 1c59 adds r1, r3, #1
  6307. 8007106: 6852 ldr r2, [r2, #4]
  6308. 8007108: 6281 str r1, [r0, #40] ; 0x28
  6309. *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
  6310. 800710a: 701a strb r2, [r3, #0]
  6311. 800710c: e7dc b.n 80070c8 <UART_Receive_IT+0x26>
  6312. 800710e: 6852 ldr r2, [r2, #4]
  6313. 8007110: 1c59 adds r1, r3, #1
  6314. 8007112: 6281 str r1, [r0, #40] ; 0x28
  6315. 8007114: f002 027f and.w r2, r2, #127 ; 0x7f
  6316. 8007118: e7f7 b.n 800710a <UART_Receive_IT+0x68>
  6317. return HAL_BUSY;
  6318. 800711a: 2002 movs r0, #2
  6319. 800711c: bd10 pop {r4, pc}
  6320. 0800711e <HAL_UART_RxHalfCpltCallback>:
  6321. 800711e: 4770 bx lr
  6322. 08007120 <UART_DMARxHalfCplt>:
  6323. {
  6324. 8007120: b508 push {r3, lr}
  6325. HAL_UART_RxHalfCpltCallback(huart);
  6326. 8007122: 6a40 ldr r0, [r0, #36] ; 0x24
  6327. 8007124: f7ff fffb bl 800711e <HAL_UART_RxHalfCpltCallback>
  6328. 8007128: bd08 pop {r3, pc}
  6329. 0800712a <HAL_UART_ErrorCallback>:
  6330. 800712a: 4770 bx lr
  6331. 0800712c <UART_DMAError>:
  6332. UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
  6333. 800712c: 6a41 ldr r1, [r0, #36] ; 0x24
  6334. {
  6335. 800712e: b508 push {r3, lr}
  6336. dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
  6337. 8007130: 680b ldr r3, [r1, #0]
  6338. 8007132: 695a ldr r2, [r3, #20]
  6339. if((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
  6340. 8007134: f891 0039 ldrb.w r0, [r1, #57] ; 0x39
  6341. 8007138: 2821 cmp r0, #33 ; 0x21
  6342. 800713a: d10a bne.n 8007152 <UART_DMAError+0x26>
  6343. 800713c: 0612 lsls r2, r2, #24
  6344. 800713e: d508 bpl.n 8007152 <UART_DMAError+0x26>
  6345. huart->TxXferCount = 0U;
  6346. 8007140: 2200 movs r2, #0
  6347. 8007142: 84ca strh r2, [r1, #38] ; 0x26
  6348. CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
  6349. 8007144: 68da ldr r2, [r3, #12]
  6350. 8007146: f022 02c0 bic.w r2, r2, #192 ; 0xc0
  6351. 800714a: 60da str r2, [r3, #12]
  6352. huart->gState = HAL_UART_STATE_READY;
  6353. 800714c: 2220 movs r2, #32
  6354. 800714e: f881 2039 strb.w r2, [r1, #57] ; 0x39
  6355. dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
  6356. 8007152: 695b ldr r3, [r3, #20]
  6357. if((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
  6358. 8007154: f891 203a ldrb.w r2, [r1, #58] ; 0x3a
  6359. 8007158: 2a22 cmp r2, #34 ; 0x22
  6360. 800715a: d106 bne.n 800716a <UART_DMAError+0x3e>
  6361. 800715c: 065b lsls r3, r3, #25
  6362. 800715e: d504 bpl.n 800716a <UART_DMAError+0x3e>
  6363. huart->RxXferCount = 0U;
  6364. 8007160: 2300 movs r3, #0
  6365. UART_EndRxTransfer(huart);
  6366. 8007162: 4608 mov r0, r1
  6367. huart->RxXferCount = 0U;
  6368. 8007164: 85cb strh r3, [r1, #46] ; 0x2e
  6369. UART_EndRxTransfer(huart);
  6370. 8007166: f7ff fd83 bl 8006c70 <UART_EndRxTransfer>
  6371. huart->ErrorCode |= HAL_UART_ERROR_DMA;
  6372. 800716a: 6bcb ldr r3, [r1, #60] ; 0x3c
  6373. HAL_UART_ErrorCallback(huart);
  6374. 800716c: 4608 mov r0, r1
  6375. huart->ErrorCode |= HAL_UART_ERROR_DMA;
  6376. 800716e: f043 0310 orr.w r3, r3, #16
  6377. 8007172: 63cb str r3, [r1, #60] ; 0x3c
  6378. HAL_UART_ErrorCallback(huart);
  6379. 8007174: f7ff ffd9 bl 800712a <HAL_UART_ErrorCallback>
  6380. 8007178: bd08 pop {r3, pc}
  6381. ...
  6382. 0800717c <HAL_UART_IRQHandler>:
  6383. uint32_t isrflags = READ_REG(huart->Instance->SR);
  6384. 800717c: 6803 ldr r3, [r0, #0]
  6385. {
  6386. 800717e: b570 push {r4, r5, r6, lr}
  6387. uint32_t isrflags = READ_REG(huart->Instance->SR);
  6388. 8007180: 681a ldr r2, [r3, #0]
  6389. {
  6390. 8007182: 4604 mov r4, r0
  6391. if(errorflags == RESET)
  6392. 8007184: 0716 lsls r6, r2, #28
  6393. uint32_t cr1its = READ_REG(huart->Instance->CR1);
  6394. 8007186: 68d9 ldr r1, [r3, #12]
  6395. uint32_t cr3its = READ_REG(huart->Instance->CR3);
  6396. 8007188: 695d ldr r5, [r3, #20]
  6397. if(errorflags == RESET)
  6398. 800718a: d107 bne.n 800719c <HAL_UART_IRQHandler+0x20>
  6399. if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
  6400. 800718c: 0696 lsls r6, r2, #26
  6401. 800718e: d55a bpl.n 8007246 <HAL_UART_IRQHandler+0xca>
  6402. 8007190: 068d lsls r5, r1, #26
  6403. 8007192: d558 bpl.n 8007246 <HAL_UART_IRQHandler+0xca>
  6404. }
  6405. 8007194: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr}
  6406. UART_Receive_IT(huart);
  6407. 8007198: f7ff bf83 b.w 80070a2 <UART_Receive_IT>
  6408. if((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
  6409. 800719c: f015 0501 ands.w r5, r5, #1
  6410. 80071a0: d102 bne.n 80071a8 <HAL_UART_IRQHandler+0x2c>
  6411. 80071a2: f411 7f90 tst.w r1, #288 ; 0x120
  6412. 80071a6: d04e beq.n 8007246 <HAL_UART_IRQHandler+0xca>
  6413. if(((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
  6414. 80071a8: 07d3 lsls r3, r2, #31
  6415. 80071aa: d505 bpl.n 80071b8 <HAL_UART_IRQHandler+0x3c>
  6416. 80071ac: 05ce lsls r6, r1, #23
  6417. huart->ErrorCode |= HAL_UART_ERROR_PE;
  6418. 80071ae: bf42 ittt mi
  6419. 80071b0: 6be3 ldrmi r3, [r4, #60] ; 0x3c
  6420. 80071b2: f043 0301 orrmi.w r3, r3, #1
  6421. 80071b6: 63e3 strmi r3, [r4, #60] ; 0x3c
  6422. if(((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
  6423. 80071b8: 0750 lsls r0, r2, #29
  6424. 80071ba: d504 bpl.n 80071c6 <HAL_UART_IRQHandler+0x4a>
  6425. 80071bc: b11d cbz r5, 80071c6 <HAL_UART_IRQHandler+0x4a>
  6426. huart->ErrorCode |= HAL_UART_ERROR_NE;
  6427. 80071be: 6be3 ldr r3, [r4, #60] ; 0x3c
  6428. 80071c0: f043 0302 orr.w r3, r3, #2
  6429. 80071c4: 63e3 str r3, [r4, #60] ; 0x3c
  6430. if(((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
  6431. 80071c6: 0793 lsls r3, r2, #30
  6432. 80071c8: d504 bpl.n 80071d4 <HAL_UART_IRQHandler+0x58>
  6433. 80071ca: b11d cbz r5, 80071d4 <HAL_UART_IRQHandler+0x58>
  6434. huart->ErrorCode |= HAL_UART_ERROR_FE;
  6435. 80071cc: 6be3 ldr r3, [r4, #60] ; 0x3c
  6436. 80071ce: f043 0304 orr.w r3, r3, #4
  6437. 80071d2: 63e3 str r3, [r4, #60] ; 0x3c
  6438. if(((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
  6439. 80071d4: 0716 lsls r6, r2, #28
  6440. 80071d6: d504 bpl.n 80071e2 <HAL_UART_IRQHandler+0x66>
  6441. 80071d8: b11d cbz r5, 80071e2 <HAL_UART_IRQHandler+0x66>
  6442. huart->ErrorCode |= HAL_UART_ERROR_ORE;
  6443. 80071da: 6be3 ldr r3, [r4, #60] ; 0x3c
  6444. 80071dc: f043 0308 orr.w r3, r3, #8
  6445. 80071e0: 63e3 str r3, [r4, #60] ; 0x3c
  6446. if(huart->ErrorCode != HAL_UART_ERROR_NONE)
  6447. 80071e2: 6be3 ldr r3, [r4, #60] ; 0x3c
  6448. 80071e4: 2b00 cmp r3, #0
  6449. 80071e6: d066 beq.n 80072b6 <HAL_UART_IRQHandler+0x13a>
  6450. if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
  6451. 80071e8: 0695 lsls r5, r2, #26
  6452. 80071ea: d504 bpl.n 80071f6 <HAL_UART_IRQHandler+0x7a>
  6453. 80071ec: 0688 lsls r0, r1, #26
  6454. 80071ee: d502 bpl.n 80071f6 <HAL_UART_IRQHandler+0x7a>
  6455. UART_Receive_IT(huart);
  6456. 80071f0: 4620 mov r0, r4
  6457. 80071f2: f7ff ff56 bl 80070a2 <UART_Receive_IT>
  6458. dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
  6459. 80071f6: 6823 ldr r3, [r4, #0]
  6460. UART_EndRxTransfer(huart);
  6461. 80071f8: 4620 mov r0, r4
  6462. dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
  6463. 80071fa: 695d ldr r5, [r3, #20]
  6464. if(((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest)
  6465. 80071fc: 6be2 ldr r2, [r4, #60] ; 0x3c
  6466. 80071fe: 0711 lsls r1, r2, #28
  6467. 8007200: d402 bmi.n 8007208 <HAL_UART_IRQHandler+0x8c>
  6468. 8007202: f015 0540 ands.w r5, r5, #64 ; 0x40
  6469. 8007206: d01a beq.n 800723e <HAL_UART_IRQHandler+0xc2>
  6470. UART_EndRxTransfer(huart);
  6471. 8007208: f7ff fd32 bl 8006c70 <UART_EndRxTransfer>
  6472. if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
  6473. 800720c: 6823 ldr r3, [r4, #0]
  6474. 800720e: 695a ldr r2, [r3, #20]
  6475. 8007210: 0652 lsls r2, r2, #25
  6476. 8007212: d510 bpl.n 8007236 <HAL_UART_IRQHandler+0xba>
  6477. CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
  6478. 8007214: 695a ldr r2, [r3, #20]
  6479. if(huart->hdmarx != NULL)
  6480. 8007216: 6b60 ldr r0, [r4, #52] ; 0x34
  6481. CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
  6482. 8007218: f022 0240 bic.w r2, r2, #64 ; 0x40
  6483. 800721c: 615a str r2, [r3, #20]
  6484. if(huart->hdmarx != NULL)
  6485. 800721e: b150 cbz r0, 8007236 <HAL_UART_IRQHandler+0xba>
  6486. huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
  6487. 8007220: 4b25 ldr r3, [pc, #148] ; (80072b8 <HAL_UART_IRQHandler+0x13c>)
  6488. 8007222: 6343 str r3, [r0, #52] ; 0x34
  6489. if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
  6490. 8007224: f7fe fcf4 bl 8005c10 <HAL_DMA_Abort_IT>
  6491. 8007228: 2800 cmp r0, #0
  6492. 800722a: d044 beq.n 80072b6 <HAL_UART_IRQHandler+0x13a>
  6493. huart->hdmarx->XferAbortCallback(huart->hdmarx);
  6494. 800722c: 6b60 ldr r0, [r4, #52] ; 0x34
  6495. }
  6496. 800722e: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr}
  6497. huart->hdmarx->XferAbortCallback(huart->hdmarx);
  6498. 8007232: 6b43 ldr r3, [r0, #52] ; 0x34
  6499. 8007234: 4718 bx r3
  6500. HAL_UART_ErrorCallback(huart);
  6501. 8007236: 4620 mov r0, r4
  6502. 8007238: f7ff ff77 bl 800712a <HAL_UART_ErrorCallback>
  6503. 800723c: bd70 pop {r4, r5, r6, pc}
  6504. HAL_UART_ErrorCallback(huart);
  6505. 800723e: f7ff ff74 bl 800712a <HAL_UART_ErrorCallback>
  6506. huart->ErrorCode = HAL_UART_ERROR_NONE;
  6507. 8007242: 63e5 str r5, [r4, #60] ; 0x3c
  6508. 8007244: bd70 pop {r4, r5, r6, pc}
  6509. if(((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
  6510. 8007246: 0616 lsls r6, r2, #24
  6511. 8007248: d527 bpl.n 800729a <HAL_UART_IRQHandler+0x11e>
  6512. 800724a: 060d lsls r5, r1, #24
  6513. 800724c: d525 bpl.n 800729a <HAL_UART_IRQHandler+0x11e>
  6514. if(huart->gState == HAL_UART_STATE_BUSY_TX)
  6515. 800724e: f894 2039 ldrb.w r2, [r4, #57] ; 0x39
  6516. 8007252: 2a21 cmp r2, #33 ; 0x21
  6517. 8007254: d12f bne.n 80072b6 <HAL_UART_IRQHandler+0x13a>
  6518. if(huart->Init.WordLength == UART_WORDLENGTH_9B)
  6519. 8007256: 68a2 ldr r2, [r4, #8]
  6520. 8007258: f5b2 5f80 cmp.w r2, #4096 ; 0x1000
  6521. 800725c: 6a22 ldr r2, [r4, #32]
  6522. 800725e: d117 bne.n 8007290 <HAL_UART_IRQHandler+0x114>
  6523. huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
  6524. 8007260: 8811 ldrh r1, [r2, #0]
  6525. 8007262: f3c1 0108 ubfx r1, r1, #0, #9
  6526. 8007266: 6059 str r1, [r3, #4]
  6527. if(huart->Init.Parity == UART_PARITY_NONE)
  6528. 8007268: 6921 ldr r1, [r4, #16]
  6529. 800726a: b979 cbnz r1, 800728c <HAL_UART_IRQHandler+0x110>
  6530. huart->pTxBuffPtr += 2U;
  6531. 800726c: 3202 adds r2, #2
  6532. huart->pTxBuffPtr += 1U;
  6533. 800726e: 6222 str r2, [r4, #32]
  6534. if(--huart->TxXferCount == 0U)
  6535. 8007270: 8ce2 ldrh r2, [r4, #38] ; 0x26
  6536. 8007272: 3a01 subs r2, #1
  6537. 8007274: b292 uxth r2, r2
  6538. 8007276: 84e2 strh r2, [r4, #38] ; 0x26
  6539. 8007278: b9ea cbnz r2, 80072b6 <HAL_UART_IRQHandler+0x13a>
  6540. __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
  6541. 800727a: 68da ldr r2, [r3, #12]
  6542. 800727c: f022 0280 bic.w r2, r2, #128 ; 0x80
  6543. 8007280: 60da str r2, [r3, #12]
  6544. __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
  6545. 8007282: 68da ldr r2, [r3, #12]
  6546. 8007284: f042 0240 orr.w r2, r2, #64 ; 0x40
  6547. 8007288: 60da str r2, [r3, #12]
  6548. 800728a: bd70 pop {r4, r5, r6, pc}
  6549. huart->pTxBuffPtr += 1U;
  6550. 800728c: 3201 adds r2, #1
  6551. 800728e: e7ee b.n 800726e <HAL_UART_IRQHandler+0xf2>
  6552. huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF);
  6553. 8007290: 1c51 adds r1, r2, #1
  6554. 8007292: 6221 str r1, [r4, #32]
  6555. 8007294: 7812 ldrb r2, [r2, #0]
  6556. 8007296: 605a str r2, [r3, #4]
  6557. 8007298: e7ea b.n 8007270 <HAL_UART_IRQHandler+0xf4>
  6558. if(((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
  6559. 800729a: 0650 lsls r0, r2, #25
  6560. 800729c: d50b bpl.n 80072b6 <HAL_UART_IRQHandler+0x13a>
  6561. 800729e: 064a lsls r2, r1, #25
  6562. 80072a0: d509 bpl.n 80072b6 <HAL_UART_IRQHandler+0x13a>
  6563. __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
  6564. 80072a2: 68da ldr r2, [r3, #12]
  6565. HAL_UART_TxCpltCallback(huart);
  6566. 80072a4: 4620 mov r0, r4
  6567. __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
  6568. 80072a6: f022 0240 bic.w r2, r2, #64 ; 0x40
  6569. 80072aa: 60da str r2, [r3, #12]
  6570. huart->gState = HAL_UART_STATE_READY;
  6571. 80072ac: 2320 movs r3, #32
  6572. 80072ae: f884 3039 strb.w r3, [r4, #57] ; 0x39
  6573. HAL_UART_TxCpltCallback(huart);
  6574. 80072b2: f7ff febd bl 8007030 <HAL_UART_TxCpltCallback>
  6575. 80072b6: bd70 pop {r4, r5, r6, pc}
  6576. 80072b8: 080072bd .word 0x080072bd
  6577. 080072bc <UART_DMAAbortOnError>:
  6578. {
  6579. 80072bc: b508 push {r3, lr}
  6580. huart->RxXferCount = 0x00U;
  6581. 80072be: 2300 movs r3, #0
  6582. UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
  6583. 80072c0: 6a40 ldr r0, [r0, #36] ; 0x24
  6584. huart->RxXferCount = 0x00U;
  6585. 80072c2: 85c3 strh r3, [r0, #46] ; 0x2e
  6586. huart->TxXferCount = 0x00U;
  6587. 80072c4: 84c3 strh r3, [r0, #38] ; 0x26
  6588. HAL_UART_ErrorCallback(huart);
  6589. 80072c6: f7ff ff30 bl 800712a <HAL_UART_ErrorCallback>
  6590. 80072ca: bd08 pop {r3, pc}
  6591. 080072cc <AD5318_Ctrl>:
  6592. AD5318_Ctrl(0x57FF);
  6593. AD5318_Ctrl(0x68FF);
  6594. AD5318_Ctrl(0x79FF);
  6595. HAL_Delay(1);
  6596. }
  6597. void AD5318_Ctrl(uint16_t ShiftTarget) {
  6598. 80072cc: b570 push {r4, r5, r6, lr}
  6599. char i; /* serial counter */
  6600. // printf("ShiftTarget : %x \r\n",ShiftTarget);
  6601. HAL_GPIO_WritePin(DA_SYNC_GPIO_Port, DA_SYNC_Pin, GPIO_PIN_RESET);
  6602. 80072ce: 2200 movs r2, #0
  6603. void AD5318_Ctrl(uint16_t ShiftTarget) {
  6604. 80072d0: 4605 mov r5, r0
  6605. HAL_GPIO_WritePin(DA_SYNC_GPIO_Port, DA_SYNC_Pin, GPIO_PIN_RESET);
  6606. 80072d2: 2104 movs r1, #4
  6607. 80072d4: 4824 ldr r0, [pc, #144] ; (8007368 <AD5318_Ctrl+0x9c>)
  6608. 80072d6: f7fe fffd bl 80062d4 <HAL_GPIO_WritePin>
  6609. 80072da: 2410 movs r4, #16
  6610. for (i=0;i < 16;i++) { /* loop through all 16 data bits */
  6611. HAL_GPIO_WritePin(DA_SCLK_GPIO_Port, DA_SCLK_Pin, GPIO_PIN_SET); /* rise clk line again */
  6612. 80072dc: 4e22 ldr r6, [pc, #136] ; (8007368 <AD5318_Ctrl+0x9c>)
  6613. 80072de: 2201 movs r2, #1
  6614. 80072e0: 2108 movs r1, #8
  6615. 80072e2: 4630 mov r0, r6
  6616. 80072e4: f7fe fff6 bl 80062d4 <HAL_GPIO_WritePin>
  6617. if (ShiftTarget & 0x8000) HAL_GPIO_WritePin(DA_DIN_GPIO_Port, DA_DIN_Pin, GPIO_PIN_SET);
  6618. 80072e8: 042b lsls r3, r5, #16
  6619. 80072ea: bf4c ite mi
  6620. 80072ec: 2201 movmi r2, #1
  6621. else HAL_GPIO_WritePin(DA_DIN_GPIO_Port, DA_DIN_Pin, GPIO_PIN_RESET); /* set data bit */
  6622. 80072ee: 2200 movpl r2, #0
  6623. 80072f0: 2110 movs r1, #16
  6624. 80072f2: 4630 mov r0, r6
  6625. 80072f4: f7fe ffee bl 80062d4 <HAL_GPIO_WritePin>
  6626. 80072f8: 3c01 subs r4, #1
  6627. HAL_GPIO_WritePin(DA_SCLK_GPIO_Port, DA_SCLK_Pin, GPIO_PIN_RESET); /* lower clock line */
  6628. 80072fa: 2200 movs r2, #0
  6629. 80072fc: 2108 movs r1, #8
  6630. 80072fe: 4630 mov r0, r6
  6631. 8007300: f7fe ffe8 bl 80062d4 <HAL_GPIO_WritePin>
  6632. ShiftTarget <<= 1;
  6633. 8007304: 006d lsls r5, r5, #1
  6634. for (i=0;i < 16;i++) { /* loop through all 16 data bits */
  6635. 8007306: f014 04ff ands.w r4, r4, #255 ; 0xff
  6636. ShiftTarget <<= 1;
  6637. 800730a: b2ad uxth r5, r5
  6638. for (i=0;i < 16;i++) { /* loop through all 16 data bits */
  6639. 800730c: d1e7 bne.n 80072de <AD5318_Ctrl+0x12>
  6640. }
  6641. HAL_GPIO_WritePin(DA_LDAC_GPIO_Port, DA_LDAC_Pin, GPIO_PIN_SET);
  6642. 800730e: 2201 movs r2, #1
  6643. 8007310: f44f 4100 mov.w r1, #32768 ; 0x8000
  6644. 8007314: 4815 ldr r0, [pc, #84] ; (800736c <AD5318_Ctrl+0xa0>)
  6645. 8007316: f7fe ffdd bl 80062d4 <HAL_GPIO_WritePin>
  6646. Pol_Delay_us(10);
  6647. 800731a: 200a movs r0, #10
  6648. 800731c: f000 fd24 bl 8007d68 <Pol_Delay_us>
  6649. HAL_GPIO_WritePin(DA_LDAC_GPIO_Port, DA_LDAC_Pin, GPIO_PIN_RESET);
  6650. 8007320: 4622 mov r2, r4
  6651. 8007322: f44f 4100 mov.w r1, #32768 ; 0x8000
  6652. 8007326: 4811 ldr r0, [pc, #68] ; (800736c <AD5318_Ctrl+0xa0>)
  6653. 8007328: f7fe ffd4 bl 80062d4 <HAL_GPIO_WritePin>
  6654. HAL_GPIO_WritePin(DA_SYNC_GPIO_Port, DA_SYNC_Pin, GPIO_PIN_SET);
  6655. 800732c: 2201 movs r2, #1
  6656. 800732e: 2104 movs r1, #4
  6657. 8007330: 480d ldr r0, [pc, #52] ; (8007368 <AD5318_Ctrl+0x9c>)
  6658. 8007332: f7fe ffcf bl 80062d4 <HAL_GPIO_WritePin>
  6659. HAL_GPIO_WritePin(DA_DIN_GPIO_Port, DA_DIN_Pin, GPIO_PIN_RESET);
  6660. 8007336: 4622 mov r2, r4
  6661. 8007338: 2110 movs r1, #16
  6662. 800733a: 480b ldr r0, [pc, #44] ; (8007368 <AD5318_Ctrl+0x9c>)
  6663. 800733c: f7fe ffca bl 80062d4 <HAL_GPIO_WritePin>
  6664. HAL_GPIO_WritePin(DA_LDAC_GPIO_Port, DA_LDAC_Pin, GPIO_PIN_SET);
  6665. 8007340: 2201 movs r2, #1
  6666. 8007342: f44f 4100 mov.w r1, #32768 ; 0x8000
  6667. 8007346: 4809 ldr r0, [pc, #36] ; (800736c <AD5318_Ctrl+0xa0>)
  6668. 8007348: f7fe ffc4 bl 80062d4 <HAL_GPIO_WritePin>
  6669. /* rise DAC SYNC line again */
  6670. HAL_GPIO_WritePin(DA_SYNC_GPIO_Port, DA_SYNC_Pin, GPIO_PIN_RESET);
  6671. 800734c: 4622 mov r2, r4
  6672. 800734e: 2104 movs r1, #4
  6673. 8007350: 4805 ldr r0, [pc, #20] ; (8007368 <AD5318_Ctrl+0x9c>)
  6674. 8007352: f7fe ffbf bl 80062d4 <HAL_GPIO_WritePin>
  6675. HAL_GPIO_WritePin(DA_LDAC_GPIO_Port, DA_LDAC_Pin, GPIO_PIN_RESET);
  6676. 8007356: 4622 mov r2, r4
  6677. }
  6678. 8007358: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr}
  6679. HAL_GPIO_WritePin(DA_LDAC_GPIO_Port, DA_LDAC_Pin, GPIO_PIN_RESET);
  6680. 800735c: f44f 4100 mov.w r1, #32768 ; 0x8000
  6681. 8007360: 4802 ldr r0, [pc, #8] ; (800736c <AD5318_Ctrl+0xa0>)
  6682. 8007362: f7fe bfb7 b.w 80062d4 <HAL_GPIO_WritePin>
  6683. 8007366: bf00 nop
  6684. 8007368: 40012000 .word 0x40012000
  6685. 800736c: 40011400 .word 0x40011400
  6686. 08007370 <BDA4601_atten_ctrl>:
  6687. BDA4601_atten_ctrl(BDA4601_2_1G_UL3,0);
  6688. BDA4601_atten_ctrl(BDA4601_2_1G_UL4,0);
  6689. }
  6690. void BDA4601_atten_ctrl(BDA4601_st BDA ,uint8_t data){
  6691. 8007370: b084 sub sp, #16
  6692. 8007372: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
  6693. 8007376: ac0a add r4, sp, #40 ; 0x28
  6694. 8007378: e884 000f stmia.w r4, {r0, r1, r2, r3}
  6695. 800737c: 9e0e ldr r6, [sp, #56] ; 0x38
  6696. 800737e: f8bd 703c ldrh.w r7, [sp, #60] ; 0x3c
  6697. printf("BDA4601_atten_ctrl : %x \r\n",data);
  6698. #endif /* DEBUG_PRINT */
  6699. #endif /* DEBUG_PRINT */
  6700. data = 4 * data;
  6701. temp = (uint8_t)data;
  6702. HAL_GPIO_WritePin(BDA.LE_PORT,BDA.LE_PIN,GPIO_PIN_RESET);
  6703. 8007382: 2200 movs r2, #0
  6704. 8007384: 4639 mov r1, r7
  6705. 8007386: 4681 mov r9, r0
  6706. 8007388: 4630 mov r0, r6
  6707. void BDA4601_atten_ctrl(BDA4601_st BDA ,uint8_t data){
  6708. 800738a: f89d 5040 ldrb.w r5, [sp, #64] ; 0x40
  6709. 800738e: f8bd a02c ldrh.w sl, [sp, #44] ; 0x2c
  6710. 8007392: f8dd 8030 ldr.w r8, [sp, #48] ; 0x30
  6711. 8007396: f8bd b034 ldrh.w fp, [sp, #52] ; 0x34
  6712. HAL_GPIO_WritePin(BDA.LE_PORT,BDA.LE_PIN,GPIO_PIN_RESET);
  6713. 800739a: f7fe ff9b bl 80062d4 <HAL_GPIO_WritePin>
  6714. HAL_Delay(1);
  6715. 800739e: 2001 movs r0, #1
  6716. 80073a0: f7fe f8a4 bl 80054ec <HAL_Delay>
  6717. 80073a4: 2408 movs r4, #8
  6718. data = 4 * data;
  6719. 80073a6: 00ad lsls r5, r5, #2
  6720. 80073a8: b2ed uxtb r5, r5
  6721. for(i = 0; i < 8; i++){
  6722. if((uint8_t)temp & 0x01){
  6723. 80073aa: f015 0201 ands.w r2, r5, #1
  6724. HAL_GPIO_WritePin(BDA.SERIAL_IN_PORT,BDA.SERIAL_IN_PIN,GPIO_PIN_SET);//DATA
  6725. 80073ae: bf18 it ne
  6726. 80073b0: 2201 movne r2, #1
  6727. }
  6728. else{
  6729. HAL_GPIO_WritePin(BDA.SERIAL_IN_PORT,BDA.SERIAL_IN_PIN,GPIO_PIN_RESET);//DATA
  6730. 80073b2: 4659 mov r1, fp
  6731. 80073b4: 4640 mov r0, r8
  6732. 80073b6: f7fe ff8d bl 80062d4 <HAL_GPIO_WritePin>
  6733. }
  6734. HAL_GPIO_WritePin(BDA.CLK_PORT,BDA.CLK_PIN,GPIO_PIN_SET);//CLOCK
  6735. 80073ba: 2201 movs r2, #1
  6736. 80073bc: 4651 mov r1, sl
  6737. 80073be: 4648 mov r0, r9
  6738. 80073c0: f7fe ff88 bl 80062d4 <HAL_GPIO_WritePin>
  6739. HAL_Delay(1);
  6740. 80073c4: 2001 movs r0, #1
  6741. 80073c6: f7fe f891 bl 80054ec <HAL_Delay>
  6742. HAL_GPIO_WritePin(BDA.CLK_PORT,BDA.CLK_PIN,GPIO_PIN_RESET);//CLOCK
  6743. 80073ca: 2200 movs r2, #0
  6744. 80073cc: 4651 mov r1, sl
  6745. 80073ce: 4648 mov r0, r9
  6746. 80073d0: f7fe ff80 bl 80062d4 <HAL_GPIO_WritePin>
  6747. 80073d4: 3c01 subs r4, #1
  6748. HAL_Delay(1);
  6749. 80073d6: 2001 movs r0, #1
  6750. 80073d8: f7fe f888 bl 80054ec <HAL_Delay>
  6751. for(i = 0; i < 8; i++){
  6752. 80073dc: f014 04ff ands.w r4, r4, #255 ; 0xff
  6753. temp >>= 1;
  6754. 80073e0: ea4f 0555 mov.w r5, r5, lsr #1
  6755. for(i = 0; i < 8; i++){
  6756. 80073e4: d1e1 bne.n 80073aa <BDA4601_atten_ctrl+0x3a>
  6757. }
  6758. HAL_GPIO_WritePin(BDA.CLK_PORT,BDA.CLK_PIN,GPIO_PIN_RESET);//CLOCK
  6759. 80073e6: 4622 mov r2, r4
  6760. 80073e8: 4651 mov r1, sl
  6761. 80073ea: 4648 mov r0, r9
  6762. 80073ec: f7fe ff72 bl 80062d4 <HAL_GPIO_WritePin>
  6763. HAL_GPIO_WritePin(BDA.SERIAL_IN_PORT,GPIO_PIN_15,GPIO_PIN_RESET);//DATA
  6764. 80073f0: 4622 mov r2, r4
  6765. 80073f2: f44f 4100 mov.w r1, #32768 ; 0x8000
  6766. 80073f6: 4640 mov r0, r8
  6767. 80073f8: f7fe ff6c bl 80062d4 <HAL_GPIO_WritePin>
  6768. HAL_Delay(5);
  6769. 80073fc: 2005 movs r0, #5
  6770. 80073fe: f7fe f875 bl 80054ec <HAL_Delay>
  6771. HAL_GPIO_WritePin(BDA.LE_PORT,BDA.LE_PIN,GPIO_PIN_SET);//LE
  6772. 8007402: 4639 mov r1, r7
  6773. 8007404: 2201 movs r2, #1
  6774. 8007406: 4630 mov r0, r6
  6775. 8007408: f7fe ff64 bl 80062d4 <HAL_GPIO_WritePin>
  6776. HAL_Delay(1);
  6777. 800740c: 2001 movs r0, #1
  6778. 800740e: f7fe f86d bl 80054ec <HAL_Delay>
  6779. HAL_GPIO_WritePin(BDA.LE_PORT,BDA.LE_PIN,GPIO_PIN_RESET);
  6780. 8007412: 4622 mov r2, r4
  6781. 8007414: 4639 mov r1, r7
  6782. 8007416: 4630 mov r0, r6
  6783. }
  6784. 8007418: e8bd 4ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
  6785. 800741c: b004 add sp, #16
  6786. HAL_GPIO_WritePin(BDA.LE_PORT,BDA.LE_PIN,GPIO_PIN_RESET);
  6787. 800741e: f7fe bf59 b.w 80062d4 <HAL_GPIO_WritePin>
  6788. 08007422 <STH30_CreateCrc>:
  6789. }
  6790. return(crc16);
  6791. }
  6792. uint8_t STH30_CreateCrc(uint8_t *data, uint8_t nbrOfBytes)
  6793. {
  6794. 8007422: b510 push {r4, lr}
  6795. uint8_t bit; // bit mask
  6796. uint8_t crc = 0xFF; // calculated checksum
  6797. 8007424: 23ff movs r3, #255 ; 0xff
  6798. uint8_t byteCtr; // byte counter
  6799. // calculates 8-Bit checksum with given polynomial
  6800. for(byteCtr = 0; byteCtr < nbrOfBytes; byteCtr++)
  6801. 8007426: 4604 mov r4, r0
  6802. 8007428: 1a22 subs r2, r4, r0
  6803. 800742a: b2d2 uxtb r2, r2
  6804. 800742c: 4291 cmp r1, r2
  6805. 800742e: d801 bhi.n 8007434 <STH30_CreateCrc+0x12>
  6806. if(crc & 0x80) crc = (crc << 1) ^ POLYNOMIAL;
  6807. else crc = (crc << 1);
  6808. }
  6809. }
  6810. return crc;
  6811. }
  6812. 8007430: 4618 mov r0, r3
  6813. 8007432: bd10 pop {r4, pc}
  6814. crc ^= (data[byteCtr]);
  6815. 8007434: f814 2b01 ldrb.w r2, [r4], #1
  6816. 8007438: 4053 eors r3, r2
  6817. 800743a: 2208 movs r2, #8
  6818. if(crc & 0x80) crc = (crc << 1) ^ POLYNOMIAL;
  6819. 800743c: f013 0f80 tst.w r3, #128 ; 0x80
  6820. 8007440: f102 32ff add.w r2, r2, #4294967295
  6821. 8007444: ea4f 0343 mov.w r3, r3, lsl #1
  6822. 8007448: bf18 it ne
  6823. 800744a: f083 0331 eorne.w r3, r3, #49 ; 0x31
  6824. for(bit = 8; bit > 0; --bit)
  6825. 800744e: f012 02ff ands.w r2, r2, #255 ; 0xff
  6826. else crc = (crc << 1);
  6827. 8007452: b2db uxtb r3, r3
  6828. for(bit = 8; bit > 0; --bit)
  6829. 8007454: d1f2 bne.n 800743c <STH30_CreateCrc+0x1a>
  6830. 8007456: e7e7 b.n 8007428 <STH30_CreateCrc+0x6>
  6831. 08007458 <STH30_CheckCrc>:
  6832. etError STH30_CheckCrc(uint8_t *data, uint8_t nbrOfBytes, uint8_t checksum)
  6833. {
  6834. 8007458: b530 push {r4, r5, lr}
  6835. uint8_t bit; // bit mask
  6836. uint8_t crc = 0xFF; // calculated checksum
  6837. 800745a: 23ff movs r3, #255 ; 0xff
  6838. uint8_t byteCtr; // byte counter
  6839. // calculates 8-Bit checksum with given polynomial
  6840. for(byteCtr = 0; byteCtr < nbrOfBytes; byteCtr++)
  6841. 800745c: 4605 mov r5, r0
  6842. 800745e: 1a2c subs r4, r5, r0
  6843. 8007460: b2e4 uxtb r4, r4
  6844. 8007462: 42a1 cmp r1, r4
  6845. 8007464: d803 bhi.n 800746e <STH30_CheckCrc+0x16>
  6846. else crc = (crc << 1);
  6847. }
  6848. }
  6849. if(crc != checksum) return CHECKSUM_ERROR;
  6850. else return NO_ERROR;
  6851. }
  6852. 8007466: 1a9b subs r3, r3, r2
  6853. 8007468: 4258 negs r0, r3
  6854. 800746a: 4158 adcs r0, r3
  6855. 800746c: bd30 pop {r4, r5, pc}
  6856. crc ^= (data[byteCtr]);
  6857. 800746e: f815 4b01 ldrb.w r4, [r5], #1
  6858. 8007472: 4063 eors r3, r4
  6859. 8007474: 2408 movs r4, #8
  6860. if(crc & 0x80) crc = (crc << 1) ^ POLYNOMIAL;
  6861. 8007476: f013 0f80 tst.w r3, #128 ; 0x80
  6862. 800747a: f104 34ff add.w r4, r4, #4294967295
  6863. 800747e: ea4f 0343 mov.w r3, r3, lsl #1
  6864. 8007482: bf18 it ne
  6865. 8007484: f083 0331 eorne.w r3, r3, #49 ; 0x31
  6866. for(bit = 8; bit > 0; --bit)
  6867. 8007488: f014 04ff ands.w r4, r4, #255 ; 0xff
  6868. else crc = (crc << 1);
  6869. 800748c: b2db uxtb r3, r3
  6870. for(bit = 8; bit > 0; --bit)
  6871. 800748e: d1f2 bne.n 8007476 <STH30_CheckCrc+0x1e>
  6872. 8007490: e7e5 b.n 800745e <STH30_CheckCrc+0x6>
  6873. 08007492 <Bit_Compare>:
  6874. ALL_ATT_3_5G.data3 = ATTEN_3_5G_Initial_Val;
  6875. ALL_ATT_3_5G.data4 = ATTEN_3_5G_Initial_Val;
  6876. PE43711_ALL_atten_ctrl(ALL_ATT_3_5G);
  6877. }
  6878. #endif // PYJ.2019.07.26_END --
  6879. void Bit_Compare(PE43711_st ATT,uint8_t data,uint8_t Shift_Index){
  6880. 8007492: b084 sub sp, #16
  6881. 8007494: e88d 000f stmia.w sp, {r0, r1, r2, r3}
  6882. 8007498: f89d 2018 ldrb.w r2, [sp, #24]
  6883. 800749c: f89d 301c ldrb.w r3, [sp, #28]
  6884. 80074a0: 9802 ldr r0, [sp, #8]
  6885. if(data & (0x01 << Shift_Index)){
  6886. 80074a2: 411a asrs r2, r3
  6887. 80074a4: f012 0201 ands.w r2, r2, #1
  6888. 80074a8: f8bd 100c ldrh.w r1, [sp, #12]
  6889. HAL_GPIO_WritePin(ATT.DATA_PORT,ATT.DATA_PIN,GPIO_PIN_SET);//DATA
  6890. 80074ac: bf18 it ne
  6891. 80074ae: 2201 movne r2, #1
  6892. }
  6893. else{
  6894. HAL_GPIO_WritePin(ATT.DATA_PORT,ATT.DATA_PIN,GPIO_PIN_RESET);//DATA
  6895. }
  6896. }
  6897. 80074b0: b004 add sp, #16
  6898. HAL_GPIO_WritePin(ATT.DATA_PORT,ATT.DATA_PIN,GPIO_PIN_RESET);//DATA
  6899. 80074b2: f7fe bf0f b.w 80062d4 <HAL_GPIO_WritePin>
  6900. ...
  6901. 080074b8 <PE43711_ALL_atten_ctrl>:
  6902. void PE43711_ALL_atten_ctrl(ALL_PE43711_st ATT){
  6903. 80074b8: b084 sub sp, #16
  6904. 80074ba: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
  6905. 80074be: b085 sub sp, #20
  6906. 80074c0: ac0e add r4, sp, #56 ; 0x38
  6907. 80074c2: e884 000f stmia.w r4, {r0, r1, r2, r3}
  6908. 80074c6: 9d12 ldr r5, [sp, #72] ; 0x48
  6909. 80074c8: f8bd 604c ldrh.w r6, [sp, #76] ; 0x4c
  6910. HAL_GPIO_WritePin(ATT.ATT0.LE_PORT,ATT.ATT0.LE_PIN,GPIO_PIN_RESET);
  6911. 80074cc: 2200 movs r2, #0
  6912. 80074ce: 4631 mov r1, r6
  6913. 80074d0: 4680 mov r8, r0
  6914. 80074d2: 4628 mov r0, r5
  6915. 80074d4: f8bd 903c ldrh.w r9, [sp, #60] ; 0x3c
  6916. 80074d8: f7fe fefc bl 80062d4 <HAL_GPIO_WritePin>
  6917. Pol_Delay_us(10);
  6918. 80074dc: 200a movs r0, #10
  6919. 80074de: f000 fc43 bl 8007d68 <Pol_Delay_us>
  6920. 80074e2: 2700 movs r7, #0
  6921. // printf("why not? \r\n");
  6922. for(uint8_t i = 0; i < 8; i++){
  6923. Bit_Compare(ATT.ATT0,ATT.data0,i);
  6924. 80074e4: f10d 0b48 add.w fp, sp, #72 ; 0x48
  6925. Bit_Compare(ATT.ATT1,ATT.data1,i);
  6926. 80074e8: f10d 0a64 add.w sl, sp, #100 ; 0x64
  6927. Bit_Compare(ATT.ATT0,ATT.data0,i);
  6928. 80074ec: f89d 3050 ldrb.w r3, [sp, #80] ; 0x50
  6929. 80074f0: b2fc uxtb r4, r7
  6930. 80074f2: 9302 str r3, [sp, #8]
  6931. 80074f4: 9512 str r5, [sp, #72] ; 0x48
  6932. 80074f6: f8ad 604c strh.w r6, [sp, #76] ; 0x4c
  6933. 80074fa: 9403 str r4, [sp, #12]
  6934. 80074fc: e89b 0003 ldmia.w fp, {r0, r1}
  6935. 8007500: e88d 0003 stmia.w sp, {r0, r1}
  6936. 8007504: f8cd 8038 str.w r8, [sp, #56] ; 0x38
  6937. 8007508: f8ad 903c strh.w r9, [sp, #60] ; 0x3c
  6938. 800750c: ab0e add r3, sp, #56 ; 0x38
  6939. 800750e: cb0f ldmia r3, {r0, r1, r2, r3}
  6940. 8007510: f7ff ffbf bl 8007492 <Bit_Compare>
  6941. Bit_Compare(ATT.ATT1,ATT.data1,i);
  6942. 8007514: f89d 306c ldrb.w r3, [sp, #108] ; 0x6c
  6943. 8007518: 9403 str r4, [sp, #12]
  6944. 800751a: 9302 str r3, [sp, #8]
  6945. 800751c: e89a 0003 ldmia.w sl, {r0, r1}
  6946. 8007520: e88d 0003 stmia.w sp, {r0, r1}
  6947. 8007524: ab15 add r3, sp, #84 ; 0x54
  6948. 8007526: cb0f ldmia r3, {r0, r1, r2, r3}
  6949. 8007528: f7ff ffb3 bl 8007492 <Bit_Compare>
  6950. Bit_Compare(ATT.ATT2,ATT.data2,i);
  6951. 800752c: f89d 3088 ldrb.w r3, [sp, #136] ; 0x88
  6952. 8007530: 9403 str r4, [sp, #12]
  6953. 8007532: 9302 str r3, [sp, #8]
  6954. 8007534: ab20 add r3, sp, #128 ; 0x80
  6955. 8007536: e893 0003 ldmia.w r3, {r0, r1}
  6956. 800753a: e88d 0003 stmia.w sp, {r0, r1}
  6957. 800753e: ab1c add r3, sp, #112 ; 0x70
  6958. 8007540: cb0f ldmia r3, {r0, r1, r2, r3}
  6959. 8007542: f7ff ffa6 bl 8007492 <Bit_Compare>
  6960. Bit_Compare(ATT.ATT3,ATT.data3,i);
  6961. 8007546: f89d 30a4 ldrb.w r3, [sp, #164] ; 0xa4
  6962. 800754a: 9403 str r4, [sp, #12]
  6963. 800754c: 9302 str r3, [sp, #8]
  6964. 800754e: ab27 add r3, sp, #156 ; 0x9c
  6965. 8007550: e893 0003 ldmia.w r3, {r0, r1}
  6966. 8007554: e88d 0003 stmia.w sp, {r0, r1}
  6967. 8007558: ab23 add r3, sp, #140 ; 0x8c
  6968. 800755a: cb0f ldmia r3, {r0, r1, r2, r3}
  6969. 800755c: f7ff ff99 bl 8007492 <Bit_Compare>
  6970. Bit_Compare(ATT.ATT4,ATT.data4,i);
  6971. 8007560: f89d 30c0 ldrb.w r3, [sp, #192] ; 0xc0
  6972. 8007564: 9403 str r4, [sp, #12]
  6973. 8007566: 9302 str r3, [sp, #8]
  6974. 8007568: ab2e add r3, sp, #184 ; 0xb8
  6975. 800756a: e893 0003 ldmia.w r3, {r0, r1}
  6976. 800756e: e88d 0003 stmia.w sp, {r0, r1}
  6977. 8007572: ab2a add r3, sp, #168 ; 0xa8
  6978. 8007574: cb0f ldmia r3, {r0, r1, r2, r3}
  6979. 8007576: f7ff ff8c bl 8007492 <Bit_Compare>
  6980. HAL_GPIO_WritePin(ATT.ATT0.CLK_PORT,ATT.ATT0.CLK_PIN,GPIO_PIN_SET);//CLOCK
  6981. 800757a: 2201 movs r2, #1
  6982. 800757c: 4649 mov r1, r9
  6983. 800757e: 4640 mov r0, r8
  6984. 8007580: f7fe fea8 bl 80062d4 <HAL_GPIO_WritePin>
  6985. Pol_Delay_us(10);
  6986. 8007584: 200a movs r0, #10
  6987. 8007586: f000 fbef bl 8007d68 <Pol_Delay_us>
  6988. 800758a: 3701 adds r7, #1
  6989. HAL_GPIO_WritePin(ATT.ATT0.CLK_PORT,ATT.ATT0.CLK_PIN,GPIO_PIN_RESET);//CLOCK
  6990. 800758c: 2200 movs r2, #0
  6991. 800758e: 4649 mov r1, r9
  6992. 8007590: 4640 mov r0, r8
  6993. 8007592: f7fe fe9f bl 80062d4 <HAL_GPIO_WritePin>
  6994. for(uint8_t i = 0; i < 8; i++){
  6995. 8007596: 2f08 cmp r7, #8
  6996. 8007598: d1a8 bne.n 80074ec <PE43711_ALL_atten_ctrl+0x34>
  6997. }
  6998. HAL_GPIO_WritePin(GPIOB,GPIO_PIN_15,GPIO_PIN_RESET);//DATA
  6999. 800759a: 2200 movs r2, #0
  7000. 800759c: f44f 4100 mov.w r1, #32768 ; 0x8000
  7001. 80075a0: 4809 ldr r0, [pc, #36] ; (80075c8 <PE43711_ALL_atten_ctrl+0x110>)
  7002. 80075a2: f7fe fe97 bl 80062d4 <HAL_GPIO_WritePin>
  7003. HAL_GPIO_WritePin(ATT.ATT0.LE_PORT,ATT.ATT0.LE_PIN,GPIO_PIN_SET);//LE
  7004. 80075a6: 4631 mov r1, r6
  7005. 80075a8: 2201 movs r2, #1
  7006. 80075aa: 4628 mov r0, r5
  7007. 80075ac: f7fe fe92 bl 80062d4 <HAL_GPIO_WritePin>
  7008. Pol_Delay_us(10);
  7009. 80075b0: 200a movs r0, #10
  7010. 80075b2: f000 fbd9 bl 8007d68 <Pol_Delay_us>
  7011. HAL_GPIO_WritePin(ATT.ATT0.LE_PORT,ATT.ATT0.LE_PIN,GPIO_PIN_RESET);
  7012. 80075b6: 2200 movs r2, #0
  7013. 80075b8: 4631 mov r1, r6
  7014. 80075ba: 4628 mov r0, r5
  7015. }
  7016. 80075bc: b005 add sp, #20
  7017. 80075be: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
  7018. 80075c2: b004 add sp, #16
  7019. HAL_GPIO_WritePin(ATT.ATT0.LE_PORT,ATT.ATT0.LE_PIN,GPIO_PIN_RESET);
  7020. 80075c4: f7fe be86 b.w 80062d4 <HAL_GPIO_WritePin>
  7021. 80075c8: 40010c00 .word 0x40010c00
  7022. 080075cc <PE43711_PinInit>:
  7023. void PE43711_PinInit(void){
  7024. 80075cc: b5f0 push {r4, r5, r6, r7, lr}
  7025. ALL_ATT_3_5G.ATT0 = ATT_3_5G_LOW1;
  7026. 80075ce: 4c21 ldr r4, [pc, #132] ; (8007654 <PE43711_PinInit+0x88>)
  7027. 80075d0: 4e21 ldr r6, [pc, #132] ; (8007658 <PE43711_PinInit+0x8c>)
  7028. 80075d2: 4625 mov r5, r4
  7029. 80075d4: ce0f ldmia r6!, {r0, r1, r2, r3}
  7030. 80075d6: c50f stmia r5!, {r0, r1, r2, r3}
  7031. 80075d8: e896 0003 ldmia.w r6, {r0, r1}
  7032. ALL_ATT_3_5G.ATT1 = ATT_3_5G_HIGH1;
  7033. 80075dc: 4f1f ldr r7, [pc, #124] ; (800765c <PE43711_PinInit+0x90>)
  7034. 80075de: f104 061c add.w r6, r4, #28
  7035. ALL_ATT_3_5G.ATT0 = ATT_3_5G_LOW1;
  7036. 80075e2: e885 0003 stmia.w r5, {r0, r1}
  7037. ALL_ATT_3_5G.ATT1 = ATT_3_5G_HIGH1;
  7038. 80075e6: cf0f ldmia r7!, {r0, r1, r2, r3}
  7039. 80075e8: c60f stmia r6!, {r0, r1, r2, r3}
  7040. 80075ea: e897 0003 ldmia.w r7, {r0, r1}
  7041. ALL_ATT_3_5G.ATT2 = ATT_3_5G_COM1;
  7042. 80075ee: 4f1c ldr r7, [pc, #112] ; (8007660 <PE43711_PinInit+0x94>)
  7043. ALL_ATT_3_5G.ATT1 = ATT_3_5G_HIGH1;
  7044. 80075f0: e886 0003 stmia.w r6, {r0, r1}
  7045. ALL_ATT_3_5G.ATT2 = ATT_3_5G_COM1;
  7046. 80075f4: cf0f ldmia r7!, {r0, r1, r2, r3}
  7047. 80075f6: f104 0638 add.w r6, r4, #56 ; 0x38
  7048. 80075fa: c60f stmia r6!, {r0, r1, r2, r3}
  7049. 80075fc: e897 0003 ldmia.w r7, {r0, r1}
  7050. ALL_ATT_3_5G.ATT3 = ATT_3_5G_COM2;
  7051. 8007600: 4f18 ldr r7, [pc, #96] ; (8007664 <PE43711_PinInit+0x98>)
  7052. ALL_ATT_3_5G.ATT2 = ATT_3_5G_COM1;
  7053. 8007602: e886 0003 stmia.w r6, {r0, r1}
  7054. ALL_ATT_3_5G.ATT3 = ATT_3_5G_COM2;
  7055. 8007606: cf0f ldmia r7!, {r0, r1, r2, r3}
  7056. 8007608: f104 0654 add.w r6, r4, #84 ; 0x54
  7057. 800760c: c60f stmia r6!, {r0, r1, r2, r3}
  7058. 800760e: e897 0003 ldmia.w r7, {r0, r1}
  7059. ALL_ATT_3_5G.ATT4 = ATT_3_5G_COM3;
  7060. 8007612: 4f15 ldr r7, [pc, #84] ; (8007668 <PE43711_PinInit+0x9c>)
  7061. ALL_ATT_3_5G.ATT3 = ATT_3_5G_COM2;
  7062. 8007614: e886 0003 stmia.w r6, {r0, r1}
  7063. ALL_ATT_3_5G.ATT4 = ATT_3_5G_COM3;
  7064. 8007618: cf0f ldmia r7!, {r0, r1, r2, r3}
  7065. 800761a: f104 0670 add.w r6, r4, #112 ; 0x70
  7066. 800761e: c60f stmia r6!, {r0, r1, r2, r3}
  7067. 8007620: e897 0003 ldmia.w r7, {r0, r1}
  7068. ALL_ATT_3_5G.data0 = ATTEN_3_5G_Initial_Val;
  7069. 8007624: 2300 movs r3, #0
  7070. void PE43711_PinInit(void){
  7071. 8007626: b0a1 sub sp, #132 ; 0x84
  7072. ALL_ATT_3_5G.ATT4 = ATT_3_5G_COM3;
  7073. 8007628: e886 0003 stmia.w r6, {r0, r1}
  7074. PE43711_ALL_atten_ctrl(ALL_ATT_3_5G);
  7075. 800762c: 227c movs r2, #124 ; 0x7c
  7076. 800762e: 4629 mov r1, r5
  7077. 8007630: 4668 mov r0, sp
  7078. ALL_ATT_3_5G.data0 = ATTEN_3_5G_Initial_Val;
  7079. 8007632: 7623 strb r3, [r4, #24]
  7080. ALL_ATT_3_5G.data1 = ATTEN_3_5G_Initial_Val;
  7081. 8007634: f884 3034 strb.w r3, [r4, #52] ; 0x34
  7082. ALL_ATT_3_5G.data2 = ATTEN_3_5G_Initial_Val;
  7083. 8007638: f884 3050 strb.w r3, [r4, #80] ; 0x50
  7084. ALL_ATT_3_5G.data3 = ATTEN_3_5G_Initial_Val;
  7085. 800763c: f884 306c strb.w r3, [r4, #108] ; 0x6c
  7086. ALL_ATT_3_5G.data4 = ATTEN_3_5G_Initial_Val;
  7087. 8007640: f884 3088 strb.w r3, [r4, #136] ; 0x88
  7088. PE43711_ALL_atten_ctrl(ALL_ATT_3_5G);
  7089. 8007644: f001 fe82 bl 800934c <memcpy>
  7090. 8007648: e894 000f ldmia.w r4, {r0, r1, r2, r3}
  7091. 800764c: f7ff ff34 bl 80074b8 <PE43711_ALL_atten_ctrl>
  7092. }
  7093. 8007650: b021 add sp, #132 ; 0x84
  7094. 8007652: bdf0 pop {r4, r5, r6, r7, pc}
  7095. 8007654: 200004e8 .word 0x200004e8
  7096. 8007658: 20000188 .word 0x20000188
  7097. 800765c: 20000170 .word 0x20000170
  7098. 8007660: 20000128 .word 0x20000128
  7099. 8007664: 20000140 .word 0x20000140
  7100. 8007668: 20000158 .word 0x20000158
  7101. 0800766c <N_Divider_Reg_Create>:
  7102. double N_Reg_Value_Calc(double val){
  7103. return val / 1000;
  7104. }
  7105. uint32_t N_Divider_Reg_Create(uint16_t _FRAC,uint16_t _INT,uint8_t _FASTLOCK){
  7106. 800766c: b570 push {r4, r5, r6, lr}
  7107. 800766e: 2302 movs r3, #2
  7108. 8007670: 4604 mov r4, r0
  7109. #ifdef DEBUG_PRINT
  7110. printf("\r\nLINE : %d ret : %x\r\n",__LINE__,ret);
  7111. #endif /* DEBUG_PRINT */
  7112. for(i = 2; i < 14; i++){
  7113. if(_FRAC & 0x01)
  7114. ret += shift_bit << i;
  7115. 8007672: 2501 movs r5, #1
  7116. uint32_t N_Divider_Reg_Create(uint16_t _FRAC,uint16_t _INT,uint8_t _FASTLOCK){
  7117. 8007674: 2000 movs r0, #0
  7118. if(_FRAC & 0x01)
  7119. 8007676: 07e6 lsls r6, r4, #31
  7120. ret += shift_bit << i;
  7121. 8007678: bf48 it mi
  7122. 800767a: fa05 f603 lslmi.w r6, r5, r3
  7123. 800767e: f103 0301 add.w r3, r3, #1
  7124. 8007682: bf48 it mi
  7125. 8007684: 1980 addmi r0, r0, r6
  7126. for(i = 2; i < 14; i++){
  7127. 8007686: 2b0e cmp r3, #14
  7128. _FRAC = _FRAC >> 1;
  7129. 8007688: ea4f 0454 mov.w r4, r4, lsr #1
  7130. for(i = 2; i < 14; i++){
  7131. 800768c: d1f3 bne.n 8007676 <N_Divider_Reg_Create+0xa>
  7132. #ifdef DEBUG_PRINT
  7133. printf("\r\nLINE : %d ret : %x\r\n",__LINE__,ret);
  7134. #endif /* DEBUG_PRINT */
  7135. for(i = 14; i < 22; i++){
  7136. if(_INT & 0x01)
  7137. ret += shift_bit << i;
  7138. 800768e: 2401 movs r4, #1
  7139. if(_INT & 0x01)
  7140. 8007690: 07cd lsls r5, r1, #31
  7141. ret += shift_bit << i;
  7142. 8007692: bf48 it mi
  7143. 8007694: fa04 f503 lslmi.w r5, r4, r3
  7144. 8007698: f103 0301 add.w r3, r3, #1
  7145. 800769c: bf48 it mi
  7146. 800769e: 1940 addmi r0, r0, r5
  7147. for(i = 14; i < 22; i++){
  7148. 80076a0: 2b16 cmp r3, #22
  7149. _INT = _INT >> 1;
  7150. 80076a2: ea4f 0151 mov.w r1, r1, lsr #1
  7151. for(i = 14; i < 22; i++){
  7152. 80076a6: d1f3 bne.n 8007690 <N_Divider_Reg_Create+0x24>
  7153. }
  7154. #ifdef DEBUG_PRINT
  7155. printf("\r\nLINE : %d ret : %x\r\n",__LINE__,ret);
  7156. #endif /* DEBUG_PRINT */
  7157. if(_FASTLOCK & 0x01)
  7158. 80076a8: 07d3 lsls r3, r2, #31
  7159. ret += shift_bit << i;
  7160. 80076aa: bf48 it mi
  7161. 80076ac: f500 0080 addmi.w r0, r0, #4194304 ; 0x400000
  7162. #ifdef DEBUG_PRINT
  7163. printf("\r\nLINE : %d ret : %x\r\n",__LINE__,ret);
  7164. #endif /* DEBUG_PRINT */
  7165. return ret;
  7166. }
  7167. 80076b0: bd70 pop {r4, r5, r6, pc}
  7168. 080076b2 <R_Divider_Reg_Create>:
  7169. uint32_t R_Divider_Reg_Create(uint16_t _MOD,uint8_t _RCOUNTER,uint8_t _PRESCALER,uint8_t _RESERVED,uint8_t _MUXOUT,uint8_t LOAD_CONTROL){
  7170. 80076b2: b5f0 push {r4, r5, r6, r7, lr}
  7171. 80076b4: 4606 mov r6, r0
  7172. 80076b6: 2001 movs r0, #1
  7173. 80076b8: 2402 movs r4, #2
  7174. #ifdef DEBUG_PRINT
  7175. printf("\r\nLINE : %d ret : %x\r\n",__LINE__,ret);
  7176. #endif /* DEBUG_PRINT */
  7177. for(i = 2; i < 14; i++){
  7178. if(_MOD & 0x01)
  7179. ret += shift_bit << i;
  7180. 80076ba: 4607 mov r7, r0
  7181. uint32_t R_Divider_Reg_Create(uint16_t _MOD,uint8_t _RCOUNTER,uint8_t _PRESCALER,uint8_t _RESERVED,uint8_t _MUXOUT,uint8_t LOAD_CONTROL){
  7182. 80076bc: f89d 5014 ldrb.w r5, [sp, #20]
  7183. if(_MOD & 0x01)
  7184. 80076c0: f016 0f01 tst.w r6, #1
  7185. ret += shift_bit << i;
  7186. 80076c4: bf18 it ne
  7187. 80076c6: fa07 fe04 lslne.w lr, r7, r4
  7188. 80076ca: f104 0401 add.w r4, r4, #1
  7189. 80076ce: bf18 it ne
  7190. 80076d0: 4470 addne r0, lr
  7191. for(i = 2; i < 14; i++){
  7192. 80076d2: 2c0e cmp r4, #14
  7193. _MOD = _MOD >> 1;
  7194. 80076d4: ea4f 0656 mov.w r6, r6, lsr #1
  7195. for(i = 2; i < 14; i++){
  7196. 80076d8: d1f2 bne.n 80076c0 <R_Divider_Reg_Create+0xe>
  7197. }
  7198. for(i = 14; i < 18; i++){
  7199. if(_RCOUNTER & 0x01)
  7200. ret += shift_bit << i;
  7201. 80076da: 2601 movs r6, #1
  7202. if(_RCOUNTER & 0x01)
  7203. 80076dc: 07cf lsls r7, r1, #31
  7204. ret += shift_bit << i;
  7205. 80076de: bf48 it mi
  7206. 80076e0: fa06 f704 lslmi.w r7, r6, r4
  7207. 80076e4: f104 0401 add.w r4, r4, #1
  7208. 80076e8: bf48 it mi
  7209. 80076ea: 19c0 addmi r0, r0, r7
  7210. for(i = 14; i < 18; i++){
  7211. 80076ec: 2c12 cmp r4, #18
  7212. _RCOUNTER = _RCOUNTER >> 1;
  7213. 80076ee: ea4f 0151 mov.w r1, r1, lsr #1
  7214. for(i = 14; i < 18; i++){
  7215. 80076f2: d1f3 bne.n 80076dc <R_Divider_Reg_Create+0x2a>
  7216. }
  7217. if(_PRESCALER & 0x01)
  7218. 80076f4: 07d7 lsls r7, r2, #31
  7219. ret += shift_bit << i++;
  7220. 80076f6: bf44 itt mi
  7221. 80076f8: f500 2080 addmi.w r0, r0, #262144 ; 0x40000
  7222. 80076fc: 2413 movmi r4, #19
  7223. if(_RESERVED & 0x01)
  7224. 80076fe: 07de lsls r6, r3, #31
  7225. ret += shift_bit << i++;
  7226. 8007700: bf42 ittt mi
  7227. 8007702: 2301 movmi r3, #1
  7228. 8007704: fa03 f404 lslmi.w r4, r3, r4
  7229. 8007708: 1900 addmi r0, r0, r4
  7230. for(i = 19; i < 22; i++){
  7231. if(_MUXOUT & 0x01)
  7232. 800770a: 07ec lsls r4, r5, #31
  7233. ret += shift_bit << i;
  7234. 800770c: bf48 it mi
  7235. 800770e: f500 2000 addmi.w r0, r0, #524288 ; 0x80000
  7236. _MUXOUT = _MUXOUT >> 1;
  7237. }
  7238. if(LOAD_CONTROL & 0x01)
  7239. 8007712: f89d 3018 ldrb.w r3, [sp, #24]
  7240. if(_MUXOUT & 0x01)
  7241. 8007716: 07a9 lsls r1, r5, #30
  7242. ret += shift_bit << i;
  7243. 8007718: bf48 it mi
  7244. 800771a: f500 1080 addmi.w r0, r0, #1048576 ; 0x100000
  7245. if(_MUXOUT & 0x01)
  7246. 800771e: 076a lsls r2, r5, #29
  7247. ret += shift_bit << i;
  7248. 8007720: bf48 it mi
  7249. 8007722: f500 1000 addmi.w r0, r0, #2097152 ; 0x200000
  7250. if(LOAD_CONTROL & 0x01)
  7251. 8007726: 07db lsls r3, r3, #31
  7252. ret += shift_bit << i++;
  7253. 8007728: bf48 it mi
  7254. 800772a: f500 0080 addmi.w r0, r0, #4194304 ; 0x400000
  7255. return ret;
  7256. }
  7257. 800772e: bdf0 pop {r4, r5, r6, r7, pc}
  7258. 08007730 <ADF4153_Freq_Calc>:
  7259. ADF4153_R_N_Reg_st ADF4153_Freq_Calc(unsigned long long Freq,unsigned long long REFin,uint8_t R_Counter,uint32_t chspacing){
  7260. 8007730: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
  7261. 8007734: 4616 mov r6, r2
  7262. adf4153_st temp_adf4153;
  7263. double temp = 0;
  7264. ADF4153_R_N_Reg_st temp_reg;
  7265. temp_adf4153.PFD_Value = REFin / (R_Counter * 1000);
  7266. 8007736: f44f 727a mov.w r2, #1000 ; 0x3e8
  7267. ADF4153_R_N_Reg_st ADF4153_Freq_Calc(unsigned long long Freq,unsigned long long REFin,uint8_t R_Counter,uint32_t chspacing){
  7268. 800773a: f89d b038 ldrb.w fp, [sp, #56] ; 0x38
  7269. temp_adf4153.MOD_Value = (temp_adf4153.PFD_Value / chspacing) * 1000;
  7270. 800773e: 2500 movs r5, #0
  7271. temp_adf4153.PFD_Value = REFin / (R_Counter * 1000);
  7272. 8007740: fb02 f20b mul.w r2, r2, fp
  7273. ADF4153_R_N_Reg_st ADF4153_Freq_Calc(unsigned long long Freq,unsigned long long REFin,uint8_t R_Counter,uint32_t chspacing){
  7274. 8007744: 4682 mov sl, r0
  7275. temp_adf4153.PFD_Value = REFin / (R_Counter * 1000);
  7276. 8007746: e9dd 010c ldrd r0, r1, [sp, #48] ; 0x30
  7277. ADF4153_R_N_Reg_st ADF4153_Freq_Calc(unsigned long long Freq,unsigned long long REFin,uint8_t R_Counter,uint32_t chspacing){
  7278. 800774a: 461f mov r7, r3
  7279. temp_adf4153.PFD_Value = REFin / (R_Counter * 1000);
  7280. 800774c: 17d3 asrs r3, r2, #31
  7281. 800774e: f7fd fcfd bl 800514c <__aeabi_uldivmod>
  7282. temp_adf4153.MOD_Value = (temp_adf4153.PFD_Value / chspacing) * 1000;
  7283. 8007752: 9a0f ldr r2, [sp, #60] ; 0x3c
  7284. 8007754: 462b mov r3, r5
  7285. temp_adf4153.PFD_Value = REFin / (R_Counter * 1000);
  7286. 8007756: 4680 mov r8, r0
  7287. 8007758: 4689 mov r9, r1
  7288. temp_adf4153.MOD_Value = (temp_adf4153.PFD_Value / chspacing) * 1000;
  7289. 800775a: f7fd fcf7 bl 800514c <__aeabi_uldivmod>
  7290. 800775e: ebc0 1440 rsb r4, r0, r0, lsl #5
  7291. temp_adf4153.N_Value = N_Reg_Value_Calc(((double)(Freq / 1000) / (double)(temp_adf4153.PFD_Value / 1000)));
  7292. 8007762: f44f 727a mov.w r2, #1000 ; 0x3e8
  7293. 8007766: 2300 movs r3, #0
  7294. temp_adf4153.MOD_Value = (temp_adf4153.PFD_Value / chspacing) * 1000;
  7295. 8007768: eb00 0484 add.w r4, r0, r4, lsl #2
  7296. temp_adf4153.N_Value = N_Reg_Value_Calc(((double)(Freq / 1000) / (double)(temp_adf4153.PFD_Value / 1000)));
  7297. 800776c: 4639 mov r1, r7
  7298. 800776e: 4630 mov r0, r6
  7299. 8007770: f7fd fcec bl 800514c <__aeabi_uldivmod>
  7300. 8007774: f7fc feee bl 8004554 <__aeabi_ul2d>
  7301. 8007778: f44f 727a mov.w r2, #1000 ; 0x3e8
  7302. 800777c: 4606 mov r6, r0
  7303. 800777e: 460f mov r7, r1
  7304. 8007780: 2300 movs r3, #0
  7305. 8007782: 4640 mov r0, r8
  7306. 8007784: 4649 mov r1, r9
  7307. 8007786: f7fd fce1 bl 800514c <__aeabi_uldivmod>
  7308. 800778a: f7fc fee3 bl 8004554 <__aeabi_ul2d>
  7309. 800778e: 4602 mov r2, r0
  7310. 8007790: 460b mov r3, r1
  7311. 8007792: 4630 mov r0, r6
  7312. 8007794: 4639 mov r1, r7
  7313. 8007796: f7fd f83d bl 8004814 <__aeabi_ddiv>
  7314. return val / 1000;
  7315. 800779a: 2200 movs r2, #0
  7316. 800779c: 4b1a ldr r3, [pc, #104] ; (8007808 <ADF4153_Freq_Calc+0xd8>)
  7317. 800779e: f7fd f839 bl 8004814 <__aeabi_ddiv>
  7318. 80077a2: 460f mov r7, r1
  7319. 80077a4: 4606 mov r6, r0
  7320. temp_adf4153.INT_Value = temp_adf4153.N_Value ;
  7321. 80077a6: f7fd f9e3 bl 8004b70 <__aeabi_d2uiz>
  7322. 80077aa: fa1f f880 uxth.w r8, r0
  7323. #ifdef DEBUG_PRINT
  7324. printf("\r\ntemp_adf4153.N_Value : %f temp_adf4153.INT_Value : %f temp_adf4153.MOD_Value : %f \r\n",temp_adf4153.N_Value,(double)temp_adf4153.INT_Value,(double)temp_adf4153.MOD_Value);
  7325. #endif /* DEBUG_PRINT */
  7326. temp = temp_adf4153.N_Value - (double)temp_adf4153.INT_Value;
  7327. 80077ae: 4640 mov r0, r8
  7328. 80077b0: f7fc fe90 bl 80044d4 <__aeabi_ui2d>
  7329. 80077b4: 460b mov r3, r1
  7330. 80077b6: 4602 mov r2, r0
  7331. 80077b8: 4639 mov r1, r7
  7332. 80077ba: 4630 mov r0, r6
  7333. 80077bc: f7fc fd4c bl 8004258 <__aeabi_dsub>
  7334. #ifdef DEBUG_PRINT
  7335. printf("\r\n temp_adf4153.N_Value - (double)temp_adf4153.INT_Value) : %f temp * (double)temp_adf4153.MOD_Value : %f \r\n",temp,temp * (double)temp_adf4153.MOD_Value);
  7336. #endif /* DEBUG_PRINT */
  7337. temp_adf4153.FRAC_Value = (float)temp * temp_adf4153.MOD_Value;
  7338. 80077c0: f7fd f9f6 bl 8004bb0 <__aeabi_d2f>
  7339. temp_adf4153.MOD_Value = (temp_adf4153.PFD_Value / chspacing) * 1000;
  7340. 80077c4: 00e4 lsls r4, r4, #3
  7341. 80077c6: b2a4 uxth r4, r4
  7342. temp_adf4153.FRAC_Value = (float)temp * temp_adf4153.MOD_Value;
  7343. 80077c8: 4606 mov r6, r0
  7344. 80077ca: 4620 mov r0, r4
  7345. 80077cc: f7fd fafa bl 8004dc4 <__aeabi_i2f>
  7346. 80077d0: 4601 mov r1, r0
  7347. 80077d2: 4630 mov r0, r6
  7348. 80077d4: f7fd fb4a bl 8004e6c <__aeabi_fmul>
  7349. 80077d8: f7fd fc98 bl 800510c <__aeabi_f2uiz>
  7350. #ifdef DEBUG_PRINT
  7351. printf("\r\n");
  7352. printf("R0: %x R1: %x \r\n",N_Divider_Reg_Create(temp_adf4153.FRAC_Value,temp_adf4153.INT_Value,0),R_Divider_Reg_Create(temp_adf4153.MOD_Value,R_Counter,1,0,2,0));
  7353. #endif /* DEBUG_PRINT */
  7354. temp_reg.N_reg = N_Divider_Reg_Create(temp_adf4153.FRAC_Value,temp_adf4153.INT_Value,0);
  7355. 80077dc: 462a mov r2, r5
  7356. 80077de: 4641 mov r1, r8
  7357. 80077e0: b280 uxth r0, r0
  7358. 80077e2: f7ff ff43 bl 800766c <N_Divider_Reg_Create>
  7359. temp_reg.R_reg = R_Divider_Reg_Create(temp_adf4153.MOD_Value,R_Counter,1,0,2,0);
  7360. 80077e6: 2302 movs r3, #2
  7361. temp_reg.N_reg = N_Divider_Reg_Create(temp_adf4153.FRAC_Value,temp_adf4153.INT_Value,0);
  7362. 80077e8: 4606 mov r6, r0
  7363. temp_reg.R_reg = R_Divider_Reg_Create(temp_adf4153.MOD_Value,R_Counter,1,0,2,0);
  7364. 80077ea: 9300 str r3, [sp, #0]
  7365. 80077ec: 9501 str r5, [sp, #4]
  7366. 80077ee: 462b mov r3, r5
  7367. 80077f0: 2201 movs r2, #1
  7368. 80077f2: 4659 mov r1, fp
  7369. 80077f4: 4620 mov r0, r4
  7370. 80077f6: f7ff ff5c bl 80076b2 <R_Divider_Reg_Create>
  7371. return temp_reg;
  7372. 80077fa: e88a 0041 stmia.w sl, {r0, r6}
  7373. // R_Divider_Reg_Create(temp_adf4153.MOD_Value,R_Counter,1,0,1,0); //prescaler 1 : 8/9 0: 4/5
  7374. }
  7375. 80077fe: 4650 mov r0, sl
  7376. 8007800: b003 add sp, #12
  7377. 8007802: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
  7378. 8007806: bf00 nop
  7379. 8007808: 408f4000 .word 0x408f4000
  7380. 0800780c <ADF4153_Initialize>:
  7381. temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
  7382. ADF4153_Module_Ctrl(Pll_test2,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
  7383. // ADF4153_Module_Ctrl(Pll_test2,0x313840,0x14BE81,0x13C2,0x3);
  7384. HAL_Delay(1);
  7385. #endif // PYJ.2019.08.09_END --
  7386. if(Flash_Save_data[INDEX_PLL_3_5G_DL_H] == 0 && Flash_Save_data[INDEX_PLL_3_5G_DL_L] == 0){
  7387. 800780c: 4b09 ldr r3, [pc, #36] ; (8007834 <ADF4153_Initialize+0x28>)
  7388. 800780e: 7f5a ldrb r2, [r3, #29]
  7389. 8007810: b92a cbnz r2, 800781e <ADF4153_Initialize+0x12>
  7390. 8007812: 7f9a ldrb r2, [r3, #30]
  7391. 8007814: b91a cbnz r2, 800781e <ADF4153_Initialize+0x12>
  7392. Flash_Save_data[INDEX_PLL_3_5G_DL_H] = ((34655 & 0xFF00) >> 8);
  7393. 8007816: 2287 movs r2, #135 ; 0x87
  7394. 8007818: 775a strb r2, [r3, #29]
  7395. Flash_Save_data[INDEX_PLL_3_5G_DL_L] = (34655 & 0x00FF);
  7396. 800781a: 225f movs r2, #95 ; 0x5f
  7397. 800781c: 779a strb r2, [r3, #30]
  7398. }
  7399. if(Flash_Save_data[INDEX_PLL_3_5G_UL_H] == 0 && Flash_Save_data[INDEX_PLL_3_5G_UL_L] == 0){
  7400. 800781e: 7fda ldrb r2, [r3, #31]
  7401. 8007820: b93a cbnz r2, 8007832 <ADF4153_Initialize+0x26>
  7402. 8007822: f893 2020 ldrb.w r2, [r3, #32]
  7403. 8007826: b922 cbnz r2, 8007832 <ADF4153_Initialize+0x26>
  7404. Flash_Save_data[INDEX_PLL_3_5G_UL_H] = ((39345 & 0xFF00) >> 8);
  7405. 8007828: 2299 movs r2, #153 ; 0x99
  7406. 800782a: 77da strb r2, [r3, #31]
  7407. Flash_Save_data[INDEX_PLL_3_5G_UL_L] = (39345 & 0x00FF);
  7408. 800782c: 22b1 movs r2, #177 ; 0xb1
  7409. 800782e: f883 2020 strb.w r2, [r3, #32]
  7410. 8007832: 4770 bx lr
  7411. 8007834: 20000488 .word 0x20000488
  7412. 08007838 <ADF4153_Module_Ctrl>:
  7413. }
  7414. }
  7415. void ADF4153_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2,uint32_t R3){
  7416. 8007838: b084 sub sp, #16
  7417. 800783a: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
  7418. 800783e: b085 sub sp, #20
  7419. 8007840: ac0e add r4, sp, #56 ; 0x38
  7420. 8007842: e884 000f stmia.w r4, {r0, r1, r2, r3}
  7421. R3 = R3 & 0x0007FF;
  7422. 8007846: 9b17 ldr r3, [sp, #92] ; 0x5c
  7423. 8007848: f8bd 803c ldrh.w r8, [sp, #60] ; 0x3c
  7424. 800784c: f3c3 0a0a ubfx sl, r3, #0, #11
  7425. R2 = R2 & 0x00FFFF;
  7426. 8007850: f8bd 3058 ldrh.w r3, [sp, #88] ; 0x58
  7427. 8007854: 9c10 ldr r4, [sp, #64] ; 0x40
  7428. 8007856: 9301 str r3, [sp, #4]
  7429. R1 = R1 & 0xFFFFFF;
  7430. 8007858: 9b15 ldr r3, [sp, #84] ; 0x54
  7431. 800785a: f8bd 5044 ldrh.w r5, [sp, #68] ; 0x44
  7432. 800785e: f023 437f bic.w r3, r3, #4278190080 ; 0xff000000
  7433. 8007862: 9302 str r3, [sp, #8]
  7434. R0 = R0 & 0xFFFFFF;
  7435. 8007864: 9b14 ldr r3, [sp, #80] ; 0x50
  7436. 8007866: 9e12 ldr r6, [sp, #72] ; 0x48
  7437. 8007868: f023 437f bic.w r3, r3, #4278190080 ; 0xff000000
  7438. 800786c: f8bd 704c ldrh.w r7, [sp, #76] ; 0x4c
  7439. // ADF4153_Freq_Calc(3461500000,40000000,2,5000);
  7440. HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
  7441. 8007870: 2200 movs r2, #0
  7442. 8007872: 4641 mov r1, r8
  7443. R0 = R0 & 0xFFFFFF;
  7444. 8007874: 9303 str r3, [sp, #12]
  7445. 8007876: 4681 mov r9, r0
  7446. HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
  7447. 8007878: f7fe fd2c bl 80062d4 <HAL_GPIO_WritePin>
  7448. HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
  7449. 800787c: 2200 movs r2, #0
  7450. 800787e: 4629 mov r1, r5
  7451. 8007880: 4620 mov r0, r4
  7452. 8007882: f7fe fd27 bl 80062d4 <HAL_GPIO_WritePin>
  7453. HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
  7454. 8007886: 2200 movs r2, #0
  7455. 8007888: 4639 mov r1, r7
  7456. 800788a: 4630 mov r0, r6
  7457. 800788c: f7fe fd22 bl 80062d4 <HAL_GPIO_WritePin>
  7458. 8007890: f04f 0b0b mov.w fp, #11
  7459. printf("YJ :R0: %x R1: %x R2 : %x R3 : %x ",R0,R1,R2,R3);
  7460. printf("\r\n");
  7461. #endif /* DEBUG_PRINT */
  7462. /* R3 Ctrl */
  7463. for(int i =0; i < 11; i++){
  7464. if(R3 & 0x000400){
  7465. 8007894: f41a 6280 ands.w r2, sl, #1024 ; 0x400
  7466. HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_SET);
  7467. 8007898: bf18 it ne
  7468. 800789a: 2201 movne r2, #1
  7469. #ifdef DEBUG_PRINT
  7470. printf("1");
  7471. #endif /* DEBUG_PRINT */
  7472. }
  7473. else{
  7474. HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
  7475. 800789c: 4629 mov r1, r5
  7476. 800789e: 4620 mov r0, r4
  7477. 80078a0: f7fe fd18 bl 80062d4 <HAL_GPIO_WritePin>
  7478. #ifdef DEBUG_PRINT
  7479. printf("0");
  7480. #endif /* DEBUG_PRINT */
  7481. }
  7482. Pol_Delay_us(50);
  7483. 80078a4: 2032 movs r0, #50 ; 0x32
  7484. 80078a6: f000 fa5f bl 8007d68 <Pol_Delay_us>
  7485. HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
  7486. 80078aa: 2201 movs r2, #1
  7487. 80078ac: 4641 mov r1, r8
  7488. 80078ae: 4648 mov r0, r9
  7489. 80078b0: f7fe fd10 bl 80062d4 <HAL_GPIO_WritePin>
  7490. Pol_Delay_us(50);
  7491. 80078b4: 2032 movs r0, #50 ; 0x32
  7492. 80078b6: f000 fa57 bl 8007d68 <Pol_Delay_us>
  7493. HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
  7494. 80078ba: 2200 movs r2, #0
  7495. 80078bc: 4641 mov r1, r8
  7496. 80078be: 4648 mov r0, r9
  7497. 80078c0: f7fe fd08 bl 80062d4 <HAL_GPIO_WritePin>
  7498. for(int i =0; i < 11; i++){
  7499. 80078c4: f1bb 0b01 subs.w fp, fp, #1
  7500. R3 = (R3 << 1);
  7501. 80078c8: ea4f 0a4a mov.w sl, sl, lsl #1
  7502. for(int i =0; i < 11; i++){
  7503. 80078cc: d1e2 bne.n 8007894 <ADF4153_Module_Ctrl+0x5c>
  7504. }
  7505. #ifdef DEBUG_PRINT
  7506. printf("\r\n");
  7507. #endif /* DEBUG_PRINT */
  7508. HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
  7509. 80078ce: 2201 movs r2, #1
  7510. 80078d0: 4639 mov r1, r7
  7511. 80078d2: 4630 mov r0, r6
  7512. 80078d4: f7fe fcfe bl 80062d4 <HAL_GPIO_WritePin>
  7513. Pol_Delay_us(50);
  7514. 80078d8: 2032 movs r0, #50 ; 0x32
  7515. 80078da: f000 fa45 bl 8007d68 <Pol_Delay_us>
  7516. HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
  7517. 80078de: 465a mov r2, fp
  7518. 80078e0: 4639 mov r1, r7
  7519. 80078e2: 4630 mov r0, r6
  7520. 80078e4: f7fe fcf6 bl 80062d4 <HAL_GPIO_WritePin>
  7521. 80078e8: f04f 0a10 mov.w sl, #16
  7522. /* R2 Ctrl */
  7523. for(int i =0; i < 16; i++){
  7524. if(R2 & 0x008000){
  7525. 80078ec: 9b01 ldr r3, [sp, #4]
  7526. #ifdef DEBUG_PRINT
  7527. printf("1");
  7528. #endif /* DEBUG_PRINT */
  7529. }
  7530. else{
  7531. HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
  7532. 80078ee: 4629 mov r1, r5
  7533. if(R2 & 0x008000){
  7534. 80078f0: f413 4200 ands.w r2, r3, #32768 ; 0x8000
  7535. HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_SET);
  7536. 80078f4: bf18 it ne
  7537. 80078f6: 2201 movne r2, #1
  7538. HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
  7539. 80078f8: 4620 mov r0, r4
  7540. 80078fa: f7fe fceb bl 80062d4 <HAL_GPIO_WritePin>
  7541. #ifdef DEBUG_PRINT
  7542. printf("0");
  7543. #endif /* DEBUG_PRINT */
  7544. }
  7545. Pol_Delay_us(50);
  7546. 80078fe: 2032 movs r0, #50 ; 0x32
  7547. 8007900: f000 fa32 bl 8007d68 <Pol_Delay_us>
  7548. HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
  7549. 8007904: 2201 movs r2, #1
  7550. 8007906: 4641 mov r1, r8
  7551. 8007908: 4648 mov r0, r9
  7552. 800790a: f7fe fce3 bl 80062d4 <HAL_GPIO_WritePin>
  7553. Pol_Delay_us(50);
  7554. 800790e: 2032 movs r0, #50 ; 0x32
  7555. 8007910: f000 fa2a bl 8007d68 <Pol_Delay_us>
  7556. HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
  7557. 8007914: 2200 movs r2, #0
  7558. 8007916: 4641 mov r1, r8
  7559. 8007918: 4648 mov r0, r9
  7560. 800791a: f7fe fcdb bl 80062d4 <HAL_GPIO_WritePin>
  7561. R2 = ((R2 << 1) & 0x00FFFF);
  7562. 800791e: 9b01 ldr r3, [sp, #4]
  7563. for(int i =0; i < 16; i++){
  7564. 8007920: f1ba 0a01 subs.w sl, sl, #1
  7565. R2 = ((R2 << 1) & 0x00FFFF);
  7566. 8007924: ea4f 0343 mov.w r3, r3, lsl #1
  7567. 8007928: b29b uxth r3, r3
  7568. 800792a: 9301 str r3, [sp, #4]
  7569. for(int i =0; i < 16; i++){
  7570. 800792c: d1de bne.n 80078ec <ADF4153_Module_Ctrl+0xb4>
  7571. }
  7572. #ifdef DEBUG_PRINT
  7573. printf("\r\n");
  7574. #endif /* DEBUG_PRINT */
  7575. HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
  7576. 800792e: 2201 movs r2, #1
  7577. 8007930: 4639 mov r1, r7
  7578. 8007932: 4630 mov r0, r6
  7579. 8007934: f7fe fcce bl 80062d4 <HAL_GPIO_WritePin>
  7580. Pol_Delay_us(50);
  7581. 8007938: 2032 movs r0, #50 ; 0x32
  7582. 800793a: f000 fa15 bl 8007d68 <Pol_Delay_us>
  7583. HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
  7584. 800793e: 4652 mov r2, sl
  7585. 8007940: 4639 mov r1, r7
  7586. 8007942: 4630 mov r0, r6
  7587. 8007944: f7fe fcc6 bl 80062d4 <HAL_GPIO_WritePin>
  7588. 8007948: f04f 0a18 mov.w sl, #24
  7589. /* R1 Ctrl */
  7590. for(int i =0; i < 24; i++){
  7591. if(R1 & 0x800000){
  7592. 800794c: 9b02 ldr r3, [sp, #8]
  7593. #ifdef DEBUG_PRINT
  7594. printf("1");
  7595. #endif /* DEBUG_PRINT */
  7596. }
  7597. else{
  7598. HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
  7599. 800794e: 4629 mov r1, r5
  7600. if(R1 & 0x800000){
  7601. 8007950: f413 0200 ands.w r2, r3, #8388608 ; 0x800000
  7602. HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_SET);
  7603. 8007954: bf18 it ne
  7604. 8007956: 2201 movne r2, #1
  7605. HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
  7606. 8007958: 4620 mov r0, r4
  7607. 800795a: f7fe fcbb bl 80062d4 <HAL_GPIO_WritePin>
  7608. #ifdef DEBUG_PRINT
  7609. printf("0");
  7610. #endif /* DEBUG_PRINT */
  7611. }
  7612. Pol_Delay_us(50);
  7613. 800795e: 2032 movs r0, #50 ; 0x32
  7614. 8007960: f000 fa02 bl 8007d68 <Pol_Delay_us>
  7615. HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
  7616. 8007964: 2201 movs r2, #1
  7617. 8007966: 4641 mov r1, r8
  7618. 8007968: 4648 mov r0, r9
  7619. 800796a: f7fe fcb3 bl 80062d4 <HAL_GPIO_WritePin>
  7620. Pol_Delay_us(50);
  7621. 800796e: 2032 movs r0, #50 ; 0x32
  7622. 8007970: f000 f9fa bl 8007d68 <Pol_Delay_us>
  7623. HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
  7624. 8007974: 2200 movs r2, #0
  7625. 8007976: 4641 mov r1, r8
  7626. 8007978: 4648 mov r0, r9
  7627. 800797a: f7fe fcab bl 80062d4 <HAL_GPIO_WritePin>
  7628. R1 = ((R1 << 1) & 0xFFFFFF);
  7629. 800797e: 9b02 ldr r3, [sp, #8]
  7630. for(int i =0; i < 24; i++){
  7631. 8007980: f1ba 0a01 subs.w sl, sl, #1
  7632. R1 = ((R1 << 1) & 0xFFFFFF);
  7633. 8007984: ea4f 0343 mov.w r3, r3, lsl #1
  7634. 8007988: f023 437f bic.w r3, r3, #4278190080 ; 0xff000000
  7635. 800798c: 9302 str r3, [sp, #8]
  7636. for(int i =0; i < 24; i++){
  7637. 800798e: d1dd bne.n 800794c <ADF4153_Module_Ctrl+0x114>
  7638. }
  7639. #ifdef DEBUG_PRINT
  7640. printf("\r\n");
  7641. #endif /* DEBUG_PRINT */
  7642. HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
  7643. 8007990: 2201 movs r2, #1
  7644. 8007992: 4639 mov r1, r7
  7645. 8007994: 4630 mov r0, r6
  7646. 8007996: f7fe fc9d bl 80062d4 <HAL_GPIO_WritePin>
  7647. Pol_Delay_us(50);
  7648. 800799a: 2032 movs r0, #50 ; 0x32
  7649. 800799c: f000 f9e4 bl 8007d68 <Pol_Delay_us>
  7650. HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
  7651. 80079a0: 4652 mov r2, sl
  7652. 80079a2: 4639 mov r1, r7
  7653. 80079a4: 4630 mov r0, r6
  7654. 80079a6: f7fe fc95 bl 80062d4 <HAL_GPIO_WritePin>
  7655. 80079aa: f04f 0a18 mov.w sl, #24
  7656. /* R0 Ctrl */
  7657. for(int i =0; i < 24; i++){
  7658. if(R0 & 0x800000){
  7659. 80079ae: 9b03 ldr r3, [sp, #12]
  7660. #ifdef DEBUG_PRINT
  7661. printf("1");
  7662. #endif /* DEBUG_PRINT */
  7663. }
  7664. else{
  7665. HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
  7666. 80079b0: 4629 mov r1, r5
  7667. if(R0 & 0x800000){
  7668. 80079b2: f413 0200 ands.w r2, r3, #8388608 ; 0x800000
  7669. HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_SET);
  7670. 80079b6: bf18 it ne
  7671. 80079b8: 2201 movne r2, #1
  7672. HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
  7673. 80079ba: 4620 mov r0, r4
  7674. 80079bc: f7fe fc8a bl 80062d4 <HAL_GPIO_WritePin>
  7675. #ifdef DEBUG_PRINT
  7676. printf("0");
  7677. #endif /* DEBUG_PRINT */
  7678. }
  7679. Pol_Delay_us(50);
  7680. 80079c0: 2032 movs r0, #50 ; 0x32
  7681. 80079c2: f000 f9d1 bl 8007d68 <Pol_Delay_us>
  7682. HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
  7683. 80079c6: 2201 movs r2, #1
  7684. 80079c8: 4641 mov r1, r8
  7685. 80079ca: 4648 mov r0, r9
  7686. 80079cc: f7fe fc82 bl 80062d4 <HAL_GPIO_WritePin>
  7687. Pol_Delay_us(50);
  7688. 80079d0: 2032 movs r0, #50 ; 0x32
  7689. 80079d2: f000 f9c9 bl 8007d68 <Pol_Delay_us>
  7690. HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
  7691. 80079d6: 2200 movs r2, #0
  7692. 80079d8: 4641 mov r1, r8
  7693. 80079da: 4648 mov r0, r9
  7694. 80079dc: f7fe fc7a bl 80062d4 <HAL_GPIO_WritePin>
  7695. R0 = ((R0 << 1) & 0xFFFFFF);
  7696. 80079e0: 9b03 ldr r3, [sp, #12]
  7697. for(int i =0; i < 24; i++){
  7698. 80079e2: f1ba 0a01 subs.w sl, sl, #1
  7699. R0 = ((R0 << 1) & 0xFFFFFF);
  7700. 80079e6: ea4f 0343 mov.w r3, r3, lsl #1
  7701. 80079ea: f023 437f bic.w r3, r3, #4278190080 ; 0xff000000
  7702. 80079ee: 9303 str r3, [sp, #12]
  7703. for(int i =0; i < 24; i++){
  7704. 80079f0: d1dd bne.n 80079ae <ADF4153_Module_Ctrl+0x176>
  7705. }
  7706. #ifdef DEBUG_PRINT
  7707. printf("\r\n");
  7708. #endif /* DEBUG_PRINT */
  7709. HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
  7710. 80079f2: 4652 mov r2, sl
  7711. 80079f4: 4629 mov r1, r5
  7712. 80079f6: 4620 mov r0, r4
  7713. 80079f8: f7fe fc6c bl 80062d4 <HAL_GPIO_WritePin>
  7714. HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
  7715. 80079fc: 4639 mov r1, r7
  7716. 80079fe: 2201 movs r2, #1
  7717. 8007a00: 4630 mov r0, r6
  7718. 8007a02: f7fe fc67 bl 80062d4 <HAL_GPIO_WritePin>
  7719. Pol_Delay_us(50);
  7720. 8007a06: 2032 movs r0, #50 ; 0x32
  7721. 8007a08: f000 f9ae bl 8007d68 <Pol_Delay_us>
  7722. HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
  7723. 8007a0c: 4652 mov r2, sl
  7724. 8007a0e: 4639 mov r1, r7
  7725. 8007a10: 4630 mov r0, r6
  7726. }
  7727. 8007a12: b005 add sp, #20
  7728. 8007a14: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
  7729. 8007a18: b004 add sp, #16
  7730. HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
  7731. 8007a1a: f7fe bc5b b.w 80062d4 <HAL_GPIO_WritePin>
  7732. ...
  7733. 08007a20 <FLASH_Byte_Write>:
  7734. #define USER_DATA2 (FLASH_USER_START_ADDR + 4)
  7735. #define USER_DATA3 (FLASH_USER_START_ADDR + 8)
  7736. #define USER_DATA4 (FLASH_USER_START_ADDR + 12)
  7737. void FLASH_Byte_Write(uint8_t* data){
  7738. 8007a20: b538 push {r3, r4, r5, lr}
  7739. /*
  7740. 페이지 단위로 지울수 있도록 구조체변수를 선언해 주고 멤버변수값들을 정해줍니다.
  7741. 데이터를 새로 쓰기위해서는 먼저 페이지 단위로 메모리를 지워 줘야 합니다.
  7742. */
  7743. static FLASH_EraseInitTypeDef EraseInitStruct;
  7744. EraseInitStruct.TypeErase = FLASH_TYPEERASE_PAGES; //0x00
  7745. 8007a22: 2300 movs r3, #0
  7746. 8007a24: 4c1a ldr r4, [pc, #104] ; (8007a90 <FLASH_Byte_Write+0x70>)
  7747. EraseInitStruct.PageAddress = FLASH_USER_START_ADDR; // 지우기 페이지의 시작 어드레스
  7748. EraseInitStruct.NbPages = (FLASH_USER_END_ADDR - FLASH_USER_START_ADDR) / FLASH_PAGE_SIZE; //지울 페이지 수
  7749. static uint32_t PAGEError = 0;
  7750. // printf("Flash Write Start \r\n");
  7751. data[INDEX_BLUE_HEADER] = 0xbe;
  7752. 8007a26: 22be movs r2, #190 ; 0xbe
  7753. EraseInitStruct.TypeErase = FLASH_TYPEERASE_PAGES; //0x00
  7754. 8007a28: 6023 str r3, [r4, #0]
  7755. EraseInitStruct.PageAddress = FLASH_USER_START_ADDR; // 지우기 페이지의 시작 어드레스
  7756. 8007a2a: 4b1a ldr r3, [pc, #104] ; (8007a94 <FLASH_Byte_Write+0x74>)
  7757. void FLASH_Byte_Write(uint8_t* data){
  7758. 8007a2c: 4605 mov r5, r0
  7759. EraseInitStruct.PageAddress = FLASH_USER_START_ADDR; // 지우기 페이지의 시작 어드레스
  7760. 8007a2e: 60a3 str r3, [r4, #8]
  7761. EraseInitStruct.NbPages = (FLASH_USER_END_ADDR - FLASH_USER_START_ADDR) / FLASH_PAGE_SIZE; //지울 페이지 수
  7762. 8007a30: 2301 movs r3, #1
  7763. 8007a32: 60e3 str r3, [r4, #12]
  7764. data[INDEX_BLUE_TYPE] = 1;
  7765. 8007a34: 7043 strb r3, [r0, #1]
  7766. data[INDEX_BLUE_LENGTH] = INDEX_BLUE_EOF - 2;
  7767. 8007a36: 235d movs r3, #93 ; 0x5d
  7768. 8007a38: 7083 strb r3, [r0, #2]
  7769. data[INDEX_BLUE_CRCINDEX] = INDEX_BLUE_EOF - 1;
  7770. 8007a3a: 235e movs r3, #94 ; 0x5e
  7771. data[INDEX_BLUE_HEADER] = 0xbe;
  7772. 8007a3c: 7002 strb r2, [r0, #0]
  7773. data[INDEX_BLUE_CRCINDEX] = INDEX_BLUE_EOF - 1;
  7774. 8007a3e: 70c3 strb r3, [r0, #3]
  7775. /*
  7776. Flash메모리를 조작 할 수 있도록 락을 풀어 줍니다.
  7777. */
  7778. HAL_FLASH_Unlock();
  7779. 8007a40: f7fe fa58 bl 8005ef4 <HAL_FLASH_Unlock>
  7780. /*
  7781. 앞에서 설정한 페이지를 지워 줍니다. 페이지 지우기에 실패하면 무한루프에 빠지게 하여 기기의 오작동을 예방합니다.
  7782. */
  7783. if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK) {
  7784. 8007a44: 4914 ldr r1, [pc, #80] ; (8007a98 <FLASH_Byte_Write+0x78>)
  7785. 8007a46: 4620 mov r0, r4
  7786. 8007a48: f7fe fb04 bl 8006054 <HAL_FLASHEx_Erase>
  7787. 8007a4c: b118 cbz r0, 8007a56 <FLASH_Byte_Write+0x36>
  7788. printf("Eraser Error\r\n");
  7789. 8007a4e: 4813 ldr r0, [pc, #76] ; (8007a9c <FLASH_Byte_Write+0x7c>)
  7790. 8007a50: f002 f964 bl 8009d1c <puts>
  7791. 8007a54: e7fe b.n 8007a54 <FLASH_Byte_Write+0x34>
  7792. 8007a56: 4604 mov r4, r0
  7793. */
  7794. /////////유저가 설정한 페이지에 데이터 쓰기 ////////////////////////////////////////////////////
  7795. //HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
  7796. for(int i = 0; i < INDEX_BLUE_EOF + 1; i += 2){
  7797. WriteData = ((data[i]) & 0x00FF);
  7798. WriteData += ((data[i + 1] << 8) & 0xFF00);
  7799. 8007a58: 192b adds r3, r5, r4
  7800. 8007a5a: 785b ldrb r3, [r3, #1]
  7801. WriteData = ((data[i]) & 0x00FF);
  7802. 8007a5c: 5d2a ldrb r2, [r5, r4]
  7803. if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_HALFWORD, FLASH_USER_START_ADDR + i, ((uint16_t)WriteData)) != HAL_OK){
  7804. 8007a5e: f104 6100 add.w r1, r4, #134217728 ; 0x8000000
  7805. WriteData += ((data[i + 1] << 8) & 0xFF00);
  7806. 8007a62: eb02 2203 add.w r2, r2, r3, lsl #8
  7807. if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_HALFWORD, FLASH_USER_START_ADDR + i, ((uint16_t)WriteData)) != HAL_OK){
  7808. 8007a66: b292 uxth r2, r2
  7809. 8007a68: 2300 movs r3, #0
  7810. 8007a6a: f501 21ff add.w r1, r1, #522240 ; 0x7f800
  7811. 8007a6e: 2001 movs r0, #1
  7812. 8007a70: f7fe fa86 bl 8005f80 <HAL_FLASH_Program>
  7813. 8007a74: b120 cbz r0, 8007a80 <FLASH_Byte_Write+0x60>
  7814. printf("Write Error %d\r\n",__LINE__);
  7815. 8007a76: 21a4 movs r1, #164 ; 0xa4
  7816. 8007a78: 4809 ldr r0, [pc, #36] ; (8007aa0 <FLASH_Byte_Write+0x80>)
  7817. 8007a7a: f002 f8db bl 8009c34 <iprintf>
  7818. 8007a7e: e7fe b.n 8007a7e <FLASH_Byte_Write+0x5e>
  7819. for(int i = 0; i < INDEX_BLUE_EOF + 1; i += 2){
  7820. 8007a80: 3402 adds r4, #2
  7821. 8007a82: 2c60 cmp r4, #96 ; 0x60
  7822. 8007a84: d1e8 bne.n 8007a58 <FLASH_Byte_Write+0x38>
  7823. printf("Addr = %x, Data = %x\r\n", FLASH_USER_START_ADDR + i, *(__IO uint16_t *)(FLASH_USER_START_ADDR + i));
  7824. }
  7825. #endif // PYJ.2019.07.31_END --
  7826. ///////////////////////////////////////////////////////////////////////////////////////////////////
  7827. }
  7828. 8007a86: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
  7829. HAL_FLASH_Lock();
  7830. 8007a8a: f7fe ba45 b.w 8005f18 <HAL_FLASH_Lock>
  7831. 8007a8e: bf00 nop
  7832. 8007a90: 20000424 .word 0x20000424
  7833. 8007a94: 0807f800 .word 0x0807f800
  7834. 8007a98: 20000434 .word 0x20000434
  7835. 8007a9c: 0800bc68 .word 0x0800bc68
  7836. 8007aa0: 0800bc76 .word 0x0800bc76
  7837. 08007aa4 <Bluecell_Flash_Write>:
  7838. uint8_t Bluecell_Flash_Write(uint8_t* data){
  7839. 8007aa4: b508 push {r3, lr}
  7840. /*Variable used for Erase procedure*/
  7841. // flashtest();
  7842. FLASH_Byte_Write(&data[INDEX_BLUE_HEADER]);
  7843. 8007aa6: f7ff ffbb bl 8007a20 <FLASH_Byte_Write>
  7844. }
  7845. 8007aaa: bd08 pop {r3, pc}
  7846. 08007aac <Bluecell_Flash_Read>:
  7847. bool Bluecell_Flash_Read(uint8_t* data){
  7848. for(int i = 0; i < INDEX_BLUE_EOF + 1; i += 2){
  7849. 8007aac: 2300 movs r3, #0
  7850. 8007aae: f103 6200 add.w r2, r3, #134217728 ; 0x8000000
  7851. 8007ab2: f502 22ff add.w r2, r2, #522240 ; 0x7f800
  7852. // printf("Addr = %x, Data = %x\r\n", FLASH_USER_START_ADDR + i, *(__IO uint16_t *)(FLASH_USER_START_ADDR + i));
  7853. data[INDEX_BLUE_HEADER + i] = *(__IO uint16_t *)(FLASH_USER_START_ADDR + i) &0x00FF;
  7854. 8007ab6: 8811 ldrh r1, [r2, #0]
  7855. 8007ab8: 54c1 strb r1, [r0, r3]
  7856. data[INDEX_BLUE_HEADER + i + 1] = (*(__IO uint16_t *)(FLASH_USER_START_ADDR + i) & 0xFF00) >> 8;
  7857. 8007aba: 8812 ldrh r2, [r2, #0]
  7858. 8007abc: 18c1 adds r1, r0, r3
  7859. for(int i = 0; i < INDEX_BLUE_EOF + 1; i += 2){
  7860. 8007abe: 3302 adds r3, #2
  7861. data[INDEX_BLUE_HEADER + i + 1] = (*(__IO uint16_t *)(FLASH_USER_START_ADDR + i) & 0xFF00) >> 8;
  7862. 8007ac0: f3c2 2207 ubfx r2, r2, #8, #8
  7863. for(int i = 0; i < INDEX_BLUE_EOF + 1; i += 2){
  7864. 8007ac4: 2b60 cmp r3, #96 ; 0x60
  7865. data[INDEX_BLUE_HEADER + i + 1] = (*(__IO uint16_t *)(FLASH_USER_START_ADDR + i) & 0xFF00) >> 8;
  7866. 8007ac6: 704a strb r2, [r1, #1]
  7867. for(int i = 0; i < INDEX_BLUE_EOF + 1; i += 2){
  7868. 8007ac8: d1f1 bne.n 8007aae <Bluecell_Flash_Read+0x2>
  7869. #if 0 // PYJ.2019.07.31_BEGIN --
  7870. for(int i = 0; i < INDEX_BLUE_EOF + 1; i++){
  7871. printf("Data = %x\r\n", data[i]);
  7872. }
  7873. #endif // PYJ.2019.07.31_END --
  7874. }
  7875. 8007aca: 4770 bx lr
  7876. 08007acc <Path_Init>:
  7877. {
  7878. #ifdef DEBUG_PRINT
  7879. printf("%s", Bluecell_Prot_IndexStr[k]);
  7880. #endif /* DEBUG_PRINT */
  7881. }
  7882. void Path_Init(void){
  7883. 8007acc: b570 push {r4, r5, r6, lr}
  7884. Prev_data[INDEX_PATH_EN_1_8G_DL] = HAL_GPIO_ReadPin(PATH_EN_1_8G_DL_GPIO_Port,PATH_EN_1_8G_DL_Pin);
  7885. 8007ace: 4d24 ldr r5, [pc, #144] ; (8007b60 <Path_Init+0x94>)
  7886. 8007ad0: f44f 4180 mov.w r1, #16384 ; 0x4000
  7887. 8007ad4: 4628 mov r0, r5
  7888. 8007ad6: f7fe fbf7 bl 80062c8 <HAL_GPIO_ReadPin>
  7889. 8007ada: 4c22 ldr r4, [pc, #136] ; (8007b64 <Path_Init+0x98>)
  7890. Prev_data[INDEX_PATH_EN_1_8G_UL] = HAL_GPIO_ReadPin(PATH_EN_1_8G_UL_GPIO_Port,PATH_EN_1_8G_UL_Pin);
  7891. 8007adc: f44f 4100 mov.w r1, #32768 ; 0x8000
  7892. Prev_data[INDEX_PATH_EN_1_8G_DL] = HAL_GPIO_ReadPin(PATH_EN_1_8G_DL_GPIO_Port,PATH_EN_1_8G_DL_Pin);
  7893. 8007ae0: f884 0040 strb.w r0, [r4, #64] ; 0x40
  7894. Prev_data[INDEX_PATH_EN_1_8G_UL] = HAL_GPIO_ReadPin(PATH_EN_1_8G_UL_GPIO_Port,PATH_EN_1_8G_UL_Pin);
  7895. 8007ae4: 4628 mov r0, r5
  7896. 8007ae6: f7fe fbef bl 80062c8 <HAL_GPIO_ReadPin>
  7897. Prev_data[INDEX_PATH_EN_2_1G_DL] = HAL_GPIO_ReadPin(PATH_EN_2_1G_DL_GPIO_Port,PATH_EN_2_1G_DL_Pin);
  7898. 8007aea: 4e1f ldr r6, [pc, #124] ; (8007b68 <Path_Init+0x9c>)
  7899. Prev_data[INDEX_PATH_EN_1_8G_UL] = HAL_GPIO_ReadPin(PATH_EN_1_8G_UL_GPIO_Port,PATH_EN_1_8G_UL_Pin);
  7900. 8007aec: f884 0041 strb.w r0, [r4, #65] ; 0x41
  7901. Prev_data[INDEX_PATH_EN_2_1G_DL] = HAL_GPIO_ReadPin(PATH_EN_2_1G_DL_GPIO_Port,PATH_EN_2_1G_DL_Pin);
  7902. 8007af0: 2101 movs r1, #1
  7903. 8007af2: 4630 mov r0, r6
  7904. 8007af4: f7fe fbe8 bl 80062c8 <HAL_GPIO_ReadPin>
  7905. Prev_data[INDEX_PATH_EN_2_1G_UL] = HAL_GPIO_ReadPin(PATH_EN_2_1G_UL_GPIO_Port,PATH_EN_2_1G_UL_Pin);
  7906. 8007af8: 2102 movs r1, #2
  7907. Prev_data[INDEX_PATH_EN_2_1G_DL] = HAL_GPIO_ReadPin(PATH_EN_2_1G_DL_GPIO_Port,PATH_EN_2_1G_DL_Pin);
  7908. 8007afa: f884 0042 strb.w r0, [r4, #66] ; 0x42
  7909. Prev_data[INDEX_PATH_EN_2_1G_UL] = HAL_GPIO_ReadPin(PATH_EN_2_1G_UL_GPIO_Port,PATH_EN_2_1G_UL_Pin);
  7910. 8007afe: 4630 mov r0, r6
  7911. 8007b00: f7fe fbe2 bl 80062c8 <HAL_GPIO_ReadPin>
  7912. Prev_data[INDEX_PATH_EN_3_5G_L] = HAL_GPIO_ReadPin(PATH_EN_3_5G_L_GPIO_Port,PATH_EN_3_5G_L_Pin);
  7913. 8007b04: 2180 movs r1, #128 ; 0x80
  7914. Prev_data[INDEX_PATH_EN_2_1G_UL] = HAL_GPIO_ReadPin(PATH_EN_2_1G_UL_GPIO_Port,PATH_EN_2_1G_UL_Pin);
  7915. 8007b06: f884 0043 strb.w r0, [r4, #67] ; 0x43
  7916. Prev_data[INDEX_PATH_EN_3_5G_L] = HAL_GPIO_ReadPin(PATH_EN_3_5G_L_GPIO_Port,PATH_EN_3_5G_L_Pin);
  7917. 8007b0a: 4818 ldr r0, [pc, #96] ; (8007b6c <Path_Init+0xa0>)
  7918. 8007b0c: f7fe fbdc bl 80062c8 <HAL_GPIO_ReadPin>
  7919. Prev_data[INDEX_PATH_EN_3_5G_H] = HAL_GPIO_ReadPin(PATH_EN_3_5G_H_GPIO_Port,PATH_EN_3_5G_H_Pin);
  7920. 8007b10: f506 6600 add.w r6, r6, #2048 ; 0x800
  7921. Prev_data[INDEX_PATH_EN_3_5G_L] = HAL_GPIO_ReadPin(PATH_EN_3_5G_L_GPIO_Port,PATH_EN_3_5G_L_Pin);
  7922. 8007b14: f884 0047 strb.w r0, [r4, #71] ; 0x47
  7923. Prev_data[INDEX_PATH_EN_3_5G_H] = HAL_GPIO_ReadPin(PATH_EN_3_5G_H_GPIO_Port,PATH_EN_3_5G_H_Pin);
  7924. 8007b18: f44f 7100 mov.w r1, #512 ; 0x200
  7925. 8007b1c: 4630 mov r0, r6
  7926. 8007b1e: f7fe fbd3 bl 80062c8 <HAL_GPIO_ReadPin>
  7927. Prev_data[INDEX_PATH_EN_3_5G_DL] = HAL_GPIO_ReadPin(PATH_EN_3_5G_DL_GPIO_Port,PATH_EN_3_5G_DL_Pin);
  7928. 8007b22: f44f 6180 mov.w r1, #1024 ; 0x400
  7929. Prev_data[INDEX_PATH_EN_3_5G_H] = HAL_GPIO_ReadPin(PATH_EN_3_5G_H_GPIO_Port,PATH_EN_3_5G_H_Pin);
  7930. 8007b26: f884 0046 strb.w r0, [r4, #70] ; 0x46
  7931. Prev_data[INDEX_PATH_EN_3_5G_DL] = HAL_GPIO_ReadPin(PATH_EN_3_5G_DL_GPIO_Port,PATH_EN_3_5G_DL_Pin);
  7932. 8007b2a: 4630 mov r0, r6
  7933. 8007b2c: f7fe fbcc bl 80062c8 <HAL_GPIO_ReadPin>
  7934. Prev_data[INDEX_PATH_EN_3_5G_UL] = HAL_GPIO_ReadPin(PATH_EN_3_5G_UL_GPIO_Port,PATH_EN_3_5G_UL_Pin);
  7935. 8007b30: f44f 6100 mov.w r1, #2048 ; 0x800
  7936. Prev_data[INDEX_PATH_EN_3_5G_DL] = HAL_GPIO_ReadPin(PATH_EN_3_5G_DL_GPIO_Port,PATH_EN_3_5G_DL_Pin);
  7937. 8007b34: f884 0044 strb.w r0, [r4, #68] ; 0x44
  7938. Prev_data[INDEX_PATH_EN_3_5G_UL] = HAL_GPIO_ReadPin(PATH_EN_3_5G_UL_GPIO_Port,PATH_EN_3_5G_UL_Pin);
  7939. 8007b38: 4630 mov r0, r6
  7940. 8007b3a: f7fe fbc5 bl 80062c8 <HAL_GPIO_ReadPin>
  7941. Prev_data[INDEX_PLL_ON_OFF_3_5G_H] = HAL_GPIO_ReadPin(PLL_ON_OFF_3_5G_H_GPIO_Port,PLL_ON_OFF_3_5G_H_Pin);
  7942. 8007b3e: f44f 5180 mov.w r1, #4096 ; 0x1000
  7943. Prev_data[INDEX_PATH_EN_3_5G_UL] = HAL_GPIO_ReadPin(PATH_EN_3_5G_UL_GPIO_Port,PATH_EN_3_5G_UL_Pin);
  7944. 8007b42: f884 0045 strb.w r0, [r4, #69] ; 0x45
  7945. Prev_data[INDEX_PLL_ON_OFF_3_5G_H] = HAL_GPIO_ReadPin(PLL_ON_OFF_3_5G_H_GPIO_Port,PLL_ON_OFF_3_5G_H_Pin);
  7946. 8007b46: 4628 mov r0, r5
  7947. 8007b48: f7fe fbbe bl 80062c8 <HAL_GPIO_ReadPin>
  7948. Prev_data[INDEX_PLL_ON_OFF_3_5G_L] = HAL_GPIO_ReadPin(PLL_ON_OFF_3_5G_L_GPIO_Port,PLL_ON_OFF_3_5G_L_Pin);
  7949. 8007b4c: f44f 6180 mov.w r1, #1024 ; 0x400
  7950. Prev_data[INDEX_PLL_ON_OFF_3_5G_H] = HAL_GPIO_ReadPin(PLL_ON_OFF_3_5G_H_GPIO_Port,PLL_ON_OFF_3_5G_H_Pin);
  7951. 8007b50: f884 0048 strb.w r0, [r4, #72] ; 0x48
  7952. Prev_data[INDEX_PLL_ON_OFF_3_5G_L] = HAL_GPIO_ReadPin(PLL_ON_OFF_3_5G_L_GPIO_Port,PLL_ON_OFF_3_5G_L_Pin);
  7953. 8007b54: 4628 mov r0, r5
  7954. 8007b56: f7fe fbb7 bl 80062c8 <HAL_GPIO_ReadPin>
  7955. 8007b5a: f884 0049 strb.w r0, [r4, #73] ; 0x49
  7956. 8007b5e: bd70 pop {r4, r5, r6, pc}
  7957. 8007b60: 40011000 .word 0x40011000
  7958. 8007b64: 20000574 .word 0x20000574
  7959. 8007b68: 40011800 .word 0x40011800
  7960. 8007b6c: 40011400 .word 0x40011400
  7961. 08007b70 <Power_ON_OFF_Ctrl>:
  7962. }
  7963. void Power_ON_OFF_Ctrl(uint8_t type,uint8_t cmd){
  7964. // printf("\r\ntype : %s cmd : %d\r\n",Bluecell_Prot_IndexStr[type - 4],cmd);
  7965. switch(type){
  7966. 8007b70: 3840 subs r0, #64 ; 0x40
  7967. void Power_ON_OFF_Ctrl(uint8_t type,uint8_t cmd){
  7968. 8007b72: b510 push {r4, lr}
  7969. 8007b74: 460c mov r4, r1
  7970. switch(type){
  7971. 8007b76: 280d cmp r0, #13
  7972. 8007b78: d877 bhi.n 8007c6a <Power_ON_OFF_Ctrl+0xfa>
  7973. 8007b7a: e8df f000 tbb [pc, r0]
  7974. 8007b7e: 1207 .short 0x1207
  7975. 8007b80: 3c352019 .word 0x3c352019
  7976. 8007b84: 4a43262d .word 0x4a43262d
  7977. 8007b88: 51515151 .word 0x51515151
  7978. case INDEX_PATH_EN_1_8G_DL :
  7979. #if 0 // PYJ.2019.07.29_BEGIN --
  7980. printf("\r\n LINE %d\r\n",__LINE__);
  7981. #endif // PYJ.2019.07.29_END --
  7982. if(cmd)
  7983. 8007b8c: b139 cbz r1, 8007b9e <Power_ON_OFF_Ctrl+0x2e>
  7984. HAL_GPIO_WritePin(PATH_EN_1_8G_DL_GPIO_Port,PATH_EN_1_8G_DL_Pin, GPIO_PIN_SET);
  7985. 8007b8e: 2201 movs r2, #1
  7986. else
  7987. HAL_GPIO_WritePin(PATH_EN_1_8G_DL_GPIO_Port,PATH_EN_1_8G_DL_Pin, GPIO_PIN_RESET);
  7988. 8007b90: f44f 4180 mov.w r1, #16384 ; 0x4000
  7989. 8007b94: 4835 ldr r0, [pc, #212] ; (8007c6c <Power_ON_OFF_Ctrl+0xfc>)
  7990. printf("Function : %s LINE : %d ERROR \r\n",__func__,__LINE__);
  7991. #endif /* DEBUG_PRINT */
  7992. break;
  7993. }
  7994. }
  7995. 8007b96: e8bd 4010 ldmia.w sp!, {r4, lr}
  7996. HAL_GPIO_WritePin(T_SYNC_DL_GPIO_Port,T_SYNC_DL_Pin, GPIO_PIN_RESET);
  7997. 8007b9a: f7fe bb9b b.w 80062d4 <HAL_GPIO_WritePin>
  7998. HAL_GPIO_WritePin(PATH_EN_1_8G_DL_GPIO_Port,PATH_EN_1_8G_DL_Pin, GPIO_PIN_RESET);
  7999. 8007b9e: 460a mov r2, r1
  8000. 8007ba0: e7f6 b.n 8007b90 <Power_ON_OFF_Ctrl+0x20>
  8001. if(cmd)
  8002. 8007ba2: b119 cbz r1, 8007bac <Power_ON_OFF_Ctrl+0x3c>
  8003. HAL_GPIO_WritePin(PATH_EN_1_8G_UL_GPIO_Port,PATH_EN_1_8G_UL_Pin, GPIO_PIN_SET);
  8004. 8007ba4: 2201 movs r2, #1
  8005. HAL_GPIO_WritePin(PATH_EN_1_8G_UL_GPIO_Port,PATH_EN_1_8G_UL_Pin, GPIO_PIN_RESET);
  8006. 8007ba6: f44f 4100 mov.w r1, #32768 ; 0x8000
  8007. 8007baa: e7f3 b.n 8007b94 <Power_ON_OFF_Ctrl+0x24>
  8008. 8007bac: 460a mov r2, r1
  8009. 8007bae: e7fa b.n 8007ba6 <Power_ON_OFF_Ctrl+0x36>
  8010. if(cmd)
  8011. 8007bb0: b119 cbz r1, 8007bba <Power_ON_OFF_Ctrl+0x4a>
  8012. HAL_GPIO_WritePin(PATH_EN_2_1G_DL_GPIO_Port,PATH_EN_2_1G_DL_Pin, GPIO_PIN_SET);
  8013. 8007bb2: 2201 movs r2, #1
  8014. HAL_GPIO_WritePin(PATH_EN_2_1G_DL_GPIO_Port,PATH_EN_2_1G_DL_Pin, GPIO_PIN_RESET);
  8015. 8007bb4: 2101 movs r1, #1
  8016. HAL_GPIO_WritePin(PATH_EN_2_1G_UL_GPIO_Port,PATH_EN_2_1G_UL_Pin, GPIO_PIN_RESET);
  8017. 8007bb6: 482e ldr r0, [pc, #184] ; (8007c70 <Power_ON_OFF_Ctrl+0x100>)
  8018. 8007bb8: e7ed b.n 8007b96 <Power_ON_OFF_Ctrl+0x26>
  8019. HAL_GPIO_WritePin(PATH_EN_2_1G_DL_GPIO_Port,PATH_EN_2_1G_DL_Pin, GPIO_PIN_RESET);
  8020. 8007bba: 460a mov r2, r1
  8021. 8007bbc: e7fa b.n 8007bb4 <Power_ON_OFF_Ctrl+0x44>
  8022. if(cmd)
  8023. 8007bbe: b111 cbz r1, 8007bc6 <Power_ON_OFF_Ctrl+0x56>
  8024. HAL_GPIO_WritePin(PATH_EN_2_1G_UL_GPIO_Port,PATH_EN_2_1G_UL_Pin, GPIO_PIN_SET);
  8025. 8007bc0: 2201 movs r2, #1
  8026. HAL_GPIO_WritePin(PATH_EN_2_1G_UL_GPIO_Port,PATH_EN_2_1G_UL_Pin, GPIO_PIN_RESET);
  8027. 8007bc2: 2102 movs r1, #2
  8028. 8007bc4: e7f7 b.n 8007bb6 <Power_ON_OFF_Ctrl+0x46>
  8029. 8007bc6: 460a mov r2, r1
  8030. 8007bc8: e7fb b.n 8007bc2 <Power_ON_OFF_Ctrl+0x52>
  8031. if(cmd){
  8032. 8007bca: b119 cbz r1, 8007bd4 <Power_ON_OFF_Ctrl+0x64>
  8033. HAL_GPIO_WritePin(PATH_EN_3_5G_L_GPIO_Port,PATH_EN_3_5G_L_Pin, GPIO_PIN_SET);
  8034. 8007bcc: 2201 movs r2, #1
  8035. HAL_GPIO_WritePin(PATH_EN_3_5G_L_GPIO_Port,PATH_EN_3_5G_L_Pin, GPIO_PIN_RESET);
  8036. 8007bce: 2180 movs r1, #128 ; 0x80
  8037. 8007bd0: 4828 ldr r0, [pc, #160] ; (8007c74 <Power_ON_OFF_Ctrl+0x104>)
  8038. 8007bd2: e7e0 b.n 8007b96 <Power_ON_OFF_Ctrl+0x26>
  8039. 8007bd4: 460a mov r2, r1
  8040. 8007bd6: e7fa b.n 8007bce <Power_ON_OFF_Ctrl+0x5e>
  8041. if(cmd){
  8042. 8007bd8: b121 cbz r1, 8007be4 <Power_ON_OFF_Ctrl+0x74>
  8043. HAL_GPIO_WritePin(PATH_EN_3_5G_H_GPIO_Port,PATH_EN_3_5G_H_Pin, GPIO_PIN_SET);
  8044. 8007bda: 2201 movs r2, #1
  8045. HAL_GPIO_WritePin(PATH_EN_3_5G_H_GPIO_Port,PATH_EN_3_5G_H_Pin, GPIO_PIN_RESET);
  8046. 8007bdc: f44f 7100 mov.w r1, #512 ; 0x200
  8047. HAL_GPIO_WritePin(T_SYNC_DL_GPIO_Port,T_SYNC_DL_Pin, GPIO_PIN_RESET);
  8048. 8007be0: 4825 ldr r0, [pc, #148] ; (8007c78 <Power_ON_OFF_Ctrl+0x108>)
  8049. 8007be2: e7d8 b.n 8007b96 <Power_ON_OFF_Ctrl+0x26>
  8050. HAL_GPIO_WritePin(PATH_EN_3_5G_H_GPIO_Port,PATH_EN_3_5G_H_Pin, GPIO_PIN_RESET);
  8051. 8007be4: 460a mov r2, r1
  8052. 8007be6: e7f9 b.n 8007bdc <Power_ON_OFF_Ctrl+0x6c>
  8053. if(cmd)
  8054. 8007be8: b119 cbz r1, 8007bf2 <Power_ON_OFF_Ctrl+0x82>
  8055. HAL_GPIO_WritePin(PATH_EN_3_5G_DL_GPIO_Port,PATH_EN_3_5G_DL_Pin, GPIO_PIN_SET);
  8056. 8007bea: 2201 movs r2, #1
  8057. HAL_GPIO_WritePin(PATH_EN_3_5G_DL_GPIO_Port,PATH_EN_3_5G_DL_Pin, GPIO_PIN_RESET);
  8058. 8007bec: f44f 6180 mov.w r1, #1024 ; 0x400
  8059. 8007bf0: e7f6 b.n 8007be0 <Power_ON_OFF_Ctrl+0x70>
  8060. 8007bf2: 460a mov r2, r1
  8061. 8007bf4: e7fa b.n 8007bec <Power_ON_OFF_Ctrl+0x7c>
  8062. if(cmd)
  8063. 8007bf6: b119 cbz r1, 8007c00 <Power_ON_OFF_Ctrl+0x90>
  8064. HAL_GPIO_WritePin(PATH_EN_3_5G_UL_GPIO_Port,PATH_EN_3_5G_UL_Pin, GPIO_PIN_SET);
  8065. 8007bf8: 2201 movs r2, #1
  8066. HAL_GPIO_WritePin(PATH_EN_3_5G_UL_GPIO_Port,PATH_EN_3_5G_UL_Pin, GPIO_PIN_RESET);
  8067. 8007bfa: f44f 6100 mov.w r1, #2048 ; 0x800
  8068. 8007bfe: e7ef b.n 8007be0 <Power_ON_OFF_Ctrl+0x70>
  8069. 8007c00: 460a mov r2, r1
  8070. 8007c02: e7fa b.n 8007bfa <Power_ON_OFF_Ctrl+0x8a>
  8071. if(cmd)
  8072. 8007c04: b119 cbz r1, 8007c0e <Power_ON_OFF_Ctrl+0x9e>
  8073. HAL_GPIO_WritePin(PLL_ON_OFF_3_5G_H_GPIO_Port,PLL_ON_OFF_3_5G_H_Pin, GPIO_PIN_SET);
  8074. 8007c06: 2201 movs r2, #1
  8075. HAL_GPIO_WritePin(PLL_ON_OFF_3_5G_H_GPIO_Port,PLL_ON_OFF_3_5G_H_Pin, GPIO_PIN_RESET);
  8076. 8007c08: f44f 5180 mov.w r1, #4096 ; 0x1000
  8077. 8007c0c: e7c2 b.n 8007b94 <Power_ON_OFF_Ctrl+0x24>
  8078. 8007c0e: 460a mov r2, r1
  8079. 8007c10: e7fa b.n 8007c08 <Power_ON_OFF_Ctrl+0x98>
  8080. if(cmd)
  8081. 8007c12: b119 cbz r1, 8007c1c <Power_ON_OFF_Ctrl+0xac>
  8082. HAL_GPIO_WritePin(PLL_ON_OFF_3_5G_L_GPIO_Port,PLL_ON_OFF_3_5G_L_Pin, GPIO_PIN_SET);
  8083. 8007c14: 2201 movs r2, #1
  8084. HAL_GPIO_WritePin(PLL_ON_OFF_3_5G_L_GPIO_Port,PLL_ON_OFF_3_5G_L_Pin, GPIO_PIN_RESET);
  8085. 8007c16: f44f 6180 mov.w r1, #1024 ; 0x400
  8086. 8007c1a: e7bb b.n 8007b94 <Power_ON_OFF_Ctrl+0x24>
  8087. 8007c1c: 460a mov r2, r1
  8088. 8007c1e: e7fa b.n 8007c16 <Power_ON_OFF_Ctrl+0xa6>
  8089. if(cmd){
  8090. 8007c20: b191 cbz r1, 8007c48 <Power_ON_OFF_Ctrl+0xd8>
  8091. HAL_GPIO_WritePin(_T_SYNC_UL_GPIO_Port,_T_SYNC_UL_Pin, GPIO_PIN_RESET);
  8092. 8007c22: 2200 movs r2, #0
  8093. 8007c24: 2120 movs r1, #32
  8094. 8007c26: 4814 ldr r0, [pc, #80] ; (8007c78 <Power_ON_OFF_Ctrl+0x108>)
  8095. 8007c28: f7fe fb54 bl 80062d4 <HAL_GPIO_WritePin>
  8096. HAL_GPIO_WritePin(T_SYNC_UL_GPIO_Port,T_SYNC_UL_Pin, GPIO_PIN_RESET);
  8097. 8007c2c: 2200 movs r2, #0
  8098. 8007c2e: 2140 movs r1, #64 ; 0x40
  8099. 8007c30: 4811 ldr r0, [pc, #68] ; (8007c78 <Power_ON_OFF_Ctrl+0x108>)
  8100. 8007c32: f7fe fb4f bl 80062d4 <HAL_GPIO_WritePin>
  8101. HAL_GPIO_WritePin(_T_SYNC_DL_GPIO_Port,_T_SYNC_DL_Pin, GPIO_PIN_SET);
  8102. 8007c36: 2201 movs r2, #1
  8103. 8007c38: 2180 movs r1, #128 ; 0x80
  8104. 8007c3a: 480f ldr r0, [pc, #60] ; (8007c78 <Power_ON_OFF_Ctrl+0x108>)
  8105. 8007c3c: f7fe fb4a bl 80062d4 <HAL_GPIO_WritePin>
  8106. HAL_GPIO_WritePin(T_SYNC_DL_GPIO_Port,T_SYNC_DL_Pin, GPIO_PIN_SET);
  8107. 8007c40: 2201 movs r2, #1
  8108. HAL_GPIO_WritePin(T_SYNC_DL_GPIO_Port,T_SYNC_DL_Pin, GPIO_PIN_RESET);
  8109. 8007c42: f44f 7180 mov.w r1, #256 ; 0x100
  8110. 8007c46: e7cb b.n 8007be0 <Power_ON_OFF_Ctrl+0x70>
  8111. HAL_GPIO_WritePin(_T_SYNC_UL_GPIO_Port,_T_SYNC_UL_Pin, GPIO_PIN_SET);
  8112. 8007c48: 2201 movs r2, #1
  8113. 8007c4a: 2120 movs r1, #32
  8114. 8007c4c: 480a ldr r0, [pc, #40] ; (8007c78 <Power_ON_OFF_Ctrl+0x108>)
  8115. 8007c4e: f7fe fb41 bl 80062d4 <HAL_GPIO_WritePin>
  8116. HAL_GPIO_WritePin(T_SYNC_UL_GPIO_Port,T_SYNC_UL_Pin, GPIO_PIN_SET);
  8117. 8007c52: 2201 movs r2, #1
  8118. 8007c54: 2140 movs r1, #64 ; 0x40
  8119. 8007c56: 4808 ldr r0, [pc, #32] ; (8007c78 <Power_ON_OFF_Ctrl+0x108>)
  8120. 8007c58: f7fe fb3c bl 80062d4 <HAL_GPIO_WritePin>
  8121. HAL_GPIO_WritePin(_T_SYNC_DL_GPIO_Port,_T_SYNC_DL_Pin, GPIO_PIN_RESET);
  8122. 8007c5c: 4622 mov r2, r4
  8123. 8007c5e: 2180 movs r1, #128 ; 0x80
  8124. 8007c60: 4805 ldr r0, [pc, #20] ; (8007c78 <Power_ON_OFF_Ctrl+0x108>)
  8125. 8007c62: f7fe fb37 bl 80062d4 <HAL_GPIO_WritePin>
  8126. HAL_GPIO_WritePin(T_SYNC_DL_GPIO_Port,T_SYNC_DL_Pin, GPIO_PIN_RESET);
  8127. 8007c66: 4622 mov r2, r4
  8128. 8007c68: e7eb b.n 8007c42 <Power_ON_OFF_Ctrl+0xd2>
  8129. 8007c6a: bd10 pop {r4, pc}
  8130. 8007c6c: 40011000 .word 0x40011000
  8131. 8007c70: 40011800 .word 0x40011800
  8132. 8007c74: 40011400 .word 0x40011400
  8133. 8007c78: 40012000 .word 0x40012000
  8134. 08007c7c <ATTEN_PLL_PATH_Initialize>:
  8135. void ATTEN_PLL_PATH_Initialize(void){
  8136. 8007c7c: b510 push {r4, lr}
  8137. #if 0 // PYJ.2019.07.31_BEGIN --
  8138. for(int i = 0; i < INDEX_BLUE_EOF + 1; i++){
  8139. printf("Data = %x\r\n", Flash_Save_data[i]);
  8140. }
  8141. #endif // PYJ.2019.07.31_END --
  8142. Flash_Save_data[INDEX_BLUE_CRC] = STH30_CreateCrc(&Flash_Save_data[Type], Flash_Save_data[Length]);
  8143. 8007c7e: 4c07 ldr r4, [pc, #28] ; (8007c9c <ATTEN_PLL_PATH_Initialize+0x20>)
  8144. 8007c80: 78a1 ldrb r1, [r4, #2]
  8145. 8007c82: 1c60 adds r0, r4, #1
  8146. 8007c84: f7ff fbcd bl 8007422 <STH30_CreateCrc>
  8147. 8007c88: f884 005e strb.w r0, [r4, #94] ; 0x5e
  8148. RF_Ctrl_Main(&Flash_Save_data[INDEX_BLUE_HEADER]);
  8149. 8007c8c: 4620 mov r0, r4
  8150. 8007c8e: f001 fabf bl 8009210 <RF_Ctrl_Main>
  8151. RF_Status_Get();
  8152. }
  8153. 8007c92: e8bd 4010 ldmia.w sp!, {r4, lr}
  8154. RF_Status_Get();
  8155. 8007c96: f000 be65 b.w 8008964 <RF_Status_Get>
  8156. 8007c9a: bf00 nop
  8157. 8007c9c: 20000488 .word 0x20000488
  8158. 08007ca0 <Power_ON_OFF_Initialize>:
  8159. void Power_ON_OFF_Initialize(void){
  8160. 8007ca0: b570 push {r4, r5, r6, lr}
  8161. /* * * PATH PLL ON OFF SECTION* * */
  8162. HAL_GPIO_WritePin(PATH_EN_3_5G_L_GPIO_Port ,PATH_EN_3_5G_L_Pin , GPIO_PIN_RESET);
  8163. 8007ca2: 4d2e ldr r5, [pc, #184] ; (8007d5c <Power_ON_OFF_Initialize+0xbc>)
  8164. HAL_GPIO_WritePin(PATH_EN_3_5G_H_GPIO_Port ,PATH_EN_3_5G_H_Pin , GPIO_PIN_RESET);
  8165. 8007ca4: 4c2e ldr r4, [pc, #184] ; (8007d60 <Power_ON_OFF_Initialize+0xc0>)
  8166. HAL_GPIO_WritePin(PATH_EN_3_5G_L_GPIO_Port ,PATH_EN_3_5G_L_Pin , GPIO_PIN_RESET);
  8167. 8007ca6: 4628 mov r0, r5
  8168. 8007ca8: 2200 movs r2, #0
  8169. 8007caa: 2180 movs r1, #128 ; 0x80
  8170. 8007cac: f7fe fb12 bl 80062d4 <HAL_GPIO_WritePin>
  8171. HAL_GPIO_WritePin(PATH_EN_3_5G_H_GPIO_Port ,PATH_EN_3_5G_H_Pin , GPIO_PIN_RESET);
  8172. 8007cb0: 4620 mov r0, r4
  8173. 8007cb2: 2200 movs r2, #0
  8174. 8007cb4: f44f 7100 mov.w r1, #512 ; 0x200
  8175. 8007cb8: f7fe fb0c bl 80062d4 <HAL_GPIO_WritePin>
  8176. HAL_GPIO_WritePin(PATH_EN_3_5G_DL_GPIO_Port ,PATH_EN_3_5G_DL_Pin , GPIO_PIN_RESET);
  8177. 8007cbc: 4620 mov r0, r4
  8178. 8007cbe: 2200 movs r2, #0
  8179. 8007cc0: f44f 6180 mov.w r1, #1024 ; 0x400
  8180. 8007cc4: f7fe fb06 bl 80062d4 <HAL_GPIO_WritePin>
  8181. HAL_GPIO_WritePin(PATH_EN_3_5G_UL_GPIO_Port ,PATH_EN_3_5G_UL_Pin , GPIO_PIN_RESET);
  8182. 8007cc8: 4620 mov r0, r4
  8183. 8007cca: 2200 movs r2, #0
  8184. 8007ccc: f44f 6100 mov.w r1, #2048 ; 0x800
  8185. 8007cd0: f7fe fb00 bl 80062d4 <HAL_GPIO_WritePin>
  8186. HAL_GPIO_WritePin(PATH_EN_3_5G_L_GPIO_Port ,PATH_EN_3_5G_L_Pin , GPIO_PIN_RESET);
  8187. 8007cd4: 4628 mov r0, r5
  8188. 8007cd6: 2200 movs r2, #0
  8189. HAL_GPIO_WritePin(PLL_ON_OFF_3_5G_H_GPIO_Port,PLL_ON_OFF_3_5G_H_Pin, GPIO_PIN_RESET);
  8190. 8007cd8: f5a5 6580 sub.w r5, r5, #1024 ; 0x400
  8191. HAL_GPIO_WritePin(PATH_EN_3_5G_L_GPIO_Port ,PATH_EN_3_5G_L_Pin , GPIO_PIN_RESET);
  8192. 8007cdc: 2180 movs r1, #128 ; 0x80
  8193. 8007cde: f7fe faf9 bl 80062d4 <HAL_GPIO_WritePin>
  8194. HAL_GPIO_WritePin(PLL_ON_OFF_3_5G_L_GPIO_Port,PLL_ON_OFF_3_5G_L_Pin, GPIO_PIN_RESET);
  8195. HAL_GPIO_WritePin(PATH_EN_2_1G_DL_GPIO_Port ,PATH_EN_2_1G_DL_Pin , GPIO_PIN_RESET);
  8196. 8007ce2: 4e20 ldr r6, [pc, #128] ; (8007d64 <Power_ON_OFF_Initialize+0xc4>)
  8197. HAL_GPIO_WritePin(PLL_ON_OFF_3_5G_H_GPIO_Port,PLL_ON_OFF_3_5G_H_Pin, GPIO_PIN_RESET);
  8198. 8007ce4: 4628 mov r0, r5
  8199. 8007ce6: 2200 movs r2, #0
  8200. 8007ce8: f44f 5180 mov.w r1, #4096 ; 0x1000
  8201. 8007cec: f7fe faf2 bl 80062d4 <HAL_GPIO_WritePin>
  8202. HAL_GPIO_WritePin(PLL_ON_OFF_3_5G_L_GPIO_Port,PLL_ON_OFF_3_5G_L_Pin, GPIO_PIN_RESET);
  8203. 8007cf0: 4628 mov r0, r5
  8204. 8007cf2: 2200 movs r2, #0
  8205. 8007cf4: f44f 6180 mov.w r1, #1024 ; 0x400
  8206. 8007cf8: f7fe faec bl 80062d4 <HAL_GPIO_WritePin>
  8207. HAL_GPIO_WritePin(PATH_EN_2_1G_DL_GPIO_Port ,PATH_EN_2_1G_DL_Pin , GPIO_PIN_RESET);
  8208. 8007cfc: 4630 mov r0, r6
  8209. 8007cfe: 2200 movs r2, #0
  8210. 8007d00: 2101 movs r1, #1
  8211. 8007d02: f7fe fae7 bl 80062d4 <HAL_GPIO_WritePin>
  8212. HAL_GPIO_WritePin(PATH_EN_2_1G_UL_GPIO_Port ,PATH_EN_2_1G_UL_Pin , GPIO_PIN_RESET);
  8213. 8007d06: 4630 mov r0, r6
  8214. 8007d08: 2200 movs r2, #0
  8215. 8007d0a: 2102 movs r1, #2
  8216. 8007d0c: f7fe fae2 bl 80062d4 <HAL_GPIO_WritePin>
  8217. HAL_GPIO_WritePin(PATH_EN_1_8G_DL_GPIO_Port ,PATH_EN_1_8G_DL_Pin , GPIO_PIN_RESET);
  8218. 8007d10: 4628 mov r0, r5
  8219. 8007d12: 2200 movs r2, #0
  8220. 8007d14: f44f 4180 mov.w r1, #16384 ; 0x4000
  8221. 8007d18: f7fe fadc bl 80062d4 <HAL_GPIO_WritePin>
  8222. HAL_GPIO_WritePin(PATH_EN_1_8G_UL_GPIO_Port ,PATH_EN_1_8G_UL_Pin , GPIO_PIN_RESET);
  8223. 8007d1c: 4628 mov r0, r5
  8224. 8007d1e: 2200 movs r2, #0
  8225. 8007d20: f44f 4100 mov.w r1, #32768 ; 0x8000
  8226. 8007d24: f7fe fad6 bl 80062d4 <HAL_GPIO_WritePin>
  8227. /* * * TDD SECTION* * */
  8228. HAL_GPIO_WritePin(_T_SYNC_UL_GPIO_Port,_T_SYNC_UL_Pin, GPIO_PIN_RESET);
  8229. 8007d28: 4620 mov r0, r4
  8230. 8007d2a: 2200 movs r2, #0
  8231. 8007d2c: 2120 movs r1, #32
  8232. 8007d2e: f7fe fad1 bl 80062d4 <HAL_GPIO_WritePin>
  8233. HAL_GPIO_WritePin(T_SYNC_UL_GPIO_Port,T_SYNC_UL_Pin, GPIO_PIN_RESET);
  8234. 8007d32: 4620 mov r0, r4
  8235. 8007d34: 2200 movs r2, #0
  8236. 8007d36: 2140 movs r1, #64 ; 0x40
  8237. 8007d38: f7fe facc bl 80062d4 <HAL_GPIO_WritePin>
  8238. HAL_GPIO_WritePin(_T_SYNC_DL_GPIO_Port,_T_SYNC_DL_Pin, GPIO_PIN_SET);
  8239. 8007d3c: 4620 mov r0, r4
  8240. 8007d3e: 2201 movs r2, #1
  8241. 8007d40: 2180 movs r1, #128 ; 0x80
  8242. 8007d42: f7fe fac7 bl 80062d4 <HAL_GPIO_WritePin>
  8243. HAL_GPIO_WritePin(T_SYNC_DL_GPIO_Port,T_SYNC_DL_Pin, GPIO_PIN_SET);
  8244. 8007d46: 4620 mov r0, r4
  8245. 8007d48: 2201 movs r2, #1
  8246. 8007d4a: f44f 7180 mov.w r1, #256 ; 0x100
  8247. 8007d4e: f7fe fac1 bl 80062d4 <HAL_GPIO_WritePin>
  8248. HAL_Delay(1);
  8249. }
  8250. 8007d52: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr}
  8251. HAL_Delay(1);
  8252. 8007d56: 2001 movs r0, #1
  8253. 8007d58: f7fd bbc8 b.w 80054ec <HAL_Delay>
  8254. 8007d5c: 40011400 .word 0x40011400
  8255. 8007d60: 40012000 .word 0x40012000
  8256. 8007d64: 40011800 .word 0x40011800
  8257. 08007d68 <Pol_Delay_us>:
  8258. HAL_UART_Transmit_DMA(&huart1,&temp_data[INDEX_BLUE_HEADER],temp_data[INDEX_BLUE_LENGTH] + 3);
  8259. }
  8260. void Pol_Delay_us(volatile uint32_t microseconds)
  8261. {
  8262. /* Go to number of cycles for system */
  8263. microseconds *= (SystemCoreClock / 1000000);
  8264. 8007d68: 4a08 ldr r2, [pc, #32] ; (8007d8c <Pol_Delay_us+0x24>)
  8265. 8007d6a: 4909 ldr r1, [pc, #36] ; (8007d90 <Pol_Delay_us+0x28>)
  8266. 8007d6c: 6812 ldr r2, [r2, #0]
  8267. {
  8268. 8007d6e: b082 sub sp, #8
  8269. microseconds *= (SystemCoreClock / 1000000);
  8270. 8007d70: fbb2 f2f1 udiv r2, r2, r1
  8271. {
  8272. 8007d74: 9001 str r0, [sp, #4]
  8273. microseconds *= (SystemCoreClock / 1000000);
  8274. 8007d76: 9b01 ldr r3, [sp, #4]
  8275. 8007d78: 4353 muls r3, r2
  8276. 8007d7a: 9301 str r3, [sp, #4]
  8277. /* Delay till end */
  8278. while (microseconds--);
  8279. 8007d7c: 9b01 ldr r3, [sp, #4]
  8280. 8007d7e: 1e5a subs r2, r3, #1
  8281. 8007d80: 9201 str r2, [sp, #4]
  8282. 8007d82: 2b00 cmp r3, #0
  8283. 8007d84: d1fa bne.n 8007d7c <Pol_Delay_us+0x14>
  8284. }
  8285. 8007d86: b002 add sp, #8
  8286. 8007d88: 4770 bx lr
  8287. 8007d8a: bf00 nop
  8288. 8007d8c: 20000200 .word 0x20000200
  8289. 8007d90: 000f4240 .word 0x000f4240
  8290. 08007d94 <Boot_LED_Toggle>:
  8291. void Boot_LED_Toggle(void){
  8292. 8007d94: b510 push {r4, lr}
  8293. if(LedTimerCnt > 500){HAL_GPIO_TogglePin(BOOT_LED_GPIO_Port,GPIO_PIN_14);LedTimerCnt = 0;}
  8294. 8007d96: 4c06 ldr r4, [pc, #24] ; (8007db0 <Boot_LED_Toggle+0x1c>)
  8295. 8007d98: 6823 ldr r3, [r4, #0]
  8296. 8007d9a: f5b3 7ffa cmp.w r3, #500 ; 0x1f4
  8297. 8007d9e: d906 bls.n 8007dae <Boot_LED_Toggle+0x1a>
  8298. 8007da0: f44f 4180 mov.w r1, #16384 ; 0x4000
  8299. 8007da4: 4803 ldr r0, [pc, #12] ; (8007db4 <Boot_LED_Toggle+0x20>)
  8300. 8007da6: f7fe fa9a bl 80062de <HAL_GPIO_TogglePin>
  8301. 8007daa: 2300 movs r3, #0
  8302. 8007dac: 6023 str r3, [r4, #0]
  8303. 8007dae: bd10 pop {r4, pc}
  8304. 8007db0: 20000440 .word 0x20000440
  8305. 8007db4: 40012000 .word 0x40012000
  8306. 08007db8 <ADC_Check>:
  8307. }
  8308. void ADC_Check(void){
  8309. if(AdcTimerCnt > 2500){
  8310. 8007db8: f640 12c4 movw r2, #2500 ; 0x9c4
  8311. 8007dbc: 4b0b ldr r3, [pc, #44] ; (8007dec <ADC_Check+0x34>)
  8312. void ADC_Check(void){
  8313. 8007dbe: b5f0 push {r4, r5, r6, r7, lr}
  8314. if(AdcTimerCnt > 2500){
  8315. 8007dc0: 6819 ldr r1, [r3, #0]
  8316. 8007dc2: 4291 cmp r1, r2
  8317. 8007dc4: 461a mov r2, r3
  8318. 8007dc6: d90f bls.n 8007de8 <ADC_Check+0x30>
  8319. 8007dc8: 2300 movs r3, #0
  8320. for(uint8_t i = 0; i< ADC_EA; i++ ){
  8321. Prev_data[INDEX_DET_1_8G_DL_IN_H + i*2] = (uint16_t)((ADCvalue[i] & 0xFF00) >> 8);
  8322. Prev_data[INDEX_DET_1_8G_DL_IN_L + i*2] = (uint16_t)(ADCvalue[i] & 0x00FF);
  8323. AdcTimerCnt = 0;
  8324. 8007dca: 461c mov r4, r3
  8325. Prev_data[INDEX_DET_1_8G_DL_IN_H + i*2] = (uint16_t)((ADCvalue[i] & 0xFF00) >> 8);
  8326. 8007dcc: 4f08 ldr r7, [pc, #32] ; (8007df0 <ADC_Check+0x38>)
  8327. 8007dce: 4e09 ldr r6, [pc, #36] ; (8007df4 <ADC_Check+0x3c>)
  8328. 8007dd0: f857 0013 ldr.w r0, [r7, r3, lsl #1]
  8329. 8007dd4: 1999 adds r1, r3, r6
  8330. 8007dd6: 3302 adds r3, #2
  8331. 8007dd8: 0a05 lsrs r5, r0, #8
  8332. for(uint8_t i = 0; i< ADC_EA; i++ ){
  8333. 8007dda: 2b1c cmp r3, #28
  8334. Prev_data[INDEX_DET_1_8G_DL_IN_H + i*2] = (uint16_t)((ADCvalue[i] & 0xFF00) >> 8);
  8335. 8007ddc: f881 5022 strb.w r5, [r1, #34] ; 0x22
  8336. Prev_data[INDEX_DET_1_8G_DL_IN_L + i*2] = (uint16_t)(ADCvalue[i] & 0x00FF);
  8337. 8007de0: f881 0023 strb.w r0, [r1, #35] ; 0x23
  8338. AdcTimerCnt = 0;
  8339. 8007de4: 6014 str r4, [r2, #0]
  8340. for(uint8_t i = 0; i< ADC_EA; i++ ){
  8341. 8007de6: d1f3 bne.n 8007dd0 <ADC_Check+0x18>
  8342. 8007de8: bdf0 pop {r4, r5, r6, r7, pc}
  8343. 8007dea: bf00 nop
  8344. 8007dec: 20000438 .word 0x20000438
  8345. 8007df0: 200005d4 .word 0x200005d4
  8346. 8007df4: 20000574 .word 0x20000574
  8347. 08007df8 <Uart_Check>:
  8348. printf("%x\r\n",i,Prev_data[INDEX_DET_1_8G_DL_IN_L + i]);
  8349. #endif // PYJ.2019.08.09_END --
  8350. }
  8351. }
  8352. }
  8353. void Uart_Check(void){
  8354. 8007df8: b570 push {r4, r5, r6, lr}
  8355. while (TerminalQueue.data > 0 && UartRxTimerCnt > 100) GetDataFromUartQueue(&hTerminal);
  8356. 8007dfa: 4d07 ldr r5, [pc, #28] ; (8007e18 <Uart_Check+0x20>)
  8357. 8007dfc: 4c07 ldr r4, [pc, #28] ; (8007e1c <Uart_Check+0x24>)
  8358. 8007dfe: 4e08 ldr r6, [pc, #32] ; (8007e20 <Uart_Check+0x28>)
  8359. 8007e00: 68ab ldr r3, [r5, #8]
  8360. 8007e02: 2b00 cmp r3, #0
  8361. 8007e04: dd02 ble.n 8007e0c <Uart_Check+0x14>
  8362. 8007e06: 6823 ldr r3, [r4, #0]
  8363. 8007e08: 2b64 cmp r3, #100 ; 0x64
  8364. 8007e0a: d800 bhi.n 8007e0e <Uart_Check+0x16>
  8365. 8007e0c: bd70 pop {r4, r5, r6, pc}
  8366. 8007e0e: 4630 mov r0, r6
  8367. 8007e10: f000 fd42 bl 8008898 <GetDataFromUartQueue>
  8368. 8007e14: e7f4 b.n 8007e00 <Uart_Check+0x8>
  8369. 8007e16: bf00 nop
  8370. 8007e18: 20000b88 .word 0x20000b88
  8371. 8007e1c: 20000444 .word 0x20000444
  8372. 8007e20: 200006c4 .word 0x200006c4
  8373. 08007e24 <HAL_TIM_PeriodElapsedCallback>:
  8374. /* USER CODE BEGIN 0 */
  8375. void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
  8376. {
  8377. if(htim->Instance == TIM6){
  8378. 8007e24: 6802 ldr r2, [r0, #0]
  8379. 8007e26: 4b0a ldr r3, [pc, #40] ; (8007e50 <HAL_TIM_PeriodElapsedCallback+0x2c>)
  8380. 8007e28: 429a cmp r2, r3
  8381. 8007e2a: d10f bne.n 8007e4c <HAL_TIM_PeriodElapsedCallback+0x28>
  8382. UartRxTimerCnt++;
  8383. 8007e2c: 4a09 ldr r2, [pc, #36] ; (8007e54 <HAL_TIM_PeriodElapsedCallback+0x30>)
  8384. 8007e2e: 6813 ldr r3, [r2, #0]
  8385. 8007e30: 3301 adds r3, #1
  8386. 8007e32: 6013 str r3, [r2, #0]
  8387. LedTimerCnt++;
  8388. 8007e34: 4a08 ldr r2, [pc, #32] ; (8007e58 <HAL_TIM_PeriodElapsedCallback+0x34>)
  8389. 8007e36: 6813 ldr r3, [r2, #0]
  8390. 8007e38: 3301 adds r3, #1
  8391. 8007e3a: 6013 str r3, [r2, #0]
  8392. AdcTimerCnt++;
  8393. 8007e3c: 4a07 ldr r2, [pc, #28] ; (8007e5c <HAL_TIM_PeriodElapsedCallback+0x38>)
  8394. 8007e3e: 6813 ldr r3, [r2, #0]
  8395. 8007e40: 3301 adds r3, #1
  8396. 8007e42: 6013 str r3, [r2, #0]
  8397. LDTimerCnt++;
  8398. 8007e44: 4a06 ldr r2, [pc, #24] ; (8007e60 <HAL_TIM_PeriodElapsedCallback+0x3c>)
  8399. 8007e46: 6813 ldr r3, [r2, #0]
  8400. 8007e48: 3301 adds r3, #1
  8401. 8007e4a: 6013 str r3, [r2, #0]
  8402. 8007e4c: 4770 bx lr
  8403. 8007e4e: bf00 nop
  8404. 8007e50: 40001000 .word 0x40001000
  8405. 8007e54: 20000444 .word 0x20000444
  8406. 8007e58: 20000440 .word 0x20000440
  8407. 8007e5c: 20000438 .word 0x20000438
  8408. 8007e60: 2000043c .word 0x2000043c
  8409. 08007e64 <_write>:
  8410. }
  8411. }
  8412. int _write (int file, uint8_t *ptr, uint16_t len)
  8413. {
  8414. 8007e64: b510 push {r4, lr}
  8415. 8007e66: 4614 mov r4, r2
  8416. HAL_UART_Transmit(&huart1, ptr, len,10);
  8417. 8007e68: 230a movs r3, #10
  8418. 8007e6a: 4802 ldr r0, [pc, #8] ; (8007e74 <_write+0x10>)
  8419. 8007e6c: f7ff f802 bl 8006e74 <HAL_UART_Transmit>
  8420. return len;
  8421. }
  8422. 8007e70: 4620 mov r0, r4
  8423. 8007e72: bd10 pop {r4, pc}
  8424. 8007e74: 200006c4 .word 0x200006c4
  8425. 08007e78 <SystemClock_Config>:
  8426. /**
  8427. * @brief System Clock Configuration
  8428. * @retval None
  8429. */
  8430. void SystemClock_Config(void)
  8431. {
  8432. 8007e78: b510 push {r4, lr}
  8433. 8007e7a: b096 sub sp, #88 ; 0x58
  8434. RCC_OscInitTypeDef RCC_OscInitStruct = {0};
  8435. 8007e7c: 2228 movs r2, #40 ; 0x28
  8436. 8007e7e: 2100 movs r1, #0
  8437. 8007e80: a80c add r0, sp, #48 ; 0x30
  8438. 8007e82: f001 fa6e bl 8009362 <memset>
  8439. RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
  8440. 8007e86: 2214 movs r2, #20
  8441. 8007e88: 2100 movs r1, #0
  8442. 8007e8a: a801 add r0, sp, #4
  8443. 8007e8c: f001 fa69 bl 8009362 <memset>
  8444. RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
  8445. 8007e90: 2218 movs r2, #24
  8446. 8007e92: 2100 movs r1, #0
  8447. 8007e94: eb0d 0002 add.w r0, sp, r2
  8448. 8007e98: f001 fa63 bl 8009362 <memset>
  8449. /** Initializes the CPU, AHB and APB busses clocks
  8450. */
  8451. RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
  8452. RCC_OscInitStruct.HSIState = RCC_HSI_ON;
  8453. 8007e9c: 2301 movs r3, #1
  8454. 8007e9e: 9310 str r3, [sp, #64] ; 0x40
  8455. RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
  8456. 8007ea0: 2310 movs r3, #16
  8457. RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
  8458. 8007ea2: 2402 movs r4, #2
  8459. RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
  8460. 8007ea4: 9311 str r3, [sp, #68] ; 0x44
  8461. RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
  8462. RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2;
  8463. RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL14;
  8464. 8007ea6: f44f 1340 mov.w r3, #3145728 ; 0x300000
  8465. if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
  8466. 8007eaa: a80c add r0, sp, #48 ; 0x30
  8467. RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL14;
  8468. 8007eac: 9315 str r3, [sp, #84] ; 0x54
  8469. RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
  8470. 8007eae: 940c str r4, [sp, #48] ; 0x30
  8471. RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
  8472. 8007eb0: 9413 str r4, [sp, #76] ; 0x4c
  8473. if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
  8474. 8007eb2: f7fe fa19 bl 80062e8 <HAL_RCC_OscConfig>
  8475. {
  8476. Error_Handler();
  8477. }
  8478. /** Initializes the CPU, AHB and APB busses clocks
  8479. */
  8480. RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
  8481. 8007eb6: 230f movs r3, #15
  8482. |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
  8483. RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
  8484. RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
  8485. RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
  8486. 8007eb8: f44f 6280 mov.w r2, #1024 ; 0x400
  8487. RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
  8488. 8007ebc: 9301 str r3, [sp, #4]
  8489. RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
  8490. 8007ebe: 2300 movs r3, #0
  8491. RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
  8492. if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
  8493. 8007ec0: 4621 mov r1, r4
  8494. 8007ec2: a801 add r0, sp, #4
  8495. RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
  8496. 8007ec4: 9303 str r3, [sp, #12]
  8497. RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
  8498. 8007ec6: 9204 str r2, [sp, #16]
  8499. RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
  8500. 8007ec8: 9305 str r3, [sp, #20]
  8501. RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
  8502. 8007eca: 9402 str r4, [sp, #8]
  8503. if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
  8504. 8007ecc: f7fe fbd4 bl 8006678 <HAL_RCC_ClockConfig>
  8505. {
  8506. Error_Handler();
  8507. }
  8508. PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
  8509. PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV4;
  8510. 8007ed0: f44f 4380 mov.w r3, #16384 ; 0x4000
  8511. if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
  8512. 8007ed4: a806 add r0, sp, #24
  8513. PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
  8514. 8007ed6: 9406 str r4, [sp, #24]
  8515. PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV4;
  8516. 8007ed8: 9308 str r3, [sp, #32]
  8517. if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
  8518. 8007eda: f7fe fc9f bl 800681c <HAL_RCCEx_PeriphCLKConfig>
  8519. {
  8520. Error_Handler();
  8521. }
  8522. }
  8523. 8007ede: b016 add sp, #88 ; 0x58
  8524. 8007ee0: bd10 pop {r4, pc}
  8525. ...
  8526. 08007ee4 <main>:
  8527. {
  8528. 8007ee4: b580 push {r7, lr}
  8529. static void MX_GPIO_Init(void)
  8530. {
  8531. GPIO_InitTypeDef GPIO_InitStruct = {0};
  8532. /* GPIO Ports Clock Enable */
  8533. __HAL_RCC_GPIOE_CLK_ENABLE();
  8534. 8007ee6: 4db0 ldr r5, [pc, #704] ; (80081a8 <main+0x2c4>)
  8535. {
  8536. 8007ee8: b08c sub sp, #48 ; 0x30
  8537. HAL_Init();
  8538. 8007eea: f7fd fadb bl 80054a4 <HAL_Init>
  8539. SystemClock_Config();
  8540. 8007eee: f7ff ffc3 bl 8007e78 <SystemClock_Config>
  8541. GPIO_InitTypeDef GPIO_InitStruct = {0};
  8542. 8007ef2: 2210 movs r2, #16
  8543. 8007ef4: 2100 movs r1, #0
  8544. 8007ef6: a808 add r0, sp, #32
  8545. 8007ef8: f001 fa33 bl 8009362 <memset>
  8546. __HAL_RCC_GPIOE_CLK_ENABLE();
  8547. 8007efc: 69ab ldr r3, [r5, #24]
  8548. __HAL_RCC_GPIOB_CLK_ENABLE();
  8549. __HAL_RCC_GPIOD_CLK_ENABLE();
  8550. __HAL_RCC_GPIOG_CLK_ENABLE();
  8551. /*Configure GPIO pin Output Level */
  8552. HAL_GPIO_WritePin(GPIOE, ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin
  8553. 8007efe: 2200 movs r2, #0
  8554. __HAL_RCC_GPIOE_CLK_ENABLE();
  8555. 8007f00: f043 0340 orr.w r3, r3, #64 ; 0x40
  8556. 8007f04: 61ab str r3, [r5, #24]
  8557. 8007f06: 69ab ldr r3, [r5, #24]
  8558. HAL_GPIO_WritePin(GPIOE, ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin
  8559. 8007f08: 217f movs r1, #127 ; 0x7f
  8560. __HAL_RCC_GPIOE_CLK_ENABLE();
  8561. 8007f0a: f003 0340 and.w r3, r3, #64 ; 0x40
  8562. 8007f0e: 9301 str r3, [sp, #4]
  8563. 8007f10: 9b01 ldr r3, [sp, #4]
  8564. __HAL_RCC_GPIOC_CLK_ENABLE();
  8565. 8007f12: 69ab ldr r3, [r5, #24]
  8566. HAL_GPIO_WritePin(GPIOE, ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin
  8567. 8007f14: 48a5 ldr r0, [pc, #660] ; (80081ac <main+0x2c8>)
  8568. __HAL_RCC_GPIOC_CLK_ENABLE();
  8569. 8007f16: f043 0310 orr.w r3, r3, #16
  8570. 8007f1a: 61ab str r3, [r5, #24]
  8571. 8007f1c: 69ab ldr r3, [r5, #24]
  8572. /*Configure GPIO pins : ATT_EN_1_8G_DL1_Pin ATT_EN_1_8G_DL2_Pin ATT_EN_1_8G_UL1_Pin ATT_EN_1_8G_UL2_Pin
  8573. ATT_EN_1_8G_UL3_Pin PATH_EN_2_1G_DL_Pin PATH_EN_2_1G_UL_Pin */
  8574. GPIO_InitStruct.Pin = ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin
  8575. |ATT_EN_1_8G_UL3_Pin|PATH_EN_2_1G_DL_Pin|PATH_EN_2_1G_UL_Pin;
  8576. GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  8577. GPIO_InitStruct.Pull = GPIO_NOPULL;
  8578. 8007f1e: 2400 movs r4, #0
  8579. __HAL_RCC_GPIOC_CLK_ENABLE();
  8580. 8007f20: f003 0310 and.w r3, r3, #16
  8581. 8007f24: 9302 str r3, [sp, #8]
  8582. 8007f26: 9b02 ldr r3, [sp, #8]
  8583. __HAL_RCC_GPIOF_CLK_ENABLE();
  8584. 8007f28: 69ab ldr r3, [r5, #24]
  8585. GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  8586. 8007f2a: 2601 movs r6, #1
  8587. __HAL_RCC_GPIOF_CLK_ENABLE();
  8588. 8007f2c: f043 0380 orr.w r3, r3, #128 ; 0x80
  8589. 8007f30: 61ab str r3, [r5, #24]
  8590. 8007f32: 69ab ldr r3, [r5, #24]
  8591. GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
  8592. 8007f34: 2702 movs r7, #2
  8593. __HAL_RCC_GPIOF_CLK_ENABLE();
  8594. 8007f36: f003 0380 and.w r3, r3, #128 ; 0x80
  8595. 8007f3a: 9303 str r3, [sp, #12]
  8596. 8007f3c: 9b03 ldr r3, [sp, #12]
  8597. __HAL_RCC_GPIOA_CLK_ENABLE();
  8598. 8007f3e: 69ab ldr r3, [r5, #24]
  8599. GPIO_InitStruct.Pull = GPIO_NOPULL;
  8600. GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
  8601. HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
  8602. /*Configure GPIO pins : PLL_LD_1_8G_DL_Pin PLL_LD_1_8G_UL_Pin */
  8603. GPIO_InitStruct.Pin = PLL_LD_1_8G_DL_Pin|PLL_LD_1_8G_UL_Pin;
  8604. 8007f40: f04f 090c mov.w r9, #12
  8605. __HAL_RCC_GPIOA_CLK_ENABLE();
  8606. 8007f44: f043 0304 orr.w r3, r3, #4
  8607. 8007f48: 61ab str r3, [r5, #24]
  8608. 8007f4a: 69ab ldr r3, [r5, #24]
  8609. hadc1.Init.NbrOfConversion = 14;
  8610. 8007f4c: f04f 080e mov.w r8, #14
  8611. __HAL_RCC_GPIOA_CLK_ENABLE();
  8612. 8007f50: f003 0304 and.w r3, r3, #4
  8613. 8007f54: 9304 str r3, [sp, #16]
  8614. 8007f56: 9b04 ldr r3, [sp, #16]
  8615. __HAL_RCC_GPIOB_CLK_ENABLE();
  8616. 8007f58: 69ab ldr r3, [r5, #24]
  8617. sConfig.SamplingTime = ADC_SAMPLETIME_239CYCLES_5;
  8618. 8007f5a: f04f 0a07 mov.w sl, #7
  8619. __HAL_RCC_GPIOB_CLK_ENABLE();
  8620. 8007f5e: f043 0308 orr.w r3, r3, #8
  8621. 8007f62: 61ab str r3, [r5, #24]
  8622. 8007f64: 69ab ldr r3, [r5, #24]
  8623. 8007f66: f003 0308 and.w r3, r3, #8
  8624. 8007f6a: 9305 str r3, [sp, #20]
  8625. 8007f6c: 9b05 ldr r3, [sp, #20]
  8626. __HAL_RCC_GPIOD_CLK_ENABLE();
  8627. 8007f6e: 69ab ldr r3, [r5, #24]
  8628. 8007f70: f043 0320 orr.w r3, r3, #32
  8629. 8007f74: 61ab str r3, [r5, #24]
  8630. 8007f76: 69ab ldr r3, [r5, #24]
  8631. 8007f78: f003 0320 and.w r3, r3, #32
  8632. 8007f7c: 9306 str r3, [sp, #24]
  8633. 8007f7e: 9b06 ldr r3, [sp, #24]
  8634. __HAL_RCC_GPIOG_CLK_ENABLE();
  8635. 8007f80: 69ab ldr r3, [r5, #24]
  8636. 8007f82: f443 7380 orr.w r3, r3, #256 ; 0x100
  8637. 8007f86: 61ab str r3, [r5, #24]
  8638. 8007f88: 69ab ldr r3, [r5, #24]
  8639. 8007f8a: f403 7380 and.w r3, r3, #256 ; 0x100
  8640. 8007f8e: 9307 str r3, [sp, #28]
  8641. 8007f90: 9b07 ldr r3, [sp, #28]
  8642. HAL_GPIO_WritePin(GPIOE, ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin
  8643. 8007f92: f7fe f99f bl 80062d4 <HAL_GPIO_WritePin>
  8644. HAL_GPIO_WritePin(GPIOC, ATT_EN_1_8G_UL4_Pin|PATH_EN_1_8G_DL_Pin|PATH_EN_1_8G_UL_Pin|PLL_EN_3_5G_L_Pin
  8645. 8007f96: 2200 movs r2, #0
  8646. 8007f98: f64f 41c0 movw r1, #64704 ; 0xfcc0
  8647. 8007f9c: 4884 ldr r0, [pc, #528] ; (80081b0 <main+0x2cc>)
  8648. 8007f9e: f7fe f999 bl 80062d4 <HAL_GPIO_WritePin>
  8649. HAL_GPIO_WritePin(GPIOF, PLL_EN_1_8G_DL_Pin|PLL_EN_1_8G_UL_Pin|ATT_EN_2_1G_DL1_Pin|ATT_EN_2_1G_DL2_Pin
  8650. 8007fa2: 2200 movs r2, #0
  8651. 8007fa4: f240 31f3 movw r1, #1011 ; 0x3f3
  8652. 8007fa8: 4882 ldr r0, [pc, #520] ; (80081b4 <main+0x2d0>)
  8653. 8007faa: f7fe f993 bl 80062d4 <HAL_GPIO_WritePin>
  8654. HAL_GPIO_WritePin(GPIOD, PLL_DATA_Pin|PLL_CLK_Pin|ATT_DATA_Pin|ATT_CLK_Pin
  8655. 8007fae: 2200 movs r2, #0
  8656. 8007fb0: f648 71ff movw r1, #36863 ; 0x8fff
  8657. 8007fb4: 4880 ldr r0, [pc, #512] ; (80081b8 <main+0x2d4>)
  8658. 8007fb6: f7fe f98d bl 80062d4 <HAL_GPIO_WritePin>
  8659. HAL_GPIO_WritePin(GPIOG, DA_SYNC_Pin|DA_SCLK_Pin|DA_DIN_Pin|_T_SYNC_UL_Pin
  8660. 8007fba: 2200 movs r2, #0
  8661. 8007fbc: f647 71fc movw r1, #32764 ; 0x7ffc
  8662. 8007fc0: 487e ldr r0, [pc, #504] ; (80081bc <main+0x2d8>)
  8663. 8007fc2: f7fe f987 bl 80062d4 <HAL_GPIO_WritePin>
  8664. HAL_GPIO_WritePin(PLL_CLK_3_5G_GPIO_Port, PLL_CLK_3_5G_Pin, GPIO_PIN_RESET);
  8665. 8007fc6: 2200 movs r2, #0
  8666. 8007fc8: f44f 4100 mov.w r1, #32768 ; 0x8000
  8667. 8007fcc: 487c ldr r0, [pc, #496] ; (80081c0 <main+0x2dc>)
  8668. 8007fce: f7fe f981 bl 80062d4 <HAL_GPIO_WritePin>
  8669. HAL_GPIO_WritePin(GPIOB, PLL_EN_2_1G_DL_Pin|PLL_EN_2_1G_UL_Pin, GPIO_PIN_RESET);
  8670. 8007fd2: 2200 movs r2, #0
  8671. 8007fd4: 2118 movs r1, #24
  8672. 8007fd6: 487b ldr r0, [pc, #492] ; (80081c4 <main+0x2e0>)
  8673. 8007fd8: f7fe f97c bl 80062d4 <HAL_GPIO_WritePin>
  8674. GPIO_InitStruct.Pin = ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin
  8675. 8007fdc: 237f movs r3, #127 ; 0x7f
  8676. HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
  8677. 8007fde: a908 add r1, sp, #32
  8678. 8007fe0: 4872 ldr r0, [pc, #456] ; (80081ac <main+0x2c8>)
  8679. GPIO_InitStruct.Pin = ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin
  8680. 8007fe2: 9308 str r3, [sp, #32]
  8681. GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  8682. 8007fe4: 9609 str r6, [sp, #36] ; 0x24
  8683. GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
  8684. 8007fe6: 970b str r7, [sp, #44] ; 0x2c
  8685. GPIO_InitStruct.Pull = GPIO_NOPULL;
  8686. 8007fe8: 940a str r4, [sp, #40] ; 0x28
  8687. HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
  8688. 8007fea: f7fe f881 bl 80060f0 <HAL_GPIO_Init>
  8689. GPIO_InitStruct.Pin = ATT_EN_1_8G_UL4_Pin|PATH_EN_1_8G_DL_Pin|PATH_EN_1_8G_UL_Pin|PLL_EN_3_5G_L_Pin
  8690. 8007fee: f64f 43c0 movw r3, #64704 ; 0xfcc0
  8691. HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
  8692. 8007ff2: a908 add r1, sp, #32
  8693. 8007ff4: 486e ldr r0, [pc, #440] ; (80081b0 <main+0x2cc>)
  8694. GPIO_InitStruct.Pin = ATT_EN_1_8G_UL4_Pin|PATH_EN_1_8G_DL_Pin|PATH_EN_1_8G_UL_Pin|PLL_EN_3_5G_L_Pin
  8695. 8007ff6: 9308 str r3, [sp, #32]
  8696. GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  8697. 8007ff8: 9609 str r6, [sp, #36] ; 0x24
  8698. GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
  8699. 8007ffa: 970b str r7, [sp, #44] ; 0x2c
  8700. GPIO_InitStruct.Pull = GPIO_NOPULL;
  8701. 8007ffc: 940a str r4, [sp, #40] ; 0x28
  8702. HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
  8703. 8007ffe: f7fe f877 bl 80060f0 <HAL_GPIO_Init>
  8704. GPIO_InitStruct.Pin = PLL_EN_1_8G_DL_Pin|PLL_EN_1_8G_UL_Pin|ATT_EN_2_1G_DL1_Pin|ATT_EN_2_1G_DL2_Pin
  8705. 8008002: f240 33f3 movw r3, #1011 ; 0x3f3
  8706. HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
  8707. 8008006: a908 add r1, sp, #32
  8708. 8008008: 486a ldr r0, [pc, #424] ; (80081b4 <main+0x2d0>)
  8709. GPIO_InitStruct.Pin = PLL_EN_1_8G_DL_Pin|PLL_EN_1_8G_UL_Pin|ATT_EN_2_1G_DL1_Pin|ATT_EN_2_1G_DL2_Pin
  8710. 800800a: 9308 str r3, [sp, #32]
  8711. GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  8712. 800800c: 9609 str r6, [sp, #36] ; 0x24
  8713. GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
  8714. 800800e: 970b str r7, [sp, #44] ; 0x2c
  8715. GPIO_InitStruct.Pull = GPIO_NOPULL;
  8716. 8008010: 940a str r4, [sp, #40] ; 0x28
  8717. HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
  8718. 8008012: f7fe f86d bl 80060f0 <HAL_GPIO_Init>
  8719. GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
  8720. GPIO_InitStruct.Pull = GPIO_NOPULL;
  8721. HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
  8722. 8008016: a908 add r1, sp, #32
  8723. 8008018: 4866 ldr r0, [pc, #408] ; (80081b4 <main+0x2d0>)
  8724. GPIO_InitStruct.Pin = PLL_LD_1_8G_DL_Pin|PLL_LD_1_8G_UL_Pin;
  8725. 800801a: f8cd 9020 str.w r9, [sp, #32]
  8726. GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
  8727. 800801e: 9409 str r4, [sp, #36] ; 0x24
  8728. GPIO_InitStruct.Pull = GPIO_NOPULL;
  8729. 8008020: 940a str r4, [sp, #40] ; 0x28
  8730. HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
  8731. 8008022: f7fe f865 bl 80060f0 <HAL_GPIO_Init>
  8732. /*Configure GPIO pins : PLL_DATA_Pin PLL_CLK_Pin ATT_DATA_Pin ATT_CLK_Pin
  8733. DA_LDAC_Pin ATT_CLK_3_5G_Pin ATT_EN_3_5G_Pin ATT_DATA_3_5G_DL_Pin
  8734. ATT_DATA_3_5G_UL_Pin ATT_DATA_3_5G_COM1_Pin ATT_DATA_3_5G_COM2_Pin ATT_DATA_3_5G_COM3_Pin
  8735. PATH_EN_3_5G_L_Pin */
  8736. GPIO_InitStruct.Pin = PLL_DATA_Pin|PLL_CLK_Pin|ATT_DATA_Pin|ATT_CLK_Pin
  8737. 8008026: f648 73ff movw r3, #36863 ; 0x8fff
  8738. |ATT_DATA_3_5G_UL_Pin|ATT_DATA_3_5G_COM1_Pin|ATT_DATA_3_5G_COM2_Pin|ATT_DATA_3_5G_COM3_Pin
  8739. |PATH_EN_3_5G_L_Pin;
  8740. GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  8741. GPIO_InitStruct.Pull = GPIO_NOPULL;
  8742. GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
  8743. HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
  8744. 800802a: a908 add r1, sp, #32
  8745. 800802c: 4862 ldr r0, [pc, #392] ; (80081b8 <main+0x2d4>)
  8746. GPIO_InitStruct.Pin = PLL_DATA_Pin|PLL_CLK_Pin|ATT_DATA_Pin|ATT_CLK_Pin
  8747. 800802e: 9308 str r3, [sp, #32]
  8748. GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  8749. 8008030: 9609 str r6, [sp, #36] ; 0x24
  8750. GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
  8751. 8008032: 970b str r7, [sp, #44] ; 0x2c
  8752. GPIO_InitStruct.Pull = GPIO_NOPULL;
  8753. 8008034: 940a str r4, [sp, #40] ; 0x28
  8754. HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
  8755. 8008036: f7fe f85b bl 80060f0 <HAL_GPIO_Init>
  8756. /*Configure GPIO pins : ALARM_DC_Pin ALARM_AC_Pin */
  8757. GPIO_InitStruct.Pin = ALARM_DC_Pin|ALARM_AC_Pin;
  8758. 800803a: f44f 5340 mov.w r3, #12288 ; 0x3000
  8759. GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
  8760. GPIO_InitStruct.Pull = GPIO_NOPULL;
  8761. HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
  8762. 800803e: a908 add r1, sp, #32
  8763. 8008040: 485d ldr r0, [pc, #372] ; (80081b8 <main+0x2d4>)
  8764. GPIO_InitStruct.Pin = ALARM_DC_Pin|ALARM_AC_Pin;
  8765. 8008042: 9308 str r3, [sp, #32]
  8766. GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
  8767. 8008044: 9409 str r4, [sp, #36] ; 0x24
  8768. GPIO_InitStruct.Pull = GPIO_NOPULL;
  8769. 8008046: 940a str r4, [sp, #40] ; 0x28
  8770. HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
  8771. 8008048: f7fe f852 bl 80060f0 <HAL_GPIO_Init>
  8772. /*Configure GPIO pins : DA_SYNC_Pin DA_SCLK_Pin DA_DIN_Pin _T_SYNC_UL_Pin
  8773. T_SYNC_UL_Pin _T_SYNC_DL_Pin T_SYNC_DL_Pin PATH_EN_3_5G_H_Pin
  8774. PATH_EN_3_5G_DL_Pin PATH_EN_3_5G_UL_Pin PLL_ON_OFF_3_5G_LG12_Pin PLL_ON_OFF_3_5G_HG13_Pin
  8775. BOOT_LED_Pin */
  8776. GPIO_InitStruct.Pin = DA_SYNC_Pin|DA_SCLK_Pin|DA_DIN_Pin|_T_SYNC_UL_Pin
  8777. 800804c: f647 73fc movw r3, #32764 ; 0x7ffc
  8778. |PATH_EN_3_5G_DL_Pin|PATH_EN_3_5G_UL_Pin|PLL_ON_OFF_3_5G_LG12_Pin|PLL_ON_OFF_3_5G_HG13_Pin
  8779. |BOOT_LED_Pin;
  8780. GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  8781. GPIO_InitStruct.Pull = GPIO_NOPULL;
  8782. GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
  8783. HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
  8784. 8008050: a908 add r1, sp, #32
  8785. 8008052: 485a ldr r0, [pc, #360] ; (80081bc <main+0x2d8>)
  8786. GPIO_InitStruct.Pin = DA_SYNC_Pin|DA_SCLK_Pin|DA_DIN_Pin|_T_SYNC_UL_Pin
  8787. 8008054: 9308 str r3, [sp, #32]
  8788. GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  8789. 8008056: 9609 str r6, [sp, #36] ; 0x24
  8790. GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
  8791. 8008058: 970b str r7, [sp, #44] ; 0x2c
  8792. GPIO_InitStruct.Pull = GPIO_NOPULL;
  8793. 800805a: 940a str r4, [sp, #40] ; 0x28
  8794. HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
  8795. 800805c: f7fe f848 bl 80060f0 <HAL_GPIO_Init>
  8796. /*Configure GPIO pins : PLL_LD_3_5G_L_Pin PLL_LD_3_5G_H_Pin */
  8797. GPIO_InitStruct.Pin = PLL_LD_3_5G_L_Pin|PLL_LD_3_5G_H_Pin;
  8798. 8008060: f44f 7340 mov.w r3, #768 ; 0x300
  8799. GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
  8800. GPIO_InitStruct.Pull = GPIO_NOPULL;
  8801. HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
  8802. 8008064: a908 add r1, sp, #32
  8803. 8008066: 4852 ldr r0, [pc, #328] ; (80081b0 <main+0x2cc>)
  8804. GPIO_InitStruct.Pin = PLL_LD_3_5G_L_Pin|PLL_LD_3_5G_H_Pin;
  8805. 8008068: 9308 str r3, [sp, #32]
  8806. GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
  8807. 800806a: 9409 str r4, [sp, #36] ; 0x24
  8808. GPIO_InitStruct.Pull = GPIO_NOPULL;
  8809. 800806c: 940a str r4, [sp, #40] ; 0x28
  8810. HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
  8811. 800806e: f7fe f83f bl 80060f0 <HAL_GPIO_Init>
  8812. /*Configure GPIO pin : PLL_CLK_3_5G_Pin */
  8813. GPIO_InitStruct.Pin = PLL_CLK_3_5G_Pin;
  8814. 8008072: f44f 4300 mov.w r3, #32768 ; 0x8000
  8815. GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  8816. GPIO_InitStruct.Pull = GPIO_NOPULL;
  8817. GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
  8818. HAL_GPIO_Init(PLL_CLK_3_5G_GPIO_Port, &GPIO_InitStruct);
  8819. 8008076: a908 add r1, sp, #32
  8820. 8008078: 4851 ldr r0, [pc, #324] ; (80081c0 <main+0x2dc>)
  8821. GPIO_InitStruct.Pin = PLL_CLK_3_5G_Pin;
  8822. 800807a: 9308 str r3, [sp, #32]
  8823. GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  8824. 800807c: 9609 str r6, [sp, #36] ; 0x24
  8825. GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
  8826. 800807e: 970b str r7, [sp, #44] ; 0x2c
  8827. GPIO_InitStruct.Pull = GPIO_NOPULL;
  8828. 8008080: 940a str r4, [sp, #40] ; 0x28
  8829. HAL_GPIO_Init(PLL_CLK_3_5G_GPIO_Port, &GPIO_InitStruct);
  8830. 8008082: f7fe f835 bl 80060f0 <HAL_GPIO_Init>
  8831. /*Configure GPIO pins : PLL_EN_2_1G_DL_Pin PLL_EN_2_1G_UL_Pin */
  8832. GPIO_InitStruct.Pin = PLL_EN_2_1G_DL_Pin|PLL_EN_2_1G_UL_Pin;
  8833. 8008086: 2318 movs r3, #24
  8834. GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  8835. GPIO_InitStruct.Pull = GPIO_NOPULL;
  8836. GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
  8837. HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
  8838. 8008088: a908 add r1, sp, #32
  8839. 800808a: 484e ldr r0, [pc, #312] ; (80081c4 <main+0x2e0>)
  8840. GPIO_InitStruct.Pin = PLL_EN_2_1G_DL_Pin|PLL_EN_2_1G_UL_Pin;
  8841. 800808c: 9308 str r3, [sp, #32]
  8842. GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  8843. 800808e: 9609 str r6, [sp, #36] ; 0x24
  8844. GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
  8845. 8008090: 970b str r7, [sp, #44] ; 0x2c
  8846. GPIO_InitStruct.Pull = GPIO_NOPULL;
  8847. 8008092: 940a str r4, [sp, #40] ; 0x28
  8848. HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
  8849. 8008094: f7fe f82c bl 80060f0 <HAL_GPIO_Init>
  8850. /*Configure GPIO pins : PLL_LD_2_1G_DL_Pin PLL_LD_2_1G_UL_Pin */
  8851. GPIO_InitStruct.Pin = PLL_LD_2_1G_DL_Pin|PLL_LD_2_1G_UL_Pin;
  8852. 8008098: 2360 movs r3, #96 ; 0x60
  8853. GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
  8854. GPIO_InitStruct.Pull = GPIO_NOPULL;
  8855. HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
  8856. 800809a: a908 add r1, sp, #32
  8857. 800809c: 4849 ldr r0, [pc, #292] ; (80081c4 <main+0x2e0>)
  8858. GPIO_InitStruct.Pin = PLL_LD_2_1G_DL_Pin|PLL_LD_2_1G_UL_Pin;
  8859. 800809e: 9308 str r3, [sp, #32]
  8860. GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
  8861. 80080a0: 9409 str r4, [sp, #36] ; 0x24
  8862. GPIO_InitStruct.Pull = GPIO_NOPULL;
  8863. 80080a2: 940a str r4, [sp, #40] ; 0x28
  8864. HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
  8865. 80080a4: f7fe f824 bl 80060f0 <HAL_GPIO_Init>
  8866. __HAL_RCC_DMA1_CLK_ENABLE();
  8867. 80080a8: 696b ldr r3, [r5, #20]
  8868. 80080aa: 4333 orrs r3, r6
  8869. 80080ac: 616b str r3, [r5, #20]
  8870. 80080ae: 696b ldr r3, [r5, #20]
  8871. hadc1.Instance = ADC1;
  8872. 80080b0: 4d45 ldr r5, [pc, #276] ; (80081c8 <main+0x2e4>)
  8873. __HAL_RCC_DMA1_CLK_ENABLE();
  8874. 80080b2: 4033 ands r3, r6
  8875. 80080b4: 9300 str r3, [sp, #0]
  8876. 80080b6: 9b00 ldr r3, [sp, #0]
  8877. hadc1.Instance = ADC1;
  8878. 80080b8: 4b44 ldr r3, [pc, #272] ; (80081cc <main+0x2e8>)
  8879. if (HAL_ADC_Init(&hadc1) != HAL_OK)
  8880. 80080ba: 4628 mov r0, r5
  8881. hadc1.Instance = ADC1;
  8882. 80080bc: 602b str r3, [r5, #0]
  8883. hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE;
  8884. 80080be: f44f 7380 mov.w r3, #256 ; 0x100
  8885. 80080c2: 60ab str r3, [r5, #8]
  8886. hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
  8887. 80080c4: f44f 2360 mov.w r3, #917504 ; 0xe0000
  8888. hadc1.Init.ContinuousConvMode = ENABLE;
  8889. 80080c8: 60ee str r6, [r5, #12]
  8890. hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
  8891. 80080ca: 61eb str r3, [r5, #28]
  8892. ADC_ChannelConfTypeDef sConfig = {0};
  8893. 80080cc: 9408 str r4, [sp, #32]
  8894. 80080ce: 9409 str r4, [sp, #36] ; 0x24
  8895. 80080d0: 940a str r4, [sp, #40] ; 0x28
  8896. hadc1.Init.DiscontinuousConvMode = DISABLE;
  8897. 80080d2: 616c str r4, [r5, #20]
  8898. hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
  8899. 80080d4: 606c str r4, [r5, #4]
  8900. hadc1.Init.NbrOfConversion = 14;
  8901. 80080d6: f8c5 8010 str.w r8, [r5, #16]
  8902. if (HAL_ADC_Init(&hadc1) != HAL_OK)
  8903. 80080da: f7fd fbc1 bl 8005860 <HAL_ADC_Init>
  8904. if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
  8905. 80080de: a908 add r1, sp, #32
  8906. 80080e0: 4628 mov r0, r5
  8907. sConfig.Rank = ADC_REGULAR_RANK_1;
  8908. 80080e2: 9609 str r6, [sp, #36] ; 0x24
  8909. sConfig.SamplingTime = ADC_SAMPLETIME_239CYCLES_5;
  8910. 80080e4: f8cd a028 str.w sl, [sp, #40] ; 0x28
  8911. sConfig.Channel = ADC_CHANNEL_0;
  8912. 80080e8: 9408 str r4, [sp, #32]
  8913. if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
  8914. 80080ea: f7fd fa4d bl 8005588 <HAL_ADC_ConfigChannel>
  8915. sConfig.Channel = ADC_CHANNEL_1;
  8916. 80080ee: 9608 str r6, [sp, #32]
  8917. sConfig.Rank = ADC_REGULAR_RANK_3;
  8918. 80080f0: 2603 movs r6, #3
  8919. if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
  8920. 80080f2: a908 add r1, sp, #32
  8921. 80080f4: 4628 mov r0, r5
  8922. sConfig.Rank = ADC_REGULAR_RANK_2;
  8923. 80080f6: 9709 str r7, [sp, #36] ; 0x24
  8924. if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
  8925. 80080f8: f7fd fa46 bl 8005588 <HAL_ADC_ConfigChannel>
  8926. if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
  8927. 80080fc: a908 add r1, sp, #32
  8928. 80080fe: 4628 mov r0, r5
  8929. sConfig.Channel = ADC_CHANNEL_2;
  8930. 8008100: 9708 str r7, [sp, #32]
  8931. sConfig.Rank = ADC_REGULAR_RANK_3;
  8932. 8008102: 9609 str r6, [sp, #36] ; 0x24
  8933. if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
  8934. 8008104: f7fd fa40 bl 8005588 <HAL_ADC_ConfigChannel>
  8935. sConfig.Channel = ADC_CHANNEL_3;
  8936. 8008108: 9608 str r6, [sp, #32]
  8937. sConfig.Rank = ADC_REGULAR_RANK_4;
  8938. 800810a: 2604 movs r6, #4
  8939. if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
  8940. 800810c: a908 add r1, sp, #32
  8941. 800810e: 4628 mov r0, r5
  8942. sConfig.Rank = ADC_REGULAR_RANK_4;
  8943. 8008110: 9609 str r6, [sp, #36] ; 0x24
  8944. if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
  8945. 8008112: f7fd fa39 bl 8005588 <HAL_ADC_ConfigChannel>
  8946. sConfig.Channel = ADC_CHANNEL_4;
  8947. 8008116: 9608 str r6, [sp, #32]
  8948. sConfig.Rank = ADC_REGULAR_RANK_5;
  8949. 8008118: 2605 movs r6, #5
  8950. if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
  8951. 800811a: a908 add r1, sp, #32
  8952. 800811c: 4628 mov r0, r5
  8953. sConfig.Rank = ADC_REGULAR_RANK_5;
  8954. 800811e: 9609 str r6, [sp, #36] ; 0x24
  8955. if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
  8956. 8008120: f7fd fa32 bl 8005588 <HAL_ADC_ConfigChannel>
  8957. sConfig.Channel = ADC_CHANNEL_5;
  8958. 8008124: 9608 str r6, [sp, #32]
  8959. sConfig.Rank = ADC_REGULAR_RANK_6;
  8960. 8008126: 2606 movs r6, #6
  8961. if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
  8962. 8008128: a908 add r1, sp, #32
  8963. 800812a: 4628 mov r0, r5
  8964. sConfig.Rank = ADC_REGULAR_RANK_6;
  8965. 800812c: 9609 str r6, [sp, #36] ; 0x24
  8966. if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
  8967. 800812e: f7fd fa2b bl 8005588 <HAL_ADC_ConfigChannel>
  8968. sConfig.Channel = ADC_CHANNEL_6;
  8969. 8008132: 9608 str r6, [sp, #32]
  8970. sConfig.Rank = ADC_REGULAR_RANK_8;
  8971. 8008134: 2608 movs r6, #8
  8972. if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
  8973. 8008136: a908 add r1, sp, #32
  8974. 8008138: 4628 mov r0, r5
  8975. sConfig.Rank = ADC_REGULAR_RANK_7;
  8976. 800813a: f8cd a024 str.w sl, [sp, #36] ; 0x24
  8977. if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
  8978. 800813e: f7fd fa23 bl 8005588 <HAL_ADC_ConfigChannel>
  8979. if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
  8980. 8008142: a908 add r1, sp, #32
  8981. 8008144: 4628 mov r0, r5
  8982. sConfig.Channel = ADC_CHANNEL_7;
  8983. 8008146: f8cd a020 str.w sl, [sp, #32]
  8984. sConfig.Rank = ADC_REGULAR_RANK_8;
  8985. 800814a: 9609 str r6, [sp, #36] ; 0x24
  8986. if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
  8987. 800814c: f7fd fa1c bl 8005588 <HAL_ADC_ConfigChannel>
  8988. sConfig.Channel = ADC_CHANNEL_8;
  8989. 8008150: 9608 str r6, [sp, #32]
  8990. sConfig.Rank = ADC_REGULAR_RANK_9;
  8991. 8008152: 2609 movs r6, #9
  8992. sConfig.Rank = ADC_REGULAR_RANK_10;
  8993. 8008154: f04f 0a0a mov.w sl, #10
  8994. sConfig.Rank = ADC_REGULAR_RANK_11;
  8995. 8008158: 270b movs r7, #11
  8996. if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
  8997. 800815a: a908 add r1, sp, #32
  8998. 800815c: 4628 mov r0, r5
  8999. sConfig.Rank = ADC_REGULAR_RANK_9;
  9000. 800815e: 9609 str r6, [sp, #36] ; 0x24
  9001. if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
  9002. 8008160: f7fd fa12 bl 8005588 <HAL_ADC_ConfigChannel>
  9003. sConfig.Channel = ADC_CHANNEL_9;
  9004. 8008164: 9608 str r6, [sp, #32]
  9005. sConfig.Rank = ADC_REGULAR_RANK_13;
  9006. 8008166: 260d movs r6, #13
  9007. if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
  9008. 8008168: a908 add r1, sp, #32
  9009. 800816a: 4628 mov r0, r5
  9010. sConfig.Rank = ADC_REGULAR_RANK_10;
  9011. 800816c: f8cd a024 str.w sl, [sp, #36] ; 0x24
  9012. if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
  9013. 8008170: f7fd fa0a bl 8005588 <HAL_ADC_ConfigChannel>
  9014. if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
  9015. 8008174: a908 add r1, sp, #32
  9016. 8008176: 4628 mov r0, r5
  9017. sConfig.Channel = ADC_CHANNEL_10;
  9018. 8008178: f8cd a020 str.w sl, [sp, #32]
  9019. sConfig.Rank = ADC_REGULAR_RANK_11;
  9020. 800817c: 9709 str r7, [sp, #36] ; 0x24
  9021. if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
  9022. 800817e: f7fd fa03 bl 8005588 <HAL_ADC_ConfigChannel>
  9023. if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
  9024. 8008182: a908 add r1, sp, #32
  9025. 8008184: 4628 mov r0, r5
  9026. sConfig.Channel = ADC_CHANNEL_11;
  9027. 8008186: 9708 str r7, [sp, #32]
  9028. sConfig.Rank = ADC_REGULAR_RANK_12;
  9029. 8008188: f8cd 9024 str.w r9, [sp, #36] ; 0x24
  9030. if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
  9031. 800818c: f7fd f9fc bl 8005588 <HAL_ADC_ConfigChannel>
  9032. if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
  9033. 8008190: a908 add r1, sp, #32
  9034. 8008192: 4628 mov r0, r5
  9035. sConfig.Rank = ADC_REGULAR_RANK_13;
  9036. 8008194: 9609 str r6, [sp, #36] ; 0x24
  9037. sConfig.Channel = ADC_CHANNEL_12;
  9038. 8008196: f8cd 9020 str.w r9, [sp, #32]
  9039. if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
  9040. 800819a: f7fd f9f5 bl 8005588 <HAL_ADC_ConfigChannel>
  9041. if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
  9042. 800819e: a908 add r1, sp, #32
  9043. 80081a0: 4628 mov r0, r5
  9044. sConfig.Channel = ADC_CHANNEL_13;
  9045. 80081a2: 9608 str r6, [sp, #32]
  9046. 80081a4: e014 b.n 80081d0 <main+0x2ec>
  9047. 80081a6: bf00 nop
  9048. 80081a8: 40021000 .word 0x40021000
  9049. 80081ac: 40011800 .word 0x40011800
  9050. 80081b0: 40011000 .word 0x40011000
  9051. 80081b4: 40011c00 .word 0x40011c00
  9052. 80081b8: 40011400 .word 0x40011400
  9053. 80081bc: 40012000 .word 0x40012000
  9054. 80081c0: 40010800 .word 0x40010800
  9055. 80081c4: 40010c00 .word 0x40010c00
  9056. 80081c8: 20000650 .word 0x20000650
  9057. 80081cc: 40012400 .word 0x40012400
  9058. sConfig.Rank = ADC_REGULAR_RANK_14;
  9059. 80081d0: f8cd 8024 str.w r8, [sp, #36] ; 0x24
  9060. if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
  9061. 80081d4: f7fd f9d8 bl 8005588 <HAL_ADC_ConfigChannel>
  9062. huart1.Init.BaudRate = 115200;
  9063. 80081d8: f44f 33e1 mov.w r3, #115200 ; 0x1c200
  9064. huart1.Instance = USART1;
  9065. 80081dc: 4836 ldr r0, [pc, #216] ; (80082b8 <main+0x3d4>)
  9066. huart1.Init.BaudRate = 115200;
  9067. 80081de: 4a37 ldr r2, [pc, #220] ; (80082bc <main+0x3d8>)
  9068. huart1.Init.WordLength = UART_WORDLENGTH_8B;
  9069. 80081e0: 6084 str r4, [r0, #8]
  9070. huart1.Init.BaudRate = 115200;
  9071. 80081e2: e880 000c stmia.w r0, {r2, r3}
  9072. huart1.Init.StopBits = UART_STOPBITS_1;
  9073. 80081e6: 60c4 str r4, [r0, #12]
  9074. huart1.Init.Parity = UART_PARITY_NONE;
  9075. 80081e8: 6104 str r4, [r0, #16]
  9076. huart1.Init.Mode = UART_MODE_TX_RX;
  9077. 80081ea: f8c0 9014 str.w r9, [r0, #20]
  9078. huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
  9079. 80081ee: 6184 str r4, [r0, #24]
  9080. huart1.Init.OverSampling = UART_OVERSAMPLING_16;
  9081. 80081f0: 61c4 str r4, [r0, #28]
  9082. if (HAL_UART_Init(&huart1) != HAL_OK)
  9083. 80081f2: f7fe fe11 bl 8006e18 <HAL_UART_Init>
  9084. htim6.Init.Prescaler = 5600-1;
  9085. 80081f6: f241 53df movw r3, #5599 ; 0x15df
  9086. htim6.Instance = TIM6;
  9087. 80081fa: 4e31 ldr r6, [pc, #196] ; (80082c0 <main+0x3dc>)
  9088. htim6.Init.Prescaler = 5600-1;
  9089. 80081fc: 4931 ldr r1, [pc, #196] ; (80082c4 <main+0x3e0>)
  9090. if (HAL_TIM_Base_Init(&htim6) != HAL_OK)
  9091. 80081fe: 4630 mov r0, r6
  9092. htim6.Init.Prescaler = 5600-1;
  9093. 8008200: e886 000a stmia.w r6, {r1, r3}
  9094. TIM_MasterConfigTypeDef sMasterConfig = {0};
  9095. 8008204: 9408 str r4, [sp, #32]
  9096. 8008206: 9409 str r4, [sp, #36] ; 0x24
  9097. htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
  9098. 8008208: 60b4 str r4, [r6, #8]
  9099. htim6.Init.Period = 10;
  9100. 800820a: f8c6 a00c str.w sl, [r6, #12]
  9101. htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
  9102. 800820e: 61b4 str r4, [r6, #24]
  9103. if (HAL_TIM_Base_Init(&htim6) != HAL_OK)
  9104. 8008210: f7fe fcf0 bl 8006bf4 <HAL_TIM_Base_Init>
  9105. if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK)
  9106. 8008214: a908 add r1, sp, #32
  9107. 8008216: 4630 mov r0, r6
  9108. sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
  9109. 8008218: 9408 str r4, [sp, #32]
  9110. sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
  9111. 800821a: 9409 str r4, [sp, #36] ; 0x24
  9112. if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK)
  9113. 800821c: f7fe fd04 bl 8006c28 <HAL_TIMEx_MasterConfigSynchronization>
  9114. HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
  9115. 8008220: 4622 mov r2, r4
  9116. 8008222: 4621 mov r1, r4
  9117. 8008224: 2025 movs r0, #37 ; 0x25
  9118. 8008226: f7fd fc1f bl 8005a68 <HAL_NVIC_SetPriority>
  9119. HAL_NVIC_EnableIRQ(USART1_IRQn);
  9120. 800822a: 2025 movs r0, #37 ; 0x25
  9121. 800822c: f7fd fc50 bl 8005ad0 <HAL_NVIC_EnableIRQ>
  9122. HAL_NVIC_SetPriority(TIM6_IRQn, 0, 0);
  9123. 8008230: 4622 mov r2, r4
  9124. 8008232: 4621 mov r1, r4
  9125. 8008234: 2036 movs r0, #54 ; 0x36
  9126. 8008236: f7fd fc17 bl 8005a68 <HAL_NVIC_SetPriority>
  9127. HAL_NVIC_EnableIRQ(TIM6_IRQn);
  9128. 800823a: 2036 movs r0, #54 ; 0x36
  9129. 800823c: f7fd fc48 bl 8005ad0 <HAL_NVIC_EnableIRQ>
  9130. HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
  9131. 8008240: 4622 mov r2, r4
  9132. 8008242: 4621 mov r1, r4
  9133. 8008244: 4638 mov r0, r7
  9134. 8008246: f7fd fc0f bl 8005a68 <HAL_NVIC_SetPriority>
  9135. HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
  9136. 800824a: 4638 mov r0, r7
  9137. 800824c: f7fd fc40 bl 8005ad0 <HAL_NVIC_EnableIRQ>
  9138. HAL_NVIC_SetPriority(DMA1_Channel4_IRQn, 0, 0);
  9139. 8008250: 4622 mov r2, r4
  9140. 8008252: 4621 mov r1, r4
  9141. 8008254: 4640 mov r0, r8
  9142. 8008256: f7fd fc07 bl 8005a68 <HAL_NVIC_SetPriority>
  9143. HAL_NVIC_EnableIRQ(DMA1_Channel4_IRQn);
  9144. 800825a: 4640 mov r0, r8
  9145. 800825c: f7fd fc38 bl 8005ad0 <HAL_NVIC_EnableIRQ>
  9146. HAL_NVIC_SetPriority(DMA1_Channel5_IRQn, 0, 0);
  9147. 8008260: 4622 mov r2, r4
  9148. 8008262: 4621 mov r1, r4
  9149. 8008264: 200f movs r0, #15
  9150. 8008266: f7fd fbff bl 8005a68 <HAL_NVIC_SetPriority>
  9151. HAL_NVIC_EnableIRQ(DMA1_Channel5_IRQn);
  9152. 800826a: 200f movs r0, #15
  9153. 800826c: f7fd fc30 bl 8005ad0 <HAL_NVIC_EnableIRQ>
  9154. InitUartQueue(&TerminalQueue);
  9155. 8008270: 4815 ldr r0, [pc, #84] ; (80082c8 <main+0x3e4>)
  9156. 8008272: f000 faf1 bl 8008858 <InitUartQueue>
  9157. PE43711_PinInit();
  9158. 8008276: f7ff f9a9 bl 80075cc <PE43711_PinInit>
  9159. Power_ON_OFF_Initialize();
  9160. 800827a: f7ff fd11 bl 8007ca0 <Power_ON_OFF_Initialize>
  9161. Path_Init();
  9162. 800827e: f7ff fc25 bl 8007acc <Path_Init>
  9163. while(!(HAL_ADCEx_Calibration_Start(&hadc1)==HAL_OK));
  9164. 8008282: 4628 mov r0, r5
  9165. 8008284: f7fd fb76 bl 8005974 <HAL_ADCEx_Calibration_Start>
  9166. 8008288: 2800 cmp r0, #0
  9167. 800828a: d1fa bne.n 8008282 <main+0x39e>
  9168. Bluecell_Flash_Read(&Flash_Save_data[INDEX_BLUE_HEADER]);
  9169. 800828c: 480f ldr r0, [pc, #60] ; (80082cc <main+0x3e8>)
  9170. 800828e: f7ff fc0d bl 8007aac <Bluecell_Flash_Read>
  9171. ADF4153_Initialize();
  9172. 8008292: f7ff fabb bl 800780c <ADF4153_Initialize>
  9173. ADF4113_Initialize();
  9174. 8008296: f000 f821 bl 80082dc <ADF4113_Initialize>
  9175. ATTEN_PLL_PATH_Initialize();
  9176. 800829a: f7ff fcef bl 8007c7c <ATTEN_PLL_PATH_Initialize>
  9177. HAL_ADC_Start_DMA(&hadc1, (uint32_t*)ADCvalue, 14);
  9178. 800829e: 220e movs r2, #14
  9179. 80082a0: 490b ldr r1, [pc, #44] ; (80082d0 <main+0x3ec>)
  9180. 80082a2: 480c ldr r0, [pc, #48] ; (80082d4 <main+0x3f0>)
  9181. 80082a4: f7fd fa2c bl 8005700 <HAL_ADC_Start_DMA>
  9182. Boot_LED_Toggle();
  9183. 80082a8: f7ff fd74 bl 8007d94 <Boot_LED_Toggle>
  9184. Uart_Check();
  9185. 80082ac: f7ff fda4 bl 8007df8 <Uart_Check>
  9186. ADC_Check();
  9187. 80082b0: f7ff fd82 bl 8007db8 <ADC_Check>
  9188. 80082b4: e7f8 b.n 80082a8 <main+0x3c4>
  9189. 80082b6: bf00 nop
  9190. 80082b8: 200006c4 .word 0x200006c4
  9191. 80082bc: 40013800 .word 0x40013800
  9192. 80082c0: 20000748 .word 0x20000748
  9193. 80082c4: 40001000 .word 0x40001000
  9194. 80082c8: 20000b88 .word 0x20000b88
  9195. 80082cc: 20000488 .word 0x20000488
  9196. 80082d0: 200005d4 .word 0x200005d4
  9197. 80082d4: 20000650 .word 0x20000650
  9198. 080082d8 <Error_Handler>:
  9199. /**
  9200. * @brief This function is executed in case of error occurrence.
  9201. * @retval None
  9202. */
  9203. void Error_Handler(void)
  9204. {
  9205. 80082d8: 4770 bx lr
  9206. ...
  9207. 080082dc <ADF4113_Initialize>:
  9208. uint16_t P;
  9209. uint16_t A;
  9210. uint16_t N;
  9211. }Adf4113_st;
  9212. void ADF4113_Initialize(void){
  9213. if(Flash_Save_data[INDEX_PLL_1_8G_DL_H] == 0 && Flash_Save_data[INDEX_PLL_1_8G_DL_L] == 0){
  9214. 80082dc: 4b10 ldr r3, [pc, #64] ; (8008320 <ADF4113_Initialize+0x44>)
  9215. 80082de: 7d5a ldrb r2, [r3, #21]
  9216. 80082e0: b92a cbnz r2, 80082ee <ADF4113_Initialize+0x12>
  9217. 80082e2: 7d9a ldrb r2, [r3, #22]
  9218. 80082e4: b91a cbnz r2, 80082ee <ADF4113_Initialize+0x12>
  9219. Flash_Save_data[INDEX_PLL_1_8G_DL_H] = ((18425 & 0xFF00) >> 8);//0x47;
  9220. 80082e6: 2247 movs r2, #71 ; 0x47
  9221. 80082e8: 755a strb r2, [r3, #21]
  9222. Flash_Save_data[INDEX_PLL_1_8G_DL_L] = (18425 & 0x00FF);
  9223. 80082ea: 22f9 movs r2, #249 ; 0xf9
  9224. 80082ec: 759a strb r2, [r3, #22]
  9225. }
  9226. if(Flash_Save_data[INDEX_PLL_1_8G_UL_H] == 0 && Flash_Save_data[INDEX_PLL_1_8G_UL_L] == 0){
  9227. 80082ee: 7dda ldrb r2, [r3, #23]
  9228. 80082f0: b92a cbnz r2, 80082fe <ADF4113_Initialize+0x22>
  9229. 80082f2: 7e1a ldrb r2, [r3, #24]
  9230. 80082f4: b91a cbnz r2, 80082fe <ADF4113_Initialize+0x22>
  9231. Flash_Save_data[INDEX_PLL_1_8G_UL_H] = ((17475 & 0xFF00) >> 8);
  9232. 80082f6: 2244 movs r2, #68 ; 0x44
  9233. 80082f8: 75da strb r2, [r3, #23]
  9234. Flash_Save_data[INDEX_PLL_1_8G_UL_L] = (17475 & 0x00FF);
  9235. 80082fa: 2243 movs r2, #67 ; 0x43
  9236. 80082fc: 761a strb r2, [r3, #24]
  9237. }
  9238. if(Flash_Save_data[INDEX_PLL_2_1G_DL_H] == 0 && Flash_Save_data[INDEX_PLL_2_1G_DL_L] == 0){
  9239. 80082fe: 7e5a ldrb r2, [r3, #25]
  9240. 8008300: b92a cbnz r2, 800830e <ADF4113_Initialize+0x32>
  9241. 8008302: 7e9a ldrb r2, [r3, #26]
  9242. 8008304: b91a cbnz r2, 800830e <ADF4113_Initialize+0x32>
  9243. Flash_Save_data[INDEX_PLL_2_1G_DL_H] = ((21400 & 0xFF00) >> 8);
  9244. 8008306: 2253 movs r2, #83 ; 0x53
  9245. 8008308: 765a strb r2, [r3, #25]
  9246. Flash_Save_data[INDEX_PLL_2_1G_DL_L] = (21400 & 0x00FF);
  9247. 800830a: 2298 movs r2, #152 ; 0x98
  9248. 800830c: 769a strb r2, [r3, #26]
  9249. }
  9250. if(Flash_Save_data[INDEX_PLL_2_1G_UL_H] == 0 && Flash_Save_data[INDEX_PLL_2_1G_UL_L] == 0){
  9251. 800830e: 7eda ldrb r2, [r3, #27]
  9252. 8008310: b92a cbnz r2, 800831e <ADF4113_Initialize+0x42>
  9253. 8008312: 7f1a ldrb r2, [r3, #28]
  9254. 8008314: b91a cbnz r2, 800831e <ADF4113_Initialize+0x42>
  9255. Flash_Save_data[INDEX_PLL_2_1G_UL_H] = ((19500 & 0xFF00) >> 8);
  9256. 8008316: 224c movs r2, #76 ; 0x4c
  9257. 8008318: 76da strb r2, [r3, #27]
  9258. Flash_Save_data[INDEX_PLL_2_1G_UL_L] = (19500 & 0x00FF);
  9259. 800831a: 222c movs r2, #44 ; 0x2c
  9260. 800831c: 771a strb r2, [r3, #28]
  9261. 800831e: 4770 bx lr
  9262. 8008320: 20000488 .word 0x20000488
  9263. 08008324 <N_Counter_Latch_Create>:
  9264. printf("FREQ:%f Mhz B : %d , A : %d N_VAL : %d \r\n",(float)(rf_Freq/1000000),B,A,N_val);
  9265. printf("YJ 4113 : %x \r\n",N_Counter_Latch_Create(A,B,0));
  9266. #endif // PYJ.2019.08.10_END --
  9267. return N_Counter_Latch_Create(A,B,0);
  9268. }
  9269. uint32_t N_Counter_Latch_Create(uint16_t _ACOUNTER,uint16_t _BCOUNTER,uint8_t _CPGAIN){
  9270. 8008324: 2301 movs r3, #1
  9271. 8008326: b570 push {r4, r5, r6, lr}
  9272. 8008328: 2402 movs r4, #2
  9273. #ifdef DEBUG_PRINT
  9274. printf("\r\nLINE : %d ret : %x\r\n",__LINE__,ret);
  9275. #endif /* DEBUG_PRINT */
  9276. for(i = 2; i < 8; i++){
  9277. if(_ACOUNTER & 0x01)
  9278. ret += shift_bit << i;
  9279. 800832a: 461d mov r5, r3
  9280. if(_ACOUNTER & 0x01)
  9281. 800832c: 07c6 lsls r6, r0, #31
  9282. ret += shift_bit << i;
  9283. 800832e: bf48 it mi
  9284. 8008330: fa05 f604 lslmi.w r6, r5, r4
  9285. 8008334: f104 0401 add.w r4, r4, #1
  9286. 8008338: bf48 it mi
  9287. 800833a: 199b addmi r3, r3, r6
  9288. for(i = 2; i < 8; i++){
  9289. 800833c: 2c08 cmp r4, #8
  9290. _ACOUNTER = _ACOUNTER >> 1;
  9291. 800833e: ea4f 0050 mov.w r0, r0, lsr #1
  9292. for(i = 2; i < 8; i++){
  9293. 8008342: d1f3 bne.n 800832c <N_Counter_Latch_Create+0x8>
  9294. #ifdef DEBUG_PRINT
  9295. printf("\r\nLINE : %d ret : %x\r\n",__LINE__,ret);
  9296. #endif /* DEBUG_PRINT */
  9297. for(i = 8; i < 21; i++){
  9298. if(_BCOUNTER & 0x01)
  9299. ret += shift_bit << i;
  9300. 8008344: 2001 movs r0, #1
  9301. if(_BCOUNTER & 0x01)
  9302. 8008346: 07cd lsls r5, r1, #31
  9303. ret += shift_bit << i;
  9304. 8008348: bf48 it mi
  9305. 800834a: fa00 f504 lslmi.w r5, r0, r4
  9306. 800834e: f104 0401 add.w r4, r4, #1
  9307. 8008352: bf48 it mi
  9308. 8008354: 195b addmi r3, r3, r5
  9309. for(i = 8; i < 21; i++){
  9310. 8008356: 2c15 cmp r4, #21
  9311. _BCOUNTER = _BCOUNTER >> 1;
  9312. 8008358: ea4f 0151 mov.w r1, r1, lsr #1
  9313. for(i = 8; i < 21; i++){
  9314. 800835c: d1f3 bne.n 8008346 <N_Counter_Latch_Create+0x22>
  9315. }
  9316. #ifdef DEBUG_PRINT
  9317. printf("\r\nLINE : %d ret : %x\r\n",__LINE__,ret);
  9318. #endif /* DEBUG_PRINT */
  9319. if(_CPGAIN & 0x01)
  9320. 800835e: 07d2 lsls r2, r2, #31
  9321. ret += shift_bit << i++;
  9322. 8008360: bf48 it mi
  9323. 8008362: f503 1300 addmi.w r3, r3, #2097152 ; 0x200000
  9324. }
  9325. #ifdef DEBUG_PRINT
  9326. printf("\r\nLINE : %d ret : %x\r\n",__LINE__,ret);
  9327. #endif /* DEBUG_PRINT */
  9328. return ret;
  9329. }
  9330. 8008366: 4618 mov r0, r3
  9331. 8008368: bd70 pop {r4, r5, r6, pc}
  9332. ...
  9333. 0800836c <halSynSetFreq>:
  9334. {
  9335. 800836c: b57f push {r0, r1, r2, r3, r4, r5, r6, lr}
  9336. N_val = (rf_Freq / ADF4113_CH_STEP);
  9337. 800836e: f24c 3550 movw r5, #50000 ; 0xc350
  9338. 8008372: fbb0 f5f5 udiv r5, r0, r5
  9339. if( N_val < ADF4113_PRE8_MIN_N) {
  9340. 8008376: 2d37 cmp r5, #55 ; 0x37
  9341. 8008378: d920 bls.n 80083bc <halSynSetFreq+0x50>
  9342. printf("FREQ:%f Mhz B : %d , A : %d N_VAL : %d \r\n",(float)(rf_Freq/1000000),B,A,N_val);
  9343. 800837a: 4b11 ldr r3, [pc, #68] ; (80083c0 <halSynSetFreq+0x54>)
  9344. B = N_val / P;
  9345. 800837c: 4c11 ldr r4, [pc, #68] ; (80083c4 <halSynSetFreq+0x58>)
  9346. 800837e: fbb0 f4f4 udiv r4, r0, r4
  9347. printf("FREQ:%f Mhz B : %d , A : %d N_VAL : %d \r\n",(float)(rf_Freq/1000000),B,A,N_val);
  9348. 8008382: fbb0 f0f3 udiv r0, r0, r3
  9349. 8008386: f7fc fd19 bl 8004dbc <__aeabi_ui2f>
  9350. 800838a: f7fc f8c5 bl 8004518 <__aeabi_f2d>
  9351. A = N_val -(B * P);
  9352. 800838e: eba5 1644 sub.w r6, r5, r4, lsl #5
  9353. printf("FREQ:%f Mhz B : %d , A : %d N_VAL : %d \r\n",(float)(rf_Freq/1000000),B,A,N_val);
  9354. 8008392: 4602 mov r2, r0
  9355. 8008394: 460b mov r3, r1
  9356. 8008396: e88d 0050 stmia.w sp, {r4, r6}
  9357. 800839a: 9502 str r5, [sp, #8]
  9358. 800839c: 480a ldr r0, [pc, #40] ; (80083c8 <halSynSetFreq+0x5c>)
  9359. 800839e: f001 fc49 bl 8009c34 <iprintf>
  9360. printf("YJ 4113 : %x \r\n",N_Counter_Latch_Create(A,B,0));
  9361. 80083a2: b2a1 uxth r1, r4
  9362. 80083a4: 2200 movs r2, #0
  9363. 80083a6: b2b0 uxth r0, r6
  9364. 80083a8: f7ff ffbc bl 8008324 <N_Counter_Latch_Create>
  9365. 80083ac: 4604 mov r4, r0
  9366. 80083ae: 4601 mov r1, r0
  9367. 80083b0: 4806 ldr r0, [pc, #24] ; (80083cc <halSynSetFreq+0x60>)
  9368. 80083b2: f001 fc3f bl 8009c34 <iprintf>
  9369. }
  9370. 80083b6: 4620 mov r0, r4
  9371. 80083b8: b004 add sp, #16
  9372. 80083ba: bd70 pop {r4, r5, r6, pc}
  9373. return HAL_SYN_INVALID_PRESCALE;
  9374. 80083bc: 2404 movs r4, #4
  9375. 80083be: e7fa b.n 80083b6 <halSynSetFreq+0x4a>
  9376. 80083c0: 000f4240 .word 0x000f4240
  9377. 80083c4: 00186a00 .word 0x00186a00
  9378. 80083c8: 0800bc87 .word 0x0800bc87
  9379. 80083cc: 0800bcb7 .word 0x0800bcb7
  9380. 080083d0 <ADF4113_Module_Ctrl>:
  9381. void ADF4113_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2){
  9382. 80083d0: b084 sub sp, #16
  9383. 80083d2: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
  9384. 80083d6: ac0c add r4, sp, #48 ; 0x30
  9385. 80083d8: e884 000f stmia.w r4, {r0, r1, r2, r3}
  9386. R2 = R2 & 0xFFFFFF;
  9387. R1 = R1 & 0xFFFFFF;
  9388. 80083dc: 9b13 ldr r3, [sp, #76] ; 0x4c
  9389. 80083de: f8bd 7034 ldrh.w r7, [sp, #52] ; 0x34
  9390. 80083e2: f023 437f bic.w r3, r3, #4278190080 ; 0xff000000
  9391. 80083e6: 9301 str r3, [sp, #4]
  9392. R0 = R0 & 0xFFFFFF;
  9393. 80083e8: 9b12 ldr r3, [sp, #72] ; 0x48
  9394. 80083ea: f8dd 8038 ldr.w r8, [sp, #56] ; 0x38
  9395. 80083ee: f8bd 903c ldrh.w r9, [sp, #60] ; 0x3c
  9396. 80083f2: f023 437f bic.w r3, r3, #4278190080 ; 0xff000000
  9397. 80083f6: 9d10 ldr r5, [sp, #64] ; 0x40
  9398. 80083f8: f8bd 6044 ldrh.w r6, [sp, #68] ; 0x44
  9399. HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
  9400. 80083fc: 2200 movs r2, #0
  9401. 80083fe: 4639 mov r1, r7
  9402. R0 = R0 & 0xFFFFFF;
  9403. 8008400: 9300 str r3, [sp, #0]
  9404. 8008402: 4682 mov sl, r0
  9405. R2 = R2 & 0xFFFFFF;
  9406. 8008404: 9c14 ldr r4, [sp, #80] ; 0x50
  9407. HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
  9408. 8008406: f7fd ff65 bl 80062d4 <HAL_GPIO_WritePin>
  9409. HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
  9410. 800840a: 2200 movs r2, #0
  9411. 800840c: 4649 mov r1, r9
  9412. 800840e: 4640 mov r0, r8
  9413. 8008410: f7fd ff60 bl 80062d4 <HAL_GPIO_WritePin>
  9414. HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
  9415. 8008414: 2200 movs r2, #0
  9416. 8008416: 4631 mov r1, r6
  9417. 8008418: 4628 mov r0, r5
  9418. 800841a: f7fd ff5b bl 80062d4 <HAL_GPIO_WritePin>
  9419. 800841e: f04f 0b18 mov.w fp, #24
  9420. R2 = R2 & 0xFFFFFF;
  9421. 8008422: f024 447f bic.w r4, r4, #4278190080 ; 0xff000000
  9422. /* R2 Ctrl */
  9423. for(int i =0; i < 24; i++){
  9424. if(R2 & 0x800000){
  9425. 8008426: f414 0200 ands.w r2, r4, #8388608 ; 0x800000
  9426. #if 0 // PYJ.2019.08.11_BEGIN --
  9427. printf("1");
  9428. #endif // PYJ.2019.08.11_END --
  9429. HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_SET);
  9430. 800842a: bf18 it ne
  9431. 800842c: 2201 movne r2, #1
  9432. }
  9433. else{
  9434. #if 0 // PYJ.2019.08.11_BEGIN --
  9435. printf("0");
  9436. #endif // PYJ.2019.08.11_END --
  9437. HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
  9438. 800842e: 4649 mov r1, r9
  9439. 8008430: 4640 mov r0, r8
  9440. 8008432: f7fd ff4f bl 80062d4 <HAL_GPIO_WritePin>
  9441. }
  9442. HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
  9443. 8008436: 2201 movs r2, #1
  9444. 8008438: 4639 mov r1, r7
  9445. 800843a: 4650 mov r0, sl
  9446. 800843c: f7fd ff4a bl 80062d4 <HAL_GPIO_WritePin>
  9447. Pol_Delay_us(10);
  9448. 8008440: 200a movs r0, #10
  9449. 8008442: f7ff fc91 bl 8007d68 <Pol_Delay_us>
  9450. HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
  9451. 8008446: 2200 movs r2, #0
  9452. 8008448: 4639 mov r1, r7
  9453. 800844a: 4650 mov r0, sl
  9454. 800844c: f7fd ff42 bl 80062d4 <HAL_GPIO_WritePin>
  9455. R2 = ((R2 << 1) & 0xFFFFFF);
  9456. 8008450: 0064 lsls r4, r4, #1
  9457. for(int i =0; i < 24; i++){
  9458. 8008452: f1bb 0b01 subs.w fp, fp, #1
  9459. R2 = ((R2 << 1) & 0xFFFFFF);
  9460. 8008456: f024 447f bic.w r4, r4, #4278190080 ; 0xff000000
  9461. for(int i =0; i < 24; i++){
  9462. 800845a: d1e4 bne.n 8008426 <ADF4113_Module_Ctrl+0x56>
  9463. }
  9464. #if 0 // PYJ.2019.08.11_BEGIN --
  9465. printf("\r\n");
  9466. #endif // PYJ.2019.08.11_END --
  9467. HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
  9468. 800845c: 2201 movs r2, #1
  9469. 800845e: 4631 mov r1, r6
  9470. 8008460: 4628 mov r0, r5
  9471. 8008462: f7fd ff37 bl 80062d4 <HAL_GPIO_WritePin>
  9472. Pol_Delay_us(10);
  9473. 8008466: 200a movs r0, #10
  9474. 8008468: f7ff fc7e bl 8007d68 <Pol_Delay_us>
  9475. HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
  9476. 800846c: 465a mov r2, fp
  9477. 800846e: 4631 mov r1, r6
  9478. 8008470: 4628 mov r0, r5
  9479. 8008472: f7fd ff2f bl 80062d4 <HAL_GPIO_WritePin>
  9480. 8008476: 2418 movs r4, #24
  9481. /* R0 Ctrl */
  9482. for(int i =0; i < 24; i++){
  9483. if(R0 & 0x800000){
  9484. 8008478: 9b00 ldr r3, [sp, #0]
  9485. #if 0 // PYJ.2019.08.11_BEGIN --
  9486. printf("1");
  9487. #endif // PYJ.2019.08.11_END --
  9488. }
  9489. else{
  9490. HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
  9491. 800847a: 4649 mov r1, r9
  9492. if(R0 & 0x800000){
  9493. 800847c: f413 0200 ands.w r2, r3, #8388608 ; 0x800000
  9494. HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_SET);
  9495. 8008480: bf18 it ne
  9496. 8008482: 2201 movne r2, #1
  9497. HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
  9498. 8008484: 4640 mov r0, r8
  9499. 8008486: f7fd ff25 bl 80062d4 <HAL_GPIO_WritePin>
  9500. #if 0 // PYJ.2019.08.11_BEGIN --
  9501. printf("0");
  9502. #endif // PYJ.2019.08.11_END --
  9503. }
  9504. HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
  9505. 800848a: 2201 movs r2, #1
  9506. 800848c: 4639 mov r1, r7
  9507. 800848e: 4650 mov r0, sl
  9508. 8008490: f7fd ff20 bl 80062d4 <HAL_GPIO_WritePin>
  9509. Pol_Delay_us(10);
  9510. 8008494: 200a movs r0, #10
  9511. 8008496: f7ff fc67 bl 8007d68 <Pol_Delay_us>
  9512. HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
  9513. 800849a: 2200 movs r2, #0
  9514. 800849c: 4639 mov r1, r7
  9515. 800849e: 4650 mov r0, sl
  9516. 80084a0: f7fd ff18 bl 80062d4 <HAL_GPIO_WritePin>
  9517. R0 = ((R0 << 1) & 0xFFFFFF);
  9518. 80084a4: 9b00 ldr r3, [sp, #0]
  9519. for(int i =0; i < 24; i++){
  9520. 80084a6: 3c01 subs r4, #1
  9521. R0 = ((R0 << 1) & 0xFFFFFF);
  9522. 80084a8: ea4f 0343 mov.w r3, r3, lsl #1
  9523. 80084ac: f023 437f bic.w r3, r3, #4278190080 ; 0xff000000
  9524. 80084b0: 9300 str r3, [sp, #0]
  9525. for(int i =0; i < 24; i++){
  9526. 80084b2: d1e1 bne.n 8008478 <ADF4113_Module_Ctrl+0xa8>
  9527. }
  9528. #if 0 // PYJ.2019.08.11_BEGIN --
  9529. printf("\r\n");
  9530. #endif // PYJ.2019.08.11_END --
  9531. HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
  9532. 80084b4: 2201 movs r2, #1
  9533. 80084b6: 4631 mov r1, r6
  9534. 80084b8: 4628 mov r0, r5
  9535. 80084ba: f7fd ff0b bl 80062d4 <HAL_GPIO_WritePin>
  9536. Pol_Delay_us(10);
  9537. 80084be: 200a movs r0, #10
  9538. 80084c0: f7ff fc52 bl 8007d68 <Pol_Delay_us>
  9539. HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
  9540. 80084c4: 4622 mov r2, r4
  9541. 80084c6: 4631 mov r1, r6
  9542. 80084c8: 4628 mov r0, r5
  9543. 80084ca: f7fd ff03 bl 80062d4 <HAL_GPIO_WritePin>
  9544. 80084ce: 2418 movs r4, #24
  9545. /* R1 Ctrl */
  9546. for(int i =0; i < 24; i++){
  9547. if(R1 & 0x800000){
  9548. 80084d0: 9b01 ldr r3, [sp, #4]
  9549. }
  9550. else{
  9551. #if 0 // PYJ.2019.08.11_BEGIN --
  9552. printf("0");
  9553. #endif // PYJ.2019.08.11_END --
  9554. HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
  9555. 80084d2: 4649 mov r1, r9
  9556. if(R1 & 0x800000){
  9557. 80084d4: f413 0200 ands.w r2, r3, #8388608 ; 0x800000
  9558. HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_SET);
  9559. 80084d8: bf18 it ne
  9560. 80084da: 2201 movne r2, #1
  9561. HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
  9562. 80084dc: 4640 mov r0, r8
  9563. 80084de: f7fd fef9 bl 80062d4 <HAL_GPIO_WritePin>
  9564. }
  9565. HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
  9566. 80084e2: 2201 movs r2, #1
  9567. 80084e4: 4639 mov r1, r7
  9568. 80084e6: 4650 mov r0, sl
  9569. 80084e8: f7fd fef4 bl 80062d4 <HAL_GPIO_WritePin>
  9570. Pol_Delay_us(10);
  9571. 80084ec: 200a movs r0, #10
  9572. 80084ee: f7ff fc3b bl 8007d68 <Pol_Delay_us>
  9573. HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
  9574. 80084f2: 2200 movs r2, #0
  9575. 80084f4: 4639 mov r1, r7
  9576. 80084f6: 4650 mov r0, sl
  9577. 80084f8: f7fd feec bl 80062d4 <HAL_GPIO_WritePin>
  9578. R1 = ((R1 << 1) & 0xFFFFFF);
  9579. 80084fc: 9b01 ldr r3, [sp, #4]
  9580. for(int i =0; i < 24; i++){
  9581. 80084fe: 3c01 subs r4, #1
  9582. R1 = ((R1 << 1) & 0xFFFFFF);
  9583. 8008500: ea4f 0343 mov.w r3, r3, lsl #1
  9584. 8008504: f023 437f bic.w r3, r3, #4278190080 ; 0xff000000
  9585. 8008508: 9301 str r3, [sp, #4]
  9586. for(int i =0; i < 24; i++){
  9587. 800850a: d1e1 bne.n 80084d0 <ADF4113_Module_Ctrl+0x100>
  9588. }
  9589. #if 0 // PYJ.2019.08.11_BEGIN --
  9590. printf("\r\n");
  9591. #endif // PYJ.2019.08.11_END --
  9592. HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
  9593. 800850c: 4631 mov r1, r6
  9594. 800850e: 2201 movs r2, #1
  9595. 8008510: 4628 mov r0, r5
  9596. 8008512: f7fd fedf bl 80062d4 <HAL_GPIO_WritePin>
  9597. Pol_Delay_us(10);
  9598. 8008516: 200a movs r0, #10
  9599. 8008518: f7ff fc26 bl 8007d68 <Pol_Delay_us>
  9600. HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
  9601. 800851c: 4622 mov r2, r4
  9602. 800851e: 4631 mov r1, r6
  9603. 8008520: 4628 mov r0, r5
  9604. }
  9605. 8008522: b003 add sp, #12
  9606. 8008524: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
  9607. 8008528: b004 add sp, #16
  9608. HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
  9609. 800852a: f7fd bed3 b.w 80062d4 <HAL_GPIO_WritePin>
  9610. ...
  9611. 08008530 <HAL_MspInit>:
  9612. {
  9613. /* USER CODE BEGIN MspInit 0 */
  9614. /* USER CODE END MspInit 0 */
  9615. __HAL_RCC_AFIO_CLK_ENABLE();
  9616. 8008530: 4b0e ldr r3, [pc, #56] ; (800856c <HAL_MspInit+0x3c>)
  9617. {
  9618. 8008532: b082 sub sp, #8
  9619. __HAL_RCC_AFIO_CLK_ENABLE();
  9620. 8008534: 699a ldr r2, [r3, #24]
  9621. 8008536: f042 0201 orr.w r2, r2, #1
  9622. 800853a: 619a str r2, [r3, #24]
  9623. 800853c: 699a ldr r2, [r3, #24]
  9624. 800853e: f002 0201 and.w r2, r2, #1
  9625. 8008542: 9200 str r2, [sp, #0]
  9626. 8008544: 9a00 ldr r2, [sp, #0]
  9627. __HAL_RCC_PWR_CLK_ENABLE();
  9628. 8008546: 69da ldr r2, [r3, #28]
  9629. 8008548: f042 5280 orr.w r2, r2, #268435456 ; 0x10000000
  9630. 800854c: 61da str r2, [r3, #28]
  9631. 800854e: 69db ldr r3, [r3, #28]
  9632. /* System interrupt init*/
  9633. /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled
  9634. */
  9635. __HAL_AFIO_REMAP_SWJ_NOJTAG();
  9636. 8008550: 4a07 ldr r2, [pc, #28] ; (8008570 <HAL_MspInit+0x40>)
  9637. __HAL_RCC_PWR_CLK_ENABLE();
  9638. 8008552: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
  9639. 8008556: 9301 str r3, [sp, #4]
  9640. 8008558: 9b01 ldr r3, [sp, #4]
  9641. __HAL_AFIO_REMAP_SWJ_NOJTAG();
  9642. 800855a: 6853 ldr r3, [r2, #4]
  9643. 800855c: f023 63e0 bic.w r3, r3, #117440512 ; 0x7000000
  9644. 8008560: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000
  9645. 8008564: 6053 str r3, [r2, #4]
  9646. /* USER CODE BEGIN MspInit 1 */
  9647. /* USER CODE END MspInit 1 */
  9648. }
  9649. 8008566: b002 add sp, #8
  9650. 8008568: 4770 bx lr
  9651. 800856a: bf00 nop
  9652. 800856c: 40021000 .word 0x40021000
  9653. 8008570: 40010000 .word 0x40010000
  9654. 08008574 <HAL_ADC_MspInit>:
  9655. * @param hadc: ADC handle pointer
  9656. * @retval None
  9657. */
  9658. void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
  9659. {
  9660. GPIO_InitTypeDef GPIO_InitStruct = {0};
  9661. 8008574: 2210 movs r2, #16
  9662. {
  9663. 8008576: b530 push {r4, r5, lr}
  9664. 8008578: 4605 mov r5, r0
  9665. 800857a: b089 sub sp, #36 ; 0x24
  9666. GPIO_InitTypeDef GPIO_InitStruct = {0};
  9667. 800857c: eb0d 0002 add.w r0, sp, r2
  9668. 8008580: 2100 movs r1, #0
  9669. 8008582: f000 feee bl 8009362 <memset>
  9670. if(hadc->Instance==ADC1)
  9671. 8008586: 682a ldr r2, [r5, #0]
  9672. 8008588: 4b2c ldr r3, [pc, #176] ; (800863c <HAL_ADC_MspInit+0xc8>)
  9673. 800858a: 429a cmp r2, r3
  9674. 800858c: d153 bne.n 8008636 <HAL_ADC_MspInit+0xc2>
  9675. {
  9676. /* USER CODE BEGIN ADC1_MspInit 0 */
  9677. /* USER CODE END ADC1_MspInit 0 */
  9678. /* Peripheral clock enable */
  9679. __HAL_RCC_ADC1_CLK_ENABLE();
  9680. 800858e: f503 436c add.w r3, r3, #60416 ; 0xec00
  9681. 8008592: 699a ldr r2, [r3, #24]
  9682. PA7 ------> ADC1_IN7
  9683. PB0 ------> ADC1_IN8
  9684. PB1 ------> ADC1_IN9
  9685. */
  9686. GPIO_InitStruct.Pin = DET_3_5G_UL_IN_Pin|DET_3_5G_UL_OUT_Pin|RFU_TEMP_Pin|_28V_DET_Pin;
  9687. GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
  9688. 8008594: 2403 movs r4, #3
  9689. __HAL_RCC_ADC1_CLK_ENABLE();
  9690. 8008596: f442 7200 orr.w r2, r2, #512 ; 0x200
  9691. 800859a: 619a str r2, [r3, #24]
  9692. 800859c: 699a ldr r2, [r3, #24]
  9693. HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
  9694. 800859e: a904 add r1, sp, #16
  9695. __HAL_RCC_ADC1_CLK_ENABLE();
  9696. 80085a0: f402 7200 and.w r2, r2, #512 ; 0x200
  9697. 80085a4: 9200 str r2, [sp, #0]
  9698. 80085a6: 9a00 ldr r2, [sp, #0]
  9699. __HAL_RCC_GPIOC_CLK_ENABLE();
  9700. 80085a8: 699a ldr r2, [r3, #24]
  9701. HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
  9702. 80085aa: 4825 ldr r0, [pc, #148] ; (8008640 <HAL_ADC_MspInit+0xcc>)
  9703. __HAL_RCC_GPIOC_CLK_ENABLE();
  9704. 80085ac: f042 0210 orr.w r2, r2, #16
  9705. 80085b0: 619a str r2, [r3, #24]
  9706. 80085b2: 699a ldr r2, [r3, #24]
  9707. 80085b4: f002 0210 and.w r2, r2, #16
  9708. 80085b8: 9201 str r2, [sp, #4]
  9709. 80085ba: 9a01 ldr r2, [sp, #4]
  9710. __HAL_RCC_GPIOA_CLK_ENABLE();
  9711. 80085bc: 699a ldr r2, [r3, #24]
  9712. 80085be: f042 0204 orr.w r2, r2, #4
  9713. 80085c2: 619a str r2, [r3, #24]
  9714. 80085c4: 699a ldr r2, [r3, #24]
  9715. 80085c6: f002 0204 and.w r2, r2, #4
  9716. 80085ca: 9202 str r2, [sp, #8]
  9717. 80085cc: 9a02 ldr r2, [sp, #8]
  9718. __HAL_RCC_GPIOB_CLK_ENABLE();
  9719. 80085ce: 699a ldr r2, [r3, #24]
  9720. 80085d0: f042 0208 orr.w r2, r2, #8
  9721. 80085d4: 619a str r2, [r3, #24]
  9722. 80085d6: 699b ldr r3, [r3, #24]
  9723. GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
  9724. 80085d8: 9405 str r4, [sp, #20]
  9725. __HAL_RCC_GPIOB_CLK_ENABLE();
  9726. 80085da: f003 0308 and.w r3, r3, #8
  9727. 80085de: 9303 str r3, [sp, #12]
  9728. 80085e0: 9b03 ldr r3, [sp, #12]
  9729. GPIO_InitStruct.Pin = DET_3_5G_UL_IN_Pin|DET_3_5G_UL_OUT_Pin|RFU_TEMP_Pin|_28V_DET_Pin;
  9730. 80085e2: 230f movs r3, #15
  9731. 80085e4: 9304 str r3, [sp, #16]
  9732. HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
  9733. 80085e6: f7fd fd83 bl 80060f0 <HAL_GPIO_Init>
  9734. GPIO_InitStruct.Pin = GPIO_PIN_0|DET_1_8G_DL_OUT_Pin|DET_1_8G_UL_IN_Pin|DET_1_8G_UL_OUT_Pin
  9735. 80085ea: 23ff movs r3, #255 ; 0xff
  9736. |DET_2_1G_DL_IN_Pin|DET_2_1G_DL_OUT_Pin|DET_2_1G_UL_IN_Pin|DET_2_1G_UL_OUT_Pin;
  9737. GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
  9738. HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
  9739. 80085ec: a904 add r1, sp, #16
  9740. 80085ee: 4815 ldr r0, [pc, #84] ; (8008644 <HAL_ADC_MspInit+0xd0>)
  9741. GPIO_InitStruct.Pin = GPIO_PIN_0|DET_1_8G_DL_OUT_Pin|DET_1_8G_UL_IN_Pin|DET_1_8G_UL_OUT_Pin
  9742. 80085f0: 9304 str r3, [sp, #16]
  9743. GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
  9744. 80085f2: 9405 str r4, [sp, #20]
  9745. HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
  9746. 80085f4: f7fd fd7c bl 80060f0 <HAL_GPIO_Init>
  9747. GPIO_InitStruct.Pin = DET_3_5G_DL_IN_Pin|DET_3_5G_DL_OUT_Pin;
  9748. GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
  9749. HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
  9750. 80085f8: 4813 ldr r0, [pc, #76] ; (8008648 <HAL_ADC_MspInit+0xd4>)
  9751. 80085fa: a904 add r1, sp, #16
  9752. GPIO_InitStruct.Pin = DET_3_5G_DL_IN_Pin|DET_3_5G_DL_OUT_Pin;
  9753. 80085fc: 9404 str r4, [sp, #16]
  9754. GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
  9755. 80085fe: 9405 str r4, [sp, #20]
  9756. HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
  9757. 8008600: f7fd fd76 bl 80060f0 <HAL_GPIO_Init>
  9758. /* ADC1 DMA Init */
  9759. /* ADC1 Init */
  9760. hdma_adc1.Instance = DMA1_Channel1;
  9761. hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY;
  9762. hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE;
  9763. hdma_adc1.Init.MemInc = DMA_MINC_ENABLE;
  9764. 8008604: 2280 movs r2, #128 ; 0x80
  9765. hdma_adc1.Instance = DMA1_Channel1;
  9766. 8008606: 4c11 ldr r4, [pc, #68] ; (800864c <HAL_ADC_MspInit+0xd8>)
  9767. 8008608: 4b11 ldr r3, [pc, #68] ; (8008650 <HAL_ADC_MspInit+0xdc>)
  9768. hdma_adc1.Init.MemInc = DMA_MINC_ENABLE;
  9769. 800860a: 60e2 str r2, [r4, #12]
  9770. hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
  9771. 800860c: f44f 7200 mov.w r2, #512 ; 0x200
  9772. 8008610: 6122 str r2, [r4, #16]
  9773. hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
  9774. 8008612: f44f 6200 mov.w r2, #2048 ; 0x800
  9775. hdma_adc1.Instance = DMA1_Channel1;
  9776. 8008616: 6023 str r3, [r4, #0]
  9777. hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
  9778. 8008618: 6162 str r2, [r4, #20]
  9779. hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY;
  9780. 800861a: 2300 movs r3, #0
  9781. hdma_adc1.Init.Mode = DMA_CIRCULAR;
  9782. 800861c: 2220 movs r2, #32
  9783. hdma_adc1.Init.Priority = DMA_PRIORITY_LOW;
  9784. if (HAL_DMA_Init(&hdma_adc1) != HAL_OK)
  9785. 800861e: 4620 mov r0, r4
  9786. hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY;
  9787. 8008620: 6063 str r3, [r4, #4]
  9788. hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE;
  9789. 8008622: 60a3 str r3, [r4, #8]
  9790. hdma_adc1.Init.Mode = DMA_CIRCULAR;
  9791. 8008624: 61a2 str r2, [r4, #24]
  9792. hdma_adc1.Init.Priority = DMA_PRIORITY_LOW;
  9793. 8008626: 61e3 str r3, [r4, #28]
  9794. if (HAL_DMA_Init(&hdma_adc1) != HAL_OK)
  9795. 8008628: f7fd fa74 bl 8005b14 <HAL_DMA_Init>
  9796. 800862c: b108 cbz r0, 8008632 <HAL_ADC_MspInit+0xbe>
  9797. {
  9798. Error_Handler();
  9799. 800862e: f7ff fe53 bl 80082d8 <Error_Handler>
  9800. }
  9801. __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc1);
  9802. 8008632: 622c str r4, [r5, #32]
  9803. 8008634: 6265 str r5, [r4, #36] ; 0x24
  9804. /* USER CODE BEGIN ADC1_MspInit 1 */
  9805. /* USER CODE END ADC1_MspInit 1 */
  9806. }
  9807. }
  9808. 8008636: b009 add sp, #36 ; 0x24
  9809. 8008638: bd30 pop {r4, r5, pc}
  9810. 800863a: bf00 nop
  9811. 800863c: 40012400 .word 0x40012400
  9812. 8008640: 40011000 .word 0x40011000
  9813. 8008644: 40010800 .word 0x40010800
  9814. 8008648: 40010c00 .word 0x40010c00
  9815. 800864c: 20000704 .word 0x20000704
  9816. 8008650: 40020008 .word 0x40020008
  9817. 08008654 <HAL_TIM_Base_MspInit>:
  9818. * @param htim_base: TIM_Base handle pointer
  9819. * @retval None
  9820. */
  9821. void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
  9822. {
  9823. if(htim_base->Instance==TIM6)
  9824. 8008654: 6802 ldr r2, [r0, #0]
  9825. 8008656: 4b08 ldr r3, [pc, #32] ; (8008678 <HAL_TIM_Base_MspInit+0x24>)
  9826. {
  9827. 8008658: b082 sub sp, #8
  9828. if(htim_base->Instance==TIM6)
  9829. 800865a: 429a cmp r2, r3
  9830. 800865c: d10a bne.n 8008674 <HAL_TIM_Base_MspInit+0x20>
  9831. {
  9832. /* USER CODE BEGIN TIM6_MspInit 0 */
  9833. /* USER CODE END TIM6_MspInit 0 */
  9834. /* Peripheral clock enable */
  9835. __HAL_RCC_TIM6_CLK_ENABLE();
  9836. 800865e: f503 3300 add.w r3, r3, #131072 ; 0x20000
  9837. 8008662: 69da ldr r2, [r3, #28]
  9838. 8008664: f042 0210 orr.w r2, r2, #16
  9839. 8008668: 61da str r2, [r3, #28]
  9840. 800866a: 69db ldr r3, [r3, #28]
  9841. 800866c: f003 0310 and.w r3, r3, #16
  9842. 8008670: 9301 str r3, [sp, #4]
  9843. 8008672: 9b01 ldr r3, [sp, #4]
  9844. /* USER CODE BEGIN TIM6_MspInit 1 */
  9845. /* USER CODE END TIM6_MspInit 1 */
  9846. }
  9847. }
  9848. 8008674: b002 add sp, #8
  9849. 8008676: 4770 bx lr
  9850. 8008678: 40001000 .word 0x40001000
  9851. 0800867c <HAL_UART_MspInit>:
  9852. * This function configures the hardware resources used in this example
  9853. * @param huart: UART handle pointer
  9854. * @retval None
  9855. */
  9856. void HAL_UART_MspInit(UART_HandleTypeDef* huart)
  9857. {
  9858. 800867c: b570 push {r4, r5, r6, lr}
  9859. 800867e: 4606 mov r6, r0
  9860. 8008680: b086 sub sp, #24
  9861. GPIO_InitTypeDef GPIO_InitStruct = {0};
  9862. 8008682: 2210 movs r2, #16
  9863. 8008684: 2100 movs r1, #0
  9864. 8008686: a802 add r0, sp, #8
  9865. 8008688: f000 fe6b bl 8009362 <memset>
  9866. if(huart->Instance==USART1)
  9867. 800868c: 6832 ldr r2, [r6, #0]
  9868. 800868e: 4b2b ldr r3, [pc, #172] ; (800873c <HAL_UART_MspInit+0xc0>)
  9869. 8008690: 429a cmp r2, r3
  9870. 8008692: d151 bne.n 8008738 <HAL_UART_MspInit+0xbc>
  9871. {
  9872. /* USER CODE BEGIN USART1_MspInit 0 */
  9873. /* USER CODE END USART1_MspInit 0 */
  9874. /* Peripheral clock enable */
  9875. __HAL_RCC_USART1_CLK_ENABLE();
  9876. 8008694: f503 4358 add.w r3, r3, #55296 ; 0xd800
  9877. 8008698: 699a ldr r2, [r3, #24]
  9878. PA10 ------> USART1_RX
  9879. */
  9880. GPIO_InitStruct.Pin = GPIO_PIN_9;
  9881. GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
  9882. GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
  9883. HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
  9884. 800869a: a902 add r1, sp, #8
  9885. __HAL_RCC_USART1_CLK_ENABLE();
  9886. 800869c: f442 4280 orr.w r2, r2, #16384 ; 0x4000
  9887. 80086a0: 619a str r2, [r3, #24]
  9888. 80086a2: 699a ldr r2, [r3, #24]
  9889. HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
  9890. 80086a4: 4826 ldr r0, [pc, #152] ; (8008740 <HAL_UART_MspInit+0xc4>)
  9891. __HAL_RCC_USART1_CLK_ENABLE();
  9892. 80086a6: f402 4280 and.w r2, r2, #16384 ; 0x4000
  9893. 80086aa: 9200 str r2, [sp, #0]
  9894. 80086ac: 9a00 ldr r2, [sp, #0]
  9895. __HAL_RCC_GPIOA_CLK_ENABLE();
  9896. 80086ae: 699a ldr r2, [r3, #24]
  9897. GPIO_InitStruct.Pin = GPIO_PIN_10;
  9898. GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
  9899. 80086b0: 2500 movs r5, #0
  9900. __HAL_RCC_GPIOA_CLK_ENABLE();
  9901. 80086b2: f042 0204 orr.w r2, r2, #4
  9902. 80086b6: 619a str r2, [r3, #24]
  9903. 80086b8: 699b ldr r3, [r3, #24]
  9904. GPIO_InitStruct.Pull = GPIO_NOPULL;
  9905. HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
  9906. /* USART1 DMA Init */
  9907. /* USART1_RX Init */
  9908. hdma_usart1_rx.Instance = DMA1_Channel5;
  9909. 80086ba: 4c22 ldr r4, [pc, #136] ; (8008744 <HAL_UART_MspInit+0xc8>)
  9910. __HAL_RCC_GPIOA_CLK_ENABLE();
  9911. 80086bc: f003 0304 and.w r3, r3, #4
  9912. 80086c0: 9301 str r3, [sp, #4]
  9913. 80086c2: 9b01 ldr r3, [sp, #4]
  9914. GPIO_InitStruct.Pin = GPIO_PIN_9;
  9915. 80086c4: f44f 7300 mov.w r3, #512 ; 0x200
  9916. 80086c8: 9302 str r3, [sp, #8]
  9917. GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
  9918. 80086ca: 2302 movs r3, #2
  9919. 80086cc: 9303 str r3, [sp, #12]
  9920. GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
  9921. 80086ce: 2303 movs r3, #3
  9922. 80086d0: 9305 str r3, [sp, #20]
  9923. HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
  9924. 80086d2: f7fd fd0d bl 80060f0 <HAL_GPIO_Init>
  9925. GPIO_InitStruct.Pin = GPIO_PIN_10;
  9926. 80086d6: f44f 6380 mov.w r3, #1024 ; 0x400
  9927. HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
  9928. 80086da: 4819 ldr r0, [pc, #100] ; (8008740 <HAL_UART_MspInit+0xc4>)
  9929. 80086dc: a902 add r1, sp, #8
  9930. GPIO_InitStruct.Pin = GPIO_PIN_10;
  9931. 80086de: 9302 str r3, [sp, #8]
  9932. GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
  9933. 80086e0: 9503 str r5, [sp, #12]
  9934. GPIO_InitStruct.Pull = GPIO_NOPULL;
  9935. 80086e2: 9504 str r5, [sp, #16]
  9936. HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
  9937. 80086e4: f7fd fd04 bl 80060f0 <HAL_GPIO_Init>
  9938. hdma_usart1_rx.Instance = DMA1_Channel5;
  9939. 80086e8: 4b17 ldr r3, [pc, #92] ; (8008748 <HAL_UART_MspInit+0xcc>)
  9940. hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE;
  9941. hdma_usart1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
  9942. hdma_usart1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
  9943. hdma_usart1_rx.Init.Mode = DMA_NORMAL;
  9944. hdma_usart1_rx.Init.Priority = DMA_PRIORITY_LOW;
  9945. if (HAL_DMA_Init(&hdma_usart1_rx) != HAL_OK)
  9946. 80086ea: 4620 mov r0, r4
  9947. hdma_usart1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
  9948. 80086ec: e884 0028 stmia.w r4, {r3, r5}
  9949. hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE;
  9950. 80086f0: 2380 movs r3, #128 ; 0x80
  9951. hdma_usart1_rx.Init.PeriphInc = DMA_PINC_DISABLE;
  9952. 80086f2: 60a5 str r5, [r4, #8]
  9953. hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE;
  9954. 80086f4: 60e3 str r3, [r4, #12]
  9955. hdma_usart1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
  9956. 80086f6: 6125 str r5, [r4, #16]
  9957. hdma_usart1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
  9958. 80086f8: 6165 str r5, [r4, #20]
  9959. hdma_usart1_rx.Init.Mode = DMA_NORMAL;
  9960. 80086fa: 61a5 str r5, [r4, #24]
  9961. hdma_usart1_rx.Init.Priority = DMA_PRIORITY_LOW;
  9962. 80086fc: 61e5 str r5, [r4, #28]
  9963. if (HAL_DMA_Init(&hdma_usart1_rx) != HAL_OK)
  9964. 80086fe: f7fd fa09 bl 8005b14 <HAL_DMA_Init>
  9965. 8008702: b108 cbz r0, 8008708 <HAL_UART_MspInit+0x8c>
  9966. {
  9967. Error_Handler();
  9968. 8008704: f7ff fde8 bl 80082d8 <Error_Handler>
  9969. __HAL_LINKDMA(huart,hdmarx,hdma_usart1_rx);
  9970. /* USART1_TX Init */
  9971. hdma_usart1_tx.Instance = DMA1_Channel4;
  9972. hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
  9973. 8008708: f04f 0c10 mov.w ip, #16
  9974. 800870c: 4b0f ldr r3, [pc, #60] ; (800874c <HAL_UART_MspInit+0xd0>)
  9975. __HAL_LINKDMA(huart,hdmarx,hdma_usart1_rx);
  9976. 800870e: 6374 str r4, [r6, #52] ; 0x34
  9977. 8008710: 6266 str r6, [r4, #36] ; 0x24
  9978. hdma_usart1_tx.Instance = DMA1_Channel4;
  9979. 8008712: 4c0f ldr r4, [pc, #60] ; (8008750 <HAL_UART_MspInit+0xd4>)
  9980. hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
  9981. hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE;
  9982. 8008714: 2280 movs r2, #128 ; 0x80
  9983. hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
  9984. 8008716: e884 1008 stmia.w r4, {r3, ip}
  9985. hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
  9986. 800871a: 2300 movs r3, #0
  9987. hdma_usart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
  9988. hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
  9989. hdma_usart1_tx.Init.Mode = DMA_NORMAL;
  9990. hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW;
  9991. if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK)
  9992. 800871c: 4620 mov r0, r4
  9993. hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
  9994. 800871e: 60a3 str r3, [r4, #8]
  9995. hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE;
  9996. 8008720: 60e2 str r2, [r4, #12]
  9997. hdma_usart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
  9998. 8008722: 6123 str r3, [r4, #16]
  9999. hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
  10000. 8008724: 6163 str r3, [r4, #20]
  10001. hdma_usart1_tx.Init.Mode = DMA_NORMAL;
  10002. 8008726: 61a3 str r3, [r4, #24]
  10003. hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW;
  10004. 8008728: 61e3 str r3, [r4, #28]
  10005. if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK)
  10006. 800872a: f7fd f9f3 bl 8005b14 <HAL_DMA_Init>
  10007. 800872e: b108 cbz r0, 8008734 <HAL_UART_MspInit+0xb8>
  10008. {
  10009. Error_Handler();
  10010. 8008730: f7ff fdd2 bl 80082d8 <Error_Handler>
  10011. }
  10012. __HAL_LINKDMA(huart,hdmatx,hdma_usart1_tx);
  10013. 8008734: 6334 str r4, [r6, #48] ; 0x30
  10014. 8008736: 6266 str r6, [r4, #36] ; 0x24
  10015. /* USER CODE BEGIN USART1_MspInit 1 */
  10016. /* USER CODE END USART1_MspInit 1 */
  10017. }
  10018. }
  10019. 8008738: b006 add sp, #24
  10020. 800873a: bd70 pop {r4, r5, r6, pc}
  10021. 800873c: 40013800 .word 0x40013800
  10022. 8008740: 40010800 .word 0x40010800
  10023. 8008744: 20000680 .word 0x20000680
  10024. 8008748: 40020058 .word 0x40020058
  10025. 800874c: 40020044 .word 0x40020044
  10026. 8008750: 2000060c .word 0x2000060c
  10027. 08008754 <NMI_Handler>:
  10028. 8008754: 4770 bx lr
  10029. 08008756 <HardFault_Handler>:
  10030. /**
  10031. * @brief This function handles Hard fault interrupt.
  10032. */
  10033. void HardFault_Handler(void)
  10034. {
  10035. 8008756: e7fe b.n 8008756 <HardFault_Handler>
  10036. 08008758 <MemManage_Handler>:
  10037. /**
  10038. * @brief This function handles Memory management fault.
  10039. */
  10040. void MemManage_Handler(void)
  10041. {
  10042. 8008758: e7fe b.n 8008758 <MemManage_Handler>
  10043. 0800875a <BusFault_Handler>:
  10044. /**
  10045. * @brief This function handles Prefetch fault, memory access fault.
  10046. */
  10047. void BusFault_Handler(void)
  10048. {
  10049. 800875a: e7fe b.n 800875a <BusFault_Handler>
  10050. 0800875c <UsageFault_Handler>:
  10051. /**
  10052. * @brief This function handles Undefined instruction or illegal state.
  10053. */
  10054. void UsageFault_Handler(void)
  10055. {
  10056. 800875c: e7fe b.n 800875c <UsageFault_Handler>
  10057. 0800875e <SVC_Handler>:
  10058. 800875e: 4770 bx lr
  10059. 08008760 <DebugMon_Handler>:
  10060. 8008760: 4770 bx lr
  10061. 08008762 <PendSV_Handler>:
  10062. /**
  10063. * @brief This function handles Pendable request for system service.
  10064. */
  10065. void PendSV_Handler(void)
  10066. {
  10067. 8008762: 4770 bx lr
  10068. 08008764 <SysTick_Handler>:
  10069. void SysTick_Handler(void)
  10070. {
  10071. /* USER CODE BEGIN SysTick_IRQn 0 */
  10072. /* USER CODE END SysTick_IRQn 0 */
  10073. HAL_IncTick();
  10074. 8008764: f7fc beb0 b.w 80054c8 <HAL_IncTick>
  10075. 08008768 <DMA1_Channel1_IRQHandler>:
  10076. void DMA1_Channel1_IRQHandler(void)
  10077. {
  10078. /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */
  10079. /* USER CODE END DMA1_Channel1_IRQn 0 */
  10080. HAL_DMA_IRQHandler(&hdma_adc1);
  10081. 8008768: 4801 ldr r0, [pc, #4] ; (8008770 <DMA1_Channel1_IRQHandler+0x8>)
  10082. 800876a: f7fd babf b.w 8005cec <HAL_DMA_IRQHandler>
  10083. 800876e: bf00 nop
  10084. 8008770: 20000704 .word 0x20000704
  10085. 08008774 <DMA1_Channel4_IRQHandler>:
  10086. void DMA1_Channel4_IRQHandler(void)
  10087. {
  10088. /* USER CODE BEGIN DMA1_Channel4_IRQn 0 */
  10089. /* USER CODE END DMA1_Channel4_IRQn 0 */
  10090. HAL_DMA_IRQHandler(&hdma_usart1_tx);
  10091. 8008774: 4801 ldr r0, [pc, #4] ; (800877c <DMA1_Channel4_IRQHandler+0x8>)
  10092. 8008776: f7fd bab9 b.w 8005cec <HAL_DMA_IRQHandler>
  10093. 800877a: bf00 nop
  10094. 800877c: 2000060c .word 0x2000060c
  10095. 08008780 <DMA1_Channel5_IRQHandler>:
  10096. void DMA1_Channel5_IRQHandler(void)
  10097. {
  10098. /* USER CODE BEGIN DMA1_Channel5_IRQn 0 */
  10099. /* USER CODE END DMA1_Channel5_IRQn 0 */
  10100. HAL_DMA_IRQHandler(&hdma_usart1_rx);
  10101. 8008780: 4801 ldr r0, [pc, #4] ; (8008788 <DMA1_Channel5_IRQHandler+0x8>)
  10102. 8008782: f7fd bab3 b.w 8005cec <HAL_DMA_IRQHandler>
  10103. 8008786: bf00 nop
  10104. 8008788: 20000680 .word 0x20000680
  10105. 0800878c <USART1_IRQHandler>:
  10106. void USART1_IRQHandler(void)
  10107. {
  10108. /* USER CODE BEGIN USART1_IRQn 0 */
  10109. /* USER CODE END USART1_IRQn 0 */
  10110. HAL_UART_IRQHandler(&huart1);
  10111. 800878c: 4801 ldr r0, [pc, #4] ; (8008794 <USART1_IRQHandler+0x8>)
  10112. 800878e: f7fe bcf5 b.w 800717c <HAL_UART_IRQHandler>
  10113. 8008792: bf00 nop
  10114. 8008794: 200006c4 .word 0x200006c4
  10115. 08008798 <TIM6_IRQHandler>:
  10116. void TIM6_IRQHandler(void)
  10117. {
  10118. /* USER CODE BEGIN TIM6_IRQn 0 */
  10119. /* USER CODE END TIM6_IRQn 0 */
  10120. HAL_TIM_IRQHandler(&htim6);
  10121. 8008798: 4801 ldr r0, [pc, #4] ; (80087a0 <TIM6_IRQHandler+0x8>)
  10122. 800879a: f7fe b93d b.w 8006a18 <HAL_TIM_IRQHandler>
  10123. 800879e: bf00 nop
  10124. 80087a0: 20000748 .word 0x20000748
  10125. 080087a4 <_read>:
  10126. _kill(status, -1);
  10127. while (1) {} /* Make sure we hang here */
  10128. }
  10129. __attribute__((weak)) int _read(int file, char *ptr, int len)
  10130. {
  10131. 80087a4: b570 push {r4, r5, r6, lr}
  10132. 80087a6: 460e mov r6, r1
  10133. 80087a8: 4615 mov r5, r2
  10134. int DataIdx;
  10135. for (DataIdx = 0; DataIdx < len; DataIdx++)
  10136. 80087aa: 460c mov r4, r1
  10137. 80087ac: 1ba3 subs r3, r4, r6
  10138. 80087ae: 429d cmp r5, r3
  10139. 80087b0: dc01 bgt.n 80087b6 <_read+0x12>
  10140. {
  10141. *ptr++ = __io_getchar();
  10142. }
  10143. return len;
  10144. }
  10145. 80087b2: 4628 mov r0, r5
  10146. 80087b4: bd70 pop {r4, r5, r6, pc}
  10147. *ptr++ = __io_getchar();
  10148. 80087b6: f3af 8000 nop.w
  10149. 80087ba: f804 0b01 strb.w r0, [r4], #1
  10150. 80087be: e7f5 b.n 80087ac <_read+0x8>
  10151. 080087c0 <_sbrk>:
  10152. }
  10153. return len;
  10154. }
  10155. caddr_t _sbrk(int incr)
  10156. {
  10157. 80087c0: b508 push {r3, lr}
  10158. extern char end asm("end");
  10159. static char *heap_end;
  10160. char *prev_heap_end;
  10161. if (heap_end == 0)
  10162. 80087c2: 4b0a ldr r3, [pc, #40] ; (80087ec <_sbrk+0x2c>)
  10163. {
  10164. 80087c4: 4602 mov r2, r0
  10165. if (heap_end == 0)
  10166. 80087c6: 6819 ldr r1, [r3, #0]
  10167. 80087c8: b909 cbnz r1, 80087ce <_sbrk+0xe>
  10168. heap_end = &end;
  10169. 80087ca: 4909 ldr r1, [pc, #36] ; (80087f0 <_sbrk+0x30>)
  10170. 80087cc: 6019 str r1, [r3, #0]
  10171. prev_heap_end = heap_end;
  10172. if (heap_end + incr > stack_ptr)
  10173. 80087ce: 4669 mov r1, sp
  10174. prev_heap_end = heap_end;
  10175. 80087d0: 6818 ldr r0, [r3, #0]
  10176. if (heap_end + incr > stack_ptr)
  10177. 80087d2: 4402 add r2, r0
  10178. 80087d4: 428a cmp r2, r1
  10179. 80087d6: d906 bls.n 80087e6 <_sbrk+0x26>
  10180. {
  10181. // write(1, "Heap and stack collision\n", 25);
  10182. // abort();
  10183. errno = ENOMEM;
  10184. 80087d8: f000 fd8e bl 80092f8 <__errno>
  10185. 80087dc: 230c movs r3, #12
  10186. 80087de: 6003 str r3, [r0, #0]
  10187. return (caddr_t) -1;
  10188. 80087e0: f04f 30ff mov.w r0, #4294967295
  10189. 80087e4: bd08 pop {r3, pc}
  10190. }
  10191. heap_end += incr;
  10192. 80087e6: 601a str r2, [r3, #0]
  10193. return (caddr_t) prev_heap_end;
  10194. }
  10195. 80087e8: bd08 pop {r3, pc}
  10196. 80087ea: bf00 nop
  10197. 80087ec: 20000448 .word 0x20000448
  10198. 80087f0: 200017a8 .word 0x200017a8
  10199. 080087f4 <_close>:
  10200. int _close(int file)
  10201. {
  10202. return -1;
  10203. }
  10204. 80087f4: f04f 30ff mov.w r0, #4294967295
  10205. 80087f8: 4770 bx lr
  10206. 080087fa <_fstat>:
  10207. int _fstat(int file, struct stat *st)
  10208. {
  10209. st->st_mode = S_IFCHR;
  10210. 80087fa: f44f 5300 mov.w r3, #8192 ; 0x2000
  10211. return 0;
  10212. }
  10213. 80087fe: 2000 movs r0, #0
  10214. st->st_mode = S_IFCHR;
  10215. 8008800: 604b str r3, [r1, #4]
  10216. }
  10217. 8008802: 4770 bx lr
  10218. 08008804 <_isatty>:
  10219. int _isatty(int file)
  10220. {
  10221. return 1;
  10222. }
  10223. 8008804: 2001 movs r0, #1
  10224. 8008806: 4770 bx lr
  10225. 08008808 <_lseek>:
  10226. int _lseek(int file, int ptr, int dir)
  10227. {
  10228. return 0;
  10229. }
  10230. 8008808: 2000 movs r0, #0
  10231. 800880a: 4770 bx lr
  10232. 0800880c <SystemInit>:
  10233. */
  10234. void SystemInit (void)
  10235. {
  10236. /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
  10237. /* Set HSION bit */
  10238. RCC->CR |= 0x00000001U;
  10239. 800880c: 4b0e ldr r3, [pc, #56] ; (8008848 <SystemInit+0x3c>)
  10240. 800880e: 681a ldr r2, [r3, #0]
  10241. 8008810: f042 0201 orr.w r2, r2, #1
  10242. 8008814: 601a str r2, [r3, #0]
  10243. /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
  10244. #if !defined(STM32F105xC) && !defined(STM32F107xC)
  10245. RCC->CFGR &= 0xF8FF0000U;
  10246. 8008816: 6859 ldr r1, [r3, #4]
  10247. 8008818: 4a0c ldr r2, [pc, #48] ; (800884c <SystemInit+0x40>)
  10248. 800881a: 400a ands r2, r1
  10249. 800881c: 605a str r2, [r3, #4]
  10250. #else
  10251. RCC->CFGR &= 0xF0FF0000U;
  10252. #endif /* STM32F105xC */
  10253. /* Reset HSEON, CSSON and PLLON bits */
  10254. RCC->CR &= 0xFEF6FFFFU;
  10255. 800881e: 681a ldr r2, [r3, #0]
  10256. 8008820: f022 7284 bic.w r2, r2, #17301504 ; 0x1080000
  10257. 8008824: f422 3280 bic.w r2, r2, #65536 ; 0x10000
  10258. 8008828: 601a str r2, [r3, #0]
  10259. /* Reset HSEBYP bit */
  10260. RCC->CR &= 0xFFFBFFFFU;
  10261. 800882a: 681a ldr r2, [r3, #0]
  10262. 800882c: f422 2280 bic.w r2, r2, #262144 ; 0x40000
  10263. 8008830: 601a str r2, [r3, #0]
  10264. /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
  10265. RCC->CFGR &= 0xFF80FFFFU;
  10266. 8008832: 685a ldr r2, [r3, #4]
  10267. 8008834: f422 02fe bic.w r2, r2, #8323072 ; 0x7f0000
  10268. 8008838: 605a str r2, [r3, #4]
  10269. /* Reset CFGR2 register */
  10270. RCC->CFGR2 = 0x00000000U;
  10271. #else
  10272. /* Disable all interrupts and clear pending bits */
  10273. RCC->CIR = 0x009F0000U;
  10274. 800883a: f44f 021f mov.w r2, #10420224 ; 0x9f0000
  10275. 800883e: 609a str r2, [r3, #8]
  10276. #endif
  10277. #ifdef VECT_TAB_SRAM
  10278. SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
  10279. #else
  10280. SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
  10281. 8008840: 4a03 ldr r2, [pc, #12] ; (8008850 <SystemInit+0x44>)
  10282. 8008842: 4b04 ldr r3, [pc, #16] ; (8008854 <SystemInit+0x48>)
  10283. 8008844: 609a str r2, [r3, #8]
  10284. 8008846: 4770 bx lr
  10285. 8008848: 40021000 .word 0x40021000
  10286. 800884c: f8ff0000 .word 0xf8ff0000
  10287. 8008850: 08004000 .word 0x08004000
  10288. 8008854: e000ed00 .word 0xe000ed00
  10289. 08008858 <InitUartQueue>:
  10290. UARTQUEUE WifiQueue;
  10291. uart_hal_tx_type uart_hal_tx;
  10292. void InitUartQueue(pUARTQUEUE pQueue)
  10293. {
  10294. setbuf(stdout, NULL);
  10295. 8008858: 4b0b ldr r3, [pc, #44] ; (8008888 <InitUartQueue+0x30>)
  10296. {
  10297. 800885a: b510 push {r4, lr}
  10298. setbuf(stdout, NULL);
  10299. 800885c: 681b ldr r3, [r3, #0]
  10300. {
  10301. 800885e: 4604 mov r4, r0
  10302. setbuf(stdout, NULL);
  10303. 8008860: 2100 movs r1, #0
  10304. 8008862: 6898 ldr r0, [r3, #8]
  10305. 8008864: f001 fa62 bl 8009d2c <setbuf>
  10306. pQueue->data = pQueue->head = pQueue->tail = 0;
  10307. 8008868: 2300 movs r3, #0
  10308. uart_hal_tx.output_p = uart_hal_tx.input_p = 0;
  10309. 800886a: 4a08 ldr r2, [pc, #32] ; (800888c <InitUartQueue+0x34>)
  10310. pQueue->data = pQueue->head = pQueue->tail = 0;
  10311. 800886c: 6063 str r3, [r4, #4]
  10312. 800886e: 6023 str r3, [r4, #0]
  10313. 8008870: 60a3 str r3, [r4, #8]
  10314. if (HAL_UART_Receive_DMA(&hTerminal, TerminalQueue.Buffer, 1) != HAL_OK)
  10315. 8008872: 4907 ldr r1, [pc, #28] ; (8008890 <InitUartQueue+0x38>)
  10316. uart_hal_tx.output_p = uart_hal_tx.input_p = 0;
  10317. 8008874: f8a2 3400 strh.w r3, [r2, #1024] ; 0x400
  10318. if (HAL_UART_Receive_DMA(&hTerminal, TerminalQueue.Buffer, 1) != HAL_OK)
  10319. 8008878: 4806 ldr r0, [pc, #24] ; (8008894 <InitUartQueue+0x3c>)
  10320. uart_hal_tx.output_p = uart_hal_tx.input_p = 0;
  10321. 800887a: f8a2 3402 strh.w r3, [r2, #1026] ; 0x402
  10322. {
  10323. //_Error_Handler(__FILE__, __LINE__);
  10324. }
  10325. //HAL_UART_Receive_DMA(&hTerminal, TerminalQueue.Buffer, 1);
  10326. //HAL_UART_Receive_IT(hTerminal, pQueue->Buffer + pQueue->head, 1);
  10327. }
  10328. 800887e: e8bd 4010 ldmia.w sp!, {r4, lr}
  10329. if (HAL_UART_Receive_DMA(&hTerminal, TerminalQueue.Buffer, 1) != HAL_OK)
  10330. 8008882: 2201 movs r2, #1
  10331. 8008884: f7fe bb8c b.w 8006fa0 <HAL_UART_Receive_DMA>
  10332. 8008888: 20000234 .word 0x20000234
  10333. 800888c: 20000f94 .word 0x20000f94
  10334. 8008890: 20000b94 .word 0x20000b94
  10335. 8008894: 200006c4 .word 0x200006c4
  10336. 08008898 <GetDataFromUartQueue>:
  10337. pUARTQUEUE pQueue = &TerminalQueue;
  10338. // if (HAL_UART_Transmit(dst, pQueue->Buffer + pQueue->tail, 1, 3000) != HAL_OK)
  10339. // {
  10340. // _Error_Handler(__FILE__, __LINE__);
  10341. // }
  10342. uart_buf[cnt++] = *(pQueue->Buffer + pQueue->tail);
  10343. 8008898: 4a14 ldr r2, [pc, #80] ; (80088ec <GetDataFromUartQueue+0x54>)
  10344. {
  10345. 800889a: b538 push {r3, r4, r5, lr}
  10346. uart_buf[cnt++] = *(pQueue->Buffer + pQueue->tail);
  10347. 800889c: 6810 ldr r0, [r2, #0]
  10348. 800889e: 1c43 adds r3, r0, #1
  10349. 80088a0: 6013 str r3, [r2, #0]
  10350. 80088a2: 4b13 ldr r3, [pc, #76] ; (80088f0 <GetDataFromUartQueue+0x58>)
  10351. 80088a4: 6859 ldr r1, [r3, #4]
  10352. 80088a6: f103 040c add.w r4, r3, #12
  10353. 80088aa: 5d0d ldrb r5, [r1, r4]
  10354. 80088ac: 4c11 ldr r4, [pc, #68] ; (80088f4 <GetDataFromUartQueue+0x5c>)
  10355. #ifdef DEBUG_PRINT
  10356. printf("%02x ",*(pQueue->Buffer + pQueue->tail)) ;
  10357. #endif /* DEBUG_PRINT */
  10358. pQueue->tail++;
  10359. 80088ae: 3101 adds r1, #1
  10360. if (pQueue->tail >= QUEUE_BUFFER_LENGTH) pQueue->tail = 0;
  10361. 80088b0: f5b1 6f80 cmp.w r1, #1024 ; 0x400
  10362. uart_buf[cnt++] = *(pQueue->Buffer + pQueue->tail);
  10363. 80088b4: 5425 strb r5, [r4, r0]
  10364. 80088b6: 4614 mov r4, r2
  10365. if (pQueue->tail >= QUEUE_BUFFER_LENGTH) pQueue->tail = 0;
  10366. 80088b8: bfa8 it ge
  10367. 80088ba: 2200 movge r2, #0
  10368. pQueue->data--;
  10369. 80088bc: 689d ldr r5, [r3, #8]
  10370. pQueue->tail++;
  10371. 80088be: bfb8 it lt
  10372. 80088c0: 6059 strlt r1, [r3, #4]
  10373. pQueue->data--;
  10374. 80088c2: f105 35ff add.w r5, r5, #4294967295
  10375. if (pQueue->tail >= QUEUE_BUFFER_LENGTH) pQueue->tail = 0;
  10376. 80088c6: bfa8 it ge
  10377. 80088c8: 605a strge r2, [r3, #4]
  10378. pQueue->data--;
  10379. 80088ca: 609d str r5, [r3, #8]
  10380. if(pQueue->data == 0){
  10381. 80088cc: b96d cbnz r5, 80088ea <GetDataFromUartQueue+0x52>
  10382. // printf("data cnt zero !!! \r\n");
  10383. RF_Ctrl_Main(&uart_buf[Header]);
  10384. 80088ce: 4809 ldr r0, [pc, #36] ; (80088f4 <GetDataFromUartQueue+0x5c>)
  10385. 80088d0: f000 fc9e bl 8009210 <RF_Ctrl_Main>
  10386. #if 0 // PYJ.2019.07.15_BEGIN --
  10387. for(int i = 0; i < cnt; i++){
  10388. printf("%02x ",uart_buf[i]);
  10389. }
  10390. #endif // PYJ.2019.07.15_END --
  10391. memset(uart_buf,0x00,cnt);
  10392. 80088d4: 6822 ldr r2, [r4, #0]
  10393. 80088d6: 4629 mov r1, r5
  10394. 80088d8: 4806 ldr r0, [pc, #24] ; (80088f4 <GetDataFromUartQueue+0x5c>)
  10395. 80088da: f000 fd42 bl 8009362 <memset>
  10396. // for(int i = 0; i < cnt; i++)
  10397. // uart_buf[i] = 0;
  10398. cnt = 0;
  10399. 80088de: 6025 str r5, [r4, #0]
  10400. HAL_Delay(1);
  10401. 80088e0: 2001 movs r0, #1
  10402. }
  10403. }
  10404. 80088e2: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
  10405. HAL_Delay(1);
  10406. 80088e6: f7fc be01 b.w 80054ec <HAL_Delay>
  10407. 80088ea: bd38 pop {r3, r4, r5, pc}
  10408. 80088ec: 2000044c .word 0x2000044c
  10409. 80088f0: 20000b88 .word 0x20000b88
  10410. 80088f4: 20000788 .word 0x20000788
  10411. 080088f8 <HAL_UART_RxCpltCallback>:
  10412. AdcTimerCnt = UartRxTimerCnt = 0;
  10413. 80088f8: 2300 movs r3, #0
  10414. 80088fa: 4a0f ldr r2, [pc, #60] ; (8008938 <HAL_UART_RxCpltCallback+0x40>)
  10415. {
  10416. 80088fc: b510 push {r4, lr}
  10417. AdcTimerCnt = UartRxTimerCnt = 0;
  10418. 80088fe: 6013 str r3, [r2, #0]
  10419. pQueue->head++;
  10420. 8008900: 4c0e ldr r4, [pc, #56] ; (800893c <HAL_UART_RxCpltCallback+0x44>)
  10421. AdcTimerCnt = UartRxTimerCnt = 0;
  10422. 8008902: 4a0f ldr r2, [pc, #60] ; (8008940 <HAL_UART_RxCpltCallback+0x48>)
  10423. 8008904: 6013 str r3, [r2, #0]
  10424. pQueue->head++;
  10425. 8008906: 6822 ldr r2, [r4, #0]
  10426. 8008908: 3201 adds r2, #1
  10427. 800890a: f5b2 6f80 cmp.w r2, #1024 ; 0x400
  10428. 800890e: bfb8 it lt
  10429. 8008910: 4613 movlt r3, r2
  10430. 8008912: 6023 str r3, [r4, #0]
  10431. pQueue->data++;
  10432. 8008914: 68a3 ldr r3, [r4, #8]
  10433. 8008916: 3301 adds r3, #1
  10434. if (pQueue->data >= QUEUE_BUFFER_LENGTH)
  10435. 8008918: f5b3 6f80 cmp.w r3, #1024 ; 0x400
  10436. pQueue->data++;
  10437. 800891c: 60a3 str r3, [r4, #8]
  10438. if (pQueue->data >= QUEUE_BUFFER_LENGTH)
  10439. 800891e: db01 blt.n 8008924 <HAL_UART_RxCpltCallback+0x2c>
  10440. GetDataFromUartQueue(huart);
  10441. 8008920: f7ff ffba bl 8008898 <GetDataFromUartQueue>
  10442. HAL_UART_Receive_DMA(&hTerminal, pQueue->Buffer + pQueue->head, 1);
  10443. 8008924: 6823 ldr r3, [r4, #0]
  10444. 8008926: 4907 ldr r1, [pc, #28] ; (8008944 <HAL_UART_RxCpltCallback+0x4c>)
  10445. 8008928: 2201 movs r2, #1
  10446. }
  10447. 800892a: e8bd 4010 ldmia.w sp!, {r4, lr}
  10448. HAL_UART_Receive_DMA(&hTerminal, pQueue->Buffer + pQueue->head, 1);
  10449. 800892e: 4419 add r1, r3
  10450. 8008930: 4805 ldr r0, [pc, #20] ; (8008948 <HAL_UART_RxCpltCallback+0x50>)
  10451. 8008932: f7fe bb35 b.w 8006fa0 <HAL_UART_Receive_DMA>
  10452. 8008936: bf00 nop
  10453. 8008938: 20000444 .word 0x20000444
  10454. 800893c: 20000b88 .word 0x20000b88
  10455. 8008940: 20000438 .word 0x20000438
  10456. 8008944: 20000b94 .word 0x20000b94
  10457. 8008948: 200006c4 .word 0x200006c4
  10458. 0800894c <RF_Data_Check>:
  10459. PATH_EN_2_1G_UL_GPIO_Port,
  10460. PATH_EN_2_1G_UL_Pin,
  10461. };
  10462. bool RF_Data_Check(uint8_t* data_buf){
  10463. 800894c: b508 push {r3, lr}
  10464. bool ret = false;
  10465. bool crcret = STH30_CheckCrc(&data_buf[Type], data_buf[Length], data_buf[data_buf[Crcindex]]);
  10466. 800894e: 78c3 ldrb r3, [r0, #3]
  10467. 8008950: 7881 ldrb r1, [r0, #2]
  10468. 8008952: 5cc2 ldrb r2, [r0, r3]
  10469. 8008954: 3001 adds r0, #1
  10470. 8008956: f7fe fd7f bl 8007458 <STH30_CheckCrc>
  10471. // printf("Recv CRC Value : \"%d\"\r\n Create CRC Value : \"%d\" \r\n",data_buf[data_buf[Crcindex]],STH30_CreateCrc(&data_buf[Type], data_buf[Length]));
  10472. }
  10473. // printf("CRC Result : \"%d\" \r\n",ret);
  10474. return ret;
  10475. }
  10476. 800895a: 3000 adds r0, #0
  10477. 800895c: bf18 it ne
  10478. 800895e: 2001 movne r0, #1
  10479. 8008960: bd08 pop {r3, pc}
  10480. ...
  10481. 08008964 <RF_Status_Get>:
  10482. PLL_EN_3_5G_L_GPIO_Port,
  10483. PLL_EN_3_5G_L_Pin,
  10484. };
  10485. void RF_Status_Get(void){
  10486. // printf("\r\nYJ2 : Prev_data[INDEX_DET_1_8G_DL_IN_L ] : %x\r\n",Prev_data[INDEX_DET_1_8G_DL_IN_L]);
  10487. Prev_data[INDEX_BLUE_HEADER] = BLUECELL_HEADER;
  10488. 8008964: 23be movs r3, #190 ; 0xbe
  10489. void RF_Status_Get(void){
  10490. 8008966: b510 push {r4, lr}
  10491. Prev_data[INDEX_BLUE_HEADER] = BLUECELL_HEADER;
  10492. 8008968: 4c0b ldr r4, [pc, #44] ; (8008998 <RF_Status_Get+0x34>)
  10493. Prev_data[INDEX_BLUE_TYPE] = TYPE_BLUECELL_GET;
  10494. Prev_data[INDEX_BLUE_LENGTH] = INDEX_BLUE_EOF - 2;
  10495. 800896a: 215d movs r1, #93 ; 0x5d
  10496. Prev_data[INDEX_BLUE_HEADER] = BLUECELL_HEADER;
  10497. 800896c: 7023 strb r3, [r4, #0]
  10498. Prev_data[INDEX_BLUE_TYPE] = TYPE_BLUECELL_GET;
  10499. 800896e: 2302 movs r3, #2
  10500. 8008970: 7063 strb r3, [r4, #1]
  10501. Prev_data[INDEX_BLUE_CRCINDEX] = INDEX_BLUE_CRC;
  10502. 8008972: 235e movs r3, #94 ; 0x5e
  10503. Prev_data[INDEX_BLUE_CRC] = STH30_CreateCrc(&Prev_data[Type], Prev_data[Length]);
  10504. 8008974: 1c60 adds r0, r4, #1
  10505. Prev_data[INDEX_BLUE_LENGTH] = INDEX_BLUE_EOF - 2;
  10506. 8008976: 70a1 strb r1, [r4, #2]
  10507. Prev_data[INDEX_BLUE_CRCINDEX] = INDEX_BLUE_CRC;
  10508. 8008978: 70e3 strb r3, [r4, #3]
  10509. Prev_data[INDEX_BLUE_CRC] = STH30_CreateCrc(&Prev_data[Type], Prev_data[Length]);
  10510. 800897a: f7fe fd52 bl 8007422 <STH30_CreateCrc>
  10511. Prev_data[INDEX_BLUE_EOF] = BLUECELL_TAILER;
  10512. 800897e: 23eb movs r3, #235 ; 0xeb
  10513. Prev_data[INDEX_BLUE_CRC] = STH30_CreateCrc(&Prev_data[Type], Prev_data[Length]);
  10514. 8008980: f884 005e strb.w r0, [r4, #94] ; 0x5e
  10515. Prev_data[INDEX_BLUE_EOF] = BLUECELL_TAILER;
  10516. 8008984: f884 305f strb.w r3, [r4, #95] ; 0x5f
  10517. HAL_UART_Transmit_DMA(&huart1,&Prev_data[INDEX_BLUE_HEADER],INDEX_BLUE_EOF + 1);
  10518. 8008988: 4621 mov r1, r4
  10519. // printf("\r\nYJ : %x",ADCvalue[0]);
  10520. // printf("\r\n");
  10521. }
  10522. 800898a: e8bd 4010 ldmia.w sp!, {r4, lr}
  10523. HAL_UART_Transmit_DMA(&huart1,&Prev_data[INDEX_BLUE_HEADER],INDEX_BLUE_EOF + 1);
  10524. 800898e: 2260 movs r2, #96 ; 0x60
  10525. 8008990: 4802 ldr r0, [pc, #8] ; (800899c <RF_Status_Get+0x38>)
  10526. 8008992: f7fe bacb b.w 8006f2c <HAL_UART_Transmit_DMA>
  10527. 8008996: bf00 nop
  10528. 8008998: 20000574 .word 0x20000574
  10529. 800899c: 200006c4 .word 0x200006c4
  10530. 080089a0 <RF_Status_Ack>:
  10531. static uint8_t Ack_Buf[6];
  10532. void RF_Status_Ack(void){
  10533. // printf("\r\nYJ2 : Prev_data[INDEX_DET_1_8G_DL_IN_L ] : %x\r\n",Prev_data[INDEX_DET_1_8G_DL_IN_L]);
  10534. Ack_Buf[INDEX_BLUE_HEADER] = BLUECELL_HEADER;
  10535. 80089a0: 23be movs r3, #190 ; 0xbe
  10536. void RF_Status_Ack(void){
  10537. 80089a2: b510 push {r4, lr}
  10538. Ack_Buf[INDEX_BLUE_HEADER] = BLUECELL_HEADER;
  10539. 80089a4: 4c0a ldr r4, [pc, #40] ; (80089d0 <RF_Status_Ack+0x30>)
  10540. Ack_Buf[INDEX_BLUE_TYPE] = TYPE_BLUECELL_ACK;
  10541. Ack_Buf[INDEX_BLUE_LENGTH] = 3;
  10542. 80089a6: 2103 movs r1, #3
  10543. Ack_Buf[INDEX_BLUE_HEADER] = BLUECELL_HEADER;
  10544. 80089a8: 7023 strb r3, [r4, #0]
  10545. Ack_Buf[INDEX_BLUE_TYPE] = TYPE_BLUECELL_ACK;
  10546. 80089aa: 2304 movs r3, #4
  10547. Ack_Buf[INDEX_BLUE_CRCINDEX + 0] = INDEX_BLUE_CRCINDEX + 1;
  10548. Ack_Buf[INDEX_BLUE_CRCINDEX + 1] = STH30_CreateCrc(&Ack_Buf[Type], Ack_Buf[Length]);
  10549. 80089ac: 1c60 adds r0, r4, #1
  10550. Ack_Buf[INDEX_BLUE_TYPE] = TYPE_BLUECELL_ACK;
  10551. 80089ae: 7063 strb r3, [r4, #1]
  10552. Ack_Buf[INDEX_BLUE_LENGTH] = 3;
  10553. 80089b0: 70a1 strb r1, [r4, #2]
  10554. Ack_Buf[INDEX_BLUE_CRCINDEX + 0] = INDEX_BLUE_CRCINDEX + 1;
  10555. 80089b2: 70e3 strb r3, [r4, #3]
  10556. Ack_Buf[INDEX_BLUE_CRCINDEX + 1] = STH30_CreateCrc(&Ack_Buf[Type], Ack_Buf[Length]);
  10557. 80089b4: f7fe fd35 bl 8007422 <STH30_CreateCrc>
  10558. Ack_Buf[INDEX_BLUE_CRCINDEX + 2] = BLUECELL_TAILER;
  10559. 80089b8: 23eb movs r3, #235 ; 0xeb
  10560. HAL_UART_Transmit_DMA(&huart1,&Ack_Buf[INDEX_BLUE_HEADER],Ack_Buf[INDEX_BLUE_LENGTH] + 3);
  10561. 80089ba: 78a2 ldrb r2, [r4, #2]
  10562. Ack_Buf[INDEX_BLUE_CRCINDEX + 1] = STH30_CreateCrc(&Ack_Buf[Type], Ack_Buf[Length]);
  10563. 80089bc: 7120 strb r0, [r4, #4]
  10564. Ack_Buf[INDEX_BLUE_CRCINDEX + 2] = BLUECELL_TAILER;
  10565. 80089be: 7163 strb r3, [r4, #5]
  10566. HAL_UART_Transmit_DMA(&huart1,&Ack_Buf[INDEX_BLUE_HEADER],Ack_Buf[INDEX_BLUE_LENGTH] + 3);
  10567. 80089c0: 4621 mov r1, r4
  10568. // printf("\r\nYJ : %x",ADCvalue[0]);
  10569. // printf("\r\n");
  10570. }
  10571. 80089c2: e8bd 4010 ldmia.w sp!, {r4, lr}
  10572. HAL_UART_Transmit_DMA(&huart1,&Ack_Buf[INDEX_BLUE_HEADER],Ack_Buf[INDEX_BLUE_LENGTH] + 3);
  10573. 80089c6: 3203 adds r2, #3
  10574. 80089c8: 4802 ldr r0, [pc, #8] ; (80089d4 <RF_Status_Ack+0x34>)
  10575. 80089ca: f7fe baaf b.w 8006f2c <HAL_UART_Transmit_DMA>
  10576. 80089ce: bf00 nop
  10577. 80089d0: 20000450 .word 0x20000450
  10578. 80089d4: 200006c4 .word 0x200006c4
  10579. 080089d8 <RF_Operate>:
  10580. void RF_Operate(uint8_t* data_buf){
  10581. 80089d8: b570 push {r4, r5, r6, lr}
  10582. uint16_t temp_val = 0;
  10583. uint8_t ADC_Modify = 0;
  10584. ADF4153_R_N_Reg_st temp_reg;
  10585. // printf("Prev_data[INDEX_ATT_1_8G_DL1] : %x data_buf[INDEX_ATT_1_8G_DL1] : %x\r\n",Prev_data[INDEX_ATT_1_8G_DL1],data_buf[INDEX_ATT_1_8G_DL1]);
  10586. if(Prev_data[INDEX_ATT_1_8G_DL1] != data_buf[INDEX_ATT_1_8G_DL1]){
  10587. 80089da: 4db1 ldr r5, [pc, #708] ; (8008ca0 <RF_Operate+0x2c8>)
  10588. 80089dc: 7902 ldrb r2, [r0, #4]
  10589. 80089de: 792b ldrb r3, [r5, #4]
  10590. void RF_Operate(uint8_t* data_buf){
  10591. 80089e0: b0a2 sub sp, #136 ; 0x88
  10592. if(Prev_data[INDEX_ATT_1_8G_DL1] != data_buf[INDEX_ATT_1_8G_DL1]){
  10593. 80089e2: 4293 cmp r3, r2
  10594. void RF_Operate(uint8_t* data_buf){
  10595. 80089e4: 4604 mov r4, r0
  10596. if(Prev_data[INDEX_ATT_1_8G_DL1] != data_buf[INDEX_ATT_1_8G_DL1]){
  10597. 80089e6: d00c beq.n 8008a02 <RF_Operate+0x2a>
  10598. BDA4601_atten_ctrl(BDA4601_1_8G_DL1,(data_buf[INDEX_ATT_1_8G_DL1]));
  10599. 80089e8: 4bae ldr r3, [pc, #696] ; (8008ca4 <RF_Operate+0x2cc>)
  10600. 80089ea: 9202 str r2, [sp, #8]
  10601. 80089ec: f103 0210 add.w r2, r3, #16
  10602. 80089f0: e892 0003 ldmia.w r2, {r0, r1}
  10603. 80089f4: e88d 0003 stmia.w sp, {r0, r1}
  10604. 80089f8: cb0f ldmia r3, {r0, r1, r2, r3}
  10605. 80089fa: f7fe fcb9 bl 8007370 <BDA4601_atten_ctrl>
  10606. Prev_data[INDEX_ATT_1_8G_DL1] = data_buf[INDEX_ATT_1_8G_DL1];
  10607. 80089fe: 7923 ldrb r3, [r4, #4]
  10608. 8008a00: 712b strb r3, [r5, #4]
  10609. }
  10610. if(Prev_data[INDEX_ATT_1_8G_DL2] != data_buf[INDEX_ATT_1_8G_DL2]){
  10611. 8008a02: 7962 ldrb r2, [r4, #5]
  10612. 8008a04: 796b ldrb r3, [r5, #5]
  10613. 8008a06: 4293 cmp r3, r2
  10614. 8008a08: d00c beq.n 8008a24 <RF_Operate+0x4c>
  10615. BDA4601_atten_ctrl(BDA4601_1_8G_DL2,(data_buf[INDEX_ATT_1_8G_DL2]));
  10616. 8008a0a: 4ba7 ldr r3, [pc, #668] ; (8008ca8 <RF_Operate+0x2d0>)
  10617. 8008a0c: 9202 str r2, [sp, #8]
  10618. 8008a0e: f103 0210 add.w r2, r3, #16
  10619. 8008a12: e892 0003 ldmia.w r2, {r0, r1}
  10620. 8008a16: e88d 0003 stmia.w sp, {r0, r1}
  10621. 8008a1a: cb0f ldmia r3, {r0, r1, r2, r3}
  10622. 8008a1c: f7fe fca8 bl 8007370 <BDA4601_atten_ctrl>
  10623. Prev_data[INDEX_ATT_1_8G_DL2] = data_buf[INDEX_ATT_1_8G_DL2];
  10624. 8008a20: 7963 ldrb r3, [r4, #5]
  10625. 8008a22: 716b strb r3, [r5, #5]
  10626. }
  10627. if(Prev_data[INDEX_ATT_1_8G_UL1] != data_buf[INDEX_ATT_1_8G_UL1]){
  10628. 8008a24: 79a2 ldrb r2, [r4, #6]
  10629. 8008a26: 79ab ldrb r3, [r5, #6]
  10630. 8008a28: 4293 cmp r3, r2
  10631. 8008a2a: d00c beq.n 8008a46 <RF_Operate+0x6e>
  10632. BDA4601_atten_ctrl(BDA4601_1_8G_UL1,(data_buf[INDEX_ATT_1_8G_UL1]));
  10633. 8008a2c: 4b9f ldr r3, [pc, #636] ; (8008cac <RF_Operate+0x2d4>)
  10634. 8008a2e: 9202 str r2, [sp, #8]
  10635. 8008a30: f103 0210 add.w r2, r3, #16
  10636. 8008a34: e892 0003 ldmia.w r2, {r0, r1}
  10637. 8008a38: e88d 0003 stmia.w sp, {r0, r1}
  10638. 8008a3c: cb0f ldmia r3, {r0, r1, r2, r3}
  10639. 8008a3e: f7fe fc97 bl 8007370 <BDA4601_atten_ctrl>
  10640. Prev_data[INDEX_ATT_1_8G_UL1] = data_buf[INDEX_ATT_1_8G_UL1];
  10641. 8008a42: 79a3 ldrb r3, [r4, #6]
  10642. 8008a44: 71ab strb r3, [r5, #6]
  10643. }
  10644. if(Prev_data[INDEX_ATT_1_8G_UL2] != data_buf[INDEX_ATT_1_8G_UL2]){
  10645. 8008a46: 79e2 ldrb r2, [r4, #7]
  10646. 8008a48: 79eb ldrb r3, [r5, #7]
  10647. 8008a4a: 4293 cmp r3, r2
  10648. 8008a4c: d00c beq.n 8008a68 <RF_Operate+0x90>
  10649. BDA4601_atten_ctrl(BDA4601_1_8G_UL2,(data_buf[INDEX_ATT_1_8G_UL2]));
  10650. 8008a4e: 4b98 ldr r3, [pc, #608] ; (8008cb0 <RF_Operate+0x2d8>)
  10651. 8008a50: 9202 str r2, [sp, #8]
  10652. 8008a52: f103 0210 add.w r2, r3, #16
  10653. 8008a56: e892 0003 ldmia.w r2, {r0, r1}
  10654. 8008a5a: e88d 0003 stmia.w sp, {r0, r1}
  10655. 8008a5e: cb0f ldmia r3, {r0, r1, r2, r3}
  10656. 8008a60: f7fe fc86 bl 8007370 <BDA4601_atten_ctrl>
  10657. Prev_data[INDEX_ATT_1_8G_UL2] = data_buf[INDEX_ATT_1_8G_UL2];
  10658. 8008a64: 79e3 ldrb r3, [r4, #7]
  10659. 8008a66: 71eb strb r3, [r5, #7]
  10660. }
  10661. if(Prev_data[INDEX_ATT_1_8G_UL3] != data_buf[INDEX_ATT_1_8G_UL3]){
  10662. 8008a68: 7a22 ldrb r2, [r4, #8]
  10663. 8008a6a: 7a2b ldrb r3, [r5, #8]
  10664. 8008a6c: 4293 cmp r3, r2
  10665. 8008a6e: d00c beq.n 8008a8a <RF_Operate+0xb2>
  10666. BDA4601_atten_ctrl(BDA4601_1_8G_UL3,(data_buf[INDEX_ATT_1_8G_UL3]));
  10667. 8008a70: 4b90 ldr r3, [pc, #576] ; (8008cb4 <RF_Operate+0x2dc>)
  10668. 8008a72: 9202 str r2, [sp, #8]
  10669. 8008a74: f103 0210 add.w r2, r3, #16
  10670. 8008a78: e892 0003 ldmia.w r2, {r0, r1}
  10671. 8008a7c: e88d 0003 stmia.w sp, {r0, r1}
  10672. 8008a80: cb0f ldmia r3, {r0, r1, r2, r3}
  10673. 8008a82: f7fe fc75 bl 8007370 <BDA4601_atten_ctrl>
  10674. Prev_data[INDEX_ATT_1_8G_UL3] = data_buf[INDEX_ATT_1_8G_UL3];
  10675. 8008a86: 7a23 ldrb r3, [r4, #8]
  10676. 8008a88: 722b strb r3, [r5, #8]
  10677. }
  10678. if(Prev_data[INDEX_ATT_1_8G_UL4] != data_buf[INDEX_ATT_1_8G_UL4]){
  10679. 8008a8a: 7a62 ldrb r2, [r4, #9]
  10680. 8008a8c: 7a6b ldrb r3, [r5, #9]
  10681. 8008a8e: 4293 cmp r3, r2
  10682. 8008a90: d00c beq.n 8008aac <RF_Operate+0xd4>
  10683. BDA4601_atten_ctrl(BDA4601_1_8G_UL4,(data_buf[INDEX_ATT_1_8G_UL4]));
  10684. 8008a92: 4b89 ldr r3, [pc, #548] ; (8008cb8 <RF_Operate+0x2e0>)
  10685. 8008a94: 9202 str r2, [sp, #8]
  10686. 8008a96: f103 0210 add.w r2, r3, #16
  10687. 8008a9a: e892 0003 ldmia.w r2, {r0, r1}
  10688. 8008a9e: e88d 0003 stmia.w sp, {r0, r1}
  10689. 8008aa2: cb0f ldmia r3, {r0, r1, r2, r3}
  10690. 8008aa4: f7fe fc64 bl 8007370 <BDA4601_atten_ctrl>
  10691. Prev_data[INDEX_ATT_1_8G_UL4] = data_buf[INDEX_ATT_1_8G_UL4];
  10692. 8008aa8: 7a63 ldrb r3, [r4, #9]
  10693. 8008aaa: 726b strb r3, [r5, #9]
  10694. }
  10695. if(Prev_data[INDEX_ATT_2_1G_DL1] != data_buf[INDEX_ATT_2_1G_DL1]){
  10696. 8008aac: 7aa2 ldrb r2, [r4, #10]
  10697. 8008aae: 7aab ldrb r3, [r5, #10]
  10698. 8008ab0: 4293 cmp r3, r2
  10699. 8008ab2: d00c beq.n 8008ace <RF_Operate+0xf6>
  10700. BDA4601_atten_ctrl(BDA4601_2_1G_DL1,(data_buf[INDEX_ATT_2_1G_DL1]));
  10701. 8008ab4: 4b81 ldr r3, [pc, #516] ; (8008cbc <RF_Operate+0x2e4>)
  10702. 8008ab6: 9202 str r2, [sp, #8]
  10703. 8008ab8: f103 0210 add.w r2, r3, #16
  10704. 8008abc: e892 0003 ldmia.w r2, {r0, r1}
  10705. 8008ac0: e88d 0003 stmia.w sp, {r0, r1}
  10706. 8008ac4: cb0f ldmia r3, {r0, r1, r2, r3}
  10707. 8008ac6: f7fe fc53 bl 8007370 <BDA4601_atten_ctrl>
  10708. Prev_data[INDEX_ATT_2_1G_DL1] = data_buf[INDEX_ATT_2_1G_DL1];
  10709. 8008aca: 7aa3 ldrb r3, [r4, #10]
  10710. 8008acc: 72ab strb r3, [r5, #10]
  10711. }
  10712. if(Prev_data[INDEX_ATT_2_1G_DL2] != data_buf[INDEX_ATT_2_1G_DL2]){
  10713. 8008ace: 7ae2 ldrb r2, [r4, #11]
  10714. 8008ad0: 7aeb ldrb r3, [r5, #11]
  10715. 8008ad2: 4293 cmp r3, r2
  10716. 8008ad4: d00c beq.n 8008af0 <RF_Operate+0x118>
  10717. BDA4601_atten_ctrl(BDA4601_2_1G_DL2,(data_buf[INDEX_ATT_2_1G_DL2]));
  10718. 8008ad6: 4b7a ldr r3, [pc, #488] ; (8008cc0 <RF_Operate+0x2e8>)
  10719. 8008ad8: 9202 str r2, [sp, #8]
  10720. 8008ada: f103 0210 add.w r2, r3, #16
  10721. 8008ade: e892 0003 ldmia.w r2, {r0, r1}
  10722. 8008ae2: e88d 0003 stmia.w sp, {r0, r1}
  10723. 8008ae6: cb0f ldmia r3, {r0, r1, r2, r3}
  10724. 8008ae8: f7fe fc42 bl 8007370 <BDA4601_atten_ctrl>
  10725. Prev_data[INDEX_ATT_2_1G_DL2] = data_buf[INDEX_ATT_2_1G_DL2];
  10726. 8008aec: 7ae3 ldrb r3, [r4, #11]
  10727. 8008aee: 72eb strb r3, [r5, #11]
  10728. }
  10729. if(Prev_data[INDEX_ATT_2_1G_UL1] != data_buf[INDEX_ATT_2_1G_UL1]){
  10730. 8008af0: 7b22 ldrb r2, [r4, #12]
  10731. 8008af2: 7b2b ldrb r3, [r5, #12]
  10732. 8008af4: 4293 cmp r3, r2
  10733. 8008af6: d00c beq.n 8008b12 <RF_Operate+0x13a>
  10734. BDA4601_atten_ctrl(BDA4601_2_1G_UL1,(data_buf[INDEX_ATT_2_1G_UL1]));
  10735. 8008af8: 4b72 ldr r3, [pc, #456] ; (8008cc4 <RF_Operate+0x2ec>)
  10736. 8008afa: 9202 str r2, [sp, #8]
  10737. 8008afc: f103 0210 add.w r2, r3, #16
  10738. 8008b00: e892 0003 ldmia.w r2, {r0, r1}
  10739. 8008b04: e88d 0003 stmia.w sp, {r0, r1}
  10740. 8008b08: cb0f ldmia r3, {r0, r1, r2, r3}
  10741. 8008b0a: f7fe fc31 bl 8007370 <BDA4601_atten_ctrl>
  10742. Prev_data[INDEX_ATT_2_1G_UL1] = data_buf[INDEX_ATT_2_1G_UL1];
  10743. 8008b0e: 7b23 ldrb r3, [r4, #12]
  10744. 8008b10: 732b strb r3, [r5, #12]
  10745. }
  10746. if(Prev_data[INDEX_ATT_2_1G_UL2] != data_buf[INDEX_ATT_2_1G_UL2]){
  10747. 8008b12: 7b62 ldrb r2, [r4, #13]
  10748. 8008b14: 7b6b ldrb r3, [r5, #13]
  10749. 8008b16: 4293 cmp r3, r2
  10750. 8008b18: d00c beq.n 8008b34 <RF_Operate+0x15c>
  10751. BDA4601_atten_ctrl(BDA4601_2_1G_UL2,(data_buf[INDEX_ATT_2_1G_UL2]));
  10752. 8008b1a: 4b6b ldr r3, [pc, #428] ; (8008cc8 <RF_Operate+0x2f0>)
  10753. 8008b1c: 9202 str r2, [sp, #8]
  10754. 8008b1e: f103 0210 add.w r2, r3, #16
  10755. 8008b22: e892 0003 ldmia.w r2, {r0, r1}
  10756. 8008b26: e88d 0003 stmia.w sp, {r0, r1}
  10757. 8008b2a: cb0f ldmia r3, {r0, r1, r2, r3}
  10758. 8008b2c: f7fe fc20 bl 8007370 <BDA4601_atten_ctrl>
  10759. Prev_data[INDEX_ATT_2_1G_UL2] = data_buf[INDEX_ATT_2_1G_UL2];
  10760. 8008b30: 7b63 ldrb r3, [r4, #13]
  10761. 8008b32: 736b strb r3, [r5, #13]
  10762. }
  10763. if(Prev_data[INDEX_ATT_2_1G_UL3] != data_buf[INDEX_ATT_2_1G_UL3]){
  10764. 8008b34: 7ba2 ldrb r2, [r4, #14]
  10765. 8008b36: 7bab ldrb r3, [r5, #14]
  10766. 8008b38: 4293 cmp r3, r2
  10767. 8008b3a: d00c beq.n 8008b56 <RF_Operate+0x17e>
  10768. BDA4601_atten_ctrl(BDA4601_2_1G_UL3,(data_buf[INDEX_ATT_2_1G_UL3]));
  10769. 8008b3c: 4b63 ldr r3, [pc, #396] ; (8008ccc <RF_Operate+0x2f4>)
  10770. 8008b3e: 9202 str r2, [sp, #8]
  10771. 8008b40: f103 0210 add.w r2, r3, #16
  10772. 8008b44: e892 0003 ldmia.w r2, {r0, r1}
  10773. 8008b48: e88d 0003 stmia.w sp, {r0, r1}
  10774. 8008b4c: cb0f ldmia r3, {r0, r1, r2, r3}
  10775. 8008b4e: f7fe fc0f bl 8007370 <BDA4601_atten_ctrl>
  10776. Prev_data[INDEX_ATT_2_1G_UL3] = data_buf[INDEX_ATT_2_1G_UL3];
  10777. 8008b52: 7ba3 ldrb r3, [r4, #14]
  10778. 8008b54: 73ab strb r3, [r5, #14]
  10779. }
  10780. if(Prev_data[INDEX_ATT_2_1G_UL4] != data_buf[INDEX_ATT_2_1G_UL4]){
  10781. 8008b56: 7be2 ldrb r2, [r4, #15]
  10782. 8008b58: 7beb ldrb r3, [r5, #15]
  10783. 8008b5a: 4293 cmp r3, r2
  10784. 8008b5c: d00c beq.n 8008b78 <RF_Operate+0x1a0>
  10785. BDA4601_atten_ctrl(BDA4601_2_1G_UL4,(data_buf[INDEX_ATT_2_1G_UL4]));
  10786. 8008b5e: 4b5c ldr r3, [pc, #368] ; (8008cd0 <RF_Operate+0x2f8>)
  10787. 8008b60: 9202 str r2, [sp, #8]
  10788. 8008b62: f103 0210 add.w r2, r3, #16
  10789. 8008b66: e892 0003 ldmia.w r2, {r0, r1}
  10790. 8008b6a: e88d 0003 stmia.w sp, {r0, r1}
  10791. 8008b6e: cb0f ldmia r3, {r0, r1, r2, r3}
  10792. 8008b70: f7fe fbfe bl 8007370 <BDA4601_atten_ctrl>
  10793. Prev_data[INDEX_ATT_2_1G_UL4] = data_buf[INDEX_ATT_2_1G_UL4];
  10794. 8008b74: 7be3 ldrb r3, [r4, #15]
  10795. 8008b76: 73eb strb r3, [r5, #15]
  10796. }
  10797. if( (Prev_data[INDEX_ATT_3_5G_LOW1] != data_buf[INDEX_ATT_3_5G_LOW1])
  10798. 8008b78: 7c23 ldrb r3, [r4, #16]
  10799. 8008b7a: 7c2a ldrb r2, [r5, #16]
  10800. 8008b7c: 429a cmp r2, r3
  10801. 8008b7e: d10f bne.n 8008ba0 <RF_Operate+0x1c8>
  10802. ||(Prev_data[INDEX_ATT_3_5G_UL] != data_buf[INDEX_ATT_3_5G_UL])
  10803. 8008b80: 7c69 ldrb r1, [r5, #17]
  10804. 8008b82: 7c62 ldrb r2, [r4, #17]
  10805. 8008b84: 4291 cmp r1, r2
  10806. 8008b86: d10b bne.n 8008ba0 <RF_Operate+0x1c8>
  10807. ||(Prev_data[INDEX_ATT_3_5G_COM1] != data_buf[INDEX_ATT_3_5G_COM1])
  10808. 8008b88: 7ca9 ldrb r1, [r5, #18]
  10809. 8008b8a: 7ca2 ldrb r2, [r4, #18]
  10810. 8008b8c: 4291 cmp r1, r2
  10811. 8008b8e: d107 bne.n 8008ba0 <RF_Operate+0x1c8>
  10812. ||(Prev_data[INDEX_ATT_3_5G_COM2] != data_buf[INDEX_ATT_3_5G_COM2])
  10813. 8008b90: 7ce9 ldrb r1, [r5, #19]
  10814. 8008b92: 7ce2 ldrb r2, [r4, #19]
  10815. 8008b94: 4291 cmp r1, r2
  10816. 8008b96: d103 bne.n 8008ba0 <RF_Operate+0x1c8>
  10817. ||(Prev_data[INDEX_ATT_3_5G_COM3] != data_buf[INDEX_ATT_3_5G_COM3])
  10818. 8008b98: 7d29 ldrb r1, [r5, #20]
  10819. 8008b9a: 7d22 ldrb r2, [r4, #20]
  10820. 8008b9c: 4291 cmp r1, r2
  10821. 8008b9e: d01c beq.n 8008bda <RF_Operate+0x202>
  10822. ){
  10823. ALL_ATT_3_5G.data0 = Prev_data[INDEX_ATT_3_5G_LOW1] = data_buf[INDEX_ATT_3_5G_LOW1];
  10824. 8008ba0: 4e4c ldr r6, [pc, #304] ; (8008cd4 <RF_Operate+0x2fc>)
  10825. 8008ba2: 742b strb r3, [r5, #16]
  10826. 8008ba4: 7633 strb r3, [r6, #24]
  10827. ALL_ATT_3_5G.data1 = Prev_data[INDEX_ATT_3_5G_UL] = data_buf[INDEX_ATT_3_5G_UL];
  10828. 8008ba6: 7c63 ldrb r3, [r4, #17]
  10829. ALL_ATT_3_5G.data2 = Prev_data[INDEX_ATT_3_5G_COM1] = data_buf[INDEX_ATT_3_5G_COM1];
  10830. ALL_ATT_3_5G.data3 = Prev_data[INDEX_ATT_3_5G_COM2] = data_buf[INDEX_ATT_3_5G_COM2];
  10831. ALL_ATT_3_5G.data4 = Prev_data[INDEX_ATT_3_5G_COM3] = data_buf[INDEX_ATT_3_5G_COM3];
  10832. PE43711_ALL_atten_ctrl(ALL_ATT_3_5G);
  10833. 8008ba8: 227c movs r2, #124 ; 0x7c
  10834. ALL_ATT_3_5G.data1 = Prev_data[INDEX_ATT_3_5G_UL] = data_buf[INDEX_ATT_3_5G_UL];
  10835. 8008baa: 746b strb r3, [r5, #17]
  10836. 8008bac: f886 3034 strb.w r3, [r6, #52] ; 0x34
  10837. ALL_ATT_3_5G.data2 = Prev_data[INDEX_ATT_3_5G_COM1] = data_buf[INDEX_ATT_3_5G_COM1];
  10838. 8008bb0: 7ca3 ldrb r3, [r4, #18]
  10839. PE43711_ALL_atten_ctrl(ALL_ATT_3_5G);
  10840. 8008bb2: f106 0110 add.w r1, r6, #16
  10841. ALL_ATT_3_5G.data2 = Prev_data[INDEX_ATT_3_5G_COM1] = data_buf[INDEX_ATT_3_5G_COM1];
  10842. 8008bb6: 74ab strb r3, [r5, #18]
  10843. 8008bb8: f886 3050 strb.w r3, [r6, #80] ; 0x50
  10844. ALL_ATT_3_5G.data3 = Prev_data[INDEX_ATT_3_5G_COM2] = data_buf[INDEX_ATT_3_5G_COM2];
  10845. 8008bbc: 7ce3 ldrb r3, [r4, #19]
  10846. PE43711_ALL_atten_ctrl(ALL_ATT_3_5G);
  10847. 8008bbe: 4668 mov r0, sp
  10848. ALL_ATT_3_5G.data3 = Prev_data[INDEX_ATT_3_5G_COM2] = data_buf[INDEX_ATT_3_5G_COM2];
  10849. 8008bc0: 74eb strb r3, [r5, #19]
  10850. 8008bc2: f886 306c strb.w r3, [r6, #108] ; 0x6c
  10851. ALL_ATT_3_5G.data4 = Prev_data[INDEX_ATT_3_5G_COM3] = data_buf[INDEX_ATT_3_5G_COM3];
  10852. 8008bc6: 7d23 ldrb r3, [r4, #20]
  10853. 8008bc8: 752b strb r3, [r5, #20]
  10854. 8008bca: f886 3088 strb.w r3, [r6, #136] ; 0x88
  10855. PE43711_ALL_atten_ctrl(ALL_ATT_3_5G);
  10856. 8008bce: f000 fbbd bl 800934c <memcpy>
  10857. 8008bd2: e896 000f ldmia.w r6, {r0, r1, r2, r3}
  10858. 8008bd6: f7fe fc6f bl 80074b8 <PE43711_ALL_atten_ctrl>
  10859. }
  10860. if((Prev_data[INDEX_PLL_1_8G_DL_H] != data_buf[INDEX_PLL_1_8G_DL_H])
  10861. 8008bda: 7d62 ldrb r2, [r4, #21]
  10862. 8008bdc: 7d6b ldrb r3, [r5, #21]
  10863. 8008bde: 4293 cmp r3, r2
  10864. 8008be0: d01d beq.n 8008c1e <RF_Operate+0x246>
  10865. && (Prev_data[INDEX_PLL_1_8G_DL_L] != data_buf[INDEX_PLL_1_8G_DL_L])
  10866. 8008be2: 7da3 ldrb r3, [r4, #22]
  10867. 8008be4: 7da9 ldrb r1, [r5, #22]
  10868. 8008be6: 4299 cmp r1, r3
  10869. 8008be8: d019 beq.n 8008c1e <RF_Operate+0x246>
  10870. ){
  10871. Prev_data[INDEX_PLL_1_8G_DL_H] = data_buf[INDEX_PLL_1_8G_DL_H];
  10872. 8008bea: 756a strb r2, [r5, #21]
  10873. Prev_data[INDEX_PLL_1_8G_DL_L] = data_buf[INDEX_PLL_1_8G_DL_L];
  10874. 8008bec: 75ab strb r3, [r5, #22]
  10875. temp_val = (data_buf[INDEX_PLL_1_8G_DL_H] << 8) | (data_buf[INDEX_PLL_1_8G_DL_L]);
  10876. 8008bee: 7d60 ldrb r0, [r4, #21]
  10877. 8008bf0: 7da3 ldrb r3, [r4, #22]
  10878. ADF4113_Module_Ctrl(ADF4113_1_8G_DL,0x410,halSynSetFreq((temp_val * 1000000) / 10 ),0x9F8092);
  10879. 8008bf2: ea43 2300 orr.w r3, r3, r0, lsl #8
  10880. 8008bf6: 4838 ldr r0, [pc, #224] ; (8008cd8 <RF_Operate+0x300>)
  10881. 8008bf8: 4358 muls r0, r3
  10882. 8008bfa: f7ff fbb7 bl 800836c <halSynSetFreq>
  10883. 8008bfe: 4a37 ldr r2, [pc, #220] ; (8008cdc <RF_Operate+0x304>)
  10884. 8008c00: 4b37 ldr r3, [pc, #220] ; (8008ce0 <RF_Operate+0x308>)
  10885. 8008c02: 9204 str r2, [sp, #16]
  10886. 8008c04: f44f 6282 mov.w r2, #1040 ; 0x410
  10887. 8008c08: 9003 str r0, [sp, #12]
  10888. 8008c0a: 9202 str r2, [sp, #8]
  10889. 8008c0c: f103 0210 add.w r2, r3, #16
  10890. 8008c10: e892 0003 ldmia.w r2, {r0, r1}
  10891. 8008c14: e88d 0003 stmia.w sp, {r0, r1}
  10892. 8008c18: cb0f ldmia r3, {r0, r1, r2, r3}
  10893. 8008c1a: f7ff fbd9 bl 80083d0 <ADF4113_Module_Ctrl>
  10894. }
  10895. if((Prev_data[INDEX_PLL_1_8G_UL_H] != data_buf[INDEX_PLL_1_8G_UL_H])
  10896. 8008c1e: 7de3 ldrb r3, [r4, #23]
  10897. 8008c20: 7dea ldrb r2, [r5, #23]
  10898. 8008c22: 429a cmp r2, r3
  10899. 8008c24: d01b beq.n 8008c5e <RF_Operate+0x286>
  10900. && (Prev_data[INDEX_PLL_1_8G_UL_L] != data_buf[INDEX_PLL_1_8G_UL_L])){
  10901. 8008c26: 7e20 ldrb r0, [r4, #24]
  10902. 8008c28: 7e2a ldrb r2, [r5, #24]
  10903. 8008c2a: 4282 cmp r2, r0
  10904. 8008c2c: d017 beq.n 8008c5e <RF_Operate+0x286>
  10905. temp_val = (data_buf[INDEX_PLL_1_8G_UL_H] << 8) | (data_buf[INDEX_PLL_1_8G_UL_L]);
  10906. Prev_data[INDEX_PLL_1_8G_UL_H] = data_buf[INDEX_PLL_1_8G_UL_H];
  10907. 8008c2e: 75eb strb r3, [r5, #23]
  10908. Prev_data[INDEX_PLL_1_8G_UL_L] = data_buf[INDEX_PLL_1_8G_UL_L];
  10909. 8008c30: 7628 strb r0, [r5, #24]
  10910. // ADF4113_Module_Ctrl(ADF4113_1_8G_UL,0x000410,0x038D31,0x9f8092);
  10911. ADF4113_Module_Ctrl(ADF4113_1_8G_UL,0x410,halSynSetFreq((temp_val * 1000000) / 10),0x9F8092);
  10912. 8008c32: ea40 2003 orr.w r0, r0, r3, lsl #8
  10913. 8008c36: 4b28 ldr r3, [pc, #160] ; (8008cd8 <RF_Operate+0x300>)
  10914. 8008c38: 4358 muls r0, r3
  10915. 8008c3a: f7ff fb97 bl 800836c <halSynSetFreq>
  10916. 8008c3e: 4a27 ldr r2, [pc, #156] ; (8008cdc <RF_Operate+0x304>)
  10917. 8008c40: 4b28 ldr r3, [pc, #160] ; (8008ce4 <RF_Operate+0x30c>)
  10918. 8008c42: 9204 str r2, [sp, #16]
  10919. 8008c44: f44f 6282 mov.w r2, #1040 ; 0x410
  10920. 8008c48: 9003 str r0, [sp, #12]
  10921. 8008c4a: 9202 str r2, [sp, #8]
  10922. 8008c4c: f103 0210 add.w r2, r3, #16
  10923. 8008c50: e892 0003 ldmia.w r2, {r0, r1}
  10924. 8008c54: e88d 0003 stmia.w sp, {r0, r1}
  10925. 8008c58: cb0f ldmia r3, {r0, r1, r2, r3}
  10926. 8008c5a: f7ff fbb9 bl 80083d0 <ADF4113_Module_Ctrl>
  10927. }
  10928. if((Prev_data[INDEX_PLL_2_1G_DL_H] != data_buf[INDEX_PLL_2_1G_DL_H])
  10929. 8008c5e: 7e63 ldrb r3, [r4, #25]
  10930. 8008c60: 7e6a ldrb r2, [r5, #25]
  10931. 8008c62: 429a cmp r2, r3
  10932. 8008c64: d042 beq.n 8008cec <RF_Operate+0x314>
  10933. && (Prev_data[INDEX_PLL_2_1G_DL_L] != data_buf[INDEX_PLL_2_1G_DL_L])){
  10934. 8008c66: 7ea0 ldrb r0, [r4, #26]
  10935. 8008c68: 7eaa ldrb r2, [r5, #26]
  10936. 8008c6a: 4282 cmp r2, r0
  10937. 8008c6c: d03e beq.n 8008cec <RF_Operate+0x314>
  10938. temp_val = ((data_buf[INDEX_PLL_2_1G_DL_H] << 8) | (data_buf[INDEX_PLL_2_1G_DL_L]));
  10939. Prev_data[INDEX_PLL_2_1G_DL_H] = data_buf[INDEX_PLL_2_1G_DL_H];
  10940. 8008c6e: 766b strb r3, [r5, #25]
  10941. Prev_data[INDEX_PLL_2_1G_DL_L] = data_buf[INDEX_PLL_2_1G_DL_L];
  10942. 8008c70: 76a8 strb r0, [r5, #26]
  10943. // ADF4113_Module_Ctrl(ADF4113_2_1G_DL,0x410,0x4DE71,0x9F8092);
  10944. ADF4113_Module_Ctrl(ADF4113_2_1G_DL,0x410,halSynSetFreq((temp_val * 1000000) / 10),0x9F8092);
  10945. 8008c72: ea40 2003 orr.w r0, r0, r3, lsl #8
  10946. 8008c76: 4b18 ldr r3, [pc, #96] ; (8008cd8 <RF_Operate+0x300>)
  10947. 8008c78: 4358 muls r0, r3
  10948. 8008c7a: f7ff fb77 bl 800836c <halSynSetFreq>
  10949. 8008c7e: 4a17 ldr r2, [pc, #92] ; (8008cdc <RF_Operate+0x304>)
  10950. 8008c80: 4b19 ldr r3, [pc, #100] ; (8008ce8 <RF_Operate+0x310>)
  10951. 8008c82: 9204 str r2, [sp, #16]
  10952. 8008c84: f44f 6282 mov.w r2, #1040 ; 0x410
  10953. 8008c88: 9003 str r0, [sp, #12]
  10954. 8008c8a: 9202 str r2, [sp, #8]
  10955. 8008c8c: f103 0210 add.w r2, r3, #16
  10956. 8008c90: e892 0003 ldmia.w r2, {r0, r1}
  10957. 8008c94: e88d 0003 stmia.w sp, {r0, r1}
  10958. 8008c98: cb0f ldmia r3, {r0, r1, r2, r3}
  10959. 8008c9a: f7ff fb99 bl 80083d0 <ADF4113_Module_Ctrl>
  10960. 8008c9e: e025 b.n 8008cec <RF_Operate+0x314>
  10961. 8008ca0: 20000574 .word 0x20000574
  10962. 8008ca4: 20000008 .word 0x20000008
  10963. 8008ca8: 20000020 .word 0x20000020
  10964. 8008cac: 20000038 .word 0x20000038
  10965. 8008cb0: 20000050 .word 0x20000050
  10966. 8008cb4: 20000068 .word 0x20000068
  10967. 8008cb8: 20000080 .word 0x20000080
  10968. 8008cbc: 20000098 .word 0x20000098
  10969. 8008cc0: 200000b0 .word 0x200000b0
  10970. 8008cc4: 200000c8 .word 0x200000c8
  10971. 8008cc8: 200000e0 .word 0x200000e0
  10972. 8008ccc: 200000f8 .word 0x200000f8
  10973. 8008cd0: 20000110 .word 0x20000110
  10974. 8008cd4: 200004e8 .word 0x200004e8
  10975. 8008cd8: 000186a0 .word 0x000186a0
  10976. 8008cdc: 009f8092 .word 0x009f8092
  10977. 8008ce0: 200001a0 .word 0x200001a0
  10978. 8008ce4: 200001b8 .word 0x200001b8
  10979. 8008ce8: 200001d0 .word 0x200001d0
  10980. }
  10981. if((Prev_data[INDEX_PLL_2_1G_UL_H] != data_buf[INDEX_PLL_2_1G_UL_H])
  10982. 8008cec: 7ee2 ldrb r2, [r4, #27]
  10983. 8008cee: 7eeb ldrb r3, [r5, #27]
  10984. 8008cf0: 4293 cmp r3, r2
  10985. 8008cf2: d01d beq.n 8008d30 <RF_Operate+0x358>
  10986. && (Prev_data[INDEX_PLL_2_1G_UL_L] != data_buf[INDEX_PLL_2_1G_UL_L])){
  10987. 8008cf4: 7f23 ldrb r3, [r4, #28]
  10988. 8008cf6: 7f29 ldrb r1, [r5, #28]
  10989. 8008cf8: 4299 cmp r1, r3
  10990. 8008cfa: d019 beq.n 8008d30 <RF_Operate+0x358>
  10991. Prev_data[INDEX_PLL_2_1G_UL_H] = data_buf[INDEX_PLL_2_1G_UL_H];
  10992. 8008cfc: 76ea strb r2, [r5, #27]
  10993. Prev_data[INDEX_PLL_2_1G_UL_L] = data_buf[INDEX_PLL_2_1G_UL_L];
  10994. 8008cfe: 772b strb r3, [r5, #28]
  10995. temp_val = (data_buf[INDEX_PLL_2_1G_UL_H] << 8) | (data_buf[INDEX_PLL_2_1G_UL_L]);
  10996. 8008d00: 7ee0 ldrb r0, [r4, #27]
  10997. 8008d02: 7f23 ldrb r3, [r4, #28]
  10998. // ADF4113_Module_Ctrl(ADF4113_2_1G_UL,0x000410,0x59A31,0x9f8092);
  10999. ADF4113_Module_Ctrl(ADF4113_2_1G_UL,0x410,halSynSetFreq((temp_val * 1000000) / 10),0x9F8092);
  11000. 8008d04: ea43 2300 orr.w r3, r3, r0, lsl #8
  11001. 8008d08: 48c7 ldr r0, [pc, #796] ; (8009028 <RF_Operate+0x650>)
  11002. 8008d0a: 4358 muls r0, r3
  11003. 8008d0c: f7ff fb2e bl 800836c <halSynSetFreq>
  11004. 8008d10: 4ac6 ldr r2, [pc, #792] ; (800902c <RF_Operate+0x654>)
  11005. 8008d12: 4bc7 ldr r3, [pc, #796] ; (8009030 <RF_Operate+0x658>)
  11006. 8008d14: 9204 str r2, [sp, #16]
  11007. 8008d16: f44f 6282 mov.w r2, #1040 ; 0x410
  11008. 8008d1a: 9003 str r0, [sp, #12]
  11009. 8008d1c: 9202 str r2, [sp, #8]
  11010. 8008d1e: f103 0210 add.w r2, r3, #16
  11011. 8008d22: e892 0003 ldmia.w r2, {r0, r1}
  11012. 8008d26: e88d 0003 stmia.w sp, {r0, r1}
  11013. 8008d2a: cb0f ldmia r3, {r0, r1, r2, r3}
  11014. 8008d2c: f7ff fb50 bl 80083d0 <ADF4113_Module_Ctrl>
  11015. }
  11016. if((Prev_data[INDEX_PLL_3_5G_DL_H] != data_buf[INDEX_PLL_3_5G_DL_H])
  11017. 8008d30: 7f62 ldrb r2, [r4, #29]
  11018. 8008d32: 7f6b ldrb r3, [r5, #29]
  11019. 8008d34: 4293 cmp r3, r2
  11020. 8008d36: d027 beq.n 8008d88 <RF_Operate+0x3b0>
  11021. && (Prev_data[INDEX_PLL_3_5G_DL_L] != data_buf[INDEX_PLL_3_5G_DL_L])){
  11022. 8008d38: 7fa3 ldrb r3, [r4, #30]
  11023. 8008d3a: 7fa9 ldrb r1, [r5, #30]
  11024. 8008d3c: 4299 cmp r1, r3
  11025. 8008d3e: d023 beq.n 8008d88 <RF_Operate+0x3b0>
  11026. Prev_data[INDEX_PLL_3_5G_DL_H] = data_buf[INDEX_PLL_3_5G_DL_H];
  11027. Prev_data[INDEX_PLL_3_5G_DL_L] = data_buf[INDEX_PLL_3_5G_DL_L];
  11028. 8008d40: 77ab strb r3, [r5, #30]
  11029. temp_val = (data_buf[INDEX_PLL_3_5G_DL_H] << 8) | (data_buf[INDEX_PLL_3_5G_DL_L]);
  11030. temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
  11031. 8008d42: f241 3388 movw r3, #5000 ; 0x1388
  11032. 8008d46: 9303 str r3, [sp, #12]
  11033. 8008d48: 2302 movs r3, #2
  11034. 8008d4a: 9302 str r3, [sp, #8]
  11035. 8008d4c: 2300 movs r3, #0
  11036. Prev_data[INDEX_PLL_3_5G_DL_H] = data_buf[INDEX_PLL_3_5G_DL_H];
  11037. 8008d4e: 776a strb r2, [r5, #29]
  11038. temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
  11039. 8008d50: 4ab8 ldr r2, [pc, #736] ; (8009034 <RF_Operate+0x65c>)
  11040. 8008d52: a820 add r0, sp, #128 ; 0x80
  11041. 8008d54: e9cd 2300 strd r2, r3, [sp]
  11042. 8008d58: a3af add r3, pc, #700 ; (adr r3, 8009018 <RF_Operate+0x640>)
  11043. 8008d5a: e9d3 2300 ldrd r2, r3, [r3]
  11044. 8008d5e: f7fe fce7 bl 8007730 <ADF4153_Freq_Calc>
  11045. ADF4153_Module_Ctrl(Pll_3_5_L,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
  11046. 8008d62: 2203 movs r2, #3
  11047. 8008d64: 9205 str r2, [sp, #20]
  11048. 8008d66: f241 32c2 movw r2, #5058 ; 0x13c2
  11049. 8008d6a: 9204 str r2, [sp, #16]
  11050. 8008d6c: 9a20 ldr r2, [sp, #128] ; 0x80
  11051. 8008d6e: 4bb2 ldr r3, [pc, #712] ; (8009038 <RF_Operate+0x660>)
  11052. 8008d70: 9203 str r2, [sp, #12]
  11053. 8008d72: 9a21 ldr r2, [sp, #132] ; 0x84
  11054. 8008d74: 9202 str r2, [sp, #8]
  11055. 8008d76: f103 0210 add.w r2, r3, #16
  11056. 8008d7a: e892 0003 ldmia.w r2, {r0, r1}
  11057. 8008d7e: e88d 0003 stmia.w sp, {r0, r1}
  11058. 8008d82: cb0f ldmia r3, {r0, r1, r2, r3}
  11059. 8008d84: f7fe fd58 bl 8007838 <ADF4153_Module_Ctrl>
  11060. }
  11061. if((Prev_data[INDEX_PLL_3_5G_UL_H] != data_buf[INDEX_PLL_3_5G_UL_H])
  11062. 8008d88: 7fe2 ldrb r2, [r4, #31]
  11063. 8008d8a: 7feb ldrb r3, [r5, #31]
  11064. 8008d8c: 4293 cmp r3, r2
  11065. 8008d8e: d02a beq.n 8008de6 <RF_Operate+0x40e>
  11066. && (Prev_data[INDEX_PLL_3_5G_UL_L] != data_buf[INDEX_PLL_3_5G_UL_L])){
  11067. 8008d90: f894 3020 ldrb.w r3, [r4, #32]
  11068. 8008d94: f895 1020 ldrb.w r1, [r5, #32]
  11069. 8008d98: 4299 cmp r1, r3
  11070. 8008d9a: d024 beq.n 8008de6 <RF_Operate+0x40e>
  11071. Prev_data[INDEX_PLL_3_5G_UL_H] = data_buf[INDEX_PLL_3_5G_UL_H];
  11072. Prev_data[INDEX_PLL_3_5G_UL_L] = data_buf[INDEX_PLL_3_5G_UL_L];
  11073. 8008d9c: f885 3020 strb.w r3, [r5, #32]
  11074. temp_val = (data_buf[INDEX_PLL_3_5G_UL_H] << 8) | (data_buf[INDEX_PLL_3_5G_UL_L]);
  11075. temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
  11076. 8008da0: f241 3388 movw r3, #5000 ; 0x1388
  11077. 8008da4: 9303 str r3, [sp, #12]
  11078. 8008da6: 2302 movs r3, #2
  11079. 8008da8: 9302 str r3, [sp, #8]
  11080. 8008daa: 2300 movs r3, #0
  11081. Prev_data[INDEX_PLL_3_5G_UL_H] = data_buf[INDEX_PLL_3_5G_UL_H];
  11082. 8008dac: 77ea strb r2, [r5, #31]
  11083. temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
  11084. 8008dae: 4aa1 ldr r2, [pc, #644] ; (8009034 <RF_Operate+0x65c>)
  11085. 8008db0: a820 add r0, sp, #128 ; 0x80
  11086. 8008db2: e9cd 2300 strd r2, r3, [sp]
  11087. 8008db6: a39a add r3, pc, #616 ; (adr r3, 8009020 <RF_Operate+0x648>)
  11088. 8008db8: e9d3 2300 ldrd r2, r3, [r3]
  11089. 8008dbc: f7fe fcb8 bl 8007730 <ADF4153_Freq_Calc>
  11090. ADF4153_Module_Ctrl(Pll_3_5_H,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
  11091. 8008dc0: 2203 movs r2, #3
  11092. 8008dc2: 9205 str r2, [sp, #20]
  11093. 8008dc4: f241 32c2 movw r2, #5058 ; 0x13c2
  11094. 8008dc8: 9204 str r2, [sp, #16]
  11095. 8008dca: 9a20 ldr r2, [sp, #128] ; 0x80
  11096. 8008dcc: 4b9b ldr r3, [pc, #620] ; (800903c <RF_Operate+0x664>)
  11097. 8008dce: 9203 str r2, [sp, #12]
  11098. 8008dd0: 9a21 ldr r2, [sp, #132] ; 0x84
  11099. 8008dd2: 9202 str r2, [sp, #8]
  11100. 8008dd4: f103 0210 add.w r2, r3, #16
  11101. 8008dd8: e892 0003 ldmia.w r2, {r0, r1}
  11102. 8008ddc: e88d 0003 stmia.w sp, {r0, r1}
  11103. 8008de0: cb0f ldmia r3, {r0, r1, r2, r3}
  11104. 8008de2: f7fe fd29 bl 8007838 <ADF4153_Module_Ctrl>
  11105. }
  11106. if(Prev_data[INDEX_ALARM_DC] != data_buf[INDEX_ALARM_DC]){
  11107. }
  11108. if(Prev_data[INDEX_PATH_EN_1_8G_DL] != data_buf[INDEX_PATH_EN_1_8G_DL]){
  11109. 8008de6: f894 1040 ldrb.w r1, [r4, #64] ; 0x40
  11110. 8008dea: f895 3040 ldrb.w r3, [r5, #64] ; 0x40
  11111. 8008dee: 428b cmp r3, r1
  11112. 8008df0: d006 beq.n 8008e00 <RF_Operate+0x428>
  11113. Power_ON_OFF_Ctrl(INDEX_PATH_EN_1_8G_DL,data_buf[INDEX_PATH_EN_1_8G_DL]);
  11114. 8008df2: 2040 movs r0, #64 ; 0x40
  11115. 8008df4: f7fe febc bl 8007b70 <Power_ON_OFF_Ctrl>
  11116. Prev_data[INDEX_PATH_EN_1_8G_DL] = data_buf[INDEX_PATH_EN_1_8G_DL];
  11117. 8008df8: f894 3040 ldrb.w r3, [r4, #64] ; 0x40
  11118. 8008dfc: f885 3040 strb.w r3, [r5, #64] ; 0x40
  11119. }
  11120. if(Prev_data[INDEX_PATH_EN_1_8G_UL] != data_buf[INDEX_PATH_EN_1_8G_UL]){
  11121. 8008e00: f894 1041 ldrb.w r1, [r4, #65] ; 0x41
  11122. 8008e04: f895 3041 ldrb.w r3, [r5, #65] ; 0x41
  11123. 8008e08: 428b cmp r3, r1
  11124. 8008e0a: d006 beq.n 8008e1a <RF_Operate+0x442>
  11125. Power_ON_OFF_Ctrl(INDEX_PATH_EN_1_8G_UL,data_buf[INDEX_PATH_EN_1_8G_UL]);
  11126. 8008e0c: 2041 movs r0, #65 ; 0x41
  11127. 8008e0e: f7fe feaf bl 8007b70 <Power_ON_OFF_Ctrl>
  11128. Prev_data[INDEX_PATH_EN_1_8G_UL] = data_buf[INDEX_PATH_EN_1_8G_UL];
  11129. 8008e12: f894 3041 ldrb.w r3, [r4, #65] ; 0x41
  11130. 8008e16: f885 3041 strb.w r3, [r5, #65] ; 0x41
  11131. }
  11132. if(Prev_data[INDEX_PATH_EN_2_1G_DL] != data_buf[INDEX_PATH_EN_2_1G_DL]){
  11133. 8008e1a: f894 1042 ldrb.w r1, [r4, #66] ; 0x42
  11134. 8008e1e: f895 3042 ldrb.w r3, [r5, #66] ; 0x42
  11135. 8008e22: 428b cmp r3, r1
  11136. 8008e24: d006 beq.n 8008e34 <RF_Operate+0x45c>
  11137. Power_ON_OFF_Ctrl(INDEX_PATH_EN_2_1G_DL,data_buf[INDEX_PATH_EN_2_1G_DL]);
  11138. 8008e26: 2042 movs r0, #66 ; 0x42
  11139. 8008e28: f7fe fea2 bl 8007b70 <Power_ON_OFF_Ctrl>
  11140. Prev_data[INDEX_PATH_EN_2_1G_DL] = data_buf[INDEX_PATH_EN_2_1G_DL];
  11141. 8008e2c: f894 3042 ldrb.w r3, [r4, #66] ; 0x42
  11142. 8008e30: f885 3042 strb.w r3, [r5, #66] ; 0x42
  11143. }
  11144. if(Prev_data[INDEX_PATH_EN_2_1G_UL] != data_buf[INDEX_PATH_EN_2_1G_UL]){
  11145. 8008e34: f894 1043 ldrb.w r1, [r4, #67] ; 0x43
  11146. 8008e38: f895 3043 ldrb.w r3, [r5, #67] ; 0x43
  11147. 8008e3c: 428b cmp r3, r1
  11148. 8008e3e: d006 beq.n 8008e4e <RF_Operate+0x476>
  11149. Power_ON_OFF_Ctrl(INDEX_PATH_EN_2_1G_UL,data_buf[INDEX_PATH_EN_2_1G_UL]);
  11150. 8008e40: 2043 movs r0, #67 ; 0x43
  11151. 8008e42: f7fe fe95 bl 8007b70 <Power_ON_OFF_Ctrl>
  11152. Prev_data[INDEX_PATH_EN_2_1G_UL] = data_buf[INDEX_PATH_EN_2_1G_UL];
  11153. 8008e46: f894 3043 ldrb.w r3, [r4, #67] ; 0x43
  11154. 8008e4a: f885 3043 strb.w r3, [r5, #67] ; 0x43
  11155. }
  11156. if(Prev_data[INDEX_PATH_EN_3_5G_L] != data_buf[INDEX_PATH_EN_3_5G_L]){
  11157. 8008e4e: f894 1047 ldrb.w r1, [r4, #71] ; 0x47
  11158. 8008e52: f895 3047 ldrb.w r3, [r5, #71] ; 0x47
  11159. 8008e56: 428b cmp r3, r1
  11160. 8008e58: d006 beq.n 8008e68 <RF_Operate+0x490>
  11161. Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_L,data_buf[INDEX_PATH_EN_3_5G_L]);
  11162. 8008e5a: 2047 movs r0, #71 ; 0x47
  11163. 8008e5c: f7fe fe88 bl 8007b70 <Power_ON_OFF_Ctrl>
  11164. Prev_data[INDEX_PATH_EN_3_5G_L] = data_buf[INDEX_PATH_EN_3_5G_L];
  11165. 8008e60: f894 3047 ldrb.w r3, [r4, #71] ; 0x47
  11166. 8008e64: f885 3047 strb.w r3, [r5, #71] ; 0x47
  11167. }
  11168. if(Prev_data[INDEX_PATH_EN_3_5G_H] != data_buf[INDEX_PATH_EN_3_5G_H]){
  11169. 8008e68: f894 1046 ldrb.w r1, [r4, #70] ; 0x46
  11170. 8008e6c: f895 3046 ldrb.w r3, [r5, #70] ; 0x46
  11171. 8008e70: 428b cmp r3, r1
  11172. 8008e72: d006 beq.n 8008e82 <RF_Operate+0x4aa>
  11173. Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_H,data_buf[INDEX_PATH_EN_3_5G_H]);
  11174. 8008e74: 2046 movs r0, #70 ; 0x46
  11175. 8008e76: f7fe fe7b bl 8007b70 <Power_ON_OFF_Ctrl>
  11176. Prev_data[INDEX_PATH_EN_3_5G_H] = data_buf[INDEX_PATH_EN_3_5G_H];
  11177. 8008e7a: f894 3046 ldrb.w r3, [r4, #70] ; 0x46
  11178. 8008e7e: f885 3046 strb.w r3, [r5, #70] ; 0x46
  11179. }
  11180. if(Prev_data[INDEX_PATH_EN_3_5G_DL] != data_buf[INDEX_PATH_EN_3_5G_DL]){
  11181. 8008e82: f894 1044 ldrb.w r1, [r4, #68] ; 0x44
  11182. 8008e86: f895 3044 ldrb.w r3, [r5, #68] ; 0x44
  11183. 8008e8a: 428b cmp r3, r1
  11184. 8008e8c: d006 beq.n 8008e9c <RF_Operate+0x4c4>
  11185. Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_DL,data_buf[INDEX_PATH_EN_3_5G_DL]);
  11186. 8008e8e: 2044 movs r0, #68 ; 0x44
  11187. 8008e90: f7fe fe6e bl 8007b70 <Power_ON_OFF_Ctrl>
  11188. Prev_data[INDEX_PATH_EN_3_5G_DL] = data_buf[INDEX_PATH_EN_3_5G_DL];
  11189. 8008e94: f894 3044 ldrb.w r3, [r4, #68] ; 0x44
  11190. 8008e98: f885 3044 strb.w r3, [r5, #68] ; 0x44
  11191. }
  11192. if(Prev_data[INDEX_PATH_EN_3_5G_UL] != data_buf[INDEX_PATH_EN_3_5G_UL]){
  11193. 8008e9c: f894 1045 ldrb.w r1, [r4, #69] ; 0x45
  11194. 8008ea0: f895 3045 ldrb.w r3, [r5, #69] ; 0x45
  11195. 8008ea4: 428b cmp r3, r1
  11196. 8008ea6: d006 beq.n 8008eb6 <RF_Operate+0x4de>
  11197. Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_UL,data_buf[INDEX_PATH_EN_3_5G_UL]);
  11198. 8008ea8: 2045 movs r0, #69 ; 0x45
  11199. 8008eaa: f7fe fe61 bl 8007b70 <Power_ON_OFF_Ctrl>
  11200. Prev_data[INDEX_PATH_EN_3_5G_UL] = data_buf[INDEX_PATH_EN_3_5G_UL];
  11201. 8008eae: f894 3045 ldrb.w r3, [r4, #69] ; 0x45
  11202. 8008eb2: f885 3045 strb.w r3, [r5, #69] ; 0x45
  11203. }
  11204. if(Prev_data[INDEX_PLL_ON_OFF_3_5G_H] != data_buf[INDEX_PLL_ON_OFF_3_5G_H]){
  11205. 8008eb6: f894 1048 ldrb.w r1, [r4, #72] ; 0x48
  11206. 8008eba: f895 3048 ldrb.w r3, [r5, #72] ; 0x48
  11207. 8008ebe: 428b cmp r3, r1
  11208. 8008ec0: d036 beq.n 8008f30 <RF_Operate+0x558>
  11209. Power_ON_OFF_Ctrl(INDEX_PLL_ON_OFF_3_5G_H,data_buf[INDEX_PLL_ON_OFF_3_5G_H]);
  11210. 8008ec2: 2048 movs r0, #72 ; 0x48
  11211. 8008ec4: f7fe fe54 bl 8007b70 <Power_ON_OFF_Ctrl>
  11212. Prev_data[INDEX_PLL_ON_OFF_3_5G_H] = data_buf[INDEX_PLL_ON_OFF_3_5G_H];
  11213. 8008ec8: f894 3048 ldrb.w r3, [r4, #72] ; 0x48
  11214. HAL_Delay(10);
  11215. 8008ecc: 200a movs r0, #10
  11216. Prev_data[INDEX_PLL_ON_OFF_3_5G_H] = data_buf[INDEX_PLL_ON_OFF_3_5G_H];
  11217. 8008ece: f885 3048 strb.w r3, [r5, #72] ; 0x48
  11218. HAL_Delay(10);
  11219. 8008ed2: f7fc fb0b bl 80054ec <HAL_Delay>
  11220. printf("POWER : %d \r\n",Prev_data[INDEX_PLL_ON_OFF_3_5G_H]);
  11221. 8008ed6: f895 1048 ldrb.w r1, [r5, #72] ; 0x48
  11222. 8008eda: 4859 ldr r0, [pc, #356] ; (8009040 <RF_Operate+0x668>)
  11223. 8008edc: f000 feaa bl 8009c34 <iprintf>
  11224. if(data_buf[INDEX_PLL_ON_OFF_3_5G_H]){
  11225. 8008ee0: f894 3048 ldrb.w r3, [r4, #72] ; 0x48
  11226. 8008ee4: b323 cbz r3, 8008f30 <RF_Operate+0x558>
  11227. printf("PLL CTRL START !! \r\n");
  11228. 8008ee6: 4857 ldr r0, [pc, #348] ; (8009044 <RF_Operate+0x66c>)
  11229. 8008ee8: f000 ff18 bl 8009d1c <puts>
  11230. temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
  11231. 8008eec: f241 3388 movw r3, #5000 ; 0x1388
  11232. 8008ef0: 9303 str r3, [sp, #12]
  11233. 8008ef2: 2302 movs r3, #2
  11234. 8008ef4: 9302 str r3, [sp, #8]
  11235. 8008ef6: 2300 movs r3, #0
  11236. 8008ef8: 4a4e ldr r2, [pc, #312] ; (8009034 <RF_Operate+0x65c>)
  11237. 8008efa: a820 add r0, sp, #128 ; 0x80
  11238. 8008efc: e9cd 2300 strd r2, r3, [sp]
  11239. 8008f00: a345 add r3, pc, #276 ; (adr r3, 8009018 <RF_Operate+0x640>)
  11240. 8008f02: e9d3 2300 ldrd r2, r3, [r3]
  11241. 8008f06: f7fe fc13 bl 8007730 <ADF4153_Freq_Calc>
  11242. ADF4153_Module_Ctrl(Pll_3_5_H,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
  11243. 8008f0a: 2203 movs r2, #3
  11244. 8008f0c: 9205 str r2, [sp, #20]
  11245. 8008f0e: f241 32c2 movw r2, #5058 ; 0x13c2
  11246. 8008f12: 9204 str r2, [sp, #16]
  11247. 8008f14: 9a20 ldr r2, [sp, #128] ; 0x80
  11248. 8008f16: 4b49 ldr r3, [pc, #292] ; (800903c <RF_Operate+0x664>)
  11249. 8008f18: 9203 str r2, [sp, #12]
  11250. 8008f1a: 9a21 ldr r2, [sp, #132] ; 0x84
  11251. 8008f1c: 9202 str r2, [sp, #8]
  11252. 8008f1e: f103 0210 add.w r2, r3, #16
  11253. 8008f22: e892 0003 ldmia.w r2, {r0, r1}
  11254. 8008f26: e88d 0003 stmia.w sp, {r0, r1}
  11255. 8008f2a: cb0f ldmia r3, {r0, r1, r2, r3}
  11256. 8008f2c: f7fe fc84 bl 8007838 <ADF4153_Module_Ctrl>
  11257. }
  11258. }
  11259. if(Prev_data[INDEX_PLL_ON_OFF_3_5G_L] != data_buf[INDEX_PLL_ON_OFF_3_5G_L]){
  11260. 8008f30: f894 1049 ldrb.w r1, [r4, #73] ; 0x49
  11261. 8008f34: f895 3049 ldrb.w r3, [r5, #73] ; 0x49
  11262. 8008f38: 428b cmp r3, r1
  11263. 8008f3a: d036 beq.n 8008faa <RF_Operate+0x5d2>
  11264. Power_ON_OFF_Ctrl(INDEX_PLL_ON_OFF_3_5G_L,data_buf[INDEX_PLL_ON_OFF_3_5G_L]);
  11265. 8008f3c: 2049 movs r0, #73 ; 0x49
  11266. 8008f3e: f7fe fe17 bl 8007b70 <Power_ON_OFF_Ctrl>
  11267. Prev_data[INDEX_PLL_ON_OFF_3_5G_L] = data_buf[INDEX_PLL_ON_OFF_3_5G_L];
  11268. 8008f42: f894 3049 ldrb.w r3, [r4, #73] ; 0x49
  11269. HAL_Delay(10);
  11270. 8008f46: 200a movs r0, #10
  11271. Prev_data[INDEX_PLL_ON_OFF_3_5G_L] = data_buf[INDEX_PLL_ON_OFF_3_5G_L];
  11272. 8008f48: f885 3049 strb.w r3, [r5, #73] ; 0x49
  11273. HAL_Delay(10);
  11274. 8008f4c: f7fc face bl 80054ec <HAL_Delay>
  11275. printf("POWER : %d \r\n",Prev_data[INDEX_PLL_ON_OFF_3_5G_L]);
  11276. 8008f50: f895 1049 ldrb.w r1, [r5, #73] ; 0x49
  11277. 8008f54: 483a ldr r0, [pc, #232] ; (8009040 <RF_Operate+0x668>)
  11278. 8008f56: f000 fe6d bl 8009c34 <iprintf>
  11279. if(data_buf[INDEX_PLL_ON_OFF_3_5G_L]){
  11280. 8008f5a: f894 3049 ldrb.w r3, [r4, #73] ; 0x49
  11281. 8008f5e: b323 cbz r3, 8008faa <RF_Operate+0x5d2>
  11282. printf("PLL CTRL START !! \r\n");
  11283. 8008f60: 4838 ldr r0, [pc, #224] ; (8009044 <RF_Operate+0x66c>)
  11284. 8008f62: f000 fedb bl 8009d1c <puts>
  11285. temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
  11286. 8008f66: f241 3388 movw r3, #5000 ; 0x1388
  11287. 8008f6a: 9303 str r3, [sp, #12]
  11288. 8008f6c: 2302 movs r3, #2
  11289. 8008f6e: 9302 str r3, [sp, #8]
  11290. 8008f70: 2300 movs r3, #0
  11291. 8008f72: 4a30 ldr r2, [pc, #192] ; (8009034 <RF_Operate+0x65c>)
  11292. 8008f74: a820 add r0, sp, #128 ; 0x80
  11293. 8008f76: e9cd 2300 strd r2, r3, [sp]
  11294. 8008f7a: a329 add r3, pc, #164 ; (adr r3, 8009020 <RF_Operate+0x648>)
  11295. 8008f7c: e9d3 2300 ldrd r2, r3, [r3]
  11296. 8008f80: f7fe fbd6 bl 8007730 <ADF4153_Freq_Calc>
  11297. ADF4153_Module_Ctrl(Pll_3_5_L,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
  11298. 8008f84: 2203 movs r2, #3
  11299. 8008f86: 9205 str r2, [sp, #20]
  11300. 8008f88: f241 32c2 movw r2, #5058 ; 0x13c2
  11301. 8008f8c: 9204 str r2, [sp, #16]
  11302. 8008f8e: 9a20 ldr r2, [sp, #128] ; 0x80
  11303. 8008f90: 4b29 ldr r3, [pc, #164] ; (8009038 <RF_Operate+0x660>)
  11304. 8008f92: 9203 str r2, [sp, #12]
  11305. 8008f94: 9a21 ldr r2, [sp, #132] ; 0x84
  11306. 8008f96: 9202 str r2, [sp, #8]
  11307. 8008f98: f103 0210 add.w r2, r3, #16
  11308. 8008f9c: e892 0003 ldmia.w r2, {r0, r1}
  11309. 8008fa0: e88d 0003 stmia.w sp, {r0, r1}
  11310. 8008fa4: cb0f ldmia r3, {r0, r1, r2, r3}
  11311. 8008fa6: f7fe fc47 bl 8007838 <ADF4153_Module_Ctrl>
  11312. }
  11313. }
  11314. if(Prev_data[INDEX_T_SYNC_DL] != data_buf[INDEX_T_SYNC_DL]){
  11315. 8008faa: f894 304a ldrb.w r3, [r4, #74] ; 0x4a
  11316. 8008fae: f895 204a ldrb.w r2, [r5, #74] ; 0x4a
  11317. 8008fb2: 429a cmp r2, r3
  11318. 8008fb4: d006 beq.n 8008fc4 <RF_Operate+0x5ec>
  11319. Prev_data[INDEX_T_SYNC_DL] = data_buf[INDEX_T_SYNC_DL];
  11320. 8008fb6: f885 304a strb.w r3, [r5, #74] ; 0x4a
  11321. Power_ON_OFF_Ctrl(INDEX_T_SYNC_DL,data_buf[INDEX_T_SYNC_DL]);
  11322. 8008fba: f894 104a ldrb.w r1, [r4, #74] ; 0x4a
  11323. 8008fbe: 204a movs r0, #74 ; 0x4a
  11324. 8008fc0: f7fe fdd6 bl 8007b70 <Power_ON_OFF_Ctrl>
  11325. }
  11326. if(Prev_data[INDEX__T_SYNC_DL] != data_buf[INDEX__T_SYNC_DL]){
  11327. 8008fc4: f894 304b ldrb.w r3, [r4, #75] ; 0x4b
  11328. 8008fc8: f895 204b ldrb.w r2, [r5, #75] ; 0x4b
  11329. 8008fcc: 429a cmp r2, r3
  11330. 8008fce: d006 beq.n 8008fde <RF_Operate+0x606>
  11331. Prev_data[INDEX__T_SYNC_DL] = data_buf[INDEX__T_SYNC_DL];
  11332. 8008fd0: f885 304b strb.w r3, [r5, #75] ; 0x4b
  11333. Power_ON_OFF_Ctrl(INDEX__T_SYNC_DL,data_buf[INDEX__T_SYNC_DL]);
  11334. 8008fd4: f894 104b ldrb.w r1, [r4, #75] ; 0x4b
  11335. 8008fd8: 204b movs r0, #75 ; 0x4b
  11336. 8008fda: f7fe fdc9 bl 8007b70 <Power_ON_OFF_Ctrl>
  11337. }
  11338. if(Prev_data[INDEX_T_SYNC_UL] != data_buf[INDEX_T_SYNC_UL]){
  11339. 8008fde: 4d1a ldr r5, [pc, #104] ; (8009048 <RF_Operate+0x670>)
  11340. 8008fe0: f894 304c ldrb.w r3, [r4, #76] ; 0x4c
  11341. 8008fe4: f895 204c ldrb.w r2, [r5, #76] ; 0x4c
  11342. 8008fe8: 429a cmp r2, r3
  11343. 8008fea: d006 beq.n 8008ffa <RF_Operate+0x622>
  11344. Prev_data[INDEX_T_SYNC_UL] = data_buf[INDEX_T_SYNC_UL];
  11345. 8008fec: f885 304c strb.w r3, [r5, #76] ; 0x4c
  11346. Power_ON_OFF_Ctrl(INDEX_T_SYNC_UL,data_buf[INDEX_T_SYNC_UL]);
  11347. 8008ff0: f894 104c ldrb.w r1, [r4, #76] ; 0x4c
  11348. 8008ff4: 204c movs r0, #76 ; 0x4c
  11349. 8008ff6: f7fe fdbb bl 8007b70 <Power_ON_OFF_Ctrl>
  11350. }
  11351. if(Prev_data[INDEX__T_SYNC_UL] != data_buf[INDEX__T_SYNC_UL]){
  11352. 8008ffa: f894 304d ldrb.w r3, [r4, #77] ; 0x4d
  11353. 8008ffe: f895 204d ldrb.w r2, [r5, #77] ; 0x4d
  11354. 8009002: 429a cmp r2, r3
  11355. 8009004: d022 beq.n 800904c <RF_Operate+0x674>
  11356. Prev_data[INDEX__T_SYNC_UL] = data_buf[INDEX__T_SYNC_UL];
  11357. 8009006: f885 304d strb.w r3, [r5, #77] ; 0x4d
  11358. Power_ON_OFF_Ctrl(INDEX__T_SYNC_UL,data_buf[INDEX__T_SYNC_UL]);
  11359. 800900a: f894 104d ldrb.w r1, [r4, #77] ; 0x4d
  11360. 800900e: 204d movs r0, #77 ; 0x4d
  11361. 8009010: f7fe fdae bl 8007b70 <Power_ON_OFF_Ctrl>
  11362. 8009014: e01a b.n 800904c <RF_Operate+0x674>
  11363. 8009016: bf00 nop
  11364. 8009018: ea83b4a0 .word 0xea83b4a0
  11365. 800901c: 00000000 .word 0x00000000
  11366. 8009020: ce8f5560 .word 0xce8f5560
  11367. 8009024: 00000000 .word 0x00000000
  11368. 8009028: 000186a0 .word 0x000186a0
  11369. 800902c: 009f8092 .word 0x009f8092
  11370. 8009030: 200001e8 .word 0x200001e8
  11371. 8009034: 02625a00 .word 0x02625a00
  11372. 8009038: 2000021c .word 0x2000021c
  11373. 800903c: 20000204 .word 0x20000204
  11374. 8009040: 0800bcf3 .word 0x0800bcf3
  11375. 8009044: 0800bd01 .word 0x0800bd01
  11376. 8009048: 20000574 .word 0x20000574
  11377. }
  11378. if((Prev_data[INDEX_DAC_VCtrl_A_H] != data_buf[INDEX_DAC_VCtrl_A_H])
  11379. 800904c: f894 304e ldrb.w r3, [r4, #78] ; 0x4e
  11380. 8009050: f895 204e ldrb.w r2, [r5, #78] ; 0x4e
  11381. 8009054: 429a cmp r2, r3
  11382. 8009056: d106 bne.n 8009066 <RF_Operate+0x68e>
  11383. ||(Prev_data[INDEX_DAC_VCtrl_A_L] != data_buf[INDEX_DAC_VCtrl_A_L])){
  11384. 8009058: f895 104f ldrb.w r1, [r5, #79] ; 0x4f
  11385. 800905c: f894 204f ldrb.w r2, [r4, #79] ; 0x4f
  11386. 8009060: 4291 cmp r1, r2
  11387. 8009062: f000 80ce beq.w 8009202 <RF_Operate+0x82a>
  11388. ADC_Modify = 1;
  11389. Prev_data[INDEX_DAC_VCtrl_A_H] = data_buf[INDEX_DAC_VCtrl_A_H];
  11390. 8009066: f885 304e strb.w r3, [r5, #78] ; 0x4e
  11391. Prev_data[INDEX_DAC_VCtrl_A_L] = data_buf[INDEX_DAC_VCtrl_A_L];
  11392. 800906a: f894 304f ldrb.w r3, [r4, #79] ; 0x4f
  11393. 800906e: f885 304f strb.w r3, [r5, #79] ; 0x4f
  11394. ADC_Modify = 1;
  11395. 8009072: 2301 movs r3, #1
  11396. }
  11397. if((Prev_data[INDEX_DAC_VCtrl_B_H] != data_buf[INDEX_DAC_VCtrl_B_H])
  11398. 8009074: f894 2050 ldrb.w r2, [r4, #80] ; 0x50
  11399. 8009078: f895 1050 ldrb.w r1, [r5, #80] ; 0x50
  11400. 800907c: 4291 cmp r1, r2
  11401. 800907e: d105 bne.n 800908c <RF_Operate+0x6b4>
  11402. ||(Prev_data[INDEX_DAC_VCtrl_B_L] != data_buf[INDEX_DAC_VCtrl_B_L])){
  11403. 8009080: f895 0051 ldrb.w r0, [r5, #81] ; 0x51
  11404. 8009084: f894 1051 ldrb.w r1, [r4, #81] ; 0x51
  11405. 8009088: 4288 cmp r0, r1
  11406. 800908a: d006 beq.n 800909a <RF_Operate+0x6c2>
  11407. ADC_Modify = 1;
  11408. Prev_data[INDEX_DAC_VCtrl_B_H] = data_buf[INDEX_DAC_VCtrl_B_H];
  11409. 800908c: f885 2050 strb.w r2, [r5, #80] ; 0x50
  11410. Prev_data[INDEX_DAC_VCtrl_B_L] = data_buf[INDEX_DAC_VCtrl_B_L];
  11411. 8009090: f894 3051 ldrb.w r3, [r4, #81] ; 0x51
  11412. 8009094: f885 3051 strb.w r3, [r5, #81] ; 0x51
  11413. ADC_Modify = 1;
  11414. 8009098: 2301 movs r3, #1
  11415. }
  11416. if((Prev_data[INDEX_DAC_VCtrl_C_H] != data_buf[INDEX_DAC_VCtrl_C_H])
  11417. 800909a: f894 2052 ldrb.w r2, [r4, #82] ; 0x52
  11418. 800909e: f895 1052 ldrb.w r1, [r5, #82] ; 0x52
  11419. 80090a2: 4291 cmp r1, r2
  11420. 80090a4: d105 bne.n 80090b2 <RF_Operate+0x6da>
  11421. ||(Prev_data[INDEX_DAC_VCtrl_C_L] != data_buf[INDEX_DAC_VCtrl_C_L])){
  11422. 80090a6: f895 0053 ldrb.w r0, [r5, #83] ; 0x53
  11423. 80090aa: f894 1053 ldrb.w r1, [r4, #83] ; 0x53
  11424. 80090ae: 4288 cmp r0, r1
  11425. 80090b0: d006 beq.n 80090c0 <RF_Operate+0x6e8>
  11426. ADC_Modify = 1;
  11427. // printf("Prev_data[INDEX_DAC_VCtrl_C_H] : %x \r\n",Prev_data[INDEX_DAC_VCtrl_C_H]);
  11428. // printf("Prev_data[INDEX_DAC_VCtrl_C_L] : %x \r\n",Prev_data[INDEX_DAC_VCtrl_C_L]);
  11429. Prev_data[INDEX_DAC_VCtrl_C_H] = data_buf[INDEX_DAC_VCtrl_C_H];
  11430. 80090b2: f885 2052 strb.w r2, [r5, #82] ; 0x52
  11431. Prev_data[INDEX_DAC_VCtrl_C_L] = data_buf[INDEX_DAC_VCtrl_C_L];
  11432. 80090b6: f894 3053 ldrb.w r3, [r4, #83] ; 0x53
  11433. 80090ba: f885 3053 strb.w r3, [r5, #83] ; 0x53
  11434. ADC_Modify = 1;
  11435. 80090be: 2301 movs r3, #1
  11436. }
  11437. if((Prev_data[INDEX_DAC_VCtrl_D_H] != data_buf[INDEX_DAC_VCtrl_D_H])
  11438. 80090c0: f894 2054 ldrb.w r2, [r4, #84] ; 0x54
  11439. 80090c4: f895 1054 ldrb.w r1, [r5, #84] ; 0x54
  11440. 80090c8: 4291 cmp r1, r2
  11441. 80090ca: d105 bne.n 80090d8 <RF_Operate+0x700>
  11442. ||(Prev_data[INDEX_DAC_VCtrl_D_L] != data_buf[INDEX_DAC_VCtrl_D_L])){
  11443. 80090cc: f895 0055 ldrb.w r0, [r5, #85] ; 0x55
  11444. 80090d0: f894 1055 ldrb.w r1, [r4, #85] ; 0x55
  11445. 80090d4: 4288 cmp r0, r1
  11446. 80090d6: d006 beq.n 80090e6 <RF_Operate+0x70e>
  11447. ADC_Modify = 1;
  11448. Prev_data[INDEX_DAC_VCtrl_D_H] = data_buf[INDEX_DAC_VCtrl_D_H];
  11449. 80090d8: f885 2054 strb.w r2, [r5, #84] ; 0x54
  11450. Prev_data[INDEX_DAC_VCtrl_D_L] = data_buf[INDEX_DAC_VCtrl_D_L];
  11451. 80090dc: f894 3055 ldrb.w r3, [r4, #85] ; 0x55
  11452. 80090e0: f885 3055 strb.w r3, [r5, #85] ; 0x55
  11453. ADC_Modify = 1;
  11454. 80090e4: 2301 movs r3, #1
  11455. }
  11456. if((Prev_data[INDEX_DAC_VCtrl_E_H] != data_buf[INDEX_DAC_VCtrl_E_H])
  11457. 80090e6: f894 2056 ldrb.w r2, [r4, #86] ; 0x56
  11458. 80090ea: f895 1056 ldrb.w r1, [r5, #86] ; 0x56
  11459. 80090ee: 4291 cmp r1, r2
  11460. 80090f0: d105 bne.n 80090fe <RF_Operate+0x726>
  11461. ||(Prev_data[INDEX_DAC_VCtrl_E_L] != data_buf[INDEX_DAC_VCtrl_E_L])){
  11462. 80090f2: f895 0057 ldrb.w r0, [r5, #87] ; 0x57
  11463. 80090f6: f894 1057 ldrb.w r1, [r4, #87] ; 0x57
  11464. 80090fa: 4288 cmp r0, r1
  11465. 80090fc: d006 beq.n 800910c <RF_Operate+0x734>
  11466. ADC_Modify = 1;
  11467. Prev_data[INDEX_DAC_VCtrl_E_H] = data_buf[INDEX_DAC_VCtrl_E_H];
  11468. 80090fe: f885 2056 strb.w r2, [r5, #86] ; 0x56
  11469. Prev_data[INDEX_DAC_VCtrl_E_L] = data_buf[INDEX_DAC_VCtrl_E_L];
  11470. 8009102: f894 3057 ldrb.w r3, [r4, #87] ; 0x57
  11471. 8009106: f885 3057 strb.w r3, [r5, #87] ; 0x57
  11472. ADC_Modify = 1;
  11473. 800910a: 2301 movs r3, #1
  11474. }
  11475. if((Prev_data[INDEX_DAC_VCtrl_F_H] != data_buf[INDEX_DAC_VCtrl_F_H])
  11476. 800910c: f894 2058 ldrb.w r2, [r4, #88] ; 0x58
  11477. 8009110: f895 1058 ldrb.w r1, [r5, #88] ; 0x58
  11478. 8009114: 4291 cmp r1, r2
  11479. 8009116: d105 bne.n 8009124 <RF_Operate+0x74c>
  11480. ||(Prev_data[INDEX_DAC_VCtrl_F_L] != data_buf[INDEX_DAC_VCtrl_F_L])){
  11481. 8009118: f895 0059 ldrb.w r0, [r5, #89] ; 0x59
  11482. 800911c: f894 1059 ldrb.w r1, [r4, #89] ; 0x59
  11483. 8009120: 4288 cmp r0, r1
  11484. 8009122: d006 beq.n 8009132 <RF_Operate+0x75a>
  11485. ADC_Modify = 1;
  11486. Prev_data[INDEX_DAC_VCtrl_F_H] = data_buf[INDEX_DAC_VCtrl_F_H];
  11487. 8009124: f885 2058 strb.w r2, [r5, #88] ; 0x58
  11488. Prev_data[INDEX_DAC_VCtrl_F_L] = data_buf[INDEX_DAC_VCtrl_F_L];
  11489. 8009128: f894 3059 ldrb.w r3, [r4, #89] ; 0x59
  11490. 800912c: f885 3059 strb.w r3, [r5, #89] ; 0x59
  11491. ADC_Modify = 1;
  11492. 8009130: 2301 movs r3, #1
  11493. }
  11494. if((Prev_data[INDEX_DAC_VCtrl_G_H] != data_buf[INDEX_DAC_VCtrl_G_H])
  11495. 8009132: f894 205a ldrb.w r2, [r4, #90] ; 0x5a
  11496. 8009136: f895 105a ldrb.w r1, [r5, #90] ; 0x5a
  11497. 800913a: 4291 cmp r1, r2
  11498. 800913c: d105 bne.n 800914a <RF_Operate+0x772>
  11499. ||(Prev_data[INDEX_DAC_VCtrl_G_L] != data_buf[INDEX_DAC_VCtrl_G_L])){
  11500. 800913e: f895 005b ldrb.w r0, [r5, #91] ; 0x5b
  11501. 8009142: f894 105b ldrb.w r1, [r4, #91] ; 0x5b
  11502. 8009146: 4288 cmp r0, r1
  11503. 8009148: d006 beq.n 8009158 <RF_Operate+0x780>
  11504. ADC_Modify = 1;
  11505. Prev_data[INDEX_DAC_VCtrl_G_H] = data_buf[INDEX_DAC_VCtrl_G_H];
  11506. 800914a: f885 205a strb.w r2, [r5, #90] ; 0x5a
  11507. Prev_data[INDEX_DAC_VCtrl_G_L] = data_buf[INDEX_DAC_VCtrl_G_L];
  11508. 800914e: f894 305b ldrb.w r3, [r4, #91] ; 0x5b
  11509. 8009152: f885 305b strb.w r3, [r5, #91] ; 0x5b
  11510. ADC_Modify = 1;
  11511. 8009156: 2301 movs r3, #1
  11512. }
  11513. if((Prev_data[INDEX_DAC_VCtrl_H_H] != data_buf[INDEX_DAC_VCtrl_H_H])
  11514. 8009158: f894 205c ldrb.w r2, [r4, #92] ; 0x5c
  11515. 800915c: f895 105c ldrb.w r1, [r5, #92] ; 0x5c
  11516. 8009160: 4291 cmp r1, r2
  11517. 8009162: d105 bne.n 8009170 <RF_Operate+0x798>
  11518. ||(Prev_data[INDEX_DAC_VCtrl_H_L] != data_buf[INDEX_DAC_VCtrl_H_L])){
  11519. 8009164: f895 005d ldrb.w r0, [r5, #93] ; 0x5d
  11520. 8009168: f894 105d ldrb.w r1, [r4, #93] ; 0x5d
  11521. 800916c: 4288 cmp r0, r1
  11522. 800916e: d04a beq.n 8009206 <RF_Operate+0x82e>
  11523. ADC_Modify = 1;
  11524. Prev_data[INDEX_DAC_VCtrl_H_H] = data_buf[INDEX_DAC_VCtrl_H_H];
  11525. 8009170: f885 205c strb.w r2, [r5, #92] ; 0x5c
  11526. Prev_data[INDEX_DAC_VCtrl_H_L] = data_buf[INDEX_DAC_VCtrl_H_L];
  11527. 8009174: f894 305d ldrb.w r3, [r4, #93] ; 0x5d
  11528. 8009178: f885 305d strb.w r3, [r5, #93] ; 0x5d
  11529. // AD5318_Ctrl(0xA000);
  11530. // printf("DAC CTRL START \r\n");
  11531. // AD5318_Ctrl(0x800C);
  11532. // AD5318_Ctrl(0xA000);
  11533. // printf("DAC Change\r\n");
  11534. AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_A_H] << 8 | Prev_data[INDEX_DAC_VCtrl_A_L]));
  11535. 800917c: f895 304f ldrb.w r3, [r5, #79] ; 0x4f
  11536. 8009180: f895 004e ldrb.w r0, [r5, #78] ; 0x4e
  11537. 8009184: ea43 2000 orr.w r0, r3, r0, lsl #8
  11538. 8009188: f7fe f8a0 bl 80072cc <AD5318_Ctrl>
  11539. AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_B_H] << 8 | Prev_data[INDEX_DAC_VCtrl_B_L]));
  11540. 800918c: f895 3051 ldrb.w r3, [r5, #81] ; 0x51
  11541. 8009190: f895 0050 ldrb.w r0, [r5, #80] ; 0x50
  11542. 8009194: ea43 2000 orr.w r0, r3, r0, lsl #8
  11543. 8009198: f7fe f898 bl 80072cc <AD5318_Ctrl>
  11544. AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_C_H] << 8 | Prev_data[INDEX_DAC_VCtrl_C_L]));
  11545. 800919c: f895 3053 ldrb.w r3, [r5, #83] ; 0x53
  11546. 80091a0: f895 0052 ldrb.w r0, [r5, #82] ; 0x52
  11547. 80091a4: ea43 2000 orr.w r0, r3, r0, lsl #8
  11548. 80091a8: f7fe f890 bl 80072cc <AD5318_Ctrl>
  11549. AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_D_H] << 8 | Prev_data[INDEX_DAC_VCtrl_D_L]));
  11550. 80091ac: f895 3055 ldrb.w r3, [r5, #85] ; 0x55
  11551. 80091b0: f895 0054 ldrb.w r0, [r5, #84] ; 0x54
  11552. 80091b4: ea43 2000 orr.w r0, r3, r0, lsl #8
  11553. 80091b8: f7fe f888 bl 80072cc <AD5318_Ctrl>
  11554. AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_E_H] << 8 | Prev_data[INDEX_DAC_VCtrl_E_L]));
  11555. 80091bc: f895 3057 ldrb.w r3, [r5, #87] ; 0x57
  11556. 80091c0: f895 0056 ldrb.w r0, [r5, #86] ; 0x56
  11557. 80091c4: ea43 2000 orr.w r0, r3, r0, lsl #8
  11558. 80091c8: f7fe f880 bl 80072cc <AD5318_Ctrl>
  11559. AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_F_H] << 8 | Prev_data[INDEX_DAC_VCtrl_F_L]));
  11560. 80091cc: f895 3059 ldrb.w r3, [r5, #89] ; 0x59
  11561. 80091d0: f895 0058 ldrb.w r0, [r5, #88] ; 0x58
  11562. 80091d4: ea43 2000 orr.w r0, r3, r0, lsl #8
  11563. 80091d8: f7fe f878 bl 80072cc <AD5318_Ctrl>
  11564. AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_G_H] << 8 | Prev_data[INDEX_DAC_VCtrl_G_L]));
  11565. 80091dc: f895 305b ldrb.w r3, [r5, #91] ; 0x5b
  11566. 80091e0: f895 005a ldrb.w r0, [r5, #90] ; 0x5a
  11567. 80091e4: ea43 2000 orr.w r0, r3, r0, lsl #8
  11568. 80091e8: f7fe f870 bl 80072cc <AD5318_Ctrl>
  11569. AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_H_H] << 8 | Prev_data[INDEX_DAC_VCtrl_H_L]));
  11570. 80091ec: f895 005c ldrb.w r0, [r5, #92] ; 0x5c
  11571. 80091f0: f895 305d ldrb.w r3, [r5, #93] ; 0x5d
  11572. 80091f4: ea43 2000 orr.w r0, r3, r0, lsl #8
  11573. }
  11574. }
  11575. 80091f8: b022 add sp, #136 ; 0x88
  11576. 80091fa: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr}
  11577. AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_H_H] << 8 | Prev_data[INDEX_DAC_VCtrl_H_L]));
  11578. 80091fe: f7fe b865 b.w 80072cc <AD5318_Ctrl>
  11579. uint8_t ADC_Modify = 0;
  11580. 8009202: 2300 movs r3, #0
  11581. 8009204: e736 b.n 8009074 <RF_Operate+0x69c>
  11582. if(ADC_Modify){
  11583. 8009206: 2b00 cmp r3, #0
  11584. 8009208: d1b8 bne.n 800917c <RF_Operate+0x7a4>
  11585. }
  11586. 800920a: b022 add sp, #136 ; 0x88
  11587. 800920c: bd70 pop {r4, r5, r6, pc}
  11588. 800920e: bf00 nop
  11589. 08009210 <RF_Ctrl_Main>:
  11590. uint8_t temp_crc = 0;
  11591. bool RF_Ctrl_Main(uint8_t* data_buf){
  11592. 8009210: b570 push {r4, r5, r6, lr}
  11593. 8009212: 4604 mov r4, r0
  11594. bool ret = false;
  11595. Bluecell_Prot_t type = data_buf[Type];
  11596. 8009214: 7846 ldrb r6, [r0, #1]
  11597. ret = RF_Data_Check(&data_buf[Header]); /* ERROR CHECK */
  11598. 8009216: f7ff fb99 bl 800894c <RF_Data_Check>
  11599. if(ret == false){
  11600. 800921a: 4605 mov r5, r0
  11601. 800921c: b948 cbnz r0, 8009232 <RF_Ctrl_Main+0x22>
  11602. HAL_UART_Transmit(&huart1,&data_buf[INDEX_BLUE_HEADER],data_buf[INDEX_BLUE_LENGTH] + 2 + 1,3000);
  11603. 800921e: 78a2 ldrb r2, [r4, #2]
  11604. 8009220: f640 33b8 movw r3, #3000 ; 0xbb8
  11605. 8009224: 3203 adds r2, #3
  11606. 8009226: 4621 mov r1, r4
  11607. 8009228: 481a ldr r0, [pc, #104] ; (8009294 <RF_Ctrl_Main+0x84>)
  11608. 800922a: f7fd fe23 bl 8006e74 <HAL_UART_Transmit>
  11609. printf("Function : %s LINE : %d type : %d \r\n",__func__,__LINE__,type);
  11610. #endif
  11611. break;
  11612. }
  11613. return ret;
  11614. }
  11615. 800922e: 4628 mov r0, r5
  11616. 8009230: bd70 pop {r4, r5, r6, pc}
  11617. switch(type){
  11618. 8009232: 2e03 cmp r6, #3
  11619. 8009234: d8fb bhi.n 800922e <RF_Ctrl_Main+0x1e>
  11620. 8009236: e8df f006 tbb [pc, r6]
  11621. 800923a: 2002 .short 0x2002
  11622. 800923c: 2926 .short 0x2926
  11623. 800923e: 2300 movs r3, #0
  11624. printf("%02x ",data_buf[i]);
  11625. 8009240: 4e15 ldr r6, [pc, #84] ; (8009298 <RF_Ctrl_Main+0x88>)
  11626. for(uint8_t i =0 ; i < data_buf[Length] + 6; i++)
  11627. 8009242: 78a2 ldrb r2, [r4, #2]
  11628. 8009244: 1c5d adds r5, r3, #1
  11629. 8009246: 3205 adds r2, #5
  11630. 8009248: b2db uxtb r3, r3
  11631. 800924a: 429a cmp r2, r3
  11632. 800924c: da0f bge.n 800926e <RF_Ctrl_Main+0x5e>
  11633. printf("Reset Start \r\n");
  11634. 800924e: 4813 ldr r0, [pc, #76] ; (800929c <RF_Ctrl_Main+0x8c>)
  11635. 8009250: f000 fd64 bl 8009d1c <puts>
  11636. \details Acts as a special kind of Data Memory Barrier.
  11637. It completes when all explicit memory accesses before this instruction complete.
  11638. */
  11639. __attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
  11640. {
  11641. __ASM volatile ("dsb 0xF":::"memory");
  11642. 8009254: f3bf 8f4f dsb sy
  11643. (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
  11644. 8009258: 4911 ldr r1, [pc, #68] ; (80092a0 <RF_Ctrl_Main+0x90>)
  11645. SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
  11646. 800925a: 4b12 ldr r3, [pc, #72] ; (80092a4 <RF_Ctrl_Main+0x94>)
  11647. (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
  11648. 800925c: 68ca ldr r2, [r1, #12]
  11649. 800925e: f402 62e0 and.w r2, r2, #1792 ; 0x700
  11650. SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
  11651. 8009262: 4313 orrs r3, r2
  11652. 8009264: 60cb str r3, [r1, #12]
  11653. 8009266: f3bf 8f4f dsb sy
  11654. __ASM volatile ("nop");
  11655. 800926a: bf00 nop
  11656. 800926c: e7fd b.n 800926a <RF_Ctrl_Main+0x5a>
  11657. printf("%02x ",data_buf[i]);
  11658. 800926e: 5ce1 ldrb r1, [r4, r3]
  11659. 8009270: 4630 mov r0, r6
  11660. 8009272: f000 fcdf bl 8009c34 <iprintf>
  11661. 8009276: 462b mov r3, r5
  11662. 8009278: e7e3 b.n 8009242 <RF_Ctrl_Main+0x32>
  11663. RF_Operate(&data_buf[Header]);
  11664. 800927a: 4620 mov r0, r4
  11665. 800927c: f7ff fbac bl 80089d8 <RF_Operate>
  11666. RF_Status_Ack();
  11667. 8009280: f7ff fb8e bl 80089a0 <RF_Status_Ack>
  11668. break;
  11669. 8009284: e7d3 b.n 800922e <RF_Ctrl_Main+0x1e>
  11670. RF_Status_Get();
  11671. 8009286: f7ff fb6d bl 8008964 <RF_Status_Get>
  11672. break;
  11673. 800928a: e7d0 b.n 800922e <RF_Ctrl_Main+0x1e>
  11674. Bluecell_Flash_Write(&Prev_data[INDEX_BLUE_HEADER]);
  11675. 800928c: 4806 ldr r0, [pc, #24] ; (80092a8 <RF_Ctrl_Main+0x98>)
  11676. 800928e: f7fe fc09 bl 8007aa4 <Bluecell_Flash_Write>
  11677. 8009292: e7f5 b.n 8009280 <RF_Ctrl_Main+0x70>
  11678. 8009294: 200006c4 .word 0x200006c4
  11679. 8009298: 0800bcdf .word 0x0800bcdf
  11680. 800929c: 0800bce5 .word 0x0800bce5
  11681. 80092a0: e000ed00 .word 0xe000ed00
  11682. 80092a4: 05fa0004 .word 0x05fa0004
  11683. 80092a8: 20000574 .word 0x20000574
  11684. 080092ac <Reset_Handler>:
  11685. .weak Reset_Handler
  11686. .type Reset_Handler, %function
  11687. Reset_Handler:
  11688. /* Copy the data segment initializers from flash to SRAM */
  11689. movs r1, #0
  11690. 80092ac: 2100 movs r1, #0
  11691. b LoopCopyDataInit
  11692. 80092ae: e003 b.n 80092b8 <LoopCopyDataInit>
  11693. 080092b0 <CopyDataInit>:
  11694. CopyDataInit:
  11695. ldr r3, =_sidata
  11696. 80092b0: 4b0b ldr r3, [pc, #44] ; (80092e0 <LoopFillZerobss+0x14>)
  11697. ldr r3, [r3, r1]
  11698. 80092b2: 585b ldr r3, [r3, r1]
  11699. str r3, [r0, r1]
  11700. 80092b4: 5043 str r3, [r0, r1]
  11701. adds r1, r1, #4
  11702. 80092b6: 3104 adds r1, #4
  11703. 080092b8 <LoopCopyDataInit>:
  11704. LoopCopyDataInit:
  11705. ldr r0, =_sdata
  11706. 80092b8: 480a ldr r0, [pc, #40] ; (80092e4 <LoopFillZerobss+0x18>)
  11707. ldr r3, =_edata
  11708. 80092ba: 4b0b ldr r3, [pc, #44] ; (80092e8 <LoopFillZerobss+0x1c>)
  11709. adds r2, r0, r1
  11710. 80092bc: 1842 adds r2, r0, r1
  11711. cmp r2, r3
  11712. 80092be: 429a cmp r2, r3
  11713. bcc CopyDataInit
  11714. 80092c0: d3f6 bcc.n 80092b0 <CopyDataInit>
  11715. ldr r2, =_sbss
  11716. 80092c2: 4a0a ldr r2, [pc, #40] ; (80092ec <LoopFillZerobss+0x20>)
  11717. b LoopFillZerobss
  11718. 80092c4: e002 b.n 80092cc <LoopFillZerobss>
  11719. 080092c6 <FillZerobss>:
  11720. /* Zero fill the bss segment. */
  11721. FillZerobss:
  11722. movs r3, #0
  11723. 80092c6: 2300 movs r3, #0
  11724. str r3, [r2], #4
  11725. 80092c8: f842 3b04 str.w r3, [r2], #4
  11726. 080092cc <LoopFillZerobss>:
  11727. LoopFillZerobss:
  11728. ldr r3, = _ebss
  11729. 80092cc: 4b08 ldr r3, [pc, #32] ; (80092f0 <LoopFillZerobss+0x24>)
  11730. cmp r2, r3
  11731. 80092ce: 429a cmp r2, r3
  11732. bcc FillZerobss
  11733. 80092d0: d3f9 bcc.n 80092c6 <FillZerobss>
  11734. /* Call the clock system intitialization function.*/
  11735. bl SystemInit
  11736. 80092d2: f7ff fa9b bl 800880c <SystemInit>
  11737. /* Call static constructors */
  11738. bl __libc_init_array
  11739. 80092d6: f000 f815 bl 8009304 <__libc_init_array>
  11740. /* Call the application's entry point.*/
  11741. bl main
  11742. 80092da: f7fe fe03 bl 8007ee4 <main>
  11743. bx lr
  11744. 80092de: 4770 bx lr
  11745. ldr r3, =_sidata
  11746. 80092e0: 0800bfe8 .word 0x0800bfe8
  11747. ldr r0, =_sdata
  11748. 80092e4: 20000000 .word 0x20000000
  11749. ldr r3, =_edata
  11750. 80092e8: 20000404 .word 0x20000404
  11751. ldr r2, =_sbss
  11752. 80092ec: 20000408 .word 0x20000408
  11753. ldr r3, = _ebss
  11754. 80092f0: 200017a8 .word 0x200017a8
  11755. 080092f4 <ADC1_2_IRQHandler>:
  11756. * @retval : None
  11757. */
  11758. .section .text.Default_Handler,"ax",%progbits
  11759. Default_Handler:
  11760. Infinite_Loop:
  11761. b Infinite_Loop
  11762. 80092f4: e7fe b.n 80092f4 <ADC1_2_IRQHandler>
  11763. ...
  11764. 080092f8 <__errno>:
  11765. 80092f8: 4b01 ldr r3, [pc, #4] ; (8009300 <__errno+0x8>)
  11766. 80092fa: 6818 ldr r0, [r3, #0]
  11767. 80092fc: 4770 bx lr
  11768. 80092fe: bf00 nop
  11769. 8009300: 20000234 .word 0x20000234
  11770. 08009304 <__libc_init_array>:
  11771. 8009304: b570 push {r4, r5, r6, lr}
  11772. 8009306: 2500 movs r5, #0
  11773. 8009308: 4e0c ldr r6, [pc, #48] ; (800933c <__libc_init_array+0x38>)
  11774. 800930a: 4c0d ldr r4, [pc, #52] ; (8009340 <__libc_init_array+0x3c>)
  11775. 800930c: 1ba4 subs r4, r4, r6
  11776. 800930e: 10a4 asrs r4, r4, #2
  11777. 8009310: 42a5 cmp r5, r4
  11778. 8009312: d109 bne.n 8009328 <__libc_init_array+0x24>
  11779. 8009314: f002 fc8a bl 800bc2c <_init>
  11780. 8009318: 2500 movs r5, #0
  11781. 800931a: 4e0a ldr r6, [pc, #40] ; (8009344 <__libc_init_array+0x40>)
  11782. 800931c: 4c0a ldr r4, [pc, #40] ; (8009348 <__libc_init_array+0x44>)
  11783. 800931e: 1ba4 subs r4, r4, r6
  11784. 8009320: 10a4 asrs r4, r4, #2
  11785. 8009322: 42a5 cmp r5, r4
  11786. 8009324: d105 bne.n 8009332 <__libc_init_array+0x2e>
  11787. 8009326: bd70 pop {r4, r5, r6, pc}
  11788. 8009328: f856 3025 ldr.w r3, [r6, r5, lsl #2]
  11789. 800932c: 4798 blx r3
  11790. 800932e: 3501 adds r5, #1
  11791. 8009330: e7ee b.n 8009310 <__libc_init_array+0xc>
  11792. 8009332: f856 3025 ldr.w r3, [r6, r5, lsl #2]
  11793. 8009336: 4798 blx r3
  11794. 8009338: 3501 adds r5, #1
  11795. 800933a: e7f2 b.n 8009322 <__libc_init_array+0x1e>
  11796. 800933c: 0800bfe0 .word 0x0800bfe0
  11797. 8009340: 0800bfe0 .word 0x0800bfe0
  11798. 8009344: 0800bfe0 .word 0x0800bfe0
  11799. 8009348: 0800bfe4 .word 0x0800bfe4
  11800. 0800934c <memcpy>:
  11801. 800934c: b510 push {r4, lr}
  11802. 800934e: 1e43 subs r3, r0, #1
  11803. 8009350: 440a add r2, r1
  11804. 8009352: 4291 cmp r1, r2
  11805. 8009354: d100 bne.n 8009358 <memcpy+0xc>
  11806. 8009356: bd10 pop {r4, pc}
  11807. 8009358: f811 4b01 ldrb.w r4, [r1], #1
  11808. 800935c: f803 4f01 strb.w r4, [r3, #1]!
  11809. 8009360: e7f7 b.n 8009352 <memcpy+0x6>
  11810. 08009362 <memset>:
  11811. 8009362: 4603 mov r3, r0
  11812. 8009364: 4402 add r2, r0
  11813. 8009366: 4293 cmp r3, r2
  11814. 8009368: d100 bne.n 800936c <memset+0xa>
  11815. 800936a: 4770 bx lr
  11816. 800936c: f803 1b01 strb.w r1, [r3], #1
  11817. 8009370: e7f9 b.n 8009366 <memset+0x4>
  11818. 08009372 <__cvt>:
  11819. 8009372: 2b00 cmp r3, #0
  11820. 8009374: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
  11821. 8009378: 461e mov r6, r3
  11822. 800937a: bfbb ittet lt
  11823. 800937c: f103 4300 addlt.w r3, r3, #2147483648 ; 0x80000000
  11824. 8009380: 461e movlt r6, r3
  11825. 8009382: 2300 movge r3, #0
  11826. 8009384: 232d movlt r3, #45 ; 0x2d
  11827. 8009386: b088 sub sp, #32
  11828. 8009388: 9f14 ldr r7, [sp, #80] ; 0x50
  11829. 800938a: 9912 ldr r1, [sp, #72] ; 0x48
  11830. 800938c: f027 0720 bic.w r7, r7, #32
  11831. 8009390: 2f46 cmp r7, #70 ; 0x46
  11832. 8009392: 4614 mov r4, r2
  11833. 8009394: 9d10 ldr r5, [sp, #64] ; 0x40
  11834. 8009396: f8dd a04c ldr.w sl, [sp, #76] ; 0x4c
  11835. 800939a: 700b strb r3, [r1, #0]
  11836. 800939c: d004 beq.n 80093a8 <__cvt+0x36>
  11837. 800939e: 2f45 cmp r7, #69 ; 0x45
  11838. 80093a0: d100 bne.n 80093a4 <__cvt+0x32>
  11839. 80093a2: 3501 adds r5, #1
  11840. 80093a4: 2302 movs r3, #2
  11841. 80093a6: e000 b.n 80093aa <__cvt+0x38>
  11842. 80093a8: 2303 movs r3, #3
  11843. 80093aa: aa07 add r2, sp, #28
  11844. 80093ac: 9204 str r2, [sp, #16]
  11845. 80093ae: aa06 add r2, sp, #24
  11846. 80093b0: 9203 str r2, [sp, #12]
  11847. 80093b2: e88d 0428 stmia.w sp, {r3, r5, sl}
  11848. 80093b6: 4622 mov r2, r4
  11849. 80093b8: 4633 mov r3, r6
  11850. 80093ba: f000 feb9 bl 800a130 <_dtoa_r>
  11851. 80093be: 2f47 cmp r7, #71 ; 0x47
  11852. 80093c0: 4680 mov r8, r0
  11853. 80093c2: d102 bne.n 80093ca <__cvt+0x58>
  11854. 80093c4: 9b11 ldr r3, [sp, #68] ; 0x44
  11855. 80093c6: 07db lsls r3, r3, #31
  11856. 80093c8: d526 bpl.n 8009418 <__cvt+0xa6>
  11857. 80093ca: 2f46 cmp r7, #70 ; 0x46
  11858. 80093cc: eb08 0905 add.w r9, r8, r5
  11859. 80093d0: d111 bne.n 80093f6 <__cvt+0x84>
  11860. 80093d2: f898 3000 ldrb.w r3, [r8]
  11861. 80093d6: 2b30 cmp r3, #48 ; 0x30
  11862. 80093d8: d10a bne.n 80093f0 <__cvt+0x7e>
  11863. 80093da: 2200 movs r2, #0
  11864. 80093dc: 2300 movs r3, #0
  11865. 80093de: 4620 mov r0, r4
  11866. 80093e0: 4631 mov r1, r6
  11867. 80093e2: f7fb fb55 bl 8004a90 <__aeabi_dcmpeq>
  11868. 80093e6: b918 cbnz r0, 80093f0 <__cvt+0x7e>
  11869. 80093e8: f1c5 0501 rsb r5, r5, #1
  11870. 80093ec: f8ca 5000 str.w r5, [sl]
  11871. 80093f0: f8da 3000 ldr.w r3, [sl]
  11872. 80093f4: 4499 add r9, r3
  11873. 80093f6: 2200 movs r2, #0
  11874. 80093f8: 2300 movs r3, #0
  11875. 80093fa: 4620 mov r0, r4
  11876. 80093fc: 4631 mov r1, r6
  11877. 80093fe: f7fb fb47 bl 8004a90 <__aeabi_dcmpeq>
  11878. 8009402: b938 cbnz r0, 8009414 <__cvt+0xa2>
  11879. 8009404: 2230 movs r2, #48 ; 0x30
  11880. 8009406: 9b07 ldr r3, [sp, #28]
  11881. 8009408: 4599 cmp r9, r3
  11882. 800940a: d905 bls.n 8009418 <__cvt+0xa6>
  11883. 800940c: 1c59 adds r1, r3, #1
  11884. 800940e: 9107 str r1, [sp, #28]
  11885. 8009410: 701a strb r2, [r3, #0]
  11886. 8009412: e7f8 b.n 8009406 <__cvt+0x94>
  11887. 8009414: f8cd 901c str.w r9, [sp, #28]
  11888. 8009418: 4640 mov r0, r8
  11889. 800941a: 9b07 ldr r3, [sp, #28]
  11890. 800941c: 9a15 ldr r2, [sp, #84] ; 0x54
  11891. 800941e: eba3 0308 sub.w r3, r3, r8
  11892. 8009422: 6013 str r3, [r2, #0]
  11893. 8009424: b008 add sp, #32
  11894. 8009426: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
  11895. 0800942a <__exponent>:
  11896. 800942a: 4603 mov r3, r0
  11897. 800942c: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
  11898. 800942e: 2900 cmp r1, #0
  11899. 8009430: f803 2b02 strb.w r2, [r3], #2
  11900. 8009434: bfb6 itet lt
  11901. 8009436: 222d movlt r2, #45 ; 0x2d
  11902. 8009438: 222b movge r2, #43 ; 0x2b
  11903. 800943a: 4249 neglt r1, r1
  11904. 800943c: 2909 cmp r1, #9
  11905. 800943e: 7042 strb r2, [r0, #1]
  11906. 8009440: dd21 ble.n 8009486 <__exponent+0x5c>
  11907. 8009442: f10d 0207 add.w r2, sp, #7
  11908. 8009446: 4617 mov r7, r2
  11909. 8009448: 260a movs r6, #10
  11910. 800944a: fb91 f5f6 sdiv r5, r1, r6
  11911. 800944e: fb06 1115 mls r1, r6, r5, r1
  11912. 8009452: 2d09 cmp r5, #9
  11913. 8009454: f101 0130 add.w r1, r1, #48 ; 0x30
  11914. 8009458: f802 1c01 strb.w r1, [r2, #-1]
  11915. 800945c: f102 34ff add.w r4, r2, #4294967295
  11916. 8009460: 4629 mov r1, r5
  11917. 8009462: dc09 bgt.n 8009478 <__exponent+0x4e>
  11918. 8009464: 3130 adds r1, #48 ; 0x30
  11919. 8009466: 3a02 subs r2, #2
  11920. 8009468: f804 1c01 strb.w r1, [r4, #-1]
  11921. 800946c: 42ba cmp r2, r7
  11922. 800946e: 461c mov r4, r3
  11923. 8009470: d304 bcc.n 800947c <__exponent+0x52>
  11924. 8009472: 1a20 subs r0, r4, r0
  11925. 8009474: b003 add sp, #12
  11926. 8009476: bdf0 pop {r4, r5, r6, r7, pc}
  11927. 8009478: 4622 mov r2, r4
  11928. 800947a: e7e6 b.n 800944a <__exponent+0x20>
  11929. 800947c: f812 1b01 ldrb.w r1, [r2], #1
  11930. 8009480: f803 1b01 strb.w r1, [r3], #1
  11931. 8009484: e7f2 b.n 800946c <__exponent+0x42>
  11932. 8009486: 2230 movs r2, #48 ; 0x30
  11933. 8009488: 461c mov r4, r3
  11934. 800948a: 4411 add r1, r2
  11935. 800948c: f804 2b02 strb.w r2, [r4], #2
  11936. 8009490: 7059 strb r1, [r3, #1]
  11937. 8009492: e7ee b.n 8009472 <__exponent+0x48>
  11938. 08009494 <_printf_float>:
  11939. 8009494: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
  11940. 8009498: b091 sub sp, #68 ; 0x44
  11941. 800949a: 460c mov r4, r1
  11942. 800949c: 9f1a ldr r7, [sp, #104] ; 0x68
  11943. 800949e: 4693 mov fp, r2
  11944. 80094a0: 461e mov r6, r3
  11945. 80094a2: 4605 mov r5, r0
  11946. 80094a4: f001 fd94 bl 800afd0 <_localeconv_r>
  11947. 80094a8: 6803 ldr r3, [r0, #0]
  11948. 80094aa: 4618 mov r0, r3
  11949. 80094ac: 9309 str r3, [sp, #36] ; 0x24
  11950. 80094ae: f7fa febb bl 8004228 <strlen>
  11951. 80094b2: 2300 movs r3, #0
  11952. 80094b4: 930e str r3, [sp, #56] ; 0x38
  11953. 80094b6: 683b ldr r3, [r7, #0]
  11954. 80094b8: 900a str r0, [sp, #40] ; 0x28
  11955. 80094ba: 3307 adds r3, #7
  11956. 80094bc: f023 0307 bic.w r3, r3, #7
  11957. 80094c0: f103 0208 add.w r2, r3, #8
  11958. 80094c4: f894 8018 ldrb.w r8, [r4, #24]
  11959. 80094c8: f8d4 a000 ldr.w sl, [r4]
  11960. 80094cc: 603a str r2, [r7, #0]
  11961. 80094ce: e9d3 2300 ldrd r2, r3, [r3]
  11962. 80094d2: e9c4 2312 strd r2, r3, [r4, #72] ; 0x48
  11963. 80094d6: f8d4 904c ldr.w r9, [r4, #76] ; 0x4c
  11964. 80094da: 6ca7 ldr r7, [r4, #72] ; 0x48
  11965. 80094dc: f029 4300 bic.w r3, r9, #2147483648 ; 0x80000000
  11966. 80094e0: 930b str r3, [sp, #44] ; 0x2c
  11967. 80094e2: f04f 32ff mov.w r2, #4294967295
  11968. 80094e6: 4ba6 ldr r3, [pc, #664] ; (8009780 <_printf_float+0x2ec>)
  11969. 80094e8: 4638 mov r0, r7
  11970. 80094ea: 990b ldr r1, [sp, #44] ; 0x2c
  11971. 80094ec: f7fb fb02 bl 8004af4 <__aeabi_dcmpun>
  11972. 80094f0: 2800 cmp r0, #0
  11973. 80094f2: f040 81f7 bne.w 80098e4 <_printf_float+0x450>
  11974. 80094f6: f04f 32ff mov.w r2, #4294967295
  11975. 80094fa: 4ba1 ldr r3, [pc, #644] ; (8009780 <_printf_float+0x2ec>)
  11976. 80094fc: 4638 mov r0, r7
  11977. 80094fe: 990b ldr r1, [sp, #44] ; 0x2c
  11978. 8009500: f7fb fada bl 8004ab8 <__aeabi_dcmple>
  11979. 8009504: 2800 cmp r0, #0
  11980. 8009506: f040 81ed bne.w 80098e4 <_printf_float+0x450>
  11981. 800950a: 2200 movs r2, #0
  11982. 800950c: 2300 movs r3, #0
  11983. 800950e: 4638 mov r0, r7
  11984. 8009510: 4649 mov r1, r9
  11985. 8009512: f7fb fac7 bl 8004aa4 <__aeabi_dcmplt>
  11986. 8009516: b110 cbz r0, 800951e <_printf_float+0x8a>
  11987. 8009518: 232d movs r3, #45 ; 0x2d
  11988. 800951a: f884 3043 strb.w r3, [r4, #67] ; 0x43
  11989. 800951e: 4b99 ldr r3, [pc, #612] ; (8009784 <_printf_float+0x2f0>)
  11990. 8009520: 4f99 ldr r7, [pc, #612] ; (8009788 <_printf_float+0x2f4>)
  11991. 8009522: f1b8 0f47 cmp.w r8, #71 ; 0x47
  11992. 8009526: bf98 it ls
  11993. 8009528: 461f movls r7, r3
  11994. 800952a: 2303 movs r3, #3
  11995. 800952c: f04f 0900 mov.w r9, #0
  11996. 8009530: 6123 str r3, [r4, #16]
  11997. 8009532: f02a 0304 bic.w r3, sl, #4
  11998. 8009536: 6023 str r3, [r4, #0]
  11999. 8009538: 9600 str r6, [sp, #0]
  12000. 800953a: 465b mov r3, fp
  12001. 800953c: aa0f add r2, sp, #60 ; 0x3c
  12002. 800953e: 4621 mov r1, r4
  12003. 8009540: 4628 mov r0, r5
  12004. 8009542: f000 f9df bl 8009904 <_printf_common>
  12005. 8009546: 3001 adds r0, #1
  12006. 8009548: f040 809a bne.w 8009680 <_printf_float+0x1ec>
  12007. 800954c: f04f 30ff mov.w r0, #4294967295
  12008. 8009550: b011 add sp, #68 ; 0x44
  12009. 8009552: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
  12010. 8009556: 6862 ldr r2, [r4, #4]
  12011. 8009558: a80e add r0, sp, #56 ; 0x38
  12012. 800955a: 1c53 adds r3, r2, #1
  12013. 800955c: f10d 0e34 add.w lr, sp, #52 ; 0x34
  12014. 8009560: f44a 6380 orr.w r3, sl, #1024 ; 0x400
  12015. 8009564: d141 bne.n 80095ea <_printf_float+0x156>
  12016. 8009566: 2206 movs r2, #6
  12017. 8009568: 6062 str r2, [r4, #4]
  12018. 800956a: 2100 movs r1, #0
  12019. 800956c: 6023 str r3, [r4, #0]
  12020. 800956e: 9301 str r3, [sp, #4]
  12021. 8009570: 6863 ldr r3, [r4, #4]
  12022. 8009572: f10d 0233 add.w r2, sp, #51 ; 0x33
  12023. 8009576: 9005 str r0, [sp, #20]
  12024. 8009578: 9202 str r2, [sp, #8]
  12025. 800957a: 9300 str r3, [sp, #0]
  12026. 800957c: 463a mov r2, r7
  12027. 800957e: 464b mov r3, r9
  12028. 8009580: 9106 str r1, [sp, #24]
  12029. 8009582: f8cd 8010 str.w r8, [sp, #16]
  12030. 8009586: f8cd e00c str.w lr, [sp, #12]
  12031. 800958a: 4628 mov r0, r5
  12032. 800958c: f7ff fef1 bl 8009372 <__cvt>
  12033. 8009590: f008 03df and.w r3, r8, #223 ; 0xdf
  12034. 8009594: 2b47 cmp r3, #71 ; 0x47
  12035. 8009596: 4607 mov r7, r0
  12036. 8009598: d109 bne.n 80095ae <_printf_float+0x11a>
  12037. 800959a: 9b0d ldr r3, [sp, #52] ; 0x34
  12038. 800959c: 1cd8 adds r0, r3, #3
  12039. 800959e: db02 blt.n 80095a6 <_printf_float+0x112>
  12040. 80095a0: 6862 ldr r2, [r4, #4]
  12041. 80095a2: 4293 cmp r3, r2
  12042. 80095a4: dd59 ble.n 800965a <_printf_float+0x1c6>
  12043. 80095a6: f1a8 0802 sub.w r8, r8, #2
  12044. 80095aa: fa5f f888 uxtb.w r8, r8
  12045. 80095ae: f1b8 0f65 cmp.w r8, #101 ; 0x65
  12046. 80095b2: 990d ldr r1, [sp, #52] ; 0x34
  12047. 80095b4: d836 bhi.n 8009624 <_printf_float+0x190>
  12048. 80095b6: 3901 subs r1, #1
  12049. 80095b8: 4642 mov r2, r8
  12050. 80095ba: f104 0050 add.w r0, r4, #80 ; 0x50
  12051. 80095be: 910d str r1, [sp, #52] ; 0x34
  12052. 80095c0: f7ff ff33 bl 800942a <__exponent>
  12053. 80095c4: 9a0e ldr r2, [sp, #56] ; 0x38
  12054. 80095c6: 4681 mov r9, r0
  12055. 80095c8: 1883 adds r3, r0, r2
  12056. 80095ca: 2a01 cmp r2, #1
  12057. 80095cc: 6123 str r3, [r4, #16]
  12058. 80095ce: dc02 bgt.n 80095d6 <_printf_float+0x142>
  12059. 80095d0: 6822 ldr r2, [r4, #0]
  12060. 80095d2: 07d1 lsls r1, r2, #31
  12061. 80095d4: d501 bpl.n 80095da <_printf_float+0x146>
  12062. 80095d6: 3301 adds r3, #1
  12063. 80095d8: 6123 str r3, [r4, #16]
  12064. 80095da: f89d 3033 ldrb.w r3, [sp, #51] ; 0x33
  12065. 80095de: 2b00 cmp r3, #0
  12066. 80095e0: d0aa beq.n 8009538 <_printf_float+0xa4>
  12067. 80095e2: 232d movs r3, #45 ; 0x2d
  12068. 80095e4: f884 3043 strb.w r3, [r4, #67] ; 0x43
  12069. 80095e8: e7a6 b.n 8009538 <_printf_float+0xa4>
  12070. 80095ea: f1b8 0f67 cmp.w r8, #103 ; 0x67
  12071. 80095ee: d002 beq.n 80095f6 <_printf_float+0x162>
  12072. 80095f0: f1b8 0f47 cmp.w r8, #71 ; 0x47
  12073. 80095f4: d1b9 bne.n 800956a <_printf_float+0xd6>
  12074. 80095f6: b19a cbz r2, 8009620 <_printf_float+0x18c>
  12075. 80095f8: 2100 movs r1, #0
  12076. 80095fa: 9106 str r1, [sp, #24]
  12077. 80095fc: f10d 0133 add.w r1, sp, #51 ; 0x33
  12078. 8009600: e88d 000c stmia.w sp, {r2, r3}
  12079. 8009604: 6023 str r3, [r4, #0]
  12080. 8009606: 9005 str r0, [sp, #20]
  12081. 8009608: 463a mov r2, r7
  12082. 800960a: f8cd 8010 str.w r8, [sp, #16]
  12083. 800960e: f8cd e00c str.w lr, [sp, #12]
  12084. 8009612: 9102 str r1, [sp, #8]
  12085. 8009614: 464b mov r3, r9
  12086. 8009616: 4628 mov r0, r5
  12087. 8009618: f7ff feab bl 8009372 <__cvt>
  12088. 800961c: 4607 mov r7, r0
  12089. 800961e: e7bc b.n 800959a <_printf_float+0x106>
  12090. 8009620: 2201 movs r2, #1
  12091. 8009622: e7a1 b.n 8009568 <_printf_float+0xd4>
  12092. 8009624: f1b8 0f66 cmp.w r8, #102 ; 0x66
  12093. 8009628: d119 bne.n 800965e <_printf_float+0x1ca>
  12094. 800962a: 2900 cmp r1, #0
  12095. 800962c: 6863 ldr r3, [r4, #4]
  12096. 800962e: dd0c ble.n 800964a <_printf_float+0x1b6>
  12097. 8009630: 6121 str r1, [r4, #16]
  12098. 8009632: b913 cbnz r3, 800963a <_printf_float+0x1a6>
  12099. 8009634: 6822 ldr r2, [r4, #0]
  12100. 8009636: 07d2 lsls r2, r2, #31
  12101. 8009638: d502 bpl.n 8009640 <_printf_float+0x1ac>
  12102. 800963a: 3301 adds r3, #1
  12103. 800963c: 440b add r3, r1
  12104. 800963e: 6123 str r3, [r4, #16]
  12105. 8009640: 9b0d ldr r3, [sp, #52] ; 0x34
  12106. 8009642: f04f 0900 mov.w r9, #0
  12107. 8009646: 65a3 str r3, [r4, #88] ; 0x58
  12108. 8009648: e7c7 b.n 80095da <_printf_float+0x146>
  12109. 800964a: b913 cbnz r3, 8009652 <_printf_float+0x1be>
  12110. 800964c: 6822 ldr r2, [r4, #0]
  12111. 800964e: 07d0 lsls r0, r2, #31
  12112. 8009650: d501 bpl.n 8009656 <_printf_float+0x1c2>
  12113. 8009652: 3302 adds r3, #2
  12114. 8009654: e7f3 b.n 800963e <_printf_float+0x1aa>
  12115. 8009656: 2301 movs r3, #1
  12116. 8009658: e7f1 b.n 800963e <_printf_float+0x1aa>
  12117. 800965a: f04f 0867 mov.w r8, #103 ; 0x67
  12118. 800965e: 9b0d ldr r3, [sp, #52] ; 0x34
  12119. 8009660: 9a0e ldr r2, [sp, #56] ; 0x38
  12120. 8009662: 4293 cmp r3, r2
  12121. 8009664: db05 blt.n 8009672 <_printf_float+0x1de>
  12122. 8009666: 6822 ldr r2, [r4, #0]
  12123. 8009668: 6123 str r3, [r4, #16]
  12124. 800966a: 07d1 lsls r1, r2, #31
  12125. 800966c: d5e8 bpl.n 8009640 <_printf_float+0x1ac>
  12126. 800966e: 3301 adds r3, #1
  12127. 8009670: e7e5 b.n 800963e <_printf_float+0x1aa>
  12128. 8009672: 2b00 cmp r3, #0
  12129. 8009674: bfcc ite gt
  12130. 8009676: 2301 movgt r3, #1
  12131. 8009678: f1c3 0302 rsble r3, r3, #2
  12132. 800967c: 4413 add r3, r2
  12133. 800967e: e7de b.n 800963e <_printf_float+0x1aa>
  12134. 8009680: 6823 ldr r3, [r4, #0]
  12135. 8009682: 055a lsls r2, r3, #21
  12136. 8009684: d407 bmi.n 8009696 <_printf_float+0x202>
  12137. 8009686: 6923 ldr r3, [r4, #16]
  12138. 8009688: 463a mov r2, r7
  12139. 800968a: 4659 mov r1, fp
  12140. 800968c: 4628 mov r0, r5
  12141. 800968e: 47b0 blx r6
  12142. 8009690: 3001 adds r0, #1
  12143. 8009692: d12a bne.n 80096ea <_printf_float+0x256>
  12144. 8009694: e75a b.n 800954c <_printf_float+0xb8>
  12145. 8009696: f1b8 0f65 cmp.w r8, #101 ; 0x65
  12146. 800969a: f240 80dc bls.w 8009856 <_printf_float+0x3c2>
  12147. 800969e: e9d4 0112 ldrd r0, r1, [r4, #72] ; 0x48
  12148. 80096a2: 2200 movs r2, #0
  12149. 80096a4: 2300 movs r3, #0
  12150. 80096a6: f7fb f9f3 bl 8004a90 <__aeabi_dcmpeq>
  12151. 80096aa: 2800 cmp r0, #0
  12152. 80096ac: d039 beq.n 8009722 <_printf_float+0x28e>
  12153. 80096ae: 2301 movs r3, #1
  12154. 80096b0: 4a36 ldr r2, [pc, #216] ; (800978c <_printf_float+0x2f8>)
  12155. 80096b2: 4659 mov r1, fp
  12156. 80096b4: 4628 mov r0, r5
  12157. 80096b6: 47b0 blx r6
  12158. 80096b8: 3001 adds r0, #1
  12159. 80096ba: f43f af47 beq.w 800954c <_printf_float+0xb8>
  12160. 80096be: 9b0e ldr r3, [sp, #56] ; 0x38
  12161. 80096c0: 9a0d ldr r2, [sp, #52] ; 0x34
  12162. 80096c2: 429a cmp r2, r3
  12163. 80096c4: db02 blt.n 80096cc <_printf_float+0x238>
  12164. 80096c6: 6823 ldr r3, [r4, #0]
  12165. 80096c8: 07d8 lsls r0, r3, #31
  12166. 80096ca: d50e bpl.n 80096ea <_printf_float+0x256>
  12167. 80096cc: 9b0a ldr r3, [sp, #40] ; 0x28
  12168. 80096ce: 9a09 ldr r2, [sp, #36] ; 0x24
  12169. 80096d0: 4659 mov r1, fp
  12170. 80096d2: 4628 mov r0, r5
  12171. 80096d4: 47b0 blx r6
  12172. 80096d6: 3001 adds r0, #1
  12173. 80096d8: f43f af38 beq.w 800954c <_printf_float+0xb8>
  12174. 80096dc: 2700 movs r7, #0
  12175. 80096de: f104 081a add.w r8, r4, #26
  12176. 80096e2: 9b0e ldr r3, [sp, #56] ; 0x38
  12177. 80096e4: 3b01 subs r3, #1
  12178. 80096e6: 429f cmp r7, r3
  12179. 80096e8: db11 blt.n 800970e <_printf_float+0x27a>
  12180. 80096ea: 6823 ldr r3, [r4, #0]
  12181. 80096ec: 079f lsls r7, r3, #30
  12182. 80096ee: d508 bpl.n 8009702 <_printf_float+0x26e>
  12183. 80096f0: 2700 movs r7, #0
  12184. 80096f2: f104 0819 add.w r8, r4, #25
  12185. 80096f6: 68e3 ldr r3, [r4, #12]
  12186. 80096f8: 9a0f ldr r2, [sp, #60] ; 0x3c
  12187. 80096fa: 1a9b subs r3, r3, r2
  12188. 80096fc: 429f cmp r7, r3
  12189. 80096fe: f2c0 80e7 blt.w 80098d0 <_printf_float+0x43c>
  12190. 8009702: 68e0 ldr r0, [r4, #12]
  12191. 8009704: 9b0f ldr r3, [sp, #60] ; 0x3c
  12192. 8009706: 4298 cmp r0, r3
  12193. 8009708: bfb8 it lt
  12194. 800970a: 4618 movlt r0, r3
  12195. 800970c: e720 b.n 8009550 <_printf_float+0xbc>
  12196. 800970e: 2301 movs r3, #1
  12197. 8009710: 4642 mov r2, r8
  12198. 8009712: 4659 mov r1, fp
  12199. 8009714: 4628 mov r0, r5
  12200. 8009716: 47b0 blx r6
  12201. 8009718: 3001 adds r0, #1
  12202. 800971a: f43f af17 beq.w 800954c <_printf_float+0xb8>
  12203. 800971e: 3701 adds r7, #1
  12204. 8009720: e7df b.n 80096e2 <_printf_float+0x24e>
  12205. 8009722: 9b0d ldr r3, [sp, #52] ; 0x34
  12206. 8009724: 2b00 cmp r3, #0
  12207. 8009726: dc33 bgt.n 8009790 <_printf_float+0x2fc>
  12208. 8009728: 2301 movs r3, #1
  12209. 800972a: 4a18 ldr r2, [pc, #96] ; (800978c <_printf_float+0x2f8>)
  12210. 800972c: 4659 mov r1, fp
  12211. 800972e: 4628 mov r0, r5
  12212. 8009730: 47b0 blx r6
  12213. 8009732: 3001 adds r0, #1
  12214. 8009734: f43f af0a beq.w 800954c <_printf_float+0xb8>
  12215. 8009738: 9b0d ldr r3, [sp, #52] ; 0x34
  12216. 800973a: b923 cbnz r3, 8009746 <_printf_float+0x2b2>
  12217. 800973c: 9b0e ldr r3, [sp, #56] ; 0x38
  12218. 800973e: b913 cbnz r3, 8009746 <_printf_float+0x2b2>
  12219. 8009740: 6823 ldr r3, [r4, #0]
  12220. 8009742: 07d9 lsls r1, r3, #31
  12221. 8009744: d5d1 bpl.n 80096ea <_printf_float+0x256>
  12222. 8009746: 9b0a ldr r3, [sp, #40] ; 0x28
  12223. 8009748: 9a09 ldr r2, [sp, #36] ; 0x24
  12224. 800974a: 4659 mov r1, fp
  12225. 800974c: 4628 mov r0, r5
  12226. 800974e: 47b0 blx r6
  12227. 8009750: 3001 adds r0, #1
  12228. 8009752: f43f aefb beq.w 800954c <_printf_float+0xb8>
  12229. 8009756: f04f 0800 mov.w r8, #0
  12230. 800975a: f104 091a add.w r9, r4, #26
  12231. 800975e: 9b0d ldr r3, [sp, #52] ; 0x34
  12232. 8009760: 425b negs r3, r3
  12233. 8009762: 4598 cmp r8, r3
  12234. 8009764: db01 blt.n 800976a <_printf_float+0x2d6>
  12235. 8009766: 9b0e ldr r3, [sp, #56] ; 0x38
  12236. 8009768: e78e b.n 8009688 <_printf_float+0x1f4>
  12237. 800976a: 2301 movs r3, #1
  12238. 800976c: 464a mov r2, r9
  12239. 800976e: 4659 mov r1, fp
  12240. 8009770: 4628 mov r0, r5
  12241. 8009772: 47b0 blx r6
  12242. 8009774: 3001 adds r0, #1
  12243. 8009776: f43f aee9 beq.w 800954c <_printf_float+0xb8>
  12244. 800977a: f108 0801 add.w r8, r8, #1
  12245. 800977e: e7ee b.n 800975e <_printf_float+0x2ca>
  12246. 8009780: 7fefffff .word 0x7fefffff
  12247. 8009784: 0800bd1c .word 0x0800bd1c
  12248. 8009788: 0800bd20 .word 0x0800bd20
  12249. 800978c: 0800bd2c .word 0x0800bd2c
  12250. 8009790: 9a0e ldr r2, [sp, #56] ; 0x38
  12251. 8009792: 6da3 ldr r3, [r4, #88] ; 0x58
  12252. 8009794: 429a cmp r2, r3
  12253. 8009796: bfa8 it ge
  12254. 8009798: 461a movge r2, r3
  12255. 800979a: 2a00 cmp r2, #0
  12256. 800979c: 4690 mov r8, r2
  12257. 800979e: dc36 bgt.n 800980e <_printf_float+0x37a>
  12258. 80097a0: f04f 0a00 mov.w sl, #0
  12259. 80097a4: f104 031a add.w r3, r4, #26
  12260. 80097a8: ea28 78e8 bic.w r8, r8, r8, asr #31
  12261. 80097ac: 930b str r3, [sp, #44] ; 0x2c
  12262. 80097ae: f8d4 9058 ldr.w r9, [r4, #88] ; 0x58
  12263. 80097b2: eba9 0308 sub.w r3, r9, r8
  12264. 80097b6: 459a cmp sl, r3
  12265. 80097b8: db31 blt.n 800981e <_printf_float+0x38a>
  12266. 80097ba: 9b0e ldr r3, [sp, #56] ; 0x38
  12267. 80097bc: 9a0d ldr r2, [sp, #52] ; 0x34
  12268. 80097be: 429a cmp r2, r3
  12269. 80097c0: db38 blt.n 8009834 <_printf_float+0x3a0>
  12270. 80097c2: 6823 ldr r3, [r4, #0]
  12271. 80097c4: 07da lsls r2, r3, #31
  12272. 80097c6: d435 bmi.n 8009834 <_printf_float+0x3a0>
  12273. 80097c8: 9b0e ldr r3, [sp, #56] ; 0x38
  12274. 80097ca: 990d ldr r1, [sp, #52] ; 0x34
  12275. 80097cc: eba3 0209 sub.w r2, r3, r9
  12276. 80097d0: eba3 0801 sub.w r8, r3, r1
  12277. 80097d4: 4590 cmp r8, r2
  12278. 80097d6: bfa8 it ge
  12279. 80097d8: 4690 movge r8, r2
  12280. 80097da: f1b8 0f00 cmp.w r8, #0
  12281. 80097de: dc31 bgt.n 8009844 <_printf_float+0x3b0>
  12282. 80097e0: 2700 movs r7, #0
  12283. 80097e2: ea28 78e8 bic.w r8, r8, r8, asr #31
  12284. 80097e6: f104 091a add.w r9, r4, #26
  12285. 80097ea: 9a0d ldr r2, [sp, #52] ; 0x34
  12286. 80097ec: 9b0e ldr r3, [sp, #56] ; 0x38
  12287. 80097ee: 1a9b subs r3, r3, r2
  12288. 80097f0: eba3 0308 sub.w r3, r3, r8
  12289. 80097f4: 429f cmp r7, r3
  12290. 80097f6: f6bf af78 bge.w 80096ea <_printf_float+0x256>
  12291. 80097fa: 2301 movs r3, #1
  12292. 80097fc: 464a mov r2, r9
  12293. 80097fe: 4659 mov r1, fp
  12294. 8009800: 4628 mov r0, r5
  12295. 8009802: 47b0 blx r6
  12296. 8009804: 3001 adds r0, #1
  12297. 8009806: f43f aea1 beq.w 800954c <_printf_float+0xb8>
  12298. 800980a: 3701 adds r7, #1
  12299. 800980c: e7ed b.n 80097ea <_printf_float+0x356>
  12300. 800980e: 4613 mov r3, r2
  12301. 8009810: 4659 mov r1, fp
  12302. 8009812: 463a mov r2, r7
  12303. 8009814: 4628 mov r0, r5
  12304. 8009816: 47b0 blx r6
  12305. 8009818: 3001 adds r0, #1
  12306. 800981a: d1c1 bne.n 80097a0 <_printf_float+0x30c>
  12307. 800981c: e696 b.n 800954c <_printf_float+0xb8>
  12308. 800981e: 2301 movs r3, #1
  12309. 8009820: 9a0b ldr r2, [sp, #44] ; 0x2c
  12310. 8009822: 4659 mov r1, fp
  12311. 8009824: 4628 mov r0, r5
  12312. 8009826: 47b0 blx r6
  12313. 8009828: 3001 adds r0, #1
  12314. 800982a: f43f ae8f beq.w 800954c <_printf_float+0xb8>
  12315. 800982e: f10a 0a01 add.w sl, sl, #1
  12316. 8009832: e7bc b.n 80097ae <_printf_float+0x31a>
  12317. 8009834: 9b0a ldr r3, [sp, #40] ; 0x28
  12318. 8009836: 9a09 ldr r2, [sp, #36] ; 0x24
  12319. 8009838: 4659 mov r1, fp
  12320. 800983a: 4628 mov r0, r5
  12321. 800983c: 47b0 blx r6
  12322. 800983e: 3001 adds r0, #1
  12323. 8009840: d1c2 bne.n 80097c8 <_printf_float+0x334>
  12324. 8009842: e683 b.n 800954c <_printf_float+0xb8>
  12325. 8009844: 4643 mov r3, r8
  12326. 8009846: eb07 0209 add.w r2, r7, r9
  12327. 800984a: 4659 mov r1, fp
  12328. 800984c: 4628 mov r0, r5
  12329. 800984e: 47b0 blx r6
  12330. 8009850: 3001 adds r0, #1
  12331. 8009852: d1c5 bne.n 80097e0 <_printf_float+0x34c>
  12332. 8009854: e67a b.n 800954c <_printf_float+0xb8>
  12333. 8009856: 9a0e ldr r2, [sp, #56] ; 0x38
  12334. 8009858: 2a01 cmp r2, #1
  12335. 800985a: dc01 bgt.n 8009860 <_printf_float+0x3cc>
  12336. 800985c: 07db lsls r3, r3, #31
  12337. 800985e: d534 bpl.n 80098ca <_printf_float+0x436>
  12338. 8009860: 2301 movs r3, #1
  12339. 8009862: 463a mov r2, r7
  12340. 8009864: 4659 mov r1, fp
  12341. 8009866: 4628 mov r0, r5
  12342. 8009868: 47b0 blx r6
  12343. 800986a: 3001 adds r0, #1
  12344. 800986c: f43f ae6e beq.w 800954c <_printf_float+0xb8>
  12345. 8009870: 9b0a ldr r3, [sp, #40] ; 0x28
  12346. 8009872: 9a09 ldr r2, [sp, #36] ; 0x24
  12347. 8009874: 4659 mov r1, fp
  12348. 8009876: 4628 mov r0, r5
  12349. 8009878: 47b0 blx r6
  12350. 800987a: 3001 adds r0, #1
  12351. 800987c: f43f ae66 beq.w 800954c <_printf_float+0xb8>
  12352. 8009880: e9d4 0112 ldrd r0, r1, [r4, #72] ; 0x48
  12353. 8009884: 2200 movs r2, #0
  12354. 8009886: 2300 movs r3, #0
  12355. 8009888: f7fb f902 bl 8004a90 <__aeabi_dcmpeq>
  12356. 800988c: b150 cbz r0, 80098a4 <_printf_float+0x410>
  12357. 800988e: 2700 movs r7, #0
  12358. 8009890: f104 081a add.w r8, r4, #26
  12359. 8009894: 9b0e ldr r3, [sp, #56] ; 0x38
  12360. 8009896: 3b01 subs r3, #1
  12361. 8009898: 429f cmp r7, r3
  12362. 800989a: db0c blt.n 80098b6 <_printf_float+0x422>
  12363. 800989c: 464b mov r3, r9
  12364. 800989e: f104 0250 add.w r2, r4, #80 ; 0x50
  12365. 80098a2: e6f2 b.n 800968a <_printf_float+0x1f6>
  12366. 80098a4: 9b0e ldr r3, [sp, #56] ; 0x38
  12367. 80098a6: 1c7a adds r2, r7, #1
  12368. 80098a8: 3b01 subs r3, #1
  12369. 80098aa: 4659 mov r1, fp
  12370. 80098ac: 4628 mov r0, r5
  12371. 80098ae: 47b0 blx r6
  12372. 80098b0: 3001 adds r0, #1
  12373. 80098b2: d1f3 bne.n 800989c <_printf_float+0x408>
  12374. 80098b4: e64a b.n 800954c <_printf_float+0xb8>
  12375. 80098b6: 2301 movs r3, #1
  12376. 80098b8: 4642 mov r2, r8
  12377. 80098ba: 4659 mov r1, fp
  12378. 80098bc: 4628 mov r0, r5
  12379. 80098be: 47b0 blx r6
  12380. 80098c0: 3001 adds r0, #1
  12381. 80098c2: f43f ae43 beq.w 800954c <_printf_float+0xb8>
  12382. 80098c6: 3701 adds r7, #1
  12383. 80098c8: e7e4 b.n 8009894 <_printf_float+0x400>
  12384. 80098ca: 2301 movs r3, #1
  12385. 80098cc: 463a mov r2, r7
  12386. 80098ce: e7ec b.n 80098aa <_printf_float+0x416>
  12387. 80098d0: 2301 movs r3, #1
  12388. 80098d2: 4642 mov r2, r8
  12389. 80098d4: 4659 mov r1, fp
  12390. 80098d6: 4628 mov r0, r5
  12391. 80098d8: 47b0 blx r6
  12392. 80098da: 3001 adds r0, #1
  12393. 80098dc: f43f ae36 beq.w 800954c <_printf_float+0xb8>
  12394. 80098e0: 3701 adds r7, #1
  12395. 80098e2: e708 b.n 80096f6 <_printf_float+0x262>
  12396. 80098e4: 463a mov r2, r7
  12397. 80098e6: 464b mov r3, r9
  12398. 80098e8: 4638 mov r0, r7
  12399. 80098ea: 4649 mov r1, r9
  12400. 80098ec: f7fb f902 bl 8004af4 <__aeabi_dcmpun>
  12401. 80098f0: 2800 cmp r0, #0
  12402. 80098f2: f43f ae30 beq.w 8009556 <_printf_float+0xc2>
  12403. 80098f6: 4b01 ldr r3, [pc, #4] ; (80098fc <_printf_float+0x468>)
  12404. 80098f8: 4f01 ldr r7, [pc, #4] ; (8009900 <_printf_float+0x46c>)
  12405. 80098fa: e612 b.n 8009522 <_printf_float+0x8e>
  12406. 80098fc: 0800bd24 .word 0x0800bd24
  12407. 8009900: 0800bd28 .word 0x0800bd28
  12408. 08009904 <_printf_common>:
  12409. 8009904: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
  12410. 8009908: 4691 mov r9, r2
  12411. 800990a: 461f mov r7, r3
  12412. 800990c: 688a ldr r2, [r1, #8]
  12413. 800990e: 690b ldr r3, [r1, #16]
  12414. 8009910: 4606 mov r6, r0
  12415. 8009912: 4293 cmp r3, r2
  12416. 8009914: bfb8 it lt
  12417. 8009916: 4613 movlt r3, r2
  12418. 8009918: f8c9 3000 str.w r3, [r9]
  12419. 800991c: f891 2043 ldrb.w r2, [r1, #67] ; 0x43
  12420. 8009920: 460c mov r4, r1
  12421. 8009922: f8dd 8020 ldr.w r8, [sp, #32]
  12422. 8009926: b112 cbz r2, 800992e <_printf_common+0x2a>
  12423. 8009928: 3301 adds r3, #1
  12424. 800992a: f8c9 3000 str.w r3, [r9]
  12425. 800992e: 6823 ldr r3, [r4, #0]
  12426. 8009930: 0699 lsls r1, r3, #26
  12427. 8009932: bf42 ittt mi
  12428. 8009934: f8d9 3000 ldrmi.w r3, [r9]
  12429. 8009938: 3302 addmi r3, #2
  12430. 800993a: f8c9 3000 strmi.w r3, [r9]
  12431. 800993e: 6825 ldr r5, [r4, #0]
  12432. 8009940: f015 0506 ands.w r5, r5, #6
  12433. 8009944: d107 bne.n 8009956 <_printf_common+0x52>
  12434. 8009946: f104 0a19 add.w sl, r4, #25
  12435. 800994a: 68e3 ldr r3, [r4, #12]
  12436. 800994c: f8d9 2000 ldr.w r2, [r9]
  12437. 8009950: 1a9b subs r3, r3, r2
  12438. 8009952: 429d cmp r5, r3
  12439. 8009954: db2a blt.n 80099ac <_printf_common+0xa8>
  12440. 8009956: f894 3043 ldrb.w r3, [r4, #67] ; 0x43
  12441. 800995a: 6822 ldr r2, [r4, #0]
  12442. 800995c: 3300 adds r3, #0
  12443. 800995e: bf18 it ne
  12444. 8009960: 2301 movne r3, #1
  12445. 8009962: 0692 lsls r2, r2, #26
  12446. 8009964: d42f bmi.n 80099c6 <_printf_common+0xc2>
  12447. 8009966: f104 0243 add.w r2, r4, #67 ; 0x43
  12448. 800996a: 4639 mov r1, r7
  12449. 800996c: 4630 mov r0, r6
  12450. 800996e: 47c0 blx r8
  12451. 8009970: 3001 adds r0, #1
  12452. 8009972: d022 beq.n 80099ba <_printf_common+0xb6>
  12453. 8009974: 6823 ldr r3, [r4, #0]
  12454. 8009976: 68e5 ldr r5, [r4, #12]
  12455. 8009978: f003 0306 and.w r3, r3, #6
  12456. 800997c: 2b04 cmp r3, #4
  12457. 800997e: bf18 it ne
  12458. 8009980: 2500 movne r5, #0
  12459. 8009982: f8d9 2000 ldr.w r2, [r9]
  12460. 8009986: f04f 0900 mov.w r9, #0
  12461. 800998a: bf08 it eq
  12462. 800998c: 1aad subeq r5, r5, r2
  12463. 800998e: 68a3 ldr r3, [r4, #8]
  12464. 8009990: 6922 ldr r2, [r4, #16]
  12465. 8009992: bf08 it eq
  12466. 8009994: ea25 75e5 biceq.w r5, r5, r5, asr #31
  12467. 8009998: 4293 cmp r3, r2
  12468. 800999a: bfc4 itt gt
  12469. 800999c: 1a9b subgt r3, r3, r2
  12470. 800999e: 18ed addgt r5, r5, r3
  12471. 80099a0: 341a adds r4, #26
  12472. 80099a2: 454d cmp r5, r9
  12473. 80099a4: d11b bne.n 80099de <_printf_common+0xda>
  12474. 80099a6: 2000 movs r0, #0
  12475. 80099a8: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
  12476. 80099ac: 2301 movs r3, #1
  12477. 80099ae: 4652 mov r2, sl
  12478. 80099b0: 4639 mov r1, r7
  12479. 80099b2: 4630 mov r0, r6
  12480. 80099b4: 47c0 blx r8
  12481. 80099b6: 3001 adds r0, #1
  12482. 80099b8: d103 bne.n 80099c2 <_printf_common+0xbe>
  12483. 80099ba: f04f 30ff mov.w r0, #4294967295
  12484. 80099be: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
  12485. 80099c2: 3501 adds r5, #1
  12486. 80099c4: e7c1 b.n 800994a <_printf_common+0x46>
  12487. 80099c6: 2030 movs r0, #48 ; 0x30
  12488. 80099c8: 18e1 adds r1, r4, r3
  12489. 80099ca: f881 0043 strb.w r0, [r1, #67] ; 0x43
  12490. 80099ce: 1c5a adds r2, r3, #1
  12491. 80099d0: f894 1045 ldrb.w r1, [r4, #69] ; 0x45
  12492. 80099d4: 4422 add r2, r4
  12493. 80099d6: 3302 adds r3, #2
  12494. 80099d8: f882 1043 strb.w r1, [r2, #67] ; 0x43
  12495. 80099dc: e7c3 b.n 8009966 <_printf_common+0x62>
  12496. 80099de: 2301 movs r3, #1
  12497. 80099e0: 4622 mov r2, r4
  12498. 80099e2: 4639 mov r1, r7
  12499. 80099e4: 4630 mov r0, r6
  12500. 80099e6: 47c0 blx r8
  12501. 80099e8: 3001 adds r0, #1
  12502. 80099ea: d0e6 beq.n 80099ba <_printf_common+0xb6>
  12503. 80099ec: f109 0901 add.w r9, r9, #1
  12504. 80099f0: e7d7 b.n 80099a2 <_printf_common+0x9e>
  12505. ...
  12506. 080099f4 <_printf_i>:
  12507. 80099f4: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr}
  12508. 80099f8: 4617 mov r7, r2
  12509. 80099fa: 7e0a ldrb r2, [r1, #24]
  12510. 80099fc: b085 sub sp, #20
  12511. 80099fe: 2a6e cmp r2, #110 ; 0x6e
  12512. 8009a00: 4698 mov r8, r3
  12513. 8009a02: 4606 mov r6, r0
  12514. 8009a04: 460c mov r4, r1
  12515. 8009a06: 9b0c ldr r3, [sp, #48] ; 0x30
  12516. 8009a08: f101 0e43 add.w lr, r1, #67 ; 0x43
  12517. 8009a0c: f000 80bc beq.w 8009b88 <_printf_i+0x194>
  12518. 8009a10: d81a bhi.n 8009a48 <_printf_i+0x54>
  12519. 8009a12: 2a63 cmp r2, #99 ; 0x63
  12520. 8009a14: d02e beq.n 8009a74 <_printf_i+0x80>
  12521. 8009a16: d80a bhi.n 8009a2e <_printf_i+0x3a>
  12522. 8009a18: 2a00 cmp r2, #0
  12523. 8009a1a: f000 80c8 beq.w 8009bae <_printf_i+0x1ba>
  12524. 8009a1e: 2a58 cmp r2, #88 ; 0x58
  12525. 8009a20: f000 808a beq.w 8009b38 <_printf_i+0x144>
  12526. 8009a24: f104 0542 add.w r5, r4, #66 ; 0x42
  12527. 8009a28: f884 2042 strb.w r2, [r4, #66] ; 0x42
  12528. 8009a2c: e02a b.n 8009a84 <_printf_i+0x90>
  12529. 8009a2e: 2a64 cmp r2, #100 ; 0x64
  12530. 8009a30: d001 beq.n 8009a36 <_printf_i+0x42>
  12531. 8009a32: 2a69 cmp r2, #105 ; 0x69
  12532. 8009a34: d1f6 bne.n 8009a24 <_printf_i+0x30>
  12533. 8009a36: 6821 ldr r1, [r4, #0]
  12534. 8009a38: 681a ldr r2, [r3, #0]
  12535. 8009a3a: f011 0f80 tst.w r1, #128 ; 0x80
  12536. 8009a3e: d023 beq.n 8009a88 <_printf_i+0x94>
  12537. 8009a40: 1d11 adds r1, r2, #4
  12538. 8009a42: 6019 str r1, [r3, #0]
  12539. 8009a44: 6813 ldr r3, [r2, #0]
  12540. 8009a46: e027 b.n 8009a98 <_printf_i+0xa4>
  12541. 8009a48: 2a73 cmp r2, #115 ; 0x73
  12542. 8009a4a: f000 80b4 beq.w 8009bb6 <_printf_i+0x1c2>
  12543. 8009a4e: d808 bhi.n 8009a62 <_printf_i+0x6e>
  12544. 8009a50: 2a6f cmp r2, #111 ; 0x6f
  12545. 8009a52: d02a beq.n 8009aaa <_printf_i+0xb6>
  12546. 8009a54: 2a70 cmp r2, #112 ; 0x70
  12547. 8009a56: d1e5 bne.n 8009a24 <_printf_i+0x30>
  12548. 8009a58: 680a ldr r2, [r1, #0]
  12549. 8009a5a: f042 0220 orr.w r2, r2, #32
  12550. 8009a5e: 600a str r2, [r1, #0]
  12551. 8009a60: e003 b.n 8009a6a <_printf_i+0x76>
  12552. 8009a62: 2a75 cmp r2, #117 ; 0x75
  12553. 8009a64: d021 beq.n 8009aaa <_printf_i+0xb6>
  12554. 8009a66: 2a78 cmp r2, #120 ; 0x78
  12555. 8009a68: d1dc bne.n 8009a24 <_printf_i+0x30>
  12556. 8009a6a: 2278 movs r2, #120 ; 0x78
  12557. 8009a6c: 496f ldr r1, [pc, #444] ; (8009c2c <_printf_i+0x238>)
  12558. 8009a6e: f884 2045 strb.w r2, [r4, #69] ; 0x45
  12559. 8009a72: e064 b.n 8009b3e <_printf_i+0x14a>
  12560. 8009a74: 681a ldr r2, [r3, #0]
  12561. 8009a76: f101 0542 add.w r5, r1, #66 ; 0x42
  12562. 8009a7a: 1d11 adds r1, r2, #4
  12563. 8009a7c: 6019 str r1, [r3, #0]
  12564. 8009a7e: 6813 ldr r3, [r2, #0]
  12565. 8009a80: f884 3042 strb.w r3, [r4, #66] ; 0x42
  12566. 8009a84: 2301 movs r3, #1
  12567. 8009a86: e0a3 b.n 8009bd0 <_printf_i+0x1dc>
  12568. 8009a88: f011 0f40 tst.w r1, #64 ; 0x40
  12569. 8009a8c: f102 0104 add.w r1, r2, #4
  12570. 8009a90: 6019 str r1, [r3, #0]
  12571. 8009a92: d0d7 beq.n 8009a44 <_printf_i+0x50>
  12572. 8009a94: f9b2 3000 ldrsh.w r3, [r2]
  12573. 8009a98: 2b00 cmp r3, #0
  12574. 8009a9a: da03 bge.n 8009aa4 <_printf_i+0xb0>
  12575. 8009a9c: 222d movs r2, #45 ; 0x2d
  12576. 8009a9e: 425b negs r3, r3
  12577. 8009aa0: f884 2043 strb.w r2, [r4, #67] ; 0x43
  12578. 8009aa4: 4962 ldr r1, [pc, #392] ; (8009c30 <_printf_i+0x23c>)
  12579. 8009aa6: 220a movs r2, #10
  12580. 8009aa8: e017 b.n 8009ada <_printf_i+0xe6>
  12581. 8009aaa: 6820 ldr r0, [r4, #0]
  12582. 8009aac: 6819 ldr r1, [r3, #0]
  12583. 8009aae: f010 0f80 tst.w r0, #128 ; 0x80
  12584. 8009ab2: d003 beq.n 8009abc <_printf_i+0xc8>
  12585. 8009ab4: 1d08 adds r0, r1, #4
  12586. 8009ab6: 6018 str r0, [r3, #0]
  12587. 8009ab8: 680b ldr r3, [r1, #0]
  12588. 8009aba: e006 b.n 8009aca <_printf_i+0xd6>
  12589. 8009abc: f010 0f40 tst.w r0, #64 ; 0x40
  12590. 8009ac0: f101 0004 add.w r0, r1, #4
  12591. 8009ac4: 6018 str r0, [r3, #0]
  12592. 8009ac6: d0f7 beq.n 8009ab8 <_printf_i+0xc4>
  12593. 8009ac8: 880b ldrh r3, [r1, #0]
  12594. 8009aca: 2a6f cmp r2, #111 ; 0x6f
  12595. 8009acc: bf14 ite ne
  12596. 8009ace: 220a movne r2, #10
  12597. 8009ad0: 2208 moveq r2, #8
  12598. 8009ad2: 4957 ldr r1, [pc, #348] ; (8009c30 <_printf_i+0x23c>)
  12599. 8009ad4: 2000 movs r0, #0
  12600. 8009ad6: f884 0043 strb.w r0, [r4, #67] ; 0x43
  12601. 8009ada: 6865 ldr r5, [r4, #4]
  12602. 8009adc: 2d00 cmp r5, #0
  12603. 8009ade: 60a5 str r5, [r4, #8]
  12604. 8009ae0: f2c0 809c blt.w 8009c1c <_printf_i+0x228>
  12605. 8009ae4: 6820 ldr r0, [r4, #0]
  12606. 8009ae6: f020 0004 bic.w r0, r0, #4
  12607. 8009aea: 6020 str r0, [r4, #0]
  12608. 8009aec: 2b00 cmp r3, #0
  12609. 8009aee: d13f bne.n 8009b70 <_printf_i+0x17c>
  12610. 8009af0: 2d00 cmp r5, #0
  12611. 8009af2: f040 8095 bne.w 8009c20 <_printf_i+0x22c>
  12612. 8009af6: 4675 mov r5, lr
  12613. 8009af8: 2a08 cmp r2, #8
  12614. 8009afa: d10b bne.n 8009b14 <_printf_i+0x120>
  12615. 8009afc: 6823 ldr r3, [r4, #0]
  12616. 8009afe: 07da lsls r2, r3, #31
  12617. 8009b00: d508 bpl.n 8009b14 <_printf_i+0x120>
  12618. 8009b02: 6923 ldr r3, [r4, #16]
  12619. 8009b04: 6862 ldr r2, [r4, #4]
  12620. 8009b06: 429a cmp r2, r3
  12621. 8009b08: bfde ittt le
  12622. 8009b0a: 2330 movle r3, #48 ; 0x30
  12623. 8009b0c: f805 3c01 strble.w r3, [r5, #-1]
  12624. 8009b10: f105 35ff addle.w r5, r5, #4294967295
  12625. 8009b14: ebae 0305 sub.w r3, lr, r5
  12626. 8009b18: 6123 str r3, [r4, #16]
  12627. 8009b1a: f8cd 8000 str.w r8, [sp]
  12628. 8009b1e: 463b mov r3, r7
  12629. 8009b20: aa03 add r2, sp, #12
  12630. 8009b22: 4621 mov r1, r4
  12631. 8009b24: 4630 mov r0, r6
  12632. 8009b26: f7ff feed bl 8009904 <_printf_common>
  12633. 8009b2a: 3001 adds r0, #1
  12634. 8009b2c: d155 bne.n 8009bda <_printf_i+0x1e6>
  12635. 8009b2e: f04f 30ff mov.w r0, #4294967295
  12636. 8009b32: b005 add sp, #20
  12637. 8009b34: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc}
  12638. 8009b38: f881 2045 strb.w r2, [r1, #69] ; 0x45
  12639. 8009b3c: 493c ldr r1, [pc, #240] ; (8009c30 <_printf_i+0x23c>)
  12640. 8009b3e: 6822 ldr r2, [r4, #0]
  12641. 8009b40: 6818 ldr r0, [r3, #0]
  12642. 8009b42: f012 0f80 tst.w r2, #128 ; 0x80
  12643. 8009b46: f100 0504 add.w r5, r0, #4
  12644. 8009b4a: 601d str r5, [r3, #0]
  12645. 8009b4c: d001 beq.n 8009b52 <_printf_i+0x15e>
  12646. 8009b4e: 6803 ldr r3, [r0, #0]
  12647. 8009b50: e002 b.n 8009b58 <_printf_i+0x164>
  12648. 8009b52: 0655 lsls r5, r2, #25
  12649. 8009b54: d5fb bpl.n 8009b4e <_printf_i+0x15a>
  12650. 8009b56: 8803 ldrh r3, [r0, #0]
  12651. 8009b58: 07d0 lsls r0, r2, #31
  12652. 8009b5a: bf44 itt mi
  12653. 8009b5c: f042 0220 orrmi.w r2, r2, #32
  12654. 8009b60: 6022 strmi r2, [r4, #0]
  12655. 8009b62: b91b cbnz r3, 8009b6c <_printf_i+0x178>
  12656. 8009b64: 6822 ldr r2, [r4, #0]
  12657. 8009b66: f022 0220 bic.w r2, r2, #32
  12658. 8009b6a: 6022 str r2, [r4, #0]
  12659. 8009b6c: 2210 movs r2, #16
  12660. 8009b6e: e7b1 b.n 8009ad4 <_printf_i+0xe0>
  12661. 8009b70: 4675 mov r5, lr
  12662. 8009b72: fbb3 f0f2 udiv r0, r3, r2
  12663. 8009b76: fb02 3310 mls r3, r2, r0, r3
  12664. 8009b7a: 5ccb ldrb r3, [r1, r3]
  12665. 8009b7c: f805 3d01 strb.w r3, [r5, #-1]!
  12666. 8009b80: 4603 mov r3, r0
  12667. 8009b82: 2800 cmp r0, #0
  12668. 8009b84: d1f5 bne.n 8009b72 <_printf_i+0x17e>
  12669. 8009b86: e7b7 b.n 8009af8 <_printf_i+0x104>
  12670. 8009b88: 6808 ldr r0, [r1, #0]
  12671. 8009b8a: 681a ldr r2, [r3, #0]
  12672. 8009b8c: f010 0f80 tst.w r0, #128 ; 0x80
  12673. 8009b90: 6949 ldr r1, [r1, #20]
  12674. 8009b92: d004 beq.n 8009b9e <_printf_i+0x1aa>
  12675. 8009b94: 1d10 adds r0, r2, #4
  12676. 8009b96: 6018 str r0, [r3, #0]
  12677. 8009b98: 6813 ldr r3, [r2, #0]
  12678. 8009b9a: 6019 str r1, [r3, #0]
  12679. 8009b9c: e007 b.n 8009bae <_printf_i+0x1ba>
  12680. 8009b9e: f010 0f40 tst.w r0, #64 ; 0x40
  12681. 8009ba2: f102 0004 add.w r0, r2, #4
  12682. 8009ba6: 6018 str r0, [r3, #0]
  12683. 8009ba8: 6813 ldr r3, [r2, #0]
  12684. 8009baa: d0f6 beq.n 8009b9a <_printf_i+0x1a6>
  12685. 8009bac: 8019 strh r1, [r3, #0]
  12686. 8009bae: 2300 movs r3, #0
  12687. 8009bb0: 4675 mov r5, lr
  12688. 8009bb2: 6123 str r3, [r4, #16]
  12689. 8009bb4: e7b1 b.n 8009b1a <_printf_i+0x126>
  12690. 8009bb6: 681a ldr r2, [r3, #0]
  12691. 8009bb8: 1d11 adds r1, r2, #4
  12692. 8009bba: 6019 str r1, [r3, #0]
  12693. 8009bbc: 6815 ldr r5, [r2, #0]
  12694. 8009bbe: 2100 movs r1, #0
  12695. 8009bc0: 6862 ldr r2, [r4, #4]
  12696. 8009bc2: 4628 mov r0, r5
  12697. 8009bc4: f001 fa7e bl 800b0c4 <memchr>
  12698. 8009bc8: b108 cbz r0, 8009bce <_printf_i+0x1da>
  12699. 8009bca: 1b40 subs r0, r0, r5
  12700. 8009bcc: 6060 str r0, [r4, #4]
  12701. 8009bce: 6863 ldr r3, [r4, #4]
  12702. 8009bd0: 6123 str r3, [r4, #16]
  12703. 8009bd2: 2300 movs r3, #0
  12704. 8009bd4: f884 3043 strb.w r3, [r4, #67] ; 0x43
  12705. 8009bd8: e79f b.n 8009b1a <_printf_i+0x126>
  12706. 8009bda: 6923 ldr r3, [r4, #16]
  12707. 8009bdc: 462a mov r2, r5
  12708. 8009bde: 4639 mov r1, r7
  12709. 8009be0: 4630 mov r0, r6
  12710. 8009be2: 47c0 blx r8
  12711. 8009be4: 3001 adds r0, #1
  12712. 8009be6: d0a2 beq.n 8009b2e <_printf_i+0x13a>
  12713. 8009be8: 6823 ldr r3, [r4, #0]
  12714. 8009bea: 079b lsls r3, r3, #30
  12715. 8009bec: d507 bpl.n 8009bfe <_printf_i+0x20a>
  12716. 8009bee: 2500 movs r5, #0
  12717. 8009bf0: f104 0919 add.w r9, r4, #25
  12718. 8009bf4: 68e3 ldr r3, [r4, #12]
  12719. 8009bf6: 9a03 ldr r2, [sp, #12]
  12720. 8009bf8: 1a9b subs r3, r3, r2
  12721. 8009bfa: 429d cmp r5, r3
  12722. 8009bfc: db05 blt.n 8009c0a <_printf_i+0x216>
  12723. 8009bfe: 68e0 ldr r0, [r4, #12]
  12724. 8009c00: 9b03 ldr r3, [sp, #12]
  12725. 8009c02: 4298 cmp r0, r3
  12726. 8009c04: bfb8 it lt
  12727. 8009c06: 4618 movlt r0, r3
  12728. 8009c08: e793 b.n 8009b32 <_printf_i+0x13e>
  12729. 8009c0a: 2301 movs r3, #1
  12730. 8009c0c: 464a mov r2, r9
  12731. 8009c0e: 4639 mov r1, r7
  12732. 8009c10: 4630 mov r0, r6
  12733. 8009c12: 47c0 blx r8
  12734. 8009c14: 3001 adds r0, #1
  12735. 8009c16: d08a beq.n 8009b2e <_printf_i+0x13a>
  12736. 8009c18: 3501 adds r5, #1
  12737. 8009c1a: e7eb b.n 8009bf4 <_printf_i+0x200>
  12738. 8009c1c: 2b00 cmp r3, #0
  12739. 8009c1e: d1a7 bne.n 8009b70 <_printf_i+0x17c>
  12740. 8009c20: 780b ldrb r3, [r1, #0]
  12741. 8009c22: f104 0542 add.w r5, r4, #66 ; 0x42
  12742. 8009c26: f884 3042 strb.w r3, [r4, #66] ; 0x42
  12743. 8009c2a: e765 b.n 8009af8 <_printf_i+0x104>
  12744. 8009c2c: 0800bd3f .word 0x0800bd3f
  12745. 8009c30: 0800bd2e .word 0x0800bd2e
  12746. 08009c34 <iprintf>:
  12747. 8009c34: b40f push {r0, r1, r2, r3}
  12748. 8009c36: 4b0a ldr r3, [pc, #40] ; (8009c60 <iprintf+0x2c>)
  12749. 8009c38: b513 push {r0, r1, r4, lr}
  12750. 8009c3a: 681c ldr r4, [r3, #0]
  12751. 8009c3c: b124 cbz r4, 8009c48 <iprintf+0x14>
  12752. 8009c3e: 69a3 ldr r3, [r4, #24]
  12753. 8009c40: b913 cbnz r3, 8009c48 <iprintf+0x14>
  12754. 8009c42: 4620 mov r0, r4
  12755. 8009c44: f001 f93a bl 800aebc <__sinit>
  12756. 8009c48: ab05 add r3, sp, #20
  12757. 8009c4a: 9a04 ldr r2, [sp, #16]
  12758. 8009c4c: 68a1 ldr r1, [r4, #8]
  12759. 8009c4e: 4620 mov r0, r4
  12760. 8009c50: 9301 str r3, [sp, #4]
  12761. 8009c52: f001 fdf7 bl 800b844 <_vfiprintf_r>
  12762. 8009c56: b002 add sp, #8
  12763. 8009c58: e8bd 4010 ldmia.w sp!, {r4, lr}
  12764. 8009c5c: b004 add sp, #16
  12765. 8009c5e: 4770 bx lr
  12766. 8009c60: 20000234 .word 0x20000234
  12767. 08009c64 <_puts_r>:
  12768. 8009c64: b570 push {r4, r5, r6, lr}
  12769. 8009c66: 460e mov r6, r1
  12770. 8009c68: 4605 mov r5, r0
  12771. 8009c6a: b118 cbz r0, 8009c74 <_puts_r+0x10>
  12772. 8009c6c: 6983 ldr r3, [r0, #24]
  12773. 8009c6e: b90b cbnz r3, 8009c74 <_puts_r+0x10>
  12774. 8009c70: f001 f924 bl 800aebc <__sinit>
  12775. 8009c74: 69ab ldr r3, [r5, #24]
  12776. 8009c76: 68ac ldr r4, [r5, #8]
  12777. 8009c78: b913 cbnz r3, 8009c80 <_puts_r+0x1c>
  12778. 8009c7a: 4628 mov r0, r5
  12779. 8009c7c: f001 f91e bl 800aebc <__sinit>
  12780. 8009c80: 4b23 ldr r3, [pc, #140] ; (8009d10 <_puts_r+0xac>)
  12781. 8009c82: 429c cmp r4, r3
  12782. 8009c84: d117 bne.n 8009cb6 <_puts_r+0x52>
  12783. 8009c86: 686c ldr r4, [r5, #4]
  12784. 8009c88: 89a3 ldrh r3, [r4, #12]
  12785. 8009c8a: 071b lsls r3, r3, #28
  12786. 8009c8c: d51d bpl.n 8009cca <_puts_r+0x66>
  12787. 8009c8e: 6923 ldr r3, [r4, #16]
  12788. 8009c90: b1db cbz r3, 8009cca <_puts_r+0x66>
  12789. 8009c92: 3e01 subs r6, #1
  12790. 8009c94: 68a3 ldr r3, [r4, #8]
  12791. 8009c96: f816 1f01 ldrb.w r1, [r6, #1]!
  12792. 8009c9a: 3b01 subs r3, #1
  12793. 8009c9c: 60a3 str r3, [r4, #8]
  12794. 8009c9e: b9e9 cbnz r1, 8009cdc <_puts_r+0x78>
  12795. 8009ca0: 2b00 cmp r3, #0
  12796. 8009ca2: da2e bge.n 8009d02 <_puts_r+0x9e>
  12797. 8009ca4: 4622 mov r2, r4
  12798. 8009ca6: 210a movs r1, #10
  12799. 8009ca8: 4628 mov r0, r5
  12800. 8009caa: f000 f8f5 bl 8009e98 <__swbuf_r>
  12801. 8009cae: 3001 adds r0, #1
  12802. 8009cb0: d011 beq.n 8009cd6 <_puts_r+0x72>
  12803. 8009cb2: 200a movs r0, #10
  12804. 8009cb4: bd70 pop {r4, r5, r6, pc}
  12805. 8009cb6: 4b17 ldr r3, [pc, #92] ; (8009d14 <_puts_r+0xb0>)
  12806. 8009cb8: 429c cmp r4, r3
  12807. 8009cba: d101 bne.n 8009cc0 <_puts_r+0x5c>
  12808. 8009cbc: 68ac ldr r4, [r5, #8]
  12809. 8009cbe: e7e3 b.n 8009c88 <_puts_r+0x24>
  12810. 8009cc0: 4b15 ldr r3, [pc, #84] ; (8009d18 <_puts_r+0xb4>)
  12811. 8009cc2: 429c cmp r4, r3
  12812. 8009cc4: bf08 it eq
  12813. 8009cc6: 68ec ldreq r4, [r5, #12]
  12814. 8009cc8: e7de b.n 8009c88 <_puts_r+0x24>
  12815. 8009cca: 4621 mov r1, r4
  12816. 8009ccc: 4628 mov r0, r5
  12817. 8009cce: f000 f935 bl 8009f3c <__swsetup_r>
  12818. 8009cd2: 2800 cmp r0, #0
  12819. 8009cd4: d0dd beq.n 8009c92 <_puts_r+0x2e>
  12820. 8009cd6: f04f 30ff mov.w r0, #4294967295
  12821. 8009cda: bd70 pop {r4, r5, r6, pc}
  12822. 8009cdc: 2b00 cmp r3, #0
  12823. 8009cde: da04 bge.n 8009cea <_puts_r+0x86>
  12824. 8009ce0: 69a2 ldr r2, [r4, #24]
  12825. 8009ce2: 4293 cmp r3, r2
  12826. 8009ce4: db06 blt.n 8009cf4 <_puts_r+0x90>
  12827. 8009ce6: 290a cmp r1, #10
  12828. 8009ce8: d004 beq.n 8009cf4 <_puts_r+0x90>
  12829. 8009cea: 6823 ldr r3, [r4, #0]
  12830. 8009cec: 1c5a adds r2, r3, #1
  12831. 8009cee: 6022 str r2, [r4, #0]
  12832. 8009cf0: 7019 strb r1, [r3, #0]
  12833. 8009cf2: e7cf b.n 8009c94 <_puts_r+0x30>
  12834. 8009cf4: 4622 mov r2, r4
  12835. 8009cf6: 4628 mov r0, r5
  12836. 8009cf8: f000 f8ce bl 8009e98 <__swbuf_r>
  12837. 8009cfc: 3001 adds r0, #1
  12838. 8009cfe: d1c9 bne.n 8009c94 <_puts_r+0x30>
  12839. 8009d00: e7e9 b.n 8009cd6 <_puts_r+0x72>
  12840. 8009d02: 200a movs r0, #10
  12841. 8009d04: 6823 ldr r3, [r4, #0]
  12842. 8009d06: 1c5a adds r2, r3, #1
  12843. 8009d08: 6022 str r2, [r4, #0]
  12844. 8009d0a: 7018 strb r0, [r3, #0]
  12845. 8009d0c: bd70 pop {r4, r5, r6, pc}
  12846. 8009d0e: bf00 nop
  12847. 8009d10: 0800bd80 .word 0x0800bd80
  12848. 8009d14: 0800bda0 .word 0x0800bda0
  12849. 8009d18: 0800bd60 .word 0x0800bd60
  12850. 08009d1c <puts>:
  12851. 8009d1c: 4b02 ldr r3, [pc, #8] ; (8009d28 <puts+0xc>)
  12852. 8009d1e: 4601 mov r1, r0
  12853. 8009d20: 6818 ldr r0, [r3, #0]
  12854. 8009d22: f7ff bf9f b.w 8009c64 <_puts_r>
  12855. 8009d26: bf00 nop
  12856. 8009d28: 20000234 .word 0x20000234
  12857. 08009d2c <setbuf>:
  12858. 8009d2c: 2900 cmp r1, #0
  12859. 8009d2e: f44f 6380 mov.w r3, #1024 ; 0x400
  12860. 8009d32: bf0c ite eq
  12861. 8009d34: 2202 moveq r2, #2
  12862. 8009d36: 2200 movne r2, #0
  12863. 8009d38: f000 b800 b.w 8009d3c <setvbuf>
  12864. 08009d3c <setvbuf>:
  12865. 8009d3c: e92d 43f7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
  12866. 8009d40: 461d mov r5, r3
  12867. 8009d42: 4b51 ldr r3, [pc, #324] ; (8009e88 <setvbuf+0x14c>)
  12868. 8009d44: 4604 mov r4, r0
  12869. 8009d46: 681e ldr r6, [r3, #0]
  12870. 8009d48: 460f mov r7, r1
  12871. 8009d4a: 4690 mov r8, r2
  12872. 8009d4c: b126 cbz r6, 8009d58 <setvbuf+0x1c>
  12873. 8009d4e: 69b3 ldr r3, [r6, #24]
  12874. 8009d50: b913 cbnz r3, 8009d58 <setvbuf+0x1c>
  12875. 8009d52: 4630 mov r0, r6
  12876. 8009d54: f001 f8b2 bl 800aebc <__sinit>
  12877. 8009d58: 4b4c ldr r3, [pc, #304] ; (8009e8c <setvbuf+0x150>)
  12878. 8009d5a: 429c cmp r4, r3
  12879. 8009d5c: d152 bne.n 8009e04 <setvbuf+0xc8>
  12880. 8009d5e: 6874 ldr r4, [r6, #4]
  12881. 8009d60: f1b8 0f02 cmp.w r8, #2
  12882. 8009d64: d006 beq.n 8009d74 <setvbuf+0x38>
  12883. 8009d66: f1b8 0f01 cmp.w r8, #1
  12884. 8009d6a: f200 8089 bhi.w 8009e80 <setvbuf+0x144>
  12885. 8009d6e: 2d00 cmp r5, #0
  12886. 8009d70: f2c0 8086 blt.w 8009e80 <setvbuf+0x144>
  12887. 8009d74: 4621 mov r1, r4
  12888. 8009d76: 4630 mov r0, r6
  12889. 8009d78: f001 f836 bl 800ade8 <_fflush_r>
  12890. 8009d7c: 6b61 ldr r1, [r4, #52] ; 0x34
  12891. 8009d7e: b141 cbz r1, 8009d92 <setvbuf+0x56>
  12892. 8009d80: f104 0344 add.w r3, r4, #68 ; 0x44
  12893. 8009d84: 4299 cmp r1, r3
  12894. 8009d86: d002 beq.n 8009d8e <setvbuf+0x52>
  12895. 8009d88: 4630 mov r0, r6
  12896. 8009d8a: f001 fc89 bl 800b6a0 <_free_r>
  12897. 8009d8e: 2300 movs r3, #0
  12898. 8009d90: 6363 str r3, [r4, #52] ; 0x34
  12899. 8009d92: 2300 movs r3, #0
  12900. 8009d94: 61a3 str r3, [r4, #24]
  12901. 8009d96: 6063 str r3, [r4, #4]
  12902. 8009d98: 89a3 ldrh r3, [r4, #12]
  12903. 8009d9a: 061b lsls r3, r3, #24
  12904. 8009d9c: d503 bpl.n 8009da6 <setvbuf+0x6a>
  12905. 8009d9e: 6921 ldr r1, [r4, #16]
  12906. 8009da0: 4630 mov r0, r6
  12907. 8009da2: f001 fc7d bl 800b6a0 <_free_r>
  12908. 8009da6: 89a3 ldrh r3, [r4, #12]
  12909. 8009da8: f1b8 0f02 cmp.w r8, #2
  12910. 8009dac: f423 634a bic.w r3, r3, #3232 ; 0xca0
  12911. 8009db0: f023 0303 bic.w r3, r3, #3
  12912. 8009db4: 81a3 strh r3, [r4, #12]
  12913. 8009db6: d05d beq.n 8009e74 <setvbuf+0x138>
  12914. 8009db8: ab01 add r3, sp, #4
  12915. 8009dba: 466a mov r2, sp
  12916. 8009dbc: 4621 mov r1, r4
  12917. 8009dbe: 4630 mov r0, r6
  12918. 8009dc0: f001 f914 bl 800afec <__swhatbuf_r>
  12919. 8009dc4: 89a3 ldrh r3, [r4, #12]
  12920. 8009dc6: 4318 orrs r0, r3
  12921. 8009dc8: 81a0 strh r0, [r4, #12]
  12922. 8009dca: bb2d cbnz r5, 8009e18 <setvbuf+0xdc>
  12923. 8009dcc: 9d00 ldr r5, [sp, #0]
  12924. 8009dce: 4628 mov r0, r5
  12925. 8009dd0: f001 f970 bl 800b0b4 <malloc>
  12926. 8009dd4: 4607 mov r7, r0
  12927. 8009dd6: 2800 cmp r0, #0
  12928. 8009dd8: d14e bne.n 8009e78 <setvbuf+0x13c>
  12929. 8009dda: f8dd 9000 ldr.w r9, [sp]
  12930. 8009dde: 45a9 cmp r9, r5
  12931. 8009de0: d13c bne.n 8009e5c <setvbuf+0x120>
  12932. 8009de2: f04f 30ff mov.w r0, #4294967295
  12933. 8009de6: 89a3 ldrh r3, [r4, #12]
  12934. 8009de8: f043 0302 orr.w r3, r3, #2
  12935. 8009dec: 81a3 strh r3, [r4, #12]
  12936. 8009dee: 2300 movs r3, #0
  12937. 8009df0: 60a3 str r3, [r4, #8]
  12938. 8009df2: f104 0347 add.w r3, r4, #71 ; 0x47
  12939. 8009df6: 6023 str r3, [r4, #0]
  12940. 8009df8: 6123 str r3, [r4, #16]
  12941. 8009dfa: 2301 movs r3, #1
  12942. 8009dfc: 6163 str r3, [r4, #20]
  12943. 8009dfe: b003 add sp, #12
  12944. 8009e00: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc}
  12945. 8009e04: 4b22 ldr r3, [pc, #136] ; (8009e90 <setvbuf+0x154>)
  12946. 8009e06: 429c cmp r4, r3
  12947. 8009e08: d101 bne.n 8009e0e <setvbuf+0xd2>
  12948. 8009e0a: 68b4 ldr r4, [r6, #8]
  12949. 8009e0c: e7a8 b.n 8009d60 <setvbuf+0x24>
  12950. 8009e0e: 4b21 ldr r3, [pc, #132] ; (8009e94 <setvbuf+0x158>)
  12951. 8009e10: 429c cmp r4, r3
  12952. 8009e12: bf08 it eq
  12953. 8009e14: 68f4 ldreq r4, [r6, #12]
  12954. 8009e16: e7a3 b.n 8009d60 <setvbuf+0x24>
  12955. 8009e18: 2f00 cmp r7, #0
  12956. 8009e1a: d0d8 beq.n 8009dce <setvbuf+0x92>
  12957. 8009e1c: 69b3 ldr r3, [r6, #24]
  12958. 8009e1e: b913 cbnz r3, 8009e26 <setvbuf+0xea>
  12959. 8009e20: 4630 mov r0, r6
  12960. 8009e22: f001 f84b bl 800aebc <__sinit>
  12961. 8009e26: f1b8 0f01 cmp.w r8, #1
  12962. 8009e2a: bf08 it eq
  12963. 8009e2c: 89a3 ldrheq r3, [r4, #12]
  12964. 8009e2e: 6027 str r7, [r4, #0]
  12965. 8009e30: bf04 itt eq
  12966. 8009e32: f043 0301 orreq.w r3, r3, #1
  12967. 8009e36: 81a3 strheq r3, [r4, #12]
  12968. 8009e38: 89a3 ldrh r3, [r4, #12]
  12969. 8009e3a: 6127 str r7, [r4, #16]
  12970. 8009e3c: f013 0008 ands.w r0, r3, #8
  12971. 8009e40: 6165 str r5, [r4, #20]
  12972. 8009e42: d01b beq.n 8009e7c <setvbuf+0x140>
  12973. 8009e44: f013 0001 ands.w r0, r3, #1
  12974. 8009e48: f04f 0300 mov.w r3, #0
  12975. 8009e4c: bf1f itttt ne
  12976. 8009e4e: 426d negne r5, r5
  12977. 8009e50: 60a3 strne r3, [r4, #8]
  12978. 8009e52: 61a5 strne r5, [r4, #24]
  12979. 8009e54: 4618 movne r0, r3
  12980. 8009e56: bf08 it eq
  12981. 8009e58: 60a5 streq r5, [r4, #8]
  12982. 8009e5a: e7d0 b.n 8009dfe <setvbuf+0xc2>
  12983. 8009e5c: 4648 mov r0, r9
  12984. 8009e5e: f001 f929 bl 800b0b4 <malloc>
  12985. 8009e62: 4607 mov r7, r0
  12986. 8009e64: 2800 cmp r0, #0
  12987. 8009e66: d0bc beq.n 8009de2 <setvbuf+0xa6>
  12988. 8009e68: 89a3 ldrh r3, [r4, #12]
  12989. 8009e6a: 464d mov r5, r9
  12990. 8009e6c: f043 0380 orr.w r3, r3, #128 ; 0x80
  12991. 8009e70: 81a3 strh r3, [r4, #12]
  12992. 8009e72: e7d3 b.n 8009e1c <setvbuf+0xe0>
  12993. 8009e74: 2000 movs r0, #0
  12994. 8009e76: e7b6 b.n 8009de6 <setvbuf+0xaa>
  12995. 8009e78: 46a9 mov r9, r5
  12996. 8009e7a: e7f5 b.n 8009e68 <setvbuf+0x12c>
  12997. 8009e7c: 60a0 str r0, [r4, #8]
  12998. 8009e7e: e7be b.n 8009dfe <setvbuf+0xc2>
  12999. 8009e80: f04f 30ff mov.w r0, #4294967295
  13000. 8009e84: e7bb b.n 8009dfe <setvbuf+0xc2>
  13001. 8009e86: bf00 nop
  13002. 8009e88: 20000234 .word 0x20000234
  13003. 8009e8c: 0800bd80 .word 0x0800bd80
  13004. 8009e90: 0800bda0 .word 0x0800bda0
  13005. 8009e94: 0800bd60 .word 0x0800bd60
  13006. 08009e98 <__swbuf_r>:
  13007. 8009e98: b5f8 push {r3, r4, r5, r6, r7, lr}
  13008. 8009e9a: 460e mov r6, r1
  13009. 8009e9c: 4614 mov r4, r2
  13010. 8009e9e: 4605 mov r5, r0
  13011. 8009ea0: b118 cbz r0, 8009eaa <__swbuf_r+0x12>
  13012. 8009ea2: 6983 ldr r3, [r0, #24]
  13013. 8009ea4: b90b cbnz r3, 8009eaa <__swbuf_r+0x12>
  13014. 8009ea6: f001 f809 bl 800aebc <__sinit>
  13015. 8009eaa: 4b21 ldr r3, [pc, #132] ; (8009f30 <__swbuf_r+0x98>)
  13016. 8009eac: 429c cmp r4, r3
  13017. 8009eae: d12a bne.n 8009f06 <__swbuf_r+0x6e>
  13018. 8009eb0: 686c ldr r4, [r5, #4]
  13019. 8009eb2: 69a3 ldr r3, [r4, #24]
  13020. 8009eb4: 60a3 str r3, [r4, #8]
  13021. 8009eb6: 89a3 ldrh r3, [r4, #12]
  13022. 8009eb8: 071a lsls r2, r3, #28
  13023. 8009eba: d52e bpl.n 8009f1a <__swbuf_r+0x82>
  13024. 8009ebc: 6923 ldr r3, [r4, #16]
  13025. 8009ebe: b363 cbz r3, 8009f1a <__swbuf_r+0x82>
  13026. 8009ec0: 6923 ldr r3, [r4, #16]
  13027. 8009ec2: 6820 ldr r0, [r4, #0]
  13028. 8009ec4: b2f6 uxtb r6, r6
  13029. 8009ec6: 1ac0 subs r0, r0, r3
  13030. 8009ec8: 6963 ldr r3, [r4, #20]
  13031. 8009eca: 4637 mov r7, r6
  13032. 8009ecc: 4298 cmp r0, r3
  13033. 8009ece: db04 blt.n 8009eda <__swbuf_r+0x42>
  13034. 8009ed0: 4621 mov r1, r4
  13035. 8009ed2: 4628 mov r0, r5
  13036. 8009ed4: f000 ff88 bl 800ade8 <_fflush_r>
  13037. 8009ed8: bb28 cbnz r0, 8009f26 <__swbuf_r+0x8e>
  13038. 8009eda: 68a3 ldr r3, [r4, #8]
  13039. 8009edc: 3001 adds r0, #1
  13040. 8009ede: 3b01 subs r3, #1
  13041. 8009ee0: 60a3 str r3, [r4, #8]
  13042. 8009ee2: 6823 ldr r3, [r4, #0]
  13043. 8009ee4: 1c5a adds r2, r3, #1
  13044. 8009ee6: 6022 str r2, [r4, #0]
  13045. 8009ee8: 701e strb r6, [r3, #0]
  13046. 8009eea: 6963 ldr r3, [r4, #20]
  13047. 8009eec: 4298 cmp r0, r3
  13048. 8009eee: d004 beq.n 8009efa <__swbuf_r+0x62>
  13049. 8009ef0: 89a3 ldrh r3, [r4, #12]
  13050. 8009ef2: 07db lsls r3, r3, #31
  13051. 8009ef4: d519 bpl.n 8009f2a <__swbuf_r+0x92>
  13052. 8009ef6: 2e0a cmp r6, #10
  13053. 8009ef8: d117 bne.n 8009f2a <__swbuf_r+0x92>
  13054. 8009efa: 4621 mov r1, r4
  13055. 8009efc: 4628 mov r0, r5
  13056. 8009efe: f000 ff73 bl 800ade8 <_fflush_r>
  13057. 8009f02: b190 cbz r0, 8009f2a <__swbuf_r+0x92>
  13058. 8009f04: e00f b.n 8009f26 <__swbuf_r+0x8e>
  13059. 8009f06: 4b0b ldr r3, [pc, #44] ; (8009f34 <__swbuf_r+0x9c>)
  13060. 8009f08: 429c cmp r4, r3
  13061. 8009f0a: d101 bne.n 8009f10 <__swbuf_r+0x78>
  13062. 8009f0c: 68ac ldr r4, [r5, #8]
  13063. 8009f0e: e7d0 b.n 8009eb2 <__swbuf_r+0x1a>
  13064. 8009f10: 4b09 ldr r3, [pc, #36] ; (8009f38 <__swbuf_r+0xa0>)
  13065. 8009f12: 429c cmp r4, r3
  13066. 8009f14: bf08 it eq
  13067. 8009f16: 68ec ldreq r4, [r5, #12]
  13068. 8009f18: e7cb b.n 8009eb2 <__swbuf_r+0x1a>
  13069. 8009f1a: 4621 mov r1, r4
  13070. 8009f1c: 4628 mov r0, r5
  13071. 8009f1e: f000 f80d bl 8009f3c <__swsetup_r>
  13072. 8009f22: 2800 cmp r0, #0
  13073. 8009f24: d0cc beq.n 8009ec0 <__swbuf_r+0x28>
  13074. 8009f26: f04f 37ff mov.w r7, #4294967295
  13075. 8009f2a: 4638 mov r0, r7
  13076. 8009f2c: bdf8 pop {r3, r4, r5, r6, r7, pc}
  13077. 8009f2e: bf00 nop
  13078. 8009f30: 0800bd80 .word 0x0800bd80
  13079. 8009f34: 0800bda0 .word 0x0800bda0
  13080. 8009f38: 0800bd60 .word 0x0800bd60
  13081. 08009f3c <__swsetup_r>:
  13082. 8009f3c: 4b32 ldr r3, [pc, #200] ; (800a008 <__swsetup_r+0xcc>)
  13083. 8009f3e: b570 push {r4, r5, r6, lr}
  13084. 8009f40: 681d ldr r5, [r3, #0]
  13085. 8009f42: 4606 mov r6, r0
  13086. 8009f44: 460c mov r4, r1
  13087. 8009f46: b125 cbz r5, 8009f52 <__swsetup_r+0x16>
  13088. 8009f48: 69ab ldr r3, [r5, #24]
  13089. 8009f4a: b913 cbnz r3, 8009f52 <__swsetup_r+0x16>
  13090. 8009f4c: 4628 mov r0, r5
  13091. 8009f4e: f000 ffb5 bl 800aebc <__sinit>
  13092. 8009f52: 4b2e ldr r3, [pc, #184] ; (800a00c <__swsetup_r+0xd0>)
  13093. 8009f54: 429c cmp r4, r3
  13094. 8009f56: d10f bne.n 8009f78 <__swsetup_r+0x3c>
  13095. 8009f58: 686c ldr r4, [r5, #4]
  13096. 8009f5a: f9b4 300c ldrsh.w r3, [r4, #12]
  13097. 8009f5e: b29a uxth r2, r3
  13098. 8009f60: 0715 lsls r5, r2, #28
  13099. 8009f62: d42c bmi.n 8009fbe <__swsetup_r+0x82>
  13100. 8009f64: 06d0 lsls r0, r2, #27
  13101. 8009f66: d411 bmi.n 8009f8c <__swsetup_r+0x50>
  13102. 8009f68: 2209 movs r2, #9
  13103. 8009f6a: 6032 str r2, [r6, #0]
  13104. 8009f6c: f043 0340 orr.w r3, r3, #64 ; 0x40
  13105. 8009f70: 81a3 strh r3, [r4, #12]
  13106. 8009f72: f04f 30ff mov.w r0, #4294967295
  13107. 8009f76: bd70 pop {r4, r5, r6, pc}
  13108. 8009f78: 4b25 ldr r3, [pc, #148] ; (800a010 <__swsetup_r+0xd4>)
  13109. 8009f7a: 429c cmp r4, r3
  13110. 8009f7c: d101 bne.n 8009f82 <__swsetup_r+0x46>
  13111. 8009f7e: 68ac ldr r4, [r5, #8]
  13112. 8009f80: e7eb b.n 8009f5a <__swsetup_r+0x1e>
  13113. 8009f82: 4b24 ldr r3, [pc, #144] ; (800a014 <__swsetup_r+0xd8>)
  13114. 8009f84: 429c cmp r4, r3
  13115. 8009f86: bf08 it eq
  13116. 8009f88: 68ec ldreq r4, [r5, #12]
  13117. 8009f8a: e7e6 b.n 8009f5a <__swsetup_r+0x1e>
  13118. 8009f8c: 0751 lsls r1, r2, #29
  13119. 8009f8e: d512 bpl.n 8009fb6 <__swsetup_r+0x7a>
  13120. 8009f90: 6b61 ldr r1, [r4, #52] ; 0x34
  13121. 8009f92: b141 cbz r1, 8009fa6 <__swsetup_r+0x6a>
  13122. 8009f94: f104 0344 add.w r3, r4, #68 ; 0x44
  13123. 8009f98: 4299 cmp r1, r3
  13124. 8009f9a: d002 beq.n 8009fa2 <__swsetup_r+0x66>
  13125. 8009f9c: 4630 mov r0, r6
  13126. 8009f9e: f001 fb7f bl 800b6a0 <_free_r>
  13127. 8009fa2: 2300 movs r3, #0
  13128. 8009fa4: 6363 str r3, [r4, #52] ; 0x34
  13129. 8009fa6: 89a3 ldrh r3, [r4, #12]
  13130. 8009fa8: f023 0324 bic.w r3, r3, #36 ; 0x24
  13131. 8009fac: 81a3 strh r3, [r4, #12]
  13132. 8009fae: 2300 movs r3, #0
  13133. 8009fb0: 6063 str r3, [r4, #4]
  13134. 8009fb2: 6923 ldr r3, [r4, #16]
  13135. 8009fb4: 6023 str r3, [r4, #0]
  13136. 8009fb6: 89a3 ldrh r3, [r4, #12]
  13137. 8009fb8: f043 0308 orr.w r3, r3, #8
  13138. 8009fbc: 81a3 strh r3, [r4, #12]
  13139. 8009fbe: 6923 ldr r3, [r4, #16]
  13140. 8009fc0: b94b cbnz r3, 8009fd6 <__swsetup_r+0x9a>
  13141. 8009fc2: 89a3 ldrh r3, [r4, #12]
  13142. 8009fc4: f403 7320 and.w r3, r3, #640 ; 0x280
  13143. 8009fc8: f5b3 7f00 cmp.w r3, #512 ; 0x200
  13144. 8009fcc: d003 beq.n 8009fd6 <__swsetup_r+0x9a>
  13145. 8009fce: 4621 mov r1, r4
  13146. 8009fd0: 4630 mov r0, r6
  13147. 8009fd2: f001 f82f bl 800b034 <__smakebuf_r>
  13148. 8009fd6: 89a2 ldrh r2, [r4, #12]
  13149. 8009fd8: f012 0301 ands.w r3, r2, #1
  13150. 8009fdc: d00c beq.n 8009ff8 <__swsetup_r+0xbc>
  13151. 8009fde: 2300 movs r3, #0
  13152. 8009fe0: 60a3 str r3, [r4, #8]
  13153. 8009fe2: 6963 ldr r3, [r4, #20]
  13154. 8009fe4: 425b negs r3, r3
  13155. 8009fe6: 61a3 str r3, [r4, #24]
  13156. 8009fe8: 6923 ldr r3, [r4, #16]
  13157. 8009fea: b953 cbnz r3, 800a002 <__swsetup_r+0xc6>
  13158. 8009fec: f9b4 300c ldrsh.w r3, [r4, #12]
  13159. 8009ff0: f013 0080 ands.w r0, r3, #128 ; 0x80
  13160. 8009ff4: d1ba bne.n 8009f6c <__swsetup_r+0x30>
  13161. 8009ff6: bd70 pop {r4, r5, r6, pc}
  13162. 8009ff8: 0792 lsls r2, r2, #30
  13163. 8009ffa: bf58 it pl
  13164. 8009ffc: 6963 ldrpl r3, [r4, #20]
  13165. 8009ffe: 60a3 str r3, [r4, #8]
  13166. 800a000: e7f2 b.n 8009fe8 <__swsetup_r+0xac>
  13167. 800a002: 2000 movs r0, #0
  13168. 800a004: e7f7 b.n 8009ff6 <__swsetup_r+0xba>
  13169. 800a006: bf00 nop
  13170. 800a008: 20000234 .word 0x20000234
  13171. 800a00c: 0800bd80 .word 0x0800bd80
  13172. 800a010: 0800bda0 .word 0x0800bda0
  13173. 800a014: 0800bd60 .word 0x0800bd60
  13174. 0800a018 <quorem>:
  13175. 800a018: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
  13176. 800a01c: 6903 ldr r3, [r0, #16]
  13177. 800a01e: 690c ldr r4, [r1, #16]
  13178. 800a020: 4680 mov r8, r0
  13179. 800a022: 429c cmp r4, r3
  13180. 800a024: f300 8082 bgt.w 800a12c <quorem+0x114>
  13181. 800a028: 3c01 subs r4, #1
  13182. 800a02a: f101 0714 add.w r7, r1, #20
  13183. 800a02e: f100 0614 add.w r6, r0, #20
  13184. 800a032: f857 5024 ldr.w r5, [r7, r4, lsl #2]
  13185. 800a036: f856 0024 ldr.w r0, [r6, r4, lsl #2]
  13186. 800a03a: 3501 adds r5, #1
  13187. 800a03c: fbb0 f5f5 udiv r5, r0, r5
  13188. 800a040: ea4f 0e84 mov.w lr, r4, lsl #2
  13189. 800a044: eb06 030e add.w r3, r6, lr
  13190. 800a048: eb07 090e add.w r9, r7, lr
  13191. 800a04c: 9301 str r3, [sp, #4]
  13192. 800a04e: b38d cbz r5, 800a0b4 <quorem+0x9c>
  13193. 800a050: f04f 0a00 mov.w sl, #0
  13194. 800a054: 4638 mov r0, r7
  13195. 800a056: 46b4 mov ip, r6
  13196. 800a058: 46d3 mov fp, sl
  13197. 800a05a: f850 2b04 ldr.w r2, [r0], #4
  13198. 800a05e: b293 uxth r3, r2
  13199. 800a060: fb05 a303 mla r3, r5, r3, sl
  13200. 800a064: 0c12 lsrs r2, r2, #16
  13201. 800a066: ea4f 4a13 mov.w sl, r3, lsr #16
  13202. 800a06a: fb05 a202 mla r2, r5, r2, sl
  13203. 800a06e: b29b uxth r3, r3
  13204. 800a070: ebab 0303 sub.w r3, fp, r3
  13205. 800a074: f8bc b000 ldrh.w fp, [ip]
  13206. 800a078: ea4f 4a12 mov.w sl, r2, lsr #16
  13207. 800a07c: 445b add r3, fp
  13208. 800a07e: fa1f fb82 uxth.w fp, r2
  13209. 800a082: f8dc 2000 ldr.w r2, [ip]
  13210. 800a086: 4581 cmp r9, r0
  13211. 800a088: ebcb 4212 rsb r2, fp, r2, lsr #16
  13212. 800a08c: eb02 4223 add.w r2, r2, r3, asr #16
  13213. 800a090: b29b uxth r3, r3
  13214. 800a092: ea43 4302 orr.w r3, r3, r2, lsl #16
  13215. 800a096: ea4f 4b22 mov.w fp, r2, asr #16
  13216. 800a09a: f84c 3b04 str.w r3, [ip], #4
  13217. 800a09e: d2dc bcs.n 800a05a <quorem+0x42>
  13218. 800a0a0: f856 300e ldr.w r3, [r6, lr]
  13219. 800a0a4: b933 cbnz r3, 800a0b4 <quorem+0x9c>
  13220. 800a0a6: 9b01 ldr r3, [sp, #4]
  13221. 800a0a8: 3b04 subs r3, #4
  13222. 800a0aa: 429e cmp r6, r3
  13223. 800a0ac: 461a mov r2, r3
  13224. 800a0ae: d331 bcc.n 800a114 <quorem+0xfc>
  13225. 800a0b0: f8c8 4010 str.w r4, [r8, #16]
  13226. 800a0b4: 4640 mov r0, r8
  13227. 800a0b6: f001 fa1c bl 800b4f2 <__mcmp>
  13228. 800a0ba: 2800 cmp r0, #0
  13229. 800a0bc: db26 blt.n 800a10c <quorem+0xf4>
  13230. 800a0be: 4630 mov r0, r6
  13231. 800a0c0: f04f 0e00 mov.w lr, #0
  13232. 800a0c4: 3501 adds r5, #1
  13233. 800a0c6: f857 1b04 ldr.w r1, [r7], #4
  13234. 800a0ca: f8d0 c000 ldr.w ip, [r0]
  13235. 800a0ce: b28b uxth r3, r1
  13236. 800a0d0: ebae 0303 sub.w r3, lr, r3
  13237. 800a0d4: fa1f f28c uxth.w r2, ip
  13238. 800a0d8: 4413 add r3, r2
  13239. 800a0da: 0c0a lsrs r2, r1, #16
  13240. 800a0dc: ebc2 421c rsb r2, r2, ip, lsr #16
  13241. 800a0e0: eb02 4223 add.w r2, r2, r3, asr #16
  13242. 800a0e4: b29b uxth r3, r3
  13243. 800a0e6: ea43 4302 orr.w r3, r3, r2, lsl #16
  13244. 800a0ea: 45b9 cmp r9, r7
  13245. 800a0ec: ea4f 4e22 mov.w lr, r2, asr #16
  13246. 800a0f0: f840 3b04 str.w r3, [r0], #4
  13247. 800a0f4: d2e7 bcs.n 800a0c6 <quorem+0xae>
  13248. 800a0f6: f856 2024 ldr.w r2, [r6, r4, lsl #2]
  13249. 800a0fa: eb06 0384 add.w r3, r6, r4, lsl #2
  13250. 800a0fe: b92a cbnz r2, 800a10c <quorem+0xf4>
  13251. 800a100: 3b04 subs r3, #4
  13252. 800a102: 429e cmp r6, r3
  13253. 800a104: 461a mov r2, r3
  13254. 800a106: d30b bcc.n 800a120 <quorem+0x108>
  13255. 800a108: f8c8 4010 str.w r4, [r8, #16]
  13256. 800a10c: 4628 mov r0, r5
  13257. 800a10e: b003 add sp, #12
  13258. 800a110: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
  13259. 800a114: 6812 ldr r2, [r2, #0]
  13260. 800a116: 3b04 subs r3, #4
  13261. 800a118: 2a00 cmp r2, #0
  13262. 800a11a: d1c9 bne.n 800a0b0 <quorem+0x98>
  13263. 800a11c: 3c01 subs r4, #1
  13264. 800a11e: e7c4 b.n 800a0aa <quorem+0x92>
  13265. 800a120: 6812 ldr r2, [r2, #0]
  13266. 800a122: 3b04 subs r3, #4
  13267. 800a124: 2a00 cmp r2, #0
  13268. 800a126: d1ef bne.n 800a108 <quorem+0xf0>
  13269. 800a128: 3c01 subs r4, #1
  13270. 800a12a: e7ea b.n 800a102 <quorem+0xea>
  13271. 800a12c: 2000 movs r0, #0
  13272. 800a12e: e7ee b.n 800a10e <quorem+0xf6>
  13273. 0800a130 <_dtoa_r>:
  13274. 800a130: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
  13275. 800a134: 6a46 ldr r6, [r0, #36] ; 0x24
  13276. 800a136: b095 sub sp, #84 ; 0x54
  13277. 800a138: 4604 mov r4, r0
  13278. 800a13a: 9d21 ldr r5, [sp, #132] ; 0x84
  13279. 800a13c: e9cd 2302 strd r2, r3, [sp, #8]
  13280. 800a140: b93e cbnz r6, 800a152 <_dtoa_r+0x22>
  13281. 800a142: 2010 movs r0, #16
  13282. 800a144: f000 ffb6 bl 800b0b4 <malloc>
  13283. 800a148: 6260 str r0, [r4, #36] ; 0x24
  13284. 800a14a: 6046 str r6, [r0, #4]
  13285. 800a14c: 6086 str r6, [r0, #8]
  13286. 800a14e: 6006 str r6, [r0, #0]
  13287. 800a150: 60c6 str r6, [r0, #12]
  13288. 800a152: 6a63 ldr r3, [r4, #36] ; 0x24
  13289. 800a154: 6819 ldr r1, [r3, #0]
  13290. 800a156: b151 cbz r1, 800a16e <_dtoa_r+0x3e>
  13291. 800a158: 685a ldr r2, [r3, #4]
  13292. 800a15a: 2301 movs r3, #1
  13293. 800a15c: 4093 lsls r3, r2
  13294. 800a15e: 604a str r2, [r1, #4]
  13295. 800a160: 608b str r3, [r1, #8]
  13296. 800a162: 4620 mov r0, r4
  13297. 800a164: f000 fff0 bl 800b148 <_Bfree>
  13298. 800a168: 2200 movs r2, #0
  13299. 800a16a: 6a63 ldr r3, [r4, #36] ; 0x24
  13300. 800a16c: 601a str r2, [r3, #0]
  13301. 800a16e: 9b03 ldr r3, [sp, #12]
  13302. 800a170: 2b00 cmp r3, #0
  13303. 800a172: bfb7 itett lt
  13304. 800a174: 2301 movlt r3, #1
  13305. 800a176: 2300 movge r3, #0
  13306. 800a178: 602b strlt r3, [r5, #0]
  13307. 800a17a: 9b03 ldrlt r3, [sp, #12]
  13308. 800a17c: bfae itee ge
  13309. 800a17e: 602b strge r3, [r5, #0]
  13310. 800a180: f023 4300 biclt.w r3, r3, #2147483648 ; 0x80000000
  13311. 800a184: 9303 strlt r3, [sp, #12]
  13312. 800a186: f8dd 900c ldr.w r9, [sp, #12]
  13313. 800a18a: 4bab ldr r3, [pc, #684] ; (800a438 <_dtoa_r+0x308>)
  13314. 800a18c: ea33 0309 bics.w r3, r3, r9
  13315. 800a190: d11b bne.n 800a1ca <_dtoa_r+0x9a>
  13316. 800a192: f242 730f movw r3, #9999 ; 0x270f
  13317. 800a196: 9a20 ldr r2, [sp, #128] ; 0x80
  13318. 800a198: 6013 str r3, [r2, #0]
  13319. 800a19a: 9b02 ldr r3, [sp, #8]
  13320. 800a19c: b923 cbnz r3, 800a1a8 <_dtoa_r+0x78>
  13321. 800a19e: f3c9 0013 ubfx r0, r9, #0, #20
  13322. 800a1a2: 2800 cmp r0, #0
  13323. 800a1a4: f000 8583 beq.w 800acae <_dtoa_r+0xb7e>
  13324. 800a1a8: 9b22 ldr r3, [sp, #136] ; 0x88
  13325. 800a1aa: b953 cbnz r3, 800a1c2 <_dtoa_r+0x92>
  13326. 800a1ac: 4ba3 ldr r3, [pc, #652] ; (800a43c <_dtoa_r+0x30c>)
  13327. 800a1ae: e021 b.n 800a1f4 <_dtoa_r+0xc4>
  13328. 800a1b0: 4ba3 ldr r3, [pc, #652] ; (800a440 <_dtoa_r+0x310>)
  13329. 800a1b2: 9306 str r3, [sp, #24]
  13330. 800a1b4: 3308 adds r3, #8
  13331. 800a1b6: 9a22 ldr r2, [sp, #136] ; 0x88
  13332. 800a1b8: 6013 str r3, [r2, #0]
  13333. 800a1ba: 9806 ldr r0, [sp, #24]
  13334. 800a1bc: b015 add sp, #84 ; 0x54
  13335. 800a1be: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
  13336. 800a1c2: 4b9e ldr r3, [pc, #632] ; (800a43c <_dtoa_r+0x30c>)
  13337. 800a1c4: 9306 str r3, [sp, #24]
  13338. 800a1c6: 3303 adds r3, #3
  13339. 800a1c8: e7f5 b.n 800a1b6 <_dtoa_r+0x86>
  13340. 800a1ca: e9dd 6702 ldrd r6, r7, [sp, #8]
  13341. 800a1ce: 2200 movs r2, #0
  13342. 800a1d0: 2300 movs r3, #0
  13343. 800a1d2: 4630 mov r0, r6
  13344. 800a1d4: 4639 mov r1, r7
  13345. 800a1d6: f7fa fc5b bl 8004a90 <__aeabi_dcmpeq>
  13346. 800a1da: 4680 mov r8, r0
  13347. 800a1dc: b160 cbz r0, 800a1f8 <_dtoa_r+0xc8>
  13348. 800a1de: 2301 movs r3, #1
  13349. 800a1e0: 9a20 ldr r2, [sp, #128] ; 0x80
  13350. 800a1e2: 6013 str r3, [r2, #0]
  13351. 800a1e4: 9b22 ldr r3, [sp, #136] ; 0x88
  13352. 800a1e6: 2b00 cmp r3, #0
  13353. 800a1e8: f000 855e beq.w 800aca8 <_dtoa_r+0xb78>
  13354. 800a1ec: 4b95 ldr r3, [pc, #596] ; (800a444 <_dtoa_r+0x314>)
  13355. 800a1ee: 9a22 ldr r2, [sp, #136] ; 0x88
  13356. 800a1f0: 6013 str r3, [r2, #0]
  13357. 800a1f2: 3b01 subs r3, #1
  13358. 800a1f4: 9306 str r3, [sp, #24]
  13359. 800a1f6: e7e0 b.n 800a1ba <_dtoa_r+0x8a>
  13360. 800a1f8: ab12 add r3, sp, #72 ; 0x48
  13361. 800a1fa: 9301 str r3, [sp, #4]
  13362. 800a1fc: ab13 add r3, sp, #76 ; 0x4c
  13363. 800a1fe: 9300 str r3, [sp, #0]
  13364. 800a200: 4632 mov r2, r6
  13365. 800a202: 463b mov r3, r7
  13366. 800a204: 4620 mov r0, r4
  13367. 800a206: f001 f9ed bl 800b5e4 <__d2b>
  13368. 800a20a: f3c9 550a ubfx r5, r9, #20, #11
  13369. 800a20e: 4682 mov sl, r0
  13370. 800a210: 2d00 cmp r5, #0
  13371. 800a212: d07d beq.n 800a310 <_dtoa_r+0x1e0>
  13372. 800a214: 4630 mov r0, r6
  13373. 800a216: f3c7 0313 ubfx r3, r7, #0, #20
  13374. 800a21a: f043 517f orr.w r1, r3, #1069547520 ; 0x3fc00000
  13375. 800a21e: f441 1140 orr.w r1, r1, #3145728 ; 0x300000
  13376. 800a222: f2a5 35ff subw r5, r5, #1023 ; 0x3ff
  13377. 800a226: f8cd 8040 str.w r8, [sp, #64] ; 0x40
  13378. 800a22a: 2200 movs r2, #0
  13379. 800a22c: 4b86 ldr r3, [pc, #536] ; (800a448 <_dtoa_r+0x318>)
  13380. 800a22e: f7fa f813 bl 8004258 <__aeabi_dsub>
  13381. 800a232: a37b add r3, pc, #492 ; (adr r3, 800a420 <_dtoa_r+0x2f0>)
  13382. 800a234: e9d3 2300 ldrd r2, r3, [r3]
  13383. 800a238: f7fa f9c2 bl 80045c0 <__aeabi_dmul>
  13384. 800a23c: a37a add r3, pc, #488 ; (adr r3, 800a428 <_dtoa_r+0x2f8>)
  13385. 800a23e: e9d3 2300 ldrd r2, r3, [r3]
  13386. 800a242: f7fa f80b bl 800425c <__adddf3>
  13387. 800a246: 4606 mov r6, r0
  13388. 800a248: 4628 mov r0, r5
  13389. 800a24a: 460f mov r7, r1
  13390. 800a24c: f7fa f952 bl 80044f4 <__aeabi_i2d>
  13391. 800a250: a377 add r3, pc, #476 ; (adr r3, 800a430 <_dtoa_r+0x300>)
  13392. 800a252: e9d3 2300 ldrd r2, r3, [r3]
  13393. 800a256: f7fa f9b3 bl 80045c0 <__aeabi_dmul>
  13394. 800a25a: 4602 mov r2, r0
  13395. 800a25c: 460b mov r3, r1
  13396. 800a25e: 4630 mov r0, r6
  13397. 800a260: 4639 mov r1, r7
  13398. 800a262: f7f9 fffb bl 800425c <__adddf3>
  13399. 800a266: 4606 mov r6, r0
  13400. 800a268: 460f mov r7, r1
  13401. 800a26a: f7fa fc59 bl 8004b20 <__aeabi_d2iz>
  13402. 800a26e: 2200 movs r2, #0
  13403. 800a270: 4683 mov fp, r0
  13404. 800a272: 2300 movs r3, #0
  13405. 800a274: 4630 mov r0, r6
  13406. 800a276: 4639 mov r1, r7
  13407. 800a278: f7fa fc14 bl 8004aa4 <__aeabi_dcmplt>
  13408. 800a27c: b158 cbz r0, 800a296 <_dtoa_r+0x166>
  13409. 800a27e: 4658 mov r0, fp
  13410. 800a280: f7fa f938 bl 80044f4 <__aeabi_i2d>
  13411. 800a284: 4602 mov r2, r0
  13412. 800a286: 460b mov r3, r1
  13413. 800a288: 4630 mov r0, r6
  13414. 800a28a: 4639 mov r1, r7
  13415. 800a28c: f7fa fc00 bl 8004a90 <__aeabi_dcmpeq>
  13416. 800a290: b908 cbnz r0, 800a296 <_dtoa_r+0x166>
  13417. 800a292: f10b 3bff add.w fp, fp, #4294967295
  13418. 800a296: f1bb 0f16 cmp.w fp, #22
  13419. 800a29a: d858 bhi.n 800a34e <_dtoa_r+0x21e>
  13420. 800a29c: e9dd 2302 ldrd r2, r3, [sp, #8]
  13421. 800a2a0: 496a ldr r1, [pc, #424] ; (800a44c <_dtoa_r+0x31c>)
  13422. 800a2a2: eb01 01cb add.w r1, r1, fp, lsl #3
  13423. 800a2a6: e9d1 0100 ldrd r0, r1, [r1]
  13424. 800a2aa: f7fa fc19 bl 8004ae0 <__aeabi_dcmpgt>
  13425. 800a2ae: 2800 cmp r0, #0
  13426. 800a2b0: d04f beq.n 800a352 <_dtoa_r+0x222>
  13427. 800a2b2: 2300 movs r3, #0
  13428. 800a2b4: f10b 3bff add.w fp, fp, #4294967295
  13429. 800a2b8: 930d str r3, [sp, #52] ; 0x34
  13430. 800a2ba: 9b12 ldr r3, [sp, #72] ; 0x48
  13431. 800a2bc: 1b5d subs r5, r3, r5
  13432. 800a2be: 1e6b subs r3, r5, #1
  13433. 800a2c0: 9307 str r3, [sp, #28]
  13434. 800a2c2: bf43 ittte mi
  13435. 800a2c4: 2300 movmi r3, #0
  13436. 800a2c6: f1c5 0801 rsbmi r8, r5, #1
  13437. 800a2ca: 9307 strmi r3, [sp, #28]
  13438. 800a2cc: f04f 0800 movpl.w r8, #0
  13439. 800a2d0: f1bb 0f00 cmp.w fp, #0
  13440. 800a2d4: db3f blt.n 800a356 <_dtoa_r+0x226>
  13441. 800a2d6: 9b07 ldr r3, [sp, #28]
  13442. 800a2d8: f8cd b030 str.w fp, [sp, #48] ; 0x30
  13443. 800a2dc: 445b add r3, fp
  13444. 800a2de: 9307 str r3, [sp, #28]
  13445. 800a2e0: 2300 movs r3, #0
  13446. 800a2e2: 9308 str r3, [sp, #32]
  13447. 800a2e4: 9b1e ldr r3, [sp, #120] ; 0x78
  13448. 800a2e6: 2b09 cmp r3, #9
  13449. 800a2e8: f200 80b4 bhi.w 800a454 <_dtoa_r+0x324>
  13450. 800a2ec: 2b05 cmp r3, #5
  13451. 800a2ee: bfc4 itt gt
  13452. 800a2f0: 3b04 subgt r3, #4
  13453. 800a2f2: 931e strgt r3, [sp, #120] ; 0x78
  13454. 800a2f4: 9b1e ldr r3, [sp, #120] ; 0x78
  13455. 800a2f6: bfc8 it gt
  13456. 800a2f8: 2600 movgt r6, #0
  13457. 800a2fa: f1a3 0302 sub.w r3, r3, #2
  13458. 800a2fe: bfd8 it le
  13459. 800a300: 2601 movle r6, #1
  13460. 800a302: 2b03 cmp r3, #3
  13461. 800a304: f200 80b2 bhi.w 800a46c <_dtoa_r+0x33c>
  13462. 800a308: e8df f003 tbb [pc, r3]
  13463. 800a30c: 782d8684 .word 0x782d8684
  13464. 800a310: 9b13 ldr r3, [sp, #76] ; 0x4c
  13465. 800a312: 9d12 ldr r5, [sp, #72] ; 0x48
  13466. 800a314: 441d add r5, r3
  13467. 800a316: f205 4332 addw r3, r5, #1074 ; 0x432
  13468. 800a31a: 2b20 cmp r3, #32
  13469. 800a31c: dd11 ble.n 800a342 <_dtoa_r+0x212>
  13470. 800a31e: 9a02 ldr r2, [sp, #8]
  13471. 800a320: f205 4012 addw r0, r5, #1042 ; 0x412
  13472. 800a324: f1c3 0340 rsb r3, r3, #64 ; 0x40
  13473. 800a328: fa22 f000 lsr.w r0, r2, r0
  13474. 800a32c: fa09 f303 lsl.w r3, r9, r3
  13475. 800a330: 4318 orrs r0, r3
  13476. 800a332: f7fa f8cf bl 80044d4 <__aeabi_ui2d>
  13477. 800a336: 2301 movs r3, #1
  13478. 800a338: f1a1 71f8 sub.w r1, r1, #32505856 ; 0x1f00000
  13479. 800a33c: 3d01 subs r5, #1
  13480. 800a33e: 9310 str r3, [sp, #64] ; 0x40
  13481. 800a340: e773 b.n 800a22a <_dtoa_r+0xfa>
  13482. 800a342: f1c3 0020 rsb r0, r3, #32
  13483. 800a346: 9b02 ldr r3, [sp, #8]
  13484. 800a348: fa03 f000 lsl.w r0, r3, r0
  13485. 800a34c: e7f1 b.n 800a332 <_dtoa_r+0x202>
  13486. 800a34e: 2301 movs r3, #1
  13487. 800a350: e7b2 b.n 800a2b8 <_dtoa_r+0x188>
  13488. 800a352: 900d str r0, [sp, #52] ; 0x34
  13489. 800a354: e7b1 b.n 800a2ba <_dtoa_r+0x18a>
  13490. 800a356: f1cb 0300 rsb r3, fp, #0
  13491. 800a35a: 9308 str r3, [sp, #32]
  13492. 800a35c: 2300 movs r3, #0
  13493. 800a35e: eba8 080b sub.w r8, r8, fp
  13494. 800a362: 930c str r3, [sp, #48] ; 0x30
  13495. 800a364: e7be b.n 800a2e4 <_dtoa_r+0x1b4>
  13496. 800a366: 2301 movs r3, #1
  13497. 800a368: 9309 str r3, [sp, #36] ; 0x24
  13498. 800a36a: 9b1f ldr r3, [sp, #124] ; 0x7c
  13499. 800a36c: 2b00 cmp r3, #0
  13500. 800a36e: f340 8080 ble.w 800a472 <_dtoa_r+0x342>
  13501. 800a372: 4699 mov r9, r3
  13502. 800a374: 9304 str r3, [sp, #16]
  13503. 800a376: 2200 movs r2, #0
  13504. 800a378: 2104 movs r1, #4
  13505. 800a37a: 6a65 ldr r5, [r4, #36] ; 0x24
  13506. 800a37c: 606a str r2, [r5, #4]
  13507. 800a37e: f101 0214 add.w r2, r1, #20
  13508. 800a382: 429a cmp r2, r3
  13509. 800a384: d97a bls.n 800a47c <_dtoa_r+0x34c>
  13510. 800a386: 6869 ldr r1, [r5, #4]
  13511. 800a388: 4620 mov r0, r4
  13512. 800a38a: f000 fea9 bl 800b0e0 <_Balloc>
  13513. 800a38e: 6a63 ldr r3, [r4, #36] ; 0x24
  13514. 800a390: 6028 str r0, [r5, #0]
  13515. 800a392: 681b ldr r3, [r3, #0]
  13516. 800a394: f1b9 0f0e cmp.w r9, #14
  13517. 800a398: 9306 str r3, [sp, #24]
  13518. 800a39a: f200 80f0 bhi.w 800a57e <_dtoa_r+0x44e>
  13519. 800a39e: 2e00 cmp r6, #0
  13520. 800a3a0: f000 80ed beq.w 800a57e <_dtoa_r+0x44e>
  13521. 800a3a4: e9dd 2302 ldrd r2, r3, [sp, #8]
  13522. 800a3a8: f1bb 0f00 cmp.w fp, #0
  13523. 800a3ac: e9cd 230e strd r2, r3, [sp, #56] ; 0x38
  13524. 800a3b0: dd79 ble.n 800a4a6 <_dtoa_r+0x376>
  13525. 800a3b2: 4a26 ldr r2, [pc, #152] ; (800a44c <_dtoa_r+0x31c>)
  13526. 800a3b4: f00b 030f and.w r3, fp, #15
  13527. 800a3b8: ea4f 162b mov.w r6, fp, asr #4
  13528. 800a3bc: eb02 03c3 add.w r3, r2, r3, lsl #3
  13529. 800a3c0: 06f0 lsls r0, r6, #27
  13530. 800a3c2: e9d3 2300 ldrd r2, r3, [r3]
  13531. 800a3c6: e9cd 230a strd r2, r3, [sp, #40] ; 0x28
  13532. 800a3ca: d55c bpl.n 800a486 <_dtoa_r+0x356>
  13533. 800a3cc: e9dd 010e ldrd r0, r1, [sp, #56] ; 0x38
  13534. 800a3d0: 4b1f ldr r3, [pc, #124] ; (800a450 <_dtoa_r+0x320>)
  13535. 800a3d2: 2503 movs r5, #3
  13536. 800a3d4: e9d3 2308 ldrd r2, r3, [r3, #32]
  13537. 800a3d8: f7fa fa1c bl 8004814 <__aeabi_ddiv>
  13538. 800a3dc: e9cd 0102 strd r0, r1, [sp, #8]
  13539. 800a3e0: f006 060f and.w r6, r6, #15
  13540. 800a3e4: 4f1a ldr r7, [pc, #104] ; (800a450 <_dtoa_r+0x320>)
  13541. 800a3e6: 2e00 cmp r6, #0
  13542. 800a3e8: d14f bne.n 800a48a <_dtoa_r+0x35a>
  13543. 800a3ea: e9dd 230a ldrd r2, r3, [sp, #40] ; 0x28
  13544. 800a3ee: e9dd 0102 ldrd r0, r1, [sp, #8]
  13545. 800a3f2: f7fa fa0f bl 8004814 <__aeabi_ddiv>
  13546. 800a3f6: e9cd 0102 strd r0, r1, [sp, #8]
  13547. 800a3fa: e06e b.n 800a4da <_dtoa_r+0x3aa>
  13548. 800a3fc: 2301 movs r3, #1
  13549. 800a3fe: 9309 str r3, [sp, #36] ; 0x24
  13550. 800a400: 9b1f ldr r3, [sp, #124] ; 0x7c
  13551. 800a402: 445b add r3, fp
  13552. 800a404: f103 0901 add.w r9, r3, #1
  13553. 800a408: 9304 str r3, [sp, #16]
  13554. 800a40a: 464b mov r3, r9
  13555. 800a40c: 2b01 cmp r3, #1
  13556. 800a40e: bfb8 it lt
  13557. 800a410: 2301 movlt r3, #1
  13558. 800a412: e7b0 b.n 800a376 <_dtoa_r+0x246>
  13559. 800a414: 2300 movs r3, #0
  13560. 800a416: e7a7 b.n 800a368 <_dtoa_r+0x238>
  13561. 800a418: 2300 movs r3, #0
  13562. 800a41a: e7f0 b.n 800a3fe <_dtoa_r+0x2ce>
  13563. 800a41c: f3af 8000 nop.w
  13564. 800a420: 636f4361 .word 0x636f4361
  13565. 800a424: 3fd287a7 .word 0x3fd287a7
  13566. 800a428: 8b60c8b3 .word 0x8b60c8b3
  13567. 800a42c: 3fc68a28 .word 0x3fc68a28
  13568. 800a430: 509f79fb .word 0x509f79fb
  13569. 800a434: 3fd34413 .word 0x3fd34413
  13570. 800a438: 7ff00000 .word 0x7ff00000
  13571. 800a43c: 0800bd59 .word 0x0800bd59
  13572. 800a440: 0800bd50 .word 0x0800bd50
  13573. 800a444: 0800bd2d .word 0x0800bd2d
  13574. 800a448: 3ff80000 .word 0x3ff80000
  13575. 800a44c: 0800bde8 .word 0x0800bde8
  13576. 800a450: 0800bdc0 .word 0x0800bdc0
  13577. 800a454: 2601 movs r6, #1
  13578. 800a456: 2300 movs r3, #0
  13579. 800a458: 9609 str r6, [sp, #36] ; 0x24
  13580. 800a45a: 931e str r3, [sp, #120] ; 0x78
  13581. 800a45c: f04f 33ff mov.w r3, #4294967295
  13582. 800a460: 2200 movs r2, #0
  13583. 800a462: 9304 str r3, [sp, #16]
  13584. 800a464: 4699 mov r9, r3
  13585. 800a466: 2312 movs r3, #18
  13586. 800a468: 921f str r2, [sp, #124] ; 0x7c
  13587. 800a46a: e784 b.n 800a376 <_dtoa_r+0x246>
  13588. 800a46c: 2301 movs r3, #1
  13589. 800a46e: 9309 str r3, [sp, #36] ; 0x24
  13590. 800a470: e7f4 b.n 800a45c <_dtoa_r+0x32c>
  13591. 800a472: 2301 movs r3, #1
  13592. 800a474: 9304 str r3, [sp, #16]
  13593. 800a476: 4699 mov r9, r3
  13594. 800a478: 461a mov r2, r3
  13595. 800a47a: e7f5 b.n 800a468 <_dtoa_r+0x338>
  13596. 800a47c: 686a ldr r2, [r5, #4]
  13597. 800a47e: 0049 lsls r1, r1, #1
  13598. 800a480: 3201 adds r2, #1
  13599. 800a482: 606a str r2, [r5, #4]
  13600. 800a484: e77b b.n 800a37e <_dtoa_r+0x24e>
  13601. 800a486: 2502 movs r5, #2
  13602. 800a488: e7ac b.n 800a3e4 <_dtoa_r+0x2b4>
  13603. 800a48a: 07f1 lsls r1, r6, #31
  13604. 800a48c: d508 bpl.n 800a4a0 <_dtoa_r+0x370>
  13605. 800a48e: e9dd 010a ldrd r0, r1, [sp, #40] ; 0x28
  13606. 800a492: e9d7 2300 ldrd r2, r3, [r7]
  13607. 800a496: f7fa f893 bl 80045c0 <__aeabi_dmul>
  13608. 800a49a: e9cd 010a strd r0, r1, [sp, #40] ; 0x28
  13609. 800a49e: 3501 adds r5, #1
  13610. 800a4a0: 1076 asrs r6, r6, #1
  13611. 800a4a2: 3708 adds r7, #8
  13612. 800a4a4: e79f b.n 800a3e6 <_dtoa_r+0x2b6>
  13613. 800a4a6: f000 80a5 beq.w 800a5f4 <_dtoa_r+0x4c4>
  13614. 800a4aa: e9dd 010e ldrd r0, r1, [sp, #56] ; 0x38
  13615. 800a4ae: f1cb 0600 rsb r6, fp, #0
  13616. 800a4b2: 4ba2 ldr r3, [pc, #648] ; (800a73c <_dtoa_r+0x60c>)
  13617. 800a4b4: f006 020f and.w r2, r6, #15
  13618. 800a4b8: eb03 03c2 add.w r3, r3, r2, lsl #3
  13619. 800a4bc: e9d3 2300 ldrd r2, r3, [r3]
  13620. 800a4c0: f7fa f87e bl 80045c0 <__aeabi_dmul>
  13621. 800a4c4: 2502 movs r5, #2
  13622. 800a4c6: 2300 movs r3, #0
  13623. 800a4c8: e9cd 0102 strd r0, r1, [sp, #8]
  13624. 800a4cc: 4f9c ldr r7, [pc, #624] ; (800a740 <_dtoa_r+0x610>)
  13625. 800a4ce: 1136 asrs r6, r6, #4
  13626. 800a4d0: 2e00 cmp r6, #0
  13627. 800a4d2: f040 8084 bne.w 800a5de <_dtoa_r+0x4ae>
  13628. 800a4d6: 2b00 cmp r3, #0
  13629. 800a4d8: d18d bne.n 800a3f6 <_dtoa_r+0x2c6>
  13630. 800a4da: 9b0d ldr r3, [sp, #52] ; 0x34
  13631. 800a4dc: 2b00 cmp r3, #0
  13632. 800a4de: f000 808b beq.w 800a5f8 <_dtoa_r+0x4c8>
  13633. 800a4e2: e9dd 2302 ldrd r2, r3, [sp, #8]
  13634. 800a4e6: e9cd 230a strd r2, r3, [sp, #40] ; 0x28
  13635. 800a4ea: e9dd 010a ldrd r0, r1, [sp, #40] ; 0x28
  13636. 800a4ee: 2200 movs r2, #0
  13637. 800a4f0: 4b94 ldr r3, [pc, #592] ; (800a744 <_dtoa_r+0x614>)
  13638. 800a4f2: f7fa fad7 bl 8004aa4 <__aeabi_dcmplt>
  13639. 800a4f6: 2800 cmp r0, #0
  13640. 800a4f8: d07e beq.n 800a5f8 <_dtoa_r+0x4c8>
  13641. 800a4fa: f1b9 0f00 cmp.w r9, #0
  13642. 800a4fe: d07b beq.n 800a5f8 <_dtoa_r+0x4c8>
  13643. 800a500: 9b04 ldr r3, [sp, #16]
  13644. 800a502: 2b00 cmp r3, #0
  13645. 800a504: dd37 ble.n 800a576 <_dtoa_r+0x446>
  13646. 800a506: e9dd 010a ldrd r0, r1, [sp, #40] ; 0x28
  13647. 800a50a: 2200 movs r2, #0
  13648. 800a50c: 4b8e ldr r3, [pc, #568] ; (800a748 <_dtoa_r+0x618>)
  13649. 800a50e: f7fa f857 bl 80045c0 <__aeabi_dmul>
  13650. 800a512: e9cd 0102 strd r0, r1, [sp, #8]
  13651. 800a516: 9e04 ldr r6, [sp, #16]
  13652. 800a518: f10b 37ff add.w r7, fp, #4294967295
  13653. 800a51c: 3501 adds r5, #1
  13654. 800a51e: 4628 mov r0, r5
  13655. 800a520: f7f9 ffe8 bl 80044f4 <__aeabi_i2d>
  13656. 800a524: e9dd 2302 ldrd r2, r3, [sp, #8]
  13657. 800a528: f7fa f84a bl 80045c0 <__aeabi_dmul>
  13658. 800a52c: 4b87 ldr r3, [pc, #540] ; (800a74c <_dtoa_r+0x61c>)
  13659. 800a52e: 2200 movs r2, #0
  13660. 800a530: f7f9 fe94 bl 800425c <__adddf3>
  13661. 800a534: e9cd 010a strd r0, r1, [sp, #40] ; 0x28
  13662. 800a538: 9b0b ldr r3, [sp, #44] ; 0x2c
  13663. 800a53a: f1a3 7550 sub.w r5, r3, #54525952 ; 0x3400000
  13664. 800a53e: 950b str r5, [sp, #44] ; 0x2c
  13665. 800a540: 2e00 cmp r6, #0
  13666. 800a542: d15c bne.n 800a5fe <_dtoa_r+0x4ce>
  13667. 800a544: e9dd 0102 ldrd r0, r1, [sp, #8]
  13668. 800a548: 2200 movs r2, #0
  13669. 800a54a: 4b81 ldr r3, [pc, #516] ; (800a750 <_dtoa_r+0x620>)
  13670. 800a54c: f7f9 fe84 bl 8004258 <__aeabi_dsub>
  13671. 800a550: 9a0a ldr r2, [sp, #40] ; 0x28
  13672. 800a552: 462b mov r3, r5
  13673. 800a554: e9cd 0102 strd r0, r1, [sp, #8]
  13674. 800a558: f7fa fac2 bl 8004ae0 <__aeabi_dcmpgt>
  13675. 800a55c: 2800 cmp r0, #0
  13676. 800a55e: f040 82f7 bne.w 800ab50 <_dtoa_r+0xa20>
  13677. 800a562: e9dd 0102 ldrd r0, r1, [sp, #8]
  13678. 800a566: 9a0a ldr r2, [sp, #40] ; 0x28
  13679. 800a568: f105 4300 add.w r3, r5, #2147483648 ; 0x80000000
  13680. 800a56c: f7fa fa9a bl 8004aa4 <__aeabi_dcmplt>
  13681. 800a570: 2800 cmp r0, #0
  13682. 800a572: f040 82eb bne.w 800ab4c <_dtoa_r+0xa1c>
  13683. 800a576: e9dd 230e ldrd r2, r3, [sp, #56] ; 0x38
  13684. 800a57a: e9cd 2302 strd r2, r3, [sp, #8]
  13685. 800a57e: 9b13 ldr r3, [sp, #76] ; 0x4c
  13686. 800a580: 2b00 cmp r3, #0
  13687. 800a582: f2c0 8150 blt.w 800a826 <_dtoa_r+0x6f6>
  13688. 800a586: f1bb 0f0e cmp.w fp, #14
  13689. 800a58a: f300 814c bgt.w 800a826 <_dtoa_r+0x6f6>
  13690. 800a58e: 4b6b ldr r3, [pc, #428] ; (800a73c <_dtoa_r+0x60c>)
  13691. 800a590: eb03 03cb add.w r3, r3, fp, lsl #3
  13692. 800a594: e9d3 2300 ldrd r2, r3, [r3]
  13693. 800a598: e9cd 2304 strd r2, r3, [sp, #16]
  13694. 800a59c: 9b1f ldr r3, [sp, #124] ; 0x7c
  13695. 800a59e: 2b00 cmp r3, #0
  13696. 800a5a0: f280 80da bge.w 800a758 <_dtoa_r+0x628>
  13697. 800a5a4: f1b9 0f00 cmp.w r9, #0
  13698. 800a5a8: f300 80d6 bgt.w 800a758 <_dtoa_r+0x628>
  13699. 800a5ac: f040 82cd bne.w 800ab4a <_dtoa_r+0xa1a>
  13700. 800a5b0: e9dd 0104 ldrd r0, r1, [sp, #16]
  13701. 800a5b4: 2200 movs r2, #0
  13702. 800a5b6: 4b66 ldr r3, [pc, #408] ; (800a750 <_dtoa_r+0x620>)
  13703. 800a5b8: f7fa f802 bl 80045c0 <__aeabi_dmul>
  13704. 800a5bc: e9dd 2302 ldrd r2, r3, [sp, #8]
  13705. 800a5c0: f7fa fa84 bl 8004acc <__aeabi_dcmpge>
  13706. 800a5c4: 464e mov r6, r9
  13707. 800a5c6: 464f mov r7, r9
  13708. 800a5c8: 2800 cmp r0, #0
  13709. 800a5ca: f040 82a4 bne.w 800ab16 <_dtoa_r+0x9e6>
  13710. 800a5ce: 9b06 ldr r3, [sp, #24]
  13711. 800a5d0: 9a06 ldr r2, [sp, #24]
  13712. 800a5d2: 1c5d adds r5, r3, #1
  13713. 800a5d4: 2331 movs r3, #49 ; 0x31
  13714. 800a5d6: f10b 0b01 add.w fp, fp, #1
  13715. 800a5da: 7013 strb r3, [r2, #0]
  13716. 800a5dc: e29f b.n 800ab1e <_dtoa_r+0x9ee>
  13717. 800a5de: 07f2 lsls r2, r6, #31
  13718. 800a5e0: d505 bpl.n 800a5ee <_dtoa_r+0x4be>
  13719. 800a5e2: e9d7 2300 ldrd r2, r3, [r7]
  13720. 800a5e6: f7f9 ffeb bl 80045c0 <__aeabi_dmul>
  13721. 800a5ea: 2301 movs r3, #1
  13722. 800a5ec: 3501 adds r5, #1
  13723. 800a5ee: 1076 asrs r6, r6, #1
  13724. 800a5f0: 3708 adds r7, #8
  13725. 800a5f2: e76d b.n 800a4d0 <_dtoa_r+0x3a0>
  13726. 800a5f4: 2502 movs r5, #2
  13727. 800a5f6: e770 b.n 800a4da <_dtoa_r+0x3aa>
  13728. 800a5f8: 465f mov r7, fp
  13729. 800a5fa: 464e mov r6, r9
  13730. 800a5fc: e78f b.n 800a51e <_dtoa_r+0x3ee>
  13731. 800a5fe: 9a06 ldr r2, [sp, #24]
  13732. 800a600: 4b4e ldr r3, [pc, #312] ; (800a73c <_dtoa_r+0x60c>)
  13733. 800a602: 4432 add r2, r6
  13734. 800a604: 9211 str r2, [sp, #68] ; 0x44
  13735. 800a606: 9a09 ldr r2, [sp, #36] ; 0x24
  13736. 800a608: 1e71 subs r1, r6, #1
  13737. 800a60a: 2a00 cmp r2, #0
  13738. 800a60c: d048 beq.n 800a6a0 <_dtoa_r+0x570>
  13739. 800a60e: eb03 03c1 add.w r3, r3, r1, lsl #3
  13740. 800a612: e9d3 2300 ldrd r2, r3, [r3]
  13741. 800a616: 2000 movs r0, #0
  13742. 800a618: 494e ldr r1, [pc, #312] ; (800a754 <_dtoa_r+0x624>)
  13743. 800a61a: f7fa f8fb bl 8004814 <__aeabi_ddiv>
  13744. 800a61e: e9dd 230a ldrd r2, r3, [sp, #40] ; 0x28
  13745. 800a622: f7f9 fe19 bl 8004258 <__aeabi_dsub>
  13746. 800a626: e9cd 010a strd r0, r1, [sp, #40] ; 0x28
  13747. 800a62a: 9d06 ldr r5, [sp, #24]
  13748. 800a62c: e9dd 0102 ldrd r0, r1, [sp, #8]
  13749. 800a630: f7fa fa76 bl 8004b20 <__aeabi_d2iz>
  13750. 800a634: 4606 mov r6, r0
  13751. 800a636: f7f9 ff5d bl 80044f4 <__aeabi_i2d>
  13752. 800a63a: 4602 mov r2, r0
  13753. 800a63c: 460b mov r3, r1
  13754. 800a63e: e9dd 0102 ldrd r0, r1, [sp, #8]
  13755. 800a642: f7f9 fe09 bl 8004258 <__aeabi_dsub>
  13756. 800a646: e9dd 230a ldrd r2, r3, [sp, #40] ; 0x28
  13757. 800a64a: 3630 adds r6, #48 ; 0x30
  13758. 800a64c: f805 6b01 strb.w r6, [r5], #1
  13759. 800a650: e9cd 0102 strd r0, r1, [sp, #8]
  13760. 800a654: f7fa fa26 bl 8004aa4 <__aeabi_dcmplt>
  13761. 800a658: 2800 cmp r0, #0
  13762. 800a65a: d164 bne.n 800a726 <_dtoa_r+0x5f6>
  13763. 800a65c: e9dd 2302 ldrd r2, r3, [sp, #8]
  13764. 800a660: 2000 movs r0, #0
  13765. 800a662: 4938 ldr r1, [pc, #224] ; (800a744 <_dtoa_r+0x614>)
  13766. 800a664: f7f9 fdf8 bl 8004258 <__aeabi_dsub>
  13767. 800a668: e9dd 230a ldrd r2, r3, [sp, #40] ; 0x28
  13768. 800a66c: f7fa fa1a bl 8004aa4 <__aeabi_dcmplt>
  13769. 800a670: 2800 cmp r0, #0
  13770. 800a672: f040 80b9 bne.w 800a7e8 <_dtoa_r+0x6b8>
  13771. 800a676: 9b11 ldr r3, [sp, #68] ; 0x44
  13772. 800a678: 429d cmp r5, r3
  13773. 800a67a: f43f af7c beq.w 800a576 <_dtoa_r+0x446>
  13774. 800a67e: e9dd 010a ldrd r0, r1, [sp, #40] ; 0x28
  13775. 800a682: 2200 movs r2, #0
  13776. 800a684: 4b30 ldr r3, [pc, #192] ; (800a748 <_dtoa_r+0x618>)
  13777. 800a686: f7f9 ff9b bl 80045c0 <__aeabi_dmul>
  13778. 800a68a: 2200 movs r2, #0
  13779. 800a68c: e9cd 010a strd r0, r1, [sp, #40] ; 0x28
  13780. 800a690: e9dd 0102 ldrd r0, r1, [sp, #8]
  13781. 800a694: 4b2c ldr r3, [pc, #176] ; (800a748 <_dtoa_r+0x618>)
  13782. 800a696: f7f9 ff93 bl 80045c0 <__aeabi_dmul>
  13783. 800a69a: e9cd 0102 strd r0, r1, [sp, #8]
  13784. 800a69e: e7c5 b.n 800a62c <_dtoa_r+0x4fc>
  13785. 800a6a0: eb03 01c1 add.w r1, r3, r1, lsl #3
  13786. 800a6a4: e9d1 0100 ldrd r0, r1, [r1]
  13787. 800a6a8: e9dd 230a ldrd r2, r3, [sp, #40] ; 0x28
  13788. 800a6ac: f7f9 ff88 bl 80045c0 <__aeabi_dmul>
  13789. 800a6b0: e9cd 010a strd r0, r1, [sp, #40] ; 0x28
  13790. 800a6b4: 9d06 ldr r5, [sp, #24]
  13791. 800a6b6: e9dd 0102 ldrd r0, r1, [sp, #8]
  13792. 800a6ba: f7fa fa31 bl 8004b20 <__aeabi_d2iz>
  13793. 800a6be: 4606 mov r6, r0
  13794. 800a6c0: f7f9 ff18 bl 80044f4 <__aeabi_i2d>
  13795. 800a6c4: 4602 mov r2, r0
  13796. 800a6c6: 460b mov r3, r1
  13797. 800a6c8: e9dd 0102 ldrd r0, r1, [sp, #8]
  13798. 800a6cc: f7f9 fdc4 bl 8004258 <__aeabi_dsub>
  13799. 800a6d0: 3630 adds r6, #48 ; 0x30
  13800. 800a6d2: 9b11 ldr r3, [sp, #68] ; 0x44
  13801. 800a6d4: f805 6b01 strb.w r6, [r5], #1
  13802. 800a6d8: 42ab cmp r3, r5
  13803. 800a6da: e9cd 0102 strd r0, r1, [sp, #8]
  13804. 800a6de: f04f 0200 mov.w r2, #0
  13805. 800a6e2: d124 bne.n 800a72e <_dtoa_r+0x5fe>
  13806. 800a6e4: 4b1b ldr r3, [pc, #108] ; (800a754 <_dtoa_r+0x624>)
  13807. 800a6e6: e9dd 010a ldrd r0, r1, [sp, #40] ; 0x28
  13808. 800a6ea: f7f9 fdb7 bl 800425c <__adddf3>
  13809. 800a6ee: 4602 mov r2, r0
  13810. 800a6f0: 460b mov r3, r1
  13811. 800a6f2: e9dd 0102 ldrd r0, r1, [sp, #8]
  13812. 800a6f6: f7fa f9f3 bl 8004ae0 <__aeabi_dcmpgt>
  13813. 800a6fa: 2800 cmp r0, #0
  13814. 800a6fc: d174 bne.n 800a7e8 <_dtoa_r+0x6b8>
  13815. 800a6fe: e9dd 230a ldrd r2, r3, [sp, #40] ; 0x28
  13816. 800a702: 2000 movs r0, #0
  13817. 800a704: 4913 ldr r1, [pc, #76] ; (800a754 <_dtoa_r+0x624>)
  13818. 800a706: f7f9 fda7 bl 8004258 <__aeabi_dsub>
  13819. 800a70a: 4602 mov r2, r0
  13820. 800a70c: 460b mov r3, r1
  13821. 800a70e: e9dd 0102 ldrd r0, r1, [sp, #8]
  13822. 800a712: f7fa f9c7 bl 8004aa4 <__aeabi_dcmplt>
  13823. 800a716: 2800 cmp r0, #0
  13824. 800a718: f43f af2d beq.w 800a576 <_dtoa_r+0x446>
  13825. 800a71c: f815 3c01 ldrb.w r3, [r5, #-1]
  13826. 800a720: 1e6a subs r2, r5, #1
  13827. 800a722: 2b30 cmp r3, #48 ; 0x30
  13828. 800a724: d001 beq.n 800a72a <_dtoa_r+0x5fa>
  13829. 800a726: 46bb mov fp, r7
  13830. 800a728: e04d b.n 800a7c6 <_dtoa_r+0x696>
  13831. 800a72a: 4615 mov r5, r2
  13832. 800a72c: e7f6 b.n 800a71c <_dtoa_r+0x5ec>
  13833. 800a72e: 4b06 ldr r3, [pc, #24] ; (800a748 <_dtoa_r+0x618>)
  13834. 800a730: f7f9 ff46 bl 80045c0 <__aeabi_dmul>
  13835. 800a734: e9cd 0102 strd r0, r1, [sp, #8]
  13836. 800a738: e7bd b.n 800a6b6 <_dtoa_r+0x586>
  13837. 800a73a: bf00 nop
  13838. 800a73c: 0800bde8 .word 0x0800bde8
  13839. 800a740: 0800bdc0 .word 0x0800bdc0
  13840. 800a744: 3ff00000 .word 0x3ff00000
  13841. 800a748: 40240000 .word 0x40240000
  13842. 800a74c: 401c0000 .word 0x401c0000
  13843. 800a750: 40140000 .word 0x40140000
  13844. 800a754: 3fe00000 .word 0x3fe00000
  13845. 800a758: 9d06 ldr r5, [sp, #24]
  13846. 800a75a: e9dd 6702 ldrd r6, r7, [sp, #8]
  13847. 800a75e: e9dd 2304 ldrd r2, r3, [sp, #16]
  13848. 800a762: 4630 mov r0, r6
  13849. 800a764: 4639 mov r1, r7
  13850. 800a766: f7fa f855 bl 8004814 <__aeabi_ddiv>
  13851. 800a76a: f7fa f9d9 bl 8004b20 <__aeabi_d2iz>
  13852. 800a76e: 4680 mov r8, r0
  13853. 800a770: f7f9 fec0 bl 80044f4 <__aeabi_i2d>
  13854. 800a774: e9dd 2304 ldrd r2, r3, [sp, #16]
  13855. 800a778: f7f9 ff22 bl 80045c0 <__aeabi_dmul>
  13856. 800a77c: 4602 mov r2, r0
  13857. 800a77e: 460b mov r3, r1
  13858. 800a780: 4630 mov r0, r6
  13859. 800a782: 4639 mov r1, r7
  13860. 800a784: f7f9 fd68 bl 8004258 <__aeabi_dsub>
  13861. 800a788: f108 0630 add.w r6, r8, #48 ; 0x30
  13862. 800a78c: f805 6b01 strb.w r6, [r5], #1
  13863. 800a790: 9e06 ldr r6, [sp, #24]
  13864. 800a792: 4602 mov r2, r0
  13865. 800a794: 1bae subs r6, r5, r6
  13866. 800a796: 45b1 cmp r9, r6
  13867. 800a798: 460b mov r3, r1
  13868. 800a79a: d137 bne.n 800a80c <_dtoa_r+0x6dc>
  13869. 800a79c: f7f9 fd5e bl 800425c <__adddf3>
  13870. 800a7a0: 4606 mov r6, r0
  13871. 800a7a2: 460f mov r7, r1
  13872. 800a7a4: 4602 mov r2, r0
  13873. 800a7a6: 460b mov r3, r1
  13874. 800a7a8: e9dd 0104 ldrd r0, r1, [sp, #16]
  13875. 800a7ac: f7fa f97a bl 8004aa4 <__aeabi_dcmplt>
  13876. 800a7b0: b9c8 cbnz r0, 800a7e6 <_dtoa_r+0x6b6>
  13877. 800a7b2: e9dd 0104 ldrd r0, r1, [sp, #16]
  13878. 800a7b6: 4632 mov r2, r6
  13879. 800a7b8: 463b mov r3, r7
  13880. 800a7ba: f7fa f969 bl 8004a90 <__aeabi_dcmpeq>
  13881. 800a7be: b110 cbz r0, 800a7c6 <_dtoa_r+0x696>
  13882. 800a7c0: f018 0f01 tst.w r8, #1
  13883. 800a7c4: d10f bne.n 800a7e6 <_dtoa_r+0x6b6>
  13884. 800a7c6: 4651 mov r1, sl
  13885. 800a7c8: 4620 mov r0, r4
  13886. 800a7ca: f000 fcbd bl 800b148 <_Bfree>
  13887. 800a7ce: 2300 movs r3, #0
  13888. 800a7d0: 9a20 ldr r2, [sp, #128] ; 0x80
  13889. 800a7d2: 702b strb r3, [r5, #0]
  13890. 800a7d4: f10b 0301 add.w r3, fp, #1
  13891. 800a7d8: 6013 str r3, [r2, #0]
  13892. 800a7da: 9b22 ldr r3, [sp, #136] ; 0x88
  13893. 800a7dc: 2b00 cmp r3, #0
  13894. 800a7de: f43f acec beq.w 800a1ba <_dtoa_r+0x8a>
  13895. 800a7e2: 601d str r5, [r3, #0]
  13896. 800a7e4: e4e9 b.n 800a1ba <_dtoa_r+0x8a>
  13897. 800a7e6: 465f mov r7, fp
  13898. 800a7e8: f815 2c01 ldrb.w r2, [r5, #-1]
  13899. 800a7ec: 1e6b subs r3, r5, #1
  13900. 800a7ee: 2a39 cmp r2, #57 ; 0x39
  13901. 800a7f0: d106 bne.n 800a800 <_dtoa_r+0x6d0>
  13902. 800a7f2: 9a06 ldr r2, [sp, #24]
  13903. 800a7f4: 429a cmp r2, r3
  13904. 800a7f6: d107 bne.n 800a808 <_dtoa_r+0x6d8>
  13905. 800a7f8: 2330 movs r3, #48 ; 0x30
  13906. 800a7fa: 7013 strb r3, [r2, #0]
  13907. 800a7fc: 4613 mov r3, r2
  13908. 800a7fe: 3701 adds r7, #1
  13909. 800a800: 781a ldrb r2, [r3, #0]
  13910. 800a802: 3201 adds r2, #1
  13911. 800a804: 701a strb r2, [r3, #0]
  13912. 800a806: e78e b.n 800a726 <_dtoa_r+0x5f6>
  13913. 800a808: 461d mov r5, r3
  13914. 800a80a: e7ed b.n 800a7e8 <_dtoa_r+0x6b8>
  13915. 800a80c: 2200 movs r2, #0
  13916. 800a80e: 4bb5 ldr r3, [pc, #724] ; (800aae4 <_dtoa_r+0x9b4>)
  13917. 800a810: f7f9 fed6 bl 80045c0 <__aeabi_dmul>
  13918. 800a814: 2200 movs r2, #0
  13919. 800a816: 2300 movs r3, #0
  13920. 800a818: 4606 mov r6, r0
  13921. 800a81a: 460f mov r7, r1
  13922. 800a81c: f7fa f938 bl 8004a90 <__aeabi_dcmpeq>
  13923. 800a820: 2800 cmp r0, #0
  13924. 800a822: d09c beq.n 800a75e <_dtoa_r+0x62e>
  13925. 800a824: e7cf b.n 800a7c6 <_dtoa_r+0x696>
  13926. 800a826: 9a09 ldr r2, [sp, #36] ; 0x24
  13927. 800a828: 2a00 cmp r2, #0
  13928. 800a82a: f000 8129 beq.w 800aa80 <_dtoa_r+0x950>
  13929. 800a82e: 9a1e ldr r2, [sp, #120] ; 0x78
  13930. 800a830: 2a01 cmp r2, #1
  13931. 800a832: f300 810e bgt.w 800aa52 <_dtoa_r+0x922>
  13932. 800a836: 9a10 ldr r2, [sp, #64] ; 0x40
  13933. 800a838: 2a00 cmp r2, #0
  13934. 800a83a: f000 8106 beq.w 800aa4a <_dtoa_r+0x91a>
  13935. 800a83e: f203 4333 addw r3, r3, #1075 ; 0x433
  13936. 800a842: 4645 mov r5, r8
  13937. 800a844: 9e08 ldr r6, [sp, #32]
  13938. 800a846: 9a07 ldr r2, [sp, #28]
  13939. 800a848: 2101 movs r1, #1
  13940. 800a84a: 441a add r2, r3
  13941. 800a84c: 4620 mov r0, r4
  13942. 800a84e: 4498 add r8, r3
  13943. 800a850: 9207 str r2, [sp, #28]
  13944. 800a852: f000 fd19 bl 800b288 <__i2b>
  13945. 800a856: 4607 mov r7, r0
  13946. 800a858: 2d00 cmp r5, #0
  13947. 800a85a: dd0b ble.n 800a874 <_dtoa_r+0x744>
  13948. 800a85c: 9b07 ldr r3, [sp, #28]
  13949. 800a85e: 2b00 cmp r3, #0
  13950. 800a860: dd08 ble.n 800a874 <_dtoa_r+0x744>
  13951. 800a862: 42ab cmp r3, r5
  13952. 800a864: bfa8 it ge
  13953. 800a866: 462b movge r3, r5
  13954. 800a868: 9a07 ldr r2, [sp, #28]
  13955. 800a86a: eba8 0803 sub.w r8, r8, r3
  13956. 800a86e: 1aed subs r5, r5, r3
  13957. 800a870: 1ad3 subs r3, r2, r3
  13958. 800a872: 9307 str r3, [sp, #28]
  13959. 800a874: 9b08 ldr r3, [sp, #32]
  13960. 800a876: b1fb cbz r3, 800a8b8 <_dtoa_r+0x788>
  13961. 800a878: 9b09 ldr r3, [sp, #36] ; 0x24
  13962. 800a87a: 2b00 cmp r3, #0
  13963. 800a87c: f000 8104 beq.w 800aa88 <_dtoa_r+0x958>
  13964. 800a880: 2e00 cmp r6, #0
  13965. 800a882: dd11 ble.n 800a8a8 <_dtoa_r+0x778>
  13966. 800a884: 4639 mov r1, r7
  13967. 800a886: 4632 mov r2, r6
  13968. 800a888: 4620 mov r0, r4
  13969. 800a88a: f000 fd93 bl 800b3b4 <__pow5mult>
  13970. 800a88e: 4652 mov r2, sl
  13971. 800a890: 4601 mov r1, r0
  13972. 800a892: 4607 mov r7, r0
  13973. 800a894: 4620 mov r0, r4
  13974. 800a896: f000 fd00 bl 800b29a <__multiply>
  13975. 800a89a: 4651 mov r1, sl
  13976. 800a89c: 900a str r0, [sp, #40] ; 0x28
  13977. 800a89e: 4620 mov r0, r4
  13978. 800a8a0: f000 fc52 bl 800b148 <_Bfree>
  13979. 800a8a4: 9b0a ldr r3, [sp, #40] ; 0x28
  13980. 800a8a6: 469a mov sl, r3
  13981. 800a8a8: 9b08 ldr r3, [sp, #32]
  13982. 800a8aa: 1b9a subs r2, r3, r6
  13983. 800a8ac: d004 beq.n 800a8b8 <_dtoa_r+0x788>
  13984. 800a8ae: 4651 mov r1, sl
  13985. 800a8b0: 4620 mov r0, r4
  13986. 800a8b2: f000 fd7f bl 800b3b4 <__pow5mult>
  13987. 800a8b6: 4682 mov sl, r0
  13988. 800a8b8: 2101 movs r1, #1
  13989. 800a8ba: 4620 mov r0, r4
  13990. 800a8bc: f000 fce4 bl 800b288 <__i2b>
  13991. 800a8c0: 9b0c ldr r3, [sp, #48] ; 0x30
  13992. 800a8c2: 4606 mov r6, r0
  13993. 800a8c4: 2b00 cmp r3, #0
  13994. 800a8c6: f340 80e1 ble.w 800aa8c <_dtoa_r+0x95c>
  13995. 800a8ca: 461a mov r2, r3
  13996. 800a8cc: 4601 mov r1, r0
  13997. 800a8ce: 4620 mov r0, r4
  13998. 800a8d0: f000 fd70 bl 800b3b4 <__pow5mult>
  13999. 800a8d4: 9b1e ldr r3, [sp, #120] ; 0x78
  14000. 800a8d6: 4606 mov r6, r0
  14001. 800a8d8: 2b01 cmp r3, #1
  14002. 800a8da: f340 80da ble.w 800aa92 <_dtoa_r+0x962>
  14003. 800a8de: 2300 movs r3, #0
  14004. 800a8e0: 9308 str r3, [sp, #32]
  14005. 800a8e2: 6933 ldr r3, [r6, #16]
  14006. 800a8e4: eb06 0383 add.w r3, r6, r3, lsl #2
  14007. 800a8e8: 6918 ldr r0, [r3, #16]
  14008. 800a8ea: f000 fc7f bl 800b1ec <__hi0bits>
  14009. 800a8ee: f1c0 0020 rsb r0, r0, #32
  14010. 800a8f2: 9b07 ldr r3, [sp, #28]
  14011. 800a8f4: 4418 add r0, r3
  14012. 800a8f6: f010 001f ands.w r0, r0, #31
  14013. 800a8fa: f000 80f0 beq.w 800aade <_dtoa_r+0x9ae>
  14014. 800a8fe: f1c0 0320 rsb r3, r0, #32
  14015. 800a902: 2b04 cmp r3, #4
  14016. 800a904: f340 80e2 ble.w 800aacc <_dtoa_r+0x99c>
  14017. 800a908: 9b07 ldr r3, [sp, #28]
  14018. 800a90a: f1c0 001c rsb r0, r0, #28
  14019. 800a90e: 4480 add r8, r0
  14020. 800a910: 4405 add r5, r0
  14021. 800a912: 4403 add r3, r0
  14022. 800a914: 9307 str r3, [sp, #28]
  14023. 800a916: f1b8 0f00 cmp.w r8, #0
  14024. 800a91a: dd05 ble.n 800a928 <_dtoa_r+0x7f8>
  14025. 800a91c: 4651 mov r1, sl
  14026. 800a91e: 4642 mov r2, r8
  14027. 800a920: 4620 mov r0, r4
  14028. 800a922: f000 fd95 bl 800b450 <__lshift>
  14029. 800a926: 4682 mov sl, r0
  14030. 800a928: 9b07 ldr r3, [sp, #28]
  14031. 800a92a: 2b00 cmp r3, #0
  14032. 800a92c: dd05 ble.n 800a93a <_dtoa_r+0x80a>
  14033. 800a92e: 4631 mov r1, r6
  14034. 800a930: 461a mov r2, r3
  14035. 800a932: 4620 mov r0, r4
  14036. 800a934: f000 fd8c bl 800b450 <__lshift>
  14037. 800a938: 4606 mov r6, r0
  14038. 800a93a: 9b0d ldr r3, [sp, #52] ; 0x34
  14039. 800a93c: 2b00 cmp r3, #0
  14040. 800a93e: f000 80d3 beq.w 800aae8 <_dtoa_r+0x9b8>
  14041. 800a942: 4631 mov r1, r6
  14042. 800a944: 4650 mov r0, sl
  14043. 800a946: f000 fdd4 bl 800b4f2 <__mcmp>
  14044. 800a94a: 2800 cmp r0, #0
  14045. 800a94c: f280 80cc bge.w 800aae8 <_dtoa_r+0x9b8>
  14046. 800a950: 2300 movs r3, #0
  14047. 800a952: 4651 mov r1, sl
  14048. 800a954: 220a movs r2, #10
  14049. 800a956: 4620 mov r0, r4
  14050. 800a958: f000 fc0d bl 800b176 <__multadd>
  14051. 800a95c: 9b09 ldr r3, [sp, #36] ; 0x24
  14052. 800a95e: f10b 3bff add.w fp, fp, #4294967295
  14053. 800a962: 4682 mov sl, r0
  14054. 800a964: 2b00 cmp r3, #0
  14055. 800a966: f000 81a9 beq.w 800acbc <_dtoa_r+0xb8c>
  14056. 800a96a: 2300 movs r3, #0
  14057. 800a96c: 4639 mov r1, r7
  14058. 800a96e: 220a movs r2, #10
  14059. 800a970: 4620 mov r0, r4
  14060. 800a972: f000 fc00 bl 800b176 <__multadd>
  14061. 800a976: 9b04 ldr r3, [sp, #16]
  14062. 800a978: 4607 mov r7, r0
  14063. 800a97a: 2b00 cmp r3, #0
  14064. 800a97c: dc03 bgt.n 800a986 <_dtoa_r+0x856>
  14065. 800a97e: 9b1e ldr r3, [sp, #120] ; 0x78
  14066. 800a980: 2b02 cmp r3, #2
  14067. 800a982: f300 80b9 bgt.w 800aaf8 <_dtoa_r+0x9c8>
  14068. 800a986: 2d00 cmp r5, #0
  14069. 800a988: dd05 ble.n 800a996 <_dtoa_r+0x866>
  14070. 800a98a: 4639 mov r1, r7
  14071. 800a98c: 462a mov r2, r5
  14072. 800a98e: 4620 mov r0, r4
  14073. 800a990: f000 fd5e bl 800b450 <__lshift>
  14074. 800a994: 4607 mov r7, r0
  14075. 800a996: 9b08 ldr r3, [sp, #32]
  14076. 800a998: 2b00 cmp r3, #0
  14077. 800a99a: f000 8110 beq.w 800abbe <_dtoa_r+0xa8e>
  14078. 800a99e: 6879 ldr r1, [r7, #4]
  14079. 800a9a0: 4620 mov r0, r4
  14080. 800a9a2: f000 fb9d bl 800b0e0 <_Balloc>
  14081. 800a9a6: 4605 mov r5, r0
  14082. 800a9a8: 693a ldr r2, [r7, #16]
  14083. 800a9aa: f107 010c add.w r1, r7, #12
  14084. 800a9ae: 3202 adds r2, #2
  14085. 800a9b0: 0092 lsls r2, r2, #2
  14086. 800a9b2: 300c adds r0, #12
  14087. 800a9b4: f7fe fcca bl 800934c <memcpy>
  14088. 800a9b8: 2201 movs r2, #1
  14089. 800a9ba: 4629 mov r1, r5
  14090. 800a9bc: 4620 mov r0, r4
  14091. 800a9be: f000 fd47 bl 800b450 <__lshift>
  14092. 800a9c2: 9707 str r7, [sp, #28]
  14093. 800a9c4: 4607 mov r7, r0
  14094. 800a9c6: 9b02 ldr r3, [sp, #8]
  14095. 800a9c8: f8dd 8018 ldr.w r8, [sp, #24]
  14096. 800a9cc: f003 0301 and.w r3, r3, #1
  14097. 800a9d0: 9308 str r3, [sp, #32]
  14098. 800a9d2: 4631 mov r1, r6
  14099. 800a9d4: 4650 mov r0, sl
  14100. 800a9d6: f7ff fb1f bl 800a018 <quorem>
  14101. 800a9da: 9907 ldr r1, [sp, #28]
  14102. 800a9dc: 4605 mov r5, r0
  14103. 800a9de: f100 0930 add.w r9, r0, #48 ; 0x30
  14104. 800a9e2: 4650 mov r0, sl
  14105. 800a9e4: f000 fd85 bl 800b4f2 <__mcmp>
  14106. 800a9e8: 463a mov r2, r7
  14107. 800a9ea: 9002 str r0, [sp, #8]
  14108. 800a9ec: 4631 mov r1, r6
  14109. 800a9ee: 4620 mov r0, r4
  14110. 800a9f0: f000 fd99 bl 800b526 <__mdiff>
  14111. 800a9f4: 68c3 ldr r3, [r0, #12]
  14112. 800a9f6: 4602 mov r2, r0
  14113. 800a9f8: 2b00 cmp r3, #0
  14114. 800a9fa: f040 80e2 bne.w 800abc2 <_dtoa_r+0xa92>
  14115. 800a9fe: 4601 mov r1, r0
  14116. 800aa00: 9009 str r0, [sp, #36] ; 0x24
  14117. 800aa02: 4650 mov r0, sl
  14118. 800aa04: f000 fd75 bl 800b4f2 <__mcmp>
  14119. 800aa08: 4603 mov r3, r0
  14120. 800aa0a: 9a09 ldr r2, [sp, #36] ; 0x24
  14121. 800aa0c: 4611 mov r1, r2
  14122. 800aa0e: 4620 mov r0, r4
  14123. 800aa10: 9309 str r3, [sp, #36] ; 0x24
  14124. 800aa12: f000 fb99 bl 800b148 <_Bfree>
  14125. 800aa16: 9b09 ldr r3, [sp, #36] ; 0x24
  14126. 800aa18: 2b00 cmp r3, #0
  14127. 800aa1a: f040 80d4 bne.w 800abc6 <_dtoa_r+0xa96>
  14128. 800aa1e: 9a1e ldr r2, [sp, #120] ; 0x78
  14129. 800aa20: 2a00 cmp r2, #0
  14130. 800aa22: f040 80d0 bne.w 800abc6 <_dtoa_r+0xa96>
  14131. 800aa26: 9a08 ldr r2, [sp, #32]
  14132. 800aa28: 2a00 cmp r2, #0
  14133. 800aa2a: f040 80cc bne.w 800abc6 <_dtoa_r+0xa96>
  14134. 800aa2e: f1b9 0f39 cmp.w r9, #57 ; 0x39
  14135. 800aa32: f000 80e8 beq.w 800ac06 <_dtoa_r+0xad6>
  14136. 800aa36: 9b02 ldr r3, [sp, #8]
  14137. 800aa38: 2b00 cmp r3, #0
  14138. 800aa3a: dd01 ble.n 800aa40 <_dtoa_r+0x910>
  14139. 800aa3c: f105 0931 add.w r9, r5, #49 ; 0x31
  14140. 800aa40: f108 0501 add.w r5, r8, #1
  14141. 800aa44: f888 9000 strb.w r9, [r8]
  14142. 800aa48: e06b b.n 800ab22 <_dtoa_r+0x9f2>
  14143. 800aa4a: 9b12 ldr r3, [sp, #72] ; 0x48
  14144. 800aa4c: f1c3 0336 rsb r3, r3, #54 ; 0x36
  14145. 800aa50: e6f7 b.n 800a842 <_dtoa_r+0x712>
  14146. 800aa52: 9b08 ldr r3, [sp, #32]
  14147. 800aa54: f109 36ff add.w r6, r9, #4294967295
  14148. 800aa58: 42b3 cmp r3, r6
  14149. 800aa5a: bfb7 itett lt
  14150. 800aa5c: 9b08 ldrlt r3, [sp, #32]
  14151. 800aa5e: 1b9e subge r6, r3, r6
  14152. 800aa60: 1af2 sublt r2, r6, r3
  14153. 800aa62: 9b0c ldrlt r3, [sp, #48] ; 0x30
  14154. 800aa64: bfbf itttt lt
  14155. 800aa66: 9608 strlt r6, [sp, #32]
  14156. 800aa68: 189b addlt r3, r3, r2
  14157. 800aa6a: 930c strlt r3, [sp, #48] ; 0x30
  14158. 800aa6c: 2600 movlt r6, #0
  14159. 800aa6e: f1b9 0f00 cmp.w r9, #0
  14160. 800aa72: bfb9 ittee lt
  14161. 800aa74: eba8 0509 sublt.w r5, r8, r9
  14162. 800aa78: 2300 movlt r3, #0
  14163. 800aa7a: 4645 movge r5, r8
  14164. 800aa7c: 464b movge r3, r9
  14165. 800aa7e: e6e2 b.n 800a846 <_dtoa_r+0x716>
  14166. 800aa80: 9e08 ldr r6, [sp, #32]
  14167. 800aa82: 4645 mov r5, r8
  14168. 800aa84: 9f09 ldr r7, [sp, #36] ; 0x24
  14169. 800aa86: e6e7 b.n 800a858 <_dtoa_r+0x728>
  14170. 800aa88: 9a08 ldr r2, [sp, #32]
  14171. 800aa8a: e710 b.n 800a8ae <_dtoa_r+0x77e>
  14172. 800aa8c: 9b1e ldr r3, [sp, #120] ; 0x78
  14173. 800aa8e: 2b01 cmp r3, #1
  14174. 800aa90: dc18 bgt.n 800aac4 <_dtoa_r+0x994>
  14175. 800aa92: 9b02 ldr r3, [sp, #8]
  14176. 800aa94: b9b3 cbnz r3, 800aac4 <_dtoa_r+0x994>
  14177. 800aa96: 9b03 ldr r3, [sp, #12]
  14178. 800aa98: f3c3 0313 ubfx r3, r3, #0, #20
  14179. 800aa9c: b9a3 cbnz r3, 800aac8 <_dtoa_r+0x998>
  14180. 800aa9e: 9b03 ldr r3, [sp, #12]
  14181. 800aaa0: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000
  14182. 800aaa4: 0d1b lsrs r3, r3, #20
  14183. 800aaa6: 051b lsls r3, r3, #20
  14184. 800aaa8: b12b cbz r3, 800aab6 <_dtoa_r+0x986>
  14185. 800aaaa: 9b07 ldr r3, [sp, #28]
  14186. 800aaac: f108 0801 add.w r8, r8, #1
  14187. 800aab0: 3301 adds r3, #1
  14188. 800aab2: 9307 str r3, [sp, #28]
  14189. 800aab4: 2301 movs r3, #1
  14190. 800aab6: 9308 str r3, [sp, #32]
  14191. 800aab8: 9b0c ldr r3, [sp, #48] ; 0x30
  14192. 800aaba: 2b00 cmp r3, #0
  14193. 800aabc: f47f af11 bne.w 800a8e2 <_dtoa_r+0x7b2>
  14194. 800aac0: 2001 movs r0, #1
  14195. 800aac2: e716 b.n 800a8f2 <_dtoa_r+0x7c2>
  14196. 800aac4: 2300 movs r3, #0
  14197. 800aac6: e7f6 b.n 800aab6 <_dtoa_r+0x986>
  14198. 800aac8: 9b02 ldr r3, [sp, #8]
  14199. 800aaca: e7f4 b.n 800aab6 <_dtoa_r+0x986>
  14200. 800aacc: f43f af23 beq.w 800a916 <_dtoa_r+0x7e6>
  14201. 800aad0: 9a07 ldr r2, [sp, #28]
  14202. 800aad2: 331c adds r3, #28
  14203. 800aad4: 441a add r2, r3
  14204. 800aad6: 4498 add r8, r3
  14205. 800aad8: 441d add r5, r3
  14206. 800aada: 4613 mov r3, r2
  14207. 800aadc: e71a b.n 800a914 <_dtoa_r+0x7e4>
  14208. 800aade: 4603 mov r3, r0
  14209. 800aae0: e7f6 b.n 800aad0 <_dtoa_r+0x9a0>
  14210. 800aae2: bf00 nop
  14211. 800aae4: 40240000 .word 0x40240000
  14212. 800aae8: f1b9 0f00 cmp.w r9, #0
  14213. 800aaec: dc33 bgt.n 800ab56 <_dtoa_r+0xa26>
  14214. 800aaee: 9b1e ldr r3, [sp, #120] ; 0x78
  14215. 800aaf0: 2b02 cmp r3, #2
  14216. 800aaf2: dd30 ble.n 800ab56 <_dtoa_r+0xa26>
  14217. 800aaf4: f8cd 9010 str.w r9, [sp, #16]
  14218. 800aaf8: 9b04 ldr r3, [sp, #16]
  14219. 800aafa: b963 cbnz r3, 800ab16 <_dtoa_r+0x9e6>
  14220. 800aafc: 4631 mov r1, r6
  14221. 800aafe: 2205 movs r2, #5
  14222. 800ab00: 4620 mov r0, r4
  14223. 800ab02: f000 fb38 bl 800b176 <__multadd>
  14224. 800ab06: 4601 mov r1, r0
  14225. 800ab08: 4606 mov r6, r0
  14226. 800ab0a: 4650 mov r0, sl
  14227. 800ab0c: f000 fcf1 bl 800b4f2 <__mcmp>
  14228. 800ab10: 2800 cmp r0, #0
  14229. 800ab12: f73f ad5c bgt.w 800a5ce <_dtoa_r+0x49e>
  14230. 800ab16: 9b1f ldr r3, [sp, #124] ; 0x7c
  14231. 800ab18: 9d06 ldr r5, [sp, #24]
  14232. 800ab1a: ea6f 0b03 mvn.w fp, r3
  14233. 800ab1e: 2300 movs r3, #0
  14234. 800ab20: 9307 str r3, [sp, #28]
  14235. 800ab22: 4631 mov r1, r6
  14236. 800ab24: 4620 mov r0, r4
  14237. 800ab26: f000 fb0f bl 800b148 <_Bfree>
  14238. 800ab2a: 2f00 cmp r7, #0
  14239. 800ab2c: f43f ae4b beq.w 800a7c6 <_dtoa_r+0x696>
  14240. 800ab30: 9b07 ldr r3, [sp, #28]
  14241. 800ab32: b12b cbz r3, 800ab40 <_dtoa_r+0xa10>
  14242. 800ab34: 42bb cmp r3, r7
  14243. 800ab36: d003 beq.n 800ab40 <_dtoa_r+0xa10>
  14244. 800ab38: 4619 mov r1, r3
  14245. 800ab3a: 4620 mov r0, r4
  14246. 800ab3c: f000 fb04 bl 800b148 <_Bfree>
  14247. 800ab40: 4639 mov r1, r7
  14248. 800ab42: 4620 mov r0, r4
  14249. 800ab44: f000 fb00 bl 800b148 <_Bfree>
  14250. 800ab48: e63d b.n 800a7c6 <_dtoa_r+0x696>
  14251. 800ab4a: 2600 movs r6, #0
  14252. 800ab4c: 4637 mov r7, r6
  14253. 800ab4e: e7e2 b.n 800ab16 <_dtoa_r+0x9e6>
  14254. 800ab50: 46bb mov fp, r7
  14255. 800ab52: 4637 mov r7, r6
  14256. 800ab54: e53b b.n 800a5ce <_dtoa_r+0x49e>
  14257. 800ab56: 9b09 ldr r3, [sp, #36] ; 0x24
  14258. 800ab58: f8cd 9010 str.w r9, [sp, #16]
  14259. 800ab5c: 2b00 cmp r3, #0
  14260. 800ab5e: f47f af12 bne.w 800a986 <_dtoa_r+0x856>
  14261. 800ab62: 9d06 ldr r5, [sp, #24]
  14262. 800ab64: 4631 mov r1, r6
  14263. 800ab66: 4650 mov r0, sl
  14264. 800ab68: f7ff fa56 bl 800a018 <quorem>
  14265. 800ab6c: 9b06 ldr r3, [sp, #24]
  14266. 800ab6e: f100 0930 add.w r9, r0, #48 ; 0x30
  14267. 800ab72: f805 9b01 strb.w r9, [r5], #1
  14268. 800ab76: 9a04 ldr r2, [sp, #16]
  14269. 800ab78: 1aeb subs r3, r5, r3
  14270. 800ab7a: 429a cmp r2, r3
  14271. 800ab7c: f300 8081 bgt.w 800ac82 <_dtoa_r+0xb52>
  14272. 800ab80: 9b06 ldr r3, [sp, #24]
  14273. 800ab82: 2a01 cmp r2, #1
  14274. 800ab84: bfac ite ge
  14275. 800ab86: 189b addge r3, r3, r2
  14276. 800ab88: 3301 addlt r3, #1
  14277. 800ab8a: 4698 mov r8, r3
  14278. 800ab8c: 2300 movs r3, #0
  14279. 800ab8e: 9307 str r3, [sp, #28]
  14280. 800ab90: 4651 mov r1, sl
  14281. 800ab92: 2201 movs r2, #1
  14282. 800ab94: 4620 mov r0, r4
  14283. 800ab96: f000 fc5b bl 800b450 <__lshift>
  14284. 800ab9a: 4631 mov r1, r6
  14285. 800ab9c: 4682 mov sl, r0
  14286. 800ab9e: f000 fca8 bl 800b4f2 <__mcmp>
  14287. 800aba2: 2800 cmp r0, #0
  14288. 800aba4: dc34 bgt.n 800ac10 <_dtoa_r+0xae0>
  14289. 800aba6: d102 bne.n 800abae <_dtoa_r+0xa7e>
  14290. 800aba8: f019 0f01 tst.w r9, #1
  14291. 800abac: d130 bne.n 800ac10 <_dtoa_r+0xae0>
  14292. 800abae: 4645 mov r5, r8
  14293. 800abb0: f815 3c01 ldrb.w r3, [r5, #-1]
  14294. 800abb4: 1e6a subs r2, r5, #1
  14295. 800abb6: 2b30 cmp r3, #48 ; 0x30
  14296. 800abb8: d1b3 bne.n 800ab22 <_dtoa_r+0x9f2>
  14297. 800abba: 4615 mov r5, r2
  14298. 800abbc: e7f8 b.n 800abb0 <_dtoa_r+0xa80>
  14299. 800abbe: 4638 mov r0, r7
  14300. 800abc0: e6ff b.n 800a9c2 <_dtoa_r+0x892>
  14301. 800abc2: 2301 movs r3, #1
  14302. 800abc4: e722 b.n 800aa0c <_dtoa_r+0x8dc>
  14303. 800abc6: 9a02 ldr r2, [sp, #8]
  14304. 800abc8: 2a00 cmp r2, #0
  14305. 800abca: db04 blt.n 800abd6 <_dtoa_r+0xaa6>
  14306. 800abcc: d128 bne.n 800ac20 <_dtoa_r+0xaf0>
  14307. 800abce: 9a1e ldr r2, [sp, #120] ; 0x78
  14308. 800abd0: bb32 cbnz r2, 800ac20 <_dtoa_r+0xaf0>
  14309. 800abd2: 9a08 ldr r2, [sp, #32]
  14310. 800abd4: bb22 cbnz r2, 800ac20 <_dtoa_r+0xaf0>
  14311. 800abd6: 2b00 cmp r3, #0
  14312. 800abd8: f77f af32 ble.w 800aa40 <_dtoa_r+0x910>
  14313. 800abdc: 4651 mov r1, sl
  14314. 800abde: 2201 movs r2, #1
  14315. 800abe0: 4620 mov r0, r4
  14316. 800abe2: f000 fc35 bl 800b450 <__lshift>
  14317. 800abe6: 4631 mov r1, r6
  14318. 800abe8: 4682 mov sl, r0
  14319. 800abea: f000 fc82 bl 800b4f2 <__mcmp>
  14320. 800abee: 2800 cmp r0, #0
  14321. 800abf0: dc05 bgt.n 800abfe <_dtoa_r+0xace>
  14322. 800abf2: f47f af25 bne.w 800aa40 <_dtoa_r+0x910>
  14323. 800abf6: f019 0f01 tst.w r9, #1
  14324. 800abfa: f43f af21 beq.w 800aa40 <_dtoa_r+0x910>
  14325. 800abfe: f1b9 0f39 cmp.w r9, #57 ; 0x39
  14326. 800ac02: f47f af1b bne.w 800aa3c <_dtoa_r+0x90c>
  14327. 800ac06: 2339 movs r3, #57 ; 0x39
  14328. 800ac08: f108 0801 add.w r8, r8, #1
  14329. 800ac0c: f808 3c01 strb.w r3, [r8, #-1]
  14330. 800ac10: 4645 mov r5, r8
  14331. 800ac12: f815 3c01 ldrb.w r3, [r5, #-1]
  14332. 800ac16: 1e6a subs r2, r5, #1
  14333. 800ac18: 2b39 cmp r3, #57 ; 0x39
  14334. 800ac1a: d03a beq.n 800ac92 <_dtoa_r+0xb62>
  14335. 800ac1c: 3301 adds r3, #1
  14336. 800ac1e: e03f b.n 800aca0 <_dtoa_r+0xb70>
  14337. 800ac20: 2b00 cmp r3, #0
  14338. 800ac22: f108 0501 add.w r5, r8, #1
  14339. 800ac26: dd05 ble.n 800ac34 <_dtoa_r+0xb04>
  14340. 800ac28: f1b9 0f39 cmp.w r9, #57 ; 0x39
  14341. 800ac2c: d0eb beq.n 800ac06 <_dtoa_r+0xad6>
  14342. 800ac2e: f109 0901 add.w r9, r9, #1
  14343. 800ac32: e707 b.n 800aa44 <_dtoa_r+0x914>
  14344. 800ac34: 9b06 ldr r3, [sp, #24]
  14345. 800ac36: 9a04 ldr r2, [sp, #16]
  14346. 800ac38: 1aeb subs r3, r5, r3
  14347. 800ac3a: 4293 cmp r3, r2
  14348. 800ac3c: 46a8 mov r8, r5
  14349. 800ac3e: f805 9c01 strb.w r9, [r5, #-1]
  14350. 800ac42: d0a5 beq.n 800ab90 <_dtoa_r+0xa60>
  14351. 800ac44: 4651 mov r1, sl
  14352. 800ac46: 2300 movs r3, #0
  14353. 800ac48: 220a movs r2, #10
  14354. 800ac4a: 4620 mov r0, r4
  14355. 800ac4c: f000 fa93 bl 800b176 <__multadd>
  14356. 800ac50: 9b07 ldr r3, [sp, #28]
  14357. 800ac52: 4682 mov sl, r0
  14358. 800ac54: 42bb cmp r3, r7
  14359. 800ac56: f04f 020a mov.w r2, #10
  14360. 800ac5a: f04f 0300 mov.w r3, #0
  14361. 800ac5e: 9907 ldr r1, [sp, #28]
  14362. 800ac60: 4620 mov r0, r4
  14363. 800ac62: d104 bne.n 800ac6e <_dtoa_r+0xb3e>
  14364. 800ac64: f000 fa87 bl 800b176 <__multadd>
  14365. 800ac68: 9007 str r0, [sp, #28]
  14366. 800ac6a: 4607 mov r7, r0
  14367. 800ac6c: e6b1 b.n 800a9d2 <_dtoa_r+0x8a2>
  14368. 800ac6e: f000 fa82 bl 800b176 <__multadd>
  14369. 800ac72: 2300 movs r3, #0
  14370. 800ac74: 9007 str r0, [sp, #28]
  14371. 800ac76: 220a movs r2, #10
  14372. 800ac78: 4639 mov r1, r7
  14373. 800ac7a: 4620 mov r0, r4
  14374. 800ac7c: f000 fa7b bl 800b176 <__multadd>
  14375. 800ac80: e7f3 b.n 800ac6a <_dtoa_r+0xb3a>
  14376. 800ac82: 4651 mov r1, sl
  14377. 800ac84: 2300 movs r3, #0
  14378. 800ac86: 220a movs r2, #10
  14379. 800ac88: 4620 mov r0, r4
  14380. 800ac8a: f000 fa74 bl 800b176 <__multadd>
  14381. 800ac8e: 4682 mov sl, r0
  14382. 800ac90: e768 b.n 800ab64 <_dtoa_r+0xa34>
  14383. 800ac92: 9b06 ldr r3, [sp, #24]
  14384. 800ac94: 4293 cmp r3, r2
  14385. 800ac96: d105 bne.n 800aca4 <_dtoa_r+0xb74>
  14386. 800ac98: 2331 movs r3, #49 ; 0x31
  14387. 800ac9a: 9a06 ldr r2, [sp, #24]
  14388. 800ac9c: f10b 0b01 add.w fp, fp, #1
  14389. 800aca0: 7013 strb r3, [r2, #0]
  14390. 800aca2: e73e b.n 800ab22 <_dtoa_r+0x9f2>
  14391. 800aca4: 4615 mov r5, r2
  14392. 800aca6: e7b4 b.n 800ac12 <_dtoa_r+0xae2>
  14393. 800aca8: 4b09 ldr r3, [pc, #36] ; (800acd0 <_dtoa_r+0xba0>)
  14394. 800acaa: f7ff baa3 b.w 800a1f4 <_dtoa_r+0xc4>
  14395. 800acae: 9b22 ldr r3, [sp, #136] ; 0x88
  14396. 800acb0: 2b00 cmp r3, #0
  14397. 800acb2: f47f aa7d bne.w 800a1b0 <_dtoa_r+0x80>
  14398. 800acb6: 4b07 ldr r3, [pc, #28] ; (800acd4 <_dtoa_r+0xba4>)
  14399. 800acb8: f7ff ba9c b.w 800a1f4 <_dtoa_r+0xc4>
  14400. 800acbc: 9b04 ldr r3, [sp, #16]
  14401. 800acbe: 2b00 cmp r3, #0
  14402. 800acc0: f73f af4f bgt.w 800ab62 <_dtoa_r+0xa32>
  14403. 800acc4: 9b1e ldr r3, [sp, #120] ; 0x78
  14404. 800acc6: 2b02 cmp r3, #2
  14405. 800acc8: f77f af4b ble.w 800ab62 <_dtoa_r+0xa32>
  14406. 800accc: e714 b.n 800aaf8 <_dtoa_r+0x9c8>
  14407. 800acce: bf00 nop
  14408. 800acd0: 0800bd2c .word 0x0800bd2c
  14409. 800acd4: 0800bd50 .word 0x0800bd50
  14410. 0800acd8 <__sflush_r>:
  14411. 800acd8: 898a ldrh r2, [r1, #12]
  14412. 800acda: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
  14413. 800acde: 4605 mov r5, r0
  14414. 800ace0: 0710 lsls r0, r2, #28
  14415. 800ace2: 460c mov r4, r1
  14416. 800ace4: d45a bmi.n 800ad9c <__sflush_r+0xc4>
  14417. 800ace6: 684b ldr r3, [r1, #4]
  14418. 800ace8: 2b00 cmp r3, #0
  14419. 800acea: dc05 bgt.n 800acf8 <__sflush_r+0x20>
  14420. 800acec: 6c0b ldr r3, [r1, #64] ; 0x40
  14421. 800acee: 2b00 cmp r3, #0
  14422. 800acf0: dc02 bgt.n 800acf8 <__sflush_r+0x20>
  14423. 800acf2: 2000 movs r0, #0
  14424. 800acf4: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
  14425. 800acf8: 6ae6 ldr r6, [r4, #44] ; 0x2c
  14426. 800acfa: 2e00 cmp r6, #0
  14427. 800acfc: d0f9 beq.n 800acf2 <__sflush_r+0x1a>
  14428. 800acfe: 2300 movs r3, #0
  14429. 800ad00: f412 5280 ands.w r2, r2, #4096 ; 0x1000
  14430. 800ad04: 682f ldr r7, [r5, #0]
  14431. 800ad06: 602b str r3, [r5, #0]
  14432. 800ad08: d033 beq.n 800ad72 <__sflush_r+0x9a>
  14433. 800ad0a: 6d60 ldr r0, [r4, #84] ; 0x54
  14434. 800ad0c: 89a3 ldrh r3, [r4, #12]
  14435. 800ad0e: 075a lsls r2, r3, #29
  14436. 800ad10: d505 bpl.n 800ad1e <__sflush_r+0x46>
  14437. 800ad12: 6863 ldr r3, [r4, #4]
  14438. 800ad14: 1ac0 subs r0, r0, r3
  14439. 800ad16: 6b63 ldr r3, [r4, #52] ; 0x34
  14440. 800ad18: b10b cbz r3, 800ad1e <__sflush_r+0x46>
  14441. 800ad1a: 6c23 ldr r3, [r4, #64] ; 0x40
  14442. 800ad1c: 1ac0 subs r0, r0, r3
  14443. 800ad1e: 2300 movs r3, #0
  14444. 800ad20: 4602 mov r2, r0
  14445. 800ad22: 6ae6 ldr r6, [r4, #44] ; 0x2c
  14446. 800ad24: 6a21 ldr r1, [r4, #32]
  14447. 800ad26: 4628 mov r0, r5
  14448. 800ad28: 47b0 blx r6
  14449. 800ad2a: 1c43 adds r3, r0, #1
  14450. 800ad2c: 89a3 ldrh r3, [r4, #12]
  14451. 800ad2e: d106 bne.n 800ad3e <__sflush_r+0x66>
  14452. 800ad30: 6829 ldr r1, [r5, #0]
  14453. 800ad32: 291d cmp r1, #29
  14454. 800ad34: d84b bhi.n 800adce <__sflush_r+0xf6>
  14455. 800ad36: 4a2b ldr r2, [pc, #172] ; (800ade4 <__sflush_r+0x10c>)
  14456. 800ad38: 40ca lsrs r2, r1
  14457. 800ad3a: 07d6 lsls r6, r2, #31
  14458. 800ad3c: d547 bpl.n 800adce <__sflush_r+0xf6>
  14459. 800ad3e: 2200 movs r2, #0
  14460. 800ad40: 6062 str r2, [r4, #4]
  14461. 800ad42: 6922 ldr r2, [r4, #16]
  14462. 800ad44: 04d9 lsls r1, r3, #19
  14463. 800ad46: 6022 str r2, [r4, #0]
  14464. 800ad48: d504 bpl.n 800ad54 <__sflush_r+0x7c>
  14465. 800ad4a: 1c42 adds r2, r0, #1
  14466. 800ad4c: d101 bne.n 800ad52 <__sflush_r+0x7a>
  14467. 800ad4e: 682b ldr r3, [r5, #0]
  14468. 800ad50: b903 cbnz r3, 800ad54 <__sflush_r+0x7c>
  14469. 800ad52: 6560 str r0, [r4, #84] ; 0x54
  14470. 800ad54: 6b61 ldr r1, [r4, #52] ; 0x34
  14471. 800ad56: 602f str r7, [r5, #0]
  14472. 800ad58: 2900 cmp r1, #0
  14473. 800ad5a: d0ca beq.n 800acf2 <__sflush_r+0x1a>
  14474. 800ad5c: f104 0344 add.w r3, r4, #68 ; 0x44
  14475. 800ad60: 4299 cmp r1, r3
  14476. 800ad62: d002 beq.n 800ad6a <__sflush_r+0x92>
  14477. 800ad64: 4628 mov r0, r5
  14478. 800ad66: f000 fc9b bl 800b6a0 <_free_r>
  14479. 800ad6a: 2000 movs r0, #0
  14480. 800ad6c: 6360 str r0, [r4, #52] ; 0x34
  14481. 800ad6e: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
  14482. 800ad72: 6a21 ldr r1, [r4, #32]
  14483. 800ad74: 2301 movs r3, #1
  14484. 800ad76: 4628 mov r0, r5
  14485. 800ad78: 47b0 blx r6
  14486. 800ad7a: 1c41 adds r1, r0, #1
  14487. 800ad7c: d1c6 bne.n 800ad0c <__sflush_r+0x34>
  14488. 800ad7e: 682b ldr r3, [r5, #0]
  14489. 800ad80: 2b00 cmp r3, #0
  14490. 800ad82: d0c3 beq.n 800ad0c <__sflush_r+0x34>
  14491. 800ad84: 2b1d cmp r3, #29
  14492. 800ad86: d001 beq.n 800ad8c <__sflush_r+0xb4>
  14493. 800ad88: 2b16 cmp r3, #22
  14494. 800ad8a: d101 bne.n 800ad90 <__sflush_r+0xb8>
  14495. 800ad8c: 602f str r7, [r5, #0]
  14496. 800ad8e: e7b0 b.n 800acf2 <__sflush_r+0x1a>
  14497. 800ad90: 89a3 ldrh r3, [r4, #12]
  14498. 800ad92: f043 0340 orr.w r3, r3, #64 ; 0x40
  14499. 800ad96: 81a3 strh r3, [r4, #12]
  14500. 800ad98: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
  14501. 800ad9c: 690f ldr r7, [r1, #16]
  14502. 800ad9e: 2f00 cmp r7, #0
  14503. 800ada0: d0a7 beq.n 800acf2 <__sflush_r+0x1a>
  14504. 800ada2: 0793 lsls r3, r2, #30
  14505. 800ada4: bf18 it ne
  14506. 800ada6: 2300 movne r3, #0
  14507. 800ada8: 680e ldr r6, [r1, #0]
  14508. 800adaa: bf08 it eq
  14509. 800adac: 694b ldreq r3, [r1, #20]
  14510. 800adae: eba6 0807 sub.w r8, r6, r7
  14511. 800adb2: 600f str r7, [r1, #0]
  14512. 800adb4: 608b str r3, [r1, #8]
  14513. 800adb6: f1b8 0f00 cmp.w r8, #0
  14514. 800adba: dd9a ble.n 800acf2 <__sflush_r+0x1a>
  14515. 800adbc: 4643 mov r3, r8
  14516. 800adbe: 463a mov r2, r7
  14517. 800adc0: 6a21 ldr r1, [r4, #32]
  14518. 800adc2: 4628 mov r0, r5
  14519. 800adc4: 6aa6 ldr r6, [r4, #40] ; 0x28
  14520. 800adc6: 47b0 blx r6
  14521. 800adc8: 2800 cmp r0, #0
  14522. 800adca: dc07 bgt.n 800addc <__sflush_r+0x104>
  14523. 800adcc: 89a3 ldrh r3, [r4, #12]
  14524. 800adce: f043 0340 orr.w r3, r3, #64 ; 0x40
  14525. 800add2: 81a3 strh r3, [r4, #12]
  14526. 800add4: f04f 30ff mov.w r0, #4294967295
  14527. 800add8: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
  14528. 800addc: 4407 add r7, r0
  14529. 800adde: eba8 0800 sub.w r8, r8, r0
  14530. 800ade2: e7e8 b.n 800adb6 <__sflush_r+0xde>
  14531. 800ade4: 20400001 .word 0x20400001
  14532. 0800ade8 <_fflush_r>:
  14533. 800ade8: b538 push {r3, r4, r5, lr}
  14534. 800adea: 690b ldr r3, [r1, #16]
  14535. 800adec: 4605 mov r5, r0
  14536. 800adee: 460c mov r4, r1
  14537. 800adf0: b1db cbz r3, 800ae2a <_fflush_r+0x42>
  14538. 800adf2: b118 cbz r0, 800adfc <_fflush_r+0x14>
  14539. 800adf4: 6983 ldr r3, [r0, #24]
  14540. 800adf6: b90b cbnz r3, 800adfc <_fflush_r+0x14>
  14541. 800adf8: f000 f860 bl 800aebc <__sinit>
  14542. 800adfc: 4b0c ldr r3, [pc, #48] ; (800ae30 <_fflush_r+0x48>)
  14543. 800adfe: 429c cmp r4, r3
  14544. 800ae00: d109 bne.n 800ae16 <_fflush_r+0x2e>
  14545. 800ae02: 686c ldr r4, [r5, #4]
  14546. 800ae04: f9b4 300c ldrsh.w r3, [r4, #12]
  14547. 800ae08: b17b cbz r3, 800ae2a <_fflush_r+0x42>
  14548. 800ae0a: 4621 mov r1, r4
  14549. 800ae0c: 4628 mov r0, r5
  14550. 800ae0e: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
  14551. 800ae12: f7ff bf61 b.w 800acd8 <__sflush_r>
  14552. 800ae16: 4b07 ldr r3, [pc, #28] ; (800ae34 <_fflush_r+0x4c>)
  14553. 800ae18: 429c cmp r4, r3
  14554. 800ae1a: d101 bne.n 800ae20 <_fflush_r+0x38>
  14555. 800ae1c: 68ac ldr r4, [r5, #8]
  14556. 800ae1e: e7f1 b.n 800ae04 <_fflush_r+0x1c>
  14557. 800ae20: 4b05 ldr r3, [pc, #20] ; (800ae38 <_fflush_r+0x50>)
  14558. 800ae22: 429c cmp r4, r3
  14559. 800ae24: bf08 it eq
  14560. 800ae26: 68ec ldreq r4, [r5, #12]
  14561. 800ae28: e7ec b.n 800ae04 <_fflush_r+0x1c>
  14562. 800ae2a: 2000 movs r0, #0
  14563. 800ae2c: bd38 pop {r3, r4, r5, pc}
  14564. 800ae2e: bf00 nop
  14565. 800ae30: 0800bd80 .word 0x0800bd80
  14566. 800ae34: 0800bda0 .word 0x0800bda0
  14567. 800ae38: 0800bd60 .word 0x0800bd60
  14568. 0800ae3c <_cleanup_r>:
  14569. 800ae3c: 4901 ldr r1, [pc, #4] ; (800ae44 <_cleanup_r+0x8>)
  14570. 800ae3e: f000 b8a9 b.w 800af94 <_fwalk_reent>
  14571. 800ae42: bf00 nop
  14572. 800ae44: 0800ade9 .word 0x0800ade9
  14573. 0800ae48 <std.isra.0>:
  14574. 800ae48: 2300 movs r3, #0
  14575. 800ae4a: b510 push {r4, lr}
  14576. 800ae4c: 4604 mov r4, r0
  14577. 800ae4e: 6003 str r3, [r0, #0]
  14578. 800ae50: 6043 str r3, [r0, #4]
  14579. 800ae52: 6083 str r3, [r0, #8]
  14580. 800ae54: 8181 strh r1, [r0, #12]
  14581. 800ae56: 6643 str r3, [r0, #100] ; 0x64
  14582. 800ae58: 81c2 strh r2, [r0, #14]
  14583. 800ae5a: 6103 str r3, [r0, #16]
  14584. 800ae5c: 6143 str r3, [r0, #20]
  14585. 800ae5e: 6183 str r3, [r0, #24]
  14586. 800ae60: 4619 mov r1, r3
  14587. 800ae62: 2208 movs r2, #8
  14588. 800ae64: 305c adds r0, #92 ; 0x5c
  14589. 800ae66: f7fe fa7c bl 8009362 <memset>
  14590. 800ae6a: 4b05 ldr r3, [pc, #20] ; (800ae80 <std.isra.0+0x38>)
  14591. 800ae6c: 6224 str r4, [r4, #32]
  14592. 800ae6e: 6263 str r3, [r4, #36] ; 0x24
  14593. 800ae70: 4b04 ldr r3, [pc, #16] ; (800ae84 <std.isra.0+0x3c>)
  14594. 800ae72: 62a3 str r3, [r4, #40] ; 0x28
  14595. 800ae74: 4b04 ldr r3, [pc, #16] ; (800ae88 <std.isra.0+0x40>)
  14596. 800ae76: 62e3 str r3, [r4, #44] ; 0x2c
  14597. 800ae78: 4b04 ldr r3, [pc, #16] ; (800ae8c <std.isra.0+0x44>)
  14598. 800ae7a: 6323 str r3, [r4, #48] ; 0x30
  14599. 800ae7c: bd10 pop {r4, pc}
  14600. 800ae7e: bf00 nop
  14601. 800ae80: 0800ba91 .word 0x0800ba91
  14602. 800ae84: 0800bab3 .word 0x0800bab3
  14603. 800ae88: 0800baeb .word 0x0800baeb
  14604. 800ae8c: 0800bb0f .word 0x0800bb0f
  14605. 0800ae90 <__sfmoreglue>:
  14606. 800ae90: b570 push {r4, r5, r6, lr}
  14607. 800ae92: 2568 movs r5, #104 ; 0x68
  14608. 800ae94: 1e4a subs r2, r1, #1
  14609. 800ae96: 4355 muls r5, r2
  14610. 800ae98: 460e mov r6, r1
  14611. 800ae9a: f105 0174 add.w r1, r5, #116 ; 0x74
  14612. 800ae9e: f000 fc4b bl 800b738 <_malloc_r>
  14613. 800aea2: 4604 mov r4, r0
  14614. 800aea4: b140 cbz r0, 800aeb8 <__sfmoreglue+0x28>
  14615. 800aea6: 2100 movs r1, #0
  14616. 800aea8: e880 0042 stmia.w r0, {r1, r6}
  14617. 800aeac: 300c adds r0, #12
  14618. 800aeae: 60a0 str r0, [r4, #8]
  14619. 800aeb0: f105 0268 add.w r2, r5, #104 ; 0x68
  14620. 800aeb4: f7fe fa55 bl 8009362 <memset>
  14621. 800aeb8: 4620 mov r0, r4
  14622. 800aeba: bd70 pop {r4, r5, r6, pc}
  14623. 0800aebc <__sinit>:
  14624. 800aebc: 6983 ldr r3, [r0, #24]
  14625. 800aebe: b510 push {r4, lr}
  14626. 800aec0: 4604 mov r4, r0
  14627. 800aec2: bb33 cbnz r3, 800af12 <__sinit+0x56>
  14628. 800aec4: 6483 str r3, [r0, #72] ; 0x48
  14629. 800aec6: 64c3 str r3, [r0, #76] ; 0x4c
  14630. 800aec8: 6503 str r3, [r0, #80] ; 0x50
  14631. 800aeca: 4b12 ldr r3, [pc, #72] ; (800af14 <__sinit+0x58>)
  14632. 800aecc: 4a12 ldr r2, [pc, #72] ; (800af18 <__sinit+0x5c>)
  14633. 800aece: 681b ldr r3, [r3, #0]
  14634. 800aed0: 6282 str r2, [r0, #40] ; 0x28
  14635. 800aed2: 4298 cmp r0, r3
  14636. 800aed4: bf04 itt eq
  14637. 800aed6: 2301 moveq r3, #1
  14638. 800aed8: 6183 streq r3, [r0, #24]
  14639. 800aeda: f000 f81f bl 800af1c <__sfp>
  14640. 800aede: 6060 str r0, [r4, #4]
  14641. 800aee0: 4620 mov r0, r4
  14642. 800aee2: f000 f81b bl 800af1c <__sfp>
  14643. 800aee6: 60a0 str r0, [r4, #8]
  14644. 800aee8: 4620 mov r0, r4
  14645. 800aeea: f000 f817 bl 800af1c <__sfp>
  14646. 800aeee: 2200 movs r2, #0
  14647. 800aef0: 60e0 str r0, [r4, #12]
  14648. 800aef2: 2104 movs r1, #4
  14649. 800aef4: 6860 ldr r0, [r4, #4]
  14650. 800aef6: f7ff ffa7 bl 800ae48 <std.isra.0>
  14651. 800aefa: 2201 movs r2, #1
  14652. 800aefc: 2109 movs r1, #9
  14653. 800aefe: 68a0 ldr r0, [r4, #8]
  14654. 800af00: f7ff ffa2 bl 800ae48 <std.isra.0>
  14655. 800af04: 2202 movs r2, #2
  14656. 800af06: 2112 movs r1, #18
  14657. 800af08: 68e0 ldr r0, [r4, #12]
  14658. 800af0a: f7ff ff9d bl 800ae48 <std.isra.0>
  14659. 800af0e: 2301 movs r3, #1
  14660. 800af10: 61a3 str r3, [r4, #24]
  14661. 800af12: bd10 pop {r4, pc}
  14662. 800af14: 0800bd18 .word 0x0800bd18
  14663. 800af18: 0800ae3d .word 0x0800ae3d
  14664. 0800af1c <__sfp>:
  14665. 800af1c: b5f8 push {r3, r4, r5, r6, r7, lr}
  14666. 800af1e: 4b1c ldr r3, [pc, #112] ; (800af90 <__sfp+0x74>)
  14667. 800af20: 4607 mov r7, r0
  14668. 800af22: 681e ldr r6, [r3, #0]
  14669. 800af24: 69b3 ldr r3, [r6, #24]
  14670. 800af26: b913 cbnz r3, 800af2e <__sfp+0x12>
  14671. 800af28: 4630 mov r0, r6
  14672. 800af2a: f7ff ffc7 bl 800aebc <__sinit>
  14673. 800af2e: 3648 adds r6, #72 ; 0x48
  14674. 800af30: 68b4 ldr r4, [r6, #8]
  14675. 800af32: 6873 ldr r3, [r6, #4]
  14676. 800af34: 3b01 subs r3, #1
  14677. 800af36: d503 bpl.n 800af40 <__sfp+0x24>
  14678. 800af38: 6833 ldr r3, [r6, #0]
  14679. 800af3a: b133 cbz r3, 800af4a <__sfp+0x2e>
  14680. 800af3c: 6836 ldr r6, [r6, #0]
  14681. 800af3e: e7f7 b.n 800af30 <__sfp+0x14>
  14682. 800af40: f9b4 500c ldrsh.w r5, [r4, #12]
  14683. 800af44: b16d cbz r5, 800af62 <__sfp+0x46>
  14684. 800af46: 3468 adds r4, #104 ; 0x68
  14685. 800af48: e7f4 b.n 800af34 <__sfp+0x18>
  14686. 800af4a: 2104 movs r1, #4
  14687. 800af4c: 4638 mov r0, r7
  14688. 800af4e: f7ff ff9f bl 800ae90 <__sfmoreglue>
  14689. 800af52: 6030 str r0, [r6, #0]
  14690. 800af54: 2800 cmp r0, #0
  14691. 800af56: d1f1 bne.n 800af3c <__sfp+0x20>
  14692. 800af58: 230c movs r3, #12
  14693. 800af5a: 4604 mov r4, r0
  14694. 800af5c: 603b str r3, [r7, #0]
  14695. 800af5e: 4620 mov r0, r4
  14696. 800af60: bdf8 pop {r3, r4, r5, r6, r7, pc}
  14697. 800af62: f64f 73ff movw r3, #65535 ; 0xffff
  14698. 800af66: 81e3 strh r3, [r4, #14]
  14699. 800af68: 2301 movs r3, #1
  14700. 800af6a: 6665 str r5, [r4, #100] ; 0x64
  14701. 800af6c: 81a3 strh r3, [r4, #12]
  14702. 800af6e: 6025 str r5, [r4, #0]
  14703. 800af70: 60a5 str r5, [r4, #8]
  14704. 800af72: 6065 str r5, [r4, #4]
  14705. 800af74: 6125 str r5, [r4, #16]
  14706. 800af76: 6165 str r5, [r4, #20]
  14707. 800af78: 61a5 str r5, [r4, #24]
  14708. 800af7a: 2208 movs r2, #8
  14709. 800af7c: 4629 mov r1, r5
  14710. 800af7e: f104 005c add.w r0, r4, #92 ; 0x5c
  14711. 800af82: f7fe f9ee bl 8009362 <memset>
  14712. 800af86: 6365 str r5, [r4, #52] ; 0x34
  14713. 800af88: 63a5 str r5, [r4, #56] ; 0x38
  14714. 800af8a: 64a5 str r5, [r4, #72] ; 0x48
  14715. 800af8c: 64e5 str r5, [r4, #76] ; 0x4c
  14716. 800af8e: e7e6 b.n 800af5e <__sfp+0x42>
  14717. 800af90: 0800bd18 .word 0x0800bd18
  14718. 0800af94 <_fwalk_reent>:
  14719. 800af94: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
  14720. 800af98: 4680 mov r8, r0
  14721. 800af9a: 4689 mov r9, r1
  14722. 800af9c: 2600 movs r6, #0
  14723. 800af9e: f100 0448 add.w r4, r0, #72 ; 0x48
  14724. 800afa2: b914 cbnz r4, 800afaa <_fwalk_reent+0x16>
  14725. 800afa4: 4630 mov r0, r6
  14726. 800afa6: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
  14727. 800afaa: 68a5 ldr r5, [r4, #8]
  14728. 800afac: 6867 ldr r7, [r4, #4]
  14729. 800afae: 3f01 subs r7, #1
  14730. 800afb0: d501 bpl.n 800afb6 <_fwalk_reent+0x22>
  14731. 800afb2: 6824 ldr r4, [r4, #0]
  14732. 800afb4: e7f5 b.n 800afa2 <_fwalk_reent+0xe>
  14733. 800afb6: 89ab ldrh r3, [r5, #12]
  14734. 800afb8: 2b01 cmp r3, #1
  14735. 800afba: d907 bls.n 800afcc <_fwalk_reent+0x38>
  14736. 800afbc: f9b5 300e ldrsh.w r3, [r5, #14]
  14737. 800afc0: 3301 adds r3, #1
  14738. 800afc2: d003 beq.n 800afcc <_fwalk_reent+0x38>
  14739. 800afc4: 4629 mov r1, r5
  14740. 800afc6: 4640 mov r0, r8
  14741. 800afc8: 47c8 blx r9
  14742. 800afca: 4306 orrs r6, r0
  14743. 800afcc: 3568 adds r5, #104 ; 0x68
  14744. 800afce: e7ee b.n 800afae <_fwalk_reent+0x1a>
  14745. 0800afd0 <_localeconv_r>:
  14746. 800afd0: 4b04 ldr r3, [pc, #16] ; (800afe4 <_localeconv_r+0x14>)
  14747. 800afd2: 681b ldr r3, [r3, #0]
  14748. 800afd4: 6a18 ldr r0, [r3, #32]
  14749. 800afd6: 4b04 ldr r3, [pc, #16] ; (800afe8 <_localeconv_r+0x18>)
  14750. 800afd8: 2800 cmp r0, #0
  14751. 800afda: bf08 it eq
  14752. 800afdc: 4618 moveq r0, r3
  14753. 800afde: 30f0 adds r0, #240 ; 0xf0
  14754. 800afe0: 4770 bx lr
  14755. 800afe2: bf00 nop
  14756. 800afe4: 20000234 .word 0x20000234
  14757. 800afe8: 20000298 .word 0x20000298
  14758. 0800afec <__swhatbuf_r>:
  14759. 800afec: b570 push {r4, r5, r6, lr}
  14760. 800afee: 460e mov r6, r1
  14761. 800aff0: f9b1 100e ldrsh.w r1, [r1, #14]
  14762. 800aff4: b090 sub sp, #64 ; 0x40
  14763. 800aff6: 2900 cmp r1, #0
  14764. 800aff8: 4614 mov r4, r2
  14765. 800affa: 461d mov r5, r3
  14766. 800affc: da07 bge.n 800b00e <__swhatbuf_r+0x22>
  14767. 800affe: 2300 movs r3, #0
  14768. 800b000: 602b str r3, [r5, #0]
  14769. 800b002: 89b3 ldrh r3, [r6, #12]
  14770. 800b004: 061a lsls r2, r3, #24
  14771. 800b006: d410 bmi.n 800b02a <__swhatbuf_r+0x3e>
  14772. 800b008: f44f 6380 mov.w r3, #1024 ; 0x400
  14773. 800b00c: e00e b.n 800b02c <__swhatbuf_r+0x40>
  14774. 800b00e: aa01 add r2, sp, #4
  14775. 800b010: f000 fda4 bl 800bb5c <_fstat_r>
  14776. 800b014: 2800 cmp r0, #0
  14777. 800b016: dbf2 blt.n 800affe <__swhatbuf_r+0x12>
  14778. 800b018: 9a02 ldr r2, [sp, #8]
  14779. 800b01a: f402 4270 and.w r2, r2, #61440 ; 0xf000
  14780. 800b01e: f5a2 5300 sub.w r3, r2, #8192 ; 0x2000
  14781. 800b022: 425a negs r2, r3
  14782. 800b024: 415a adcs r2, r3
  14783. 800b026: 602a str r2, [r5, #0]
  14784. 800b028: e7ee b.n 800b008 <__swhatbuf_r+0x1c>
  14785. 800b02a: 2340 movs r3, #64 ; 0x40
  14786. 800b02c: 2000 movs r0, #0
  14787. 800b02e: 6023 str r3, [r4, #0]
  14788. 800b030: b010 add sp, #64 ; 0x40
  14789. 800b032: bd70 pop {r4, r5, r6, pc}
  14790. 0800b034 <__smakebuf_r>:
  14791. 800b034: 898b ldrh r3, [r1, #12]
  14792. 800b036: b573 push {r0, r1, r4, r5, r6, lr}
  14793. 800b038: 079d lsls r5, r3, #30
  14794. 800b03a: 4606 mov r6, r0
  14795. 800b03c: 460c mov r4, r1
  14796. 800b03e: d507 bpl.n 800b050 <__smakebuf_r+0x1c>
  14797. 800b040: f104 0347 add.w r3, r4, #71 ; 0x47
  14798. 800b044: 6023 str r3, [r4, #0]
  14799. 800b046: 6123 str r3, [r4, #16]
  14800. 800b048: 2301 movs r3, #1
  14801. 800b04a: 6163 str r3, [r4, #20]
  14802. 800b04c: b002 add sp, #8
  14803. 800b04e: bd70 pop {r4, r5, r6, pc}
  14804. 800b050: ab01 add r3, sp, #4
  14805. 800b052: 466a mov r2, sp
  14806. 800b054: f7ff ffca bl 800afec <__swhatbuf_r>
  14807. 800b058: 9900 ldr r1, [sp, #0]
  14808. 800b05a: 4605 mov r5, r0
  14809. 800b05c: 4630 mov r0, r6
  14810. 800b05e: f000 fb6b bl 800b738 <_malloc_r>
  14811. 800b062: b948 cbnz r0, 800b078 <__smakebuf_r+0x44>
  14812. 800b064: f9b4 300c ldrsh.w r3, [r4, #12]
  14813. 800b068: 059a lsls r2, r3, #22
  14814. 800b06a: d4ef bmi.n 800b04c <__smakebuf_r+0x18>
  14815. 800b06c: f023 0303 bic.w r3, r3, #3
  14816. 800b070: f043 0302 orr.w r3, r3, #2
  14817. 800b074: 81a3 strh r3, [r4, #12]
  14818. 800b076: e7e3 b.n 800b040 <__smakebuf_r+0xc>
  14819. 800b078: 4b0d ldr r3, [pc, #52] ; (800b0b0 <__smakebuf_r+0x7c>)
  14820. 800b07a: 62b3 str r3, [r6, #40] ; 0x28
  14821. 800b07c: 89a3 ldrh r3, [r4, #12]
  14822. 800b07e: 6020 str r0, [r4, #0]
  14823. 800b080: f043 0380 orr.w r3, r3, #128 ; 0x80
  14824. 800b084: 81a3 strh r3, [r4, #12]
  14825. 800b086: 9b00 ldr r3, [sp, #0]
  14826. 800b088: 6120 str r0, [r4, #16]
  14827. 800b08a: 6163 str r3, [r4, #20]
  14828. 800b08c: 9b01 ldr r3, [sp, #4]
  14829. 800b08e: b15b cbz r3, 800b0a8 <__smakebuf_r+0x74>
  14830. 800b090: f9b4 100e ldrsh.w r1, [r4, #14]
  14831. 800b094: 4630 mov r0, r6
  14832. 800b096: f000 fd73 bl 800bb80 <_isatty_r>
  14833. 800b09a: b128 cbz r0, 800b0a8 <__smakebuf_r+0x74>
  14834. 800b09c: 89a3 ldrh r3, [r4, #12]
  14835. 800b09e: f023 0303 bic.w r3, r3, #3
  14836. 800b0a2: f043 0301 orr.w r3, r3, #1
  14837. 800b0a6: 81a3 strh r3, [r4, #12]
  14838. 800b0a8: 89a3 ldrh r3, [r4, #12]
  14839. 800b0aa: 431d orrs r5, r3
  14840. 800b0ac: 81a5 strh r5, [r4, #12]
  14841. 800b0ae: e7cd b.n 800b04c <__smakebuf_r+0x18>
  14842. 800b0b0: 0800ae3d .word 0x0800ae3d
  14843. 0800b0b4 <malloc>:
  14844. 800b0b4: 4b02 ldr r3, [pc, #8] ; (800b0c0 <malloc+0xc>)
  14845. 800b0b6: 4601 mov r1, r0
  14846. 800b0b8: 6818 ldr r0, [r3, #0]
  14847. 800b0ba: f000 bb3d b.w 800b738 <_malloc_r>
  14848. 800b0be: bf00 nop
  14849. 800b0c0: 20000234 .word 0x20000234
  14850. 0800b0c4 <memchr>:
  14851. 800b0c4: b510 push {r4, lr}
  14852. 800b0c6: b2c9 uxtb r1, r1
  14853. 800b0c8: 4402 add r2, r0
  14854. 800b0ca: 4290 cmp r0, r2
  14855. 800b0cc: 4603 mov r3, r0
  14856. 800b0ce: d101 bne.n 800b0d4 <memchr+0x10>
  14857. 800b0d0: 2000 movs r0, #0
  14858. 800b0d2: bd10 pop {r4, pc}
  14859. 800b0d4: 781c ldrb r4, [r3, #0]
  14860. 800b0d6: 3001 adds r0, #1
  14861. 800b0d8: 428c cmp r4, r1
  14862. 800b0da: d1f6 bne.n 800b0ca <memchr+0x6>
  14863. 800b0dc: 4618 mov r0, r3
  14864. 800b0de: bd10 pop {r4, pc}
  14865. 0800b0e0 <_Balloc>:
  14866. 800b0e0: b570 push {r4, r5, r6, lr}
  14867. 800b0e2: 6a45 ldr r5, [r0, #36] ; 0x24
  14868. 800b0e4: 4604 mov r4, r0
  14869. 800b0e6: 460e mov r6, r1
  14870. 800b0e8: b93d cbnz r5, 800b0fa <_Balloc+0x1a>
  14871. 800b0ea: 2010 movs r0, #16
  14872. 800b0ec: f7ff ffe2 bl 800b0b4 <malloc>
  14873. 800b0f0: 6260 str r0, [r4, #36] ; 0x24
  14874. 800b0f2: 6045 str r5, [r0, #4]
  14875. 800b0f4: 6085 str r5, [r0, #8]
  14876. 800b0f6: 6005 str r5, [r0, #0]
  14877. 800b0f8: 60c5 str r5, [r0, #12]
  14878. 800b0fa: 6a65 ldr r5, [r4, #36] ; 0x24
  14879. 800b0fc: 68eb ldr r3, [r5, #12]
  14880. 800b0fe: b183 cbz r3, 800b122 <_Balloc+0x42>
  14881. 800b100: 6a63 ldr r3, [r4, #36] ; 0x24
  14882. 800b102: 68db ldr r3, [r3, #12]
  14883. 800b104: f853 0026 ldr.w r0, [r3, r6, lsl #2]
  14884. 800b108: b9b8 cbnz r0, 800b13a <_Balloc+0x5a>
  14885. 800b10a: 2101 movs r1, #1
  14886. 800b10c: fa01 f506 lsl.w r5, r1, r6
  14887. 800b110: 1d6a adds r2, r5, #5
  14888. 800b112: 0092 lsls r2, r2, #2
  14889. 800b114: 4620 mov r0, r4
  14890. 800b116: f000 fab4 bl 800b682 <_calloc_r>
  14891. 800b11a: b160 cbz r0, 800b136 <_Balloc+0x56>
  14892. 800b11c: 6046 str r6, [r0, #4]
  14893. 800b11e: 6085 str r5, [r0, #8]
  14894. 800b120: e00e b.n 800b140 <_Balloc+0x60>
  14895. 800b122: 2221 movs r2, #33 ; 0x21
  14896. 800b124: 2104 movs r1, #4
  14897. 800b126: 4620 mov r0, r4
  14898. 800b128: f000 faab bl 800b682 <_calloc_r>
  14899. 800b12c: 6a63 ldr r3, [r4, #36] ; 0x24
  14900. 800b12e: 60e8 str r0, [r5, #12]
  14901. 800b130: 68db ldr r3, [r3, #12]
  14902. 800b132: 2b00 cmp r3, #0
  14903. 800b134: d1e4 bne.n 800b100 <_Balloc+0x20>
  14904. 800b136: 2000 movs r0, #0
  14905. 800b138: bd70 pop {r4, r5, r6, pc}
  14906. 800b13a: 6802 ldr r2, [r0, #0]
  14907. 800b13c: f843 2026 str.w r2, [r3, r6, lsl #2]
  14908. 800b140: 2300 movs r3, #0
  14909. 800b142: 6103 str r3, [r0, #16]
  14910. 800b144: 60c3 str r3, [r0, #12]
  14911. 800b146: bd70 pop {r4, r5, r6, pc}
  14912. 0800b148 <_Bfree>:
  14913. 800b148: b570 push {r4, r5, r6, lr}
  14914. 800b14a: 6a44 ldr r4, [r0, #36] ; 0x24
  14915. 800b14c: 4606 mov r6, r0
  14916. 800b14e: 460d mov r5, r1
  14917. 800b150: b93c cbnz r4, 800b162 <_Bfree+0x1a>
  14918. 800b152: 2010 movs r0, #16
  14919. 800b154: f7ff ffae bl 800b0b4 <malloc>
  14920. 800b158: 6270 str r0, [r6, #36] ; 0x24
  14921. 800b15a: 6044 str r4, [r0, #4]
  14922. 800b15c: 6084 str r4, [r0, #8]
  14923. 800b15e: 6004 str r4, [r0, #0]
  14924. 800b160: 60c4 str r4, [r0, #12]
  14925. 800b162: b13d cbz r5, 800b174 <_Bfree+0x2c>
  14926. 800b164: 6a73 ldr r3, [r6, #36] ; 0x24
  14927. 800b166: 686a ldr r2, [r5, #4]
  14928. 800b168: 68db ldr r3, [r3, #12]
  14929. 800b16a: f853 1022 ldr.w r1, [r3, r2, lsl #2]
  14930. 800b16e: 6029 str r1, [r5, #0]
  14931. 800b170: f843 5022 str.w r5, [r3, r2, lsl #2]
  14932. 800b174: bd70 pop {r4, r5, r6, pc}
  14933. 0800b176 <__multadd>:
  14934. 800b176: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
  14935. 800b17a: 461f mov r7, r3
  14936. 800b17c: 4606 mov r6, r0
  14937. 800b17e: 460c mov r4, r1
  14938. 800b180: 2300 movs r3, #0
  14939. 800b182: 690d ldr r5, [r1, #16]
  14940. 800b184: f101 0e14 add.w lr, r1, #20
  14941. 800b188: f8de 0000 ldr.w r0, [lr]
  14942. 800b18c: 3301 adds r3, #1
  14943. 800b18e: b281 uxth r1, r0
  14944. 800b190: fb02 7101 mla r1, r2, r1, r7
  14945. 800b194: 0c00 lsrs r0, r0, #16
  14946. 800b196: 0c0f lsrs r7, r1, #16
  14947. 800b198: fb02 7000 mla r0, r2, r0, r7
  14948. 800b19c: b289 uxth r1, r1
  14949. 800b19e: eb01 4100 add.w r1, r1, r0, lsl #16
  14950. 800b1a2: 429d cmp r5, r3
  14951. 800b1a4: ea4f 4710 mov.w r7, r0, lsr #16
  14952. 800b1a8: f84e 1b04 str.w r1, [lr], #4
  14953. 800b1ac: dcec bgt.n 800b188 <__multadd+0x12>
  14954. 800b1ae: b1d7 cbz r7, 800b1e6 <__multadd+0x70>
  14955. 800b1b0: 68a3 ldr r3, [r4, #8]
  14956. 800b1b2: 429d cmp r5, r3
  14957. 800b1b4: db12 blt.n 800b1dc <__multadd+0x66>
  14958. 800b1b6: 6861 ldr r1, [r4, #4]
  14959. 800b1b8: 4630 mov r0, r6
  14960. 800b1ba: 3101 adds r1, #1
  14961. 800b1bc: f7ff ff90 bl 800b0e0 <_Balloc>
  14962. 800b1c0: 4680 mov r8, r0
  14963. 800b1c2: 6922 ldr r2, [r4, #16]
  14964. 800b1c4: f104 010c add.w r1, r4, #12
  14965. 800b1c8: 3202 adds r2, #2
  14966. 800b1ca: 0092 lsls r2, r2, #2
  14967. 800b1cc: 300c adds r0, #12
  14968. 800b1ce: f7fe f8bd bl 800934c <memcpy>
  14969. 800b1d2: 4621 mov r1, r4
  14970. 800b1d4: 4630 mov r0, r6
  14971. 800b1d6: f7ff ffb7 bl 800b148 <_Bfree>
  14972. 800b1da: 4644 mov r4, r8
  14973. 800b1dc: eb04 0385 add.w r3, r4, r5, lsl #2
  14974. 800b1e0: 3501 adds r5, #1
  14975. 800b1e2: 615f str r7, [r3, #20]
  14976. 800b1e4: 6125 str r5, [r4, #16]
  14977. 800b1e6: 4620 mov r0, r4
  14978. 800b1e8: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
  14979. 0800b1ec <__hi0bits>:
  14980. 800b1ec: 0c02 lsrs r2, r0, #16
  14981. 800b1ee: 0412 lsls r2, r2, #16
  14982. 800b1f0: 4603 mov r3, r0
  14983. 800b1f2: b9b2 cbnz r2, 800b222 <__hi0bits+0x36>
  14984. 800b1f4: 0403 lsls r3, r0, #16
  14985. 800b1f6: 2010 movs r0, #16
  14986. 800b1f8: f013 4f7f tst.w r3, #4278190080 ; 0xff000000
  14987. 800b1fc: bf04 itt eq
  14988. 800b1fe: 021b lsleq r3, r3, #8
  14989. 800b200: 3008 addeq r0, #8
  14990. 800b202: f013 4f70 tst.w r3, #4026531840 ; 0xf0000000
  14991. 800b206: bf04 itt eq
  14992. 800b208: 011b lsleq r3, r3, #4
  14993. 800b20a: 3004 addeq r0, #4
  14994. 800b20c: f013 4f40 tst.w r3, #3221225472 ; 0xc0000000
  14995. 800b210: bf04 itt eq
  14996. 800b212: 009b lsleq r3, r3, #2
  14997. 800b214: 3002 addeq r0, #2
  14998. 800b216: 2b00 cmp r3, #0
  14999. 800b218: db06 blt.n 800b228 <__hi0bits+0x3c>
  15000. 800b21a: 005b lsls r3, r3, #1
  15001. 800b21c: d503 bpl.n 800b226 <__hi0bits+0x3a>
  15002. 800b21e: 3001 adds r0, #1
  15003. 800b220: 4770 bx lr
  15004. 800b222: 2000 movs r0, #0
  15005. 800b224: e7e8 b.n 800b1f8 <__hi0bits+0xc>
  15006. 800b226: 2020 movs r0, #32
  15007. 800b228: 4770 bx lr
  15008. 0800b22a <__lo0bits>:
  15009. 800b22a: 6803 ldr r3, [r0, #0]
  15010. 800b22c: 4601 mov r1, r0
  15011. 800b22e: f013 0207 ands.w r2, r3, #7
  15012. 800b232: d00b beq.n 800b24c <__lo0bits+0x22>
  15013. 800b234: 07da lsls r2, r3, #31
  15014. 800b236: d423 bmi.n 800b280 <__lo0bits+0x56>
  15015. 800b238: 0798 lsls r0, r3, #30
  15016. 800b23a: bf49 itett mi
  15017. 800b23c: 085b lsrmi r3, r3, #1
  15018. 800b23e: 089b lsrpl r3, r3, #2
  15019. 800b240: 2001 movmi r0, #1
  15020. 800b242: 600b strmi r3, [r1, #0]
  15021. 800b244: bf5c itt pl
  15022. 800b246: 600b strpl r3, [r1, #0]
  15023. 800b248: 2002 movpl r0, #2
  15024. 800b24a: 4770 bx lr
  15025. 800b24c: b298 uxth r0, r3
  15026. 800b24e: b9a8 cbnz r0, 800b27c <__lo0bits+0x52>
  15027. 800b250: 2010 movs r0, #16
  15028. 800b252: 0c1b lsrs r3, r3, #16
  15029. 800b254: f013 0fff tst.w r3, #255 ; 0xff
  15030. 800b258: bf04 itt eq
  15031. 800b25a: 0a1b lsreq r3, r3, #8
  15032. 800b25c: 3008 addeq r0, #8
  15033. 800b25e: 071a lsls r2, r3, #28
  15034. 800b260: bf04 itt eq
  15035. 800b262: 091b lsreq r3, r3, #4
  15036. 800b264: 3004 addeq r0, #4
  15037. 800b266: 079a lsls r2, r3, #30
  15038. 800b268: bf04 itt eq
  15039. 800b26a: 089b lsreq r3, r3, #2
  15040. 800b26c: 3002 addeq r0, #2
  15041. 800b26e: 07da lsls r2, r3, #31
  15042. 800b270: d402 bmi.n 800b278 <__lo0bits+0x4e>
  15043. 800b272: 085b lsrs r3, r3, #1
  15044. 800b274: d006 beq.n 800b284 <__lo0bits+0x5a>
  15045. 800b276: 3001 adds r0, #1
  15046. 800b278: 600b str r3, [r1, #0]
  15047. 800b27a: 4770 bx lr
  15048. 800b27c: 4610 mov r0, r2
  15049. 800b27e: e7e9 b.n 800b254 <__lo0bits+0x2a>
  15050. 800b280: 2000 movs r0, #0
  15051. 800b282: 4770 bx lr
  15052. 800b284: 2020 movs r0, #32
  15053. 800b286: 4770 bx lr
  15054. 0800b288 <__i2b>:
  15055. 800b288: b510 push {r4, lr}
  15056. 800b28a: 460c mov r4, r1
  15057. 800b28c: 2101 movs r1, #1
  15058. 800b28e: f7ff ff27 bl 800b0e0 <_Balloc>
  15059. 800b292: 2201 movs r2, #1
  15060. 800b294: 6144 str r4, [r0, #20]
  15061. 800b296: 6102 str r2, [r0, #16]
  15062. 800b298: bd10 pop {r4, pc}
  15063. 0800b29a <__multiply>:
  15064. 800b29a: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
  15065. 800b29e: 4614 mov r4, r2
  15066. 800b2a0: 690a ldr r2, [r1, #16]
  15067. 800b2a2: 6923 ldr r3, [r4, #16]
  15068. 800b2a4: 4689 mov r9, r1
  15069. 800b2a6: 429a cmp r2, r3
  15070. 800b2a8: bfbe ittt lt
  15071. 800b2aa: 460b movlt r3, r1
  15072. 800b2ac: 46a1 movlt r9, r4
  15073. 800b2ae: 461c movlt r4, r3
  15074. 800b2b0: f8d9 7010 ldr.w r7, [r9, #16]
  15075. 800b2b4: f8d4 a010 ldr.w sl, [r4, #16]
  15076. 800b2b8: f8d9 3008 ldr.w r3, [r9, #8]
  15077. 800b2bc: f8d9 1004 ldr.w r1, [r9, #4]
  15078. 800b2c0: eb07 060a add.w r6, r7, sl
  15079. 800b2c4: 429e cmp r6, r3
  15080. 800b2c6: bfc8 it gt
  15081. 800b2c8: 3101 addgt r1, #1
  15082. 800b2ca: f7ff ff09 bl 800b0e0 <_Balloc>
  15083. 800b2ce: f100 0514 add.w r5, r0, #20
  15084. 800b2d2: 462b mov r3, r5
  15085. 800b2d4: 2200 movs r2, #0
  15086. 800b2d6: eb05 0886 add.w r8, r5, r6, lsl #2
  15087. 800b2da: 4543 cmp r3, r8
  15088. 800b2dc: d316 bcc.n 800b30c <__multiply+0x72>
  15089. 800b2de: f104 0214 add.w r2, r4, #20
  15090. 800b2e2: f109 0114 add.w r1, r9, #20
  15091. 800b2e6: eb02 038a add.w r3, r2, sl, lsl #2
  15092. 800b2ea: eb01 0787 add.w r7, r1, r7, lsl #2
  15093. 800b2ee: 9301 str r3, [sp, #4]
  15094. 800b2f0: 9c01 ldr r4, [sp, #4]
  15095. 800b2f2: 4613 mov r3, r2
  15096. 800b2f4: 4294 cmp r4, r2
  15097. 800b2f6: d80c bhi.n 800b312 <__multiply+0x78>
  15098. 800b2f8: 2e00 cmp r6, #0
  15099. 800b2fa: dd03 ble.n 800b304 <__multiply+0x6a>
  15100. 800b2fc: f858 3d04 ldr.w r3, [r8, #-4]!
  15101. 800b300: 2b00 cmp r3, #0
  15102. 800b302: d054 beq.n 800b3ae <__multiply+0x114>
  15103. 800b304: 6106 str r6, [r0, #16]
  15104. 800b306: b003 add sp, #12
  15105. 800b308: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
  15106. 800b30c: f843 2b04 str.w r2, [r3], #4
  15107. 800b310: e7e3 b.n 800b2da <__multiply+0x40>
  15108. 800b312: f8b3 a000 ldrh.w sl, [r3]
  15109. 800b316: 3204 adds r2, #4
  15110. 800b318: f1ba 0f00 cmp.w sl, #0
  15111. 800b31c: d020 beq.n 800b360 <__multiply+0xc6>
  15112. 800b31e: 46ae mov lr, r5
  15113. 800b320: 4689 mov r9, r1
  15114. 800b322: f04f 0c00 mov.w ip, #0
  15115. 800b326: f859 4b04 ldr.w r4, [r9], #4
  15116. 800b32a: f8be b000 ldrh.w fp, [lr]
  15117. 800b32e: b2a3 uxth r3, r4
  15118. 800b330: fb0a b303 mla r3, sl, r3, fp
  15119. 800b334: ea4f 4b14 mov.w fp, r4, lsr #16
  15120. 800b338: f8de 4000 ldr.w r4, [lr]
  15121. 800b33c: 4463 add r3, ip
  15122. 800b33e: ea4f 4c14 mov.w ip, r4, lsr #16
  15123. 800b342: fb0a c40b mla r4, sl, fp, ip
  15124. 800b346: eb04 4413 add.w r4, r4, r3, lsr #16
  15125. 800b34a: b29b uxth r3, r3
  15126. 800b34c: ea43 4304 orr.w r3, r3, r4, lsl #16
  15127. 800b350: 454f cmp r7, r9
  15128. 800b352: ea4f 4c14 mov.w ip, r4, lsr #16
  15129. 800b356: f84e 3b04 str.w r3, [lr], #4
  15130. 800b35a: d8e4 bhi.n 800b326 <__multiply+0x8c>
  15131. 800b35c: f8ce c000 str.w ip, [lr]
  15132. 800b360: f832 9c02 ldrh.w r9, [r2, #-2]
  15133. 800b364: f1b9 0f00 cmp.w r9, #0
  15134. 800b368: d01f beq.n 800b3aa <__multiply+0x110>
  15135. 800b36a: 46ae mov lr, r5
  15136. 800b36c: 468c mov ip, r1
  15137. 800b36e: f04f 0a00 mov.w sl, #0
  15138. 800b372: 682b ldr r3, [r5, #0]
  15139. 800b374: f8bc 4000 ldrh.w r4, [ip]
  15140. 800b378: f8be b002 ldrh.w fp, [lr, #2]
  15141. 800b37c: b29b uxth r3, r3
  15142. 800b37e: fb09 b404 mla r4, r9, r4, fp
  15143. 800b382: 44a2 add sl, r4
  15144. 800b384: ea43 430a orr.w r3, r3, sl, lsl #16
  15145. 800b388: f84e 3b04 str.w r3, [lr], #4
  15146. 800b38c: f85c 3b04 ldr.w r3, [ip], #4
  15147. 800b390: f8be 4000 ldrh.w r4, [lr]
  15148. 800b394: 0c1b lsrs r3, r3, #16
  15149. 800b396: fb09 4303 mla r3, r9, r3, r4
  15150. 800b39a: 4567 cmp r7, ip
  15151. 800b39c: eb03 431a add.w r3, r3, sl, lsr #16
  15152. 800b3a0: ea4f 4a13 mov.w sl, r3, lsr #16
  15153. 800b3a4: d8e6 bhi.n 800b374 <__multiply+0xda>
  15154. 800b3a6: f8ce 3000 str.w r3, [lr]
  15155. 800b3aa: 3504 adds r5, #4
  15156. 800b3ac: e7a0 b.n 800b2f0 <__multiply+0x56>
  15157. 800b3ae: 3e01 subs r6, #1
  15158. 800b3b0: e7a2 b.n 800b2f8 <__multiply+0x5e>
  15159. ...
  15160. 0800b3b4 <__pow5mult>:
  15161. 800b3b4: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
  15162. 800b3b8: 4615 mov r5, r2
  15163. 800b3ba: f012 0203 ands.w r2, r2, #3
  15164. 800b3be: 4606 mov r6, r0
  15165. 800b3c0: 460f mov r7, r1
  15166. 800b3c2: d007 beq.n 800b3d4 <__pow5mult+0x20>
  15167. 800b3c4: 4c21 ldr r4, [pc, #132] ; (800b44c <__pow5mult+0x98>)
  15168. 800b3c6: 3a01 subs r2, #1
  15169. 800b3c8: 2300 movs r3, #0
  15170. 800b3ca: f854 2022 ldr.w r2, [r4, r2, lsl #2]
  15171. 800b3ce: f7ff fed2 bl 800b176 <__multadd>
  15172. 800b3d2: 4607 mov r7, r0
  15173. 800b3d4: 10ad asrs r5, r5, #2
  15174. 800b3d6: d035 beq.n 800b444 <__pow5mult+0x90>
  15175. 800b3d8: 6a74 ldr r4, [r6, #36] ; 0x24
  15176. 800b3da: b93c cbnz r4, 800b3ec <__pow5mult+0x38>
  15177. 800b3dc: 2010 movs r0, #16
  15178. 800b3de: f7ff fe69 bl 800b0b4 <malloc>
  15179. 800b3e2: 6270 str r0, [r6, #36] ; 0x24
  15180. 800b3e4: 6044 str r4, [r0, #4]
  15181. 800b3e6: 6084 str r4, [r0, #8]
  15182. 800b3e8: 6004 str r4, [r0, #0]
  15183. 800b3ea: 60c4 str r4, [r0, #12]
  15184. 800b3ec: f8d6 8024 ldr.w r8, [r6, #36] ; 0x24
  15185. 800b3f0: f8d8 4008 ldr.w r4, [r8, #8]
  15186. 800b3f4: b94c cbnz r4, 800b40a <__pow5mult+0x56>
  15187. 800b3f6: f240 2171 movw r1, #625 ; 0x271
  15188. 800b3fa: 4630 mov r0, r6
  15189. 800b3fc: f7ff ff44 bl 800b288 <__i2b>
  15190. 800b400: 2300 movs r3, #0
  15191. 800b402: 4604 mov r4, r0
  15192. 800b404: f8c8 0008 str.w r0, [r8, #8]
  15193. 800b408: 6003 str r3, [r0, #0]
  15194. 800b40a: f04f 0800 mov.w r8, #0
  15195. 800b40e: 07eb lsls r3, r5, #31
  15196. 800b410: d50a bpl.n 800b428 <__pow5mult+0x74>
  15197. 800b412: 4639 mov r1, r7
  15198. 800b414: 4622 mov r2, r4
  15199. 800b416: 4630 mov r0, r6
  15200. 800b418: f7ff ff3f bl 800b29a <__multiply>
  15201. 800b41c: 4681 mov r9, r0
  15202. 800b41e: 4639 mov r1, r7
  15203. 800b420: 4630 mov r0, r6
  15204. 800b422: f7ff fe91 bl 800b148 <_Bfree>
  15205. 800b426: 464f mov r7, r9
  15206. 800b428: 106d asrs r5, r5, #1
  15207. 800b42a: d00b beq.n 800b444 <__pow5mult+0x90>
  15208. 800b42c: 6820 ldr r0, [r4, #0]
  15209. 800b42e: b938 cbnz r0, 800b440 <__pow5mult+0x8c>
  15210. 800b430: 4622 mov r2, r4
  15211. 800b432: 4621 mov r1, r4
  15212. 800b434: 4630 mov r0, r6
  15213. 800b436: f7ff ff30 bl 800b29a <__multiply>
  15214. 800b43a: 6020 str r0, [r4, #0]
  15215. 800b43c: f8c0 8000 str.w r8, [r0]
  15216. 800b440: 4604 mov r4, r0
  15217. 800b442: e7e4 b.n 800b40e <__pow5mult+0x5a>
  15218. 800b444: 4638 mov r0, r7
  15219. 800b446: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
  15220. 800b44a: bf00 nop
  15221. 800b44c: 0800beb0 .word 0x0800beb0
  15222. 0800b450 <__lshift>:
  15223. 800b450: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
  15224. 800b454: 460c mov r4, r1
  15225. 800b456: 4607 mov r7, r0
  15226. 800b458: 4616 mov r6, r2
  15227. 800b45a: 6923 ldr r3, [r4, #16]
  15228. 800b45c: ea4f 1a62 mov.w sl, r2, asr #5
  15229. 800b460: eb0a 0903 add.w r9, sl, r3
  15230. 800b464: 6849 ldr r1, [r1, #4]
  15231. 800b466: 68a3 ldr r3, [r4, #8]
  15232. 800b468: f109 0501 add.w r5, r9, #1
  15233. 800b46c: 42ab cmp r3, r5
  15234. 800b46e: db31 blt.n 800b4d4 <__lshift+0x84>
  15235. 800b470: 4638 mov r0, r7
  15236. 800b472: f7ff fe35 bl 800b0e0 <_Balloc>
  15237. 800b476: 2200 movs r2, #0
  15238. 800b478: 4680 mov r8, r0
  15239. 800b47a: 4611 mov r1, r2
  15240. 800b47c: f100 0314 add.w r3, r0, #20
  15241. 800b480: 4552 cmp r2, sl
  15242. 800b482: db2a blt.n 800b4da <__lshift+0x8a>
  15243. 800b484: 6920 ldr r0, [r4, #16]
  15244. 800b486: ea2a 7aea bic.w sl, sl, sl, asr #31
  15245. 800b48a: f104 0114 add.w r1, r4, #20
  15246. 800b48e: f016 021f ands.w r2, r6, #31
  15247. 800b492: eb03 038a add.w r3, r3, sl, lsl #2
  15248. 800b496: eb01 0e80 add.w lr, r1, r0, lsl #2
  15249. 800b49a: d022 beq.n 800b4e2 <__lshift+0x92>
  15250. 800b49c: 2000 movs r0, #0
  15251. 800b49e: f1c2 0c20 rsb ip, r2, #32
  15252. 800b4a2: 680e ldr r6, [r1, #0]
  15253. 800b4a4: 4096 lsls r6, r2
  15254. 800b4a6: 4330 orrs r0, r6
  15255. 800b4a8: f843 0b04 str.w r0, [r3], #4
  15256. 800b4ac: f851 0b04 ldr.w r0, [r1], #4
  15257. 800b4b0: 458e cmp lr, r1
  15258. 800b4b2: fa20 f00c lsr.w r0, r0, ip
  15259. 800b4b6: d8f4 bhi.n 800b4a2 <__lshift+0x52>
  15260. 800b4b8: 6018 str r0, [r3, #0]
  15261. 800b4ba: b108 cbz r0, 800b4c0 <__lshift+0x70>
  15262. 800b4bc: f109 0502 add.w r5, r9, #2
  15263. 800b4c0: 3d01 subs r5, #1
  15264. 800b4c2: 4638 mov r0, r7
  15265. 800b4c4: f8c8 5010 str.w r5, [r8, #16]
  15266. 800b4c8: 4621 mov r1, r4
  15267. 800b4ca: f7ff fe3d bl 800b148 <_Bfree>
  15268. 800b4ce: 4640 mov r0, r8
  15269. 800b4d0: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
  15270. 800b4d4: 3101 adds r1, #1
  15271. 800b4d6: 005b lsls r3, r3, #1
  15272. 800b4d8: e7c8 b.n 800b46c <__lshift+0x1c>
  15273. 800b4da: f843 1022 str.w r1, [r3, r2, lsl #2]
  15274. 800b4de: 3201 adds r2, #1
  15275. 800b4e0: e7ce b.n 800b480 <__lshift+0x30>
  15276. 800b4e2: 3b04 subs r3, #4
  15277. 800b4e4: f851 2b04 ldr.w r2, [r1], #4
  15278. 800b4e8: 458e cmp lr, r1
  15279. 800b4ea: f843 2f04 str.w r2, [r3, #4]!
  15280. 800b4ee: d8f9 bhi.n 800b4e4 <__lshift+0x94>
  15281. 800b4f0: e7e6 b.n 800b4c0 <__lshift+0x70>
  15282. 0800b4f2 <__mcmp>:
  15283. 800b4f2: 6903 ldr r3, [r0, #16]
  15284. 800b4f4: 690a ldr r2, [r1, #16]
  15285. 800b4f6: b530 push {r4, r5, lr}
  15286. 800b4f8: 1a9b subs r3, r3, r2
  15287. 800b4fa: d10c bne.n 800b516 <__mcmp+0x24>
  15288. 800b4fc: 0092 lsls r2, r2, #2
  15289. 800b4fe: 3014 adds r0, #20
  15290. 800b500: 3114 adds r1, #20
  15291. 800b502: 1884 adds r4, r0, r2
  15292. 800b504: 4411 add r1, r2
  15293. 800b506: f854 5d04 ldr.w r5, [r4, #-4]!
  15294. 800b50a: f851 2d04 ldr.w r2, [r1, #-4]!
  15295. 800b50e: 4295 cmp r5, r2
  15296. 800b510: d003 beq.n 800b51a <__mcmp+0x28>
  15297. 800b512: d305 bcc.n 800b520 <__mcmp+0x2e>
  15298. 800b514: 2301 movs r3, #1
  15299. 800b516: 4618 mov r0, r3
  15300. 800b518: bd30 pop {r4, r5, pc}
  15301. 800b51a: 42a0 cmp r0, r4
  15302. 800b51c: d3f3 bcc.n 800b506 <__mcmp+0x14>
  15303. 800b51e: e7fa b.n 800b516 <__mcmp+0x24>
  15304. 800b520: f04f 33ff mov.w r3, #4294967295
  15305. 800b524: e7f7 b.n 800b516 <__mcmp+0x24>
  15306. 0800b526 <__mdiff>:
  15307. 800b526: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
  15308. 800b52a: 460d mov r5, r1
  15309. 800b52c: 4607 mov r7, r0
  15310. 800b52e: 4611 mov r1, r2
  15311. 800b530: 4628 mov r0, r5
  15312. 800b532: 4614 mov r4, r2
  15313. 800b534: f7ff ffdd bl 800b4f2 <__mcmp>
  15314. 800b538: 1e06 subs r6, r0, #0
  15315. 800b53a: d108 bne.n 800b54e <__mdiff+0x28>
  15316. 800b53c: 4631 mov r1, r6
  15317. 800b53e: 4638 mov r0, r7
  15318. 800b540: f7ff fdce bl 800b0e0 <_Balloc>
  15319. 800b544: 2301 movs r3, #1
  15320. 800b546: 6146 str r6, [r0, #20]
  15321. 800b548: 6103 str r3, [r0, #16]
  15322. 800b54a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
  15323. 800b54e: bfa4 itt ge
  15324. 800b550: 4623 movge r3, r4
  15325. 800b552: 462c movge r4, r5
  15326. 800b554: 4638 mov r0, r7
  15327. 800b556: 6861 ldr r1, [r4, #4]
  15328. 800b558: bfa6 itte ge
  15329. 800b55a: 461d movge r5, r3
  15330. 800b55c: 2600 movge r6, #0
  15331. 800b55e: 2601 movlt r6, #1
  15332. 800b560: f7ff fdbe bl 800b0e0 <_Balloc>
  15333. 800b564: f04f 0c00 mov.w ip, #0
  15334. 800b568: 60c6 str r6, [r0, #12]
  15335. 800b56a: 692b ldr r3, [r5, #16]
  15336. 800b56c: 6926 ldr r6, [r4, #16]
  15337. 800b56e: f104 0214 add.w r2, r4, #20
  15338. 800b572: f105 0914 add.w r9, r5, #20
  15339. 800b576: eb02 0786 add.w r7, r2, r6, lsl #2
  15340. 800b57a: eb09 0883 add.w r8, r9, r3, lsl #2
  15341. 800b57e: f100 0114 add.w r1, r0, #20
  15342. 800b582: f852 ab04 ldr.w sl, [r2], #4
  15343. 800b586: f859 5b04 ldr.w r5, [r9], #4
  15344. 800b58a: fa1f f38a uxth.w r3, sl
  15345. 800b58e: 4463 add r3, ip
  15346. 800b590: b2ac uxth r4, r5
  15347. 800b592: 1b1b subs r3, r3, r4
  15348. 800b594: 0c2c lsrs r4, r5, #16
  15349. 800b596: ebc4 441a rsb r4, r4, sl, lsr #16
  15350. 800b59a: eb04 4423 add.w r4, r4, r3, asr #16
  15351. 800b59e: b29b uxth r3, r3
  15352. 800b5a0: ea4f 4c24 mov.w ip, r4, asr #16
  15353. 800b5a4: 45c8 cmp r8, r9
  15354. 800b5a6: ea43 4404 orr.w r4, r3, r4, lsl #16
  15355. 800b5aa: 4696 mov lr, r2
  15356. 800b5ac: f841 4b04 str.w r4, [r1], #4
  15357. 800b5b0: d8e7 bhi.n 800b582 <__mdiff+0x5c>
  15358. 800b5b2: 45be cmp lr, r7
  15359. 800b5b4: d305 bcc.n 800b5c2 <__mdiff+0x9c>
  15360. 800b5b6: f851 3d04 ldr.w r3, [r1, #-4]!
  15361. 800b5ba: b18b cbz r3, 800b5e0 <__mdiff+0xba>
  15362. 800b5bc: 6106 str r6, [r0, #16]
  15363. 800b5be: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
  15364. 800b5c2: f85e 4b04 ldr.w r4, [lr], #4
  15365. 800b5c6: b2a2 uxth r2, r4
  15366. 800b5c8: 4462 add r2, ip
  15367. 800b5ca: 1413 asrs r3, r2, #16
  15368. 800b5cc: eb03 4314 add.w r3, r3, r4, lsr #16
  15369. 800b5d0: b292 uxth r2, r2
  15370. 800b5d2: ea42 4203 orr.w r2, r2, r3, lsl #16
  15371. 800b5d6: ea4f 4c23 mov.w ip, r3, asr #16
  15372. 800b5da: f841 2b04 str.w r2, [r1], #4
  15373. 800b5de: e7e8 b.n 800b5b2 <__mdiff+0x8c>
  15374. 800b5e0: 3e01 subs r6, #1
  15375. 800b5e2: e7e8 b.n 800b5b6 <__mdiff+0x90>
  15376. 0800b5e4 <__d2b>:
  15377. 800b5e4: e92d 41f3 stmdb sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
  15378. 800b5e8: 461c mov r4, r3
  15379. 800b5ea: 2101 movs r1, #1
  15380. 800b5ec: 4690 mov r8, r2
  15381. 800b5ee: 9e08 ldr r6, [sp, #32]
  15382. 800b5f0: 9d09 ldr r5, [sp, #36] ; 0x24
  15383. 800b5f2: f7ff fd75 bl 800b0e0 <_Balloc>
  15384. 800b5f6: f3c4 0213 ubfx r2, r4, #0, #20
  15385. 800b5fa: f3c4 540a ubfx r4, r4, #20, #11
  15386. 800b5fe: 4607 mov r7, r0
  15387. 800b600: bb34 cbnz r4, 800b650 <__d2b+0x6c>
  15388. 800b602: 9201 str r2, [sp, #4]
  15389. 800b604: f1b8 0f00 cmp.w r8, #0
  15390. 800b608: d027 beq.n 800b65a <__d2b+0x76>
  15391. 800b60a: a802 add r0, sp, #8
  15392. 800b60c: f840 8d08 str.w r8, [r0, #-8]!
  15393. 800b610: f7ff fe0b bl 800b22a <__lo0bits>
  15394. 800b614: 9900 ldr r1, [sp, #0]
  15395. 800b616: b1f0 cbz r0, 800b656 <__d2b+0x72>
  15396. 800b618: 9a01 ldr r2, [sp, #4]
  15397. 800b61a: f1c0 0320 rsb r3, r0, #32
  15398. 800b61e: fa02 f303 lsl.w r3, r2, r3
  15399. 800b622: 430b orrs r3, r1
  15400. 800b624: 40c2 lsrs r2, r0
  15401. 800b626: 617b str r3, [r7, #20]
  15402. 800b628: 9201 str r2, [sp, #4]
  15403. 800b62a: 9b01 ldr r3, [sp, #4]
  15404. 800b62c: 2b00 cmp r3, #0
  15405. 800b62e: bf14 ite ne
  15406. 800b630: 2102 movne r1, #2
  15407. 800b632: 2101 moveq r1, #1
  15408. 800b634: 61bb str r3, [r7, #24]
  15409. 800b636: 6139 str r1, [r7, #16]
  15410. 800b638: b1c4 cbz r4, 800b66c <__d2b+0x88>
  15411. 800b63a: f2a4 4433 subw r4, r4, #1075 ; 0x433
  15412. 800b63e: 4404 add r4, r0
  15413. 800b640: 6034 str r4, [r6, #0]
  15414. 800b642: f1c0 0035 rsb r0, r0, #53 ; 0x35
  15415. 800b646: 6028 str r0, [r5, #0]
  15416. 800b648: 4638 mov r0, r7
  15417. 800b64a: b002 add sp, #8
  15418. 800b64c: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
  15419. 800b650: f442 1280 orr.w r2, r2, #1048576 ; 0x100000
  15420. 800b654: e7d5 b.n 800b602 <__d2b+0x1e>
  15421. 800b656: 6179 str r1, [r7, #20]
  15422. 800b658: e7e7 b.n 800b62a <__d2b+0x46>
  15423. 800b65a: a801 add r0, sp, #4
  15424. 800b65c: f7ff fde5 bl 800b22a <__lo0bits>
  15425. 800b660: 2101 movs r1, #1
  15426. 800b662: 9b01 ldr r3, [sp, #4]
  15427. 800b664: 6139 str r1, [r7, #16]
  15428. 800b666: 617b str r3, [r7, #20]
  15429. 800b668: 3020 adds r0, #32
  15430. 800b66a: e7e5 b.n 800b638 <__d2b+0x54>
  15431. 800b66c: f2a0 4032 subw r0, r0, #1074 ; 0x432
  15432. 800b670: eb07 0381 add.w r3, r7, r1, lsl #2
  15433. 800b674: 6030 str r0, [r6, #0]
  15434. 800b676: 6918 ldr r0, [r3, #16]
  15435. 800b678: f7ff fdb8 bl 800b1ec <__hi0bits>
  15436. 800b67c: ebc0 1041 rsb r0, r0, r1, lsl #5
  15437. 800b680: e7e1 b.n 800b646 <__d2b+0x62>
  15438. 0800b682 <_calloc_r>:
  15439. 800b682: b538 push {r3, r4, r5, lr}
  15440. 800b684: fb02 f401 mul.w r4, r2, r1
  15441. 800b688: 4621 mov r1, r4
  15442. 800b68a: f000 f855 bl 800b738 <_malloc_r>
  15443. 800b68e: 4605 mov r5, r0
  15444. 800b690: b118 cbz r0, 800b69a <_calloc_r+0x18>
  15445. 800b692: 4622 mov r2, r4
  15446. 800b694: 2100 movs r1, #0
  15447. 800b696: f7fd fe64 bl 8009362 <memset>
  15448. 800b69a: 4628 mov r0, r5
  15449. 800b69c: bd38 pop {r3, r4, r5, pc}
  15450. ...
  15451. 0800b6a0 <_free_r>:
  15452. 800b6a0: b538 push {r3, r4, r5, lr}
  15453. 800b6a2: 4605 mov r5, r0
  15454. 800b6a4: 2900 cmp r1, #0
  15455. 800b6a6: d043 beq.n 800b730 <_free_r+0x90>
  15456. 800b6a8: f851 3c04 ldr.w r3, [r1, #-4]
  15457. 800b6ac: 1f0c subs r4, r1, #4
  15458. 800b6ae: 2b00 cmp r3, #0
  15459. 800b6b0: bfb8 it lt
  15460. 800b6b2: 18e4 addlt r4, r4, r3
  15461. 800b6b4: f000 fa98 bl 800bbe8 <__malloc_lock>
  15462. 800b6b8: 4a1e ldr r2, [pc, #120] ; (800b734 <_free_r+0x94>)
  15463. 800b6ba: 6813 ldr r3, [r2, #0]
  15464. 800b6bc: 4610 mov r0, r2
  15465. 800b6be: b933 cbnz r3, 800b6ce <_free_r+0x2e>
  15466. 800b6c0: 6063 str r3, [r4, #4]
  15467. 800b6c2: 6014 str r4, [r2, #0]
  15468. 800b6c4: 4628 mov r0, r5
  15469. 800b6c6: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
  15470. 800b6ca: f000 ba8e b.w 800bbea <__malloc_unlock>
  15471. 800b6ce: 42a3 cmp r3, r4
  15472. 800b6d0: d90b bls.n 800b6ea <_free_r+0x4a>
  15473. 800b6d2: 6821 ldr r1, [r4, #0]
  15474. 800b6d4: 1862 adds r2, r4, r1
  15475. 800b6d6: 4293 cmp r3, r2
  15476. 800b6d8: bf01 itttt eq
  15477. 800b6da: 681a ldreq r2, [r3, #0]
  15478. 800b6dc: 685b ldreq r3, [r3, #4]
  15479. 800b6de: 1852 addeq r2, r2, r1
  15480. 800b6e0: 6022 streq r2, [r4, #0]
  15481. 800b6e2: 6063 str r3, [r4, #4]
  15482. 800b6e4: 6004 str r4, [r0, #0]
  15483. 800b6e6: e7ed b.n 800b6c4 <_free_r+0x24>
  15484. 800b6e8: 4613 mov r3, r2
  15485. 800b6ea: 685a ldr r2, [r3, #4]
  15486. 800b6ec: b10a cbz r2, 800b6f2 <_free_r+0x52>
  15487. 800b6ee: 42a2 cmp r2, r4
  15488. 800b6f0: d9fa bls.n 800b6e8 <_free_r+0x48>
  15489. 800b6f2: 6819 ldr r1, [r3, #0]
  15490. 800b6f4: 1858 adds r0, r3, r1
  15491. 800b6f6: 42a0 cmp r0, r4
  15492. 800b6f8: d10b bne.n 800b712 <_free_r+0x72>
  15493. 800b6fa: 6820 ldr r0, [r4, #0]
  15494. 800b6fc: 4401 add r1, r0
  15495. 800b6fe: 1858 adds r0, r3, r1
  15496. 800b700: 4282 cmp r2, r0
  15497. 800b702: 6019 str r1, [r3, #0]
  15498. 800b704: d1de bne.n 800b6c4 <_free_r+0x24>
  15499. 800b706: 6810 ldr r0, [r2, #0]
  15500. 800b708: 6852 ldr r2, [r2, #4]
  15501. 800b70a: 4401 add r1, r0
  15502. 800b70c: 6019 str r1, [r3, #0]
  15503. 800b70e: 605a str r2, [r3, #4]
  15504. 800b710: e7d8 b.n 800b6c4 <_free_r+0x24>
  15505. 800b712: d902 bls.n 800b71a <_free_r+0x7a>
  15506. 800b714: 230c movs r3, #12
  15507. 800b716: 602b str r3, [r5, #0]
  15508. 800b718: e7d4 b.n 800b6c4 <_free_r+0x24>
  15509. 800b71a: 6820 ldr r0, [r4, #0]
  15510. 800b71c: 1821 adds r1, r4, r0
  15511. 800b71e: 428a cmp r2, r1
  15512. 800b720: bf01 itttt eq
  15513. 800b722: 6811 ldreq r1, [r2, #0]
  15514. 800b724: 6852 ldreq r2, [r2, #4]
  15515. 800b726: 1809 addeq r1, r1, r0
  15516. 800b728: 6021 streq r1, [r4, #0]
  15517. 800b72a: 6062 str r2, [r4, #4]
  15518. 800b72c: 605c str r4, [r3, #4]
  15519. 800b72e: e7c9 b.n 800b6c4 <_free_r+0x24>
  15520. 800b730: bd38 pop {r3, r4, r5, pc}
  15521. 800b732: bf00 nop
  15522. 800b734: 20000458 .word 0x20000458
  15523. 0800b738 <_malloc_r>:
  15524. 800b738: b570 push {r4, r5, r6, lr}
  15525. 800b73a: 1ccd adds r5, r1, #3
  15526. 800b73c: f025 0503 bic.w r5, r5, #3
  15527. 800b740: 3508 adds r5, #8
  15528. 800b742: 2d0c cmp r5, #12
  15529. 800b744: bf38 it cc
  15530. 800b746: 250c movcc r5, #12
  15531. 800b748: 2d00 cmp r5, #0
  15532. 800b74a: 4606 mov r6, r0
  15533. 800b74c: db01 blt.n 800b752 <_malloc_r+0x1a>
  15534. 800b74e: 42a9 cmp r1, r5
  15535. 800b750: d903 bls.n 800b75a <_malloc_r+0x22>
  15536. 800b752: 230c movs r3, #12
  15537. 800b754: 6033 str r3, [r6, #0]
  15538. 800b756: 2000 movs r0, #0
  15539. 800b758: bd70 pop {r4, r5, r6, pc}
  15540. 800b75a: f000 fa45 bl 800bbe8 <__malloc_lock>
  15541. 800b75e: 4a23 ldr r2, [pc, #140] ; (800b7ec <_malloc_r+0xb4>)
  15542. 800b760: 6814 ldr r4, [r2, #0]
  15543. 800b762: 4621 mov r1, r4
  15544. 800b764: b991 cbnz r1, 800b78c <_malloc_r+0x54>
  15545. 800b766: 4c22 ldr r4, [pc, #136] ; (800b7f0 <_malloc_r+0xb8>)
  15546. 800b768: 6823 ldr r3, [r4, #0]
  15547. 800b76a: b91b cbnz r3, 800b774 <_malloc_r+0x3c>
  15548. 800b76c: 4630 mov r0, r6
  15549. 800b76e: f000 f97f bl 800ba70 <_sbrk_r>
  15550. 800b772: 6020 str r0, [r4, #0]
  15551. 800b774: 4629 mov r1, r5
  15552. 800b776: 4630 mov r0, r6
  15553. 800b778: f000 f97a bl 800ba70 <_sbrk_r>
  15554. 800b77c: 1c43 adds r3, r0, #1
  15555. 800b77e: d126 bne.n 800b7ce <_malloc_r+0x96>
  15556. 800b780: 230c movs r3, #12
  15557. 800b782: 4630 mov r0, r6
  15558. 800b784: 6033 str r3, [r6, #0]
  15559. 800b786: f000 fa30 bl 800bbea <__malloc_unlock>
  15560. 800b78a: e7e4 b.n 800b756 <_malloc_r+0x1e>
  15561. 800b78c: 680b ldr r3, [r1, #0]
  15562. 800b78e: 1b5b subs r3, r3, r5
  15563. 800b790: d41a bmi.n 800b7c8 <_malloc_r+0x90>
  15564. 800b792: 2b0b cmp r3, #11
  15565. 800b794: d90f bls.n 800b7b6 <_malloc_r+0x7e>
  15566. 800b796: 600b str r3, [r1, #0]
  15567. 800b798: 18cc adds r4, r1, r3
  15568. 800b79a: 50cd str r5, [r1, r3]
  15569. 800b79c: 4630 mov r0, r6
  15570. 800b79e: f000 fa24 bl 800bbea <__malloc_unlock>
  15571. 800b7a2: f104 000b add.w r0, r4, #11
  15572. 800b7a6: 1d23 adds r3, r4, #4
  15573. 800b7a8: f020 0007 bic.w r0, r0, #7
  15574. 800b7ac: 1ac3 subs r3, r0, r3
  15575. 800b7ae: d01b beq.n 800b7e8 <_malloc_r+0xb0>
  15576. 800b7b0: 425a negs r2, r3
  15577. 800b7b2: 50e2 str r2, [r4, r3]
  15578. 800b7b4: bd70 pop {r4, r5, r6, pc}
  15579. 800b7b6: 428c cmp r4, r1
  15580. 800b7b8: bf0b itete eq
  15581. 800b7ba: 6863 ldreq r3, [r4, #4]
  15582. 800b7bc: 684b ldrne r3, [r1, #4]
  15583. 800b7be: 6013 streq r3, [r2, #0]
  15584. 800b7c0: 6063 strne r3, [r4, #4]
  15585. 800b7c2: bf18 it ne
  15586. 800b7c4: 460c movne r4, r1
  15587. 800b7c6: e7e9 b.n 800b79c <_malloc_r+0x64>
  15588. 800b7c8: 460c mov r4, r1
  15589. 800b7ca: 6849 ldr r1, [r1, #4]
  15590. 800b7cc: e7ca b.n 800b764 <_malloc_r+0x2c>
  15591. 800b7ce: 1cc4 adds r4, r0, #3
  15592. 800b7d0: f024 0403 bic.w r4, r4, #3
  15593. 800b7d4: 42a0 cmp r0, r4
  15594. 800b7d6: d005 beq.n 800b7e4 <_malloc_r+0xac>
  15595. 800b7d8: 1a21 subs r1, r4, r0
  15596. 800b7da: 4630 mov r0, r6
  15597. 800b7dc: f000 f948 bl 800ba70 <_sbrk_r>
  15598. 800b7e0: 3001 adds r0, #1
  15599. 800b7e2: d0cd beq.n 800b780 <_malloc_r+0x48>
  15600. 800b7e4: 6025 str r5, [r4, #0]
  15601. 800b7e6: e7d9 b.n 800b79c <_malloc_r+0x64>
  15602. 800b7e8: bd70 pop {r4, r5, r6, pc}
  15603. 800b7ea: bf00 nop
  15604. 800b7ec: 20000458 .word 0x20000458
  15605. 800b7f0: 2000045c .word 0x2000045c
  15606. 0800b7f4 <__sfputc_r>:
  15607. 800b7f4: 6893 ldr r3, [r2, #8]
  15608. 800b7f6: b410 push {r4}
  15609. 800b7f8: 3b01 subs r3, #1
  15610. 800b7fa: 2b00 cmp r3, #0
  15611. 800b7fc: 6093 str r3, [r2, #8]
  15612. 800b7fe: da08 bge.n 800b812 <__sfputc_r+0x1e>
  15613. 800b800: 6994 ldr r4, [r2, #24]
  15614. 800b802: 42a3 cmp r3, r4
  15615. 800b804: db02 blt.n 800b80c <__sfputc_r+0x18>
  15616. 800b806: b2cb uxtb r3, r1
  15617. 800b808: 2b0a cmp r3, #10
  15618. 800b80a: d102 bne.n 800b812 <__sfputc_r+0x1e>
  15619. 800b80c: bc10 pop {r4}
  15620. 800b80e: f7fe bb43 b.w 8009e98 <__swbuf_r>
  15621. 800b812: 6813 ldr r3, [r2, #0]
  15622. 800b814: 1c58 adds r0, r3, #1
  15623. 800b816: 6010 str r0, [r2, #0]
  15624. 800b818: 7019 strb r1, [r3, #0]
  15625. 800b81a: b2c8 uxtb r0, r1
  15626. 800b81c: bc10 pop {r4}
  15627. 800b81e: 4770 bx lr
  15628. 0800b820 <__sfputs_r>:
  15629. 800b820: b5f8 push {r3, r4, r5, r6, r7, lr}
  15630. 800b822: 4606 mov r6, r0
  15631. 800b824: 460f mov r7, r1
  15632. 800b826: 4614 mov r4, r2
  15633. 800b828: 18d5 adds r5, r2, r3
  15634. 800b82a: 42ac cmp r4, r5
  15635. 800b82c: d101 bne.n 800b832 <__sfputs_r+0x12>
  15636. 800b82e: 2000 movs r0, #0
  15637. 800b830: e007 b.n 800b842 <__sfputs_r+0x22>
  15638. 800b832: 463a mov r2, r7
  15639. 800b834: f814 1b01 ldrb.w r1, [r4], #1
  15640. 800b838: 4630 mov r0, r6
  15641. 800b83a: f7ff ffdb bl 800b7f4 <__sfputc_r>
  15642. 800b83e: 1c43 adds r3, r0, #1
  15643. 800b840: d1f3 bne.n 800b82a <__sfputs_r+0xa>
  15644. 800b842: bdf8 pop {r3, r4, r5, r6, r7, pc}
  15645. 0800b844 <_vfiprintf_r>:
  15646. 800b844: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
  15647. 800b848: b09d sub sp, #116 ; 0x74
  15648. 800b84a: 460c mov r4, r1
  15649. 800b84c: 4617 mov r7, r2
  15650. 800b84e: 9303 str r3, [sp, #12]
  15651. 800b850: 4606 mov r6, r0
  15652. 800b852: b118 cbz r0, 800b85c <_vfiprintf_r+0x18>
  15653. 800b854: 6983 ldr r3, [r0, #24]
  15654. 800b856: b90b cbnz r3, 800b85c <_vfiprintf_r+0x18>
  15655. 800b858: f7ff fb30 bl 800aebc <__sinit>
  15656. 800b85c: 4b7c ldr r3, [pc, #496] ; (800ba50 <_vfiprintf_r+0x20c>)
  15657. 800b85e: 429c cmp r4, r3
  15658. 800b860: d157 bne.n 800b912 <_vfiprintf_r+0xce>
  15659. 800b862: 6874 ldr r4, [r6, #4]
  15660. 800b864: 89a3 ldrh r3, [r4, #12]
  15661. 800b866: 0718 lsls r0, r3, #28
  15662. 800b868: d55d bpl.n 800b926 <_vfiprintf_r+0xe2>
  15663. 800b86a: 6923 ldr r3, [r4, #16]
  15664. 800b86c: 2b00 cmp r3, #0
  15665. 800b86e: d05a beq.n 800b926 <_vfiprintf_r+0xe2>
  15666. 800b870: 2300 movs r3, #0
  15667. 800b872: 9309 str r3, [sp, #36] ; 0x24
  15668. 800b874: 2320 movs r3, #32
  15669. 800b876: f88d 3029 strb.w r3, [sp, #41] ; 0x29
  15670. 800b87a: 2330 movs r3, #48 ; 0x30
  15671. 800b87c: f04f 0b01 mov.w fp, #1
  15672. 800b880: f88d 302a strb.w r3, [sp, #42] ; 0x2a
  15673. 800b884: 46b8 mov r8, r7
  15674. 800b886: 4645 mov r5, r8
  15675. 800b888: f815 3b01 ldrb.w r3, [r5], #1
  15676. 800b88c: 2b00 cmp r3, #0
  15677. 800b88e: d155 bne.n 800b93c <_vfiprintf_r+0xf8>
  15678. 800b890: ebb8 0a07 subs.w sl, r8, r7
  15679. 800b894: d00b beq.n 800b8ae <_vfiprintf_r+0x6a>
  15680. 800b896: 4653 mov r3, sl
  15681. 800b898: 463a mov r2, r7
  15682. 800b89a: 4621 mov r1, r4
  15683. 800b89c: 4630 mov r0, r6
  15684. 800b89e: f7ff ffbf bl 800b820 <__sfputs_r>
  15685. 800b8a2: 3001 adds r0, #1
  15686. 800b8a4: f000 80c4 beq.w 800ba30 <_vfiprintf_r+0x1ec>
  15687. 800b8a8: 9b09 ldr r3, [sp, #36] ; 0x24
  15688. 800b8aa: 4453 add r3, sl
  15689. 800b8ac: 9309 str r3, [sp, #36] ; 0x24
  15690. 800b8ae: f898 3000 ldrb.w r3, [r8]
  15691. 800b8b2: 2b00 cmp r3, #0
  15692. 800b8b4: f000 80bc beq.w 800ba30 <_vfiprintf_r+0x1ec>
  15693. 800b8b8: 2300 movs r3, #0
  15694. 800b8ba: f04f 32ff mov.w r2, #4294967295
  15695. 800b8be: 9304 str r3, [sp, #16]
  15696. 800b8c0: 9307 str r3, [sp, #28]
  15697. 800b8c2: 9205 str r2, [sp, #20]
  15698. 800b8c4: 9306 str r3, [sp, #24]
  15699. 800b8c6: f88d 3053 strb.w r3, [sp, #83] ; 0x53
  15700. 800b8ca: 931a str r3, [sp, #104] ; 0x68
  15701. 800b8cc: 2205 movs r2, #5
  15702. 800b8ce: 7829 ldrb r1, [r5, #0]
  15703. 800b8d0: 4860 ldr r0, [pc, #384] ; (800ba54 <_vfiprintf_r+0x210>)
  15704. 800b8d2: f7ff fbf7 bl 800b0c4 <memchr>
  15705. 800b8d6: f105 0801 add.w r8, r5, #1
  15706. 800b8da: 9b04 ldr r3, [sp, #16]
  15707. 800b8dc: 2800 cmp r0, #0
  15708. 800b8de: d131 bne.n 800b944 <_vfiprintf_r+0x100>
  15709. 800b8e0: 06d9 lsls r1, r3, #27
  15710. 800b8e2: bf44 itt mi
  15711. 800b8e4: 2220 movmi r2, #32
  15712. 800b8e6: f88d 2053 strbmi.w r2, [sp, #83] ; 0x53
  15713. 800b8ea: 071a lsls r2, r3, #28
  15714. 800b8ec: bf44 itt mi
  15715. 800b8ee: 222b movmi r2, #43 ; 0x2b
  15716. 800b8f0: f88d 2053 strbmi.w r2, [sp, #83] ; 0x53
  15717. 800b8f4: 782a ldrb r2, [r5, #0]
  15718. 800b8f6: 2a2a cmp r2, #42 ; 0x2a
  15719. 800b8f8: d02c beq.n 800b954 <_vfiprintf_r+0x110>
  15720. 800b8fa: 2100 movs r1, #0
  15721. 800b8fc: 200a movs r0, #10
  15722. 800b8fe: 9a07 ldr r2, [sp, #28]
  15723. 800b900: 46a8 mov r8, r5
  15724. 800b902: f898 3000 ldrb.w r3, [r8]
  15725. 800b906: 3501 adds r5, #1
  15726. 800b908: 3b30 subs r3, #48 ; 0x30
  15727. 800b90a: 2b09 cmp r3, #9
  15728. 800b90c: d96d bls.n 800b9ea <_vfiprintf_r+0x1a6>
  15729. 800b90e: b371 cbz r1, 800b96e <_vfiprintf_r+0x12a>
  15730. 800b910: e026 b.n 800b960 <_vfiprintf_r+0x11c>
  15731. 800b912: 4b51 ldr r3, [pc, #324] ; (800ba58 <_vfiprintf_r+0x214>)
  15732. 800b914: 429c cmp r4, r3
  15733. 800b916: d101 bne.n 800b91c <_vfiprintf_r+0xd8>
  15734. 800b918: 68b4 ldr r4, [r6, #8]
  15735. 800b91a: e7a3 b.n 800b864 <_vfiprintf_r+0x20>
  15736. 800b91c: 4b4f ldr r3, [pc, #316] ; (800ba5c <_vfiprintf_r+0x218>)
  15737. 800b91e: 429c cmp r4, r3
  15738. 800b920: bf08 it eq
  15739. 800b922: 68f4 ldreq r4, [r6, #12]
  15740. 800b924: e79e b.n 800b864 <_vfiprintf_r+0x20>
  15741. 800b926: 4621 mov r1, r4
  15742. 800b928: 4630 mov r0, r6
  15743. 800b92a: f7fe fb07 bl 8009f3c <__swsetup_r>
  15744. 800b92e: 2800 cmp r0, #0
  15745. 800b930: d09e beq.n 800b870 <_vfiprintf_r+0x2c>
  15746. 800b932: f04f 30ff mov.w r0, #4294967295
  15747. 800b936: b01d add sp, #116 ; 0x74
  15748. 800b938: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
  15749. 800b93c: 2b25 cmp r3, #37 ; 0x25
  15750. 800b93e: d0a7 beq.n 800b890 <_vfiprintf_r+0x4c>
  15751. 800b940: 46a8 mov r8, r5
  15752. 800b942: e7a0 b.n 800b886 <_vfiprintf_r+0x42>
  15753. 800b944: 4a43 ldr r2, [pc, #268] ; (800ba54 <_vfiprintf_r+0x210>)
  15754. 800b946: 4645 mov r5, r8
  15755. 800b948: 1a80 subs r0, r0, r2
  15756. 800b94a: fa0b f000 lsl.w r0, fp, r0
  15757. 800b94e: 4318 orrs r0, r3
  15758. 800b950: 9004 str r0, [sp, #16]
  15759. 800b952: e7bb b.n 800b8cc <_vfiprintf_r+0x88>
  15760. 800b954: 9a03 ldr r2, [sp, #12]
  15761. 800b956: 1d11 adds r1, r2, #4
  15762. 800b958: 6812 ldr r2, [r2, #0]
  15763. 800b95a: 9103 str r1, [sp, #12]
  15764. 800b95c: 2a00 cmp r2, #0
  15765. 800b95e: db01 blt.n 800b964 <_vfiprintf_r+0x120>
  15766. 800b960: 9207 str r2, [sp, #28]
  15767. 800b962: e004 b.n 800b96e <_vfiprintf_r+0x12a>
  15768. 800b964: 4252 negs r2, r2
  15769. 800b966: f043 0302 orr.w r3, r3, #2
  15770. 800b96a: 9207 str r2, [sp, #28]
  15771. 800b96c: 9304 str r3, [sp, #16]
  15772. 800b96e: f898 3000 ldrb.w r3, [r8]
  15773. 800b972: 2b2e cmp r3, #46 ; 0x2e
  15774. 800b974: d110 bne.n 800b998 <_vfiprintf_r+0x154>
  15775. 800b976: f898 3001 ldrb.w r3, [r8, #1]
  15776. 800b97a: f108 0101 add.w r1, r8, #1
  15777. 800b97e: 2b2a cmp r3, #42 ; 0x2a
  15778. 800b980: d137 bne.n 800b9f2 <_vfiprintf_r+0x1ae>
  15779. 800b982: 9b03 ldr r3, [sp, #12]
  15780. 800b984: f108 0802 add.w r8, r8, #2
  15781. 800b988: 1d1a adds r2, r3, #4
  15782. 800b98a: 681b ldr r3, [r3, #0]
  15783. 800b98c: 9203 str r2, [sp, #12]
  15784. 800b98e: 2b00 cmp r3, #0
  15785. 800b990: bfb8 it lt
  15786. 800b992: f04f 33ff movlt.w r3, #4294967295
  15787. 800b996: 9305 str r3, [sp, #20]
  15788. 800b998: 4d31 ldr r5, [pc, #196] ; (800ba60 <_vfiprintf_r+0x21c>)
  15789. 800b99a: 2203 movs r2, #3
  15790. 800b99c: f898 1000 ldrb.w r1, [r8]
  15791. 800b9a0: 4628 mov r0, r5
  15792. 800b9a2: f7ff fb8f bl 800b0c4 <memchr>
  15793. 800b9a6: b140 cbz r0, 800b9ba <_vfiprintf_r+0x176>
  15794. 800b9a8: 2340 movs r3, #64 ; 0x40
  15795. 800b9aa: 1b40 subs r0, r0, r5
  15796. 800b9ac: fa03 f000 lsl.w r0, r3, r0
  15797. 800b9b0: 9b04 ldr r3, [sp, #16]
  15798. 800b9b2: f108 0801 add.w r8, r8, #1
  15799. 800b9b6: 4303 orrs r3, r0
  15800. 800b9b8: 9304 str r3, [sp, #16]
  15801. 800b9ba: f898 1000 ldrb.w r1, [r8]
  15802. 800b9be: 2206 movs r2, #6
  15803. 800b9c0: 4828 ldr r0, [pc, #160] ; (800ba64 <_vfiprintf_r+0x220>)
  15804. 800b9c2: f108 0701 add.w r7, r8, #1
  15805. 800b9c6: f88d 1028 strb.w r1, [sp, #40] ; 0x28
  15806. 800b9ca: f7ff fb7b bl 800b0c4 <memchr>
  15807. 800b9ce: 2800 cmp r0, #0
  15808. 800b9d0: d034 beq.n 800ba3c <_vfiprintf_r+0x1f8>
  15809. 800b9d2: 4b25 ldr r3, [pc, #148] ; (800ba68 <_vfiprintf_r+0x224>)
  15810. 800b9d4: bb03 cbnz r3, 800ba18 <_vfiprintf_r+0x1d4>
  15811. 800b9d6: 9b03 ldr r3, [sp, #12]
  15812. 800b9d8: 3307 adds r3, #7
  15813. 800b9da: f023 0307 bic.w r3, r3, #7
  15814. 800b9de: 3308 adds r3, #8
  15815. 800b9e0: 9303 str r3, [sp, #12]
  15816. 800b9e2: 9b09 ldr r3, [sp, #36] ; 0x24
  15817. 800b9e4: 444b add r3, r9
  15818. 800b9e6: 9309 str r3, [sp, #36] ; 0x24
  15819. 800b9e8: e74c b.n 800b884 <_vfiprintf_r+0x40>
  15820. 800b9ea: fb00 3202 mla r2, r0, r2, r3
  15821. 800b9ee: 2101 movs r1, #1
  15822. 800b9f0: e786 b.n 800b900 <_vfiprintf_r+0xbc>
  15823. 800b9f2: 2300 movs r3, #0
  15824. 800b9f4: 250a movs r5, #10
  15825. 800b9f6: 4618 mov r0, r3
  15826. 800b9f8: 9305 str r3, [sp, #20]
  15827. 800b9fa: 4688 mov r8, r1
  15828. 800b9fc: f898 2000 ldrb.w r2, [r8]
  15829. 800ba00: 3101 adds r1, #1
  15830. 800ba02: 3a30 subs r2, #48 ; 0x30
  15831. 800ba04: 2a09 cmp r2, #9
  15832. 800ba06: d903 bls.n 800ba10 <_vfiprintf_r+0x1cc>
  15833. 800ba08: 2b00 cmp r3, #0
  15834. 800ba0a: d0c5 beq.n 800b998 <_vfiprintf_r+0x154>
  15835. 800ba0c: 9005 str r0, [sp, #20]
  15836. 800ba0e: e7c3 b.n 800b998 <_vfiprintf_r+0x154>
  15837. 800ba10: fb05 2000 mla r0, r5, r0, r2
  15838. 800ba14: 2301 movs r3, #1
  15839. 800ba16: e7f0 b.n 800b9fa <_vfiprintf_r+0x1b6>
  15840. 800ba18: ab03 add r3, sp, #12
  15841. 800ba1a: 9300 str r3, [sp, #0]
  15842. 800ba1c: 4622 mov r2, r4
  15843. 800ba1e: 4b13 ldr r3, [pc, #76] ; (800ba6c <_vfiprintf_r+0x228>)
  15844. 800ba20: a904 add r1, sp, #16
  15845. 800ba22: 4630 mov r0, r6
  15846. 800ba24: f7fd fd36 bl 8009494 <_printf_float>
  15847. 800ba28: f1b0 3fff cmp.w r0, #4294967295
  15848. 800ba2c: 4681 mov r9, r0
  15849. 800ba2e: d1d8 bne.n 800b9e2 <_vfiprintf_r+0x19e>
  15850. 800ba30: 89a3 ldrh r3, [r4, #12]
  15851. 800ba32: 065b lsls r3, r3, #25
  15852. 800ba34: f53f af7d bmi.w 800b932 <_vfiprintf_r+0xee>
  15853. 800ba38: 9809 ldr r0, [sp, #36] ; 0x24
  15854. 800ba3a: e77c b.n 800b936 <_vfiprintf_r+0xf2>
  15855. 800ba3c: ab03 add r3, sp, #12
  15856. 800ba3e: 9300 str r3, [sp, #0]
  15857. 800ba40: 4622 mov r2, r4
  15858. 800ba42: 4b0a ldr r3, [pc, #40] ; (800ba6c <_vfiprintf_r+0x228>)
  15859. 800ba44: a904 add r1, sp, #16
  15860. 800ba46: 4630 mov r0, r6
  15861. 800ba48: f7fd ffd4 bl 80099f4 <_printf_i>
  15862. 800ba4c: e7ec b.n 800ba28 <_vfiprintf_r+0x1e4>
  15863. 800ba4e: bf00 nop
  15864. 800ba50: 0800bd80 .word 0x0800bd80
  15865. 800ba54: 0800bebc .word 0x0800bebc
  15866. 800ba58: 0800bda0 .word 0x0800bda0
  15867. 800ba5c: 0800bd60 .word 0x0800bd60
  15868. 800ba60: 0800bec2 .word 0x0800bec2
  15869. 800ba64: 0800bec6 .word 0x0800bec6
  15870. 800ba68: 08009495 .word 0x08009495
  15871. 800ba6c: 0800b821 .word 0x0800b821
  15872. 0800ba70 <_sbrk_r>:
  15873. 800ba70: b538 push {r3, r4, r5, lr}
  15874. 800ba72: 2300 movs r3, #0
  15875. 800ba74: 4c05 ldr r4, [pc, #20] ; (800ba8c <_sbrk_r+0x1c>)
  15876. 800ba76: 4605 mov r5, r0
  15877. 800ba78: 4608 mov r0, r1
  15878. 800ba7a: 6023 str r3, [r4, #0]
  15879. 800ba7c: f7fc fea0 bl 80087c0 <_sbrk>
  15880. 800ba80: 1c43 adds r3, r0, #1
  15881. 800ba82: d102 bne.n 800ba8a <_sbrk_r+0x1a>
  15882. 800ba84: 6823 ldr r3, [r4, #0]
  15883. 800ba86: b103 cbz r3, 800ba8a <_sbrk_r+0x1a>
  15884. 800ba88: 602b str r3, [r5, #0]
  15885. 800ba8a: bd38 pop {r3, r4, r5, pc}
  15886. 800ba8c: 200017a4 .word 0x200017a4
  15887. 0800ba90 <__sread>:
  15888. 800ba90: b510 push {r4, lr}
  15889. 800ba92: 460c mov r4, r1
  15890. 800ba94: f9b1 100e ldrsh.w r1, [r1, #14]
  15891. 800ba98: f000 f8a8 bl 800bbec <_read_r>
  15892. 800ba9c: 2800 cmp r0, #0
  15893. 800ba9e: bfab itete ge
  15894. 800baa0: 6d63 ldrge r3, [r4, #84] ; 0x54
  15895. 800baa2: 89a3 ldrhlt r3, [r4, #12]
  15896. 800baa4: 181b addge r3, r3, r0
  15897. 800baa6: f423 5380 biclt.w r3, r3, #4096 ; 0x1000
  15898. 800baaa: bfac ite ge
  15899. 800baac: 6563 strge r3, [r4, #84] ; 0x54
  15900. 800baae: 81a3 strhlt r3, [r4, #12]
  15901. 800bab0: bd10 pop {r4, pc}
  15902. 0800bab2 <__swrite>:
  15903. 800bab2: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
  15904. 800bab6: 461f mov r7, r3
  15905. 800bab8: 898b ldrh r3, [r1, #12]
  15906. 800baba: 4605 mov r5, r0
  15907. 800babc: 05db lsls r3, r3, #23
  15908. 800babe: 460c mov r4, r1
  15909. 800bac0: 4616 mov r6, r2
  15910. 800bac2: d505 bpl.n 800bad0 <__swrite+0x1e>
  15911. 800bac4: 2302 movs r3, #2
  15912. 800bac6: 2200 movs r2, #0
  15913. 800bac8: f9b1 100e ldrsh.w r1, [r1, #14]
  15914. 800bacc: f000 f868 bl 800bba0 <_lseek_r>
  15915. 800bad0: 89a3 ldrh r3, [r4, #12]
  15916. 800bad2: 4632 mov r2, r6
  15917. 800bad4: f423 5380 bic.w r3, r3, #4096 ; 0x1000
  15918. 800bad8: 81a3 strh r3, [r4, #12]
  15919. 800bada: f9b4 100e ldrsh.w r1, [r4, #14]
  15920. 800bade: 463b mov r3, r7
  15921. 800bae0: 4628 mov r0, r5
  15922. 800bae2: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr}
  15923. 800bae6: f000 b817 b.w 800bb18 <_write_r>
  15924. 0800baea <__sseek>:
  15925. 800baea: b510 push {r4, lr}
  15926. 800baec: 460c mov r4, r1
  15927. 800baee: f9b1 100e ldrsh.w r1, [r1, #14]
  15928. 800baf2: f000 f855 bl 800bba0 <_lseek_r>
  15929. 800baf6: 1c43 adds r3, r0, #1
  15930. 800baf8: 89a3 ldrh r3, [r4, #12]
  15931. 800bafa: bf15 itete ne
  15932. 800bafc: 6560 strne r0, [r4, #84] ; 0x54
  15933. 800bafe: f423 5380 biceq.w r3, r3, #4096 ; 0x1000
  15934. 800bb02: f443 5380 orrne.w r3, r3, #4096 ; 0x1000
  15935. 800bb06: 81a3 strheq r3, [r4, #12]
  15936. 800bb08: bf18 it ne
  15937. 800bb0a: 81a3 strhne r3, [r4, #12]
  15938. 800bb0c: bd10 pop {r4, pc}
  15939. 0800bb0e <__sclose>:
  15940. 800bb0e: f9b1 100e ldrsh.w r1, [r1, #14]
  15941. 800bb12: f000 b813 b.w 800bb3c <_close_r>
  15942. ...
  15943. 0800bb18 <_write_r>:
  15944. 800bb18: b538 push {r3, r4, r5, lr}
  15945. 800bb1a: 4605 mov r5, r0
  15946. 800bb1c: 4608 mov r0, r1
  15947. 800bb1e: 4611 mov r1, r2
  15948. 800bb20: 2200 movs r2, #0
  15949. 800bb22: 4c05 ldr r4, [pc, #20] ; (800bb38 <_write_r+0x20>)
  15950. 800bb24: 6022 str r2, [r4, #0]
  15951. 800bb26: 461a mov r2, r3
  15952. 800bb28: f7fc f99c bl 8007e64 <_write>
  15953. 800bb2c: 1c43 adds r3, r0, #1
  15954. 800bb2e: d102 bne.n 800bb36 <_write_r+0x1e>
  15955. 800bb30: 6823 ldr r3, [r4, #0]
  15956. 800bb32: b103 cbz r3, 800bb36 <_write_r+0x1e>
  15957. 800bb34: 602b str r3, [r5, #0]
  15958. 800bb36: bd38 pop {r3, r4, r5, pc}
  15959. 800bb38: 200017a4 .word 0x200017a4
  15960. 0800bb3c <_close_r>:
  15961. 800bb3c: b538 push {r3, r4, r5, lr}
  15962. 800bb3e: 2300 movs r3, #0
  15963. 800bb40: 4c05 ldr r4, [pc, #20] ; (800bb58 <_close_r+0x1c>)
  15964. 800bb42: 4605 mov r5, r0
  15965. 800bb44: 4608 mov r0, r1
  15966. 800bb46: 6023 str r3, [r4, #0]
  15967. 800bb48: f7fc fe54 bl 80087f4 <_close>
  15968. 800bb4c: 1c43 adds r3, r0, #1
  15969. 800bb4e: d102 bne.n 800bb56 <_close_r+0x1a>
  15970. 800bb50: 6823 ldr r3, [r4, #0]
  15971. 800bb52: b103 cbz r3, 800bb56 <_close_r+0x1a>
  15972. 800bb54: 602b str r3, [r5, #0]
  15973. 800bb56: bd38 pop {r3, r4, r5, pc}
  15974. 800bb58: 200017a4 .word 0x200017a4
  15975. 0800bb5c <_fstat_r>:
  15976. 800bb5c: b538 push {r3, r4, r5, lr}
  15977. 800bb5e: 2300 movs r3, #0
  15978. 800bb60: 4c06 ldr r4, [pc, #24] ; (800bb7c <_fstat_r+0x20>)
  15979. 800bb62: 4605 mov r5, r0
  15980. 800bb64: 4608 mov r0, r1
  15981. 800bb66: 4611 mov r1, r2
  15982. 800bb68: 6023 str r3, [r4, #0]
  15983. 800bb6a: f7fc fe46 bl 80087fa <_fstat>
  15984. 800bb6e: 1c43 adds r3, r0, #1
  15985. 800bb70: d102 bne.n 800bb78 <_fstat_r+0x1c>
  15986. 800bb72: 6823 ldr r3, [r4, #0]
  15987. 800bb74: b103 cbz r3, 800bb78 <_fstat_r+0x1c>
  15988. 800bb76: 602b str r3, [r5, #0]
  15989. 800bb78: bd38 pop {r3, r4, r5, pc}
  15990. 800bb7a: bf00 nop
  15991. 800bb7c: 200017a4 .word 0x200017a4
  15992. 0800bb80 <_isatty_r>:
  15993. 800bb80: b538 push {r3, r4, r5, lr}
  15994. 800bb82: 2300 movs r3, #0
  15995. 800bb84: 4c05 ldr r4, [pc, #20] ; (800bb9c <_isatty_r+0x1c>)
  15996. 800bb86: 4605 mov r5, r0
  15997. 800bb88: 4608 mov r0, r1
  15998. 800bb8a: 6023 str r3, [r4, #0]
  15999. 800bb8c: f7fc fe3a bl 8008804 <_isatty>
  16000. 800bb90: 1c43 adds r3, r0, #1
  16001. 800bb92: d102 bne.n 800bb9a <_isatty_r+0x1a>
  16002. 800bb94: 6823 ldr r3, [r4, #0]
  16003. 800bb96: b103 cbz r3, 800bb9a <_isatty_r+0x1a>
  16004. 800bb98: 602b str r3, [r5, #0]
  16005. 800bb9a: bd38 pop {r3, r4, r5, pc}
  16006. 800bb9c: 200017a4 .word 0x200017a4
  16007. 0800bba0 <_lseek_r>:
  16008. 800bba0: b538 push {r3, r4, r5, lr}
  16009. 800bba2: 4605 mov r5, r0
  16010. 800bba4: 4608 mov r0, r1
  16011. 800bba6: 4611 mov r1, r2
  16012. 800bba8: 2200 movs r2, #0
  16013. 800bbaa: 4c05 ldr r4, [pc, #20] ; (800bbc0 <_lseek_r+0x20>)
  16014. 800bbac: 6022 str r2, [r4, #0]
  16015. 800bbae: 461a mov r2, r3
  16016. 800bbb0: f7fc fe2a bl 8008808 <_lseek>
  16017. 800bbb4: 1c43 adds r3, r0, #1
  16018. 800bbb6: d102 bne.n 800bbbe <_lseek_r+0x1e>
  16019. 800bbb8: 6823 ldr r3, [r4, #0]
  16020. 800bbba: b103 cbz r3, 800bbbe <_lseek_r+0x1e>
  16021. 800bbbc: 602b str r3, [r5, #0]
  16022. 800bbbe: bd38 pop {r3, r4, r5, pc}
  16023. 800bbc0: 200017a4 .word 0x200017a4
  16024. 0800bbc4 <__ascii_mbtowc>:
  16025. 800bbc4: b082 sub sp, #8
  16026. 800bbc6: b901 cbnz r1, 800bbca <__ascii_mbtowc+0x6>
  16027. 800bbc8: a901 add r1, sp, #4
  16028. 800bbca: b142 cbz r2, 800bbde <__ascii_mbtowc+0x1a>
  16029. 800bbcc: b14b cbz r3, 800bbe2 <__ascii_mbtowc+0x1e>
  16030. 800bbce: 7813 ldrb r3, [r2, #0]
  16031. 800bbd0: 600b str r3, [r1, #0]
  16032. 800bbd2: 7812 ldrb r2, [r2, #0]
  16033. 800bbd4: 1c10 adds r0, r2, #0
  16034. 800bbd6: bf18 it ne
  16035. 800bbd8: 2001 movne r0, #1
  16036. 800bbda: b002 add sp, #8
  16037. 800bbdc: 4770 bx lr
  16038. 800bbde: 4610 mov r0, r2
  16039. 800bbe0: e7fb b.n 800bbda <__ascii_mbtowc+0x16>
  16040. 800bbe2: f06f 0001 mvn.w r0, #1
  16041. 800bbe6: e7f8 b.n 800bbda <__ascii_mbtowc+0x16>
  16042. 0800bbe8 <__malloc_lock>:
  16043. 800bbe8: 4770 bx lr
  16044. 0800bbea <__malloc_unlock>:
  16045. 800bbea: 4770 bx lr
  16046. 0800bbec <_read_r>:
  16047. 800bbec: b538 push {r3, r4, r5, lr}
  16048. 800bbee: 4605 mov r5, r0
  16049. 800bbf0: 4608 mov r0, r1
  16050. 800bbf2: 4611 mov r1, r2
  16051. 800bbf4: 2200 movs r2, #0
  16052. 800bbf6: 4c05 ldr r4, [pc, #20] ; (800bc0c <_read_r+0x20>)
  16053. 800bbf8: 6022 str r2, [r4, #0]
  16054. 800bbfa: 461a mov r2, r3
  16055. 800bbfc: f7fc fdd2 bl 80087a4 <_read>
  16056. 800bc00: 1c43 adds r3, r0, #1
  16057. 800bc02: d102 bne.n 800bc0a <_read_r+0x1e>
  16058. 800bc04: 6823 ldr r3, [r4, #0]
  16059. 800bc06: b103 cbz r3, 800bc0a <_read_r+0x1e>
  16060. 800bc08: 602b str r3, [r5, #0]
  16061. 800bc0a: bd38 pop {r3, r4, r5, pc}
  16062. 800bc0c: 200017a4 .word 0x200017a4
  16063. 0800bc10 <__ascii_wctomb>:
  16064. 800bc10: b149 cbz r1, 800bc26 <__ascii_wctomb+0x16>
  16065. 800bc12: 2aff cmp r2, #255 ; 0xff
  16066. 800bc14: bf8b itete hi
  16067. 800bc16: 238a movhi r3, #138 ; 0x8a
  16068. 800bc18: 700a strbls r2, [r1, #0]
  16069. 800bc1a: 6003 strhi r3, [r0, #0]
  16070. 800bc1c: 2001 movls r0, #1
  16071. 800bc1e: bf88 it hi
  16072. 800bc20: f04f 30ff movhi.w r0, #4294967295
  16073. 800bc24: 4770 bx lr
  16074. 800bc26: 4608 mov r0, r1
  16075. 800bc28: 4770 bx lr
  16076. ...
  16077. 0800bc2c <_init>:
  16078. 800bc2c: b5f8 push {r3, r4, r5, r6, r7, lr}
  16079. 800bc2e: bf00 nop
  16080. 800bc30: bcf8 pop {r3, r4, r5, r6, r7}
  16081. 800bc32: bc08 pop {r3}
  16082. 800bc34: 469e mov lr, r3
  16083. 800bc36: 4770 bx lr
  16084. 0800bc38 <_fini>:
  16085. 800bc38: b5f8 push {r3, r4, r5, r6, r7, lr}
  16086. 800bc3a: bf00 nop
  16087. 800bc3c: bcf8 pop {r3, r4, r5, r6, r7}
  16088. 800bc3e: bc08 pop {r3}
  16089. 800bc40: 469e mov lr, r3
  16090. 800bc42: 4770 bx lr