STM32F103_ATTEN_PLL_Zig/Src/zig_operate.c

/*
 * zig_operate.c
 *
 *  Created on: 2019. 7. 26.
 *      Author: parkyj
 */
#include "zig_operate.h"

/* * * * * * * #define Struct* * * * * * * */
PLL_Setting_st Pll_1_8GHz_DL = {
	PLL_CLK_GPIO_Port,
	PLL_CLK_Pin,
	PLL_DATA_GPIO_Port,
	PLL_DATA_Pin,
    PLL_EN_1_8G_DL_GPIO_Port,    
    PLL_EN_1_8G_DL_Pin,
};
PLL_Setting_st Pll_1_8GHz_UL = {
    PLL_CLK_GPIO_Port,
    PLL_CLK_Pin,
    PLL_DATA_GPIO_Port,
    PLL_DATA_Pin,
    PLL_EN_1_8G_UL_GPIO_Port,    
    PLL_EN_1_8G_UL_Pin,
};
PLL_Setting_st Pll_2_1GHz_DL = {
    PLL_CLK_GPIO_Port,
    PLL_CLK_Pin,
    PLL_DATA_GPIO_Port,
    PLL_DATA_Pin,
    PLL_EN_2_1G_DL_GPIO_Port,    
    PLL_EN_2_1G_DL_Pin,
};
PLL_Setting_st Pll_2_1GHz_UL = {
    PLL_CLK_GPIO_Port,
    PLL_CLK_Pin,
    PLL_DATA_GPIO_Port,
    PLL_DATA_Pin,
    PLL_EN_2_1G_UL_GPIO_Port,    
    PLL_EN_2_1G_UL_Pin,
};
/* * * * * * * * NOT YET * * * * * * * */
PLL_Setting_st Pll_3_5GHz_DL = {
    ATT_CLK_3_5G_GPIO_Port,
    ATT_EN_3_5G_Pin,
    PLL_DATA_GPIO_Port,
    PLL_DATA_Pin,
    PLL_EN_2_1G_DL_GPIO_Port,    
    PLL_EN_2_1G_DL_Pin,
};
PLL_Setting_st Pll_3_5GHz_UL = {
    PLL_CLK_GPIO_Port,
    PLL_CLK_Pin,
    PLL_DATA_GPIO_Port,
    PLL_DATA_Pin,
    PLL_EN_2_1G_UL_GPIO_Port,    
    PLL_EN_2_1G_UL_Pin,
};
/* * * * * * * * ATTEN * * * * * * * */    
ATTEN_Setting_st Atten_1_8Ghz_DL1 ={
    ATT_CLK_GPIO_Port,
    ATT_CLK_Pin,
    ATT_DATA_GPIO_Port,
    ATT_DATA_Pin,
    ATT_EN_1_8G_DL1_GPIO_Port,    
    ATT_EN_1_8G_DL1_Pin,
    PATH_EN_1_8G_DL_GPIO_Port,
    PATH_EN_1_8G_DL_Pin,
};

ATTEN_Setting_st Atten_1_8Ghz_DL2 ={
    ATT_CLK_GPIO_Port,
    ATT_CLK_Pin,
    ATT_DATA_GPIO_Port,
    ATT_DATA_Pin,
    ATT_EN_1_8G_DL2_GPIO_Port,    
    ATT_EN_1_8G_DL2_Pin,
    PATH_EN_1_8G_DL_GPIO_Port,
    PATH_EN_1_8G_DL_Pin,    
};
ATTEN_Setting_st Atten_1_8Ghz_UL1 ={
    ATT_CLK_GPIO_Port,
    ATT_CLK_Pin,
    ATT_DATA_GPIO_Port,
    ATT_DATA_Pin,
    ATT_EN_1_8G_UL1_GPIO_Port,    
    ATT_EN_1_8G_UL1_Pin,
    PATH_EN_1_8G_UL_GPIO_Port,
    PATH_EN_1_8G_UL_Pin,      
};
ATTEN_Setting_st Atten_1_8Ghz_UL2 ={
    ATT_CLK_GPIO_Port,
    ATT_CLK_Pin,
    ATT_DATA_GPIO_Port,
    ATT_DATA_Pin,
    ATT_EN_1_8G_UL2_GPIO_Port,    
    ATT_EN_1_8G_UL2_Pin,
    PATH_EN_1_8G_UL_GPIO_Port,
    PATH_EN_1_8G_UL_Pin,    
};
ATTEN_Setting_st Atten_1_8Ghz_UL3 ={
    ATT_CLK_GPIO_Port,
    ATT_CLK_Pin,
    ATT_DATA_GPIO_Port,
    ATT_DATA_Pin,
    ATT_EN_1_8G_UL3_GPIO_Port,    
    ATT_EN_1_8G_UL3_Pin,
    PATH_EN_1_8G_UL_GPIO_Port,
    PATH_EN_1_8G_UL_Pin,    
};
ATTEN_Setting_st Atten_1_8Ghz_UL4 ={
    ATT_CLK_GPIO_Port,
    ATT_CLK_Pin,
    ATT_DATA_GPIO_Port,
    ATT_DATA_Pin,
    ATT_EN_1_8G_UL4_GPIO_Port,    
    ATT_EN_1_8G_UL4_Pin,
    PATH_EN_1_8G_UL_GPIO_Port,
    PATH_EN_1_8G_UL_Pin,    
};
ATTEN_Setting_st Atten_2_1Ghz_DL1 ={
    ATT_CLK_GPIO_Port,
    ATT_CLK_Pin,
    ATT_DATA_GPIO_Port,
    ATT_DATA_Pin,
    ATT_EN_2_1G_DL1_GPIO_Port,    
    ATT_EN_2_1G_DL1_Pin,
    PATH_EN_2_1G_DL_GPIO_Port,
    PATH_EN_2_1G_DL_Pin,    
};
ATTEN_Setting_st Atten_2_1Ghz_DL2 ={
    ATT_CLK_GPIO_Port,
    ATT_CLK_Pin,
    ATT_DATA_GPIO_Port,
    ATT_DATA_Pin,
    ATT_EN_2_1G_DL2_GPIO_Port,    
    ATT_EN_2_1G_DL2_Pin,
    PATH_EN_2_1G_DL_GPIO_Port,
    PATH_EN_2_1G_DL_Pin,    
};

ATTEN_Setting_st Atten_2_1Ghz_UL1 ={
    ATT_CLK_GPIO_Port,
    ATT_CLK_Pin,
    ATT_DATA_GPIO_Port,
    ATT_DATA_Pin,
    ATT_EN_2_1G_UL1_GPIO_Port,    
    ATT_EN_2_1G_UL1_Pin,
    PATH_EN_2_1G_UL_GPIO_Port,
    PATH_EN_2_1G_UL_Pin,    
};
ATTEN_Setting_st Atten_2_1Ghz_UL2 ={
    ATT_CLK_GPIO_Port,
    ATT_CLK_Pin,
    ATT_DATA_GPIO_Port,
    ATT_DATA_Pin,
    ATT_EN_2_1G_UL2_GPIO_Port,    
    ATT_EN_2_1G_UL2_Pin,
    PATH_EN_2_1G_UL_GPIO_Port,
    PATH_EN_2_1G_UL_Pin,    
};
ATTEN_Setting_st Atten_2_1Ghz_UL3 ={
    ATT_CLK_GPIO_Port,
    ATT_CLK_Pin,
    ATT_DATA_GPIO_Port,
    ATT_DATA_Pin,
    ATT_EN_2_1G_UL3_GPIO_Port,    
    ATT_EN_2_1G_UL3_Pin,
    PATH_EN_2_1G_UL_GPIO_Port,
    PATH_EN_2_1G_UL_Pin,    
};
ATTEN_Setting_st Atten_2_1Ghz_UL4 ={
    ATT_CLK_GPIO_Port,
    ATT_CLK_Pin,
    ATT_DATA_GPIO_Port,
    ATT_DATA_Pin,
    ATT_EN_2_1G_UL4_GPIO_Port,    
    ATT_EN_2_1G_UL4_Pin,
    PATH_EN_2_1G_UL_GPIO_Port,
    PATH_EN_2_1G_UL_Pin,    
};

uint8_t Prev_data[INDEX__T_SYNC_UL + 1];
bool RF_Data_Check(uint8_t* data_buf){
    bool ret = false;
    bool crcret = STH30_CheckCrc(&data_buf[Type], data_buf[Length], data_buf[data_buf[Crcindex]]);
    if(data_buf[Header] == BLUECELL_HEADER){ /*HEADER CHECK*/
        ret= true;
    }
    if(crcret == true){/*CRC CHECK*/
        ret = true;
    }else{
        ret = false;
        printf("Recv CRC Value : \"%d\"\r\n Create CRC Value : \"%d\"   \r\n",data_buf[data_buf[Crcindex]],STH30_CreateCrc(&data_buf[Type], data_buf[Length]));
    }
    printf("CRC Result : \"%d\"   \r\n",ret);

    return ret;

}
PLL_Setting_st Pll_3_5_H = {
     PLL_CLK_3_5G_GPIO_Port,
     PLL_CLK_3_5G_Pin,
     PLL_DATA_3_5G_GPIO_Port,
     PLL_DATA_3_5G_Pin,
   PLL_EN_3_5G_L_GPIO_Port,    
   PLL_EN_3_5G_L_Pin,
 };
 PLL_Setting_st Pll_3_5_L = {
     PLL_CLK_3_5G_GPIO_Port,
     PLL_CLK_3_5G_Pin,
     PLL_DATA_3_5G_GPIO_Port,
     PLL_DATA_3_5G_Pin,
       PLL_EN_3_5G_H_GPIO_Port,    
       PLL_EN_3_5G_H_Pin,
 };

void RF_Operate(uint8_t* data_buf){
    uint16_t temp_val = 0;

    if(Prev_data[INDEX_ATT_1_8G_DL1] != data_buf[INDEX_ATT_1_8G_DL1]){
        
        printf("\r\nLINE : %d  \r\n",__LINE__);    
        BDA4601_atten_ctrl(BDA4601_1_8G_DL1,(data_buf[INDEX_ATT_1_8G_DL1]));
        Prev_data[INDEX_ATT_1_8G_DL1] = data_buf[INDEX_ATT_1_8G_DL1];
    }
    if(Prev_data[INDEX_ATT_1_8G_DL2] != data_buf[INDEX_ATT_1_8G_DL2]){
        printf("\r\nLINE : %d  \r\n",__LINE__);    
        BDA4601_atten_ctrl(BDA4601_1_8G_DL2,(data_buf[INDEX_ATT_1_8G_DL2]));
        Prev_data[INDEX_ATT_1_8G_DL2] = data_buf[INDEX_ATT_1_8G_DL2];
    }
    if(Prev_data[INDEX_ATT_1_8G_UL1] != data_buf[INDEX_ATT_1_8G_UL1]){
        printf("\r\nLINE : %d  \r\n",__LINE__);    
        BDA4601_atten_ctrl(BDA4601_1_8G_UL1,(data_buf[INDEX_ATT_1_8G_UL1]));
        Prev_data[INDEX_ATT_1_8G_UL1] = data_buf[INDEX_ATT_1_8G_UL1];
    }
    if(Prev_data[INDEX_ATT_1_8G_UL2] != data_buf[INDEX_ATT_1_8G_UL2]){
        printf("\r\nLINE : %d  \r\n",__LINE__);    
        BDA4601_atten_ctrl(BDA4601_1_8G_UL2,(data_buf[INDEX_ATT_1_8G_UL2]));
        Prev_data[INDEX_ATT_1_8G_UL2] = data_buf[INDEX_ATT_1_8G_UL2];

    }
    if(Prev_data[INDEX_ATT_1_8G_UL3] != data_buf[INDEX_ATT_1_8G_UL3]){
        BDA4601_atten_ctrl(BDA4601_1_8G_UL3,(data_buf[INDEX_ATT_1_8G_UL3]));
        Prev_data[INDEX_ATT_1_8G_UL3] = data_buf[INDEX_ATT_1_8G_UL3];

    }
    if(Prev_data[INDEX_ATT_1_8G_UL4] != data_buf[INDEX_ATT_1_8G_UL4]){
        printf("\r\nLINE : %d  \r\n",__LINE__);    
        BDA4601_atten_ctrl(BDA4601_1_8G_UL4,(data_buf[INDEX_ATT_1_8G_UL4]));
        Prev_data[INDEX_ATT_1_8G_UL4] = data_buf[INDEX_ATT_1_8G_UL4];

    }
    if(Prev_data[INDEX_ATT_2_1G_DL1] != data_buf[INDEX_ATT_2_1G_DL1]){
        printf("\r\nLINE : %d  \r\n",__LINE__);    
        BDA4601_atten_ctrl(BDA4601_2_1G_DL1,(data_buf[INDEX_ATT_2_1G_DL1]));
        Prev_data[INDEX_ATT_2_1G_DL1] = data_buf[INDEX_ATT_2_1G_DL1];

    }
    if(Prev_data[INDEX_ATT_2_1G_DL2] != data_buf[INDEX_ATT_2_1G_DL2]){
        printf("\r\nLINE : %d  \r\n",__LINE__);    
        BDA4601_atten_ctrl(BDA4601_2_1G_DL2,(data_buf[INDEX_ATT_2_1G_DL2]));
        Prev_data[INDEX_ATT_2_1G_DL2] = data_buf[INDEX_ATT_2_1G_DL2];

    }
    if(Prev_data[INDEX_ATT_2_1G_UL1] != data_buf[INDEX_ATT_2_1G_UL1]){
        printf("\r\nLINE : %d  \r\n",__LINE__);    
        BDA4601_atten_ctrl(BDA4601_2_1G_UL1,(data_buf[INDEX_ATT_2_1G_UL1]));
        Prev_data[INDEX_ATT_2_1G_UL1] = data_buf[INDEX_ATT_2_1G_UL1];

    }
    if(Prev_data[INDEX_ATT_2_1G_UL2] != data_buf[INDEX_ATT_2_1G_UL2]){
        BDA4601_atten_ctrl(BDA4601_2_1G_UL2,(data_buf[INDEX_ATT_2_1G_UL2]));
        Prev_data[INDEX_ATT_2_1G_UL2] = data_buf[INDEX_ATT_2_1G_UL2];

    }
    if(Prev_data[INDEX_ATT_2_1G_UL3] != data_buf[INDEX_ATT_2_1G_UL3]){
        BDA4601_atten_ctrl(BDA4601_2_1G_UL3,(data_buf[INDEX_ATT_2_1G_UL3]));
        Prev_data[INDEX_ATT_2_1G_UL3] = data_buf[INDEX_ATT_2_1G_UL3];

    }
    if(Prev_data[INDEX_ATT_2_1G_UL4] != data_buf[INDEX_ATT_2_1G_UL4]){
        BDA4601_atten_ctrl(BDA4601_2_1G_UL4,(data_buf[INDEX_ATT_2_1G_UL4]));
        Prev_data[INDEX_ATT_2_1G_UL4] = data_buf[INDEX_ATT_2_1G_UL4];
    }
    if(   (Prev_data[INDEX_ATT_3_5G_DL] != data_buf[INDEX_ATT_3_5G_DL])
        ||(Prev_data[INDEX_ATT_3_5G_UL] != data_buf[INDEX_ATT_3_5G_UL])
        ||(Prev_data[INDEX_ATT_3_5G_COM1] != data_buf[INDEX_ATT_3_5G_COM1])
        ||(Prev_data[INDEX_ATT_3_5G_COM2] != data_buf[INDEX_ATT_3_5G_COM2])
        ||(Prev_data[INDEX_ATT_3_5G_COM3] != data_buf[INDEX_ATT_3_5G_COM3])
    ){
        ALL_ATT_3_5G.data0 = Prev_data[INDEX_ATT_3_5G_DL]   = data_buf[INDEX_ATT_3_5G_DL];
        ALL_ATT_3_5G.data1 = Prev_data[INDEX_ATT_3_5G_UL]   = data_buf[INDEX_ATT_3_5G_UL];
        ALL_ATT_3_5G.data2 = Prev_data[INDEX_ATT_3_5G_COM1] = data_buf[INDEX_ATT_3_5G_COM1];
        ALL_ATT_3_5G.data3 = Prev_data[INDEX_ATT_3_5G_COM2] = data_buf[INDEX_ATT_3_5G_COM2];
        ALL_ATT_3_5G.data4 = Prev_data[INDEX_ATT_3_5G_COM3] = data_buf[INDEX_ATT_3_5G_COM3];
        printf("YJ : data0  : %x \r\n",ALL_ATT_3_5G.data0);
        printf("YJ : data1  : %x \r\n",ALL_ATT_3_5G.data1);
        printf("YJ : data2  : %x \r\n",ALL_ATT_3_5G.data2);
        printf("YJ : data3  : %x \r\n",ALL_ATT_3_5G.data3);
        printf("YJ : data4  : %x \r\n",ALL_ATT_3_5G.data4);
        PE43711_ALL_atten_ctrl(ALL_ATT_3_5G);
    }

    if((Prev_data[INDEX_PLL_1_8G_DL_H] != data_buf[INDEX_PLL_1_8G_DL_H])
        && (Prev_data[INDEX_PLL_1_8G_DL_L] != data_buf[INDEX_PLL_1_8G_DL_L])
    ){
        temp_val = (data_buf[INDEX_PLL_1_8G_DL_H] << 8) | (data_buf[INDEX_PLL_1_8G_DL_L]);
//        printf("INDEX_PLL_1_8G_DL_H : %x \r\n",temp_val);
        ADF4113_Module_Ctrl(ADF4113_1_8G_DL,0x410,halSynSetFreq((temp_val * 1000000) / 10 ),0x9F8092);
    }
    if((Prev_data[INDEX_PLL_1_8G_UL_H] != data_buf[INDEX_PLL_1_8G_UL_H])
        && (Prev_data[INDEX_PLL_1_8G_UL_L] != data_buf[INDEX_PLL_1_8G_UL_L])){
        temp_val = (data_buf[INDEX_PLL_1_8G_UL_H] << 8) | (data_buf[INDEX_PLL_1_8G_UL_L]);
        ADF4113_Module_Ctrl(ADF4113_1_8G_UL,0x410,halSynSetFreq((temp_val * 1000000) / 10),0x9F8092);
    }
    if((Prev_data[INDEX_PLL_2_1G_DL_H] != data_buf[INDEX_PLL_2_1G_DL_H])
        && (Prev_data[INDEX_PLL_2_1G_DL_L] != data_buf[INDEX_PLL_2_1G_DL_L])){
        temp_val = ((data_buf[INDEX_PLL_2_1G_DL_H] << 8) | (data_buf[INDEX_PLL_2_1G_DL_L]));
        printf("data_buf[INDEX_PLL_2_1G_DL_H]  %x \r\ndata_buf[INDEX_PLL_2_1G_DL_L]  temp_val : %x\r\n ",data_buf[INDEX_PLL_2_1G_DL_H],data_buf[INDEX_PLL_2_1G_DL_L],temp_val);
        ADF4113_Module_Ctrl(ADF4113_2_1G_DL,0x410,halSynSetFreq((temp_val * 1000000) / 10),0x9F8092);
    }
    if((Prev_data[INDEX_PLL_2_1G_UL_H] != data_buf[INDEX_PLL_2_1G_UL_H])
        && (Prev_data[INDEX_PLL_2_1G_UL_L] != data_buf[INDEX_PLL_2_1G_UL_L])){
        temp_val = (data_buf[INDEX_PLL_2_1G_UL_H] << 8) | (data_buf[INDEX_PLL_2_1G_UL_L]);
        ADF4113_Module_Ctrl(ADF4113_2_1G_UL,0x410,halSynSetFreq((temp_val * 1000000) / 10),0x9F8092);

    }
    if((Prev_data[INDEX_PLL_3_5G_DL_H] != data_buf[INDEX_PLL_3_5G_DL_H])
        && (Prev_data[INDEX_PLL_3_5G_DL_L] != data_buf[INDEX_PLL_3_5G_DL_L])){
        temp_val = (data_buf[INDEX_PLL_3_5G_DL_H] << 8) | (data_buf[INDEX_PLL_3_5G_DL_L]);
        ADF4153_Module_Ctrl(Pll_3_5_L,ADF4153_Freq_Calc(3465500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING),0x14be81,0x13c2,0x3);
    }
    if((Prev_data[INDEX_PLL_3_5G_UL_H] != data_buf[INDEX_PLL_3_5G_UL_H])
        && (Prev_data[INDEX_PLL_3_5G_UL_L] != data_buf[INDEX_PLL_3_5G_UL_L])){
        temp_val = (data_buf[INDEX_PLL_3_5G_UL_H] << 8) | (data_buf[INDEX_PLL_3_5G_UL_L]);
        ADF4153_Module_Ctrl(Pll_3_5_H,ADF4153_Freq_Calc(3934500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING),0x14be81,0x13c2,0x3);
    }
    if(Prev_data[INDEX_PLL_LD_6_BIT] != data_buf[INDEX_PLL_LD_6_BIT]){

    }
#if 0 // PYJ.2019.07.28_BEGIN -- 
    if(Prev_data[INDEX_DET_1_8G_DL_IN_H] != data_buf[INDEX_DET_1_8G_DL_IN_H]){

    }
    if(Prev_data[INDEX_DET_1_8G_DL_IN_L] != data_buf[INDEX_DET_1_8G_DL_IN_L]){

    }
    if(Prev_data[INDEX_DET_1_8G_DL_OUT_H] != data_buf[INDEX_DET_1_8G_DL_OUT_H]){

    }
    if(Prev_data[INDEX_DET_1_8G_DL_OUT_L] != data_buf[INDEX_DET_1_8G_DL_OUT_L]){

    }
    if(Prev_data[INDEX_DET_1_8G_UL_IN_H] != data_buf[INDEX_DET_1_8G_UL_IN_H]){

    }
    if(Prev_data[INDEX_DET_1_8G_UL_IN_L] != data_buf[INDEX_DET_1_8G_UL_IN_L]){

    }
    if(Prev_data[INDEX_DET_1_8G_UL_OUT_H] != data_buf[INDEX_DET_1_8G_UL_OUT_H]){

    }
    if(Prev_data[INDEX_DET_1_8G_UL_OUT_L] != data_buf[INDEX_DET_1_8G_UL_OUT_L]){

    }
    if(Prev_data[INDEX_DET_2_1G_DL_IN_H] != data_buf[INDEX_DET_2_1G_DL_IN_H]){

    }
    if(Prev_data[INDEX_DET_2_1G_DL_IN_L] != data_buf[INDEX_DET_2_1G_DL_IN_L]){

    }
    if(Prev_data[INDEX_DET_2_1G_DL_OUT_H] != data_buf[INDEX_DET_2_1G_DL_OUT_H]){

    }
    if(Prev_data[INDEX_DET_2_1G_DL_OUT_L] != data_buf[INDEX_DET_2_1G_DL_OUT_L]){

    }
    if(Prev_data[INDEX_DET_2_1G_UL_IN_H] != data_buf[INDEX_DET_2_1G_UL_IN_H]){

    }
    if(Prev_data[INDEX_DET_2_1G_UL_IN_L] != data_buf[INDEX_DET_2_1G_UL_IN_L]){

    }

    if(Prev_data[INDEX_DET_2_1G_UL_OUT_H] != data_buf[INDEX_DET_2_1G_UL_OUT_H]){

    }
    if(Prev_data[INDEX_DET_2_1G_UL_OUT_L] != data_buf[INDEX_DET_2_1G_UL_OUT_L]){

    }
    if(Prev_data[INDEX_DET_3_5G_DL_IN_H] != data_buf[INDEX_DET_3_5G_DL_IN_H]){

    }
    if(Prev_data[INDEX_DET_3_5G_DL_IN_L] != data_buf[INDEX_DET_3_5G_DL_IN_L]){

    }
    if(Prev_data[INDEX_DET_3_5G_DL_OUT_L] != data_buf[INDEX_DET_3_5G_DL_OUT_L]){

    }
    if(Prev_data[INDEX_DET_3_5G_DL_OUT_H] != data_buf[INDEX_DET_3_5G_DL_OUT_H]){

    }
    if(Prev_data[INDEX_DET_3_5G_UL_IN_H] != data_buf[INDEX_DET_3_5G_UL_IN_H]){

    }
    if(Prev_data[INDEX_DET_3_5G_UL_IN_L] != data_buf[INDEX_DET_3_5G_UL_IN_L]){

    }

    if(Prev_data[INDEX_DET_3_5G_UL_OUT_H] != data_buf[INDEX_DET_3_5G_UL_OUT_H]){

    }
    if(Prev_data[INDEX_DET_3_5G_UL_OUT_L] != data_buf[INDEX_DET_3_5G_UL_OUT_L]){

    }
    if(Prev_data[INDEX_RFU_TEMP_H] != data_buf[INDEX_RFU_TEMP_H]){

    }
    if(Prev_data[INDEX_RFU_TEMP_L] != data_buf[INDEX_RFU_TEMP_L]){

    }
    if(Prev_data[INDEX__28V_DET_H] != data_buf[INDEX__28V_DET_H]){

    }
    if(Prev_data[INDEX__28V_DET_L] != data_buf[INDEX__28V_DET_L]){

    }
#endif // PYJ.2019.07.28_END -- 
    if(Prev_data[INDEX_ALARM_AC] != data_buf[INDEX_ALARM_AC]){

    }
    if(Prev_data[INDEX_ALARM_DC] != data_buf[INDEX_ALARM_DC]){

    }
    if(Prev_data[INDEX_PATH_EN_1_8G_DL] != data_buf[INDEX_PATH_EN_1_8G_DL]){
        Power_ON_OFF_Ctrl(INDEX_PATH_EN_1_8G_DL,data_buf[INDEX_PATH_EN_1_8G_DL]);
    }
    if(Prev_data[INDEX_PATH_EN_1_8G_UL] != data_buf[INDEX_PATH_EN_1_8G_UL]){
        Power_ON_OFF_Ctrl(INDEX_PATH_EN_1_8G_UL,data_buf[INDEX_PATH_EN_1_8G_DL]);

    }

    if(Prev_data[INDEX_PATH_EN_2_1G_DL] != data_buf[INDEX_PATH_EN_2_1G_DL]){
        Power_ON_OFF_Ctrl(INDEX_PATH_EN_2_1G_DL,data_buf[INDEX_PATH_EN_1_8G_DL]);

    }
    if(Prev_data[INDEX_PATH_EN_2_1G_UL] != data_buf[INDEX_PATH_EN_2_1G_UL]){
        Power_ON_OFF_Ctrl(INDEX_PATH_EN_2_1G_UL,data_buf[INDEX_PATH_EN_1_8G_DL]);

    }
    if(Prev_data[INDEX_PATH_EN_3_5G_L] != data_buf[INDEX_PATH_EN_3_5G_L]){
        Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_L,data_buf[INDEX_PATH_EN_1_8G_DL]);

    }
    if(Prev_data[INDEX_PATH_EN_3_5G_H] != data_buf[INDEX_PATH_EN_3_5G_H]){
        Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_H,data_buf[INDEX_PATH_EN_1_8G_DL]);

    }
    if(Prev_data[INDEX_PATH_EN_3_5G_DL] != data_buf[INDEX_PATH_EN_3_5G_DL]){
        Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_DL,data_buf[INDEX_PATH_EN_1_8G_DL]);

    }
    if(Prev_data[INDEX_PATH_EN_3_5G_UL] != data_buf[INDEX_PATH_EN_3_5G_UL]){
        Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_UL,data_buf[INDEX_PATH_EN_1_8G_DL]);

    }
    if(Prev_data[INDEX_PLL_ON_OFF_3_5G_H] != data_buf[INDEX_PLL_ON_OFF_3_5G_H]){
        Power_ON_OFF_Ctrl(INDEX_PLL_ON_OFF_3_5G_H,data_buf[INDEX_PATH_EN_1_8G_DL]);

    }
    if(Prev_data[INDEX_PLL_ON_OFF_3_5G_L] != data_buf[INDEX_PLL_ON_OFF_3_5G_L]){
        Power_ON_OFF_Ctrl(INDEX_PLL_ON_OFF_3_5G_L,data_buf[INDEX_PATH_EN_1_8G_DL]);
    }

    if(Prev_data[INDEX_T_SYNC_DL] != data_buf[INDEX_T_SYNC_DL]){
        Prev_data[INDEX_T_SYNC_DL] = data_buf[INDEX_T_SYNC_DL];
    }
    if(Prev_data[INDEX__T_SYNC_DL] != data_buf[INDEX__T_SYNC_DL]){
        Prev_data[INDEX__T_SYNC_DL] = data_buf[INDEX__T_SYNC_DL];
    }
    if(Prev_data[INDEX_T_SYNC_UL] != data_buf[INDEX_T_SYNC_UL]){
        Prev_data[INDEX_T_SYNC_UL] = data_buf[INDEX_T_SYNC_UL];
    }
    if(Prev_data[INDEX__T_SYNC_UL] != data_buf[INDEX__T_SYNC_UL]){
        Prev_data[INDEX__T_SYNC_UL] = data_buf[INDEX__T_SYNC_UL];
        Power_ON_OFF_Ctrl(INDEX__T_SYNC_UL,data_buf[INDEX__T_SYNC_UL]);
    }
}

bool RF_Ctrl_Main(uint8_t* data_buf){
    bool ret = false;
    Bluecell_Prot_t type = data_buf[Type];
    ret = RF_Data_Check(&data_buf[Header]); /* ERROR CHECK */
    if(ret == false)
    return ret;

    
    switch(type){
    case TYPE_BLUECELL_RESET:
#ifdef DEBUG_PRINT // PYJ.2019.07.27_BEGIN -- 
        for(uint8_t i =0 ; i < data_buf[Length] + 6; i++)
            printf("%02x ",data_buf[i]);
        printf("Reset Start \r\n");
#endif // PYJ.2019.07.27_END -- 
        NVIC_SystemReset();
        break;
    case TYPE_BLUECELL_SET:
#ifdef DEBUG_PRINT // PYJ.2019.07.27_BEGIN --     
    printf("TYPE_BLUECELL_SET : ");
    for(uint8_t i =0 ; i < data_buf[Length] - 1; i++)
        printf("%02x ",data_buf[4 + i]);
#endif
        RF_Operate(&data_buf[Header]);
        

//        ADF4153_Freq_Calc(3465500000,40000000,2,5000);
//        ADF4153_Freq_Calc(3993450000,40000000,2,5000);
//        halSynSetFreq(1995000000);
//        halSynSetFreq(1600000000);
//        halSynSetFreq(1455000000);        
        break;
    case TYPE_BLUECELL_GET:
        
        break;
 
        default:
#ifdef DEBUG_PRINT // PYJ.2019.07.27_BEGIN --         
            printf("Function : %s   LINE : %d    type : %d \r\n",__func__,__LINE__,type);
#endif
            break;
    }
    return ret;
}