STM32F103_ATTEN_PLL_Zig/Debug/STM32F103_ATTEN_PLL_Zig.list

STM32F103_ATTEN_PLL_Zig.elf:     file format elf32-littlearm

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .isr_vector   000001e4  08000000  08000000  00010000  2**0
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  1 .text         00001d54  080001e4  080001e4  000101e4  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  2 .rodata       00000038  08001f38  08001f38  00011f38  2**0
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  3 .init_array   00000004  08001f70  08001f70  00011f70  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  4 .fini_array   00000004  08001f74  08001f74  00011f74  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  5 .data         0000000c  20000000  08001f78  00020000  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  6 .bss          0000010c  2000000c  08001f84  0002000c  2**2
                  ALLOC
  7 ._user_heap_stack 00000600  20000118  08001f84  00020118  2**0
                  ALLOC
  8 .ARM.attributes 00000029  00000000  00000000  0002000c  2**0
                  CONTENTS, READONLY
  9 .debug_info   0000fa01  00000000  00000000  00020035  2**0
                  CONTENTS, READONLY, DEBUGGING
 10 .debug_abbrev 00002402  00000000  00000000  0002fa36  2**0
                  CONTENTS, READONLY, DEBUGGING
 11 .debug_loc    00003b1d  00000000  00000000  00031e38  2**0
                  CONTENTS, READONLY, DEBUGGING
 12 .debug_aranges 000006b0  00000000  00000000  00035958  2**3
                  CONTENTS, READONLY, DEBUGGING
 13 .debug_ranges 00000930  00000000  00000000  00036008  2**3
                  CONTENTS, READONLY, DEBUGGING
 14 .debug_line   000049ed  00000000  00000000  00036938  2**0
                  CONTENTS, READONLY, DEBUGGING
 15 .debug_str    0000294a  00000000  00000000  0003b325  2**0
                  CONTENTS, READONLY, DEBUGGING
 16 .comment      0000007c  00000000  00000000  0003dc6f  2**0
                  CONTENTS, READONLY
 17 .debug_frame  000011a0  00000000  00000000  0003dcec  2**2
                  CONTENTS, READONLY, DEBUGGING

Disassembly of section .text:

080001e4 <__do_global_dtors_aux>:
 80001e4:	b510      	push	{r4, lr}
 80001e6:	4c05      	ldr	r4, [pc, #20]	; (80001fc <__do_global_dtors_aux+0x18>)
 80001e8:	7823      	ldrb	r3, [r4, #0]
 80001ea:	b933      	cbnz	r3, 80001fa <__do_global_dtors_aux+0x16>
 80001ec:	4b04      	ldr	r3, [pc, #16]	; (8000200 <__do_global_dtors_aux+0x1c>)
 80001ee:	b113      	cbz	r3, 80001f6 <__do_global_dtors_aux+0x12>
 80001f0:	4804      	ldr	r0, [pc, #16]	; (8000204 <__do_global_dtors_aux+0x20>)
 80001f2:	f3af 8000 	nop.w
 80001f6:	2301      	movs	r3, #1
 80001f8:	7023      	strb	r3, [r4, #0]
 80001fa:	bd10      	pop	{r4, pc}
 80001fc:	2000000c 	.word	0x2000000c
 8000200:	00000000 	.word	0x00000000
 8000204:	08001f20 	.word	0x08001f20

08000208 <frame_dummy>:
 8000208:	b508      	push	{r3, lr}
 800020a:	4b03      	ldr	r3, [pc, #12]	; (8000218 <frame_dummy+0x10>)
 800020c:	b11b      	cbz	r3, 8000216 <frame_dummy+0xe>
 800020e:	4903      	ldr	r1, [pc, #12]	; (800021c <frame_dummy+0x14>)
 8000210:	4803      	ldr	r0, [pc, #12]	; (8000220 <frame_dummy+0x18>)
 8000212:	f3af 8000 	nop.w
 8000216:	bd08      	pop	{r3, pc}
 8000218:	00000000 	.word	0x00000000
 800021c:	20000010 	.word	0x20000010
 8000220:	08001f20 	.word	0x08001f20

08000224 <HAL_InitTick>:
  *       implementation  in user file.
  * @param TickPriority Tick interrupt priority.
  * @retval HAL status
  */
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
 8000224:	b538      	push	{r3, r4, r5, lr}
  /* Configure the SysTick to have interrupt in 1ms time basis*/
  if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
 8000226:	4b0e      	ldr	r3, [pc, #56]	; (8000260 <HAL_InitTick+0x3c>)
{
 8000228:	4605      	mov	r5, r0
  if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
 800022a:	7818      	ldrb	r0, [r3, #0]
 800022c:	f44f 737a 	mov.w	r3, #1000	; 0x3e8
 8000230:	fbb3 f3f0 	udiv	r3, r3, r0
 8000234:	4a0b      	ldr	r2, [pc, #44]	; (8000264 <HAL_InitTick+0x40>)
 8000236:	6810      	ldr	r0, [r2, #0]
 8000238:	fbb0 f0f3 	udiv	r0, r0, r3
 800023c:	f000 fb26 	bl	800088c <HAL_SYSTICK_Config>
 8000240:	4604      	mov	r4, r0
 8000242:	b958      	cbnz	r0, 800025c <HAL_InitTick+0x38>
  {
    return HAL_ERROR;
  }

  /* Configure the SysTick IRQ priority */
  if (TickPriority < (1UL << __NVIC_PRIO_BITS))
 8000244:	2d0f      	cmp	r5, #15
 8000246:	d809      	bhi.n	800025c <HAL_InitTick+0x38>
  {
    HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
 8000248:	4602      	mov	r2, r0
 800024a:	4629      	mov	r1, r5
 800024c:	f04f 30ff 	mov.w	r0, #4294967295
 8000250:	f000 fadc 	bl	800080c <HAL_NVIC_SetPriority>
    uwTickPrio = TickPriority;
 8000254:	4b04      	ldr	r3, [pc, #16]	; (8000268 <HAL_InitTick+0x44>)
 8000256:	4620      	mov	r0, r4
 8000258:	601d      	str	r5, [r3, #0]
 800025a:	bd38      	pop	{r3, r4, r5, pc}
    return HAL_ERROR;
 800025c:	2001      	movs	r0, #1
    return HAL_ERROR;
  }

  /* Return function status */
  return HAL_OK;
}
 800025e:	bd38      	pop	{r3, r4, r5, pc}
 8000260:	20000000 	.word	0x20000000
 8000264:	20000008 	.word	0x20000008
 8000268:	20000004 	.word	0x20000004

0800026c <HAL_Init>:
  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
 800026c:	4a07      	ldr	r2, [pc, #28]	; (800028c <HAL_Init+0x20>)
{
 800026e:	b508      	push	{r3, lr}
  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
 8000270:	6813      	ldr	r3, [r2, #0]
  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
 8000272:	2003      	movs	r0, #3
  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
 8000274:	f043 0310 	orr.w	r3, r3, #16
 8000278:	6013      	str	r3, [r2, #0]
  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
 800027a:	f000 fab5 	bl	80007e8 <HAL_NVIC_SetPriorityGrouping>
  HAL_InitTick(TICK_INT_PRIORITY);
 800027e:	2000      	movs	r0, #0
 8000280:	f7ff ffd0 	bl	8000224 <HAL_InitTick>
  HAL_MspInit();
 8000284:	f001 fcf2 	bl	8001c6c <HAL_MspInit>
}
 8000288:	2000      	movs	r0, #0
 800028a:	bd08      	pop	{r3, pc}
 800028c:	40022000 	.word	0x40022000

08000290 <HAL_IncTick>:
  *      implementations in user file.
  * @retval None
  */
__weak void HAL_IncTick(void)
{
  uwTick += uwTickFreq;
 8000290:	4a03      	ldr	r2, [pc, #12]	; (80002a0 <HAL_IncTick+0x10>)
 8000292:	4b04      	ldr	r3, [pc, #16]	; (80002a4 <HAL_IncTick+0x14>)
 8000294:	6811      	ldr	r1, [r2, #0]
 8000296:	781b      	ldrb	r3, [r3, #0]
 8000298:	440b      	add	r3, r1
 800029a:	6013      	str	r3, [r2, #0]
 800029c:	4770      	bx	lr
 800029e:	bf00      	nop
 80002a0:	20000028 	.word	0x20000028
 80002a4:	20000000 	.word	0x20000000

080002a8 <HAL_GetTick>:
  *       implementations in user file.
  * @retval tick value
  */
__weak uint32_t HAL_GetTick(void)
{
  return uwTick;
 80002a8:	4b01      	ldr	r3, [pc, #4]	; (80002b0 <HAL_GetTick+0x8>)
 80002aa:	6818      	ldr	r0, [r3, #0]
}
 80002ac:	4770      	bx	lr
 80002ae:	bf00      	nop
 80002b0:	20000028 	.word	0x20000028

080002b4 <HAL_ADC_ConvCpltCallback>:
 80002b4:	4770      	bx	lr

080002b6 <ADC_DMAConvCplt>:
  * @retval None
  */
void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
{
  /* Retrieve ADC handle corresponding to current DMA handle */
  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
 80002b6:	6a43      	ldr	r3, [r0, #36]	; 0x24
{
 80002b8:	b510      	push	{r4, lr}
 
  /* Update state machine on conversion status if not in error state */
  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
 80002ba:	6a9a      	ldr	r2, [r3, #40]	; 0x28
 80002bc:	f012 0f50 	tst.w	r2, #80	; 0x50
 80002c0:	d11b      	bne.n	80002fa <ADC_DMAConvCplt+0x44>
  {
    /* Update ADC state machine */
    SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
 80002c2:	6a9a      	ldr	r2, [r3, #40]	; 0x28
 80002c4:	f442 7200 	orr.w	r2, r2, #512	; 0x200
 80002c8:	629a      	str	r2, [r3, #40]	; 0x28
    /* Determine whether any further conversion upcoming on group regular     */
    /* by external trigger, continuous mode or scan sequence on going.        */
    /* Note: On STM32F1 devices, in case of sequencer enabled                 */
    /*       (several ranks selected), end of conversion flag is raised       */
    /*       at the end of the sequence.                                      */
    if(ADC_IS_SOFTWARE_START_REGULAR(hadc)        && 
 80002ca:	681a      	ldr	r2, [r3, #0]
 80002cc:	6892      	ldr	r2, [r2, #8]
 80002ce:	f402 2260 	and.w	r2, r2, #917504	; 0xe0000
 80002d2:	f5b2 2f60 	cmp.w	r2, #917504	; 0xe0000
 80002d6:	d10c      	bne.n	80002f2 <ADC_DMAConvCplt+0x3c>
 80002d8:	68da      	ldr	r2, [r3, #12]
 80002da:	b952      	cbnz	r2, 80002f2 <ADC_DMAConvCplt+0x3c>
       (hadc->Init.ContinuousConvMode == DISABLE)   )
    {
      /* Set ADC state */
      CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);   
 80002dc:	6a9a      	ldr	r2, [r3, #40]	; 0x28
 80002de:	f422 7280 	bic.w	r2, r2, #256	; 0x100
 80002e2:	629a      	str	r2, [r3, #40]	; 0x28
      
      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
 80002e4:	6a9a      	ldr	r2, [r3, #40]	; 0x28
 80002e6:	04d2      	lsls	r2, r2, #19
      {
        SET_BIT(hadc->State, HAL_ADC_STATE_READY);
 80002e8:	bf5e      	ittt	pl
 80002ea:	6a9a      	ldrpl	r2, [r3, #40]	; 0x28
 80002ec:	f042 0201 	orrpl.w	r2, r2, #1
 80002f0:	629a      	strpl	r2, [r3, #40]	; 0x28
      }
    }
    
    /* Conversion complete callback */
    HAL_ADC_ConvCpltCallback(hadc); 
 80002f2:	4618      	mov	r0, r3
 80002f4:	f7ff ffde 	bl	80002b4 <HAL_ADC_ConvCpltCallback>
 80002f8:	bd10      	pop	{r4, pc}
  }
  else
  {
    /* Call DMA error callback */
    hadc->DMA_Handle->XferErrorCallback(hdma);
 80002fa:	6a1b      	ldr	r3, [r3, #32]
  }
}
 80002fc:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
    hadc->DMA_Handle->XferErrorCallback(hdma);
 8000300:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 8000302:	4718      	bx	r3

08000304 <HAL_ADC_ConvHalfCpltCallback>:
 8000304:	4770      	bx	lr

08000306 <ADC_DMAHalfConvCplt>:
  * @brief  DMA half transfer complete callback. 
  * @param  hdma: pointer to DMA handle.
  * @retval None
  */
void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)   
{
 8000306:	b508      	push	{r3, lr}
  /* Retrieve ADC handle corresponding to current DMA handle */
  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
  
  /* Half conversion callback */
  HAL_ADC_ConvHalfCpltCallback(hadc); 
 8000308:	6a40      	ldr	r0, [r0, #36]	; 0x24
 800030a:	f7ff fffb 	bl	8000304 <HAL_ADC_ConvHalfCpltCallback>
 800030e:	bd08      	pop	{r3, pc}

08000310 <HAL_ADC_ErrorCallback>:
{
 8000310:	4770      	bx	lr

08000312 <ADC_DMAError>:
  * @retval None
  */
void ADC_DMAError(DMA_HandleTypeDef *hdma)   
{
  /* Retrieve ADC handle corresponding to current DMA handle */
  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
 8000312:	6a40      	ldr	r0, [r0, #36]	; 0x24
{
 8000314:	b508      	push	{r3, lr}
  
  /* Set ADC state */
  SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
 8000316:	6a83      	ldr	r3, [r0, #40]	; 0x28
 8000318:	f043 0340 	orr.w	r3, r3, #64	; 0x40
 800031c:	6283      	str	r3, [r0, #40]	; 0x28
  
  /* Set ADC error code to DMA error */
  SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
 800031e:	6ac3      	ldr	r3, [r0, #44]	; 0x2c
 8000320:	f043 0304 	orr.w	r3, r3, #4
 8000324:	62c3      	str	r3, [r0, #44]	; 0x2c
  
  /* Error callback */
  HAL_ADC_ErrorCallback(hadc); 
 8000326:	f7ff fff3 	bl	8000310 <HAL_ADC_ErrorCallback>
 800032a:	bd08      	pop	{r3, pc}

0800032c <HAL_ADC_ConfigChannel>:
  __IO uint32_t wait_loop_index = 0U;
 800032c:	2300      	movs	r3, #0
{ 
 800032e:	b573      	push	{r0, r1, r4, r5, r6, lr}
  __IO uint32_t wait_loop_index = 0U;
 8000330:	9301      	str	r3, [sp, #4]
  __HAL_LOCK(hadc);
 8000332:	f890 3024 	ldrb.w	r3, [r0, #36]	; 0x24
 8000336:	2b01      	cmp	r3, #1
 8000338:	d074      	beq.n	8000424 <HAL_ADC_ConfigChannel+0xf8>
 800033a:	2301      	movs	r3, #1
  if (sConfig->Rank < 7U)
 800033c:	684d      	ldr	r5, [r1, #4]
  __HAL_LOCK(hadc);
 800033e:	f880 3024 	strb.w	r3, [r0, #36]	; 0x24
  if (sConfig->Rank < 7U)
 8000342:	2d06      	cmp	r5, #6
 8000344:	6802      	ldr	r2, [r0, #0]
 8000346:	ea4f 0385 	mov.w	r3, r5, lsl #2
 800034a:	680c      	ldr	r4, [r1, #0]
 800034c:	d825      	bhi.n	800039a <HAL_ADC_ConfigChannel+0x6e>
    MODIFY_REG(hadc->Instance->SQR3                        ,
 800034e:	442b      	add	r3, r5
 8000350:	251f      	movs	r5, #31
 8000352:	6b56      	ldr	r6, [r2, #52]	; 0x34
 8000354:	3b05      	subs	r3, #5
 8000356:	409d      	lsls	r5, r3
 8000358:	ea26 0505 	bic.w	r5, r6, r5
 800035c:	fa04 f303 	lsl.w	r3, r4, r3
 8000360:	432b      	orrs	r3, r5
 8000362:	6353      	str	r3, [r2, #52]	; 0x34
  if (sConfig->Channel >= ADC_CHANNEL_10)
 8000364:	2c09      	cmp	r4, #9
 8000366:	ea4f 0344 	mov.w	r3, r4, lsl #1
 800036a:	688d      	ldr	r5, [r1, #8]
 800036c:	d92f      	bls.n	80003ce <HAL_ADC_ConfigChannel+0xa2>
    MODIFY_REG(hadc->Instance->SMPR1                             ,
 800036e:	2607      	movs	r6, #7
 8000370:	4423      	add	r3, r4
 8000372:	68d1      	ldr	r1, [r2, #12]
 8000374:	3b1e      	subs	r3, #30
 8000376:	409e      	lsls	r6, r3
 8000378:	ea21 0106 	bic.w	r1, r1, r6
 800037c:	fa05 f303 	lsl.w	r3, r5, r3
 8000380:	430b      	orrs	r3, r1
 8000382:	60d3      	str	r3, [r2, #12]
  if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
 8000384:	f1a4 0310 	sub.w	r3, r4, #16
 8000388:	2b01      	cmp	r3, #1
 800038a:	d92b      	bls.n	80003e4 <HAL_ADC_ConfigChannel+0xb8>
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
 800038c:	2300      	movs	r3, #0
  __HAL_UNLOCK(hadc);
 800038e:	2200      	movs	r2, #0
 8000390:	f880 2024 	strb.w	r2, [r0, #36]	; 0x24
}
 8000394:	4618      	mov	r0, r3
 8000396:	b002      	add	sp, #8
 8000398:	bd70      	pop	{r4, r5, r6, pc}
  else if (sConfig->Rank < 13U)
 800039a:	2d0c      	cmp	r5, #12
 800039c:	d80b      	bhi.n	80003b6 <HAL_ADC_ConfigChannel+0x8a>
    MODIFY_REG(hadc->Instance->SQR2                        ,
 800039e:	442b      	add	r3, r5
 80003a0:	251f      	movs	r5, #31
 80003a2:	6b16      	ldr	r6, [r2, #48]	; 0x30
 80003a4:	3b23      	subs	r3, #35	; 0x23
 80003a6:	409d      	lsls	r5, r3
 80003a8:	ea26 0505 	bic.w	r5, r6, r5
 80003ac:	fa04 f303 	lsl.w	r3, r4, r3
 80003b0:	432b      	orrs	r3, r5
 80003b2:	6313      	str	r3, [r2, #48]	; 0x30
 80003b4:	e7d6      	b.n	8000364 <HAL_ADC_ConfigChannel+0x38>
    MODIFY_REG(hadc->Instance->SQR1                        ,
 80003b6:	442b      	add	r3, r5
 80003b8:	251f      	movs	r5, #31
 80003ba:	6ad6      	ldr	r6, [r2, #44]	; 0x2c
 80003bc:	3b41      	subs	r3, #65	; 0x41
 80003be:	409d      	lsls	r5, r3
 80003c0:	ea26 0505 	bic.w	r5, r6, r5
 80003c4:	fa04 f303 	lsl.w	r3, r4, r3
 80003c8:	432b      	orrs	r3, r5
 80003ca:	62d3      	str	r3, [r2, #44]	; 0x2c
 80003cc:	e7ca      	b.n	8000364 <HAL_ADC_ConfigChannel+0x38>
    MODIFY_REG(hadc->Instance->SMPR2                             ,
 80003ce:	2607      	movs	r6, #7
 80003d0:	6911      	ldr	r1, [r2, #16]
 80003d2:	4423      	add	r3, r4
 80003d4:	409e      	lsls	r6, r3
 80003d6:	ea21 0106 	bic.w	r1, r1, r6
 80003da:	fa05 f303 	lsl.w	r3, r5, r3
 80003de:	430b      	orrs	r3, r1
 80003e0:	6113      	str	r3, [r2, #16]
 80003e2:	e7cf      	b.n	8000384 <HAL_ADC_ConfigChannel+0x58>
    if (hadc->Instance == ADC1)
 80003e4:	4b10      	ldr	r3, [pc, #64]	; (8000428 <HAL_ADC_ConfigChannel+0xfc>)
 80003e6:	429a      	cmp	r2, r3
 80003e8:	d116      	bne.n	8000418 <HAL_ADC_ConfigChannel+0xec>
      if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET)
 80003ea:	6893      	ldr	r3, [r2, #8]
 80003ec:	021b      	lsls	r3, r3, #8
 80003ee:	d4cd      	bmi.n	800038c <HAL_ADC_ConfigChannel+0x60>
        SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
 80003f0:	6893      	ldr	r3, [r2, #8]
        if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
 80003f2:	2c10      	cmp	r4, #16
        SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
 80003f4:	f443 0300 	orr.w	r3, r3, #8388608	; 0x800000
 80003f8:	6093      	str	r3, [r2, #8]
        if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
 80003fa:	d1c7      	bne.n	800038c <HAL_ADC_ConfigChannel+0x60>
          wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
 80003fc:	4b0b      	ldr	r3, [pc, #44]	; (800042c <HAL_ADC_ConfigChannel+0x100>)
 80003fe:	4a0c      	ldr	r2, [pc, #48]	; (8000430 <HAL_ADC_ConfigChannel+0x104>)
 8000400:	681b      	ldr	r3, [r3, #0]
 8000402:	fbb3 f2f2 	udiv	r2, r3, r2
 8000406:	230a      	movs	r3, #10
 8000408:	4353      	muls	r3, r2
            wait_loop_index--;
 800040a:	9301      	str	r3, [sp, #4]
          while(wait_loop_index != 0U)
 800040c:	9b01      	ldr	r3, [sp, #4]
 800040e:	2b00      	cmp	r3, #0
 8000410:	d0bc      	beq.n	800038c <HAL_ADC_ConfigChannel+0x60>
            wait_loop_index--;
 8000412:	9b01      	ldr	r3, [sp, #4]
 8000414:	3b01      	subs	r3, #1
 8000416:	e7f8      	b.n	800040a <HAL_ADC_ConfigChannel+0xde>
      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
 8000418:	6a83      	ldr	r3, [r0, #40]	; 0x28
 800041a:	f043 0320 	orr.w	r3, r3, #32
 800041e:	6283      	str	r3, [r0, #40]	; 0x28
      tmp_hal_status = HAL_ERROR;
 8000420:	2301      	movs	r3, #1
 8000422:	e7b4      	b.n	800038e <HAL_ADC_ConfigChannel+0x62>
  __HAL_LOCK(hadc);
 8000424:	2302      	movs	r3, #2
 8000426:	e7b5      	b.n	8000394 <HAL_ADC_ConfigChannel+0x68>
 8000428:	40012400 	.word	0x40012400
 800042c:	20000008 	.word	0x20000008
 8000430:	000f4240 	.word	0x000f4240

08000434 <ADC_Enable>:
  __IO uint32_t wait_loop_index = 0U;
 8000434:	2300      	movs	r3, #0
{
 8000436:	b573      	push	{r0, r1, r4, r5, r6, lr}
  __IO uint32_t wait_loop_index = 0U;
 8000438:	9301      	str	r3, [sp, #4]
  if (ADC_IS_ENABLE(hadc) == RESET)
 800043a:	6803      	ldr	r3, [r0, #0]
{
 800043c:	4604      	mov	r4, r0
  if (ADC_IS_ENABLE(hadc) == RESET)
 800043e:	689a      	ldr	r2, [r3, #8]
 8000440:	07d2      	lsls	r2, r2, #31
 8000442:	d502      	bpl.n	800044a <ADC_Enable+0x16>
  return HAL_OK;
 8000444:	2000      	movs	r0, #0
}
 8000446:	b002      	add	sp, #8
 8000448:	bd70      	pop	{r4, r5, r6, pc}
    __HAL_ADC_ENABLE(hadc);
 800044a:	689a      	ldr	r2, [r3, #8]
 800044c:	f042 0201 	orr.w	r2, r2, #1
 8000450:	609a      	str	r2, [r3, #8]
    wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
 8000452:	4b12      	ldr	r3, [pc, #72]	; (800049c <ADC_Enable+0x68>)
 8000454:	4a12      	ldr	r2, [pc, #72]	; (80004a0 <ADC_Enable+0x6c>)
 8000456:	681b      	ldr	r3, [r3, #0]
 8000458:	fbb3 f3f2 	udiv	r3, r3, r2
      wait_loop_index--;
 800045c:	9301      	str	r3, [sp, #4]
    while(wait_loop_index != 0U)
 800045e:	9b01      	ldr	r3, [sp, #4]
 8000460:	b9c3      	cbnz	r3, 8000494 <ADC_Enable+0x60>
    tickstart = HAL_GetTick();
 8000462:	f7ff ff21 	bl	80002a8 <HAL_GetTick>
 8000466:	4606      	mov	r6, r0
    while(ADC_IS_ENABLE(hadc) == RESET)
 8000468:	6823      	ldr	r3, [r4, #0]
 800046a:	689d      	ldr	r5, [r3, #8]
 800046c:	f015 0501 	ands.w	r5, r5, #1
 8000470:	d1e8      	bne.n	8000444 <ADC_Enable+0x10>
      if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
 8000472:	f7ff ff19 	bl	80002a8 <HAL_GetTick>
 8000476:	1b80      	subs	r0, r0, r6
 8000478:	2802      	cmp	r0, #2
 800047a:	d9f5      	bls.n	8000468 <ADC_Enable+0x34>
        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
 800047c:	6aa3      	ldr	r3, [r4, #40]	; 0x28
        __HAL_UNLOCK(hadc);
 800047e:	f884 5024 	strb.w	r5, [r4, #36]	; 0x24
        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
 8000482:	f043 0310 	orr.w	r3, r3, #16
 8000486:	62a3      	str	r3, [r4, #40]	; 0x28
        SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
 8000488:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
        __HAL_UNLOCK(hadc);
 800048a:	2001      	movs	r0, #1
        SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
 800048c:	f043 0301 	orr.w	r3, r3, #1
 8000490:	62e3      	str	r3, [r4, #44]	; 0x2c
 8000492:	e7d8      	b.n	8000446 <ADC_Enable+0x12>
      wait_loop_index--;
 8000494:	9b01      	ldr	r3, [sp, #4]
 8000496:	3b01      	subs	r3, #1
 8000498:	e7e0      	b.n	800045c <ADC_Enable+0x28>
 800049a:	bf00      	nop
 800049c:	20000008 	.word	0x20000008
 80004a0:	000f4240 	.word	0x000f4240

080004a4 <HAL_ADC_Start_DMA>:
{
 80004a4:	e92d 41d8 	stmdb	sp!, {r3, r4, r6, r7, r8, lr}
 80004a8:	4690      	mov	r8, r2
  if(ADC_MULTIMODE_IS_ENABLE(hadc) == RESET)
 80004aa:	4b40      	ldr	r3, [pc, #256]	; (80005ac <HAL_ADC_Start_DMA+0x108>)
 80004ac:	6802      	ldr	r2, [r0, #0]
{
 80004ae:	4604      	mov	r4, r0
  if(ADC_MULTIMODE_IS_ENABLE(hadc) == RESET)
 80004b0:	429a      	cmp	r2, r3
{
 80004b2:	460f      	mov	r7, r1
  if(ADC_MULTIMODE_IS_ENABLE(hadc) == RESET)
 80004b4:	d002      	beq.n	80004bc <HAL_ADC_Start_DMA+0x18>
 80004b6:	493e      	ldr	r1, [pc, #248]	; (80005b0 <HAL_ADC_Start_DMA+0x10c>)
 80004b8:	428a      	cmp	r2, r1
 80004ba:	d103      	bne.n	80004c4 <HAL_ADC_Start_DMA+0x20>
 80004bc:	685b      	ldr	r3, [r3, #4]
 80004be:	f413 2f70 	tst.w	r3, #983040	; 0xf0000
 80004c2:	d16e      	bne.n	80005a2 <HAL_ADC_Start_DMA+0xfe>
    __HAL_LOCK(hadc);
 80004c4:	f894 3024 	ldrb.w	r3, [r4, #36]	; 0x24
 80004c8:	2b01      	cmp	r3, #1
 80004ca:	d06c      	beq.n	80005a6 <HAL_ADC_Start_DMA+0x102>
 80004cc:	2301      	movs	r3, #1
    tmp_hal_status = ADC_Enable(hadc);
 80004ce:	4620      	mov	r0, r4
    __HAL_LOCK(hadc);
 80004d0:	f884 3024 	strb.w	r3, [r4, #36]	; 0x24
    tmp_hal_status = ADC_Enable(hadc);
 80004d4:	f7ff ffae 	bl	8000434 <ADC_Enable>
    if (tmp_hal_status == HAL_OK)
 80004d8:	4606      	mov	r6, r0
 80004da:	2800      	cmp	r0, #0
 80004dc:	d15d      	bne.n	800059a <HAL_ADC_Start_DMA+0xf6>
      ADC_STATE_CLR_SET(hadc->State,
 80004de:	6aa0      	ldr	r0, [r4, #40]	; 0x28
    if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
 80004e0:	6821      	ldr	r1, [r4, #0]
      ADC_STATE_CLR_SET(hadc->State,
 80004e2:	f420 6070 	bic.w	r0, r0, #3840	; 0xf00
    if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
 80004e6:	4b32      	ldr	r3, [pc, #200]	; (80005b0 <HAL_ADC_Start_DMA+0x10c>)
      ADC_STATE_CLR_SET(hadc->State,
 80004e8:	f020 0001 	bic.w	r0, r0, #1
 80004ec:	f440 7080 	orr.w	r0, r0, #256	; 0x100
    if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
 80004f0:	4299      	cmp	r1, r3
      ADC_STATE_CLR_SET(hadc->State,
 80004f2:	62a0      	str	r0, [r4, #40]	; 0x28
    if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
 80004f4:	d104      	bne.n	8000500 <HAL_ADC_Start_DMA+0x5c>
 80004f6:	4a2d      	ldr	r2, [pc, #180]	; (80005ac <HAL_ADC_Start_DMA+0x108>)
 80004f8:	6853      	ldr	r3, [r2, #4]
 80004fa:	f413 2f70 	tst.w	r3, #983040	; 0xf0000
 80004fe:	d13e      	bne.n	800057e <HAL_ADC_Start_DMA+0xda>
      CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
 8000500:	6aa3      	ldr	r3, [r4, #40]	; 0x28
 8000502:	f423 1380 	bic.w	r3, r3, #1048576	; 0x100000
 8000506:	62a3      	str	r3, [r4, #40]	; 0x28
      if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
 8000508:	684b      	ldr	r3, [r1, #4]
 800050a:	055a      	lsls	r2, r3, #21
 800050c:	d505      	bpl.n	800051a <HAL_ADC_Start_DMA+0x76>
        ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);  
 800050e:	6aa3      	ldr	r3, [r4, #40]	; 0x28
 8000510:	f423 5340 	bic.w	r3, r3, #12288	; 0x3000
 8000514:	f443 5380 	orr.w	r3, r3, #4096	; 0x1000
 8000518:	62a3      	str	r3, [r4, #40]	; 0x28
      if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
 800051a:	6aa3      	ldr	r3, [r4, #40]	; 0x28
      hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
 800051c:	6a20      	ldr	r0, [r4, #32]
      if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
 800051e:	f413 5380 	ands.w	r3, r3, #4096	; 0x1000
        CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));         
 8000522:	bf18      	it	ne
 8000524:	6ae3      	ldrne	r3, [r4, #44]	; 0x2c
      HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
 8000526:	463a      	mov	r2, r7
        CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));         
 8000528:	bf18      	it	ne
 800052a:	f023 0306 	bicne.w	r3, r3, #6
        ADC_CLEAR_ERRORCODE(hadc);
 800052e:	62e3      	str	r3, [r4, #44]	; 0x2c
      __HAL_UNLOCK(hadc);
 8000530:	2300      	movs	r3, #0
 8000532:	f884 3024 	strb.w	r3, [r4, #36]	; 0x24
      hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
 8000536:	4b1f      	ldr	r3, [pc, #124]	; (80005b4 <HAL_ADC_Start_DMA+0x110>)
      HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
 8000538:	314c      	adds	r1, #76	; 0x4c
      hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
 800053a:	6283      	str	r3, [r0, #40]	; 0x28
      hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
 800053c:	4b1e      	ldr	r3, [pc, #120]	; (80005b8 <HAL_ADC_Start_DMA+0x114>)
 800053e:	62c3      	str	r3, [r0, #44]	; 0x2c
      hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
 8000540:	4b1e      	ldr	r3, [pc, #120]	; (80005bc <HAL_ADC_Start_DMA+0x118>)
 8000542:	6303      	str	r3, [r0, #48]	; 0x30
      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
 8000544:	f06f 0302 	mvn.w	r3, #2
 8000548:	f841 3c4c 	str.w	r3, [r1, #-76]
      SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA);
 800054c:	f851 3c44 	ldr.w	r3, [r1, #-68]
 8000550:	f443 7380 	orr.w	r3, r3, #256	; 0x100
 8000554:	f841 3c44 	str.w	r3, [r1, #-68]
      HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
 8000558:	4643      	mov	r3, r8
 800055a:	f000 f9ed 	bl	8000938 <HAL_DMA_Start_IT>
      if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
 800055e:	6823      	ldr	r3, [r4, #0]
 8000560:	689a      	ldr	r2, [r3, #8]
 8000562:	f402 2260 	and.w	r2, r2, #917504	; 0xe0000
 8000566:	f5b2 2f60 	cmp.w	r2, #917504	; 0xe0000
        SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
 800056a:	689a      	ldr	r2, [r3, #8]
 800056c:	bf0c      	ite	eq
 800056e:	f442 02a0 	orreq.w	r2, r2, #5242880	; 0x500000
        SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
 8000572:	f442 1280 	orrne.w	r2, r2, #1048576	; 0x100000
 8000576:	609a      	str	r2, [r3, #8]
}
 8000578:	4630      	mov	r0, r6
 800057a:	e8bd 81d8 	ldmia.w	sp!, {r3, r4, r6, r7, r8, pc}
      SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
 800057e:	6aa3      	ldr	r3, [r4, #40]	; 0x28
 8000580:	f443 1380 	orr.w	r3, r3, #1048576	; 0x100000
 8000584:	62a3      	str	r3, [r4, #40]	; 0x28
      if (ADC_MULTIMODE_AUTO_INJECTED(hadc))
 8000586:	6853      	ldr	r3, [r2, #4]
 8000588:	055b      	lsls	r3, r3, #21
        ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
 800058a:	bf41      	itttt	mi
 800058c:	6aa0      	ldrmi	r0, [r4, #40]	; 0x28
 800058e:	f420 5040 	bicmi.w	r0, r0, #12288	; 0x3000
 8000592:	f440 5080 	orrmi.w	r0, r0, #4096	; 0x1000
 8000596:	62a0      	strmi	r0, [r4, #40]	; 0x28
 8000598:	e7bf      	b.n	800051a <HAL_ADC_Start_DMA+0x76>
      __HAL_UNLOCK(hadc);
 800059a:	2300      	movs	r3, #0
 800059c:	f884 3024 	strb.w	r3, [r4, #36]	; 0x24
 80005a0:	e7ea      	b.n	8000578 <HAL_ADC_Start_DMA+0xd4>
    tmp_hal_status = HAL_ERROR;
 80005a2:	2601      	movs	r6, #1
 80005a4:	e7e8      	b.n	8000578 <HAL_ADC_Start_DMA+0xd4>
    __HAL_LOCK(hadc);
 80005a6:	2602      	movs	r6, #2
 80005a8:	e7e6      	b.n	8000578 <HAL_ADC_Start_DMA+0xd4>
 80005aa:	bf00      	nop
 80005ac:	40012400 	.word	0x40012400
 80005b0:	40012800 	.word	0x40012800
 80005b4:	080002b7 	.word	0x080002b7
 80005b8:	08000307 	.word	0x08000307
 80005bc:	08000313 	.word	0x08000313

080005c0 <ADC_ConversionStop_Disable>:
{
 80005c0:	b538      	push	{r3, r4, r5, lr}
  if (ADC_IS_ENABLE(hadc) != RESET)
 80005c2:	6803      	ldr	r3, [r0, #0]
{
 80005c4:	4604      	mov	r4, r0
  if (ADC_IS_ENABLE(hadc) != RESET)
 80005c6:	689a      	ldr	r2, [r3, #8]
 80005c8:	07d2      	lsls	r2, r2, #31
 80005ca:	d401      	bmi.n	80005d0 <ADC_ConversionStop_Disable+0x10>
  return HAL_OK;
 80005cc:	2000      	movs	r0, #0
 80005ce:	bd38      	pop	{r3, r4, r5, pc}
    __HAL_ADC_DISABLE(hadc);
 80005d0:	689a      	ldr	r2, [r3, #8]
 80005d2:	f022 0201 	bic.w	r2, r2, #1
 80005d6:	609a      	str	r2, [r3, #8]
    tickstart = HAL_GetTick();
 80005d8:	f7ff fe66 	bl	80002a8 <HAL_GetTick>
 80005dc:	4605      	mov	r5, r0
    while(ADC_IS_ENABLE(hadc) != RESET)
 80005de:	6823      	ldr	r3, [r4, #0]
 80005e0:	689b      	ldr	r3, [r3, #8]
 80005e2:	07db      	lsls	r3, r3, #31
 80005e4:	d5f2      	bpl.n	80005cc <ADC_ConversionStop_Disable+0xc>
      if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
 80005e6:	f7ff fe5f 	bl	80002a8 <HAL_GetTick>
 80005ea:	1b40      	subs	r0, r0, r5
 80005ec:	2802      	cmp	r0, #2
 80005ee:	d9f6      	bls.n	80005de <ADC_ConversionStop_Disable+0x1e>
        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
 80005f0:	6aa3      	ldr	r3, [r4, #40]	; 0x28
        SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
 80005f2:	2001      	movs	r0, #1
        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
 80005f4:	f043 0310 	orr.w	r3, r3, #16
 80005f8:	62a3      	str	r3, [r4, #40]	; 0x28
        SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
 80005fa:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
 80005fc:	f043 0301 	orr.w	r3, r3, #1
 8000600:	62e3      	str	r3, [r4, #44]	; 0x2c
 8000602:	bd38      	pop	{r3, r4, r5, pc}

08000604 <HAL_ADC_Init>:
{
 8000604:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
  if(hadc == NULL)
 8000606:	4604      	mov	r4, r0
 8000608:	2800      	cmp	r0, #0
 800060a:	d077      	beq.n	80006fc <HAL_ADC_Init+0xf8>
  if (hadc->State == HAL_ADC_STATE_RESET)
 800060c:	6a83      	ldr	r3, [r0, #40]	; 0x28
 800060e:	b923      	cbnz	r3, 800061a <HAL_ADC_Init+0x16>
    ADC_CLEAR_ERRORCODE(hadc);
 8000610:	62c3      	str	r3, [r0, #44]	; 0x2c
    hadc->Lock = HAL_UNLOCKED;
 8000612:	f880 3024 	strb.w	r3, [r0, #36]	; 0x24
    HAL_ADC_MspInit(hadc);
 8000616:	f001 fb4b 	bl	8001cb0 <HAL_ADC_MspInit>
  tmp_hal_status = ADC_ConversionStop_Disable(hadc);
 800061a:	4620      	mov	r0, r4
 800061c:	f7ff ffd0 	bl	80005c0 <ADC_ConversionStop_Disable>
  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
 8000620:	6aa3      	ldr	r3, [r4, #40]	; 0x28
 8000622:	f013 0310 	ands.w	r3, r3, #16
 8000626:	d16b      	bne.n	8000700 <HAL_ADC_Init+0xfc>
 8000628:	2800      	cmp	r0, #0
 800062a:	d169      	bne.n	8000700 <HAL_ADC_Init+0xfc>
    ADC_STATE_CLR_SET(hadc->State,
 800062c:	6aa2      	ldr	r2, [r4, #40]	; 0x28
                ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) |
 800062e:	4937      	ldr	r1, [pc, #220]	; (800070c <HAL_ADC_Init+0x108>)
    ADC_STATE_CLR_SET(hadc->State,
 8000630:	f422 5288 	bic.w	r2, r2, #4352	; 0x1100
 8000634:	f022 0202 	bic.w	r2, r2, #2
 8000638:	f042 0202 	orr.w	r2, r2, #2
 800063c:	62a2      	str	r2, [r4, #40]	; 0x28
                ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) |
 800063e:	e894 0024 	ldmia.w	r4, {r2, r5}
 8000642:	428a      	cmp	r2, r1
 8000644:	69e1      	ldr	r1, [r4, #28]
 8000646:	d104      	bne.n	8000652 <HAL_ADC_Init+0x4e>
 8000648:	f5b1 2f40 	cmp.w	r1, #786432	; 0xc0000
 800064c:	bf08      	it	eq
 800064e:	f44f 2100 	moveq.w	r1, #524288	; 0x80000
                ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode)   );
 8000652:	68e6      	ldr	r6, [r4, #12]
                ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) |
 8000654:	ea45 0546 	orr.w	r5, r5, r6, lsl #1
 8000658:	4329      	orrs	r1, r5
    tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode));
 800065a:	68a5      	ldr	r5, [r4, #8]
 800065c:	f5b5 7f80 	cmp.w	r5, #256	; 0x100
 8000660:	d035      	beq.n	80006ce <HAL_ADC_Init+0xca>
 8000662:	2d01      	cmp	r5, #1
 8000664:	bf08      	it	eq
 8000666:	f44f 7380 	moveq.w	r3, #256	; 0x100
    if (hadc->Init.DiscontinuousConvMode == ENABLE)
 800066a:	6967      	ldr	r7, [r4, #20]
 800066c:	2f01      	cmp	r7, #1
 800066e:	d106      	bne.n	800067e <HAL_ADC_Init+0x7a>
      if (hadc->Init.ContinuousConvMode == DISABLE)
 8000670:	bb7e      	cbnz	r6, 80006d2 <HAL_ADC_Init+0xce>
        SET_BIT(tmp_cr1, ADC_CR1_DISCEN                                            |
 8000672:	69a6      	ldr	r6, [r4, #24]
 8000674:	3e01      	subs	r6, #1
 8000676:	ea43 3346 	orr.w	r3, r3, r6, lsl #13
 800067a:	f443 6300 	orr.w	r3, r3, #2048	; 0x800
      MODIFY_REG(hadc->Instance->CR1,
 800067e:	6856      	ldr	r6, [r2, #4]
    if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE)
 8000680:	f5b5 7f80 	cmp.w	r5, #256	; 0x100
      MODIFY_REG(hadc->Instance->CR1,
 8000684:	f426 4669 	bic.w	r6, r6, #59648	; 0xe900
 8000688:	ea43 0306 	orr.w	r3, r3, r6
 800068c:	6053      	str	r3, [r2, #4]
      MODIFY_REG(hadc->Instance->CR2,
 800068e:	6896      	ldr	r6, [r2, #8]
 8000690:	4b1f      	ldr	r3, [pc, #124]	; (8000710 <HAL_ADC_Init+0x10c>)
 8000692:	ea03 0306 	and.w	r3, r3, r6
 8000696:	ea43 0301 	orr.w	r3, r3, r1
 800069a:	6093      	str	r3, [r2, #8]
    if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE)
 800069c:	d001      	beq.n	80006a2 <HAL_ADC_Init+0x9e>
 800069e:	2d01      	cmp	r5, #1
 80006a0:	d120      	bne.n	80006e4 <HAL_ADC_Init+0xe0>
      tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion);
 80006a2:	6923      	ldr	r3, [r4, #16]
 80006a4:	3b01      	subs	r3, #1
 80006a6:	051b      	lsls	r3, r3, #20
    MODIFY_REG(hadc->Instance->SQR1,
 80006a8:	6ad5      	ldr	r5, [r2, #44]	; 0x2c
 80006aa:	f425 0570 	bic.w	r5, r5, #15728640	; 0xf00000
 80006ae:	432b      	orrs	r3, r5
 80006b0:	62d3      	str	r3, [r2, #44]	; 0x2c
    if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
 80006b2:	6892      	ldr	r2, [r2, #8]
 80006b4:	4b17      	ldr	r3, [pc, #92]	; (8000714 <HAL_ADC_Init+0x110>)
 80006b6:	4013      	ands	r3, r2
 80006b8:	4299      	cmp	r1, r3
 80006ba:	d115      	bne.n	80006e8 <HAL_ADC_Init+0xe4>
      ADC_CLEAR_ERRORCODE(hadc);
 80006bc:	2300      	movs	r3, #0
 80006be:	62e3      	str	r3, [r4, #44]	; 0x2c
      ADC_STATE_CLR_SET(hadc->State,
 80006c0:	6aa3      	ldr	r3, [r4, #40]	; 0x28
 80006c2:	f023 0303 	bic.w	r3, r3, #3
 80006c6:	f043 0301 	orr.w	r3, r3, #1
 80006ca:	62a3      	str	r3, [r4, #40]	; 0x28
 80006cc:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode));
 80006ce:	462b      	mov	r3, r5
 80006d0:	e7cb      	b.n	800066a <HAL_ADC_Init+0x66>
        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
 80006d2:	6aa6      	ldr	r6, [r4, #40]	; 0x28
 80006d4:	f046 0620 	orr.w	r6, r6, #32
 80006d8:	62a6      	str	r6, [r4, #40]	; 0x28
        SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
 80006da:	6ae6      	ldr	r6, [r4, #44]	; 0x2c
 80006dc:	f046 0601 	orr.w	r6, r6, #1
 80006e0:	62e6      	str	r6, [r4, #44]	; 0x2c
 80006e2:	e7cc      	b.n	800067e <HAL_ADC_Init+0x7a>
  uint32_t tmp_sqr1 = 0U;
 80006e4:	2300      	movs	r3, #0
 80006e6:	e7df      	b.n	80006a8 <HAL_ADC_Init+0xa4>
      ADC_STATE_CLR_SET(hadc->State,
 80006e8:	6aa3      	ldr	r3, [r4, #40]	; 0x28
 80006ea:	f023 0312 	bic.w	r3, r3, #18
 80006ee:	f043 0310 	orr.w	r3, r3, #16
 80006f2:	62a3      	str	r3, [r4, #40]	; 0x28
      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
 80006f4:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
 80006f6:	f043 0301 	orr.w	r3, r3, #1
 80006fa:	62e3      	str	r3, [r4, #44]	; 0x2c
    return HAL_ERROR;
 80006fc:	2001      	movs	r0, #1
}
 80006fe:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
 8000700:	6aa3      	ldr	r3, [r4, #40]	; 0x28
 8000702:	f043 0310 	orr.w	r3, r3, #16
 8000706:	62a3      	str	r3, [r4, #40]	; 0x28
 8000708:	e7f8      	b.n	80006fc <HAL_ADC_Init+0xf8>
 800070a:	bf00      	nop
 800070c:	40013c00 	.word	0x40013c00
 8000710:	ffe1f7fd 	.word	0xffe1f7fd
 8000714:	ff1f0efe 	.word	0xff1f0efe

08000718 <HAL_ADCEx_Calibration_Start>:
  */
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc)
{
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
  uint32_t tickstart;
  __IO uint32_t wait_loop_index = 0U;
 8000718:	2300      	movs	r3, #0
{
 800071a:	b573      	push	{r0, r1, r4, r5, r6, lr}
  __IO uint32_t wait_loop_index = 0U;
 800071c:	9301      	str	r3, [sp, #4]
  
  /* Check the parameters */
  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));

  /* Process locked */
  __HAL_LOCK(hadc);
 800071e:	f890 3024 	ldrb.w	r3, [r0, #36]	; 0x24
{
 8000722:	4604      	mov	r4, r0
  __HAL_LOCK(hadc);
 8000724:	2b01      	cmp	r3, #1
 8000726:	d05a      	beq.n	80007de <HAL_ADCEx_Calibration_Start+0xc6>
 8000728:	2301      	movs	r3, #1
 800072a:	f880 3024 	strb.w	r3, [r0, #36]	; 0x24
  /* 1. Calibration prerequisite:                                             */
  /*    - ADC must be disabled for at least two ADC clock cycles in disable   */
  /*      mode before ADC enable                                              */
  /* Stop potential conversion on going, on regular and injected groups       */
  /* Disable ADC peripheral */
  tmp_hal_status = ADC_ConversionStop_Disable(hadc);
 800072e:	f7ff ff47 	bl	80005c0 <ADC_ConversionStop_Disable>
  
  /* Check if ADC is effectively disabled */
  if (tmp_hal_status == HAL_OK)
 8000732:	4605      	mov	r5, r0
 8000734:	2800      	cmp	r0, #0
 8000736:	d132      	bne.n	800079e <HAL_ADCEx_Calibration_Start+0x86>
  {
    /* Set ADC state */
    ADC_STATE_CLR_SET(hadc->State,
 8000738:	6aa3      	ldr	r3, [r4, #40]	; 0x28
    
    /* Hardware prerequisite: delay before starting the calibration.          */
    /*  - Computation of CPU clock cycles corresponding to ADC clock cycles.  */
    /*  - Wait for the expected ADC clock cycles delay */
    wait_loop_index = ((SystemCoreClock
                        / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC))
 800073a:	2002      	movs	r0, #2
    ADC_STATE_CLR_SET(hadc->State,
 800073c:	f423 5388 	bic.w	r3, r3, #4352	; 0x1100
 8000740:	f023 0302 	bic.w	r3, r3, #2
 8000744:	f043 0302 	orr.w	r3, r3, #2
 8000748:	62a3      	str	r3, [r4, #40]	; 0x28
                        / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC))
 800074a:	4b26      	ldr	r3, [pc, #152]	; (80007e4 <HAL_ADCEx_Calibration_Start+0xcc>)
 800074c:	681e      	ldr	r6, [r3, #0]
 800074e:	f000 fe7f 	bl	8001450 <HAL_RCCEx_GetPeriphCLKFreq>
 8000752:	fbb6 f0f0 	udiv	r0, r6, r0
                       * ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES        );
 8000756:	0040      	lsls	r0, r0, #1
    wait_loop_index = ((SystemCoreClock
 8000758:	9001      	str	r0, [sp, #4]

    while(wait_loop_index != 0U)
 800075a:	9b01      	ldr	r3, [sp, #4]
 800075c:	bb1b      	cbnz	r3, 80007a6 <HAL_ADCEx_Calibration_Start+0x8e>
    {
      wait_loop_index--;
    }
    
    /* 2. Enable the ADC peripheral */
    ADC_Enable(hadc);
 800075e:	4620      	mov	r0, r4
 8000760:	f7ff fe68 	bl	8000434 <ADC_Enable>
    
    /* 3. Resets ADC calibration registers */  
    SET_BIT(hadc->Instance->CR2, ADC_CR2_RSTCAL);
 8000764:	6822      	ldr	r2, [r4, #0]
 8000766:	6893      	ldr	r3, [r2, #8]
 8000768:	f043 0308 	orr.w	r3, r3, #8
 800076c:	6093      	str	r3, [r2, #8]
    
    tickstart = HAL_GetTick();  
 800076e:	f7ff fd9b 	bl	80002a8 <HAL_GetTick>
 8000772:	4606      	mov	r6, r0

    /* Wait for calibration reset completion */
    while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL))
 8000774:	6823      	ldr	r3, [r4, #0]
 8000776:	689a      	ldr	r2, [r3, #8]
 8000778:	0712      	lsls	r2, r2, #28
 800077a:	d418      	bmi.n	80007ae <HAL_ADCEx_Calibration_Start+0x96>
      }
    }
    
    
    /* 4. Start ADC calibration */
    SET_BIT(hadc->Instance->CR2, ADC_CR2_CAL);
 800077c:	689a      	ldr	r2, [r3, #8]
 800077e:	f042 0204 	orr.w	r2, r2, #4
 8000782:	609a      	str	r2, [r3, #8]
    
    tickstart = HAL_GetTick();  
 8000784:	f7ff fd90 	bl	80002a8 <HAL_GetTick>
 8000788:	4606      	mov	r6, r0

    /* Wait for calibration completion */
    while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL))
 800078a:	6823      	ldr	r3, [r4, #0]
 800078c:	689b      	ldr	r3, [r3, #8]
 800078e:	075b      	lsls	r3, r3, #29
 8000790:	d41f      	bmi.n	80007d2 <HAL_ADCEx_Calibration_Start+0xba>
        return HAL_ERROR;
      }
    }
    
    /* Set ADC state */
    ADC_STATE_CLR_SET(hadc->State,
 8000792:	6aa3      	ldr	r3, [r4, #40]	; 0x28
 8000794:	f023 0303 	bic.w	r3, r3, #3
 8000798:	f043 0301 	orr.w	r3, r3, #1
 800079c:	62a3      	str	r3, [r4, #40]	; 0x28
                      HAL_ADC_STATE_BUSY_INTERNAL,
                      HAL_ADC_STATE_READY);
  }
  
  /* Process unlocked */
  __HAL_UNLOCK(hadc);
 800079e:	2300      	movs	r3, #0
 80007a0:	f884 3024 	strb.w	r3, [r4, #36]	; 0x24
  
  /* Return function status */
  return tmp_hal_status;
 80007a4:	e012      	b.n	80007cc <HAL_ADCEx_Calibration_Start+0xb4>
      wait_loop_index--;
 80007a6:	9b01      	ldr	r3, [sp, #4]
 80007a8:	3b01      	subs	r3, #1
 80007aa:	9301      	str	r3, [sp, #4]
 80007ac:	e7d5      	b.n	800075a <HAL_ADCEx_Calibration_Start+0x42>
      if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
 80007ae:	f7ff fd7b 	bl	80002a8 <HAL_GetTick>
 80007b2:	1b80      	subs	r0, r0, r6
 80007b4:	280a      	cmp	r0, #10
 80007b6:	d9dd      	bls.n	8000774 <HAL_ADCEx_Calibration_Start+0x5c>
        ADC_STATE_CLR_SET(hadc->State,
 80007b8:	6aa3      	ldr	r3, [r4, #40]	; 0x28
        return HAL_ERROR;
 80007ba:	2501      	movs	r5, #1
        ADC_STATE_CLR_SET(hadc->State,
 80007bc:	f023 0312 	bic.w	r3, r3, #18
 80007c0:	f043 0310 	orr.w	r3, r3, #16
 80007c4:	62a3      	str	r3, [r4, #40]	; 0x28
        __HAL_UNLOCK(hadc);
 80007c6:	2300      	movs	r3, #0
 80007c8:	f884 3024 	strb.w	r3, [r4, #36]	; 0x24
}
 80007cc:	4628      	mov	r0, r5
 80007ce:	b002      	add	sp, #8
 80007d0:	bd70      	pop	{r4, r5, r6, pc}
      if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
 80007d2:	f7ff fd69 	bl	80002a8 <HAL_GetTick>
 80007d6:	1b80      	subs	r0, r0, r6
 80007d8:	280a      	cmp	r0, #10
 80007da:	d9d6      	bls.n	800078a <HAL_ADCEx_Calibration_Start+0x72>
 80007dc:	e7ec      	b.n	80007b8 <HAL_ADCEx_Calibration_Start+0xa0>
  __HAL_LOCK(hadc);
 80007de:	2502      	movs	r5, #2
 80007e0:	e7f4      	b.n	80007cc <HAL_ADCEx_Calibration_Start+0xb4>
 80007e2:	bf00      	nop
 80007e4:	20000008 	.word	0x20000008

080007e8 <HAL_NVIC_SetPriorityGrouping>:
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
  uint32_t reg_value;
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */

  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
 80007e8:	4a07      	ldr	r2, [pc, #28]	; (8000808 <HAL_NVIC_SetPriorityGrouping+0x20>)
  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
  reg_value  =  (reg_value                                   |
                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
 80007ea:	0200      	lsls	r0, r0, #8
  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
 80007ec:	68d3      	ldr	r3, [r2, #12]
                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
 80007ee:	f400 60e0 	and.w	r0, r0, #1792	; 0x700
  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
 80007f2:	f423 63e0 	bic.w	r3, r3, #1792	; 0x700
 80007f6:	041b      	lsls	r3, r3, #16
 80007f8:	0c1b      	lsrs	r3, r3, #16
 80007fa:	f043 63bf 	orr.w	r3, r3, #100139008	; 0x5f80000
 80007fe:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
  reg_value  =  (reg_value                                   |
 8000802:	4303      	orrs	r3, r0
  SCB->AIRCR =  reg_value;
 8000804:	60d3      	str	r3, [r2, #12]
 8000806:	4770      	bx	lr
 8000808:	e000ed00 	.word	0xe000ed00

0800080c <HAL_NVIC_SetPriority>:
  \details Reads the priority grouping field from the NVIC Interrupt Controller.
  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
 */
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
{
  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
 800080c:	4b17      	ldr	r3, [pc, #92]	; (800086c <HAL_NVIC_SetPriority+0x60>)
  *         This parameter can be a value between 0 and 15
  *         A lower priority value indicates a higher priority.          
  * @retval None
  */
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{ 
 800080e:	b530      	push	{r4, r5, lr}
 8000810:	68dc      	ldr	r4, [r3, #12]
 8000812:	f3c4 2402 	ubfx	r4, r4, #8, #3
{
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
  uint32_t PreemptPriorityBits;
  uint32_t SubPriorityBits;

  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
 8000816:	f1c4 0307 	rsb	r3, r4, #7
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 800081a:	1d25      	adds	r5, r4, #4
  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
 800081c:	2b04      	cmp	r3, #4
 800081e:	bf28      	it	cs
 8000820:	2304      	movcs	r3, #4
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 8000822:	2d06      	cmp	r5, #6

  return (
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 8000824:	f04f 0501 	mov.w	r5, #1
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 8000828:	bf98      	it	ls
 800082a:	2400      	movls	r4, #0
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 800082c:	fa05 f303 	lsl.w	r3, r5, r3
 8000830:	f103 33ff 	add.w	r3, r3, #4294967295
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 8000834:	bf88      	it	hi
 8000836:	3c03      	subhi	r4, #3
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 8000838:	4019      	ands	r1, r3
 800083a:	40a1      	lsls	r1, r4
           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
 800083c:	fa05 f404 	lsl.w	r4, r5, r4
 8000840:	3c01      	subs	r4, #1
 8000842:	4022      	ands	r2, r4
  if ((int32_t)(IRQn) < 0)
 8000844:	2800      	cmp	r0, #0
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 8000846:	ea42 0201 	orr.w	r2, r2, r1
 800084a:	ea4f 1202 	mov.w	r2, r2, lsl #4
    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 800084e:	bfaf      	iteee	ge
 8000850:	f100 4060 	addge.w	r0, r0, #3758096384	; 0xe0000000
    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8000854:	4b06      	ldrlt	r3, [pc, #24]	; (8000870 <HAL_NVIC_SetPriority+0x64>)
 8000856:	f000 000f 	andlt.w	r0, r0, #15
 800085a:	b2d2      	uxtblt	r2, r2
    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 800085c:	bfa5      	ittet	ge
 800085e:	b2d2      	uxtbge	r2, r2
 8000860:	f500 4061 	addge.w	r0, r0, #57600	; 0xe100
    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8000864:	541a      	strblt	r2, [r3, r0]
    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8000866:	f880 2300 	strbge.w	r2, [r0, #768]	; 0x300
 800086a:	bd30      	pop	{r4, r5, pc}
 800086c:	e000ed00 	.word	0xe000ed00
 8000870:	e000ed14 	.word	0xe000ed14

08000874 <HAL_NVIC_EnableIRQ>:
  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
 8000874:	2301      	movs	r3, #1
 8000876:	0942      	lsrs	r2, r0, #5
 8000878:	f000 001f 	and.w	r0, r0, #31
 800087c:	fa03 f000 	lsl.w	r0, r3, r0
 8000880:	4b01      	ldr	r3, [pc, #4]	; (8000888 <HAL_NVIC_EnableIRQ+0x14>)
 8000882:	f843 0022 	str.w	r0, [r3, r2, lsl #2]
 8000886:	4770      	bx	lr
 8000888:	e000e100 	.word	0xe000e100

0800088c <HAL_SYSTICK_Config>:
           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
           must contain a vendor-specific implementation of this function.
 */
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
 800088c:	3801      	subs	r0, #1
 800088e:	f1b0 7f80 	cmp.w	r0, #16777216	; 0x1000000
 8000892:	d20a      	bcs.n	80008aa <HAL_SYSTICK_Config+0x1e>
    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8000894:	21f0      	movs	r1, #240	; 0xf0
  {
    return (1UL);                                                   /* Reload value impossible */
  }

  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
 8000896:	4b06      	ldr	r3, [pc, #24]	; (80008b0 <HAL_SYSTICK_Config+0x24>)
    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8000898:	4a06      	ldr	r2, [pc, #24]	; (80008b4 <HAL_SYSTICK_Config+0x28>)
  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
 800089a:	6058      	str	r0, [r3, #4]
    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 800089c:	f882 1023 	strb.w	r1, [r2, #35]	; 0x23
  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
 80008a0:	2000      	movs	r0, #0
  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
 80008a2:	2207      	movs	r2, #7
  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
 80008a4:	6098      	str	r0, [r3, #8]
  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
 80008a6:	601a      	str	r2, [r3, #0]
 80008a8:	4770      	bx	lr
    return (1UL);                                                   /* Reload value impossible */
 80008aa:	2001      	movs	r0, #1
  *                  - 1  Function failed.
  */
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
   return SysTick_Config(TicksNumb);
}
 80008ac:	4770      	bx	lr
 80008ae:	bf00      	nop
 80008b0:	e000e010 	.word	0xe000e010
 80008b4:	e000ed00 	.word	0xe000ed00

080008b8 <HAL_DMA_Init>:
  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
  *               the configuration information for the specified DMA Channel.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
{
 80008b8:	b510      	push	{r4, lr}
  uint32_t tmp = 0U;

  /* Check the DMA handle allocation */
  if(hdma == NULL)
 80008ba:	2800      	cmp	r0, #0
 80008bc:	d032      	beq.n	8000924 <HAL_DMA_Init+0x6c>
  assert_param(IS_DMA_MODE(hdma->Init.Mode));
  assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));

#if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F100xE) || defined (STM32F105xC) || defined (STM32F107xC)
  /* calculation of the channel index */
  if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
 80008be:	6801      	ldr	r1, [r0, #0]
 80008c0:	4b19      	ldr	r3, [pc, #100]	; (8000928 <HAL_DMA_Init+0x70>)
 80008c2:	2414      	movs	r4, #20
 80008c4:	4299      	cmp	r1, r3
 80008c6:	d825      	bhi.n	8000914 <HAL_DMA_Init+0x5c>
  {
    /* DMA1 */
    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
 80008c8:	4a18      	ldr	r2, [pc, #96]	; (800092c <HAL_DMA_Init+0x74>)
    hdma->DmaBaseAddress = DMA1;
 80008ca:	f2a3 4307 	subw	r3, r3, #1031	; 0x407
    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
 80008ce:	440a      	add	r2, r1
 80008d0:	fbb2 f2f4 	udiv	r2, r2, r4
 80008d4:	0092      	lsls	r2, r2, #2
 80008d6:	6402      	str	r2, [r0, #64]	; 0x40
  tmp &= ((uint32_t)~(DMA_CCR_PL    | DMA_CCR_MSIZE  | DMA_CCR_PSIZE  | \
                      DMA_CCR_MINC  | DMA_CCR_PINC   | DMA_CCR_CIRC   | \
                      DMA_CCR_DIR));

  /* Prepare the DMA Channel configuration */
  tmp |=  hdma->Init.Direction        |
 80008d8:	6884      	ldr	r4, [r0, #8]
    hdma->DmaBaseAddress = DMA2;
 80008da:	63c3      	str	r3, [r0, #60]	; 0x3c
  tmp |=  hdma->Init.Direction        |
 80008dc:	6843      	ldr	r3, [r0, #4]
  tmp = hdma->Instance->CCR;
 80008de:	680a      	ldr	r2, [r1, #0]
  tmp |=  hdma->Init.Direction        |
 80008e0:	4323      	orrs	r3, r4
          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
 80008e2:	68c4      	ldr	r4, [r0, #12]
  tmp &= ((uint32_t)~(DMA_CCR_PL    | DMA_CCR_MSIZE  | DMA_CCR_PSIZE  | \
 80008e4:	f422 527f 	bic.w	r2, r2, #16320	; 0x3fc0
          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
 80008e8:	4323      	orrs	r3, r4
 80008ea:	6904      	ldr	r4, [r0, #16]
  tmp &= ((uint32_t)~(DMA_CCR_PL    | DMA_CCR_MSIZE  | DMA_CCR_PSIZE  | \
 80008ec:	f022 0230 	bic.w	r2, r2, #48	; 0x30
          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
 80008f0:	4323      	orrs	r3, r4
          hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
 80008f2:	6944      	ldr	r4, [r0, #20]
 80008f4:	4323      	orrs	r3, r4
 80008f6:	6984      	ldr	r4, [r0, #24]
 80008f8:	4323      	orrs	r3, r4
          hdma->Init.Mode                | hdma->Init.Priority;
 80008fa:	69c4      	ldr	r4, [r0, #28]
 80008fc:	4323      	orrs	r3, r4
  tmp |=  hdma->Init.Direction        |
 80008fe:	4313      	orrs	r3, r2

  /* Write to DMA Channel CR register */
  hdma->Instance->CCR = tmp;
 8000900:	600b      	str	r3, [r1, #0]

  /* Initialise the error code */
  hdma->ErrorCode = HAL_DMA_ERROR_NONE;

  /* Initialize the DMA state*/
  hdma->State = HAL_DMA_STATE_READY;
 8000902:	2201      	movs	r2, #1
  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
 8000904:	2300      	movs	r3, #0
  hdma->State = HAL_DMA_STATE_READY;
 8000906:	f880 2021 	strb.w	r2, [r0, #33]	; 0x21
  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
 800090a:	6383      	str	r3, [r0, #56]	; 0x38
  /* Allocate lock resource and initialize it */
  hdma->Lock = HAL_UNLOCKED;
 800090c:	f880 3020 	strb.w	r3, [r0, #32]

  return HAL_OK;
 8000910:	4618      	mov	r0, r3
 8000912:	bd10      	pop	{r4, pc}
    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
 8000914:	4b06      	ldr	r3, [pc, #24]	; (8000930 <HAL_DMA_Init+0x78>)
 8000916:	440b      	add	r3, r1
 8000918:	fbb3 f3f4 	udiv	r3, r3, r4
 800091c:	009b      	lsls	r3, r3, #2
 800091e:	6403      	str	r3, [r0, #64]	; 0x40
    hdma->DmaBaseAddress = DMA2;
 8000920:	4b04      	ldr	r3, [pc, #16]	; (8000934 <HAL_DMA_Init+0x7c>)
 8000922:	e7d9      	b.n	80008d8 <HAL_DMA_Init+0x20>
    return HAL_ERROR;
 8000924:	2001      	movs	r0, #1
}
 8000926:	bd10      	pop	{r4, pc}
 8000928:	40020407 	.word	0x40020407
 800092c:	bffdfff8 	.word	0xbffdfff8
 8000930:	bffdfbf8 	.word	0xbffdfbf8
 8000934:	40020400 	.word	0x40020400

08000938 <HAL_DMA_Start_IT>:
  * @param  DstAddress: The destination memory Buffer address
  * @param  DataLength: The length of data to be transferred from source to destination
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
 8000938:	b5f0      	push	{r4, r5, r6, r7, lr}

  /* Check the parameters */
  assert_param(IS_DMA_BUFFER_SIZE(DataLength));

  /* Process locked */
  __HAL_LOCK(hdma);
 800093a:	f890 4020 	ldrb.w	r4, [r0, #32]
 800093e:	2c01      	cmp	r4, #1
 8000940:	d035      	beq.n	80009ae <HAL_DMA_Start_IT+0x76>
 8000942:	2401      	movs	r4, #1
  
  if(HAL_DMA_STATE_READY == hdma->State)
 8000944:	f890 5021 	ldrb.w	r5, [r0, #33]	; 0x21
  __HAL_LOCK(hdma);
 8000948:	f880 4020 	strb.w	r4, [r0, #32]
  if(HAL_DMA_STATE_READY == hdma->State)
 800094c:	42a5      	cmp	r5, r4
 800094e:	f04f 0600 	mov.w	r6, #0
 8000952:	f04f 0402 	mov.w	r4, #2
 8000956:	d128      	bne.n	80009aa <HAL_DMA_Start_IT+0x72>
  {
    /* Change DMA peripheral state */
    hdma->State = HAL_DMA_STATE_BUSY;
 8000958:	f880 4021 	strb.w	r4, [r0, #33]	; 0x21
    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
    
    /* Disable the peripheral */
    __HAL_DMA_DISABLE(hdma);
 800095c:	6804      	ldr	r4, [r0, #0]
    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
 800095e:	6386      	str	r6, [r0, #56]	; 0x38
    __HAL_DMA_DISABLE(hdma);
 8000960:	6826      	ldr	r6, [r4, #0]
  * @retval HAL status
  */
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
  /* Clear all flags */
  hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
 8000962:	6c07      	ldr	r7, [r0, #64]	; 0x40
    __HAL_DMA_DISABLE(hdma);
 8000964:	f026 0601 	bic.w	r6, r6, #1
 8000968:	6026      	str	r6, [r4, #0]
  hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
 800096a:	6bc6      	ldr	r6, [r0, #60]	; 0x3c
 800096c:	40bd      	lsls	r5, r7
 800096e:	6075      	str	r5, [r6, #4]

  /* Configure DMA Channel data length */
  hdma->Instance->CNDTR = DataLength;
 8000970:	6063      	str	r3, [r4, #4]

  /* Memory to Peripheral */
  if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
 8000972:	6843      	ldr	r3, [r0, #4]
 8000974:	6805      	ldr	r5, [r0, #0]
 8000976:	2b10      	cmp	r3, #16
    if(NULL != hdma->XferHalfCpltCallback)
 8000978:	6ac3      	ldr	r3, [r0, #44]	; 0x2c
  {
    /* Configure DMA Channel destination address */
    hdma->Instance->CPAR = DstAddress;
 800097a:	bf0b      	itete	eq
 800097c:	60a2      	streq	r2, [r4, #8]
  }
  /* Peripheral to Memory */
  else
  {
    /* Configure DMA Channel source address */
    hdma->Instance->CPAR = SrcAddress;
 800097e:	60a1      	strne	r1, [r4, #8]
    hdma->Instance->CMAR = SrcAddress;
 8000980:	60e1      	streq	r1, [r4, #12]

    /* Configure DMA Channel destination address */
    hdma->Instance->CMAR = DstAddress;
 8000982:	60e2      	strne	r2, [r4, #12]
    if(NULL != hdma->XferHalfCpltCallback)
 8000984:	b14b      	cbz	r3, 800099a <HAL_DMA_Start_IT+0x62>
      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
 8000986:	6823      	ldr	r3, [r4, #0]
 8000988:	f043 030e 	orr.w	r3, r3, #14
      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
 800098c:	6023      	str	r3, [r4, #0]
    __HAL_DMA_ENABLE(hdma);
 800098e:	682b      	ldr	r3, [r5, #0]
  HAL_StatusTypeDef status = HAL_OK;
 8000990:	2000      	movs	r0, #0
    __HAL_DMA_ENABLE(hdma);
 8000992:	f043 0301 	orr.w	r3, r3, #1
 8000996:	602b      	str	r3, [r5, #0]
 8000998:	bdf0      	pop	{r4, r5, r6, r7, pc}
      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
 800099a:	6823      	ldr	r3, [r4, #0]
 800099c:	f023 0304 	bic.w	r3, r3, #4
 80009a0:	6023      	str	r3, [r4, #0]
      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
 80009a2:	6823      	ldr	r3, [r4, #0]
 80009a4:	f043 030a 	orr.w	r3, r3, #10
 80009a8:	e7f0      	b.n	800098c <HAL_DMA_Start_IT+0x54>
    __HAL_UNLOCK(hdma); 
 80009aa:	f880 6020 	strb.w	r6, [r0, #32]
  __HAL_LOCK(hdma);
 80009ae:	2002      	movs	r0, #2
}
 80009b0:	bdf0      	pop	{r4, r5, r6, r7, pc}
	...

080009b4 <HAL_DMA_Abort_IT>:
  if(HAL_DMA_STATE_BUSY != hdma->State)
 80009b4:	f890 3021 	ldrb.w	r3, [r0, #33]	; 0x21
{  
 80009b8:	b510      	push	{r4, lr}
  if(HAL_DMA_STATE_BUSY != hdma->State)
 80009ba:	2b02      	cmp	r3, #2
 80009bc:	d003      	beq.n	80009c6 <HAL_DMA_Abort_IT+0x12>
    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
 80009be:	2304      	movs	r3, #4
 80009c0:	6383      	str	r3, [r0, #56]	; 0x38
    status = HAL_ERROR;
 80009c2:	2001      	movs	r0, #1
 80009c4:	bd10      	pop	{r4, pc}
    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
 80009c6:	6803      	ldr	r3, [r0, #0]
 80009c8:	681a      	ldr	r2, [r3, #0]
 80009ca:	f022 020e 	bic.w	r2, r2, #14
 80009ce:	601a      	str	r2, [r3, #0]
    __HAL_DMA_DISABLE(hdma);
 80009d0:	681a      	ldr	r2, [r3, #0]
 80009d2:	f022 0201 	bic.w	r2, r2, #1
 80009d6:	601a      	str	r2, [r3, #0]
    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma));
 80009d8:	4a29      	ldr	r2, [pc, #164]	; (8000a80 <HAL_DMA_Abort_IT+0xcc>)
 80009da:	4293      	cmp	r3, r2
 80009dc:	d924      	bls.n	8000a28 <HAL_DMA_Abort_IT+0x74>
 80009de:	f502 7262 	add.w	r2, r2, #904	; 0x388
 80009e2:	4293      	cmp	r3, r2
 80009e4:	d019      	beq.n	8000a1a <HAL_DMA_Abort_IT+0x66>
 80009e6:	3214      	adds	r2, #20
 80009e8:	4293      	cmp	r3, r2
 80009ea:	d018      	beq.n	8000a1e <HAL_DMA_Abort_IT+0x6a>
 80009ec:	3214      	adds	r2, #20
 80009ee:	4293      	cmp	r3, r2
 80009f0:	d017      	beq.n	8000a22 <HAL_DMA_Abort_IT+0x6e>
 80009f2:	3214      	adds	r2, #20
 80009f4:	4293      	cmp	r3, r2
 80009f6:	bf0c      	ite	eq
 80009f8:	f44f 5380 	moveq.w	r3, #4096	; 0x1000
 80009fc:	f44f 3380 	movne.w	r3, #65536	; 0x10000
 8000a00:	4a20      	ldr	r2, [pc, #128]	; (8000a84 <HAL_DMA_Abort_IT+0xd0>)
 8000a02:	6053      	str	r3, [r2, #4]
    hdma->State = HAL_DMA_STATE_READY;
 8000a04:	2301      	movs	r3, #1
    __HAL_UNLOCK(hdma);
 8000a06:	2400      	movs	r4, #0
    hdma->State = HAL_DMA_STATE_READY;
 8000a08:	f880 3021 	strb.w	r3, [r0, #33]	; 0x21
    if(hdma->XferAbortCallback != NULL)
 8000a0c:	6b43      	ldr	r3, [r0, #52]	; 0x34
    __HAL_UNLOCK(hdma);
 8000a0e:	f880 4020 	strb.w	r4, [r0, #32]
    if(hdma->XferAbortCallback != NULL)
 8000a12:	b39b      	cbz	r3, 8000a7c <HAL_DMA_Abort_IT+0xc8>
      hdma->XferAbortCallback(hdma);
 8000a14:	4798      	blx	r3
  HAL_StatusTypeDef status = HAL_OK;
 8000a16:	4620      	mov	r0, r4
 8000a18:	bd10      	pop	{r4, pc}
    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma));
 8000a1a:	2301      	movs	r3, #1
 8000a1c:	e7f0      	b.n	8000a00 <HAL_DMA_Abort_IT+0x4c>
 8000a1e:	2310      	movs	r3, #16
 8000a20:	e7ee      	b.n	8000a00 <HAL_DMA_Abort_IT+0x4c>
 8000a22:	f44f 7380 	mov.w	r3, #256	; 0x100
 8000a26:	e7eb      	b.n	8000a00 <HAL_DMA_Abort_IT+0x4c>
 8000a28:	4917      	ldr	r1, [pc, #92]	; (8000a88 <HAL_DMA_Abort_IT+0xd4>)
 8000a2a:	428b      	cmp	r3, r1
 8000a2c:	d016      	beq.n	8000a5c <HAL_DMA_Abort_IT+0xa8>
 8000a2e:	3114      	adds	r1, #20
 8000a30:	428b      	cmp	r3, r1
 8000a32:	d015      	beq.n	8000a60 <HAL_DMA_Abort_IT+0xac>
 8000a34:	3114      	adds	r1, #20
 8000a36:	428b      	cmp	r3, r1
 8000a38:	d014      	beq.n	8000a64 <HAL_DMA_Abort_IT+0xb0>
 8000a3a:	3114      	adds	r1, #20
 8000a3c:	428b      	cmp	r3, r1
 8000a3e:	d014      	beq.n	8000a6a <HAL_DMA_Abort_IT+0xb6>
 8000a40:	3114      	adds	r1, #20
 8000a42:	428b      	cmp	r3, r1
 8000a44:	d014      	beq.n	8000a70 <HAL_DMA_Abort_IT+0xbc>
 8000a46:	3114      	adds	r1, #20
 8000a48:	428b      	cmp	r3, r1
 8000a4a:	d014      	beq.n	8000a76 <HAL_DMA_Abort_IT+0xc2>
 8000a4c:	4293      	cmp	r3, r2
 8000a4e:	bf14      	ite	ne
 8000a50:	f44f 3380 	movne.w	r3, #65536	; 0x10000
 8000a54:	f04f 7380 	moveq.w	r3, #16777216	; 0x1000000
 8000a58:	4a0c      	ldr	r2, [pc, #48]	; (8000a8c <HAL_DMA_Abort_IT+0xd8>)
 8000a5a:	e7d2      	b.n	8000a02 <HAL_DMA_Abort_IT+0x4e>
 8000a5c:	2301      	movs	r3, #1
 8000a5e:	e7fb      	b.n	8000a58 <HAL_DMA_Abort_IT+0xa4>
 8000a60:	2310      	movs	r3, #16
 8000a62:	e7f9      	b.n	8000a58 <HAL_DMA_Abort_IT+0xa4>
 8000a64:	f44f 7380 	mov.w	r3, #256	; 0x100
 8000a68:	e7f6      	b.n	8000a58 <HAL_DMA_Abort_IT+0xa4>
 8000a6a:	f44f 5380 	mov.w	r3, #4096	; 0x1000
 8000a6e:	e7f3      	b.n	8000a58 <HAL_DMA_Abort_IT+0xa4>
 8000a70:	f44f 3380 	mov.w	r3, #65536	; 0x10000
 8000a74:	e7f0      	b.n	8000a58 <HAL_DMA_Abort_IT+0xa4>
 8000a76:	f44f 1380 	mov.w	r3, #1048576	; 0x100000
 8000a7a:	e7ed      	b.n	8000a58 <HAL_DMA_Abort_IT+0xa4>
  HAL_StatusTypeDef status = HAL_OK;
 8000a7c:	4618      	mov	r0, r3
}
 8000a7e:	bd10      	pop	{r4, pc}
 8000a80:	40020080 	.word	0x40020080
 8000a84:	40020400 	.word	0x40020400
 8000a88:	40020008 	.word	0x40020008
 8000a8c:	40020000 	.word	0x40020000

08000a90 <HAL_DMA_IRQHandler>:
{
 8000a90:	b470      	push	{r4, r5, r6}
  if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET))
 8000a92:	2504      	movs	r5, #4
  uint32_t flag_it = hdma->DmaBaseAddress->ISR;
 8000a94:	6bc6      	ldr	r6, [r0, #60]	; 0x3c
  if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET))
 8000a96:	6c02      	ldr	r2, [r0, #64]	; 0x40
  uint32_t flag_it = hdma->DmaBaseAddress->ISR;
 8000a98:	6834      	ldr	r4, [r6, #0]
  uint32_t source_it = hdma->Instance->CCR;
 8000a9a:	6803      	ldr	r3, [r0, #0]
  if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET))
 8000a9c:	4095      	lsls	r5, r2
 8000a9e:	4225      	tst	r5, r4
  uint32_t source_it = hdma->Instance->CCR;
 8000aa0:	6819      	ldr	r1, [r3, #0]
  if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET))
 8000aa2:	d055      	beq.n	8000b50 <HAL_DMA_IRQHandler+0xc0>
 8000aa4:	074d      	lsls	r5, r1, #29
 8000aa6:	d553      	bpl.n	8000b50 <HAL_DMA_IRQHandler+0xc0>
    if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
 8000aa8:	681a      	ldr	r2, [r3, #0]
 8000aaa:	0696      	lsls	r6, r2, #26
      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
 8000aac:	bf5e      	ittt	pl
 8000aae:	681a      	ldrpl	r2, [r3, #0]
 8000ab0:	f022 0204 	bicpl.w	r2, r2, #4
 8000ab4:	601a      	strpl	r2, [r3, #0]
    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
 8000ab6:	4a60      	ldr	r2, [pc, #384]	; (8000c38 <HAL_DMA_IRQHandler+0x1a8>)
 8000ab8:	4293      	cmp	r3, r2
 8000aba:	d91f      	bls.n	8000afc <HAL_DMA_IRQHandler+0x6c>
 8000abc:	f502 7262 	add.w	r2, r2, #904	; 0x388
 8000ac0:	4293      	cmp	r3, r2
 8000ac2:	d014      	beq.n	8000aee <HAL_DMA_IRQHandler+0x5e>
 8000ac4:	3214      	adds	r2, #20
 8000ac6:	4293      	cmp	r3, r2
 8000ac8:	d013      	beq.n	8000af2 <HAL_DMA_IRQHandler+0x62>
 8000aca:	3214      	adds	r2, #20
 8000acc:	4293      	cmp	r3, r2
 8000ace:	d012      	beq.n	8000af6 <HAL_DMA_IRQHandler+0x66>
 8000ad0:	3214      	adds	r2, #20
 8000ad2:	4293      	cmp	r3, r2
 8000ad4:	bf0c      	ite	eq
 8000ad6:	f44f 4380 	moveq.w	r3, #16384	; 0x4000
 8000ada:	f44f 2380 	movne.w	r3, #262144	; 0x40000
 8000ade:	4a57      	ldr	r2, [pc, #348]	; (8000c3c <HAL_DMA_IRQHandler+0x1ac>)
 8000ae0:	6053      	str	r3, [r2, #4]
    if(hdma->XferHalfCpltCallback != NULL)
 8000ae2:	6ac3      	ldr	r3, [r0, #44]	; 0x2c
    if (hdma->XferErrorCallback != NULL)
 8000ae4:	2b00      	cmp	r3, #0
 8000ae6:	f000 80a5 	beq.w	8000c34 <HAL_DMA_IRQHandler+0x1a4>
}
 8000aea:	bc70      	pop	{r4, r5, r6}
      hdma->XferErrorCallback(hdma);
 8000aec:	4718      	bx	r3
    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
 8000aee:	2304      	movs	r3, #4
 8000af0:	e7f5      	b.n	8000ade <HAL_DMA_IRQHandler+0x4e>
 8000af2:	2340      	movs	r3, #64	; 0x40
 8000af4:	e7f3      	b.n	8000ade <HAL_DMA_IRQHandler+0x4e>
 8000af6:	f44f 6380 	mov.w	r3, #1024	; 0x400
 8000afa:	e7f0      	b.n	8000ade <HAL_DMA_IRQHandler+0x4e>
 8000afc:	4950      	ldr	r1, [pc, #320]	; (8000c40 <HAL_DMA_IRQHandler+0x1b0>)
 8000afe:	428b      	cmp	r3, r1
 8000b00:	d016      	beq.n	8000b30 <HAL_DMA_IRQHandler+0xa0>
 8000b02:	3114      	adds	r1, #20
 8000b04:	428b      	cmp	r3, r1
 8000b06:	d015      	beq.n	8000b34 <HAL_DMA_IRQHandler+0xa4>
 8000b08:	3114      	adds	r1, #20
 8000b0a:	428b      	cmp	r3, r1
 8000b0c:	d014      	beq.n	8000b38 <HAL_DMA_IRQHandler+0xa8>
 8000b0e:	3114      	adds	r1, #20
 8000b10:	428b      	cmp	r3, r1
 8000b12:	d014      	beq.n	8000b3e <HAL_DMA_IRQHandler+0xae>
 8000b14:	3114      	adds	r1, #20
 8000b16:	428b      	cmp	r3, r1
 8000b18:	d014      	beq.n	8000b44 <HAL_DMA_IRQHandler+0xb4>
 8000b1a:	3114      	adds	r1, #20
 8000b1c:	428b      	cmp	r3, r1
 8000b1e:	d014      	beq.n	8000b4a <HAL_DMA_IRQHandler+0xba>
 8000b20:	4293      	cmp	r3, r2
 8000b22:	bf14      	ite	ne
 8000b24:	f44f 2380 	movne.w	r3, #262144	; 0x40000
 8000b28:	f04f 6380 	moveq.w	r3, #67108864	; 0x4000000
 8000b2c:	4a45      	ldr	r2, [pc, #276]	; (8000c44 <HAL_DMA_IRQHandler+0x1b4>)
 8000b2e:	e7d7      	b.n	8000ae0 <HAL_DMA_IRQHandler+0x50>
 8000b30:	2304      	movs	r3, #4
 8000b32:	e7fb      	b.n	8000b2c <HAL_DMA_IRQHandler+0x9c>
 8000b34:	2340      	movs	r3, #64	; 0x40
 8000b36:	e7f9      	b.n	8000b2c <HAL_DMA_IRQHandler+0x9c>
 8000b38:	f44f 6380 	mov.w	r3, #1024	; 0x400
 8000b3c:	e7f6      	b.n	8000b2c <HAL_DMA_IRQHandler+0x9c>
 8000b3e:	f44f 4380 	mov.w	r3, #16384	; 0x4000
 8000b42:	e7f3      	b.n	8000b2c <HAL_DMA_IRQHandler+0x9c>
 8000b44:	f44f 2380 	mov.w	r3, #262144	; 0x40000
 8000b48:	e7f0      	b.n	8000b2c <HAL_DMA_IRQHandler+0x9c>
 8000b4a:	f44f 0380 	mov.w	r3, #4194304	; 0x400000
 8000b4e:	e7ed      	b.n	8000b2c <HAL_DMA_IRQHandler+0x9c>
  else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET))
 8000b50:	2502      	movs	r5, #2
 8000b52:	4095      	lsls	r5, r2
 8000b54:	4225      	tst	r5, r4
 8000b56:	d057      	beq.n	8000c08 <HAL_DMA_IRQHandler+0x178>
 8000b58:	078d      	lsls	r5, r1, #30
 8000b5a:	d555      	bpl.n	8000c08 <HAL_DMA_IRQHandler+0x178>
    if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
 8000b5c:	681a      	ldr	r2, [r3, #0]
 8000b5e:	0694      	lsls	r4, r2, #26
 8000b60:	d406      	bmi.n	8000b70 <HAL_DMA_IRQHandler+0xe0>
      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);  
 8000b62:	681a      	ldr	r2, [r3, #0]
 8000b64:	f022 020a 	bic.w	r2, r2, #10
 8000b68:	601a      	str	r2, [r3, #0]
      hdma->State = HAL_DMA_STATE_READY;
 8000b6a:	2201      	movs	r2, #1
 8000b6c:	f880 2021 	strb.w	r2, [r0, #33]	; 0x21
      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
 8000b70:	4a31      	ldr	r2, [pc, #196]	; (8000c38 <HAL_DMA_IRQHandler+0x1a8>)
 8000b72:	4293      	cmp	r3, r2
 8000b74:	d91e      	bls.n	8000bb4 <HAL_DMA_IRQHandler+0x124>
 8000b76:	f502 7262 	add.w	r2, r2, #904	; 0x388
 8000b7a:	4293      	cmp	r3, r2
 8000b7c:	d013      	beq.n	8000ba6 <HAL_DMA_IRQHandler+0x116>
 8000b7e:	3214      	adds	r2, #20
 8000b80:	4293      	cmp	r3, r2
 8000b82:	d012      	beq.n	8000baa <HAL_DMA_IRQHandler+0x11a>
 8000b84:	3214      	adds	r2, #20
 8000b86:	4293      	cmp	r3, r2
 8000b88:	d011      	beq.n	8000bae <HAL_DMA_IRQHandler+0x11e>
 8000b8a:	3214      	adds	r2, #20
 8000b8c:	4293      	cmp	r3, r2
 8000b8e:	bf0c      	ite	eq
 8000b90:	f44f 5300 	moveq.w	r3, #8192	; 0x2000
 8000b94:	f44f 3300 	movne.w	r3, #131072	; 0x20000
 8000b98:	4a28      	ldr	r2, [pc, #160]	; (8000c3c <HAL_DMA_IRQHandler+0x1ac>)
 8000b9a:	6053      	str	r3, [r2, #4]
    __HAL_UNLOCK(hdma);
 8000b9c:	2300      	movs	r3, #0
 8000b9e:	f880 3020 	strb.w	r3, [r0, #32]
    if(hdma->XferCpltCallback != NULL)
 8000ba2:	6a83      	ldr	r3, [r0, #40]	; 0x28
 8000ba4:	e79e      	b.n	8000ae4 <HAL_DMA_IRQHandler+0x54>
      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
 8000ba6:	2302      	movs	r3, #2
 8000ba8:	e7f6      	b.n	8000b98 <HAL_DMA_IRQHandler+0x108>
 8000baa:	2320      	movs	r3, #32
 8000bac:	e7f4      	b.n	8000b98 <HAL_DMA_IRQHandler+0x108>
 8000bae:	f44f 7300 	mov.w	r3, #512	; 0x200
 8000bb2:	e7f1      	b.n	8000b98 <HAL_DMA_IRQHandler+0x108>
 8000bb4:	4922      	ldr	r1, [pc, #136]	; (8000c40 <HAL_DMA_IRQHandler+0x1b0>)
 8000bb6:	428b      	cmp	r3, r1
 8000bb8:	d016      	beq.n	8000be8 <HAL_DMA_IRQHandler+0x158>
 8000bba:	3114      	adds	r1, #20
 8000bbc:	428b      	cmp	r3, r1
 8000bbe:	d015      	beq.n	8000bec <HAL_DMA_IRQHandler+0x15c>
 8000bc0:	3114      	adds	r1, #20
 8000bc2:	428b      	cmp	r3, r1
 8000bc4:	d014      	beq.n	8000bf0 <HAL_DMA_IRQHandler+0x160>
 8000bc6:	3114      	adds	r1, #20
 8000bc8:	428b      	cmp	r3, r1
 8000bca:	d014      	beq.n	8000bf6 <HAL_DMA_IRQHandler+0x166>
 8000bcc:	3114      	adds	r1, #20
 8000bce:	428b      	cmp	r3, r1
 8000bd0:	d014      	beq.n	8000bfc <HAL_DMA_IRQHandler+0x16c>
 8000bd2:	3114      	adds	r1, #20
 8000bd4:	428b      	cmp	r3, r1
 8000bd6:	d014      	beq.n	8000c02 <HAL_DMA_IRQHandler+0x172>
 8000bd8:	4293      	cmp	r3, r2
 8000bda:	bf14      	ite	ne
 8000bdc:	f44f 3300 	movne.w	r3, #131072	; 0x20000
 8000be0:	f04f 7300 	moveq.w	r3, #33554432	; 0x2000000
 8000be4:	4a17      	ldr	r2, [pc, #92]	; (8000c44 <HAL_DMA_IRQHandler+0x1b4>)
 8000be6:	e7d8      	b.n	8000b9a <HAL_DMA_IRQHandler+0x10a>
 8000be8:	2302      	movs	r3, #2
 8000bea:	e7fb      	b.n	8000be4 <HAL_DMA_IRQHandler+0x154>
 8000bec:	2320      	movs	r3, #32
 8000bee:	e7f9      	b.n	8000be4 <HAL_DMA_IRQHandler+0x154>
 8000bf0:	f44f 7300 	mov.w	r3, #512	; 0x200
 8000bf4:	e7f6      	b.n	8000be4 <HAL_DMA_IRQHandler+0x154>
 8000bf6:	f44f 5300 	mov.w	r3, #8192	; 0x2000
 8000bfa:	e7f3      	b.n	8000be4 <HAL_DMA_IRQHandler+0x154>
 8000bfc:	f44f 3300 	mov.w	r3, #131072	; 0x20000
 8000c00:	e7f0      	b.n	8000be4 <HAL_DMA_IRQHandler+0x154>
 8000c02:	f44f 1300 	mov.w	r3, #2097152	; 0x200000
 8000c06:	e7ed      	b.n	8000be4 <HAL_DMA_IRQHandler+0x154>
  else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
 8000c08:	2508      	movs	r5, #8
 8000c0a:	4095      	lsls	r5, r2
 8000c0c:	4225      	tst	r5, r4
 8000c0e:	d011      	beq.n	8000c34 <HAL_DMA_IRQHandler+0x1a4>
 8000c10:	0709      	lsls	r1, r1, #28
 8000c12:	d50f      	bpl.n	8000c34 <HAL_DMA_IRQHandler+0x1a4>
    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
 8000c14:	6819      	ldr	r1, [r3, #0]
 8000c16:	f021 010e 	bic.w	r1, r1, #14
 8000c1a:	6019      	str	r1, [r3, #0]
    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
 8000c1c:	2301      	movs	r3, #1
 8000c1e:	fa03 f202 	lsl.w	r2, r3, r2
 8000c22:	6072      	str	r2, [r6, #4]
    hdma->ErrorCode = HAL_DMA_ERROR_TE;
 8000c24:	6383      	str	r3, [r0, #56]	; 0x38
    hdma->State = HAL_DMA_STATE_READY;
 8000c26:	f880 3021 	strb.w	r3, [r0, #33]	; 0x21
    __HAL_UNLOCK(hdma);
 8000c2a:	2300      	movs	r3, #0
 8000c2c:	f880 3020 	strb.w	r3, [r0, #32]
    if (hdma->XferErrorCallback != NULL)
 8000c30:	6b03      	ldr	r3, [r0, #48]	; 0x30
 8000c32:	e757      	b.n	8000ae4 <HAL_DMA_IRQHandler+0x54>
}
 8000c34:	bc70      	pop	{r4, r5, r6}
 8000c36:	4770      	bx	lr
 8000c38:	40020080 	.word	0x40020080
 8000c3c:	40020400 	.word	0x40020400
 8000c40:	40020008 	.word	0x40020008
 8000c44:	40020000 	.word	0x40020000

08000c48 <HAL_GPIO_Init>:
  * @param  GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
  *         the configuration information for the specified GPIO peripheral.
  * @retval None
  */
void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
 8000c48:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
  uint32_t position;
  uint32_t ioposition = 0x00U;
  uint32_t iocurrent = 0x00U;
  uint32_t temp = 0x00U;
  uint32_t config = 0x00U;
 8000c4c:	2200      	movs	r2, #0
  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));

  /* Configure the port pins */
  for (position = 0U; position < GPIO_NUMBER; position++)
 8000c4e:	4616      	mov	r6, r2
      /*--------------------- EXTI Mode Configuration ------------------------*/
      /* Configure the External Interrupt or event for the current IO */
      if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
      {
        /* Enable AFIO Clock */
        __HAL_RCC_AFIO_CLK_ENABLE();
 8000c50:	4f6c      	ldr	r7, [pc, #432]	; (8000e04 <HAL_GPIO_Init+0x1bc>)
 8000c52:	4b6d      	ldr	r3, [pc, #436]	; (8000e08 <HAL_GPIO_Init+0x1c0>)
        temp = AFIO->EXTICR[position >> 2U];
        CLEAR_BIT(temp, (0x0FU) << (4U * (position & 0x03U)));
        SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
 8000c54:	f8df e1b8 	ldr.w	lr, [pc, #440]	; 8000e10 <HAL_GPIO_Init+0x1c8>
      switch (GPIO_Init->Mode)
 8000c58:	f8df c1b8 	ldr.w	ip, [pc, #440]	; 8000e14 <HAL_GPIO_Init+0x1cc>
    ioposition = (0x01U << position);
 8000c5c:	f04f 0801 	mov.w	r8, #1
    iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
 8000c60:	680c      	ldr	r4, [r1, #0]
    ioposition = (0x01U << position);
 8000c62:	fa08 f806 	lsl.w	r8, r8, r6
    iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
 8000c66:	ea08 0404 	and.w	r4, r8, r4
    if (iocurrent == ioposition)
 8000c6a:	45a0      	cmp	r8, r4
 8000c6c:	f040 8085 	bne.w	8000d7a <HAL_GPIO_Init+0x132>
      switch (GPIO_Init->Mode)
 8000c70:	684d      	ldr	r5, [r1, #4]
 8000c72:	2d12      	cmp	r5, #18
 8000c74:	f000 80b7 	beq.w	8000de6 <HAL_GPIO_Init+0x19e>
 8000c78:	f200 808d 	bhi.w	8000d96 <HAL_GPIO_Init+0x14e>
 8000c7c:	2d02      	cmp	r5, #2
 8000c7e:	f000 80af 	beq.w	8000de0 <HAL_GPIO_Init+0x198>
 8000c82:	f200 8081 	bhi.w	8000d88 <HAL_GPIO_Init+0x140>
 8000c86:	2d00      	cmp	r5, #0
 8000c88:	f000 8091 	beq.w	8000dae <HAL_GPIO_Init+0x166>
 8000c8c:	2d01      	cmp	r5, #1
 8000c8e:	f000 80a5 	beq.w	8000ddc <HAL_GPIO_Init+0x194>
      MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
 8000c92:	f04f 090f 	mov.w	r9, #15
      configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL     : &GPIOx->CRH;
 8000c96:	2cff      	cmp	r4, #255	; 0xff
 8000c98:	bf93      	iteet	ls
 8000c9a:	4682      	movls	sl, r0
 8000c9c:	f106 4580 	addhi.w	r5, r6, #1073741824	; 0x40000000
 8000ca0:	3d08      	subhi	r5, #8
 8000ca2:	f8d0 b000 	ldrls.w	fp, [r0]
 8000ca6:	bf92      	itee	ls
 8000ca8:	00b5      	lslls	r5, r6, #2
 8000caa:	f8d0 b004 	ldrhi.w	fp, [r0, #4]
 8000cae:	00ad      	lslhi	r5, r5, #2
      MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
 8000cb0:	fa09 f805 	lsl.w	r8, r9, r5
 8000cb4:	ea2b 0808 	bic.w	r8, fp, r8
 8000cb8:	fa02 f505 	lsl.w	r5, r2, r5
      configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL     : &GPIOx->CRH;
 8000cbc:	bf88      	it	hi
 8000cbe:	f100 0a04 	addhi.w	sl, r0, #4
      MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
 8000cc2:	ea48 0505 	orr.w	r5, r8, r5
 8000cc6:	f8ca 5000 	str.w	r5, [sl]
      if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
 8000cca:	f8d1 a004 	ldr.w	sl, [r1, #4]
 8000cce:	f01a 5f80 	tst.w	sl, #268435456	; 0x10000000
 8000cd2:	d052      	beq.n	8000d7a <HAL_GPIO_Init+0x132>
        __HAL_RCC_AFIO_CLK_ENABLE();
 8000cd4:	69bd      	ldr	r5, [r7, #24]
 8000cd6:	f026 0803 	bic.w	r8, r6, #3
 8000cda:	f045 0501 	orr.w	r5, r5, #1
 8000cde:	61bd      	str	r5, [r7, #24]
 8000ce0:	69bd      	ldr	r5, [r7, #24]
 8000ce2:	f108 4880 	add.w	r8, r8, #1073741824	; 0x40000000
 8000ce6:	f005 0501 	and.w	r5, r5, #1
 8000cea:	9501      	str	r5, [sp, #4]
 8000cec:	f508 3880 	add.w	r8, r8, #65536	; 0x10000
        CLEAR_BIT(temp, (0x0FU) << (4U * (position & 0x03U)));
 8000cf0:	f006 0b03 	and.w	fp, r6, #3
        __HAL_RCC_AFIO_CLK_ENABLE();
 8000cf4:	9d01      	ldr	r5, [sp, #4]
        CLEAR_BIT(temp, (0x0FU) << (4U * (position & 0x03U)));
 8000cf6:	ea4f 0b8b 	mov.w	fp, fp, lsl #2
        temp = AFIO->EXTICR[position >> 2U];
 8000cfa:	f8d8 5008 	ldr.w	r5, [r8, #8]
        CLEAR_BIT(temp, (0x0FU) << (4U * (position & 0x03U)));
 8000cfe:	fa09 f90b 	lsl.w	r9, r9, fp
 8000d02:	ea25 0909 	bic.w	r9, r5, r9
        SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
 8000d06:	4d41      	ldr	r5, [pc, #260]	; (8000e0c <HAL_GPIO_Init+0x1c4>)
 8000d08:	42a8      	cmp	r0, r5
 8000d0a:	d071      	beq.n	8000df0 <HAL_GPIO_Init+0x1a8>
 8000d0c:	f505 6580 	add.w	r5, r5, #1024	; 0x400
 8000d10:	42a8      	cmp	r0, r5
 8000d12:	d06f      	beq.n	8000df4 <HAL_GPIO_Init+0x1ac>
 8000d14:	f505 6580 	add.w	r5, r5, #1024	; 0x400
 8000d18:	42a8      	cmp	r0, r5
 8000d1a:	d06d      	beq.n	8000df8 <HAL_GPIO_Init+0x1b0>
 8000d1c:	f505 6580 	add.w	r5, r5, #1024	; 0x400
 8000d20:	42a8      	cmp	r0, r5
 8000d22:	d06b      	beq.n	8000dfc <HAL_GPIO_Init+0x1b4>
 8000d24:	f505 6580 	add.w	r5, r5, #1024	; 0x400
 8000d28:	42a8      	cmp	r0, r5
 8000d2a:	d069      	beq.n	8000e00 <HAL_GPIO_Init+0x1b8>
 8000d2c:	4570      	cmp	r0, lr
 8000d2e:	bf0c      	ite	eq
 8000d30:	2505      	moveq	r5, #5
 8000d32:	2506      	movne	r5, #6
 8000d34:	fa05 f50b 	lsl.w	r5, r5, fp
 8000d38:	ea45 0509 	orr.w	r5, r5, r9
        AFIO->EXTICR[position >> 2U] = temp;
 8000d3c:	f8c8 5008 	str.w	r5, [r8, #8]


        /* Configure the interrupt mask */
        if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
        {
          SET_BIT(EXTI->IMR, iocurrent);
 8000d40:	681d      	ldr	r5, [r3, #0]
        if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
 8000d42:	f41a 3f80 	tst.w	sl, #65536	; 0x10000
          SET_BIT(EXTI->IMR, iocurrent);
 8000d46:	bf14      	ite	ne
 8000d48:	4325      	orrne	r5, r4
        }
        else
        {
          CLEAR_BIT(EXTI->IMR, iocurrent);
 8000d4a:	43a5      	biceq	r5, r4
 8000d4c:	601d      	str	r5, [r3, #0]
        }

        /* Configure the event mask */
        if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
        {
          SET_BIT(EXTI->EMR, iocurrent);
 8000d4e:	685d      	ldr	r5, [r3, #4]
        if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
 8000d50:	f41a 3f00 	tst.w	sl, #131072	; 0x20000
          SET_BIT(EXTI->EMR, iocurrent);
 8000d54:	bf14      	ite	ne
 8000d56:	4325      	orrne	r5, r4
        }
        else
        {
          CLEAR_BIT(EXTI->EMR, iocurrent);
 8000d58:	43a5      	biceq	r5, r4
 8000d5a:	605d      	str	r5, [r3, #4]
        }

        /* Enable or disable the rising trigger */
        if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
        {
          SET_BIT(EXTI->RTSR, iocurrent);
 8000d5c:	689d      	ldr	r5, [r3, #8]
        if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
 8000d5e:	f41a 1f80 	tst.w	sl, #1048576	; 0x100000
          SET_BIT(EXTI->RTSR, iocurrent);
 8000d62:	bf14      	ite	ne
 8000d64:	4325      	orrne	r5, r4
        }
        else
        {
          CLEAR_BIT(EXTI->RTSR, iocurrent);
 8000d66:	43a5      	biceq	r5, r4
 8000d68:	609d      	str	r5, [r3, #8]
        }

        /* Enable or disable the falling trigger */
        if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
        {
          SET_BIT(EXTI->FTSR, iocurrent);
 8000d6a:	68dd      	ldr	r5, [r3, #12]
        if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
 8000d6c:	f41a 1f00 	tst.w	sl, #2097152	; 0x200000
          SET_BIT(EXTI->FTSR, iocurrent);
 8000d70:	bf14      	ite	ne
 8000d72:	432c      	orrne	r4, r5
        }
        else
        {
          CLEAR_BIT(EXTI->FTSR, iocurrent);
 8000d74:	ea25 0404 	biceq.w	r4, r5, r4
 8000d78:	60dc      	str	r4, [r3, #12]
  for (position = 0U; position < GPIO_NUMBER; position++)
 8000d7a:	3601      	adds	r6, #1
 8000d7c:	2e10      	cmp	r6, #16
 8000d7e:	f47f af6d 	bne.w	8000c5c <HAL_GPIO_Init+0x14>
        }
      }
    }
  }
}
 8000d82:	b003      	add	sp, #12
 8000d84:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
      switch (GPIO_Init->Mode)
 8000d88:	2d03      	cmp	r5, #3
 8000d8a:	d025      	beq.n	8000dd8 <HAL_GPIO_Init+0x190>
 8000d8c:	2d11      	cmp	r5, #17
 8000d8e:	d180      	bne.n	8000c92 <HAL_GPIO_Init+0x4a>
          config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;
 8000d90:	68ca      	ldr	r2, [r1, #12]
 8000d92:	3204      	adds	r2, #4
          break;
 8000d94:	e77d      	b.n	8000c92 <HAL_GPIO_Init+0x4a>
      switch (GPIO_Init->Mode)
 8000d96:	4565      	cmp	r5, ip
 8000d98:	d009      	beq.n	8000dae <HAL_GPIO_Init+0x166>
 8000d9a:	d812      	bhi.n	8000dc2 <HAL_GPIO_Init+0x17a>
 8000d9c:	f8df 9078 	ldr.w	r9, [pc, #120]	; 8000e18 <HAL_GPIO_Init+0x1d0>
 8000da0:	454d      	cmp	r5, r9
 8000da2:	d004      	beq.n	8000dae <HAL_GPIO_Init+0x166>
 8000da4:	f509 3980 	add.w	r9, r9, #65536	; 0x10000
 8000da8:	454d      	cmp	r5, r9
 8000daa:	f47f af72 	bne.w	8000c92 <HAL_GPIO_Init+0x4a>
          if (GPIO_Init->Pull == GPIO_NOPULL)
 8000dae:	688a      	ldr	r2, [r1, #8]
 8000db0:	b1e2      	cbz	r2, 8000dec <HAL_GPIO_Init+0x1a4>
          else if (GPIO_Init->Pull == GPIO_PULLUP)
 8000db2:	2a01      	cmp	r2, #1
            GPIOx->BSRR = ioposition;
 8000db4:	bf0c      	ite	eq
 8000db6:	f8c0 8010 	streq.w	r8, [r0, #16]
            GPIOx->BRR = ioposition;
 8000dba:	f8c0 8014 	strne.w	r8, [r0, #20]
            config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
 8000dbe:	2208      	movs	r2, #8
 8000dc0:	e767      	b.n	8000c92 <HAL_GPIO_Init+0x4a>
      switch (GPIO_Init->Mode)
 8000dc2:	f8df 9058 	ldr.w	r9, [pc, #88]	; 8000e1c <HAL_GPIO_Init+0x1d4>
 8000dc6:	454d      	cmp	r5, r9
 8000dc8:	d0f1      	beq.n	8000dae <HAL_GPIO_Init+0x166>
 8000dca:	f509 3980 	add.w	r9, r9, #65536	; 0x10000
 8000dce:	454d      	cmp	r5, r9
 8000dd0:	d0ed      	beq.n	8000dae <HAL_GPIO_Init+0x166>
 8000dd2:	f5a9 1980 	sub.w	r9, r9, #1048576	; 0x100000
 8000dd6:	e7e7      	b.n	8000da8 <HAL_GPIO_Init+0x160>
          config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
 8000dd8:	2200      	movs	r2, #0
 8000dda:	e75a      	b.n	8000c92 <HAL_GPIO_Init+0x4a>
          config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;
 8000ddc:	68ca      	ldr	r2, [r1, #12]
          break;
 8000dde:	e758      	b.n	8000c92 <HAL_GPIO_Init+0x4a>
          config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;
 8000de0:	68ca      	ldr	r2, [r1, #12]
 8000de2:	3208      	adds	r2, #8
          break;
 8000de4:	e755      	b.n	8000c92 <HAL_GPIO_Init+0x4a>
          config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;
 8000de6:	68ca      	ldr	r2, [r1, #12]
 8000de8:	320c      	adds	r2, #12
          break;
 8000dea:	e752      	b.n	8000c92 <HAL_GPIO_Init+0x4a>
            config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
 8000dec:	2204      	movs	r2, #4
 8000dee:	e750      	b.n	8000c92 <HAL_GPIO_Init+0x4a>
        SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
 8000df0:	2500      	movs	r5, #0
 8000df2:	e79f      	b.n	8000d34 <HAL_GPIO_Init+0xec>
 8000df4:	2501      	movs	r5, #1
 8000df6:	e79d      	b.n	8000d34 <HAL_GPIO_Init+0xec>
 8000df8:	2502      	movs	r5, #2
 8000dfa:	e79b      	b.n	8000d34 <HAL_GPIO_Init+0xec>
 8000dfc:	2503      	movs	r5, #3
 8000dfe:	e799      	b.n	8000d34 <HAL_GPIO_Init+0xec>
 8000e00:	2504      	movs	r5, #4
 8000e02:	e797      	b.n	8000d34 <HAL_GPIO_Init+0xec>
 8000e04:	40021000 	.word	0x40021000
 8000e08:	40010400 	.word	0x40010400
 8000e0c:	40010800 	.word	0x40010800
 8000e10:	40011c00 	.word	0x40011c00
 8000e14:	10210000 	.word	0x10210000
 8000e18:	10110000 	.word	0x10110000
 8000e1c:	10310000 	.word	0x10310000

08000e20 <HAL_GPIO_WritePin>:
{
  /* Check the parameters */
  assert_param(IS_GPIO_PIN(GPIO_Pin));
  assert_param(IS_GPIO_PIN_ACTION(PinState));

  if (PinState != GPIO_PIN_RESET)
 8000e20:	b10a      	cbz	r2, 8000e26 <HAL_GPIO_WritePin+0x6>
  {
    GPIOx->BSRR = GPIO_Pin;
  }
  else
  {
    GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
 8000e22:	6101      	str	r1, [r0, #16]
 8000e24:	4770      	bx	lr
 8000e26:	0409      	lsls	r1, r1, #16
 8000e28:	e7fb      	b.n	8000e22 <HAL_GPIO_WritePin+0x2>
	...

08000e2c <HAL_RCC_OscConfig>:
  /* Check the parameters */
  assert_param(RCC_OscInitStruct != NULL);
  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
  
  /*------------------------------- HSE Configuration ------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
 8000e2c:	6803      	ldr	r3, [r0, #0]
{
 8000e2e:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
 8000e32:	07db      	lsls	r3, r3, #31
{
 8000e34:	4605      	mov	r5, r0
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
 8000e36:	d410      	bmi.n	8000e5a <HAL_RCC_OscConfig+0x2e>
        }
      }
    }
  }
  /*----------------------------- HSI Configuration --------------------------*/ 
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
 8000e38:	682b      	ldr	r3, [r5, #0]
 8000e3a:	079f      	lsls	r7, r3, #30
 8000e3c:	d45e      	bmi.n	8000efc <HAL_RCC_OscConfig+0xd0>
        }
      }
    }
  }
  /*------------------------------ LSI Configuration -------------------------*/ 
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
 8000e3e:	682b      	ldr	r3, [r5, #0]
 8000e40:	0719      	lsls	r1, r3, #28
 8000e42:	f100 8095 	bmi.w	8000f70 <HAL_RCC_OscConfig+0x144>
        }
      }
    }
  }
  /*------------------------------ LSE Configuration -------------------------*/ 
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
 8000e46:	682b      	ldr	r3, [r5, #0]
 8000e48:	075a      	lsls	r2, r3, #29
 8000e4a:	f100 80bf 	bmi.w	8000fcc <HAL_RCC_OscConfig+0x1a0>

#endif /* RCC_CR_PLL2ON */
  /*-------------------------------- PLL Configuration -----------------------*/
  /* Check the parameters */
  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
 8000e4e:	69ea      	ldr	r2, [r5, #28]
 8000e50:	2a00      	cmp	r2, #0
 8000e52:	f040 812d 	bne.w	80010b0 <HAL_RCC_OscConfig+0x284>
    {
      return HAL_ERROR;
    }
  }
  
  return HAL_OK;
 8000e56:	2000      	movs	r0, #0
 8000e58:	e014      	b.n	8000e84 <HAL_RCC_OscConfig+0x58>
    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 
 8000e5a:	4c90      	ldr	r4, [pc, #576]	; (800109c <HAL_RCC_OscConfig+0x270>)
 8000e5c:	6863      	ldr	r3, [r4, #4]
 8000e5e:	f003 030c 	and.w	r3, r3, #12
 8000e62:	2b04      	cmp	r3, #4
 8000e64:	d007      	beq.n	8000e76 <HAL_RCC_OscConfig+0x4a>
       || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
 8000e66:	6863      	ldr	r3, [r4, #4]
 8000e68:	f003 030c 	and.w	r3, r3, #12
 8000e6c:	2b08      	cmp	r3, #8
 8000e6e:	d10c      	bne.n	8000e8a <HAL_RCC_OscConfig+0x5e>
 8000e70:	6863      	ldr	r3, [r4, #4]
 8000e72:	03de      	lsls	r6, r3, #15
 8000e74:	d509      	bpl.n	8000e8a <HAL_RCC_OscConfig+0x5e>
      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
 8000e76:	6823      	ldr	r3, [r4, #0]
 8000e78:	039c      	lsls	r4, r3, #14
 8000e7a:	d5dd      	bpl.n	8000e38 <HAL_RCC_OscConfig+0xc>
 8000e7c:	686b      	ldr	r3, [r5, #4]
 8000e7e:	2b00      	cmp	r3, #0
 8000e80:	d1da      	bne.n	8000e38 <HAL_RCC_OscConfig+0xc>
        return HAL_ERROR;
 8000e82:	2001      	movs	r0, #1
}
 8000e84:	b002      	add	sp, #8
 8000e86:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 8000e8a:	686b      	ldr	r3, [r5, #4]
 8000e8c:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
 8000e90:	d110      	bne.n	8000eb4 <HAL_RCC_OscConfig+0x88>
 8000e92:	6823      	ldr	r3, [r4, #0]
 8000e94:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
 8000e98:	6023      	str	r3, [r4, #0]
        tickstart = HAL_GetTick();
 8000e9a:	f7ff fa05 	bl	80002a8 <HAL_GetTick>
 8000e9e:	4606      	mov	r6, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 8000ea0:	6823      	ldr	r3, [r4, #0]
 8000ea2:	0398      	lsls	r0, r3, #14
 8000ea4:	d4c8      	bmi.n	8000e38 <HAL_RCC_OscConfig+0xc>
          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
 8000ea6:	f7ff f9ff 	bl	80002a8 <HAL_GetTick>
 8000eaa:	1b80      	subs	r0, r0, r6
 8000eac:	2864      	cmp	r0, #100	; 0x64
 8000eae:	d9f7      	bls.n	8000ea0 <HAL_RCC_OscConfig+0x74>
            return HAL_TIMEOUT;
 8000eb0:	2003      	movs	r0, #3
 8000eb2:	e7e7      	b.n	8000e84 <HAL_RCC_OscConfig+0x58>
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 8000eb4:	b99b      	cbnz	r3, 8000ede <HAL_RCC_OscConfig+0xb2>
 8000eb6:	6823      	ldr	r3, [r4, #0]
 8000eb8:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
 8000ebc:	6023      	str	r3, [r4, #0]
 8000ebe:	6823      	ldr	r3, [r4, #0]
 8000ec0:	f423 2380 	bic.w	r3, r3, #262144	; 0x40000
 8000ec4:	6023      	str	r3, [r4, #0]
        tickstart = HAL_GetTick();
 8000ec6:	f7ff f9ef 	bl	80002a8 <HAL_GetTick>
 8000eca:	4606      	mov	r6, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
 8000ecc:	6823      	ldr	r3, [r4, #0]
 8000ece:	0399      	lsls	r1, r3, #14
 8000ed0:	d5b2      	bpl.n	8000e38 <HAL_RCC_OscConfig+0xc>
           if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
 8000ed2:	f7ff f9e9 	bl	80002a8 <HAL_GetTick>
 8000ed6:	1b80      	subs	r0, r0, r6
 8000ed8:	2864      	cmp	r0, #100	; 0x64
 8000eda:	d9f7      	bls.n	8000ecc <HAL_RCC_OscConfig+0xa0>
 8000edc:	e7e8      	b.n	8000eb0 <HAL_RCC_OscConfig+0x84>
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 8000ede:	f5b3 2fa0 	cmp.w	r3, #327680	; 0x50000
 8000ee2:	6823      	ldr	r3, [r4, #0]
 8000ee4:	d103      	bne.n	8000eee <HAL_RCC_OscConfig+0xc2>
 8000ee6:	f443 2380 	orr.w	r3, r3, #262144	; 0x40000
 8000eea:	6023      	str	r3, [r4, #0]
 8000eec:	e7d1      	b.n	8000e92 <HAL_RCC_OscConfig+0x66>
 8000eee:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
 8000ef2:	6023      	str	r3, [r4, #0]
 8000ef4:	6823      	ldr	r3, [r4, #0]
 8000ef6:	f423 2380 	bic.w	r3, r3, #262144	; 0x40000
 8000efa:	e7cd      	b.n	8000e98 <HAL_RCC_OscConfig+0x6c>
    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 
 8000efc:	4c67      	ldr	r4, [pc, #412]	; (800109c <HAL_RCC_OscConfig+0x270>)
 8000efe:	6863      	ldr	r3, [r4, #4]
 8000f00:	f013 0f0c 	tst.w	r3, #12
 8000f04:	d007      	beq.n	8000f16 <HAL_RCC_OscConfig+0xea>
       || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
 8000f06:	6863      	ldr	r3, [r4, #4]
 8000f08:	f003 030c 	and.w	r3, r3, #12
 8000f0c:	2b08      	cmp	r3, #8
 8000f0e:	d110      	bne.n	8000f32 <HAL_RCC_OscConfig+0x106>
 8000f10:	6863      	ldr	r3, [r4, #4]
 8000f12:	03da      	lsls	r2, r3, #15
 8000f14:	d40d      	bmi.n	8000f32 <HAL_RCC_OscConfig+0x106>
      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
 8000f16:	6823      	ldr	r3, [r4, #0]
 8000f18:	079b      	lsls	r3, r3, #30
 8000f1a:	d502      	bpl.n	8000f22 <HAL_RCC_OscConfig+0xf6>
 8000f1c:	692b      	ldr	r3, [r5, #16]
 8000f1e:	2b01      	cmp	r3, #1
 8000f20:	d1af      	bne.n	8000e82 <HAL_RCC_OscConfig+0x56>
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 8000f22:	6823      	ldr	r3, [r4, #0]
 8000f24:	696a      	ldr	r2, [r5, #20]
 8000f26:	f023 03f8 	bic.w	r3, r3, #248	; 0xf8
 8000f2a:	ea43 03c2 	orr.w	r3, r3, r2, lsl #3
 8000f2e:	6023      	str	r3, [r4, #0]
 8000f30:	e785      	b.n	8000e3e <HAL_RCC_OscConfig+0x12>
      if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
 8000f32:	692a      	ldr	r2, [r5, #16]
 8000f34:	4b5a      	ldr	r3, [pc, #360]	; (80010a0 <HAL_RCC_OscConfig+0x274>)
 8000f36:	b16a      	cbz	r2, 8000f54 <HAL_RCC_OscConfig+0x128>
        __HAL_RCC_HSI_ENABLE();
 8000f38:	2201      	movs	r2, #1
 8000f3a:	601a      	str	r2, [r3, #0]
        tickstart = HAL_GetTick();
 8000f3c:	f7ff f9b4 	bl	80002a8 <HAL_GetTick>
 8000f40:	4606      	mov	r6, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 8000f42:	6823      	ldr	r3, [r4, #0]
 8000f44:	079f      	lsls	r7, r3, #30
 8000f46:	d4ec      	bmi.n	8000f22 <HAL_RCC_OscConfig+0xf6>
          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
 8000f48:	f7ff f9ae 	bl	80002a8 <HAL_GetTick>
 8000f4c:	1b80      	subs	r0, r0, r6
 8000f4e:	2802      	cmp	r0, #2
 8000f50:	d9f7      	bls.n	8000f42 <HAL_RCC_OscConfig+0x116>
 8000f52:	e7ad      	b.n	8000eb0 <HAL_RCC_OscConfig+0x84>
        __HAL_RCC_HSI_DISABLE();
 8000f54:	601a      	str	r2, [r3, #0]
        tickstart = HAL_GetTick();
 8000f56:	f7ff f9a7 	bl	80002a8 <HAL_GetTick>
 8000f5a:	4606      	mov	r6, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
 8000f5c:	6823      	ldr	r3, [r4, #0]
 8000f5e:	0798      	lsls	r0, r3, #30
 8000f60:	f57f af6d 	bpl.w	8000e3e <HAL_RCC_OscConfig+0x12>
          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
 8000f64:	f7ff f9a0 	bl	80002a8 <HAL_GetTick>
 8000f68:	1b80      	subs	r0, r0, r6
 8000f6a:	2802      	cmp	r0, #2
 8000f6c:	d9f6      	bls.n	8000f5c <HAL_RCC_OscConfig+0x130>
 8000f6e:	e79f      	b.n	8000eb0 <HAL_RCC_OscConfig+0x84>
    if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
 8000f70:	69aa      	ldr	r2, [r5, #24]
 8000f72:	4c4a      	ldr	r4, [pc, #296]	; (800109c <HAL_RCC_OscConfig+0x270>)
 8000f74:	4b4b      	ldr	r3, [pc, #300]	; (80010a4 <HAL_RCC_OscConfig+0x278>)
 8000f76:	b1da      	cbz	r2, 8000fb0 <HAL_RCC_OscConfig+0x184>
      __HAL_RCC_LSI_ENABLE();
 8000f78:	2201      	movs	r2, #1
 8000f7a:	601a      	str	r2, [r3, #0]
      tickstart = HAL_GetTick();
 8000f7c:	f7ff f994 	bl	80002a8 <HAL_GetTick>
 8000f80:	4606      	mov	r6, r0
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
 8000f82:	6a63      	ldr	r3, [r4, #36]	; 0x24
 8000f84:	079b      	lsls	r3, r3, #30
 8000f86:	d50d      	bpl.n	8000fa4 <HAL_RCC_OscConfig+0x178>
  * @param  mdelay: specifies the delay time length, in milliseconds.
  * @retval None
  */
static void RCC_Delay(uint32_t mdelay)
{
  __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
 8000f88:	f44f 52fa 	mov.w	r2, #8000	; 0x1f40
 8000f8c:	4b46      	ldr	r3, [pc, #280]	; (80010a8 <HAL_RCC_OscConfig+0x27c>)
 8000f8e:	681b      	ldr	r3, [r3, #0]
 8000f90:	fbb3 f3f2 	udiv	r3, r3, r2
 8000f94:	9301      	str	r3, [sp, #4]
  \brief   No Operation
  \details No Operation does nothing. This instruction can be used for code alignment purposes.
 */
__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
{
  __ASM volatile ("nop");
 8000f96:	bf00      	nop
  do 
  {
    __NOP();
  } 
  while (Delay --);
 8000f98:	9b01      	ldr	r3, [sp, #4]
 8000f9a:	1e5a      	subs	r2, r3, #1
 8000f9c:	9201      	str	r2, [sp, #4]
 8000f9e:	2b00      	cmp	r3, #0
 8000fa0:	d1f9      	bne.n	8000f96 <HAL_RCC_OscConfig+0x16a>
 8000fa2:	e750      	b.n	8000e46 <HAL_RCC_OscConfig+0x1a>
        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
 8000fa4:	f7ff f980 	bl	80002a8 <HAL_GetTick>
 8000fa8:	1b80      	subs	r0, r0, r6
 8000faa:	2802      	cmp	r0, #2
 8000fac:	d9e9      	bls.n	8000f82 <HAL_RCC_OscConfig+0x156>
 8000fae:	e77f      	b.n	8000eb0 <HAL_RCC_OscConfig+0x84>
      __HAL_RCC_LSI_DISABLE();
 8000fb0:	601a      	str	r2, [r3, #0]
      tickstart = HAL_GetTick();
 8000fb2:	f7ff f979 	bl	80002a8 <HAL_GetTick>
 8000fb6:	4606      	mov	r6, r0
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
 8000fb8:	6a63      	ldr	r3, [r4, #36]	; 0x24
 8000fba:	079f      	lsls	r7, r3, #30
 8000fbc:	f57f af43 	bpl.w	8000e46 <HAL_RCC_OscConfig+0x1a>
        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
 8000fc0:	f7ff f972 	bl	80002a8 <HAL_GetTick>
 8000fc4:	1b80      	subs	r0, r0, r6
 8000fc6:	2802      	cmp	r0, #2
 8000fc8:	d9f6      	bls.n	8000fb8 <HAL_RCC_OscConfig+0x18c>
 8000fca:	e771      	b.n	8000eb0 <HAL_RCC_OscConfig+0x84>
    if(__HAL_RCC_PWR_IS_CLK_DISABLED())
 8000fcc:	4c33      	ldr	r4, [pc, #204]	; (800109c <HAL_RCC_OscConfig+0x270>)
 8000fce:	69e3      	ldr	r3, [r4, #28]
 8000fd0:	00d8      	lsls	r0, r3, #3
 8000fd2:	d424      	bmi.n	800101e <HAL_RCC_OscConfig+0x1f2>
      pwrclkchanged = SET;
 8000fd4:	2701      	movs	r7, #1
      __HAL_RCC_PWR_CLK_ENABLE();
 8000fd6:	69e3      	ldr	r3, [r4, #28]
 8000fd8:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
 8000fdc:	61e3      	str	r3, [r4, #28]
 8000fde:	69e3      	ldr	r3, [r4, #28]
 8000fe0:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8000fe4:	9300      	str	r3, [sp, #0]
 8000fe6:	9b00      	ldr	r3, [sp, #0]
    if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 8000fe8:	4e30      	ldr	r6, [pc, #192]	; (80010ac <HAL_RCC_OscConfig+0x280>)
 8000fea:	6833      	ldr	r3, [r6, #0]
 8000fec:	05d9      	lsls	r1, r3, #23
 8000fee:	d518      	bpl.n	8001022 <HAL_RCC_OscConfig+0x1f6>
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 8000ff0:	68eb      	ldr	r3, [r5, #12]
 8000ff2:	2b01      	cmp	r3, #1
 8000ff4:	d126      	bne.n	8001044 <HAL_RCC_OscConfig+0x218>
 8000ff6:	6a23      	ldr	r3, [r4, #32]
 8000ff8:	f043 0301 	orr.w	r3, r3, #1
 8000ffc:	6223      	str	r3, [r4, #32]
      tickstart = HAL_GetTick();
 8000ffe:	f7ff f953 	bl	80002a8 <HAL_GetTick>
        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
 8001002:	f241 3688 	movw	r6, #5000	; 0x1388
      tickstart = HAL_GetTick();
 8001006:	4680      	mov	r8, r0
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
 8001008:	6a23      	ldr	r3, [r4, #32]
 800100a:	079b      	lsls	r3, r3, #30
 800100c:	d53f      	bpl.n	800108e <HAL_RCC_OscConfig+0x262>
    if(pwrclkchanged == SET)
 800100e:	2f00      	cmp	r7, #0
 8001010:	f43f af1d 	beq.w	8000e4e <HAL_RCC_OscConfig+0x22>
      __HAL_RCC_PWR_CLK_DISABLE();
 8001014:	69e3      	ldr	r3, [r4, #28]
 8001016:	f023 5380 	bic.w	r3, r3, #268435456	; 0x10000000
 800101a:	61e3      	str	r3, [r4, #28]
 800101c:	e717      	b.n	8000e4e <HAL_RCC_OscConfig+0x22>
    FlagStatus       pwrclkchanged = RESET;
 800101e:	2700      	movs	r7, #0
 8001020:	e7e2      	b.n	8000fe8 <HAL_RCC_OscConfig+0x1bc>
      SET_BIT(PWR->CR, PWR_CR_DBP);
 8001022:	6833      	ldr	r3, [r6, #0]
 8001024:	f443 7380 	orr.w	r3, r3, #256	; 0x100
 8001028:	6033      	str	r3, [r6, #0]
      tickstart = HAL_GetTick();
 800102a:	f7ff f93d 	bl	80002a8 <HAL_GetTick>
 800102e:	4680      	mov	r8, r0
      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 8001030:	6833      	ldr	r3, [r6, #0]
 8001032:	05da      	lsls	r2, r3, #23
 8001034:	d4dc      	bmi.n	8000ff0 <HAL_RCC_OscConfig+0x1c4>
        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
 8001036:	f7ff f937 	bl	80002a8 <HAL_GetTick>
 800103a:	eba0 0008 	sub.w	r0, r0, r8
 800103e:	2864      	cmp	r0, #100	; 0x64
 8001040:	d9f6      	bls.n	8001030 <HAL_RCC_OscConfig+0x204>
 8001042:	e735      	b.n	8000eb0 <HAL_RCC_OscConfig+0x84>
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 8001044:	b9ab      	cbnz	r3, 8001072 <HAL_RCC_OscConfig+0x246>
 8001046:	6a23      	ldr	r3, [r4, #32]
        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
 8001048:	f241 3888 	movw	r8, #5000	; 0x1388
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 800104c:	f023 0301 	bic.w	r3, r3, #1
 8001050:	6223      	str	r3, [r4, #32]
 8001052:	6a23      	ldr	r3, [r4, #32]
 8001054:	f023 0304 	bic.w	r3, r3, #4
 8001058:	6223      	str	r3, [r4, #32]
      tickstart = HAL_GetTick();
 800105a:	f7ff f925 	bl	80002a8 <HAL_GetTick>
 800105e:	4606      	mov	r6, r0
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
 8001060:	6a23      	ldr	r3, [r4, #32]
 8001062:	0798      	lsls	r0, r3, #30
 8001064:	d5d3      	bpl.n	800100e <HAL_RCC_OscConfig+0x1e2>
        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
 8001066:	f7ff f91f 	bl	80002a8 <HAL_GetTick>
 800106a:	1b80      	subs	r0, r0, r6
 800106c:	4540      	cmp	r0, r8
 800106e:	d9f7      	bls.n	8001060 <HAL_RCC_OscConfig+0x234>
 8001070:	e71e      	b.n	8000eb0 <HAL_RCC_OscConfig+0x84>
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 8001072:	2b05      	cmp	r3, #5
 8001074:	6a23      	ldr	r3, [r4, #32]
 8001076:	d103      	bne.n	8001080 <HAL_RCC_OscConfig+0x254>
 8001078:	f043 0304 	orr.w	r3, r3, #4
 800107c:	6223      	str	r3, [r4, #32]
 800107e:	e7ba      	b.n	8000ff6 <HAL_RCC_OscConfig+0x1ca>
 8001080:	f023 0301 	bic.w	r3, r3, #1
 8001084:	6223      	str	r3, [r4, #32]
 8001086:	6a23      	ldr	r3, [r4, #32]
 8001088:	f023 0304 	bic.w	r3, r3, #4
 800108c:	e7b6      	b.n	8000ffc <HAL_RCC_OscConfig+0x1d0>
        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
 800108e:	f7ff f90b 	bl	80002a8 <HAL_GetTick>
 8001092:	eba0 0008 	sub.w	r0, r0, r8
 8001096:	42b0      	cmp	r0, r6
 8001098:	d9b6      	bls.n	8001008 <HAL_RCC_OscConfig+0x1dc>
 800109a:	e709      	b.n	8000eb0 <HAL_RCC_OscConfig+0x84>
 800109c:	40021000 	.word	0x40021000
 80010a0:	42420000 	.word	0x42420000
 80010a4:	42420480 	.word	0x42420480
 80010a8:	20000008 	.word	0x20000008
 80010ac:	40007000 	.word	0x40007000
    if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
 80010b0:	4c22      	ldr	r4, [pc, #136]	; (800113c <HAL_RCC_OscConfig+0x310>)
 80010b2:	6863      	ldr	r3, [r4, #4]
 80010b4:	f003 030c 	and.w	r3, r3, #12
 80010b8:	2b08      	cmp	r3, #8
 80010ba:	f43f aee2 	beq.w	8000e82 <HAL_RCC_OscConfig+0x56>
 80010be:	2300      	movs	r3, #0
 80010c0:	4e1f      	ldr	r6, [pc, #124]	; (8001140 <HAL_RCC_OscConfig+0x314>)
      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
 80010c2:	2a02      	cmp	r2, #2
        __HAL_RCC_PLL_DISABLE();
 80010c4:	6033      	str	r3, [r6, #0]
      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
 80010c6:	d12b      	bne.n	8001120 <HAL_RCC_OscConfig+0x2f4>
        tickstart = HAL_GetTick();
 80010c8:	f7ff f8ee 	bl	80002a8 <HAL_GetTick>
 80010cc:	4607      	mov	r7, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
 80010ce:	6823      	ldr	r3, [r4, #0]
 80010d0:	0199      	lsls	r1, r3, #6
 80010d2:	d41f      	bmi.n	8001114 <HAL_RCC_OscConfig+0x2e8>
        if(RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
 80010d4:	6a2b      	ldr	r3, [r5, #32]
 80010d6:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
 80010da:	d105      	bne.n	80010e8 <HAL_RCC_OscConfig+0x2bc>
          __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
 80010dc:	6862      	ldr	r2, [r4, #4]
 80010de:	68a9      	ldr	r1, [r5, #8]
 80010e0:	f422 3200 	bic.w	r2, r2, #131072	; 0x20000
 80010e4:	430a      	orrs	r2, r1
 80010e6:	6062      	str	r2, [r4, #4]
        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
 80010e8:	6a69      	ldr	r1, [r5, #36]	; 0x24
 80010ea:	6862      	ldr	r2, [r4, #4]
 80010ec:	430b      	orrs	r3, r1
 80010ee:	f422 1274 	bic.w	r2, r2, #3997696	; 0x3d0000
 80010f2:	4313      	orrs	r3, r2
 80010f4:	6063      	str	r3, [r4, #4]
        __HAL_RCC_PLL_ENABLE();
 80010f6:	2301      	movs	r3, #1
 80010f8:	6033      	str	r3, [r6, #0]
        tickstart = HAL_GetTick();
 80010fa:	f7ff f8d5 	bl	80002a8 <HAL_GetTick>
 80010fe:	4605      	mov	r5, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  == RESET)
 8001100:	6823      	ldr	r3, [r4, #0]
 8001102:	019a      	lsls	r2, r3, #6
 8001104:	f53f aea7 	bmi.w	8000e56 <HAL_RCC_OscConfig+0x2a>
          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
 8001108:	f7ff f8ce 	bl	80002a8 <HAL_GetTick>
 800110c:	1b40      	subs	r0, r0, r5
 800110e:	2802      	cmp	r0, #2
 8001110:	d9f6      	bls.n	8001100 <HAL_RCC_OscConfig+0x2d4>
 8001112:	e6cd      	b.n	8000eb0 <HAL_RCC_OscConfig+0x84>
          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
 8001114:	f7ff f8c8 	bl	80002a8 <HAL_GetTick>
 8001118:	1bc0      	subs	r0, r0, r7
 800111a:	2802      	cmp	r0, #2
 800111c:	d9d7      	bls.n	80010ce <HAL_RCC_OscConfig+0x2a2>
 800111e:	e6c7      	b.n	8000eb0 <HAL_RCC_OscConfig+0x84>
        tickstart = HAL_GetTick();
 8001120:	f7ff f8c2 	bl	80002a8 <HAL_GetTick>
 8001124:	4605      	mov	r5, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
 8001126:	6823      	ldr	r3, [r4, #0]
 8001128:	019b      	lsls	r3, r3, #6
 800112a:	f57f ae94 	bpl.w	8000e56 <HAL_RCC_OscConfig+0x2a>
          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
 800112e:	f7ff f8bb 	bl	80002a8 <HAL_GetTick>
 8001132:	1b40      	subs	r0, r0, r5
 8001134:	2802      	cmp	r0, #2
 8001136:	d9f6      	bls.n	8001126 <HAL_RCC_OscConfig+0x2fa>
 8001138:	e6ba      	b.n	8000eb0 <HAL_RCC_OscConfig+0x84>
 800113a:	bf00      	nop
 800113c:	40021000 	.word	0x40021000
 8001140:	42420060 	.word	0x42420060

08001144 <HAL_RCC_GetSysClockFreq>:
{
 8001144:	b530      	push	{r4, r5, lr}
  const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
 8001146:	4b19      	ldr	r3, [pc, #100]	; (80011ac <HAL_RCC_GetSysClockFreq+0x68>)
{
 8001148:	b087      	sub	sp, #28
  const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
 800114a:	ac02      	add	r4, sp, #8
 800114c:	f103 0510 	add.w	r5, r3, #16
 8001150:	4622      	mov	r2, r4
 8001152:	6818      	ldr	r0, [r3, #0]
 8001154:	6859      	ldr	r1, [r3, #4]
 8001156:	3308      	adds	r3, #8
 8001158:	c203      	stmia	r2!, {r0, r1}
 800115a:	42ab      	cmp	r3, r5
 800115c:	4614      	mov	r4, r2
 800115e:	d1f7      	bne.n	8001150 <HAL_RCC_GetSysClockFreq+0xc>
  const uint8_t aPredivFactorTable[2] = {1, 2};
 8001160:	2301      	movs	r3, #1
 8001162:	f88d 3004 	strb.w	r3, [sp, #4]
 8001166:	2302      	movs	r3, #2
  tmpreg = RCC->CFGR;
 8001168:	4911      	ldr	r1, [pc, #68]	; (80011b0 <HAL_RCC_GetSysClockFreq+0x6c>)
  const uint8_t aPredivFactorTable[2] = {1, 2};
 800116a:	f88d 3005 	strb.w	r3, [sp, #5]
  tmpreg = RCC->CFGR;
 800116e:	684b      	ldr	r3, [r1, #4]
  switch (tmpreg & RCC_CFGR_SWS)
 8001170:	f003 020c 	and.w	r2, r3, #12
 8001174:	2a08      	cmp	r2, #8
 8001176:	d117      	bne.n	80011a8 <HAL_RCC_GetSysClockFreq+0x64>
      pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
 8001178:	f3c3 4283 	ubfx	r2, r3, #18, #4
 800117c:	a806      	add	r0, sp, #24
 800117e:	4402      	add	r2, r0
      if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
 8001180:	03db      	lsls	r3, r3, #15
      pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
 8001182:	f812 2c10 	ldrb.w	r2, [r2, #-16]
      if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
 8001186:	d50c      	bpl.n	80011a2 <HAL_RCC_GetSysClockFreq+0x5e>
        prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
 8001188:	684b      	ldr	r3, [r1, #4]
        pllclk = (uint32_t)((HSE_VALUE  * pllmul) / prediv);
 800118a:	480a      	ldr	r0, [pc, #40]	; (80011b4 <HAL_RCC_GetSysClockFreq+0x70>)
        prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
 800118c:	f3c3 4340 	ubfx	r3, r3, #17, #1
        pllclk = (uint32_t)((HSE_VALUE  * pllmul) / prediv);
 8001190:	4350      	muls	r0, r2
        prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
 8001192:	aa06      	add	r2, sp, #24
 8001194:	4413      	add	r3, r2
 8001196:	f813 3c14 	ldrb.w	r3, [r3, #-20]
        pllclk = (uint32_t)((HSE_VALUE  * pllmul) / prediv);
 800119a:	fbb0 f0f3 	udiv	r0, r0, r3
}
 800119e:	b007      	add	sp, #28
 80011a0:	bd30      	pop	{r4, r5, pc}
        pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
 80011a2:	4805      	ldr	r0, [pc, #20]	; (80011b8 <HAL_RCC_GetSysClockFreq+0x74>)
 80011a4:	4350      	muls	r0, r2
 80011a6:	e7fa      	b.n	800119e <HAL_RCC_GetSysClockFreq+0x5a>
      sysclockfreq = HSE_VALUE;
 80011a8:	4802      	ldr	r0, [pc, #8]	; (80011b4 <HAL_RCC_GetSysClockFreq+0x70>)
  return sysclockfreq;
 80011aa:	e7f8      	b.n	800119e <HAL_RCC_GetSysClockFreq+0x5a>
 80011ac:	08001f38 	.word	0x08001f38
 80011b0:	40021000 	.word	0x40021000
 80011b4:	007a1200 	.word	0x007a1200
 80011b8:	003d0900 	.word	0x003d0900

080011bc <HAL_RCC_ClockConfig>:
  if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
 80011bc:	4a54      	ldr	r2, [pc, #336]	; (8001310 <HAL_RCC_ClockConfig+0x154>)
{
 80011be:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
  if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
 80011c2:	6813      	ldr	r3, [r2, #0]
{
 80011c4:	4605      	mov	r5, r0
  if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
 80011c6:	f003 0307 	and.w	r3, r3, #7
 80011ca:	428b      	cmp	r3, r1
{
 80011cc:	460e      	mov	r6, r1
  if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
 80011ce:	d32a      	bcc.n	8001226 <HAL_RCC_ClockConfig+0x6a>
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
 80011d0:	6829      	ldr	r1, [r5, #0]
 80011d2:	078c      	lsls	r4, r1, #30
 80011d4:	d434      	bmi.n	8001240 <HAL_RCC_ClockConfig+0x84>
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
 80011d6:	07ca      	lsls	r2, r1, #31
 80011d8:	d447      	bmi.n	800126a <HAL_RCC_ClockConfig+0xae>
  if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
 80011da:	4a4d      	ldr	r2, [pc, #308]	; (8001310 <HAL_RCC_ClockConfig+0x154>)
 80011dc:	6813      	ldr	r3, [r2, #0]
 80011de:	f003 0307 	and.w	r3, r3, #7
 80011e2:	429e      	cmp	r6, r3
 80011e4:	f0c0 8082 	bcc.w	80012ec <HAL_RCC_ClockConfig+0x130>
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 80011e8:	682a      	ldr	r2, [r5, #0]
 80011ea:	4c4a      	ldr	r4, [pc, #296]	; (8001314 <HAL_RCC_ClockConfig+0x158>)
 80011ec:	f012 0f04 	tst.w	r2, #4
 80011f0:	f040 8087 	bne.w	8001302 <HAL_RCC_ClockConfig+0x146>
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
 80011f4:	0713      	lsls	r3, r2, #28
 80011f6:	d506      	bpl.n	8001206 <HAL_RCC_ClockConfig+0x4a>
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
 80011f8:	6863      	ldr	r3, [r4, #4]
 80011fa:	692a      	ldr	r2, [r5, #16]
 80011fc:	f423 5360 	bic.w	r3, r3, #14336	; 0x3800
 8001200:	ea43 03c2 	orr.w	r3, r3, r2, lsl #3
 8001204:	6063      	str	r3, [r4, #4]
  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
 8001206:	f7ff ff9d 	bl	8001144 <HAL_RCC_GetSysClockFreq>
 800120a:	6863      	ldr	r3, [r4, #4]
 800120c:	4a42      	ldr	r2, [pc, #264]	; (8001318 <HAL_RCC_ClockConfig+0x15c>)
 800120e:	f3c3 1303 	ubfx	r3, r3, #4, #4
 8001212:	5cd3      	ldrb	r3, [r2, r3]
 8001214:	40d8      	lsrs	r0, r3
 8001216:	4b41      	ldr	r3, [pc, #260]	; (800131c <HAL_RCC_ClockConfig+0x160>)
 8001218:	6018      	str	r0, [r3, #0]
  HAL_InitTick (TICK_INT_PRIORITY);
 800121a:	2000      	movs	r0, #0
 800121c:	f7ff f802 	bl	8000224 <HAL_InitTick>
  return HAL_OK;
 8001220:	2000      	movs	r0, #0
}
 8001222:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    __HAL_FLASH_SET_LATENCY(FLatency);
 8001226:	6813      	ldr	r3, [r2, #0]
 8001228:	f023 0307 	bic.w	r3, r3, #7
 800122c:	430b      	orrs	r3, r1
 800122e:	6013      	str	r3, [r2, #0]
    if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
 8001230:	6813      	ldr	r3, [r2, #0]
 8001232:	f003 0307 	and.w	r3, r3, #7
 8001236:	4299      	cmp	r1, r3
 8001238:	d0ca      	beq.n	80011d0 <HAL_RCC_ClockConfig+0x14>
      return HAL_ERROR;
 800123a:	2001      	movs	r0, #1
 800123c:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
 8001240:	4b34      	ldr	r3, [pc, #208]	; (8001314 <HAL_RCC_ClockConfig+0x158>)
    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 8001242:	f011 0f04 	tst.w	r1, #4
      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
 8001246:	bf1e      	ittt	ne
 8001248:	685a      	ldrne	r2, [r3, #4]
 800124a:	f442 62e0 	orrne.w	r2, r2, #1792	; 0x700
 800124e:	605a      	strne	r2, [r3, #4]
    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
 8001250:	0708      	lsls	r0, r1, #28
      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
 8001252:	bf42      	ittt	mi
 8001254:	685a      	ldrmi	r2, [r3, #4]
 8001256:	f442 5260 	orrmi.w	r2, r2, #14336	; 0x3800
 800125a:	605a      	strmi	r2, [r3, #4]
    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
 800125c:	685a      	ldr	r2, [r3, #4]
 800125e:	68a8      	ldr	r0, [r5, #8]
 8001260:	f022 02f0 	bic.w	r2, r2, #240	; 0xf0
 8001264:	4302      	orrs	r2, r0
 8001266:	605a      	str	r2, [r3, #4]
 8001268:	e7b5      	b.n	80011d6 <HAL_RCC_ClockConfig+0x1a>
    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 800126a:	686a      	ldr	r2, [r5, #4]
 800126c:	4c29      	ldr	r4, [pc, #164]	; (8001314 <HAL_RCC_ClockConfig+0x158>)
 800126e:	2a01      	cmp	r2, #1
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 8001270:	6823      	ldr	r3, [r4, #0]
    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 8001272:	d11c      	bne.n	80012ae <HAL_RCC_ClockConfig+0xf2>
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 8001274:	f413 3f00 	tst.w	r3, #131072	; 0x20000
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 8001278:	d0df      	beq.n	800123a <HAL_RCC_ClockConfig+0x7e>
    __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
 800127a:	6863      	ldr	r3, [r4, #4]
        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
 800127c:	f241 3888 	movw	r8, #5000	; 0x1388
    __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
 8001280:	f023 0303 	bic.w	r3, r3, #3
 8001284:	4313      	orrs	r3, r2
 8001286:	6063      	str	r3, [r4, #4]
    tickstart = HAL_GetTick();
 8001288:	f7ff f80e 	bl	80002a8 <HAL_GetTick>
    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 800128c:	686b      	ldr	r3, [r5, #4]
    tickstart = HAL_GetTick();
 800128e:	4607      	mov	r7, r0
    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 8001290:	2b01      	cmp	r3, #1
 8001292:	d114      	bne.n	80012be <HAL_RCC_ClockConfig+0x102>
      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
 8001294:	6863      	ldr	r3, [r4, #4]
 8001296:	f003 030c 	and.w	r3, r3, #12
 800129a:	2b04      	cmp	r3, #4
 800129c:	d09d      	beq.n	80011da <HAL_RCC_ClockConfig+0x1e>
        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
 800129e:	f7ff f803 	bl	80002a8 <HAL_GetTick>
 80012a2:	1bc0      	subs	r0, r0, r7
 80012a4:	4540      	cmp	r0, r8
 80012a6:	d9f5      	bls.n	8001294 <HAL_RCC_ClockConfig+0xd8>
          return HAL_TIMEOUT;
 80012a8:	2003      	movs	r0, #3
 80012aa:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
 80012ae:	2a02      	cmp	r2, #2
 80012b0:	d102      	bne.n	80012b8 <HAL_RCC_ClockConfig+0xfc>
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
 80012b2:	f013 7f00 	tst.w	r3, #33554432	; 0x2000000
 80012b6:	e7df      	b.n	8001278 <HAL_RCC_ClockConfig+0xbc>
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 80012b8:	f013 0f02 	tst.w	r3, #2
 80012bc:	e7dc      	b.n	8001278 <HAL_RCC_ClockConfig+0xbc>
    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
 80012be:	2b02      	cmp	r3, #2
 80012c0:	d10f      	bne.n	80012e2 <HAL_RCC_ClockConfig+0x126>
      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
 80012c2:	6863      	ldr	r3, [r4, #4]
 80012c4:	f003 030c 	and.w	r3, r3, #12
 80012c8:	2b08      	cmp	r3, #8
 80012ca:	d086      	beq.n	80011da <HAL_RCC_ClockConfig+0x1e>
        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
 80012cc:	f7fe ffec 	bl	80002a8 <HAL_GetTick>
 80012d0:	1bc0      	subs	r0, r0, r7
 80012d2:	4540      	cmp	r0, r8
 80012d4:	d9f5      	bls.n	80012c2 <HAL_RCC_ClockConfig+0x106>
 80012d6:	e7e7      	b.n	80012a8 <HAL_RCC_ClockConfig+0xec>
        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
 80012d8:	f7fe ffe6 	bl	80002a8 <HAL_GetTick>
 80012dc:	1bc0      	subs	r0, r0, r7
 80012de:	4540      	cmp	r0, r8
 80012e0:	d8e2      	bhi.n	80012a8 <HAL_RCC_ClockConfig+0xec>
      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
 80012e2:	6863      	ldr	r3, [r4, #4]
 80012e4:	f013 0f0c 	tst.w	r3, #12
 80012e8:	d1f6      	bne.n	80012d8 <HAL_RCC_ClockConfig+0x11c>
 80012ea:	e776      	b.n	80011da <HAL_RCC_ClockConfig+0x1e>
    __HAL_FLASH_SET_LATENCY(FLatency);
 80012ec:	6813      	ldr	r3, [r2, #0]
 80012ee:	f023 0307 	bic.w	r3, r3, #7
 80012f2:	4333      	orrs	r3, r6
 80012f4:	6013      	str	r3, [r2, #0]
    if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
 80012f6:	6813      	ldr	r3, [r2, #0]
 80012f8:	f003 0307 	and.w	r3, r3, #7
 80012fc:	429e      	cmp	r6, r3
 80012fe:	d19c      	bne.n	800123a <HAL_RCC_ClockConfig+0x7e>
 8001300:	e772      	b.n	80011e8 <HAL_RCC_ClockConfig+0x2c>
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
 8001302:	6863      	ldr	r3, [r4, #4]
 8001304:	68e9      	ldr	r1, [r5, #12]
 8001306:	f423 63e0 	bic.w	r3, r3, #1792	; 0x700
 800130a:	430b      	orrs	r3, r1
 800130c:	6063      	str	r3, [r4, #4]
 800130e:	e771      	b.n	80011f4 <HAL_RCC_ClockConfig+0x38>
 8001310:	40022000 	.word	0x40022000
 8001314:	40021000 	.word	0x40021000
 8001318:	08001f58 	.word	0x08001f58
 800131c:	20000008 	.word	0x20000008

08001320 <HAL_RCC_GetPCLK1Freq>:
  return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
 8001320:	4b04      	ldr	r3, [pc, #16]	; (8001334 <HAL_RCC_GetPCLK1Freq+0x14>)
 8001322:	4a05      	ldr	r2, [pc, #20]	; (8001338 <HAL_RCC_GetPCLK1Freq+0x18>)
 8001324:	685b      	ldr	r3, [r3, #4]
 8001326:	f3c3 2302 	ubfx	r3, r3, #8, #3
 800132a:	5cd3      	ldrb	r3, [r2, r3]
 800132c:	4a03      	ldr	r2, [pc, #12]	; (800133c <HAL_RCC_GetPCLK1Freq+0x1c>)
 800132e:	6810      	ldr	r0, [r2, #0]
}    
 8001330:	40d8      	lsrs	r0, r3
 8001332:	4770      	bx	lr
 8001334:	40021000 	.word	0x40021000
 8001338:	08001f68 	.word	0x08001f68
 800133c:	20000008 	.word	0x20000008

08001340 <HAL_RCC_GetPCLK2Freq>:
  return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
 8001340:	4b04      	ldr	r3, [pc, #16]	; (8001354 <HAL_RCC_GetPCLK2Freq+0x14>)
 8001342:	4a05      	ldr	r2, [pc, #20]	; (8001358 <HAL_RCC_GetPCLK2Freq+0x18>)
 8001344:	685b      	ldr	r3, [r3, #4]
 8001346:	f3c3 23c2 	ubfx	r3, r3, #11, #3
 800134a:	5cd3      	ldrb	r3, [r2, r3]
 800134c:	4a03      	ldr	r2, [pc, #12]	; (800135c <HAL_RCC_GetPCLK2Freq+0x1c>)
 800134e:	6810      	ldr	r0, [r2, #0]
} 
 8001350:	40d8      	lsrs	r0, r3
 8001352:	4770      	bx	lr
 8001354:	40021000 	.word	0x40021000
 8001358:	08001f68 	.word	0x08001f68
 800135c:	20000008 	.word	0x20000008

08001360 <HAL_RCCEx_PeriphCLKConfig>:

  /* Check the parameters */
  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
  
  /*------------------------------- RTC/LCD Configuration ------------------------*/ 
  if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
 8001360:	6803      	ldr	r3, [r0, #0]
{
 8001362:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
  if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
 8001366:	07d9      	lsls	r1, r3, #31
{
 8001368:	4605      	mov	r5, r0
  if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
 800136a:	d520      	bpl.n	80013ae <HAL_RCCEx_PeriphCLKConfig+0x4e>
    FlagStatus       pwrclkchanged = RESET;

    /* As soon as function is called to change RTC clock source, activation of the 
       power domain is done. */
    /* Requires to enable write access to Backup Domain of necessary */
    if(__HAL_RCC_PWR_IS_CLK_DISABLED())
 800136c:	4c35      	ldr	r4, [pc, #212]	; (8001444 <HAL_RCCEx_PeriphCLKConfig+0xe4>)
 800136e:	69e3      	ldr	r3, [r4, #28]
 8001370:	00da      	lsls	r2, r3, #3
 8001372:	d432      	bmi.n	80013da <HAL_RCCEx_PeriphCLKConfig+0x7a>
    {
    __HAL_RCC_PWR_CLK_ENABLE();
      pwrclkchanged = SET;
 8001374:	2701      	movs	r7, #1
    __HAL_RCC_PWR_CLK_ENABLE();
 8001376:	69e3      	ldr	r3, [r4, #28]
 8001378:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
 800137c:	61e3      	str	r3, [r4, #28]
 800137e:	69e3      	ldr	r3, [r4, #28]
 8001380:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8001384:	9301      	str	r3, [sp, #4]
 8001386:	9b01      	ldr	r3, [sp, #4]
    }
    
    if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 8001388:	4e2f      	ldr	r6, [pc, #188]	; (8001448 <HAL_RCCEx_PeriphCLKConfig+0xe8>)
 800138a:	6833      	ldr	r3, [r6, #0]
 800138c:	05db      	lsls	r3, r3, #23
 800138e:	d526      	bpl.n	80013de <HAL_RCCEx_PeriphCLKConfig+0x7e>
        }
      }
    }
      
    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ 
    temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
 8001390:	6a23      	ldr	r3, [r4, #32]
    if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
 8001392:	f413 7340 	ands.w	r3, r3, #768	; 0x300
 8001396:	d136      	bne.n	8001406 <HAL_RCCEx_PeriphCLKConfig+0xa6>
            return HAL_TIMEOUT;
          }      
        }  
      }
    }
    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 
 8001398:	6a23      	ldr	r3, [r4, #32]
 800139a:	686a      	ldr	r2, [r5, #4]
 800139c:	f423 7340 	bic.w	r3, r3, #768	; 0x300
 80013a0:	4313      	orrs	r3, r2
 80013a2:	6223      	str	r3, [r4, #32]

    /* Require to disable power clock if necessary */
    if(pwrclkchanged == SET)
 80013a4:	b11f      	cbz	r7, 80013ae <HAL_RCCEx_PeriphCLKConfig+0x4e>
    {
      __HAL_RCC_PWR_CLK_DISABLE();
 80013a6:	69e3      	ldr	r3, [r4, #28]
 80013a8:	f023 5380 	bic.w	r3, r3, #268435456	; 0x10000000
 80013ac:	61e3      	str	r3, [r4, #28]
    }
  }

  /*------------------------------ ADC clock Configuration ------------------*/ 
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
 80013ae:	6828      	ldr	r0, [r5, #0]
 80013b0:	0783      	lsls	r3, r0, #30
 80013b2:	d506      	bpl.n	80013c2 <HAL_RCCEx_PeriphCLKConfig+0x62>
  {
    /* Check the parameters */
    assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection));
    
    /* Configure the ADC clock source */
    __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
 80013b4:	4a23      	ldr	r2, [pc, #140]	; (8001444 <HAL_RCCEx_PeriphCLKConfig+0xe4>)
 80013b6:	68a9      	ldr	r1, [r5, #8]
 80013b8:	6853      	ldr	r3, [r2, #4]
 80013ba:	f423 4340 	bic.w	r3, r3, #49152	; 0xc000
 80013be:	430b      	orrs	r3, r1
 80013c0:	6053      	str	r3, [r2, #4]

#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
 || defined(STM32F105xC) || defined(STM32F107xC)
  /*------------------------------ USB clock Configuration ------------------*/ 
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
 80013c2:	f010 0010 	ands.w	r0, r0, #16
 80013c6:	d01b      	beq.n	8001400 <HAL_RCCEx_PeriphCLKConfig+0xa0>
  {
    /* Check the parameters */
    assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection));
    
    /* Configure the USB clock source */
    __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
 80013c8:	4a1e      	ldr	r2, [pc, #120]	; (8001444 <HAL_RCCEx_PeriphCLKConfig+0xe4>)
 80013ca:	6969      	ldr	r1, [r5, #20]
 80013cc:	6853      	ldr	r3, [r2, #4]
  }
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */

  return HAL_OK;
 80013ce:	2000      	movs	r0, #0
    __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
 80013d0:	f423 0380 	bic.w	r3, r3, #4194304	; 0x400000
 80013d4:	430b      	orrs	r3, r1
 80013d6:	6053      	str	r3, [r2, #4]
 80013d8:	e012      	b.n	8001400 <HAL_RCCEx_PeriphCLKConfig+0xa0>
    FlagStatus       pwrclkchanged = RESET;
 80013da:	2700      	movs	r7, #0
 80013dc:	e7d4      	b.n	8001388 <HAL_RCCEx_PeriphCLKConfig+0x28>
      SET_BIT(PWR->CR, PWR_CR_DBP);
 80013de:	6833      	ldr	r3, [r6, #0]
 80013e0:	f443 7380 	orr.w	r3, r3, #256	; 0x100
 80013e4:	6033      	str	r3, [r6, #0]
      tickstart = HAL_GetTick();
 80013e6:	f7fe ff5f 	bl	80002a8 <HAL_GetTick>
 80013ea:	4680      	mov	r8, r0
      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 80013ec:	6833      	ldr	r3, [r6, #0]
 80013ee:	05d8      	lsls	r0, r3, #23
 80013f0:	d4ce      	bmi.n	8001390 <HAL_RCCEx_PeriphCLKConfig+0x30>
        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
 80013f2:	f7fe ff59 	bl	80002a8 <HAL_GetTick>
 80013f6:	eba0 0008 	sub.w	r0, r0, r8
 80013fa:	2864      	cmp	r0, #100	; 0x64
 80013fc:	d9f6      	bls.n	80013ec <HAL_RCCEx_PeriphCLKConfig+0x8c>
          return HAL_TIMEOUT;
 80013fe:	2003      	movs	r0, #3
}
 8001400:	b002      	add	sp, #8
 8001402:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
 8001406:	686a      	ldr	r2, [r5, #4]
 8001408:	f402 7240 	and.w	r2, r2, #768	; 0x300
 800140c:	4293      	cmp	r3, r2
 800140e:	d0c3      	beq.n	8001398 <HAL_RCCEx_PeriphCLKConfig+0x38>
      __HAL_RCC_BACKUPRESET_FORCE();
 8001410:	2001      	movs	r0, #1
 8001412:	4a0e      	ldr	r2, [pc, #56]	; (800144c <HAL_RCCEx_PeriphCLKConfig+0xec>)
      temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
 8001414:	6a23      	ldr	r3, [r4, #32]
      __HAL_RCC_BACKUPRESET_FORCE();
 8001416:	6010      	str	r0, [r2, #0]
      __HAL_RCC_BACKUPRESET_RELEASE();
 8001418:	2000      	movs	r0, #0
      temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
 800141a:	f423 7140 	bic.w	r1, r3, #768	; 0x300
      __HAL_RCC_BACKUPRESET_RELEASE();
 800141e:	6010      	str	r0, [r2, #0]
      RCC->BDCR = temp_reg;
 8001420:	6221      	str	r1, [r4, #32]
      if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
 8001422:	07d9      	lsls	r1, r3, #31
 8001424:	d5b8      	bpl.n	8001398 <HAL_RCCEx_PeriphCLKConfig+0x38>
        tickstart = HAL_GetTick();
 8001426:	f7fe ff3f 	bl	80002a8 <HAL_GetTick>
          if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 800142a:	f241 3888 	movw	r8, #5000	; 0x1388
        tickstart = HAL_GetTick();
 800142e:	4606      	mov	r6, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
 8001430:	6a23      	ldr	r3, [r4, #32]
 8001432:	079a      	lsls	r2, r3, #30
 8001434:	d4b0      	bmi.n	8001398 <HAL_RCCEx_PeriphCLKConfig+0x38>
          if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 8001436:	f7fe ff37 	bl	80002a8 <HAL_GetTick>
 800143a:	1b80      	subs	r0, r0, r6
 800143c:	4540      	cmp	r0, r8
 800143e:	d9f7      	bls.n	8001430 <HAL_RCCEx_PeriphCLKConfig+0xd0>
 8001440:	e7dd      	b.n	80013fe <HAL_RCCEx_PeriphCLKConfig+0x9e>
 8001442:	bf00      	nop
 8001444:	40021000 	.word	0x40021000
 8001448:	40007000 	.word	0x40007000
 800144c:	42420440 	.word	0x42420440

08001450 <HAL_RCCEx_GetPeriphCLKFreq>:
  *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock
  @endif
  * @retval Frequency in Hz (0: means that no available frequency for the peripheral)
  */
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
{
 8001450:	4602      	mov	r2, r0
 8001452:	b570      	push	{r4, r5, r6, lr}
  uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U;
  uint32_t pll2mul = 0U, pll3mul = 0U, prediv2 = 0U;
#endif /* STM32F105xC || STM32F107xC */
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || \
    defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
  const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
 8001454:	4b3b      	ldr	r3, [pc, #236]	; (8001544 <HAL_RCCEx_GetPeriphCLKFreq+0xf4>)
{
 8001456:	b086      	sub	sp, #24
  const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
 8001458:	ad02      	add	r5, sp, #8
 800145a:	f103 0610 	add.w	r6, r3, #16
 800145e:	462c      	mov	r4, r5
 8001460:	6818      	ldr	r0, [r3, #0]
 8001462:	6859      	ldr	r1, [r3, #4]
 8001464:	3308      	adds	r3, #8
 8001466:	c403      	stmia	r4!, {r0, r1}
 8001468:	42b3      	cmp	r3, r6
 800146a:	4625      	mov	r5, r4
 800146c:	d1f7      	bne.n	800145e <HAL_RCCEx_GetPeriphCLKFreq+0xe>
  const uint8_t aPredivFactorTable[2] = {1, 2};
 800146e:	2301      	movs	r3, #1
 8001470:	f88d 3004 	strb.w	r3, [sp, #4]
 8001474:	2302      	movs	r3, #2
  uint32_t temp_reg = 0U, frequency = 0U;

  /* Check the parameters */
  assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
  
  switch (PeriphClk)
 8001476:	1e50      	subs	r0, r2, #1
  const uint8_t aPredivFactorTable[2] = {1, 2};
 8001478:	f88d 3005 	strb.w	r3, [sp, #5]
  switch (PeriphClk)
 800147c:	280f      	cmp	r0, #15
 800147e:	d85e      	bhi.n	800153e <HAL_RCCEx_GetPeriphCLKFreq+0xee>
 8001480:	e8df f000 	tbb	[pc, r0]
 8001484:	2d5d5132 	.word	0x2d5d5132
 8001488:	2d5d5d5d 	.word	0x2d5d5d5d
 800148c:	5d5d5d5d 	.word	0x5d5d5d5d
 8001490:	085d5d5d 	.word	0x085d5d5d
 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
 || defined(STM32F105xC) || defined(STM32F107xC)
  case RCC_PERIPHCLK_USB:  
    {
      /* Get RCC configuration ------------------------------------------------------*/
      temp_reg = RCC->CFGR;
 8001494:	4b2c      	ldr	r3, [pc, #176]	; (8001548 <HAL_RCCEx_GetPeriphCLKFreq+0xf8>)
 8001496:	6859      	ldr	r1, [r3, #4]
  
      /* Check if PLL is enabled */
      if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLLON))
 8001498:	6818      	ldr	r0, [r3, #0]
 800149a:	f010 7080 	ands.w	r0, r0, #16777216	; 0x1000000
 800149e:	d037      	beq.n	8001510 <HAL_RCCEx_GetPeriphCLKFreq+0xc0>
      {
        pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
 80014a0:	f3c1 4283 	ubfx	r2, r1, #18, #4
 80014a4:	a806      	add	r0, sp, #24
 80014a6:	4402      	add	r2, r0
 80014a8:	f812 0c10 	ldrb.w	r0, [r2, #-16]
        if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
 80014ac:	03ca      	lsls	r2, r1, #15
        {
#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
 || defined(STM32F100xE)
          prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
#else
          prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
 80014ae:	bf41      	itttt	mi
 80014b0:	685a      	ldrmi	r2, [r3, #4]
 80014b2:	a906      	addmi	r1, sp, #24
 80014b4:	f3c2 4240 	ubfxmi	r2, r2, #17, #1
 80014b8:	1852      	addmi	r2, r2, r1
 80014ba:	bf44      	itt	mi
 80014bc:	f812 1c14 	ldrbmi.w	r1, [r2, #-20]
          }
#else
          if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
          {
            /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
            pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
 80014c0:	4a22      	ldrmi	r2, [pc, #136]	; (800154c <HAL_RCCEx_GetPeriphCLKFreq+0xfc>)
          /* Prescaler of 3 selected for USB */ 
          frequency = (2 * pllclk) / 3;
        }
#else
        /* USBCLK = PLLCLK / USB prescaler */
        if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL)
 80014c2:	685b      	ldr	r3, [r3, #4]
            pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
 80014c4:	bf4c      	ite	mi
 80014c6:	fbb2 f2f1 	udivmi	r2, r2, r1
          pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
 80014ca:	4a21      	ldrpl	r2, [pc, #132]	; (8001550 <HAL_RCCEx_GetPeriphCLKFreq+0x100>)
        if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL)
 80014cc:	025b      	lsls	r3, r3, #9
          pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
 80014ce:	fb02 f000 	mul.w	r0, r2, r0
        if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL)
 80014d2:	d41d      	bmi.n	8001510 <HAL_RCCEx_GetPeriphCLKFreq+0xc0>
          frequency = pllclk;
        }
        else
        {
          /* Prescaler of 1.5 selected for USB */ 
          frequency = (pllclk * 2) / 3;
 80014d4:	2303      	movs	r3, #3
 80014d6:	0040      	lsls	r0, r0, #1
      }
      break;
    }
  case RCC_PERIPHCLK_ADC:  
    {
      frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2);
 80014d8:	fbb0 f0f3 	udiv	r0, r0, r3
      break;
 80014dc:	e018      	b.n	8001510 <HAL_RCCEx_GetPeriphCLKFreq+0xc0>
    {
      break;
    }
  }
  return(frequency);
}
 80014de:	b006      	add	sp, #24
 80014e0:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
      frequency = HAL_RCC_GetSysClockFreq();
 80014e4:	f7ff be2e 	b.w	8001144 <HAL_RCC_GetSysClockFreq>
      if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY)))
 80014e8:	f240 3102 	movw	r1, #770	; 0x302
      temp_reg = RCC->BDCR;
 80014ec:	4a16      	ldr	r2, [pc, #88]	; (8001548 <HAL_RCCEx_GetPeriphCLKFreq+0xf8>)
 80014ee:	6a13      	ldr	r3, [r2, #32]
      if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY)))
 80014f0:	4019      	ands	r1, r3
 80014f2:	f5b1 7f81 	cmp.w	r1, #258	; 0x102
 80014f6:	d01f      	beq.n	8001538 <HAL_RCCEx_GetPeriphCLKFreq+0xe8>
      else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
 80014f8:	f403 7340 	and.w	r3, r3, #768	; 0x300
 80014fc:	f5b3 7f00 	cmp.w	r3, #512	; 0x200
 8001500:	d108      	bne.n	8001514 <HAL_RCCEx_GetPeriphCLKFreq+0xc4>
        frequency = LSI_VALUE;
 8001502:	f649 4040 	movw	r0, #40000	; 0x9c40
      else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
 8001506:	6a53      	ldr	r3, [r2, #36]	; 0x24
        frequency = LSI_VALUE;
 8001508:	f013 0f02 	tst.w	r3, #2
        frequency = HSE_VALUE / 128U;
 800150c:	bf08      	it	eq
 800150e:	2000      	moveq	r0, #0
}
 8001510:	b006      	add	sp, #24
 8001512:	bd70      	pop	{r4, r5, r6, pc}
      else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)))
 8001514:	f5b3 7f40 	cmp.w	r3, #768	; 0x300
 8001518:	d111      	bne.n	800153e <HAL_RCCEx_GetPeriphCLKFreq+0xee>
 800151a:	6813      	ldr	r3, [r2, #0]
        frequency = HSE_VALUE / 128U;
 800151c:	f24f 4024 	movw	r0, #62500	; 0xf424
 8001520:	f413 3f00 	tst.w	r3, #131072	; 0x20000
 8001524:	e7f2      	b.n	800150c <HAL_RCCEx_GetPeriphCLKFreq+0xbc>
      frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2);
 8001526:	f7ff ff0b 	bl	8001340 <HAL_RCC_GetPCLK2Freq>
 800152a:	4b07      	ldr	r3, [pc, #28]	; (8001548 <HAL_RCCEx_GetPeriphCLKFreq+0xf8>)
 800152c:	685b      	ldr	r3, [r3, #4]
 800152e:	f3c3 3381 	ubfx	r3, r3, #14, #2
 8001532:	3301      	adds	r3, #1
 8001534:	005b      	lsls	r3, r3, #1
 8001536:	e7cf      	b.n	80014d8 <HAL_RCCEx_GetPeriphCLKFreq+0x88>
        frequency = LSE_VALUE;
 8001538:	f44f 4000 	mov.w	r0, #32768	; 0x8000
 800153c:	e7e8      	b.n	8001510 <HAL_RCCEx_GetPeriphCLKFreq+0xc0>
        frequency = 0U;
 800153e:	2000      	movs	r0, #0
 8001540:	e7e6      	b.n	8001510 <HAL_RCCEx_GetPeriphCLKFreq+0xc0>
 8001542:	bf00      	nop
 8001544:	08001f48 	.word	0x08001f48
 8001548:	40021000 	.word	0x40021000
 800154c:	007a1200 	.word	0x007a1200
 8001550:	003d0900 	.word	0x003d0900

08001554 <UART_EndRxTransfer>:
  * @retval None
  */
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
{
  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
 8001554:	6803      	ldr	r3, [r0, #0]
 8001556:	68da      	ldr	r2, [r3, #12]
 8001558:	f422 7290 	bic.w	r2, r2, #288	; 0x120
 800155c:	60da      	str	r2, [r3, #12]
  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 800155e:	695a      	ldr	r2, [r3, #20]
 8001560:	f022 0201 	bic.w	r2, r2, #1
 8001564:	615a      	str	r2, [r3, #20]

  /* At end of Rx process, restore huart->RxState to Ready */
  huart->RxState = HAL_UART_STATE_READY;
 8001566:	2320      	movs	r3, #32
 8001568:	f880 303a 	strb.w	r3, [r0, #58]	; 0x3a
 800156c:	4770      	bx	lr
	...

08001570 <UART_SetConfig>:
  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
  *                the configuration information for the specified UART module.
  * @retval None
  */
static void UART_SetConfig(UART_HandleTypeDef *huart)
{
 8001570:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
  assert_param(IS_UART_MODE(huart->Init.Mode));

  /*------- UART-associated USART registers setting : CR2 Configuration ------*/
  /* Configure the UART Stop Bits: Set STOP[13:12] bits according 
   * to huart->Init.StopBits value */
  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
 8001574:	6805      	ldr	r5, [r0, #0]
 8001576:	68c2      	ldr	r2, [r0, #12]
 8001578:	692b      	ldr	r3, [r5, #16]
  tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
  MODIFY_REG(huart->Instance->CR1, 
             (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), 
             tmpreg);
#else
  tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
 800157a:	6901      	ldr	r1, [r0, #16]
  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
 800157c:	f423 5340 	bic.w	r3, r3, #12288	; 0x3000
 8001580:	4313      	orrs	r3, r2
 8001582:	612b      	str	r3, [r5, #16]
  tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
 8001584:	6883      	ldr	r3, [r0, #8]
  MODIFY_REG(huart->Instance->CR1, 
 8001586:	68ea      	ldr	r2, [r5, #12]
  tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
 8001588:	430b      	orrs	r3, r1
 800158a:	6941      	ldr	r1, [r0, #20]
  MODIFY_REG(huart->Instance->CR1, 
 800158c:	f422 52b0 	bic.w	r2, r2, #5632	; 0x1600
 8001590:	f022 020c 	bic.w	r2, r2, #12
  tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
 8001594:	430b      	orrs	r3, r1
  MODIFY_REG(huart->Instance->CR1, 
 8001596:	4313      	orrs	r3, r2
 8001598:	60eb      	str	r3, [r5, #12]
             tmpreg);
#endif /* USART_CR1_OVER8 */

  /*------- UART-associated USART registers setting : CR3 Configuration ------*/
  /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
  MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
 800159a:	696b      	ldr	r3, [r5, #20]
 800159c:	6982      	ldr	r2, [r0, #24]
 800159e:	f423 7340 	bic.w	r3, r3, #768	; 0x300
 80015a2:	4313      	orrs	r3, r2
 80015a4:	616b      	str	r3, [r5, #20]
      huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
    }
  }
#else
  /*-------------------------- USART BRR Configuration ---------------------*/
  if(huart->Instance == USART1)
 80015a6:	4b40      	ldr	r3, [pc, #256]	; (80016a8 <UART_SetConfig+0x138>)
{
 80015a8:	4681      	mov	r9, r0
  if(huart->Instance == USART1)
 80015aa:	429d      	cmp	r5, r3
 80015ac:	f04f 0419 	mov.w	r4, #25
 80015b0:	d146      	bne.n	8001640 <UART_SetConfig+0xd0>
  {
    huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
 80015b2:	f7ff fec5 	bl	8001340 <HAL_RCC_GetPCLK2Freq>
 80015b6:	fb04 f300 	mul.w	r3, r4, r0
 80015ba:	f8d9 6004 	ldr.w	r6, [r9, #4]
 80015be:	f04f 0864 	mov.w	r8, #100	; 0x64
 80015c2:	00b6      	lsls	r6, r6, #2
 80015c4:	fbb3 f3f6 	udiv	r3, r3, r6
 80015c8:	fbb3 f3f8 	udiv	r3, r3, r8
 80015cc:	011e      	lsls	r6, r3, #4
 80015ce:	f7ff feb7 	bl	8001340 <HAL_RCC_GetPCLK2Freq>
 80015d2:	4360      	muls	r0, r4
 80015d4:	f8d9 3004 	ldr.w	r3, [r9, #4]
 80015d8:	009b      	lsls	r3, r3, #2
 80015da:	fbb0 f7f3 	udiv	r7, r0, r3
 80015de:	f7ff feaf 	bl	8001340 <HAL_RCC_GetPCLK2Freq>
 80015e2:	4360      	muls	r0, r4
 80015e4:	f8d9 3004 	ldr.w	r3, [r9, #4]
 80015e8:	009b      	lsls	r3, r3, #2
 80015ea:	fbb0 f3f3 	udiv	r3, r0, r3
 80015ee:	fbb3 f3f8 	udiv	r3, r3, r8
 80015f2:	fb08 7313 	mls	r3, r8, r3, r7
 80015f6:	011b      	lsls	r3, r3, #4
 80015f8:	3332      	adds	r3, #50	; 0x32
 80015fa:	fbb3 f3f8 	udiv	r3, r3, r8
 80015fe:	f003 07f0 	and.w	r7, r3, #240	; 0xf0
 8001602:	f7ff fe9d 	bl	8001340 <HAL_RCC_GetPCLK2Freq>
 8001606:	4360      	muls	r0, r4
 8001608:	f8d9 2004 	ldr.w	r2, [r9, #4]
 800160c:	0092      	lsls	r2, r2, #2
 800160e:	fbb0 faf2 	udiv	sl, r0, r2
 8001612:	f7ff fe95 	bl	8001340 <HAL_RCC_GetPCLK2Freq>
  }
  else
  {
    huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
 8001616:	4360      	muls	r0, r4
 8001618:	f8d9 3004 	ldr.w	r3, [r9, #4]
 800161c:	009b      	lsls	r3, r3, #2
 800161e:	fbb0 f3f3 	udiv	r3, r0, r3
 8001622:	fbb3 f3f8 	udiv	r3, r3, r8
 8001626:	fb08 a313 	mls	r3, r8, r3, sl
 800162a:	011b      	lsls	r3, r3, #4
 800162c:	3332      	adds	r3, #50	; 0x32
 800162e:	fbb3 f3f8 	udiv	r3, r3, r8
 8001632:	f003 030f 	and.w	r3, r3, #15
 8001636:	433b      	orrs	r3, r7
 8001638:	4433      	add	r3, r6
 800163a:	60ab      	str	r3, [r5, #8]
 800163c:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 8001640:	f7ff fe6e 	bl	8001320 <HAL_RCC_GetPCLK1Freq>
 8001644:	fb04 f300 	mul.w	r3, r4, r0
 8001648:	f8d9 6004 	ldr.w	r6, [r9, #4]
 800164c:	f04f 0864 	mov.w	r8, #100	; 0x64
 8001650:	00b6      	lsls	r6, r6, #2
 8001652:	fbb3 f3f6 	udiv	r3, r3, r6
 8001656:	fbb3 f3f8 	udiv	r3, r3, r8
 800165a:	011e      	lsls	r6, r3, #4
 800165c:	f7ff fe60 	bl	8001320 <HAL_RCC_GetPCLK1Freq>
 8001660:	4360      	muls	r0, r4
 8001662:	f8d9 3004 	ldr.w	r3, [r9, #4]
 8001666:	009b      	lsls	r3, r3, #2
 8001668:	fbb0 f7f3 	udiv	r7, r0, r3
 800166c:	f7ff fe58 	bl	8001320 <HAL_RCC_GetPCLK1Freq>
 8001670:	4360      	muls	r0, r4
 8001672:	f8d9 3004 	ldr.w	r3, [r9, #4]
 8001676:	009b      	lsls	r3, r3, #2
 8001678:	fbb0 f3f3 	udiv	r3, r0, r3
 800167c:	fbb3 f3f8 	udiv	r3, r3, r8
 8001680:	fb08 7313 	mls	r3, r8, r3, r7
 8001684:	011b      	lsls	r3, r3, #4
 8001686:	3332      	adds	r3, #50	; 0x32
 8001688:	fbb3 f3f8 	udiv	r3, r3, r8
 800168c:	f003 07f0 	and.w	r7, r3, #240	; 0xf0
 8001690:	f7ff fe46 	bl	8001320 <HAL_RCC_GetPCLK1Freq>
 8001694:	4360      	muls	r0, r4
 8001696:	f8d9 2004 	ldr.w	r2, [r9, #4]
 800169a:	0092      	lsls	r2, r2, #2
 800169c:	fbb0 faf2 	udiv	sl, r0, r2
 80016a0:	f7ff fe3e 	bl	8001320 <HAL_RCC_GetPCLK1Freq>
 80016a4:	e7b7      	b.n	8001616 <UART_SetConfig+0xa6>
 80016a6:	bf00      	nop
 80016a8:	40013800 	.word	0x40013800

080016ac <HAL_UART_Init>:
{
 80016ac:	b510      	push	{r4, lr}
  if(huart == NULL)
 80016ae:	4604      	mov	r4, r0
 80016b0:	b340      	cbz	r0, 8001704 <HAL_UART_Init+0x58>
  if(huart->gState == HAL_UART_STATE_RESET)
 80016b2:	f890 3039 	ldrb.w	r3, [r0, #57]	; 0x39
 80016b6:	f003 02ff 	and.w	r2, r3, #255	; 0xff
 80016ba:	b91b      	cbnz	r3, 80016c4 <HAL_UART_Init+0x18>
    huart->Lock = HAL_UNLOCKED;
 80016bc:	f880 2038 	strb.w	r2, [r0, #56]	; 0x38
    HAL_UART_MspInit(huart);
 80016c0:	f000 fb64 	bl	8001d8c <HAL_UART_MspInit>
  huart->gState = HAL_UART_STATE_BUSY;
 80016c4:	2324      	movs	r3, #36	; 0x24
  __HAL_UART_DISABLE(huart);
 80016c6:	6822      	ldr	r2, [r4, #0]
  huart->gState = HAL_UART_STATE_BUSY;
 80016c8:	f884 3039 	strb.w	r3, [r4, #57]	; 0x39
  __HAL_UART_DISABLE(huart);
 80016cc:	68d3      	ldr	r3, [r2, #12]
  UART_SetConfig(huart);
 80016ce:	4620      	mov	r0, r4
  __HAL_UART_DISABLE(huart);
 80016d0:	f423 5300 	bic.w	r3, r3, #8192	; 0x2000
 80016d4:	60d3      	str	r3, [r2, #12]
  UART_SetConfig(huart);
 80016d6:	f7ff ff4b 	bl	8001570 <UART_SetConfig>
  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
 80016da:	6823      	ldr	r3, [r4, #0]
  huart->ErrorCode = HAL_UART_ERROR_NONE;
 80016dc:	2000      	movs	r0, #0
  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
 80016de:	691a      	ldr	r2, [r3, #16]
 80016e0:	f422 4290 	bic.w	r2, r2, #18432	; 0x4800
 80016e4:	611a      	str	r2, [r3, #16]
  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
 80016e6:	695a      	ldr	r2, [r3, #20]
 80016e8:	f022 022a 	bic.w	r2, r2, #42	; 0x2a
 80016ec:	615a      	str	r2, [r3, #20]
  __HAL_UART_ENABLE(huart);
 80016ee:	68da      	ldr	r2, [r3, #12]
 80016f0:	f442 5200 	orr.w	r2, r2, #8192	; 0x2000
 80016f4:	60da      	str	r2, [r3, #12]
  huart->gState= HAL_UART_STATE_READY;
 80016f6:	2320      	movs	r3, #32
  huart->ErrorCode = HAL_UART_ERROR_NONE;
 80016f8:	63e0      	str	r0, [r4, #60]	; 0x3c
  huart->gState= HAL_UART_STATE_READY;
 80016fa:	f884 3039 	strb.w	r3, [r4, #57]	; 0x39
  huart->RxState= HAL_UART_STATE_READY;
 80016fe:	f884 303a 	strb.w	r3, [r4, #58]	; 0x3a
  return HAL_OK;
 8001702:	bd10      	pop	{r4, pc}
    return HAL_ERROR;
 8001704:	2001      	movs	r0, #1
}
 8001706:	bd10      	pop	{r4, pc}

08001708 <HAL_UART_TxCpltCallback>:
 8001708:	4770      	bx	lr

0800170a <HAL_UART_RxCpltCallback>:
 800170a:	4770      	bx	lr

0800170c <UART_Receive_IT>:
  if(huart->RxState == HAL_UART_STATE_BUSY_RX) 
 800170c:	f890 303a 	ldrb.w	r3, [r0, #58]	; 0x3a
{
 8001710:	b510      	push	{r4, lr}
  if(huart->RxState == HAL_UART_STATE_BUSY_RX) 
 8001712:	2b22      	cmp	r3, #34	; 0x22
 8001714:	d136      	bne.n	8001784 <UART_Receive_IT+0x78>
    if(huart->Init.WordLength == UART_WORDLENGTH_9B)
 8001716:	6883      	ldr	r3, [r0, #8]
 8001718:	6901      	ldr	r1, [r0, #16]
 800171a:	f5b3 5f80 	cmp.w	r3, #4096	; 0x1000
 800171e:	6802      	ldr	r2, [r0, #0]
 8001720:	6a83      	ldr	r3, [r0, #40]	; 0x28
 8001722:	d123      	bne.n	800176c <UART_Receive_IT+0x60>
        *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
 8001724:	6852      	ldr	r2, [r2, #4]
      if(huart->Init.Parity == UART_PARITY_NONE)
 8001726:	b9e9      	cbnz	r1, 8001764 <UART_Receive_IT+0x58>
        *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
 8001728:	f3c2 0208 	ubfx	r2, r2, #0, #9
 800172c:	f823 2b02 	strh.w	r2, [r3], #2
        huart->pRxBuffPtr += 1U;
 8001730:	6283      	str	r3, [r0, #40]	; 0x28
    if(--huart->RxXferCount == 0U)
 8001732:	8dc4      	ldrh	r4, [r0, #46]	; 0x2e
 8001734:	3c01      	subs	r4, #1
 8001736:	b2a4      	uxth	r4, r4
 8001738:	85c4      	strh	r4, [r0, #46]	; 0x2e
 800173a:	b98c      	cbnz	r4, 8001760 <UART_Receive_IT+0x54>
      __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
 800173c:	6803      	ldr	r3, [r0, #0]
 800173e:	68da      	ldr	r2, [r3, #12]
 8001740:	f022 0220 	bic.w	r2, r2, #32
 8001744:	60da      	str	r2, [r3, #12]
      __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
 8001746:	68da      	ldr	r2, [r3, #12]
 8001748:	f422 7280 	bic.w	r2, r2, #256	; 0x100
 800174c:	60da      	str	r2, [r3, #12]
        __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
 800174e:	695a      	ldr	r2, [r3, #20]
 8001750:	f022 0201 	bic.w	r2, r2, #1
 8001754:	615a      	str	r2, [r3, #20]
      huart->RxState = HAL_UART_STATE_READY;
 8001756:	2320      	movs	r3, #32
 8001758:	f880 303a 	strb.w	r3, [r0, #58]	; 0x3a
      HAL_UART_RxCpltCallback(huart);
 800175c:	f7ff ffd5 	bl	800170a <HAL_UART_RxCpltCallback>
    if(--huart->RxXferCount == 0U)
 8001760:	2000      	movs	r0, #0
}
 8001762:	bd10      	pop	{r4, pc}
        *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF);
 8001764:	b2d2      	uxtb	r2, r2
 8001766:	f823 2b01 	strh.w	r2, [r3], #1
 800176a:	e7e1      	b.n	8001730 <UART_Receive_IT+0x24>
      if(huart->Init.Parity == UART_PARITY_NONE)
 800176c:	b921      	cbnz	r1, 8001778 <UART_Receive_IT+0x6c>
        *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
 800176e:	1c59      	adds	r1, r3, #1
 8001770:	6852      	ldr	r2, [r2, #4]
 8001772:	6281      	str	r1, [r0, #40]	; 0x28
        *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
 8001774:	701a      	strb	r2, [r3, #0]
 8001776:	e7dc      	b.n	8001732 <UART_Receive_IT+0x26>
 8001778:	6852      	ldr	r2, [r2, #4]
 800177a:	1c59      	adds	r1, r3, #1
 800177c:	6281      	str	r1, [r0, #40]	; 0x28
 800177e:	f002 027f 	and.w	r2, r2, #127	; 0x7f
 8001782:	e7f7      	b.n	8001774 <UART_Receive_IT+0x68>
    return HAL_BUSY;
 8001784:	2002      	movs	r0, #2
 8001786:	bd10      	pop	{r4, pc}

08001788 <HAL_UART_ErrorCallback>:
 8001788:	4770      	bx	lr
	...

0800178c <HAL_UART_IRQHandler>:
   uint32_t isrflags   = READ_REG(huart->Instance->SR);
 800178c:	6803      	ldr	r3, [r0, #0]
{
 800178e:	b570      	push	{r4, r5, r6, lr}
   uint32_t isrflags   = READ_REG(huart->Instance->SR);
 8001790:	681a      	ldr	r2, [r3, #0]
{
 8001792:	4604      	mov	r4, r0
  if(errorflags == RESET)
 8001794:	0716      	lsls	r6, r2, #28
   uint32_t cr1its     = READ_REG(huart->Instance->CR1);
 8001796:	68d9      	ldr	r1, [r3, #12]
   uint32_t cr3its     = READ_REG(huart->Instance->CR3);
 8001798:	695d      	ldr	r5, [r3, #20]
  if(errorflags == RESET)
 800179a:	d107      	bne.n	80017ac <HAL_UART_IRQHandler+0x20>
    if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
 800179c:	0696      	lsls	r6, r2, #26
 800179e:	d55a      	bpl.n	8001856 <HAL_UART_IRQHandler+0xca>
 80017a0:	068d      	lsls	r5, r1, #26
 80017a2:	d558      	bpl.n	8001856 <HAL_UART_IRQHandler+0xca>
}
 80017a4:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
      UART_Receive_IT(huart);
 80017a8:	f7ff bfb0 	b.w	800170c <UART_Receive_IT>
  if((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
 80017ac:	f015 0501 	ands.w	r5, r5, #1
 80017b0:	d102      	bne.n	80017b8 <HAL_UART_IRQHandler+0x2c>
 80017b2:	f411 7f90 	tst.w	r1, #288	; 0x120
 80017b6:	d04e      	beq.n	8001856 <HAL_UART_IRQHandler+0xca>
    if(((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
 80017b8:	07d3      	lsls	r3, r2, #31
 80017ba:	d505      	bpl.n	80017c8 <HAL_UART_IRQHandler+0x3c>
 80017bc:	05ce      	lsls	r6, r1, #23
      huart->ErrorCode |= HAL_UART_ERROR_PE;
 80017be:	bf42      	ittt	mi
 80017c0:	6be3      	ldrmi	r3, [r4, #60]	; 0x3c
 80017c2:	f043 0301 	orrmi.w	r3, r3, #1
 80017c6:	63e3      	strmi	r3, [r4, #60]	; 0x3c
    if(((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
 80017c8:	0750      	lsls	r0, r2, #29
 80017ca:	d504      	bpl.n	80017d6 <HAL_UART_IRQHandler+0x4a>
 80017cc:	b11d      	cbz	r5, 80017d6 <HAL_UART_IRQHandler+0x4a>
      huart->ErrorCode |= HAL_UART_ERROR_NE;
 80017ce:	6be3      	ldr	r3, [r4, #60]	; 0x3c
 80017d0:	f043 0302 	orr.w	r3, r3, #2
 80017d4:	63e3      	str	r3, [r4, #60]	; 0x3c
    if(((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
 80017d6:	0793      	lsls	r3, r2, #30
 80017d8:	d504      	bpl.n	80017e4 <HAL_UART_IRQHandler+0x58>
 80017da:	b11d      	cbz	r5, 80017e4 <HAL_UART_IRQHandler+0x58>
      huart->ErrorCode |= HAL_UART_ERROR_FE;
 80017dc:	6be3      	ldr	r3, [r4, #60]	; 0x3c
 80017de:	f043 0304 	orr.w	r3, r3, #4
 80017e2:	63e3      	str	r3, [r4, #60]	; 0x3c
    if(((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
 80017e4:	0716      	lsls	r6, r2, #28
 80017e6:	d504      	bpl.n	80017f2 <HAL_UART_IRQHandler+0x66>
 80017e8:	b11d      	cbz	r5, 80017f2 <HAL_UART_IRQHandler+0x66>
      huart->ErrorCode |= HAL_UART_ERROR_ORE;
 80017ea:	6be3      	ldr	r3, [r4, #60]	; 0x3c
 80017ec:	f043 0308 	orr.w	r3, r3, #8
 80017f0:	63e3      	str	r3, [r4, #60]	; 0x3c
    if(huart->ErrorCode != HAL_UART_ERROR_NONE)
 80017f2:	6be3      	ldr	r3, [r4, #60]	; 0x3c
 80017f4:	2b00      	cmp	r3, #0
 80017f6:	d066      	beq.n	80018c6 <HAL_UART_IRQHandler+0x13a>
      if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
 80017f8:	0695      	lsls	r5, r2, #26
 80017fa:	d504      	bpl.n	8001806 <HAL_UART_IRQHandler+0x7a>
 80017fc:	0688      	lsls	r0, r1, #26
 80017fe:	d502      	bpl.n	8001806 <HAL_UART_IRQHandler+0x7a>
        UART_Receive_IT(huart);
 8001800:	4620      	mov	r0, r4
 8001802:	f7ff ff83 	bl	800170c <UART_Receive_IT>
      dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
 8001806:	6823      	ldr	r3, [r4, #0]
        UART_EndRxTransfer(huart);
 8001808:	4620      	mov	r0, r4
      dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
 800180a:	695d      	ldr	r5, [r3, #20]
      if(((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest)
 800180c:	6be2      	ldr	r2, [r4, #60]	; 0x3c
 800180e:	0711      	lsls	r1, r2, #28
 8001810:	d402      	bmi.n	8001818 <HAL_UART_IRQHandler+0x8c>
 8001812:	f015 0540 	ands.w	r5, r5, #64	; 0x40
 8001816:	d01a      	beq.n	800184e <HAL_UART_IRQHandler+0xc2>
        UART_EndRxTransfer(huart);
 8001818:	f7ff fe9c 	bl	8001554 <UART_EndRxTransfer>
        if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
 800181c:	6823      	ldr	r3, [r4, #0]
 800181e:	695a      	ldr	r2, [r3, #20]
 8001820:	0652      	lsls	r2, r2, #25
 8001822:	d510      	bpl.n	8001846 <HAL_UART_IRQHandler+0xba>
          CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
 8001824:	695a      	ldr	r2, [r3, #20]
          if(huart->hdmarx != NULL)
 8001826:	6b60      	ldr	r0, [r4, #52]	; 0x34
          CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
 8001828:	f022 0240 	bic.w	r2, r2, #64	; 0x40
 800182c:	615a      	str	r2, [r3, #20]
          if(huart->hdmarx != NULL)
 800182e:	b150      	cbz	r0, 8001846 <HAL_UART_IRQHandler+0xba>
            huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
 8001830:	4b25      	ldr	r3, [pc, #148]	; (80018c8 <HAL_UART_IRQHandler+0x13c>)
 8001832:	6343      	str	r3, [r0, #52]	; 0x34
            if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
 8001834:	f7ff f8be 	bl	80009b4 <HAL_DMA_Abort_IT>
 8001838:	2800      	cmp	r0, #0
 800183a:	d044      	beq.n	80018c6 <HAL_UART_IRQHandler+0x13a>
              huart->hdmarx->XferAbortCallback(huart->hdmarx);
 800183c:	6b60      	ldr	r0, [r4, #52]	; 0x34
}
 800183e:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
              huart->hdmarx->XferAbortCallback(huart->hdmarx);
 8001842:	6b43      	ldr	r3, [r0, #52]	; 0x34
 8001844:	4718      	bx	r3
            HAL_UART_ErrorCallback(huart);
 8001846:	4620      	mov	r0, r4
 8001848:	f7ff ff9e 	bl	8001788 <HAL_UART_ErrorCallback>
 800184c:	bd70      	pop	{r4, r5, r6, pc}
        HAL_UART_ErrorCallback(huart);
 800184e:	f7ff ff9b 	bl	8001788 <HAL_UART_ErrorCallback>
        huart->ErrorCode = HAL_UART_ERROR_NONE;
 8001852:	63e5      	str	r5, [r4, #60]	; 0x3c
 8001854:	bd70      	pop	{r4, r5, r6, pc}
  if(((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
 8001856:	0616      	lsls	r6, r2, #24
 8001858:	d527      	bpl.n	80018aa <HAL_UART_IRQHandler+0x11e>
 800185a:	060d      	lsls	r5, r1, #24
 800185c:	d525      	bpl.n	80018aa <HAL_UART_IRQHandler+0x11e>
  if(huart->gState == HAL_UART_STATE_BUSY_TX)
 800185e:	f894 2039 	ldrb.w	r2, [r4, #57]	; 0x39
 8001862:	2a21      	cmp	r2, #33	; 0x21
 8001864:	d12f      	bne.n	80018c6 <HAL_UART_IRQHandler+0x13a>
    if(huart->Init.WordLength == UART_WORDLENGTH_9B)
 8001866:	68a2      	ldr	r2, [r4, #8]
 8001868:	f5b2 5f80 	cmp.w	r2, #4096	; 0x1000
 800186c:	6a22      	ldr	r2, [r4, #32]
 800186e:	d117      	bne.n	80018a0 <HAL_UART_IRQHandler+0x114>
      huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
 8001870:	8811      	ldrh	r1, [r2, #0]
 8001872:	f3c1 0108 	ubfx	r1, r1, #0, #9
 8001876:	6059      	str	r1, [r3, #4]
      if(huart->Init.Parity == UART_PARITY_NONE)
 8001878:	6921      	ldr	r1, [r4, #16]
 800187a:	b979      	cbnz	r1, 800189c <HAL_UART_IRQHandler+0x110>
        huart->pTxBuffPtr += 2U;
 800187c:	3202      	adds	r2, #2
        huart->pTxBuffPtr += 1U;
 800187e:	6222      	str	r2, [r4, #32]
    if(--huart->TxXferCount == 0U)
 8001880:	8ce2      	ldrh	r2, [r4, #38]	; 0x26
 8001882:	3a01      	subs	r2, #1
 8001884:	b292      	uxth	r2, r2
 8001886:	84e2      	strh	r2, [r4, #38]	; 0x26
 8001888:	b9ea      	cbnz	r2, 80018c6 <HAL_UART_IRQHandler+0x13a>
      __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
 800188a:	68da      	ldr	r2, [r3, #12]
 800188c:	f022 0280 	bic.w	r2, r2, #128	; 0x80
 8001890:	60da      	str	r2, [r3, #12]
      __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
 8001892:	68da      	ldr	r2, [r3, #12]
 8001894:	f042 0240 	orr.w	r2, r2, #64	; 0x40
 8001898:	60da      	str	r2, [r3, #12]
 800189a:	bd70      	pop	{r4, r5, r6, pc}
        huart->pTxBuffPtr += 1U;
 800189c:	3201      	adds	r2, #1
 800189e:	e7ee      	b.n	800187e <HAL_UART_IRQHandler+0xf2>
      huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF);
 80018a0:	1c51      	adds	r1, r2, #1
 80018a2:	6221      	str	r1, [r4, #32]
 80018a4:	7812      	ldrb	r2, [r2, #0]
 80018a6:	605a      	str	r2, [r3, #4]
 80018a8:	e7ea      	b.n	8001880 <HAL_UART_IRQHandler+0xf4>
  if(((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
 80018aa:	0650      	lsls	r0, r2, #25
 80018ac:	d50b      	bpl.n	80018c6 <HAL_UART_IRQHandler+0x13a>
 80018ae:	064a      	lsls	r2, r1, #25
 80018b0:	d509      	bpl.n	80018c6 <HAL_UART_IRQHandler+0x13a>
  __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
 80018b2:	68da      	ldr	r2, [r3, #12]
  HAL_UART_TxCpltCallback(huart);
 80018b4:	4620      	mov	r0, r4
  __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
 80018b6:	f022 0240 	bic.w	r2, r2, #64	; 0x40
 80018ba:	60da      	str	r2, [r3, #12]
  huart->gState = HAL_UART_STATE_READY;
 80018bc:	2320      	movs	r3, #32
 80018be:	f884 3039 	strb.w	r3, [r4, #57]	; 0x39
  HAL_UART_TxCpltCallback(huart);
 80018c2:	f7ff ff21 	bl	8001708 <HAL_UART_TxCpltCallback>
 80018c6:	bd70      	pop	{r4, r5, r6, pc}
 80018c8:	080018cd 	.word	0x080018cd

080018cc <UART_DMAAbortOnError>:
{
 80018cc:	b508      	push	{r3, lr}
  huart->RxXferCount = 0x00U;
 80018ce:	2300      	movs	r3, #0
  UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
 80018d0:	6a40      	ldr	r0, [r0, #36]	; 0x24
  huart->RxXferCount = 0x00U;
 80018d2:	85c3      	strh	r3, [r0, #46]	; 0x2e
  huart->TxXferCount = 0x00U;
 80018d4:	84c3      	strh	r3, [r0, #38]	; 0x26
  HAL_UART_ErrorCallback(huart);
 80018d6:	f7ff ff57 	bl	8001788 <HAL_UART_ErrorCallback>
 80018da:	bd08      	pop	{r3, pc}

080018dc <SystemClock_Config>:
/**
  * @brief System Clock Configuration
  * @retval None
  */
void SystemClock_Config(void)
{
 80018dc:	b510      	push	{r4, lr}
 80018de:	b096      	sub	sp, #88	; 0x58
  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
 80018e0:	2228      	movs	r2, #40	; 0x28
 80018e2:	2100      	movs	r1, #0
 80018e4:	a80c      	add	r0, sp, #48	; 0x30
 80018e6:	f000 fb13 	bl	8001f10 <memset>
  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 80018ea:	2214      	movs	r2, #20
 80018ec:	2100      	movs	r1, #0
 80018ee:	a801      	add	r0, sp, #4
 80018f0:	f000 fb0e 	bl	8001f10 <memset>
  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 80018f4:	2218      	movs	r2, #24
 80018f6:	2100      	movs	r1, #0
 80018f8:	eb0d 0002 	add.w	r0, sp, r2
 80018fc:	f000 fb08 	bl	8001f10 <memset>

  /** Initializes the CPU, AHB and APB busses clocks 
  */
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
 8001900:	2301      	movs	r3, #1
 8001902:	9310      	str	r3, [sp, #64]	; 0x40
  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
 8001904:	2310      	movs	r3, #16
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
 8001906:	2402      	movs	r4, #2
  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
 8001908:	9311      	str	r3, [sp, #68]	; 0x44
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2;
  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL15;
 800190a:	f44f 1350 	mov.w	r3, #3407872	; 0x340000
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 800190e:	a80c      	add	r0, sp, #48	; 0x30
  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL15;
 8001910:	9315      	str	r3, [sp, #84]	; 0x54
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
 8001912:	940c      	str	r4, [sp, #48]	; 0x30
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
 8001914:	9413      	str	r4, [sp, #76]	; 0x4c
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 8001916:	f7ff fa89 	bl	8000e2c <HAL_RCC_OscConfig>
  {
    Error_Handler();
  }
  /** Initializes the CPU, AHB and APB busses clocks 
  */
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
 800191a:	230f      	movs	r3, #15
                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
 800191c:	f44f 6280 	mov.w	r2, #1024	; 0x400
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
 8001920:	9301      	str	r3, [sp, #4]
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
 8001922:	2300      	movs	r3, #0
  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;

  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
 8001924:	4621      	mov	r1, r4
 8001926:	a801      	add	r0, sp, #4
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
 8001928:	9303      	str	r3, [sp, #12]
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
 800192a:	9204      	str	r2, [sp, #16]
  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
 800192c:	9305      	str	r3, [sp, #20]
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
 800192e:	9402      	str	r4, [sp, #8]
  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
 8001930:	f7ff fc44 	bl	80011bc <HAL_RCC_ClockConfig>
  {
    Error_Handler();
  }
  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
  PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6;
 8001934:	f44f 4300 	mov.w	r3, #32768	; 0x8000
  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
 8001938:	a806      	add	r0, sp, #24
  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
 800193a:	9406      	str	r4, [sp, #24]
  PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6;
 800193c:	9308      	str	r3, [sp, #32]
  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
 800193e:	f7ff fd0f 	bl	8001360 <HAL_RCCEx_PeriphCLKConfig>
  {
    Error_Handler();
  }
}
 8001942:	b016      	add	sp, #88	; 0x58
 8001944:	bd10      	pop	{r4, pc}
	...

08001948 <main>:
{
 8001948:	b580      	push	{r7, lr}
static void MX_GPIO_Init(void)
{
  GPIO_InitTypeDef GPIO_InitStruct = {0};

  /* GPIO Ports Clock Enable */
  __HAL_RCC_GPIOE_CLK_ENABLE();
 800194a:	4db2      	ldr	r5, [pc, #712]	; (8001c14 <main+0x2cc>)
{
 800194c:	b08c      	sub	sp, #48	; 0x30
  HAL_Init();
 800194e:	f7fe fc8d 	bl	800026c <HAL_Init>
  SystemClock_Config();
 8001952:	f7ff ffc3 	bl	80018dc <SystemClock_Config>
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8001956:	2210      	movs	r2, #16
 8001958:	2100      	movs	r1, #0
 800195a:	a808      	add	r0, sp, #32
 800195c:	f000 fad8 	bl	8001f10 <memset>
  __HAL_RCC_GPIOE_CLK_ENABLE();
 8001960:	69ab      	ldr	r3, [r5, #24]
  __HAL_RCC_GPIOB_CLK_ENABLE();
  __HAL_RCC_GPIOD_CLK_ENABLE();
  __HAL_RCC_GPIOG_CLK_ENABLE();

  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(GPIOE, ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin 
 8001962:	2200      	movs	r2, #0
  __HAL_RCC_GPIOE_CLK_ENABLE();
 8001964:	f043 0340 	orr.w	r3, r3, #64	; 0x40
 8001968:	61ab      	str	r3, [r5, #24]
 800196a:	69ab      	ldr	r3, [r5, #24]
  HAL_GPIO_WritePin(GPIOE, ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin 
 800196c:	217f      	movs	r1, #127	; 0x7f
  __HAL_RCC_GPIOE_CLK_ENABLE();
 800196e:	f003 0340 	and.w	r3, r3, #64	; 0x40
 8001972:	9301      	str	r3, [sp, #4]
 8001974:	9b01      	ldr	r3, [sp, #4]
  __HAL_RCC_GPIOC_CLK_ENABLE();
 8001976:	69ab      	ldr	r3, [r5, #24]
  HAL_GPIO_WritePin(GPIOE, ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin 
 8001978:	48a7      	ldr	r0, [pc, #668]	; (8001c18 <main+0x2d0>)
  __HAL_RCC_GPIOC_CLK_ENABLE();
 800197a:	f043 0310 	orr.w	r3, r3, #16
 800197e:	61ab      	str	r3, [r5, #24]
 8001980:	69ab      	ldr	r3, [r5, #24]
  /*Configure GPIO pins : ATT_EN_1_8G_DL1_Pin ATT_EN_1_8G_DL2_Pin ATT_EN_1_8G_UL1_Pin ATT_EN_1_8G_UL2_Pin 
                           ATT_EN_1_8G_UL3_Pin PATH_EN_2_1G_DL_Pin PATH_EN_2_1G_UL_Pin */
  GPIO_InitStruct.Pin = ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin 
                          |ATT_EN_1_8G_UL3_Pin|PATH_EN_2_1G_DL_Pin|PATH_EN_2_1G_UL_Pin;
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8001982:	2400      	movs	r4, #0
  __HAL_RCC_GPIOC_CLK_ENABLE();
 8001984:	f003 0310 	and.w	r3, r3, #16
 8001988:	9302      	str	r3, [sp, #8]
 800198a:	9b02      	ldr	r3, [sp, #8]
  __HAL_RCC_GPIOF_CLK_ENABLE();
 800198c:	69ab      	ldr	r3, [r5, #24]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 800198e:	2601      	movs	r6, #1
  __HAL_RCC_GPIOF_CLK_ENABLE();
 8001990:	f043 0380 	orr.w	r3, r3, #128	; 0x80
 8001994:	61ab      	str	r3, [r5, #24]
 8001996:	69ab      	ldr	r3, [r5, #24]
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8001998:	2702      	movs	r7, #2
  __HAL_RCC_GPIOF_CLK_ENABLE();
 800199a:	f003 0380 	and.w	r3, r3, #128	; 0x80
 800199e:	9303      	str	r3, [sp, #12]
 80019a0:	9b03      	ldr	r3, [sp, #12]
  __HAL_RCC_GPIOA_CLK_ENABLE();
 80019a2:	69ab      	ldr	r3, [r5, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
  HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);

  /*Configure GPIO pins : PLL_LD_1_8G_DL_Pin PLL_LD_1_8G_UL_Pin */
  GPIO_InitStruct.Pin = PLL_LD_1_8G_DL_Pin|PLL_LD_1_8G_UL_Pin;
 80019a4:	f04f 080c 	mov.w	r8, #12
  __HAL_RCC_GPIOA_CLK_ENABLE();
 80019a8:	f043 0304 	orr.w	r3, r3, #4
 80019ac:	61ab      	str	r3, [r5, #24]
 80019ae:	69ab      	ldr	r3, [r5, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);

  /*Configure GPIO pin : PATH_EN_3_5G_H_Pin */
  GPIO_InitStruct.Pin = PATH_EN_3_5G_H_Pin;
  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
 80019b0:	f04f 0903 	mov.w	r9, #3
  __HAL_RCC_GPIOA_CLK_ENABLE();
 80019b4:	f003 0304 	and.w	r3, r3, #4
 80019b8:	9304      	str	r3, [sp, #16]
 80019ba:	9b04      	ldr	r3, [sp, #16]
  __HAL_RCC_GPIOB_CLK_ENABLE();
 80019bc:	69ab      	ldr	r3, [r5, #24]
  hadc1.Init.NbrOfConversion = 14;
 80019be:	f04f 0a0e 	mov.w	sl, #14
  __HAL_RCC_GPIOB_CLK_ENABLE();
 80019c2:	f043 0308 	orr.w	r3, r3, #8
 80019c6:	61ab      	str	r3, [r5, #24]
 80019c8:	69ab      	ldr	r3, [r5, #24]
 80019ca:	f003 0308 	and.w	r3, r3, #8
 80019ce:	9305      	str	r3, [sp, #20]
 80019d0:	9b05      	ldr	r3, [sp, #20]
  __HAL_RCC_GPIOD_CLK_ENABLE();
 80019d2:	69ab      	ldr	r3, [r5, #24]
 80019d4:	f043 0320 	orr.w	r3, r3, #32
 80019d8:	61ab      	str	r3, [r5, #24]
 80019da:	69ab      	ldr	r3, [r5, #24]
 80019dc:	f003 0320 	and.w	r3, r3, #32
 80019e0:	9306      	str	r3, [sp, #24]
 80019e2:	9b06      	ldr	r3, [sp, #24]
  __HAL_RCC_GPIOG_CLK_ENABLE();
 80019e4:	69ab      	ldr	r3, [r5, #24]
 80019e6:	f443 7380 	orr.w	r3, r3, #256	; 0x100
 80019ea:	61ab      	str	r3, [r5, #24]
 80019ec:	69ab      	ldr	r3, [r5, #24]
 80019ee:	f403 7380 	and.w	r3, r3, #256	; 0x100
 80019f2:	9307      	str	r3, [sp, #28]
 80019f4:	9b07      	ldr	r3, [sp, #28]
  HAL_GPIO_WritePin(GPIOE, ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin 
 80019f6:	f7ff fa13 	bl	8000e20 <HAL_GPIO_WritePin>
  HAL_GPIO_WritePin(GPIOC, ATT_EN_1_8G_UL4_Pin|PATH_EN_1_8G_DL_Pin|PATH_EN_1_8G_UL_Pin|PLL_EN_3_5G_L_Pin 
 80019fa:	2200      	movs	r2, #0
 80019fc:	f24e 01c0 	movw	r1, #57536	; 0xe0c0
 8001a00:	4886      	ldr	r0, [pc, #536]	; (8001c1c <main+0x2d4>)
 8001a02:	f7ff fa0d 	bl	8000e20 <HAL_GPIO_WritePin>
  HAL_GPIO_WritePin(GPIOF, PLL_EN_1_8G_DL_Pin|PLL_EN_1_8G_UL_Pin|ATT_EN_2_1G_DL1_Pin|ATT_EN_2_1G_DL2_Pin 
 8001a06:	2200      	movs	r2, #0
 8001a08:	f240 31f3 	movw	r1, #1011	; 0x3f3
 8001a0c:	4884      	ldr	r0, [pc, #528]	; (8001c20 <main+0x2d8>)
 8001a0e:	f7ff fa07 	bl	8000e20 <HAL_GPIO_WritePin>
  HAL_GPIO_WritePin(GPIOD, PLL_DATA_Pin|PLL_CLK_Pin|ATT_DATA_Pin|ATT_CLK_Pin 
 8001a12:	2200      	movs	r2, #0
 8001a14:	f648 71ff 	movw	r1, #36863	; 0x8fff
 8001a18:	4882      	ldr	r0, [pc, #520]	; (8001c24 <main+0x2dc>)
 8001a1a:	f7ff fa01 	bl	8000e20 <HAL_GPIO_WritePin>
  HAL_GPIO_WritePin(GPIOG, DA_SYNC_Pin|DA_SCLK_Pin|DA_DIN_Pin|_T_SYNC_UL_Pin 
 8001a1e:	2200      	movs	r2, #0
 8001a20:	f643 51fc 	movw	r1, #15868	; 0x3dfc
 8001a24:	4880      	ldr	r0, [pc, #512]	; (8001c28 <main+0x2e0>)
 8001a26:	f7ff f9fb 	bl	8000e20 <HAL_GPIO_WritePin>
  HAL_GPIO_WritePin(GPIOB, PLL_EN_2_1G_DL_Pin|PLL_EN_2_1G_UL_Pin, GPIO_PIN_RESET);
 8001a2a:	2200      	movs	r2, #0
 8001a2c:	2118      	movs	r1, #24
 8001a2e:	487f      	ldr	r0, [pc, #508]	; (8001c2c <main+0x2e4>)
 8001a30:	f7ff f9f6 	bl	8000e20 <HAL_GPIO_WritePin>
  GPIO_InitStruct.Pin = ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin 
 8001a34:	237f      	movs	r3, #127	; 0x7f
  HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
 8001a36:	a908      	add	r1, sp, #32
 8001a38:	4877      	ldr	r0, [pc, #476]	; (8001c18 <main+0x2d0>)
  GPIO_InitStruct.Pin = ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin 
 8001a3a:	9308      	str	r3, [sp, #32]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 8001a3c:	9609      	str	r6, [sp, #36]	; 0x24
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8001a3e:	940a      	str	r4, [sp, #40]	; 0x28
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8001a40:	970b      	str	r7, [sp, #44]	; 0x2c
  HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
 8001a42:	f7ff f901 	bl	8000c48 <HAL_GPIO_Init>
  GPIO_InitStruct.Pin = ATT_EN_1_8G_UL4_Pin|PATH_EN_1_8G_DL_Pin|PATH_EN_1_8G_UL_Pin|PLL_EN_3_5G_L_Pin 
 8001a46:	f24e 03c0 	movw	r3, #57536	; 0xe0c0
  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 8001a4a:	a908      	add	r1, sp, #32
 8001a4c:	4873      	ldr	r0, [pc, #460]	; (8001c1c <main+0x2d4>)
  GPIO_InitStruct.Pin = ATT_EN_1_8G_UL4_Pin|PATH_EN_1_8G_DL_Pin|PATH_EN_1_8G_UL_Pin|PLL_EN_3_5G_L_Pin 
 8001a4e:	9308      	str	r3, [sp, #32]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 8001a50:	9609      	str	r6, [sp, #36]	; 0x24
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8001a52:	940a      	str	r4, [sp, #40]	; 0x28
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8001a54:	970b      	str	r7, [sp, #44]	; 0x2c
  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 8001a56:	f7ff f8f7 	bl	8000c48 <HAL_GPIO_Init>
  GPIO_InitStruct.Pin = PLL_EN_1_8G_DL_Pin|PLL_EN_1_8G_UL_Pin|ATT_EN_2_1G_DL1_Pin|ATT_EN_2_1G_DL2_Pin 
 8001a5a:	f240 33f3 	movw	r3, #1011	; 0x3f3
  HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
 8001a5e:	a908      	add	r1, sp, #32
 8001a60:	486f      	ldr	r0, [pc, #444]	; (8001c20 <main+0x2d8>)
  GPIO_InitStruct.Pin = PLL_EN_1_8G_DL_Pin|PLL_EN_1_8G_UL_Pin|ATT_EN_2_1G_DL1_Pin|ATT_EN_2_1G_DL2_Pin 
 8001a62:	9308      	str	r3, [sp, #32]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 8001a64:	9609      	str	r6, [sp, #36]	; 0x24
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8001a66:	940a      	str	r4, [sp, #40]	; 0x28
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8001a68:	970b      	str	r7, [sp, #44]	; 0x2c
  HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
 8001a6a:	f7ff f8ed 	bl	8000c48 <HAL_GPIO_Init>
  HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
 8001a6e:	a908      	add	r1, sp, #32
 8001a70:	486b      	ldr	r0, [pc, #428]	; (8001c20 <main+0x2d8>)
  GPIO_InitStruct.Pin = PLL_LD_1_8G_DL_Pin|PLL_LD_1_8G_UL_Pin;
 8001a72:	f8cd 8020 	str.w	r8, [sp, #32]
  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
 8001a76:	9409      	str	r4, [sp, #36]	; 0x24
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8001a78:	940a      	str	r4, [sp, #40]	; 0x28
  HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
 8001a7a:	f7ff f8e5 	bl	8000c48 <HAL_GPIO_Init>
  GPIO_InitStruct.Pin = PLL_DATA_Pin|PLL_CLK_Pin|ATT_DATA_Pin|ATT_CLK_Pin 
 8001a7e:	f648 73ff 	movw	r3, #36863	; 0x8fff
  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
 8001a82:	a908      	add	r1, sp, #32
 8001a84:	4867      	ldr	r0, [pc, #412]	; (8001c24 <main+0x2dc>)
  GPIO_InitStruct.Pin = PLL_DATA_Pin|PLL_CLK_Pin|ATT_DATA_Pin|ATT_CLK_Pin 
 8001a86:	9308      	str	r3, [sp, #32]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 8001a88:	9609      	str	r6, [sp, #36]	; 0x24
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8001a8a:	940a      	str	r4, [sp, #40]	; 0x28
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8001a8c:	970b      	str	r7, [sp, #44]	; 0x2c
  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
 8001a8e:	f7ff f8db 	bl	8000c48 <HAL_GPIO_Init>
  GPIO_InitStruct.Pin = ALARM_DC_Pin|ALARM_AC_Pin;
 8001a92:	f44f 5340 	mov.w	r3, #12288	; 0x3000
  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
 8001a96:	a908      	add	r1, sp, #32
 8001a98:	4862      	ldr	r0, [pc, #392]	; (8001c24 <main+0x2dc>)
  GPIO_InitStruct.Pin = ALARM_DC_Pin|ALARM_AC_Pin;
 8001a9a:	9308      	str	r3, [sp, #32]
  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
 8001a9c:	9409      	str	r4, [sp, #36]	; 0x24
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8001a9e:	940a      	str	r4, [sp, #40]	; 0x28
  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
 8001aa0:	f7ff f8d2 	bl	8000c48 <HAL_GPIO_Init>
  GPIO_InitStruct.Pin = DA_SYNC_Pin|DA_SCLK_Pin|DA_DIN_Pin|_T_SYNC_UL_Pin 
 8001aa4:	f643 53fc 	movw	r3, #15868	; 0x3dfc
  HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
 8001aa8:	a908      	add	r1, sp, #32
 8001aaa:	485f      	ldr	r0, [pc, #380]	; (8001c28 <main+0x2e0>)
  GPIO_InitStruct.Pin = DA_SYNC_Pin|DA_SCLK_Pin|DA_DIN_Pin|_T_SYNC_UL_Pin 
 8001aac:	9308      	str	r3, [sp, #32]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 8001aae:	9609      	str	r6, [sp, #36]	; 0x24
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8001ab0:	940a      	str	r4, [sp, #40]	; 0x28
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8001ab2:	970b      	str	r7, [sp, #44]	; 0x2c
  HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
 8001ab4:	f7ff f8c8 	bl	8000c48 <HAL_GPIO_Init>
  GPIO_InitStruct.Pin = PLL_LD_3_5G_L_Pin|PLL_LD_3_5G_H_Pin;
 8001ab8:	f44f 7340 	mov.w	r3, #768	; 0x300
  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 8001abc:	a908      	add	r1, sp, #32
 8001abe:	4857      	ldr	r0, [pc, #348]	; (8001c1c <main+0x2d4>)
  GPIO_InitStruct.Pin = PLL_LD_3_5G_L_Pin|PLL_LD_3_5G_H_Pin;
 8001ac0:	9308      	str	r3, [sp, #32]
  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
 8001ac2:	9409      	str	r4, [sp, #36]	; 0x24
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8001ac4:	940a      	str	r4, [sp, #40]	; 0x28
  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 8001ac6:	f7ff f8bf 	bl	8000c48 <HAL_GPIO_Init>
  GPIO_InitStruct.Pin = PATH_EN_3_5G_H_Pin;
 8001aca:	f44f 7300 	mov.w	r3, #512	; 0x200
  HAL_GPIO_Init(PATH_EN_3_5G_H_GPIO_Port, &GPIO_InitStruct);
 8001ace:	a908      	add	r1, sp, #32
 8001ad0:	4855      	ldr	r0, [pc, #340]	; (8001c28 <main+0x2e0>)
  GPIO_InitStruct.Pin = PATH_EN_3_5G_H_Pin;
 8001ad2:	9308      	str	r3, [sp, #32]
  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
 8001ad4:	f8cd 9024 	str.w	r9, [sp, #36]	; 0x24
  HAL_GPIO_Init(PATH_EN_3_5G_H_GPIO_Port, &GPIO_InitStruct);
 8001ad8:	f7ff f8b6 	bl	8000c48 <HAL_GPIO_Init>

  /*Configure GPIO pins : PLL_EN_2_1G_DL_Pin PLL_EN_2_1G_UL_Pin */
  GPIO_InitStruct.Pin = PLL_EN_2_1G_DL_Pin|PLL_EN_2_1G_UL_Pin;
 8001adc:	2318      	movs	r3, #24
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  GPIO_InitStruct.Pull = GPIO_NOPULL;
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8001ade:	a908      	add	r1, sp, #32
 8001ae0:	4852      	ldr	r0, [pc, #328]	; (8001c2c <main+0x2e4>)
  GPIO_InitStruct.Pin = PLL_EN_2_1G_DL_Pin|PLL_EN_2_1G_UL_Pin;
 8001ae2:	9308      	str	r3, [sp, #32]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 8001ae4:	9609      	str	r6, [sp, #36]	; 0x24
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8001ae6:	940a      	str	r4, [sp, #40]	; 0x28
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8001ae8:	970b      	str	r7, [sp, #44]	; 0x2c
  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8001aea:	f7ff f8ad 	bl	8000c48 <HAL_GPIO_Init>

  /*Configure GPIO pins : PLL_LD_2_1G_DL_Pin PLL_LD_2_1G_UL_Pin */
  GPIO_InitStruct.Pin = PLL_LD_2_1G_DL_Pin|PLL_LD_2_1G_UL_Pin;
 8001aee:	2360      	movs	r3, #96	; 0x60
  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
  GPIO_InitStruct.Pull = GPIO_NOPULL;
  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8001af0:	a908      	add	r1, sp, #32
 8001af2:	484e      	ldr	r0, [pc, #312]	; (8001c2c <main+0x2e4>)
  GPIO_InitStruct.Pin = PLL_LD_2_1G_DL_Pin|PLL_LD_2_1G_UL_Pin;
 8001af4:	9308      	str	r3, [sp, #32]
  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
 8001af6:	9409      	str	r4, [sp, #36]	; 0x24
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8001af8:	940a      	str	r4, [sp, #40]	; 0x28
  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8001afa:	f7ff f8a5 	bl	8000c48 <HAL_GPIO_Init>
  __HAL_RCC_DMA1_CLK_ENABLE();
 8001afe:	696b      	ldr	r3, [r5, #20]
  HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
 8001b00:	4622      	mov	r2, r4
  __HAL_RCC_DMA1_CLK_ENABLE();
 8001b02:	4333      	orrs	r3, r6
 8001b04:	616b      	str	r3, [r5, #20]
 8001b06:	696b      	ldr	r3, [r5, #20]
  HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
 8001b08:	4621      	mov	r1, r4
  __HAL_RCC_DMA1_CLK_ENABLE();
 8001b0a:	4033      	ands	r3, r6
 8001b0c:	9300      	str	r3, [sp, #0]
  HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
 8001b0e:	200b      	movs	r0, #11
  __HAL_RCC_DMA1_CLK_ENABLE();
 8001b10:	9b00      	ldr	r3, [sp, #0]
  HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
 8001b12:	f7fe fe7b 	bl	800080c <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
 8001b16:	200b      	movs	r0, #11
  hadc1.Instance = ADC1;
 8001b18:	4d45      	ldr	r5, [pc, #276]	; (8001c30 <main+0x2e8>)
  HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
 8001b1a:	f7fe feab 	bl	8000874 <HAL_NVIC_EnableIRQ>
  hadc1.Instance = ADC1;
 8001b1e:	4b45      	ldr	r3, [pc, #276]	; (8001c34 <main+0x2ec>)
  if (HAL_ADC_Init(&hadc1) != HAL_OK)
 8001b20:	4628      	mov	r0, r5
  hadc1.Instance = ADC1;
 8001b22:	602b      	str	r3, [r5, #0]
  hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE;
 8001b24:	f44f 7380 	mov.w	r3, #256	; 0x100
 8001b28:	60ab      	str	r3, [r5, #8]
  hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
 8001b2a:	f44f 2360 	mov.w	r3, #917504	; 0xe0000
  ADC_ChannelConfTypeDef sConfig = {0};
 8001b2e:	9408      	str	r4, [sp, #32]
  hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
 8001b30:	61eb      	str	r3, [r5, #28]
  ADC_ChannelConfTypeDef sConfig = {0};
 8001b32:	9409      	str	r4, [sp, #36]	; 0x24
 8001b34:	940a      	str	r4, [sp, #40]	; 0x28
  hadc1.Init.ContinuousConvMode = ENABLE;
 8001b36:	60ee      	str	r6, [r5, #12]
  hadc1.Init.DiscontinuousConvMode = DISABLE;
 8001b38:	616c      	str	r4, [r5, #20]
  hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
 8001b3a:	606c      	str	r4, [r5, #4]
  hadc1.Init.NbrOfConversion = 14;
 8001b3c:	f8c5 a010 	str.w	sl, [r5, #16]
  if (HAL_ADC_Init(&hadc1) != HAL_OK)
 8001b40:	f7fe fd60 	bl	8000604 <HAL_ADC_Init>
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8001b44:	a908      	add	r1, sp, #32
 8001b46:	4628      	mov	r0, r5
  sConfig.Channel = ADC_CHANNEL_0;
 8001b48:	9408      	str	r4, [sp, #32]
  sConfig.Rank = ADC_REGULAR_RANK_1;
 8001b4a:	9609      	str	r6, [sp, #36]	; 0x24
  sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
 8001b4c:	940a      	str	r4, [sp, #40]	; 0x28
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8001b4e:	f7fe fbed 	bl	800032c <HAL_ADC_ConfigChannel>
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8001b52:	a908      	add	r1, sp, #32
 8001b54:	4628      	mov	r0, r5
  sConfig.Rank = ADC_REGULAR_RANK_2;
 8001b56:	9709      	str	r7, [sp, #36]	; 0x24
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8001b58:	f7fe fbe8 	bl	800032c <HAL_ADC_ConfigChannel>
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8001b5c:	a908      	add	r1, sp, #32
 8001b5e:	4628      	mov	r0, r5
  sConfig.Rank = ADC_REGULAR_RANK_3;
 8001b60:	f8cd 9024 	str.w	r9, [sp, #36]	; 0x24
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8001b64:	f7fe fbe2 	bl	800032c <HAL_ADC_ConfigChannel>
  sConfig.Rank = ADC_REGULAR_RANK_4;
 8001b68:	2304      	movs	r3, #4
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8001b6a:	a908      	add	r1, sp, #32
 8001b6c:	4628      	mov	r0, r5
  sConfig.Rank = ADC_REGULAR_RANK_4;
 8001b6e:	9309      	str	r3, [sp, #36]	; 0x24
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8001b70:	f7fe fbdc 	bl	800032c <HAL_ADC_ConfigChannel>
  sConfig.Rank = ADC_REGULAR_RANK_5;
 8001b74:	2305      	movs	r3, #5
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8001b76:	a908      	add	r1, sp, #32
 8001b78:	4628      	mov	r0, r5
  sConfig.Rank = ADC_REGULAR_RANK_5;
 8001b7a:	9309      	str	r3, [sp, #36]	; 0x24
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8001b7c:	f7fe fbd6 	bl	800032c <HAL_ADC_ConfigChannel>
  sConfig.Rank = ADC_REGULAR_RANK_6;
 8001b80:	2306      	movs	r3, #6
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8001b82:	a908      	add	r1, sp, #32
 8001b84:	4628      	mov	r0, r5
  sConfig.Rank = ADC_REGULAR_RANK_6;
 8001b86:	9309      	str	r3, [sp, #36]	; 0x24
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8001b88:	f7fe fbd0 	bl	800032c <HAL_ADC_ConfigChannel>
  sConfig.Rank = ADC_REGULAR_RANK_7;
 8001b8c:	2307      	movs	r3, #7
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8001b8e:	a908      	add	r1, sp, #32
 8001b90:	4628      	mov	r0, r5
  sConfig.Rank = ADC_REGULAR_RANK_7;
 8001b92:	9309      	str	r3, [sp, #36]	; 0x24
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8001b94:	f7fe fbca 	bl	800032c <HAL_ADC_ConfigChannel>
  sConfig.Rank = ADC_REGULAR_RANK_8;
 8001b98:	2308      	movs	r3, #8
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8001b9a:	a908      	add	r1, sp, #32
 8001b9c:	4628      	mov	r0, r5
  sConfig.Rank = ADC_REGULAR_RANK_8;
 8001b9e:	9309      	str	r3, [sp, #36]	; 0x24
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8001ba0:	f7fe fbc4 	bl	800032c <HAL_ADC_ConfigChannel>
  sConfig.Rank = ADC_REGULAR_RANK_9;
 8001ba4:	2309      	movs	r3, #9
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8001ba6:	a908      	add	r1, sp, #32
 8001ba8:	4628      	mov	r0, r5
  sConfig.Rank = ADC_REGULAR_RANK_9;
 8001baa:	9309      	str	r3, [sp, #36]	; 0x24
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8001bac:	f7fe fbbe 	bl	800032c <HAL_ADC_ConfigChannel>
  sConfig.Rank = ADC_REGULAR_RANK_10;
 8001bb0:	230a      	movs	r3, #10
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8001bb2:	a908      	add	r1, sp, #32
 8001bb4:	4628      	mov	r0, r5
  sConfig.Rank = ADC_REGULAR_RANK_10;
 8001bb6:	9309      	str	r3, [sp, #36]	; 0x24
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8001bb8:	f7fe fbb8 	bl	800032c <HAL_ADC_ConfigChannel>
  sConfig.Rank = ADC_REGULAR_RANK_11;
 8001bbc:	230b      	movs	r3, #11
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8001bbe:	a908      	add	r1, sp, #32
 8001bc0:	4628      	mov	r0, r5
  sConfig.Rank = ADC_REGULAR_RANK_11;
 8001bc2:	9309      	str	r3, [sp, #36]	; 0x24
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8001bc4:	f7fe fbb2 	bl	800032c <HAL_ADC_ConfigChannel>
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8001bc8:	a908      	add	r1, sp, #32
 8001bca:	4628      	mov	r0, r5
  sConfig.Rank = ADC_REGULAR_RANK_12;
 8001bcc:	f8cd 8024 	str.w	r8, [sp, #36]	; 0x24
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8001bd0:	f7fe fbac 	bl	800032c <HAL_ADC_ConfigChannel>
  sConfig.Rank = ADC_REGULAR_RANK_13;
 8001bd4:	230d      	movs	r3, #13
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8001bd6:	a908      	add	r1, sp, #32
 8001bd8:	4628      	mov	r0, r5
  sConfig.Rank = ADC_REGULAR_RANK_13;
 8001bda:	9309      	str	r3, [sp, #36]	; 0x24
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8001bdc:	f7fe fba6 	bl	800032c <HAL_ADC_ConfigChannel>
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8001be0:	a908      	add	r1, sp, #32
 8001be2:	4628      	mov	r0, r5
  sConfig.Rank = ADC_REGULAR_RANK_14;
 8001be4:	f8cd a024 	str.w	sl, [sp, #36]	; 0x24
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8001be8:	f7fe fba0 	bl	800032c <HAL_ADC_ConfigChannel>
  huart1.Init.BaudRate = 115200;
 8001bec:	f44f 33e1 	mov.w	r3, #115200	; 0x1c200
  huart1.Instance = USART1;
 8001bf0:	4811      	ldr	r0, [pc, #68]	; (8001c38 <main+0x2f0>)
  huart1.Init.BaudRate = 115200;
 8001bf2:	4a12      	ldr	r2, [pc, #72]	; (8001c3c <main+0x2f4>)
  huart1.Init.WordLength = UART_WORDLENGTH_8B;
 8001bf4:	6084      	str	r4, [r0, #8]
  huart1.Init.BaudRate = 115200;
 8001bf6:	e880 000c 	stmia.w	r0, {r2, r3}
  huart1.Init.StopBits = UART_STOPBITS_1;
 8001bfa:	60c4      	str	r4, [r0, #12]
  huart1.Init.Parity = UART_PARITY_NONE;
 8001bfc:	6104      	str	r4, [r0, #16]
  huart1.Init.Mode = UART_MODE_TX_RX;
 8001bfe:	f8c0 8014 	str.w	r8, [r0, #20]
  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
 8001c02:	6184      	str	r4, [r0, #24]
  huart1.Init.OverSampling = UART_OVERSAMPLING_16;
 8001c04:	61c4      	str	r4, [r0, #28]
  if (HAL_UART_Init(&huart1) != HAL_OK)
 8001c06:	f7ff fd51 	bl	80016ac <HAL_UART_Init>
  HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
 8001c0a:	2025      	movs	r0, #37	; 0x25
 8001c0c:	4622      	mov	r2, r4
 8001c0e:	4621      	mov	r1, r4
 8001c10:	e016      	b.n	8001c40 <main+0x2f8>
 8001c12:	bf00      	nop
 8001c14:	40021000 	.word	0x40021000
 8001c18:	40011800 	.word	0x40011800
 8001c1c:	40011000 	.word	0x40011000
 8001c20:	40011c00 	.word	0x40011c00
 8001c24:	40011400 	.word	0x40011400
 8001c28:	40012000 	.word	0x40012000
 8001c2c:	40010c00 	.word	0x40010c00
 8001c30:	2000002c 	.word	0x2000002c
 8001c34:	40012400 	.word	0x40012400
 8001c38:	2000005c 	.word	0x2000005c
 8001c3c:	40013800 	.word	0x40013800
 8001c40:	f7fe fde4 	bl	800080c <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(USART1_IRQn);
 8001c44:	2025      	movs	r0, #37	; 0x25
 8001c46:	f7fe fe15 	bl	8000874 <HAL_NVIC_EnableIRQ>
  while(HAL_ADCEx_Calibration_Start(&hadc1) != HAL_OK); //ADC Calibration 
 8001c4a:	4628      	mov	r0, r5
 8001c4c:	f7fe fd64 	bl	8000718 <HAL_ADCEx_Calibration_Start>
 8001c50:	2800      	cmp	r0, #0
 8001c52:	d1fa      	bne.n	8001c4a <main+0x302>
   HAL_ADC_Start_DMA(&hadc1, (uint32_t*)ADCvalue, ADC_EA);
 8001c54:	220e      	movs	r2, #14
 8001c56:	4902      	ldr	r1, [pc, #8]	; (8001c60 <main+0x318>)
 8001c58:	4802      	ldr	r0, [pc, #8]	; (8001c64 <main+0x31c>)
 8001c5a:	f7fe fc23 	bl	80004a4 <HAL_ADC_Start_DMA>
 8001c5e:	e7fe      	b.n	8001c5e <main+0x316>
 8001c60:	200000e0 	.word	0x200000e0
 8001c64:	2000002c 	.word	0x2000002c

08001c68 <Error_Handler>:
/**
  * @brief  This function is executed in case of error occurrence.
  * @retval None
  */
void Error_Handler(void)
{
 8001c68:	4770      	bx	lr
	...

08001c6c <HAL_MspInit>:
{
  /* USER CODE BEGIN MspInit 0 */

  /* USER CODE END MspInit 0 */

  __HAL_RCC_AFIO_CLK_ENABLE();
 8001c6c:	4b0e      	ldr	r3, [pc, #56]	; (8001ca8 <HAL_MspInit+0x3c>)
{
 8001c6e:	b082      	sub	sp, #8
  __HAL_RCC_AFIO_CLK_ENABLE();
 8001c70:	699a      	ldr	r2, [r3, #24]
 8001c72:	f042 0201 	orr.w	r2, r2, #1
 8001c76:	619a      	str	r2, [r3, #24]
 8001c78:	699a      	ldr	r2, [r3, #24]
 8001c7a:	f002 0201 	and.w	r2, r2, #1
 8001c7e:	9200      	str	r2, [sp, #0]
 8001c80:	9a00      	ldr	r2, [sp, #0]
  __HAL_RCC_PWR_CLK_ENABLE();
 8001c82:	69da      	ldr	r2, [r3, #28]
 8001c84:	f042 5280 	orr.w	r2, r2, #268435456	; 0x10000000
 8001c88:	61da      	str	r2, [r3, #28]
 8001c8a:	69db      	ldr	r3, [r3, #28]

  /* System interrupt init*/

  /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled 
  */
  __HAL_AFIO_REMAP_SWJ_NOJTAG();
 8001c8c:	4a07      	ldr	r2, [pc, #28]	; (8001cac <HAL_MspInit+0x40>)
  __HAL_RCC_PWR_CLK_ENABLE();
 8001c8e:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8001c92:	9301      	str	r3, [sp, #4]
 8001c94:	9b01      	ldr	r3, [sp, #4]
  __HAL_AFIO_REMAP_SWJ_NOJTAG();
 8001c96:	6853      	ldr	r3, [r2, #4]
 8001c98:	f023 63e0 	bic.w	r3, r3, #117440512	; 0x7000000
 8001c9c:	f043 7300 	orr.w	r3, r3, #33554432	; 0x2000000
 8001ca0:	6053      	str	r3, [r2, #4]

  /* USER CODE BEGIN MspInit 1 */

  /* USER CODE END MspInit 1 */
}
 8001ca2:	b002      	add	sp, #8
 8001ca4:	4770      	bx	lr
 8001ca6:	bf00      	nop
 8001ca8:	40021000 	.word	0x40021000
 8001cac:	40010000 	.word	0x40010000

08001cb0 <HAL_ADC_MspInit>:
* @param hadc: ADC handle pointer
* @retval None
*/
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
{
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8001cb0:	2210      	movs	r2, #16
{
 8001cb2:	b530      	push	{r4, r5, lr}
 8001cb4:	4605      	mov	r5, r0
 8001cb6:	b089      	sub	sp, #36	; 0x24
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8001cb8:	eb0d 0002 	add.w	r0, sp, r2
 8001cbc:	2100      	movs	r1, #0
 8001cbe:	f000 f927 	bl	8001f10 <memset>
  if(hadc->Instance==ADC1)
 8001cc2:	682a      	ldr	r2, [r5, #0]
 8001cc4:	4b2b      	ldr	r3, [pc, #172]	; (8001d74 <HAL_ADC_MspInit+0xc4>)
 8001cc6:	429a      	cmp	r2, r3
 8001cc8:	d152      	bne.n	8001d70 <HAL_ADC_MspInit+0xc0>
  {
  /* USER CODE BEGIN ADC1_MspInit 0 */

  /* USER CODE END ADC1_MspInit 0 */
    /* Peripheral clock enable */
    __HAL_RCC_ADC1_CLK_ENABLE();
 8001cca:	f503 436c 	add.w	r3, r3, #60416	; 0xec00
 8001cce:	699a      	ldr	r2, [r3, #24]
    PA7     ------> ADC1_IN7
    PB0     ------> ADC1_IN8
    PB1     ------> ADC1_IN9 
    */
    GPIO_InitStruct.Pin = DET_3_5G_UL_IN_Pin|DET_3_5G_UL_OUT_Pin|RFU_TEMP_Pin|_28V_DET_Pin;
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
 8001cd0:	2403      	movs	r4, #3
    __HAL_RCC_ADC1_CLK_ENABLE();
 8001cd2:	f442 7200 	orr.w	r2, r2, #512	; 0x200
 8001cd6:	619a      	str	r2, [r3, #24]
 8001cd8:	699a      	ldr	r2, [r3, #24]
    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 8001cda:	a904      	add	r1, sp, #16
    __HAL_RCC_ADC1_CLK_ENABLE();
 8001cdc:	f402 7200 	and.w	r2, r2, #512	; 0x200
 8001ce0:	9200      	str	r2, [sp, #0]
 8001ce2:	9a00      	ldr	r2, [sp, #0]
    __HAL_RCC_GPIOC_CLK_ENABLE();
 8001ce4:	699a      	ldr	r2, [r3, #24]
    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 8001ce6:	4824      	ldr	r0, [pc, #144]	; (8001d78 <HAL_ADC_MspInit+0xc8>)
    __HAL_RCC_GPIOC_CLK_ENABLE();
 8001ce8:	f042 0210 	orr.w	r2, r2, #16
 8001cec:	619a      	str	r2, [r3, #24]
 8001cee:	699a      	ldr	r2, [r3, #24]
 8001cf0:	f002 0210 	and.w	r2, r2, #16
 8001cf4:	9201      	str	r2, [sp, #4]
 8001cf6:	9a01      	ldr	r2, [sp, #4]
    __HAL_RCC_GPIOA_CLK_ENABLE();
 8001cf8:	699a      	ldr	r2, [r3, #24]
 8001cfa:	f042 0204 	orr.w	r2, r2, #4
 8001cfe:	619a      	str	r2, [r3, #24]
 8001d00:	699a      	ldr	r2, [r3, #24]
 8001d02:	f002 0204 	and.w	r2, r2, #4
 8001d06:	9202      	str	r2, [sp, #8]
 8001d08:	9a02      	ldr	r2, [sp, #8]
    __HAL_RCC_GPIOB_CLK_ENABLE();
 8001d0a:	699a      	ldr	r2, [r3, #24]
 8001d0c:	f042 0208 	orr.w	r2, r2, #8
 8001d10:	619a      	str	r2, [r3, #24]
 8001d12:	699b      	ldr	r3, [r3, #24]
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
 8001d14:	9405      	str	r4, [sp, #20]
    __HAL_RCC_GPIOB_CLK_ENABLE();
 8001d16:	f003 0308 	and.w	r3, r3, #8
 8001d1a:	9303      	str	r3, [sp, #12]
 8001d1c:	9b03      	ldr	r3, [sp, #12]
    GPIO_InitStruct.Pin = DET_3_5G_UL_IN_Pin|DET_3_5G_UL_OUT_Pin|RFU_TEMP_Pin|_28V_DET_Pin;
 8001d1e:	230f      	movs	r3, #15
 8001d20:	9304      	str	r3, [sp, #16]
    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 8001d22:	f7fe ff91 	bl	8000c48 <HAL_GPIO_Init>

    GPIO_InitStruct.Pin = DET_1_8G_DL_IN_Pin|DET_1_8G_DL_OUT_Pin|DET_1_8G_UL_IN_Pin|DET_1_8G_UL_OUT_Pin 
 8001d26:	23ff      	movs	r3, #255	; 0xff
                          |DET_2_1G_DL_IN_Pin|DET_2_1G_DL_OUT_Pin|DET_2_1G_UL_IN_Pin|DET_2_1G_UL_OUT_Pin;
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8001d28:	a904      	add	r1, sp, #16
 8001d2a:	4814      	ldr	r0, [pc, #80]	; (8001d7c <HAL_ADC_MspInit+0xcc>)
    GPIO_InitStruct.Pin = DET_1_8G_DL_IN_Pin|DET_1_8G_DL_OUT_Pin|DET_1_8G_UL_IN_Pin|DET_1_8G_UL_OUT_Pin 
 8001d2c:	9304      	str	r3, [sp, #16]
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
 8001d2e:	9405      	str	r4, [sp, #20]
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8001d30:	f7fe ff8a 	bl	8000c48 <HAL_GPIO_Init>

    GPIO_InitStruct.Pin = DET_3_5G_DL_IN_Pin|DET_3_5G_DL_OUT_Pin;
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8001d34:	4812      	ldr	r0, [pc, #72]	; (8001d80 <HAL_ADC_MspInit+0xd0>)
 8001d36:	a904      	add	r1, sp, #16
    GPIO_InitStruct.Pin = DET_3_5G_DL_IN_Pin|DET_3_5G_DL_OUT_Pin;
 8001d38:	9404      	str	r4, [sp, #16]
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
 8001d3a:	9405      	str	r4, [sp, #20]
    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8001d3c:	f7fe ff84 	bl	8000c48 <HAL_GPIO_Init>
    /* ADC1 DMA Init */
    /* ADC1 Init */
    hdma_adc1.Instance = DMA1_Channel1;
    hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY;
    hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE;
    hdma_adc1.Init.MemInc = DMA_MINC_ENABLE;
 8001d40:	2280      	movs	r2, #128	; 0x80
    hdma_adc1.Instance = DMA1_Channel1;
 8001d42:	4c10      	ldr	r4, [pc, #64]	; (8001d84 <HAL_ADC_MspInit+0xd4>)
 8001d44:	4b10      	ldr	r3, [pc, #64]	; (8001d88 <HAL_ADC_MspInit+0xd8>)
    hdma_adc1.Init.MemInc = DMA_MINC_ENABLE;
 8001d46:	60e2      	str	r2, [r4, #12]
    hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
 8001d48:	f44f 7200 	mov.w	r2, #512	; 0x200
    hdma_adc1.Instance = DMA1_Channel1;
 8001d4c:	6023      	str	r3, [r4, #0]
    hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
 8001d4e:	6122      	str	r2, [r4, #16]
    hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY;
 8001d50:	2300      	movs	r3, #0
    hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
 8001d52:	f44f 6200 	mov.w	r2, #2048	; 0x800
    hdma_adc1.Init.Mode = DMA_NORMAL;
    hdma_adc1.Init.Priority = DMA_PRIORITY_LOW;
    if (HAL_DMA_Init(&hdma_adc1) != HAL_OK)
 8001d56:	4620      	mov	r0, r4
    hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY;
 8001d58:	6063      	str	r3, [r4, #4]
    hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE;
 8001d5a:	60a3      	str	r3, [r4, #8]
    hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
 8001d5c:	6162      	str	r2, [r4, #20]
    hdma_adc1.Init.Mode = DMA_NORMAL;
 8001d5e:	61a3      	str	r3, [r4, #24]
    hdma_adc1.Init.Priority = DMA_PRIORITY_LOW;
 8001d60:	61e3      	str	r3, [r4, #28]
    if (HAL_DMA_Init(&hdma_adc1) != HAL_OK)
 8001d62:	f7fe fda9 	bl	80008b8 <HAL_DMA_Init>
 8001d66:	b108      	cbz	r0, 8001d6c <HAL_ADC_MspInit+0xbc>
    {
      Error_Handler();
 8001d68:	f7ff ff7e 	bl	8001c68 <Error_Handler>
    }

    __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc1);
 8001d6c:	622c      	str	r4, [r5, #32]
 8001d6e:	6265      	str	r5, [r4, #36]	; 0x24
  /* USER CODE BEGIN ADC1_MspInit 1 */

  /* USER CODE END ADC1_MspInit 1 */
  }

}
 8001d70:	b009      	add	sp, #36	; 0x24
 8001d72:	bd30      	pop	{r4, r5, pc}
 8001d74:	40012400 	.word	0x40012400
 8001d78:	40011000 	.word	0x40011000
 8001d7c:	40010800 	.word	0x40010800
 8001d80:	40010c00 	.word	0x40010c00
 8001d84:	2000009c 	.word	0x2000009c
 8001d88:	40020008 	.word	0x40020008

08001d8c <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
 8001d8c:	b510      	push	{r4, lr}
 8001d8e:	4604      	mov	r4, r0
 8001d90:	b086      	sub	sp, #24
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8001d92:	2210      	movs	r2, #16
 8001d94:	2100      	movs	r1, #0
 8001d96:	a802      	add	r0, sp, #8
 8001d98:	f000 f8ba 	bl	8001f10 <memset>
  if(huart->Instance==USART1)
 8001d9c:	6822      	ldr	r2, [r4, #0]
 8001d9e:	4b17      	ldr	r3, [pc, #92]	; (8001dfc <HAL_UART_MspInit+0x70>)
 8001da0:	429a      	cmp	r2, r3
 8001da2:	d128      	bne.n	8001df6 <HAL_UART_MspInit+0x6a>
  {
  /* USER CODE BEGIN USART1_MspInit 0 */

  /* USER CODE END USART1_MspInit 0 */
    /* Peripheral clock enable */
    __HAL_RCC_USART1_CLK_ENABLE();
 8001da4:	f503 4358 	add.w	r3, r3, #55296	; 0xd800
 8001da8:	699a      	ldr	r2, [r3, #24]
    PA10     ------> USART1_RX 
    */
    GPIO_InitStruct.Pin = GPIO_PIN_9;
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8001daa:	a902      	add	r1, sp, #8
    __HAL_RCC_USART1_CLK_ENABLE();
 8001dac:	f442 4280 	orr.w	r2, r2, #16384	; 0x4000
 8001db0:	619a      	str	r2, [r3, #24]
 8001db2:	699a      	ldr	r2, [r3, #24]
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8001db4:	4812      	ldr	r0, [pc, #72]	; (8001e00 <HAL_UART_MspInit+0x74>)
    __HAL_RCC_USART1_CLK_ENABLE();
 8001db6:	f402 4280 	and.w	r2, r2, #16384	; 0x4000
 8001dba:	9200      	str	r2, [sp, #0]
 8001dbc:	9a00      	ldr	r2, [sp, #0]
    __HAL_RCC_GPIOA_CLK_ENABLE();
 8001dbe:	699a      	ldr	r2, [r3, #24]
 8001dc0:	f042 0204 	orr.w	r2, r2, #4
 8001dc4:	619a      	str	r2, [r3, #24]
 8001dc6:	699b      	ldr	r3, [r3, #24]
 8001dc8:	f003 0304 	and.w	r3, r3, #4
 8001dcc:	9301      	str	r3, [sp, #4]
 8001dce:	9b01      	ldr	r3, [sp, #4]
    GPIO_InitStruct.Pin = GPIO_PIN_9;
 8001dd0:	f44f 7300 	mov.w	r3, #512	; 0x200
 8001dd4:	9302      	str	r3, [sp, #8]
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 8001dd6:	2302      	movs	r3, #2
 8001dd8:	9303      	str	r3, [sp, #12]
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
 8001dda:	2303      	movs	r3, #3
 8001ddc:	9305      	str	r3, [sp, #20]
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8001dde:	f7fe ff33 	bl	8000c48 <HAL_GPIO_Init>

    GPIO_InitStruct.Pin = GPIO_PIN_10;
 8001de2:	f44f 6380 	mov.w	r3, #1024	; 0x400
 8001de6:	9302      	str	r3, [sp, #8]
    GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
 8001de8:	2300      	movs	r3, #0
    GPIO_InitStruct.Pull = GPIO_NOPULL;
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8001dea:	a902      	add	r1, sp, #8
 8001dec:	4804      	ldr	r0, [pc, #16]	; (8001e00 <HAL_UART_MspInit+0x74>)
    GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
 8001dee:	9303      	str	r3, [sp, #12]
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 8001df0:	9304      	str	r3, [sp, #16]
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8001df2:	f7fe ff29 	bl	8000c48 <HAL_GPIO_Init>
  /* USER CODE BEGIN USART1_MspInit 1 */

  /* USER CODE END USART1_MspInit 1 */
  }

}
 8001df6:	b006      	add	sp, #24
 8001df8:	bd10      	pop	{r4, pc}
 8001dfa:	bf00      	nop
 8001dfc:	40013800 	.word	0x40013800
 8001e00:	40010800 	.word	0x40010800

08001e04 <NMI_Handler>:
 8001e04:	4770      	bx	lr

08001e06 <HardFault_Handler>:

/**
  * @brief This function handles Hard fault interrupt.
  */
void HardFault_Handler(void)
{
 8001e06:	e7fe      	b.n	8001e06 <HardFault_Handler>

08001e08 <MemManage_Handler>:

/**
  * @brief This function handles Memory management fault.
  */
void MemManage_Handler(void)
{
 8001e08:	e7fe      	b.n	8001e08 <MemManage_Handler>

08001e0a <BusFault_Handler>:

/**
  * @brief This function handles Prefetch fault, memory access fault.
  */
void BusFault_Handler(void)
{
 8001e0a:	e7fe      	b.n	8001e0a <BusFault_Handler>

08001e0c <UsageFault_Handler>:

/**
  * @brief This function handles Undefined instruction or illegal state.
  */
void UsageFault_Handler(void)
{
 8001e0c:	e7fe      	b.n	8001e0c <UsageFault_Handler>

08001e0e <SVC_Handler>:
 8001e0e:	4770      	bx	lr

08001e10 <DebugMon_Handler>:
 8001e10:	4770      	bx	lr

08001e12 <PendSV_Handler>:

/**
  * @brief This function handles Pendable request for system service.
  */
void PendSV_Handler(void)
{
 8001e12:	4770      	bx	lr

08001e14 <SysTick_Handler>:
void SysTick_Handler(void)
{
  /* USER CODE BEGIN SysTick_IRQn 0 */

  /* USER CODE END SysTick_IRQn 0 */
  HAL_IncTick();
 8001e14:	f7fe ba3c 	b.w	8000290 <HAL_IncTick>

08001e18 <DMA1_Channel1_IRQHandler>:
void DMA1_Channel1_IRQHandler(void)
{
  /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */

  /* USER CODE END DMA1_Channel1_IRQn 0 */
  HAL_DMA_IRQHandler(&hdma_adc1);
 8001e18:	4801      	ldr	r0, [pc, #4]	; (8001e20 <DMA1_Channel1_IRQHandler+0x8>)
 8001e1a:	f7fe be39 	b.w	8000a90 <HAL_DMA_IRQHandler>
 8001e1e:	bf00      	nop
 8001e20:	2000009c 	.word	0x2000009c

08001e24 <USART1_IRQHandler>:
void USART1_IRQHandler(void)
{
  /* USER CODE BEGIN USART1_IRQn 0 */

  /* USER CODE END USART1_IRQn 0 */
  HAL_UART_IRQHandler(&huart1);
 8001e24:	4801      	ldr	r0, [pc, #4]	; (8001e2c <USART1_IRQHandler+0x8>)
 8001e26:	f7ff bcb1 	b.w	800178c <HAL_UART_IRQHandler>
 8001e2a:	bf00      	nop
 8001e2c:	2000005c 	.word	0x2000005c

08001e30 <SystemInit>:
  */
void SystemInit (void)
{
  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
  /* Set HSION bit */
  RCC->CR |= 0x00000001U;
 8001e30:	4b0f      	ldr	r3, [pc, #60]	; (8001e70 <SystemInit+0x40>)
 8001e32:	681a      	ldr	r2, [r3, #0]
 8001e34:	f042 0201 	orr.w	r2, r2, #1
 8001e38:	601a      	str	r2, [r3, #0]

  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
#if !defined(STM32F105xC) && !defined(STM32F107xC)
  RCC->CFGR &= 0xF8FF0000U;
 8001e3a:	6859      	ldr	r1, [r3, #4]
 8001e3c:	4a0d      	ldr	r2, [pc, #52]	; (8001e74 <SystemInit+0x44>)
 8001e3e:	400a      	ands	r2, r1
 8001e40:	605a      	str	r2, [r3, #4]
#else
  RCC->CFGR &= 0xF0FF0000U;
#endif /* STM32F105xC */   
  
  /* Reset HSEON, CSSON and PLLON bits */
  RCC->CR &= 0xFEF6FFFFU;
 8001e42:	681a      	ldr	r2, [r3, #0]
 8001e44:	f022 7284 	bic.w	r2, r2, #17301504	; 0x1080000
 8001e48:	f422 3280 	bic.w	r2, r2, #65536	; 0x10000
 8001e4c:	601a      	str	r2, [r3, #0]

  /* Reset HSEBYP bit */
  RCC->CR &= 0xFFFBFFFFU;
 8001e4e:	681a      	ldr	r2, [r3, #0]
 8001e50:	f422 2280 	bic.w	r2, r2, #262144	; 0x40000
 8001e54:	601a      	str	r2, [r3, #0]

  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
  RCC->CFGR &= 0xFF80FFFFU;
 8001e56:	685a      	ldr	r2, [r3, #4]
 8001e58:	f422 02fe 	bic.w	r2, r2, #8323072	; 0x7f0000
 8001e5c:	605a      	str	r2, [r3, #4]

  /* Reset CFGR2 register */
  RCC->CFGR2 = 0x00000000U;      
#else
  /* Disable all interrupts and clear pending bits  */
  RCC->CIR = 0x009F0000U;
 8001e5e:	f44f 021f 	mov.w	r2, #10420224	; 0x9f0000
 8001e62:	609a      	str	r2, [r3, #8]
#endif 

#ifdef VECT_TAB_SRAM
  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#else
  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
 8001e64:	f04f 6200 	mov.w	r2, #134217728	; 0x8000000
 8001e68:	4b03      	ldr	r3, [pc, #12]	; (8001e78 <SystemInit+0x48>)
 8001e6a:	609a      	str	r2, [r3, #8]
 8001e6c:	4770      	bx	lr
 8001e6e:	bf00      	nop
 8001e70:	40021000 	.word	0x40021000
 8001e74:	f8ff0000 	.word	0xf8ff0000
 8001e78:	e000ed00 	.word	0xe000ed00

08001e7c <Reset_Handler>:
  .weak Reset_Handler
  .type Reset_Handler, %function
Reset_Handler:

/* Copy the data segment initializers from flash to SRAM */
  movs r1, #0
 8001e7c:	2100      	movs	r1, #0
  b LoopCopyDataInit
 8001e7e:	e003      	b.n	8001e88 <LoopCopyDataInit>

08001e80 <CopyDataInit>:

CopyDataInit:
  ldr r3, =_sidata
 8001e80:	4b0b      	ldr	r3, [pc, #44]	; (8001eb0 <LoopFillZerobss+0x14>)
  ldr r3, [r3, r1]
 8001e82:	585b      	ldr	r3, [r3, r1]
  str r3, [r0, r1]
 8001e84:	5043      	str	r3, [r0, r1]
  adds r1, r1, #4
 8001e86:	3104      	adds	r1, #4

08001e88 <LoopCopyDataInit>:

LoopCopyDataInit:
  ldr r0, =_sdata
 8001e88:	480a      	ldr	r0, [pc, #40]	; (8001eb4 <LoopFillZerobss+0x18>)
  ldr r3, =_edata
 8001e8a:	4b0b      	ldr	r3, [pc, #44]	; (8001eb8 <LoopFillZerobss+0x1c>)
  adds r2, r0, r1
 8001e8c:	1842      	adds	r2, r0, r1
  cmp r2, r3
 8001e8e:	429a      	cmp	r2, r3
  bcc CopyDataInit
 8001e90:	d3f6      	bcc.n	8001e80 <CopyDataInit>
  ldr r2, =_sbss
 8001e92:	4a0a      	ldr	r2, [pc, #40]	; (8001ebc <LoopFillZerobss+0x20>)
  b LoopFillZerobss
 8001e94:	e002      	b.n	8001e9c <LoopFillZerobss>

08001e96 <FillZerobss>:
/* Zero fill the bss segment. */
FillZerobss:
  movs r3, #0
 8001e96:	2300      	movs	r3, #0
  str r3, [r2], #4
 8001e98:	f842 3b04 	str.w	r3, [r2], #4

08001e9c <LoopFillZerobss>:

LoopFillZerobss:
  ldr r3, = _ebss
 8001e9c:	4b08      	ldr	r3, [pc, #32]	; (8001ec0 <LoopFillZerobss+0x24>)
  cmp r2, r3
 8001e9e:	429a      	cmp	r2, r3
  bcc FillZerobss
 8001ea0:	d3f9      	bcc.n	8001e96 <FillZerobss>

/* Call the clock system intitialization function.*/
    bl  SystemInit
 8001ea2:	f7ff ffc5 	bl	8001e30 <SystemInit>
/* Call static constructors */
    bl __libc_init_array
 8001ea6:	f000 f80f 	bl	8001ec8 <__libc_init_array>
/* Call the application's entry point.*/
  bl main
 8001eaa:	f7ff fd4d 	bl	8001948 <main>
  bx lr
 8001eae:	4770      	bx	lr
  ldr r3, =_sidata
 8001eb0:	08001f78 	.word	0x08001f78
  ldr r0, =_sdata
 8001eb4:	20000000 	.word	0x20000000
  ldr r3, =_edata
 8001eb8:	2000000c 	.word	0x2000000c
  ldr r2, =_sbss
 8001ebc:	2000000c 	.word	0x2000000c
  ldr r3, = _ebss
 8001ec0:	20000118 	.word	0x20000118

08001ec4 <ADC1_2_IRQHandler>:
 * @retval : None
*/
    .section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
  b Infinite_Loop
 8001ec4:	e7fe      	b.n	8001ec4 <ADC1_2_IRQHandler>
	...

08001ec8 <__libc_init_array>:
 8001ec8:	b570      	push	{r4, r5, r6, lr}
 8001eca:	2500      	movs	r5, #0
 8001ecc:	4e0c      	ldr	r6, [pc, #48]	; (8001f00 <__libc_init_array+0x38>)
 8001ece:	4c0d      	ldr	r4, [pc, #52]	; (8001f04 <__libc_init_array+0x3c>)
 8001ed0:	1ba4      	subs	r4, r4, r6
 8001ed2:	10a4      	asrs	r4, r4, #2
 8001ed4:	42a5      	cmp	r5, r4
 8001ed6:	d109      	bne.n	8001eec <__libc_init_array+0x24>
 8001ed8:	f000 f822 	bl	8001f20 <_init>
 8001edc:	2500      	movs	r5, #0
 8001ede:	4e0a      	ldr	r6, [pc, #40]	; (8001f08 <__libc_init_array+0x40>)
 8001ee0:	4c0a      	ldr	r4, [pc, #40]	; (8001f0c <__libc_init_array+0x44>)
 8001ee2:	1ba4      	subs	r4, r4, r6
 8001ee4:	10a4      	asrs	r4, r4, #2
 8001ee6:	42a5      	cmp	r5, r4
 8001ee8:	d105      	bne.n	8001ef6 <__libc_init_array+0x2e>
 8001eea:	bd70      	pop	{r4, r5, r6, pc}
 8001eec:	f856 3025 	ldr.w	r3, [r6, r5, lsl #2]
 8001ef0:	4798      	blx	r3
 8001ef2:	3501      	adds	r5, #1
 8001ef4:	e7ee      	b.n	8001ed4 <__libc_init_array+0xc>
 8001ef6:	f856 3025 	ldr.w	r3, [r6, r5, lsl #2]
 8001efa:	4798      	blx	r3
 8001efc:	3501      	adds	r5, #1
 8001efe:	e7f2      	b.n	8001ee6 <__libc_init_array+0x1e>
 8001f00:	08001f70 	.word	0x08001f70
 8001f04:	08001f70 	.word	0x08001f70
 8001f08:	08001f70 	.word	0x08001f70
 8001f0c:	08001f74 	.word	0x08001f74

08001f10 <memset>:
 8001f10:	4603      	mov	r3, r0
 8001f12:	4402      	add	r2, r0
 8001f14:	4293      	cmp	r3, r2
 8001f16:	d100      	bne.n	8001f1a <memset+0xa>
 8001f18:	4770      	bx	lr
 8001f1a:	f803 1b01 	strb.w	r1, [r3], #1
 8001f1e:	e7f9      	b.n	8001f14 <memset+0x4>

08001f20 <_init>:
 8001f20:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 8001f22:	bf00      	nop
 8001f24:	bcf8      	pop	{r3, r4, r5, r6, r7}
 8001f26:	bc08      	pop	{r3}
 8001f28:	469e      	mov	lr, r3
 8001f2a:	4770      	bx	lr

08001f2c <_fini>:
 8001f2c:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 8001f2e:	bf00      	nop
 8001f30:	bcf8      	pop	{r3, r4, r5, r6, r7}
 8001f32:	bc08      	pop	{r3}
 8001f34:	469e      	mov	lr, r3
 8001f36:	4770      	bx	lr