STM32F103_ATTEN_PLL_Zig/Debug/STM32F103_ATTEN_PLL_Zig.list

STM32F103_ATTEN_PLL_Zig.elf:     file format elf32-littlearm

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .isr_vector   000001e4  08004000  08004000  00004000  2**0
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  1 .text         00002814  080041e4  080041e4  000041e4  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  2 .rodata       0000009c  080069f8  080069f8  000069f8  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  3 .init_array   00000004  08006a94  08006a94  00006a94  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  4 .fini_array   00000004  08006a98  08006a98  00006a98  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  5 .data         00000070  20000000  08006a9c  00010000  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  6 .bss          00000168  20000070  08006b0c  00010070  2**2
                  ALLOC
  7 ._user_heap_stack 00000600  200001d8  08006b0c  000101d8  2**0
                  ALLOC
  8 .ARM.attributes 00000029  00000000  00000000  00010070  2**0
                  CONTENTS, READONLY
  9 .debug_info   0001557e  00000000  00000000  00010099  2**0
                  CONTENTS, READONLY, DEBUGGING
 10 .debug_abbrev 00002bd3  00000000  00000000  00025617  2**0
                  CONTENTS, READONLY, DEBUGGING
 11 .debug_loc    00007133  00000000  00000000  000281ea  2**0
                  CONTENTS, READONLY, DEBUGGING
 12 .debug_aranges 00000a40  00000000  00000000  0002f320  2**3
                  CONTENTS, READONLY, DEBUGGING
 13 .debug_ranges 00000da0  00000000  00000000  0002fd60  2**3
                  CONTENTS, READONLY, DEBUGGING
 14 .debug_line   000060b7  00000000  00000000  00030b00  2**0
                  CONTENTS, READONLY, DEBUGGING
 15 .debug_str    00003d7c  00000000  00000000  00036bb7  2**0
                  CONTENTS, READONLY, DEBUGGING
 16 .comment      0000007c  00000000  00000000  0003a933  2**0
                  CONTENTS, READONLY
 17 .debug_frame  000023d8  00000000  00000000  0003a9b0  2**2
                  CONTENTS, READONLY, DEBUGGING

Disassembly of section .text:

080041e4 <__do_global_dtors_aux>:
 80041e4:	b510      	push	{r4, lr}
 80041e6:	4c05      	ldr	r4, [pc, #20]	; (80041fc <__do_global_dtors_aux+0x18>)
 80041e8:	7823      	ldrb	r3, [r4, #0]
 80041ea:	b933      	cbnz	r3, 80041fa <__do_global_dtors_aux+0x16>
 80041ec:	4b04      	ldr	r3, [pc, #16]	; (8004200 <__do_global_dtors_aux+0x1c>)
 80041ee:	b113      	cbz	r3, 80041f6 <__do_global_dtors_aux+0x12>
 80041f0:	4804      	ldr	r0, [pc, #16]	; (8004204 <__do_global_dtors_aux+0x20>)
 80041f2:	f3af 8000 	nop.w
 80041f6:	2301      	movs	r3, #1
 80041f8:	7023      	strb	r3, [r4, #0]
 80041fa:	bd10      	pop	{r4, pc}
 80041fc:	20000070 	.word	0x20000070
 8004200:	00000000 	.word	0x00000000
 8004204:	080069e0 	.word	0x080069e0

08004208 <frame_dummy>:
 8004208:	b508      	push	{r3, lr}
 800420a:	4b03      	ldr	r3, [pc, #12]	; (8004218 <frame_dummy+0x10>)
 800420c:	b11b      	cbz	r3, 8004216 <frame_dummy+0xe>
 800420e:	4903      	ldr	r1, [pc, #12]	; (800421c <frame_dummy+0x14>)
 8004210:	4803      	ldr	r0, [pc, #12]	; (8004220 <frame_dummy+0x18>)
 8004212:	f3af 8000 	nop.w
 8004216:	bd08      	pop	{r3, pc}
 8004218:	00000000 	.word	0x00000000
 800421c:	20000074 	.word	0x20000074
 8004220:	080069e0 	.word	0x080069e0

08004224 <HAL_InitTick>:
  *       implementation  in user file.
  * @param TickPriority Tick interrupt priority.
  * @retval HAL status
  */
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
 8004224:	b538      	push	{r3, r4, r5, lr}
  /* Configure the SysTick to have interrupt in 1ms time basis*/
  if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
 8004226:	4b0e      	ldr	r3, [pc, #56]	; (8004260 <HAL_InitTick+0x3c>)
{
 8004228:	4605      	mov	r5, r0
  if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
 800422a:	7818      	ldrb	r0, [r3, #0]
 800422c:	f44f 737a 	mov.w	r3, #1000	; 0x3e8
 8004230:	fbb3 f3f0 	udiv	r3, r3, r0
 8004234:	4a0b      	ldr	r2, [pc, #44]	; (8004264 <HAL_InitTick+0x40>)
 8004236:	6810      	ldr	r0, [r2, #0]
 8004238:	fbb0 f0f3 	udiv	r0, r0, r3
 800423c:	f000 f9bc 	bl	80045b8 <HAL_SYSTICK_Config>
 8004240:	4604      	mov	r4, r0
 8004242:	b958      	cbnz	r0, 800425c <HAL_InitTick+0x38>
  {
    return HAL_ERROR;
  }

  /* Configure the SysTick IRQ priority */
  if (TickPriority < (1UL << __NVIC_PRIO_BITS))
 8004244:	2d0f      	cmp	r5, #15
 8004246:	d809      	bhi.n	800425c <HAL_InitTick+0x38>
  {
    HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
 8004248:	4602      	mov	r2, r0
 800424a:	4629      	mov	r1, r5
 800424c:	f04f 30ff 	mov.w	r0, #4294967295
 8004250:	f000 f972 	bl	8004538 <HAL_NVIC_SetPriority>
    uwTickPrio = TickPriority;
 8004254:	4b04      	ldr	r3, [pc, #16]	; (8004268 <HAL_InitTick+0x44>)
 8004256:	4620      	mov	r0, r4
 8004258:	601d      	str	r5, [r3, #0]
 800425a:	bd38      	pop	{r3, r4, r5, pc}
    return HAL_ERROR;
 800425c:	2001      	movs	r0, #1
    return HAL_ERROR;
  }

  /* Return function status */
  return HAL_OK;
}
 800425e:	bd38      	pop	{r3, r4, r5, pc}
 8004260:	20000000 	.word	0x20000000
 8004264:	20000008 	.word	0x20000008
 8004268:	20000004 	.word	0x20000004

0800426c <HAL_Init>:
  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
 800426c:	4a07      	ldr	r2, [pc, #28]	; (800428c <HAL_Init+0x20>)
{
 800426e:	b508      	push	{r3, lr}
  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
 8004270:	6813      	ldr	r3, [r2, #0]
  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
 8004272:	2003      	movs	r0, #3
  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
 8004274:	f043 0310 	orr.w	r3, r3, #16
 8004278:	6013      	str	r3, [r2, #0]
  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
 800427a:	f000 f94b 	bl	8004514 <HAL_NVIC_SetPriorityGrouping>
  HAL_InitTick(TICK_INT_PRIORITY);
 800427e:	2000      	movs	r0, #0
 8004280:	f7ff ffd0 	bl	8004224 <HAL_InitTick>
  HAL_MspInit();
 8004284:	f001 fcd4 	bl	8005c30 <HAL_MspInit>
}
 8004288:	2000      	movs	r0, #0
 800428a:	bd08      	pop	{r3, pc}
 800428c:	40022000 	.word	0x40022000

08004290 <HAL_IncTick>:
  *      implementations in user file.
  * @retval None
  */
__weak void HAL_IncTick(void)
{
  uwTick += uwTickFreq;
 8004290:	4a03      	ldr	r2, [pc, #12]	; (80042a0 <HAL_IncTick+0x10>)
 8004292:	4b04      	ldr	r3, [pc, #16]	; (80042a4 <HAL_IncTick+0x14>)
 8004294:	6811      	ldr	r1, [r2, #0]
 8004296:	781b      	ldrb	r3, [r3, #0]
 8004298:	440b      	add	r3, r1
 800429a:	6013      	str	r3, [r2, #0]
 800429c:	4770      	bx	lr
 800429e:	bf00      	nop
 80042a0:	200000a4 	.word	0x200000a4
 80042a4:	20000000 	.word	0x20000000

080042a8 <HAL_GetTick>:
  *       implementations in user file.
  * @retval tick value
  */
__weak uint32_t HAL_GetTick(void)
{
  return uwTick;
 80042a8:	4b01      	ldr	r3, [pc, #4]	; (80042b0 <HAL_GetTick+0x8>)
 80042aa:	6818      	ldr	r0, [r3, #0]
}
 80042ac:	4770      	bx	lr
 80042ae:	bf00      	nop
 80042b0:	200000a4 	.word	0x200000a4

080042b4 <HAL_ADC_ConfigChannel>:
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
{ 
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
  __IO uint32_t wait_loop_index = 0U;
 80042b4:	2300      	movs	r3, #0
{ 
 80042b6:	b573      	push	{r0, r1, r4, r5, r6, lr}
  __IO uint32_t wait_loop_index = 0U;
 80042b8:	9301      	str	r3, [sp, #4]
  assert_param(IS_ADC_CHANNEL(sConfig->Channel));
  assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
  assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
  
  /* Process locked */
  __HAL_LOCK(hadc);
 80042ba:	f890 3024 	ldrb.w	r3, [r0, #36]	; 0x24
 80042be:	2b01      	cmp	r3, #1
 80042c0:	d074      	beq.n	80043ac <HAL_ADC_ConfigChannel+0xf8>
 80042c2:	2301      	movs	r3, #1
  
  
  /* Regular sequence configuration */
  /* For Rank 1 to 6 */
  if (sConfig->Rank < 7U)
 80042c4:	684d      	ldr	r5, [r1, #4]
  __HAL_LOCK(hadc);
 80042c6:	f880 3024 	strb.w	r3, [r0, #36]	; 0x24
  if (sConfig->Rank < 7U)
 80042ca:	2d06      	cmp	r5, #6
 80042cc:	6802      	ldr	r2, [r0, #0]
 80042ce:	ea4f 0385 	mov.w	r3, r5, lsl #2
 80042d2:	680c      	ldr	r4, [r1, #0]
 80042d4:	d825      	bhi.n	8004322 <HAL_ADC_ConfigChannel+0x6e>
  {
    MODIFY_REG(hadc->Instance->SQR3                        ,
 80042d6:	442b      	add	r3, r5
 80042d8:	251f      	movs	r5, #31
 80042da:	6b56      	ldr	r6, [r2, #52]	; 0x34
 80042dc:	3b05      	subs	r3, #5
 80042de:	409d      	lsls	r5, r3
 80042e0:	ea26 0505 	bic.w	r5, r6, r5
 80042e4:	fa04 f303 	lsl.w	r3, r4, r3
 80042e8:	432b      	orrs	r3, r5
 80042ea:	6353      	str	r3, [r2, #52]	; 0x34
  }
  
  
  /* Channel sampling time configuration */
  /* For channels 10 to 17 */
  if (sConfig->Channel >= ADC_CHANNEL_10)
 80042ec:	2c09      	cmp	r4, #9
 80042ee:	ea4f 0344 	mov.w	r3, r4, lsl #1
 80042f2:	688d      	ldr	r5, [r1, #8]
 80042f4:	d92f      	bls.n	8004356 <HAL_ADC_ConfigChannel+0xa2>
  {
    MODIFY_REG(hadc->Instance->SMPR1                             ,
 80042f6:	2607      	movs	r6, #7
 80042f8:	4423      	add	r3, r4
 80042fa:	68d1      	ldr	r1, [r2, #12]
 80042fc:	3b1e      	subs	r3, #30
 80042fe:	409e      	lsls	r6, r3
 8004300:	ea21 0106 	bic.w	r1, r1, r6
 8004304:	fa05 f303 	lsl.w	r3, r5, r3
 8004308:	430b      	orrs	r3, r1
 800430a:	60d3      	str	r3, [r2, #12]
               ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
  }
  
  /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor  */
  /* and VREFINT measurement path.                                            */
  if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
 800430c:	f1a4 0310 	sub.w	r3, r4, #16
 8004310:	2b01      	cmp	r3, #1
 8004312:	d92b      	bls.n	800436c <HAL_ADC_ConfigChannel+0xb8>
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
 8004314:	2300      	movs	r3, #0
      tmp_hal_status = HAL_ERROR;
    }
  }
  
  /* Process unlocked */
  __HAL_UNLOCK(hadc);
 8004316:	2200      	movs	r2, #0
 8004318:	f880 2024 	strb.w	r2, [r0, #36]	; 0x24
  
  /* Return function status */
  return tmp_hal_status;
}
 800431c:	4618      	mov	r0, r3
 800431e:	b002      	add	sp, #8
 8004320:	bd70      	pop	{r4, r5, r6, pc}
  else if (sConfig->Rank < 13U)
 8004322:	2d0c      	cmp	r5, #12
 8004324:	d80b      	bhi.n	800433e <HAL_ADC_ConfigChannel+0x8a>
    MODIFY_REG(hadc->Instance->SQR2                        ,
 8004326:	442b      	add	r3, r5
 8004328:	251f      	movs	r5, #31
 800432a:	6b16      	ldr	r6, [r2, #48]	; 0x30
 800432c:	3b23      	subs	r3, #35	; 0x23
 800432e:	409d      	lsls	r5, r3
 8004330:	ea26 0505 	bic.w	r5, r6, r5
 8004334:	fa04 f303 	lsl.w	r3, r4, r3
 8004338:	432b      	orrs	r3, r5
 800433a:	6313      	str	r3, [r2, #48]	; 0x30
 800433c:	e7d6      	b.n	80042ec <HAL_ADC_ConfigChannel+0x38>
    MODIFY_REG(hadc->Instance->SQR1                        ,
 800433e:	442b      	add	r3, r5
 8004340:	251f      	movs	r5, #31
 8004342:	6ad6      	ldr	r6, [r2, #44]	; 0x2c
 8004344:	3b41      	subs	r3, #65	; 0x41
 8004346:	409d      	lsls	r5, r3
 8004348:	ea26 0505 	bic.w	r5, r6, r5
 800434c:	fa04 f303 	lsl.w	r3, r4, r3
 8004350:	432b      	orrs	r3, r5
 8004352:	62d3      	str	r3, [r2, #44]	; 0x2c
 8004354:	e7ca      	b.n	80042ec <HAL_ADC_ConfigChannel+0x38>
    MODIFY_REG(hadc->Instance->SMPR2                             ,
 8004356:	2607      	movs	r6, #7
 8004358:	6911      	ldr	r1, [r2, #16]
 800435a:	4423      	add	r3, r4
 800435c:	409e      	lsls	r6, r3
 800435e:	ea21 0106 	bic.w	r1, r1, r6
 8004362:	fa05 f303 	lsl.w	r3, r5, r3
 8004366:	430b      	orrs	r3, r1
 8004368:	6113      	str	r3, [r2, #16]
 800436a:	e7cf      	b.n	800430c <HAL_ADC_ConfigChannel+0x58>
    if (hadc->Instance == ADC1)
 800436c:	4b10      	ldr	r3, [pc, #64]	; (80043b0 <HAL_ADC_ConfigChannel+0xfc>)
 800436e:	429a      	cmp	r2, r3
 8004370:	d116      	bne.n	80043a0 <HAL_ADC_ConfigChannel+0xec>
      if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET)
 8004372:	6893      	ldr	r3, [r2, #8]
 8004374:	021b      	lsls	r3, r3, #8
 8004376:	d4cd      	bmi.n	8004314 <HAL_ADC_ConfigChannel+0x60>
        SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
 8004378:	6893      	ldr	r3, [r2, #8]
        if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
 800437a:	2c10      	cmp	r4, #16
        SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
 800437c:	f443 0300 	orr.w	r3, r3, #8388608	; 0x800000
 8004380:	6093      	str	r3, [r2, #8]
        if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
 8004382:	d1c7      	bne.n	8004314 <HAL_ADC_ConfigChannel+0x60>
          wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
 8004384:	4b0b      	ldr	r3, [pc, #44]	; (80043b4 <HAL_ADC_ConfigChannel+0x100>)
 8004386:	4a0c      	ldr	r2, [pc, #48]	; (80043b8 <HAL_ADC_ConfigChannel+0x104>)
 8004388:	681b      	ldr	r3, [r3, #0]
 800438a:	fbb3 f2f2 	udiv	r2, r3, r2
 800438e:	230a      	movs	r3, #10
 8004390:	4353      	muls	r3, r2
            wait_loop_index--;
 8004392:	9301      	str	r3, [sp, #4]
          while(wait_loop_index != 0U)
 8004394:	9b01      	ldr	r3, [sp, #4]
 8004396:	2b00      	cmp	r3, #0
 8004398:	d0bc      	beq.n	8004314 <HAL_ADC_ConfigChannel+0x60>
            wait_loop_index--;
 800439a:	9b01      	ldr	r3, [sp, #4]
 800439c:	3b01      	subs	r3, #1
 800439e:	e7f8      	b.n	8004392 <HAL_ADC_ConfigChannel+0xde>
      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
 80043a0:	6a83      	ldr	r3, [r0, #40]	; 0x28
 80043a2:	f043 0320 	orr.w	r3, r3, #32
 80043a6:	6283      	str	r3, [r0, #40]	; 0x28
      tmp_hal_status = HAL_ERROR;
 80043a8:	2301      	movs	r3, #1
 80043aa:	e7b4      	b.n	8004316 <HAL_ADC_ConfigChannel+0x62>
  __HAL_LOCK(hadc);
 80043ac:	2302      	movs	r3, #2
 80043ae:	e7b5      	b.n	800431c <HAL_ADC_ConfigChannel+0x68>
 80043b0:	40012400 	.word	0x40012400
 80043b4:	20000008 	.word	0x20000008
 80043b8:	000f4240 	.word	0x000f4240

080043bc <ADC_ConversionStop_Disable>:
  *         stopped to disable the ADC.
  * @param  hadc: ADC handle
  * @retval HAL status.
  */
HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc)
{
 80043bc:	b538      	push	{r3, r4, r5, lr}
  uint32_t tickstart = 0U;
  
  /* Verification if ADC is not already disabled */
  if (ADC_IS_ENABLE(hadc) != RESET)
 80043be:	6803      	ldr	r3, [r0, #0]
{
 80043c0:	4604      	mov	r4, r0
  if (ADC_IS_ENABLE(hadc) != RESET)
 80043c2:	689a      	ldr	r2, [r3, #8]
 80043c4:	07d2      	lsls	r2, r2, #31
 80043c6:	d401      	bmi.n	80043cc <ADC_ConversionStop_Disable+0x10>
      }
    }
  }
  
  /* Return HAL status */
  return HAL_OK;
 80043c8:	2000      	movs	r0, #0
 80043ca:	bd38      	pop	{r3, r4, r5, pc}
    __HAL_ADC_DISABLE(hadc);
 80043cc:	689a      	ldr	r2, [r3, #8]
 80043ce:	f022 0201 	bic.w	r2, r2, #1
 80043d2:	609a      	str	r2, [r3, #8]
    tickstart = HAL_GetTick();
 80043d4:	f7ff ff68 	bl	80042a8 <HAL_GetTick>
 80043d8:	4605      	mov	r5, r0
    while(ADC_IS_ENABLE(hadc) != RESET)
 80043da:	6823      	ldr	r3, [r4, #0]
 80043dc:	689b      	ldr	r3, [r3, #8]
 80043de:	07db      	lsls	r3, r3, #31
 80043e0:	d5f2      	bpl.n	80043c8 <ADC_ConversionStop_Disable+0xc>
      if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
 80043e2:	f7ff ff61 	bl	80042a8 <HAL_GetTick>
 80043e6:	1b40      	subs	r0, r0, r5
 80043e8:	2802      	cmp	r0, #2
 80043ea:	d9f6      	bls.n	80043da <ADC_ConversionStop_Disable+0x1e>
        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
 80043ec:	6aa3      	ldr	r3, [r4, #40]	; 0x28
        SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
 80043ee:	2001      	movs	r0, #1
        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
 80043f0:	f043 0310 	orr.w	r3, r3, #16
 80043f4:	62a3      	str	r3, [r4, #40]	; 0x28
        SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
 80043f6:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
 80043f8:	f043 0301 	orr.w	r3, r3, #1
 80043fc:	62e3      	str	r3, [r4, #44]	; 0x2c
 80043fe:	bd38      	pop	{r3, r4, r5, pc}

08004400 <HAL_ADC_Init>:
{
 8004400:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
  if(hadc == NULL)
 8004402:	4604      	mov	r4, r0
 8004404:	2800      	cmp	r0, #0
 8004406:	d077      	beq.n	80044f8 <HAL_ADC_Init+0xf8>
  if (hadc->State == HAL_ADC_STATE_RESET)
 8004408:	6a83      	ldr	r3, [r0, #40]	; 0x28
 800440a:	b923      	cbnz	r3, 8004416 <HAL_ADC_Init+0x16>
    ADC_CLEAR_ERRORCODE(hadc);
 800440c:	62c3      	str	r3, [r0, #44]	; 0x2c
    hadc->Lock = HAL_UNLOCKED;
 800440e:	f880 3024 	strb.w	r3, [r0, #36]	; 0x24
    HAL_ADC_MspInit(hadc);
 8004412:	f001 fc2f 	bl	8005c74 <HAL_ADC_MspInit>
  tmp_hal_status = ADC_ConversionStop_Disable(hadc);
 8004416:	4620      	mov	r0, r4
 8004418:	f7ff ffd0 	bl	80043bc <ADC_ConversionStop_Disable>
  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
 800441c:	6aa3      	ldr	r3, [r4, #40]	; 0x28
 800441e:	f013 0310 	ands.w	r3, r3, #16
 8004422:	d16b      	bne.n	80044fc <HAL_ADC_Init+0xfc>
 8004424:	2800      	cmp	r0, #0
 8004426:	d169      	bne.n	80044fc <HAL_ADC_Init+0xfc>
    ADC_STATE_CLR_SET(hadc->State,
 8004428:	6aa2      	ldr	r2, [r4, #40]	; 0x28
                ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) |
 800442a:	4937      	ldr	r1, [pc, #220]	; (8004508 <HAL_ADC_Init+0x108>)
    ADC_STATE_CLR_SET(hadc->State,
 800442c:	f422 5288 	bic.w	r2, r2, #4352	; 0x1100
 8004430:	f022 0202 	bic.w	r2, r2, #2
 8004434:	f042 0202 	orr.w	r2, r2, #2
 8004438:	62a2      	str	r2, [r4, #40]	; 0x28
                ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) |
 800443a:	e894 0024 	ldmia.w	r4, {r2, r5}
 800443e:	428a      	cmp	r2, r1
 8004440:	69e1      	ldr	r1, [r4, #28]
 8004442:	d104      	bne.n	800444e <HAL_ADC_Init+0x4e>
 8004444:	f5b1 2f40 	cmp.w	r1, #786432	; 0xc0000
 8004448:	bf08      	it	eq
 800444a:	f44f 2100 	moveq.w	r1, #524288	; 0x80000
                ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode)   );
 800444e:	68e6      	ldr	r6, [r4, #12]
                ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) |
 8004450:	ea45 0546 	orr.w	r5, r5, r6, lsl #1
 8004454:	4329      	orrs	r1, r5
    tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode));
 8004456:	68a5      	ldr	r5, [r4, #8]
 8004458:	f5b5 7f80 	cmp.w	r5, #256	; 0x100
 800445c:	d035      	beq.n	80044ca <HAL_ADC_Init+0xca>
 800445e:	2d01      	cmp	r5, #1
 8004460:	bf08      	it	eq
 8004462:	f44f 7380 	moveq.w	r3, #256	; 0x100
    if (hadc->Init.DiscontinuousConvMode == ENABLE)
 8004466:	6967      	ldr	r7, [r4, #20]
 8004468:	2f01      	cmp	r7, #1
 800446a:	d106      	bne.n	800447a <HAL_ADC_Init+0x7a>
      if (hadc->Init.ContinuousConvMode == DISABLE)
 800446c:	bb7e      	cbnz	r6, 80044ce <HAL_ADC_Init+0xce>
        SET_BIT(tmp_cr1, ADC_CR1_DISCEN                                            |
 800446e:	69a6      	ldr	r6, [r4, #24]
 8004470:	3e01      	subs	r6, #1
 8004472:	ea43 3346 	orr.w	r3, r3, r6, lsl #13
 8004476:	f443 6300 	orr.w	r3, r3, #2048	; 0x800
      MODIFY_REG(hadc->Instance->CR1,
 800447a:	6856      	ldr	r6, [r2, #4]
    if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE)
 800447c:	f5b5 7f80 	cmp.w	r5, #256	; 0x100
      MODIFY_REG(hadc->Instance->CR1,
 8004480:	f426 4669 	bic.w	r6, r6, #59648	; 0xe900
 8004484:	ea43 0306 	orr.w	r3, r3, r6
 8004488:	6053      	str	r3, [r2, #4]
      MODIFY_REG(hadc->Instance->CR2,
 800448a:	6896      	ldr	r6, [r2, #8]
 800448c:	4b1f      	ldr	r3, [pc, #124]	; (800450c <HAL_ADC_Init+0x10c>)
 800448e:	ea03 0306 	and.w	r3, r3, r6
 8004492:	ea43 0301 	orr.w	r3, r3, r1
 8004496:	6093      	str	r3, [r2, #8]
    if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE)
 8004498:	d001      	beq.n	800449e <HAL_ADC_Init+0x9e>
 800449a:	2d01      	cmp	r5, #1
 800449c:	d120      	bne.n	80044e0 <HAL_ADC_Init+0xe0>
      tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion);
 800449e:	6923      	ldr	r3, [r4, #16]
 80044a0:	3b01      	subs	r3, #1
 80044a2:	051b      	lsls	r3, r3, #20
    MODIFY_REG(hadc->Instance->SQR1,
 80044a4:	6ad5      	ldr	r5, [r2, #44]	; 0x2c
 80044a6:	f425 0570 	bic.w	r5, r5, #15728640	; 0xf00000
 80044aa:	432b      	orrs	r3, r5
 80044ac:	62d3      	str	r3, [r2, #44]	; 0x2c
    if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
 80044ae:	6892      	ldr	r2, [r2, #8]
 80044b0:	4b17      	ldr	r3, [pc, #92]	; (8004510 <HAL_ADC_Init+0x110>)
 80044b2:	4013      	ands	r3, r2
 80044b4:	4299      	cmp	r1, r3
 80044b6:	d115      	bne.n	80044e4 <HAL_ADC_Init+0xe4>
      ADC_CLEAR_ERRORCODE(hadc);
 80044b8:	2300      	movs	r3, #0
 80044ba:	62e3      	str	r3, [r4, #44]	; 0x2c
      ADC_STATE_CLR_SET(hadc->State,
 80044bc:	6aa3      	ldr	r3, [r4, #40]	; 0x28
 80044be:	f023 0303 	bic.w	r3, r3, #3
 80044c2:	f043 0301 	orr.w	r3, r3, #1
 80044c6:	62a3      	str	r3, [r4, #40]	; 0x28
 80044c8:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode));
 80044ca:	462b      	mov	r3, r5
 80044cc:	e7cb      	b.n	8004466 <HAL_ADC_Init+0x66>
        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
 80044ce:	6aa6      	ldr	r6, [r4, #40]	; 0x28
 80044d0:	f046 0620 	orr.w	r6, r6, #32
 80044d4:	62a6      	str	r6, [r4, #40]	; 0x28
        SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
 80044d6:	6ae6      	ldr	r6, [r4, #44]	; 0x2c
 80044d8:	f046 0601 	orr.w	r6, r6, #1
 80044dc:	62e6      	str	r6, [r4, #44]	; 0x2c
 80044de:	e7cc      	b.n	800447a <HAL_ADC_Init+0x7a>
  uint32_t tmp_sqr1 = 0U;
 80044e0:	2300      	movs	r3, #0
 80044e2:	e7df      	b.n	80044a4 <HAL_ADC_Init+0xa4>
      ADC_STATE_CLR_SET(hadc->State,
 80044e4:	6aa3      	ldr	r3, [r4, #40]	; 0x28
 80044e6:	f023 0312 	bic.w	r3, r3, #18
 80044ea:	f043 0310 	orr.w	r3, r3, #16
 80044ee:	62a3      	str	r3, [r4, #40]	; 0x28
      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
 80044f0:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
 80044f2:	f043 0301 	orr.w	r3, r3, #1
 80044f6:	62e3      	str	r3, [r4, #44]	; 0x2c
    return HAL_ERROR;
 80044f8:	2001      	movs	r0, #1
}
 80044fa:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
 80044fc:	6aa3      	ldr	r3, [r4, #40]	; 0x28
 80044fe:	f043 0310 	orr.w	r3, r3, #16
 8004502:	62a3      	str	r3, [r4, #40]	; 0x28
 8004504:	e7f8      	b.n	80044f8 <HAL_ADC_Init+0xf8>
 8004506:	bf00      	nop
 8004508:	40013c00 	.word	0x40013c00
 800450c:	ffe1f7fd 	.word	0xffe1f7fd
 8004510:	ff1f0efe 	.word	0xff1f0efe

08004514 <HAL_NVIC_SetPriorityGrouping>:
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
  uint32_t reg_value;
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */

  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
 8004514:	4a07      	ldr	r2, [pc, #28]	; (8004534 <HAL_NVIC_SetPriorityGrouping+0x20>)
  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
  reg_value  =  (reg_value                                   |
                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
 8004516:	0200      	lsls	r0, r0, #8
  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
 8004518:	68d3      	ldr	r3, [r2, #12]
                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
 800451a:	f400 60e0 	and.w	r0, r0, #1792	; 0x700
  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
 800451e:	f423 63e0 	bic.w	r3, r3, #1792	; 0x700
 8004522:	041b      	lsls	r3, r3, #16
 8004524:	0c1b      	lsrs	r3, r3, #16
 8004526:	f043 63bf 	orr.w	r3, r3, #100139008	; 0x5f80000
 800452a:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
  reg_value  =  (reg_value                                   |
 800452e:	4303      	orrs	r3, r0
  SCB->AIRCR =  reg_value;
 8004530:	60d3      	str	r3, [r2, #12]
 8004532:	4770      	bx	lr
 8004534:	e000ed00 	.word	0xe000ed00

08004538 <HAL_NVIC_SetPriority>:
  \details Reads the priority grouping field from the NVIC Interrupt Controller.
  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
 */
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
{
  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
 8004538:	4b17      	ldr	r3, [pc, #92]	; (8004598 <HAL_NVIC_SetPriority+0x60>)
  *         This parameter can be a value between 0 and 15
  *         A lower priority value indicates a higher priority.          
  * @retval None
  */
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{ 
 800453a:	b530      	push	{r4, r5, lr}
 800453c:	68dc      	ldr	r4, [r3, #12]
 800453e:	f3c4 2402 	ubfx	r4, r4, #8, #3
{
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
  uint32_t PreemptPriorityBits;
  uint32_t SubPriorityBits;

  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
 8004542:	f1c4 0307 	rsb	r3, r4, #7
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 8004546:	1d25      	adds	r5, r4, #4
  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
 8004548:	2b04      	cmp	r3, #4
 800454a:	bf28      	it	cs
 800454c:	2304      	movcs	r3, #4
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 800454e:	2d06      	cmp	r5, #6

  return (
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 8004550:	f04f 0501 	mov.w	r5, #1
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 8004554:	bf98      	it	ls
 8004556:	2400      	movls	r4, #0
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 8004558:	fa05 f303 	lsl.w	r3, r5, r3
 800455c:	f103 33ff 	add.w	r3, r3, #4294967295
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 8004560:	bf88      	it	hi
 8004562:	3c03      	subhi	r4, #3
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 8004564:	4019      	ands	r1, r3
 8004566:	40a1      	lsls	r1, r4
           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
 8004568:	fa05 f404 	lsl.w	r4, r5, r4
 800456c:	3c01      	subs	r4, #1
 800456e:	4022      	ands	r2, r4
  if ((int32_t)(IRQn) < 0)
 8004570:	2800      	cmp	r0, #0
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 8004572:	ea42 0201 	orr.w	r2, r2, r1
 8004576:	ea4f 1202 	mov.w	r2, r2, lsl #4
    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 800457a:	bfaf      	iteee	ge
 800457c:	f100 4060 	addge.w	r0, r0, #3758096384	; 0xe0000000
    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8004580:	4b06      	ldrlt	r3, [pc, #24]	; (800459c <HAL_NVIC_SetPriority+0x64>)
 8004582:	f000 000f 	andlt.w	r0, r0, #15
 8004586:	b2d2      	uxtblt	r2, r2
    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8004588:	bfa5      	ittet	ge
 800458a:	b2d2      	uxtbge	r2, r2
 800458c:	f500 4061 	addge.w	r0, r0, #57600	; 0xe100
    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8004590:	541a      	strblt	r2, [r3, r0]
    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8004592:	f880 2300 	strbge.w	r2, [r0, #768]	; 0x300
 8004596:	bd30      	pop	{r4, r5, pc}
 8004598:	e000ed00 	.word	0xe000ed00
 800459c:	e000ed14 	.word	0xe000ed14

080045a0 <HAL_NVIC_EnableIRQ>:
  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
 80045a0:	2301      	movs	r3, #1
 80045a2:	0942      	lsrs	r2, r0, #5
 80045a4:	f000 001f 	and.w	r0, r0, #31
 80045a8:	fa03 f000 	lsl.w	r0, r3, r0
 80045ac:	4b01      	ldr	r3, [pc, #4]	; (80045b4 <HAL_NVIC_EnableIRQ+0x14>)
 80045ae:	f843 0022 	str.w	r0, [r3, r2, lsl #2]
 80045b2:	4770      	bx	lr
 80045b4:	e000e100 	.word	0xe000e100

080045b8 <HAL_SYSTICK_Config>:
           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
           must contain a vendor-specific implementation of this function.
 */
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
 80045b8:	3801      	subs	r0, #1
 80045ba:	f1b0 7f80 	cmp.w	r0, #16777216	; 0x1000000
 80045be:	d20a      	bcs.n	80045d6 <HAL_SYSTICK_Config+0x1e>
    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 80045c0:	21f0      	movs	r1, #240	; 0xf0
  {
    return (1UL);                                                   /* Reload value impossible */
  }

  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
 80045c2:	4b06      	ldr	r3, [pc, #24]	; (80045dc <HAL_SYSTICK_Config+0x24>)
    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 80045c4:	4a06      	ldr	r2, [pc, #24]	; (80045e0 <HAL_SYSTICK_Config+0x28>)
  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
 80045c6:	6058      	str	r0, [r3, #4]
    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 80045c8:	f882 1023 	strb.w	r1, [r2, #35]	; 0x23
  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
 80045cc:	2000      	movs	r0, #0
  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
 80045ce:	2207      	movs	r2, #7
  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
 80045d0:	6098      	str	r0, [r3, #8]
  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
 80045d2:	601a      	str	r2, [r3, #0]
 80045d4:	4770      	bx	lr
    return (1UL);                                                   /* Reload value impossible */
 80045d6:	2001      	movs	r0, #1
  *                  - 1  Function failed.
  */
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
   return SysTick_Config(TicksNumb);
}
 80045d8:	4770      	bx	lr
 80045da:	bf00      	nop
 80045dc:	e000e010 	.word	0xe000e010
 80045e0:	e000ed00 	.word	0xe000ed00

080045e4 <HAL_DMA_Init>:
  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
  *               the configuration information for the specified DMA Channel.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
{
 80045e4:	b510      	push	{r4, lr}
  uint32_t tmp = 0U;

  /* Check the DMA handle allocation */
  if(hdma == NULL)
 80045e6:	2800      	cmp	r0, #0
 80045e8:	d032      	beq.n	8004650 <HAL_DMA_Init+0x6c>
  assert_param(IS_DMA_MODE(hdma->Init.Mode));
  assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));

#if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F100xE) || defined (STM32F105xC) || defined (STM32F107xC)
  /* calculation of the channel index */
  if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
 80045ea:	6801      	ldr	r1, [r0, #0]
 80045ec:	4b19      	ldr	r3, [pc, #100]	; (8004654 <HAL_DMA_Init+0x70>)
 80045ee:	2414      	movs	r4, #20
 80045f0:	4299      	cmp	r1, r3
 80045f2:	d825      	bhi.n	8004640 <HAL_DMA_Init+0x5c>
  {
    /* DMA1 */
    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
 80045f4:	4a18      	ldr	r2, [pc, #96]	; (8004658 <HAL_DMA_Init+0x74>)
    hdma->DmaBaseAddress = DMA1;
 80045f6:	f2a3 4307 	subw	r3, r3, #1031	; 0x407
    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
 80045fa:	440a      	add	r2, r1
 80045fc:	fbb2 f2f4 	udiv	r2, r2, r4
 8004600:	0092      	lsls	r2, r2, #2
 8004602:	6402      	str	r2, [r0, #64]	; 0x40
  tmp &= ((uint32_t)~(DMA_CCR_PL    | DMA_CCR_MSIZE  | DMA_CCR_PSIZE  | \
                      DMA_CCR_MINC  | DMA_CCR_PINC   | DMA_CCR_CIRC   | \
                      DMA_CCR_DIR));

  /* Prepare the DMA Channel configuration */
  tmp |=  hdma->Init.Direction        |
 8004604:	6884      	ldr	r4, [r0, #8]
    hdma->DmaBaseAddress = DMA2;
 8004606:	63c3      	str	r3, [r0, #60]	; 0x3c
  tmp |=  hdma->Init.Direction        |
 8004608:	6843      	ldr	r3, [r0, #4]
  tmp = hdma->Instance->CCR;
 800460a:	680a      	ldr	r2, [r1, #0]
  tmp |=  hdma->Init.Direction        |
 800460c:	4323      	orrs	r3, r4
          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
 800460e:	68c4      	ldr	r4, [r0, #12]
  tmp &= ((uint32_t)~(DMA_CCR_PL    | DMA_CCR_MSIZE  | DMA_CCR_PSIZE  | \
 8004610:	f422 527f 	bic.w	r2, r2, #16320	; 0x3fc0
          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
 8004614:	4323      	orrs	r3, r4
 8004616:	6904      	ldr	r4, [r0, #16]
  tmp &= ((uint32_t)~(DMA_CCR_PL    | DMA_CCR_MSIZE  | DMA_CCR_PSIZE  | \
 8004618:	f022 0230 	bic.w	r2, r2, #48	; 0x30
          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
 800461c:	4323      	orrs	r3, r4
          hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
 800461e:	6944      	ldr	r4, [r0, #20]
 8004620:	4323      	orrs	r3, r4
 8004622:	6984      	ldr	r4, [r0, #24]
 8004624:	4323      	orrs	r3, r4
          hdma->Init.Mode                | hdma->Init.Priority;
 8004626:	69c4      	ldr	r4, [r0, #28]
 8004628:	4323      	orrs	r3, r4
  tmp |=  hdma->Init.Direction        |
 800462a:	4313      	orrs	r3, r2

  /* Write to DMA Channel CR register */
  hdma->Instance->CCR = tmp;
 800462c:	600b      	str	r3, [r1, #0]

  /* Initialise the error code */
  hdma->ErrorCode = HAL_DMA_ERROR_NONE;

  /* Initialize the DMA state*/
  hdma->State = HAL_DMA_STATE_READY;
 800462e:	2201      	movs	r2, #1
  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
 8004630:	2300      	movs	r3, #0
  hdma->State = HAL_DMA_STATE_READY;
 8004632:	f880 2021 	strb.w	r2, [r0, #33]	; 0x21
  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
 8004636:	6383      	str	r3, [r0, #56]	; 0x38
  /* Allocate lock resource and initialize it */
  hdma->Lock = HAL_UNLOCKED;
 8004638:	f880 3020 	strb.w	r3, [r0, #32]

  return HAL_OK;
 800463c:	4618      	mov	r0, r3
 800463e:	bd10      	pop	{r4, pc}
    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
 8004640:	4b06      	ldr	r3, [pc, #24]	; (800465c <HAL_DMA_Init+0x78>)
 8004642:	440b      	add	r3, r1
 8004644:	fbb3 f3f4 	udiv	r3, r3, r4
 8004648:	009b      	lsls	r3, r3, #2
 800464a:	6403      	str	r3, [r0, #64]	; 0x40
    hdma->DmaBaseAddress = DMA2;
 800464c:	4b04      	ldr	r3, [pc, #16]	; (8004660 <HAL_DMA_Init+0x7c>)
 800464e:	e7d9      	b.n	8004604 <HAL_DMA_Init+0x20>
    return HAL_ERROR;
 8004650:	2001      	movs	r0, #1
}
 8004652:	bd10      	pop	{r4, pc}
 8004654:	40020407 	.word	0x40020407
 8004658:	bffdfff8 	.word	0xbffdfff8
 800465c:	bffdfbf8 	.word	0xbffdfbf8
 8004660:	40020400 	.word	0x40020400

08004664 <HAL_DMA_Abort_IT>:
  */
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
{  
  HAL_StatusTypeDef status = HAL_OK;
  
  if(HAL_DMA_STATE_BUSY != hdma->State)
 8004664:	f890 3021 	ldrb.w	r3, [r0, #33]	; 0x21
{  
 8004668:	b510      	push	{r4, lr}
  if(HAL_DMA_STATE_BUSY != hdma->State)
 800466a:	2b02      	cmp	r3, #2
 800466c:	d003      	beq.n	8004676 <HAL_DMA_Abort_IT+0x12>
  {
    /* no transfer ongoing */
    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
 800466e:	2304      	movs	r3, #4
 8004670:	6383      	str	r3, [r0, #56]	; 0x38
        
    status = HAL_ERROR;
 8004672:	2001      	movs	r0, #1
 8004674:	bd10      	pop	{r4, pc}
  }
  else
  { 
    /* Disable DMA IT */
    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
 8004676:	6803      	ldr	r3, [r0, #0]
 8004678:	681a      	ldr	r2, [r3, #0]
 800467a:	f022 020e 	bic.w	r2, r2, #14
 800467e:	601a      	str	r2, [r3, #0]

    /* Disable the channel */
    __HAL_DMA_DISABLE(hdma);
 8004680:	681a      	ldr	r2, [r3, #0]
 8004682:	f022 0201 	bic.w	r2, r2, #1
 8004686:	601a      	str	r2, [r3, #0]

    /* Clear all flags */
    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma));
 8004688:	4a29      	ldr	r2, [pc, #164]	; (8004730 <HAL_DMA_Abort_IT+0xcc>)
 800468a:	4293      	cmp	r3, r2
 800468c:	d924      	bls.n	80046d8 <HAL_DMA_Abort_IT+0x74>
 800468e:	f502 7262 	add.w	r2, r2, #904	; 0x388
 8004692:	4293      	cmp	r3, r2
 8004694:	d019      	beq.n	80046ca <HAL_DMA_Abort_IT+0x66>
 8004696:	3214      	adds	r2, #20
 8004698:	4293      	cmp	r3, r2
 800469a:	d018      	beq.n	80046ce <HAL_DMA_Abort_IT+0x6a>
 800469c:	3214      	adds	r2, #20
 800469e:	4293      	cmp	r3, r2
 80046a0:	d017      	beq.n	80046d2 <HAL_DMA_Abort_IT+0x6e>
 80046a2:	3214      	adds	r2, #20
 80046a4:	4293      	cmp	r3, r2
 80046a6:	bf0c      	ite	eq
 80046a8:	f44f 5380 	moveq.w	r3, #4096	; 0x1000
 80046ac:	f44f 3380 	movne.w	r3, #65536	; 0x10000
 80046b0:	4a20      	ldr	r2, [pc, #128]	; (8004734 <HAL_DMA_Abort_IT+0xd0>)
 80046b2:	6053      	str	r3, [r2, #4]

    /* Change the DMA state */
    hdma->State = HAL_DMA_STATE_READY;
 80046b4:	2301      	movs	r3, #1

    /* Process Unlocked */
    __HAL_UNLOCK(hdma);
 80046b6:	2400      	movs	r4, #0
    hdma->State = HAL_DMA_STATE_READY;
 80046b8:	f880 3021 	strb.w	r3, [r0, #33]	; 0x21

    /* Call User Abort callback */
    if(hdma->XferAbortCallback != NULL)
 80046bc:	6b43      	ldr	r3, [r0, #52]	; 0x34
    __HAL_UNLOCK(hdma);
 80046be:	f880 4020 	strb.w	r4, [r0, #32]
    if(hdma->XferAbortCallback != NULL)
 80046c2:	b39b      	cbz	r3, 800472c <HAL_DMA_Abort_IT+0xc8>
    {
      hdma->XferAbortCallback(hdma);
 80046c4:	4798      	blx	r3
  HAL_StatusTypeDef status = HAL_OK;
 80046c6:	4620      	mov	r0, r4
 80046c8:	bd10      	pop	{r4, pc}
    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma));
 80046ca:	2301      	movs	r3, #1
 80046cc:	e7f0      	b.n	80046b0 <HAL_DMA_Abort_IT+0x4c>
 80046ce:	2310      	movs	r3, #16
 80046d0:	e7ee      	b.n	80046b0 <HAL_DMA_Abort_IT+0x4c>
 80046d2:	f44f 7380 	mov.w	r3, #256	; 0x100
 80046d6:	e7eb      	b.n	80046b0 <HAL_DMA_Abort_IT+0x4c>
 80046d8:	4917      	ldr	r1, [pc, #92]	; (8004738 <HAL_DMA_Abort_IT+0xd4>)
 80046da:	428b      	cmp	r3, r1
 80046dc:	d016      	beq.n	800470c <HAL_DMA_Abort_IT+0xa8>
 80046de:	3114      	adds	r1, #20
 80046e0:	428b      	cmp	r3, r1
 80046e2:	d015      	beq.n	8004710 <HAL_DMA_Abort_IT+0xac>
 80046e4:	3114      	adds	r1, #20
 80046e6:	428b      	cmp	r3, r1
 80046e8:	d014      	beq.n	8004714 <HAL_DMA_Abort_IT+0xb0>
 80046ea:	3114      	adds	r1, #20
 80046ec:	428b      	cmp	r3, r1
 80046ee:	d014      	beq.n	800471a <HAL_DMA_Abort_IT+0xb6>
 80046f0:	3114      	adds	r1, #20
 80046f2:	428b      	cmp	r3, r1
 80046f4:	d014      	beq.n	8004720 <HAL_DMA_Abort_IT+0xbc>
 80046f6:	3114      	adds	r1, #20
 80046f8:	428b      	cmp	r3, r1
 80046fa:	d014      	beq.n	8004726 <HAL_DMA_Abort_IT+0xc2>
 80046fc:	4293      	cmp	r3, r2
 80046fe:	bf14      	ite	ne
 8004700:	f44f 3380 	movne.w	r3, #65536	; 0x10000
 8004704:	f04f 7380 	moveq.w	r3, #16777216	; 0x1000000
 8004708:	4a0c      	ldr	r2, [pc, #48]	; (800473c <HAL_DMA_Abort_IT+0xd8>)
 800470a:	e7d2      	b.n	80046b2 <HAL_DMA_Abort_IT+0x4e>
 800470c:	2301      	movs	r3, #1
 800470e:	e7fb      	b.n	8004708 <HAL_DMA_Abort_IT+0xa4>
 8004710:	2310      	movs	r3, #16
 8004712:	e7f9      	b.n	8004708 <HAL_DMA_Abort_IT+0xa4>
 8004714:	f44f 7380 	mov.w	r3, #256	; 0x100
 8004718:	e7f6      	b.n	8004708 <HAL_DMA_Abort_IT+0xa4>
 800471a:	f44f 5380 	mov.w	r3, #4096	; 0x1000
 800471e:	e7f3      	b.n	8004708 <HAL_DMA_Abort_IT+0xa4>
 8004720:	f44f 3380 	mov.w	r3, #65536	; 0x10000
 8004724:	e7f0      	b.n	8004708 <HAL_DMA_Abort_IT+0xa4>
 8004726:	f44f 1380 	mov.w	r3, #1048576	; 0x100000
 800472a:	e7ed      	b.n	8004708 <HAL_DMA_Abort_IT+0xa4>
  HAL_StatusTypeDef status = HAL_OK;
 800472c:	4618      	mov	r0, r3
    } 
  }
  return status;
}
 800472e:	bd10      	pop	{r4, pc}
 8004730:	40020080 	.word	0x40020080
 8004734:	40020400 	.word	0x40020400
 8004738:	40020008 	.word	0x40020008
 800473c:	40020000 	.word	0x40020000

08004740 <HAL_DMA_IRQHandler>:
  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
  *               the configuration information for the specified DMA Channel.  
  * @retval None
  */
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
{
 8004740:	b470      	push	{r4, r5, r6}
  uint32_t flag_it = hdma->DmaBaseAddress->ISR;
  uint32_t source_it = hdma->Instance->CCR;
  
  /* Half Transfer Complete Interrupt management ******************************/
  if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET))
 8004742:	2504      	movs	r5, #4
  uint32_t flag_it = hdma->DmaBaseAddress->ISR;
 8004744:	6bc6      	ldr	r6, [r0, #60]	; 0x3c
  if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET))
 8004746:	6c02      	ldr	r2, [r0, #64]	; 0x40
  uint32_t flag_it = hdma->DmaBaseAddress->ISR;
 8004748:	6834      	ldr	r4, [r6, #0]
  uint32_t source_it = hdma->Instance->CCR;
 800474a:	6803      	ldr	r3, [r0, #0]
  if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET))
 800474c:	4095      	lsls	r5, r2
 800474e:	4225      	tst	r5, r4
  uint32_t source_it = hdma->Instance->CCR;
 8004750:	6819      	ldr	r1, [r3, #0]
  if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET))
 8004752:	d055      	beq.n	8004800 <HAL_DMA_IRQHandler+0xc0>
 8004754:	074d      	lsls	r5, r1, #29
 8004756:	d553      	bpl.n	8004800 <HAL_DMA_IRQHandler+0xc0>
  {
    /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
    if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
 8004758:	681a      	ldr	r2, [r3, #0]
 800475a:	0696      	lsls	r6, r2, #26
    {
      /* Disable the half transfer interrupt */
      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
 800475c:	bf5e      	ittt	pl
 800475e:	681a      	ldrpl	r2, [r3, #0]
 8004760:	f022 0204 	bicpl.w	r2, r2, #4
 8004764:	601a      	strpl	r2, [r3, #0]
    }
    /* Clear the half transfer complete flag */
    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
 8004766:	4a60      	ldr	r2, [pc, #384]	; (80048e8 <HAL_DMA_IRQHandler+0x1a8>)
 8004768:	4293      	cmp	r3, r2
 800476a:	d91f      	bls.n	80047ac <HAL_DMA_IRQHandler+0x6c>
 800476c:	f502 7262 	add.w	r2, r2, #904	; 0x388
 8004770:	4293      	cmp	r3, r2
 8004772:	d014      	beq.n	800479e <HAL_DMA_IRQHandler+0x5e>
 8004774:	3214      	adds	r2, #20
 8004776:	4293      	cmp	r3, r2
 8004778:	d013      	beq.n	80047a2 <HAL_DMA_IRQHandler+0x62>
 800477a:	3214      	adds	r2, #20
 800477c:	4293      	cmp	r3, r2
 800477e:	d012      	beq.n	80047a6 <HAL_DMA_IRQHandler+0x66>
 8004780:	3214      	adds	r2, #20
 8004782:	4293      	cmp	r3, r2
 8004784:	bf0c      	ite	eq
 8004786:	f44f 4380 	moveq.w	r3, #16384	; 0x4000
 800478a:	f44f 2380 	movne.w	r3, #262144	; 0x40000
 800478e:	4a57      	ldr	r2, [pc, #348]	; (80048ec <HAL_DMA_IRQHandler+0x1ac>)
 8004790:	6053      	str	r3, [r2, #4]

    /* DMA peripheral state is not updated in Half Transfer */
    /* but in Transfer Complete case */

    if(hdma->XferHalfCpltCallback != NULL)
 8004792:	6ac3      	ldr	r3, [r0, #44]	; 0x2c
    hdma->State = HAL_DMA_STATE_READY;

    /* Process Unlocked */
    __HAL_UNLOCK(hdma);

    if (hdma->XferErrorCallback != NULL)
 8004794:	2b00      	cmp	r3, #0
 8004796:	f000 80a5 	beq.w	80048e4 <HAL_DMA_IRQHandler+0x1a4>
      /* Transfer error callback */
      hdma->XferErrorCallback(hdma);
    }
  }
  return;
}
 800479a:	bc70      	pop	{r4, r5, r6}
      hdma->XferErrorCallback(hdma);
 800479c:	4718      	bx	r3
    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
 800479e:	2304      	movs	r3, #4
 80047a0:	e7f5      	b.n	800478e <HAL_DMA_IRQHandler+0x4e>
 80047a2:	2340      	movs	r3, #64	; 0x40
 80047a4:	e7f3      	b.n	800478e <HAL_DMA_IRQHandler+0x4e>
 80047a6:	f44f 6380 	mov.w	r3, #1024	; 0x400
 80047aa:	e7f0      	b.n	800478e <HAL_DMA_IRQHandler+0x4e>
 80047ac:	4950      	ldr	r1, [pc, #320]	; (80048f0 <HAL_DMA_IRQHandler+0x1b0>)
 80047ae:	428b      	cmp	r3, r1
 80047b0:	d016      	beq.n	80047e0 <HAL_DMA_IRQHandler+0xa0>
 80047b2:	3114      	adds	r1, #20
 80047b4:	428b      	cmp	r3, r1
 80047b6:	d015      	beq.n	80047e4 <HAL_DMA_IRQHandler+0xa4>
 80047b8:	3114      	adds	r1, #20
 80047ba:	428b      	cmp	r3, r1
 80047bc:	d014      	beq.n	80047e8 <HAL_DMA_IRQHandler+0xa8>
 80047be:	3114      	adds	r1, #20
 80047c0:	428b      	cmp	r3, r1
 80047c2:	d014      	beq.n	80047ee <HAL_DMA_IRQHandler+0xae>
 80047c4:	3114      	adds	r1, #20
 80047c6:	428b      	cmp	r3, r1
 80047c8:	d014      	beq.n	80047f4 <HAL_DMA_IRQHandler+0xb4>
 80047ca:	3114      	adds	r1, #20
 80047cc:	428b      	cmp	r3, r1
 80047ce:	d014      	beq.n	80047fa <HAL_DMA_IRQHandler+0xba>
 80047d0:	4293      	cmp	r3, r2
 80047d2:	bf14      	ite	ne
 80047d4:	f44f 2380 	movne.w	r3, #262144	; 0x40000
 80047d8:	f04f 6380 	moveq.w	r3, #67108864	; 0x4000000
 80047dc:	4a45      	ldr	r2, [pc, #276]	; (80048f4 <HAL_DMA_IRQHandler+0x1b4>)
 80047de:	e7d7      	b.n	8004790 <HAL_DMA_IRQHandler+0x50>
 80047e0:	2304      	movs	r3, #4
 80047e2:	e7fb      	b.n	80047dc <HAL_DMA_IRQHandler+0x9c>
 80047e4:	2340      	movs	r3, #64	; 0x40
 80047e6:	e7f9      	b.n	80047dc <HAL_DMA_IRQHandler+0x9c>
 80047e8:	f44f 6380 	mov.w	r3, #1024	; 0x400
 80047ec:	e7f6      	b.n	80047dc <HAL_DMA_IRQHandler+0x9c>
 80047ee:	f44f 4380 	mov.w	r3, #16384	; 0x4000
 80047f2:	e7f3      	b.n	80047dc <HAL_DMA_IRQHandler+0x9c>
 80047f4:	f44f 2380 	mov.w	r3, #262144	; 0x40000
 80047f8:	e7f0      	b.n	80047dc <HAL_DMA_IRQHandler+0x9c>
 80047fa:	f44f 0380 	mov.w	r3, #4194304	; 0x400000
 80047fe:	e7ed      	b.n	80047dc <HAL_DMA_IRQHandler+0x9c>
  else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET))
 8004800:	2502      	movs	r5, #2
 8004802:	4095      	lsls	r5, r2
 8004804:	4225      	tst	r5, r4
 8004806:	d057      	beq.n	80048b8 <HAL_DMA_IRQHandler+0x178>
 8004808:	078d      	lsls	r5, r1, #30
 800480a:	d555      	bpl.n	80048b8 <HAL_DMA_IRQHandler+0x178>
    if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
 800480c:	681a      	ldr	r2, [r3, #0]
 800480e:	0694      	lsls	r4, r2, #26
 8004810:	d406      	bmi.n	8004820 <HAL_DMA_IRQHandler+0xe0>
      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);  
 8004812:	681a      	ldr	r2, [r3, #0]
 8004814:	f022 020a 	bic.w	r2, r2, #10
 8004818:	601a      	str	r2, [r3, #0]
      hdma->State = HAL_DMA_STATE_READY;
 800481a:	2201      	movs	r2, #1
 800481c:	f880 2021 	strb.w	r2, [r0, #33]	; 0x21
      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
 8004820:	4a31      	ldr	r2, [pc, #196]	; (80048e8 <HAL_DMA_IRQHandler+0x1a8>)
 8004822:	4293      	cmp	r3, r2
 8004824:	d91e      	bls.n	8004864 <HAL_DMA_IRQHandler+0x124>
 8004826:	f502 7262 	add.w	r2, r2, #904	; 0x388
 800482a:	4293      	cmp	r3, r2
 800482c:	d013      	beq.n	8004856 <HAL_DMA_IRQHandler+0x116>
 800482e:	3214      	adds	r2, #20
 8004830:	4293      	cmp	r3, r2
 8004832:	d012      	beq.n	800485a <HAL_DMA_IRQHandler+0x11a>
 8004834:	3214      	adds	r2, #20
 8004836:	4293      	cmp	r3, r2
 8004838:	d011      	beq.n	800485e <HAL_DMA_IRQHandler+0x11e>
 800483a:	3214      	adds	r2, #20
 800483c:	4293      	cmp	r3, r2
 800483e:	bf0c      	ite	eq
 8004840:	f44f 5300 	moveq.w	r3, #8192	; 0x2000
 8004844:	f44f 3300 	movne.w	r3, #131072	; 0x20000
 8004848:	4a28      	ldr	r2, [pc, #160]	; (80048ec <HAL_DMA_IRQHandler+0x1ac>)
 800484a:	6053      	str	r3, [r2, #4]
    __HAL_UNLOCK(hdma);
 800484c:	2300      	movs	r3, #0
 800484e:	f880 3020 	strb.w	r3, [r0, #32]
    if(hdma->XferCpltCallback != NULL)
 8004852:	6a83      	ldr	r3, [r0, #40]	; 0x28
 8004854:	e79e      	b.n	8004794 <HAL_DMA_IRQHandler+0x54>
      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
 8004856:	2302      	movs	r3, #2
 8004858:	e7f6      	b.n	8004848 <HAL_DMA_IRQHandler+0x108>
 800485a:	2320      	movs	r3, #32
 800485c:	e7f4      	b.n	8004848 <HAL_DMA_IRQHandler+0x108>
 800485e:	f44f 7300 	mov.w	r3, #512	; 0x200
 8004862:	e7f1      	b.n	8004848 <HAL_DMA_IRQHandler+0x108>
 8004864:	4922      	ldr	r1, [pc, #136]	; (80048f0 <HAL_DMA_IRQHandler+0x1b0>)
 8004866:	428b      	cmp	r3, r1
 8004868:	d016      	beq.n	8004898 <HAL_DMA_IRQHandler+0x158>
 800486a:	3114      	adds	r1, #20
 800486c:	428b      	cmp	r3, r1
 800486e:	d015      	beq.n	800489c <HAL_DMA_IRQHandler+0x15c>
 8004870:	3114      	adds	r1, #20
 8004872:	428b      	cmp	r3, r1
 8004874:	d014      	beq.n	80048a0 <HAL_DMA_IRQHandler+0x160>
 8004876:	3114      	adds	r1, #20
 8004878:	428b      	cmp	r3, r1
 800487a:	d014      	beq.n	80048a6 <HAL_DMA_IRQHandler+0x166>
 800487c:	3114      	adds	r1, #20
 800487e:	428b      	cmp	r3, r1
 8004880:	d014      	beq.n	80048ac <HAL_DMA_IRQHandler+0x16c>
 8004882:	3114      	adds	r1, #20
 8004884:	428b      	cmp	r3, r1
 8004886:	d014      	beq.n	80048b2 <HAL_DMA_IRQHandler+0x172>
 8004888:	4293      	cmp	r3, r2
 800488a:	bf14      	ite	ne
 800488c:	f44f 3300 	movne.w	r3, #131072	; 0x20000
 8004890:	f04f 7300 	moveq.w	r3, #33554432	; 0x2000000
 8004894:	4a17      	ldr	r2, [pc, #92]	; (80048f4 <HAL_DMA_IRQHandler+0x1b4>)
 8004896:	e7d8      	b.n	800484a <HAL_DMA_IRQHandler+0x10a>
 8004898:	2302      	movs	r3, #2
 800489a:	e7fb      	b.n	8004894 <HAL_DMA_IRQHandler+0x154>
 800489c:	2320      	movs	r3, #32
 800489e:	e7f9      	b.n	8004894 <HAL_DMA_IRQHandler+0x154>
 80048a0:	f44f 7300 	mov.w	r3, #512	; 0x200
 80048a4:	e7f6      	b.n	8004894 <HAL_DMA_IRQHandler+0x154>
 80048a6:	f44f 5300 	mov.w	r3, #8192	; 0x2000
 80048aa:	e7f3      	b.n	8004894 <HAL_DMA_IRQHandler+0x154>
 80048ac:	f44f 3300 	mov.w	r3, #131072	; 0x20000
 80048b0:	e7f0      	b.n	8004894 <HAL_DMA_IRQHandler+0x154>
 80048b2:	f44f 1300 	mov.w	r3, #2097152	; 0x200000
 80048b6:	e7ed      	b.n	8004894 <HAL_DMA_IRQHandler+0x154>
  else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
 80048b8:	2508      	movs	r5, #8
 80048ba:	4095      	lsls	r5, r2
 80048bc:	4225      	tst	r5, r4
 80048be:	d011      	beq.n	80048e4 <HAL_DMA_IRQHandler+0x1a4>
 80048c0:	0709      	lsls	r1, r1, #28
 80048c2:	d50f      	bpl.n	80048e4 <HAL_DMA_IRQHandler+0x1a4>
    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
 80048c4:	6819      	ldr	r1, [r3, #0]
 80048c6:	f021 010e 	bic.w	r1, r1, #14
 80048ca:	6019      	str	r1, [r3, #0]
    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
 80048cc:	2301      	movs	r3, #1
 80048ce:	fa03 f202 	lsl.w	r2, r3, r2
 80048d2:	6072      	str	r2, [r6, #4]
    hdma->ErrorCode = HAL_DMA_ERROR_TE;
 80048d4:	6383      	str	r3, [r0, #56]	; 0x38
    hdma->State = HAL_DMA_STATE_READY;
 80048d6:	f880 3021 	strb.w	r3, [r0, #33]	; 0x21
    __HAL_UNLOCK(hdma);
 80048da:	2300      	movs	r3, #0
 80048dc:	f880 3020 	strb.w	r3, [r0, #32]
    if (hdma->XferErrorCallback != NULL)
 80048e0:	6b03      	ldr	r3, [r0, #48]	; 0x30
 80048e2:	e757      	b.n	8004794 <HAL_DMA_IRQHandler+0x54>
}
 80048e4:	bc70      	pop	{r4, r5, r6}
 80048e6:	4770      	bx	lr
 80048e8:	40020080 	.word	0x40020080
 80048ec:	40020400 	.word	0x40020400
 80048f0:	40020008 	.word	0x40020008
 80048f4:	40020000 	.word	0x40020000

080048f8 <HAL_GPIO_Init>:
  * @param  GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
  *         the configuration information for the specified GPIO peripheral.
  * @retval None
  */
void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
 80048f8:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
  uint32_t position;
  uint32_t ioposition = 0x00U;
  uint32_t iocurrent = 0x00U;
  uint32_t temp = 0x00U;
  uint32_t config = 0x00U;
 80048fc:	2200      	movs	r2, #0
  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));

  /* Configure the port pins */
  for (position = 0U; position < GPIO_NUMBER; position++)
 80048fe:	4616      	mov	r6, r2
      /*--------------------- EXTI Mode Configuration ------------------------*/
      /* Configure the External Interrupt or event for the current IO */
      if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
      {
        /* Enable AFIO Clock */
        __HAL_RCC_AFIO_CLK_ENABLE();
 8004900:	4f6c      	ldr	r7, [pc, #432]	; (8004ab4 <HAL_GPIO_Init+0x1bc>)
 8004902:	4b6d      	ldr	r3, [pc, #436]	; (8004ab8 <HAL_GPIO_Init+0x1c0>)
        temp = AFIO->EXTICR[position >> 2U];
        CLEAR_BIT(temp, (0x0FU) << (4U * (position & 0x03U)));
        SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
 8004904:	f8df e1b8 	ldr.w	lr, [pc, #440]	; 8004ac0 <HAL_GPIO_Init+0x1c8>
      switch (GPIO_Init->Mode)
 8004908:	f8df c1b8 	ldr.w	ip, [pc, #440]	; 8004ac4 <HAL_GPIO_Init+0x1cc>
    ioposition = (0x01U << position);
 800490c:	f04f 0801 	mov.w	r8, #1
    iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
 8004910:	680c      	ldr	r4, [r1, #0]
    ioposition = (0x01U << position);
 8004912:	fa08 f806 	lsl.w	r8, r8, r6
    iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
 8004916:	ea08 0404 	and.w	r4, r8, r4
    if (iocurrent == ioposition)
 800491a:	45a0      	cmp	r8, r4
 800491c:	f040 8085 	bne.w	8004a2a <HAL_GPIO_Init+0x132>
      switch (GPIO_Init->Mode)
 8004920:	684d      	ldr	r5, [r1, #4]
 8004922:	2d12      	cmp	r5, #18
 8004924:	f000 80b7 	beq.w	8004a96 <HAL_GPIO_Init+0x19e>
 8004928:	f200 808d 	bhi.w	8004a46 <HAL_GPIO_Init+0x14e>
 800492c:	2d02      	cmp	r5, #2
 800492e:	f000 80af 	beq.w	8004a90 <HAL_GPIO_Init+0x198>
 8004932:	f200 8081 	bhi.w	8004a38 <HAL_GPIO_Init+0x140>
 8004936:	2d00      	cmp	r5, #0
 8004938:	f000 8091 	beq.w	8004a5e <HAL_GPIO_Init+0x166>
 800493c:	2d01      	cmp	r5, #1
 800493e:	f000 80a5 	beq.w	8004a8c <HAL_GPIO_Init+0x194>
      MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
 8004942:	f04f 090f 	mov.w	r9, #15
      configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL     : &GPIOx->CRH;
 8004946:	2cff      	cmp	r4, #255	; 0xff
 8004948:	bf93      	iteet	ls
 800494a:	4682      	movls	sl, r0
 800494c:	f106 4580 	addhi.w	r5, r6, #1073741824	; 0x40000000
 8004950:	3d08      	subhi	r5, #8
 8004952:	f8d0 b000 	ldrls.w	fp, [r0]
 8004956:	bf92      	itee	ls
 8004958:	00b5      	lslls	r5, r6, #2
 800495a:	f8d0 b004 	ldrhi.w	fp, [r0, #4]
 800495e:	00ad      	lslhi	r5, r5, #2
      MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
 8004960:	fa09 f805 	lsl.w	r8, r9, r5
 8004964:	ea2b 0808 	bic.w	r8, fp, r8
 8004968:	fa02 f505 	lsl.w	r5, r2, r5
      configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL     : &GPIOx->CRH;
 800496c:	bf88      	it	hi
 800496e:	f100 0a04 	addhi.w	sl, r0, #4
      MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
 8004972:	ea48 0505 	orr.w	r5, r8, r5
 8004976:	f8ca 5000 	str.w	r5, [sl]
      if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
 800497a:	f8d1 a004 	ldr.w	sl, [r1, #4]
 800497e:	f01a 5f80 	tst.w	sl, #268435456	; 0x10000000
 8004982:	d052      	beq.n	8004a2a <HAL_GPIO_Init+0x132>
        __HAL_RCC_AFIO_CLK_ENABLE();
 8004984:	69bd      	ldr	r5, [r7, #24]
 8004986:	f026 0803 	bic.w	r8, r6, #3
 800498a:	f045 0501 	orr.w	r5, r5, #1
 800498e:	61bd      	str	r5, [r7, #24]
 8004990:	69bd      	ldr	r5, [r7, #24]
 8004992:	f108 4880 	add.w	r8, r8, #1073741824	; 0x40000000
 8004996:	f005 0501 	and.w	r5, r5, #1
 800499a:	9501      	str	r5, [sp, #4]
 800499c:	f508 3880 	add.w	r8, r8, #65536	; 0x10000
        CLEAR_BIT(temp, (0x0FU) << (4U * (position & 0x03U)));
 80049a0:	f006 0b03 	and.w	fp, r6, #3
        __HAL_RCC_AFIO_CLK_ENABLE();
 80049a4:	9d01      	ldr	r5, [sp, #4]
        CLEAR_BIT(temp, (0x0FU) << (4U * (position & 0x03U)));
 80049a6:	ea4f 0b8b 	mov.w	fp, fp, lsl #2
        temp = AFIO->EXTICR[position >> 2U];
 80049aa:	f8d8 5008 	ldr.w	r5, [r8, #8]
        CLEAR_BIT(temp, (0x0FU) << (4U * (position & 0x03U)));
 80049ae:	fa09 f90b 	lsl.w	r9, r9, fp
 80049b2:	ea25 0909 	bic.w	r9, r5, r9
        SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
 80049b6:	4d41      	ldr	r5, [pc, #260]	; (8004abc <HAL_GPIO_Init+0x1c4>)
 80049b8:	42a8      	cmp	r0, r5
 80049ba:	d071      	beq.n	8004aa0 <HAL_GPIO_Init+0x1a8>
 80049bc:	f505 6580 	add.w	r5, r5, #1024	; 0x400
 80049c0:	42a8      	cmp	r0, r5
 80049c2:	d06f      	beq.n	8004aa4 <HAL_GPIO_Init+0x1ac>
 80049c4:	f505 6580 	add.w	r5, r5, #1024	; 0x400
 80049c8:	42a8      	cmp	r0, r5
 80049ca:	d06d      	beq.n	8004aa8 <HAL_GPIO_Init+0x1b0>
 80049cc:	f505 6580 	add.w	r5, r5, #1024	; 0x400
 80049d0:	42a8      	cmp	r0, r5
 80049d2:	d06b      	beq.n	8004aac <HAL_GPIO_Init+0x1b4>
 80049d4:	f505 6580 	add.w	r5, r5, #1024	; 0x400
 80049d8:	42a8      	cmp	r0, r5
 80049da:	d069      	beq.n	8004ab0 <HAL_GPIO_Init+0x1b8>
 80049dc:	4570      	cmp	r0, lr
 80049de:	bf0c      	ite	eq
 80049e0:	2505      	moveq	r5, #5
 80049e2:	2506      	movne	r5, #6
 80049e4:	fa05 f50b 	lsl.w	r5, r5, fp
 80049e8:	ea45 0509 	orr.w	r5, r5, r9
        AFIO->EXTICR[position >> 2U] = temp;
 80049ec:	f8c8 5008 	str.w	r5, [r8, #8]


        /* Configure the interrupt mask */
        if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
        {
          SET_BIT(EXTI->IMR, iocurrent);
 80049f0:	681d      	ldr	r5, [r3, #0]
        if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
 80049f2:	f41a 3f80 	tst.w	sl, #65536	; 0x10000
          SET_BIT(EXTI->IMR, iocurrent);
 80049f6:	bf14      	ite	ne
 80049f8:	4325      	orrne	r5, r4
        }
        else
        {
          CLEAR_BIT(EXTI->IMR, iocurrent);
 80049fa:	43a5      	biceq	r5, r4
 80049fc:	601d      	str	r5, [r3, #0]
        }

        /* Configure the event mask */
        if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
        {
          SET_BIT(EXTI->EMR, iocurrent);
 80049fe:	685d      	ldr	r5, [r3, #4]
        if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
 8004a00:	f41a 3f00 	tst.w	sl, #131072	; 0x20000
          SET_BIT(EXTI->EMR, iocurrent);
 8004a04:	bf14      	ite	ne
 8004a06:	4325      	orrne	r5, r4
        }
        else
        {
          CLEAR_BIT(EXTI->EMR, iocurrent);
 8004a08:	43a5      	biceq	r5, r4
 8004a0a:	605d      	str	r5, [r3, #4]
        }

        /* Enable or disable the rising trigger */
        if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
        {
          SET_BIT(EXTI->RTSR, iocurrent);
 8004a0c:	689d      	ldr	r5, [r3, #8]
        if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
 8004a0e:	f41a 1f80 	tst.w	sl, #1048576	; 0x100000
          SET_BIT(EXTI->RTSR, iocurrent);
 8004a12:	bf14      	ite	ne
 8004a14:	4325      	orrne	r5, r4
        }
        else
        {
          CLEAR_BIT(EXTI->RTSR, iocurrent);
 8004a16:	43a5      	biceq	r5, r4
 8004a18:	609d      	str	r5, [r3, #8]
        }

        /* Enable or disable the falling trigger */
        if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
        {
          SET_BIT(EXTI->FTSR, iocurrent);
 8004a1a:	68dd      	ldr	r5, [r3, #12]
        if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
 8004a1c:	f41a 1f00 	tst.w	sl, #2097152	; 0x200000
          SET_BIT(EXTI->FTSR, iocurrent);
 8004a20:	bf14      	ite	ne
 8004a22:	432c      	orrne	r4, r5
        }
        else
        {
          CLEAR_BIT(EXTI->FTSR, iocurrent);
 8004a24:	ea25 0404 	biceq.w	r4, r5, r4
 8004a28:	60dc      	str	r4, [r3, #12]
  for (position = 0U; position < GPIO_NUMBER; position++)
 8004a2a:	3601      	adds	r6, #1
 8004a2c:	2e10      	cmp	r6, #16
 8004a2e:	f47f af6d 	bne.w	800490c <HAL_GPIO_Init+0x14>
        }
      }
    }
  }
}
 8004a32:	b003      	add	sp, #12
 8004a34:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
      switch (GPIO_Init->Mode)
 8004a38:	2d03      	cmp	r5, #3
 8004a3a:	d025      	beq.n	8004a88 <HAL_GPIO_Init+0x190>
 8004a3c:	2d11      	cmp	r5, #17
 8004a3e:	d180      	bne.n	8004942 <HAL_GPIO_Init+0x4a>
          config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;
 8004a40:	68ca      	ldr	r2, [r1, #12]
 8004a42:	3204      	adds	r2, #4
          break;
 8004a44:	e77d      	b.n	8004942 <HAL_GPIO_Init+0x4a>
      switch (GPIO_Init->Mode)
 8004a46:	4565      	cmp	r5, ip
 8004a48:	d009      	beq.n	8004a5e <HAL_GPIO_Init+0x166>
 8004a4a:	d812      	bhi.n	8004a72 <HAL_GPIO_Init+0x17a>
 8004a4c:	f8df 9078 	ldr.w	r9, [pc, #120]	; 8004ac8 <HAL_GPIO_Init+0x1d0>
 8004a50:	454d      	cmp	r5, r9
 8004a52:	d004      	beq.n	8004a5e <HAL_GPIO_Init+0x166>
 8004a54:	f509 3980 	add.w	r9, r9, #65536	; 0x10000
 8004a58:	454d      	cmp	r5, r9
 8004a5a:	f47f af72 	bne.w	8004942 <HAL_GPIO_Init+0x4a>
          if (GPIO_Init->Pull == GPIO_NOPULL)
 8004a5e:	688a      	ldr	r2, [r1, #8]
 8004a60:	b1e2      	cbz	r2, 8004a9c <HAL_GPIO_Init+0x1a4>
          else if (GPIO_Init->Pull == GPIO_PULLUP)
 8004a62:	2a01      	cmp	r2, #1
            GPIOx->BSRR = ioposition;
 8004a64:	bf0c      	ite	eq
 8004a66:	f8c0 8010 	streq.w	r8, [r0, #16]
            GPIOx->BRR = ioposition;
 8004a6a:	f8c0 8014 	strne.w	r8, [r0, #20]
            config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
 8004a6e:	2208      	movs	r2, #8
 8004a70:	e767      	b.n	8004942 <HAL_GPIO_Init+0x4a>
      switch (GPIO_Init->Mode)
 8004a72:	f8df 9058 	ldr.w	r9, [pc, #88]	; 8004acc <HAL_GPIO_Init+0x1d4>
 8004a76:	454d      	cmp	r5, r9
 8004a78:	d0f1      	beq.n	8004a5e <HAL_GPIO_Init+0x166>
 8004a7a:	f509 3980 	add.w	r9, r9, #65536	; 0x10000
 8004a7e:	454d      	cmp	r5, r9
 8004a80:	d0ed      	beq.n	8004a5e <HAL_GPIO_Init+0x166>
 8004a82:	f5a9 1980 	sub.w	r9, r9, #1048576	; 0x100000
 8004a86:	e7e7      	b.n	8004a58 <HAL_GPIO_Init+0x160>
          config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
 8004a88:	2200      	movs	r2, #0
 8004a8a:	e75a      	b.n	8004942 <HAL_GPIO_Init+0x4a>
          config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;
 8004a8c:	68ca      	ldr	r2, [r1, #12]
          break;
 8004a8e:	e758      	b.n	8004942 <HAL_GPIO_Init+0x4a>
          config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;
 8004a90:	68ca      	ldr	r2, [r1, #12]
 8004a92:	3208      	adds	r2, #8
          break;
 8004a94:	e755      	b.n	8004942 <HAL_GPIO_Init+0x4a>
          config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;
 8004a96:	68ca      	ldr	r2, [r1, #12]
 8004a98:	320c      	adds	r2, #12
          break;
 8004a9a:	e752      	b.n	8004942 <HAL_GPIO_Init+0x4a>
            config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
 8004a9c:	2204      	movs	r2, #4
 8004a9e:	e750      	b.n	8004942 <HAL_GPIO_Init+0x4a>
        SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
 8004aa0:	2500      	movs	r5, #0
 8004aa2:	e79f      	b.n	80049e4 <HAL_GPIO_Init+0xec>
 8004aa4:	2501      	movs	r5, #1
 8004aa6:	e79d      	b.n	80049e4 <HAL_GPIO_Init+0xec>
 8004aa8:	2502      	movs	r5, #2
 8004aaa:	e79b      	b.n	80049e4 <HAL_GPIO_Init+0xec>
 8004aac:	2503      	movs	r5, #3
 8004aae:	e799      	b.n	80049e4 <HAL_GPIO_Init+0xec>
 8004ab0:	2504      	movs	r5, #4
 8004ab2:	e797      	b.n	80049e4 <HAL_GPIO_Init+0xec>
 8004ab4:	40021000 	.word	0x40021000
 8004ab8:	40010400 	.word	0x40010400
 8004abc:	40010800 	.word	0x40010800
 8004ac0:	40011c00 	.word	0x40011c00
 8004ac4:	10210000 	.word	0x10210000
 8004ac8:	10110000 	.word	0x10110000
 8004acc:	10310000 	.word	0x10310000

08004ad0 <HAL_GPIO_WritePin>:
{
  /* Check the parameters */
  assert_param(IS_GPIO_PIN(GPIO_Pin));
  assert_param(IS_GPIO_PIN_ACTION(PinState));

  if (PinState != GPIO_PIN_RESET)
 8004ad0:	b10a      	cbz	r2, 8004ad6 <HAL_GPIO_WritePin+0x6>
  {
    GPIOx->BSRR = GPIO_Pin;
  }
  else
  {
    GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
 8004ad2:	6101      	str	r1, [r0, #16]
 8004ad4:	4770      	bx	lr
 8004ad6:	0409      	lsls	r1, r1, #16
 8004ad8:	e7fb      	b.n	8004ad2 <HAL_GPIO_WritePin+0x2>

08004ada <HAL_GPIO_TogglePin>:
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
  /* Check the parameters */
  assert_param(IS_GPIO_PIN(GPIO_Pin));

  GPIOx->ODR ^= GPIO_Pin;
 8004ada:	68c3      	ldr	r3, [r0, #12]
 8004adc:	4059      	eors	r1, r3
 8004ade:	60c1      	str	r1, [r0, #12]
 8004ae0:	4770      	bx	lr
	...

08004ae4 <HAL_RCC_OscConfig>:
  /* Check the parameters */
  assert_param(RCC_OscInitStruct != NULL);
  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
  
  /*------------------------------- HSE Configuration ------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
 8004ae4:	6803      	ldr	r3, [r0, #0]
{
 8004ae6:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
 8004aea:	07db      	lsls	r3, r3, #31
{
 8004aec:	4605      	mov	r5, r0
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
 8004aee:	d410      	bmi.n	8004b12 <HAL_RCC_OscConfig+0x2e>
        }
      }
    }
  }
  /*----------------------------- HSI Configuration --------------------------*/ 
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
 8004af0:	682b      	ldr	r3, [r5, #0]
 8004af2:	079f      	lsls	r7, r3, #30
 8004af4:	d45e      	bmi.n	8004bb4 <HAL_RCC_OscConfig+0xd0>
        }
      }
    }
  }
  /*------------------------------ LSI Configuration -------------------------*/ 
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
 8004af6:	682b      	ldr	r3, [r5, #0]
 8004af8:	0719      	lsls	r1, r3, #28
 8004afa:	f100 8095 	bmi.w	8004c28 <HAL_RCC_OscConfig+0x144>
        }
      }
    }
  }
  /*------------------------------ LSE Configuration -------------------------*/ 
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
 8004afe:	682b      	ldr	r3, [r5, #0]
 8004b00:	075a      	lsls	r2, r3, #29
 8004b02:	f100 80bf 	bmi.w	8004c84 <HAL_RCC_OscConfig+0x1a0>

#endif /* RCC_CR_PLL2ON */
  /*-------------------------------- PLL Configuration -----------------------*/
  /* Check the parameters */
  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
 8004b06:	69ea      	ldr	r2, [r5, #28]
 8004b08:	2a00      	cmp	r2, #0
 8004b0a:	f040 812d 	bne.w	8004d68 <HAL_RCC_OscConfig+0x284>
    {
      return HAL_ERROR;
    }
  }
  
  return HAL_OK;
 8004b0e:	2000      	movs	r0, #0
 8004b10:	e014      	b.n	8004b3c <HAL_RCC_OscConfig+0x58>
    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 
 8004b12:	4c90      	ldr	r4, [pc, #576]	; (8004d54 <HAL_RCC_OscConfig+0x270>)
 8004b14:	6863      	ldr	r3, [r4, #4]
 8004b16:	f003 030c 	and.w	r3, r3, #12
 8004b1a:	2b04      	cmp	r3, #4
 8004b1c:	d007      	beq.n	8004b2e <HAL_RCC_OscConfig+0x4a>
       || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
 8004b1e:	6863      	ldr	r3, [r4, #4]
 8004b20:	f003 030c 	and.w	r3, r3, #12
 8004b24:	2b08      	cmp	r3, #8
 8004b26:	d10c      	bne.n	8004b42 <HAL_RCC_OscConfig+0x5e>
 8004b28:	6863      	ldr	r3, [r4, #4]
 8004b2a:	03de      	lsls	r6, r3, #15
 8004b2c:	d509      	bpl.n	8004b42 <HAL_RCC_OscConfig+0x5e>
      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
 8004b2e:	6823      	ldr	r3, [r4, #0]
 8004b30:	039c      	lsls	r4, r3, #14
 8004b32:	d5dd      	bpl.n	8004af0 <HAL_RCC_OscConfig+0xc>
 8004b34:	686b      	ldr	r3, [r5, #4]
 8004b36:	2b00      	cmp	r3, #0
 8004b38:	d1da      	bne.n	8004af0 <HAL_RCC_OscConfig+0xc>
        return HAL_ERROR;
 8004b3a:	2001      	movs	r0, #1
}
 8004b3c:	b002      	add	sp, #8
 8004b3e:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 8004b42:	686b      	ldr	r3, [r5, #4]
 8004b44:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
 8004b48:	d110      	bne.n	8004b6c <HAL_RCC_OscConfig+0x88>
 8004b4a:	6823      	ldr	r3, [r4, #0]
 8004b4c:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
 8004b50:	6023      	str	r3, [r4, #0]
        tickstart = HAL_GetTick();
 8004b52:	f7ff fba9 	bl	80042a8 <HAL_GetTick>
 8004b56:	4606      	mov	r6, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 8004b58:	6823      	ldr	r3, [r4, #0]
 8004b5a:	0398      	lsls	r0, r3, #14
 8004b5c:	d4c8      	bmi.n	8004af0 <HAL_RCC_OscConfig+0xc>
          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
 8004b5e:	f7ff fba3 	bl	80042a8 <HAL_GetTick>
 8004b62:	1b80      	subs	r0, r0, r6
 8004b64:	2864      	cmp	r0, #100	; 0x64
 8004b66:	d9f7      	bls.n	8004b58 <HAL_RCC_OscConfig+0x74>
            return HAL_TIMEOUT;
 8004b68:	2003      	movs	r0, #3
 8004b6a:	e7e7      	b.n	8004b3c <HAL_RCC_OscConfig+0x58>
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 8004b6c:	b99b      	cbnz	r3, 8004b96 <HAL_RCC_OscConfig+0xb2>
 8004b6e:	6823      	ldr	r3, [r4, #0]
 8004b70:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
 8004b74:	6023      	str	r3, [r4, #0]
 8004b76:	6823      	ldr	r3, [r4, #0]
 8004b78:	f423 2380 	bic.w	r3, r3, #262144	; 0x40000
 8004b7c:	6023      	str	r3, [r4, #0]
        tickstart = HAL_GetTick();
 8004b7e:	f7ff fb93 	bl	80042a8 <HAL_GetTick>
 8004b82:	4606      	mov	r6, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
 8004b84:	6823      	ldr	r3, [r4, #0]
 8004b86:	0399      	lsls	r1, r3, #14
 8004b88:	d5b2      	bpl.n	8004af0 <HAL_RCC_OscConfig+0xc>
           if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
 8004b8a:	f7ff fb8d 	bl	80042a8 <HAL_GetTick>
 8004b8e:	1b80      	subs	r0, r0, r6
 8004b90:	2864      	cmp	r0, #100	; 0x64
 8004b92:	d9f7      	bls.n	8004b84 <HAL_RCC_OscConfig+0xa0>
 8004b94:	e7e8      	b.n	8004b68 <HAL_RCC_OscConfig+0x84>
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 8004b96:	f5b3 2fa0 	cmp.w	r3, #327680	; 0x50000
 8004b9a:	6823      	ldr	r3, [r4, #0]
 8004b9c:	d103      	bne.n	8004ba6 <HAL_RCC_OscConfig+0xc2>
 8004b9e:	f443 2380 	orr.w	r3, r3, #262144	; 0x40000
 8004ba2:	6023      	str	r3, [r4, #0]
 8004ba4:	e7d1      	b.n	8004b4a <HAL_RCC_OscConfig+0x66>
 8004ba6:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
 8004baa:	6023      	str	r3, [r4, #0]
 8004bac:	6823      	ldr	r3, [r4, #0]
 8004bae:	f423 2380 	bic.w	r3, r3, #262144	; 0x40000
 8004bb2:	e7cd      	b.n	8004b50 <HAL_RCC_OscConfig+0x6c>
    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 
 8004bb4:	4c67      	ldr	r4, [pc, #412]	; (8004d54 <HAL_RCC_OscConfig+0x270>)
 8004bb6:	6863      	ldr	r3, [r4, #4]
 8004bb8:	f013 0f0c 	tst.w	r3, #12
 8004bbc:	d007      	beq.n	8004bce <HAL_RCC_OscConfig+0xea>
       || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
 8004bbe:	6863      	ldr	r3, [r4, #4]
 8004bc0:	f003 030c 	and.w	r3, r3, #12
 8004bc4:	2b08      	cmp	r3, #8
 8004bc6:	d110      	bne.n	8004bea <HAL_RCC_OscConfig+0x106>
 8004bc8:	6863      	ldr	r3, [r4, #4]
 8004bca:	03da      	lsls	r2, r3, #15
 8004bcc:	d40d      	bmi.n	8004bea <HAL_RCC_OscConfig+0x106>
      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
 8004bce:	6823      	ldr	r3, [r4, #0]
 8004bd0:	079b      	lsls	r3, r3, #30
 8004bd2:	d502      	bpl.n	8004bda <HAL_RCC_OscConfig+0xf6>
 8004bd4:	692b      	ldr	r3, [r5, #16]
 8004bd6:	2b01      	cmp	r3, #1
 8004bd8:	d1af      	bne.n	8004b3a <HAL_RCC_OscConfig+0x56>
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 8004bda:	6823      	ldr	r3, [r4, #0]
 8004bdc:	696a      	ldr	r2, [r5, #20]
 8004bde:	f023 03f8 	bic.w	r3, r3, #248	; 0xf8
 8004be2:	ea43 03c2 	orr.w	r3, r3, r2, lsl #3
 8004be6:	6023      	str	r3, [r4, #0]
 8004be8:	e785      	b.n	8004af6 <HAL_RCC_OscConfig+0x12>
      if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
 8004bea:	692a      	ldr	r2, [r5, #16]
 8004bec:	4b5a      	ldr	r3, [pc, #360]	; (8004d58 <HAL_RCC_OscConfig+0x274>)
 8004bee:	b16a      	cbz	r2, 8004c0c <HAL_RCC_OscConfig+0x128>
        __HAL_RCC_HSI_ENABLE();
 8004bf0:	2201      	movs	r2, #1
 8004bf2:	601a      	str	r2, [r3, #0]
        tickstart = HAL_GetTick();
 8004bf4:	f7ff fb58 	bl	80042a8 <HAL_GetTick>
 8004bf8:	4606      	mov	r6, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 8004bfa:	6823      	ldr	r3, [r4, #0]
 8004bfc:	079f      	lsls	r7, r3, #30
 8004bfe:	d4ec      	bmi.n	8004bda <HAL_RCC_OscConfig+0xf6>
          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
 8004c00:	f7ff fb52 	bl	80042a8 <HAL_GetTick>
 8004c04:	1b80      	subs	r0, r0, r6
 8004c06:	2802      	cmp	r0, #2
 8004c08:	d9f7      	bls.n	8004bfa <HAL_RCC_OscConfig+0x116>
 8004c0a:	e7ad      	b.n	8004b68 <HAL_RCC_OscConfig+0x84>
        __HAL_RCC_HSI_DISABLE();
 8004c0c:	601a      	str	r2, [r3, #0]
        tickstart = HAL_GetTick();
 8004c0e:	f7ff fb4b 	bl	80042a8 <HAL_GetTick>
 8004c12:	4606      	mov	r6, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
 8004c14:	6823      	ldr	r3, [r4, #0]
 8004c16:	0798      	lsls	r0, r3, #30
 8004c18:	f57f af6d 	bpl.w	8004af6 <HAL_RCC_OscConfig+0x12>
          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
 8004c1c:	f7ff fb44 	bl	80042a8 <HAL_GetTick>
 8004c20:	1b80      	subs	r0, r0, r6
 8004c22:	2802      	cmp	r0, #2
 8004c24:	d9f6      	bls.n	8004c14 <HAL_RCC_OscConfig+0x130>
 8004c26:	e79f      	b.n	8004b68 <HAL_RCC_OscConfig+0x84>
    if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
 8004c28:	69aa      	ldr	r2, [r5, #24]
 8004c2a:	4c4a      	ldr	r4, [pc, #296]	; (8004d54 <HAL_RCC_OscConfig+0x270>)
 8004c2c:	4b4b      	ldr	r3, [pc, #300]	; (8004d5c <HAL_RCC_OscConfig+0x278>)
 8004c2e:	b1da      	cbz	r2, 8004c68 <HAL_RCC_OscConfig+0x184>
      __HAL_RCC_LSI_ENABLE();
 8004c30:	2201      	movs	r2, #1
 8004c32:	601a      	str	r2, [r3, #0]
      tickstart = HAL_GetTick();
 8004c34:	f7ff fb38 	bl	80042a8 <HAL_GetTick>
 8004c38:	4606      	mov	r6, r0
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
 8004c3a:	6a63      	ldr	r3, [r4, #36]	; 0x24
 8004c3c:	079b      	lsls	r3, r3, #30
 8004c3e:	d50d      	bpl.n	8004c5c <HAL_RCC_OscConfig+0x178>
  * @param  mdelay: specifies the delay time length, in milliseconds.
  * @retval None
  */
static void RCC_Delay(uint32_t mdelay)
{
  __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
 8004c40:	f44f 52fa 	mov.w	r2, #8000	; 0x1f40
 8004c44:	4b46      	ldr	r3, [pc, #280]	; (8004d60 <HAL_RCC_OscConfig+0x27c>)
 8004c46:	681b      	ldr	r3, [r3, #0]
 8004c48:	fbb3 f3f2 	udiv	r3, r3, r2
 8004c4c:	9301      	str	r3, [sp, #4]
  \brief   No Operation
  \details No Operation does nothing. This instruction can be used for code alignment purposes.
 */
__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
{
  __ASM volatile ("nop");
 8004c4e:	bf00      	nop
  do 
  {
    __NOP();
  } 
  while (Delay --);
 8004c50:	9b01      	ldr	r3, [sp, #4]
 8004c52:	1e5a      	subs	r2, r3, #1
 8004c54:	9201      	str	r2, [sp, #4]
 8004c56:	2b00      	cmp	r3, #0
 8004c58:	d1f9      	bne.n	8004c4e <HAL_RCC_OscConfig+0x16a>
 8004c5a:	e750      	b.n	8004afe <HAL_RCC_OscConfig+0x1a>
        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
 8004c5c:	f7ff fb24 	bl	80042a8 <HAL_GetTick>
 8004c60:	1b80      	subs	r0, r0, r6
 8004c62:	2802      	cmp	r0, #2
 8004c64:	d9e9      	bls.n	8004c3a <HAL_RCC_OscConfig+0x156>
 8004c66:	e77f      	b.n	8004b68 <HAL_RCC_OscConfig+0x84>
      __HAL_RCC_LSI_DISABLE();
 8004c68:	601a      	str	r2, [r3, #0]
      tickstart = HAL_GetTick();
 8004c6a:	f7ff fb1d 	bl	80042a8 <HAL_GetTick>
 8004c6e:	4606      	mov	r6, r0
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
 8004c70:	6a63      	ldr	r3, [r4, #36]	; 0x24
 8004c72:	079f      	lsls	r7, r3, #30
 8004c74:	f57f af43 	bpl.w	8004afe <HAL_RCC_OscConfig+0x1a>
        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
 8004c78:	f7ff fb16 	bl	80042a8 <HAL_GetTick>
 8004c7c:	1b80      	subs	r0, r0, r6
 8004c7e:	2802      	cmp	r0, #2
 8004c80:	d9f6      	bls.n	8004c70 <HAL_RCC_OscConfig+0x18c>
 8004c82:	e771      	b.n	8004b68 <HAL_RCC_OscConfig+0x84>
    if(__HAL_RCC_PWR_IS_CLK_DISABLED())
 8004c84:	4c33      	ldr	r4, [pc, #204]	; (8004d54 <HAL_RCC_OscConfig+0x270>)
 8004c86:	69e3      	ldr	r3, [r4, #28]
 8004c88:	00d8      	lsls	r0, r3, #3
 8004c8a:	d424      	bmi.n	8004cd6 <HAL_RCC_OscConfig+0x1f2>
      pwrclkchanged = SET;
 8004c8c:	2701      	movs	r7, #1
      __HAL_RCC_PWR_CLK_ENABLE();
 8004c8e:	69e3      	ldr	r3, [r4, #28]
 8004c90:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
 8004c94:	61e3      	str	r3, [r4, #28]
 8004c96:	69e3      	ldr	r3, [r4, #28]
 8004c98:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8004c9c:	9300      	str	r3, [sp, #0]
 8004c9e:	9b00      	ldr	r3, [sp, #0]
    if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 8004ca0:	4e30      	ldr	r6, [pc, #192]	; (8004d64 <HAL_RCC_OscConfig+0x280>)
 8004ca2:	6833      	ldr	r3, [r6, #0]
 8004ca4:	05d9      	lsls	r1, r3, #23
 8004ca6:	d518      	bpl.n	8004cda <HAL_RCC_OscConfig+0x1f6>
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 8004ca8:	68eb      	ldr	r3, [r5, #12]
 8004caa:	2b01      	cmp	r3, #1
 8004cac:	d126      	bne.n	8004cfc <HAL_RCC_OscConfig+0x218>
 8004cae:	6a23      	ldr	r3, [r4, #32]
 8004cb0:	f043 0301 	orr.w	r3, r3, #1
 8004cb4:	6223      	str	r3, [r4, #32]
      tickstart = HAL_GetTick();
 8004cb6:	f7ff faf7 	bl	80042a8 <HAL_GetTick>
        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
 8004cba:	f241 3688 	movw	r6, #5000	; 0x1388
      tickstart = HAL_GetTick();
 8004cbe:	4680      	mov	r8, r0
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
 8004cc0:	6a23      	ldr	r3, [r4, #32]
 8004cc2:	079b      	lsls	r3, r3, #30
 8004cc4:	d53f      	bpl.n	8004d46 <HAL_RCC_OscConfig+0x262>
    if(pwrclkchanged == SET)
 8004cc6:	2f00      	cmp	r7, #0
 8004cc8:	f43f af1d 	beq.w	8004b06 <HAL_RCC_OscConfig+0x22>
      __HAL_RCC_PWR_CLK_DISABLE();
 8004ccc:	69e3      	ldr	r3, [r4, #28]
 8004cce:	f023 5380 	bic.w	r3, r3, #268435456	; 0x10000000
 8004cd2:	61e3      	str	r3, [r4, #28]
 8004cd4:	e717      	b.n	8004b06 <HAL_RCC_OscConfig+0x22>
    FlagStatus       pwrclkchanged = RESET;
 8004cd6:	2700      	movs	r7, #0
 8004cd8:	e7e2      	b.n	8004ca0 <HAL_RCC_OscConfig+0x1bc>
      SET_BIT(PWR->CR, PWR_CR_DBP);
 8004cda:	6833      	ldr	r3, [r6, #0]
 8004cdc:	f443 7380 	orr.w	r3, r3, #256	; 0x100
 8004ce0:	6033      	str	r3, [r6, #0]
      tickstart = HAL_GetTick();
 8004ce2:	f7ff fae1 	bl	80042a8 <HAL_GetTick>
 8004ce6:	4680      	mov	r8, r0
      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 8004ce8:	6833      	ldr	r3, [r6, #0]
 8004cea:	05da      	lsls	r2, r3, #23
 8004cec:	d4dc      	bmi.n	8004ca8 <HAL_RCC_OscConfig+0x1c4>
        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
 8004cee:	f7ff fadb 	bl	80042a8 <HAL_GetTick>
 8004cf2:	eba0 0008 	sub.w	r0, r0, r8
 8004cf6:	2864      	cmp	r0, #100	; 0x64
 8004cf8:	d9f6      	bls.n	8004ce8 <HAL_RCC_OscConfig+0x204>
 8004cfa:	e735      	b.n	8004b68 <HAL_RCC_OscConfig+0x84>
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 8004cfc:	b9ab      	cbnz	r3, 8004d2a <HAL_RCC_OscConfig+0x246>
 8004cfe:	6a23      	ldr	r3, [r4, #32]
        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
 8004d00:	f241 3888 	movw	r8, #5000	; 0x1388
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 8004d04:	f023 0301 	bic.w	r3, r3, #1
 8004d08:	6223      	str	r3, [r4, #32]
 8004d0a:	6a23      	ldr	r3, [r4, #32]
 8004d0c:	f023 0304 	bic.w	r3, r3, #4
 8004d10:	6223      	str	r3, [r4, #32]
      tickstart = HAL_GetTick();
 8004d12:	f7ff fac9 	bl	80042a8 <HAL_GetTick>
 8004d16:	4606      	mov	r6, r0
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
 8004d18:	6a23      	ldr	r3, [r4, #32]
 8004d1a:	0798      	lsls	r0, r3, #30
 8004d1c:	d5d3      	bpl.n	8004cc6 <HAL_RCC_OscConfig+0x1e2>
        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
 8004d1e:	f7ff fac3 	bl	80042a8 <HAL_GetTick>
 8004d22:	1b80      	subs	r0, r0, r6
 8004d24:	4540      	cmp	r0, r8
 8004d26:	d9f7      	bls.n	8004d18 <HAL_RCC_OscConfig+0x234>
 8004d28:	e71e      	b.n	8004b68 <HAL_RCC_OscConfig+0x84>
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 8004d2a:	2b05      	cmp	r3, #5
 8004d2c:	6a23      	ldr	r3, [r4, #32]
 8004d2e:	d103      	bne.n	8004d38 <HAL_RCC_OscConfig+0x254>
 8004d30:	f043 0304 	orr.w	r3, r3, #4
 8004d34:	6223      	str	r3, [r4, #32]
 8004d36:	e7ba      	b.n	8004cae <HAL_RCC_OscConfig+0x1ca>
 8004d38:	f023 0301 	bic.w	r3, r3, #1
 8004d3c:	6223      	str	r3, [r4, #32]
 8004d3e:	6a23      	ldr	r3, [r4, #32]
 8004d40:	f023 0304 	bic.w	r3, r3, #4
 8004d44:	e7b6      	b.n	8004cb4 <HAL_RCC_OscConfig+0x1d0>
        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
 8004d46:	f7ff faaf 	bl	80042a8 <HAL_GetTick>
 8004d4a:	eba0 0008 	sub.w	r0, r0, r8
 8004d4e:	42b0      	cmp	r0, r6
 8004d50:	d9b6      	bls.n	8004cc0 <HAL_RCC_OscConfig+0x1dc>
 8004d52:	e709      	b.n	8004b68 <HAL_RCC_OscConfig+0x84>
 8004d54:	40021000 	.word	0x40021000
 8004d58:	42420000 	.word	0x42420000
 8004d5c:	42420480 	.word	0x42420480
 8004d60:	20000008 	.word	0x20000008
 8004d64:	40007000 	.word	0x40007000
    if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
 8004d68:	4c22      	ldr	r4, [pc, #136]	; (8004df4 <HAL_RCC_OscConfig+0x310>)
 8004d6a:	6863      	ldr	r3, [r4, #4]
 8004d6c:	f003 030c 	and.w	r3, r3, #12
 8004d70:	2b08      	cmp	r3, #8
 8004d72:	f43f aee2 	beq.w	8004b3a <HAL_RCC_OscConfig+0x56>
 8004d76:	2300      	movs	r3, #0
 8004d78:	4e1f      	ldr	r6, [pc, #124]	; (8004df8 <HAL_RCC_OscConfig+0x314>)
      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
 8004d7a:	2a02      	cmp	r2, #2
        __HAL_RCC_PLL_DISABLE();
 8004d7c:	6033      	str	r3, [r6, #0]
      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
 8004d7e:	d12b      	bne.n	8004dd8 <HAL_RCC_OscConfig+0x2f4>
        tickstart = HAL_GetTick();
 8004d80:	f7ff fa92 	bl	80042a8 <HAL_GetTick>
 8004d84:	4607      	mov	r7, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
 8004d86:	6823      	ldr	r3, [r4, #0]
 8004d88:	0199      	lsls	r1, r3, #6
 8004d8a:	d41f      	bmi.n	8004dcc <HAL_RCC_OscConfig+0x2e8>
        if(RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
 8004d8c:	6a2b      	ldr	r3, [r5, #32]
 8004d8e:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
 8004d92:	d105      	bne.n	8004da0 <HAL_RCC_OscConfig+0x2bc>
          __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
 8004d94:	6862      	ldr	r2, [r4, #4]
 8004d96:	68a9      	ldr	r1, [r5, #8]
 8004d98:	f422 3200 	bic.w	r2, r2, #131072	; 0x20000
 8004d9c:	430a      	orrs	r2, r1
 8004d9e:	6062      	str	r2, [r4, #4]
        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
 8004da0:	6a69      	ldr	r1, [r5, #36]	; 0x24
 8004da2:	6862      	ldr	r2, [r4, #4]
 8004da4:	430b      	orrs	r3, r1
 8004da6:	f422 1274 	bic.w	r2, r2, #3997696	; 0x3d0000
 8004daa:	4313      	orrs	r3, r2
 8004dac:	6063      	str	r3, [r4, #4]
        __HAL_RCC_PLL_ENABLE();
 8004dae:	2301      	movs	r3, #1
 8004db0:	6033      	str	r3, [r6, #0]
        tickstart = HAL_GetTick();
 8004db2:	f7ff fa79 	bl	80042a8 <HAL_GetTick>
 8004db6:	4605      	mov	r5, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  == RESET)
 8004db8:	6823      	ldr	r3, [r4, #0]
 8004dba:	019a      	lsls	r2, r3, #6
 8004dbc:	f53f aea7 	bmi.w	8004b0e <HAL_RCC_OscConfig+0x2a>
          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
 8004dc0:	f7ff fa72 	bl	80042a8 <HAL_GetTick>
 8004dc4:	1b40      	subs	r0, r0, r5
 8004dc6:	2802      	cmp	r0, #2
 8004dc8:	d9f6      	bls.n	8004db8 <HAL_RCC_OscConfig+0x2d4>
 8004dca:	e6cd      	b.n	8004b68 <HAL_RCC_OscConfig+0x84>
          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
 8004dcc:	f7ff fa6c 	bl	80042a8 <HAL_GetTick>
 8004dd0:	1bc0      	subs	r0, r0, r7
 8004dd2:	2802      	cmp	r0, #2
 8004dd4:	d9d7      	bls.n	8004d86 <HAL_RCC_OscConfig+0x2a2>
 8004dd6:	e6c7      	b.n	8004b68 <HAL_RCC_OscConfig+0x84>
        tickstart = HAL_GetTick();
 8004dd8:	f7ff fa66 	bl	80042a8 <HAL_GetTick>
 8004ddc:	4605      	mov	r5, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
 8004dde:	6823      	ldr	r3, [r4, #0]
 8004de0:	019b      	lsls	r3, r3, #6
 8004de2:	f57f ae94 	bpl.w	8004b0e <HAL_RCC_OscConfig+0x2a>
          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
 8004de6:	f7ff fa5f 	bl	80042a8 <HAL_GetTick>
 8004dea:	1b40      	subs	r0, r0, r5
 8004dec:	2802      	cmp	r0, #2
 8004dee:	d9f6      	bls.n	8004dde <HAL_RCC_OscConfig+0x2fa>
 8004df0:	e6ba      	b.n	8004b68 <HAL_RCC_OscConfig+0x84>
 8004df2:	bf00      	nop
 8004df4:	40021000 	.word	0x40021000
 8004df8:	42420060 	.word	0x42420060

08004dfc <HAL_RCC_GetSysClockFreq>:
{
 8004dfc:	b530      	push	{r4, r5, lr}
  const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
 8004dfe:	4b19      	ldr	r3, [pc, #100]	; (8004e64 <HAL_RCC_GetSysClockFreq+0x68>)
{
 8004e00:	b087      	sub	sp, #28
  const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
 8004e02:	ac02      	add	r4, sp, #8
 8004e04:	f103 0510 	add.w	r5, r3, #16
 8004e08:	4622      	mov	r2, r4
 8004e0a:	6818      	ldr	r0, [r3, #0]
 8004e0c:	6859      	ldr	r1, [r3, #4]
 8004e0e:	3308      	adds	r3, #8
 8004e10:	c203      	stmia	r2!, {r0, r1}
 8004e12:	42ab      	cmp	r3, r5
 8004e14:	4614      	mov	r4, r2
 8004e16:	d1f7      	bne.n	8004e08 <HAL_RCC_GetSysClockFreq+0xc>
  const uint8_t aPredivFactorTable[2] = {1, 2};
 8004e18:	2301      	movs	r3, #1
 8004e1a:	f88d 3004 	strb.w	r3, [sp, #4]
 8004e1e:	2302      	movs	r3, #2
  tmpreg = RCC->CFGR;
 8004e20:	4911      	ldr	r1, [pc, #68]	; (8004e68 <HAL_RCC_GetSysClockFreq+0x6c>)
  const uint8_t aPredivFactorTable[2] = {1, 2};
 8004e22:	f88d 3005 	strb.w	r3, [sp, #5]
  tmpreg = RCC->CFGR;
 8004e26:	684b      	ldr	r3, [r1, #4]
  switch (tmpreg & RCC_CFGR_SWS)
 8004e28:	f003 020c 	and.w	r2, r3, #12
 8004e2c:	2a08      	cmp	r2, #8
 8004e2e:	d117      	bne.n	8004e60 <HAL_RCC_GetSysClockFreq+0x64>
      pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
 8004e30:	f3c3 4283 	ubfx	r2, r3, #18, #4
 8004e34:	a806      	add	r0, sp, #24
 8004e36:	4402      	add	r2, r0
      if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
 8004e38:	03db      	lsls	r3, r3, #15
      pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
 8004e3a:	f812 2c10 	ldrb.w	r2, [r2, #-16]
      if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
 8004e3e:	d50c      	bpl.n	8004e5a <HAL_RCC_GetSysClockFreq+0x5e>
        prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
 8004e40:	684b      	ldr	r3, [r1, #4]
        pllclk = (uint32_t)((HSE_VALUE  * pllmul) / prediv);
 8004e42:	480a      	ldr	r0, [pc, #40]	; (8004e6c <HAL_RCC_GetSysClockFreq+0x70>)
        prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
 8004e44:	f3c3 4340 	ubfx	r3, r3, #17, #1
        pllclk = (uint32_t)((HSE_VALUE  * pllmul) / prediv);
 8004e48:	4350      	muls	r0, r2
        prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
 8004e4a:	aa06      	add	r2, sp, #24
 8004e4c:	4413      	add	r3, r2
 8004e4e:	f813 3c14 	ldrb.w	r3, [r3, #-20]
        pllclk = (uint32_t)((HSE_VALUE  * pllmul) / prediv);
 8004e52:	fbb0 f0f3 	udiv	r0, r0, r3
}
 8004e56:	b007      	add	sp, #28
 8004e58:	bd30      	pop	{r4, r5, pc}
        pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
 8004e5a:	4805      	ldr	r0, [pc, #20]	; (8004e70 <HAL_RCC_GetSysClockFreq+0x74>)
 8004e5c:	4350      	muls	r0, r2
 8004e5e:	e7fa      	b.n	8004e56 <HAL_RCC_GetSysClockFreq+0x5a>
      sysclockfreq = HSE_VALUE;
 8004e60:	4802      	ldr	r0, [pc, #8]	; (8004e6c <HAL_RCC_GetSysClockFreq+0x70>)
  return sysclockfreq;
 8004e62:	e7f8      	b.n	8004e56 <HAL_RCC_GetSysClockFreq+0x5a>
 8004e64:	080069f8 	.word	0x080069f8
 8004e68:	40021000 	.word	0x40021000
 8004e6c:	007a1200 	.word	0x007a1200
 8004e70:	003d0900 	.word	0x003d0900

08004e74 <HAL_RCC_ClockConfig>:
  if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
 8004e74:	4a54      	ldr	r2, [pc, #336]	; (8004fc8 <HAL_RCC_ClockConfig+0x154>)
{
 8004e76:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
  if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
 8004e7a:	6813      	ldr	r3, [r2, #0]
{
 8004e7c:	4605      	mov	r5, r0
  if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
 8004e7e:	f003 0307 	and.w	r3, r3, #7
 8004e82:	428b      	cmp	r3, r1
{
 8004e84:	460e      	mov	r6, r1
  if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
 8004e86:	d32a      	bcc.n	8004ede <HAL_RCC_ClockConfig+0x6a>
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
 8004e88:	6829      	ldr	r1, [r5, #0]
 8004e8a:	078c      	lsls	r4, r1, #30
 8004e8c:	d434      	bmi.n	8004ef8 <HAL_RCC_ClockConfig+0x84>
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
 8004e8e:	07ca      	lsls	r2, r1, #31
 8004e90:	d447      	bmi.n	8004f22 <HAL_RCC_ClockConfig+0xae>
  if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
 8004e92:	4a4d      	ldr	r2, [pc, #308]	; (8004fc8 <HAL_RCC_ClockConfig+0x154>)
 8004e94:	6813      	ldr	r3, [r2, #0]
 8004e96:	f003 0307 	and.w	r3, r3, #7
 8004e9a:	429e      	cmp	r6, r3
 8004e9c:	f0c0 8082 	bcc.w	8004fa4 <HAL_RCC_ClockConfig+0x130>
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 8004ea0:	682a      	ldr	r2, [r5, #0]
 8004ea2:	4c4a      	ldr	r4, [pc, #296]	; (8004fcc <HAL_RCC_ClockConfig+0x158>)
 8004ea4:	f012 0f04 	tst.w	r2, #4
 8004ea8:	f040 8087 	bne.w	8004fba <HAL_RCC_ClockConfig+0x146>
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
 8004eac:	0713      	lsls	r3, r2, #28
 8004eae:	d506      	bpl.n	8004ebe <HAL_RCC_ClockConfig+0x4a>
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
 8004eb0:	6863      	ldr	r3, [r4, #4]
 8004eb2:	692a      	ldr	r2, [r5, #16]
 8004eb4:	f423 5360 	bic.w	r3, r3, #14336	; 0x3800
 8004eb8:	ea43 03c2 	orr.w	r3, r3, r2, lsl #3
 8004ebc:	6063      	str	r3, [r4, #4]
  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
 8004ebe:	f7ff ff9d 	bl	8004dfc <HAL_RCC_GetSysClockFreq>
 8004ec2:	6863      	ldr	r3, [r4, #4]
 8004ec4:	4a42      	ldr	r2, [pc, #264]	; (8004fd0 <HAL_RCC_ClockConfig+0x15c>)
 8004ec6:	f3c3 1303 	ubfx	r3, r3, #4, #4
 8004eca:	5cd3      	ldrb	r3, [r2, r3]
 8004ecc:	40d8      	lsrs	r0, r3
 8004ece:	4b41      	ldr	r3, [pc, #260]	; (8004fd4 <HAL_RCC_ClockConfig+0x160>)
 8004ed0:	6018      	str	r0, [r3, #0]
  HAL_InitTick (TICK_INT_PRIORITY);
 8004ed2:	2000      	movs	r0, #0
 8004ed4:	f7ff f9a6 	bl	8004224 <HAL_InitTick>
  return HAL_OK;
 8004ed8:	2000      	movs	r0, #0
}
 8004eda:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    __HAL_FLASH_SET_LATENCY(FLatency);
 8004ede:	6813      	ldr	r3, [r2, #0]
 8004ee0:	f023 0307 	bic.w	r3, r3, #7
 8004ee4:	430b      	orrs	r3, r1
 8004ee6:	6013      	str	r3, [r2, #0]
    if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
 8004ee8:	6813      	ldr	r3, [r2, #0]
 8004eea:	f003 0307 	and.w	r3, r3, #7
 8004eee:	4299      	cmp	r1, r3
 8004ef0:	d0ca      	beq.n	8004e88 <HAL_RCC_ClockConfig+0x14>
      return HAL_ERROR;
 8004ef2:	2001      	movs	r0, #1
 8004ef4:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
 8004ef8:	4b34      	ldr	r3, [pc, #208]	; (8004fcc <HAL_RCC_ClockConfig+0x158>)
    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 8004efa:	f011 0f04 	tst.w	r1, #4
      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
 8004efe:	bf1e      	ittt	ne
 8004f00:	685a      	ldrne	r2, [r3, #4]
 8004f02:	f442 62e0 	orrne.w	r2, r2, #1792	; 0x700
 8004f06:	605a      	strne	r2, [r3, #4]
    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
 8004f08:	0708      	lsls	r0, r1, #28
      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
 8004f0a:	bf42      	ittt	mi
 8004f0c:	685a      	ldrmi	r2, [r3, #4]
 8004f0e:	f442 5260 	orrmi.w	r2, r2, #14336	; 0x3800
 8004f12:	605a      	strmi	r2, [r3, #4]
    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
 8004f14:	685a      	ldr	r2, [r3, #4]
 8004f16:	68a8      	ldr	r0, [r5, #8]
 8004f18:	f022 02f0 	bic.w	r2, r2, #240	; 0xf0
 8004f1c:	4302      	orrs	r2, r0
 8004f1e:	605a      	str	r2, [r3, #4]
 8004f20:	e7b5      	b.n	8004e8e <HAL_RCC_ClockConfig+0x1a>
    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 8004f22:	686a      	ldr	r2, [r5, #4]
 8004f24:	4c29      	ldr	r4, [pc, #164]	; (8004fcc <HAL_RCC_ClockConfig+0x158>)
 8004f26:	2a01      	cmp	r2, #1
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 8004f28:	6823      	ldr	r3, [r4, #0]
    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 8004f2a:	d11c      	bne.n	8004f66 <HAL_RCC_ClockConfig+0xf2>
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 8004f2c:	f413 3f00 	tst.w	r3, #131072	; 0x20000
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 8004f30:	d0df      	beq.n	8004ef2 <HAL_RCC_ClockConfig+0x7e>
    __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
 8004f32:	6863      	ldr	r3, [r4, #4]
        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
 8004f34:	f241 3888 	movw	r8, #5000	; 0x1388
    __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
 8004f38:	f023 0303 	bic.w	r3, r3, #3
 8004f3c:	4313      	orrs	r3, r2
 8004f3e:	6063      	str	r3, [r4, #4]
    tickstart = HAL_GetTick();
 8004f40:	f7ff f9b2 	bl	80042a8 <HAL_GetTick>
    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 8004f44:	686b      	ldr	r3, [r5, #4]
    tickstart = HAL_GetTick();
 8004f46:	4607      	mov	r7, r0
    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 8004f48:	2b01      	cmp	r3, #1
 8004f4a:	d114      	bne.n	8004f76 <HAL_RCC_ClockConfig+0x102>
      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
 8004f4c:	6863      	ldr	r3, [r4, #4]
 8004f4e:	f003 030c 	and.w	r3, r3, #12
 8004f52:	2b04      	cmp	r3, #4
 8004f54:	d09d      	beq.n	8004e92 <HAL_RCC_ClockConfig+0x1e>
        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
 8004f56:	f7ff f9a7 	bl	80042a8 <HAL_GetTick>
 8004f5a:	1bc0      	subs	r0, r0, r7
 8004f5c:	4540      	cmp	r0, r8
 8004f5e:	d9f5      	bls.n	8004f4c <HAL_RCC_ClockConfig+0xd8>
          return HAL_TIMEOUT;
 8004f60:	2003      	movs	r0, #3
 8004f62:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
 8004f66:	2a02      	cmp	r2, #2
 8004f68:	d102      	bne.n	8004f70 <HAL_RCC_ClockConfig+0xfc>
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
 8004f6a:	f013 7f00 	tst.w	r3, #33554432	; 0x2000000
 8004f6e:	e7df      	b.n	8004f30 <HAL_RCC_ClockConfig+0xbc>
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 8004f70:	f013 0f02 	tst.w	r3, #2
 8004f74:	e7dc      	b.n	8004f30 <HAL_RCC_ClockConfig+0xbc>
    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
 8004f76:	2b02      	cmp	r3, #2
 8004f78:	d10f      	bne.n	8004f9a <HAL_RCC_ClockConfig+0x126>
      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
 8004f7a:	6863      	ldr	r3, [r4, #4]
 8004f7c:	f003 030c 	and.w	r3, r3, #12
 8004f80:	2b08      	cmp	r3, #8
 8004f82:	d086      	beq.n	8004e92 <HAL_RCC_ClockConfig+0x1e>
        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
 8004f84:	f7ff f990 	bl	80042a8 <HAL_GetTick>
 8004f88:	1bc0      	subs	r0, r0, r7
 8004f8a:	4540      	cmp	r0, r8
 8004f8c:	d9f5      	bls.n	8004f7a <HAL_RCC_ClockConfig+0x106>
 8004f8e:	e7e7      	b.n	8004f60 <HAL_RCC_ClockConfig+0xec>
        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
 8004f90:	f7ff f98a 	bl	80042a8 <HAL_GetTick>
 8004f94:	1bc0      	subs	r0, r0, r7
 8004f96:	4540      	cmp	r0, r8
 8004f98:	d8e2      	bhi.n	8004f60 <HAL_RCC_ClockConfig+0xec>
      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
 8004f9a:	6863      	ldr	r3, [r4, #4]
 8004f9c:	f013 0f0c 	tst.w	r3, #12
 8004fa0:	d1f6      	bne.n	8004f90 <HAL_RCC_ClockConfig+0x11c>
 8004fa2:	e776      	b.n	8004e92 <HAL_RCC_ClockConfig+0x1e>
    __HAL_FLASH_SET_LATENCY(FLatency);
 8004fa4:	6813      	ldr	r3, [r2, #0]
 8004fa6:	f023 0307 	bic.w	r3, r3, #7
 8004faa:	4333      	orrs	r3, r6
 8004fac:	6013      	str	r3, [r2, #0]
    if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
 8004fae:	6813      	ldr	r3, [r2, #0]
 8004fb0:	f003 0307 	and.w	r3, r3, #7
 8004fb4:	429e      	cmp	r6, r3
 8004fb6:	d19c      	bne.n	8004ef2 <HAL_RCC_ClockConfig+0x7e>
 8004fb8:	e772      	b.n	8004ea0 <HAL_RCC_ClockConfig+0x2c>
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
 8004fba:	6863      	ldr	r3, [r4, #4]
 8004fbc:	68e9      	ldr	r1, [r5, #12]
 8004fbe:	f423 63e0 	bic.w	r3, r3, #1792	; 0x700
 8004fc2:	430b      	orrs	r3, r1
 8004fc4:	6063      	str	r3, [r4, #4]
 8004fc6:	e771      	b.n	8004eac <HAL_RCC_ClockConfig+0x38>
 8004fc8:	40022000 	.word	0x40022000
 8004fcc:	40021000 	.word	0x40021000
 8004fd0:	08006a15 	.word	0x08006a15
 8004fd4:	20000008 	.word	0x20000008

08004fd8 <HAL_RCC_GetPCLK1Freq>:
  return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
 8004fd8:	4b04      	ldr	r3, [pc, #16]	; (8004fec <HAL_RCC_GetPCLK1Freq+0x14>)
 8004fda:	4a05      	ldr	r2, [pc, #20]	; (8004ff0 <HAL_RCC_GetPCLK1Freq+0x18>)
 8004fdc:	685b      	ldr	r3, [r3, #4]
 8004fde:	f3c3 2302 	ubfx	r3, r3, #8, #3
 8004fe2:	5cd3      	ldrb	r3, [r2, r3]
 8004fe4:	4a03      	ldr	r2, [pc, #12]	; (8004ff4 <HAL_RCC_GetPCLK1Freq+0x1c>)
 8004fe6:	6810      	ldr	r0, [r2, #0]
}    
 8004fe8:	40d8      	lsrs	r0, r3
 8004fea:	4770      	bx	lr
 8004fec:	40021000 	.word	0x40021000
 8004ff0:	08006a25 	.word	0x08006a25
 8004ff4:	20000008 	.word	0x20000008

08004ff8 <HAL_RCC_GetPCLK2Freq>:
  return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
 8004ff8:	4b04      	ldr	r3, [pc, #16]	; (800500c <HAL_RCC_GetPCLK2Freq+0x14>)
 8004ffa:	4a05      	ldr	r2, [pc, #20]	; (8005010 <HAL_RCC_GetPCLK2Freq+0x18>)
 8004ffc:	685b      	ldr	r3, [r3, #4]
 8004ffe:	f3c3 23c2 	ubfx	r3, r3, #11, #3
 8005002:	5cd3      	ldrb	r3, [r2, r3]
 8005004:	4a03      	ldr	r2, [pc, #12]	; (8005014 <HAL_RCC_GetPCLK2Freq+0x1c>)
 8005006:	6810      	ldr	r0, [r2, #0]
} 
 8005008:	40d8      	lsrs	r0, r3
 800500a:	4770      	bx	lr
 800500c:	40021000 	.word	0x40021000
 8005010:	08006a25 	.word	0x08006a25
 8005014:	20000008 	.word	0x20000008

08005018 <HAL_RCCEx_PeriphCLKConfig>:

  /* Check the parameters */
  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
  
  /*------------------------------- RTC/LCD Configuration ------------------------*/ 
  if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
 8005018:	6803      	ldr	r3, [r0, #0]
{
 800501a:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
  if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
 800501e:	07d9      	lsls	r1, r3, #31
{
 8005020:	4605      	mov	r5, r0
  if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
 8005022:	d520      	bpl.n	8005066 <HAL_RCCEx_PeriphCLKConfig+0x4e>
    FlagStatus       pwrclkchanged = RESET;

    /* As soon as function is called to change RTC clock source, activation of the 
       power domain is done. */
    /* Requires to enable write access to Backup Domain of necessary */
    if(__HAL_RCC_PWR_IS_CLK_DISABLED())
 8005024:	4c35      	ldr	r4, [pc, #212]	; (80050fc <HAL_RCCEx_PeriphCLKConfig+0xe4>)
 8005026:	69e3      	ldr	r3, [r4, #28]
 8005028:	00da      	lsls	r2, r3, #3
 800502a:	d432      	bmi.n	8005092 <HAL_RCCEx_PeriphCLKConfig+0x7a>
    {
    __HAL_RCC_PWR_CLK_ENABLE();
      pwrclkchanged = SET;
 800502c:	2701      	movs	r7, #1
    __HAL_RCC_PWR_CLK_ENABLE();
 800502e:	69e3      	ldr	r3, [r4, #28]
 8005030:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
 8005034:	61e3      	str	r3, [r4, #28]
 8005036:	69e3      	ldr	r3, [r4, #28]
 8005038:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 800503c:	9301      	str	r3, [sp, #4]
 800503e:	9b01      	ldr	r3, [sp, #4]
    }
    
    if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 8005040:	4e2f      	ldr	r6, [pc, #188]	; (8005100 <HAL_RCCEx_PeriphCLKConfig+0xe8>)
 8005042:	6833      	ldr	r3, [r6, #0]
 8005044:	05db      	lsls	r3, r3, #23
 8005046:	d526      	bpl.n	8005096 <HAL_RCCEx_PeriphCLKConfig+0x7e>
        }
      }
    }
      
    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ 
    temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
 8005048:	6a23      	ldr	r3, [r4, #32]
    if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
 800504a:	f413 7340 	ands.w	r3, r3, #768	; 0x300
 800504e:	d136      	bne.n	80050be <HAL_RCCEx_PeriphCLKConfig+0xa6>
            return HAL_TIMEOUT;
          }      
        }  
      }
    }
    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 
 8005050:	6a23      	ldr	r3, [r4, #32]
 8005052:	686a      	ldr	r2, [r5, #4]
 8005054:	f423 7340 	bic.w	r3, r3, #768	; 0x300
 8005058:	4313      	orrs	r3, r2
 800505a:	6223      	str	r3, [r4, #32]

    /* Require to disable power clock if necessary */
    if(pwrclkchanged == SET)
 800505c:	b11f      	cbz	r7, 8005066 <HAL_RCCEx_PeriphCLKConfig+0x4e>
    {
      __HAL_RCC_PWR_CLK_DISABLE();
 800505e:	69e3      	ldr	r3, [r4, #28]
 8005060:	f023 5380 	bic.w	r3, r3, #268435456	; 0x10000000
 8005064:	61e3      	str	r3, [r4, #28]
    }
  }

  /*------------------------------ ADC clock Configuration ------------------*/ 
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
 8005066:	6828      	ldr	r0, [r5, #0]
 8005068:	0783      	lsls	r3, r0, #30
 800506a:	d506      	bpl.n	800507a <HAL_RCCEx_PeriphCLKConfig+0x62>
  {
    /* Check the parameters */
    assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection));
    
    /* Configure the ADC clock source */
    __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
 800506c:	4a23      	ldr	r2, [pc, #140]	; (80050fc <HAL_RCCEx_PeriphCLKConfig+0xe4>)
 800506e:	68a9      	ldr	r1, [r5, #8]
 8005070:	6853      	ldr	r3, [r2, #4]
 8005072:	f423 4340 	bic.w	r3, r3, #49152	; 0xc000
 8005076:	430b      	orrs	r3, r1
 8005078:	6053      	str	r3, [r2, #4]

#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
 || defined(STM32F105xC) || defined(STM32F107xC)
  /*------------------------------ USB clock Configuration ------------------*/ 
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
 800507a:	f010 0010 	ands.w	r0, r0, #16
 800507e:	d01b      	beq.n	80050b8 <HAL_RCCEx_PeriphCLKConfig+0xa0>
  {
    /* Check the parameters */
    assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection));
    
    /* Configure the USB clock source */
    __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
 8005080:	4a1e      	ldr	r2, [pc, #120]	; (80050fc <HAL_RCCEx_PeriphCLKConfig+0xe4>)
 8005082:	6969      	ldr	r1, [r5, #20]
 8005084:	6853      	ldr	r3, [r2, #4]
  }
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */

  return HAL_OK;
 8005086:	2000      	movs	r0, #0
    __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
 8005088:	f423 0380 	bic.w	r3, r3, #4194304	; 0x400000
 800508c:	430b      	orrs	r3, r1
 800508e:	6053      	str	r3, [r2, #4]
 8005090:	e012      	b.n	80050b8 <HAL_RCCEx_PeriphCLKConfig+0xa0>
    FlagStatus       pwrclkchanged = RESET;
 8005092:	2700      	movs	r7, #0
 8005094:	e7d4      	b.n	8005040 <HAL_RCCEx_PeriphCLKConfig+0x28>
      SET_BIT(PWR->CR, PWR_CR_DBP);
 8005096:	6833      	ldr	r3, [r6, #0]
 8005098:	f443 7380 	orr.w	r3, r3, #256	; 0x100
 800509c:	6033      	str	r3, [r6, #0]
      tickstart = HAL_GetTick();
 800509e:	f7ff f903 	bl	80042a8 <HAL_GetTick>
 80050a2:	4680      	mov	r8, r0
      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 80050a4:	6833      	ldr	r3, [r6, #0]
 80050a6:	05d8      	lsls	r0, r3, #23
 80050a8:	d4ce      	bmi.n	8005048 <HAL_RCCEx_PeriphCLKConfig+0x30>
        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
 80050aa:	f7ff f8fd 	bl	80042a8 <HAL_GetTick>
 80050ae:	eba0 0008 	sub.w	r0, r0, r8
 80050b2:	2864      	cmp	r0, #100	; 0x64
 80050b4:	d9f6      	bls.n	80050a4 <HAL_RCCEx_PeriphCLKConfig+0x8c>
          return HAL_TIMEOUT;
 80050b6:	2003      	movs	r0, #3
}
 80050b8:	b002      	add	sp, #8
 80050ba:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
 80050be:	686a      	ldr	r2, [r5, #4]
 80050c0:	f402 7240 	and.w	r2, r2, #768	; 0x300
 80050c4:	4293      	cmp	r3, r2
 80050c6:	d0c3      	beq.n	8005050 <HAL_RCCEx_PeriphCLKConfig+0x38>
      __HAL_RCC_BACKUPRESET_FORCE();
 80050c8:	2001      	movs	r0, #1
 80050ca:	4a0e      	ldr	r2, [pc, #56]	; (8005104 <HAL_RCCEx_PeriphCLKConfig+0xec>)
      temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
 80050cc:	6a23      	ldr	r3, [r4, #32]
      __HAL_RCC_BACKUPRESET_FORCE();
 80050ce:	6010      	str	r0, [r2, #0]
      __HAL_RCC_BACKUPRESET_RELEASE();
 80050d0:	2000      	movs	r0, #0
      temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
 80050d2:	f423 7140 	bic.w	r1, r3, #768	; 0x300
      __HAL_RCC_BACKUPRESET_RELEASE();
 80050d6:	6010      	str	r0, [r2, #0]
      RCC->BDCR = temp_reg;
 80050d8:	6221      	str	r1, [r4, #32]
      if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
 80050da:	07d9      	lsls	r1, r3, #31
 80050dc:	d5b8      	bpl.n	8005050 <HAL_RCCEx_PeriphCLKConfig+0x38>
        tickstart = HAL_GetTick();
 80050de:	f7ff f8e3 	bl	80042a8 <HAL_GetTick>
          if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 80050e2:	f241 3888 	movw	r8, #5000	; 0x1388
        tickstart = HAL_GetTick();
 80050e6:	4606      	mov	r6, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
 80050e8:	6a23      	ldr	r3, [r4, #32]
 80050ea:	079a      	lsls	r2, r3, #30
 80050ec:	d4b0      	bmi.n	8005050 <HAL_RCCEx_PeriphCLKConfig+0x38>
          if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 80050ee:	f7ff f8db 	bl	80042a8 <HAL_GetTick>
 80050f2:	1b80      	subs	r0, r0, r6
 80050f4:	4540      	cmp	r0, r8
 80050f6:	d9f7      	bls.n	80050e8 <HAL_RCCEx_PeriphCLKConfig+0xd0>
 80050f8:	e7dd      	b.n	80050b6 <HAL_RCCEx_PeriphCLKConfig+0x9e>
 80050fa:	bf00      	nop
 80050fc:	40021000 	.word	0x40021000
 8005100:	40007000 	.word	0x40007000
 8005104:	42420440 	.word	0x42420440

08005108 <HAL_TIM_OC_DelayElapsedCallback>:
 8005108:	4770      	bx	lr

0800510a <HAL_TIM_IC_CaptureCallback>:
 800510a:	4770      	bx	lr

0800510c <HAL_TIM_PWM_PulseFinishedCallback>:
 800510c:	4770      	bx	lr

0800510e <HAL_TIM_TriggerCallback>:
 800510e:	4770      	bx	lr

08005110 <HAL_TIM_IRQHandler>:
  * @retval None
  */
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
  /* Capture compare 1 event */
  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
 8005110:	6803      	ldr	r3, [r0, #0]
{
 8005112:	b510      	push	{r4, lr}
  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
 8005114:	691a      	ldr	r2, [r3, #16]
{
 8005116:	4604      	mov	r4, r0
  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
 8005118:	0791      	lsls	r1, r2, #30
 800511a:	d50e      	bpl.n	800513a <HAL_TIM_IRQHandler+0x2a>
  {
    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
 800511c:	68da      	ldr	r2, [r3, #12]
 800511e:	0792      	lsls	r2, r2, #30
 8005120:	d50b      	bpl.n	800513a <HAL_TIM_IRQHandler+0x2a>
    {
      {
        __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
 8005122:	f06f 0202 	mvn.w	r2, #2
 8005126:	611a      	str	r2, [r3, #16]
        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
 8005128:	2201      	movs	r2, #1

        /* Input capture event */
        if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
 800512a:	699b      	ldr	r3, [r3, #24]
        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
 800512c:	7702      	strb	r2, [r0, #28]
        if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
 800512e:	079b      	lsls	r3, r3, #30
 8005130:	d077      	beq.n	8005222 <HAL_TIM_IRQHandler+0x112>
        {
          HAL_TIM_IC_CaptureCallback(htim);
 8005132:	f7ff ffea 	bl	800510a <HAL_TIM_IC_CaptureCallback>
        else
        {
          HAL_TIM_OC_DelayElapsedCallback(htim);
          HAL_TIM_PWM_PulseFinishedCallback(htim);
        }
        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 8005136:	2300      	movs	r3, #0
 8005138:	7723      	strb	r3, [r4, #28]
      }
    }
  }
  /* Capture compare 2 event */
  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
 800513a:	6823      	ldr	r3, [r4, #0]
 800513c:	691a      	ldr	r2, [r3, #16]
 800513e:	0750      	lsls	r0, r2, #29
 8005140:	d510      	bpl.n	8005164 <HAL_TIM_IRQHandler+0x54>
  {
    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
 8005142:	68da      	ldr	r2, [r3, #12]
 8005144:	0751      	lsls	r1, r2, #29
 8005146:	d50d      	bpl.n	8005164 <HAL_TIM_IRQHandler+0x54>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
 8005148:	f06f 0204 	mvn.w	r2, #4
 800514c:	611a      	str	r2, [r3, #16]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
 800514e:	2202      	movs	r2, #2
      /* Input capture event */
      if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
 8005150:	699b      	ldr	r3, [r3, #24]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
 8005152:	7722      	strb	r2, [r4, #28]
      if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
 8005154:	f413 7f40 	tst.w	r3, #768	; 0x300
      {
        HAL_TIM_IC_CaptureCallback(htim);
 8005158:	4620      	mov	r0, r4
      if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
 800515a:	d068      	beq.n	800522e <HAL_TIM_IRQHandler+0x11e>
        HAL_TIM_IC_CaptureCallback(htim);
 800515c:	f7ff ffd5 	bl	800510a <HAL_TIM_IC_CaptureCallback>
      else
      {
        HAL_TIM_OC_DelayElapsedCallback(htim);
        HAL_TIM_PWM_PulseFinishedCallback(htim);
      }
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 8005160:	2300      	movs	r3, #0
 8005162:	7723      	strb	r3, [r4, #28]
    }
  }
  /* Capture compare 3 event */
  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
 8005164:	6823      	ldr	r3, [r4, #0]
 8005166:	691a      	ldr	r2, [r3, #16]
 8005168:	0712      	lsls	r2, r2, #28
 800516a:	d50f      	bpl.n	800518c <HAL_TIM_IRQHandler+0x7c>
  {
    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
 800516c:	68da      	ldr	r2, [r3, #12]
 800516e:	0710      	lsls	r0, r2, #28
 8005170:	d50c      	bpl.n	800518c <HAL_TIM_IRQHandler+0x7c>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
 8005172:	f06f 0208 	mvn.w	r2, #8
 8005176:	611a      	str	r2, [r3, #16]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
 8005178:	2204      	movs	r2, #4
      /* Input capture event */
      if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
 800517a:	69db      	ldr	r3, [r3, #28]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
 800517c:	7722      	strb	r2, [r4, #28]
      if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
 800517e:	0799      	lsls	r1, r3, #30
      {
        HAL_TIM_IC_CaptureCallback(htim);
 8005180:	4620      	mov	r0, r4
      if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
 8005182:	d05a      	beq.n	800523a <HAL_TIM_IRQHandler+0x12a>
        HAL_TIM_IC_CaptureCallback(htim);
 8005184:	f7ff ffc1 	bl	800510a <HAL_TIM_IC_CaptureCallback>
      else
      {
        HAL_TIM_OC_DelayElapsedCallback(htim);
        HAL_TIM_PWM_PulseFinishedCallback(htim);
      }
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 8005188:	2300      	movs	r3, #0
 800518a:	7723      	strb	r3, [r4, #28]
    }
  }
  /* Capture compare 4 event */
  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
 800518c:	6823      	ldr	r3, [r4, #0]
 800518e:	691a      	ldr	r2, [r3, #16]
 8005190:	06d2      	lsls	r2, r2, #27
 8005192:	d510      	bpl.n	80051b6 <HAL_TIM_IRQHandler+0xa6>
  {
    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
 8005194:	68da      	ldr	r2, [r3, #12]
 8005196:	06d0      	lsls	r0, r2, #27
 8005198:	d50d      	bpl.n	80051b6 <HAL_TIM_IRQHandler+0xa6>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
 800519a:	f06f 0210 	mvn.w	r2, #16
 800519e:	611a      	str	r2, [r3, #16]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
 80051a0:	2208      	movs	r2, #8
      /* Input capture event */
      if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
 80051a2:	69db      	ldr	r3, [r3, #28]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
 80051a4:	7722      	strb	r2, [r4, #28]
      if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
 80051a6:	f413 7f40 	tst.w	r3, #768	; 0x300
      {
        HAL_TIM_IC_CaptureCallback(htim);
 80051aa:	4620      	mov	r0, r4
      if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
 80051ac:	d04b      	beq.n	8005246 <HAL_TIM_IRQHandler+0x136>
        HAL_TIM_IC_CaptureCallback(htim);
 80051ae:	f7ff ffac 	bl	800510a <HAL_TIM_IC_CaptureCallback>
      else
      {
        HAL_TIM_OC_DelayElapsedCallback(htim);
        HAL_TIM_PWM_PulseFinishedCallback(htim);
      }
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 80051b2:	2300      	movs	r3, #0
 80051b4:	7723      	strb	r3, [r4, #28]
    }
  }
  /* TIM Update event */
  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
 80051b6:	6823      	ldr	r3, [r4, #0]
 80051b8:	691a      	ldr	r2, [r3, #16]
 80051ba:	07d1      	lsls	r1, r2, #31
 80051bc:	d508      	bpl.n	80051d0 <HAL_TIM_IRQHandler+0xc0>
  {
    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
 80051be:	68da      	ldr	r2, [r3, #12]
 80051c0:	07d2      	lsls	r2, r2, #31
 80051c2:	d505      	bpl.n	80051d0 <HAL_TIM_IRQHandler+0xc0>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
 80051c4:	f06f 0201 	mvn.w	r2, #1
      HAL_TIM_PeriodElapsedCallback(htim);
 80051c8:	4620      	mov	r0, r4
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
 80051ca:	611a      	str	r2, [r3, #16]
      HAL_TIM_PeriodElapsedCallback(htim);
 80051cc:	f000 fb14 	bl	80057f8 <HAL_TIM_PeriodElapsedCallback>
    }
  }
  /* TIM Break input event */
  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
 80051d0:	6823      	ldr	r3, [r4, #0]
 80051d2:	691a      	ldr	r2, [r3, #16]
 80051d4:	0610      	lsls	r0, r2, #24
 80051d6:	d508      	bpl.n	80051ea <HAL_TIM_IRQHandler+0xda>
  {
    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
 80051d8:	68da      	ldr	r2, [r3, #12]
 80051da:	0611      	lsls	r1, r2, #24
 80051dc:	d505      	bpl.n	80051ea <HAL_TIM_IRQHandler+0xda>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
 80051de:	f06f 0280 	mvn.w	r2, #128	; 0x80
      HAL_TIMEx_BreakCallback(htim);
 80051e2:	4620      	mov	r0, r4
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
 80051e4:	611a      	str	r2, [r3, #16]
      HAL_TIMEx_BreakCallback(htim);
 80051e6:	f000 f8be 	bl	8005366 <HAL_TIMEx_BreakCallback>
    }
  }
  /* TIM Trigger detection event */
  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
 80051ea:	6823      	ldr	r3, [r4, #0]
 80051ec:	691a      	ldr	r2, [r3, #16]
 80051ee:	0652      	lsls	r2, r2, #25
 80051f0:	d508      	bpl.n	8005204 <HAL_TIM_IRQHandler+0xf4>
  {
    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
 80051f2:	68da      	ldr	r2, [r3, #12]
 80051f4:	0650      	lsls	r0, r2, #25
 80051f6:	d505      	bpl.n	8005204 <HAL_TIM_IRQHandler+0xf4>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
 80051f8:	f06f 0240 	mvn.w	r2, #64	; 0x40
      HAL_TIM_TriggerCallback(htim);
 80051fc:	4620      	mov	r0, r4
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
 80051fe:	611a      	str	r2, [r3, #16]
      HAL_TIM_TriggerCallback(htim);
 8005200:	f7ff ff85 	bl	800510e <HAL_TIM_TriggerCallback>
    }
  }
  /* TIM commutation event */
  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
 8005204:	6823      	ldr	r3, [r4, #0]
 8005206:	691a      	ldr	r2, [r3, #16]
 8005208:	0691      	lsls	r1, r2, #26
 800520a:	d522      	bpl.n	8005252 <HAL_TIM_IRQHandler+0x142>
  {
    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
 800520c:	68da      	ldr	r2, [r3, #12]
 800520e:	0692      	lsls	r2, r2, #26
 8005210:	d51f      	bpl.n	8005252 <HAL_TIM_IRQHandler+0x142>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
 8005212:	f06f 0220 	mvn.w	r2, #32
      HAL_TIMEx_CommutationCallback(htim);
 8005216:	4620      	mov	r0, r4
    }
  }
}
 8005218:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
      __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
 800521c:	611a      	str	r2, [r3, #16]
      HAL_TIMEx_CommutationCallback(htim);
 800521e:	f000 b8a1 	b.w	8005364 <HAL_TIMEx_CommutationCallback>
          HAL_TIM_OC_DelayElapsedCallback(htim);
 8005222:	f7ff ff71 	bl	8005108 <HAL_TIM_OC_DelayElapsedCallback>
          HAL_TIM_PWM_PulseFinishedCallback(htim);
 8005226:	4620      	mov	r0, r4
 8005228:	f7ff ff70 	bl	800510c <HAL_TIM_PWM_PulseFinishedCallback>
 800522c:	e783      	b.n	8005136 <HAL_TIM_IRQHandler+0x26>
        HAL_TIM_OC_DelayElapsedCallback(htim);
 800522e:	f7ff ff6b 	bl	8005108 <HAL_TIM_OC_DelayElapsedCallback>
        HAL_TIM_PWM_PulseFinishedCallback(htim);
 8005232:	4620      	mov	r0, r4
 8005234:	f7ff ff6a 	bl	800510c <HAL_TIM_PWM_PulseFinishedCallback>
 8005238:	e792      	b.n	8005160 <HAL_TIM_IRQHandler+0x50>
        HAL_TIM_OC_DelayElapsedCallback(htim);
 800523a:	f7ff ff65 	bl	8005108 <HAL_TIM_OC_DelayElapsedCallback>
        HAL_TIM_PWM_PulseFinishedCallback(htim);
 800523e:	4620      	mov	r0, r4
 8005240:	f7ff ff64 	bl	800510c <HAL_TIM_PWM_PulseFinishedCallback>
 8005244:	e7a0      	b.n	8005188 <HAL_TIM_IRQHandler+0x78>
        HAL_TIM_OC_DelayElapsedCallback(htim);
 8005246:	f7ff ff5f 	bl	8005108 <HAL_TIM_OC_DelayElapsedCallback>
        HAL_TIM_PWM_PulseFinishedCallback(htim);
 800524a:	4620      	mov	r0, r4
 800524c:	f7ff ff5e 	bl	800510c <HAL_TIM_PWM_PulseFinishedCallback>
 8005250:	e7af      	b.n	80051b2 <HAL_TIM_IRQHandler+0xa2>
 8005252:	bd10      	pop	{r4, pc}

08005254 <TIM_Base_SetConfig>:
{
  uint32_t tmpcr1 = 0U;
  tmpcr1 = TIMx->CR1;

  /* Set TIM Time Base Unit parameters ---------------------------------------*/
  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
 8005254:	4a24      	ldr	r2, [pc, #144]	; (80052e8 <TIM_Base_SetConfig+0x94>)
  tmpcr1 = TIMx->CR1;
 8005256:	6803      	ldr	r3, [r0, #0]
  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
 8005258:	4290      	cmp	r0, r2
 800525a:	d012      	beq.n	8005282 <TIM_Base_SetConfig+0x2e>
 800525c:	f502 6200 	add.w	r2, r2, #2048	; 0x800
 8005260:	4290      	cmp	r0, r2
 8005262:	d00e      	beq.n	8005282 <TIM_Base_SetConfig+0x2e>
 8005264:	f1b0 4f80 	cmp.w	r0, #1073741824	; 0x40000000
 8005268:	d00b      	beq.n	8005282 <TIM_Base_SetConfig+0x2e>
 800526a:	f5a2 3298 	sub.w	r2, r2, #77824	; 0x13000
 800526e:	4290      	cmp	r0, r2
 8005270:	d007      	beq.n	8005282 <TIM_Base_SetConfig+0x2e>
 8005272:	f502 6280 	add.w	r2, r2, #1024	; 0x400
 8005276:	4290      	cmp	r0, r2
 8005278:	d003      	beq.n	8005282 <TIM_Base_SetConfig+0x2e>
 800527a:	f502 6280 	add.w	r2, r2, #1024	; 0x400
 800527e:	4290      	cmp	r0, r2
 8005280:	d11d      	bne.n	80052be <TIM_Base_SetConfig+0x6a>
  {
    /* Select the Counter Mode */
    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
    tmpcr1 |= Structure->CounterMode;
 8005282:	684a      	ldr	r2, [r1, #4]
    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
 8005284:	f023 0370 	bic.w	r3, r3, #112	; 0x70
    tmpcr1 |= Structure->CounterMode;
 8005288:	4313      	orrs	r3, r2
  }

  if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
 800528a:	4a17      	ldr	r2, [pc, #92]	; (80052e8 <TIM_Base_SetConfig+0x94>)
 800528c:	4290      	cmp	r0, r2
 800528e:	d012      	beq.n	80052b6 <TIM_Base_SetConfig+0x62>
 8005290:	f502 6200 	add.w	r2, r2, #2048	; 0x800
 8005294:	4290      	cmp	r0, r2
 8005296:	d00e      	beq.n	80052b6 <TIM_Base_SetConfig+0x62>
 8005298:	f1b0 4f80 	cmp.w	r0, #1073741824	; 0x40000000
 800529c:	d00b      	beq.n	80052b6 <TIM_Base_SetConfig+0x62>
 800529e:	f5a2 3298 	sub.w	r2, r2, #77824	; 0x13000
 80052a2:	4290      	cmp	r0, r2
 80052a4:	d007      	beq.n	80052b6 <TIM_Base_SetConfig+0x62>
 80052a6:	f502 6280 	add.w	r2, r2, #1024	; 0x400
 80052aa:	4290      	cmp	r0, r2
 80052ac:	d003      	beq.n	80052b6 <TIM_Base_SetConfig+0x62>
 80052ae:	f502 6280 	add.w	r2, r2, #1024	; 0x400
 80052b2:	4290      	cmp	r0, r2
 80052b4:	d103      	bne.n	80052be <TIM_Base_SetConfig+0x6a>
  {
    /* Set the clock division */
    tmpcr1 &= ~TIM_CR1_CKD;
    tmpcr1 |= (uint32_t)Structure->ClockDivision;
 80052b6:	68ca      	ldr	r2, [r1, #12]
    tmpcr1 &= ~TIM_CR1_CKD;
 80052b8:	f423 7340 	bic.w	r3, r3, #768	; 0x300
    tmpcr1 |= (uint32_t)Structure->ClockDivision;
 80052bc:	4313      	orrs	r3, r2
  }

  /* Set the auto-reload preload */
  tmpcr1 &= ~TIM_CR1_ARPE;
  tmpcr1 |= (uint32_t)Structure->AutoReloadPreload;
 80052be:	694a      	ldr	r2, [r1, #20]
  tmpcr1 &= ~TIM_CR1_ARPE;
 80052c0:	f023 0380 	bic.w	r3, r3, #128	; 0x80
  tmpcr1 |= (uint32_t)Structure->AutoReloadPreload;
 80052c4:	4313      	orrs	r3, r2

  TIMx->CR1 = tmpcr1;
 80052c6:	6003      	str	r3, [r0, #0]

  /* Set the Autoreload value */
  TIMx->ARR = (uint32_t)Structure->Period ;
 80052c8:	688b      	ldr	r3, [r1, #8]
 80052ca:	62c3      	str	r3, [r0, #44]	; 0x2c

  /* Set the Prescaler value */
  TIMx->PSC = (uint32_t)Structure->Prescaler;
 80052cc:	680b      	ldr	r3, [r1, #0]
 80052ce:	6283      	str	r3, [r0, #40]	; 0x28

  if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
 80052d0:	4b05      	ldr	r3, [pc, #20]	; (80052e8 <TIM_Base_SetConfig+0x94>)
 80052d2:	4298      	cmp	r0, r3
 80052d4:	d003      	beq.n	80052de <TIM_Base_SetConfig+0x8a>
 80052d6:	f503 6300 	add.w	r3, r3, #2048	; 0x800
 80052da:	4298      	cmp	r0, r3
 80052dc:	d101      	bne.n	80052e2 <TIM_Base_SetConfig+0x8e>
  {
    /* Set the Repetition Counter value */
    TIMx->RCR = Structure->RepetitionCounter;
 80052de:	690b      	ldr	r3, [r1, #16]
 80052e0:	6303      	str	r3, [r0, #48]	; 0x30
  }

  /* Generate an update event to reload the Prescaler 
     and the repetition counter(only for TIM1 and TIM8) value immediatly */
  TIMx->EGR = TIM_EGR_UG;
 80052e2:	2301      	movs	r3, #1
 80052e4:	6143      	str	r3, [r0, #20]
 80052e6:	4770      	bx	lr
 80052e8:	40012c00 	.word	0x40012c00

080052ec <HAL_TIM_Base_Init>:
{
 80052ec:	b510      	push	{r4, lr}
  if(htim == NULL)
 80052ee:	4604      	mov	r4, r0
 80052f0:	b1a0      	cbz	r0, 800531c <HAL_TIM_Base_Init+0x30>
  if(htim->State == HAL_TIM_STATE_RESET)
 80052f2:	f890 303d 	ldrb.w	r3, [r0, #61]	; 0x3d
 80052f6:	f003 02ff 	and.w	r2, r3, #255	; 0xff
 80052fa:	b91b      	cbnz	r3, 8005304 <HAL_TIM_Base_Init+0x18>
    htim->Lock = HAL_UNLOCKED;
 80052fc:	f880 203c 	strb.w	r2, [r0, #60]	; 0x3c
    HAL_TIM_Base_MspInit(htim);
 8005300:	f000 fd26 	bl	8005d50 <HAL_TIM_Base_MspInit>
  htim->State= HAL_TIM_STATE_BUSY;
 8005304:	2302      	movs	r3, #2
  TIM_Base_SetConfig(htim->Instance, &htim->Init);
 8005306:	6820      	ldr	r0, [r4, #0]
  htim->State= HAL_TIM_STATE_BUSY;
 8005308:	f884 303d 	strb.w	r3, [r4, #61]	; 0x3d
  TIM_Base_SetConfig(htim->Instance, &htim->Init);
 800530c:	1d21      	adds	r1, r4, #4
 800530e:	f7ff ffa1 	bl	8005254 <TIM_Base_SetConfig>
  htim->State= HAL_TIM_STATE_READY;
 8005312:	2301      	movs	r3, #1
  return HAL_OK;
 8005314:	2000      	movs	r0, #0
  htim->State= HAL_TIM_STATE_READY;
 8005316:	f884 303d 	strb.w	r3, [r4, #61]	; 0x3d
  return HAL_OK;
 800531a:	bd10      	pop	{r4, pc}
    return HAL_ERROR;
 800531c:	2001      	movs	r0, #1
}
 800531e:	bd10      	pop	{r4, pc}

08005320 <HAL_TIMEx_MasterConfigSynchronization>:
  /* Check the parameters */
  assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
  assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
  assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));

  __HAL_LOCK(htim);
 8005320:	f890 303c 	ldrb.w	r3, [r0, #60]	; 0x3c
{
 8005324:	b510      	push	{r4, lr}
  __HAL_LOCK(htim);
 8005326:	2b01      	cmp	r3, #1
 8005328:	f04f 0302 	mov.w	r3, #2
 800532c:	d018      	beq.n	8005360 <HAL_TIMEx_MasterConfigSynchronization+0x40>

  htim->State = HAL_TIM_STATE_BUSY;
 800532e:	f880 303d 	strb.w	r3, [r0, #61]	; 0x3d

  /* Reset the MMS Bits */
  htim->Instance->CR2 &= ~TIM_CR2_MMS;
 8005332:	6803      	ldr	r3, [r0, #0]
  /* Select the TRGO source */
  htim->Instance->CR2 |=  sMasterConfig->MasterOutputTrigger;
 8005334:	680c      	ldr	r4, [r1, #0]
  htim->Instance->CR2 &= ~TIM_CR2_MMS;
 8005336:	685a      	ldr	r2, [r3, #4]

  /* Reset the MSM Bit */
  htim->Instance->SMCR &= ~TIM_SMCR_MSM;
  /* Set or Reset the MSM Bit */
  htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode;
 8005338:	6849      	ldr	r1, [r1, #4]
  htim->Instance->CR2 &= ~TIM_CR2_MMS;
 800533a:	f022 0270 	bic.w	r2, r2, #112	; 0x70
 800533e:	605a      	str	r2, [r3, #4]
  htim->Instance->CR2 |=  sMasterConfig->MasterOutputTrigger;
 8005340:	685a      	ldr	r2, [r3, #4]
 8005342:	4322      	orrs	r2, r4
 8005344:	605a      	str	r2, [r3, #4]
  htim->Instance->SMCR &= ~TIM_SMCR_MSM;
 8005346:	689a      	ldr	r2, [r3, #8]
 8005348:	f022 0280 	bic.w	r2, r2, #128	; 0x80
 800534c:	609a      	str	r2, [r3, #8]
  htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode;
 800534e:	689a      	ldr	r2, [r3, #8]
 8005350:	430a      	orrs	r2, r1
 8005352:	609a      	str	r2, [r3, #8]

  htim->State = HAL_TIM_STATE_READY;
 8005354:	2301      	movs	r3, #1
 8005356:	f880 303d 	strb.w	r3, [r0, #61]	; 0x3d

  __HAL_UNLOCK(htim);
 800535a:	2300      	movs	r3, #0
 800535c:	f880 303c 	strb.w	r3, [r0, #60]	; 0x3c
  __HAL_LOCK(htim);
 8005360:	4618      	mov	r0, r3

  return HAL_OK;
}
 8005362:	bd10      	pop	{r4, pc}

08005364 <HAL_TIMEx_CommutationCallback>:
 8005364:	4770      	bx	lr

08005366 <HAL_TIMEx_BreakCallback>:
  * @brief  Hall Break detection callback in non blocking mode
  * @param  htim : TIM handle
  * @retval None
  */
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
{
 8005366:	4770      	bx	lr

08005368 <UART_EndRxTransfer>:
  * @retval None
  */
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
{
  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
 8005368:	6803      	ldr	r3, [r0, #0]
 800536a:	68da      	ldr	r2, [r3, #12]
 800536c:	f422 7290 	bic.w	r2, r2, #288	; 0x120
 8005370:	60da      	str	r2, [r3, #12]
  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 8005372:	695a      	ldr	r2, [r3, #20]
 8005374:	f022 0201 	bic.w	r2, r2, #1
 8005378:	615a      	str	r2, [r3, #20]

  /* At end of Rx process, restore huart->RxState to Ready */
  huart->RxState = HAL_UART_STATE_READY;
 800537a:	2320      	movs	r3, #32
 800537c:	f880 303a 	strb.w	r3, [r0, #58]	; 0x3a
 8005380:	4770      	bx	lr
	...

08005384 <UART_SetConfig>:
  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
  *                the configuration information for the specified UART module.
  * @retval None
  */
static void UART_SetConfig(UART_HandleTypeDef *huart)
{
 8005384:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
  assert_param(IS_UART_MODE(huart->Init.Mode));

  /*------- UART-associated USART registers setting : CR2 Configuration ------*/
  /* Configure the UART Stop Bits: Set STOP[13:12] bits according 
   * to huart->Init.StopBits value */
  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
 8005388:	6805      	ldr	r5, [r0, #0]
 800538a:	68c2      	ldr	r2, [r0, #12]
 800538c:	692b      	ldr	r3, [r5, #16]
  tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
  MODIFY_REG(huart->Instance->CR1, 
             (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), 
             tmpreg);
#else
  tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
 800538e:	6901      	ldr	r1, [r0, #16]
  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
 8005390:	f423 5340 	bic.w	r3, r3, #12288	; 0x3000
 8005394:	4313      	orrs	r3, r2
 8005396:	612b      	str	r3, [r5, #16]
  tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
 8005398:	6883      	ldr	r3, [r0, #8]
  MODIFY_REG(huart->Instance->CR1, 
 800539a:	68ea      	ldr	r2, [r5, #12]
  tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
 800539c:	430b      	orrs	r3, r1
 800539e:	6941      	ldr	r1, [r0, #20]
  MODIFY_REG(huart->Instance->CR1, 
 80053a0:	f422 52b0 	bic.w	r2, r2, #5632	; 0x1600
 80053a4:	f022 020c 	bic.w	r2, r2, #12
  tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
 80053a8:	430b      	orrs	r3, r1
  MODIFY_REG(huart->Instance->CR1, 
 80053aa:	4313      	orrs	r3, r2
 80053ac:	60eb      	str	r3, [r5, #12]
             tmpreg);
#endif /* USART_CR1_OVER8 */

  /*------- UART-associated USART registers setting : CR3 Configuration ------*/
  /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
  MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
 80053ae:	696b      	ldr	r3, [r5, #20]
 80053b0:	6982      	ldr	r2, [r0, #24]
 80053b2:	f423 7340 	bic.w	r3, r3, #768	; 0x300
 80053b6:	4313      	orrs	r3, r2
 80053b8:	616b      	str	r3, [r5, #20]
      huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
    }
  }
#else
  /*-------------------------- USART BRR Configuration ---------------------*/
  if(huart->Instance == USART1)
 80053ba:	4b40      	ldr	r3, [pc, #256]	; (80054bc <UART_SetConfig+0x138>)
{
 80053bc:	4681      	mov	r9, r0
  if(huart->Instance == USART1)
 80053be:	429d      	cmp	r5, r3
 80053c0:	f04f 0419 	mov.w	r4, #25
 80053c4:	d146      	bne.n	8005454 <UART_SetConfig+0xd0>
  {
    huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
 80053c6:	f7ff fe17 	bl	8004ff8 <HAL_RCC_GetPCLK2Freq>
 80053ca:	fb04 f300 	mul.w	r3, r4, r0
 80053ce:	f8d9 6004 	ldr.w	r6, [r9, #4]
 80053d2:	f04f 0864 	mov.w	r8, #100	; 0x64
 80053d6:	00b6      	lsls	r6, r6, #2
 80053d8:	fbb3 f3f6 	udiv	r3, r3, r6
 80053dc:	fbb3 f3f8 	udiv	r3, r3, r8
 80053e0:	011e      	lsls	r6, r3, #4
 80053e2:	f7ff fe09 	bl	8004ff8 <HAL_RCC_GetPCLK2Freq>
 80053e6:	4360      	muls	r0, r4
 80053e8:	f8d9 3004 	ldr.w	r3, [r9, #4]
 80053ec:	009b      	lsls	r3, r3, #2
 80053ee:	fbb0 f7f3 	udiv	r7, r0, r3
 80053f2:	f7ff fe01 	bl	8004ff8 <HAL_RCC_GetPCLK2Freq>
 80053f6:	4360      	muls	r0, r4
 80053f8:	f8d9 3004 	ldr.w	r3, [r9, #4]
 80053fc:	009b      	lsls	r3, r3, #2
 80053fe:	fbb0 f3f3 	udiv	r3, r0, r3
 8005402:	fbb3 f3f8 	udiv	r3, r3, r8
 8005406:	fb08 7313 	mls	r3, r8, r3, r7
 800540a:	011b      	lsls	r3, r3, #4
 800540c:	3332      	adds	r3, #50	; 0x32
 800540e:	fbb3 f3f8 	udiv	r3, r3, r8
 8005412:	f003 07f0 	and.w	r7, r3, #240	; 0xf0
 8005416:	f7ff fdef 	bl	8004ff8 <HAL_RCC_GetPCLK2Freq>
 800541a:	4360      	muls	r0, r4
 800541c:	f8d9 2004 	ldr.w	r2, [r9, #4]
 8005420:	0092      	lsls	r2, r2, #2
 8005422:	fbb0 faf2 	udiv	sl, r0, r2
 8005426:	f7ff fde7 	bl	8004ff8 <HAL_RCC_GetPCLK2Freq>
  }
  else
  {
    huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
 800542a:	4360      	muls	r0, r4
 800542c:	f8d9 3004 	ldr.w	r3, [r9, #4]
 8005430:	009b      	lsls	r3, r3, #2
 8005432:	fbb0 f3f3 	udiv	r3, r0, r3
 8005436:	fbb3 f3f8 	udiv	r3, r3, r8
 800543a:	fb08 a313 	mls	r3, r8, r3, sl
 800543e:	011b      	lsls	r3, r3, #4
 8005440:	3332      	adds	r3, #50	; 0x32
 8005442:	fbb3 f3f8 	udiv	r3, r3, r8
 8005446:	f003 030f 	and.w	r3, r3, #15
 800544a:	433b      	orrs	r3, r7
 800544c:	4433      	add	r3, r6
 800544e:	60ab      	str	r3, [r5, #8]
 8005450:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 8005454:	f7ff fdc0 	bl	8004fd8 <HAL_RCC_GetPCLK1Freq>
 8005458:	fb04 f300 	mul.w	r3, r4, r0
 800545c:	f8d9 6004 	ldr.w	r6, [r9, #4]
 8005460:	f04f 0864 	mov.w	r8, #100	; 0x64
 8005464:	00b6      	lsls	r6, r6, #2
 8005466:	fbb3 f3f6 	udiv	r3, r3, r6
 800546a:	fbb3 f3f8 	udiv	r3, r3, r8
 800546e:	011e      	lsls	r6, r3, #4
 8005470:	f7ff fdb2 	bl	8004fd8 <HAL_RCC_GetPCLK1Freq>
 8005474:	4360      	muls	r0, r4
 8005476:	f8d9 3004 	ldr.w	r3, [r9, #4]
 800547a:	009b      	lsls	r3, r3, #2
 800547c:	fbb0 f7f3 	udiv	r7, r0, r3
 8005480:	f7ff fdaa 	bl	8004fd8 <HAL_RCC_GetPCLK1Freq>
 8005484:	4360      	muls	r0, r4
 8005486:	f8d9 3004 	ldr.w	r3, [r9, #4]
 800548a:	009b      	lsls	r3, r3, #2
 800548c:	fbb0 f3f3 	udiv	r3, r0, r3
 8005490:	fbb3 f3f8 	udiv	r3, r3, r8
 8005494:	fb08 7313 	mls	r3, r8, r3, r7
 8005498:	011b      	lsls	r3, r3, #4
 800549a:	3332      	adds	r3, #50	; 0x32
 800549c:	fbb3 f3f8 	udiv	r3, r3, r8
 80054a0:	f003 07f0 	and.w	r7, r3, #240	; 0xf0
 80054a4:	f7ff fd98 	bl	8004fd8 <HAL_RCC_GetPCLK1Freq>
 80054a8:	4360      	muls	r0, r4
 80054aa:	f8d9 2004 	ldr.w	r2, [r9, #4]
 80054ae:	0092      	lsls	r2, r2, #2
 80054b0:	fbb0 faf2 	udiv	sl, r0, r2
 80054b4:	f7ff fd90 	bl	8004fd8 <HAL_RCC_GetPCLK1Freq>
 80054b8:	e7b7      	b.n	800542a <UART_SetConfig+0xa6>
 80054ba:	bf00      	nop
 80054bc:	40013800 	.word	0x40013800

080054c0 <UART_WaitOnFlagUntilTimeout.constprop.3>:
static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
 80054c0:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 80054c2:	4604      	mov	r4, r0
 80054c4:	460e      	mov	r6, r1
 80054c6:	4617      	mov	r7, r2
 80054c8:	461d      	mov	r5, r3
  while((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 
 80054ca:	6821      	ldr	r1, [r4, #0]
 80054cc:	680b      	ldr	r3, [r1, #0]
 80054ce:	ea36 0303 	bics.w	r3, r6, r3
 80054d2:	d101      	bne.n	80054d8 <UART_WaitOnFlagUntilTimeout.constprop.3+0x18>
  return HAL_OK;
 80054d4:	2000      	movs	r0, #0
}
 80054d6:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    if(Timeout != HAL_MAX_DELAY)
 80054d8:	1c6b      	adds	r3, r5, #1
 80054da:	d0f7      	beq.n	80054cc <UART_WaitOnFlagUntilTimeout.constprop.3+0xc>
      if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
 80054dc:	b995      	cbnz	r5, 8005504 <UART_WaitOnFlagUntilTimeout.constprop.3+0x44>
        CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
 80054de:	6823      	ldr	r3, [r4, #0]
        __HAL_UNLOCK(huart);
 80054e0:	2003      	movs	r0, #3
        CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
 80054e2:	68da      	ldr	r2, [r3, #12]
 80054e4:	f422 72d0 	bic.w	r2, r2, #416	; 0x1a0
 80054e8:	60da      	str	r2, [r3, #12]
        CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 80054ea:	695a      	ldr	r2, [r3, #20]
 80054ec:	f022 0201 	bic.w	r2, r2, #1
 80054f0:	615a      	str	r2, [r3, #20]
        huart->gState  = HAL_UART_STATE_READY;
 80054f2:	2320      	movs	r3, #32
 80054f4:	f884 3039 	strb.w	r3, [r4, #57]	; 0x39
        huart->RxState = HAL_UART_STATE_READY;
 80054f8:	f884 303a 	strb.w	r3, [r4, #58]	; 0x3a
        __HAL_UNLOCK(huart);
 80054fc:	2300      	movs	r3, #0
 80054fe:	f884 3038 	strb.w	r3, [r4, #56]	; 0x38
 8005502:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
      if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
 8005504:	f7fe fed0 	bl	80042a8 <HAL_GetTick>
 8005508:	1bc0      	subs	r0, r0, r7
 800550a:	4285      	cmp	r5, r0
 800550c:	d2dd      	bcs.n	80054ca <UART_WaitOnFlagUntilTimeout.constprop.3+0xa>
 800550e:	e7e6      	b.n	80054de <UART_WaitOnFlagUntilTimeout.constprop.3+0x1e>

08005510 <HAL_UART_Init>:
{
 8005510:	b510      	push	{r4, lr}
  if(huart == NULL)
 8005512:	4604      	mov	r4, r0
 8005514:	b340      	cbz	r0, 8005568 <HAL_UART_Init+0x58>
  if(huart->gState == HAL_UART_STATE_RESET)
 8005516:	f890 3039 	ldrb.w	r3, [r0, #57]	; 0x39
 800551a:	f003 02ff 	and.w	r2, r3, #255	; 0xff
 800551e:	b91b      	cbnz	r3, 8005528 <HAL_UART_Init+0x18>
    huart->Lock = HAL_UNLOCKED;
 8005520:	f880 2038 	strb.w	r2, [r0, #56]	; 0x38
    HAL_UART_MspInit(huart);
 8005524:	f000 fc28 	bl	8005d78 <HAL_UART_MspInit>
  huart->gState = HAL_UART_STATE_BUSY;
 8005528:	2324      	movs	r3, #36	; 0x24
  __HAL_UART_DISABLE(huart);
 800552a:	6822      	ldr	r2, [r4, #0]
  huart->gState = HAL_UART_STATE_BUSY;
 800552c:	f884 3039 	strb.w	r3, [r4, #57]	; 0x39
  __HAL_UART_DISABLE(huart);
 8005530:	68d3      	ldr	r3, [r2, #12]
  UART_SetConfig(huart);
 8005532:	4620      	mov	r0, r4
  __HAL_UART_DISABLE(huart);
 8005534:	f423 5300 	bic.w	r3, r3, #8192	; 0x2000
 8005538:	60d3      	str	r3, [r2, #12]
  UART_SetConfig(huart);
 800553a:	f7ff ff23 	bl	8005384 <UART_SetConfig>
  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
 800553e:	6823      	ldr	r3, [r4, #0]
  huart->ErrorCode = HAL_UART_ERROR_NONE;
 8005540:	2000      	movs	r0, #0
  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
 8005542:	691a      	ldr	r2, [r3, #16]
 8005544:	f422 4290 	bic.w	r2, r2, #18432	; 0x4800
 8005548:	611a      	str	r2, [r3, #16]
  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
 800554a:	695a      	ldr	r2, [r3, #20]
 800554c:	f022 022a 	bic.w	r2, r2, #42	; 0x2a
 8005550:	615a      	str	r2, [r3, #20]
  __HAL_UART_ENABLE(huart);
 8005552:	68da      	ldr	r2, [r3, #12]
 8005554:	f442 5200 	orr.w	r2, r2, #8192	; 0x2000
 8005558:	60da      	str	r2, [r3, #12]
  huart->gState= HAL_UART_STATE_READY;
 800555a:	2320      	movs	r3, #32
  huart->ErrorCode = HAL_UART_ERROR_NONE;
 800555c:	63e0      	str	r0, [r4, #60]	; 0x3c
  huart->gState= HAL_UART_STATE_READY;
 800555e:	f884 3039 	strb.w	r3, [r4, #57]	; 0x39
  huart->RxState= HAL_UART_STATE_READY;
 8005562:	f884 303a 	strb.w	r3, [r4, #58]	; 0x3a
  return HAL_OK;
 8005566:	bd10      	pop	{r4, pc}
    return HAL_ERROR;
 8005568:	2001      	movs	r0, #1
}
 800556a:	bd10      	pop	{r4, pc}

0800556c <HAL_UART_Transmit>:
{
 800556c:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
 8005570:	461f      	mov	r7, r3
  if(huart->gState == HAL_UART_STATE_READY)
 8005572:	f890 3039 	ldrb.w	r3, [r0, #57]	; 0x39
{
 8005576:	4604      	mov	r4, r0
  if(huart->gState == HAL_UART_STATE_READY)
 8005578:	2b20      	cmp	r3, #32
{
 800557a:	460d      	mov	r5, r1
 800557c:	4690      	mov	r8, r2
  if(huart->gState == HAL_UART_STATE_READY)
 800557e:	d14e      	bne.n	800561e <HAL_UART_Transmit+0xb2>
    if((pData == NULL) || (Size == 0U))
 8005580:	2900      	cmp	r1, #0
 8005582:	d049      	beq.n	8005618 <HAL_UART_Transmit+0xac>
 8005584:	2a00      	cmp	r2, #0
 8005586:	d047      	beq.n	8005618 <HAL_UART_Transmit+0xac>
    __HAL_LOCK(huart);
 8005588:	f890 3038 	ldrb.w	r3, [r0, #56]	; 0x38
 800558c:	2b01      	cmp	r3, #1
 800558e:	d046      	beq.n	800561e <HAL_UART_Transmit+0xb2>
 8005590:	2301      	movs	r3, #1
 8005592:	f880 3038 	strb.w	r3, [r0, #56]	; 0x38
    huart->ErrorCode = HAL_UART_ERROR_NONE;
 8005596:	2300      	movs	r3, #0
 8005598:	63c3      	str	r3, [r0, #60]	; 0x3c
    huart->gState = HAL_UART_STATE_BUSY_TX;
 800559a:	2321      	movs	r3, #33	; 0x21
 800559c:	f880 3039 	strb.w	r3, [r0, #57]	; 0x39
    tickstart = HAL_GetTick();
 80055a0:	f7fe fe82 	bl	80042a8 <HAL_GetTick>
 80055a4:	4606      	mov	r6, r0
    huart->TxXferSize = Size;
 80055a6:	f8a4 8024 	strh.w	r8, [r4, #36]	; 0x24
    huart->TxXferCount = Size;
 80055aa:	f8a4 8026 	strh.w	r8, [r4, #38]	; 0x26
    while(huart->TxXferCount > 0U)
 80055ae:	8ce3      	ldrh	r3, [r4, #38]	; 0x26
 80055b0:	b29b      	uxth	r3, r3
 80055b2:	b96b      	cbnz	r3, 80055d0 <HAL_UART_Transmit+0x64>
    if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
 80055b4:	463b      	mov	r3, r7
 80055b6:	4632      	mov	r2, r6
 80055b8:	2140      	movs	r1, #64	; 0x40
 80055ba:	4620      	mov	r0, r4
 80055bc:	f7ff ff80 	bl	80054c0 <UART_WaitOnFlagUntilTimeout.constprop.3>
 80055c0:	b9a8      	cbnz	r0, 80055ee <HAL_UART_Transmit+0x82>
    huart->gState = HAL_UART_STATE_READY;
 80055c2:	2320      	movs	r3, #32
    __HAL_UNLOCK(huart);
 80055c4:	f884 0038 	strb.w	r0, [r4, #56]	; 0x38
    huart->gState = HAL_UART_STATE_READY;
 80055c8:	f884 3039 	strb.w	r3, [r4, #57]	; 0x39
    return HAL_OK;
 80055cc:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
      huart->TxXferCount--;
 80055d0:	8ce3      	ldrh	r3, [r4, #38]	; 0x26
        if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
 80055d2:	4632      	mov	r2, r6
      huart->TxXferCount--;
 80055d4:	3b01      	subs	r3, #1
 80055d6:	b29b      	uxth	r3, r3
 80055d8:	84e3      	strh	r3, [r4, #38]	; 0x26
      if(huart->Init.WordLength == UART_WORDLENGTH_9B)
 80055da:	68a3      	ldr	r3, [r4, #8]
        if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
 80055dc:	2180      	movs	r1, #128	; 0x80
      if(huart->Init.WordLength == UART_WORDLENGTH_9B)
 80055de:	f5b3 5f80 	cmp.w	r3, #4096	; 0x1000
        if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
 80055e2:	4620      	mov	r0, r4
 80055e4:	463b      	mov	r3, r7
      if(huart->Init.WordLength == UART_WORDLENGTH_9B)
 80055e6:	d10e      	bne.n	8005606 <HAL_UART_Transmit+0x9a>
        if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
 80055e8:	f7ff ff6a 	bl	80054c0 <UART_WaitOnFlagUntilTimeout.constprop.3>
 80055ec:	b110      	cbz	r0, 80055f4 <HAL_UART_Transmit+0x88>
          return HAL_TIMEOUT;
 80055ee:	2003      	movs	r0, #3
 80055f0:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
        huart->Instance->DR = (*tmp & (uint16_t)0x01FF);
 80055f4:	882b      	ldrh	r3, [r5, #0]
 80055f6:	6822      	ldr	r2, [r4, #0]
 80055f8:	f3c3 0308 	ubfx	r3, r3, #0, #9
 80055fc:	6053      	str	r3, [r2, #4]
        if(huart->Init.Parity == UART_PARITY_NONE)
 80055fe:	6923      	ldr	r3, [r4, #16]
 8005600:	b943      	cbnz	r3, 8005614 <HAL_UART_Transmit+0xa8>
          pData +=2U;
 8005602:	3502      	adds	r5, #2
 8005604:	e7d3      	b.n	80055ae <HAL_UART_Transmit+0x42>
        if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
 8005606:	f7ff ff5b 	bl	80054c0 <UART_WaitOnFlagUntilTimeout.constprop.3>
 800560a:	2800      	cmp	r0, #0
 800560c:	d1ef      	bne.n	80055ee <HAL_UART_Transmit+0x82>
        huart->Instance->DR = (*pData++ & (uint8_t)0xFF);
 800560e:	6823      	ldr	r3, [r4, #0]
 8005610:	782a      	ldrb	r2, [r5, #0]
 8005612:	605a      	str	r2, [r3, #4]
 8005614:	3501      	adds	r5, #1
 8005616:	e7ca      	b.n	80055ae <HAL_UART_Transmit+0x42>
      return  HAL_ERROR;
 8005618:	2001      	movs	r0, #1
 800561a:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    return HAL_BUSY;
 800561e:	2002      	movs	r0, #2
}
 8005620:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

08005624 <HAL_UART_TxCpltCallback>:
 8005624:	4770      	bx	lr

08005626 <HAL_UART_RxCpltCallback>:
 8005626:	4770      	bx	lr

08005628 <UART_Receive_IT>:
  if(huart->RxState == HAL_UART_STATE_BUSY_RX) 
 8005628:	f890 303a 	ldrb.w	r3, [r0, #58]	; 0x3a
{
 800562c:	b510      	push	{r4, lr}
  if(huart->RxState == HAL_UART_STATE_BUSY_RX) 
 800562e:	2b22      	cmp	r3, #34	; 0x22
 8005630:	d136      	bne.n	80056a0 <UART_Receive_IT+0x78>
    if(huart->Init.WordLength == UART_WORDLENGTH_9B)
 8005632:	6883      	ldr	r3, [r0, #8]
 8005634:	6901      	ldr	r1, [r0, #16]
 8005636:	f5b3 5f80 	cmp.w	r3, #4096	; 0x1000
 800563a:	6802      	ldr	r2, [r0, #0]
 800563c:	6a83      	ldr	r3, [r0, #40]	; 0x28
 800563e:	d123      	bne.n	8005688 <UART_Receive_IT+0x60>
        *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
 8005640:	6852      	ldr	r2, [r2, #4]
      if(huart->Init.Parity == UART_PARITY_NONE)
 8005642:	b9e9      	cbnz	r1, 8005680 <UART_Receive_IT+0x58>
        *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
 8005644:	f3c2 0208 	ubfx	r2, r2, #0, #9
 8005648:	f823 2b02 	strh.w	r2, [r3], #2
        huart->pRxBuffPtr += 1U;
 800564c:	6283      	str	r3, [r0, #40]	; 0x28
    if(--huart->RxXferCount == 0U)
 800564e:	8dc4      	ldrh	r4, [r0, #46]	; 0x2e
 8005650:	3c01      	subs	r4, #1
 8005652:	b2a4      	uxth	r4, r4
 8005654:	85c4      	strh	r4, [r0, #46]	; 0x2e
 8005656:	b98c      	cbnz	r4, 800567c <UART_Receive_IT+0x54>
      __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
 8005658:	6803      	ldr	r3, [r0, #0]
 800565a:	68da      	ldr	r2, [r3, #12]
 800565c:	f022 0220 	bic.w	r2, r2, #32
 8005660:	60da      	str	r2, [r3, #12]
      __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
 8005662:	68da      	ldr	r2, [r3, #12]
 8005664:	f422 7280 	bic.w	r2, r2, #256	; 0x100
 8005668:	60da      	str	r2, [r3, #12]
        __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
 800566a:	695a      	ldr	r2, [r3, #20]
 800566c:	f022 0201 	bic.w	r2, r2, #1
 8005670:	615a      	str	r2, [r3, #20]
      huart->RxState = HAL_UART_STATE_READY;
 8005672:	2320      	movs	r3, #32
 8005674:	f880 303a 	strb.w	r3, [r0, #58]	; 0x3a
      HAL_UART_RxCpltCallback(huart);
 8005678:	f7ff ffd5 	bl	8005626 <HAL_UART_RxCpltCallback>
    if(--huart->RxXferCount == 0U)
 800567c:	2000      	movs	r0, #0
}
 800567e:	bd10      	pop	{r4, pc}
        *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF);
 8005680:	b2d2      	uxtb	r2, r2
 8005682:	f823 2b01 	strh.w	r2, [r3], #1
 8005686:	e7e1      	b.n	800564c <UART_Receive_IT+0x24>
      if(huart->Init.Parity == UART_PARITY_NONE)
 8005688:	b921      	cbnz	r1, 8005694 <UART_Receive_IT+0x6c>
        *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
 800568a:	1c59      	adds	r1, r3, #1
 800568c:	6852      	ldr	r2, [r2, #4]
 800568e:	6281      	str	r1, [r0, #40]	; 0x28
        *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
 8005690:	701a      	strb	r2, [r3, #0]
 8005692:	e7dc      	b.n	800564e <UART_Receive_IT+0x26>
 8005694:	6852      	ldr	r2, [r2, #4]
 8005696:	1c59      	adds	r1, r3, #1
 8005698:	6281      	str	r1, [r0, #40]	; 0x28
 800569a:	f002 027f 	and.w	r2, r2, #127	; 0x7f
 800569e:	e7f7      	b.n	8005690 <UART_Receive_IT+0x68>
    return HAL_BUSY;
 80056a0:	2002      	movs	r0, #2
 80056a2:	bd10      	pop	{r4, pc}

080056a4 <HAL_UART_ErrorCallback>:
 80056a4:	4770      	bx	lr
	...

080056a8 <HAL_UART_IRQHandler>:
   uint32_t isrflags   = READ_REG(huart->Instance->SR);
 80056a8:	6803      	ldr	r3, [r0, #0]
{
 80056aa:	b570      	push	{r4, r5, r6, lr}
   uint32_t isrflags   = READ_REG(huart->Instance->SR);
 80056ac:	681a      	ldr	r2, [r3, #0]
{
 80056ae:	4604      	mov	r4, r0
  if(errorflags == RESET)
 80056b0:	0716      	lsls	r6, r2, #28
   uint32_t cr1its     = READ_REG(huart->Instance->CR1);
 80056b2:	68d9      	ldr	r1, [r3, #12]
   uint32_t cr3its     = READ_REG(huart->Instance->CR3);
 80056b4:	695d      	ldr	r5, [r3, #20]
  if(errorflags == RESET)
 80056b6:	d107      	bne.n	80056c8 <HAL_UART_IRQHandler+0x20>
    if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
 80056b8:	0696      	lsls	r6, r2, #26
 80056ba:	d55a      	bpl.n	8005772 <HAL_UART_IRQHandler+0xca>
 80056bc:	068d      	lsls	r5, r1, #26
 80056be:	d558      	bpl.n	8005772 <HAL_UART_IRQHandler+0xca>
}
 80056c0:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
      UART_Receive_IT(huart);
 80056c4:	f7ff bfb0 	b.w	8005628 <UART_Receive_IT>
  if((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
 80056c8:	f015 0501 	ands.w	r5, r5, #1
 80056cc:	d102      	bne.n	80056d4 <HAL_UART_IRQHandler+0x2c>
 80056ce:	f411 7f90 	tst.w	r1, #288	; 0x120
 80056d2:	d04e      	beq.n	8005772 <HAL_UART_IRQHandler+0xca>
    if(((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
 80056d4:	07d3      	lsls	r3, r2, #31
 80056d6:	d505      	bpl.n	80056e4 <HAL_UART_IRQHandler+0x3c>
 80056d8:	05ce      	lsls	r6, r1, #23
      huart->ErrorCode |= HAL_UART_ERROR_PE;
 80056da:	bf42      	ittt	mi
 80056dc:	6be3      	ldrmi	r3, [r4, #60]	; 0x3c
 80056de:	f043 0301 	orrmi.w	r3, r3, #1
 80056e2:	63e3      	strmi	r3, [r4, #60]	; 0x3c
    if(((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
 80056e4:	0750      	lsls	r0, r2, #29
 80056e6:	d504      	bpl.n	80056f2 <HAL_UART_IRQHandler+0x4a>
 80056e8:	b11d      	cbz	r5, 80056f2 <HAL_UART_IRQHandler+0x4a>
      huart->ErrorCode |= HAL_UART_ERROR_NE;
 80056ea:	6be3      	ldr	r3, [r4, #60]	; 0x3c
 80056ec:	f043 0302 	orr.w	r3, r3, #2
 80056f0:	63e3      	str	r3, [r4, #60]	; 0x3c
    if(((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
 80056f2:	0793      	lsls	r3, r2, #30
 80056f4:	d504      	bpl.n	8005700 <HAL_UART_IRQHandler+0x58>
 80056f6:	b11d      	cbz	r5, 8005700 <HAL_UART_IRQHandler+0x58>
      huart->ErrorCode |= HAL_UART_ERROR_FE;
 80056f8:	6be3      	ldr	r3, [r4, #60]	; 0x3c
 80056fa:	f043 0304 	orr.w	r3, r3, #4
 80056fe:	63e3      	str	r3, [r4, #60]	; 0x3c
    if(((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
 8005700:	0716      	lsls	r6, r2, #28
 8005702:	d504      	bpl.n	800570e <HAL_UART_IRQHandler+0x66>
 8005704:	b11d      	cbz	r5, 800570e <HAL_UART_IRQHandler+0x66>
      huart->ErrorCode |= HAL_UART_ERROR_ORE;
 8005706:	6be3      	ldr	r3, [r4, #60]	; 0x3c
 8005708:	f043 0308 	orr.w	r3, r3, #8
 800570c:	63e3      	str	r3, [r4, #60]	; 0x3c
    if(huart->ErrorCode != HAL_UART_ERROR_NONE)
 800570e:	6be3      	ldr	r3, [r4, #60]	; 0x3c
 8005710:	2b00      	cmp	r3, #0
 8005712:	d066      	beq.n	80057e2 <HAL_UART_IRQHandler+0x13a>
      if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
 8005714:	0695      	lsls	r5, r2, #26
 8005716:	d504      	bpl.n	8005722 <HAL_UART_IRQHandler+0x7a>
 8005718:	0688      	lsls	r0, r1, #26
 800571a:	d502      	bpl.n	8005722 <HAL_UART_IRQHandler+0x7a>
        UART_Receive_IT(huart);
 800571c:	4620      	mov	r0, r4
 800571e:	f7ff ff83 	bl	8005628 <UART_Receive_IT>
      dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
 8005722:	6823      	ldr	r3, [r4, #0]
        UART_EndRxTransfer(huart);
 8005724:	4620      	mov	r0, r4
      dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
 8005726:	695d      	ldr	r5, [r3, #20]
      if(((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest)
 8005728:	6be2      	ldr	r2, [r4, #60]	; 0x3c
 800572a:	0711      	lsls	r1, r2, #28
 800572c:	d402      	bmi.n	8005734 <HAL_UART_IRQHandler+0x8c>
 800572e:	f015 0540 	ands.w	r5, r5, #64	; 0x40
 8005732:	d01a      	beq.n	800576a <HAL_UART_IRQHandler+0xc2>
        UART_EndRxTransfer(huart);
 8005734:	f7ff fe18 	bl	8005368 <UART_EndRxTransfer>
        if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
 8005738:	6823      	ldr	r3, [r4, #0]
 800573a:	695a      	ldr	r2, [r3, #20]
 800573c:	0652      	lsls	r2, r2, #25
 800573e:	d510      	bpl.n	8005762 <HAL_UART_IRQHandler+0xba>
          CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
 8005740:	695a      	ldr	r2, [r3, #20]
          if(huart->hdmarx != NULL)
 8005742:	6b60      	ldr	r0, [r4, #52]	; 0x34
          CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
 8005744:	f022 0240 	bic.w	r2, r2, #64	; 0x40
 8005748:	615a      	str	r2, [r3, #20]
          if(huart->hdmarx != NULL)
 800574a:	b150      	cbz	r0, 8005762 <HAL_UART_IRQHandler+0xba>
            huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
 800574c:	4b25      	ldr	r3, [pc, #148]	; (80057e4 <HAL_UART_IRQHandler+0x13c>)
 800574e:	6343      	str	r3, [r0, #52]	; 0x34
            if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
 8005750:	f7fe ff88 	bl	8004664 <HAL_DMA_Abort_IT>
 8005754:	2800      	cmp	r0, #0
 8005756:	d044      	beq.n	80057e2 <HAL_UART_IRQHandler+0x13a>
              huart->hdmarx->XferAbortCallback(huart->hdmarx);
 8005758:	6b60      	ldr	r0, [r4, #52]	; 0x34
}
 800575a:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
              huart->hdmarx->XferAbortCallback(huart->hdmarx);
 800575e:	6b43      	ldr	r3, [r0, #52]	; 0x34
 8005760:	4718      	bx	r3
            HAL_UART_ErrorCallback(huart);
 8005762:	4620      	mov	r0, r4
 8005764:	f7ff ff9e 	bl	80056a4 <HAL_UART_ErrorCallback>
 8005768:	bd70      	pop	{r4, r5, r6, pc}
        HAL_UART_ErrorCallback(huart);
 800576a:	f7ff ff9b 	bl	80056a4 <HAL_UART_ErrorCallback>
        huart->ErrorCode = HAL_UART_ERROR_NONE;
 800576e:	63e5      	str	r5, [r4, #60]	; 0x3c
 8005770:	bd70      	pop	{r4, r5, r6, pc}
  if(((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
 8005772:	0616      	lsls	r6, r2, #24
 8005774:	d527      	bpl.n	80057c6 <HAL_UART_IRQHandler+0x11e>
 8005776:	060d      	lsls	r5, r1, #24
 8005778:	d525      	bpl.n	80057c6 <HAL_UART_IRQHandler+0x11e>
  if(huart->gState == HAL_UART_STATE_BUSY_TX)
 800577a:	f894 2039 	ldrb.w	r2, [r4, #57]	; 0x39
 800577e:	2a21      	cmp	r2, #33	; 0x21
 8005780:	d12f      	bne.n	80057e2 <HAL_UART_IRQHandler+0x13a>
    if(huart->Init.WordLength == UART_WORDLENGTH_9B)
 8005782:	68a2      	ldr	r2, [r4, #8]
 8005784:	f5b2 5f80 	cmp.w	r2, #4096	; 0x1000
 8005788:	6a22      	ldr	r2, [r4, #32]
 800578a:	d117      	bne.n	80057bc <HAL_UART_IRQHandler+0x114>
      huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
 800578c:	8811      	ldrh	r1, [r2, #0]
 800578e:	f3c1 0108 	ubfx	r1, r1, #0, #9
 8005792:	6059      	str	r1, [r3, #4]
      if(huart->Init.Parity == UART_PARITY_NONE)
 8005794:	6921      	ldr	r1, [r4, #16]
 8005796:	b979      	cbnz	r1, 80057b8 <HAL_UART_IRQHandler+0x110>
        huart->pTxBuffPtr += 2U;
 8005798:	3202      	adds	r2, #2
        huart->pTxBuffPtr += 1U;
 800579a:	6222      	str	r2, [r4, #32]
    if(--huart->TxXferCount == 0U)
 800579c:	8ce2      	ldrh	r2, [r4, #38]	; 0x26
 800579e:	3a01      	subs	r2, #1
 80057a0:	b292      	uxth	r2, r2
 80057a2:	84e2      	strh	r2, [r4, #38]	; 0x26
 80057a4:	b9ea      	cbnz	r2, 80057e2 <HAL_UART_IRQHandler+0x13a>
      __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
 80057a6:	68da      	ldr	r2, [r3, #12]
 80057a8:	f022 0280 	bic.w	r2, r2, #128	; 0x80
 80057ac:	60da      	str	r2, [r3, #12]
      __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
 80057ae:	68da      	ldr	r2, [r3, #12]
 80057b0:	f042 0240 	orr.w	r2, r2, #64	; 0x40
 80057b4:	60da      	str	r2, [r3, #12]
 80057b6:	bd70      	pop	{r4, r5, r6, pc}
        huart->pTxBuffPtr += 1U;
 80057b8:	3201      	adds	r2, #1
 80057ba:	e7ee      	b.n	800579a <HAL_UART_IRQHandler+0xf2>
      huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF);
 80057bc:	1c51      	adds	r1, r2, #1
 80057be:	6221      	str	r1, [r4, #32]
 80057c0:	7812      	ldrb	r2, [r2, #0]
 80057c2:	605a      	str	r2, [r3, #4]
 80057c4:	e7ea      	b.n	800579c <HAL_UART_IRQHandler+0xf4>
  if(((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
 80057c6:	0650      	lsls	r0, r2, #25
 80057c8:	d50b      	bpl.n	80057e2 <HAL_UART_IRQHandler+0x13a>
 80057ca:	064a      	lsls	r2, r1, #25
 80057cc:	d509      	bpl.n	80057e2 <HAL_UART_IRQHandler+0x13a>
  __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
 80057ce:	68da      	ldr	r2, [r3, #12]
  HAL_UART_TxCpltCallback(huart);
 80057d0:	4620      	mov	r0, r4
  __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
 80057d2:	f022 0240 	bic.w	r2, r2, #64	; 0x40
 80057d6:	60da      	str	r2, [r3, #12]
  huart->gState = HAL_UART_STATE_READY;
 80057d8:	2320      	movs	r3, #32
 80057da:	f884 3039 	strb.w	r3, [r4, #57]	; 0x39
  HAL_UART_TxCpltCallback(huart);
 80057de:	f7ff ff21 	bl	8005624 <HAL_UART_TxCpltCallback>
 80057e2:	bd70      	pop	{r4, r5, r6, pc}
 80057e4:	080057e9 	.word	0x080057e9

080057e8 <UART_DMAAbortOnError>:
{
 80057e8:	b508      	push	{r3, lr}
  huart->RxXferCount = 0x00U;
 80057ea:	2300      	movs	r3, #0
  UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
 80057ec:	6a40      	ldr	r0, [r0, #36]	; 0x24
  huart->RxXferCount = 0x00U;
 80057ee:	85c3      	strh	r3, [r0, #46]	; 0x2e
  huart->TxXferCount = 0x00U;
 80057f0:	84c3      	strh	r3, [r0, #38]	; 0x26
  HAL_UART_ErrorCallback(huart);
 80057f2:	f7ff ff57 	bl	80056a4 <HAL_UART_ErrorCallback>
 80057f6:	bd08      	pop	{r3, pc}

080057f8 <HAL_TIM_PeriodElapsedCallback>:
__IO uint32_t ADCvalue[ADC_EA];
#if 1 // PYJ.2019.07.26_BEGIN --

void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
    if(htim->Instance == TIM6){
 80057f8:	6802      	ldr	r2, [r0, #0]
 80057fa:	4b08      	ldr	r3, [pc, #32]	; (800581c <HAL_TIM_PeriodElapsedCallback+0x24>)
 80057fc:	429a      	cmp	r2, r3
 80057fe:	d10b      	bne.n	8005818 <HAL_TIM_PeriodElapsedCallback+0x20>
        UartTimerCnt++;
 8005800:	4a07      	ldr	r2, [pc, #28]	; (8005820 <HAL_TIM_PeriodElapsedCallback+0x28>)
 8005802:	6813      	ldr	r3, [r2, #0]
 8005804:	3301      	adds	r3, #1
 8005806:	6013      	str	r3, [r2, #0]
        LedTimerCnt++;
 8005808:	4a06      	ldr	r2, [pc, #24]	; (8005824 <HAL_TIM_PeriodElapsedCallback+0x2c>)
 800580a:	6813      	ldr	r3, [r2, #0]
 800580c:	3301      	adds	r3, #1
 800580e:	6013      	str	r3, [r2, #0]
        FirmwareTimerCnt++;
 8005810:	4a05      	ldr	r2, [pc, #20]	; (8005828 <HAL_TIM_PeriodElapsedCallback+0x30>)
 8005812:	6813      	ldr	r3, [r2, #0]
 8005814:	3301      	adds	r3, #1
 8005816:	6013      	str	r3, [r2, #0]
 8005818:	4770      	bx	lr
 800581a:	bf00      	nop
 800581c:	40001000 	.word	0x40001000
 8005820:	20000094 	.word	0x20000094
 8005824:	20000090 	.word	0x20000090
 8005828:	2000008c 	.word	0x2000008c

0800582c <_write>:
    }
} 
#endif // PYJ.2019.07.26_END -- 
int _write (int file, uint8_t *ptr, uint16_t len)
{
 800582c:	b510      	push	{r4, lr}
 800582e:	4614      	mov	r4, r2
    HAL_UART_Transmit (&huart1, ptr, len, 10);
 8005830:	230a      	movs	r3, #10
 8005832:	4802      	ldr	r0, [pc, #8]	; (800583c <_write+0x10>)
 8005834:	f7ff fe9a 	bl	800556c <HAL_UART_Transmit>
    return len;
}
 8005838:	4620      	mov	r0, r4
 800583a:	bd10      	pop	{r4, pc}
 800583c:	200000d8 	.word	0x200000d8

08005840 <SystemClock_Config>:
/**
  * @brief System Clock Configuration
  * @retval None
  */
void SystemClock_Config(void)
{
 8005840:	b510      	push	{r4, lr}
 8005842:	b096      	sub	sp, #88	; 0x58
  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
 8005844:	2228      	movs	r2, #40	; 0x28
 8005846:	2100      	movs	r1, #0
 8005848:	a80c      	add	r0, sp, #48	; 0x30
 800584a:	f000 fb97 	bl	8005f7c <memset>
  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 800584e:	2214      	movs	r2, #20
 8005850:	2100      	movs	r1, #0
 8005852:	a801      	add	r0, sp, #4
 8005854:	f000 fb92 	bl	8005f7c <memset>
  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 8005858:	2218      	movs	r2, #24
 800585a:	2100      	movs	r1, #0
 800585c:	eb0d 0002 	add.w	r0, sp, r2
 8005860:	f000 fb8c 	bl	8005f7c <memset>

  /** Initializes the CPU, AHB and APB busses clocks 
  */
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
 8005864:	2301      	movs	r3, #1
 8005866:	9310      	str	r3, [sp, #64]	; 0x40
  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
 8005868:	2310      	movs	r3, #16
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
 800586a:	2402      	movs	r4, #2
  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
 800586c:	9311      	str	r3, [sp, #68]	; 0x44
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2;
  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL15;
 800586e:	f44f 1350 	mov.w	r3, #3407872	; 0x340000
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 8005872:	a80c      	add	r0, sp, #48	; 0x30
  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL15;
 8005874:	9315      	str	r3, [sp, #84]	; 0x54
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
 8005876:	940c      	str	r4, [sp, #48]	; 0x30
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
 8005878:	9413      	str	r4, [sp, #76]	; 0x4c
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 800587a:	f7ff f933 	bl	8004ae4 <HAL_RCC_OscConfig>
  {
    Error_Handler();
  }
  /** Initializes the CPU, AHB and APB busses clocks 
  */
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
 800587e:	230f      	movs	r3, #15
                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
 8005880:	f44f 6280 	mov.w	r2, #1024	; 0x400
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
 8005884:	9301      	str	r3, [sp, #4]
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
 8005886:	2300      	movs	r3, #0
  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;

  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
 8005888:	4621      	mov	r1, r4
 800588a:	a801      	add	r0, sp, #4
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
 800588c:	9303      	str	r3, [sp, #12]
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
 800588e:	9204      	str	r2, [sp, #16]
  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
 8005890:	9305      	str	r3, [sp, #20]
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
 8005892:	9402      	str	r4, [sp, #8]
  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
 8005894:	f7ff faee 	bl	8004e74 <HAL_RCC_ClockConfig>
  {
    Error_Handler();
  }
  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
  PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6;
 8005898:	f44f 4300 	mov.w	r3, #32768	; 0x8000
  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
 800589c:	a806      	add	r0, sp, #24
  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
 800589e:	9406      	str	r4, [sp, #24]
  PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6;
 80058a0:	9308      	str	r3, [sp, #32]
  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
 80058a2:	f7ff fbb9 	bl	8005018 <HAL_RCCEx_PeriphCLKConfig>
  {
    Error_Handler();
  }
}
 80058a6:	b016      	add	sp, #88	; 0x58
 80058a8:	bd10      	pop	{r4, pc}
	...

080058ac <main>:
{
 80058ac:	b580      	push	{r7, lr}
static void MX_GPIO_Init(void)
{
  GPIO_InitTypeDef GPIO_InitStruct = {0};

  /* GPIO Ports Clock Enable */
  __HAL_RCC_GPIOE_CLK_ENABLE();
 80058ae:	4db1      	ldr	r5, [pc, #708]	; (8005b74 <main+0x2c8>)
{
 80058b0:	b08c      	sub	sp, #48	; 0x30
  HAL_Init();
 80058b2:	f7fe fcdb 	bl	800426c <HAL_Init>
  SystemClock_Config();
 80058b6:	f7ff ffc3 	bl	8005840 <SystemClock_Config>
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 80058ba:	2210      	movs	r2, #16
 80058bc:	2100      	movs	r1, #0
 80058be:	a808      	add	r0, sp, #32
 80058c0:	f000 fb5c 	bl	8005f7c <memset>
  __HAL_RCC_GPIOE_CLK_ENABLE();
 80058c4:	69ab      	ldr	r3, [r5, #24]
  __HAL_RCC_GPIOB_CLK_ENABLE();
  __HAL_RCC_GPIOD_CLK_ENABLE();
  __HAL_RCC_GPIOG_CLK_ENABLE();

  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(GPIOE, ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin 
 80058c6:	2200      	movs	r2, #0
  __HAL_RCC_GPIOE_CLK_ENABLE();
 80058c8:	f043 0340 	orr.w	r3, r3, #64	; 0x40
 80058cc:	61ab      	str	r3, [r5, #24]
 80058ce:	69ab      	ldr	r3, [r5, #24]
  HAL_GPIO_WritePin(GPIOE, ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin 
 80058d0:	217f      	movs	r1, #127	; 0x7f
  __HAL_RCC_GPIOE_CLK_ENABLE();
 80058d2:	f003 0340 	and.w	r3, r3, #64	; 0x40
 80058d6:	9301      	str	r3, [sp, #4]
 80058d8:	9b01      	ldr	r3, [sp, #4]
  __HAL_RCC_GPIOC_CLK_ENABLE();
 80058da:	69ab      	ldr	r3, [r5, #24]
  HAL_GPIO_WritePin(GPIOE, ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin 
 80058dc:	48a6      	ldr	r0, [pc, #664]	; (8005b78 <main+0x2cc>)
  __HAL_RCC_GPIOC_CLK_ENABLE();
 80058de:	f043 0310 	orr.w	r3, r3, #16
 80058e2:	61ab      	str	r3, [r5, #24]
 80058e4:	69ab      	ldr	r3, [r5, #24]
  /*Configure GPIO pins : ATT_EN_1_8G_DL1_Pin ATT_EN_1_8G_DL2_Pin ATT_EN_1_8G_UL1_Pin ATT_EN_1_8G_UL2_Pin 
                           ATT_EN_1_8G_UL3_Pin PATH_EN_2_1G_DL_Pin PATH_EN_2_1G_UL_Pin */
  GPIO_InitStruct.Pin = ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin 
                          |ATT_EN_1_8G_UL3_Pin|PATH_EN_2_1G_DL_Pin|PATH_EN_2_1G_UL_Pin;
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 80058e6:	2400      	movs	r4, #0
  __HAL_RCC_GPIOC_CLK_ENABLE();
 80058e8:	f003 0310 	and.w	r3, r3, #16
 80058ec:	9302      	str	r3, [sp, #8]
 80058ee:	9b02      	ldr	r3, [sp, #8]
  __HAL_RCC_GPIOF_CLK_ENABLE();
 80058f0:	69ab      	ldr	r3, [r5, #24]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 80058f2:	2601      	movs	r6, #1
  __HAL_RCC_GPIOF_CLK_ENABLE();
 80058f4:	f043 0380 	orr.w	r3, r3, #128	; 0x80
 80058f8:	61ab      	str	r3, [r5, #24]
 80058fa:	69ab      	ldr	r3, [r5, #24]
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 80058fc:	2702      	movs	r7, #2
  __HAL_RCC_GPIOF_CLK_ENABLE();
 80058fe:	f003 0380 	and.w	r3, r3, #128	; 0x80
 8005902:	9303      	str	r3, [sp, #12]
 8005904:	9b03      	ldr	r3, [sp, #12]
  __HAL_RCC_GPIOA_CLK_ENABLE();
 8005906:	69ab      	ldr	r3, [r5, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
  HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);

  /*Configure GPIO pins : PLL_LD_1_8G_DL_Pin PLL_LD_1_8G_UL_Pin */
  GPIO_InitStruct.Pin = PLL_LD_1_8G_DL_Pin|PLL_LD_1_8G_UL_Pin;
 8005908:	f04f 080c 	mov.w	r8, #12
  __HAL_RCC_GPIOA_CLK_ENABLE();
 800590c:	f043 0304 	orr.w	r3, r3, #4
 8005910:	61ab      	str	r3, [r5, #24]
 8005912:	69ab      	ldr	r3, [r5, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);

  /*Configure GPIO pin : PATH_EN_3_5G_H_Pin */
  GPIO_InitStruct.Pin = PATH_EN_3_5G_H_Pin;
  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
 8005914:	f04f 0903 	mov.w	r9, #3
  __HAL_RCC_GPIOA_CLK_ENABLE();
 8005918:	f003 0304 	and.w	r3, r3, #4
 800591c:	9304      	str	r3, [sp, #16]
 800591e:	9b04      	ldr	r3, [sp, #16]
  __HAL_RCC_GPIOB_CLK_ENABLE();
 8005920:	69ab      	ldr	r3, [r5, #24]
  hadc1.Init.NbrOfConversion = 14;
 8005922:	f04f 0a0e 	mov.w	sl, #14
  __HAL_RCC_GPIOB_CLK_ENABLE();
 8005926:	f043 0308 	orr.w	r3, r3, #8
 800592a:	61ab      	str	r3, [r5, #24]
 800592c:	69ab      	ldr	r3, [r5, #24]
 800592e:	f003 0308 	and.w	r3, r3, #8
 8005932:	9305      	str	r3, [sp, #20]
 8005934:	9b05      	ldr	r3, [sp, #20]
  __HAL_RCC_GPIOD_CLK_ENABLE();
 8005936:	69ab      	ldr	r3, [r5, #24]
 8005938:	f043 0320 	orr.w	r3, r3, #32
 800593c:	61ab      	str	r3, [r5, #24]
 800593e:	69ab      	ldr	r3, [r5, #24]
 8005940:	f003 0320 	and.w	r3, r3, #32
 8005944:	9306      	str	r3, [sp, #24]
 8005946:	9b06      	ldr	r3, [sp, #24]
  __HAL_RCC_GPIOG_CLK_ENABLE();
 8005948:	69ab      	ldr	r3, [r5, #24]
 800594a:	f443 7380 	orr.w	r3, r3, #256	; 0x100
 800594e:	61ab      	str	r3, [r5, #24]
 8005950:	69ab      	ldr	r3, [r5, #24]
 8005952:	f403 7380 	and.w	r3, r3, #256	; 0x100
 8005956:	9307      	str	r3, [sp, #28]
 8005958:	9b07      	ldr	r3, [sp, #28]
  HAL_GPIO_WritePin(GPIOE, ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin 
 800595a:	f7ff f8b9 	bl	8004ad0 <HAL_GPIO_WritePin>
  HAL_GPIO_WritePin(GPIOC, ATT_EN_1_8G_UL4_Pin|PATH_EN_1_8G_DL_Pin|PATH_EN_1_8G_UL_Pin|PLL_EN_3_5G_L_Pin 
 800595e:	2200      	movs	r2, #0
 8005960:	f24e 01c0 	movw	r1, #57536	; 0xe0c0
 8005964:	4885      	ldr	r0, [pc, #532]	; (8005b7c <main+0x2d0>)
 8005966:	f7ff f8b3 	bl	8004ad0 <HAL_GPIO_WritePin>
  HAL_GPIO_WritePin(GPIOF, PLL_EN_1_8G_DL_Pin|PLL_EN_1_8G_UL_Pin|ATT_EN_2_1G_DL1_Pin|ATT_EN_2_1G_DL2_Pin 
 800596a:	2200      	movs	r2, #0
 800596c:	f240 31f3 	movw	r1, #1011	; 0x3f3
 8005970:	4883      	ldr	r0, [pc, #524]	; (8005b80 <main+0x2d4>)
 8005972:	f7ff f8ad 	bl	8004ad0 <HAL_GPIO_WritePin>
  HAL_GPIO_WritePin(GPIOD, PLL_DATA_Pin|PLL_CLK_Pin|ATT_DATA_Pin|ATT_CLK_Pin 
 8005976:	2200      	movs	r2, #0
 8005978:	f648 71ff 	movw	r1, #36863	; 0x8fff
 800597c:	4881      	ldr	r0, [pc, #516]	; (8005b84 <main+0x2d8>)
 800597e:	f7ff f8a7 	bl	8004ad0 <HAL_GPIO_WritePin>
  HAL_GPIO_WritePin(GPIOG, DA_SYNC_Pin|DA_SCLK_Pin|DA_DIN_Pin|_T_SYNC_UL_Pin 
 8005982:	2200      	movs	r2, #0
 8005984:	f647 51fc 	movw	r1, #32252	; 0x7dfc
 8005988:	487f      	ldr	r0, [pc, #508]	; (8005b88 <main+0x2dc>)
 800598a:	f7ff f8a1 	bl	8004ad0 <HAL_GPIO_WritePin>
  HAL_GPIO_WritePin(GPIOB, PLL_EN_2_1G_DL_Pin|PLL_EN_2_1G_UL_Pin, GPIO_PIN_RESET);
 800598e:	2200      	movs	r2, #0
 8005990:	2118      	movs	r1, #24
 8005992:	487e      	ldr	r0, [pc, #504]	; (8005b8c <main+0x2e0>)
 8005994:	f7ff f89c 	bl	8004ad0 <HAL_GPIO_WritePin>
  GPIO_InitStruct.Pin = ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin 
 8005998:	237f      	movs	r3, #127	; 0x7f
  HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
 800599a:	a908      	add	r1, sp, #32
 800599c:	4876      	ldr	r0, [pc, #472]	; (8005b78 <main+0x2cc>)
  GPIO_InitStruct.Pin = ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin 
 800599e:	9308      	str	r3, [sp, #32]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 80059a0:	9609      	str	r6, [sp, #36]	; 0x24
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 80059a2:	940a      	str	r4, [sp, #40]	; 0x28
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 80059a4:	970b      	str	r7, [sp, #44]	; 0x2c
  HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
 80059a6:	f7fe ffa7 	bl	80048f8 <HAL_GPIO_Init>
  GPIO_InitStruct.Pin = ATT_EN_1_8G_UL4_Pin|PATH_EN_1_8G_DL_Pin|PATH_EN_1_8G_UL_Pin|PLL_EN_3_5G_L_Pin 
 80059aa:	f24e 03c0 	movw	r3, #57536	; 0xe0c0
  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 80059ae:	a908      	add	r1, sp, #32
 80059b0:	4872      	ldr	r0, [pc, #456]	; (8005b7c <main+0x2d0>)
  GPIO_InitStruct.Pin = ATT_EN_1_8G_UL4_Pin|PATH_EN_1_8G_DL_Pin|PATH_EN_1_8G_UL_Pin|PLL_EN_3_5G_L_Pin 
 80059b2:	9308      	str	r3, [sp, #32]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 80059b4:	9609      	str	r6, [sp, #36]	; 0x24
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 80059b6:	940a      	str	r4, [sp, #40]	; 0x28
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 80059b8:	970b      	str	r7, [sp, #44]	; 0x2c
  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 80059ba:	f7fe ff9d 	bl	80048f8 <HAL_GPIO_Init>
  GPIO_InitStruct.Pin = PLL_EN_1_8G_DL_Pin|PLL_EN_1_8G_UL_Pin|ATT_EN_2_1G_DL1_Pin|ATT_EN_2_1G_DL2_Pin 
 80059be:	f240 33f3 	movw	r3, #1011	; 0x3f3
  HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
 80059c2:	a908      	add	r1, sp, #32
 80059c4:	486e      	ldr	r0, [pc, #440]	; (8005b80 <main+0x2d4>)
  GPIO_InitStruct.Pin = PLL_EN_1_8G_DL_Pin|PLL_EN_1_8G_UL_Pin|ATT_EN_2_1G_DL1_Pin|ATT_EN_2_1G_DL2_Pin 
 80059c6:	9308      	str	r3, [sp, #32]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 80059c8:	9609      	str	r6, [sp, #36]	; 0x24
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 80059ca:	940a      	str	r4, [sp, #40]	; 0x28
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 80059cc:	970b      	str	r7, [sp, #44]	; 0x2c
  HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
 80059ce:	f7fe ff93 	bl	80048f8 <HAL_GPIO_Init>
  HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
 80059d2:	a908      	add	r1, sp, #32
 80059d4:	486a      	ldr	r0, [pc, #424]	; (8005b80 <main+0x2d4>)
  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
 80059d6:	9409      	str	r4, [sp, #36]	; 0x24
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 80059d8:	940a      	str	r4, [sp, #40]	; 0x28
  GPIO_InitStruct.Pin = PLL_LD_1_8G_DL_Pin|PLL_LD_1_8G_UL_Pin;
 80059da:	f8cd 8020 	str.w	r8, [sp, #32]
  HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
 80059de:	f7fe ff8b 	bl	80048f8 <HAL_GPIO_Init>
  GPIO_InitStruct.Pin = PLL_DATA_Pin|PLL_CLK_Pin|ATT_DATA_Pin|ATT_CLK_Pin 
 80059e2:	f648 73ff 	movw	r3, #36863	; 0x8fff
  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
 80059e6:	a908      	add	r1, sp, #32
 80059e8:	4866      	ldr	r0, [pc, #408]	; (8005b84 <main+0x2d8>)
  GPIO_InitStruct.Pin = PLL_DATA_Pin|PLL_CLK_Pin|ATT_DATA_Pin|ATT_CLK_Pin 
 80059ea:	9308      	str	r3, [sp, #32]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 80059ec:	9609      	str	r6, [sp, #36]	; 0x24
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 80059ee:	940a      	str	r4, [sp, #40]	; 0x28
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 80059f0:	970b      	str	r7, [sp, #44]	; 0x2c
  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
 80059f2:	f7fe ff81 	bl	80048f8 <HAL_GPIO_Init>
  GPIO_InitStruct.Pin = ALARM_DC_Pin|ALARM_AC_Pin;
 80059f6:	f44f 5340 	mov.w	r3, #12288	; 0x3000
  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
 80059fa:	a908      	add	r1, sp, #32
 80059fc:	4861      	ldr	r0, [pc, #388]	; (8005b84 <main+0x2d8>)
  GPIO_InitStruct.Pin = ALARM_DC_Pin|ALARM_AC_Pin;
 80059fe:	9308      	str	r3, [sp, #32]
  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
 8005a00:	9409      	str	r4, [sp, #36]	; 0x24
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8005a02:	940a      	str	r4, [sp, #40]	; 0x28
  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
 8005a04:	f7fe ff78 	bl	80048f8 <HAL_GPIO_Init>
  GPIO_InitStruct.Pin = DA_SYNC_Pin|DA_SCLK_Pin|DA_DIN_Pin|_T_SYNC_UL_Pin 
 8005a08:	f647 53fc 	movw	r3, #32252	; 0x7dfc
  HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
 8005a0c:	a908      	add	r1, sp, #32
 8005a0e:	485e      	ldr	r0, [pc, #376]	; (8005b88 <main+0x2dc>)
  GPIO_InitStruct.Pin = DA_SYNC_Pin|DA_SCLK_Pin|DA_DIN_Pin|_T_SYNC_UL_Pin 
 8005a10:	9308      	str	r3, [sp, #32]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 8005a12:	9609      	str	r6, [sp, #36]	; 0x24
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8005a14:	940a      	str	r4, [sp, #40]	; 0x28
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8005a16:	970b      	str	r7, [sp, #44]	; 0x2c
  HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
 8005a18:	f7fe ff6e 	bl	80048f8 <HAL_GPIO_Init>
  GPIO_InitStruct.Pin = PLL_LD_3_5G_L_Pin|PLL_LD_3_5G_H_Pin;
 8005a1c:	f44f 7340 	mov.w	r3, #768	; 0x300
  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 8005a20:	a908      	add	r1, sp, #32
 8005a22:	4856      	ldr	r0, [pc, #344]	; (8005b7c <main+0x2d0>)
  GPIO_InitStruct.Pin = PLL_LD_3_5G_L_Pin|PLL_LD_3_5G_H_Pin;
 8005a24:	9308      	str	r3, [sp, #32]
  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
 8005a26:	9409      	str	r4, [sp, #36]	; 0x24
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8005a28:	940a      	str	r4, [sp, #40]	; 0x28
  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 8005a2a:	f7fe ff65 	bl	80048f8 <HAL_GPIO_Init>
  GPIO_InitStruct.Pin = PATH_EN_3_5G_H_Pin;
 8005a2e:	f44f 7300 	mov.w	r3, #512	; 0x200
  HAL_GPIO_Init(PATH_EN_3_5G_H_GPIO_Port, &GPIO_InitStruct);
 8005a32:	a908      	add	r1, sp, #32
 8005a34:	4854      	ldr	r0, [pc, #336]	; (8005b88 <main+0x2dc>)
  GPIO_InitStruct.Pin = PATH_EN_3_5G_H_Pin;
 8005a36:	9308      	str	r3, [sp, #32]
  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
 8005a38:	f8cd 9024 	str.w	r9, [sp, #36]	; 0x24
  HAL_GPIO_Init(PATH_EN_3_5G_H_GPIO_Port, &GPIO_InitStruct);
 8005a3c:	f7fe ff5c 	bl	80048f8 <HAL_GPIO_Init>

  /*Configure GPIO pins : PLL_EN_2_1G_DL_Pin PLL_EN_2_1G_UL_Pin */
  GPIO_InitStruct.Pin = PLL_EN_2_1G_DL_Pin|PLL_EN_2_1G_UL_Pin;
 8005a40:	2318      	movs	r3, #24
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  GPIO_InitStruct.Pull = GPIO_NOPULL;
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8005a42:	a908      	add	r1, sp, #32
 8005a44:	4851      	ldr	r0, [pc, #324]	; (8005b8c <main+0x2e0>)
  GPIO_InitStruct.Pin = PLL_EN_2_1G_DL_Pin|PLL_EN_2_1G_UL_Pin;
 8005a46:	9308      	str	r3, [sp, #32]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 8005a48:	9609      	str	r6, [sp, #36]	; 0x24
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8005a4a:	940a      	str	r4, [sp, #40]	; 0x28
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8005a4c:	970b      	str	r7, [sp, #44]	; 0x2c
  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8005a4e:	f7fe ff53 	bl	80048f8 <HAL_GPIO_Init>

  /*Configure GPIO pins : PLL_LD_2_1G_DL_Pin PLL_LD_2_1G_UL_Pin */
  GPIO_InitStruct.Pin = PLL_LD_2_1G_DL_Pin|PLL_LD_2_1G_UL_Pin;
 8005a52:	2360      	movs	r3, #96	; 0x60
  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
  GPIO_InitStruct.Pull = GPIO_NOPULL;
  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8005a54:	a908      	add	r1, sp, #32
 8005a56:	484d      	ldr	r0, [pc, #308]	; (8005b8c <main+0x2e0>)
  GPIO_InitStruct.Pin = PLL_LD_2_1G_DL_Pin|PLL_LD_2_1G_UL_Pin;
 8005a58:	9308      	str	r3, [sp, #32]
  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
 8005a5a:	9409      	str	r4, [sp, #36]	; 0x24
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8005a5c:	940a      	str	r4, [sp, #40]	; 0x28
  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8005a5e:	f7fe ff4b 	bl	80048f8 <HAL_GPIO_Init>
  __HAL_RCC_DMA1_CLK_ENABLE();
 8005a62:	696b      	ldr	r3, [r5, #20]
  HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
 8005a64:	4622      	mov	r2, r4
  __HAL_RCC_DMA1_CLK_ENABLE();
 8005a66:	4333      	orrs	r3, r6
 8005a68:	616b      	str	r3, [r5, #20]
 8005a6a:	696b      	ldr	r3, [r5, #20]
  HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
 8005a6c:	4621      	mov	r1, r4
  __HAL_RCC_DMA1_CLK_ENABLE();
 8005a6e:	4033      	ands	r3, r6
 8005a70:	9300      	str	r3, [sp, #0]
  HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
 8005a72:	200b      	movs	r0, #11
  __HAL_RCC_DMA1_CLK_ENABLE();
 8005a74:	9b00      	ldr	r3, [sp, #0]
  HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
 8005a76:	f7fe fd5f 	bl	8004538 <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
 8005a7a:	200b      	movs	r0, #11
  hadc1.Instance = ADC1;
 8005a7c:	4d44      	ldr	r5, [pc, #272]	; (8005b90 <main+0x2e4>)
  HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
 8005a7e:	f7fe fd8f 	bl	80045a0 <HAL_NVIC_EnableIRQ>
  hadc1.Instance = ADC1;
 8005a82:	4b44      	ldr	r3, [pc, #272]	; (8005b94 <main+0x2e8>)
  if (HAL_ADC_Init(&hadc1) != HAL_OK)
 8005a84:	4628      	mov	r0, r5
  hadc1.Instance = ADC1;
 8005a86:	602b      	str	r3, [r5, #0]
  hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE;
 8005a88:	f44f 7380 	mov.w	r3, #256	; 0x100
 8005a8c:	60ab      	str	r3, [r5, #8]
  hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
 8005a8e:	f44f 2360 	mov.w	r3, #917504	; 0xe0000
  hadc1.Init.ContinuousConvMode = ENABLE;
 8005a92:	60ee      	str	r6, [r5, #12]
  hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
 8005a94:	61eb      	str	r3, [r5, #28]
  hadc1.Init.DiscontinuousConvMode = DISABLE;
 8005a96:	616c      	str	r4, [r5, #20]
  hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
 8005a98:	606c      	str	r4, [r5, #4]
  ADC_ChannelConfTypeDef sConfig = {0};
 8005a9a:	9408      	str	r4, [sp, #32]
 8005a9c:	9409      	str	r4, [sp, #36]	; 0x24
 8005a9e:	940a      	str	r4, [sp, #40]	; 0x28
  hadc1.Init.NbrOfConversion = 14;
 8005aa0:	f8c5 a010 	str.w	sl, [r5, #16]
  if (HAL_ADC_Init(&hadc1) != HAL_OK)
 8005aa4:	f7fe fcac 	bl	8004400 <HAL_ADC_Init>
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005aa8:	a908      	add	r1, sp, #32
 8005aaa:	4628      	mov	r0, r5
  sConfig.Channel = ADC_CHANNEL_0;
 8005aac:	9408      	str	r4, [sp, #32]
  sConfig.Rank = ADC_REGULAR_RANK_1;
 8005aae:	9609      	str	r6, [sp, #36]	; 0x24
  sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
 8005ab0:	940a      	str	r4, [sp, #40]	; 0x28
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005ab2:	f7fe fbff 	bl	80042b4 <HAL_ADC_ConfigChannel>
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005ab6:	a908      	add	r1, sp, #32
 8005ab8:	4628      	mov	r0, r5
  sConfig.Rank = ADC_REGULAR_RANK_2;
 8005aba:	9709      	str	r7, [sp, #36]	; 0x24
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005abc:	f7fe fbfa 	bl	80042b4 <HAL_ADC_ConfigChannel>
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005ac0:	a908      	add	r1, sp, #32
 8005ac2:	4628      	mov	r0, r5
  sConfig.Rank = ADC_REGULAR_RANK_3;
 8005ac4:	f8cd 9024 	str.w	r9, [sp, #36]	; 0x24
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005ac8:	f7fe fbf4 	bl	80042b4 <HAL_ADC_ConfigChannel>
  sConfig.Rank = ADC_REGULAR_RANK_4;
 8005acc:	2304      	movs	r3, #4
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005ace:	a908      	add	r1, sp, #32
 8005ad0:	4628      	mov	r0, r5
  sConfig.Rank = ADC_REGULAR_RANK_4;
 8005ad2:	9309      	str	r3, [sp, #36]	; 0x24
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005ad4:	f7fe fbee 	bl	80042b4 <HAL_ADC_ConfigChannel>
  sConfig.Rank = ADC_REGULAR_RANK_5;
 8005ad8:	2305      	movs	r3, #5
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005ada:	a908      	add	r1, sp, #32
 8005adc:	4628      	mov	r0, r5
  sConfig.Rank = ADC_REGULAR_RANK_5;
 8005ade:	9309      	str	r3, [sp, #36]	; 0x24
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005ae0:	f7fe fbe8 	bl	80042b4 <HAL_ADC_ConfigChannel>
  sConfig.Rank = ADC_REGULAR_RANK_6;
 8005ae4:	2306      	movs	r3, #6
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005ae6:	a908      	add	r1, sp, #32
 8005ae8:	4628      	mov	r0, r5
  sConfig.Rank = ADC_REGULAR_RANK_6;
 8005aea:	9309      	str	r3, [sp, #36]	; 0x24
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005aec:	f7fe fbe2 	bl	80042b4 <HAL_ADC_ConfigChannel>
  sConfig.Rank = ADC_REGULAR_RANK_7;
 8005af0:	2307      	movs	r3, #7
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005af2:	a908      	add	r1, sp, #32
 8005af4:	4628      	mov	r0, r5
  sConfig.Rank = ADC_REGULAR_RANK_7;
 8005af6:	9309      	str	r3, [sp, #36]	; 0x24
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005af8:	f7fe fbdc 	bl	80042b4 <HAL_ADC_ConfigChannel>
  sConfig.Rank = ADC_REGULAR_RANK_8;
 8005afc:	2308      	movs	r3, #8
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005afe:	a908      	add	r1, sp, #32
 8005b00:	4628      	mov	r0, r5
  sConfig.Rank = ADC_REGULAR_RANK_8;
 8005b02:	9309      	str	r3, [sp, #36]	; 0x24
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005b04:	f7fe fbd6 	bl	80042b4 <HAL_ADC_ConfigChannel>
  sConfig.Rank = ADC_REGULAR_RANK_9;
 8005b08:	2309      	movs	r3, #9
  sConfig.Rank = ADC_REGULAR_RANK_10;
 8005b0a:	260a      	movs	r6, #10
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005b0c:	a908      	add	r1, sp, #32
 8005b0e:	4628      	mov	r0, r5
  sConfig.Rank = ADC_REGULAR_RANK_9;
 8005b10:	9309      	str	r3, [sp, #36]	; 0x24
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005b12:	f7fe fbcf 	bl	80042b4 <HAL_ADC_ConfigChannel>
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005b16:	a908      	add	r1, sp, #32
 8005b18:	4628      	mov	r0, r5
  sConfig.Rank = ADC_REGULAR_RANK_10;
 8005b1a:	9609      	str	r6, [sp, #36]	; 0x24
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005b1c:	f7fe fbca 	bl	80042b4 <HAL_ADC_ConfigChannel>
  sConfig.Rank = ADC_REGULAR_RANK_11;
 8005b20:	230b      	movs	r3, #11
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005b22:	a908      	add	r1, sp, #32
 8005b24:	4628      	mov	r0, r5
  sConfig.Rank = ADC_REGULAR_RANK_11;
 8005b26:	9309      	str	r3, [sp, #36]	; 0x24
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005b28:	f7fe fbc4 	bl	80042b4 <HAL_ADC_ConfigChannel>
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005b2c:	a908      	add	r1, sp, #32
 8005b2e:	4628      	mov	r0, r5
  sConfig.Rank = ADC_REGULAR_RANK_12;
 8005b30:	f8cd 8024 	str.w	r8, [sp, #36]	; 0x24
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005b34:	f7fe fbbe 	bl	80042b4 <HAL_ADC_ConfigChannel>
  sConfig.Rank = ADC_REGULAR_RANK_13;
 8005b38:	230d      	movs	r3, #13
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005b3a:	a908      	add	r1, sp, #32
 8005b3c:	4628      	mov	r0, r5
  sConfig.Rank = ADC_REGULAR_RANK_13;
 8005b3e:	9309      	str	r3, [sp, #36]	; 0x24
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005b40:	f7fe fbb8 	bl	80042b4 <HAL_ADC_ConfigChannel>
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005b44:	a908      	add	r1, sp, #32
 8005b46:	4628      	mov	r0, r5
  sConfig.Rank = ADC_REGULAR_RANK_14;
 8005b48:	f8cd a024 	str.w	sl, [sp, #36]	; 0x24
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8005b4c:	f7fe fbb2 	bl	80042b4 <HAL_ADC_ConfigChannel>
  huart1.Init.BaudRate = 115200;
 8005b50:	f44f 33e1 	mov.w	r3, #115200	; 0x1c200
  huart1.Instance = USART1;
 8005b54:	4810      	ldr	r0, [pc, #64]	; (8005b98 <main+0x2ec>)
  huart1.Init.BaudRate = 115200;
 8005b56:	4a11      	ldr	r2, [pc, #68]	; (8005b9c <main+0x2f0>)
  huart1.Init.WordLength = UART_WORDLENGTH_8B;
 8005b58:	6084      	str	r4, [r0, #8]
  huart1.Init.BaudRate = 115200;
 8005b5a:	e880 000c 	stmia.w	r0, {r2, r3}
  huart1.Init.StopBits = UART_STOPBITS_1;
 8005b5e:	60c4      	str	r4, [r0, #12]
  huart1.Init.Parity = UART_PARITY_NONE;
 8005b60:	6104      	str	r4, [r0, #16]
  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
 8005b62:	6184      	str	r4, [r0, #24]
  huart1.Init.OverSampling = UART_OVERSAMPLING_16;
 8005b64:	61c4      	str	r4, [r0, #28]
  huart1.Init.Mode = UART_MODE_TX_RX;
 8005b66:	f8c0 8014 	str.w	r8, [r0, #20]
  if (HAL_UART_Init(&huart1) != HAL_OK)
 8005b6a:	f7ff fcd1 	bl	8005510 <HAL_UART_Init>
  htim6.Init.Prescaler = 6000-1;
 8005b6e:	f241 736f 	movw	r3, #5999	; 0x176f
 8005b72:	e015      	b.n	8005ba0 <main+0x2f4>
 8005b74:	40021000 	.word	0x40021000
 8005b78:	40011800 	.word	0x40011800
 8005b7c:	40011000 	.word	0x40011000
 8005b80:	40011c00 	.word	0x40011c00
 8005b84:	40011400 	.word	0x40011400
 8005b88:	40012000 	.word	0x40012000
 8005b8c:	40010c00 	.word	0x40010c00
 8005b90:	200000a8 	.word	0x200000a8
 8005b94:	40012400 	.word	0x40012400
 8005b98:	200000d8 	.word	0x200000d8
 8005b9c:	40013800 	.word	0x40013800
  htim6.Instance = TIM6;
 8005ba0:	4d1c      	ldr	r5, [pc, #112]	; (8005c14 <main+0x368>)
  htim6.Init.Prescaler = 6000-1;
 8005ba2:	491d      	ldr	r1, [pc, #116]	; (8005c18 <main+0x36c>)
  if (HAL_TIM_Base_Init(&htim6) != HAL_OK)
 8005ba4:	4628      	mov	r0, r5
  htim6.Init.Prescaler = 6000-1;
 8005ba6:	e885 000a 	stmia.w	r5, {r1, r3}
  htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
 8005baa:	60ac      	str	r4, [r5, #8]
  htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
 8005bac:	61ac      	str	r4, [r5, #24]
  TIM_MasterConfigTypeDef sMasterConfig = {0};
 8005bae:	9408      	str	r4, [sp, #32]
 8005bb0:	9409      	str	r4, [sp, #36]	; 0x24
  htim6.Init.Period = 10;
 8005bb2:	60ee      	str	r6, [r5, #12]
  if (HAL_TIM_Base_Init(&htim6) != HAL_OK)
 8005bb4:	f7ff fb9a 	bl	80052ec <HAL_TIM_Base_Init>
  if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK)
 8005bb8:	a908      	add	r1, sp, #32
 8005bba:	4628      	mov	r0, r5
  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
 8005bbc:	9408      	str	r4, [sp, #32]
  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
 8005bbe:	9409      	str	r4, [sp, #36]	; 0x24
  if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK)
 8005bc0:	f7ff fbae 	bl	8005320 <HAL_TIMEx_MasterConfigSynchronization>
  HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
 8005bc4:	4622      	mov	r2, r4
 8005bc6:	4621      	mov	r1, r4
 8005bc8:	2025      	movs	r0, #37	; 0x25
 8005bca:	f7fe fcb5 	bl	8004538 <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(USART1_IRQn);
 8005bce:	2025      	movs	r0, #37	; 0x25
 8005bd0:	f7fe fce6 	bl	80045a0 <HAL_NVIC_EnableIRQ>
  HAL_NVIC_SetPriority(TIM6_IRQn, 0, 0);
 8005bd4:	4622      	mov	r2, r4
 8005bd6:	4621      	mov	r1, r4
 8005bd8:	2036      	movs	r0, #54	; 0x36
 8005bda:	f7fe fcad 	bl	8004538 <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(TIM6_IRQn);
 8005bde:	2036      	movs	r0, #54	; 0x36
 8005be0:	f7fe fcde 	bl	80045a0 <HAL_NVIC_EnableIRQ>
  setbuf(stdout, NULL);
 8005be4:	4b0d      	ldr	r3, [pc, #52]	; (8005c1c <main+0x370>)
 8005be6:	4621      	mov	r1, r4
 8005be8:	681b      	ldr	r3, [r3, #0]
    if(LedTimerCnt > 500){HAL_GPIO_TogglePin(BOOT_LED_GPIO_Port,GPIO_PIN_14);LedTimerCnt = 0;}
 8005bea:	4c0d      	ldr	r4, [pc, #52]	; (8005c20 <main+0x374>)
  setbuf(stdout, NULL);
 8005bec:	6898      	ldr	r0, [r3, #8]
 8005bee:	f000 fa31 	bl	8006054 <setbuf>
  printf("UART Start \r\n");
 8005bf2:	480c      	ldr	r0, [pc, #48]	; (8005c24 <main+0x378>)
 8005bf4:	f000 fa26 	bl	8006044 <puts>
    if(LedTimerCnt > 500){HAL_GPIO_TogglePin(BOOT_LED_GPIO_Port,GPIO_PIN_14);LedTimerCnt = 0;}
 8005bf8:	4d0b      	ldr	r5, [pc, #44]	; (8005c28 <main+0x37c>)
 8005bfa:	6823      	ldr	r3, [r4, #0]
 8005bfc:	f5b3 7ffa 	cmp.w	r3, #500	; 0x1f4
 8005c00:	d9fb      	bls.n	8005bfa <main+0x34e>
 8005c02:	f44f 4180 	mov.w	r1, #16384	; 0x4000
 8005c06:	4628      	mov	r0, r5
 8005c08:	f7fe ff67 	bl	8004ada <HAL_GPIO_TogglePin>
 8005c0c:	2300      	movs	r3, #0
 8005c0e:	6023      	str	r3, [r4, #0]
 8005c10:	e7f3      	b.n	8005bfa <main+0x34e>
 8005c12:	bf00      	nop
 8005c14:	2000015c 	.word	0x2000015c
 8005c18:	40001000 	.word	0x40001000
 8005c1c:	2000000c 	.word	0x2000000c
 8005c20:	20000090 	.word	0x20000090
 8005c24:	08006a08 	.word	0x08006a08
 8005c28:	40012000 	.word	0x40012000

08005c2c <Error_Handler>:
/**
  * @brief  This function is executed in case of error occurrence.
  * @retval None
  */
void Error_Handler(void)
{
 8005c2c:	4770      	bx	lr
	...

08005c30 <HAL_MspInit>:
{
  /* USER CODE BEGIN MspInit 0 */

  /* USER CODE END MspInit 0 */

  __HAL_RCC_AFIO_CLK_ENABLE();
 8005c30:	4b0e      	ldr	r3, [pc, #56]	; (8005c6c <HAL_MspInit+0x3c>)
{
 8005c32:	b082      	sub	sp, #8
  __HAL_RCC_AFIO_CLK_ENABLE();
 8005c34:	699a      	ldr	r2, [r3, #24]
 8005c36:	f042 0201 	orr.w	r2, r2, #1
 8005c3a:	619a      	str	r2, [r3, #24]
 8005c3c:	699a      	ldr	r2, [r3, #24]
 8005c3e:	f002 0201 	and.w	r2, r2, #1
 8005c42:	9200      	str	r2, [sp, #0]
 8005c44:	9a00      	ldr	r2, [sp, #0]
  __HAL_RCC_PWR_CLK_ENABLE();
 8005c46:	69da      	ldr	r2, [r3, #28]
 8005c48:	f042 5280 	orr.w	r2, r2, #268435456	; 0x10000000
 8005c4c:	61da      	str	r2, [r3, #28]
 8005c4e:	69db      	ldr	r3, [r3, #28]

  /* System interrupt init*/

  /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled 
  */
  __HAL_AFIO_REMAP_SWJ_NOJTAG();
 8005c50:	4a07      	ldr	r2, [pc, #28]	; (8005c70 <HAL_MspInit+0x40>)
  __HAL_RCC_PWR_CLK_ENABLE();
 8005c52:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8005c56:	9301      	str	r3, [sp, #4]
 8005c58:	9b01      	ldr	r3, [sp, #4]
  __HAL_AFIO_REMAP_SWJ_NOJTAG();
 8005c5a:	6853      	ldr	r3, [r2, #4]
 8005c5c:	f023 63e0 	bic.w	r3, r3, #117440512	; 0x7000000
 8005c60:	f043 7300 	orr.w	r3, r3, #33554432	; 0x2000000
 8005c64:	6053      	str	r3, [r2, #4]

  /* USER CODE BEGIN MspInit 1 */

  /* USER CODE END MspInit 1 */
}
 8005c66:	b002      	add	sp, #8
 8005c68:	4770      	bx	lr
 8005c6a:	bf00      	nop
 8005c6c:	40021000 	.word	0x40021000
 8005c70:	40010000 	.word	0x40010000

08005c74 <HAL_ADC_MspInit>:
* @param hadc: ADC handle pointer
* @retval None
*/
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
{
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8005c74:	2210      	movs	r2, #16
{
 8005c76:	b530      	push	{r4, r5, lr}
 8005c78:	4605      	mov	r5, r0
 8005c7a:	b089      	sub	sp, #36	; 0x24
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8005c7c:	eb0d 0002 	add.w	r0, sp, r2
 8005c80:	2100      	movs	r1, #0
 8005c82:	f000 f97b 	bl	8005f7c <memset>
  if(hadc->Instance==ADC1)
 8005c86:	682a      	ldr	r2, [r5, #0]
 8005c88:	4b2b      	ldr	r3, [pc, #172]	; (8005d38 <HAL_ADC_MspInit+0xc4>)
 8005c8a:	429a      	cmp	r2, r3
 8005c8c:	d152      	bne.n	8005d34 <HAL_ADC_MspInit+0xc0>
  {
  /* USER CODE BEGIN ADC1_MspInit 0 */

  /* USER CODE END ADC1_MspInit 0 */
    /* Peripheral clock enable */
    __HAL_RCC_ADC1_CLK_ENABLE();
 8005c8e:	f503 436c 	add.w	r3, r3, #60416	; 0xec00
 8005c92:	699a      	ldr	r2, [r3, #24]
    PA7     ------> ADC1_IN7
    PB0     ------> ADC1_IN8
    PB1     ------> ADC1_IN9 
    */
    GPIO_InitStruct.Pin = DET_3_5G_UL_IN_Pin|DET_3_5G_UL_OUT_Pin|RFU_TEMP_Pin|_28V_DET_Pin;
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
 8005c94:	2403      	movs	r4, #3
    __HAL_RCC_ADC1_CLK_ENABLE();
 8005c96:	f442 7200 	orr.w	r2, r2, #512	; 0x200
 8005c9a:	619a      	str	r2, [r3, #24]
 8005c9c:	699a      	ldr	r2, [r3, #24]
    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 8005c9e:	a904      	add	r1, sp, #16
    __HAL_RCC_ADC1_CLK_ENABLE();
 8005ca0:	f402 7200 	and.w	r2, r2, #512	; 0x200
 8005ca4:	9200      	str	r2, [sp, #0]
 8005ca6:	9a00      	ldr	r2, [sp, #0]
    __HAL_RCC_GPIOC_CLK_ENABLE();
 8005ca8:	699a      	ldr	r2, [r3, #24]
    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 8005caa:	4824      	ldr	r0, [pc, #144]	; (8005d3c <HAL_ADC_MspInit+0xc8>)
    __HAL_RCC_GPIOC_CLK_ENABLE();
 8005cac:	f042 0210 	orr.w	r2, r2, #16
 8005cb0:	619a      	str	r2, [r3, #24]
 8005cb2:	699a      	ldr	r2, [r3, #24]
 8005cb4:	f002 0210 	and.w	r2, r2, #16
 8005cb8:	9201      	str	r2, [sp, #4]
 8005cba:	9a01      	ldr	r2, [sp, #4]
    __HAL_RCC_GPIOA_CLK_ENABLE();
 8005cbc:	699a      	ldr	r2, [r3, #24]
 8005cbe:	f042 0204 	orr.w	r2, r2, #4
 8005cc2:	619a      	str	r2, [r3, #24]
 8005cc4:	699a      	ldr	r2, [r3, #24]
 8005cc6:	f002 0204 	and.w	r2, r2, #4
 8005cca:	9202      	str	r2, [sp, #8]
 8005ccc:	9a02      	ldr	r2, [sp, #8]
    __HAL_RCC_GPIOB_CLK_ENABLE();
 8005cce:	699a      	ldr	r2, [r3, #24]
 8005cd0:	f042 0208 	orr.w	r2, r2, #8
 8005cd4:	619a      	str	r2, [r3, #24]
 8005cd6:	699b      	ldr	r3, [r3, #24]
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
 8005cd8:	9405      	str	r4, [sp, #20]
    __HAL_RCC_GPIOB_CLK_ENABLE();
 8005cda:	f003 0308 	and.w	r3, r3, #8
 8005cde:	9303      	str	r3, [sp, #12]
 8005ce0:	9b03      	ldr	r3, [sp, #12]
    GPIO_InitStruct.Pin = DET_3_5G_UL_IN_Pin|DET_3_5G_UL_OUT_Pin|RFU_TEMP_Pin|_28V_DET_Pin;
 8005ce2:	230f      	movs	r3, #15
 8005ce4:	9304      	str	r3, [sp, #16]
    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 8005ce6:	f7fe fe07 	bl	80048f8 <HAL_GPIO_Init>

    GPIO_InitStruct.Pin = DET_1_8G_DL_IN_Pin|DET_1_8G_DL_OUT_Pin|DET_1_8G_UL_IN_Pin|DET_1_8G_UL_OUT_Pin 
 8005cea:	23ff      	movs	r3, #255	; 0xff
                          |DET_2_1G_DL_IN_Pin|DET_2_1G_DL_OUT_Pin|DET_2_1G_UL_IN_Pin|DET_2_1G_UL_OUT_Pin;
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8005cec:	a904      	add	r1, sp, #16
 8005cee:	4814      	ldr	r0, [pc, #80]	; (8005d40 <HAL_ADC_MspInit+0xcc>)
    GPIO_InitStruct.Pin = DET_1_8G_DL_IN_Pin|DET_1_8G_DL_OUT_Pin|DET_1_8G_UL_IN_Pin|DET_1_8G_UL_OUT_Pin 
 8005cf0:	9304      	str	r3, [sp, #16]
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
 8005cf2:	9405      	str	r4, [sp, #20]
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8005cf4:	f7fe fe00 	bl	80048f8 <HAL_GPIO_Init>

    GPIO_InitStruct.Pin = DET_3_5G_DL_IN_Pin|DET_3_5G_DL_OUT_Pin;
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8005cf8:	4812      	ldr	r0, [pc, #72]	; (8005d44 <HAL_ADC_MspInit+0xd0>)
 8005cfa:	a904      	add	r1, sp, #16
    GPIO_InitStruct.Pin = DET_3_5G_DL_IN_Pin|DET_3_5G_DL_OUT_Pin;
 8005cfc:	9404      	str	r4, [sp, #16]
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
 8005cfe:	9405      	str	r4, [sp, #20]
    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8005d00:	f7fe fdfa 	bl	80048f8 <HAL_GPIO_Init>
    /* ADC1 DMA Init */
    /* ADC1 Init */
    hdma_adc1.Instance = DMA1_Channel1;
    hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY;
    hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE;
    hdma_adc1.Init.MemInc = DMA_MINC_ENABLE;
 8005d04:	2280      	movs	r2, #128	; 0x80
    hdma_adc1.Instance = DMA1_Channel1;
 8005d06:	4c10      	ldr	r4, [pc, #64]	; (8005d48 <HAL_ADC_MspInit+0xd4>)
 8005d08:	4b10      	ldr	r3, [pc, #64]	; (8005d4c <HAL_ADC_MspInit+0xd8>)
    hdma_adc1.Init.MemInc = DMA_MINC_ENABLE;
 8005d0a:	60e2      	str	r2, [r4, #12]
    hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
 8005d0c:	f44f 7200 	mov.w	r2, #512	; 0x200
    hdma_adc1.Instance = DMA1_Channel1;
 8005d10:	6023      	str	r3, [r4, #0]
    hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
 8005d12:	6122      	str	r2, [r4, #16]
    hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY;
 8005d14:	2300      	movs	r3, #0
    hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
 8005d16:	f44f 6200 	mov.w	r2, #2048	; 0x800
    hdma_adc1.Init.Mode = DMA_NORMAL;
    hdma_adc1.Init.Priority = DMA_PRIORITY_LOW;
    if (HAL_DMA_Init(&hdma_adc1) != HAL_OK)
 8005d1a:	4620      	mov	r0, r4
    hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY;
 8005d1c:	6063      	str	r3, [r4, #4]
    hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE;
 8005d1e:	60a3      	str	r3, [r4, #8]
    hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
 8005d20:	6162      	str	r2, [r4, #20]
    hdma_adc1.Init.Mode = DMA_NORMAL;
 8005d22:	61a3      	str	r3, [r4, #24]
    hdma_adc1.Init.Priority = DMA_PRIORITY_LOW;
 8005d24:	61e3      	str	r3, [r4, #28]
    if (HAL_DMA_Init(&hdma_adc1) != HAL_OK)
 8005d26:	f7fe fc5d 	bl	80045e4 <HAL_DMA_Init>
 8005d2a:	b108      	cbz	r0, 8005d30 <HAL_ADC_MspInit+0xbc>
    {
      Error_Handler();
 8005d2c:	f7ff ff7e 	bl	8005c2c <Error_Handler>
    }

    __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc1);
 8005d30:	622c      	str	r4, [r5, #32]
 8005d32:	6265      	str	r5, [r4, #36]	; 0x24
  /* USER CODE BEGIN ADC1_MspInit 1 */

  /* USER CODE END ADC1_MspInit 1 */
  }

}
 8005d34:	b009      	add	sp, #36	; 0x24
 8005d36:	bd30      	pop	{r4, r5, pc}
 8005d38:	40012400 	.word	0x40012400
 8005d3c:	40011000 	.word	0x40011000
 8005d40:	40010800 	.word	0x40010800
 8005d44:	40010c00 	.word	0x40010c00
 8005d48:	20000118 	.word	0x20000118
 8005d4c:	40020008 	.word	0x40020008

08005d50 <HAL_TIM_Base_MspInit>:
* @param htim_base: TIM_Base handle pointer
* @retval None
*/
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
{
  if(htim_base->Instance==TIM6)
 8005d50:	6802      	ldr	r2, [r0, #0]
 8005d52:	4b08      	ldr	r3, [pc, #32]	; (8005d74 <HAL_TIM_Base_MspInit+0x24>)
{
 8005d54:	b082      	sub	sp, #8
  if(htim_base->Instance==TIM6)
 8005d56:	429a      	cmp	r2, r3
 8005d58:	d10a      	bne.n	8005d70 <HAL_TIM_Base_MspInit+0x20>
  {
  /* USER CODE BEGIN TIM6_MspInit 0 */

  /* USER CODE END TIM6_MspInit 0 */
    /* Peripheral clock enable */
    __HAL_RCC_TIM6_CLK_ENABLE();
 8005d5a:	f503 3300 	add.w	r3, r3, #131072	; 0x20000
 8005d5e:	69da      	ldr	r2, [r3, #28]
 8005d60:	f042 0210 	orr.w	r2, r2, #16
 8005d64:	61da      	str	r2, [r3, #28]
 8005d66:	69db      	ldr	r3, [r3, #28]
 8005d68:	f003 0310 	and.w	r3, r3, #16
 8005d6c:	9301      	str	r3, [sp, #4]
 8005d6e:	9b01      	ldr	r3, [sp, #4]
  /* USER CODE BEGIN TIM6_MspInit 1 */

  /* USER CODE END TIM6_MspInit 1 */
  }

}
 8005d70:	b002      	add	sp, #8
 8005d72:	4770      	bx	lr
 8005d74:	40001000 	.word	0x40001000

08005d78 <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
 8005d78:	b510      	push	{r4, lr}
 8005d7a:	4604      	mov	r4, r0
 8005d7c:	b086      	sub	sp, #24
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8005d7e:	2210      	movs	r2, #16
 8005d80:	2100      	movs	r1, #0
 8005d82:	a802      	add	r0, sp, #8
 8005d84:	f000 f8fa 	bl	8005f7c <memset>
  if(huart->Instance==USART1)
 8005d88:	6822      	ldr	r2, [r4, #0]
 8005d8a:	4b17      	ldr	r3, [pc, #92]	; (8005de8 <HAL_UART_MspInit+0x70>)
 8005d8c:	429a      	cmp	r2, r3
 8005d8e:	d128      	bne.n	8005de2 <HAL_UART_MspInit+0x6a>
  {
  /* USER CODE BEGIN USART1_MspInit 0 */

  /* USER CODE END USART1_MspInit 0 */
    /* Peripheral clock enable */
    __HAL_RCC_USART1_CLK_ENABLE();
 8005d90:	f503 4358 	add.w	r3, r3, #55296	; 0xd800
 8005d94:	699a      	ldr	r2, [r3, #24]
    PA10     ------> USART1_RX 
    */
    GPIO_InitStruct.Pin = GPIO_PIN_9;
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8005d96:	a902      	add	r1, sp, #8
    __HAL_RCC_USART1_CLK_ENABLE();
 8005d98:	f442 4280 	orr.w	r2, r2, #16384	; 0x4000
 8005d9c:	619a      	str	r2, [r3, #24]
 8005d9e:	699a      	ldr	r2, [r3, #24]
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8005da0:	4812      	ldr	r0, [pc, #72]	; (8005dec <HAL_UART_MspInit+0x74>)
    __HAL_RCC_USART1_CLK_ENABLE();
 8005da2:	f402 4280 	and.w	r2, r2, #16384	; 0x4000
 8005da6:	9200      	str	r2, [sp, #0]
 8005da8:	9a00      	ldr	r2, [sp, #0]
    __HAL_RCC_GPIOA_CLK_ENABLE();
 8005daa:	699a      	ldr	r2, [r3, #24]
 8005dac:	f042 0204 	orr.w	r2, r2, #4
 8005db0:	619a      	str	r2, [r3, #24]
 8005db2:	699b      	ldr	r3, [r3, #24]
 8005db4:	f003 0304 	and.w	r3, r3, #4
 8005db8:	9301      	str	r3, [sp, #4]
 8005dba:	9b01      	ldr	r3, [sp, #4]
    GPIO_InitStruct.Pin = GPIO_PIN_9;
 8005dbc:	f44f 7300 	mov.w	r3, #512	; 0x200
 8005dc0:	9302      	str	r3, [sp, #8]
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 8005dc2:	2302      	movs	r3, #2
 8005dc4:	9303      	str	r3, [sp, #12]
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
 8005dc6:	2303      	movs	r3, #3
 8005dc8:	9305      	str	r3, [sp, #20]
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8005dca:	f7fe fd95 	bl	80048f8 <HAL_GPIO_Init>

    GPIO_InitStruct.Pin = GPIO_PIN_10;
 8005dce:	f44f 6380 	mov.w	r3, #1024	; 0x400
 8005dd2:	9302      	str	r3, [sp, #8]
    GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
 8005dd4:	2300      	movs	r3, #0
    GPIO_InitStruct.Pull = GPIO_NOPULL;
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8005dd6:	a902      	add	r1, sp, #8
 8005dd8:	4804      	ldr	r0, [pc, #16]	; (8005dec <HAL_UART_MspInit+0x74>)
    GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
 8005dda:	9303      	str	r3, [sp, #12]
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 8005ddc:	9304      	str	r3, [sp, #16]
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8005dde:	f7fe fd8b 	bl	80048f8 <HAL_GPIO_Init>
  /* USER CODE BEGIN USART1_MspInit 1 */

  /* USER CODE END USART1_MspInit 1 */
  }

}
 8005de2:	b006      	add	sp, #24
 8005de4:	bd10      	pop	{r4, pc}
 8005de6:	bf00      	nop
 8005de8:	40013800 	.word	0x40013800
 8005dec:	40010800 	.word	0x40010800

08005df0 <NMI_Handler>:
 8005df0:	4770      	bx	lr

08005df2 <HardFault_Handler>:

/**
  * @brief This function handles Hard fault interrupt.
  */
void HardFault_Handler(void)
{
 8005df2:	e7fe      	b.n	8005df2 <HardFault_Handler>

08005df4 <MemManage_Handler>:

/**
  * @brief This function handles Memory management fault.
  */
void MemManage_Handler(void)
{
 8005df4:	e7fe      	b.n	8005df4 <MemManage_Handler>

08005df6 <BusFault_Handler>:

/**
  * @brief This function handles Prefetch fault, memory access fault.
  */
void BusFault_Handler(void)
{
 8005df6:	e7fe      	b.n	8005df6 <BusFault_Handler>

08005df8 <UsageFault_Handler>:

/**
  * @brief This function handles Undefined instruction or illegal state.
  */
void UsageFault_Handler(void)
{
 8005df8:	e7fe      	b.n	8005df8 <UsageFault_Handler>

08005dfa <SVC_Handler>:
 8005dfa:	4770      	bx	lr

08005dfc <DebugMon_Handler>:
 8005dfc:	4770      	bx	lr

08005dfe <PendSV_Handler>:

/**
  * @brief This function handles Pendable request for system service.
  */
void PendSV_Handler(void)
{
 8005dfe:	4770      	bx	lr

08005e00 <SysTick_Handler>:
void SysTick_Handler(void)
{
  /* USER CODE BEGIN SysTick_IRQn 0 */

  /* USER CODE END SysTick_IRQn 0 */
  HAL_IncTick();
 8005e00:	f7fe ba46 	b.w	8004290 <HAL_IncTick>

08005e04 <DMA1_Channel1_IRQHandler>:
void DMA1_Channel1_IRQHandler(void)
{
  /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */

  /* USER CODE END DMA1_Channel1_IRQn 0 */
  HAL_DMA_IRQHandler(&hdma_adc1);
 8005e04:	4801      	ldr	r0, [pc, #4]	; (8005e0c <DMA1_Channel1_IRQHandler+0x8>)
 8005e06:	f7fe bc9b 	b.w	8004740 <HAL_DMA_IRQHandler>
 8005e0a:	bf00      	nop
 8005e0c:	20000118 	.word	0x20000118

08005e10 <USART1_IRQHandler>:
void USART1_IRQHandler(void)
{
  /* USER CODE BEGIN USART1_IRQn 0 */

  /* USER CODE END USART1_IRQn 0 */
  HAL_UART_IRQHandler(&huart1);
 8005e10:	4801      	ldr	r0, [pc, #4]	; (8005e18 <USART1_IRQHandler+0x8>)
 8005e12:	f7ff bc49 	b.w	80056a8 <HAL_UART_IRQHandler>
 8005e16:	bf00      	nop
 8005e18:	200000d8 	.word	0x200000d8

08005e1c <TIM6_IRQHandler>:
void TIM6_IRQHandler(void)
{
  /* USER CODE BEGIN TIM6_IRQn 0 */

  /* USER CODE END TIM6_IRQn 0 */
  HAL_TIM_IRQHandler(&htim6);
 8005e1c:	4801      	ldr	r0, [pc, #4]	; (8005e24 <TIM6_IRQHandler+0x8>)
 8005e1e:	f7ff b977 	b.w	8005110 <HAL_TIM_IRQHandler>
 8005e22:	bf00      	nop
 8005e24:	2000015c 	.word	0x2000015c

08005e28 <_read>:
	_kill(status, -1);
	while (1) {}		/* Make sure we hang here */
}

__attribute__((weak)) int _read(int file, char *ptr, int len)
{
 8005e28:	b570      	push	{r4, r5, r6, lr}
 8005e2a:	460e      	mov	r6, r1
 8005e2c:	4615      	mov	r5, r2
	int DataIdx;

	for (DataIdx = 0; DataIdx < len; DataIdx++)
 8005e2e:	460c      	mov	r4, r1
 8005e30:	1ba3      	subs	r3, r4, r6
 8005e32:	429d      	cmp	r5, r3
 8005e34:	dc01      	bgt.n	8005e3a <_read+0x12>
	{
		*ptr++ = __io_getchar();
	}

return len;
}
 8005e36:	4628      	mov	r0, r5
 8005e38:	bd70      	pop	{r4, r5, r6, pc}
		*ptr++ = __io_getchar();
 8005e3a:	f3af 8000 	nop.w
 8005e3e:	f804 0b01 	strb.w	r0, [r4], #1
 8005e42:	e7f5      	b.n	8005e30 <_read+0x8>

08005e44 <_sbrk>:
	}
	return len;
}

caddr_t _sbrk(int incr)
{
 8005e44:	b508      	push	{r3, lr}
	extern char end asm("end");
	static char *heap_end;
	char *prev_heap_end;

	if (heap_end == 0)
 8005e46:	4b0a      	ldr	r3, [pc, #40]	; (8005e70 <_sbrk+0x2c>)
{
 8005e48:	4602      	mov	r2, r0
	if (heap_end == 0)
 8005e4a:	6819      	ldr	r1, [r3, #0]
 8005e4c:	b909      	cbnz	r1, 8005e52 <_sbrk+0xe>
		heap_end = &end;
 8005e4e:	4909      	ldr	r1, [pc, #36]	; (8005e74 <_sbrk+0x30>)
 8005e50:	6019      	str	r1, [r3, #0]

	prev_heap_end = heap_end;
	if (heap_end + incr > stack_ptr)
 8005e52:	4669      	mov	r1, sp
	prev_heap_end = heap_end;
 8005e54:	6818      	ldr	r0, [r3, #0]
	if (heap_end + incr > stack_ptr)
 8005e56:	4402      	add	r2, r0
 8005e58:	428a      	cmp	r2, r1
 8005e5a:	d906      	bls.n	8005e6a <_sbrk+0x26>
	{
//		write(1, "Heap and stack collision\n", 25);
//		abort();
		errno = ENOMEM;
 8005e5c:	f000 f864 	bl	8005f28 <__errno>
 8005e60:	230c      	movs	r3, #12
 8005e62:	6003      	str	r3, [r0, #0]
		return (caddr_t) -1;
 8005e64:	f04f 30ff 	mov.w	r0, #4294967295
 8005e68:	bd08      	pop	{r3, pc}
	}

	heap_end += incr;
 8005e6a:	601a      	str	r2, [r3, #0]

	return (caddr_t) prev_heap_end;
}
 8005e6c:	bd08      	pop	{r3, pc}
 8005e6e:	bf00      	nop
 8005e70:	20000098 	.word	0x20000098
 8005e74:	200001d8 	.word	0x200001d8

08005e78 <_close>:

int _close(int file)
{
	return -1;
}
 8005e78:	f04f 30ff 	mov.w	r0, #4294967295
 8005e7c:	4770      	bx	lr

08005e7e <_fstat>:


int _fstat(int file, struct stat *st)
{
	st->st_mode = S_IFCHR;
 8005e7e:	f44f 5300 	mov.w	r3, #8192	; 0x2000
	return 0;
}
 8005e82:	2000      	movs	r0, #0
	st->st_mode = S_IFCHR;
 8005e84:	604b      	str	r3, [r1, #4]
}
 8005e86:	4770      	bx	lr

08005e88 <_isatty>:

int _isatty(int file)
{
	return 1;
}
 8005e88:	2001      	movs	r0, #1
 8005e8a:	4770      	bx	lr

08005e8c <_lseek>:

int _lseek(int file, int ptr, int dir)
{
	return 0;
}
 8005e8c:	2000      	movs	r0, #0
 8005e8e:	4770      	bx	lr

08005e90 <SystemInit>:
  */
void SystemInit (void)
{
  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
  /* Set HSION bit */
  RCC->CR |= 0x00000001U;
 8005e90:	4b0e      	ldr	r3, [pc, #56]	; (8005ecc <SystemInit+0x3c>)
 8005e92:	681a      	ldr	r2, [r3, #0]
 8005e94:	f042 0201 	orr.w	r2, r2, #1
 8005e98:	601a      	str	r2, [r3, #0]

  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
#if !defined(STM32F105xC) && !defined(STM32F107xC)
  RCC->CFGR &= 0xF8FF0000U;
 8005e9a:	6859      	ldr	r1, [r3, #4]
 8005e9c:	4a0c      	ldr	r2, [pc, #48]	; (8005ed0 <SystemInit+0x40>)
 8005e9e:	400a      	ands	r2, r1
 8005ea0:	605a      	str	r2, [r3, #4]
#else
  RCC->CFGR &= 0xF0FF0000U;
#endif /* STM32F105xC */   
  
  /* Reset HSEON, CSSON and PLLON bits */
  RCC->CR &= 0xFEF6FFFFU;
 8005ea2:	681a      	ldr	r2, [r3, #0]
 8005ea4:	f022 7284 	bic.w	r2, r2, #17301504	; 0x1080000
 8005ea8:	f422 3280 	bic.w	r2, r2, #65536	; 0x10000
 8005eac:	601a      	str	r2, [r3, #0]

  /* Reset HSEBYP bit */
  RCC->CR &= 0xFFFBFFFFU;
 8005eae:	681a      	ldr	r2, [r3, #0]
 8005eb0:	f422 2280 	bic.w	r2, r2, #262144	; 0x40000
 8005eb4:	601a      	str	r2, [r3, #0]

  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
  RCC->CFGR &= 0xFF80FFFFU;
 8005eb6:	685a      	ldr	r2, [r3, #4]
 8005eb8:	f422 02fe 	bic.w	r2, r2, #8323072	; 0x7f0000
 8005ebc:	605a      	str	r2, [r3, #4]

  /* Reset CFGR2 register */
  RCC->CFGR2 = 0x00000000U;      
#else
  /* Disable all interrupts and clear pending bits  */
  RCC->CIR = 0x009F0000U;
 8005ebe:	f44f 021f 	mov.w	r2, #10420224	; 0x9f0000
 8005ec2:	609a      	str	r2, [r3, #8]
#endif 

#ifdef VECT_TAB_SRAM
  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#else
  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
 8005ec4:	4a03      	ldr	r2, [pc, #12]	; (8005ed4 <SystemInit+0x44>)
 8005ec6:	4b04      	ldr	r3, [pc, #16]	; (8005ed8 <SystemInit+0x48>)
 8005ec8:	609a      	str	r2, [r3, #8]
 8005eca:	4770      	bx	lr
 8005ecc:	40021000 	.word	0x40021000
 8005ed0:	f8ff0000 	.word	0xf8ff0000
 8005ed4:	08004000 	.word	0x08004000
 8005ed8:	e000ed00 	.word	0xe000ed00

08005edc <Reset_Handler>:
  .weak Reset_Handler
  .type Reset_Handler, %function
Reset_Handler:

/* Copy the data segment initializers from flash to SRAM */
  movs r1, #0
 8005edc:	2100      	movs	r1, #0
  b LoopCopyDataInit
 8005ede:	e003      	b.n	8005ee8 <LoopCopyDataInit>

08005ee0 <CopyDataInit>:

CopyDataInit:
  ldr r3, =_sidata
 8005ee0:	4b0b      	ldr	r3, [pc, #44]	; (8005f10 <LoopFillZerobss+0x14>)
  ldr r3, [r3, r1]
 8005ee2:	585b      	ldr	r3, [r3, r1]
  str r3, [r0, r1]
 8005ee4:	5043      	str	r3, [r0, r1]
  adds r1, r1, #4
 8005ee6:	3104      	adds	r1, #4

08005ee8 <LoopCopyDataInit>:

LoopCopyDataInit:
  ldr r0, =_sdata
 8005ee8:	480a      	ldr	r0, [pc, #40]	; (8005f14 <LoopFillZerobss+0x18>)
  ldr r3, =_edata
 8005eea:	4b0b      	ldr	r3, [pc, #44]	; (8005f18 <LoopFillZerobss+0x1c>)
  adds r2, r0, r1
 8005eec:	1842      	adds	r2, r0, r1
  cmp r2, r3
 8005eee:	429a      	cmp	r2, r3
  bcc CopyDataInit
 8005ef0:	d3f6      	bcc.n	8005ee0 <CopyDataInit>
  ldr r2, =_sbss
 8005ef2:	4a0a      	ldr	r2, [pc, #40]	; (8005f1c <LoopFillZerobss+0x20>)
  b LoopFillZerobss
 8005ef4:	e002      	b.n	8005efc <LoopFillZerobss>

08005ef6 <FillZerobss>:
/* Zero fill the bss segment. */
FillZerobss:
  movs r3, #0
 8005ef6:	2300      	movs	r3, #0
  str r3, [r2], #4
 8005ef8:	f842 3b04 	str.w	r3, [r2], #4

08005efc <LoopFillZerobss>:

LoopFillZerobss:
  ldr r3, = _ebss
 8005efc:	4b08      	ldr	r3, [pc, #32]	; (8005f20 <LoopFillZerobss+0x24>)
  cmp r2, r3
 8005efe:	429a      	cmp	r2, r3
  bcc FillZerobss
 8005f00:	d3f9      	bcc.n	8005ef6 <FillZerobss>

/* Call the clock system intitialization function.*/
    bl  SystemInit
 8005f02:	f7ff ffc5 	bl	8005e90 <SystemInit>
/* Call static constructors */
    bl __libc_init_array
 8005f06:	f000 f815 	bl	8005f34 <__libc_init_array>
/* Call the application's entry point.*/
  bl main
 8005f0a:	f7ff fccf 	bl	80058ac <main>
  bx lr
 8005f0e:	4770      	bx	lr
  ldr r3, =_sidata
 8005f10:	08006a9c 	.word	0x08006a9c
  ldr r0, =_sdata
 8005f14:	20000000 	.word	0x20000000
  ldr r3, =_edata
 8005f18:	20000070 	.word	0x20000070
  ldr r2, =_sbss
 8005f1c:	20000070 	.word	0x20000070
  ldr r3, = _ebss
 8005f20:	200001d8 	.word	0x200001d8

08005f24 <ADC1_2_IRQHandler>:
 * @retval : None
*/
    .section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
  b Infinite_Loop
 8005f24:	e7fe      	b.n	8005f24 <ADC1_2_IRQHandler>
	...

08005f28 <__errno>:
 8005f28:	4b01      	ldr	r3, [pc, #4]	; (8005f30 <__errno+0x8>)
 8005f2a:	6818      	ldr	r0, [r3, #0]
 8005f2c:	4770      	bx	lr
 8005f2e:	bf00      	nop
 8005f30:	2000000c 	.word	0x2000000c

08005f34 <__libc_init_array>:
 8005f34:	b570      	push	{r4, r5, r6, lr}
 8005f36:	2500      	movs	r5, #0
 8005f38:	4e0c      	ldr	r6, [pc, #48]	; (8005f6c <__libc_init_array+0x38>)
 8005f3a:	4c0d      	ldr	r4, [pc, #52]	; (8005f70 <__libc_init_array+0x3c>)
 8005f3c:	1ba4      	subs	r4, r4, r6
 8005f3e:	10a4      	asrs	r4, r4, #2
 8005f40:	42a5      	cmp	r5, r4
 8005f42:	d109      	bne.n	8005f58 <__libc_init_array+0x24>
 8005f44:	f000 fd4c 	bl	80069e0 <_init>
 8005f48:	2500      	movs	r5, #0
 8005f4a:	4e0a      	ldr	r6, [pc, #40]	; (8005f74 <__libc_init_array+0x40>)
 8005f4c:	4c0a      	ldr	r4, [pc, #40]	; (8005f78 <__libc_init_array+0x44>)
 8005f4e:	1ba4      	subs	r4, r4, r6
 8005f50:	10a4      	asrs	r4, r4, #2
 8005f52:	42a5      	cmp	r5, r4
 8005f54:	d105      	bne.n	8005f62 <__libc_init_array+0x2e>
 8005f56:	bd70      	pop	{r4, r5, r6, pc}
 8005f58:	f856 3025 	ldr.w	r3, [r6, r5, lsl #2]
 8005f5c:	4798      	blx	r3
 8005f5e:	3501      	adds	r5, #1
 8005f60:	e7ee      	b.n	8005f40 <__libc_init_array+0xc>
 8005f62:	f856 3025 	ldr.w	r3, [r6, r5, lsl #2]
 8005f66:	4798      	blx	r3
 8005f68:	3501      	adds	r5, #1
 8005f6a:	e7f2      	b.n	8005f52 <__libc_init_array+0x1e>
 8005f6c:	08006a94 	.word	0x08006a94
 8005f70:	08006a94 	.word	0x08006a94
 8005f74:	08006a94 	.word	0x08006a94
 8005f78:	08006a98 	.word	0x08006a98

08005f7c <memset>:
 8005f7c:	4603      	mov	r3, r0
 8005f7e:	4402      	add	r2, r0
 8005f80:	4293      	cmp	r3, r2
 8005f82:	d100      	bne.n	8005f86 <memset+0xa>
 8005f84:	4770      	bx	lr
 8005f86:	f803 1b01 	strb.w	r1, [r3], #1
 8005f8a:	e7f9      	b.n	8005f80 <memset+0x4>

08005f8c <_puts_r>:
 8005f8c:	b570      	push	{r4, r5, r6, lr}
 8005f8e:	460e      	mov	r6, r1
 8005f90:	4605      	mov	r5, r0
 8005f92:	b118      	cbz	r0, 8005f9c <_puts_r+0x10>
 8005f94:	6983      	ldr	r3, [r0, #24]
 8005f96:	b90b      	cbnz	r3, 8005f9c <_puts_r+0x10>
 8005f98:	f000 fac4 	bl	8006524 <__sinit>
 8005f9c:	69ab      	ldr	r3, [r5, #24]
 8005f9e:	68ac      	ldr	r4, [r5, #8]
 8005fa0:	b913      	cbnz	r3, 8005fa8 <_puts_r+0x1c>
 8005fa2:	4628      	mov	r0, r5
 8005fa4:	f000 fabe 	bl	8006524 <__sinit>
 8005fa8:	4b23      	ldr	r3, [pc, #140]	; (8006038 <_puts_r+0xac>)
 8005faa:	429c      	cmp	r4, r3
 8005fac:	d117      	bne.n	8005fde <_puts_r+0x52>
 8005fae:	686c      	ldr	r4, [r5, #4]
 8005fb0:	89a3      	ldrh	r3, [r4, #12]
 8005fb2:	071b      	lsls	r3, r3, #28
 8005fb4:	d51d      	bpl.n	8005ff2 <_puts_r+0x66>
 8005fb6:	6923      	ldr	r3, [r4, #16]
 8005fb8:	b1db      	cbz	r3, 8005ff2 <_puts_r+0x66>
 8005fba:	3e01      	subs	r6, #1
 8005fbc:	68a3      	ldr	r3, [r4, #8]
 8005fbe:	f816 1f01 	ldrb.w	r1, [r6, #1]!
 8005fc2:	3b01      	subs	r3, #1
 8005fc4:	60a3      	str	r3, [r4, #8]
 8005fc6:	b9e9      	cbnz	r1, 8006004 <_puts_r+0x78>
 8005fc8:	2b00      	cmp	r3, #0
 8005fca:	da2e      	bge.n	800602a <_puts_r+0x9e>
 8005fcc:	4622      	mov	r2, r4
 8005fce:	210a      	movs	r1, #10
 8005fd0:	4628      	mov	r0, r5
 8005fd2:	f000 f8f5 	bl	80061c0 <__swbuf_r>
 8005fd6:	3001      	adds	r0, #1
 8005fd8:	d011      	beq.n	8005ffe <_puts_r+0x72>
 8005fda:	200a      	movs	r0, #10
 8005fdc:	bd70      	pop	{r4, r5, r6, pc}
 8005fde:	4b17      	ldr	r3, [pc, #92]	; (800603c <_puts_r+0xb0>)
 8005fe0:	429c      	cmp	r4, r3
 8005fe2:	d101      	bne.n	8005fe8 <_puts_r+0x5c>
 8005fe4:	68ac      	ldr	r4, [r5, #8]
 8005fe6:	e7e3      	b.n	8005fb0 <_puts_r+0x24>
 8005fe8:	4b15      	ldr	r3, [pc, #84]	; (8006040 <_puts_r+0xb4>)
 8005fea:	429c      	cmp	r4, r3
 8005fec:	bf08      	it	eq
 8005fee:	68ec      	ldreq	r4, [r5, #12]
 8005ff0:	e7de      	b.n	8005fb0 <_puts_r+0x24>
 8005ff2:	4621      	mov	r1, r4
 8005ff4:	4628      	mov	r0, r5
 8005ff6:	f000 f935 	bl	8006264 <__swsetup_r>
 8005ffa:	2800      	cmp	r0, #0
 8005ffc:	d0dd      	beq.n	8005fba <_puts_r+0x2e>
 8005ffe:	f04f 30ff 	mov.w	r0, #4294967295
 8006002:	bd70      	pop	{r4, r5, r6, pc}
 8006004:	2b00      	cmp	r3, #0
 8006006:	da04      	bge.n	8006012 <_puts_r+0x86>
 8006008:	69a2      	ldr	r2, [r4, #24]
 800600a:	4293      	cmp	r3, r2
 800600c:	db06      	blt.n	800601c <_puts_r+0x90>
 800600e:	290a      	cmp	r1, #10
 8006010:	d004      	beq.n	800601c <_puts_r+0x90>
 8006012:	6823      	ldr	r3, [r4, #0]
 8006014:	1c5a      	adds	r2, r3, #1
 8006016:	6022      	str	r2, [r4, #0]
 8006018:	7019      	strb	r1, [r3, #0]
 800601a:	e7cf      	b.n	8005fbc <_puts_r+0x30>
 800601c:	4622      	mov	r2, r4
 800601e:	4628      	mov	r0, r5
 8006020:	f000 f8ce 	bl	80061c0 <__swbuf_r>
 8006024:	3001      	adds	r0, #1
 8006026:	d1c9      	bne.n	8005fbc <_puts_r+0x30>
 8006028:	e7e9      	b.n	8005ffe <_puts_r+0x72>
 800602a:	200a      	movs	r0, #10
 800602c:	6823      	ldr	r3, [r4, #0]
 800602e:	1c5a      	adds	r2, r3, #1
 8006030:	6022      	str	r2, [r4, #0]
 8006032:	7018      	strb	r0, [r3, #0]
 8006034:	bd70      	pop	{r4, r5, r6, pc}
 8006036:	bf00      	nop
 8006038:	08006a54 	.word	0x08006a54
 800603c:	08006a74 	.word	0x08006a74
 8006040:	08006a34 	.word	0x08006a34

08006044 <puts>:
 8006044:	4b02      	ldr	r3, [pc, #8]	; (8006050 <puts+0xc>)
 8006046:	4601      	mov	r1, r0
 8006048:	6818      	ldr	r0, [r3, #0]
 800604a:	f7ff bf9f 	b.w	8005f8c <_puts_r>
 800604e:	bf00      	nop
 8006050:	2000000c 	.word	0x2000000c

08006054 <setbuf>:
 8006054:	2900      	cmp	r1, #0
 8006056:	f44f 6380 	mov.w	r3, #1024	; 0x400
 800605a:	bf0c      	ite	eq
 800605c:	2202      	moveq	r2, #2
 800605e:	2200      	movne	r2, #0
 8006060:	f000 b800 	b.w	8006064 <setvbuf>

08006064 <setvbuf>:
 8006064:	e92d 43f7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
 8006068:	461d      	mov	r5, r3
 800606a:	4b51      	ldr	r3, [pc, #324]	; (80061b0 <setvbuf+0x14c>)
 800606c:	4604      	mov	r4, r0
 800606e:	681e      	ldr	r6, [r3, #0]
 8006070:	460f      	mov	r7, r1
 8006072:	4690      	mov	r8, r2
 8006074:	b126      	cbz	r6, 8006080 <setvbuf+0x1c>
 8006076:	69b3      	ldr	r3, [r6, #24]
 8006078:	b913      	cbnz	r3, 8006080 <setvbuf+0x1c>
 800607a:	4630      	mov	r0, r6
 800607c:	f000 fa52 	bl	8006524 <__sinit>
 8006080:	4b4c      	ldr	r3, [pc, #304]	; (80061b4 <setvbuf+0x150>)
 8006082:	429c      	cmp	r4, r3
 8006084:	d152      	bne.n	800612c <setvbuf+0xc8>
 8006086:	6874      	ldr	r4, [r6, #4]
 8006088:	f1b8 0f02 	cmp.w	r8, #2
 800608c:	d006      	beq.n	800609c <setvbuf+0x38>
 800608e:	f1b8 0f01 	cmp.w	r8, #1
 8006092:	f200 8089 	bhi.w	80061a8 <setvbuf+0x144>
 8006096:	2d00      	cmp	r5, #0
 8006098:	f2c0 8086 	blt.w	80061a8 <setvbuf+0x144>
 800609c:	4621      	mov	r1, r4
 800609e:	4630      	mov	r0, r6
 80060a0:	f000 f9d6 	bl	8006450 <_fflush_r>
 80060a4:	6b61      	ldr	r1, [r4, #52]	; 0x34
 80060a6:	b141      	cbz	r1, 80060ba <setvbuf+0x56>
 80060a8:	f104 0344 	add.w	r3, r4, #68	; 0x44
 80060ac:	4299      	cmp	r1, r3
 80060ae:	d002      	beq.n	80060b6 <setvbuf+0x52>
 80060b0:	4630      	mov	r0, r6
 80060b2:	f000 fb2d 	bl	8006710 <_free_r>
 80060b6:	2300      	movs	r3, #0
 80060b8:	6363      	str	r3, [r4, #52]	; 0x34
 80060ba:	2300      	movs	r3, #0
 80060bc:	61a3      	str	r3, [r4, #24]
 80060be:	6063      	str	r3, [r4, #4]
 80060c0:	89a3      	ldrh	r3, [r4, #12]
 80060c2:	061b      	lsls	r3, r3, #24
 80060c4:	d503      	bpl.n	80060ce <setvbuf+0x6a>
 80060c6:	6921      	ldr	r1, [r4, #16]
 80060c8:	4630      	mov	r0, r6
 80060ca:	f000 fb21 	bl	8006710 <_free_r>
 80060ce:	89a3      	ldrh	r3, [r4, #12]
 80060d0:	f1b8 0f02 	cmp.w	r8, #2
 80060d4:	f423 634a 	bic.w	r3, r3, #3232	; 0xca0
 80060d8:	f023 0303 	bic.w	r3, r3, #3
 80060dc:	81a3      	strh	r3, [r4, #12]
 80060de:	d05d      	beq.n	800619c <setvbuf+0x138>
 80060e0:	ab01      	add	r3, sp, #4
 80060e2:	466a      	mov	r2, sp
 80060e4:	4621      	mov	r1, r4
 80060e6:	4630      	mov	r0, r6
 80060e8:	f000 faa6 	bl	8006638 <__swhatbuf_r>
 80060ec:	89a3      	ldrh	r3, [r4, #12]
 80060ee:	4318      	orrs	r0, r3
 80060f0:	81a0      	strh	r0, [r4, #12]
 80060f2:	bb2d      	cbnz	r5, 8006140 <setvbuf+0xdc>
 80060f4:	9d00      	ldr	r5, [sp, #0]
 80060f6:	4628      	mov	r0, r5
 80060f8:	f000 fb02 	bl	8006700 <malloc>
 80060fc:	4607      	mov	r7, r0
 80060fe:	2800      	cmp	r0, #0
 8006100:	d14e      	bne.n	80061a0 <setvbuf+0x13c>
 8006102:	f8dd 9000 	ldr.w	r9, [sp]
 8006106:	45a9      	cmp	r9, r5
 8006108:	d13c      	bne.n	8006184 <setvbuf+0x120>
 800610a:	f04f 30ff 	mov.w	r0, #4294967295
 800610e:	89a3      	ldrh	r3, [r4, #12]
 8006110:	f043 0302 	orr.w	r3, r3, #2
 8006114:	81a3      	strh	r3, [r4, #12]
 8006116:	2300      	movs	r3, #0
 8006118:	60a3      	str	r3, [r4, #8]
 800611a:	f104 0347 	add.w	r3, r4, #71	; 0x47
 800611e:	6023      	str	r3, [r4, #0]
 8006120:	6123      	str	r3, [r4, #16]
 8006122:	2301      	movs	r3, #1
 8006124:	6163      	str	r3, [r4, #20]
 8006126:	b003      	add	sp, #12
 8006128:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
 800612c:	4b22      	ldr	r3, [pc, #136]	; (80061b8 <setvbuf+0x154>)
 800612e:	429c      	cmp	r4, r3
 8006130:	d101      	bne.n	8006136 <setvbuf+0xd2>
 8006132:	68b4      	ldr	r4, [r6, #8]
 8006134:	e7a8      	b.n	8006088 <setvbuf+0x24>
 8006136:	4b21      	ldr	r3, [pc, #132]	; (80061bc <setvbuf+0x158>)
 8006138:	429c      	cmp	r4, r3
 800613a:	bf08      	it	eq
 800613c:	68f4      	ldreq	r4, [r6, #12]
 800613e:	e7a3      	b.n	8006088 <setvbuf+0x24>
 8006140:	2f00      	cmp	r7, #0
 8006142:	d0d8      	beq.n	80060f6 <setvbuf+0x92>
 8006144:	69b3      	ldr	r3, [r6, #24]
 8006146:	b913      	cbnz	r3, 800614e <setvbuf+0xea>
 8006148:	4630      	mov	r0, r6
 800614a:	f000 f9eb 	bl	8006524 <__sinit>
 800614e:	f1b8 0f01 	cmp.w	r8, #1
 8006152:	bf08      	it	eq
 8006154:	89a3      	ldrheq	r3, [r4, #12]
 8006156:	6027      	str	r7, [r4, #0]
 8006158:	bf04      	itt	eq
 800615a:	f043 0301 	orreq.w	r3, r3, #1
 800615e:	81a3      	strheq	r3, [r4, #12]
 8006160:	89a3      	ldrh	r3, [r4, #12]
 8006162:	6127      	str	r7, [r4, #16]
 8006164:	f013 0008 	ands.w	r0, r3, #8
 8006168:	6165      	str	r5, [r4, #20]
 800616a:	d01b      	beq.n	80061a4 <setvbuf+0x140>
 800616c:	f013 0001 	ands.w	r0, r3, #1
 8006170:	f04f 0300 	mov.w	r3, #0
 8006174:	bf1f      	itttt	ne
 8006176:	426d      	negne	r5, r5
 8006178:	60a3      	strne	r3, [r4, #8]
 800617a:	61a5      	strne	r5, [r4, #24]
 800617c:	4618      	movne	r0, r3
 800617e:	bf08      	it	eq
 8006180:	60a5      	streq	r5, [r4, #8]
 8006182:	e7d0      	b.n	8006126 <setvbuf+0xc2>
 8006184:	4648      	mov	r0, r9
 8006186:	f000 fabb 	bl	8006700 <malloc>
 800618a:	4607      	mov	r7, r0
 800618c:	2800      	cmp	r0, #0
 800618e:	d0bc      	beq.n	800610a <setvbuf+0xa6>
 8006190:	89a3      	ldrh	r3, [r4, #12]
 8006192:	464d      	mov	r5, r9
 8006194:	f043 0380 	orr.w	r3, r3, #128	; 0x80
 8006198:	81a3      	strh	r3, [r4, #12]
 800619a:	e7d3      	b.n	8006144 <setvbuf+0xe0>
 800619c:	2000      	movs	r0, #0
 800619e:	e7b6      	b.n	800610e <setvbuf+0xaa>
 80061a0:	46a9      	mov	r9, r5
 80061a2:	e7f5      	b.n	8006190 <setvbuf+0x12c>
 80061a4:	60a0      	str	r0, [r4, #8]
 80061a6:	e7be      	b.n	8006126 <setvbuf+0xc2>
 80061a8:	f04f 30ff 	mov.w	r0, #4294967295
 80061ac:	e7bb      	b.n	8006126 <setvbuf+0xc2>
 80061ae:	bf00      	nop
 80061b0:	2000000c 	.word	0x2000000c
 80061b4:	08006a54 	.word	0x08006a54
 80061b8:	08006a74 	.word	0x08006a74
 80061bc:	08006a34 	.word	0x08006a34

080061c0 <__swbuf_r>:
 80061c0:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 80061c2:	460e      	mov	r6, r1
 80061c4:	4614      	mov	r4, r2
 80061c6:	4605      	mov	r5, r0
 80061c8:	b118      	cbz	r0, 80061d2 <__swbuf_r+0x12>
 80061ca:	6983      	ldr	r3, [r0, #24]
 80061cc:	b90b      	cbnz	r3, 80061d2 <__swbuf_r+0x12>
 80061ce:	f000 f9a9 	bl	8006524 <__sinit>
 80061d2:	4b21      	ldr	r3, [pc, #132]	; (8006258 <__swbuf_r+0x98>)
 80061d4:	429c      	cmp	r4, r3
 80061d6:	d12a      	bne.n	800622e <__swbuf_r+0x6e>
 80061d8:	686c      	ldr	r4, [r5, #4]
 80061da:	69a3      	ldr	r3, [r4, #24]
 80061dc:	60a3      	str	r3, [r4, #8]
 80061de:	89a3      	ldrh	r3, [r4, #12]
 80061e0:	071a      	lsls	r2, r3, #28
 80061e2:	d52e      	bpl.n	8006242 <__swbuf_r+0x82>
 80061e4:	6923      	ldr	r3, [r4, #16]
 80061e6:	b363      	cbz	r3, 8006242 <__swbuf_r+0x82>
 80061e8:	6923      	ldr	r3, [r4, #16]
 80061ea:	6820      	ldr	r0, [r4, #0]
 80061ec:	b2f6      	uxtb	r6, r6
 80061ee:	1ac0      	subs	r0, r0, r3
 80061f0:	6963      	ldr	r3, [r4, #20]
 80061f2:	4637      	mov	r7, r6
 80061f4:	4298      	cmp	r0, r3
 80061f6:	db04      	blt.n	8006202 <__swbuf_r+0x42>
 80061f8:	4621      	mov	r1, r4
 80061fa:	4628      	mov	r0, r5
 80061fc:	f000 f928 	bl	8006450 <_fflush_r>
 8006200:	bb28      	cbnz	r0, 800624e <__swbuf_r+0x8e>
 8006202:	68a3      	ldr	r3, [r4, #8]
 8006204:	3001      	adds	r0, #1
 8006206:	3b01      	subs	r3, #1
 8006208:	60a3      	str	r3, [r4, #8]
 800620a:	6823      	ldr	r3, [r4, #0]
 800620c:	1c5a      	adds	r2, r3, #1
 800620e:	6022      	str	r2, [r4, #0]
 8006210:	701e      	strb	r6, [r3, #0]
 8006212:	6963      	ldr	r3, [r4, #20]
 8006214:	4298      	cmp	r0, r3
 8006216:	d004      	beq.n	8006222 <__swbuf_r+0x62>
 8006218:	89a3      	ldrh	r3, [r4, #12]
 800621a:	07db      	lsls	r3, r3, #31
 800621c:	d519      	bpl.n	8006252 <__swbuf_r+0x92>
 800621e:	2e0a      	cmp	r6, #10
 8006220:	d117      	bne.n	8006252 <__swbuf_r+0x92>
 8006222:	4621      	mov	r1, r4
 8006224:	4628      	mov	r0, r5
 8006226:	f000 f913 	bl	8006450 <_fflush_r>
 800622a:	b190      	cbz	r0, 8006252 <__swbuf_r+0x92>
 800622c:	e00f      	b.n	800624e <__swbuf_r+0x8e>
 800622e:	4b0b      	ldr	r3, [pc, #44]	; (800625c <__swbuf_r+0x9c>)
 8006230:	429c      	cmp	r4, r3
 8006232:	d101      	bne.n	8006238 <__swbuf_r+0x78>
 8006234:	68ac      	ldr	r4, [r5, #8]
 8006236:	e7d0      	b.n	80061da <__swbuf_r+0x1a>
 8006238:	4b09      	ldr	r3, [pc, #36]	; (8006260 <__swbuf_r+0xa0>)
 800623a:	429c      	cmp	r4, r3
 800623c:	bf08      	it	eq
 800623e:	68ec      	ldreq	r4, [r5, #12]
 8006240:	e7cb      	b.n	80061da <__swbuf_r+0x1a>
 8006242:	4621      	mov	r1, r4
 8006244:	4628      	mov	r0, r5
 8006246:	f000 f80d 	bl	8006264 <__swsetup_r>
 800624a:	2800      	cmp	r0, #0
 800624c:	d0cc      	beq.n	80061e8 <__swbuf_r+0x28>
 800624e:	f04f 37ff 	mov.w	r7, #4294967295
 8006252:	4638      	mov	r0, r7
 8006254:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
 8006256:	bf00      	nop
 8006258:	08006a54 	.word	0x08006a54
 800625c:	08006a74 	.word	0x08006a74
 8006260:	08006a34 	.word	0x08006a34

08006264 <__swsetup_r>:
 8006264:	4b32      	ldr	r3, [pc, #200]	; (8006330 <__swsetup_r+0xcc>)
 8006266:	b570      	push	{r4, r5, r6, lr}
 8006268:	681d      	ldr	r5, [r3, #0]
 800626a:	4606      	mov	r6, r0
 800626c:	460c      	mov	r4, r1
 800626e:	b125      	cbz	r5, 800627a <__swsetup_r+0x16>
 8006270:	69ab      	ldr	r3, [r5, #24]
 8006272:	b913      	cbnz	r3, 800627a <__swsetup_r+0x16>
 8006274:	4628      	mov	r0, r5
 8006276:	f000 f955 	bl	8006524 <__sinit>
 800627a:	4b2e      	ldr	r3, [pc, #184]	; (8006334 <__swsetup_r+0xd0>)
 800627c:	429c      	cmp	r4, r3
 800627e:	d10f      	bne.n	80062a0 <__swsetup_r+0x3c>
 8006280:	686c      	ldr	r4, [r5, #4]
 8006282:	f9b4 300c 	ldrsh.w	r3, [r4, #12]
 8006286:	b29a      	uxth	r2, r3
 8006288:	0715      	lsls	r5, r2, #28
 800628a:	d42c      	bmi.n	80062e6 <__swsetup_r+0x82>
 800628c:	06d0      	lsls	r0, r2, #27
 800628e:	d411      	bmi.n	80062b4 <__swsetup_r+0x50>
 8006290:	2209      	movs	r2, #9
 8006292:	6032      	str	r2, [r6, #0]
 8006294:	f043 0340 	orr.w	r3, r3, #64	; 0x40
 8006298:	81a3      	strh	r3, [r4, #12]
 800629a:	f04f 30ff 	mov.w	r0, #4294967295
 800629e:	bd70      	pop	{r4, r5, r6, pc}
 80062a0:	4b25      	ldr	r3, [pc, #148]	; (8006338 <__swsetup_r+0xd4>)
 80062a2:	429c      	cmp	r4, r3
 80062a4:	d101      	bne.n	80062aa <__swsetup_r+0x46>
 80062a6:	68ac      	ldr	r4, [r5, #8]
 80062a8:	e7eb      	b.n	8006282 <__swsetup_r+0x1e>
 80062aa:	4b24      	ldr	r3, [pc, #144]	; (800633c <__swsetup_r+0xd8>)
 80062ac:	429c      	cmp	r4, r3
 80062ae:	bf08      	it	eq
 80062b0:	68ec      	ldreq	r4, [r5, #12]
 80062b2:	e7e6      	b.n	8006282 <__swsetup_r+0x1e>
 80062b4:	0751      	lsls	r1, r2, #29
 80062b6:	d512      	bpl.n	80062de <__swsetup_r+0x7a>
 80062b8:	6b61      	ldr	r1, [r4, #52]	; 0x34
 80062ba:	b141      	cbz	r1, 80062ce <__swsetup_r+0x6a>
 80062bc:	f104 0344 	add.w	r3, r4, #68	; 0x44
 80062c0:	4299      	cmp	r1, r3
 80062c2:	d002      	beq.n	80062ca <__swsetup_r+0x66>
 80062c4:	4630      	mov	r0, r6
 80062c6:	f000 fa23 	bl	8006710 <_free_r>
 80062ca:	2300      	movs	r3, #0
 80062cc:	6363      	str	r3, [r4, #52]	; 0x34
 80062ce:	89a3      	ldrh	r3, [r4, #12]
 80062d0:	f023 0324 	bic.w	r3, r3, #36	; 0x24
 80062d4:	81a3      	strh	r3, [r4, #12]
 80062d6:	2300      	movs	r3, #0
 80062d8:	6063      	str	r3, [r4, #4]
 80062da:	6923      	ldr	r3, [r4, #16]
 80062dc:	6023      	str	r3, [r4, #0]
 80062de:	89a3      	ldrh	r3, [r4, #12]
 80062e0:	f043 0308 	orr.w	r3, r3, #8
 80062e4:	81a3      	strh	r3, [r4, #12]
 80062e6:	6923      	ldr	r3, [r4, #16]
 80062e8:	b94b      	cbnz	r3, 80062fe <__swsetup_r+0x9a>
 80062ea:	89a3      	ldrh	r3, [r4, #12]
 80062ec:	f403 7320 	and.w	r3, r3, #640	; 0x280
 80062f0:	f5b3 7f00 	cmp.w	r3, #512	; 0x200
 80062f4:	d003      	beq.n	80062fe <__swsetup_r+0x9a>
 80062f6:	4621      	mov	r1, r4
 80062f8:	4630      	mov	r0, r6
 80062fa:	f000 f9c1 	bl	8006680 <__smakebuf_r>
 80062fe:	89a2      	ldrh	r2, [r4, #12]
 8006300:	f012 0301 	ands.w	r3, r2, #1
 8006304:	d00c      	beq.n	8006320 <__swsetup_r+0xbc>
 8006306:	2300      	movs	r3, #0
 8006308:	60a3      	str	r3, [r4, #8]
 800630a:	6963      	ldr	r3, [r4, #20]
 800630c:	425b      	negs	r3, r3
 800630e:	61a3      	str	r3, [r4, #24]
 8006310:	6923      	ldr	r3, [r4, #16]
 8006312:	b953      	cbnz	r3, 800632a <__swsetup_r+0xc6>
 8006314:	f9b4 300c 	ldrsh.w	r3, [r4, #12]
 8006318:	f013 0080 	ands.w	r0, r3, #128	; 0x80
 800631c:	d1ba      	bne.n	8006294 <__swsetup_r+0x30>
 800631e:	bd70      	pop	{r4, r5, r6, pc}
 8006320:	0792      	lsls	r2, r2, #30
 8006322:	bf58      	it	pl
 8006324:	6963      	ldrpl	r3, [r4, #20]
 8006326:	60a3      	str	r3, [r4, #8]
 8006328:	e7f2      	b.n	8006310 <__swsetup_r+0xac>
 800632a:	2000      	movs	r0, #0
 800632c:	e7f7      	b.n	800631e <__swsetup_r+0xba>
 800632e:	bf00      	nop
 8006330:	2000000c 	.word	0x2000000c
 8006334:	08006a54 	.word	0x08006a54
 8006338:	08006a74 	.word	0x08006a74
 800633c:	08006a34 	.word	0x08006a34

08006340 <__sflush_r>:
 8006340:	898a      	ldrh	r2, [r1, #12]
 8006342:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
 8006346:	4605      	mov	r5, r0
 8006348:	0710      	lsls	r0, r2, #28
 800634a:	460c      	mov	r4, r1
 800634c:	d45a      	bmi.n	8006404 <__sflush_r+0xc4>
 800634e:	684b      	ldr	r3, [r1, #4]
 8006350:	2b00      	cmp	r3, #0
 8006352:	dc05      	bgt.n	8006360 <__sflush_r+0x20>
 8006354:	6c0b      	ldr	r3, [r1, #64]	; 0x40
 8006356:	2b00      	cmp	r3, #0
 8006358:	dc02      	bgt.n	8006360 <__sflush_r+0x20>
 800635a:	2000      	movs	r0, #0
 800635c:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
 8006360:	6ae6      	ldr	r6, [r4, #44]	; 0x2c
 8006362:	2e00      	cmp	r6, #0
 8006364:	d0f9      	beq.n	800635a <__sflush_r+0x1a>
 8006366:	2300      	movs	r3, #0
 8006368:	f412 5280 	ands.w	r2, r2, #4096	; 0x1000
 800636c:	682f      	ldr	r7, [r5, #0]
 800636e:	602b      	str	r3, [r5, #0]
 8006370:	d033      	beq.n	80063da <__sflush_r+0x9a>
 8006372:	6d60      	ldr	r0, [r4, #84]	; 0x54
 8006374:	89a3      	ldrh	r3, [r4, #12]
 8006376:	075a      	lsls	r2, r3, #29
 8006378:	d505      	bpl.n	8006386 <__sflush_r+0x46>
 800637a:	6863      	ldr	r3, [r4, #4]
 800637c:	1ac0      	subs	r0, r0, r3
 800637e:	6b63      	ldr	r3, [r4, #52]	; 0x34
 8006380:	b10b      	cbz	r3, 8006386 <__sflush_r+0x46>
 8006382:	6c23      	ldr	r3, [r4, #64]	; 0x40
 8006384:	1ac0      	subs	r0, r0, r3
 8006386:	2300      	movs	r3, #0
 8006388:	4602      	mov	r2, r0
 800638a:	6ae6      	ldr	r6, [r4, #44]	; 0x2c
 800638c:	6a21      	ldr	r1, [r4, #32]
 800638e:	4628      	mov	r0, r5
 8006390:	47b0      	blx	r6
 8006392:	1c43      	adds	r3, r0, #1
 8006394:	89a3      	ldrh	r3, [r4, #12]
 8006396:	d106      	bne.n	80063a6 <__sflush_r+0x66>
 8006398:	6829      	ldr	r1, [r5, #0]
 800639a:	291d      	cmp	r1, #29
 800639c:	d84b      	bhi.n	8006436 <__sflush_r+0xf6>
 800639e:	4a2b      	ldr	r2, [pc, #172]	; (800644c <__sflush_r+0x10c>)
 80063a0:	40ca      	lsrs	r2, r1
 80063a2:	07d6      	lsls	r6, r2, #31
 80063a4:	d547      	bpl.n	8006436 <__sflush_r+0xf6>
 80063a6:	2200      	movs	r2, #0
 80063a8:	6062      	str	r2, [r4, #4]
 80063aa:	6922      	ldr	r2, [r4, #16]
 80063ac:	04d9      	lsls	r1, r3, #19
 80063ae:	6022      	str	r2, [r4, #0]
 80063b0:	d504      	bpl.n	80063bc <__sflush_r+0x7c>
 80063b2:	1c42      	adds	r2, r0, #1
 80063b4:	d101      	bne.n	80063ba <__sflush_r+0x7a>
 80063b6:	682b      	ldr	r3, [r5, #0]
 80063b8:	b903      	cbnz	r3, 80063bc <__sflush_r+0x7c>
 80063ba:	6560      	str	r0, [r4, #84]	; 0x54
 80063bc:	6b61      	ldr	r1, [r4, #52]	; 0x34
 80063be:	602f      	str	r7, [r5, #0]
 80063c0:	2900      	cmp	r1, #0
 80063c2:	d0ca      	beq.n	800635a <__sflush_r+0x1a>
 80063c4:	f104 0344 	add.w	r3, r4, #68	; 0x44
 80063c8:	4299      	cmp	r1, r3
 80063ca:	d002      	beq.n	80063d2 <__sflush_r+0x92>
 80063cc:	4628      	mov	r0, r5
 80063ce:	f000 f99f 	bl	8006710 <_free_r>
 80063d2:	2000      	movs	r0, #0
 80063d4:	6360      	str	r0, [r4, #52]	; 0x34
 80063d6:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
 80063da:	6a21      	ldr	r1, [r4, #32]
 80063dc:	2301      	movs	r3, #1
 80063de:	4628      	mov	r0, r5
 80063e0:	47b0      	blx	r6
 80063e2:	1c41      	adds	r1, r0, #1
 80063e4:	d1c6      	bne.n	8006374 <__sflush_r+0x34>
 80063e6:	682b      	ldr	r3, [r5, #0]
 80063e8:	2b00      	cmp	r3, #0
 80063ea:	d0c3      	beq.n	8006374 <__sflush_r+0x34>
 80063ec:	2b1d      	cmp	r3, #29
 80063ee:	d001      	beq.n	80063f4 <__sflush_r+0xb4>
 80063f0:	2b16      	cmp	r3, #22
 80063f2:	d101      	bne.n	80063f8 <__sflush_r+0xb8>
 80063f4:	602f      	str	r7, [r5, #0]
 80063f6:	e7b0      	b.n	800635a <__sflush_r+0x1a>
 80063f8:	89a3      	ldrh	r3, [r4, #12]
 80063fa:	f043 0340 	orr.w	r3, r3, #64	; 0x40
 80063fe:	81a3      	strh	r3, [r4, #12]
 8006400:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
 8006404:	690f      	ldr	r7, [r1, #16]
 8006406:	2f00      	cmp	r7, #0
 8006408:	d0a7      	beq.n	800635a <__sflush_r+0x1a>
 800640a:	0793      	lsls	r3, r2, #30
 800640c:	bf18      	it	ne
 800640e:	2300      	movne	r3, #0
 8006410:	680e      	ldr	r6, [r1, #0]
 8006412:	bf08      	it	eq
 8006414:	694b      	ldreq	r3, [r1, #20]
 8006416:	eba6 0807 	sub.w	r8, r6, r7
 800641a:	600f      	str	r7, [r1, #0]
 800641c:	608b      	str	r3, [r1, #8]
 800641e:	f1b8 0f00 	cmp.w	r8, #0
 8006422:	dd9a      	ble.n	800635a <__sflush_r+0x1a>
 8006424:	4643      	mov	r3, r8
 8006426:	463a      	mov	r2, r7
 8006428:	6a21      	ldr	r1, [r4, #32]
 800642a:	4628      	mov	r0, r5
 800642c:	6aa6      	ldr	r6, [r4, #40]	; 0x28
 800642e:	47b0      	blx	r6
 8006430:	2800      	cmp	r0, #0
 8006432:	dc07      	bgt.n	8006444 <__sflush_r+0x104>
 8006434:	89a3      	ldrh	r3, [r4, #12]
 8006436:	f043 0340 	orr.w	r3, r3, #64	; 0x40
 800643a:	81a3      	strh	r3, [r4, #12]
 800643c:	f04f 30ff 	mov.w	r0, #4294967295
 8006440:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
 8006444:	4407      	add	r7, r0
 8006446:	eba8 0800 	sub.w	r8, r8, r0
 800644a:	e7e8      	b.n	800641e <__sflush_r+0xde>
 800644c:	20400001 	.word	0x20400001

08006450 <_fflush_r>:
 8006450:	b538      	push	{r3, r4, r5, lr}
 8006452:	690b      	ldr	r3, [r1, #16]
 8006454:	4605      	mov	r5, r0
 8006456:	460c      	mov	r4, r1
 8006458:	b1db      	cbz	r3, 8006492 <_fflush_r+0x42>
 800645a:	b118      	cbz	r0, 8006464 <_fflush_r+0x14>
 800645c:	6983      	ldr	r3, [r0, #24]
 800645e:	b90b      	cbnz	r3, 8006464 <_fflush_r+0x14>
 8006460:	f000 f860 	bl	8006524 <__sinit>
 8006464:	4b0c      	ldr	r3, [pc, #48]	; (8006498 <_fflush_r+0x48>)
 8006466:	429c      	cmp	r4, r3
 8006468:	d109      	bne.n	800647e <_fflush_r+0x2e>
 800646a:	686c      	ldr	r4, [r5, #4]
 800646c:	f9b4 300c 	ldrsh.w	r3, [r4, #12]
 8006470:	b17b      	cbz	r3, 8006492 <_fflush_r+0x42>
 8006472:	4621      	mov	r1, r4
 8006474:	4628      	mov	r0, r5
 8006476:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
 800647a:	f7ff bf61 	b.w	8006340 <__sflush_r>
 800647e:	4b07      	ldr	r3, [pc, #28]	; (800649c <_fflush_r+0x4c>)
 8006480:	429c      	cmp	r4, r3
 8006482:	d101      	bne.n	8006488 <_fflush_r+0x38>
 8006484:	68ac      	ldr	r4, [r5, #8]
 8006486:	e7f1      	b.n	800646c <_fflush_r+0x1c>
 8006488:	4b05      	ldr	r3, [pc, #20]	; (80064a0 <_fflush_r+0x50>)
 800648a:	429c      	cmp	r4, r3
 800648c:	bf08      	it	eq
 800648e:	68ec      	ldreq	r4, [r5, #12]
 8006490:	e7ec      	b.n	800646c <_fflush_r+0x1c>
 8006492:	2000      	movs	r0, #0
 8006494:	bd38      	pop	{r3, r4, r5, pc}
 8006496:	bf00      	nop
 8006498:	08006a54 	.word	0x08006a54
 800649c:	08006a74 	.word	0x08006a74
 80064a0:	08006a34 	.word	0x08006a34

080064a4 <_cleanup_r>:
 80064a4:	4901      	ldr	r1, [pc, #4]	; (80064ac <_cleanup_r+0x8>)
 80064a6:	f000 b8a9 	b.w	80065fc <_fwalk_reent>
 80064aa:	bf00      	nop
 80064ac:	08006451 	.word	0x08006451

080064b0 <std.isra.0>:
 80064b0:	2300      	movs	r3, #0
 80064b2:	b510      	push	{r4, lr}
 80064b4:	4604      	mov	r4, r0
 80064b6:	6003      	str	r3, [r0, #0]
 80064b8:	6043      	str	r3, [r0, #4]
 80064ba:	6083      	str	r3, [r0, #8]
 80064bc:	8181      	strh	r1, [r0, #12]
 80064be:	6643      	str	r3, [r0, #100]	; 0x64
 80064c0:	81c2      	strh	r2, [r0, #14]
 80064c2:	6103      	str	r3, [r0, #16]
 80064c4:	6143      	str	r3, [r0, #20]
 80064c6:	6183      	str	r3, [r0, #24]
 80064c8:	4619      	mov	r1, r3
 80064ca:	2208      	movs	r2, #8
 80064cc:	305c      	adds	r0, #92	; 0x5c
 80064ce:	f7ff fd55 	bl	8005f7c <memset>
 80064d2:	4b05      	ldr	r3, [pc, #20]	; (80064e8 <std.isra.0+0x38>)
 80064d4:	6224      	str	r4, [r4, #32]
 80064d6:	6263      	str	r3, [r4, #36]	; 0x24
 80064d8:	4b04      	ldr	r3, [pc, #16]	; (80064ec <std.isra.0+0x3c>)
 80064da:	62a3      	str	r3, [r4, #40]	; 0x28
 80064dc:	4b04      	ldr	r3, [pc, #16]	; (80064f0 <std.isra.0+0x40>)
 80064de:	62e3      	str	r3, [r4, #44]	; 0x2c
 80064e0:	4b04      	ldr	r3, [pc, #16]	; (80064f4 <std.isra.0+0x44>)
 80064e2:	6323      	str	r3, [r4, #48]	; 0x30
 80064e4:	bd10      	pop	{r4, pc}
 80064e6:	bf00      	nop
 80064e8:	08006885 	.word	0x08006885
 80064ec:	080068a7 	.word	0x080068a7
 80064f0:	080068df 	.word	0x080068df
 80064f4:	08006903 	.word	0x08006903

080064f8 <__sfmoreglue>:
 80064f8:	b570      	push	{r4, r5, r6, lr}
 80064fa:	2568      	movs	r5, #104	; 0x68
 80064fc:	1e4a      	subs	r2, r1, #1
 80064fe:	4355      	muls	r5, r2
 8006500:	460e      	mov	r6, r1
 8006502:	f105 0174 	add.w	r1, r5, #116	; 0x74
 8006506:	f000 f94f 	bl	80067a8 <_malloc_r>
 800650a:	4604      	mov	r4, r0
 800650c:	b140      	cbz	r0, 8006520 <__sfmoreglue+0x28>
 800650e:	2100      	movs	r1, #0
 8006510:	e880 0042 	stmia.w	r0, {r1, r6}
 8006514:	300c      	adds	r0, #12
 8006516:	60a0      	str	r0, [r4, #8]
 8006518:	f105 0268 	add.w	r2, r5, #104	; 0x68
 800651c:	f7ff fd2e 	bl	8005f7c <memset>
 8006520:	4620      	mov	r0, r4
 8006522:	bd70      	pop	{r4, r5, r6, pc}

08006524 <__sinit>:
 8006524:	6983      	ldr	r3, [r0, #24]
 8006526:	b510      	push	{r4, lr}
 8006528:	4604      	mov	r4, r0
 800652a:	bb33      	cbnz	r3, 800657a <__sinit+0x56>
 800652c:	6483      	str	r3, [r0, #72]	; 0x48
 800652e:	64c3      	str	r3, [r0, #76]	; 0x4c
 8006530:	6503      	str	r3, [r0, #80]	; 0x50
 8006532:	4b12      	ldr	r3, [pc, #72]	; (800657c <__sinit+0x58>)
 8006534:	4a12      	ldr	r2, [pc, #72]	; (8006580 <__sinit+0x5c>)
 8006536:	681b      	ldr	r3, [r3, #0]
 8006538:	6282      	str	r2, [r0, #40]	; 0x28
 800653a:	4298      	cmp	r0, r3
 800653c:	bf04      	itt	eq
 800653e:	2301      	moveq	r3, #1
 8006540:	6183      	streq	r3, [r0, #24]
 8006542:	f000 f81f 	bl	8006584 <__sfp>
 8006546:	6060      	str	r0, [r4, #4]
 8006548:	4620      	mov	r0, r4
 800654a:	f000 f81b 	bl	8006584 <__sfp>
 800654e:	60a0      	str	r0, [r4, #8]
 8006550:	4620      	mov	r0, r4
 8006552:	f000 f817 	bl	8006584 <__sfp>
 8006556:	2200      	movs	r2, #0
 8006558:	60e0      	str	r0, [r4, #12]
 800655a:	2104      	movs	r1, #4
 800655c:	6860      	ldr	r0, [r4, #4]
 800655e:	f7ff ffa7 	bl	80064b0 <std.isra.0>
 8006562:	2201      	movs	r2, #1
 8006564:	2109      	movs	r1, #9
 8006566:	68a0      	ldr	r0, [r4, #8]
 8006568:	f7ff ffa2 	bl	80064b0 <std.isra.0>
 800656c:	2202      	movs	r2, #2
 800656e:	2112      	movs	r1, #18
 8006570:	68e0      	ldr	r0, [r4, #12]
 8006572:	f7ff ff9d 	bl	80064b0 <std.isra.0>
 8006576:	2301      	movs	r3, #1
 8006578:	61a3      	str	r3, [r4, #24]
 800657a:	bd10      	pop	{r4, pc}
 800657c:	08006a30 	.word	0x08006a30
 8006580:	080064a5 	.word	0x080064a5

08006584 <__sfp>:
 8006584:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 8006586:	4b1c      	ldr	r3, [pc, #112]	; (80065f8 <__sfp+0x74>)
 8006588:	4607      	mov	r7, r0
 800658a:	681e      	ldr	r6, [r3, #0]
 800658c:	69b3      	ldr	r3, [r6, #24]
 800658e:	b913      	cbnz	r3, 8006596 <__sfp+0x12>
 8006590:	4630      	mov	r0, r6
 8006592:	f7ff ffc7 	bl	8006524 <__sinit>
 8006596:	3648      	adds	r6, #72	; 0x48
 8006598:	68b4      	ldr	r4, [r6, #8]
 800659a:	6873      	ldr	r3, [r6, #4]
 800659c:	3b01      	subs	r3, #1
 800659e:	d503      	bpl.n	80065a8 <__sfp+0x24>
 80065a0:	6833      	ldr	r3, [r6, #0]
 80065a2:	b133      	cbz	r3, 80065b2 <__sfp+0x2e>
 80065a4:	6836      	ldr	r6, [r6, #0]
 80065a6:	e7f7      	b.n	8006598 <__sfp+0x14>
 80065a8:	f9b4 500c 	ldrsh.w	r5, [r4, #12]
 80065ac:	b16d      	cbz	r5, 80065ca <__sfp+0x46>
 80065ae:	3468      	adds	r4, #104	; 0x68
 80065b0:	e7f4      	b.n	800659c <__sfp+0x18>
 80065b2:	2104      	movs	r1, #4
 80065b4:	4638      	mov	r0, r7
 80065b6:	f7ff ff9f 	bl	80064f8 <__sfmoreglue>
 80065ba:	6030      	str	r0, [r6, #0]
 80065bc:	2800      	cmp	r0, #0
 80065be:	d1f1      	bne.n	80065a4 <__sfp+0x20>
 80065c0:	230c      	movs	r3, #12
 80065c2:	4604      	mov	r4, r0
 80065c4:	603b      	str	r3, [r7, #0]
 80065c6:	4620      	mov	r0, r4
 80065c8:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
 80065ca:	f64f 73ff 	movw	r3, #65535	; 0xffff
 80065ce:	81e3      	strh	r3, [r4, #14]
 80065d0:	2301      	movs	r3, #1
 80065d2:	6665      	str	r5, [r4, #100]	; 0x64
 80065d4:	81a3      	strh	r3, [r4, #12]
 80065d6:	6025      	str	r5, [r4, #0]
 80065d8:	60a5      	str	r5, [r4, #8]
 80065da:	6065      	str	r5, [r4, #4]
 80065dc:	6125      	str	r5, [r4, #16]
 80065de:	6165      	str	r5, [r4, #20]
 80065e0:	61a5      	str	r5, [r4, #24]
 80065e2:	2208      	movs	r2, #8
 80065e4:	4629      	mov	r1, r5
 80065e6:	f104 005c 	add.w	r0, r4, #92	; 0x5c
 80065ea:	f7ff fcc7 	bl	8005f7c <memset>
 80065ee:	6365      	str	r5, [r4, #52]	; 0x34
 80065f0:	63a5      	str	r5, [r4, #56]	; 0x38
 80065f2:	64a5      	str	r5, [r4, #72]	; 0x48
 80065f4:	64e5      	str	r5, [r4, #76]	; 0x4c
 80065f6:	e7e6      	b.n	80065c6 <__sfp+0x42>
 80065f8:	08006a30 	.word	0x08006a30

080065fc <_fwalk_reent>:
 80065fc:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
 8006600:	4680      	mov	r8, r0
 8006602:	4689      	mov	r9, r1
 8006604:	2600      	movs	r6, #0
 8006606:	f100 0448 	add.w	r4, r0, #72	; 0x48
 800660a:	b914      	cbnz	r4, 8006612 <_fwalk_reent+0x16>
 800660c:	4630      	mov	r0, r6
 800660e:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
 8006612:	68a5      	ldr	r5, [r4, #8]
 8006614:	6867      	ldr	r7, [r4, #4]
 8006616:	3f01      	subs	r7, #1
 8006618:	d501      	bpl.n	800661e <_fwalk_reent+0x22>
 800661a:	6824      	ldr	r4, [r4, #0]
 800661c:	e7f5      	b.n	800660a <_fwalk_reent+0xe>
 800661e:	89ab      	ldrh	r3, [r5, #12]
 8006620:	2b01      	cmp	r3, #1
 8006622:	d907      	bls.n	8006634 <_fwalk_reent+0x38>
 8006624:	f9b5 300e 	ldrsh.w	r3, [r5, #14]
 8006628:	3301      	adds	r3, #1
 800662a:	d003      	beq.n	8006634 <_fwalk_reent+0x38>
 800662c:	4629      	mov	r1, r5
 800662e:	4640      	mov	r0, r8
 8006630:	47c8      	blx	r9
 8006632:	4306      	orrs	r6, r0
 8006634:	3568      	adds	r5, #104	; 0x68
 8006636:	e7ee      	b.n	8006616 <_fwalk_reent+0x1a>

08006638 <__swhatbuf_r>:
 8006638:	b570      	push	{r4, r5, r6, lr}
 800663a:	460e      	mov	r6, r1
 800663c:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 8006640:	b090      	sub	sp, #64	; 0x40
 8006642:	2900      	cmp	r1, #0
 8006644:	4614      	mov	r4, r2
 8006646:	461d      	mov	r5, r3
 8006648:	da07      	bge.n	800665a <__swhatbuf_r+0x22>
 800664a:	2300      	movs	r3, #0
 800664c:	602b      	str	r3, [r5, #0]
 800664e:	89b3      	ldrh	r3, [r6, #12]
 8006650:	061a      	lsls	r2, r3, #24
 8006652:	d410      	bmi.n	8006676 <__swhatbuf_r+0x3e>
 8006654:	f44f 6380 	mov.w	r3, #1024	; 0x400
 8006658:	e00e      	b.n	8006678 <__swhatbuf_r+0x40>
 800665a:	aa01      	add	r2, sp, #4
 800665c:	f000 f978 	bl	8006950 <_fstat_r>
 8006660:	2800      	cmp	r0, #0
 8006662:	dbf2      	blt.n	800664a <__swhatbuf_r+0x12>
 8006664:	9a02      	ldr	r2, [sp, #8]
 8006666:	f402 4270 	and.w	r2, r2, #61440	; 0xf000
 800666a:	f5a2 5300 	sub.w	r3, r2, #8192	; 0x2000
 800666e:	425a      	negs	r2, r3
 8006670:	415a      	adcs	r2, r3
 8006672:	602a      	str	r2, [r5, #0]
 8006674:	e7ee      	b.n	8006654 <__swhatbuf_r+0x1c>
 8006676:	2340      	movs	r3, #64	; 0x40
 8006678:	2000      	movs	r0, #0
 800667a:	6023      	str	r3, [r4, #0]
 800667c:	b010      	add	sp, #64	; 0x40
 800667e:	bd70      	pop	{r4, r5, r6, pc}

08006680 <__smakebuf_r>:
 8006680:	898b      	ldrh	r3, [r1, #12]
 8006682:	b573      	push	{r0, r1, r4, r5, r6, lr}
 8006684:	079d      	lsls	r5, r3, #30
 8006686:	4606      	mov	r6, r0
 8006688:	460c      	mov	r4, r1
 800668a:	d507      	bpl.n	800669c <__smakebuf_r+0x1c>
 800668c:	f104 0347 	add.w	r3, r4, #71	; 0x47
 8006690:	6023      	str	r3, [r4, #0]
 8006692:	6123      	str	r3, [r4, #16]
 8006694:	2301      	movs	r3, #1
 8006696:	6163      	str	r3, [r4, #20]
 8006698:	b002      	add	sp, #8
 800669a:	bd70      	pop	{r4, r5, r6, pc}
 800669c:	ab01      	add	r3, sp, #4
 800669e:	466a      	mov	r2, sp
 80066a0:	f7ff ffca 	bl	8006638 <__swhatbuf_r>
 80066a4:	9900      	ldr	r1, [sp, #0]
 80066a6:	4605      	mov	r5, r0
 80066a8:	4630      	mov	r0, r6
 80066aa:	f000 f87d 	bl	80067a8 <_malloc_r>
 80066ae:	b948      	cbnz	r0, 80066c4 <__smakebuf_r+0x44>
 80066b0:	f9b4 300c 	ldrsh.w	r3, [r4, #12]
 80066b4:	059a      	lsls	r2, r3, #22
 80066b6:	d4ef      	bmi.n	8006698 <__smakebuf_r+0x18>
 80066b8:	f023 0303 	bic.w	r3, r3, #3
 80066bc:	f043 0302 	orr.w	r3, r3, #2
 80066c0:	81a3      	strh	r3, [r4, #12]
 80066c2:	e7e3      	b.n	800668c <__smakebuf_r+0xc>
 80066c4:	4b0d      	ldr	r3, [pc, #52]	; (80066fc <__smakebuf_r+0x7c>)
 80066c6:	62b3      	str	r3, [r6, #40]	; 0x28
 80066c8:	89a3      	ldrh	r3, [r4, #12]
 80066ca:	6020      	str	r0, [r4, #0]
 80066cc:	f043 0380 	orr.w	r3, r3, #128	; 0x80
 80066d0:	81a3      	strh	r3, [r4, #12]
 80066d2:	9b00      	ldr	r3, [sp, #0]
 80066d4:	6120      	str	r0, [r4, #16]
 80066d6:	6163      	str	r3, [r4, #20]
 80066d8:	9b01      	ldr	r3, [sp, #4]
 80066da:	b15b      	cbz	r3, 80066f4 <__smakebuf_r+0x74>
 80066dc:	f9b4 100e 	ldrsh.w	r1, [r4, #14]
 80066e0:	4630      	mov	r0, r6
 80066e2:	f000 f947 	bl	8006974 <_isatty_r>
 80066e6:	b128      	cbz	r0, 80066f4 <__smakebuf_r+0x74>
 80066e8:	89a3      	ldrh	r3, [r4, #12]
 80066ea:	f023 0303 	bic.w	r3, r3, #3
 80066ee:	f043 0301 	orr.w	r3, r3, #1
 80066f2:	81a3      	strh	r3, [r4, #12]
 80066f4:	89a3      	ldrh	r3, [r4, #12]
 80066f6:	431d      	orrs	r5, r3
 80066f8:	81a5      	strh	r5, [r4, #12]
 80066fa:	e7cd      	b.n	8006698 <__smakebuf_r+0x18>
 80066fc:	080064a5 	.word	0x080064a5

08006700 <malloc>:
 8006700:	4b02      	ldr	r3, [pc, #8]	; (800670c <malloc+0xc>)
 8006702:	4601      	mov	r1, r0
 8006704:	6818      	ldr	r0, [r3, #0]
 8006706:	f000 b84f 	b.w	80067a8 <_malloc_r>
 800670a:	bf00      	nop
 800670c:	2000000c 	.word	0x2000000c

08006710 <_free_r>:
 8006710:	b538      	push	{r3, r4, r5, lr}
 8006712:	4605      	mov	r5, r0
 8006714:	2900      	cmp	r1, #0
 8006716:	d043      	beq.n	80067a0 <_free_r+0x90>
 8006718:	f851 3c04 	ldr.w	r3, [r1, #-4]
 800671c:	1f0c      	subs	r4, r1, #4
 800671e:	2b00      	cmp	r3, #0
 8006720:	bfb8      	it	lt
 8006722:	18e4      	addlt	r4, r4, r3
 8006724:	f000 f948 	bl	80069b8 <__malloc_lock>
 8006728:	4a1e      	ldr	r2, [pc, #120]	; (80067a4 <_free_r+0x94>)
 800672a:	6813      	ldr	r3, [r2, #0]
 800672c:	4610      	mov	r0, r2
 800672e:	b933      	cbnz	r3, 800673e <_free_r+0x2e>
 8006730:	6063      	str	r3, [r4, #4]
 8006732:	6014      	str	r4, [r2, #0]
 8006734:	4628      	mov	r0, r5
 8006736:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
 800673a:	f000 b93e 	b.w	80069ba <__malloc_unlock>
 800673e:	42a3      	cmp	r3, r4
 8006740:	d90b      	bls.n	800675a <_free_r+0x4a>
 8006742:	6821      	ldr	r1, [r4, #0]
 8006744:	1862      	adds	r2, r4, r1
 8006746:	4293      	cmp	r3, r2
 8006748:	bf01      	itttt	eq
 800674a:	681a      	ldreq	r2, [r3, #0]
 800674c:	685b      	ldreq	r3, [r3, #4]
 800674e:	1852      	addeq	r2, r2, r1
 8006750:	6022      	streq	r2, [r4, #0]
 8006752:	6063      	str	r3, [r4, #4]
 8006754:	6004      	str	r4, [r0, #0]
 8006756:	e7ed      	b.n	8006734 <_free_r+0x24>
 8006758:	4613      	mov	r3, r2
 800675a:	685a      	ldr	r2, [r3, #4]
 800675c:	b10a      	cbz	r2, 8006762 <_free_r+0x52>
 800675e:	42a2      	cmp	r2, r4
 8006760:	d9fa      	bls.n	8006758 <_free_r+0x48>
 8006762:	6819      	ldr	r1, [r3, #0]
 8006764:	1858      	adds	r0, r3, r1
 8006766:	42a0      	cmp	r0, r4
 8006768:	d10b      	bne.n	8006782 <_free_r+0x72>
 800676a:	6820      	ldr	r0, [r4, #0]
 800676c:	4401      	add	r1, r0
 800676e:	1858      	adds	r0, r3, r1
 8006770:	4282      	cmp	r2, r0
 8006772:	6019      	str	r1, [r3, #0]
 8006774:	d1de      	bne.n	8006734 <_free_r+0x24>
 8006776:	6810      	ldr	r0, [r2, #0]
 8006778:	6852      	ldr	r2, [r2, #4]
 800677a:	4401      	add	r1, r0
 800677c:	6019      	str	r1, [r3, #0]
 800677e:	605a      	str	r2, [r3, #4]
 8006780:	e7d8      	b.n	8006734 <_free_r+0x24>
 8006782:	d902      	bls.n	800678a <_free_r+0x7a>
 8006784:	230c      	movs	r3, #12
 8006786:	602b      	str	r3, [r5, #0]
 8006788:	e7d4      	b.n	8006734 <_free_r+0x24>
 800678a:	6820      	ldr	r0, [r4, #0]
 800678c:	1821      	adds	r1, r4, r0
 800678e:	428a      	cmp	r2, r1
 8006790:	bf01      	itttt	eq
 8006792:	6811      	ldreq	r1, [r2, #0]
 8006794:	6852      	ldreq	r2, [r2, #4]
 8006796:	1809      	addeq	r1, r1, r0
 8006798:	6021      	streq	r1, [r4, #0]
 800679a:	6062      	str	r2, [r4, #4]
 800679c:	605c      	str	r4, [r3, #4]
 800679e:	e7c9      	b.n	8006734 <_free_r+0x24>
 80067a0:	bd38      	pop	{r3, r4, r5, pc}
 80067a2:	bf00      	nop
 80067a4:	2000009c 	.word	0x2000009c

080067a8 <_malloc_r>:
 80067a8:	b570      	push	{r4, r5, r6, lr}
 80067aa:	1ccd      	adds	r5, r1, #3
 80067ac:	f025 0503 	bic.w	r5, r5, #3
 80067b0:	3508      	adds	r5, #8
 80067b2:	2d0c      	cmp	r5, #12
 80067b4:	bf38      	it	cc
 80067b6:	250c      	movcc	r5, #12
 80067b8:	2d00      	cmp	r5, #0
 80067ba:	4606      	mov	r6, r0
 80067bc:	db01      	blt.n	80067c2 <_malloc_r+0x1a>
 80067be:	42a9      	cmp	r1, r5
 80067c0:	d903      	bls.n	80067ca <_malloc_r+0x22>
 80067c2:	230c      	movs	r3, #12
 80067c4:	6033      	str	r3, [r6, #0]
 80067c6:	2000      	movs	r0, #0
 80067c8:	bd70      	pop	{r4, r5, r6, pc}
 80067ca:	f000 f8f5 	bl	80069b8 <__malloc_lock>
 80067ce:	4a23      	ldr	r2, [pc, #140]	; (800685c <_malloc_r+0xb4>)
 80067d0:	6814      	ldr	r4, [r2, #0]
 80067d2:	4621      	mov	r1, r4
 80067d4:	b991      	cbnz	r1, 80067fc <_malloc_r+0x54>
 80067d6:	4c22      	ldr	r4, [pc, #136]	; (8006860 <_malloc_r+0xb8>)
 80067d8:	6823      	ldr	r3, [r4, #0]
 80067da:	b91b      	cbnz	r3, 80067e4 <_malloc_r+0x3c>
 80067dc:	4630      	mov	r0, r6
 80067de:	f000 f841 	bl	8006864 <_sbrk_r>
 80067e2:	6020      	str	r0, [r4, #0]
 80067e4:	4629      	mov	r1, r5
 80067e6:	4630      	mov	r0, r6
 80067e8:	f000 f83c 	bl	8006864 <_sbrk_r>
 80067ec:	1c43      	adds	r3, r0, #1
 80067ee:	d126      	bne.n	800683e <_malloc_r+0x96>
 80067f0:	230c      	movs	r3, #12
 80067f2:	4630      	mov	r0, r6
 80067f4:	6033      	str	r3, [r6, #0]
 80067f6:	f000 f8e0 	bl	80069ba <__malloc_unlock>
 80067fa:	e7e4      	b.n	80067c6 <_malloc_r+0x1e>
 80067fc:	680b      	ldr	r3, [r1, #0]
 80067fe:	1b5b      	subs	r3, r3, r5
 8006800:	d41a      	bmi.n	8006838 <_malloc_r+0x90>
 8006802:	2b0b      	cmp	r3, #11
 8006804:	d90f      	bls.n	8006826 <_malloc_r+0x7e>
 8006806:	600b      	str	r3, [r1, #0]
 8006808:	18cc      	adds	r4, r1, r3
 800680a:	50cd      	str	r5, [r1, r3]
 800680c:	4630      	mov	r0, r6
 800680e:	f000 f8d4 	bl	80069ba <__malloc_unlock>
 8006812:	f104 000b 	add.w	r0, r4, #11
 8006816:	1d23      	adds	r3, r4, #4
 8006818:	f020 0007 	bic.w	r0, r0, #7
 800681c:	1ac3      	subs	r3, r0, r3
 800681e:	d01b      	beq.n	8006858 <_malloc_r+0xb0>
 8006820:	425a      	negs	r2, r3
 8006822:	50e2      	str	r2, [r4, r3]
 8006824:	bd70      	pop	{r4, r5, r6, pc}
 8006826:	428c      	cmp	r4, r1
 8006828:	bf0b      	itete	eq
 800682a:	6863      	ldreq	r3, [r4, #4]
 800682c:	684b      	ldrne	r3, [r1, #4]
 800682e:	6013      	streq	r3, [r2, #0]
 8006830:	6063      	strne	r3, [r4, #4]
 8006832:	bf18      	it	ne
 8006834:	460c      	movne	r4, r1
 8006836:	e7e9      	b.n	800680c <_malloc_r+0x64>
 8006838:	460c      	mov	r4, r1
 800683a:	6849      	ldr	r1, [r1, #4]
 800683c:	e7ca      	b.n	80067d4 <_malloc_r+0x2c>
 800683e:	1cc4      	adds	r4, r0, #3
 8006840:	f024 0403 	bic.w	r4, r4, #3
 8006844:	42a0      	cmp	r0, r4
 8006846:	d005      	beq.n	8006854 <_malloc_r+0xac>
 8006848:	1a21      	subs	r1, r4, r0
 800684a:	4630      	mov	r0, r6
 800684c:	f000 f80a 	bl	8006864 <_sbrk_r>
 8006850:	3001      	adds	r0, #1
 8006852:	d0cd      	beq.n	80067f0 <_malloc_r+0x48>
 8006854:	6025      	str	r5, [r4, #0]
 8006856:	e7d9      	b.n	800680c <_malloc_r+0x64>
 8006858:	bd70      	pop	{r4, r5, r6, pc}
 800685a:	bf00      	nop
 800685c:	2000009c 	.word	0x2000009c
 8006860:	200000a0 	.word	0x200000a0

08006864 <_sbrk_r>:
 8006864:	b538      	push	{r3, r4, r5, lr}
 8006866:	2300      	movs	r3, #0
 8006868:	4c05      	ldr	r4, [pc, #20]	; (8006880 <_sbrk_r+0x1c>)
 800686a:	4605      	mov	r5, r0
 800686c:	4608      	mov	r0, r1
 800686e:	6023      	str	r3, [r4, #0]
 8006870:	f7ff fae8 	bl	8005e44 <_sbrk>
 8006874:	1c43      	adds	r3, r0, #1
 8006876:	d102      	bne.n	800687e <_sbrk_r+0x1a>
 8006878:	6823      	ldr	r3, [r4, #0]
 800687a:	b103      	cbz	r3, 800687e <_sbrk_r+0x1a>
 800687c:	602b      	str	r3, [r5, #0]
 800687e:	bd38      	pop	{r3, r4, r5, pc}
 8006880:	200001d4 	.word	0x200001d4

08006884 <__sread>:
 8006884:	b510      	push	{r4, lr}
 8006886:	460c      	mov	r4, r1
 8006888:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 800688c:	f000 f896 	bl	80069bc <_read_r>
 8006890:	2800      	cmp	r0, #0
 8006892:	bfab      	itete	ge
 8006894:	6d63      	ldrge	r3, [r4, #84]	; 0x54
 8006896:	89a3      	ldrhlt	r3, [r4, #12]
 8006898:	181b      	addge	r3, r3, r0
 800689a:	f423 5380 	biclt.w	r3, r3, #4096	; 0x1000
 800689e:	bfac      	ite	ge
 80068a0:	6563      	strge	r3, [r4, #84]	; 0x54
 80068a2:	81a3      	strhlt	r3, [r4, #12]
 80068a4:	bd10      	pop	{r4, pc}

080068a6 <__swrite>:
 80068a6:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
 80068aa:	461f      	mov	r7, r3
 80068ac:	898b      	ldrh	r3, [r1, #12]
 80068ae:	4605      	mov	r5, r0
 80068b0:	05db      	lsls	r3, r3, #23
 80068b2:	460c      	mov	r4, r1
 80068b4:	4616      	mov	r6, r2
 80068b6:	d505      	bpl.n	80068c4 <__swrite+0x1e>
 80068b8:	2302      	movs	r3, #2
 80068ba:	2200      	movs	r2, #0
 80068bc:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 80068c0:	f000 f868 	bl	8006994 <_lseek_r>
 80068c4:	89a3      	ldrh	r3, [r4, #12]
 80068c6:	4632      	mov	r2, r6
 80068c8:	f423 5380 	bic.w	r3, r3, #4096	; 0x1000
 80068cc:	81a3      	strh	r3, [r4, #12]
 80068ce:	f9b4 100e 	ldrsh.w	r1, [r4, #14]
 80068d2:	463b      	mov	r3, r7
 80068d4:	4628      	mov	r0, r5
 80068d6:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
 80068da:	f000 b817 	b.w	800690c <_write_r>

080068de <__sseek>:
 80068de:	b510      	push	{r4, lr}
 80068e0:	460c      	mov	r4, r1
 80068e2:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 80068e6:	f000 f855 	bl	8006994 <_lseek_r>
 80068ea:	1c43      	adds	r3, r0, #1
 80068ec:	89a3      	ldrh	r3, [r4, #12]
 80068ee:	bf15      	itete	ne
 80068f0:	6560      	strne	r0, [r4, #84]	; 0x54
 80068f2:	f423 5380 	biceq.w	r3, r3, #4096	; 0x1000
 80068f6:	f443 5380 	orrne.w	r3, r3, #4096	; 0x1000
 80068fa:	81a3      	strheq	r3, [r4, #12]
 80068fc:	bf18      	it	ne
 80068fe:	81a3      	strhne	r3, [r4, #12]
 8006900:	bd10      	pop	{r4, pc}

08006902 <__sclose>:
 8006902:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 8006906:	f000 b813 	b.w	8006930 <_close_r>
	...

0800690c <_write_r>:
 800690c:	b538      	push	{r3, r4, r5, lr}
 800690e:	4605      	mov	r5, r0
 8006910:	4608      	mov	r0, r1
 8006912:	4611      	mov	r1, r2
 8006914:	2200      	movs	r2, #0
 8006916:	4c05      	ldr	r4, [pc, #20]	; (800692c <_write_r+0x20>)
 8006918:	6022      	str	r2, [r4, #0]
 800691a:	461a      	mov	r2, r3
 800691c:	f7fe ff86 	bl	800582c <_write>
 8006920:	1c43      	adds	r3, r0, #1
 8006922:	d102      	bne.n	800692a <_write_r+0x1e>
 8006924:	6823      	ldr	r3, [r4, #0]
 8006926:	b103      	cbz	r3, 800692a <_write_r+0x1e>
 8006928:	602b      	str	r3, [r5, #0]
 800692a:	bd38      	pop	{r3, r4, r5, pc}
 800692c:	200001d4 	.word	0x200001d4

08006930 <_close_r>:
 8006930:	b538      	push	{r3, r4, r5, lr}
 8006932:	2300      	movs	r3, #0
 8006934:	4c05      	ldr	r4, [pc, #20]	; (800694c <_close_r+0x1c>)
 8006936:	4605      	mov	r5, r0
 8006938:	4608      	mov	r0, r1
 800693a:	6023      	str	r3, [r4, #0]
 800693c:	f7ff fa9c 	bl	8005e78 <_close>
 8006940:	1c43      	adds	r3, r0, #1
 8006942:	d102      	bne.n	800694a <_close_r+0x1a>
 8006944:	6823      	ldr	r3, [r4, #0]
 8006946:	b103      	cbz	r3, 800694a <_close_r+0x1a>
 8006948:	602b      	str	r3, [r5, #0]
 800694a:	bd38      	pop	{r3, r4, r5, pc}
 800694c:	200001d4 	.word	0x200001d4

08006950 <_fstat_r>:
 8006950:	b538      	push	{r3, r4, r5, lr}
 8006952:	2300      	movs	r3, #0
 8006954:	4c06      	ldr	r4, [pc, #24]	; (8006970 <_fstat_r+0x20>)
 8006956:	4605      	mov	r5, r0
 8006958:	4608      	mov	r0, r1
 800695a:	4611      	mov	r1, r2
 800695c:	6023      	str	r3, [r4, #0]
 800695e:	f7ff fa8e 	bl	8005e7e <_fstat>
 8006962:	1c43      	adds	r3, r0, #1
 8006964:	d102      	bne.n	800696c <_fstat_r+0x1c>
 8006966:	6823      	ldr	r3, [r4, #0]
 8006968:	b103      	cbz	r3, 800696c <_fstat_r+0x1c>
 800696a:	602b      	str	r3, [r5, #0]
 800696c:	bd38      	pop	{r3, r4, r5, pc}
 800696e:	bf00      	nop
 8006970:	200001d4 	.word	0x200001d4

08006974 <_isatty_r>:
 8006974:	b538      	push	{r3, r4, r5, lr}
 8006976:	2300      	movs	r3, #0
 8006978:	4c05      	ldr	r4, [pc, #20]	; (8006990 <_isatty_r+0x1c>)
 800697a:	4605      	mov	r5, r0
 800697c:	4608      	mov	r0, r1
 800697e:	6023      	str	r3, [r4, #0]
 8006980:	f7ff fa82 	bl	8005e88 <_isatty>
 8006984:	1c43      	adds	r3, r0, #1
 8006986:	d102      	bne.n	800698e <_isatty_r+0x1a>
 8006988:	6823      	ldr	r3, [r4, #0]
 800698a:	b103      	cbz	r3, 800698e <_isatty_r+0x1a>
 800698c:	602b      	str	r3, [r5, #0]
 800698e:	bd38      	pop	{r3, r4, r5, pc}
 8006990:	200001d4 	.word	0x200001d4

08006994 <_lseek_r>:
 8006994:	b538      	push	{r3, r4, r5, lr}
 8006996:	4605      	mov	r5, r0
 8006998:	4608      	mov	r0, r1
 800699a:	4611      	mov	r1, r2
 800699c:	2200      	movs	r2, #0
 800699e:	4c05      	ldr	r4, [pc, #20]	; (80069b4 <_lseek_r+0x20>)
 80069a0:	6022      	str	r2, [r4, #0]
 80069a2:	461a      	mov	r2, r3
 80069a4:	f7ff fa72 	bl	8005e8c <_lseek>
 80069a8:	1c43      	adds	r3, r0, #1
 80069aa:	d102      	bne.n	80069b2 <_lseek_r+0x1e>
 80069ac:	6823      	ldr	r3, [r4, #0]
 80069ae:	b103      	cbz	r3, 80069b2 <_lseek_r+0x1e>
 80069b0:	602b      	str	r3, [r5, #0]
 80069b2:	bd38      	pop	{r3, r4, r5, pc}
 80069b4:	200001d4 	.word	0x200001d4

080069b8 <__malloc_lock>:
 80069b8:	4770      	bx	lr

080069ba <__malloc_unlock>:
 80069ba:	4770      	bx	lr

080069bc <_read_r>:
 80069bc:	b538      	push	{r3, r4, r5, lr}
 80069be:	4605      	mov	r5, r0
 80069c0:	4608      	mov	r0, r1
 80069c2:	4611      	mov	r1, r2
 80069c4:	2200      	movs	r2, #0
 80069c6:	4c05      	ldr	r4, [pc, #20]	; (80069dc <_read_r+0x20>)
 80069c8:	6022      	str	r2, [r4, #0]
 80069ca:	461a      	mov	r2, r3
 80069cc:	f7ff fa2c 	bl	8005e28 <_read>
 80069d0:	1c43      	adds	r3, r0, #1
 80069d2:	d102      	bne.n	80069da <_read_r+0x1e>
 80069d4:	6823      	ldr	r3, [r4, #0]
 80069d6:	b103      	cbz	r3, 80069da <_read_r+0x1e>
 80069d8:	602b      	str	r3, [r5, #0]
 80069da:	bd38      	pop	{r3, r4, r5, pc}
 80069dc:	200001d4 	.word	0x200001d4

080069e0 <_init>:
 80069e0:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 80069e2:	bf00      	nop
 80069e4:	bcf8      	pop	{r3, r4, r5, r6, r7}
 80069e6:	bc08      	pop	{r3}
 80069e8:	469e      	mov	lr, r3
 80069ea:	4770      	bx	lr

080069ec <_fini>:
 80069ec:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 80069ee:	bf00      	nop
 80069f0:	bcf8      	pop	{r3, r4, r5, r6, r7}
 80069f2:	bc08      	pop	{r3}
 80069f4:	469e      	mov	lr, r3
 80069f6:	4770      	bx	lr