/* * zig_operate.c * * Created on: 2019. 7. 26. * Author: parkyj */ #include "zig_operate.h" /* * * * * * * #define Struct* * * * * * * */ PLL_Setting_st Pll_1_8GHz_DL = { PLL_CLK_GPIO_Port, PLL_CLK_Pin, PLL_DATA_GPIO_Port, PLL_DATA_Pin, PLL_EN_1_8G_DL_GPIO_Port, PLL_EN_1_8G_DL_Pin, }; PLL_Setting_st Pll_1_8GHz_UL = { PLL_CLK_GPIO_Port, PLL_CLK_Pin, PLL_DATA_GPIO_Port, PLL_DATA_Pin, PLL_EN_1_8G_UL_GPIO_Port, PLL_EN_1_8G_UL_Pin, }; PLL_Setting_st Pll_2_1GHz_DL = { PLL_CLK_GPIO_Port, PLL_CLK_Pin, PLL_DATA_GPIO_Port, PLL_DATA_Pin, PLL_EN_2_1G_DL_GPIO_Port, PLL_EN_2_1G_DL_Pin, }; PLL_Setting_st Pll_2_1GHz_UL = { PLL_CLK_GPIO_Port, PLL_CLK_Pin, PLL_DATA_GPIO_Port, PLL_DATA_Pin, PLL_EN_2_1G_UL_GPIO_Port, PLL_EN_2_1G_UL_Pin, }; /* * * * * * * * NOT YET * * * * * * * */ PLL_Setting_st Pll_3_5GHz_DL = { ATT_CLK_3_5G_GPIO_Port, ATT_EN_3_5G_Pin, PLL_DATA_GPIO_Port, PLL_DATA_Pin, PLL_EN_2_1G_DL_GPIO_Port, PLL_EN_2_1G_DL_Pin, }; PLL_Setting_st Pll_3_5GHz_UL = { PLL_CLK_GPIO_Port, PLL_CLK_Pin, PLL_DATA_GPIO_Port, PLL_DATA_Pin, PLL_EN_2_1G_UL_GPIO_Port, PLL_EN_2_1G_UL_Pin, }; /* * * * * * * * ATTEN * * * * * * * */ ATTEN_Setting_st Atten_1_8Ghz_DL1 ={ ATT_CLK_GPIO_Port, ATT_CLK_Pin, ATT_DATA_GPIO_Port, ATT_DATA_Pin, ATT_EN_1_8G_DL1_GPIO_Port, ATT_EN_1_8G_DL1_Pin, PATH_EN_1_8G_DL_GPIO_Port, PATH_EN_1_8G_DL_Pin, }; ATTEN_Setting_st Atten_1_8Ghz_DL2 ={ ATT_CLK_GPIO_Port, ATT_CLK_Pin, ATT_DATA_GPIO_Port, ATT_DATA_Pin, ATT_EN_1_8G_DL2_GPIO_Port, ATT_EN_1_8G_DL2_Pin, PATH_EN_1_8G_DL_GPIO_Port, PATH_EN_1_8G_DL_Pin, }; ATTEN_Setting_st Atten_1_8Ghz_UL1 ={ ATT_CLK_GPIO_Port, ATT_CLK_Pin, ATT_DATA_GPIO_Port, ATT_DATA_Pin, ATT_EN_1_8G_UL1_GPIO_Port, ATT_EN_1_8G_UL1_Pin, PATH_EN_1_8G_UL_GPIO_Port, PATH_EN_1_8G_UL_Pin, }; ATTEN_Setting_st Atten_1_8Ghz_UL2 ={ ATT_CLK_GPIO_Port, ATT_CLK_Pin, ATT_DATA_GPIO_Port, ATT_DATA_Pin, ATT_EN_1_8G_UL2_GPIO_Port, ATT_EN_1_8G_UL2_Pin, PATH_EN_1_8G_UL_GPIO_Port, PATH_EN_1_8G_UL_Pin, }; ATTEN_Setting_st Atten_1_8Ghz_UL3 ={ ATT_CLK_GPIO_Port, ATT_CLK_Pin, ATT_DATA_GPIO_Port, ATT_DATA_Pin, ATT_EN_1_8G_UL3_GPIO_Port, ATT_EN_1_8G_UL3_Pin, PATH_EN_1_8G_UL_GPIO_Port, PATH_EN_1_8G_UL_Pin, }; ATTEN_Setting_st Atten_1_8Ghz_UL4 ={ ATT_CLK_GPIO_Port, ATT_CLK_Pin, ATT_DATA_GPIO_Port, ATT_DATA_Pin, ATT_EN_1_8G_UL4_GPIO_Port, ATT_EN_1_8G_UL4_Pin, PATH_EN_1_8G_UL_GPIO_Port, PATH_EN_1_8G_UL_Pin, }; ATTEN_Setting_st Atten_2_1Ghz_DL1 ={ ATT_CLK_GPIO_Port, ATT_CLK_Pin, ATT_DATA_GPIO_Port, ATT_DATA_Pin, ATT_EN_2_1G_DL1_GPIO_Port, ATT_EN_2_1G_DL1_Pin, PATH_EN_2_1G_DL_GPIO_Port, PATH_EN_2_1G_DL_Pin, }; ATTEN_Setting_st Atten_2_1Ghz_DL2 ={ ATT_CLK_GPIO_Port, ATT_CLK_Pin, ATT_DATA_GPIO_Port, ATT_DATA_Pin, ATT_EN_2_1G_DL2_GPIO_Port, ATT_EN_2_1G_DL2_Pin, PATH_EN_2_1G_DL_GPIO_Port, PATH_EN_2_1G_DL_Pin, }; ATTEN_Setting_st Atten_2_1Ghz_UL1 ={ ATT_CLK_GPIO_Port, ATT_CLK_Pin, ATT_DATA_GPIO_Port, ATT_DATA_Pin, ATT_EN_2_1G_UL1_GPIO_Port, ATT_EN_2_1G_UL1_Pin, PATH_EN_2_1G_UL_GPIO_Port, PATH_EN_2_1G_UL_Pin, }; ATTEN_Setting_st Atten_2_1Ghz_UL2 ={ ATT_CLK_GPIO_Port, ATT_CLK_Pin, ATT_DATA_GPIO_Port, ATT_DATA_Pin, ATT_EN_2_1G_UL2_GPIO_Port, ATT_EN_2_1G_UL2_Pin, PATH_EN_2_1G_UL_GPIO_Port, PATH_EN_2_1G_UL_Pin, }; ATTEN_Setting_st Atten_2_1Ghz_UL3 ={ ATT_CLK_GPIO_Port, ATT_CLK_Pin, ATT_DATA_GPIO_Port, ATT_DATA_Pin, ATT_EN_2_1G_UL3_GPIO_Port, ATT_EN_2_1G_UL3_Pin, PATH_EN_2_1G_UL_GPIO_Port, PATH_EN_2_1G_UL_Pin, }; ATTEN_Setting_st Atten_2_1Ghz_UL4 ={ ATT_CLK_GPIO_Port, ATT_CLK_Pin, ATT_DATA_GPIO_Port, ATT_DATA_Pin, ATT_EN_2_1G_UL4_GPIO_Port, ATT_EN_2_1G_UL4_Pin, PATH_EN_2_1G_UL_GPIO_Port, PATH_EN_2_1G_UL_Pin, }; typedef enum{ TYPE_ATT_1_8GHz_DL1 = 1, TYPE_ATT_1_8GHz_DL2, TYPE_ATT_1_8GHz_UL1, TYPE_ATT_1_8GHz_UL2, TYPE_ATT_1_8GHz_UL3, //5 TYPE_ATT_1_8GHz_UL4, TYPE_ATT_2_1GHz_DL1, TYPE_ATT_2_1GHz_DL2, TYPE_ATT_2_1GHz_UL1, TYPE_ATT_2_1GHz_UL2, // 10 TYPE_ATT_2_1GHz_UL3, TYPE_ATT_2_1GHz_UL4, TYPE_ATT_3_5GHz_DL, TYPE_ATT_3_5GHz_UL, TYPE_ATT_3_5GHz_COM1, // 15 TYPE_ATT_3_5GHz_COM2, TYPE_ATT_3_5GHz_COM3, }Bluecell_Prot_t; typedef enum{ Header = 0, Length, Type, Crcindex, }Bluecell_Prot_p; bool RF_Data_Check(uint8_t* data_buf){ bool ret = false; bool crcret = STH30_CheckCrc(&data_buf[Type], data_buf[Length], data_buf[Crcindex]); if(data_buf[Header] == BLUECELL_HEADER){ /*HEADER CHECK*/ ret= true; } if(crcret == true){/*CRC CHECK*/ ret = true; } return ret; } bool RF_Ctrl_Main(uint8_t* data_buf){ bool ret = false; Bluecell_Prot_t type = data_buf[Type]; RF_Data_Check(&data_buf[Header]); /* ERROR CHECK */ switch(type){ case TYPE_ATT_1_8GHz_DL1: break; case TYPE_ATT_1_8GHz_DL2: break; case TYPE_ATT_1_8GHz_UL1: break; case TYPE_ATT_1_8GHz_UL2: break; case TYPE_ATT_1_8GHz_UL3: break;//5 case TYPE_ATT_1_8GHz_UL4:break; case TYPE_ATT_2_1GHz_DL1:break; case TYPE_ATT_2_1GHz_DL2:break; case TYPE_ATT_2_1GHz_UL1:break; case TYPE_ATT_2_1GHz_UL2: break;// 10 case TYPE_ATT_2_1GHz_UL3:break; case TYPE_ATT_2_1GHz_UL4: break; case TYPE_ATT_3_5GHz_DL:break; case TYPE_ATT_3_5GHz_UL:break; case TYPE_ATT_3_5GHz_COM1: break;// 15 case TYPE_ATT_3_5GHz_COM2:break; case TYPE_ATT_3_5GHz_COM3: break; default: printf("Function : %s LINE : %d type : %d \r\n",__func__,__LINE__,type); break; } return ret; }