STM32F103_ATTEN_PLL_Zig.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000001e4 08004000 08004000 00004000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 000030ac 080041e4 080041e4 000041e4 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000104 08007290 08007290 00007290 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .init_array 00000004 08007394 08007394 00007394 2**2 CONTENTS, ALLOC, LOAD, DATA 4 .fini_array 00000004 08007398 08007398 00007398 2**2 CONTENTS, ALLOC, LOAD, DATA 5 .data 00000070 20000000 0800739c 00010000 2**2 CONTENTS, ALLOC, LOAD, DATA 6 .bss 0000077c 20000070 0800740c 00010070 2**2 ALLOC 7 ._user_heap_stack 00000600 200007ec 0800740c 000107ec 2**0 ALLOC 8 .ARM.attributes 00000029 00000000 00000000 00010070 2**0 CONTENTS, READONLY 9 .debug_info 00017979 00000000 00000000 00010099 2**0 CONTENTS, READONLY, DEBUGGING 10 .debug_abbrev 00003109 00000000 00000000 00027a12 2**0 CONTENTS, READONLY, DEBUGGING 11 .debug_loc 00007292 00000000 00000000 0002ab1b 2**0 CONTENTS, READONLY, DEBUGGING 12 .debug_aranges 00000aa0 00000000 00000000 00031db0 2**3 CONTENTS, READONLY, DEBUGGING 13 .debug_ranges 00000e10 00000000 00000000 00032850 2**3 CONTENTS, READONLY, DEBUGGING 14 .debug_line 000067ab 00000000 00000000 00033660 2**0 CONTENTS, READONLY, DEBUGGING 15 .debug_str 00004157 00000000 00000000 00039e0b 2**0 CONTENTS, READONLY, DEBUGGING 16 .comment 0000007c 00000000 00000000 0003df62 2**0 CONTENTS, READONLY 17 .debug_frame 00002638 00000000 00000000 0003dfe0 2**2 CONTENTS, READONLY, DEBUGGING Disassembly of section .text: 080041e4 <__do_global_dtors_aux>: 80041e4: b510 push {r4, lr} 80041e6: 4c05 ldr r4, [pc, #20] ; (80041fc <__do_global_dtors_aux+0x18>) 80041e8: 7823 ldrb r3, [r4, #0] 80041ea: b933 cbnz r3, 80041fa <__do_global_dtors_aux+0x16> 80041ec: 4b04 ldr r3, [pc, #16] ; (8004200 <__do_global_dtors_aux+0x1c>) 80041ee: b113 cbz r3, 80041f6 <__do_global_dtors_aux+0x12> 80041f0: 4804 ldr r0, [pc, #16] ; (8004204 <__do_global_dtors_aux+0x20>) 80041f2: f3af 8000 nop.w 80041f6: 2301 movs r3, #1 80041f8: 7023 strb r3, [r4, #0] 80041fa: bd10 pop {r4, pc} 80041fc: 20000070 .word 0x20000070 8004200: 00000000 .word 0x00000000 8004204: 08007278 .word 0x08007278 08004208 : 8004208: b508 push {r3, lr} 800420a: 4b03 ldr r3, [pc, #12] ; (8004218 ) 800420c: b11b cbz r3, 8004216 800420e: 4903 ldr r1, [pc, #12] ; (800421c ) 8004210: 4803 ldr r0, [pc, #12] ; (8004220 ) 8004212: f3af 8000 nop.w 8004216: bd08 pop {r3, pc} 8004218: 00000000 .word 0x00000000 800421c: 20000074 .word 0x20000074 8004220: 08007278 .word 0x08007278 08004224 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8004224: b538 push {r3, r4, r5, lr} /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 8004226: 4b0e ldr r3, [pc, #56] ; (8004260 ) { 8004228: 4605 mov r5, r0 if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 800422a: 7818 ldrb r0, [r3, #0] 800422c: f44f 737a mov.w r3, #1000 ; 0x3e8 8004230: fbb3 f3f0 udiv r3, r3, r0 8004234: 4a0b ldr r2, [pc, #44] ; (8004264 ) 8004236: 6810 ldr r0, [r2, #0] 8004238: fbb0 f0f3 udiv r0, r0, r3 800423c: f000 f9ce bl 80045dc 8004240: 4604 mov r4, r0 8004242: b958 cbnz r0, 800425c { return HAL_ERROR; } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 8004244: 2d0f cmp r5, #15 8004246: d809 bhi.n 800425c { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 8004248: 4602 mov r2, r0 800424a: 4629 mov r1, r5 800424c: f04f 30ff mov.w r0, #4294967295 8004250: f000 f984 bl 800455c uwTickPrio = TickPriority; 8004254: 4b04 ldr r3, [pc, #16] ; (8004268 ) 8004256: 4620 mov r0, r4 8004258: 601d str r5, [r3, #0] 800425a: bd38 pop {r3, r4, r5, pc} return HAL_ERROR; 800425c: 2001 movs r0, #1 return HAL_ERROR; } /* Return function status */ return HAL_OK; } 800425e: bd38 pop {r3, r4, r5, pc} 8004260: 20000000 .word 0x20000000 8004264: 20000008 .word 0x20000008 8004268: 20000004 .word 0x20000004 0800426c : __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 800426c: 4a07 ldr r2, [pc, #28] ; (800428c ) { 800426e: b508 push {r3, lr} __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 8004270: 6813 ldr r3, [r2, #0] HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8004272: 2003 movs r0, #3 __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 8004274: f043 0310 orr.w r3, r3, #16 8004278: 6013 str r3, [r2, #0] HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 800427a: f000 f95d bl 8004538 HAL_InitTick(TICK_INT_PRIORITY); 800427e: 2000 movs r0, #0 8004280: f7ff ffd0 bl 8004224 HAL_MspInit(); 8004284: f001 fdc0 bl 8005e08 } 8004288: 2000 movs r0, #0 800428a: bd08 pop {r3, pc} 800428c: 40022000 .word 0x40022000 08004290 : * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { uwTick += uwTickFreq; 8004290: 4a03 ldr r2, [pc, #12] ; (80042a0 ) 8004292: 4b04 ldr r3, [pc, #16] ; (80042a4 ) 8004294: 6811 ldr r1, [r2, #0] 8004296: 781b ldrb r3, [r3, #0] 8004298: 440b add r3, r1 800429a: 6013 str r3, [r2, #0] 800429c: 4770 bx lr 800429e: bf00 nop 80042a0: 200004a0 .word 0x200004a0 80042a4: 20000000 .word 0x20000000 080042a8 : * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { return uwTick; 80042a8: 4b01 ldr r3, [pc, #4] ; (80042b0 ) 80042aa: 6818 ldr r0, [r3, #0] } 80042ac: 4770 bx lr 80042ae: bf00 nop 80042b0: 200004a0 .word 0x200004a0 080042b4 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 80042b4: b538 push {r3, r4, r5, lr} 80042b6: 4604 mov r4, r0 uint32_t tickstart = HAL_GetTick(); 80042b8: f7ff fff6 bl 80042a8 80042bc: 4605 mov r5, r0 uint32_t wait = Delay; /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 80042be: 1c63 adds r3, r4, #1 { wait += (uint32_t)(uwTickFreq); 80042c0: bf1e ittt ne 80042c2: 4b04 ldrne r3, [pc, #16] ; (80042d4 ) 80042c4: 781b ldrbne r3, [r3, #0] 80042c6: 18e4 addne r4, r4, r3 } while ((HAL_GetTick() - tickstart) < wait) 80042c8: f7ff ffee bl 80042a8 80042cc: 1b40 subs r0, r0, r5 80042ce: 4284 cmp r4, r0 80042d0: d8fa bhi.n 80042c8 { } } 80042d2: bd38 pop {r3, r4, r5, pc} 80042d4: 20000000 .word 0x20000000 080042d8 : * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; __IO uint32_t wait_loop_index = 0U; 80042d8: 2300 movs r3, #0 { 80042da: b573 push {r0, r1, r4, r5, r6, lr} __IO uint32_t wait_loop_index = 0U; 80042dc: 9301 str r3, [sp, #4] assert_param(IS_ADC_CHANNEL(sConfig->Channel)); assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); /* Process locked */ __HAL_LOCK(hadc); 80042de: f890 3024 ldrb.w r3, [r0, #36] ; 0x24 80042e2: 2b01 cmp r3, #1 80042e4: d074 beq.n 80043d0 80042e6: 2301 movs r3, #1 /* Regular sequence configuration */ /* For Rank 1 to 6 */ if (sConfig->Rank < 7U) 80042e8: 684d ldr r5, [r1, #4] __HAL_LOCK(hadc); 80042ea: f880 3024 strb.w r3, [r0, #36] ; 0x24 if (sConfig->Rank < 7U) 80042ee: 2d06 cmp r5, #6 80042f0: 6802 ldr r2, [r0, #0] 80042f2: ea4f 0385 mov.w r3, r5, lsl #2 80042f6: 680c ldr r4, [r1, #0] 80042f8: d825 bhi.n 8004346 { MODIFY_REG(hadc->Instance->SQR3 , 80042fa: 442b add r3, r5 80042fc: 251f movs r5, #31 80042fe: 6b56 ldr r6, [r2, #52] ; 0x34 8004300: 3b05 subs r3, #5 8004302: 409d lsls r5, r3 8004304: ea26 0505 bic.w r5, r6, r5 8004308: fa04 f303 lsl.w r3, r4, r3 800430c: 432b orrs r3, r5 800430e: 6353 str r3, [r2, #52] ; 0x34 } /* Channel sampling time configuration */ /* For channels 10 to 17 */ if (sConfig->Channel >= ADC_CHANNEL_10) 8004310: 2c09 cmp r4, #9 8004312: ea4f 0344 mov.w r3, r4, lsl #1 8004316: 688d ldr r5, [r1, #8] 8004318: d92f bls.n 800437a { MODIFY_REG(hadc->Instance->SMPR1 , 800431a: 2607 movs r6, #7 800431c: 4423 add r3, r4 800431e: 68d1 ldr r1, [r2, #12] 8004320: 3b1e subs r3, #30 8004322: 409e lsls r6, r3 8004324: ea21 0106 bic.w r1, r1, r6 8004328: fa05 f303 lsl.w r3, r5, r3 800432c: 430b orrs r3, r1 800432e: 60d3 str r3, [r2, #12] ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); } /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ /* and VREFINT measurement path. */ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 8004330: f1a4 0310 sub.w r3, r4, #16 8004334: 2b01 cmp r3, #1 8004336: d92b bls.n 8004390 HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8004338: 2300 movs r3, #0 tmp_hal_status = HAL_ERROR; } } /* Process unlocked */ __HAL_UNLOCK(hadc); 800433a: 2200 movs r2, #0 800433c: f880 2024 strb.w r2, [r0, #36] ; 0x24 /* Return function status */ return tmp_hal_status; } 8004340: 4618 mov r0, r3 8004342: b002 add sp, #8 8004344: bd70 pop {r4, r5, r6, pc} else if (sConfig->Rank < 13U) 8004346: 2d0c cmp r5, #12 8004348: d80b bhi.n 8004362 MODIFY_REG(hadc->Instance->SQR2 , 800434a: 442b add r3, r5 800434c: 251f movs r5, #31 800434e: 6b16 ldr r6, [r2, #48] ; 0x30 8004350: 3b23 subs r3, #35 ; 0x23 8004352: 409d lsls r5, r3 8004354: ea26 0505 bic.w r5, r6, r5 8004358: fa04 f303 lsl.w r3, r4, r3 800435c: 432b orrs r3, r5 800435e: 6313 str r3, [r2, #48] ; 0x30 8004360: e7d6 b.n 8004310 MODIFY_REG(hadc->Instance->SQR1 , 8004362: 442b add r3, r5 8004364: 251f movs r5, #31 8004366: 6ad6 ldr r6, [r2, #44] ; 0x2c 8004368: 3b41 subs r3, #65 ; 0x41 800436a: 409d lsls r5, r3 800436c: ea26 0505 bic.w r5, r6, r5 8004370: fa04 f303 lsl.w r3, r4, r3 8004374: 432b orrs r3, r5 8004376: 62d3 str r3, [r2, #44] ; 0x2c 8004378: e7ca b.n 8004310 MODIFY_REG(hadc->Instance->SMPR2 , 800437a: 2607 movs r6, #7 800437c: 6911 ldr r1, [r2, #16] 800437e: 4423 add r3, r4 8004380: 409e lsls r6, r3 8004382: ea21 0106 bic.w r1, r1, r6 8004386: fa05 f303 lsl.w r3, r5, r3 800438a: 430b orrs r3, r1 800438c: 6113 str r3, [r2, #16] 800438e: e7cf b.n 8004330 if (hadc->Instance == ADC1) 8004390: 4b10 ldr r3, [pc, #64] ; (80043d4 ) 8004392: 429a cmp r2, r3 8004394: d116 bne.n 80043c4 if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET) 8004396: 6893 ldr r3, [r2, #8] 8004398: 021b lsls r3, r3, #8 800439a: d4cd bmi.n 8004338 SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); 800439c: 6893 ldr r3, [r2, #8] if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)) 800439e: 2c10 cmp r4, #16 SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); 80043a0: f443 0300 orr.w r3, r3, #8388608 ; 0x800000 80043a4: 6093 str r3, [r2, #8] if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)) 80043a6: d1c7 bne.n 8004338 wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); 80043a8: 4b0b ldr r3, [pc, #44] ; (80043d8 ) 80043aa: 4a0c ldr r2, [pc, #48] ; (80043dc ) 80043ac: 681b ldr r3, [r3, #0] 80043ae: fbb3 f2f2 udiv r2, r3, r2 80043b2: 230a movs r3, #10 80043b4: 4353 muls r3, r2 wait_loop_index--; 80043b6: 9301 str r3, [sp, #4] while(wait_loop_index != 0U) 80043b8: 9b01 ldr r3, [sp, #4] 80043ba: 2b00 cmp r3, #0 80043bc: d0bc beq.n 8004338 wait_loop_index--; 80043be: 9b01 ldr r3, [sp, #4] 80043c0: 3b01 subs r3, #1 80043c2: e7f8 b.n 80043b6 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 80043c4: 6a83 ldr r3, [r0, #40] ; 0x28 80043c6: f043 0320 orr.w r3, r3, #32 80043ca: 6283 str r3, [r0, #40] ; 0x28 tmp_hal_status = HAL_ERROR; 80043cc: 2301 movs r3, #1 80043ce: e7b4 b.n 800433a __HAL_LOCK(hadc); 80043d0: 2302 movs r3, #2 80043d2: e7b5 b.n 8004340 80043d4: 40012400 .word 0x40012400 80043d8: 20000008 .word 0x20000008 80043dc: 000f4240 .word 0x000f4240 080043e0 : * stopped to disable the ADC. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc) { 80043e0: b538 push {r3, r4, r5, lr} uint32_t tickstart = 0U; /* Verification if ADC is not already disabled */ if (ADC_IS_ENABLE(hadc) != RESET) 80043e2: 6803 ldr r3, [r0, #0] { 80043e4: 4604 mov r4, r0 if (ADC_IS_ENABLE(hadc) != RESET) 80043e6: 689a ldr r2, [r3, #8] 80043e8: 07d2 lsls r2, r2, #31 80043ea: d401 bmi.n 80043f0 } } } /* Return HAL status */ return HAL_OK; 80043ec: 2000 movs r0, #0 80043ee: bd38 pop {r3, r4, r5, pc} __HAL_ADC_DISABLE(hadc); 80043f0: 689a ldr r2, [r3, #8] 80043f2: f022 0201 bic.w r2, r2, #1 80043f6: 609a str r2, [r3, #8] tickstart = HAL_GetTick(); 80043f8: f7ff ff56 bl 80042a8 80043fc: 4605 mov r5, r0 while(ADC_IS_ENABLE(hadc) != RESET) 80043fe: 6823 ldr r3, [r4, #0] 8004400: 689b ldr r3, [r3, #8] 8004402: 07db lsls r3, r3, #31 8004404: d5f2 bpl.n 80043ec if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 8004406: f7ff ff4f bl 80042a8 800440a: 1b40 subs r0, r0, r5 800440c: 2802 cmp r0, #2 800440e: d9f6 bls.n 80043fe SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8004410: 6aa3 ldr r3, [r4, #40] ; 0x28 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8004412: 2001 movs r0, #1 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8004414: f043 0310 orr.w r3, r3, #16 8004418: 62a3 str r3, [r4, #40] ; 0x28 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800441a: 6ae3 ldr r3, [r4, #44] ; 0x2c 800441c: f043 0301 orr.w r3, r3, #1 8004420: 62e3 str r3, [r4, #44] ; 0x2c 8004422: bd38 pop {r3, r4, r5, pc} 08004424 : { 8004424: b5f8 push {r3, r4, r5, r6, r7, lr} if(hadc == NULL) 8004426: 4604 mov r4, r0 8004428: 2800 cmp r0, #0 800442a: d077 beq.n 800451c if (hadc->State == HAL_ADC_STATE_RESET) 800442c: 6a83 ldr r3, [r0, #40] ; 0x28 800442e: b923 cbnz r3, 800443a ADC_CLEAR_ERRORCODE(hadc); 8004430: 62c3 str r3, [r0, #44] ; 0x2c hadc->Lock = HAL_UNLOCKED; 8004432: f880 3024 strb.w r3, [r0, #36] ; 0x24 HAL_ADC_MspInit(hadc); 8004436: f001 fd09 bl 8005e4c tmp_hal_status = ADC_ConversionStop_Disable(hadc); 800443a: 4620 mov r0, r4 800443c: f7ff ffd0 bl 80043e0 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && 8004440: 6aa3 ldr r3, [r4, #40] ; 0x28 8004442: f013 0310 ands.w r3, r3, #16 8004446: d16b bne.n 8004520 8004448: 2800 cmp r0, #0 800444a: d169 bne.n 8004520 ADC_STATE_CLR_SET(hadc->State, 800444c: 6aa2 ldr r2, [r4, #40] ; 0x28 ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 800444e: 4937 ldr r1, [pc, #220] ; (800452c ) ADC_STATE_CLR_SET(hadc->State, 8004450: f422 5288 bic.w r2, r2, #4352 ; 0x1100 8004454: f022 0202 bic.w r2, r2, #2 8004458: f042 0202 orr.w r2, r2, #2 800445c: 62a2 str r2, [r4, #40] ; 0x28 ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 800445e: e894 0024 ldmia.w r4, {r2, r5} 8004462: 428a cmp r2, r1 8004464: 69e1 ldr r1, [r4, #28] 8004466: d104 bne.n 8004472 8004468: f5b1 2f40 cmp.w r1, #786432 ; 0xc0000 800446c: bf08 it eq 800446e: f44f 2100 moveq.w r1, #524288 ; 0x80000 ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode) ); 8004472: 68e6 ldr r6, [r4, #12] ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 8004474: ea45 0546 orr.w r5, r5, r6, lsl #1 8004478: 4329 orrs r1, r5 tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode)); 800447a: 68a5 ldr r5, [r4, #8] 800447c: f5b5 7f80 cmp.w r5, #256 ; 0x100 8004480: d035 beq.n 80044ee 8004482: 2d01 cmp r5, #1 8004484: bf08 it eq 8004486: f44f 7380 moveq.w r3, #256 ; 0x100 if (hadc->Init.DiscontinuousConvMode == ENABLE) 800448a: 6967 ldr r7, [r4, #20] 800448c: 2f01 cmp r7, #1 800448e: d106 bne.n 800449e if (hadc->Init.ContinuousConvMode == DISABLE) 8004490: bb7e cbnz r6, 80044f2 SET_BIT(tmp_cr1, ADC_CR1_DISCEN | 8004492: 69a6 ldr r6, [r4, #24] 8004494: 3e01 subs r6, #1 8004496: ea43 3346 orr.w r3, r3, r6, lsl #13 800449a: f443 6300 orr.w r3, r3, #2048 ; 0x800 MODIFY_REG(hadc->Instance->CR1, 800449e: 6856 ldr r6, [r2, #4] if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE) 80044a0: f5b5 7f80 cmp.w r5, #256 ; 0x100 MODIFY_REG(hadc->Instance->CR1, 80044a4: f426 4669 bic.w r6, r6, #59648 ; 0xe900 80044a8: ea43 0306 orr.w r3, r3, r6 80044ac: 6053 str r3, [r2, #4] MODIFY_REG(hadc->Instance->CR2, 80044ae: 6896 ldr r6, [r2, #8] 80044b0: 4b1f ldr r3, [pc, #124] ; (8004530 ) 80044b2: ea03 0306 and.w r3, r3, r6 80044b6: ea43 0301 orr.w r3, r3, r1 80044ba: 6093 str r3, [r2, #8] if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE) 80044bc: d001 beq.n 80044c2 80044be: 2d01 cmp r5, #1 80044c0: d120 bne.n 8004504 tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion); 80044c2: 6923 ldr r3, [r4, #16] 80044c4: 3b01 subs r3, #1 80044c6: 051b lsls r3, r3, #20 MODIFY_REG(hadc->Instance->SQR1, 80044c8: 6ad5 ldr r5, [r2, #44] ; 0x2c 80044ca: f425 0570 bic.w r5, r5, #15728640 ; 0xf00000 80044ce: 432b orrs r3, r5 80044d0: 62d3 str r3, [r2, #44] ; 0x2c if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 80044d2: 6892 ldr r2, [r2, #8] 80044d4: 4b17 ldr r3, [pc, #92] ; (8004534 ) 80044d6: 4013 ands r3, r2 80044d8: 4299 cmp r1, r3 80044da: d115 bne.n 8004508 ADC_CLEAR_ERRORCODE(hadc); 80044dc: 2300 movs r3, #0 80044de: 62e3 str r3, [r4, #44] ; 0x2c ADC_STATE_CLR_SET(hadc->State, 80044e0: 6aa3 ldr r3, [r4, #40] ; 0x28 80044e2: f023 0303 bic.w r3, r3, #3 80044e6: f043 0301 orr.w r3, r3, #1 80044ea: 62a3 str r3, [r4, #40] ; 0x28 80044ec: bdf8 pop {r3, r4, r5, r6, r7, pc} tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode)); 80044ee: 462b mov r3, r5 80044f0: e7cb b.n 800448a SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 80044f2: 6aa6 ldr r6, [r4, #40] ; 0x28 80044f4: f046 0620 orr.w r6, r6, #32 80044f8: 62a6 str r6, [r4, #40] ; 0x28 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 80044fa: 6ae6 ldr r6, [r4, #44] ; 0x2c 80044fc: f046 0601 orr.w r6, r6, #1 8004500: 62e6 str r6, [r4, #44] ; 0x2c 8004502: e7cc b.n 800449e uint32_t tmp_sqr1 = 0U; 8004504: 2300 movs r3, #0 8004506: e7df b.n 80044c8 ADC_STATE_CLR_SET(hadc->State, 8004508: 6aa3 ldr r3, [r4, #40] ; 0x28 800450a: f023 0312 bic.w r3, r3, #18 800450e: f043 0310 orr.w r3, r3, #16 8004512: 62a3 str r3, [r4, #40] ; 0x28 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8004514: 6ae3 ldr r3, [r4, #44] ; 0x2c 8004516: f043 0301 orr.w r3, r3, #1 800451a: 62e3 str r3, [r4, #44] ; 0x2c return HAL_ERROR; 800451c: 2001 movs r0, #1 } 800451e: bdf8 pop {r3, r4, r5, r6, r7, pc} SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8004520: 6aa3 ldr r3, [r4, #40] ; 0x28 8004522: f043 0310 orr.w r3, r3, #16 8004526: 62a3 str r3, [r4, #40] ; 0x28 8004528: e7f8 b.n 800451c 800452a: bf00 nop 800452c: 40013c00 .word 0x40013c00 8004530: ffe1f7fd .word 0xffe1f7fd 8004534: ff1f0efe .word 0xff1f0efe 08004538 : __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ 8004538: 4a07 ldr r2, [pc, #28] ; (8004558 ) reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ 800453a: 0200 lsls r0, r0, #8 reg_value = SCB->AIRCR; /* read old register configuration */ 800453c: 68d3 ldr r3, [r2, #12] (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ 800453e: f400 60e0 and.w r0, r0, #1792 ; 0x700 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8004542: f423 63e0 bic.w r3, r3, #1792 ; 0x700 8004546: 041b lsls r3, r3, #16 8004548: 0c1b lsrs r3, r3, #16 800454a: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 800454e: f443 3300 orr.w r3, r3, #131072 ; 0x20000 reg_value = (reg_value | 8004552: 4303 orrs r3, r0 SCB->AIRCR = reg_value; 8004554: 60d3 str r3, [r2, #12] 8004556: 4770 bx lr 8004558: e000ed00 .word 0xe000ed00 0800455c : \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 800455c: 4b17 ldr r3, [pc, #92] ; (80045bc ) * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 800455e: b530 push {r4, r5, lr} 8004560: 68dc ldr r4, [r3, #12] 8004562: f3c4 2402 ubfx r4, r4, #8, #3 { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8004566: f1c4 0307 rsb r3, r4, #7 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 800456a: 1d25 adds r5, r4, #4 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 800456c: 2b04 cmp r3, #4 800456e: bf28 it cs 8004570: 2304 movcs r3, #4 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8004572: 2d06 cmp r5, #6 return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8004574: f04f 0501 mov.w r5, #1 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8004578: bf98 it ls 800457a: 2400 movls r4, #0 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 800457c: fa05 f303 lsl.w r3, r5, r3 8004580: f103 33ff add.w r3, r3, #4294967295 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8004584: bf88 it hi 8004586: 3c03 subhi r4, #3 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8004588: 4019 ands r1, r3 800458a: 40a1 lsls r1, r4 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 800458c: fa05 f404 lsl.w r4, r5, r4 8004590: 3c01 subs r4, #1 8004592: 4022 ands r2, r4 if ((int32_t)(IRQn) < 0) 8004594: 2800 cmp r0, #0 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8004596: ea42 0201 orr.w r2, r2, r1 800459a: ea4f 1202 mov.w r2, r2, lsl #4 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800459e: bfaf iteee ge 80045a0: f100 4060 addge.w r0, r0, #3758096384 ; 0xe0000000 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80045a4: 4b06 ldrlt r3, [pc, #24] ; (80045c0 ) 80045a6: f000 000f andlt.w r0, r0, #15 80045aa: b2d2 uxtblt r2, r2 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80045ac: bfa5 ittet ge 80045ae: b2d2 uxtbge r2, r2 80045b0: f500 4061 addge.w r0, r0, #57600 ; 0xe100 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80045b4: 541a strblt r2, [r3, r0] NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80045b6: f880 2300 strbge.w r2, [r0, #768] ; 0x300 80045ba: bd30 pop {r4, r5, pc} 80045bc: e000ed00 .word 0xe000ed00 80045c0: e000ed14 .word 0xe000ed14 080045c4 : NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 80045c4: 2301 movs r3, #1 80045c6: 0942 lsrs r2, r0, #5 80045c8: f000 001f and.w r0, r0, #31 80045cc: fa03 f000 lsl.w r0, r3, r0 80045d0: 4b01 ldr r3, [pc, #4] ; (80045d8 ) 80045d2: f843 0022 str.w r0, [r3, r2, lsl #2] 80045d6: 4770 bx lr 80045d8: e000e100 .word 0xe000e100 080045dc : function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 80045dc: 3801 subs r0, #1 80045de: f1b0 7f80 cmp.w r0, #16777216 ; 0x1000000 80045e2: d20a bcs.n 80045fa SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80045e4: 21f0 movs r1, #240 ; 0xf0 { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 80045e6: 4b06 ldr r3, [pc, #24] ; (8004600 ) SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80045e8: 4a06 ldr r2, [pc, #24] ; (8004604 ) SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 80045ea: 6058 str r0, [r3, #4] SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80045ec: f882 1023 strb.w r1, [r2, #35] ; 0x23 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 80045f0: 2000 movs r0, #0 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 80045f2: 2207 movs r2, #7 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 80045f4: 6098 str r0, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 80045f6: 601a str r2, [r3, #0] 80045f8: 4770 bx lr return (1UL); /* Reload value impossible */ 80045fa: 2001 movs r0, #1 * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { return SysTick_Config(TicksNumb); } 80045fc: 4770 bx lr 80045fe: bf00 nop 8004600: e000e010 .word 0xe000e010 8004604: e000ed00 .word 0xe000ed00 08004608 : * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { 8004608: b510 push {r4, lr} uint32_t tmp = 0U; /* Check the DMA handle allocation */ if(hdma == NULL) 800460a: 2800 cmp r0, #0 800460c: d032 beq.n 8004674 assert_param(IS_DMA_MODE(hdma->Init.Mode)); assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); #if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F100xE) || defined (STM32F105xC) || defined (STM32F107xC) /* calculation of the channel index */ if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) 800460e: 6801 ldr r1, [r0, #0] 8004610: 4b19 ldr r3, [pc, #100] ; (8004678 ) 8004612: 2414 movs r4, #20 8004614: 4299 cmp r1, r3 8004616: d825 bhi.n 8004664 { /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; 8004618: 4a18 ldr r2, [pc, #96] ; (800467c ) hdma->DmaBaseAddress = DMA1; 800461a: f2a3 4307 subw r3, r3, #1031 ; 0x407 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; 800461e: 440a add r2, r1 8004620: fbb2 f2f4 udiv r2, r2, r4 8004624: 0092 lsls r2, r2, #2 8004626: 6402 str r2, [r0, #64] ; 0x40 tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ DMA_CCR_DIR)); /* Prepare the DMA Channel configuration */ tmp |= hdma->Init.Direction | 8004628: 6884 ldr r4, [r0, #8] hdma->DmaBaseAddress = DMA2; 800462a: 63c3 str r3, [r0, #60] ; 0x3c tmp |= hdma->Init.Direction | 800462c: 6843 ldr r3, [r0, #4] tmp = hdma->Instance->CCR; 800462e: 680a ldr r2, [r1, #0] tmp |= hdma->Init.Direction | 8004630: 4323 orrs r3, r4 hdma->Init.PeriphInc | hdma->Init.MemInc | 8004632: 68c4 ldr r4, [r0, #12] tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ 8004634: f422 527f bic.w r2, r2, #16320 ; 0x3fc0 hdma->Init.PeriphInc | hdma->Init.MemInc | 8004638: 4323 orrs r3, r4 800463a: 6904 ldr r4, [r0, #16] tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ 800463c: f022 0230 bic.w r2, r2, #48 ; 0x30 hdma->Init.PeriphInc | hdma->Init.MemInc | 8004640: 4323 orrs r3, r4 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8004642: 6944 ldr r4, [r0, #20] 8004644: 4323 orrs r3, r4 8004646: 6984 ldr r4, [r0, #24] 8004648: 4323 orrs r3, r4 hdma->Init.Mode | hdma->Init.Priority; 800464a: 69c4 ldr r4, [r0, #28] 800464c: 4323 orrs r3, r4 tmp |= hdma->Init.Direction | 800464e: 4313 orrs r3, r2 /* Write to DMA Channel CR register */ hdma->Instance->CCR = tmp; 8004650: 600b str r3, [r1, #0] /* Initialise the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; /* Initialize the DMA state*/ hdma->State = HAL_DMA_STATE_READY; 8004652: 2201 movs r2, #1 hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8004654: 2300 movs r3, #0 hdma->State = HAL_DMA_STATE_READY; 8004656: f880 2021 strb.w r2, [r0, #33] ; 0x21 hdma->ErrorCode = HAL_DMA_ERROR_NONE; 800465a: 6383 str r3, [r0, #56] ; 0x38 /* Allocate lock resource and initialize it */ hdma->Lock = HAL_UNLOCKED; 800465c: f880 3020 strb.w r3, [r0, #32] return HAL_OK; 8004660: 4618 mov r0, r3 8004662: bd10 pop {r4, pc} hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; 8004664: 4b06 ldr r3, [pc, #24] ; (8004680 ) 8004666: 440b add r3, r1 8004668: fbb3 f3f4 udiv r3, r3, r4 800466c: 009b lsls r3, r3, #2 800466e: 6403 str r3, [r0, #64] ; 0x40 hdma->DmaBaseAddress = DMA2; 8004670: 4b04 ldr r3, [pc, #16] ; (8004684 ) 8004672: e7d9 b.n 8004628 return HAL_ERROR; 8004674: 2001 movs r0, #1 } 8004676: bd10 pop {r4, pc} 8004678: 40020407 .word 0x40020407 800467c: bffdfff8 .word 0xbffdfff8 8004680: bffdfbf8 .word 0xbffdfbf8 8004684: 40020400 .word 0x40020400 08004688 : * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 8004688: b5f0 push {r4, r5, r6, r7, lr} /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Process locked */ __HAL_LOCK(hdma); 800468a: f890 4020 ldrb.w r4, [r0, #32] 800468e: 2c01 cmp r4, #1 8004690: d035 beq.n 80046fe 8004692: 2401 movs r4, #1 if(HAL_DMA_STATE_READY == hdma->State) 8004694: f890 5021 ldrb.w r5, [r0, #33] ; 0x21 __HAL_LOCK(hdma); 8004698: f880 4020 strb.w r4, [r0, #32] if(HAL_DMA_STATE_READY == hdma->State) 800469c: 42a5 cmp r5, r4 800469e: f04f 0600 mov.w r6, #0 80046a2: f04f 0402 mov.w r4, #2 80046a6: d128 bne.n 80046fa { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 80046a8: f880 4021 strb.w r4, [r0, #33] ; 0x21 hdma->ErrorCode = HAL_DMA_ERROR_NONE; /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); 80046ac: 6804 ldr r4, [r0, #0] hdma->ErrorCode = HAL_DMA_ERROR_NONE; 80046ae: 6386 str r6, [r0, #56] ; 0x38 __HAL_DMA_DISABLE(hdma); 80046b0: 6826 ldr r6, [r4, #0] * @retval HAL status */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); 80046b2: 6c07 ldr r7, [r0, #64] ; 0x40 __HAL_DMA_DISABLE(hdma); 80046b4: f026 0601 bic.w r6, r6, #1 80046b8: 6026 str r6, [r4, #0] hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); 80046ba: 6bc6 ldr r6, [r0, #60] ; 0x3c 80046bc: 40bd lsls r5, r7 80046be: 6075 str r5, [r6, #4] /* Configure DMA Channel data length */ hdma->Instance->CNDTR = DataLength; 80046c0: 6063 str r3, [r4, #4] /* Memory to Peripheral */ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 80046c2: 6843 ldr r3, [r0, #4] 80046c4: 6805 ldr r5, [r0, #0] 80046c6: 2b10 cmp r3, #16 if(NULL != hdma->XferHalfCpltCallback) 80046c8: 6ac3 ldr r3, [r0, #44] ; 0x2c { /* Configure DMA Channel destination address */ hdma->Instance->CPAR = DstAddress; 80046ca: bf0b itete eq 80046cc: 60a2 streq r2, [r4, #8] } /* Peripheral to Memory */ else { /* Configure DMA Channel source address */ hdma->Instance->CPAR = SrcAddress; 80046ce: 60a1 strne r1, [r4, #8] hdma->Instance->CMAR = SrcAddress; 80046d0: 60e1 streq r1, [r4, #12] /* Configure DMA Channel destination address */ hdma->Instance->CMAR = DstAddress; 80046d2: 60e2 strne r2, [r4, #12] if(NULL != hdma->XferHalfCpltCallback) 80046d4: b14b cbz r3, 80046ea __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 80046d6: 6823 ldr r3, [r4, #0] 80046d8: f043 030e orr.w r3, r3, #14 __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); 80046dc: 6023 str r3, [r4, #0] __HAL_DMA_ENABLE(hdma); 80046de: 682b ldr r3, [r5, #0] HAL_StatusTypeDef status = HAL_OK; 80046e0: 2000 movs r0, #0 __HAL_DMA_ENABLE(hdma); 80046e2: f043 0301 orr.w r3, r3, #1 80046e6: 602b str r3, [r5, #0] 80046e8: bdf0 pop {r4, r5, r6, r7, pc} __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 80046ea: 6823 ldr r3, [r4, #0] 80046ec: f023 0304 bic.w r3, r3, #4 80046f0: 6023 str r3, [r4, #0] __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); 80046f2: 6823 ldr r3, [r4, #0] 80046f4: f043 030a orr.w r3, r3, #10 80046f8: e7f0 b.n 80046dc __HAL_UNLOCK(hdma); 80046fa: f880 6020 strb.w r6, [r0, #32] __HAL_LOCK(hdma); 80046fe: 2002 movs r0, #2 } 8004700: bdf0 pop {r4, r5, r6, r7, pc} ... 08004704 : if(HAL_DMA_STATE_BUSY != hdma->State) 8004704: f890 3021 ldrb.w r3, [r0, #33] ; 0x21 { 8004708: b510 push {r4, lr} if(HAL_DMA_STATE_BUSY != hdma->State) 800470a: 2b02 cmp r3, #2 800470c: d003 beq.n 8004716 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 800470e: 2304 movs r3, #4 8004710: 6383 str r3, [r0, #56] ; 0x38 status = HAL_ERROR; 8004712: 2001 movs r0, #1 8004714: bd10 pop {r4, pc} __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8004716: 6803 ldr r3, [r0, #0] 8004718: 681a ldr r2, [r3, #0] 800471a: f022 020e bic.w r2, r2, #14 800471e: 601a str r2, [r3, #0] __HAL_DMA_DISABLE(hdma); 8004720: 681a ldr r2, [r3, #0] 8004722: f022 0201 bic.w r2, r2, #1 8004726: 601a str r2, [r3, #0] __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); 8004728: 4a29 ldr r2, [pc, #164] ; (80047d0 ) 800472a: 4293 cmp r3, r2 800472c: d924 bls.n 8004778 800472e: f502 7262 add.w r2, r2, #904 ; 0x388 8004732: 4293 cmp r3, r2 8004734: d019 beq.n 800476a 8004736: 3214 adds r2, #20 8004738: 4293 cmp r3, r2 800473a: d018 beq.n 800476e 800473c: 3214 adds r2, #20 800473e: 4293 cmp r3, r2 8004740: d017 beq.n 8004772 8004742: 3214 adds r2, #20 8004744: 4293 cmp r3, r2 8004746: bf0c ite eq 8004748: f44f 5380 moveq.w r3, #4096 ; 0x1000 800474c: f44f 3380 movne.w r3, #65536 ; 0x10000 8004750: 4a20 ldr r2, [pc, #128] ; (80047d4 ) 8004752: 6053 str r3, [r2, #4] hdma->State = HAL_DMA_STATE_READY; 8004754: 2301 movs r3, #1 __HAL_UNLOCK(hdma); 8004756: 2400 movs r4, #0 hdma->State = HAL_DMA_STATE_READY; 8004758: f880 3021 strb.w r3, [r0, #33] ; 0x21 if(hdma->XferAbortCallback != NULL) 800475c: 6b43 ldr r3, [r0, #52] ; 0x34 __HAL_UNLOCK(hdma); 800475e: f880 4020 strb.w r4, [r0, #32] if(hdma->XferAbortCallback != NULL) 8004762: b39b cbz r3, 80047cc hdma->XferAbortCallback(hdma); 8004764: 4798 blx r3 HAL_StatusTypeDef status = HAL_OK; 8004766: 4620 mov r0, r4 8004768: bd10 pop {r4, pc} __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); 800476a: 2301 movs r3, #1 800476c: e7f0 b.n 8004750 800476e: 2310 movs r3, #16 8004770: e7ee b.n 8004750 8004772: f44f 7380 mov.w r3, #256 ; 0x100 8004776: e7eb b.n 8004750 8004778: 4917 ldr r1, [pc, #92] ; (80047d8 ) 800477a: 428b cmp r3, r1 800477c: d016 beq.n 80047ac 800477e: 3114 adds r1, #20 8004780: 428b cmp r3, r1 8004782: d015 beq.n 80047b0 8004784: 3114 adds r1, #20 8004786: 428b cmp r3, r1 8004788: d014 beq.n 80047b4 800478a: 3114 adds r1, #20 800478c: 428b cmp r3, r1 800478e: d014 beq.n 80047ba 8004790: 3114 adds r1, #20 8004792: 428b cmp r3, r1 8004794: d014 beq.n 80047c0 8004796: 3114 adds r1, #20 8004798: 428b cmp r3, r1 800479a: d014 beq.n 80047c6 800479c: 4293 cmp r3, r2 800479e: bf14 ite ne 80047a0: f44f 3380 movne.w r3, #65536 ; 0x10000 80047a4: f04f 7380 moveq.w r3, #16777216 ; 0x1000000 80047a8: 4a0c ldr r2, [pc, #48] ; (80047dc ) 80047aa: e7d2 b.n 8004752 80047ac: 2301 movs r3, #1 80047ae: e7fb b.n 80047a8 80047b0: 2310 movs r3, #16 80047b2: e7f9 b.n 80047a8 80047b4: f44f 7380 mov.w r3, #256 ; 0x100 80047b8: e7f6 b.n 80047a8 80047ba: f44f 5380 mov.w r3, #4096 ; 0x1000 80047be: e7f3 b.n 80047a8 80047c0: f44f 3380 mov.w r3, #65536 ; 0x10000 80047c4: e7f0 b.n 80047a8 80047c6: f44f 1380 mov.w r3, #1048576 ; 0x100000 80047ca: e7ed b.n 80047a8 HAL_StatusTypeDef status = HAL_OK; 80047cc: 4618 mov r0, r3 } 80047ce: bd10 pop {r4, pc} 80047d0: 40020080 .word 0x40020080 80047d4: 40020400 .word 0x40020400 80047d8: 40020008 .word 0x40020008 80047dc: 40020000 .word 0x40020000 080047e0 : { 80047e0: b470 push {r4, r5, r6} if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET)) 80047e2: 2504 movs r5, #4 uint32_t flag_it = hdma->DmaBaseAddress->ISR; 80047e4: 6bc6 ldr r6, [r0, #60] ; 0x3c if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET)) 80047e6: 6c02 ldr r2, [r0, #64] ; 0x40 uint32_t flag_it = hdma->DmaBaseAddress->ISR; 80047e8: 6834 ldr r4, [r6, #0] uint32_t source_it = hdma->Instance->CCR; 80047ea: 6803 ldr r3, [r0, #0] if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET)) 80047ec: 4095 lsls r5, r2 80047ee: 4225 tst r5, r4 uint32_t source_it = hdma->Instance->CCR; 80047f0: 6819 ldr r1, [r3, #0] if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET)) 80047f2: d055 beq.n 80048a0 80047f4: 074d lsls r5, r1, #29 80047f6: d553 bpl.n 80048a0 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 80047f8: 681a ldr r2, [r3, #0] 80047fa: 0696 lsls r6, r2, #26 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 80047fc: bf5e ittt pl 80047fe: 681a ldrpl r2, [r3, #0] 8004800: f022 0204 bicpl.w r2, r2, #4 8004804: 601a strpl r2, [r3, #0] __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); 8004806: 4a60 ldr r2, [pc, #384] ; (8004988 ) 8004808: 4293 cmp r3, r2 800480a: d91f bls.n 800484c 800480c: f502 7262 add.w r2, r2, #904 ; 0x388 8004810: 4293 cmp r3, r2 8004812: d014 beq.n 800483e 8004814: 3214 adds r2, #20 8004816: 4293 cmp r3, r2 8004818: d013 beq.n 8004842 800481a: 3214 adds r2, #20 800481c: 4293 cmp r3, r2 800481e: d012 beq.n 8004846 8004820: 3214 adds r2, #20 8004822: 4293 cmp r3, r2 8004824: bf0c ite eq 8004826: f44f 4380 moveq.w r3, #16384 ; 0x4000 800482a: f44f 2380 movne.w r3, #262144 ; 0x40000 800482e: 4a57 ldr r2, [pc, #348] ; (800498c ) 8004830: 6053 str r3, [r2, #4] if(hdma->XferHalfCpltCallback != NULL) 8004832: 6ac3 ldr r3, [r0, #44] ; 0x2c if (hdma->XferErrorCallback != NULL) 8004834: 2b00 cmp r3, #0 8004836: f000 80a5 beq.w 8004984 } 800483a: bc70 pop {r4, r5, r6} hdma->XferErrorCallback(hdma); 800483c: 4718 bx r3 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); 800483e: 2304 movs r3, #4 8004840: e7f5 b.n 800482e 8004842: 2340 movs r3, #64 ; 0x40 8004844: e7f3 b.n 800482e 8004846: f44f 6380 mov.w r3, #1024 ; 0x400 800484a: e7f0 b.n 800482e 800484c: 4950 ldr r1, [pc, #320] ; (8004990 ) 800484e: 428b cmp r3, r1 8004850: d016 beq.n 8004880 8004852: 3114 adds r1, #20 8004854: 428b cmp r3, r1 8004856: d015 beq.n 8004884 8004858: 3114 adds r1, #20 800485a: 428b cmp r3, r1 800485c: d014 beq.n 8004888 800485e: 3114 adds r1, #20 8004860: 428b cmp r3, r1 8004862: d014 beq.n 800488e 8004864: 3114 adds r1, #20 8004866: 428b cmp r3, r1 8004868: d014 beq.n 8004894 800486a: 3114 adds r1, #20 800486c: 428b cmp r3, r1 800486e: d014 beq.n 800489a 8004870: 4293 cmp r3, r2 8004872: bf14 ite ne 8004874: f44f 2380 movne.w r3, #262144 ; 0x40000 8004878: f04f 6380 moveq.w r3, #67108864 ; 0x4000000 800487c: 4a45 ldr r2, [pc, #276] ; (8004994 ) 800487e: e7d7 b.n 8004830 8004880: 2304 movs r3, #4 8004882: e7fb b.n 800487c 8004884: 2340 movs r3, #64 ; 0x40 8004886: e7f9 b.n 800487c 8004888: f44f 6380 mov.w r3, #1024 ; 0x400 800488c: e7f6 b.n 800487c 800488e: f44f 4380 mov.w r3, #16384 ; 0x4000 8004892: e7f3 b.n 800487c 8004894: f44f 2380 mov.w r3, #262144 ; 0x40000 8004898: e7f0 b.n 800487c 800489a: f44f 0380 mov.w r3, #4194304 ; 0x400000 800489e: e7ed b.n 800487c else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET)) 80048a0: 2502 movs r5, #2 80048a2: 4095 lsls r5, r2 80048a4: 4225 tst r5, r4 80048a6: d057 beq.n 8004958 80048a8: 078d lsls r5, r1, #30 80048aa: d555 bpl.n 8004958 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 80048ac: 681a ldr r2, [r3, #0] 80048ae: 0694 lsls r4, r2, #26 80048b0: d406 bmi.n 80048c0 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); 80048b2: 681a ldr r2, [r3, #0] 80048b4: f022 020a bic.w r2, r2, #10 80048b8: 601a str r2, [r3, #0] hdma->State = HAL_DMA_STATE_READY; 80048ba: 2201 movs r2, #1 80048bc: f880 2021 strb.w r2, [r0, #33] ; 0x21 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); 80048c0: 4a31 ldr r2, [pc, #196] ; (8004988 ) 80048c2: 4293 cmp r3, r2 80048c4: d91e bls.n 8004904 80048c6: f502 7262 add.w r2, r2, #904 ; 0x388 80048ca: 4293 cmp r3, r2 80048cc: d013 beq.n 80048f6 80048ce: 3214 adds r2, #20 80048d0: 4293 cmp r3, r2 80048d2: d012 beq.n 80048fa 80048d4: 3214 adds r2, #20 80048d6: 4293 cmp r3, r2 80048d8: d011 beq.n 80048fe 80048da: 3214 adds r2, #20 80048dc: 4293 cmp r3, r2 80048de: bf0c ite eq 80048e0: f44f 5300 moveq.w r3, #8192 ; 0x2000 80048e4: f44f 3300 movne.w r3, #131072 ; 0x20000 80048e8: 4a28 ldr r2, [pc, #160] ; (800498c ) 80048ea: 6053 str r3, [r2, #4] __HAL_UNLOCK(hdma); 80048ec: 2300 movs r3, #0 80048ee: f880 3020 strb.w r3, [r0, #32] if(hdma->XferCpltCallback != NULL) 80048f2: 6a83 ldr r3, [r0, #40] ; 0x28 80048f4: e79e b.n 8004834 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); 80048f6: 2302 movs r3, #2 80048f8: e7f6 b.n 80048e8 80048fa: 2320 movs r3, #32 80048fc: e7f4 b.n 80048e8 80048fe: f44f 7300 mov.w r3, #512 ; 0x200 8004902: e7f1 b.n 80048e8 8004904: 4922 ldr r1, [pc, #136] ; (8004990 ) 8004906: 428b cmp r3, r1 8004908: d016 beq.n 8004938 800490a: 3114 adds r1, #20 800490c: 428b cmp r3, r1 800490e: d015 beq.n 800493c 8004910: 3114 adds r1, #20 8004912: 428b cmp r3, r1 8004914: d014 beq.n 8004940 8004916: 3114 adds r1, #20 8004918: 428b cmp r3, r1 800491a: d014 beq.n 8004946 800491c: 3114 adds r1, #20 800491e: 428b cmp r3, r1 8004920: d014 beq.n 800494c 8004922: 3114 adds r1, #20 8004924: 428b cmp r3, r1 8004926: d014 beq.n 8004952 8004928: 4293 cmp r3, r2 800492a: bf14 ite ne 800492c: f44f 3300 movne.w r3, #131072 ; 0x20000 8004930: f04f 7300 moveq.w r3, #33554432 ; 0x2000000 8004934: 4a17 ldr r2, [pc, #92] ; (8004994 ) 8004936: e7d8 b.n 80048ea 8004938: 2302 movs r3, #2 800493a: e7fb b.n 8004934 800493c: 2320 movs r3, #32 800493e: e7f9 b.n 8004934 8004940: f44f 7300 mov.w r3, #512 ; 0x200 8004944: e7f6 b.n 8004934 8004946: f44f 5300 mov.w r3, #8192 ; 0x2000 800494a: e7f3 b.n 8004934 800494c: f44f 3300 mov.w r3, #131072 ; 0x20000 8004950: e7f0 b.n 8004934 8004952: f44f 1300 mov.w r3, #2097152 ; 0x200000 8004956: e7ed b.n 8004934 else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE))) 8004958: 2508 movs r5, #8 800495a: 4095 lsls r5, r2 800495c: 4225 tst r5, r4 800495e: d011 beq.n 8004984 8004960: 0709 lsls r1, r1, #28 8004962: d50f bpl.n 8004984 __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8004964: 6819 ldr r1, [r3, #0] 8004966: f021 010e bic.w r1, r1, #14 800496a: 6019 str r1, [r3, #0] hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); 800496c: 2301 movs r3, #1 800496e: fa03 f202 lsl.w r2, r3, r2 8004972: 6072 str r2, [r6, #4] hdma->ErrorCode = HAL_DMA_ERROR_TE; 8004974: 6383 str r3, [r0, #56] ; 0x38 hdma->State = HAL_DMA_STATE_READY; 8004976: f880 3021 strb.w r3, [r0, #33] ; 0x21 __HAL_UNLOCK(hdma); 800497a: 2300 movs r3, #0 800497c: f880 3020 strb.w r3, [r0, #32] if (hdma->XferErrorCallback != NULL) 8004980: 6b03 ldr r3, [r0, #48] ; 0x30 8004982: e757 b.n 8004834 } 8004984: bc70 pop {r4, r5, r6} 8004986: 4770 bx lr 8004988: 40020080 .word 0x40020080 800498c: 40020400 .word 0x40020400 8004990: 40020008 .word 0x40020008 8004994: 40020000 .word 0x40020000 08004998 : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8004998: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} uint32_t position; uint32_t ioposition = 0x00U; uint32_t iocurrent = 0x00U; uint32_t temp = 0x00U; uint32_t config = 0x00U; 800499c: 2200 movs r2, #0 assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ for (position = 0U; position < GPIO_NUMBER; position++) 800499e: 4616 mov r6, r2 /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) { /* Enable AFIO Clock */ __HAL_RCC_AFIO_CLK_ENABLE(); 80049a0: 4f6c ldr r7, [pc, #432] ; (8004b54 ) 80049a2: 4b6d ldr r3, [pc, #436] ; (8004b58 ) temp = AFIO->EXTICR[position >> 2U]; CLEAR_BIT(temp, (0x0FU) << (4U * (position & 0x03U))); SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); 80049a4: f8df e1b8 ldr.w lr, [pc, #440] ; 8004b60 switch (GPIO_Init->Mode) 80049a8: f8df c1b8 ldr.w ip, [pc, #440] ; 8004b64 ioposition = (0x01U << position); 80049ac: f04f 0801 mov.w r8, #1 iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 80049b0: 680c ldr r4, [r1, #0] ioposition = (0x01U << position); 80049b2: fa08 f806 lsl.w r8, r8, r6 iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 80049b6: ea08 0404 and.w r4, r8, r4 if (iocurrent == ioposition) 80049ba: 45a0 cmp r8, r4 80049bc: f040 8085 bne.w 8004aca switch (GPIO_Init->Mode) 80049c0: 684d ldr r5, [r1, #4] 80049c2: 2d12 cmp r5, #18 80049c4: f000 80b7 beq.w 8004b36 80049c8: f200 808d bhi.w 8004ae6 80049cc: 2d02 cmp r5, #2 80049ce: f000 80af beq.w 8004b30 80049d2: f200 8081 bhi.w 8004ad8 80049d6: 2d00 cmp r5, #0 80049d8: f000 8091 beq.w 8004afe 80049dc: 2d01 cmp r5, #1 80049de: f000 80a5 beq.w 8004b2c MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); 80049e2: f04f 090f mov.w r9, #15 configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; 80049e6: 2cff cmp r4, #255 ; 0xff 80049e8: bf93 iteet ls 80049ea: 4682 movls sl, r0 80049ec: f106 4580 addhi.w r5, r6, #1073741824 ; 0x40000000 80049f0: 3d08 subhi r5, #8 80049f2: f8d0 b000 ldrls.w fp, [r0] 80049f6: bf92 itee ls 80049f8: 00b5 lslls r5, r6, #2 80049fa: f8d0 b004 ldrhi.w fp, [r0, #4] 80049fe: 00ad lslhi r5, r5, #2 MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); 8004a00: fa09 f805 lsl.w r8, r9, r5 8004a04: ea2b 0808 bic.w r8, fp, r8 8004a08: fa02 f505 lsl.w r5, r2, r5 configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; 8004a0c: bf88 it hi 8004a0e: f100 0a04 addhi.w sl, r0, #4 MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); 8004a12: ea48 0505 orr.w r5, r8, r5 8004a16: f8ca 5000 str.w r5, [sl] if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 8004a1a: f8d1 a004 ldr.w sl, [r1, #4] 8004a1e: f01a 5f80 tst.w sl, #268435456 ; 0x10000000 8004a22: d052 beq.n 8004aca __HAL_RCC_AFIO_CLK_ENABLE(); 8004a24: 69bd ldr r5, [r7, #24] 8004a26: f026 0803 bic.w r8, r6, #3 8004a2a: f045 0501 orr.w r5, r5, #1 8004a2e: 61bd str r5, [r7, #24] 8004a30: 69bd ldr r5, [r7, #24] 8004a32: f108 4880 add.w r8, r8, #1073741824 ; 0x40000000 8004a36: f005 0501 and.w r5, r5, #1 8004a3a: 9501 str r5, [sp, #4] 8004a3c: f508 3880 add.w r8, r8, #65536 ; 0x10000 CLEAR_BIT(temp, (0x0FU) << (4U * (position & 0x03U))); 8004a40: f006 0b03 and.w fp, r6, #3 __HAL_RCC_AFIO_CLK_ENABLE(); 8004a44: 9d01 ldr r5, [sp, #4] CLEAR_BIT(temp, (0x0FU) << (4U * (position & 0x03U))); 8004a46: ea4f 0b8b mov.w fp, fp, lsl #2 temp = AFIO->EXTICR[position >> 2U]; 8004a4a: f8d8 5008 ldr.w r5, [r8, #8] CLEAR_BIT(temp, (0x0FU) << (4U * (position & 0x03U))); 8004a4e: fa09 f90b lsl.w r9, r9, fp 8004a52: ea25 0909 bic.w r9, r5, r9 SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); 8004a56: 4d41 ldr r5, [pc, #260] ; (8004b5c ) 8004a58: 42a8 cmp r0, r5 8004a5a: d071 beq.n 8004b40 8004a5c: f505 6580 add.w r5, r5, #1024 ; 0x400 8004a60: 42a8 cmp r0, r5 8004a62: d06f beq.n 8004b44 8004a64: f505 6580 add.w r5, r5, #1024 ; 0x400 8004a68: 42a8 cmp r0, r5 8004a6a: d06d beq.n 8004b48 8004a6c: f505 6580 add.w r5, r5, #1024 ; 0x400 8004a70: 42a8 cmp r0, r5 8004a72: d06b beq.n 8004b4c 8004a74: f505 6580 add.w r5, r5, #1024 ; 0x400 8004a78: 42a8 cmp r0, r5 8004a7a: d069 beq.n 8004b50 8004a7c: 4570 cmp r0, lr 8004a7e: bf0c ite eq 8004a80: 2505 moveq r5, #5 8004a82: 2506 movne r5, #6 8004a84: fa05 f50b lsl.w r5, r5, fp 8004a88: ea45 0509 orr.w r5, r5, r9 AFIO->EXTICR[position >> 2U] = temp; 8004a8c: f8c8 5008 str.w r5, [r8, #8] /* Configure the interrupt mask */ if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) { SET_BIT(EXTI->IMR, iocurrent); 8004a90: 681d ldr r5, [r3, #0] if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) 8004a92: f41a 3f80 tst.w sl, #65536 ; 0x10000 SET_BIT(EXTI->IMR, iocurrent); 8004a96: bf14 ite ne 8004a98: 4325 orrne r5, r4 } else { CLEAR_BIT(EXTI->IMR, iocurrent); 8004a9a: 43a5 biceq r5, r4 8004a9c: 601d str r5, [r3, #0] } /* Configure the event mask */ if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) { SET_BIT(EXTI->EMR, iocurrent); 8004a9e: 685d ldr r5, [r3, #4] if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) 8004aa0: f41a 3f00 tst.w sl, #131072 ; 0x20000 SET_BIT(EXTI->EMR, iocurrent); 8004aa4: bf14 ite ne 8004aa6: 4325 orrne r5, r4 } else { CLEAR_BIT(EXTI->EMR, iocurrent); 8004aa8: 43a5 biceq r5, r4 8004aaa: 605d str r5, [r3, #4] } /* Enable or disable the rising trigger */ if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) { SET_BIT(EXTI->RTSR, iocurrent); 8004aac: 689d ldr r5, [r3, #8] if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) 8004aae: f41a 1f80 tst.w sl, #1048576 ; 0x100000 SET_BIT(EXTI->RTSR, iocurrent); 8004ab2: bf14 ite ne 8004ab4: 4325 orrne r5, r4 } else { CLEAR_BIT(EXTI->RTSR, iocurrent); 8004ab6: 43a5 biceq r5, r4 8004ab8: 609d str r5, [r3, #8] } /* Enable or disable the falling trigger */ if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) { SET_BIT(EXTI->FTSR, iocurrent); 8004aba: 68dd ldr r5, [r3, #12] if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) 8004abc: f41a 1f00 tst.w sl, #2097152 ; 0x200000 SET_BIT(EXTI->FTSR, iocurrent); 8004ac0: bf14 ite ne 8004ac2: 432c orrne r4, r5 } else { CLEAR_BIT(EXTI->FTSR, iocurrent); 8004ac4: ea25 0404 biceq.w r4, r5, r4 8004ac8: 60dc str r4, [r3, #12] for (position = 0U; position < GPIO_NUMBER; position++) 8004aca: 3601 adds r6, #1 8004acc: 2e10 cmp r6, #16 8004ace: f47f af6d bne.w 80049ac } } } } } 8004ad2: b003 add sp, #12 8004ad4: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} switch (GPIO_Init->Mode) 8004ad8: 2d03 cmp r5, #3 8004ada: d025 beq.n 8004b28 8004adc: 2d11 cmp r5, #17 8004ade: d180 bne.n 80049e2 config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; 8004ae0: 68ca ldr r2, [r1, #12] 8004ae2: 3204 adds r2, #4 break; 8004ae4: e77d b.n 80049e2 switch (GPIO_Init->Mode) 8004ae6: 4565 cmp r5, ip 8004ae8: d009 beq.n 8004afe 8004aea: d812 bhi.n 8004b12 8004aec: f8df 9078 ldr.w r9, [pc, #120] ; 8004b68 8004af0: 454d cmp r5, r9 8004af2: d004 beq.n 8004afe 8004af4: f509 3980 add.w r9, r9, #65536 ; 0x10000 8004af8: 454d cmp r5, r9 8004afa: f47f af72 bne.w 80049e2 if (GPIO_Init->Pull == GPIO_NOPULL) 8004afe: 688a ldr r2, [r1, #8] 8004b00: b1e2 cbz r2, 8004b3c else if (GPIO_Init->Pull == GPIO_PULLUP) 8004b02: 2a01 cmp r2, #1 GPIOx->BSRR = ioposition; 8004b04: bf0c ite eq 8004b06: f8c0 8010 streq.w r8, [r0, #16] GPIOx->BRR = ioposition; 8004b0a: f8c0 8014 strne.w r8, [r0, #20] config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 8004b0e: 2208 movs r2, #8 8004b10: e767 b.n 80049e2 switch (GPIO_Init->Mode) 8004b12: f8df 9058 ldr.w r9, [pc, #88] ; 8004b6c 8004b16: 454d cmp r5, r9 8004b18: d0f1 beq.n 8004afe 8004b1a: f509 3980 add.w r9, r9, #65536 ; 0x10000 8004b1e: 454d cmp r5, r9 8004b20: d0ed beq.n 8004afe 8004b22: f5a9 1980 sub.w r9, r9, #1048576 ; 0x100000 8004b26: e7e7 b.n 8004af8 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; 8004b28: 2200 movs r2, #0 8004b2a: e75a b.n 80049e2 config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; 8004b2c: 68ca ldr r2, [r1, #12] break; 8004b2e: e758 b.n 80049e2 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; 8004b30: 68ca ldr r2, [r1, #12] 8004b32: 3208 adds r2, #8 break; 8004b34: e755 b.n 80049e2 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; 8004b36: 68ca ldr r2, [r1, #12] 8004b38: 320c adds r2, #12 break; 8004b3a: e752 b.n 80049e2 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; 8004b3c: 2204 movs r2, #4 8004b3e: e750 b.n 80049e2 SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); 8004b40: 2500 movs r5, #0 8004b42: e79f b.n 8004a84 8004b44: 2501 movs r5, #1 8004b46: e79d b.n 8004a84 8004b48: 2502 movs r5, #2 8004b4a: e79b b.n 8004a84 8004b4c: 2503 movs r5, #3 8004b4e: e799 b.n 8004a84 8004b50: 2504 movs r5, #4 8004b52: e797 b.n 8004a84 8004b54: 40021000 .word 0x40021000 8004b58: 40010400 .word 0x40010400 8004b5c: 40010800 .word 0x40010800 8004b60: 40011c00 .word 0x40011c00 8004b64: 10210000 .word 0x10210000 8004b68: 10110000 .word 0x10110000 8004b6c: 10310000 .word 0x10310000 08004b70 : { /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 8004b70: b10a cbz r2, 8004b76 { GPIOx->BSRR = GPIO_Pin; } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; 8004b72: 6101 str r1, [r0, #16] 8004b74: 4770 bx lr 8004b76: 0409 lsls r1, r1, #16 8004b78: e7fb b.n 8004b72 08004b7a : void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); GPIOx->ODR ^= GPIO_Pin; 8004b7a: 68c3 ldr r3, [r0, #12] 8004b7c: 4059 eors r1, r3 8004b7e: 60c1 str r1, [r0, #12] 8004b80: 4770 bx lr ... 08004b84 : /* Check the parameters */ assert_param(RCC_OscInitStruct != NULL); assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8004b84: 6803 ldr r3, [r0, #0] { 8004b86: e92d 41f3 stmdb sp!, {r0, r1, r4, r5, r6, r7, r8, lr} if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8004b8a: 07db lsls r3, r3, #31 { 8004b8c: 4605 mov r5, r0 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8004b8e: d410 bmi.n 8004bb2 } } } } /*----------------------------- HSI Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8004b90: 682b ldr r3, [r5, #0] 8004b92: 079f lsls r7, r3, #30 8004b94: d45e bmi.n 8004c54 } } } } /*------------------------------ LSI Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8004b96: 682b ldr r3, [r5, #0] 8004b98: 0719 lsls r1, r3, #28 8004b9a: f100 8095 bmi.w 8004cc8 } } } } /*------------------------------ LSE Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8004b9e: 682b ldr r3, [r5, #0] 8004ba0: 075a lsls r2, r3, #29 8004ba2: f100 80bf bmi.w 8004d24 #endif /* RCC_CR_PLL2ON */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 8004ba6: 69ea ldr r2, [r5, #28] 8004ba8: 2a00 cmp r2, #0 8004baa: f040 812d bne.w 8004e08 { return HAL_ERROR; } } return HAL_OK; 8004bae: 2000 movs r0, #0 8004bb0: e014 b.n 8004bdc if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 8004bb2: 4c90 ldr r4, [pc, #576] ; (8004df4 ) 8004bb4: 6863 ldr r3, [r4, #4] 8004bb6: f003 030c and.w r3, r3, #12 8004bba: 2b04 cmp r3, #4 8004bbc: d007 beq.n 8004bce || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 8004bbe: 6863 ldr r3, [r4, #4] 8004bc0: f003 030c and.w r3, r3, #12 8004bc4: 2b08 cmp r3, #8 8004bc6: d10c bne.n 8004be2 8004bc8: 6863 ldr r3, [r4, #4] 8004bca: 03de lsls r6, r3, #15 8004bcc: d509 bpl.n 8004be2 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8004bce: 6823 ldr r3, [r4, #0] 8004bd0: 039c lsls r4, r3, #14 8004bd2: d5dd bpl.n 8004b90 8004bd4: 686b ldr r3, [r5, #4] 8004bd6: 2b00 cmp r3, #0 8004bd8: d1da bne.n 8004b90 return HAL_ERROR; 8004bda: 2001 movs r0, #1 } 8004bdc: b002 add sp, #8 8004bde: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8004be2: 686b ldr r3, [r5, #4] 8004be4: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8004be8: d110 bne.n 8004c0c 8004bea: 6823 ldr r3, [r4, #0] 8004bec: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8004bf0: 6023 str r3, [r4, #0] tickstart = HAL_GetTick(); 8004bf2: f7ff fb59 bl 80042a8 8004bf6: 4606 mov r6, r0 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8004bf8: 6823 ldr r3, [r4, #0] 8004bfa: 0398 lsls r0, r3, #14 8004bfc: d4c8 bmi.n 8004b90 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 8004bfe: f7ff fb53 bl 80042a8 8004c02: 1b80 subs r0, r0, r6 8004c04: 2864 cmp r0, #100 ; 0x64 8004c06: d9f7 bls.n 8004bf8 return HAL_TIMEOUT; 8004c08: 2003 movs r0, #3 8004c0a: e7e7 b.n 8004bdc __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8004c0c: b99b cbnz r3, 8004c36 8004c0e: 6823 ldr r3, [r4, #0] 8004c10: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8004c14: 6023 str r3, [r4, #0] 8004c16: 6823 ldr r3, [r4, #0] 8004c18: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8004c1c: 6023 str r3, [r4, #0] tickstart = HAL_GetTick(); 8004c1e: f7ff fb43 bl 80042a8 8004c22: 4606 mov r6, r0 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8004c24: 6823 ldr r3, [r4, #0] 8004c26: 0399 lsls r1, r3, #14 8004c28: d5b2 bpl.n 8004b90 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 8004c2a: f7ff fb3d bl 80042a8 8004c2e: 1b80 subs r0, r0, r6 8004c30: 2864 cmp r0, #100 ; 0x64 8004c32: d9f7 bls.n 8004c24 8004c34: e7e8 b.n 8004c08 __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8004c36: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 8004c3a: 6823 ldr r3, [r4, #0] 8004c3c: d103 bne.n 8004c46 8004c3e: f443 2380 orr.w r3, r3, #262144 ; 0x40000 8004c42: 6023 str r3, [r4, #0] 8004c44: e7d1 b.n 8004bea 8004c46: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8004c4a: 6023 str r3, [r4, #0] 8004c4c: 6823 ldr r3, [r4, #0] 8004c4e: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8004c52: e7cd b.n 8004bf0 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 8004c54: 4c67 ldr r4, [pc, #412] ; (8004df4 ) 8004c56: 6863 ldr r3, [r4, #4] 8004c58: f013 0f0c tst.w r3, #12 8004c5c: d007 beq.n 8004c6e || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) 8004c5e: 6863 ldr r3, [r4, #4] 8004c60: f003 030c and.w r3, r3, #12 8004c64: 2b08 cmp r3, #8 8004c66: d110 bne.n 8004c8a 8004c68: 6863 ldr r3, [r4, #4] 8004c6a: 03da lsls r2, r3, #15 8004c6c: d40d bmi.n 8004c8a if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8004c6e: 6823 ldr r3, [r4, #0] 8004c70: 079b lsls r3, r3, #30 8004c72: d502 bpl.n 8004c7a 8004c74: 692b ldr r3, [r5, #16] 8004c76: 2b01 cmp r3, #1 8004c78: d1af bne.n 8004bda __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8004c7a: 6823 ldr r3, [r4, #0] 8004c7c: 696a ldr r2, [r5, #20] 8004c7e: f023 03f8 bic.w r3, r3, #248 ; 0xf8 8004c82: ea43 03c2 orr.w r3, r3, r2, lsl #3 8004c86: 6023 str r3, [r4, #0] 8004c88: e785 b.n 8004b96 if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 8004c8a: 692a ldr r2, [r5, #16] 8004c8c: 4b5a ldr r3, [pc, #360] ; (8004df8 ) 8004c8e: b16a cbz r2, 8004cac __HAL_RCC_HSI_ENABLE(); 8004c90: 2201 movs r2, #1 8004c92: 601a str r2, [r3, #0] tickstart = HAL_GetTick(); 8004c94: f7ff fb08 bl 80042a8 8004c98: 4606 mov r6, r0 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8004c9a: 6823 ldr r3, [r4, #0] 8004c9c: 079f lsls r7, r3, #30 8004c9e: d4ec bmi.n 8004c7a if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 8004ca0: f7ff fb02 bl 80042a8 8004ca4: 1b80 subs r0, r0, r6 8004ca6: 2802 cmp r0, #2 8004ca8: d9f7 bls.n 8004c9a 8004caa: e7ad b.n 8004c08 __HAL_RCC_HSI_DISABLE(); 8004cac: 601a str r2, [r3, #0] tickstart = HAL_GetTick(); 8004cae: f7ff fafb bl 80042a8 8004cb2: 4606 mov r6, r0 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8004cb4: 6823 ldr r3, [r4, #0] 8004cb6: 0798 lsls r0, r3, #30 8004cb8: f57f af6d bpl.w 8004b96 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 8004cbc: f7ff faf4 bl 80042a8 8004cc0: 1b80 subs r0, r0, r6 8004cc2: 2802 cmp r0, #2 8004cc4: d9f6 bls.n 8004cb4 8004cc6: e79f b.n 8004c08 if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 8004cc8: 69aa ldr r2, [r5, #24] 8004cca: 4c4a ldr r4, [pc, #296] ; (8004df4 ) 8004ccc: 4b4b ldr r3, [pc, #300] ; (8004dfc ) 8004cce: b1da cbz r2, 8004d08 __HAL_RCC_LSI_ENABLE(); 8004cd0: 2201 movs r2, #1 8004cd2: 601a str r2, [r3, #0] tickstart = HAL_GetTick(); 8004cd4: f7ff fae8 bl 80042a8 8004cd8: 4606 mov r6, r0 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8004cda: 6a63 ldr r3, [r4, #36] ; 0x24 8004cdc: 079b lsls r3, r3, #30 8004cde: d50d bpl.n 8004cfc * @param mdelay: specifies the delay time length, in milliseconds. * @retval None */ static void RCC_Delay(uint32_t mdelay) { __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U); 8004ce0: f44f 52fa mov.w r2, #8000 ; 0x1f40 8004ce4: 4b46 ldr r3, [pc, #280] ; (8004e00 ) 8004ce6: 681b ldr r3, [r3, #0] 8004ce8: fbb3 f3f2 udiv r3, r3, r2 8004cec: 9301 str r3, [sp, #4] \brief No Operation \details No Operation does nothing. This instruction can be used for code alignment purposes. */ __attribute__((always_inline)) __STATIC_INLINE void __NOP(void) { __ASM volatile ("nop"); 8004cee: bf00 nop do { __NOP(); } while (Delay --); 8004cf0: 9b01 ldr r3, [sp, #4] 8004cf2: 1e5a subs r2, r3, #1 8004cf4: 9201 str r2, [sp, #4] 8004cf6: 2b00 cmp r3, #0 8004cf8: d1f9 bne.n 8004cee 8004cfa: e750 b.n 8004b9e if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 8004cfc: f7ff fad4 bl 80042a8 8004d00: 1b80 subs r0, r0, r6 8004d02: 2802 cmp r0, #2 8004d04: d9e9 bls.n 8004cda 8004d06: e77f b.n 8004c08 __HAL_RCC_LSI_DISABLE(); 8004d08: 601a str r2, [r3, #0] tickstart = HAL_GetTick(); 8004d0a: f7ff facd bl 80042a8 8004d0e: 4606 mov r6, r0 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8004d10: 6a63 ldr r3, [r4, #36] ; 0x24 8004d12: 079f lsls r7, r3, #30 8004d14: f57f af43 bpl.w 8004b9e if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 8004d18: f7ff fac6 bl 80042a8 8004d1c: 1b80 subs r0, r0, r6 8004d1e: 2802 cmp r0, #2 8004d20: d9f6 bls.n 8004d10 8004d22: e771 b.n 8004c08 if(__HAL_RCC_PWR_IS_CLK_DISABLED()) 8004d24: 4c33 ldr r4, [pc, #204] ; (8004df4 ) 8004d26: 69e3 ldr r3, [r4, #28] 8004d28: 00d8 lsls r0, r3, #3 8004d2a: d424 bmi.n 8004d76 pwrclkchanged = SET; 8004d2c: 2701 movs r7, #1 __HAL_RCC_PWR_CLK_ENABLE(); 8004d2e: 69e3 ldr r3, [r4, #28] 8004d30: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8004d34: 61e3 str r3, [r4, #28] 8004d36: 69e3 ldr r3, [r4, #28] 8004d38: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8004d3c: 9300 str r3, [sp, #0] 8004d3e: 9b00 ldr r3, [sp, #0] if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8004d40: 4e30 ldr r6, [pc, #192] ; (8004e04 ) 8004d42: 6833 ldr r3, [r6, #0] 8004d44: 05d9 lsls r1, r3, #23 8004d46: d518 bpl.n 8004d7a __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8004d48: 68eb ldr r3, [r5, #12] 8004d4a: 2b01 cmp r3, #1 8004d4c: d126 bne.n 8004d9c 8004d4e: 6a23 ldr r3, [r4, #32] 8004d50: f043 0301 orr.w r3, r3, #1 8004d54: 6223 str r3, [r4, #32] tickstart = HAL_GetTick(); 8004d56: f7ff faa7 bl 80042a8 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 8004d5a: f241 3688 movw r6, #5000 ; 0x1388 tickstart = HAL_GetTick(); 8004d5e: 4680 mov r8, r0 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8004d60: 6a23 ldr r3, [r4, #32] 8004d62: 079b lsls r3, r3, #30 8004d64: d53f bpl.n 8004de6 if(pwrclkchanged == SET) 8004d66: 2f00 cmp r7, #0 8004d68: f43f af1d beq.w 8004ba6 __HAL_RCC_PWR_CLK_DISABLE(); 8004d6c: 69e3 ldr r3, [r4, #28] 8004d6e: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 8004d72: 61e3 str r3, [r4, #28] 8004d74: e717 b.n 8004ba6 FlagStatus pwrclkchanged = RESET; 8004d76: 2700 movs r7, #0 8004d78: e7e2 b.n 8004d40 SET_BIT(PWR->CR, PWR_CR_DBP); 8004d7a: 6833 ldr r3, [r6, #0] 8004d7c: f443 7380 orr.w r3, r3, #256 ; 0x100 8004d80: 6033 str r3, [r6, #0] tickstart = HAL_GetTick(); 8004d82: f7ff fa91 bl 80042a8 8004d86: 4680 mov r8, r0 while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8004d88: 6833 ldr r3, [r6, #0] 8004d8a: 05da lsls r2, r3, #23 8004d8c: d4dc bmi.n 8004d48 if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8004d8e: f7ff fa8b bl 80042a8 8004d92: eba0 0008 sub.w r0, r0, r8 8004d96: 2864 cmp r0, #100 ; 0x64 8004d98: d9f6 bls.n 8004d88 8004d9a: e735 b.n 8004c08 __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8004d9c: b9ab cbnz r3, 8004dca 8004d9e: 6a23 ldr r3, [r4, #32] if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 8004da0: f241 3888 movw r8, #5000 ; 0x1388 __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8004da4: f023 0301 bic.w r3, r3, #1 8004da8: 6223 str r3, [r4, #32] 8004daa: 6a23 ldr r3, [r4, #32] 8004dac: f023 0304 bic.w r3, r3, #4 8004db0: 6223 str r3, [r4, #32] tickstart = HAL_GetTick(); 8004db2: f7ff fa79 bl 80042a8 8004db6: 4606 mov r6, r0 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8004db8: 6a23 ldr r3, [r4, #32] 8004dba: 0798 lsls r0, r3, #30 8004dbc: d5d3 bpl.n 8004d66 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 8004dbe: f7ff fa73 bl 80042a8 8004dc2: 1b80 subs r0, r0, r6 8004dc4: 4540 cmp r0, r8 8004dc6: d9f7 bls.n 8004db8 8004dc8: e71e b.n 8004c08 __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8004dca: 2b05 cmp r3, #5 8004dcc: 6a23 ldr r3, [r4, #32] 8004dce: d103 bne.n 8004dd8 8004dd0: f043 0304 orr.w r3, r3, #4 8004dd4: 6223 str r3, [r4, #32] 8004dd6: e7ba b.n 8004d4e 8004dd8: f023 0301 bic.w r3, r3, #1 8004ddc: 6223 str r3, [r4, #32] 8004dde: 6a23 ldr r3, [r4, #32] 8004de0: f023 0304 bic.w r3, r3, #4 8004de4: e7b6 b.n 8004d54 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 8004de6: f7ff fa5f bl 80042a8 8004dea: eba0 0008 sub.w r0, r0, r8 8004dee: 42b0 cmp r0, r6 8004df0: d9b6 bls.n 8004d60 8004df2: e709 b.n 8004c08 8004df4: 40021000 .word 0x40021000 8004df8: 42420000 .word 0x42420000 8004dfc: 42420480 .word 0x42420480 8004e00: 20000008 .word 0x20000008 8004e04: 40007000 .word 0x40007000 if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 8004e08: 4c22 ldr r4, [pc, #136] ; (8004e94 ) 8004e0a: 6863 ldr r3, [r4, #4] 8004e0c: f003 030c and.w r3, r3, #12 8004e10: 2b08 cmp r3, #8 8004e12: f43f aee2 beq.w 8004bda 8004e16: 2300 movs r3, #0 8004e18: 4e1f ldr r6, [pc, #124] ; (8004e98 ) if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 8004e1a: 2a02 cmp r2, #2 __HAL_RCC_PLL_DISABLE(); 8004e1c: 6033 str r3, [r6, #0] if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 8004e1e: d12b bne.n 8004e78 tickstart = HAL_GetTick(); 8004e20: f7ff fa42 bl 80042a8 8004e24: 4607 mov r7, r0 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8004e26: 6823 ldr r3, [r4, #0] 8004e28: 0199 lsls r1, r3, #6 8004e2a: d41f bmi.n 8004e6c if(RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE) 8004e2c: 6a2b ldr r3, [r5, #32] 8004e2e: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8004e32: d105 bne.n 8004e40 __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); 8004e34: 6862 ldr r2, [r4, #4] 8004e36: 68a9 ldr r1, [r5, #8] 8004e38: f422 3200 bic.w r2, r2, #131072 ; 0x20000 8004e3c: 430a orrs r2, r1 8004e3e: 6062 str r2, [r4, #4] __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 8004e40: 6a69 ldr r1, [r5, #36] ; 0x24 8004e42: 6862 ldr r2, [r4, #4] 8004e44: 430b orrs r3, r1 8004e46: f422 1274 bic.w r2, r2, #3997696 ; 0x3d0000 8004e4a: 4313 orrs r3, r2 8004e4c: 6063 str r3, [r4, #4] __HAL_RCC_PLL_ENABLE(); 8004e4e: 2301 movs r3, #1 8004e50: 6033 str r3, [r6, #0] tickstart = HAL_GetTick(); 8004e52: f7ff fa29 bl 80042a8 8004e56: 4605 mov r5, r0 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8004e58: 6823 ldr r3, [r4, #0] 8004e5a: 019a lsls r2, r3, #6 8004e5c: f53f aea7 bmi.w 8004bae if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8004e60: f7ff fa22 bl 80042a8 8004e64: 1b40 subs r0, r0, r5 8004e66: 2802 cmp r0, #2 8004e68: d9f6 bls.n 8004e58 8004e6a: e6cd b.n 8004c08 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8004e6c: f7ff fa1c bl 80042a8 8004e70: 1bc0 subs r0, r0, r7 8004e72: 2802 cmp r0, #2 8004e74: d9d7 bls.n 8004e26 8004e76: e6c7 b.n 8004c08 tickstart = HAL_GetTick(); 8004e78: f7ff fa16 bl 80042a8 8004e7c: 4605 mov r5, r0 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8004e7e: 6823 ldr r3, [r4, #0] 8004e80: 019b lsls r3, r3, #6 8004e82: f57f ae94 bpl.w 8004bae if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8004e86: f7ff fa0f bl 80042a8 8004e8a: 1b40 subs r0, r0, r5 8004e8c: 2802 cmp r0, #2 8004e8e: d9f6 bls.n 8004e7e 8004e90: e6ba b.n 8004c08 8004e92: bf00 nop 8004e94: 40021000 .word 0x40021000 8004e98: 42420060 .word 0x42420060 08004e9c : { 8004e9c: b530 push {r4, r5, lr} const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; 8004e9e: 4b19 ldr r3, [pc, #100] ; (8004f04 ) { 8004ea0: b087 sub sp, #28 const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; 8004ea2: ac02 add r4, sp, #8 8004ea4: f103 0510 add.w r5, r3, #16 8004ea8: 4622 mov r2, r4 8004eaa: 6818 ldr r0, [r3, #0] 8004eac: 6859 ldr r1, [r3, #4] 8004eae: 3308 adds r3, #8 8004eb0: c203 stmia r2!, {r0, r1} 8004eb2: 42ab cmp r3, r5 8004eb4: 4614 mov r4, r2 8004eb6: d1f7 bne.n 8004ea8 const uint8_t aPredivFactorTable[2] = {1, 2}; 8004eb8: 2301 movs r3, #1 8004eba: f88d 3004 strb.w r3, [sp, #4] 8004ebe: 2302 movs r3, #2 tmpreg = RCC->CFGR; 8004ec0: 4911 ldr r1, [pc, #68] ; (8004f08 ) const uint8_t aPredivFactorTable[2] = {1, 2}; 8004ec2: f88d 3005 strb.w r3, [sp, #5] tmpreg = RCC->CFGR; 8004ec6: 684b ldr r3, [r1, #4] switch (tmpreg & RCC_CFGR_SWS) 8004ec8: f003 020c and.w r2, r3, #12 8004ecc: 2a08 cmp r2, #8 8004ece: d117 bne.n 8004f00 pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; 8004ed0: f3c3 4283 ubfx r2, r3, #18, #4 8004ed4: a806 add r0, sp, #24 8004ed6: 4402 add r2, r0 if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) 8004ed8: 03db lsls r3, r3, #15 pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; 8004eda: f812 2c10 ldrb.w r2, [r2, #-16] if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) 8004ede: d50c bpl.n 8004efa prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; 8004ee0: 684b ldr r3, [r1, #4] pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv); 8004ee2: 480a ldr r0, [pc, #40] ; (8004f0c ) prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; 8004ee4: f3c3 4340 ubfx r3, r3, #17, #1 pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv); 8004ee8: 4350 muls r0, r2 prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; 8004eea: aa06 add r2, sp, #24 8004eec: 4413 add r3, r2 8004eee: f813 3c14 ldrb.w r3, [r3, #-20] pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv); 8004ef2: fbb0 f0f3 udiv r0, r0, r3 } 8004ef6: b007 add sp, #28 8004ef8: bd30 pop {r4, r5, pc} pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); 8004efa: 4805 ldr r0, [pc, #20] ; (8004f10 ) 8004efc: 4350 muls r0, r2 8004efe: e7fa b.n 8004ef6 sysclockfreq = HSE_VALUE; 8004f00: 4802 ldr r0, [pc, #8] ; (8004f0c ) return sysclockfreq; 8004f02: e7f8 b.n 8004ef6 8004f04: 08007290 .word 0x08007290 8004f08: 40021000 .word 0x40021000 8004f0c: 007a1200 .word 0x007a1200 8004f10: 003d0900 .word 0x003d0900 08004f14 : if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY)) 8004f14: 4a54 ldr r2, [pc, #336] ; (8005068 ) { 8004f16: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY)) 8004f1a: 6813 ldr r3, [r2, #0] { 8004f1c: 4605 mov r5, r0 if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY)) 8004f1e: f003 0307 and.w r3, r3, #7 8004f22: 428b cmp r3, r1 { 8004f24: 460e mov r6, r1 if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY)) 8004f26: d32a bcc.n 8004f7e if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8004f28: 6829 ldr r1, [r5, #0] 8004f2a: 078c lsls r4, r1, #30 8004f2c: d434 bmi.n 8004f98 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 8004f2e: 07ca lsls r2, r1, #31 8004f30: d447 bmi.n 8004fc2 if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY)) 8004f32: 4a4d ldr r2, [pc, #308] ; (8005068 ) 8004f34: 6813 ldr r3, [r2, #0] 8004f36: f003 0307 and.w r3, r3, #7 8004f3a: 429e cmp r6, r3 8004f3c: f0c0 8082 bcc.w 8005044 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8004f40: 682a ldr r2, [r5, #0] 8004f42: 4c4a ldr r4, [pc, #296] ; (800506c ) 8004f44: f012 0f04 tst.w r2, #4 8004f48: f040 8087 bne.w 800505a if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8004f4c: 0713 lsls r3, r2, #28 8004f4e: d506 bpl.n 8004f5e MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); 8004f50: 6863 ldr r3, [r4, #4] 8004f52: 692a ldr r2, [r5, #16] 8004f54: f423 5360 bic.w r3, r3, #14336 ; 0x3800 8004f58: ea43 03c2 orr.w r3, r3, r2, lsl #3 8004f5c: 6063 str r3, [r4, #4] SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos]; 8004f5e: f7ff ff9d bl 8004e9c 8004f62: 6863 ldr r3, [r4, #4] 8004f64: 4a42 ldr r2, [pc, #264] ; (8005070 ) 8004f66: f3c3 1303 ubfx r3, r3, #4, #4 8004f6a: 5cd3 ldrb r3, [r2, r3] 8004f6c: 40d8 lsrs r0, r3 8004f6e: 4b41 ldr r3, [pc, #260] ; (8005074 ) 8004f70: 6018 str r0, [r3, #0] HAL_InitTick (TICK_INT_PRIORITY); 8004f72: 2000 movs r0, #0 8004f74: f7ff f956 bl 8004224 return HAL_OK; 8004f78: 2000 movs r0, #0 } 8004f7a: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} __HAL_FLASH_SET_LATENCY(FLatency); 8004f7e: 6813 ldr r3, [r2, #0] 8004f80: f023 0307 bic.w r3, r3, #7 8004f84: 430b orrs r3, r1 8004f86: 6013 str r3, [r2, #0] if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) 8004f88: 6813 ldr r3, [r2, #0] 8004f8a: f003 0307 and.w r3, r3, #7 8004f8e: 4299 cmp r1, r3 8004f90: d0ca beq.n 8004f28 return HAL_ERROR; 8004f92: 2001 movs r0, #1 8004f94: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8004f98: 4b34 ldr r3, [pc, #208] ; (800506c ) if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8004f9a: f011 0f04 tst.w r1, #4 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 8004f9e: bf1e ittt ne 8004fa0: 685a ldrne r2, [r3, #4] 8004fa2: f442 62e0 orrne.w r2, r2, #1792 ; 0x700 8004fa6: 605a strne r2, [r3, #4] if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8004fa8: 0708 lsls r0, r1, #28 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); 8004faa: bf42 ittt mi 8004fac: 685a ldrmi r2, [r3, #4] 8004fae: f442 5260 orrmi.w r2, r2, #14336 ; 0x3800 8004fb2: 605a strmi r2, [r3, #4] MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8004fb4: 685a ldr r2, [r3, #4] 8004fb6: 68a8 ldr r0, [r5, #8] 8004fb8: f022 02f0 bic.w r2, r2, #240 ; 0xf0 8004fbc: 4302 orrs r2, r0 8004fbe: 605a str r2, [r3, #4] 8004fc0: e7b5 b.n 8004f2e if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8004fc2: 686a ldr r2, [r5, #4] 8004fc4: 4c29 ldr r4, [pc, #164] ; (800506c ) 8004fc6: 2a01 cmp r2, #1 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8004fc8: 6823 ldr r3, [r4, #0] if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8004fca: d11c bne.n 8005006 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8004fcc: f413 3f00 tst.w r3, #131072 ; 0x20000 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8004fd0: d0df beq.n 8004f92 __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 8004fd2: 6863 ldr r3, [r4, #4] if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) 8004fd4: f241 3888 movw r8, #5000 ; 0x1388 __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 8004fd8: f023 0303 bic.w r3, r3, #3 8004fdc: 4313 orrs r3, r2 8004fde: 6063 str r3, [r4, #4] tickstart = HAL_GetTick(); 8004fe0: f7ff f962 bl 80042a8 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8004fe4: 686b ldr r3, [r5, #4] tickstart = HAL_GetTick(); 8004fe6: 4607 mov r7, r0 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8004fe8: 2b01 cmp r3, #1 8004fea: d114 bne.n 8005016 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) 8004fec: 6863 ldr r3, [r4, #4] 8004fee: f003 030c and.w r3, r3, #12 8004ff2: 2b04 cmp r3, #4 8004ff4: d09d beq.n 8004f32 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) 8004ff6: f7ff f957 bl 80042a8 8004ffa: 1bc0 subs r0, r0, r7 8004ffc: 4540 cmp r0, r8 8004ffe: d9f5 bls.n 8004fec return HAL_TIMEOUT; 8005000: 2003 movs r0, #3 8005002: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 8005006: 2a02 cmp r2, #2 8005008: d102 bne.n 8005010 if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 800500a: f013 7f00 tst.w r3, #33554432 ; 0x2000000 800500e: e7df b.n 8004fd0 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8005010: f013 0f02 tst.w r3, #2 8005014: e7dc b.n 8004fd0 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 8005016: 2b02 cmp r3, #2 8005018: d10f bne.n 800503a while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 800501a: 6863 ldr r3, [r4, #4] 800501c: f003 030c and.w r3, r3, #12 8005020: 2b08 cmp r3, #8 8005022: d086 beq.n 8004f32 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) 8005024: f7ff f940 bl 80042a8 8005028: 1bc0 subs r0, r0, r7 800502a: 4540 cmp r0, r8 800502c: d9f5 bls.n 800501a 800502e: e7e7 b.n 8005000 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) 8005030: f7ff f93a bl 80042a8 8005034: 1bc0 subs r0, r0, r7 8005036: 4540 cmp r0, r8 8005038: d8e2 bhi.n 8005000 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) 800503a: 6863 ldr r3, [r4, #4] 800503c: f013 0f0c tst.w r3, #12 8005040: d1f6 bne.n 8005030 8005042: e776 b.n 8004f32 __HAL_FLASH_SET_LATENCY(FLatency); 8005044: 6813 ldr r3, [r2, #0] 8005046: f023 0307 bic.w r3, r3, #7 800504a: 4333 orrs r3, r6 800504c: 6013 str r3, [r2, #0] if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) 800504e: 6813 ldr r3, [r2, #0] 8005050: f003 0307 and.w r3, r3, #7 8005054: 429e cmp r6, r3 8005056: d19c bne.n 8004f92 8005058: e772 b.n 8004f40 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 800505a: 6863 ldr r3, [r4, #4] 800505c: 68e9 ldr r1, [r5, #12] 800505e: f423 63e0 bic.w r3, r3, #1792 ; 0x700 8005062: 430b orrs r3, r1 8005064: 6063 str r3, [r4, #4] 8005066: e771 b.n 8004f4c 8005068: 40022000 .word 0x40022000 800506c: 40021000 .word 0x40021000 8005070: 080072ad .word 0x080072ad 8005074: 20000008 .word 0x20000008 08005078 : return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); 8005078: 4b04 ldr r3, [pc, #16] ; (800508c ) 800507a: 4a05 ldr r2, [pc, #20] ; (8005090 ) 800507c: 685b ldr r3, [r3, #4] 800507e: f3c3 2302 ubfx r3, r3, #8, #3 8005082: 5cd3 ldrb r3, [r2, r3] 8005084: 4a03 ldr r2, [pc, #12] ; (8005094 ) 8005086: 6810 ldr r0, [r2, #0] } 8005088: 40d8 lsrs r0, r3 800508a: 4770 bx lr 800508c: 40021000 .word 0x40021000 8005090: 080072bd .word 0x080072bd 8005094: 20000008 .word 0x20000008 08005098 : return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); 8005098: 4b04 ldr r3, [pc, #16] ; (80050ac ) 800509a: 4a05 ldr r2, [pc, #20] ; (80050b0 ) 800509c: 685b ldr r3, [r3, #4] 800509e: f3c3 23c2 ubfx r3, r3, #11, #3 80050a2: 5cd3 ldrb r3, [r2, r3] 80050a4: 4a03 ldr r2, [pc, #12] ; (80050b4 ) 80050a6: 6810 ldr r0, [r2, #0] } 80050a8: 40d8 lsrs r0, r3 80050aa: 4770 bx lr 80050ac: 40021000 .word 0x40021000 80050b0: 080072bd .word 0x080072bd 80050b4: 20000008 .word 0x20000008 080050b8 : /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*------------------------------- RTC/LCD Configuration ------------------------*/ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 80050b8: 6803 ldr r3, [r0, #0] { 80050ba: e92d 41f3 stmdb sp!, {r0, r1, r4, r5, r6, r7, r8, lr} if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 80050be: 07d9 lsls r1, r3, #31 { 80050c0: 4605 mov r5, r0 if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 80050c2: d520 bpl.n 8005106 FlagStatus pwrclkchanged = RESET; /* As soon as function is called to change RTC clock source, activation of the power domain is done. */ /* Requires to enable write access to Backup Domain of necessary */ if(__HAL_RCC_PWR_IS_CLK_DISABLED()) 80050c4: 4c35 ldr r4, [pc, #212] ; (800519c ) 80050c6: 69e3 ldr r3, [r4, #28] 80050c8: 00da lsls r2, r3, #3 80050ca: d432 bmi.n 8005132 { __HAL_RCC_PWR_CLK_ENABLE(); pwrclkchanged = SET; 80050cc: 2701 movs r7, #1 __HAL_RCC_PWR_CLK_ENABLE(); 80050ce: 69e3 ldr r3, [r4, #28] 80050d0: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 80050d4: 61e3 str r3, [r4, #28] 80050d6: 69e3 ldr r3, [r4, #28] 80050d8: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 80050dc: 9301 str r3, [sp, #4] 80050de: 9b01 ldr r3, [sp, #4] } if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80050e0: 4e2f ldr r6, [pc, #188] ; (80051a0 ) 80050e2: 6833 ldr r3, [r6, #0] 80050e4: 05db lsls r3, r3, #23 80050e6: d526 bpl.n 8005136 } } } /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); 80050e8: 6a23 ldr r3, [r4, #32] if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) 80050ea: f413 7340 ands.w r3, r3, #768 ; 0x300 80050ee: d136 bne.n 800515e return HAL_TIMEOUT; } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 80050f0: 6a23 ldr r3, [r4, #32] 80050f2: 686a ldr r2, [r5, #4] 80050f4: f423 7340 bic.w r3, r3, #768 ; 0x300 80050f8: 4313 orrs r3, r2 80050fa: 6223 str r3, [r4, #32] /* Require to disable power clock if necessary */ if(pwrclkchanged == SET) 80050fc: b11f cbz r7, 8005106 { __HAL_RCC_PWR_CLK_DISABLE(); 80050fe: 69e3 ldr r3, [r4, #28] 8005100: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 8005104: 61e3 str r3, [r4, #28] } } /*------------------------------ ADC clock Configuration ------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 8005106: 6828 ldr r0, [r5, #0] 8005108: 0783 lsls r3, r0, #30 800510a: d506 bpl.n 800511a { /* Check the parameters */ assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection)); /* Configure the ADC clock source */ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 800510c: 4a23 ldr r2, [pc, #140] ; (800519c ) 800510e: 68a9 ldr r1, [r5, #8] 8005110: 6853 ldr r3, [r2, #4] 8005112: f423 4340 bic.w r3, r3, #49152 ; 0xc000 8005116: 430b orrs r3, r1 8005118: 6053 str r3, [r2, #4] #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ || defined(STM32F105xC) || defined(STM32F107xC) /*------------------------------ USB clock Configuration ------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) 800511a: f010 0010 ands.w r0, r0, #16 800511e: d01b beq.n 8005158 { /* Check the parameters */ assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection)); /* Configure the USB clock source */ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 8005120: 4a1e ldr r2, [pc, #120] ; (800519c ) 8005122: 6969 ldr r1, [r5, #20] 8005124: 6853 ldr r3, [r2, #4] } #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ return HAL_OK; 8005126: 2000 movs r0, #0 __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 8005128: f423 0380 bic.w r3, r3, #4194304 ; 0x400000 800512c: 430b orrs r3, r1 800512e: 6053 str r3, [r2, #4] 8005130: e012 b.n 8005158 FlagStatus pwrclkchanged = RESET; 8005132: 2700 movs r7, #0 8005134: e7d4 b.n 80050e0 SET_BIT(PWR->CR, PWR_CR_DBP); 8005136: 6833 ldr r3, [r6, #0] 8005138: f443 7380 orr.w r3, r3, #256 ; 0x100 800513c: 6033 str r3, [r6, #0] tickstart = HAL_GetTick(); 800513e: f7ff f8b3 bl 80042a8 8005142: 4680 mov r8, r0 while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8005144: 6833 ldr r3, [r6, #0] 8005146: 05d8 lsls r0, r3, #23 8005148: d4ce bmi.n 80050e8 if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 800514a: f7ff f8ad bl 80042a8 800514e: eba0 0008 sub.w r0, r0, r8 8005152: 2864 cmp r0, #100 ; 0x64 8005154: d9f6 bls.n 8005144 return HAL_TIMEOUT; 8005156: 2003 movs r0, #3 } 8005158: b002 add sp, #8 800515a: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) 800515e: 686a ldr r2, [r5, #4] 8005160: f402 7240 and.w r2, r2, #768 ; 0x300 8005164: 4293 cmp r3, r2 8005166: d0c3 beq.n 80050f0 __HAL_RCC_BACKUPRESET_FORCE(); 8005168: 2001 movs r0, #1 800516a: 4a0e ldr r2, [pc, #56] ; (80051a4 ) temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 800516c: 6a23 ldr r3, [r4, #32] __HAL_RCC_BACKUPRESET_FORCE(); 800516e: 6010 str r0, [r2, #0] __HAL_RCC_BACKUPRESET_RELEASE(); 8005170: 2000 movs r0, #0 temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 8005172: f423 7140 bic.w r1, r3, #768 ; 0x300 __HAL_RCC_BACKUPRESET_RELEASE(); 8005176: 6010 str r0, [r2, #0] RCC->BDCR = temp_reg; 8005178: 6221 str r1, [r4, #32] if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) 800517a: 07d9 lsls r1, r3, #31 800517c: d5b8 bpl.n 80050f0 tickstart = HAL_GetTick(); 800517e: f7ff f893 bl 80042a8 if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8005182: f241 3888 movw r8, #5000 ; 0x1388 tickstart = HAL_GetTick(); 8005186: 4606 mov r6, r0 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8005188: 6a23 ldr r3, [r4, #32] 800518a: 079a lsls r2, r3, #30 800518c: d4b0 bmi.n 80050f0 if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800518e: f7ff f88b bl 80042a8 8005192: 1b80 subs r0, r0, r6 8005194: 4540 cmp r0, r8 8005196: d9f7 bls.n 8005188 8005198: e7dd b.n 8005156 800519a: bf00 nop 800519c: 40021000 .word 0x40021000 80051a0: 40007000 .word 0x40007000 80051a4: 42420440 .word 0x42420440 080051a8 : 80051a8: 4770 bx lr 080051aa : 80051aa: 4770 bx lr 080051ac : 80051ac: 4770 bx lr 080051ae : 80051ae: 4770 bx lr 080051b0 : * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { /* Capture compare 1 event */ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) 80051b0: 6803 ldr r3, [r0, #0] { 80051b2: b510 push {r4, lr} if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) 80051b4: 691a ldr r2, [r3, #16] { 80051b6: 4604 mov r4, r0 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) 80051b8: 0791 lsls r1, r2, #30 80051ba: d50e bpl.n 80051da { if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET) 80051bc: 68da ldr r2, [r3, #12] 80051be: 0792 lsls r2, r2, #30 80051c0: d50b bpl.n 80051da { { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); 80051c2: f06f 0202 mvn.w r2, #2 80051c6: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 80051c8: 2201 movs r2, #1 /* Input capture event */ if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 80051ca: 699b ldr r3, [r3, #24] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 80051cc: 7702 strb r2, [r0, #28] if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 80051ce: 079b lsls r3, r3, #30 80051d0: d077 beq.n 80052c2 { HAL_TIM_IC_CaptureCallback(htim); 80051d2: f7ff ffea bl 80051aa else { HAL_TIM_OC_DelayElapsedCallback(htim); HAL_TIM_PWM_PulseFinishedCallback(htim); } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 80051d6: 2300 movs r3, #0 80051d8: 7723 strb r3, [r4, #28] } } } /* Capture compare 2 event */ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) 80051da: 6823 ldr r3, [r4, #0] 80051dc: 691a ldr r2, [r3, #16] 80051de: 0750 lsls r0, r2, #29 80051e0: d510 bpl.n 8005204 { if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET) 80051e2: 68da ldr r2, [r3, #12] 80051e4: 0751 lsls r1, r2, #29 80051e6: d50d bpl.n 8005204 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); 80051e8: f06f 0204 mvn.w r2, #4 80051ec: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 80051ee: 2202 movs r2, #2 /* Input capture event */ if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 80051f0: 699b ldr r3, [r3, #24] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 80051f2: 7722 strb r2, [r4, #28] if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 80051f4: f413 7f40 tst.w r3, #768 ; 0x300 { HAL_TIM_IC_CaptureCallback(htim); 80051f8: 4620 mov r0, r4 if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 80051fa: d068 beq.n 80052ce HAL_TIM_IC_CaptureCallback(htim); 80051fc: f7ff ffd5 bl 80051aa else { HAL_TIM_OC_DelayElapsedCallback(htim); HAL_TIM_PWM_PulseFinishedCallback(htim); } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8005200: 2300 movs r3, #0 8005202: 7723 strb r3, [r4, #28] } } /* Capture compare 3 event */ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) 8005204: 6823 ldr r3, [r4, #0] 8005206: 691a ldr r2, [r3, #16] 8005208: 0712 lsls r2, r2, #28 800520a: d50f bpl.n 800522c { if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET) 800520c: 68da ldr r2, [r3, #12] 800520e: 0710 lsls r0, r2, #28 8005210: d50c bpl.n 800522c { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); 8005212: f06f 0208 mvn.w r2, #8 8005216: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 8005218: 2204 movs r2, #4 /* Input capture event */ if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 800521a: 69db ldr r3, [r3, #28] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 800521c: 7722 strb r2, [r4, #28] if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 800521e: 0799 lsls r1, r3, #30 { HAL_TIM_IC_CaptureCallback(htim); 8005220: 4620 mov r0, r4 if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 8005222: d05a beq.n 80052da HAL_TIM_IC_CaptureCallback(htim); 8005224: f7ff ffc1 bl 80051aa else { HAL_TIM_OC_DelayElapsedCallback(htim); HAL_TIM_PWM_PulseFinishedCallback(htim); } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8005228: 2300 movs r3, #0 800522a: 7723 strb r3, [r4, #28] } } /* Capture compare 4 event */ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) 800522c: 6823 ldr r3, [r4, #0] 800522e: 691a ldr r2, [r3, #16] 8005230: 06d2 lsls r2, r2, #27 8005232: d510 bpl.n 8005256 { if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET) 8005234: 68da ldr r2, [r3, #12] 8005236: 06d0 lsls r0, r2, #27 8005238: d50d bpl.n 8005256 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); 800523a: f06f 0210 mvn.w r2, #16 800523e: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 8005240: 2208 movs r2, #8 /* Input capture event */ if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 8005242: 69db ldr r3, [r3, #28] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 8005244: 7722 strb r2, [r4, #28] if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 8005246: f413 7f40 tst.w r3, #768 ; 0x300 { HAL_TIM_IC_CaptureCallback(htim); 800524a: 4620 mov r0, r4 if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 800524c: d04b beq.n 80052e6 HAL_TIM_IC_CaptureCallback(htim); 800524e: f7ff ffac bl 80051aa else { HAL_TIM_OC_DelayElapsedCallback(htim); HAL_TIM_PWM_PulseFinishedCallback(htim); } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8005252: 2300 movs r3, #0 8005254: 7723 strb r3, [r4, #28] } } /* TIM Update event */ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) 8005256: 6823 ldr r3, [r4, #0] 8005258: 691a ldr r2, [r3, #16] 800525a: 07d1 lsls r1, r2, #31 800525c: d508 bpl.n 8005270 { if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET) 800525e: 68da ldr r2, [r3, #12] 8005260: 07d2 lsls r2, r2, #31 8005262: d505 bpl.n 8005270 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); 8005264: f06f 0201 mvn.w r2, #1 HAL_TIM_PeriodElapsedCallback(htim); 8005268: 4620 mov r0, r4 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); 800526a: 611a str r2, [r3, #16] HAL_TIM_PeriodElapsedCallback(htim); 800526c: f000 fba4 bl 80059b8 } } /* TIM Break input event */ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) 8005270: 6823 ldr r3, [r4, #0] 8005272: 691a ldr r2, [r3, #16] 8005274: 0610 lsls r0, r2, #24 8005276: d508 bpl.n 800528a { if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET) 8005278: 68da ldr r2, [r3, #12] 800527a: 0611 lsls r1, r2, #24 800527c: d505 bpl.n 800528a { __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); 800527e: f06f 0280 mvn.w r2, #128 ; 0x80 HAL_TIMEx_BreakCallback(htim); 8005282: 4620 mov r0, r4 __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); 8005284: 611a str r2, [r3, #16] HAL_TIMEx_BreakCallback(htim); 8005286: f000 f8be bl 8005406 } } /* TIM Trigger detection event */ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) 800528a: 6823 ldr r3, [r4, #0] 800528c: 691a ldr r2, [r3, #16] 800528e: 0652 lsls r2, r2, #25 8005290: d508 bpl.n 80052a4 { if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET) 8005292: 68da ldr r2, [r3, #12] 8005294: 0650 lsls r0, r2, #25 8005296: d505 bpl.n 80052a4 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); 8005298: f06f 0240 mvn.w r2, #64 ; 0x40 HAL_TIM_TriggerCallback(htim); 800529c: 4620 mov r0, r4 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); 800529e: 611a str r2, [r3, #16] HAL_TIM_TriggerCallback(htim); 80052a0: f7ff ff85 bl 80051ae } } /* TIM commutation event */ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) 80052a4: 6823 ldr r3, [r4, #0] 80052a6: 691a ldr r2, [r3, #16] 80052a8: 0691 lsls r1, r2, #26 80052aa: d522 bpl.n 80052f2 { if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET) 80052ac: 68da ldr r2, [r3, #12] 80052ae: 0692 lsls r2, r2, #26 80052b0: d51f bpl.n 80052f2 { __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); 80052b2: f06f 0220 mvn.w r2, #32 HAL_TIMEx_CommutationCallback(htim); 80052b6: 4620 mov r0, r4 } } } 80052b8: e8bd 4010 ldmia.w sp!, {r4, lr} __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); 80052bc: 611a str r2, [r3, #16] HAL_TIMEx_CommutationCallback(htim); 80052be: f000 b8a1 b.w 8005404 HAL_TIM_OC_DelayElapsedCallback(htim); 80052c2: f7ff ff71 bl 80051a8 HAL_TIM_PWM_PulseFinishedCallback(htim); 80052c6: 4620 mov r0, r4 80052c8: f7ff ff70 bl 80051ac 80052cc: e783 b.n 80051d6 HAL_TIM_OC_DelayElapsedCallback(htim); 80052ce: f7ff ff6b bl 80051a8 HAL_TIM_PWM_PulseFinishedCallback(htim); 80052d2: 4620 mov r0, r4 80052d4: f7ff ff6a bl 80051ac 80052d8: e792 b.n 8005200 HAL_TIM_OC_DelayElapsedCallback(htim); 80052da: f7ff ff65 bl 80051a8 HAL_TIM_PWM_PulseFinishedCallback(htim); 80052de: 4620 mov r0, r4 80052e0: f7ff ff64 bl 80051ac 80052e4: e7a0 b.n 8005228 HAL_TIM_OC_DelayElapsedCallback(htim); 80052e6: f7ff ff5f bl 80051a8 HAL_TIM_PWM_PulseFinishedCallback(htim); 80052ea: 4620 mov r0, r4 80052ec: f7ff ff5e bl 80051ac 80052f0: e7af b.n 8005252 80052f2: bd10 pop {r4, pc} 080052f4 : { uint32_t tmpcr1 = 0U; tmpcr1 = TIMx->CR1; /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 80052f4: 4a24 ldr r2, [pc, #144] ; (8005388 ) tmpcr1 = TIMx->CR1; 80052f6: 6803 ldr r3, [r0, #0] if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 80052f8: 4290 cmp r0, r2 80052fa: d012 beq.n 8005322 80052fc: f502 6200 add.w r2, r2, #2048 ; 0x800 8005300: 4290 cmp r0, r2 8005302: d00e beq.n 8005322 8005304: f1b0 4f80 cmp.w r0, #1073741824 ; 0x40000000 8005308: d00b beq.n 8005322 800530a: f5a2 3298 sub.w r2, r2, #77824 ; 0x13000 800530e: 4290 cmp r0, r2 8005310: d007 beq.n 8005322 8005312: f502 6280 add.w r2, r2, #1024 ; 0x400 8005316: 4290 cmp r0, r2 8005318: d003 beq.n 8005322 800531a: f502 6280 add.w r2, r2, #1024 ; 0x400 800531e: 4290 cmp r0, r2 8005320: d11d bne.n 800535e { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); tmpcr1 |= Structure->CounterMode; 8005322: 684a ldr r2, [r1, #4] tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 8005324: f023 0370 bic.w r3, r3, #112 ; 0x70 tmpcr1 |= Structure->CounterMode; 8005328: 4313 orrs r3, r2 } if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 800532a: 4a17 ldr r2, [pc, #92] ; (8005388 ) 800532c: 4290 cmp r0, r2 800532e: d012 beq.n 8005356 8005330: f502 6200 add.w r2, r2, #2048 ; 0x800 8005334: 4290 cmp r0, r2 8005336: d00e beq.n 8005356 8005338: f1b0 4f80 cmp.w r0, #1073741824 ; 0x40000000 800533c: d00b beq.n 8005356 800533e: f5a2 3298 sub.w r2, r2, #77824 ; 0x13000 8005342: 4290 cmp r0, r2 8005344: d007 beq.n 8005356 8005346: f502 6280 add.w r2, r2, #1024 ; 0x400 800534a: 4290 cmp r0, r2 800534c: d003 beq.n 8005356 800534e: f502 6280 add.w r2, r2, #1024 ; 0x400 8005352: 4290 cmp r0, r2 8005354: d103 bne.n 800535e { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; tmpcr1 |= (uint32_t)Structure->ClockDivision; 8005356: 68ca ldr r2, [r1, #12] tmpcr1 &= ~TIM_CR1_CKD; 8005358: f423 7340 bic.w r3, r3, #768 ; 0x300 tmpcr1 |= (uint32_t)Structure->ClockDivision; 800535c: 4313 orrs r3, r2 } /* Set the auto-reload preload */ tmpcr1 &= ~TIM_CR1_ARPE; tmpcr1 |= (uint32_t)Structure->AutoReloadPreload; 800535e: 694a ldr r2, [r1, #20] tmpcr1 &= ~TIM_CR1_ARPE; 8005360: f023 0380 bic.w r3, r3, #128 ; 0x80 tmpcr1 |= (uint32_t)Structure->AutoReloadPreload; 8005364: 4313 orrs r3, r2 TIMx->CR1 = tmpcr1; 8005366: 6003 str r3, [r0, #0] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 8005368: 688b ldr r3, [r1, #8] 800536a: 62c3 str r3, [r0, #44] ; 0x2c /* Set the Prescaler value */ TIMx->PSC = (uint32_t)Structure->Prescaler; 800536c: 680b ldr r3, [r1, #0] 800536e: 6283 str r3, [r0, #40] ; 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 8005370: 4b05 ldr r3, [pc, #20] ; (8005388 ) 8005372: 4298 cmp r0, r3 8005374: d003 beq.n 800537e 8005376: f503 6300 add.w r3, r3, #2048 ; 0x800 800537a: 4298 cmp r0, r3 800537c: d101 bne.n 8005382 { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 800537e: 690b ldr r3, [r1, #16] 8005380: 6303 str r3, [r0, #48] ; 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter(only for TIM1 and TIM8) value immediatly */ TIMx->EGR = TIM_EGR_UG; 8005382: 2301 movs r3, #1 8005384: 6143 str r3, [r0, #20] 8005386: 4770 bx lr 8005388: 40012c00 .word 0x40012c00 0800538c : { 800538c: b510 push {r4, lr} if(htim == NULL) 800538e: 4604 mov r4, r0 8005390: b1a0 cbz r0, 80053bc if(htim->State == HAL_TIM_STATE_RESET) 8005392: f890 303d ldrb.w r3, [r0, #61] ; 0x3d 8005396: f003 02ff and.w r2, r3, #255 ; 0xff 800539a: b91b cbnz r3, 80053a4 htim->Lock = HAL_UNLOCKED; 800539c: f880 203c strb.w r2, [r0, #60] ; 0x3c HAL_TIM_Base_MspInit(htim); 80053a0: f000 fdc2 bl 8005f28 htim->State= HAL_TIM_STATE_BUSY; 80053a4: 2302 movs r3, #2 TIM_Base_SetConfig(htim->Instance, &htim->Init); 80053a6: 6820 ldr r0, [r4, #0] htim->State= HAL_TIM_STATE_BUSY; 80053a8: f884 303d strb.w r3, [r4, #61] ; 0x3d TIM_Base_SetConfig(htim->Instance, &htim->Init); 80053ac: 1d21 adds r1, r4, #4 80053ae: f7ff ffa1 bl 80052f4 htim->State= HAL_TIM_STATE_READY; 80053b2: 2301 movs r3, #1 return HAL_OK; 80053b4: 2000 movs r0, #0 htim->State= HAL_TIM_STATE_READY; 80053b6: f884 303d strb.w r3, [r4, #61] ; 0x3d return HAL_OK; 80053ba: bd10 pop {r4, pc} return HAL_ERROR; 80053bc: 2001 movs r0, #1 } 80053be: bd10 pop {r4, pc} 080053c0 : /* Check the parameters */ assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); __HAL_LOCK(htim); 80053c0: f890 303c ldrb.w r3, [r0, #60] ; 0x3c { 80053c4: b510 push {r4, lr} __HAL_LOCK(htim); 80053c6: 2b01 cmp r3, #1 80053c8: f04f 0302 mov.w r3, #2 80053cc: d018 beq.n 8005400 htim->State = HAL_TIM_STATE_BUSY; 80053ce: f880 303d strb.w r3, [r0, #61] ; 0x3d /* Reset the MMS Bits */ htim->Instance->CR2 &= ~TIM_CR2_MMS; 80053d2: 6803 ldr r3, [r0, #0] /* Select the TRGO source */ htim->Instance->CR2 |= sMasterConfig->MasterOutputTrigger; 80053d4: 680c ldr r4, [r1, #0] htim->Instance->CR2 &= ~TIM_CR2_MMS; 80053d6: 685a ldr r2, [r3, #4] /* Reset the MSM Bit */ htim->Instance->SMCR &= ~TIM_SMCR_MSM; /* Set or Reset the MSM Bit */ htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode; 80053d8: 6849 ldr r1, [r1, #4] htim->Instance->CR2 &= ~TIM_CR2_MMS; 80053da: f022 0270 bic.w r2, r2, #112 ; 0x70 80053de: 605a str r2, [r3, #4] htim->Instance->CR2 |= sMasterConfig->MasterOutputTrigger; 80053e0: 685a ldr r2, [r3, #4] 80053e2: 4322 orrs r2, r4 80053e4: 605a str r2, [r3, #4] htim->Instance->SMCR &= ~TIM_SMCR_MSM; 80053e6: 689a ldr r2, [r3, #8] 80053e8: f022 0280 bic.w r2, r2, #128 ; 0x80 80053ec: 609a str r2, [r3, #8] htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode; 80053ee: 689a ldr r2, [r3, #8] 80053f0: 430a orrs r2, r1 80053f2: 609a str r2, [r3, #8] htim->State = HAL_TIM_STATE_READY; 80053f4: 2301 movs r3, #1 80053f6: f880 303d strb.w r3, [r0, #61] ; 0x3d __HAL_UNLOCK(htim); 80053fa: 2300 movs r3, #0 80053fc: f880 303c strb.w r3, [r0, #60] ; 0x3c __HAL_LOCK(htim); 8005400: 4618 mov r0, r3 return HAL_OK; } 8005402: bd10 pop {r4, pc} 08005404 : 8005404: 4770 bx lr 08005406 : * @brief Hall Break detection callback in non blocking mode * @param htim : TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { 8005406: 4770 bx lr 08005408 : * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 8005408: 6803 ldr r3, [r0, #0] 800540a: 68da ldr r2, [r3, #12] 800540c: f422 7290 bic.w r2, r2, #288 ; 0x120 8005410: 60da str r2, [r3, #12] CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8005412: 695a ldr r2, [r3, #20] 8005414: f022 0201 bic.w r2, r2, #1 8005418: 615a str r2, [r3, #20] /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 800541a: 2320 movs r3, #32 800541c: f880 303a strb.w r3, [r0, #58] ; 0x3a 8005420: 4770 bx lr ... 08005424 : * @param huart: pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_SetConfig(UART_HandleTypeDef *huart) { 8005424: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} assert_param(IS_UART_MODE(huart->Init.Mode)); /*------- UART-associated USART registers setting : CR2 Configuration ------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according * to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 8005428: 6805 ldr r5, [r0, #0] 800542a: 68c2 ldr r2, [r0, #12] 800542c: 692b ldr r3, [r5, #16] tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; MODIFY_REG(huart->Instance->CR1, (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), tmpreg); #else tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode; 800542e: 6901 ldr r1, [r0, #16] MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 8005430: f423 5340 bic.w r3, r3, #12288 ; 0x3000 8005434: 4313 orrs r3, r2 8005436: 612b str r3, [r5, #16] tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode; 8005438: 6883 ldr r3, [r0, #8] MODIFY_REG(huart->Instance->CR1, 800543a: 68ea ldr r2, [r5, #12] tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode; 800543c: 430b orrs r3, r1 800543e: 6941 ldr r1, [r0, #20] MODIFY_REG(huart->Instance->CR1, 8005440: f422 52b0 bic.w r2, r2, #5632 ; 0x1600 8005444: f022 020c bic.w r2, r2, #12 tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode; 8005448: 430b orrs r3, r1 MODIFY_REG(huart->Instance->CR1, 800544a: 4313 orrs r3, r2 800544c: 60eb str r3, [r5, #12] tmpreg); #endif /* USART_CR1_OVER8 */ /*------- UART-associated USART registers setting : CR3 Configuration ------*/ /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); 800544e: 696b ldr r3, [r5, #20] 8005450: 6982 ldr r2, [r0, #24] 8005452: f423 7340 bic.w r3, r3, #768 ; 0x300 8005456: 4313 orrs r3, r2 8005458: 616b str r3, [r5, #20] huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate); } } #else /*-------------------------- USART BRR Configuration ---------------------*/ if(huart->Instance == USART1) 800545a: 4b40 ldr r3, [pc, #256] ; (800555c ) { 800545c: 4681 mov r9, r0 if(huart->Instance == USART1) 800545e: 429d cmp r5, r3 8005460: f04f 0419 mov.w r4, #25 8005464: d146 bne.n 80054f4 { huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate); 8005466: f7ff fe17 bl 8005098 800546a: fb04 f300 mul.w r3, r4, r0 800546e: f8d9 6004 ldr.w r6, [r9, #4] 8005472: f04f 0864 mov.w r8, #100 ; 0x64 8005476: 00b6 lsls r6, r6, #2 8005478: fbb3 f3f6 udiv r3, r3, r6 800547c: fbb3 f3f8 udiv r3, r3, r8 8005480: 011e lsls r6, r3, #4 8005482: f7ff fe09 bl 8005098 8005486: 4360 muls r0, r4 8005488: f8d9 3004 ldr.w r3, [r9, #4] 800548c: 009b lsls r3, r3, #2 800548e: fbb0 f7f3 udiv r7, r0, r3 8005492: f7ff fe01 bl 8005098 8005496: 4360 muls r0, r4 8005498: f8d9 3004 ldr.w r3, [r9, #4] 800549c: 009b lsls r3, r3, #2 800549e: fbb0 f3f3 udiv r3, r0, r3 80054a2: fbb3 f3f8 udiv r3, r3, r8 80054a6: fb08 7313 mls r3, r8, r3, r7 80054aa: 011b lsls r3, r3, #4 80054ac: 3332 adds r3, #50 ; 0x32 80054ae: fbb3 f3f8 udiv r3, r3, r8 80054b2: f003 07f0 and.w r7, r3, #240 ; 0xf0 80054b6: f7ff fdef bl 8005098 80054ba: 4360 muls r0, r4 80054bc: f8d9 2004 ldr.w r2, [r9, #4] 80054c0: 0092 lsls r2, r2, #2 80054c2: fbb0 faf2 udiv sl, r0, r2 80054c6: f7ff fde7 bl 8005098 } else { huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate); 80054ca: 4360 muls r0, r4 80054cc: f8d9 3004 ldr.w r3, [r9, #4] 80054d0: 009b lsls r3, r3, #2 80054d2: fbb0 f3f3 udiv r3, r0, r3 80054d6: fbb3 f3f8 udiv r3, r3, r8 80054da: fb08 a313 mls r3, r8, r3, sl 80054de: 011b lsls r3, r3, #4 80054e0: 3332 adds r3, #50 ; 0x32 80054e2: fbb3 f3f8 udiv r3, r3, r8 80054e6: f003 030f and.w r3, r3, #15 80054ea: 433b orrs r3, r7 80054ec: 4433 add r3, r6 80054ee: 60ab str r3, [r5, #8] 80054f0: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80054f4: f7ff fdc0 bl 8005078 80054f8: fb04 f300 mul.w r3, r4, r0 80054fc: f8d9 6004 ldr.w r6, [r9, #4] 8005500: f04f 0864 mov.w r8, #100 ; 0x64 8005504: 00b6 lsls r6, r6, #2 8005506: fbb3 f3f6 udiv r3, r3, r6 800550a: fbb3 f3f8 udiv r3, r3, r8 800550e: 011e lsls r6, r3, #4 8005510: f7ff fdb2 bl 8005078 8005514: 4360 muls r0, r4 8005516: f8d9 3004 ldr.w r3, [r9, #4] 800551a: 009b lsls r3, r3, #2 800551c: fbb0 f7f3 udiv r7, r0, r3 8005520: f7ff fdaa bl 8005078 8005524: 4360 muls r0, r4 8005526: f8d9 3004 ldr.w r3, [r9, #4] 800552a: 009b lsls r3, r3, #2 800552c: fbb0 f3f3 udiv r3, r0, r3 8005530: fbb3 f3f8 udiv r3, r3, r8 8005534: fb08 7313 mls r3, r8, r3, r7 8005538: 011b lsls r3, r3, #4 800553a: 3332 adds r3, #50 ; 0x32 800553c: fbb3 f3f8 udiv r3, r3, r8 8005540: f003 07f0 and.w r7, r3, #240 ; 0xf0 8005544: f7ff fd98 bl 8005078 8005548: 4360 muls r0, r4 800554a: f8d9 2004 ldr.w r2, [r9, #4] 800554e: 0092 lsls r2, r2, #2 8005550: fbb0 faf2 udiv sl, r0, r2 8005554: f7ff fd90 bl 8005078 8005558: e7b7 b.n 80054ca 800555a: bf00 nop 800555c: 40013800 .word 0x40013800 08005560 : static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) 8005560: b5f8 push {r3, r4, r5, r6, r7, lr} 8005562: 4604 mov r4, r0 8005564: 460e mov r6, r1 8005566: 4617 mov r7, r2 8005568: 461d mov r5, r3 while((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 800556a: 6821 ldr r1, [r4, #0] 800556c: 680b ldr r3, [r1, #0] 800556e: ea36 0303 bics.w r3, r6, r3 8005572: d101 bne.n 8005578 return HAL_OK; 8005574: 2000 movs r0, #0 } 8005576: bdf8 pop {r3, r4, r5, r6, r7, pc} if(Timeout != HAL_MAX_DELAY) 8005578: 1c6b adds r3, r5, #1 800557a: d0f7 beq.n 800556c if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout)) 800557c: b995 cbnz r5, 80055a4 CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); 800557e: 6823 ldr r3, [r4, #0] __HAL_UNLOCK(huart); 8005580: 2003 movs r0, #3 CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); 8005582: 68da ldr r2, [r3, #12] 8005584: f422 72d0 bic.w r2, r2, #416 ; 0x1a0 8005588: 60da str r2, [r3, #12] CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 800558a: 695a ldr r2, [r3, #20] 800558c: f022 0201 bic.w r2, r2, #1 8005590: 615a str r2, [r3, #20] huart->gState = HAL_UART_STATE_READY; 8005592: 2320 movs r3, #32 8005594: f884 3039 strb.w r3, [r4, #57] ; 0x39 huart->RxState = HAL_UART_STATE_READY; 8005598: f884 303a strb.w r3, [r4, #58] ; 0x3a __HAL_UNLOCK(huart); 800559c: 2300 movs r3, #0 800559e: f884 3038 strb.w r3, [r4, #56] ; 0x38 80055a2: bdf8 pop {r3, r4, r5, r6, r7, pc} if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout)) 80055a4: f7fe fe80 bl 80042a8 80055a8: 1bc0 subs r0, r0, r7 80055aa: 4285 cmp r5, r0 80055ac: d2dd bcs.n 800556a 80055ae: e7e6 b.n 800557e 080055b0 : { 80055b0: b510 push {r4, lr} if(huart == NULL) 80055b2: 4604 mov r4, r0 80055b4: b340 cbz r0, 8005608 if(huart->gState == HAL_UART_STATE_RESET) 80055b6: f890 3039 ldrb.w r3, [r0, #57] ; 0x39 80055ba: f003 02ff and.w r2, r3, #255 ; 0xff 80055be: b91b cbnz r3, 80055c8 huart->Lock = HAL_UNLOCKED; 80055c0: f880 2038 strb.w r2, [r0, #56] ; 0x38 HAL_UART_MspInit(huart); 80055c4: f000 fcc4 bl 8005f50 huart->gState = HAL_UART_STATE_BUSY; 80055c8: 2324 movs r3, #36 ; 0x24 __HAL_UART_DISABLE(huart); 80055ca: 6822 ldr r2, [r4, #0] huart->gState = HAL_UART_STATE_BUSY; 80055cc: f884 3039 strb.w r3, [r4, #57] ; 0x39 __HAL_UART_DISABLE(huart); 80055d0: 68d3 ldr r3, [r2, #12] UART_SetConfig(huart); 80055d2: 4620 mov r0, r4 __HAL_UART_DISABLE(huart); 80055d4: f423 5300 bic.w r3, r3, #8192 ; 0x2000 80055d8: 60d3 str r3, [r2, #12] UART_SetConfig(huart); 80055da: f7ff ff23 bl 8005424 CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 80055de: 6823 ldr r3, [r4, #0] huart->ErrorCode = HAL_UART_ERROR_NONE; 80055e0: 2000 movs r0, #0 CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 80055e2: 691a ldr r2, [r3, #16] 80055e4: f422 4290 bic.w r2, r2, #18432 ; 0x4800 80055e8: 611a str r2, [r3, #16] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 80055ea: 695a ldr r2, [r3, #20] 80055ec: f022 022a bic.w r2, r2, #42 ; 0x2a 80055f0: 615a str r2, [r3, #20] __HAL_UART_ENABLE(huart); 80055f2: 68da ldr r2, [r3, #12] 80055f4: f442 5200 orr.w r2, r2, #8192 ; 0x2000 80055f8: 60da str r2, [r3, #12] huart->gState= HAL_UART_STATE_READY; 80055fa: 2320 movs r3, #32 huart->ErrorCode = HAL_UART_ERROR_NONE; 80055fc: 63e0 str r0, [r4, #60] ; 0x3c huart->gState= HAL_UART_STATE_READY; 80055fe: f884 3039 strb.w r3, [r4, #57] ; 0x39 huart->RxState= HAL_UART_STATE_READY; 8005602: f884 303a strb.w r3, [r4, #58] ; 0x3a return HAL_OK; 8005606: bd10 pop {r4, pc} return HAL_ERROR; 8005608: 2001 movs r0, #1 } 800560a: bd10 pop {r4, pc} 0800560c : { 800560c: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 8005610: 461f mov r7, r3 if(huart->gState == HAL_UART_STATE_READY) 8005612: f890 3039 ldrb.w r3, [r0, #57] ; 0x39 { 8005616: 4604 mov r4, r0 if(huart->gState == HAL_UART_STATE_READY) 8005618: 2b20 cmp r3, #32 { 800561a: 460d mov r5, r1 800561c: 4690 mov r8, r2 if(huart->gState == HAL_UART_STATE_READY) 800561e: d14e bne.n 80056be if((pData == NULL) || (Size == 0U)) 8005620: 2900 cmp r1, #0 8005622: d049 beq.n 80056b8 8005624: 2a00 cmp r2, #0 8005626: d047 beq.n 80056b8 __HAL_LOCK(huart); 8005628: f890 3038 ldrb.w r3, [r0, #56] ; 0x38 800562c: 2b01 cmp r3, #1 800562e: d046 beq.n 80056be 8005630: 2301 movs r3, #1 8005632: f880 3038 strb.w r3, [r0, #56] ; 0x38 huart->ErrorCode = HAL_UART_ERROR_NONE; 8005636: 2300 movs r3, #0 8005638: 63c3 str r3, [r0, #60] ; 0x3c huart->gState = HAL_UART_STATE_BUSY_TX; 800563a: 2321 movs r3, #33 ; 0x21 800563c: f880 3039 strb.w r3, [r0, #57] ; 0x39 tickstart = HAL_GetTick(); 8005640: f7fe fe32 bl 80042a8 8005644: 4606 mov r6, r0 huart->TxXferSize = Size; 8005646: f8a4 8024 strh.w r8, [r4, #36] ; 0x24 huart->TxXferCount = Size; 800564a: f8a4 8026 strh.w r8, [r4, #38] ; 0x26 while(huart->TxXferCount > 0U) 800564e: 8ce3 ldrh r3, [r4, #38] ; 0x26 8005650: b29b uxth r3, r3 8005652: b96b cbnz r3, 8005670 if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) 8005654: 463b mov r3, r7 8005656: 4632 mov r2, r6 8005658: 2140 movs r1, #64 ; 0x40 800565a: 4620 mov r0, r4 800565c: f7ff ff80 bl 8005560 8005660: b9a8 cbnz r0, 800568e huart->gState = HAL_UART_STATE_READY; 8005662: 2320 movs r3, #32 __HAL_UNLOCK(huart); 8005664: f884 0038 strb.w r0, [r4, #56] ; 0x38 huart->gState = HAL_UART_STATE_READY; 8005668: f884 3039 strb.w r3, [r4, #57] ; 0x39 return HAL_OK; 800566c: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} huart->TxXferCount--; 8005670: 8ce3 ldrh r3, [r4, #38] ; 0x26 if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) 8005672: 4632 mov r2, r6 huart->TxXferCount--; 8005674: 3b01 subs r3, #1 8005676: b29b uxth r3, r3 8005678: 84e3 strh r3, [r4, #38] ; 0x26 if(huart->Init.WordLength == UART_WORDLENGTH_9B) 800567a: 68a3 ldr r3, [r4, #8] if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) 800567c: 2180 movs r1, #128 ; 0x80 if(huart->Init.WordLength == UART_WORDLENGTH_9B) 800567e: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) 8005682: 4620 mov r0, r4 8005684: 463b mov r3, r7 if(huart->Init.WordLength == UART_WORDLENGTH_9B) 8005686: d10e bne.n 80056a6 if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) 8005688: f7ff ff6a bl 8005560 800568c: b110 cbz r0, 8005694 return HAL_TIMEOUT; 800568e: 2003 movs r0, #3 8005690: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} huart->Instance->DR = (*tmp & (uint16_t)0x01FF); 8005694: 882b ldrh r3, [r5, #0] 8005696: 6822 ldr r2, [r4, #0] 8005698: f3c3 0308 ubfx r3, r3, #0, #9 800569c: 6053 str r3, [r2, #4] if(huart->Init.Parity == UART_PARITY_NONE) 800569e: 6923 ldr r3, [r4, #16] 80056a0: b943 cbnz r3, 80056b4 pData +=2U; 80056a2: 3502 adds r5, #2 80056a4: e7d3 b.n 800564e if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) 80056a6: f7ff ff5b bl 8005560 80056aa: 2800 cmp r0, #0 80056ac: d1ef bne.n 800568e huart->Instance->DR = (*pData++ & (uint8_t)0xFF); 80056ae: 6823 ldr r3, [r4, #0] 80056b0: 782a ldrb r2, [r5, #0] 80056b2: 605a str r2, [r3, #4] 80056b4: 3501 adds r5, #1 80056b6: e7ca b.n 800564e return HAL_ERROR; 80056b8: 2001 movs r0, #1 80056ba: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} return HAL_BUSY; 80056be: 2002 movs r0, #2 } 80056c0: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 080056c4 : { 80056c4: 4613 mov r3, r2 if(huart->RxState == HAL_UART_STATE_READY) 80056c6: f890 203a ldrb.w r2, [r0, #58] ; 0x3a { 80056ca: b573 push {r0, r1, r4, r5, r6, lr} if(huart->RxState == HAL_UART_STATE_READY) 80056cc: 2a20 cmp r2, #32 { 80056ce: 4605 mov r5, r0 if(huart->RxState == HAL_UART_STATE_READY) 80056d0: d138 bne.n 8005744 if((pData == NULL) || (Size == 0U)) 80056d2: 2900 cmp r1, #0 80056d4: d034 beq.n 8005740 80056d6: 2b00 cmp r3, #0 80056d8: d032 beq.n 8005740 __HAL_LOCK(huart); 80056da: f890 2038 ldrb.w r2, [r0, #56] ; 0x38 80056de: 2a01 cmp r2, #1 80056e0: d030 beq.n 8005744 80056e2: 2201 movs r2, #1 huart->ErrorCode = HAL_UART_ERROR_NONE; 80056e4: 2400 movs r4, #0 __HAL_LOCK(huart); 80056e6: f880 2038 strb.w r2, [r0, #56] ; 0x38 huart->RxState = HAL_UART_STATE_BUSY_RX; 80056ea: 2222 movs r2, #34 ; 0x22 huart->pRxBuffPtr = pData; 80056ec: 6281 str r1, [r0, #40] ; 0x28 huart->RxXferSize = Size; 80056ee: 8583 strh r3, [r0, #44] ; 0x2c huart->ErrorCode = HAL_UART_ERROR_NONE; 80056f0: 63c4 str r4, [r0, #60] ; 0x3c huart->RxState = HAL_UART_STATE_BUSY_RX; 80056f2: f880 203a strb.w r2, [r0, #58] ; 0x3a huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; 80056f6: 6b40 ldr r0, [r0, #52] ; 0x34 80056f8: 4a13 ldr r2, [pc, #76] ; (8005748 ) HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t*)tmp, Size); 80056fa: 682e ldr r6, [r5, #0] huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; 80056fc: 6282 str r2, [r0, #40] ; 0x28 huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; 80056fe: 4a13 ldr r2, [pc, #76] ; (800574c ) huart->hdmarx->XferAbortCallback = NULL; 8005700: 6344 str r4, [r0, #52] ; 0x34 huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; 8005702: 62c2 str r2, [r0, #44] ; 0x2c huart->hdmarx->XferErrorCallback = UART_DMAError; 8005704: 4a12 ldr r2, [pc, #72] ; (8005750 ) 8005706: 6302 str r2, [r0, #48] ; 0x30 HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t*)tmp, Size); 8005708: 460a mov r2, r1 800570a: 1d31 adds r1, r6, #4 800570c: f7fe ffbc bl 8004688 return HAL_OK; 8005710: 4620 mov r0, r4 __HAL_UART_CLEAR_OREFLAG(huart); 8005712: 682b ldr r3, [r5, #0] 8005714: 9401 str r4, [sp, #4] 8005716: 681a ldr r2, [r3, #0] 8005718: 9201 str r2, [sp, #4] 800571a: 685a ldr r2, [r3, #4] __HAL_UNLOCK(huart); 800571c: f885 4038 strb.w r4, [r5, #56] ; 0x38 __HAL_UART_CLEAR_OREFLAG(huart); 8005720: 9201 str r2, [sp, #4] 8005722: 9a01 ldr r2, [sp, #4] SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8005724: 68da ldr r2, [r3, #12] 8005726: f442 7280 orr.w r2, r2, #256 ; 0x100 800572a: 60da str r2, [r3, #12] SET_BIT(huart->Instance->CR3, USART_CR3_EIE); 800572c: 695a ldr r2, [r3, #20] 800572e: f042 0201 orr.w r2, r2, #1 8005732: 615a str r2, [r3, #20] SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8005734: 695a ldr r2, [r3, #20] 8005736: f042 0240 orr.w r2, r2, #64 ; 0x40 800573a: 615a str r2, [r3, #20] } 800573c: b002 add sp, #8 800573e: bd70 pop {r4, r5, r6, pc} return HAL_ERROR; 8005740: 2001 movs r0, #1 8005742: e7fb b.n 800573c return HAL_BUSY; 8005744: 2002 movs r0, #2 8005746: e7f9 b.n 800573c 8005748: 08005757 .word 0x08005757 800574c: 0800580d .word 0x0800580d 8005750: 08005819 .word 0x08005819 08005754 : 8005754: 4770 bx lr 08005756 : { 8005756: b508 push {r3, lr} if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 8005758: 6803 ldr r3, [r0, #0] UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 800575a: 6a42 ldr r2, [r0, #36] ; 0x24 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 800575c: 681b ldr r3, [r3, #0] 800575e: f013 0320 ands.w r3, r3, #32 8005762: d110 bne.n 8005786 huart->RxXferCount = 0U; 8005764: 85d3 strh r3, [r2, #46] ; 0x2e CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8005766: 6813 ldr r3, [r2, #0] 8005768: 68d9 ldr r1, [r3, #12] 800576a: f421 7180 bic.w r1, r1, #256 ; 0x100 800576e: 60d9 str r1, [r3, #12] CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8005770: 6959 ldr r1, [r3, #20] 8005772: f021 0101 bic.w r1, r1, #1 8005776: 6159 str r1, [r3, #20] CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8005778: 6959 ldr r1, [r3, #20] 800577a: f021 0140 bic.w r1, r1, #64 ; 0x40 800577e: 6159 str r1, [r3, #20] huart->RxState = HAL_UART_STATE_READY; 8005780: 2320 movs r3, #32 8005782: f882 303a strb.w r3, [r2, #58] ; 0x3a HAL_UART_RxCpltCallback(huart); 8005786: 4610 mov r0, r2 8005788: f000 fcc6 bl 8006118 800578c: bd08 pop {r3, pc} 0800578e : if(huart->RxState == HAL_UART_STATE_BUSY_RX) 800578e: f890 303a ldrb.w r3, [r0, #58] ; 0x3a { 8005792: b510 push {r4, lr} if(huart->RxState == HAL_UART_STATE_BUSY_RX) 8005794: 2b22 cmp r3, #34 ; 0x22 8005796: d136 bne.n 8005806 if(huart->Init.WordLength == UART_WORDLENGTH_9B) 8005798: 6883 ldr r3, [r0, #8] 800579a: 6901 ldr r1, [r0, #16] 800579c: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 80057a0: 6802 ldr r2, [r0, #0] 80057a2: 6a83 ldr r3, [r0, #40] ; 0x28 80057a4: d123 bne.n 80057ee *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); 80057a6: 6852 ldr r2, [r2, #4] if(huart->Init.Parity == UART_PARITY_NONE) 80057a8: b9e9 cbnz r1, 80057e6 *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); 80057aa: f3c2 0208 ubfx r2, r2, #0, #9 80057ae: f823 2b02 strh.w r2, [r3], #2 huart->pRxBuffPtr += 1U; 80057b2: 6283 str r3, [r0, #40] ; 0x28 if(--huart->RxXferCount == 0U) 80057b4: 8dc4 ldrh r4, [r0, #46] ; 0x2e 80057b6: 3c01 subs r4, #1 80057b8: b2a4 uxth r4, r4 80057ba: 85c4 strh r4, [r0, #46] ; 0x2e 80057bc: b98c cbnz r4, 80057e2 __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); 80057be: 6803 ldr r3, [r0, #0] 80057c0: 68da ldr r2, [r3, #12] 80057c2: f022 0220 bic.w r2, r2, #32 80057c6: 60da str r2, [r3, #12] __HAL_UART_DISABLE_IT(huart, UART_IT_PE); 80057c8: 68da ldr r2, [r3, #12] 80057ca: f422 7280 bic.w r2, r2, #256 ; 0x100 80057ce: 60da str r2, [r3, #12] __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); 80057d0: 695a ldr r2, [r3, #20] 80057d2: f022 0201 bic.w r2, r2, #1 80057d6: 615a str r2, [r3, #20] huart->RxState = HAL_UART_STATE_READY; 80057d8: 2320 movs r3, #32 80057da: f880 303a strb.w r3, [r0, #58] ; 0x3a HAL_UART_RxCpltCallback(huart); 80057de: f000 fc9b bl 8006118 if(--huart->RxXferCount == 0U) 80057e2: 2000 movs r0, #0 } 80057e4: bd10 pop {r4, pc} *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF); 80057e6: b2d2 uxtb r2, r2 80057e8: f823 2b01 strh.w r2, [r3], #1 80057ec: e7e1 b.n 80057b2 if(huart->Init.Parity == UART_PARITY_NONE) 80057ee: b921 cbnz r1, 80057fa *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); 80057f0: 1c59 adds r1, r3, #1 80057f2: 6852 ldr r2, [r2, #4] 80057f4: 6281 str r1, [r0, #40] ; 0x28 *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); 80057f6: 701a strb r2, [r3, #0] 80057f8: e7dc b.n 80057b4 80057fa: 6852 ldr r2, [r2, #4] 80057fc: 1c59 adds r1, r3, #1 80057fe: 6281 str r1, [r0, #40] ; 0x28 8005800: f002 027f and.w r2, r2, #127 ; 0x7f 8005804: e7f7 b.n 80057f6 return HAL_BUSY; 8005806: 2002 movs r0, #2 8005808: bd10 pop {r4, pc} 0800580a : 800580a: 4770 bx lr 0800580c : { 800580c: b508 push {r3, lr} HAL_UART_RxHalfCpltCallback(huart); 800580e: 6a40 ldr r0, [r0, #36] ; 0x24 8005810: f7ff fffb bl 800580a 8005814: bd08 pop {r3, pc} 08005816 : 8005816: 4770 bx lr 08005818 : UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 8005818: 6a41 ldr r1, [r0, #36] ; 0x24 { 800581a: b508 push {r3, lr} dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT); 800581c: 680b ldr r3, [r1, #0] 800581e: 695a ldr r2, [r3, #20] if((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) 8005820: f891 0039 ldrb.w r0, [r1, #57] ; 0x39 8005824: 2821 cmp r0, #33 ; 0x21 8005826: d10a bne.n 800583e 8005828: 0612 lsls r2, r2, #24 800582a: d508 bpl.n 800583e huart->TxXferCount = 0U; 800582c: 2200 movs r2, #0 800582e: 84ca strh r2, [r1, #38] ; 0x26 CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); 8005830: 68da ldr r2, [r3, #12] 8005832: f022 02c0 bic.w r2, r2, #192 ; 0xc0 8005836: 60da str r2, [r3, #12] huart->gState = HAL_UART_STATE_READY; 8005838: 2220 movs r2, #32 800583a: f881 2039 strb.w r2, [r1, #57] ; 0x39 dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 800583e: 695b ldr r3, [r3, #20] if((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest) 8005840: f891 203a ldrb.w r2, [r1, #58] ; 0x3a 8005844: 2a22 cmp r2, #34 ; 0x22 8005846: d106 bne.n 8005856 8005848: 065b lsls r3, r3, #25 800584a: d504 bpl.n 8005856 huart->RxXferCount = 0U; 800584c: 2300 movs r3, #0 UART_EndRxTransfer(huart); 800584e: 4608 mov r0, r1 huart->RxXferCount = 0U; 8005850: 85cb strh r3, [r1, #46] ; 0x2e UART_EndRxTransfer(huart); 8005852: f7ff fdd9 bl 8005408 huart->ErrorCode |= HAL_UART_ERROR_DMA; 8005856: 6bcb ldr r3, [r1, #60] ; 0x3c HAL_UART_ErrorCallback(huart); 8005858: 4608 mov r0, r1 huart->ErrorCode |= HAL_UART_ERROR_DMA; 800585a: f043 0310 orr.w r3, r3, #16 800585e: 63cb str r3, [r1, #60] ; 0x3c HAL_UART_ErrorCallback(huart); 8005860: f7ff ffd9 bl 8005816 8005864: bd08 pop {r3, pc} ... 08005868 : uint32_t isrflags = READ_REG(huart->Instance->SR); 8005868: 6803 ldr r3, [r0, #0] { 800586a: b570 push {r4, r5, r6, lr} uint32_t isrflags = READ_REG(huart->Instance->SR); 800586c: 681a ldr r2, [r3, #0] { 800586e: 4604 mov r4, r0 if(errorflags == RESET) 8005870: 0716 lsls r6, r2, #28 uint32_t cr1its = READ_REG(huart->Instance->CR1); 8005872: 68d9 ldr r1, [r3, #12] uint32_t cr3its = READ_REG(huart->Instance->CR3); 8005874: 695d ldr r5, [r3, #20] if(errorflags == RESET) 8005876: d107 bne.n 8005888 if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 8005878: 0696 lsls r6, r2, #26 800587a: d55a bpl.n 8005932 800587c: 068d lsls r5, r1, #26 800587e: d558 bpl.n 8005932 } 8005880: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} UART_Receive_IT(huart); 8005884: f7ff bf83 b.w 800578e if((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) 8005888: f015 0501 ands.w r5, r5, #1 800588c: d102 bne.n 8005894 800588e: f411 7f90 tst.w r1, #288 ; 0x120 8005892: d04e beq.n 8005932 if(((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) 8005894: 07d3 lsls r3, r2, #31 8005896: d505 bpl.n 80058a4 8005898: 05ce lsls r6, r1, #23 huart->ErrorCode |= HAL_UART_ERROR_PE; 800589a: bf42 ittt mi 800589c: 6be3 ldrmi r3, [r4, #60] ; 0x3c 800589e: f043 0301 orrmi.w r3, r3, #1 80058a2: 63e3 strmi r3, [r4, #60] ; 0x3c if(((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 80058a4: 0750 lsls r0, r2, #29 80058a6: d504 bpl.n 80058b2 80058a8: b11d cbz r5, 80058b2 huart->ErrorCode |= HAL_UART_ERROR_NE; 80058aa: 6be3 ldr r3, [r4, #60] ; 0x3c 80058ac: f043 0302 orr.w r3, r3, #2 80058b0: 63e3 str r3, [r4, #60] ; 0x3c if(((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 80058b2: 0793 lsls r3, r2, #30 80058b4: d504 bpl.n 80058c0 80058b6: b11d cbz r5, 80058c0 huart->ErrorCode |= HAL_UART_ERROR_FE; 80058b8: 6be3 ldr r3, [r4, #60] ; 0x3c 80058ba: f043 0304 orr.w r3, r3, #4 80058be: 63e3 str r3, [r4, #60] ; 0x3c if(((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 80058c0: 0716 lsls r6, r2, #28 80058c2: d504 bpl.n 80058ce 80058c4: b11d cbz r5, 80058ce huart->ErrorCode |= HAL_UART_ERROR_ORE; 80058c6: 6be3 ldr r3, [r4, #60] ; 0x3c 80058c8: f043 0308 orr.w r3, r3, #8 80058cc: 63e3 str r3, [r4, #60] ; 0x3c if(huart->ErrorCode != HAL_UART_ERROR_NONE) 80058ce: 6be3 ldr r3, [r4, #60] ; 0x3c 80058d0: 2b00 cmp r3, #0 80058d2: d066 beq.n 80059a2 if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 80058d4: 0695 lsls r5, r2, #26 80058d6: d504 bpl.n 80058e2 80058d8: 0688 lsls r0, r1, #26 80058da: d502 bpl.n 80058e2 UART_Receive_IT(huart); 80058dc: 4620 mov r0, r4 80058de: f7ff ff56 bl 800578e dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 80058e2: 6823 ldr r3, [r4, #0] UART_EndRxTransfer(huart); 80058e4: 4620 mov r0, r4 dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 80058e6: 695d ldr r5, [r3, #20] if(((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest) 80058e8: 6be2 ldr r2, [r4, #60] ; 0x3c 80058ea: 0711 lsls r1, r2, #28 80058ec: d402 bmi.n 80058f4 80058ee: f015 0540 ands.w r5, r5, #64 ; 0x40 80058f2: d01a beq.n 800592a UART_EndRxTransfer(huart); 80058f4: f7ff fd88 bl 8005408 if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80058f8: 6823 ldr r3, [r4, #0] 80058fa: 695a ldr r2, [r3, #20] 80058fc: 0652 lsls r2, r2, #25 80058fe: d510 bpl.n 8005922 CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8005900: 695a ldr r2, [r3, #20] if(huart->hdmarx != NULL) 8005902: 6b60 ldr r0, [r4, #52] ; 0x34 CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8005904: f022 0240 bic.w r2, r2, #64 ; 0x40 8005908: 615a str r2, [r3, #20] if(huart->hdmarx != NULL) 800590a: b150 cbz r0, 8005922 huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; 800590c: 4b25 ldr r3, [pc, #148] ; (80059a4 ) 800590e: 6343 str r3, [r0, #52] ; 0x34 if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 8005910: f7fe fef8 bl 8004704 8005914: 2800 cmp r0, #0 8005916: d044 beq.n 80059a2 huart->hdmarx->XferAbortCallback(huart->hdmarx); 8005918: 6b60 ldr r0, [r4, #52] ; 0x34 } 800591a: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} huart->hdmarx->XferAbortCallback(huart->hdmarx); 800591e: 6b43 ldr r3, [r0, #52] ; 0x34 8005920: 4718 bx r3 HAL_UART_ErrorCallback(huart); 8005922: 4620 mov r0, r4 8005924: f7ff ff77 bl 8005816 8005928: bd70 pop {r4, r5, r6, pc} HAL_UART_ErrorCallback(huart); 800592a: f7ff ff74 bl 8005816 huart->ErrorCode = HAL_UART_ERROR_NONE; 800592e: 63e5 str r5, [r4, #60] ; 0x3c 8005930: bd70 pop {r4, r5, r6, pc} if(((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) 8005932: 0616 lsls r6, r2, #24 8005934: d527 bpl.n 8005986 8005936: 060d lsls r5, r1, #24 8005938: d525 bpl.n 8005986 if(huart->gState == HAL_UART_STATE_BUSY_TX) 800593a: f894 2039 ldrb.w r2, [r4, #57] ; 0x39 800593e: 2a21 cmp r2, #33 ; 0x21 8005940: d12f bne.n 80059a2 if(huart->Init.WordLength == UART_WORDLENGTH_9B) 8005942: 68a2 ldr r2, [r4, #8] 8005944: f5b2 5f80 cmp.w r2, #4096 ; 0x1000 8005948: 6a22 ldr r2, [r4, #32] 800594a: d117 bne.n 800597c huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); 800594c: 8811 ldrh r1, [r2, #0] 800594e: f3c1 0108 ubfx r1, r1, #0, #9 8005952: 6059 str r1, [r3, #4] if(huart->Init.Parity == UART_PARITY_NONE) 8005954: 6921 ldr r1, [r4, #16] 8005956: b979 cbnz r1, 8005978 huart->pTxBuffPtr += 2U; 8005958: 3202 adds r2, #2 huart->pTxBuffPtr += 1U; 800595a: 6222 str r2, [r4, #32] if(--huart->TxXferCount == 0U) 800595c: 8ce2 ldrh r2, [r4, #38] ; 0x26 800595e: 3a01 subs r2, #1 8005960: b292 uxth r2, r2 8005962: 84e2 strh r2, [r4, #38] ; 0x26 8005964: b9ea cbnz r2, 80059a2 __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); 8005966: 68da ldr r2, [r3, #12] 8005968: f022 0280 bic.w r2, r2, #128 ; 0x80 800596c: 60da str r2, [r3, #12] __HAL_UART_ENABLE_IT(huart, UART_IT_TC); 800596e: 68da ldr r2, [r3, #12] 8005970: f042 0240 orr.w r2, r2, #64 ; 0x40 8005974: 60da str r2, [r3, #12] 8005976: bd70 pop {r4, r5, r6, pc} huart->pTxBuffPtr += 1U; 8005978: 3201 adds r2, #1 800597a: e7ee b.n 800595a huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF); 800597c: 1c51 adds r1, r2, #1 800597e: 6221 str r1, [r4, #32] 8005980: 7812 ldrb r2, [r2, #0] 8005982: 605a str r2, [r3, #4] 8005984: e7ea b.n 800595c if(((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) 8005986: 0650 lsls r0, r2, #25 8005988: d50b bpl.n 80059a2 800598a: 064a lsls r2, r1, #25 800598c: d509 bpl.n 80059a2 __HAL_UART_DISABLE_IT(huart, UART_IT_TC); 800598e: 68da ldr r2, [r3, #12] HAL_UART_TxCpltCallback(huart); 8005990: 4620 mov r0, r4 __HAL_UART_DISABLE_IT(huart, UART_IT_TC); 8005992: f022 0240 bic.w r2, r2, #64 ; 0x40 8005996: 60da str r2, [r3, #12] huart->gState = HAL_UART_STATE_READY; 8005998: 2320 movs r3, #32 800599a: f884 3039 strb.w r3, [r4, #57] ; 0x39 HAL_UART_TxCpltCallback(huart); 800599e: f7ff fed9 bl 8005754 80059a2: bd70 pop {r4, r5, r6, pc} 80059a4: 080059a9 .word 0x080059a9 080059a8 : { 80059a8: b508 push {r3, lr} huart->RxXferCount = 0x00U; 80059aa: 2300 movs r3, #0 UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 80059ac: 6a40 ldr r0, [r0, #36] ; 0x24 huart->RxXferCount = 0x00U; 80059ae: 85c3 strh r3, [r0, #46] ; 0x2e huart->TxXferCount = 0x00U; 80059b0: 84c3 strh r3, [r0, #38] ; 0x26 HAL_UART_ErrorCallback(huart); 80059b2: f7ff ff30 bl 8005816 80059b6: bd08 pop {r3, pc} 080059b8 : __IO uint32_t ADCvalue[ADC_EA]; #if 1 // PYJ.2019.07.26_BEGIN -- void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { if(htim->Instance == TIM6){ 80059b8: 6802 ldr r2, [r0, #0] 80059ba: 4b06 ldr r3, [pc, #24] ; (80059d4 ) 80059bc: 429a cmp r2, r3 80059be: d107 bne.n 80059d0 UartTimerCnt++; 80059c0: 4a05 ldr r2, [pc, #20] ; (80059d8 ) 80059c2: 6813 ldr r3, [r2, #0] 80059c4: 3301 adds r3, #1 80059c6: 6013 str r3, [r2, #0] LedTimerCnt++; 80059c8: 4a04 ldr r2, [pc, #16] ; (80059dc ) 80059ca: 6813 ldr r3, [r2, #0] 80059cc: 3301 adds r3, #1 80059ce: 6013 str r3, [r2, #0] 80059d0: 4770 bx lr 80059d2: bf00 nop 80059d4: 40001000 .word 0x40001000 80059d8: 20000090 .word 0x20000090 80059dc: 2000008c .word 0x2000008c 080059e0 <_write>: } } #endif // PYJ.2019.07.26_END -- int _write (int file, uint8_t *ptr, uint16_t len) { 80059e0: b510 push {r4, lr} 80059e2: 4614 mov r4, r2 HAL_UART_Transmit (&huart1, ptr, len, 10); 80059e4: 230a movs r3, #10 80059e6: 4802 ldr r0, [pc, #8] ; (80059f0 <_write+0x10>) 80059e8: f7ff fe10 bl 800560c return len; } 80059ec: 4620 mov r0, r4 80059ee: bd10 pop {r4, pc} 80059f0: 200004d4 .word 0x200004d4 080059f4 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 80059f4: b510 push {r4, lr} 80059f6: b096 sub sp, #88 ; 0x58 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 80059f8: 2228 movs r2, #40 ; 0x28 80059fa: 2100 movs r1, #0 80059fc: a80c add r0, sp, #48 ; 0x30 80059fe: f000 fc0d bl 800621c RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8005a02: 2214 movs r2, #20 8005a04: 2100 movs r1, #0 8005a06: a801 add r0, sp, #4 8005a08: f000 fc08 bl 800621c RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 8005a0c: 2218 movs r2, #24 8005a0e: 2100 movs r1, #0 8005a10: eb0d 0002 add.w r0, sp, r2 8005a14: f000 fc02 bl 800621c /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; RCC_OscInitStruct.HSIState = RCC_HSI_ON; 8005a18: 2301 movs r3, #1 8005a1a: 9310 str r3, [sp, #64] ; 0x40 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 8005a1c: 2310 movs r3, #16 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; 8005a1e: 2402 movs r4, #2 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 8005a20: 9311 str r3, [sp, #68] ; 0x44 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2; RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL15; 8005a22: f44f 1350 mov.w r3, #3407872 ; 0x340000 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8005a26: a80c add r0, sp, #48 ; 0x30 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL15; 8005a28: 9315 str r3, [sp, #84] ; 0x54 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; 8005a2a: 940c str r4, [sp, #48] ; 0x30 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 8005a2c: 9413 str r4, [sp, #76] ; 0x4c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8005a2e: f7ff f8a9 bl 8004b84 { Error_Handler(); } /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8005a32: 230f movs r3, #15 |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 8005a34: f44f 6280 mov.w r2, #1024 ; 0x400 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8005a38: 9301 str r3, [sp, #4] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 8005a3a: 2300 movs r3, #0 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 8005a3c: 4621 mov r1, r4 8005a3e: a801 add r0, sp, #4 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 8005a40: 9303 str r3, [sp, #12] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 8005a42: 9204 str r2, [sp, #16] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 8005a44: 9305 str r3, [sp, #20] RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 8005a46: 9402 str r4, [sp, #8] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 8005a48: f7ff fa64 bl 8004f14 { Error_Handler(); } PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6; 8005a4c: f44f 4300 mov.w r3, #32768 ; 0x8000 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 8005a50: a806 add r0, sp, #24 PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; 8005a52: 9406 str r4, [sp, #24] PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6; 8005a54: 9308 str r3, [sp, #32] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 8005a56: f7ff fb2f bl 80050b8 { Error_Handler(); } } 8005a5a: b016 add sp, #88 ; 0x58 8005a5c: bd10 pop {r4, pc} ... 08005a60
: { 8005a60: b580 push {r7, lr} static void MX_GPIO_Init(void) { GPIO_InitTypeDef GPIO_InitStruct = {0}; /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOE_CLK_ENABLE(); 8005a62: 4db1 ldr r5, [pc, #708] ; (8005d28 ) { 8005a64: b08c sub sp, #48 ; 0x30 HAL_Init(); 8005a66: f7fe fc01 bl 800426c SystemClock_Config(); 8005a6a: f7ff ffc3 bl 80059f4 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8005a6e: 2210 movs r2, #16 8005a70: 2100 movs r1, #0 8005a72: a808 add r0, sp, #32 8005a74: f000 fbd2 bl 800621c __HAL_RCC_GPIOE_CLK_ENABLE(); 8005a78: 69ab ldr r3, [r5, #24] __HAL_RCC_GPIOB_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); __HAL_RCC_GPIOG_CLK_ENABLE(); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOE, ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin 8005a7a: 2200 movs r2, #0 __HAL_RCC_GPIOE_CLK_ENABLE(); 8005a7c: f043 0340 orr.w r3, r3, #64 ; 0x40 8005a80: 61ab str r3, [r5, #24] 8005a82: 69ab ldr r3, [r5, #24] HAL_GPIO_WritePin(GPIOE, ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin 8005a84: 217f movs r1, #127 ; 0x7f __HAL_RCC_GPIOE_CLK_ENABLE(); 8005a86: f003 0340 and.w r3, r3, #64 ; 0x40 8005a8a: 9301 str r3, [sp, #4] 8005a8c: 9b01 ldr r3, [sp, #4] __HAL_RCC_GPIOC_CLK_ENABLE(); 8005a8e: 69ab ldr r3, [r5, #24] HAL_GPIO_WritePin(GPIOE, ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin 8005a90: 48a6 ldr r0, [pc, #664] ; (8005d2c ) __HAL_RCC_GPIOC_CLK_ENABLE(); 8005a92: f043 0310 orr.w r3, r3, #16 8005a96: 61ab str r3, [r5, #24] 8005a98: 69ab ldr r3, [r5, #24] /*Configure GPIO pins : ATT_EN_1_8G_DL1_Pin ATT_EN_1_8G_DL2_Pin ATT_EN_1_8G_UL1_Pin ATT_EN_1_8G_UL2_Pin ATT_EN_1_8G_UL3_Pin PATH_EN_2_1G_DL_Pin PATH_EN_2_1G_UL_Pin */ GPIO_InitStruct.Pin = ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin |ATT_EN_1_8G_UL3_Pin|PATH_EN_2_1G_DL_Pin|PATH_EN_2_1G_UL_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; 8005a9a: 2400 movs r4, #0 __HAL_RCC_GPIOC_CLK_ENABLE(); 8005a9c: f003 0310 and.w r3, r3, #16 8005aa0: 9302 str r3, [sp, #8] 8005aa2: 9b02 ldr r3, [sp, #8] __HAL_RCC_GPIOF_CLK_ENABLE(); 8005aa4: 69ab ldr r3, [r5, #24] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8005aa6: 2601 movs r6, #1 __HAL_RCC_GPIOF_CLK_ENABLE(); 8005aa8: f043 0380 orr.w r3, r3, #128 ; 0x80 8005aac: 61ab str r3, [r5, #24] 8005aae: 69ab ldr r3, [r5, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8005ab0: 2702 movs r7, #2 __HAL_RCC_GPIOF_CLK_ENABLE(); 8005ab2: f003 0380 and.w r3, r3, #128 ; 0x80 8005ab6: 9303 str r3, [sp, #12] 8005ab8: 9b03 ldr r3, [sp, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 8005aba: 69ab ldr r3, [r5, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); /*Configure GPIO pins : PLL_LD_1_8G_DL_Pin PLL_LD_1_8G_UL_Pin */ GPIO_InitStruct.Pin = PLL_LD_1_8G_DL_Pin|PLL_LD_1_8G_UL_Pin; 8005abc: f04f 080c mov.w r8, #12 __HAL_RCC_GPIOA_CLK_ENABLE(); 8005ac0: f043 0304 orr.w r3, r3, #4 8005ac4: 61ab str r3, [r5, #24] 8005ac6: 69ab ldr r3, [r5, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); /*Configure GPIO pin : PATH_EN_3_5G_H_Pin */ GPIO_InitStruct.Pin = PATH_EN_3_5G_H_Pin; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8005ac8: f04f 0903 mov.w r9, #3 __HAL_RCC_GPIOA_CLK_ENABLE(); 8005acc: f003 0304 and.w r3, r3, #4 8005ad0: 9304 str r3, [sp, #16] 8005ad2: 9b04 ldr r3, [sp, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 8005ad4: 69ab ldr r3, [r5, #24] hadc1.Init.NbrOfConversion = 14; 8005ad6: f04f 0a0e mov.w sl, #14 __HAL_RCC_GPIOB_CLK_ENABLE(); 8005ada: f043 0308 orr.w r3, r3, #8 8005ade: 61ab str r3, [r5, #24] 8005ae0: 69ab ldr r3, [r5, #24] 8005ae2: f003 0308 and.w r3, r3, #8 8005ae6: 9305 str r3, [sp, #20] 8005ae8: 9b05 ldr r3, [sp, #20] __HAL_RCC_GPIOD_CLK_ENABLE(); 8005aea: 69ab ldr r3, [r5, #24] 8005aec: f043 0320 orr.w r3, r3, #32 8005af0: 61ab str r3, [r5, #24] 8005af2: 69ab ldr r3, [r5, #24] 8005af4: f003 0320 and.w r3, r3, #32 8005af8: 9306 str r3, [sp, #24] 8005afa: 9b06 ldr r3, [sp, #24] __HAL_RCC_GPIOG_CLK_ENABLE(); 8005afc: 69ab ldr r3, [r5, #24] 8005afe: f443 7380 orr.w r3, r3, #256 ; 0x100 8005b02: 61ab str r3, [r5, #24] 8005b04: 69ab ldr r3, [r5, #24] 8005b06: f403 7380 and.w r3, r3, #256 ; 0x100 8005b0a: 9307 str r3, [sp, #28] 8005b0c: 9b07 ldr r3, [sp, #28] HAL_GPIO_WritePin(GPIOE, ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin 8005b0e: f7ff f82f bl 8004b70 HAL_GPIO_WritePin(GPIOC, ATT_EN_1_8G_UL4_Pin|PATH_EN_1_8G_DL_Pin|PATH_EN_1_8G_UL_Pin|PLL_EN_3_5G_L_Pin 8005b12: 2200 movs r2, #0 8005b14: f24e 01c0 movw r1, #57536 ; 0xe0c0 8005b18: 4885 ldr r0, [pc, #532] ; (8005d30 ) 8005b1a: f7ff f829 bl 8004b70 HAL_GPIO_WritePin(GPIOF, PLL_EN_1_8G_DL_Pin|PLL_EN_1_8G_UL_Pin|ATT_EN_2_1G_DL1_Pin|ATT_EN_2_1G_DL2_Pin 8005b1e: 2200 movs r2, #0 8005b20: f240 31f3 movw r1, #1011 ; 0x3f3 8005b24: 4883 ldr r0, [pc, #524] ; (8005d34 ) 8005b26: f7ff f823 bl 8004b70 HAL_GPIO_WritePin(GPIOD, PLL_DATA_Pin|PLL_CLK_Pin|ATT_DATA_Pin|ATT_CLK_Pin 8005b2a: 2200 movs r2, #0 8005b2c: f648 71ff movw r1, #36863 ; 0x8fff 8005b30: 4881 ldr r0, [pc, #516] ; (8005d38 ) 8005b32: f7ff f81d bl 8004b70 HAL_GPIO_WritePin(GPIOG, DA_SYNC_Pin|DA_SCLK_Pin|DA_DIN_Pin|_T_SYNC_UL_Pin 8005b36: 2200 movs r2, #0 8005b38: f647 51fc movw r1, #32252 ; 0x7dfc 8005b3c: 487f ldr r0, [pc, #508] ; (8005d3c ) 8005b3e: f7ff f817 bl 8004b70 HAL_GPIO_WritePin(GPIOB, PLL_EN_2_1G_DL_Pin|PLL_EN_2_1G_UL_Pin, GPIO_PIN_RESET); 8005b42: 2200 movs r2, #0 8005b44: 2118 movs r1, #24 8005b46: 487e ldr r0, [pc, #504] ; (8005d40 ) 8005b48: f7ff f812 bl 8004b70 GPIO_InitStruct.Pin = ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin 8005b4c: 237f movs r3, #127 ; 0x7f HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 8005b4e: a908 add r1, sp, #32 8005b50: 4876 ldr r0, [pc, #472] ; (8005d2c ) GPIO_InitStruct.Pin = ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin 8005b52: 9308 str r3, [sp, #32] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8005b54: 9609 str r6, [sp, #36] ; 0x24 GPIO_InitStruct.Pull = GPIO_NOPULL; 8005b56: 940a str r4, [sp, #40] ; 0x28 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8005b58: 970b str r7, [sp, #44] ; 0x2c HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 8005b5a: f7fe ff1d bl 8004998 GPIO_InitStruct.Pin = ATT_EN_1_8G_UL4_Pin|PATH_EN_1_8G_DL_Pin|PATH_EN_1_8G_UL_Pin|PLL_EN_3_5G_L_Pin 8005b5e: f24e 03c0 movw r3, #57536 ; 0xe0c0 HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8005b62: a908 add r1, sp, #32 8005b64: 4872 ldr r0, [pc, #456] ; (8005d30 ) GPIO_InitStruct.Pin = ATT_EN_1_8G_UL4_Pin|PATH_EN_1_8G_DL_Pin|PATH_EN_1_8G_UL_Pin|PLL_EN_3_5G_L_Pin 8005b66: 9308 str r3, [sp, #32] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8005b68: 9609 str r6, [sp, #36] ; 0x24 GPIO_InitStruct.Pull = GPIO_NOPULL; 8005b6a: 940a str r4, [sp, #40] ; 0x28 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8005b6c: 970b str r7, [sp, #44] ; 0x2c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8005b6e: f7fe ff13 bl 8004998 GPIO_InitStruct.Pin = PLL_EN_1_8G_DL_Pin|PLL_EN_1_8G_UL_Pin|ATT_EN_2_1G_DL1_Pin|ATT_EN_2_1G_DL2_Pin 8005b72: f240 33f3 movw r3, #1011 ; 0x3f3 HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); 8005b76: a908 add r1, sp, #32 8005b78: 486e ldr r0, [pc, #440] ; (8005d34 ) GPIO_InitStruct.Pin = PLL_EN_1_8G_DL_Pin|PLL_EN_1_8G_UL_Pin|ATT_EN_2_1G_DL1_Pin|ATT_EN_2_1G_DL2_Pin 8005b7a: 9308 str r3, [sp, #32] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8005b7c: 9609 str r6, [sp, #36] ; 0x24 GPIO_InitStruct.Pull = GPIO_NOPULL; 8005b7e: 940a str r4, [sp, #40] ; 0x28 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8005b80: 970b str r7, [sp, #44] ; 0x2c HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); 8005b82: f7fe ff09 bl 8004998 HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); 8005b86: a908 add r1, sp, #32 8005b88: 486a ldr r0, [pc, #424] ; (8005d34 ) GPIO_InitStruct.Pin = PLL_LD_1_8G_DL_Pin|PLL_LD_1_8G_UL_Pin; 8005b8a: f8cd 8020 str.w r8, [sp, #32] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8005b8e: 9409 str r4, [sp, #36] ; 0x24 GPIO_InitStruct.Pull = GPIO_NOPULL; 8005b90: 940a str r4, [sp, #40] ; 0x28 HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); 8005b92: f7fe ff01 bl 8004998 GPIO_InitStruct.Pin = PLL_DATA_Pin|PLL_CLK_Pin|ATT_DATA_Pin|ATT_CLK_Pin 8005b96: f648 73ff movw r3, #36863 ; 0x8fff HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8005b9a: a908 add r1, sp, #32 8005b9c: 4866 ldr r0, [pc, #408] ; (8005d38 ) GPIO_InitStruct.Pin = PLL_DATA_Pin|PLL_CLK_Pin|ATT_DATA_Pin|ATT_CLK_Pin 8005b9e: 9308 str r3, [sp, #32] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8005ba0: 9609 str r6, [sp, #36] ; 0x24 GPIO_InitStruct.Pull = GPIO_NOPULL; 8005ba2: 940a str r4, [sp, #40] ; 0x28 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8005ba4: 970b str r7, [sp, #44] ; 0x2c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8005ba6: f7fe fef7 bl 8004998 GPIO_InitStruct.Pin = ALARM_DC_Pin|ALARM_AC_Pin; 8005baa: f44f 5340 mov.w r3, #12288 ; 0x3000 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8005bae: a908 add r1, sp, #32 8005bb0: 4861 ldr r0, [pc, #388] ; (8005d38 ) GPIO_InitStruct.Pin = ALARM_DC_Pin|ALARM_AC_Pin; 8005bb2: 9308 str r3, [sp, #32] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8005bb4: 9409 str r4, [sp, #36] ; 0x24 GPIO_InitStruct.Pull = GPIO_NOPULL; 8005bb6: 940a str r4, [sp, #40] ; 0x28 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8005bb8: f7fe feee bl 8004998 GPIO_InitStruct.Pin = DA_SYNC_Pin|DA_SCLK_Pin|DA_DIN_Pin|_T_SYNC_UL_Pin 8005bbc: f647 53fc movw r3, #32252 ; 0x7dfc HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); 8005bc0: a908 add r1, sp, #32 8005bc2: 485e ldr r0, [pc, #376] ; (8005d3c ) GPIO_InitStruct.Pin = DA_SYNC_Pin|DA_SCLK_Pin|DA_DIN_Pin|_T_SYNC_UL_Pin 8005bc4: 9308 str r3, [sp, #32] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8005bc6: 9609 str r6, [sp, #36] ; 0x24 GPIO_InitStruct.Pull = GPIO_NOPULL; 8005bc8: 940a str r4, [sp, #40] ; 0x28 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8005bca: 970b str r7, [sp, #44] ; 0x2c HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); 8005bcc: f7fe fee4 bl 8004998 GPIO_InitStruct.Pin = PLL_LD_3_5G_L_Pin|PLL_LD_3_5G_H_Pin; 8005bd0: f44f 7340 mov.w r3, #768 ; 0x300 HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8005bd4: a908 add r1, sp, #32 8005bd6: 4856 ldr r0, [pc, #344] ; (8005d30 ) GPIO_InitStruct.Pin = PLL_LD_3_5G_L_Pin|PLL_LD_3_5G_H_Pin; 8005bd8: 9308 str r3, [sp, #32] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8005bda: 9409 str r4, [sp, #36] ; 0x24 GPIO_InitStruct.Pull = GPIO_NOPULL; 8005bdc: 940a str r4, [sp, #40] ; 0x28 HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8005bde: f7fe fedb bl 8004998 GPIO_InitStruct.Pin = PATH_EN_3_5G_H_Pin; 8005be2: f44f 7300 mov.w r3, #512 ; 0x200 HAL_GPIO_Init(PATH_EN_3_5G_H_GPIO_Port, &GPIO_InitStruct); 8005be6: a908 add r1, sp, #32 8005be8: 4854 ldr r0, [pc, #336] ; (8005d3c ) GPIO_InitStruct.Pin = PATH_EN_3_5G_H_Pin; 8005bea: 9308 str r3, [sp, #32] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8005bec: f8cd 9024 str.w r9, [sp, #36] ; 0x24 HAL_GPIO_Init(PATH_EN_3_5G_H_GPIO_Port, &GPIO_InitStruct); 8005bf0: f7fe fed2 bl 8004998 /*Configure GPIO pins : PLL_EN_2_1G_DL_Pin PLL_EN_2_1G_UL_Pin */ GPIO_InitStruct.Pin = PLL_EN_2_1G_DL_Pin|PLL_EN_2_1G_UL_Pin; 8005bf4: 2318 movs r3, #24 GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8005bf6: a908 add r1, sp, #32 8005bf8: 4851 ldr r0, [pc, #324] ; (8005d40 ) GPIO_InitStruct.Pin = PLL_EN_2_1G_DL_Pin|PLL_EN_2_1G_UL_Pin; 8005bfa: 9308 str r3, [sp, #32] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8005bfc: 9609 str r6, [sp, #36] ; 0x24 GPIO_InitStruct.Pull = GPIO_NOPULL; 8005bfe: 940a str r4, [sp, #40] ; 0x28 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8005c00: 970b str r7, [sp, #44] ; 0x2c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8005c02: f7fe fec9 bl 8004998 /*Configure GPIO pins : PLL_LD_2_1G_DL_Pin PLL_LD_2_1G_UL_Pin */ GPIO_InitStruct.Pin = PLL_LD_2_1G_DL_Pin|PLL_LD_2_1G_UL_Pin; 8005c06: 2360 movs r3, #96 ; 0x60 GPIO_InitStruct.Mode = GPIO_MODE_INPUT; GPIO_InitStruct.Pull = GPIO_NOPULL; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8005c08: a908 add r1, sp, #32 8005c0a: 484d ldr r0, [pc, #308] ; (8005d40 ) GPIO_InitStruct.Pin = PLL_LD_2_1G_DL_Pin|PLL_LD_2_1G_UL_Pin; 8005c0c: 9308 str r3, [sp, #32] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8005c0e: 9409 str r4, [sp, #36] ; 0x24 GPIO_InitStruct.Pull = GPIO_NOPULL; 8005c10: 940a str r4, [sp, #40] ; 0x28 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8005c12: f7fe fec1 bl 8004998 __HAL_RCC_DMA1_CLK_ENABLE(); 8005c16: 696b ldr r3, [r5, #20] HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0); 8005c18: 4622 mov r2, r4 __HAL_RCC_DMA1_CLK_ENABLE(); 8005c1a: 4333 orrs r3, r6 8005c1c: 616b str r3, [r5, #20] 8005c1e: 696b ldr r3, [r5, #20] HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0); 8005c20: 4621 mov r1, r4 __HAL_RCC_DMA1_CLK_ENABLE(); 8005c22: 4033 ands r3, r6 8005c24: 9300 str r3, [sp, #0] HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0); 8005c26: 200b movs r0, #11 __HAL_RCC_DMA1_CLK_ENABLE(); 8005c28: 9b00 ldr r3, [sp, #0] HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0); 8005c2a: f7fe fc97 bl 800455c HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn); 8005c2e: 200b movs r0, #11 hadc1.Instance = ADC1; 8005c30: 4d44 ldr r5, [pc, #272] ; (8005d44 ) HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn); 8005c32: f7fe fcc7 bl 80045c4 hadc1.Instance = ADC1; 8005c36: 4b44 ldr r3, [pc, #272] ; (8005d48 ) if (HAL_ADC_Init(&hadc1) != HAL_OK) 8005c38: 4628 mov r0, r5 hadc1.Instance = ADC1; 8005c3a: 602b str r3, [r5, #0] hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; 8005c3c: f44f 7380 mov.w r3, #256 ; 0x100 8005c40: 60ab str r3, [r5, #8] hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; 8005c42: f44f 2360 mov.w r3, #917504 ; 0xe0000 hadc1.Init.ContinuousConvMode = ENABLE; 8005c46: 60ee str r6, [r5, #12] hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; 8005c48: 61eb str r3, [r5, #28] hadc1.Init.DiscontinuousConvMode = DISABLE; 8005c4a: 616c str r4, [r5, #20] hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; 8005c4c: 606c str r4, [r5, #4] hadc1.Init.NbrOfConversion = 14; 8005c4e: f8c5 a010 str.w sl, [r5, #16] ADC_ChannelConfTypeDef sConfig = {0}; 8005c52: 9408 str r4, [sp, #32] 8005c54: 9409 str r4, [sp, #36] ; 0x24 8005c56: 940a str r4, [sp, #40] ; 0x28 if (HAL_ADC_Init(&hadc1) != HAL_OK) 8005c58: f7fe fbe4 bl 8004424 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8005c5c: a908 add r1, sp, #32 8005c5e: 4628 mov r0, r5 sConfig.Rank = ADC_REGULAR_RANK_1; 8005c60: 9609 str r6, [sp, #36] ; 0x24 sConfig.Channel = ADC_CHANNEL_0; 8005c62: 9408 str r4, [sp, #32] sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5; 8005c64: 940a str r4, [sp, #40] ; 0x28 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8005c66: f7fe fb37 bl 80042d8 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8005c6a: a908 add r1, sp, #32 8005c6c: 4628 mov r0, r5 sConfig.Rank = ADC_REGULAR_RANK_2; 8005c6e: 9709 str r7, [sp, #36] ; 0x24 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8005c70: f7fe fb32 bl 80042d8 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8005c74: a908 add r1, sp, #32 8005c76: 4628 mov r0, r5 sConfig.Rank = ADC_REGULAR_RANK_3; 8005c78: f8cd 9024 str.w r9, [sp, #36] ; 0x24 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8005c7c: f7fe fb2c bl 80042d8 sConfig.Rank = ADC_REGULAR_RANK_4; 8005c80: 2304 movs r3, #4 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8005c82: a908 add r1, sp, #32 8005c84: 4628 mov r0, r5 sConfig.Rank = ADC_REGULAR_RANK_4; 8005c86: 9309 str r3, [sp, #36] ; 0x24 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8005c88: f7fe fb26 bl 80042d8 sConfig.Rank = ADC_REGULAR_RANK_5; 8005c8c: 2305 movs r3, #5 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8005c8e: a908 add r1, sp, #32 8005c90: 4628 mov r0, r5 sConfig.Rank = ADC_REGULAR_RANK_5; 8005c92: 9309 str r3, [sp, #36] ; 0x24 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8005c94: f7fe fb20 bl 80042d8 sConfig.Rank = ADC_REGULAR_RANK_6; 8005c98: 2306 movs r3, #6 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8005c9a: a908 add r1, sp, #32 8005c9c: 4628 mov r0, r5 sConfig.Rank = ADC_REGULAR_RANK_6; 8005c9e: 9309 str r3, [sp, #36] ; 0x24 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8005ca0: f7fe fb1a bl 80042d8 sConfig.Rank = ADC_REGULAR_RANK_7; 8005ca4: 2307 movs r3, #7 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8005ca6: a908 add r1, sp, #32 8005ca8: 4628 mov r0, r5 sConfig.Rank = ADC_REGULAR_RANK_7; 8005caa: 9309 str r3, [sp, #36] ; 0x24 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8005cac: f7fe fb14 bl 80042d8 sConfig.Rank = ADC_REGULAR_RANK_8; 8005cb0: 2308 movs r3, #8 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8005cb2: a908 add r1, sp, #32 8005cb4: 4628 mov r0, r5 sConfig.Rank = ADC_REGULAR_RANK_8; 8005cb6: 9309 str r3, [sp, #36] ; 0x24 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8005cb8: f7fe fb0e bl 80042d8 sConfig.Rank = ADC_REGULAR_RANK_9; 8005cbc: 2309 movs r3, #9 sConfig.Rank = ADC_REGULAR_RANK_10; 8005cbe: 260a movs r6, #10 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8005cc0: a908 add r1, sp, #32 8005cc2: 4628 mov r0, r5 sConfig.Rank = ADC_REGULAR_RANK_9; 8005cc4: 9309 str r3, [sp, #36] ; 0x24 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8005cc6: f7fe fb07 bl 80042d8 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8005cca: a908 add r1, sp, #32 8005ccc: 4628 mov r0, r5 sConfig.Rank = ADC_REGULAR_RANK_10; 8005cce: 9609 str r6, [sp, #36] ; 0x24 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8005cd0: f7fe fb02 bl 80042d8 sConfig.Rank = ADC_REGULAR_RANK_11; 8005cd4: 230b movs r3, #11 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8005cd6: a908 add r1, sp, #32 8005cd8: 4628 mov r0, r5 sConfig.Rank = ADC_REGULAR_RANK_11; 8005cda: 9309 str r3, [sp, #36] ; 0x24 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8005cdc: f7fe fafc bl 80042d8 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8005ce0: a908 add r1, sp, #32 8005ce2: 4628 mov r0, r5 sConfig.Rank = ADC_REGULAR_RANK_12; 8005ce4: f8cd 8024 str.w r8, [sp, #36] ; 0x24 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8005ce8: f7fe faf6 bl 80042d8 sConfig.Rank = ADC_REGULAR_RANK_13; 8005cec: 230d movs r3, #13 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8005cee: a908 add r1, sp, #32 8005cf0: 4628 mov r0, r5 sConfig.Rank = ADC_REGULAR_RANK_13; 8005cf2: 9309 str r3, [sp, #36] ; 0x24 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8005cf4: f7fe faf0 bl 80042d8 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8005cf8: a908 add r1, sp, #32 8005cfa: 4628 mov r0, r5 sConfig.Rank = ADC_REGULAR_RANK_14; 8005cfc: f8cd a024 str.w sl, [sp, #36] ; 0x24 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8005d00: f7fe faea bl 80042d8 huart1.Init.BaudRate = 115200; 8005d04: f44f 33e1 mov.w r3, #115200 ; 0x1c200 huart1.Instance = USART1; 8005d08: 4810 ldr r0, [pc, #64] ; (8005d4c ) huart1.Init.BaudRate = 115200; 8005d0a: 4a11 ldr r2, [pc, #68] ; (8005d50 ) huart1.Init.WordLength = UART_WORDLENGTH_8B; 8005d0c: 6084 str r4, [r0, #8] huart1.Init.BaudRate = 115200; 8005d0e: e880 000c stmia.w r0, {r2, r3} huart1.Init.StopBits = UART_STOPBITS_1; 8005d12: 60c4 str r4, [r0, #12] huart1.Init.Parity = UART_PARITY_NONE; 8005d14: 6104 str r4, [r0, #16] huart1.Init.Mode = UART_MODE_TX_RX; 8005d16: f8c0 8014 str.w r8, [r0, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8005d1a: 6184 str r4, [r0, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 8005d1c: 61c4 str r4, [r0, #28] if (HAL_UART_Init(&huart1) != HAL_OK) 8005d1e: f7ff fc47 bl 80055b0 htim6.Init.Prescaler = 6000-1; 8005d22: f241 736f movw r3, #5999 ; 0x176f 8005d26: e015 b.n 8005d54 8005d28: 40021000 .word 0x40021000 8005d2c: 40011800 .word 0x40011800 8005d30: 40011000 .word 0x40011000 8005d34: 40011c00 .word 0x40011c00 8005d38: 40011400 .word 0x40011400 8005d3c: 40012000 .word 0x40012000 8005d40: 40010c00 .word 0x40010c00 8005d44: 200004a4 .word 0x200004a4 8005d48: 40012400 .word 0x40012400 8005d4c: 200004d4 .word 0x200004d4 8005d50: 40013800 .word 0x40013800 htim6.Instance = TIM6; 8005d54: 4d22 ldr r5, [pc, #136] ; (8005de0 ) htim6.Init.Prescaler = 6000-1; 8005d56: 4923 ldr r1, [pc, #140] ; (8005de4 ) if (HAL_TIM_Base_Init(&htim6) != HAL_OK) 8005d58: 4628 mov r0, r5 htim6.Init.Prescaler = 6000-1; 8005d5a: e885 000a stmia.w r5, {r1, r3} htim6.Init.Period = 10; 8005d5e: 60ee str r6, [r5, #12] htim6.Init.CounterMode = TIM_COUNTERMODE_UP; 8005d60: 60ac str r4, [r5, #8] htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8005d62: 61ac str r4, [r5, #24] TIM_MasterConfigTypeDef sMasterConfig = {0}; 8005d64: 9408 str r4, [sp, #32] 8005d66: 9409 str r4, [sp, #36] ; 0x24 if (HAL_TIM_Base_Init(&htim6) != HAL_OK) 8005d68: f7ff fb10 bl 800538c if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK) 8005d6c: a908 add r1, sp, #32 8005d6e: 4628 mov r0, r5 sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8005d70: 9408 str r4, [sp, #32] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8005d72: 9409 str r4, [sp, #36] ; 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK) 8005d74: f7ff fb24 bl 80053c0 HAL_NVIC_SetPriority(USART1_IRQn, 0, 0); 8005d78: 4622 mov r2, r4 8005d7a: 4621 mov r1, r4 8005d7c: 2025 movs r0, #37 ; 0x25 8005d7e: f7fe fbed bl 800455c HAL_NVIC_EnableIRQ(USART1_IRQn); 8005d82: 2025 movs r0, #37 ; 0x25 8005d84: f7fe fc1e bl 80045c4 HAL_NVIC_SetPriority(TIM6_IRQn, 0, 0); 8005d88: 4622 mov r2, r4 8005d8a: 4621 mov r1, r4 8005d8c: 2036 movs r0, #54 ; 0x36 8005d8e: f7fe fbe5 bl 800455c HAL_NVIC_EnableIRQ(TIM6_IRQn); 8005d92: 2036 movs r0, #54 ; 0x36 8005d94: f7fe fc16 bl 80045c4 setbuf(stdout, NULL); 8005d98: 4b13 ldr r3, [pc, #76] ; (8005de8 ) 8005d9a: 4621 mov r1, r4 8005d9c: 681b ldr r3, [r3, #0] if(LedTimerCnt > 500){HAL_GPIO_TogglePin(BOOT_LED_GPIO_Port,GPIO_PIN_14);LedTimerCnt = 0;} 8005d9e: 4e13 ldr r6, [pc, #76] ; (8005dec ) setbuf(stdout, NULL); 8005da0: 6898 ldr r0, [r3, #8] 8005da2: f000 fabf bl 8006324 printf("UART Start \r\n"); 8005da6: 4812 ldr r0, [pc, #72] ; (8005df0 ) 8005da8: f000 fab4 bl 8006314 while (TerminalQueue.data > 0 && UartTimerCnt > 100) GetDataFromUartQueue(&hTerminal); 8005dac: 4d11 ldr r5, [pc, #68] ; (8005df4 ) if(LedTimerCnt > 500){HAL_GPIO_TogglePin(BOOT_LED_GPIO_Port,GPIO_PIN_14);LedTimerCnt = 0;} 8005dae: 4c12 ldr r4, [pc, #72] ; (8005df8 ) 8005db0: 6823 ldr r3, [r4, #0] 8005db2: f5b3 7ffa cmp.w r3, #500 ; 0x1f4 8005db6: d906 bls.n 8005dc6 8005db8: f44f 4180 mov.w r1, #16384 ; 0x4000 8005dbc: 4630 mov r0, r6 8005dbe: f7fe fedc bl 8004b7a 8005dc2: 2300 movs r3, #0 8005dc4: 6023 str r3, [r4, #0] while (TerminalQueue.data > 0 && UartTimerCnt > 100) GetDataFromUartQueue(&hTerminal); 8005dc6: 4c0d ldr r4, [pc, #52] ; (8005dfc ) 8005dc8: 4f0d ldr r7, [pc, #52] ; (8005e00 ) 8005dca: 68a3 ldr r3, [r4, #8] 8005dcc: 2b00 cmp r3, #0 8005dce: ddee ble.n 8005dae 8005dd0: 682b ldr r3, [r5, #0] 8005dd2: 2b64 cmp r3, #100 ; 0x64 8005dd4: d9eb bls.n 8005dae 8005dd6: 4638 mov r0, r7 8005dd8: f000 f96c bl 80060b4 8005ddc: e7f5 b.n 8005dca 8005dde: bf00 nop 8005de0: 20000558 .word 0x20000558 8005de4: 40001000 .word 0x40001000 8005de8: 2000000c .word 0x2000000c 8005dec: 40012000 .word 0x40012000 8005df0: 080072a0 .word 0x080072a0 8005df4: 20000090 .word 0x20000090 8005df8: 2000008c .word 0x2000008c 8005dfc: 200005d0 .word 0x200005d0 8005e00: 200004d4 .word 0x200004d4 08005e04 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8005e04: 4770 bx lr ... 08005e08 : { /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_AFIO_CLK_ENABLE(); 8005e08: 4b0e ldr r3, [pc, #56] ; (8005e44 ) { 8005e0a: b082 sub sp, #8 __HAL_RCC_AFIO_CLK_ENABLE(); 8005e0c: 699a ldr r2, [r3, #24] 8005e0e: f042 0201 orr.w r2, r2, #1 8005e12: 619a str r2, [r3, #24] 8005e14: 699a ldr r2, [r3, #24] 8005e16: f002 0201 and.w r2, r2, #1 8005e1a: 9200 str r2, [sp, #0] 8005e1c: 9a00 ldr r2, [sp, #0] __HAL_RCC_PWR_CLK_ENABLE(); 8005e1e: 69da ldr r2, [r3, #28] 8005e20: f042 5280 orr.w r2, r2, #268435456 ; 0x10000000 8005e24: 61da str r2, [r3, #28] 8005e26: 69db ldr r3, [r3, #28] /* System interrupt init*/ /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled */ __HAL_AFIO_REMAP_SWJ_NOJTAG(); 8005e28: 4a07 ldr r2, [pc, #28] ; (8005e48 ) __HAL_RCC_PWR_CLK_ENABLE(); 8005e2a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8005e2e: 9301 str r3, [sp, #4] 8005e30: 9b01 ldr r3, [sp, #4] __HAL_AFIO_REMAP_SWJ_NOJTAG(); 8005e32: 6853 ldr r3, [r2, #4] 8005e34: f023 63e0 bic.w r3, r3, #117440512 ; 0x7000000 8005e38: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000 8005e3c: 6053 str r3, [r2, #4] /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8005e3e: b002 add sp, #8 8005e40: 4770 bx lr 8005e42: bf00 nop 8005e44: 40021000 .word 0x40021000 8005e48: 40010000 .word 0x40010000 08005e4c : * @param hadc: ADC handle pointer * @retval None */ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) { GPIO_InitTypeDef GPIO_InitStruct = {0}; 8005e4c: 2210 movs r2, #16 { 8005e4e: b530 push {r4, r5, lr} 8005e50: 4605 mov r5, r0 8005e52: b089 sub sp, #36 ; 0x24 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8005e54: eb0d 0002 add.w r0, sp, r2 8005e58: 2100 movs r1, #0 8005e5a: f000 f9df bl 800621c if(hadc->Instance==ADC1) 8005e5e: 682a ldr r2, [r5, #0] 8005e60: 4b2b ldr r3, [pc, #172] ; (8005f10 ) 8005e62: 429a cmp r2, r3 8005e64: d152 bne.n 8005f0c { /* USER CODE BEGIN ADC1_MspInit 0 */ /* USER CODE END ADC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_ADC1_CLK_ENABLE(); 8005e66: f503 436c add.w r3, r3, #60416 ; 0xec00 8005e6a: 699a ldr r2, [r3, #24] PA7 ------> ADC1_IN7 PB0 ------> ADC1_IN8 PB1 ------> ADC1_IN9 */ GPIO_InitStruct.Pin = DET_3_5G_UL_IN_Pin|DET_3_5G_UL_OUT_Pin|RFU_TEMP_Pin|_28V_DET_Pin; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8005e6c: 2403 movs r4, #3 __HAL_RCC_ADC1_CLK_ENABLE(); 8005e6e: f442 7200 orr.w r2, r2, #512 ; 0x200 8005e72: 619a str r2, [r3, #24] 8005e74: 699a ldr r2, [r3, #24] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8005e76: a904 add r1, sp, #16 __HAL_RCC_ADC1_CLK_ENABLE(); 8005e78: f402 7200 and.w r2, r2, #512 ; 0x200 8005e7c: 9200 str r2, [sp, #0] 8005e7e: 9a00 ldr r2, [sp, #0] __HAL_RCC_GPIOC_CLK_ENABLE(); 8005e80: 699a ldr r2, [r3, #24] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8005e82: 4824 ldr r0, [pc, #144] ; (8005f14 ) __HAL_RCC_GPIOC_CLK_ENABLE(); 8005e84: f042 0210 orr.w r2, r2, #16 8005e88: 619a str r2, [r3, #24] 8005e8a: 699a ldr r2, [r3, #24] 8005e8c: f002 0210 and.w r2, r2, #16 8005e90: 9201 str r2, [sp, #4] 8005e92: 9a01 ldr r2, [sp, #4] __HAL_RCC_GPIOA_CLK_ENABLE(); 8005e94: 699a ldr r2, [r3, #24] 8005e96: f042 0204 orr.w r2, r2, #4 8005e9a: 619a str r2, [r3, #24] 8005e9c: 699a ldr r2, [r3, #24] 8005e9e: f002 0204 and.w r2, r2, #4 8005ea2: 9202 str r2, [sp, #8] 8005ea4: 9a02 ldr r2, [sp, #8] __HAL_RCC_GPIOB_CLK_ENABLE(); 8005ea6: 699a ldr r2, [r3, #24] 8005ea8: f042 0208 orr.w r2, r2, #8 8005eac: 619a str r2, [r3, #24] 8005eae: 699b ldr r3, [r3, #24] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8005eb0: 9405 str r4, [sp, #20] __HAL_RCC_GPIOB_CLK_ENABLE(); 8005eb2: f003 0308 and.w r3, r3, #8 8005eb6: 9303 str r3, [sp, #12] 8005eb8: 9b03 ldr r3, [sp, #12] GPIO_InitStruct.Pin = DET_3_5G_UL_IN_Pin|DET_3_5G_UL_OUT_Pin|RFU_TEMP_Pin|_28V_DET_Pin; 8005eba: 230f movs r3, #15 8005ebc: 9304 str r3, [sp, #16] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8005ebe: f7fe fd6b bl 8004998 GPIO_InitStruct.Pin = DET_1_8G_DL_IN_Pin|DET_1_8G_DL_OUT_Pin|DET_1_8G_UL_IN_Pin|DET_1_8G_UL_OUT_Pin 8005ec2: 23ff movs r3, #255 ; 0xff |DET_2_1G_DL_IN_Pin|DET_2_1G_DL_OUT_Pin|DET_2_1G_UL_IN_Pin|DET_2_1G_UL_OUT_Pin; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8005ec4: a904 add r1, sp, #16 8005ec6: 4814 ldr r0, [pc, #80] ; (8005f18 ) GPIO_InitStruct.Pin = DET_1_8G_DL_IN_Pin|DET_1_8G_DL_OUT_Pin|DET_1_8G_UL_IN_Pin|DET_1_8G_UL_OUT_Pin 8005ec8: 9304 str r3, [sp, #16] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8005eca: 9405 str r4, [sp, #20] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8005ecc: f7fe fd64 bl 8004998 GPIO_InitStruct.Pin = DET_3_5G_DL_IN_Pin|DET_3_5G_DL_OUT_Pin; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8005ed0: 4812 ldr r0, [pc, #72] ; (8005f1c ) 8005ed2: a904 add r1, sp, #16 GPIO_InitStruct.Pin = DET_3_5G_DL_IN_Pin|DET_3_5G_DL_OUT_Pin; 8005ed4: 9404 str r4, [sp, #16] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8005ed6: 9405 str r4, [sp, #20] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8005ed8: f7fe fd5e bl 8004998 /* ADC1 DMA Init */ /* ADC1 Init */ hdma_adc1.Instance = DMA1_Channel1; hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY; hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE; hdma_adc1.Init.MemInc = DMA_MINC_ENABLE; 8005edc: 2280 movs r2, #128 ; 0x80 hdma_adc1.Instance = DMA1_Channel1; 8005ede: 4c10 ldr r4, [pc, #64] ; (8005f20 ) 8005ee0: 4b10 ldr r3, [pc, #64] ; (8005f24 ) hdma_adc1.Init.MemInc = DMA_MINC_ENABLE; 8005ee2: 60e2 str r2, [r4, #12] hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; 8005ee4: f44f 7200 mov.w r2, #512 ; 0x200 hdma_adc1.Instance = DMA1_Channel1; 8005ee8: 6023 str r3, [r4, #0] hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; 8005eea: 6122 str r2, [r4, #16] hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY; 8005eec: 2300 movs r3, #0 hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; 8005eee: f44f 6200 mov.w r2, #2048 ; 0x800 hdma_adc1.Init.Mode = DMA_NORMAL; hdma_adc1.Init.Priority = DMA_PRIORITY_LOW; if (HAL_DMA_Init(&hdma_adc1) != HAL_OK) 8005ef2: 4620 mov r0, r4 hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY; 8005ef4: 6063 str r3, [r4, #4] hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE; 8005ef6: 60a3 str r3, [r4, #8] hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; 8005ef8: 6162 str r2, [r4, #20] hdma_adc1.Init.Mode = DMA_NORMAL; 8005efa: 61a3 str r3, [r4, #24] hdma_adc1.Init.Priority = DMA_PRIORITY_LOW; 8005efc: 61e3 str r3, [r4, #28] if (HAL_DMA_Init(&hdma_adc1) != HAL_OK) 8005efe: f7fe fb83 bl 8004608 8005f02: b108 cbz r0, 8005f08 { Error_Handler(); 8005f04: f7ff ff7e bl 8005e04 } __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc1); 8005f08: 622c str r4, [r5, #32] 8005f0a: 6265 str r5, [r4, #36] ; 0x24 /* USER CODE BEGIN ADC1_MspInit 1 */ /* USER CODE END ADC1_MspInit 1 */ } } 8005f0c: b009 add sp, #36 ; 0x24 8005f0e: bd30 pop {r4, r5, pc} 8005f10: 40012400 .word 0x40012400 8005f14: 40011000 .word 0x40011000 8005f18: 40010800 .word 0x40010800 8005f1c: 40010c00 .word 0x40010c00 8005f20: 20000514 .word 0x20000514 8005f24: 40020008 .word 0x40020008 08005f28 : * @param htim_base: TIM_Base handle pointer * @retval None */ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) { if(htim_base->Instance==TIM6) 8005f28: 6802 ldr r2, [r0, #0] 8005f2a: 4b08 ldr r3, [pc, #32] ; (8005f4c ) { 8005f2c: b082 sub sp, #8 if(htim_base->Instance==TIM6) 8005f2e: 429a cmp r2, r3 8005f30: d10a bne.n 8005f48 { /* USER CODE BEGIN TIM6_MspInit 0 */ /* USER CODE END TIM6_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM6_CLK_ENABLE(); 8005f32: f503 3300 add.w r3, r3, #131072 ; 0x20000 8005f36: 69da ldr r2, [r3, #28] 8005f38: f042 0210 orr.w r2, r2, #16 8005f3c: 61da str r2, [r3, #28] 8005f3e: 69db ldr r3, [r3, #28] 8005f40: f003 0310 and.w r3, r3, #16 8005f44: 9301 str r3, [sp, #4] 8005f46: 9b01 ldr r3, [sp, #4] /* USER CODE BEGIN TIM6_MspInit 1 */ /* USER CODE END TIM6_MspInit 1 */ } } 8005f48: b002 add sp, #8 8005f4a: 4770 bx lr 8005f4c: 40001000 .word 0x40001000 08005f50 : * This function configures the hardware resources used in this example * @param huart: UART handle pointer * @retval None */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { 8005f50: b510 push {r4, lr} 8005f52: 4604 mov r4, r0 8005f54: b086 sub sp, #24 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8005f56: 2210 movs r2, #16 8005f58: 2100 movs r1, #0 8005f5a: a802 add r0, sp, #8 8005f5c: f000 f95e bl 800621c if(huart->Instance==USART1) 8005f60: 6822 ldr r2, [r4, #0] 8005f62: 4b17 ldr r3, [pc, #92] ; (8005fc0 ) 8005f64: 429a cmp r2, r3 8005f66: d128 bne.n 8005fba { /* USER CODE BEGIN USART1_MspInit 0 */ /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); 8005f68: f503 4358 add.w r3, r3, #55296 ; 0xd800 8005f6c: 699a ldr r2, [r3, #24] PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_9; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8005f6e: a902 add r1, sp, #8 __HAL_RCC_USART1_CLK_ENABLE(); 8005f70: f442 4280 orr.w r2, r2, #16384 ; 0x4000 8005f74: 619a str r2, [r3, #24] 8005f76: 699a ldr r2, [r3, #24] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8005f78: 4812 ldr r0, [pc, #72] ; (8005fc4 ) __HAL_RCC_USART1_CLK_ENABLE(); 8005f7a: f402 4280 and.w r2, r2, #16384 ; 0x4000 8005f7e: 9200 str r2, [sp, #0] 8005f80: 9a00 ldr r2, [sp, #0] __HAL_RCC_GPIOA_CLK_ENABLE(); 8005f82: 699a ldr r2, [r3, #24] 8005f84: f042 0204 orr.w r2, r2, #4 8005f88: 619a str r2, [r3, #24] 8005f8a: 699b ldr r3, [r3, #24] 8005f8c: f003 0304 and.w r3, r3, #4 8005f90: 9301 str r3, [sp, #4] 8005f92: 9b01 ldr r3, [sp, #4] GPIO_InitStruct.Pin = GPIO_PIN_9; 8005f94: f44f 7300 mov.w r3, #512 ; 0x200 8005f98: 9302 str r3, [sp, #8] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8005f9a: 2302 movs r3, #2 8005f9c: 9303 str r3, [sp, #12] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8005f9e: 2303 movs r3, #3 8005fa0: 9305 str r3, [sp, #20] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8005fa2: f7fe fcf9 bl 8004998 GPIO_InitStruct.Pin = GPIO_PIN_10; 8005fa6: f44f 6380 mov.w r3, #1024 ; 0x400 8005faa: 9302 str r3, [sp, #8] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8005fac: 2300 movs r3, #0 GPIO_InitStruct.Pull = GPIO_NOPULL; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8005fae: a902 add r1, sp, #8 8005fb0: 4804 ldr r0, [pc, #16] ; (8005fc4 ) GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8005fb2: 9303 str r3, [sp, #12] GPIO_InitStruct.Pull = GPIO_NOPULL; 8005fb4: 9304 str r3, [sp, #16] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8005fb6: f7fe fcef bl 8004998 /* USER CODE BEGIN USART1_MspInit 1 */ /* USER CODE END USART1_MspInit 1 */ } } 8005fba: b006 add sp, #24 8005fbc: bd10 pop {r4, pc} 8005fbe: bf00 nop 8005fc0: 40013800 .word 0x40013800 8005fc4: 40010800 .word 0x40010800 08005fc8 : 8005fc8: 4770 bx lr 08005fca : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8005fca: e7fe b.n 8005fca 08005fcc : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8005fcc: e7fe b.n 8005fcc 08005fce : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { 8005fce: e7fe b.n 8005fce 08005fd0 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8005fd0: e7fe b.n 8005fd0 08005fd2 : 8005fd2: 4770 bx lr 08005fd4 : 8005fd4: 4770 bx lr 08005fd6 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8005fd6: 4770 bx lr 08005fd8 : void SysTick_Handler(void) { /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 8005fd8: f7fe b95a b.w 8004290 08005fdc : void DMA1_Channel1_IRQHandler(void) { /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */ /* USER CODE END DMA1_Channel1_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc1); 8005fdc: 4801 ldr r0, [pc, #4] ; (8005fe4 ) 8005fde: f7fe bbff b.w 80047e0 8005fe2: bf00 nop 8005fe4: 20000514 .word 0x20000514 08005fe8 : void USART1_IRQHandler(void) { /* USER CODE BEGIN USART1_IRQn 0 */ /* USER CODE END USART1_IRQn 0 */ HAL_UART_IRQHandler(&huart1); 8005fe8: 4801 ldr r0, [pc, #4] ; (8005ff0 ) 8005fea: f7ff bc3d b.w 8005868 8005fee: bf00 nop 8005ff0: 200004d4 .word 0x200004d4 08005ff4 : void TIM6_IRQHandler(void) { /* USER CODE BEGIN TIM6_IRQn 0 */ /* USER CODE END TIM6_IRQn 0 */ HAL_TIM_IRQHandler(&htim6); 8005ff4: 4801 ldr r0, [pc, #4] ; (8005ffc ) 8005ff6: f7ff b8db b.w 80051b0 8005ffa: bf00 nop 8005ffc: 20000558 .word 0x20000558 08006000 <_read>: _kill(status, -1); while (1) {} /* Make sure we hang here */ } __attribute__((weak)) int _read(int file, char *ptr, int len) { 8006000: b570 push {r4, r5, r6, lr} 8006002: 460e mov r6, r1 8006004: 4615 mov r5, r2 int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 8006006: 460c mov r4, r1 8006008: 1ba3 subs r3, r4, r6 800600a: 429d cmp r5, r3 800600c: dc01 bgt.n 8006012 <_read+0x12> { *ptr++ = __io_getchar(); } return len; } 800600e: 4628 mov r0, r5 8006010: bd70 pop {r4, r5, r6, pc} *ptr++ = __io_getchar(); 8006012: f3af 8000 nop.w 8006016: f804 0b01 strb.w r0, [r4], #1 800601a: e7f5 b.n 8006008 <_read+0x8> 0800601c <_sbrk>: } return len; } caddr_t _sbrk(int incr) { 800601c: b508 push {r3, lr} extern char end asm("end"); static char *heap_end; char *prev_heap_end; if (heap_end == 0) 800601e: 4b0a ldr r3, [pc, #40] ; (8006048 <_sbrk+0x2c>) { 8006020: 4602 mov r2, r0 if (heap_end == 0) 8006022: 6819 ldr r1, [r3, #0] 8006024: b909 cbnz r1, 800602a <_sbrk+0xe> heap_end = &end; 8006026: 4909 ldr r1, [pc, #36] ; (800604c <_sbrk+0x30>) 8006028: 6019 str r1, [r3, #0] prev_heap_end = heap_end; if (heap_end + incr > stack_ptr) 800602a: 4669 mov r1, sp prev_heap_end = heap_end; 800602c: 6818 ldr r0, [r3, #0] if (heap_end + incr > stack_ptr) 800602e: 4402 add r2, r0 8006030: 428a cmp r2, r1 8006032: d906 bls.n 8006042 <_sbrk+0x26> { // write(1, "Heap and stack collision\n", 25); // abort(); errno = ENOMEM; 8006034: f000 f8c8 bl 80061c8 <__errno> 8006038: 230c movs r3, #12 800603a: 6003 str r3, [r0, #0] return (caddr_t) -1; 800603c: f04f 30ff mov.w r0, #4294967295 8006040: bd08 pop {r3, pc} } heap_end += incr; 8006042: 601a str r2, [r3, #0] return (caddr_t) prev_heap_end; } 8006044: bd08 pop {r3, pc} 8006046: bf00 nop 8006048: 20000094 .word 0x20000094 800604c: 200007ec .word 0x200007ec 08006050 <_close>: int _close(int file) { return -1; } 8006050: f04f 30ff mov.w r0, #4294967295 8006054: 4770 bx lr 08006056 <_fstat>: int _fstat(int file, struct stat *st) { st->st_mode = S_IFCHR; 8006056: f44f 5300 mov.w r3, #8192 ; 0x2000 return 0; } 800605a: 2000 movs r0, #0 st->st_mode = S_IFCHR; 800605c: 604b str r3, [r1, #4] } 800605e: 4770 bx lr 08006060 <_isatty>: int _isatty(int file) { return 1; } 8006060: 2001 movs r0, #1 8006062: 4770 bx lr 08006064 <_lseek>: int _lseek(int file, int ptr, int dir) { return 0; } 8006064: 2000 movs r0, #0 8006066: 4770 bx lr 08006068 : */ void SystemInit (void) { /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ /* Set HSION bit */ RCC->CR |= 0x00000001U; 8006068: 4b0e ldr r3, [pc, #56] ; (80060a4 ) 800606a: 681a ldr r2, [r3, #0] 800606c: f042 0201 orr.w r2, r2, #1 8006070: 601a str r2, [r3, #0] /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ #if !defined(STM32F105xC) && !defined(STM32F107xC) RCC->CFGR &= 0xF8FF0000U; 8006072: 6859 ldr r1, [r3, #4] 8006074: 4a0c ldr r2, [pc, #48] ; (80060a8 ) 8006076: 400a ands r2, r1 8006078: 605a str r2, [r3, #4] #else RCC->CFGR &= 0xF0FF0000U; #endif /* STM32F105xC */ /* Reset HSEON, CSSON and PLLON bits */ RCC->CR &= 0xFEF6FFFFU; 800607a: 681a ldr r2, [r3, #0] 800607c: f022 7284 bic.w r2, r2, #17301504 ; 0x1080000 8006080: f422 3280 bic.w r2, r2, #65536 ; 0x10000 8006084: 601a str r2, [r3, #0] /* Reset HSEBYP bit */ RCC->CR &= 0xFFFBFFFFU; 8006086: 681a ldr r2, [r3, #0] 8006088: f422 2280 bic.w r2, r2, #262144 ; 0x40000 800608c: 601a str r2, [r3, #0] /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ RCC->CFGR &= 0xFF80FFFFU; 800608e: 685a ldr r2, [r3, #4] 8006090: f422 02fe bic.w r2, r2, #8323072 ; 0x7f0000 8006094: 605a str r2, [r3, #4] /* Reset CFGR2 register */ RCC->CFGR2 = 0x00000000U; #else /* Disable all interrupts and clear pending bits */ RCC->CIR = 0x009F0000U; 8006096: f44f 021f mov.w r2, #10420224 ; 0x9f0000 800609a: 609a str r2, [r3, #8] #endif #ifdef VECT_TAB_SRAM SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #else SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ 800609c: 4a03 ldr r2, [pc, #12] ; (80060ac ) 800609e: 4b04 ldr r3, [pc, #16] ; (80060b0 ) 80060a0: 609a str r2, [r3, #8] 80060a2: 4770 bx lr 80060a4: 40021000 .word 0x40021000 80060a8: f8ff0000 .word 0xf8ff0000 80060ac: 08004000 .word 0x08004000 80060b0: e000ed00 .word 0xe000ed00 080060b4 : pUARTQUEUE pQueue = &TerminalQueue; // if (HAL_UART_Transmit(dst, pQueue->Buffer + pQueue->tail, 1, 3000) != HAL_OK) // { // _Error_Handler(__FILE__, __LINE__); // } uart_buf[cnt++] = *(pQueue->Buffer + pQueue->tail); 80060b4: 4a15 ldr r2, [pc, #84] ; (800610c ) { 80060b6: b570 push {r4, r5, r6, lr} uart_buf[cnt++] = *(pQueue->Buffer + pQueue->tail); 80060b8: 6814 ldr r4, [r2, #0] 80060ba: 4e15 ldr r6, [pc, #84] ; (8006110 ) 80060bc: 1c63 adds r3, r4, #1 80060be: 6013 str r3, [r2, #0] 80060c0: 4b14 ldr r3, [pc, #80] ; (8006114 ) 80060c2: 6859 ldr r1, [r3, #4] 80060c4: f103 000c add.w r0, r3, #12 80060c8: 5c0d ldrb r5, [r1, r0] pQueue->tail++; 80060ca: 3101 adds r1, #1 if (pQueue->tail >= QUEUE_BUFFER_LENGTH) pQueue->tail = 0; 80060cc: 29fe cmp r1, #254 ; 0xfe uart_buf[cnt++] = *(pQueue->Buffer + pQueue->tail); 80060ce: f846 5024 str.w r5, [r6, r4, lsl #2] 80060d2: 4615 mov r5, r2 if (pQueue->tail >= QUEUE_BUFFER_LENGTH) pQueue->tail = 0; 80060d4: bfc8 it gt 80060d6: 2200 movgt r2, #0 pQueue->data--; 80060d8: 689c ldr r4, [r3, #8] pQueue->tail++; 80060da: bfd8 it le 80060dc: 6059 strle r1, [r3, #4] pQueue->data--; 80060de: f104 34ff add.w r4, r4, #4294967295 if (pQueue->tail >= QUEUE_BUFFER_LENGTH) pQueue->tail = 0; 80060e2: bfc8 it gt 80060e4: 605a strgt r2, [r3, #4] pQueue->data--; 80060e6: 609c str r4, [r3, #8] if(pQueue->data == 0){ 80060e8: b974 cbnz r4, 8006108 RF_Ctrl_Main(&uart_buf[0]); 80060ea: 4809 ldr r0, [pc, #36] ; (8006110 ) 80060ec: f000 f838 bl 8006160 // } #endif // PYJ.2019.07.15_END -- cnt = 0; for(int i = 0; i < QUEUE_BUFFER_LENGTH; i++) uart_buf[i] = 0; 80060f0: 4623 mov r3, r4 cnt = 0; 80060f2: 602c str r4, [r5, #0] uart_buf[i] = 0; 80060f4: f846 3024 str.w r3, [r6, r4, lsl #2] for(int i = 0; i < QUEUE_BUFFER_LENGTH; i++) 80060f8: 3401 adds r4, #1 80060fa: 2cff cmp r4, #255 ; 0xff 80060fc: d1fa bne.n 80060f4 HAL_Delay(1); 80060fe: 2001 movs r0, #1 } } 8006100: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} HAL_Delay(1); 8006104: f7fe b8d6 b.w 80042b4 8006108: bd70 pop {r4, r5, r6, pc} 800610a: bf00 nop 800610c: 20000098 .word 0x20000098 8006110: 2000009c .word 0x2000009c 8006114: 200005d0 .word 0x200005d0 08006118 : UartTimerCnt = 0; 8006118: 2300 movs r3, #0 { 800611a: b510 push {r4, lr} UartTimerCnt = 0; 800611c: 4a0c ldr r2, [pc, #48] ; (8006150 ) pQueue->head++; 800611e: 4c0d ldr r4, [pc, #52] ; (8006154 ) UartTimerCnt = 0; 8006120: 6013 str r3, [r2, #0] pQueue->head++; 8006122: 6822 ldr r2, [r4, #0] 8006124: 3201 adds r2, #1 8006126: 2afe cmp r2, #254 ; 0xfe 8006128: bfd8 it le 800612a: 4613 movle r3, r2 800612c: 6023 str r3, [r4, #0] pQueue->data++; 800612e: 68a3 ldr r3, [r4, #8] 8006130: 3301 adds r3, #1 if (pQueue->data >= QUEUE_BUFFER_LENGTH) 8006132: 2bfe cmp r3, #254 ; 0xfe pQueue->data++; 8006134: 60a3 str r3, [r4, #8] if (pQueue->data >= QUEUE_BUFFER_LENGTH) 8006136: dd01 ble.n 800613c GetDataFromUartQueue(huart); 8006138: f7ff ffbc bl 80060b4 HAL_UART_Receive_DMA(&hTerminal, pQueue->Buffer + pQueue->head, 1); 800613c: 6823 ldr r3, [r4, #0] 800613e: 4906 ldr r1, [pc, #24] ; (8006158 ) 8006140: 2201 movs r2, #1 } 8006142: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_UART_Receive_DMA(&hTerminal, pQueue->Buffer + pQueue->head, 1); 8006146: 4419 add r1, r3 8006148: 4804 ldr r0, [pc, #16] ; (800615c ) 800614a: f7ff babb b.w 80056c4 800614e: bf00 nop 8006150: 20000090 .word 0x20000090 8006154: 200005d0 .word 0x200005d0 8006158: 200005dc .word 0x200005dc 800615c: 200004d4 .word 0x200004d4 08006160 : }Bluecell_Prot_p; bool RF_Ctrl_Main(uint8_t* data_buf){ 8006160: b508 push {r3, lr} case TYPE_ATT_3_5GHz_UL: case TYPE_ATT_3_5GHz_COM1: // 15 case TYPE_ATT_3_5GHz_COM2: case TYPE_ATT_3_5GHz_COM3: default: printf("Function : %s LINE : %d type : %d \r\n",__func__,__LINE__,type); 8006162: 22f1 movs r2, #241 ; 0xf1 8006164: 7843 ldrb r3, [r0, #1] 8006166: 4903 ldr r1, [pc, #12] ; (8006174 ) 8006168: 4803 ldr r0, [pc, #12] ; (8006178 ) 800616a: f000 f85f bl 800622c break; } return ret; } 800616e: 2000 movs r0, #0 8006170: bd08 pop {r3, pc} 8006172: bf00 nop 8006174: 080072ef .word 0x080072ef 8006178: 080072c5 .word 0x080072c5 0800617c : .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 800617c: 2100 movs r1, #0 b LoopCopyDataInit 800617e: e003 b.n 8006188 08006180 : CopyDataInit: ldr r3, =_sidata 8006180: 4b0b ldr r3, [pc, #44] ; (80061b0 ) ldr r3, [r3, r1] 8006182: 585b ldr r3, [r3, r1] str r3, [r0, r1] 8006184: 5043 str r3, [r0, r1] adds r1, r1, #4 8006186: 3104 adds r1, #4 08006188 : LoopCopyDataInit: ldr r0, =_sdata 8006188: 480a ldr r0, [pc, #40] ; (80061b4 ) ldr r3, =_edata 800618a: 4b0b ldr r3, [pc, #44] ; (80061b8 ) adds r2, r0, r1 800618c: 1842 adds r2, r0, r1 cmp r2, r3 800618e: 429a cmp r2, r3 bcc CopyDataInit 8006190: d3f6 bcc.n 8006180 ldr r2, =_sbss 8006192: 4a0a ldr r2, [pc, #40] ; (80061bc ) b LoopFillZerobss 8006194: e002 b.n 800619c 08006196 : /* Zero fill the bss segment. */ FillZerobss: movs r3, #0 8006196: 2300 movs r3, #0 str r3, [r2], #4 8006198: f842 3b04 str.w r3, [r2], #4 0800619c : LoopFillZerobss: ldr r3, = _ebss 800619c: 4b08 ldr r3, [pc, #32] ; (80061c0 ) cmp r2, r3 800619e: 429a cmp r2, r3 bcc FillZerobss 80061a0: d3f9 bcc.n 8006196 /* Call the clock system intitialization function.*/ bl SystemInit 80061a2: f7ff ff61 bl 8006068 /* Call static constructors */ bl __libc_init_array 80061a6: f000 f815 bl 80061d4 <__libc_init_array> /* Call the application's entry point.*/ bl main 80061aa: f7ff fc59 bl 8005a60
bx lr 80061ae: 4770 bx lr ldr r3, =_sidata 80061b0: 0800739c .word 0x0800739c ldr r0, =_sdata 80061b4: 20000000 .word 0x20000000 ldr r3, =_edata 80061b8: 20000070 .word 0x20000070 ldr r2, =_sbss 80061bc: 20000070 .word 0x20000070 ldr r3, = _ebss 80061c0: 200007ec .word 0x200007ec 080061c4 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 80061c4: e7fe b.n 80061c4 ... 080061c8 <__errno>: 80061c8: 4b01 ldr r3, [pc, #4] ; (80061d0 <__errno+0x8>) 80061ca: 6818 ldr r0, [r3, #0] 80061cc: 4770 bx lr 80061ce: bf00 nop 80061d0: 2000000c .word 0x2000000c 080061d4 <__libc_init_array>: 80061d4: b570 push {r4, r5, r6, lr} 80061d6: 2500 movs r5, #0 80061d8: 4e0c ldr r6, [pc, #48] ; (800620c <__libc_init_array+0x38>) 80061da: 4c0d ldr r4, [pc, #52] ; (8006210 <__libc_init_array+0x3c>) 80061dc: 1ba4 subs r4, r4, r6 80061de: 10a4 asrs r4, r4, #2 80061e0: 42a5 cmp r5, r4 80061e2: d109 bne.n 80061f8 <__libc_init_array+0x24> 80061e4: f001 f848 bl 8007278 <_init> 80061e8: 2500 movs r5, #0 80061ea: 4e0a ldr r6, [pc, #40] ; (8006214 <__libc_init_array+0x40>) 80061ec: 4c0a ldr r4, [pc, #40] ; (8006218 <__libc_init_array+0x44>) 80061ee: 1ba4 subs r4, r4, r6 80061f0: 10a4 asrs r4, r4, #2 80061f2: 42a5 cmp r5, r4 80061f4: d105 bne.n 8006202 <__libc_init_array+0x2e> 80061f6: bd70 pop {r4, r5, r6, pc} 80061f8: f856 3025 ldr.w r3, [r6, r5, lsl #2] 80061fc: 4798 blx r3 80061fe: 3501 adds r5, #1 8006200: e7ee b.n 80061e0 <__libc_init_array+0xc> 8006202: f856 3025 ldr.w r3, [r6, r5, lsl #2] 8006206: 4798 blx r3 8006208: 3501 adds r5, #1 800620a: e7f2 b.n 80061f2 <__libc_init_array+0x1e> 800620c: 08007394 .word 0x08007394 8006210: 08007394 .word 0x08007394 8006214: 08007394 .word 0x08007394 8006218: 08007398 .word 0x08007398 0800621c : 800621c: 4603 mov r3, r0 800621e: 4402 add r2, r0 8006220: 4293 cmp r3, r2 8006222: d100 bne.n 8006226 8006224: 4770 bx lr 8006226: f803 1b01 strb.w r1, [r3], #1 800622a: e7f9 b.n 8006220 0800622c : 800622c: b40f push {r0, r1, r2, r3} 800622e: 4b0a ldr r3, [pc, #40] ; (8006258 ) 8006230: b513 push {r0, r1, r4, lr} 8006232: 681c ldr r4, [r3, #0] 8006234: b124 cbz r4, 8006240 8006236: 69a3 ldr r3, [r4, #24] 8006238: b913 cbnz r3, 8006240 800623a: 4620 mov r0, r4 800623c: f000 fada bl 80067f4 <__sinit> 8006240: ab05 add r3, sp, #20 8006242: 9a04 ldr r2, [sp, #16] 8006244: 68a1 ldr r1, [r4, #8] 8006246: 4620 mov r0, r4 8006248: 9301 str r3, [sp, #4] 800624a: f000 fc9b bl 8006b84 <_vfiprintf_r> 800624e: b002 add sp, #8 8006250: e8bd 4010 ldmia.w sp!, {r4, lr} 8006254: b004 add sp, #16 8006256: 4770 bx lr 8006258: 2000000c .word 0x2000000c 0800625c <_puts_r>: 800625c: b570 push {r4, r5, r6, lr} 800625e: 460e mov r6, r1 8006260: 4605 mov r5, r0 8006262: b118 cbz r0, 800626c <_puts_r+0x10> 8006264: 6983 ldr r3, [r0, #24] 8006266: b90b cbnz r3, 800626c <_puts_r+0x10> 8006268: f000 fac4 bl 80067f4 <__sinit> 800626c: 69ab ldr r3, [r5, #24] 800626e: 68ac ldr r4, [r5, #8] 8006270: b913 cbnz r3, 8006278 <_puts_r+0x1c> 8006272: 4628 mov r0, r5 8006274: f000 fabe bl 80067f4 <__sinit> 8006278: 4b23 ldr r3, [pc, #140] ; (8006308 <_puts_r+0xac>) 800627a: 429c cmp r4, r3 800627c: d117 bne.n 80062ae <_puts_r+0x52> 800627e: 686c ldr r4, [r5, #4] 8006280: 89a3 ldrh r3, [r4, #12] 8006282: 071b lsls r3, r3, #28 8006284: d51d bpl.n 80062c2 <_puts_r+0x66> 8006286: 6923 ldr r3, [r4, #16] 8006288: b1db cbz r3, 80062c2 <_puts_r+0x66> 800628a: 3e01 subs r6, #1 800628c: 68a3 ldr r3, [r4, #8] 800628e: f816 1f01 ldrb.w r1, [r6, #1]! 8006292: 3b01 subs r3, #1 8006294: 60a3 str r3, [r4, #8] 8006296: b9e9 cbnz r1, 80062d4 <_puts_r+0x78> 8006298: 2b00 cmp r3, #0 800629a: da2e bge.n 80062fa <_puts_r+0x9e> 800629c: 4622 mov r2, r4 800629e: 210a movs r1, #10 80062a0: 4628 mov r0, r5 80062a2: f000 f8f5 bl 8006490 <__swbuf_r> 80062a6: 3001 adds r0, #1 80062a8: d011 beq.n 80062ce <_puts_r+0x72> 80062aa: 200a movs r0, #10 80062ac: bd70 pop {r4, r5, r6, pc} 80062ae: 4b17 ldr r3, [pc, #92] ; (800630c <_puts_r+0xb0>) 80062b0: 429c cmp r4, r3 80062b2: d101 bne.n 80062b8 <_puts_r+0x5c> 80062b4: 68ac ldr r4, [r5, #8] 80062b6: e7e3 b.n 8006280 <_puts_r+0x24> 80062b8: 4b15 ldr r3, [pc, #84] ; (8006310 <_puts_r+0xb4>) 80062ba: 429c cmp r4, r3 80062bc: bf08 it eq 80062be: 68ec ldreq r4, [r5, #12] 80062c0: e7de b.n 8006280 <_puts_r+0x24> 80062c2: 4621 mov r1, r4 80062c4: 4628 mov r0, r5 80062c6: f000 f935 bl 8006534 <__swsetup_r> 80062ca: 2800 cmp r0, #0 80062cc: d0dd beq.n 800628a <_puts_r+0x2e> 80062ce: f04f 30ff mov.w r0, #4294967295 80062d2: bd70 pop {r4, r5, r6, pc} 80062d4: 2b00 cmp r3, #0 80062d6: da04 bge.n 80062e2 <_puts_r+0x86> 80062d8: 69a2 ldr r2, [r4, #24] 80062da: 4293 cmp r3, r2 80062dc: db06 blt.n 80062ec <_puts_r+0x90> 80062de: 290a cmp r1, #10 80062e0: d004 beq.n 80062ec <_puts_r+0x90> 80062e2: 6823 ldr r3, [r4, #0] 80062e4: 1c5a adds r2, r3, #1 80062e6: 6022 str r2, [r4, #0] 80062e8: 7019 strb r1, [r3, #0] 80062ea: e7cf b.n 800628c <_puts_r+0x30> 80062ec: 4622 mov r2, r4 80062ee: 4628 mov r0, r5 80062f0: f000 f8ce bl 8006490 <__swbuf_r> 80062f4: 3001 adds r0, #1 80062f6: d1c9 bne.n 800628c <_puts_r+0x30> 80062f8: e7e9 b.n 80062ce <_puts_r+0x72> 80062fa: 200a movs r0, #10 80062fc: 6823 ldr r3, [r4, #0] 80062fe: 1c5a adds r2, r3, #1 8006300: 6022 str r2, [r4, #0] 8006302: 7018 strb r0, [r3, #0] 8006304: bd70 pop {r4, r5, r6, pc} 8006306: bf00 nop 8006308: 08007320 .word 0x08007320 800630c: 08007340 .word 0x08007340 8006310: 08007300 .word 0x08007300 08006314 : 8006314: 4b02 ldr r3, [pc, #8] ; (8006320 ) 8006316: 4601 mov r1, r0 8006318: 6818 ldr r0, [r3, #0] 800631a: f7ff bf9f b.w 800625c <_puts_r> 800631e: bf00 nop 8006320: 2000000c .word 0x2000000c 08006324 : 8006324: 2900 cmp r1, #0 8006326: f44f 6380 mov.w r3, #1024 ; 0x400 800632a: bf0c ite eq 800632c: 2202 moveq r2, #2 800632e: 2200 movne r2, #0 8006330: f000 b800 b.w 8006334 08006334 : 8006334: e92d 43f7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr} 8006338: 461d mov r5, r3 800633a: 4b51 ldr r3, [pc, #324] ; (8006480 ) 800633c: 4604 mov r4, r0 800633e: 681e ldr r6, [r3, #0] 8006340: 460f mov r7, r1 8006342: 4690 mov r8, r2 8006344: b126 cbz r6, 8006350 8006346: 69b3 ldr r3, [r6, #24] 8006348: b913 cbnz r3, 8006350 800634a: 4630 mov r0, r6 800634c: f000 fa52 bl 80067f4 <__sinit> 8006350: 4b4c ldr r3, [pc, #304] ; (8006484 ) 8006352: 429c cmp r4, r3 8006354: d152 bne.n 80063fc 8006356: 6874 ldr r4, [r6, #4] 8006358: f1b8 0f02 cmp.w r8, #2 800635c: d006 beq.n 800636c 800635e: f1b8 0f01 cmp.w r8, #1 8006362: f200 8089 bhi.w 8006478 8006366: 2d00 cmp r5, #0 8006368: f2c0 8086 blt.w 8006478 800636c: 4621 mov r1, r4 800636e: 4630 mov r0, r6 8006370: f000 f9d6 bl 8006720 <_fflush_r> 8006374: 6b61 ldr r1, [r4, #52] ; 0x34 8006376: b141 cbz r1, 800638a 8006378: f104 0344 add.w r3, r4, #68 ; 0x44 800637c: 4299 cmp r1, r3 800637e: d002 beq.n 8006386 8006380: 4630 mov r0, r6 8006382: f000 fb2d bl 80069e0 <_free_r> 8006386: 2300 movs r3, #0 8006388: 6363 str r3, [r4, #52] ; 0x34 800638a: 2300 movs r3, #0 800638c: 61a3 str r3, [r4, #24] 800638e: 6063 str r3, [r4, #4] 8006390: 89a3 ldrh r3, [r4, #12] 8006392: 061b lsls r3, r3, #24 8006394: d503 bpl.n 800639e 8006396: 6921 ldr r1, [r4, #16] 8006398: 4630 mov r0, r6 800639a: f000 fb21 bl 80069e0 <_free_r> 800639e: 89a3 ldrh r3, [r4, #12] 80063a0: f1b8 0f02 cmp.w r8, #2 80063a4: f423 634a bic.w r3, r3, #3232 ; 0xca0 80063a8: f023 0303 bic.w r3, r3, #3 80063ac: 81a3 strh r3, [r4, #12] 80063ae: d05d beq.n 800646c 80063b0: ab01 add r3, sp, #4 80063b2: 466a mov r2, sp 80063b4: 4621 mov r1, r4 80063b6: 4630 mov r0, r6 80063b8: f000 faa6 bl 8006908 <__swhatbuf_r> 80063bc: 89a3 ldrh r3, [r4, #12] 80063be: 4318 orrs r0, r3 80063c0: 81a0 strh r0, [r4, #12] 80063c2: bb2d cbnz r5, 8006410 80063c4: 9d00 ldr r5, [sp, #0] 80063c6: 4628 mov r0, r5 80063c8: f000 fb02 bl 80069d0 80063cc: 4607 mov r7, r0 80063ce: 2800 cmp r0, #0 80063d0: d14e bne.n 8006470 80063d2: f8dd 9000 ldr.w r9, [sp] 80063d6: 45a9 cmp r9, r5 80063d8: d13c bne.n 8006454 80063da: f04f 30ff mov.w r0, #4294967295 80063de: 89a3 ldrh r3, [r4, #12] 80063e0: f043 0302 orr.w r3, r3, #2 80063e4: 81a3 strh r3, [r4, #12] 80063e6: 2300 movs r3, #0 80063e8: 60a3 str r3, [r4, #8] 80063ea: f104 0347 add.w r3, r4, #71 ; 0x47 80063ee: 6023 str r3, [r4, #0] 80063f0: 6123 str r3, [r4, #16] 80063f2: 2301 movs r3, #1 80063f4: 6163 str r3, [r4, #20] 80063f6: b003 add sp, #12 80063f8: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} 80063fc: 4b22 ldr r3, [pc, #136] ; (8006488 ) 80063fe: 429c cmp r4, r3 8006400: d101 bne.n 8006406 8006402: 68b4 ldr r4, [r6, #8] 8006404: e7a8 b.n 8006358 8006406: 4b21 ldr r3, [pc, #132] ; (800648c ) 8006408: 429c cmp r4, r3 800640a: bf08 it eq 800640c: 68f4 ldreq r4, [r6, #12] 800640e: e7a3 b.n 8006358 8006410: 2f00 cmp r7, #0 8006412: d0d8 beq.n 80063c6 8006414: 69b3 ldr r3, [r6, #24] 8006416: b913 cbnz r3, 800641e 8006418: 4630 mov r0, r6 800641a: f000 f9eb bl 80067f4 <__sinit> 800641e: f1b8 0f01 cmp.w r8, #1 8006422: bf08 it eq 8006424: 89a3 ldrheq r3, [r4, #12] 8006426: 6027 str r7, [r4, #0] 8006428: bf04 itt eq 800642a: f043 0301 orreq.w r3, r3, #1 800642e: 81a3 strheq r3, [r4, #12] 8006430: 89a3 ldrh r3, [r4, #12] 8006432: 6127 str r7, [r4, #16] 8006434: f013 0008 ands.w r0, r3, #8 8006438: 6165 str r5, [r4, #20] 800643a: d01b beq.n 8006474 800643c: f013 0001 ands.w r0, r3, #1 8006440: f04f 0300 mov.w r3, #0 8006444: bf1f itttt ne 8006446: 426d negne r5, r5 8006448: 60a3 strne r3, [r4, #8] 800644a: 61a5 strne r5, [r4, #24] 800644c: 4618 movne r0, r3 800644e: bf08 it eq 8006450: 60a5 streq r5, [r4, #8] 8006452: e7d0 b.n 80063f6 8006454: 4648 mov r0, r9 8006456: f000 fabb bl 80069d0 800645a: 4607 mov r7, r0 800645c: 2800 cmp r0, #0 800645e: d0bc beq.n 80063da 8006460: 89a3 ldrh r3, [r4, #12] 8006462: 464d mov r5, r9 8006464: f043 0380 orr.w r3, r3, #128 ; 0x80 8006468: 81a3 strh r3, [r4, #12] 800646a: e7d3 b.n 8006414 800646c: 2000 movs r0, #0 800646e: e7b6 b.n 80063de 8006470: 46a9 mov r9, r5 8006472: e7f5 b.n 8006460 8006474: 60a0 str r0, [r4, #8] 8006476: e7be b.n 80063f6 8006478: f04f 30ff mov.w r0, #4294967295 800647c: e7bb b.n 80063f6 800647e: bf00 nop 8006480: 2000000c .word 0x2000000c 8006484: 08007320 .word 0x08007320 8006488: 08007340 .word 0x08007340 800648c: 08007300 .word 0x08007300 08006490 <__swbuf_r>: 8006490: b5f8 push {r3, r4, r5, r6, r7, lr} 8006492: 460e mov r6, r1 8006494: 4614 mov r4, r2 8006496: 4605 mov r5, r0 8006498: b118 cbz r0, 80064a2 <__swbuf_r+0x12> 800649a: 6983 ldr r3, [r0, #24] 800649c: b90b cbnz r3, 80064a2 <__swbuf_r+0x12> 800649e: f000 f9a9 bl 80067f4 <__sinit> 80064a2: 4b21 ldr r3, [pc, #132] ; (8006528 <__swbuf_r+0x98>) 80064a4: 429c cmp r4, r3 80064a6: d12a bne.n 80064fe <__swbuf_r+0x6e> 80064a8: 686c ldr r4, [r5, #4] 80064aa: 69a3 ldr r3, [r4, #24] 80064ac: 60a3 str r3, [r4, #8] 80064ae: 89a3 ldrh r3, [r4, #12] 80064b0: 071a lsls r2, r3, #28 80064b2: d52e bpl.n 8006512 <__swbuf_r+0x82> 80064b4: 6923 ldr r3, [r4, #16] 80064b6: b363 cbz r3, 8006512 <__swbuf_r+0x82> 80064b8: 6923 ldr r3, [r4, #16] 80064ba: 6820 ldr r0, [r4, #0] 80064bc: b2f6 uxtb r6, r6 80064be: 1ac0 subs r0, r0, r3 80064c0: 6963 ldr r3, [r4, #20] 80064c2: 4637 mov r7, r6 80064c4: 4298 cmp r0, r3 80064c6: db04 blt.n 80064d2 <__swbuf_r+0x42> 80064c8: 4621 mov r1, r4 80064ca: 4628 mov r0, r5 80064cc: f000 f928 bl 8006720 <_fflush_r> 80064d0: bb28 cbnz r0, 800651e <__swbuf_r+0x8e> 80064d2: 68a3 ldr r3, [r4, #8] 80064d4: 3001 adds r0, #1 80064d6: 3b01 subs r3, #1 80064d8: 60a3 str r3, [r4, #8] 80064da: 6823 ldr r3, [r4, #0] 80064dc: 1c5a adds r2, r3, #1 80064de: 6022 str r2, [r4, #0] 80064e0: 701e strb r6, [r3, #0] 80064e2: 6963 ldr r3, [r4, #20] 80064e4: 4298 cmp r0, r3 80064e6: d004 beq.n 80064f2 <__swbuf_r+0x62> 80064e8: 89a3 ldrh r3, [r4, #12] 80064ea: 07db lsls r3, r3, #31 80064ec: d519 bpl.n 8006522 <__swbuf_r+0x92> 80064ee: 2e0a cmp r6, #10 80064f0: d117 bne.n 8006522 <__swbuf_r+0x92> 80064f2: 4621 mov r1, r4 80064f4: 4628 mov r0, r5 80064f6: f000 f913 bl 8006720 <_fflush_r> 80064fa: b190 cbz r0, 8006522 <__swbuf_r+0x92> 80064fc: e00f b.n 800651e <__swbuf_r+0x8e> 80064fe: 4b0b ldr r3, [pc, #44] ; (800652c <__swbuf_r+0x9c>) 8006500: 429c cmp r4, r3 8006502: d101 bne.n 8006508 <__swbuf_r+0x78> 8006504: 68ac ldr r4, [r5, #8] 8006506: e7d0 b.n 80064aa <__swbuf_r+0x1a> 8006508: 4b09 ldr r3, [pc, #36] ; (8006530 <__swbuf_r+0xa0>) 800650a: 429c cmp r4, r3 800650c: bf08 it eq 800650e: 68ec ldreq r4, [r5, #12] 8006510: e7cb b.n 80064aa <__swbuf_r+0x1a> 8006512: 4621 mov r1, r4 8006514: 4628 mov r0, r5 8006516: f000 f80d bl 8006534 <__swsetup_r> 800651a: 2800 cmp r0, #0 800651c: d0cc beq.n 80064b8 <__swbuf_r+0x28> 800651e: f04f 37ff mov.w r7, #4294967295 8006522: 4638 mov r0, r7 8006524: bdf8 pop {r3, r4, r5, r6, r7, pc} 8006526: bf00 nop 8006528: 08007320 .word 0x08007320 800652c: 08007340 .word 0x08007340 8006530: 08007300 .word 0x08007300 08006534 <__swsetup_r>: 8006534: 4b32 ldr r3, [pc, #200] ; (8006600 <__swsetup_r+0xcc>) 8006536: b570 push {r4, r5, r6, lr} 8006538: 681d ldr r5, [r3, #0] 800653a: 4606 mov r6, r0 800653c: 460c mov r4, r1 800653e: b125 cbz r5, 800654a <__swsetup_r+0x16> 8006540: 69ab ldr r3, [r5, #24] 8006542: b913 cbnz r3, 800654a <__swsetup_r+0x16> 8006544: 4628 mov r0, r5 8006546: f000 f955 bl 80067f4 <__sinit> 800654a: 4b2e ldr r3, [pc, #184] ; (8006604 <__swsetup_r+0xd0>) 800654c: 429c cmp r4, r3 800654e: d10f bne.n 8006570 <__swsetup_r+0x3c> 8006550: 686c ldr r4, [r5, #4] 8006552: f9b4 300c ldrsh.w r3, [r4, #12] 8006556: b29a uxth r2, r3 8006558: 0715 lsls r5, r2, #28 800655a: d42c bmi.n 80065b6 <__swsetup_r+0x82> 800655c: 06d0 lsls r0, r2, #27 800655e: d411 bmi.n 8006584 <__swsetup_r+0x50> 8006560: 2209 movs r2, #9 8006562: 6032 str r2, [r6, #0] 8006564: f043 0340 orr.w r3, r3, #64 ; 0x40 8006568: 81a3 strh r3, [r4, #12] 800656a: f04f 30ff mov.w r0, #4294967295 800656e: bd70 pop {r4, r5, r6, pc} 8006570: 4b25 ldr r3, [pc, #148] ; (8006608 <__swsetup_r+0xd4>) 8006572: 429c cmp r4, r3 8006574: d101 bne.n 800657a <__swsetup_r+0x46> 8006576: 68ac ldr r4, [r5, #8] 8006578: e7eb b.n 8006552 <__swsetup_r+0x1e> 800657a: 4b24 ldr r3, [pc, #144] ; (800660c <__swsetup_r+0xd8>) 800657c: 429c cmp r4, r3 800657e: bf08 it eq 8006580: 68ec ldreq r4, [r5, #12] 8006582: e7e6 b.n 8006552 <__swsetup_r+0x1e> 8006584: 0751 lsls r1, r2, #29 8006586: d512 bpl.n 80065ae <__swsetup_r+0x7a> 8006588: 6b61 ldr r1, [r4, #52] ; 0x34 800658a: b141 cbz r1, 800659e <__swsetup_r+0x6a> 800658c: f104 0344 add.w r3, r4, #68 ; 0x44 8006590: 4299 cmp r1, r3 8006592: d002 beq.n 800659a <__swsetup_r+0x66> 8006594: 4630 mov r0, r6 8006596: f000 fa23 bl 80069e0 <_free_r> 800659a: 2300 movs r3, #0 800659c: 6363 str r3, [r4, #52] ; 0x34 800659e: 89a3 ldrh r3, [r4, #12] 80065a0: f023 0324 bic.w r3, r3, #36 ; 0x24 80065a4: 81a3 strh r3, [r4, #12] 80065a6: 2300 movs r3, #0 80065a8: 6063 str r3, [r4, #4] 80065aa: 6923 ldr r3, [r4, #16] 80065ac: 6023 str r3, [r4, #0] 80065ae: 89a3 ldrh r3, [r4, #12] 80065b0: f043 0308 orr.w r3, r3, #8 80065b4: 81a3 strh r3, [r4, #12] 80065b6: 6923 ldr r3, [r4, #16] 80065b8: b94b cbnz r3, 80065ce <__swsetup_r+0x9a> 80065ba: 89a3 ldrh r3, [r4, #12] 80065bc: f403 7320 and.w r3, r3, #640 ; 0x280 80065c0: f5b3 7f00 cmp.w r3, #512 ; 0x200 80065c4: d003 beq.n 80065ce <__swsetup_r+0x9a> 80065c6: 4621 mov r1, r4 80065c8: 4630 mov r0, r6 80065ca: f000 f9c1 bl 8006950 <__smakebuf_r> 80065ce: 89a2 ldrh r2, [r4, #12] 80065d0: f012 0301 ands.w r3, r2, #1 80065d4: d00c beq.n 80065f0 <__swsetup_r+0xbc> 80065d6: 2300 movs r3, #0 80065d8: 60a3 str r3, [r4, #8] 80065da: 6963 ldr r3, [r4, #20] 80065dc: 425b negs r3, r3 80065de: 61a3 str r3, [r4, #24] 80065e0: 6923 ldr r3, [r4, #16] 80065e2: b953 cbnz r3, 80065fa <__swsetup_r+0xc6> 80065e4: f9b4 300c ldrsh.w r3, [r4, #12] 80065e8: f013 0080 ands.w r0, r3, #128 ; 0x80 80065ec: d1ba bne.n 8006564 <__swsetup_r+0x30> 80065ee: bd70 pop {r4, r5, r6, pc} 80065f0: 0792 lsls r2, r2, #30 80065f2: bf58 it pl 80065f4: 6963 ldrpl r3, [r4, #20] 80065f6: 60a3 str r3, [r4, #8] 80065f8: e7f2 b.n 80065e0 <__swsetup_r+0xac> 80065fa: 2000 movs r0, #0 80065fc: e7f7 b.n 80065ee <__swsetup_r+0xba> 80065fe: bf00 nop 8006600: 2000000c .word 0x2000000c 8006604: 08007320 .word 0x08007320 8006608: 08007340 .word 0x08007340 800660c: 08007300 .word 0x08007300 08006610 <__sflush_r>: 8006610: 898a ldrh r2, [r1, #12] 8006612: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 8006616: 4605 mov r5, r0 8006618: 0710 lsls r0, r2, #28 800661a: 460c mov r4, r1 800661c: d45a bmi.n 80066d4 <__sflush_r+0xc4> 800661e: 684b ldr r3, [r1, #4] 8006620: 2b00 cmp r3, #0 8006622: dc05 bgt.n 8006630 <__sflush_r+0x20> 8006624: 6c0b ldr r3, [r1, #64] ; 0x40 8006626: 2b00 cmp r3, #0 8006628: dc02 bgt.n 8006630 <__sflush_r+0x20> 800662a: 2000 movs r0, #0 800662c: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8006630: 6ae6 ldr r6, [r4, #44] ; 0x2c 8006632: 2e00 cmp r6, #0 8006634: d0f9 beq.n 800662a <__sflush_r+0x1a> 8006636: 2300 movs r3, #0 8006638: f412 5280 ands.w r2, r2, #4096 ; 0x1000 800663c: 682f ldr r7, [r5, #0] 800663e: 602b str r3, [r5, #0] 8006640: d033 beq.n 80066aa <__sflush_r+0x9a> 8006642: 6d60 ldr r0, [r4, #84] ; 0x54 8006644: 89a3 ldrh r3, [r4, #12] 8006646: 075a lsls r2, r3, #29 8006648: d505 bpl.n 8006656 <__sflush_r+0x46> 800664a: 6863 ldr r3, [r4, #4] 800664c: 1ac0 subs r0, r0, r3 800664e: 6b63 ldr r3, [r4, #52] ; 0x34 8006650: b10b cbz r3, 8006656 <__sflush_r+0x46> 8006652: 6c23 ldr r3, [r4, #64] ; 0x40 8006654: 1ac0 subs r0, r0, r3 8006656: 2300 movs r3, #0 8006658: 4602 mov r2, r0 800665a: 6ae6 ldr r6, [r4, #44] ; 0x2c 800665c: 6a21 ldr r1, [r4, #32] 800665e: 4628 mov r0, r5 8006660: 47b0 blx r6 8006662: 1c43 adds r3, r0, #1 8006664: 89a3 ldrh r3, [r4, #12] 8006666: d106 bne.n 8006676 <__sflush_r+0x66> 8006668: 6829 ldr r1, [r5, #0] 800666a: 291d cmp r1, #29 800666c: d84b bhi.n 8006706 <__sflush_r+0xf6> 800666e: 4a2b ldr r2, [pc, #172] ; (800671c <__sflush_r+0x10c>) 8006670: 40ca lsrs r2, r1 8006672: 07d6 lsls r6, r2, #31 8006674: d547 bpl.n 8006706 <__sflush_r+0xf6> 8006676: 2200 movs r2, #0 8006678: 6062 str r2, [r4, #4] 800667a: 6922 ldr r2, [r4, #16] 800667c: 04d9 lsls r1, r3, #19 800667e: 6022 str r2, [r4, #0] 8006680: d504 bpl.n 800668c <__sflush_r+0x7c> 8006682: 1c42 adds r2, r0, #1 8006684: d101 bne.n 800668a <__sflush_r+0x7a> 8006686: 682b ldr r3, [r5, #0] 8006688: b903 cbnz r3, 800668c <__sflush_r+0x7c> 800668a: 6560 str r0, [r4, #84] ; 0x54 800668c: 6b61 ldr r1, [r4, #52] ; 0x34 800668e: 602f str r7, [r5, #0] 8006690: 2900 cmp r1, #0 8006692: d0ca beq.n 800662a <__sflush_r+0x1a> 8006694: f104 0344 add.w r3, r4, #68 ; 0x44 8006698: 4299 cmp r1, r3 800669a: d002 beq.n 80066a2 <__sflush_r+0x92> 800669c: 4628 mov r0, r5 800669e: f000 f99f bl 80069e0 <_free_r> 80066a2: 2000 movs r0, #0 80066a4: 6360 str r0, [r4, #52] ; 0x34 80066a6: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 80066aa: 6a21 ldr r1, [r4, #32] 80066ac: 2301 movs r3, #1 80066ae: 4628 mov r0, r5 80066b0: 47b0 blx r6 80066b2: 1c41 adds r1, r0, #1 80066b4: d1c6 bne.n 8006644 <__sflush_r+0x34> 80066b6: 682b ldr r3, [r5, #0] 80066b8: 2b00 cmp r3, #0 80066ba: d0c3 beq.n 8006644 <__sflush_r+0x34> 80066bc: 2b1d cmp r3, #29 80066be: d001 beq.n 80066c4 <__sflush_r+0xb4> 80066c0: 2b16 cmp r3, #22 80066c2: d101 bne.n 80066c8 <__sflush_r+0xb8> 80066c4: 602f str r7, [r5, #0] 80066c6: e7b0 b.n 800662a <__sflush_r+0x1a> 80066c8: 89a3 ldrh r3, [r4, #12] 80066ca: f043 0340 orr.w r3, r3, #64 ; 0x40 80066ce: 81a3 strh r3, [r4, #12] 80066d0: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 80066d4: 690f ldr r7, [r1, #16] 80066d6: 2f00 cmp r7, #0 80066d8: d0a7 beq.n 800662a <__sflush_r+0x1a> 80066da: 0793 lsls r3, r2, #30 80066dc: bf18 it ne 80066de: 2300 movne r3, #0 80066e0: 680e ldr r6, [r1, #0] 80066e2: bf08 it eq 80066e4: 694b ldreq r3, [r1, #20] 80066e6: eba6 0807 sub.w r8, r6, r7 80066ea: 600f str r7, [r1, #0] 80066ec: 608b str r3, [r1, #8] 80066ee: f1b8 0f00 cmp.w r8, #0 80066f2: dd9a ble.n 800662a <__sflush_r+0x1a> 80066f4: 4643 mov r3, r8 80066f6: 463a mov r2, r7 80066f8: 6a21 ldr r1, [r4, #32] 80066fa: 4628 mov r0, r5 80066fc: 6aa6 ldr r6, [r4, #40] ; 0x28 80066fe: 47b0 blx r6 8006700: 2800 cmp r0, #0 8006702: dc07 bgt.n 8006714 <__sflush_r+0x104> 8006704: 89a3 ldrh r3, [r4, #12] 8006706: f043 0340 orr.w r3, r3, #64 ; 0x40 800670a: 81a3 strh r3, [r4, #12] 800670c: f04f 30ff mov.w r0, #4294967295 8006710: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8006714: 4407 add r7, r0 8006716: eba8 0800 sub.w r8, r8, r0 800671a: e7e8 b.n 80066ee <__sflush_r+0xde> 800671c: 20400001 .word 0x20400001 08006720 <_fflush_r>: 8006720: b538 push {r3, r4, r5, lr} 8006722: 690b ldr r3, [r1, #16] 8006724: 4605 mov r5, r0 8006726: 460c mov r4, r1 8006728: b1db cbz r3, 8006762 <_fflush_r+0x42> 800672a: b118 cbz r0, 8006734 <_fflush_r+0x14> 800672c: 6983 ldr r3, [r0, #24] 800672e: b90b cbnz r3, 8006734 <_fflush_r+0x14> 8006730: f000 f860 bl 80067f4 <__sinit> 8006734: 4b0c ldr r3, [pc, #48] ; (8006768 <_fflush_r+0x48>) 8006736: 429c cmp r4, r3 8006738: d109 bne.n 800674e <_fflush_r+0x2e> 800673a: 686c ldr r4, [r5, #4] 800673c: f9b4 300c ldrsh.w r3, [r4, #12] 8006740: b17b cbz r3, 8006762 <_fflush_r+0x42> 8006742: 4621 mov r1, r4 8006744: 4628 mov r0, r5 8006746: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 800674a: f7ff bf61 b.w 8006610 <__sflush_r> 800674e: 4b07 ldr r3, [pc, #28] ; (800676c <_fflush_r+0x4c>) 8006750: 429c cmp r4, r3 8006752: d101 bne.n 8006758 <_fflush_r+0x38> 8006754: 68ac ldr r4, [r5, #8] 8006756: e7f1 b.n 800673c <_fflush_r+0x1c> 8006758: 4b05 ldr r3, [pc, #20] ; (8006770 <_fflush_r+0x50>) 800675a: 429c cmp r4, r3 800675c: bf08 it eq 800675e: 68ec ldreq r4, [r5, #12] 8006760: e7ec b.n 800673c <_fflush_r+0x1c> 8006762: 2000 movs r0, #0 8006764: bd38 pop {r3, r4, r5, pc} 8006766: bf00 nop 8006768: 08007320 .word 0x08007320 800676c: 08007340 .word 0x08007340 8006770: 08007300 .word 0x08007300 08006774 <_cleanup_r>: 8006774: 4901 ldr r1, [pc, #4] ; (800677c <_cleanup_r+0x8>) 8006776: f000 b8a9 b.w 80068cc <_fwalk_reent> 800677a: bf00 nop 800677c: 08006721 .word 0x08006721 08006780 : 8006780: 2300 movs r3, #0 8006782: b510 push {r4, lr} 8006784: 4604 mov r4, r0 8006786: 6003 str r3, [r0, #0] 8006788: 6043 str r3, [r0, #4] 800678a: 6083 str r3, [r0, #8] 800678c: 8181 strh r1, [r0, #12] 800678e: 6643 str r3, [r0, #100] ; 0x64 8006790: 81c2 strh r2, [r0, #14] 8006792: 6103 str r3, [r0, #16] 8006794: 6143 str r3, [r0, #20] 8006796: 6183 str r3, [r0, #24] 8006798: 4619 mov r1, r3 800679a: 2208 movs r2, #8 800679c: 305c adds r0, #92 ; 0x5c 800679e: f7ff fd3d bl 800621c 80067a2: 4b05 ldr r3, [pc, #20] ; (80067b8 ) 80067a4: 6224 str r4, [r4, #32] 80067a6: 6263 str r3, [r4, #36] ; 0x24 80067a8: 4b04 ldr r3, [pc, #16] ; (80067bc ) 80067aa: 62a3 str r3, [r4, #40] ; 0x28 80067ac: 4b04 ldr r3, [pc, #16] ; (80067c0 ) 80067ae: 62e3 str r3, [r4, #44] ; 0x2c 80067b0: 4b04 ldr r3, [pc, #16] ; (80067c4 ) 80067b2: 6323 str r3, [r4, #48] ; 0x30 80067b4: bd10 pop {r4, pc} 80067b6: bf00 nop 80067b8: 08007101 .word 0x08007101 80067bc: 08007123 .word 0x08007123 80067c0: 0800715b .word 0x0800715b 80067c4: 0800717f .word 0x0800717f 080067c8 <__sfmoreglue>: 80067c8: b570 push {r4, r5, r6, lr} 80067ca: 2568 movs r5, #104 ; 0x68 80067cc: 1e4a subs r2, r1, #1 80067ce: 4355 muls r5, r2 80067d0: 460e mov r6, r1 80067d2: f105 0174 add.w r1, r5, #116 ; 0x74 80067d6: f000 f94f bl 8006a78 <_malloc_r> 80067da: 4604 mov r4, r0 80067dc: b140 cbz r0, 80067f0 <__sfmoreglue+0x28> 80067de: 2100 movs r1, #0 80067e0: e880 0042 stmia.w r0, {r1, r6} 80067e4: 300c adds r0, #12 80067e6: 60a0 str r0, [r4, #8] 80067e8: f105 0268 add.w r2, r5, #104 ; 0x68 80067ec: f7ff fd16 bl 800621c 80067f0: 4620 mov r0, r4 80067f2: bd70 pop {r4, r5, r6, pc} 080067f4 <__sinit>: 80067f4: 6983 ldr r3, [r0, #24] 80067f6: b510 push {r4, lr} 80067f8: 4604 mov r4, r0 80067fa: bb33 cbnz r3, 800684a <__sinit+0x56> 80067fc: 6483 str r3, [r0, #72] ; 0x48 80067fe: 64c3 str r3, [r0, #76] ; 0x4c 8006800: 6503 str r3, [r0, #80] ; 0x50 8006802: 4b12 ldr r3, [pc, #72] ; (800684c <__sinit+0x58>) 8006804: 4a12 ldr r2, [pc, #72] ; (8006850 <__sinit+0x5c>) 8006806: 681b ldr r3, [r3, #0] 8006808: 6282 str r2, [r0, #40] ; 0x28 800680a: 4298 cmp r0, r3 800680c: bf04 itt eq 800680e: 2301 moveq r3, #1 8006810: 6183 streq r3, [r0, #24] 8006812: f000 f81f bl 8006854 <__sfp> 8006816: 6060 str r0, [r4, #4] 8006818: 4620 mov r0, r4 800681a: f000 f81b bl 8006854 <__sfp> 800681e: 60a0 str r0, [r4, #8] 8006820: 4620 mov r0, r4 8006822: f000 f817 bl 8006854 <__sfp> 8006826: 2200 movs r2, #0 8006828: 60e0 str r0, [r4, #12] 800682a: 2104 movs r1, #4 800682c: 6860 ldr r0, [r4, #4] 800682e: f7ff ffa7 bl 8006780 8006832: 2201 movs r2, #1 8006834: 2109 movs r1, #9 8006836: 68a0 ldr r0, [r4, #8] 8006838: f7ff ffa2 bl 8006780 800683c: 2202 movs r2, #2 800683e: 2112 movs r1, #18 8006840: 68e0 ldr r0, [r4, #12] 8006842: f7ff ff9d bl 8006780 8006846: 2301 movs r3, #1 8006848: 61a3 str r3, [r4, #24] 800684a: bd10 pop {r4, pc} 800684c: 080072fc .word 0x080072fc 8006850: 08006775 .word 0x08006775 08006854 <__sfp>: 8006854: b5f8 push {r3, r4, r5, r6, r7, lr} 8006856: 4b1c ldr r3, [pc, #112] ; (80068c8 <__sfp+0x74>) 8006858: 4607 mov r7, r0 800685a: 681e ldr r6, [r3, #0] 800685c: 69b3 ldr r3, [r6, #24] 800685e: b913 cbnz r3, 8006866 <__sfp+0x12> 8006860: 4630 mov r0, r6 8006862: f7ff ffc7 bl 80067f4 <__sinit> 8006866: 3648 adds r6, #72 ; 0x48 8006868: 68b4 ldr r4, [r6, #8] 800686a: 6873 ldr r3, [r6, #4] 800686c: 3b01 subs r3, #1 800686e: d503 bpl.n 8006878 <__sfp+0x24> 8006870: 6833 ldr r3, [r6, #0] 8006872: b133 cbz r3, 8006882 <__sfp+0x2e> 8006874: 6836 ldr r6, [r6, #0] 8006876: e7f7 b.n 8006868 <__sfp+0x14> 8006878: f9b4 500c ldrsh.w r5, [r4, #12] 800687c: b16d cbz r5, 800689a <__sfp+0x46> 800687e: 3468 adds r4, #104 ; 0x68 8006880: e7f4 b.n 800686c <__sfp+0x18> 8006882: 2104 movs r1, #4 8006884: 4638 mov r0, r7 8006886: f7ff ff9f bl 80067c8 <__sfmoreglue> 800688a: 6030 str r0, [r6, #0] 800688c: 2800 cmp r0, #0 800688e: d1f1 bne.n 8006874 <__sfp+0x20> 8006890: 230c movs r3, #12 8006892: 4604 mov r4, r0 8006894: 603b str r3, [r7, #0] 8006896: 4620 mov r0, r4 8006898: bdf8 pop {r3, r4, r5, r6, r7, pc} 800689a: f64f 73ff movw r3, #65535 ; 0xffff 800689e: 81e3 strh r3, [r4, #14] 80068a0: 2301 movs r3, #1 80068a2: 6665 str r5, [r4, #100] ; 0x64 80068a4: 81a3 strh r3, [r4, #12] 80068a6: 6025 str r5, [r4, #0] 80068a8: 60a5 str r5, [r4, #8] 80068aa: 6065 str r5, [r4, #4] 80068ac: 6125 str r5, [r4, #16] 80068ae: 6165 str r5, [r4, #20] 80068b0: 61a5 str r5, [r4, #24] 80068b2: 2208 movs r2, #8 80068b4: 4629 mov r1, r5 80068b6: f104 005c add.w r0, r4, #92 ; 0x5c 80068ba: f7ff fcaf bl 800621c 80068be: 6365 str r5, [r4, #52] ; 0x34 80068c0: 63a5 str r5, [r4, #56] ; 0x38 80068c2: 64a5 str r5, [r4, #72] ; 0x48 80068c4: 64e5 str r5, [r4, #76] ; 0x4c 80068c6: e7e6 b.n 8006896 <__sfp+0x42> 80068c8: 080072fc .word 0x080072fc 080068cc <_fwalk_reent>: 80068cc: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 80068d0: 4680 mov r8, r0 80068d2: 4689 mov r9, r1 80068d4: 2600 movs r6, #0 80068d6: f100 0448 add.w r4, r0, #72 ; 0x48 80068da: b914 cbnz r4, 80068e2 <_fwalk_reent+0x16> 80068dc: 4630 mov r0, r6 80068de: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 80068e2: 68a5 ldr r5, [r4, #8] 80068e4: 6867 ldr r7, [r4, #4] 80068e6: 3f01 subs r7, #1 80068e8: d501 bpl.n 80068ee <_fwalk_reent+0x22> 80068ea: 6824 ldr r4, [r4, #0] 80068ec: e7f5 b.n 80068da <_fwalk_reent+0xe> 80068ee: 89ab ldrh r3, [r5, #12] 80068f0: 2b01 cmp r3, #1 80068f2: d907 bls.n 8006904 <_fwalk_reent+0x38> 80068f4: f9b5 300e ldrsh.w r3, [r5, #14] 80068f8: 3301 adds r3, #1 80068fa: d003 beq.n 8006904 <_fwalk_reent+0x38> 80068fc: 4629 mov r1, r5 80068fe: 4640 mov r0, r8 8006900: 47c8 blx r9 8006902: 4306 orrs r6, r0 8006904: 3568 adds r5, #104 ; 0x68 8006906: e7ee b.n 80068e6 <_fwalk_reent+0x1a> 08006908 <__swhatbuf_r>: 8006908: b570 push {r4, r5, r6, lr} 800690a: 460e mov r6, r1 800690c: f9b1 100e ldrsh.w r1, [r1, #14] 8006910: b090 sub sp, #64 ; 0x40 8006912: 2900 cmp r1, #0 8006914: 4614 mov r4, r2 8006916: 461d mov r5, r3 8006918: da07 bge.n 800692a <__swhatbuf_r+0x22> 800691a: 2300 movs r3, #0 800691c: 602b str r3, [r5, #0] 800691e: 89b3 ldrh r3, [r6, #12] 8006920: 061a lsls r2, r3, #24 8006922: d410 bmi.n 8006946 <__swhatbuf_r+0x3e> 8006924: f44f 6380 mov.w r3, #1024 ; 0x400 8006928: e00e b.n 8006948 <__swhatbuf_r+0x40> 800692a: aa01 add r2, sp, #4 800692c: f000 fc4e bl 80071cc <_fstat_r> 8006930: 2800 cmp r0, #0 8006932: dbf2 blt.n 800691a <__swhatbuf_r+0x12> 8006934: 9a02 ldr r2, [sp, #8] 8006936: f402 4270 and.w r2, r2, #61440 ; 0xf000 800693a: f5a2 5300 sub.w r3, r2, #8192 ; 0x2000 800693e: 425a negs r2, r3 8006940: 415a adcs r2, r3 8006942: 602a str r2, [r5, #0] 8006944: e7ee b.n 8006924 <__swhatbuf_r+0x1c> 8006946: 2340 movs r3, #64 ; 0x40 8006948: 2000 movs r0, #0 800694a: 6023 str r3, [r4, #0] 800694c: b010 add sp, #64 ; 0x40 800694e: bd70 pop {r4, r5, r6, pc} 08006950 <__smakebuf_r>: 8006950: 898b ldrh r3, [r1, #12] 8006952: b573 push {r0, r1, r4, r5, r6, lr} 8006954: 079d lsls r5, r3, #30 8006956: 4606 mov r6, r0 8006958: 460c mov r4, r1 800695a: d507 bpl.n 800696c <__smakebuf_r+0x1c> 800695c: f104 0347 add.w r3, r4, #71 ; 0x47 8006960: 6023 str r3, [r4, #0] 8006962: 6123 str r3, [r4, #16] 8006964: 2301 movs r3, #1 8006966: 6163 str r3, [r4, #20] 8006968: b002 add sp, #8 800696a: bd70 pop {r4, r5, r6, pc} 800696c: ab01 add r3, sp, #4 800696e: 466a mov r2, sp 8006970: f7ff ffca bl 8006908 <__swhatbuf_r> 8006974: 9900 ldr r1, [sp, #0] 8006976: 4605 mov r5, r0 8006978: 4630 mov r0, r6 800697a: f000 f87d bl 8006a78 <_malloc_r> 800697e: b948 cbnz r0, 8006994 <__smakebuf_r+0x44> 8006980: f9b4 300c ldrsh.w r3, [r4, #12] 8006984: 059a lsls r2, r3, #22 8006986: d4ef bmi.n 8006968 <__smakebuf_r+0x18> 8006988: f023 0303 bic.w r3, r3, #3 800698c: f043 0302 orr.w r3, r3, #2 8006990: 81a3 strh r3, [r4, #12] 8006992: e7e3 b.n 800695c <__smakebuf_r+0xc> 8006994: 4b0d ldr r3, [pc, #52] ; (80069cc <__smakebuf_r+0x7c>) 8006996: 62b3 str r3, [r6, #40] ; 0x28 8006998: 89a3 ldrh r3, [r4, #12] 800699a: 6020 str r0, [r4, #0] 800699c: f043 0380 orr.w r3, r3, #128 ; 0x80 80069a0: 81a3 strh r3, [r4, #12] 80069a2: 9b00 ldr r3, [sp, #0] 80069a4: 6120 str r0, [r4, #16] 80069a6: 6163 str r3, [r4, #20] 80069a8: 9b01 ldr r3, [sp, #4] 80069aa: b15b cbz r3, 80069c4 <__smakebuf_r+0x74> 80069ac: f9b4 100e ldrsh.w r1, [r4, #14] 80069b0: 4630 mov r0, r6 80069b2: f000 fc1d bl 80071f0 <_isatty_r> 80069b6: b128 cbz r0, 80069c4 <__smakebuf_r+0x74> 80069b8: 89a3 ldrh r3, [r4, #12] 80069ba: f023 0303 bic.w r3, r3, #3 80069be: f043 0301 orr.w r3, r3, #1 80069c2: 81a3 strh r3, [r4, #12] 80069c4: 89a3 ldrh r3, [r4, #12] 80069c6: 431d orrs r5, r3 80069c8: 81a5 strh r5, [r4, #12] 80069ca: e7cd b.n 8006968 <__smakebuf_r+0x18> 80069cc: 08006775 .word 0x08006775 080069d0 : 80069d0: 4b02 ldr r3, [pc, #8] ; (80069dc ) 80069d2: 4601 mov r1, r0 80069d4: 6818 ldr r0, [r3, #0] 80069d6: f000 b84f b.w 8006a78 <_malloc_r> 80069da: bf00 nop 80069dc: 2000000c .word 0x2000000c 080069e0 <_free_r>: 80069e0: b538 push {r3, r4, r5, lr} 80069e2: 4605 mov r5, r0 80069e4: 2900 cmp r1, #0 80069e6: d043 beq.n 8006a70 <_free_r+0x90> 80069e8: f851 3c04 ldr.w r3, [r1, #-4] 80069ec: 1f0c subs r4, r1, #4 80069ee: 2b00 cmp r3, #0 80069f0: bfb8 it lt 80069f2: 18e4 addlt r4, r4, r3 80069f4: f000 fc2c bl 8007250 <__malloc_lock> 80069f8: 4a1e ldr r2, [pc, #120] ; (8006a74 <_free_r+0x94>) 80069fa: 6813 ldr r3, [r2, #0] 80069fc: 4610 mov r0, r2 80069fe: b933 cbnz r3, 8006a0e <_free_r+0x2e> 8006a00: 6063 str r3, [r4, #4] 8006a02: 6014 str r4, [r2, #0] 8006a04: 4628 mov r0, r5 8006a06: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 8006a0a: f000 bc22 b.w 8007252 <__malloc_unlock> 8006a0e: 42a3 cmp r3, r4 8006a10: d90b bls.n 8006a2a <_free_r+0x4a> 8006a12: 6821 ldr r1, [r4, #0] 8006a14: 1862 adds r2, r4, r1 8006a16: 4293 cmp r3, r2 8006a18: bf01 itttt eq 8006a1a: 681a ldreq r2, [r3, #0] 8006a1c: 685b ldreq r3, [r3, #4] 8006a1e: 1852 addeq r2, r2, r1 8006a20: 6022 streq r2, [r4, #0] 8006a22: 6063 str r3, [r4, #4] 8006a24: 6004 str r4, [r0, #0] 8006a26: e7ed b.n 8006a04 <_free_r+0x24> 8006a28: 4613 mov r3, r2 8006a2a: 685a ldr r2, [r3, #4] 8006a2c: b10a cbz r2, 8006a32 <_free_r+0x52> 8006a2e: 42a2 cmp r2, r4 8006a30: d9fa bls.n 8006a28 <_free_r+0x48> 8006a32: 6819 ldr r1, [r3, #0] 8006a34: 1858 adds r0, r3, r1 8006a36: 42a0 cmp r0, r4 8006a38: d10b bne.n 8006a52 <_free_r+0x72> 8006a3a: 6820 ldr r0, [r4, #0] 8006a3c: 4401 add r1, r0 8006a3e: 1858 adds r0, r3, r1 8006a40: 4282 cmp r2, r0 8006a42: 6019 str r1, [r3, #0] 8006a44: d1de bne.n 8006a04 <_free_r+0x24> 8006a46: 6810 ldr r0, [r2, #0] 8006a48: 6852 ldr r2, [r2, #4] 8006a4a: 4401 add r1, r0 8006a4c: 6019 str r1, [r3, #0] 8006a4e: 605a str r2, [r3, #4] 8006a50: e7d8 b.n 8006a04 <_free_r+0x24> 8006a52: d902 bls.n 8006a5a <_free_r+0x7a> 8006a54: 230c movs r3, #12 8006a56: 602b str r3, [r5, #0] 8006a58: e7d4 b.n 8006a04 <_free_r+0x24> 8006a5a: 6820 ldr r0, [r4, #0] 8006a5c: 1821 adds r1, r4, r0 8006a5e: 428a cmp r2, r1 8006a60: bf01 itttt eq 8006a62: 6811 ldreq r1, [r2, #0] 8006a64: 6852 ldreq r2, [r2, #4] 8006a66: 1809 addeq r1, r1, r0 8006a68: 6021 streq r1, [r4, #0] 8006a6a: 6062 str r2, [r4, #4] 8006a6c: 605c str r4, [r3, #4] 8006a6e: e7c9 b.n 8006a04 <_free_r+0x24> 8006a70: bd38 pop {r3, r4, r5, pc} 8006a72: bf00 nop 8006a74: 20000498 .word 0x20000498 08006a78 <_malloc_r>: 8006a78: b570 push {r4, r5, r6, lr} 8006a7a: 1ccd adds r5, r1, #3 8006a7c: f025 0503 bic.w r5, r5, #3 8006a80: 3508 adds r5, #8 8006a82: 2d0c cmp r5, #12 8006a84: bf38 it cc 8006a86: 250c movcc r5, #12 8006a88: 2d00 cmp r5, #0 8006a8a: 4606 mov r6, r0 8006a8c: db01 blt.n 8006a92 <_malloc_r+0x1a> 8006a8e: 42a9 cmp r1, r5 8006a90: d903 bls.n 8006a9a <_malloc_r+0x22> 8006a92: 230c movs r3, #12 8006a94: 6033 str r3, [r6, #0] 8006a96: 2000 movs r0, #0 8006a98: bd70 pop {r4, r5, r6, pc} 8006a9a: f000 fbd9 bl 8007250 <__malloc_lock> 8006a9e: 4a23 ldr r2, [pc, #140] ; (8006b2c <_malloc_r+0xb4>) 8006aa0: 6814 ldr r4, [r2, #0] 8006aa2: 4621 mov r1, r4 8006aa4: b991 cbnz r1, 8006acc <_malloc_r+0x54> 8006aa6: 4c22 ldr r4, [pc, #136] ; (8006b30 <_malloc_r+0xb8>) 8006aa8: 6823 ldr r3, [r4, #0] 8006aaa: b91b cbnz r3, 8006ab4 <_malloc_r+0x3c> 8006aac: 4630 mov r0, r6 8006aae: f000 fb17 bl 80070e0 <_sbrk_r> 8006ab2: 6020 str r0, [r4, #0] 8006ab4: 4629 mov r1, r5 8006ab6: 4630 mov r0, r6 8006ab8: f000 fb12 bl 80070e0 <_sbrk_r> 8006abc: 1c43 adds r3, r0, #1 8006abe: d126 bne.n 8006b0e <_malloc_r+0x96> 8006ac0: 230c movs r3, #12 8006ac2: 4630 mov r0, r6 8006ac4: 6033 str r3, [r6, #0] 8006ac6: f000 fbc4 bl 8007252 <__malloc_unlock> 8006aca: e7e4 b.n 8006a96 <_malloc_r+0x1e> 8006acc: 680b ldr r3, [r1, #0] 8006ace: 1b5b subs r3, r3, r5 8006ad0: d41a bmi.n 8006b08 <_malloc_r+0x90> 8006ad2: 2b0b cmp r3, #11 8006ad4: d90f bls.n 8006af6 <_malloc_r+0x7e> 8006ad6: 600b str r3, [r1, #0] 8006ad8: 18cc adds r4, r1, r3 8006ada: 50cd str r5, [r1, r3] 8006adc: 4630 mov r0, r6 8006ade: f000 fbb8 bl 8007252 <__malloc_unlock> 8006ae2: f104 000b add.w r0, r4, #11 8006ae6: 1d23 adds r3, r4, #4 8006ae8: f020 0007 bic.w r0, r0, #7 8006aec: 1ac3 subs r3, r0, r3 8006aee: d01b beq.n 8006b28 <_malloc_r+0xb0> 8006af0: 425a negs r2, r3 8006af2: 50e2 str r2, [r4, r3] 8006af4: bd70 pop {r4, r5, r6, pc} 8006af6: 428c cmp r4, r1 8006af8: bf0b itete eq 8006afa: 6863 ldreq r3, [r4, #4] 8006afc: 684b ldrne r3, [r1, #4] 8006afe: 6013 streq r3, [r2, #0] 8006b00: 6063 strne r3, [r4, #4] 8006b02: bf18 it ne 8006b04: 460c movne r4, r1 8006b06: e7e9 b.n 8006adc <_malloc_r+0x64> 8006b08: 460c mov r4, r1 8006b0a: 6849 ldr r1, [r1, #4] 8006b0c: e7ca b.n 8006aa4 <_malloc_r+0x2c> 8006b0e: 1cc4 adds r4, r0, #3 8006b10: f024 0403 bic.w r4, r4, #3 8006b14: 42a0 cmp r0, r4 8006b16: d005 beq.n 8006b24 <_malloc_r+0xac> 8006b18: 1a21 subs r1, r4, r0 8006b1a: 4630 mov r0, r6 8006b1c: f000 fae0 bl 80070e0 <_sbrk_r> 8006b20: 3001 adds r0, #1 8006b22: d0cd beq.n 8006ac0 <_malloc_r+0x48> 8006b24: 6025 str r5, [r4, #0] 8006b26: e7d9 b.n 8006adc <_malloc_r+0x64> 8006b28: bd70 pop {r4, r5, r6, pc} 8006b2a: bf00 nop 8006b2c: 20000498 .word 0x20000498 8006b30: 2000049c .word 0x2000049c 08006b34 <__sfputc_r>: 8006b34: 6893 ldr r3, [r2, #8] 8006b36: b410 push {r4} 8006b38: 3b01 subs r3, #1 8006b3a: 2b00 cmp r3, #0 8006b3c: 6093 str r3, [r2, #8] 8006b3e: da08 bge.n 8006b52 <__sfputc_r+0x1e> 8006b40: 6994 ldr r4, [r2, #24] 8006b42: 42a3 cmp r3, r4 8006b44: db02 blt.n 8006b4c <__sfputc_r+0x18> 8006b46: b2cb uxtb r3, r1 8006b48: 2b0a cmp r3, #10 8006b4a: d102 bne.n 8006b52 <__sfputc_r+0x1e> 8006b4c: bc10 pop {r4} 8006b4e: f7ff bc9f b.w 8006490 <__swbuf_r> 8006b52: 6813 ldr r3, [r2, #0] 8006b54: 1c58 adds r0, r3, #1 8006b56: 6010 str r0, [r2, #0] 8006b58: 7019 strb r1, [r3, #0] 8006b5a: b2c8 uxtb r0, r1 8006b5c: bc10 pop {r4} 8006b5e: 4770 bx lr 08006b60 <__sfputs_r>: 8006b60: b5f8 push {r3, r4, r5, r6, r7, lr} 8006b62: 4606 mov r6, r0 8006b64: 460f mov r7, r1 8006b66: 4614 mov r4, r2 8006b68: 18d5 adds r5, r2, r3 8006b6a: 42ac cmp r4, r5 8006b6c: d101 bne.n 8006b72 <__sfputs_r+0x12> 8006b6e: 2000 movs r0, #0 8006b70: e007 b.n 8006b82 <__sfputs_r+0x22> 8006b72: 463a mov r2, r7 8006b74: f814 1b01 ldrb.w r1, [r4], #1 8006b78: 4630 mov r0, r6 8006b7a: f7ff ffdb bl 8006b34 <__sfputc_r> 8006b7e: 1c43 adds r3, r0, #1 8006b80: d1f3 bne.n 8006b6a <__sfputs_r+0xa> 8006b82: bdf8 pop {r3, r4, r5, r6, r7, pc} 08006b84 <_vfiprintf_r>: 8006b84: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8006b88: b09d sub sp, #116 ; 0x74 8006b8a: 460c mov r4, r1 8006b8c: 4617 mov r7, r2 8006b8e: 9303 str r3, [sp, #12] 8006b90: 4606 mov r6, r0 8006b92: b118 cbz r0, 8006b9c <_vfiprintf_r+0x18> 8006b94: 6983 ldr r3, [r0, #24] 8006b96: b90b cbnz r3, 8006b9c <_vfiprintf_r+0x18> 8006b98: f7ff fe2c bl 80067f4 <__sinit> 8006b9c: 4b7c ldr r3, [pc, #496] ; (8006d90 <_vfiprintf_r+0x20c>) 8006b9e: 429c cmp r4, r3 8006ba0: d157 bne.n 8006c52 <_vfiprintf_r+0xce> 8006ba2: 6874 ldr r4, [r6, #4] 8006ba4: 89a3 ldrh r3, [r4, #12] 8006ba6: 0718 lsls r0, r3, #28 8006ba8: d55d bpl.n 8006c66 <_vfiprintf_r+0xe2> 8006baa: 6923 ldr r3, [r4, #16] 8006bac: 2b00 cmp r3, #0 8006bae: d05a beq.n 8006c66 <_vfiprintf_r+0xe2> 8006bb0: 2300 movs r3, #0 8006bb2: 9309 str r3, [sp, #36] ; 0x24 8006bb4: 2320 movs r3, #32 8006bb6: f88d 3029 strb.w r3, [sp, #41] ; 0x29 8006bba: 2330 movs r3, #48 ; 0x30 8006bbc: f04f 0b01 mov.w fp, #1 8006bc0: f88d 302a strb.w r3, [sp, #42] ; 0x2a 8006bc4: 46b8 mov r8, r7 8006bc6: 4645 mov r5, r8 8006bc8: f815 3b01 ldrb.w r3, [r5], #1 8006bcc: 2b00 cmp r3, #0 8006bce: d155 bne.n 8006c7c <_vfiprintf_r+0xf8> 8006bd0: ebb8 0a07 subs.w sl, r8, r7 8006bd4: d00b beq.n 8006bee <_vfiprintf_r+0x6a> 8006bd6: 4653 mov r3, sl 8006bd8: 463a mov r2, r7 8006bda: 4621 mov r1, r4 8006bdc: 4630 mov r0, r6 8006bde: f7ff ffbf bl 8006b60 <__sfputs_r> 8006be2: 3001 adds r0, #1 8006be4: f000 80c4 beq.w 8006d70 <_vfiprintf_r+0x1ec> 8006be8: 9b09 ldr r3, [sp, #36] ; 0x24 8006bea: 4453 add r3, sl 8006bec: 9309 str r3, [sp, #36] ; 0x24 8006bee: f898 3000 ldrb.w r3, [r8] 8006bf2: 2b00 cmp r3, #0 8006bf4: f000 80bc beq.w 8006d70 <_vfiprintf_r+0x1ec> 8006bf8: 2300 movs r3, #0 8006bfa: f04f 32ff mov.w r2, #4294967295 8006bfe: 9304 str r3, [sp, #16] 8006c00: 9307 str r3, [sp, #28] 8006c02: 9205 str r2, [sp, #20] 8006c04: 9306 str r3, [sp, #24] 8006c06: f88d 3053 strb.w r3, [sp, #83] ; 0x53 8006c0a: 931a str r3, [sp, #104] ; 0x68 8006c0c: 2205 movs r2, #5 8006c0e: 7829 ldrb r1, [r5, #0] 8006c10: 4860 ldr r0, [pc, #384] ; (8006d94 <_vfiprintf_r+0x210>) 8006c12: f000 fb0f bl 8007234 8006c16: f105 0801 add.w r8, r5, #1 8006c1a: 9b04 ldr r3, [sp, #16] 8006c1c: 2800 cmp r0, #0 8006c1e: d131 bne.n 8006c84 <_vfiprintf_r+0x100> 8006c20: 06d9 lsls r1, r3, #27 8006c22: bf44 itt mi 8006c24: 2220 movmi r2, #32 8006c26: f88d 2053 strbmi.w r2, [sp, #83] ; 0x53 8006c2a: 071a lsls r2, r3, #28 8006c2c: bf44 itt mi 8006c2e: 222b movmi r2, #43 ; 0x2b 8006c30: f88d 2053 strbmi.w r2, [sp, #83] ; 0x53 8006c34: 782a ldrb r2, [r5, #0] 8006c36: 2a2a cmp r2, #42 ; 0x2a 8006c38: d02c beq.n 8006c94 <_vfiprintf_r+0x110> 8006c3a: 2100 movs r1, #0 8006c3c: 200a movs r0, #10 8006c3e: 9a07 ldr r2, [sp, #28] 8006c40: 46a8 mov r8, r5 8006c42: f898 3000 ldrb.w r3, [r8] 8006c46: 3501 adds r5, #1 8006c48: 3b30 subs r3, #48 ; 0x30 8006c4a: 2b09 cmp r3, #9 8006c4c: d96d bls.n 8006d2a <_vfiprintf_r+0x1a6> 8006c4e: b371 cbz r1, 8006cae <_vfiprintf_r+0x12a> 8006c50: e026 b.n 8006ca0 <_vfiprintf_r+0x11c> 8006c52: 4b51 ldr r3, [pc, #324] ; (8006d98 <_vfiprintf_r+0x214>) 8006c54: 429c cmp r4, r3 8006c56: d101 bne.n 8006c5c <_vfiprintf_r+0xd8> 8006c58: 68b4 ldr r4, [r6, #8] 8006c5a: e7a3 b.n 8006ba4 <_vfiprintf_r+0x20> 8006c5c: 4b4f ldr r3, [pc, #316] ; (8006d9c <_vfiprintf_r+0x218>) 8006c5e: 429c cmp r4, r3 8006c60: bf08 it eq 8006c62: 68f4 ldreq r4, [r6, #12] 8006c64: e79e b.n 8006ba4 <_vfiprintf_r+0x20> 8006c66: 4621 mov r1, r4 8006c68: 4630 mov r0, r6 8006c6a: f7ff fc63 bl 8006534 <__swsetup_r> 8006c6e: 2800 cmp r0, #0 8006c70: d09e beq.n 8006bb0 <_vfiprintf_r+0x2c> 8006c72: f04f 30ff mov.w r0, #4294967295 8006c76: b01d add sp, #116 ; 0x74 8006c78: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8006c7c: 2b25 cmp r3, #37 ; 0x25 8006c7e: d0a7 beq.n 8006bd0 <_vfiprintf_r+0x4c> 8006c80: 46a8 mov r8, r5 8006c82: e7a0 b.n 8006bc6 <_vfiprintf_r+0x42> 8006c84: 4a43 ldr r2, [pc, #268] ; (8006d94 <_vfiprintf_r+0x210>) 8006c86: 4645 mov r5, r8 8006c88: 1a80 subs r0, r0, r2 8006c8a: fa0b f000 lsl.w r0, fp, r0 8006c8e: 4318 orrs r0, r3 8006c90: 9004 str r0, [sp, #16] 8006c92: e7bb b.n 8006c0c <_vfiprintf_r+0x88> 8006c94: 9a03 ldr r2, [sp, #12] 8006c96: 1d11 adds r1, r2, #4 8006c98: 6812 ldr r2, [r2, #0] 8006c9a: 9103 str r1, [sp, #12] 8006c9c: 2a00 cmp r2, #0 8006c9e: db01 blt.n 8006ca4 <_vfiprintf_r+0x120> 8006ca0: 9207 str r2, [sp, #28] 8006ca2: e004 b.n 8006cae <_vfiprintf_r+0x12a> 8006ca4: 4252 negs r2, r2 8006ca6: f043 0302 orr.w r3, r3, #2 8006caa: 9207 str r2, [sp, #28] 8006cac: 9304 str r3, [sp, #16] 8006cae: f898 3000 ldrb.w r3, [r8] 8006cb2: 2b2e cmp r3, #46 ; 0x2e 8006cb4: d110 bne.n 8006cd8 <_vfiprintf_r+0x154> 8006cb6: f898 3001 ldrb.w r3, [r8, #1] 8006cba: f108 0101 add.w r1, r8, #1 8006cbe: 2b2a cmp r3, #42 ; 0x2a 8006cc0: d137 bne.n 8006d32 <_vfiprintf_r+0x1ae> 8006cc2: 9b03 ldr r3, [sp, #12] 8006cc4: f108 0802 add.w r8, r8, #2 8006cc8: 1d1a adds r2, r3, #4 8006cca: 681b ldr r3, [r3, #0] 8006ccc: 9203 str r2, [sp, #12] 8006cce: 2b00 cmp r3, #0 8006cd0: bfb8 it lt 8006cd2: f04f 33ff movlt.w r3, #4294967295 8006cd6: 9305 str r3, [sp, #20] 8006cd8: 4d31 ldr r5, [pc, #196] ; (8006da0 <_vfiprintf_r+0x21c>) 8006cda: 2203 movs r2, #3 8006cdc: f898 1000 ldrb.w r1, [r8] 8006ce0: 4628 mov r0, r5 8006ce2: f000 faa7 bl 8007234 8006ce6: b140 cbz r0, 8006cfa <_vfiprintf_r+0x176> 8006ce8: 2340 movs r3, #64 ; 0x40 8006cea: 1b40 subs r0, r0, r5 8006cec: fa03 f000 lsl.w r0, r3, r0 8006cf0: 9b04 ldr r3, [sp, #16] 8006cf2: f108 0801 add.w r8, r8, #1 8006cf6: 4303 orrs r3, r0 8006cf8: 9304 str r3, [sp, #16] 8006cfa: f898 1000 ldrb.w r1, [r8] 8006cfe: 2206 movs r2, #6 8006d00: 4828 ldr r0, [pc, #160] ; (8006da4 <_vfiprintf_r+0x220>) 8006d02: f108 0701 add.w r7, r8, #1 8006d06: f88d 1028 strb.w r1, [sp, #40] ; 0x28 8006d0a: f000 fa93 bl 8007234 8006d0e: 2800 cmp r0, #0 8006d10: d034 beq.n 8006d7c <_vfiprintf_r+0x1f8> 8006d12: 4b25 ldr r3, [pc, #148] ; (8006da8 <_vfiprintf_r+0x224>) 8006d14: bb03 cbnz r3, 8006d58 <_vfiprintf_r+0x1d4> 8006d16: 9b03 ldr r3, [sp, #12] 8006d18: 3307 adds r3, #7 8006d1a: f023 0307 bic.w r3, r3, #7 8006d1e: 3308 adds r3, #8 8006d20: 9303 str r3, [sp, #12] 8006d22: 9b09 ldr r3, [sp, #36] ; 0x24 8006d24: 444b add r3, r9 8006d26: 9309 str r3, [sp, #36] ; 0x24 8006d28: e74c b.n 8006bc4 <_vfiprintf_r+0x40> 8006d2a: fb00 3202 mla r2, r0, r2, r3 8006d2e: 2101 movs r1, #1 8006d30: e786 b.n 8006c40 <_vfiprintf_r+0xbc> 8006d32: 2300 movs r3, #0 8006d34: 250a movs r5, #10 8006d36: 4618 mov r0, r3 8006d38: 9305 str r3, [sp, #20] 8006d3a: 4688 mov r8, r1 8006d3c: f898 2000 ldrb.w r2, [r8] 8006d40: 3101 adds r1, #1 8006d42: 3a30 subs r2, #48 ; 0x30 8006d44: 2a09 cmp r2, #9 8006d46: d903 bls.n 8006d50 <_vfiprintf_r+0x1cc> 8006d48: 2b00 cmp r3, #0 8006d4a: d0c5 beq.n 8006cd8 <_vfiprintf_r+0x154> 8006d4c: 9005 str r0, [sp, #20] 8006d4e: e7c3 b.n 8006cd8 <_vfiprintf_r+0x154> 8006d50: fb05 2000 mla r0, r5, r0, r2 8006d54: 2301 movs r3, #1 8006d56: e7f0 b.n 8006d3a <_vfiprintf_r+0x1b6> 8006d58: ab03 add r3, sp, #12 8006d5a: 9300 str r3, [sp, #0] 8006d5c: 4622 mov r2, r4 8006d5e: 4b13 ldr r3, [pc, #76] ; (8006dac <_vfiprintf_r+0x228>) 8006d60: a904 add r1, sp, #16 8006d62: 4630 mov r0, r6 8006d64: f3af 8000 nop.w 8006d68: f1b0 3fff cmp.w r0, #4294967295 8006d6c: 4681 mov r9, r0 8006d6e: d1d8 bne.n 8006d22 <_vfiprintf_r+0x19e> 8006d70: 89a3 ldrh r3, [r4, #12] 8006d72: 065b lsls r3, r3, #25 8006d74: f53f af7d bmi.w 8006c72 <_vfiprintf_r+0xee> 8006d78: 9809 ldr r0, [sp, #36] ; 0x24 8006d7a: e77c b.n 8006c76 <_vfiprintf_r+0xf2> 8006d7c: ab03 add r3, sp, #12 8006d7e: 9300 str r3, [sp, #0] 8006d80: 4622 mov r2, r4 8006d82: 4b0a ldr r3, [pc, #40] ; (8006dac <_vfiprintf_r+0x228>) 8006d84: a904 add r1, sp, #16 8006d86: 4630 mov r0, r6 8006d88: f000 f88a bl 8006ea0 <_printf_i> 8006d8c: e7ec b.n 8006d68 <_vfiprintf_r+0x1e4> 8006d8e: bf00 nop 8006d90: 08007320 .word 0x08007320 8006d94: 08007360 .word 0x08007360 8006d98: 08007340 .word 0x08007340 8006d9c: 08007300 .word 0x08007300 8006da0: 08007366 .word 0x08007366 8006da4: 0800736a .word 0x0800736a 8006da8: 00000000 .word 0x00000000 8006dac: 08006b61 .word 0x08006b61 08006db0 <_printf_common>: 8006db0: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8006db4: 4691 mov r9, r2 8006db6: 461f mov r7, r3 8006db8: 688a ldr r2, [r1, #8] 8006dba: 690b ldr r3, [r1, #16] 8006dbc: 4606 mov r6, r0 8006dbe: 4293 cmp r3, r2 8006dc0: bfb8 it lt 8006dc2: 4613 movlt r3, r2 8006dc4: f8c9 3000 str.w r3, [r9] 8006dc8: f891 2043 ldrb.w r2, [r1, #67] ; 0x43 8006dcc: 460c mov r4, r1 8006dce: f8dd 8020 ldr.w r8, [sp, #32] 8006dd2: b112 cbz r2, 8006dda <_printf_common+0x2a> 8006dd4: 3301 adds r3, #1 8006dd6: f8c9 3000 str.w r3, [r9] 8006dda: 6823 ldr r3, [r4, #0] 8006ddc: 0699 lsls r1, r3, #26 8006dde: bf42 ittt mi 8006de0: f8d9 3000 ldrmi.w r3, [r9] 8006de4: 3302 addmi r3, #2 8006de6: f8c9 3000 strmi.w r3, [r9] 8006dea: 6825 ldr r5, [r4, #0] 8006dec: f015 0506 ands.w r5, r5, #6 8006df0: d107 bne.n 8006e02 <_printf_common+0x52> 8006df2: f104 0a19 add.w sl, r4, #25 8006df6: 68e3 ldr r3, [r4, #12] 8006df8: f8d9 2000 ldr.w r2, [r9] 8006dfc: 1a9b subs r3, r3, r2 8006dfe: 429d cmp r5, r3 8006e00: db2a blt.n 8006e58 <_printf_common+0xa8> 8006e02: f894 3043 ldrb.w r3, [r4, #67] ; 0x43 8006e06: 6822 ldr r2, [r4, #0] 8006e08: 3300 adds r3, #0 8006e0a: bf18 it ne 8006e0c: 2301 movne r3, #1 8006e0e: 0692 lsls r2, r2, #26 8006e10: d42f bmi.n 8006e72 <_printf_common+0xc2> 8006e12: f104 0243 add.w r2, r4, #67 ; 0x43 8006e16: 4639 mov r1, r7 8006e18: 4630 mov r0, r6 8006e1a: 47c0 blx r8 8006e1c: 3001 adds r0, #1 8006e1e: d022 beq.n 8006e66 <_printf_common+0xb6> 8006e20: 6823 ldr r3, [r4, #0] 8006e22: 68e5 ldr r5, [r4, #12] 8006e24: f003 0306 and.w r3, r3, #6 8006e28: 2b04 cmp r3, #4 8006e2a: bf18 it ne 8006e2c: 2500 movne r5, #0 8006e2e: f8d9 2000 ldr.w r2, [r9] 8006e32: f04f 0900 mov.w r9, #0 8006e36: bf08 it eq 8006e38: 1aad subeq r5, r5, r2 8006e3a: 68a3 ldr r3, [r4, #8] 8006e3c: 6922 ldr r2, [r4, #16] 8006e3e: bf08 it eq 8006e40: ea25 75e5 biceq.w r5, r5, r5, asr #31 8006e44: 4293 cmp r3, r2 8006e46: bfc4 itt gt 8006e48: 1a9b subgt r3, r3, r2 8006e4a: 18ed addgt r5, r5, r3 8006e4c: 341a adds r4, #26 8006e4e: 454d cmp r5, r9 8006e50: d11b bne.n 8006e8a <_printf_common+0xda> 8006e52: 2000 movs r0, #0 8006e54: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8006e58: 2301 movs r3, #1 8006e5a: 4652 mov r2, sl 8006e5c: 4639 mov r1, r7 8006e5e: 4630 mov r0, r6 8006e60: 47c0 blx r8 8006e62: 3001 adds r0, #1 8006e64: d103 bne.n 8006e6e <_printf_common+0xbe> 8006e66: f04f 30ff mov.w r0, #4294967295 8006e6a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8006e6e: 3501 adds r5, #1 8006e70: e7c1 b.n 8006df6 <_printf_common+0x46> 8006e72: 2030 movs r0, #48 ; 0x30 8006e74: 18e1 adds r1, r4, r3 8006e76: f881 0043 strb.w r0, [r1, #67] ; 0x43 8006e7a: 1c5a adds r2, r3, #1 8006e7c: f894 1045 ldrb.w r1, [r4, #69] ; 0x45 8006e80: 4422 add r2, r4 8006e82: 3302 adds r3, #2 8006e84: f882 1043 strb.w r1, [r2, #67] ; 0x43 8006e88: e7c3 b.n 8006e12 <_printf_common+0x62> 8006e8a: 2301 movs r3, #1 8006e8c: 4622 mov r2, r4 8006e8e: 4639 mov r1, r7 8006e90: 4630 mov r0, r6 8006e92: 47c0 blx r8 8006e94: 3001 adds r0, #1 8006e96: d0e6 beq.n 8006e66 <_printf_common+0xb6> 8006e98: f109 0901 add.w r9, r9, #1 8006e9c: e7d7 b.n 8006e4e <_printf_common+0x9e> ... 08006ea0 <_printf_i>: 8006ea0: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} 8006ea4: 4617 mov r7, r2 8006ea6: 7e0a ldrb r2, [r1, #24] 8006ea8: b085 sub sp, #20 8006eaa: 2a6e cmp r2, #110 ; 0x6e 8006eac: 4698 mov r8, r3 8006eae: 4606 mov r6, r0 8006eb0: 460c mov r4, r1 8006eb2: 9b0c ldr r3, [sp, #48] ; 0x30 8006eb4: f101 0e43 add.w lr, r1, #67 ; 0x43 8006eb8: f000 80bc beq.w 8007034 <_printf_i+0x194> 8006ebc: d81a bhi.n 8006ef4 <_printf_i+0x54> 8006ebe: 2a63 cmp r2, #99 ; 0x63 8006ec0: d02e beq.n 8006f20 <_printf_i+0x80> 8006ec2: d80a bhi.n 8006eda <_printf_i+0x3a> 8006ec4: 2a00 cmp r2, #0 8006ec6: f000 80c8 beq.w 800705a <_printf_i+0x1ba> 8006eca: 2a58 cmp r2, #88 ; 0x58 8006ecc: f000 808a beq.w 8006fe4 <_printf_i+0x144> 8006ed0: f104 0542 add.w r5, r4, #66 ; 0x42 8006ed4: f884 2042 strb.w r2, [r4, #66] ; 0x42 8006ed8: e02a b.n 8006f30 <_printf_i+0x90> 8006eda: 2a64 cmp r2, #100 ; 0x64 8006edc: d001 beq.n 8006ee2 <_printf_i+0x42> 8006ede: 2a69 cmp r2, #105 ; 0x69 8006ee0: d1f6 bne.n 8006ed0 <_printf_i+0x30> 8006ee2: 6821 ldr r1, [r4, #0] 8006ee4: 681a ldr r2, [r3, #0] 8006ee6: f011 0f80 tst.w r1, #128 ; 0x80 8006eea: d023 beq.n 8006f34 <_printf_i+0x94> 8006eec: 1d11 adds r1, r2, #4 8006eee: 6019 str r1, [r3, #0] 8006ef0: 6813 ldr r3, [r2, #0] 8006ef2: e027 b.n 8006f44 <_printf_i+0xa4> 8006ef4: 2a73 cmp r2, #115 ; 0x73 8006ef6: f000 80b4 beq.w 8007062 <_printf_i+0x1c2> 8006efa: d808 bhi.n 8006f0e <_printf_i+0x6e> 8006efc: 2a6f cmp r2, #111 ; 0x6f 8006efe: d02a beq.n 8006f56 <_printf_i+0xb6> 8006f00: 2a70 cmp r2, #112 ; 0x70 8006f02: d1e5 bne.n 8006ed0 <_printf_i+0x30> 8006f04: 680a ldr r2, [r1, #0] 8006f06: f042 0220 orr.w r2, r2, #32 8006f0a: 600a str r2, [r1, #0] 8006f0c: e003 b.n 8006f16 <_printf_i+0x76> 8006f0e: 2a75 cmp r2, #117 ; 0x75 8006f10: d021 beq.n 8006f56 <_printf_i+0xb6> 8006f12: 2a78 cmp r2, #120 ; 0x78 8006f14: d1dc bne.n 8006ed0 <_printf_i+0x30> 8006f16: 2278 movs r2, #120 ; 0x78 8006f18: 496f ldr r1, [pc, #444] ; (80070d8 <_printf_i+0x238>) 8006f1a: f884 2045 strb.w r2, [r4, #69] ; 0x45 8006f1e: e064 b.n 8006fea <_printf_i+0x14a> 8006f20: 681a ldr r2, [r3, #0] 8006f22: f101 0542 add.w r5, r1, #66 ; 0x42 8006f26: 1d11 adds r1, r2, #4 8006f28: 6019 str r1, [r3, #0] 8006f2a: 6813 ldr r3, [r2, #0] 8006f2c: f884 3042 strb.w r3, [r4, #66] ; 0x42 8006f30: 2301 movs r3, #1 8006f32: e0a3 b.n 800707c <_printf_i+0x1dc> 8006f34: f011 0f40 tst.w r1, #64 ; 0x40 8006f38: f102 0104 add.w r1, r2, #4 8006f3c: 6019 str r1, [r3, #0] 8006f3e: d0d7 beq.n 8006ef0 <_printf_i+0x50> 8006f40: f9b2 3000 ldrsh.w r3, [r2] 8006f44: 2b00 cmp r3, #0 8006f46: da03 bge.n 8006f50 <_printf_i+0xb0> 8006f48: 222d movs r2, #45 ; 0x2d 8006f4a: 425b negs r3, r3 8006f4c: f884 2043 strb.w r2, [r4, #67] ; 0x43 8006f50: 4962 ldr r1, [pc, #392] ; (80070dc <_printf_i+0x23c>) 8006f52: 220a movs r2, #10 8006f54: e017 b.n 8006f86 <_printf_i+0xe6> 8006f56: 6820 ldr r0, [r4, #0] 8006f58: 6819 ldr r1, [r3, #0] 8006f5a: f010 0f80 tst.w r0, #128 ; 0x80 8006f5e: d003 beq.n 8006f68 <_printf_i+0xc8> 8006f60: 1d08 adds r0, r1, #4 8006f62: 6018 str r0, [r3, #0] 8006f64: 680b ldr r3, [r1, #0] 8006f66: e006 b.n 8006f76 <_printf_i+0xd6> 8006f68: f010 0f40 tst.w r0, #64 ; 0x40 8006f6c: f101 0004 add.w r0, r1, #4 8006f70: 6018 str r0, [r3, #0] 8006f72: d0f7 beq.n 8006f64 <_printf_i+0xc4> 8006f74: 880b ldrh r3, [r1, #0] 8006f76: 2a6f cmp r2, #111 ; 0x6f 8006f78: bf14 ite ne 8006f7a: 220a movne r2, #10 8006f7c: 2208 moveq r2, #8 8006f7e: 4957 ldr r1, [pc, #348] ; (80070dc <_printf_i+0x23c>) 8006f80: 2000 movs r0, #0 8006f82: f884 0043 strb.w r0, [r4, #67] ; 0x43 8006f86: 6865 ldr r5, [r4, #4] 8006f88: 2d00 cmp r5, #0 8006f8a: 60a5 str r5, [r4, #8] 8006f8c: f2c0 809c blt.w 80070c8 <_printf_i+0x228> 8006f90: 6820 ldr r0, [r4, #0] 8006f92: f020 0004 bic.w r0, r0, #4 8006f96: 6020 str r0, [r4, #0] 8006f98: 2b00 cmp r3, #0 8006f9a: d13f bne.n 800701c <_printf_i+0x17c> 8006f9c: 2d00 cmp r5, #0 8006f9e: f040 8095 bne.w 80070cc <_printf_i+0x22c> 8006fa2: 4675 mov r5, lr 8006fa4: 2a08 cmp r2, #8 8006fa6: d10b bne.n 8006fc0 <_printf_i+0x120> 8006fa8: 6823 ldr r3, [r4, #0] 8006faa: 07da lsls r2, r3, #31 8006fac: d508 bpl.n 8006fc0 <_printf_i+0x120> 8006fae: 6923 ldr r3, [r4, #16] 8006fb0: 6862 ldr r2, [r4, #4] 8006fb2: 429a cmp r2, r3 8006fb4: bfde ittt le 8006fb6: 2330 movle r3, #48 ; 0x30 8006fb8: f805 3c01 strble.w r3, [r5, #-1] 8006fbc: f105 35ff addle.w r5, r5, #4294967295 8006fc0: ebae 0305 sub.w r3, lr, r5 8006fc4: 6123 str r3, [r4, #16] 8006fc6: f8cd 8000 str.w r8, [sp] 8006fca: 463b mov r3, r7 8006fcc: aa03 add r2, sp, #12 8006fce: 4621 mov r1, r4 8006fd0: 4630 mov r0, r6 8006fd2: f7ff feed bl 8006db0 <_printf_common> 8006fd6: 3001 adds r0, #1 8006fd8: d155 bne.n 8007086 <_printf_i+0x1e6> 8006fda: f04f 30ff mov.w r0, #4294967295 8006fde: b005 add sp, #20 8006fe0: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} 8006fe4: f881 2045 strb.w r2, [r1, #69] ; 0x45 8006fe8: 493c ldr r1, [pc, #240] ; (80070dc <_printf_i+0x23c>) 8006fea: 6822 ldr r2, [r4, #0] 8006fec: 6818 ldr r0, [r3, #0] 8006fee: f012 0f80 tst.w r2, #128 ; 0x80 8006ff2: f100 0504 add.w r5, r0, #4 8006ff6: 601d str r5, [r3, #0] 8006ff8: d001 beq.n 8006ffe <_printf_i+0x15e> 8006ffa: 6803 ldr r3, [r0, #0] 8006ffc: e002 b.n 8007004 <_printf_i+0x164> 8006ffe: 0655 lsls r5, r2, #25 8007000: d5fb bpl.n 8006ffa <_printf_i+0x15a> 8007002: 8803 ldrh r3, [r0, #0] 8007004: 07d0 lsls r0, r2, #31 8007006: bf44 itt mi 8007008: f042 0220 orrmi.w r2, r2, #32 800700c: 6022 strmi r2, [r4, #0] 800700e: b91b cbnz r3, 8007018 <_printf_i+0x178> 8007010: 6822 ldr r2, [r4, #0] 8007012: f022 0220 bic.w r2, r2, #32 8007016: 6022 str r2, [r4, #0] 8007018: 2210 movs r2, #16 800701a: e7b1 b.n 8006f80 <_printf_i+0xe0> 800701c: 4675 mov r5, lr 800701e: fbb3 f0f2 udiv r0, r3, r2 8007022: fb02 3310 mls r3, r2, r0, r3 8007026: 5ccb ldrb r3, [r1, r3] 8007028: f805 3d01 strb.w r3, [r5, #-1]! 800702c: 4603 mov r3, r0 800702e: 2800 cmp r0, #0 8007030: d1f5 bne.n 800701e <_printf_i+0x17e> 8007032: e7b7 b.n 8006fa4 <_printf_i+0x104> 8007034: 6808 ldr r0, [r1, #0] 8007036: 681a ldr r2, [r3, #0] 8007038: f010 0f80 tst.w r0, #128 ; 0x80 800703c: 6949 ldr r1, [r1, #20] 800703e: d004 beq.n 800704a <_printf_i+0x1aa> 8007040: 1d10 adds r0, r2, #4 8007042: 6018 str r0, [r3, #0] 8007044: 6813 ldr r3, [r2, #0] 8007046: 6019 str r1, [r3, #0] 8007048: e007 b.n 800705a <_printf_i+0x1ba> 800704a: f010 0f40 tst.w r0, #64 ; 0x40 800704e: f102 0004 add.w r0, r2, #4 8007052: 6018 str r0, [r3, #0] 8007054: 6813 ldr r3, [r2, #0] 8007056: d0f6 beq.n 8007046 <_printf_i+0x1a6> 8007058: 8019 strh r1, [r3, #0] 800705a: 2300 movs r3, #0 800705c: 4675 mov r5, lr 800705e: 6123 str r3, [r4, #16] 8007060: e7b1 b.n 8006fc6 <_printf_i+0x126> 8007062: 681a ldr r2, [r3, #0] 8007064: 1d11 adds r1, r2, #4 8007066: 6019 str r1, [r3, #0] 8007068: 6815 ldr r5, [r2, #0] 800706a: 2100 movs r1, #0 800706c: 6862 ldr r2, [r4, #4] 800706e: 4628 mov r0, r5 8007070: f000 f8e0 bl 8007234 8007074: b108 cbz r0, 800707a <_printf_i+0x1da> 8007076: 1b40 subs r0, r0, r5 8007078: 6060 str r0, [r4, #4] 800707a: 6863 ldr r3, [r4, #4] 800707c: 6123 str r3, [r4, #16] 800707e: 2300 movs r3, #0 8007080: f884 3043 strb.w r3, [r4, #67] ; 0x43 8007084: e79f b.n 8006fc6 <_printf_i+0x126> 8007086: 6923 ldr r3, [r4, #16] 8007088: 462a mov r2, r5 800708a: 4639 mov r1, r7 800708c: 4630 mov r0, r6 800708e: 47c0 blx r8 8007090: 3001 adds r0, #1 8007092: d0a2 beq.n 8006fda <_printf_i+0x13a> 8007094: 6823 ldr r3, [r4, #0] 8007096: 079b lsls r3, r3, #30 8007098: d507 bpl.n 80070aa <_printf_i+0x20a> 800709a: 2500 movs r5, #0 800709c: f104 0919 add.w r9, r4, #25 80070a0: 68e3 ldr r3, [r4, #12] 80070a2: 9a03 ldr r2, [sp, #12] 80070a4: 1a9b subs r3, r3, r2 80070a6: 429d cmp r5, r3 80070a8: db05 blt.n 80070b6 <_printf_i+0x216> 80070aa: 68e0 ldr r0, [r4, #12] 80070ac: 9b03 ldr r3, [sp, #12] 80070ae: 4298 cmp r0, r3 80070b0: bfb8 it lt 80070b2: 4618 movlt r0, r3 80070b4: e793 b.n 8006fde <_printf_i+0x13e> 80070b6: 2301 movs r3, #1 80070b8: 464a mov r2, r9 80070ba: 4639 mov r1, r7 80070bc: 4630 mov r0, r6 80070be: 47c0 blx r8 80070c0: 3001 adds r0, #1 80070c2: d08a beq.n 8006fda <_printf_i+0x13a> 80070c4: 3501 adds r5, #1 80070c6: e7eb b.n 80070a0 <_printf_i+0x200> 80070c8: 2b00 cmp r3, #0 80070ca: d1a7 bne.n 800701c <_printf_i+0x17c> 80070cc: 780b ldrb r3, [r1, #0] 80070ce: f104 0542 add.w r5, r4, #66 ; 0x42 80070d2: f884 3042 strb.w r3, [r4, #66] ; 0x42 80070d6: e765 b.n 8006fa4 <_printf_i+0x104> 80070d8: 08007382 .word 0x08007382 80070dc: 08007371 .word 0x08007371 080070e0 <_sbrk_r>: 80070e0: b538 push {r3, r4, r5, lr} 80070e2: 2300 movs r3, #0 80070e4: 4c05 ldr r4, [pc, #20] ; (80070fc <_sbrk_r+0x1c>) 80070e6: 4605 mov r5, r0 80070e8: 4608 mov r0, r1 80070ea: 6023 str r3, [r4, #0] 80070ec: f7fe ff96 bl 800601c <_sbrk> 80070f0: 1c43 adds r3, r0, #1 80070f2: d102 bne.n 80070fa <_sbrk_r+0x1a> 80070f4: 6823 ldr r3, [r4, #0] 80070f6: b103 cbz r3, 80070fa <_sbrk_r+0x1a> 80070f8: 602b str r3, [r5, #0] 80070fa: bd38 pop {r3, r4, r5, pc} 80070fc: 200007e8 .word 0x200007e8 08007100 <__sread>: 8007100: b510 push {r4, lr} 8007102: 460c mov r4, r1 8007104: f9b1 100e ldrsh.w r1, [r1, #14] 8007108: f000 f8a4 bl 8007254 <_read_r> 800710c: 2800 cmp r0, #0 800710e: bfab itete ge 8007110: 6d63 ldrge r3, [r4, #84] ; 0x54 8007112: 89a3 ldrhlt r3, [r4, #12] 8007114: 181b addge r3, r3, r0 8007116: f423 5380 biclt.w r3, r3, #4096 ; 0x1000 800711a: bfac ite ge 800711c: 6563 strge r3, [r4, #84] ; 0x54 800711e: 81a3 strhlt r3, [r4, #12] 8007120: bd10 pop {r4, pc} 08007122 <__swrite>: 8007122: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 8007126: 461f mov r7, r3 8007128: 898b ldrh r3, [r1, #12] 800712a: 4605 mov r5, r0 800712c: 05db lsls r3, r3, #23 800712e: 460c mov r4, r1 8007130: 4616 mov r6, r2 8007132: d505 bpl.n 8007140 <__swrite+0x1e> 8007134: 2302 movs r3, #2 8007136: 2200 movs r2, #0 8007138: f9b1 100e ldrsh.w r1, [r1, #14] 800713c: f000 f868 bl 8007210 <_lseek_r> 8007140: 89a3 ldrh r3, [r4, #12] 8007142: 4632 mov r2, r6 8007144: f423 5380 bic.w r3, r3, #4096 ; 0x1000 8007148: 81a3 strh r3, [r4, #12] 800714a: f9b4 100e ldrsh.w r1, [r4, #14] 800714e: 463b mov r3, r7 8007150: 4628 mov r0, r5 8007152: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 8007156: f000 b817 b.w 8007188 <_write_r> 0800715a <__sseek>: 800715a: b510 push {r4, lr} 800715c: 460c mov r4, r1 800715e: f9b1 100e ldrsh.w r1, [r1, #14] 8007162: f000 f855 bl 8007210 <_lseek_r> 8007166: 1c43 adds r3, r0, #1 8007168: 89a3 ldrh r3, [r4, #12] 800716a: bf15 itete ne 800716c: 6560 strne r0, [r4, #84] ; 0x54 800716e: f423 5380 biceq.w r3, r3, #4096 ; 0x1000 8007172: f443 5380 orrne.w r3, r3, #4096 ; 0x1000 8007176: 81a3 strheq r3, [r4, #12] 8007178: bf18 it ne 800717a: 81a3 strhne r3, [r4, #12] 800717c: bd10 pop {r4, pc} 0800717e <__sclose>: 800717e: f9b1 100e ldrsh.w r1, [r1, #14] 8007182: f000 b813 b.w 80071ac <_close_r> ... 08007188 <_write_r>: 8007188: b538 push {r3, r4, r5, lr} 800718a: 4605 mov r5, r0 800718c: 4608 mov r0, r1 800718e: 4611 mov r1, r2 8007190: 2200 movs r2, #0 8007192: 4c05 ldr r4, [pc, #20] ; (80071a8 <_write_r+0x20>) 8007194: 6022 str r2, [r4, #0] 8007196: 461a mov r2, r3 8007198: f7fe fc22 bl 80059e0 <_write> 800719c: 1c43 adds r3, r0, #1 800719e: d102 bne.n 80071a6 <_write_r+0x1e> 80071a0: 6823 ldr r3, [r4, #0] 80071a2: b103 cbz r3, 80071a6 <_write_r+0x1e> 80071a4: 602b str r3, [r5, #0] 80071a6: bd38 pop {r3, r4, r5, pc} 80071a8: 200007e8 .word 0x200007e8 080071ac <_close_r>: 80071ac: b538 push {r3, r4, r5, lr} 80071ae: 2300 movs r3, #0 80071b0: 4c05 ldr r4, [pc, #20] ; (80071c8 <_close_r+0x1c>) 80071b2: 4605 mov r5, r0 80071b4: 4608 mov r0, r1 80071b6: 6023 str r3, [r4, #0] 80071b8: f7fe ff4a bl 8006050 <_close> 80071bc: 1c43 adds r3, r0, #1 80071be: d102 bne.n 80071c6 <_close_r+0x1a> 80071c0: 6823 ldr r3, [r4, #0] 80071c2: b103 cbz r3, 80071c6 <_close_r+0x1a> 80071c4: 602b str r3, [r5, #0] 80071c6: bd38 pop {r3, r4, r5, pc} 80071c8: 200007e8 .word 0x200007e8 080071cc <_fstat_r>: 80071cc: b538 push {r3, r4, r5, lr} 80071ce: 2300 movs r3, #0 80071d0: 4c06 ldr r4, [pc, #24] ; (80071ec <_fstat_r+0x20>) 80071d2: 4605 mov r5, r0 80071d4: 4608 mov r0, r1 80071d6: 4611 mov r1, r2 80071d8: 6023 str r3, [r4, #0] 80071da: f7fe ff3c bl 8006056 <_fstat> 80071de: 1c43 adds r3, r0, #1 80071e0: d102 bne.n 80071e8 <_fstat_r+0x1c> 80071e2: 6823 ldr r3, [r4, #0] 80071e4: b103 cbz r3, 80071e8 <_fstat_r+0x1c> 80071e6: 602b str r3, [r5, #0] 80071e8: bd38 pop {r3, r4, r5, pc} 80071ea: bf00 nop 80071ec: 200007e8 .word 0x200007e8 080071f0 <_isatty_r>: 80071f0: b538 push {r3, r4, r5, lr} 80071f2: 2300 movs r3, #0 80071f4: 4c05 ldr r4, [pc, #20] ; (800720c <_isatty_r+0x1c>) 80071f6: 4605 mov r5, r0 80071f8: 4608 mov r0, r1 80071fa: 6023 str r3, [r4, #0] 80071fc: f7fe ff30 bl 8006060 <_isatty> 8007200: 1c43 adds r3, r0, #1 8007202: d102 bne.n 800720a <_isatty_r+0x1a> 8007204: 6823 ldr r3, [r4, #0] 8007206: b103 cbz r3, 800720a <_isatty_r+0x1a> 8007208: 602b str r3, [r5, #0] 800720a: bd38 pop {r3, r4, r5, pc} 800720c: 200007e8 .word 0x200007e8 08007210 <_lseek_r>: 8007210: b538 push {r3, r4, r5, lr} 8007212: 4605 mov r5, r0 8007214: 4608 mov r0, r1 8007216: 4611 mov r1, r2 8007218: 2200 movs r2, #0 800721a: 4c05 ldr r4, [pc, #20] ; (8007230 <_lseek_r+0x20>) 800721c: 6022 str r2, [r4, #0] 800721e: 461a mov r2, r3 8007220: f7fe ff20 bl 8006064 <_lseek> 8007224: 1c43 adds r3, r0, #1 8007226: d102 bne.n 800722e <_lseek_r+0x1e> 8007228: 6823 ldr r3, [r4, #0] 800722a: b103 cbz r3, 800722e <_lseek_r+0x1e> 800722c: 602b str r3, [r5, #0] 800722e: bd38 pop {r3, r4, r5, pc} 8007230: 200007e8 .word 0x200007e8 08007234 : 8007234: b510 push {r4, lr} 8007236: b2c9 uxtb r1, r1 8007238: 4402 add r2, r0 800723a: 4290 cmp r0, r2 800723c: 4603 mov r3, r0 800723e: d101 bne.n 8007244 8007240: 2000 movs r0, #0 8007242: bd10 pop {r4, pc} 8007244: 781c ldrb r4, [r3, #0] 8007246: 3001 adds r0, #1 8007248: 428c cmp r4, r1 800724a: d1f6 bne.n 800723a 800724c: 4618 mov r0, r3 800724e: bd10 pop {r4, pc} 08007250 <__malloc_lock>: 8007250: 4770 bx lr 08007252 <__malloc_unlock>: 8007252: 4770 bx lr 08007254 <_read_r>: 8007254: b538 push {r3, r4, r5, lr} 8007256: 4605 mov r5, r0 8007258: 4608 mov r0, r1 800725a: 4611 mov r1, r2 800725c: 2200 movs r2, #0 800725e: 4c05 ldr r4, [pc, #20] ; (8007274 <_read_r+0x20>) 8007260: 6022 str r2, [r4, #0] 8007262: 461a mov r2, r3 8007264: f7fe fecc bl 8006000 <_read> 8007268: 1c43 adds r3, r0, #1 800726a: d102 bne.n 8007272 <_read_r+0x1e> 800726c: 6823 ldr r3, [r4, #0] 800726e: b103 cbz r3, 8007272 <_read_r+0x1e> 8007270: 602b str r3, [r5, #0] 8007272: bd38 pop {r3, r4, r5, pc} 8007274: 200007e8 .word 0x200007e8 08007278 <_init>: 8007278: b5f8 push {r3, r4, r5, r6, r7, lr} 800727a: bf00 nop 800727c: bcf8 pop {r3, r4, r5, r6, r7} 800727e: bc08 pop {r3} 8007280: 469e mov lr, r3 8007282: 4770 bx lr 08007284 <_fini>: 8007284: b5f8 push {r3, r4, r5, r6, r7, lr} 8007286: bf00 nop 8007288: bcf8 pop {r3, r4, r5, r6, r7} 800728a: bc08 pop {r3} 800728c: 469e mov lr, r3 800728e: 4770 bx lr