STM32F103_ATTEN_PLL_Zig.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000001e4 08000000 08000000 00010000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 00002fc0 080001e4 080001e4 000101e4 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000128 080031a4 080031a4 000131a4 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .init_array 00000004 080032cc 080032cc 000132cc 2**2 CONTENTS, ALLOC, LOAD, DATA 4 .fini_array 00000004 080032d0 080032d0 000132d0 2**2 CONTENTS, ALLOC, LOAD, DATA 5 .data 00000074 20000000 080032d4 00020000 2**2 CONTENTS, ALLOC, LOAD, DATA 6 .bss 00001560 20000078 08003348 00020078 2**3 ALLOC 7 ._user_heap_stack 00000600 200015d8 08003348 000215d8 2**0 ALLOC 8 .ARM.attributes 00000029 00000000 00000000 00020074 2**0 CONTENTS, READONLY 9 .debug_info 00019193 00000000 00000000 0002009d 2**0 CONTENTS, READONLY, DEBUGGING 10 .debug_abbrev 000037bc 00000000 00000000 00039230 2**0 CONTENTS, READONLY, DEBUGGING 11 .debug_loc 000075a9 00000000 00000000 0003c9ec 2**0 CONTENTS, READONLY, DEBUGGING 12 .debug_aranges 00000af0 00000000 00000000 00043f98 2**3 CONTENTS, READONLY, DEBUGGING 13 .debug_ranges 00000e40 00000000 00000000 00044a88 2**3 CONTENTS, READONLY, DEBUGGING 14 .debug_line 00006ce5 00000000 00000000 000458c8 2**0 CONTENTS, READONLY, DEBUGGING 15 .debug_str 00004068 00000000 00000000 0004c5ad 2**0 CONTENTS, READONLY, DEBUGGING 16 .comment 0000007c 00000000 00000000 00050615 2**0 CONTENTS, READONLY 17 .debug_frame 00002638 00000000 00000000 00050694 2**2 CONTENTS, READONLY, DEBUGGING Disassembly of section .text: 080001e4 <__do_global_dtors_aux>: 80001e4: b510 push {r4, lr} 80001e6: 4c05 ldr r4, [pc, #20] ; (80001fc <__do_global_dtors_aux+0x18>) 80001e8: 7823 ldrb r3, [r4, #0] 80001ea: b933 cbnz r3, 80001fa <__do_global_dtors_aux+0x16> 80001ec: 4b04 ldr r3, [pc, #16] ; (8000200 <__do_global_dtors_aux+0x1c>) 80001ee: b113 cbz r3, 80001f6 <__do_global_dtors_aux+0x12> 80001f0: 4804 ldr r0, [pc, #16] ; (8000204 <__do_global_dtors_aux+0x20>) 80001f2: f3af 8000 nop.w 80001f6: 2301 movs r3, #1 80001f8: 7023 strb r3, [r4, #0] 80001fa: bd10 pop {r4, pc} 80001fc: 20000078 .word 0x20000078 8000200: 00000000 .word 0x00000000 8000204: 0800318c .word 0x0800318c 08000208 : 8000208: b508 push {r3, lr} 800020a: 4b03 ldr r3, [pc, #12] ; (8000218 ) 800020c: b11b cbz r3, 8000216 800020e: 4903 ldr r1, [pc, #12] ; (800021c ) 8000210: 4803 ldr r0, [pc, #12] ; (8000220 ) 8000212: f3af 8000 nop.w 8000216: bd08 pop {r3, pc} 8000218: 00000000 .word 0x00000000 800021c: 2000007c .word 0x2000007c 8000220: 0800318c .word 0x0800318c 08000224 <__aeabi_llsr>: 8000224: 40d0 lsrs r0, r2 8000226: 1c0b adds r3, r1, #0 8000228: 40d1 lsrs r1, r2 800022a: 469c mov ip, r3 800022c: 3a20 subs r2, #32 800022e: 40d3 lsrs r3, r2 8000230: 4318 orrs r0, r3 8000232: 4252 negs r2, r2 8000234: 4663 mov r3, ip 8000236: 4093 lsls r3, r2 8000238: 4318 orrs r0, r3 800023a: 4770 bx lr 0800023c : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 800023c: b538 push {r3, r4, r5, lr} /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 800023e: 4b0e ldr r3, [pc, #56] ; (8000278 ) { 8000240: 4605 mov r5, r0 if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 8000242: 7818 ldrb r0, [r3, #0] 8000244: f44f 737a mov.w r3, #1000 ; 0x3e8 8000248: fbb3 f3f0 udiv r3, r3, r0 800024c: 4a0b ldr r2, [pc, #44] ; (800027c ) 800024e: 6810 ldr r0, [r2, #0] 8000250: fbb0 f0f3 udiv r0, r0, r3 8000254: f000 f89e bl 8000394 8000258: 4604 mov r4, r0 800025a: b958 cbnz r0, 8000274 { return HAL_ERROR; } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 800025c: 2d0f cmp r5, #15 800025e: d809 bhi.n 8000274 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 8000260: 4602 mov r2, r0 8000262: 4629 mov r1, r5 8000264: f04f 30ff mov.w r0, #4294967295 8000268: f000 f854 bl 8000314 uwTickPrio = TickPriority; 800026c: 4b04 ldr r3, [pc, #16] ; (8000280 ) 800026e: 4620 mov r0, r4 8000270: 601d str r5, [r3, #0] 8000272: bd38 pop {r3, r4, r5, pc} return HAL_ERROR; 8000274: 2001 movs r0, #1 return HAL_ERROR; } /* Return function status */ return HAL_OK; } 8000276: bd38 pop {r3, r4, r5, pc} 8000278: 20000000 .word 0x20000000 800027c: 2000000c .word 0x2000000c 8000280: 20000004 .word 0x20000004 08000284 : __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 8000284: 4a07 ldr r2, [pc, #28] ; (80002a4 ) { 8000286: b508 push {r3, lr} __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 8000288: 6813 ldr r3, [r2, #0] HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 800028a: 2003 movs r0, #3 __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 800028c: f043 0310 orr.w r3, r3, #16 8000290: 6013 str r3, [r2, #0] HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8000292: f000 f82d bl 80002f0 HAL_InitTick(TICK_INT_PRIORITY); 8000296: 2000 movs r0, #0 8000298: f7ff ffd0 bl 800023c HAL_MspInit(); 800029c: f001 fd84 bl 8001da8 } 80002a0: 2000 movs r0, #0 80002a2: bd08 pop {r3, pc} 80002a4: 40022000 .word 0x40022000 080002a8 : * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { uwTick += uwTickFreq; 80002a8: 4a03 ldr r2, [pc, #12] ; (80002b8 ) 80002aa: 4b04 ldr r3, [pc, #16] ; (80002bc ) 80002ac: 6811 ldr r1, [r2, #0] 80002ae: 781b ldrb r3, [r3, #0] 80002b0: 440b add r3, r1 80002b2: 6013 str r3, [r2, #0] 80002b4: 4770 bx lr 80002b6: bf00 nop 80002b8: 200004c8 .word 0x200004c8 80002bc: 20000000 .word 0x20000000 080002c0 : * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { return uwTick; 80002c0: 4b01 ldr r3, [pc, #4] ; (80002c8 ) 80002c2: 6818 ldr r0, [r3, #0] } 80002c4: 4770 bx lr 80002c6: bf00 nop 80002c8: 200004c8 .word 0x200004c8 080002cc : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 80002cc: b538 push {r3, r4, r5, lr} 80002ce: 4604 mov r4, r0 uint32_t tickstart = HAL_GetTick(); 80002d0: f7ff fff6 bl 80002c0 80002d4: 4605 mov r5, r0 uint32_t wait = Delay; /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 80002d6: 1c63 adds r3, r4, #1 { wait += (uint32_t)(uwTickFreq); 80002d8: bf1e ittt ne 80002da: 4b04 ldrne r3, [pc, #16] ; (80002ec ) 80002dc: 781b ldrbne r3, [r3, #0] 80002de: 18e4 addne r4, r4, r3 } while ((HAL_GetTick() - tickstart) < wait) 80002e0: f7ff ffee bl 80002c0 80002e4: 1b40 subs r0, r0, r5 80002e6: 4284 cmp r4, r0 80002e8: d8fa bhi.n 80002e0 { } } 80002ea: bd38 pop {r3, r4, r5, pc} 80002ec: 20000000 .word 0x20000000 080002f0 : __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ 80002f0: 4a07 ldr r2, [pc, #28] ; (8000310 ) reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ 80002f2: 0200 lsls r0, r0, #8 reg_value = SCB->AIRCR; /* read old register configuration */ 80002f4: 68d3 ldr r3, [r2, #12] (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ 80002f6: f400 60e0 and.w r0, r0, #1792 ; 0x700 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 80002fa: f423 63e0 bic.w r3, r3, #1792 ; 0x700 80002fe: 041b lsls r3, r3, #16 8000300: 0c1b lsrs r3, r3, #16 8000302: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 8000306: f443 3300 orr.w r3, r3, #131072 ; 0x20000 reg_value = (reg_value | 800030a: 4303 orrs r3, r0 SCB->AIRCR = reg_value; 800030c: 60d3 str r3, [r2, #12] 800030e: 4770 bx lr 8000310: e000ed00 .word 0xe000ed00 08000314 : \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8000314: 4b17 ldr r3, [pc, #92] ; (8000374 ) * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8000316: b530 push {r4, r5, lr} 8000318: 68dc ldr r4, [r3, #12] 800031a: f3c4 2402 ubfx r4, r4, #8, #3 { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 800031e: f1c4 0307 rsb r3, r4, #7 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8000322: 1d25 adds r5, r4, #4 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8000324: 2b04 cmp r3, #4 8000326: bf28 it cs 8000328: 2304 movcs r3, #4 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 800032a: 2d06 cmp r5, #6 return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 800032c: f04f 0501 mov.w r5, #1 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8000330: bf98 it ls 8000332: 2400 movls r4, #0 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8000334: fa05 f303 lsl.w r3, r5, r3 8000338: f103 33ff add.w r3, r3, #4294967295 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 800033c: bf88 it hi 800033e: 3c03 subhi r4, #3 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8000340: 4019 ands r1, r3 8000342: 40a1 lsls r1, r4 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8000344: fa05 f404 lsl.w r4, r5, r4 8000348: 3c01 subs r4, #1 800034a: 4022 ands r2, r4 if ((int32_t)(IRQn) < 0) 800034c: 2800 cmp r0, #0 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 800034e: ea42 0201 orr.w r2, r2, r1 8000352: ea4f 1202 mov.w r2, r2, lsl #4 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8000356: bfaf iteee ge 8000358: f100 4060 addge.w r0, r0, #3758096384 ; 0xe0000000 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800035c: 4b06 ldrlt r3, [pc, #24] ; (8000378 ) 800035e: f000 000f andlt.w r0, r0, #15 8000362: b2d2 uxtblt r2, r2 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8000364: bfa5 ittet ge 8000366: b2d2 uxtbge r2, r2 8000368: f500 4061 addge.w r0, r0, #57600 ; 0xe100 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800036c: 541a strblt r2, [r3, r0] NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800036e: f880 2300 strbge.w r2, [r0, #768] ; 0x300 8000372: bd30 pop {r4, r5, pc} 8000374: e000ed00 .word 0xe000ed00 8000378: e000ed14 .word 0xe000ed14 0800037c : NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 800037c: 2301 movs r3, #1 800037e: 0942 lsrs r2, r0, #5 8000380: f000 001f and.w r0, r0, #31 8000384: fa03 f000 lsl.w r0, r3, r0 8000388: 4b01 ldr r3, [pc, #4] ; (8000390 ) 800038a: f843 0022 str.w r0, [r3, r2, lsl #2] 800038e: 4770 bx lr 8000390: e000e100 .word 0xe000e100 08000394 : function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8000394: 3801 subs r0, #1 8000396: f1b0 7f80 cmp.w r0, #16777216 ; 0x1000000 800039a: d20a bcs.n 80003b2 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800039c: 21f0 movs r1, #240 ; 0xf0 { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 800039e: 4b06 ldr r3, [pc, #24] ; (80003b8 ) SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80003a0: 4a06 ldr r2, [pc, #24] ; (80003bc ) SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 80003a2: 6058 str r0, [r3, #4] SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80003a4: f882 1023 strb.w r1, [r2, #35] ; 0x23 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 80003a8: 2000 movs r0, #0 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 80003aa: 2207 movs r2, #7 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 80003ac: 6098 str r0, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 80003ae: 601a str r2, [r3, #0] 80003b0: 4770 bx lr return (1UL); /* Reload value impossible */ 80003b2: 2001 movs r0, #1 * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { return SysTick_Config(TicksNumb); } 80003b4: 4770 bx lr 80003b6: bf00 nop 80003b8: e000e010 .word 0xe000e010 80003bc: e000ed00 .word 0xe000ed00 080003c0 : * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { 80003c0: b510 push {r4, lr} uint32_t tmp = 0U; /* Check the DMA handle allocation */ if(hdma == NULL) 80003c2: 2800 cmp r0, #0 80003c4: d032 beq.n 800042c assert_param(IS_DMA_MODE(hdma->Init.Mode)); assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); #if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F100xE) || defined (STM32F105xC) || defined (STM32F107xC) /* calculation of the channel index */ if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) 80003c6: 6801 ldr r1, [r0, #0] 80003c8: 4b19 ldr r3, [pc, #100] ; (8000430 ) 80003ca: 2414 movs r4, #20 80003cc: 4299 cmp r1, r3 80003ce: d825 bhi.n 800041c { /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; 80003d0: 4a18 ldr r2, [pc, #96] ; (8000434 ) hdma->DmaBaseAddress = DMA1; 80003d2: f2a3 4307 subw r3, r3, #1031 ; 0x407 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; 80003d6: 440a add r2, r1 80003d8: fbb2 f2f4 udiv r2, r2, r4 80003dc: 0092 lsls r2, r2, #2 80003de: 6402 str r2, [r0, #64] ; 0x40 tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ DMA_CCR_DIR)); /* Prepare the DMA Channel configuration */ tmp |= hdma->Init.Direction | 80003e0: 6884 ldr r4, [r0, #8] hdma->DmaBaseAddress = DMA2; 80003e2: 63c3 str r3, [r0, #60] ; 0x3c tmp |= hdma->Init.Direction | 80003e4: 6843 ldr r3, [r0, #4] tmp = hdma->Instance->CCR; 80003e6: 680a ldr r2, [r1, #0] tmp |= hdma->Init.Direction | 80003e8: 4323 orrs r3, r4 hdma->Init.PeriphInc | hdma->Init.MemInc | 80003ea: 68c4 ldr r4, [r0, #12] tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ 80003ec: f422 527f bic.w r2, r2, #16320 ; 0x3fc0 hdma->Init.PeriphInc | hdma->Init.MemInc | 80003f0: 4323 orrs r3, r4 80003f2: 6904 ldr r4, [r0, #16] tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ 80003f4: f022 0230 bic.w r2, r2, #48 ; 0x30 hdma->Init.PeriphInc | hdma->Init.MemInc | 80003f8: 4323 orrs r3, r4 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 80003fa: 6944 ldr r4, [r0, #20] 80003fc: 4323 orrs r3, r4 80003fe: 6984 ldr r4, [r0, #24] 8000400: 4323 orrs r3, r4 hdma->Init.Mode | hdma->Init.Priority; 8000402: 69c4 ldr r4, [r0, #28] 8000404: 4323 orrs r3, r4 tmp |= hdma->Init.Direction | 8000406: 4313 orrs r3, r2 /* Write to DMA Channel CR register */ hdma->Instance->CCR = tmp; 8000408: 600b str r3, [r1, #0] /* Initialise the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; /* Initialize the DMA state*/ hdma->State = HAL_DMA_STATE_READY; 800040a: 2201 movs r2, #1 hdma->ErrorCode = HAL_DMA_ERROR_NONE; 800040c: 2300 movs r3, #0 hdma->State = HAL_DMA_STATE_READY; 800040e: f880 2021 strb.w r2, [r0, #33] ; 0x21 hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8000412: 6383 str r3, [r0, #56] ; 0x38 /* Allocate lock resource and initialize it */ hdma->Lock = HAL_UNLOCKED; 8000414: f880 3020 strb.w r3, [r0, #32] return HAL_OK; 8000418: 4618 mov r0, r3 800041a: bd10 pop {r4, pc} hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; 800041c: 4b06 ldr r3, [pc, #24] ; (8000438 ) 800041e: 440b add r3, r1 8000420: fbb3 f3f4 udiv r3, r3, r4 8000424: 009b lsls r3, r3, #2 8000426: 6403 str r3, [r0, #64] ; 0x40 hdma->DmaBaseAddress = DMA2; 8000428: 4b04 ldr r3, [pc, #16] ; (800043c ) 800042a: e7d9 b.n 80003e0 return HAL_ERROR; 800042c: 2001 movs r0, #1 } 800042e: bd10 pop {r4, pc} 8000430: 40020407 .word 0x40020407 8000434: bffdfff8 .word 0xbffdfff8 8000438: bffdfbf8 .word 0xbffdfbf8 800043c: 40020400 .word 0x40020400 08000440 : * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 8000440: b5f0 push {r4, r5, r6, r7, lr} /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Process locked */ __HAL_LOCK(hdma); 8000442: f890 4020 ldrb.w r4, [r0, #32] 8000446: 2c01 cmp r4, #1 8000448: d035 beq.n 80004b6 800044a: 2401 movs r4, #1 if(HAL_DMA_STATE_READY == hdma->State) 800044c: f890 5021 ldrb.w r5, [r0, #33] ; 0x21 __HAL_LOCK(hdma); 8000450: f880 4020 strb.w r4, [r0, #32] if(HAL_DMA_STATE_READY == hdma->State) 8000454: 42a5 cmp r5, r4 8000456: f04f 0600 mov.w r6, #0 800045a: f04f 0402 mov.w r4, #2 800045e: d128 bne.n 80004b2 { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8000460: f880 4021 strb.w r4, [r0, #33] ; 0x21 hdma->ErrorCode = HAL_DMA_ERROR_NONE; /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); 8000464: 6804 ldr r4, [r0, #0] hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8000466: 6386 str r6, [r0, #56] ; 0x38 __HAL_DMA_DISABLE(hdma); 8000468: 6826 ldr r6, [r4, #0] * @retval HAL status */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); 800046a: 6c07 ldr r7, [r0, #64] ; 0x40 __HAL_DMA_DISABLE(hdma); 800046c: f026 0601 bic.w r6, r6, #1 8000470: 6026 str r6, [r4, #0] hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); 8000472: 6bc6 ldr r6, [r0, #60] ; 0x3c 8000474: 40bd lsls r5, r7 8000476: 6075 str r5, [r6, #4] /* Configure DMA Channel data length */ hdma->Instance->CNDTR = DataLength; 8000478: 6063 str r3, [r4, #4] /* Memory to Peripheral */ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 800047a: 6843 ldr r3, [r0, #4] 800047c: 6805 ldr r5, [r0, #0] 800047e: 2b10 cmp r3, #16 if(NULL != hdma->XferHalfCpltCallback) 8000480: 6ac3 ldr r3, [r0, #44] ; 0x2c { /* Configure DMA Channel destination address */ hdma->Instance->CPAR = DstAddress; 8000482: bf0b itete eq 8000484: 60a2 streq r2, [r4, #8] } /* Peripheral to Memory */ else { /* Configure DMA Channel source address */ hdma->Instance->CPAR = SrcAddress; 8000486: 60a1 strne r1, [r4, #8] hdma->Instance->CMAR = SrcAddress; 8000488: 60e1 streq r1, [r4, #12] /* Configure DMA Channel destination address */ hdma->Instance->CMAR = DstAddress; 800048a: 60e2 strne r2, [r4, #12] if(NULL != hdma->XferHalfCpltCallback) 800048c: b14b cbz r3, 80004a2 __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 800048e: 6823 ldr r3, [r4, #0] 8000490: f043 030e orr.w r3, r3, #14 __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); 8000494: 6023 str r3, [r4, #0] __HAL_DMA_ENABLE(hdma); 8000496: 682b ldr r3, [r5, #0] HAL_StatusTypeDef status = HAL_OK; 8000498: 2000 movs r0, #0 __HAL_DMA_ENABLE(hdma); 800049a: f043 0301 orr.w r3, r3, #1 800049e: 602b str r3, [r5, #0] 80004a0: bdf0 pop {r4, r5, r6, r7, pc} __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 80004a2: 6823 ldr r3, [r4, #0] 80004a4: f023 0304 bic.w r3, r3, #4 80004a8: 6023 str r3, [r4, #0] __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); 80004aa: 6823 ldr r3, [r4, #0] 80004ac: f043 030a orr.w r3, r3, #10 80004b0: e7f0 b.n 8000494 __HAL_UNLOCK(hdma); 80004b2: f880 6020 strb.w r6, [r0, #32] __HAL_LOCK(hdma); 80004b6: 2002 movs r0, #2 } 80004b8: bdf0 pop {r4, r5, r6, r7, pc} ... 080004bc : if(HAL_DMA_STATE_BUSY != hdma->State) 80004bc: f890 3021 ldrb.w r3, [r0, #33] ; 0x21 { 80004c0: b510 push {r4, lr} if(HAL_DMA_STATE_BUSY != hdma->State) 80004c2: 2b02 cmp r3, #2 80004c4: d003 beq.n 80004ce hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 80004c6: 2304 movs r3, #4 80004c8: 6383 str r3, [r0, #56] ; 0x38 status = HAL_ERROR; 80004ca: 2001 movs r0, #1 80004cc: bd10 pop {r4, pc} __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 80004ce: 6803 ldr r3, [r0, #0] 80004d0: 681a ldr r2, [r3, #0] 80004d2: f022 020e bic.w r2, r2, #14 80004d6: 601a str r2, [r3, #0] __HAL_DMA_DISABLE(hdma); 80004d8: 681a ldr r2, [r3, #0] 80004da: f022 0201 bic.w r2, r2, #1 80004de: 601a str r2, [r3, #0] __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); 80004e0: 4a29 ldr r2, [pc, #164] ; (8000588 ) 80004e2: 4293 cmp r3, r2 80004e4: d924 bls.n 8000530 80004e6: f502 7262 add.w r2, r2, #904 ; 0x388 80004ea: 4293 cmp r3, r2 80004ec: d019 beq.n 8000522 80004ee: 3214 adds r2, #20 80004f0: 4293 cmp r3, r2 80004f2: d018 beq.n 8000526 80004f4: 3214 adds r2, #20 80004f6: 4293 cmp r3, r2 80004f8: d017 beq.n 800052a 80004fa: 3214 adds r2, #20 80004fc: 4293 cmp r3, r2 80004fe: bf0c ite eq 8000500: f44f 5380 moveq.w r3, #4096 ; 0x1000 8000504: f44f 3380 movne.w r3, #65536 ; 0x10000 8000508: 4a20 ldr r2, [pc, #128] ; (800058c ) 800050a: 6053 str r3, [r2, #4] hdma->State = HAL_DMA_STATE_READY; 800050c: 2301 movs r3, #1 __HAL_UNLOCK(hdma); 800050e: 2400 movs r4, #0 hdma->State = HAL_DMA_STATE_READY; 8000510: f880 3021 strb.w r3, [r0, #33] ; 0x21 if(hdma->XferAbortCallback != NULL) 8000514: 6b43 ldr r3, [r0, #52] ; 0x34 __HAL_UNLOCK(hdma); 8000516: f880 4020 strb.w r4, [r0, #32] if(hdma->XferAbortCallback != NULL) 800051a: b39b cbz r3, 8000584 hdma->XferAbortCallback(hdma); 800051c: 4798 blx r3 HAL_StatusTypeDef status = HAL_OK; 800051e: 4620 mov r0, r4 8000520: bd10 pop {r4, pc} __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); 8000522: 2301 movs r3, #1 8000524: e7f0 b.n 8000508 8000526: 2310 movs r3, #16 8000528: e7ee b.n 8000508 800052a: f44f 7380 mov.w r3, #256 ; 0x100 800052e: e7eb b.n 8000508 8000530: 4917 ldr r1, [pc, #92] ; (8000590 ) 8000532: 428b cmp r3, r1 8000534: d016 beq.n 8000564 8000536: 3114 adds r1, #20 8000538: 428b cmp r3, r1 800053a: d015 beq.n 8000568 800053c: 3114 adds r1, #20 800053e: 428b cmp r3, r1 8000540: d014 beq.n 800056c 8000542: 3114 adds r1, #20 8000544: 428b cmp r3, r1 8000546: d014 beq.n 8000572 8000548: 3114 adds r1, #20 800054a: 428b cmp r3, r1 800054c: d014 beq.n 8000578 800054e: 3114 adds r1, #20 8000550: 428b cmp r3, r1 8000552: d014 beq.n 800057e 8000554: 4293 cmp r3, r2 8000556: bf14 ite ne 8000558: f44f 3380 movne.w r3, #65536 ; 0x10000 800055c: f04f 7380 moveq.w r3, #16777216 ; 0x1000000 8000560: 4a0c ldr r2, [pc, #48] ; (8000594 ) 8000562: e7d2 b.n 800050a 8000564: 2301 movs r3, #1 8000566: e7fb b.n 8000560 8000568: 2310 movs r3, #16 800056a: e7f9 b.n 8000560 800056c: f44f 7380 mov.w r3, #256 ; 0x100 8000570: e7f6 b.n 8000560 8000572: f44f 5380 mov.w r3, #4096 ; 0x1000 8000576: e7f3 b.n 8000560 8000578: f44f 3380 mov.w r3, #65536 ; 0x10000 800057c: e7f0 b.n 8000560 800057e: f44f 1380 mov.w r3, #1048576 ; 0x100000 8000582: e7ed b.n 8000560 HAL_StatusTypeDef status = HAL_OK; 8000584: 4618 mov r0, r3 } 8000586: bd10 pop {r4, pc} 8000588: 40020080 .word 0x40020080 800058c: 40020400 .word 0x40020400 8000590: 40020008 .word 0x40020008 8000594: 40020000 .word 0x40020000 08000598 : { 8000598: b470 push {r4, r5, r6} if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET)) 800059a: 2504 movs r5, #4 uint32_t flag_it = hdma->DmaBaseAddress->ISR; 800059c: 6bc6 ldr r6, [r0, #60] ; 0x3c if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET)) 800059e: 6c02 ldr r2, [r0, #64] ; 0x40 uint32_t flag_it = hdma->DmaBaseAddress->ISR; 80005a0: 6834 ldr r4, [r6, #0] uint32_t source_it = hdma->Instance->CCR; 80005a2: 6803 ldr r3, [r0, #0] if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET)) 80005a4: 4095 lsls r5, r2 80005a6: 4225 tst r5, r4 uint32_t source_it = hdma->Instance->CCR; 80005a8: 6819 ldr r1, [r3, #0] if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET)) 80005aa: d055 beq.n 8000658 80005ac: 074d lsls r5, r1, #29 80005ae: d553 bpl.n 8000658 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 80005b0: 681a ldr r2, [r3, #0] 80005b2: 0696 lsls r6, r2, #26 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 80005b4: bf5e ittt pl 80005b6: 681a ldrpl r2, [r3, #0] 80005b8: f022 0204 bicpl.w r2, r2, #4 80005bc: 601a strpl r2, [r3, #0] __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); 80005be: 4a60 ldr r2, [pc, #384] ; (8000740 ) 80005c0: 4293 cmp r3, r2 80005c2: d91f bls.n 8000604 80005c4: f502 7262 add.w r2, r2, #904 ; 0x388 80005c8: 4293 cmp r3, r2 80005ca: d014 beq.n 80005f6 80005cc: 3214 adds r2, #20 80005ce: 4293 cmp r3, r2 80005d0: d013 beq.n 80005fa 80005d2: 3214 adds r2, #20 80005d4: 4293 cmp r3, r2 80005d6: d012 beq.n 80005fe 80005d8: 3214 adds r2, #20 80005da: 4293 cmp r3, r2 80005dc: bf0c ite eq 80005de: f44f 4380 moveq.w r3, #16384 ; 0x4000 80005e2: f44f 2380 movne.w r3, #262144 ; 0x40000 80005e6: 4a57 ldr r2, [pc, #348] ; (8000744 ) 80005e8: 6053 str r3, [r2, #4] if(hdma->XferHalfCpltCallback != NULL) 80005ea: 6ac3 ldr r3, [r0, #44] ; 0x2c if (hdma->XferErrorCallback != NULL) 80005ec: 2b00 cmp r3, #0 80005ee: f000 80a5 beq.w 800073c } 80005f2: bc70 pop {r4, r5, r6} hdma->XferErrorCallback(hdma); 80005f4: 4718 bx r3 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); 80005f6: 2304 movs r3, #4 80005f8: e7f5 b.n 80005e6 80005fa: 2340 movs r3, #64 ; 0x40 80005fc: e7f3 b.n 80005e6 80005fe: f44f 6380 mov.w r3, #1024 ; 0x400 8000602: e7f0 b.n 80005e6 8000604: 4950 ldr r1, [pc, #320] ; (8000748 ) 8000606: 428b cmp r3, r1 8000608: d016 beq.n 8000638 800060a: 3114 adds r1, #20 800060c: 428b cmp r3, r1 800060e: d015 beq.n 800063c 8000610: 3114 adds r1, #20 8000612: 428b cmp r3, r1 8000614: d014 beq.n 8000640 8000616: 3114 adds r1, #20 8000618: 428b cmp r3, r1 800061a: d014 beq.n 8000646 800061c: 3114 adds r1, #20 800061e: 428b cmp r3, r1 8000620: d014 beq.n 800064c 8000622: 3114 adds r1, #20 8000624: 428b cmp r3, r1 8000626: d014 beq.n 8000652 8000628: 4293 cmp r3, r2 800062a: bf14 ite ne 800062c: f44f 2380 movne.w r3, #262144 ; 0x40000 8000630: f04f 6380 moveq.w r3, #67108864 ; 0x4000000 8000634: 4a45 ldr r2, [pc, #276] ; (800074c ) 8000636: e7d7 b.n 80005e8 8000638: 2304 movs r3, #4 800063a: e7fb b.n 8000634 800063c: 2340 movs r3, #64 ; 0x40 800063e: e7f9 b.n 8000634 8000640: f44f 6380 mov.w r3, #1024 ; 0x400 8000644: e7f6 b.n 8000634 8000646: f44f 4380 mov.w r3, #16384 ; 0x4000 800064a: e7f3 b.n 8000634 800064c: f44f 2380 mov.w r3, #262144 ; 0x40000 8000650: e7f0 b.n 8000634 8000652: f44f 0380 mov.w r3, #4194304 ; 0x400000 8000656: e7ed b.n 8000634 else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET)) 8000658: 2502 movs r5, #2 800065a: 4095 lsls r5, r2 800065c: 4225 tst r5, r4 800065e: d057 beq.n 8000710 8000660: 078d lsls r5, r1, #30 8000662: d555 bpl.n 8000710 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 8000664: 681a ldr r2, [r3, #0] 8000666: 0694 lsls r4, r2, #26 8000668: d406 bmi.n 8000678 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); 800066a: 681a ldr r2, [r3, #0] 800066c: f022 020a bic.w r2, r2, #10 8000670: 601a str r2, [r3, #0] hdma->State = HAL_DMA_STATE_READY; 8000672: 2201 movs r2, #1 8000674: f880 2021 strb.w r2, [r0, #33] ; 0x21 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); 8000678: 4a31 ldr r2, [pc, #196] ; (8000740 ) 800067a: 4293 cmp r3, r2 800067c: d91e bls.n 80006bc 800067e: f502 7262 add.w r2, r2, #904 ; 0x388 8000682: 4293 cmp r3, r2 8000684: d013 beq.n 80006ae 8000686: 3214 adds r2, #20 8000688: 4293 cmp r3, r2 800068a: d012 beq.n 80006b2 800068c: 3214 adds r2, #20 800068e: 4293 cmp r3, r2 8000690: d011 beq.n 80006b6 8000692: 3214 adds r2, #20 8000694: 4293 cmp r3, r2 8000696: bf0c ite eq 8000698: f44f 5300 moveq.w r3, #8192 ; 0x2000 800069c: f44f 3300 movne.w r3, #131072 ; 0x20000 80006a0: 4a28 ldr r2, [pc, #160] ; (8000744 ) 80006a2: 6053 str r3, [r2, #4] __HAL_UNLOCK(hdma); 80006a4: 2300 movs r3, #0 80006a6: f880 3020 strb.w r3, [r0, #32] if(hdma->XferCpltCallback != NULL) 80006aa: 6a83 ldr r3, [r0, #40] ; 0x28 80006ac: e79e b.n 80005ec __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); 80006ae: 2302 movs r3, #2 80006b0: e7f6 b.n 80006a0 80006b2: 2320 movs r3, #32 80006b4: e7f4 b.n 80006a0 80006b6: f44f 7300 mov.w r3, #512 ; 0x200 80006ba: e7f1 b.n 80006a0 80006bc: 4922 ldr r1, [pc, #136] ; (8000748 ) 80006be: 428b cmp r3, r1 80006c0: d016 beq.n 80006f0 80006c2: 3114 adds r1, #20 80006c4: 428b cmp r3, r1 80006c6: d015 beq.n 80006f4 80006c8: 3114 adds r1, #20 80006ca: 428b cmp r3, r1 80006cc: d014 beq.n 80006f8 80006ce: 3114 adds r1, #20 80006d0: 428b cmp r3, r1 80006d2: d014 beq.n 80006fe 80006d4: 3114 adds r1, #20 80006d6: 428b cmp r3, r1 80006d8: d014 beq.n 8000704 80006da: 3114 adds r1, #20 80006dc: 428b cmp r3, r1 80006de: d014 beq.n 800070a 80006e0: 4293 cmp r3, r2 80006e2: bf14 ite ne 80006e4: f44f 3300 movne.w r3, #131072 ; 0x20000 80006e8: f04f 7300 moveq.w r3, #33554432 ; 0x2000000 80006ec: 4a17 ldr r2, [pc, #92] ; (800074c ) 80006ee: e7d8 b.n 80006a2 80006f0: 2302 movs r3, #2 80006f2: e7fb b.n 80006ec 80006f4: 2320 movs r3, #32 80006f6: e7f9 b.n 80006ec 80006f8: f44f 7300 mov.w r3, #512 ; 0x200 80006fc: e7f6 b.n 80006ec 80006fe: f44f 5300 mov.w r3, #8192 ; 0x2000 8000702: e7f3 b.n 80006ec 8000704: f44f 3300 mov.w r3, #131072 ; 0x20000 8000708: e7f0 b.n 80006ec 800070a: f44f 1300 mov.w r3, #2097152 ; 0x200000 800070e: e7ed b.n 80006ec else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE))) 8000710: 2508 movs r5, #8 8000712: 4095 lsls r5, r2 8000714: 4225 tst r5, r4 8000716: d011 beq.n 800073c 8000718: 0709 lsls r1, r1, #28 800071a: d50f bpl.n 800073c __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 800071c: 6819 ldr r1, [r3, #0] 800071e: f021 010e bic.w r1, r1, #14 8000722: 6019 str r1, [r3, #0] hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); 8000724: 2301 movs r3, #1 8000726: fa03 f202 lsl.w r2, r3, r2 800072a: 6072 str r2, [r6, #4] hdma->ErrorCode = HAL_DMA_ERROR_TE; 800072c: 6383 str r3, [r0, #56] ; 0x38 hdma->State = HAL_DMA_STATE_READY; 800072e: f880 3021 strb.w r3, [r0, #33] ; 0x21 __HAL_UNLOCK(hdma); 8000732: 2300 movs r3, #0 8000734: f880 3020 strb.w r3, [r0, #32] if (hdma->XferErrorCallback != NULL) 8000738: 6b03 ldr r3, [r0, #48] ; 0x30 800073a: e757 b.n 80005ec } 800073c: bc70 pop {r4, r5, r6} 800073e: 4770 bx lr 8000740: 40020080 .word 0x40020080 8000744: 40020400 .word 0x40020400 8000748: 40020008 .word 0x40020008 800074c: 40020000 .word 0x40020000 08000750 : uint32_t flags = 0U; #if defined(FLASH_BANK2_END) if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2)) #else if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) 8000750: 4a11 ldr r2, [pc, #68] ; (8000798 ) 8000752: 68d3 ldr r3, [r2, #12] 8000754: f013 0310 ands.w r3, r3, #16 8000758: d005 beq.n 8000766 #endif /* FLASH_BANK2_END */ { pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; 800075a: 4910 ldr r1, [pc, #64] ; (800079c ) 800075c: 69cb ldr r3, [r1, #28] 800075e: f043 0302 orr.w r3, r3, #2 8000762: 61cb str r3, [r1, #28] #if defined(FLASH_BANK2_END) flags |= FLASH_FLAG_WRPERR | FLASH_FLAG_WRPERR_BANK2; #else flags |= FLASH_FLAG_WRPERR; 8000764: 2310 movs r3, #16 #endif /* FLASH_BANK2_END */ } #if defined(FLASH_BANK2_END) if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2)) #else if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) 8000766: 68d2 ldr r2, [r2, #12] 8000768: 0750 lsls r0, r2, #29 800076a: d506 bpl.n 800077a #endif /* FLASH_BANK2_END */ { pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG; 800076c: 490b ldr r1, [pc, #44] ; (800079c ) #if defined(FLASH_BANK2_END) flags |= FLASH_FLAG_PGERR | FLASH_FLAG_PGERR_BANK2; #else flags |= FLASH_FLAG_PGERR; 800076e: f043 0304 orr.w r3, r3, #4 pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG; 8000772: 69ca ldr r2, [r1, #28] 8000774: f042 0201 orr.w r2, r2, #1 8000778: 61ca str r2, [r1, #28] #endif /* FLASH_BANK2_END */ } if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) 800077a: 4a07 ldr r2, [pc, #28] ; (8000798 ) 800077c: 69d1 ldr r1, [r2, #28] 800077e: 07c9 lsls r1, r1, #31 8000780: d508 bpl.n 8000794 { pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV; 8000782: 4806 ldr r0, [pc, #24] ; (800079c ) 8000784: 69c1 ldr r1, [r0, #28] 8000786: f041 0104 orr.w r1, r1, #4 800078a: 61c1 str r1, [r0, #28] __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR); 800078c: 69d1 ldr r1, [r2, #28] 800078e: f021 0101 bic.w r1, r1, #1 8000792: 61d1 str r1, [r2, #28] } /* Clear FLASH error pending bits */ __HAL_FLASH_CLEAR_FLAG(flags); 8000794: 60d3 str r3, [r2, #12] 8000796: 4770 bx lr 8000798: 40022000 .word 0x40022000 800079c: 200004d0 .word 0x200004d0 080007a0 : if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) 80007a0: 4b06 ldr r3, [pc, #24] ; (80007bc ) 80007a2: 6918 ldr r0, [r3, #16] 80007a4: f010 0080 ands.w r0, r0, #128 ; 0x80 80007a8: d007 beq.n 80007ba WRITE_REG(FLASH->KEYR, FLASH_KEY1); 80007aa: 4a05 ldr r2, [pc, #20] ; (80007c0 ) 80007ac: 605a str r2, [r3, #4] WRITE_REG(FLASH->KEYR, FLASH_KEY2); 80007ae: f102 3288 add.w r2, r2, #2290649224 ; 0x88888888 80007b2: 605a str r2, [r3, #4] if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) 80007b4: 6918 ldr r0, [r3, #16] HAL_StatusTypeDef status = HAL_OK; 80007b6: f3c0 10c0 ubfx r0, r0, #7, #1 } 80007ba: 4770 bx lr 80007bc: 40022000 .word 0x40022000 80007c0: 45670123 .word 0x45670123 080007c4 : SET_BIT(FLASH->CR, FLASH_CR_LOCK); 80007c4: 4a03 ldr r2, [pc, #12] ; (80007d4 ) } 80007c6: 2000 movs r0, #0 SET_BIT(FLASH->CR, FLASH_CR_LOCK); 80007c8: 6913 ldr r3, [r2, #16] 80007ca: f043 0380 orr.w r3, r3, #128 ; 0x80 80007ce: 6113 str r3, [r2, #16] } 80007d0: 4770 bx lr 80007d2: bf00 nop 80007d4: 40022000 .word 0x40022000 080007d8 : { 80007d8: b5f8 push {r3, r4, r5, r6, r7, lr} 80007da: 4606 mov r6, r0 uint32_t tickstart = HAL_GetTick(); 80007dc: f7ff fd70 bl 80002c0 while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) 80007e0: 4c11 ldr r4, [pc, #68] ; (8000828 ) uint32_t tickstart = HAL_GetTick(); 80007e2: 4607 mov r7, r0 80007e4: 4625 mov r5, r4 while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) 80007e6: 68e3 ldr r3, [r4, #12] 80007e8: 07d8 lsls r0, r3, #31 80007ea: d412 bmi.n 8000812 if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) 80007ec: 68e3 ldr r3, [r4, #12] 80007ee: 0699 lsls r1, r3, #26 __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); 80007f0: bf44 itt mi 80007f2: 2320 movmi r3, #32 80007f4: 60e3 strmi r3, [r4, #12] if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || 80007f6: 68eb ldr r3, [r5, #12] 80007f8: 06da lsls r2, r3, #27 80007fa: d406 bmi.n 800080a __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || 80007fc: 69eb ldr r3, [r5, #28] if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || 80007fe: 07db lsls r3, r3, #31 8000800: d403 bmi.n 800080a __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) 8000802: 68e8 ldr r0, [r5, #12] __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || 8000804: f010 0004 ands.w r0, r0, #4 8000808: d002 beq.n 8000810 FLASH_SetErrorCode(); 800080a: f7ff ffa1 bl 8000750 return HAL_ERROR; 800080e: 2001 movs r0, #1 } 8000810: bdf8 pop {r3, r4, r5, r6, r7, pc} if (Timeout != HAL_MAX_DELAY) 8000812: 1c73 adds r3, r6, #1 8000814: d0e7 beq.n 80007e6 if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) 8000816: b90e cbnz r6, 800081c return HAL_TIMEOUT; 8000818: 2003 movs r0, #3 800081a: bdf8 pop {r3, r4, r5, r6, r7, pc} if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) 800081c: f7ff fd50 bl 80002c0 8000820: 1bc0 subs r0, r0, r7 8000822: 4286 cmp r6, r0 8000824: d2df bcs.n 80007e6 8000826: e7f7 b.n 8000818 8000828: 40022000 .word 0x40022000 0800082c : { 800082c: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} __HAL_LOCK(&pFlash); 8000830: 4c1f ldr r4, [pc, #124] ; (80008b0 ) { 8000832: 4699 mov r9, r3 __HAL_LOCK(&pFlash); 8000834: 7e23 ldrb r3, [r4, #24] { 8000836: 4605 mov r5, r0 __HAL_LOCK(&pFlash); 8000838: 2b01 cmp r3, #1 { 800083a: 460f mov r7, r1 800083c: 4690 mov r8, r2 __HAL_LOCK(&pFlash); 800083e: d033 beq.n 80008a8 8000840: 2301 movs r3, #1 status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); 8000842: f24c 3050 movw r0, #50000 ; 0xc350 __HAL_LOCK(&pFlash); 8000846: 7623 strb r3, [r4, #24] status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); 8000848: f7ff ffc6 bl 80007d8 if(status == HAL_OK) 800084c: bb40 cbnz r0, 80008a0 if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) 800084e: 2d01 cmp r5, #1 8000850: d003 beq.n 800085a nbiterations = 4U; 8000852: 2d02 cmp r5, #2 8000854: bf0c ite eq 8000856: 2502 moveq r5, #2 8000858: 2504 movne r5, #4 800085a: 2600 movs r6, #0 pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; 800085c: 46b2 mov sl, r6 SET_BIT(FLASH->CR, FLASH_CR_PG); 800085e: f8df b054 ldr.w fp, [pc, #84] ; 80008b4 FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index))); 8000862: 0132 lsls r2, r6, #4 8000864: 4640 mov r0, r8 8000866: 4649 mov r1, r9 8000868: f7ff fcdc bl 8000224 <__aeabi_llsr> pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; 800086c: f8c4 a01c str.w sl, [r4, #28] SET_BIT(FLASH->CR, FLASH_CR_PG); 8000870: f8db 3010 ldr.w r3, [fp, #16] FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index))); 8000874: b280 uxth r0, r0 SET_BIT(FLASH->CR, FLASH_CR_PG); 8000876: f043 0301 orr.w r3, r3, #1 800087a: f8cb 3010 str.w r3, [fp, #16] *(__IO uint16_t*)Address = Data; 800087e: f827 0016 strh.w r0, [r7, r6, lsl #1] status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); 8000882: f24c 3050 movw r0, #50000 ; 0xc350 8000886: f7ff ffa7 bl 80007d8 CLEAR_BIT(FLASH->CR, FLASH_CR_PG); 800088a: f8db 3010 ldr.w r3, [fp, #16] 800088e: f023 0301 bic.w r3, r3, #1 8000892: f8cb 3010 str.w r3, [fp, #16] if (status != HAL_OK) 8000896: b918 cbnz r0, 80008a0 8000898: 3601 adds r6, #1 for (index = 0U; index < nbiterations; index++) 800089a: b2f3 uxtb r3, r6 800089c: 429d cmp r5, r3 800089e: d8e0 bhi.n 8000862 __HAL_UNLOCK(&pFlash); 80008a0: 2300 movs r3, #0 80008a2: 7623 strb r3, [r4, #24] return status; 80008a4: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc} __HAL_LOCK(&pFlash); 80008a8: 2002 movs r0, #2 } 80008aa: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc} 80008ae: bf00 nop 80008b0: 200004d0 .word 0x200004d0 80008b4: 40022000 .word 0x40022000 080008b8 : { /* Check the parameters */ assert_param(IS_FLASH_BANK(Banks)); /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; 80008b8: 2200 movs r2, #0 80008ba: 4b06 ldr r3, [pc, #24] ; (80008d4 ) 80008bc: 61da str r2, [r3, #28] #if !defined(FLASH_BANK2_END) /* Prevent unused argument(s) compilation warning */ UNUSED(Banks); #endif /* FLASH_BANK2_END */ /* Only bank1 will be erased*/ SET_BIT(FLASH->CR, FLASH_CR_MER); 80008be: 4b06 ldr r3, [pc, #24] ; (80008d8 ) 80008c0: 691a ldr r2, [r3, #16] 80008c2: f042 0204 orr.w r2, r2, #4 80008c6: 611a str r2, [r3, #16] SET_BIT(FLASH->CR, FLASH_CR_STRT); 80008c8: 691a ldr r2, [r3, #16] 80008ca: f042 0240 orr.w r2, r2, #64 ; 0x40 80008ce: 611a str r2, [r3, #16] 80008d0: 4770 bx lr 80008d2: bf00 nop 80008d4: 200004d0 .word 0x200004d0 80008d8: 40022000 .word 0x40022000 080008dc : * @retval None */ void FLASH_PageErase(uint32_t PageAddress) { /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; 80008dc: 2200 movs r2, #0 80008de: 4b06 ldr r3, [pc, #24] ; (80008f8 ) 80008e0: 61da str r2, [r3, #28] } else { #endif /* FLASH_BANK2_END */ /* Proceed to erase the page */ SET_BIT(FLASH->CR, FLASH_CR_PER); 80008e2: 4b06 ldr r3, [pc, #24] ; (80008fc ) 80008e4: 691a ldr r2, [r3, #16] 80008e6: f042 0202 orr.w r2, r2, #2 80008ea: 611a str r2, [r3, #16] WRITE_REG(FLASH->AR, PageAddress); 80008ec: 6158 str r0, [r3, #20] SET_BIT(FLASH->CR, FLASH_CR_STRT); 80008ee: 691a ldr r2, [r3, #16] 80008f0: f042 0240 orr.w r2, r2, #64 ; 0x40 80008f4: 611a str r2, [r3, #16] 80008f6: 4770 bx lr 80008f8: 200004d0 .word 0x200004d0 80008fc: 40022000 .word 0x40022000 08000900 : { 8000900: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} __HAL_LOCK(&pFlash); 8000904: 4d23 ldr r5, [pc, #140] ; (8000994 ) { 8000906: 4607 mov r7, r0 __HAL_LOCK(&pFlash); 8000908: 7e2b ldrb r3, [r5, #24] { 800090a: 4688 mov r8, r1 __HAL_LOCK(&pFlash); 800090c: 2b01 cmp r3, #1 800090e: d03d beq.n 800098c 8000910: 2401 movs r4, #1 if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) 8000912: 6803 ldr r3, [r0, #0] __HAL_LOCK(&pFlash); 8000914: 762c strb r4, [r5, #24] if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) 8000916: 2b02 cmp r3, #2 if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) 8000918: f24c 3050 movw r0, #50000 ; 0xc350 if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) 800091c: d113 bne.n 8000946 if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) 800091e: f7ff ff5b bl 80007d8 8000922: b120 cbz r0, 800092e HAL_StatusTypeDef status = HAL_ERROR; 8000924: 2001 movs r0, #1 __HAL_UNLOCK(&pFlash); 8000926: 2300 movs r3, #0 8000928: 762b strb r3, [r5, #24] return status; 800092a: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} FLASH_MassErase(FLASH_BANK_1); 800092e: f7ff ffc3 bl 80008b8 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); 8000932: f24c 3050 movw r0, #50000 ; 0xc350 8000936: f7ff ff4f bl 80007d8 CLEAR_BIT(FLASH->CR, FLASH_CR_MER); 800093a: 4a17 ldr r2, [pc, #92] ; (8000998 ) 800093c: 6913 ldr r3, [r2, #16] 800093e: f023 0304 bic.w r3, r3, #4 8000942: 6113 str r3, [r2, #16] 8000944: e7ef b.n 8000926 if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) 8000946: f7ff ff47 bl 80007d8 800094a: 2800 cmp r0, #0 800094c: d1ea bne.n 8000924 *PageError = 0xFFFFFFFFU; 800094e: f04f 33ff mov.w r3, #4294967295 8000952: f8c8 3000 str.w r3, [r8] HAL_StatusTypeDef status = HAL_ERROR; 8000956: 4620 mov r0, r4 for(address = pEraseInit->PageAddress; 8000958: 68be ldr r6, [r7, #8] CLEAR_BIT(FLASH->CR, FLASH_CR_PER); 800095a: 4c0f ldr r4, [pc, #60] ; (8000998 ) address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress); 800095c: 68fa ldr r2, [r7, #12] 800095e: 68bb ldr r3, [r7, #8] 8000960: eb03 23c2 add.w r3, r3, r2, lsl #11 for(address = pEraseInit->PageAddress; 8000964: 429e cmp r6, r3 8000966: d2de bcs.n 8000926 FLASH_PageErase(address); 8000968: 4630 mov r0, r6 800096a: f7ff ffb7 bl 80008dc status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); 800096e: f24c 3050 movw r0, #50000 ; 0xc350 8000972: f7ff ff31 bl 80007d8 CLEAR_BIT(FLASH->CR, FLASH_CR_PER); 8000976: 6923 ldr r3, [r4, #16] 8000978: f023 0302 bic.w r3, r3, #2 800097c: 6123 str r3, [r4, #16] if (status != HAL_OK) 800097e: b110 cbz r0, 8000986 *PageError = address; 8000980: f8c8 6000 str.w r6, [r8] break; 8000984: e7cf b.n 8000926 address += FLASH_PAGE_SIZE) 8000986: f506 6600 add.w r6, r6, #2048 ; 0x800 800098a: e7e7 b.n 800095c __HAL_LOCK(&pFlash); 800098c: 2002 movs r0, #2 } 800098e: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8000992: bf00 nop 8000994: 200004d0 .word 0x200004d0 8000998: 40022000 .word 0x40022000 0800099c : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 800099c: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} uint32_t position; uint32_t ioposition = 0x00U; uint32_t iocurrent = 0x00U; uint32_t temp = 0x00U; uint32_t config = 0x00U; 80009a0: 2200 movs r2, #0 assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ for (position = 0U; position < GPIO_NUMBER; position++) 80009a2: 4616 mov r6, r2 /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) { /* Enable AFIO Clock */ __HAL_RCC_AFIO_CLK_ENABLE(); 80009a4: 4f6c ldr r7, [pc, #432] ; (8000b58 ) 80009a6: 4b6d ldr r3, [pc, #436] ; (8000b5c ) temp = AFIO->EXTICR[position >> 2U]; CLEAR_BIT(temp, (0x0FU) << (4U * (position & 0x03U))); SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); 80009a8: f8df e1b8 ldr.w lr, [pc, #440] ; 8000b64 switch (GPIO_Init->Mode) 80009ac: f8df c1b8 ldr.w ip, [pc, #440] ; 8000b68 ioposition = (0x01U << position); 80009b0: f04f 0801 mov.w r8, #1 iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 80009b4: 680c ldr r4, [r1, #0] ioposition = (0x01U << position); 80009b6: fa08 f806 lsl.w r8, r8, r6 iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 80009ba: ea08 0404 and.w r4, r8, r4 if (iocurrent == ioposition) 80009be: 45a0 cmp r8, r4 80009c0: f040 8085 bne.w 8000ace switch (GPIO_Init->Mode) 80009c4: 684d ldr r5, [r1, #4] 80009c6: 2d12 cmp r5, #18 80009c8: f000 80b7 beq.w 8000b3a 80009cc: f200 808d bhi.w 8000aea 80009d0: 2d02 cmp r5, #2 80009d2: f000 80af beq.w 8000b34 80009d6: f200 8081 bhi.w 8000adc 80009da: 2d00 cmp r5, #0 80009dc: f000 8091 beq.w 8000b02 80009e0: 2d01 cmp r5, #1 80009e2: f000 80a5 beq.w 8000b30 MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); 80009e6: f04f 090f mov.w r9, #15 configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; 80009ea: 2cff cmp r4, #255 ; 0xff 80009ec: bf93 iteet ls 80009ee: 4682 movls sl, r0 80009f0: f106 4580 addhi.w r5, r6, #1073741824 ; 0x40000000 80009f4: 3d08 subhi r5, #8 80009f6: f8d0 b000 ldrls.w fp, [r0] 80009fa: bf92 itee ls 80009fc: 00b5 lslls r5, r6, #2 80009fe: f8d0 b004 ldrhi.w fp, [r0, #4] 8000a02: 00ad lslhi r5, r5, #2 MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); 8000a04: fa09 f805 lsl.w r8, r9, r5 8000a08: ea2b 0808 bic.w r8, fp, r8 8000a0c: fa02 f505 lsl.w r5, r2, r5 configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; 8000a10: bf88 it hi 8000a12: f100 0a04 addhi.w sl, r0, #4 MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); 8000a16: ea48 0505 orr.w r5, r8, r5 8000a1a: f8ca 5000 str.w r5, [sl] if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 8000a1e: f8d1 a004 ldr.w sl, [r1, #4] 8000a22: f01a 5f80 tst.w sl, #268435456 ; 0x10000000 8000a26: d052 beq.n 8000ace __HAL_RCC_AFIO_CLK_ENABLE(); 8000a28: 69bd ldr r5, [r7, #24] 8000a2a: f026 0803 bic.w r8, r6, #3 8000a2e: f045 0501 orr.w r5, r5, #1 8000a32: 61bd str r5, [r7, #24] 8000a34: 69bd ldr r5, [r7, #24] 8000a36: f108 4880 add.w r8, r8, #1073741824 ; 0x40000000 8000a3a: f005 0501 and.w r5, r5, #1 8000a3e: 9501 str r5, [sp, #4] 8000a40: f508 3880 add.w r8, r8, #65536 ; 0x10000 CLEAR_BIT(temp, (0x0FU) << (4U * (position & 0x03U))); 8000a44: f006 0b03 and.w fp, r6, #3 __HAL_RCC_AFIO_CLK_ENABLE(); 8000a48: 9d01 ldr r5, [sp, #4] CLEAR_BIT(temp, (0x0FU) << (4U * (position & 0x03U))); 8000a4a: ea4f 0b8b mov.w fp, fp, lsl #2 temp = AFIO->EXTICR[position >> 2U]; 8000a4e: f8d8 5008 ldr.w r5, [r8, #8] CLEAR_BIT(temp, (0x0FU) << (4U * (position & 0x03U))); 8000a52: fa09 f90b lsl.w r9, r9, fp 8000a56: ea25 0909 bic.w r9, r5, r9 SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); 8000a5a: 4d41 ldr r5, [pc, #260] ; (8000b60 ) 8000a5c: 42a8 cmp r0, r5 8000a5e: d071 beq.n 8000b44 8000a60: f505 6580 add.w r5, r5, #1024 ; 0x400 8000a64: 42a8 cmp r0, r5 8000a66: d06f beq.n 8000b48 8000a68: f505 6580 add.w r5, r5, #1024 ; 0x400 8000a6c: 42a8 cmp r0, r5 8000a6e: d06d beq.n 8000b4c 8000a70: f505 6580 add.w r5, r5, #1024 ; 0x400 8000a74: 42a8 cmp r0, r5 8000a76: d06b beq.n 8000b50 8000a78: f505 6580 add.w r5, r5, #1024 ; 0x400 8000a7c: 42a8 cmp r0, r5 8000a7e: d069 beq.n 8000b54 8000a80: 4570 cmp r0, lr 8000a82: bf0c ite eq 8000a84: 2505 moveq r5, #5 8000a86: 2506 movne r5, #6 8000a88: fa05 f50b lsl.w r5, r5, fp 8000a8c: ea45 0509 orr.w r5, r5, r9 AFIO->EXTICR[position >> 2U] = temp; 8000a90: f8c8 5008 str.w r5, [r8, #8] /* Configure the interrupt mask */ if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) { SET_BIT(EXTI->IMR, iocurrent); 8000a94: 681d ldr r5, [r3, #0] if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) 8000a96: f41a 3f80 tst.w sl, #65536 ; 0x10000 SET_BIT(EXTI->IMR, iocurrent); 8000a9a: bf14 ite ne 8000a9c: 4325 orrne r5, r4 } else { CLEAR_BIT(EXTI->IMR, iocurrent); 8000a9e: 43a5 biceq r5, r4 8000aa0: 601d str r5, [r3, #0] } /* Configure the event mask */ if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) { SET_BIT(EXTI->EMR, iocurrent); 8000aa2: 685d ldr r5, [r3, #4] if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) 8000aa4: f41a 3f00 tst.w sl, #131072 ; 0x20000 SET_BIT(EXTI->EMR, iocurrent); 8000aa8: bf14 ite ne 8000aaa: 4325 orrne r5, r4 } else { CLEAR_BIT(EXTI->EMR, iocurrent); 8000aac: 43a5 biceq r5, r4 8000aae: 605d str r5, [r3, #4] } /* Enable or disable the rising trigger */ if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) { SET_BIT(EXTI->RTSR, iocurrent); 8000ab0: 689d ldr r5, [r3, #8] if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) 8000ab2: f41a 1f80 tst.w sl, #1048576 ; 0x100000 SET_BIT(EXTI->RTSR, iocurrent); 8000ab6: bf14 ite ne 8000ab8: 4325 orrne r5, r4 } else { CLEAR_BIT(EXTI->RTSR, iocurrent); 8000aba: 43a5 biceq r5, r4 8000abc: 609d str r5, [r3, #8] } /* Enable or disable the falling trigger */ if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) { SET_BIT(EXTI->FTSR, iocurrent); 8000abe: 68dd ldr r5, [r3, #12] if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) 8000ac0: f41a 1f00 tst.w sl, #2097152 ; 0x200000 SET_BIT(EXTI->FTSR, iocurrent); 8000ac4: bf14 ite ne 8000ac6: 432c orrne r4, r5 } else { CLEAR_BIT(EXTI->FTSR, iocurrent); 8000ac8: ea25 0404 biceq.w r4, r5, r4 8000acc: 60dc str r4, [r3, #12] for (position = 0U; position < GPIO_NUMBER; position++) 8000ace: 3601 adds r6, #1 8000ad0: 2e10 cmp r6, #16 8000ad2: f47f af6d bne.w 80009b0 } } } } } 8000ad6: b003 add sp, #12 8000ad8: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} switch (GPIO_Init->Mode) 8000adc: 2d03 cmp r5, #3 8000ade: d025 beq.n 8000b2c 8000ae0: 2d11 cmp r5, #17 8000ae2: d180 bne.n 80009e6 config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; 8000ae4: 68ca ldr r2, [r1, #12] 8000ae6: 3204 adds r2, #4 break; 8000ae8: e77d b.n 80009e6 switch (GPIO_Init->Mode) 8000aea: 4565 cmp r5, ip 8000aec: d009 beq.n 8000b02 8000aee: d812 bhi.n 8000b16 8000af0: f8df 9078 ldr.w r9, [pc, #120] ; 8000b6c 8000af4: 454d cmp r5, r9 8000af6: d004 beq.n 8000b02 8000af8: f509 3980 add.w r9, r9, #65536 ; 0x10000 8000afc: 454d cmp r5, r9 8000afe: f47f af72 bne.w 80009e6 if (GPIO_Init->Pull == GPIO_NOPULL) 8000b02: 688a ldr r2, [r1, #8] 8000b04: b1e2 cbz r2, 8000b40 else if (GPIO_Init->Pull == GPIO_PULLUP) 8000b06: 2a01 cmp r2, #1 GPIOx->BSRR = ioposition; 8000b08: bf0c ite eq 8000b0a: f8c0 8010 streq.w r8, [r0, #16] GPIOx->BRR = ioposition; 8000b0e: f8c0 8014 strne.w r8, [r0, #20] config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 8000b12: 2208 movs r2, #8 8000b14: e767 b.n 80009e6 switch (GPIO_Init->Mode) 8000b16: f8df 9058 ldr.w r9, [pc, #88] ; 8000b70 8000b1a: 454d cmp r5, r9 8000b1c: d0f1 beq.n 8000b02 8000b1e: f509 3980 add.w r9, r9, #65536 ; 0x10000 8000b22: 454d cmp r5, r9 8000b24: d0ed beq.n 8000b02 8000b26: f5a9 1980 sub.w r9, r9, #1048576 ; 0x100000 8000b2a: e7e7 b.n 8000afc config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; 8000b2c: 2200 movs r2, #0 8000b2e: e75a b.n 80009e6 config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; 8000b30: 68ca ldr r2, [r1, #12] break; 8000b32: e758 b.n 80009e6 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; 8000b34: 68ca ldr r2, [r1, #12] 8000b36: 3208 adds r2, #8 break; 8000b38: e755 b.n 80009e6 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; 8000b3a: 68ca ldr r2, [r1, #12] 8000b3c: 320c adds r2, #12 break; 8000b3e: e752 b.n 80009e6 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; 8000b40: 2204 movs r2, #4 8000b42: e750 b.n 80009e6 SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); 8000b44: 2500 movs r5, #0 8000b46: e79f b.n 8000a88 8000b48: 2501 movs r5, #1 8000b4a: e79d b.n 8000a88 8000b4c: 2502 movs r5, #2 8000b4e: e79b b.n 8000a88 8000b50: 2503 movs r5, #3 8000b52: e799 b.n 8000a88 8000b54: 2504 movs r5, #4 8000b56: e797 b.n 8000a88 8000b58: 40021000 .word 0x40021000 8000b5c: 40010400 .word 0x40010400 8000b60: 40010800 .word 0x40010800 8000b64: 40011c00 .word 0x40011c00 8000b68: 10210000 .word 0x10210000 8000b6c: 10110000 .word 0x10110000 8000b70: 10310000 .word 0x10310000 08000b74 : { /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 8000b74: b10a cbz r2, 8000b7a { GPIOx->BSRR = GPIO_Pin; } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; 8000b76: 6101 str r1, [r0, #16] 8000b78: 4770 bx lr 8000b7a: 0409 lsls r1, r1, #16 8000b7c: e7fb b.n 8000b76 08000b7e : void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); GPIOx->ODR ^= GPIO_Pin; 8000b7e: 68c3 ldr r3, [r0, #12] 8000b80: 4059 eors r1, r3 8000b82: 60c1 str r1, [r0, #12] 8000b84: 4770 bx lr ... 08000b88 : /* Check the parameters */ assert_param(RCC_OscInitStruct != NULL); assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8000b88: 6803 ldr r3, [r0, #0] { 8000b8a: e92d 41f3 stmdb sp!, {r0, r1, r4, r5, r6, r7, r8, lr} if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8000b8e: 07db lsls r3, r3, #31 { 8000b90: 4605 mov r5, r0 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8000b92: d410 bmi.n 8000bb6 } } } } /*----------------------------- HSI Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8000b94: 682b ldr r3, [r5, #0] 8000b96: 079f lsls r7, r3, #30 8000b98: d45e bmi.n 8000c58 } } } } /*------------------------------ LSI Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8000b9a: 682b ldr r3, [r5, #0] 8000b9c: 0719 lsls r1, r3, #28 8000b9e: f100 8095 bmi.w 8000ccc } } } } /*------------------------------ LSE Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8000ba2: 682b ldr r3, [r5, #0] 8000ba4: 075a lsls r2, r3, #29 8000ba6: f100 80bf bmi.w 8000d28 #endif /* RCC_CR_PLL2ON */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 8000baa: 69ea ldr r2, [r5, #28] 8000bac: 2a00 cmp r2, #0 8000bae: f040 812d bne.w 8000e0c { return HAL_ERROR; } } return HAL_OK; 8000bb2: 2000 movs r0, #0 8000bb4: e014 b.n 8000be0 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 8000bb6: 4c90 ldr r4, [pc, #576] ; (8000df8 ) 8000bb8: 6863 ldr r3, [r4, #4] 8000bba: f003 030c and.w r3, r3, #12 8000bbe: 2b04 cmp r3, #4 8000bc0: d007 beq.n 8000bd2 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 8000bc2: 6863 ldr r3, [r4, #4] 8000bc4: f003 030c and.w r3, r3, #12 8000bc8: 2b08 cmp r3, #8 8000bca: d10c bne.n 8000be6 8000bcc: 6863 ldr r3, [r4, #4] 8000bce: 03de lsls r6, r3, #15 8000bd0: d509 bpl.n 8000be6 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8000bd2: 6823 ldr r3, [r4, #0] 8000bd4: 039c lsls r4, r3, #14 8000bd6: d5dd bpl.n 8000b94 8000bd8: 686b ldr r3, [r5, #4] 8000bda: 2b00 cmp r3, #0 8000bdc: d1da bne.n 8000b94 return HAL_ERROR; 8000bde: 2001 movs r0, #1 } 8000be0: b002 add sp, #8 8000be2: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8000be6: 686b ldr r3, [r5, #4] 8000be8: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8000bec: d110 bne.n 8000c10 8000bee: 6823 ldr r3, [r4, #0] 8000bf0: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8000bf4: 6023 str r3, [r4, #0] tickstart = HAL_GetTick(); 8000bf6: f7ff fb63 bl 80002c0 8000bfa: 4606 mov r6, r0 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8000bfc: 6823 ldr r3, [r4, #0] 8000bfe: 0398 lsls r0, r3, #14 8000c00: d4c8 bmi.n 8000b94 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 8000c02: f7ff fb5d bl 80002c0 8000c06: 1b80 subs r0, r0, r6 8000c08: 2864 cmp r0, #100 ; 0x64 8000c0a: d9f7 bls.n 8000bfc return HAL_TIMEOUT; 8000c0c: 2003 movs r0, #3 8000c0e: e7e7 b.n 8000be0 __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8000c10: b99b cbnz r3, 8000c3a 8000c12: 6823 ldr r3, [r4, #0] 8000c14: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8000c18: 6023 str r3, [r4, #0] 8000c1a: 6823 ldr r3, [r4, #0] 8000c1c: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8000c20: 6023 str r3, [r4, #0] tickstart = HAL_GetTick(); 8000c22: f7ff fb4d bl 80002c0 8000c26: 4606 mov r6, r0 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8000c28: 6823 ldr r3, [r4, #0] 8000c2a: 0399 lsls r1, r3, #14 8000c2c: d5b2 bpl.n 8000b94 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 8000c2e: f7ff fb47 bl 80002c0 8000c32: 1b80 subs r0, r0, r6 8000c34: 2864 cmp r0, #100 ; 0x64 8000c36: d9f7 bls.n 8000c28 8000c38: e7e8 b.n 8000c0c __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8000c3a: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 8000c3e: 6823 ldr r3, [r4, #0] 8000c40: d103 bne.n 8000c4a 8000c42: f443 2380 orr.w r3, r3, #262144 ; 0x40000 8000c46: 6023 str r3, [r4, #0] 8000c48: e7d1 b.n 8000bee 8000c4a: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8000c4e: 6023 str r3, [r4, #0] 8000c50: 6823 ldr r3, [r4, #0] 8000c52: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8000c56: e7cd b.n 8000bf4 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 8000c58: 4c67 ldr r4, [pc, #412] ; (8000df8 ) 8000c5a: 6863 ldr r3, [r4, #4] 8000c5c: f013 0f0c tst.w r3, #12 8000c60: d007 beq.n 8000c72 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) 8000c62: 6863 ldr r3, [r4, #4] 8000c64: f003 030c and.w r3, r3, #12 8000c68: 2b08 cmp r3, #8 8000c6a: d110 bne.n 8000c8e 8000c6c: 6863 ldr r3, [r4, #4] 8000c6e: 03da lsls r2, r3, #15 8000c70: d40d bmi.n 8000c8e if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8000c72: 6823 ldr r3, [r4, #0] 8000c74: 079b lsls r3, r3, #30 8000c76: d502 bpl.n 8000c7e 8000c78: 692b ldr r3, [r5, #16] 8000c7a: 2b01 cmp r3, #1 8000c7c: d1af bne.n 8000bde __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8000c7e: 6823 ldr r3, [r4, #0] 8000c80: 696a ldr r2, [r5, #20] 8000c82: f023 03f8 bic.w r3, r3, #248 ; 0xf8 8000c86: ea43 03c2 orr.w r3, r3, r2, lsl #3 8000c8a: 6023 str r3, [r4, #0] 8000c8c: e785 b.n 8000b9a if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 8000c8e: 692a ldr r2, [r5, #16] 8000c90: 4b5a ldr r3, [pc, #360] ; (8000dfc ) 8000c92: b16a cbz r2, 8000cb0 __HAL_RCC_HSI_ENABLE(); 8000c94: 2201 movs r2, #1 8000c96: 601a str r2, [r3, #0] tickstart = HAL_GetTick(); 8000c98: f7ff fb12 bl 80002c0 8000c9c: 4606 mov r6, r0 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8000c9e: 6823 ldr r3, [r4, #0] 8000ca0: 079f lsls r7, r3, #30 8000ca2: d4ec bmi.n 8000c7e if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 8000ca4: f7ff fb0c bl 80002c0 8000ca8: 1b80 subs r0, r0, r6 8000caa: 2802 cmp r0, #2 8000cac: d9f7 bls.n 8000c9e 8000cae: e7ad b.n 8000c0c __HAL_RCC_HSI_DISABLE(); 8000cb0: 601a str r2, [r3, #0] tickstart = HAL_GetTick(); 8000cb2: f7ff fb05 bl 80002c0 8000cb6: 4606 mov r6, r0 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8000cb8: 6823 ldr r3, [r4, #0] 8000cba: 0798 lsls r0, r3, #30 8000cbc: f57f af6d bpl.w 8000b9a if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 8000cc0: f7ff fafe bl 80002c0 8000cc4: 1b80 subs r0, r0, r6 8000cc6: 2802 cmp r0, #2 8000cc8: d9f6 bls.n 8000cb8 8000cca: e79f b.n 8000c0c if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 8000ccc: 69aa ldr r2, [r5, #24] 8000cce: 4c4a ldr r4, [pc, #296] ; (8000df8 ) 8000cd0: 4b4b ldr r3, [pc, #300] ; (8000e00 ) 8000cd2: b1da cbz r2, 8000d0c __HAL_RCC_LSI_ENABLE(); 8000cd4: 2201 movs r2, #1 8000cd6: 601a str r2, [r3, #0] tickstart = HAL_GetTick(); 8000cd8: f7ff faf2 bl 80002c0 8000cdc: 4606 mov r6, r0 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8000cde: 6a63 ldr r3, [r4, #36] ; 0x24 8000ce0: 079b lsls r3, r3, #30 8000ce2: d50d bpl.n 8000d00 * @param mdelay: specifies the delay time length, in milliseconds. * @retval None */ static void RCC_Delay(uint32_t mdelay) { __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U); 8000ce4: f44f 52fa mov.w r2, #8000 ; 0x1f40 8000ce8: 4b46 ldr r3, [pc, #280] ; (8000e04 ) 8000cea: 681b ldr r3, [r3, #0] 8000cec: fbb3 f3f2 udiv r3, r3, r2 8000cf0: 9301 str r3, [sp, #4] \brief No Operation \details No Operation does nothing. This instruction can be used for code alignment purposes. */ __attribute__((always_inline)) __STATIC_INLINE void __NOP(void) { __ASM volatile ("nop"); 8000cf2: bf00 nop do { __NOP(); } while (Delay --); 8000cf4: 9b01 ldr r3, [sp, #4] 8000cf6: 1e5a subs r2, r3, #1 8000cf8: 9201 str r2, [sp, #4] 8000cfa: 2b00 cmp r3, #0 8000cfc: d1f9 bne.n 8000cf2 8000cfe: e750 b.n 8000ba2 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 8000d00: f7ff fade bl 80002c0 8000d04: 1b80 subs r0, r0, r6 8000d06: 2802 cmp r0, #2 8000d08: d9e9 bls.n 8000cde 8000d0a: e77f b.n 8000c0c __HAL_RCC_LSI_DISABLE(); 8000d0c: 601a str r2, [r3, #0] tickstart = HAL_GetTick(); 8000d0e: f7ff fad7 bl 80002c0 8000d12: 4606 mov r6, r0 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8000d14: 6a63 ldr r3, [r4, #36] ; 0x24 8000d16: 079f lsls r7, r3, #30 8000d18: f57f af43 bpl.w 8000ba2 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 8000d1c: f7ff fad0 bl 80002c0 8000d20: 1b80 subs r0, r0, r6 8000d22: 2802 cmp r0, #2 8000d24: d9f6 bls.n 8000d14 8000d26: e771 b.n 8000c0c if(__HAL_RCC_PWR_IS_CLK_DISABLED()) 8000d28: 4c33 ldr r4, [pc, #204] ; (8000df8 ) 8000d2a: 69e3 ldr r3, [r4, #28] 8000d2c: 00d8 lsls r0, r3, #3 8000d2e: d424 bmi.n 8000d7a pwrclkchanged = SET; 8000d30: 2701 movs r7, #1 __HAL_RCC_PWR_CLK_ENABLE(); 8000d32: 69e3 ldr r3, [r4, #28] 8000d34: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8000d38: 61e3 str r3, [r4, #28] 8000d3a: 69e3 ldr r3, [r4, #28] 8000d3c: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8000d40: 9300 str r3, [sp, #0] 8000d42: 9b00 ldr r3, [sp, #0] if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8000d44: 4e30 ldr r6, [pc, #192] ; (8000e08 ) 8000d46: 6833 ldr r3, [r6, #0] 8000d48: 05d9 lsls r1, r3, #23 8000d4a: d518 bpl.n 8000d7e __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8000d4c: 68eb ldr r3, [r5, #12] 8000d4e: 2b01 cmp r3, #1 8000d50: d126 bne.n 8000da0 8000d52: 6a23 ldr r3, [r4, #32] 8000d54: f043 0301 orr.w r3, r3, #1 8000d58: 6223 str r3, [r4, #32] tickstart = HAL_GetTick(); 8000d5a: f7ff fab1 bl 80002c0 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 8000d5e: f241 3688 movw r6, #5000 ; 0x1388 tickstart = HAL_GetTick(); 8000d62: 4680 mov r8, r0 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8000d64: 6a23 ldr r3, [r4, #32] 8000d66: 079b lsls r3, r3, #30 8000d68: d53f bpl.n 8000dea if(pwrclkchanged == SET) 8000d6a: 2f00 cmp r7, #0 8000d6c: f43f af1d beq.w 8000baa __HAL_RCC_PWR_CLK_DISABLE(); 8000d70: 69e3 ldr r3, [r4, #28] 8000d72: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 8000d76: 61e3 str r3, [r4, #28] 8000d78: e717 b.n 8000baa FlagStatus pwrclkchanged = RESET; 8000d7a: 2700 movs r7, #0 8000d7c: e7e2 b.n 8000d44 SET_BIT(PWR->CR, PWR_CR_DBP); 8000d7e: 6833 ldr r3, [r6, #0] 8000d80: f443 7380 orr.w r3, r3, #256 ; 0x100 8000d84: 6033 str r3, [r6, #0] tickstart = HAL_GetTick(); 8000d86: f7ff fa9b bl 80002c0 8000d8a: 4680 mov r8, r0 while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8000d8c: 6833 ldr r3, [r6, #0] 8000d8e: 05da lsls r2, r3, #23 8000d90: d4dc bmi.n 8000d4c if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8000d92: f7ff fa95 bl 80002c0 8000d96: eba0 0008 sub.w r0, r0, r8 8000d9a: 2864 cmp r0, #100 ; 0x64 8000d9c: d9f6 bls.n 8000d8c 8000d9e: e735 b.n 8000c0c __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8000da0: b9ab cbnz r3, 8000dce 8000da2: 6a23 ldr r3, [r4, #32] if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 8000da4: f241 3888 movw r8, #5000 ; 0x1388 __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8000da8: f023 0301 bic.w r3, r3, #1 8000dac: 6223 str r3, [r4, #32] 8000dae: 6a23 ldr r3, [r4, #32] 8000db0: f023 0304 bic.w r3, r3, #4 8000db4: 6223 str r3, [r4, #32] tickstart = HAL_GetTick(); 8000db6: f7ff fa83 bl 80002c0 8000dba: 4606 mov r6, r0 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8000dbc: 6a23 ldr r3, [r4, #32] 8000dbe: 0798 lsls r0, r3, #30 8000dc0: d5d3 bpl.n 8000d6a if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 8000dc2: f7ff fa7d bl 80002c0 8000dc6: 1b80 subs r0, r0, r6 8000dc8: 4540 cmp r0, r8 8000dca: d9f7 bls.n 8000dbc 8000dcc: e71e b.n 8000c0c __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8000dce: 2b05 cmp r3, #5 8000dd0: 6a23 ldr r3, [r4, #32] 8000dd2: d103 bne.n 8000ddc 8000dd4: f043 0304 orr.w r3, r3, #4 8000dd8: 6223 str r3, [r4, #32] 8000dda: e7ba b.n 8000d52 8000ddc: f023 0301 bic.w r3, r3, #1 8000de0: 6223 str r3, [r4, #32] 8000de2: 6a23 ldr r3, [r4, #32] 8000de4: f023 0304 bic.w r3, r3, #4 8000de8: e7b6 b.n 8000d58 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 8000dea: f7ff fa69 bl 80002c0 8000dee: eba0 0008 sub.w r0, r0, r8 8000df2: 42b0 cmp r0, r6 8000df4: d9b6 bls.n 8000d64 8000df6: e709 b.n 8000c0c 8000df8: 40021000 .word 0x40021000 8000dfc: 42420000 .word 0x42420000 8000e00: 42420480 .word 0x42420480 8000e04: 2000000c .word 0x2000000c 8000e08: 40007000 .word 0x40007000 if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 8000e0c: 4c22 ldr r4, [pc, #136] ; (8000e98 ) 8000e0e: 6863 ldr r3, [r4, #4] 8000e10: f003 030c and.w r3, r3, #12 8000e14: 2b08 cmp r3, #8 8000e16: f43f aee2 beq.w 8000bde 8000e1a: 2300 movs r3, #0 8000e1c: 4e1f ldr r6, [pc, #124] ; (8000e9c ) if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 8000e1e: 2a02 cmp r2, #2 __HAL_RCC_PLL_DISABLE(); 8000e20: 6033 str r3, [r6, #0] if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 8000e22: d12b bne.n 8000e7c tickstart = HAL_GetTick(); 8000e24: f7ff fa4c bl 80002c0 8000e28: 4607 mov r7, r0 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8000e2a: 6823 ldr r3, [r4, #0] 8000e2c: 0199 lsls r1, r3, #6 8000e2e: d41f bmi.n 8000e70 if(RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE) 8000e30: 6a2b ldr r3, [r5, #32] 8000e32: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8000e36: d105 bne.n 8000e44 __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); 8000e38: 6862 ldr r2, [r4, #4] 8000e3a: 68a9 ldr r1, [r5, #8] 8000e3c: f422 3200 bic.w r2, r2, #131072 ; 0x20000 8000e40: 430a orrs r2, r1 8000e42: 6062 str r2, [r4, #4] __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 8000e44: 6a69 ldr r1, [r5, #36] ; 0x24 8000e46: 6862 ldr r2, [r4, #4] 8000e48: 430b orrs r3, r1 8000e4a: f422 1274 bic.w r2, r2, #3997696 ; 0x3d0000 8000e4e: 4313 orrs r3, r2 8000e50: 6063 str r3, [r4, #4] __HAL_RCC_PLL_ENABLE(); 8000e52: 2301 movs r3, #1 8000e54: 6033 str r3, [r6, #0] tickstart = HAL_GetTick(); 8000e56: f7ff fa33 bl 80002c0 8000e5a: 4605 mov r5, r0 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8000e5c: 6823 ldr r3, [r4, #0] 8000e5e: 019a lsls r2, r3, #6 8000e60: f53f aea7 bmi.w 8000bb2 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8000e64: f7ff fa2c bl 80002c0 8000e68: 1b40 subs r0, r0, r5 8000e6a: 2802 cmp r0, #2 8000e6c: d9f6 bls.n 8000e5c 8000e6e: e6cd b.n 8000c0c if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8000e70: f7ff fa26 bl 80002c0 8000e74: 1bc0 subs r0, r0, r7 8000e76: 2802 cmp r0, #2 8000e78: d9d7 bls.n 8000e2a 8000e7a: e6c7 b.n 8000c0c tickstart = HAL_GetTick(); 8000e7c: f7ff fa20 bl 80002c0 8000e80: 4605 mov r5, r0 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8000e82: 6823 ldr r3, [r4, #0] 8000e84: 019b lsls r3, r3, #6 8000e86: f57f ae94 bpl.w 8000bb2 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8000e8a: f7ff fa19 bl 80002c0 8000e8e: 1b40 subs r0, r0, r5 8000e90: 2802 cmp r0, #2 8000e92: d9f6 bls.n 8000e82 8000e94: e6ba b.n 8000c0c 8000e96: bf00 nop 8000e98: 40021000 .word 0x40021000 8000e9c: 42420060 .word 0x42420060 08000ea0 : { 8000ea0: b530 push {r4, r5, lr} const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; 8000ea2: 4b19 ldr r3, [pc, #100] ; (8000f08 ) { 8000ea4: b087 sub sp, #28 const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; 8000ea6: ac02 add r4, sp, #8 8000ea8: f103 0510 add.w r5, r3, #16 8000eac: 4622 mov r2, r4 8000eae: 6818 ldr r0, [r3, #0] 8000eb0: 6859 ldr r1, [r3, #4] 8000eb2: 3308 adds r3, #8 8000eb4: c203 stmia r2!, {r0, r1} 8000eb6: 42ab cmp r3, r5 8000eb8: 4614 mov r4, r2 8000eba: d1f7 bne.n 8000eac const uint8_t aPredivFactorTable[2] = {1, 2}; 8000ebc: 2301 movs r3, #1 8000ebe: f88d 3004 strb.w r3, [sp, #4] 8000ec2: 2302 movs r3, #2 tmpreg = RCC->CFGR; 8000ec4: 4911 ldr r1, [pc, #68] ; (8000f0c ) const uint8_t aPredivFactorTable[2] = {1, 2}; 8000ec6: f88d 3005 strb.w r3, [sp, #5] tmpreg = RCC->CFGR; 8000eca: 684b ldr r3, [r1, #4] switch (tmpreg & RCC_CFGR_SWS) 8000ecc: f003 020c and.w r2, r3, #12 8000ed0: 2a08 cmp r2, #8 8000ed2: d117 bne.n 8000f04 pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; 8000ed4: f3c3 4283 ubfx r2, r3, #18, #4 8000ed8: a806 add r0, sp, #24 8000eda: 4402 add r2, r0 if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) 8000edc: 03db lsls r3, r3, #15 pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; 8000ede: f812 2c10 ldrb.w r2, [r2, #-16] if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) 8000ee2: d50c bpl.n 8000efe prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; 8000ee4: 684b ldr r3, [r1, #4] pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv); 8000ee6: 480a ldr r0, [pc, #40] ; (8000f10 ) prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; 8000ee8: f3c3 4340 ubfx r3, r3, #17, #1 pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv); 8000eec: 4350 muls r0, r2 prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; 8000eee: aa06 add r2, sp, #24 8000ef0: 4413 add r3, r2 8000ef2: f813 3c14 ldrb.w r3, [r3, #-20] pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv); 8000ef6: fbb0 f0f3 udiv r0, r0, r3 } 8000efa: b007 add sp, #28 8000efc: bd30 pop {r4, r5, pc} pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); 8000efe: 4805 ldr r0, [pc, #20] ; (8000f14 ) 8000f00: 4350 muls r0, r2 8000f02: e7fa b.n 8000efa sysclockfreq = HSE_VALUE; 8000f04: 4802 ldr r0, [pc, #8] ; (8000f10 ) return sysclockfreq; 8000f06: e7f8 b.n 8000efa 8000f08: 080031a4 .word 0x080031a4 8000f0c: 40021000 .word 0x40021000 8000f10: 007a1200 .word 0x007a1200 8000f14: 003d0900 .word 0x003d0900 08000f18 : if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY)) 8000f18: 4a54 ldr r2, [pc, #336] ; (800106c ) { 8000f1a: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY)) 8000f1e: 6813 ldr r3, [r2, #0] { 8000f20: 4605 mov r5, r0 if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY)) 8000f22: f003 0307 and.w r3, r3, #7 8000f26: 428b cmp r3, r1 { 8000f28: 460e mov r6, r1 if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY)) 8000f2a: d32a bcc.n 8000f82 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8000f2c: 6829 ldr r1, [r5, #0] 8000f2e: 078c lsls r4, r1, #30 8000f30: d434 bmi.n 8000f9c if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 8000f32: 07ca lsls r2, r1, #31 8000f34: d447 bmi.n 8000fc6 if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY)) 8000f36: 4a4d ldr r2, [pc, #308] ; (800106c ) 8000f38: 6813 ldr r3, [r2, #0] 8000f3a: f003 0307 and.w r3, r3, #7 8000f3e: 429e cmp r6, r3 8000f40: f0c0 8082 bcc.w 8001048 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8000f44: 682a ldr r2, [r5, #0] 8000f46: 4c4a ldr r4, [pc, #296] ; (8001070 ) 8000f48: f012 0f04 tst.w r2, #4 8000f4c: f040 8087 bne.w 800105e if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8000f50: 0713 lsls r3, r2, #28 8000f52: d506 bpl.n 8000f62 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); 8000f54: 6863 ldr r3, [r4, #4] 8000f56: 692a ldr r2, [r5, #16] 8000f58: f423 5360 bic.w r3, r3, #14336 ; 0x3800 8000f5c: ea43 03c2 orr.w r3, r3, r2, lsl #3 8000f60: 6063 str r3, [r4, #4] SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos]; 8000f62: f7ff ff9d bl 8000ea0 8000f66: 6863 ldr r3, [r4, #4] 8000f68: 4a42 ldr r2, [pc, #264] ; (8001074 ) 8000f6a: f3c3 1303 ubfx r3, r3, #4, #4 8000f6e: 5cd3 ldrb r3, [r2, r3] 8000f70: 40d8 lsrs r0, r3 8000f72: 4b41 ldr r3, [pc, #260] ; (8001078 ) 8000f74: 6018 str r0, [r3, #0] HAL_InitTick (TICK_INT_PRIORITY); 8000f76: 2000 movs r0, #0 8000f78: f7ff f960 bl 800023c return HAL_OK; 8000f7c: 2000 movs r0, #0 } 8000f7e: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} __HAL_FLASH_SET_LATENCY(FLatency); 8000f82: 6813 ldr r3, [r2, #0] 8000f84: f023 0307 bic.w r3, r3, #7 8000f88: 430b orrs r3, r1 8000f8a: 6013 str r3, [r2, #0] if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) 8000f8c: 6813 ldr r3, [r2, #0] 8000f8e: f003 0307 and.w r3, r3, #7 8000f92: 4299 cmp r1, r3 8000f94: d0ca beq.n 8000f2c return HAL_ERROR; 8000f96: 2001 movs r0, #1 8000f98: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8000f9c: 4b34 ldr r3, [pc, #208] ; (8001070 ) if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8000f9e: f011 0f04 tst.w r1, #4 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 8000fa2: bf1e ittt ne 8000fa4: 685a ldrne r2, [r3, #4] 8000fa6: f442 62e0 orrne.w r2, r2, #1792 ; 0x700 8000faa: 605a strne r2, [r3, #4] if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8000fac: 0708 lsls r0, r1, #28 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); 8000fae: bf42 ittt mi 8000fb0: 685a ldrmi r2, [r3, #4] 8000fb2: f442 5260 orrmi.w r2, r2, #14336 ; 0x3800 8000fb6: 605a strmi r2, [r3, #4] MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8000fb8: 685a ldr r2, [r3, #4] 8000fba: 68a8 ldr r0, [r5, #8] 8000fbc: f022 02f0 bic.w r2, r2, #240 ; 0xf0 8000fc0: 4302 orrs r2, r0 8000fc2: 605a str r2, [r3, #4] 8000fc4: e7b5 b.n 8000f32 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8000fc6: 686a ldr r2, [r5, #4] 8000fc8: 4c29 ldr r4, [pc, #164] ; (8001070 ) 8000fca: 2a01 cmp r2, #1 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8000fcc: 6823 ldr r3, [r4, #0] if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8000fce: d11c bne.n 800100a if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8000fd0: f413 3f00 tst.w r3, #131072 ; 0x20000 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8000fd4: d0df beq.n 8000f96 __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 8000fd6: 6863 ldr r3, [r4, #4] if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) 8000fd8: f241 3888 movw r8, #5000 ; 0x1388 __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 8000fdc: f023 0303 bic.w r3, r3, #3 8000fe0: 4313 orrs r3, r2 8000fe2: 6063 str r3, [r4, #4] tickstart = HAL_GetTick(); 8000fe4: f7ff f96c bl 80002c0 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8000fe8: 686b ldr r3, [r5, #4] tickstart = HAL_GetTick(); 8000fea: 4607 mov r7, r0 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8000fec: 2b01 cmp r3, #1 8000fee: d114 bne.n 800101a while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) 8000ff0: 6863 ldr r3, [r4, #4] 8000ff2: f003 030c and.w r3, r3, #12 8000ff6: 2b04 cmp r3, #4 8000ff8: d09d beq.n 8000f36 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) 8000ffa: f7ff f961 bl 80002c0 8000ffe: 1bc0 subs r0, r0, r7 8001000: 4540 cmp r0, r8 8001002: d9f5 bls.n 8000ff0 return HAL_TIMEOUT; 8001004: 2003 movs r0, #3 8001006: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 800100a: 2a02 cmp r2, #2 800100c: d102 bne.n 8001014 if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 800100e: f013 7f00 tst.w r3, #33554432 ; 0x2000000 8001012: e7df b.n 8000fd4 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8001014: f013 0f02 tst.w r3, #2 8001018: e7dc b.n 8000fd4 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 800101a: 2b02 cmp r3, #2 800101c: d10f bne.n 800103e while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 800101e: 6863 ldr r3, [r4, #4] 8001020: f003 030c and.w r3, r3, #12 8001024: 2b08 cmp r3, #8 8001026: d086 beq.n 8000f36 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) 8001028: f7ff f94a bl 80002c0 800102c: 1bc0 subs r0, r0, r7 800102e: 4540 cmp r0, r8 8001030: d9f5 bls.n 800101e 8001032: e7e7 b.n 8001004 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) 8001034: f7ff f944 bl 80002c0 8001038: 1bc0 subs r0, r0, r7 800103a: 4540 cmp r0, r8 800103c: d8e2 bhi.n 8001004 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) 800103e: 6863 ldr r3, [r4, #4] 8001040: f013 0f0c tst.w r3, #12 8001044: d1f6 bne.n 8001034 8001046: e776 b.n 8000f36 __HAL_FLASH_SET_LATENCY(FLatency); 8001048: 6813 ldr r3, [r2, #0] 800104a: f023 0307 bic.w r3, r3, #7 800104e: 4333 orrs r3, r6 8001050: 6013 str r3, [r2, #0] if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) 8001052: 6813 ldr r3, [r2, #0] 8001054: f003 0307 and.w r3, r3, #7 8001058: 429e cmp r6, r3 800105a: d19c bne.n 8000f96 800105c: e772 b.n 8000f44 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 800105e: 6863 ldr r3, [r4, #4] 8001060: 68e9 ldr r1, [r5, #12] 8001062: f423 63e0 bic.w r3, r3, #1792 ; 0x700 8001066: 430b orrs r3, r1 8001068: 6063 str r3, [r4, #4] 800106a: e771 b.n 8000f50 800106c: 40022000 .word 0x40022000 8001070: 40021000 .word 0x40021000 8001074: 08003219 .word 0x08003219 8001078: 2000000c .word 0x2000000c 0800107c : return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); 800107c: 4b04 ldr r3, [pc, #16] ; (8001090 ) 800107e: 4a05 ldr r2, [pc, #20] ; (8001094 ) 8001080: 685b ldr r3, [r3, #4] 8001082: f3c3 2302 ubfx r3, r3, #8, #3 8001086: 5cd3 ldrb r3, [r2, r3] 8001088: 4a03 ldr r2, [pc, #12] ; (8001098 ) 800108a: 6810 ldr r0, [r2, #0] } 800108c: 40d8 lsrs r0, r3 800108e: 4770 bx lr 8001090: 40021000 .word 0x40021000 8001094: 08003229 .word 0x08003229 8001098: 2000000c .word 0x2000000c 0800109c : return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); 800109c: 4b04 ldr r3, [pc, #16] ; (80010b0 ) 800109e: 4a05 ldr r2, [pc, #20] ; (80010b4 ) 80010a0: 685b ldr r3, [r3, #4] 80010a2: f3c3 23c2 ubfx r3, r3, #11, #3 80010a6: 5cd3 ldrb r3, [r2, r3] 80010a8: 4a03 ldr r2, [pc, #12] ; (80010b8 ) 80010aa: 6810 ldr r0, [r2, #0] } 80010ac: 40d8 lsrs r0, r3 80010ae: 4770 bx lr 80010b0: 40021000 .word 0x40021000 80010b4: 08003229 .word 0x08003229 80010b8: 2000000c .word 0x2000000c 080010bc : { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Enable the TIM Update interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); 80010bc: 6803 ldr r3, [r0, #0] /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); /* Return function status */ return HAL_OK; } 80010be: 2000 movs r0, #0 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); 80010c0: 68da ldr r2, [r3, #12] 80010c2: f042 0201 orr.w r2, r2, #1 80010c6: 60da str r2, [r3, #12] __HAL_TIM_ENABLE(htim); 80010c8: 681a ldr r2, [r3, #0] 80010ca: f042 0201 orr.w r2, r2, #1 80010ce: 601a str r2, [r3, #0] } 80010d0: 4770 bx lr 080010d2 : 80010d2: 4770 bx lr 080010d4 : 80010d4: 4770 bx lr 080010d6 : 80010d6: 4770 bx lr 080010d8 : 80010d8: 4770 bx lr 080010da : * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { /* Capture compare 1 event */ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) 80010da: 6803 ldr r3, [r0, #0] { 80010dc: b510 push {r4, lr} if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) 80010de: 691a ldr r2, [r3, #16] { 80010e0: 4604 mov r4, r0 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) 80010e2: 0791 lsls r1, r2, #30 80010e4: d50e bpl.n 8001104 { if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET) 80010e6: 68da ldr r2, [r3, #12] 80010e8: 0792 lsls r2, r2, #30 80010ea: d50b bpl.n 8001104 { { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); 80010ec: f06f 0202 mvn.w r2, #2 80010f0: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 80010f2: 2201 movs r2, #1 /* Input capture event */ if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 80010f4: 699b ldr r3, [r3, #24] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 80010f6: 7702 strb r2, [r0, #28] if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 80010f8: 079b lsls r3, r3, #30 80010fa: d077 beq.n 80011ec { HAL_TIM_IC_CaptureCallback(htim); 80010fc: f7ff ffea bl 80010d4 else { HAL_TIM_OC_DelayElapsedCallback(htim); HAL_TIM_PWM_PulseFinishedCallback(htim); } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8001100: 2300 movs r3, #0 8001102: 7723 strb r3, [r4, #28] } } } /* Capture compare 2 event */ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) 8001104: 6823 ldr r3, [r4, #0] 8001106: 691a ldr r2, [r3, #16] 8001108: 0750 lsls r0, r2, #29 800110a: d510 bpl.n 800112e { if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET) 800110c: 68da ldr r2, [r3, #12] 800110e: 0751 lsls r1, r2, #29 8001110: d50d bpl.n 800112e { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); 8001112: f06f 0204 mvn.w r2, #4 8001116: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 8001118: 2202 movs r2, #2 /* Input capture event */ if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 800111a: 699b ldr r3, [r3, #24] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 800111c: 7722 strb r2, [r4, #28] if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 800111e: f413 7f40 tst.w r3, #768 ; 0x300 { HAL_TIM_IC_CaptureCallback(htim); 8001122: 4620 mov r0, r4 if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 8001124: d068 beq.n 80011f8 HAL_TIM_IC_CaptureCallback(htim); 8001126: f7ff ffd5 bl 80010d4 else { HAL_TIM_OC_DelayElapsedCallback(htim); HAL_TIM_PWM_PulseFinishedCallback(htim); } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800112a: 2300 movs r3, #0 800112c: 7723 strb r3, [r4, #28] } } /* Capture compare 3 event */ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) 800112e: 6823 ldr r3, [r4, #0] 8001130: 691a ldr r2, [r3, #16] 8001132: 0712 lsls r2, r2, #28 8001134: d50f bpl.n 8001156 { if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET) 8001136: 68da ldr r2, [r3, #12] 8001138: 0710 lsls r0, r2, #28 800113a: d50c bpl.n 8001156 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); 800113c: f06f 0208 mvn.w r2, #8 8001140: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 8001142: 2204 movs r2, #4 /* Input capture event */ if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 8001144: 69db ldr r3, [r3, #28] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 8001146: 7722 strb r2, [r4, #28] if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 8001148: 0799 lsls r1, r3, #30 { HAL_TIM_IC_CaptureCallback(htim); 800114a: 4620 mov r0, r4 if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 800114c: d05a beq.n 8001204 HAL_TIM_IC_CaptureCallback(htim); 800114e: f7ff ffc1 bl 80010d4 else { HAL_TIM_OC_DelayElapsedCallback(htim); HAL_TIM_PWM_PulseFinishedCallback(htim); } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8001152: 2300 movs r3, #0 8001154: 7723 strb r3, [r4, #28] } } /* Capture compare 4 event */ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) 8001156: 6823 ldr r3, [r4, #0] 8001158: 691a ldr r2, [r3, #16] 800115a: 06d2 lsls r2, r2, #27 800115c: d510 bpl.n 8001180 { if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET) 800115e: 68da ldr r2, [r3, #12] 8001160: 06d0 lsls r0, r2, #27 8001162: d50d bpl.n 8001180 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); 8001164: f06f 0210 mvn.w r2, #16 8001168: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 800116a: 2208 movs r2, #8 /* Input capture event */ if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 800116c: 69db ldr r3, [r3, #28] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 800116e: 7722 strb r2, [r4, #28] if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 8001170: f413 7f40 tst.w r3, #768 ; 0x300 { HAL_TIM_IC_CaptureCallback(htim); 8001174: 4620 mov r0, r4 if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 8001176: d04b beq.n 8001210 HAL_TIM_IC_CaptureCallback(htim); 8001178: f7ff ffac bl 80010d4 else { HAL_TIM_OC_DelayElapsedCallback(htim); HAL_TIM_PWM_PulseFinishedCallback(htim); } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800117c: 2300 movs r3, #0 800117e: 7723 strb r3, [r4, #28] } } /* TIM Update event */ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) 8001180: 6823 ldr r3, [r4, #0] 8001182: 691a ldr r2, [r3, #16] 8001184: 07d1 lsls r1, r2, #31 8001186: d508 bpl.n 800119a { if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET) 8001188: 68da ldr r2, [r3, #12] 800118a: 07d2 lsls r2, r2, #31 800118c: d505 bpl.n 800119a { __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); 800118e: f06f 0201 mvn.w r2, #1 HAL_TIM_PeriodElapsedCallback(htim); 8001192: 4620 mov r0, r4 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); 8001194: 611a str r2, [r3, #16] HAL_TIM_PeriodElapsedCallback(htim); 8001196: f000 fce9 bl 8001b6c } } /* TIM Break input event */ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) 800119a: 6823 ldr r3, [r4, #0] 800119c: 691a ldr r2, [r3, #16] 800119e: 0610 lsls r0, r2, #24 80011a0: d508 bpl.n 80011b4 { if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET) 80011a2: 68da ldr r2, [r3, #12] 80011a4: 0611 lsls r1, r2, #24 80011a6: d505 bpl.n 80011b4 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); 80011a8: f06f 0280 mvn.w r2, #128 ; 0x80 HAL_TIMEx_BreakCallback(htim); 80011ac: 4620 mov r0, r4 __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); 80011ae: 611a str r2, [r3, #16] HAL_TIMEx_BreakCallback(htim); 80011b0: f000 f8bf bl 8001332 } } /* TIM Trigger detection event */ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) 80011b4: 6823 ldr r3, [r4, #0] 80011b6: 691a ldr r2, [r3, #16] 80011b8: 0652 lsls r2, r2, #25 80011ba: d508 bpl.n 80011ce { if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET) 80011bc: 68da ldr r2, [r3, #12] 80011be: 0650 lsls r0, r2, #25 80011c0: d505 bpl.n 80011ce { __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); 80011c2: f06f 0240 mvn.w r2, #64 ; 0x40 HAL_TIM_TriggerCallback(htim); 80011c6: 4620 mov r0, r4 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); 80011c8: 611a str r2, [r3, #16] HAL_TIM_TriggerCallback(htim); 80011ca: f7ff ff85 bl 80010d8 } } /* TIM commutation event */ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) 80011ce: 6823 ldr r3, [r4, #0] 80011d0: 691a ldr r2, [r3, #16] 80011d2: 0691 lsls r1, r2, #26 80011d4: d522 bpl.n 800121c { if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET) 80011d6: 68da ldr r2, [r3, #12] 80011d8: 0692 lsls r2, r2, #26 80011da: d51f bpl.n 800121c { __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); 80011dc: f06f 0220 mvn.w r2, #32 HAL_TIMEx_CommutationCallback(htim); 80011e0: 4620 mov r0, r4 } } } 80011e2: e8bd 4010 ldmia.w sp!, {r4, lr} __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); 80011e6: 611a str r2, [r3, #16] HAL_TIMEx_CommutationCallback(htim); 80011e8: f000 b8a2 b.w 8001330 HAL_TIM_OC_DelayElapsedCallback(htim); 80011ec: f7ff ff71 bl 80010d2 HAL_TIM_PWM_PulseFinishedCallback(htim); 80011f0: 4620 mov r0, r4 80011f2: f7ff ff70 bl 80010d6 80011f6: e783 b.n 8001100 HAL_TIM_OC_DelayElapsedCallback(htim); 80011f8: f7ff ff6b bl 80010d2 HAL_TIM_PWM_PulseFinishedCallback(htim); 80011fc: 4620 mov r0, r4 80011fe: f7ff ff6a bl 80010d6 8001202: e792 b.n 800112a HAL_TIM_OC_DelayElapsedCallback(htim); 8001204: f7ff ff65 bl 80010d2 HAL_TIM_PWM_PulseFinishedCallback(htim); 8001208: 4620 mov r0, r4 800120a: f7ff ff64 bl 80010d6 800120e: e7a0 b.n 8001152 HAL_TIM_OC_DelayElapsedCallback(htim); 8001210: f7ff ff5f bl 80010d2 HAL_TIM_PWM_PulseFinishedCallback(htim); 8001214: 4620 mov r0, r4 8001216: f7ff ff5e bl 80010d6 800121a: e7af b.n 800117c 800121c: bd10 pop {r4, pc} ... 08001220 : { uint32_t tmpcr1 = 0U; tmpcr1 = TIMx->CR1; /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 8001220: 4a24 ldr r2, [pc, #144] ; (80012b4 ) tmpcr1 = TIMx->CR1; 8001222: 6803 ldr r3, [r0, #0] if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 8001224: 4290 cmp r0, r2 8001226: d012 beq.n 800124e 8001228: f502 6200 add.w r2, r2, #2048 ; 0x800 800122c: 4290 cmp r0, r2 800122e: d00e beq.n 800124e 8001230: f1b0 4f80 cmp.w r0, #1073741824 ; 0x40000000 8001234: d00b beq.n 800124e 8001236: f5a2 3298 sub.w r2, r2, #77824 ; 0x13000 800123a: 4290 cmp r0, r2 800123c: d007 beq.n 800124e 800123e: f502 6280 add.w r2, r2, #1024 ; 0x400 8001242: 4290 cmp r0, r2 8001244: d003 beq.n 800124e 8001246: f502 6280 add.w r2, r2, #1024 ; 0x400 800124a: 4290 cmp r0, r2 800124c: d11d bne.n 800128a { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); tmpcr1 |= Structure->CounterMode; 800124e: 684a ldr r2, [r1, #4] tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 8001250: f023 0370 bic.w r3, r3, #112 ; 0x70 tmpcr1 |= Structure->CounterMode; 8001254: 4313 orrs r3, r2 } if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 8001256: 4a17 ldr r2, [pc, #92] ; (80012b4 ) 8001258: 4290 cmp r0, r2 800125a: d012 beq.n 8001282 800125c: f502 6200 add.w r2, r2, #2048 ; 0x800 8001260: 4290 cmp r0, r2 8001262: d00e beq.n 8001282 8001264: f1b0 4f80 cmp.w r0, #1073741824 ; 0x40000000 8001268: d00b beq.n 8001282 800126a: f5a2 3298 sub.w r2, r2, #77824 ; 0x13000 800126e: 4290 cmp r0, r2 8001270: d007 beq.n 8001282 8001272: f502 6280 add.w r2, r2, #1024 ; 0x400 8001276: 4290 cmp r0, r2 8001278: d003 beq.n 8001282 800127a: f502 6280 add.w r2, r2, #1024 ; 0x400 800127e: 4290 cmp r0, r2 8001280: d103 bne.n 800128a { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; tmpcr1 |= (uint32_t)Structure->ClockDivision; 8001282: 68ca ldr r2, [r1, #12] tmpcr1 &= ~TIM_CR1_CKD; 8001284: f423 7340 bic.w r3, r3, #768 ; 0x300 tmpcr1 |= (uint32_t)Structure->ClockDivision; 8001288: 4313 orrs r3, r2 } /* Set the auto-reload preload */ tmpcr1 &= ~TIM_CR1_ARPE; tmpcr1 |= (uint32_t)Structure->AutoReloadPreload; 800128a: 694a ldr r2, [r1, #20] tmpcr1 &= ~TIM_CR1_ARPE; 800128c: f023 0380 bic.w r3, r3, #128 ; 0x80 tmpcr1 |= (uint32_t)Structure->AutoReloadPreload; 8001290: 4313 orrs r3, r2 TIMx->CR1 = tmpcr1; 8001292: 6003 str r3, [r0, #0] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 8001294: 688b ldr r3, [r1, #8] 8001296: 62c3 str r3, [r0, #44] ; 0x2c /* Set the Prescaler value */ TIMx->PSC = (uint32_t)Structure->Prescaler; 8001298: 680b ldr r3, [r1, #0] 800129a: 6283 str r3, [r0, #40] ; 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 800129c: 4b05 ldr r3, [pc, #20] ; (80012b4 ) 800129e: 4298 cmp r0, r3 80012a0: d003 beq.n 80012aa 80012a2: f503 6300 add.w r3, r3, #2048 ; 0x800 80012a6: 4298 cmp r0, r3 80012a8: d101 bne.n 80012ae { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 80012aa: 690b ldr r3, [r1, #16] 80012ac: 6303 str r3, [r0, #48] ; 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter(only for TIM1 and TIM8) value immediatly */ TIMx->EGR = TIM_EGR_UG; 80012ae: 2301 movs r3, #1 80012b0: 6143 str r3, [r0, #20] 80012b2: 4770 bx lr 80012b4: 40012c00 .word 0x40012c00 080012b8 : { 80012b8: b510 push {r4, lr} if(htim == NULL) 80012ba: 4604 mov r4, r0 80012bc: b1a0 cbz r0, 80012e8 if(htim->State == HAL_TIM_STATE_RESET) 80012be: f890 303d ldrb.w r3, [r0, #61] ; 0x3d 80012c2: f003 02ff and.w r2, r3, #255 ; 0xff 80012c6: b91b cbnz r3, 80012d0 htim->Lock = HAL_UNLOCKED; 80012c8: f880 203c strb.w r2, [r0, #60] ; 0x3c HAL_TIM_Base_MspInit(htim); 80012cc: f000 fd8e bl 8001dec htim->State= HAL_TIM_STATE_BUSY; 80012d0: 2302 movs r3, #2 TIM_Base_SetConfig(htim->Instance, &htim->Init); 80012d2: 6820 ldr r0, [r4, #0] htim->State= HAL_TIM_STATE_BUSY; 80012d4: f884 303d strb.w r3, [r4, #61] ; 0x3d TIM_Base_SetConfig(htim->Instance, &htim->Init); 80012d8: 1d21 adds r1, r4, #4 80012da: f7ff ffa1 bl 8001220 htim->State= HAL_TIM_STATE_READY; 80012de: 2301 movs r3, #1 return HAL_OK; 80012e0: 2000 movs r0, #0 htim->State= HAL_TIM_STATE_READY; 80012e2: f884 303d strb.w r3, [r4, #61] ; 0x3d return HAL_OK; 80012e6: bd10 pop {r4, pc} return HAL_ERROR; 80012e8: 2001 movs r0, #1 } 80012ea: bd10 pop {r4, pc} 080012ec : /* Check the parameters */ assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); __HAL_LOCK(htim); 80012ec: f890 303c ldrb.w r3, [r0, #60] ; 0x3c { 80012f0: b510 push {r4, lr} __HAL_LOCK(htim); 80012f2: 2b01 cmp r3, #1 80012f4: f04f 0302 mov.w r3, #2 80012f8: d018 beq.n 800132c htim->State = HAL_TIM_STATE_BUSY; 80012fa: f880 303d strb.w r3, [r0, #61] ; 0x3d /* Reset the MMS Bits */ htim->Instance->CR2 &= ~TIM_CR2_MMS; 80012fe: 6803 ldr r3, [r0, #0] /* Select the TRGO source */ htim->Instance->CR2 |= sMasterConfig->MasterOutputTrigger; 8001300: 680c ldr r4, [r1, #0] htim->Instance->CR2 &= ~TIM_CR2_MMS; 8001302: 685a ldr r2, [r3, #4] /* Reset the MSM Bit */ htim->Instance->SMCR &= ~TIM_SMCR_MSM; /* Set or Reset the MSM Bit */ htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode; 8001304: 6849 ldr r1, [r1, #4] htim->Instance->CR2 &= ~TIM_CR2_MMS; 8001306: f022 0270 bic.w r2, r2, #112 ; 0x70 800130a: 605a str r2, [r3, #4] htim->Instance->CR2 |= sMasterConfig->MasterOutputTrigger; 800130c: 685a ldr r2, [r3, #4] 800130e: 4322 orrs r2, r4 8001310: 605a str r2, [r3, #4] htim->Instance->SMCR &= ~TIM_SMCR_MSM; 8001312: 689a ldr r2, [r3, #8] 8001314: f022 0280 bic.w r2, r2, #128 ; 0x80 8001318: 609a str r2, [r3, #8] htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode; 800131a: 689a ldr r2, [r3, #8] 800131c: 430a orrs r2, r1 800131e: 609a str r2, [r3, #8] htim->State = HAL_TIM_STATE_READY; 8001320: 2301 movs r3, #1 8001322: f880 303d strb.w r3, [r0, #61] ; 0x3d __HAL_UNLOCK(htim); 8001326: 2300 movs r3, #0 8001328: f880 303c strb.w r3, [r0, #60] ; 0x3c __HAL_LOCK(htim); 800132c: 4618 mov r0, r3 return HAL_OK; } 800132e: bd10 pop {r4, pc} 08001330 : 8001330: 4770 bx lr 08001332 : * @brief Hall Break detection callback in non blocking mode * @param htim : TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { 8001332: 4770 bx lr 08001334 : * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 8001334: 6803 ldr r3, [r0, #0] 8001336: 68da ldr r2, [r3, #12] 8001338: f422 7290 bic.w r2, r2, #288 ; 0x120 800133c: 60da str r2, [r3, #12] CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 800133e: 695a ldr r2, [r3, #20] 8001340: f022 0201 bic.w r2, r2, #1 8001344: 615a str r2, [r3, #20] /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8001346: 2320 movs r3, #32 8001348: f880 303a strb.w r3, [r0, #58] ; 0x3a 800134c: 4770 bx lr ... 08001350 : * @param huart: pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_SetConfig(UART_HandleTypeDef *huart) { 8001350: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} assert_param(IS_UART_MODE(huart->Init.Mode)); /*------- UART-associated USART registers setting : CR2 Configuration ------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according * to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 8001354: 6805 ldr r5, [r0, #0] 8001356: 68c2 ldr r2, [r0, #12] 8001358: 692b ldr r3, [r5, #16] tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; MODIFY_REG(huart->Instance->CR1, (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), tmpreg); #else tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode; 800135a: 6901 ldr r1, [r0, #16] MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 800135c: f423 5340 bic.w r3, r3, #12288 ; 0x3000 8001360: 4313 orrs r3, r2 8001362: 612b str r3, [r5, #16] tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode; 8001364: 6883 ldr r3, [r0, #8] MODIFY_REG(huart->Instance->CR1, 8001366: 68ea ldr r2, [r5, #12] tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode; 8001368: 430b orrs r3, r1 800136a: 6941 ldr r1, [r0, #20] MODIFY_REG(huart->Instance->CR1, 800136c: f422 52b0 bic.w r2, r2, #5632 ; 0x1600 8001370: f022 020c bic.w r2, r2, #12 tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode; 8001374: 430b orrs r3, r1 MODIFY_REG(huart->Instance->CR1, 8001376: 4313 orrs r3, r2 8001378: 60eb str r3, [r5, #12] tmpreg); #endif /* USART_CR1_OVER8 */ /*------- UART-associated USART registers setting : CR3 Configuration ------*/ /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); 800137a: 696b ldr r3, [r5, #20] 800137c: 6982 ldr r2, [r0, #24] 800137e: f423 7340 bic.w r3, r3, #768 ; 0x300 8001382: 4313 orrs r3, r2 8001384: 616b str r3, [r5, #20] huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate); } } #else /*-------------------------- USART BRR Configuration ---------------------*/ if(huart->Instance == USART1) 8001386: 4b40 ldr r3, [pc, #256] ; (8001488 ) { 8001388: 4681 mov r9, r0 if(huart->Instance == USART1) 800138a: 429d cmp r5, r3 800138c: f04f 0419 mov.w r4, #25 8001390: d146 bne.n 8001420 { huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate); 8001392: f7ff fe83 bl 800109c 8001396: fb04 f300 mul.w r3, r4, r0 800139a: f8d9 6004 ldr.w r6, [r9, #4] 800139e: f04f 0864 mov.w r8, #100 ; 0x64 80013a2: 00b6 lsls r6, r6, #2 80013a4: fbb3 f3f6 udiv r3, r3, r6 80013a8: fbb3 f3f8 udiv r3, r3, r8 80013ac: 011e lsls r6, r3, #4 80013ae: f7ff fe75 bl 800109c 80013b2: 4360 muls r0, r4 80013b4: f8d9 3004 ldr.w r3, [r9, #4] 80013b8: 009b lsls r3, r3, #2 80013ba: fbb0 f7f3 udiv r7, r0, r3 80013be: f7ff fe6d bl 800109c 80013c2: 4360 muls r0, r4 80013c4: f8d9 3004 ldr.w r3, [r9, #4] 80013c8: 009b lsls r3, r3, #2 80013ca: fbb0 f3f3 udiv r3, r0, r3 80013ce: fbb3 f3f8 udiv r3, r3, r8 80013d2: fb08 7313 mls r3, r8, r3, r7 80013d6: 011b lsls r3, r3, #4 80013d8: 3332 adds r3, #50 ; 0x32 80013da: fbb3 f3f8 udiv r3, r3, r8 80013de: f003 07f0 and.w r7, r3, #240 ; 0xf0 80013e2: f7ff fe5b bl 800109c 80013e6: 4360 muls r0, r4 80013e8: f8d9 2004 ldr.w r2, [r9, #4] 80013ec: 0092 lsls r2, r2, #2 80013ee: fbb0 faf2 udiv sl, r0, r2 80013f2: f7ff fe53 bl 800109c } else { huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate); 80013f6: 4360 muls r0, r4 80013f8: f8d9 3004 ldr.w r3, [r9, #4] 80013fc: 009b lsls r3, r3, #2 80013fe: fbb0 f3f3 udiv r3, r0, r3 8001402: fbb3 f3f8 udiv r3, r3, r8 8001406: fb08 a313 mls r3, r8, r3, sl 800140a: 011b lsls r3, r3, #4 800140c: 3332 adds r3, #50 ; 0x32 800140e: fbb3 f3f8 udiv r3, r3, r8 8001412: f003 030f and.w r3, r3, #15 8001416: 433b orrs r3, r7 8001418: 4433 add r3, r6 800141a: 60ab str r3, [r5, #8] 800141c: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8001420: f7ff fe2c bl 800107c 8001424: fb04 f300 mul.w r3, r4, r0 8001428: f8d9 6004 ldr.w r6, [r9, #4] 800142c: f04f 0864 mov.w r8, #100 ; 0x64 8001430: 00b6 lsls r6, r6, #2 8001432: fbb3 f3f6 udiv r3, r3, r6 8001436: fbb3 f3f8 udiv r3, r3, r8 800143a: 011e lsls r6, r3, #4 800143c: f7ff fe1e bl 800107c 8001440: 4360 muls r0, r4 8001442: f8d9 3004 ldr.w r3, [r9, #4] 8001446: 009b lsls r3, r3, #2 8001448: fbb0 f7f3 udiv r7, r0, r3 800144c: f7ff fe16 bl 800107c 8001450: 4360 muls r0, r4 8001452: f8d9 3004 ldr.w r3, [r9, #4] 8001456: 009b lsls r3, r3, #2 8001458: fbb0 f3f3 udiv r3, r0, r3 800145c: fbb3 f3f8 udiv r3, r3, r8 8001460: fb08 7313 mls r3, r8, r3, r7 8001464: 011b lsls r3, r3, #4 8001466: 3332 adds r3, #50 ; 0x32 8001468: fbb3 f3f8 udiv r3, r3, r8 800146c: f003 07f0 and.w r7, r3, #240 ; 0xf0 8001470: f7ff fe04 bl 800107c 8001474: 4360 muls r0, r4 8001476: f8d9 2004 ldr.w r2, [r9, #4] 800147a: 0092 lsls r2, r2, #2 800147c: fbb0 faf2 udiv sl, r0, r2 8001480: f7ff fdfc bl 800107c 8001484: e7b7 b.n 80013f6 8001486: bf00 nop 8001488: 40013800 .word 0x40013800 0800148c : static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) 800148c: b5f8 push {r3, r4, r5, r6, r7, lr} 800148e: 4604 mov r4, r0 8001490: 460e mov r6, r1 8001492: 4617 mov r7, r2 8001494: 461d mov r5, r3 while((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8001496: 6821 ldr r1, [r4, #0] 8001498: 680b ldr r3, [r1, #0] 800149a: ea36 0303 bics.w r3, r6, r3 800149e: d101 bne.n 80014a4 return HAL_OK; 80014a0: 2000 movs r0, #0 } 80014a2: bdf8 pop {r3, r4, r5, r6, r7, pc} if(Timeout != HAL_MAX_DELAY) 80014a4: 1c6b adds r3, r5, #1 80014a6: d0f7 beq.n 8001498 if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout)) 80014a8: b995 cbnz r5, 80014d0 CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); 80014aa: 6823 ldr r3, [r4, #0] __HAL_UNLOCK(huart); 80014ac: 2003 movs r0, #3 CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); 80014ae: 68da ldr r2, [r3, #12] 80014b0: f422 72d0 bic.w r2, r2, #416 ; 0x1a0 80014b4: 60da str r2, [r3, #12] CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 80014b6: 695a ldr r2, [r3, #20] 80014b8: f022 0201 bic.w r2, r2, #1 80014bc: 615a str r2, [r3, #20] huart->gState = HAL_UART_STATE_READY; 80014be: 2320 movs r3, #32 80014c0: f884 3039 strb.w r3, [r4, #57] ; 0x39 huart->RxState = HAL_UART_STATE_READY; 80014c4: f884 303a strb.w r3, [r4, #58] ; 0x3a __HAL_UNLOCK(huart); 80014c8: 2300 movs r3, #0 80014ca: f884 3038 strb.w r3, [r4, #56] ; 0x38 80014ce: bdf8 pop {r3, r4, r5, r6, r7, pc} if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout)) 80014d0: f7fe fef6 bl 80002c0 80014d4: 1bc0 subs r0, r0, r7 80014d6: 4285 cmp r5, r0 80014d8: d2dd bcs.n 8001496 80014da: e7e6 b.n 80014aa 080014dc : { 80014dc: b510 push {r4, lr} if(huart == NULL) 80014de: 4604 mov r4, r0 80014e0: b340 cbz r0, 8001534 if(huart->gState == HAL_UART_STATE_RESET) 80014e2: f890 3039 ldrb.w r3, [r0, #57] ; 0x39 80014e6: f003 02ff and.w r2, r3, #255 ; 0xff 80014ea: b91b cbnz r3, 80014f4 huart->Lock = HAL_UNLOCKED; 80014ec: f880 2038 strb.w r2, [r0, #56] ; 0x38 HAL_UART_MspInit(huart); 80014f0: f000 fc90 bl 8001e14 huart->gState = HAL_UART_STATE_BUSY; 80014f4: 2324 movs r3, #36 ; 0x24 __HAL_UART_DISABLE(huart); 80014f6: 6822 ldr r2, [r4, #0] huart->gState = HAL_UART_STATE_BUSY; 80014f8: f884 3039 strb.w r3, [r4, #57] ; 0x39 __HAL_UART_DISABLE(huart); 80014fc: 68d3 ldr r3, [r2, #12] UART_SetConfig(huart); 80014fe: 4620 mov r0, r4 __HAL_UART_DISABLE(huart); 8001500: f423 5300 bic.w r3, r3, #8192 ; 0x2000 8001504: 60d3 str r3, [r2, #12] UART_SetConfig(huart); 8001506: f7ff ff23 bl 8001350 CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 800150a: 6823 ldr r3, [r4, #0] huart->ErrorCode = HAL_UART_ERROR_NONE; 800150c: 2000 movs r0, #0 CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 800150e: 691a ldr r2, [r3, #16] 8001510: f422 4290 bic.w r2, r2, #18432 ; 0x4800 8001514: 611a str r2, [r3, #16] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 8001516: 695a ldr r2, [r3, #20] 8001518: f022 022a bic.w r2, r2, #42 ; 0x2a 800151c: 615a str r2, [r3, #20] __HAL_UART_ENABLE(huart); 800151e: 68da ldr r2, [r3, #12] 8001520: f442 5200 orr.w r2, r2, #8192 ; 0x2000 8001524: 60da str r2, [r3, #12] huart->gState= HAL_UART_STATE_READY; 8001526: 2320 movs r3, #32 huart->ErrorCode = HAL_UART_ERROR_NONE; 8001528: 63e0 str r0, [r4, #60] ; 0x3c huart->gState= HAL_UART_STATE_READY; 800152a: f884 3039 strb.w r3, [r4, #57] ; 0x39 huart->RxState= HAL_UART_STATE_READY; 800152e: f884 303a strb.w r3, [r4, #58] ; 0x3a return HAL_OK; 8001532: bd10 pop {r4, pc} return HAL_ERROR; 8001534: 2001 movs r0, #1 } 8001536: bd10 pop {r4, pc} 08001538 : { 8001538: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 800153c: 461f mov r7, r3 if(huart->gState == HAL_UART_STATE_READY) 800153e: f890 3039 ldrb.w r3, [r0, #57] ; 0x39 { 8001542: 4604 mov r4, r0 if(huart->gState == HAL_UART_STATE_READY) 8001544: 2b20 cmp r3, #32 { 8001546: 460d mov r5, r1 8001548: 4690 mov r8, r2 if(huart->gState == HAL_UART_STATE_READY) 800154a: d14e bne.n 80015ea if((pData == NULL) || (Size == 0U)) 800154c: 2900 cmp r1, #0 800154e: d049 beq.n 80015e4 8001550: 2a00 cmp r2, #0 8001552: d047 beq.n 80015e4 __HAL_LOCK(huart); 8001554: f890 3038 ldrb.w r3, [r0, #56] ; 0x38 8001558: 2b01 cmp r3, #1 800155a: d046 beq.n 80015ea 800155c: 2301 movs r3, #1 800155e: f880 3038 strb.w r3, [r0, #56] ; 0x38 huart->ErrorCode = HAL_UART_ERROR_NONE; 8001562: 2300 movs r3, #0 8001564: 63c3 str r3, [r0, #60] ; 0x3c huart->gState = HAL_UART_STATE_BUSY_TX; 8001566: 2321 movs r3, #33 ; 0x21 8001568: f880 3039 strb.w r3, [r0, #57] ; 0x39 tickstart = HAL_GetTick(); 800156c: f7fe fea8 bl 80002c0 8001570: 4606 mov r6, r0 huart->TxXferSize = Size; 8001572: f8a4 8024 strh.w r8, [r4, #36] ; 0x24 huart->TxXferCount = Size; 8001576: f8a4 8026 strh.w r8, [r4, #38] ; 0x26 while(huart->TxXferCount > 0U) 800157a: 8ce3 ldrh r3, [r4, #38] ; 0x26 800157c: b29b uxth r3, r3 800157e: b96b cbnz r3, 800159c if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) 8001580: 463b mov r3, r7 8001582: 4632 mov r2, r6 8001584: 2140 movs r1, #64 ; 0x40 8001586: 4620 mov r0, r4 8001588: f7ff ff80 bl 800148c 800158c: b9a8 cbnz r0, 80015ba huart->gState = HAL_UART_STATE_READY; 800158e: 2320 movs r3, #32 __HAL_UNLOCK(huart); 8001590: f884 0038 strb.w r0, [r4, #56] ; 0x38 huart->gState = HAL_UART_STATE_READY; 8001594: f884 3039 strb.w r3, [r4, #57] ; 0x39 return HAL_OK; 8001598: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} huart->TxXferCount--; 800159c: 8ce3 ldrh r3, [r4, #38] ; 0x26 if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) 800159e: 4632 mov r2, r6 huart->TxXferCount--; 80015a0: 3b01 subs r3, #1 80015a2: b29b uxth r3, r3 80015a4: 84e3 strh r3, [r4, #38] ; 0x26 if(huart->Init.WordLength == UART_WORDLENGTH_9B) 80015a6: 68a3 ldr r3, [r4, #8] if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) 80015a8: 2180 movs r1, #128 ; 0x80 if(huart->Init.WordLength == UART_WORDLENGTH_9B) 80015aa: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) 80015ae: 4620 mov r0, r4 80015b0: 463b mov r3, r7 if(huart->Init.WordLength == UART_WORDLENGTH_9B) 80015b2: d10e bne.n 80015d2 if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) 80015b4: f7ff ff6a bl 800148c 80015b8: b110 cbz r0, 80015c0 return HAL_TIMEOUT; 80015ba: 2003 movs r0, #3 80015bc: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} huart->Instance->DR = (*tmp & (uint16_t)0x01FF); 80015c0: 882b ldrh r3, [r5, #0] 80015c2: 6822 ldr r2, [r4, #0] 80015c4: f3c3 0308 ubfx r3, r3, #0, #9 80015c8: 6053 str r3, [r2, #4] if(huart->Init.Parity == UART_PARITY_NONE) 80015ca: 6923 ldr r3, [r4, #16] 80015cc: b943 cbnz r3, 80015e0 pData +=2U; 80015ce: 3502 adds r5, #2 80015d0: e7d3 b.n 800157a if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) 80015d2: f7ff ff5b bl 800148c 80015d6: 2800 cmp r0, #0 80015d8: d1ef bne.n 80015ba huart->Instance->DR = (*pData++ & (uint8_t)0xFF); 80015da: 6823 ldr r3, [r4, #0] 80015dc: 782a ldrb r2, [r5, #0] 80015de: 605a str r2, [r3, #4] 80015e0: 3501 adds r5, #1 80015e2: e7ca b.n 800157a return HAL_ERROR; 80015e4: 2001 movs r0, #1 80015e6: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} return HAL_BUSY; 80015ea: 2002 movs r0, #2 } 80015ec: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 080015f0 : { 80015f0: 4613 mov r3, r2 if(huart->RxState == HAL_UART_STATE_READY) 80015f2: f890 203a ldrb.w r2, [r0, #58] ; 0x3a { 80015f6: b573 push {r0, r1, r4, r5, r6, lr} if(huart->RxState == HAL_UART_STATE_READY) 80015f8: 2a20 cmp r2, #32 { 80015fa: 4605 mov r5, r0 if(huart->RxState == HAL_UART_STATE_READY) 80015fc: d138 bne.n 8001670 if((pData == NULL) || (Size == 0U)) 80015fe: 2900 cmp r1, #0 8001600: d034 beq.n 800166c 8001602: 2b00 cmp r3, #0 8001604: d032 beq.n 800166c __HAL_LOCK(huart); 8001606: f890 2038 ldrb.w r2, [r0, #56] ; 0x38 800160a: 2a01 cmp r2, #1 800160c: d030 beq.n 8001670 800160e: 2201 movs r2, #1 huart->ErrorCode = HAL_UART_ERROR_NONE; 8001610: 2400 movs r4, #0 __HAL_LOCK(huart); 8001612: f880 2038 strb.w r2, [r0, #56] ; 0x38 huart->RxState = HAL_UART_STATE_BUSY_RX; 8001616: 2222 movs r2, #34 ; 0x22 huart->pRxBuffPtr = pData; 8001618: 6281 str r1, [r0, #40] ; 0x28 huart->RxXferSize = Size; 800161a: 8583 strh r3, [r0, #44] ; 0x2c huart->ErrorCode = HAL_UART_ERROR_NONE; 800161c: 63c4 str r4, [r0, #60] ; 0x3c huart->RxState = HAL_UART_STATE_BUSY_RX; 800161e: f880 203a strb.w r2, [r0, #58] ; 0x3a huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; 8001622: 6b40 ldr r0, [r0, #52] ; 0x34 8001624: 4a13 ldr r2, [pc, #76] ; (8001674 ) HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t*)tmp, Size); 8001626: 682e ldr r6, [r5, #0] huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; 8001628: 6282 str r2, [r0, #40] ; 0x28 huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; 800162a: 4a13 ldr r2, [pc, #76] ; (8001678 ) huart->hdmarx->XferAbortCallback = NULL; 800162c: 6344 str r4, [r0, #52] ; 0x34 huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; 800162e: 62c2 str r2, [r0, #44] ; 0x2c huart->hdmarx->XferErrorCallback = UART_DMAError; 8001630: 4a12 ldr r2, [pc, #72] ; (800167c ) 8001632: 6302 str r2, [r0, #48] ; 0x30 HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t*)tmp, Size); 8001634: 460a mov r2, r1 8001636: 1d31 adds r1, r6, #4 8001638: f7fe ff02 bl 8000440 return HAL_OK; 800163c: 4620 mov r0, r4 __HAL_UART_CLEAR_OREFLAG(huart); 800163e: 682b ldr r3, [r5, #0] 8001640: 9401 str r4, [sp, #4] 8001642: 681a ldr r2, [r3, #0] 8001644: 9201 str r2, [sp, #4] 8001646: 685a ldr r2, [r3, #4] __HAL_UNLOCK(huart); 8001648: f885 4038 strb.w r4, [r5, #56] ; 0x38 __HAL_UART_CLEAR_OREFLAG(huart); 800164c: 9201 str r2, [sp, #4] 800164e: 9a01 ldr r2, [sp, #4] SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8001650: 68da ldr r2, [r3, #12] 8001652: f442 7280 orr.w r2, r2, #256 ; 0x100 8001656: 60da str r2, [r3, #12] SET_BIT(huart->Instance->CR3, USART_CR3_EIE); 8001658: 695a ldr r2, [r3, #20] 800165a: f042 0201 orr.w r2, r2, #1 800165e: 615a str r2, [r3, #20] SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8001660: 695a ldr r2, [r3, #20] 8001662: f042 0240 orr.w r2, r2, #64 ; 0x40 8001666: 615a str r2, [r3, #20] } 8001668: b002 add sp, #8 800166a: bd70 pop {r4, r5, r6, pc} return HAL_ERROR; 800166c: 2001 movs r0, #1 800166e: e7fb b.n 8001668 return HAL_BUSY; 8001670: 2002 movs r0, #2 8001672: e7f9 b.n 8001668 8001674: 08001683 .word 0x08001683 8001678: 08001739 .word 0x08001739 800167c: 08001745 .word 0x08001745 08001680 : 8001680: 4770 bx lr 08001682 : { 8001682: b508 push {r3, lr} if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 8001684: 6803 ldr r3, [r0, #0] UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 8001686: 6a42 ldr r2, [r0, #36] ; 0x24 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 8001688: 681b ldr r3, [r3, #0] 800168a: f013 0320 ands.w r3, r3, #32 800168e: d110 bne.n 80016b2 huart->RxXferCount = 0U; 8001690: 85d3 strh r3, [r2, #46] ; 0x2e CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8001692: 6813 ldr r3, [r2, #0] 8001694: 68d9 ldr r1, [r3, #12] 8001696: f421 7180 bic.w r1, r1, #256 ; 0x100 800169a: 60d9 str r1, [r3, #12] CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 800169c: 6959 ldr r1, [r3, #20] 800169e: f021 0101 bic.w r1, r1, #1 80016a2: 6159 str r1, [r3, #20] CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 80016a4: 6959 ldr r1, [r3, #20] 80016a6: f021 0140 bic.w r1, r1, #64 ; 0x40 80016aa: 6159 str r1, [r3, #20] huart->RxState = HAL_UART_STATE_READY; 80016ac: 2320 movs r3, #32 80016ae: f882 303a strb.w r3, [r2, #58] ; 0x3a HAL_UART_RxCpltCallback(huart); 80016b2: 4610 mov r0, r2 80016b4: f000 fcbe bl 8002034 80016b8: bd08 pop {r3, pc} 080016ba : if(huart->RxState == HAL_UART_STATE_BUSY_RX) 80016ba: f890 303a ldrb.w r3, [r0, #58] ; 0x3a { 80016be: b510 push {r4, lr} if(huart->RxState == HAL_UART_STATE_BUSY_RX) 80016c0: 2b22 cmp r3, #34 ; 0x22 80016c2: d136 bne.n 8001732 if(huart->Init.WordLength == UART_WORDLENGTH_9B) 80016c4: 6883 ldr r3, [r0, #8] 80016c6: 6901 ldr r1, [r0, #16] 80016c8: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 80016cc: 6802 ldr r2, [r0, #0] 80016ce: 6a83 ldr r3, [r0, #40] ; 0x28 80016d0: d123 bne.n 800171a *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); 80016d2: 6852 ldr r2, [r2, #4] if(huart->Init.Parity == UART_PARITY_NONE) 80016d4: b9e9 cbnz r1, 8001712 *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); 80016d6: f3c2 0208 ubfx r2, r2, #0, #9 80016da: f823 2b02 strh.w r2, [r3], #2 huart->pRxBuffPtr += 1U; 80016de: 6283 str r3, [r0, #40] ; 0x28 if(--huart->RxXferCount == 0U) 80016e0: 8dc4 ldrh r4, [r0, #46] ; 0x2e 80016e2: 3c01 subs r4, #1 80016e4: b2a4 uxth r4, r4 80016e6: 85c4 strh r4, [r0, #46] ; 0x2e 80016e8: b98c cbnz r4, 800170e __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); 80016ea: 6803 ldr r3, [r0, #0] 80016ec: 68da ldr r2, [r3, #12] 80016ee: f022 0220 bic.w r2, r2, #32 80016f2: 60da str r2, [r3, #12] __HAL_UART_DISABLE_IT(huart, UART_IT_PE); 80016f4: 68da ldr r2, [r3, #12] 80016f6: f422 7280 bic.w r2, r2, #256 ; 0x100 80016fa: 60da str r2, [r3, #12] __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); 80016fc: 695a ldr r2, [r3, #20] 80016fe: f022 0201 bic.w r2, r2, #1 8001702: 615a str r2, [r3, #20] huart->RxState = HAL_UART_STATE_READY; 8001704: 2320 movs r3, #32 8001706: f880 303a strb.w r3, [r0, #58] ; 0x3a HAL_UART_RxCpltCallback(huart); 800170a: f000 fc93 bl 8002034 if(--huart->RxXferCount == 0U) 800170e: 2000 movs r0, #0 } 8001710: bd10 pop {r4, pc} *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF); 8001712: b2d2 uxtb r2, r2 8001714: f823 2b01 strh.w r2, [r3], #1 8001718: e7e1 b.n 80016de if(huart->Init.Parity == UART_PARITY_NONE) 800171a: b921 cbnz r1, 8001726 *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); 800171c: 1c59 adds r1, r3, #1 800171e: 6852 ldr r2, [r2, #4] 8001720: 6281 str r1, [r0, #40] ; 0x28 *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); 8001722: 701a strb r2, [r3, #0] 8001724: e7dc b.n 80016e0 8001726: 6852 ldr r2, [r2, #4] 8001728: 1c59 adds r1, r3, #1 800172a: 6281 str r1, [r0, #40] ; 0x28 800172c: f002 027f and.w r2, r2, #127 ; 0x7f 8001730: e7f7 b.n 8001722 return HAL_BUSY; 8001732: 2002 movs r0, #2 8001734: bd10 pop {r4, pc} 08001736 : 8001736: 4770 bx lr 08001738 : { 8001738: b508 push {r3, lr} HAL_UART_RxHalfCpltCallback(huart); 800173a: 6a40 ldr r0, [r0, #36] ; 0x24 800173c: f7ff fffb bl 8001736 8001740: bd08 pop {r3, pc} 08001742 : 8001742: 4770 bx lr 08001744 : UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 8001744: 6a41 ldr r1, [r0, #36] ; 0x24 { 8001746: b508 push {r3, lr} dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT); 8001748: 680b ldr r3, [r1, #0] 800174a: 695a ldr r2, [r3, #20] if((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) 800174c: f891 0039 ldrb.w r0, [r1, #57] ; 0x39 8001750: 2821 cmp r0, #33 ; 0x21 8001752: d10a bne.n 800176a 8001754: 0612 lsls r2, r2, #24 8001756: d508 bpl.n 800176a huart->TxXferCount = 0U; 8001758: 2200 movs r2, #0 800175a: 84ca strh r2, [r1, #38] ; 0x26 CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); 800175c: 68da ldr r2, [r3, #12] 800175e: f022 02c0 bic.w r2, r2, #192 ; 0xc0 8001762: 60da str r2, [r3, #12] huart->gState = HAL_UART_STATE_READY; 8001764: 2220 movs r2, #32 8001766: f881 2039 strb.w r2, [r1, #57] ; 0x39 dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 800176a: 695b ldr r3, [r3, #20] if((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest) 800176c: f891 203a ldrb.w r2, [r1, #58] ; 0x3a 8001770: 2a22 cmp r2, #34 ; 0x22 8001772: d106 bne.n 8001782 8001774: 065b lsls r3, r3, #25 8001776: d504 bpl.n 8001782 huart->RxXferCount = 0U; 8001778: 2300 movs r3, #0 UART_EndRxTransfer(huart); 800177a: 4608 mov r0, r1 huart->RxXferCount = 0U; 800177c: 85cb strh r3, [r1, #46] ; 0x2e UART_EndRxTransfer(huart); 800177e: f7ff fdd9 bl 8001334 huart->ErrorCode |= HAL_UART_ERROR_DMA; 8001782: 6bcb ldr r3, [r1, #60] ; 0x3c HAL_UART_ErrorCallback(huart); 8001784: 4608 mov r0, r1 huart->ErrorCode |= HAL_UART_ERROR_DMA; 8001786: f043 0310 orr.w r3, r3, #16 800178a: 63cb str r3, [r1, #60] ; 0x3c HAL_UART_ErrorCallback(huart); 800178c: f7ff ffd9 bl 8001742 8001790: bd08 pop {r3, pc} ... 08001794 : uint32_t isrflags = READ_REG(huart->Instance->SR); 8001794: 6803 ldr r3, [r0, #0] { 8001796: b570 push {r4, r5, r6, lr} uint32_t isrflags = READ_REG(huart->Instance->SR); 8001798: 681a ldr r2, [r3, #0] { 800179a: 4604 mov r4, r0 if(errorflags == RESET) 800179c: 0716 lsls r6, r2, #28 uint32_t cr1its = READ_REG(huart->Instance->CR1); 800179e: 68d9 ldr r1, [r3, #12] uint32_t cr3its = READ_REG(huart->Instance->CR3); 80017a0: 695d ldr r5, [r3, #20] if(errorflags == RESET) 80017a2: d107 bne.n 80017b4 if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 80017a4: 0696 lsls r6, r2, #26 80017a6: d55a bpl.n 800185e 80017a8: 068d lsls r5, r1, #26 80017aa: d558 bpl.n 800185e } 80017ac: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} UART_Receive_IT(huart); 80017b0: f7ff bf83 b.w 80016ba if((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) 80017b4: f015 0501 ands.w r5, r5, #1 80017b8: d102 bne.n 80017c0 80017ba: f411 7f90 tst.w r1, #288 ; 0x120 80017be: d04e beq.n 800185e if(((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) 80017c0: 07d3 lsls r3, r2, #31 80017c2: d505 bpl.n 80017d0 80017c4: 05ce lsls r6, r1, #23 huart->ErrorCode |= HAL_UART_ERROR_PE; 80017c6: bf42 ittt mi 80017c8: 6be3 ldrmi r3, [r4, #60] ; 0x3c 80017ca: f043 0301 orrmi.w r3, r3, #1 80017ce: 63e3 strmi r3, [r4, #60] ; 0x3c if(((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 80017d0: 0750 lsls r0, r2, #29 80017d2: d504 bpl.n 80017de 80017d4: b11d cbz r5, 80017de huart->ErrorCode |= HAL_UART_ERROR_NE; 80017d6: 6be3 ldr r3, [r4, #60] ; 0x3c 80017d8: f043 0302 orr.w r3, r3, #2 80017dc: 63e3 str r3, [r4, #60] ; 0x3c if(((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 80017de: 0793 lsls r3, r2, #30 80017e0: d504 bpl.n 80017ec 80017e2: b11d cbz r5, 80017ec huart->ErrorCode |= HAL_UART_ERROR_FE; 80017e4: 6be3 ldr r3, [r4, #60] ; 0x3c 80017e6: f043 0304 orr.w r3, r3, #4 80017ea: 63e3 str r3, [r4, #60] ; 0x3c if(((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 80017ec: 0716 lsls r6, r2, #28 80017ee: d504 bpl.n 80017fa 80017f0: b11d cbz r5, 80017fa huart->ErrorCode |= HAL_UART_ERROR_ORE; 80017f2: 6be3 ldr r3, [r4, #60] ; 0x3c 80017f4: f043 0308 orr.w r3, r3, #8 80017f8: 63e3 str r3, [r4, #60] ; 0x3c if(huart->ErrorCode != HAL_UART_ERROR_NONE) 80017fa: 6be3 ldr r3, [r4, #60] ; 0x3c 80017fc: 2b00 cmp r3, #0 80017fe: d066 beq.n 80018ce if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 8001800: 0695 lsls r5, r2, #26 8001802: d504 bpl.n 800180e 8001804: 0688 lsls r0, r1, #26 8001806: d502 bpl.n 800180e UART_Receive_IT(huart); 8001808: 4620 mov r0, r4 800180a: f7ff ff56 bl 80016ba dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 800180e: 6823 ldr r3, [r4, #0] UART_EndRxTransfer(huart); 8001810: 4620 mov r0, r4 dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 8001812: 695d ldr r5, [r3, #20] if(((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest) 8001814: 6be2 ldr r2, [r4, #60] ; 0x3c 8001816: 0711 lsls r1, r2, #28 8001818: d402 bmi.n 8001820 800181a: f015 0540 ands.w r5, r5, #64 ; 0x40 800181e: d01a beq.n 8001856 UART_EndRxTransfer(huart); 8001820: f7ff fd88 bl 8001334 if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8001824: 6823 ldr r3, [r4, #0] 8001826: 695a ldr r2, [r3, #20] 8001828: 0652 lsls r2, r2, #25 800182a: d510 bpl.n 800184e CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 800182c: 695a ldr r2, [r3, #20] if(huart->hdmarx != NULL) 800182e: 6b60 ldr r0, [r4, #52] ; 0x34 CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8001830: f022 0240 bic.w r2, r2, #64 ; 0x40 8001834: 615a str r2, [r3, #20] if(huart->hdmarx != NULL) 8001836: b150 cbz r0, 800184e huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; 8001838: 4b25 ldr r3, [pc, #148] ; (80018d0 ) 800183a: 6343 str r3, [r0, #52] ; 0x34 if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 800183c: f7fe fe3e bl 80004bc 8001840: 2800 cmp r0, #0 8001842: d044 beq.n 80018ce huart->hdmarx->XferAbortCallback(huart->hdmarx); 8001844: 6b60 ldr r0, [r4, #52] ; 0x34 } 8001846: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} huart->hdmarx->XferAbortCallback(huart->hdmarx); 800184a: 6b43 ldr r3, [r0, #52] ; 0x34 800184c: 4718 bx r3 HAL_UART_ErrorCallback(huart); 800184e: 4620 mov r0, r4 8001850: f7ff ff77 bl 8001742 8001854: bd70 pop {r4, r5, r6, pc} HAL_UART_ErrorCallback(huart); 8001856: f7ff ff74 bl 8001742 huart->ErrorCode = HAL_UART_ERROR_NONE; 800185a: 63e5 str r5, [r4, #60] ; 0x3c 800185c: bd70 pop {r4, r5, r6, pc} if(((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) 800185e: 0616 lsls r6, r2, #24 8001860: d527 bpl.n 80018b2 8001862: 060d lsls r5, r1, #24 8001864: d525 bpl.n 80018b2 if(huart->gState == HAL_UART_STATE_BUSY_TX) 8001866: f894 2039 ldrb.w r2, [r4, #57] ; 0x39 800186a: 2a21 cmp r2, #33 ; 0x21 800186c: d12f bne.n 80018ce if(huart->Init.WordLength == UART_WORDLENGTH_9B) 800186e: 68a2 ldr r2, [r4, #8] 8001870: f5b2 5f80 cmp.w r2, #4096 ; 0x1000 8001874: 6a22 ldr r2, [r4, #32] 8001876: d117 bne.n 80018a8 huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); 8001878: 8811 ldrh r1, [r2, #0] 800187a: f3c1 0108 ubfx r1, r1, #0, #9 800187e: 6059 str r1, [r3, #4] if(huart->Init.Parity == UART_PARITY_NONE) 8001880: 6921 ldr r1, [r4, #16] 8001882: b979 cbnz r1, 80018a4 huart->pTxBuffPtr += 2U; 8001884: 3202 adds r2, #2 huart->pTxBuffPtr += 1U; 8001886: 6222 str r2, [r4, #32] if(--huart->TxXferCount == 0U) 8001888: 8ce2 ldrh r2, [r4, #38] ; 0x26 800188a: 3a01 subs r2, #1 800188c: b292 uxth r2, r2 800188e: 84e2 strh r2, [r4, #38] ; 0x26 8001890: b9ea cbnz r2, 80018ce __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); 8001892: 68da ldr r2, [r3, #12] 8001894: f022 0280 bic.w r2, r2, #128 ; 0x80 8001898: 60da str r2, [r3, #12] __HAL_UART_ENABLE_IT(huart, UART_IT_TC); 800189a: 68da ldr r2, [r3, #12] 800189c: f042 0240 orr.w r2, r2, #64 ; 0x40 80018a0: 60da str r2, [r3, #12] 80018a2: bd70 pop {r4, r5, r6, pc} huart->pTxBuffPtr += 1U; 80018a4: 3201 adds r2, #1 80018a6: e7ee b.n 8001886 huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF); 80018a8: 1c51 adds r1, r2, #1 80018aa: 6221 str r1, [r4, #32] 80018ac: 7812 ldrb r2, [r2, #0] 80018ae: 605a str r2, [r3, #4] 80018b0: e7ea b.n 8001888 if(((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) 80018b2: 0650 lsls r0, r2, #25 80018b4: d50b bpl.n 80018ce 80018b6: 064a lsls r2, r1, #25 80018b8: d509 bpl.n 80018ce __HAL_UART_DISABLE_IT(huart, UART_IT_TC); 80018ba: 68da ldr r2, [r3, #12] HAL_UART_TxCpltCallback(huart); 80018bc: 4620 mov r0, r4 __HAL_UART_DISABLE_IT(huart, UART_IT_TC); 80018be: f022 0240 bic.w r2, r2, #64 ; 0x40 80018c2: 60da str r2, [r3, #12] huart->gState = HAL_UART_STATE_READY; 80018c4: 2320 movs r3, #32 80018c6: f884 3039 strb.w r3, [r4, #57] ; 0x39 HAL_UART_TxCpltCallback(huart); 80018ca: f7ff fed9 bl 8001680 80018ce: bd70 pop {r4, r5, r6, pc} 80018d0: 080018d5 .word 0x080018d5 080018d4 : { 80018d4: b508 push {r3, lr} huart->RxXferCount = 0x00U; 80018d6: 2300 movs r3, #0 UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 80018d8: 6a40 ldr r0, [r0, #36] ; 0x24 huart->RxXferCount = 0x00U; 80018da: 85c3 strh r3, [r0, #46] ; 0x2e huart->TxXferCount = 0x00U; 80018dc: 84c3 strh r3, [r0, #38] ; 0x26 HAL_UART_ErrorCallback(huart); 80018de: f7ff ff30 bl 8001742 80018e2: bd08 pop {r3, pc} 080018e4 : * Header Check Function * ***/ #define Bluecell_BootStart 0x0b void Firmware_BootStart_Signal(){ 80018e4: b507 push {r0, r1, r2, lr} uint8_t bootdata[5] = {0xbe,Bluecell_BootStart,0x02,0,0xeb}; 80018e6: 4b0b ldr r3, [pc, #44] ; (8001914 ) bootdata[bluecell_crc] = STH30_CreateCrc(&bootdata[bluecell_type],bootdata[bluecell_length]); 80018e8: 2102 movs r1, #2 uint8_t bootdata[5] = {0xbe,Bluecell_BootStart,0x02,0,0xeb}; 80018ea: 6818 ldr r0, [r3, #0] 80018ec: 791b ldrb r3, [r3, #4] 80018ee: 9000 str r0, [sp, #0] bootdata[bluecell_crc] = STH30_CreateCrc(&bootdata[bluecell_type],bootdata[bluecell_length]); 80018f0: f10d 0001 add.w r0, sp, #1 uint8_t bootdata[5] = {0xbe,Bluecell_BootStart,0x02,0,0xeb}; 80018f4: f88d 3004 strb.w r3, [sp, #4] bootdata[bluecell_crc] = STH30_CreateCrc(&bootdata[bluecell_type],bootdata[bluecell_length]); 80018f8: f000 f866 bl 80019c8 Uart1_Data_Send(&bootdata[bluecell_stx],bootdata[bluecell_length] + 3); 80018fc: f89d 1002 ldrb.w r1, [sp, #2] bootdata[bluecell_crc] = STH30_CreateCrc(&bootdata[bluecell_type],bootdata[bluecell_length]); 8001900: f88d 0003 strb.w r0, [sp, #3] Uart1_Data_Send(&bootdata[bluecell_stx],bootdata[bluecell_length] + 3); 8001904: 3103 adds r1, #3 8001906: 4668 mov r0, sp 8001908: f000 fbba bl 8002080 } 800190c: b003 add sp, #12 800190e: f85d fb04 ldr.w pc, [sp], #4 8001912: bf00 nop 8001914: 080031b4 .word 0x080031b4 08001918 : void FirmwareUpdateStart(uint8_t* data){ 8001918: b573 push {r0, r1, r4, r5, r6, lr} 800191a: 4604 mov r4, r0 uint8_t ret = 0,crccheck = 0; uint8_t tempdata[5] = {0xbe,FirmwareUpdataAck,0x02,0,0xbe}; 800191c: 4b26 ldr r3, [pc, #152] ; (80019b8 ) crccheck = STH30_CheckCrc(&data[bluecell_type],data[bluecell_length],data[data[bluecell_length] + 1]); 800191e: 78a1 ldrb r1, [r4, #2] uint8_t tempdata[5] = {0xbe,FirmwareUpdataAck,0x02,0,0xbe}; 8001920: 6818 ldr r0, [r3, #0] 8001922: 791b ldrb r3, [r3, #4] 8001924: 9000 str r0, [sp, #0] 8001926: f88d 3004 strb.w r3, [sp, #4] crccheck = STH30_CheckCrc(&data[bluecell_type],data[bluecell_length],data[data[bluecell_length] + 1]); 800192a: 1863 adds r3, r4, r1 800192c: 785a ldrb r2, [r3, #1] 800192e: 1c60 adds r0, r4, #1 8001930: f000 f865 bl 80019fe if(crccheck == NO_ERROR){ 8001934: b2c0 uxtb r0, r0 8001936: 2801 cmp r0, #1 8001938: d00b beq.n 8001952 800193a: 2300 movs r3, #0 ret = Flash_write(&data[0]); if(ret == 1) tempdata[bluecell_type] = FirmwareUpdataNak; }else{ for(uint8_t i = 0; i < data[bluecell_length] + 3; i++) printf("%02x ",data[i]); 800193c: 4e1f ldr r6, [pc, #124] ; (80019bc ) for(uint8_t i = 0; i < data[bluecell_length] + 3; i++) 800193e: 78a2 ldrb r2, [r4, #2] 8001940: 1c5d adds r5, r3, #1 8001942: 3202 adds r2, #2 8001944: b2db uxtb r3, r3 8001946: 429a cmp r2, r3 8001948: da2f bge.n 80019aa printf("Check Sum error \n"); 800194a: 481d ldr r0, [pc, #116] ; (80019c0 ) 800194c: f000 fc6c bl 8002228 8001950: e00d b.n 800196e tempdata[bluecell_type] = FirmwareUpdataAck; 8001952: 2311 movs r3, #17 8001954: f88d 3001 strb.w r3, [sp, #1] if(data[bluecell_type] == 0xDD || data[bluecell_type] == 0xEE)//Start Firmware byte 8001958: 7863 ldrb r3, [r4, #1] 800195a: 2bdd cmp r3, #221 ; 0xdd 800195c: d001 beq.n 8001962 800195e: 2bee cmp r3, #238 ; 0xee 8001960: d108 bne.n 8001974 ret = Flash_write(&data[0]); 8001962: 4620 mov r0, r4 8001964: f000 f8c6 bl 8001af4 if(ret == 1) 8001968: b2c0 uxtb r0, r0 800196a: 2801 cmp r0, #1 800196c: d102 bne.n 8001974 tempdata[bluecell_type] = FirmwareUpdataNak; 800196e: 2322 movs r3, #34 ; 0x22 8001970: f88d 3001 strb.w r3, [sp, #1] } tempdata[bluecell_crc] = STH30_CreateCrc(&tempdata[bluecell_type],tempdata[bluecell_length]); 8001974: f89d 1002 ldrb.w r1, [sp, #2] 8001978: f10d 0001 add.w r0, sp, #1 800197c: f000 f824 bl 80019c8 if(data[bluecell_type] != 0xEE && data[bluecell_type] != Bluecell_Reset){ 8001980: 7863 ldrb r3, [r4, #1] tempdata[bluecell_crc] = STH30_CreateCrc(&tempdata[bluecell_type],tempdata[bluecell_length]); 8001982: f88d 0003 strb.w r0, [sp, #3] if(data[bluecell_type] != 0xEE && data[bluecell_type] != Bluecell_Reset){ 8001986: 2bee cmp r3, #238 ; 0xee 8001988: d007 beq.n 800199a 800198a: 2b0a cmp r3, #10 800198c: d005 beq.n 800199a Uart1_Data_Send(&tempdata[bluecell_stx],tempdata[bluecell_length] + 3); 800198e: f89d 1002 ldrb.w r1, [sp, #2] 8001992: 4668 mov r0, sp 8001994: 3103 adds r1, #3 8001996: f000 fb73 bl 8002080 } if(data[bluecell_type] == 0xEE) 800199a: 7863 ldrb r3, [r4, #1] 800199c: 2bee cmp r3, #238 ; 0xee 800199e: d102 bne.n 80019a6 printf("update Complete \n"); 80019a0: 4808 ldr r0, [pc, #32] ; (80019c4 ) 80019a2: f000 fc41 bl 8002228 } 80019a6: b002 add sp, #8 80019a8: bd70 pop {r4, r5, r6, pc} printf("%02x ",data[i]); 80019aa: 5ce1 ldrb r1, [r4, r3] 80019ac: 4630 mov r0, r6 80019ae: f000 fbc7 bl 8002140 80019b2: 462b mov r3, r5 80019b4: e7c3 b.n 800193e 80019b6: bf00 nop 80019b8: 080031b9 .word 0x080031b9 80019bc: 080031be .word 0x080031be 80019c0: 080031c4 .word 0x080031c4 80019c4: 080031d5 .word 0x080031d5 080019c8 : } return(crc16 == checksum ? CHECKSUM_ERROR : NO_ERROR ); } uint8_t STH30_CreateCrc(uint8_t *data, uint8_t nbrOfBytes) { 80019c8: b510 push {r4, lr} uint8_t bit; // bit mask uint8_t crc = 0xFF; // calculated checksum 80019ca: 23ff movs r3, #255 ; 0xff uint8_t byteCtr; // byte counter // calculates 8-Bit checksum with given polynomial for(byteCtr = 0; byteCtr < nbrOfBytes; byteCtr++) 80019cc: 4604 mov r4, r0 80019ce: 1a22 subs r2, r4, r0 80019d0: b2d2 uxtb r2, r2 80019d2: 4291 cmp r1, r2 80019d4: d801 bhi.n 80019da if(crc & 0x80) crc = (crc << 1) ^ POLYNOMIAL; else crc = (crc << 1); } } return crc; } 80019d6: 4618 mov r0, r3 80019d8: bd10 pop {r4, pc} crc ^= (data[byteCtr]); 80019da: f814 2b01 ldrb.w r2, [r4], #1 80019de: 4053 eors r3, r2 80019e0: 2208 movs r2, #8 if(crc & 0x80) crc = (crc << 1) ^ POLYNOMIAL; 80019e2: f013 0f80 tst.w r3, #128 ; 0x80 80019e6: f102 32ff add.w r2, r2, #4294967295 80019ea: ea4f 0343 mov.w r3, r3, lsl #1 80019ee: bf18 it ne 80019f0: f083 0331 eorne.w r3, r3, #49 ; 0x31 for(bit = 8; bit > 0; --bit) 80019f4: f012 02ff ands.w r2, r2, #255 ; 0xff else crc = (crc << 1); 80019f8: b2db uxtb r3, r3 for(bit = 8; bit > 0; --bit) 80019fa: d1f2 bne.n 80019e2 80019fc: e7e7 b.n 80019ce 080019fe : etError STH30_CheckCrc(uint8_t *data, uint8_t nbrOfBytes, uint8_t checksum) { 80019fe: b530 push {r4, r5, lr} uint8_t bit; // bit mask uint8_t crc = 0xFF; // calculated checksum 8001a00: 23ff movs r3, #255 ; 0xff uint8_t byteCtr; // byte counter // calculates 8-Bit checksum with given polynomial for(byteCtr = 0; byteCtr < nbrOfBytes; byteCtr++) 8001a02: 4605 mov r5, r0 8001a04: 1a2c subs r4, r5, r0 8001a06: b2e4 uxtb r4, r4 8001a08: 42a1 cmp r1, r4 8001a0a: d803 bhi.n 8001a14 else crc = (crc << 1); } } if(crc != checksum) return CHECKSUM_ERROR; else return NO_ERROR; } 8001a0c: 1a9b subs r3, r3, r2 8001a0e: 4258 negs r0, r3 8001a10: 4158 adcs r0, r3 8001a12: bd30 pop {r4, r5, pc} crc ^= (data[byteCtr]); 8001a14: f815 4b01 ldrb.w r4, [r5], #1 8001a18: 4063 eors r3, r4 8001a1a: 2408 movs r4, #8 if(crc & 0x80) crc = (crc << 1) ^ POLYNOMIAL; 8001a1c: f013 0f80 tst.w r3, #128 ; 0x80 8001a20: f104 34ff add.w r4, r4, #4294967295 8001a24: ea4f 0343 mov.w r3, r3, lsl #1 8001a28: bf18 it ne 8001a2a: f083 0331 eorne.w r3, r3, #49 ; 0x31 for(bit = 8; bit > 0; --bit) 8001a2e: f014 04ff ands.w r4, r4, #255 ; 0xff else crc = (crc << 1); 8001a32: b2db uxtb r3, r3 for(bit = 8; bit > 0; --bit) 8001a34: d1f2 bne.n 8001a1c 8001a36: e7e5 b.n 8001a04 08001a38 : uint32_t Address = FLASH_USER_START_ADDR; typedef void (*fptr)(void); fptr jump_to_app; uint32_t jump_addr; void Jump_App(void){ 8001a38: b5b0 push {r4, r5, r7, lr} __HAL_RCC_TIM6_CLK_DISABLE(); // 매인???��머�?? ?���??��?��?�� 8001a3a: 4a0d ldr r2, [pc, #52] ; (8001a70 ) void Jump_App(void){ 8001a3c: af00 add r7, sp, #0 __HAL_RCC_TIM6_CLK_DISABLE(); // 매인???��머�?? ?���??��?��?�� 8001a3e: 69d3 ldr r3, [r2, #28] printf("boot loader start\n"); //메세�? 출력 8001a40: 480c ldr r0, [pc, #48] ; (8001a74 ) __HAL_RCC_TIM6_CLK_DISABLE(); // 매인???��머�?? ?���??��?��?�� 8001a42: f023 0310 bic.w r3, r3, #16 8001a46: 61d3 str r3, [r2, #28] printf("boot loader start\n"); //메세�? 출력 8001a48: f000 fbee bl 8002228 jump_addr = *(__IO uint32_t*) (APPLICATION_ADDRESS + 4); 8001a4c: 4b0a ldr r3, [pc, #40] ; (8001a78 ) 8001a4e: 4a0b ldr r2, [pc, #44] ; (8001a7c ) 8001a50: 681b ldr r3, [r3, #0] jump_to_app = (fptr) jump_addr; 8001a52: 4c0b ldr r4, [pc, #44] ; (8001a80 ) /* init user app's sp */ printf("jump!\n"); 8001a54: 480b ldr r0, [pc, #44] ; (8001a84 ) jump_addr = *(__IO uint32_t*) (APPLICATION_ADDRESS + 4); 8001a56: 6013 str r3, [r2, #0] jump_to_app = (fptr) jump_addr; 8001a58: 6023 str r3, [r4, #0] printf("jump!\n"); 8001a5a: f000 fbe5 bl 8002228 __set_MSP(*(__IO uint32_t*) APPLICATION_ADDRESS); 8001a5e: 4b0a ldr r3, [pc, #40] ; (8001a88 ) 8001a60: 681b ldr r3, [r3, #0] __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); 8001a62: f383 8808 msr MSP, r3 jump_to_app(); 8001a66: 6823 ldr r3, [r4, #0] } 8001a68: 46bd mov sp, r7 8001a6a: e8bd 40b0 ldmia.w sp!, {r4, r5, r7, lr} jump_to_app(); 8001a6e: 4718 bx r3 8001a70: 40021000 .word 0x40021000 8001a74: 08003201 .word 0x08003201 8001a78: 08004004 .word 0x08004004 8001a7c: 200004f0 .word 0x200004f0 8001a80: 200004f4 .word 0x200004f4 8001a84: 08003213 .word 0x08003213 8001a88: 08004000 .word 0x08004000 08001a8c : } #endif // PYJ.2019.03.27_END -- } uint8_t Flash_RGB_Data_Write(uint8_t* data){ 8001a8c: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} uint16_t Firmdata = 0; uint8_t ret = 0; for(uint8_t i = 0; i < data[bluecell_length] - 2; i+=2){ 8001a90: 2400 movs r4, #0 uint8_t Flash_RGB_Data_Write(uint8_t* data){ 8001a92: 4607 mov r7, r0 uint8_t ret = 0; 8001a94: 4626 mov r6, r4 Firmdata = ((data[(bluecell_length + 1) + i]) & 0x00FF); Firmdata += ((data[(bluecell_length + 1) + (i + 1)] << 8) & 0xFF00); if(HAL_FLASH_Program(FLASH_TYPEPROGRAM_HALFWORD,Address , (uint16_t)Firmdata) != HAL_OK){ 8001a96: 4d15 ldr r5, [pc, #84] ; (8001aec ) printf("HAL NOT OK \n"); 8001a98: f8df 8054 ldr.w r8, [pc, #84] ; 8001af0 for(uint8_t i = 0; i < data[bluecell_length] - 2; i+=2){ 8001a9c: 78bb ldrb r3, [r7, #2] 8001a9e: 3b02 subs r3, #2 8001aa0: 429c cmp r4, r3 8001aa2: db02 blt.n 8001aaa Address += 2; if(!(i%FirmwareUpdateDelay)) HAL_Delay(1); } return ret; } 8001aa4: 4630 mov r0, r6 8001aa6: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} Firmdata = ((data[(bluecell_length + 1) + i]) & 0x00FF); 8001aaa: 193b adds r3, r7, r4 8001aac: 78da ldrb r2, [r3, #3] Firmdata += ((data[(bluecell_length + 1) + (i + 1)] << 8) & 0xFF00); 8001aae: 791b ldrb r3, [r3, #4] if(HAL_FLASH_Program(FLASH_TYPEPROGRAM_HALFWORD,Address , (uint16_t)Firmdata) != HAL_OK){ 8001ab0: 6829 ldr r1, [r5, #0] Firmdata += ((data[(bluecell_length + 1) + (i + 1)] << 8) & 0xFF00); 8001ab2: eb02 2203 add.w r2, r2, r3, lsl #8 if(HAL_FLASH_Program(FLASH_TYPEPROGRAM_HALFWORD,Address , (uint16_t)Firmdata) != HAL_OK){ 8001ab6: b292 uxth r2, r2 8001ab8: 2300 movs r3, #0 8001aba: 2001 movs r0, #1 8001abc: f7fe feb6 bl 800082c 8001ac0: b118 cbz r0, 8001aca printf("HAL NOT OK \n"); 8001ac2: 4640 mov r0, r8 8001ac4: f000 fbb0 bl 8002228 ret = 1; 8001ac8: 2601 movs r6, #1 if(!(i%FirmwareUpdateDelay)) 8001aca: 2232 movs r2, #50 ; 0x32 Address += 2; 8001acc: 682b ldr r3, [r5, #0] 8001ace: 3302 adds r3, #2 8001ad0: 602b str r3, [r5, #0] if(!(i%FirmwareUpdateDelay)) 8001ad2: fbb4 f3f2 udiv r3, r4, r2 8001ad6: fb02 4313 mls r3, r2, r3, r4 8001ada: f013 0fff tst.w r3, #255 ; 0xff 8001ade: d102 bne.n 8001ae6 HAL_Delay(1); 8001ae0: 2001 movs r0, #1 8001ae2: f7fe fbf3 bl 80002cc for(uint8_t i = 0; i < data[bluecell_length] - 2; i+=2){ 8001ae6: 3402 adds r4, #2 8001ae8: b2e4 uxtb r4, r4 8001aea: e7d7 b.n 8001a9c 8001aec: 20000008 .word 0x20000008 8001af0: 080031e6 .word 0x080031e6 08001af4 : /*Variable used for Erase procedure*/ static FLASH_EraseInitTypeDef EraseInitStruct; static uint32_t PAGEError = 0; uint8_t ret = 0; /* Fill EraseInit structure*/ EraseInitStruct.TypeErase = FLASH_TYPEERASE_PAGES; 8001af4: 2300 movs r3, #0 { 8001af6: b573 push {r0, r1, r4, r5, r6, lr} EraseInitStruct.TypeErase = FLASH_TYPEERASE_PAGES; 8001af8: 4d16 ldr r5, [pc, #88] ; (8001b54 ) EraseInitStruct.PageAddress = FLASH_USER_START_ADDR; EraseInitStruct.NbPages = (FLASH_USER_END_ADDR - FLASH_USER_START_ADDR) / FLASH_PAGE_SIZE; __HAL_RCC_TIM6_CLK_DISABLE(); // 매인???��머�?? ?���??��?��?�� 8001afa: 4c17 ldr r4, [pc, #92] ; (8001b58 ) EraseInitStruct.TypeErase = FLASH_TYPEERASE_PAGES; 8001afc: 602b str r3, [r5, #0] EraseInitStruct.PageAddress = FLASH_USER_START_ADDR; 8001afe: 4b17 ldr r3, [pc, #92] ; (8001b5c ) { 8001b00: 4606 mov r6, r0 EraseInitStruct.PageAddress = FLASH_USER_START_ADDR; 8001b02: 60ab str r3, [r5, #8] EraseInitStruct.NbPages = (FLASH_USER_END_ADDR - FLASH_USER_START_ADDR) / FLASH_PAGE_SIZE; 8001b04: 231f movs r3, #31 8001b06: 60eb str r3, [r5, #12] __HAL_RCC_TIM6_CLK_DISABLE(); // 매인???��머�?? ?���??��?��?�� 8001b08: 69e3 ldr r3, [r4, #28] 8001b0a: f023 0310 bic.w r3, r3, #16 8001b0e: 61e3 str r3, [r4, #28] HAL_FLASH_Unlock(); // lock ??�? 8001b10: f7fe fe46 bl 80007a0 if(flashinit == 0){ 8001b14: 4b12 ldr r3, [pc, #72] ; (8001b60 ) 8001b16: 781a ldrb r2, [r3, #0] 8001b18: b94a cbnz r2, 8001b2e flashinit= 1; 8001b1a: 2201 movs r2, #1 //FLASH_PageErase(StartAddr); if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK){ 8001b1c: 4911 ldr r1, [pc, #68] ; (8001b64 ) 8001b1e: 4628 mov r0, r5 flashinit= 1; 8001b20: 701a strb r2, [r3, #0] if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK){ 8001b22: f7fe feed bl 8000900 8001b26: b110 cbz r0, 8001b2e printf("Erase Failed \r\n"); 8001b28: 480f ldr r0, [pc, #60] ; (8001b68 ) 8001b2a: f000 fb7d bl 8002228 } } // FLASH_If_Erase(); ret = Flash_RGB_Data_Write(&data[bluecell_stx]); 8001b2e: 4630 mov r0, r6 8001b30: f7ff ffac bl 8001a8c 8001b34: 4605 mov r5, r0 HAL_FLASH_Lock(); // lock ?��그기 8001b36: f7fe fe45 bl 80007c4 __HAL_RCC_TIM6_CLK_ENABLE(); // 매인???��머�?? ?��?��?��?��?��?�� return ret; } 8001b3a: 4628 mov r0, r5 __HAL_RCC_TIM6_CLK_ENABLE(); // 매인???��머�?? ?��?��?��?��?��?�� 8001b3c: 69e3 ldr r3, [r4, #28] 8001b3e: f043 0310 orr.w r3, r3, #16 8001b42: 61e3 str r3, [r4, #28] 8001b44: 69e3 ldr r3, [r4, #28] 8001b46: f003 0310 and.w r3, r3, #16 8001b4a: 9301 str r3, [sp, #4] 8001b4c: 9b01 ldr r3, [sp, #4] } 8001b4e: b002 add sp, #8 8001b50: bd70 pop {r4, r5, r6, pc} 8001b52: bf00 nop 8001b54: 20000094 .word 0x20000094 8001b58: 40021000 .word 0x40021000 8001b5c: 08004000 .word 0x08004000 8001b60: 200000a8 .word 0x200000a8 8001b64: 200000a4 .word 0x200000a4 8001b68: 080031f2 .word 0x080031f2 08001b6c : /* Private user code ---------------------------------------------------------*/ /* USER CODE BEGIN 0 */ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { if(htim->Instance == TIM6){ 8001b6c: 6802 ldr r2, [r0, #0] 8001b6e: 4b08 ldr r3, [pc, #32] ; (8001b90 ) 8001b70: 429a cmp r2, r3 8001b72: d10b bne.n 8001b8c UartTimerCnt++; 8001b74: 4a07 ldr r2, [pc, #28] ; (8001b94 ) 8001b76: 6813 ldr r3, [r2, #0] 8001b78: 3301 adds r3, #1 8001b7a: 6013 str r3, [r2, #0] LedTimerCnt++; 8001b7c: 4a06 ldr r2, [pc, #24] ; (8001b98 ) 8001b7e: 6813 ldr r3, [r2, #0] 8001b80: 3301 adds r3, #1 8001b82: 6013 str r3, [r2, #0] FirmwareTimerCnt++; 8001b84: 4a05 ldr r2, [pc, #20] ; (8001b9c ) 8001b86: 6813 ldr r3, [r2, #0] 8001b88: 3301 adds r3, #1 8001b8a: 6013 str r3, [r2, #0] 8001b8c: 4770 bx lr 8001b8e: bf00 nop 8001b90: 40001000 .word 0x40001000 8001b94: 200000b4 .word 0x200000b4 8001b98: 200000b0 .word 0x200000b0 8001b9c: 200000ac .word 0x200000ac 08001ba0 <_write>: } } int _write (int file, uint8_t *ptr, uint16_t len) { 8001ba0: b510 push {r4, lr} 8001ba2: 4614 mov r4, r2 HAL_UART_Transmit (&huart1, ptr, len, 10); 8001ba4: 230a movs r3, #10 8001ba6: 4802 ldr r0, [pc, #8] ; (8001bb0 <_write+0x10>) 8001ba8: f7ff fcc6 bl 8001538 return len; } 8001bac: 4620 mov r0, r4 8001bae: bd10 pop {r4, pc} 8001bb0: 2000053c .word 0x2000053c 08001bb4 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8001bb4: b510 push {r4, lr} 8001bb6: b090 sub sp, #64 ; 0x40 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8001bb8: 2228 movs r2, #40 ; 0x28 8001bba: 2100 movs r1, #0 8001bbc: a806 add r0, sp, #24 8001bbe: f000 fab7 bl 8002130 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8001bc2: 2214 movs r2, #20 8001bc4: 2100 movs r1, #0 8001bc6: a801 add r0, sp, #4 8001bc8: f000 fab2 bl 8002130 /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; RCC_OscInitStruct.HSIState = RCC_HSI_ON; 8001bcc: 2301 movs r3, #1 8001bce: 930a str r3, [sp, #40] ; 0x28 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 8001bd0: 2310 movs r3, #16 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; 8001bd2: 2402 movs r4, #2 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 8001bd4: 930b str r3, [sp, #44] ; 0x2c RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2; RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL15; 8001bd6: f44f 1350 mov.w r3, #3407872 ; 0x340000 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8001bda: a806 add r0, sp, #24 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL15; 8001bdc: 930f str r3, [sp, #60] ; 0x3c RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; 8001bde: 9406 str r4, [sp, #24] RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 8001be0: 940d str r4, [sp, #52] ; 0x34 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8001be2: f7fe ffd1 bl 8000b88 { Error_Handler(); } /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8001be6: 230f movs r3, #15 |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 8001be8: f44f 6280 mov.w r2, #1024 ; 0x400 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8001bec: 9301 str r3, [sp, #4] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 8001bee: 2300 movs r3, #0 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 8001bf0: 4621 mov r1, r4 8001bf2: a801 add r0, sp, #4 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 8001bf4: 9402 str r4, [sp, #8] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 8001bf6: 9303 str r3, [sp, #12] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 8001bf8: 9204 str r2, [sp, #16] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 8001bfa: 9305 str r3, [sp, #20] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 8001bfc: f7ff f98c bl 8000f18 { Error_Handler(); } } 8001c00: b010 add sp, #64 ; 0x40 8001c02: bd10 pop {r4, pc} 08001c04
: { 8001c04: b580 push {r7, lr} 8001c06: b088 sub sp, #32 HAL_Init(); 8001c08: f7fe fb3c bl 8000284 SystemClock_Config(); 8001c0c: f7ff ffd2 bl 8001bb4 * @param None * @retval None */ static void MX_GPIO_Init(void) { GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001c10: 2210 movs r2, #16 /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOA_CLK_ENABLE(); 8001c12: 4d58 ldr r5, [pc, #352] ; (8001d74 ) GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001c14: 2100 movs r1, #0 8001c16: eb0d 0002 add.w r0, sp, r2 8001c1a: f000 fa89 bl 8002130 __HAL_RCC_GPIOA_CLK_ENABLE(); 8001c1e: 69ab ldr r3, [r5, #24] __HAL_RCC_GPIOG_CLK_ENABLE(); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOA, GPIO_PIN_15, GPIO_PIN_RESET); 8001c20: 2200 movs r2, #0 __HAL_RCC_GPIOA_CLK_ENABLE(); 8001c22: f043 0304 orr.w r3, r3, #4 8001c26: 61ab str r3, [r5, #24] 8001c28: 69ab ldr r3, [r5, #24] HAL_GPIO_WritePin(GPIOA, GPIO_PIN_15, GPIO_PIN_RESET); 8001c2a: f44f 4100 mov.w r1, #32768 ; 0x8000 __HAL_RCC_GPIOA_CLK_ENABLE(); 8001c2e: f003 0304 and.w r3, r3, #4 8001c32: 9302 str r3, [sp, #8] 8001c34: 9b02 ldr r3, [sp, #8] __HAL_RCC_GPIOG_CLK_ENABLE(); 8001c36: 69ab ldr r3, [r5, #24] HAL_GPIO_WritePin(GPIOA, GPIO_PIN_15, GPIO_PIN_RESET); 8001c38: 484f ldr r0, [pc, #316] ; (8001d78 ) __HAL_RCC_GPIOG_CLK_ENABLE(); 8001c3a: f443 7380 orr.w r3, r3, #256 ; 0x100 8001c3e: 61ab str r3, [r5, #24] 8001c40: 69ab ldr r3, [r5, #24] HAL_GPIO_WritePin(BOOT_LED_GPIO_Port, BOOT_LED_Pin, GPIO_PIN_RESET); /*Configure GPIO pin : PA15 */ GPIO_InitStruct.Pin = GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; 8001c42: 2400 movs r4, #0 __HAL_RCC_GPIOG_CLK_ENABLE(); 8001c44: f403 7380 and.w r3, r3, #256 ; 0x100 8001c48: 9303 str r3, [sp, #12] 8001c4a: 9b03 ldr r3, [sp, #12] HAL_GPIO_WritePin(GPIOA, GPIO_PIN_15, GPIO_PIN_RESET); 8001c4c: f7fe ff92 bl 8000b74 HAL_GPIO_WritePin(BOOT_LED_GPIO_Port, BOOT_LED_Pin, GPIO_PIN_RESET); 8001c50: 2200 movs r2, #0 8001c52: f44f 4180 mov.w r1, #16384 ; 0x4000 8001c56: 4849 ldr r0, [pc, #292] ; (8001d7c ) 8001c58: f7fe ff8c bl 8000b74 GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8001c5c: 2701 movs r7, #1 GPIO_InitStruct.Pin = GPIO_PIN_15; 8001c5e: f44f 4300 mov.w r3, #32768 ; 0x8000 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001c62: 2602 movs r6, #2 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001c64: a904 add r1, sp, #16 8001c66: 4844 ldr r0, [pc, #272] ; (8001d78 ) GPIO_InitStruct.Pin = GPIO_PIN_15; 8001c68: 9304 str r3, [sp, #16] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001c6a: 9607 str r6, [sp, #28] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8001c6c: 9705 str r7, [sp, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001c6e: 9406 str r4, [sp, #24] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001c70: f7fe fe94 bl 800099c /*Configure GPIO pin : BOOT_LED_Pin */ GPIO_InitStruct.Pin = BOOT_LED_Pin; 8001c74: f44f 4380 mov.w r3, #16384 ; 0x4000 GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; HAL_GPIO_Init(BOOT_LED_GPIO_Port, &GPIO_InitStruct); 8001c78: a904 add r1, sp, #16 8001c7a: 4840 ldr r0, [pc, #256] ; (8001d7c ) GPIO_InitStruct.Pin = BOOT_LED_Pin; 8001c7c: 9304 str r3, [sp, #16] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001c7e: 9607 str r6, [sp, #28] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8001c80: 9705 str r7, [sp, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001c82: 9406 str r4, [sp, #24] HAL_GPIO_Init(BOOT_LED_GPIO_Port, &GPIO_InitStruct); 8001c84: f7fe fe8a bl 800099c __HAL_RCC_DMA1_CLK_ENABLE(); 8001c88: 696b ldr r3, [r5, #20] huart1.Instance = USART1; 8001c8a: 483d ldr r0, [pc, #244] ; (8001d80 ) __HAL_RCC_DMA1_CLK_ENABLE(); 8001c8c: 433b orrs r3, r7 8001c8e: 616b str r3, [r5, #20] 8001c90: 696b ldr r3, [r5, #20] huart1.Init.BaudRate = 115200; 8001c92: 4a3c ldr r2, [pc, #240] ; (8001d84 ) __HAL_RCC_DMA1_CLK_ENABLE(); 8001c94: 403b ands r3, r7 8001c96: 9301 str r3, [sp, #4] 8001c98: 9b01 ldr r3, [sp, #4] huart1.Init.BaudRate = 115200; 8001c9a: f44f 33e1 mov.w r3, #115200 ; 0x1c200 8001c9e: e880 000c stmia.w r0, {r2, r3} huart1.Init.Mode = UART_MODE_TX_RX; 8001ca2: 230c movs r3, #12 huart1.Init.WordLength = UART_WORDLENGTH_8B; 8001ca4: 6084 str r4, [r0, #8] huart1.Init.Mode = UART_MODE_TX_RX; 8001ca6: 6143 str r3, [r0, #20] huart1.Init.StopBits = UART_STOPBITS_1; 8001ca8: 60c4 str r4, [r0, #12] huart1.Init.Parity = UART_PARITY_NONE; 8001caa: 6104 str r4, [r0, #16] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8001cac: 6184 str r4, [r0, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 8001cae: 61c4 str r4, [r0, #28] if (HAL_UART_Init(&huart1) != HAL_OK) 8001cb0: f7ff fc14 bl 80014dc htim6.Init.Prescaler = 6000 - 1; 8001cb4: f241 736f movw r3, #5999 ; 0x176f htim6.Instance = TIM6; 8001cb8: 4d33 ldr r5, [pc, #204] ; (8001d88 ) htim6.Init.Prescaler = 6000 - 1; 8001cba: 4934 ldr r1, [pc, #208] ; (8001d8c ) if (HAL_TIM_Base_Init(&htim6) != HAL_OK) 8001cbc: 4628 mov r0, r5 htim6.Init.Prescaler = 6000 - 1; 8001cbe: e885 000a stmia.w r5, {r1, r3} htim6.Init.Period = 10 - 1; 8001cc2: 2309 movs r3, #9 htim6.Init.CounterMode = TIM_COUNTERMODE_UP; 8001cc4: 60ac str r4, [r5, #8] htim6.Init.Period = 10 - 1; 8001cc6: 60eb str r3, [r5, #12] htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8001cc8: 61ac str r4, [r5, #24] TIM_MasterConfigTypeDef sMasterConfig = {0}; 8001cca: 9404 str r4, [sp, #16] 8001ccc: 9405 str r4, [sp, #20] if (HAL_TIM_Base_Init(&htim6) != HAL_OK) 8001cce: f7ff faf3 bl 80012b8 if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK) 8001cd2: a904 add r1, sp, #16 8001cd4: 4628 mov r0, r5 sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8001cd6: 9404 str r4, [sp, #16] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8001cd8: 9405 str r4, [sp, #20] if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK) 8001cda: f7ff fb07 bl 80012ec HAL_NVIC_SetPriority(DMA1_Channel5_IRQn, 0, 0); 8001cde: 4622 mov r2, r4 8001ce0: 4621 mov r1, r4 8001ce2: 200f movs r0, #15 8001ce4: f7fe fb16 bl 8000314 HAL_NVIC_EnableIRQ(DMA1_Channel5_IRQn); 8001ce8: 200f movs r0, #15 8001cea: f7fe fb47 bl 800037c HAL_NVIC_SetPriority(USART1_IRQn, 0, 0); 8001cee: 4622 mov r2, r4 8001cf0: 4621 mov r1, r4 8001cf2: 2025 movs r0, #37 ; 0x25 8001cf4: f7fe fb0e bl 8000314 HAL_NVIC_EnableIRQ(USART1_IRQn); 8001cf8: 2025 movs r0, #37 ; 0x25 8001cfa: f7fe fb3f bl 800037c HAL_NVIC_SetPriority(TIM6_IRQn, 0, 0); 8001cfe: 4622 mov r2, r4 8001d00: 4621 mov r1, r4 8001d02: 2036 movs r0, #54 ; 0x36 8001d04: f7fe fb06 bl 8000314 HAL_NVIC_EnableIRQ(TIM6_IRQn); 8001d08: 2036 movs r0, #54 ; 0x36 8001d0a: f7fe fb37 bl 800037c HAL_TIM_Base_Start_IT(&htim6); 8001d0e: 4628 mov r0, r5 8001d10: f7ff f9d4 bl 80010bc setbuf(stdout, NULL); 8001d14: 4b1e ldr r3, [pc, #120] ; (8001d90 ) 8001d16: 4621 mov r1, r4 8001d18: 681b ldr r3, [r3, #0] if(LedTimerCnt > 500){HAL_GPIO_TogglePin(BOOT_LED_GPIO_Port,GPIO_PIN_14);LedTimerCnt = 0;} 8001d1a: 4e18 ldr r6, [pc, #96] ; (8001d7c ) setbuf(stdout, NULL); 8001d1c: 6898 ldr r0, [r3, #8] 8001d1e: f000 fa8b bl 8002238 Firmware_BootStart_Signal(); 8001d22: f7ff fddf bl 80018e4 InitUartQueue(&TerminalQueue); 8001d26: 481b ldr r0, [pc, #108] ; (8001d94 ) 8001d28: f000 f93c bl 8001fa4 while (TerminalQueue.data > 0 && UartTimerCnt > 100) GetDataFromUartQueue(&hTerminal); 8001d2c: 4d1a ldr r5, [pc, #104] ; (8001d98 ) if(LedTimerCnt > 500){HAL_GPIO_TogglePin(BOOT_LED_GPIO_Port,GPIO_PIN_14);LedTimerCnt = 0;} 8001d2e: 4c1b ldr r4, [pc, #108] ; (8001d9c ) 8001d30: 6823 ldr r3, [r4, #0] 8001d32: f5b3 7ffa cmp.w r3, #500 ; 0x1f4 8001d36: d906 bls.n 8001d46 8001d38: f44f 4180 mov.w r1, #16384 ; 0x4000 8001d3c: 4630 mov r0, r6 8001d3e: f7fe ff1e bl 8000b7e 8001d42: 2300 movs r3, #0 8001d44: 6023 str r3, [r4, #0] while (TerminalQueue.data > 0 && UartTimerCnt > 100) GetDataFromUartQueue(&hTerminal); 8001d46: 4c13 ldr r4, [pc, #76] ; (8001d94 ) 8001d48: 4f0d ldr r7, [pc, #52] ; (8001d80 ) 8001d4a: 68a3 ldr r3, [r4, #8] 8001d4c: 2b00 cmp r3, #0 8001d4e: dd02 ble.n 8001d56 8001d50: 682b ldr r3, [r5, #0] 8001d52: 2b64 cmp r3, #100 ; 0x64 8001d54: d803 bhi.n 8001d5e while(FirmwareTimerCnt > 3000) Jump_App(); 8001d56: 4f12 ldr r7, [pc, #72] ; (8001da0 ) 8001d58: f640 34b8 movw r4, #3000 ; 0xbb8 8001d5c: e005 b.n 8001d6a while (TerminalQueue.data > 0 && UartTimerCnt > 100) GetDataFromUartQueue(&hTerminal); 8001d5e: 4638 mov r0, r7 8001d60: f000 f92e bl 8001fc0 8001d64: e7f1 b.n 8001d4a while(FirmwareTimerCnt > 3000) Jump_App(); 8001d66: f7ff fe67 bl 8001a38 8001d6a: 683b ldr r3, [r7, #0] 8001d6c: 42a3 cmp r3, r4 8001d6e: d8fa bhi.n 8001d66 8001d70: e7dd b.n 8001d2e 8001d72: bf00 nop 8001d74: 40021000 .word 0x40021000 8001d78: 40010800 .word 0x40010800 8001d7c: 40012000 .word 0x40012000 8001d80: 2000053c .word 0x2000053c 8001d84: 40013800 .word 0x40013800 8001d88: 2000057c .word 0x2000057c 8001d8c: 40001000 .word 0x40001000 8001d90: 20000010 .word 0x20000010 8001d94: 200005bc .word 0x200005bc 8001d98: 200000b4 .word 0x200000b4 8001d9c: 200000b0 .word 0x200000b0 8001da0: 200000ac .word 0x200000ac 08001da4 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8001da4: 4770 bx lr ... 08001da8 : { /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_AFIO_CLK_ENABLE(); 8001da8: 4b0e ldr r3, [pc, #56] ; (8001de4 ) { 8001daa: b082 sub sp, #8 __HAL_RCC_AFIO_CLK_ENABLE(); 8001dac: 699a ldr r2, [r3, #24] 8001dae: f042 0201 orr.w r2, r2, #1 8001db2: 619a str r2, [r3, #24] 8001db4: 699a ldr r2, [r3, #24] 8001db6: f002 0201 and.w r2, r2, #1 8001dba: 9200 str r2, [sp, #0] 8001dbc: 9a00 ldr r2, [sp, #0] __HAL_RCC_PWR_CLK_ENABLE(); 8001dbe: 69da ldr r2, [r3, #28] 8001dc0: f042 5280 orr.w r2, r2, #268435456 ; 0x10000000 8001dc4: 61da str r2, [r3, #28] 8001dc6: 69db ldr r3, [r3, #28] /* System interrupt init*/ /** DISABLE: JTAG-DP Disabled and SW-DP Disabled */ __HAL_AFIO_REMAP_SWJ_DISABLE(); 8001dc8: 4a07 ldr r2, [pc, #28] ; (8001de8 ) __HAL_RCC_PWR_CLK_ENABLE(); 8001dca: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8001dce: 9301 str r3, [sp, #4] 8001dd0: 9b01 ldr r3, [sp, #4] __HAL_AFIO_REMAP_SWJ_DISABLE(); 8001dd2: 6853 ldr r3, [r2, #4] 8001dd4: f023 63e0 bic.w r3, r3, #117440512 ; 0x7000000 8001dd8: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000 8001ddc: 6053 str r3, [r2, #4] /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8001dde: b002 add sp, #8 8001de0: 4770 bx lr 8001de2: bf00 nop 8001de4: 40021000 .word 0x40021000 8001de8: 40010000 .word 0x40010000 08001dec : * @param htim_base: TIM_Base handle pointer * @retval None */ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) { if(htim_base->Instance==TIM6) 8001dec: 6802 ldr r2, [r0, #0] 8001dee: 4b08 ldr r3, [pc, #32] ; (8001e10 ) { 8001df0: b082 sub sp, #8 if(htim_base->Instance==TIM6) 8001df2: 429a cmp r2, r3 8001df4: d10a bne.n 8001e0c { /* USER CODE BEGIN TIM6_MspInit 0 */ /* USER CODE END TIM6_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM6_CLK_ENABLE(); 8001df6: f503 3300 add.w r3, r3, #131072 ; 0x20000 8001dfa: 69da ldr r2, [r3, #28] 8001dfc: f042 0210 orr.w r2, r2, #16 8001e00: 61da str r2, [r3, #28] 8001e02: 69db ldr r3, [r3, #28] 8001e04: f003 0310 and.w r3, r3, #16 8001e08: 9301 str r3, [sp, #4] 8001e0a: 9b01 ldr r3, [sp, #4] /* USER CODE BEGIN TIM6_MspInit 1 */ /* USER CODE END TIM6_MspInit 1 */ } } 8001e0c: b002 add sp, #8 8001e0e: 4770 bx lr 8001e10: 40001000 .word 0x40001000 08001e14 : * This function configures the hardware resources used in this example * @param huart: UART handle pointer * @retval None */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { 8001e14: b570 push {r4, r5, r6, lr} 8001e16: 4606 mov r6, r0 8001e18: b086 sub sp, #24 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001e1a: 2210 movs r2, #16 8001e1c: 2100 movs r1, #0 8001e1e: a802 add r0, sp, #8 8001e20: f000 f986 bl 8002130 if(huart->Instance==USART1) 8001e24: 6832 ldr r2, [r6, #0] 8001e26: 4b20 ldr r3, [pc, #128] ; (8001ea8 ) 8001e28: 429a cmp r2, r3 8001e2a: d13b bne.n 8001ea4 { /* USER CODE BEGIN USART1_MspInit 0 */ /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); 8001e2c: f503 4358 add.w r3, r3, #55296 ; 0xd800 8001e30: 699a ldr r2, [r3, #24] PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_9; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001e32: a902 add r1, sp, #8 __HAL_RCC_USART1_CLK_ENABLE(); 8001e34: f442 4280 orr.w r2, r2, #16384 ; 0x4000 8001e38: 619a str r2, [r3, #24] 8001e3a: 699a ldr r2, [r3, #24] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001e3c: 481b ldr r0, [pc, #108] ; (8001eac ) __HAL_RCC_USART1_CLK_ENABLE(); 8001e3e: f402 4280 and.w r2, r2, #16384 ; 0x4000 8001e42: 9200 str r2, [sp, #0] 8001e44: 9a00 ldr r2, [sp, #0] __HAL_RCC_GPIOA_CLK_ENABLE(); 8001e46: 699a ldr r2, [r3, #24] GPIO_InitStruct.Pin = GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8001e48: 2500 movs r5, #0 __HAL_RCC_GPIOA_CLK_ENABLE(); 8001e4a: f042 0204 orr.w r2, r2, #4 8001e4e: 619a str r2, [r3, #24] 8001e50: 699b ldr r3, [r3, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); /* USART1 DMA Init */ /* USART1_RX Init */ hdma_usart1_rx.Instance = DMA1_Channel5; 8001e52: 4c17 ldr r4, [pc, #92] ; (8001eb0 ) __HAL_RCC_GPIOA_CLK_ENABLE(); 8001e54: f003 0304 and.w r3, r3, #4 8001e58: 9301 str r3, [sp, #4] 8001e5a: 9b01 ldr r3, [sp, #4] GPIO_InitStruct.Pin = GPIO_PIN_9; 8001e5c: f44f 7300 mov.w r3, #512 ; 0x200 8001e60: 9302 str r3, [sp, #8] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001e62: 2302 movs r3, #2 8001e64: 9303 str r3, [sp, #12] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8001e66: 2303 movs r3, #3 8001e68: 9305 str r3, [sp, #20] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001e6a: f7fe fd97 bl 800099c GPIO_InitStruct.Pin = GPIO_PIN_10; 8001e6e: f44f 6380 mov.w r3, #1024 ; 0x400 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001e72: 480e ldr r0, [pc, #56] ; (8001eac ) 8001e74: a902 add r1, sp, #8 GPIO_InitStruct.Pin = GPIO_PIN_10; 8001e76: 9302 str r3, [sp, #8] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8001e78: 9503 str r5, [sp, #12] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001e7a: 9504 str r5, [sp, #16] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001e7c: f7fe fd8e bl 800099c hdma_usart1_rx.Instance = DMA1_Channel5; 8001e80: 4b0c ldr r3, [pc, #48] ; (8001eb4 ) hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE; hdma_usart1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; hdma_usart1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; hdma_usart1_rx.Init.Mode = DMA_NORMAL; hdma_usart1_rx.Init.Priority = DMA_PRIORITY_LOW; if (HAL_DMA_Init(&hdma_usart1_rx) != HAL_OK) 8001e82: 4620 mov r0, r4 hdma_usart1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 8001e84: e884 0028 stmia.w r4, {r3, r5} hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE; 8001e88: 2380 movs r3, #128 ; 0x80 hdma_usart1_rx.Init.PeriphInc = DMA_PINC_DISABLE; 8001e8a: 60a5 str r5, [r4, #8] hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE; 8001e8c: 60e3 str r3, [r4, #12] hdma_usart1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8001e8e: 6125 str r5, [r4, #16] hdma_usart1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8001e90: 6165 str r5, [r4, #20] hdma_usart1_rx.Init.Mode = DMA_NORMAL; 8001e92: 61a5 str r5, [r4, #24] hdma_usart1_rx.Init.Priority = DMA_PRIORITY_LOW; 8001e94: 61e5 str r5, [r4, #28] if (HAL_DMA_Init(&hdma_usart1_rx) != HAL_OK) 8001e96: f7fe fa93 bl 80003c0 8001e9a: b108 cbz r0, 8001ea0 { Error_Handler(); 8001e9c: f7ff ff82 bl 8001da4 } __HAL_LINKDMA(huart,hdmarx,hdma_usart1_rx); 8001ea0: 6374 str r4, [r6, #52] ; 0x34 8001ea2: 6266 str r6, [r4, #36] ; 0x24 /* USER CODE BEGIN USART1_MspInit 1 */ /* USER CODE END USART1_MspInit 1 */ } } 8001ea4: b006 add sp, #24 8001ea6: bd70 pop {r4, r5, r6, pc} 8001ea8: 40013800 .word 0x40013800 8001eac: 40010800 .word 0x40010800 8001eb0: 200004f8 .word 0x200004f8 8001eb4: 40020058 .word 0x40020058 08001eb8 : 8001eb8: 4770 bx lr 08001eba : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8001eba: e7fe b.n 8001eba 08001ebc : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8001ebc: e7fe b.n 8001ebc 08001ebe : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { 8001ebe: e7fe b.n 8001ebe 08001ec0 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8001ec0: e7fe b.n 8001ec0 08001ec2 : 8001ec2: 4770 bx lr 08001ec4 : 8001ec4: 4770 bx lr 08001ec6 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8001ec6: 4770 bx lr 08001ec8 : void SysTick_Handler(void) { /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 8001ec8: f7fe b9ee b.w 80002a8 08001ecc : void DMA1_Channel5_IRQHandler(void) { /* USER CODE BEGIN DMA1_Channel5_IRQn 0 */ /* USER CODE END DMA1_Channel5_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart1_rx); 8001ecc: 4801 ldr r0, [pc, #4] ; (8001ed4 ) 8001ece: f7fe bb63 b.w 8000598 8001ed2: bf00 nop 8001ed4: 200004f8 .word 0x200004f8 08001ed8 : void USART1_IRQHandler(void) { /* USER CODE BEGIN USART1_IRQn 0 */ /* USER CODE END USART1_IRQn 0 */ HAL_UART_IRQHandler(&huart1); 8001ed8: 4801 ldr r0, [pc, #4] ; (8001ee0 ) 8001eda: f7ff bc5b b.w 8001794 8001ede: bf00 nop 8001ee0: 2000053c .word 0x2000053c 08001ee4 : void TIM6_IRQHandler(void) { /* USER CODE BEGIN TIM6_IRQn 0 */ /* USER CODE END TIM6_IRQn 0 */ HAL_TIM_IRQHandler(&htim6); 8001ee4: 4801 ldr r0, [pc, #4] ; (8001eec ) 8001ee6: f7ff b8f8 b.w 80010da 8001eea: bf00 nop 8001eec: 2000057c .word 0x2000057c 08001ef0 <_read>: _kill(status, -1); while (1) {} /* Make sure we hang here */ } __attribute__((weak)) int _read(int file, char *ptr, int len) { 8001ef0: b570 push {r4, r5, r6, lr} 8001ef2: 460e mov r6, r1 8001ef4: 4615 mov r5, r2 int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 8001ef6: 460c mov r4, r1 8001ef8: 1ba3 subs r3, r4, r6 8001efa: 429d cmp r5, r3 8001efc: dc01 bgt.n 8001f02 <_read+0x12> { *ptr++ = __io_getchar(); } return len; } 8001efe: 4628 mov r0, r5 8001f00: bd70 pop {r4, r5, r6, pc} *ptr++ = __io_getchar(); 8001f02: f3af 8000 nop.w 8001f06: f804 0b01 strb.w r0, [r4], #1 8001f0a: e7f5 b.n 8001ef8 <_read+0x8> 08001f0c <_sbrk>: } return len; } caddr_t _sbrk(int incr) { 8001f0c: b508 push {r3, lr} extern char end asm("end"); static char *heap_end; char *prev_heap_end; if (heap_end == 0) 8001f0e: 4b0a ldr r3, [pc, #40] ; (8001f38 <_sbrk+0x2c>) { 8001f10: 4602 mov r2, r0 if (heap_end == 0) 8001f12: 6819 ldr r1, [r3, #0] 8001f14: b909 cbnz r1, 8001f1a <_sbrk+0xe> heap_end = &end; 8001f16: 4909 ldr r1, [pc, #36] ; (8001f3c <_sbrk+0x30>) 8001f18: 6019 str r1, [r3, #0] prev_heap_end = heap_end; if (heap_end + incr > stack_ptr) 8001f1a: 4669 mov r1, sp prev_heap_end = heap_end; 8001f1c: 6818 ldr r0, [r3, #0] if (heap_end + incr > stack_ptr) 8001f1e: 4402 add r2, r0 8001f20: 428a cmp r2, r1 8001f22: d906 bls.n 8001f32 <_sbrk+0x26> { // write(1, "Heap and stack collision\n", 25); // abort(); errno = ENOMEM; 8001f24: f000 f8da bl 80020dc <__errno> 8001f28: 230c movs r3, #12 8001f2a: 6003 str r3, [r0, #0] return (caddr_t) -1; 8001f2c: f04f 30ff mov.w r0, #4294967295 8001f30: bd08 pop {r3, pc} } heap_end += incr; 8001f32: 601a str r2, [r3, #0] return (caddr_t) prev_heap_end; } 8001f34: bd08 pop {r3, pc} 8001f36: bf00 nop 8001f38: 200000b8 .word 0x200000b8 8001f3c: 200015d8 .word 0x200015d8 08001f40 <_close>: int _close(int file) { return -1; } 8001f40: f04f 30ff mov.w r0, #4294967295 8001f44: 4770 bx lr 08001f46 <_fstat>: int _fstat(int file, struct stat *st) { st->st_mode = S_IFCHR; 8001f46: f44f 5300 mov.w r3, #8192 ; 0x2000 return 0; } 8001f4a: 2000 movs r0, #0 st->st_mode = S_IFCHR; 8001f4c: 604b str r3, [r1, #4] } 8001f4e: 4770 bx lr 08001f50 <_isatty>: int _isatty(int file) { return 1; } 8001f50: 2001 movs r0, #1 8001f52: 4770 bx lr 08001f54 <_lseek>: int _lseek(int file, int ptr, int dir) { return 0; } 8001f54: 2000 movs r0, #0 8001f56: 4770 bx lr 08001f58 : */ void SystemInit (void) { /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ /* Set HSION bit */ RCC->CR |= 0x00000001U; 8001f58: 4b0f ldr r3, [pc, #60] ; (8001f98 ) 8001f5a: 681a ldr r2, [r3, #0] 8001f5c: f042 0201 orr.w r2, r2, #1 8001f60: 601a str r2, [r3, #0] /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ #if !defined(STM32F105xC) && !defined(STM32F107xC) RCC->CFGR &= 0xF8FF0000U; 8001f62: 6859 ldr r1, [r3, #4] 8001f64: 4a0d ldr r2, [pc, #52] ; (8001f9c ) 8001f66: 400a ands r2, r1 8001f68: 605a str r2, [r3, #4] #else RCC->CFGR &= 0xF0FF0000U; #endif /* STM32F105xC */ /* Reset HSEON, CSSON and PLLON bits */ RCC->CR &= 0xFEF6FFFFU; 8001f6a: 681a ldr r2, [r3, #0] 8001f6c: f022 7284 bic.w r2, r2, #17301504 ; 0x1080000 8001f70: f422 3280 bic.w r2, r2, #65536 ; 0x10000 8001f74: 601a str r2, [r3, #0] /* Reset HSEBYP bit */ RCC->CR &= 0xFFFBFFFFU; 8001f76: 681a ldr r2, [r3, #0] 8001f78: f422 2280 bic.w r2, r2, #262144 ; 0x40000 8001f7c: 601a str r2, [r3, #0] /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ RCC->CFGR &= 0xFF80FFFFU; 8001f7e: 685a ldr r2, [r3, #4] 8001f80: f422 02fe bic.w r2, r2, #8323072 ; 0x7f0000 8001f84: 605a str r2, [r3, #4] /* Reset CFGR2 register */ RCC->CFGR2 = 0x00000000U; #else /* Disable all interrupts and clear pending bits */ RCC->CIR = 0x009F0000U; 8001f86: f44f 021f mov.w r2, #10420224 ; 0x9f0000 8001f8a: 609a str r2, [r3, #8] #endif #ifdef VECT_TAB_SRAM SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #else SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ 8001f8c: f04f 6200 mov.w r2, #134217728 ; 0x8000000 8001f90: 4b03 ldr r3, [pc, #12] ; (8001fa0 ) 8001f92: 609a str r2, [r3, #8] 8001f94: 4770 bx lr 8001f96: bf00 nop 8001f98: 40021000 .word 0x40021000 8001f9c: f8ff0000 .word 0xf8ff0000 8001fa0: e000ed00 .word 0xe000ed00 08001fa4 : UARTQUEUE TerminalQueue; UARTQUEUE WifiQueue; void InitUartQueue(pUARTQUEUE pQueue) { pQueue->data = pQueue->head = pQueue->tail = 0; 8001fa4: 2300 movs r3, #0 if (HAL_UART_Receive_DMA(&hTerminal, TerminalQueue.Buffer, 1) != HAL_OK) 8001fa6: 2201 movs r2, #1 pQueue->data = pQueue->head = pQueue->tail = 0; 8001fa8: 6043 str r3, [r0, #4] 8001faa: 6003 str r3, [r0, #0] 8001fac: 6083 str r3, [r0, #8] if (HAL_UART_Receive_DMA(&hTerminal, TerminalQueue.Buffer, 1) != HAL_OK) 8001fae: 4902 ldr r1, [pc, #8] ; (8001fb8 ) 8001fb0: 4802 ldr r0, [pc, #8] ; (8001fbc ) 8001fb2: f7ff bb1d b.w 80015f0 8001fb6: bf00 nop 8001fb8: 200005c8 .word 0x200005c8 8001fbc: 2000053c .word 0x2000053c 08001fc0 : pQueue->data++; // HAL_UART_Receive_DMA(&hTerminal, pQueue->Buffer + pQueue->head, 10); } void GetDataFromUartQueue(UART_HandleTypeDef *huart) { 8001fc0: b57f push {r0, r1, r2, r3, r4, r5, r6, lr} pUARTQUEUE pQueue = &TerminalQueue; // if (HAL_UART_Transmit(dst, pQueue->Buffer + pQueue->tail, 1, 3000) != HAL_OK) // { // _Error_Handler(__FILE__, __LINE__); // } update_data_buf[cnt++] = *(pQueue->Buffer + pQueue->tail); 8001fc2: 4e17 ldr r6, [pc, #92] ; (8002020 ) 8001fc4: 6834 ldr r4, [r6, #0] 8001fc6: 1c63 adds r3, r4, #1 8001fc8: 6033 str r3, [r6, #0] 8001fca: 4b16 ldr r3, [pc, #88] ; (8002024 ) 8001fcc: 685a ldr r2, [r3, #4] 8001fce: f103 010c add.w r1, r3, #12 8001fd2: 5c55 ldrb r5, [r2, r1] pQueue->tail++; 8001fd4: 3201 adds r2, #1 if (pQueue->tail >= QUEUE_BUFFER_LENGTH) pQueue->tail = 0; 8001fd6: f5b2 6f00 cmp.w r2, #2048 ; 0x800 8001fda: bfa8 it ge 8001fdc: 2200 movge r2, #0 update_data_buf[cnt++] = *(pQueue->Buffer + pQueue->tail); 8001fde: 4912 ldr r1, [pc, #72] ; (8002028 ) if (pQueue->tail >= QUEUE_BUFFER_LENGTH) pQueue->tail = 0; 8001fe0: 605a str r2, [r3, #4] update_data_buf[cnt++] = *(pQueue->Buffer + pQueue->tail); 8001fe2: 550d strb r5, [r1, r4] pQueue->data--; 8001fe4: 689c ldr r4, [r3, #8] 8001fe6: 460d mov r5, r1 8001fe8: 3c01 subs r4, #1 8001fea: 609c str r4, [r3, #8] if(pQueue->data == 0){ 8001fec: b9ac cbnz r4, 800201a HAL_UART_Transmit(dst, &temp_buf[BLUECELL_HEADER00], 11, 3000); 8001fee: f640 33b8 movw r3, #3000 ; 0xbb8 8001ff2: 220b movs r2, #11 8001ff4: a901 add r1, sp, #4 8001ff6: 480d ldr r0, [pc, #52] ; (800202c ) 8001ff8: f7ff fa9e bl 8001538 // for(int i = 0; i < cnt; i++){ // printf("%02x",update_data_buf[i]); // } #endif // PYJ.2019.07.15_END -- cnt = 0; FirmwareUpdateStart(&update_data_buf[0]); 8001ffc: 480a ldr r0, [pc, #40] ; (8002028 ) cnt = 0; 8001ffe: 6034 str r4, [r6, #0] FirmwareUpdateStart(&update_data_buf[0]); 8002000: f7ff fc8a bl 8001918 for(int i = 0; i < 1024; i++) update_data_buf[i] = 0; 8002004: 4623 mov r3, r4 8002006: 552b strb r3, [r5, r4] for(int i = 0; i < 1024; i++) 8002008: 3401 adds r4, #1 800200a: f5b4 6f80 cmp.w r4, #1024 ; 0x400 800200e: d1fa bne.n 8002006 FirmwareTimerCnt = 0; 8002010: 4a07 ldr r2, [pc, #28] ; (8002030 ) HAL_Delay(1); 8002012: 2001 movs r0, #1 FirmwareTimerCnt = 0; 8002014: 6013 str r3, [r2, #0] HAL_Delay(1); 8002016: f7fe f959 bl 80002cc } } 800201a: b004 add sp, #16 800201c: bd70 pop {r4, r5, r6, pc} 800201e: bf00 nop 8002020: 200000bc .word 0x200000bc 8002024: 200005bc .word 0x200005bc 8002028: 200000c0 .word 0x200000c0 800202c: 2000053c .word 0x2000053c 8002030: 200000ac .word 0x200000ac 08002034 : UartTimerCnt = 0; 8002034: 2300 movs r3, #0 { 8002036: b510 push {r4, lr} UartTimerCnt = 0; 8002038: 4a0d ldr r2, [pc, #52] ; (8002070 ) pQueue->head++; 800203a: 4c0e ldr r4, [pc, #56] ; (8002074 ) UartTimerCnt = 0; 800203c: 6013 str r3, [r2, #0] pQueue->head++; 800203e: 6822 ldr r2, [r4, #0] 8002040: 3201 adds r2, #1 8002042: f5b2 6f00 cmp.w r2, #2048 ; 0x800 8002046: bfb8 it lt 8002048: 4613 movlt r3, r2 800204a: 6023 str r3, [r4, #0] pQueue->data++; 800204c: 68a3 ldr r3, [r4, #8] 800204e: 3301 adds r3, #1 if (pQueue->data >= QUEUE_BUFFER_LENGTH) 8002050: f5b3 6f00 cmp.w r3, #2048 ; 0x800 pQueue->data++; 8002054: 60a3 str r3, [r4, #8] if (pQueue->data >= QUEUE_BUFFER_LENGTH) 8002056: db01 blt.n 800205c GetDataFromUartQueue(huart); 8002058: f7ff ffb2 bl 8001fc0 HAL_UART_Receive_DMA(&hTerminal, pQueue->Buffer + pQueue->head, 1); 800205c: 6823 ldr r3, [r4, #0] 800205e: 4906 ldr r1, [pc, #24] ; (8002078 ) 8002060: 2201 movs r2, #1 } 8002062: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_UART_Receive_DMA(&hTerminal, pQueue->Buffer + pQueue->head, 1); 8002066: 4419 add r1, r3 8002068: 4804 ldr r0, [pc, #16] ; (800207c ) 800206a: f7ff bac1 b.w 80015f0 800206e: bf00 nop 8002070: 200000b4 .word 0x200000b4 8002074: 200005bc .word 0x200005bc 8002078: 200005c8 .word 0x200005c8 800207c: 2000053c .word 0x2000053c 08002080 : void Uart1_Data_Send(uint8_t* data,uint8_t size){ HAL_UART_Transmit(&huart1, data,size, 10); 8002080: 460a mov r2, r1 8002082: 230a movs r3, #10 8002084: 4601 mov r1, r0 8002086: 4801 ldr r0, [pc, #4] ; (800208c ) 8002088: f7ff ba56 b.w 8001538 800208c: 2000053c .word 0x2000053c 08002090 : .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 8002090: 2100 movs r1, #0 b LoopCopyDataInit 8002092: e003 b.n 800209c 08002094 : CopyDataInit: ldr r3, =_sidata 8002094: 4b0b ldr r3, [pc, #44] ; (80020c4 ) ldr r3, [r3, r1] 8002096: 585b ldr r3, [r3, r1] str r3, [r0, r1] 8002098: 5043 str r3, [r0, r1] adds r1, r1, #4 800209a: 3104 adds r1, #4 0800209c : LoopCopyDataInit: ldr r0, =_sdata 800209c: 480a ldr r0, [pc, #40] ; (80020c8 ) ldr r3, =_edata 800209e: 4b0b ldr r3, [pc, #44] ; (80020cc ) adds r2, r0, r1 80020a0: 1842 adds r2, r0, r1 cmp r2, r3 80020a2: 429a cmp r2, r3 bcc CopyDataInit 80020a4: d3f6 bcc.n 8002094 ldr r2, =_sbss 80020a6: 4a0a ldr r2, [pc, #40] ; (80020d0 ) b LoopFillZerobss 80020a8: e002 b.n 80020b0 080020aa : /* Zero fill the bss segment. */ FillZerobss: movs r3, #0 80020aa: 2300 movs r3, #0 str r3, [r2], #4 80020ac: f842 3b04 str.w r3, [r2], #4 080020b0 : LoopFillZerobss: ldr r3, = _ebss 80020b0: 4b08 ldr r3, [pc, #32] ; (80020d4 ) cmp r2, r3 80020b2: 429a cmp r2, r3 bcc FillZerobss 80020b4: d3f9 bcc.n 80020aa /* Call the clock system intitialization function.*/ bl SystemInit 80020b6: f7ff ff4f bl 8001f58 /* Call static constructors */ bl __libc_init_array 80020ba: f000 f815 bl 80020e8 <__libc_init_array> /* Call the application's entry point.*/ bl main 80020be: f7ff fda1 bl 8001c04
bx lr 80020c2: 4770 bx lr ldr r3, =_sidata 80020c4: 080032d4 .word 0x080032d4 ldr r0, =_sdata 80020c8: 20000000 .word 0x20000000 ldr r3, =_edata 80020cc: 20000074 .word 0x20000074 ldr r2, =_sbss 80020d0: 20000078 .word 0x20000078 ldr r3, = _ebss 80020d4: 200015d8 .word 0x200015d8 080020d8 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 80020d8: e7fe b.n 80020d8 ... 080020dc <__errno>: 80020dc: 4b01 ldr r3, [pc, #4] ; (80020e4 <__errno+0x8>) 80020de: 6818 ldr r0, [r3, #0] 80020e0: 4770 bx lr 80020e2: bf00 nop 80020e4: 20000010 .word 0x20000010 080020e8 <__libc_init_array>: 80020e8: b570 push {r4, r5, r6, lr} 80020ea: 2500 movs r5, #0 80020ec: 4e0c ldr r6, [pc, #48] ; (8002120 <__libc_init_array+0x38>) 80020ee: 4c0d ldr r4, [pc, #52] ; (8002124 <__libc_init_array+0x3c>) 80020f0: 1ba4 subs r4, r4, r6 80020f2: 10a4 asrs r4, r4, #2 80020f4: 42a5 cmp r5, r4 80020f6: d109 bne.n 800210c <__libc_init_array+0x24> 80020f8: f001 f848 bl 800318c <_init> 80020fc: 2500 movs r5, #0 80020fe: 4e0a ldr r6, [pc, #40] ; (8002128 <__libc_init_array+0x40>) 8002100: 4c0a ldr r4, [pc, #40] ; (800212c <__libc_init_array+0x44>) 8002102: 1ba4 subs r4, r4, r6 8002104: 10a4 asrs r4, r4, #2 8002106: 42a5 cmp r5, r4 8002108: d105 bne.n 8002116 <__libc_init_array+0x2e> 800210a: bd70 pop {r4, r5, r6, pc} 800210c: f856 3025 ldr.w r3, [r6, r5, lsl #2] 8002110: 4798 blx r3 8002112: 3501 adds r5, #1 8002114: e7ee b.n 80020f4 <__libc_init_array+0xc> 8002116: f856 3025 ldr.w r3, [r6, r5, lsl #2] 800211a: 4798 blx r3 800211c: 3501 adds r5, #1 800211e: e7f2 b.n 8002106 <__libc_init_array+0x1e> 8002120: 080032cc .word 0x080032cc 8002124: 080032cc .word 0x080032cc 8002128: 080032cc .word 0x080032cc 800212c: 080032d0 .word 0x080032d0 08002130 : 8002130: 4603 mov r3, r0 8002132: 4402 add r2, r0 8002134: 4293 cmp r3, r2 8002136: d100 bne.n 800213a 8002138: 4770 bx lr 800213a: f803 1b01 strb.w r1, [r3], #1 800213e: e7f9 b.n 8002134 08002140 : 8002140: b40f push {r0, r1, r2, r3} 8002142: 4b0a ldr r3, [pc, #40] ; (800216c ) 8002144: b513 push {r0, r1, r4, lr} 8002146: 681c ldr r4, [r3, #0] 8002148: b124 cbz r4, 8002154 800214a: 69a3 ldr r3, [r4, #24] 800214c: b913 cbnz r3, 8002154 800214e: 4620 mov r0, r4 8002150: f000 fada bl 8002708 <__sinit> 8002154: ab05 add r3, sp, #20 8002156: 9a04 ldr r2, [sp, #16] 8002158: 68a1 ldr r1, [r4, #8] 800215a: 4620 mov r0, r4 800215c: 9301 str r3, [sp, #4] 800215e: f000 fc9b bl 8002a98 <_vfiprintf_r> 8002162: b002 add sp, #8 8002164: e8bd 4010 ldmia.w sp!, {r4, lr} 8002168: b004 add sp, #16 800216a: 4770 bx lr 800216c: 20000010 .word 0x20000010 08002170 <_puts_r>: 8002170: b570 push {r4, r5, r6, lr} 8002172: 460e mov r6, r1 8002174: 4605 mov r5, r0 8002176: b118 cbz r0, 8002180 <_puts_r+0x10> 8002178: 6983 ldr r3, [r0, #24] 800217a: b90b cbnz r3, 8002180 <_puts_r+0x10> 800217c: f000 fac4 bl 8002708 <__sinit> 8002180: 69ab ldr r3, [r5, #24] 8002182: 68ac ldr r4, [r5, #8] 8002184: b913 cbnz r3, 800218c <_puts_r+0x1c> 8002186: 4628 mov r0, r5 8002188: f000 fabe bl 8002708 <__sinit> 800218c: 4b23 ldr r3, [pc, #140] ; (800221c <_puts_r+0xac>) 800218e: 429c cmp r4, r3 8002190: d117 bne.n 80021c2 <_puts_r+0x52> 8002192: 686c ldr r4, [r5, #4] 8002194: 89a3 ldrh r3, [r4, #12] 8002196: 071b lsls r3, r3, #28 8002198: d51d bpl.n 80021d6 <_puts_r+0x66> 800219a: 6923 ldr r3, [r4, #16] 800219c: b1db cbz r3, 80021d6 <_puts_r+0x66> 800219e: 3e01 subs r6, #1 80021a0: 68a3 ldr r3, [r4, #8] 80021a2: f816 1f01 ldrb.w r1, [r6, #1]! 80021a6: 3b01 subs r3, #1 80021a8: 60a3 str r3, [r4, #8] 80021aa: b9e9 cbnz r1, 80021e8 <_puts_r+0x78> 80021ac: 2b00 cmp r3, #0 80021ae: da2e bge.n 800220e <_puts_r+0x9e> 80021b0: 4622 mov r2, r4 80021b2: 210a movs r1, #10 80021b4: 4628 mov r0, r5 80021b6: f000 f8f5 bl 80023a4 <__swbuf_r> 80021ba: 3001 adds r0, #1 80021bc: d011 beq.n 80021e2 <_puts_r+0x72> 80021be: 200a movs r0, #10 80021c0: bd70 pop {r4, r5, r6, pc} 80021c2: 4b17 ldr r3, [pc, #92] ; (8002220 <_puts_r+0xb0>) 80021c4: 429c cmp r4, r3 80021c6: d101 bne.n 80021cc <_puts_r+0x5c> 80021c8: 68ac ldr r4, [r5, #8] 80021ca: e7e3 b.n 8002194 <_puts_r+0x24> 80021cc: 4b15 ldr r3, [pc, #84] ; (8002224 <_puts_r+0xb4>) 80021ce: 429c cmp r4, r3 80021d0: bf08 it eq 80021d2: 68ec ldreq r4, [r5, #12] 80021d4: e7de b.n 8002194 <_puts_r+0x24> 80021d6: 4621 mov r1, r4 80021d8: 4628 mov r0, r5 80021da: f000 f935 bl 8002448 <__swsetup_r> 80021de: 2800 cmp r0, #0 80021e0: d0dd beq.n 800219e <_puts_r+0x2e> 80021e2: f04f 30ff mov.w r0, #4294967295 80021e6: bd70 pop {r4, r5, r6, pc} 80021e8: 2b00 cmp r3, #0 80021ea: da04 bge.n 80021f6 <_puts_r+0x86> 80021ec: 69a2 ldr r2, [r4, #24] 80021ee: 4293 cmp r3, r2 80021f0: db06 blt.n 8002200 <_puts_r+0x90> 80021f2: 290a cmp r1, #10 80021f4: d004 beq.n 8002200 <_puts_r+0x90> 80021f6: 6823 ldr r3, [r4, #0] 80021f8: 1c5a adds r2, r3, #1 80021fa: 6022 str r2, [r4, #0] 80021fc: 7019 strb r1, [r3, #0] 80021fe: e7cf b.n 80021a0 <_puts_r+0x30> 8002200: 4622 mov r2, r4 8002202: 4628 mov r0, r5 8002204: f000 f8ce bl 80023a4 <__swbuf_r> 8002208: 3001 adds r0, #1 800220a: d1c9 bne.n 80021a0 <_puts_r+0x30> 800220c: e7e9 b.n 80021e2 <_puts_r+0x72> 800220e: 200a movs r0, #10 8002210: 6823 ldr r3, [r4, #0] 8002212: 1c5a adds r2, r3, #1 8002214: 6022 str r2, [r4, #0] 8002216: 7018 strb r0, [r3, #0] 8002218: bd70 pop {r4, r5, r6, pc} 800221a: bf00 nop 800221c: 08003258 .word 0x08003258 8002220: 08003278 .word 0x08003278 8002224: 08003238 .word 0x08003238 08002228 : 8002228: 4b02 ldr r3, [pc, #8] ; (8002234 ) 800222a: 4601 mov r1, r0 800222c: 6818 ldr r0, [r3, #0] 800222e: f7ff bf9f b.w 8002170 <_puts_r> 8002232: bf00 nop 8002234: 20000010 .word 0x20000010 08002238 : 8002238: 2900 cmp r1, #0 800223a: f44f 6380 mov.w r3, #1024 ; 0x400 800223e: bf0c ite eq 8002240: 2202 moveq r2, #2 8002242: 2200 movne r2, #0 8002244: f000 b800 b.w 8002248 08002248 : 8002248: e92d 43f7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr} 800224c: 461d mov r5, r3 800224e: 4b51 ldr r3, [pc, #324] ; (8002394 ) 8002250: 4604 mov r4, r0 8002252: 681e ldr r6, [r3, #0] 8002254: 460f mov r7, r1 8002256: 4690 mov r8, r2 8002258: b126 cbz r6, 8002264 800225a: 69b3 ldr r3, [r6, #24] 800225c: b913 cbnz r3, 8002264 800225e: 4630 mov r0, r6 8002260: f000 fa52 bl 8002708 <__sinit> 8002264: 4b4c ldr r3, [pc, #304] ; (8002398 ) 8002266: 429c cmp r4, r3 8002268: d152 bne.n 8002310 800226a: 6874 ldr r4, [r6, #4] 800226c: f1b8 0f02 cmp.w r8, #2 8002270: d006 beq.n 8002280 8002272: f1b8 0f01 cmp.w r8, #1 8002276: f200 8089 bhi.w 800238c 800227a: 2d00 cmp r5, #0 800227c: f2c0 8086 blt.w 800238c 8002280: 4621 mov r1, r4 8002282: 4630 mov r0, r6 8002284: f000 f9d6 bl 8002634 <_fflush_r> 8002288: 6b61 ldr r1, [r4, #52] ; 0x34 800228a: b141 cbz r1, 800229e 800228c: f104 0344 add.w r3, r4, #68 ; 0x44 8002290: 4299 cmp r1, r3 8002292: d002 beq.n 800229a 8002294: 4630 mov r0, r6 8002296: f000 fb2d bl 80028f4 <_free_r> 800229a: 2300 movs r3, #0 800229c: 6363 str r3, [r4, #52] ; 0x34 800229e: 2300 movs r3, #0 80022a0: 61a3 str r3, [r4, #24] 80022a2: 6063 str r3, [r4, #4] 80022a4: 89a3 ldrh r3, [r4, #12] 80022a6: 061b lsls r3, r3, #24 80022a8: d503 bpl.n 80022b2 80022aa: 6921 ldr r1, [r4, #16] 80022ac: 4630 mov r0, r6 80022ae: f000 fb21 bl 80028f4 <_free_r> 80022b2: 89a3 ldrh r3, [r4, #12] 80022b4: f1b8 0f02 cmp.w r8, #2 80022b8: f423 634a bic.w r3, r3, #3232 ; 0xca0 80022bc: f023 0303 bic.w r3, r3, #3 80022c0: 81a3 strh r3, [r4, #12] 80022c2: d05d beq.n 8002380 80022c4: ab01 add r3, sp, #4 80022c6: 466a mov r2, sp 80022c8: 4621 mov r1, r4 80022ca: 4630 mov r0, r6 80022cc: f000 faa6 bl 800281c <__swhatbuf_r> 80022d0: 89a3 ldrh r3, [r4, #12] 80022d2: 4318 orrs r0, r3 80022d4: 81a0 strh r0, [r4, #12] 80022d6: bb2d cbnz r5, 8002324 80022d8: 9d00 ldr r5, [sp, #0] 80022da: 4628 mov r0, r5 80022dc: f000 fb02 bl 80028e4 80022e0: 4607 mov r7, r0 80022e2: 2800 cmp r0, #0 80022e4: d14e bne.n 8002384 80022e6: f8dd 9000 ldr.w r9, [sp] 80022ea: 45a9 cmp r9, r5 80022ec: d13c bne.n 8002368 80022ee: f04f 30ff mov.w r0, #4294967295 80022f2: 89a3 ldrh r3, [r4, #12] 80022f4: f043 0302 orr.w r3, r3, #2 80022f8: 81a3 strh r3, [r4, #12] 80022fa: 2300 movs r3, #0 80022fc: 60a3 str r3, [r4, #8] 80022fe: f104 0347 add.w r3, r4, #71 ; 0x47 8002302: 6023 str r3, [r4, #0] 8002304: 6123 str r3, [r4, #16] 8002306: 2301 movs r3, #1 8002308: 6163 str r3, [r4, #20] 800230a: b003 add sp, #12 800230c: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} 8002310: 4b22 ldr r3, [pc, #136] ; (800239c ) 8002312: 429c cmp r4, r3 8002314: d101 bne.n 800231a 8002316: 68b4 ldr r4, [r6, #8] 8002318: e7a8 b.n 800226c 800231a: 4b21 ldr r3, [pc, #132] ; (80023a0 ) 800231c: 429c cmp r4, r3 800231e: bf08 it eq 8002320: 68f4 ldreq r4, [r6, #12] 8002322: e7a3 b.n 800226c 8002324: 2f00 cmp r7, #0 8002326: d0d8 beq.n 80022da 8002328: 69b3 ldr r3, [r6, #24] 800232a: b913 cbnz r3, 8002332 800232c: 4630 mov r0, r6 800232e: f000 f9eb bl 8002708 <__sinit> 8002332: f1b8 0f01 cmp.w r8, #1 8002336: bf08 it eq 8002338: 89a3 ldrheq r3, [r4, #12] 800233a: 6027 str r7, [r4, #0] 800233c: bf04 itt eq 800233e: f043 0301 orreq.w r3, r3, #1 8002342: 81a3 strheq r3, [r4, #12] 8002344: 89a3 ldrh r3, [r4, #12] 8002346: 6127 str r7, [r4, #16] 8002348: f013 0008 ands.w r0, r3, #8 800234c: 6165 str r5, [r4, #20] 800234e: d01b beq.n 8002388 8002350: f013 0001 ands.w r0, r3, #1 8002354: f04f 0300 mov.w r3, #0 8002358: bf1f itttt ne 800235a: 426d negne r5, r5 800235c: 60a3 strne r3, [r4, #8] 800235e: 61a5 strne r5, [r4, #24] 8002360: 4618 movne r0, r3 8002362: bf08 it eq 8002364: 60a5 streq r5, [r4, #8] 8002366: e7d0 b.n 800230a 8002368: 4648 mov r0, r9 800236a: f000 fabb bl 80028e4 800236e: 4607 mov r7, r0 8002370: 2800 cmp r0, #0 8002372: d0bc beq.n 80022ee 8002374: 89a3 ldrh r3, [r4, #12] 8002376: 464d mov r5, r9 8002378: f043 0380 orr.w r3, r3, #128 ; 0x80 800237c: 81a3 strh r3, [r4, #12] 800237e: e7d3 b.n 8002328 8002380: 2000 movs r0, #0 8002382: e7b6 b.n 80022f2 8002384: 46a9 mov r9, r5 8002386: e7f5 b.n 8002374 8002388: 60a0 str r0, [r4, #8] 800238a: e7be b.n 800230a 800238c: f04f 30ff mov.w r0, #4294967295 8002390: e7bb b.n 800230a 8002392: bf00 nop 8002394: 20000010 .word 0x20000010 8002398: 08003258 .word 0x08003258 800239c: 08003278 .word 0x08003278 80023a0: 08003238 .word 0x08003238 080023a4 <__swbuf_r>: 80023a4: b5f8 push {r3, r4, r5, r6, r7, lr} 80023a6: 460e mov r6, r1 80023a8: 4614 mov r4, r2 80023aa: 4605 mov r5, r0 80023ac: b118 cbz r0, 80023b6 <__swbuf_r+0x12> 80023ae: 6983 ldr r3, [r0, #24] 80023b0: b90b cbnz r3, 80023b6 <__swbuf_r+0x12> 80023b2: f000 f9a9 bl 8002708 <__sinit> 80023b6: 4b21 ldr r3, [pc, #132] ; (800243c <__swbuf_r+0x98>) 80023b8: 429c cmp r4, r3 80023ba: d12a bne.n 8002412 <__swbuf_r+0x6e> 80023bc: 686c ldr r4, [r5, #4] 80023be: 69a3 ldr r3, [r4, #24] 80023c0: 60a3 str r3, [r4, #8] 80023c2: 89a3 ldrh r3, [r4, #12] 80023c4: 071a lsls r2, r3, #28 80023c6: d52e bpl.n 8002426 <__swbuf_r+0x82> 80023c8: 6923 ldr r3, [r4, #16] 80023ca: b363 cbz r3, 8002426 <__swbuf_r+0x82> 80023cc: 6923 ldr r3, [r4, #16] 80023ce: 6820 ldr r0, [r4, #0] 80023d0: b2f6 uxtb r6, r6 80023d2: 1ac0 subs r0, r0, r3 80023d4: 6963 ldr r3, [r4, #20] 80023d6: 4637 mov r7, r6 80023d8: 4298 cmp r0, r3 80023da: db04 blt.n 80023e6 <__swbuf_r+0x42> 80023dc: 4621 mov r1, r4 80023de: 4628 mov r0, r5 80023e0: f000 f928 bl 8002634 <_fflush_r> 80023e4: bb28 cbnz r0, 8002432 <__swbuf_r+0x8e> 80023e6: 68a3 ldr r3, [r4, #8] 80023e8: 3001 adds r0, #1 80023ea: 3b01 subs r3, #1 80023ec: 60a3 str r3, [r4, #8] 80023ee: 6823 ldr r3, [r4, #0] 80023f0: 1c5a adds r2, r3, #1 80023f2: 6022 str r2, [r4, #0] 80023f4: 701e strb r6, [r3, #0] 80023f6: 6963 ldr r3, [r4, #20] 80023f8: 4298 cmp r0, r3 80023fa: d004 beq.n 8002406 <__swbuf_r+0x62> 80023fc: 89a3 ldrh r3, [r4, #12] 80023fe: 07db lsls r3, r3, #31 8002400: d519 bpl.n 8002436 <__swbuf_r+0x92> 8002402: 2e0a cmp r6, #10 8002404: d117 bne.n 8002436 <__swbuf_r+0x92> 8002406: 4621 mov r1, r4 8002408: 4628 mov r0, r5 800240a: f000 f913 bl 8002634 <_fflush_r> 800240e: b190 cbz r0, 8002436 <__swbuf_r+0x92> 8002410: e00f b.n 8002432 <__swbuf_r+0x8e> 8002412: 4b0b ldr r3, [pc, #44] ; (8002440 <__swbuf_r+0x9c>) 8002414: 429c cmp r4, r3 8002416: d101 bne.n 800241c <__swbuf_r+0x78> 8002418: 68ac ldr r4, [r5, #8] 800241a: e7d0 b.n 80023be <__swbuf_r+0x1a> 800241c: 4b09 ldr r3, [pc, #36] ; (8002444 <__swbuf_r+0xa0>) 800241e: 429c cmp r4, r3 8002420: bf08 it eq 8002422: 68ec ldreq r4, [r5, #12] 8002424: e7cb b.n 80023be <__swbuf_r+0x1a> 8002426: 4621 mov r1, r4 8002428: 4628 mov r0, r5 800242a: f000 f80d bl 8002448 <__swsetup_r> 800242e: 2800 cmp r0, #0 8002430: d0cc beq.n 80023cc <__swbuf_r+0x28> 8002432: f04f 37ff mov.w r7, #4294967295 8002436: 4638 mov r0, r7 8002438: bdf8 pop {r3, r4, r5, r6, r7, pc} 800243a: bf00 nop 800243c: 08003258 .word 0x08003258 8002440: 08003278 .word 0x08003278 8002444: 08003238 .word 0x08003238 08002448 <__swsetup_r>: 8002448: 4b32 ldr r3, [pc, #200] ; (8002514 <__swsetup_r+0xcc>) 800244a: b570 push {r4, r5, r6, lr} 800244c: 681d ldr r5, [r3, #0] 800244e: 4606 mov r6, r0 8002450: 460c mov r4, r1 8002452: b125 cbz r5, 800245e <__swsetup_r+0x16> 8002454: 69ab ldr r3, [r5, #24] 8002456: b913 cbnz r3, 800245e <__swsetup_r+0x16> 8002458: 4628 mov r0, r5 800245a: f000 f955 bl 8002708 <__sinit> 800245e: 4b2e ldr r3, [pc, #184] ; (8002518 <__swsetup_r+0xd0>) 8002460: 429c cmp r4, r3 8002462: d10f bne.n 8002484 <__swsetup_r+0x3c> 8002464: 686c ldr r4, [r5, #4] 8002466: f9b4 300c ldrsh.w r3, [r4, #12] 800246a: b29a uxth r2, r3 800246c: 0715 lsls r5, r2, #28 800246e: d42c bmi.n 80024ca <__swsetup_r+0x82> 8002470: 06d0 lsls r0, r2, #27 8002472: d411 bmi.n 8002498 <__swsetup_r+0x50> 8002474: 2209 movs r2, #9 8002476: 6032 str r2, [r6, #0] 8002478: f043 0340 orr.w r3, r3, #64 ; 0x40 800247c: 81a3 strh r3, [r4, #12] 800247e: f04f 30ff mov.w r0, #4294967295 8002482: bd70 pop {r4, r5, r6, pc} 8002484: 4b25 ldr r3, [pc, #148] ; (800251c <__swsetup_r+0xd4>) 8002486: 429c cmp r4, r3 8002488: d101 bne.n 800248e <__swsetup_r+0x46> 800248a: 68ac ldr r4, [r5, #8] 800248c: e7eb b.n 8002466 <__swsetup_r+0x1e> 800248e: 4b24 ldr r3, [pc, #144] ; (8002520 <__swsetup_r+0xd8>) 8002490: 429c cmp r4, r3 8002492: bf08 it eq 8002494: 68ec ldreq r4, [r5, #12] 8002496: e7e6 b.n 8002466 <__swsetup_r+0x1e> 8002498: 0751 lsls r1, r2, #29 800249a: d512 bpl.n 80024c2 <__swsetup_r+0x7a> 800249c: 6b61 ldr r1, [r4, #52] ; 0x34 800249e: b141 cbz r1, 80024b2 <__swsetup_r+0x6a> 80024a0: f104 0344 add.w r3, r4, #68 ; 0x44 80024a4: 4299 cmp r1, r3 80024a6: d002 beq.n 80024ae <__swsetup_r+0x66> 80024a8: 4630 mov r0, r6 80024aa: f000 fa23 bl 80028f4 <_free_r> 80024ae: 2300 movs r3, #0 80024b0: 6363 str r3, [r4, #52] ; 0x34 80024b2: 89a3 ldrh r3, [r4, #12] 80024b4: f023 0324 bic.w r3, r3, #36 ; 0x24 80024b8: 81a3 strh r3, [r4, #12] 80024ba: 2300 movs r3, #0 80024bc: 6063 str r3, [r4, #4] 80024be: 6923 ldr r3, [r4, #16] 80024c0: 6023 str r3, [r4, #0] 80024c2: 89a3 ldrh r3, [r4, #12] 80024c4: f043 0308 orr.w r3, r3, #8 80024c8: 81a3 strh r3, [r4, #12] 80024ca: 6923 ldr r3, [r4, #16] 80024cc: b94b cbnz r3, 80024e2 <__swsetup_r+0x9a> 80024ce: 89a3 ldrh r3, [r4, #12] 80024d0: f403 7320 and.w r3, r3, #640 ; 0x280 80024d4: f5b3 7f00 cmp.w r3, #512 ; 0x200 80024d8: d003 beq.n 80024e2 <__swsetup_r+0x9a> 80024da: 4621 mov r1, r4 80024dc: 4630 mov r0, r6 80024de: f000 f9c1 bl 8002864 <__smakebuf_r> 80024e2: 89a2 ldrh r2, [r4, #12] 80024e4: f012 0301 ands.w r3, r2, #1 80024e8: d00c beq.n 8002504 <__swsetup_r+0xbc> 80024ea: 2300 movs r3, #0 80024ec: 60a3 str r3, [r4, #8] 80024ee: 6963 ldr r3, [r4, #20] 80024f0: 425b negs r3, r3 80024f2: 61a3 str r3, [r4, #24] 80024f4: 6923 ldr r3, [r4, #16] 80024f6: b953 cbnz r3, 800250e <__swsetup_r+0xc6> 80024f8: f9b4 300c ldrsh.w r3, [r4, #12] 80024fc: f013 0080 ands.w r0, r3, #128 ; 0x80 8002500: d1ba bne.n 8002478 <__swsetup_r+0x30> 8002502: bd70 pop {r4, r5, r6, pc} 8002504: 0792 lsls r2, r2, #30 8002506: bf58 it pl 8002508: 6963 ldrpl r3, [r4, #20] 800250a: 60a3 str r3, [r4, #8] 800250c: e7f2 b.n 80024f4 <__swsetup_r+0xac> 800250e: 2000 movs r0, #0 8002510: e7f7 b.n 8002502 <__swsetup_r+0xba> 8002512: bf00 nop 8002514: 20000010 .word 0x20000010 8002518: 08003258 .word 0x08003258 800251c: 08003278 .word 0x08003278 8002520: 08003238 .word 0x08003238 08002524 <__sflush_r>: 8002524: 898a ldrh r2, [r1, #12] 8002526: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 800252a: 4605 mov r5, r0 800252c: 0710 lsls r0, r2, #28 800252e: 460c mov r4, r1 8002530: d45a bmi.n 80025e8 <__sflush_r+0xc4> 8002532: 684b ldr r3, [r1, #4] 8002534: 2b00 cmp r3, #0 8002536: dc05 bgt.n 8002544 <__sflush_r+0x20> 8002538: 6c0b ldr r3, [r1, #64] ; 0x40 800253a: 2b00 cmp r3, #0 800253c: dc02 bgt.n 8002544 <__sflush_r+0x20> 800253e: 2000 movs r0, #0 8002540: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8002544: 6ae6 ldr r6, [r4, #44] ; 0x2c 8002546: 2e00 cmp r6, #0 8002548: d0f9 beq.n 800253e <__sflush_r+0x1a> 800254a: 2300 movs r3, #0 800254c: f412 5280 ands.w r2, r2, #4096 ; 0x1000 8002550: 682f ldr r7, [r5, #0] 8002552: 602b str r3, [r5, #0] 8002554: d033 beq.n 80025be <__sflush_r+0x9a> 8002556: 6d60 ldr r0, [r4, #84] ; 0x54 8002558: 89a3 ldrh r3, [r4, #12] 800255a: 075a lsls r2, r3, #29 800255c: d505 bpl.n 800256a <__sflush_r+0x46> 800255e: 6863 ldr r3, [r4, #4] 8002560: 1ac0 subs r0, r0, r3 8002562: 6b63 ldr r3, [r4, #52] ; 0x34 8002564: b10b cbz r3, 800256a <__sflush_r+0x46> 8002566: 6c23 ldr r3, [r4, #64] ; 0x40 8002568: 1ac0 subs r0, r0, r3 800256a: 2300 movs r3, #0 800256c: 4602 mov r2, r0 800256e: 6ae6 ldr r6, [r4, #44] ; 0x2c 8002570: 6a21 ldr r1, [r4, #32] 8002572: 4628 mov r0, r5 8002574: 47b0 blx r6 8002576: 1c43 adds r3, r0, #1 8002578: 89a3 ldrh r3, [r4, #12] 800257a: d106 bne.n 800258a <__sflush_r+0x66> 800257c: 6829 ldr r1, [r5, #0] 800257e: 291d cmp r1, #29 8002580: d84b bhi.n 800261a <__sflush_r+0xf6> 8002582: 4a2b ldr r2, [pc, #172] ; (8002630 <__sflush_r+0x10c>) 8002584: 40ca lsrs r2, r1 8002586: 07d6 lsls r6, r2, #31 8002588: d547 bpl.n 800261a <__sflush_r+0xf6> 800258a: 2200 movs r2, #0 800258c: 6062 str r2, [r4, #4] 800258e: 6922 ldr r2, [r4, #16] 8002590: 04d9 lsls r1, r3, #19 8002592: 6022 str r2, [r4, #0] 8002594: d504 bpl.n 80025a0 <__sflush_r+0x7c> 8002596: 1c42 adds r2, r0, #1 8002598: d101 bne.n 800259e <__sflush_r+0x7a> 800259a: 682b ldr r3, [r5, #0] 800259c: b903 cbnz r3, 80025a0 <__sflush_r+0x7c> 800259e: 6560 str r0, [r4, #84] ; 0x54 80025a0: 6b61 ldr r1, [r4, #52] ; 0x34 80025a2: 602f str r7, [r5, #0] 80025a4: 2900 cmp r1, #0 80025a6: d0ca beq.n 800253e <__sflush_r+0x1a> 80025a8: f104 0344 add.w r3, r4, #68 ; 0x44 80025ac: 4299 cmp r1, r3 80025ae: d002 beq.n 80025b6 <__sflush_r+0x92> 80025b0: 4628 mov r0, r5 80025b2: f000 f99f bl 80028f4 <_free_r> 80025b6: 2000 movs r0, #0 80025b8: 6360 str r0, [r4, #52] ; 0x34 80025ba: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 80025be: 6a21 ldr r1, [r4, #32] 80025c0: 2301 movs r3, #1 80025c2: 4628 mov r0, r5 80025c4: 47b0 blx r6 80025c6: 1c41 adds r1, r0, #1 80025c8: d1c6 bne.n 8002558 <__sflush_r+0x34> 80025ca: 682b ldr r3, [r5, #0] 80025cc: 2b00 cmp r3, #0 80025ce: d0c3 beq.n 8002558 <__sflush_r+0x34> 80025d0: 2b1d cmp r3, #29 80025d2: d001 beq.n 80025d8 <__sflush_r+0xb4> 80025d4: 2b16 cmp r3, #22 80025d6: d101 bne.n 80025dc <__sflush_r+0xb8> 80025d8: 602f str r7, [r5, #0] 80025da: e7b0 b.n 800253e <__sflush_r+0x1a> 80025dc: 89a3 ldrh r3, [r4, #12] 80025de: f043 0340 orr.w r3, r3, #64 ; 0x40 80025e2: 81a3 strh r3, [r4, #12] 80025e4: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 80025e8: 690f ldr r7, [r1, #16] 80025ea: 2f00 cmp r7, #0 80025ec: d0a7 beq.n 800253e <__sflush_r+0x1a> 80025ee: 0793 lsls r3, r2, #30 80025f0: bf18 it ne 80025f2: 2300 movne r3, #0 80025f4: 680e ldr r6, [r1, #0] 80025f6: bf08 it eq 80025f8: 694b ldreq r3, [r1, #20] 80025fa: eba6 0807 sub.w r8, r6, r7 80025fe: 600f str r7, [r1, #0] 8002600: 608b str r3, [r1, #8] 8002602: f1b8 0f00 cmp.w r8, #0 8002606: dd9a ble.n 800253e <__sflush_r+0x1a> 8002608: 4643 mov r3, r8 800260a: 463a mov r2, r7 800260c: 6a21 ldr r1, [r4, #32] 800260e: 4628 mov r0, r5 8002610: 6aa6 ldr r6, [r4, #40] ; 0x28 8002612: 47b0 blx r6 8002614: 2800 cmp r0, #0 8002616: dc07 bgt.n 8002628 <__sflush_r+0x104> 8002618: 89a3 ldrh r3, [r4, #12] 800261a: f043 0340 orr.w r3, r3, #64 ; 0x40 800261e: 81a3 strh r3, [r4, #12] 8002620: f04f 30ff mov.w r0, #4294967295 8002624: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8002628: 4407 add r7, r0 800262a: eba8 0800 sub.w r8, r8, r0 800262e: e7e8 b.n 8002602 <__sflush_r+0xde> 8002630: 20400001 .word 0x20400001 08002634 <_fflush_r>: 8002634: b538 push {r3, r4, r5, lr} 8002636: 690b ldr r3, [r1, #16] 8002638: 4605 mov r5, r0 800263a: 460c mov r4, r1 800263c: b1db cbz r3, 8002676 <_fflush_r+0x42> 800263e: b118 cbz r0, 8002648 <_fflush_r+0x14> 8002640: 6983 ldr r3, [r0, #24] 8002642: b90b cbnz r3, 8002648 <_fflush_r+0x14> 8002644: f000 f860 bl 8002708 <__sinit> 8002648: 4b0c ldr r3, [pc, #48] ; (800267c <_fflush_r+0x48>) 800264a: 429c cmp r4, r3 800264c: d109 bne.n 8002662 <_fflush_r+0x2e> 800264e: 686c ldr r4, [r5, #4] 8002650: f9b4 300c ldrsh.w r3, [r4, #12] 8002654: b17b cbz r3, 8002676 <_fflush_r+0x42> 8002656: 4621 mov r1, r4 8002658: 4628 mov r0, r5 800265a: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 800265e: f7ff bf61 b.w 8002524 <__sflush_r> 8002662: 4b07 ldr r3, [pc, #28] ; (8002680 <_fflush_r+0x4c>) 8002664: 429c cmp r4, r3 8002666: d101 bne.n 800266c <_fflush_r+0x38> 8002668: 68ac ldr r4, [r5, #8] 800266a: e7f1 b.n 8002650 <_fflush_r+0x1c> 800266c: 4b05 ldr r3, [pc, #20] ; (8002684 <_fflush_r+0x50>) 800266e: 429c cmp r4, r3 8002670: bf08 it eq 8002672: 68ec ldreq r4, [r5, #12] 8002674: e7ec b.n 8002650 <_fflush_r+0x1c> 8002676: 2000 movs r0, #0 8002678: bd38 pop {r3, r4, r5, pc} 800267a: bf00 nop 800267c: 08003258 .word 0x08003258 8002680: 08003278 .word 0x08003278 8002684: 08003238 .word 0x08003238 08002688 <_cleanup_r>: 8002688: 4901 ldr r1, [pc, #4] ; (8002690 <_cleanup_r+0x8>) 800268a: f000 b8a9 b.w 80027e0 <_fwalk_reent> 800268e: bf00 nop 8002690: 08002635 .word 0x08002635 08002694 : 8002694: 2300 movs r3, #0 8002696: b510 push {r4, lr} 8002698: 4604 mov r4, r0 800269a: 6003 str r3, [r0, #0] 800269c: 6043 str r3, [r0, #4] 800269e: 6083 str r3, [r0, #8] 80026a0: 8181 strh r1, [r0, #12] 80026a2: 6643 str r3, [r0, #100] ; 0x64 80026a4: 81c2 strh r2, [r0, #14] 80026a6: 6103 str r3, [r0, #16] 80026a8: 6143 str r3, [r0, #20] 80026aa: 6183 str r3, [r0, #24] 80026ac: 4619 mov r1, r3 80026ae: 2208 movs r2, #8 80026b0: 305c adds r0, #92 ; 0x5c 80026b2: f7ff fd3d bl 8002130 80026b6: 4b05 ldr r3, [pc, #20] ; (80026cc ) 80026b8: 6224 str r4, [r4, #32] 80026ba: 6263 str r3, [r4, #36] ; 0x24 80026bc: 4b04 ldr r3, [pc, #16] ; (80026d0 ) 80026be: 62a3 str r3, [r4, #40] ; 0x28 80026c0: 4b04 ldr r3, [pc, #16] ; (80026d4 ) 80026c2: 62e3 str r3, [r4, #44] ; 0x2c 80026c4: 4b04 ldr r3, [pc, #16] ; (80026d8 ) 80026c6: 6323 str r3, [r4, #48] ; 0x30 80026c8: bd10 pop {r4, pc} 80026ca: bf00 nop 80026cc: 08003015 .word 0x08003015 80026d0: 08003037 .word 0x08003037 80026d4: 0800306f .word 0x0800306f 80026d8: 08003093 .word 0x08003093 080026dc <__sfmoreglue>: 80026dc: b570 push {r4, r5, r6, lr} 80026de: 2568 movs r5, #104 ; 0x68 80026e0: 1e4a subs r2, r1, #1 80026e2: 4355 muls r5, r2 80026e4: 460e mov r6, r1 80026e6: f105 0174 add.w r1, r5, #116 ; 0x74 80026ea: f000 f94f bl 800298c <_malloc_r> 80026ee: 4604 mov r4, r0 80026f0: b140 cbz r0, 8002704 <__sfmoreglue+0x28> 80026f2: 2100 movs r1, #0 80026f4: e880 0042 stmia.w r0, {r1, r6} 80026f8: 300c adds r0, #12 80026fa: 60a0 str r0, [r4, #8] 80026fc: f105 0268 add.w r2, r5, #104 ; 0x68 8002700: f7ff fd16 bl 8002130 8002704: 4620 mov r0, r4 8002706: bd70 pop {r4, r5, r6, pc} 08002708 <__sinit>: 8002708: 6983 ldr r3, [r0, #24] 800270a: b510 push {r4, lr} 800270c: 4604 mov r4, r0 800270e: bb33 cbnz r3, 800275e <__sinit+0x56> 8002710: 6483 str r3, [r0, #72] ; 0x48 8002712: 64c3 str r3, [r0, #76] ; 0x4c 8002714: 6503 str r3, [r0, #80] ; 0x50 8002716: 4b12 ldr r3, [pc, #72] ; (8002760 <__sinit+0x58>) 8002718: 4a12 ldr r2, [pc, #72] ; (8002764 <__sinit+0x5c>) 800271a: 681b ldr r3, [r3, #0] 800271c: 6282 str r2, [r0, #40] ; 0x28 800271e: 4298 cmp r0, r3 8002720: bf04 itt eq 8002722: 2301 moveq r3, #1 8002724: 6183 streq r3, [r0, #24] 8002726: f000 f81f bl 8002768 <__sfp> 800272a: 6060 str r0, [r4, #4] 800272c: 4620 mov r0, r4 800272e: f000 f81b bl 8002768 <__sfp> 8002732: 60a0 str r0, [r4, #8] 8002734: 4620 mov r0, r4 8002736: f000 f817 bl 8002768 <__sfp> 800273a: 2200 movs r2, #0 800273c: 60e0 str r0, [r4, #12] 800273e: 2104 movs r1, #4 8002740: 6860 ldr r0, [r4, #4] 8002742: f7ff ffa7 bl 8002694 8002746: 2201 movs r2, #1 8002748: 2109 movs r1, #9 800274a: 68a0 ldr r0, [r4, #8] 800274c: f7ff ffa2 bl 8002694 8002750: 2202 movs r2, #2 8002752: 2112 movs r1, #18 8002754: 68e0 ldr r0, [r4, #12] 8002756: f7ff ff9d bl 8002694 800275a: 2301 movs r3, #1 800275c: 61a3 str r3, [r4, #24] 800275e: bd10 pop {r4, pc} 8002760: 08003234 .word 0x08003234 8002764: 08002689 .word 0x08002689 08002768 <__sfp>: 8002768: b5f8 push {r3, r4, r5, r6, r7, lr} 800276a: 4b1c ldr r3, [pc, #112] ; (80027dc <__sfp+0x74>) 800276c: 4607 mov r7, r0 800276e: 681e ldr r6, [r3, #0] 8002770: 69b3 ldr r3, [r6, #24] 8002772: b913 cbnz r3, 800277a <__sfp+0x12> 8002774: 4630 mov r0, r6 8002776: f7ff ffc7 bl 8002708 <__sinit> 800277a: 3648 adds r6, #72 ; 0x48 800277c: 68b4 ldr r4, [r6, #8] 800277e: 6873 ldr r3, [r6, #4] 8002780: 3b01 subs r3, #1 8002782: d503 bpl.n 800278c <__sfp+0x24> 8002784: 6833 ldr r3, [r6, #0] 8002786: b133 cbz r3, 8002796 <__sfp+0x2e> 8002788: 6836 ldr r6, [r6, #0] 800278a: e7f7 b.n 800277c <__sfp+0x14> 800278c: f9b4 500c ldrsh.w r5, [r4, #12] 8002790: b16d cbz r5, 80027ae <__sfp+0x46> 8002792: 3468 adds r4, #104 ; 0x68 8002794: e7f4 b.n 8002780 <__sfp+0x18> 8002796: 2104 movs r1, #4 8002798: 4638 mov r0, r7 800279a: f7ff ff9f bl 80026dc <__sfmoreglue> 800279e: 6030 str r0, [r6, #0] 80027a0: 2800 cmp r0, #0 80027a2: d1f1 bne.n 8002788 <__sfp+0x20> 80027a4: 230c movs r3, #12 80027a6: 4604 mov r4, r0 80027a8: 603b str r3, [r7, #0] 80027aa: 4620 mov r0, r4 80027ac: bdf8 pop {r3, r4, r5, r6, r7, pc} 80027ae: f64f 73ff movw r3, #65535 ; 0xffff 80027b2: 81e3 strh r3, [r4, #14] 80027b4: 2301 movs r3, #1 80027b6: 6665 str r5, [r4, #100] ; 0x64 80027b8: 81a3 strh r3, [r4, #12] 80027ba: 6025 str r5, [r4, #0] 80027bc: 60a5 str r5, [r4, #8] 80027be: 6065 str r5, [r4, #4] 80027c0: 6125 str r5, [r4, #16] 80027c2: 6165 str r5, [r4, #20] 80027c4: 61a5 str r5, [r4, #24] 80027c6: 2208 movs r2, #8 80027c8: 4629 mov r1, r5 80027ca: f104 005c add.w r0, r4, #92 ; 0x5c 80027ce: f7ff fcaf bl 8002130 80027d2: 6365 str r5, [r4, #52] ; 0x34 80027d4: 63a5 str r5, [r4, #56] ; 0x38 80027d6: 64a5 str r5, [r4, #72] ; 0x48 80027d8: 64e5 str r5, [r4, #76] ; 0x4c 80027da: e7e6 b.n 80027aa <__sfp+0x42> 80027dc: 08003234 .word 0x08003234 080027e0 <_fwalk_reent>: 80027e0: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 80027e4: 4680 mov r8, r0 80027e6: 4689 mov r9, r1 80027e8: 2600 movs r6, #0 80027ea: f100 0448 add.w r4, r0, #72 ; 0x48 80027ee: b914 cbnz r4, 80027f6 <_fwalk_reent+0x16> 80027f0: 4630 mov r0, r6 80027f2: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 80027f6: 68a5 ldr r5, [r4, #8] 80027f8: 6867 ldr r7, [r4, #4] 80027fa: 3f01 subs r7, #1 80027fc: d501 bpl.n 8002802 <_fwalk_reent+0x22> 80027fe: 6824 ldr r4, [r4, #0] 8002800: e7f5 b.n 80027ee <_fwalk_reent+0xe> 8002802: 89ab ldrh r3, [r5, #12] 8002804: 2b01 cmp r3, #1 8002806: d907 bls.n 8002818 <_fwalk_reent+0x38> 8002808: f9b5 300e ldrsh.w r3, [r5, #14] 800280c: 3301 adds r3, #1 800280e: d003 beq.n 8002818 <_fwalk_reent+0x38> 8002810: 4629 mov r1, r5 8002812: 4640 mov r0, r8 8002814: 47c8 blx r9 8002816: 4306 orrs r6, r0 8002818: 3568 adds r5, #104 ; 0x68 800281a: e7ee b.n 80027fa <_fwalk_reent+0x1a> 0800281c <__swhatbuf_r>: 800281c: b570 push {r4, r5, r6, lr} 800281e: 460e mov r6, r1 8002820: f9b1 100e ldrsh.w r1, [r1, #14] 8002824: b090 sub sp, #64 ; 0x40 8002826: 2900 cmp r1, #0 8002828: 4614 mov r4, r2 800282a: 461d mov r5, r3 800282c: da07 bge.n 800283e <__swhatbuf_r+0x22> 800282e: 2300 movs r3, #0 8002830: 602b str r3, [r5, #0] 8002832: 89b3 ldrh r3, [r6, #12] 8002834: 061a lsls r2, r3, #24 8002836: d410 bmi.n 800285a <__swhatbuf_r+0x3e> 8002838: f44f 6380 mov.w r3, #1024 ; 0x400 800283c: e00e b.n 800285c <__swhatbuf_r+0x40> 800283e: aa01 add r2, sp, #4 8002840: f000 fc4e bl 80030e0 <_fstat_r> 8002844: 2800 cmp r0, #0 8002846: dbf2 blt.n 800282e <__swhatbuf_r+0x12> 8002848: 9a02 ldr r2, [sp, #8] 800284a: f402 4270 and.w r2, r2, #61440 ; 0xf000 800284e: f5a2 5300 sub.w r3, r2, #8192 ; 0x2000 8002852: 425a negs r2, r3 8002854: 415a adcs r2, r3 8002856: 602a str r2, [r5, #0] 8002858: e7ee b.n 8002838 <__swhatbuf_r+0x1c> 800285a: 2340 movs r3, #64 ; 0x40 800285c: 2000 movs r0, #0 800285e: 6023 str r3, [r4, #0] 8002860: b010 add sp, #64 ; 0x40 8002862: bd70 pop {r4, r5, r6, pc} 08002864 <__smakebuf_r>: 8002864: 898b ldrh r3, [r1, #12] 8002866: b573 push {r0, r1, r4, r5, r6, lr} 8002868: 079d lsls r5, r3, #30 800286a: 4606 mov r6, r0 800286c: 460c mov r4, r1 800286e: d507 bpl.n 8002880 <__smakebuf_r+0x1c> 8002870: f104 0347 add.w r3, r4, #71 ; 0x47 8002874: 6023 str r3, [r4, #0] 8002876: 6123 str r3, [r4, #16] 8002878: 2301 movs r3, #1 800287a: 6163 str r3, [r4, #20] 800287c: b002 add sp, #8 800287e: bd70 pop {r4, r5, r6, pc} 8002880: ab01 add r3, sp, #4 8002882: 466a mov r2, sp 8002884: f7ff ffca bl 800281c <__swhatbuf_r> 8002888: 9900 ldr r1, [sp, #0] 800288a: 4605 mov r5, r0 800288c: 4630 mov r0, r6 800288e: f000 f87d bl 800298c <_malloc_r> 8002892: b948 cbnz r0, 80028a8 <__smakebuf_r+0x44> 8002894: f9b4 300c ldrsh.w r3, [r4, #12] 8002898: 059a lsls r2, r3, #22 800289a: d4ef bmi.n 800287c <__smakebuf_r+0x18> 800289c: f023 0303 bic.w r3, r3, #3 80028a0: f043 0302 orr.w r3, r3, #2 80028a4: 81a3 strh r3, [r4, #12] 80028a6: e7e3 b.n 8002870 <__smakebuf_r+0xc> 80028a8: 4b0d ldr r3, [pc, #52] ; (80028e0 <__smakebuf_r+0x7c>) 80028aa: 62b3 str r3, [r6, #40] ; 0x28 80028ac: 89a3 ldrh r3, [r4, #12] 80028ae: 6020 str r0, [r4, #0] 80028b0: f043 0380 orr.w r3, r3, #128 ; 0x80 80028b4: 81a3 strh r3, [r4, #12] 80028b6: 9b00 ldr r3, [sp, #0] 80028b8: 6120 str r0, [r4, #16] 80028ba: 6163 str r3, [r4, #20] 80028bc: 9b01 ldr r3, [sp, #4] 80028be: b15b cbz r3, 80028d8 <__smakebuf_r+0x74> 80028c0: f9b4 100e ldrsh.w r1, [r4, #14] 80028c4: 4630 mov r0, r6 80028c6: f000 fc1d bl 8003104 <_isatty_r> 80028ca: b128 cbz r0, 80028d8 <__smakebuf_r+0x74> 80028cc: 89a3 ldrh r3, [r4, #12] 80028ce: f023 0303 bic.w r3, r3, #3 80028d2: f043 0301 orr.w r3, r3, #1 80028d6: 81a3 strh r3, [r4, #12] 80028d8: 89a3 ldrh r3, [r4, #12] 80028da: 431d orrs r5, r3 80028dc: 81a5 strh r5, [r4, #12] 80028de: e7cd b.n 800287c <__smakebuf_r+0x18> 80028e0: 08002689 .word 0x08002689 080028e4 : 80028e4: 4b02 ldr r3, [pc, #8] ; (80028f0 ) 80028e6: 4601 mov r1, r0 80028e8: 6818 ldr r0, [r3, #0] 80028ea: f000 b84f b.w 800298c <_malloc_r> 80028ee: bf00 nop 80028f0: 20000010 .word 0x20000010 080028f4 <_free_r>: 80028f4: b538 push {r3, r4, r5, lr} 80028f6: 4605 mov r5, r0 80028f8: 2900 cmp r1, #0 80028fa: d043 beq.n 8002984 <_free_r+0x90> 80028fc: f851 3c04 ldr.w r3, [r1, #-4] 8002900: 1f0c subs r4, r1, #4 8002902: 2b00 cmp r3, #0 8002904: bfb8 it lt 8002906: 18e4 addlt r4, r4, r3 8002908: f000 fc2c bl 8003164 <__malloc_lock> 800290c: 4a1e ldr r2, [pc, #120] ; (8002988 <_free_r+0x94>) 800290e: 6813 ldr r3, [r2, #0] 8002910: 4610 mov r0, r2 8002912: b933 cbnz r3, 8002922 <_free_r+0x2e> 8002914: 6063 str r3, [r4, #4] 8002916: 6014 str r4, [r2, #0] 8002918: 4628 mov r0, r5 800291a: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 800291e: f000 bc22 b.w 8003166 <__malloc_unlock> 8002922: 42a3 cmp r3, r4 8002924: d90b bls.n 800293e <_free_r+0x4a> 8002926: 6821 ldr r1, [r4, #0] 8002928: 1862 adds r2, r4, r1 800292a: 4293 cmp r3, r2 800292c: bf01 itttt eq 800292e: 681a ldreq r2, [r3, #0] 8002930: 685b ldreq r3, [r3, #4] 8002932: 1852 addeq r2, r2, r1 8002934: 6022 streq r2, [r4, #0] 8002936: 6063 str r3, [r4, #4] 8002938: 6004 str r4, [r0, #0] 800293a: e7ed b.n 8002918 <_free_r+0x24> 800293c: 4613 mov r3, r2 800293e: 685a ldr r2, [r3, #4] 8002940: b10a cbz r2, 8002946 <_free_r+0x52> 8002942: 42a2 cmp r2, r4 8002944: d9fa bls.n 800293c <_free_r+0x48> 8002946: 6819 ldr r1, [r3, #0] 8002948: 1858 adds r0, r3, r1 800294a: 42a0 cmp r0, r4 800294c: d10b bne.n 8002966 <_free_r+0x72> 800294e: 6820 ldr r0, [r4, #0] 8002950: 4401 add r1, r0 8002952: 1858 adds r0, r3, r1 8002954: 4282 cmp r2, r0 8002956: 6019 str r1, [r3, #0] 8002958: d1de bne.n 8002918 <_free_r+0x24> 800295a: 6810 ldr r0, [r2, #0] 800295c: 6852 ldr r2, [r2, #4] 800295e: 4401 add r1, r0 8002960: 6019 str r1, [r3, #0] 8002962: 605a str r2, [r3, #4] 8002964: e7d8 b.n 8002918 <_free_r+0x24> 8002966: d902 bls.n 800296e <_free_r+0x7a> 8002968: 230c movs r3, #12 800296a: 602b str r3, [r5, #0] 800296c: e7d4 b.n 8002918 <_free_r+0x24> 800296e: 6820 ldr r0, [r4, #0] 8002970: 1821 adds r1, r4, r0 8002972: 428a cmp r2, r1 8002974: bf01 itttt eq 8002976: 6811 ldreq r1, [r2, #0] 8002978: 6852 ldreq r2, [r2, #4] 800297a: 1809 addeq r1, r1, r0 800297c: 6021 streq r1, [r4, #0] 800297e: 6062 str r2, [r4, #4] 8002980: 605c str r4, [r3, #4] 8002982: e7c9 b.n 8002918 <_free_r+0x24> 8002984: bd38 pop {r3, r4, r5, pc} 8002986: bf00 nop 8002988: 200004c0 .word 0x200004c0 0800298c <_malloc_r>: 800298c: b570 push {r4, r5, r6, lr} 800298e: 1ccd adds r5, r1, #3 8002990: f025 0503 bic.w r5, r5, #3 8002994: 3508 adds r5, #8 8002996: 2d0c cmp r5, #12 8002998: bf38 it cc 800299a: 250c movcc r5, #12 800299c: 2d00 cmp r5, #0 800299e: 4606 mov r6, r0 80029a0: db01 blt.n 80029a6 <_malloc_r+0x1a> 80029a2: 42a9 cmp r1, r5 80029a4: d903 bls.n 80029ae <_malloc_r+0x22> 80029a6: 230c movs r3, #12 80029a8: 6033 str r3, [r6, #0] 80029aa: 2000 movs r0, #0 80029ac: bd70 pop {r4, r5, r6, pc} 80029ae: f000 fbd9 bl 8003164 <__malloc_lock> 80029b2: 4a23 ldr r2, [pc, #140] ; (8002a40 <_malloc_r+0xb4>) 80029b4: 6814 ldr r4, [r2, #0] 80029b6: 4621 mov r1, r4 80029b8: b991 cbnz r1, 80029e0 <_malloc_r+0x54> 80029ba: 4c22 ldr r4, [pc, #136] ; (8002a44 <_malloc_r+0xb8>) 80029bc: 6823 ldr r3, [r4, #0] 80029be: b91b cbnz r3, 80029c8 <_malloc_r+0x3c> 80029c0: 4630 mov r0, r6 80029c2: f000 fb17 bl 8002ff4 <_sbrk_r> 80029c6: 6020 str r0, [r4, #0] 80029c8: 4629 mov r1, r5 80029ca: 4630 mov r0, r6 80029cc: f000 fb12 bl 8002ff4 <_sbrk_r> 80029d0: 1c43 adds r3, r0, #1 80029d2: d126 bne.n 8002a22 <_malloc_r+0x96> 80029d4: 230c movs r3, #12 80029d6: 4630 mov r0, r6 80029d8: 6033 str r3, [r6, #0] 80029da: f000 fbc4 bl 8003166 <__malloc_unlock> 80029de: e7e4 b.n 80029aa <_malloc_r+0x1e> 80029e0: 680b ldr r3, [r1, #0] 80029e2: 1b5b subs r3, r3, r5 80029e4: d41a bmi.n 8002a1c <_malloc_r+0x90> 80029e6: 2b0b cmp r3, #11 80029e8: d90f bls.n 8002a0a <_malloc_r+0x7e> 80029ea: 600b str r3, [r1, #0] 80029ec: 18cc adds r4, r1, r3 80029ee: 50cd str r5, [r1, r3] 80029f0: 4630 mov r0, r6 80029f2: f000 fbb8 bl 8003166 <__malloc_unlock> 80029f6: f104 000b add.w r0, r4, #11 80029fa: 1d23 adds r3, r4, #4 80029fc: f020 0007 bic.w r0, r0, #7 8002a00: 1ac3 subs r3, r0, r3 8002a02: d01b beq.n 8002a3c <_malloc_r+0xb0> 8002a04: 425a negs r2, r3 8002a06: 50e2 str r2, [r4, r3] 8002a08: bd70 pop {r4, r5, r6, pc} 8002a0a: 428c cmp r4, r1 8002a0c: bf0b itete eq 8002a0e: 6863 ldreq r3, [r4, #4] 8002a10: 684b ldrne r3, [r1, #4] 8002a12: 6013 streq r3, [r2, #0] 8002a14: 6063 strne r3, [r4, #4] 8002a16: bf18 it ne 8002a18: 460c movne r4, r1 8002a1a: e7e9 b.n 80029f0 <_malloc_r+0x64> 8002a1c: 460c mov r4, r1 8002a1e: 6849 ldr r1, [r1, #4] 8002a20: e7ca b.n 80029b8 <_malloc_r+0x2c> 8002a22: 1cc4 adds r4, r0, #3 8002a24: f024 0403 bic.w r4, r4, #3 8002a28: 42a0 cmp r0, r4 8002a2a: d005 beq.n 8002a38 <_malloc_r+0xac> 8002a2c: 1a21 subs r1, r4, r0 8002a2e: 4630 mov r0, r6 8002a30: f000 fae0 bl 8002ff4 <_sbrk_r> 8002a34: 3001 adds r0, #1 8002a36: d0cd beq.n 80029d4 <_malloc_r+0x48> 8002a38: 6025 str r5, [r4, #0] 8002a3a: e7d9 b.n 80029f0 <_malloc_r+0x64> 8002a3c: bd70 pop {r4, r5, r6, pc} 8002a3e: bf00 nop 8002a40: 200004c0 .word 0x200004c0 8002a44: 200004c4 .word 0x200004c4 08002a48 <__sfputc_r>: 8002a48: 6893 ldr r3, [r2, #8] 8002a4a: b410 push {r4} 8002a4c: 3b01 subs r3, #1 8002a4e: 2b00 cmp r3, #0 8002a50: 6093 str r3, [r2, #8] 8002a52: da08 bge.n 8002a66 <__sfputc_r+0x1e> 8002a54: 6994 ldr r4, [r2, #24] 8002a56: 42a3 cmp r3, r4 8002a58: db02 blt.n 8002a60 <__sfputc_r+0x18> 8002a5a: b2cb uxtb r3, r1 8002a5c: 2b0a cmp r3, #10 8002a5e: d102 bne.n 8002a66 <__sfputc_r+0x1e> 8002a60: bc10 pop {r4} 8002a62: f7ff bc9f b.w 80023a4 <__swbuf_r> 8002a66: 6813 ldr r3, [r2, #0] 8002a68: 1c58 adds r0, r3, #1 8002a6a: 6010 str r0, [r2, #0] 8002a6c: 7019 strb r1, [r3, #0] 8002a6e: b2c8 uxtb r0, r1 8002a70: bc10 pop {r4} 8002a72: 4770 bx lr 08002a74 <__sfputs_r>: 8002a74: b5f8 push {r3, r4, r5, r6, r7, lr} 8002a76: 4606 mov r6, r0 8002a78: 460f mov r7, r1 8002a7a: 4614 mov r4, r2 8002a7c: 18d5 adds r5, r2, r3 8002a7e: 42ac cmp r4, r5 8002a80: d101 bne.n 8002a86 <__sfputs_r+0x12> 8002a82: 2000 movs r0, #0 8002a84: e007 b.n 8002a96 <__sfputs_r+0x22> 8002a86: 463a mov r2, r7 8002a88: f814 1b01 ldrb.w r1, [r4], #1 8002a8c: 4630 mov r0, r6 8002a8e: f7ff ffdb bl 8002a48 <__sfputc_r> 8002a92: 1c43 adds r3, r0, #1 8002a94: d1f3 bne.n 8002a7e <__sfputs_r+0xa> 8002a96: bdf8 pop {r3, r4, r5, r6, r7, pc} 08002a98 <_vfiprintf_r>: 8002a98: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8002a9c: b09d sub sp, #116 ; 0x74 8002a9e: 460c mov r4, r1 8002aa0: 4617 mov r7, r2 8002aa2: 9303 str r3, [sp, #12] 8002aa4: 4606 mov r6, r0 8002aa6: b118 cbz r0, 8002ab0 <_vfiprintf_r+0x18> 8002aa8: 6983 ldr r3, [r0, #24] 8002aaa: b90b cbnz r3, 8002ab0 <_vfiprintf_r+0x18> 8002aac: f7ff fe2c bl 8002708 <__sinit> 8002ab0: 4b7c ldr r3, [pc, #496] ; (8002ca4 <_vfiprintf_r+0x20c>) 8002ab2: 429c cmp r4, r3 8002ab4: d157 bne.n 8002b66 <_vfiprintf_r+0xce> 8002ab6: 6874 ldr r4, [r6, #4] 8002ab8: 89a3 ldrh r3, [r4, #12] 8002aba: 0718 lsls r0, r3, #28 8002abc: d55d bpl.n 8002b7a <_vfiprintf_r+0xe2> 8002abe: 6923 ldr r3, [r4, #16] 8002ac0: 2b00 cmp r3, #0 8002ac2: d05a beq.n 8002b7a <_vfiprintf_r+0xe2> 8002ac4: 2300 movs r3, #0 8002ac6: 9309 str r3, [sp, #36] ; 0x24 8002ac8: 2320 movs r3, #32 8002aca: f88d 3029 strb.w r3, [sp, #41] ; 0x29 8002ace: 2330 movs r3, #48 ; 0x30 8002ad0: f04f 0b01 mov.w fp, #1 8002ad4: f88d 302a strb.w r3, [sp, #42] ; 0x2a 8002ad8: 46b8 mov r8, r7 8002ada: 4645 mov r5, r8 8002adc: f815 3b01 ldrb.w r3, [r5], #1 8002ae0: 2b00 cmp r3, #0 8002ae2: d155 bne.n 8002b90 <_vfiprintf_r+0xf8> 8002ae4: ebb8 0a07 subs.w sl, r8, r7 8002ae8: d00b beq.n 8002b02 <_vfiprintf_r+0x6a> 8002aea: 4653 mov r3, sl 8002aec: 463a mov r2, r7 8002aee: 4621 mov r1, r4 8002af0: 4630 mov r0, r6 8002af2: f7ff ffbf bl 8002a74 <__sfputs_r> 8002af6: 3001 adds r0, #1 8002af8: f000 80c4 beq.w 8002c84 <_vfiprintf_r+0x1ec> 8002afc: 9b09 ldr r3, [sp, #36] ; 0x24 8002afe: 4453 add r3, sl 8002b00: 9309 str r3, [sp, #36] ; 0x24 8002b02: f898 3000 ldrb.w r3, [r8] 8002b06: 2b00 cmp r3, #0 8002b08: f000 80bc beq.w 8002c84 <_vfiprintf_r+0x1ec> 8002b0c: 2300 movs r3, #0 8002b0e: f04f 32ff mov.w r2, #4294967295 8002b12: 9304 str r3, [sp, #16] 8002b14: 9307 str r3, [sp, #28] 8002b16: 9205 str r2, [sp, #20] 8002b18: 9306 str r3, [sp, #24] 8002b1a: f88d 3053 strb.w r3, [sp, #83] ; 0x53 8002b1e: 931a str r3, [sp, #104] ; 0x68 8002b20: 2205 movs r2, #5 8002b22: 7829 ldrb r1, [r5, #0] 8002b24: 4860 ldr r0, [pc, #384] ; (8002ca8 <_vfiprintf_r+0x210>) 8002b26: f000 fb0f bl 8003148 8002b2a: f105 0801 add.w r8, r5, #1 8002b2e: 9b04 ldr r3, [sp, #16] 8002b30: 2800 cmp r0, #0 8002b32: d131 bne.n 8002b98 <_vfiprintf_r+0x100> 8002b34: 06d9 lsls r1, r3, #27 8002b36: bf44 itt mi 8002b38: 2220 movmi r2, #32 8002b3a: f88d 2053 strbmi.w r2, [sp, #83] ; 0x53 8002b3e: 071a lsls r2, r3, #28 8002b40: bf44 itt mi 8002b42: 222b movmi r2, #43 ; 0x2b 8002b44: f88d 2053 strbmi.w r2, [sp, #83] ; 0x53 8002b48: 782a ldrb r2, [r5, #0] 8002b4a: 2a2a cmp r2, #42 ; 0x2a 8002b4c: d02c beq.n 8002ba8 <_vfiprintf_r+0x110> 8002b4e: 2100 movs r1, #0 8002b50: 200a movs r0, #10 8002b52: 9a07 ldr r2, [sp, #28] 8002b54: 46a8 mov r8, r5 8002b56: f898 3000 ldrb.w r3, [r8] 8002b5a: 3501 adds r5, #1 8002b5c: 3b30 subs r3, #48 ; 0x30 8002b5e: 2b09 cmp r3, #9 8002b60: d96d bls.n 8002c3e <_vfiprintf_r+0x1a6> 8002b62: b371 cbz r1, 8002bc2 <_vfiprintf_r+0x12a> 8002b64: e026 b.n 8002bb4 <_vfiprintf_r+0x11c> 8002b66: 4b51 ldr r3, [pc, #324] ; (8002cac <_vfiprintf_r+0x214>) 8002b68: 429c cmp r4, r3 8002b6a: d101 bne.n 8002b70 <_vfiprintf_r+0xd8> 8002b6c: 68b4 ldr r4, [r6, #8] 8002b6e: e7a3 b.n 8002ab8 <_vfiprintf_r+0x20> 8002b70: 4b4f ldr r3, [pc, #316] ; (8002cb0 <_vfiprintf_r+0x218>) 8002b72: 429c cmp r4, r3 8002b74: bf08 it eq 8002b76: 68f4 ldreq r4, [r6, #12] 8002b78: e79e b.n 8002ab8 <_vfiprintf_r+0x20> 8002b7a: 4621 mov r1, r4 8002b7c: 4630 mov r0, r6 8002b7e: f7ff fc63 bl 8002448 <__swsetup_r> 8002b82: 2800 cmp r0, #0 8002b84: d09e beq.n 8002ac4 <_vfiprintf_r+0x2c> 8002b86: f04f 30ff mov.w r0, #4294967295 8002b8a: b01d add sp, #116 ; 0x74 8002b8c: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8002b90: 2b25 cmp r3, #37 ; 0x25 8002b92: d0a7 beq.n 8002ae4 <_vfiprintf_r+0x4c> 8002b94: 46a8 mov r8, r5 8002b96: e7a0 b.n 8002ada <_vfiprintf_r+0x42> 8002b98: 4a43 ldr r2, [pc, #268] ; (8002ca8 <_vfiprintf_r+0x210>) 8002b9a: 4645 mov r5, r8 8002b9c: 1a80 subs r0, r0, r2 8002b9e: fa0b f000 lsl.w r0, fp, r0 8002ba2: 4318 orrs r0, r3 8002ba4: 9004 str r0, [sp, #16] 8002ba6: e7bb b.n 8002b20 <_vfiprintf_r+0x88> 8002ba8: 9a03 ldr r2, [sp, #12] 8002baa: 1d11 adds r1, r2, #4 8002bac: 6812 ldr r2, [r2, #0] 8002bae: 9103 str r1, [sp, #12] 8002bb0: 2a00 cmp r2, #0 8002bb2: db01 blt.n 8002bb8 <_vfiprintf_r+0x120> 8002bb4: 9207 str r2, [sp, #28] 8002bb6: e004 b.n 8002bc2 <_vfiprintf_r+0x12a> 8002bb8: 4252 negs r2, r2 8002bba: f043 0302 orr.w r3, r3, #2 8002bbe: 9207 str r2, [sp, #28] 8002bc0: 9304 str r3, [sp, #16] 8002bc2: f898 3000 ldrb.w r3, [r8] 8002bc6: 2b2e cmp r3, #46 ; 0x2e 8002bc8: d110 bne.n 8002bec <_vfiprintf_r+0x154> 8002bca: f898 3001 ldrb.w r3, [r8, #1] 8002bce: f108 0101 add.w r1, r8, #1 8002bd2: 2b2a cmp r3, #42 ; 0x2a 8002bd4: d137 bne.n 8002c46 <_vfiprintf_r+0x1ae> 8002bd6: 9b03 ldr r3, [sp, #12] 8002bd8: f108 0802 add.w r8, r8, #2 8002bdc: 1d1a adds r2, r3, #4 8002bde: 681b ldr r3, [r3, #0] 8002be0: 9203 str r2, [sp, #12] 8002be2: 2b00 cmp r3, #0 8002be4: bfb8 it lt 8002be6: f04f 33ff movlt.w r3, #4294967295 8002bea: 9305 str r3, [sp, #20] 8002bec: 4d31 ldr r5, [pc, #196] ; (8002cb4 <_vfiprintf_r+0x21c>) 8002bee: 2203 movs r2, #3 8002bf0: f898 1000 ldrb.w r1, [r8] 8002bf4: 4628 mov r0, r5 8002bf6: f000 faa7 bl 8003148 8002bfa: b140 cbz r0, 8002c0e <_vfiprintf_r+0x176> 8002bfc: 2340 movs r3, #64 ; 0x40 8002bfe: 1b40 subs r0, r0, r5 8002c00: fa03 f000 lsl.w r0, r3, r0 8002c04: 9b04 ldr r3, [sp, #16] 8002c06: f108 0801 add.w r8, r8, #1 8002c0a: 4303 orrs r3, r0 8002c0c: 9304 str r3, [sp, #16] 8002c0e: f898 1000 ldrb.w r1, [r8] 8002c12: 2206 movs r2, #6 8002c14: 4828 ldr r0, [pc, #160] ; (8002cb8 <_vfiprintf_r+0x220>) 8002c16: f108 0701 add.w r7, r8, #1 8002c1a: f88d 1028 strb.w r1, [sp, #40] ; 0x28 8002c1e: f000 fa93 bl 8003148 8002c22: 2800 cmp r0, #0 8002c24: d034 beq.n 8002c90 <_vfiprintf_r+0x1f8> 8002c26: 4b25 ldr r3, [pc, #148] ; (8002cbc <_vfiprintf_r+0x224>) 8002c28: bb03 cbnz r3, 8002c6c <_vfiprintf_r+0x1d4> 8002c2a: 9b03 ldr r3, [sp, #12] 8002c2c: 3307 adds r3, #7 8002c2e: f023 0307 bic.w r3, r3, #7 8002c32: 3308 adds r3, #8 8002c34: 9303 str r3, [sp, #12] 8002c36: 9b09 ldr r3, [sp, #36] ; 0x24 8002c38: 444b add r3, r9 8002c3a: 9309 str r3, [sp, #36] ; 0x24 8002c3c: e74c b.n 8002ad8 <_vfiprintf_r+0x40> 8002c3e: fb00 3202 mla r2, r0, r2, r3 8002c42: 2101 movs r1, #1 8002c44: e786 b.n 8002b54 <_vfiprintf_r+0xbc> 8002c46: 2300 movs r3, #0 8002c48: 250a movs r5, #10 8002c4a: 4618 mov r0, r3 8002c4c: 9305 str r3, [sp, #20] 8002c4e: 4688 mov r8, r1 8002c50: f898 2000 ldrb.w r2, [r8] 8002c54: 3101 adds r1, #1 8002c56: 3a30 subs r2, #48 ; 0x30 8002c58: 2a09 cmp r2, #9 8002c5a: d903 bls.n 8002c64 <_vfiprintf_r+0x1cc> 8002c5c: 2b00 cmp r3, #0 8002c5e: d0c5 beq.n 8002bec <_vfiprintf_r+0x154> 8002c60: 9005 str r0, [sp, #20] 8002c62: e7c3 b.n 8002bec <_vfiprintf_r+0x154> 8002c64: fb05 2000 mla r0, r5, r0, r2 8002c68: 2301 movs r3, #1 8002c6a: e7f0 b.n 8002c4e <_vfiprintf_r+0x1b6> 8002c6c: ab03 add r3, sp, #12 8002c6e: 9300 str r3, [sp, #0] 8002c70: 4622 mov r2, r4 8002c72: 4b13 ldr r3, [pc, #76] ; (8002cc0 <_vfiprintf_r+0x228>) 8002c74: a904 add r1, sp, #16 8002c76: 4630 mov r0, r6 8002c78: f3af 8000 nop.w 8002c7c: f1b0 3fff cmp.w r0, #4294967295 8002c80: 4681 mov r9, r0 8002c82: d1d8 bne.n 8002c36 <_vfiprintf_r+0x19e> 8002c84: 89a3 ldrh r3, [r4, #12] 8002c86: 065b lsls r3, r3, #25 8002c88: f53f af7d bmi.w 8002b86 <_vfiprintf_r+0xee> 8002c8c: 9809 ldr r0, [sp, #36] ; 0x24 8002c8e: e77c b.n 8002b8a <_vfiprintf_r+0xf2> 8002c90: ab03 add r3, sp, #12 8002c92: 9300 str r3, [sp, #0] 8002c94: 4622 mov r2, r4 8002c96: 4b0a ldr r3, [pc, #40] ; (8002cc0 <_vfiprintf_r+0x228>) 8002c98: a904 add r1, sp, #16 8002c9a: 4630 mov r0, r6 8002c9c: f000 f88a bl 8002db4 <_printf_i> 8002ca0: e7ec b.n 8002c7c <_vfiprintf_r+0x1e4> 8002ca2: bf00 nop 8002ca4: 08003258 .word 0x08003258 8002ca8: 08003298 .word 0x08003298 8002cac: 08003278 .word 0x08003278 8002cb0: 08003238 .word 0x08003238 8002cb4: 0800329e .word 0x0800329e 8002cb8: 080032a2 .word 0x080032a2 8002cbc: 00000000 .word 0x00000000 8002cc0: 08002a75 .word 0x08002a75 08002cc4 <_printf_common>: 8002cc4: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8002cc8: 4691 mov r9, r2 8002cca: 461f mov r7, r3 8002ccc: 688a ldr r2, [r1, #8] 8002cce: 690b ldr r3, [r1, #16] 8002cd0: 4606 mov r6, r0 8002cd2: 4293 cmp r3, r2 8002cd4: bfb8 it lt 8002cd6: 4613 movlt r3, r2 8002cd8: f8c9 3000 str.w r3, [r9] 8002cdc: f891 2043 ldrb.w r2, [r1, #67] ; 0x43 8002ce0: 460c mov r4, r1 8002ce2: f8dd 8020 ldr.w r8, [sp, #32] 8002ce6: b112 cbz r2, 8002cee <_printf_common+0x2a> 8002ce8: 3301 adds r3, #1 8002cea: f8c9 3000 str.w r3, [r9] 8002cee: 6823 ldr r3, [r4, #0] 8002cf0: 0699 lsls r1, r3, #26 8002cf2: bf42 ittt mi 8002cf4: f8d9 3000 ldrmi.w r3, [r9] 8002cf8: 3302 addmi r3, #2 8002cfa: f8c9 3000 strmi.w r3, [r9] 8002cfe: 6825 ldr r5, [r4, #0] 8002d00: f015 0506 ands.w r5, r5, #6 8002d04: d107 bne.n 8002d16 <_printf_common+0x52> 8002d06: f104 0a19 add.w sl, r4, #25 8002d0a: 68e3 ldr r3, [r4, #12] 8002d0c: f8d9 2000 ldr.w r2, [r9] 8002d10: 1a9b subs r3, r3, r2 8002d12: 429d cmp r5, r3 8002d14: db2a blt.n 8002d6c <_printf_common+0xa8> 8002d16: f894 3043 ldrb.w r3, [r4, #67] ; 0x43 8002d1a: 6822 ldr r2, [r4, #0] 8002d1c: 3300 adds r3, #0 8002d1e: bf18 it ne 8002d20: 2301 movne r3, #1 8002d22: 0692 lsls r2, r2, #26 8002d24: d42f bmi.n 8002d86 <_printf_common+0xc2> 8002d26: f104 0243 add.w r2, r4, #67 ; 0x43 8002d2a: 4639 mov r1, r7 8002d2c: 4630 mov r0, r6 8002d2e: 47c0 blx r8 8002d30: 3001 adds r0, #1 8002d32: d022 beq.n 8002d7a <_printf_common+0xb6> 8002d34: 6823 ldr r3, [r4, #0] 8002d36: 68e5 ldr r5, [r4, #12] 8002d38: f003 0306 and.w r3, r3, #6 8002d3c: 2b04 cmp r3, #4 8002d3e: bf18 it ne 8002d40: 2500 movne r5, #0 8002d42: f8d9 2000 ldr.w r2, [r9] 8002d46: f04f 0900 mov.w r9, #0 8002d4a: bf08 it eq 8002d4c: 1aad subeq r5, r5, r2 8002d4e: 68a3 ldr r3, [r4, #8] 8002d50: 6922 ldr r2, [r4, #16] 8002d52: bf08 it eq 8002d54: ea25 75e5 biceq.w r5, r5, r5, asr #31 8002d58: 4293 cmp r3, r2 8002d5a: bfc4 itt gt 8002d5c: 1a9b subgt r3, r3, r2 8002d5e: 18ed addgt r5, r5, r3 8002d60: 341a adds r4, #26 8002d62: 454d cmp r5, r9 8002d64: d11b bne.n 8002d9e <_printf_common+0xda> 8002d66: 2000 movs r0, #0 8002d68: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8002d6c: 2301 movs r3, #1 8002d6e: 4652 mov r2, sl 8002d70: 4639 mov r1, r7 8002d72: 4630 mov r0, r6 8002d74: 47c0 blx r8 8002d76: 3001 adds r0, #1 8002d78: d103 bne.n 8002d82 <_printf_common+0xbe> 8002d7a: f04f 30ff mov.w r0, #4294967295 8002d7e: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8002d82: 3501 adds r5, #1 8002d84: e7c1 b.n 8002d0a <_printf_common+0x46> 8002d86: 2030 movs r0, #48 ; 0x30 8002d88: 18e1 adds r1, r4, r3 8002d8a: f881 0043 strb.w r0, [r1, #67] ; 0x43 8002d8e: 1c5a adds r2, r3, #1 8002d90: f894 1045 ldrb.w r1, [r4, #69] ; 0x45 8002d94: 4422 add r2, r4 8002d96: 3302 adds r3, #2 8002d98: f882 1043 strb.w r1, [r2, #67] ; 0x43 8002d9c: e7c3 b.n 8002d26 <_printf_common+0x62> 8002d9e: 2301 movs r3, #1 8002da0: 4622 mov r2, r4 8002da2: 4639 mov r1, r7 8002da4: 4630 mov r0, r6 8002da6: 47c0 blx r8 8002da8: 3001 adds r0, #1 8002daa: d0e6 beq.n 8002d7a <_printf_common+0xb6> 8002dac: f109 0901 add.w r9, r9, #1 8002db0: e7d7 b.n 8002d62 <_printf_common+0x9e> ... 08002db4 <_printf_i>: 8002db4: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} 8002db8: 4617 mov r7, r2 8002dba: 7e0a ldrb r2, [r1, #24] 8002dbc: b085 sub sp, #20 8002dbe: 2a6e cmp r2, #110 ; 0x6e 8002dc0: 4698 mov r8, r3 8002dc2: 4606 mov r6, r0 8002dc4: 460c mov r4, r1 8002dc6: 9b0c ldr r3, [sp, #48] ; 0x30 8002dc8: f101 0e43 add.w lr, r1, #67 ; 0x43 8002dcc: f000 80bc beq.w 8002f48 <_printf_i+0x194> 8002dd0: d81a bhi.n 8002e08 <_printf_i+0x54> 8002dd2: 2a63 cmp r2, #99 ; 0x63 8002dd4: d02e beq.n 8002e34 <_printf_i+0x80> 8002dd6: d80a bhi.n 8002dee <_printf_i+0x3a> 8002dd8: 2a00 cmp r2, #0 8002dda: f000 80c8 beq.w 8002f6e <_printf_i+0x1ba> 8002dde: 2a58 cmp r2, #88 ; 0x58 8002de0: f000 808a beq.w 8002ef8 <_printf_i+0x144> 8002de4: f104 0542 add.w r5, r4, #66 ; 0x42 8002de8: f884 2042 strb.w r2, [r4, #66] ; 0x42 8002dec: e02a b.n 8002e44 <_printf_i+0x90> 8002dee: 2a64 cmp r2, #100 ; 0x64 8002df0: d001 beq.n 8002df6 <_printf_i+0x42> 8002df2: 2a69 cmp r2, #105 ; 0x69 8002df4: d1f6 bne.n 8002de4 <_printf_i+0x30> 8002df6: 6821 ldr r1, [r4, #0] 8002df8: 681a ldr r2, [r3, #0] 8002dfa: f011 0f80 tst.w r1, #128 ; 0x80 8002dfe: d023 beq.n 8002e48 <_printf_i+0x94> 8002e00: 1d11 adds r1, r2, #4 8002e02: 6019 str r1, [r3, #0] 8002e04: 6813 ldr r3, [r2, #0] 8002e06: e027 b.n 8002e58 <_printf_i+0xa4> 8002e08: 2a73 cmp r2, #115 ; 0x73 8002e0a: f000 80b4 beq.w 8002f76 <_printf_i+0x1c2> 8002e0e: d808 bhi.n 8002e22 <_printf_i+0x6e> 8002e10: 2a6f cmp r2, #111 ; 0x6f 8002e12: d02a beq.n 8002e6a <_printf_i+0xb6> 8002e14: 2a70 cmp r2, #112 ; 0x70 8002e16: d1e5 bne.n 8002de4 <_printf_i+0x30> 8002e18: 680a ldr r2, [r1, #0] 8002e1a: f042 0220 orr.w r2, r2, #32 8002e1e: 600a str r2, [r1, #0] 8002e20: e003 b.n 8002e2a <_printf_i+0x76> 8002e22: 2a75 cmp r2, #117 ; 0x75 8002e24: d021 beq.n 8002e6a <_printf_i+0xb6> 8002e26: 2a78 cmp r2, #120 ; 0x78 8002e28: d1dc bne.n 8002de4 <_printf_i+0x30> 8002e2a: 2278 movs r2, #120 ; 0x78 8002e2c: 496f ldr r1, [pc, #444] ; (8002fec <_printf_i+0x238>) 8002e2e: f884 2045 strb.w r2, [r4, #69] ; 0x45 8002e32: e064 b.n 8002efe <_printf_i+0x14a> 8002e34: 681a ldr r2, [r3, #0] 8002e36: f101 0542 add.w r5, r1, #66 ; 0x42 8002e3a: 1d11 adds r1, r2, #4 8002e3c: 6019 str r1, [r3, #0] 8002e3e: 6813 ldr r3, [r2, #0] 8002e40: f884 3042 strb.w r3, [r4, #66] ; 0x42 8002e44: 2301 movs r3, #1 8002e46: e0a3 b.n 8002f90 <_printf_i+0x1dc> 8002e48: f011 0f40 tst.w r1, #64 ; 0x40 8002e4c: f102 0104 add.w r1, r2, #4 8002e50: 6019 str r1, [r3, #0] 8002e52: d0d7 beq.n 8002e04 <_printf_i+0x50> 8002e54: f9b2 3000 ldrsh.w r3, [r2] 8002e58: 2b00 cmp r3, #0 8002e5a: da03 bge.n 8002e64 <_printf_i+0xb0> 8002e5c: 222d movs r2, #45 ; 0x2d 8002e5e: 425b negs r3, r3 8002e60: f884 2043 strb.w r2, [r4, #67] ; 0x43 8002e64: 4962 ldr r1, [pc, #392] ; (8002ff0 <_printf_i+0x23c>) 8002e66: 220a movs r2, #10 8002e68: e017 b.n 8002e9a <_printf_i+0xe6> 8002e6a: 6820 ldr r0, [r4, #0] 8002e6c: 6819 ldr r1, [r3, #0] 8002e6e: f010 0f80 tst.w r0, #128 ; 0x80 8002e72: d003 beq.n 8002e7c <_printf_i+0xc8> 8002e74: 1d08 adds r0, r1, #4 8002e76: 6018 str r0, [r3, #0] 8002e78: 680b ldr r3, [r1, #0] 8002e7a: e006 b.n 8002e8a <_printf_i+0xd6> 8002e7c: f010 0f40 tst.w r0, #64 ; 0x40 8002e80: f101 0004 add.w r0, r1, #4 8002e84: 6018 str r0, [r3, #0] 8002e86: d0f7 beq.n 8002e78 <_printf_i+0xc4> 8002e88: 880b ldrh r3, [r1, #0] 8002e8a: 2a6f cmp r2, #111 ; 0x6f 8002e8c: bf14 ite ne 8002e8e: 220a movne r2, #10 8002e90: 2208 moveq r2, #8 8002e92: 4957 ldr r1, [pc, #348] ; (8002ff0 <_printf_i+0x23c>) 8002e94: 2000 movs r0, #0 8002e96: f884 0043 strb.w r0, [r4, #67] ; 0x43 8002e9a: 6865 ldr r5, [r4, #4] 8002e9c: 2d00 cmp r5, #0 8002e9e: 60a5 str r5, [r4, #8] 8002ea0: f2c0 809c blt.w 8002fdc <_printf_i+0x228> 8002ea4: 6820 ldr r0, [r4, #0] 8002ea6: f020 0004 bic.w r0, r0, #4 8002eaa: 6020 str r0, [r4, #0] 8002eac: 2b00 cmp r3, #0 8002eae: d13f bne.n 8002f30 <_printf_i+0x17c> 8002eb0: 2d00 cmp r5, #0 8002eb2: f040 8095 bne.w 8002fe0 <_printf_i+0x22c> 8002eb6: 4675 mov r5, lr 8002eb8: 2a08 cmp r2, #8 8002eba: d10b bne.n 8002ed4 <_printf_i+0x120> 8002ebc: 6823 ldr r3, [r4, #0] 8002ebe: 07da lsls r2, r3, #31 8002ec0: d508 bpl.n 8002ed4 <_printf_i+0x120> 8002ec2: 6923 ldr r3, [r4, #16] 8002ec4: 6862 ldr r2, [r4, #4] 8002ec6: 429a cmp r2, r3 8002ec8: bfde ittt le 8002eca: 2330 movle r3, #48 ; 0x30 8002ecc: f805 3c01 strble.w r3, [r5, #-1] 8002ed0: f105 35ff addle.w r5, r5, #4294967295 8002ed4: ebae 0305 sub.w r3, lr, r5 8002ed8: 6123 str r3, [r4, #16] 8002eda: f8cd 8000 str.w r8, [sp] 8002ede: 463b mov r3, r7 8002ee0: aa03 add r2, sp, #12 8002ee2: 4621 mov r1, r4 8002ee4: 4630 mov r0, r6 8002ee6: f7ff feed bl 8002cc4 <_printf_common> 8002eea: 3001 adds r0, #1 8002eec: d155 bne.n 8002f9a <_printf_i+0x1e6> 8002eee: f04f 30ff mov.w r0, #4294967295 8002ef2: b005 add sp, #20 8002ef4: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} 8002ef8: f881 2045 strb.w r2, [r1, #69] ; 0x45 8002efc: 493c ldr r1, [pc, #240] ; (8002ff0 <_printf_i+0x23c>) 8002efe: 6822 ldr r2, [r4, #0] 8002f00: 6818 ldr r0, [r3, #0] 8002f02: f012 0f80 tst.w r2, #128 ; 0x80 8002f06: f100 0504 add.w r5, r0, #4 8002f0a: 601d str r5, [r3, #0] 8002f0c: d001 beq.n 8002f12 <_printf_i+0x15e> 8002f0e: 6803 ldr r3, [r0, #0] 8002f10: e002 b.n 8002f18 <_printf_i+0x164> 8002f12: 0655 lsls r5, r2, #25 8002f14: d5fb bpl.n 8002f0e <_printf_i+0x15a> 8002f16: 8803 ldrh r3, [r0, #0] 8002f18: 07d0 lsls r0, r2, #31 8002f1a: bf44 itt mi 8002f1c: f042 0220 orrmi.w r2, r2, #32 8002f20: 6022 strmi r2, [r4, #0] 8002f22: b91b cbnz r3, 8002f2c <_printf_i+0x178> 8002f24: 6822 ldr r2, [r4, #0] 8002f26: f022 0220 bic.w r2, r2, #32 8002f2a: 6022 str r2, [r4, #0] 8002f2c: 2210 movs r2, #16 8002f2e: e7b1 b.n 8002e94 <_printf_i+0xe0> 8002f30: 4675 mov r5, lr 8002f32: fbb3 f0f2 udiv r0, r3, r2 8002f36: fb02 3310 mls r3, r2, r0, r3 8002f3a: 5ccb ldrb r3, [r1, r3] 8002f3c: f805 3d01 strb.w r3, [r5, #-1]! 8002f40: 4603 mov r3, r0 8002f42: 2800 cmp r0, #0 8002f44: d1f5 bne.n 8002f32 <_printf_i+0x17e> 8002f46: e7b7 b.n 8002eb8 <_printf_i+0x104> 8002f48: 6808 ldr r0, [r1, #0] 8002f4a: 681a ldr r2, [r3, #0] 8002f4c: f010 0f80 tst.w r0, #128 ; 0x80 8002f50: 6949 ldr r1, [r1, #20] 8002f52: d004 beq.n 8002f5e <_printf_i+0x1aa> 8002f54: 1d10 adds r0, r2, #4 8002f56: 6018 str r0, [r3, #0] 8002f58: 6813 ldr r3, [r2, #0] 8002f5a: 6019 str r1, [r3, #0] 8002f5c: e007 b.n 8002f6e <_printf_i+0x1ba> 8002f5e: f010 0f40 tst.w r0, #64 ; 0x40 8002f62: f102 0004 add.w r0, r2, #4 8002f66: 6018 str r0, [r3, #0] 8002f68: 6813 ldr r3, [r2, #0] 8002f6a: d0f6 beq.n 8002f5a <_printf_i+0x1a6> 8002f6c: 8019 strh r1, [r3, #0] 8002f6e: 2300 movs r3, #0 8002f70: 4675 mov r5, lr 8002f72: 6123 str r3, [r4, #16] 8002f74: e7b1 b.n 8002eda <_printf_i+0x126> 8002f76: 681a ldr r2, [r3, #0] 8002f78: 1d11 adds r1, r2, #4 8002f7a: 6019 str r1, [r3, #0] 8002f7c: 6815 ldr r5, [r2, #0] 8002f7e: 2100 movs r1, #0 8002f80: 6862 ldr r2, [r4, #4] 8002f82: 4628 mov r0, r5 8002f84: f000 f8e0 bl 8003148 8002f88: b108 cbz r0, 8002f8e <_printf_i+0x1da> 8002f8a: 1b40 subs r0, r0, r5 8002f8c: 6060 str r0, [r4, #4] 8002f8e: 6863 ldr r3, [r4, #4] 8002f90: 6123 str r3, [r4, #16] 8002f92: 2300 movs r3, #0 8002f94: f884 3043 strb.w r3, [r4, #67] ; 0x43 8002f98: e79f b.n 8002eda <_printf_i+0x126> 8002f9a: 6923 ldr r3, [r4, #16] 8002f9c: 462a mov r2, r5 8002f9e: 4639 mov r1, r7 8002fa0: 4630 mov r0, r6 8002fa2: 47c0 blx r8 8002fa4: 3001 adds r0, #1 8002fa6: d0a2 beq.n 8002eee <_printf_i+0x13a> 8002fa8: 6823 ldr r3, [r4, #0] 8002faa: 079b lsls r3, r3, #30 8002fac: d507 bpl.n 8002fbe <_printf_i+0x20a> 8002fae: 2500 movs r5, #0 8002fb0: f104 0919 add.w r9, r4, #25 8002fb4: 68e3 ldr r3, [r4, #12] 8002fb6: 9a03 ldr r2, [sp, #12] 8002fb8: 1a9b subs r3, r3, r2 8002fba: 429d cmp r5, r3 8002fbc: db05 blt.n 8002fca <_printf_i+0x216> 8002fbe: 68e0 ldr r0, [r4, #12] 8002fc0: 9b03 ldr r3, [sp, #12] 8002fc2: 4298 cmp r0, r3 8002fc4: bfb8 it lt 8002fc6: 4618 movlt r0, r3 8002fc8: e793 b.n 8002ef2 <_printf_i+0x13e> 8002fca: 2301 movs r3, #1 8002fcc: 464a mov r2, r9 8002fce: 4639 mov r1, r7 8002fd0: 4630 mov r0, r6 8002fd2: 47c0 blx r8 8002fd4: 3001 adds r0, #1 8002fd6: d08a beq.n 8002eee <_printf_i+0x13a> 8002fd8: 3501 adds r5, #1 8002fda: e7eb b.n 8002fb4 <_printf_i+0x200> 8002fdc: 2b00 cmp r3, #0 8002fde: d1a7 bne.n 8002f30 <_printf_i+0x17c> 8002fe0: 780b ldrb r3, [r1, #0] 8002fe2: f104 0542 add.w r5, r4, #66 ; 0x42 8002fe6: f884 3042 strb.w r3, [r4, #66] ; 0x42 8002fea: e765 b.n 8002eb8 <_printf_i+0x104> 8002fec: 080032ba .word 0x080032ba 8002ff0: 080032a9 .word 0x080032a9 08002ff4 <_sbrk_r>: 8002ff4: b538 push {r3, r4, r5, lr} 8002ff6: 2300 movs r3, #0 8002ff8: 4c05 ldr r4, [pc, #20] ; (8003010 <_sbrk_r+0x1c>) 8002ffa: 4605 mov r5, r0 8002ffc: 4608 mov r0, r1 8002ffe: 6023 str r3, [r4, #0] 8003000: f7fe ff84 bl 8001f0c <_sbrk> 8003004: 1c43 adds r3, r0, #1 8003006: d102 bne.n 800300e <_sbrk_r+0x1a> 8003008: 6823 ldr r3, [r4, #0] 800300a: b103 cbz r3, 800300e <_sbrk_r+0x1a> 800300c: 602b str r3, [r5, #0] 800300e: bd38 pop {r3, r4, r5, pc} 8003010: 200015d4 .word 0x200015d4 08003014 <__sread>: 8003014: b510 push {r4, lr} 8003016: 460c mov r4, r1 8003018: f9b1 100e ldrsh.w r1, [r1, #14] 800301c: f000 f8a4 bl 8003168 <_read_r> 8003020: 2800 cmp r0, #0 8003022: bfab itete ge 8003024: 6d63 ldrge r3, [r4, #84] ; 0x54 8003026: 89a3 ldrhlt r3, [r4, #12] 8003028: 181b addge r3, r3, r0 800302a: f423 5380 biclt.w r3, r3, #4096 ; 0x1000 800302e: bfac ite ge 8003030: 6563 strge r3, [r4, #84] ; 0x54 8003032: 81a3 strhlt r3, [r4, #12] 8003034: bd10 pop {r4, pc} 08003036 <__swrite>: 8003036: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 800303a: 461f mov r7, r3 800303c: 898b ldrh r3, [r1, #12] 800303e: 4605 mov r5, r0 8003040: 05db lsls r3, r3, #23 8003042: 460c mov r4, r1 8003044: 4616 mov r6, r2 8003046: d505 bpl.n 8003054 <__swrite+0x1e> 8003048: 2302 movs r3, #2 800304a: 2200 movs r2, #0 800304c: f9b1 100e ldrsh.w r1, [r1, #14] 8003050: f000 f868 bl 8003124 <_lseek_r> 8003054: 89a3 ldrh r3, [r4, #12] 8003056: 4632 mov r2, r6 8003058: f423 5380 bic.w r3, r3, #4096 ; 0x1000 800305c: 81a3 strh r3, [r4, #12] 800305e: f9b4 100e ldrsh.w r1, [r4, #14] 8003062: 463b mov r3, r7 8003064: 4628 mov r0, r5 8003066: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 800306a: f000 b817 b.w 800309c <_write_r> 0800306e <__sseek>: 800306e: b510 push {r4, lr} 8003070: 460c mov r4, r1 8003072: f9b1 100e ldrsh.w r1, [r1, #14] 8003076: f000 f855 bl 8003124 <_lseek_r> 800307a: 1c43 adds r3, r0, #1 800307c: 89a3 ldrh r3, [r4, #12] 800307e: bf15 itete ne 8003080: 6560 strne r0, [r4, #84] ; 0x54 8003082: f423 5380 biceq.w r3, r3, #4096 ; 0x1000 8003086: f443 5380 orrne.w r3, r3, #4096 ; 0x1000 800308a: 81a3 strheq r3, [r4, #12] 800308c: bf18 it ne 800308e: 81a3 strhne r3, [r4, #12] 8003090: bd10 pop {r4, pc} 08003092 <__sclose>: 8003092: f9b1 100e ldrsh.w r1, [r1, #14] 8003096: f000 b813 b.w 80030c0 <_close_r> ... 0800309c <_write_r>: 800309c: b538 push {r3, r4, r5, lr} 800309e: 4605 mov r5, r0 80030a0: 4608 mov r0, r1 80030a2: 4611 mov r1, r2 80030a4: 2200 movs r2, #0 80030a6: 4c05 ldr r4, [pc, #20] ; (80030bc <_write_r+0x20>) 80030a8: 6022 str r2, [r4, #0] 80030aa: 461a mov r2, r3 80030ac: f7fe fd78 bl 8001ba0 <_write> 80030b0: 1c43 adds r3, r0, #1 80030b2: d102 bne.n 80030ba <_write_r+0x1e> 80030b4: 6823 ldr r3, [r4, #0] 80030b6: b103 cbz r3, 80030ba <_write_r+0x1e> 80030b8: 602b str r3, [r5, #0] 80030ba: bd38 pop {r3, r4, r5, pc} 80030bc: 200015d4 .word 0x200015d4 080030c0 <_close_r>: 80030c0: b538 push {r3, r4, r5, lr} 80030c2: 2300 movs r3, #0 80030c4: 4c05 ldr r4, [pc, #20] ; (80030dc <_close_r+0x1c>) 80030c6: 4605 mov r5, r0 80030c8: 4608 mov r0, r1 80030ca: 6023 str r3, [r4, #0] 80030cc: f7fe ff38 bl 8001f40 <_close> 80030d0: 1c43 adds r3, r0, #1 80030d2: d102 bne.n 80030da <_close_r+0x1a> 80030d4: 6823 ldr r3, [r4, #0] 80030d6: b103 cbz r3, 80030da <_close_r+0x1a> 80030d8: 602b str r3, [r5, #0] 80030da: bd38 pop {r3, r4, r5, pc} 80030dc: 200015d4 .word 0x200015d4 080030e0 <_fstat_r>: 80030e0: b538 push {r3, r4, r5, lr} 80030e2: 2300 movs r3, #0 80030e4: 4c06 ldr r4, [pc, #24] ; (8003100 <_fstat_r+0x20>) 80030e6: 4605 mov r5, r0 80030e8: 4608 mov r0, r1 80030ea: 4611 mov r1, r2 80030ec: 6023 str r3, [r4, #0] 80030ee: f7fe ff2a bl 8001f46 <_fstat> 80030f2: 1c43 adds r3, r0, #1 80030f4: d102 bne.n 80030fc <_fstat_r+0x1c> 80030f6: 6823 ldr r3, [r4, #0] 80030f8: b103 cbz r3, 80030fc <_fstat_r+0x1c> 80030fa: 602b str r3, [r5, #0] 80030fc: bd38 pop {r3, r4, r5, pc} 80030fe: bf00 nop 8003100: 200015d4 .word 0x200015d4 08003104 <_isatty_r>: 8003104: b538 push {r3, r4, r5, lr} 8003106: 2300 movs r3, #0 8003108: 4c05 ldr r4, [pc, #20] ; (8003120 <_isatty_r+0x1c>) 800310a: 4605 mov r5, r0 800310c: 4608 mov r0, r1 800310e: 6023 str r3, [r4, #0] 8003110: f7fe ff1e bl 8001f50 <_isatty> 8003114: 1c43 adds r3, r0, #1 8003116: d102 bne.n 800311e <_isatty_r+0x1a> 8003118: 6823 ldr r3, [r4, #0] 800311a: b103 cbz r3, 800311e <_isatty_r+0x1a> 800311c: 602b str r3, [r5, #0] 800311e: bd38 pop {r3, r4, r5, pc} 8003120: 200015d4 .word 0x200015d4 08003124 <_lseek_r>: 8003124: b538 push {r3, r4, r5, lr} 8003126: 4605 mov r5, r0 8003128: 4608 mov r0, r1 800312a: 4611 mov r1, r2 800312c: 2200 movs r2, #0 800312e: 4c05 ldr r4, [pc, #20] ; (8003144 <_lseek_r+0x20>) 8003130: 6022 str r2, [r4, #0] 8003132: 461a mov r2, r3 8003134: f7fe ff0e bl 8001f54 <_lseek> 8003138: 1c43 adds r3, r0, #1 800313a: d102 bne.n 8003142 <_lseek_r+0x1e> 800313c: 6823 ldr r3, [r4, #0] 800313e: b103 cbz r3, 8003142 <_lseek_r+0x1e> 8003140: 602b str r3, [r5, #0] 8003142: bd38 pop {r3, r4, r5, pc} 8003144: 200015d4 .word 0x200015d4 08003148 : 8003148: b510 push {r4, lr} 800314a: b2c9 uxtb r1, r1 800314c: 4402 add r2, r0 800314e: 4290 cmp r0, r2 8003150: 4603 mov r3, r0 8003152: d101 bne.n 8003158 8003154: 2000 movs r0, #0 8003156: bd10 pop {r4, pc} 8003158: 781c ldrb r4, [r3, #0] 800315a: 3001 adds r0, #1 800315c: 428c cmp r4, r1 800315e: d1f6 bne.n 800314e 8003160: 4618 mov r0, r3 8003162: bd10 pop {r4, pc} 08003164 <__malloc_lock>: 8003164: 4770 bx lr 08003166 <__malloc_unlock>: 8003166: 4770 bx lr 08003168 <_read_r>: 8003168: b538 push {r3, r4, r5, lr} 800316a: 4605 mov r5, r0 800316c: 4608 mov r0, r1 800316e: 4611 mov r1, r2 8003170: 2200 movs r2, #0 8003172: 4c05 ldr r4, [pc, #20] ; (8003188 <_read_r+0x20>) 8003174: 6022 str r2, [r4, #0] 8003176: 461a mov r2, r3 8003178: f7fe feba bl 8001ef0 <_read> 800317c: 1c43 adds r3, r0, #1 800317e: d102 bne.n 8003186 <_read_r+0x1e> 8003180: 6823 ldr r3, [r4, #0] 8003182: b103 cbz r3, 8003186 <_read_r+0x1e> 8003184: 602b str r3, [r5, #0] 8003186: bd38 pop {r3, r4, r5, pc} 8003188: 200015d4 .word 0x200015d4 0800318c <_init>: 800318c: b5f8 push {r3, r4, r5, r6, r7, lr} 800318e: bf00 nop 8003190: bcf8 pop {r3, r4, r5, r6, r7} 8003192: bc08 pop {r3} 8003194: 469e mov lr, r3 8003196: 4770 bx lr 08003198 <_fini>: 8003198: b5f8 push {r3, r4, r5, r6, r7, lr} 800319a: bf00 nop 800319c: bcf8 pop {r3, r4, r5, r6, r7} 800319e: bc08 pop {r3} 80031a0: 469e mov lr, r3 80031a2: 4770 bx lr