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3.5G 최초 Power ON 시 LOCK 안잡 히는 문제 수정

PLL ON OFF SAVE 시 HIGH LOW 동작이 서로 뒤바껴있었음
YJ 5 년 전
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30개의 변경된 파일854개의 추가작업 그리고 223개의 파일을 삭제
  1. BIN
      Debug/STM32F103_ATTEN_PLL_Zig.binary
  2. BIN
      Debug/STM32F103_ATTEN_PLL_Zig.elf
  3. 12 12
      Debug/STM32F103_ATTEN_PLL_Zig.hex
  4. 79 73
      Debug/STM32F103_ATTEN_PLL_Zig.list
  5. BIN
      Debug/Src/zig_operate.o
  6. 1 1
      Debug/Src/zig_operate.su
  7. 14 6
      Src/zig_operate.c
  8. 744 0
      insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/zig_operate(2390).c
  9. 4 131
      insight/STM32F103_ATTEN_PLL_Zig.si4project/STM32F103_ATTEN_PLL_Zig.SearchResults
  10. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/STM32F103_ATTEN_PLL_Zig.siwork
  11. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_adc_ex.c.sisc
  12. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_gpio.c.sisc
  13. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_BDA4601.h.sisc
  14. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_PE43711.h.sisc
  15. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_adf4153.h.sisc
  16. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_flash.h.sisc
  17. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_includes.h.sisc
  18. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_main.h.sisc
  19. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_pll_4113.h.sisc
  20. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_zig_operate.h.sisc
  21. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_AD5318.c.sisc
  22. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_BDA4601.c.sisc
  23. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_PE43711.c.sisc
  24. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_adf4153.c.sisc
  25. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_flash.c.sisc
  26. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_includes.c.sisc
  27. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_main.c.sisc
  28. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_pll_4113.c.sisc
  29. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_uart.c.sisc
  30. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_zig_operate.c.sisc

BIN
Debug/STM32F103_ATTEN_PLL_Zig.binary


BIN
Debug/STM32F103_ATTEN_PLL_Zig.elf


+ 12 - 12
Debug/STM32F103_ATTEN_PLL_Zig.hex

@@ -1317,19 +1317,19 @@
1317 1317
 :1092280047308B4206D04720FEF792FD94F847302E
1318 1318
 :1092380085F8473094F8481095F848308B4206D0A6
1319 1319
 :109248004820FEF785FD94F8483085F8483094F8B2
1320
-:109258004B1095F84B308B4243D04B20FEF778FDEE
1320
+:109258004B1095F84B308B4245D04B20FEF778FDEC
1321 1321
 :1092680094F84B30012085F84B30FCF73BF994F823
1322
-:109278004B30002B35D0EB7FAA7F1B0243EA024319
1323
-:1092880095F820200021134341F2883203920222EC
1324
-:10929800029242F21072C4485A43CDE900010023F9
1325
-:1092A80026A8FEF729FB0322059241F2C232049256
1326
-:1092B800269ABE4B0392279ABD4E029203F11002E2
1327
-:1092C80092E803008DE803000FCBFEF7A3FB98227A
1328
-:1092D80006F11001684600F00FFA96E80F00FEF755
1329
-:1092E800B3F994F84C1095F84C308B4245D04C208B
1330
-:1092F800FEF72EFD94F84C30012085F84C30FCF731
1331
-:10930800F1F894F84C30002B37D095F8223095F8C6
1332
-:1093180021201B0243EA024395F82320002113432E
1322
+:109278004B30002B37D095F8223095F821201B026F
1323
+:1092880043EA024395F823200021134341F2883230
1324
+:1092980003920222029242F21072C3485A43CDE965
1325
+:1092A8000001002326A8FEF727FB0322059241F2BE
1326
+:1092B800C2320492269ABD4B0392279ABC4E029260
1327
+:1092C80003F1100292E803008DE803000FCBFEF7CC
1328
+:1092D800A1FB982206F11001684600F00DFA96E805
1329
+:1092E8000F00FEF7B1F994F84C1095F84C308B420A
1330
+:1092F80043D04C20FEF72CFD94F84C30012085F823
1331
+:109308004C30FCF7EFF894F84C30002B35D0EB7F5D
1332
+:10931800AA7F1B0243EA024395F820200021134349
1333 1333
 :1093280041F2883203920222029242F210729E485F
1334 1334
 :109338005A43CDE90001002326A8FEF7DDFA0322EF
1335 1335
 :10934800059241F2C2320492269A9A4B0392279AC6

+ 79 - 73
Debug/STM32F103_ATTEN_PLL_Zig.list

@@ -12011,7 +12011,7 @@ void RF_Operate(uint8_t* data_buf){
12011 12011
  8009256:	f894 104b 	ldrb.w	r1, [r4, #75]	; 0x4b
12012 12012
  800925a:	f895 304b 	ldrb.w	r3, [r5, #75]	; 0x4b
12013 12013
  800925e:	428b      	cmp	r3, r1
12014
- 8009260:	d043      	beq.n	80092ea <RF_Operate+0x75e>
12014
+ 8009260:	d045      	beq.n	80092ee <RF_Operate+0x762>
12015 12015
         Power_ON_OFF_Ctrl(INDEX_PLL_ON_OFF_3_5G_H,data_buf[INDEX_PLL_ON_OFF_3_5G_H]);
12016 12016
  8009262:	204b      	movs	r0, #75	; 0x4b
12017 12017
  8009264:	f7fe fd78 	bl	8007d58 <Power_ON_OFF_Ctrl>
@@ -12027,103 +12027,109 @@ void RF_Operate(uint8_t* data_buf){
12027 12027
         if(data_buf[INDEX_PLL_ON_OFF_3_5G_H]){
12028 12028
  8009276:	f894 304b 	ldrb.w	r3, [r4, #75]	; 0x4b
12029 12029
  800927a:	2b00      	cmp	r3, #0
12030
- 800927c:	d035      	beq.n	80092ea <RF_Operate+0x75e>
12031
-//            printf("PLL CTRL START !! \r\n");
12030
+ 800927c:	d037      	beq.n	80092ee <RF_Operate+0x762>
12032 12031
 #if 1 // PYJ.2019.08.12_BEGIN -- 
12033
-            temp_val = (Prev_data[INDEX_PLL_3_5G_LOW_H] << 16) |
12034
-                       (Prev_data[INDEX_PLL_3_5G_LOW_M] << 8) | 
12035
- 800927e:	7feb      	ldrb	r3, [r5, #31]
12036
-            temp_val = (Prev_data[INDEX_PLL_3_5G_LOW_H] << 16) |
12037
- 8009280:	7faa      	ldrb	r2, [r5, #30]
12038
-                       (Prev_data[INDEX_PLL_3_5G_LOW_M] << 8) | 
12039
- 8009282:	021b      	lsls	r3, r3, #8
12040
-            temp_val = (Prev_data[INDEX_PLL_3_5G_LOW_H] << 16) |
12041
- 8009284:	ea43 4302 	orr.w	r3, r3, r2, lsl #16
12042
-                       (Prev_data[INDEX_PLL_3_5G_LOW_L]);
12043
- 8009288:	f895 2020 	ldrb.w	r2, [r5, #32]
12032
+//            temp_val = (Prev_data[INDEX_PLL_3_5G_LOW_H] << 16) |
12033
+//                       (Prev_data[INDEX_PLL_3_5G_LOW_M] << 8) | 
12034
+//                       (Prev_data[INDEX_PLL_3_5G_LOW_L]);
12035
+            temp_val = (Prev_data[INDEX_PLL_3_5G_HIGH_H] << 16) | 
12036
+                       (Prev_data[INDEX_PLL_3_5G_HIGH_M] << 8)  | 
12037
+ 800927e:	f895 3022 	ldrb.w	r3, [r5, #34]	; 0x22
12038
+            temp_val = (Prev_data[INDEX_PLL_3_5G_HIGH_H] << 16) | 
12039
+ 8009282:	f895 2021 	ldrb.w	r2, [r5, #33]	; 0x21
12040
+                       (Prev_data[INDEX_PLL_3_5G_HIGH_M] << 8)  | 
12041
+ 8009286:	021b      	lsls	r3, r3, #8
12042
+            temp_val = (Prev_data[INDEX_PLL_3_5G_HIGH_H] << 16) | 
12043
+ 8009288:	ea43 4302 	orr.w	r3, r3, r2, lsl #16
12044
+                       (Prev_data[INDEX_PLL_3_5G_HIGH_L]);
12045
+ 800928c:	f895 2023 	ldrb.w	r2, [r5, #35]	; 0x23
12046
+
12047
+
12044 12048
             temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
12045
- 800928c:	2100      	movs	r1, #0
12046
-                       (Prev_data[INDEX_PLL_3_5G_LOW_M] << 8) | 
12047
- 800928e:	4313      	orrs	r3, r2
12049
+ 8009290:	2100      	movs	r1, #0
12050
+                       (Prev_data[INDEX_PLL_3_5G_HIGH_M] << 8)  | 
12051
+ 8009292:	4313      	orrs	r3, r2
12048 12052
             temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
12049
- 8009290:	f241 3288 	movw	r2, #5000	; 0x1388
12050
- 8009294:	9203      	str	r2, [sp, #12]
12051
- 8009296:	2202      	movs	r2, #2
12052
- 8009298:	9202      	str	r2, [sp, #8]
12053
- 800929a:	f242 7210 	movw	r2, #10000	; 0x2710
12054
- 800929e:	48c4      	ldr	r0, [pc, #784]	; (80095b0 <RF_Operate+0xa24>)
12055
- 80092a0:	435a      	muls	r2, r3
12056
- 80092a2:	e9cd 0100 	strd	r0, r1, [sp]
12057
- 80092a6:	2300      	movs	r3, #0
12058
- 80092a8:	a826      	add	r0, sp, #152	; 0x98
12059
- 80092aa:	f7fe fb29 	bl	8007900 <ADF4153_Freq_Calc>
12053
+ 8009294:	f241 3288 	movw	r2, #5000	; 0x1388
12054
+ 8009298:	9203      	str	r2, [sp, #12]
12055
+ 800929a:	2202      	movs	r2, #2
12056
+ 800929c:	9202      	str	r2, [sp, #8]
12057
+ 800929e:	f242 7210 	movw	r2, #10000	; 0x2710
12058
+ 80092a2:	48c3      	ldr	r0, [pc, #780]	; (80095b0 <RF_Operate+0xa24>)
12059
+ 80092a4:	435a      	muls	r2, r3
12060
+ 80092a6:	e9cd 0100 	strd	r0, r1, [sp]
12061
+ 80092aa:	2300      	movs	r3, #0
12062
+ 80092ac:	a826      	add	r0, sp, #152	; 0x98
12063
+ 80092ae:	f7fe fb27 	bl	8007900 <ADF4153_Freq_Calc>
12060 12064
 #else
12061 12065
             temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
12062 12066
 #endif // PYJ.2019.08.12_END -- 
12063 12067
             ADF4153_Module_Ctrl(Pll_3_5_H,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
12064
- 80092ae:	2203      	movs	r2, #3
12065
- 80092b0:	9205      	str	r2, [sp, #20]
12066
- 80092b2:	f241 32c2 	movw	r2, #5058	; 0x13c2
12067
- 80092b6:	9204      	str	r2, [sp, #16]
12068
- 80092b8:	9a26      	ldr	r2, [sp, #152]	; 0x98
12069
- 80092ba:	4bbe      	ldr	r3, [pc, #760]	; (80095b4 <RF_Operate+0xa28>)
12070
- 80092bc:	9203      	str	r2, [sp, #12]
12071
- 80092be:	9a27      	ldr	r2, [sp, #156]	; 0x9c
12068
+ 80092b2:	2203      	movs	r2, #3
12069
+ 80092b4:	9205      	str	r2, [sp, #20]
12070
+ 80092b6:	f241 32c2 	movw	r2, #5058	; 0x13c2
12071
+ 80092ba:	9204      	str	r2, [sp, #16]
12072
+ 80092bc:	9a26      	ldr	r2, [sp, #152]	; 0x98
12073
+ 80092be:	4bbd      	ldr	r3, [pc, #756]	; (80095b4 <RF_Operate+0xa28>)
12074
+ 80092c0:	9203      	str	r2, [sp, #12]
12075
+ 80092c2:	9a27      	ldr	r2, [sp, #156]	; 0x9c
12072 12076
             PE43711_ALL_atten_ctrl(ALL_ATT_3_5G);
12073
- 80092c0:	4ebd      	ldr	r6, [pc, #756]	; (80095b8 <RF_Operate+0xa2c>)
12077
+ 80092c4:	4ebc      	ldr	r6, [pc, #752]	; (80095b8 <RF_Operate+0xa2c>)
12074 12078
             ADF4153_Module_Ctrl(Pll_3_5_H,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
12075
- 80092c2:	9202      	str	r2, [sp, #8]
12076
- 80092c4:	f103 0210 	add.w	r2, r3, #16
12077
- 80092c8:	e892 0003 	ldmia.w	r2, {r0, r1}
12078
- 80092cc:	e88d 0003 	stmia.w	sp, {r0, r1}
12079
- 80092d0:	cb0f      	ldmia	r3, {r0, r1, r2, r3}
12080
- 80092d2:	f7fe fba3 	bl	8007a1c <ADF4153_Module_Ctrl>
12079
+ 80092c6:	9202      	str	r2, [sp, #8]
12080
+ 80092c8:	f103 0210 	add.w	r2, r3, #16
12081
+ 80092cc:	e892 0003 	ldmia.w	r2, {r0, r1}
12082
+ 80092d0:	e88d 0003 	stmia.w	sp, {r0, r1}
12083
+ 80092d4:	cb0f      	ldmia	r3, {r0, r1, r2, r3}
12084
+ 80092d6:	f7fe fba1 	bl	8007a1c <ADF4153_Module_Ctrl>
12081 12085
             PE43711_ALL_atten_ctrl(ALL_ATT_3_5G);
12082
- 80092d6:	2298      	movs	r2, #152	; 0x98
12083
- 80092d8:	f106 0110 	add.w	r1, r6, #16
12084
- 80092dc:	4668      	mov	r0, sp
12085
- 80092de:	f000 fa0f 	bl	8009700 <memcpy>
12086
- 80092e2:	e896 000f 	ldmia.w	r6, {r0, r1, r2, r3}
12087
- 80092e6:	f7fe f9b3 	bl	8007650 <PE43711_ALL_atten_ctrl>
12086
+ 80092da:	2298      	movs	r2, #152	; 0x98
12087
+ 80092dc:	f106 0110 	add.w	r1, r6, #16
12088
+ 80092e0:	4668      	mov	r0, sp
12089
+ 80092e2:	f000 fa0d 	bl	8009700 <memcpy>
12090
+ 80092e6:	e896 000f 	ldmia.w	r6, {r0, r1, r2, r3}
12091
+ 80092ea:	f7fe f9b1 	bl	8007650 <PE43711_ALL_atten_ctrl>
12088 12092
         }
12089 12093
     }
12090 12094
     if(Prev_data[INDEX_PLL_ON_OFF_3_5G_L] != data_buf[INDEX_PLL_ON_OFF_3_5G_L]){
12091
- 80092ea:	f894 104c 	ldrb.w	r1, [r4, #76]	; 0x4c
12092
- 80092ee:	f895 304c 	ldrb.w	r3, [r5, #76]	; 0x4c
12093
- 80092f2:	428b      	cmp	r3, r1
12094
- 80092f4:	d045      	beq.n	8009382 <RF_Operate+0x7f6>
12095
+ 80092ee:	f894 104c 	ldrb.w	r1, [r4, #76]	; 0x4c
12096
+ 80092f2:	f895 304c 	ldrb.w	r3, [r5, #76]	; 0x4c
12097
+ 80092f6:	428b      	cmp	r3, r1
12098
+ 80092f8:	d043      	beq.n	8009382 <RF_Operate+0x7f6>
12095 12099
         Power_ON_OFF_Ctrl(INDEX_PLL_ON_OFF_3_5G_L,data_buf[INDEX_PLL_ON_OFF_3_5G_L]);
12096
- 80092f6:	204c      	movs	r0, #76	; 0x4c
12097
- 80092f8:	f7fe fd2e 	bl	8007d58 <Power_ON_OFF_Ctrl>
12100
+ 80092fa:	204c      	movs	r0, #76	; 0x4c
12101
+ 80092fc:	f7fe fd2c 	bl	8007d58 <Power_ON_OFF_Ctrl>
12098 12102
         Prev_data[INDEX_PLL_ON_OFF_3_5G_L] = data_buf[INDEX_PLL_ON_OFF_3_5G_L];
12099
- 80092fc:	f894 304c 	ldrb.w	r3, [r4, #76]	; 0x4c
12103
+ 8009300:	f894 304c 	ldrb.w	r3, [r4, #76]	; 0x4c
12100 12104
         HAL_Delay(1);
12101
- 8009300:	2001      	movs	r0, #1
12105
+ 8009304:	2001      	movs	r0, #1
12102 12106
         Prev_data[INDEX_PLL_ON_OFF_3_5G_L] = data_buf[INDEX_PLL_ON_OFF_3_5G_L];
12103
- 8009302:	f885 304c 	strb.w	r3, [r5, #76]	; 0x4c
12107
+ 8009306:	f885 304c 	strb.w	r3, [r5, #76]	; 0x4c
12104 12108
         HAL_Delay(1);
12105
- 8009306:	f7fc f8f1 	bl	80054ec <HAL_Delay>
12109
+ 800930a:	f7fc f8ef 	bl	80054ec <HAL_Delay>
12106 12110
 //        printf("POWER : %d \r\n",Prev_data[INDEX_PLL_ON_OFF_3_5G_L]);        
12107 12111
         if(data_buf[INDEX_PLL_ON_OFF_3_5G_L]){
12108
- 800930a:	f894 304c 	ldrb.w	r3, [r4, #76]	; 0x4c
12109
- 800930e:	2b00      	cmp	r3, #0
12110
- 8009310:	d037      	beq.n	8009382 <RF_Operate+0x7f6>
12111
-//            printf("PLL CTRL START !! \r\n");
12112
+ 800930e:	f894 304c 	ldrb.w	r3, [r4, #76]	; 0x4c
12113
+ 8009312:	2b00      	cmp	r3, #0
12114
+ 8009314:	d035      	beq.n	8009382 <RF_Operate+0x7f6>
12112 12115
 #if 1 // PYJ.2019.08.12_BEGIN -- 
12113
-            temp_val = (Prev_data[INDEX_PLL_3_5G_HIGH_H] << 16) | 
12114
-                       (Prev_data[INDEX_PLL_3_5G_HIGH_M] << 8)  | 
12115
- 8009312:	f895 3022 	ldrb.w	r3, [r5, #34]	; 0x22
12116
-            temp_val = (Prev_data[INDEX_PLL_3_5G_HIGH_H] << 16) | 
12117
- 8009316:	f895 2021 	ldrb.w	r2, [r5, #33]	; 0x21
12118
-                       (Prev_data[INDEX_PLL_3_5G_HIGH_M] << 8)  | 
12116
+//            temp_val = (Prev_data[INDEX_PLL_3_5G_HIGH_H] << 16) | 
12117
+//                       (Prev_data[INDEX_PLL_3_5G_HIGH_M] << 8)  | 
12118
+//                       (Prev_data[INDEX_PLL_3_5G_HIGH_L]);
12119
+            temp_val = (Prev_data[INDEX_PLL_3_5G_LOW_H] << 16) |
12120
+                       (Prev_data[INDEX_PLL_3_5G_LOW_M] << 8) | 
12121
+ 8009316:	7feb      	ldrb	r3, [r5, #31]
12122
+            temp_val = (Prev_data[INDEX_PLL_3_5G_LOW_H] << 16) |
12123
+ 8009318:	7faa      	ldrb	r2, [r5, #30]
12124
+                       (Prev_data[INDEX_PLL_3_5G_LOW_M] << 8) | 
12119 12125
  800931a:	021b      	lsls	r3, r3, #8
12120
-            temp_val = (Prev_data[INDEX_PLL_3_5G_HIGH_H] << 16) | 
12126
+            temp_val = (Prev_data[INDEX_PLL_3_5G_LOW_H] << 16) |
12121 12127
  800931c:	ea43 4302 	orr.w	r3, r3, r2, lsl #16
12122
-                       (Prev_data[INDEX_PLL_3_5G_HIGH_L]);
12123
- 8009320:	f895 2023 	ldrb.w	r2, [r5, #35]	; 0x23
12128
+                       (Prev_data[INDEX_PLL_3_5G_LOW_L]);
12129
+ 8009320:	f895 2020 	ldrb.w	r2, [r5, #32]
12124 12130
             temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
12125 12131
  8009324:	2100      	movs	r1, #0
12126
-                       (Prev_data[INDEX_PLL_3_5G_HIGH_M] << 8)  | 
12132
+                       (Prev_data[INDEX_PLL_3_5G_LOW_M] << 8) | 
12127 12133
  8009326:	4313      	orrs	r3, r2
12128 12134
             temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
12129 12135
  8009328:	f241 3288 	movw	r2, #5000	; 0x1388

BIN
Debug/Src/zig_operate.o


+ 1 - 1
Debug/Src/zig_operate.su

@@ -2,4 +2,4 @@ zig_operate.c:201:6:RF_Data_Check	8	static
2 2
 zig_operate.c:234:6:RF_Status_Get	8	static
3 3
 zig_operate.c:248:6:RF_Status_Ack	8	static
4 4
 zig_operate.c:262:6:RF_Operate	176	static
5
-zig_operate.c:694:6:RF_Ctrl_Main	16	static
5
+zig_operate.c:702:6:RF_Ctrl_Main	16	static

+ 14 - 6
Src/zig_operate.c

@@ -566,9 +566,14 @@ void RF_Operate(uint8_t* data_buf){
566 566
         if(data_buf[INDEX_PLL_ON_OFF_3_5G_H]){
567 567
 //            printf("PLL CTRL START !! \r\n");
568 568
 #if 1 // PYJ.2019.08.12_BEGIN -- 
569
-            temp_val = (Prev_data[INDEX_PLL_3_5G_LOW_H] << 16) |
570
-                       (Prev_data[INDEX_PLL_3_5G_LOW_M] << 8) | 
571
-                       (Prev_data[INDEX_PLL_3_5G_LOW_L]);
569
+//            temp_val = (Prev_data[INDEX_PLL_3_5G_LOW_H] << 16) |
570
+//                       (Prev_data[INDEX_PLL_3_5G_LOW_M] << 8) | 
571
+//                       (Prev_data[INDEX_PLL_3_5G_LOW_L]);
572
+            temp_val = (Prev_data[INDEX_PLL_3_5G_HIGH_H] << 16) | 
573
+                       (Prev_data[INDEX_PLL_3_5G_HIGH_M] << 8)  | 
574
+                       (Prev_data[INDEX_PLL_3_5G_HIGH_L]);
575
+
576
+
572 577
             temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
573 578
 #else
574 579
             temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
@@ -585,9 +590,12 @@ void RF_Operate(uint8_t* data_buf){
585 590
         if(data_buf[INDEX_PLL_ON_OFF_3_5G_L]){
586 591
 //            printf("PLL CTRL START !! \r\n");
587 592
 #if 1 // PYJ.2019.08.12_BEGIN -- 
588
-            temp_val = (Prev_data[INDEX_PLL_3_5G_HIGH_H] << 16) | 
589
-                       (Prev_data[INDEX_PLL_3_5G_HIGH_M] << 8)  | 
590
-                       (Prev_data[INDEX_PLL_3_5G_HIGH_L]);
593
+//            temp_val = (Prev_data[INDEX_PLL_3_5G_HIGH_H] << 16) | 
594
+//                       (Prev_data[INDEX_PLL_3_5G_HIGH_M] << 8)  | 
595
+//                       (Prev_data[INDEX_PLL_3_5G_HIGH_L]);
596
+            temp_val = (Prev_data[INDEX_PLL_3_5G_LOW_H] << 16) |
597
+                       (Prev_data[INDEX_PLL_3_5G_LOW_M] << 8) | 
598
+                       (Prev_data[INDEX_PLL_3_5G_LOW_L]);
591 599
             temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
592 600
 #else
593 601
           temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);            

+ 744 - 0
insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/zig_operate(2390).c

@@ -0,0 +1,744 @@
1
+/*
2
+ * zig_operate.c
3
+ *
4
+ *  Created on: 2019. 7. 26.
5
+ *      Author: parkyj
6
+ */
7
+#include "zig_operate.h"
8
+#include "main.h"
9
+#include "pll_4113.h"
10
+#include "ADF4153.h"
11
+#include "PE43711.h"
12
+#include "BDA4601.h"
13
+#include "uart.h"
14
+#include "CRC16.h"
15
+extern void AD5318_Ctrl(uint16_t ShiftTarget) ;
16
+extern etError STH30_CheckCrc(uint8_t *data, uint8_t nbrOfBytes, uint8_t checksum);
17
+extern void ADF4153_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2,uint32_t R3);
18
+extern bool Bluecell_Flash_Read(uint8_t* data);
19
+extern void PE43711_ALL_atten_ctrl(ALL_PE43711_st ATT);
20
+extern void Power_ON_OFF_Ctrl(uint8_t type,uint8_t cmd);
21
+extern uint8_t Bluecell_Flash_Write(uint8_t* data);
22
+uint8_t Prev_data[INDEX_BLUE_EOF + 1];
23
+uint8_t Flash_Save_data[INDEX_BLUE_EOF + 1];
24
+
25
+
26
+/* * * * * * * #define Struct* * * * * * * */
27
+PLL_Setting_st Pll_1_8GHz_DL = {
28
+	PLL_CLK_GPIO_Port,
29
+	PLL_CLK_Pin,
30
+	PLL_DATA_GPIO_Port,
31
+	PLL_DATA_Pin,
32
+    PLL_EN_1_8G_DL_GPIO_Port,    
33
+    PLL_EN_1_8G_DL_Pin,
34
+};
35
+PLL_Setting_st Pll_1_8GHz_UL = {
36
+    PLL_CLK_GPIO_Port,
37
+    PLL_CLK_Pin,
38
+    PLL_DATA_GPIO_Port,
39
+    PLL_DATA_Pin,
40
+    PLL_EN_1_8G_UL_GPIO_Port,    
41
+    PLL_EN_1_8G_UL_Pin,
42
+};
43
+PLL_Setting_st Pll_2_1GHz_DL = {
44
+    PLL_CLK_GPIO_Port,
45
+    PLL_CLK_Pin,
46
+    PLL_DATA_GPIO_Port,
47
+    PLL_DATA_Pin,
48
+    PLL_EN_2_1G_DL_GPIO_Port,    
49
+    PLL_EN_2_1G_DL_Pin,
50
+};
51
+PLL_Setting_st Pll_2_1GHz_UL = {
52
+    PLL_CLK_GPIO_Port,
53
+    PLL_CLK_Pin,
54
+    PLL_DATA_GPIO_Port,
55
+    PLL_DATA_Pin,
56
+    PLL_EN_2_1G_UL_GPIO_Port,    
57
+    PLL_EN_2_1G_UL_Pin,
58
+};
59
+/* * * * * * * * NOT YET * * * * * * * */
60
+PLL_Setting_st Pll_3_5GHz_DL = {
61
+    ATT_CLK_3_5G_GPIO_Port,
62
+    ATT_EN_3_5G_Pin,
63
+    PLL_DATA_GPIO_Port,
64
+    PLL_DATA_Pin,
65
+    PLL_EN_2_1G_DL_GPIO_Port,    
66
+    PLL_EN_2_1G_DL_Pin,
67
+};
68
+PLL_Setting_st Pll_3_5GHz_UL = {
69
+    PLL_CLK_GPIO_Port,
70
+    PLL_CLK_Pin,
71
+    PLL_DATA_GPIO_Port,
72
+    PLL_DATA_Pin,
73
+    PLL_EN_2_1G_UL_GPIO_Port,    
74
+    PLL_EN_2_1G_UL_Pin,
75
+};
76
+/* * * * * * * * ATTEN * * * * * * * */    
77
+ATTEN_Setting_st Atten_1_8Ghz_DL1 ={
78
+    ATT_CLK_GPIO_Port,
79
+    ATT_CLK_Pin,
80
+    ATT_DATA_GPIO_Port,
81
+    ATT_DATA_Pin,
82
+    ATT_EN_1_8G_DL1_GPIO_Port,    
83
+    ATT_EN_1_8G_DL1_Pin,
84
+    PATH_EN_1_8G_DL_GPIO_Port,
85
+    PATH_EN_1_8G_DL_Pin,
86
+};
87
+
88
+ATTEN_Setting_st Atten_1_8Ghz_DL2 ={
89
+    ATT_CLK_GPIO_Port,
90
+    ATT_CLK_Pin,
91
+    ATT_DATA_GPIO_Port,
92
+    ATT_DATA_Pin,
93
+    ATT_EN_1_8G_DL2_GPIO_Port,    
94
+    ATT_EN_1_8G_DL2_Pin,
95
+    PATH_EN_1_8G_DL_GPIO_Port,
96
+    PATH_EN_1_8G_DL_Pin,    
97
+};
98
+ATTEN_Setting_st Atten_1_8Ghz_UL1 ={
99
+    ATT_CLK_GPIO_Port,
100
+    ATT_CLK_Pin,
101
+    ATT_DATA_GPIO_Port,
102
+    ATT_DATA_Pin,
103
+    ATT_EN_1_8G_UL1_GPIO_Port,    
104
+    ATT_EN_1_8G_UL1_Pin,
105
+    PATH_EN_1_8G_UL_GPIO_Port,
106
+    PATH_EN_1_8G_UL_Pin,      
107
+};
108
+ATTEN_Setting_st Atten_1_8Ghz_UL2 ={
109
+    ATT_CLK_GPIO_Port,
110
+    ATT_CLK_Pin,
111
+    ATT_DATA_GPIO_Port,
112
+    ATT_DATA_Pin,
113
+    ATT_EN_1_8G_UL2_GPIO_Port,    
114
+    ATT_EN_1_8G_UL2_Pin,
115
+    PATH_EN_1_8G_UL_GPIO_Port,
116
+    PATH_EN_1_8G_UL_Pin,    
117
+};
118
+ATTEN_Setting_st Atten_1_8Ghz_UL3 ={
119
+    ATT_CLK_GPIO_Port,
120
+    ATT_CLK_Pin,
121
+    ATT_DATA_GPIO_Port,
122
+    ATT_DATA_Pin,
123
+    ATT_EN_1_8G_UL3_GPIO_Port,    
124
+    ATT_EN_1_8G_UL3_Pin,
125
+    PATH_EN_1_8G_UL_GPIO_Port,
126
+    PATH_EN_1_8G_UL_Pin,    
127
+};
128
+ATTEN_Setting_st Atten_1_8Ghz_UL4 ={
129
+    ATT_CLK_GPIO_Port,
130
+    ATT_CLK_Pin,
131
+    ATT_DATA_GPIO_Port,
132
+    ATT_DATA_Pin,
133
+    ATT_EN_1_8G_UL4_GPIO_Port,    
134
+    ATT_EN_1_8G_UL4_Pin,
135
+    PATH_EN_1_8G_UL_GPIO_Port,
136
+    PATH_EN_1_8G_UL_Pin,    
137
+};
138
+ATTEN_Setting_st Atten_2_1Ghz_DL1 ={
139
+    ATT_CLK_GPIO_Port,
140
+    ATT_CLK_Pin,
141
+    ATT_DATA_GPIO_Port,
142
+    ATT_DATA_Pin,
143
+    ATT_EN_2_1G_DL1_GPIO_Port,    
144
+    ATT_EN_2_1G_DL1_Pin,
145
+    PATH_EN_2_1G_DL_GPIO_Port,
146
+    PATH_EN_2_1G_DL_Pin,    
147
+};
148
+ATTEN_Setting_st Atten_2_1Ghz_DL2 ={
149
+    ATT_CLK_GPIO_Port,
150
+    ATT_CLK_Pin,
151
+    ATT_DATA_GPIO_Port,
152
+    ATT_DATA_Pin,
153
+    ATT_EN_2_1G_DL2_GPIO_Port,    
154
+    ATT_EN_2_1G_DL2_Pin,
155
+    PATH_EN_2_1G_DL_GPIO_Port,
156
+    PATH_EN_2_1G_DL_Pin,    
157
+};
158
+
159
+ATTEN_Setting_st Atten_2_1Ghz_UL1 ={
160
+    ATT_CLK_GPIO_Port,
161
+    ATT_CLK_Pin,
162
+    ATT_DATA_GPIO_Port,
163
+    ATT_DATA_Pin,
164
+    ATT_EN_2_1G_UL1_GPIO_Port,    
165
+    ATT_EN_2_1G_UL1_Pin,
166
+    PATH_EN_2_1G_UL_GPIO_Port,
167
+    PATH_EN_2_1G_UL_Pin,    
168
+};
169
+ATTEN_Setting_st Atten_2_1Ghz_UL2 ={
170
+    ATT_CLK_GPIO_Port,
171
+    ATT_CLK_Pin,
172
+    ATT_DATA_GPIO_Port,
173
+    ATT_DATA_Pin,
174
+    ATT_EN_2_1G_UL2_GPIO_Port,    
175
+    ATT_EN_2_1G_UL2_Pin,
176
+    PATH_EN_2_1G_UL_GPIO_Port,
177
+    PATH_EN_2_1G_UL_Pin,    
178
+};
179
+ATTEN_Setting_st Atten_2_1Ghz_UL3 ={
180
+    ATT_CLK_GPIO_Port,
181
+    ATT_CLK_Pin,
182
+    ATT_DATA_GPIO_Port,
183
+    ATT_DATA_Pin,
184
+    ATT_EN_2_1G_UL3_GPIO_Port,    
185
+    ATT_EN_2_1G_UL3_Pin,
186
+    PATH_EN_2_1G_UL_GPIO_Port,
187
+    PATH_EN_2_1G_UL_Pin,    
188
+};
189
+ATTEN_Setting_st Atten_2_1Ghz_UL4 ={
190
+    ATT_CLK_GPIO_Port,
191
+    ATT_CLK_Pin,
192
+    ATT_DATA_GPIO_Port,
193
+    ATT_DATA_Pin,
194
+    ATT_EN_2_1G_UL4_GPIO_Port,    
195
+    ATT_EN_2_1G_UL4_Pin,
196
+    PATH_EN_2_1G_UL_GPIO_Port,
197
+    PATH_EN_2_1G_UL_Pin,    
198
+};
199
+
200
+
201
+bool RF_Data_Check(uint8_t* data_buf){
202
+    bool ret = false;
203
+    bool crcret = STH30_CheckCrc(&data_buf[Type], data_buf[Length], data_buf[data_buf[Crcindex]]);
204
+    if(data_buf[Header] == BLUECELL_HEADER){ /*HEADER CHECK*/
205
+        ret= true;
206
+    }
207
+    if(crcret == true){/*CRC CHECK*/
208
+        ret = true;
209
+    }else{
210
+        ret = false;
211
+//        printf("Recv CRC Value : \"%d\"\r\n Create CRC Value : \"%d\"   \r\n",data_buf[data_buf[Crcindex]],STH30_CreateCrc(&data_buf[Type], data_buf[Length]));
212
+    }
213
+//    printf("CRC Result : \"%d\"   \r\n",ret);
214
+    return ret;
215
+
216
+}
217
+
218
+PLL_Setting_st Pll_3_5_H = {
219
+     PLL_CLK_3_5G_GPIO_Port,
220
+     PLL_CLK_3_5G_Pin,
221
+     PLL_DATA_3_5G_GPIO_Port,
222
+     PLL_DATA_3_5G_Pin,
223
+   PLL_EN_3_5G_H_GPIO_Port,    
224
+   PLL_EN_3_5G_H_Pin,
225
+ };
226
+ PLL_Setting_st Pll_3_5_L = {
227
+     PLL_CLK_3_5G_GPIO_Port,
228
+     PLL_CLK_3_5G_Pin,
229
+     PLL_DATA_3_5G_GPIO_Port,
230
+     PLL_DATA_3_5G_Pin,
231
+       PLL_EN_3_5G_L_GPIO_Port,    
232
+       PLL_EN_3_5G_L_Pin,
233
+ };
234
+void RF_Status_Get(void){
235
+//    printf("\r\nYJ2 : Prev_data[INDEX_DET_1_8G_DL_IN_L ] : %x\r\n",Prev_data[INDEX_DET_1_8G_DL_IN_L]);            
236
+    Prev_data[INDEX_BLUE_HEADER]   = BLUECELL_HEADER;
237
+    Prev_data[INDEX_BLUE_TYPE]     = TYPE_BLUECELL_GET;
238
+    Prev_data[INDEX_BLUE_LENGTH]   = INDEX_BLUE_EOF - 2;
239
+    Prev_data[INDEX_BLUE_CRCINDEX] = INDEX_BLUE_CRC;
240
+    Prev_data[INDEX_BLUE_CRC]      = STH30_CreateCrc(&Prev_data[Type], Prev_data[Length]);
241
+    Prev_data[INDEX_BLUE_EOF] = BLUECELL_TAILER;    
242
+    HAL_UART_Transmit_DMA(&huart1,&Prev_data[INDEX_BLUE_HEADER],INDEX_BLUE_EOF + 1); 
243
+//    printf("\r\nYJ : %x",ADCvalue[0]);
244
+//    printf("\r\n");
245
+
246
+}
247
+static uint8_t Ack_Buf[6];
248
+void RF_Status_Ack(void){
249
+//    printf("\r\nYJ2 : Prev_data[INDEX_DET_1_8G_DL_IN_L ] : %x\r\n",Prev_data[INDEX_DET_1_8G_DL_IN_L]);            
250
+    Ack_Buf[INDEX_BLUE_HEADER]       = BLUECELL_HEADER;
251
+    Ack_Buf[INDEX_BLUE_TYPE]         = TYPE_BLUECELL_ACK;
252
+    Ack_Buf[INDEX_BLUE_LENGTH]       = 3;
253
+    Ack_Buf[INDEX_BLUE_CRCINDEX + 0] = INDEX_BLUE_CRCINDEX + 1;
254
+    Ack_Buf[INDEX_BLUE_CRCINDEX + 1] = STH30_CreateCrc(&Ack_Buf[Type], Ack_Buf[Length]);
255
+    Ack_Buf[INDEX_BLUE_CRCINDEX + 2] = BLUECELL_TAILER;
256
+    HAL_UART_Transmit_DMA(&huart1,&Ack_Buf[INDEX_BLUE_HEADER],Ack_Buf[INDEX_BLUE_LENGTH]  + 3); 
257
+//    printf("\r\nYJ : %x",ADCvalue[0]);
258
+//    printf("\r\n");
259
+
260
+}
261
+
262
+void RF_Operate(uint8_t* data_buf){
263
+    uint32_t temp_val = 0;
264
+    uint8_t  ADC_Modify = 0;
265
+    ADF4153_R_N_Reg_st temp_reg;
266
+//    printf("Prev_data[INDEX_ATT_1_8G_DL1]  : %x  data_buf[INDEX_ATT_1_8G_DL1] : %x\r\n",Prev_data[INDEX_ATT_1_8G_DL1],data_buf[INDEX_ATT_1_8G_DL1]);
267
+    if(Prev_data[INDEX_ATT_1_8G_DL1] != data_buf[INDEX_ATT_1_8G_DL1]){
268
+        BDA4601_atten_ctrl(BDA4601_1_8G_DL1,(data_buf[INDEX_ATT_1_8G_DL1]));
269
+        Prev_data[INDEX_ATT_1_8G_DL1] = data_buf[INDEX_ATT_1_8G_DL1];
270
+    }
271
+    if(Prev_data[INDEX_ATT_1_8G_DL2] != data_buf[INDEX_ATT_1_8G_DL2]){
272
+        BDA4601_atten_ctrl(BDA4601_1_8G_DL2,(data_buf[INDEX_ATT_1_8G_DL2]));
273
+        Prev_data[INDEX_ATT_1_8G_DL2] = data_buf[INDEX_ATT_1_8G_DL2];
274
+    }
275
+    if(Prev_data[INDEX_ATT_1_8G_UL1] != data_buf[INDEX_ATT_1_8G_UL1]){
276
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL1,(data_buf[INDEX_ATT_1_8G_UL1]));
277
+        Prev_data[INDEX_ATT_1_8G_UL1] = data_buf[INDEX_ATT_1_8G_UL1];
278
+    }
279
+    if(Prev_data[INDEX_ATT_1_8G_UL2] != data_buf[INDEX_ATT_1_8G_UL2]){
280
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL2,(data_buf[INDEX_ATT_1_8G_UL2]));
281
+        Prev_data[INDEX_ATT_1_8G_UL2] = data_buf[INDEX_ATT_1_8G_UL2];
282
+    }
283
+    if(Prev_data[INDEX_ATT_1_8G_UL3] != data_buf[INDEX_ATT_1_8G_UL3]){
284
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL3,(data_buf[INDEX_ATT_1_8G_UL3]));
285
+        Prev_data[INDEX_ATT_1_8G_UL3] = data_buf[INDEX_ATT_1_8G_UL3];
286
+    }
287
+    if(Prev_data[INDEX_ATT_1_8G_UL4] != data_buf[INDEX_ATT_1_8G_UL4]){
288
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL4,(data_buf[INDEX_ATT_1_8G_UL4]));
289
+        Prev_data[INDEX_ATT_1_8G_UL4] = data_buf[INDEX_ATT_1_8G_UL4];
290
+    }
291
+    if(Prev_data[INDEX_ATT_2_1G_DL1] != data_buf[INDEX_ATT_2_1G_DL1]){
292
+        BDA4601_atten_ctrl(BDA4601_2_1G_DL1,(data_buf[INDEX_ATT_2_1G_DL1]));
293
+        Prev_data[INDEX_ATT_2_1G_DL1] = data_buf[INDEX_ATT_2_1G_DL1];
294
+
295
+    }
296
+    if(Prev_data[INDEX_ATT_2_1G_DL2] != data_buf[INDEX_ATT_2_1G_DL2]){
297
+        BDA4601_atten_ctrl(BDA4601_2_1G_DL2,(data_buf[INDEX_ATT_2_1G_DL2]));
298
+        Prev_data[INDEX_ATT_2_1G_DL2] = data_buf[INDEX_ATT_2_1G_DL2];
299
+
300
+    }
301
+    if(Prev_data[INDEX_ATT_2_1G_UL1] != data_buf[INDEX_ATT_2_1G_UL1]){
302
+        BDA4601_atten_ctrl(BDA4601_2_1G_UL1,(data_buf[INDEX_ATT_2_1G_UL1]));
303
+        Prev_data[INDEX_ATT_2_1G_UL1] = data_buf[INDEX_ATT_2_1G_UL1];
304
+
305
+    }
306
+    if(Prev_data[INDEX_ATT_2_1G_UL2] != data_buf[INDEX_ATT_2_1G_UL2]){
307
+        BDA4601_atten_ctrl(BDA4601_2_1G_UL2,(data_buf[INDEX_ATT_2_1G_UL2]));
308
+        Prev_data[INDEX_ATT_2_1G_UL2] = data_buf[INDEX_ATT_2_1G_UL2];
309
+
310
+    }
311
+    if(Prev_data[INDEX_ATT_2_1G_UL3] != data_buf[INDEX_ATT_2_1G_UL3]){
312
+        BDA4601_atten_ctrl(BDA4601_2_1G_UL3,(data_buf[INDEX_ATT_2_1G_UL3]));
313
+        Prev_data[INDEX_ATT_2_1G_UL3] = data_buf[INDEX_ATT_2_1G_UL3];
314
+    }
315
+    if(Prev_data[INDEX_ATT_2_1G_UL4] != data_buf[INDEX_ATT_2_1G_UL4]){
316
+        BDA4601_atten_ctrl(BDA4601_2_1G_UL4,(data_buf[INDEX_ATT_2_1G_UL4]));
317
+        Prev_data[INDEX_ATT_2_1G_UL4] = data_buf[INDEX_ATT_2_1G_UL4];
318
+    }
319
+    if(   (Prev_data[INDEX_ATT_3_5G_LOW1] != data_buf[INDEX_ATT_3_5G_LOW1])
320
+        ||(Prev_data[INDEX_ATT_3_5G_HIGH1] != data_buf[INDEX_ATT_3_5G_HIGH1])
321
+        ||(Prev_data[INDEX_ATT_3_5G_COM1] != data_buf[INDEX_ATT_3_5G_COM1])
322
+        ||(Prev_data[INDEX_ATT_3_5G_LOW2] != data_buf[INDEX_ATT_3_5G_LOW2])
323
+        ||(Prev_data[INDEX_ATT_3_5G_HIGH2] != data_buf[INDEX_ATT_3_5G_HIGH2])
324
+        ||(Prev_data[INDEX_ATT_3_5G_COM2] != data_buf[INDEX_ATT_3_5G_COM2])
325
+    ){
326
+        ALL_ATT_3_5G.data0 = Prev_data[INDEX_ATT_3_5G_LOW1]  = data_buf[INDEX_ATT_3_5G_LOW1];
327
+        ALL_ATT_3_5G.data1 = Prev_data[INDEX_ATT_3_5G_HIGH1] = data_buf[INDEX_ATT_3_5G_HIGH1];
328
+        ALL_ATT_3_5G.data2 = Prev_data[INDEX_ATT_3_5G_COM1]  = data_buf[INDEX_ATT_3_5G_COM1];
329
+        ALL_ATT_3_5G.data3 = Prev_data[INDEX_ATT_3_5G_LOW2]  = data_buf[INDEX_ATT_3_5G_LOW2];
330
+        ALL_ATT_3_5G.data4 = Prev_data[INDEX_ATT_3_5G_HIGH2] = data_buf[INDEX_ATT_3_5G_HIGH2];
331
+        ALL_ATT_3_5G.data5 = Prev_data[INDEX_ATT_3_5G_COM2]  = data_buf[INDEX_ATT_3_5G_COM2];
332
+        PE43711_ALL_atten_ctrl(ALL_ATT_3_5G);
333
+    }
334
+    if((Prev_data[INDEX_PLL_1_8G_DL_H] != data_buf[INDEX_PLL_1_8G_DL_H])
335
+        || (Prev_data[INDEX_PLL_1_8G_DL_L] != data_buf[INDEX_PLL_1_8G_DL_L])
336
+    ){
337
+        Prev_data[INDEX_PLL_1_8G_DL_H] = data_buf[INDEX_PLL_1_8G_DL_H];
338
+        Prev_data[INDEX_PLL_1_8G_DL_L] = data_buf[INDEX_PLL_1_8G_DL_L];
339
+//        printf("data_buf[INDEX_PLL_1_8G_DL_H] : %x \r\n",data_buf[INDEX_PLL_1_8G_DL_H]);
340
+//        printf("data_buf[INDEX_PLL_1_8G_DL_L] : %x\r\n",data_buf[INDEX_PLL_1_8G_DL_L]);
341
+        temp_val = (data_buf[INDEX_PLL_1_8G_DL_H] << 8) | (data_buf[INDEX_PLL_1_8G_DL_L]);
342
+        ADF4113_Module_Ctrl(ADF4113_1_8G_DL,0x410,halSynSetFreq(temp_val * 100000),0x9F8092);
343
+        HAL_Delay(1);
344
+        BDA4601_atten_ctrl(BDA4601_1_8G_DL1,(data_buf[INDEX_ATT_1_8G_DL1]));
345
+        BDA4601_atten_ctrl(BDA4601_1_8G_DL2,(data_buf[INDEX_ATT_1_8G_DL2]));
346
+    }
347
+    if((Prev_data[INDEX_PLL_1_8G_UL_H] != data_buf[INDEX_PLL_1_8G_UL_H])
348
+        || (Prev_data[INDEX_PLL_1_8G_UL_L] != data_buf[INDEX_PLL_1_8G_UL_L])){
349
+        temp_val = (data_buf[INDEX_PLL_1_8G_UL_H] << 8) | (data_buf[INDEX_PLL_1_8G_UL_L]);
350
+//        printf("data_buf[INDEX_PLL_1_8G_UL_H] : %x \r\n",data_buf[INDEX_PLL_1_8G_UL_H]);
351
+//        printf("data_buf[INDEX_PLL_1_8G_UL_L] : %x\r\n",data_buf[INDEX_PLL_1_8G_UL_L]);
352
+        Prev_data[INDEX_PLL_1_8G_UL_H] = data_buf[INDEX_PLL_1_8G_UL_H];
353
+        Prev_data[INDEX_PLL_1_8G_UL_L] = data_buf[INDEX_PLL_1_8G_UL_L];
354
+//         ADF4113_Module_Ctrl(ADF4113_1_8G_UL,0x000410,0x038D31,0x9f8092);
355
+         ADF4113_Module_Ctrl(ADF4113_1_8G_UL,0x410,halSynSetFreq(temp_val * 100000),0x9F8092);
356
+        HAL_Delay(1);
357
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL1,(data_buf[INDEX_ATT_1_8G_UL1]));
358
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL2,(data_buf[INDEX_ATT_1_8G_UL2]));
359
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL3,(data_buf[INDEX_ATT_1_8G_UL3]));
360
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL4,(data_buf[INDEX_ATT_1_8G_UL4]));
361
+    }
362
+    if((Prev_data[INDEX_PLL_2_1G_DL_H] != data_buf[INDEX_PLL_2_1G_DL_H])
363
+        || (Prev_data[INDEX_PLL_2_1G_DL_L] != data_buf[INDEX_PLL_2_1G_DL_L])){
364
+        temp_val = ((data_buf[INDEX_PLL_2_1G_DL_H] << 8) | (data_buf[INDEX_PLL_2_1G_DL_L]));
365
+//        printf("data_buf[INDEX_PLL_2_1G_DL_H] : %x \r\n",data_buf[INDEX_PLL_2_1G_DL_H]);
366
+//        printf("data_buf[INDEX_PLL_2_1G_DL_L] : %x\r\n",data_buf[INDEX_PLL_2_1G_DL_L]);
367
+        Prev_data[INDEX_PLL_2_1G_DL_H] = data_buf[INDEX_PLL_2_1G_DL_H];
368
+        Prev_data[INDEX_PLL_2_1G_DL_L] = data_buf[INDEX_PLL_2_1G_DL_L];        
369
+//         ADF4113_Module_Ctrl(ADF4113_2_1G_DL,0x410,0x4DE71,0x9F8092);
370
+        ADF4113_Module_Ctrl(ADF4113_2_1G_DL,0x410,halSynSetFreq(temp_val * 100000),0x9F8092);
371
+      HAL_Delay(1);
372
+      BDA4601_atten_ctrl(BDA4601_2_1G_DL1,(data_buf[INDEX_ATT_2_1G_DL1]));
373
+      BDA4601_atten_ctrl(BDA4601_2_1G_DL2,(data_buf[INDEX_ATT_2_1G_DL2]));
374
+    }
375
+    if((Prev_data[INDEX_PLL_2_1G_UL_H] != data_buf[INDEX_PLL_2_1G_UL_H])
376
+        || (Prev_data[INDEX_PLL_2_1G_UL_L] != data_buf[INDEX_PLL_2_1G_UL_L])){
377
+        Prev_data[INDEX_PLL_2_1G_UL_H] = data_buf[INDEX_PLL_2_1G_UL_H];
378
+        Prev_data[INDEX_PLL_2_1G_UL_L] = data_buf[INDEX_PLL_2_1G_UL_L];    
379
+//        printf("data_buf[INDEX_PLL_2_1G_UL_H] : %x \r\n",data_buf[INDEX_PLL_2_1G_UL_H]);
380
+//        printf("data_buf[INDEX_PLL_2_1G_UL_L] : %x\r\n",data_buf[INDEX_PLL_2_1G_UL_L]);
381
+        temp_val = (data_buf[INDEX_PLL_2_1G_UL_H] << 8) | (data_buf[INDEX_PLL_2_1G_UL_L]);
382
+//        ADF4113_Module_Ctrl(ADF4113_2_1G_UL,0x000410,0x59A31,0x9f8092);
383
+        ADF4113_Module_Ctrl(ADF4113_2_1G_UL,0x410,halSynSetFreq(temp_val * 100000),0x9F8092);
384
+      HAL_Delay(1);
385
+      BDA4601_atten_ctrl(BDA4601_2_1G_UL1,(data_buf[INDEX_ATT_2_1G_UL1]));
386
+      BDA4601_atten_ctrl(BDA4601_2_1G_UL2,(data_buf[INDEX_ATT_2_1G_UL2]));
387
+      BDA4601_atten_ctrl(BDA4601_2_1G_UL3,(data_buf[INDEX_ATT_2_1G_UL3]));      
388
+      BDA4601_atten_ctrl(BDA4601_2_1G_UL4,(data_buf[INDEX_ATT_2_1G_UL4]));      
389
+
390
+
391
+    }
392
+    if((Prev_data[INDEX_PLL_3_5G_LOW_H] != data_buf[INDEX_PLL_3_5G_LOW_H])
393
+        ||(Prev_data[INDEX_PLL_3_5G_LOW_M] != data_buf[INDEX_PLL_3_5G_LOW_M])
394
+        || (Prev_data[INDEX_PLL_3_5G_LOW_L] != data_buf[INDEX_PLL_3_5G_LOW_L])){
395
+        Prev_data[INDEX_PLL_3_5G_LOW_H] = data_buf[INDEX_PLL_3_5G_LOW_H];
396
+        Prev_data[INDEX_PLL_3_5G_LOW_M] = data_buf[INDEX_PLL_3_5G_LOW_M];        
397
+        Prev_data[INDEX_PLL_3_5G_LOW_L] = data_buf[INDEX_PLL_3_5G_LOW_L];
398
+        temp_val = (data_buf[INDEX_PLL_3_5G_LOW_H] << 16) | 
399
+                   (data_buf[INDEX_PLL_3_5G_LOW_M] << 8)  | 
400
+                   (data_buf[INDEX_PLL_3_5G_LOW_L]);
401
+#if 1 // PYJ.2019.08.12_BEGIN -- 
402
+        temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
403
+#else
404
+        temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
405
+#endif // PYJ.2019.08.12_END -- 
406
+        ADF4153_Module_Ctrl(Pll_3_5_L,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
407
+    }
408
+    if((Prev_data[INDEX_PLL_3_5G_HIGH_H] != data_buf[INDEX_PLL_3_5G_HIGH_H])
409
+        || (Prev_data[INDEX_PLL_3_5G_HIGH_M] != data_buf[INDEX_PLL_3_5G_HIGH_M])
410
+        || (Prev_data[INDEX_PLL_3_5G_HIGH_L] != data_buf[INDEX_PLL_3_5G_HIGH_L])){
411
+        Prev_data[INDEX_PLL_3_5G_HIGH_H] = data_buf[INDEX_PLL_3_5G_HIGH_H];
412
+        Prev_data[INDEX_PLL_3_5G_HIGH_M] = data_buf[INDEX_PLL_3_5G_HIGH_M];
413
+        Prev_data[INDEX_PLL_3_5G_HIGH_L] = data_buf[INDEX_PLL_3_5G_HIGH_L];
414
+        temp_val = (data_buf[INDEX_PLL_3_5G_HIGH_H] << 16) |
415
+                   (data_buf[INDEX_PLL_3_5G_HIGH_M] << 8)  |
416
+                   (data_buf[INDEX_PLL_3_5G_HIGH_L]);
417
+#if 1 // PYJ.2019.08.12_BEGIN -- 
418
+        temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
419
+#else
420
+        temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
421
+#endif // PYJ.2019.08.12_END -- 
422
+        ADF4153_Module_Ctrl(Pll_3_5_H,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
423
+
424
+    }
425
+    if(Prev_data[INDEX_PLL_LD_6_BIT] != data_buf[INDEX_PLL_LD_6_BIT]){
426
+
427
+    }
428
+#if 0 // PYJ.2019.07.28_BEGIN -- 
429
+    if(Prev_data[INDEX_DET_1_8G_DL_IN_H] != data_buf[INDEX_DET_1_8G_DL_IN_H]){
430
+
431
+    }
432
+    if(Prev_data[INDEX_DET_1_8G_DL_IN_L] != data_buf[INDEX_DET_1_8G_DL_IN_L]){
433
+
434
+    }
435
+    if(Prev_data[INDEX_DET_1_8G_DL_OUT_H] != data_buf[INDEX_DET_1_8G_DL_OUT_H]){
436
+
437
+    }
438
+    if(Prev_data[INDEX_DET_1_8G_DL_OUT_L] != data_buf[INDEX_DET_1_8G_DL_OUT_L]){
439
+
440
+    }
441
+    if(Prev_data[INDEX_DET_1_8G_UL_IN_H] != data_buf[INDEX_DET_1_8G_UL_IN_H]){
442
+
443
+    }
444
+    if(Prev_data[INDEX_DET_1_8G_UL_IN_L] != data_buf[INDEX_DET_1_8G_UL_IN_L]){
445
+
446
+    }
447
+    if(Prev_data[INDEX_DET_1_8G_UL_OUT_H] != data_buf[INDEX_DET_1_8G_UL_OUT_H]){
448
+
449
+    }
450
+    if(Prev_data[INDEX_DET_1_8G_UL_OUT_L] != data_buf[INDEX_DET_1_8G_UL_OUT_L]){
451
+
452
+    }
453
+    if(Prev_data[INDEX_DET_2_1G_DL_IN_H] != data_buf[INDEX_DET_2_1G_DL_IN_H]){
454
+
455
+    }
456
+    if(Prev_data[INDEX_DET_2_1G_DL_IN_L] != data_buf[INDEX_DET_2_1G_DL_IN_L]){
457
+
458
+    }
459
+    if(Prev_data[INDEX_DET_2_1G_DL_OUT_H] != data_buf[INDEX_DET_2_1G_DL_OUT_H]){
460
+
461
+    }
462
+    if(Prev_data[INDEX_DET_2_1G_DL_OUT_L] != data_buf[INDEX_DET_2_1G_DL_OUT_L]){
463
+
464
+    }
465
+    if(Prev_data[INDEX_DET_2_1G_UL_IN_H] != data_buf[INDEX_DET_2_1G_UL_IN_H]){
466
+
467
+    }
468
+    if(Prev_data[INDEX_DET_2_1G_UL_IN_L] != data_buf[INDEX_DET_2_1G_UL_IN_L]){
469
+
470
+    }
471
+
472
+    if(Prev_data[INDEX_DET_2_1G_UL_OUT_H] != data_buf[INDEX_DET_2_1G_UL_OUT_H]){
473
+
474
+    }
475
+    if(Prev_data[INDEX_DET_2_1G_UL_OUT_L] != data_buf[INDEX_DET_2_1G_UL_OUT_L]){
476
+
477
+    }
478
+    if(Prev_data[INDEX_DET_3_5G_DL_IN_H] != data_buf[INDEX_DET_3_5G_DL_IN_H]){
479
+
480
+    }
481
+    if(Prev_data[INDEX_DET_3_5G_DL_IN_L] != data_buf[INDEX_DET_3_5G_DL_IN_L]){
482
+
483
+    }
484
+    if(Prev_data[INDEX_DET_3_5G_DL_OUT_L] != data_buf[INDEX_DET_3_5G_DL_OUT_L]){
485
+
486
+    }
487
+    if(Prev_data[INDEX_DET_3_5G_DL_OUT_H] != data_buf[INDEX_DET_3_5G_DL_OUT_H]){
488
+
489
+    }
490
+    if(Prev_data[INDEX_DET_3_5G_UL_IN_H] != data_buf[INDEX_DET_3_5G_UL_IN_H]){
491
+
492
+    }
493
+    if(Prev_data[INDEX_DET_3_5G_UL_IN_L] != data_buf[INDEX_DET_3_5G_UL_IN_L]){
494
+
495
+    }
496
+
497
+    if(Prev_data[INDEX_DET_3_5G_UL_OUT_H] != data_buf[INDEX_DET_3_5G_UL_OUT_H]){
498
+
499
+    }
500
+    if(Prev_data[INDEX_DET_3_5G_UL_OUT_L] != data_buf[INDEX_DET_3_5G_UL_OUT_L]){
501
+
502
+    }
503
+    if(Prev_data[INDEX_RFU_TEMP_H] != data_buf[INDEX_RFU_TEMP_H]){
504
+
505
+    }
506
+    if(Prev_data[INDEX_RFU_TEMP_L] != data_buf[INDEX_RFU_TEMP_L]){
507
+
508
+    }
509
+    if(Prev_data[INDEX__28V_DET_H] != data_buf[INDEX__28V_DET_H]){
510
+
511
+    }
512
+    if(Prev_data[INDEX__28V_DET_L] != data_buf[INDEX__28V_DET_L]){
513
+
514
+    }
515
+#endif // PYJ.2019.07.28_END -- 
516
+    if(Prev_data[INDEX_ALARM_AC] != data_buf[INDEX_ALARM_AC]){
517
+
518
+    }
519
+    if(Prev_data[INDEX_ALARM_DC] != data_buf[INDEX_ALARM_DC]){
520
+
521
+    }
522
+    if(Prev_data[INDEX_PATH_EN_1_8G_DL] != data_buf[INDEX_PATH_EN_1_8G_DL]){
523
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_1_8G_DL,data_buf[INDEX_PATH_EN_1_8G_DL]);
524
+        Prev_data[INDEX_PATH_EN_1_8G_DL] = data_buf[INDEX_PATH_EN_1_8G_DL];
525
+    }
526
+    if(Prev_data[INDEX_PATH_EN_1_8G_UL] != data_buf[INDEX_PATH_EN_1_8G_UL]){
527
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_1_8G_UL,data_buf[INDEX_PATH_EN_1_8G_UL]);
528
+        Prev_data[INDEX_PATH_EN_1_8G_UL] = data_buf[INDEX_PATH_EN_1_8G_UL];
529
+
530
+    }
531
+
532
+    if(Prev_data[INDEX_PATH_EN_2_1G_DL] != data_buf[INDEX_PATH_EN_2_1G_DL]){
533
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_2_1G_DL,data_buf[INDEX_PATH_EN_2_1G_DL]);
534
+        Prev_data[INDEX_PATH_EN_2_1G_DL] = data_buf[INDEX_PATH_EN_2_1G_DL];
535
+    }
536
+    if(Prev_data[INDEX_PATH_EN_2_1G_UL] != data_buf[INDEX_PATH_EN_2_1G_UL]){
537
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_2_1G_UL,data_buf[INDEX_PATH_EN_2_1G_UL]);
538
+        Prev_data[INDEX_PATH_EN_2_1G_UL] = data_buf[INDEX_PATH_EN_2_1G_UL];
539
+
540
+    }
541
+    if(Prev_data[INDEX_PATH_EN_3_5G_L] != data_buf[INDEX_PATH_EN_3_5G_L]){
542
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_L,data_buf[INDEX_PATH_EN_3_5G_L]);
543
+        Prev_data[INDEX_PATH_EN_3_5G_L] = data_buf[INDEX_PATH_EN_3_5G_L];
544
+
545
+    }
546
+    if(Prev_data[INDEX_PATH_EN_3_5G_H] != data_buf[INDEX_PATH_EN_3_5G_H]){
547
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_H,data_buf[INDEX_PATH_EN_3_5G_H]);
548
+        Prev_data[INDEX_PATH_EN_3_5G_H] = data_buf[INDEX_PATH_EN_3_5G_H];
549
+
550
+    }
551
+    if(Prev_data[INDEX_PATH_EN_3_5G_DL] != data_buf[INDEX_PATH_EN_3_5G_DL]){
552
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_DL,data_buf[INDEX_PATH_EN_3_5G_DL]);
553
+        Prev_data[INDEX_PATH_EN_3_5G_DL] = data_buf[INDEX_PATH_EN_3_5G_DL];
554
+
555
+    }
556
+    if(Prev_data[INDEX_PATH_EN_3_5G_UL] != data_buf[INDEX_PATH_EN_3_5G_UL]){
557
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_UL,data_buf[INDEX_PATH_EN_3_5G_UL]);
558
+        Prev_data[INDEX_PATH_EN_3_5G_UL] = data_buf[INDEX_PATH_EN_3_5G_UL];
559
+
560
+    }
561
+    if(Prev_data[INDEX_PLL_ON_OFF_3_5G_H] != data_buf[INDEX_PLL_ON_OFF_3_5G_H]){
562
+        Power_ON_OFF_Ctrl(INDEX_PLL_ON_OFF_3_5G_H,data_buf[INDEX_PLL_ON_OFF_3_5G_H]);
563
+        Prev_data[INDEX_PLL_ON_OFF_3_5G_H] = data_buf[INDEX_PLL_ON_OFF_3_5G_H];
564
+        HAL_Delay(1);
565
+//        printf("POWER : %d \r\n",Prev_data[INDEX_PLL_ON_OFF_3_5G_H]);
566
+        if(data_buf[INDEX_PLL_ON_OFF_3_5G_H]){
567
+//            printf("PLL CTRL START !! \r\n");
568
+#if 1 // PYJ.2019.08.12_BEGIN -- 
569
+            temp_val = (Prev_data[INDEX_PLL_3_5G_LOW_H] << 16) |
570
+                       (Prev_data[INDEX_PLL_3_5G_LOW_M] << 8) | 
571
+                       (Prev_data[INDEX_PLL_3_5G_LOW_L]);
572
+            temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
573
+#else
574
+            temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
575
+#endif // PYJ.2019.08.12_END -- 
576
+            ADF4153_Module_Ctrl(Pll_3_5_H,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
577
+            PE43711_ALL_atten_ctrl(ALL_ATT_3_5G);
578
+        }
579
+    }
580
+    if(Prev_data[INDEX_PLL_ON_OFF_3_5G_L] != data_buf[INDEX_PLL_ON_OFF_3_5G_L]){
581
+        Power_ON_OFF_Ctrl(INDEX_PLL_ON_OFF_3_5G_L,data_buf[INDEX_PLL_ON_OFF_3_5G_L]);
582
+        Prev_data[INDEX_PLL_ON_OFF_3_5G_L] = data_buf[INDEX_PLL_ON_OFF_3_5G_L];
583
+        HAL_Delay(1);
584
+//        printf("POWER : %d \r\n",Prev_data[INDEX_PLL_ON_OFF_3_5G_L]);        
585
+        if(data_buf[INDEX_PLL_ON_OFF_3_5G_L]){
586
+//            printf("PLL CTRL START !! \r\n");
587
+#if 1 // PYJ.2019.08.12_BEGIN -- 
588
+            temp_val = (Prev_data[INDEX_PLL_3_5G_HIGH_H] << 16) | 
589
+                       (Prev_data[INDEX_PLL_3_5G_HIGH_M] << 8)  | 
590
+                       (Prev_data[INDEX_PLL_3_5G_HIGH_L]);
591
+            temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
592
+#else
593
+          temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);            
594
+#endif // PYJ.2019.08.12_END -- 
595
+            ADF4153_Module_Ctrl(Pll_3_5_L,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
596
+            PE43711_ALL_atten_ctrl(ALL_ATT_3_5G);
597
+        }
598
+    }
599
+
600
+    if(Prev_data[INDEX_T_SYNC_DL] != data_buf[INDEX_T_SYNC_DL]){
601
+        Prev_data[INDEX_T_SYNC_DL] = data_buf[INDEX_T_SYNC_DL];
602
+        Power_ON_OFF_Ctrl(INDEX_T_SYNC_DL,data_buf[INDEX_T_SYNC_DL]);
603
+    }
604
+    if(Prev_data[INDEX__T_SYNC_DL] != data_buf[INDEX__T_SYNC_DL]){
605
+        Prev_data[INDEX__T_SYNC_DL] = data_buf[INDEX__T_SYNC_DL];
606
+        Power_ON_OFF_Ctrl(INDEX__T_SYNC_DL,data_buf[INDEX__T_SYNC_DL]);
607
+    }
608
+    if(Prev_data[INDEX_T_SYNC_UL] != data_buf[INDEX_T_SYNC_UL]){
609
+        Prev_data[INDEX_T_SYNC_UL] = data_buf[INDEX_T_SYNC_UL];
610
+        Power_ON_OFF_Ctrl(INDEX_T_SYNC_UL,data_buf[INDEX_T_SYNC_UL]);
611
+    }
612
+    if(Prev_data[INDEX__T_SYNC_UL] != data_buf[INDEX__T_SYNC_UL]){
613
+        Prev_data[INDEX__T_SYNC_UL] = data_buf[INDEX__T_SYNC_UL];
614
+        Power_ON_OFF_Ctrl(INDEX__T_SYNC_UL,data_buf[INDEX__T_SYNC_UL]);
615
+    }
616
+
617
+
618
+    if((Prev_data[INDEX_DAC_VCtrl_A_H] != data_buf[INDEX_DAC_VCtrl_A_H])
619
+        ||(Prev_data[INDEX_DAC_VCtrl_A_L] != data_buf[INDEX_DAC_VCtrl_A_L])){
620
+        ADC_Modify = 1;
621
+        Prev_data[INDEX_DAC_VCtrl_A_H] = data_buf[INDEX_DAC_VCtrl_A_H];
622
+        Prev_data[INDEX_DAC_VCtrl_A_L] = data_buf[INDEX_DAC_VCtrl_A_L];
623
+    }
624
+    if((Prev_data[INDEX_DAC_VCtrl_B_H] != data_buf[INDEX_DAC_VCtrl_B_H])
625
+        ||(Prev_data[INDEX_DAC_VCtrl_B_L] != data_buf[INDEX_DAC_VCtrl_B_L])){
626
+        ADC_Modify = 1;
627
+        
628
+        Prev_data[INDEX_DAC_VCtrl_B_H] = data_buf[INDEX_DAC_VCtrl_B_H];
629
+        Prev_data[INDEX_DAC_VCtrl_B_L] = data_buf[INDEX_DAC_VCtrl_B_L];        
630
+    }    
631
+    if((Prev_data[INDEX_DAC_VCtrl_C_H] != data_buf[INDEX_DAC_VCtrl_C_H])
632
+        ||(Prev_data[INDEX_DAC_VCtrl_C_L] != data_buf[INDEX_DAC_VCtrl_C_L])){
633
+        ADC_Modify = 1;
634
+//        printf("Prev_data[INDEX_DAC_VCtrl_C_H] : %x \r\n",Prev_data[INDEX_DAC_VCtrl_C_H]);
635
+//        printf("Prev_data[INDEX_DAC_VCtrl_C_L] : %x \r\n",Prev_data[INDEX_DAC_VCtrl_C_L]);
636
+
637
+        Prev_data[INDEX_DAC_VCtrl_C_H] = data_buf[INDEX_DAC_VCtrl_C_H];
638
+        Prev_data[INDEX_DAC_VCtrl_C_L] = data_buf[INDEX_DAC_VCtrl_C_L];        
639
+    }
640
+    if((Prev_data[INDEX_DAC_VCtrl_D_H] != data_buf[INDEX_DAC_VCtrl_D_H])
641
+        ||(Prev_data[INDEX_DAC_VCtrl_D_L] != data_buf[INDEX_DAC_VCtrl_D_L])){
642
+        ADC_Modify = 1;
643
+        Prev_data[INDEX_DAC_VCtrl_D_H] = data_buf[INDEX_DAC_VCtrl_D_H];
644
+        Prev_data[INDEX_DAC_VCtrl_D_L] = data_buf[INDEX_DAC_VCtrl_D_L];
645
+    }
646
+    if((Prev_data[INDEX_DAC_VCtrl_E_H] != data_buf[INDEX_DAC_VCtrl_E_H])
647
+        ||(Prev_data[INDEX_DAC_VCtrl_E_L] != data_buf[INDEX_DAC_VCtrl_E_L])){
648
+        ADC_Modify = 1;
649
+
650
+        Prev_data[INDEX_DAC_VCtrl_E_H] = data_buf[INDEX_DAC_VCtrl_E_H];
651
+        Prev_data[INDEX_DAC_VCtrl_E_L] = data_buf[INDEX_DAC_VCtrl_E_L];        
652
+    }
653
+    if((Prev_data[INDEX_DAC_VCtrl_F_H] != data_buf[INDEX_DAC_VCtrl_F_H])
654
+        ||(Prev_data[INDEX_DAC_VCtrl_F_L] != data_buf[INDEX_DAC_VCtrl_F_L])){
655
+        ADC_Modify = 1;
656
+        Prev_data[INDEX_DAC_VCtrl_F_H] = data_buf[INDEX_DAC_VCtrl_F_H];
657
+        Prev_data[INDEX_DAC_VCtrl_F_L] = data_buf[INDEX_DAC_VCtrl_F_L];        
658
+    }
659
+    if((Prev_data[INDEX_DAC_VCtrl_G_H] != data_buf[INDEX_DAC_VCtrl_G_H])
660
+        ||(Prev_data[INDEX_DAC_VCtrl_G_L] != data_buf[INDEX_DAC_VCtrl_G_L])){
661
+        ADC_Modify = 1;
662
+        Prev_data[INDEX_DAC_VCtrl_G_H] = data_buf[INDEX_DAC_VCtrl_G_H];
663
+        Prev_data[INDEX_DAC_VCtrl_G_L] = data_buf[INDEX_DAC_VCtrl_G_L];        
664
+    }    
665
+    if((Prev_data[INDEX_DAC_VCtrl_H_H] != data_buf[INDEX_DAC_VCtrl_H_H])
666
+        ||(Prev_data[INDEX_DAC_VCtrl_H_L] != data_buf[INDEX_DAC_VCtrl_H_L])){
667
+        ADC_Modify = 1;
668
+        Prev_data[INDEX_DAC_VCtrl_H_H] = data_buf[INDEX_DAC_VCtrl_H_H];
669
+        Prev_data[INDEX_DAC_VCtrl_H_L] = data_buf[INDEX_DAC_VCtrl_H_L];        
670
+    }
671
+    if(ADC_Modify){
672
+//        AD5318_Ctrl(0xF000);
673
+//        HAL_Delay(1);
674
+//        AD5318_Ctrl(0x800C);
675
+//        AD5318_Ctrl(0x2FFF );
676
+//        AD5318_Ctrl(0xA000);
677
+//        printf("DAC CTRL START \r\n");
678
+//        AD5318_Ctrl(0x800C);
679
+//        AD5318_Ctrl(0xA000);
680
+//        printf("DAC Change\r\n");
681
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_A_H] << 8 | Prev_data[INDEX_DAC_VCtrl_A_L]));    
682
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_B_H] << 8 | Prev_data[INDEX_DAC_VCtrl_B_L]));    
683
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_C_H] << 8 | Prev_data[INDEX_DAC_VCtrl_C_L]));
684
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_D_H] << 8 | Prev_data[INDEX_DAC_VCtrl_D_L]));
685
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_E_H] << 8 | Prev_data[INDEX_DAC_VCtrl_E_L]));    
686
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_F_H] << 8 | Prev_data[INDEX_DAC_VCtrl_F_L]));
687
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_G_H] << 8 | Prev_data[INDEX_DAC_VCtrl_G_L]));
688
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_H_H] << 8 | Prev_data[INDEX_DAC_VCtrl_H_L]));
689
+    }
690
+    
691
+}
692
+
693
+uint8_t temp_crc = 0;
694
+bool RF_Ctrl_Main(uint8_t* data_buf){
695
+    bool ret = false;
696
+    Bluecell_Prot_t type = data_buf[Type];
697
+    ret = RF_Data_Check(&data_buf[Header]); /* ERROR CHECK */
698
+    if(ret == false){
699
+        HAL_UART_Transmit(&huart1,&data_buf[INDEX_BLUE_HEADER],data_buf[INDEX_BLUE_LENGTH] + 2 + 1,3000); 
700
+        return ret;
701
+    }
702
+    
703
+    switch(type){
704
+    case TYPE_BLUECELL_RESET:
705
+        for(uint8_t i =0 ; i < data_buf[Length] + 6; i++)
706
+            printf("%02x ",data_buf[i]);
707
+        printf("Reset Start \r\n");
708
+        NVIC_SystemReset();
709
+        break;
710
+    case TYPE_BLUECELL_SET:
711
+#if 0 // PYJ.2019.07.31_BEGIN -- 
712
+    printf("TYPE_BLUECELL_SET : ");
713
+    for(uint8_t i =0 ; i < INDEX_BLUE_EOF + 1; i++)
714
+        printf("%02x ",data_buf[i]);
715
+#endif // PYJ.2019.07.31_END -- 
716
+        RF_Operate(&data_buf[Header]);
717
+        RF_Status_Ack();
718
+
719
+//        ADF4153_Freq_Calc(3465500000,40000000,2,5000);
720
+//        ADF4153_Freq_Calc(3993450000,40000000,2,5000);
721
+//        halSynSetFreq(1995000000);
722
+//        halSynSetFreq(1600000000);
723
+//        halSynSetFreq(1455000000);        
724
+        break;
725
+    case TYPE_BLUECELL_GET:
726
+#if 0 // PYJ.2019.08.01_BEGIN -- 
727
+        printf("\r\nTYPE_BLUECELL_GET : \r\n");
728
+#endif // PYJ.2019.08.01_END -- 
729
+        RF_Status_Get();
730
+        break;
731
+    case TYPE_BLUECELL_SAVE:
732
+//        printf("\r\nFLASH Write\r\n");
733
+        Bluecell_Flash_Write(&Prev_data[INDEX_BLUE_HEADER]);
734
+        RF_Status_Ack();
735
+
736
+        break;
737
+        default:
738
+#ifdef DEBUG_PRINT // PYJ.2019.07.27_BEGIN --         
739
+            printf("Function : %s   LINE : %d    type : %d \r\n",__func__,__LINE__,type);
740
+#endif
741
+            break;
742
+    }
743
+    return ret;
744
+}

+ 4 - 131
insight/STM32F103_ATTEN_PLL_Zig.si4project/STM32F103_ATTEN_PLL_Zig.SearchResults

@@ -1,131 +1,4 @@
1
----- printf Matches (130 in 10 files) ----
2
-AD5318_Ctrl in AD5318.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) : //    printf("ShiftTarget : %x \r\n",ShiftTarget);
3
-N_Divider_Reg_Create in adf4153.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :     printf("FRAC : %d INT : %d \r\n",(int)_FRAC,_INT);
4
-N_Divider_Reg_Create in adf4153.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :     printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);
5
-N_Divider_Reg_Create in adf4153.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :     printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);    
6
-N_Divider_Reg_Create in adf4153.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :     printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);    
7
-N_Divider_Reg_Create in adf4153.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :     printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);
8
-R_Divider_Reg_Create in adf4153.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :     printf("_MOD : %d INT : %d \r\n",_MOD,_RCOUNTER);
9
-R_Divider_Reg_Create in adf4153.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :     printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);
10
-R_Divider_Reg_Create in adf4153.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :     printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);
11
-ADF4153_Freq_Calc in adf4153.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :     printf("\r\ntemp_adf4153.N_Value : %f  temp_adf4153.INT_Value : %f  temp_adf4153.MOD_Value : %f \r\n",temp_adf4153.N_Value,(double)temp_adf4153.INT_Value,(double)temp_adf4153.MOD_Value);
12
-ADF4153_Freq_Calc in adf4153.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :     printf("\r\n temp_adf4153.N_Value - (double)temp_adf4153.INT_Value) : %f  temp * (double)temp_adf4153.MOD_Value : %f \r\n",temp,temp * (double)temp_adf4153.MOD_Value);
13
-ADF4153_Freq_Calc in adf4153.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :     printf("\r\ntemp_adf4153.N_Value : %x   : %f ",temp_adf4153.N_Value,((double)(Freq / 1000) /  (double)(temp_adf4153.PFD_Value / 1000)) / 1000);
14
-ADF4153_Freq_Calc in adf4153.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :     printf("temp_adf4153.MOD_Value : %x   : %d \r\n",temp_adf4153.MOD_Value,temp_adf4153.MOD_Value);
15
-ADF4153_Freq_Calc in adf4153.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :             printf("1");
16
-ADF4153_Freq_Calc in adf4153.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :             printf("0");
17
-ADF4153_Freq_Calc in adf4153.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :     printf("\r\n");
18
-ADF4153_Freq_Calc in adf4153.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :     printf("temp_adf4153.FRAC_Value : %x   : %d\r\n",temp_adf4153.FRAC_Value,temp_adf4153.FRAC_Value);
19
-ADF4153_Freq_Calc in adf4153.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :             printf("1");
20
-ADF4153_Freq_Calc in adf4153.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :             printf("0");
21
-ADF4153_Freq_Calc in adf4153.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :     printf("\r\n");    
22
-ADF4153_Freq_Calc in adf4153.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :     printf("temp_adf4153.INT_Value : %x   : %d\r\n",temp_adf4153.INT_Value,temp_adf4153.INT_Value); 
23
-ADF4153_Freq_Calc in adf4153.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :             printf("1");
24
-ADF4153_Freq_Calc in adf4153.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :             printf("0");
25
-ADF4153_Freq_Calc in adf4153.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :     printf("\r\n");    
26
-ADF4153_Freq_Calc in adf4153.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :     printf("R0: %x  R1: %x \r\n",N_Divider_Reg_Create(temp_adf4153.FRAC_Value,temp_adf4153.INT_Value,0),R_Divider_Reg_Create(temp_adf4153.MOD_Value,R_Counter,1,0,2,0));   
27
-ADF4153_Initialize in adf4153.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :         printf("\r\nPLL_EN_3_5G_H_GPIO_Port\r\n");
28
-ADF4153_Module_Ctrl in adf4153.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :     printf("YJ :R0: %x  R1:  %x   R2 : %x R3 : %x ",R0,R1,R2,R3);
29
-ADF4153_Module_Ctrl in adf4153.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :     printf("\r\n");
30
-ADF4153_Module_Ctrl in adf4153.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :             printf("1");
31
-ADF4153_Module_Ctrl in adf4153.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :             printf("0");
32
-ADF4153_Module_Ctrl in adf4153.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :     printf("\r\n");
33
-ADF4153_Module_Ctrl in adf4153.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :              printf("1");
34
-ADF4153_Module_Ctrl in adf4153.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :              printf("0");
35
-ADF4153_Module_Ctrl in adf4153.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :      printf("\r\n");
36
-ADF4153_Module_Ctrl in adf4153.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :             printf("1");
37
-ADF4153_Module_Ctrl in adf4153.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :             printf("0");
38
-ADF4153_Module_Ctrl in adf4153.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :     printf("\r\n");
39
-ADF4153_Module_Ctrl in adf4153.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :             printf("1");
40
-ADF4153_Module_Ctrl in adf4153.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :             printf("0");
41
-ADF4153_Module_Ctrl in adf4153.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :     printf("\r\n");
42
-BDA4601_atten_ctrl in BDA4601.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) : //    printf("BDA4601_atten_ctrl : %x \r\n",data);
43
-BDA4601_atten_ctrl in BDA4601.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) : //                     printf("1");
44
-BDA4601_atten_ctrl in BDA4601.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) : //                printf("0");
45
-Jump_App in flash.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :     printf("boot loader start\n");               //硫붿꽭占�? 異쒕젰
46
-Jump_App in flash.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :     printf("jump!\n");
47
-Flash_InitRead in flash.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :         printf("%08x : %02X \n",Address ,*(uint8_t*)Address);
48
-Flash_InitRead in flash.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :         printf("%08x : %02X \n",Address ,*(uint8_t*)Address);
49
-Flash_InitRead in flash.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :         printf("%02X ",*(uint8_t*)Address);
50
-Flash_RGB_Data_Write in flash.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :             printf("HAL NOT OK \n");
51
-Flash_write in flash.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :             printf("Erase Failed \r\n");
52
-FLASH_Byte_Write in flash.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) : //  printf("Flash Write Start \r\n");
53
-FLASH_Byte_Write in flash.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :     printf("Eraser Error\r\n");
54
-FLASH_Byte_Write in flash.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :             printf("Write Error %d\r\n",__LINE__);
55
-FLASH_Byte_Write in flash.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :     printf("Addr = %x, Data = %x\r\n", FLASH_USER_START_ADDR + i, *(__IO uint16_t *)(FLASH_USER_START_ADDR + i));
56
-Bluecell_Flash_Read in flash.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) : //        printf("Addr = %x, Data = %x\r\n", FLASH_USER_START_ADDR + i, *(__IO uint16_t *)(FLASH_USER_START_ADDR + i));
57
-Bluecell_Flash_Read in flash.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :         printf("Data = %x\r\n",  data[i]);
58
-kConstPrinter in includes.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :     printf("%s", Bluecell_Prot_IndexStr[k]);
59
-Power_ON_OFF_Ctrl in includes.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) : //    printf("\r\ntype : %s cmd : %d\r\n",Bluecell_Prot_IndexStr[type - 4],cmd);
60
-Power_ON_OFF_Ctrl in includes.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :             printf("\r\n LINE %d\r\n",__LINE__);
61
-Power_ON_OFF_Ctrl in includes.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :             printf("\r\n LINE %d\r\n",__LINE__);
62
-Power_ON_OFF_Ctrl in includes.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :             printf("\r\n LINE %d\r\n",__LINE__);
63
-Power_ON_OFF_Ctrl in includes.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :             printf("\r\n LINE %d\r\n",__LINE__);
64
-Power_ON_OFF_Ctrl in includes.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) : //                printf("\r\n LINE %d\r\n",__LINE__);
65
-Power_ON_OFF_Ctrl in includes.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) : //                printf("\r\n LINE %d\r\n",__LINE__);
66
-Power_ON_OFF_Ctrl in includes.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) : //                            printf("\r\n LINE %d\r\n",__LINE__);
67
-Power_ON_OFF_Ctrl in includes.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) : //                            printf("\r\n LINE %d\r\n",__LINE__);
68
-Power_ON_OFF_Ctrl in includes.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :             printf("\r\n LINE %d\r\n",__LINE__);
69
-Power_ON_OFF_Ctrl in includes.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :             printf("\r\n LINE %d\r\n",__LINE__);
70
-Power_ON_OFF_Ctrl in includes.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) : //            printf("\r\n LINE %d\r\n",__LINE__);
71
-Power_ON_OFF_Ctrl in includes.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) : //            printf("\r\n LINE %d\r\n",__LINE__);
72
-Power_ON_OFF_Ctrl in includes.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :             printf("TDD SYNC OPERATE ; %d\r\n",cmd);
73
-Power_ON_OFF_Ctrl in includes.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :         printf("Function : %s LINE : %d   ERROR \r\n",__func__,__LINE__);
74
-ATTEN_PLL_PATH_Initialize in includes.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :             printf("Data = %x\r\n",  Flash_Save_data[i]);
75
-ADC_Check in includes.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :           printf("Prev_data[%d] : %x",i,Prev_data[INDEX_DET_1_8G_DL_IN_H + i]);
76
-ADC_Check in includes.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :           printf("%x\r\n",i,Prev_data[INDEX_DET_1_8G_DL_IN_L + i]);            
77
-assert_failed in main.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :      tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
78
-PE43711_ALL_atten_ctrl in PE43711.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) : //    printf("why not? \r\n");
79
-halSynSetFreq in pll_4113.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :     printf("FREQ:%f Mhz  B : %d , A  : %d    N_VAL  : %d \r\n",(float)(rf_Freq/1000000),B,A,N_val);
80
-halSynSetFreq in pll_4113.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :     printf("YJ 4113 : %x \r\n",N_Counter_Latch_Create(A,B,0));
81
-N_Counter_Latch_Create in pll_4113.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :     printf("_ACOUNTER : %d _BCOUNTER : %d \r\n",_ACOUNTER,_BCOUNTER);
82
-N_Counter_Latch_Create in pll_4113.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :     printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);
83
-N_Counter_Latch_Create in pll_4113.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :     printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);
84
-N_Counter_Latch_Create in pll_4113.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :     printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);
85
-N_Counter_Latch_Create in pll_4113.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :     printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);
86
-N_Counter_Latch_Create in pll_4113.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :     printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);
87
-ADF4113_Module_Ctrl in pll_4113.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :             printf("1");
88
-ADF4113_Module_Ctrl in pll_4113.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :             printf("0");
89
-ADF4113_Module_Ctrl in pll_4113.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :      printf("\r\n");
90
-ADF4113_Module_Ctrl in pll_4113.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :             printf("1");
91
-ADF4113_Module_Ctrl in pll_4113.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :             printf("0");
92
-ADF4113_Module_Ctrl in pll_4113.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :         printf("\r\n");
93
-ADF4113_Module_Ctrl in pll_4113.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :             printf("1");
94
-ADF4113_Module_Ctrl in pll_4113.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :             printf("0");            
95
-ADF4113_Module_Ctrl in pll_4113.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :         printf("\r\n");
96
-HAL_UART_RxCpltCallback in uart.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) : //    printf("Function : %s : \r\n",__func__);
97
-GetDataFromUartQueue in uart.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :     printf("%02x ",*(pQueue->Buffer + pQueue->tail)) ;
98
-GetDataFromUartQueue in uart.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) : //        printf("data cnt zero !!!  \r\n");
99
-GetDataFromUartQueue in uart.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :                 printf("%02x ",uart_buf[i]);
100
-RF_Data_Check in zig_operate.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) : //        printf("Recv CRC Value : \"%d\"\r\n Create CRC Value : \"%d\"   \r\n",data_buf[data_buf[Crcindex]],STH30_CreateCrc(&data_buf[Type], data_buf[Length]));
101
-RF_Data_Check in zig_operate.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) : //    printf("CRC Result : \"%d\"   \r\n",ret);
102
-RF_Status_Get in zig_operate.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) : //    printf("\r\nYJ2 : Prev_data[INDEX_DET_1_8G_DL_IN_L ] : %x\r\n",Prev_data[INDEX_DET_1_8G_DL_IN_L]);            
103
-RF_Status_Get in zig_operate.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) : //    printf("\r\nYJ : %x",ADCvalue[0]);
104
-RF_Status_Get in zig_operate.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) : //    printf("\r\n");
105
-RF_Status_Ack in zig_operate.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) : //    printf("\r\nYJ2 : Prev_data[INDEX_DET_1_8G_DL_IN_L ] : %x\r\n",Prev_data[INDEX_DET_1_8G_DL_IN_L]);            
106
-RF_Status_Ack in zig_operate.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) : //    printf("\r\nYJ : %x",ADCvalue[0]);
107
-RF_Status_Ack in zig_operate.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) : //    printf("\r\n");
108
-RF_Operate in zig_operate.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) : //    printf("Prev_data[INDEX_ATT_1_8G_DL1]  : %x  data_buf[INDEX_ATT_1_8G_DL1] : %x\r\n",Prev_data[INDEX_ATT_1_8G_DL1],data_buf[INDEX_ATT_1_8G_DL1]);
109
-RF_Operate in zig_operate.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) : //        printf("data_buf[INDEX_PLL_1_8G_DL_H] : %x \r\n",data_buf[INDEX_PLL_1_8G_DL_H]);
110
-RF_Operate in zig_operate.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) : //        printf("data_buf[INDEX_PLL_1_8G_DL_L] : %x\r\n",data_buf[INDEX_PLL_1_8G_DL_L]);
111
-RF_Operate in zig_operate.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) : //        printf("data_buf[INDEX_PLL_1_8G_UL_H] : %x \r\n",data_buf[INDEX_PLL_1_8G_UL_H]);
112
-RF_Operate in zig_operate.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) : //        printf("data_buf[INDEX_PLL_1_8G_UL_L] : %x\r\n",data_buf[INDEX_PLL_1_8G_UL_L]);
113
-RF_Operate in zig_operate.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) : //        printf("data_buf[INDEX_PLL_2_1G_DL_H] : %x \r\n",data_buf[INDEX_PLL_2_1G_DL_H]);
114
-RF_Operate in zig_operate.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) : //        printf("data_buf[INDEX_PLL_2_1G_DL_L] : %x\r\n",data_buf[INDEX_PLL_2_1G_DL_L]);
115
-RF_Operate in zig_operate.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) : //        printf("data_buf[INDEX_PLL_2_1G_UL_H] : %x \r\n",data_buf[INDEX_PLL_2_1G_UL_H]);
116
-RF_Operate in zig_operate.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) : //        printf("data_buf[INDEX_PLL_2_1G_UL_L] : %x\r\n",data_buf[INDEX_PLL_2_1G_UL_L]);
117
-RF_Operate in zig_operate.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) : //        printf("POWER : %d \r\n",Prev_data[INDEX_PLL_ON_OFF_3_5G_H]);
118
-RF_Operate in zig_operate.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) : //            printf("PLL CTRL START !! \r\n");
119
-RF_Operate in zig_operate.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) : //        printf("POWER : %d \r\n",Prev_data[INDEX_PLL_ON_OFF_3_5G_L]);        
120
-RF_Operate in zig_operate.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) : //            printf("PLL CTRL START !! \r\n");
121
-RF_Operate in zig_operate.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) : //        printf("Prev_data[INDEX_DAC_VCtrl_C_H] : %x \r\n",Prev_data[INDEX_DAC_VCtrl_C_H]);
122
-RF_Operate in zig_operate.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) : //        printf("Prev_data[INDEX_DAC_VCtrl_C_L] : %x \r\n",Prev_data[INDEX_DAC_VCtrl_C_L]);
123
-RF_Operate in zig_operate.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) : //        printf("DAC CTRL START \r\n");
124
-RF_Operate in zig_operate.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) : //        printf("DAC Change\r\n");
125
-RF_Ctrl_Main in zig_operate.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :             printf("%02x ",data_buf[i]);
126
-RF_Ctrl_Main in zig_operate.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :         printf("Reset Start \r\n");
127
-RF_Ctrl_Main in zig_operate.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :     printf("TYPE_BLUECELL_SET : ");
128
-RF_Ctrl_Main in zig_operate.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :         printf("%02x ",data_buf[i]);
129
-RF_Ctrl_Main in zig_operate.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :         printf("\r\nTYPE_BLUECELL_GET : \r\n");
130
-RF_Ctrl_Main in zig_operate.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) : //        printf("\r\nFLASH Write\r\n");
131
-RF_Ctrl_Main in zig_operate.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :             printf("Function : %s   LINE : %d    type : %d \r\n",__func__,__LINE__,type);
1
+---- UART_HandleTypeDef huart1; Matches (3 in 3 files) ----
2
+main.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) line 50 : UART_HandleTypeDef huart1;
3
+stm32f1xx_it.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) line 63 : extern UART_HandleTypeDef huart1;
4
+uart.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Inc) line 28 : extern UART_HandleTypeDef huart1;

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insight/STM32F103_ATTEN_PLL_Zig.si4project/STM32F103_ATTEN_PLL_Zig.siwork


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_adc_ex.c.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_gpio.c.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_BDA4601.h.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_PE43711.h.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_adf4153.h.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_flash.h.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_includes.h.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_main.h.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_pll_4113.h.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_zig_operate.h.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_AD5318.c.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_BDA4601.c.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_PE43711.c.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_adf4153.c.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_flash.c.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_includes.c.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_main.c.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_pll_4113.c.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_uart.c.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_zig_operate.c.sisc