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ATTEN Initialize / PLL 상위 비트하위비트 둘중 하나만 변경되었을때 zig 동작하도록 수정

YJ vor 5 Jahren
Ursprung
Commit
eabd2f4d9b

BIN
Debug/STM32F103_ATTEN_PLL_Zig.elf


Datei-Diff unterdrückt, da er zu groß ist
+ 1349 - 1322
Debug/STM32F103_ATTEN_PLL_Zig.hex


Datei-Diff unterdrückt, da er zu groß ist
+ 7654 - 7456
Debug/STM32F103_ATTEN_PLL_Zig.list


Datei-Diff unterdrückt, da er zu groß ist
+ 440 - 440
Debug/STM32F103_ATTEN_PLL_Zig.map


BIN
Debug/Src/BDA4601.o


+ 1 - 1
Debug/Src/BDA4601.su

@@ -1,2 +1,2 @@
1 1
 BDA4601.c:127:6:BDA4601_atten_ctrl	40	static
2
-BDA4601.c:108:6:BDA4601_Test	24	static
2
+BDA4601.c:108:6:BDA4601_Initialize	24	static

+ 2 - 2
Debug/Src/main.su

@@ -1,5 +1,5 @@
1 1
 main.c:83:6:HAL_TIM_PeriodElapsedCallback	0	static
2 2
 main.c:92:5:_write	8	static
3
-main.c:171:6:SystemClock_Config	96	static
3
+main.c:172:6:SystemClock_Config	96	static
4 4
 main.c:104:5:main	56	static
5
-main.c:613:6:Error_Handler	0	static
5
+main.c:614:6:Error_Handler	0	static

+ 2 - 0
Inc/BDA4601.h

@@ -34,6 +34,8 @@ BDA4601_st BDA4601_2_1G_UL3;
34 34
 BDA4601_st BDA4601_2_1G_UL4;    
35 35
 
36 36
 void BDA4601_atten_ctrl(BDA4601_st type ,uint8_t data);
37
+void BDA4601_Initialize(void);
38
+
37 39
 uint8_t BDA4601_Data_Calc(uint8_t val);
38 40
 
39 41
 //void BDA4601_Test(void);

+ 1 - 1
Src/BDA4601.c

@@ -105,7 +105,7 @@ BDA4601_st BDA4601_2_1G_UL4= {
105 105
 
106 106
 
107 107
 
108
-void BDA4601_Test(void){
108
+void BDA4601_Initialize(void){
109 109
     BDA4601_atten_ctrl(BDA4601_1_8G_DL1,0);           
110 110
     BDA4601_atten_ctrl(BDA4601_1_8G_DL2,0);           
111 111
 

+ 2 - 1
Src/main.c

@@ -136,7 +136,7 @@ int main(void)
136 136
   MX_NVIC_Init();
137 137
   /* USER CODE BEGIN 2 */
138 138
   InitUartQueue(&TerminalQueue);
139
-  PE43711_PinInit();
139
+//  PE43711_PinInit();
140 140
   Power_ON_OFF_Initialize();  
141 141
   Path_Init();
142 142
   while(!(HAL_ADCEx_Calibration_Start(&hadc1)==HAL_OK));
@@ -144,6 +144,7 @@ int main(void)
144 144
   ADF4153_Initialize();
145 145
   ADF4113_Initialize();
146 146
   PE43711_PinInit();
147
+  BDA4601_Initialize();
147 148
   ATTEN_PLL_PATH_Initialize();
148 149
   HAL_ADC_Start_DMA(&hadc1, (uint32_t*)ADCvalue, 14);
149 150
   /* USER CODE END 2 */

+ 45 - 17
Src/zig_operate.c

@@ -320,51 +320,70 @@ void RF_Operate(uint8_t* data_buf){
320 320
         PE43711_ALL_atten_ctrl(ALL_ATT_3_5G);
321 321
     }
322 322
     if((Prev_data[INDEX_PLL_1_8G_DL_H] != data_buf[INDEX_PLL_1_8G_DL_H])
323
-        && (Prev_data[INDEX_PLL_1_8G_DL_L] != data_buf[INDEX_PLL_1_8G_DL_L])
323
+        || (Prev_data[INDEX_PLL_1_8G_DL_L] != data_buf[INDEX_PLL_1_8G_DL_L])
324 324
     ){
325 325
         Prev_data[INDEX_PLL_1_8G_DL_H] = data_buf[INDEX_PLL_1_8G_DL_H];
326 326
         Prev_data[INDEX_PLL_1_8G_DL_L] = data_buf[INDEX_PLL_1_8G_DL_L];
327
+//        printf("data_buf[INDEX_PLL_1_8G_DL_H] : %x \r\n",data_buf[INDEX_PLL_1_8G_DL_H]);
328
+//        printf("data_buf[INDEX_PLL_1_8G_DL_L] : %x\r\n",data_buf[INDEX_PLL_1_8G_DL_L]);
327 329
         temp_val = (data_buf[INDEX_PLL_1_8G_DL_H] << 8) | (data_buf[INDEX_PLL_1_8G_DL_L]);
328
-        ADF4113_Module_Ctrl(ADF4113_1_8G_DL,0x410,halSynSetFreq((temp_val * 1000000) / 10 ),0x9F8092);
330
+        ADF4113_Module_Ctrl(ADF4113_1_8G_DL,0x410,halSynSetFreq(temp_val * 100000),0x9F8092);
331
+        HAL_Delay(1);
332
+        BDA4601_atten_ctrl(BDA4601_1_8G_DL1,(data_buf[INDEX_ATT_1_8G_DL1]));
329 333
     }
330 334
     if((Prev_data[INDEX_PLL_1_8G_UL_H] != data_buf[INDEX_PLL_1_8G_UL_H])
331
-        && (Prev_data[INDEX_PLL_1_8G_UL_L] != data_buf[INDEX_PLL_1_8G_UL_L])){
335
+        || (Prev_data[INDEX_PLL_1_8G_UL_L] != data_buf[INDEX_PLL_1_8G_UL_L])){
332 336
         temp_val = (data_buf[INDEX_PLL_1_8G_UL_H] << 8) | (data_buf[INDEX_PLL_1_8G_UL_L]);
337
+//        printf("data_buf[INDEX_PLL_1_8G_UL_H] : %x \r\n",data_buf[INDEX_PLL_1_8G_UL_H]);
338
+//        printf("data_buf[INDEX_PLL_1_8G_UL_L] : %x\r\n",data_buf[INDEX_PLL_1_8G_UL_L]);
333 339
         Prev_data[INDEX_PLL_1_8G_UL_H] = data_buf[INDEX_PLL_1_8G_UL_H];
334 340
         Prev_data[INDEX_PLL_1_8G_UL_L] = data_buf[INDEX_PLL_1_8G_UL_L];
335 341
 //         ADF4113_Module_Ctrl(ADF4113_1_8G_UL,0x000410,0x038D31,0x9f8092);
336
-         ADF4113_Module_Ctrl(ADF4113_1_8G_UL,0x410,halSynSetFreq((temp_val * 1000000) / 10),0x9F8092);
342
+         ADF4113_Module_Ctrl(ADF4113_1_8G_UL,0x410,halSynSetFreq(temp_val * 100000),0x9F8092);
343
+        HAL_Delay(1);
344
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL1,(data_buf[INDEX_ATT_1_8G_UL1]));
337 345
     }
338 346
     if((Prev_data[INDEX_PLL_2_1G_DL_H] != data_buf[INDEX_PLL_2_1G_DL_H])
339
-        && (Prev_data[INDEX_PLL_2_1G_DL_L] != data_buf[INDEX_PLL_2_1G_DL_L])){
347
+        || (Prev_data[INDEX_PLL_2_1G_DL_L] != data_buf[INDEX_PLL_2_1G_DL_L])){
340 348
         temp_val = ((data_buf[INDEX_PLL_2_1G_DL_H] << 8) | (data_buf[INDEX_PLL_2_1G_DL_L]));
349
+//        printf("data_buf[INDEX_PLL_2_1G_DL_H] : %x \r\n",data_buf[INDEX_PLL_2_1G_DL_H]);
350
+//        printf("data_buf[INDEX_PLL_2_1G_DL_L] : %x\r\n",data_buf[INDEX_PLL_2_1G_DL_L]);
341 351
         Prev_data[INDEX_PLL_2_1G_DL_H] = data_buf[INDEX_PLL_2_1G_DL_H];
342 352
         Prev_data[INDEX_PLL_2_1G_DL_L] = data_buf[INDEX_PLL_2_1G_DL_L];        
343 353
 //         ADF4113_Module_Ctrl(ADF4113_2_1G_DL,0x410,0x4DE71,0x9F8092);
344
-        ADF4113_Module_Ctrl(ADF4113_2_1G_DL,0x410,halSynSetFreq((temp_val * 1000000) / 10),0x9F8092);
354
+        ADF4113_Module_Ctrl(ADF4113_2_1G_DL,0x410,halSynSetFreq(temp_val * 100000),0x9F8092);
355
+      HAL_Delay(1);
356
+      BDA4601_atten_ctrl(BDA4601_2_1G_DL1,(data_buf[INDEX_ATT_2_1G_DL1]));
345 357
     }
346 358
     if((Prev_data[INDEX_PLL_2_1G_UL_H] != data_buf[INDEX_PLL_2_1G_UL_H])
347
-        && (Prev_data[INDEX_PLL_2_1G_UL_L] != data_buf[INDEX_PLL_2_1G_UL_L])){
359
+        || (Prev_data[INDEX_PLL_2_1G_UL_L] != data_buf[INDEX_PLL_2_1G_UL_L])){
348 360
         Prev_data[INDEX_PLL_2_1G_UL_H] = data_buf[INDEX_PLL_2_1G_UL_H];
349
-        Prev_data[INDEX_PLL_2_1G_UL_L] = data_buf[INDEX_PLL_2_1G_UL_L];          
361
+        Prev_data[INDEX_PLL_2_1G_UL_L] = data_buf[INDEX_PLL_2_1G_UL_L];    
362
+//        printf("data_buf[INDEX_PLL_2_1G_UL_H] : %x \r\n",data_buf[INDEX_PLL_2_1G_UL_H]);
363
+//        printf("data_buf[INDEX_PLL_2_1G_UL_L] : %x\r\n",data_buf[INDEX_PLL_2_1G_UL_L]);
350 364
         temp_val = (data_buf[INDEX_PLL_2_1G_UL_H] << 8) | (data_buf[INDEX_PLL_2_1G_UL_L]);
351 365
 //        ADF4113_Module_Ctrl(ADF4113_2_1G_UL,0x000410,0x59A31,0x9f8092);
352
-        ADF4113_Module_Ctrl(ADF4113_2_1G_UL,0x410,halSynSetFreq((temp_val * 1000000) / 10),0x9F8092);
366
+        ADF4113_Module_Ctrl(ADF4113_2_1G_UL,0x410,halSynSetFreq(temp_val * 100000),0x9F8092);
367
+      HAL_Delay(1);
368
+      BDA4601_atten_ctrl(BDA4601_2_1G_DL1,(data_buf[INDEX_ATT_2_1G_UL1]));
369
+
353 370
 
354 371
     }
355 372
     if((Prev_data[INDEX_PLL_3_5G_DL_H] != data_buf[INDEX_PLL_3_5G_DL_H])
356
-        && (Prev_data[INDEX_PLL_3_5G_DL_L] != data_buf[INDEX_PLL_3_5G_DL_L])){
373
+        || (Prev_data[INDEX_PLL_3_5G_DL_L] != data_buf[INDEX_PLL_3_5G_DL_L])){
357 374
         Prev_data[INDEX_PLL_3_5G_DL_H] = data_buf[INDEX_PLL_3_5G_DL_H];
358 375
         Prev_data[INDEX_PLL_3_5G_DL_L] = data_buf[INDEX_PLL_3_5G_DL_L];
359 376
         temp_val = (data_buf[INDEX_PLL_3_5G_DL_H] << 8) | (data_buf[INDEX_PLL_3_5G_DL_L]);
377
+//        temp_reg = ADF4153_Freq_Calc(temp_val  * 100000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
360 378
         temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
361 379
         ADF4153_Module_Ctrl(Pll_3_5_L,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
362 380
     }
363 381
     if((Prev_data[INDEX_PLL_3_5G_UL_H] != data_buf[INDEX_PLL_3_5G_UL_H])
364
-        && (Prev_data[INDEX_PLL_3_5G_UL_L] != data_buf[INDEX_PLL_3_5G_UL_L])){
382
+        || (Prev_data[INDEX_PLL_3_5G_UL_L] != data_buf[INDEX_PLL_3_5G_UL_L])){
365 383
         Prev_data[INDEX_PLL_3_5G_UL_H] = data_buf[INDEX_PLL_3_5G_UL_H];
366 384
         Prev_data[INDEX_PLL_3_5G_UL_L] = data_buf[INDEX_PLL_3_5G_UL_L];
367 385
         temp_val = (data_buf[INDEX_PLL_3_5G_UL_H] << 8) | (data_buf[INDEX_PLL_3_5G_UL_L]);
386
+//        temp_reg = ADF4153_Freq_Calc(temp_val  * 100000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
368 387
         temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
369 388
         ADF4153_Module_Ctrl(Pll_3_5_H,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
370 389
 
@@ -508,23 +527,32 @@ void RF_Operate(uint8_t* data_buf){
508 527
     if(Prev_data[INDEX_PLL_ON_OFF_3_5G_H] != data_buf[INDEX_PLL_ON_OFF_3_5G_H]){
509 528
         Power_ON_OFF_Ctrl(INDEX_PLL_ON_OFF_3_5G_H,data_buf[INDEX_PLL_ON_OFF_3_5G_H]);
510 529
         Prev_data[INDEX_PLL_ON_OFF_3_5G_H] = data_buf[INDEX_PLL_ON_OFF_3_5G_H];
511
-        HAL_Delay(10);
512
-        printf("POWER : %d \r\n",Prev_data[INDEX_PLL_ON_OFF_3_5G_H]);
530
+        HAL_Delay(1);
531
+//        printf("POWER : %d \r\n",Prev_data[INDEX_PLL_ON_OFF_3_5G_H]);
513 532
         if(data_buf[INDEX_PLL_ON_OFF_3_5G_H]){
514
-            printf("PLL CTRL START !! \r\n");
533
+//            printf("PLL CTRL START !! \r\n");
534
+//            temp_val = (Prev_data[INDEX_PLL_3_5G_DL_H] << 8) | (Prev_data[INDEX_PLL_3_5G_DL_L]);
535
+//            temp_reg = ADF4153_Freq_Calc(temp_val  * 100000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
536
+
515 537
             temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
516 538
             ADF4153_Module_Ctrl(Pll_3_5_H,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
539
+            PE43711_ALL_atten_ctrl(ALL_ATT_3_5G);
517 540
         }
518 541
     }
519 542
     if(Prev_data[INDEX_PLL_ON_OFF_3_5G_L] != data_buf[INDEX_PLL_ON_OFF_3_5G_L]){
520 543
         Power_ON_OFF_Ctrl(INDEX_PLL_ON_OFF_3_5G_L,data_buf[INDEX_PLL_ON_OFF_3_5G_L]);
521 544
         Prev_data[INDEX_PLL_ON_OFF_3_5G_L] = data_buf[INDEX_PLL_ON_OFF_3_5G_L];
522
-        HAL_Delay(10);
523
-        printf("POWER : %d \r\n",Prev_data[INDEX_PLL_ON_OFF_3_5G_L]);        
545
+        HAL_Delay(1);
546
+//        printf("POWER : %d \r\n",Prev_data[INDEX_PLL_ON_OFF_3_5G_L]);        
524 547
         if(data_buf[INDEX_PLL_ON_OFF_3_5G_L]){
525
-            printf("PLL CTRL START !! \r\n");
548
+//            printf("PLL CTRL START !! \r\n");
549
+//            temp_val = (Prev_data[INDEX_PLL_3_5G_UL_H] << 8) | (Prev_data[INDEX_PLL_3_5G_UL_L]);
550
+//            temp_reg = ADF4153_Freq_Calc(temp_val  * 100000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
551
+//                    temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
552
+//                    ADF4153_Module_Ctrl(Pll_3_5_H,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
526 553
             temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);            
527 554
             ADF4153_Module_Ctrl(Pll_3_5_L,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
555
+            PE43711_ALL_atten_ctrl(ALL_ATT_3_5G);
528 556
         }
529 557
     }
530 558
 

+ 41 - 0
insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/BDA4601(2527).h

@@ -0,0 +1,41 @@
1
+/*
2
+ * BDA4601.h
3
+ *
4
+ *  Created on: 2019. 6. 28.
5
+ *      Author: parkyj
6
+ */
7
+
8
+#ifndef BDA4601_H_
9
+#define BDA4601_H_
10
+#include "main.h"
11
+typedef struct{
12
+   GPIO_TypeDef *CLK_PORT;
13
+   uint16_t CLK_PIN;
14
+
15
+   GPIO_TypeDef *SERIAL_IN_PORT;
16
+   uint16_t SERIAL_IN_PIN;;
17
+
18
+   GPIO_TypeDef *LE_PORT;
19
+   uint16_t LE_PIN;
20
+
21
+}BDA4601_st;
22
+BDA4601_st BDA4601_1_8G_DL1;
23
+BDA4601_st BDA4601_1_8G_DL2;
24
+BDA4601_st BDA4601_1_8G_UL1;
25
+BDA4601_st BDA4601_1_8G_UL2;
26
+BDA4601_st BDA4601_1_8G_UL3;    
27
+BDA4601_st BDA4601_1_8G_UL4;          
28
+
29
+BDA4601_st BDA4601_2_1G_DL1;
30
+BDA4601_st BDA4601_2_1G_DL2;           
31
+BDA4601_st BDA4601_2_1G_UL1;           
32
+BDA4601_st BDA4601_2_1G_UL2;           
33
+BDA4601_st BDA4601_2_1G_UL3;           
34
+BDA4601_st BDA4601_2_1G_UL4;    
35
+
36
+void BDA4601_atten_ctrl(BDA4601_st type ,uint8_t data);
37
+uint8_t BDA4601_Data_Calc(uint8_t val);
38
+
39
+//void BDA4601_Test(void);
40
+
41
+#endif /* BDA4601_H_ */

+ 161 - 0
insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/BDA4601(5295).c

@@ -0,0 +1,161 @@
1
+/*
2
+ * BDA4601.c
3
+ *
4
+ *  Created on: 2019. 6. 28.
5
+ *      Author: parkyj
6
+ */
7
+#include "BDA4601.h"
8
+BDA4601_st BDA4601_1_8G_DL1 = {
9
+    ATT_CLK_GPIO_Port,
10
+    ATT_CLK_Pin,
11
+    ATT_DATA_GPIO_Port,
12
+    ATT_DATA_Pin,
13
+    ATT_EN_1_8G_DL1_GPIO_Port,
14
+    ATT_EN_1_8G_DL1_Pin,
15
+};
16
+BDA4601_st BDA4601_1_8G_DL2 = {
17
+   ATT_CLK_GPIO_Port,
18
+   ATT_CLK_Pin,
19
+   ATT_DATA_GPIO_Port,
20
+   ATT_DATA_Pin,
21
+   ATT_EN_1_8G_DL2_GPIO_Port,
22
+   ATT_EN_1_8G_DL2_Pin,
23
+};
24
+BDA4601_st BDA4601_1_8G_UL1 = {
25
+    ATT_CLK_GPIO_Port,
26
+    ATT_CLK_Pin,
27
+    ATT_DATA_GPIO_Port,
28
+    ATT_DATA_Pin,
29
+    ATT_EN_1_8G_UL1_GPIO_Port,
30
+    ATT_EN_1_8G_UL1_Pin,
31
+};
32
+BDA4601_st BDA4601_1_8G_UL2 = {
33
+   ATT_CLK_GPIO_Port,
34
+   ATT_CLK_Pin,
35
+   ATT_DATA_GPIO_Port,
36
+   ATT_DATA_Pin,
37
+   ATT_EN_1_8G_UL2_GPIO_Port,
38
+   ATT_EN_1_8G_UL2_Pin,
39
+};
40
+BDA4601_st BDA4601_1_8G_UL3 = {
41
+   ATT_CLK_GPIO_Port,
42
+   ATT_CLK_Pin,
43
+   ATT_DATA_GPIO_Port,
44
+   ATT_DATA_Pin,
45
+   ATT_EN_1_8G_UL1_GPIO_Port,
46
+   ATT_EN_1_8G_UL1_Pin,
47
+};    
48
+BDA4601_st BDA4601_1_8G_UL4 = {
49
+   ATT_CLK_GPIO_Port,
50
+   ATT_CLK_Pin,
51
+   ATT_DATA_GPIO_Port,
52
+   ATT_DATA_Pin,
53
+   ATT_EN_1_8G_UL4_GPIO_Port,
54
+   ATT_EN_1_8G_UL4_Pin,
55
+};          
56
+
57
+BDA4601_st BDA4601_2_1G_DL1= {
58
+    ATT_CLK_GPIO_Port,
59
+    ATT_CLK_Pin,
60
+    ATT_DATA_GPIO_Port,
61
+    ATT_DATA_Pin,
62
+    ATT_EN_2_1G_DL1_GPIO_Port,
63
+    ATT_EN_2_1G_DL1_Pin,
64
+};           ;
65
+BDA4601_st BDA4601_2_1G_DL2= {
66
+    ATT_CLK_GPIO_Port,
67
+    ATT_CLK_Pin,
68
+    ATT_DATA_GPIO_Port,
69
+    ATT_DATA_Pin,
70
+    ATT_EN_2_1G_DL2_GPIO_Port,
71
+    ATT_EN_2_1G_DL2_Pin,
72
+};           
73
+BDA4601_st BDA4601_2_1G_UL1= {
74
+    ATT_CLK_GPIO_Port,
75
+    ATT_CLK_Pin,
76
+    ATT_DATA_GPIO_Port,
77
+    ATT_DATA_Pin,
78
+    ATT_EN_2_1G_UL1_GPIO_Port,
79
+    ATT_EN_2_1G_UL1_Pin,
80
+};           
81
+BDA4601_st BDA4601_2_1G_UL2= {
82
+    ATT_CLK_GPIO_Port,
83
+    ATT_CLK_Pin,
84
+    ATT_DATA_GPIO_Port,
85
+    ATT_DATA_Pin,
86
+    ATT_EN_2_1G_UL2_GPIO_Port,
87
+    ATT_EN_2_1G_UL2_Pin,
88
+};           
89
+BDA4601_st BDA4601_2_1G_UL3= {
90
+    ATT_CLK_GPIO_Port,
91
+    ATT_CLK_Pin,
92
+    ATT_DATA_GPIO_Port,
93
+    ATT_DATA_Pin,
94
+    ATT_EN_2_1G_UL3_GPIO_Port,
95
+    ATT_EN_2_1G_UL3_Pin,
96
+};           
97
+BDA4601_st BDA4601_2_1G_UL4= {
98
+    ATT_CLK_GPIO_Port,
99
+    ATT_CLK_Pin,
100
+    ATT_DATA_GPIO_Port,
101
+    ATT_DATA_Pin,
102
+    ATT_EN_2_1G_UL4_GPIO_Port,
103
+    ATT_EN_2_1G_UL4_Pin,
104
+};    
105
+
106
+
107
+
108
+void BDA4601_Test(void){
109
+    BDA4601_atten_ctrl(BDA4601_1_8G_DL1,0);           
110
+    BDA4601_atten_ctrl(BDA4601_1_8G_DL2,0);           
111
+
112
+    BDA4601_atten_ctrl(BDA4601_1_8G_UL1,0);           
113
+    BDA4601_atten_ctrl(BDA4601_1_8G_UL2,0);           
114
+    BDA4601_atten_ctrl(BDA4601_1_8G_UL3,0);           
115
+    BDA4601_atten_ctrl(BDA4601_1_8G_UL4,0);           
116
+
117
+    BDA4601_atten_ctrl(BDA4601_2_1G_DL1,0);           
118
+    BDA4601_atten_ctrl(BDA4601_2_1G_DL2,0);           
119
+
120
+    BDA4601_atten_ctrl(BDA4601_2_1G_UL1,0);           
121
+    BDA4601_atten_ctrl(BDA4601_2_1G_UL2,0);
122
+    BDA4601_atten_ctrl(BDA4601_2_1G_UL3,0);           
123
+    BDA4601_atten_ctrl(BDA4601_2_1G_UL4,0);               
124
+}
125
+
126
+
127
+void BDA4601_atten_ctrl(BDA4601_st BDA ,uint8_t data){
128
+    uint8_t i = 0;
129
+    uint8_t temp = 0;
130
+#ifdef DEBUG_PRINT
131
+#ifdef DEBUG_PRINT
132
+    printf("BDA4601_atten_ctrl : %x \r\n",data);
133
+#endif /* DEBUG_PRINT */
134
+#endif /* DEBUG_PRINT */
135
+    data = 4 * data;
136
+    temp = (uint8_t)data;
137
+    HAL_GPIO_WritePin(BDA.LE_PORT,BDA.LE_PIN,GPIO_PIN_RESET);
138
+    HAL_Delay(1);
139
+    for(i = 0; i < 8; i++){
140
+        if((uint8_t)temp & 0x01){
141
+           HAL_GPIO_WritePin(BDA.SERIAL_IN_PORT,BDA.SERIAL_IN_PIN,GPIO_PIN_SET);//DATA
142
+        }
143
+           else{
144
+           HAL_GPIO_WritePin(BDA.SERIAL_IN_PORT,BDA.SERIAL_IN_PIN,GPIO_PIN_RESET);//DATA
145
+           }
146
+
147
+        HAL_GPIO_WritePin(BDA.CLK_PORT,BDA.CLK_PIN,GPIO_PIN_SET);//CLOCK
148
+        HAL_Delay(1);
149
+        HAL_GPIO_WritePin(BDA.CLK_PORT,BDA.CLK_PIN,GPIO_PIN_RESET);//CLOCK
150
+        HAL_Delay(1);
151
+        temp >>= 1;
152
+    }
153
+    HAL_GPIO_WritePin(BDA.CLK_PORT,BDA.CLK_PIN,GPIO_PIN_RESET);//CLOCK
154
+    HAL_GPIO_WritePin(BDA.SERIAL_IN_PORT,GPIO_PIN_15,GPIO_PIN_RESET);//DATA
155
+    HAL_Delay(5);
156
+    HAL_GPIO_WritePin(BDA.LE_PORT,BDA.LE_PIN,GPIO_PIN_SET);//LE
157
+    HAL_Delay(1);
158
+    HAL_GPIO_WritePin(BDA.LE_PORT,BDA.LE_PIN,GPIO_PIN_RESET);
159
+}
160
+
161
+

+ 638 - 0
insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/main(1810).c

@@ -0,0 +1,638 @@
1
+/* USER CODE BEGIN Header */
2
+/**
3
+  ******************************************************************************
4
+  * @file           : main.c
5
+  * @brief          : Main program body
6
+  ******************************************************************************
7
+  * @attention
8
+  *
9
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
10
+  * All rights reserved.</center></h2>
11
+  *
12
+  * This software component is licensed by ST under BSD 3-Clause license,
13
+  * the "License"; You may not use this file except in compliance with the
14
+  * License. You may obtain a copy of the License at:
15
+  *                        opensource.org/licenses/BSD-3-Clause
16
+  *
17
+  ******************************************************************************
18
+  */
19
+/* USER CODE END Header */
20
+
21
+/* Includes ------------------------------------------------------------------*/
22
+#include "main.h"
23
+
24
+/* Private includes ----------------------------------------------------------*/
25
+/* USER CODE BEGIN Includes */
26
+
27
+/* USER CODE END Includes */
28
+
29
+/* Private typedef -----------------------------------------------------------*/
30
+/* USER CODE BEGIN PTD */
31
+
32
+/* USER CODE END PTD */
33
+
34
+/* Private define ------------------------------------------------------------*/
35
+/* USER CODE BEGIN PD */
36
+
37
+/* USER CODE END PD */
38
+
39
+/* Private macro -------------------------------------------------------------*/
40
+/* USER CODE BEGIN PM */
41
+
42
+/* USER CODE END PM */
43
+
44
+/* Private variables ---------------------------------------------------------*/
45
+ADC_HandleTypeDef hadc1;
46
+DMA_HandleTypeDef hdma_adc1;
47
+
48
+TIM_HandleTypeDef htim6;
49
+
50
+UART_HandleTypeDef huart1;
51
+DMA_HandleTypeDef hdma_usart1_rx;
52
+DMA_HandleTypeDef hdma_usart1_tx;
53
+
54
+/* USER CODE BEGIN PV */
55
+volatile uint32_t AdcTimerCnt = 0;
56
+volatile uint32_t LedTimerCnt = 0;
57
+volatile uint32_t UartRxTimerCnt = 0;
58
+volatile uint32_t LDTimerCnt = 0;
59
+
60
+extern PLL_Setting_st Pll_3_5_H;
61
+extern PLL_Setting_st Pll_3_5_L;
62
+
63
+//volatile uint32_t UartTxTimerCnt = 0;
64
+
65
+/* USER CODE END PV */
66
+
67
+/* Private function prototypes -----------------------------------------------*/
68
+void SystemClock_Config(void);
69
+static void MX_GPIO_Init(void);
70
+static void MX_DMA_Init(void);
71
+static void MX_ADC1_Init(void);
72
+static void MX_USART1_UART_Init(void);
73
+static void MX_TIM6_Init(void);
74
+static void MX_NVIC_Init(void);
75
+/* USER CODE BEGIN PFP */
76
+void ADF4153_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2,uint32_t R3);
77
+/* USER CODE END PFP */
78
+
79
+/* Private user code ---------------------------------------------------------*/
80
+/* USER CODE BEGIN 0 */
81
+
82
+
83
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
84
+{
85
+    if(htim->Instance == TIM6){
86
+        UartRxTimerCnt++;
87
+        LedTimerCnt++;
88
+        AdcTimerCnt++;
89
+        LDTimerCnt++;
90
+    }
91
+} 
92
+int _write (int file, uint8_t *ptr, uint16_t len)
93
+{
94
+    HAL_UART_Transmit(&huart1, ptr, len,10);
95
+    return len;
96
+}
97
+
98
+/* USER CODE END 0 */
99
+
100
+/**
101
+  * @brief  The application entry point.
102
+  * @retval int
103
+  */
104
+int main(void)
105
+{
106
+  /* USER CODE BEGIN 1 */
107
+ 
108
+
109
+  /* USER CODE END 1 */
110
+  
111
+
112
+  /* MCU Configuration--------------------------------------------------------*/
113
+
114
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
115
+  HAL_Init();
116
+
117
+  /* USER CODE BEGIN Init */
118
+
119
+  /* USER CODE END Init */
120
+
121
+  /* Configure the system clock */
122
+  SystemClock_Config();
123
+
124
+  /* USER CODE BEGIN SysInit */
125
+
126
+  /* USER CODE END SysInit */
127
+
128
+  /* Initialize all configured peripherals */
129
+  MX_GPIO_Init();
130
+  MX_DMA_Init();
131
+  MX_ADC1_Init();
132
+  MX_USART1_UART_Init();
133
+  MX_TIM6_Init();
134
+
135
+  /* Initialize interrupts */
136
+  MX_NVIC_Init();
137
+  /* USER CODE BEGIN 2 */
138
+  InitUartQueue(&TerminalQueue);
139
+  PE43711_PinInit();
140
+  Power_ON_OFF_Initialize();  
141
+  Path_Init();
142
+  while(!(HAL_ADCEx_Calibration_Start(&hadc1)==HAL_OK));
143
+  Bluecell_Flash_Read(&Flash_Save_data[INDEX_BLUE_HEADER]);
144
+  ADF4153_Initialize();
145
+  ADF4113_Initialize();
146
+  PE43711_PinInit();
147
+  ATTEN_PLL_PATH_Initialize();
148
+  HAL_ADC_Start_DMA(&hadc1, (uint32_t*)ADCvalue, 14);
149
+  /* USER CODE END 2 */
150
+
151
+  /* Infinite loop */
152
+  /* USER CODE BEGIN WHILE */
153
+  while (1)
154
+  {
155
+//    ADF4113_Check();
156
+//    ADF4153_Check();
157
+    Boot_LED_Toggle();
158
+    Uart_Check();
159
+    ADC_Check();
160
+    /* USER CODE END WHILE */
161
+
162
+    /* USER CODE BEGIN 3 */
163
+  }
164
+  /* USER CODE END 3 */
165
+}
166
+
167
+/**
168
+  * @brief System Clock Configuration
169
+  * @retval None
170
+  */
171
+void SystemClock_Config(void)
172
+{
173
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
174
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
175
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
176
+
177
+  /** Initializes the CPU, AHB and APB busses clocks 
178
+  */
179
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
180
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
181
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
182
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
183
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2;
184
+  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL14;
185
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
186
+  {
187
+    Error_Handler();
188
+  }
189
+  /** Initializes the CPU, AHB and APB busses clocks 
190
+  */
191
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
192
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
193
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
194
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
195
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
196
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
197
+
198
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
199
+  {
200
+    Error_Handler();
201
+  }
202
+  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
203
+  PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV4;
204
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
205
+  {
206
+    Error_Handler();
207
+  }
208
+}
209
+
210
+/**
211
+  * @brief NVIC Configuration.
212
+  * @retval None
213
+  */
214
+static void MX_NVIC_Init(void)
215
+{
216
+  /* USART1_IRQn interrupt configuration */
217
+  HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
218
+  HAL_NVIC_EnableIRQ(USART1_IRQn);
219
+  /* TIM6_IRQn interrupt configuration */
220
+  HAL_NVIC_SetPriority(TIM6_IRQn, 0, 0);
221
+  HAL_NVIC_EnableIRQ(TIM6_IRQn);
222
+  /* DMA1_Channel1_IRQn interrupt configuration */
223
+  HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
224
+  HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
225
+  /* DMA1_Channel4_IRQn interrupt configuration */
226
+  HAL_NVIC_SetPriority(DMA1_Channel4_IRQn, 0, 0);
227
+  HAL_NVIC_EnableIRQ(DMA1_Channel4_IRQn);
228
+  /* DMA1_Channel5_IRQn interrupt configuration */
229
+  HAL_NVIC_SetPriority(DMA1_Channel5_IRQn, 0, 0);
230
+  HAL_NVIC_EnableIRQ(DMA1_Channel5_IRQn);
231
+}
232
+
233
+/**
234
+  * @brief ADC1 Initialization Function
235
+  * @param None
236
+  * @retval None
237
+  */
238
+static void MX_ADC1_Init(void)
239
+{
240
+
241
+  /* USER CODE BEGIN ADC1_Init 0 */
242
+
243
+  /* USER CODE END ADC1_Init 0 */
244
+
245
+  ADC_ChannelConfTypeDef sConfig = {0};
246
+
247
+  /* USER CODE BEGIN ADC1_Init 1 */
248
+
249
+  /* USER CODE END ADC1_Init 1 */
250
+  /** Common config 
251
+  */
252
+  hadc1.Instance = ADC1;
253
+  hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE;
254
+  hadc1.Init.ContinuousConvMode = ENABLE;
255
+  hadc1.Init.DiscontinuousConvMode = DISABLE;
256
+  hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
257
+  hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
258
+  hadc1.Init.NbrOfConversion = 14;
259
+  if (HAL_ADC_Init(&hadc1) != HAL_OK)
260
+  {
261
+    Error_Handler();
262
+  }
263
+  /** Configure Regular Channel 
264
+  */
265
+  sConfig.Channel = ADC_CHANNEL_0;
266
+  sConfig.Rank = ADC_REGULAR_RANK_1;
267
+  sConfig.SamplingTime = ADC_SAMPLETIME_239CYCLES_5;
268
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
269
+  {
270
+    Error_Handler();
271
+  }
272
+  /** Configure Regular Channel 
273
+  */
274
+  sConfig.Channel = ADC_CHANNEL_1;
275
+  sConfig.Rank = ADC_REGULAR_RANK_2;
276
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
277
+  {
278
+    Error_Handler();
279
+  }
280
+  /** Configure Regular Channel 
281
+  */
282
+  sConfig.Channel = ADC_CHANNEL_2;
283
+  sConfig.Rank = ADC_REGULAR_RANK_3;
284
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
285
+  {
286
+    Error_Handler();
287
+  }
288
+  /** Configure Regular Channel 
289
+  */
290
+  sConfig.Channel = ADC_CHANNEL_3;
291
+  sConfig.Rank = ADC_REGULAR_RANK_4;
292
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
293
+  {
294
+    Error_Handler();
295
+  }
296
+  /** Configure Regular Channel 
297
+  */
298
+  sConfig.Channel = ADC_CHANNEL_4;
299
+  sConfig.Rank = ADC_REGULAR_RANK_5;
300
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
301
+  {
302
+    Error_Handler();
303
+  }
304
+  /** Configure Regular Channel 
305
+  */
306
+  sConfig.Channel = ADC_CHANNEL_5;
307
+  sConfig.Rank = ADC_REGULAR_RANK_6;
308
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
309
+  {
310
+    Error_Handler();
311
+  }
312
+  /** Configure Regular Channel 
313
+  */
314
+  sConfig.Channel = ADC_CHANNEL_6;
315
+  sConfig.Rank = ADC_REGULAR_RANK_7;
316
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
317
+  {
318
+    Error_Handler();
319
+  }
320
+  /** Configure Regular Channel 
321
+  */
322
+  sConfig.Channel = ADC_CHANNEL_7;
323
+  sConfig.Rank = ADC_REGULAR_RANK_8;
324
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
325
+  {
326
+    Error_Handler();
327
+  }
328
+  /** Configure Regular Channel 
329
+  */
330
+  sConfig.Channel = ADC_CHANNEL_8;
331
+  sConfig.Rank = ADC_REGULAR_RANK_9;
332
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
333
+  {
334
+    Error_Handler();
335
+  }
336
+  /** Configure Regular Channel 
337
+  */
338
+  sConfig.Channel = ADC_CHANNEL_9;
339
+  sConfig.Rank = ADC_REGULAR_RANK_10;
340
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
341
+  {
342
+    Error_Handler();
343
+  }
344
+  /** Configure Regular Channel 
345
+  */
346
+  sConfig.Channel = ADC_CHANNEL_10;
347
+  sConfig.Rank = ADC_REGULAR_RANK_11;
348
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
349
+  {
350
+    Error_Handler();
351
+  }
352
+  /** Configure Regular Channel 
353
+  */
354
+  sConfig.Channel = ADC_CHANNEL_11;
355
+  sConfig.Rank = ADC_REGULAR_RANK_12;
356
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
357
+  {
358
+    Error_Handler();
359
+  }
360
+  /** Configure Regular Channel 
361
+  */
362
+  sConfig.Channel = ADC_CHANNEL_12;
363
+  sConfig.Rank = ADC_REGULAR_RANK_13;
364
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
365
+  {
366
+    Error_Handler();
367
+  }
368
+  /** Configure Regular Channel 
369
+  */
370
+  sConfig.Channel = ADC_CHANNEL_13;
371
+  sConfig.Rank = ADC_REGULAR_RANK_14;
372
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
373
+  {
374
+    Error_Handler();
375
+  }
376
+  /* USER CODE BEGIN ADC1_Init 2 */
377
+
378
+  /* USER CODE END ADC1_Init 2 */
379
+
380
+}
381
+
382
+/**
383
+  * @brief TIM6 Initialization Function
384
+  * @param None
385
+  * @retval None
386
+  */
387
+static void MX_TIM6_Init(void)
388
+{
389
+
390
+  /* USER CODE BEGIN TIM6_Init 0 */
391
+
392
+  /* USER CODE END TIM6_Init 0 */
393
+
394
+  TIM_MasterConfigTypeDef sMasterConfig = {0};
395
+
396
+  /* USER CODE BEGIN TIM6_Init 1 */
397
+
398
+  /* USER CODE END TIM6_Init 1 */
399
+  htim6.Instance = TIM6;
400
+  htim6.Init.Prescaler = 5600-1;
401
+  htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
402
+  htim6.Init.Period = 10;
403
+  htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
404
+  if (HAL_TIM_Base_Init(&htim6) != HAL_OK)
405
+  {
406
+    Error_Handler();
407
+  }
408
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
409
+  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
410
+  if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK)
411
+  {
412
+    Error_Handler();
413
+  }
414
+  /* USER CODE BEGIN TIM6_Init 2 */
415
+
416
+  /* USER CODE END TIM6_Init 2 */
417
+
418
+}
419
+
420
+/**
421
+  * @brief USART1 Initialization Function
422
+  * @param None
423
+  * @retval None
424
+  */
425
+static void MX_USART1_UART_Init(void)
426
+{
427
+
428
+  /* USER CODE BEGIN USART1_Init 0 */
429
+
430
+  /* USER CODE END USART1_Init 0 */
431
+
432
+  /* USER CODE BEGIN USART1_Init 1 */
433
+
434
+  /* USER CODE END USART1_Init 1 */
435
+  huart1.Instance = USART1;
436
+  huart1.Init.BaudRate = 115200;
437
+  huart1.Init.WordLength = UART_WORDLENGTH_8B;
438
+  huart1.Init.StopBits = UART_STOPBITS_1;
439
+  huart1.Init.Parity = UART_PARITY_NONE;
440
+  huart1.Init.Mode = UART_MODE_TX_RX;
441
+  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
442
+  huart1.Init.OverSampling = UART_OVERSAMPLING_16;
443
+  if (HAL_UART_Init(&huart1) != HAL_OK)
444
+  {
445
+    Error_Handler();
446
+  }
447
+  /* USER CODE BEGIN USART1_Init 2 */
448
+
449
+  /* USER CODE END USART1_Init 2 */
450
+
451
+}
452
+
453
+/** 
454
+  * Enable DMA controller clock
455
+  */
456
+static void MX_DMA_Init(void) 
457
+{
458
+
459
+  /* DMA controller clock enable */
460
+  __HAL_RCC_DMA1_CLK_ENABLE();
461
+
462
+}
463
+
464
+/**
465
+  * @brief GPIO Initialization Function
466
+  * @param None
467
+  * @retval None
468
+  */
469
+static void MX_GPIO_Init(void)
470
+{
471
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
472
+
473
+  /* GPIO Ports Clock Enable */
474
+  __HAL_RCC_GPIOE_CLK_ENABLE();
475
+  __HAL_RCC_GPIOC_CLK_ENABLE();
476
+  __HAL_RCC_GPIOF_CLK_ENABLE();
477
+  __HAL_RCC_GPIOA_CLK_ENABLE();
478
+  __HAL_RCC_GPIOB_CLK_ENABLE();
479
+  __HAL_RCC_GPIOD_CLK_ENABLE();
480
+  __HAL_RCC_GPIOG_CLK_ENABLE();
481
+
482
+  /*Configure GPIO pin Output Level */
483
+  HAL_GPIO_WritePin(GPIOE, ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin 
484
+                          |ATT_EN_1_8G_UL3_Pin|PATH_EN_2_1G_DL_Pin|PATH_EN_2_1G_UL_Pin, GPIO_PIN_RESET);
485
+
486
+  /*Configure GPIO pin Output Level */
487
+  HAL_GPIO_WritePin(GPIOC, ATT_EN_1_8G_UL4_Pin|PATH_EN_1_8G_DL_Pin|PATH_EN_1_8G_UL_Pin|PLL_EN_3_5G_L_Pin 
488
+                          |PLL_EN_3_5G_H_Pin|PLL_ON_OFF_3_5G_L_Pin|PLL_DATA_3_5G_Pin|PLL_ON_OFF_3_5G_H_Pin, GPIO_PIN_RESET);
489
+
490
+  /*Configure GPIO pin Output Level */
491
+  HAL_GPIO_WritePin(GPIOF, PLL_EN_1_8G_DL_Pin|PLL_EN_1_8G_UL_Pin|ATT_EN_2_1G_DL1_Pin|ATT_EN_2_1G_DL2_Pin 
492
+                          |ATT_EN_2_1G_UL1_Pin|ATT_EN_2_1G_UL2_Pin|ATT_EN_2_1G_UL3_Pin|ATT_EN_2_1G_UL4_Pin, GPIO_PIN_RESET);
493
+
494
+  /*Configure GPIO pin Output Level */
495
+  HAL_GPIO_WritePin(GPIOD, PLL_DATA_Pin|PLL_CLK_Pin|ATT_DATA_Pin|ATT_CLK_Pin 
496
+                          |DA_LDAC_Pin|ATT_CLK_3_5G_Pin|ATT_EN_3_5G_Pin|ATT_DATA_3_5G_LOW1_Pin 
497
+                          |ATT_DATA_3_5G_HIGH1_Pin|ATT_DATA_3_5G_COM1_Pin|ATT_DATA_3_5G_LOW2_Pin|ATT_DATA_3_5G_COM2_Pin 
498
+                          |PATH_EN_3_5G_L_Pin, GPIO_PIN_RESET);
499
+
500
+  /*Configure GPIO pin Output Level */
501
+  HAL_GPIO_WritePin(GPIOG, DA_SYNC_Pin|DA_SCLK_Pin|DA_DIN_Pin|_T_SYNC_UL_Pin 
502
+                          |T_SYNC_UL_Pin|_T_SYNC_DL_Pin|T_SYNC_DL_Pin|PATH_EN_3_5G_H_Pin 
503
+                          |PATH_EN_3_5G_DL_Pin|PATH_EN_3_5G_UL_Pin|PLL_ON_OFF_3_5G_LG12_Pin|ATT_DATA_3_5G_HIGH2_Pin 
504
+                          |BOOT_LED_Pin, GPIO_PIN_RESET);
505
+
506
+  /*Configure GPIO pin Output Level */
507
+  HAL_GPIO_WritePin(PLL_CLK_3_5G_GPIO_Port, PLL_CLK_3_5G_Pin, GPIO_PIN_RESET);
508
+
509
+  /*Configure GPIO pin Output Level */
510
+  HAL_GPIO_WritePin(GPIOB, PLL_EN_2_1G_DL_Pin|PLL_EN_2_1G_UL_Pin, GPIO_PIN_RESET);
511
+
512
+  /*Configure GPIO pins : ATT_EN_1_8G_DL1_Pin ATT_EN_1_8G_DL2_Pin ATT_EN_1_8G_UL1_Pin ATT_EN_1_8G_UL2_Pin 
513
+                           ATT_EN_1_8G_UL3_Pin PATH_EN_2_1G_DL_Pin PATH_EN_2_1G_UL_Pin */
514
+  GPIO_InitStruct.Pin = ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin 
515
+                          |ATT_EN_1_8G_UL3_Pin|PATH_EN_2_1G_DL_Pin|PATH_EN_2_1G_UL_Pin;
516
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
517
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
518
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
519
+  HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
520
+
521
+  /*Configure GPIO pins : ATT_EN_1_8G_UL4_Pin PATH_EN_1_8G_DL_Pin PATH_EN_1_8G_UL_Pin PLL_EN_3_5G_L_Pin 
522
+                           PLL_EN_3_5G_H_Pin PLL_ON_OFF_3_5G_L_Pin PLL_DATA_3_5G_Pin PLL_ON_OFF_3_5G_H_Pin */
523
+  GPIO_InitStruct.Pin = ATT_EN_1_8G_UL4_Pin|PATH_EN_1_8G_DL_Pin|PATH_EN_1_8G_UL_Pin|PLL_EN_3_5G_L_Pin 
524
+                          |PLL_EN_3_5G_H_Pin|PLL_ON_OFF_3_5G_L_Pin|PLL_DATA_3_5G_Pin|PLL_ON_OFF_3_5G_H_Pin;
525
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
526
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
527
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
528
+  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
529
+
530
+  /*Configure GPIO pins : PLL_EN_1_8G_DL_Pin PLL_EN_1_8G_UL_Pin ATT_EN_2_1G_DL1_Pin ATT_EN_2_1G_DL2_Pin 
531
+                           ATT_EN_2_1G_UL1_Pin ATT_EN_2_1G_UL2_Pin ATT_EN_2_1G_UL3_Pin ATT_EN_2_1G_UL4_Pin */
532
+  GPIO_InitStruct.Pin = PLL_EN_1_8G_DL_Pin|PLL_EN_1_8G_UL_Pin|ATT_EN_2_1G_DL1_Pin|ATT_EN_2_1G_DL2_Pin 
533
+                          |ATT_EN_2_1G_UL1_Pin|ATT_EN_2_1G_UL2_Pin|ATT_EN_2_1G_UL3_Pin|ATT_EN_2_1G_UL4_Pin;
534
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
535
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
536
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
537
+  HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
538
+
539
+  /*Configure GPIO pins : PLL_LD_1_8G_DL_Pin PLL_LD_1_8G_UL_Pin */
540
+  GPIO_InitStruct.Pin = PLL_LD_1_8G_DL_Pin|PLL_LD_1_8G_UL_Pin;
541
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
542
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
543
+  HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
544
+
545
+  /*Configure GPIO pins : PLL_DATA_Pin PLL_CLK_Pin ATT_DATA_Pin ATT_CLK_Pin 
546
+                           DA_LDAC_Pin ATT_CLK_3_5G_Pin ATT_EN_3_5G_Pin ATT_DATA_3_5G_LOW1_Pin 
547
+                           ATT_DATA_3_5G_HIGH1_Pin ATT_DATA_3_5G_COM1_Pin ATT_DATA_3_5G_LOW2_Pin ATT_DATA_3_5G_COM2_Pin 
548
+                           PATH_EN_3_5G_L_Pin */
549
+  GPIO_InitStruct.Pin = PLL_DATA_Pin|PLL_CLK_Pin|ATT_DATA_Pin|ATT_CLK_Pin 
550
+                          |DA_LDAC_Pin|ATT_CLK_3_5G_Pin|ATT_EN_3_5G_Pin|ATT_DATA_3_5G_LOW1_Pin 
551
+                          |ATT_DATA_3_5G_HIGH1_Pin|ATT_DATA_3_5G_COM1_Pin|ATT_DATA_3_5G_LOW2_Pin|ATT_DATA_3_5G_COM2_Pin 
552
+                          |PATH_EN_3_5G_L_Pin;
553
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
554
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
555
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
556
+  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
557
+
558
+  /*Configure GPIO pins : ALARM_DC_Pin ALARM_AC_Pin */
559
+  GPIO_InitStruct.Pin = ALARM_DC_Pin|ALARM_AC_Pin;
560
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
561
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
562
+  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
563
+
564
+  /*Configure GPIO pins : DA_SYNC_Pin DA_SCLK_Pin DA_DIN_Pin _T_SYNC_UL_Pin 
565
+                           T_SYNC_UL_Pin _T_SYNC_DL_Pin T_SYNC_DL_Pin PATH_EN_3_5G_H_Pin 
566
+                           PATH_EN_3_5G_DL_Pin PATH_EN_3_5G_UL_Pin PLL_ON_OFF_3_5G_LG12_Pin ATT_DATA_3_5G_HIGH2_Pin 
567
+                           BOOT_LED_Pin */
568
+  GPIO_InitStruct.Pin = DA_SYNC_Pin|DA_SCLK_Pin|DA_DIN_Pin|_T_SYNC_UL_Pin 
569
+                          |T_SYNC_UL_Pin|_T_SYNC_DL_Pin|T_SYNC_DL_Pin|PATH_EN_3_5G_H_Pin 
570
+                          |PATH_EN_3_5G_DL_Pin|PATH_EN_3_5G_UL_Pin|PLL_ON_OFF_3_5G_LG12_Pin|ATT_DATA_3_5G_HIGH2_Pin 
571
+                          |BOOT_LED_Pin;
572
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
573
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
574
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
575
+  HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
576
+
577
+  /*Configure GPIO pins : PLL_LD_3_5G_L_Pin PLL_LD_3_5G_H_Pin */
578
+  GPIO_InitStruct.Pin = PLL_LD_3_5G_L_Pin|PLL_LD_3_5G_H_Pin;
579
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
580
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
581
+  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
582
+
583
+  /*Configure GPIO pin : PLL_CLK_3_5G_Pin */
584
+  GPIO_InitStruct.Pin = PLL_CLK_3_5G_Pin;
585
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
586
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
587
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
588
+  HAL_GPIO_Init(PLL_CLK_3_5G_GPIO_Port, &GPIO_InitStruct);
589
+
590
+  /*Configure GPIO pins : PLL_EN_2_1G_DL_Pin PLL_EN_2_1G_UL_Pin */
591
+  GPIO_InitStruct.Pin = PLL_EN_2_1G_DL_Pin|PLL_EN_2_1G_UL_Pin;
592
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
593
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
594
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
595
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
596
+
597
+  /*Configure GPIO pins : PLL_LD_2_1G_DL_Pin PLL_LD_2_1G_UL_Pin */
598
+  GPIO_InitStruct.Pin = PLL_LD_2_1G_DL_Pin|PLL_LD_2_1G_UL_Pin;
599
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
600
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
601
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
602
+
603
+}
604
+
605
+/* USER CODE BEGIN 4 */
606
+
607
+/* USER CODE END 4 */
608
+
609
+/**
610
+  * @brief  This function is executed in case of error occurrence.
611
+  * @retval None
612
+  */
613
+void Error_Handler(void)
614
+{
615
+  /* USER CODE BEGIN Error_Handler_Debug */
616
+  /* User can add his own implementation to report the HAL error return state */
617
+
618
+  /* USER CODE END Error_Handler_Debug */
619
+}
620
+
621
+#ifdef  USE_FULL_ASSERT
622
+/**
623
+  * @brief  Reports the name of the source file and the source line number
624
+  *         where the assert_param error has occurred.
625
+  * @param  file: pointer to the source file name
626
+  * @param  line: assert_param error line source number
627
+  * @retval None
628
+  */
629
+void assert_failed(uint8_t *file, uint32_t line)
630
+{ 
631
+  /* USER CODE BEGIN 6 */
632
+  /* User can add his own implementation to report the file name and line number,
633
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
634
+  /* USER CODE END 6 */
635
+}
636
+#endif /* USE_FULL_ASSERT */
637
+
638
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 675 - 0
insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/zig_operate(4986).c

@@ -0,0 +1,675 @@
1
+/*
2
+ * zig_operate.c
3
+ *
4
+ *  Created on: 2019. 7. 26.
5
+ *      Author: parkyj
6
+ */
7
+#include "zig_operate.h"
8
+uint8_t Prev_data[INDEX_BLUE_EOF + 1];
9
+uint8_t Flash_Save_data[INDEX_BLUE_EOF + 1];
10
+
11
+
12
+/* * * * * * * #define Struct* * * * * * * */
13
+PLL_Setting_st Pll_1_8GHz_DL = {
14
+	PLL_CLK_GPIO_Port,
15
+	PLL_CLK_Pin,
16
+	PLL_DATA_GPIO_Port,
17
+	PLL_DATA_Pin,
18
+    PLL_EN_1_8G_DL_GPIO_Port,    
19
+    PLL_EN_1_8G_DL_Pin,
20
+};
21
+PLL_Setting_st Pll_1_8GHz_UL = {
22
+    PLL_CLK_GPIO_Port,
23
+    PLL_CLK_Pin,
24
+    PLL_DATA_GPIO_Port,
25
+    PLL_DATA_Pin,
26
+    PLL_EN_1_8G_UL_GPIO_Port,    
27
+    PLL_EN_1_8G_UL_Pin,
28
+};
29
+PLL_Setting_st Pll_2_1GHz_DL = {
30
+    PLL_CLK_GPIO_Port,
31
+    PLL_CLK_Pin,
32
+    PLL_DATA_GPIO_Port,
33
+    PLL_DATA_Pin,
34
+    PLL_EN_2_1G_DL_GPIO_Port,    
35
+    PLL_EN_2_1G_DL_Pin,
36
+};
37
+PLL_Setting_st Pll_2_1GHz_UL = {
38
+    PLL_CLK_GPIO_Port,
39
+    PLL_CLK_Pin,
40
+    PLL_DATA_GPIO_Port,
41
+    PLL_DATA_Pin,
42
+    PLL_EN_2_1G_UL_GPIO_Port,    
43
+    PLL_EN_2_1G_UL_Pin,
44
+};
45
+/* * * * * * * * NOT YET * * * * * * * */
46
+PLL_Setting_st Pll_3_5GHz_DL = {
47
+    ATT_CLK_3_5G_GPIO_Port,
48
+    ATT_EN_3_5G_Pin,
49
+    PLL_DATA_GPIO_Port,
50
+    PLL_DATA_Pin,
51
+    PLL_EN_2_1G_DL_GPIO_Port,    
52
+    PLL_EN_2_1G_DL_Pin,
53
+};
54
+PLL_Setting_st Pll_3_5GHz_UL = {
55
+    PLL_CLK_GPIO_Port,
56
+    PLL_CLK_Pin,
57
+    PLL_DATA_GPIO_Port,
58
+    PLL_DATA_Pin,
59
+    PLL_EN_2_1G_UL_GPIO_Port,    
60
+    PLL_EN_2_1G_UL_Pin,
61
+};
62
+/* * * * * * * * ATTEN * * * * * * * */    
63
+ATTEN_Setting_st Atten_1_8Ghz_DL1 ={
64
+    ATT_CLK_GPIO_Port,
65
+    ATT_CLK_Pin,
66
+    ATT_DATA_GPIO_Port,
67
+    ATT_DATA_Pin,
68
+    ATT_EN_1_8G_DL1_GPIO_Port,    
69
+    ATT_EN_1_8G_DL1_Pin,
70
+    PATH_EN_1_8G_DL_GPIO_Port,
71
+    PATH_EN_1_8G_DL_Pin,
72
+};
73
+
74
+ATTEN_Setting_st Atten_1_8Ghz_DL2 ={
75
+    ATT_CLK_GPIO_Port,
76
+    ATT_CLK_Pin,
77
+    ATT_DATA_GPIO_Port,
78
+    ATT_DATA_Pin,
79
+    ATT_EN_1_8G_DL2_GPIO_Port,    
80
+    ATT_EN_1_8G_DL2_Pin,
81
+    PATH_EN_1_8G_DL_GPIO_Port,
82
+    PATH_EN_1_8G_DL_Pin,    
83
+};
84
+ATTEN_Setting_st Atten_1_8Ghz_UL1 ={
85
+    ATT_CLK_GPIO_Port,
86
+    ATT_CLK_Pin,
87
+    ATT_DATA_GPIO_Port,
88
+    ATT_DATA_Pin,
89
+    ATT_EN_1_8G_UL1_GPIO_Port,    
90
+    ATT_EN_1_8G_UL1_Pin,
91
+    PATH_EN_1_8G_UL_GPIO_Port,
92
+    PATH_EN_1_8G_UL_Pin,      
93
+};
94
+ATTEN_Setting_st Atten_1_8Ghz_UL2 ={
95
+    ATT_CLK_GPIO_Port,
96
+    ATT_CLK_Pin,
97
+    ATT_DATA_GPIO_Port,
98
+    ATT_DATA_Pin,
99
+    ATT_EN_1_8G_UL2_GPIO_Port,    
100
+    ATT_EN_1_8G_UL2_Pin,
101
+    PATH_EN_1_8G_UL_GPIO_Port,
102
+    PATH_EN_1_8G_UL_Pin,    
103
+};
104
+ATTEN_Setting_st Atten_1_8Ghz_UL3 ={
105
+    ATT_CLK_GPIO_Port,
106
+    ATT_CLK_Pin,
107
+    ATT_DATA_GPIO_Port,
108
+    ATT_DATA_Pin,
109
+    ATT_EN_1_8G_UL3_GPIO_Port,    
110
+    ATT_EN_1_8G_UL3_Pin,
111
+    PATH_EN_1_8G_UL_GPIO_Port,
112
+    PATH_EN_1_8G_UL_Pin,    
113
+};
114
+ATTEN_Setting_st Atten_1_8Ghz_UL4 ={
115
+    ATT_CLK_GPIO_Port,
116
+    ATT_CLK_Pin,
117
+    ATT_DATA_GPIO_Port,
118
+    ATT_DATA_Pin,
119
+    ATT_EN_1_8G_UL4_GPIO_Port,    
120
+    ATT_EN_1_8G_UL4_Pin,
121
+    PATH_EN_1_8G_UL_GPIO_Port,
122
+    PATH_EN_1_8G_UL_Pin,    
123
+};
124
+ATTEN_Setting_st Atten_2_1Ghz_DL1 ={
125
+    ATT_CLK_GPIO_Port,
126
+    ATT_CLK_Pin,
127
+    ATT_DATA_GPIO_Port,
128
+    ATT_DATA_Pin,
129
+    ATT_EN_2_1G_DL1_GPIO_Port,    
130
+    ATT_EN_2_1G_DL1_Pin,
131
+    PATH_EN_2_1G_DL_GPIO_Port,
132
+    PATH_EN_2_1G_DL_Pin,    
133
+};
134
+ATTEN_Setting_st Atten_2_1Ghz_DL2 ={
135
+    ATT_CLK_GPIO_Port,
136
+    ATT_CLK_Pin,
137
+    ATT_DATA_GPIO_Port,
138
+    ATT_DATA_Pin,
139
+    ATT_EN_2_1G_DL2_GPIO_Port,    
140
+    ATT_EN_2_1G_DL2_Pin,
141
+    PATH_EN_2_1G_DL_GPIO_Port,
142
+    PATH_EN_2_1G_DL_Pin,    
143
+};
144
+
145
+ATTEN_Setting_st Atten_2_1Ghz_UL1 ={
146
+    ATT_CLK_GPIO_Port,
147
+    ATT_CLK_Pin,
148
+    ATT_DATA_GPIO_Port,
149
+    ATT_DATA_Pin,
150
+    ATT_EN_2_1G_UL1_GPIO_Port,    
151
+    ATT_EN_2_1G_UL1_Pin,
152
+    PATH_EN_2_1G_UL_GPIO_Port,
153
+    PATH_EN_2_1G_UL_Pin,    
154
+};
155
+ATTEN_Setting_st Atten_2_1Ghz_UL2 ={
156
+    ATT_CLK_GPIO_Port,
157
+    ATT_CLK_Pin,
158
+    ATT_DATA_GPIO_Port,
159
+    ATT_DATA_Pin,
160
+    ATT_EN_2_1G_UL2_GPIO_Port,    
161
+    ATT_EN_2_1G_UL2_Pin,
162
+    PATH_EN_2_1G_UL_GPIO_Port,
163
+    PATH_EN_2_1G_UL_Pin,    
164
+};
165
+ATTEN_Setting_st Atten_2_1Ghz_UL3 ={
166
+    ATT_CLK_GPIO_Port,
167
+    ATT_CLK_Pin,
168
+    ATT_DATA_GPIO_Port,
169
+    ATT_DATA_Pin,
170
+    ATT_EN_2_1G_UL3_GPIO_Port,    
171
+    ATT_EN_2_1G_UL3_Pin,
172
+    PATH_EN_2_1G_UL_GPIO_Port,
173
+    PATH_EN_2_1G_UL_Pin,    
174
+};
175
+ATTEN_Setting_st Atten_2_1Ghz_UL4 ={
176
+    ATT_CLK_GPIO_Port,
177
+    ATT_CLK_Pin,
178
+    ATT_DATA_GPIO_Port,
179
+    ATT_DATA_Pin,
180
+    ATT_EN_2_1G_UL4_GPIO_Port,    
181
+    ATT_EN_2_1G_UL4_Pin,
182
+    PATH_EN_2_1G_UL_GPIO_Port,
183
+    PATH_EN_2_1G_UL_Pin,    
184
+};
185
+
186
+
187
+bool RF_Data_Check(uint8_t* data_buf){
188
+    bool ret = false;
189
+    bool crcret = STH30_CheckCrc(&data_buf[Type], data_buf[Length], data_buf[data_buf[Crcindex]]);
190
+    if(data_buf[Header] == BLUECELL_HEADER){ /*HEADER CHECK*/
191
+        ret= true;
192
+    }
193
+    if(crcret == true){/*CRC CHECK*/
194
+        ret = true;
195
+    }else{
196
+        ret = false;
197
+//        printf("Recv CRC Value : \"%d\"\r\n Create CRC Value : \"%d\"   \r\n",data_buf[data_buf[Crcindex]],STH30_CreateCrc(&data_buf[Type], data_buf[Length]));
198
+    }
199
+//    printf("CRC Result : \"%d\"   \r\n",ret);
200
+    return ret;
201
+
202
+}
203
+
204
+PLL_Setting_st Pll_3_5_H = {
205
+     PLL_CLK_3_5G_GPIO_Port,
206
+     PLL_CLK_3_5G_Pin,
207
+     PLL_DATA_3_5G_GPIO_Port,
208
+     PLL_DATA_3_5G_Pin,
209
+   PLL_EN_3_5G_H_GPIO_Port,    
210
+   PLL_EN_3_5G_H_Pin,
211
+ };
212
+ PLL_Setting_st Pll_3_5_L = {
213
+     PLL_CLK_3_5G_GPIO_Port,
214
+     PLL_CLK_3_5G_Pin,
215
+     PLL_DATA_3_5G_GPIO_Port,
216
+     PLL_DATA_3_5G_Pin,
217
+       PLL_EN_3_5G_L_GPIO_Port,    
218
+       PLL_EN_3_5G_L_Pin,
219
+ };
220
+void RF_Status_Get(void){
221
+//    printf("\r\nYJ2 : Prev_data[INDEX_DET_1_8G_DL_IN_L ] : %x\r\n",Prev_data[INDEX_DET_1_8G_DL_IN_L]);            
222
+    Prev_data[INDEX_BLUE_HEADER]   = BLUECELL_HEADER;
223
+    Prev_data[INDEX_BLUE_TYPE]     = TYPE_BLUECELL_GET;
224
+    Prev_data[INDEX_BLUE_LENGTH]   = INDEX_BLUE_EOF - 2;
225
+    Prev_data[INDEX_BLUE_CRCINDEX] = INDEX_BLUE_CRC;
226
+    Prev_data[INDEX_BLUE_CRC]      = STH30_CreateCrc(&Prev_data[Type], Prev_data[Length]);
227
+    Prev_data[INDEX_BLUE_EOF] = BLUECELL_TAILER;    
228
+    HAL_UART_Transmit_DMA(&huart1,&Prev_data[INDEX_BLUE_HEADER],INDEX_BLUE_EOF + 1); 
229
+//    printf("\r\nYJ : %x",ADCvalue[0]);
230
+//    printf("\r\n");
231
+
232
+}
233
+static uint8_t Ack_Buf[6];
234
+void RF_Status_Ack(void){
235
+//    printf("\r\nYJ2 : Prev_data[INDEX_DET_1_8G_DL_IN_L ] : %x\r\n",Prev_data[INDEX_DET_1_8G_DL_IN_L]);            
236
+    Ack_Buf[INDEX_BLUE_HEADER]       = BLUECELL_HEADER;
237
+    Ack_Buf[INDEX_BLUE_TYPE]         = TYPE_BLUECELL_ACK;
238
+    Ack_Buf[INDEX_BLUE_LENGTH]       = 3;
239
+    Ack_Buf[INDEX_BLUE_CRCINDEX + 0] = INDEX_BLUE_CRCINDEX + 1;
240
+    Ack_Buf[INDEX_BLUE_CRCINDEX + 1] = STH30_CreateCrc(&Ack_Buf[Type], Ack_Buf[Length]);
241
+    Ack_Buf[INDEX_BLUE_CRCINDEX + 2] = BLUECELL_TAILER;
242
+    HAL_UART_Transmit_DMA(&huart1,&Ack_Buf[INDEX_BLUE_HEADER],Ack_Buf[INDEX_BLUE_LENGTH]  + 3); 
243
+//    printf("\r\nYJ : %x",ADCvalue[0]);
244
+//    printf("\r\n");
245
+
246
+}
247
+
248
+void RF_Operate(uint8_t* data_buf){
249
+    uint16_t temp_val = 0;
250
+    uint8_t  ADC_Modify = 0;
251
+    ADF4153_R_N_Reg_st temp_reg;
252
+//    printf("Prev_data[INDEX_ATT_1_8G_DL1]  : %x  data_buf[INDEX_ATT_1_8G_DL1] : %x\r\n",Prev_data[INDEX_ATT_1_8G_DL1],data_buf[INDEX_ATT_1_8G_DL1]);
253
+    if(Prev_data[INDEX_ATT_1_8G_DL1] != data_buf[INDEX_ATT_1_8G_DL1]){
254
+        BDA4601_atten_ctrl(BDA4601_1_8G_DL1,(data_buf[INDEX_ATT_1_8G_DL1]));
255
+        Prev_data[INDEX_ATT_1_8G_DL1] = data_buf[INDEX_ATT_1_8G_DL1];
256
+    }
257
+    if(Prev_data[INDEX_ATT_1_8G_DL2] != data_buf[INDEX_ATT_1_8G_DL2]){
258
+        BDA4601_atten_ctrl(BDA4601_1_8G_DL2,(data_buf[INDEX_ATT_1_8G_DL2]));
259
+        Prev_data[INDEX_ATT_1_8G_DL2] = data_buf[INDEX_ATT_1_8G_DL2];
260
+    }
261
+    if(Prev_data[INDEX_ATT_1_8G_UL1] != data_buf[INDEX_ATT_1_8G_UL1]){
262
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL1,(data_buf[INDEX_ATT_1_8G_UL1]));
263
+        Prev_data[INDEX_ATT_1_8G_UL1] = data_buf[INDEX_ATT_1_8G_UL1];
264
+    }
265
+    if(Prev_data[INDEX_ATT_1_8G_UL2] != data_buf[INDEX_ATT_1_8G_UL2]){
266
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL2,(data_buf[INDEX_ATT_1_8G_UL2]));
267
+        Prev_data[INDEX_ATT_1_8G_UL2] = data_buf[INDEX_ATT_1_8G_UL2];
268
+    }
269
+    if(Prev_data[INDEX_ATT_1_8G_UL3] != data_buf[INDEX_ATT_1_8G_UL3]){
270
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL3,(data_buf[INDEX_ATT_1_8G_UL3]));
271
+        Prev_data[INDEX_ATT_1_8G_UL3] = data_buf[INDEX_ATT_1_8G_UL3];
272
+
273
+    }
274
+    if(Prev_data[INDEX_ATT_1_8G_UL4] != data_buf[INDEX_ATT_1_8G_UL4]){
275
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL4,(data_buf[INDEX_ATT_1_8G_UL4]));
276
+        Prev_data[INDEX_ATT_1_8G_UL4] = data_buf[INDEX_ATT_1_8G_UL4];
277
+
278
+    }
279
+    if(Prev_data[INDEX_ATT_2_1G_DL1] != data_buf[INDEX_ATT_2_1G_DL1]){
280
+        BDA4601_atten_ctrl(BDA4601_2_1G_DL1,(data_buf[INDEX_ATT_2_1G_DL1]));
281
+        Prev_data[INDEX_ATT_2_1G_DL1] = data_buf[INDEX_ATT_2_1G_DL1];
282
+
283
+    }
284
+    if(Prev_data[INDEX_ATT_2_1G_DL2] != data_buf[INDEX_ATT_2_1G_DL2]){
285
+        BDA4601_atten_ctrl(BDA4601_2_1G_DL2,(data_buf[INDEX_ATT_2_1G_DL2]));
286
+        Prev_data[INDEX_ATT_2_1G_DL2] = data_buf[INDEX_ATT_2_1G_DL2];
287
+
288
+    }
289
+    if(Prev_data[INDEX_ATT_2_1G_UL1] != data_buf[INDEX_ATT_2_1G_UL1]){
290
+        BDA4601_atten_ctrl(BDA4601_2_1G_UL1,(data_buf[INDEX_ATT_2_1G_UL1]));
291
+        Prev_data[INDEX_ATT_2_1G_UL1] = data_buf[INDEX_ATT_2_1G_UL1];
292
+
293
+    }
294
+    if(Prev_data[INDEX_ATT_2_1G_UL2] != data_buf[INDEX_ATT_2_1G_UL2]){
295
+        BDA4601_atten_ctrl(BDA4601_2_1G_UL2,(data_buf[INDEX_ATT_2_1G_UL2]));
296
+        Prev_data[INDEX_ATT_2_1G_UL2] = data_buf[INDEX_ATT_2_1G_UL2];
297
+
298
+    }
299
+    if(Prev_data[INDEX_ATT_2_1G_UL3] != data_buf[INDEX_ATT_2_1G_UL3]){
300
+        BDA4601_atten_ctrl(BDA4601_2_1G_UL3,(data_buf[INDEX_ATT_2_1G_UL3]));
301
+        Prev_data[INDEX_ATT_2_1G_UL3] = data_buf[INDEX_ATT_2_1G_UL3];
302
+    }
303
+    if(Prev_data[INDEX_ATT_2_1G_UL4] != data_buf[INDEX_ATT_2_1G_UL4]){
304
+        BDA4601_atten_ctrl(BDA4601_2_1G_UL4,(data_buf[INDEX_ATT_2_1G_UL4]));
305
+        Prev_data[INDEX_ATT_2_1G_UL4] = data_buf[INDEX_ATT_2_1G_UL4];
306
+    }
307
+    if(   (Prev_data[INDEX_ATT_3_5G_LOW1] != data_buf[INDEX_ATT_3_5G_LOW1])
308
+        ||(Prev_data[INDEX_ATT_3_5G_HIGH1] != data_buf[INDEX_ATT_3_5G_HIGH1])
309
+        ||(Prev_data[INDEX_ATT_3_5G_COM1] != data_buf[INDEX_ATT_3_5G_COM1])
310
+        ||(Prev_data[INDEX_ATT_3_5G_LOW2] != data_buf[INDEX_ATT_3_5G_LOW2])
311
+        ||(Prev_data[INDEX_ATT_3_5G_HIGH2] != data_buf[INDEX_ATT_3_5G_HIGH2])
312
+        ||(Prev_data[INDEX_ATT_3_5G_COM2] != data_buf[INDEX_ATT_3_5G_COM2])
313
+    ){
314
+        ALL_ATT_3_5G.data0 = Prev_data[INDEX_ATT_3_5G_LOW1]  = data_buf[INDEX_ATT_3_5G_LOW1];
315
+        ALL_ATT_3_5G.data1 = Prev_data[INDEX_ATT_3_5G_HIGH1] = data_buf[INDEX_ATT_3_5G_HIGH1];
316
+        ALL_ATT_3_5G.data2 = Prev_data[INDEX_ATT_3_5G_COM1]  = data_buf[INDEX_ATT_3_5G_COM1];
317
+        ALL_ATT_3_5G.data3 = Prev_data[INDEX_ATT_3_5G_LOW2]  = data_buf[INDEX_ATT_3_5G_LOW2];
318
+        ALL_ATT_3_5G.data4 = Prev_data[INDEX_ATT_3_5G_HIGH2] = data_buf[INDEX_ATT_3_5G_HIGH2];
319
+        ALL_ATT_3_5G.data5 = Prev_data[INDEX_ATT_3_5G_COM2]  = data_buf[INDEX_ATT_3_5G_COM2];
320
+        PE43711_ALL_atten_ctrl(ALL_ATT_3_5G);
321
+    }
322
+    if((Prev_data[INDEX_PLL_1_8G_DL_H] != data_buf[INDEX_PLL_1_8G_DL_H])
323
+        && (Prev_data[INDEX_PLL_1_8G_DL_L] != data_buf[INDEX_PLL_1_8G_DL_L])
324
+    ){
325
+        Prev_data[INDEX_PLL_1_8G_DL_H] = data_buf[INDEX_PLL_1_8G_DL_H];
326
+        Prev_data[INDEX_PLL_1_8G_DL_L] = data_buf[INDEX_PLL_1_8G_DL_L];
327
+        temp_val = (data_buf[INDEX_PLL_1_8G_DL_H] << 8) | (data_buf[INDEX_PLL_1_8G_DL_L]);
328
+        ADF4113_Module_Ctrl(ADF4113_1_8G_DL,0x410,halSynSetFreq((temp_val * 1000000) / 10 ),0x9F8092);
329
+    }
330
+    if((Prev_data[INDEX_PLL_1_8G_UL_H] != data_buf[INDEX_PLL_1_8G_UL_H])
331
+        && (Prev_data[INDEX_PLL_1_8G_UL_L] != data_buf[INDEX_PLL_1_8G_UL_L])){
332
+        temp_val = (data_buf[INDEX_PLL_1_8G_UL_H] << 8) | (data_buf[INDEX_PLL_1_8G_UL_L]);
333
+        Prev_data[INDEX_PLL_1_8G_UL_H] = data_buf[INDEX_PLL_1_8G_UL_H];
334
+        Prev_data[INDEX_PLL_1_8G_UL_L] = data_buf[INDEX_PLL_1_8G_UL_L];
335
+//         ADF4113_Module_Ctrl(ADF4113_1_8G_UL,0x000410,0x038D31,0x9f8092);
336
+         ADF4113_Module_Ctrl(ADF4113_1_8G_UL,0x410,halSynSetFreq((temp_val * 1000000) / 10),0x9F8092);
337
+    }
338
+    if((Prev_data[INDEX_PLL_2_1G_DL_H] != data_buf[INDEX_PLL_2_1G_DL_H])
339
+        && (Prev_data[INDEX_PLL_2_1G_DL_L] != data_buf[INDEX_PLL_2_1G_DL_L])){
340
+        temp_val = ((data_buf[INDEX_PLL_2_1G_DL_H] << 8) | (data_buf[INDEX_PLL_2_1G_DL_L]));
341
+        Prev_data[INDEX_PLL_2_1G_DL_H] = data_buf[INDEX_PLL_2_1G_DL_H];
342
+        Prev_data[INDEX_PLL_2_1G_DL_L] = data_buf[INDEX_PLL_2_1G_DL_L];        
343
+//         ADF4113_Module_Ctrl(ADF4113_2_1G_DL,0x410,0x4DE71,0x9F8092);
344
+        ADF4113_Module_Ctrl(ADF4113_2_1G_DL,0x410,halSynSetFreq((temp_val * 1000000) / 10),0x9F8092);
345
+    }
346
+    if((Prev_data[INDEX_PLL_2_1G_UL_H] != data_buf[INDEX_PLL_2_1G_UL_H])
347
+        && (Prev_data[INDEX_PLL_2_1G_UL_L] != data_buf[INDEX_PLL_2_1G_UL_L])){
348
+        Prev_data[INDEX_PLL_2_1G_UL_H] = data_buf[INDEX_PLL_2_1G_UL_H];
349
+        Prev_data[INDEX_PLL_2_1G_UL_L] = data_buf[INDEX_PLL_2_1G_UL_L];          
350
+        temp_val = (data_buf[INDEX_PLL_2_1G_UL_H] << 8) | (data_buf[INDEX_PLL_2_1G_UL_L]);
351
+//        ADF4113_Module_Ctrl(ADF4113_2_1G_UL,0x000410,0x59A31,0x9f8092);
352
+        ADF4113_Module_Ctrl(ADF4113_2_1G_UL,0x410,halSynSetFreq((temp_val * 1000000) / 10),0x9F8092);
353
+
354
+    }
355
+    if((Prev_data[INDEX_PLL_3_5G_DL_H] != data_buf[INDEX_PLL_3_5G_DL_H])
356
+        && (Prev_data[INDEX_PLL_3_5G_DL_L] != data_buf[INDEX_PLL_3_5G_DL_L])){
357
+        Prev_data[INDEX_PLL_3_5G_DL_H] = data_buf[INDEX_PLL_3_5G_DL_H];
358
+        Prev_data[INDEX_PLL_3_5G_DL_L] = data_buf[INDEX_PLL_3_5G_DL_L];
359
+        temp_val = (data_buf[INDEX_PLL_3_5G_DL_H] << 8) | (data_buf[INDEX_PLL_3_5G_DL_L]);
360
+        temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
361
+        ADF4153_Module_Ctrl(Pll_3_5_L,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
362
+    }
363
+    if((Prev_data[INDEX_PLL_3_5G_UL_H] != data_buf[INDEX_PLL_3_5G_UL_H])
364
+        && (Prev_data[INDEX_PLL_3_5G_UL_L] != data_buf[INDEX_PLL_3_5G_UL_L])){
365
+        Prev_data[INDEX_PLL_3_5G_UL_H] = data_buf[INDEX_PLL_3_5G_UL_H];
366
+        Prev_data[INDEX_PLL_3_5G_UL_L] = data_buf[INDEX_PLL_3_5G_UL_L];
367
+        temp_val = (data_buf[INDEX_PLL_3_5G_UL_H] << 8) | (data_buf[INDEX_PLL_3_5G_UL_L]);
368
+        temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
369
+        ADF4153_Module_Ctrl(Pll_3_5_H,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
370
+
371
+    }
372
+    if(Prev_data[INDEX_PLL_LD_6_BIT] != data_buf[INDEX_PLL_LD_6_BIT]){
373
+
374
+    }
375
+#if 0 // PYJ.2019.07.28_BEGIN -- 
376
+    if(Prev_data[INDEX_DET_1_8G_DL_IN_H] != data_buf[INDEX_DET_1_8G_DL_IN_H]){
377
+
378
+    }
379
+    if(Prev_data[INDEX_DET_1_8G_DL_IN_L] != data_buf[INDEX_DET_1_8G_DL_IN_L]){
380
+
381
+    }
382
+    if(Prev_data[INDEX_DET_1_8G_DL_OUT_H] != data_buf[INDEX_DET_1_8G_DL_OUT_H]){
383
+
384
+    }
385
+    if(Prev_data[INDEX_DET_1_8G_DL_OUT_L] != data_buf[INDEX_DET_1_8G_DL_OUT_L]){
386
+
387
+    }
388
+    if(Prev_data[INDEX_DET_1_8G_UL_IN_H] != data_buf[INDEX_DET_1_8G_UL_IN_H]){
389
+
390
+    }
391
+    if(Prev_data[INDEX_DET_1_8G_UL_IN_L] != data_buf[INDEX_DET_1_8G_UL_IN_L]){
392
+
393
+    }
394
+    if(Prev_data[INDEX_DET_1_8G_UL_OUT_H] != data_buf[INDEX_DET_1_8G_UL_OUT_H]){
395
+
396
+    }
397
+    if(Prev_data[INDEX_DET_1_8G_UL_OUT_L] != data_buf[INDEX_DET_1_8G_UL_OUT_L]){
398
+
399
+    }
400
+    if(Prev_data[INDEX_DET_2_1G_DL_IN_H] != data_buf[INDEX_DET_2_1G_DL_IN_H]){
401
+
402
+    }
403
+    if(Prev_data[INDEX_DET_2_1G_DL_IN_L] != data_buf[INDEX_DET_2_1G_DL_IN_L]){
404
+
405
+    }
406
+    if(Prev_data[INDEX_DET_2_1G_DL_OUT_H] != data_buf[INDEX_DET_2_1G_DL_OUT_H]){
407
+
408
+    }
409
+    if(Prev_data[INDEX_DET_2_1G_DL_OUT_L] != data_buf[INDEX_DET_2_1G_DL_OUT_L]){
410
+
411
+    }
412
+    if(Prev_data[INDEX_DET_2_1G_UL_IN_H] != data_buf[INDEX_DET_2_1G_UL_IN_H]){
413
+
414
+    }
415
+    if(Prev_data[INDEX_DET_2_1G_UL_IN_L] != data_buf[INDEX_DET_2_1G_UL_IN_L]){
416
+
417
+    }
418
+
419
+    if(Prev_data[INDEX_DET_2_1G_UL_OUT_H] != data_buf[INDEX_DET_2_1G_UL_OUT_H]){
420
+
421
+    }
422
+    if(Prev_data[INDEX_DET_2_1G_UL_OUT_L] != data_buf[INDEX_DET_2_1G_UL_OUT_L]){
423
+
424
+    }
425
+    if(Prev_data[INDEX_DET_3_5G_DL_IN_H] != data_buf[INDEX_DET_3_5G_DL_IN_H]){
426
+
427
+    }
428
+    if(Prev_data[INDEX_DET_3_5G_DL_IN_L] != data_buf[INDEX_DET_3_5G_DL_IN_L]){
429
+
430
+    }
431
+    if(Prev_data[INDEX_DET_3_5G_DL_OUT_L] != data_buf[INDEX_DET_3_5G_DL_OUT_L]){
432
+
433
+    }
434
+    if(Prev_data[INDEX_DET_3_5G_DL_OUT_H] != data_buf[INDEX_DET_3_5G_DL_OUT_H]){
435
+
436
+    }
437
+    if(Prev_data[INDEX_DET_3_5G_UL_IN_H] != data_buf[INDEX_DET_3_5G_UL_IN_H]){
438
+
439
+    }
440
+    if(Prev_data[INDEX_DET_3_5G_UL_IN_L] != data_buf[INDEX_DET_3_5G_UL_IN_L]){
441
+
442
+    }
443
+
444
+    if(Prev_data[INDEX_DET_3_5G_UL_OUT_H] != data_buf[INDEX_DET_3_5G_UL_OUT_H]){
445
+
446
+    }
447
+    if(Prev_data[INDEX_DET_3_5G_UL_OUT_L] != data_buf[INDEX_DET_3_5G_UL_OUT_L]){
448
+
449
+    }
450
+    if(Prev_data[INDEX_RFU_TEMP_H] != data_buf[INDEX_RFU_TEMP_H]){
451
+
452
+    }
453
+    if(Prev_data[INDEX_RFU_TEMP_L] != data_buf[INDEX_RFU_TEMP_L]){
454
+
455
+    }
456
+    if(Prev_data[INDEX__28V_DET_H] != data_buf[INDEX__28V_DET_H]){
457
+
458
+    }
459
+    if(Prev_data[INDEX__28V_DET_L] != data_buf[INDEX__28V_DET_L]){
460
+
461
+    }
462
+#endif // PYJ.2019.07.28_END -- 
463
+    if(Prev_data[INDEX_ALARM_AC] != data_buf[INDEX_ALARM_AC]){
464
+
465
+    }
466
+    if(Prev_data[INDEX_ALARM_DC] != data_buf[INDEX_ALARM_DC]){
467
+
468
+    }
469
+    if(Prev_data[INDEX_PATH_EN_1_8G_DL] != data_buf[INDEX_PATH_EN_1_8G_DL]){
470
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_1_8G_DL,data_buf[INDEX_PATH_EN_1_8G_DL]);
471
+        Prev_data[INDEX_PATH_EN_1_8G_DL] = data_buf[INDEX_PATH_EN_1_8G_DL];
472
+    }
473
+    if(Prev_data[INDEX_PATH_EN_1_8G_UL] != data_buf[INDEX_PATH_EN_1_8G_UL]){
474
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_1_8G_UL,data_buf[INDEX_PATH_EN_1_8G_UL]);
475
+        Prev_data[INDEX_PATH_EN_1_8G_UL] = data_buf[INDEX_PATH_EN_1_8G_UL];
476
+
477
+    }
478
+
479
+    if(Prev_data[INDEX_PATH_EN_2_1G_DL] != data_buf[INDEX_PATH_EN_2_1G_DL]){
480
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_2_1G_DL,data_buf[INDEX_PATH_EN_2_1G_DL]);
481
+        Prev_data[INDEX_PATH_EN_2_1G_DL] = data_buf[INDEX_PATH_EN_2_1G_DL];
482
+    }
483
+    if(Prev_data[INDEX_PATH_EN_2_1G_UL] != data_buf[INDEX_PATH_EN_2_1G_UL]){
484
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_2_1G_UL,data_buf[INDEX_PATH_EN_2_1G_UL]);
485
+        Prev_data[INDEX_PATH_EN_2_1G_UL] = data_buf[INDEX_PATH_EN_2_1G_UL];
486
+
487
+    }
488
+    if(Prev_data[INDEX_PATH_EN_3_5G_L] != data_buf[INDEX_PATH_EN_3_5G_L]){
489
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_L,data_buf[INDEX_PATH_EN_3_5G_L]);
490
+        Prev_data[INDEX_PATH_EN_3_5G_L] = data_buf[INDEX_PATH_EN_3_5G_L];
491
+
492
+    }
493
+    if(Prev_data[INDEX_PATH_EN_3_5G_H] != data_buf[INDEX_PATH_EN_3_5G_H]){
494
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_H,data_buf[INDEX_PATH_EN_3_5G_H]);
495
+        Prev_data[INDEX_PATH_EN_3_5G_H] = data_buf[INDEX_PATH_EN_3_5G_H];
496
+
497
+    }
498
+    if(Prev_data[INDEX_PATH_EN_3_5G_DL] != data_buf[INDEX_PATH_EN_3_5G_DL]){
499
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_DL,data_buf[INDEX_PATH_EN_3_5G_DL]);
500
+        Prev_data[INDEX_PATH_EN_3_5G_DL] = data_buf[INDEX_PATH_EN_3_5G_DL];
501
+
502
+    }
503
+    if(Prev_data[INDEX_PATH_EN_3_5G_UL] != data_buf[INDEX_PATH_EN_3_5G_UL]){
504
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_UL,data_buf[INDEX_PATH_EN_3_5G_UL]);
505
+        Prev_data[INDEX_PATH_EN_3_5G_UL] = data_buf[INDEX_PATH_EN_3_5G_UL];
506
+
507
+    }
508
+    if(Prev_data[INDEX_PLL_ON_OFF_3_5G_H] != data_buf[INDEX_PLL_ON_OFF_3_5G_H]){
509
+        Power_ON_OFF_Ctrl(INDEX_PLL_ON_OFF_3_5G_H,data_buf[INDEX_PLL_ON_OFF_3_5G_H]);
510
+        Prev_data[INDEX_PLL_ON_OFF_3_5G_H] = data_buf[INDEX_PLL_ON_OFF_3_5G_H];
511
+        HAL_Delay(10);
512
+        printf("POWER : %d \r\n",Prev_data[INDEX_PLL_ON_OFF_3_5G_H]);
513
+        if(data_buf[INDEX_PLL_ON_OFF_3_5G_H]){
514
+            printf("PLL CTRL START !! \r\n");
515
+            temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
516
+            ADF4153_Module_Ctrl(Pll_3_5_H,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
517
+        }
518
+    }
519
+    if(Prev_data[INDEX_PLL_ON_OFF_3_5G_L] != data_buf[INDEX_PLL_ON_OFF_3_5G_L]){
520
+        Power_ON_OFF_Ctrl(INDEX_PLL_ON_OFF_3_5G_L,data_buf[INDEX_PLL_ON_OFF_3_5G_L]);
521
+        Prev_data[INDEX_PLL_ON_OFF_3_5G_L] = data_buf[INDEX_PLL_ON_OFF_3_5G_L];
522
+        HAL_Delay(10);
523
+        printf("POWER : %d \r\n",Prev_data[INDEX_PLL_ON_OFF_3_5G_L]);        
524
+        if(data_buf[INDEX_PLL_ON_OFF_3_5G_L]){
525
+            printf("PLL CTRL START !! \r\n");
526
+            temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);            
527
+            ADF4153_Module_Ctrl(Pll_3_5_L,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
528
+        }
529
+    }
530
+
531
+    if(Prev_data[INDEX_T_SYNC_DL] != data_buf[INDEX_T_SYNC_DL]){
532
+        Prev_data[INDEX_T_SYNC_DL] = data_buf[INDEX_T_SYNC_DL];
533
+        Power_ON_OFF_Ctrl(INDEX_T_SYNC_DL,data_buf[INDEX_T_SYNC_DL]);
534
+    }
535
+    if(Prev_data[INDEX__T_SYNC_DL] != data_buf[INDEX__T_SYNC_DL]){
536
+        Prev_data[INDEX__T_SYNC_DL] = data_buf[INDEX__T_SYNC_DL];
537
+        Power_ON_OFF_Ctrl(INDEX__T_SYNC_DL,data_buf[INDEX__T_SYNC_DL]);
538
+    }
539
+    if(Prev_data[INDEX_T_SYNC_UL] != data_buf[INDEX_T_SYNC_UL]){
540
+        Prev_data[INDEX_T_SYNC_UL] = data_buf[INDEX_T_SYNC_UL];
541
+        Power_ON_OFF_Ctrl(INDEX_T_SYNC_UL,data_buf[INDEX_T_SYNC_UL]);
542
+    }
543
+    if(Prev_data[INDEX__T_SYNC_UL] != data_buf[INDEX__T_SYNC_UL]){
544
+        Prev_data[INDEX__T_SYNC_UL] = data_buf[INDEX__T_SYNC_UL];
545
+        Power_ON_OFF_Ctrl(INDEX__T_SYNC_UL,data_buf[INDEX__T_SYNC_UL]);
546
+    }
547
+
548
+
549
+    if((Prev_data[INDEX_DAC_VCtrl_A_H] != data_buf[INDEX_DAC_VCtrl_A_H])
550
+        ||(Prev_data[INDEX_DAC_VCtrl_A_L] != data_buf[INDEX_DAC_VCtrl_A_L])){
551
+        ADC_Modify = 1;
552
+        Prev_data[INDEX_DAC_VCtrl_A_H] = data_buf[INDEX_DAC_VCtrl_A_H];
553
+        Prev_data[INDEX_DAC_VCtrl_A_L] = data_buf[INDEX_DAC_VCtrl_A_L];
554
+    }
555
+    if((Prev_data[INDEX_DAC_VCtrl_B_H] != data_buf[INDEX_DAC_VCtrl_B_H])
556
+        ||(Prev_data[INDEX_DAC_VCtrl_B_L] != data_buf[INDEX_DAC_VCtrl_B_L])){
557
+        ADC_Modify = 1;
558
+        
559
+        Prev_data[INDEX_DAC_VCtrl_B_H] = data_buf[INDEX_DAC_VCtrl_B_H];
560
+        Prev_data[INDEX_DAC_VCtrl_B_L] = data_buf[INDEX_DAC_VCtrl_B_L];        
561
+    }    
562
+    if((Prev_data[INDEX_DAC_VCtrl_C_H] != data_buf[INDEX_DAC_VCtrl_C_H])
563
+        ||(Prev_data[INDEX_DAC_VCtrl_C_L] != data_buf[INDEX_DAC_VCtrl_C_L])){
564
+        ADC_Modify = 1;
565
+//        printf("Prev_data[INDEX_DAC_VCtrl_C_H] : %x \r\n",Prev_data[INDEX_DAC_VCtrl_C_H]);
566
+//        printf("Prev_data[INDEX_DAC_VCtrl_C_L] : %x \r\n",Prev_data[INDEX_DAC_VCtrl_C_L]);
567
+
568
+        Prev_data[INDEX_DAC_VCtrl_C_H] = data_buf[INDEX_DAC_VCtrl_C_H];
569
+        Prev_data[INDEX_DAC_VCtrl_C_L] = data_buf[INDEX_DAC_VCtrl_C_L];        
570
+    }
571
+    if((Prev_data[INDEX_DAC_VCtrl_D_H] != data_buf[INDEX_DAC_VCtrl_D_H])
572
+        ||(Prev_data[INDEX_DAC_VCtrl_D_L] != data_buf[INDEX_DAC_VCtrl_D_L])){
573
+        ADC_Modify = 1;
574
+        Prev_data[INDEX_DAC_VCtrl_D_H] = data_buf[INDEX_DAC_VCtrl_D_H];
575
+        Prev_data[INDEX_DAC_VCtrl_D_L] = data_buf[INDEX_DAC_VCtrl_D_L];
576
+    }
577
+    if((Prev_data[INDEX_DAC_VCtrl_E_H] != data_buf[INDEX_DAC_VCtrl_E_H])
578
+        ||(Prev_data[INDEX_DAC_VCtrl_E_L] != data_buf[INDEX_DAC_VCtrl_E_L])){
579
+        ADC_Modify = 1;
580
+
581
+        Prev_data[INDEX_DAC_VCtrl_E_H] = data_buf[INDEX_DAC_VCtrl_E_H];
582
+        Prev_data[INDEX_DAC_VCtrl_E_L] = data_buf[INDEX_DAC_VCtrl_E_L];        
583
+    }
584
+    if((Prev_data[INDEX_DAC_VCtrl_F_H] != data_buf[INDEX_DAC_VCtrl_F_H])
585
+        ||(Prev_data[INDEX_DAC_VCtrl_F_L] != data_buf[INDEX_DAC_VCtrl_F_L])){
586
+        ADC_Modify = 1;
587
+        Prev_data[INDEX_DAC_VCtrl_F_H] = data_buf[INDEX_DAC_VCtrl_F_H];
588
+        Prev_data[INDEX_DAC_VCtrl_F_L] = data_buf[INDEX_DAC_VCtrl_F_L];        
589
+    }
590
+    if((Prev_data[INDEX_DAC_VCtrl_G_H] != data_buf[INDEX_DAC_VCtrl_G_H])
591
+        ||(Prev_data[INDEX_DAC_VCtrl_G_L] != data_buf[INDEX_DAC_VCtrl_G_L])){
592
+        ADC_Modify = 1;
593
+        Prev_data[INDEX_DAC_VCtrl_G_H] = data_buf[INDEX_DAC_VCtrl_G_H];
594
+        Prev_data[INDEX_DAC_VCtrl_G_L] = data_buf[INDEX_DAC_VCtrl_G_L];        
595
+    }    
596
+    if((Prev_data[INDEX_DAC_VCtrl_H_H] != data_buf[INDEX_DAC_VCtrl_H_H])
597
+        ||(Prev_data[INDEX_DAC_VCtrl_H_L] != data_buf[INDEX_DAC_VCtrl_H_L])){
598
+        ADC_Modify = 1;
599
+        Prev_data[INDEX_DAC_VCtrl_H_H] = data_buf[INDEX_DAC_VCtrl_H_H];
600
+        Prev_data[INDEX_DAC_VCtrl_H_L] = data_buf[INDEX_DAC_VCtrl_H_L];        
601
+    }
602
+    if(ADC_Modify){
603
+//        AD5318_Ctrl(0xF000);
604
+//        HAL_Delay(1);
605
+//        AD5318_Ctrl(0x800C);
606
+//        AD5318_Ctrl(0x2FFF );
607
+//        AD5318_Ctrl(0xA000);
608
+//        printf("DAC CTRL START \r\n");
609
+//        AD5318_Ctrl(0x800C);
610
+//        AD5318_Ctrl(0xA000);
611
+//        printf("DAC Change\r\n");
612
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_A_H] << 8 | Prev_data[INDEX_DAC_VCtrl_A_L]));    
613
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_B_H] << 8 | Prev_data[INDEX_DAC_VCtrl_B_L]));    
614
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_C_H] << 8 | Prev_data[INDEX_DAC_VCtrl_C_L]));
615
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_D_H] << 8 | Prev_data[INDEX_DAC_VCtrl_D_L]));
616
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_E_H] << 8 | Prev_data[INDEX_DAC_VCtrl_E_L]));    
617
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_F_H] << 8 | Prev_data[INDEX_DAC_VCtrl_F_L]));
618
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_G_H] << 8 | Prev_data[INDEX_DAC_VCtrl_G_L]));
619
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_H_H] << 8 | Prev_data[INDEX_DAC_VCtrl_H_L]));
620
+    }
621
+    
622
+}
623
+
624
+uint8_t temp_crc = 0;
625
+bool RF_Ctrl_Main(uint8_t* data_buf){
626
+    bool ret = false;
627
+    Bluecell_Prot_t type = data_buf[Type];
628
+    ret = RF_Data_Check(&data_buf[Header]); /* ERROR CHECK */
629
+    if(ret == false){
630
+        HAL_UART_Transmit(&huart1,&data_buf[INDEX_BLUE_HEADER],data_buf[INDEX_BLUE_LENGTH] + 2 + 1,3000); 
631
+        return ret;
632
+    }
633
+    
634
+    switch(type){
635
+    case TYPE_BLUECELL_RESET:
636
+        for(uint8_t i =0 ; i < data_buf[Length] + 6; i++)
637
+            printf("%02x ",data_buf[i]);
638
+        printf("Reset Start \r\n");
639
+        NVIC_SystemReset();
640
+        break;
641
+    case TYPE_BLUECELL_SET:
642
+#if 0 // PYJ.2019.07.31_BEGIN -- 
643
+    printf("TYPE_BLUECELL_SET : ");
644
+    for(uint8_t i =0 ; i < INDEX_BLUE_EOF + 1; i++)
645
+        printf("%02x ",data_buf[i]);
646
+#endif // PYJ.2019.07.31_END -- 
647
+        RF_Operate(&data_buf[Header]);
648
+        RF_Status_Ack();
649
+
650
+//        ADF4153_Freq_Calc(3465500000,40000000,2,5000);
651
+//        ADF4153_Freq_Calc(3993450000,40000000,2,5000);
652
+//        halSynSetFreq(1995000000);
653
+//        halSynSetFreq(1600000000);
654
+//        halSynSetFreq(1455000000);        
655
+        break;
656
+    case TYPE_BLUECELL_GET:
657
+#if 0 // PYJ.2019.08.01_BEGIN -- 
658
+        printf("\r\nTYPE_BLUECELL_GET : \r\n");
659
+#endif // PYJ.2019.08.01_END -- 
660
+        RF_Status_Get();
661
+        break;
662
+    case TYPE_BLUECELL_SAVE:
663
+//        printf("\r\nFLASH Write\r\n");
664
+        Bluecell_Flash_Write(&Prev_data[INDEX_BLUE_HEADER]);
665
+        RF_Status_Ack();
666
+
667
+        break;
668
+        default:
669
+#ifdef DEBUG_PRINT // PYJ.2019.07.27_BEGIN --         
670
+            printf("Function : %s   LINE : %d    type : %d \r\n",__func__,__LINE__,type);
671
+#endif
672
+            break;
673
+    }
674
+    return ret;
675
+}

BIN
insight/STM32F103_ATTEN_PLL_Zig.si4project/STM32F103_ATTEN_PLL_Zig.sip_sym


BIN
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_BDA4601.h.sisc


BIN
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_BDA4601.c.sisc


BIN
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_main.c.sisc


BIN
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_zig_operate.c.sisc