瀏覽代碼

3.5G LOW 값 122.88 수정

YJ 5 年之前
父節點
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e22a9a8038

二進制
Debug/STM32F103_ATTEN_PLL_Zig.binary


二進制
Debug/STM32F103_ATTEN_PLL_Zig.elf


文件差異過大導致無法顯示
+ 935 - 938
Debug/STM32F103_ATTEN_PLL_Zig.hex


文件差異過大導致無法顯示
+ 4907 - 4916
Debug/STM32F103_ATTEN_PLL_Zig.list


+ 290 - 290
Debug/STM32F103_ATTEN_PLL_Zig.map

@@ -1303,7 +1303,7 @@ LOAD c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../l
1303 1303
                 0x08004000                g_pfnVectors
1304 1304
                 0x080041e4                . = ALIGN (0x4)
1305 1305
 
1306
-.text           0x080041e8     0x7d94
1306
+.text           0x080041e8     0x7d6c
1307 1307
                 0x080041e8                . = ALIGN (0x4)
1308 1308
  *(.text)
1309 1309
  .text          0x080041e8       0x40 c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/armv7-m/crtbegin.o
@@ -1798,361 +1798,361 @@ LOAD c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../l
1798 1798
                 0x08008af0       0x38 Src\zig_operate.o
1799 1799
                 0x08008af0                RF_Status_Ack
1800 1800
  .text.RF_Operate
1801
-                0x08008b28      0xa1c Src\zig_operate.o
1801
+                0x08008b28      0x9f4 Src\zig_operate.o
1802 1802
                 0x08008b28                RF_Operate
1803 1803
  .text.RF_Ctrl_Main
1804
-                0x08009544       0x9c Src\zig_operate.o
1805
-                0x08009544                RF_Ctrl_Main
1804
+                0x0800951c       0x9c Src\zig_operate.o
1805
+                0x0800951c                RF_Ctrl_Main
1806 1806
  .text.Reset_Handler
1807
-                0x080095e0       0x48 startup\startup_stm32f103xe.o
1808
-                0x080095e0                Reset_Handler
1807
+                0x080095b8       0x48 startup\startup_stm32f103xe.o
1808
+                0x080095b8                Reset_Handler
1809 1809
  .text.Default_Handler
1810
-                0x08009628        0x2 startup\startup_stm32f103xe.o
1811
-                0x08009628                RTC_Alarm_IRQHandler
1812
-                0x08009628                EXTI2_IRQHandler
1813
-                0x08009628                TIM8_TRG_COM_IRQHandler
1814
-                0x08009628                TIM8_CC_IRQHandler
1815
-                0x08009628                TIM1_CC_IRQHandler
1816
-                0x08009628                PVD_IRQHandler
1817
-                0x08009628                SDIO_IRQHandler
1818
-                0x08009628                EXTI3_IRQHandler
1819
-                0x08009628                EXTI0_IRQHandler
1820
-                0x08009628                I2C2_EV_IRQHandler
1821
-                0x08009628                ADC1_2_IRQHandler
1822
-                0x08009628                SPI1_IRQHandler
1823
-                0x08009628                TAMPER_IRQHandler
1824
-                0x08009628                TIM8_UP_IRQHandler
1825
-                0x08009628                DMA2_Channel2_IRQHandler
1826
-                0x08009628                USART3_IRQHandler
1827
-                0x08009628                RTC_IRQHandler
1828
-                0x08009628                DMA1_Channel7_IRQHandler
1829
-                0x08009628                CAN1_RX1_IRQHandler
1830
-                0x08009628                UART5_IRQHandler
1831
-                0x08009628                ADC3_IRQHandler
1832
-                0x08009628                TIM4_IRQHandler
1833
-                0x08009628                DMA2_Channel1_IRQHandler
1834
-                0x08009628                I2C1_EV_IRQHandler
1835
-                0x08009628                DMA1_Channel6_IRQHandler
1836
-                0x08009628                UART4_IRQHandler
1837
-                0x08009628                TIM3_IRQHandler
1838
-                0x08009628                RCC_IRQHandler
1839
-                0x08009628                TIM1_TRG_COM_IRQHandler
1840
-                0x08009628                Default_Handler
1841
-                0x08009628                EXTI15_10_IRQHandler
1842
-                0x08009628                TIM7_IRQHandler
1843
-                0x08009628                TIM5_IRQHandler
1844
-                0x08009628                EXTI9_5_IRQHandler
1845
-                0x08009628                SPI2_IRQHandler
1846
-                0x08009628                EXTI4_IRQHandler
1847
-                0x08009628                USB_LP_CAN1_RX0_IRQHandler
1848
-                0x08009628                USB_HP_CAN1_TX_IRQHandler
1849
-                0x08009628                DMA1_Channel3_IRQHandler
1850
-                0x08009628                FSMC_IRQHandler
1851
-                0x08009628                TIM1_UP_IRQHandler
1852
-                0x08009628                WWDG_IRQHandler
1853
-                0x08009628                TIM2_IRQHandler
1854
-                0x08009628                TIM1_BRK_IRQHandler
1855
-                0x08009628                EXTI1_IRQHandler
1856
-                0x08009628                DMA2_Channel4_5_IRQHandler
1857
-                0x08009628                USART2_IRQHandler
1858
-                0x08009628                I2C2_ER_IRQHandler
1859
-                0x08009628                DMA1_Channel2_IRQHandler
1860
-                0x08009628                TIM8_BRK_IRQHandler
1861
-                0x08009628                CAN1_SCE_IRQHandler
1862
-                0x08009628                FLASH_IRQHandler
1863
-                0x08009628                SPI3_IRQHandler
1864
-                0x08009628                I2C1_ER_IRQHandler
1865
-                0x08009628                USBWakeUp_IRQHandler
1866
-                0x08009628                DMA2_Channel3_IRQHandler
1867
- *fill*         0x0800962a        0x2 
1868
- .text.__errno  0x0800962c        0xc c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7-m\libc_nano.a(lib_a-errno.o)
1869
-                0x0800962c                __errno
1810
+                0x08009600        0x2 startup\startup_stm32f103xe.o
1811
+                0x08009600                RTC_Alarm_IRQHandler
1812
+                0x08009600                EXTI2_IRQHandler
1813
+                0x08009600                TIM8_TRG_COM_IRQHandler
1814
+                0x08009600                TIM8_CC_IRQHandler
1815
+                0x08009600                TIM1_CC_IRQHandler
1816
+                0x08009600                PVD_IRQHandler
1817
+                0x08009600                SDIO_IRQHandler
1818
+                0x08009600                EXTI3_IRQHandler
1819
+                0x08009600                EXTI0_IRQHandler
1820
+                0x08009600                I2C2_EV_IRQHandler
1821
+                0x08009600                ADC1_2_IRQHandler
1822
+                0x08009600                SPI1_IRQHandler
1823
+                0x08009600                TAMPER_IRQHandler
1824
+                0x08009600                TIM8_UP_IRQHandler
1825
+                0x08009600                DMA2_Channel2_IRQHandler
1826
+                0x08009600                USART3_IRQHandler
1827
+                0x08009600                RTC_IRQHandler
1828
+                0x08009600                DMA1_Channel7_IRQHandler
1829
+                0x08009600                CAN1_RX1_IRQHandler
1830
+                0x08009600                UART5_IRQHandler
1831
+                0x08009600                ADC3_IRQHandler
1832
+                0x08009600                TIM4_IRQHandler
1833
+                0x08009600                DMA2_Channel1_IRQHandler
1834
+                0x08009600                I2C1_EV_IRQHandler
1835
+                0x08009600                DMA1_Channel6_IRQHandler
1836
+                0x08009600                UART4_IRQHandler
1837
+                0x08009600                TIM3_IRQHandler
1838
+                0x08009600                RCC_IRQHandler
1839
+                0x08009600                TIM1_TRG_COM_IRQHandler
1840
+                0x08009600                Default_Handler
1841
+                0x08009600                EXTI15_10_IRQHandler
1842
+                0x08009600                TIM7_IRQHandler
1843
+                0x08009600                TIM5_IRQHandler
1844
+                0x08009600                EXTI9_5_IRQHandler
1845
+                0x08009600                SPI2_IRQHandler
1846
+                0x08009600                EXTI4_IRQHandler
1847
+                0x08009600                USB_LP_CAN1_RX0_IRQHandler
1848
+                0x08009600                USB_HP_CAN1_TX_IRQHandler
1849
+                0x08009600                DMA1_Channel3_IRQHandler
1850
+                0x08009600                FSMC_IRQHandler
1851
+                0x08009600                TIM1_UP_IRQHandler
1852
+                0x08009600                WWDG_IRQHandler
1853
+                0x08009600                TIM2_IRQHandler
1854
+                0x08009600                TIM1_BRK_IRQHandler
1855
+                0x08009600                EXTI1_IRQHandler
1856
+                0x08009600                DMA2_Channel4_5_IRQHandler
1857
+                0x08009600                USART2_IRQHandler
1858
+                0x08009600                I2C2_ER_IRQHandler
1859
+                0x08009600                DMA1_Channel2_IRQHandler
1860
+                0x08009600                TIM8_BRK_IRQHandler
1861
+                0x08009600                CAN1_SCE_IRQHandler
1862
+                0x08009600                FLASH_IRQHandler
1863
+                0x08009600                SPI3_IRQHandler
1864
+                0x08009600                I2C1_ER_IRQHandler
1865
+                0x08009600                USBWakeUp_IRQHandler
1866
+                0x08009600                DMA2_Channel3_IRQHandler
1867
+ *fill*         0x08009602        0x2 
1868
+ .text.__errno  0x08009604        0xc c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7-m\libc_nano.a(lib_a-errno.o)
1869
+                0x08009604                __errno
1870 1870
  .text.__libc_init_array
1871
-                0x08009638       0x48 c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7-m\libc_nano.a(lib_a-init.o)
1872
-                0x08009638                __libc_init_array
1873
- .text.memcpy   0x08009680       0x16 c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7-m\libc_nano.a(lib_a-memcpy-stub.o)
1874
-                0x08009680                memcpy
1875
- .text.memset   0x08009696       0x10 c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7-m\libc_nano.a(lib_a-memset.o)
1876
-                0x08009696                memset
1877
- .text.__cvt    0x080096a6       0xb8 c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7-m\libc_nano.a(lib_a-nano-vfprintf_float.o)
1878
-                0x080096a6                __cvt
1871
+                0x08009610       0x48 c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7-m\libc_nano.a(lib_a-init.o)
1872
+                0x08009610                __libc_init_array
1873
+ .text.memcpy   0x08009658       0x16 c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7-m\libc_nano.a(lib_a-memcpy-stub.o)
1874
+                0x08009658                memcpy
1875
+ .text.memset   0x0800966e       0x10 c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7-m\libc_nano.a(lib_a-memset.o)
1876
+                0x0800966e                memset
1877
+ .text.__cvt    0x0800967e       0xb8 c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7-m\libc_nano.a(lib_a-nano-vfprintf_float.o)
1878
+                0x0800967e                __cvt
1879 1879
  .text.__exponent
1880
-                0x0800975e       0x6a c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7-m\libc_nano.a(lib_a-nano-vfprintf_float.o)
1881
-                0x0800975e                __exponent
1880
+                0x08009736       0x6a c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7-m\libc_nano.a(lib_a-nano-vfprintf_float.o)
1881
+                0x08009736                __exponent
1882 1882
  .text._printf_float
1883
-                0x080097c8      0x470 c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7-m\libc_nano.a(lib_a-nano-vfprintf_float.o)
1884
-                0x080097c8                _printf_float
1883
+                0x080097a0      0x470 c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7-m\libc_nano.a(lib_a-nano-vfprintf_float.o)
1884
+                0x080097a0                _printf_float
1885 1885
  .text._printf_common
1886
-                0x08009c38       0xee c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7-m\libc_nano.a(lib_a-nano-vfprintf_i.o)
1887
-                0x08009c38                _printf_common
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- *fill*         0x08009d26        0x2 
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+                0x08009c10       0xee c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7-m\libc_nano.a(lib_a-nano-vfprintf_i.o)
1887
+                0x08009c10                _printf_common
1888
+ *fill*         0x08009cfe        0x2 
1889 1889
  .text._printf_i
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-                0x08009d28      0x240 c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7-m\libc_nano.a(lib_a-nano-vfprintf_i.o)
1891
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- .text.printf   0x08009f68       0x30 c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7-m\libc_nano.a(lib_a-printf.o)
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- .text._puts_r  0x08009f98       0xb8 c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7-m\libc_nano.a(lib_a-puts.o)
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- .text.puts     0x0800a050       0x10 c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7-m\libc_nano.a(lib_a-puts.o)
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- .text.setbuf   0x0800a060       0x10 c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7-m\libc_nano.a(lib_a-setbuf.o)
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- .text.setvbuf  0x0800a070      0x15c c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7-m\libc_nano.a(lib_a-setvbuf.o)
1902
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1890
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1893
+                0x08009f40                iprintf
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1899
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1900
+                0x0800a038                setbuf
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1902
+                0x0800a048                setvbuf
1903 1903
  .text.__swbuf_r
1904
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1905
-                0x0800a1cc                __swbuf_r
1904
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1905
+                0x0800a1a4                __swbuf_r
1906 1906
  .text.__swsetup_r
1907
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- *fill*         0x0800a464        0x4 
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1912
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1908
+                0x0800a248                __swsetup_r
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+ *fill*         0x0800a43c        0x4 
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1912
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1913 1913
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1914
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1918
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1918
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1921
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1920
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1921
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1922 1922
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1923
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1924 1924
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1925
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1928
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1930
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1925
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1928
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1930
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1931 1931
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1932
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1933
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1932
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1933
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1934 1934
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1935
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1936
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1935
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1936
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1937 1937
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1938
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1939
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1938
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1939
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1940 1940
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1941
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1942
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1943
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1944
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1945
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1946
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1947
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1948
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1949
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1950
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1941
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1942
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1943
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1944
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1945
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1946
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1948
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1949
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1950
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1951 1951
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1952
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1953
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1952
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1953
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1954 1954
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1955
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1956
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1955
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1956
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1958
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1959
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1960
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1961
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1958
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1959
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1960
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1961
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1963
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1964
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1965
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1963
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1964
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1966 1966
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1967
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1968
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1967
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1968
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1969 1969
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1970
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1971
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1972
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1973
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1974
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1975
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1976
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1977
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1971
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1972
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1973
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1974
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1975
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1976
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1977
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1978 1978
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1979
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1980
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1981
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1982
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1983
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1980
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1981
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1982
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1983
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1984 1984
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1985
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1986
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1986
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1987 1987
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1988
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1988
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1989 1989
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1990
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1991
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1991
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1992 1992
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1993
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1994
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1995
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1996
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1997
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1998
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1999
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1993
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1994
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1995
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1996
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1997
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1998
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1999
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2000 2000
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2001
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2002
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2003
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2004
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2002
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2004
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2005 2005
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2006
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2007
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2006
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2007
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2011
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2010
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2011
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2012 2012
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2013
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2014
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2013
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2014
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2015 2015
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2016
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2017
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2016
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2017
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2018 2018
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2019
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2020
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2020
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2037
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2045 2045
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2049 2049
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2050
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2055 2055
 
2056
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2058 2058
 
2059
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2062
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2064 2064
 
2065
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2071 2071
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  .rodata.__sf_fake_stdout
2100
-                0x0800c074       0x20 c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7-m\libc_nano.a(lib_a-findfp.o)
2101
-                0x0800c074                __sf_fake_stdout
2102
- *fill*         0x0800c094        0x4 
2100
+                0x0800c04c       0x20 c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7-m\libc_nano.a(lib_a-findfp.o)
2101
+                0x0800c04c                __sf_fake_stdout
2102
+ *fill*         0x0800c06c        0x4 
2103 2103
  .rodata.__mprec_bigtens
2104
-                0x0800c098       0x28 c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7-m\libc_nano.a(lib_a-mprec.o)
2105
-                0x0800c098                __mprec_bigtens
2104
+                0x0800c070       0x28 c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7-m\libc_nano.a(lib_a-mprec.o)
2105
+                0x0800c070                __mprec_bigtens
2106 2106
  .rodata.__mprec_tens
2107
-                0x0800c0c0       0xc8 c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7-m\libc_nano.a(lib_a-mprec.o)
2108
-                0x0800c0c0                __mprec_tens
2107
+                0x0800c098       0xc8 c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7-m\libc_nano.a(lib_a-mprec.o)
2108
+                0x0800c098                __mprec_tens
2109 2109
  .rodata.p05.6052
2110
-                0x0800c188        0xc c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7-m\libc_nano.a(lib_a-mprec.o)
2110
+                0x0800c160        0xc c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7-m\libc_nano.a(lib_a-mprec.o)
2111 2111
  .rodata._vfprintf_r.str1.1
2112
-                0x0800c194       0x11 c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7-m\libc_nano.a(lib_a-nano-vfprintf.o)
2112
+                0x0800c16c       0x11 c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7-m\libc_nano.a(lib_a-nano-vfprintf.o)
2113 2113
  .rodata._setlocale_r.str1.1
2114
-                0x0800c1a5        0x8 c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7-m\libc_nano.a(lib_a-locale.o)
2114
+                0x0800c17d        0x8 c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7-m\libc_nano.a(lib_a-locale.o)
2115 2115
                                   0x9 (size before relaxing)
2116 2116
  .rodata.str1.1
2117
-                0x0800c1ad        0x2 c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7-m\libc_nano.a(lib_a-locale.o)
2117
+                0x0800c185        0x2 c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7-m\libc_nano.a(lib_a-locale.o)
2118 2118
  .rodata._ctype_
2119
-                0x0800c1af      0x101 c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7-m\libc_nano.a(lib_a-ctype_.o)
2120
-                0x0800c1af                _ctype_
2121
-                0x0800c2b0                . = ALIGN (0x4)
2119
+                0x0800c187      0x101 c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7-m\libc_nano.a(lib_a-ctype_.o)
2120
+                0x0800c187                _ctype_
2121
+                0x0800c288                . = ALIGN (0x4)
2122 2122
 
2123 2123
 .ARM.extab
2124 2124
  *(.ARM.extab* .gnu.linkonce.armextab.*)
2125 2125
 
2126
-.ARM            0x0800c2b0        0x8
2127
-                0x0800c2b0                __exidx_start = .
2126
+.ARM            0x0800c288        0x8
2127
+                0x0800c288                __exidx_start = .
2128 2128
  *(.ARM.exidx*)
2129
- .ARM.exidx     0x0800c2b0        0x8 c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/armv7-m\libgcc.a(_udivmoddi4.o)
2130
-                0x0800c2b8                __exidx_end = .
2129
+ .ARM.exidx     0x0800c288        0x8 c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/armv7-m\libgcc.a(_udivmoddi4.o)
2130
+                0x0800c290                __exidx_end = .
2131 2131
 
2132
-.rel.dyn        0x0800c2b8        0x0
2133
- .rel.iplt      0x0800c2b8        0x0 c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/armv7-m/crtbegin.o
2132
+.rel.dyn        0x0800c290        0x0
2133
+ .rel.iplt      0x0800c290        0x0 c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/armv7-m/crtbegin.o
2134 2134
 
2135
-.preinit_array  0x0800c2b8        0x0
2136
-                0x0800c2b8                PROVIDE (__preinit_array_start, .)
2135
+.preinit_array  0x0800c290        0x0
2136
+                0x0800c290                PROVIDE (__preinit_array_start, .)
2137 2137
  *(.preinit_array*)
2138
-                0x0800c2b8                PROVIDE (__preinit_array_end, .)
2138
+                0x0800c290                PROVIDE (__preinit_array_end, .)
2139 2139
 
2140
-.init_array     0x0800c2b8        0x4
2141
-                0x0800c2b8                PROVIDE (__init_array_start, .)
2140
+.init_array     0x0800c290        0x4
2141
+                0x0800c290                PROVIDE (__init_array_start, .)
2142 2142
  *(SORT(.init_array.*))
2143 2143
  *(.init_array*)
2144
- .init_array    0x0800c2b8        0x4 c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/armv7-m/crtbegin.o
2145
-                0x0800c2bc                PROVIDE (__init_array_end, .)
2144
+ .init_array    0x0800c290        0x4 c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/armv7-m/crtbegin.o
2145
+                0x0800c294                PROVIDE (__init_array_end, .)
2146 2146
 
2147
-.fini_array     0x0800c2bc        0x4
2147
+.fini_array     0x0800c294        0x4
2148 2148
                 [!provide]                PROVIDE (__fini_array_start, .)
2149 2149
  *(SORT(.fini_array.*))
2150 2150
  *(.fini_array*)
2151
- .fini_array    0x0800c2bc        0x4 c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/armv7-m/crtbegin.o
2151
+ .fini_array    0x0800c294        0x4 c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/armv7-m/crtbegin.o
2152 2152
                 [!provide]                PROVIDE (__fini_array_end, .)
2153
-                0x0800c2c0                _sidata = LOADADDR (.data)
2153
+                0x0800c298                _sidata = LOADADDR (.data)
2154 2154
 
2155
-.data           0x20000000      0x41c load address 0x0800c2c0
2155
+.data           0x20000000      0x41c load address 0x0800c298
2156 2156
                 0x20000000                . = ALIGN (0x4)
2157 2157
                 0x20000000                _sdata = .
2158 2158
  *(.data)
@@ -2250,11 +2250,11 @@ LOAD c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../l
2250 2250
                 0x2000041c                . = ALIGN (0x4)
2251 2251
                 0x2000041c                _edata = .
2252 2252
 
2253
-.igot.plt       0x2000041c        0x0 load address 0x0800c6dc
2253
+.igot.plt       0x2000041c        0x0 load address 0x0800c6b4
2254 2254
  .igot.plt      0x2000041c        0x0 c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/armv7-m/crtbegin.o
2255 2255
                 0x2000041c                . = ALIGN (0x4)
2256 2256
 
2257
-.bss            0x20000420     0x13c4 load address 0x0800c6dc
2257
+.bss            0x20000420     0x13c4 load address 0x0800c6b4
2258 2258
                 0x20000420                _sbss = .
2259 2259
                 0x20000420                __bss_start__ = _sbss
2260 2260
  *(.bss)
@@ -2320,7 +2320,7 @@ LOAD c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../l
2320 2320
                 0x200017e4                __bss_end__ = _ebss
2321 2321
 
2322 2322
 ._user_heap_stack
2323
-                0x200017e4      0x600 load address 0x0800c6dc
2323
+                0x200017e4      0x600 load address 0x0800c6b4
2324 2324
                 0x200017e4                . = ALIGN (0x4)
2325 2325
                 0x200017e4                PROVIDE (end, .)
2326 2326
                 [!provide]                PROVIDE (_end, .)
@@ -2514,7 +2514,7 @@ LOAD c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../l
2514 2514
                 0x00000ec4       0x1d c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/armv7-m/crtn.o
2515 2515
 OUTPUT(STM32F103_ATTEN_PLL_Zig.elf elf32-littlearm)
2516 2516
 
2517
-.debug_info     0x00000000    0x2556e
2517
+.debug_info     0x00000000    0x25539
2518 2518
  .debug_info    0x00000000     0x102e Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal.o
2519 2519
  .debug_info    0x0000102e     0x16a1 Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_adc.o
2520 2520
  .debug_info    0x000026cf     0x138b Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_adc_ex.o
@@ -2532,20 +2532,20 @@ OUTPUT(STM32F103_ATTEN_PLL_Zig.elf elf32-littlearm)
2532 2532
  .debug_info    0x000130cd      0xe76 Src\BDA4601.o
2533 2533
  .debug_info    0x00013f43      0xb55 Src\CRC16.o
2534 2534
  .debug_info    0x00014a98     0x1080 Src\PE43711.o
2535
- .debug_info    0x00015b18     0x184b Src\adf4153.o
2536
- .debug_info    0x00017363     0x1219 Src\flash.o
2537
- .debug_info    0x0001857c     0x175b Src\includes.o
2538
- .debug_info    0x00019cd7     0x2660 Src\main.o
2539
- .debug_info    0x0001c337     0x14e7 Src\pll_4113.o
2540
- .debug_info    0x0001d81e     0x1a08 Src\stm32f1xx_hal_msp.o
2541
- .debug_info    0x0001f226     0x11ef Src\stm32f1xx_it.o
2542
- .debug_info    0x00020415      0xfe1 Src\syscalls.o
2543
- .debug_info    0x000213f6      0xc4d Src\system_stm32f1xx.o
2544
- .debug_info    0x00022043     0x141e Src\uart.o
2545
- .debug_info    0x00023461     0x209c Src\zig_operate.o
2546
- .debug_info    0x000254fd       0x71 startup\startup_stm32f103xe.o
2535
+ .debug_info    0x00015b18     0x183f Src\adf4153.o
2536
+ .debug_info    0x00017357     0x1219 Src\flash.o
2537
+ .debug_info    0x00018570     0x175b Src\includes.o
2538
+ .debug_info    0x00019ccb     0x2660 Src\main.o
2539
+ .debug_info    0x0001c32b     0x14e7 Src\pll_4113.o
2540
+ .debug_info    0x0001d812     0x1a08 Src\stm32f1xx_hal_msp.o
2541
+ .debug_info    0x0001f21a     0x11ef Src\stm32f1xx_it.o
2542
+ .debug_info    0x00020409      0xfe1 Src\syscalls.o
2543
+ .debug_info    0x000213ea      0xc4d Src\system_stm32f1xx.o
2544
+ .debug_info    0x00022037     0x141e Src\uart.o
2545
+ .debug_info    0x00023455     0x2073 Src\zig_operate.o
2546
+ .debug_info    0x000254c8       0x71 startup\startup_stm32f103xe.o
2547 2547
 
2548
-.debug_abbrev   0x00000000     0x5046
2548
+.debug_abbrev   0x00000000     0x5055
2549 2549
  .debug_abbrev  0x00000000      0x315 Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal.o
2550 2550
  .debug_abbrev  0x00000315      0x2fb Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_adc.o
2551 2551
  .debug_abbrev  0x00000610      0x296 Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_adc_ex.o
@@ -2573,10 +2573,10 @@ OUTPUT(STM32F103_ATTEN_PLL_Zig.elf elf32-littlearm)
2573 2573
  .debug_abbrev  0x0000455b      0x2d9 Src\syscalls.o
2574 2574
  .debug_abbrev  0x00004834      0x1eb Src\system_stm32f1xx.o
2575 2575
  .debug_abbrev  0x00004a1f      0x2be Src\uart.o
2576
- .debug_abbrev  0x00004cdd      0x357 Src\zig_operate.o
2577
- .debug_abbrev  0x00005034       0x12 startup\startup_stm32f103xe.o
2576
+ .debug_abbrev  0x00004cdd      0x366 Src\zig_operate.o
2577
+ .debug_abbrev  0x00005043       0x12 startup\startup_stm32f103xe.o
2578 2578
 
2579
-.debug_loc      0x00000000     0x9d58
2579
+.debug_loc      0x00000000     0x9d1a
2580 2580
  .debug_loc     0x00000000      0x11b Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal.o
2581 2581
  .debug_loc     0x0000011b      0x87e Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_adc.o
2582 2582
  .debug_loc     0x00000999      0x769 Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_adc_ex.o
@@ -2603,7 +2603,7 @@ OUTPUT(STM32F103_ATTEN_PLL_Zig.elf elf32-littlearm)
2603 2603
  .debug_loc     0x00009358      0x3ef Src\syscalls.o
2604 2604
  .debug_loc     0x00009747       0xcd Src\system_stm32f1xx.o
2605 2605
  .debug_loc     0x00009814      0x113 Src\uart.o
2606
- .debug_loc     0x00009927      0x431 Src\zig_operate.o
2606
+ .debug_loc     0x00009927      0x3f3 Src\zig_operate.o
2607 2607
 
2608 2608
 .debug_aranges  0x00000000      0xe38
2609 2609
  .debug_aranges
@@ -2696,7 +2696,7 @@ OUTPUT(STM32F103_ATTEN_PLL_Zig.elf elf32-littlearm)
2696 2696
  .debug_ranges  0x000011b0       0x48 Src\zig_operate.o
2697 2697
  .debug_ranges  0x000011f8       0x20 startup\startup_stm32f103xe.o
2698 2698
 
2699
-.debug_line     0x00000000     0x9906
2699
+.debug_line     0x00000000     0x990a
2700 2700
  .debug_line    0x00000000      0x45f Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal.o
2701 2701
  .debug_line    0x0000045f      0x863 Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_adc.o
2702 2702
  .debug_line    0x00000cc2      0x737 Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_adc_ex.o
@@ -2724,8 +2724,8 @@ OUTPUT(STM32F103_ATTEN_PLL_Zig.elf elf32-littlearm)
2724 2724
  .debug_line    0x000088c7      0x3c0 Src\syscalls.o
2725 2725
  .debug_line    0x00008c87      0x2bf Src\system_stm32f1xx.o
2726 2726
  .debug_line    0x00008f46      0x3c6 Src\uart.o
2727
- .debug_line    0x0000930c      0x57d Src\zig_operate.o
2728
- .debug_line    0x00009889       0x7d startup\startup_stm32f103xe.o
2727
+ .debug_line    0x0000930c      0x581 Src\zig_operate.o
2728
+ .debug_line    0x0000988d       0x7d startup\startup_stm32f103xe.o
2729 2729
 
2730 2730
 .debug_str      0x00000000     0x58a5
2731 2731
  .debug_str     0x00000000      0xc6c Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal.o

二進制
Debug/Src/adf4153.o


二進制
Debug/Src/zig_operate.o


+ 1 - 1
Debug/Src/zig_operate.su

@@ -2,4 +2,4 @@ zig_operate.c:201:6:RF_Data_Check	8	static
2 2
 zig_operate.c:234:6:RF_Status_Get	8	static
3 3
 zig_operate.c:248:6:RF_Status_Ack	8	static
4 4
 zig_operate.c:262:6:RF_Operate	184	static
5
-zig_operate.c:708:6:RF_Ctrl_Main	16	static
5
+zig_operate.c:710:6:RF_Ctrl_Main	16	static

+ 12 - 12
Src/adf4153.c

@@ -337,9 +337,9 @@ void ADF4153_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2,
337 337
             printf("0");
338 338
 #endif /* DEBUG_PRINT */
339 339
         }
340
-        Pol_Delay_us(50);
340
+        Pol_Delay_us(10);
341 341
         HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
342
-        Pol_Delay_us(50);
342
+        Pol_Delay_us(10);
343 343
         HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
344 344
         R3 = (R3 << 1);
345 345
     }
@@ -347,7 +347,7 @@ void ADF4153_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2,
347 347
     printf("\r\n");
348 348
 #endif /* DEBUG_PRINT */
349 349
     HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
350
-      Pol_Delay_us(50);
350
+      Pol_Delay_us(10);
351 351
     HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
352 352
     
353 353
     /*   R2 Ctrl    */
@@ -364,9 +364,9 @@ void ADF4153_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2,
364 364
              printf("0");
365 365
 #endif /* DEBUG_PRINT */
366 366
          }
367
-         Pol_Delay_us(50);
367
+         Pol_Delay_us(10);
368 368
          HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
369
-         Pol_Delay_us(50);
369
+         Pol_Delay_us(10);
370 370
          HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
371 371
 
372 372
          R2 = ((R2 << 1) & 0x00FFFF);
@@ -375,7 +375,7 @@ void ADF4153_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2,
375 375
      printf("\r\n");
376 376
 #endif /* DEBUG_PRINT */
377 377
      HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
378
-      Pol_Delay_us(50);
378
+      Pol_Delay_us(10);
379 379
      HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
380 380
     
381 381
      /*   R1 Ctrl    */
@@ -392,9 +392,9 @@ void ADF4153_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2,
392 392
             printf("0");
393 393
 #endif /* DEBUG_PRINT */
394 394
         }
395
-        Pol_Delay_us(50);
395
+        Pol_Delay_us(10);
396 396
         HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
397
-        Pol_Delay_us(50);
397
+        Pol_Delay_us(10);
398 398
         HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
399 399
 
400 400
         R1 = ((R1 << 1) & 0xFFFFFF);
@@ -403,7 +403,7 @@ void ADF4153_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2,
403 403
     printf("\r\n");
404 404
 #endif /* DEBUG_PRINT */
405 405
     HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
406
-      Pol_Delay_us(50);
406
+      Pol_Delay_us(10);
407 407
     HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
408 408
 
409 409
 
@@ -422,9 +422,9 @@ void ADF4153_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2,
422 422
             printf("0");
423 423
 #endif /* DEBUG_PRINT */
424 424
         }
425
-        Pol_Delay_us(50);
425
+        Pol_Delay_us(10);
426 426
         HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
427
-        Pol_Delay_us(50);
427
+        Pol_Delay_us(10);
428 428
         HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
429 429
 
430 430
         R0 = ((R0 << 1) & 0xFFFFFF);
@@ -434,7 +434,7 @@ void ADF4153_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2,
434 434
 #endif /* DEBUG_PRINT */
435 435
     HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
436 436
     HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
437
-    Pol_Delay_us(50);
437
+    Pol_Delay_us(10);
438 438
     HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
439 439
 
440 440
 }

+ 12 - 10
Src/zig_operate.c

@@ -25,12 +25,12 @@ uint8_t Flash_Save_data[INDEX_BLUE_EOF + 1];
25 25
 
26 26
 /* * * * * * * #define Struct* * * * * * * */
27 27
 PLL_Setting_st Pll_1_8GHz_DL = {
28
-	PLL_CLK_GPIO_Port,
29
-	PLL_CLK_Pin,
30
-	PLL_DATA_GPIO_Port,
31
-	PLL_DATA_Pin,
32
-    PLL_EN_1_8G_DL_GPIO_Port,    
33
-    PLL_EN_1_8G_DL_Pin,
28
+  PLL_CLK_GPIO_Port,
29
+  PLL_CLK_Pin,
30
+  PLL_DATA_GPIO_Port,
31
+  PLL_DATA_Pin,
32
+  PLL_EN_1_8G_DL_GPIO_Port,    
33
+  PLL_EN_1_8G_DL_Pin,
34 34
 };
35 35
 PLL_Setting_st Pll_1_8GHz_UL = {
36 36
     PLL_CLK_GPIO_Port,
@@ -403,7 +403,9 @@ void RF_Operate(uint8_t* data_buf){
403 403
 #else
404 404
         temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
405 405
 #endif // PYJ.2019.08.12_END -- 
406
-        ADF4153_Module_Ctrl(Pll_3_5_L,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
406
+//        ADF4153_Module_Ctrl(Pll_3_5_L,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
407
+      ADF4153_Module_Ctrl(Pll_3_5_L,0x385E48,0x163001,0x1442,3);
408
+
407 409
     }
408 410
     if((Prev_data[INDEX_PLL_3_5G_HIGH_H] != data_buf[INDEX_PLL_3_5G_HIGH_H])
409 411
         || (Prev_data[INDEX_PLL_3_5G_HIGH_M] != data_buf[INDEX_PLL_3_5G_HIGH_M])
@@ -420,7 +422,7 @@ void RF_Operate(uint8_t* data_buf){
420 422
         temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
421 423
 #endif // PYJ.2019.08.12_END -- 
422 424
 //        ADF4153_Module_Ctrl(Pll_3_5_H,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
423
-
425
+        ADF4153_Module_Ctrl(Pll_3_5_H,0x4006C0,0x163001,0x14C2,3);
424 426
     }
425 427
     if(Prev_data[INDEX_PLL_LD_6_BIT] != data_buf[INDEX_PLL_LD_6_BIT]){
426 428
 
@@ -582,7 +584,7 @@ void RF_Operate(uint8_t* data_buf){
582 584
             temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
583 585
 #endif // PYJ.2019.08.12_END -- 
584 586
 //            ADF4153_Module_Ctrl(Pll_3_5_H,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
585
-            ADF4153_Module_Ctrl(Pll_3_5_H,0x4006C0,0x163001,0x1642,3);
587
+//            ADF4153_Module_Ctrl(Pll_3_5_H,0x4006C0,0x163001,0x14C2,3);
586 588
 
587 589
             PE43711_ALL_atten_ctrl(ALL_ATT_3_5G);
588 590
         }
@@ -606,7 +608,7 @@ void RF_Operate(uint8_t* data_buf){
606 608
 #else
607 609
           temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);            
608 610
 #endif // PYJ.2019.08.12_END -- 
609
-            ADF4153_Module_Ctrl(Pll_3_5_L,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
611
+//            ADF4153_Module_Ctrl(Pll_3_5_L,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
610 612
             PE43711_ALL_atten_ctrl(ALL_ATT_3_5G);
611 613
         }
612 614
     }

+ 440 - 0
insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/adf4153(4358).c

@@ -0,0 +1,440 @@
1
+/******************************************************************************
2
+*   @file   ADF4153.c
3
+*   @brief  Implementation of ADF4153 Driver for Microblaze processor.
4
+*   @author Istvan Csomortani (istvan.csomortani@analog.com)
5
+*
6
+*******************************************************************************
7
+* Copyright 2013(c) Analog Devices, Inc.
8
+*
9
+* All rights reserved.
10
+*
11
+* Redistribution and use in source and binary forms, with or without modification,
12
+* are permitted provided that the following conditions are met:
13
+*  - Redistributions of source code must retain the above copyright
14
+*    notice, this list of conditions and the following disclaimer.
15
+*  - Redistributions in binary form must reproduce the above copyright
16
+*    notice, this list of conditions and the following disclaimer in
17
+*    the documentation and/or other materials provided with the
18
+*    distribution.
19
+*  - Neither the name of Analog Devices, Inc. nor the names of its
20
+*    contributors may be used to endorse or promote products derived
21
+*    from this software without specific prior written permission.
22
+*  - The use of this software may or may not infringe the patent rights
23
+*    of one or more patent holders.  This license does not release you
24
+*    from the requirement that you obtain separate licenses from these
25
+*    patent holders to use this software.
26
+*  - Use of the software either in source or binary form, must be run
27
+*    on or directly connected to an Analog Devices Inc. component.
28
+*
29
+* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED
30
+* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY
31
+* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
32
+* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
34
+* INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
35
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
36
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
38
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39
+*
40
+******************************************************************************/
41
+
42
+/*****************************************************************************/
43
+/****************************** Include Files ********************************/
44
+/*****************************************************************************/
45
+#include "adf4153.h"
46
+#include "zig_operate.h"
47
+#include "main.h"
48
+#include "pll_4113.h"
49
+
50
+extern void Pol_Delay_us(volatile uint32_t microseconds);
51
+typedef struct _adf4153_st{
52
+    unsigned long long PFD_Value;
53
+    uint16_t MOD_Value;
54
+    uint32_t FRAC_Value;
55
+    uint16_t INT_Value;    
56
+    double N_Value;
57
+}adf4153_st;
58
+extern PLL_Setting_st Pll_3_5_H;
59
+extern PLL_Setting_st Pll_3_5_L;
60
+
61
+uint32_t pow2(uint32_t val,int32_t val2){
62
+    for(uint8_t i = 0; i < val2 - 1; i++){
63
+        val = val * val;
64
+    }
65
+
66
+    return val;
67
+}
68
+
69
+double round_up( double value, int pos )
70
+{
71
+    double temp;
72
+    temp = value * pow2( 10, pos );  // �썝�븯�뒗 �냼�닔�젏 �옄由ъ닔留뚰겮 10�쓽 �늻�듅�쓣 �븿
73
+    temp =  (int)(temp + 0.5);          // 0.5瑜� �뜑�븳�썑 踰꾨┝�븯硫� 諛섏삱由쇱씠 �맖
74
+    temp *= pow2( 10, -pos );           // �떎�떆 �썝�옒 �냼�닔�젏 �옄由ъ닔濡�
75
+
76
+    return temp;
77
+}
78
+
79
+
80
+double N_Reg_Value_Calc(double val){
81
+    return  val / 1000;
82
+}
83
+uint32_t N_Divider_Reg_Create(uint16_t _FRAC,uint16_t _INT,uint8_t _FASTLOCK){
84
+    uint32_t ret = 0;
85
+    uint32_t shift_bit = 0x01;
86
+    uint8_t control_bit = 0;
87
+    uint8_t i = 0;
88
+#ifdef DEBUG_PRINT
89
+    printf("FRAC : %d INT : %d \r\n",(int)_FRAC,_INT);
90
+#endif /* DEBUG_PRINT */
91
+    for(i = 0; i < 2; i++){
92
+        if(control_bit & 0x01)
93
+            ret += shift_bit << i;
94
+        control_bit = control_bit >> 1;
95
+    }
96
+#ifdef DEBUG_PRINT
97
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);
98
+#endif /* DEBUG_PRINT */
99
+    for(i = 2; i < 14; i++){
100
+        if(_FRAC & 0x01)
101
+            ret += shift_bit << i;
102
+        _FRAC = _FRAC >> 1;
103
+    }
104
+#ifdef DEBUG_PRINT
105
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);    
106
+#endif /* DEBUG_PRINT */
107
+    for(i = 14; i < 22; i++){
108
+        if(_INT & 0x01)
109
+            ret += shift_bit << i;
110
+        _INT = _INT >> 1;
111
+    }  
112
+#ifdef DEBUG_PRINT
113
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);    
114
+#endif /* DEBUG_PRINT */
115
+    if(_FASTLOCK & 0x01)
116
+            ret += shift_bit << i;
117
+#ifdef DEBUG_PRINT
118
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);
119
+#endif /* DEBUG_PRINT */
120
+
121
+    return ret;
122
+}
123
+uint32_t R_Divider_Reg_Create(uint16_t _MOD,uint8_t _RCOUNTER,uint8_t _PRESCALER,uint8_t _RESERVED,uint8_t _MUXOUT,uint8_t LOAD_CONTROL){
124
+    uint32_t ret = 0;
125
+    uint32_t shift_bit = 0x01;
126
+    uint8_t control_bit = 1;
127
+    uint8_t i = 0;
128
+#ifdef DEBUG_PRINT
129
+    printf("_MOD : %d INT : %d \r\n",_MOD,_RCOUNTER);
130
+#endif /* DEBUG_PRINT */
131
+
132
+#ifdef DEBUG_PRINT
133
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);
134
+#endif /* DEBUG_PRINT */
135
+    for(i = 0; i < 2; i++){
136
+        if(control_bit & 0x01)
137
+            ret += shift_bit << i;
138
+        control_bit = control_bit >> 1;
139
+    }
140
+#ifdef DEBUG_PRINT
141
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);
142
+#endif /* DEBUG_PRINT */
143
+    for(i = 2; i < 14; i++){
144
+        if(_MOD & 0x01)
145
+            ret += shift_bit << i;
146
+        _MOD = _MOD >> 1;
147
+    }
148
+    for(i = 14; i < 18; i++){
149
+        if(_RCOUNTER & 0x01)
150
+            ret += shift_bit << i;
151
+        _RCOUNTER = _RCOUNTER >> 1;
152
+    }  
153
+    if(_PRESCALER & 0x01)
154
+            ret += shift_bit << i++;
155
+    if(_RESERVED & 0x01)
156
+            ret += shift_bit << i++;
157
+    for(i = 19; i < 22; i++){
158
+        if(_MUXOUT & 0x01)
159
+            ret += shift_bit << i;
160
+        _MUXOUT = _MUXOUT >> 1;
161
+    }   
162
+    if(LOAD_CONTROL & 0x01)
163
+        ret += shift_bit << i++;
164
+
165
+    return ret;
166
+}
167
+
168
+ADF4153_R_N_Reg_st ADF4153_Freq_Calc(unsigned long long Freq,unsigned long long REFin,uint8_t R_Counter,uint32_t chspacing){
169
+    adf4153_st temp_adf4153;
170
+    double temp = 0;
171
+    ADF4153_R_N_Reg_st temp_reg;
172
+    temp_adf4153.PFD_Value  =  REFin / (R_Counter * 1000);
173
+    temp_adf4153.MOD_Value  =  (temp_adf4153.PFD_Value / chspacing) * 1000;
174
+    temp_adf4153.N_Value    =  N_Reg_Value_Calc(((double)(Freq / 1000) /  (double)(temp_adf4153.PFD_Value / 1000)));
175
+    temp_adf4153.INT_Value  =   temp_adf4153.N_Value ;
176
+#ifdef DEBUG_PRINT
177
+    printf("\r\ntemp_adf4153.N_Value : %f  temp_adf4153.INT_Value : %f  temp_adf4153.MOD_Value : %f \r\n",temp_adf4153.N_Value,(double)temp_adf4153.INT_Value,(double)temp_adf4153.MOD_Value);
178
+#endif /* DEBUG_PRINT */
179
+    temp = temp_adf4153.N_Value - (double)temp_adf4153.INT_Value;
180
+#ifdef DEBUG_PRINT
181
+    printf("\r\n temp_adf4153.N_Value - (double)temp_adf4153.INT_Value) : %f  temp * (double)temp_adf4153.MOD_Value : %f \r\n",temp,temp * (double)temp_adf4153.MOD_Value);
182
+#endif /* DEBUG_PRINT */
183
+    temp_adf4153.FRAC_Value =  (float)temp * temp_adf4153.MOD_Value;
184
+   
185
+#ifdef DEBUG_PRINT
186
+    printf("\r\ntemp_adf4153.N_Value : %x   : %f ",temp_adf4153.N_Value,((double)(Freq / 1000) /  (double)(temp_adf4153.PFD_Value / 1000)) / 1000);
187
+    printf("temp_adf4153.MOD_Value : %x   : %d \r\n",temp_adf4153.MOD_Value,temp_adf4153.MOD_Value);
188
+#endif /* DEBUG_PRINT */
189
+    uint16_t tempmod = temp_adf4153.FRAC_Value;
190
+    for(uint8_t i = 0; i < 12; i++){
191
+#ifdef DEBUG_PRINT
192
+        if(temp_adf4153.MOD_Value & 0x800){
193
+            printf("1");
194
+        }else{
195
+            printf("0");
196
+        }
197
+#endif /* DEBUG_PRINT */
198
+        tempmod = tempmod << 1;
199
+    }
200
+#ifdef DEBUG_PRINT
201
+    printf("\r\n");
202
+    printf("temp_adf4153.FRAC_Value : %x   : %d\r\n",temp_adf4153.FRAC_Value,temp_adf4153.FRAC_Value);
203
+#endif /* DEBUG_PRINT */
204
+    uint16_t tempfrac = temp_adf4153.FRAC_Value;
205
+    for(uint8_t i = 0; i < 12; i++){
206
+#ifdef DEBUG_PRINT
207
+        if(tempfrac & 0x800){
208
+            printf("1");
209
+        }else{
210
+            printf("0");
211
+        }
212
+#endif /* DEBUG_PRINT */
213
+        tempfrac = tempfrac << 1;
214
+    }
215
+#ifdef DEBUG_PRINT
216
+    printf("\r\n");    
217
+#endif /* DEBUG_PRINT */
218
+#ifdef DEBUG_PRINT
219
+    printf("temp_adf4153.INT_Value : %x   : %d\r\n",temp_adf4153.INT_Value,temp_adf4153.INT_Value); 
220
+#endif /* DEBUG_PRINT */
221
+    uint16_t tempint = temp_adf4153.INT_Value;
222
+    for(uint8_t i = 0; i < 9; i++){
223
+#ifdef DEBUG_PRINT
224
+        if(tempint & 0x100){
225
+            printf("1");
226
+        }else{
227
+            printf("0");
228
+        }
229
+#endif /* DEBUG_PRINT */
230
+        tempint = tempint << 1;
231
+    }
232
+#ifdef DEBUG_PRINT
233
+    printf("\r\n");    
234
+
235
+    printf("R0: %x  R1: %x \r\n",N_Divider_Reg_Create(temp_adf4153.FRAC_Value,temp_adf4153.INT_Value,0),R_Divider_Reg_Create(temp_adf4153.MOD_Value,R_Counter,1,0,2,0));   
236
+#endif /* DEBUG_PRINT */
237
+    temp_reg.N_reg = N_Divider_Reg_Create(temp_adf4153.FRAC_Value,temp_adf4153.INT_Value,0);
238
+    temp_reg.R_reg = R_Divider_Reg_Create(temp_adf4153.MOD_Value,R_Counter,1,0,2,0);
239
+
240
+    return temp_reg;
241
+//    R_Divider_Reg_Create(temp_adf4153.MOD_Value,R_Counter,1,0,1,0); //prescaler 1 : 8/9 0: 4/5
242
+}
243
+void ADF4153_Initialize(void){
244
+#if 0 // PYJ.2019.08.09_BEGIN -- 
245
+PLL_Setting_st Pll_test = {
246
+      PLL_CLK_3_5G_GPIO_Port,
247
+      PLL_CLK_3_5G_Pin,
248
+      PLL_DATA_3_5G_GPIO_Port,
249
+      PLL_DATA_3_5G_Pin,
250
+    PLL_EN_3_5G_L_GPIO_Port,    
251
+    PLL_EN_3_5G_L_Pin,
252
+  };
253
+PLL_Setting_st Pll_test2 = {
254
+    PLL_CLK_3_5G_GPIO_Port,
255
+    PLL_CLK_3_5G_Pin,
256
+    PLL_DATA_3_5G_GPIO_Port,
257
+    PLL_DATA_3_5G_Pin,
258
+    PLL_EN_3_5G_H_GPIO_Port,    
259
+    PLL_EN_3_5G_H_Pin,
260
+  };          
261
+    //  ADF4153_Module_Ctrl(Pll_test,0x2B44B0,0x14BE81,0x0013C2,0x000003);
262
+      ADF4153_R_N_Reg_st temp_reg;
263
+      temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
264
+      ADF4153_Module_Ctrl(Pll_test,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);      
265
+    
266
+      HAL_Delay(1);
267
+#ifdef DEBUG_PRINT
268
+        printf("\r\nPLL_EN_3_5G_H_GPIO_Port\r\n");
269
+#endif /* DEBUG_PRINT */
270
+   
271
+        temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
272
+        ADF4153_Module_Ctrl(Pll_test2,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);                  
273
+    //  ADF4153_Module_Ctrl(Pll_test2,0x313840,0x14BE81,0x13C2,0x3);
274
+      HAL_Delay(1);
275
+#endif // PYJ.2019.08.09_END -- 
276
+  if(  Flash_Save_data[INDEX_PLL_3_5G_LOW_H] == 0 
277
+    && Flash_Save_data[INDEX_PLL_3_5G_LOW_M] == 0
278
+    &&Flash_Save_data[INDEX_PLL_3_5G_LOW_L] == 0)
279
+  {
280
+    Flash_Save_data[INDEX_PLL_3_5G_LOW_H] = ((34655 & 0xFF0000) >> 16);
281
+    Flash_Save_data[INDEX_PLL_3_5G_LOW_M] = ((34655 & 0x00FF00) >> 8);
282
+    Flash_Save_data[INDEX_PLL_3_5G_LOW_L] = (34655 & 0x0000FF);
283
+  }
284
+  if(Flash_Save_data[INDEX_PLL_3_5G_HIGH_H] == 0 
285
+    && Flash_Save_data[INDEX_PLL_3_5G_HIGH_M] == 0 
286
+    && Flash_Save_data[INDEX_PLL_3_5G_HIGH_L] == 0)
287
+  {
288
+    Flash_Save_data[INDEX_PLL_3_5G_HIGH_H] = ((39345 & 0xFF0000) >> 16);
289
+    Flash_Save_data[INDEX_PLL_3_5G_HIGH_M] = ((39345 & 0x00FF00) >> 8);    
290
+    Flash_Save_data[INDEX_PLL_3_5G_HIGH_L] = (39345  & 0x0000FF);    
291
+  }
292
+
293
+
294
+}
295
+void ADF4153_Check(void){
296
+  ADF4153_R_N_Reg_st temp_reg;
297
+  if(HAL_GPIO_ReadPin(PLL_LD_3_5G_H_GPIO_Port, PLL_LD_3_5G_H_Pin) == GPIO_PIN_RESET 
298
+     && HAL_GPIO_ReadPin(PLL_ON_OFF_3_5G_H_GPIO_Port, PLL_ON_OFF_3_5G_H_Pin) == GPIO_PIN_SET){
299
+       temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
300
+       ADF4153_Module_Ctrl(Pll_3_5_H,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
301
+       HAL_Delay(1);
302
+     }
303
+     if(HAL_GPIO_ReadPin(PLL_LD_3_5G_L_GPIO_Port, PLL_LD_3_5G_L_Pin) == GPIO_PIN_RESET
304
+     && HAL_GPIO_ReadPin(PLL_ON_OFF_3_5G_L_GPIO_Port, PLL_ON_OFF_3_5G_L_Pin) == GPIO_PIN_SET){
305
+       temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
306
+       ADF4153_Module_Ctrl(Pll_3_5_L,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
307
+       HAL_Delay(1);
308
+     }
309
+
310
+
311
+}
312
+
313
+void ADF4153_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2,uint32_t R3){
314
+    R3  = R3  & 0x0007FF;
315
+    R2 = R2 & 0x00FFFF;
316
+    R1 = R1 & 0xFFFFFF;
317
+    R0 = R0 & 0xFFFFFF;
318
+//    ADF4153_Freq_Calc(3461500000,40000000,2,5000);
319
+    HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
320
+    HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
321
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
322
+#ifdef DEBUG_PRINT
323
+    printf("YJ :R0: %x  R1:  %x   R2 : %x R3 : %x ",R0,R1,R2,R3);
324
+    printf("\r\n");
325
+#endif /* DEBUG_PRINT */
326
+    /*   R3 Ctrl    */
327
+    for(int i =0; i < 11; i++){
328
+        if(R3 & 0x000400){
329
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_SET);
330
+#ifdef DEBUG_PRINT
331
+            printf("1");
332
+#endif /* DEBUG_PRINT */
333
+        }
334
+        else{
335
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
336
+#ifdef DEBUG_PRINT
337
+            printf("0");
338
+#endif /* DEBUG_PRINT */
339
+        }
340
+        Pol_Delay_us(50);
341
+        HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
342
+        Pol_Delay_us(50);
343
+        HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
344
+        R3 = (R3 << 1);
345
+    }
346
+#ifdef DEBUG_PRINT
347
+    printf("\r\n");
348
+#endif /* DEBUG_PRINT */
349
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
350
+      Pol_Delay_us(50);
351
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
352
+    
353
+    /*   R2 Ctrl    */
354
+     for(int i =0; i < 16; i++){
355
+         if(R2 & 0x008000){
356
+             HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_SET);
357
+#ifdef DEBUG_PRINT
358
+             printf("1");
359
+#endif /* DEBUG_PRINT */
360
+         }
361
+         else{
362
+             HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
363
+#ifdef DEBUG_PRINT
364
+             printf("0");
365
+#endif /* DEBUG_PRINT */
366
+         }
367
+         Pol_Delay_us(50);
368
+         HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
369
+         Pol_Delay_us(50);
370
+         HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
371
+
372
+         R2 = ((R2 << 1) & 0x00FFFF);
373
+     }
374
+#ifdef DEBUG_PRINT
375
+     printf("\r\n");
376
+#endif /* DEBUG_PRINT */
377
+     HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
378
+      Pol_Delay_us(50);
379
+     HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
380
+    
381
+     /*   R1 Ctrl    */
382
+    for(int i =0; i < 24; i++){
383
+        if(R1 & 0x800000){
384
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_SET);
385
+#ifdef DEBUG_PRINT
386
+            printf("1");
387
+#endif /* DEBUG_PRINT */
388
+        }
389
+        else{
390
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
391
+#ifdef DEBUG_PRINT
392
+            printf("0");
393
+#endif /* DEBUG_PRINT */
394
+        }
395
+        Pol_Delay_us(50);
396
+        HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
397
+        Pol_Delay_us(50);
398
+        HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
399
+
400
+        R1 = ((R1 << 1) & 0xFFFFFF);
401
+    }
402
+#ifdef DEBUG_PRINT
403
+    printf("\r\n");
404
+#endif /* DEBUG_PRINT */
405
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
406
+      Pol_Delay_us(50);
407
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
408
+
409
+
410
+        /*   R0 Ctrl    */
411
+   
412
+    for(int i =0; i < 24; i++){
413
+        if(R0 & 0x800000){
414
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_SET);
415
+#ifdef DEBUG_PRINT
416
+            printf("1");
417
+#endif /* DEBUG_PRINT */
418
+        }
419
+        else{
420
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
421
+#ifdef DEBUG_PRINT
422
+            printf("0");
423
+#endif /* DEBUG_PRINT */
424
+        }
425
+        Pol_Delay_us(50);
426
+        HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
427
+        Pol_Delay_us(50);
428
+        HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
429
+
430
+        R0 = ((R0 << 1) & 0xFFFFFF);
431
+    }
432
+#ifdef DEBUG_PRINT
433
+    printf("\r\n");
434
+#endif /* DEBUG_PRINT */
435
+    HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
436
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
437
+    Pol_Delay_us(50);
438
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
439
+
440
+}

+ 758 - 0
insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/zig_operate(3055).c

@@ -0,0 +1,758 @@
1
+/*
2
+ * zig_operate.c
3
+ *
4
+ *  Created on: 2019. 7. 26.
5
+ *      Author: parkyj
6
+ */
7
+#include "zig_operate.h"
8
+#include "main.h"
9
+#include "pll_4113.h"
10
+#include "ADF4153.h"
11
+#include "PE43711.h"
12
+#include "BDA4601.h"
13
+#include "uart.h"
14
+#include "CRC16.h"
15
+extern void AD5318_Ctrl(uint16_t ShiftTarget) ;
16
+extern etError STH30_CheckCrc(uint8_t *data, uint8_t nbrOfBytes, uint8_t checksum);
17
+extern void ADF4153_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2,uint32_t R3);
18
+extern bool Bluecell_Flash_Read(uint8_t* data);
19
+extern void PE43711_ALL_atten_ctrl(ALL_PE43711_st ATT);
20
+extern void Power_ON_OFF_Ctrl(uint8_t type,uint8_t cmd);
21
+extern uint8_t Bluecell_Flash_Write(uint8_t* data);
22
+uint8_t Prev_data[INDEX_BLUE_EOF + 1];
23
+uint8_t Flash_Save_data[INDEX_BLUE_EOF + 1];
24
+
25
+
26
+/* * * * * * * #define Struct* * * * * * * */
27
+PLL_Setting_st Pll_1_8GHz_DL = {
28
+	PLL_CLK_GPIO_Port,
29
+	PLL_CLK_Pin,
30
+	PLL_DATA_GPIO_Port,
31
+	PLL_DATA_Pin,
32
+    PLL_EN_1_8G_DL_GPIO_Port,    
33
+    PLL_EN_1_8G_DL_Pin,
34
+};
35
+PLL_Setting_st Pll_1_8GHz_UL = {
36
+    PLL_CLK_GPIO_Port,
37
+    PLL_CLK_Pin,
38
+    PLL_DATA_GPIO_Port,
39
+    PLL_DATA_Pin,
40
+    PLL_EN_1_8G_UL_GPIO_Port,    
41
+    PLL_EN_1_8G_UL_Pin,
42
+};
43
+PLL_Setting_st Pll_2_1GHz_DL = {
44
+    PLL_CLK_GPIO_Port,
45
+    PLL_CLK_Pin,
46
+    PLL_DATA_GPIO_Port,
47
+    PLL_DATA_Pin,
48
+    PLL_EN_2_1G_DL_GPIO_Port,    
49
+    PLL_EN_2_1G_DL_Pin,
50
+};
51
+PLL_Setting_st Pll_2_1GHz_UL = {
52
+    PLL_CLK_GPIO_Port,
53
+    PLL_CLK_Pin,
54
+    PLL_DATA_GPIO_Port,
55
+    PLL_DATA_Pin,
56
+    PLL_EN_2_1G_UL_GPIO_Port,    
57
+    PLL_EN_2_1G_UL_Pin,
58
+};
59
+/* * * * * * * * NOT YET * * * * * * * */
60
+PLL_Setting_st Pll_3_5GHz_DL = {
61
+    ATT_CLK_3_5G_GPIO_Port,
62
+    ATT_EN_3_5G_Pin,
63
+    PLL_DATA_GPIO_Port,
64
+    PLL_DATA_Pin,
65
+    PLL_EN_2_1G_DL_GPIO_Port,    
66
+    PLL_EN_2_1G_DL_Pin,
67
+};
68
+PLL_Setting_st Pll_3_5GHz_UL = {
69
+    PLL_CLK_GPIO_Port,
70
+    PLL_CLK_Pin,
71
+    PLL_DATA_GPIO_Port,
72
+    PLL_DATA_Pin,
73
+    PLL_EN_2_1G_UL_GPIO_Port,    
74
+    PLL_EN_2_1G_UL_Pin,
75
+};
76
+/* * * * * * * * ATTEN * * * * * * * */    
77
+ATTEN_Setting_st Atten_1_8Ghz_DL1 ={
78
+    ATT_CLK_GPIO_Port,
79
+    ATT_CLK_Pin,
80
+    ATT_DATA_GPIO_Port,
81
+    ATT_DATA_Pin,
82
+    ATT_EN_1_8G_DL1_GPIO_Port,    
83
+    ATT_EN_1_8G_DL1_Pin,
84
+    PATH_EN_1_8G_DL_GPIO_Port,
85
+    PATH_EN_1_8G_DL_Pin,
86
+};
87
+
88
+ATTEN_Setting_st Atten_1_8Ghz_DL2 ={
89
+    ATT_CLK_GPIO_Port,
90
+    ATT_CLK_Pin,
91
+    ATT_DATA_GPIO_Port,
92
+    ATT_DATA_Pin,
93
+    ATT_EN_1_8G_DL2_GPIO_Port,    
94
+    ATT_EN_1_8G_DL2_Pin,
95
+    PATH_EN_1_8G_DL_GPIO_Port,
96
+    PATH_EN_1_8G_DL_Pin,    
97
+};
98
+ATTEN_Setting_st Atten_1_8Ghz_UL1 ={
99
+    ATT_CLK_GPIO_Port,
100
+    ATT_CLK_Pin,
101
+    ATT_DATA_GPIO_Port,
102
+    ATT_DATA_Pin,
103
+    ATT_EN_1_8G_UL1_GPIO_Port,    
104
+    ATT_EN_1_8G_UL1_Pin,
105
+    PATH_EN_1_8G_UL_GPIO_Port,
106
+    PATH_EN_1_8G_UL_Pin,      
107
+};
108
+ATTEN_Setting_st Atten_1_8Ghz_UL2 ={
109
+    ATT_CLK_GPIO_Port,
110
+    ATT_CLK_Pin,
111
+    ATT_DATA_GPIO_Port,
112
+    ATT_DATA_Pin,
113
+    ATT_EN_1_8G_UL2_GPIO_Port,    
114
+    ATT_EN_1_8G_UL2_Pin,
115
+    PATH_EN_1_8G_UL_GPIO_Port,
116
+    PATH_EN_1_8G_UL_Pin,    
117
+};
118
+ATTEN_Setting_st Atten_1_8Ghz_UL3 ={
119
+    ATT_CLK_GPIO_Port,
120
+    ATT_CLK_Pin,
121
+    ATT_DATA_GPIO_Port,
122
+    ATT_DATA_Pin,
123
+    ATT_EN_1_8G_UL3_GPIO_Port,    
124
+    ATT_EN_1_8G_UL3_Pin,
125
+    PATH_EN_1_8G_UL_GPIO_Port,
126
+    PATH_EN_1_8G_UL_Pin,    
127
+};
128
+ATTEN_Setting_st Atten_1_8Ghz_UL4 ={
129
+    ATT_CLK_GPIO_Port,
130
+    ATT_CLK_Pin,
131
+    ATT_DATA_GPIO_Port,
132
+    ATT_DATA_Pin,
133
+    ATT_EN_1_8G_UL4_GPIO_Port,    
134
+    ATT_EN_1_8G_UL4_Pin,
135
+    PATH_EN_1_8G_UL_GPIO_Port,
136
+    PATH_EN_1_8G_UL_Pin,    
137
+};
138
+ATTEN_Setting_st Atten_2_1Ghz_DL1 ={
139
+    ATT_CLK_GPIO_Port,
140
+    ATT_CLK_Pin,
141
+    ATT_DATA_GPIO_Port,
142
+    ATT_DATA_Pin,
143
+    ATT_EN_2_1G_DL1_GPIO_Port,    
144
+    ATT_EN_2_1G_DL1_Pin,
145
+    PATH_EN_2_1G_DL_GPIO_Port,
146
+    PATH_EN_2_1G_DL_Pin,    
147
+};
148
+ATTEN_Setting_st Atten_2_1Ghz_DL2 ={
149
+    ATT_CLK_GPIO_Port,
150
+    ATT_CLK_Pin,
151
+    ATT_DATA_GPIO_Port,
152
+    ATT_DATA_Pin,
153
+    ATT_EN_2_1G_DL2_GPIO_Port,    
154
+    ATT_EN_2_1G_DL2_Pin,
155
+    PATH_EN_2_1G_DL_GPIO_Port,
156
+    PATH_EN_2_1G_DL_Pin,    
157
+};
158
+
159
+ATTEN_Setting_st Atten_2_1Ghz_UL1 ={
160
+    ATT_CLK_GPIO_Port,
161
+    ATT_CLK_Pin,
162
+    ATT_DATA_GPIO_Port,
163
+    ATT_DATA_Pin,
164
+    ATT_EN_2_1G_UL1_GPIO_Port,    
165
+    ATT_EN_2_1G_UL1_Pin,
166
+    PATH_EN_2_1G_UL_GPIO_Port,
167
+    PATH_EN_2_1G_UL_Pin,    
168
+};
169
+ATTEN_Setting_st Atten_2_1Ghz_UL2 ={
170
+    ATT_CLK_GPIO_Port,
171
+    ATT_CLK_Pin,
172
+    ATT_DATA_GPIO_Port,
173
+    ATT_DATA_Pin,
174
+    ATT_EN_2_1G_UL2_GPIO_Port,    
175
+    ATT_EN_2_1G_UL2_Pin,
176
+    PATH_EN_2_1G_UL_GPIO_Port,
177
+    PATH_EN_2_1G_UL_Pin,    
178
+};
179
+ATTEN_Setting_st Atten_2_1Ghz_UL3 ={
180
+    ATT_CLK_GPIO_Port,
181
+    ATT_CLK_Pin,
182
+    ATT_DATA_GPIO_Port,
183
+    ATT_DATA_Pin,
184
+    ATT_EN_2_1G_UL3_GPIO_Port,    
185
+    ATT_EN_2_1G_UL3_Pin,
186
+    PATH_EN_2_1G_UL_GPIO_Port,
187
+    PATH_EN_2_1G_UL_Pin,    
188
+};
189
+ATTEN_Setting_st Atten_2_1Ghz_UL4 ={
190
+    ATT_CLK_GPIO_Port,
191
+    ATT_CLK_Pin,
192
+    ATT_DATA_GPIO_Port,
193
+    ATT_DATA_Pin,
194
+    ATT_EN_2_1G_UL4_GPIO_Port,    
195
+    ATT_EN_2_1G_UL4_Pin,
196
+    PATH_EN_2_1G_UL_GPIO_Port,
197
+    PATH_EN_2_1G_UL_Pin,    
198
+};
199
+
200
+
201
+bool RF_Data_Check(uint8_t* data_buf){
202
+    bool ret = false;
203
+    bool crcret = STH30_CheckCrc(&data_buf[Type], data_buf[Length], data_buf[data_buf[Crcindex]]);
204
+    if(data_buf[Header] == BLUECELL_HEADER){ /*HEADER CHECK*/
205
+        ret= true;
206
+    }
207
+    if(crcret == true){/*CRC CHECK*/
208
+        ret = true;
209
+    }else{
210
+        ret = false;
211
+//        printf("Recv CRC Value : \"%d\"\r\n Create CRC Value : \"%d\"   \r\n",data_buf[data_buf[Crcindex]],STH30_CreateCrc(&data_buf[Type], data_buf[Length]));
212
+    }
213
+//    printf("CRC Result : \"%d\"   \r\n",ret);
214
+    return ret;
215
+
216
+}
217
+
218
+PLL_Setting_st Pll_3_5_H = {
219
+     PLL_CLK_3_5G_GPIO_Port,
220
+     PLL_CLK_3_5G_Pin,
221
+     PLL_DATA_3_5G_GPIO_Port,
222
+     PLL_DATA_3_5G_Pin,
223
+   PLL_EN_3_5G_H_GPIO_Port,    
224
+   PLL_EN_3_5G_H_Pin,
225
+ };
226
+ PLL_Setting_st Pll_3_5_L = {
227
+     PLL_CLK_3_5G_GPIO_Port,
228
+     PLL_CLK_3_5G_Pin,
229
+     PLL_DATA_3_5G_GPIO_Port,
230
+     PLL_DATA_3_5G_Pin,
231
+       PLL_EN_3_5G_L_GPIO_Port,    
232
+       PLL_EN_3_5G_L_Pin,
233
+ };
234
+void RF_Status_Get(void){
235
+//    printf("\r\nYJ2 : Prev_data[INDEX_DET_1_8G_DL_IN_L ] : %x\r\n",Prev_data[INDEX_DET_1_8G_DL_IN_L]);            
236
+    Prev_data[INDEX_BLUE_HEADER]   = BLUECELL_HEADER;
237
+    Prev_data[INDEX_BLUE_TYPE]     = TYPE_BLUECELL_GET;
238
+    Prev_data[INDEX_BLUE_LENGTH]   = INDEX_BLUE_EOF - 2;
239
+    Prev_data[INDEX_BLUE_CRCINDEX] = INDEX_BLUE_CRC;
240
+    Prev_data[INDEX_BLUE_CRC]      = STH30_CreateCrc(&Prev_data[Type], Prev_data[Length]);
241
+    Prev_data[INDEX_BLUE_EOF] = BLUECELL_TAILER;    
242
+    HAL_UART_Transmit_DMA(&huart1,&Prev_data[INDEX_BLUE_HEADER],INDEX_BLUE_EOF + 1); 
243
+//    printf("\r\nYJ : %x",ADCvalue[0]);
244
+//    printf("\r\n");
245
+
246
+}
247
+static uint8_t Ack_Buf[6];
248
+void RF_Status_Ack(void){
249
+//    printf("\r\nYJ2 : Prev_data[INDEX_DET_1_8G_DL_IN_L ] : %x\r\n",Prev_data[INDEX_DET_1_8G_DL_IN_L]);            
250
+    Ack_Buf[INDEX_BLUE_HEADER]       = BLUECELL_HEADER;
251
+    Ack_Buf[INDEX_BLUE_TYPE]         = TYPE_BLUECELL_ACK;
252
+    Ack_Buf[INDEX_BLUE_LENGTH]       = 3;
253
+    Ack_Buf[INDEX_BLUE_CRCINDEX + 0] = INDEX_BLUE_CRCINDEX + 1;
254
+    Ack_Buf[INDEX_BLUE_CRCINDEX + 1] = STH30_CreateCrc(&Ack_Buf[Type], Ack_Buf[Length]);
255
+    Ack_Buf[INDEX_BLUE_CRCINDEX + 2] = BLUECELL_TAILER;
256
+    HAL_UART_Transmit_DMA(&huart1,&Ack_Buf[INDEX_BLUE_HEADER],Ack_Buf[INDEX_BLUE_LENGTH]  + 3); 
257
+//    printf("\r\nYJ : %x",ADCvalue[0]);
258
+//    printf("\r\n");
259
+
260
+}
261
+
262
+void RF_Operate(uint8_t* data_buf){
263
+    uint32_t temp_val = 0;
264
+    uint8_t  ADC_Modify = 0;
265
+    ADF4153_R_N_Reg_st temp_reg;
266
+//    printf("Prev_data[INDEX_ATT_1_8G_DL1]  : %x  data_buf[INDEX_ATT_1_8G_DL1] : %x\r\n",Prev_data[INDEX_ATT_1_8G_DL1],data_buf[INDEX_ATT_1_8G_DL1]);
267
+    if(Prev_data[INDEX_ATT_1_8G_DL1] != data_buf[INDEX_ATT_1_8G_DL1]){
268
+        BDA4601_atten_ctrl(BDA4601_1_8G_DL1,(data_buf[INDEX_ATT_1_8G_DL1]));
269
+        Prev_data[INDEX_ATT_1_8G_DL1] = data_buf[INDEX_ATT_1_8G_DL1];
270
+    }
271
+    if(Prev_data[INDEX_ATT_1_8G_DL2] != data_buf[INDEX_ATT_1_8G_DL2]){
272
+        BDA4601_atten_ctrl(BDA4601_1_8G_DL2,(data_buf[INDEX_ATT_1_8G_DL2]));
273
+        Prev_data[INDEX_ATT_1_8G_DL2] = data_buf[INDEX_ATT_1_8G_DL2];
274
+    }
275
+    if(Prev_data[INDEX_ATT_1_8G_UL1] != data_buf[INDEX_ATT_1_8G_UL1]){
276
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL1,(data_buf[INDEX_ATT_1_8G_UL1]));
277
+        Prev_data[INDEX_ATT_1_8G_UL1] = data_buf[INDEX_ATT_1_8G_UL1];
278
+    }
279
+    if(Prev_data[INDEX_ATT_1_8G_UL2] != data_buf[INDEX_ATT_1_8G_UL2]){
280
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL2,(data_buf[INDEX_ATT_1_8G_UL2]));
281
+        Prev_data[INDEX_ATT_1_8G_UL2] = data_buf[INDEX_ATT_1_8G_UL2];
282
+    }
283
+    if(Prev_data[INDEX_ATT_1_8G_UL3] != data_buf[INDEX_ATT_1_8G_UL3]){
284
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL3,(data_buf[INDEX_ATT_1_8G_UL3]));
285
+        Prev_data[INDEX_ATT_1_8G_UL3] = data_buf[INDEX_ATT_1_8G_UL3];
286
+    }
287
+    if(Prev_data[INDEX_ATT_1_8G_UL4] != data_buf[INDEX_ATT_1_8G_UL4]){
288
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL4,(data_buf[INDEX_ATT_1_8G_UL4]));
289
+        Prev_data[INDEX_ATT_1_8G_UL4] = data_buf[INDEX_ATT_1_8G_UL4];
290
+    }
291
+    if(Prev_data[INDEX_ATT_2_1G_DL1] != data_buf[INDEX_ATT_2_1G_DL1]){
292
+        BDA4601_atten_ctrl(BDA4601_2_1G_DL1,(data_buf[INDEX_ATT_2_1G_DL1]));
293
+        Prev_data[INDEX_ATT_2_1G_DL1] = data_buf[INDEX_ATT_2_1G_DL1];
294
+
295
+    }
296
+    if(Prev_data[INDEX_ATT_2_1G_DL2] != data_buf[INDEX_ATT_2_1G_DL2]){
297
+        BDA4601_atten_ctrl(BDA4601_2_1G_DL2,(data_buf[INDEX_ATT_2_1G_DL2]));
298
+        Prev_data[INDEX_ATT_2_1G_DL2] = data_buf[INDEX_ATT_2_1G_DL2];
299
+
300
+    }
301
+    if(Prev_data[INDEX_ATT_2_1G_UL1] != data_buf[INDEX_ATT_2_1G_UL1]){
302
+        BDA4601_atten_ctrl(BDA4601_2_1G_UL1,(data_buf[INDEX_ATT_2_1G_UL1]));
303
+        Prev_data[INDEX_ATT_2_1G_UL1] = data_buf[INDEX_ATT_2_1G_UL1];
304
+
305
+    }
306
+    if(Prev_data[INDEX_ATT_2_1G_UL2] != data_buf[INDEX_ATT_2_1G_UL2]){
307
+        BDA4601_atten_ctrl(BDA4601_2_1G_UL2,(data_buf[INDEX_ATT_2_1G_UL2]));
308
+        Prev_data[INDEX_ATT_2_1G_UL2] = data_buf[INDEX_ATT_2_1G_UL2];
309
+
310
+    }
311
+    if(Prev_data[INDEX_ATT_2_1G_UL3] != data_buf[INDEX_ATT_2_1G_UL3]){
312
+        BDA4601_atten_ctrl(BDA4601_2_1G_UL3,(data_buf[INDEX_ATT_2_1G_UL3]));
313
+        Prev_data[INDEX_ATT_2_1G_UL3] = data_buf[INDEX_ATT_2_1G_UL3];
314
+    }
315
+    if(Prev_data[INDEX_ATT_2_1G_UL4] != data_buf[INDEX_ATT_2_1G_UL4]){
316
+        BDA4601_atten_ctrl(BDA4601_2_1G_UL4,(data_buf[INDEX_ATT_2_1G_UL4]));
317
+        Prev_data[INDEX_ATT_2_1G_UL4] = data_buf[INDEX_ATT_2_1G_UL4];
318
+    }
319
+    if(   (Prev_data[INDEX_ATT_3_5G_LOW1] != data_buf[INDEX_ATT_3_5G_LOW1])
320
+        ||(Prev_data[INDEX_ATT_3_5G_HIGH1] != data_buf[INDEX_ATT_3_5G_HIGH1])
321
+        ||(Prev_data[INDEX_ATT_3_5G_COM1] != data_buf[INDEX_ATT_3_5G_COM1])
322
+        ||(Prev_data[INDEX_ATT_3_5G_LOW2] != data_buf[INDEX_ATT_3_5G_LOW2])
323
+        ||(Prev_data[INDEX_ATT_3_5G_HIGH2] != data_buf[INDEX_ATT_3_5G_HIGH2])
324
+        ||(Prev_data[INDEX_ATT_3_5G_COM2] != data_buf[INDEX_ATT_3_5G_COM2])
325
+    ){
326
+        ALL_ATT_3_5G.data0 = Prev_data[INDEX_ATT_3_5G_LOW1]  = data_buf[INDEX_ATT_3_5G_LOW1];
327
+        ALL_ATT_3_5G.data1 = Prev_data[INDEX_ATT_3_5G_HIGH1] = data_buf[INDEX_ATT_3_5G_HIGH1];
328
+        ALL_ATT_3_5G.data2 = Prev_data[INDEX_ATT_3_5G_COM1]  = data_buf[INDEX_ATT_3_5G_COM1];
329
+        ALL_ATT_3_5G.data3 = Prev_data[INDEX_ATT_3_5G_LOW2]  = data_buf[INDEX_ATT_3_5G_LOW2];
330
+        ALL_ATT_3_5G.data4 = Prev_data[INDEX_ATT_3_5G_HIGH2] = data_buf[INDEX_ATT_3_5G_HIGH2];
331
+        ALL_ATT_3_5G.data5 = Prev_data[INDEX_ATT_3_5G_COM2]  = data_buf[INDEX_ATT_3_5G_COM2];
332
+        PE43711_ALL_atten_ctrl(ALL_ATT_3_5G);
333
+    }
334
+    if((Prev_data[INDEX_PLL_1_8G_DL_H] != data_buf[INDEX_PLL_1_8G_DL_H])
335
+        || (Prev_data[INDEX_PLL_1_8G_DL_L] != data_buf[INDEX_PLL_1_8G_DL_L])
336
+    ){
337
+        Prev_data[INDEX_PLL_1_8G_DL_H] = data_buf[INDEX_PLL_1_8G_DL_H];
338
+        Prev_data[INDEX_PLL_1_8G_DL_L] = data_buf[INDEX_PLL_1_8G_DL_L];
339
+//        printf("data_buf[INDEX_PLL_1_8G_DL_H] : %x \r\n",data_buf[INDEX_PLL_1_8G_DL_H]);
340
+//        printf("data_buf[INDEX_PLL_1_8G_DL_L] : %x\r\n",data_buf[INDEX_PLL_1_8G_DL_L]);
341
+        temp_val = (data_buf[INDEX_PLL_1_8G_DL_H] << 8) | (data_buf[INDEX_PLL_1_8G_DL_L]);
342
+        ADF4113_Module_Ctrl(ADF4113_1_8G_DL,0x410,halSynSetFreq(temp_val * 100000),0x9F8092);
343
+        HAL_Delay(1);
344
+        BDA4601_atten_ctrl(BDA4601_1_8G_DL1,(data_buf[INDEX_ATT_1_8G_DL1]));
345
+        BDA4601_atten_ctrl(BDA4601_1_8G_DL2,(data_buf[INDEX_ATT_1_8G_DL2]));
346
+    }
347
+    if((Prev_data[INDEX_PLL_1_8G_UL_H] != data_buf[INDEX_PLL_1_8G_UL_H])
348
+        || (Prev_data[INDEX_PLL_1_8G_UL_L] != data_buf[INDEX_PLL_1_8G_UL_L])){
349
+        temp_val = (data_buf[INDEX_PLL_1_8G_UL_H] << 8) | (data_buf[INDEX_PLL_1_8G_UL_L]);
350
+//        printf("data_buf[INDEX_PLL_1_8G_UL_H] : %x \r\n",data_buf[INDEX_PLL_1_8G_UL_H]);
351
+//        printf("data_buf[INDEX_PLL_1_8G_UL_L] : %x\r\n",data_buf[INDEX_PLL_1_8G_UL_L]);
352
+        Prev_data[INDEX_PLL_1_8G_UL_H] = data_buf[INDEX_PLL_1_8G_UL_H];
353
+        Prev_data[INDEX_PLL_1_8G_UL_L] = data_buf[INDEX_PLL_1_8G_UL_L];
354
+//         ADF4113_Module_Ctrl(ADF4113_1_8G_UL,0x000410,0x038D31,0x9f8092);
355
+         ADF4113_Module_Ctrl(ADF4113_1_8G_UL,0x410,halSynSetFreq(temp_val * 100000),0x9F8092);
356
+        HAL_Delay(1);
357
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL1,(data_buf[INDEX_ATT_1_8G_UL1]));
358
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL2,(data_buf[INDEX_ATT_1_8G_UL2]));
359
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL3,(data_buf[INDEX_ATT_1_8G_UL3]));
360
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL4,(data_buf[INDEX_ATT_1_8G_UL4]));
361
+    }
362
+    if((Prev_data[INDEX_PLL_2_1G_DL_H] != data_buf[INDEX_PLL_2_1G_DL_H])
363
+        || (Prev_data[INDEX_PLL_2_1G_DL_L] != data_buf[INDEX_PLL_2_1G_DL_L])){
364
+        temp_val = ((data_buf[INDEX_PLL_2_1G_DL_H] << 8) | (data_buf[INDEX_PLL_2_1G_DL_L]));
365
+//        printf("data_buf[INDEX_PLL_2_1G_DL_H] : %x \r\n",data_buf[INDEX_PLL_2_1G_DL_H]);
366
+//        printf("data_buf[INDEX_PLL_2_1G_DL_L] : %x\r\n",data_buf[INDEX_PLL_2_1G_DL_L]);
367
+        Prev_data[INDEX_PLL_2_1G_DL_H] = data_buf[INDEX_PLL_2_1G_DL_H];
368
+        Prev_data[INDEX_PLL_2_1G_DL_L] = data_buf[INDEX_PLL_2_1G_DL_L];        
369
+//         ADF4113_Module_Ctrl(ADF4113_2_1G_DL,0x410,0x4DE71,0x9F8092);
370
+        ADF4113_Module_Ctrl(ADF4113_2_1G_DL,0x410,halSynSetFreq(temp_val * 100000),0x9F8092);
371
+      HAL_Delay(1);
372
+      BDA4601_atten_ctrl(BDA4601_2_1G_DL1,(data_buf[INDEX_ATT_2_1G_DL1]));
373
+      BDA4601_atten_ctrl(BDA4601_2_1G_DL2,(data_buf[INDEX_ATT_2_1G_DL2]));
374
+    }
375
+    if((Prev_data[INDEX_PLL_2_1G_UL_H] != data_buf[INDEX_PLL_2_1G_UL_H])
376
+        || (Prev_data[INDEX_PLL_2_1G_UL_L] != data_buf[INDEX_PLL_2_1G_UL_L])){
377
+        Prev_data[INDEX_PLL_2_1G_UL_H] = data_buf[INDEX_PLL_2_1G_UL_H];
378
+        Prev_data[INDEX_PLL_2_1G_UL_L] = data_buf[INDEX_PLL_2_1G_UL_L];    
379
+//        printf("data_buf[INDEX_PLL_2_1G_UL_H] : %x \r\n",data_buf[INDEX_PLL_2_1G_UL_H]);
380
+//        printf("data_buf[INDEX_PLL_2_1G_UL_L] : %x\r\n",data_buf[INDEX_PLL_2_1G_UL_L]);
381
+        temp_val = (data_buf[INDEX_PLL_2_1G_UL_H] << 8) | (data_buf[INDEX_PLL_2_1G_UL_L]);
382
+//        ADF4113_Module_Ctrl(ADF4113_2_1G_UL,0x000410,0x59A31,0x9f8092);
383
+        ADF4113_Module_Ctrl(ADF4113_2_1G_UL,0x410,halSynSetFreq(temp_val * 100000),0x9F8092);
384
+      HAL_Delay(1);
385
+      BDA4601_atten_ctrl(BDA4601_2_1G_UL1,(data_buf[INDEX_ATT_2_1G_UL1]));
386
+      BDA4601_atten_ctrl(BDA4601_2_1G_UL2,(data_buf[INDEX_ATT_2_1G_UL2]));
387
+      BDA4601_atten_ctrl(BDA4601_2_1G_UL3,(data_buf[INDEX_ATT_2_1G_UL3]));      
388
+      BDA4601_atten_ctrl(BDA4601_2_1G_UL4,(data_buf[INDEX_ATT_2_1G_UL4]));      
389
+
390
+
391
+    }
392
+    if((Prev_data[INDEX_PLL_3_5G_LOW_H] != data_buf[INDEX_PLL_3_5G_LOW_H])
393
+        ||(Prev_data[INDEX_PLL_3_5G_LOW_M] != data_buf[INDEX_PLL_3_5G_LOW_M])
394
+        || (Prev_data[INDEX_PLL_3_5G_LOW_L] != data_buf[INDEX_PLL_3_5G_LOW_L])){
395
+        Prev_data[INDEX_PLL_3_5G_LOW_H] = data_buf[INDEX_PLL_3_5G_LOW_H];
396
+        Prev_data[INDEX_PLL_3_5G_LOW_M] = data_buf[INDEX_PLL_3_5G_LOW_M];        
397
+        Prev_data[INDEX_PLL_3_5G_LOW_L] = data_buf[INDEX_PLL_3_5G_LOW_L];
398
+        temp_val = (data_buf[INDEX_PLL_3_5G_LOW_H] << 16) | 
399
+                   (data_buf[INDEX_PLL_3_5G_LOW_M] << 8)  | 
400
+                   (data_buf[INDEX_PLL_3_5G_LOW_L]);
401
+#if 1 // PYJ.2019.08.12_BEGIN -- 
402
+        temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
403
+#else
404
+        temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
405
+#endif // PYJ.2019.08.12_END -- 
406
+        ADF4153_Module_Ctrl(Pll_3_5_L,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
407
+    }
408
+    if((Prev_data[INDEX_PLL_3_5G_HIGH_H] != data_buf[INDEX_PLL_3_5G_HIGH_H])
409
+        || (Prev_data[INDEX_PLL_3_5G_HIGH_M] != data_buf[INDEX_PLL_3_5G_HIGH_M])
410
+        || (Prev_data[INDEX_PLL_3_5G_HIGH_L] != data_buf[INDEX_PLL_3_5G_HIGH_L])){
411
+        Prev_data[INDEX_PLL_3_5G_HIGH_H] = data_buf[INDEX_PLL_3_5G_HIGH_H];
412
+        Prev_data[INDEX_PLL_3_5G_HIGH_M] = data_buf[INDEX_PLL_3_5G_HIGH_M];
413
+        Prev_data[INDEX_PLL_3_5G_HIGH_L] = data_buf[INDEX_PLL_3_5G_HIGH_L];
414
+        temp_val = (data_buf[INDEX_PLL_3_5G_HIGH_H] << 16) |
415
+                   (data_buf[INDEX_PLL_3_5G_HIGH_M] << 8)  |
416
+                   (data_buf[INDEX_PLL_3_5G_HIGH_L]);
417
+#if 1 // PYJ.2019.08.12_BEGIN -- 
418
+        temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
419
+#else
420
+        temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
421
+#endif // PYJ.2019.08.12_END -- 
422
+//        ADF4153_Module_Ctrl(Pll_3_5_H,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
423
+
424
+    }
425
+    if(Prev_data[INDEX_PLL_LD_6_BIT] != data_buf[INDEX_PLL_LD_6_BIT]){
426
+
427
+    }
428
+#if 0 // PYJ.2019.07.28_BEGIN -- 
429
+    if(Prev_data[INDEX_DET_1_8G_DL_IN_H] != data_buf[INDEX_DET_1_8G_DL_IN_H]){
430
+
431
+    }
432
+    if(Prev_data[INDEX_DET_1_8G_DL_IN_L] != data_buf[INDEX_DET_1_8G_DL_IN_L]){
433
+
434
+    }
435
+    if(Prev_data[INDEX_DET_1_8G_DL_OUT_H] != data_buf[INDEX_DET_1_8G_DL_OUT_H]){
436
+
437
+    }
438
+    if(Prev_data[INDEX_DET_1_8G_DL_OUT_L] != data_buf[INDEX_DET_1_8G_DL_OUT_L]){
439
+
440
+    }
441
+    if(Prev_data[INDEX_DET_1_8G_UL_IN_H] != data_buf[INDEX_DET_1_8G_UL_IN_H]){
442
+
443
+    }
444
+    if(Prev_data[INDEX_DET_1_8G_UL_IN_L] != data_buf[INDEX_DET_1_8G_UL_IN_L]){
445
+
446
+    }
447
+    if(Prev_data[INDEX_DET_1_8G_UL_OUT_H] != data_buf[INDEX_DET_1_8G_UL_OUT_H]){
448
+
449
+    }
450
+    if(Prev_data[INDEX_DET_1_8G_UL_OUT_L] != data_buf[INDEX_DET_1_8G_UL_OUT_L]){
451
+
452
+    }
453
+    if(Prev_data[INDEX_DET_2_1G_DL_IN_H] != data_buf[INDEX_DET_2_1G_DL_IN_H]){
454
+
455
+    }
456
+    if(Prev_data[INDEX_DET_2_1G_DL_IN_L] != data_buf[INDEX_DET_2_1G_DL_IN_L]){
457
+
458
+    }
459
+    if(Prev_data[INDEX_DET_2_1G_DL_OUT_H] != data_buf[INDEX_DET_2_1G_DL_OUT_H]){
460
+
461
+    }
462
+    if(Prev_data[INDEX_DET_2_1G_DL_OUT_L] != data_buf[INDEX_DET_2_1G_DL_OUT_L]){
463
+
464
+    }
465
+    if(Prev_data[INDEX_DET_2_1G_UL_IN_H] != data_buf[INDEX_DET_2_1G_UL_IN_H]){
466
+
467
+    }
468
+    if(Prev_data[INDEX_DET_2_1G_UL_IN_L] != data_buf[INDEX_DET_2_1G_UL_IN_L]){
469
+
470
+    }
471
+
472
+    if(Prev_data[INDEX_DET_2_1G_UL_OUT_H] != data_buf[INDEX_DET_2_1G_UL_OUT_H]){
473
+
474
+    }
475
+    if(Prev_data[INDEX_DET_2_1G_UL_OUT_L] != data_buf[INDEX_DET_2_1G_UL_OUT_L]){
476
+
477
+    }
478
+    if(Prev_data[INDEX_DET_3_5G_DL_IN_H] != data_buf[INDEX_DET_3_5G_DL_IN_H]){
479
+
480
+    }
481
+    if(Prev_data[INDEX_DET_3_5G_DL_IN_L] != data_buf[INDEX_DET_3_5G_DL_IN_L]){
482
+
483
+    }
484
+    if(Prev_data[INDEX_DET_3_5G_DL_OUT_L] != data_buf[INDEX_DET_3_5G_DL_OUT_L]){
485
+
486
+    }
487
+    if(Prev_data[INDEX_DET_3_5G_DL_OUT_H] != data_buf[INDEX_DET_3_5G_DL_OUT_H]){
488
+
489
+    }
490
+    if(Prev_data[INDEX_DET_3_5G_UL_IN_H] != data_buf[INDEX_DET_3_5G_UL_IN_H]){
491
+
492
+    }
493
+    if(Prev_data[INDEX_DET_3_5G_UL_IN_L] != data_buf[INDEX_DET_3_5G_UL_IN_L]){
494
+
495
+    }
496
+
497
+    if(Prev_data[INDEX_DET_3_5G_UL_OUT_H] != data_buf[INDEX_DET_3_5G_UL_OUT_H]){
498
+
499
+    }
500
+    if(Prev_data[INDEX_DET_3_5G_UL_OUT_L] != data_buf[INDEX_DET_3_5G_UL_OUT_L]){
501
+
502
+    }
503
+    if(Prev_data[INDEX_RFU_TEMP_H] != data_buf[INDEX_RFU_TEMP_H]){
504
+
505
+    }
506
+    if(Prev_data[INDEX_RFU_TEMP_L] != data_buf[INDEX_RFU_TEMP_L]){
507
+
508
+    }
509
+    if(Prev_data[INDEX__28V_DET_H] != data_buf[INDEX__28V_DET_H]){
510
+
511
+    }
512
+    if(Prev_data[INDEX__28V_DET_L] != data_buf[INDEX__28V_DET_L]){
513
+
514
+    }
515
+#endif // PYJ.2019.07.28_END -- 
516
+    if(Prev_data[INDEX_ALARM_AC] != data_buf[INDEX_ALARM_AC]){
517
+
518
+    }
519
+    if(Prev_data[INDEX_ALARM_DC] != data_buf[INDEX_ALARM_DC]){
520
+
521
+    }
522
+    if(Prev_data[INDEX_PATH_EN_1_8G_DL] != data_buf[INDEX_PATH_EN_1_8G_DL]){
523
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_1_8G_DL,data_buf[INDEX_PATH_EN_1_8G_DL]);
524
+        Prev_data[INDEX_PATH_EN_1_8G_DL] = data_buf[INDEX_PATH_EN_1_8G_DL];
525
+    }
526
+    if(Prev_data[INDEX_PATH_EN_1_8G_UL] != data_buf[INDEX_PATH_EN_1_8G_UL]){
527
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_1_8G_UL,data_buf[INDEX_PATH_EN_1_8G_UL]);
528
+        Prev_data[INDEX_PATH_EN_1_8G_UL] = data_buf[INDEX_PATH_EN_1_8G_UL];
529
+
530
+    }
531
+
532
+    if(Prev_data[INDEX_PATH_EN_2_1G_DL] != data_buf[INDEX_PATH_EN_2_1G_DL]){
533
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_2_1G_DL,data_buf[INDEX_PATH_EN_2_1G_DL]);
534
+        Prev_data[INDEX_PATH_EN_2_1G_DL] = data_buf[INDEX_PATH_EN_2_1G_DL];
535
+    }
536
+    if(Prev_data[INDEX_PATH_EN_2_1G_UL] != data_buf[INDEX_PATH_EN_2_1G_UL]){
537
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_2_1G_UL,data_buf[INDEX_PATH_EN_2_1G_UL]);
538
+        Prev_data[INDEX_PATH_EN_2_1G_UL] = data_buf[INDEX_PATH_EN_2_1G_UL];
539
+
540
+    }
541
+    if(Prev_data[INDEX_PATH_EN_3_5G_L] != data_buf[INDEX_PATH_EN_3_5G_L]){
542
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_L,data_buf[INDEX_PATH_EN_3_5G_L]);
543
+        Prev_data[INDEX_PATH_EN_3_5G_L] = data_buf[INDEX_PATH_EN_3_5G_L];
544
+
545
+    }
546
+    if(Prev_data[INDEX_PATH_EN_3_5G_H] != data_buf[INDEX_PATH_EN_3_5G_H]){
547
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_H,data_buf[INDEX_PATH_EN_3_5G_H]);
548
+        Prev_data[INDEX_PATH_EN_3_5G_H] = data_buf[INDEX_PATH_EN_3_5G_H];
549
+    
550
+
551
+    }
552
+    if(Prev_data[INDEX_PATH_EN_3_5G_DL] != data_buf[INDEX_PATH_EN_3_5G_DL]){
553
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_DL,data_buf[INDEX_PATH_EN_3_5G_DL]);
554
+        Prev_data[INDEX_PATH_EN_3_5G_DL] = data_buf[INDEX_PATH_EN_3_5G_DL];
555
+        ADC_Modify = 1;
556
+
557
+    }
558
+    if(Prev_data[INDEX_PATH_EN_3_5G_UL] != data_buf[INDEX_PATH_EN_3_5G_UL]){
559
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_UL,data_buf[INDEX_PATH_EN_3_5G_UL]);
560
+        Prev_data[INDEX_PATH_EN_3_5G_UL] = data_buf[INDEX_PATH_EN_3_5G_UL];
561
+        ADC_Modify = 1;
562
+    }
563
+    if(Prev_data[INDEX_PLL_ON_OFF_3_5G_H] != data_buf[INDEX_PLL_ON_OFF_3_5G_H]){
564
+        Power_ON_OFF_Ctrl(INDEX_PLL_ON_OFF_3_5G_H,data_buf[INDEX_PLL_ON_OFF_3_5G_H]);
565
+        Prev_data[INDEX_PLL_ON_OFF_3_5G_H] = data_buf[INDEX_PLL_ON_OFF_3_5G_H];
566
+        HAL_Delay(1);
567
+//        printf("POWER : %d \r\n",Prev_data[INDEX_PLL_ON_OFF_3_5G_H]);
568
+        if(data_buf[INDEX_PLL_ON_OFF_3_5G_H]){
569
+//            printf("PLL CTRL START !! \r\n");
570
+#if 1 // PYJ.2019.08.12_BEGIN -- 
571
+//            temp_val = (Prev_data[INDEX_PLL_3_5G_LOW_H] << 16) |
572
+//                       (Prev_data[INDEX_PLL_3_5G_LOW_M] << 8) | 
573
+//                       (Prev_data[INDEX_PLL_3_5G_LOW_L]);
574
+            temp_val = (Prev_data[INDEX_PLL_3_5G_HIGH_H] << 16) | 
575
+                       (Prev_data[INDEX_PLL_3_5G_HIGH_M] << 8)  | 
576
+                       (Prev_data[INDEX_PLL_3_5G_HIGH_L]);
577
+
578
+
579
+//            temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
580
+            temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_122_88MHzREFIN,ADF4153_8RCOUNTER,ADF4153_CHANNEL_SPACING);
581
+#else
582
+            temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
583
+#endif // PYJ.2019.08.12_END -- 
584
+//            ADF4153_Module_Ctrl(Pll_3_5_H,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
585
+            ADF4153_Module_Ctrl(Pll_3_5_H,0x4006C0,0x163001,0x1642,3);
586
+
587
+            PE43711_ALL_atten_ctrl(ALL_ATT_3_5G);
588
+        }
589
+    }
590
+    if(Prev_data[INDEX_PLL_ON_OFF_3_5G_L] != data_buf[INDEX_PLL_ON_OFF_3_5G_L]){
591
+        Power_ON_OFF_Ctrl(INDEX_PLL_ON_OFF_3_5G_L,data_buf[INDEX_PLL_ON_OFF_3_5G_L]);
592
+        Prev_data[INDEX_PLL_ON_OFF_3_5G_L] = data_buf[INDEX_PLL_ON_OFF_3_5G_L];
593
+        HAL_Delay(1);
594
+//        printf("POWER : %d \r\n",Prev_data[INDEX_PLL_ON_OFF_3_5G_L]);        
595
+        if(data_buf[INDEX_PLL_ON_OFF_3_5G_L]){
596
+//            printf("PLL CTRL START !! \r\n");
597
+#if 1 // PYJ.2019.08.12_BEGIN -- 
598
+//            temp_val = (Prev_data[INDEX_PLL_3_5G_HIGH_H] << 16) | 
599
+//                       (Prev_data[INDEX_PLL_3_5G_HIGH_M] << 8)  | 
600
+//                       (Prev_data[INDEX_PLL_3_5G_HIGH_L]);
601
+            temp_val = (Prev_data[INDEX_PLL_3_5G_LOW_H] << 16) |
602
+                       (Prev_data[INDEX_PLL_3_5G_LOW_M] << 8) | 
603
+                       (Prev_data[INDEX_PLL_3_5G_LOW_L]);
604
+            temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
605
+//            temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_122_88MHzREFIN,ADF4153_8RCOUNTER,ADF4153_CHANNEL_SPACING);
606
+#else
607
+          temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);            
608
+#endif // PYJ.2019.08.12_END -- 
609
+            ADF4153_Module_Ctrl(Pll_3_5_L,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
610
+            PE43711_ALL_atten_ctrl(ALL_ATT_3_5G);
611
+        }
612
+    }
613
+
614
+    if(Prev_data[INDEX_T_SYNC_DL] != data_buf[INDEX_T_SYNC_DL]){
615
+        Prev_data[INDEX_T_SYNC_DL] = data_buf[INDEX_T_SYNC_DL];
616
+        Power_ON_OFF_Ctrl(INDEX_T_SYNC_DL,data_buf[INDEX_T_SYNC_DL]);
617
+    }
618
+    if(Prev_data[INDEX__T_SYNC_DL] != data_buf[INDEX__T_SYNC_DL]){
619
+        Prev_data[INDEX__T_SYNC_DL] = data_buf[INDEX__T_SYNC_DL];
620
+        Power_ON_OFF_Ctrl(INDEX__T_SYNC_DL,data_buf[INDEX__T_SYNC_DL]);
621
+    }
622
+    if(Prev_data[INDEX_T_SYNC_UL] != data_buf[INDEX_T_SYNC_UL]){
623
+        Prev_data[INDEX_T_SYNC_UL] = data_buf[INDEX_T_SYNC_UL];
624
+        Power_ON_OFF_Ctrl(INDEX_T_SYNC_UL,data_buf[INDEX_T_SYNC_UL]);
625
+    }
626
+    if(Prev_data[INDEX__T_SYNC_UL] != data_buf[INDEX__T_SYNC_UL]){
627
+        Prev_data[INDEX__T_SYNC_UL] = data_buf[INDEX__T_SYNC_UL];
628
+        Power_ON_OFF_Ctrl(INDEX__T_SYNC_UL,data_buf[INDEX__T_SYNC_UL]);
629
+    }
630
+
631
+
632
+    if((Prev_data[INDEX_DAC_VCtrl_A_H] != data_buf[INDEX_DAC_VCtrl_A_H])
633
+        ||(Prev_data[INDEX_DAC_VCtrl_A_L] != data_buf[INDEX_DAC_VCtrl_A_L])){
634
+        ADC_Modify = 1;
635
+        Prev_data[INDEX_DAC_VCtrl_A_H] = data_buf[INDEX_DAC_VCtrl_A_H];
636
+        Prev_data[INDEX_DAC_VCtrl_A_L] = data_buf[INDEX_DAC_VCtrl_A_L];
637
+    }
638
+    if((Prev_data[INDEX_DAC_VCtrl_B_H] != data_buf[INDEX_DAC_VCtrl_B_H])
639
+        ||(Prev_data[INDEX_DAC_VCtrl_B_L] != data_buf[INDEX_DAC_VCtrl_B_L])){
640
+        ADC_Modify = 1;
641
+        
642
+        Prev_data[INDEX_DAC_VCtrl_B_H] = data_buf[INDEX_DAC_VCtrl_B_H];
643
+        Prev_data[INDEX_DAC_VCtrl_B_L] = data_buf[INDEX_DAC_VCtrl_B_L];        
644
+    }    
645
+    if((Prev_data[INDEX_DAC_VCtrl_C_H] != data_buf[INDEX_DAC_VCtrl_C_H])
646
+        ||(Prev_data[INDEX_DAC_VCtrl_C_L] != data_buf[INDEX_DAC_VCtrl_C_L])){
647
+        ADC_Modify = 1;
648
+//        printf("Prev_data[INDEX_DAC_VCtrl_C_H] : %x \r\n",Prev_data[INDEX_DAC_VCtrl_C_H]);
649
+//        printf("Prev_data[INDEX_DAC_VCtrl_C_L] : %x \r\n",Prev_data[INDEX_DAC_VCtrl_C_L]);
650
+
651
+        Prev_data[INDEX_DAC_VCtrl_C_H] = data_buf[INDEX_DAC_VCtrl_C_H];
652
+        Prev_data[INDEX_DAC_VCtrl_C_L] = data_buf[INDEX_DAC_VCtrl_C_L];        
653
+    }
654
+    if((Prev_data[INDEX_DAC_VCtrl_D_H] != data_buf[INDEX_DAC_VCtrl_D_H])
655
+        ||(Prev_data[INDEX_DAC_VCtrl_D_L] != data_buf[INDEX_DAC_VCtrl_D_L])){
656
+        ADC_Modify = 1;
657
+        Prev_data[INDEX_DAC_VCtrl_D_H] = data_buf[INDEX_DAC_VCtrl_D_H];
658
+        Prev_data[INDEX_DAC_VCtrl_D_L] = data_buf[INDEX_DAC_VCtrl_D_L];
659
+    }
660
+    if((Prev_data[INDEX_DAC_VCtrl_E_H] != data_buf[INDEX_DAC_VCtrl_E_H])
661
+        ||(Prev_data[INDEX_DAC_VCtrl_E_L] != data_buf[INDEX_DAC_VCtrl_E_L])){
662
+        ADC_Modify = 1;
663
+
664
+        Prev_data[INDEX_DAC_VCtrl_E_H] = data_buf[INDEX_DAC_VCtrl_E_H];
665
+        Prev_data[INDEX_DAC_VCtrl_E_L] = data_buf[INDEX_DAC_VCtrl_E_L];        
666
+    }
667
+    if((Prev_data[INDEX_DAC_VCtrl_F_H] != data_buf[INDEX_DAC_VCtrl_F_H])
668
+        ||(Prev_data[INDEX_DAC_VCtrl_F_L] != data_buf[INDEX_DAC_VCtrl_F_L])){
669
+        ADC_Modify = 1;
670
+        Prev_data[INDEX_DAC_VCtrl_F_H] = data_buf[INDEX_DAC_VCtrl_F_H];
671
+        Prev_data[INDEX_DAC_VCtrl_F_L] = data_buf[INDEX_DAC_VCtrl_F_L];        
672
+    }
673
+    if((Prev_data[INDEX_DAC_VCtrl_G_H] != data_buf[INDEX_DAC_VCtrl_G_H])
674
+        ||(Prev_data[INDEX_DAC_VCtrl_G_L] != data_buf[INDEX_DAC_VCtrl_G_L])){
675
+        ADC_Modify = 1;
676
+        Prev_data[INDEX_DAC_VCtrl_G_H] = data_buf[INDEX_DAC_VCtrl_G_H];
677
+        Prev_data[INDEX_DAC_VCtrl_G_L] = data_buf[INDEX_DAC_VCtrl_G_L];        
678
+    }    
679
+    if((Prev_data[INDEX_DAC_VCtrl_H_H] != data_buf[INDEX_DAC_VCtrl_H_H])
680
+        ||(Prev_data[INDEX_DAC_VCtrl_H_L] != data_buf[INDEX_DAC_VCtrl_H_L])){
681
+        ADC_Modify = 1;
682
+        Prev_data[INDEX_DAC_VCtrl_H_H] = data_buf[INDEX_DAC_VCtrl_H_H];
683
+        Prev_data[INDEX_DAC_VCtrl_H_L] = data_buf[INDEX_DAC_VCtrl_H_L];        
684
+    }
685
+    if(ADC_Modify){
686
+//        AD5318_Ctrl(0xF000);
687
+//        HAL_Delay(1);
688
+//        AD5318_Ctrl(0x800C);
689
+//        AD5318_Ctrl(0x2FFF );
690
+//        AD5318_Ctrl(0xA000);
691
+//        printf("DAC CTRL START \r\n");
692
+//        AD5318_Ctrl(0x800C);
693
+//        AD5318_Ctrl(0xA000);
694
+//        printf("DAC Change\r\n");
695
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_A_H] << 8 | Prev_data[INDEX_DAC_VCtrl_A_L]));    
696
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_B_H] << 8 | Prev_data[INDEX_DAC_VCtrl_B_L]));    
697
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_C_H] << 8 | Prev_data[INDEX_DAC_VCtrl_C_L]));
698
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_D_H] << 8 | Prev_data[INDEX_DAC_VCtrl_D_L]));
699
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_E_H] << 8 | Prev_data[INDEX_DAC_VCtrl_E_L]));    
700
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_F_H] << 8 | Prev_data[INDEX_DAC_VCtrl_F_L]));
701
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_G_H] << 8 | Prev_data[INDEX_DAC_VCtrl_G_L]));
702
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_H_H] << 8 | Prev_data[INDEX_DAC_VCtrl_H_L]));
703
+    }
704
+    
705
+}
706
+
707
+uint8_t temp_crc = 0;
708
+bool RF_Ctrl_Main(uint8_t* data_buf){
709
+    bool ret = false;
710
+    Bluecell_Prot_t type = data_buf[Type];
711
+    ret = RF_Data_Check(&data_buf[Header]); /* ERROR CHECK */
712
+    if(ret == false){
713
+        HAL_UART_Transmit(&huart1,&data_buf[INDEX_BLUE_HEADER],data_buf[INDEX_BLUE_LENGTH] + 2 + 1,3000); 
714
+        return ret;
715
+    }
716
+    
717
+    switch(type){
718
+    case TYPE_BLUECELL_RESET:
719
+        for(uint8_t i =0 ; i < data_buf[Length] + 6; i++)
720
+            printf("%02x ",data_buf[i]);
721
+        printf("Reset Start \r\n");
722
+        NVIC_SystemReset();
723
+        break;
724
+    case TYPE_BLUECELL_SET:
725
+#if 0 // PYJ.2019.07.31_BEGIN -- 
726
+    printf("TYPE_BLUECELL_SET : ");
727
+    for(uint8_t i =0 ; i < INDEX_BLUE_EOF + 1; i++)
728
+        printf("%02x ",data_buf[i]);
729
+#endif // PYJ.2019.07.31_END -- 
730
+        RF_Operate(&data_buf[Header]);
731
+        RF_Status_Ack();
732
+
733
+//        ADF4153_Freq_Calc(3465500000,40000000,2,5000);
734
+//        ADF4153_Freq_Calc(3993450000,40000000,2,5000);
735
+//        halSynSetFreq(1995000000);
736
+//        halSynSetFreq(1600000000);
737
+//        halSynSetFreq(1455000000);        
738
+        break;
739
+    case TYPE_BLUECELL_GET:
740
+#if 0 // PYJ.2019.08.01_BEGIN -- 
741
+        printf("\r\nTYPE_BLUECELL_GET : \r\n");
742
+#endif // PYJ.2019.08.01_END -- 
743
+        RF_Status_Get();
744
+        break;
745
+    case TYPE_BLUECELL_SAVE:
746
+//        printf("\r\nFLASH Write\r\n");
747
+        Bluecell_Flash_Write(&Prev_data[INDEX_BLUE_HEADER]);
748
+        RF_Status_Ack();
749
+
750
+        break;
751
+        default:
752
+#ifdef DEBUG_PRINT // PYJ.2019.07.27_BEGIN --         
753
+            printf("Function : %s   LINE : %d    type : %d \r\n",__func__,__LINE__,type);
754
+#endif
755
+            break;
756
+    }
757
+    return ret;
758
+}

+ 758 - 0
insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/zig_operate(4870).c

@@ -0,0 +1,758 @@
1
+/*
2
+ * zig_operate.c
3
+ *
4
+ *  Created on: 2019. 7. 26.
5
+ *      Author: parkyj
6
+ */
7
+#include "zig_operate.h"
8
+#include "main.h"
9
+#include "pll_4113.h"
10
+#include "ADF4153.h"
11
+#include "PE43711.h"
12
+#include "BDA4601.h"
13
+#include "uart.h"
14
+#include "CRC16.h"
15
+extern void AD5318_Ctrl(uint16_t ShiftTarget) ;
16
+extern etError STH30_CheckCrc(uint8_t *data, uint8_t nbrOfBytes, uint8_t checksum);
17
+extern void ADF4153_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2,uint32_t R3);
18
+extern bool Bluecell_Flash_Read(uint8_t* data);
19
+extern void PE43711_ALL_atten_ctrl(ALL_PE43711_st ATT);
20
+extern void Power_ON_OFF_Ctrl(uint8_t type,uint8_t cmd);
21
+extern uint8_t Bluecell_Flash_Write(uint8_t* data);
22
+uint8_t Prev_data[INDEX_BLUE_EOF + 1];
23
+uint8_t Flash_Save_data[INDEX_BLUE_EOF + 1];
24
+
25
+
26
+/* * * * * * * #define Struct* * * * * * * */
27
+PLL_Setting_st Pll_1_8GHz_DL = {
28
+  PLL_CLK_GPIO_Port,
29
+  PLL_CLK_Pin,
30
+  PLL_DATA_GPIO_Port,
31
+  PLL_DATA_Pin,
32
+  PLL_EN_1_8G_DL_GPIO_Port,    
33
+  PLL_EN_1_8G_DL_Pin,
34
+};
35
+PLL_Setting_st Pll_1_8GHz_UL = {
36
+    PLL_CLK_GPIO_Port,
37
+    PLL_CLK_Pin,
38
+    PLL_DATA_GPIO_Port,
39
+    PLL_DATA_Pin,
40
+    PLL_EN_1_8G_UL_GPIO_Port,    
41
+    PLL_EN_1_8G_UL_Pin,
42
+};
43
+PLL_Setting_st Pll_2_1GHz_DL = {
44
+    PLL_CLK_GPIO_Port,
45
+    PLL_CLK_Pin,
46
+    PLL_DATA_GPIO_Port,
47
+    PLL_DATA_Pin,
48
+    PLL_EN_2_1G_DL_GPIO_Port,    
49
+    PLL_EN_2_1G_DL_Pin,
50
+};
51
+PLL_Setting_st Pll_2_1GHz_UL = {
52
+    PLL_CLK_GPIO_Port,
53
+    PLL_CLK_Pin,
54
+    PLL_DATA_GPIO_Port,
55
+    PLL_DATA_Pin,
56
+    PLL_EN_2_1G_UL_GPIO_Port,    
57
+    PLL_EN_2_1G_UL_Pin,
58
+};
59
+/* * * * * * * * NOT YET * * * * * * * */
60
+PLL_Setting_st Pll_3_5GHz_DL = {
61
+    ATT_CLK_3_5G_GPIO_Port,
62
+    ATT_EN_3_5G_Pin,
63
+    PLL_DATA_GPIO_Port,
64
+    PLL_DATA_Pin,
65
+    PLL_EN_2_1G_DL_GPIO_Port,    
66
+    PLL_EN_2_1G_DL_Pin,
67
+};
68
+PLL_Setting_st Pll_3_5GHz_UL = {
69
+    PLL_CLK_GPIO_Port,
70
+    PLL_CLK_Pin,
71
+    PLL_DATA_GPIO_Port,
72
+    PLL_DATA_Pin,
73
+    PLL_EN_2_1G_UL_GPIO_Port,    
74
+    PLL_EN_2_1G_UL_Pin,
75
+};
76
+/* * * * * * * * ATTEN * * * * * * * */    
77
+ATTEN_Setting_st Atten_1_8Ghz_DL1 ={
78
+    ATT_CLK_GPIO_Port,
79
+    ATT_CLK_Pin,
80
+    ATT_DATA_GPIO_Port,
81
+    ATT_DATA_Pin,
82
+    ATT_EN_1_8G_DL1_GPIO_Port,    
83
+    ATT_EN_1_8G_DL1_Pin,
84
+    PATH_EN_1_8G_DL_GPIO_Port,
85
+    PATH_EN_1_8G_DL_Pin,
86
+};
87
+
88
+ATTEN_Setting_st Atten_1_8Ghz_DL2 ={
89
+    ATT_CLK_GPIO_Port,
90
+    ATT_CLK_Pin,
91
+    ATT_DATA_GPIO_Port,
92
+    ATT_DATA_Pin,
93
+    ATT_EN_1_8G_DL2_GPIO_Port,    
94
+    ATT_EN_1_8G_DL2_Pin,
95
+    PATH_EN_1_8G_DL_GPIO_Port,
96
+    PATH_EN_1_8G_DL_Pin,    
97
+};
98
+ATTEN_Setting_st Atten_1_8Ghz_UL1 ={
99
+    ATT_CLK_GPIO_Port,
100
+    ATT_CLK_Pin,
101
+    ATT_DATA_GPIO_Port,
102
+    ATT_DATA_Pin,
103
+    ATT_EN_1_8G_UL1_GPIO_Port,    
104
+    ATT_EN_1_8G_UL1_Pin,
105
+    PATH_EN_1_8G_UL_GPIO_Port,
106
+    PATH_EN_1_8G_UL_Pin,      
107
+};
108
+ATTEN_Setting_st Atten_1_8Ghz_UL2 ={
109
+    ATT_CLK_GPIO_Port,
110
+    ATT_CLK_Pin,
111
+    ATT_DATA_GPIO_Port,
112
+    ATT_DATA_Pin,
113
+    ATT_EN_1_8G_UL2_GPIO_Port,    
114
+    ATT_EN_1_8G_UL2_Pin,
115
+    PATH_EN_1_8G_UL_GPIO_Port,
116
+    PATH_EN_1_8G_UL_Pin,    
117
+};
118
+ATTEN_Setting_st Atten_1_8Ghz_UL3 ={
119
+    ATT_CLK_GPIO_Port,
120
+    ATT_CLK_Pin,
121
+    ATT_DATA_GPIO_Port,
122
+    ATT_DATA_Pin,
123
+    ATT_EN_1_8G_UL3_GPIO_Port,    
124
+    ATT_EN_1_8G_UL3_Pin,
125
+    PATH_EN_1_8G_UL_GPIO_Port,
126
+    PATH_EN_1_8G_UL_Pin,    
127
+};
128
+ATTEN_Setting_st Atten_1_8Ghz_UL4 ={
129
+    ATT_CLK_GPIO_Port,
130
+    ATT_CLK_Pin,
131
+    ATT_DATA_GPIO_Port,
132
+    ATT_DATA_Pin,
133
+    ATT_EN_1_8G_UL4_GPIO_Port,    
134
+    ATT_EN_1_8G_UL4_Pin,
135
+    PATH_EN_1_8G_UL_GPIO_Port,
136
+    PATH_EN_1_8G_UL_Pin,    
137
+};
138
+ATTEN_Setting_st Atten_2_1Ghz_DL1 ={
139
+    ATT_CLK_GPIO_Port,
140
+    ATT_CLK_Pin,
141
+    ATT_DATA_GPIO_Port,
142
+    ATT_DATA_Pin,
143
+    ATT_EN_2_1G_DL1_GPIO_Port,    
144
+    ATT_EN_2_1G_DL1_Pin,
145
+    PATH_EN_2_1G_DL_GPIO_Port,
146
+    PATH_EN_2_1G_DL_Pin,    
147
+};
148
+ATTEN_Setting_st Atten_2_1Ghz_DL2 ={
149
+    ATT_CLK_GPIO_Port,
150
+    ATT_CLK_Pin,
151
+    ATT_DATA_GPIO_Port,
152
+    ATT_DATA_Pin,
153
+    ATT_EN_2_1G_DL2_GPIO_Port,    
154
+    ATT_EN_2_1G_DL2_Pin,
155
+    PATH_EN_2_1G_DL_GPIO_Port,
156
+    PATH_EN_2_1G_DL_Pin,    
157
+};
158
+
159
+ATTEN_Setting_st Atten_2_1Ghz_UL1 ={
160
+    ATT_CLK_GPIO_Port,
161
+    ATT_CLK_Pin,
162
+    ATT_DATA_GPIO_Port,
163
+    ATT_DATA_Pin,
164
+    ATT_EN_2_1G_UL1_GPIO_Port,    
165
+    ATT_EN_2_1G_UL1_Pin,
166
+    PATH_EN_2_1G_UL_GPIO_Port,
167
+    PATH_EN_2_1G_UL_Pin,    
168
+};
169
+ATTEN_Setting_st Atten_2_1Ghz_UL2 ={
170
+    ATT_CLK_GPIO_Port,
171
+    ATT_CLK_Pin,
172
+    ATT_DATA_GPIO_Port,
173
+    ATT_DATA_Pin,
174
+    ATT_EN_2_1G_UL2_GPIO_Port,    
175
+    ATT_EN_2_1G_UL2_Pin,
176
+    PATH_EN_2_1G_UL_GPIO_Port,
177
+    PATH_EN_2_1G_UL_Pin,    
178
+};
179
+ATTEN_Setting_st Atten_2_1Ghz_UL3 ={
180
+    ATT_CLK_GPIO_Port,
181
+    ATT_CLK_Pin,
182
+    ATT_DATA_GPIO_Port,
183
+    ATT_DATA_Pin,
184
+    ATT_EN_2_1G_UL3_GPIO_Port,    
185
+    ATT_EN_2_1G_UL3_Pin,
186
+    PATH_EN_2_1G_UL_GPIO_Port,
187
+    PATH_EN_2_1G_UL_Pin,    
188
+};
189
+ATTEN_Setting_st Atten_2_1Ghz_UL4 ={
190
+    ATT_CLK_GPIO_Port,
191
+    ATT_CLK_Pin,
192
+    ATT_DATA_GPIO_Port,
193
+    ATT_DATA_Pin,
194
+    ATT_EN_2_1G_UL4_GPIO_Port,    
195
+    ATT_EN_2_1G_UL4_Pin,
196
+    PATH_EN_2_1G_UL_GPIO_Port,
197
+    PATH_EN_2_1G_UL_Pin,    
198
+};
199
+
200
+
201
+bool RF_Data_Check(uint8_t* data_buf){
202
+    bool ret = false;
203
+    bool crcret = STH30_CheckCrc(&data_buf[Type], data_buf[Length], data_buf[data_buf[Crcindex]]);
204
+    if(data_buf[Header] == BLUECELL_HEADER){ /*HEADER CHECK*/
205
+        ret= true;
206
+    }
207
+    if(crcret == true){/*CRC CHECK*/
208
+        ret = true;
209
+    }else{
210
+        ret = false;
211
+//        printf("Recv CRC Value : \"%d\"\r\n Create CRC Value : \"%d\"   \r\n",data_buf[data_buf[Crcindex]],STH30_CreateCrc(&data_buf[Type], data_buf[Length]));
212
+    }
213
+//    printf("CRC Result : \"%d\"   \r\n",ret);
214
+    return ret;
215
+
216
+}
217
+
218
+PLL_Setting_st Pll_3_5_H = {
219
+     PLL_CLK_3_5G_GPIO_Port,
220
+     PLL_CLK_3_5G_Pin,
221
+     PLL_DATA_3_5G_GPIO_Port,
222
+     PLL_DATA_3_5G_Pin,
223
+   PLL_EN_3_5G_H_GPIO_Port,    
224
+   PLL_EN_3_5G_H_Pin,
225
+ };
226
+ PLL_Setting_st Pll_3_5_L = {
227
+     PLL_CLK_3_5G_GPIO_Port,
228
+     PLL_CLK_3_5G_Pin,
229
+     PLL_DATA_3_5G_GPIO_Port,
230
+     PLL_DATA_3_5G_Pin,
231
+       PLL_EN_3_5G_L_GPIO_Port,    
232
+       PLL_EN_3_5G_L_Pin,
233
+ };
234
+void RF_Status_Get(void){
235
+//    printf("\r\nYJ2 : Prev_data[INDEX_DET_1_8G_DL_IN_L ] : %x\r\n",Prev_data[INDEX_DET_1_8G_DL_IN_L]);            
236
+    Prev_data[INDEX_BLUE_HEADER]   = BLUECELL_HEADER;
237
+    Prev_data[INDEX_BLUE_TYPE]     = TYPE_BLUECELL_GET;
238
+    Prev_data[INDEX_BLUE_LENGTH]   = INDEX_BLUE_EOF - 2;
239
+    Prev_data[INDEX_BLUE_CRCINDEX] = INDEX_BLUE_CRC;
240
+    Prev_data[INDEX_BLUE_CRC]      = STH30_CreateCrc(&Prev_data[Type], Prev_data[Length]);
241
+    Prev_data[INDEX_BLUE_EOF] = BLUECELL_TAILER;    
242
+    HAL_UART_Transmit_DMA(&huart1,&Prev_data[INDEX_BLUE_HEADER],INDEX_BLUE_EOF + 1); 
243
+//    printf("\r\nYJ : %x",ADCvalue[0]);
244
+//    printf("\r\n");
245
+
246
+}
247
+static uint8_t Ack_Buf[6];
248
+void RF_Status_Ack(void){
249
+//    printf("\r\nYJ2 : Prev_data[INDEX_DET_1_8G_DL_IN_L ] : %x\r\n",Prev_data[INDEX_DET_1_8G_DL_IN_L]);            
250
+    Ack_Buf[INDEX_BLUE_HEADER]       = BLUECELL_HEADER;
251
+    Ack_Buf[INDEX_BLUE_TYPE]         = TYPE_BLUECELL_ACK;
252
+    Ack_Buf[INDEX_BLUE_LENGTH]       = 3;
253
+    Ack_Buf[INDEX_BLUE_CRCINDEX + 0] = INDEX_BLUE_CRCINDEX + 1;
254
+    Ack_Buf[INDEX_BLUE_CRCINDEX + 1] = STH30_CreateCrc(&Ack_Buf[Type], Ack_Buf[Length]);
255
+    Ack_Buf[INDEX_BLUE_CRCINDEX + 2] = BLUECELL_TAILER;
256
+    HAL_UART_Transmit_DMA(&huart1,&Ack_Buf[INDEX_BLUE_HEADER],Ack_Buf[INDEX_BLUE_LENGTH]  + 3); 
257
+//    printf("\r\nYJ : %x",ADCvalue[0]);
258
+//    printf("\r\n");
259
+
260
+}
261
+
262
+void RF_Operate(uint8_t* data_buf){
263
+    uint32_t temp_val = 0;
264
+    uint8_t  ADC_Modify = 0;
265
+    ADF4153_R_N_Reg_st temp_reg;
266
+//    printf("Prev_data[INDEX_ATT_1_8G_DL1]  : %x  data_buf[INDEX_ATT_1_8G_DL1] : %x\r\n",Prev_data[INDEX_ATT_1_8G_DL1],data_buf[INDEX_ATT_1_8G_DL1]);
267
+    if(Prev_data[INDEX_ATT_1_8G_DL1] != data_buf[INDEX_ATT_1_8G_DL1]){
268
+        BDA4601_atten_ctrl(BDA4601_1_8G_DL1,(data_buf[INDEX_ATT_1_8G_DL1]));
269
+        Prev_data[INDEX_ATT_1_8G_DL1] = data_buf[INDEX_ATT_1_8G_DL1];
270
+    }
271
+    if(Prev_data[INDEX_ATT_1_8G_DL2] != data_buf[INDEX_ATT_1_8G_DL2]){
272
+        BDA4601_atten_ctrl(BDA4601_1_8G_DL2,(data_buf[INDEX_ATT_1_8G_DL2]));
273
+        Prev_data[INDEX_ATT_1_8G_DL2] = data_buf[INDEX_ATT_1_8G_DL2];
274
+    }
275
+    if(Prev_data[INDEX_ATT_1_8G_UL1] != data_buf[INDEX_ATT_1_8G_UL1]){
276
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL1,(data_buf[INDEX_ATT_1_8G_UL1]));
277
+        Prev_data[INDEX_ATT_1_8G_UL1] = data_buf[INDEX_ATT_1_8G_UL1];
278
+    }
279
+    if(Prev_data[INDEX_ATT_1_8G_UL2] != data_buf[INDEX_ATT_1_8G_UL2]){
280
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL2,(data_buf[INDEX_ATT_1_8G_UL2]));
281
+        Prev_data[INDEX_ATT_1_8G_UL2] = data_buf[INDEX_ATT_1_8G_UL2];
282
+    }
283
+    if(Prev_data[INDEX_ATT_1_8G_UL3] != data_buf[INDEX_ATT_1_8G_UL3]){
284
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL3,(data_buf[INDEX_ATT_1_8G_UL3]));
285
+        Prev_data[INDEX_ATT_1_8G_UL3] = data_buf[INDEX_ATT_1_8G_UL3];
286
+    }
287
+    if(Prev_data[INDEX_ATT_1_8G_UL4] != data_buf[INDEX_ATT_1_8G_UL4]){
288
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL4,(data_buf[INDEX_ATT_1_8G_UL4]));
289
+        Prev_data[INDEX_ATT_1_8G_UL4] = data_buf[INDEX_ATT_1_8G_UL4];
290
+    }
291
+    if(Prev_data[INDEX_ATT_2_1G_DL1] != data_buf[INDEX_ATT_2_1G_DL1]){
292
+        BDA4601_atten_ctrl(BDA4601_2_1G_DL1,(data_buf[INDEX_ATT_2_1G_DL1]));
293
+        Prev_data[INDEX_ATT_2_1G_DL1] = data_buf[INDEX_ATT_2_1G_DL1];
294
+
295
+    }
296
+    if(Prev_data[INDEX_ATT_2_1G_DL2] != data_buf[INDEX_ATT_2_1G_DL2]){
297
+        BDA4601_atten_ctrl(BDA4601_2_1G_DL2,(data_buf[INDEX_ATT_2_1G_DL2]));
298
+        Prev_data[INDEX_ATT_2_1G_DL2] = data_buf[INDEX_ATT_2_1G_DL2];
299
+
300
+    }
301
+    if(Prev_data[INDEX_ATT_2_1G_UL1] != data_buf[INDEX_ATT_2_1G_UL1]){
302
+        BDA4601_atten_ctrl(BDA4601_2_1G_UL1,(data_buf[INDEX_ATT_2_1G_UL1]));
303
+        Prev_data[INDEX_ATT_2_1G_UL1] = data_buf[INDEX_ATT_2_1G_UL1];
304
+
305
+    }
306
+    if(Prev_data[INDEX_ATT_2_1G_UL2] != data_buf[INDEX_ATT_2_1G_UL2]){
307
+        BDA4601_atten_ctrl(BDA4601_2_1G_UL2,(data_buf[INDEX_ATT_2_1G_UL2]));
308
+        Prev_data[INDEX_ATT_2_1G_UL2] = data_buf[INDEX_ATT_2_1G_UL2];
309
+
310
+    }
311
+    if(Prev_data[INDEX_ATT_2_1G_UL3] != data_buf[INDEX_ATT_2_1G_UL3]){
312
+        BDA4601_atten_ctrl(BDA4601_2_1G_UL3,(data_buf[INDEX_ATT_2_1G_UL3]));
313
+        Prev_data[INDEX_ATT_2_1G_UL3] = data_buf[INDEX_ATT_2_1G_UL3];
314
+    }
315
+    if(Prev_data[INDEX_ATT_2_1G_UL4] != data_buf[INDEX_ATT_2_1G_UL4]){
316
+        BDA4601_atten_ctrl(BDA4601_2_1G_UL4,(data_buf[INDEX_ATT_2_1G_UL4]));
317
+        Prev_data[INDEX_ATT_2_1G_UL4] = data_buf[INDEX_ATT_2_1G_UL4];
318
+    }
319
+    if(   (Prev_data[INDEX_ATT_3_5G_LOW1] != data_buf[INDEX_ATT_3_5G_LOW1])
320
+        ||(Prev_data[INDEX_ATT_3_5G_HIGH1] != data_buf[INDEX_ATT_3_5G_HIGH1])
321
+        ||(Prev_data[INDEX_ATT_3_5G_COM1] != data_buf[INDEX_ATT_3_5G_COM1])
322
+        ||(Prev_data[INDEX_ATT_3_5G_LOW2] != data_buf[INDEX_ATT_3_5G_LOW2])
323
+        ||(Prev_data[INDEX_ATT_3_5G_HIGH2] != data_buf[INDEX_ATT_3_5G_HIGH2])
324
+        ||(Prev_data[INDEX_ATT_3_5G_COM2] != data_buf[INDEX_ATT_3_5G_COM2])
325
+    ){
326
+        ALL_ATT_3_5G.data0 = Prev_data[INDEX_ATT_3_5G_LOW1]  = data_buf[INDEX_ATT_3_5G_LOW1];
327
+        ALL_ATT_3_5G.data1 = Prev_data[INDEX_ATT_3_5G_HIGH1] = data_buf[INDEX_ATT_3_5G_HIGH1];
328
+        ALL_ATT_3_5G.data2 = Prev_data[INDEX_ATT_3_5G_COM1]  = data_buf[INDEX_ATT_3_5G_COM1];
329
+        ALL_ATT_3_5G.data3 = Prev_data[INDEX_ATT_3_5G_LOW2]  = data_buf[INDEX_ATT_3_5G_LOW2];
330
+        ALL_ATT_3_5G.data4 = Prev_data[INDEX_ATT_3_5G_HIGH2] = data_buf[INDEX_ATT_3_5G_HIGH2];
331
+        ALL_ATT_3_5G.data5 = Prev_data[INDEX_ATT_3_5G_COM2]  = data_buf[INDEX_ATT_3_5G_COM2];
332
+        PE43711_ALL_atten_ctrl(ALL_ATT_3_5G);
333
+    }
334
+    if((Prev_data[INDEX_PLL_1_8G_DL_H] != data_buf[INDEX_PLL_1_8G_DL_H])
335
+        || (Prev_data[INDEX_PLL_1_8G_DL_L] != data_buf[INDEX_PLL_1_8G_DL_L])
336
+    ){
337
+        Prev_data[INDEX_PLL_1_8G_DL_H] = data_buf[INDEX_PLL_1_8G_DL_H];
338
+        Prev_data[INDEX_PLL_1_8G_DL_L] = data_buf[INDEX_PLL_1_8G_DL_L];
339
+//        printf("data_buf[INDEX_PLL_1_8G_DL_H] : %x \r\n",data_buf[INDEX_PLL_1_8G_DL_H]);
340
+//        printf("data_buf[INDEX_PLL_1_8G_DL_L] : %x\r\n",data_buf[INDEX_PLL_1_8G_DL_L]);
341
+        temp_val = (data_buf[INDEX_PLL_1_8G_DL_H] << 8) | (data_buf[INDEX_PLL_1_8G_DL_L]);
342
+        ADF4113_Module_Ctrl(ADF4113_1_8G_DL,0x410,halSynSetFreq(temp_val * 100000),0x9F8092);
343
+        HAL_Delay(1);
344
+        BDA4601_atten_ctrl(BDA4601_1_8G_DL1,(data_buf[INDEX_ATT_1_8G_DL1]));
345
+        BDA4601_atten_ctrl(BDA4601_1_8G_DL2,(data_buf[INDEX_ATT_1_8G_DL2]));
346
+    }
347
+    if((Prev_data[INDEX_PLL_1_8G_UL_H] != data_buf[INDEX_PLL_1_8G_UL_H])
348
+        || (Prev_data[INDEX_PLL_1_8G_UL_L] != data_buf[INDEX_PLL_1_8G_UL_L])){
349
+        temp_val = (data_buf[INDEX_PLL_1_8G_UL_H] << 8) | (data_buf[INDEX_PLL_1_8G_UL_L]);
350
+//        printf("data_buf[INDEX_PLL_1_8G_UL_H] : %x \r\n",data_buf[INDEX_PLL_1_8G_UL_H]);
351
+//        printf("data_buf[INDEX_PLL_1_8G_UL_L] : %x\r\n",data_buf[INDEX_PLL_1_8G_UL_L]);
352
+        Prev_data[INDEX_PLL_1_8G_UL_H] = data_buf[INDEX_PLL_1_8G_UL_H];
353
+        Prev_data[INDEX_PLL_1_8G_UL_L] = data_buf[INDEX_PLL_1_8G_UL_L];
354
+//         ADF4113_Module_Ctrl(ADF4113_1_8G_UL,0x000410,0x038D31,0x9f8092);
355
+         ADF4113_Module_Ctrl(ADF4113_1_8G_UL,0x410,halSynSetFreq(temp_val * 100000),0x9F8092);
356
+        HAL_Delay(1);
357
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL1,(data_buf[INDEX_ATT_1_8G_UL1]));
358
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL2,(data_buf[INDEX_ATT_1_8G_UL2]));
359
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL3,(data_buf[INDEX_ATT_1_8G_UL3]));
360
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL4,(data_buf[INDEX_ATT_1_8G_UL4]));
361
+    }
362
+    if((Prev_data[INDEX_PLL_2_1G_DL_H] != data_buf[INDEX_PLL_2_1G_DL_H])
363
+        || (Prev_data[INDEX_PLL_2_1G_DL_L] != data_buf[INDEX_PLL_2_1G_DL_L])){
364
+        temp_val = ((data_buf[INDEX_PLL_2_1G_DL_H] << 8) | (data_buf[INDEX_PLL_2_1G_DL_L]));
365
+//        printf("data_buf[INDEX_PLL_2_1G_DL_H] : %x \r\n",data_buf[INDEX_PLL_2_1G_DL_H]);
366
+//        printf("data_buf[INDEX_PLL_2_1G_DL_L] : %x\r\n",data_buf[INDEX_PLL_2_1G_DL_L]);
367
+        Prev_data[INDEX_PLL_2_1G_DL_H] = data_buf[INDEX_PLL_2_1G_DL_H];
368
+        Prev_data[INDEX_PLL_2_1G_DL_L] = data_buf[INDEX_PLL_2_1G_DL_L];        
369
+//         ADF4113_Module_Ctrl(ADF4113_2_1G_DL,0x410,0x4DE71,0x9F8092);
370
+        ADF4113_Module_Ctrl(ADF4113_2_1G_DL,0x410,halSynSetFreq(temp_val * 100000),0x9F8092);
371
+      HAL_Delay(1);
372
+      BDA4601_atten_ctrl(BDA4601_2_1G_DL1,(data_buf[INDEX_ATT_2_1G_DL1]));
373
+      BDA4601_atten_ctrl(BDA4601_2_1G_DL2,(data_buf[INDEX_ATT_2_1G_DL2]));
374
+    }
375
+    if((Prev_data[INDEX_PLL_2_1G_UL_H] != data_buf[INDEX_PLL_2_1G_UL_H])
376
+        || (Prev_data[INDEX_PLL_2_1G_UL_L] != data_buf[INDEX_PLL_2_1G_UL_L])){
377
+        Prev_data[INDEX_PLL_2_1G_UL_H] = data_buf[INDEX_PLL_2_1G_UL_H];
378
+        Prev_data[INDEX_PLL_2_1G_UL_L] = data_buf[INDEX_PLL_2_1G_UL_L];    
379
+//        printf("data_buf[INDEX_PLL_2_1G_UL_H] : %x \r\n",data_buf[INDEX_PLL_2_1G_UL_H]);
380
+//        printf("data_buf[INDEX_PLL_2_1G_UL_L] : %x\r\n",data_buf[INDEX_PLL_2_1G_UL_L]);
381
+        temp_val = (data_buf[INDEX_PLL_2_1G_UL_H] << 8) | (data_buf[INDEX_PLL_2_1G_UL_L]);
382
+//        ADF4113_Module_Ctrl(ADF4113_2_1G_UL,0x000410,0x59A31,0x9f8092);
383
+        ADF4113_Module_Ctrl(ADF4113_2_1G_UL,0x410,halSynSetFreq(temp_val * 100000),0x9F8092);
384
+      HAL_Delay(1);
385
+      BDA4601_atten_ctrl(BDA4601_2_1G_UL1,(data_buf[INDEX_ATT_2_1G_UL1]));
386
+      BDA4601_atten_ctrl(BDA4601_2_1G_UL2,(data_buf[INDEX_ATT_2_1G_UL2]));
387
+      BDA4601_atten_ctrl(BDA4601_2_1G_UL3,(data_buf[INDEX_ATT_2_1G_UL3]));      
388
+      BDA4601_atten_ctrl(BDA4601_2_1G_UL4,(data_buf[INDEX_ATT_2_1G_UL4]));      
389
+
390
+
391
+    }
392
+    if((Prev_data[INDEX_PLL_3_5G_LOW_H] != data_buf[INDEX_PLL_3_5G_LOW_H])
393
+        ||(Prev_data[INDEX_PLL_3_5G_LOW_M] != data_buf[INDEX_PLL_3_5G_LOW_M])
394
+        || (Prev_data[INDEX_PLL_3_5G_LOW_L] != data_buf[INDEX_PLL_3_5G_LOW_L])){
395
+        Prev_data[INDEX_PLL_3_5G_LOW_H] = data_buf[INDEX_PLL_3_5G_LOW_H];
396
+        Prev_data[INDEX_PLL_3_5G_LOW_M] = data_buf[INDEX_PLL_3_5G_LOW_M];        
397
+        Prev_data[INDEX_PLL_3_5G_LOW_L] = data_buf[INDEX_PLL_3_5G_LOW_L];
398
+        temp_val = (data_buf[INDEX_PLL_3_5G_LOW_H] << 16) | 
399
+                   (data_buf[INDEX_PLL_3_5G_LOW_M] << 8)  | 
400
+                   (data_buf[INDEX_PLL_3_5G_LOW_L]);
401
+#if 1 // PYJ.2019.08.12_BEGIN -- 
402
+        temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
403
+#else
404
+        temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
405
+#endif // PYJ.2019.08.12_END -- 
406
+        ADF4153_Module_Ctrl(Pll_3_5_L,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
407
+    }
408
+    if((Prev_data[INDEX_PLL_3_5G_HIGH_H] != data_buf[INDEX_PLL_3_5G_HIGH_H])
409
+        || (Prev_data[INDEX_PLL_3_5G_HIGH_M] != data_buf[INDEX_PLL_3_5G_HIGH_M])
410
+        || (Prev_data[INDEX_PLL_3_5G_HIGH_L] != data_buf[INDEX_PLL_3_5G_HIGH_L])){
411
+        Prev_data[INDEX_PLL_3_5G_HIGH_H] = data_buf[INDEX_PLL_3_5G_HIGH_H];
412
+        Prev_data[INDEX_PLL_3_5G_HIGH_M] = data_buf[INDEX_PLL_3_5G_HIGH_M];
413
+        Prev_data[INDEX_PLL_3_5G_HIGH_L] = data_buf[INDEX_PLL_3_5G_HIGH_L];
414
+        temp_val = (data_buf[INDEX_PLL_3_5G_HIGH_H] << 16) |
415
+                   (data_buf[INDEX_PLL_3_5G_HIGH_M] << 8)  |
416
+                   (data_buf[INDEX_PLL_3_5G_HIGH_L]);
417
+#if 1 // PYJ.2019.08.12_BEGIN -- 
418
+        temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
419
+#else
420
+        temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
421
+#endif // PYJ.2019.08.12_END -- 
422
+//        ADF4153_Module_Ctrl(Pll_3_5_H,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
423
+
424
+    }
425
+    if(Prev_data[INDEX_PLL_LD_6_BIT] != data_buf[INDEX_PLL_LD_6_BIT]){
426
+
427
+    }
428
+#if 0 // PYJ.2019.07.28_BEGIN -- 
429
+    if(Prev_data[INDEX_DET_1_8G_DL_IN_H] != data_buf[INDEX_DET_1_8G_DL_IN_H]){
430
+
431
+    }
432
+    if(Prev_data[INDEX_DET_1_8G_DL_IN_L] != data_buf[INDEX_DET_1_8G_DL_IN_L]){
433
+
434
+    }
435
+    if(Prev_data[INDEX_DET_1_8G_DL_OUT_H] != data_buf[INDEX_DET_1_8G_DL_OUT_H]){
436
+
437
+    }
438
+    if(Prev_data[INDEX_DET_1_8G_DL_OUT_L] != data_buf[INDEX_DET_1_8G_DL_OUT_L]){
439
+
440
+    }
441
+    if(Prev_data[INDEX_DET_1_8G_UL_IN_H] != data_buf[INDEX_DET_1_8G_UL_IN_H]){
442
+
443
+    }
444
+    if(Prev_data[INDEX_DET_1_8G_UL_IN_L] != data_buf[INDEX_DET_1_8G_UL_IN_L]){
445
+
446
+    }
447
+    if(Prev_data[INDEX_DET_1_8G_UL_OUT_H] != data_buf[INDEX_DET_1_8G_UL_OUT_H]){
448
+
449
+    }
450
+    if(Prev_data[INDEX_DET_1_8G_UL_OUT_L] != data_buf[INDEX_DET_1_8G_UL_OUT_L]){
451
+
452
+    }
453
+    if(Prev_data[INDEX_DET_2_1G_DL_IN_H] != data_buf[INDEX_DET_2_1G_DL_IN_H]){
454
+
455
+    }
456
+    if(Prev_data[INDEX_DET_2_1G_DL_IN_L] != data_buf[INDEX_DET_2_1G_DL_IN_L]){
457
+
458
+    }
459
+    if(Prev_data[INDEX_DET_2_1G_DL_OUT_H] != data_buf[INDEX_DET_2_1G_DL_OUT_H]){
460
+
461
+    }
462
+    if(Prev_data[INDEX_DET_2_1G_DL_OUT_L] != data_buf[INDEX_DET_2_1G_DL_OUT_L]){
463
+
464
+    }
465
+    if(Prev_data[INDEX_DET_2_1G_UL_IN_H] != data_buf[INDEX_DET_2_1G_UL_IN_H]){
466
+
467
+    }
468
+    if(Prev_data[INDEX_DET_2_1G_UL_IN_L] != data_buf[INDEX_DET_2_1G_UL_IN_L]){
469
+
470
+    }
471
+
472
+    if(Prev_data[INDEX_DET_2_1G_UL_OUT_H] != data_buf[INDEX_DET_2_1G_UL_OUT_H]){
473
+
474
+    }
475
+    if(Prev_data[INDEX_DET_2_1G_UL_OUT_L] != data_buf[INDEX_DET_2_1G_UL_OUT_L]){
476
+
477
+    }
478
+    if(Prev_data[INDEX_DET_3_5G_DL_IN_H] != data_buf[INDEX_DET_3_5G_DL_IN_H]){
479
+
480
+    }
481
+    if(Prev_data[INDEX_DET_3_5G_DL_IN_L] != data_buf[INDEX_DET_3_5G_DL_IN_L]){
482
+
483
+    }
484
+    if(Prev_data[INDEX_DET_3_5G_DL_OUT_L] != data_buf[INDEX_DET_3_5G_DL_OUT_L]){
485
+
486
+    }
487
+    if(Prev_data[INDEX_DET_3_5G_DL_OUT_H] != data_buf[INDEX_DET_3_5G_DL_OUT_H]){
488
+
489
+    }
490
+    if(Prev_data[INDEX_DET_3_5G_UL_IN_H] != data_buf[INDEX_DET_3_5G_UL_IN_H]){
491
+
492
+    }
493
+    if(Prev_data[INDEX_DET_3_5G_UL_IN_L] != data_buf[INDEX_DET_3_5G_UL_IN_L]){
494
+
495
+    }
496
+
497
+    if(Prev_data[INDEX_DET_3_5G_UL_OUT_H] != data_buf[INDEX_DET_3_5G_UL_OUT_H]){
498
+
499
+    }
500
+    if(Prev_data[INDEX_DET_3_5G_UL_OUT_L] != data_buf[INDEX_DET_3_5G_UL_OUT_L]){
501
+
502
+    }
503
+    if(Prev_data[INDEX_RFU_TEMP_H] != data_buf[INDEX_RFU_TEMP_H]){
504
+
505
+    }
506
+    if(Prev_data[INDEX_RFU_TEMP_L] != data_buf[INDEX_RFU_TEMP_L]){
507
+
508
+    }
509
+    if(Prev_data[INDEX__28V_DET_H] != data_buf[INDEX__28V_DET_H]){
510
+
511
+    }
512
+    if(Prev_data[INDEX__28V_DET_L] != data_buf[INDEX__28V_DET_L]){
513
+
514
+    }
515
+#endif // PYJ.2019.07.28_END -- 
516
+    if(Prev_data[INDEX_ALARM_AC] != data_buf[INDEX_ALARM_AC]){
517
+
518
+    }
519
+    if(Prev_data[INDEX_ALARM_DC] != data_buf[INDEX_ALARM_DC]){
520
+
521
+    }
522
+    if(Prev_data[INDEX_PATH_EN_1_8G_DL] != data_buf[INDEX_PATH_EN_1_8G_DL]){
523
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_1_8G_DL,data_buf[INDEX_PATH_EN_1_8G_DL]);
524
+        Prev_data[INDEX_PATH_EN_1_8G_DL] = data_buf[INDEX_PATH_EN_1_8G_DL];
525
+    }
526
+    if(Prev_data[INDEX_PATH_EN_1_8G_UL] != data_buf[INDEX_PATH_EN_1_8G_UL]){
527
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_1_8G_UL,data_buf[INDEX_PATH_EN_1_8G_UL]);
528
+        Prev_data[INDEX_PATH_EN_1_8G_UL] = data_buf[INDEX_PATH_EN_1_8G_UL];
529
+
530
+    }
531
+
532
+    if(Prev_data[INDEX_PATH_EN_2_1G_DL] != data_buf[INDEX_PATH_EN_2_1G_DL]){
533
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_2_1G_DL,data_buf[INDEX_PATH_EN_2_1G_DL]);
534
+        Prev_data[INDEX_PATH_EN_2_1G_DL] = data_buf[INDEX_PATH_EN_2_1G_DL];
535
+    }
536
+    if(Prev_data[INDEX_PATH_EN_2_1G_UL] != data_buf[INDEX_PATH_EN_2_1G_UL]){
537
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_2_1G_UL,data_buf[INDEX_PATH_EN_2_1G_UL]);
538
+        Prev_data[INDEX_PATH_EN_2_1G_UL] = data_buf[INDEX_PATH_EN_2_1G_UL];
539
+
540
+    }
541
+    if(Prev_data[INDEX_PATH_EN_3_5G_L] != data_buf[INDEX_PATH_EN_3_5G_L]){
542
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_L,data_buf[INDEX_PATH_EN_3_5G_L]);
543
+        Prev_data[INDEX_PATH_EN_3_5G_L] = data_buf[INDEX_PATH_EN_3_5G_L];
544
+
545
+    }
546
+    if(Prev_data[INDEX_PATH_EN_3_5G_H] != data_buf[INDEX_PATH_EN_3_5G_H]){
547
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_H,data_buf[INDEX_PATH_EN_3_5G_H]);
548
+        Prev_data[INDEX_PATH_EN_3_5G_H] = data_buf[INDEX_PATH_EN_3_5G_H];
549
+    
550
+
551
+    }
552
+    if(Prev_data[INDEX_PATH_EN_3_5G_DL] != data_buf[INDEX_PATH_EN_3_5G_DL]){
553
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_DL,data_buf[INDEX_PATH_EN_3_5G_DL]);
554
+        Prev_data[INDEX_PATH_EN_3_5G_DL] = data_buf[INDEX_PATH_EN_3_5G_DL];
555
+        ADC_Modify = 1;
556
+
557
+    }
558
+    if(Prev_data[INDEX_PATH_EN_3_5G_UL] != data_buf[INDEX_PATH_EN_3_5G_UL]){
559
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_UL,data_buf[INDEX_PATH_EN_3_5G_UL]);
560
+        Prev_data[INDEX_PATH_EN_3_5G_UL] = data_buf[INDEX_PATH_EN_3_5G_UL];
561
+        ADC_Modify = 1;
562
+    }
563
+    if(Prev_data[INDEX_PLL_ON_OFF_3_5G_H] != data_buf[INDEX_PLL_ON_OFF_3_5G_H]){
564
+        Power_ON_OFF_Ctrl(INDEX_PLL_ON_OFF_3_5G_H,data_buf[INDEX_PLL_ON_OFF_3_5G_H]);
565
+        Prev_data[INDEX_PLL_ON_OFF_3_5G_H] = data_buf[INDEX_PLL_ON_OFF_3_5G_H];
566
+        HAL_Delay(1);
567
+//        printf("POWER : %d \r\n",Prev_data[INDEX_PLL_ON_OFF_3_5G_H]);
568
+        if(data_buf[INDEX_PLL_ON_OFF_3_5G_H]){
569
+//            printf("PLL CTRL START !! \r\n");
570
+#if 1 // PYJ.2019.08.12_BEGIN -- 
571
+//            temp_val = (Prev_data[INDEX_PLL_3_5G_LOW_H] << 16) |
572
+//                       (Prev_data[INDEX_PLL_3_5G_LOW_M] << 8) | 
573
+//                       (Prev_data[INDEX_PLL_3_5G_LOW_L]);
574
+            temp_val = (Prev_data[INDEX_PLL_3_5G_HIGH_H] << 16) | 
575
+                       (Prev_data[INDEX_PLL_3_5G_HIGH_M] << 8)  | 
576
+                       (Prev_data[INDEX_PLL_3_5G_HIGH_L]);
577
+
578
+
579
+//            temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
580
+            temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_122_88MHzREFIN,ADF4153_8RCOUNTER,ADF4153_CHANNEL_SPACING);
581
+#else
582
+            temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
583
+#endif // PYJ.2019.08.12_END -- 
584
+//            ADF4153_Module_Ctrl(Pll_3_5_H,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
585
+            ADF4153_Module_Ctrl(Pll_3_5_H,0x4006C0,0x163001,0x1642,3);
586
+
587
+            PE43711_ALL_atten_ctrl(ALL_ATT_3_5G);
588
+        }
589
+    }
590
+    if(Prev_data[INDEX_PLL_ON_OFF_3_5G_L] != data_buf[INDEX_PLL_ON_OFF_3_5G_L]){
591
+        Power_ON_OFF_Ctrl(INDEX_PLL_ON_OFF_3_5G_L,data_buf[INDEX_PLL_ON_OFF_3_5G_L]);
592
+        Prev_data[INDEX_PLL_ON_OFF_3_5G_L] = data_buf[INDEX_PLL_ON_OFF_3_5G_L];
593
+        HAL_Delay(1);
594
+//        printf("POWER : %d \r\n",Prev_data[INDEX_PLL_ON_OFF_3_5G_L]);        
595
+        if(data_buf[INDEX_PLL_ON_OFF_3_5G_L]){
596
+//            printf("PLL CTRL START !! \r\n");
597
+#if 1 // PYJ.2019.08.12_BEGIN -- 
598
+//            temp_val = (Prev_data[INDEX_PLL_3_5G_HIGH_H] << 16) | 
599
+//                       (Prev_data[INDEX_PLL_3_5G_HIGH_M] << 8)  | 
600
+//                       (Prev_data[INDEX_PLL_3_5G_HIGH_L]);
601
+            temp_val = (Prev_data[INDEX_PLL_3_5G_LOW_H] << 16) |
602
+                       (Prev_data[INDEX_PLL_3_5G_LOW_M] << 8) | 
603
+                       (Prev_data[INDEX_PLL_3_5G_LOW_L]);
604
+            temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
605
+//            temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_122_88MHzREFIN,ADF4153_8RCOUNTER,ADF4153_CHANNEL_SPACING);
606
+#else
607
+          temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);            
608
+#endif // PYJ.2019.08.12_END -- 
609
+            ADF4153_Module_Ctrl(Pll_3_5_L,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
610
+            PE43711_ALL_atten_ctrl(ALL_ATT_3_5G);
611
+        }
612
+    }
613
+
614
+    if(Prev_data[INDEX_T_SYNC_DL] != data_buf[INDEX_T_SYNC_DL]){
615
+        Prev_data[INDEX_T_SYNC_DL] = data_buf[INDEX_T_SYNC_DL];
616
+        Power_ON_OFF_Ctrl(INDEX_T_SYNC_DL,data_buf[INDEX_T_SYNC_DL]);
617
+    }
618
+    if(Prev_data[INDEX__T_SYNC_DL] != data_buf[INDEX__T_SYNC_DL]){
619
+        Prev_data[INDEX__T_SYNC_DL] = data_buf[INDEX__T_SYNC_DL];
620
+        Power_ON_OFF_Ctrl(INDEX__T_SYNC_DL,data_buf[INDEX__T_SYNC_DL]);
621
+    }
622
+    if(Prev_data[INDEX_T_SYNC_UL] != data_buf[INDEX_T_SYNC_UL]){
623
+        Prev_data[INDEX_T_SYNC_UL] = data_buf[INDEX_T_SYNC_UL];
624
+        Power_ON_OFF_Ctrl(INDEX_T_SYNC_UL,data_buf[INDEX_T_SYNC_UL]);
625
+    }
626
+    if(Prev_data[INDEX__T_SYNC_UL] != data_buf[INDEX__T_SYNC_UL]){
627
+        Prev_data[INDEX__T_SYNC_UL] = data_buf[INDEX__T_SYNC_UL];
628
+        Power_ON_OFF_Ctrl(INDEX__T_SYNC_UL,data_buf[INDEX__T_SYNC_UL]);
629
+    }
630
+
631
+
632
+    if((Prev_data[INDEX_DAC_VCtrl_A_H] != data_buf[INDEX_DAC_VCtrl_A_H])
633
+        ||(Prev_data[INDEX_DAC_VCtrl_A_L] != data_buf[INDEX_DAC_VCtrl_A_L])){
634
+        ADC_Modify = 1;
635
+        Prev_data[INDEX_DAC_VCtrl_A_H] = data_buf[INDEX_DAC_VCtrl_A_H];
636
+        Prev_data[INDEX_DAC_VCtrl_A_L] = data_buf[INDEX_DAC_VCtrl_A_L];
637
+    }
638
+    if((Prev_data[INDEX_DAC_VCtrl_B_H] != data_buf[INDEX_DAC_VCtrl_B_H])
639
+        ||(Prev_data[INDEX_DAC_VCtrl_B_L] != data_buf[INDEX_DAC_VCtrl_B_L])){
640
+        ADC_Modify = 1;
641
+        
642
+        Prev_data[INDEX_DAC_VCtrl_B_H] = data_buf[INDEX_DAC_VCtrl_B_H];
643
+        Prev_data[INDEX_DAC_VCtrl_B_L] = data_buf[INDEX_DAC_VCtrl_B_L];        
644
+    }    
645
+    if((Prev_data[INDEX_DAC_VCtrl_C_H] != data_buf[INDEX_DAC_VCtrl_C_H])
646
+        ||(Prev_data[INDEX_DAC_VCtrl_C_L] != data_buf[INDEX_DAC_VCtrl_C_L])){
647
+        ADC_Modify = 1;
648
+//        printf("Prev_data[INDEX_DAC_VCtrl_C_H] : %x \r\n",Prev_data[INDEX_DAC_VCtrl_C_H]);
649
+//        printf("Prev_data[INDEX_DAC_VCtrl_C_L] : %x \r\n",Prev_data[INDEX_DAC_VCtrl_C_L]);
650
+
651
+        Prev_data[INDEX_DAC_VCtrl_C_H] = data_buf[INDEX_DAC_VCtrl_C_H];
652
+        Prev_data[INDEX_DAC_VCtrl_C_L] = data_buf[INDEX_DAC_VCtrl_C_L];        
653
+    }
654
+    if((Prev_data[INDEX_DAC_VCtrl_D_H] != data_buf[INDEX_DAC_VCtrl_D_H])
655
+        ||(Prev_data[INDEX_DAC_VCtrl_D_L] != data_buf[INDEX_DAC_VCtrl_D_L])){
656
+        ADC_Modify = 1;
657
+        Prev_data[INDEX_DAC_VCtrl_D_H] = data_buf[INDEX_DAC_VCtrl_D_H];
658
+        Prev_data[INDEX_DAC_VCtrl_D_L] = data_buf[INDEX_DAC_VCtrl_D_L];
659
+    }
660
+    if((Prev_data[INDEX_DAC_VCtrl_E_H] != data_buf[INDEX_DAC_VCtrl_E_H])
661
+        ||(Prev_data[INDEX_DAC_VCtrl_E_L] != data_buf[INDEX_DAC_VCtrl_E_L])){
662
+        ADC_Modify = 1;
663
+
664
+        Prev_data[INDEX_DAC_VCtrl_E_H] = data_buf[INDEX_DAC_VCtrl_E_H];
665
+        Prev_data[INDEX_DAC_VCtrl_E_L] = data_buf[INDEX_DAC_VCtrl_E_L];        
666
+    }
667
+    if((Prev_data[INDEX_DAC_VCtrl_F_H] != data_buf[INDEX_DAC_VCtrl_F_H])
668
+        ||(Prev_data[INDEX_DAC_VCtrl_F_L] != data_buf[INDEX_DAC_VCtrl_F_L])){
669
+        ADC_Modify = 1;
670
+        Prev_data[INDEX_DAC_VCtrl_F_H] = data_buf[INDEX_DAC_VCtrl_F_H];
671
+        Prev_data[INDEX_DAC_VCtrl_F_L] = data_buf[INDEX_DAC_VCtrl_F_L];        
672
+    }
673
+    if((Prev_data[INDEX_DAC_VCtrl_G_H] != data_buf[INDEX_DAC_VCtrl_G_H])
674
+        ||(Prev_data[INDEX_DAC_VCtrl_G_L] != data_buf[INDEX_DAC_VCtrl_G_L])){
675
+        ADC_Modify = 1;
676
+        Prev_data[INDEX_DAC_VCtrl_G_H] = data_buf[INDEX_DAC_VCtrl_G_H];
677
+        Prev_data[INDEX_DAC_VCtrl_G_L] = data_buf[INDEX_DAC_VCtrl_G_L];        
678
+    }    
679
+    if((Prev_data[INDEX_DAC_VCtrl_H_H] != data_buf[INDEX_DAC_VCtrl_H_H])
680
+        ||(Prev_data[INDEX_DAC_VCtrl_H_L] != data_buf[INDEX_DAC_VCtrl_H_L])){
681
+        ADC_Modify = 1;
682
+        Prev_data[INDEX_DAC_VCtrl_H_H] = data_buf[INDEX_DAC_VCtrl_H_H];
683
+        Prev_data[INDEX_DAC_VCtrl_H_L] = data_buf[INDEX_DAC_VCtrl_H_L];        
684
+    }
685
+    if(ADC_Modify){
686
+//        AD5318_Ctrl(0xF000);
687
+//        HAL_Delay(1);
688
+//        AD5318_Ctrl(0x800C);
689
+//        AD5318_Ctrl(0x2FFF );
690
+//        AD5318_Ctrl(0xA000);
691
+//        printf("DAC CTRL START \r\n");
692
+//        AD5318_Ctrl(0x800C);
693
+//        AD5318_Ctrl(0xA000);
694
+//        printf("DAC Change\r\n");
695
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_A_H] << 8 | Prev_data[INDEX_DAC_VCtrl_A_L]));    
696
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_B_H] << 8 | Prev_data[INDEX_DAC_VCtrl_B_L]));    
697
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_C_H] << 8 | Prev_data[INDEX_DAC_VCtrl_C_L]));
698
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_D_H] << 8 | Prev_data[INDEX_DAC_VCtrl_D_L]));
699
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_E_H] << 8 | Prev_data[INDEX_DAC_VCtrl_E_L]));    
700
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_F_H] << 8 | Prev_data[INDEX_DAC_VCtrl_F_L]));
701
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_G_H] << 8 | Prev_data[INDEX_DAC_VCtrl_G_L]));
702
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_H_H] << 8 | Prev_data[INDEX_DAC_VCtrl_H_L]));
703
+    }
704
+    
705
+}
706
+
707
+uint8_t temp_crc = 0;
708
+bool RF_Ctrl_Main(uint8_t* data_buf){
709
+    bool ret = false;
710
+    Bluecell_Prot_t type = data_buf[Type];
711
+    ret = RF_Data_Check(&data_buf[Header]); /* ERROR CHECK */
712
+    if(ret == false){
713
+        HAL_UART_Transmit(&huart1,&data_buf[INDEX_BLUE_HEADER],data_buf[INDEX_BLUE_LENGTH] + 2 + 1,3000); 
714
+        return ret;
715
+    }
716
+    
717
+    switch(type){
718
+    case TYPE_BLUECELL_RESET:
719
+        for(uint8_t i =0 ; i < data_buf[Length] + 6; i++)
720
+            printf("%02x ",data_buf[i]);
721
+        printf("Reset Start \r\n");
722
+        NVIC_SystemReset();
723
+        break;
724
+    case TYPE_BLUECELL_SET:
725
+#if 0 // PYJ.2019.07.31_BEGIN -- 
726
+    printf("TYPE_BLUECELL_SET : ");
727
+    for(uint8_t i =0 ; i < INDEX_BLUE_EOF + 1; i++)
728
+        printf("%02x ",data_buf[i]);
729
+#endif // PYJ.2019.07.31_END -- 
730
+        RF_Operate(&data_buf[Header]);
731
+        RF_Status_Ack();
732
+
733
+//        ADF4153_Freq_Calc(3465500000,40000000,2,5000);
734
+//        ADF4153_Freq_Calc(3993450000,40000000,2,5000);
735
+//        halSynSetFreq(1995000000);
736
+//        halSynSetFreq(1600000000);
737
+//        halSynSetFreq(1455000000);        
738
+        break;
739
+    case TYPE_BLUECELL_GET:
740
+#if 0 // PYJ.2019.08.01_BEGIN -- 
741
+        printf("\r\nTYPE_BLUECELL_GET : \r\n");
742
+#endif // PYJ.2019.08.01_END -- 
743
+        RF_Status_Get();
744
+        break;
745
+    case TYPE_BLUECELL_SAVE:
746
+//        printf("\r\nFLASH Write\r\n");
747
+        Bluecell_Flash_Write(&Prev_data[INDEX_BLUE_HEADER]);
748
+        RF_Status_Ack();
749
+
750
+        break;
751
+        default:
752
+#ifdef DEBUG_PRINT // PYJ.2019.07.27_BEGIN --         
753
+            printf("Function : %s   LINE : %d    type : %d \r\n",__func__,__LINE__,type);
754
+#endif
755
+            break;
756
+    }
757
+    return ret;
758
+}

+ 758 - 0
insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/zig_operate(6204).c

@@ -0,0 +1,758 @@
1
+/*
2
+ * zig_operate.c
3
+ *
4
+ *  Created on: 2019. 7. 26.
5
+ *      Author: parkyj
6
+ */
7
+#include "zig_operate.h"
8
+#include "main.h"
9
+#include "pll_4113.h"
10
+#include "ADF4153.h"
11
+#include "PE43711.h"
12
+#include "BDA4601.h"
13
+#include "uart.h"
14
+#include "CRC16.h"
15
+extern void AD5318_Ctrl(uint16_t ShiftTarget) ;
16
+extern etError STH30_CheckCrc(uint8_t *data, uint8_t nbrOfBytes, uint8_t checksum);
17
+extern void ADF4153_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2,uint32_t R3);
18
+extern bool Bluecell_Flash_Read(uint8_t* data);
19
+extern void PE43711_ALL_atten_ctrl(ALL_PE43711_st ATT);
20
+extern void Power_ON_OFF_Ctrl(uint8_t type,uint8_t cmd);
21
+extern uint8_t Bluecell_Flash_Write(uint8_t* data);
22
+uint8_t Prev_data[INDEX_BLUE_EOF + 1];
23
+uint8_t Flash_Save_data[INDEX_BLUE_EOF + 1];
24
+
25
+
26
+/* * * * * * * #define Struct* * * * * * * */
27
+PLL_Setting_st Pll_1_8GHz_DL = {
28
+  PLL_CLK_GPIO_Port,
29
+  PLL_CLK_Pin,
30
+  PLL_DATA_GPIO_Port,
31
+  PLL_DATA_Pin,
32
+  PLL_EN_1_8G_DL_GPIO_Port,    
33
+  PLL_EN_1_8G_DL_Pin,
34
+};
35
+PLL_Setting_st Pll_1_8GHz_UL = {
36
+    PLL_CLK_GPIO_Port,
37
+    PLL_CLK_Pin,
38
+    PLL_DATA_GPIO_Port,
39
+    PLL_DATA_Pin,
40
+    PLL_EN_1_8G_UL_GPIO_Port,    
41
+    PLL_EN_1_8G_UL_Pin,
42
+};
43
+PLL_Setting_st Pll_2_1GHz_DL = {
44
+    PLL_CLK_GPIO_Port,
45
+    PLL_CLK_Pin,
46
+    PLL_DATA_GPIO_Port,
47
+    PLL_DATA_Pin,
48
+    PLL_EN_2_1G_DL_GPIO_Port,    
49
+    PLL_EN_2_1G_DL_Pin,
50
+};
51
+PLL_Setting_st Pll_2_1GHz_UL = {
52
+    PLL_CLK_GPIO_Port,
53
+    PLL_CLK_Pin,
54
+    PLL_DATA_GPIO_Port,
55
+    PLL_DATA_Pin,
56
+    PLL_EN_2_1G_UL_GPIO_Port,    
57
+    PLL_EN_2_1G_UL_Pin,
58
+};
59
+/* * * * * * * * NOT YET * * * * * * * */
60
+PLL_Setting_st Pll_3_5GHz_DL = {
61
+    ATT_CLK_3_5G_GPIO_Port,
62
+    ATT_EN_3_5G_Pin,
63
+    PLL_DATA_GPIO_Port,
64
+    PLL_DATA_Pin,
65
+    PLL_EN_2_1G_DL_GPIO_Port,    
66
+    PLL_EN_2_1G_DL_Pin,
67
+};
68
+PLL_Setting_st Pll_3_5GHz_UL = {
69
+    PLL_CLK_GPIO_Port,
70
+    PLL_CLK_Pin,
71
+    PLL_DATA_GPIO_Port,
72
+    PLL_DATA_Pin,
73
+    PLL_EN_2_1G_UL_GPIO_Port,    
74
+    PLL_EN_2_1G_UL_Pin,
75
+};
76
+/* * * * * * * * ATTEN * * * * * * * */    
77
+ATTEN_Setting_st Atten_1_8Ghz_DL1 ={
78
+    ATT_CLK_GPIO_Port,
79
+    ATT_CLK_Pin,
80
+    ATT_DATA_GPIO_Port,
81
+    ATT_DATA_Pin,
82
+    ATT_EN_1_8G_DL1_GPIO_Port,    
83
+    ATT_EN_1_8G_DL1_Pin,
84
+    PATH_EN_1_8G_DL_GPIO_Port,
85
+    PATH_EN_1_8G_DL_Pin,
86
+};
87
+
88
+ATTEN_Setting_st Atten_1_8Ghz_DL2 ={
89
+    ATT_CLK_GPIO_Port,
90
+    ATT_CLK_Pin,
91
+    ATT_DATA_GPIO_Port,
92
+    ATT_DATA_Pin,
93
+    ATT_EN_1_8G_DL2_GPIO_Port,    
94
+    ATT_EN_1_8G_DL2_Pin,
95
+    PATH_EN_1_8G_DL_GPIO_Port,
96
+    PATH_EN_1_8G_DL_Pin,    
97
+};
98
+ATTEN_Setting_st Atten_1_8Ghz_UL1 ={
99
+    ATT_CLK_GPIO_Port,
100
+    ATT_CLK_Pin,
101
+    ATT_DATA_GPIO_Port,
102
+    ATT_DATA_Pin,
103
+    ATT_EN_1_8G_UL1_GPIO_Port,    
104
+    ATT_EN_1_8G_UL1_Pin,
105
+    PATH_EN_1_8G_UL_GPIO_Port,
106
+    PATH_EN_1_8G_UL_Pin,      
107
+};
108
+ATTEN_Setting_st Atten_1_8Ghz_UL2 ={
109
+    ATT_CLK_GPIO_Port,
110
+    ATT_CLK_Pin,
111
+    ATT_DATA_GPIO_Port,
112
+    ATT_DATA_Pin,
113
+    ATT_EN_1_8G_UL2_GPIO_Port,    
114
+    ATT_EN_1_8G_UL2_Pin,
115
+    PATH_EN_1_8G_UL_GPIO_Port,
116
+    PATH_EN_1_8G_UL_Pin,    
117
+};
118
+ATTEN_Setting_st Atten_1_8Ghz_UL3 ={
119
+    ATT_CLK_GPIO_Port,
120
+    ATT_CLK_Pin,
121
+    ATT_DATA_GPIO_Port,
122
+    ATT_DATA_Pin,
123
+    ATT_EN_1_8G_UL3_GPIO_Port,    
124
+    ATT_EN_1_8G_UL3_Pin,
125
+    PATH_EN_1_8G_UL_GPIO_Port,
126
+    PATH_EN_1_8G_UL_Pin,    
127
+};
128
+ATTEN_Setting_st Atten_1_8Ghz_UL4 ={
129
+    ATT_CLK_GPIO_Port,
130
+    ATT_CLK_Pin,
131
+    ATT_DATA_GPIO_Port,
132
+    ATT_DATA_Pin,
133
+    ATT_EN_1_8G_UL4_GPIO_Port,    
134
+    ATT_EN_1_8G_UL4_Pin,
135
+    PATH_EN_1_8G_UL_GPIO_Port,
136
+    PATH_EN_1_8G_UL_Pin,    
137
+};
138
+ATTEN_Setting_st Atten_2_1Ghz_DL1 ={
139
+    ATT_CLK_GPIO_Port,
140
+    ATT_CLK_Pin,
141
+    ATT_DATA_GPIO_Port,
142
+    ATT_DATA_Pin,
143
+    ATT_EN_2_1G_DL1_GPIO_Port,    
144
+    ATT_EN_2_1G_DL1_Pin,
145
+    PATH_EN_2_1G_DL_GPIO_Port,
146
+    PATH_EN_2_1G_DL_Pin,    
147
+};
148
+ATTEN_Setting_st Atten_2_1Ghz_DL2 ={
149
+    ATT_CLK_GPIO_Port,
150
+    ATT_CLK_Pin,
151
+    ATT_DATA_GPIO_Port,
152
+    ATT_DATA_Pin,
153
+    ATT_EN_2_1G_DL2_GPIO_Port,    
154
+    ATT_EN_2_1G_DL2_Pin,
155
+    PATH_EN_2_1G_DL_GPIO_Port,
156
+    PATH_EN_2_1G_DL_Pin,    
157
+};
158
+
159
+ATTEN_Setting_st Atten_2_1Ghz_UL1 ={
160
+    ATT_CLK_GPIO_Port,
161
+    ATT_CLK_Pin,
162
+    ATT_DATA_GPIO_Port,
163
+    ATT_DATA_Pin,
164
+    ATT_EN_2_1G_UL1_GPIO_Port,    
165
+    ATT_EN_2_1G_UL1_Pin,
166
+    PATH_EN_2_1G_UL_GPIO_Port,
167
+    PATH_EN_2_1G_UL_Pin,    
168
+};
169
+ATTEN_Setting_st Atten_2_1Ghz_UL2 ={
170
+    ATT_CLK_GPIO_Port,
171
+    ATT_CLK_Pin,
172
+    ATT_DATA_GPIO_Port,
173
+    ATT_DATA_Pin,
174
+    ATT_EN_2_1G_UL2_GPIO_Port,    
175
+    ATT_EN_2_1G_UL2_Pin,
176
+    PATH_EN_2_1G_UL_GPIO_Port,
177
+    PATH_EN_2_1G_UL_Pin,    
178
+};
179
+ATTEN_Setting_st Atten_2_1Ghz_UL3 ={
180
+    ATT_CLK_GPIO_Port,
181
+    ATT_CLK_Pin,
182
+    ATT_DATA_GPIO_Port,
183
+    ATT_DATA_Pin,
184
+    ATT_EN_2_1G_UL3_GPIO_Port,    
185
+    ATT_EN_2_1G_UL3_Pin,
186
+    PATH_EN_2_1G_UL_GPIO_Port,
187
+    PATH_EN_2_1G_UL_Pin,    
188
+};
189
+ATTEN_Setting_st Atten_2_1Ghz_UL4 ={
190
+    ATT_CLK_GPIO_Port,
191
+    ATT_CLK_Pin,
192
+    ATT_DATA_GPIO_Port,
193
+    ATT_DATA_Pin,
194
+    ATT_EN_2_1G_UL4_GPIO_Port,    
195
+    ATT_EN_2_1G_UL4_Pin,
196
+    PATH_EN_2_1G_UL_GPIO_Port,
197
+    PATH_EN_2_1G_UL_Pin,    
198
+};
199
+
200
+
201
+bool RF_Data_Check(uint8_t* data_buf){
202
+    bool ret = false;
203
+    bool crcret = STH30_CheckCrc(&data_buf[Type], data_buf[Length], data_buf[data_buf[Crcindex]]);
204
+    if(data_buf[Header] == BLUECELL_HEADER){ /*HEADER CHECK*/
205
+        ret= true;
206
+    }
207
+    if(crcret == true){/*CRC CHECK*/
208
+        ret = true;
209
+    }else{
210
+        ret = false;
211
+//        printf("Recv CRC Value : \"%d\"\r\n Create CRC Value : \"%d\"   \r\n",data_buf[data_buf[Crcindex]],STH30_CreateCrc(&data_buf[Type], data_buf[Length]));
212
+    }
213
+//    printf("CRC Result : \"%d\"   \r\n",ret);
214
+    return ret;
215
+
216
+}
217
+
218
+PLL_Setting_st Pll_3_5_H = {
219
+     PLL_CLK_3_5G_GPIO_Port,
220
+     PLL_CLK_3_5G_Pin,
221
+     PLL_DATA_3_5G_GPIO_Port,
222
+     PLL_DATA_3_5G_Pin,
223
+   PLL_EN_3_5G_H_GPIO_Port,    
224
+   PLL_EN_3_5G_H_Pin,
225
+ };
226
+ PLL_Setting_st Pll_3_5_L = {
227
+     PLL_CLK_3_5G_GPIO_Port,
228
+     PLL_CLK_3_5G_Pin,
229
+     PLL_DATA_3_5G_GPIO_Port,
230
+     PLL_DATA_3_5G_Pin,
231
+       PLL_EN_3_5G_L_GPIO_Port,    
232
+       PLL_EN_3_5G_L_Pin,
233
+ };
234
+void RF_Status_Get(void){
235
+//    printf("\r\nYJ2 : Prev_data[INDEX_DET_1_8G_DL_IN_L ] : %x\r\n",Prev_data[INDEX_DET_1_8G_DL_IN_L]);            
236
+    Prev_data[INDEX_BLUE_HEADER]   = BLUECELL_HEADER;
237
+    Prev_data[INDEX_BLUE_TYPE]     = TYPE_BLUECELL_GET;
238
+    Prev_data[INDEX_BLUE_LENGTH]   = INDEX_BLUE_EOF - 2;
239
+    Prev_data[INDEX_BLUE_CRCINDEX] = INDEX_BLUE_CRC;
240
+    Prev_data[INDEX_BLUE_CRC]      = STH30_CreateCrc(&Prev_data[Type], Prev_data[Length]);
241
+    Prev_data[INDEX_BLUE_EOF] = BLUECELL_TAILER;    
242
+    HAL_UART_Transmit_DMA(&huart1,&Prev_data[INDEX_BLUE_HEADER],INDEX_BLUE_EOF + 1); 
243
+//    printf("\r\nYJ : %x",ADCvalue[0]);
244
+//    printf("\r\n");
245
+
246
+}
247
+static uint8_t Ack_Buf[6];
248
+void RF_Status_Ack(void){
249
+//    printf("\r\nYJ2 : Prev_data[INDEX_DET_1_8G_DL_IN_L ] : %x\r\n",Prev_data[INDEX_DET_1_8G_DL_IN_L]);            
250
+    Ack_Buf[INDEX_BLUE_HEADER]       = BLUECELL_HEADER;
251
+    Ack_Buf[INDEX_BLUE_TYPE]         = TYPE_BLUECELL_ACK;
252
+    Ack_Buf[INDEX_BLUE_LENGTH]       = 3;
253
+    Ack_Buf[INDEX_BLUE_CRCINDEX + 0] = INDEX_BLUE_CRCINDEX + 1;
254
+    Ack_Buf[INDEX_BLUE_CRCINDEX + 1] = STH30_CreateCrc(&Ack_Buf[Type], Ack_Buf[Length]);
255
+    Ack_Buf[INDEX_BLUE_CRCINDEX + 2] = BLUECELL_TAILER;
256
+    HAL_UART_Transmit_DMA(&huart1,&Ack_Buf[INDEX_BLUE_HEADER],Ack_Buf[INDEX_BLUE_LENGTH]  + 3); 
257
+//    printf("\r\nYJ : %x",ADCvalue[0]);
258
+//    printf("\r\n");
259
+
260
+}
261
+
262
+void RF_Operate(uint8_t* data_buf){
263
+    uint32_t temp_val = 0;
264
+    uint8_t  ADC_Modify = 0;
265
+    ADF4153_R_N_Reg_st temp_reg;
266
+//    printf("Prev_data[INDEX_ATT_1_8G_DL1]  : %x  data_buf[INDEX_ATT_1_8G_DL1] : %x\r\n",Prev_data[INDEX_ATT_1_8G_DL1],data_buf[INDEX_ATT_1_8G_DL1]);
267
+    if(Prev_data[INDEX_ATT_1_8G_DL1] != data_buf[INDEX_ATT_1_8G_DL1]){
268
+        BDA4601_atten_ctrl(BDA4601_1_8G_DL1,(data_buf[INDEX_ATT_1_8G_DL1]));
269
+        Prev_data[INDEX_ATT_1_8G_DL1] = data_buf[INDEX_ATT_1_8G_DL1];
270
+    }
271
+    if(Prev_data[INDEX_ATT_1_8G_DL2] != data_buf[INDEX_ATT_1_8G_DL2]){
272
+        BDA4601_atten_ctrl(BDA4601_1_8G_DL2,(data_buf[INDEX_ATT_1_8G_DL2]));
273
+        Prev_data[INDEX_ATT_1_8G_DL2] = data_buf[INDEX_ATT_1_8G_DL2];
274
+    }
275
+    if(Prev_data[INDEX_ATT_1_8G_UL1] != data_buf[INDEX_ATT_1_8G_UL1]){
276
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL1,(data_buf[INDEX_ATT_1_8G_UL1]));
277
+        Prev_data[INDEX_ATT_1_8G_UL1] = data_buf[INDEX_ATT_1_8G_UL1];
278
+    }
279
+    if(Prev_data[INDEX_ATT_1_8G_UL2] != data_buf[INDEX_ATT_1_8G_UL2]){
280
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL2,(data_buf[INDEX_ATT_1_8G_UL2]));
281
+        Prev_data[INDEX_ATT_1_8G_UL2] = data_buf[INDEX_ATT_1_8G_UL2];
282
+    }
283
+    if(Prev_data[INDEX_ATT_1_8G_UL3] != data_buf[INDEX_ATT_1_8G_UL3]){
284
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL3,(data_buf[INDEX_ATT_1_8G_UL3]));
285
+        Prev_data[INDEX_ATT_1_8G_UL3] = data_buf[INDEX_ATT_1_8G_UL3];
286
+    }
287
+    if(Prev_data[INDEX_ATT_1_8G_UL4] != data_buf[INDEX_ATT_1_8G_UL4]){
288
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL4,(data_buf[INDEX_ATT_1_8G_UL4]));
289
+        Prev_data[INDEX_ATT_1_8G_UL4] = data_buf[INDEX_ATT_1_8G_UL4];
290
+    }
291
+    if(Prev_data[INDEX_ATT_2_1G_DL1] != data_buf[INDEX_ATT_2_1G_DL1]){
292
+        BDA4601_atten_ctrl(BDA4601_2_1G_DL1,(data_buf[INDEX_ATT_2_1G_DL1]));
293
+        Prev_data[INDEX_ATT_2_1G_DL1] = data_buf[INDEX_ATT_2_1G_DL1];
294
+
295
+    }
296
+    if(Prev_data[INDEX_ATT_2_1G_DL2] != data_buf[INDEX_ATT_2_1G_DL2]){
297
+        BDA4601_atten_ctrl(BDA4601_2_1G_DL2,(data_buf[INDEX_ATT_2_1G_DL2]));
298
+        Prev_data[INDEX_ATT_2_1G_DL2] = data_buf[INDEX_ATT_2_1G_DL2];
299
+
300
+    }
301
+    if(Prev_data[INDEX_ATT_2_1G_UL1] != data_buf[INDEX_ATT_2_1G_UL1]){
302
+        BDA4601_atten_ctrl(BDA4601_2_1G_UL1,(data_buf[INDEX_ATT_2_1G_UL1]));
303
+        Prev_data[INDEX_ATT_2_1G_UL1] = data_buf[INDEX_ATT_2_1G_UL1];
304
+
305
+    }
306
+    if(Prev_data[INDEX_ATT_2_1G_UL2] != data_buf[INDEX_ATT_2_1G_UL2]){
307
+        BDA4601_atten_ctrl(BDA4601_2_1G_UL2,(data_buf[INDEX_ATT_2_1G_UL2]));
308
+        Prev_data[INDEX_ATT_2_1G_UL2] = data_buf[INDEX_ATT_2_1G_UL2];
309
+
310
+    }
311
+    if(Prev_data[INDEX_ATT_2_1G_UL3] != data_buf[INDEX_ATT_2_1G_UL3]){
312
+        BDA4601_atten_ctrl(BDA4601_2_1G_UL3,(data_buf[INDEX_ATT_2_1G_UL3]));
313
+        Prev_data[INDEX_ATT_2_1G_UL3] = data_buf[INDEX_ATT_2_1G_UL3];
314
+    }
315
+    if(Prev_data[INDEX_ATT_2_1G_UL4] != data_buf[INDEX_ATT_2_1G_UL4]){
316
+        BDA4601_atten_ctrl(BDA4601_2_1G_UL4,(data_buf[INDEX_ATT_2_1G_UL4]));
317
+        Prev_data[INDEX_ATT_2_1G_UL4] = data_buf[INDEX_ATT_2_1G_UL4];
318
+    }
319
+    if(   (Prev_data[INDEX_ATT_3_5G_LOW1] != data_buf[INDEX_ATT_3_5G_LOW1])
320
+        ||(Prev_data[INDEX_ATT_3_5G_HIGH1] != data_buf[INDEX_ATT_3_5G_HIGH1])
321
+        ||(Prev_data[INDEX_ATT_3_5G_COM1] != data_buf[INDEX_ATT_3_5G_COM1])
322
+        ||(Prev_data[INDEX_ATT_3_5G_LOW2] != data_buf[INDEX_ATT_3_5G_LOW2])
323
+        ||(Prev_data[INDEX_ATT_3_5G_HIGH2] != data_buf[INDEX_ATT_3_5G_HIGH2])
324
+        ||(Prev_data[INDEX_ATT_3_5G_COM2] != data_buf[INDEX_ATT_3_5G_COM2])
325
+    ){
326
+        ALL_ATT_3_5G.data0 = Prev_data[INDEX_ATT_3_5G_LOW1]  = data_buf[INDEX_ATT_3_5G_LOW1];
327
+        ALL_ATT_3_5G.data1 = Prev_data[INDEX_ATT_3_5G_HIGH1] = data_buf[INDEX_ATT_3_5G_HIGH1];
328
+        ALL_ATT_3_5G.data2 = Prev_data[INDEX_ATT_3_5G_COM1]  = data_buf[INDEX_ATT_3_5G_COM1];
329
+        ALL_ATT_3_5G.data3 = Prev_data[INDEX_ATT_3_5G_LOW2]  = data_buf[INDEX_ATT_3_5G_LOW2];
330
+        ALL_ATT_3_5G.data4 = Prev_data[INDEX_ATT_3_5G_HIGH2] = data_buf[INDEX_ATT_3_5G_HIGH2];
331
+        ALL_ATT_3_5G.data5 = Prev_data[INDEX_ATT_3_5G_COM2]  = data_buf[INDEX_ATT_3_5G_COM2];
332
+        PE43711_ALL_atten_ctrl(ALL_ATT_3_5G);
333
+    }
334
+    if((Prev_data[INDEX_PLL_1_8G_DL_H] != data_buf[INDEX_PLL_1_8G_DL_H])
335
+        || (Prev_data[INDEX_PLL_1_8G_DL_L] != data_buf[INDEX_PLL_1_8G_DL_L])
336
+    ){
337
+        Prev_data[INDEX_PLL_1_8G_DL_H] = data_buf[INDEX_PLL_1_8G_DL_H];
338
+        Prev_data[INDEX_PLL_1_8G_DL_L] = data_buf[INDEX_PLL_1_8G_DL_L];
339
+//        printf("data_buf[INDEX_PLL_1_8G_DL_H] : %x \r\n",data_buf[INDEX_PLL_1_8G_DL_H]);
340
+//        printf("data_buf[INDEX_PLL_1_8G_DL_L] : %x\r\n",data_buf[INDEX_PLL_1_8G_DL_L]);
341
+        temp_val = (data_buf[INDEX_PLL_1_8G_DL_H] << 8) | (data_buf[INDEX_PLL_1_8G_DL_L]);
342
+        ADF4113_Module_Ctrl(ADF4113_1_8G_DL,0x410,halSynSetFreq(temp_val * 100000),0x9F8092);
343
+        HAL_Delay(1);
344
+        BDA4601_atten_ctrl(BDA4601_1_8G_DL1,(data_buf[INDEX_ATT_1_8G_DL1]));
345
+        BDA4601_atten_ctrl(BDA4601_1_8G_DL2,(data_buf[INDEX_ATT_1_8G_DL2]));
346
+    }
347
+    if((Prev_data[INDEX_PLL_1_8G_UL_H] != data_buf[INDEX_PLL_1_8G_UL_H])
348
+        || (Prev_data[INDEX_PLL_1_8G_UL_L] != data_buf[INDEX_PLL_1_8G_UL_L])){
349
+        temp_val = (data_buf[INDEX_PLL_1_8G_UL_H] << 8) | (data_buf[INDEX_PLL_1_8G_UL_L]);
350
+//        printf("data_buf[INDEX_PLL_1_8G_UL_H] : %x \r\n",data_buf[INDEX_PLL_1_8G_UL_H]);
351
+//        printf("data_buf[INDEX_PLL_1_8G_UL_L] : %x\r\n",data_buf[INDEX_PLL_1_8G_UL_L]);
352
+        Prev_data[INDEX_PLL_1_8G_UL_H] = data_buf[INDEX_PLL_1_8G_UL_H];
353
+        Prev_data[INDEX_PLL_1_8G_UL_L] = data_buf[INDEX_PLL_1_8G_UL_L];
354
+//         ADF4113_Module_Ctrl(ADF4113_1_8G_UL,0x000410,0x038D31,0x9f8092);
355
+         ADF4113_Module_Ctrl(ADF4113_1_8G_UL,0x410,halSynSetFreq(temp_val * 100000),0x9F8092);
356
+        HAL_Delay(1);
357
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL1,(data_buf[INDEX_ATT_1_8G_UL1]));
358
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL2,(data_buf[INDEX_ATT_1_8G_UL2]));
359
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL3,(data_buf[INDEX_ATT_1_8G_UL3]));
360
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL4,(data_buf[INDEX_ATT_1_8G_UL4]));
361
+    }
362
+    if((Prev_data[INDEX_PLL_2_1G_DL_H] != data_buf[INDEX_PLL_2_1G_DL_H])
363
+        || (Prev_data[INDEX_PLL_2_1G_DL_L] != data_buf[INDEX_PLL_2_1G_DL_L])){
364
+        temp_val = ((data_buf[INDEX_PLL_2_1G_DL_H] << 8) | (data_buf[INDEX_PLL_2_1G_DL_L]));
365
+//        printf("data_buf[INDEX_PLL_2_1G_DL_H] : %x \r\n",data_buf[INDEX_PLL_2_1G_DL_H]);
366
+//        printf("data_buf[INDEX_PLL_2_1G_DL_L] : %x\r\n",data_buf[INDEX_PLL_2_1G_DL_L]);
367
+        Prev_data[INDEX_PLL_2_1G_DL_H] = data_buf[INDEX_PLL_2_1G_DL_H];
368
+        Prev_data[INDEX_PLL_2_1G_DL_L] = data_buf[INDEX_PLL_2_1G_DL_L];        
369
+//         ADF4113_Module_Ctrl(ADF4113_2_1G_DL,0x410,0x4DE71,0x9F8092);
370
+        ADF4113_Module_Ctrl(ADF4113_2_1G_DL,0x410,halSynSetFreq(temp_val * 100000),0x9F8092);
371
+      HAL_Delay(1);
372
+      BDA4601_atten_ctrl(BDA4601_2_1G_DL1,(data_buf[INDEX_ATT_2_1G_DL1]));
373
+      BDA4601_atten_ctrl(BDA4601_2_1G_DL2,(data_buf[INDEX_ATT_2_1G_DL2]));
374
+    }
375
+    if((Prev_data[INDEX_PLL_2_1G_UL_H] != data_buf[INDEX_PLL_2_1G_UL_H])
376
+        || (Prev_data[INDEX_PLL_2_1G_UL_L] != data_buf[INDEX_PLL_2_1G_UL_L])){
377
+        Prev_data[INDEX_PLL_2_1G_UL_H] = data_buf[INDEX_PLL_2_1G_UL_H];
378
+        Prev_data[INDEX_PLL_2_1G_UL_L] = data_buf[INDEX_PLL_2_1G_UL_L];    
379
+//        printf("data_buf[INDEX_PLL_2_1G_UL_H] : %x \r\n",data_buf[INDEX_PLL_2_1G_UL_H]);
380
+//        printf("data_buf[INDEX_PLL_2_1G_UL_L] : %x\r\n",data_buf[INDEX_PLL_2_1G_UL_L]);
381
+        temp_val = (data_buf[INDEX_PLL_2_1G_UL_H] << 8) | (data_buf[INDEX_PLL_2_1G_UL_L]);
382
+//        ADF4113_Module_Ctrl(ADF4113_2_1G_UL,0x000410,0x59A31,0x9f8092);
383
+        ADF4113_Module_Ctrl(ADF4113_2_1G_UL,0x410,halSynSetFreq(temp_val * 100000),0x9F8092);
384
+      HAL_Delay(1);
385
+      BDA4601_atten_ctrl(BDA4601_2_1G_UL1,(data_buf[INDEX_ATT_2_1G_UL1]));
386
+      BDA4601_atten_ctrl(BDA4601_2_1G_UL2,(data_buf[INDEX_ATT_2_1G_UL2]));
387
+      BDA4601_atten_ctrl(BDA4601_2_1G_UL3,(data_buf[INDEX_ATT_2_1G_UL3]));      
388
+      BDA4601_atten_ctrl(BDA4601_2_1G_UL4,(data_buf[INDEX_ATT_2_1G_UL4]));      
389
+
390
+
391
+    }
392
+    if((Prev_data[INDEX_PLL_3_5G_LOW_H] != data_buf[INDEX_PLL_3_5G_LOW_H])
393
+        ||(Prev_data[INDEX_PLL_3_5G_LOW_M] != data_buf[INDEX_PLL_3_5G_LOW_M])
394
+        || (Prev_data[INDEX_PLL_3_5G_LOW_L] != data_buf[INDEX_PLL_3_5G_LOW_L])){
395
+        Prev_data[INDEX_PLL_3_5G_LOW_H] = data_buf[INDEX_PLL_3_5G_LOW_H];
396
+        Prev_data[INDEX_PLL_3_5G_LOW_M] = data_buf[INDEX_PLL_3_5G_LOW_M];        
397
+        Prev_data[INDEX_PLL_3_5G_LOW_L] = data_buf[INDEX_PLL_3_5G_LOW_L];
398
+        temp_val = (data_buf[INDEX_PLL_3_5G_LOW_H] << 16) | 
399
+                   (data_buf[INDEX_PLL_3_5G_LOW_M] << 8)  | 
400
+                   (data_buf[INDEX_PLL_3_5G_LOW_L]);
401
+#if 1 // PYJ.2019.08.12_BEGIN -- 
402
+        temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
403
+#else
404
+        temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
405
+#endif // PYJ.2019.08.12_END -- 
406
+        ADF4153_Module_Ctrl(Pll_3_5_L,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
407
+    }
408
+    if((Prev_data[INDEX_PLL_3_5G_HIGH_H] != data_buf[INDEX_PLL_3_5G_HIGH_H])
409
+        || (Prev_data[INDEX_PLL_3_5G_HIGH_M] != data_buf[INDEX_PLL_3_5G_HIGH_M])
410
+        || (Prev_data[INDEX_PLL_3_5G_HIGH_L] != data_buf[INDEX_PLL_3_5G_HIGH_L])){
411
+        Prev_data[INDEX_PLL_3_5G_HIGH_H] = data_buf[INDEX_PLL_3_5G_HIGH_H];
412
+        Prev_data[INDEX_PLL_3_5G_HIGH_M] = data_buf[INDEX_PLL_3_5G_HIGH_M];
413
+        Prev_data[INDEX_PLL_3_5G_HIGH_L] = data_buf[INDEX_PLL_3_5G_HIGH_L];
414
+        temp_val = (data_buf[INDEX_PLL_3_5G_HIGH_H] << 16) |
415
+                   (data_buf[INDEX_PLL_3_5G_HIGH_M] << 8)  |
416
+                   (data_buf[INDEX_PLL_3_5G_HIGH_L]);
417
+#if 1 // PYJ.2019.08.12_BEGIN -- 
418
+        temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
419
+#else
420
+        temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
421
+#endif // PYJ.2019.08.12_END -- 
422
+//        ADF4153_Module_Ctrl(Pll_3_5_H,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
423
+        ADF4153_Module_Ctrl(Pll_3_5_H,0x4006C0,0x163001,0x14C2,3);
424
+    }
425
+    if(Prev_data[INDEX_PLL_LD_6_BIT] != data_buf[INDEX_PLL_LD_6_BIT]){
426
+
427
+    }
428
+#if 0 // PYJ.2019.07.28_BEGIN -- 
429
+    if(Prev_data[INDEX_DET_1_8G_DL_IN_H] != data_buf[INDEX_DET_1_8G_DL_IN_H]){
430
+
431
+    }
432
+    if(Prev_data[INDEX_DET_1_8G_DL_IN_L] != data_buf[INDEX_DET_1_8G_DL_IN_L]){
433
+
434
+    }
435
+    if(Prev_data[INDEX_DET_1_8G_DL_OUT_H] != data_buf[INDEX_DET_1_8G_DL_OUT_H]){
436
+
437
+    }
438
+    if(Prev_data[INDEX_DET_1_8G_DL_OUT_L] != data_buf[INDEX_DET_1_8G_DL_OUT_L]){
439
+
440
+    }
441
+    if(Prev_data[INDEX_DET_1_8G_UL_IN_H] != data_buf[INDEX_DET_1_8G_UL_IN_H]){
442
+
443
+    }
444
+    if(Prev_data[INDEX_DET_1_8G_UL_IN_L] != data_buf[INDEX_DET_1_8G_UL_IN_L]){
445
+
446
+    }
447
+    if(Prev_data[INDEX_DET_1_8G_UL_OUT_H] != data_buf[INDEX_DET_1_8G_UL_OUT_H]){
448
+
449
+    }
450
+    if(Prev_data[INDEX_DET_1_8G_UL_OUT_L] != data_buf[INDEX_DET_1_8G_UL_OUT_L]){
451
+
452
+    }
453
+    if(Prev_data[INDEX_DET_2_1G_DL_IN_H] != data_buf[INDEX_DET_2_1G_DL_IN_H]){
454
+
455
+    }
456
+    if(Prev_data[INDEX_DET_2_1G_DL_IN_L] != data_buf[INDEX_DET_2_1G_DL_IN_L]){
457
+
458
+    }
459
+    if(Prev_data[INDEX_DET_2_1G_DL_OUT_H] != data_buf[INDEX_DET_2_1G_DL_OUT_H]){
460
+
461
+    }
462
+    if(Prev_data[INDEX_DET_2_1G_DL_OUT_L] != data_buf[INDEX_DET_2_1G_DL_OUT_L]){
463
+
464
+    }
465
+    if(Prev_data[INDEX_DET_2_1G_UL_IN_H] != data_buf[INDEX_DET_2_1G_UL_IN_H]){
466
+
467
+    }
468
+    if(Prev_data[INDEX_DET_2_1G_UL_IN_L] != data_buf[INDEX_DET_2_1G_UL_IN_L]){
469
+
470
+    }
471
+
472
+    if(Prev_data[INDEX_DET_2_1G_UL_OUT_H] != data_buf[INDEX_DET_2_1G_UL_OUT_H]){
473
+
474
+    }
475
+    if(Prev_data[INDEX_DET_2_1G_UL_OUT_L] != data_buf[INDEX_DET_2_1G_UL_OUT_L]){
476
+
477
+    }
478
+    if(Prev_data[INDEX_DET_3_5G_DL_IN_H] != data_buf[INDEX_DET_3_5G_DL_IN_H]){
479
+
480
+    }
481
+    if(Prev_data[INDEX_DET_3_5G_DL_IN_L] != data_buf[INDEX_DET_3_5G_DL_IN_L]){
482
+
483
+    }
484
+    if(Prev_data[INDEX_DET_3_5G_DL_OUT_L] != data_buf[INDEX_DET_3_5G_DL_OUT_L]){
485
+
486
+    }
487
+    if(Prev_data[INDEX_DET_3_5G_DL_OUT_H] != data_buf[INDEX_DET_3_5G_DL_OUT_H]){
488
+
489
+    }
490
+    if(Prev_data[INDEX_DET_3_5G_UL_IN_H] != data_buf[INDEX_DET_3_5G_UL_IN_H]){
491
+
492
+    }
493
+    if(Prev_data[INDEX_DET_3_5G_UL_IN_L] != data_buf[INDEX_DET_3_5G_UL_IN_L]){
494
+
495
+    }
496
+
497
+    if(Prev_data[INDEX_DET_3_5G_UL_OUT_H] != data_buf[INDEX_DET_3_5G_UL_OUT_H]){
498
+
499
+    }
500
+    if(Prev_data[INDEX_DET_3_5G_UL_OUT_L] != data_buf[INDEX_DET_3_5G_UL_OUT_L]){
501
+
502
+    }
503
+    if(Prev_data[INDEX_RFU_TEMP_H] != data_buf[INDEX_RFU_TEMP_H]){
504
+
505
+    }
506
+    if(Prev_data[INDEX_RFU_TEMP_L] != data_buf[INDEX_RFU_TEMP_L]){
507
+
508
+    }
509
+    if(Prev_data[INDEX__28V_DET_H] != data_buf[INDEX__28V_DET_H]){
510
+
511
+    }
512
+    if(Prev_data[INDEX__28V_DET_L] != data_buf[INDEX__28V_DET_L]){
513
+
514
+    }
515
+#endif // PYJ.2019.07.28_END -- 
516
+    if(Prev_data[INDEX_ALARM_AC] != data_buf[INDEX_ALARM_AC]){
517
+
518
+    }
519
+    if(Prev_data[INDEX_ALARM_DC] != data_buf[INDEX_ALARM_DC]){
520
+
521
+    }
522
+    if(Prev_data[INDEX_PATH_EN_1_8G_DL] != data_buf[INDEX_PATH_EN_1_8G_DL]){
523
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_1_8G_DL,data_buf[INDEX_PATH_EN_1_8G_DL]);
524
+        Prev_data[INDEX_PATH_EN_1_8G_DL] = data_buf[INDEX_PATH_EN_1_8G_DL];
525
+    }
526
+    if(Prev_data[INDEX_PATH_EN_1_8G_UL] != data_buf[INDEX_PATH_EN_1_8G_UL]){
527
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_1_8G_UL,data_buf[INDEX_PATH_EN_1_8G_UL]);
528
+        Prev_data[INDEX_PATH_EN_1_8G_UL] = data_buf[INDEX_PATH_EN_1_8G_UL];
529
+
530
+    }
531
+
532
+    if(Prev_data[INDEX_PATH_EN_2_1G_DL] != data_buf[INDEX_PATH_EN_2_1G_DL]){
533
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_2_1G_DL,data_buf[INDEX_PATH_EN_2_1G_DL]);
534
+        Prev_data[INDEX_PATH_EN_2_1G_DL] = data_buf[INDEX_PATH_EN_2_1G_DL];
535
+    }
536
+    if(Prev_data[INDEX_PATH_EN_2_1G_UL] != data_buf[INDEX_PATH_EN_2_1G_UL]){
537
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_2_1G_UL,data_buf[INDEX_PATH_EN_2_1G_UL]);
538
+        Prev_data[INDEX_PATH_EN_2_1G_UL] = data_buf[INDEX_PATH_EN_2_1G_UL];
539
+
540
+    }
541
+    if(Prev_data[INDEX_PATH_EN_3_5G_L] != data_buf[INDEX_PATH_EN_3_5G_L]){
542
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_L,data_buf[INDEX_PATH_EN_3_5G_L]);
543
+        Prev_data[INDEX_PATH_EN_3_5G_L] = data_buf[INDEX_PATH_EN_3_5G_L];
544
+
545
+    }
546
+    if(Prev_data[INDEX_PATH_EN_3_5G_H] != data_buf[INDEX_PATH_EN_3_5G_H]){
547
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_H,data_buf[INDEX_PATH_EN_3_5G_H]);
548
+        Prev_data[INDEX_PATH_EN_3_5G_H] = data_buf[INDEX_PATH_EN_3_5G_H];
549
+    
550
+
551
+    }
552
+    if(Prev_data[INDEX_PATH_EN_3_5G_DL] != data_buf[INDEX_PATH_EN_3_5G_DL]){
553
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_DL,data_buf[INDEX_PATH_EN_3_5G_DL]);
554
+        Prev_data[INDEX_PATH_EN_3_5G_DL] = data_buf[INDEX_PATH_EN_3_5G_DL];
555
+        ADC_Modify = 1;
556
+
557
+    }
558
+    if(Prev_data[INDEX_PATH_EN_3_5G_UL] != data_buf[INDEX_PATH_EN_3_5G_UL]){
559
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_UL,data_buf[INDEX_PATH_EN_3_5G_UL]);
560
+        Prev_data[INDEX_PATH_EN_3_5G_UL] = data_buf[INDEX_PATH_EN_3_5G_UL];
561
+        ADC_Modify = 1;
562
+    }
563
+    if(Prev_data[INDEX_PLL_ON_OFF_3_5G_H] != data_buf[INDEX_PLL_ON_OFF_3_5G_H]){
564
+        Power_ON_OFF_Ctrl(INDEX_PLL_ON_OFF_3_5G_H,data_buf[INDEX_PLL_ON_OFF_3_5G_H]);
565
+        Prev_data[INDEX_PLL_ON_OFF_3_5G_H] = data_buf[INDEX_PLL_ON_OFF_3_5G_H];
566
+        HAL_Delay(1);
567
+//        printf("POWER : %d \r\n",Prev_data[INDEX_PLL_ON_OFF_3_5G_H]);
568
+        if(data_buf[INDEX_PLL_ON_OFF_3_5G_H]){
569
+//            printf("PLL CTRL START !! \r\n");
570
+#if 1 // PYJ.2019.08.12_BEGIN -- 
571
+//            temp_val = (Prev_data[INDEX_PLL_3_5G_LOW_H] << 16) |
572
+//                       (Prev_data[INDEX_PLL_3_5G_LOW_M] << 8) | 
573
+//                       (Prev_data[INDEX_PLL_3_5G_LOW_L]);
574
+            temp_val = (Prev_data[INDEX_PLL_3_5G_HIGH_H] << 16) | 
575
+                       (Prev_data[INDEX_PLL_3_5G_HIGH_M] << 8)  | 
576
+                       (Prev_data[INDEX_PLL_3_5G_HIGH_L]);
577
+
578
+
579
+//            temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
580
+            temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_122_88MHzREFIN,ADF4153_8RCOUNTER,ADF4153_CHANNEL_SPACING);
581
+#else
582
+            temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
583
+#endif // PYJ.2019.08.12_END -- 
584
+//            ADF4153_Module_Ctrl(Pll_3_5_H,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
585
+            ADF4153_Module_Ctrl(Pll_3_5_H,0x4006C0,0x163001,0x14C2,3);
586
+
587
+            PE43711_ALL_atten_ctrl(ALL_ATT_3_5G);
588
+        }
589
+    }
590
+    if(Prev_data[INDEX_PLL_ON_OFF_3_5G_L] != data_buf[INDEX_PLL_ON_OFF_3_5G_L]){
591
+        Power_ON_OFF_Ctrl(INDEX_PLL_ON_OFF_3_5G_L,data_buf[INDEX_PLL_ON_OFF_3_5G_L]);
592
+        Prev_data[INDEX_PLL_ON_OFF_3_5G_L] = data_buf[INDEX_PLL_ON_OFF_3_5G_L];
593
+        HAL_Delay(1);
594
+//        printf("POWER : %d \r\n",Prev_data[INDEX_PLL_ON_OFF_3_5G_L]);        
595
+        if(data_buf[INDEX_PLL_ON_OFF_3_5G_L]){
596
+//            printf("PLL CTRL START !! \r\n");
597
+#if 1 // PYJ.2019.08.12_BEGIN -- 
598
+//            temp_val = (Prev_data[INDEX_PLL_3_5G_HIGH_H] << 16) | 
599
+//                       (Prev_data[INDEX_PLL_3_5G_HIGH_M] << 8)  | 
600
+//                       (Prev_data[INDEX_PLL_3_5G_HIGH_L]);
601
+            temp_val = (Prev_data[INDEX_PLL_3_5G_LOW_H] << 16) |
602
+                       (Prev_data[INDEX_PLL_3_5G_LOW_M] << 8) | 
603
+                       (Prev_data[INDEX_PLL_3_5G_LOW_L]);
604
+            temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
605
+//            temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_122_88MHzREFIN,ADF4153_8RCOUNTER,ADF4153_CHANNEL_SPACING);
606
+#else
607
+          temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);            
608
+#endif // PYJ.2019.08.12_END -- 
609
+            ADF4153_Module_Ctrl(Pll_3_5_L,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
610
+            PE43711_ALL_atten_ctrl(ALL_ATT_3_5G);
611
+        }
612
+    }
613
+
614
+    if(Prev_data[INDEX_T_SYNC_DL] != data_buf[INDEX_T_SYNC_DL]){
615
+        Prev_data[INDEX_T_SYNC_DL] = data_buf[INDEX_T_SYNC_DL];
616
+        Power_ON_OFF_Ctrl(INDEX_T_SYNC_DL,data_buf[INDEX_T_SYNC_DL]);
617
+    }
618
+    if(Prev_data[INDEX__T_SYNC_DL] != data_buf[INDEX__T_SYNC_DL]){
619
+        Prev_data[INDEX__T_SYNC_DL] = data_buf[INDEX__T_SYNC_DL];
620
+        Power_ON_OFF_Ctrl(INDEX__T_SYNC_DL,data_buf[INDEX__T_SYNC_DL]);
621
+    }
622
+    if(Prev_data[INDEX_T_SYNC_UL] != data_buf[INDEX_T_SYNC_UL]){
623
+        Prev_data[INDEX_T_SYNC_UL] = data_buf[INDEX_T_SYNC_UL];
624
+        Power_ON_OFF_Ctrl(INDEX_T_SYNC_UL,data_buf[INDEX_T_SYNC_UL]);
625
+    }
626
+    if(Prev_data[INDEX__T_SYNC_UL] != data_buf[INDEX__T_SYNC_UL]){
627
+        Prev_data[INDEX__T_SYNC_UL] = data_buf[INDEX__T_SYNC_UL];
628
+        Power_ON_OFF_Ctrl(INDEX__T_SYNC_UL,data_buf[INDEX__T_SYNC_UL]);
629
+    }
630
+
631
+
632
+    if((Prev_data[INDEX_DAC_VCtrl_A_H] != data_buf[INDEX_DAC_VCtrl_A_H])
633
+        ||(Prev_data[INDEX_DAC_VCtrl_A_L] != data_buf[INDEX_DAC_VCtrl_A_L])){
634
+        ADC_Modify = 1;
635
+        Prev_data[INDEX_DAC_VCtrl_A_H] = data_buf[INDEX_DAC_VCtrl_A_H];
636
+        Prev_data[INDEX_DAC_VCtrl_A_L] = data_buf[INDEX_DAC_VCtrl_A_L];
637
+    }
638
+    if((Prev_data[INDEX_DAC_VCtrl_B_H] != data_buf[INDEX_DAC_VCtrl_B_H])
639
+        ||(Prev_data[INDEX_DAC_VCtrl_B_L] != data_buf[INDEX_DAC_VCtrl_B_L])){
640
+        ADC_Modify = 1;
641
+        
642
+        Prev_data[INDEX_DAC_VCtrl_B_H] = data_buf[INDEX_DAC_VCtrl_B_H];
643
+        Prev_data[INDEX_DAC_VCtrl_B_L] = data_buf[INDEX_DAC_VCtrl_B_L];        
644
+    }    
645
+    if((Prev_data[INDEX_DAC_VCtrl_C_H] != data_buf[INDEX_DAC_VCtrl_C_H])
646
+        ||(Prev_data[INDEX_DAC_VCtrl_C_L] != data_buf[INDEX_DAC_VCtrl_C_L])){
647
+        ADC_Modify = 1;
648
+//        printf("Prev_data[INDEX_DAC_VCtrl_C_H] : %x \r\n",Prev_data[INDEX_DAC_VCtrl_C_H]);
649
+//        printf("Prev_data[INDEX_DAC_VCtrl_C_L] : %x \r\n",Prev_data[INDEX_DAC_VCtrl_C_L]);
650
+
651
+        Prev_data[INDEX_DAC_VCtrl_C_H] = data_buf[INDEX_DAC_VCtrl_C_H];
652
+        Prev_data[INDEX_DAC_VCtrl_C_L] = data_buf[INDEX_DAC_VCtrl_C_L];        
653
+    }
654
+    if((Prev_data[INDEX_DAC_VCtrl_D_H] != data_buf[INDEX_DAC_VCtrl_D_H])
655
+        ||(Prev_data[INDEX_DAC_VCtrl_D_L] != data_buf[INDEX_DAC_VCtrl_D_L])){
656
+        ADC_Modify = 1;
657
+        Prev_data[INDEX_DAC_VCtrl_D_H] = data_buf[INDEX_DAC_VCtrl_D_H];
658
+        Prev_data[INDEX_DAC_VCtrl_D_L] = data_buf[INDEX_DAC_VCtrl_D_L];
659
+    }
660
+    if((Prev_data[INDEX_DAC_VCtrl_E_H] != data_buf[INDEX_DAC_VCtrl_E_H])
661
+        ||(Prev_data[INDEX_DAC_VCtrl_E_L] != data_buf[INDEX_DAC_VCtrl_E_L])){
662
+        ADC_Modify = 1;
663
+
664
+        Prev_data[INDEX_DAC_VCtrl_E_H] = data_buf[INDEX_DAC_VCtrl_E_H];
665
+        Prev_data[INDEX_DAC_VCtrl_E_L] = data_buf[INDEX_DAC_VCtrl_E_L];        
666
+    }
667
+    if((Prev_data[INDEX_DAC_VCtrl_F_H] != data_buf[INDEX_DAC_VCtrl_F_H])
668
+        ||(Prev_data[INDEX_DAC_VCtrl_F_L] != data_buf[INDEX_DAC_VCtrl_F_L])){
669
+        ADC_Modify = 1;
670
+        Prev_data[INDEX_DAC_VCtrl_F_H] = data_buf[INDEX_DAC_VCtrl_F_H];
671
+        Prev_data[INDEX_DAC_VCtrl_F_L] = data_buf[INDEX_DAC_VCtrl_F_L];        
672
+    }
673
+    if((Prev_data[INDEX_DAC_VCtrl_G_H] != data_buf[INDEX_DAC_VCtrl_G_H])
674
+        ||(Prev_data[INDEX_DAC_VCtrl_G_L] != data_buf[INDEX_DAC_VCtrl_G_L])){
675
+        ADC_Modify = 1;
676
+        Prev_data[INDEX_DAC_VCtrl_G_H] = data_buf[INDEX_DAC_VCtrl_G_H];
677
+        Prev_data[INDEX_DAC_VCtrl_G_L] = data_buf[INDEX_DAC_VCtrl_G_L];        
678
+    }    
679
+    if((Prev_data[INDEX_DAC_VCtrl_H_H] != data_buf[INDEX_DAC_VCtrl_H_H])
680
+        ||(Prev_data[INDEX_DAC_VCtrl_H_L] != data_buf[INDEX_DAC_VCtrl_H_L])){
681
+        ADC_Modify = 1;
682
+        Prev_data[INDEX_DAC_VCtrl_H_H] = data_buf[INDEX_DAC_VCtrl_H_H];
683
+        Prev_data[INDEX_DAC_VCtrl_H_L] = data_buf[INDEX_DAC_VCtrl_H_L];        
684
+    }
685
+    if(ADC_Modify){
686
+//        AD5318_Ctrl(0xF000);
687
+//        HAL_Delay(1);
688
+//        AD5318_Ctrl(0x800C);
689
+//        AD5318_Ctrl(0x2FFF );
690
+//        AD5318_Ctrl(0xA000);
691
+//        printf("DAC CTRL START \r\n");
692
+//        AD5318_Ctrl(0x800C);
693
+//        AD5318_Ctrl(0xA000);
694
+//        printf("DAC Change\r\n");
695
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_A_H] << 8 | Prev_data[INDEX_DAC_VCtrl_A_L]));    
696
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_B_H] << 8 | Prev_data[INDEX_DAC_VCtrl_B_L]));    
697
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_C_H] << 8 | Prev_data[INDEX_DAC_VCtrl_C_L]));
698
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_D_H] << 8 | Prev_data[INDEX_DAC_VCtrl_D_L]));
699
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_E_H] << 8 | Prev_data[INDEX_DAC_VCtrl_E_L]));    
700
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_F_H] << 8 | Prev_data[INDEX_DAC_VCtrl_F_L]));
701
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_G_H] << 8 | Prev_data[INDEX_DAC_VCtrl_G_L]));
702
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_H_H] << 8 | Prev_data[INDEX_DAC_VCtrl_H_L]));
703
+    }
704
+    
705
+}
706
+
707
+uint8_t temp_crc = 0;
708
+bool RF_Ctrl_Main(uint8_t* data_buf){
709
+    bool ret = false;
710
+    Bluecell_Prot_t type = data_buf[Type];
711
+    ret = RF_Data_Check(&data_buf[Header]); /* ERROR CHECK */
712
+    if(ret == false){
713
+        HAL_UART_Transmit(&huart1,&data_buf[INDEX_BLUE_HEADER],data_buf[INDEX_BLUE_LENGTH] + 2 + 1,3000); 
714
+        return ret;
715
+    }
716
+    
717
+    switch(type){
718
+    case TYPE_BLUECELL_RESET:
719
+        for(uint8_t i =0 ; i < data_buf[Length] + 6; i++)
720
+            printf("%02x ",data_buf[i]);
721
+        printf("Reset Start \r\n");
722
+        NVIC_SystemReset();
723
+        break;
724
+    case TYPE_BLUECELL_SET:
725
+#if 0 // PYJ.2019.07.31_BEGIN -- 
726
+    printf("TYPE_BLUECELL_SET : ");
727
+    for(uint8_t i =0 ; i < INDEX_BLUE_EOF + 1; i++)
728
+        printf("%02x ",data_buf[i]);
729
+#endif // PYJ.2019.07.31_END -- 
730
+        RF_Operate(&data_buf[Header]);
731
+        RF_Status_Ack();
732
+
733
+//        ADF4153_Freq_Calc(3465500000,40000000,2,5000);
734
+//        ADF4153_Freq_Calc(3993450000,40000000,2,5000);
735
+//        halSynSetFreq(1995000000);
736
+//        halSynSetFreq(1600000000);
737
+//        halSynSetFreq(1455000000);        
738
+        break;
739
+    case TYPE_BLUECELL_GET:
740
+#if 0 // PYJ.2019.08.01_BEGIN -- 
741
+        printf("\r\nTYPE_BLUECELL_GET : \r\n");
742
+#endif // PYJ.2019.08.01_END -- 
743
+        RF_Status_Get();
744
+        break;
745
+    case TYPE_BLUECELL_SAVE:
746
+//        printf("\r\nFLASH Write\r\n");
747
+        Bluecell_Flash_Write(&Prev_data[INDEX_BLUE_HEADER]);
748
+        RF_Status_Ack();
749
+
750
+        break;
751
+        default:
752
+#ifdef DEBUG_PRINT // PYJ.2019.07.27_BEGIN --         
753
+            printf("Function : %s   LINE : %d    type : %d \r\n",__func__,__LINE__,type);
754
+#endif
755
+            break;
756
+    }
757
+    return ret;
758
+}

二進制
insight/STM32F103_ATTEN_PLL_Zig.si4project/STM32F103_ATTEN_PLL_Zig.siwork


二進制
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_adf4153.h.sisc


二進制
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_adf4153.c.sisc


二進制
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_main.c.sisc


二進制
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_uart.c.sisc


二進制
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_zig_operate.c.sisc