adf4153 define 추가 /계산 식 추가 / Atten BDA4601 제어문 추가 각 포트,핀 별로 변수 추가 /includes.h 헤더 추가/ PE43711 추가

GUI 에서 ATTEN 제어 할 수 있도록 프로토콜 갱신
GUI 에서 1.8 /  2.1 제어 할 수 있도록 프르토콜 갱신
3.5GHz PLL FIx 로 인한 제어 무시
GUI 에서 TDD 제어 할 수 있도록 프로토콜 갱신

Debug/Src/BDA4601.su

@@ -1 +1,2 @@
-BDA4601.c:8:6:BDA4601_atten_ctrl	16	static
+BDA4601.c:127:6:BDA4601_atten_ctrl	40	static
+BDA4601.c:108:6:BDA4601_Test	24	static

Debug/Src/PE43711.su

@@ -1 +1,4 @@
-PE43711.c:61:6:PE43711_atten_ctrl	16	static
+PE43711.c:69:6:Bit_Compare	0	static
+PE43711.c:77:6:PE43711_ALL_atten_ctrl	56	static
+PE43711.c:55:6:PE43711_PinInit	152	static
+PE43711.c:96:6:PE43711_atten_ctrl	40	static

Debug/Src/main.su

@@ -1,6 +1,6 @@
 main.c:78:6:HAL_TIM_PeriodElapsedCallback	0	static
 main.c:86:5:_write	8	static
 main.c:91:6:Pol_Delay_us	8	static
-main.c:254:6:SystemClock_Config	96	static
-main.c:108:5:main	104	static
-main.c:683:6:Error_Handler	0	static
+main.c:258:6:SystemClock_Config	96	static
+main.c:108:5:main	232	static
+main.c:687:6:Error_Handler	0	static

Inc/BDA4601.h

@@ -8,6 +8,34 @@
 #ifndef BDA4601_H_
 #define BDA4601_H_
 #include "main.h"
-//void BDA4601_atten_ctrl(PE43711_st* type ,double data);
+typedef struct{
+   GPIO_TypeDef *CLK_PORT;
+   uint16_t CLK_PIN;
+
+   GPIO_TypeDef *SERIAL_IN_PORT;
+   uint16_t SERIAL_IN_PIN;;
+
+   GPIO_TypeDef *LE_PORT;
+   uint16_t LE_PIN;
+
+}BDA4601_st;
+BDA4601_st BDA4601_1_8G_DL1;
+BDA4601_st BDA4601_1_8G_DL2;
+BDA4601_st BDA4601_1_8G_UL1;
+BDA4601_st BDA4601_1_8G_UL2;
+BDA4601_st BDA4601_1_8G_UL3;    
+BDA4601_st BDA4601_1_8G_UL4;          
+
+BDA4601_st BDA4601_2_1G_DL1;
+BDA4601_st BDA4601_2_1G_DL2;           
+BDA4601_st BDA4601_2_1G_UL1;           
+BDA4601_st BDA4601_2_1G_UL2;           
+BDA4601_st BDA4601_2_1G_UL3;           
+BDA4601_st BDA4601_2_1G_UL4;    
+
+void BDA4601_atten_ctrl(BDA4601_st type ,uint8_t data);
+uint8_t BDA4601_Data_Calc(uint8_t val);
+
+void BDA4601_Test(void);
 
 #endif /* BDA4601_H_ */

Inc/PE43711.h

@@ -8,25 +8,33 @@
 #ifndef PE43711_H_
 #define PE43711_H_
 #include "main.h"
- typedef struct{
-    uint16_t ATT_EN_1_8G_DL1_PIN;
-    GPIO_TypeDef *ATT_EN_1_8G_DL1_PORT;
-
-    uint16_t ATT_EN_1_8G_DL2_PIN;
-    GPIO_TypeDef *ATT_EN_1_8G_DL2_PORT;
+ void PE43711_PinInit(void);
 
-    uint16_t ATT_EN_1_8G_UL1_PIN;
-    GPIO_TypeDef *ATT_EN_1_8G_UL1_PORT;
 
-    uint16_t ATT_EN_1_8G_UL2_PIN;
-    GPIO_TypeDef *ATT_EN_1_8G_UL2_PORT;
+ typedef struct{
+    GPIO_TypeDef * CLK_PORT;
+    uint16_t CLK_PIN;
 
-    uint16_t ATT_EN_1_8G_UL3_PIN;
-    GPIO_TypeDef *ATT_EN_1_8G_UL3_PORT;
+    GPIO_TypeDef *DATA_PORT;
+    uint16_t DATA_PIN;
 
-    uint16_t ATT_EN_1_8G_UL4_PIN;
-    GPIO_TypeDef *ATT_EN_1_8G_UL4_PORT;
+    GPIO_TypeDef *LE_PORT;
+    uint16_t LE_PIN;
  }PE43711_st;
+ 
+ typedef struct{
+     PE43711_st ATT0;
+     uint8_t    data0;
+     PE43711_st ATT1;
+     uint8_t    data1;
+     PE43711_st ATT2;
+     uint8_t    data2;
+     PE43711_st ATT3;
+     uint8_t    data3;
+     PE43711_st ATT4;    
+     uint8_t    data4;
+ }ALL_PE43711_st;
+ALL_PE43711_st ALL_ATT_3_5G;
 
 
 #endif /* PE43711_H_ */

Inc/adf4153.h

@@ -43,19 +43,25 @@
 #define __ADF4153_H__
 
 #include "main.h"
-typedef struct _PLL_Setting_st{
 
-    GPIO_TypeDef * PLL_CLK_PORT;
-    uint16_t       PLL_CLK_PIN;
-    GPIO_TypeDef * PLL_DATA_PORT;
-    uint16_t       PLL_DATA_PIN;
-    GPIO_TypeDef * PLL_ENABLE_PORT;
-    uint16_t       PLL_ENABLE_PIN;
-} PLL_Setting_st;
-void ADF4153_Freq_Calc(unsigned long long Freq,unsigned long long REFin,uint8_t R_Counter,uint32_t chspacing);
 
 
-void ADF_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2,uint32_t R3);
+
+#define ADF4153_REFIN 40000000
+#define ADF4153_RCOUNTER 2
+#define ADF4153_CHANNEL_SPACING 5000
+
+
+typedef struct {
+    uint32_t R_reg;
+    uint32_t N_reg;
+}ADF4153_R_N_Reg_st;
+
+//void ADF4153_Freq_Calc(unsigned long long Freq,unsigned long long REFin,uint8_t R_Counter,uint32_t chspacing);
+
+
+//void ADF4153_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2,uint32_t R3);
+ADF4153_R_N_Reg_st ADF4153_Freq_Calc(unsigned long long Freq,unsigned long long REFin,uint8_t R_Counter,uint32_t chspacing);
 
 
 #endif // __ADF4153_H__

Inc/includes.h

@@ -0,0 +1,28 @@
+/*
+ * includes.h
+ *
+ *  Created on: 2019. 7. 28.
+ *      Author: parkyj
+ */
+
+#ifndef INCLUDES_H_
+#define INCLUDES_H_
+#include "main.h"
+#if 0 // PYJ.2019.07.28_BEGIN -- 
+typedef enum{
+    TYPE_PATH_EN_1_8G_DL  = 0 , 
+    TYPE_PATH_EN_1_8G_UL  ,
+    TYPE_PATH_EN_2_1G_DL  ,
+    TYPE_PATH_EN_2_1G_UL  ,
+    TYPE_PATH_EN_3_5G_L   ,
+    TYPE_PATH_EN_3_5G_H   ,
+    TYPE_PATH_EN_3_5G_DL  ,
+    TYPE_PATH_EN_3_5G_UL  ,
+    TYPE_PLL_ON_OFF_3_5G_L,
+    TYPE_PLL_ON_OFF_3_5G_H,
+}Bluecell_Power_Index;
+#endif // PYJ.2019.07.28_END -- 
+void Power_ON_OFF_Ctrl(uint8_t type,uint8_t cmd);
+
+
+#endif /* INCLUDES_H_ */

Inc/main.h

@@ -40,7 +40,7 @@ extern "C" {
 #include "pll_4113.h"
 #include "adf4153.h"
 #include "uart.h"
-
+#include "includes.h"
 /* USER CODE END Includes */
 
 /* Exported types ------------------------------------------------------------*/
@@ -62,6 +62,7 @@ typedef struct _ATTEN_Setting_st{
     uint16_t       PATH_EN_PIN;    
 } ATTEN_Setting_st;
 
+
 /* USER CODE END EC */
 
 /* Exported macro ------------------------------------------------------------*/

Inc/pll_4113.h

@@ -7,8 +7,21 @@
 #ifndef HAL_ADF4113_H
 #define HAL_ADF4113_H
 #include "main.h"
+typedef struct _PLL_Setting_st{
+    GPIO_TypeDef * PLL_CLK_PORT;
+    uint16_t       PLL_CLK_PIN;
+    GPIO_TypeDef * PLL_DATA_PORT;
+    uint16_t       PLL_DATA_PIN;
+    GPIO_TypeDef * PLL_ENABLE_PORT;
+    uint16_t       PLL_ENABLE_PIN;
+} PLL_Setting_st;
+PLL_Setting_st ADF4113_1_8G_DL;
+PLL_Setting_st ADF4113_1_8G_UL;
+PLL_Setting_st ADF4113_2_1G_DL;
+PLL_Setting_st ADF4113_2_1G_UL;
 
 uint8_t halSynSetFreq(uint32_t rf_Freq);
+void ADF4113_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2);
 
 //void ADF4113_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2);
 

Inc/zig_operate.h

@@ -18,5 +18,87 @@ typedef enum{
     Crcindex,
 }Bluecell_Prot_p;
 
+typedef enum {
+    TYPE_BLUECELL_RESET = 0,
+    TYPE_BLUECELL_SET   = 1,
+    TYPE_BLUECELL_GET   = 2,
+}Bluecell_Prot_t;
+
+typedef enum{
+    INDEX_ATT_1_8G_DL1 = 4,
+    INDEX_ATT_1_8G_DL2 ,
+    INDEX_ATT_1_8G_UL1 ,
+    INDEX_ATT_1_8G_UL2 ,
+    INDEX_ATT_1_8G_UL3 ,
+    INDEX_ATT_1_8G_UL4 , //5
+    INDEX_ATT_2_1G_DL1 ,
+    INDEX_ATT_2_1G_DL2 ,
+    INDEX_ATT_2_1G_UL1 ,
+    INDEX_ATT_2_1G_UL2 ,
+    INDEX_ATT_2_1G_UL3 , //10
+    INDEX_ATT_2_1G_UL4 ,
+    INDEX_ATT_3_5G_DL  ,
+    INDEX_ATT_3_5G_UL  ,
+    INDEX_ATT_3_5G_COM1,
+    INDEX_ATT_3_5G_COM2, //15
+    INDEX_ATT_3_5G_COM3,
+    INDEX_PLL_1_8G_DL_H,
+    INDEX_PLL_1_8G_DL_L,
+    INDEX_PLL_1_8G_UL_H,
+    INDEX_PLL_1_8G_UL_L,//20
+    INDEX_PLL_2_1G_DL_H,
+    INDEX_PLL_2_1G_DL_L,
+    INDEX_PLL_2_1G_UL_H,
+    INDEX_PLL_2_1G_UL_L,
+    INDEX_PLL_3_5G_DL_H ,//25
+    INDEX_PLL_3_5G_DL_L ,
+    INDEX_PLL_3_5G_UL_H ,
+    INDEX_PLL_3_5G_UL_L ,
+    INDEX_PLL_LD_6_BIT  ,
+    INDEX_DET_1_8G_DL_IN_H  ,//30
+    INDEX_DET_1_8G_DL_IN_L  ,
+    INDEX_DET_1_8G_DL_OUT_H ,
+    INDEX_DET_1_8G_DL_OUT_L ,
+    INDEX_DET_1_8G_UL_IN_H  ,
+    INDEX_DET_1_8G_UL_IN_L  ,//35
+    INDEX_DET_1_8G_UL_OUT_H ,
+    INDEX_DET_1_8G_UL_OUT_L ,
+    INDEX_DET_2_1G_DL_IN_H  ,
+    INDEX_DET_2_1G_DL_IN_L  ,
+    INDEX_DET_2_1G_DL_OUT_H ,//40
+    INDEX_DET_2_1G_DL_OUT_L ,
+    INDEX_DET_2_1G_UL_IN_H  ,
+    INDEX_DET_2_1G_UL_IN_L  ,
+    INDEX_DET_2_1G_UL_OUT_H ,
+    INDEX_DET_2_1G_UL_OUT_L ,//45
+    INDEX_DET_3_5G_DL_IN_H  ,
+    INDEX_DET_3_5G_DL_IN_L  ,
+    INDEX_DET_3_5G_DL_OUT_L ,
+    INDEX_DET_3_5G_DL_OUT_H ,
+    INDEX_DET_3_5G_UL_IN_H  ,//50
+    INDEX_DET_3_5G_UL_IN_L  ,
+    INDEX_DET_3_5G_UL_OUT_H ,
+    INDEX_DET_3_5G_UL_OUT_L ,
+    INDEX_RFU_TEMP_H    ,
+    INDEX_RFU_TEMP_L    ,//55
+    INDEX__28V_DET_H    ,
+    INDEX__28V_DET_L    ,
+    INDEX_ALARM_AC      ,
+    INDEX_ALARM_DC      ,
+    INDEX_PATH_EN_1_8G_DL   ,//60
+    INDEX_PATH_EN_1_8G_UL   ,
+    INDEX_PATH_EN_2_1G_DL   ,
+    INDEX_PATH_EN_2_1G_UL   ,
+    INDEX_PATH_EN_3_5G_L,
+    INDEX_PATH_EN_3_5G_H,//65
+    INDEX_PATH_EN_3_5G_DL   ,
+    INDEX_PATH_EN_3_5G_UL   ,
+    INDEX_PLL_ON_OFF_3_5G_H ,
+    INDEX_PLL_ON_OFF_3_5G_L ,//69
+    INDEX_T_SYNC_DL,
+    INDEX__T_SYNC_DL,
+    INDEX_T_SYNC_UL,
+    INDEX__T_SYNC_UL,    
+}Bluecell_Prot_Index;
 
 #endif /* ZIG_OPERATE_H_ */

Src/BDA4601.c

@@ -5,33 +5,153 @@
  *      Author: parkyj
  */
 #include "BDA4601.h"
-void BDA4601_atten_ctrl(PE43711_st* type ,double data){
+BDA4601_st BDA4601_1_8G_DL1 = {
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_1_8G_DL1_GPIO_Port,
+    ATT_EN_1_8G_DL1_Pin,
+};
+BDA4601_st BDA4601_1_8G_DL2 = {
+   ATT_CLK_GPIO_Port,
+   ATT_CLK_Pin,
+   ATT_DATA_GPIO_Port,
+   ATT_DATA_Pin,
+   ATT_EN_1_8G_DL2_GPIO_Port,
+   ATT_EN_1_8G_DL2_Pin,
+};
+BDA4601_st BDA4601_1_8G_UL1 = {
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_1_8G_UL1_GPIO_Port,
+    ATT_EN_1_8G_UL1_Pin,
+};
+BDA4601_st BDA4601_1_8G_UL2 = {
+   ATT_CLK_GPIO_Port,
+   ATT_CLK_Pin,
+   ATT_DATA_GPIO_Port,
+   ATT_DATA_Pin,
+   ATT_EN_1_8G_UL2_GPIO_Port,
+   ATT_EN_1_8G_UL2_Pin,
+};
+BDA4601_st BDA4601_1_8G_UL3 = {
+   ATT_CLK_GPIO_Port,
+   ATT_CLK_Pin,
+   ATT_DATA_GPIO_Port,
+   ATT_DATA_Pin,
+   ATT_EN_1_8G_UL1_GPIO_Port,
+   ATT_EN_1_8G_UL1_Pin,
+};    
+BDA4601_st BDA4601_1_8G_UL4 = {
+   ATT_CLK_GPIO_Port,
+   ATT_CLK_Pin,
+   ATT_DATA_GPIO_Port,
+   ATT_DATA_Pin,
+   ATT_EN_1_8G_UL4_GPIO_Port,
+   ATT_EN_1_8G_UL4_Pin,
+};          
+
+BDA4601_st BDA4601_2_1G_DL1= {
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_2_1G_DL1_GPIO_Port,
+    ATT_EN_2_1G_DL1_Pin,
+};           ;
+BDA4601_st BDA4601_2_1G_DL2= {
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_2_1G_DL2_GPIO_Port,
+    ATT_EN_2_1G_DL2_Pin,
+};           
+BDA4601_st BDA4601_2_1G_UL1= {
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_2_1G_UL1_GPIO_Port,
+    ATT_EN_2_1G_UL1_Pin,
+};           
+BDA4601_st BDA4601_2_1G_UL2= {
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_2_1G_UL2_GPIO_Port,
+    ATT_EN_2_1G_UL2_Pin,
+};           
+BDA4601_st BDA4601_2_1G_UL3= {
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_2_1G_UL3_GPIO_Port,
+    ATT_EN_2_1G_UL3_Pin,
+};           
+BDA4601_st BDA4601_2_1G_UL4= {
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_2_1G_UL4_GPIO_Port,
+    ATT_EN_2_1G_UL4_Pin,
+};    
+
+
+
+void BDA4601_Test(void){
+    BDA4601_atten_ctrl(BDA4601_1_8G_DL1,0);           
+    BDA4601_atten_ctrl(BDA4601_1_8G_DL2,0);           
+
+    BDA4601_atten_ctrl(BDA4601_1_8G_UL1,0);           
+    BDA4601_atten_ctrl(BDA4601_1_8G_UL2,0);           
+    BDA4601_atten_ctrl(BDA4601_1_8G_UL3,0);           
+    BDA4601_atten_ctrl(BDA4601_1_8G_UL4,0);           
+
+    BDA4601_atten_ctrl(BDA4601_2_1G_DL1,0);           
+    BDA4601_atten_ctrl(BDA4601_2_1G_DL2,0);           
+
+    BDA4601_atten_ctrl(BDA4601_2_1G_UL1,0);           
+    BDA4601_atten_ctrl(BDA4601_2_1G_UL2,0);
+    BDA4601_atten_ctrl(BDA4601_2_1G_UL3,0);           
+    BDA4601_atten_ctrl(BDA4601_2_1G_UL4,0);               
+}
+
+
+void BDA4601_atten_ctrl(BDA4601_st BDA ,uint8_t data){
     uint8_t i = 0;
     uint8_t temp = 0;
+    printf("BDA4601_atten_ctrl : %x \r\n",data);
     data = 4 * data;
     temp = (uint8_t)data;
-    HAL_GPIO_WritePin(GPIOB,GPIO_PIN_1,GPIO_PIN_RESET);
+    HAL_GPIO_WritePin(BDA.LE_PORT,BDA.LE_PIN,GPIO_PIN_RESET);
     HAL_Delay(1);
     for(i = 0; i < 8; i++){
         if((uint8_t)temp & 0x01){
-           HAL_GPIO_WritePin(GPIOB,GPIO_PIN_15,GPIO_PIN_SET);//DATA
+           HAL_GPIO_WritePin(BDA.SERIAL_IN_PORT,BDA.SERIAL_IN_PIN,GPIO_PIN_SET);//DATA
         }
            else{
-           HAL_GPIO_WritePin(GPIOB,GPIO_PIN_15,GPIO_PIN_RESET);//DATA
+           HAL_GPIO_WritePin(BDA.SERIAL_IN_PORT,BDA.SERIAL_IN_PIN,GPIO_PIN_RESET);//DATA
            }
 
-        HAL_GPIO_WritePin(GPIOB,GPIO_PIN_2,GPIO_PIN_SET);//CLOCK
+        HAL_GPIO_WritePin(BDA.CLK_PORT,BDA.CLK_PIN,GPIO_PIN_SET);//CLOCK
         HAL_Delay(1);
-        HAL_GPIO_WritePin(GPIOB,GPIO_PIN_2,GPIO_PIN_RESET);//CLOCK
+        HAL_GPIO_WritePin(BDA.CLK_PORT,BDA.CLK_PIN,GPIO_PIN_RESET);//CLOCK
         HAL_Delay(1);
         temp >>= 1;
     }
-    HAL_GPIO_WritePin(GPIOB,GPIO_PIN_2,GPIO_PIN_RESET);//CLOCK
-    HAL_GPIO_WritePin(GPIOB,GPIO_PIN_15,GPIO_PIN_RESET);//DATA
+    HAL_GPIO_WritePin(BDA.CLK_PORT,BDA.CLK_PIN,GPIO_PIN_RESET);//CLOCK
+    HAL_GPIO_WritePin(BDA.SERIAL_IN_PORT,GPIO_PIN_15,GPIO_PIN_RESET);//DATA
     HAL_Delay(5);
-    HAL_GPIO_WritePin(GPIOB,GPIO_PIN_1,GPIO_PIN_SET);//LE
+    HAL_GPIO_WritePin(BDA.LE_PORT,BDA.LE_PIN,GPIO_PIN_SET);//LE
     HAL_Delay(1);
-    HAL_GPIO_WritePin(GPIOB,GPIO_PIN_1,GPIO_PIN_RESET);
+    HAL_GPIO_WritePin(BDA.LE_PORT,BDA.LE_PIN,GPIO_PIN_RESET);
 }
 
 

Src/PE43711.c

@@ -5,86 +5,121 @@
  *      Author: parkyj
  */
  #include "PE43711.h"
-#if 0 // PYJ.2019.07.26_BEGIN -- 
+#if 1 // PYJ.2019.07.26_BEGIN -- 
+#define ATTEN_3_5G_Initial_Val 0
+void PE43711_ALL_atten_ctrl(ALL_PE43711_st ATT);
 
-PE43711_st *Atten_1_8Ghz; 
-PE43711_st *Atten_2_1Ghz; 
+void PE43711_atten_ctrl(PE43711_st ATT ,uint8_t data);
+ALL_PE43711_st ALL_ATT_3_5G;
 
- 
+PE43711_st ATT_3_5G_DL ={
+    ATT_CLK_3_5G_GPIO_Port,
+    ATT_CLK_3_5G_Pin,
+    ATT_DATA_3_5G_DL_GPIO_Port,
+    ATT_DATA_3_5G_DL_Pin,
+    ATT_EN_3_5G_GPIO_Port,
+    ATT_EN_3_5G_Pin,
+}; 
+PE43711_st ATT_3_5G_UL ={
+    ATT_CLK_3_5G_GPIO_Port,
+    ATT_CLK_3_5G_Pin,
+    ATT_DATA_3_5G_UL_GPIO_Port,
+    ATT_DATA_3_5G_UL_Pin,
+    ATT_EN_3_5G_GPIO_Port,
+    ATT_EN_3_5G_Pin,
+}; 
+PE43711_st ATT_3_5G_COM1={
+    ATT_CLK_3_5G_GPIO_Port,
+    ATT_CLK_3_5G_Pin,
+    ATT_DATA_3_5G_COM1_GPIO_Port,
+    ATT_DATA_3_5G_COM1_Pin,
+    ATT_EN_3_5G_GPIO_Port,
+    ATT_EN_3_5G_Pin,
+}; 
+PE43711_st ATT_3_5G_COM2={
+    ATT_CLK_3_5G_GPIO_Port,
+    ATT_CLK_3_5G_Pin,
+    ATT_DATA_3_5G_COM2_GPIO_Port,
+    ATT_DATA_3_5G_COM2_Pin,
+    ATT_EN_3_5G_GPIO_Port,
+    ATT_EN_3_5G_Pin,
+}; 
+PE43711_st ATT_3_5G_COM3={
+    ATT_CLK_3_5G_GPIO_Port,
+    ATT_CLK_3_5G_Pin,
+    ATT_DATA_3_5G_COM3_GPIO_Port,
+    ATT_DATA_3_5G_COM3_Pin,
+    ATT_EN_3_5G_GPIO_Port,
+    ATT_EN_3_5G_Pin,
+}; 
 void PE43711_PinInit(void){
-    Atten_1_8Ghz->ATT_EN_1_8G_DL1_PIN = GPIO_PIN_1;
-    Atten_1_8Ghz->ATT_EN_1_8G_DL1_PORT = GPIOB;
-    
-    Atten_1_8Ghz->ATT_EN_1_8G_DL2_PIN = GPIO_PIN_1;
-    Atten_1_8Ghz->ATT_EN_1_8G_DL2_PORT = GPIOB;
-    
-    Atten_1_8Ghz->ATT_EN_1_8G_UL1_PIN = GPIO_PIN_1;
-    Atten_1_8Ghz->ATT_EN_1_8G_UL1_PORT = GPIOB;
-    
-    Atten_1_8Ghz->ATT_EN_1_8G_DL1_PIN = GPIO_PIN_1;
-    Atten_1_8Ghz->ATT_EN_1_8G_DL1_PORT = GPIOB;
-    
-    Atten_1_8Ghz->ATT_EN_1_8G_UL2_PIN = GPIO_PIN_1;
-    Atten_1_8Ghz->ATT_EN_1_8G_UL2_PORT = GPIOB;
-
-    Atten_1_8Ghz->ATT_EN_1_8G_UL3_PIN = GPIO_PIN_1;
-    Atten_1_8Ghz->ATT_EN_1_8G_UL3_PORT = GPIOB;
-    
-    Atten_1_8Ghz->ATT_EN_1_8G_UL4_PIN = GPIO_PIN_1;
-    Atten_1_8Ghz->ATT_EN_1_8G_UL4_PORT = GPIOB;
-
-
-    Atten_2_1Ghz->ATT_EN_1_8G_DL1_PIN = GPIO_PIN_1;
-    Atten_2_1Ghz->ATT_EN_1_8G_DL1_PORT = GPIOB;
-
-    Atten_2_1Ghz->ATT_EN_1_8G_DL2_PIN = GPIO_PIN_1;
-    Atten_2_1Ghz->ATT_EN_1_8G_DL2_PORT = GPIOB;
-
-    Atten_2_1Ghz->ATT_EN_1_8G_UL1_PIN = GPIO_PIN_1;
-    Atten_2_1Ghz->ATT_EN_1_8G_UL1_PORT = GPIOB;
-
-    Atten_2_1Ghz->ATT_EN_1_8G_DL1_PIN = GPIO_PIN_1;
-    Atten_2_1Ghz->ATT_EN_1_8G_DL1_PORT = GPIOB;
-
-    Atten_2_1Ghz->ATT_EN_1_8G_UL2_PIN = GPIO_PIN_1;
-    Atten_2_1Ghz->ATT_EN_1_8G_UL2_PORT = GPIOB;
-
-    Atten_2_1Ghz->ATT_EN_1_8G_UL3_PIN = GPIO_PIN_1;
-    Atten_2_1Ghz->ATT_EN_1_8G_UL3_PORT = GPIOB;
-
-    Atten_2_1Ghz->ATT_EN_1_8G_UL4_PIN = GPIO_PIN_1;
-    Atten_2_1Ghz->ATT_EN_1_8G_UL4_PORT = GPIOB;
-    
+    ALL_ATT_3_5G.ATT0 = ATT_3_5G_DL;
+    ALL_ATT_3_5G.ATT1 = ATT_3_5G_UL;
+    ALL_ATT_3_5G.ATT2 = ATT_3_5G_COM1;
+    ALL_ATT_3_5G.ATT3 = ATT_3_5G_COM2;
+    ALL_ATT_3_5G.ATT4 = ATT_3_5G_COM3;
+    ALL_ATT_3_5G.data0 = ATTEN_3_5G_Initial_Val;    
+    ALL_ATT_3_5G.data1 = ATTEN_3_5G_Initial_Val;
+    ALL_ATT_3_5G.data2 = ATTEN_3_5G_Initial_Val;
+    ALL_ATT_3_5G.data3 = ATTEN_3_5G_Initial_Val;
+    ALL_ATT_3_5G.data4 = ATTEN_3_5G_Initial_Val;    
+    PE43711_ALL_atten_ctrl(ALL_ATT_3_5G);
 }
 #endif // PYJ.2019.07.26_END -- 
+void Bit_Compare(PE43711_st ATT,uint8_t data,uint8_t Shift_Index){
+    if(data & (0x01 << Shift_Index)){
+        HAL_GPIO_WritePin(ATT.DATA_PORT,ATT.DATA_PIN,GPIO_PIN_SET);//DATA
+    }
+    else{
+        HAL_GPIO_WritePin(ATT.DATA_PORT,ATT.DATA_PIN,GPIO_PIN_RESET);//DATA
+    }
+}
+void PE43711_ALL_atten_ctrl(ALL_PE43711_st ATT){
+    HAL_GPIO_WritePin(ATT.ATT0.LE_PORT,ATT.ATT0.LE_PIN,GPIO_PIN_RESET);
+    Pol_Delay_us(10);
+    for(uint8_t i = 0; i < 8; i++){
+        Bit_Compare(ATT.ATT0,ATT.data0,i);
+        Bit_Compare(ATT.ATT1,ATT.data1,i);
+        Bit_Compare(ATT.ATT2,ATT.data2,i);
+        Bit_Compare(ATT.ATT3,ATT.data3,i);
+        Bit_Compare(ATT.ATT4,ATT.data4,i);
+		HAL_GPIO_WritePin(ATT.ATT0.CLK_PORT,ATT.ATT0.CLK_PIN,GPIO_PIN_SET);//CLOCK
+		Pol_Delay_us(10);
+		HAL_GPIO_WritePin(ATT.ATT0.CLK_PORT,ATT.ATT0.CLK_PIN,GPIO_PIN_RESET);//CLOCK
+    }
+    HAL_GPIO_WritePin(GPIOB,GPIO_PIN_15,GPIO_PIN_RESET);//DATA
+    HAL_GPIO_WritePin(ATT.ATT0.LE_PORT,ATT.ATT0.LE_PIN,GPIO_PIN_SET);//LE
+    Pol_Delay_us(10);
+    HAL_GPIO_WritePin(ATT.ATT0.LE_PORT,ATT.ATT0.LE_PIN,GPIO_PIN_RESET);
+}
 
-void PE43711_atten_ctrl(PE43711_st* Atten_xGhz ,double data){
+void PE43711_atten_ctrl(PE43711_st ATT ,uint8_t data){
     uint8_t i = 0;
     uint8_t temp = 0;
     data = 4 * data;
     temp = (uint8_t)data;
     
-    HAL_GPIO_WritePin(GPIOB,GPIO_PIN_1,GPIO_PIN_RESET);
-    HAL_Delay(1);
+    HAL_GPIO_WritePin(ATT.LE_PORT,ATT.LE_PIN,GPIO_PIN_RESET);
+    Pol_Delay_us(10);
     for(i = 0; i < 8; i++){
         if((uint8_t)temp & 0x01){
-           HAL_GPIO_WritePin(GPIOB,GPIO_PIN_15,GPIO_PIN_SET);//DATA
+           HAL_GPIO_WritePin(ATT.DATA_PORT,ATT.DATA_PIN,GPIO_PIN_SET);//DATA
         }
            else{
-           HAL_GPIO_WritePin(GPIOB,GPIO_PIN_15,GPIO_PIN_RESET);//DATA
+           HAL_GPIO_WritePin(ATT.DATA_PORT,ATT.DATA_PIN,GPIO_PIN_RESET);//DATA
            }
 
-		HAL_GPIO_WritePin(GPIOB,GPIO_PIN_2,GPIO_PIN_SET);//CLOCK
-		HAL_Delay(1);
-		HAL_GPIO_WritePin(GPIOB,GPIO_PIN_2,GPIO_PIN_RESET);//CLOCK
-		HAL_Delay(1);
+		HAL_GPIO_WritePin(ATT.CLK_PORT,ATT.CLK_PIN,GPIO_PIN_SET);//CLOCK
+		Pol_Delay_us(10);
+		HAL_GPIO_WritePin(ATT.CLK_PORT,ATT.CLK_PIN,GPIO_PIN_RESET);//CLOCK
+		Pol_Delay_us(10);
 		temp >>= 1;
     }
     
-	HAL_GPIO_WritePin(GPIOB,GPIO_PIN_2,GPIO_PIN_RESET);//CLOCK
-    HAL_GPIO_WritePin(GPIOB,GPIO_PIN_15,GPIO_PIN_RESET);//DATA
+	HAL_GPIO_WritePin(ATT.CLK_PORT,ATT.CLK_PIN,GPIO_PIN_RESET);//CLOCK
+    HAL_GPIO_WritePin(ATT.DATA_PORT,ATT.DATA_PIN,GPIO_PIN_RESET);//DATA
     HAL_Delay(5);
-    HAL_GPIO_WritePin(GPIOB,GPIO_PIN_1,GPIO_PIN_SET);//LE
-    HAL_Delay(1);
-    HAL_GPIO_WritePin(GPIOB,GPIO_PIN_1,GPIO_PIN_RESET);
+    HAL_GPIO_WritePin(ATT.LE_PORT,ATT.LE_PIN,GPIO_PIN_SET);//LE
+    Pol_Delay_us(10);
+    HAL_GPIO_WritePin(ATT.LE_PORT,ATT.LE_PIN,GPIO_PIN_RESET);
 }

Src/adf4153.c

@@ -78,7 +78,7 @@ uint32_t N_Divider_Reg_Create(uint16_t _FRAC,uint16_t _INT,uint8_t _FASTLOCK){
     uint32_t shift_bit = 0x01;
     uint8_t control_bit = 0;
     uint8_t i = 0;
-    printf("FRAC : %d INT : %d \r\n",_FRAC,_INT);
+    printf("FRAC : %d INT : %d \r\n",(int)_FRAC,_INT);
     for(i = 0; i < 2; i++){
         if(control_bit & 0x01)
             ret += shift_bit << i;
@@ -142,16 +142,17 @@ uint32_t R_Divider_Reg_Create(uint16_t _MOD,uint8_t _RCOUNTER,uint8_t _PRESCALER
     return ret;
 }
 
-void ADF4153_Freq_Calc(unsigned long long Freq,unsigned long long REFin,uint8_t R_Counter,uint32_t chspacing){
+ADF4153_R_N_Reg_st ADF4153_Freq_Calc(unsigned long long Freq,unsigned long long REFin,uint8_t R_Counter,uint32_t chspacing){
     adf4153_st temp_adf4153;
     double temp = 0;
+    ADF4153_R_N_Reg_st temp_reg;
     temp_adf4153.PFD_Value  =  REFin / (R_Counter * 1000);
     temp_adf4153.MOD_Value  =  (temp_adf4153.PFD_Value / chspacing) * 1000;
     temp_adf4153.N_Value    =  N_Reg_Value_Calc(((double)(Freq / 1000) /  (double)(temp_adf4153.PFD_Value / 1000)));
     temp_adf4153.INT_Value  =   temp_adf4153.N_Value ;
-//    printf("\r\ntemp_adf4153.N_Value : %f  temp_adf4153.INT_Value : %f  temp_adf4153.MOD_Value : %f \r\n",temp_adf4153.N_Value,(double)temp_adf4153.INT_Value,(double)temp_adf4153.MOD_Value);
+    printf("\r\ntemp_adf4153.N_Value : %f  temp_adf4153.INT_Value : %f  temp_adf4153.MOD_Value : %f \r\n",temp_adf4153.N_Value,(double)temp_adf4153.INT_Value,(double)temp_adf4153.MOD_Value);
     temp = temp_adf4153.N_Value - (double)temp_adf4153.INT_Value;
-//    printf("\r\n temp_adf4153.N_Value - (double)temp_adf4153.INT_Value) : %f  temp * (double)temp_adf4153.MOD_Value : %f \r\n",temp,temp * (double)temp_adf4153.MOD_Value);
+    printf("\r\n temp_adf4153.N_Value - (double)temp_adf4153.INT_Value) : %f  temp * (double)temp_adf4153.MOD_Value : %f \r\n",temp,temp * (double)temp_adf4153.MOD_Value);
     temp_adf4153.FRAC_Value =  (float)temp * temp_adf4153.MOD_Value;
    
     printf("\r\ntemp_adf4153.N_Value : %x   : %f ",temp_adf4153.N_Value,((double)(Freq / 1000) /  (double)(temp_adf4153.PFD_Value / 1000)) / 1000);
@@ -190,20 +191,23 @@ void ADF4153_Freq_Calc(unsigned long long Freq,unsigned long long REFin,uint8_t
     printf("\r\n");    
 
     printf("R0: %x  R1: %x \r\n",N_Divider_Reg_Create(temp_adf4153.FRAC_Value,temp_adf4153.INT_Value,0),R_Divider_Reg_Create(temp_adf4153.MOD_Value,R_Counter,1,0,2,0));   
-        
+    temp_reg.N_reg = N_Divider_Reg_Create(temp_adf4153.FRAC_Value,temp_adf4153.INT_Value,0);
+    temp_reg.R_reg = R_Divider_Reg_Create(temp_adf4153.MOD_Value,R_Counter,1,0,2,0);
+
+    return temp_reg;
 //    R_Divider_Reg_Create(temp_adf4153.MOD_Value,R_Counter,1,0,1,0); //prescaler 1 : 8/9 0: 4/5
 }
 
-void ADF_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2,uint32_t R3){
+void ADF4153_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2,uint32_t R3){
     R3  = R3  & 0x0007FF;
     R2 = R2 & 0x00FFFF;
     R1 = R1 & 0xFFFFFF;
     R0 = R0 & 0xFFFFFF;
-    
+//    ADF4153_Freq_Calc(3461500000,40000000,2,5000);
     HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
     HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
     HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
-    printf("YJ : R3 : %x ",R3);
+    printf("YJ :R0: %x  R1:  %x   R2 : %x R3 : %x ",R0,R1,R2,R3);
     printf("\r\n");
     /*   R3 Ctrl    */
     for(int i =0; i < 11; i++){
@@ -215,12 +219,15 @@ void ADF_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2,uint
             HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
             printf("0");
         }
+        Pol_Delay_us(10);
         HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
+        Pol_Delay_us(10);
         HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
         R3 = (R3 << 1);
     }
     printf("\r\n");
     HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
+      Pol_Delay_us(10);
     HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
     
     /*   R2 Ctrl    */
@@ -233,12 +240,16 @@ void ADF_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2,uint
              HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
              printf("0");
          }
+         Pol_Delay_us(10);
          HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
+         Pol_Delay_us(10);
          HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
+
          R2 = ((R2 << 1) & 0x00FFFF);
      }
      printf("\r\n");
      HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
+      Pol_Delay_us(10);
      HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
     
      /*   R1 Ctrl    */
@@ -251,12 +262,16 @@ void ADF_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2,uint
             HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
             printf("0");
         }
+        Pol_Delay_us(10);
         HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
+        Pol_Delay_us(10);
         HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
+
         R1 = ((R1 << 1) & 0xFFFFFF);
     }
     printf("\r\n");
     HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
+      Pol_Delay_us(10);
     HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
 
 
@@ -271,12 +286,16 @@ void ADF_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2,uint
             HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
             printf("0");
         }
+        Pol_Delay_us(10);
         HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
+        Pol_Delay_us(10);
         HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
+
         R0 = ((R0 << 1) & 0xFFFFFF);
     }
     printf("\r\n");
     HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
+    Pol_Delay_us(10);
     HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
 
 }

Src/includes.c

@@ -0,0 +1,87 @@
+/*
+ * includes.c
+ *
+ *  Created on: 2019. 7. 28.
+ *      Author: parkyj
+ */
+#include "includes.h"
+
+
+void Power_ON_OFF_Ctrl(uint8_t type,uint8_t cmd){
+    switch(type){
+        case INDEX_PATH_EN_1_8G_DL  : 
+            if(cmd)
+                HAL_GPIO_WritePin(PATH_EN_1_8G_DL_GPIO_Port,PATH_EN_1_8G_DL_Pin, GPIO_PIN_SET);
+            else
+                HAL_GPIO_WritePin(PATH_EN_1_8G_DL_GPIO_Port,PATH_EN_1_8G_DL_Pin, GPIO_PIN_RESET);
+            break; 
+        case INDEX_PATH_EN_1_8G_UL  : 
+            if(cmd)
+                HAL_GPIO_WritePin(PATH_EN_1_8G_UL_GPIO_Port,PATH_EN_1_8G_UL_Pin, GPIO_PIN_SET);
+            else
+                HAL_GPIO_WritePin(PATH_EN_1_8G_UL_GPIO_Port,PATH_EN_1_8G_UL_Pin, GPIO_PIN_RESET);
+                
+            break;
+        case INDEX_PATH_EN_2_1G_DL  : 
+            if(cmd)
+                HAL_GPIO_WritePin(PATH_EN_2_1G_DL_GPIO_Port,PATH_EN_2_1G_DL_Pin, GPIO_PIN_SET);
+            else
+                HAL_GPIO_WritePin(PATH_EN_2_1G_DL_GPIO_Port,PATH_EN_2_1G_DL_Pin, GPIO_PIN_RESET);                
+            break;
+        case INDEX_PATH_EN_2_1G_UL  : 
+            if(cmd)
+                HAL_GPIO_WritePin(PATH_EN_2_1G_UL_GPIO_Port,PATH_EN_2_1G_UL_Pin, GPIO_PIN_SET);
+            else
+                HAL_GPIO_WritePin(PATH_EN_2_1G_UL_GPIO_Port,PATH_EN_2_1G_UL_Pin, GPIO_PIN_RESET);                
+            break;
+        case INDEX_PATH_EN_3_5G_L   : 
+            if(cmd)
+                HAL_GPIO_WritePin(PATH_EN_3_5G_L_GPIO_Port,PATH_EN_3_5G_L_Pin, GPIO_PIN_SET);
+            else
+                HAL_GPIO_WritePin(PATH_EN_3_5G_L_GPIO_Port,PATH_EN_3_5G_L_Pin, GPIO_PIN_RESET);
+            break;
+        case INDEX_PATH_EN_3_5G_H   : 
+            if(cmd)
+                HAL_GPIO_WritePin(PATH_EN_3_5G_H_GPIO_Port,PATH_EN_3_5G_H_Pin, GPIO_PIN_SET);
+            else
+                HAL_GPIO_WritePin(PATH_EN_3_5G_H_GPIO_Port,PATH_EN_3_5G_H_Pin, GPIO_PIN_RESET);
+            break;
+        case INDEX_PATH_EN_3_5G_DL  : 
+            HAL_GPIO_WritePin(PATH_EN_3_5G_DL_GPIO_Port,PATH_EN_3_5G_DL_Pin, GPIO_PIN_SET);
+
+            break;
+        case INDEX_PATH_EN_3_5G_UL  : 
+            HAL_GPIO_WritePin(PATH_EN_3_5G_UL_GPIO_Port,PATH_EN_3_5G_UL_Pin, GPIO_PIN_SET);
+            break;
+        case INDEX_PLL_ON_OFF_3_5G_L: 
+            HAL_GPIO_WritePin(PLL_ON_OFF_3_5G_L_GPIO_Port,PLL_ON_OFF_3_5G_L_Pin, GPIO_PIN_SET);  
+            break;
+        case INDEX_PLL_ON_OFF_3_5G_H: 
+            HAL_GPIO_WritePin(PLL_ON_OFF_3_5G_H_GPIO_Port,PLL_ON_OFF_3_5G_H_Pin, GPIO_PIN_SET);
+            break;
+        case INDEX_T_SYNC_DL:
+        case INDEX__T_SYNC_UL:
+        case INDEX_T_SYNC_UL:
+        case INDEX__T_SYNC_DL:
+            if(cmd){
+                HAL_GPIO_WritePin(_T_SYNC_UL_GPIO_Port,_T_SYNC_UL_Pin, GPIO_PIN_RESET);
+                HAL_GPIO_WritePin(T_SYNC_UL_GPIO_Port,T_SYNC_UL_Pin, GPIO_PIN_RESET);
+                HAL_GPIO_WritePin(_T_SYNC_DL_GPIO_Port,_T_SYNC_DL_Pin, GPIO_PIN_SET);
+                HAL_GPIO_WritePin(T_SYNC_DL_GPIO_Port,T_SYNC_DL_Pin, GPIO_PIN_SET);                
+            }
+            else{
+                HAL_GPIO_WritePin(_T_SYNC_UL_GPIO_Port,_T_SYNC_UL_Pin, GPIO_PIN_SET);
+                HAL_GPIO_WritePin(T_SYNC_UL_GPIO_Port,T_SYNC_UL_Pin, GPIO_PIN_SET);
+                HAL_GPIO_WritePin(_T_SYNC_DL_GPIO_Port,_T_SYNC_DL_Pin, GPIO_PIN_RESET);
+                HAL_GPIO_WritePin(T_SYNC_DL_GPIO_Port,T_SYNC_DL_Pin, GPIO_PIN_RESET);                
+            }
+            printf("TDD SYNC OPERATE ; %d\r\n",cmd);
+            break;
+        default :
+        printf("Function : %s LINE : %d   ERROR \r\n",__func__,__LINE__);
+    break;
+
+    }
+
+}
+

Src/main.c

@@ -86,6 +86,7 @@ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
 int _write (int file, uint8_t *ptr, uint16_t len)
 {
     HAL_UART_Transmit(&huart1, ptr, len,10);
+//    HAL_UART_Transmit_IT(&huart1, ptr, len);
     return len;
 }
 void Pol_Delay_us(volatile uint32_t microseconds)
@@ -141,6 +142,7 @@ int main(void)
   setbuf(stdout, NULL);
   printf("UART Start \r\n");
   HAL_UART_Receive_DMA(&huart1, TerminalQueue.Buffer, 1);
+  PE43711_PinInit();
     HAL_GPIO_WritePin(PATH_EN_3_5G_L_GPIO_Port,PATH_EN_3_5G_L_Pin, GPIO_PIN_SET);
     HAL_GPIO_WritePin(PATH_EN_3_5G_H_GPIO_Port,PATH_EN_3_5G_H_Pin, GPIO_PIN_SET);
     HAL_GPIO_WritePin(PATH_EN_3_5G_DL_GPIO_Port,PATH_EN_3_5G_DL_Pin, GPIO_PIN_SET);
@@ -148,14 +150,12 @@ int main(void)
     HAL_GPIO_WritePin(PATH_EN_3_5G_L_GPIO_Port,PATH_EN_3_5G_L_Pin, GPIO_PIN_SET);  
     HAL_GPIO_WritePin(PLL_ON_OFF_3_5G_H_GPIO_Port,PLL_ON_OFF_3_5G_H_Pin, GPIO_PIN_SET);
     HAL_GPIO_WritePin(PLL_ON_OFF_3_5G_L_GPIO_Port,PLL_ON_OFF_3_5G_L_Pin, GPIO_PIN_SET);  
-
     HAL_GPIO_WritePin(PATH_EN_2_1G_DL_GPIO_Port,PATH_EN_2_1G_DL_Pin, GPIO_PIN_SET);
     HAL_GPIO_WritePin(PATH_EN_2_1G_UL_GPIO_Port,PATH_EN_2_1G_UL_Pin, GPIO_PIN_SET);
     HAL_GPIO_WritePin(PATH_EN_1_8G_DL_GPIO_Port,PATH_EN_1_8G_DL_Pin, GPIO_PIN_SET);
     HAL_GPIO_WritePin(PATH_EN_1_8G_UL_GPIO_Port,PATH_EN_1_8G_UL_Pin, GPIO_PIN_SET);
+    HAL_Delay(1);
 
-  HAL_Delay(1);
-#if 0 // PYJ.2019.07.28_BEGIN -- 
   printf("\r\nPLL_EN_3_5G_L_GPIO_Port\r\n");
   PLL_Setting_st Pll_test = {
       PLL_CLK_3_5G_GPIO_Port,
@@ -165,9 +165,12 @@ int main(void)
     PLL_EN_3_5G_L_GPIO_Port,    
     PLL_EN_3_5G_L_Pin,
   };
-  ADF_Module_Ctrl(Pll_test,0x2B44B0,0x14BE81,0x0013C2,0x000003);
+//  ADF4153_Module_Ctrl(Pll_test,0x2B44B0,0x14BE81,0x0013C2,0x000003);
+  ADF4153_R_N_Reg_st temp_reg;
+  temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
+  ADF4153_Module_Ctrl(Pll_test,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);      
+
   HAL_Delay(1);
-#endif // PYJ.2019.07.28_END -- 
     printf("\r\nPLL_EN_3_5G_H_GPIO_Port\r\n");
   PLL_Setting_st Pll_test2 = {
       PLL_CLK_3_5G_GPIO_Port,
@@ -177,9 +180,10 @@ int main(void)
         PLL_EN_3_5G_H_GPIO_Port,    
         PLL_EN_3_5G_H_Pin,
   };
-  ADF_Module_Ctrl(Pll_test2,0x313840,0x14BE81,0x13C2,0x3);
+    temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
+    ADF4153_Module_Ctrl(Pll_test2,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);                  
+//  ADF4153_Module_Ctrl(Pll_test2,0x313840,0x14BE81,0x13C2,0x3);
   HAL_Delay(1);
-#if 0 // PYJ.2019.07.28_BEGIN -- 
   printf("\r\nPLL_EN_2_1G_UL_GPIO_Port\r\n");
 
   PLL_Setting_st Pll_test3 = {
@@ -226,7 +230,8 @@ int main(void)
         PLL_EN_1_8G_DL_Pin,
   };
   ADF4113_Module_Ctrl(Pll_test6,0x000410,0x03E801,0x9F8092);
-#endif // PYJ.2019.07.28_END -- 
+  BDA4601_Test();
+
 
 //  ADF_Module_Ctrl(Pll_test,0x324000,0x144051,0x0017c2,0x0003c7);
 

Src/pll_4113.c

@@ -5,6 +5,7 @@
   Description:   This file contains the interface to the ADF4113 frequency synthesizer.
 **************************************************************************************************/
 #include "pll_4113.h"
+void ADF4113_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2);
 
 uint32_t N_Counter_Latch_Create(uint16_t _ACOUNTER,uint16_t _BCOUNTER,uint8_t _CPGAIN);
 
@@ -22,6 +23,40 @@ uint32_t N_Counter_Latch_Create(uint16_t _ACOUNTER,uint16_t _BCOUNTER,uint8_t _C
 #define ADF4113_CH_STEP          50000
 #define HAL_SYN_INVALID_PRESCALE  0x04
 #define ADF4113_REF_FREQ_MHZ    13000000
+PLL_Setting_st ADF4113_1_8G_DL = {
+    PLL_CLK_GPIO_Port,
+    PLL_CLK_Pin,
+    PLL_DATA_GPIO_Port,
+    PLL_DATA_Pin,
+    PLL_EN_1_8G_DL_GPIO_Port,    
+    PLL_EN_1_8G_DL_Pin,
+};
+PLL_Setting_st ADF4113_1_8G_UL = {
+    PLL_CLK_GPIO_Port,
+    PLL_CLK_Pin,
+    PLL_DATA_GPIO_Port,
+    PLL_DATA_Pin,
+    PLL_EN_1_8G_UL_GPIO_Port,    
+    PLL_EN_1_8G_UL_Pin,
+};
+PLL_Setting_st ADF4113_2_1G_DL = {
+    PLL_CLK_GPIO_Port,
+    PLL_CLK_Pin,
+    PLL_DATA_GPIO_Port,
+    PLL_DATA_Pin,
+    PLL_EN_2_1G_DL_GPIO_Port,    
+    PLL_EN_2_1G_DL_Pin,
+};
+PLL_Setting_st ADF4113_2_1G_UL = {
+    PLL_CLK_GPIO_Port,
+    PLL_CLK_Pin,
+    PLL_DATA_GPIO_Port,
+    PLL_DATA_Pin,
+    PLL_EN_2_1G_UL_GPIO_Port,    
+    PLL_EN_2_1G_UL_Pin,
+};
+
+
 
 // Error Code
 typedef struct{
@@ -30,6 +65,7 @@ typedef struct{
     uint16_t A;   
     uint16_t N;       
 }Adf4113_st;
+
 uint8_t halSynSetFreq(uint32_t rf_Freq)
 {
     uint32_t  R, B;
@@ -56,7 +92,7 @@ uint8_t halSynSetFreq(uint32_t rf_Freq)
     P = 32;
     B = N_val / P;
     A = N_val -(B * P);
-    printf("B : %d , A  : %d    N_VAL  : %d \r\n",B,A,N_val);
+    printf("FREQ:%f Mhz  B : %d , A  : %d    N_VAL  : %d \r\n",(float)(rf_Freq/1000000),B,A,N_val);
     printf("YJ 4113 : %x \r\n",N_Counter_Latch_Create(A,B,0));
 }
 uint32_t N_Counter_Latch_Create(uint16_t _ACOUNTER,uint16_t _BCOUNTER,uint8_t _CPGAIN){
@@ -96,7 +132,6 @@ uint32_t N_Counter_Latch_Create(uint16_t _ACOUNTER,uint16_t _BCOUNTER,uint8_t _C
     printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);
     return ret;
 }
-
 void ADF4113_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2){
     R2 = R2 & 0xFFFFFF;
     R1 = R1 & 0xFFFFFF;

Src/zig_operate.c

@@ -179,14 +179,8 @@ ATTEN_Setting_st Atten_2_1Ghz_UL4 ={
     PATH_EN_2_1G_UL_GPIO_Port,
     PATH_EN_2_1G_UL_Pin,    
 };
-typedef enum {
-    TYPE_BLUECELL_RESET = 0,
-    TYPE_BLUECELL_SET   = 1,
-    TYPE_BLUECELL_GET   = 2,
-}Bluecell_Prot_t;
-
-
 
+uint8_t Prev_data[INDEX__T_SYNC_UL + 1];
 bool RF_Data_Check(uint8_t* data_buf){
     bool ret = false;
     bool crcret = STH30_CheckCrc(&data_buf[Type], data_buf[Length], data_buf[data_buf[Crcindex]]);
@@ -204,12 +198,302 @@ bool RF_Data_Check(uint8_t* data_buf){
     return ret;
 
 }
+PLL_Setting_st Pll_3_5_H = {
+     PLL_CLK_3_5G_GPIO_Port,
+     PLL_CLK_3_5G_Pin,
+     PLL_DATA_3_5G_GPIO_Port,
+     PLL_DATA_3_5G_Pin,
+   PLL_EN_3_5G_L_GPIO_Port,    
+   PLL_EN_3_5G_L_Pin,
+ };
+ PLL_Setting_st Pll_3_5_L = {
+     PLL_CLK_3_5G_GPIO_Port,
+     PLL_CLK_3_5G_Pin,
+     PLL_DATA_3_5G_GPIO_Port,
+     PLL_DATA_3_5G_Pin,
+       PLL_EN_3_5G_H_GPIO_Port,    
+       PLL_EN_3_5G_H_Pin,
+ };
+
+void RF_Operate(uint8_t* data_buf){
+    uint16_t temp_val = 0;
+
+    if(Prev_data[INDEX_ATT_1_8G_DL1] != data_buf[INDEX_ATT_1_8G_DL1]){
+        
+        printf("\r\nLINE : %d  \r\n",__LINE__);    
+        BDA4601_atten_ctrl(BDA4601_1_8G_DL1,(data_buf[INDEX_ATT_1_8G_DL1]));
+        Prev_data[INDEX_ATT_1_8G_DL1] = data_buf[INDEX_ATT_1_8G_DL1];
+    }
+    if(Prev_data[INDEX_ATT_1_8G_DL2] != data_buf[INDEX_ATT_1_8G_DL2]){
+        printf("\r\nLINE : %d  \r\n",__LINE__);    
+        BDA4601_atten_ctrl(BDA4601_1_8G_DL2,(data_buf[INDEX_ATT_1_8G_DL2]));
+        Prev_data[INDEX_ATT_1_8G_DL2] = data_buf[INDEX_ATT_1_8G_DL2];
+    }
+    if(Prev_data[INDEX_ATT_1_8G_UL1] != data_buf[INDEX_ATT_1_8G_UL1]){
+        printf("\r\nLINE : %d  \r\n",__LINE__);    
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL1,(data_buf[INDEX_ATT_1_8G_UL1]));
+        Prev_data[INDEX_ATT_1_8G_UL1] = data_buf[INDEX_ATT_1_8G_UL1];
+    }
+    if(Prev_data[INDEX_ATT_1_8G_UL2] != data_buf[INDEX_ATT_1_8G_UL2]){
+        printf("\r\nLINE : %d  \r\n",__LINE__);    
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL2,(data_buf[INDEX_ATT_1_8G_UL2]));
+        Prev_data[INDEX_ATT_1_8G_UL2] = data_buf[INDEX_ATT_1_8G_UL2];
+
+    }
+    if(Prev_data[INDEX_ATT_1_8G_UL3] != data_buf[INDEX_ATT_1_8G_UL3]){
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL3,(data_buf[INDEX_ATT_1_8G_UL3]));
+        Prev_data[INDEX_ATT_1_8G_UL3] = data_buf[INDEX_ATT_1_8G_UL3];
+
+    }
+    if(Prev_data[INDEX_ATT_1_8G_UL4] != data_buf[INDEX_ATT_1_8G_UL4]){
+        printf("\r\nLINE : %d  \r\n",__LINE__);    
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL4,(data_buf[INDEX_ATT_1_8G_UL4]));
+        Prev_data[INDEX_ATT_1_8G_UL4] = data_buf[INDEX_ATT_1_8G_UL4];
+
+    }
+    if(Prev_data[INDEX_ATT_2_1G_DL1] != data_buf[INDEX_ATT_2_1G_DL1]){
+        printf("\r\nLINE : %d  \r\n",__LINE__);    
+        BDA4601_atten_ctrl(BDA4601_2_1G_DL1,(data_buf[INDEX_ATT_2_1G_DL1]));
+        Prev_data[INDEX_ATT_2_1G_DL1] = data_buf[INDEX_ATT_2_1G_DL1];
+
+    }
+    if(Prev_data[INDEX_ATT_2_1G_DL2] != data_buf[INDEX_ATT_2_1G_DL2]){
+        printf("\r\nLINE : %d  \r\n",__LINE__);    
+        BDA4601_atten_ctrl(BDA4601_2_1G_DL2,(data_buf[INDEX_ATT_2_1G_DL2]));
+        Prev_data[INDEX_ATT_2_1G_DL2] = data_buf[INDEX_ATT_2_1G_DL2];
+
+    }
+    if(Prev_data[INDEX_ATT_2_1G_UL1] != data_buf[INDEX_ATT_2_1G_UL1]){
+        printf("\r\nLINE : %d  \r\n",__LINE__);    
+        BDA4601_atten_ctrl(BDA4601_2_1G_UL1,(data_buf[INDEX_ATT_2_1G_UL1]));
+        Prev_data[INDEX_ATT_2_1G_UL1] = data_buf[INDEX_ATT_2_1G_UL1];
+
+    }
+    if(Prev_data[INDEX_ATT_2_1G_UL2] != data_buf[INDEX_ATT_2_1G_UL2]){
+        BDA4601_atten_ctrl(BDA4601_2_1G_UL2,(data_buf[INDEX_ATT_2_1G_UL2]));
+        Prev_data[INDEX_ATT_2_1G_UL2] = data_buf[INDEX_ATT_2_1G_UL2];
+
+    }
+    if(Prev_data[INDEX_ATT_2_1G_UL3] != data_buf[INDEX_ATT_2_1G_UL3]){
+        BDA4601_atten_ctrl(BDA4601_2_1G_UL3,(data_buf[INDEX_ATT_2_1G_UL3]));
+        Prev_data[INDEX_ATT_2_1G_UL3] = data_buf[INDEX_ATT_2_1G_UL3];
+
+    }
+    if(Prev_data[INDEX_ATT_2_1G_UL4] != data_buf[INDEX_ATT_2_1G_UL4]){
+        BDA4601_atten_ctrl(BDA4601_2_1G_UL4,(data_buf[INDEX_ATT_2_1G_UL4]));
+        Prev_data[INDEX_ATT_2_1G_UL4] = data_buf[INDEX_ATT_2_1G_UL4];
+    }
+    if(   (Prev_data[INDEX_ATT_3_5G_DL] != data_buf[INDEX_ATT_3_5G_DL])
+        ||(Prev_data[INDEX_ATT_3_5G_UL] != data_buf[INDEX_ATT_3_5G_UL])
+        ||(Prev_data[INDEX_ATT_3_5G_COM1] != data_buf[INDEX_ATT_3_5G_COM1])
+        ||(Prev_data[INDEX_ATT_3_5G_COM2] != data_buf[INDEX_ATT_3_5G_COM2])
+        ||(Prev_data[INDEX_ATT_3_5G_COM3] != data_buf[INDEX_ATT_3_5G_COM3])
+    ){
+        ALL_ATT_3_5G.data0 = Prev_data[INDEX_ATT_3_5G_DL]   = data_buf[INDEX_ATT_3_5G_DL];
+        ALL_ATT_3_5G.data1 = Prev_data[INDEX_ATT_3_5G_UL]   = data_buf[INDEX_ATT_3_5G_UL];
+        ALL_ATT_3_5G.data2 = Prev_data[INDEX_ATT_3_5G_COM1] = data_buf[INDEX_ATT_3_5G_COM1];
+        ALL_ATT_3_5G.data3 = Prev_data[INDEX_ATT_3_5G_COM2] = data_buf[INDEX_ATT_3_5G_COM2];
+        ALL_ATT_3_5G.data4 = Prev_data[INDEX_ATT_3_5G_COM3] = data_buf[INDEX_ATT_3_5G_COM3];
+        printf("YJ : data0  : %x \r\n",ALL_ATT_3_5G.data0);
+        printf("YJ : data1  : %x \r\n",ALL_ATT_3_5G.data1);
+        printf("YJ : data2  : %x \r\n",ALL_ATT_3_5G.data2);
+        printf("YJ : data3  : %x \r\n",ALL_ATT_3_5G.data3);
+        printf("YJ : data4  : %x \r\n",ALL_ATT_3_5G.data4);
+        PE43711_ALL_atten_ctrl(ALL_ATT_3_5G);
+    }
+
+    if((Prev_data[INDEX_PLL_1_8G_DL_H] != data_buf[INDEX_PLL_1_8G_DL_H])
+        && (Prev_data[INDEX_PLL_1_8G_DL_L] != data_buf[INDEX_PLL_1_8G_DL_L])
+    ){
+        temp_val = (data_buf[INDEX_PLL_1_8G_DL_H] << 8) | (data_buf[INDEX_PLL_1_8G_DL_L]);
+//        printf("INDEX_PLL_1_8G_DL_H : %x \r\n",temp_val);
+        ADF4113_Module_Ctrl(ADF4113_1_8G_DL,0x410,halSynSetFreq((temp_val * 1000000) / 10 ),0x9F8092);
+    }
+    if((Prev_data[INDEX_PLL_1_8G_UL_H] != data_buf[INDEX_PLL_1_8G_UL_H])
+        && (Prev_data[INDEX_PLL_1_8G_UL_L] != data_buf[INDEX_PLL_1_8G_UL_L])){
+        temp_val = (data_buf[INDEX_PLL_1_8G_UL_H] << 8) | (data_buf[INDEX_PLL_1_8G_UL_L]);
+        ADF4113_Module_Ctrl(ADF4113_1_8G_UL,0x410,halSynSetFreq((temp_val * 1000000) / 10),0x9F8092);
+    }
+    if((Prev_data[INDEX_PLL_2_1G_DL_H] != data_buf[INDEX_PLL_2_1G_DL_H])
+        && (Prev_data[INDEX_PLL_2_1G_DL_L] != data_buf[INDEX_PLL_2_1G_DL_L])){
+        temp_val = ((data_buf[INDEX_PLL_2_1G_DL_H] << 8) | (data_buf[INDEX_PLL_2_1G_DL_L]));
+        printf("data_buf[INDEX_PLL_2_1G_DL_H]  %x \r\ndata_buf[INDEX_PLL_2_1G_DL_L]  temp_val : %x\r\n ",data_buf[INDEX_PLL_2_1G_DL_H],data_buf[INDEX_PLL_2_1G_DL_L],temp_val);
+        ADF4113_Module_Ctrl(ADF4113_2_1G_DL,0x410,halSynSetFreq((temp_val * 1000000) / 10),0x9F8092);
+    }
+    if((Prev_data[INDEX_PLL_2_1G_UL_H] != data_buf[INDEX_PLL_2_1G_UL_H])
+        && (Prev_data[INDEX_PLL_2_1G_UL_L] != data_buf[INDEX_PLL_2_1G_UL_L])){
+        temp_val = (data_buf[INDEX_PLL_2_1G_UL_H] << 8) | (data_buf[INDEX_PLL_2_1G_UL_L]);
+        ADF4113_Module_Ctrl(ADF4113_2_1G_UL,0x410,halSynSetFreq((temp_val * 1000000) / 10),0x9F8092);
+
+    }
+    if((Prev_data[INDEX_PLL_3_5G_DL_H] != data_buf[INDEX_PLL_3_5G_DL_H])
+        && (Prev_data[INDEX_PLL_3_5G_DL_L] != data_buf[INDEX_PLL_3_5G_DL_L])){
+        temp_val = (data_buf[INDEX_PLL_3_5G_DL_H] << 8) | (data_buf[INDEX_PLL_3_5G_DL_L]);
+        ADF4153_Module_Ctrl(Pll_3_5_L,ADF4153_Freq_Calc(3465500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING),0x14be81,0x13c2,0x3);
+    }
+    if((Prev_data[INDEX_PLL_3_5G_UL_H] != data_buf[INDEX_PLL_3_5G_UL_H])
+        && (Prev_data[INDEX_PLL_3_5G_UL_L] != data_buf[INDEX_PLL_3_5G_UL_L])){
+        temp_val = (data_buf[INDEX_PLL_3_5G_UL_H] << 8) | (data_buf[INDEX_PLL_3_5G_UL_L]);
+        ADF4153_Module_Ctrl(Pll_3_5_H,ADF4153_Freq_Calc(3934500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING),0x14be81,0x13c2,0x3);
+    }
+    if(Prev_data[INDEX_PLL_LD_6_BIT] != data_buf[INDEX_PLL_LD_6_BIT]){
+
+    }
+#if 0 // PYJ.2019.07.28_BEGIN -- 
+    if(Prev_data[INDEX_DET_1_8G_DL_IN_H] != data_buf[INDEX_DET_1_8G_DL_IN_H]){
+
+    }
+    if(Prev_data[INDEX_DET_1_8G_DL_IN_L] != data_buf[INDEX_DET_1_8G_DL_IN_L]){
+
+    }
+    if(Prev_data[INDEX_DET_1_8G_DL_OUT_H] != data_buf[INDEX_DET_1_8G_DL_OUT_H]){
+
+    }
+    if(Prev_data[INDEX_DET_1_8G_DL_OUT_L] != data_buf[INDEX_DET_1_8G_DL_OUT_L]){
+
+    }
+    if(Prev_data[INDEX_DET_1_8G_UL_IN_H] != data_buf[INDEX_DET_1_8G_UL_IN_H]){
+
+    }
+    if(Prev_data[INDEX_DET_1_8G_UL_IN_L] != data_buf[INDEX_DET_1_8G_UL_IN_L]){
+
+    }
+    if(Prev_data[INDEX_DET_1_8G_UL_OUT_H] != data_buf[INDEX_DET_1_8G_UL_OUT_H]){
+
+    }
+    if(Prev_data[INDEX_DET_1_8G_UL_OUT_L] != data_buf[INDEX_DET_1_8G_UL_OUT_L]){
+
+    }
+    if(Prev_data[INDEX_DET_2_1G_DL_IN_H] != data_buf[INDEX_DET_2_1G_DL_IN_H]){
+
+    }
+    if(Prev_data[INDEX_DET_2_1G_DL_IN_L] != data_buf[INDEX_DET_2_1G_DL_IN_L]){
+
+    }
+    if(Prev_data[INDEX_DET_2_1G_DL_OUT_H] != data_buf[INDEX_DET_2_1G_DL_OUT_H]){
+
+    }
+    if(Prev_data[INDEX_DET_2_1G_DL_OUT_L] != data_buf[INDEX_DET_2_1G_DL_OUT_L]){
+
+    }
+    if(Prev_data[INDEX_DET_2_1G_UL_IN_H] != data_buf[INDEX_DET_2_1G_UL_IN_H]){
+
+    }
+    if(Prev_data[INDEX_DET_2_1G_UL_IN_L] != data_buf[INDEX_DET_2_1G_UL_IN_L]){
+
+    }
+
+    if(Prev_data[INDEX_DET_2_1G_UL_OUT_H] != data_buf[INDEX_DET_2_1G_UL_OUT_H]){
+
+    }
+    if(Prev_data[INDEX_DET_2_1G_UL_OUT_L] != data_buf[INDEX_DET_2_1G_UL_OUT_L]){
+
+    }
+    if(Prev_data[INDEX_DET_3_5G_DL_IN_H] != data_buf[INDEX_DET_3_5G_DL_IN_H]){
+
+    }
+    if(Prev_data[INDEX_DET_3_5G_DL_IN_L] != data_buf[INDEX_DET_3_5G_DL_IN_L]){
+
+    }
+    if(Prev_data[INDEX_DET_3_5G_DL_OUT_L] != data_buf[INDEX_DET_3_5G_DL_OUT_L]){
+
+    }
+    if(Prev_data[INDEX_DET_3_5G_DL_OUT_H] != data_buf[INDEX_DET_3_5G_DL_OUT_H]){
+
+    }
+    if(Prev_data[INDEX_DET_3_5G_UL_IN_H] != data_buf[INDEX_DET_3_5G_UL_IN_H]){
+
+    }
+    if(Prev_data[INDEX_DET_3_5G_UL_IN_L] != data_buf[INDEX_DET_3_5G_UL_IN_L]){
+
+    }
+
+    if(Prev_data[INDEX_DET_3_5G_UL_OUT_H] != data_buf[INDEX_DET_3_5G_UL_OUT_H]){
+
+    }
+    if(Prev_data[INDEX_DET_3_5G_UL_OUT_L] != data_buf[INDEX_DET_3_5G_UL_OUT_L]){
+
+    }
+    if(Prev_data[INDEX_RFU_TEMP_H] != data_buf[INDEX_RFU_TEMP_H]){
+
+    }
+    if(Prev_data[INDEX_RFU_TEMP_L] != data_buf[INDEX_RFU_TEMP_L]){
+
+    }
+    if(Prev_data[INDEX__28V_DET_H] != data_buf[INDEX__28V_DET_H]){
+
+    }
+    if(Prev_data[INDEX__28V_DET_L] != data_buf[INDEX__28V_DET_L]){
+
+    }
+#endif // PYJ.2019.07.28_END -- 
+    if(Prev_data[INDEX_ALARM_AC] != data_buf[INDEX_ALARM_AC]){
+
+    }
+    if(Prev_data[INDEX_ALARM_DC] != data_buf[INDEX_ALARM_DC]){
+
+    }
+    if(Prev_data[INDEX_PATH_EN_1_8G_DL] != data_buf[INDEX_PATH_EN_1_8G_DL]){
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_1_8G_DL,data_buf[INDEX_PATH_EN_1_8G_DL]);
+    }
+    if(Prev_data[INDEX_PATH_EN_1_8G_UL] != data_buf[INDEX_PATH_EN_1_8G_UL]){
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_1_8G_UL,data_buf[INDEX_PATH_EN_1_8G_DL]);
+
+    }
+
+    if(Prev_data[INDEX_PATH_EN_2_1G_DL] != data_buf[INDEX_PATH_EN_2_1G_DL]){
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_2_1G_DL,data_buf[INDEX_PATH_EN_1_8G_DL]);
+
+    }
+    if(Prev_data[INDEX_PATH_EN_2_1G_UL] != data_buf[INDEX_PATH_EN_2_1G_UL]){
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_2_1G_UL,data_buf[INDEX_PATH_EN_1_8G_DL]);
+
+    }
+    if(Prev_data[INDEX_PATH_EN_3_5G_L] != data_buf[INDEX_PATH_EN_3_5G_L]){
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_L,data_buf[INDEX_PATH_EN_1_8G_DL]);
+
+    }
+    if(Prev_data[INDEX_PATH_EN_3_5G_H] != data_buf[INDEX_PATH_EN_3_5G_H]){
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_H,data_buf[INDEX_PATH_EN_1_8G_DL]);
+
+    }
+    if(Prev_data[INDEX_PATH_EN_3_5G_DL] != data_buf[INDEX_PATH_EN_3_5G_DL]){
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_DL,data_buf[INDEX_PATH_EN_1_8G_DL]);
+
+    }
+    if(Prev_data[INDEX_PATH_EN_3_5G_UL] != data_buf[INDEX_PATH_EN_3_5G_UL]){
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_UL,data_buf[INDEX_PATH_EN_1_8G_DL]);
+
+    }
+    if(Prev_data[INDEX_PLL_ON_OFF_3_5G_H] != data_buf[INDEX_PLL_ON_OFF_3_5G_H]){
+        Power_ON_OFF_Ctrl(INDEX_PLL_ON_OFF_3_5G_H,data_buf[INDEX_PATH_EN_1_8G_DL]);
+
+    }
+    if(Prev_data[INDEX_PLL_ON_OFF_3_5G_L] != data_buf[INDEX_PLL_ON_OFF_3_5G_L]){
+        Power_ON_OFF_Ctrl(INDEX_PLL_ON_OFF_3_5G_L,data_buf[INDEX_PATH_EN_1_8G_DL]);
+    }
+
+    if(Prev_data[INDEX_T_SYNC_DL] != data_buf[INDEX_T_SYNC_DL]){
+        Prev_data[INDEX_T_SYNC_DL] = data_buf[INDEX_T_SYNC_DL];
+    }
+    if(Prev_data[INDEX__T_SYNC_DL] != data_buf[INDEX__T_SYNC_DL]){
+        Prev_data[INDEX__T_SYNC_DL] = data_buf[INDEX__T_SYNC_DL];
+    }
+    if(Prev_data[INDEX_T_SYNC_UL] != data_buf[INDEX_T_SYNC_UL]){
+        Prev_data[INDEX_T_SYNC_UL] = data_buf[INDEX_T_SYNC_UL];
+    }
+    if(Prev_data[INDEX__T_SYNC_UL] != data_buf[INDEX__T_SYNC_UL]){
+        Prev_data[INDEX__T_SYNC_UL] = data_buf[INDEX__T_SYNC_UL];
+        Power_ON_OFF_Ctrl(INDEX__T_SYNC_UL,data_buf[INDEX__T_SYNC_UL]);
+    }
+}
+
 bool RF_Ctrl_Main(uint8_t* data_buf){
     bool ret = false;
     Bluecell_Prot_t type = data_buf[Type];
     ret = RF_Data_Check(&data_buf[Header]); /* ERROR CHECK */
     if(ret == false)
-        return ret;
+    return ret;
 
     
     switch(type){
@@ -227,10 +511,14 @@ bool RF_Ctrl_Main(uint8_t* data_buf){
     for(uint8_t i =0 ; i < data_buf[Length] - 1; i++)
         printf("%02x ",data_buf[4 + i]);
 #endif
-        ADF4153_Freq_Calc(3461500000,40000000,2,5000);
+        RF_Operate(&data_buf[Header]);
+        
 
-        ADF4153_Freq_Calc(3938000000,40000000,2,5000);
-        halSynSetFreq(1995000000);
+//        ADF4153_Freq_Calc(3465500000,40000000,2,5000);
+//        ADF4153_Freq_Calc(3993450000,40000000,2,5000);
+//        halSynSetFreq(1995000000);
+//        halSynSetFreq(1600000000);
+//        halSynSetFreq(1455000000);        
         break;
     case TYPE_BLUECELL_GET:
         

insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/BDA4601(1127).c

@@ -0,0 +1,37 @@
+/*
+ * BDA4601.c
+ *
+ *  Created on: 2019. 6. 28.
+ *      Author: parkyj
+ */
+#include "BDA4601.h"
+void BDA4601_atten_ctrl(PE43711_st* type ,double data){
+    uint8_t i = 0;
+    uint8_t temp = 0;
+    data = 4 * data;
+    temp = (uint8_t)data;
+    HAL_GPIO_WritePin(GPIOB,GPIO_PIN_1,GPIO_PIN_RESET);
+    HAL_Delay(1);
+    for(i = 0; i < 8; i++){
+        if((uint8_t)temp & 0x01){
+           HAL_GPIO_WritePin(GPIOB,GPIO_PIN_15,GPIO_PIN_SET);//DATA
+        }
+           else{
+           HAL_GPIO_WritePin(GPIOB,GPIO_PIN_15,GPIO_PIN_RESET);//DATA
+           }
+
+        HAL_GPIO_WritePin(GPIOB,GPIO_PIN_2,GPIO_PIN_SET);//CLOCK
+        HAL_Delay(1);
+        HAL_GPIO_WritePin(GPIOB,GPIO_PIN_2,GPIO_PIN_RESET);//CLOCK
+        HAL_Delay(1);
+        temp >>= 1;
+    }
+    HAL_GPIO_WritePin(GPIOB,GPIO_PIN_2,GPIO_PIN_RESET);//CLOCK
+    HAL_GPIO_WritePin(GPIOB,GPIO_PIN_15,GPIO_PIN_RESET);//DATA
+    HAL_Delay(5);
+    HAL_GPIO_WritePin(GPIOB,GPIO_PIN_1,GPIO_PIN_SET);//LE
+    HAL_Delay(1);
+    HAL_GPIO_WritePin(GPIOB,GPIO_PIN_1,GPIO_PIN_RESET);
+}
+
+

insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/BDA4601(2263).h

@@ -0,0 +1,13 @@
+/*
+ * BDA4601.h
+ *
+ *  Created on: 2019. 6. 28.
+ *      Author: parkyj
+ */
+
+#ifndef BDA4601_H_
+#define BDA4601_H_
+#include "main.h"
+//void BDA4601_atten_ctrl(PE43711_st* type ,double data);
+
+#endif /* BDA4601_H_ */

insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/BDA4601(275).c

@@ -0,0 +1,163 @@
+/*
+ * BDA4601.c
+ *
+ *  Created on: 2019. 6. 28.
+ *      Author: parkyj
+ */
+#include "BDA4601.h"
+BDA4601_st BDA4601_1_8G_DL1 = {
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_1_8G_DL1_GPIO_Port,
+    ATT_EN_1_8G_DL1_Pin,
+};
+BDA4601_st BDA4601_1_8G_DL2 = {
+   ATT_CLK_GPIO_Port,
+   ATT_CLK_Pin,
+   ATT_DATA_GPIO_Port,
+   ATT_DATA_Pin,
+   ATT_EN_1_8G_DL2_GPIO_Port,
+   ATT_EN_1_8G_DL2_Pin,
+};
+BDA4601_st BDA4601_1_8G_UL1 = {
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_1_8G_UL1_GPIO_Port,
+    ATT_EN_1_8G_UL1_Pin,
+};
+BDA4601_st BDA4601_1_8G_UL2 = {
+   ATT_CLK_GPIO_Port,
+   ATT_CLK_Pin,
+   ATT_DATA_GPIO_Port,
+   ATT_DATA_Pin,
+   ATT_EN_1_8G_UL2_GPIO_Port,
+   ATT_EN_1_8G_UL2_Pin,
+};
+BDA4601_st BDA4601_1_8G_UL3 = {
+   ATT_CLK_GPIO_Port,
+   ATT_CLK_Pin,
+   ATT_DATA_GPIO_Port,
+   ATT_DATA_Pin,
+   ATT_EN_1_8G_UL1_GPIO_Port,
+   ATT_EN_1_8G_UL1_Pin,
+};    
+BDA4601_st BDA4601_1_8G_UL4 = {
+   ATT_CLK_GPIO_Port,
+   ATT_CLK_Pin,
+   ATT_DATA_GPIO_Port,
+   ATT_DATA_Pin,
+   ATT_EN_1_8G_UL4_GPIO_Port,
+   ATT_EN_1_8G_UL4_Pin,
+};          
+
+
+
+
+
+
+BDA4601_st BDA4601_2_1G_DL1= {
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_2_1G_DL1_GPIO_Port,
+    ATT_EN_2_1G_DL1_Pin,
+};           ;
+BDA4601_st BDA4601_2_1G_DL2= {
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_2_1G_DL2_GPIO_Port,
+    ATT_EN_2_1G_DL2_Pin,
+};           
+BDA4601_st BDA4601_2_1G_UL1= {
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_2_1G_UL1_GPIO_Port,
+    ATT_EN_2_1G_UL1_Pin,
+};           
+BDA4601_st BDA4601_2_1G_UL2= {
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_2_1G_UL2_GPIO_Port,
+    ATT_EN_2_1G_UL2_Pin,
+};           
+BDA4601_st BDA4601_2_1G_UL3= {
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_2_1G_UL3_GPIO_Port,
+    ATT_EN_2_1G_UL3_Pin,
+};           
+BDA4601_st BDA4601_2_1G_UL4= {
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_2_1G_UL4_GPIO_Port,
+    ATT_EN_2_1G_UL4_Pin,
+};    
+
+
+
+void BDA4601_Test(void){
+    BDA4601_atten_ctrl(BDA4601_1_8G_DL1,0);           
+    BDA4601_atten_ctrl(BDA4601_1_8G_DL2,0);           
+
+    BDA4601_atten_ctrl(BDA4601_1_8G_UL1,0);           
+    BDA4601_atten_ctrl(BDA4601_1_8G_UL2,0);           
+    BDA4601_atten_ctrl(BDA4601_1_8G_UL3,0);           
+    BDA4601_atten_ctrl(BDA4601_1_8G_UL4,0);           
+
+    BDA4601_atten_ctrl(BDA4601_2_1G_DL1,0);           
+    BDA4601_atten_ctrl(BDA4601_2_1G_DL2,0);           
+
+    BDA4601_atten_ctrl(BDA4601_2_1G_UL1,0);           
+    BDA4601_atten_ctrl(BDA4601_2_1G_UL2,0);
+    BDA4601_atten_ctrl(BDA4601_2_1G_UL3,0);           
+    BDA4601_atten_ctrl(BDA4601_2_1G_UL4,0);               
+}
+
+
+
+
+void BDA4601_atten_ctrl(BDA4601_st BDA ,double data){
+    uint8_t i = 0;
+    uint8_t temp = 0;
+    data = 4 * data;
+    temp = (uint8_t)data;
+    HAL_GPIO_WritePin(BDA.LE_PORT,BDA.LE_PIN,GPIO_PIN_RESET);
+    HAL_Delay(1);
+    for(i = 0; i < 8; i++){
+        if((uint8_t)temp & 0x01){
+           HAL_GPIO_WritePin(BDA.SERIAL_IN_PORT,BDA.SERIAL_IN_PIN,GPIO_PIN_SET);//DATA
+        }
+           else{
+           HAL_GPIO_WritePin(BDA.SERIAL_IN_PORT,BDA.SERIAL_IN_PIN,GPIO_PIN_RESET);//DATA
+           }
+
+        HAL_GPIO_WritePin(BDA.CLK_PORT,BDA.CLK_PIN,GPIO_PIN_SET);//CLOCK
+        HAL_Delay(1);
+        HAL_GPIO_WritePin(BDA.CLK_PORT,BDA.CLK_PIN,GPIO_PIN_RESET);//CLOCK
+        HAL_Delay(1);
+        temp >>= 1;
+    }
+    HAL_GPIO_WritePin(BDA.CLK_PORT,BDA.CLK_PIN,GPIO_PIN_RESET);//CLOCK
+    HAL_GPIO_WritePin(BDA.SERIAL_IN_PORT,GPIO_PIN_15,GPIO_PIN_RESET);//DATA
+    HAL_Delay(5);
+    HAL_GPIO_WritePin(BDA.LE_PORT,BDA.LE_PIN,GPIO_PIN_SET);//LE
+    HAL_Delay(1);
+    HAL_GPIO_WritePin(BDA.LE_PORT,BDA.LE_PIN,GPIO_PIN_RESET);
+}
+
+

insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/PE43711(1542).h

@@ -0,0 +1,32 @@
+/*
+ * PE43711.h
+ *
+ *  Created on: 2019. 6. 28.
+ *      Author: parkyj
+ */
+
+#ifndef PE43711_H_
+#define PE43711_H_
+#include "main.h"
+ typedef struct{
+    uint16_t ATT_EN_1_8G_DL1_PIN;
+    GPIO_TypeDef *ATT_EN_1_8G_DL1_PORT;
+
+    uint16_t ATT_EN_1_8G_DL2_PIN;
+    GPIO_TypeDef *ATT_EN_1_8G_DL2_PORT;
+
+    uint16_t ATT_EN_1_8G_UL1_PIN;
+    GPIO_TypeDef *ATT_EN_1_8G_UL1_PORT;
+
+    uint16_t ATT_EN_1_8G_UL2_PIN;
+    GPIO_TypeDef *ATT_EN_1_8G_UL2_PORT;
+
+    uint16_t ATT_EN_1_8G_UL3_PIN;
+    GPIO_TypeDef *ATT_EN_1_8G_UL3_PORT;
+
+    uint16_t ATT_EN_1_8G_UL4_PIN;
+    GPIO_TypeDef *ATT_EN_1_8G_UL4_PORT;
+ }PE43711_st;
+
+
+#endif /* PE43711_H_ */

insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/PE43711(2912).c

@@ -0,0 +1,90 @@
+/*
+ * PE43711.c
+ *
+ *  Created on: 2019. 6. 28.
+ *      Author: parkyj
+ */
+ #include "PE43711.h"
+#if 0 // PYJ.2019.07.26_BEGIN -- 
+
+PE43711_st *Atten_1_8Ghz; 
+PE43711_st *Atten_2_1Ghz; 
+
+ 
+void PE43711_PinInit(void){
+    Atten_1_8Ghz->ATT_EN_1_8G_DL1_PIN = GPIO_PIN_1;
+    Atten_1_8Ghz->ATT_EN_1_8G_DL1_PORT = GPIOB;
+    
+    Atten_1_8Ghz->ATT_EN_1_8G_DL2_PIN = GPIO_PIN_1;
+    Atten_1_8Ghz->ATT_EN_1_8G_DL2_PORT = GPIOB;
+    
+    Atten_1_8Ghz->ATT_EN_1_8G_UL1_PIN = GPIO_PIN_1;
+    Atten_1_8Ghz->ATT_EN_1_8G_UL1_PORT = GPIOB;
+    
+    Atten_1_8Ghz->ATT_EN_1_8G_DL1_PIN = GPIO_PIN_1;
+    Atten_1_8Ghz->ATT_EN_1_8G_DL1_PORT = GPIOB;
+    
+    Atten_1_8Ghz->ATT_EN_1_8G_UL2_PIN = GPIO_PIN_1;
+    Atten_1_8Ghz->ATT_EN_1_8G_UL2_PORT = GPIOB;
+
+    Atten_1_8Ghz->ATT_EN_1_8G_UL3_PIN = GPIO_PIN_1;
+    Atten_1_8Ghz->ATT_EN_1_8G_UL3_PORT = GPIOB;
+    
+    Atten_1_8Ghz->ATT_EN_1_8G_UL4_PIN = GPIO_PIN_1;
+    Atten_1_8Ghz->ATT_EN_1_8G_UL4_PORT = GPIOB;
+
+
+    Atten_2_1Ghz->ATT_EN_1_8G_DL1_PIN = GPIO_PIN_1;
+    Atten_2_1Ghz->ATT_EN_1_8G_DL1_PORT = GPIOB;
+
+    Atten_2_1Ghz->ATT_EN_1_8G_DL2_PIN = GPIO_PIN_1;
+    Atten_2_1Ghz->ATT_EN_1_8G_DL2_PORT = GPIOB;
+
+    Atten_2_1Ghz->ATT_EN_1_8G_UL1_PIN = GPIO_PIN_1;
+    Atten_2_1Ghz->ATT_EN_1_8G_UL1_PORT = GPIOB;
+
+    Atten_2_1Ghz->ATT_EN_1_8G_DL1_PIN = GPIO_PIN_1;
+    Atten_2_1Ghz->ATT_EN_1_8G_DL1_PORT = GPIOB;
+
+    Atten_2_1Ghz->ATT_EN_1_8G_UL2_PIN = GPIO_PIN_1;
+    Atten_2_1Ghz->ATT_EN_1_8G_UL2_PORT = GPIOB;
+
+    Atten_2_1Ghz->ATT_EN_1_8G_UL3_PIN = GPIO_PIN_1;
+    Atten_2_1Ghz->ATT_EN_1_8G_UL3_PORT = GPIOB;
+
+    Atten_2_1Ghz->ATT_EN_1_8G_UL4_PIN = GPIO_PIN_1;
+    Atten_2_1Ghz->ATT_EN_1_8G_UL4_PORT = GPIOB;
+    
+}
+#endif // PYJ.2019.07.26_END -- 
+
+void PE43711_atten_ctrl(PE43711_st* Atten_xGhz ,double data){
+    uint8_t i = 0;
+    uint8_t temp = 0;
+    data = 4 * data;
+    temp = (uint8_t)data;
+    
+    HAL_GPIO_WritePin(GPIOB,GPIO_PIN_1,GPIO_PIN_RESET);
+    HAL_Delay(1);
+    for(i = 0; i < 8; i++){
+        if((uint8_t)temp & 0x01){
+           HAL_GPIO_WritePin(GPIOB,GPIO_PIN_15,GPIO_PIN_SET);//DATA
+        }
+           else{
+           HAL_GPIO_WritePin(GPIOB,GPIO_PIN_15,GPIO_PIN_RESET);//DATA
+           }
+
+		HAL_GPIO_WritePin(GPIOB,GPIO_PIN_2,GPIO_PIN_SET);//CLOCK
+		HAL_Delay(1);
+		HAL_GPIO_WritePin(GPIOB,GPIO_PIN_2,GPIO_PIN_RESET);//CLOCK
+		HAL_Delay(1);
+		temp >>= 1;
+    }
+    
+	HAL_GPIO_WritePin(GPIOB,GPIO_PIN_2,GPIO_PIN_RESET);//CLOCK
+    HAL_GPIO_WritePin(GPIOB,GPIO_PIN_15,GPIO_PIN_RESET);//DATA
+    HAL_Delay(5);
+    HAL_GPIO_WritePin(GPIOB,GPIO_PIN_1,GPIO_PIN_SET);//LE
+    HAL_Delay(1);
+    HAL_GPIO_WritePin(GPIOB,GPIO_PIN_1,GPIO_PIN_RESET);
+}

insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/adf4153(5862).c

@@ -0,0 +1,282 @@
+/******************************************************************************
+*   @file   ADF4153.c
+*   @brief  Implementation of ADF4153 Driver for Microblaze processor.
+*   @author Istvan Csomortani (istvan.csomortani@analog.com)
+*
+*******************************************************************************
+* Copyright 2013(c) Analog Devices, Inc.
+*
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*  - Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*  - Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in
+*    the documentation and/or other materials provided with the
+*    distribution.
+*  - Neither the name of Analog Devices, Inc. nor the names of its
+*    contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*  - The use of this software may or may not infringe the patent rights
+*    of one or more patent holders.  This license does not release you
+*    from the requirement that you obtain separate licenses from these
+*    patent holders to use this software.
+*  - Use of the software either in source or binary form, must be run
+*    on or directly connected to an Analog Devices Inc. component.
+*
+* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED
+* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY
+* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+* INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+/*****************************************************************************/
+/****************************** Include Files ********************************/
+/*****************************************************************************/
+#include "adf4153.h"
+typedef struct _adf4153_st{
+    unsigned long long PFD_Value;
+    uint16_t MOD_Value;
+    uint32_t FRAC_Value;
+    uint16_t INT_Value;    
+    double N_Value;
+}adf4153_st;
+
+uint32_t pow2(uint32_t val,int32_t val2){
+    for(uint8_t i = 0; i < val2 - 1; i++){
+        val = val * val;
+    }
+
+    return val;
+}
+
+double round_up( double value, int pos )
+{
+    double temp;
+    temp = value * pow2( 10, pos );  // �썝�븯�뒗 �냼�닔�젏 �옄由ъ닔留뚰겮 10�쓽 �늻�듅�쓣 �븿
+    temp =  (int)(temp + 0.5);          // 0.5瑜� �뜑�븳�썑 踰꾨┝�븯硫� 諛섏삱由쇱씠 �맖
+    temp *= pow2( 10, -pos );           // �떎�떆 �썝�옒 �냼�닔�젏 �옄由ъ닔濡�
+
+    return temp;
+}
+
+
+double N_Reg_Value_Calc(double val){
+    return  val / 1000;
+}
+uint32_t N_Divider_Reg_Create(uint16_t _FRAC,uint16_t _INT,uint8_t _FASTLOCK){
+    uint32_t ret = 0;
+    uint32_t shift_bit = 0x01;
+    uint8_t control_bit = 0;
+    uint8_t i = 0;
+    printf("FRAC : %d INT : %d \r\n",_FRAC,_INT);
+    for(i = 0; i < 2; i++){
+        if(control_bit & 0x01)
+            ret += shift_bit << i;
+        control_bit = control_bit >> 1;
+    }
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);
+    for(i = 2; i < 14; i++){
+        if(_FRAC & 0x01)
+            ret += shift_bit << i;
+        _FRAC = _FRAC >> 1;
+    }
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);    
+    for(i = 14; i < 22; i++){
+        if(_INT & 0x01)
+            ret += shift_bit << i;
+        _INT = _INT >> 1;
+    }  
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);    
+    if(_FASTLOCK & 0x01)
+            ret += shift_bit << i;
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);
+
+    return ret;
+}
+uint32_t R_Divider_Reg_Create(uint16_t _MOD,uint8_t _RCOUNTER,uint8_t _PRESCALER,uint8_t _RESERVED,uint8_t _MUXOUT,uint8_t LOAD_CONTROL){
+    uint32_t ret = 0;
+    uint32_t shift_bit = 0x01;
+    uint8_t control_bit = 1;
+    uint8_t i = 0;
+    printf("_MOD : %d INT : %d \r\n",_MOD,_RCOUNTER);
+
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);
+    for(i = 0; i < 2; i++){
+        if(control_bit & 0x01)
+            ret += shift_bit << i;
+        control_bit = control_bit >> 1;
+    }
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);
+    for(i = 2; i < 14; i++){
+        if(_MOD & 0x01)
+            ret += shift_bit << i;
+        _MOD = _MOD >> 1;
+    }
+    for(i = 14; i < 18; i++){
+        if(_RCOUNTER & 0x01)
+            ret += shift_bit << i;
+        _RCOUNTER = _RCOUNTER >> 1;
+    }  
+    if(_PRESCALER & 0x01)
+            ret += shift_bit << i++;
+    if(_RESERVED & 0x01)
+            ret += shift_bit << i++;
+    for(i = 19; i < 22; i++){
+        if(_MUXOUT & 0x01)
+            ret += shift_bit << i;
+        _MUXOUT = _MUXOUT >> 1;
+    }   
+    if(LOAD_CONTROL & 0x01)
+        ret += shift_bit << i++;
+
+    return ret;
+}
+
+void ADF4153_Freq_Calc(unsigned long long Freq,unsigned long long REFin,uint8_t R_Counter,uint32_t chspacing){
+    adf4153_st temp_adf4153;
+    double temp = 0;
+    temp_adf4153.PFD_Value  =  REFin / (R_Counter * 1000);
+    temp_adf4153.MOD_Value  =  (temp_adf4153.PFD_Value / chspacing) * 1000;
+    temp_adf4153.N_Value    =  N_Reg_Value_Calc(((double)(Freq / 1000) /  (double)(temp_adf4153.PFD_Value / 1000)));
+    temp_adf4153.INT_Value  =   temp_adf4153.N_Value ;
+//    printf("\r\ntemp_adf4153.N_Value : %f  temp_adf4153.INT_Value : %f  temp_adf4153.MOD_Value : %f \r\n",temp_adf4153.N_Value,(double)temp_adf4153.INT_Value,(double)temp_adf4153.MOD_Value);
+    temp = temp_adf4153.N_Value - (double)temp_adf4153.INT_Value;
+//    printf("\r\n temp_adf4153.N_Value - (double)temp_adf4153.INT_Value) : %f  temp * (double)temp_adf4153.MOD_Value : %f \r\n",temp,temp * (double)temp_adf4153.MOD_Value);
+    temp_adf4153.FRAC_Value =  (float)temp * temp_adf4153.MOD_Value;
+   
+    printf("\r\ntemp_adf4153.N_Value : %x   : %f ",temp_adf4153.N_Value,((double)(Freq / 1000) /  (double)(temp_adf4153.PFD_Value / 1000)) / 1000);
+    printf("temp_adf4153.MOD_Value : %x   : %d \r\n",temp_adf4153.MOD_Value,temp_adf4153.MOD_Value);
+    uint16_t tempmod = temp_adf4153.FRAC_Value;
+    for(uint8_t i = 0; i < 12; i++){
+        if(temp_adf4153.MOD_Value & 0x800){
+            printf("1");
+        }else{
+            printf("0");
+        }
+        tempmod = tempmod << 1;
+    }
+    printf("\r\n");
+    printf("temp_adf4153.FRAC_Value : %x   : %d\r\n",temp_adf4153.FRAC_Value,temp_adf4153.FRAC_Value);
+    uint16_t tempfrac = temp_adf4153.FRAC_Value;
+    for(uint8_t i = 0; i < 12; i++){
+        if(tempfrac & 0x800){
+            printf("1");
+        }else{
+            printf("0");
+        }
+        tempfrac = tempfrac << 1;
+    }
+    printf("\r\n");    
+    printf("temp_adf4153.INT_Value : %x   : %d\r\n",temp_adf4153.INT_Value,temp_adf4153.INT_Value); 
+    uint16_t tempint = temp_adf4153.INT_Value;
+    for(uint8_t i = 0; i < 9; i++){
+        if(tempint & 0x100){
+            printf("1");
+        }else{
+            printf("0");
+        }
+        tempint = tempint << 1;
+    }
+    printf("\r\n");    
+
+    printf("R0: %x  R1: %x \r\n",N_Divider_Reg_Create(temp_adf4153.FRAC_Value,temp_adf4153.INT_Value,0),R_Divider_Reg_Create(temp_adf4153.MOD_Value,R_Counter,1,0,2,0));   
+        
+//    R_Divider_Reg_Create(temp_adf4153.MOD_Value,R_Counter,1,0,1,0); //prescaler 1 : 8/9 0: 4/5
+}
+
+void ADF_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2,uint32_t R3){
+    R3  = R3  & 0x0007FF;
+    R2 = R2 & 0x00FFFF;
+    R1 = R1 & 0xFFFFFF;
+    R0 = R0 & 0xFFFFFF;
+    
+    HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
+    HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
+    printf("YJ : R3 : %x ",R3);
+    printf("\r\n");
+    /*   R3 Ctrl    */
+    for(int i =0; i < 11; i++){
+        if(R3 & 0x000400){
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_SET);
+            printf("1");
+        }
+        else{
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
+            printf("0");
+        }
+        HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
+        HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
+        R3 = (R3 << 1);
+    }
+    printf("\r\n");
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
+    
+    /*   R2 Ctrl    */
+     for(int i =0; i < 16; i++){
+         if(R2 & 0x008000){
+             HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_SET);
+             printf("1");
+         }
+         else{
+             HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
+             printf("0");
+         }
+         HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
+         HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
+         R2 = ((R2 << 1) & 0x00FFFF);
+     }
+     printf("\r\n");
+     HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
+     HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
+    
+     /*   R1 Ctrl    */
+    for(int i =0; i < 24; i++){
+        if(R1 & 0x800000){
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_SET);
+            printf("1");
+        }
+        else{
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
+            printf("0");
+        }
+        HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
+        HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
+        R1 = ((R1 << 1) & 0xFFFFFF);
+    }
+    printf("\r\n");
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
+
+
+        /*   R0 Ctrl    */
+   
+    for(int i =0; i < 24; i++){
+        if(R0 & 0x800000){
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_SET);
+            printf("1");
+        }
+        else{
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
+            printf("0");
+        }
+        HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
+        HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
+        R0 = ((R0 << 1) & 0xFFFFFF);
+    }
+    printf("\r\n");
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
+
+}

insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/adf4153(6358).h

@@ -0,0 +1,61 @@
+/**************************************************************************//**
+*   @file   adf4153.h
+*   @brief  Header file of adf4153 driver.
+*
+*   @author Istvan Csomortani (istvan.csomortani@analog.com)
+*
+*******************************************************************************
+* Copyright 2013(c) Analog Devices, Inc.
+*
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*  - Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*  - Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in
+*    the documentation and/or other materials provided with the
+*    distribution.
+*  - Neither the name of Analog Devices, Inc. nor the names of its
+*    contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*  - The use of this software may or may not infringe the patent rights
+*    of one or more patent holders.  This license does not release you
+*    from the requirement that you obtain separate licenses from these
+*    patent holders to use this software.
+*  - Use of the software either in source or binary form, must be run
+*    on or directly connected to an Analog Devices Inc. component.
+*
+* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED
+* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY
+* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+* INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+#ifndef __ADF4153_H__
+#define __ADF4153_H__
+
+#include "main.h"
+typedef struct _PLL_Setting_st{
+
+    GPIO_TypeDef * PLL_CLK_PORT;
+    uint16_t       PLL_CLK_PIN;
+    GPIO_TypeDef * PLL_DATA_PORT;
+    uint16_t       PLL_DATA_PIN;
+    GPIO_TypeDef * PLL_ENABLE_PORT;
+    uint16_t       PLL_ENABLE_PIN;
+} PLL_Setting_st;
+void ADF4153_Freq_Calc(unsigned long long Freq,unsigned long long REFin,uint8_t R_Counter,uint32_t chspacing);
+
+
+void ADF_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2,uint32_t R3);
+
+
+#endif // __ADF4153_H__

insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/includes(188).h

@@ -0,0 +1,13 @@
+/*
+ * includes.h
+ *
+ *  Created on: 2019. 7. 28.
+ *      Author: parkyj
+ */
+
+#ifndef INCLUDES_H_
+#define INCLUDES_H_
+
+
+
+#endif /* INCLUDES_H_ */

insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/includes(4979).c

@@ -0,0 +1,8 @@
+/*
+ * includes.c
+ *
+ *  Created on: 2019. 7. 28.
+ *      Author: parkyj
+ */
+
+

insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/main(4523).h

@@ -0,0 +1,241 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : main.h
+  * @brief          : Header for main.c file.
+  *                   This file contains the common defines of the application.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include <stdio.h>
+#include <stdbool.h>
+#include "PE43711.h"
+#include "BDA4601.h"
+#include "zig_operate.h"
+#include "pll_4113.h"
+#include "adf4153.h"
+#include "uart.h"
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+typedef struct _ATTEN_Setting_st{
+
+    GPIO_TypeDef * CLK_PORT;
+    uint16_t       CLK_PIN;
+    GPIO_TypeDef * DATA_PORT;
+    uint16_t       DATA_PIN;    
+    GPIO_TypeDef * ENABLE_PORT;    
+    uint16_t       ENABLE_PIN;    
+    GPIO_TypeDef * PATH_EN_PORT;    
+    uint16_t       PATH_EN_PIN;    
+} ATTEN_Setting_st;
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+volatile uint32_t UartTimerCnt;
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+extern void Pol_Delay_us(volatile uint32_t microseconds);
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+#define ATT_EN_1_8G_DL1_Pin GPIO_PIN_2
+#define ATT_EN_1_8G_DL1_GPIO_Port GPIOE
+#define ATT_EN_1_8G_DL2_Pin GPIO_PIN_3
+#define ATT_EN_1_8G_DL2_GPIO_Port GPIOE
+#define ATT_EN_1_8G_UL1_Pin GPIO_PIN_4
+#define ATT_EN_1_8G_UL1_GPIO_Port GPIOE
+#define ATT_EN_1_8G_UL2_Pin GPIO_PIN_5
+#define ATT_EN_1_8G_UL2_GPIO_Port GPIOE
+#define ATT_EN_1_8G_UL3_Pin GPIO_PIN_6
+#define ATT_EN_1_8G_UL3_GPIO_Port GPIOE
+#define ATT_EN_1_8G_UL4_Pin GPIO_PIN_13
+#define ATT_EN_1_8G_UL4_GPIO_Port GPIOC
+#define PATH_EN_1_8G_DL_Pin GPIO_PIN_14
+#define PATH_EN_1_8G_DL_GPIO_Port GPIOC
+#define PATH_EN_1_8G_UL_Pin GPIO_PIN_15
+#define PATH_EN_1_8G_UL_GPIO_Port GPIOC
+#define PLL_EN_1_8G_DL_Pin GPIO_PIN_0
+#define PLL_EN_1_8G_DL_GPIO_Port GPIOF
+#define PLL_EN_1_8G_UL_Pin GPIO_PIN_1
+#define PLL_EN_1_8G_UL_GPIO_Port GPIOF
+#define PLL_LD_1_8G_DL_Pin GPIO_PIN_2
+#define PLL_LD_1_8G_DL_GPIO_Port GPIOF
+#define PLL_LD_1_8G_UL_Pin GPIO_PIN_3
+#define PLL_LD_1_8G_UL_GPIO_Port GPIOF
+#define ATT_EN_2_1G_DL1_Pin GPIO_PIN_4
+#define ATT_EN_2_1G_DL1_GPIO_Port GPIOF
+#define ATT_EN_2_1G_DL2_Pin GPIO_PIN_5
+#define ATT_EN_2_1G_DL2_GPIO_Port GPIOF
+#define ATT_EN_2_1G_UL1_Pin GPIO_PIN_6
+#define ATT_EN_2_1G_UL1_GPIO_Port GPIOF
+#define ATT_EN_2_1G_UL2_Pin GPIO_PIN_7
+#define ATT_EN_2_1G_UL2_GPIO_Port GPIOF
+#define ATT_EN_2_1G_UL3_Pin GPIO_PIN_8
+#define ATT_EN_2_1G_UL3_GPIO_Port GPIOF
+#define ATT_EN_2_1G_UL4_Pin GPIO_PIN_9
+#define ATT_EN_2_1G_UL4_GPIO_Port GPIOF
+#define DET_3_5G_UL_IN_Pin GPIO_PIN_0
+#define DET_3_5G_UL_IN_GPIO_Port GPIOC
+#define DET_3_5G_UL_OUT_Pin GPIO_PIN_1
+#define DET_3_5G_UL_OUT_GPIO_Port GPIOC
+#define RFU_TEMP_Pin GPIO_PIN_2
+#define RFU_TEMP_GPIO_Port GPIOC
+#define _28V_DET_Pin GPIO_PIN_3
+#define _28V_DET_GPIO_Port GPIOC
+#define DET_1_8G_DL_IN_Pin GPIO_PIN_0
+#define DET_1_8G_DL_IN_GPIO_Port GPIOA
+#define DET_1_8G_DL_OUT_Pin GPIO_PIN_1
+#define DET_1_8G_DL_OUT_GPIO_Port GPIOA
+#define DET_1_8G_UL_IN_Pin GPIO_PIN_2
+#define DET_1_8G_UL_IN_GPIO_Port GPIOA
+#define DET_1_8G_UL_OUT_Pin GPIO_PIN_3
+#define DET_1_8G_UL_OUT_GPIO_Port GPIOA
+#define DET_2_1G_DL_IN_Pin GPIO_PIN_4
+#define DET_2_1G_DL_IN_GPIO_Port GPIOA
+#define DET_2_1G_DL_OUT_Pin GPIO_PIN_5
+#define DET_2_1G_DL_OUT_GPIO_Port GPIOA
+#define DET_2_1G_UL_IN_Pin GPIO_PIN_6
+#define DET_2_1G_UL_IN_GPIO_Port GPIOA
+#define DET_2_1G_UL_OUT_Pin GPIO_PIN_7
+#define DET_2_1G_UL_OUT_GPIO_Port GPIOA
+#define DET_3_5G_DL_IN_Pin GPIO_PIN_0
+#define DET_3_5G_DL_IN_GPIO_Port GPIOB
+#define DET_3_5G_DL_OUT_Pin GPIO_PIN_1
+#define DET_3_5G_DL_OUT_GPIO_Port GPIOB
+#define PLL_DATA_Pin GPIO_PIN_8
+#define PLL_DATA_GPIO_Port GPIOD
+#define PLL_CLK_Pin GPIO_PIN_9
+#define PLL_CLK_GPIO_Port GPIOD
+#define ATT_DATA_Pin GPIO_PIN_10
+#define ATT_DATA_GPIO_Port GPIOD
+#define ATT_CLK_Pin GPIO_PIN_11
+#define ATT_CLK_GPIO_Port GPIOD
+#define ALARM_DC_Pin GPIO_PIN_12
+#define ALARM_DC_GPIO_Port GPIOD
+#define ALARM_AC_Pin GPIO_PIN_13
+#define ALARM_AC_GPIO_Port GPIOD
+#define DA_LDAC_Pin GPIO_PIN_15
+#define DA_LDAC_GPIO_Port GPIOD
+#define DA_SYNC_Pin GPIO_PIN_2
+#define DA_SYNC_GPIO_Port GPIOG
+#define DA_SCLK_Pin GPIO_PIN_3
+#define DA_SCLK_GPIO_Port GPIOG
+#define DA_DIN_Pin GPIO_PIN_4
+#define DA_DIN_GPIO_Port GPIOG
+#define _T_SYNC_UL_Pin GPIO_PIN_5
+#define _T_SYNC_UL_GPIO_Port GPIOG
+#define T_SYNC_UL_Pin GPIO_PIN_6
+#define T_SYNC_UL_GPIO_Port GPIOG
+#define _T_SYNC_DL_Pin GPIO_PIN_7
+#define _T_SYNC_DL_GPIO_Port GPIOG
+#define T_SYNC_DL_Pin GPIO_PIN_8
+#define T_SYNC_DL_GPIO_Port GPIOG
+#define PLL_EN_3_5G_L_Pin GPIO_PIN_6
+#define PLL_EN_3_5G_L_GPIO_Port GPIOC
+#define PLL_EN_3_5G_H_Pin GPIO_PIN_7
+#define PLL_EN_3_5G_H_GPIO_Port GPIOC
+#define PLL_LD_3_5G_L_Pin GPIO_PIN_8
+#define PLL_LD_3_5G_L_GPIO_Port GPIOC
+#define PLL_LD_3_5G_H_Pin GPIO_PIN_9
+#define PLL_LD_3_5G_H_GPIO_Port GPIOC
+#define PLL_CLK_3_5G_Pin GPIO_PIN_15
+#define PLL_CLK_3_5G_GPIO_Port GPIOA
+#define PLL_ON_OFF_3_5G_L_Pin GPIO_PIN_10
+#define PLL_ON_OFF_3_5G_L_GPIO_Port GPIOC
+#define PLL_DATA_3_5G_Pin GPIO_PIN_11
+#define PLL_DATA_3_5G_GPIO_Port GPIOC
+#define PLL_ON_OFF_3_5G_H_Pin GPIO_PIN_12
+#define PLL_ON_OFF_3_5G_H_GPIO_Port GPIOC
+#define ATT_CLK_3_5G_Pin GPIO_PIN_0
+#define ATT_CLK_3_5G_GPIO_Port GPIOD
+#define ATT_EN_3_5G_Pin GPIO_PIN_1
+#define ATT_EN_3_5G_GPIO_Port GPIOD
+#define ATT_DATA_3_5G_DL_Pin GPIO_PIN_2
+#define ATT_DATA_3_5G_DL_GPIO_Port GPIOD
+#define ATT_DATA_3_5G_UL_Pin GPIO_PIN_3
+#define ATT_DATA_3_5G_UL_GPIO_Port GPIOD
+#define ATT_DATA_3_5G_COM1_Pin GPIO_PIN_4
+#define ATT_DATA_3_5G_COM1_GPIO_Port GPIOD
+#define ATT_DATA_3_5G_COM2_Pin GPIO_PIN_5
+#define ATT_DATA_3_5G_COM2_GPIO_Port GPIOD
+#define ATT_DATA_3_5G_COM3_Pin GPIO_PIN_6
+#define ATT_DATA_3_5G_COM3_GPIO_Port GPIOD
+#define PATH_EN_3_5G_L_Pin GPIO_PIN_7
+#define PATH_EN_3_5G_L_GPIO_Port GPIOD
+#define PATH_EN_3_5G_H_Pin GPIO_PIN_9
+#define PATH_EN_3_5G_H_GPIO_Port GPIOG
+#define PATH_EN_3_5G_DL_Pin GPIO_PIN_10
+#define PATH_EN_3_5G_DL_GPIO_Port GPIOG
+#define PATH_EN_3_5G_UL_Pin GPIO_PIN_11
+#define PATH_EN_3_5G_UL_GPIO_Port GPIOG
+#define PLL_ON_OFF_3_5G_LG12_Pin GPIO_PIN_12
+#define PLL_ON_OFF_3_5G_LG12_GPIO_Port GPIOG
+#define PLL_ON_OFF_3_5G_HG13_Pin GPIO_PIN_13
+#define PLL_ON_OFF_3_5G_HG13_GPIO_Port GPIOG
+#define BOOT_LED_Pin GPIO_PIN_14
+#define BOOT_LED_GPIO_Port GPIOG
+#define PLL_EN_2_1G_DL_Pin GPIO_PIN_3
+#define PLL_EN_2_1G_DL_GPIO_Port GPIOB
+#define PLL_EN_2_1G_UL_Pin GPIO_PIN_4
+#define PLL_EN_2_1G_UL_GPIO_Port GPIOB
+#define PLL_LD_2_1G_DL_Pin GPIO_PIN_5
+#define PLL_LD_2_1G_DL_GPIO_Port GPIOB
+#define PLL_LD_2_1G_UL_Pin GPIO_PIN_6
+#define PLL_LD_2_1G_UL_GPIO_Port GPIOB
+#define PATH_EN_2_1G_DL_Pin GPIO_PIN_0
+#define PATH_EN_2_1G_DL_GPIO_Port GPIOE
+#define PATH_EN_2_1G_UL_Pin GPIO_PIN_1
+#define PATH_EN_2_1G_UL_GPIO_Port GPIOE
+/* USER CODE BEGIN Private defines */
+#define BLUECELL_HEADER 0xBE
+#define DEBUG_PRINT   
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/main(5473).c

@@ -0,0 +1,713 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : main.c
+  * @brief          : Main program body
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+ADC_HandleTypeDef hadc1;
+DMA_HandleTypeDef hdma_adc1;
+
+TIM_HandleTypeDef htim6;
+
+UART_HandleTypeDef huart1;
+DMA_HandleTypeDef hdma_usart1_rx;
+
+/* USER CODE BEGIN PV */
+volatile uint32_t LedTimerCnt = 0;
+volatile uint32_t UartTimerCnt = 0;
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_DMA_Init(void);
+static void MX_ADC1_Init(void);
+static void MX_USART1_UART_Init(void);
+static void MX_TIM6_Init(void);
+static void MX_NVIC_Init(void);
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+#define ADC_EA     14
+__IO uint32_t ADCvalue[ADC_EA];
+
+#if 1 // PYJ.2019.07.26_BEGIN --
+
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+{
+    if(htim->Instance == TIM6){
+        UartTimerCnt++;
+        LedTimerCnt++;
+    }
+} 
+#endif // PYJ.2019.07.26_END -- 
+int _write (int file, uint8_t *ptr, uint16_t len)
+{
+    HAL_UART_Transmit(&huart1, ptr, len,10);
+    return len;
+}
+void Pol_Delay_us(volatile uint32_t microseconds)
+{
+  /* Go to number of cycles for system */
+  microseconds *= (SystemCoreClock / 1000000);
+ 
+  /* Delay till end */
+  while (microseconds--);
+}
+
+
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* USER CODE END 1 */
+  
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_DMA_Init();
+  MX_ADC1_Init();
+  MX_USART1_UART_Init();
+  MX_TIM6_Init();
+
+  /* Initialize interrupts */
+  MX_NVIC_Init();
+  /* USER CODE BEGIN 2 */
+  setbuf(stdout, NULL);
+  printf("UART Start \r\n");
+  HAL_UART_Receive_DMA(&huart1, TerminalQueue.Buffer, 1);
+    HAL_GPIO_WritePin(PATH_EN_3_5G_L_GPIO_Port,PATH_EN_3_5G_L_Pin, GPIO_PIN_SET);
+    HAL_GPIO_WritePin(PATH_EN_3_5G_H_GPIO_Port,PATH_EN_3_5G_H_Pin, GPIO_PIN_SET);
+    HAL_GPIO_WritePin(PATH_EN_3_5G_DL_GPIO_Port,PATH_EN_3_5G_DL_Pin, GPIO_PIN_SET);
+    HAL_GPIO_WritePin(PATH_EN_3_5G_UL_GPIO_Port,PATH_EN_3_5G_UL_Pin, GPIO_PIN_SET);
+    HAL_GPIO_WritePin(PATH_EN_3_5G_L_GPIO_Port,PATH_EN_3_5G_L_Pin, GPIO_PIN_SET);  
+    HAL_GPIO_WritePin(PLL_ON_OFF_3_5G_H_GPIO_Port,PLL_ON_OFF_3_5G_H_Pin, GPIO_PIN_SET);
+    HAL_GPIO_WritePin(PLL_ON_OFF_3_5G_L_GPIO_Port,PLL_ON_OFF_3_5G_L_Pin, GPIO_PIN_SET);  
+    HAL_GPIO_WritePin(PATH_EN_2_1G_DL_GPIO_Port,PATH_EN_2_1G_DL_Pin, GPIO_PIN_SET);
+    HAL_GPIO_WritePin(PATH_EN_2_1G_UL_GPIO_Port,PATH_EN_2_1G_UL_Pin, GPIO_PIN_SET);
+    HAL_GPIO_WritePin(PATH_EN_1_8G_DL_GPIO_Port,PATH_EN_1_8G_DL_Pin, GPIO_PIN_SET);
+    HAL_GPIO_WritePin(PATH_EN_1_8G_UL_GPIO_Port,PATH_EN_1_8G_UL_Pin, GPIO_PIN_SET);
+    HAL_Delay(1);
+
+  printf("\r\nPLL_EN_3_5G_L_GPIO_Port\r\n");
+  PLL_Setting_st Pll_test = {
+      PLL_CLK_3_5G_GPIO_Port,
+      PLL_CLK_3_5G_Pin,
+      PLL_DATA_3_5G_GPIO_Port,
+      PLL_DATA_3_5G_Pin,
+    PLL_EN_3_5G_L_GPIO_Port,    
+    PLL_EN_3_5G_L_Pin,
+  };
+  ADF4153_Module_Ctrl(Pll_test,0x2B44B0,0x14BE81,0x0013C2,0x000003);
+
+//  ADF4153_R_N_Reg_st temp_reg;
+//  temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
+//
+//  ADF4153_Module_Ctrl(Pll_test,temp_reg.N_reg,temp_reg.R_reg,0x14be81,0x13c2,0x3);      
+
+  HAL_Delay(1);
+    printf("\r\nPLL_EN_3_5G_H_GPIO_Port\r\n");
+  PLL_Setting_st Pll_test2 = {
+      PLL_CLK_3_5G_GPIO_Port,
+      PLL_CLK_3_5G_Pin,
+      PLL_DATA_3_5G_GPIO_Port,
+      PLL_DATA_3_5G_Pin,
+        PLL_EN_3_5G_H_GPIO_Port,    
+        PLL_EN_3_5G_H_Pin,
+  };
+//    temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
+//    ADF4153_Module_Ctrl(Pll_test,temp_reg.N_reg,temp_reg.R_reg,0x14be81,0x13c2,0x3);                  
+  ADF4153_Module_Ctrl(Pll_test2,0x313840,0x14BE81,0x13C2,0x3);
+  HAL_Delay(1);
+  printf("\r\nPLL_EN_2_1G_UL_GPIO_Port\r\n");
+
+  PLL_Setting_st Pll_test3 = {
+      PLL_CLK_GPIO_Port,
+      PLL_CLK_Pin,
+      PLL_DATA_GPIO_Port,
+      PLL_DATA_Pin,
+      PLL_EN_2_1G_UL_GPIO_Port,    
+      PLL_EN_2_1G_UL_Pin,
+  };
+  ADF4113_Module_Ctrl(Pll_test3,0x000410,0x59A31,0x9f8092);
+  HAL_Delay(1);
+  printf("\r\nPLL_EN_2_1G_DL_GPIO_Port\r\n");
+    
+  PLL_Setting_st Pll_test4 = {
+      PLL_CLK_GPIO_Port,
+      PLL_CLK_Pin,
+      PLL_DATA_GPIO_Port,
+      PLL_DATA_Pin,
+      PLL_EN_2_1G_DL_GPIO_Port,    
+      PLL_EN_2_1G_DL_Pin,
+  };
+  ADF4113_Module_Ctrl(Pll_test4,0x410,0x4DE71,0x9F8092);
+
+    HAL_Delay(1);
+    printf("\r\nPLL_EN_1_8G_UL_GPIO_Port\r\n");
+    PLL_Setting_st Pll_test5 = {
+        PLL_CLK_GPIO_Port,
+        PLL_CLK_Pin,
+        PLL_DATA_GPIO_Port,
+        PLL_DATA_Pin,
+        PLL_EN_1_8G_UL_GPIO_Port,    
+        PLL_EN_1_8G_UL_Pin,
+  };
+  ADF4113_Module_Ctrl(Pll_test5,0x000410,0x038D31,0x9f8092);
+    HAL_Delay(1);
+    printf("\r\nPLL_EN_1_8G_DL_GPIO_Port\r\n");
+    PLL_Setting_st Pll_test6 = {
+        PLL_CLK_GPIO_Port,
+        PLL_CLK_Pin,
+        PLL_DATA_GPIO_Port,
+        PLL_DATA_Pin,
+        PLL_EN_1_8G_DL_GPIO_Port,    
+        PLL_EN_1_8G_DL_Pin,
+  };
+  ADF4113_Module_Ctrl(Pll_test6,0x000410,0x03E801,0x9F8092);
+  BDA4601_Test();
+
+
+//  ADF_Module_Ctrl(Pll_test,0x324000,0x144051,0x0017c2,0x0003c7);
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+//  while(HAL_ADCEx_Calibration_Start(&hadc1) != HAL_OK); //ADC Calibration 
+//   HAL_ADC_Start_DMA(&hadc1, (uint32_t*)ADCvalue, ADC_EA);
+  while (1)
+  {
+    if(LedTimerCnt > 500){HAL_GPIO_TogglePin(BOOT_LED_GPIO_Port,GPIO_PIN_14);LedTimerCnt = 0;}
+    while (TerminalQueue.data > 0 && UartTimerCnt > 100) GetDataFromUartQueue(&hTerminal);
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2;
+  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL15;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
+  PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6;
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+  {
+    Error_Handler();
+  }
+}
+
+/**
+  * @brief NVIC Configuration.
+  * @retval None
+  */
+static void MX_NVIC_Init(void)
+{
+  /* USART1_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(USART1_IRQn);
+  /* TIM6_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(TIM6_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(TIM6_IRQn);
+}
+
+/**
+  * @brief ADC1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_ADC1_Init(void)
+{
+
+  /* USER CODE BEGIN ADC1_Init 0 */
+
+  /* USER CODE END ADC1_Init 0 */
+
+  ADC_ChannelConfTypeDef sConfig = {0};
+
+  /* USER CODE BEGIN ADC1_Init 1 */
+
+  /* USER CODE END ADC1_Init 1 */
+  /** Common config 
+  */
+  hadc1.Instance = ADC1;
+  hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE;
+  hadc1.Init.ContinuousConvMode = ENABLE;
+  hadc1.Init.DiscontinuousConvMode = DISABLE;
+  hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
+  hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+  hadc1.Init.NbrOfConversion = 14;
+  if (HAL_ADC_Init(&hadc1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Channel = ADC_CHANNEL_0;
+  sConfig.Rank = ADC_REGULAR_RANK_1;
+  sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Rank = ADC_REGULAR_RANK_2;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Rank = ADC_REGULAR_RANK_3;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Rank = ADC_REGULAR_RANK_4;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Rank = ADC_REGULAR_RANK_5;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Rank = ADC_REGULAR_RANK_6;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Rank = ADC_REGULAR_RANK_7;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Rank = ADC_REGULAR_RANK_8;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Rank = ADC_REGULAR_RANK_9;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Rank = ADC_REGULAR_RANK_10;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Rank = ADC_REGULAR_RANK_11;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Rank = ADC_REGULAR_RANK_12;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Rank = ADC_REGULAR_RANK_13;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Rank = ADC_REGULAR_RANK_14;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN ADC1_Init 2 */
+
+  /* USER CODE END ADC1_Init 2 */
+
+}
+
+/**
+  * @brief TIM6 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_TIM6_Init(void)
+{
+
+  /* USER CODE BEGIN TIM6_Init 0 */
+
+  /* USER CODE END TIM6_Init 0 */
+
+  TIM_MasterConfigTypeDef sMasterConfig = {0};
+
+  /* USER CODE BEGIN TIM6_Init 1 */
+
+  /* USER CODE END TIM6_Init 1 */
+  htim6.Instance = TIM6;
+  htim6.Init.Prescaler = 6000-1;
+  htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
+  htim6.Init.Period = 10;
+  htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+  if (HAL_TIM_Base_Init(&htim6) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+  if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN TIM6_Init 2 */
+
+  /* USER CODE END TIM6_Init 2 */
+
+}
+
+/**
+  * @brief USART1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_USART1_UART_Init(void)
+{
+
+  /* USER CODE BEGIN USART1_Init 0 */
+
+  /* USER CODE END USART1_Init 0 */
+
+  /* USER CODE BEGIN USART1_Init 1 */
+
+  /* USER CODE END USART1_Init 1 */
+  huart1.Instance = USART1;
+  huart1.Init.BaudRate = 115200;
+  huart1.Init.WordLength = UART_WORDLENGTH_8B;
+  huart1.Init.StopBits = UART_STOPBITS_1;
+  huart1.Init.Parity = UART_PARITY_NONE;
+  huart1.Init.Mode = UART_MODE_TX_RX;
+  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  huart1.Init.OverSampling = UART_OVERSAMPLING_16;
+  if (HAL_UART_Init(&huart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN USART1_Init 2 */
+
+  /* USER CODE END USART1_Init 2 */
+
+}
+
+/** 
+  * Enable DMA controller clock
+  */
+static void MX_DMA_Init(void) 
+{
+  /* DMA controller clock enable */
+  __HAL_RCC_DMA1_CLK_ENABLE();
+
+  /* DMA interrupt init */
+  /* DMA1_Channel1_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
+  /* DMA1_Channel5_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Channel5_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Channel5_IRQn);
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOE_CLK_ENABLE();
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOF_CLK_ENABLE();
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+  __HAL_RCC_GPIOG_CLK_ENABLE();
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOE, ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin 
+                          |ATT_EN_1_8G_UL3_Pin|PATH_EN_2_1G_DL_Pin|PATH_EN_2_1G_UL_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOC, ATT_EN_1_8G_UL4_Pin|PATH_EN_1_8G_DL_Pin|PATH_EN_1_8G_UL_Pin|PLL_EN_3_5G_L_Pin 
+                          |PLL_EN_3_5G_H_Pin|PLL_ON_OFF_3_5G_L_Pin|PLL_DATA_3_5G_Pin|PLL_ON_OFF_3_5G_H_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOF, PLL_EN_1_8G_DL_Pin|PLL_EN_1_8G_UL_Pin|ATT_EN_2_1G_DL1_Pin|ATT_EN_2_1G_DL2_Pin 
+                          |ATT_EN_2_1G_UL1_Pin|ATT_EN_2_1G_UL2_Pin|ATT_EN_2_1G_UL3_Pin|ATT_EN_2_1G_UL4_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOD, PLL_DATA_Pin|PLL_CLK_Pin|ATT_DATA_Pin|ATT_CLK_Pin 
+                          |DA_LDAC_Pin|ATT_CLK_3_5G_Pin|ATT_EN_3_5G_Pin|ATT_DATA_3_5G_DL_Pin 
+                          |ATT_DATA_3_5G_UL_Pin|ATT_DATA_3_5G_COM1_Pin|ATT_DATA_3_5G_COM2_Pin|ATT_DATA_3_5G_COM3_Pin 
+                          |PATH_EN_3_5G_L_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOG, DA_SYNC_Pin|DA_SCLK_Pin|DA_DIN_Pin|_T_SYNC_UL_Pin 
+                          |T_SYNC_UL_Pin|_T_SYNC_DL_Pin|T_SYNC_DL_Pin|PATH_EN_3_5G_DL_Pin 
+                          |PATH_EN_3_5G_UL_Pin|PLL_ON_OFF_3_5G_LG12_Pin|PLL_ON_OFF_3_5G_HG13_Pin|BOOT_LED_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(PLL_CLK_3_5G_GPIO_Port, PLL_CLK_3_5G_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOB, PLL_EN_2_1G_DL_Pin|PLL_EN_2_1G_UL_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pins : ATT_EN_1_8G_DL1_Pin ATT_EN_1_8G_DL2_Pin ATT_EN_1_8G_UL1_Pin ATT_EN_1_8G_UL2_Pin 
+                           ATT_EN_1_8G_UL3_Pin PATH_EN_2_1G_DL_Pin PATH_EN_2_1G_UL_Pin */
+  GPIO_InitStruct.Pin = ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin 
+                          |ATT_EN_1_8G_UL3_Pin|PATH_EN_2_1G_DL_Pin|PATH_EN_2_1G_UL_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : ATT_EN_1_8G_UL4_Pin PATH_EN_1_8G_DL_Pin PATH_EN_1_8G_UL_Pin PLL_EN_3_5G_L_Pin 
+                           PLL_EN_3_5G_H_Pin PLL_ON_OFF_3_5G_L_Pin PLL_DATA_3_5G_Pin PLL_ON_OFF_3_5G_H_Pin */
+  GPIO_InitStruct.Pin = ATT_EN_1_8G_UL4_Pin|PATH_EN_1_8G_DL_Pin|PATH_EN_1_8G_UL_Pin|PLL_EN_3_5G_L_Pin 
+                          |PLL_EN_3_5G_H_Pin|PLL_ON_OFF_3_5G_L_Pin|PLL_DATA_3_5G_Pin|PLL_ON_OFF_3_5G_H_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : PLL_EN_1_8G_DL_Pin PLL_EN_1_8G_UL_Pin ATT_EN_2_1G_DL1_Pin ATT_EN_2_1G_DL2_Pin 
+                           ATT_EN_2_1G_UL1_Pin ATT_EN_2_1G_UL2_Pin ATT_EN_2_1G_UL3_Pin ATT_EN_2_1G_UL4_Pin */
+  GPIO_InitStruct.Pin = PLL_EN_1_8G_DL_Pin|PLL_EN_1_8G_UL_Pin|ATT_EN_2_1G_DL1_Pin|ATT_EN_2_1G_DL2_Pin 
+                          |ATT_EN_2_1G_UL1_Pin|ATT_EN_2_1G_UL2_Pin|ATT_EN_2_1G_UL3_Pin|ATT_EN_2_1G_UL4_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : PLL_LD_1_8G_DL_Pin PLL_LD_1_8G_UL_Pin */
+  GPIO_InitStruct.Pin = PLL_LD_1_8G_DL_Pin|PLL_LD_1_8G_UL_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : PLL_DATA_Pin PLL_CLK_Pin ATT_DATA_Pin ATT_CLK_Pin 
+                           DA_LDAC_Pin ATT_CLK_3_5G_Pin ATT_EN_3_5G_Pin ATT_DATA_3_5G_DL_Pin 
+                           ATT_DATA_3_5G_UL_Pin ATT_DATA_3_5G_COM1_Pin ATT_DATA_3_5G_COM2_Pin ATT_DATA_3_5G_COM3_Pin 
+                           PATH_EN_3_5G_L_Pin */
+  GPIO_InitStruct.Pin = PLL_DATA_Pin|PLL_CLK_Pin|ATT_DATA_Pin|ATT_CLK_Pin 
+                          |DA_LDAC_Pin|ATT_CLK_3_5G_Pin|ATT_EN_3_5G_Pin|ATT_DATA_3_5G_DL_Pin 
+                          |ATT_DATA_3_5G_UL_Pin|ATT_DATA_3_5G_COM1_Pin|ATT_DATA_3_5G_COM2_Pin|ATT_DATA_3_5G_COM3_Pin 
+                          |PATH_EN_3_5G_L_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : ALARM_DC_Pin ALARM_AC_Pin */
+  GPIO_InitStruct.Pin = ALARM_DC_Pin|ALARM_AC_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : DA_SYNC_Pin DA_SCLK_Pin DA_DIN_Pin _T_SYNC_UL_Pin 
+                           T_SYNC_UL_Pin _T_SYNC_DL_Pin T_SYNC_DL_Pin PATH_EN_3_5G_DL_Pin 
+                           PATH_EN_3_5G_UL_Pin PLL_ON_OFF_3_5G_LG12_Pin PLL_ON_OFF_3_5G_HG13_Pin BOOT_LED_Pin */
+  GPIO_InitStruct.Pin = DA_SYNC_Pin|DA_SCLK_Pin|DA_DIN_Pin|_T_SYNC_UL_Pin 
+                          |T_SYNC_UL_Pin|_T_SYNC_DL_Pin|T_SYNC_DL_Pin|PATH_EN_3_5G_DL_Pin 
+                          |PATH_EN_3_5G_UL_Pin|PLL_ON_OFF_3_5G_LG12_Pin|PLL_ON_OFF_3_5G_HG13_Pin|BOOT_LED_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : PLL_LD_3_5G_L_Pin PLL_LD_3_5G_H_Pin */
+  GPIO_InitStruct.Pin = PLL_LD_3_5G_L_Pin|PLL_LD_3_5G_H_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+  /*Configure GPIO pin : PLL_CLK_3_5G_Pin */
+  GPIO_InitStruct.Pin = PLL_CLK_3_5G_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(PLL_CLK_3_5G_GPIO_Port, &GPIO_InitStruct);
+
+  /*Configure GPIO pin : PATH_EN_3_5G_H_Pin */
+  GPIO_InitStruct.Pin = PATH_EN_3_5G_H_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+  HAL_GPIO_Init(PATH_EN_3_5G_H_GPIO_Port, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : PLL_EN_2_1G_DL_Pin PLL_EN_2_1G_UL_Pin */
+  GPIO_InitStruct.Pin = PLL_EN_2_1G_DL_Pin|PLL_EN_2_1G_UL_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : PLL_LD_2_1G_DL_Pin PLL_LD_2_1G_UL_Pin */
+  GPIO_InitStruct.Pin = PLL_LD_2_1G_DL_Pin|PLL_LD_2_1G_UL_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+}
+
+/* USER CODE BEGIN 4 */
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/main(7269).c

@@ -0,0 +1,708 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : main.c
+  * @brief          : Main program body
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+ADC_HandleTypeDef hadc1;
+DMA_HandleTypeDef hdma_adc1;
+
+TIM_HandleTypeDef htim6;
+
+UART_HandleTypeDef huart1;
+DMA_HandleTypeDef hdma_usart1_rx;
+
+/* USER CODE BEGIN PV */
+volatile uint32_t LedTimerCnt = 0;
+volatile uint32_t UartTimerCnt = 0;
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_DMA_Init(void);
+static void MX_ADC1_Init(void);
+static void MX_USART1_UART_Init(void);
+static void MX_TIM6_Init(void);
+static void MX_NVIC_Init(void);
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+#define ADC_EA     14
+__IO uint32_t ADCvalue[ADC_EA];
+
+#if 1 // PYJ.2019.07.26_BEGIN --
+
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+{
+    if(htim->Instance == TIM6){
+        UartTimerCnt++;
+        LedTimerCnt++;
+    }
+} 
+#endif // PYJ.2019.07.26_END -- 
+int _write (int file, uint8_t *ptr, uint16_t len)
+{
+    HAL_UART_Transmit(&huart1, ptr, len,10);
+    return len;
+}
+void Pol_Delay_us(volatile uint32_t microseconds)
+{
+  /* Go to number of cycles for system */
+  microseconds *= (SystemCoreClock / 1000000);
+ 
+  /* Delay till end */
+  while (microseconds--);
+}
+
+
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* USER CODE END 1 */
+  
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_DMA_Init();
+  MX_ADC1_Init();
+  MX_USART1_UART_Init();
+  MX_TIM6_Init();
+
+  /* Initialize interrupts */
+  MX_NVIC_Init();
+  /* USER CODE BEGIN 2 */
+  setbuf(stdout, NULL);
+  printf("UART Start \r\n");
+  HAL_UART_Receive_DMA(&huart1, TerminalQueue.Buffer, 1);
+    HAL_GPIO_WritePin(PATH_EN_3_5G_L_GPIO_Port,PATH_EN_3_5G_L_Pin, GPIO_PIN_SET);
+    HAL_GPIO_WritePin(PATH_EN_3_5G_H_GPIO_Port,PATH_EN_3_5G_H_Pin, GPIO_PIN_SET);
+    HAL_GPIO_WritePin(PATH_EN_3_5G_DL_GPIO_Port,PATH_EN_3_5G_DL_Pin, GPIO_PIN_SET);
+    HAL_GPIO_WritePin(PATH_EN_3_5G_UL_GPIO_Port,PATH_EN_3_5G_UL_Pin, GPIO_PIN_SET);
+    HAL_GPIO_WritePin(PATH_EN_3_5G_L_GPIO_Port,PATH_EN_3_5G_L_Pin, GPIO_PIN_SET);  
+    HAL_GPIO_WritePin(PLL_ON_OFF_3_5G_H_GPIO_Port,PLL_ON_OFF_3_5G_H_Pin, GPIO_PIN_SET);
+    HAL_GPIO_WritePin(PLL_ON_OFF_3_5G_L_GPIO_Port,PLL_ON_OFF_3_5G_L_Pin, GPIO_PIN_SET);  
+
+    HAL_GPIO_WritePin(PATH_EN_2_1G_DL_GPIO_Port,PATH_EN_2_1G_DL_Pin, GPIO_PIN_SET);
+    HAL_GPIO_WritePin(PATH_EN_2_1G_UL_GPIO_Port,PATH_EN_2_1G_UL_Pin, GPIO_PIN_SET);
+    HAL_GPIO_WritePin(PATH_EN_1_8G_DL_GPIO_Port,PATH_EN_1_8G_DL_Pin, GPIO_PIN_SET);
+    HAL_GPIO_WritePin(PATH_EN_1_8G_UL_GPIO_Port,PATH_EN_1_8G_UL_Pin, GPIO_PIN_SET);
+
+  HAL_Delay(1);
+#if 0 // PYJ.2019.07.28_BEGIN -- 
+  printf("\r\nPLL_EN_3_5G_L_GPIO_Port\r\n");
+  PLL_Setting_st Pll_test = {
+      PLL_CLK_3_5G_GPIO_Port,
+      PLL_CLK_3_5G_Pin,
+      PLL_DATA_3_5G_GPIO_Port,
+      PLL_DATA_3_5G_Pin,
+    PLL_EN_3_5G_L_GPIO_Port,    
+    PLL_EN_3_5G_L_Pin,
+  };
+  ADF_Module_Ctrl(Pll_test,0x2B44B0,0x14BE81,0x0013C2,0x000003);
+  HAL_Delay(1);
+#endif // PYJ.2019.07.28_END -- 
+    printf("\r\nPLL_EN_3_5G_H_GPIO_Port\r\n");
+  PLL_Setting_st Pll_test2 = {
+      PLL_CLK_3_5G_GPIO_Port,
+      PLL_CLK_3_5G_Pin,
+      PLL_DATA_3_5G_GPIO_Port,
+      PLL_DATA_3_5G_Pin,
+        PLL_EN_3_5G_H_GPIO_Port,    
+        PLL_EN_3_5G_H_Pin,
+  };
+  ADF_Module_Ctrl(Pll_test2,0x313840,0x14BE81,0x13C2,0x3);
+  HAL_Delay(1);
+#if 0 // PYJ.2019.07.28_BEGIN -- 
+  printf("\r\nPLL_EN_2_1G_UL_GPIO_Port\r\n");
+
+  PLL_Setting_st Pll_test3 = {
+      PLL_CLK_GPIO_Port,
+      PLL_CLK_Pin,
+      PLL_DATA_GPIO_Port,
+      PLL_DATA_Pin,
+      PLL_EN_2_1G_UL_GPIO_Port,    
+      PLL_EN_2_1G_UL_Pin,
+  };
+  ADF4113_Module_Ctrl(Pll_test3,0x000410,0x59A31,0x9f8092);
+  HAL_Delay(1);
+  printf("\r\nPLL_EN_2_1G_DL_GPIO_Port\r\n");
+    
+  PLL_Setting_st Pll_test4 = {
+      PLL_CLK_GPIO_Port,
+      PLL_CLK_Pin,
+      PLL_DATA_GPIO_Port,
+      PLL_DATA_Pin,
+      PLL_EN_2_1G_DL_GPIO_Port,    
+      PLL_EN_2_1G_DL_Pin,
+  };
+  ADF4113_Module_Ctrl(Pll_test4,0x410,0x4DE71,0x9F8092);
+
+    HAL_Delay(1);
+    printf("\r\nPLL_EN_1_8G_UL_GPIO_Port\r\n");
+    PLL_Setting_st Pll_test5 = {
+        PLL_CLK_GPIO_Port,
+        PLL_CLK_Pin,
+        PLL_DATA_GPIO_Port,
+        PLL_DATA_Pin,
+        PLL_EN_1_8G_UL_GPIO_Port,    
+        PLL_EN_1_8G_UL_Pin,
+  };
+  ADF4113_Module_Ctrl(Pll_test5,0x000410,0x038D31,0x9f8092);
+    HAL_Delay(1);
+    printf("\r\nPLL_EN_1_8G_DL_GPIO_Port\r\n");
+    PLL_Setting_st Pll_test6 = {
+        PLL_CLK_GPIO_Port,
+        PLL_CLK_Pin,
+        PLL_DATA_GPIO_Port,
+        PLL_DATA_Pin,
+        PLL_EN_1_8G_DL_GPIO_Port,    
+        PLL_EN_1_8G_DL_Pin,
+  };
+  ADF4113_Module_Ctrl(Pll_test6,0x000410,0x03E801,0x9F8092);
+#endif // PYJ.2019.07.28_END -- 
+
+//  ADF_Module_Ctrl(Pll_test,0x324000,0x144051,0x0017c2,0x0003c7);
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+//  while(HAL_ADCEx_Calibration_Start(&hadc1) != HAL_OK); //ADC Calibration 
+//   HAL_ADC_Start_DMA(&hadc1, (uint32_t*)ADCvalue, ADC_EA);
+  while (1)
+  {
+    if(LedTimerCnt > 500){HAL_GPIO_TogglePin(BOOT_LED_GPIO_Port,GPIO_PIN_14);LedTimerCnt = 0;}
+    while (TerminalQueue.data > 0 && UartTimerCnt > 100) GetDataFromUartQueue(&hTerminal);
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2;
+  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL15;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
+  PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6;
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+  {
+    Error_Handler();
+  }
+}
+
+/**
+  * @brief NVIC Configuration.
+  * @retval None
+  */
+static void MX_NVIC_Init(void)
+{
+  /* USART1_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(USART1_IRQn);
+  /* TIM6_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(TIM6_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(TIM6_IRQn);
+}
+
+/**
+  * @brief ADC1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_ADC1_Init(void)
+{
+
+  /* USER CODE BEGIN ADC1_Init 0 */
+
+  /* USER CODE END ADC1_Init 0 */
+
+  ADC_ChannelConfTypeDef sConfig = {0};
+
+  /* USER CODE BEGIN ADC1_Init 1 */
+
+  /* USER CODE END ADC1_Init 1 */
+  /** Common config 
+  */
+  hadc1.Instance = ADC1;
+  hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE;
+  hadc1.Init.ContinuousConvMode = ENABLE;
+  hadc1.Init.DiscontinuousConvMode = DISABLE;
+  hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
+  hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+  hadc1.Init.NbrOfConversion = 14;
+  if (HAL_ADC_Init(&hadc1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Channel = ADC_CHANNEL_0;
+  sConfig.Rank = ADC_REGULAR_RANK_1;
+  sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Rank = ADC_REGULAR_RANK_2;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Rank = ADC_REGULAR_RANK_3;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Rank = ADC_REGULAR_RANK_4;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Rank = ADC_REGULAR_RANK_5;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Rank = ADC_REGULAR_RANK_6;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Rank = ADC_REGULAR_RANK_7;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Rank = ADC_REGULAR_RANK_8;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Rank = ADC_REGULAR_RANK_9;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Rank = ADC_REGULAR_RANK_10;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Rank = ADC_REGULAR_RANK_11;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Rank = ADC_REGULAR_RANK_12;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Rank = ADC_REGULAR_RANK_13;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Rank = ADC_REGULAR_RANK_14;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN ADC1_Init 2 */
+
+  /* USER CODE END ADC1_Init 2 */
+
+}
+
+/**
+  * @brief TIM6 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_TIM6_Init(void)
+{
+
+  /* USER CODE BEGIN TIM6_Init 0 */
+
+  /* USER CODE END TIM6_Init 0 */
+
+  TIM_MasterConfigTypeDef sMasterConfig = {0};
+
+  /* USER CODE BEGIN TIM6_Init 1 */
+
+  /* USER CODE END TIM6_Init 1 */
+  htim6.Instance = TIM6;
+  htim6.Init.Prescaler = 6000-1;
+  htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
+  htim6.Init.Period = 10;
+  htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+  if (HAL_TIM_Base_Init(&htim6) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+  if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN TIM6_Init 2 */
+
+  /* USER CODE END TIM6_Init 2 */
+
+}
+
+/**
+  * @brief USART1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_USART1_UART_Init(void)
+{
+
+  /* USER CODE BEGIN USART1_Init 0 */
+
+  /* USER CODE END USART1_Init 0 */
+
+  /* USER CODE BEGIN USART1_Init 1 */
+
+  /* USER CODE END USART1_Init 1 */
+  huart1.Instance = USART1;
+  huart1.Init.BaudRate = 115200;
+  huart1.Init.WordLength = UART_WORDLENGTH_8B;
+  huart1.Init.StopBits = UART_STOPBITS_1;
+  huart1.Init.Parity = UART_PARITY_NONE;
+  huart1.Init.Mode = UART_MODE_TX_RX;
+  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  huart1.Init.OverSampling = UART_OVERSAMPLING_16;
+  if (HAL_UART_Init(&huart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN USART1_Init 2 */
+
+  /* USER CODE END USART1_Init 2 */
+
+}
+
+/** 
+  * Enable DMA controller clock
+  */
+static void MX_DMA_Init(void) 
+{
+  /* DMA controller clock enable */
+  __HAL_RCC_DMA1_CLK_ENABLE();
+
+  /* DMA interrupt init */
+  /* DMA1_Channel1_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
+  /* DMA1_Channel5_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Channel5_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Channel5_IRQn);
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOE_CLK_ENABLE();
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOF_CLK_ENABLE();
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+  __HAL_RCC_GPIOG_CLK_ENABLE();
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOE, ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin 
+                          |ATT_EN_1_8G_UL3_Pin|PATH_EN_2_1G_DL_Pin|PATH_EN_2_1G_UL_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOC, ATT_EN_1_8G_UL4_Pin|PATH_EN_1_8G_DL_Pin|PATH_EN_1_8G_UL_Pin|PLL_EN_3_5G_L_Pin 
+                          |PLL_EN_3_5G_H_Pin|PLL_ON_OFF_3_5G_L_Pin|PLL_DATA_3_5G_Pin|PLL_ON_OFF_3_5G_H_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOF, PLL_EN_1_8G_DL_Pin|PLL_EN_1_8G_UL_Pin|ATT_EN_2_1G_DL1_Pin|ATT_EN_2_1G_DL2_Pin 
+                          |ATT_EN_2_1G_UL1_Pin|ATT_EN_2_1G_UL2_Pin|ATT_EN_2_1G_UL3_Pin|ATT_EN_2_1G_UL4_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOD, PLL_DATA_Pin|PLL_CLK_Pin|ATT_DATA_Pin|ATT_CLK_Pin 
+                          |DA_LDAC_Pin|ATT_CLK_3_5G_Pin|ATT_EN_3_5G_Pin|ATT_DATA_3_5G_DL_Pin 
+                          |ATT_DATA_3_5G_UL_Pin|ATT_DATA_3_5G_COM1_Pin|ATT_DATA_3_5G_COM2_Pin|ATT_DATA_3_5G_COM3_Pin 
+                          |PATH_EN_3_5G_L_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOG, DA_SYNC_Pin|DA_SCLK_Pin|DA_DIN_Pin|_T_SYNC_UL_Pin 
+                          |T_SYNC_UL_Pin|_T_SYNC_DL_Pin|T_SYNC_DL_Pin|PATH_EN_3_5G_DL_Pin 
+                          |PATH_EN_3_5G_UL_Pin|PLL_ON_OFF_3_5G_LG12_Pin|PLL_ON_OFF_3_5G_HG13_Pin|BOOT_LED_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(PLL_CLK_3_5G_GPIO_Port, PLL_CLK_3_5G_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOB, PLL_EN_2_1G_DL_Pin|PLL_EN_2_1G_UL_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pins : ATT_EN_1_8G_DL1_Pin ATT_EN_1_8G_DL2_Pin ATT_EN_1_8G_UL1_Pin ATT_EN_1_8G_UL2_Pin 
+                           ATT_EN_1_8G_UL3_Pin PATH_EN_2_1G_DL_Pin PATH_EN_2_1G_UL_Pin */
+  GPIO_InitStruct.Pin = ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin 
+                          |ATT_EN_1_8G_UL3_Pin|PATH_EN_2_1G_DL_Pin|PATH_EN_2_1G_UL_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : ATT_EN_1_8G_UL4_Pin PATH_EN_1_8G_DL_Pin PATH_EN_1_8G_UL_Pin PLL_EN_3_5G_L_Pin 
+                           PLL_EN_3_5G_H_Pin PLL_ON_OFF_3_5G_L_Pin PLL_DATA_3_5G_Pin PLL_ON_OFF_3_5G_H_Pin */
+  GPIO_InitStruct.Pin = ATT_EN_1_8G_UL4_Pin|PATH_EN_1_8G_DL_Pin|PATH_EN_1_8G_UL_Pin|PLL_EN_3_5G_L_Pin 
+                          |PLL_EN_3_5G_H_Pin|PLL_ON_OFF_3_5G_L_Pin|PLL_DATA_3_5G_Pin|PLL_ON_OFF_3_5G_H_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : PLL_EN_1_8G_DL_Pin PLL_EN_1_8G_UL_Pin ATT_EN_2_1G_DL1_Pin ATT_EN_2_1G_DL2_Pin 
+                           ATT_EN_2_1G_UL1_Pin ATT_EN_2_1G_UL2_Pin ATT_EN_2_1G_UL3_Pin ATT_EN_2_1G_UL4_Pin */
+  GPIO_InitStruct.Pin = PLL_EN_1_8G_DL_Pin|PLL_EN_1_8G_UL_Pin|ATT_EN_2_1G_DL1_Pin|ATT_EN_2_1G_DL2_Pin 
+                          |ATT_EN_2_1G_UL1_Pin|ATT_EN_2_1G_UL2_Pin|ATT_EN_2_1G_UL3_Pin|ATT_EN_2_1G_UL4_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : PLL_LD_1_8G_DL_Pin PLL_LD_1_8G_UL_Pin */
+  GPIO_InitStruct.Pin = PLL_LD_1_8G_DL_Pin|PLL_LD_1_8G_UL_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : PLL_DATA_Pin PLL_CLK_Pin ATT_DATA_Pin ATT_CLK_Pin 
+                           DA_LDAC_Pin ATT_CLK_3_5G_Pin ATT_EN_3_5G_Pin ATT_DATA_3_5G_DL_Pin 
+                           ATT_DATA_3_5G_UL_Pin ATT_DATA_3_5G_COM1_Pin ATT_DATA_3_5G_COM2_Pin ATT_DATA_3_5G_COM3_Pin 
+                           PATH_EN_3_5G_L_Pin */
+  GPIO_InitStruct.Pin = PLL_DATA_Pin|PLL_CLK_Pin|ATT_DATA_Pin|ATT_CLK_Pin 
+                          |DA_LDAC_Pin|ATT_CLK_3_5G_Pin|ATT_EN_3_5G_Pin|ATT_DATA_3_5G_DL_Pin 
+                          |ATT_DATA_3_5G_UL_Pin|ATT_DATA_3_5G_COM1_Pin|ATT_DATA_3_5G_COM2_Pin|ATT_DATA_3_5G_COM3_Pin 
+                          |PATH_EN_3_5G_L_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : ALARM_DC_Pin ALARM_AC_Pin */
+  GPIO_InitStruct.Pin = ALARM_DC_Pin|ALARM_AC_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : DA_SYNC_Pin DA_SCLK_Pin DA_DIN_Pin _T_SYNC_UL_Pin 
+                           T_SYNC_UL_Pin _T_SYNC_DL_Pin T_SYNC_DL_Pin PATH_EN_3_5G_DL_Pin 
+                           PATH_EN_3_5G_UL_Pin PLL_ON_OFF_3_5G_LG12_Pin PLL_ON_OFF_3_5G_HG13_Pin BOOT_LED_Pin */
+  GPIO_InitStruct.Pin = DA_SYNC_Pin|DA_SCLK_Pin|DA_DIN_Pin|_T_SYNC_UL_Pin 
+                          |T_SYNC_UL_Pin|_T_SYNC_DL_Pin|T_SYNC_DL_Pin|PATH_EN_3_5G_DL_Pin 
+                          |PATH_EN_3_5G_UL_Pin|PLL_ON_OFF_3_5G_LG12_Pin|PLL_ON_OFF_3_5G_HG13_Pin|BOOT_LED_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : PLL_LD_3_5G_L_Pin PLL_LD_3_5G_H_Pin */
+  GPIO_InitStruct.Pin = PLL_LD_3_5G_L_Pin|PLL_LD_3_5G_H_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+  /*Configure GPIO pin : PLL_CLK_3_5G_Pin */
+  GPIO_InitStruct.Pin = PLL_CLK_3_5G_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(PLL_CLK_3_5G_GPIO_Port, &GPIO_InitStruct);
+
+  /*Configure GPIO pin : PATH_EN_3_5G_H_Pin */
+  GPIO_InitStruct.Pin = PATH_EN_3_5G_H_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+  HAL_GPIO_Init(PATH_EN_3_5G_H_GPIO_Port, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : PLL_EN_2_1G_DL_Pin PLL_EN_2_1G_UL_Pin */
+  GPIO_InitStruct.Pin = PLL_EN_2_1G_DL_Pin|PLL_EN_2_1G_UL_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : PLL_LD_2_1G_DL_Pin PLL_LD_2_1G_UL_Pin */
+  GPIO_InitStruct.Pin = PLL_LD_2_1G_DL_Pin|PLL_LD_2_1G_UL_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+}
+
+/* USER CODE BEGIN 4 */
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/pll_4113(1863).h

@@ -0,0 +1,15 @@
+/**************************************************************************************************
+  Filename:       hal_adf4113.h
+  Revised:        $Date: 2013-11-17 $
+  Revision:       $Revision: $
+  Description:    This file contains the interface to the ADF4113 frequency synthesizer.
+**************************************************************************************************/
+#ifndef HAL_ADF4113_H
+#define HAL_ADF4113_H
+#include "main.h"
+
+uint8_t halSynSetFreq(uint32_t rf_Freq);
+
+//void ADF4113_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2);
+
+#endif

insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/pll_4113(306).c

@@ -0,0 +1,168 @@
+/**************************************************************************************************
+  Filename:       hal_adf4113.c
+  Revised:        $Date: 2013-11-17 $
+  Revision:       $Revision:  $
+  Description:   This file contains the interface to the ADF4113 frequency synthesizer.
+**************************************************************************************************/
+#include "pll_4113.h"
+
+uint32_t N_Counter_Latch_Create(uint16_t _ACOUNTER,uint16_t _BCOUNTER,uint8_t _CPGAIN);
+
+#define ADF4113_PRESCALE8         0
+#define ADF4113_PRESCALE16        1
+#define ADF4113_PRESCALE32        2
+#define ADF4113_PRESCALE64        3
+// ADF4113 Prescale value for minimum required division ratio
+#define ADF4113_PRE8_MIN_N        56
+#define ADF4113_PRE16_MIN_N       240
+#define ADF4113_PRE32_MIN_N       992
+#define ADF4113_PRE64_MIN_N       4032
+// Frequency Settings
+// Initally, the synthesizer will operate at 2450 MHz
+#define ADF4113_CH_STEP          50000
+#define HAL_SYN_INVALID_PRESCALE  0x04
+#define ADF4113_REF_FREQ_MHZ    13000000
+
+// Error Code
+typedef struct{
+    uint16_t B;
+    uint16_t P;
+    uint16_t A;   
+    uint16_t N;       
+}Adf4113_st;
+uint8_t halSynSetFreq(uint32_t rf_Freq)
+{
+    uint32_t  R, B;
+    uint32_t  A, P, p_mode;
+    uint32_t  N_val = 0;
+    N_val = (rf_Freq / ADF4113_CH_STEP);
+    if( N_val < ADF4113_PRE8_MIN_N) { 
+        return HAL_SYN_INVALID_PRESCALE; 
+    } else if(( N_val> ADF4113_PRE8_MIN_N) && (N_val < ADF4113_PRE16_MIN_N)) { 
+        P = 8;  
+        p_mode = ADF4113_PRESCALE8;
+    } else if(( N_val > ADF4113_PRE16_MIN_N) && (N_val < ADF4113_PRE32_MIN_N)) { 
+        P = 16;
+        p_mode = ADF4113_PRESCALE16;
+        
+    } else if((N_val > ADF4113_PRE32_MIN_N) && ( N_val < ADF4113_PRE64_MIN_N)) { 
+        P = 32;
+        p_mode = ADF4113_PRESCALE32;
+        
+    } else if( N_val > ADF4113_PRE64_MIN_N) { 
+        P = 64; 
+        p_mode = ADF4113_PRESCALE64;
+    }
+    P = 32;
+    B = N_val / P;
+    A = N_val -(B * P);
+    printf("B : %d , A  : %d    N_VAL  : %d \r\n",B,A,N_val);
+    printf("YJ 4113 : %x \r\n",N_Counter_Latch_Create(A,B,0));
+}
+uint32_t N_Counter_Latch_Create(uint16_t _ACOUNTER,uint16_t _BCOUNTER,uint8_t _CPGAIN){
+    uint32_t ret = 0;
+    uint32_t shift_bit = 0x01;
+    uint8_t control_bit = 1;
+    uint8_t i = 0;
+    uint8_t reserve = 0;
+    printf("_ACOUNTER : %d _BCOUNTER : %d \r\n",_ACOUNTER,_BCOUNTER);
+
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);
+    for(i = 0; i < 2; i++){
+        if(control_bit & 0x01)
+            ret += shift_bit << i;
+        control_bit = control_bit >> 1;
+    }
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);
+    for(i = 2; i < 8; i++){
+        if(_ACOUNTER & 0x01)
+            ret += shift_bit << i;
+        _ACOUNTER = _ACOUNTER >> 1;
+    }  
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);
+    for(i = 8; i < 21; i++){
+        if(_BCOUNTER & 0x01)
+            ret += shift_bit << i;
+        _BCOUNTER = _BCOUNTER >> 1;
+    }      
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);
+    if(_CPGAIN & 0x01)
+            ret += shift_bit << i++;
+    for(i = 22; i < 24; i++){
+        if(reserve & 0x01)
+            ret += shift_bit << i;
+        reserve = reserve >> 1;
+    }   
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);
+    return ret;
+}
+
+void ADF4113_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2){
+    R2 = R2 & 0xFFFFFF;
+    R1 = R1 & 0xFFFFFF;
+    R0 = R0 & 0xFFFFFF;
+    
+    HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
+    HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
+    /*   R2 Ctrl    */
+     for(int i =0; i < 24; i++){
+         if(R2 & 0x800000){
+            printf("1");
+             HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_SET);
+         }
+         else{
+            printf("0");
+             HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
+         }
+          HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
+         Pol_Delay_us(10);
+          HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
+         R2 = ((R2 << 1) & 0xFFFFFF);
+     }
+     printf("\r\n");
+     HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
+     Pol_Delay_us(10);
+     HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
+        /*   R0 Ctrl    */
+   
+    for(int i =0; i < 24; i++){
+        if(R0 & 0x800000){
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_SET);
+            printf("1");
+        }
+        else{
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
+            printf("0");
+        }
+         HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
+        Pol_Delay_us(10);
+         HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
+        R0 = ((R0 << 1) & 0xFFFFFF);
+    }  
+        printf("\r\n");
+     HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
+     
+     Pol_Delay_us(10);
+     HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);    
+     /*   R1 Ctrl    */
+    for(int i =0; i < 24; i++){
+        if(R1 & 0x800000){
+            printf("1");
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_SET);
+        }
+        else{
+            printf("0");            
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
+        }
+         HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
+        Pol_Delay_us(10);
+         HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
+        R1 = ((R1 << 1) & 0xFFFFFF);
+    }
+        printf("\r\n");
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
+    Pol_Delay_us(10);
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
+
+}

insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/zig_operate(3178).c

@@ -0,0 +1,246 @@
+/*
+ * zig_operate.c
+ *
+ *  Created on: 2019. 7. 26.
+ *      Author: parkyj
+ */
+#include "zig_operate.h"
+
+/* * * * * * * #define Struct* * * * * * * */
+PLL_Setting_st Pll_1_8GHz_DL = {
+	PLL_CLK_GPIO_Port,
+	PLL_CLK_Pin,
+	PLL_DATA_GPIO_Port,
+	PLL_DATA_Pin,
+    PLL_EN_1_8G_DL_GPIO_Port,    
+    PLL_EN_1_8G_DL_Pin,
+};
+PLL_Setting_st Pll_1_8GHz_UL = {
+    PLL_CLK_GPIO_Port,
+    PLL_CLK_Pin,
+    PLL_DATA_GPIO_Port,
+    PLL_DATA_Pin,
+    PLL_EN_1_8G_UL_GPIO_Port,    
+    PLL_EN_1_8G_UL_Pin,
+};
+PLL_Setting_st Pll_2_1GHz_DL = {
+    PLL_CLK_GPIO_Port,
+    PLL_CLK_Pin,
+    PLL_DATA_GPIO_Port,
+    PLL_DATA_Pin,
+    PLL_EN_2_1G_DL_GPIO_Port,    
+    PLL_EN_2_1G_DL_Pin,
+};
+PLL_Setting_st Pll_2_1GHz_UL = {
+    PLL_CLK_GPIO_Port,
+    PLL_CLK_Pin,
+    PLL_DATA_GPIO_Port,
+    PLL_DATA_Pin,
+    PLL_EN_2_1G_UL_GPIO_Port,    
+    PLL_EN_2_1G_UL_Pin,
+};
+/* * * * * * * * NOT YET * * * * * * * */
+PLL_Setting_st Pll_3_5GHz_DL = {
+    ATT_CLK_3_5G_GPIO_Port,
+    ATT_EN_3_5G_Pin,
+    PLL_DATA_GPIO_Port,
+    PLL_DATA_Pin,
+    PLL_EN_2_1G_DL_GPIO_Port,    
+    PLL_EN_2_1G_DL_Pin,
+};
+PLL_Setting_st Pll_3_5GHz_UL = {
+    PLL_CLK_GPIO_Port,
+    PLL_CLK_Pin,
+    PLL_DATA_GPIO_Port,
+    PLL_DATA_Pin,
+    PLL_EN_2_1G_UL_GPIO_Port,    
+    PLL_EN_2_1G_UL_Pin,
+};
+/* * * * * * * * ATTEN * * * * * * * */    
+ATTEN_Setting_st Atten_1_8Ghz_DL1 ={
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_1_8G_DL1_GPIO_Port,    
+    ATT_EN_1_8G_DL1_Pin,
+    PATH_EN_1_8G_DL_GPIO_Port,
+    PATH_EN_1_8G_DL_Pin,
+};
+
+ATTEN_Setting_st Atten_1_8Ghz_DL2 ={
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_1_8G_DL2_GPIO_Port,    
+    ATT_EN_1_8G_DL2_Pin,
+    PATH_EN_1_8G_DL_GPIO_Port,
+    PATH_EN_1_8G_DL_Pin,    
+};
+ATTEN_Setting_st Atten_1_8Ghz_UL1 ={
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_1_8G_UL1_GPIO_Port,    
+    ATT_EN_1_8G_UL1_Pin,
+    PATH_EN_1_8G_UL_GPIO_Port,
+    PATH_EN_1_8G_UL_Pin,      
+};
+ATTEN_Setting_st Atten_1_8Ghz_UL2 ={
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_1_8G_UL2_GPIO_Port,    
+    ATT_EN_1_8G_UL2_Pin,
+    PATH_EN_1_8G_UL_GPIO_Port,
+    PATH_EN_1_8G_UL_Pin,    
+};
+ATTEN_Setting_st Atten_1_8Ghz_UL3 ={
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_1_8G_UL3_GPIO_Port,    
+    ATT_EN_1_8G_UL3_Pin,
+    PATH_EN_1_8G_UL_GPIO_Port,
+    PATH_EN_1_8G_UL_Pin,    
+};
+ATTEN_Setting_st Atten_1_8Ghz_UL4 ={
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_1_8G_UL4_GPIO_Port,    
+    ATT_EN_1_8G_UL4_Pin,
+    PATH_EN_1_8G_UL_GPIO_Port,
+    PATH_EN_1_8G_UL_Pin,    
+};
+ATTEN_Setting_st Atten_2_1Ghz_DL1 ={
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_2_1G_DL1_GPIO_Port,    
+    ATT_EN_2_1G_DL1_Pin,
+    PATH_EN_2_1G_DL_GPIO_Port,
+    PATH_EN_2_1G_DL_Pin,    
+};
+ATTEN_Setting_st Atten_2_1Ghz_DL2 ={
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_2_1G_DL2_GPIO_Port,    
+    ATT_EN_2_1G_DL2_Pin,
+    PATH_EN_2_1G_DL_GPIO_Port,
+    PATH_EN_2_1G_DL_Pin,    
+};
+
+ATTEN_Setting_st Atten_2_1Ghz_UL1 ={
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_2_1G_UL1_GPIO_Port,    
+    ATT_EN_2_1G_UL1_Pin,
+    PATH_EN_2_1G_UL_GPIO_Port,
+    PATH_EN_2_1G_UL_Pin,    
+};
+ATTEN_Setting_st Atten_2_1Ghz_UL2 ={
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_2_1G_UL2_GPIO_Port,    
+    ATT_EN_2_1G_UL2_Pin,
+    PATH_EN_2_1G_UL_GPIO_Port,
+    PATH_EN_2_1G_UL_Pin,    
+};
+ATTEN_Setting_st Atten_2_1Ghz_UL3 ={
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_2_1G_UL3_GPIO_Port,    
+    ATT_EN_2_1G_UL3_Pin,
+    PATH_EN_2_1G_UL_GPIO_Port,
+    PATH_EN_2_1G_UL_Pin,    
+};
+ATTEN_Setting_st Atten_2_1Ghz_UL4 ={
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_2_1G_UL4_GPIO_Port,    
+    ATT_EN_2_1G_UL4_Pin,
+    PATH_EN_2_1G_UL_GPIO_Port,
+    PATH_EN_2_1G_UL_Pin,    
+};
+typedef enum {
+    TYPE_BLUECELL_RESET = 0,
+    TYPE_BLUECELL_SET   = 1,
+    TYPE_BLUECELL_GET   = 2,
+}Bluecell_Prot_t;
+
+
+
+bool RF_Data_Check(uint8_t* data_buf){
+    bool ret = false;
+    bool crcret = STH30_CheckCrc(&data_buf[Type], data_buf[Length], data_buf[data_buf[Crcindex]]);
+    if(data_buf[Header] == BLUECELL_HEADER){ /*HEADER CHECK*/
+        ret= true;
+    }
+    if(crcret == true){/*CRC CHECK*/
+        ret = true;
+    }else{
+        ret = false;
+        printf("Recv CRC Value : \"%d\"\r\n Create CRC Value : \"%d\"   \r\n",data_buf[data_buf[Crcindex]],STH30_CreateCrc(&data_buf[Type], data_buf[Length]));
+    }
+    printf("CRC Result : \"%d\"   \r\n",ret);
+
+    return ret;
+
+}
+bool RF_Ctrl_Main(uint8_t* data_buf){
+    bool ret = false;
+    Bluecell_Prot_t type = data_buf[Type];
+    ret = RF_Data_Check(&data_buf[Header]); /* ERROR CHECK */
+    if(ret == false)
+        return ret;
+
+    
+    switch(type){
+    case TYPE_BLUECELL_RESET:
+#ifdef DEBUG_PRINT // PYJ.2019.07.27_BEGIN -- 
+        for(uint8_t i =0 ; i < data_buf[Length] + 6; i++)
+            printf("%02x ",data_buf[i]);
+        printf("Reset Start \r\n");
+#endif // PYJ.2019.07.27_END -- 
+        NVIC_SystemReset();
+        break;
+    case TYPE_BLUECELL_SET:
+#ifdef DEBUG_PRINT // PYJ.2019.07.27_BEGIN --     
+    printf("TYPE_BLUECELL_SET : ");
+    for(uint8_t i =0 ; i < data_buf[Length] - 1; i++)
+        printf("%02x ",data_buf[4 + i]);
+#endif
+        ADF4153_Freq_Calc(3461500000,40000000,2,5000);
+
+        ADF4153_Freq_Calc(3938000000,40000000,2,5000);
+        halSynSetFreq(1995000000);
+        break;
+    case TYPE_BLUECELL_GET:
+        
+        break;
+ 
+        default:
+#ifdef DEBUG_PRINT // PYJ.2019.07.27_BEGIN --         
+            printf("Function : %s   LINE : %d    type : %d \r\n",__func__,__LINE__,type);
+#endif
+            break;
+    }
+    return ret;
+}

insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/zig_operate(6583).h

@@ -0,0 +1,22 @@
+/*
+ * zig_operate.h
+ *
+ *  Created on: 2019. 7. 26.
+ *      Author: parkyj
+ */
+
+#ifndef ZIG_OPERATE_H_
+#define ZIG_OPERATE_H_
+#include "main.h"
+bool RF_Ctrl_Main(uint8_t* data_buf);
+
+
+typedef enum{
+    Header = 0,
+    Type,
+    Length,
+    Crcindex,
+}Bluecell_Prot_p;
+
+
+#endif /* ZIG_OPERATE_H_ */

insight/STM32F103_ATTEN_PLL_Zig.si4project/STM32F103_ATTEN_PLL_Zig.SearchResults

@@ -1,5 +1,2 @@
----- printf("1"); Matches (4 in 2 files) ----
-ADF4153_Freq_Calc in adf4153.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :             printf("1");
-ADF4153_Freq_Calc in adf4153.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :             printf("1");
-ADF4153_Freq_Calc in adf4153.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :             printf("1");
-ADF4113_Module_Ctrl in pll_4113.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :              printf("1");
+---- YJ : R3 : Matches (1 in 1 files) ----
+ADF4153_Module_Ctrl in adf4153.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :     printf("YJ : R3 : %x ",R3);