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ZIG 3.5G HIGH 수정 할 수 있도록 변경

Charge pump는 0.xx mA 가 가장 좋은 EVM 을 표시한다.
R2의 14C2를 기준으로 코딩 하면 될 것같다.
YJ 5 lat temu
rodzic
commit
aeab2ce005
100 zmienionych plików z 8819 dodań i 6075 usunięć
  1. BIN
      Debug/STM32F103_ATTEN_PLL_Zig.binary
  2. BIN
      Debug/STM32F103_ATTEN_PLL_Zig.elf
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      Debug/STM32F103_ATTEN_PLL_Zig.hex
  4. 4876 4892
      Debug/STM32F103_ATTEN_PLL_Zig.list
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      Debug/STM32F103_ATTEN_PLL_Zig.map
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      Debug/STM32F103_ATTEN_PLL_Zig_DAC.binary
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      Debug/Src/adf4153.o
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      Debug/Src/zig_operate.o
  9. 1 1
      Debug/Src/zig_operate.su
  10. 4 0
      Inc/adf4153.h
  11. 6 5
      Src/zig_operate.c
  12. 74 0
      insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/adf4153(1821).h
  13. 74 0
      insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/adf4153(4208).h
  14. 440 0
      insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/adf4153(7343).c
  15. 655 0
      insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/main(4289).c
  16. 757 0
      insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/zig_operate(3458).c
  17. 757 0
      insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/zig_operate(674).c
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      insight/STM32F103_ATTEN_PLL_Zig.si4project/STM32F103_ATTEN_PLL_Zig.sip_sym
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      insight/STM32F103_ATTEN_PLL_Zig.si4project/STM32F103_ATTEN_PLL_Zig.sip_xab
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      insight/STM32F103_ATTEN_PLL_Zig.si4project/STM32F103_ATTEN_PLL_Zig.sip_xad
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      insight/STM32F103_ATTEN_PLL_Zig.si4project/STM32F103_ATTEN_PLL_Zig.sip_xc
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      insight/STM32F103_ATTEN_PLL_Zig.si4project/STM32F103_ATTEN_PLL_Zig.sip_xf
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      insight/STM32F103_ATTEN_PLL_Zig.si4project/STM32F103_ATTEN_PLL_Zig.sip_xr
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      insight/STM32F103_ATTEN_PLL_Zig.si4project/STM32F103_ATTEN_PLL_Zig.sip_xsb
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      insight/STM32F103_ATTEN_PLL_Zig.si4project/STM32F103_ATTEN_PLL_Zig.sip_xsd
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      insight/STM32F103_ATTEN_PLL_Zig.si4project/STM32F103_ATTEN_PLL_Zig.siwork
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      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Device_ST_STM32F1xx_Include_stm32f103xe.h.sisc
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      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Device_ST_STM32F1xx_Include_stm32f1xx.h.sisc
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      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Device_ST_STM32F1xx_Include_system_stm32f1xx.h.sisc
  30. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_arm_common_tables.h.sisc
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      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_arm_const_structs.h.sisc
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      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_arm_math.h.sisc
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      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_cmsis_armcc.h.sisc
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      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_cmsis_armcc_V6.h.sisc
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      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_cmsis_gcc.h.sisc
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      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_core_cm0.h.sisc
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      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_core_cm0plus.h.sisc
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      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_core_cm3.h.sisc
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      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_core_cm4.h.sisc
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      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_core_cm7.h.sisc
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      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_core_cmFunc.h.sisc
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      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_core_cmInstr.h.sisc
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      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_core_cmSimd.h.sisc
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      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_core_sc000.h.sisc
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      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_core_sc300.h.sisc
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      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_Legacy_stm32_hal_legacy.h.sisc
  47. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal.h.sisc
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      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_adc.h.sisc
  49. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_adc_ex.h.sisc
  50. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_cortex.h.sisc
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      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_def.h.sisc
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      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_dma.h.sisc
  53. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_dma_ex.h.sisc
  54. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_exti.h.sisc
  55. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_flash.h.sisc
  56. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_flash_ex.h.sisc
  57. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_gpio.h.sisc
  58. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_gpio_ex.h.sisc
  59. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_pwr.h.sisc
  60. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_rcc.h.sisc
  61. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_rcc_ex.h.sisc
  62. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_tim.h.sisc
  63. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_tim_ex.h.sisc
  64. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_uart.h.sisc
  65. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal.c.sisc
  66. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_adc.c.sisc
  67. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_adc_ex.c.sisc
  68. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_cortex.c.sisc
  69. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_dma.c.sisc
  70. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_exti.c.sisc
  71. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_flash.c.sisc
  72. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_flash_ex.c.sisc
  73. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_gpio.c.sisc
  74. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_gpio_ex.c.sisc
  75. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_pwr.c.sisc
  76. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_rcc.c.sisc
  77. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_rcc_ex.c.sisc
  78. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_tim.c.sisc
  79. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_tim_ex.c.sisc
  80. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_uart.c.sisc
  81. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_AD5318.h.sisc
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      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_BDA4601.h.sisc
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      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_CRC16.h.sisc
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      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_PE43711.h.sisc
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      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_adf4153.h.sisc
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      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_flash.h.sisc
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      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_AD5318.c.sisc
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      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_BDA4601.c.sisc
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      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_CRC16.c.sisc
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      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_PE43711.c.sisc
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      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_adf4153.c.sisc
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      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_flash.c.sisc

BIN
Debug/STM32F103_ATTEN_PLL_Zig.binary


BIN
Debug/STM32F103_ATTEN_PLL_Zig.elf


Plik diff jest za duży
+ 898 - 900
Debug/STM32F103_ATTEN_PLL_Zig.hex


Plik diff jest za duży
+ 4876 - 4892
Debug/STM32F103_ATTEN_PLL_Zig.list


+ 277 - 277
Debug/STM32F103_ATTEN_PLL_Zig.map

@@ -1303,7 +1303,7 @@ LOAD c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../l
1303 1303
                 0x08004000                g_pfnVectors
1304 1304
                 0x080041e4                . = ALIGN (0x4)
1305 1305
 
1306
-.text           0x080041e8     0x7db4
1306
+.text           0x080041e8     0x7d94
1307 1307
                 0x080041e8                . = ALIGN (0x4)
1308 1308
  *(.text)
1309 1309
  .text          0x080041e8       0x40 c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/armv7-m/crtbegin.o
@@ -1798,361 +1798,361 @@ LOAD c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../l
1798 1798
                 0x08008af0       0x38 Src\zig_operate.o
1799 1799
                 0x08008af0                RF_Status_Ack
1800 1800
  .text.RF_Operate
1801
-                0x08008b28      0xa3c Src\zig_operate.o
1801
+                0x08008b28      0xa1c Src\zig_operate.o
1802 1802
                 0x08008b28                RF_Operate
1803 1803
  .text.RF_Ctrl_Main
1804
-                0x08009564       0x9c Src\zig_operate.o
1805
-                0x08009564                RF_Ctrl_Main
1804
+                0x08009544       0x9c Src\zig_operate.o
1805
+                0x08009544                RF_Ctrl_Main
1806 1806
  .text.Reset_Handler
1807
-                0x08009600       0x48 startup\startup_stm32f103xe.o
1808
-                0x08009600                Reset_Handler
1807
+                0x080095e0       0x48 startup\startup_stm32f103xe.o
1808
+                0x080095e0                Reset_Handler
1809 1809
  .text.Default_Handler
1810
-                0x08009648        0x2 startup\startup_stm32f103xe.o
1811
-                0x08009648                RTC_Alarm_IRQHandler
1812
-                0x08009648                EXTI2_IRQHandler
1813
-                0x08009648                TIM8_TRG_COM_IRQHandler
1814
-                0x08009648                TIM8_CC_IRQHandler
1815
-                0x08009648                TIM1_CC_IRQHandler
1816
-                0x08009648                PVD_IRQHandler
1817
-                0x08009648                SDIO_IRQHandler
1818
-                0x08009648                EXTI3_IRQHandler
1819
-                0x08009648                EXTI0_IRQHandler
1820
-                0x08009648                I2C2_EV_IRQHandler
1821
-                0x08009648                ADC1_2_IRQHandler
1822
-                0x08009648                SPI1_IRQHandler
1823
-                0x08009648                TAMPER_IRQHandler
1824
-                0x08009648                TIM8_UP_IRQHandler
1825
-                0x08009648                DMA2_Channel2_IRQHandler
1826
-                0x08009648                USART3_IRQHandler
1827
-                0x08009648                RTC_IRQHandler
1828
-                0x08009648                DMA1_Channel7_IRQHandler
1829
-                0x08009648                CAN1_RX1_IRQHandler
1830
-                0x08009648                UART5_IRQHandler
1831
-                0x08009648                ADC3_IRQHandler
1832
-                0x08009648                TIM4_IRQHandler
1833
-                0x08009648                DMA2_Channel1_IRQHandler
1834
-                0x08009648                I2C1_EV_IRQHandler
1835
-                0x08009648                DMA1_Channel6_IRQHandler
1836
-                0x08009648                UART4_IRQHandler
1837
-                0x08009648                TIM3_IRQHandler
1838
-                0x08009648                RCC_IRQHandler
1839
-                0x08009648                TIM1_TRG_COM_IRQHandler
1840
-                0x08009648                Default_Handler
1841
-                0x08009648                EXTI15_10_IRQHandler
1842
-                0x08009648                TIM7_IRQHandler
1843
-                0x08009648                TIM5_IRQHandler
1844
-                0x08009648                EXTI9_5_IRQHandler
1845
-                0x08009648                SPI2_IRQHandler
1846
-                0x08009648                EXTI4_IRQHandler
1847
-                0x08009648                USB_LP_CAN1_RX0_IRQHandler
1848
-                0x08009648                USB_HP_CAN1_TX_IRQHandler
1849
-                0x08009648                DMA1_Channel3_IRQHandler
1850
-                0x08009648                FSMC_IRQHandler
1851
-                0x08009648                TIM1_UP_IRQHandler
1852
-                0x08009648                WWDG_IRQHandler
1853
-                0x08009648                TIM2_IRQHandler
1854
-                0x08009648                TIM1_BRK_IRQHandler
1855
-                0x08009648                EXTI1_IRQHandler
1856
-                0x08009648                DMA2_Channel4_5_IRQHandler
1857
-                0x08009648                USART2_IRQHandler
1858
-                0x08009648                I2C2_ER_IRQHandler
1859
-                0x08009648                DMA1_Channel2_IRQHandler
1860
-                0x08009648                TIM8_BRK_IRQHandler
1861
-                0x08009648                CAN1_SCE_IRQHandler
1862
-                0x08009648                FLASH_IRQHandler
1863
-                0x08009648                SPI3_IRQHandler
1864
-                0x08009648                I2C1_ER_IRQHandler
1865
-                0x08009648                USBWakeUp_IRQHandler
1866
-                0x08009648                DMA2_Channel3_IRQHandler
1867
- *fill*         0x0800964a        0x2 
1868
- .text.__errno  0x0800964c        0xc c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/../../../../arm-atollic-eabi/lib/armv7-m\libc_nano.a(lib_a-errno.o)
1869
-                0x0800964c                __errno
1810
+                0x08009628        0x2 startup\startup_stm32f103xe.o
1811
+                0x08009628                RTC_Alarm_IRQHandler
1812
+                0x08009628                EXTI2_IRQHandler
1813
+                0x08009628                TIM8_TRG_COM_IRQHandler
1814
+                0x08009628                TIM8_CC_IRQHandler
1815
+                0x08009628                TIM1_CC_IRQHandler
1816
+                0x08009628                PVD_IRQHandler
1817
+                0x08009628                SDIO_IRQHandler
1818
+                0x08009628                EXTI3_IRQHandler
1819
+                0x08009628                EXTI0_IRQHandler
1820
+                0x08009628                I2C2_EV_IRQHandler
1821
+                0x08009628                ADC1_2_IRQHandler
1822
+                0x08009628                SPI1_IRQHandler
1823
+                0x08009628                TAMPER_IRQHandler
1824
+                0x08009628                TIM8_UP_IRQHandler
1825
+                0x08009628                DMA2_Channel2_IRQHandler
1826
+                0x08009628                USART3_IRQHandler
1827
+                0x08009628                RTC_IRQHandler
1828
+                0x08009628                DMA1_Channel7_IRQHandler
1829
+                0x08009628                CAN1_RX1_IRQHandler
1830
+                0x08009628                UART5_IRQHandler
1831
+                0x08009628                ADC3_IRQHandler
1832
+                0x08009628                TIM4_IRQHandler
1833
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1837
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1848
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1849
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1860
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1864
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1866
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1869
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1889 1889
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1944
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1945
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1946
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1947
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1948
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1949
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1950
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1941
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1942
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1943
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1944
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1945
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1946
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1947
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1948
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1949
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1950
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1951 1951
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1952
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1953
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1952
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1953
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1954 1954
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1955
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1956
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1955
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1956
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1957 1957
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1958
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1959
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1960
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1961
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1958
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1959
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1960
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1961
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1962 1962
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1963
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1964
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1965
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1963
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1964
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1965
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1966 1966
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1967
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1968
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1967
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1968
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1969 1969
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1970
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1971
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1972
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1973
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1974
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1975
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1976
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1977
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1970
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1971
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1972
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1973
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1974
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1975
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1976
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1977
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1978 1978
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1979
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1980
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1981
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1982
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1983
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1979
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1980
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1981
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1982
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1983
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1984 1984
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1985
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1986
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1985
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1986
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1987 1987
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1988
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1988
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1989 1989
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1990
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1991
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1990
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1991
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1992 1992
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1993
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1994
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1995
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1996
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1997
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1998
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1999
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1993
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1994
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1995
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1996
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1997
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1998
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1999
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2000 2000
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2001
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2002
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2003
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2004
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2001
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2002
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2003
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2004
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2005 2005
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2006
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2007
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2008
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2006
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2007
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2009 2009
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2010
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2011
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2010
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2011
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2012 2012
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2013
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2014
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2013
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2014
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2015 2015
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2016
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2017
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2016
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2017
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2018 2018
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2019
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2020
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2020
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2021 2021
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2022
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2023
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2024 2024
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-                0x0800c2d8                PROVIDE (__preinit_array_start, .)
2135
+.preinit_array  0x0800c2b8        0x0
2136
+                0x0800c2b8                PROVIDE (__preinit_array_start, .)
2137 2137
  *(.preinit_array*)
2138
-                0x0800c2d8                PROVIDE (__preinit_array_end, .)
2138
+                0x0800c2b8                PROVIDE (__preinit_array_end, .)
2139 2139
 
2140
-.init_array     0x0800c2d8        0x4
2141
-                0x0800c2d8                PROVIDE (__init_array_start, .)
2140
+.init_array     0x0800c2b8        0x4
2141
+                0x0800c2b8                PROVIDE (__init_array_start, .)
2142 2142
  *(SORT(.init_array.*))
2143 2143
  *(.init_array*)
2144
- .init_array    0x0800c2d8        0x4 c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/armv7-m/crtbegin.o
2145
-                0x0800c2dc                PROVIDE (__init_array_end, .)
2144
+ .init_array    0x0800c2b8        0x4 c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/armv7-m/crtbegin.o
2145
+                0x0800c2bc                PROVIDE (__init_array_end, .)
2146 2146
 
2147
-.fini_array     0x0800c2dc        0x4
2147
+.fini_array     0x0800c2bc        0x4
2148 2148
                 [!provide]                PROVIDE (__fini_array_start, .)
2149 2149
  *(SORT(.fini_array.*))
2150 2150
  *(.fini_array*)
2151
- .fini_array    0x0800c2dc        0x4 c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/armv7-m/crtbegin.o
2151
+ .fini_array    0x0800c2bc        0x4 c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/armv7-m/crtbegin.o
2152 2152
                 [!provide]                PROVIDE (__fini_array_end, .)
2153
-                0x0800c2e0                _sidata = LOADADDR (.data)
2153
+                0x0800c2c0                _sidata = LOADADDR (.data)
2154 2154
 
2155
-.data           0x20000000      0x41c load address 0x0800c2e0
2155
+.data           0x20000000      0x41c load address 0x0800c2c0
2156 2156
                 0x20000000                . = ALIGN (0x4)
2157 2157
                 0x20000000                _sdata = .
2158 2158
  *(.data)
@@ -2250,11 +2250,11 @@ LOAD c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../l
2250 2250
                 0x2000041c                . = ALIGN (0x4)
2251 2251
                 0x2000041c                _edata = .
2252 2252
 
2253
-.igot.plt       0x2000041c        0x0 load address 0x0800c6fc
2253
+.igot.plt       0x2000041c        0x0 load address 0x0800c6dc
2254 2254
  .igot.plt      0x2000041c        0x0 c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/armv7-m/crtbegin.o
2255 2255
                 0x2000041c                . = ALIGN (0x4)
2256 2256
 
2257
-.bss            0x20000420     0x13c4 load address 0x0800c6fc
2257
+.bss            0x20000420     0x13c4 load address 0x0800c6dc
2258 2258
                 0x20000420                _sbss = .
2259 2259
                 0x20000420                __bss_start__ = _sbss
2260 2260
  *(.bss)
@@ -2320,7 +2320,7 @@ LOAD c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../l
2320 2320
                 0x200017e4                __bss_end__ = _ebss
2321 2321
 
2322 2322
 ._user_heap_stack
2323
-                0x200017e4      0x600 load address 0x0800c6fc
2323
+                0x200017e4      0x600 load address 0x0800c6dc
2324 2324
                 0x200017e4                . = ALIGN (0x4)
2325 2325
                 0x200017e4                PROVIDE (end, .)
2326 2326
                 [!provide]                PROVIDE (_end, .)
@@ -2514,7 +2514,7 @@ LOAD c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../l
2514 2514
                 0x00000ec4       0x1d c:/program files (x86)/atollic/truestudio for stm32 9.3.0/armtools/bin/../lib/gcc/arm-atollic-eabi/6.3.1/armv7-m/crtn.o
2515 2515
 OUTPUT(STM32F103_ATTEN_PLL_Zig.elf elf32-littlearm)
2516 2516
 
2517
-.debug_info     0x00000000    0x25596
2517
+.debug_info     0x00000000    0x2556e
2518 2518
  .debug_info    0x00000000     0x102e Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal.o
2519 2519
  .debug_info    0x0000102e     0x16a1 Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_adc.o
2520 2520
  .debug_info    0x000026cf     0x138b Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_adc_ex.o
@@ -2542,8 +2542,8 @@ OUTPUT(STM32F103_ATTEN_PLL_Zig.elf elf32-littlearm)
2542 2542
  .debug_info    0x00020415      0xfe1 Src\syscalls.o
2543 2543
  .debug_info    0x000213f6      0xc4d Src\system_stm32f1xx.o
2544 2544
  .debug_info    0x00022043     0x141e Src\uart.o
2545
- .debug_info    0x00023461     0x20c4 Src\zig_operate.o
2546
- .debug_info    0x00025525       0x71 startup\startup_stm32f103xe.o
2545
+ .debug_info    0x00023461     0x209c Src\zig_operate.o
2546
+ .debug_info    0x000254fd       0x71 startup\startup_stm32f103xe.o
2547 2547
 
2548 2548
 .debug_abbrev   0x00000000     0x5046
2549 2549
  .debug_abbrev  0x00000000      0x315 Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal.o
@@ -2576,7 +2576,7 @@ OUTPUT(STM32F103_ATTEN_PLL_Zig.elf elf32-littlearm)
2576 2576
  .debug_abbrev  0x00004cdd      0x357 Src\zig_operate.o
2577 2577
  .debug_abbrev  0x00005034       0x12 startup\startup_stm32f103xe.o
2578 2578
 
2579
-.debug_loc      0x00000000     0x9d6a
2579
+.debug_loc      0x00000000     0x9d58
2580 2580
  .debug_loc     0x00000000      0x11b Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal.o
2581 2581
  .debug_loc     0x0000011b      0x87e Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_adc.o
2582 2582
  .debug_loc     0x00000999      0x769 Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_adc_ex.o
@@ -2603,7 +2603,7 @@ OUTPUT(STM32F103_ATTEN_PLL_Zig.elf elf32-littlearm)
2603 2603
  .debug_loc     0x00009358      0x3ef Src\syscalls.o
2604 2604
  .debug_loc     0x00009747       0xcd Src\system_stm32f1xx.o
2605 2605
  .debug_loc     0x00009814      0x113 Src\uart.o
2606
- .debug_loc     0x00009927      0x443 Src\zig_operate.o
2606
+ .debug_loc     0x00009927      0x431 Src\zig_operate.o
2607 2607
 
2608 2608
 .debug_aranges  0x00000000      0xe38
2609 2609
  .debug_aranges
@@ -2696,7 +2696,7 @@ OUTPUT(STM32F103_ATTEN_PLL_Zig.elf elf32-littlearm)
2696 2696
  .debug_ranges  0x000011b0       0x48 Src\zig_operate.o
2697 2697
  .debug_ranges  0x000011f8       0x20 startup\startup_stm32f103xe.o
2698 2698
 
2699
-.debug_line     0x00000000     0x9908
2699
+.debug_line     0x00000000     0x9906
2700 2700
  .debug_line    0x00000000      0x45f Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal.o
2701 2701
  .debug_line    0x0000045f      0x863 Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_adc.o
2702 2702
  .debug_line    0x00000cc2      0x737 Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_adc_ex.o
@@ -2724,8 +2724,8 @@ OUTPUT(STM32F103_ATTEN_PLL_Zig.elf elf32-littlearm)
2724 2724
  .debug_line    0x000088c7      0x3c0 Src\syscalls.o
2725 2725
  .debug_line    0x00008c87      0x2bf Src\system_stm32f1xx.o
2726 2726
  .debug_line    0x00008f46      0x3c6 Src\uart.o
2727
- .debug_line    0x0000930c      0x57f Src\zig_operate.o
2728
- .debug_line    0x0000988b       0x7d startup\startup_stm32f103xe.o
2727
+ .debug_line    0x0000930c      0x57d Src\zig_operate.o
2728
+ .debug_line    0x00009889       0x7d startup\startup_stm32f103xe.o
2729 2729
 
2730 2730
 .debug_str      0x00000000     0x58a5
2731 2731
  .debug_str     0x00000000      0xc6c Drivers\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal.o

BIN
Debug/STM32F103_ATTEN_PLL_Zig_DAC.binary


BIN
Debug/Src/adf4153.o


BIN
Debug/Src/zig_operate.o


+ 1 - 1
Debug/Src/zig_operate.su

@@ -2,4 +2,4 @@ zig_operate.c:201:6:RF_Data_Check	8	static
2 2
 zig_operate.c:234:6:RF_Status_Get	8	static
3 3
 zig_operate.c:248:6:RF_Status_Ack	8	static
4 4
 zig_operate.c:262:6:RF_Operate	184	static
5
-zig_operate.c:707:6:RF_Ctrl_Main	16	static
5
+zig_operate.c:708:6:RF_Ctrl_Main	16	static

+ 4 - 0
Inc/adf4153.h

@@ -49,9 +49,13 @@
49 49
 
50 50
 #define ADF4153_40MHzREFIN 40000000
51 51
 #define ADF4153_61_44MHzREFIN 61440000
52
+#define ADF4153_122_88MHzREFIN (ADF4153_61_44MHzREFIN * 2)
53
+
52 54
 
53 55
 #define ADF4153_2RCOUNTER 2
54 56
 #define ADF4153_4RCOUNTER 4
57
+#define ADF4153_8RCOUNTER 8
58
+
55 59
 
56 60
 #define ADF4153_CHANNEL_SPACING 5000
57 61
 

+ 6 - 5
Src/zig_operate.c

@@ -419,7 +419,7 @@ void RF_Operate(uint8_t* data_buf){
419 419
 #else
420 420
         temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
421 421
 #endif // PYJ.2019.08.12_END -- 
422
-        ADF4153_Module_Ctrl(Pll_3_5_H,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
422
+//        ADF4153_Module_Ctrl(Pll_3_5_H,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
423 423
 
424 424
     }
425 425
     if(Prev_data[INDEX_PLL_LD_6_BIT] != data_buf[INDEX_PLL_LD_6_BIT]){
@@ -577,12 +577,13 @@ void RF_Operate(uint8_t* data_buf){
577 577
 
578 578
 
579 579
 //            temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
580
-            temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
581
-
580
+            temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_122_88MHzREFIN,ADF4153_8RCOUNTER,ADF4153_CHANNEL_SPACING);
582 581
 #else
583 582
             temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
584 583
 #endif // PYJ.2019.08.12_END -- 
585
-            ADF4153_Module_Ctrl(Pll_3_5_H,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
584
+//            ADF4153_Module_Ctrl(Pll_3_5_H,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
585
+            ADF4153_Module_Ctrl(Pll_3_5_H,0x4006C0,0x163001,0x1642,3);
586
+
586 587
             PE43711_ALL_atten_ctrl(ALL_ATT_3_5G);
587 588
         }
588 589
     }
@@ -600,8 +601,8 @@ void RF_Operate(uint8_t* data_buf){
600 601
             temp_val = (Prev_data[INDEX_PLL_3_5G_LOW_H] << 16) |
601 602
                        (Prev_data[INDEX_PLL_3_5G_LOW_M] << 8) | 
602 603
                        (Prev_data[INDEX_PLL_3_5G_LOW_L]);
603
-//            temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
604 604
             temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
605
+//            temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_122_88MHzREFIN,ADF4153_8RCOUNTER,ADF4153_CHANNEL_SPACING);
605 606
 #else
606 607
           temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);            
607 608
 #endif // PYJ.2019.08.12_END -- 

+ 74 - 0
insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/adf4153(1821).h

@@ -0,0 +1,74 @@
1
+/**************************************************************************//**
2
+*   @file   adf4153.h
3
+*   @brief  Header file of adf4153 driver.
4
+*
5
+*   @author Istvan Csomortani (istvan.csomortani@analog.com)
6
+*
7
+*******************************************************************************
8
+* Copyright 2013(c) Analog Devices, Inc.
9
+*
10
+* All rights reserved.
11
+*
12
+* Redistribution and use in source and binary forms, with or without modification,
13
+* are permitted provided that the following conditions are met:
14
+*  - Redistributions of source code must retain the above copyright
15
+*    notice, this list of conditions and the following disclaimer.
16
+*  - Redistributions in binary form must reproduce the above copyright
17
+*    notice, this list of conditions and the following disclaimer in
18
+*    the documentation and/or other materials provided with the
19
+*    distribution.
20
+*  - Neither the name of Analog Devices, Inc. nor the names of its
21
+*    contributors may be used to endorse or promote products derived
22
+*    from this software without specific prior written permission.
23
+*  - The use of this software may or may not infringe the patent rights
24
+*    of one or more patent holders.  This license does not release you
25
+*    from the requirement that you obtain separate licenses from these
26
+*    patent holders to use this software.
27
+*  - Use of the software either in source or binary form, must be run
28
+*    on or directly connected to an Analog Devices Inc. component.
29
+*
30
+* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED
31
+* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY
32
+* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
33
+* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
35
+* INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
36
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
37
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
39
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40
+*
41
+******************************************************************************/
42
+#ifndef __ADF4153_H__
43
+#define __ADF4153_H__
44
+
45
+//#include "main.h"
46
+
47
+#include "main.h"
48
+#include "pll_4113.h"
49
+
50
+#define ADF4153_40MHzREFIN 40000000
51
+#define ADF4153_61_44MHzREFIN 61440000
52
+
53
+#define ADF4153_2RCOUNTER 2
54
+#define ADF4153_4RCOUNTER 4
55
+
56
+#define ADF4153_CHANNEL_SPACING 5000
57
+
58
+
59
+typedef struct {
60
+    uint32_t R_reg;
61
+    uint32_t N_reg;
62
+}ADF4153_R_N_Reg_st;
63
+
64
+//void ADF4153_Freq_Calc(unsigned long long Freq,unsigned long long REFin,uint8_t R_Counter,uint32_t chspacing);
65
+
66
+
67
+//void ADF4153_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2,uint32_t R3);
68
+void ADF4153_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2,uint32_t R3);
69
+ADF4153_R_N_Reg_st ADF4153_Freq_Calc(unsigned long long Freq,unsigned long long REFin,uint8_t R_Counter,uint32_t chspacing);
70
+void ADF4153_Initialize(void);
71
+void ADF4153_Check(void);
72
+
73
+
74
+#endif // __ADF4153_H__

+ 74 - 0
insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/adf4153(4208).h

@@ -0,0 +1,74 @@
1
+/**************************************************************************//**
2
+*   @file   adf4153.h
3
+*   @brief  Header file of adf4153 driver.
4
+*
5
+*   @author Istvan Csomortani (istvan.csomortani@analog.com)
6
+*
7
+*******************************************************************************
8
+* Copyright 2013(c) Analog Devices, Inc.
9
+*
10
+* All rights reserved.
11
+*
12
+* Redistribution and use in source and binary forms, with or without modification,
13
+* are permitted provided that the following conditions are met:
14
+*  - Redistributions of source code must retain the above copyright
15
+*    notice, this list of conditions and the following disclaimer.
16
+*  - Redistributions in binary form must reproduce the above copyright
17
+*    notice, this list of conditions and the following disclaimer in
18
+*    the documentation and/or other materials provided with the
19
+*    distribution.
20
+*  - Neither the name of Analog Devices, Inc. nor the names of its
21
+*    contributors may be used to endorse or promote products derived
22
+*    from this software without specific prior written permission.
23
+*  - The use of this software may or may not infringe the patent rights
24
+*    of one or more patent holders.  This license does not release you
25
+*    from the requirement that you obtain separate licenses from these
26
+*    patent holders to use this software.
27
+*  - Use of the software either in source or binary form, must be run
28
+*    on or directly connected to an Analog Devices Inc. component.
29
+*
30
+* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED
31
+* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY
32
+* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
33
+* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
35
+* INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
36
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
37
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
39
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40
+*
41
+******************************************************************************/
42
+#ifndef __ADF4153_H__
43
+#define __ADF4153_H__
44
+
45
+//#include "main.h"
46
+
47
+#include "main.h"
48
+#include "pll_4113.h"
49
+
50
+#define ADF4153_40MHzREFIN 40000000
51
+#define ADF4153_61_44MHzREFIN 61440000
52
+
53
+#define ADF4153_2RCOUNTER 2
54
+#define ADF4153_4RCOUNTER 4
55
+
56
+#define ADF4153_CHANNEL_SPACING 5000
57
+
58
+
59
+typedef struct {
60
+    uint32_t R_reg;
61
+    uint32_t N_reg;
62
+}ADF4153_R_N_Reg_st;
63
+
64
+//void ADF4153_Freq_Calc(unsigned long long Freq,unsigned long long REFin,uint8_t R_Counter,uint32_t chspacing);
65
+
66
+
67
+//void ADF4153_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2,uint32_t R3);
68
+void ADF4153_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2,uint32_t R3);
69
+ADF4153_R_N_Reg_st ADF4153_Freq_Calc(unsigned long long Freq,unsigned long long REFin,uint8_t R_Counter,uint32_t chspacing);
70
+void ADF4153_Initialize(void);
71
+void ADF4153_Check(void);
72
+
73
+
74
+#endif // __ADF4153_H__

+ 440 - 0
insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/adf4153(7343).c

@@ -0,0 +1,440 @@
1
+/******************************************************************************
2
+*   @file   ADF4153.c
3
+*   @brief  Implementation of ADF4153 Driver for Microblaze processor.
4
+*   @author Istvan Csomortani (istvan.csomortani@analog.com)
5
+*
6
+*******************************************************************************
7
+* Copyright 2013(c) Analog Devices, Inc.
8
+*
9
+* All rights reserved.
10
+*
11
+* Redistribution and use in source and binary forms, with or without modification,
12
+* are permitted provided that the following conditions are met:
13
+*  - Redistributions of source code must retain the above copyright
14
+*    notice, this list of conditions and the following disclaimer.
15
+*  - Redistributions in binary form must reproduce the above copyright
16
+*    notice, this list of conditions and the following disclaimer in
17
+*    the documentation and/or other materials provided with the
18
+*    distribution.
19
+*  - Neither the name of Analog Devices, Inc. nor the names of its
20
+*    contributors may be used to endorse or promote products derived
21
+*    from this software without specific prior written permission.
22
+*  - The use of this software may or may not infringe the patent rights
23
+*    of one or more patent holders.  This license does not release you
24
+*    from the requirement that you obtain separate licenses from these
25
+*    patent holders to use this software.
26
+*  - Use of the software either in source or binary form, must be run
27
+*    on or directly connected to an Analog Devices Inc. component.
28
+*
29
+* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED
30
+* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY
31
+* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
32
+* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
34
+* INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
35
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
36
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
38
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39
+*
40
+******************************************************************************/
41
+
42
+/*****************************************************************************/
43
+/****************************** Include Files ********************************/
44
+/*****************************************************************************/
45
+#include "adf4153.h"
46
+#include "zig_operate.h"
47
+#include "main.h"
48
+#include "pll_4113.h"
49
+
50
+extern void Pol_Delay_us(volatile uint32_t microseconds);
51
+typedef struct _adf4153_st{
52
+    unsigned long long PFD_Value;
53
+    uint16_t MOD_Value;
54
+    uint32_t FRAC_Value;
55
+    uint16_t INT_Value;    
56
+    double N_Value;
57
+}adf4153_st;
58
+extern PLL_Setting_st Pll_3_5_H;
59
+extern PLL_Setting_st Pll_3_5_L;
60
+
61
+uint32_t pow2(uint32_t val,int32_t val2){
62
+    for(uint8_t i = 0; i < val2 - 1; i++){
63
+        val = val * val;
64
+    }
65
+
66
+    return val;
67
+}
68
+
69
+double round_up( double value, int pos )
70
+{
71
+    double temp;
72
+    temp = value * pow2( 10, pos );  // �썝�븯�뒗 �냼�닔�젏 �옄由ъ닔留뚰겮 10�쓽 �늻�듅�쓣 �븿
73
+    temp =  (int)(temp + 0.5);          // 0.5瑜� �뜑�븳�썑 踰꾨┝�븯硫� 諛섏삱由쇱씠 �맖
74
+    temp *= pow2( 10, -pos );           // �떎�떆 �썝�옒 �냼�닔�젏 �옄由ъ닔濡�
75
+
76
+    return temp;
77
+}
78
+
79
+
80
+double N_Reg_Value_Calc(double val){
81
+    return  val / 1000;
82
+}
83
+uint32_t N_Divider_Reg_Create(uint16_t _FRAC,uint16_t _INT,uint8_t _FASTLOCK){
84
+    uint32_t ret = 0;
85
+    uint32_t shift_bit = 0x01;
86
+    uint8_t control_bit = 0;
87
+    uint8_t i = 0;
88
+#ifdef DEBUG_PRINT
89
+    printf("FRAC : %d INT : %d \r\n",(int)_FRAC,_INT);
90
+#endif /* DEBUG_PRINT */
91
+    for(i = 0; i < 2; i++){
92
+        if(control_bit & 0x01)
93
+            ret += shift_bit << i;
94
+        control_bit = control_bit >> 1;
95
+    }
96
+#ifdef DEBUG_PRINT
97
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);
98
+#endif /* DEBUG_PRINT */
99
+    for(i = 2; i < 14; i++){
100
+        if(_FRAC & 0x01)
101
+            ret += shift_bit << i;
102
+        _FRAC = _FRAC >> 1;
103
+    }
104
+#ifdef DEBUG_PRINT
105
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);    
106
+#endif /* DEBUG_PRINT */
107
+    for(i = 14; i < 22; i++){
108
+        if(_INT & 0x01)
109
+            ret += shift_bit << i;
110
+        _INT = _INT >> 1;
111
+    }  
112
+#ifdef DEBUG_PRINT
113
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);    
114
+#endif /* DEBUG_PRINT */
115
+    if(_FASTLOCK & 0x01)
116
+            ret += shift_bit << i;
117
+#ifdef DEBUG_PRINT
118
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);
119
+#endif /* DEBUG_PRINT */
120
+
121
+    return ret;
122
+}
123
+uint32_t R_Divider_Reg_Create(uint16_t _MOD,uint8_t _RCOUNTER,uint8_t _PRESCALER,uint8_t _RESERVED,uint8_t _MUXOUT,uint8_t LOAD_CONTROL){
124
+    uint32_t ret = 0;
125
+    uint32_t shift_bit = 0x01;
126
+    uint8_t control_bit = 1;
127
+    uint8_t i = 0;
128
+#ifdef DEBUG_PRINT
129
+    printf("_MOD : %d INT : %d \r\n",_MOD,_RCOUNTER);
130
+#endif /* DEBUG_PRINT */
131
+
132
+#ifdef DEBUG_PRINT
133
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);
134
+#endif /* DEBUG_PRINT */
135
+    for(i = 0; i < 2; i++){
136
+        if(control_bit & 0x01)
137
+            ret += shift_bit << i;
138
+        control_bit = control_bit >> 1;
139
+    }
140
+#ifdef DEBUG_PRINT
141
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);
142
+#endif /* DEBUG_PRINT */
143
+    for(i = 2; i < 14; i++){
144
+        if(_MOD & 0x01)
145
+            ret += shift_bit << i;
146
+        _MOD = _MOD >> 1;
147
+    }
148
+    for(i = 14; i < 18; i++){
149
+        if(_RCOUNTER & 0x01)
150
+            ret += shift_bit << i;
151
+        _RCOUNTER = _RCOUNTER >> 1;
152
+    }  
153
+    if(_PRESCALER & 0x01)
154
+            ret += shift_bit << i++;
155
+    if(_RESERVED & 0x01)
156
+            ret += shift_bit << i++;
157
+    for(i = 19; i < 22; i++){
158
+        if(_MUXOUT & 0x01)
159
+            ret += shift_bit << i;
160
+        _MUXOUT = _MUXOUT >> 1;
161
+    }   
162
+    if(LOAD_CONTROL & 0x01)
163
+        ret += shift_bit << i++;
164
+
165
+    return ret;
166
+}
167
+
168
+ADF4153_R_N_Reg_st ADF4153_Freq_Calc(unsigned long long Freq,unsigned long long REFin,uint8_t R_Counter,uint32_t chspacing){
169
+    adf4153_st temp_adf4153;
170
+    double temp = 0;
171
+    ADF4153_R_N_Reg_st temp_reg;
172
+    temp_adf4153.PFD_Value  =  REFin / (R_Counter * 1000);
173
+    temp_adf4153.MOD_Value  =  (temp_adf4153.PFD_Value / chspacing) * 1000;
174
+    temp_adf4153.N_Value    =  N_Reg_Value_Calc(((double)(Freq / 1000) /  (double)(temp_adf4153.PFD_Value / 1000)));
175
+    temp_adf4153.INT_Value  =   temp_adf4153.N_Value ;
176
+#ifdef DEBUG_PRINT
177
+    printf("\r\ntemp_adf4153.N_Value : %f  temp_adf4153.INT_Value : %f  temp_adf4153.MOD_Value : %f \r\n",temp_adf4153.N_Value,(double)temp_adf4153.INT_Value,(double)temp_adf4153.MOD_Value);
178
+#endif /* DEBUG_PRINT */
179
+    temp = temp_adf4153.N_Value - (double)temp_adf4153.INT_Value;
180
+#ifdef DEBUG_PRINT
181
+    printf("\r\n temp_adf4153.N_Value - (double)temp_adf4153.INT_Value) : %f  temp * (double)temp_adf4153.MOD_Value : %f \r\n",temp,temp * (double)temp_adf4153.MOD_Value);
182
+#endif /* DEBUG_PRINT */
183
+    temp_adf4153.FRAC_Value =  (float)temp * temp_adf4153.MOD_Value;
184
+   
185
+#ifdef DEBUG_PRINT
186
+    printf("\r\ntemp_adf4153.N_Value : %x   : %f ",temp_adf4153.N_Value,((double)(Freq / 1000) /  (double)(temp_adf4153.PFD_Value / 1000)) / 1000);
187
+    printf("temp_adf4153.MOD_Value : %x   : %d \r\n",temp_adf4153.MOD_Value,temp_adf4153.MOD_Value);
188
+#endif /* DEBUG_PRINT */
189
+    uint16_t tempmod = temp_adf4153.FRAC_Value;
190
+    for(uint8_t i = 0; i < 12; i++){
191
+#ifdef DEBUG_PRINT
192
+        if(temp_adf4153.MOD_Value & 0x800){
193
+            printf("1");
194
+        }else{
195
+            printf("0");
196
+        }
197
+#endif /* DEBUG_PRINT */
198
+        tempmod = tempmod << 1;
199
+    }
200
+#ifdef DEBUG_PRINT
201
+    printf("\r\n");
202
+    printf("temp_adf4153.FRAC_Value : %x   : %d\r\n",temp_adf4153.FRAC_Value,temp_adf4153.FRAC_Value);
203
+#endif /* DEBUG_PRINT */
204
+    uint16_t tempfrac = temp_adf4153.FRAC_Value;
205
+    for(uint8_t i = 0; i < 12; i++){
206
+#ifdef DEBUG_PRINT
207
+        if(tempfrac & 0x800){
208
+            printf("1");
209
+        }else{
210
+            printf("0");
211
+        }
212
+#endif /* DEBUG_PRINT */
213
+        tempfrac = tempfrac << 1;
214
+    }
215
+#ifdef DEBUG_PRINT
216
+    printf("\r\n");    
217
+#endif /* DEBUG_PRINT */
218
+#ifdef DEBUG_PRINT
219
+    printf("temp_adf4153.INT_Value : %x   : %d\r\n",temp_adf4153.INT_Value,temp_adf4153.INT_Value); 
220
+#endif /* DEBUG_PRINT */
221
+    uint16_t tempint = temp_adf4153.INT_Value;
222
+    for(uint8_t i = 0; i < 9; i++){
223
+#ifdef DEBUG_PRINT
224
+        if(tempint & 0x100){
225
+            printf("1");
226
+        }else{
227
+            printf("0");
228
+        }
229
+#endif /* DEBUG_PRINT */
230
+        tempint = tempint << 1;
231
+    }
232
+#ifdef DEBUG_PRINT
233
+    printf("\r\n");    
234
+
235
+    printf("R0: %x  R1: %x \r\n",N_Divider_Reg_Create(temp_adf4153.FRAC_Value,temp_adf4153.INT_Value,0),R_Divider_Reg_Create(temp_adf4153.MOD_Value,R_Counter,1,0,2,0));   
236
+#endif /* DEBUG_PRINT */
237
+    temp_reg.N_reg = N_Divider_Reg_Create(temp_adf4153.FRAC_Value,temp_adf4153.INT_Value,0);
238
+    temp_reg.R_reg = R_Divider_Reg_Create(temp_adf4153.MOD_Value,R_Counter,1,0,2,0);
239
+
240
+    return temp_reg;
241
+//    R_Divider_Reg_Create(temp_adf4153.MOD_Value,R_Counter,1,0,1,0); //prescaler 1 : 8/9 0: 4/5
242
+}
243
+void ADF4153_Initialize(void){
244
+#if 0 // PYJ.2019.08.09_BEGIN -- 
245
+PLL_Setting_st Pll_test = {
246
+      PLL_CLK_3_5G_GPIO_Port,
247
+      PLL_CLK_3_5G_Pin,
248
+      PLL_DATA_3_5G_GPIO_Port,
249
+      PLL_DATA_3_5G_Pin,
250
+    PLL_EN_3_5G_L_GPIO_Port,    
251
+    PLL_EN_3_5G_L_Pin,
252
+  };
253
+PLL_Setting_st Pll_test2 = {
254
+    PLL_CLK_3_5G_GPIO_Port,
255
+    PLL_CLK_3_5G_Pin,
256
+    PLL_DATA_3_5G_GPIO_Port,
257
+    PLL_DATA_3_5G_Pin,
258
+    PLL_EN_3_5G_H_GPIO_Port,    
259
+    PLL_EN_3_5G_H_Pin,
260
+  };          
261
+    //  ADF4153_Module_Ctrl(Pll_test,0x2B44B0,0x14BE81,0x0013C2,0x000003);
262
+      ADF4153_R_N_Reg_st temp_reg;
263
+      temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
264
+      ADF4153_Module_Ctrl(Pll_test,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);      
265
+    
266
+      HAL_Delay(1);
267
+#ifdef DEBUG_PRINT
268
+        printf("\r\nPLL_EN_3_5G_H_GPIO_Port\r\n");
269
+#endif /* DEBUG_PRINT */
270
+   
271
+        temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
272
+        ADF4153_Module_Ctrl(Pll_test2,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);                  
273
+    //  ADF4153_Module_Ctrl(Pll_test2,0x313840,0x14BE81,0x13C2,0x3);
274
+      HAL_Delay(1);
275
+#endif // PYJ.2019.08.09_END -- 
276
+  if(  Flash_Save_data[INDEX_PLL_3_5G_LOW_H] == 0 
277
+    && Flash_Save_data[INDEX_PLL_3_5G_LOW_M] == 0
278
+    &&Flash_Save_data[INDEX_PLL_3_5G_LOW_L] == 0)
279
+  {
280
+    Flash_Save_data[INDEX_PLL_3_5G_LOW_H] = ((34655 & 0xFF0000) >> 16);
281
+    Flash_Save_data[INDEX_PLL_3_5G_LOW_M] = ((34655 & 0x00FF00) >> 8);
282
+    Flash_Save_data[INDEX_PLL_3_5G_LOW_L] = (34655 & 0x0000FF);
283
+  }
284
+  if(Flash_Save_data[INDEX_PLL_3_5G_HIGH_H] == 0 
285
+    && Flash_Save_data[INDEX_PLL_3_5G_HIGH_M] == 0 
286
+    && Flash_Save_data[INDEX_PLL_3_5G_HIGH_L] == 0)
287
+  {
288
+    Flash_Save_data[INDEX_PLL_3_5G_HIGH_H] = ((39345 & 0xFF0000) >> 16);
289
+    Flash_Save_data[INDEX_PLL_3_5G_HIGH_M] = ((39345 & 0x00FF00) >> 8);    
290
+    Flash_Save_data[INDEX_PLL_3_5G_HIGH_L] = (39345  & 0x0000FF);    
291
+  }
292
+
293
+
294
+}
295
+void ADF4153_Check(void){
296
+  ADF4153_R_N_Reg_st temp_reg;
297
+  if(HAL_GPIO_ReadPin(PLL_LD_3_5G_H_GPIO_Port, PLL_LD_3_5G_H_Pin) == GPIO_PIN_RESET 
298
+     && HAL_GPIO_ReadPin(PLL_ON_OFF_3_5G_H_GPIO_Port, PLL_ON_OFF_3_5G_H_Pin) == GPIO_PIN_SET){
299
+       temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
300
+       ADF4153_Module_Ctrl(Pll_3_5_H,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
301
+       HAL_Delay(1);
302
+     }
303
+     if(HAL_GPIO_ReadPin(PLL_LD_3_5G_L_GPIO_Port, PLL_LD_3_5G_L_Pin) == GPIO_PIN_RESET
304
+     && HAL_GPIO_ReadPin(PLL_ON_OFF_3_5G_L_GPIO_Port, PLL_ON_OFF_3_5G_L_Pin) == GPIO_PIN_SET){
305
+       temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
306
+       ADF4153_Module_Ctrl(Pll_3_5_L,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
307
+       HAL_Delay(1);
308
+     }
309
+
310
+
311
+}
312
+
313
+void ADF4153_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2,uint32_t R3){
314
+    R3  = R3  & 0x0007FF;
315
+    R2 = R2 & 0x00FFFF;
316
+    R1 = R1 & 0xFFFFFF;
317
+    R0 = R0 & 0xFFFFFF;
318
+//    ADF4153_Freq_Calc(3461500000,40000000,2,5000);
319
+    HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
320
+    HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
321
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
322
+#ifdef DEBUG_PRINT
323
+    printf("YJ :R0: %x  R1:  %x   R2 : %x R3 : %x ",R0,R1,R2,R3);
324
+    printf("\r\n");
325
+#endif /* DEBUG_PRINT */
326
+    /*   R3 Ctrl    */
327
+    for(int i =0; i < 11; i++){
328
+        if(R3 & 0x000400){
329
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_SET);
330
+#ifdef DEBUG_PRINT
331
+            printf("1");
332
+#endif /* DEBUG_PRINT */
333
+        }
334
+        else{
335
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
336
+#ifdef DEBUG_PRINT
337
+            printf("0");
338
+#endif /* DEBUG_PRINT */
339
+        }
340
+        Pol_Delay_us(50);
341
+        HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
342
+        Pol_Delay_us(50);
343
+        HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
344
+        R3 = (R3 << 1);
345
+    }
346
+#ifdef DEBUG_PRINT
347
+    printf("\r\n");
348
+#endif /* DEBUG_PRINT */
349
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
350
+      Pol_Delay_us(50);
351
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
352
+    
353
+    /*   R2 Ctrl    */
354
+     for(int i =0; i < 16; i++){
355
+         if(R2 & 0x008000){
356
+             HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_SET);
357
+#ifdef DEBUG_PRINT
358
+             printf("1");
359
+#endif /* DEBUG_PRINT */
360
+         }
361
+         else{
362
+             HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
363
+#ifdef DEBUG_PRINT
364
+             printf("0");
365
+#endif /* DEBUG_PRINT */
366
+         }
367
+         Pol_Delay_us(50);
368
+         HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
369
+         Pol_Delay_us(50);
370
+         HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
371
+
372
+         R2 = ((R2 << 1) & 0x00FFFF);
373
+     }
374
+#ifdef DEBUG_PRINT
375
+     printf("\r\n");
376
+#endif /* DEBUG_PRINT */
377
+     HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
378
+      Pol_Delay_us(50);
379
+     HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
380
+    
381
+     /*   R1 Ctrl    */
382
+    for(int i =0; i < 24; i++){
383
+        if(R1 & 0x800000){
384
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_SET);
385
+#ifdef DEBUG_PRINT
386
+            printf("1");
387
+#endif /* DEBUG_PRINT */
388
+        }
389
+        else{
390
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
391
+#ifdef DEBUG_PRINT
392
+            printf("0");
393
+#endif /* DEBUG_PRINT */
394
+        }
395
+        Pol_Delay_us(50);
396
+        HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
397
+        Pol_Delay_us(50);
398
+        HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
399
+
400
+        R1 = ((R1 << 1) & 0xFFFFFF);
401
+    }
402
+#ifdef DEBUG_PRINT
403
+    printf("\r\n");
404
+#endif /* DEBUG_PRINT */
405
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
406
+      Pol_Delay_us(50);
407
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
408
+
409
+
410
+        /*   R0 Ctrl    */
411
+   
412
+    for(int i =0; i < 24; i++){
413
+        if(R0 & 0x800000){
414
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_SET);
415
+#ifdef DEBUG_PRINT
416
+            printf("1");
417
+#endif /* DEBUG_PRINT */
418
+        }
419
+        else{
420
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
421
+#ifdef DEBUG_PRINT
422
+            printf("0");
423
+#endif /* DEBUG_PRINT */
424
+        }
425
+        Pol_Delay_us(50);
426
+        HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
427
+        Pol_Delay_us(50);
428
+        HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
429
+
430
+        R0 = ((R0 << 1) & 0xFFFFFF);
431
+    }
432
+#ifdef DEBUG_PRINT
433
+    printf("\r\n");
434
+#endif /* DEBUG_PRINT */
435
+    HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
436
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
437
+    Pol_Delay_us(50);
438
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
439
+
440
+}

+ 655 - 0
insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/main(4289).c

@@ -0,0 +1,655 @@
1
+/* USER CODE BEGIN Header */
2
+/**
3
+  ******************************************************************************
4
+  * @file           : main.c
5
+  * @brief          : Main program body
6
+  ******************************************************************************
7
+  * @attention
8
+  *
9
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
10
+  * All rights reserved.</center></h2>
11
+  *
12
+  * This software component is licensed by ST under BSD 3-Clause license,
13
+  * the "License"; You may not use this file except in compliance with the
14
+  * License. You may obtain a copy of the License at:
15
+  *                        opensource.org/licenses/BSD-3-Clause
16
+  *
17
+  ******************************************************************************
18
+  */
19
+/* USER CODE END Header */
20
+
21
+/* Includes ------------------------------------------------------------------*/
22
+#include "main.h"
23
+
24
+/* Private includes ----------------------------------------------------------*/
25
+/* USER CODE BEGIN Includes */
26
+#include "zig_operate.h"
27
+#include "uart.h"
28
+#include "pll_4113.h"
29
+/* USER CODE END Includes */
30
+
31
+/* Private typedef -----------------------------------------------------------*/
32
+/* USER CODE BEGIN PTD */
33
+
34
+/* USER CODE END PTD */
35
+
36
+/* Private define ------------------------------------------------------------*/
37
+/* USER CODE BEGIN PD */
38
+
39
+/* USER CODE END PD */
40
+
41
+/* Private macro -------------------------------------------------------------*/
42
+/* USER CODE BEGIN PM */
43
+
44
+/* USER CODE END PM */
45
+
46
+/* Private variables ---------------------------------------------------------*/
47
+ADC_HandleTypeDef hadc1;
48
+DMA_HandleTypeDef hdma_adc1;
49
+
50
+TIM_HandleTypeDef htim6;
51
+
52
+UART_HandleTypeDef huart1;
53
+DMA_HandleTypeDef hdma_usart1_rx;
54
+DMA_HandleTypeDef hdma_usart1_tx;
55
+
56
+/* USER CODE BEGIN PV */
57
+volatile uint32_t AdcTimerCnt = 0;
58
+volatile uint32_t LedTimerCnt = 0;
59
+volatile uint32_t UartRxTimerCnt = 0;
60
+volatile uint32_t LDTimerCnt = 0;
61
+
62
+extern PLL_Setting_st Pll_3_5_H;
63
+extern PLL_Setting_st Pll_3_5_L;
64
+
65
+//volatile uint32_t UartTxTimerCnt = 0;
66
+
67
+/* USER CODE END PV */
68
+
69
+/* Private function prototypes -----------------------------------------------*/
70
+void SystemClock_Config(void);
71
+static void MX_GPIO_Init(void);
72
+static void MX_DMA_Init(void);
73
+static void MX_ADC1_Init(void);
74
+static void MX_USART1_UART_Init(void);
75
+static void MX_TIM6_Init(void);
76
+static void MX_NVIC_Init(void);
77
+/* USER CODE BEGIN PFP */
78
+extern void ADF4153_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2,uint32_t R3);
79
+extern void ADF4153_Initialize(void);
80
+extern void Path_Init(void);
81
+extern void PE43711_PinInit(void);
82
+extern void BDA4601_Initialize(void);
83
+extern void Uart_Check(void);
84
+extern void Power_ON_OFF_Initialize(void);
85
+extern void Boot_LED_Toggle(void);
86
+extern uint8_t Bluecell_Flash_Write(uint8_t* data);
87
+extern void ADC_Check(void);
88
+extern void AD5318_Initialize(void);
89
+extern void Bluecell_Flash_Read(uint8_t* data);
90
+/* USER CODE END PFP */
91
+
92
+/* Private user code ---------------------------------------------------------*/
93
+/* USER CODE BEGIN 0 */
94
+
95
+
96
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
97
+{
98
+    if(htim->Instance == TIM6){
99
+        UartRxTimerCnt++;
100
+        LedTimerCnt++;
101
+        AdcTimerCnt++;
102
+        LDTimerCnt++;
103
+    }
104
+} 
105
+int _write (int file, uint8_t *ptr, uint16_t len)
106
+{
107
+    HAL_UART_Transmit(&huart1, ptr, len,10);
108
+    return len;
109
+}
110
+
111
+/* USER CODE END 0 */
112
+
113
+/**
114
+  * @brief  The application entry point.
115
+  * @retval int
116
+  */
117
+int main(void)
118
+{
119
+  /* USER CODE BEGIN 1 */
120
+ 
121
+
122
+  /* USER CODE END 1 */
123
+  
124
+
125
+  /* MCU Configuration--------------------------------------------------------*/
126
+
127
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
128
+  HAL_Init();
129
+
130
+  /* USER CODE BEGIN Init */
131
+
132
+  /* USER CODE END Init */
133
+
134
+  /* Configure the system clock */
135
+  SystemClock_Config();
136
+
137
+  /* USER CODE BEGIN SysInit */
138
+
139
+  /* USER CODE END SysInit */
140
+
141
+  /* Initialize all configured peripherals */
142
+  MX_GPIO_Init();
143
+  MX_DMA_Init();
144
+  MX_ADC1_Init();
145
+  MX_USART1_UART_Init();
146
+  MX_TIM6_Init();
147
+
148
+  /* Initialize interrupts */
149
+  MX_NVIC_Init();
150
+  /* USER CODE BEGIN 2 */
151
+  InitUartQueue(&TerminalQueue);
152
+//  PE43711_PinInit();
153
+  Power_ON_OFF_Initialize();  
154
+  Path_Init();
155
+  while(!(HAL_ADCEx_Calibration_Start(&hadc1)==HAL_OK));
156
+  AD5318_Initialize();
157
+  Bluecell_Flash_Read(&Flash_Save_data[INDEX_BLUE_HEADER]);
158
+  ADF4153_Initialize();
159
+  ADF4113_Initialize();
160
+  PE43711_PinInit();
161
+  BDA4601_Initialize();
162
+  ATTEN_PLL_PATH_Initialize();
163
+  HAL_ADC_Start_DMA(&hadc1, (uint32_t*)ADCvalue, 14);
164
+  /* USER CODE END 2 */
165
+
166
+  /* Infinite loop */
167
+  /* USER CODE BEGIN WHILE */
168
+  while (1)
169
+  {
170
+//    ADF4113_Check();
171
+//    ADF4153_Check();
172
+//    HAL_GPIO_TogglePin(ATT_EN_1_8G_UL4_GPIO_Port,ATT_EN_1_8G_UL4_Pin);//DATA
173
+  
174
+    Boot_LED_Toggle();
175
+    Uart_Check();
176
+    ADC_Check();
177
+    /* USER CODE END WHILE */
178
+
179
+    /* USER CODE BEGIN 3 */
180
+  }
181
+  /* USER CODE END 3 */
182
+}
183
+
184
+/**
185
+  * @brief System Clock Configuration
186
+  * @retval None
187
+  */
188
+void SystemClock_Config(void)
189
+{
190
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
191
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
192
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
193
+
194
+  /** Initializes the CPU, AHB and APB busses clocks 
195
+  */
196
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
197
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
198
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
199
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
200
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2;
201
+  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL14;
202
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
203
+  {
204
+    Error_Handler();
205
+  }
206
+  /** Initializes the CPU, AHB and APB busses clocks 
207
+  */
208
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
209
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
210
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
211
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
212
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
213
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
214
+
215
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
216
+  {
217
+    Error_Handler();
218
+  }
219
+  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
220
+  PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV4;
221
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
222
+  {
223
+    Error_Handler();
224
+  }
225
+}
226
+
227
+/**
228
+  * @brief NVIC Configuration.
229
+  * @retval None
230
+  */
231
+static void MX_NVIC_Init(void)
232
+{
233
+  /* USART1_IRQn interrupt configuration */
234
+  HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
235
+  HAL_NVIC_EnableIRQ(USART1_IRQn);
236
+  /* TIM6_IRQn interrupt configuration */
237
+  HAL_NVIC_SetPriority(TIM6_IRQn, 0, 0);
238
+  HAL_NVIC_EnableIRQ(TIM6_IRQn);
239
+  /* DMA1_Channel1_IRQn interrupt configuration */
240
+  HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
241
+  HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
242
+  /* DMA1_Channel4_IRQn interrupt configuration */
243
+  HAL_NVIC_SetPriority(DMA1_Channel4_IRQn, 0, 0);
244
+  HAL_NVIC_EnableIRQ(DMA1_Channel4_IRQn);
245
+  /* DMA1_Channel5_IRQn interrupt configuration */
246
+  HAL_NVIC_SetPriority(DMA1_Channel5_IRQn, 0, 0);
247
+  HAL_NVIC_EnableIRQ(DMA1_Channel5_IRQn);
248
+}
249
+
250
+/**
251
+  * @brief ADC1 Initialization Function
252
+  * @param None
253
+  * @retval None
254
+  */
255
+static void MX_ADC1_Init(void)
256
+{
257
+
258
+  /* USER CODE BEGIN ADC1_Init 0 */
259
+
260
+  /* USER CODE END ADC1_Init 0 */
261
+
262
+  ADC_ChannelConfTypeDef sConfig = {0};
263
+
264
+  /* USER CODE BEGIN ADC1_Init 1 */
265
+
266
+  /* USER CODE END ADC1_Init 1 */
267
+  /** Common config 
268
+  */
269
+  hadc1.Instance = ADC1;
270
+  hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE;
271
+  hadc1.Init.ContinuousConvMode = ENABLE;
272
+  hadc1.Init.DiscontinuousConvMode = DISABLE;
273
+  hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
274
+  hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
275
+  hadc1.Init.NbrOfConversion = 14;
276
+  if (HAL_ADC_Init(&hadc1) != HAL_OK)
277
+  {
278
+    Error_Handler();
279
+  }
280
+  /** Configure Regular Channel 
281
+  */
282
+  sConfig.Channel = ADC_CHANNEL_0;
283
+  sConfig.Rank = ADC_REGULAR_RANK_1;
284
+  sConfig.SamplingTime = ADC_SAMPLETIME_239CYCLES_5;
285
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
286
+  {
287
+    Error_Handler();
288
+  }
289
+  /** Configure Regular Channel 
290
+  */
291
+  sConfig.Channel = ADC_CHANNEL_1;
292
+  sConfig.Rank = ADC_REGULAR_RANK_2;
293
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
294
+  {
295
+    Error_Handler();
296
+  }
297
+  /** Configure Regular Channel 
298
+  */
299
+  sConfig.Channel = ADC_CHANNEL_2;
300
+  sConfig.Rank = ADC_REGULAR_RANK_3;
301
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
302
+  {
303
+    Error_Handler();
304
+  }
305
+  /** Configure Regular Channel 
306
+  */
307
+  sConfig.Channel = ADC_CHANNEL_3;
308
+  sConfig.Rank = ADC_REGULAR_RANK_4;
309
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
310
+  {
311
+    Error_Handler();
312
+  }
313
+  /** Configure Regular Channel 
314
+  */
315
+  sConfig.Channel = ADC_CHANNEL_4;
316
+  sConfig.Rank = ADC_REGULAR_RANK_5;
317
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
318
+  {
319
+    Error_Handler();
320
+  }
321
+  /** Configure Regular Channel 
322
+  */
323
+  sConfig.Channel = ADC_CHANNEL_5;
324
+  sConfig.Rank = ADC_REGULAR_RANK_6;
325
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
326
+  {
327
+    Error_Handler();
328
+  }
329
+  /** Configure Regular Channel 
330
+  */
331
+  sConfig.Channel = ADC_CHANNEL_6;
332
+  sConfig.Rank = ADC_REGULAR_RANK_7;
333
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
334
+  {
335
+    Error_Handler();
336
+  }
337
+  /** Configure Regular Channel 
338
+  */
339
+  sConfig.Channel = ADC_CHANNEL_7;
340
+  sConfig.Rank = ADC_REGULAR_RANK_8;
341
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
342
+  {
343
+    Error_Handler();
344
+  }
345
+  /** Configure Regular Channel 
346
+  */
347
+  sConfig.Channel = ADC_CHANNEL_8;
348
+  sConfig.Rank = ADC_REGULAR_RANK_9;
349
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
350
+  {
351
+    Error_Handler();
352
+  }
353
+  /** Configure Regular Channel 
354
+  */
355
+  sConfig.Channel = ADC_CHANNEL_9;
356
+  sConfig.Rank = ADC_REGULAR_RANK_10;
357
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
358
+  {
359
+    Error_Handler();
360
+  }
361
+  /** Configure Regular Channel 
362
+  */
363
+  sConfig.Channel = ADC_CHANNEL_10;
364
+  sConfig.Rank = ADC_REGULAR_RANK_11;
365
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
366
+  {
367
+    Error_Handler();
368
+  }
369
+  /** Configure Regular Channel 
370
+  */
371
+  sConfig.Channel = ADC_CHANNEL_11;
372
+  sConfig.Rank = ADC_REGULAR_RANK_12;
373
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
374
+  {
375
+    Error_Handler();
376
+  }
377
+  /** Configure Regular Channel 
378
+  */
379
+  sConfig.Channel = ADC_CHANNEL_12;
380
+  sConfig.Rank = ADC_REGULAR_RANK_13;
381
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
382
+  {
383
+    Error_Handler();
384
+  }
385
+  /** Configure Regular Channel 
386
+  */
387
+  sConfig.Channel = ADC_CHANNEL_13;
388
+  sConfig.Rank = ADC_REGULAR_RANK_14;
389
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
390
+  {
391
+    Error_Handler();
392
+  }
393
+  /* USER CODE BEGIN ADC1_Init 2 */
394
+
395
+  /* USER CODE END ADC1_Init 2 */
396
+
397
+}
398
+
399
+/**
400
+  * @brief TIM6 Initialization Function
401
+  * @param None
402
+  * @retval None
403
+  */
404
+static void MX_TIM6_Init(void)
405
+{
406
+
407
+  /* USER CODE BEGIN TIM6_Init 0 */
408
+
409
+  /* USER CODE END TIM6_Init 0 */
410
+
411
+  TIM_MasterConfigTypeDef sMasterConfig = {0};
412
+
413
+  /* USER CODE BEGIN TIM6_Init 1 */
414
+
415
+  /* USER CODE END TIM6_Init 1 */
416
+  htim6.Instance = TIM6;
417
+  htim6.Init.Prescaler = 5600-1;
418
+  htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
419
+  htim6.Init.Period = 10;
420
+  htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
421
+  if (HAL_TIM_Base_Init(&htim6) != HAL_OK)
422
+  {
423
+    Error_Handler();
424
+  }
425
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
426
+  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
427
+  if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK)
428
+  {
429
+    Error_Handler();
430
+  }
431
+  /* USER CODE BEGIN TIM6_Init 2 */
432
+
433
+  /* USER CODE END TIM6_Init 2 */
434
+
435
+}
436
+
437
+/**
438
+  * @brief USART1 Initialization Function
439
+  * @param None
440
+  * @retval None
441
+  */
442
+static void MX_USART1_UART_Init(void)
443
+{
444
+
445
+  /* USER CODE BEGIN USART1_Init 0 */
446
+
447
+  /* USER CODE END USART1_Init 0 */
448
+
449
+  /* USER CODE BEGIN USART1_Init 1 */
450
+
451
+  /* USER CODE END USART1_Init 1 */
452
+  huart1.Instance = USART1;
453
+  huart1.Init.BaudRate = 115200;
454
+  huart1.Init.WordLength = UART_WORDLENGTH_8B;
455
+  huart1.Init.StopBits = UART_STOPBITS_1;
456
+  huart1.Init.Parity = UART_PARITY_NONE;
457
+  huart1.Init.Mode = UART_MODE_TX_RX;
458
+  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
459
+  huart1.Init.OverSampling = UART_OVERSAMPLING_16;
460
+  if (HAL_UART_Init(&huart1) != HAL_OK)
461
+  {
462
+    Error_Handler();
463
+  }
464
+  /* USER CODE BEGIN USART1_Init 2 */
465
+
466
+  /* USER CODE END USART1_Init 2 */
467
+
468
+}
469
+
470
+/** 
471
+  * Enable DMA controller clock
472
+  */
473
+static void MX_DMA_Init(void) 
474
+{
475
+
476
+  /* DMA controller clock enable */
477
+  __HAL_RCC_DMA1_CLK_ENABLE();
478
+
479
+}
480
+
481
+/**
482
+  * @brief GPIO Initialization Function
483
+  * @param None
484
+  * @retval None
485
+  */
486
+static void MX_GPIO_Init(void)
487
+{
488
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
489
+
490
+  /* GPIO Ports Clock Enable */
491
+  __HAL_RCC_GPIOE_CLK_ENABLE();
492
+  __HAL_RCC_GPIOC_CLK_ENABLE();
493
+  __HAL_RCC_GPIOF_CLK_ENABLE();
494
+  __HAL_RCC_GPIOA_CLK_ENABLE();
495
+  __HAL_RCC_GPIOB_CLK_ENABLE();
496
+  __HAL_RCC_GPIOD_CLK_ENABLE();
497
+  __HAL_RCC_GPIOG_CLK_ENABLE();
498
+
499
+  /*Configure GPIO pin Output Level */
500
+  HAL_GPIO_WritePin(GPIOE, ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin 
501
+                          |ATT_EN_1_8G_UL3_Pin|PATH_EN_2_1G_DL_Pin|PATH_EN_2_1G_UL_Pin, GPIO_PIN_RESET);
502
+
503
+  /*Configure GPIO pin Output Level */
504
+  HAL_GPIO_WritePin(GPIOC, ATT_EN_1_8G_UL4_Pin|PATH_EN_1_8G_DL_Pin|PATH_EN_1_8G_UL_Pin|PLL_EN_3_5G_L_Pin 
505
+                          |PLL_EN_3_5G_H_Pin|PLL_ON_OFF_3_5G_L_Pin|PLL_DATA_3_5G_Pin|PLL_ON_OFF_3_5G_H_Pin, GPIO_PIN_RESET);
506
+
507
+  /*Configure GPIO pin Output Level */
508
+  HAL_GPIO_WritePin(GPIOF, PLL_EN_1_8G_DL_Pin|PLL_EN_1_8G_UL_Pin|ATT_EN_2_1G_DL1_Pin|ATT_EN_2_1G_DL2_Pin 
509
+                          |ATT_EN_2_1G_UL1_Pin|ATT_EN_2_1G_UL2_Pin|ATT_EN_2_1G_UL3_Pin|ATT_EN_2_1G_UL4_Pin, GPIO_PIN_RESET);
510
+
511
+  /*Configure GPIO pin Output Level */
512
+  HAL_GPIO_WritePin(GPIOD, PLL_DATA_Pin|PLL_CLK_Pin|ATT_DATA_Pin|ATT_CLK_Pin 
513
+                          |DA_LDAC_Pin|ATT_CLK_3_5G_Pin|ATT_EN_3_5G_Pin|ATT_DATA_3_5G_LOW1_Pin 
514
+                          |ATT_DATA_3_5G_HIGH1_Pin|ATT_DATA_3_5G_COM1_Pin|ATT_DATA_3_5G_LOW2_Pin|ATT_DATA_3_5G_COM2_Pin 
515
+                          |PATH_EN_3_5G_L_Pin, GPIO_PIN_RESET);
516
+
517
+  /*Configure GPIO pin Output Level */
518
+  HAL_GPIO_WritePin(GPIOG, DA_SYNC_Pin|DA_SCLK_Pin|DA_DIN_Pin|_T_SYNC_UL_Pin 
519
+                          |T_SYNC_UL_Pin|_T_SYNC_DL_Pin|T_SYNC_DL_Pin|PATH_EN_3_5G_H_Pin 
520
+                          |PATH_EN_3_5G_DL_Pin|PATH_EN_3_5G_UL_Pin|PLL_ON_OFF_3_5G_LG12_Pin|ATT_DATA_3_5G_HIGH2_Pin 
521
+                          |BOOT_LED_Pin, GPIO_PIN_RESET);
522
+
523
+  /*Configure GPIO pin Output Level */
524
+  HAL_GPIO_WritePin(PLL_CLK_3_5G_GPIO_Port, PLL_CLK_3_5G_Pin, GPIO_PIN_RESET);
525
+
526
+  /*Configure GPIO pin Output Level */
527
+  HAL_GPIO_WritePin(GPIOB, PLL_EN_2_1G_DL_Pin|PLL_EN_2_1G_UL_Pin, GPIO_PIN_RESET);
528
+
529
+  /*Configure GPIO pins : ATT_EN_1_8G_DL1_Pin ATT_EN_1_8G_DL2_Pin ATT_EN_1_8G_UL1_Pin ATT_EN_1_8G_UL2_Pin 
530
+                           ATT_EN_1_8G_UL3_Pin PATH_EN_2_1G_DL_Pin PATH_EN_2_1G_UL_Pin */
531
+  GPIO_InitStruct.Pin = ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin 
532
+                          |ATT_EN_1_8G_UL3_Pin|PATH_EN_2_1G_DL_Pin|PATH_EN_2_1G_UL_Pin;
533
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
534
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
535
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
536
+  HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
537
+
538
+  /*Configure GPIO pins : ATT_EN_1_8G_UL4_Pin PATH_EN_1_8G_DL_Pin PATH_EN_1_8G_UL_Pin PLL_EN_3_5G_L_Pin 
539
+                           PLL_EN_3_5G_H_Pin PLL_ON_OFF_3_5G_L_Pin PLL_DATA_3_5G_Pin PLL_ON_OFF_3_5G_H_Pin */
540
+  GPIO_InitStruct.Pin = ATT_EN_1_8G_UL4_Pin|PATH_EN_1_8G_DL_Pin|PATH_EN_1_8G_UL_Pin|PLL_EN_3_5G_L_Pin 
541
+                          |PLL_EN_3_5G_H_Pin|PLL_ON_OFF_3_5G_L_Pin|PLL_DATA_3_5G_Pin|PLL_ON_OFF_3_5G_H_Pin;
542
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
543
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
544
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
545
+  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
546
+
547
+  /*Configure GPIO pins : PLL_EN_1_8G_DL_Pin PLL_EN_1_8G_UL_Pin ATT_EN_2_1G_DL1_Pin ATT_EN_2_1G_DL2_Pin 
548
+                           ATT_EN_2_1G_UL1_Pin ATT_EN_2_1G_UL2_Pin ATT_EN_2_1G_UL3_Pin ATT_EN_2_1G_UL4_Pin */
549
+  GPIO_InitStruct.Pin = PLL_EN_1_8G_DL_Pin|PLL_EN_1_8G_UL_Pin|ATT_EN_2_1G_DL1_Pin|ATT_EN_2_1G_DL2_Pin 
550
+                          |ATT_EN_2_1G_UL1_Pin|ATT_EN_2_1G_UL2_Pin|ATT_EN_2_1G_UL3_Pin|ATT_EN_2_1G_UL4_Pin;
551
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
552
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
553
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
554
+  HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
555
+
556
+  /*Configure GPIO pins : PLL_LD_1_8G_DL_Pin PLL_LD_1_8G_UL_Pin */
557
+  GPIO_InitStruct.Pin = PLL_LD_1_8G_DL_Pin|PLL_LD_1_8G_UL_Pin;
558
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
559
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
560
+  HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
561
+
562
+  /*Configure GPIO pins : PLL_DATA_Pin PLL_CLK_Pin ATT_DATA_Pin ATT_CLK_Pin 
563
+                           DA_LDAC_Pin ATT_CLK_3_5G_Pin ATT_EN_3_5G_Pin ATT_DATA_3_5G_LOW1_Pin 
564
+                           ATT_DATA_3_5G_HIGH1_Pin ATT_DATA_3_5G_COM1_Pin ATT_DATA_3_5G_LOW2_Pin ATT_DATA_3_5G_COM2_Pin 
565
+                           PATH_EN_3_5G_L_Pin */
566
+  GPIO_InitStruct.Pin = PLL_DATA_Pin|PLL_CLK_Pin|ATT_DATA_Pin|ATT_CLK_Pin 
567
+                          |DA_LDAC_Pin|ATT_CLK_3_5G_Pin|ATT_EN_3_5G_Pin|ATT_DATA_3_5G_LOW1_Pin 
568
+                          |ATT_DATA_3_5G_HIGH1_Pin|ATT_DATA_3_5G_COM1_Pin|ATT_DATA_3_5G_LOW2_Pin|ATT_DATA_3_5G_COM2_Pin 
569
+                          |PATH_EN_3_5G_L_Pin;
570
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
571
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
572
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
573
+  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
574
+
575
+  /*Configure GPIO pins : ALARM_DC_Pin ALARM_AC_Pin */
576
+  GPIO_InitStruct.Pin = ALARM_DC_Pin|ALARM_AC_Pin;
577
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
578
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
579
+  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
580
+
581
+  /*Configure GPIO pins : DA_SYNC_Pin DA_SCLK_Pin DA_DIN_Pin _T_SYNC_UL_Pin 
582
+                           T_SYNC_UL_Pin _T_SYNC_DL_Pin T_SYNC_DL_Pin PATH_EN_3_5G_H_Pin 
583
+                           PATH_EN_3_5G_DL_Pin PATH_EN_3_5G_UL_Pin PLL_ON_OFF_3_5G_LG12_Pin ATT_DATA_3_5G_HIGH2_Pin 
584
+                           BOOT_LED_Pin */
585
+  GPIO_InitStruct.Pin = DA_SYNC_Pin|DA_SCLK_Pin|DA_DIN_Pin|_T_SYNC_UL_Pin 
586
+                          |T_SYNC_UL_Pin|_T_SYNC_DL_Pin|T_SYNC_DL_Pin|PATH_EN_3_5G_H_Pin 
587
+                          |PATH_EN_3_5G_DL_Pin|PATH_EN_3_5G_UL_Pin|PLL_ON_OFF_3_5G_LG12_Pin|ATT_DATA_3_5G_HIGH2_Pin 
588
+                          |BOOT_LED_Pin;
589
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
590
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
591
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
592
+  HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
593
+
594
+  /*Configure GPIO pins : PLL_LD_3_5G_L_Pin PLL_LD_3_5G_H_Pin */
595
+  GPIO_InitStruct.Pin = PLL_LD_3_5G_L_Pin|PLL_LD_3_5G_H_Pin;
596
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
597
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
598
+  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
599
+
600
+  /*Configure GPIO pin : PLL_CLK_3_5G_Pin */
601
+  GPIO_InitStruct.Pin = PLL_CLK_3_5G_Pin;
602
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
603
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
604
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
605
+  HAL_GPIO_Init(PLL_CLK_3_5G_GPIO_Port, &GPIO_InitStruct);
606
+
607
+  /*Configure GPIO pins : PLL_EN_2_1G_DL_Pin PLL_EN_2_1G_UL_Pin */
608
+  GPIO_InitStruct.Pin = PLL_EN_2_1G_DL_Pin|PLL_EN_2_1G_UL_Pin;
609
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
610
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
611
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
612
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
613
+
614
+  /*Configure GPIO pins : PLL_LD_2_1G_DL_Pin PLL_LD_2_1G_UL_Pin */
615
+  GPIO_InitStruct.Pin = PLL_LD_2_1G_DL_Pin|PLL_LD_2_1G_UL_Pin;
616
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
617
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
618
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
619
+
620
+}
621
+
622
+/* USER CODE BEGIN 4 */
623
+
624
+/* USER CODE END 4 */
625
+
626
+/**
627
+  * @brief  This function is executed in case of error occurrence.
628
+  * @retval None
629
+  */
630
+void Error_Handler(void)
631
+{
632
+  /* USER CODE BEGIN Error_Handler_Debug */
633
+  /* User can add his own implementation to report the HAL error return state */
634
+
635
+  /* USER CODE END Error_Handler_Debug */
636
+}
637
+
638
+#ifdef  USE_FULL_ASSERT
639
+/**
640
+  * @brief  Reports the name of the source file and the source line number
641
+  *         where the assert_param error has occurred.
642
+  * @param  file: pointer to the source file name
643
+  * @param  line: assert_param error line source number
644
+  * @retval None
645
+  */
646
+void assert_failed(uint8_t *file, uint32_t line)
647
+{ 
648
+  /* USER CODE BEGIN 6 */
649
+  /* User can add his own implementation to report the file name and line number,
650
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
651
+  /* USER CODE END 6 */
652
+}
653
+#endif /* USE_FULL_ASSERT */
654
+
655
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 757 - 0
insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/zig_operate(3458).c

@@ -0,0 +1,757 @@
1
+/*
2
+ * zig_operate.c
3
+ *
4
+ *  Created on: 2019. 7. 26.
5
+ *      Author: parkyj
6
+ */
7
+#include "zig_operate.h"
8
+#include "main.h"
9
+#include "pll_4113.h"
10
+#include "ADF4153.h"
11
+#include "PE43711.h"
12
+#include "BDA4601.h"
13
+#include "uart.h"
14
+#include "CRC16.h"
15
+extern void AD5318_Ctrl(uint16_t ShiftTarget) ;
16
+extern etError STH30_CheckCrc(uint8_t *data, uint8_t nbrOfBytes, uint8_t checksum);
17
+extern void ADF4153_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2,uint32_t R3);
18
+extern bool Bluecell_Flash_Read(uint8_t* data);
19
+extern void PE43711_ALL_atten_ctrl(ALL_PE43711_st ATT);
20
+extern void Power_ON_OFF_Ctrl(uint8_t type,uint8_t cmd);
21
+extern uint8_t Bluecell_Flash_Write(uint8_t* data);
22
+uint8_t Prev_data[INDEX_BLUE_EOF + 1];
23
+uint8_t Flash_Save_data[INDEX_BLUE_EOF + 1];
24
+
25
+
26
+/* * * * * * * #define Struct* * * * * * * */
27
+PLL_Setting_st Pll_1_8GHz_DL = {
28
+	PLL_CLK_GPIO_Port,
29
+	PLL_CLK_Pin,
30
+	PLL_DATA_GPIO_Port,
31
+	PLL_DATA_Pin,
32
+    PLL_EN_1_8G_DL_GPIO_Port,    
33
+    PLL_EN_1_8G_DL_Pin,
34
+};
35
+PLL_Setting_st Pll_1_8GHz_UL = {
36
+    PLL_CLK_GPIO_Port,
37
+    PLL_CLK_Pin,
38
+    PLL_DATA_GPIO_Port,
39
+    PLL_DATA_Pin,
40
+    PLL_EN_1_8G_UL_GPIO_Port,    
41
+    PLL_EN_1_8G_UL_Pin,
42
+};
43
+PLL_Setting_st Pll_2_1GHz_DL = {
44
+    PLL_CLK_GPIO_Port,
45
+    PLL_CLK_Pin,
46
+    PLL_DATA_GPIO_Port,
47
+    PLL_DATA_Pin,
48
+    PLL_EN_2_1G_DL_GPIO_Port,    
49
+    PLL_EN_2_1G_DL_Pin,
50
+};
51
+PLL_Setting_st Pll_2_1GHz_UL = {
52
+    PLL_CLK_GPIO_Port,
53
+    PLL_CLK_Pin,
54
+    PLL_DATA_GPIO_Port,
55
+    PLL_DATA_Pin,
56
+    PLL_EN_2_1G_UL_GPIO_Port,    
57
+    PLL_EN_2_1G_UL_Pin,
58
+};
59
+/* * * * * * * * NOT YET * * * * * * * */
60
+PLL_Setting_st Pll_3_5GHz_DL = {
61
+    ATT_CLK_3_5G_GPIO_Port,
62
+    ATT_EN_3_5G_Pin,
63
+    PLL_DATA_GPIO_Port,
64
+    PLL_DATA_Pin,
65
+    PLL_EN_2_1G_DL_GPIO_Port,    
66
+    PLL_EN_2_1G_DL_Pin,
67
+};
68
+PLL_Setting_st Pll_3_5GHz_UL = {
69
+    PLL_CLK_GPIO_Port,
70
+    PLL_CLK_Pin,
71
+    PLL_DATA_GPIO_Port,
72
+    PLL_DATA_Pin,
73
+    PLL_EN_2_1G_UL_GPIO_Port,    
74
+    PLL_EN_2_1G_UL_Pin,
75
+};
76
+/* * * * * * * * ATTEN * * * * * * * */    
77
+ATTEN_Setting_st Atten_1_8Ghz_DL1 ={
78
+    ATT_CLK_GPIO_Port,
79
+    ATT_CLK_Pin,
80
+    ATT_DATA_GPIO_Port,
81
+    ATT_DATA_Pin,
82
+    ATT_EN_1_8G_DL1_GPIO_Port,    
83
+    ATT_EN_1_8G_DL1_Pin,
84
+    PATH_EN_1_8G_DL_GPIO_Port,
85
+    PATH_EN_1_8G_DL_Pin,
86
+};
87
+
88
+ATTEN_Setting_st Atten_1_8Ghz_DL2 ={
89
+    ATT_CLK_GPIO_Port,
90
+    ATT_CLK_Pin,
91
+    ATT_DATA_GPIO_Port,
92
+    ATT_DATA_Pin,
93
+    ATT_EN_1_8G_DL2_GPIO_Port,    
94
+    ATT_EN_1_8G_DL2_Pin,
95
+    PATH_EN_1_8G_DL_GPIO_Port,
96
+    PATH_EN_1_8G_DL_Pin,    
97
+};
98
+ATTEN_Setting_st Atten_1_8Ghz_UL1 ={
99
+    ATT_CLK_GPIO_Port,
100
+    ATT_CLK_Pin,
101
+    ATT_DATA_GPIO_Port,
102
+    ATT_DATA_Pin,
103
+    ATT_EN_1_8G_UL1_GPIO_Port,    
104
+    ATT_EN_1_8G_UL1_Pin,
105
+    PATH_EN_1_8G_UL_GPIO_Port,
106
+    PATH_EN_1_8G_UL_Pin,      
107
+};
108
+ATTEN_Setting_st Atten_1_8Ghz_UL2 ={
109
+    ATT_CLK_GPIO_Port,
110
+    ATT_CLK_Pin,
111
+    ATT_DATA_GPIO_Port,
112
+    ATT_DATA_Pin,
113
+    ATT_EN_1_8G_UL2_GPIO_Port,    
114
+    ATT_EN_1_8G_UL2_Pin,
115
+    PATH_EN_1_8G_UL_GPIO_Port,
116
+    PATH_EN_1_8G_UL_Pin,    
117
+};
118
+ATTEN_Setting_st Atten_1_8Ghz_UL3 ={
119
+    ATT_CLK_GPIO_Port,
120
+    ATT_CLK_Pin,
121
+    ATT_DATA_GPIO_Port,
122
+    ATT_DATA_Pin,
123
+    ATT_EN_1_8G_UL3_GPIO_Port,    
124
+    ATT_EN_1_8G_UL3_Pin,
125
+    PATH_EN_1_8G_UL_GPIO_Port,
126
+    PATH_EN_1_8G_UL_Pin,    
127
+};
128
+ATTEN_Setting_st Atten_1_8Ghz_UL4 ={
129
+    ATT_CLK_GPIO_Port,
130
+    ATT_CLK_Pin,
131
+    ATT_DATA_GPIO_Port,
132
+    ATT_DATA_Pin,
133
+    ATT_EN_1_8G_UL4_GPIO_Port,    
134
+    ATT_EN_1_8G_UL4_Pin,
135
+    PATH_EN_1_8G_UL_GPIO_Port,
136
+    PATH_EN_1_8G_UL_Pin,    
137
+};
138
+ATTEN_Setting_st Atten_2_1Ghz_DL1 ={
139
+    ATT_CLK_GPIO_Port,
140
+    ATT_CLK_Pin,
141
+    ATT_DATA_GPIO_Port,
142
+    ATT_DATA_Pin,
143
+    ATT_EN_2_1G_DL1_GPIO_Port,    
144
+    ATT_EN_2_1G_DL1_Pin,
145
+    PATH_EN_2_1G_DL_GPIO_Port,
146
+    PATH_EN_2_1G_DL_Pin,    
147
+};
148
+ATTEN_Setting_st Atten_2_1Ghz_DL2 ={
149
+    ATT_CLK_GPIO_Port,
150
+    ATT_CLK_Pin,
151
+    ATT_DATA_GPIO_Port,
152
+    ATT_DATA_Pin,
153
+    ATT_EN_2_1G_DL2_GPIO_Port,    
154
+    ATT_EN_2_1G_DL2_Pin,
155
+    PATH_EN_2_1G_DL_GPIO_Port,
156
+    PATH_EN_2_1G_DL_Pin,    
157
+};
158
+
159
+ATTEN_Setting_st Atten_2_1Ghz_UL1 ={
160
+    ATT_CLK_GPIO_Port,
161
+    ATT_CLK_Pin,
162
+    ATT_DATA_GPIO_Port,
163
+    ATT_DATA_Pin,
164
+    ATT_EN_2_1G_UL1_GPIO_Port,    
165
+    ATT_EN_2_1G_UL1_Pin,
166
+    PATH_EN_2_1G_UL_GPIO_Port,
167
+    PATH_EN_2_1G_UL_Pin,    
168
+};
169
+ATTEN_Setting_st Atten_2_1Ghz_UL2 ={
170
+    ATT_CLK_GPIO_Port,
171
+    ATT_CLK_Pin,
172
+    ATT_DATA_GPIO_Port,
173
+    ATT_DATA_Pin,
174
+    ATT_EN_2_1G_UL2_GPIO_Port,    
175
+    ATT_EN_2_1G_UL2_Pin,
176
+    PATH_EN_2_1G_UL_GPIO_Port,
177
+    PATH_EN_2_1G_UL_Pin,    
178
+};
179
+ATTEN_Setting_st Atten_2_1Ghz_UL3 ={
180
+    ATT_CLK_GPIO_Port,
181
+    ATT_CLK_Pin,
182
+    ATT_DATA_GPIO_Port,
183
+    ATT_DATA_Pin,
184
+    ATT_EN_2_1G_UL3_GPIO_Port,    
185
+    ATT_EN_2_1G_UL3_Pin,
186
+    PATH_EN_2_1G_UL_GPIO_Port,
187
+    PATH_EN_2_1G_UL_Pin,    
188
+};
189
+ATTEN_Setting_st Atten_2_1Ghz_UL4 ={
190
+    ATT_CLK_GPIO_Port,
191
+    ATT_CLK_Pin,
192
+    ATT_DATA_GPIO_Port,
193
+    ATT_DATA_Pin,
194
+    ATT_EN_2_1G_UL4_GPIO_Port,    
195
+    ATT_EN_2_1G_UL4_Pin,
196
+    PATH_EN_2_1G_UL_GPIO_Port,
197
+    PATH_EN_2_1G_UL_Pin,    
198
+};
199
+
200
+
201
+bool RF_Data_Check(uint8_t* data_buf){
202
+    bool ret = false;
203
+    bool crcret = STH30_CheckCrc(&data_buf[Type], data_buf[Length], data_buf[data_buf[Crcindex]]);
204
+    if(data_buf[Header] == BLUECELL_HEADER){ /*HEADER CHECK*/
205
+        ret= true;
206
+    }
207
+    if(crcret == true){/*CRC CHECK*/
208
+        ret = true;
209
+    }else{
210
+        ret = false;
211
+//        printf("Recv CRC Value : \"%d\"\r\n Create CRC Value : \"%d\"   \r\n",data_buf[data_buf[Crcindex]],STH30_CreateCrc(&data_buf[Type], data_buf[Length]));
212
+    }
213
+//    printf("CRC Result : \"%d\"   \r\n",ret);
214
+    return ret;
215
+
216
+}
217
+
218
+PLL_Setting_st Pll_3_5_H = {
219
+     PLL_CLK_3_5G_GPIO_Port,
220
+     PLL_CLK_3_5G_Pin,
221
+     PLL_DATA_3_5G_GPIO_Port,
222
+     PLL_DATA_3_5G_Pin,
223
+   PLL_EN_3_5G_H_GPIO_Port,    
224
+   PLL_EN_3_5G_H_Pin,
225
+ };
226
+ PLL_Setting_st Pll_3_5_L = {
227
+     PLL_CLK_3_5G_GPIO_Port,
228
+     PLL_CLK_3_5G_Pin,
229
+     PLL_DATA_3_5G_GPIO_Port,
230
+     PLL_DATA_3_5G_Pin,
231
+       PLL_EN_3_5G_L_GPIO_Port,    
232
+       PLL_EN_3_5G_L_Pin,
233
+ };
234
+void RF_Status_Get(void){
235
+//    printf("\r\nYJ2 : Prev_data[INDEX_DET_1_8G_DL_IN_L ] : %x\r\n",Prev_data[INDEX_DET_1_8G_DL_IN_L]);            
236
+    Prev_data[INDEX_BLUE_HEADER]   = BLUECELL_HEADER;
237
+    Prev_data[INDEX_BLUE_TYPE]     = TYPE_BLUECELL_GET;
238
+    Prev_data[INDEX_BLUE_LENGTH]   = INDEX_BLUE_EOF - 2;
239
+    Prev_data[INDEX_BLUE_CRCINDEX] = INDEX_BLUE_CRC;
240
+    Prev_data[INDEX_BLUE_CRC]      = STH30_CreateCrc(&Prev_data[Type], Prev_data[Length]);
241
+    Prev_data[INDEX_BLUE_EOF] = BLUECELL_TAILER;    
242
+    HAL_UART_Transmit_DMA(&huart1,&Prev_data[INDEX_BLUE_HEADER],INDEX_BLUE_EOF + 1); 
243
+//    printf("\r\nYJ : %x",ADCvalue[0]);
244
+//    printf("\r\n");
245
+
246
+}
247
+static uint8_t Ack_Buf[6];
248
+void RF_Status_Ack(void){
249
+//    printf("\r\nYJ2 : Prev_data[INDEX_DET_1_8G_DL_IN_L ] : %x\r\n",Prev_data[INDEX_DET_1_8G_DL_IN_L]);            
250
+    Ack_Buf[INDEX_BLUE_HEADER]       = BLUECELL_HEADER;
251
+    Ack_Buf[INDEX_BLUE_TYPE]         = TYPE_BLUECELL_ACK;
252
+    Ack_Buf[INDEX_BLUE_LENGTH]       = 3;
253
+    Ack_Buf[INDEX_BLUE_CRCINDEX + 0] = INDEX_BLUE_CRCINDEX + 1;
254
+    Ack_Buf[INDEX_BLUE_CRCINDEX + 1] = STH30_CreateCrc(&Ack_Buf[Type], Ack_Buf[Length]);
255
+    Ack_Buf[INDEX_BLUE_CRCINDEX + 2] = BLUECELL_TAILER;
256
+    HAL_UART_Transmit_DMA(&huart1,&Ack_Buf[INDEX_BLUE_HEADER],Ack_Buf[INDEX_BLUE_LENGTH]  + 3); 
257
+//    printf("\r\nYJ : %x",ADCvalue[0]);
258
+//    printf("\r\n");
259
+
260
+}
261
+
262
+void RF_Operate(uint8_t* data_buf){
263
+    uint32_t temp_val = 0;
264
+    uint8_t  ADC_Modify = 0;
265
+    ADF4153_R_N_Reg_st temp_reg;
266
+//    printf("Prev_data[INDEX_ATT_1_8G_DL1]  : %x  data_buf[INDEX_ATT_1_8G_DL1] : %x\r\n",Prev_data[INDEX_ATT_1_8G_DL1],data_buf[INDEX_ATT_1_8G_DL1]);
267
+    if(Prev_data[INDEX_ATT_1_8G_DL1] != data_buf[INDEX_ATT_1_8G_DL1]){
268
+        BDA4601_atten_ctrl(BDA4601_1_8G_DL1,(data_buf[INDEX_ATT_1_8G_DL1]));
269
+        Prev_data[INDEX_ATT_1_8G_DL1] = data_buf[INDEX_ATT_1_8G_DL1];
270
+    }
271
+    if(Prev_data[INDEX_ATT_1_8G_DL2] != data_buf[INDEX_ATT_1_8G_DL2]){
272
+        BDA4601_atten_ctrl(BDA4601_1_8G_DL2,(data_buf[INDEX_ATT_1_8G_DL2]));
273
+        Prev_data[INDEX_ATT_1_8G_DL2] = data_buf[INDEX_ATT_1_8G_DL2];
274
+    }
275
+    if(Prev_data[INDEX_ATT_1_8G_UL1] != data_buf[INDEX_ATT_1_8G_UL1]){
276
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL1,(data_buf[INDEX_ATT_1_8G_UL1]));
277
+        Prev_data[INDEX_ATT_1_8G_UL1] = data_buf[INDEX_ATT_1_8G_UL1];
278
+    }
279
+    if(Prev_data[INDEX_ATT_1_8G_UL2] != data_buf[INDEX_ATT_1_8G_UL2]){
280
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL2,(data_buf[INDEX_ATT_1_8G_UL2]));
281
+        Prev_data[INDEX_ATT_1_8G_UL2] = data_buf[INDEX_ATT_1_8G_UL2];
282
+    }
283
+    if(Prev_data[INDEX_ATT_1_8G_UL3] != data_buf[INDEX_ATT_1_8G_UL3]){
284
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL3,(data_buf[INDEX_ATT_1_8G_UL3]));
285
+        Prev_data[INDEX_ATT_1_8G_UL3] = data_buf[INDEX_ATT_1_8G_UL3];
286
+    }
287
+    if(Prev_data[INDEX_ATT_1_8G_UL4] != data_buf[INDEX_ATT_1_8G_UL4]){
288
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL4,(data_buf[INDEX_ATT_1_8G_UL4]));
289
+        Prev_data[INDEX_ATT_1_8G_UL4] = data_buf[INDEX_ATT_1_8G_UL4];
290
+    }
291
+    if(Prev_data[INDEX_ATT_2_1G_DL1] != data_buf[INDEX_ATT_2_1G_DL1]){
292
+        BDA4601_atten_ctrl(BDA4601_2_1G_DL1,(data_buf[INDEX_ATT_2_1G_DL1]));
293
+        Prev_data[INDEX_ATT_2_1G_DL1] = data_buf[INDEX_ATT_2_1G_DL1];
294
+
295
+    }
296
+    if(Prev_data[INDEX_ATT_2_1G_DL2] != data_buf[INDEX_ATT_2_1G_DL2]){
297
+        BDA4601_atten_ctrl(BDA4601_2_1G_DL2,(data_buf[INDEX_ATT_2_1G_DL2]));
298
+        Prev_data[INDEX_ATT_2_1G_DL2] = data_buf[INDEX_ATT_2_1G_DL2];
299
+
300
+    }
301
+    if(Prev_data[INDEX_ATT_2_1G_UL1] != data_buf[INDEX_ATT_2_1G_UL1]){
302
+        BDA4601_atten_ctrl(BDA4601_2_1G_UL1,(data_buf[INDEX_ATT_2_1G_UL1]));
303
+        Prev_data[INDEX_ATT_2_1G_UL1] = data_buf[INDEX_ATT_2_1G_UL1];
304
+
305
+    }
306
+    if(Prev_data[INDEX_ATT_2_1G_UL2] != data_buf[INDEX_ATT_2_1G_UL2]){
307
+        BDA4601_atten_ctrl(BDA4601_2_1G_UL2,(data_buf[INDEX_ATT_2_1G_UL2]));
308
+        Prev_data[INDEX_ATT_2_1G_UL2] = data_buf[INDEX_ATT_2_1G_UL2];
309
+
310
+    }
311
+    if(Prev_data[INDEX_ATT_2_1G_UL3] != data_buf[INDEX_ATT_2_1G_UL3]){
312
+        BDA4601_atten_ctrl(BDA4601_2_1G_UL3,(data_buf[INDEX_ATT_2_1G_UL3]));
313
+        Prev_data[INDEX_ATT_2_1G_UL3] = data_buf[INDEX_ATT_2_1G_UL3];
314
+    }
315
+    if(Prev_data[INDEX_ATT_2_1G_UL4] != data_buf[INDEX_ATT_2_1G_UL4]){
316
+        BDA4601_atten_ctrl(BDA4601_2_1G_UL4,(data_buf[INDEX_ATT_2_1G_UL4]));
317
+        Prev_data[INDEX_ATT_2_1G_UL4] = data_buf[INDEX_ATT_2_1G_UL4];
318
+    }
319
+    if(   (Prev_data[INDEX_ATT_3_5G_LOW1] != data_buf[INDEX_ATT_3_5G_LOW1])
320
+        ||(Prev_data[INDEX_ATT_3_5G_HIGH1] != data_buf[INDEX_ATT_3_5G_HIGH1])
321
+        ||(Prev_data[INDEX_ATT_3_5G_COM1] != data_buf[INDEX_ATT_3_5G_COM1])
322
+        ||(Prev_data[INDEX_ATT_3_5G_LOW2] != data_buf[INDEX_ATT_3_5G_LOW2])
323
+        ||(Prev_data[INDEX_ATT_3_5G_HIGH2] != data_buf[INDEX_ATT_3_5G_HIGH2])
324
+        ||(Prev_data[INDEX_ATT_3_5G_COM2] != data_buf[INDEX_ATT_3_5G_COM2])
325
+    ){
326
+        ALL_ATT_3_5G.data0 = Prev_data[INDEX_ATT_3_5G_LOW1]  = data_buf[INDEX_ATT_3_5G_LOW1];
327
+        ALL_ATT_3_5G.data1 = Prev_data[INDEX_ATT_3_5G_HIGH1] = data_buf[INDEX_ATT_3_5G_HIGH1];
328
+        ALL_ATT_3_5G.data2 = Prev_data[INDEX_ATT_3_5G_COM1]  = data_buf[INDEX_ATT_3_5G_COM1];
329
+        ALL_ATT_3_5G.data3 = Prev_data[INDEX_ATT_3_5G_LOW2]  = data_buf[INDEX_ATT_3_5G_LOW2];
330
+        ALL_ATT_3_5G.data4 = Prev_data[INDEX_ATT_3_5G_HIGH2] = data_buf[INDEX_ATT_3_5G_HIGH2];
331
+        ALL_ATT_3_5G.data5 = Prev_data[INDEX_ATT_3_5G_COM2]  = data_buf[INDEX_ATT_3_5G_COM2];
332
+        PE43711_ALL_atten_ctrl(ALL_ATT_3_5G);
333
+    }
334
+    if((Prev_data[INDEX_PLL_1_8G_DL_H] != data_buf[INDEX_PLL_1_8G_DL_H])
335
+        || (Prev_data[INDEX_PLL_1_8G_DL_L] != data_buf[INDEX_PLL_1_8G_DL_L])
336
+    ){
337
+        Prev_data[INDEX_PLL_1_8G_DL_H] = data_buf[INDEX_PLL_1_8G_DL_H];
338
+        Prev_data[INDEX_PLL_1_8G_DL_L] = data_buf[INDEX_PLL_1_8G_DL_L];
339
+//        printf("data_buf[INDEX_PLL_1_8G_DL_H] : %x \r\n",data_buf[INDEX_PLL_1_8G_DL_H]);
340
+//        printf("data_buf[INDEX_PLL_1_8G_DL_L] : %x\r\n",data_buf[INDEX_PLL_1_8G_DL_L]);
341
+        temp_val = (data_buf[INDEX_PLL_1_8G_DL_H] << 8) | (data_buf[INDEX_PLL_1_8G_DL_L]);
342
+        ADF4113_Module_Ctrl(ADF4113_1_8G_DL,0x410,halSynSetFreq(temp_val * 100000),0x9F8092);
343
+        HAL_Delay(1);
344
+        BDA4601_atten_ctrl(BDA4601_1_8G_DL1,(data_buf[INDEX_ATT_1_8G_DL1]));
345
+        BDA4601_atten_ctrl(BDA4601_1_8G_DL2,(data_buf[INDEX_ATT_1_8G_DL2]));
346
+    }
347
+    if((Prev_data[INDEX_PLL_1_8G_UL_H] != data_buf[INDEX_PLL_1_8G_UL_H])
348
+        || (Prev_data[INDEX_PLL_1_8G_UL_L] != data_buf[INDEX_PLL_1_8G_UL_L])){
349
+        temp_val = (data_buf[INDEX_PLL_1_8G_UL_H] << 8) | (data_buf[INDEX_PLL_1_8G_UL_L]);
350
+//        printf("data_buf[INDEX_PLL_1_8G_UL_H] : %x \r\n",data_buf[INDEX_PLL_1_8G_UL_H]);
351
+//        printf("data_buf[INDEX_PLL_1_8G_UL_L] : %x\r\n",data_buf[INDEX_PLL_1_8G_UL_L]);
352
+        Prev_data[INDEX_PLL_1_8G_UL_H] = data_buf[INDEX_PLL_1_8G_UL_H];
353
+        Prev_data[INDEX_PLL_1_8G_UL_L] = data_buf[INDEX_PLL_1_8G_UL_L];
354
+//         ADF4113_Module_Ctrl(ADF4113_1_8G_UL,0x000410,0x038D31,0x9f8092);
355
+         ADF4113_Module_Ctrl(ADF4113_1_8G_UL,0x410,halSynSetFreq(temp_val * 100000),0x9F8092);
356
+        HAL_Delay(1);
357
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL1,(data_buf[INDEX_ATT_1_8G_UL1]));
358
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL2,(data_buf[INDEX_ATT_1_8G_UL2]));
359
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL3,(data_buf[INDEX_ATT_1_8G_UL3]));
360
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL4,(data_buf[INDEX_ATT_1_8G_UL4]));
361
+    }
362
+    if((Prev_data[INDEX_PLL_2_1G_DL_H] != data_buf[INDEX_PLL_2_1G_DL_H])
363
+        || (Prev_data[INDEX_PLL_2_1G_DL_L] != data_buf[INDEX_PLL_2_1G_DL_L])){
364
+        temp_val = ((data_buf[INDEX_PLL_2_1G_DL_H] << 8) | (data_buf[INDEX_PLL_2_1G_DL_L]));
365
+//        printf("data_buf[INDEX_PLL_2_1G_DL_H] : %x \r\n",data_buf[INDEX_PLL_2_1G_DL_H]);
366
+//        printf("data_buf[INDEX_PLL_2_1G_DL_L] : %x\r\n",data_buf[INDEX_PLL_2_1G_DL_L]);
367
+        Prev_data[INDEX_PLL_2_1G_DL_H] = data_buf[INDEX_PLL_2_1G_DL_H];
368
+        Prev_data[INDEX_PLL_2_1G_DL_L] = data_buf[INDEX_PLL_2_1G_DL_L];        
369
+//         ADF4113_Module_Ctrl(ADF4113_2_1G_DL,0x410,0x4DE71,0x9F8092);
370
+        ADF4113_Module_Ctrl(ADF4113_2_1G_DL,0x410,halSynSetFreq(temp_val * 100000),0x9F8092);
371
+      HAL_Delay(1);
372
+      BDA4601_atten_ctrl(BDA4601_2_1G_DL1,(data_buf[INDEX_ATT_2_1G_DL1]));
373
+      BDA4601_atten_ctrl(BDA4601_2_1G_DL2,(data_buf[INDEX_ATT_2_1G_DL2]));
374
+    }
375
+    if((Prev_data[INDEX_PLL_2_1G_UL_H] != data_buf[INDEX_PLL_2_1G_UL_H])
376
+        || (Prev_data[INDEX_PLL_2_1G_UL_L] != data_buf[INDEX_PLL_2_1G_UL_L])){
377
+        Prev_data[INDEX_PLL_2_1G_UL_H] = data_buf[INDEX_PLL_2_1G_UL_H];
378
+        Prev_data[INDEX_PLL_2_1G_UL_L] = data_buf[INDEX_PLL_2_1G_UL_L];    
379
+//        printf("data_buf[INDEX_PLL_2_1G_UL_H] : %x \r\n",data_buf[INDEX_PLL_2_1G_UL_H]);
380
+//        printf("data_buf[INDEX_PLL_2_1G_UL_L] : %x\r\n",data_buf[INDEX_PLL_2_1G_UL_L]);
381
+        temp_val = (data_buf[INDEX_PLL_2_1G_UL_H] << 8) | (data_buf[INDEX_PLL_2_1G_UL_L]);
382
+//        ADF4113_Module_Ctrl(ADF4113_2_1G_UL,0x000410,0x59A31,0x9f8092);
383
+        ADF4113_Module_Ctrl(ADF4113_2_1G_UL,0x410,halSynSetFreq(temp_val * 100000),0x9F8092);
384
+      HAL_Delay(1);
385
+      BDA4601_atten_ctrl(BDA4601_2_1G_UL1,(data_buf[INDEX_ATT_2_1G_UL1]));
386
+      BDA4601_atten_ctrl(BDA4601_2_1G_UL2,(data_buf[INDEX_ATT_2_1G_UL2]));
387
+      BDA4601_atten_ctrl(BDA4601_2_1G_UL3,(data_buf[INDEX_ATT_2_1G_UL3]));      
388
+      BDA4601_atten_ctrl(BDA4601_2_1G_UL4,(data_buf[INDEX_ATT_2_1G_UL4]));      
389
+
390
+
391
+    }
392
+    if((Prev_data[INDEX_PLL_3_5G_LOW_H] != data_buf[INDEX_PLL_3_5G_LOW_H])
393
+        ||(Prev_data[INDEX_PLL_3_5G_LOW_M] != data_buf[INDEX_PLL_3_5G_LOW_M])
394
+        || (Prev_data[INDEX_PLL_3_5G_LOW_L] != data_buf[INDEX_PLL_3_5G_LOW_L])){
395
+        Prev_data[INDEX_PLL_3_5G_LOW_H] = data_buf[INDEX_PLL_3_5G_LOW_H];
396
+        Prev_data[INDEX_PLL_3_5G_LOW_M] = data_buf[INDEX_PLL_3_5G_LOW_M];        
397
+        Prev_data[INDEX_PLL_3_5G_LOW_L] = data_buf[INDEX_PLL_3_5G_LOW_L];
398
+        temp_val = (data_buf[INDEX_PLL_3_5G_LOW_H] << 16) | 
399
+                   (data_buf[INDEX_PLL_3_5G_LOW_M] << 8)  | 
400
+                   (data_buf[INDEX_PLL_3_5G_LOW_L]);
401
+#if 1 // PYJ.2019.08.12_BEGIN -- 
402
+        temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
403
+#else
404
+        temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
405
+#endif // PYJ.2019.08.12_END -- 
406
+        ADF4153_Module_Ctrl(Pll_3_5_L,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
407
+    }
408
+    if((Prev_data[INDEX_PLL_3_5G_HIGH_H] != data_buf[INDEX_PLL_3_5G_HIGH_H])
409
+        || (Prev_data[INDEX_PLL_3_5G_HIGH_M] != data_buf[INDEX_PLL_3_5G_HIGH_M])
410
+        || (Prev_data[INDEX_PLL_3_5G_HIGH_L] != data_buf[INDEX_PLL_3_5G_HIGH_L])){
411
+        Prev_data[INDEX_PLL_3_5G_HIGH_H] = data_buf[INDEX_PLL_3_5G_HIGH_H];
412
+        Prev_data[INDEX_PLL_3_5G_HIGH_M] = data_buf[INDEX_PLL_3_5G_HIGH_M];
413
+        Prev_data[INDEX_PLL_3_5G_HIGH_L] = data_buf[INDEX_PLL_3_5G_HIGH_L];
414
+        temp_val = (data_buf[INDEX_PLL_3_5G_HIGH_H] << 16) |
415
+                   (data_buf[INDEX_PLL_3_5G_HIGH_M] << 8)  |
416
+                   (data_buf[INDEX_PLL_3_5G_HIGH_L]);
417
+#if 1 // PYJ.2019.08.12_BEGIN -- 
418
+        temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
419
+#else
420
+        temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
421
+#endif // PYJ.2019.08.12_END -- 
422
+        ADF4153_Module_Ctrl(Pll_3_5_H,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
423
+
424
+    }
425
+    if(Prev_data[INDEX_PLL_LD_6_BIT] != data_buf[INDEX_PLL_LD_6_BIT]){
426
+
427
+    }
428
+#if 0 // PYJ.2019.07.28_BEGIN -- 
429
+    if(Prev_data[INDEX_DET_1_8G_DL_IN_H] != data_buf[INDEX_DET_1_8G_DL_IN_H]){
430
+
431
+    }
432
+    if(Prev_data[INDEX_DET_1_8G_DL_IN_L] != data_buf[INDEX_DET_1_8G_DL_IN_L]){
433
+
434
+    }
435
+    if(Prev_data[INDEX_DET_1_8G_DL_OUT_H] != data_buf[INDEX_DET_1_8G_DL_OUT_H]){
436
+
437
+    }
438
+    if(Prev_data[INDEX_DET_1_8G_DL_OUT_L] != data_buf[INDEX_DET_1_8G_DL_OUT_L]){
439
+
440
+    }
441
+    if(Prev_data[INDEX_DET_1_8G_UL_IN_H] != data_buf[INDEX_DET_1_8G_UL_IN_H]){
442
+
443
+    }
444
+    if(Prev_data[INDEX_DET_1_8G_UL_IN_L] != data_buf[INDEX_DET_1_8G_UL_IN_L]){
445
+
446
+    }
447
+    if(Prev_data[INDEX_DET_1_8G_UL_OUT_H] != data_buf[INDEX_DET_1_8G_UL_OUT_H]){
448
+
449
+    }
450
+    if(Prev_data[INDEX_DET_1_8G_UL_OUT_L] != data_buf[INDEX_DET_1_8G_UL_OUT_L]){
451
+
452
+    }
453
+    if(Prev_data[INDEX_DET_2_1G_DL_IN_H] != data_buf[INDEX_DET_2_1G_DL_IN_H]){
454
+
455
+    }
456
+    if(Prev_data[INDEX_DET_2_1G_DL_IN_L] != data_buf[INDEX_DET_2_1G_DL_IN_L]){
457
+
458
+    }
459
+    if(Prev_data[INDEX_DET_2_1G_DL_OUT_H] != data_buf[INDEX_DET_2_1G_DL_OUT_H]){
460
+
461
+    }
462
+    if(Prev_data[INDEX_DET_2_1G_DL_OUT_L] != data_buf[INDEX_DET_2_1G_DL_OUT_L]){
463
+
464
+    }
465
+    if(Prev_data[INDEX_DET_2_1G_UL_IN_H] != data_buf[INDEX_DET_2_1G_UL_IN_H]){
466
+
467
+    }
468
+    if(Prev_data[INDEX_DET_2_1G_UL_IN_L] != data_buf[INDEX_DET_2_1G_UL_IN_L]){
469
+
470
+    }
471
+
472
+    if(Prev_data[INDEX_DET_2_1G_UL_OUT_H] != data_buf[INDEX_DET_2_1G_UL_OUT_H]){
473
+
474
+    }
475
+    if(Prev_data[INDEX_DET_2_1G_UL_OUT_L] != data_buf[INDEX_DET_2_1G_UL_OUT_L]){
476
+
477
+    }
478
+    if(Prev_data[INDEX_DET_3_5G_DL_IN_H] != data_buf[INDEX_DET_3_5G_DL_IN_H]){
479
+
480
+    }
481
+    if(Prev_data[INDEX_DET_3_5G_DL_IN_L] != data_buf[INDEX_DET_3_5G_DL_IN_L]){
482
+
483
+    }
484
+    if(Prev_data[INDEX_DET_3_5G_DL_OUT_L] != data_buf[INDEX_DET_3_5G_DL_OUT_L]){
485
+
486
+    }
487
+    if(Prev_data[INDEX_DET_3_5G_DL_OUT_H] != data_buf[INDEX_DET_3_5G_DL_OUT_H]){
488
+
489
+    }
490
+    if(Prev_data[INDEX_DET_3_5G_UL_IN_H] != data_buf[INDEX_DET_3_5G_UL_IN_H]){
491
+
492
+    }
493
+    if(Prev_data[INDEX_DET_3_5G_UL_IN_L] != data_buf[INDEX_DET_3_5G_UL_IN_L]){
494
+
495
+    }
496
+
497
+    if(Prev_data[INDEX_DET_3_5G_UL_OUT_H] != data_buf[INDEX_DET_3_5G_UL_OUT_H]){
498
+
499
+    }
500
+    if(Prev_data[INDEX_DET_3_5G_UL_OUT_L] != data_buf[INDEX_DET_3_5G_UL_OUT_L]){
501
+
502
+    }
503
+    if(Prev_data[INDEX_RFU_TEMP_H] != data_buf[INDEX_RFU_TEMP_H]){
504
+
505
+    }
506
+    if(Prev_data[INDEX_RFU_TEMP_L] != data_buf[INDEX_RFU_TEMP_L]){
507
+
508
+    }
509
+    if(Prev_data[INDEX__28V_DET_H] != data_buf[INDEX__28V_DET_H]){
510
+
511
+    }
512
+    if(Prev_data[INDEX__28V_DET_L] != data_buf[INDEX__28V_DET_L]){
513
+
514
+    }
515
+#endif // PYJ.2019.07.28_END -- 
516
+    if(Prev_data[INDEX_ALARM_AC] != data_buf[INDEX_ALARM_AC]){
517
+
518
+    }
519
+    if(Prev_data[INDEX_ALARM_DC] != data_buf[INDEX_ALARM_DC]){
520
+
521
+    }
522
+    if(Prev_data[INDEX_PATH_EN_1_8G_DL] != data_buf[INDEX_PATH_EN_1_8G_DL]){
523
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_1_8G_DL,data_buf[INDEX_PATH_EN_1_8G_DL]);
524
+        Prev_data[INDEX_PATH_EN_1_8G_DL] = data_buf[INDEX_PATH_EN_1_8G_DL];
525
+    }
526
+    if(Prev_data[INDEX_PATH_EN_1_8G_UL] != data_buf[INDEX_PATH_EN_1_8G_UL]){
527
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_1_8G_UL,data_buf[INDEX_PATH_EN_1_8G_UL]);
528
+        Prev_data[INDEX_PATH_EN_1_8G_UL] = data_buf[INDEX_PATH_EN_1_8G_UL];
529
+
530
+    }
531
+
532
+    if(Prev_data[INDEX_PATH_EN_2_1G_DL] != data_buf[INDEX_PATH_EN_2_1G_DL]){
533
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_2_1G_DL,data_buf[INDEX_PATH_EN_2_1G_DL]);
534
+        Prev_data[INDEX_PATH_EN_2_1G_DL] = data_buf[INDEX_PATH_EN_2_1G_DL];
535
+    }
536
+    if(Prev_data[INDEX_PATH_EN_2_1G_UL] != data_buf[INDEX_PATH_EN_2_1G_UL]){
537
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_2_1G_UL,data_buf[INDEX_PATH_EN_2_1G_UL]);
538
+        Prev_data[INDEX_PATH_EN_2_1G_UL] = data_buf[INDEX_PATH_EN_2_1G_UL];
539
+
540
+    }
541
+    if(Prev_data[INDEX_PATH_EN_3_5G_L] != data_buf[INDEX_PATH_EN_3_5G_L]){
542
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_L,data_buf[INDEX_PATH_EN_3_5G_L]);
543
+        Prev_data[INDEX_PATH_EN_3_5G_L] = data_buf[INDEX_PATH_EN_3_5G_L];
544
+
545
+    }
546
+    if(Prev_data[INDEX_PATH_EN_3_5G_H] != data_buf[INDEX_PATH_EN_3_5G_H]){
547
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_H,data_buf[INDEX_PATH_EN_3_5G_H]);
548
+        Prev_data[INDEX_PATH_EN_3_5G_H] = data_buf[INDEX_PATH_EN_3_5G_H];
549
+    
550
+
551
+    }
552
+    if(Prev_data[INDEX_PATH_EN_3_5G_DL] != data_buf[INDEX_PATH_EN_3_5G_DL]){
553
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_DL,data_buf[INDEX_PATH_EN_3_5G_DL]);
554
+        Prev_data[INDEX_PATH_EN_3_5G_DL] = data_buf[INDEX_PATH_EN_3_5G_DL];
555
+        ADC_Modify = 1;
556
+
557
+    }
558
+    if(Prev_data[INDEX_PATH_EN_3_5G_UL] != data_buf[INDEX_PATH_EN_3_5G_UL]){
559
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_UL,data_buf[INDEX_PATH_EN_3_5G_UL]);
560
+        Prev_data[INDEX_PATH_EN_3_5G_UL] = data_buf[INDEX_PATH_EN_3_5G_UL];
561
+        ADC_Modify = 1;
562
+    }
563
+    if(Prev_data[INDEX_PLL_ON_OFF_3_5G_H] != data_buf[INDEX_PLL_ON_OFF_3_5G_H]){
564
+        Power_ON_OFF_Ctrl(INDEX_PLL_ON_OFF_3_5G_H,data_buf[INDEX_PLL_ON_OFF_3_5G_H]);
565
+        Prev_data[INDEX_PLL_ON_OFF_3_5G_H] = data_buf[INDEX_PLL_ON_OFF_3_5G_H];
566
+        HAL_Delay(1);
567
+//        printf("POWER : %d \r\n",Prev_data[INDEX_PLL_ON_OFF_3_5G_H]);
568
+        if(data_buf[INDEX_PLL_ON_OFF_3_5G_H]){
569
+//            printf("PLL CTRL START !! \r\n");
570
+#if 1 // PYJ.2019.08.12_BEGIN -- 
571
+//            temp_val = (Prev_data[INDEX_PLL_3_5G_LOW_H] << 16) |
572
+//                       (Prev_data[INDEX_PLL_3_5G_LOW_M] << 8) | 
573
+//                       (Prev_data[INDEX_PLL_3_5G_LOW_L]);
574
+            temp_val = (Prev_data[INDEX_PLL_3_5G_HIGH_H] << 16) | 
575
+                       (Prev_data[INDEX_PLL_3_5G_HIGH_M] << 8)  | 
576
+                       (Prev_data[INDEX_PLL_3_5G_HIGH_L]);
577
+
578
+
579
+//            temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
580
+            temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
581
+
582
+#else
583
+            temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
584
+#endif // PYJ.2019.08.12_END -- 
585
+            ADF4153_Module_Ctrl(Pll_3_5_H,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
586
+            PE43711_ALL_atten_ctrl(ALL_ATT_3_5G);
587
+        }
588
+    }
589
+    if(Prev_data[INDEX_PLL_ON_OFF_3_5G_L] != data_buf[INDEX_PLL_ON_OFF_3_5G_L]){
590
+        Power_ON_OFF_Ctrl(INDEX_PLL_ON_OFF_3_5G_L,data_buf[INDEX_PLL_ON_OFF_3_5G_L]);
591
+        Prev_data[INDEX_PLL_ON_OFF_3_5G_L] = data_buf[INDEX_PLL_ON_OFF_3_5G_L];
592
+        HAL_Delay(1);
593
+//        printf("POWER : %d \r\n",Prev_data[INDEX_PLL_ON_OFF_3_5G_L]);        
594
+        if(data_buf[INDEX_PLL_ON_OFF_3_5G_L]){
595
+//            printf("PLL CTRL START !! \r\n");
596
+#if 1 // PYJ.2019.08.12_BEGIN -- 
597
+//            temp_val = (Prev_data[INDEX_PLL_3_5G_HIGH_H] << 16) | 
598
+//                       (Prev_data[INDEX_PLL_3_5G_HIGH_M] << 8)  | 
599
+//                       (Prev_data[INDEX_PLL_3_5G_HIGH_L]);
600
+            temp_val = (Prev_data[INDEX_PLL_3_5G_LOW_H] << 16) |
601
+                       (Prev_data[INDEX_PLL_3_5G_LOW_M] << 8) | 
602
+                       (Prev_data[INDEX_PLL_3_5G_LOW_L]);
603
+//            temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
604
+            temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
605
+#else
606
+          temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);            
607
+#endif // PYJ.2019.08.12_END -- 
608
+            ADF4153_Module_Ctrl(Pll_3_5_L,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
609
+            PE43711_ALL_atten_ctrl(ALL_ATT_3_5G);
610
+        }
611
+    }
612
+
613
+    if(Prev_data[INDEX_T_SYNC_DL] != data_buf[INDEX_T_SYNC_DL]){
614
+        Prev_data[INDEX_T_SYNC_DL] = data_buf[INDEX_T_SYNC_DL];
615
+        Power_ON_OFF_Ctrl(INDEX_T_SYNC_DL,data_buf[INDEX_T_SYNC_DL]);
616
+    }
617
+    if(Prev_data[INDEX__T_SYNC_DL] != data_buf[INDEX__T_SYNC_DL]){
618
+        Prev_data[INDEX__T_SYNC_DL] = data_buf[INDEX__T_SYNC_DL];
619
+        Power_ON_OFF_Ctrl(INDEX__T_SYNC_DL,data_buf[INDEX__T_SYNC_DL]);
620
+    }
621
+    if(Prev_data[INDEX_T_SYNC_UL] != data_buf[INDEX_T_SYNC_UL]){
622
+        Prev_data[INDEX_T_SYNC_UL] = data_buf[INDEX_T_SYNC_UL];
623
+        Power_ON_OFF_Ctrl(INDEX_T_SYNC_UL,data_buf[INDEX_T_SYNC_UL]);
624
+    }
625
+    if(Prev_data[INDEX__T_SYNC_UL] != data_buf[INDEX__T_SYNC_UL]){
626
+        Prev_data[INDEX__T_SYNC_UL] = data_buf[INDEX__T_SYNC_UL];
627
+        Power_ON_OFF_Ctrl(INDEX__T_SYNC_UL,data_buf[INDEX__T_SYNC_UL]);
628
+    }
629
+
630
+
631
+    if((Prev_data[INDEX_DAC_VCtrl_A_H] != data_buf[INDEX_DAC_VCtrl_A_H])
632
+        ||(Prev_data[INDEX_DAC_VCtrl_A_L] != data_buf[INDEX_DAC_VCtrl_A_L])){
633
+        ADC_Modify = 1;
634
+        Prev_data[INDEX_DAC_VCtrl_A_H] = data_buf[INDEX_DAC_VCtrl_A_H];
635
+        Prev_data[INDEX_DAC_VCtrl_A_L] = data_buf[INDEX_DAC_VCtrl_A_L];
636
+    }
637
+    if((Prev_data[INDEX_DAC_VCtrl_B_H] != data_buf[INDEX_DAC_VCtrl_B_H])
638
+        ||(Prev_data[INDEX_DAC_VCtrl_B_L] != data_buf[INDEX_DAC_VCtrl_B_L])){
639
+        ADC_Modify = 1;
640
+        
641
+        Prev_data[INDEX_DAC_VCtrl_B_H] = data_buf[INDEX_DAC_VCtrl_B_H];
642
+        Prev_data[INDEX_DAC_VCtrl_B_L] = data_buf[INDEX_DAC_VCtrl_B_L];        
643
+    }    
644
+    if((Prev_data[INDEX_DAC_VCtrl_C_H] != data_buf[INDEX_DAC_VCtrl_C_H])
645
+        ||(Prev_data[INDEX_DAC_VCtrl_C_L] != data_buf[INDEX_DAC_VCtrl_C_L])){
646
+        ADC_Modify = 1;
647
+//        printf("Prev_data[INDEX_DAC_VCtrl_C_H] : %x \r\n",Prev_data[INDEX_DAC_VCtrl_C_H]);
648
+//        printf("Prev_data[INDEX_DAC_VCtrl_C_L] : %x \r\n",Prev_data[INDEX_DAC_VCtrl_C_L]);
649
+
650
+        Prev_data[INDEX_DAC_VCtrl_C_H] = data_buf[INDEX_DAC_VCtrl_C_H];
651
+        Prev_data[INDEX_DAC_VCtrl_C_L] = data_buf[INDEX_DAC_VCtrl_C_L];        
652
+    }
653
+    if((Prev_data[INDEX_DAC_VCtrl_D_H] != data_buf[INDEX_DAC_VCtrl_D_H])
654
+        ||(Prev_data[INDEX_DAC_VCtrl_D_L] != data_buf[INDEX_DAC_VCtrl_D_L])){
655
+        ADC_Modify = 1;
656
+        Prev_data[INDEX_DAC_VCtrl_D_H] = data_buf[INDEX_DAC_VCtrl_D_H];
657
+        Prev_data[INDEX_DAC_VCtrl_D_L] = data_buf[INDEX_DAC_VCtrl_D_L];
658
+    }
659
+    if((Prev_data[INDEX_DAC_VCtrl_E_H] != data_buf[INDEX_DAC_VCtrl_E_H])
660
+        ||(Prev_data[INDEX_DAC_VCtrl_E_L] != data_buf[INDEX_DAC_VCtrl_E_L])){
661
+        ADC_Modify = 1;
662
+
663
+        Prev_data[INDEX_DAC_VCtrl_E_H] = data_buf[INDEX_DAC_VCtrl_E_H];
664
+        Prev_data[INDEX_DAC_VCtrl_E_L] = data_buf[INDEX_DAC_VCtrl_E_L];        
665
+    }
666
+    if((Prev_data[INDEX_DAC_VCtrl_F_H] != data_buf[INDEX_DAC_VCtrl_F_H])
667
+        ||(Prev_data[INDEX_DAC_VCtrl_F_L] != data_buf[INDEX_DAC_VCtrl_F_L])){
668
+        ADC_Modify = 1;
669
+        Prev_data[INDEX_DAC_VCtrl_F_H] = data_buf[INDEX_DAC_VCtrl_F_H];
670
+        Prev_data[INDEX_DAC_VCtrl_F_L] = data_buf[INDEX_DAC_VCtrl_F_L];        
671
+    }
672
+    if((Prev_data[INDEX_DAC_VCtrl_G_H] != data_buf[INDEX_DAC_VCtrl_G_H])
673
+        ||(Prev_data[INDEX_DAC_VCtrl_G_L] != data_buf[INDEX_DAC_VCtrl_G_L])){
674
+        ADC_Modify = 1;
675
+        Prev_data[INDEX_DAC_VCtrl_G_H] = data_buf[INDEX_DAC_VCtrl_G_H];
676
+        Prev_data[INDEX_DAC_VCtrl_G_L] = data_buf[INDEX_DAC_VCtrl_G_L];        
677
+    }    
678
+    if((Prev_data[INDEX_DAC_VCtrl_H_H] != data_buf[INDEX_DAC_VCtrl_H_H])
679
+        ||(Prev_data[INDEX_DAC_VCtrl_H_L] != data_buf[INDEX_DAC_VCtrl_H_L])){
680
+        ADC_Modify = 1;
681
+        Prev_data[INDEX_DAC_VCtrl_H_H] = data_buf[INDEX_DAC_VCtrl_H_H];
682
+        Prev_data[INDEX_DAC_VCtrl_H_L] = data_buf[INDEX_DAC_VCtrl_H_L];        
683
+    }
684
+    if(ADC_Modify){
685
+//        AD5318_Ctrl(0xF000);
686
+//        HAL_Delay(1);
687
+//        AD5318_Ctrl(0x800C);
688
+//        AD5318_Ctrl(0x2FFF );
689
+//        AD5318_Ctrl(0xA000);
690
+//        printf("DAC CTRL START \r\n");
691
+//        AD5318_Ctrl(0x800C);
692
+//        AD5318_Ctrl(0xA000);
693
+//        printf("DAC Change\r\n");
694
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_A_H] << 8 | Prev_data[INDEX_DAC_VCtrl_A_L]));    
695
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_B_H] << 8 | Prev_data[INDEX_DAC_VCtrl_B_L]));    
696
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_C_H] << 8 | Prev_data[INDEX_DAC_VCtrl_C_L]));
697
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_D_H] << 8 | Prev_data[INDEX_DAC_VCtrl_D_L]));
698
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_E_H] << 8 | Prev_data[INDEX_DAC_VCtrl_E_L]));    
699
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_F_H] << 8 | Prev_data[INDEX_DAC_VCtrl_F_L]));
700
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_G_H] << 8 | Prev_data[INDEX_DAC_VCtrl_G_L]));
701
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_H_H] << 8 | Prev_data[INDEX_DAC_VCtrl_H_L]));
702
+    }
703
+    
704
+}
705
+
706
+uint8_t temp_crc = 0;
707
+bool RF_Ctrl_Main(uint8_t* data_buf){
708
+    bool ret = false;
709
+    Bluecell_Prot_t type = data_buf[Type];
710
+    ret = RF_Data_Check(&data_buf[Header]); /* ERROR CHECK */
711
+    if(ret == false){
712
+        HAL_UART_Transmit(&huart1,&data_buf[INDEX_BLUE_HEADER],data_buf[INDEX_BLUE_LENGTH] + 2 + 1,3000); 
713
+        return ret;
714
+    }
715
+    
716
+    switch(type){
717
+    case TYPE_BLUECELL_RESET:
718
+        for(uint8_t i =0 ; i < data_buf[Length] + 6; i++)
719
+            printf("%02x ",data_buf[i]);
720
+        printf("Reset Start \r\n");
721
+        NVIC_SystemReset();
722
+        break;
723
+    case TYPE_BLUECELL_SET:
724
+#if 0 // PYJ.2019.07.31_BEGIN -- 
725
+    printf("TYPE_BLUECELL_SET : ");
726
+    for(uint8_t i =0 ; i < INDEX_BLUE_EOF + 1; i++)
727
+        printf("%02x ",data_buf[i]);
728
+#endif // PYJ.2019.07.31_END -- 
729
+        RF_Operate(&data_buf[Header]);
730
+        RF_Status_Ack();
731
+
732
+//        ADF4153_Freq_Calc(3465500000,40000000,2,5000);
733
+//        ADF4153_Freq_Calc(3993450000,40000000,2,5000);
734
+//        halSynSetFreq(1995000000);
735
+//        halSynSetFreq(1600000000);
736
+//        halSynSetFreq(1455000000);        
737
+        break;
738
+    case TYPE_BLUECELL_GET:
739
+#if 0 // PYJ.2019.08.01_BEGIN -- 
740
+        printf("\r\nTYPE_BLUECELL_GET : \r\n");
741
+#endif // PYJ.2019.08.01_END -- 
742
+        RF_Status_Get();
743
+        break;
744
+    case TYPE_BLUECELL_SAVE:
745
+//        printf("\r\nFLASH Write\r\n");
746
+        Bluecell_Flash_Write(&Prev_data[INDEX_BLUE_HEADER]);
747
+        RF_Status_Ack();
748
+
749
+        break;
750
+        default:
751
+#ifdef DEBUG_PRINT // PYJ.2019.07.27_BEGIN --         
752
+            printf("Function : %s   LINE : %d    type : %d \r\n",__func__,__LINE__,type);
753
+#endif
754
+            break;
755
+    }
756
+    return ret;
757
+}

+ 757 - 0
insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/zig_operate(674).c

@@ -0,0 +1,757 @@
1
+/*
2
+ * zig_operate.c
3
+ *
4
+ *  Created on: 2019. 7. 26.
5
+ *      Author: parkyj
6
+ */
7
+#include "zig_operate.h"
8
+#include "main.h"
9
+#include "pll_4113.h"
10
+#include "ADF4153.h"
11
+#include "PE43711.h"
12
+#include "BDA4601.h"
13
+#include "uart.h"
14
+#include "CRC16.h"
15
+extern void AD5318_Ctrl(uint16_t ShiftTarget) ;
16
+extern etError STH30_CheckCrc(uint8_t *data, uint8_t nbrOfBytes, uint8_t checksum);
17
+extern void ADF4153_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2,uint32_t R3);
18
+extern bool Bluecell_Flash_Read(uint8_t* data);
19
+extern void PE43711_ALL_atten_ctrl(ALL_PE43711_st ATT);
20
+extern void Power_ON_OFF_Ctrl(uint8_t type,uint8_t cmd);
21
+extern uint8_t Bluecell_Flash_Write(uint8_t* data);
22
+uint8_t Prev_data[INDEX_BLUE_EOF + 1];
23
+uint8_t Flash_Save_data[INDEX_BLUE_EOF + 1];
24
+
25
+
26
+/* * * * * * * #define Struct* * * * * * * */
27
+PLL_Setting_st Pll_1_8GHz_DL = {
28
+	PLL_CLK_GPIO_Port,
29
+	PLL_CLK_Pin,
30
+	PLL_DATA_GPIO_Port,
31
+	PLL_DATA_Pin,
32
+    PLL_EN_1_8G_DL_GPIO_Port,    
33
+    PLL_EN_1_8G_DL_Pin,
34
+};
35
+PLL_Setting_st Pll_1_8GHz_UL = {
36
+    PLL_CLK_GPIO_Port,
37
+    PLL_CLK_Pin,
38
+    PLL_DATA_GPIO_Port,
39
+    PLL_DATA_Pin,
40
+    PLL_EN_1_8G_UL_GPIO_Port,    
41
+    PLL_EN_1_8G_UL_Pin,
42
+};
43
+PLL_Setting_st Pll_2_1GHz_DL = {
44
+    PLL_CLK_GPIO_Port,
45
+    PLL_CLK_Pin,
46
+    PLL_DATA_GPIO_Port,
47
+    PLL_DATA_Pin,
48
+    PLL_EN_2_1G_DL_GPIO_Port,    
49
+    PLL_EN_2_1G_DL_Pin,
50
+};
51
+PLL_Setting_st Pll_2_1GHz_UL = {
52
+    PLL_CLK_GPIO_Port,
53
+    PLL_CLK_Pin,
54
+    PLL_DATA_GPIO_Port,
55
+    PLL_DATA_Pin,
56
+    PLL_EN_2_1G_UL_GPIO_Port,    
57
+    PLL_EN_2_1G_UL_Pin,
58
+};
59
+/* * * * * * * * NOT YET * * * * * * * */
60
+PLL_Setting_st Pll_3_5GHz_DL = {
61
+    ATT_CLK_3_5G_GPIO_Port,
62
+    ATT_EN_3_5G_Pin,
63
+    PLL_DATA_GPIO_Port,
64
+    PLL_DATA_Pin,
65
+    PLL_EN_2_1G_DL_GPIO_Port,    
66
+    PLL_EN_2_1G_DL_Pin,
67
+};
68
+PLL_Setting_st Pll_3_5GHz_UL = {
69
+    PLL_CLK_GPIO_Port,
70
+    PLL_CLK_Pin,
71
+    PLL_DATA_GPIO_Port,
72
+    PLL_DATA_Pin,
73
+    PLL_EN_2_1G_UL_GPIO_Port,    
74
+    PLL_EN_2_1G_UL_Pin,
75
+};
76
+/* * * * * * * * ATTEN * * * * * * * */    
77
+ATTEN_Setting_st Atten_1_8Ghz_DL1 ={
78
+    ATT_CLK_GPIO_Port,
79
+    ATT_CLK_Pin,
80
+    ATT_DATA_GPIO_Port,
81
+    ATT_DATA_Pin,
82
+    ATT_EN_1_8G_DL1_GPIO_Port,    
83
+    ATT_EN_1_8G_DL1_Pin,
84
+    PATH_EN_1_8G_DL_GPIO_Port,
85
+    PATH_EN_1_8G_DL_Pin,
86
+};
87
+
88
+ATTEN_Setting_st Atten_1_8Ghz_DL2 ={
89
+    ATT_CLK_GPIO_Port,
90
+    ATT_CLK_Pin,
91
+    ATT_DATA_GPIO_Port,
92
+    ATT_DATA_Pin,
93
+    ATT_EN_1_8G_DL2_GPIO_Port,    
94
+    ATT_EN_1_8G_DL2_Pin,
95
+    PATH_EN_1_8G_DL_GPIO_Port,
96
+    PATH_EN_1_8G_DL_Pin,    
97
+};
98
+ATTEN_Setting_st Atten_1_8Ghz_UL1 ={
99
+    ATT_CLK_GPIO_Port,
100
+    ATT_CLK_Pin,
101
+    ATT_DATA_GPIO_Port,
102
+    ATT_DATA_Pin,
103
+    ATT_EN_1_8G_UL1_GPIO_Port,    
104
+    ATT_EN_1_8G_UL1_Pin,
105
+    PATH_EN_1_8G_UL_GPIO_Port,
106
+    PATH_EN_1_8G_UL_Pin,      
107
+};
108
+ATTEN_Setting_st Atten_1_8Ghz_UL2 ={
109
+    ATT_CLK_GPIO_Port,
110
+    ATT_CLK_Pin,
111
+    ATT_DATA_GPIO_Port,
112
+    ATT_DATA_Pin,
113
+    ATT_EN_1_8G_UL2_GPIO_Port,    
114
+    ATT_EN_1_8G_UL2_Pin,
115
+    PATH_EN_1_8G_UL_GPIO_Port,
116
+    PATH_EN_1_8G_UL_Pin,    
117
+};
118
+ATTEN_Setting_st Atten_1_8Ghz_UL3 ={
119
+    ATT_CLK_GPIO_Port,
120
+    ATT_CLK_Pin,
121
+    ATT_DATA_GPIO_Port,
122
+    ATT_DATA_Pin,
123
+    ATT_EN_1_8G_UL3_GPIO_Port,    
124
+    ATT_EN_1_8G_UL3_Pin,
125
+    PATH_EN_1_8G_UL_GPIO_Port,
126
+    PATH_EN_1_8G_UL_Pin,    
127
+};
128
+ATTEN_Setting_st Atten_1_8Ghz_UL4 ={
129
+    ATT_CLK_GPIO_Port,
130
+    ATT_CLK_Pin,
131
+    ATT_DATA_GPIO_Port,
132
+    ATT_DATA_Pin,
133
+    ATT_EN_1_8G_UL4_GPIO_Port,    
134
+    ATT_EN_1_8G_UL4_Pin,
135
+    PATH_EN_1_8G_UL_GPIO_Port,
136
+    PATH_EN_1_8G_UL_Pin,    
137
+};
138
+ATTEN_Setting_st Atten_2_1Ghz_DL1 ={
139
+    ATT_CLK_GPIO_Port,
140
+    ATT_CLK_Pin,
141
+    ATT_DATA_GPIO_Port,
142
+    ATT_DATA_Pin,
143
+    ATT_EN_2_1G_DL1_GPIO_Port,    
144
+    ATT_EN_2_1G_DL1_Pin,
145
+    PATH_EN_2_1G_DL_GPIO_Port,
146
+    PATH_EN_2_1G_DL_Pin,    
147
+};
148
+ATTEN_Setting_st Atten_2_1Ghz_DL2 ={
149
+    ATT_CLK_GPIO_Port,
150
+    ATT_CLK_Pin,
151
+    ATT_DATA_GPIO_Port,
152
+    ATT_DATA_Pin,
153
+    ATT_EN_2_1G_DL2_GPIO_Port,    
154
+    ATT_EN_2_1G_DL2_Pin,
155
+    PATH_EN_2_1G_DL_GPIO_Port,
156
+    PATH_EN_2_1G_DL_Pin,    
157
+};
158
+
159
+ATTEN_Setting_st Atten_2_1Ghz_UL1 ={
160
+    ATT_CLK_GPIO_Port,
161
+    ATT_CLK_Pin,
162
+    ATT_DATA_GPIO_Port,
163
+    ATT_DATA_Pin,
164
+    ATT_EN_2_1G_UL1_GPIO_Port,    
165
+    ATT_EN_2_1G_UL1_Pin,
166
+    PATH_EN_2_1G_UL_GPIO_Port,
167
+    PATH_EN_2_1G_UL_Pin,    
168
+};
169
+ATTEN_Setting_st Atten_2_1Ghz_UL2 ={
170
+    ATT_CLK_GPIO_Port,
171
+    ATT_CLK_Pin,
172
+    ATT_DATA_GPIO_Port,
173
+    ATT_DATA_Pin,
174
+    ATT_EN_2_1G_UL2_GPIO_Port,    
175
+    ATT_EN_2_1G_UL2_Pin,
176
+    PATH_EN_2_1G_UL_GPIO_Port,
177
+    PATH_EN_2_1G_UL_Pin,    
178
+};
179
+ATTEN_Setting_st Atten_2_1Ghz_UL3 ={
180
+    ATT_CLK_GPIO_Port,
181
+    ATT_CLK_Pin,
182
+    ATT_DATA_GPIO_Port,
183
+    ATT_DATA_Pin,
184
+    ATT_EN_2_1G_UL3_GPIO_Port,    
185
+    ATT_EN_2_1G_UL3_Pin,
186
+    PATH_EN_2_1G_UL_GPIO_Port,
187
+    PATH_EN_2_1G_UL_Pin,    
188
+};
189
+ATTEN_Setting_st Atten_2_1Ghz_UL4 ={
190
+    ATT_CLK_GPIO_Port,
191
+    ATT_CLK_Pin,
192
+    ATT_DATA_GPIO_Port,
193
+    ATT_DATA_Pin,
194
+    ATT_EN_2_1G_UL4_GPIO_Port,    
195
+    ATT_EN_2_1G_UL4_Pin,
196
+    PATH_EN_2_1G_UL_GPIO_Port,
197
+    PATH_EN_2_1G_UL_Pin,    
198
+};
199
+
200
+
201
+bool RF_Data_Check(uint8_t* data_buf){
202
+    bool ret = false;
203
+    bool crcret = STH30_CheckCrc(&data_buf[Type], data_buf[Length], data_buf[data_buf[Crcindex]]);
204
+    if(data_buf[Header] == BLUECELL_HEADER){ /*HEADER CHECK*/
205
+        ret= true;
206
+    }
207
+    if(crcret == true){/*CRC CHECK*/
208
+        ret = true;
209
+    }else{
210
+        ret = false;
211
+//        printf("Recv CRC Value : \"%d\"\r\n Create CRC Value : \"%d\"   \r\n",data_buf[data_buf[Crcindex]],STH30_CreateCrc(&data_buf[Type], data_buf[Length]));
212
+    }
213
+//    printf("CRC Result : \"%d\"   \r\n",ret);
214
+    return ret;
215
+
216
+}
217
+
218
+PLL_Setting_st Pll_3_5_H = {
219
+     PLL_CLK_3_5G_GPIO_Port,
220
+     PLL_CLK_3_5G_Pin,
221
+     PLL_DATA_3_5G_GPIO_Port,
222
+     PLL_DATA_3_5G_Pin,
223
+   PLL_EN_3_5G_H_GPIO_Port,    
224
+   PLL_EN_3_5G_H_Pin,
225
+ };
226
+ PLL_Setting_st Pll_3_5_L = {
227
+     PLL_CLK_3_5G_GPIO_Port,
228
+     PLL_CLK_3_5G_Pin,
229
+     PLL_DATA_3_5G_GPIO_Port,
230
+     PLL_DATA_3_5G_Pin,
231
+       PLL_EN_3_5G_L_GPIO_Port,    
232
+       PLL_EN_3_5G_L_Pin,
233
+ };
234
+void RF_Status_Get(void){
235
+//    printf("\r\nYJ2 : Prev_data[INDEX_DET_1_8G_DL_IN_L ] : %x\r\n",Prev_data[INDEX_DET_1_8G_DL_IN_L]);            
236
+    Prev_data[INDEX_BLUE_HEADER]   = BLUECELL_HEADER;
237
+    Prev_data[INDEX_BLUE_TYPE]     = TYPE_BLUECELL_GET;
238
+    Prev_data[INDEX_BLUE_LENGTH]   = INDEX_BLUE_EOF - 2;
239
+    Prev_data[INDEX_BLUE_CRCINDEX] = INDEX_BLUE_CRC;
240
+    Prev_data[INDEX_BLUE_CRC]      = STH30_CreateCrc(&Prev_data[Type], Prev_data[Length]);
241
+    Prev_data[INDEX_BLUE_EOF] = BLUECELL_TAILER;    
242
+    HAL_UART_Transmit_DMA(&huart1,&Prev_data[INDEX_BLUE_HEADER],INDEX_BLUE_EOF + 1); 
243
+//    printf("\r\nYJ : %x",ADCvalue[0]);
244
+//    printf("\r\n");
245
+
246
+}
247
+static uint8_t Ack_Buf[6];
248
+void RF_Status_Ack(void){
249
+//    printf("\r\nYJ2 : Prev_data[INDEX_DET_1_8G_DL_IN_L ] : %x\r\n",Prev_data[INDEX_DET_1_8G_DL_IN_L]);            
250
+    Ack_Buf[INDEX_BLUE_HEADER]       = BLUECELL_HEADER;
251
+    Ack_Buf[INDEX_BLUE_TYPE]         = TYPE_BLUECELL_ACK;
252
+    Ack_Buf[INDEX_BLUE_LENGTH]       = 3;
253
+    Ack_Buf[INDEX_BLUE_CRCINDEX + 0] = INDEX_BLUE_CRCINDEX + 1;
254
+    Ack_Buf[INDEX_BLUE_CRCINDEX + 1] = STH30_CreateCrc(&Ack_Buf[Type], Ack_Buf[Length]);
255
+    Ack_Buf[INDEX_BLUE_CRCINDEX + 2] = BLUECELL_TAILER;
256
+    HAL_UART_Transmit_DMA(&huart1,&Ack_Buf[INDEX_BLUE_HEADER],Ack_Buf[INDEX_BLUE_LENGTH]  + 3); 
257
+//    printf("\r\nYJ : %x",ADCvalue[0]);
258
+//    printf("\r\n");
259
+
260
+}
261
+
262
+void RF_Operate(uint8_t* data_buf){
263
+    uint32_t temp_val = 0;
264
+    uint8_t  ADC_Modify = 0;
265
+    ADF4153_R_N_Reg_st temp_reg;
266
+//    printf("Prev_data[INDEX_ATT_1_8G_DL1]  : %x  data_buf[INDEX_ATT_1_8G_DL1] : %x\r\n",Prev_data[INDEX_ATT_1_8G_DL1],data_buf[INDEX_ATT_1_8G_DL1]);
267
+    if(Prev_data[INDEX_ATT_1_8G_DL1] != data_buf[INDEX_ATT_1_8G_DL1]){
268
+        BDA4601_atten_ctrl(BDA4601_1_8G_DL1,(data_buf[INDEX_ATT_1_8G_DL1]));
269
+        Prev_data[INDEX_ATT_1_8G_DL1] = data_buf[INDEX_ATT_1_8G_DL1];
270
+    }
271
+    if(Prev_data[INDEX_ATT_1_8G_DL2] != data_buf[INDEX_ATT_1_8G_DL2]){
272
+        BDA4601_atten_ctrl(BDA4601_1_8G_DL2,(data_buf[INDEX_ATT_1_8G_DL2]));
273
+        Prev_data[INDEX_ATT_1_8G_DL2] = data_buf[INDEX_ATT_1_8G_DL2];
274
+    }
275
+    if(Prev_data[INDEX_ATT_1_8G_UL1] != data_buf[INDEX_ATT_1_8G_UL1]){
276
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL1,(data_buf[INDEX_ATT_1_8G_UL1]));
277
+        Prev_data[INDEX_ATT_1_8G_UL1] = data_buf[INDEX_ATT_1_8G_UL1];
278
+    }
279
+    if(Prev_data[INDEX_ATT_1_8G_UL2] != data_buf[INDEX_ATT_1_8G_UL2]){
280
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL2,(data_buf[INDEX_ATT_1_8G_UL2]));
281
+        Prev_data[INDEX_ATT_1_8G_UL2] = data_buf[INDEX_ATT_1_8G_UL2];
282
+    }
283
+    if(Prev_data[INDEX_ATT_1_8G_UL3] != data_buf[INDEX_ATT_1_8G_UL3]){
284
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL3,(data_buf[INDEX_ATT_1_8G_UL3]));
285
+        Prev_data[INDEX_ATT_1_8G_UL3] = data_buf[INDEX_ATT_1_8G_UL3];
286
+    }
287
+    if(Prev_data[INDEX_ATT_1_8G_UL4] != data_buf[INDEX_ATT_1_8G_UL4]){
288
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL4,(data_buf[INDEX_ATT_1_8G_UL4]));
289
+        Prev_data[INDEX_ATT_1_8G_UL4] = data_buf[INDEX_ATT_1_8G_UL4];
290
+    }
291
+    if(Prev_data[INDEX_ATT_2_1G_DL1] != data_buf[INDEX_ATT_2_1G_DL1]){
292
+        BDA4601_atten_ctrl(BDA4601_2_1G_DL1,(data_buf[INDEX_ATT_2_1G_DL1]));
293
+        Prev_data[INDEX_ATT_2_1G_DL1] = data_buf[INDEX_ATT_2_1G_DL1];
294
+
295
+    }
296
+    if(Prev_data[INDEX_ATT_2_1G_DL2] != data_buf[INDEX_ATT_2_1G_DL2]){
297
+        BDA4601_atten_ctrl(BDA4601_2_1G_DL2,(data_buf[INDEX_ATT_2_1G_DL2]));
298
+        Prev_data[INDEX_ATT_2_1G_DL2] = data_buf[INDEX_ATT_2_1G_DL2];
299
+
300
+    }
301
+    if(Prev_data[INDEX_ATT_2_1G_UL1] != data_buf[INDEX_ATT_2_1G_UL1]){
302
+        BDA4601_atten_ctrl(BDA4601_2_1G_UL1,(data_buf[INDEX_ATT_2_1G_UL1]));
303
+        Prev_data[INDEX_ATT_2_1G_UL1] = data_buf[INDEX_ATT_2_1G_UL1];
304
+
305
+    }
306
+    if(Prev_data[INDEX_ATT_2_1G_UL2] != data_buf[INDEX_ATT_2_1G_UL2]){
307
+        BDA4601_atten_ctrl(BDA4601_2_1G_UL2,(data_buf[INDEX_ATT_2_1G_UL2]));
308
+        Prev_data[INDEX_ATT_2_1G_UL2] = data_buf[INDEX_ATT_2_1G_UL2];
309
+
310
+    }
311
+    if(Prev_data[INDEX_ATT_2_1G_UL3] != data_buf[INDEX_ATT_2_1G_UL3]){
312
+        BDA4601_atten_ctrl(BDA4601_2_1G_UL3,(data_buf[INDEX_ATT_2_1G_UL3]));
313
+        Prev_data[INDEX_ATT_2_1G_UL3] = data_buf[INDEX_ATT_2_1G_UL3];
314
+    }
315
+    if(Prev_data[INDEX_ATT_2_1G_UL4] != data_buf[INDEX_ATT_2_1G_UL4]){
316
+        BDA4601_atten_ctrl(BDA4601_2_1G_UL4,(data_buf[INDEX_ATT_2_1G_UL4]));
317
+        Prev_data[INDEX_ATT_2_1G_UL4] = data_buf[INDEX_ATT_2_1G_UL4];
318
+    }
319
+    if(   (Prev_data[INDEX_ATT_3_5G_LOW1] != data_buf[INDEX_ATT_3_5G_LOW1])
320
+        ||(Prev_data[INDEX_ATT_3_5G_HIGH1] != data_buf[INDEX_ATT_3_5G_HIGH1])
321
+        ||(Prev_data[INDEX_ATT_3_5G_COM1] != data_buf[INDEX_ATT_3_5G_COM1])
322
+        ||(Prev_data[INDEX_ATT_3_5G_LOW2] != data_buf[INDEX_ATT_3_5G_LOW2])
323
+        ||(Prev_data[INDEX_ATT_3_5G_HIGH2] != data_buf[INDEX_ATT_3_5G_HIGH2])
324
+        ||(Prev_data[INDEX_ATT_3_5G_COM2] != data_buf[INDEX_ATT_3_5G_COM2])
325
+    ){
326
+        ALL_ATT_3_5G.data0 = Prev_data[INDEX_ATT_3_5G_LOW1]  = data_buf[INDEX_ATT_3_5G_LOW1];
327
+        ALL_ATT_3_5G.data1 = Prev_data[INDEX_ATT_3_5G_HIGH1] = data_buf[INDEX_ATT_3_5G_HIGH1];
328
+        ALL_ATT_3_5G.data2 = Prev_data[INDEX_ATT_3_5G_COM1]  = data_buf[INDEX_ATT_3_5G_COM1];
329
+        ALL_ATT_3_5G.data3 = Prev_data[INDEX_ATT_3_5G_LOW2]  = data_buf[INDEX_ATT_3_5G_LOW2];
330
+        ALL_ATT_3_5G.data4 = Prev_data[INDEX_ATT_3_5G_HIGH2] = data_buf[INDEX_ATT_3_5G_HIGH2];
331
+        ALL_ATT_3_5G.data5 = Prev_data[INDEX_ATT_3_5G_COM2]  = data_buf[INDEX_ATT_3_5G_COM2];
332
+        PE43711_ALL_atten_ctrl(ALL_ATT_3_5G);
333
+    }
334
+    if((Prev_data[INDEX_PLL_1_8G_DL_H] != data_buf[INDEX_PLL_1_8G_DL_H])
335
+        || (Prev_data[INDEX_PLL_1_8G_DL_L] != data_buf[INDEX_PLL_1_8G_DL_L])
336
+    ){
337
+        Prev_data[INDEX_PLL_1_8G_DL_H] = data_buf[INDEX_PLL_1_8G_DL_H];
338
+        Prev_data[INDEX_PLL_1_8G_DL_L] = data_buf[INDEX_PLL_1_8G_DL_L];
339
+//        printf("data_buf[INDEX_PLL_1_8G_DL_H] : %x \r\n",data_buf[INDEX_PLL_1_8G_DL_H]);
340
+//        printf("data_buf[INDEX_PLL_1_8G_DL_L] : %x\r\n",data_buf[INDEX_PLL_1_8G_DL_L]);
341
+        temp_val = (data_buf[INDEX_PLL_1_8G_DL_H] << 8) | (data_buf[INDEX_PLL_1_8G_DL_L]);
342
+        ADF4113_Module_Ctrl(ADF4113_1_8G_DL,0x410,halSynSetFreq(temp_val * 100000),0x9F8092);
343
+        HAL_Delay(1);
344
+        BDA4601_atten_ctrl(BDA4601_1_8G_DL1,(data_buf[INDEX_ATT_1_8G_DL1]));
345
+        BDA4601_atten_ctrl(BDA4601_1_8G_DL2,(data_buf[INDEX_ATT_1_8G_DL2]));
346
+    }
347
+    if((Prev_data[INDEX_PLL_1_8G_UL_H] != data_buf[INDEX_PLL_1_8G_UL_H])
348
+        || (Prev_data[INDEX_PLL_1_8G_UL_L] != data_buf[INDEX_PLL_1_8G_UL_L])){
349
+        temp_val = (data_buf[INDEX_PLL_1_8G_UL_H] << 8) | (data_buf[INDEX_PLL_1_8G_UL_L]);
350
+//        printf("data_buf[INDEX_PLL_1_8G_UL_H] : %x \r\n",data_buf[INDEX_PLL_1_8G_UL_H]);
351
+//        printf("data_buf[INDEX_PLL_1_8G_UL_L] : %x\r\n",data_buf[INDEX_PLL_1_8G_UL_L]);
352
+        Prev_data[INDEX_PLL_1_8G_UL_H] = data_buf[INDEX_PLL_1_8G_UL_H];
353
+        Prev_data[INDEX_PLL_1_8G_UL_L] = data_buf[INDEX_PLL_1_8G_UL_L];
354
+//         ADF4113_Module_Ctrl(ADF4113_1_8G_UL,0x000410,0x038D31,0x9f8092);
355
+         ADF4113_Module_Ctrl(ADF4113_1_8G_UL,0x410,halSynSetFreq(temp_val * 100000),0x9F8092);
356
+        HAL_Delay(1);
357
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL1,(data_buf[INDEX_ATT_1_8G_UL1]));
358
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL2,(data_buf[INDEX_ATT_1_8G_UL2]));
359
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL3,(data_buf[INDEX_ATT_1_8G_UL3]));
360
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL4,(data_buf[INDEX_ATT_1_8G_UL4]));
361
+    }
362
+    if((Prev_data[INDEX_PLL_2_1G_DL_H] != data_buf[INDEX_PLL_2_1G_DL_H])
363
+        || (Prev_data[INDEX_PLL_2_1G_DL_L] != data_buf[INDEX_PLL_2_1G_DL_L])){
364
+        temp_val = ((data_buf[INDEX_PLL_2_1G_DL_H] << 8) | (data_buf[INDEX_PLL_2_1G_DL_L]));
365
+//        printf("data_buf[INDEX_PLL_2_1G_DL_H] : %x \r\n",data_buf[INDEX_PLL_2_1G_DL_H]);
366
+//        printf("data_buf[INDEX_PLL_2_1G_DL_L] : %x\r\n",data_buf[INDEX_PLL_2_1G_DL_L]);
367
+        Prev_data[INDEX_PLL_2_1G_DL_H] = data_buf[INDEX_PLL_2_1G_DL_H];
368
+        Prev_data[INDEX_PLL_2_1G_DL_L] = data_buf[INDEX_PLL_2_1G_DL_L];        
369
+//         ADF4113_Module_Ctrl(ADF4113_2_1G_DL,0x410,0x4DE71,0x9F8092);
370
+        ADF4113_Module_Ctrl(ADF4113_2_1G_DL,0x410,halSynSetFreq(temp_val * 100000),0x9F8092);
371
+      HAL_Delay(1);
372
+      BDA4601_atten_ctrl(BDA4601_2_1G_DL1,(data_buf[INDEX_ATT_2_1G_DL1]));
373
+      BDA4601_atten_ctrl(BDA4601_2_1G_DL2,(data_buf[INDEX_ATT_2_1G_DL2]));
374
+    }
375
+    if((Prev_data[INDEX_PLL_2_1G_UL_H] != data_buf[INDEX_PLL_2_1G_UL_H])
376
+        || (Prev_data[INDEX_PLL_2_1G_UL_L] != data_buf[INDEX_PLL_2_1G_UL_L])){
377
+        Prev_data[INDEX_PLL_2_1G_UL_H] = data_buf[INDEX_PLL_2_1G_UL_H];
378
+        Prev_data[INDEX_PLL_2_1G_UL_L] = data_buf[INDEX_PLL_2_1G_UL_L];    
379
+//        printf("data_buf[INDEX_PLL_2_1G_UL_H] : %x \r\n",data_buf[INDEX_PLL_2_1G_UL_H]);
380
+//        printf("data_buf[INDEX_PLL_2_1G_UL_L] : %x\r\n",data_buf[INDEX_PLL_2_1G_UL_L]);
381
+        temp_val = (data_buf[INDEX_PLL_2_1G_UL_H] << 8) | (data_buf[INDEX_PLL_2_1G_UL_L]);
382
+//        ADF4113_Module_Ctrl(ADF4113_2_1G_UL,0x000410,0x59A31,0x9f8092);
383
+        ADF4113_Module_Ctrl(ADF4113_2_1G_UL,0x410,halSynSetFreq(temp_val * 100000),0x9F8092);
384
+      HAL_Delay(1);
385
+      BDA4601_atten_ctrl(BDA4601_2_1G_UL1,(data_buf[INDEX_ATT_2_1G_UL1]));
386
+      BDA4601_atten_ctrl(BDA4601_2_1G_UL2,(data_buf[INDEX_ATT_2_1G_UL2]));
387
+      BDA4601_atten_ctrl(BDA4601_2_1G_UL3,(data_buf[INDEX_ATT_2_1G_UL3]));      
388
+      BDA4601_atten_ctrl(BDA4601_2_1G_UL4,(data_buf[INDEX_ATT_2_1G_UL4]));      
389
+
390
+
391
+    }
392
+    if((Prev_data[INDEX_PLL_3_5G_LOW_H] != data_buf[INDEX_PLL_3_5G_LOW_H])
393
+        ||(Prev_data[INDEX_PLL_3_5G_LOW_M] != data_buf[INDEX_PLL_3_5G_LOW_M])
394
+        || (Prev_data[INDEX_PLL_3_5G_LOW_L] != data_buf[INDEX_PLL_3_5G_LOW_L])){
395
+        Prev_data[INDEX_PLL_3_5G_LOW_H] = data_buf[INDEX_PLL_3_5G_LOW_H];
396
+        Prev_data[INDEX_PLL_3_5G_LOW_M] = data_buf[INDEX_PLL_3_5G_LOW_M];        
397
+        Prev_data[INDEX_PLL_3_5G_LOW_L] = data_buf[INDEX_PLL_3_5G_LOW_L];
398
+        temp_val = (data_buf[INDEX_PLL_3_5G_LOW_H] << 16) | 
399
+                   (data_buf[INDEX_PLL_3_5G_LOW_M] << 8)  | 
400
+                   (data_buf[INDEX_PLL_3_5G_LOW_L]);
401
+#if 1 // PYJ.2019.08.12_BEGIN -- 
402
+        temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
403
+#else
404
+        temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
405
+#endif // PYJ.2019.08.12_END -- 
406
+        ADF4153_Module_Ctrl(Pll_3_5_L,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
407
+    }
408
+    if((Prev_data[INDEX_PLL_3_5G_HIGH_H] != data_buf[INDEX_PLL_3_5G_HIGH_H])
409
+        || (Prev_data[INDEX_PLL_3_5G_HIGH_M] != data_buf[INDEX_PLL_3_5G_HIGH_M])
410
+        || (Prev_data[INDEX_PLL_3_5G_HIGH_L] != data_buf[INDEX_PLL_3_5G_HIGH_L])){
411
+        Prev_data[INDEX_PLL_3_5G_HIGH_H] = data_buf[INDEX_PLL_3_5G_HIGH_H];
412
+        Prev_data[INDEX_PLL_3_5G_HIGH_M] = data_buf[INDEX_PLL_3_5G_HIGH_M];
413
+        Prev_data[INDEX_PLL_3_5G_HIGH_L] = data_buf[INDEX_PLL_3_5G_HIGH_L];
414
+        temp_val = (data_buf[INDEX_PLL_3_5G_HIGH_H] << 16) |
415
+                   (data_buf[INDEX_PLL_3_5G_HIGH_M] << 8)  |
416
+                   (data_buf[INDEX_PLL_3_5G_HIGH_L]);
417
+#if 1 // PYJ.2019.08.12_BEGIN -- 
418
+        temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
419
+#else
420
+        temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
421
+#endif // PYJ.2019.08.12_END -- 
422
+        ADF4153_Module_Ctrl(Pll_3_5_H,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
423
+
424
+    }
425
+    if(Prev_data[INDEX_PLL_LD_6_BIT] != data_buf[INDEX_PLL_LD_6_BIT]){
426
+
427
+    }
428
+#if 0 // PYJ.2019.07.28_BEGIN -- 
429
+    if(Prev_data[INDEX_DET_1_8G_DL_IN_H] != data_buf[INDEX_DET_1_8G_DL_IN_H]){
430
+
431
+    }
432
+    if(Prev_data[INDEX_DET_1_8G_DL_IN_L] != data_buf[INDEX_DET_1_8G_DL_IN_L]){
433
+
434
+    }
435
+    if(Prev_data[INDEX_DET_1_8G_DL_OUT_H] != data_buf[INDEX_DET_1_8G_DL_OUT_H]){
436
+
437
+    }
438
+    if(Prev_data[INDEX_DET_1_8G_DL_OUT_L] != data_buf[INDEX_DET_1_8G_DL_OUT_L]){
439
+
440
+    }
441
+    if(Prev_data[INDEX_DET_1_8G_UL_IN_H] != data_buf[INDEX_DET_1_8G_UL_IN_H]){
442
+
443
+    }
444
+    if(Prev_data[INDEX_DET_1_8G_UL_IN_L] != data_buf[INDEX_DET_1_8G_UL_IN_L]){
445
+
446
+    }
447
+    if(Prev_data[INDEX_DET_1_8G_UL_OUT_H] != data_buf[INDEX_DET_1_8G_UL_OUT_H]){
448
+
449
+    }
450
+    if(Prev_data[INDEX_DET_1_8G_UL_OUT_L] != data_buf[INDEX_DET_1_8G_UL_OUT_L]){
451
+
452
+    }
453
+    if(Prev_data[INDEX_DET_2_1G_DL_IN_H] != data_buf[INDEX_DET_2_1G_DL_IN_H]){
454
+
455
+    }
456
+    if(Prev_data[INDEX_DET_2_1G_DL_IN_L] != data_buf[INDEX_DET_2_1G_DL_IN_L]){
457
+
458
+    }
459
+    if(Prev_data[INDEX_DET_2_1G_DL_OUT_H] != data_buf[INDEX_DET_2_1G_DL_OUT_H]){
460
+
461
+    }
462
+    if(Prev_data[INDEX_DET_2_1G_DL_OUT_L] != data_buf[INDEX_DET_2_1G_DL_OUT_L]){
463
+
464
+    }
465
+    if(Prev_data[INDEX_DET_2_1G_UL_IN_H] != data_buf[INDEX_DET_2_1G_UL_IN_H]){
466
+
467
+    }
468
+    if(Prev_data[INDEX_DET_2_1G_UL_IN_L] != data_buf[INDEX_DET_2_1G_UL_IN_L]){
469
+
470
+    }
471
+
472
+    if(Prev_data[INDEX_DET_2_1G_UL_OUT_H] != data_buf[INDEX_DET_2_1G_UL_OUT_H]){
473
+
474
+    }
475
+    if(Prev_data[INDEX_DET_2_1G_UL_OUT_L] != data_buf[INDEX_DET_2_1G_UL_OUT_L]){
476
+
477
+    }
478
+    if(Prev_data[INDEX_DET_3_5G_DL_IN_H] != data_buf[INDEX_DET_3_5G_DL_IN_H]){
479
+
480
+    }
481
+    if(Prev_data[INDEX_DET_3_5G_DL_IN_L] != data_buf[INDEX_DET_3_5G_DL_IN_L]){
482
+
483
+    }
484
+    if(Prev_data[INDEX_DET_3_5G_DL_OUT_L] != data_buf[INDEX_DET_3_5G_DL_OUT_L]){
485
+
486
+    }
487
+    if(Prev_data[INDEX_DET_3_5G_DL_OUT_H] != data_buf[INDEX_DET_3_5G_DL_OUT_H]){
488
+
489
+    }
490
+    if(Prev_data[INDEX_DET_3_5G_UL_IN_H] != data_buf[INDEX_DET_3_5G_UL_IN_H]){
491
+
492
+    }
493
+    if(Prev_data[INDEX_DET_3_5G_UL_IN_L] != data_buf[INDEX_DET_3_5G_UL_IN_L]){
494
+
495
+    }
496
+
497
+    if(Prev_data[INDEX_DET_3_5G_UL_OUT_H] != data_buf[INDEX_DET_3_5G_UL_OUT_H]){
498
+
499
+    }
500
+    if(Prev_data[INDEX_DET_3_5G_UL_OUT_L] != data_buf[INDEX_DET_3_5G_UL_OUT_L]){
501
+
502
+    }
503
+    if(Prev_data[INDEX_RFU_TEMP_H] != data_buf[INDEX_RFU_TEMP_H]){
504
+
505
+    }
506
+    if(Prev_data[INDEX_RFU_TEMP_L] != data_buf[INDEX_RFU_TEMP_L]){
507
+
508
+    }
509
+    if(Prev_data[INDEX__28V_DET_H] != data_buf[INDEX__28V_DET_H]){
510
+
511
+    }
512
+    if(Prev_data[INDEX__28V_DET_L] != data_buf[INDEX__28V_DET_L]){
513
+
514
+    }
515
+#endif // PYJ.2019.07.28_END -- 
516
+    if(Prev_data[INDEX_ALARM_AC] != data_buf[INDEX_ALARM_AC]){
517
+
518
+    }
519
+    if(Prev_data[INDEX_ALARM_DC] != data_buf[INDEX_ALARM_DC]){
520
+
521
+    }
522
+    if(Prev_data[INDEX_PATH_EN_1_8G_DL] != data_buf[INDEX_PATH_EN_1_8G_DL]){
523
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_1_8G_DL,data_buf[INDEX_PATH_EN_1_8G_DL]);
524
+        Prev_data[INDEX_PATH_EN_1_8G_DL] = data_buf[INDEX_PATH_EN_1_8G_DL];
525
+    }
526
+    if(Prev_data[INDEX_PATH_EN_1_8G_UL] != data_buf[INDEX_PATH_EN_1_8G_UL]){
527
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_1_8G_UL,data_buf[INDEX_PATH_EN_1_8G_UL]);
528
+        Prev_data[INDEX_PATH_EN_1_8G_UL] = data_buf[INDEX_PATH_EN_1_8G_UL];
529
+
530
+    }
531
+
532
+    if(Prev_data[INDEX_PATH_EN_2_1G_DL] != data_buf[INDEX_PATH_EN_2_1G_DL]){
533
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_2_1G_DL,data_buf[INDEX_PATH_EN_2_1G_DL]);
534
+        Prev_data[INDEX_PATH_EN_2_1G_DL] = data_buf[INDEX_PATH_EN_2_1G_DL];
535
+    }
536
+    if(Prev_data[INDEX_PATH_EN_2_1G_UL] != data_buf[INDEX_PATH_EN_2_1G_UL]){
537
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_2_1G_UL,data_buf[INDEX_PATH_EN_2_1G_UL]);
538
+        Prev_data[INDEX_PATH_EN_2_1G_UL] = data_buf[INDEX_PATH_EN_2_1G_UL];
539
+
540
+    }
541
+    if(Prev_data[INDEX_PATH_EN_3_5G_L] != data_buf[INDEX_PATH_EN_3_5G_L]){
542
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_L,data_buf[INDEX_PATH_EN_3_5G_L]);
543
+        Prev_data[INDEX_PATH_EN_3_5G_L] = data_buf[INDEX_PATH_EN_3_5G_L];
544
+
545
+    }
546
+    if(Prev_data[INDEX_PATH_EN_3_5G_H] != data_buf[INDEX_PATH_EN_3_5G_H]){
547
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_H,data_buf[INDEX_PATH_EN_3_5G_H]);
548
+        Prev_data[INDEX_PATH_EN_3_5G_H] = data_buf[INDEX_PATH_EN_3_5G_H];
549
+    
550
+
551
+    }
552
+    if(Prev_data[INDEX_PATH_EN_3_5G_DL] != data_buf[INDEX_PATH_EN_3_5G_DL]){
553
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_DL,data_buf[INDEX_PATH_EN_3_5G_DL]);
554
+        Prev_data[INDEX_PATH_EN_3_5G_DL] = data_buf[INDEX_PATH_EN_3_5G_DL];
555
+        ADC_Modify = 1;
556
+
557
+    }
558
+    if(Prev_data[INDEX_PATH_EN_3_5G_UL] != data_buf[INDEX_PATH_EN_3_5G_UL]){
559
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_UL,data_buf[INDEX_PATH_EN_3_5G_UL]);
560
+        Prev_data[INDEX_PATH_EN_3_5G_UL] = data_buf[INDEX_PATH_EN_3_5G_UL];
561
+        ADC_Modify = 1;
562
+    }
563
+    if(Prev_data[INDEX_PLL_ON_OFF_3_5G_H] != data_buf[INDEX_PLL_ON_OFF_3_5G_H]){
564
+        Power_ON_OFF_Ctrl(INDEX_PLL_ON_OFF_3_5G_H,data_buf[INDEX_PLL_ON_OFF_3_5G_H]);
565
+        Prev_data[INDEX_PLL_ON_OFF_3_5G_H] = data_buf[INDEX_PLL_ON_OFF_3_5G_H];
566
+        HAL_Delay(1);
567
+//        printf("POWER : %d \r\n",Prev_data[INDEX_PLL_ON_OFF_3_5G_H]);
568
+        if(data_buf[INDEX_PLL_ON_OFF_3_5G_H]){
569
+//            printf("PLL CTRL START !! \r\n");
570
+#if 1 // PYJ.2019.08.12_BEGIN -- 
571
+//            temp_val = (Prev_data[INDEX_PLL_3_5G_LOW_H] << 16) |
572
+//                       (Prev_data[INDEX_PLL_3_5G_LOW_M] << 8) | 
573
+//                       (Prev_data[INDEX_PLL_3_5G_LOW_L]);
574
+            temp_val = (Prev_data[INDEX_PLL_3_5G_HIGH_H] << 16) | 
575
+                       (Prev_data[INDEX_PLL_3_5G_HIGH_M] << 8)  | 
576
+                       (Prev_data[INDEX_PLL_3_5G_HIGH_L]);
577
+
578
+
579
+//            temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
580
+            temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
581
+
582
+#else
583
+            temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
584
+#endif // PYJ.2019.08.12_END -- 
585
+            ADF4153_Module_Ctrl(Pll_3_5_H,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
586
+            PE43711_ALL_atten_ctrl(ALL_ATT_3_5G);
587
+        }
588
+    }
589
+    if(Prev_data[INDEX_PLL_ON_OFF_3_5G_L] != data_buf[INDEX_PLL_ON_OFF_3_5G_L]){
590
+        Power_ON_OFF_Ctrl(INDEX_PLL_ON_OFF_3_5G_L,data_buf[INDEX_PLL_ON_OFF_3_5G_L]);
591
+        Prev_data[INDEX_PLL_ON_OFF_3_5G_L] = data_buf[INDEX_PLL_ON_OFF_3_5G_L];
592
+        HAL_Delay(1);
593
+//        printf("POWER : %d \r\n",Prev_data[INDEX_PLL_ON_OFF_3_5G_L]);        
594
+        if(data_buf[INDEX_PLL_ON_OFF_3_5G_L]){
595
+//            printf("PLL CTRL START !! \r\n");
596
+#if 1 // PYJ.2019.08.12_BEGIN -- 
597
+//            temp_val = (Prev_data[INDEX_PLL_3_5G_HIGH_H] << 16) | 
598
+//                       (Prev_data[INDEX_PLL_3_5G_HIGH_M] << 8)  | 
599
+//                       (Prev_data[INDEX_PLL_3_5G_HIGH_L]);
600
+            temp_val = (Prev_data[INDEX_PLL_3_5G_LOW_H] << 16) |
601
+                       (Prev_data[INDEX_PLL_3_5G_LOW_M] << 8) | 
602
+                       (Prev_data[INDEX_PLL_3_5G_LOW_L]);
603
+//            temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
604
+            temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
605
+#else
606
+          temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);            
607
+#endif // PYJ.2019.08.12_END -- 
608
+            ADF4153_Module_Ctrl(Pll_3_5_L,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
609
+            PE43711_ALL_atten_ctrl(ALL_ATT_3_5G);
610
+        }
611
+    }
612
+
613
+    if(Prev_data[INDEX_T_SYNC_DL] != data_buf[INDEX_T_SYNC_DL]){
614
+        Prev_data[INDEX_T_SYNC_DL] = data_buf[INDEX_T_SYNC_DL];
615
+        Power_ON_OFF_Ctrl(INDEX_T_SYNC_DL,data_buf[INDEX_T_SYNC_DL]);
616
+    }
617
+    if(Prev_data[INDEX__T_SYNC_DL] != data_buf[INDEX__T_SYNC_DL]){
618
+        Prev_data[INDEX__T_SYNC_DL] = data_buf[INDEX__T_SYNC_DL];
619
+        Power_ON_OFF_Ctrl(INDEX__T_SYNC_DL,data_buf[INDEX__T_SYNC_DL]);
620
+    }
621
+    if(Prev_data[INDEX_T_SYNC_UL] != data_buf[INDEX_T_SYNC_UL]){
622
+        Prev_data[INDEX_T_SYNC_UL] = data_buf[INDEX_T_SYNC_UL];
623
+        Power_ON_OFF_Ctrl(INDEX_T_SYNC_UL,data_buf[INDEX_T_SYNC_UL]);
624
+    }
625
+    if(Prev_data[INDEX__T_SYNC_UL] != data_buf[INDEX__T_SYNC_UL]){
626
+        Prev_data[INDEX__T_SYNC_UL] = data_buf[INDEX__T_SYNC_UL];
627
+        Power_ON_OFF_Ctrl(INDEX__T_SYNC_UL,data_buf[INDEX__T_SYNC_UL]);
628
+    }
629
+
630
+
631
+    if((Prev_data[INDEX_DAC_VCtrl_A_H] != data_buf[INDEX_DAC_VCtrl_A_H])
632
+        ||(Prev_data[INDEX_DAC_VCtrl_A_L] != data_buf[INDEX_DAC_VCtrl_A_L])){
633
+        ADC_Modify = 1;
634
+        Prev_data[INDEX_DAC_VCtrl_A_H] = data_buf[INDEX_DAC_VCtrl_A_H];
635
+        Prev_data[INDEX_DAC_VCtrl_A_L] = data_buf[INDEX_DAC_VCtrl_A_L];
636
+    }
637
+    if((Prev_data[INDEX_DAC_VCtrl_B_H] != data_buf[INDEX_DAC_VCtrl_B_H])
638
+        ||(Prev_data[INDEX_DAC_VCtrl_B_L] != data_buf[INDEX_DAC_VCtrl_B_L])){
639
+        ADC_Modify = 1;
640
+        
641
+        Prev_data[INDEX_DAC_VCtrl_B_H] = data_buf[INDEX_DAC_VCtrl_B_H];
642
+        Prev_data[INDEX_DAC_VCtrl_B_L] = data_buf[INDEX_DAC_VCtrl_B_L];        
643
+    }    
644
+    if((Prev_data[INDEX_DAC_VCtrl_C_H] != data_buf[INDEX_DAC_VCtrl_C_H])
645
+        ||(Prev_data[INDEX_DAC_VCtrl_C_L] != data_buf[INDEX_DAC_VCtrl_C_L])){
646
+        ADC_Modify = 1;
647
+//        printf("Prev_data[INDEX_DAC_VCtrl_C_H] : %x \r\n",Prev_data[INDEX_DAC_VCtrl_C_H]);
648
+//        printf("Prev_data[INDEX_DAC_VCtrl_C_L] : %x \r\n",Prev_data[INDEX_DAC_VCtrl_C_L]);
649
+
650
+        Prev_data[INDEX_DAC_VCtrl_C_H] = data_buf[INDEX_DAC_VCtrl_C_H];
651
+        Prev_data[INDEX_DAC_VCtrl_C_L] = data_buf[INDEX_DAC_VCtrl_C_L];        
652
+    }
653
+    if((Prev_data[INDEX_DAC_VCtrl_D_H] != data_buf[INDEX_DAC_VCtrl_D_H])
654
+        ||(Prev_data[INDEX_DAC_VCtrl_D_L] != data_buf[INDEX_DAC_VCtrl_D_L])){
655
+        ADC_Modify = 1;
656
+        Prev_data[INDEX_DAC_VCtrl_D_H] = data_buf[INDEX_DAC_VCtrl_D_H];
657
+        Prev_data[INDEX_DAC_VCtrl_D_L] = data_buf[INDEX_DAC_VCtrl_D_L];
658
+    }
659
+    if((Prev_data[INDEX_DAC_VCtrl_E_H] != data_buf[INDEX_DAC_VCtrl_E_H])
660
+        ||(Prev_data[INDEX_DAC_VCtrl_E_L] != data_buf[INDEX_DAC_VCtrl_E_L])){
661
+        ADC_Modify = 1;
662
+
663
+        Prev_data[INDEX_DAC_VCtrl_E_H] = data_buf[INDEX_DAC_VCtrl_E_H];
664
+        Prev_data[INDEX_DAC_VCtrl_E_L] = data_buf[INDEX_DAC_VCtrl_E_L];        
665
+    }
666
+    if((Prev_data[INDEX_DAC_VCtrl_F_H] != data_buf[INDEX_DAC_VCtrl_F_H])
667
+        ||(Prev_data[INDEX_DAC_VCtrl_F_L] != data_buf[INDEX_DAC_VCtrl_F_L])){
668
+        ADC_Modify = 1;
669
+        Prev_data[INDEX_DAC_VCtrl_F_H] = data_buf[INDEX_DAC_VCtrl_F_H];
670
+        Prev_data[INDEX_DAC_VCtrl_F_L] = data_buf[INDEX_DAC_VCtrl_F_L];        
671
+    }
672
+    if((Prev_data[INDEX_DAC_VCtrl_G_H] != data_buf[INDEX_DAC_VCtrl_G_H])
673
+        ||(Prev_data[INDEX_DAC_VCtrl_G_L] != data_buf[INDEX_DAC_VCtrl_G_L])){
674
+        ADC_Modify = 1;
675
+        Prev_data[INDEX_DAC_VCtrl_G_H] = data_buf[INDEX_DAC_VCtrl_G_H];
676
+        Prev_data[INDEX_DAC_VCtrl_G_L] = data_buf[INDEX_DAC_VCtrl_G_L];        
677
+    }    
678
+    if((Prev_data[INDEX_DAC_VCtrl_H_H] != data_buf[INDEX_DAC_VCtrl_H_H])
679
+        ||(Prev_data[INDEX_DAC_VCtrl_H_L] != data_buf[INDEX_DAC_VCtrl_H_L])){
680
+        ADC_Modify = 1;
681
+        Prev_data[INDEX_DAC_VCtrl_H_H] = data_buf[INDEX_DAC_VCtrl_H_H];
682
+        Prev_data[INDEX_DAC_VCtrl_H_L] = data_buf[INDEX_DAC_VCtrl_H_L];        
683
+    }
684
+    if(ADC_Modify){
685
+//        AD5318_Ctrl(0xF000);
686
+//        HAL_Delay(1);
687
+//        AD5318_Ctrl(0x800C);
688
+//        AD5318_Ctrl(0x2FFF );
689
+//        AD5318_Ctrl(0xA000);
690
+//        printf("DAC CTRL START \r\n");
691
+//        AD5318_Ctrl(0x800C);
692
+//        AD5318_Ctrl(0xA000);
693
+//        printf("DAC Change\r\n");
694
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_A_H] << 8 | Prev_data[INDEX_DAC_VCtrl_A_L]));    
695
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_B_H] << 8 | Prev_data[INDEX_DAC_VCtrl_B_L]));    
696
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_C_H] << 8 | Prev_data[INDEX_DAC_VCtrl_C_L]));
697
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_D_H] << 8 | Prev_data[INDEX_DAC_VCtrl_D_L]));
698
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_E_H] << 8 | Prev_data[INDEX_DAC_VCtrl_E_L]));    
699
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_F_H] << 8 | Prev_data[INDEX_DAC_VCtrl_F_L]));
700
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_G_H] << 8 | Prev_data[INDEX_DAC_VCtrl_G_L]));
701
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_H_H] << 8 | Prev_data[INDEX_DAC_VCtrl_H_L]));
702
+    }
703
+    
704
+}
705
+
706
+uint8_t temp_crc = 0;
707
+bool RF_Ctrl_Main(uint8_t* data_buf){
708
+    bool ret = false;
709
+    Bluecell_Prot_t type = data_buf[Type];
710
+    ret = RF_Data_Check(&data_buf[Header]); /* ERROR CHECK */
711
+    if(ret == false){
712
+        HAL_UART_Transmit(&huart1,&data_buf[INDEX_BLUE_HEADER],data_buf[INDEX_BLUE_LENGTH] + 2 + 1,3000); 
713
+        return ret;
714
+    }
715
+    
716
+    switch(type){
717
+    case TYPE_BLUECELL_RESET:
718
+        for(uint8_t i =0 ; i < data_buf[Length] + 6; i++)
719
+            printf("%02x ",data_buf[i]);
720
+        printf("Reset Start \r\n");
721
+        NVIC_SystemReset();
722
+        break;
723
+    case TYPE_BLUECELL_SET:
724
+#if 0 // PYJ.2019.07.31_BEGIN -- 
725
+    printf("TYPE_BLUECELL_SET : ");
726
+    for(uint8_t i =0 ; i < INDEX_BLUE_EOF + 1; i++)
727
+        printf("%02x ",data_buf[i]);
728
+#endif // PYJ.2019.07.31_END -- 
729
+        RF_Operate(&data_buf[Header]);
730
+        RF_Status_Ack();
731
+
732
+//        ADF4153_Freq_Calc(3465500000,40000000,2,5000);
733
+//        ADF4153_Freq_Calc(3993450000,40000000,2,5000);
734
+//        halSynSetFreq(1995000000);
735
+//        halSynSetFreq(1600000000);
736
+//        halSynSetFreq(1455000000);        
737
+        break;
738
+    case TYPE_BLUECELL_GET:
739
+#if 0 // PYJ.2019.08.01_BEGIN -- 
740
+        printf("\r\nTYPE_BLUECELL_GET : \r\n");
741
+#endif // PYJ.2019.08.01_END -- 
742
+        RF_Status_Get();
743
+        break;
744
+    case TYPE_BLUECELL_SAVE:
745
+//        printf("\r\nFLASH Write\r\n");
746
+        Bluecell_Flash_Write(&Prev_data[INDEX_BLUE_HEADER]);
747
+        RF_Status_Ack();
748
+
749
+        break;
750
+        default:
751
+#ifdef DEBUG_PRINT // PYJ.2019.07.27_BEGIN --         
752
+            printf("Function : %s   LINE : %d    type : %d \r\n",__func__,__LINE__,type);
753
+#endif
754
+            break;
755
+    }
756
+    return ret;
757
+}

BIN
insight/STM32F103_ATTEN_PLL_Zig.si4project/STM32F103_ATTEN_PLL_Zig.sip_sym


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insight/STM32F103_ATTEN_PLL_Zig.si4project/STM32F103_ATTEN_PLL_Zig.sip_xab


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insight/STM32F103_ATTEN_PLL_Zig.si4project/STM32F103_ATTEN_PLL_Zig.sip_xad


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insight/STM32F103_ATTEN_PLL_Zig.si4project/STM32F103_ATTEN_PLL_Zig.sip_xc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/STM32F103_ATTEN_PLL_Zig.sip_xf


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insight/STM32F103_ATTEN_PLL_Zig.si4project/STM32F103_ATTEN_PLL_Zig.sip_xr


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insight/STM32F103_ATTEN_PLL_Zig.si4project/STM32F103_ATTEN_PLL_Zig.sip_xsb


BIN
insight/STM32F103_ATTEN_PLL_Zig.si4project/STM32F103_ATTEN_PLL_Zig.sip_xsd


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insight/STM32F103_ATTEN_PLL_Zig.si4project/STM32F103_ATTEN_PLL_Zig.siwork


BIN
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Device_ST_STM32F1xx_Include_stm32f103xe.h.sisc


BIN
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Device_ST_STM32F1xx_Include_stm32f1xx.h.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Device_ST_STM32F1xx_Include_system_stm32f1xx.h.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_arm_common_tables.h.sisc


BIN
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_arm_const_structs.h.sisc


BIN
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_arm_math.h.sisc


BIN
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_cmsis_armcc.h.sisc


BIN
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_cmsis_armcc_V6.h.sisc


BIN
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_cmsis_gcc.h.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_core_cm0.h.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_core_cm0plus.h.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_core_cm3.h.sisc


BIN
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_core_cm4.h.sisc


BIN
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_core_cm7.h.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_core_cmFunc.h.sisc


BIN
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_core_cmInstr.h.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_core_cmSimd.h.sisc


BIN
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_core_sc000.h.sisc


BIN
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_core_sc300.h.sisc


BIN
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_Legacy_stm32_hal_legacy.h.sisc


BIN
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal.h.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_adc.h.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_adc_ex.h.sisc


BIN
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_cortex.h.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_def.h.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_dma.h.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_dma_ex.h.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_exti.h.sisc


BIN
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_flash.h.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_flash_ex.h.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_gpio.h.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_gpio_ex.h.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_pwr.h.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_rcc.h.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_rcc_ex.h.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_tim.h.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_tim_ex.h.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_uart.h.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal.c.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_adc.c.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_adc_ex.c.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_cortex.c.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_dma.c.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_exti.c.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_flash.c.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_flash_ex.c.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_gpio.c.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_gpio_ex.c.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_pwr.c.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_rcc.c.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_rcc_ex.c.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_tim.c.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_tim_ex.c.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_uart.c.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_AD5318.h.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_BDA4601.h.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_CRC16.h.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_PE43711.h.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_adf4153.h.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_flash.h.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_hal_types.h.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_includes.h.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_main.h.sisc


BIN
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_pll_4113.h.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_stm32f1xx_hal_conf.h.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_stm32f1xx_it.h.sisc


BIN
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_uart.h.sisc


BIN
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_zig_operate.h.sisc


BIN
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_AD5318.c.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_BDA4601.c.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_CRC16.c.sisc


BIN
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_PE43711.c.sisc


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insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_adf4153.c.sisc


+ 0 - 0
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_flash.c.sisc


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