Index change / Power On off 추가 /

Debug/Src/main.su

@@ -1,6 +1,6 @@
 main.c:84:6:HAL_TIM_PeriodElapsedCallback	0	static
 main.c:93:5:_write	8	static
 main.c:99:6:Pol_Delay_us	8	static
-main.c:276:6:SystemClock_Config	96	static
+main.c:286:6:SystemClock_Config	96	static
 main.c:129:5:main	120	static
-main.c:717:6:Error_Handler	0	static
+main.c:727:6:Error_Handler	0	static

Inc/zig_operate.h

@@ -93,10 +93,10 @@ typedef enum{
     INDEX_PATH_EN_1_8G_UL   ,
     INDEX_PATH_EN_2_1G_DL   ,
     INDEX_PATH_EN_2_1G_UL   ,
-    INDEX_PATH_EN_3_5G_L,
-    INDEX_PATH_EN_3_5G_H,
-    INDEX_PATH_EN_3_5G_DL   =70,
+    INDEX_PATH_EN_3_5G_DL,
     INDEX_PATH_EN_3_5G_UL   ,
+    INDEX_PATH_EN_3_5G_H = 70,
+    INDEX_PATH_EN_3_5G_L,
     INDEX_PLL_ON_OFF_3_5G_H ,
     INDEX_PLL_ON_OFF_3_5G_L ,
     INDEX_T_SYNC_DL,

Src/includes.c

@@ -234,4 +234,16 @@ void ATTEN_PLL_PATH_Initialize(void){
     RF_Ctrl_Main(&Flash_Save_data[INDEX_BLUE_HEADER]);
     RF_Status_Get();
 }
-
+void Power_ON_OFF_Initialize(void){
+    HAL_GPIO_WritePin(PATH_EN_3_5G_L_GPIO_Port,PATH_EN_3_5G_L_Pin, GPIO_PIN_RESET);
+    HAL_GPIO_WritePin(PATH_EN_3_5G_H_GPIO_Port,PATH_EN_3_5G_H_Pin, GPIO_PIN_RESET);
+    HAL_GPIO_WritePin(PATH_EN_3_5G_DL_GPIO_Port,PATH_EN_3_5G_DL_Pin, GPIO_PIN_RESET);
+    HAL_GPIO_WritePin(PATH_EN_3_5G_UL_GPIO_Port,PATH_EN_3_5G_UL_Pin, GPIO_PIN_RESET);
+    HAL_GPIO_WritePin(PATH_EN_3_5G_L_GPIO_Port,PATH_EN_3_5G_L_Pin, GPIO_PIN_RESET);  
+    HAL_GPIO_WritePin(PLL_ON_OFF_3_5G_H_GPIO_Port,PLL_ON_OFF_3_5G_H_Pin, GPIO_PIN_RESET);
+    HAL_GPIO_WritePin(PLL_ON_OFF_3_5G_L_GPIO_Port,PLL_ON_OFF_3_5G_L_Pin, GPIO_PIN_RESET);  
+    HAL_GPIO_WritePin(PATH_EN_2_1G_DL_GPIO_Port,PATH_EN_2_1G_DL_Pin, GPIO_PIN_RESET);
+    HAL_GPIO_WritePin(PATH_EN_2_1G_UL_GPIO_Port,PATH_EN_2_1G_UL_Pin, GPIO_PIN_RESET);
+    HAL_GPIO_WritePin(PATH_EN_1_8G_DL_GPIO_Port,PATH_EN_1_8G_DL_Pin, GPIO_PIN_RESET);
+    HAL_GPIO_WritePin(PATH_EN_1_8G_UL_GPIO_Port,PATH_EN_1_8G_UL_Pin, GPIO_PIN_RESET);
+}

Src/main.c

@@ -165,30 +165,36 @@ int main(void)
 #endif /* DEBUG_PRINT */
     HAL_UART_Receive_DMA(&huart1, TerminalQueue.Buffer, 1);
     PE43711_PinInit();
-    HAL_GPIO_WritePin(PATH_EN_3_5G_L_GPIO_Port,PATH_EN_3_5G_L_Pin, GPIO_PIN_SET);
-    HAL_GPIO_WritePin(PATH_EN_3_5G_H_GPIO_Port,PATH_EN_3_5G_H_Pin, GPIO_PIN_SET);
-    HAL_GPIO_WritePin(PATH_EN_3_5G_DL_GPIO_Port,PATH_EN_3_5G_DL_Pin, GPIO_PIN_SET);
-    HAL_GPIO_WritePin(PATH_EN_3_5G_UL_GPIO_Port,PATH_EN_3_5G_UL_Pin, GPIO_PIN_SET);
-    HAL_GPIO_WritePin(PATH_EN_3_5G_L_GPIO_Port,PATH_EN_3_5G_L_Pin, GPIO_PIN_SET);  
-    HAL_GPIO_WritePin(PLL_ON_OFF_3_5G_H_GPIO_Port,PLL_ON_OFF_3_5G_H_Pin, GPIO_PIN_SET);
-    HAL_GPIO_WritePin(PLL_ON_OFF_3_5G_L_GPIO_Port,PLL_ON_OFF_3_5G_L_Pin, GPIO_PIN_SET);  
-    HAL_GPIO_WritePin(PATH_EN_2_1G_DL_GPIO_Port,PATH_EN_2_1G_DL_Pin, GPIO_PIN_SET);
-    HAL_GPIO_WritePin(PATH_EN_2_1G_UL_GPIO_Port,PATH_EN_2_1G_UL_Pin, GPIO_PIN_SET);
-    HAL_GPIO_WritePin(PATH_EN_1_8G_DL_GPIO_Port,PATH_EN_1_8G_DL_Pin, GPIO_PIN_SET);
-    HAL_GPIO_WritePin(PATH_EN_1_8G_UL_GPIO_Port,PATH_EN_1_8G_UL_Pin, GPIO_PIN_SET);
+    
+    HAL_GPIO_WritePin(PATH_EN_3_5G_L_GPIO_Port,PATH_EN_3_5G_L_Pin, GPIO_PIN_RESET);
+    HAL_GPIO_WritePin(PATH_EN_3_5G_H_GPIO_Port,PATH_EN_3_5G_H_Pin, GPIO_PIN_RESET);
+    HAL_GPIO_WritePin(PATH_EN_3_5G_DL_GPIO_Port,PATH_EN_3_5G_DL_Pin, GPIO_PIN_RESET);
+    HAL_GPIO_WritePin(PATH_EN_3_5G_UL_GPIO_Port,PATH_EN_3_5G_UL_Pin, GPIO_PIN_RESET);
+    HAL_GPIO_WritePin(PATH_EN_3_5G_L_GPIO_Port,PATH_EN_3_5G_L_Pin, GPIO_PIN_RESET);  
+    HAL_GPIO_WritePin(PLL_ON_OFF_3_5G_H_GPIO_Port,PLL_ON_OFF_3_5G_H_Pin, GPIO_PIN_RESET);
+    HAL_GPIO_WritePin(PLL_ON_OFF_3_5G_L_GPIO_Port,PLL_ON_OFF_3_5G_L_Pin, GPIO_PIN_RESET);  
+    HAL_GPIO_WritePin(PATH_EN_2_1G_DL_GPIO_Port,PATH_EN_2_1G_DL_Pin, GPIO_PIN_RESET);
+    HAL_GPIO_WritePin(PATH_EN_2_1G_UL_GPIO_Port,PATH_EN_2_1G_UL_Pin, GPIO_PIN_RESET);
+    HAL_GPIO_WritePin(PATH_EN_1_8G_DL_GPIO_Port,PATH_EN_1_8G_DL_Pin, GPIO_PIN_RESET);
+    HAL_GPIO_WritePin(PATH_EN_1_8G_UL_GPIO_Port,PATH_EN_1_8G_UL_Pin, GPIO_PIN_RESET);
+
+    
     HAL_GPIO_WritePin(_T_SYNC_UL_GPIO_Port,_T_SYNC_UL_Pin, GPIO_PIN_RESET);
     HAL_GPIO_WritePin(T_SYNC_UL_GPIO_Port,T_SYNC_UL_Pin, GPIO_PIN_RESET);
     HAL_GPIO_WritePin(_T_SYNC_DL_GPIO_Port,_T_SYNC_DL_Pin, GPIO_PIN_SET);
-    HAL_GPIO_WritePin(T_SYNC_DL_GPIO_Port,T_SYNC_DL_Pin, GPIO_PIN_SET);                
+    HAL_GPIO_WritePin(T_SYNC_DL_GPIO_Port,T_SYNC_DL_Pin, GPIO_PIN_SET);     
+    
     HAL_Delay(1);
     Path_Init();
     ADF4153_Init();
     SubmitDAC(0x800C);
     SubmitDAC(0xA000);
-#if 1 // PYJ.2019.07.30_BEGIN -- 
+    HAL_Delay(1);
+#if 1
+// PYJ.2019.07.30_BEGIN -- 
     SubmitDAC(0x0FFF);
     SubmitDAC(0x13FF);
-    SubmitDAC(0x23FF);
+    SubmitDAC(0x2FFF);
     SubmitDAC(0x35FF);
     SubmitDAC(0x46FF);
     SubmitDAC(0x57FF);
@@ -210,8 +216,10 @@ int main(void)
 //  BDA4601_Test();
     HAL_ADCEx_Calibration_Start(&hadc1);
     ADF4153_R_N_Reg_st temp_reg;
+#if 0 // PYJ.2019.08.01_BEGIN -- 
     Bluecell_Flash_Read(&Flash_Save_data[INDEX_BLUE_HEADER]);
     ATTEN_PLL_PATH_Initialize();
+#endif // PYJ.2019.08.01_END -- 
 
 //  ADF_Module_Ctrl(Pll_test,0x324000,0x144051,0x0017c2,0x0003c7);
 
@@ -223,12 +231,14 @@ int main(void)
 //   HAL_ADC_Start_DMA(&hadc1, (uint32_t*)ADCvalue, ADC_EA);
   while (1)
   {
-    if(HAL_GPIO_ReadPin(PLL_LD_3_5G_H_GPIO_Port, PLL_LD_3_5G_H_Pin) == GPIO_PIN_RESET){
+    if(HAL_GPIO_ReadPin(PLL_LD_3_5G_H_GPIO_Port, PLL_LD_3_5G_H_Pin) == GPIO_PIN_RESET 
+        && HAL_GPIO_ReadPin(PLL_ON_OFF_3_5G_H_GPIO_Port, PLL_ON_OFF_3_5G_H_Pin) == GPIO_PIN_SET){
         temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
         ADF4153_Module_Ctrl(Pll_3_5_H,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
         HAL_Delay(1);
     }
-    if(HAL_GPIO_ReadPin(PLL_LD_3_5G_L_GPIO_Port, PLL_LD_3_5G_L_Pin) == GPIO_PIN_RESET){
+    if(HAL_GPIO_ReadPin(PLL_LD_3_5G_L_GPIO_Port, PLL_LD_3_5G_L_Pin) == GPIO_PIN_RESET
+        || HAL_GPIO_ReadPin(PLL_ON_OFF_3_5G_L_GPIO_Port, PLL_ON_OFF_3_5G_L_Pin) == GPIO_PIN_SET){
         temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
         ADF4153_Module_Ctrl(Pll_3_5_L,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
         HAL_Delay(1);

Src/zig_operate.c

@@ -336,7 +336,6 @@ void RF_Operate(uint8_t* data_buf){
         ALL_ATT_3_5G.data4 = Prev_data[INDEX_ATT_3_5G_COM3] = data_buf[INDEX_ATT_3_5G_COM3];
         PE43711_ALL_atten_ctrl(ALL_ATT_3_5G);
     }
-
     if((Prev_data[INDEX_PLL_1_8G_DL_H] != data_buf[INDEX_PLL_1_8G_DL_H])
         && (Prev_data[INDEX_PLL_1_8G_DL_L] != data_buf[INDEX_PLL_1_8G_DL_L])
     ){
@@ -566,7 +565,6 @@ void RF_Operate(uint8_t* data_buf){
     if((Prev_data[INDEX_DAC_VCtrl_A_H] != data_buf[INDEX_DAC_VCtrl_A_H])
         ||(Prev_data[INDEX_DAC_VCtrl_A_L] != data_buf[INDEX_DAC_VCtrl_A_L])){
         ADC_Modify = 1;
-
         Prev_data[INDEX_DAC_VCtrl_A_H] = data_buf[INDEX_DAC_VCtrl_A_H];
         Prev_data[INDEX_DAC_VCtrl_A_L] = data_buf[INDEX_DAC_VCtrl_A_L];
     }
@@ -580,6 +578,8 @@ void RF_Operate(uint8_t* data_buf){
     if((Prev_data[INDEX_DAC_VCtrl_C_H] != data_buf[INDEX_DAC_VCtrl_C_H])
         ||(Prev_data[INDEX_DAC_VCtrl_C_L] != data_buf[INDEX_DAC_VCtrl_C_L])){
         ADC_Modify = 1;
+        printf("Prev_data[INDEX_DAC_VCtrl_C_H] : %x \r\n",Prev_data[INDEX_DAC_VCtrl_C_H]);
+        printf("Prev_data[INDEX_DAC_VCtrl_C_L] : %x \r\n",Prev_data[INDEX_DAC_VCtrl_C_L]);
 
         Prev_data[INDEX_DAC_VCtrl_C_H] = data_buf[INDEX_DAC_VCtrl_C_H];
         Prev_data[INDEX_DAC_VCtrl_C_L] = data_buf[INDEX_DAC_VCtrl_C_L];        
@@ -619,10 +619,14 @@ void RF_Operate(uint8_t* data_buf){
 //        SubmitDAC(0xF000);
 //        HAL_Delay(1);
 //        SubmitDAC(0x800C);
+//        SubmitDAC(0x2FFF );
+//        SubmitDAC(0xA000);
+        printf("DAC CTRL START \r\n");
+//        SubmitDAC(0x800C);
 //        SubmitDAC(0xA000);
-        SubmitDAC((Prev_data[INDEX_DAC_VCtrl_A_H] << 8 | Prev_data[INDEX_DAC_VCtrl_A_L]) );    
+
+        SubmitDAC((Prev_data[INDEX_DAC_VCtrl_A_H] << 8 | Prev_data[INDEX_DAC_VCtrl_A_L]));    
         SubmitDAC((Prev_data[INDEX_DAC_VCtrl_B_H] << 8 | Prev_data[INDEX_DAC_VCtrl_B_L]));    
-//        SubmitDAC(0x2FFF );
         SubmitDAC((Prev_data[INDEX_DAC_VCtrl_C_H] << 8 | Prev_data[INDEX_DAC_VCtrl_C_L]));
         SubmitDAC((Prev_data[INDEX_DAC_VCtrl_D_H] << 8 | Prev_data[INDEX_DAC_VCtrl_D_L]));
         SubmitDAC((Prev_data[INDEX_DAC_VCtrl_E_H] << 8 | Prev_data[INDEX_DAC_VCtrl_E_L]));    
@@ -657,8 +661,6 @@ bool RF_Ctrl_Main(uint8_t* data_buf){
         printf("%02x ",data_buf[i]);
 #endif // PYJ.2019.07.31_END -- 
         RF_Operate(&data_buf[Header]);
-        
-
 //        ADF4153_Freq_Calc(3465500000,40000000,2,5000);
 //        ADF4153_Freq_Calc(3993450000,40000000,2,5000);
 //        halSynSetFreq(1995000000);
@@ -670,6 +672,7 @@ bool RF_Ctrl_Main(uint8_t* data_buf){
         RF_Status_Get();
         break;
     case TYPE_BLUECELL_SAVE:
+        printf("\r\nFLASH Write\r\n");
         Bluecell_Flash_Write(&Prev_data[INDEX_BLUE_HEADER]);
         break;
         default:

insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/adf4153(3476).c

@@ -0,0 +1,398 @@
+/******************************************************************************
+*   @file   ADF4153.c
+*   @brief  Implementation of ADF4153 Driver for Microblaze processor.
+*   @author Istvan Csomortani (istvan.csomortani@analog.com)
+*
+*******************************************************************************
+* Copyright 2013(c) Analog Devices, Inc.
+*
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted provided that the following conditions are met:
+*  - Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*  - Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in
+*    the documentation and/or other materials provided with the
+*    distribution.
+*  - Neither the name of Analog Devices, Inc. nor the names of its
+*    contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*  - The use of this software may or may not infringe the patent rights
+*    of one or more patent holders.  This license does not release you
+*    from the requirement that you obtain separate licenses from these
+*    patent holders to use this software.
+*  - Use of the software either in source or binary form, must be run
+*    on or directly connected to an Analog Devices Inc. component.
+*
+* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED
+* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY
+* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+* INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+/*****************************************************************************/
+/****************************** Include Files ********************************/
+/*****************************************************************************/
+#include "adf4153.h"
+typedef struct _adf4153_st{
+    unsigned long long PFD_Value;
+    uint16_t MOD_Value;
+    uint32_t FRAC_Value;
+    uint16_t INT_Value;    
+    double N_Value;
+}adf4153_st;
+
+uint32_t pow2(uint32_t val,int32_t val2){
+    for(uint8_t i = 0; i < val2 - 1; i++){
+        val = val * val;
+    }
+
+    return val;
+}
+
+double round_up( double value, int pos )
+{
+    double temp;
+    temp = value * pow2( 10, pos );  // �썝�븯�뒗 �냼�닔�젏 �옄由ъ닔留뚰겮 10�쓽 �늻�듅�쓣 �븿
+    temp =  (int)(temp + 0.5);          // 0.5瑜� �뜑�븳�썑 踰꾨┝�븯硫� 諛섏삱由쇱씠 �맖
+    temp *= pow2( 10, -pos );           // �떎�떆 �썝�옒 �냼�닔�젏 �옄由ъ닔濡�
+
+    return temp;
+}
+
+
+double N_Reg_Value_Calc(double val){
+    return  val / 1000;
+}
+uint32_t N_Divider_Reg_Create(uint16_t _FRAC,uint16_t _INT,uint8_t _FASTLOCK){
+    uint32_t ret = 0;
+    uint32_t shift_bit = 0x01;
+    uint8_t control_bit = 0;
+    uint8_t i = 0;
+#ifdef DEBUG_PRINT
+    printf("FRAC : %d INT : %d \r\n",(int)_FRAC,_INT);
+#endif /* DEBUG_PRINT */
+    for(i = 0; i < 2; i++){
+        if(control_bit & 0x01)
+            ret += shift_bit << i;
+        control_bit = control_bit >> 1;
+    }
+#ifdef DEBUG_PRINT
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);
+#endif /* DEBUG_PRINT */
+    for(i = 2; i < 14; i++){
+        if(_FRAC & 0x01)
+            ret += shift_bit << i;
+        _FRAC = _FRAC >> 1;
+    }
+#ifdef DEBUG_PRINT
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);    
+#endif /* DEBUG_PRINT */
+    for(i = 14; i < 22; i++){
+        if(_INT & 0x01)
+            ret += shift_bit << i;
+        _INT = _INT >> 1;
+    }  
+#ifdef DEBUG_PRINT
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);    
+#endif /* DEBUG_PRINT */
+    if(_FASTLOCK & 0x01)
+            ret += shift_bit << i;
+#ifdef DEBUG_PRINT
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);
+#endif /* DEBUG_PRINT */
+
+    return ret;
+}
+uint32_t R_Divider_Reg_Create(uint16_t _MOD,uint8_t _RCOUNTER,uint8_t _PRESCALER,uint8_t _RESERVED,uint8_t _MUXOUT,uint8_t LOAD_CONTROL){
+    uint32_t ret = 0;
+    uint32_t shift_bit = 0x01;
+    uint8_t control_bit = 1;
+    uint8_t i = 0;
+#ifdef DEBUG_PRINT
+    printf("_MOD : %d INT : %d \r\n",_MOD,_RCOUNTER);
+#endif /* DEBUG_PRINT */
+
+#ifdef DEBUG_PRINT
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);
+#endif /* DEBUG_PRINT */
+    for(i = 0; i < 2; i++){
+        if(control_bit & 0x01)
+            ret += shift_bit << i;
+        control_bit = control_bit >> 1;
+    }
+#ifdef DEBUG_PRINT
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);
+#endif /* DEBUG_PRINT */
+    for(i = 2; i < 14; i++){
+        if(_MOD & 0x01)
+            ret += shift_bit << i;
+        _MOD = _MOD >> 1;
+    }
+    for(i = 14; i < 18; i++){
+        if(_RCOUNTER & 0x01)
+            ret += shift_bit << i;
+        _RCOUNTER = _RCOUNTER >> 1;
+    }  
+    if(_PRESCALER & 0x01)
+            ret += shift_bit << i++;
+    if(_RESERVED & 0x01)
+            ret += shift_bit << i++;
+    for(i = 19; i < 22; i++){
+        if(_MUXOUT & 0x01)
+            ret += shift_bit << i;
+        _MUXOUT = _MUXOUT >> 1;
+    }   
+    if(LOAD_CONTROL & 0x01)
+        ret += shift_bit << i++;
+
+    return ret;
+}
+
+ADF4153_R_N_Reg_st ADF4153_Freq_Calc(unsigned long long Freq,unsigned long long REFin,uint8_t R_Counter,uint32_t chspacing){
+    adf4153_st temp_adf4153;
+    double temp = 0;
+    ADF4153_R_N_Reg_st temp_reg;
+    temp_adf4153.PFD_Value  =  REFin / (R_Counter * 1000);
+    temp_adf4153.MOD_Value  =  (temp_adf4153.PFD_Value / chspacing) * 1000;
+    temp_adf4153.N_Value    =  N_Reg_Value_Calc(((double)(Freq / 1000) /  (double)(temp_adf4153.PFD_Value / 1000)));
+    temp_adf4153.INT_Value  =   temp_adf4153.N_Value ;
+#ifdef DEBUG_PRINT
+    printf("\r\ntemp_adf4153.N_Value : %f  temp_adf4153.INT_Value : %f  temp_adf4153.MOD_Value : %f \r\n",temp_adf4153.N_Value,(double)temp_adf4153.INT_Value,(double)temp_adf4153.MOD_Value);
+#endif /* DEBUG_PRINT */
+    temp = temp_adf4153.N_Value - (double)temp_adf4153.INT_Value;
+#ifdef DEBUG_PRINT
+    printf("\r\n temp_adf4153.N_Value - (double)temp_adf4153.INT_Value) : %f  temp * (double)temp_adf4153.MOD_Value : %f \r\n",temp,temp * (double)temp_adf4153.MOD_Value);
+#endif /* DEBUG_PRINT */
+    temp_adf4153.FRAC_Value =  (float)temp * temp_adf4153.MOD_Value;
+   
+#ifdef DEBUG_PRINT
+    printf("\r\ntemp_adf4153.N_Value : %x   : %f ",temp_adf4153.N_Value,((double)(Freq / 1000) /  (double)(temp_adf4153.PFD_Value / 1000)) / 1000);
+    printf("temp_adf4153.MOD_Value : %x   : %d \r\n",temp_adf4153.MOD_Value,temp_adf4153.MOD_Value);
+#endif /* DEBUG_PRINT */
+    uint16_t tempmod = temp_adf4153.FRAC_Value;
+    for(uint8_t i = 0; i < 12; i++){
+#ifdef DEBUG_PRINT
+        if(temp_adf4153.MOD_Value & 0x800){
+            printf("1");
+        }else{
+            printf("0");
+        }
+#endif /* DEBUG_PRINT */
+        tempmod = tempmod << 1;
+    }
+#ifdef DEBUG_PRINT
+    printf("\r\n");
+    printf("temp_adf4153.FRAC_Value : %x   : %d\r\n",temp_adf4153.FRAC_Value,temp_adf4153.FRAC_Value);
+#endif /* DEBUG_PRINT */
+    uint16_t tempfrac = temp_adf4153.FRAC_Value;
+    for(uint8_t i = 0; i < 12; i++){
+#ifdef DEBUG_PRINT
+        if(tempfrac & 0x800){
+            printf("1");
+        }else{
+            printf("0");
+        }
+#endif /* DEBUG_PRINT */
+        tempfrac = tempfrac << 1;
+    }
+#ifdef DEBUG_PRINT
+    printf("\r\n");    
+#endif /* DEBUG_PRINT */
+#ifdef DEBUG_PRINT
+    printf("temp_adf4153.INT_Value : %x   : %d\r\n",temp_adf4153.INT_Value,temp_adf4153.INT_Value); 
+#endif /* DEBUG_PRINT */
+    uint16_t tempint = temp_adf4153.INT_Value;
+    for(uint8_t i = 0; i < 9; i++){
+#ifdef DEBUG_PRINT
+        if(tempint & 0x100){
+            printf("1");
+        }else{
+            printf("0");
+        }
+#endif /* DEBUG_PRINT */
+        tempint = tempint << 1;
+    }
+#ifdef DEBUG_PRINT
+    printf("\r\n");    
+
+    printf("R0: %x  R1: %x \r\n",N_Divider_Reg_Create(temp_adf4153.FRAC_Value,temp_adf4153.INT_Value,0),R_Divider_Reg_Create(temp_adf4153.MOD_Value,R_Counter,1,0,2,0));   
+#endif /* DEBUG_PRINT */
+    temp_reg.N_reg = N_Divider_Reg_Create(temp_adf4153.FRAC_Value,temp_adf4153.INT_Value,0);
+    temp_reg.R_reg = R_Divider_Reg_Create(temp_adf4153.MOD_Value,R_Counter,1,0,2,0);
+
+    return temp_reg;
+//    R_Divider_Reg_Create(temp_adf4153.MOD_Value,R_Counter,1,0,1,0); //prescaler 1 : 8/9 0: 4/5
+}
+void ADF4153_Init(void){
+PLL_Setting_st Pll_test = {
+      PLL_CLK_3_5G_GPIO_Port,
+      PLL_CLK_3_5G_Pin,
+      PLL_DATA_3_5G_GPIO_Port,
+      PLL_DATA_3_5G_Pin,
+    PLL_EN_3_5G_L_GPIO_Port,    
+    PLL_EN_3_5G_L_Pin,
+  };
+PLL_Setting_st Pll_test2 = {
+    PLL_CLK_3_5G_GPIO_Port,
+    PLL_CLK_3_5G_Pin,
+    PLL_DATA_3_5G_GPIO_Port,
+    PLL_DATA_3_5G_Pin,
+    PLL_EN_3_5G_H_GPIO_Port,    
+    PLL_EN_3_5G_H_Pin,
+  };          
+    //  ADF4153_Module_Ctrl(Pll_test,0x2B44B0,0x14BE81,0x0013C2,0x000003);
+      ADF4153_R_N_Reg_st temp_reg;
+      temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
+      ADF4153_Module_Ctrl(Pll_test,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);      
+    
+      HAL_Delay(1);
+#ifdef DEBUG_PRINT
+        printf("\r\nPLL_EN_3_5G_H_GPIO_Port\r\n");
+#endif /* DEBUG_PRINT */
+   
+        temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
+        ADF4153_Module_Ctrl(Pll_test2,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);                  
+    //  ADF4153_Module_Ctrl(Pll_test2,0x313840,0x14BE81,0x13C2,0x3);
+      HAL_Delay(1);
+
+
+}
+
+void ADF4153_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2,uint32_t R3){
+    R3  = R3  & 0x0007FF;
+    R2 = R2 & 0x00FFFF;
+    R1 = R1 & 0xFFFFFF;
+    R0 = R0 & 0xFFFFFF;
+//    ADF4153_Freq_Calc(3461500000,40000000,2,5000);
+    HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
+    HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
+#ifdef DEBUG_PRINT
+    printf("YJ :R0: %x  R1:  %x   R2 : %x R3 : %x ",R0,R1,R2,R3);
+    printf("\r\n");
+#endif /* DEBUG_PRINT */
+    /*   R3 Ctrl    */
+    for(int i =0; i < 11; i++){
+        if(R3 & 0x000400){
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_SET);
+#ifdef DEBUG_PRINT
+            printf("1");
+#endif /* DEBUG_PRINT */
+        }
+        else{
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
+#ifdef DEBUG_PRINT
+            printf("0");
+#endif /* DEBUG_PRINT */
+        }
+        Pol_Delay_us(50);
+        HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
+        Pol_Delay_us(50);
+        HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
+        R3 = (R3 << 1);
+    }
+#ifdef DEBUG_PRINT
+    printf("\r\n");
+#endif /* DEBUG_PRINT */
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
+      Pol_Delay_us(50);
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
+    
+    /*   R2 Ctrl    */
+     for(int i =0; i < 16; i++){
+         if(R2 & 0x008000){
+             HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_SET);
+#ifdef DEBUG_PRINT
+             printf("1");
+#endif /* DEBUG_PRINT */
+         }
+         else{
+             HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
+#ifdef DEBUG_PRINT
+             printf("0");
+#endif /* DEBUG_PRINT */
+         }
+         Pol_Delay_us(50);
+         HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
+         Pol_Delay_us(50);
+         HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
+
+         R2 = ((R2 << 1) & 0x00FFFF);
+     }
+#ifdef DEBUG_PRINT
+     printf("\r\n");
+#endif /* DEBUG_PRINT */
+     HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
+      Pol_Delay_us(50);
+     HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
+    
+     /*   R1 Ctrl    */
+    for(int i =0; i < 24; i++){
+        if(R1 & 0x800000){
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_SET);
+#ifdef DEBUG_PRINT
+            printf("1");
+#endif /* DEBUG_PRINT */
+        }
+        else{
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
+#ifdef DEBUG_PRINT
+            printf("0");
+#endif /* DEBUG_PRINT */
+        }
+        Pol_Delay_us(50);
+        HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
+        Pol_Delay_us(50);
+        HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
+
+        R1 = ((R1 << 1) & 0xFFFFFF);
+    }
+#ifdef DEBUG_PRINT
+    printf("\r\n");
+#endif /* DEBUG_PRINT */
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
+      Pol_Delay_us(50);
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
+
+
+        /*   R0 Ctrl    */
+   
+    for(int i =0; i < 24; i++){
+        if(R0 & 0x800000){
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_SET);
+#ifdef DEBUG_PRINT
+            printf("1");
+#endif /* DEBUG_PRINT */
+        }
+        else{
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
+#ifdef DEBUG_PRINT
+            printf("0");
+#endif /* DEBUG_PRINT */
+        }
+        Pol_Delay_us(50);
+        HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
+        Pol_Delay_us(50);
+        HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
+
+        R0 = ((R0 << 1) & 0xFFFFFF);
+    }
+#ifdef DEBUG_PRINT
+    printf("\r\n");
+#endif /* DEBUG_PRINT */
+    HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
+    Pol_Delay_us(50);
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
+
+}

insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/includes(8004).c

@@ -0,0 +1,237 @@
+/*
+ * includes.c
+ *
+ *  Created on: 2019. 7. 28.
+ *      Author: parkyj
+ */
+#include "includes.h"
+
+#define MACROSTR(k) #k
+
+
+static char *Bluecell_Prot_IndexStr[] = {
+    MACROSTR(INDEX_ATT_1_8G_DL1     ),
+    MACROSTR(INDEX_ATT_1_8G_DL2     ),
+    MACROSTR(INDEX_ATT_1_8G_UL1     ),
+    MACROSTR(INDEX_ATT_1_8G_UL2     ),
+    MACROSTR(INDEX_ATT_1_8G_UL3     ),
+    MACROSTR(INDEX_ATT_1_8G_UL4     ),
+    MACROSTR(INDEX_ATT_2_1G_DL1     ),
+    MACROSTR(INDEX_ATT_2_1G_DL2     ),
+    MACROSTR(INDEX_ATT_2_1G_UL1     ),
+    MACROSTR(INDEX_ATT_2_1G_UL2     ),
+    MACROSTR(INDEX_ATT_2_1G_UL3     ),
+    MACROSTR(INDEX_ATT_2_1G_UL4     ),
+    MACROSTR(INDEX_ATT_3_5G_DL      ),
+    MACROSTR(INDEX_ATT_3_5G_UL      ),
+    MACROSTR(INDEX_ATT_3_5G_COM1    ),
+    MACROSTR(INDEX_ATT_3_5G_COM2    ),
+    MACROSTR(INDEX_ATT_3_5G_COM3    ),
+    MACROSTR(INDEX_PLL_1_8G_DL_H    ),
+    MACROSTR(INDEX_PLL_1_8G_DL_L    ),
+    MACROSTR(INDEX_PLL_1_8G_UL_H    ),
+    MACROSTR(INDEX_PLL_1_8G_UL_L    ),
+    MACROSTR(INDEX_PLL_2_1G_DL_H    ),
+    MACROSTR(INDEX_PLL_2_1G_DL_L    ),
+    MACROSTR(INDEX_PLL_2_1G_UL_H    ),
+    MACROSTR(INDEX_PLL_2_1G_UL_L    ),
+    MACROSTR(INDEX_PLL_3_5G_DL_H    ),
+    MACROSTR(INDEX_PLL_3_5G_DL_L    ),
+    MACROSTR(INDEX_PLL_3_5G_UL_H    ),
+    MACROSTR(INDEX_PLL_3_5G_UL_L    ),
+    MACROSTR(INDEX_PLL_LD_6_BIT     ),
+    MACROSTR(INDEX_DET_1_8G_DL_IN_H ),
+    MACROSTR(INDEX_DET_1_8G_DL_IN_L ),
+    MACROSTR(INDEX_DET_1_8G_DL_OUT_H),
+    MACROSTR(INDEX_DET_1_8G_DL_OUT_L),
+    MACROSTR(INDEX_DET_1_8G_UL_IN_H ),
+    MACROSTR(INDEX_DET_1_8G_UL_IN_L ),
+    MACROSTR(INDEX_DET_1_8G_UL_OUT_H),
+    MACROSTR(INDEX_DET_1_8G_UL_OUT_L),
+    MACROSTR(INDEX_DET_2_1G_DL_IN_H ),
+    MACROSTR(INDEX_DET_2_1G_DL_IN_L ),
+    MACROSTR(INDEX_DET_2_1G_DL_OUT_H),
+    MACROSTR(INDEX_DET_2_1G_DL_OUT_L),
+    MACROSTR(INDEX_DET_2_1G_UL_IN_H ),
+    MACROSTR(INDEX_DET_2_1G_UL_IN_L ),
+    MACROSTR(INDEX_DET_2_1G_UL_OUT_H),
+    MACROSTR(INDEX_DET_2_1G_UL_OUT_L),
+    MACROSTR(INDEX_DET_3_5G_DL_IN_H ),
+    MACROSTR(INDEX_DET_3_5G_DL_IN_L ),
+    MACROSTR(INDEX_DET_3_5G_DL_OUT_L),
+    MACROSTR(INDEX_DET_3_5G_DL_OUT_H),
+    MACROSTR(INDEX_DET_3_5G_UL_IN_H ),
+    MACROSTR(INDEX_DET_3_5G_UL_IN_L ),
+    MACROSTR(INDEX_DET_3_5G_UL_OUT_H),
+    MACROSTR(INDEX_DET_3_5G_UL_OUT_L),
+    MACROSTR(INDEX_RFU_TEMP_H       ),
+    MACROSTR(INDEX_RFU_TEMP_L       ),
+    MACROSTR(INDEX__28V_DET_H       ),
+    MACROSTR(INDEX__28V_DET_L       ),
+    MACROSTR(INDEX_ALARM_AC         ),
+    MACROSTR(INDEX_ALARM_DC         ),
+    MACROSTR(INDEX_PATH_EN_1_8G_DL  ),
+    MACROSTR(INDEX_PATH_EN_1_8G_UL  ),
+    MACROSTR(INDEX_PATH_EN_2_1G_DL  ),
+    MACROSTR(INDEX_PATH_EN_2_1G_UL  ),
+    MACROSTR(INDEX_PATH_EN_3_5G_L   ),
+    MACROSTR(INDEX_PATH_EN_3_5G_H   ),
+    MACROSTR(INDEX_PATH_EN_3_5G_DL  ),
+    MACROSTR(INDEX_PATH_EN_3_5G_UL  ),
+    MACROSTR(INDEX_PLL_ON_OFF_3_5G_H),
+    MACROSTR(INDEX_PLL_ON_OFF_3_5G_L),
+    MACROSTR(INDEX_T_SYNC_DL        ),
+    MACROSTR(INDEX__T_SYNC_DL       ),
+    MACROSTR(INDEX_T_SYNC_UL        ),
+    MACROSTR(INDEX__T_SYNC_UL       ),   
+};
+
+static void kConstPrinter(Bluecell_Prot_Index k)
+{
+#ifdef DEBUG_PRINT
+    printf("%s", Bluecell_Prot_IndexStr[k]);
+#endif /* DEBUG_PRINT */
+}
+void Path_Init(void){
+    Prev_data[INDEX_PATH_EN_1_8G_DL]   = HAL_GPIO_ReadPin(PATH_EN_1_8G_DL_GPIO_Port,PATH_EN_1_8G_DL_Pin);
+    Prev_data[INDEX_PATH_EN_1_8G_UL]   = HAL_GPIO_ReadPin(PATH_EN_1_8G_UL_GPIO_Port,PATH_EN_1_8G_UL_Pin);
+    Prev_data[INDEX_PATH_EN_2_1G_DL]   = HAL_GPIO_ReadPin(PATH_EN_2_1G_DL_GPIO_Port,PATH_EN_2_1G_DL_Pin);
+    Prev_data[INDEX_PATH_EN_2_1G_UL]   = HAL_GPIO_ReadPin(PATH_EN_2_1G_UL_GPIO_Port,PATH_EN_2_1G_UL_Pin);
+    Prev_data[INDEX_PATH_EN_3_5G_L]    = HAL_GPIO_ReadPin(PATH_EN_3_5G_L_GPIO_Port,PATH_EN_3_5G_L_Pin);
+    Prev_data[INDEX_PATH_EN_3_5G_H]    = HAL_GPIO_ReadPin(PATH_EN_3_5G_H_GPIO_Port,PATH_EN_3_5G_H_Pin);
+    Prev_data[INDEX_PATH_EN_3_5G_DL]   = HAL_GPIO_ReadPin(PATH_EN_3_5G_DL_GPIO_Port,PATH_EN_3_5G_DL_Pin);
+    Prev_data[INDEX_PATH_EN_3_5G_UL]   = HAL_GPIO_ReadPin(PATH_EN_3_5G_UL_GPIO_Port,PATH_EN_3_5G_UL_Pin);
+    Prev_data[INDEX_PLL_ON_OFF_3_5G_H] = HAL_GPIO_ReadPin(PLL_ON_OFF_3_5G_H_GPIO_Port,PLL_ON_OFF_3_5G_H_Pin);
+    Prev_data[INDEX_PLL_ON_OFF_3_5G_L] = HAL_GPIO_ReadPin(PLL_ON_OFF_3_5G_L_GPIO_Port,PLL_ON_OFF_3_5G_L_Pin);
+}
+void Power_ON_OFF_Ctrl(uint8_t type,uint8_t cmd){
+    printf("\r\ntype : %s cmd : %d\r\n",Bluecell_Prot_IndexStr[type - 4],cmd);
+    switch(type){
+        case INDEX_PATH_EN_1_8G_DL  : 
+#if 0 // PYJ.2019.07.29_BEGIN -- 
+            printf("\r\n LINE %d\r\n",__LINE__);
+#endif // PYJ.2019.07.29_END -- 
+            if(cmd)
+                HAL_GPIO_WritePin(PATH_EN_1_8G_DL_GPIO_Port,PATH_EN_1_8G_DL_Pin, GPIO_PIN_SET);
+            else
+                HAL_GPIO_WritePin(PATH_EN_1_8G_DL_GPIO_Port,PATH_EN_1_8G_DL_Pin, GPIO_PIN_RESET);
+            break; 
+        case INDEX_PATH_EN_1_8G_UL  : 
+#if 0 // PYJ.2019.07.29_BEGIN -- 
+            printf("\r\n LINE %d\r\n",__LINE__);
+#endif // PYJ.2019.07.29_END -- 
+            if(cmd)
+                HAL_GPIO_WritePin(PATH_EN_1_8G_UL_GPIO_Port,PATH_EN_1_8G_UL_Pin, GPIO_PIN_SET);
+            else
+                HAL_GPIO_WritePin(PATH_EN_1_8G_UL_GPIO_Port,PATH_EN_1_8G_UL_Pin, GPIO_PIN_RESET);
+                
+            break;
+        case INDEX_PATH_EN_2_1G_DL  : 
+#ifdef DEBUG_PRINT
+            printf("\r\n LINE %d\r\n",__LINE__);
+#endif /* DEBUG_PRINT */
+            if(cmd)
+                HAL_GPIO_WritePin(PATH_EN_2_1G_DL_GPIO_Port,PATH_EN_2_1G_DL_Pin, GPIO_PIN_SET);
+            else
+                HAL_GPIO_WritePin(PATH_EN_2_1G_DL_GPIO_Port,PATH_EN_2_1G_DL_Pin, GPIO_PIN_RESET);                
+            break;
+        case INDEX_PATH_EN_2_1G_UL  : 
+#ifdef DEBUG_PRINT
+            printf("\r\n LINE %d\r\n",__LINE__);
+#endif /* DEBUG_PRINT */
+            if(cmd)
+                HAL_GPIO_WritePin(PATH_EN_2_1G_UL_GPIO_Port,PATH_EN_2_1G_UL_Pin, GPIO_PIN_SET);
+            else
+                HAL_GPIO_WritePin(PATH_EN_2_1G_UL_GPIO_Port,PATH_EN_2_1G_UL_Pin, GPIO_PIN_RESET);                
+            break;
+        case INDEX_PATH_EN_3_5G_L   : 
+            if(cmd){
+                HAL_GPIO_WritePin(PATH_EN_3_5G_L_GPIO_Port,PATH_EN_3_5G_L_Pin, GPIO_PIN_SET);
+                printf("\r\n LINE %d\r\n",__LINE__);
+            }
+            else{
+                HAL_GPIO_WritePin(PATH_EN_3_5G_L_GPIO_Port,PATH_EN_3_5G_L_Pin, GPIO_PIN_RESET);
+                printf("\r\n LINE %d\r\n",__LINE__);
+            }
+            break;
+        case INDEX_PATH_EN_3_5G_H   : 
+            if(cmd){
+                HAL_GPIO_WritePin(PATH_EN_3_5G_H_GPIO_Port,PATH_EN_3_5G_H_Pin, GPIO_PIN_SET);
+                            printf("\r\n LINE %d\r\n",__LINE__);
+            }
+            else{
+                HAL_GPIO_WritePin(PATH_EN_3_5G_H_GPIO_Port,PATH_EN_3_5G_H_Pin, GPIO_PIN_RESET);
+                            printf("\r\n LINE %d\r\n",__LINE__);
+            }
+            break;
+        case INDEX_PATH_EN_3_5G_DL  : 
+#ifdef DEBUG_PRINT
+            printf("\r\n LINE %d\r\n",__LINE__);
+#endif /* DEBUG_PRINT */
+            if(cmd)
+                HAL_GPIO_WritePin(PATH_EN_3_5G_DL_GPIO_Port,PATH_EN_3_5G_DL_Pin, GPIO_PIN_SET);
+            else
+                HAL_GPIO_WritePin(PATH_EN_3_5G_DL_GPIO_Port,PATH_EN_3_5G_DL_Pin, GPIO_PIN_RESET);
+            break;
+        case INDEX_PATH_EN_3_5G_UL  : 
+#ifdef DEBUG_PRINT
+            printf("\r\n LINE %d\r\n",__LINE__);
+#endif /* DEBUG_PRINT */
+            if(cmd)
+                HAL_GPIO_WritePin(PATH_EN_3_5G_UL_GPIO_Port,PATH_EN_3_5G_UL_Pin, GPIO_PIN_SET);
+            else
+                HAL_GPIO_WritePin(PATH_EN_3_5G_UL_GPIO_Port,PATH_EN_3_5G_UL_Pin, GPIO_PIN_RESET);
+            break;
+        case INDEX_PLL_ON_OFF_3_5G_H: 
+            printf("\r\n LINE %d\r\n",__LINE__);
+            if(cmd)
+                HAL_GPIO_WritePin(PLL_ON_OFF_3_5G_H_GPIO_Port,PLL_ON_OFF_3_5G_H_Pin, GPIO_PIN_SET);
+            else
+                HAL_GPIO_WritePin(PLL_ON_OFF_3_5G_H_GPIO_Port,PLL_ON_OFF_3_5G_H_Pin, GPIO_PIN_RESET);
+            break;
+        case INDEX_PLL_ON_OFF_3_5G_L: 
+            printf("\r\n LINE %d\r\n",__LINE__);
+            if(cmd)
+                HAL_GPIO_WritePin(PLL_ON_OFF_3_5G_L_GPIO_Port,PLL_ON_OFF_3_5G_L_Pin, GPIO_PIN_SET);  
+            else
+                HAL_GPIO_WritePin(PLL_ON_OFF_3_5G_L_GPIO_Port,PLL_ON_OFF_3_5G_L_Pin, GPIO_PIN_RESET);
+            break;
+        case INDEX_T_SYNC_DL:
+        case INDEX__T_SYNC_UL:
+        case INDEX_T_SYNC_UL:
+        case INDEX__T_SYNC_DL:
+            if(cmd){
+                HAL_GPIO_WritePin(_T_SYNC_UL_GPIO_Port,_T_SYNC_UL_Pin, GPIO_PIN_RESET);
+                HAL_GPIO_WritePin(T_SYNC_UL_GPIO_Port,T_SYNC_UL_Pin, GPIO_PIN_RESET);
+                HAL_GPIO_WritePin(_T_SYNC_DL_GPIO_Port,_T_SYNC_DL_Pin, GPIO_PIN_SET);
+                HAL_GPIO_WritePin(T_SYNC_DL_GPIO_Port,T_SYNC_DL_Pin, GPIO_PIN_SET);                
+            }
+            else{
+                HAL_GPIO_WritePin(_T_SYNC_UL_GPIO_Port,_T_SYNC_UL_Pin, GPIO_PIN_SET);
+                HAL_GPIO_WritePin(T_SYNC_UL_GPIO_Port,T_SYNC_UL_Pin, GPIO_PIN_SET);
+                HAL_GPIO_WritePin(_T_SYNC_DL_GPIO_Port,_T_SYNC_DL_Pin, GPIO_PIN_RESET);
+                HAL_GPIO_WritePin(T_SYNC_DL_GPIO_Port,T_SYNC_DL_Pin, GPIO_PIN_RESET);                
+            }
+#ifdef DEBUG_PRINT
+            printf("TDD SYNC OPERATE ; %d\r\n",cmd);
+#endif /* DEBUG_PRINT */
+            break;
+        default :
+#ifdef DEBUG_PRINT
+        printf("Function : %s LINE : %d   ERROR \r\n",__func__,__LINE__);
+#endif /* DEBUG_PRINT */
+    break;
+
+    }
+}
+void ATTEN_PLL_PATH_Initialize(void){
+#if 0 // PYJ.2019.07.31_BEGIN -- 
+        for(int i = 0; i < INDEX_BLUE_EOF + 1; i++){
+            printf("Data = %x\r\n",  Flash_Save_data[i]);
+        }
+#endif // PYJ.2019.07.31_END -- 
+    Flash_Save_data[INDEX_BLUE_CRC]      = STH30_CreateCrc(&Flash_Save_data[Type], Flash_Save_data[Length]);
+    RF_Ctrl_Main(&Flash_Save_data[INDEX_BLUE_HEADER]);
+    RF_Status_Get();
+}
+

insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/main(2522).c

@@ -0,0 +1,742 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : main.c
+  * @brief          : Main program body
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+ADC_HandleTypeDef hadc1;
+DMA_HandleTypeDef hdma_adc1;
+
+TIM_HandleTypeDef htim6;
+
+UART_HandleTypeDef huart1;
+DMA_HandleTypeDef hdma_usart1_rx;
+DMA_HandleTypeDef hdma_usart1_tx;
+
+/* USER CODE BEGIN PV */
+volatile uint32_t AdcTimerCnt = 0;
+volatile uint32_t LedTimerCnt = 0;
+volatile uint32_t UartRxTimerCnt = 0;
+extern PLL_Setting_st Pll_3_5_H;
+extern PLL_Setting_st Pll_3_5_L;
+
+//volatile uint32_t UartTxTimerCnt = 0;
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_DMA_Init(void);
+static void MX_ADC1_Init(void);
+static void MX_USART1_UART_Init(void);
+static void MX_TIM6_Init(void);
+static void MX_NVIC_Init(void);
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+uint32_t ADCvalue[ADC_EA];
+
+#if 1 // PYJ.2019.07.26_BEGIN --
+
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+{
+    if(htim->Instance == TIM6){
+        UartRxTimerCnt++;
+        LedTimerCnt++;
+        AdcTimerCnt++;
+    }
+} 
+#endif // PYJ.2019.07.26_END -- 
+int _write (int file, uint8_t *ptr, uint16_t len)
+{
+    HAL_UART_Transmit(&huart1, ptr, len,10);
+//    HAL_UART_Transmit_IT(&huart1, ptr, len);
+    return len;
+}
+void Pol_Delay_us(volatile uint32_t microseconds)
+{
+  /* Go to number of cycles for system */
+  microseconds *= (SystemCoreClock / 1000000);
+ 
+  /* Delay till end */
+  while (microseconds--);
+}
+/* define address bits for addressing dac outputs. */
+#define SPI_DAC_ADDR0  (1 << 12)
+#define SPI_DAC_ADDR1  (1 << 13)
+#define SPI_DAC_ADDR2  (1 << 14)
+
+/* define addresses for each dac output. */
+#define SPI_DAC_OUTPUT_A   0x00
+#define SPI_DAC_OUTPUT_B   SPI_DAC_ADDR0
+#define SPI_DAC_OUTPUT_C   SPI_DAC_ADDR1
+#define SPI_DAC_OUTPUT_D  (SPI_DAC_ADDR1 | SPI_DAC_ADDR0)
+#define SPI_DAC_OUTPUT_E   SPI_DAC_ADDR2
+#define SPI_DAC_OUTPUT_F  (SPI_DAC_ADDR2 | SPI_DAC_ADDR0)
+#define SPI_DAC_OUTPUT_G  (SPI_DAC_ADDR2 | SPI_DAC_ADDR1)
+#define SPI_DAC_OUTPUT_H  (SPI_DAC_ADDR2 | SPI_DAC_ADDR1 | SPI_DAC_ADDR0)
+
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* USER CODE END 1 */
+  
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_DMA_Init();
+  MX_ADC1_Init();
+  MX_USART1_UART_Init();
+  MX_TIM6_Init();
+
+  /* Initialize interrupts */
+  MX_NVIC_Init();
+  /* USER CODE BEGIN 2 */
+  setbuf(stdout, NULL);
+#ifdef DEBUG_PRINT
+  printf("UART Start \r\n");
+#endif /* DEBUG_PRINT */
+    HAL_UART_Receive_DMA(&huart1, TerminalQueue.Buffer, 1);
+    PE43711_PinInit();
+    HAL_GPIO_WritePin(PATH_EN_3_5G_L_GPIO_Port,PATH_EN_3_5G_L_Pin, GPIO_PIN_SET);
+    HAL_GPIO_WritePin(PATH_EN_3_5G_H_GPIO_Port,PATH_EN_3_5G_H_Pin, GPIO_PIN_SET);
+    HAL_GPIO_WritePin(PATH_EN_3_5G_DL_GPIO_Port,PATH_EN_3_5G_DL_Pin, GPIO_PIN_SET);
+    HAL_GPIO_WritePin(PATH_EN_3_5G_UL_GPIO_Port,PATH_EN_3_5G_UL_Pin, GPIO_PIN_SET);
+    HAL_GPIO_WritePin(PATH_EN_3_5G_L_GPIO_Port,PATH_EN_3_5G_L_Pin, GPIO_PIN_SET);  
+    HAL_GPIO_WritePin(PLL_ON_OFF_3_5G_H_GPIO_Port,PLL_ON_OFF_3_5G_H_Pin, GPIO_PIN_SET);
+    HAL_GPIO_WritePin(PLL_ON_OFF_3_5G_L_GPIO_Port,PLL_ON_OFF_3_5G_L_Pin, GPIO_PIN_SET);  
+    HAL_GPIO_WritePin(PATH_EN_2_1G_DL_GPIO_Port,PATH_EN_2_1G_DL_Pin, GPIO_PIN_SET);
+    HAL_GPIO_WritePin(PATH_EN_2_1G_UL_GPIO_Port,PATH_EN_2_1G_UL_Pin, GPIO_PIN_SET);
+    HAL_GPIO_WritePin(PATH_EN_1_8G_DL_GPIO_Port,PATH_EN_1_8G_DL_Pin, GPIO_PIN_SET);
+    HAL_GPIO_WritePin(PATH_EN_1_8G_UL_GPIO_Port,PATH_EN_1_8G_UL_Pin, GPIO_PIN_SET);
+    HAL_GPIO_WritePin(_T_SYNC_UL_GPIO_Port,_T_SYNC_UL_Pin, GPIO_PIN_RESET);
+    HAL_GPIO_WritePin(T_SYNC_UL_GPIO_Port,T_SYNC_UL_Pin, GPIO_PIN_RESET);
+    HAL_GPIO_WritePin(_T_SYNC_DL_GPIO_Port,_T_SYNC_DL_Pin, GPIO_PIN_SET);
+    HAL_GPIO_WritePin(T_SYNC_DL_GPIO_Port,T_SYNC_DL_Pin, GPIO_PIN_SET);                
+    HAL_Delay(1);
+    Path_Init();
+    ADF4153_Init();
+    SubmitDAC(0x800C);
+    SubmitDAC(0xA000);
+#if 1 // PYJ.2019.07.30_BEGIN -- 
+    SubmitDAC(0x0FFF);
+    SubmitDAC(0x13FF);
+    SubmitDAC(0x23FF);
+    SubmitDAC(0x35FF);
+    SubmitDAC(0x46FF);
+    SubmitDAC(0x57FF);
+    SubmitDAC(0x68FF);
+    SubmitDAC(0x79FF);
+#endif // PYJ.2019.07.30_END -- 
+        
+//    ad53_write(0x2BFF);
+
+#ifdef DEBUG_PRINT
+  printf("\r\nPLL_EN_3_5G_L_GPIO_Port\r\n");
+#endif /* DEBUG_PRINT */
+  
+#ifdef DEBUG_PRINT
+  printf("\r\nPLL_EN_2_1G_UL_GPIO_Port\r\n");
+#endif /* DEBUG_PRINT */
+  HAL_Delay(1);
+  ADF4113_Initialize();
+//  BDA4601_Test();
+    HAL_ADCEx_Calibration_Start(&hadc1);
+    ADF4153_R_N_Reg_st temp_reg;
+    Bluecell_Flash_Read(&Flash_Save_data[INDEX_BLUE_HEADER]);
+    ATTEN_PLL_PATH_Initialize();
+
+//  ADF_Module_Ctrl(Pll_test,0x324000,0x144051,0x0017c2,0x0003c7);
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+//  while(HAL_ADCEx_Calibration_Start(&hadc1) != HAL_OK); //ADC Calibration 
+//   HAL_ADC_Start_DMA(&hadc1, (uint32_t*)ADCvalue, ADC_EA);
+  while (1)
+  {
+    if(HAL_GPIO_ReadPin(PLL_LD_3_5G_H_GPIO_Port, PLL_LD_3_5G_H_Pin) == GPIO_PIN_RESET){
+        temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
+        ADF4153_Module_Ctrl(Pll_3_5_H,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
+        HAL_Delay(1);
+    }
+    if(HAL_GPIO_ReadPin(PLL_LD_3_5G_L_GPIO_Port, PLL_LD_3_5G_L_Pin) == GPIO_PIN_RESET){
+        temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
+        ADF4153_Module_Ctrl(Pll_3_5_L,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
+        HAL_Delay(1);
+    }
+    if(LedTimerCnt > 500){HAL_GPIO_TogglePin(BOOT_LED_GPIO_Port,GPIO_PIN_14);LedTimerCnt = 0;}
+    while (TerminalQueue.data > 0 && UartRxTimerCnt > 100) GetDataFromUartQueue(&hTerminal);
+    if(AdcTimerCnt > 5000){
+        HAL_ADC_Start_DMA(&hadc1, (uint32_t*)ADCvalue, 14);  
+        for(uint8_t i = 0; i< ADC_EA; i += 2 ){
+            Prev_data[INDEX_DET_1_8G_DL_IN_H + i]     = (uint16_t)((ADCvalue[i] & 0xFF00) >> 8);
+            Prev_data[INDEX_DET_1_8G_DL_IN_L + i]     = (uint16_t)(ADCvalue[i] & 0x00FF);
+//            printf("Prev_data[INDEX_DET_1_8G_DL_IN_H + i] : %x\r\n",Prev_data[INDEX_DET_1_8G_DL_IN_H + i]);
+//            printf("Prev_data[INDEX_DET_1_8G_DL_IN_L + i] : %x\r\n",Prev_data[INDEX_DET_1_8G_DL_IN_L]);            
+        }
+//        for(int i = 0; i < 14; i++)
+//            printf("\r\nYJ[%d] : %x \r\n",i,ADCvalue[i]);
+//        HAL_Delay(3000);
+        RF_Status_Get();
+#if 1 // PYJ.2019.07.29_BEGIN -- 
+//        printf("====================================\r\n");
+//            for(uint8_t i = 0; i< ADC_EA; i++){
+//                printf("%x",ADCvalue[0]);
+//                printf("\r\n");
+//                printf("%d",ADCvalue[i]);
+//                printf("\r\n");
+//            }
+//                printf("\r\nADC[%d] : %d\r\n ",i,ADCvalue[i]);
+//        printf("====================================\r\n");
+#endif // PYJ.2019.07.29_END -- 
+        AdcTimerCnt = 0;
+
+    }
+
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2;
+  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL15;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
+  PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6;
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+  {
+    Error_Handler();
+  }
+}
+
+/**
+  * @brief NVIC Configuration.
+  * @retval None
+  */
+static void MX_NVIC_Init(void)
+{
+  /* USART1_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(USART1_IRQn);
+  /* TIM6_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(TIM6_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(TIM6_IRQn);
+  /* DMA1_Channel1_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
+  /* DMA1_Channel4_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Channel4_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Channel4_IRQn);
+  /* DMA1_Channel5_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Channel5_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Channel5_IRQn);
+}
+
+/**
+  * @brief ADC1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_ADC1_Init(void)
+{
+
+  /* USER CODE BEGIN ADC1_Init 0 */
+
+  /* USER CODE END ADC1_Init 0 */
+
+  ADC_ChannelConfTypeDef sConfig = {0};
+
+  /* USER CODE BEGIN ADC1_Init 1 */
+
+  /* USER CODE END ADC1_Init 1 */
+  /** Common config 
+  */
+  hadc1.Instance = ADC1;
+  hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE;
+  hadc1.Init.ContinuousConvMode = ENABLE;
+  hadc1.Init.DiscontinuousConvMode = DISABLE;
+  hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
+  hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+  hadc1.Init.NbrOfConversion = 14;
+  if (HAL_ADC_Init(&hadc1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Channel = ADC_CHANNEL_0;
+  sConfig.Rank = ADC_REGULAR_RANK_1;
+  sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Channel = ADC_CHANNEL_1;
+  sConfig.Rank = ADC_REGULAR_RANK_2;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Channel = ADC_CHANNEL_2;
+  sConfig.Rank = ADC_REGULAR_RANK_3;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Channel = ADC_CHANNEL_3;
+  sConfig.Rank = ADC_REGULAR_RANK_4;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Channel = ADC_CHANNEL_4;
+  sConfig.Rank = ADC_REGULAR_RANK_5;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Channel = ADC_CHANNEL_5;
+  sConfig.Rank = ADC_REGULAR_RANK_6;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Channel = ADC_CHANNEL_6;
+  sConfig.Rank = ADC_REGULAR_RANK_7;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Channel = ADC_CHANNEL_7;
+  sConfig.Rank = ADC_REGULAR_RANK_8;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Channel = ADC_CHANNEL_8;
+  sConfig.Rank = ADC_REGULAR_RANK_9;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Channel = ADC_CHANNEL_9;
+  sConfig.Rank = ADC_REGULAR_RANK_10;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Channel = ADC_CHANNEL_10;
+  sConfig.Rank = ADC_REGULAR_RANK_11;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Channel = ADC_CHANNEL_11;
+  sConfig.Rank = ADC_REGULAR_RANK_12;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Channel = ADC_CHANNEL_12;
+  sConfig.Rank = ADC_REGULAR_RANK_13;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Channel = ADC_CHANNEL_13;
+  sConfig.Rank = ADC_REGULAR_RANK_14;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN ADC1_Init 2 */
+
+  /* USER CODE END ADC1_Init 2 */
+
+}
+
+/**
+  * @brief TIM6 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_TIM6_Init(void)
+{
+
+  /* USER CODE BEGIN TIM6_Init 0 */
+
+  /* USER CODE END TIM6_Init 0 */
+
+  TIM_MasterConfigTypeDef sMasterConfig = {0};
+
+  /* USER CODE BEGIN TIM6_Init 1 */
+
+  /* USER CODE END TIM6_Init 1 */
+  htim6.Instance = TIM6;
+  htim6.Init.Prescaler = 6000-1;
+  htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
+  htim6.Init.Period = 10;
+  htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+  if (HAL_TIM_Base_Init(&htim6) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+  if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN TIM6_Init 2 */
+
+  /* USER CODE END TIM6_Init 2 */
+
+}
+
+/**
+  * @brief USART1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_USART1_UART_Init(void)
+{
+
+  /* USER CODE BEGIN USART1_Init 0 */
+
+  /* USER CODE END USART1_Init 0 */
+
+  /* USER CODE BEGIN USART1_Init 1 */
+
+  /* USER CODE END USART1_Init 1 */
+  huart1.Instance = USART1;
+  huart1.Init.BaudRate = 115200;
+  huart1.Init.WordLength = UART_WORDLENGTH_8B;
+  huart1.Init.StopBits = UART_STOPBITS_1;
+  huart1.Init.Parity = UART_PARITY_NONE;
+  huart1.Init.Mode = UART_MODE_TX_RX;
+  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  huart1.Init.OverSampling = UART_OVERSAMPLING_16;
+  if (HAL_UART_Init(&huart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN USART1_Init 2 */
+
+  /* USER CODE END USART1_Init 2 */
+
+}
+
+/** 
+  * Enable DMA controller clock
+  */
+static void MX_DMA_Init(void) 
+{
+  /* DMA controller clock enable */
+  __HAL_RCC_DMA1_CLK_ENABLE();
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOE_CLK_ENABLE();
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOF_CLK_ENABLE();
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+  __HAL_RCC_GPIOG_CLK_ENABLE();
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOE, ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin 
+                          |ATT_EN_1_8G_UL3_Pin|PATH_EN_2_1G_DL_Pin|PATH_EN_2_1G_UL_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOC, ATT_EN_1_8G_UL4_Pin|PATH_EN_1_8G_DL_Pin|PATH_EN_1_8G_UL_Pin|PLL_EN_3_5G_L_Pin 
+                          |PLL_EN_3_5G_H_Pin|PLL_ON_OFF_3_5G_L_Pin|PLL_DATA_3_5G_Pin|PLL_ON_OFF_3_5G_H_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOF, PLL_EN_1_8G_DL_Pin|PLL_EN_1_8G_UL_Pin|ATT_EN_2_1G_DL1_Pin|ATT_EN_2_1G_DL2_Pin 
+                          |ATT_EN_2_1G_UL1_Pin|ATT_EN_2_1G_UL2_Pin|ATT_EN_2_1G_UL3_Pin|ATT_EN_2_1G_UL4_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOD, PLL_DATA_Pin|PLL_CLK_Pin|ATT_DATA_Pin|ATT_CLK_Pin 
+                          |DA_LDAC_Pin|ATT_CLK_3_5G_Pin|ATT_EN_3_5G_Pin|ATT_DATA_3_5G_DL_Pin 
+                          |ATT_DATA_3_5G_UL_Pin|ATT_DATA_3_5G_COM1_Pin|ATT_DATA_3_5G_COM2_Pin|ATT_DATA_3_5G_COM3_Pin 
+                          |PATH_EN_3_5G_L_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOG, DA_SYNC_Pin|DA_SCLK_Pin|DA_DIN_Pin|_T_SYNC_UL_Pin 
+                          |T_SYNC_UL_Pin|_T_SYNC_DL_Pin|T_SYNC_DL_Pin|PATH_EN_3_5G_H_Pin 
+                          |PATH_EN_3_5G_DL_Pin|PATH_EN_3_5G_UL_Pin|PLL_ON_OFF_3_5G_LG12_Pin|PLL_ON_OFF_3_5G_HG13_Pin 
+                          |BOOT_LED_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(PLL_CLK_3_5G_GPIO_Port, PLL_CLK_3_5G_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOB, PLL_EN_2_1G_DL_Pin|PLL_EN_2_1G_UL_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pins : ATT_EN_1_8G_DL1_Pin ATT_EN_1_8G_DL2_Pin ATT_EN_1_8G_UL1_Pin ATT_EN_1_8G_UL2_Pin 
+                           ATT_EN_1_8G_UL3_Pin PATH_EN_2_1G_DL_Pin PATH_EN_2_1G_UL_Pin */
+  GPIO_InitStruct.Pin = ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin 
+                          |ATT_EN_1_8G_UL3_Pin|PATH_EN_2_1G_DL_Pin|PATH_EN_2_1G_UL_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : ATT_EN_1_8G_UL4_Pin PATH_EN_1_8G_DL_Pin PATH_EN_1_8G_UL_Pin PLL_EN_3_5G_L_Pin 
+                           PLL_EN_3_5G_H_Pin PLL_ON_OFF_3_5G_L_Pin PLL_DATA_3_5G_Pin PLL_ON_OFF_3_5G_H_Pin */
+  GPIO_InitStruct.Pin = ATT_EN_1_8G_UL4_Pin|PATH_EN_1_8G_DL_Pin|PATH_EN_1_8G_UL_Pin|PLL_EN_3_5G_L_Pin 
+                          |PLL_EN_3_5G_H_Pin|PLL_ON_OFF_3_5G_L_Pin|PLL_DATA_3_5G_Pin|PLL_ON_OFF_3_5G_H_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : PLL_EN_1_8G_DL_Pin PLL_EN_1_8G_UL_Pin ATT_EN_2_1G_DL1_Pin ATT_EN_2_1G_DL2_Pin 
+                           ATT_EN_2_1G_UL1_Pin ATT_EN_2_1G_UL2_Pin ATT_EN_2_1G_UL3_Pin ATT_EN_2_1G_UL4_Pin */
+  GPIO_InitStruct.Pin = PLL_EN_1_8G_DL_Pin|PLL_EN_1_8G_UL_Pin|ATT_EN_2_1G_DL1_Pin|ATT_EN_2_1G_DL2_Pin 
+                          |ATT_EN_2_1G_UL1_Pin|ATT_EN_2_1G_UL2_Pin|ATT_EN_2_1G_UL3_Pin|ATT_EN_2_1G_UL4_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : PLL_LD_1_8G_DL_Pin PLL_LD_1_8G_UL_Pin */
+  GPIO_InitStruct.Pin = PLL_LD_1_8G_DL_Pin|PLL_LD_1_8G_UL_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : PLL_DATA_Pin PLL_CLK_Pin ATT_DATA_Pin ATT_CLK_Pin 
+                           DA_LDAC_Pin ATT_CLK_3_5G_Pin ATT_EN_3_5G_Pin ATT_DATA_3_5G_DL_Pin 
+                           ATT_DATA_3_5G_UL_Pin ATT_DATA_3_5G_COM1_Pin ATT_DATA_3_5G_COM2_Pin ATT_DATA_3_5G_COM3_Pin 
+                           PATH_EN_3_5G_L_Pin */
+  GPIO_InitStruct.Pin = PLL_DATA_Pin|PLL_CLK_Pin|ATT_DATA_Pin|ATT_CLK_Pin 
+                          |DA_LDAC_Pin|ATT_CLK_3_5G_Pin|ATT_EN_3_5G_Pin|ATT_DATA_3_5G_DL_Pin 
+                          |ATT_DATA_3_5G_UL_Pin|ATT_DATA_3_5G_COM1_Pin|ATT_DATA_3_5G_COM2_Pin|ATT_DATA_3_5G_COM3_Pin 
+                          |PATH_EN_3_5G_L_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : ALARM_DC_Pin ALARM_AC_Pin */
+  GPIO_InitStruct.Pin = ALARM_DC_Pin|ALARM_AC_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : DA_SYNC_Pin DA_SCLK_Pin DA_DIN_Pin _T_SYNC_UL_Pin 
+                           T_SYNC_UL_Pin _T_SYNC_DL_Pin T_SYNC_DL_Pin PATH_EN_3_5G_H_Pin 
+                           PATH_EN_3_5G_DL_Pin PATH_EN_3_5G_UL_Pin PLL_ON_OFF_3_5G_LG12_Pin PLL_ON_OFF_3_5G_HG13_Pin 
+                           BOOT_LED_Pin */
+  GPIO_InitStruct.Pin = DA_SYNC_Pin|DA_SCLK_Pin|DA_DIN_Pin|_T_SYNC_UL_Pin 
+                          |T_SYNC_UL_Pin|_T_SYNC_DL_Pin|T_SYNC_DL_Pin|PATH_EN_3_5G_H_Pin 
+                          |PATH_EN_3_5G_DL_Pin|PATH_EN_3_5G_UL_Pin|PLL_ON_OFF_3_5G_LG12_Pin|PLL_ON_OFF_3_5G_HG13_Pin 
+                          |BOOT_LED_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : PLL_LD_3_5G_L_Pin PLL_LD_3_5G_H_Pin */
+  GPIO_InitStruct.Pin = PLL_LD_3_5G_L_Pin|PLL_LD_3_5G_H_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+  /*Configure GPIO pin : PLL_CLK_3_5G_Pin */
+  GPIO_InitStruct.Pin = PLL_CLK_3_5G_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(PLL_CLK_3_5G_GPIO_Port, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : PLL_EN_2_1G_DL_Pin PLL_EN_2_1G_UL_Pin */
+  GPIO_InitStruct.Pin = PLL_EN_2_1G_DL_Pin|PLL_EN_2_1G_UL_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : PLL_LD_2_1G_DL_Pin PLL_LD_2_1G_UL_Pin */
+  GPIO_InitStruct.Pin = PLL_LD_2_1G_DL_Pin|PLL_LD_2_1G_UL_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+}
+
+/* USER CODE BEGIN 4 */
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/main(4598).c

@@ -0,0 +1,749 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : main.c
+  * @brief          : Main program body
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+ADC_HandleTypeDef hadc1;
+DMA_HandleTypeDef hdma_adc1;
+
+TIM_HandleTypeDef htim6;
+
+UART_HandleTypeDef huart1;
+DMA_HandleTypeDef hdma_usart1_rx;
+DMA_HandleTypeDef hdma_usart1_tx;
+
+/* USER CODE BEGIN PV */
+volatile uint32_t AdcTimerCnt = 0;
+volatile uint32_t LedTimerCnt = 0;
+volatile uint32_t UartRxTimerCnt = 0;
+extern PLL_Setting_st Pll_3_5_H;
+extern PLL_Setting_st Pll_3_5_L;
+
+//volatile uint32_t UartTxTimerCnt = 0;
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_DMA_Init(void);
+static void MX_ADC1_Init(void);
+static void MX_USART1_UART_Init(void);
+static void MX_TIM6_Init(void);
+static void MX_NVIC_Init(void);
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+uint32_t ADCvalue[ADC_EA];
+
+#if 1 // PYJ.2019.07.26_BEGIN --
+
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+{
+    if(htim->Instance == TIM6){
+        UartRxTimerCnt++;
+        LedTimerCnt++;
+        AdcTimerCnt++;
+    }
+} 
+#endif // PYJ.2019.07.26_END -- 
+int _write (int file, uint8_t *ptr, uint16_t len)
+{
+    HAL_UART_Transmit(&huart1, ptr, len,10);
+//    HAL_UART_Transmit_IT(&huart1, ptr, len);
+    return len;
+}
+void Pol_Delay_us(volatile uint32_t microseconds)
+{
+  /* Go to number of cycles for system */
+  microseconds *= (SystemCoreClock / 1000000);
+ 
+  /* Delay till end */
+  while (microseconds--);
+}
+/* define address bits for addressing dac outputs. */
+#define SPI_DAC_ADDR0  (1 << 12)
+#define SPI_DAC_ADDR1  (1 << 13)
+#define SPI_DAC_ADDR2  (1 << 14)
+
+/* define addresses for each dac output. */
+#define SPI_DAC_OUTPUT_A   0x00
+#define SPI_DAC_OUTPUT_B   SPI_DAC_ADDR0
+#define SPI_DAC_OUTPUT_C   SPI_DAC_ADDR1
+#define SPI_DAC_OUTPUT_D  (SPI_DAC_ADDR1 | SPI_DAC_ADDR0)
+#define SPI_DAC_OUTPUT_E   SPI_DAC_ADDR2
+#define SPI_DAC_OUTPUT_F  (SPI_DAC_ADDR2 | SPI_DAC_ADDR0)
+#define SPI_DAC_OUTPUT_G  (SPI_DAC_ADDR2 | SPI_DAC_ADDR1)
+#define SPI_DAC_OUTPUT_H  (SPI_DAC_ADDR2 | SPI_DAC_ADDR1 | SPI_DAC_ADDR0)
+
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* USER CODE END 1 */
+  
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_DMA_Init();
+  MX_ADC1_Init();
+  MX_USART1_UART_Init();
+  MX_TIM6_Init();
+
+  /* Initialize interrupts */
+  MX_NVIC_Init();
+  /* USER CODE BEGIN 2 */
+  setbuf(stdout, NULL);
+#ifdef DEBUG_PRINT
+  printf("UART Start \r\n");
+#endif /* DEBUG_PRINT */
+    HAL_UART_Receive_DMA(&huart1, TerminalQueue.Buffer, 1);
+    PE43711_PinInit();
+    
+    HAL_GPIO_WritePin(PATH_EN_3_5G_L_GPIO_Port,PATH_EN_3_5G_L_Pin, GPIO_PIN_RESET);
+    HAL_GPIO_WritePin(PATH_EN_3_5G_H_GPIO_Port,PATH_EN_3_5G_H_Pin, GPIO_PIN_RESET);
+    HAL_GPIO_WritePin(PATH_EN_3_5G_DL_GPIO_Port,PATH_EN_3_5G_DL_Pin, GPIO_PIN_RESET);
+    HAL_GPIO_WritePin(PATH_EN_3_5G_UL_GPIO_Port,PATH_EN_3_5G_UL_Pin, GPIO_PIN_RESET);
+    HAL_GPIO_WritePin(PATH_EN_3_5G_L_GPIO_Port,PATH_EN_3_5G_L_Pin, GPIO_PIN_RESET);  
+    HAL_GPIO_WritePin(PLL_ON_OFF_3_5G_H_GPIO_Port,PLL_ON_OFF_3_5G_H_Pin, GPIO_PIN_RESET);
+    HAL_GPIO_WritePin(PLL_ON_OFF_3_5G_L_GPIO_Port,PLL_ON_OFF_3_5G_L_Pin, GPIO_PIN_RESET);  
+    HAL_GPIO_WritePin(PATH_EN_2_1G_DL_GPIO_Port,PATH_EN_2_1G_DL_Pin, GPIO_PIN_RESET);
+    HAL_GPIO_WritePin(PATH_EN_2_1G_UL_GPIO_Port,PATH_EN_2_1G_UL_Pin, GPIO_PIN_RESET);
+    HAL_GPIO_WritePin(PATH_EN_1_8G_DL_GPIO_Port,PATH_EN_1_8G_DL_Pin, GPIO_PIN_RESET);
+    HAL_GPIO_WritePin(PATH_EN_1_8G_UL_GPIO_Port,PATH_EN_1_8G_UL_Pin, GPIO_PIN_RESET);
+
+    
+    HAL_GPIO_WritePin(_T_SYNC_UL_GPIO_Port,_T_SYNC_UL_Pin, GPIO_PIN_RESET);
+    HAL_GPIO_WritePin(T_SYNC_UL_GPIO_Port,T_SYNC_UL_Pin, GPIO_PIN_RESET);
+    HAL_GPIO_WritePin(_T_SYNC_DL_GPIO_Port,_T_SYNC_DL_Pin, GPIO_PIN_SET);
+    HAL_GPIO_WritePin(T_SYNC_DL_GPIO_Port,T_SYNC_DL_Pin, GPIO_PIN_SET);     
+    
+    HAL_Delay(1);
+    Path_Init();
+    ADF4153_Init();
+    SubmitDAC(0x800C);
+    SubmitDAC(0xA000);
+#if 1
+// PYJ.2019.07.30_BEGIN -- 
+    SubmitDAC(0x0FFF);
+    SubmitDAC(0x13FF);
+    SubmitDAC(0x23FF);
+    SubmitDAC(0x35FF);
+    SubmitDAC(0x46FF);
+    SubmitDAC(0x57FF);
+    SubmitDAC(0x68FF);
+    SubmitDAC(0x79FF);
+#endif // PYJ.2019.07.30_END -- 
+        
+//    ad53_write(0x2BFF);
+
+#ifdef DEBUG_PRINT
+  printf("\r\nPLL_EN_3_5G_L_GPIO_Port\r\n");
+#endif /* DEBUG_PRINT */
+  
+#ifdef DEBUG_PRINT
+  printf("\r\nPLL_EN_2_1G_UL_GPIO_Port\r\n");
+#endif /* DEBUG_PRINT */
+  HAL_Delay(1);
+  ADF4113_Initialize();
+//  BDA4601_Test();
+    HAL_ADCEx_Calibration_Start(&hadc1);
+    ADF4153_R_N_Reg_st temp_reg;
+#if 0 // PYJ.2019.08.01_BEGIN -- 
+    Bluecell_Flash_Read(&Flash_Save_data[INDEX_BLUE_HEADER]);
+    ATTEN_PLL_PATH_Initialize();
+#endif // PYJ.2019.08.01_END -- 
+
+//  ADF_Module_Ctrl(Pll_test,0x324000,0x144051,0x0017c2,0x0003c7);
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+//  while(HAL_ADCEx_Calibration_Start(&hadc1) != HAL_OK); //ADC Calibration 
+//   HAL_ADC_Start_DMA(&hadc1, (uint32_t*)ADCvalue, ADC_EA);
+  while (1)
+  {
+    if(HAL_GPIO_ReadPin(PLL_LD_3_5G_H_GPIO_Port, PLL_LD_3_5G_H_Pin) == GPIO_PIN_RESET){
+        temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
+        ADF4153_Module_Ctrl(Pll_3_5_H,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
+        HAL_Delay(1);
+    }
+    if(HAL_GPIO_ReadPin(PLL_LD_3_5G_L_GPIO_Port, PLL_LD_3_5G_L_Pin) == GPIO_PIN_RESET){
+        temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
+        ADF4153_Module_Ctrl(Pll_3_5_L,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
+        HAL_Delay(1);
+    }
+    if(LedTimerCnt > 500){HAL_GPIO_TogglePin(BOOT_LED_GPIO_Port,GPIO_PIN_14);LedTimerCnt = 0;}
+    while (TerminalQueue.data > 0 && UartRxTimerCnt > 100) GetDataFromUartQueue(&hTerminal);
+    if(AdcTimerCnt > 5000){
+        HAL_ADC_Start_DMA(&hadc1, (uint32_t*)ADCvalue, 14);  
+        for(uint8_t i = 0; i< ADC_EA; i += 2 ){
+            Prev_data[INDEX_DET_1_8G_DL_IN_H + i]     = (uint16_t)((ADCvalue[i] & 0xFF00) >> 8);
+            Prev_data[INDEX_DET_1_8G_DL_IN_L + i]     = (uint16_t)(ADCvalue[i] & 0x00FF);
+//            printf("Prev_data[INDEX_DET_1_8G_DL_IN_H + i] : %x\r\n",Prev_data[INDEX_DET_1_8G_DL_IN_H + i]);
+//            printf("Prev_data[INDEX_DET_1_8G_DL_IN_L + i] : %x\r\n",Prev_data[INDEX_DET_1_8G_DL_IN_L]);            
+        }
+//        for(int i = 0; i < 14; i++)
+//            printf("\r\nYJ[%d] : %x \r\n",i,ADCvalue[i]);
+//        HAL_Delay(3000);
+        RF_Status_Get();
+#if 1 // PYJ.2019.07.29_BEGIN -- 
+//        printf("====================================\r\n");
+//            for(uint8_t i = 0; i< ADC_EA; i++){
+//                printf("%x",ADCvalue[0]);
+//                printf("\r\n");
+//                printf("%d",ADCvalue[i]);
+//                printf("\r\n");
+//            }
+//                printf("\r\nADC[%d] : %d\r\n ",i,ADCvalue[i]);
+//        printf("====================================\r\n");
+#endif // PYJ.2019.07.29_END -- 
+        AdcTimerCnt = 0;
+
+    }
+
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2;
+  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL15;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
+  PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6;
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+  {
+    Error_Handler();
+  }
+}
+
+/**
+  * @brief NVIC Configuration.
+  * @retval None
+  */
+static void MX_NVIC_Init(void)
+{
+  /* USART1_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(USART1_IRQn);
+  /* TIM6_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(TIM6_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(TIM6_IRQn);
+  /* DMA1_Channel1_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
+  /* DMA1_Channel4_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Channel4_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Channel4_IRQn);
+  /* DMA1_Channel5_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Channel5_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Channel5_IRQn);
+}
+
+/**
+  * @brief ADC1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_ADC1_Init(void)
+{
+
+  /* USER CODE BEGIN ADC1_Init 0 */
+
+  /* USER CODE END ADC1_Init 0 */
+
+  ADC_ChannelConfTypeDef sConfig = {0};
+
+  /* USER CODE BEGIN ADC1_Init 1 */
+
+  /* USER CODE END ADC1_Init 1 */
+  /** Common config 
+  */
+  hadc1.Instance = ADC1;
+  hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE;
+  hadc1.Init.ContinuousConvMode = ENABLE;
+  hadc1.Init.DiscontinuousConvMode = DISABLE;
+  hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
+  hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+  hadc1.Init.NbrOfConversion = 14;
+  if (HAL_ADC_Init(&hadc1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Channel = ADC_CHANNEL_0;
+  sConfig.Rank = ADC_REGULAR_RANK_1;
+  sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Channel = ADC_CHANNEL_1;
+  sConfig.Rank = ADC_REGULAR_RANK_2;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Channel = ADC_CHANNEL_2;
+  sConfig.Rank = ADC_REGULAR_RANK_3;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Channel = ADC_CHANNEL_3;
+  sConfig.Rank = ADC_REGULAR_RANK_4;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Channel = ADC_CHANNEL_4;
+  sConfig.Rank = ADC_REGULAR_RANK_5;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Channel = ADC_CHANNEL_5;
+  sConfig.Rank = ADC_REGULAR_RANK_6;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Channel = ADC_CHANNEL_6;
+  sConfig.Rank = ADC_REGULAR_RANK_7;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Channel = ADC_CHANNEL_7;
+  sConfig.Rank = ADC_REGULAR_RANK_8;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Channel = ADC_CHANNEL_8;
+  sConfig.Rank = ADC_REGULAR_RANK_9;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Channel = ADC_CHANNEL_9;
+  sConfig.Rank = ADC_REGULAR_RANK_10;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Channel = ADC_CHANNEL_10;
+  sConfig.Rank = ADC_REGULAR_RANK_11;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Channel = ADC_CHANNEL_11;
+  sConfig.Rank = ADC_REGULAR_RANK_12;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Channel = ADC_CHANNEL_12;
+  sConfig.Rank = ADC_REGULAR_RANK_13;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel 
+  */
+  sConfig.Channel = ADC_CHANNEL_13;
+  sConfig.Rank = ADC_REGULAR_RANK_14;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN ADC1_Init 2 */
+
+  /* USER CODE END ADC1_Init 2 */
+
+}
+
+/**
+  * @brief TIM6 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_TIM6_Init(void)
+{
+
+  /* USER CODE BEGIN TIM6_Init 0 */
+
+  /* USER CODE END TIM6_Init 0 */
+
+  TIM_MasterConfigTypeDef sMasterConfig = {0};
+
+  /* USER CODE BEGIN TIM6_Init 1 */
+
+  /* USER CODE END TIM6_Init 1 */
+  htim6.Instance = TIM6;
+  htim6.Init.Prescaler = 6000-1;
+  htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
+  htim6.Init.Period = 10;
+  htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+  if (HAL_TIM_Base_Init(&htim6) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+  if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN TIM6_Init 2 */
+
+  /* USER CODE END TIM6_Init 2 */
+
+}
+
+/**
+  * @brief USART1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_USART1_UART_Init(void)
+{
+
+  /* USER CODE BEGIN USART1_Init 0 */
+
+  /* USER CODE END USART1_Init 0 */
+
+  /* USER CODE BEGIN USART1_Init 1 */
+
+  /* USER CODE END USART1_Init 1 */
+  huart1.Instance = USART1;
+  huart1.Init.BaudRate = 115200;
+  huart1.Init.WordLength = UART_WORDLENGTH_8B;
+  huart1.Init.StopBits = UART_STOPBITS_1;
+  huart1.Init.Parity = UART_PARITY_NONE;
+  huart1.Init.Mode = UART_MODE_TX_RX;
+  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  huart1.Init.OverSampling = UART_OVERSAMPLING_16;
+  if (HAL_UART_Init(&huart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN USART1_Init 2 */
+
+  /* USER CODE END USART1_Init 2 */
+
+}
+
+/** 
+  * Enable DMA controller clock
+  */
+static void MX_DMA_Init(void) 
+{
+  /* DMA controller clock enable */
+  __HAL_RCC_DMA1_CLK_ENABLE();
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOE_CLK_ENABLE();
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOF_CLK_ENABLE();
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+  __HAL_RCC_GPIOG_CLK_ENABLE();
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOE, ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin 
+                          |ATT_EN_1_8G_UL3_Pin|PATH_EN_2_1G_DL_Pin|PATH_EN_2_1G_UL_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOC, ATT_EN_1_8G_UL4_Pin|PATH_EN_1_8G_DL_Pin|PATH_EN_1_8G_UL_Pin|PLL_EN_3_5G_L_Pin 
+                          |PLL_EN_3_5G_H_Pin|PLL_ON_OFF_3_5G_L_Pin|PLL_DATA_3_5G_Pin|PLL_ON_OFF_3_5G_H_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOF, PLL_EN_1_8G_DL_Pin|PLL_EN_1_8G_UL_Pin|ATT_EN_2_1G_DL1_Pin|ATT_EN_2_1G_DL2_Pin 
+                          |ATT_EN_2_1G_UL1_Pin|ATT_EN_2_1G_UL2_Pin|ATT_EN_2_1G_UL3_Pin|ATT_EN_2_1G_UL4_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOD, PLL_DATA_Pin|PLL_CLK_Pin|ATT_DATA_Pin|ATT_CLK_Pin 
+                          |DA_LDAC_Pin|ATT_CLK_3_5G_Pin|ATT_EN_3_5G_Pin|ATT_DATA_3_5G_DL_Pin 
+                          |ATT_DATA_3_5G_UL_Pin|ATT_DATA_3_5G_COM1_Pin|ATT_DATA_3_5G_COM2_Pin|ATT_DATA_3_5G_COM3_Pin 
+                          |PATH_EN_3_5G_L_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOG, DA_SYNC_Pin|DA_SCLK_Pin|DA_DIN_Pin|_T_SYNC_UL_Pin 
+                          |T_SYNC_UL_Pin|_T_SYNC_DL_Pin|T_SYNC_DL_Pin|PATH_EN_3_5G_H_Pin 
+                          |PATH_EN_3_5G_DL_Pin|PATH_EN_3_5G_UL_Pin|PLL_ON_OFF_3_5G_LG12_Pin|PLL_ON_OFF_3_5G_HG13_Pin 
+                          |BOOT_LED_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(PLL_CLK_3_5G_GPIO_Port, PLL_CLK_3_5G_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOB, PLL_EN_2_1G_DL_Pin|PLL_EN_2_1G_UL_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pins : ATT_EN_1_8G_DL1_Pin ATT_EN_1_8G_DL2_Pin ATT_EN_1_8G_UL1_Pin ATT_EN_1_8G_UL2_Pin 
+                           ATT_EN_1_8G_UL3_Pin PATH_EN_2_1G_DL_Pin PATH_EN_2_1G_UL_Pin */
+  GPIO_InitStruct.Pin = ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin 
+                          |ATT_EN_1_8G_UL3_Pin|PATH_EN_2_1G_DL_Pin|PATH_EN_2_1G_UL_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : ATT_EN_1_8G_UL4_Pin PATH_EN_1_8G_DL_Pin PATH_EN_1_8G_UL_Pin PLL_EN_3_5G_L_Pin 
+                           PLL_EN_3_5G_H_Pin PLL_ON_OFF_3_5G_L_Pin PLL_DATA_3_5G_Pin PLL_ON_OFF_3_5G_H_Pin */
+  GPIO_InitStruct.Pin = ATT_EN_1_8G_UL4_Pin|PATH_EN_1_8G_DL_Pin|PATH_EN_1_8G_UL_Pin|PLL_EN_3_5G_L_Pin 
+                          |PLL_EN_3_5G_H_Pin|PLL_ON_OFF_3_5G_L_Pin|PLL_DATA_3_5G_Pin|PLL_ON_OFF_3_5G_H_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : PLL_EN_1_8G_DL_Pin PLL_EN_1_8G_UL_Pin ATT_EN_2_1G_DL1_Pin ATT_EN_2_1G_DL2_Pin 
+                           ATT_EN_2_1G_UL1_Pin ATT_EN_2_1G_UL2_Pin ATT_EN_2_1G_UL3_Pin ATT_EN_2_1G_UL4_Pin */
+  GPIO_InitStruct.Pin = PLL_EN_1_8G_DL_Pin|PLL_EN_1_8G_UL_Pin|ATT_EN_2_1G_DL1_Pin|ATT_EN_2_1G_DL2_Pin 
+                          |ATT_EN_2_1G_UL1_Pin|ATT_EN_2_1G_UL2_Pin|ATT_EN_2_1G_UL3_Pin|ATT_EN_2_1G_UL4_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : PLL_LD_1_8G_DL_Pin PLL_LD_1_8G_UL_Pin */
+  GPIO_InitStruct.Pin = PLL_LD_1_8G_DL_Pin|PLL_LD_1_8G_UL_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : PLL_DATA_Pin PLL_CLK_Pin ATT_DATA_Pin ATT_CLK_Pin 
+                           DA_LDAC_Pin ATT_CLK_3_5G_Pin ATT_EN_3_5G_Pin ATT_DATA_3_5G_DL_Pin 
+                           ATT_DATA_3_5G_UL_Pin ATT_DATA_3_5G_COM1_Pin ATT_DATA_3_5G_COM2_Pin ATT_DATA_3_5G_COM3_Pin 
+                           PATH_EN_3_5G_L_Pin */
+  GPIO_InitStruct.Pin = PLL_DATA_Pin|PLL_CLK_Pin|ATT_DATA_Pin|ATT_CLK_Pin 
+                          |DA_LDAC_Pin|ATT_CLK_3_5G_Pin|ATT_EN_3_5G_Pin|ATT_DATA_3_5G_DL_Pin 
+                          |ATT_DATA_3_5G_UL_Pin|ATT_DATA_3_5G_COM1_Pin|ATT_DATA_3_5G_COM2_Pin|ATT_DATA_3_5G_COM3_Pin 
+                          |PATH_EN_3_5G_L_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : ALARM_DC_Pin ALARM_AC_Pin */
+  GPIO_InitStruct.Pin = ALARM_DC_Pin|ALARM_AC_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : DA_SYNC_Pin DA_SCLK_Pin DA_DIN_Pin _T_SYNC_UL_Pin 
+                           T_SYNC_UL_Pin _T_SYNC_DL_Pin T_SYNC_DL_Pin PATH_EN_3_5G_H_Pin 
+                           PATH_EN_3_5G_DL_Pin PATH_EN_3_5G_UL_Pin PLL_ON_OFF_3_5G_LG12_Pin PLL_ON_OFF_3_5G_HG13_Pin 
+                           BOOT_LED_Pin */
+  GPIO_InitStruct.Pin = DA_SYNC_Pin|DA_SCLK_Pin|DA_DIN_Pin|_T_SYNC_UL_Pin 
+                          |T_SYNC_UL_Pin|_T_SYNC_DL_Pin|T_SYNC_DL_Pin|PATH_EN_3_5G_H_Pin 
+                          |PATH_EN_3_5G_DL_Pin|PATH_EN_3_5G_UL_Pin|PLL_ON_OFF_3_5G_LG12_Pin|PLL_ON_OFF_3_5G_HG13_Pin 
+                          |BOOT_LED_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : PLL_LD_3_5G_L_Pin PLL_LD_3_5G_H_Pin */
+  GPIO_InitStruct.Pin = PLL_LD_3_5G_L_Pin|PLL_LD_3_5G_H_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+  /*Configure GPIO pin : PLL_CLK_3_5G_Pin */
+  GPIO_InitStruct.Pin = PLL_CLK_3_5G_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(PLL_CLK_3_5G_GPIO_Port, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : PLL_EN_2_1G_DL_Pin PLL_EN_2_1G_UL_Pin */
+  GPIO_InitStruct.Pin = PLL_EN_2_1G_DL_Pin|PLL_EN_2_1G_UL_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : PLL_LD_2_1G_DL_Pin PLL_LD_2_1G_UL_Pin */
+  GPIO_InitStruct.Pin = PLL_LD_2_1G_DL_Pin|PLL_LD_2_1G_UL_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+}
+
+/* USER CODE BEGIN 4 */
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/zig_operate(2485).h

@@ -0,0 +1,132 @@
+/*
+ * zig_operate.h
+ *
+ *  Created on: 2019. 7. 26.
+ *      Author: parkyj
+ */
+
+#ifndef ZIG_OPERATE_H_
+#define ZIG_OPERATE_H_
+#include "main.h"
+bool RF_Ctrl_Main(uint8_t* data_buf);
+
void RF_Status_Get(void);
+typedef enum{
+    Header = 0,
+    Type,
+    Length,
+    Crcindex,
+}Bluecell_Prot_p;
+
+typedef enum {
+    TYPE_BLUECELL_RESET = 0,
+    TYPE_BLUECELL_SET   = 1,
+    TYPE_BLUECELL_GET   = 2,
+    TYPE_BLUECELL_SAVE   = 3,    
+}Bluecell_Prot_t;
+
+typedef enum{
+    INDEX_BLUE_HEADER = 0,
+    INDEX_BLUE_TYPE,
+    INDEX_BLUE_LENGTH,
+    INDEX_BLUE_CRCINDEX,
+    INDEX_ATT_1_8G_DL1 ,
+    INDEX_ATT_1_8G_DL2 ,
+    INDEX_ATT_1_8G_UL1 ,
+    INDEX_ATT_1_8G_UL2 ,
+    INDEX_ATT_1_8G_UL3 ,
+    INDEX_ATT_1_8G_UL4 , 
+    INDEX_ATT_2_1G_DL1  = 10,
+    INDEX_ATT_2_1G_DL2 ,
+    INDEX_ATT_2_1G_UL1 ,
+    INDEX_ATT_2_1G_UL2 ,
+    INDEX_ATT_2_1G_UL3 , 
+    INDEX_ATT_2_1G_UL4 ,
+    INDEX_ATT_3_5G_DL  ,
+    INDEX_ATT_3_5G_UL  ,
+    INDEX_ATT_3_5G_COM1,
+    INDEX_ATT_3_5G_COM2, 
+    INDEX_ATT_3_5G_COM3 = 20,
+    INDEX_PLL_1_8G_DL_H,
+    INDEX_PLL_1_8G_DL_L,
+    INDEX_PLL_1_8G_UL_H,
+    INDEX_PLL_1_8G_UL_L,
+    INDEX_PLL_2_1G_DL_H,
+    INDEX_PLL_2_1G_DL_L,
+    INDEX_PLL_2_1G_UL_H,
+    INDEX_PLL_2_1G_UL_L,
+    INDEX_PLL_3_5G_DL_H ,
+    INDEX_PLL_3_5G_DL_L = 30,
+    INDEX_PLL_3_5G_UL_H ,
+    INDEX_PLL_3_5G_UL_L ,
+    INDEX_PLL_LD_6_BIT  ,
+    INDEX_DET_1_8G_DL_IN_H  ,
+    INDEX_DET_1_8G_DL_IN_L  ,
+    INDEX_DET_1_8G_DL_OUT_H ,
+    INDEX_DET_1_8G_DL_OUT_L ,
+    INDEX_DET_1_8G_UL_IN_H  ,
+    INDEX_DET_1_8G_UL_IN_L  ,
+    INDEX_DET_1_8G_UL_OUT_H = 40,
+    INDEX_DET_1_8G_UL_OUT_L ,
+    INDEX_DET_2_1G_DL_IN_H  ,
+    INDEX_DET_2_1G_DL_IN_L  ,
+    INDEX_DET_2_1G_DL_OUT_H ,
+    INDEX_DET_2_1G_DL_OUT_L ,
+    INDEX_DET_2_1G_UL_IN_H  ,
+    INDEX_DET_2_1G_UL_IN_L  ,
+    INDEX_DET_2_1G_UL_OUT_H ,
+    INDEX_DET_2_1G_UL_OUT_L ,
+    INDEX_DET_3_5G_DL_IN_H  = 50,
+    INDEX_DET_3_5G_DL_IN_L  ,
+    INDEX_DET_3_5G_DL_OUT_H ,
+    INDEX_DET_3_5G_DL_OUT_L ,
+    INDEX_DET_3_5G_UL_IN_H  ,
+    INDEX_DET_3_5G_UL_IN_L  ,
+    INDEX_DET_3_5G_UL_OUT_H ,
+    INDEX_DET_3_5G_UL_OUT_L ,
+    INDEX_RFU_TEMP_H    ,
+    INDEX_RFU_TEMP_L    ,
+    INDEX__28V_DET_H    = 60,
+    INDEX__28V_DET_L    ,
+    INDEX_ALARM_AC      ,
+    INDEX_ALARM_DC      ,
+    INDEX_PATH_EN_1_8G_DL   ,
+    INDEX_PATH_EN_1_8G_UL   ,
+    INDEX_PATH_EN_2_1G_DL   ,
+    INDEX_PATH_EN_2_1G_UL   ,
+    INDEX_PATH_EN_3_5G_L,
+    INDEX_PATH_EN_3_5G_H,
+    INDEX_PATH_EN_3_5G_DL   =70,
+    INDEX_PATH_EN_3_5G_UL   ,
+    INDEX_PLL_ON_OFF_3_5G_H ,
+    INDEX_PLL_ON_OFF_3_5G_L ,
+    INDEX_T_SYNC_DL,
+    INDEX__T_SYNC_DL,
+    INDEX_T_SYNC_UL,
+    INDEX__T_SYNC_UL,    
+    INDEX_DAC_VCtrl_A_H,
+    INDEX_DAC_VCtrl_A_L,
+    INDEX_DAC_VCtrl_B_H = 80, 
+    INDEX_DAC_VCtrl_B_L,
+    INDEX_DAC_VCtrl_C_H,
+    INDEX_DAC_VCtrl_C_L,
+    INDEX_DAC_VCtrl_D_H,
+    INDEX_DAC_VCtrl_D_L,
+    INDEX_DAC_VCtrl_E_H,
+    INDEX_DAC_VCtrl_E_L,
+    INDEX_DAC_VCtrl_F_H,
+    INDEX_DAC_VCtrl_F_L,
+    INDEX_DAC_VCtrl_G_H = 90,
+    INDEX_DAC_VCtrl_G_L,
+    INDEX_DAC_VCtrl_H_H,
+    INDEX_DAC_VCtrl_H_L,   
+    INDEX_BLUE_CRC, 
+    INDEX_BLUE_EOF,//95
+}Bluecell_Prot_Index;
+uint8_t Prev_data[INDEX_BLUE_EOF + 1];
+uint8_t Flash_Save_data[INDEX_BLUE_EOF + 1];
+
+//extern PLL_Setting_st Pll_3_5_H;
+//extern PLL_Setting_st Pll_3_5_L;
+
+
+#endif /* ZIG_OPERATE_H_ */

insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/zig_operate(6046).c

@@ -0,0 +1,682 @@
+/*
+ * zig_operate.c
+ *
+ *  Created on: 2019. 7. 26.
+ *      Author: parkyj
+ */
+#include "zig_operate.h"
+uint8_t Prev_data[INDEX_BLUE_EOF + 1];
+uint8_t Flash_Save_data[INDEX_BLUE_EOF + 1];
+
+
+/* * * * * * * #define Struct* * * * * * * */
+PLL_Setting_st Pll_1_8GHz_DL = {
+	PLL_CLK_GPIO_Port,
+	PLL_CLK_Pin,
+	PLL_DATA_GPIO_Port,
+	PLL_DATA_Pin,
+    PLL_EN_1_8G_DL_GPIO_Port,    
+    PLL_EN_1_8G_DL_Pin,
+};
+PLL_Setting_st Pll_1_8GHz_UL = {
+    PLL_CLK_GPIO_Port,
+    PLL_CLK_Pin,
+    PLL_DATA_GPIO_Port,
+    PLL_DATA_Pin,
+    PLL_EN_1_8G_UL_GPIO_Port,    
+    PLL_EN_1_8G_UL_Pin,
+};
+PLL_Setting_st Pll_2_1GHz_DL = {
+    PLL_CLK_GPIO_Port,
+    PLL_CLK_Pin,
+    PLL_DATA_GPIO_Port,
+    PLL_DATA_Pin,
+    PLL_EN_2_1G_DL_GPIO_Port,    
+    PLL_EN_2_1G_DL_Pin,
+};
+PLL_Setting_st Pll_2_1GHz_UL = {
+    PLL_CLK_GPIO_Port,
+    PLL_CLK_Pin,
+    PLL_DATA_GPIO_Port,
+    PLL_DATA_Pin,
+    PLL_EN_2_1G_UL_GPIO_Port,    
+    PLL_EN_2_1G_UL_Pin,
+};
+/* * * * * * * * NOT YET * * * * * * * */
+PLL_Setting_st Pll_3_5GHz_DL = {
+    ATT_CLK_3_5G_GPIO_Port,
+    ATT_EN_3_5G_Pin,
+    PLL_DATA_GPIO_Port,
+    PLL_DATA_Pin,
+    PLL_EN_2_1G_DL_GPIO_Port,    
+    PLL_EN_2_1G_DL_Pin,
+};
+PLL_Setting_st Pll_3_5GHz_UL = {
+    PLL_CLK_GPIO_Port,
+    PLL_CLK_Pin,
+    PLL_DATA_GPIO_Port,
+    PLL_DATA_Pin,
+    PLL_EN_2_1G_UL_GPIO_Port,    
+    PLL_EN_2_1G_UL_Pin,
+};
+/* * * * * * * * ATTEN * * * * * * * */    
+ATTEN_Setting_st Atten_1_8Ghz_DL1 ={
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_1_8G_DL1_GPIO_Port,    
+    ATT_EN_1_8G_DL1_Pin,
+    PATH_EN_1_8G_DL_GPIO_Port,
+    PATH_EN_1_8G_DL_Pin,
+};
+
+ATTEN_Setting_st Atten_1_8Ghz_DL2 ={
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_1_8G_DL2_GPIO_Port,    
+    ATT_EN_1_8G_DL2_Pin,
+    PATH_EN_1_8G_DL_GPIO_Port,
+    PATH_EN_1_8G_DL_Pin,    
+};
+ATTEN_Setting_st Atten_1_8Ghz_UL1 ={
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_1_8G_UL1_GPIO_Port,    
+    ATT_EN_1_8G_UL1_Pin,
+    PATH_EN_1_8G_UL_GPIO_Port,
+    PATH_EN_1_8G_UL_Pin,      
+};
+ATTEN_Setting_st Atten_1_8Ghz_UL2 ={
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_1_8G_UL2_GPIO_Port,    
+    ATT_EN_1_8G_UL2_Pin,
+    PATH_EN_1_8G_UL_GPIO_Port,
+    PATH_EN_1_8G_UL_Pin,    
+};
+ATTEN_Setting_st Atten_1_8Ghz_UL3 ={
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_1_8G_UL3_GPIO_Port,    
+    ATT_EN_1_8G_UL3_Pin,
+    PATH_EN_1_8G_UL_GPIO_Port,
+    PATH_EN_1_8G_UL_Pin,    
+};
+ATTEN_Setting_st Atten_1_8Ghz_UL4 ={
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_1_8G_UL4_GPIO_Port,    
+    ATT_EN_1_8G_UL4_Pin,
+    PATH_EN_1_8G_UL_GPIO_Port,
+    PATH_EN_1_8G_UL_Pin,    
+};
+ATTEN_Setting_st Atten_2_1Ghz_DL1 ={
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_2_1G_DL1_GPIO_Port,    
+    ATT_EN_2_1G_DL1_Pin,
+    PATH_EN_2_1G_DL_GPIO_Port,
+    PATH_EN_2_1G_DL_Pin,    
+};
+ATTEN_Setting_st Atten_2_1Ghz_DL2 ={
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_2_1G_DL2_GPIO_Port,    
+    ATT_EN_2_1G_DL2_Pin,
+    PATH_EN_2_1G_DL_GPIO_Port,
+    PATH_EN_2_1G_DL_Pin,    
+};
+
+ATTEN_Setting_st Atten_2_1Ghz_UL1 ={
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_2_1G_UL1_GPIO_Port,    
+    ATT_EN_2_1G_UL1_Pin,
+    PATH_EN_2_1G_UL_GPIO_Port,
+    PATH_EN_2_1G_UL_Pin,    
+};
+ATTEN_Setting_st Atten_2_1Ghz_UL2 ={
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_2_1G_UL2_GPIO_Port,    
+    ATT_EN_2_1G_UL2_Pin,
+    PATH_EN_2_1G_UL_GPIO_Port,
+    PATH_EN_2_1G_UL_Pin,    
+};
+ATTEN_Setting_st Atten_2_1Ghz_UL3 ={
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_2_1G_UL3_GPIO_Port,    
+    ATT_EN_2_1G_UL3_Pin,
+    PATH_EN_2_1G_UL_GPIO_Port,
+    PATH_EN_2_1G_UL_Pin,    
+};
+ATTEN_Setting_st Atten_2_1Ghz_UL4 ={
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_2_1G_UL4_GPIO_Port,    
+    ATT_EN_2_1G_UL4_Pin,
+    PATH_EN_2_1G_UL_GPIO_Port,
+    PATH_EN_2_1G_UL_Pin,    
+};
+
+
+bool RF_Data_Check(uint8_t* data_buf){
+    bool ret = false;
+    bool crcret = STH30_CheckCrc(&data_buf[Type], data_buf[Length], data_buf[data_buf[Crcindex]]);
+    if(data_buf[Header] == BLUECELL_HEADER){ /*HEADER CHECK*/
+        ret= true;
+    }
+    if(crcret == true){/*CRC CHECK*/
+        ret = true;
+    }else{
+        ret = false;
+#ifdef DEBUG_PRINT
+        printf("Recv CRC Value : \"%d\"\r\n Create CRC Value : \"%d\"   \r\n",data_buf[data_buf[Crcindex]],STH30_CreateCrc(&data_buf[Type], data_buf[Length]));
+#endif /* DEBUG_PRINT */
+    }
+#ifdef DEBUG_PRINT
+    printf("CRC Result : \"%d\"   \r\n",ret);
+#endif /* DEBUG_PRINT */
+
+    return ret;
+
+}
+
+PLL_Setting_st Pll_3_5_H = {
+     PLL_CLK_3_5G_GPIO_Port,
+     PLL_CLK_3_5G_Pin,
+     PLL_DATA_3_5G_GPIO_Port,
+     PLL_DATA_3_5G_Pin,
+   PLL_EN_3_5G_H_GPIO_Port,    
+   PLL_EN_3_5G_H_Pin,
+ };
+ PLL_Setting_st Pll_3_5_L = {
+     PLL_CLK_3_5G_GPIO_Port,
+     PLL_CLK_3_5G_Pin,
+     PLL_DATA_3_5G_GPIO_Port,
+     PLL_DATA_3_5G_Pin,
+       PLL_EN_3_5G_L_GPIO_Port,    
+       PLL_EN_3_5G_L_Pin,
+ };
+void RF_Status_Get(void){
+//    printf("\r\nYJ2 : Prev_data[INDEX_DET_1_8G_DL_IN_L ] : %x\r\n",Prev_data[INDEX_DET_1_8G_DL_IN_L]);            
+    uint8_t data[10];
+    Prev_data[INDEX_BLUE_HEADER]   = BLUECELL_HEADER;
+    Prev_data[INDEX_BLUE_TYPE]     = TYPE_BLUECELL_GET;
+    Prev_data[INDEX_BLUE_LENGTH]   = INDEX_BLUE_EOF - 2;
+    Prev_data[INDEX_BLUE_CRCINDEX] = INDEX_BLUE_CRC;
+    Prev_data[INDEX_BLUE_CRC]      = STH30_CreateCrc(&Prev_data[Type], Prev_data[Length]);
+    Prev_data[INDEX_BLUE_EOF] = BLUECELL_TAILER;    
+    HAL_UART_Transmit_DMA(&huart1,&Prev_data[INDEX_BLUE_HEADER],INDEX_BLUE_EOF + 1); 
+//    printf("\r\nYJ : %x",ADCvalue[0]);
+//    printf("\r\n");
+
+}
+
+void RF_Operate(uint8_t* data_buf){
+    uint16_t temp_val = 0;
+    uint8_t  ADC_Modify = 0;
+    ADF4153_R_N_Reg_st temp_reg;
+//    printf("Prev_data[INDEX_ATT_1_8G_DL1]  : %x  data_buf[INDEX_ATT_1_8G_DL1] : %x\r\n",Prev_data[INDEX_ATT_1_8G_DL1],data_buf[INDEX_ATT_1_8G_DL1]);
+    if(Prev_data[INDEX_ATT_1_8G_DL1] != data_buf[INDEX_ATT_1_8G_DL1]){
+        
+#if 0 // PYJ.2019.07.31_BEGIN -- 
+        printf("\r\nLINE : %d  \r\n",__LINE__);    
+#endif // PYJ.2019.07.31_END -- 
+        BDA4601_atten_ctrl(BDA4601_1_8G_DL1,(data_buf[INDEX_ATT_1_8G_DL1]));
+        Prev_data[INDEX_ATT_1_8G_DL1] = data_buf[INDEX_ATT_1_8G_DL1];
+    }
+    if(Prev_data[INDEX_ATT_1_8G_DL2] != data_buf[INDEX_ATT_1_8G_DL2]){
+#ifdef DEBUG_PRINT
+        printf("\r\nLINE : %d  \r\n",__LINE__);    
+#endif /* DEBUG_PRINT */
+        BDA4601_atten_ctrl(BDA4601_1_8G_DL2,(data_buf[INDEX_ATT_1_8G_DL2]));
+        Prev_data[INDEX_ATT_1_8G_DL2] = data_buf[INDEX_ATT_1_8G_DL2];
+    }
+    if(Prev_data[INDEX_ATT_1_8G_UL1] != data_buf[INDEX_ATT_1_8G_UL1]){
+#ifdef DEBUG_PRINT
+        printf("\r\nLINE : %d  \r\n",__LINE__);    
+#endif /* DEBUG_PRINT */
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL1,(data_buf[INDEX_ATT_1_8G_UL1]));
+        Prev_data[INDEX_ATT_1_8G_UL1] = data_buf[INDEX_ATT_1_8G_UL1];
+    }
+    if(Prev_data[INDEX_ATT_1_8G_UL2] != data_buf[INDEX_ATT_1_8G_UL2]){
+#ifdef DEBUG_PRINT
+        printf("\r\nLINE : %d  \r\n",__LINE__);    
+#endif /* DEBUG_PRINT */
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL2,(data_buf[INDEX_ATT_1_8G_UL2]));
+        Prev_data[INDEX_ATT_1_8G_UL2] = data_buf[INDEX_ATT_1_8G_UL2];
+
+    }
+    if(Prev_data[INDEX_ATT_1_8G_UL3] != data_buf[INDEX_ATT_1_8G_UL3]){
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL3,(data_buf[INDEX_ATT_1_8G_UL3]));
+        Prev_data[INDEX_ATT_1_8G_UL3] = data_buf[INDEX_ATT_1_8G_UL3];
+
+    }
+    if(Prev_data[INDEX_ATT_1_8G_UL4] != data_buf[INDEX_ATT_1_8G_UL4]){
+#ifdef DEBUG_PRINT
+        printf("\r\nLINE : %d  \r\n",__LINE__);    
+#endif /* DEBUG_PRINT */
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL4,(data_buf[INDEX_ATT_1_8G_UL4]));
+        Prev_data[INDEX_ATT_1_8G_UL4] = data_buf[INDEX_ATT_1_8G_UL4];
+
+    }
+    if(Prev_data[INDEX_ATT_2_1G_DL1] != data_buf[INDEX_ATT_2_1G_DL1]){
+#ifdef DEBUG_PRINT
+        printf("\r\nLINE : %d  \r\n",__LINE__);    
+#endif /* DEBUG_PRINT */
+        BDA4601_atten_ctrl(BDA4601_2_1G_DL1,(data_buf[INDEX_ATT_2_1G_DL1]));
+        Prev_data[INDEX_ATT_2_1G_DL1] = data_buf[INDEX_ATT_2_1G_DL1];
+
+    }
+    if(Prev_data[INDEX_ATT_2_1G_DL2] != data_buf[INDEX_ATT_2_1G_DL2]){
+#ifdef DEBUG_PRINT
+        printf("\r\nLINE : %d  \r\n",__LINE__);    
+#endif /* DEBUG_PRINT */
+        BDA4601_atten_ctrl(BDA4601_2_1G_DL2,(data_buf[INDEX_ATT_2_1G_DL2]));
+        Prev_data[INDEX_ATT_2_1G_DL2] = data_buf[INDEX_ATT_2_1G_DL2];
+
+    }
+    if(Prev_data[INDEX_ATT_2_1G_UL1] != data_buf[INDEX_ATT_2_1G_UL1]){
+#ifdef DEBUG_PRINT
+        printf("\r\nLINE : %d  \r\n",__LINE__);    
+#endif /* DEBUG_PRINT */
+        BDA4601_atten_ctrl(BDA4601_2_1G_UL1,(data_buf[INDEX_ATT_2_1G_UL1]));
+        Prev_data[INDEX_ATT_2_1G_UL1] = data_buf[INDEX_ATT_2_1G_UL1];
+
+    }
+    if(Prev_data[INDEX_ATT_2_1G_UL2] != data_buf[INDEX_ATT_2_1G_UL2]){
+        BDA4601_atten_ctrl(BDA4601_2_1G_UL2,(data_buf[INDEX_ATT_2_1G_UL2]));
+        Prev_data[INDEX_ATT_2_1G_UL2] = data_buf[INDEX_ATT_2_1G_UL2];
+
+    }
+    if(Prev_data[INDEX_ATT_2_1G_UL3] != data_buf[INDEX_ATT_2_1G_UL3]){
+        BDA4601_atten_ctrl(BDA4601_2_1G_UL3,(data_buf[INDEX_ATT_2_1G_UL3]));
+        Prev_data[INDEX_ATT_2_1G_UL3] = data_buf[INDEX_ATT_2_1G_UL3];
+
+    }
+    if(Prev_data[INDEX_ATT_2_1G_UL4] != data_buf[INDEX_ATT_2_1G_UL4]){
+        BDA4601_atten_ctrl(BDA4601_2_1G_UL4,(data_buf[INDEX_ATT_2_1G_UL4]));
+        Prev_data[INDEX_ATT_2_1G_UL4] = data_buf[INDEX_ATT_2_1G_UL4];
+    }
+    if(   (Prev_data[INDEX_ATT_3_5G_DL] != data_buf[INDEX_ATT_3_5G_DL])
+        ||(Prev_data[INDEX_ATT_3_5G_UL] != data_buf[INDEX_ATT_3_5G_UL])
+        ||(Prev_data[INDEX_ATT_3_5G_COM1] != data_buf[INDEX_ATT_3_5G_COM1])
+        ||(Prev_data[INDEX_ATT_3_5G_COM2] != data_buf[INDEX_ATT_3_5G_COM2])
+        ||(Prev_data[INDEX_ATT_3_5G_COM3] != data_buf[INDEX_ATT_3_5G_COM3])
+    ){
+        ALL_ATT_3_5G.data0 = Prev_data[INDEX_ATT_3_5G_DL]   = data_buf[INDEX_ATT_3_5G_DL];
+        ALL_ATT_3_5G.data1 = Prev_data[INDEX_ATT_3_5G_UL]   = data_buf[INDEX_ATT_3_5G_UL];
+        ALL_ATT_3_5G.data2 = Prev_data[INDEX_ATT_3_5G_COM1] = data_buf[INDEX_ATT_3_5G_COM1];
+        ALL_ATT_3_5G.data3 = Prev_data[INDEX_ATT_3_5G_COM2] = data_buf[INDEX_ATT_3_5G_COM2];
+        ALL_ATT_3_5G.data4 = Prev_data[INDEX_ATT_3_5G_COM3] = data_buf[INDEX_ATT_3_5G_COM3];
+        PE43711_ALL_atten_ctrl(ALL_ATT_3_5G);
+    }
+
+    if((Prev_data[INDEX_PLL_1_8G_DL_H] != data_buf[INDEX_PLL_1_8G_DL_H])
+        && (Prev_data[INDEX_PLL_1_8G_DL_L] != data_buf[INDEX_PLL_1_8G_DL_L])
+    ){
+        Prev_data[INDEX_PLL_1_8G_DL_H] = data_buf[INDEX_PLL_1_8G_DL_H];
+        Prev_data[INDEX_PLL_1_8G_DL_L] = data_buf[INDEX_PLL_1_8G_DL_L];
+        temp_val = (data_buf[INDEX_PLL_1_8G_DL_H] << 8) | (data_buf[INDEX_PLL_1_8G_DL_L]);
+        ADF4113_Module_Ctrl(ADF4113_1_8G_DL,0x410,halSynSetFreq((temp_val * 1000000) / 10 ),0x9F8092);
+    }
+    if((Prev_data[INDEX_PLL_1_8G_UL_H] != data_buf[INDEX_PLL_1_8G_UL_H])
+        && (Prev_data[INDEX_PLL_1_8G_UL_L] != data_buf[INDEX_PLL_1_8G_UL_L])){
+        temp_val = (data_buf[INDEX_PLL_1_8G_UL_H] << 8) | (data_buf[INDEX_PLL_1_8G_UL_L]);
+        Prev_data[INDEX_PLL_1_8G_UL_H] = data_buf[INDEX_PLL_1_8G_UL_H];
+        Prev_data[INDEX_PLL_1_8G_UL_L] = data_buf[INDEX_PLL_1_8G_UL_L];
+        ADF4113_Module_Ctrl(ADF4113_1_8G_UL,0x410,halSynSetFreq((temp_val * 1000000) / 10),0x9F8092);
+    }
+    if((Prev_data[INDEX_PLL_2_1G_DL_H] != data_buf[INDEX_PLL_2_1G_DL_H])
+        && (Prev_data[INDEX_PLL_2_1G_DL_L] != data_buf[INDEX_PLL_2_1G_DL_L])){
+        temp_val = ((data_buf[INDEX_PLL_2_1G_DL_H] << 8) | (data_buf[INDEX_PLL_2_1G_DL_L]));
+        Prev_data[INDEX_PLL_2_1G_DL_H] = data_buf[INDEX_PLL_2_1G_DL_H];
+        Prev_data[INDEX_PLL_2_1G_DL_L] = data_buf[INDEX_PLL_2_1G_DL_L];        
+        ADF4113_Module_Ctrl(ADF4113_2_1G_DL,0x410,halSynSetFreq((temp_val * 1000000) / 10),0x9F8092);
+    }
+    if((Prev_data[INDEX_PLL_2_1G_UL_H] != data_buf[INDEX_PLL_2_1G_UL_H])
+        && (Prev_data[INDEX_PLL_2_1G_UL_L] != data_buf[INDEX_PLL_2_1G_UL_L])){
+        Prev_data[INDEX_PLL_2_1G_UL_H] = data_buf[INDEX_PLL_2_1G_UL_H];
+        Prev_data[INDEX_PLL_2_1G_UL_L] = data_buf[INDEX_PLL_2_1G_UL_L];          
+        temp_val = (data_buf[INDEX_PLL_2_1G_UL_H] << 8) | (data_buf[INDEX_PLL_2_1G_UL_L]);
+        ADF4113_Module_Ctrl(ADF4113_2_1G_UL,0x410,halSynSetFreq((temp_val * 1000000) / 10),0x9F8092);
+
+    }
+    if((Prev_data[INDEX_PLL_3_5G_DL_H] != data_buf[INDEX_PLL_3_5G_DL_H])
+        && (Prev_data[INDEX_PLL_3_5G_DL_L] != data_buf[INDEX_PLL_3_5G_DL_L])){
+        Prev_data[INDEX_PLL_3_5G_DL_H] = data_buf[INDEX_PLL_3_5G_DL_H];
+        Prev_data[INDEX_PLL_3_5G_DL_L] = data_buf[INDEX_PLL_3_5G_DL_L];
+        temp_val = (data_buf[INDEX_PLL_3_5G_DL_H] << 8) | (data_buf[INDEX_PLL_3_5G_DL_L]);
+        temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
+        ADF4153_Module_Ctrl(Pll_3_5_L,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
+    }
+    if((Prev_data[INDEX_PLL_3_5G_UL_H] != data_buf[INDEX_PLL_3_5G_UL_H])
+        && (Prev_data[INDEX_PLL_3_5G_UL_L] != data_buf[INDEX_PLL_3_5G_UL_L])){
+        Prev_data[INDEX_PLL_3_5G_UL_H] = data_buf[INDEX_PLL_3_5G_UL_H];
+        Prev_data[INDEX_PLL_3_5G_UL_L] = data_buf[INDEX_PLL_3_5G_UL_L];
+        temp_val = (data_buf[INDEX_PLL_3_5G_UL_H] << 8) | (data_buf[INDEX_PLL_3_5G_UL_L]);
+        temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
+        ADF4153_Module_Ctrl(Pll_3_5_H,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
+
+    }
+    if(Prev_data[INDEX_PLL_LD_6_BIT] != data_buf[INDEX_PLL_LD_6_BIT]){
+
+    }
+#if 0 // PYJ.2019.07.28_BEGIN -- 
+    if(Prev_data[INDEX_DET_1_8G_DL_IN_H] != data_buf[INDEX_DET_1_8G_DL_IN_H]){
+
+    }
+    if(Prev_data[INDEX_DET_1_8G_DL_IN_L] != data_buf[INDEX_DET_1_8G_DL_IN_L]){
+
+    }
+    if(Prev_data[INDEX_DET_1_8G_DL_OUT_H] != data_buf[INDEX_DET_1_8G_DL_OUT_H]){
+
+    }
+    if(Prev_data[INDEX_DET_1_8G_DL_OUT_L] != data_buf[INDEX_DET_1_8G_DL_OUT_L]){
+
+    }
+    if(Prev_data[INDEX_DET_1_8G_UL_IN_H] != data_buf[INDEX_DET_1_8G_UL_IN_H]){
+
+    }
+    if(Prev_data[INDEX_DET_1_8G_UL_IN_L] != data_buf[INDEX_DET_1_8G_UL_IN_L]){
+
+    }
+    if(Prev_data[INDEX_DET_1_8G_UL_OUT_H] != data_buf[INDEX_DET_1_8G_UL_OUT_H]){
+
+    }
+    if(Prev_data[INDEX_DET_1_8G_UL_OUT_L] != data_buf[INDEX_DET_1_8G_UL_OUT_L]){
+
+    }
+    if(Prev_data[INDEX_DET_2_1G_DL_IN_H] != data_buf[INDEX_DET_2_1G_DL_IN_H]){
+
+    }
+    if(Prev_data[INDEX_DET_2_1G_DL_IN_L] != data_buf[INDEX_DET_2_1G_DL_IN_L]){
+
+    }
+    if(Prev_data[INDEX_DET_2_1G_DL_OUT_H] != data_buf[INDEX_DET_2_1G_DL_OUT_H]){
+
+    }
+    if(Prev_data[INDEX_DET_2_1G_DL_OUT_L] != data_buf[INDEX_DET_2_1G_DL_OUT_L]){
+
+    }
+    if(Prev_data[INDEX_DET_2_1G_UL_IN_H] != data_buf[INDEX_DET_2_1G_UL_IN_H]){
+
+    }
+    if(Prev_data[INDEX_DET_2_1G_UL_IN_L] != data_buf[INDEX_DET_2_1G_UL_IN_L]){
+
+    }
+
+    if(Prev_data[INDEX_DET_2_1G_UL_OUT_H] != data_buf[INDEX_DET_2_1G_UL_OUT_H]){
+
+    }
+    if(Prev_data[INDEX_DET_2_1G_UL_OUT_L] != data_buf[INDEX_DET_2_1G_UL_OUT_L]){
+
+    }
+    if(Prev_data[INDEX_DET_3_5G_DL_IN_H] != data_buf[INDEX_DET_3_5G_DL_IN_H]){
+
+    }
+    if(Prev_data[INDEX_DET_3_5G_DL_IN_L] != data_buf[INDEX_DET_3_5G_DL_IN_L]){
+
+    }
+    if(Prev_data[INDEX_DET_3_5G_DL_OUT_L] != data_buf[INDEX_DET_3_5G_DL_OUT_L]){
+
+    }
+    if(Prev_data[INDEX_DET_3_5G_DL_OUT_H] != data_buf[INDEX_DET_3_5G_DL_OUT_H]){
+
+    }
+    if(Prev_data[INDEX_DET_3_5G_UL_IN_H] != data_buf[INDEX_DET_3_5G_UL_IN_H]){
+
+    }
+    if(Prev_data[INDEX_DET_3_5G_UL_IN_L] != data_buf[INDEX_DET_3_5G_UL_IN_L]){
+
+    }
+
+    if(Prev_data[INDEX_DET_3_5G_UL_OUT_H] != data_buf[INDEX_DET_3_5G_UL_OUT_H]){
+
+    }
+    if(Prev_data[INDEX_DET_3_5G_UL_OUT_L] != data_buf[INDEX_DET_3_5G_UL_OUT_L]){
+
+    }
+    if(Prev_data[INDEX_RFU_TEMP_H] != data_buf[INDEX_RFU_TEMP_H]){
+
+    }
+    if(Prev_data[INDEX_RFU_TEMP_L] != data_buf[INDEX_RFU_TEMP_L]){
+
+    }
+    if(Prev_data[INDEX__28V_DET_H] != data_buf[INDEX__28V_DET_H]){
+
+    }
+    if(Prev_data[INDEX__28V_DET_L] != data_buf[INDEX__28V_DET_L]){
+
+    }
+#endif // PYJ.2019.07.28_END -- 
+    if(Prev_data[INDEX_ALARM_AC] != data_buf[INDEX_ALARM_AC]){
+
+    }
+    if(Prev_data[INDEX_ALARM_DC] != data_buf[INDEX_ALARM_DC]){
+
+    }
+    if(Prev_data[INDEX_PATH_EN_1_8G_DL] != data_buf[INDEX_PATH_EN_1_8G_DL]){
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_1_8G_DL,data_buf[INDEX_PATH_EN_1_8G_DL]);
+        Prev_data[INDEX_PATH_EN_1_8G_DL] = data_buf[INDEX_PATH_EN_1_8G_DL];
+    }
+    if(Prev_data[INDEX_PATH_EN_1_8G_UL] != data_buf[INDEX_PATH_EN_1_8G_UL]){
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_1_8G_UL,data_buf[INDEX_PATH_EN_1_8G_UL]);
+        Prev_data[INDEX_PATH_EN_1_8G_UL] = data_buf[INDEX_PATH_EN_1_8G_UL];
+
+    }
+
+    if(Prev_data[INDEX_PATH_EN_2_1G_DL] != data_buf[INDEX_PATH_EN_2_1G_DL]){
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_2_1G_DL,data_buf[INDEX_PATH_EN_2_1G_DL]);
+        Prev_data[INDEX_PATH_EN_2_1G_DL] = data_buf[INDEX_PATH_EN_2_1G_DL];
+
+    }
+    if(Prev_data[INDEX_PATH_EN_2_1G_UL] != data_buf[INDEX_PATH_EN_2_1G_UL]){
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_2_1G_UL,data_buf[INDEX_PATH_EN_2_1G_UL]);
+        Prev_data[INDEX_PATH_EN_2_1G_UL] = data_buf[INDEX_PATH_EN_2_1G_UL];
+
+    }
+    if(Prev_data[INDEX_PATH_EN_3_5G_L] != data_buf[INDEX_PATH_EN_3_5G_L]){
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_L,data_buf[INDEX_PATH_EN_3_5G_L]);
+        Prev_data[INDEX_PATH_EN_3_5G_L] = data_buf[INDEX_PATH_EN_3_5G_L];
+
+    }
+    if(Prev_data[INDEX_PATH_EN_3_5G_H] != data_buf[INDEX_PATH_EN_3_5G_H]){
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_H,data_buf[INDEX_PATH_EN_3_5G_H]);
+        Prev_data[INDEX_PATH_EN_3_5G_H] = data_buf[INDEX_PATH_EN_3_5G_H];
+
+    }
+    if(Prev_data[INDEX_PATH_EN_3_5G_DL] != data_buf[INDEX_PATH_EN_3_5G_DL]){
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_DL,data_buf[INDEX_PATH_EN_3_5G_DL]);
+        Prev_data[INDEX_PATH_EN_3_5G_DL] = data_buf[INDEX_PATH_EN_3_5G_DL];
+
+    }
+    if(Prev_data[INDEX_PATH_EN_3_5G_UL] != data_buf[INDEX_PATH_EN_3_5G_UL]){
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_UL,data_buf[INDEX_PATH_EN_3_5G_UL]);
+        Prev_data[INDEX_PATH_EN_3_5G_UL] = data_buf[INDEX_PATH_EN_3_5G_UL];
+
+    }
+    if(Prev_data[INDEX_PLL_ON_OFF_3_5G_H] != data_buf[INDEX_PLL_ON_OFF_3_5G_H]){
+        Power_ON_OFF_Ctrl(INDEX_PLL_ON_OFF_3_5G_H,data_buf[INDEX_PLL_ON_OFF_3_5G_H]);
+        Prev_data[INDEX_PLL_ON_OFF_3_5G_H] = data_buf[INDEX_PLL_ON_OFF_3_5G_H];
+        HAL_Delay(10);
+        printf("POWER : %d \r\n",Prev_data[INDEX_PLL_ON_OFF_3_5G_H]);
+        if(data_buf[INDEX_PLL_ON_OFF_3_5G_H]){
+            printf("PLL CTRL START !! \r\n");
+//            ADF4153_Init();
+            temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
+            ADF4153_Module_Ctrl(Pll_3_5_H,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
+        }
+    }
+    if(Prev_data[INDEX_PLL_ON_OFF_3_5G_L] != data_buf[INDEX_PLL_ON_OFF_3_5G_L]){
+        Power_ON_OFF_Ctrl(INDEX_PLL_ON_OFF_3_5G_L,data_buf[INDEX_PLL_ON_OFF_3_5G_L]);
+        Prev_data[INDEX_PLL_ON_OFF_3_5G_L] = data_buf[INDEX_PLL_ON_OFF_3_5G_L];
+        HAL_Delay(10);
+        printf("POWER : %d \r\n",Prev_data[INDEX_PLL_ON_OFF_3_5G_L]);        
+        if(data_buf[INDEX_PLL_ON_OFF_3_5G_L]){
+            printf("PLL CTRL START !! \r\n");
+            temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);            
+            ADF4153_Module_Ctrl(Pll_3_5_L,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
+        }
+    }
+
+    if(Prev_data[INDEX_T_SYNC_DL] != data_buf[INDEX_T_SYNC_DL]){
+        Prev_data[INDEX_T_SYNC_DL] = data_buf[INDEX_T_SYNC_DL];
+        Power_ON_OFF_Ctrl(INDEX_T_SYNC_DL,data_buf[INDEX_T_SYNC_DL]);
+    }
+    if(Prev_data[INDEX__T_SYNC_DL] != data_buf[INDEX__T_SYNC_DL]){
+        Prev_data[INDEX__T_SYNC_DL] = data_buf[INDEX__T_SYNC_DL];
+        Power_ON_OFF_Ctrl(INDEX__T_SYNC_DL,data_buf[INDEX__T_SYNC_DL]);
+    }
+    if(Prev_data[INDEX_T_SYNC_UL] != data_buf[INDEX_T_SYNC_UL]){
+        Prev_data[INDEX_T_SYNC_UL] = data_buf[INDEX_T_SYNC_UL];
+        Power_ON_OFF_Ctrl(INDEX_T_SYNC_UL,data_buf[INDEX_T_SYNC_UL]);
+    }
+    if(Prev_data[INDEX__T_SYNC_UL] != data_buf[INDEX__T_SYNC_UL]){
+        Prev_data[INDEX__T_SYNC_UL] = data_buf[INDEX__T_SYNC_UL];
+        Power_ON_OFF_Ctrl(INDEX__T_SYNC_UL,data_buf[INDEX__T_SYNC_UL]);
+    }
+
+
+    if((Prev_data[INDEX_DAC_VCtrl_A_H] != data_buf[INDEX_DAC_VCtrl_A_H])
+        ||(Prev_data[INDEX_DAC_VCtrl_A_L] != data_buf[INDEX_DAC_VCtrl_A_L])){
+        ADC_Modify = 1;
+
+        Prev_data[INDEX_DAC_VCtrl_A_H] = data_buf[INDEX_DAC_VCtrl_A_H];
+        Prev_data[INDEX_DAC_VCtrl_A_L] = data_buf[INDEX_DAC_VCtrl_A_L];
+    }
+    if((Prev_data[INDEX_DAC_VCtrl_B_H] != data_buf[INDEX_DAC_VCtrl_B_H])
+        ||(Prev_data[INDEX_DAC_VCtrl_B_L] != data_buf[INDEX_DAC_VCtrl_B_L])){
+        ADC_Modify = 1;
+        
+        Prev_data[INDEX_DAC_VCtrl_B_H] = data_buf[INDEX_DAC_VCtrl_B_H];
+        Prev_data[INDEX_DAC_VCtrl_B_L] = data_buf[INDEX_DAC_VCtrl_B_L];        
+    }    
+    if((Prev_data[INDEX_DAC_VCtrl_C_H] != data_buf[INDEX_DAC_VCtrl_C_H])
+        ||(Prev_data[INDEX_DAC_VCtrl_C_L] != data_buf[INDEX_DAC_VCtrl_C_L])){
+        ADC_Modify = 1;
+
+        Prev_data[INDEX_DAC_VCtrl_C_H] = data_buf[INDEX_DAC_VCtrl_C_H];
+        Prev_data[INDEX_DAC_VCtrl_C_L] = data_buf[INDEX_DAC_VCtrl_C_L];        
+    }
+    if((Prev_data[INDEX_DAC_VCtrl_D_H] != data_buf[INDEX_DAC_VCtrl_D_H])
+        ||(Prev_data[INDEX_DAC_VCtrl_D_L] != data_buf[INDEX_DAC_VCtrl_D_L])){
+        ADC_Modify = 1;
+        Prev_data[INDEX_DAC_VCtrl_D_H] = data_buf[INDEX_DAC_VCtrl_D_H];
+        Prev_data[INDEX_DAC_VCtrl_D_L] = data_buf[INDEX_DAC_VCtrl_D_L];
+    }
+    if((Prev_data[INDEX_DAC_VCtrl_E_H] != data_buf[INDEX_DAC_VCtrl_E_H])
+        ||(Prev_data[INDEX_DAC_VCtrl_E_L] != data_buf[INDEX_DAC_VCtrl_E_L])){
+        ADC_Modify = 1;
+
+        Prev_data[INDEX_DAC_VCtrl_E_H] = data_buf[INDEX_DAC_VCtrl_E_H];
+        Prev_data[INDEX_DAC_VCtrl_E_L] = data_buf[INDEX_DAC_VCtrl_E_L];        
+    }
+    if((Prev_data[INDEX_DAC_VCtrl_F_H] != data_buf[INDEX_DAC_VCtrl_F_H])
+        ||(Prev_data[INDEX_DAC_VCtrl_F_L] != data_buf[INDEX_DAC_VCtrl_F_L])){
+        ADC_Modify = 1;
+        Prev_data[INDEX_DAC_VCtrl_F_H] = data_buf[INDEX_DAC_VCtrl_F_H];
+        Prev_data[INDEX_DAC_VCtrl_F_L] = data_buf[INDEX_DAC_VCtrl_F_L];        
+    }
+    if((Prev_data[INDEX_DAC_VCtrl_G_H] != data_buf[INDEX_DAC_VCtrl_G_H])
+        ||(Prev_data[INDEX_DAC_VCtrl_G_L] != data_buf[INDEX_DAC_VCtrl_G_L])){
+        ADC_Modify = 1;
+        Prev_data[INDEX_DAC_VCtrl_G_H] = data_buf[INDEX_DAC_VCtrl_G_H];
+        Prev_data[INDEX_DAC_VCtrl_G_L] = data_buf[INDEX_DAC_VCtrl_G_L];        
+    }    
+    if((Prev_data[INDEX_DAC_VCtrl_H_H] != data_buf[INDEX_DAC_VCtrl_H_H])
+        ||(Prev_data[INDEX_DAC_VCtrl_H_L] != data_buf[INDEX_DAC_VCtrl_H_L])){
+        ADC_Modify = 1;
+        Prev_data[INDEX_DAC_VCtrl_H_H] = data_buf[INDEX_DAC_VCtrl_H_H];
+        Prev_data[INDEX_DAC_VCtrl_H_L] = data_buf[INDEX_DAC_VCtrl_H_L];        
+    }
+    if(ADC_Modify){
+//        SubmitDAC(0xF000);
+//        HAL_Delay(1);
+//        SubmitDAC(0x800C);
+//        SubmitDAC(0xA000);
+        SubmitDAC((Prev_data[INDEX_DAC_VCtrl_A_H] << 8 | Prev_data[INDEX_DAC_VCtrl_A_L]) );    
+        SubmitDAC((Prev_data[INDEX_DAC_VCtrl_B_H] << 8 | Prev_data[INDEX_DAC_VCtrl_B_L]));    
+//        SubmitDAC(0x2FFF );
+        SubmitDAC((Prev_data[INDEX_DAC_VCtrl_C_H] << 8 | Prev_data[INDEX_DAC_VCtrl_C_L]));
+        SubmitDAC((Prev_data[INDEX_DAC_VCtrl_D_H] << 8 | Prev_data[INDEX_DAC_VCtrl_D_L]));
+        SubmitDAC((Prev_data[INDEX_DAC_VCtrl_E_H] << 8 | Prev_data[INDEX_DAC_VCtrl_E_L]));    
+        SubmitDAC((Prev_data[INDEX_DAC_VCtrl_F_H] << 8 | Prev_data[INDEX_DAC_VCtrl_F_L]));
+        SubmitDAC((Prev_data[INDEX_DAC_VCtrl_G_H] << 8 | Prev_data[INDEX_DAC_VCtrl_G_L]));
+        SubmitDAC((Prev_data[INDEX_DAC_VCtrl_H_H] << 8 | Prev_data[INDEX_DAC_VCtrl_H_L]));
+    }
+    
+}
+
+
+bool RF_Ctrl_Main(uint8_t* data_buf){
+    bool ret = false;
+    Bluecell_Prot_t type = data_buf[Type];
+    ret = RF_Data_Check(&data_buf[Header]); /* ERROR CHECK */
+    if(ret == false){
+        HAL_UART_Transmit(&huart1,&data_buf[INDEX_BLUE_HEADER],data_buf[INDEX_BLUE_LENGTH] + 2 + 1,3000); 
+        return ret;
+    }
+    
+    switch(type){
+    case TYPE_BLUECELL_RESET:
+        for(uint8_t i =0 ; i < data_buf[Length] + 6; i++)
+            printf("%02x ",data_buf[i]);
+        printf("Reset Start \r\n");
+        NVIC_SystemReset();
+        break;
+    case TYPE_BLUECELL_SET:
+#if 0 // PYJ.2019.07.31_BEGIN -- 
+    printf("TYPE_BLUECELL_SET : ");
+    for(uint8_t i =0 ; i < INDEX_BLUE_EOF + 1; i++)
+        printf("%02x ",data_buf[i]);
+#endif // PYJ.2019.07.31_END -- 
+        RF_Operate(&data_buf[Header]);
+        
+
+//        ADF4153_Freq_Calc(3465500000,40000000,2,5000);
+//        ADF4153_Freq_Calc(3993450000,40000000,2,5000);
+//        halSynSetFreq(1995000000);
+//        halSynSetFreq(1600000000);
+//        halSynSetFreq(1455000000);        
+        break;
+    case TYPE_BLUECELL_GET:
+        printf("\r\nTYPE_BLUECELL_GET : \r\n");
+        RF_Status_Get();
+        break;
+    case TYPE_BLUECELL_SAVE:
+        Bluecell_Flash_Write(&Prev_data[INDEX_BLUE_HEADER]);
+        break;
+        default:
+#ifdef DEBUG_PRINT // PYJ.2019.07.27_BEGIN --         
+            printf("Function : %s   LINE : %d    type : %d \r\n",__func__,__LINE__,type);
+#endif
+            break;
+    }
+    return ret;
+}

insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/zig_operate(6248).c

@@ -0,0 +1,681 @@
+/*
+ * zig_operate.c
+ *
+ *  Created on: 2019. 7. 26.
+ *      Author: parkyj
+ */
+#include "zig_operate.h"
+uint8_t Prev_data[INDEX_BLUE_EOF + 1];
+uint8_t Flash_Save_data[INDEX_BLUE_EOF + 1];
+
+
+/* * * * * * * #define Struct* * * * * * * */
+PLL_Setting_st Pll_1_8GHz_DL = {
+	PLL_CLK_GPIO_Port,
+	PLL_CLK_Pin,
+	PLL_DATA_GPIO_Port,
+	PLL_DATA_Pin,
+    PLL_EN_1_8G_DL_GPIO_Port,    
+    PLL_EN_1_8G_DL_Pin,
+};
+PLL_Setting_st Pll_1_8GHz_UL = {
+    PLL_CLK_GPIO_Port,
+    PLL_CLK_Pin,
+    PLL_DATA_GPIO_Port,
+    PLL_DATA_Pin,
+    PLL_EN_1_8G_UL_GPIO_Port,    
+    PLL_EN_1_8G_UL_Pin,
+};
+PLL_Setting_st Pll_2_1GHz_DL = {
+    PLL_CLK_GPIO_Port,
+    PLL_CLK_Pin,
+    PLL_DATA_GPIO_Port,
+    PLL_DATA_Pin,
+    PLL_EN_2_1G_DL_GPIO_Port,    
+    PLL_EN_2_1G_DL_Pin,
+};
+PLL_Setting_st Pll_2_1GHz_UL = {
+    PLL_CLK_GPIO_Port,
+    PLL_CLK_Pin,
+    PLL_DATA_GPIO_Port,
+    PLL_DATA_Pin,
+    PLL_EN_2_1G_UL_GPIO_Port,    
+    PLL_EN_2_1G_UL_Pin,
+};
+/* * * * * * * * NOT YET * * * * * * * */
+PLL_Setting_st Pll_3_5GHz_DL = {
+    ATT_CLK_3_5G_GPIO_Port,
+    ATT_EN_3_5G_Pin,
+    PLL_DATA_GPIO_Port,
+    PLL_DATA_Pin,
+    PLL_EN_2_1G_DL_GPIO_Port,    
+    PLL_EN_2_1G_DL_Pin,
+};
+PLL_Setting_st Pll_3_5GHz_UL = {
+    PLL_CLK_GPIO_Port,
+    PLL_CLK_Pin,
+    PLL_DATA_GPIO_Port,
+    PLL_DATA_Pin,
+    PLL_EN_2_1G_UL_GPIO_Port,    
+    PLL_EN_2_1G_UL_Pin,
+};
+/* * * * * * * * ATTEN * * * * * * * */    
+ATTEN_Setting_st Atten_1_8Ghz_DL1 ={
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_1_8G_DL1_GPIO_Port,    
+    ATT_EN_1_8G_DL1_Pin,
+    PATH_EN_1_8G_DL_GPIO_Port,
+    PATH_EN_1_8G_DL_Pin,
+};
+
+ATTEN_Setting_st Atten_1_8Ghz_DL2 ={
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_1_8G_DL2_GPIO_Port,    
+    ATT_EN_1_8G_DL2_Pin,
+    PATH_EN_1_8G_DL_GPIO_Port,
+    PATH_EN_1_8G_DL_Pin,    
+};
+ATTEN_Setting_st Atten_1_8Ghz_UL1 ={
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_1_8G_UL1_GPIO_Port,    
+    ATT_EN_1_8G_UL1_Pin,
+    PATH_EN_1_8G_UL_GPIO_Port,
+    PATH_EN_1_8G_UL_Pin,      
+};
+ATTEN_Setting_st Atten_1_8Ghz_UL2 ={
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_1_8G_UL2_GPIO_Port,    
+    ATT_EN_1_8G_UL2_Pin,
+    PATH_EN_1_8G_UL_GPIO_Port,
+    PATH_EN_1_8G_UL_Pin,    
+};
+ATTEN_Setting_st Atten_1_8Ghz_UL3 ={
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_1_8G_UL3_GPIO_Port,    
+    ATT_EN_1_8G_UL3_Pin,
+    PATH_EN_1_8G_UL_GPIO_Port,
+    PATH_EN_1_8G_UL_Pin,    
+};
+ATTEN_Setting_st Atten_1_8Ghz_UL4 ={
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_1_8G_UL4_GPIO_Port,    
+    ATT_EN_1_8G_UL4_Pin,
+    PATH_EN_1_8G_UL_GPIO_Port,
+    PATH_EN_1_8G_UL_Pin,    
+};
+ATTEN_Setting_st Atten_2_1Ghz_DL1 ={
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_2_1G_DL1_GPIO_Port,    
+    ATT_EN_2_1G_DL1_Pin,
+    PATH_EN_2_1G_DL_GPIO_Port,
+    PATH_EN_2_1G_DL_Pin,    
+};
+ATTEN_Setting_st Atten_2_1Ghz_DL2 ={
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_2_1G_DL2_GPIO_Port,    
+    ATT_EN_2_1G_DL2_Pin,
+    PATH_EN_2_1G_DL_GPIO_Port,
+    PATH_EN_2_1G_DL_Pin,    
+};
+
+ATTEN_Setting_st Atten_2_1Ghz_UL1 ={
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_2_1G_UL1_GPIO_Port,    
+    ATT_EN_2_1G_UL1_Pin,
+    PATH_EN_2_1G_UL_GPIO_Port,
+    PATH_EN_2_1G_UL_Pin,    
+};
+ATTEN_Setting_st Atten_2_1Ghz_UL2 ={
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_2_1G_UL2_GPIO_Port,    
+    ATT_EN_2_1G_UL2_Pin,
+    PATH_EN_2_1G_UL_GPIO_Port,
+    PATH_EN_2_1G_UL_Pin,    
+};
+ATTEN_Setting_st Atten_2_1Ghz_UL3 ={
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_2_1G_UL3_GPIO_Port,    
+    ATT_EN_2_1G_UL3_Pin,
+    PATH_EN_2_1G_UL_GPIO_Port,
+    PATH_EN_2_1G_UL_Pin,    
+};
+ATTEN_Setting_st Atten_2_1Ghz_UL4 ={
+    ATT_CLK_GPIO_Port,
+    ATT_CLK_Pin,
+    ATT_DATA_GPIO_Port,
+    ATT_DATA_Pin,
+    ATT_EN_2_1G_UL4_GPIO_Port,    
+    ATT_EN_2_1G_UL4_Pin,
+    PATH_EN_2_1G_UL_GPIO_Port,
+    PATH_EN_2_1G_UL_Pin,    
+};
+
+
+bool RF_Data_Check(uint8_t* data_buf){
+    bool ret = false;
+    bool crcret = STH30_CheckCrc(&data_buf[Type], data_buf[Length], data_buf[data_buf[Crcindex]]);
+    if(data_buf[Header] == BLUECELL_HEADER){ /*HEADER CHECK*/
+        ret= true;
+    }
+    if(crcret == true){/*CRC CHECK*/
+        ret = true;
+    }else{
+        ret = false;
+#ifdef DEBUG_PRINT
+        printf("Recv CRC Value : \"%d\"\r\n Create CRC Value : \"%d\"   \r\n",data_buf[data_buf[Crcindex]],STH30_CreateCrc(&data_buf[Type], data_buf[Length]));
+#endif /* DEBUG_PRINT */
+    }
+#ifdef DEBUG_PRINT
+    printf("CRC Result : \"%d\"   \r\n",ret);
+#endif /* DEBUG_PRINT */
+
+    return ret;
+
+}
+
+PLL_Setting_st Pll_3_5_H = {
+     PLL_CLK_3_5G_GPIO_Port,
+     PLL_CLK_3_5G_Pin,
+     PLL_DATA_3_5G_GPIO_Port,
+     PLL_DATA_3_5G_Pin,
+   PLL_EN_3_5G_H_GPIO_Port,    
+   PLL_EN_3_5G_H_Pin,
+ };
+ PLL_Setting_st Pll_3_5_L = {
+     PLL_CLK_3_5G_GPIO_Port,
+     PLL_CLK_3_5G_Pin,
+     PLL_DATA_3_5G_GPIO_Port,
+     PLL_DATA_3_5G_Pin,
+       PLL_EN_3_5G_L_GPIO_Port,    
+       PLL_EN_3_5G_L_Pin,
+ };
+void RF_Status_Get(void){
+//    printf("\r\nYJ2 : Prev_data[INDEX_DET_1_8G_DL_IN_L ] : %x\r\n",Prev_data[INDEX_DET_1_8G_DL_IN_L]);            
+    uint8_t data[10];
+    Prev_data[INDEX_BLUE_HEADER]   = BLUECELL_HEADER;
+    Prev_data[INDEX_BLUE_TYPE]     = TYPE_BLUECELL_GET;
+    Prev_data[INDEX_BLUE_LENGTH]   = INDEX_BLUE_EOF - 2;
+    Prev_data[INDEX_BLUE_CRCINDEX] = INDEX_BLUE_CRC;
+    Prev_data[INDEX_BLUE_CRC]      = STH30_CreateCrc(&Prev_data[Type], Prev_data[Length]);
+    Prev_data[INDEX_BLUE_EOF] = BLUECELL_TAILER;    
+    HAL_UART_Transmit_DMA(&huart1,&Prev_data[INDEX_BLUE_HEADER],INDEX_BLUE_EOF + 1); 
+//    printf("\r\nYJ : %x",ADCvalue[0]);
+//    printf("\r\n");
+
+}
+
+void RF_Operate(uint8_t* data_buf){
+    uint16_t temp_val = 0;
+    uint8_t  ADC_Modify = 0;
+    ADF4153_R_N_Reg_st temp_reg;
+//    printf("Prev_data[INDEX_ATT_1_8G_DL1]  : %x  data_buf[INDEX_ATT_1_8G_DL1] : %x\r\n",Prev_data[INDEX_ATT_1_8G_DL1],data_buf[INDEX_ATT_1_8G_DL1]);
+    if(Prev_data[INDEX_ATT_1_8G_DL1] != data_buf[INDEX_ATT_1_8G_DL1]){
+        
+#if 0 // PYJ.2019.07.31_BEGIN -- 
+        printf("\r\nLINE : %d  \r\n",__LINE__);    
+#endif // PYJ.2019.07.31_END -- 
+        BDA4601_atten_ctrl(BDA4601_1_8G_DL1,(data_buf[INDEX_ATT_1_8G_DL1]));
+        Prev_data[INDEX_ATT_1_8G_DL1] = data_buf[INDEX_ATT_1_8G_DL1];
+    }
+    if(Prev_data[INDEX_ATT_1_8G_DL2] != data_buf[INDEX_ATT_1_8G_DL2]){
+#ifdef DEBUG_PRINT
+        printf("\r\nLINE : %d  \r\n",__LINE__);    
+#endif /* DEBUG_PRINT */
+        BDA4601_atten_ctrl(BDA4601_1_8G_DL2,(data_buf[INDEX_ATT_1_8G_DL2]));
+        Prev_data[INDEX_ATT_1_8G_DL2] = data_buf[INDEX_ATT_1_8G_DL2];
+    }
+    if(Prev_data[INDEX_ATT_1_8G_UL1] != data_buf[INDEX_ATT_1_8G_UL1]){
+#ifdef DEBUG_PRINT
+        printf("\r\nLINE : %d  \r\n",__LINE__);    
+#endif /* DEBUG_PRINT */
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL1,(data_buf[INDEX_ATT_1_8G_UL1]));
+        Prev_data[INDEX_ATT_1_8G_UL1] = data_buf[INDEX_ATT_1_8G_UL1];
+    }
+    if(Prev_data[INDEX_ATT_1_8G_UL2] != data_buf[INDEX_ATT_1_8G_UL2]){
+#ifdef DEBUG_PRINT
+        printf("\r\nLINE : %d  \r\n",__LINE__);    
+#endif /* DEBUG_PRINT */
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL2,(data_buf[INDEX_ATT_1_8G_UL2]));
+        Prev_data[INDEX_ATT_1_8G_UL2] = data_buf[INDEX_ATT_1_8G_UL2];
+
+    }
+    if(Prev_data[INDEX_ATT_1_8G_UL3] != data_buf[INDEX_ATT_1_8G_UL3]){
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL3,(data_buf[INDEX_ATT_1_8G_UL3]));
+        Prev_data[INDEX_ATT_1_8G_UL3] = data_buf[INDEX_ATT_1_8G_UL3];
+
+    }
+    if(Prev_data[INDEX_ATT_1_8G_UL4] != data_buf[INDEX_ATT_1_8G_UL4]){
+#ifdef DEBUG_PRINT
+        printf("\r\nLINE : %d  \r\n",__LINE__);    
+#endif /* DEBUG_PRINT */
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL4,(data_buf[INDEX_ATT_1_8G_UL4]));
+        Prev_data[INDEX_ATT_1_8G_UL4] = data_buf[INDEX_ATT_1_8G_UL4];
+
+    }
+    if(Prev_data[INDEX_ATT_2_1G_DL1] != data_buf[INDEX_ATT_2_1G_DL1]){
+#ifdef DEBUG_PRINT
+        printf("\r\nLINE : %d  \r\n",__LINE__);    
+#endif /* DEBUG_PRINT */
+        BDA4601_atten_ctrl(BDA4601_2_1G_DL1,(data_buf[INDEX_ATT_2_1G_DL1]));
+        Prev_data[INDEX_ATT_2_1G_DL1] = data_buf[INDEX_ATT_2_1G_DL1];
+
+    }
+    if(Prev_data[INDEX_ATT_2_1G_DL2] != data_buf[INDEX_ATT_2_1G_DL2]){
+#ifdef DEBUG_PRINT
+        printf("\r\nLINE : %d  \r\n",__LINE__);    
+#endif /* DEBUG_PRINT */
+        BDA4601_atten_ctrl(BDA4601_2_1G_DL2,(data_buf[INDEX_ATT_2_1G_DL2]));
+        Prev_data[INDEX_ATT_2_1G_DL2] = data_buf[INDEX_ATT_2_1G_DL2];
+
+    }
+    if(Prev_data[INDEX_ATT_2_1G_UL1] != data_buf[INDEX_ATT_2_1G_UL1]){
+#ifdef DEBUG_PRINT
+        printf("\r\nLINE : %d  \r\n",__LINE__);    
+#endif /* DEBUG_PRINT */
+        BDA4601_atten_ctrl(BDA4601_2_1G_UL1,(data_buf[INDEX_ATT_2_1G_UL1]));
+        Prev_data[INDEX_ATT_2_1G_UL1] = data_buf[INDEX_ATT_2_1G_UL1];
+
+    }
+    if(Prev_data[INDEX_ATT_2_1G_UL2] != data_buf[INDEX_ATT_2_1G_UL2]){
+        BDA4601_atten_ctrl(BDA4601_2_1G_UL2,(data_buf[INDEX_ATT_2_1G_UL2]));
+        Prev_data[INDEX_ATT_2_1G_UL2] = data_buf[INDEX_ATT_2_1G_UL2];
+
+    }
+    if(Prev_data[INDEX_ATT_2_1G_UL3] != data_buf[INDEX_ATT_2_1G_UL3]){
+        BDA4601_atten_ctrl(BDA4601_2_1G_UL3,(data_buf[INDEX_ATT_2_1G_UL3]));
+        Prev_data[INDEX_ATT_2_1G_UL3] = data_buf[INDEX_ATT_2_1G_UL3];
+
+    }
+    if(Prev_data[INDEX_ATT_2_1G_UL4] != data_buf[INDEX_ATT_2_1G_UL4]){
+        BDA4601_atten_ctrl(BDA4601_2_1G_UL4,(data_buf[INDEX_ATT_2_1G_UL4]));
+        Prev_data[INDEX_ATT_2_1G_UL4] = data_buf[INDEX_ATT_2_1G_UL4];
+    }
+    if(   (Prev_data[INDEX_ATT_3_5G_DL] != data_buf[INDEX_ATT_3_5G_DL])
+        ||(Prev_data[INDEX_ATT_3_5G_UL] != data_buf[INDEX_ATT_3_5G_UL])
+        ||(Prev_data[INDEX_ATT_3_5G_COM1] != data_buf[INDEX_ATT_3_5G_COM1])
+        ||(Prev_data[INDEX_ATT_3_5G_COM2] != data_buf[INDEX_ATT_3_5G_COM2])
+        ||(Prev_data[INDEX_ATT_3_5G_COM3] != data_buf[INDEX_ATT_3_5G_COM3])
+    ){
+        ALL_ATT_3_5G.data0 = Prev_data[INDEX_ATT_3_5G_DL]   = data_buf[INDEX_ATT_3_5G_DL];
+        ALL_ATT_3_5G.data1 = Prev_data[INDEX_ATT_3_5G_UL]   = data_buf[INDEX_ATT_3_5G_UL];
+        ALL_ATT_3_5G.data2 = Prev_data[INDEX_ATT_3_5G_COM1] = data_buf[INDEX_ATT_3_5G_COM1];
+        ALL_ATT_3_5G.data3 = Prev_data[INDEX_ATT_3_5G_COM2] = data_buf[INDEX_ATT_3_5G_COM2];
+        ALL_ATT_3_5G.data4 = Prev_data[INDEX_ATT_3_5G_COM3] = data_buf[INDEX_ATT_3_5G_COM3];
+        PE43711_ALL_atten_ctrl(ALL_ATT_3_5G);
+    }
+    if((Prev_data[INDEX_PLL_1_8G_DL_H] != data_buf[INDEX_PLL_1_8G_DL_H])
+        && (Prev_data[INDEX_PLL_1_8G_DL_L] != data_buf[INDEX_PLL_1_8G_DL_L])
+    ){
+        Prev_data[INDEX_PLL_1_8G_DL_H] = data_buf[INDEX_PLL_1_8G_DL_H];
+        Prev_data[INDEX_PLL_1_8G_DL_L] = data_buf[INDEX_PLL_1_8G_DL_L];
+        temp_val = (data_buf[INDEX_PLL_1_8G_DL_H] << 8) | (data_buf[INDEX_PLL_1_8G_DL_L]);
+        ADF4113_Module_Ctrl(ADF4113_1_8G_DL,0x410,halSynSetFreq((temp_val * 1000000) / 10 ),0x9F8092);
+    }
+    if((Prev_data[INDEX_PLL_1_8G_UL_H] != data_buf[INDEX_PLL_1_8G_UL_H])
+        && (Prev_data[INDEX_PLL_1_8G_UL_L] != data_buf[INDEX_PLL_1_8G_UL_L])){
+        temp_val = (data_buf[INDEX_PLL_1_8G_UL_H] << 8) | (data_buf[INDEX_PLL_1_8G_UL_L]);
+        Prev_data[INDEX_PLL_1_8G_UL_H] = data_buf[INDEX_PLL_1_8G_UL_H];
+        Prev_data[INDEX_PLL_1_8G_UL_L] = data_buf[INDEX_PLL_1_8G_UL_L];
+        ADF4113_Module_Ctrl(ADF4113_1_8G_UL,0x410,halSynSetFreq((temp_val * 1000000) / 10),0x9F8092);
+    }
+    if((Prev_data[INDEX_PLL_2_1G_DL_H] != data_buf[INDEX_PLL_2_1G_DL_H])
+        && (Prev_data[INDEX_PLL_2_1G_DL_L] != data_buf[INDEX_PLL_2_1G_DL_L])){
+        temp_val = ((data_buf[INDEX_PLL_2_1G_DL_H] << 8) | (data_buf[INDEX_PLL_2_1G_DL_L]));
+        Prev_data[INDEX_PLL_2_1G_DL_H] = data_buf[INDEX_PLL_2_1G_DL_H];
+        Prev_data[INDEX_PLL_2_1G_DL_L] = data_buf[INDEX_PLL_2_1G_DL_L];        
+        ADF4113_Module_Ctrl(ADF4113_2_1G_DL,0x410,halSynSetFreq((temp_val * 1000000) / 10),0x9F8092);
+    }
+    if((Prev_data[INDEX_PLL_2_1G_UL_H] != data_buf[INDEX_PLL_2_1G_UL_H])
+        && (Prev_data[INDEX_PLL_2_1G_UL_L] != data_buf[INDEX_PLL_2_1G_UL_L])){
+        Prev_data[INDEX_PLL_2_1G_UL_H] = data_buf[INDEX_PLL_2_1G_UL_H];
+        Prev_data[INDEX_PLL_2_1G_UL_L] = data_buf[INDEX_PLL_2_1G_UL_L];          
+        temp_val = (data_buf[INDEX_PLL_2_1G_UL_H] << 8) | (data_buf[INDEX_PLL_2_1G_UL_L]);
+        ADF4113_Module_Ctrl(ADF4113_2_1G_UL,0x410,halSynSetFreq((temp_val * 1000000) / 10),0x9F8092);
+
+    }
+    if((Prev_data[INDEX_PLL_3_5G_DL_H] != data_buf[INDEX_PLL_3_5G_DL_H])
+        && (Prev_data[INDEX_PLL_3_5G_DL_L] != data_buf[INDEX_PLL_3_5G_DL_L])){
+        Prev_data[INDEX_PLL_3_5G_DL_H] = data_buf[INDEX_PLL_3_5G_DL_H];
+        Prev_data[INDEX_PLL_3_5G_DL_L] = data_buf[INDEX_PLL_3_5G_DL_L];
+        temp_val = (data_buf[INDEX_PLL_3_5G_DL_H] << 8) | (data_buf[INDEX_PLL_3_5G_DL_L]);
+        temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
+        ADF4153_Module_Ctrl(Pll_3_5_L,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
+    }
+    if((Prev_data[INDEX_PLL_3_5G_UL_H] != data_buf[INDEX_PLL_3_5G_UL_H])
+        && (Prev_data[INDEX_PLL_3_5G_UL_L] != data_buf[INDEX_PLL_3_5G_UL_L])){
+        Prev_data[INDEX_PLL_3_5G_UL_H] = data_buf[INDEX_PLL_3_5G_UL_H];
+        Prev_data[INDEX_PLL_3_5G_UL_L] = data_buf[INDEX_PLL_3_5G_UL_L];
+        temp_val = (data_buf[INDEX_PLL_3_5G_UL_H] << 8) | (data_buf[INDEX_PLL_3_5G_UL_L]);
+        temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
+        ADF4153_Module_Ctrl(Pll_3_5_H,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
+
+    }
+    if(Prev_data[INDEX_PLL_LD_6_BIT] != data_buf[INDEX_PLL_LD_6_BIT]){
+
+    }
+#if 0 // PYJ.2019.07.28_BEGIN -- 
+    if(Prev_data[INDEX_DET_1_8G_DL_IN_H] != data_buf[INDEX_DET_1_8G_DL_IN_H]){
+
+    }
+    if(Prev_data[INDEX_DET_1_8G_DL_IN_L] != data_buf[INDEX_DET_1_8G_DL_IN_L]){
+
+    }
+    if(Prev_data[INDEX_DET_1_8G_DL_OUT_H] != data_buf[INDEX_DET_1_8G_DL_OUT_H]){
+
+    }
+    if(Prev_data[INDEX_DET_1_8G_DL_OUT_L] != data_buf[INDEX_DET_1_8G_DL_OUT_L]){
+
+    }
+    if(Prev_data[INDEX_DET_1_8G_UL_IN_H] != data_buf[INDEX_DET_1_8G_UL_IN_H]){
+
+    }
+    if(Prev_data[INDEX_DET_1_8G_UL_IN_L] != data_buf[INDEX_DET_1_8G_UL_IN_L]){
+
+    }
+    if(Prev_data[INDEX_DET_1_8G_UL_OUT_H] != data_buf[INDEX_DET_1_8G_UL_OUT_H]){
+
+    }
+    if(Prev_data[INDEX_DET_1_8G_UL_OUT_L] != data_buf[INDEX_DET_1_8G_UL_OUT_L]){
+
+    }
+    if(Prev_data[INDEX_DET_2_1G_DL_IN_H] != data_buf[INDEX_DET_2_1G_DL_IN_H]){
+
+    }
+    if(Prev_data[INDEX_DET_2_1G_DL_IN_L] != data_buf[INDEX_DET_2_1G_DL_IN_L]){
+
+    }
+    if(Prev_data[INDEX_DET_2_1G_DL_OUT_H] != data_buf[INDEX_DET_2_1G_DL_OUT_H]){
+
+    }
+    if(Prev_data[INDEX_DET_2_1G_DL_OUT_L] != data_buf[INDEX_DET_2_1G_DL_OUT_L]){
+
+    }
+    if(Prev_data[INDEX_DET_2_1G_UL_IN_H] != data_buf[INDEX_DET_2_1G_UL_IN_H]){
+
+    }
+    if(Prev_data[INDEX_DET_2_1G_UL_IN_L] != data_buf[INDEX_DET_2_1G_UL_IN_L]){
+
+    }
+
+    if(Prev_data[INDEX_DET_2_1G_UL_OUT_H] != data_buf[INDEX_DET_2_1G_UL_OUT_H]){
+
+    }
+    if(Prev_data[INDEX_DET_2_1G_UL_OUT_L] != data_buf[INDEX_DET_2_1G_UL_OUT_L]){
+
+    }
+    if(Prev_data[INDEX_DET_3_5G_DL_IN_H] != data_buf[INDEX_DET_3_5G_DL_IN_H]){
+
+    }
+    if(Prev_data[INDEX_DET_3_5G_DL_IN_L] != data_buf[INDEX_DET_3_5G_DL_IN_L]){
+
+    }
+    if(Prev_data[INDEX_DET_3_5G_DL_OUT_L] != data_buf[INDEX_DET_3_5G_DL_OUT_L]){
+
+    }
+    if(Prev_data[INDEX_DET_3_5G_DL_OUT_H] != data_buf[INDEX_DET_3_5G_DL_OUT_H]){
+
+    }
+    if(Prev_data[INDEX_DET_3_5G_UL_IN_H] != data_buf[INDEX_DET_3_5G_UL_IN_H]){
+
+    }
+    if(Prev_data[INDEX_DET_3_5G_UL_IN_L] != data_buf[INDEX_DET_3_5G_UL_IN_L]){
+
+    }
+
+    if(Prev_data[INDEX_DET_3_5G_UL_OUT_H] != data_buf[INDEX_DET_3_5G_UL_OUT_H]){
+
+    }
+    if(Prev_data[INDEX_DET_3_5G_UL_OUT_L] != data_buf[INDEX_DET_3_5G_UL_OUT_L]){
+
+    }
+    if(Prev_data[INDEX_RFU_TEMP_H] != data_buf[INDEX_RFU_TEMP_H]){
+
+    }
+    if(Prev_data[INDEX_RFU_TEMP_L] != data_buf[INDEX_RFU_TEMP_L]){
+
+    }
+    if(Prev_data[INDEX__28V_DET_H] != data_buf[INDEX__28V_DET_H]){
+
+    }
+    if(Prev_data[INDEX__28V_DET_L] != data_buf[INDEX__28V_DET_L]){
+
+    }
+#endif // PYJ.2019.07.28_END -- 
+    if(Prev_data[INDEX_ALARM_AC] != data_buf[INDEX_ALARM_AC]){
+
+    }
+    if(Prev_data[INDEX_ALARM_DC] != data_buf[INDEX_ALARM_DC]){
+
+    }
+    if(Prev_data[INDEX_PATH_EN_1_8G_DL] != data_buf[INDEX_PATH_EN_1_8G_DL]){
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_1_8G_DL,data_buf[INDEX_PATH_EN_1_8G_DL]);
+        Prev_data[INDEX_PATH_EN_1_8G_DL] = data_buf[INDEX_PATH_EN_1_8G_DL];
+    }
+    if(Prev_data[INDEX_PATH_EN_1_8G_UL] != data_buf[INDEX_PATH_EN_1_8G_UL]){
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_1_8G_UL,data_buf[INDEX_PATH_EN_1_8G_UL]);
+        Prev_data[INDEX_PATH_EN_1_8G_UL] = data_buf[INDEX_PATH_EN_1_8G_UL];
+
+    }
+
+    if(Prev_data[INDEX_PATH_EN_2_1G_DL] != data_buf[INDEX_PATH_EN_2_1G_DL]){
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_2_1G_DL,data_buf[INDEX_PATH_EN_2_1G_DL]);
+        Prev_data[INDEX_PATH_EN_2_1G_DL] = data_buf[INDEX_PATH_EN_2_1G_DL];
+
+    }
+    if(Prev_data[INDEX_PATH_EN_2_1G_UL] != data_buf[INDEX_PATH_EN_2_1G_UL]){
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_2_1G_UL,data_buf[INDEX_PATH_EN_2_1G_UL]);
+        Prev_data[INDEX_PATH_EN_2_1G_UL] = data_buf[INDEX_PATH_EN_2_1G_UL];
+
+    }
+    if(Prev_data[INDEX_PATH_EN_3_5G_L] != data_buf[INDEX_PATH_EN_3_5G_L]){
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_L,data_buf[INDEX_PATH_EN_3_5G_L]);
+        Prev_data[INDEX_PATH_EN_3_5G_L] = data_buf[INDEX_PATH_EN_3_5G_L];
+
+    }
+    if(Prev_data[INDEX_PATH_EN_3_5G_H] != data_buf[INDEX_PATH_EN_3_5G_H]){
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_H,data_buf[INDEX_PATH_EN_3_5G_H]);
+        Prev_data[INDEX_PATH_EN_3_5G_H] = data_buf[INDEX_PATH_EN_3_5G_H];
+
+    }
+    if(Prev_data[INDEX_PATH_EN_3_5G_DL] != data_buf[INDEX_PATH_EN_3_5G_DL]){
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_DL,data_buf[INDEX_PATH_EN_3_5G_DL]);
+        Prev_data[INDEX_PATH_EN_3_5G_DL] = data_buf[INDEX_PATH_EN_3_5G_DL];
+
+    }
+    if(Prev_data[INDEX_PATH_EN_3_5G_UL] != data_buf[INDEX_PATH_EN_3_5G_UL]){
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_UL,data_buf[INDEX_PATH_EN_3_5G_UL]);
+        Prev_data[INDEX_PATH_EN_3_5G_UL] = data_buf[INDEX_PATH_EN_3_5G_UL];
+
+    }
+    if(Prev_data[INDEX_PLL_ON_OFF_3_5G_H] != data_buf[INDEX_PLL_ON_OFF_3_5G_H]){
+        Power_ON_OFF_Ctrl(INDEX_PLL_ON_OFF_3_5G_H,data_buf[INDEX_PLL_ON_OFF_3_5G_H]);
+        Prev_data[INDEX_PLL_ON_OFF_3_5G_H] = data_buf[INDEX_PLL_ON_OFF_3_5G_H];
+        HAL_Delay(10);
+        printf("POWER : %d \r\n",Prev_data[INDEX_PLL_ON_OFF_3_5G_H]);
+        if(data_buf[INDEX_PLL_ON_OFF_3_5G_H]){
+            printf("PLL CTRL START !! \r\n");
+//            ADF4153_Init();
+            temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
+            ADF4153_Module_Ctrl(Pll_3_5_H,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
+        }
+    }
+    if(Prev_data[INDEX_PLL_ON_OFF_3_5G_L] != data_buf[INDEX_PLL_ON_OFF_3_5G_L]){
+        Power_ON_OFF_Ctrl(INDEX_PLL_ON_OFF_3_5G_L,data_buf[INDEX_PLL_ON_OFF_3_5G_L]);
+        Prev_data[INDEX_PLL_ON_OFF_3_5G_L] = data_buf[INDEX_PLL_ON_OFF_3_5G_L];
+        HAL_Delay(10);
+        printf("POWER : %d \r\n",Prev_data[INDEX_PLL_ON_OFF_3_5G_L]);        
+        if(data_buf[INDEX_PLL_ON_OFF_3_5G_L]){
+            printf("PLL CTRL START !! \r\n");
+            temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);            
+            ADF4153_Module_Ctrl(Pll_3_5_L,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
+        }
+    }
+
+    if(Prev_data[INDEX_T_SYNC_DL] != data_buf[INDEX_T_SYNC_DL]){
+        Prev_data[INDEX_T_SYNC_DL] = data_buf[INDEX_T_SYNC_DL];
+        Power_ON_OFF_Ctrl(INDEX_T_SYNC_DL,data_buf[INDEX_T_SYNC_DL]);
+    }
+    if(Prev_data[INDEX__T_SYNC_DL] != data_buf[INDEX__T_SYNC_DL]){
+        Prev_data[INDEX__T_SYNC_DL] = data_buf[INDEX__T_SYNC_DL];
+        Power_ON_OFF_Ctrl(INDEX__T_SYNC_DL,data_buf[INDEX__T_SYNC_DL]);
+    }
+    if(Prev_data[INDEX_T_SYNC_UL] != data_buf[INDEX_T_SYNC_UL]){
+        Prev_data[INDEX_T_SYNC_UL] = data_buf[INDEX_T_SYNC_UL];
+        Power_ON_OFF_Ctrl(INDEX_T_SYNC_UL,data_buf[INDEX_T_SYNC_UL]);
+    }
+    if(Prev_data[INDEX__T_SYNC_UL] != data_buf[INDEX__T_SYNC_UL]){
+        Prev_data[INDEX__T_SYNC_UL] = data_buf[INDEX__T_SYNC_UL];
+        Power_ON_OFF_Ctrl(INDEX__T_SYNC_UL,data_buf[INDEX__T_SYNC_UL]);
+    }
+
+
+    if((Prev_data[INDEX_DAC_VCtrl_A_H] != data_buf[INDEX_DAC_VCtrl_A_H])
+        ||(Prev_data[INDEX_DAC_VCtrl_A_L] != data_buf[INDEX_DAC_VCtrl_A_L])){
+        ADC_Modify = 1;
+        Prev_data[INDEX_DAC_VCtrl_A_H] = data_buf[INDEX_DAC_VCtrl_A_H];
+        Prev_data[INDEX_DAC_VCtrl_A_L] = data_buf[INDEX_DAC_VCtrl_A_L];
+    }
+    if((Prev_data[INDEX_DAC_VCtrl_B_H] != data_buf[INDEX_DAC_VCtrl_B_H])
+        ||(Prev_data[INDEX_DAC_VCtrl_B_L] != data_buf[INDEX_DAC_VCtrl_B_L])){
+        ADC_Modify = 1;
+        
+        Prev_data[INDEX_DAC_VCtrl_B_H] = data_buf[INDEX_DAC_VCtrl_B_H];
+        Prev_data[INDEX_DAC_VCtrl_B_L] = data_buf[INDEX_DAC_VCtrl_B_L];        
+    }    
+    if((Prev_data[INDEX_DAC_VCtrl_C_H] != data_buf[INDEX_DAC_VCtrl_C_H])
+        ||(Prev_data[INDEX_DAC_VCtrl_C_L] != data_buf[INDEX_DAC_VCtrl_C_L])){
+        ADC_Modify = 1;
+        printf("Prev_data[INDEX_DAC_VCtrl_C_H] : %x \r\n",Prev_data[INDEX_DAC_VCtrl_C_H]);
+        printf("Prev_data[INDEX_DAC_VCtrl_C_L] : %x \r\n",Prev_data[INDEX_DAC_VCtrl_C_L]);
+
+        Prev_data[INDEX_DAC_VCtrl_C_H] = data_buf[INDEX_DAC_VCtrl_C_H];
+        Prev_data[INDEX_DAC_VCtrl_C_L] = data_buf[INDEX_DAC_VCtrl_C_L];        
+    }
+    if((Prev_data[INDEX_DAC_VCtrl_D_H] != data_buf[INDEX_DAC_VCtrl_D_H])
+        ||(Prev_data[INDEX_DAC_VCtrl_D_L] != data_buf[INDEX_DAC_VCtrl_D_L])){
+        ADC_Modify = 1;
+        Prev_data[INDEX_DAC_VCtrl_D_H] = data_buf[INDEX_DAC_VCtrl_D_H];
+        Prev_data[INDEX_DAC_VCtrl_D_L] = data_buf[INDEX_DAC_VCtrl_D_L];
+    }
+    if((Prev_data[INDEX_DAC_VCtrl_E_H] != data_buf[INDEX_DAC_VCtrl_E_H])
+        ||(Prev_data[INDEX_DAC_VCtrl_E_L] != data_buf[INDEX_DAC_VCtrl_E_L])){
+        ADC_Modify = 1;
+
+        Prev_data[INDEX_DAC_VCtrl_E_H] = data_buf[INDEX_DAC_VCtrl_E_H];
+        Prev_data[INDEX_DAC_VCtrl_E_L] = data_buf[INDEX_DAC_VCtrl_E_L];        
+    }
+    if((Prev_data[INDEX_DAC_VCtrl_F_H] != data_buf[INDEX_DAC_VCtrl_F_H])
+        ||(Prev_data[INDEX_DAC_VCtrl_F_L] != data_buf[INDEX_DAC_VCtrl_F_L])){
+        ADC_Modify = 1;
+        Prev_data[INDEX_DAC_VCtrl_F_H] = data_buf[INDEX_DAC_VCtrl_F_H];
+        Prev_data[INDEX_DAC_VCtrl_F_L] = data_buf[INDEX_DAC_VCtrl_F_L];        
+    }
+    if((Prev_data[INDEX_DAC_VCtrl_G_H] != data_buf[INDEX_DAC_VCtrl_G_H])
+        ||(Prev_data[INDEX_DAC_VCtrl_G_L] != data_buf[INDEX_DAC_VCtrl_G_L])){
+        ADC_Modify = 1;
+        Prev_data[INDEX_DAC_VCtrl_G_H] = data_buf[INDEX_DAC_VCtrl_G_H];
+        Prev_data[INDEX_DAC_VCtrl_G_L] = data_buf[INDEX_DAC_VCtrl_G_L];        
+    }    
+    if((Prev_data[INDEX_DAC_VCtrl_H_H] != data_buf[INDEX_DAC_VCtrl_H_H])
+        ||(Prev_data[INDEX_DAC_VCtrl_H_L] != data_buf[INDEX_DAC_VCtrl_H_L])){
+        ADC_Modify = 1;
+        Prev_data[INDEX_DAC_VCtrl_H_H] = data_buf[INDEX_DAC_VCtrl_H_H];
+        Prev_data[INDEX_DAC_VCtrl_H_L] = data_buf[INDEX_DAC_VCtrl_H_L];        
+    }
+    if(ADC_Modify){
+//        SubmitDAC(0xF000);
+//        HAL_Delay(1);
+//        SubmitDAC(0x800C);
+//        SubmitDAC(0x2FFF );
+//        SubmitDAC(0xA000);
+        SubmitDAC((Prev_data[INDEX_DAC_VCtrl_A_H] << 8 | Prev_data[INDEX_DAC_VCtrl_A_L]));    
+        SubmitDAC((Prev_data[INDEX_DAC_VCtrl_B_H] << 8 | Prev_data[INDEX_DAC_VCtrl_B_L]));    
+        SubmitDAC((Prev_data[INDEX_DAC_VCtrl_C_H] << 8 | Prev_data[INDEX_DAC_VCtrl_C_L]));
+        SubmitDAC((Prev_data[INDEX_DAC_VCtrl_D_H] << 8 | Prev_data[INDEX_DAC_VCtrl_D_L]));
+        SubmitDAC((Prev_data[INDEX_DAC_VCtrl_E_H] << 8 | Prev_data[INDEX_DAC_VCtrl_E_L]));    
+        SubmitDAC((Prev_data[INDEX_DAC_VCtrl_F_H] << 8 | Prev_data[INDEX_DAC_VCtrl_F_L]));
+        SubmitDAC((Prev_data[INDEX_DAC_VCtrl_G_H] << 8 | Prev_data[INDEX_DAC_VCtrl_G_L]));
+        SubmitDAC((Prev_data[INDEX_DAC_VCtrl_H_H] << 8 | Prev_data[INDEX_DAC_VCtrl_H_L]));
+    }
+    
+}
+
+
+bool RF_Ctrl_Main(uint8_t* data_buf){
+    bool ret = false;
+    Bluecell_Prot_t type = data_buf[Type];
+    ret = RF_Data_Check(&data_buf[Header]); /* ERROR CHECK */
+    if(ret == false){
+        HAL_UART_Transmit(&huart1,&data_buf[INDEX_BLUE_HEADER],data_buf[INDEX_BLUE_LENGTH] + 2 + 1,3000); 
+        return ret;
+    }
+    
+    switch(type){
+    case TYPE_BLUECELL_RESET:
+        for(uint8_t i =0 ; i < data_buf[Length] + 6; i++)
+            printf("%02x ",data_buf[i]);
+        printf("Reset Start \r\n");
+        NVIC_SystemReset();
+        break;
+    case TYPE_BLUECELL_SET:
+#if 0 // PYJ.2019.07.31_BEGIN -- 
+    printf("TYPE_BLUECELL_SET : ");
+    for(uint8_t i =0 ; i < INDEX_BLUE_EOF + 1; i++)
+        printf("%02x ",data_buf[i]);
+#endif // PYJ.2019.07.31_END -- 
+        RF_Operate(&data_buf[Header]);
+//        ADF4153_Freq_Calc(3465500000,40000000,2,5000);
+//        ADF4153_Freq_Calc(3993450000,40000000,2,5000);
+//        halSynSetFreq(1995000000);
+//        halSynSetFreq(1600000000);
+//        halSynSetFreq(1455000000);        
+        break;
+    case TYPE_BLUECELL_GET:
+        printf("\r\nTYPE_BLUECELL_GET : \r\n");
+        RF_Status_Get();
+        break;
+    case TYPE_BLUECELL_SAVE:
+        printf("\r\nFLASH Write\r\n");
+        Bluecell_Flash_Write(&Prev_data[INDEX_BLUE_HEADER]);
+        break;
+        default:
+#ifdef DEBUG_PRINT // PYJ.2019.07.27_BEGIN --         
+            printf("Function : %s   LINE : %d    type : %d \r\n",__func__,__LINE__,type);
+#endif
+            break;
+    }
+    return ret;
+}

insight/STM32F103_ATTEN_PLL_Zig.si4project/STM32F103_ATTEN_PLL_Zig.SearchResults

@@ -1,2 +1,3 @@
----- why not? Matches (1 in 1 files) ----
-PE43711_ALL_atten_ctrl in PE43711.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :     printf("why not? \r\n");
+---- RF_Operate Matches (2 in 1 files) ----
+zig_operate.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) line 240 : void RF_Operate(uint8_t* data_buf){
+RF_Ctrl_Main in zig_operate.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :         RF_Operate(&data_buf[Header]);