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3.5G HIGH 부분 가변 할 수 있도록 변경

변경사항 3.5G  ADF4153_Freq_Calc 함수 내용 변경
unsigned long long 인식불가 로인해 uint32_t로 대체
YJ il y a 5 ans
Parent
commit
4093275c52
31 fichiers modifiés avec 16168 ajouts et 13821 suppressions
  1. BIN
      Debug/STM32F103_ATTEN_PLL_Zig.binary
  2. BIN
      Debug/STM32F103_ATTEN_PLL_Zig.elf
  3. 1851 1903
      Debug/STM32F103_ATTEN_PLL_Zig.hex
  4. 10931 11227
      Debug/STM32F103_ATTEN_PLL_Zig.list
  5. 645 674
      Debug/STM32F103_ATTEN_PLL_Zig.map
  6. BIN
      Debug/Src/adf4153.o
  7. 4 4
      Debug/Src/adf4153.su
  8. BIN
      Debug/Src/zig_operate.o
  9. 1 1
      Debug/Src/zig_operate.su
  10. 2 2
      Inc/adf4153.h
  11. 22 7
      Src/adf4153.c
  12. 6 3
      Src/zig_operate.c
  13. 78 0
      insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/adf4153(189).h
  14. 452 0
      insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/adf4153(300).c
  15. 78 0
      insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/adf4153(3306).h
  16. 443 0
      insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/adf4153(4400).c
  17. 440 0
      insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/adf4153(7026).c
  18. 449 0
      insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/adf4153(785).c
  19. 766 0
      insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/zig_operate(1884).c
  20. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/STM32F103_ATTEN_PLL_Zig.sip_xm
  21. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Device_ST_STM32F1xx_Include_stm32f103xe.h.sisc
  22. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_core_cm7.h.sisc
  23. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_gpio.h.sisc
  24. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_adf4153.h.sisc
  25. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_pll_4113.h.sisc
  26. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_zig_operate.h.sisc
  27. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_adf4153.c.sisc
  28. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_flash.c.sisc
  29. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_main.c.sisc
  30. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_pll_4113.c.sisc
  31. BIN
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_zig_operate.c.sisc

BIN
Debug/STM32F103_ATTEN_PLL_Zig.binary


BIN
Debug/STM32F103_ATTEN_PLL_Zig.elf


Fichier diff supprimé car celui-ci est trop grand
+ 1851 - 1903
Debug/STM32F103_ATTEN_PLL_Zig.hex


Fichier diff supprimé car celui-ci est trop grand
+ 10931 - 11227
Debug/STM32F103_ATTEN_PLL_Zig.list


Fichier diff supprimé car celui-ci est trop grand
+ 645 - 674
Debug/STM32F103_ATTEN_PLL_Zig.map


BIN
Debug/Src/adf4153.o


+ 4 - 4
Debug/Src/adf4153.su

@@ -3,7 +3,7 @@ adf4153.c:69:8:round_up	16	static
3 3
 adf4153.c:80:8:N_Reg_Value_Calc	8	static
4 4
 adf4153.c:83:10:N_Divider_Reg_Create	16	static
5 5
 adf4153.c:123:10:R_Divider_Reg_Create	20	static
6
-adf4153.c:168:20:ADF4153_Freq_Calc	48	static
7
-adf4153.c:243:6:ADF4153_Initialize	0	static
8
-adf4153.c:313:6:ADF4153_Module_Ctrl	56	static
9
-adf4153.c:295:6:ADF4153_Check	40	static
6
+adf4153.c:168:20:ADF4153_Freq_Calc	40	static
7
+adf4153.c:258:6:ADF4153_Initialize	0	static
8
+adf4153.c:328:6:ADF4153_Module_Ctrl	56	static
9
+adf4153.c:310:6:ADF4153_Check	40	static

BIN
Debug/Src/zig_operate.o


+ 1 - 1
Debug/Src/zig_operate.su

@@ -2,4 +2,4 @@ zig_operate.c:201:6:RF_Data_Check	8	static
2 2
 zig_operate.c:234:6:RF_Status_Get	8	static
3 3
 zig_operate.c:248:6:RF_Status_Ack	8	static
4 4
 zig_operate.c:262:6:RF_Operate	184	static
5
-zig_operate.c:716:6:RF_Ctrl_Main	16	static
5
+zig_operate.c:719:6:RF_Ctrl_Main	16	static

+ 2 - 2
Inc/adf4153.h

@@ -49,7 +49,7 @@
49 49
 
50 50
 #define ADF4153_40MHzREFIN 40000000
51 51
 #define ADF4153_61_44MHzREFIN 61440000
52
-#define ADF4153_122_88MHzREFIN (ADF4153_61_44MHzREFIN * 2)
52
+#define ADF4153_122_88MHzREFIN  (ADF4153_61_44MHzREFIN * 2)/10000
53 53
 
54 54
 
55 55
 #define ADF4153_2RCOUNTER 2
@@ -70,7 +70,7 @@ typedef struct {
70 70
 
71 71
 //void ADF4153_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2,uint32_t R3);
72 72
 void ADF4153_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2,uint32_t R3);
73
-ADF4153_R_N_Reg_st ADF4153_Freq_Calc(unsigned long long Freq,unsigned long long REFin,uint8_t R_Counter,uint32_t chspacing);
73
+ADF4153_R_N_Reg_st ADF4153_Freq_Calc(uint32_t Freq,uint32_t REFin,uint8_t R_Counter,uint32_t chspacing);
74 74
 void ADF4153_Initialize(void);
75 75
 void ADF4153_Check(void);
76 76
 

+ 22 - 7
Src/adf4153.c

@@ -49,8 +49,8 @@
49 49
 
50 50
 extern void Pol_Delay_us(volatile uint32_t microseconds);
51 51
 typedef struct _adf4153_st{
52
-    unsigned long long PFD_Value;
53
-    uint16_t MOD_Value;
52
+    double PFD_Value;
53
+    uint32_t MOD_Value;
54 54
     uint32_t FRAC_Value;
55 55
     uint16_t INT_Value;    
56 56
     double N_Value;
@@ -104,7 +104,7 @@ uint32_t N_Divider_Reg_Create(uint16_t _FRAC,uint16_t _INT,uint8_t _FASTLOCK){
104 104
 #ifdef DEBUG_PRINT
105 105
     printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);    
106 106
 #endif /* DEBUG_PRINT */
107
-    for(i = 14; i < 22; i++){
107
+    for(i = 14; i < 24; i++){
108 108
         if(_INT & 0x01)
109 109
             ret += shift_bit << i;
110 110
         _INT = _INT >> 1;
@@ -165,14 +165,26 @@ uint32_t R_Divider_Reg_Create(uint16_t _MOD,uint8_t _RCOUNTER,uint8_t _PRESCALER
165 165
     return ret;
166 166
 }
167 167
 
168
-ADF4153_R_N_Reg_st ADF4153_Freq_Calc(unsigned long long Freq,unsigned long long REFin,uint8_t R_Counter,uint32_t chspacing){
168
+ADF4153_R_N_Reg_st ADF4153_Freq_Calc(uint32_t Freq,uint32_t REFin,uint8_t R_Counter,uint32_t chspacing){
169 169
     adf4153_st temp_adf4153;
170 170
     double temp = 0;
171 171
     ADF4153_R_N_Reg_st temp_reg;
172
-    temp_adf4153.PFD_Value  =  REFin / (R_Counter * 1000);
173
-    temp_adf4153.MOD_Value  =  (temp_adf4153.PFD_Value / chspacing) * 1000;
174
-    temp_adf4153.N_Value    =  N_Reg_Value_Calc(((double)(Freq / 1000) /  (double)(temp_adf4153.PFD_Value / 1000)));
172
+    temp_adf4153.PFD_Value  =  (REFin / R_Counter)* 0.01 ;
173
+//    printf("chspacing : %d",chspacing);
174
+//    printf("(temp_adf4153.PFD_Value / chspacing) : %f",((double)(temp_adf4153.PFD_Value / chspacing)));
175
+    temp  =  ((double)(temp_adf4153.PFD_Value / chspacing));
176
+//    printf("temp : %f \r\n",temp);
177
+    temp_adf4153.MOD_Value  = temp * 1000000;
178
+//    printf("temp_adf4153.MOD_Value : %d \r\n",temp_adf4153.MOD_Value);      
179
+//    printf("Freq : %d \r\n",Freq);
180
+    temp_adf4153.N_Value    =  N_Reg_Value_Calc(((Freq * 10) /  (temp_adf4153.PFD_Value / 1000)));
181
+    temp_adf4153.N_Value    /=  1000;
182
+//    printf("temp_adf4153.N_Value : %f \r\n",temp_adf4153.N_Value);      
175 183
     temp_adf4153.INT_Value  =   temp_adf4153.N_Value ;
184
+//    printf("temp_adf4153.INT_Value : %d \r\n",temp_adf4153.INT_Value);   
185
+   /* if(Freq == 393432){
186
+      printf("temp_adf4153.PFD_Value : %f \r\ntemp_adf4153.MOD_Value : %f \r\n temp_adf4153.N_Value   : %f \r\n  temp_adf4153.INT_Value : %f \r\n",temp_adf4153.PFD_Value,temp_adf4153.MOD_Value,temp_adf4153.N_Value,temp_adf4153.INT_Value);
187
+    }    */
176 188
 #ifdef DEBUG_PRINT
177 189
     printf("\r\ntemp_adf4153.N_Value : %f  temp_adf4153.INT_Value : %f  temp_adf4153.MOD_Value : %f \r\n",temp_adf4153.N_Value,(double)temp_adf4153.INT_Value,(double)temp_adf4153.MOD_Value);
178 190
 #endif /* DEBUG_PRINT */
@@ -234,6 +246,9 @@ ADF4153_R_N_Reg_st ADF4153_Freq_Calc(unsigned long long Freq,unsigned long long
234 246
 
235 247
     printf("R0: %x  R1: %x \r\n",N_Divider_Reg_Create(temp_adf4153.FRAC_Value,temp_adf4153.INT_Value,0),R_Divider_Reg_Create(temp_adf4153.MOD_Value,R_Counter,1,0,2,0));   
236 248
 #endif /* DEBUG_PRINT */
249
+
250
+//    printf("N_reg : %08x R_reg :%x\r\n",temp_reg.N_reg,temp_reg.R_reg);
251
+
237 252
     temp_reg.N_reg = N_Divider_Reg_Create(temp_adf4153.FRAC_Value,temp_adf4153.INT_Value,0);
238 253
     temp_reg.R_reg = R_Divider_Reg_Create(temp_adf4153.MOD_Value,R_Counter,1,0,2,0);
239 254
 

+ 6 - 3
Src/zig_operate.c

@@ -423,12 +423,15 @@ void RF_Operate(uint8_t* data_buf){
423 423
                    (data_buf[INDEX_PLL_3_5G_HIGH_M] << 8)  |
424 424
                    (data_buf[INDEX_PLL_3_5G_HIGH_L]);
425 425
 #if 1 // PYJ.2019.08.12_BEGIN -- 
426
-        temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
426
+//        temp_reg = ADF4153_Freq_Calc(temp_val,ADF4153_122_88MHzREFIN,ADF4153_8RCOUNTER,ADF4153_CHANNEL_SPACING);
427
+        temp_reg = ADF4153_Freq_Calc(temp_val,ADF4153_122_88MHzREFIN,ADF4153_8RCOUNTER,ADF4153_CHANNEL_SPACING);
428
+//        printf("N_reg : %08x R_reg :%x\r\n",temp_reg.N_reg,temp_reg.R_reg);
429
+
427 430
 #else
428 431
         temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
429 432
 #endif // PYJ.2019.08.12_END -- 
430
-//        ADF4153_Module_Ctrl(Pll_3_5_H,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
431
-        ADF4153_Module_Ctrl(Pll_3_5_H,0x4006C0,0x163001,0x14C2,3);
433
+        ADF4153_Module_Ctrl(Pll_3_5_H,temp_reg.N_reg,temp_reg.R_reg,0x14C2,0x3);
434
+//        ADF4153_Module_Ctrl(Pll_3_5_H,0x4006C0,0x163001,0x14C2,3);
432 435
     }
433 436
     if(Prev_data[INDEX_PLL_LD_6_BIT] != data_buf[INDEX_PLL_LD_6_BIT]){
434 437
 

+ 78 - 0
insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/adf4153(189).h

@@ -0,0 +1,78 @@
1
+/**************************************************************************//**
2
+*   @file   adf4153.h
3
+*   @brief  Header file of adf4153 driver.
4
+*
5
+*   @author Istvan Csomortani (istvan.csomortani@analog.com)
6
+*
7
+*******************************************************************************
8
+* Copyright 2013(c) Analog Devices, Inc.
9
+*
10
+* All rights reserved.
11
+*
12
+* Redistribution and use in source and binary forms, with or without modification,
13
+* are permitted provided that the following conditions are met:
14
+*  - Redistributions of source code must retain the above copyright
15
+*    notice, this list of conditions and the following disclaimer.
16
+*  - Redistributions in binary form must reproduce the above copyright
17
+*    notice, this list of conditions and the following disclaimer in
18
+*    the documentation and/or other materials provided with the
19
+*    distribution.
20
+*  - Neither the name of Analog Devices, Inc. nor the names of its
21
+*    contributors may be used to endorse or promote products derived
22
+*    from this software without specific prior written permission.
23
+*  - The use of this software may or may not infringe the patent rights
24
+*    of one or more patent holders.  This license does not release you
25
+*    from the requirement that you obtain separate licenses from these
26
+*    patent holders to use this software.
27
+*  - Use of the software either in source or binary form, must be run
28
+*    on or directly connected to an Analog Devices Inc. component.
29
+*
30
+* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED
31
+* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY
32
+* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
33
+* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
35
+* INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
36
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
37
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
39
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40
+*
41
+******************************************************************************/
42
+#ifndef __ADF4153_H__
43
+#define __ADF4153_H__
44
+
45
+//#include "main.h"
46
+
47
+#include "main.h"
48
+#include "pll_4113.h"
49
+
50
+#define ADF4153_40MHzREFIN 40000000
51
+#define ADF4153_61_44MHzREFIN 61440000
52
+#define ADF4153_122_88MHzREFIN  12288‬
53
+
54
+
55
+#define ADF4153_2RCOUNTER 2
56
+#define ADF4153_4RCOUNTER 4
57
+#define ADF4153_8RCOUNTER 8
58
+
59
+
60
+#define ADF4153_CHANNEL_SPACING 5000
61
+
62
+
63
+typedef struct {
64
+    uint32_t R_reg;
65
+    uint32_t N_reg;
66
+}ADF4153_R_N_Reg_st;
67
+
68
+//void ADF4153_Freq_Calc(unsigned long long Freq,unsigned long long REFin,uint8_t R_Counter,uint32_t chspacing);
69
+
70
+
71
+//void ADF4153_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2,uint32_t R3);
72
+void ADF4153_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2,uint32_t R3);
73
+ADF4153_R_N_Reg_st ADF4153_Freq_Calc(unsigned long long Freq,unsigned long long REFin,uint8_t R_Counter,uint32_t chspacing);
74
+void ADF4153_Initialize(void);
75
+void ADF4153_Check(void);
76
+
77
+
78
+#endif // __ADF4153_H__

+ 452 - 0
insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/adf4153(300).c

@@ -0,0 +1,452 @@
1
+/******************************************************************************
2
+*   @file   ADF4153.c
3
+*   @brief  Implementation of ADF4153 Driver for Microblaze processor.
4
+*   @author Istvan Csomortani (istvan.csomortani@analog.com)
5
+*
6
+*******************************************************************************
7
+* Copyright 2013(c) Analog Devices, Inc.
8
+*
9
+* All rights reserved.
10
+*
11
+* Redistribution and use in source and binary forms, with or without modification,
12
+* are permitted provided that the following conditions are met:
13
+*  - Redistributions of source code must retain the above copyright
14
+*    notice, this list of conditions and the following disclaimer.
15
+*  - Redistributions in binary form must reproduce the above copyright
16
+*    notice, this list of conditions and the following disclaimer in
17
+*    the documentation and/or other materials provided with the
18
+*    distribution.
19
+*  - Neither the name of Analog Devices, Inc. nor the names of its
20
+*    contributors may be used to endorse or promote products derived
21
+*    from this software without specific prior written permission.
22
+*  - The use of this software may or may not infringe the patent rights
23
+*    of one or more patent holders.  This license does not release you
24
+*    from the requirement that you obtain separate licenses from these
25
+*    patent holders to use this software.
26
+*  - Use of the software either in source or binary form, must be run
27
+*    on or directly connected to an Analog Devices Inc. component.
28
+*
29
+* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED
30
+* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY
31
+* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
32
+* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
34
+* INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
35
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
36
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
38
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39
+*
40
+******************************************************************************/
41
+
42
+/*****************************************************************************/
43
+/****************************** Include Files ********************************/
44
+/*****************************************************************************/
45
+#include "adf4153.h"
46
+#include "zig_operate.h"
47
+#include "main.h"
48
+#include "pll_4113.h"
49
+
50
+extern void Pol_Delay_us(volatile uint32_t microseconds);
51
+typedef struct _adf4153_st{
52
+    double PFD_Value;
53
+    uint32_t MOD_Value;
54
+    uint32_t FRAC_Value;
55
+    uint16_t INT_Value;    
56
+    double N_Value;
57
+}adf4153_st;
58
+extern PLL_Setting_st Pll_3_5_H;
59
+extern PLL_Setting_st Pll_3_5_L;
60
+
61
+uint32_t pow2(uint32_t val,int32_t val2){
62
+    for(uint8_t i = 0; i < val2 - 1; i++){
63
+        val = val * val;
64
+    }
65
+
66
+    return val;
67
+}
68
+
69
+double round_up( double value, int pos )
70
+{
71
+    double temp;
72
+    temp = value * pow2( 10, pos );  // �썝�븯�뒗 �냼�닔�젏 �옄由ъ닔留뚰겮 10�쓽 �늻�듅�쓣 �븿
73
+    temp =  (int)(temp + 0.5);          // 0.5瑜� �뜑�븳�썑 踰꾨┝�븯硫� 諛섏삱由쇱씠 �맖
74
+    temp *= pow2( 10, -pos );           // �떎�떆 �썝�옒 �냼�닔�젏 �옄由ъ닔濡�
75
+
76
+    return temp;
77
+}
78
+
79
+
80
+double N_Reg_Value_Calc(double val){
81
+    return  val / 1000;
82
+}
83
+uint32_t N_Divider_Reg_Create(uint16_t _FRAC,uint16_t _INT,uint8_t _FASTLOCK){
84
+    uint32_t ret = 0;
85
+    uint32_t shift_bit = 0x01;
86
+    uint8_t control_bit = 0;
87
+    uint8_t i = 0;
88
+#ifdef DEBUG_PRINT
89
+    printf("FRAC : %d INT : %d \r\n",(int)_FRAC,_INT);
90
+#endif /* DEBUG_PRINT */
91
+    for(i = 0; i < 2; i++){
92
+        if(control_bit & 0x01)
93
+            ret += shift_bit << i;
94
+        control_bit = control_bit >> 1;
95
+    }
96
+#ifdef DEBUG_PRINT
97
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);
98
+#endif /* DEBUG_PRINT */
99
+    for(i = 2; i < 14; i++){
100
+        if(_FRAC & 0x01)
101
+            ret += shift_bit << i;
102
+        _FRAC = _FRAC >> 1;
103
+    }
104
+#ifdef DEBUG_PRINT
105
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);    
106
+#endif /* DEBUG_PRINT */
107
+    for(i = 14; i < 22; i++){
108
+        if(_INT & 0x01)
109
+            ret += shift_bit << i;
110
+        _INT = _INT >> 1;
111
+    }  
112
+#ifdef DEBUG_PRINT
113
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);    
114
+#endif /* DEBUG_PRINT */
115
+    if(_FASTLOCK & 0x01)
116
+            ret += shift_bit << i;
117
+#ifdef DEBUG_PRINT
118
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);
119
+#endif /* DEBUG_PRINT */
120
+
121
+    return ret;
122
+}
123
+uint32_t R_Divider_Reg_Create(uint16_t _MOD,uint8_t _RCOUNTER,uint8_t _PRESCALER,uint8_t _RESERVED,uint8_t _MUXOUT,uint8_t LOAD_CONTROL){
124
+    uint32_t ret = 0;
125
+    uint32_t shift_bit = 0x01;
126
+    uint8_t control_bit = 1;
127
+    uint8_t i = 0;
128
+#ifdef DEBUG_PRINT
129
+    printf("_MOD : %d INT : %d \r\n",_MOD,_RCOUNTER);
130
+#endif /* DEBUG_PRINT */
131
+
132
+#ifdef DEBUG_PRINT
133
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);
134
+#endif /* DEBUG_PRINT */
135
+    for(i = 0; i < 2; i++){
136
+        if(control_bit & 0x01)
137
+            ret += shift_bit << i;
138
+        control_bit = control_bit >> 1;
139
+    }
140
+#ifdef DEBUG_PRINT
141
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);
142
+#endif /* DEBUG_PRINT */
143
+    for(i = 2; i < 14; i++){
144
+        if(_MOD & 0x01)
145
+            ret += shift_bit << i;
146
+        _MOD = _MOD >> 1;
147
+    }
148
+    for(i = 14; i < 18; i++){
149
+        if(_RCOUNTER & 0x01)
150
+            ret += shift_bit << i;
151
+        _RCOUNTER = _RCOUNTER >> 1;
152
+    }  
153
+    if(_PRESCALER & 0x01)
154
+            ret += shift_bit << i++;
155
+    if(_RESERVED & 0x01)
156
+            ret += shift_bit << i++;
157
+    for(i = 19; i < 22; i++){
158
+        if(_MUXOUT & 0x01)
159
+            ret += shift_bit << i;
160
+        _MUXOUT = _MUXOUT >> 1;
161
+    }   
162
+    if(LOAD_CONTROL & 0x01)
163
+        ret += shift_bit << i++;
164
+
165
+    return ret;
166
+}
167
+
168
+ADF4153_R_N_Reg_st ADF4153_Freq_Calc(uint32_t Freq,uint32_t REFin,uint8_t R_Counter,uint32_t chspacing){
169
+    adf4153_st temp_adf4153;
170
+    double temp = 0;
171
+    ADF4153_R_N_Reg_st temp_reg;
172
+    temp_adf4153.PFD_Value  =  (REFin / R_Counter)* 0.01 ;
173
+//    printf("chspacing : %d",chspacing);
174
+//    printf("(temp_adf4153.PFD_Value / chspacing) : %f",((double)(temp_adf4153.PFD_Value / chspacing)));
175
+    temp  =  ((double)(temp_adf4153.PFD_Value / chspacing));
176
+//    printf("temp : %f \r\n",temp);
177
+    temp_adf4153.MOD_Value  = temp * 1000000;
178
+    printf("temp_adf4153.MOD_Value : %d \r\n",temp_adf4153.MOD_Value);      
179
+    printf("Freq : %d \r\n",Freq);
180
+    temp_adf4153.N_Value    =  N_Reg_Value_Calc(((Freq * 10) /  (temp_adf4153.PFD_Value / 1000)));
181
+    temp_adf4153.N_Value    /=  1000;
182
+    printf("temp_adf4153.N_Value : %f \r\n",temp_adf4153.N_Value);      
183
+    temp_adf4153.INT_Value  =   temp_adf4153.N_Value ;
184
+    printf("temp_adf4153.INT_Value : %d \r\n",temp_adf4153.INT_Value);   
185
+   /* if(Freq == 393432){
186
+      printf("temp_adf4153.PFD_Value : %f \r\ntemp_adf4153.MOD_Value : %f \r\n temp_adf4153.N_Value   : %f \r\n  temp_adf4153.INT_Value : %f \r\n",temp_adf4153.PFD_Value,temp_adf4153.MOD_Value,temp_adf4153.N_Value,temp_adf4153.INT_Value);
187
+    }    */
188
+#ifdef DEBUG_PRINT
189
+    printf("\r\ntemp_adf4153.N_Value : %f  temp_adf4153.INT_Value : %f  temp_adf4153.MOD_Value : %f \r\n",temp_adf4153.N_Value,(double)temp_adf4153.INT_Value,(double)temp_adf4153.MOD_Value);
190
+#endif /* DEBUG_PRINT */
191
+    temp = temp_adf4153.N_Value - (double)temp_adf4153.INT_Value;
192
+#ifdef DEBUG_PRINT
193
+    printf("\r\n temp_adf4153.N_Value - (double)temp_adf4153.INT_Value) : %f  temp * (double)temp_adf4153.MOD_Value : %f \r\n",temp,temp * (double)temp_adf4153.MOD_Value);
194
+#endif /* DEBUG_PRINT */
195
+    temp_adf4153.FRAC_Value =  (float)temp * temp_adf4153.MOD_Value;
196
+   
197
+#ifdef DEBUG_PRINT
198
+    printf("\r\ntemp_adf4153.N_Value : %x   : %f ",temp_adf4153.N_Value,((double)(Freq / 1000) /  (double)(temp_adf4153.PFD_Value / 1000)) / 1000);
199
+    printf("temp_adf4153.MOD_Value : %x   : %d \r\n",temp_adf4153.MOD_Value,temp_adf4153.MOD_Value);
200
+#endif /* DEBUG_PRINT */
201
+    uint16_t tempmod = temp_adf4153.FRAC_Value;
202
+    for(uint8_t i = 0; i < 12; i++){
203
+#ifdef DEBUG_PRINT
204
+        if(temp_adf4153.MOD_Value & 0x800){
205
+            printf("1");
206
+        }else{
207
+            printf("0");
208
+        }
209
+#endif /* DEBUG_PRINT */
210
+        tempmod = tempmod << 1;
211
+    }
212
+#ifdef DEBUG_PRINT
213
+    printf("\r\n");
214
+    printf("temp_adf4153.FRAC_Value : %x   : %d\r\n",temp_adf4153.FRAC_Value,temp_adf4153.FRAC_Value);
215
+#endif /* DEBUG_PRINT */
216
+    uint16_t tempfrac = temp_adf4153.FRAC_Value;
217
+    for(uint8_t i = 0; i < 12; i++){
218
+#ifdef DEBUG_PRINT
219
+        if(tempfrac & 0x800){
220
+            printf("1");
221
+        }else{
222
+            printf("0");
223
+        }
224
+#endif /* DEBUG_PRINT */
225
+        tempfrac = tempfrac << 1;
226
+    }
227
+#ifdef DEBUG_PRINT
228
+    printf("\r\n");    
229
+#endif /* DEBUG_PRINT */
230
+#ifdef DEBUG_PRINT
231
+    printf("temp_adf4153.INT_Value : %x   : %d\r\n",temp_adf4153.INT_Value,temp_adf4153.INT_Value); 
232
+#endif /* DEBUG_PRINT */
233
+    uint16_t tempint = temp_adf4153.INT_Value;
234
+    for(uint8_t i = 0; i < 9; i++){
235
+#ifdef DEBUG_PRINT
236
+        if(tempint & 0x100){
237
+            printf("1");
238
+        }else{
239
+            printf("0");
240
+        }
241
+#endif /* DEBUG_PRINT */
242
+        tempint = tempint << 1;
243
+    }
244
+#ifdef DEBUG_PRINT
245
+    printf("\r\n");    
246
+
247
+    printf("R0: %x  R1: %x \r\n",N_Divider_Reg_Create(temp_adf4153.FRAC_Value,temp_adf4153.INT_Value,0),R_Divider_Reg_Create(temp_adf4153.MOD_Value,R_Counter,1,0,2,0));   
248
+#endif /* DEBUG_PRINT */
249
+    temp_reg.N_reg = N_Divider_Reg_Create(temp_adf4153.FRAC_Value,temp_adf4153.INT_Value,0);
250
+    temp_reg.R_reg = R_Divider_Reg_Create(temp_adf4153.MOD_Value,R_Counter,1,0,2,0);
251
+
252
+    return temp_reg;
253
+//    R_Divider_Reg_Create(temp_adf4153.MOD_Value,R_Counter,1,0,1,0); //prescaler 1 : 8/9 0: 4/5
254
+}
255
+void ADF4153_Initialize(void){
256
+#if 0 // PYJ.2019.08.09_BEGIN -- 
257
+PLL_Setting_st Pll_test = {
258
+      PLL_CLK_3_5G_GPIO_Port,
259
+      PLL_CLK_3_5G_Pin,
260
+      PLL_DATA_3_5G_GPIO_Port,
261
+      PLL_DATA_3_5G_Pin,
262
+    PLL_EN_3_5G_L_GPIO_Port,    
263
+    PLL_EN_3_5G_L_Pin,
264
+  };
265
+PLL_Setting_st Pll_test2 = {
266
+    PLL_CLK_3_5G_GPIO_Port,
267
+    PLL_CLK_3_5G_Pin,
268
+    PLL_DATA_3_5G_GPIO_Port,
269
+    PLL_DATA_3_5G_Pin,
270
+    PLL_EN_3_5G_H_GPIO_Port,    
271
+    PLL_EN_3_5G_H_Pin,
272
+  };          
273
+    //  ADF4153_Module_Ctrl(Pll_test,0x2B44B0,0x14BE81,0x0013C2,0x000003);
274
+      ADF4153_R_N_Reg_st temp_reg;
275
+      temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
276
+      ADF4153_Module_Ctrl(Pll_test,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);      
277
+    
278
+      HAL_Delay(1);
279
+#ifdef DEBUG_PRINT
280
+        printf("\r\nPLL_EN_3_5G_H_GPIO_Port\r\n");
281
+#endif /* DEBUG_PRINT */
282
+   
283
+        temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
284
+        ADF4153_Module_Ctrl(Pll_test2,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);                  
285
+    //  ADF4153_Module_Ctrl(Pll_test2,0x313840,0x14BE81,0x13C2,0x3);
286
+      HAL_Delay(1);
287
+#endif // PYJ.2019.08.09_END -- 
288
+  if(  Flash_Save_data[INDEX_PLL_3_5G_LOW_H] == 0 
289
+    && Flash_Save_data[INDEX_PLL_3_5G_LOW_M] == 0
290
+    &&Flash_Save_data[INDEX_PLL_3_5G_LOW_L] == 0)
291
+  {
292
+    Flash_Save_data[INDEX_PLL_3_5G_LOW_H] = ((34655 & 0xFF0000) >> 16);
293
+    Flash_Save_data[INDEX_PLL_3_5G_LOW_M] = ((34655 & 0x00FF00) >> 8);
294
+    Flash_Save_data[INDEX_PLL_3_5G_LOW_L] = (34655 & 0x0000FF);
295
+  }
296
+  if(Flash_Save_data[INDEX_PLL_3_5G_HIGH_H] == 0 
297
+    && Flash_Save_data[INDEX_PLL_3_5G_HIGH_M] == 0 
298
+    && Flash_Save_data[INDEX_PLL_3_5G_HIGH_L] == 0)
299
+  {
300
+    Flash_Save_data[INDEX_PLL_3_5G_HIGH_H] = ((39345 & 0xFF0000) >> 16);
301
+    Flash_Save_data[INDEX_PLL_3_5G_HIGH_M] = ((39345 & 0x00FF00) >> 8);    
302
+    Flash_Save_data[INDEX_PLL_3_5G_HIGH_L] = (39345  & 0x0000FF);    
303
+  }
304
+
305
+
306
+}
307
+void ADF4153_Check(void){
308
+  ADF4153_R_N_Reg_st temp_reg;
309
+  if(HAL_GPIO_ReadPin(PLL_LD_3_5G_H_GPIO_Port, PLL_LD_3_5G_H_Pin) == GPIO_PIN_RESET 
310
+     && HAL_GPIO_ReadPin(PLL_ON_OFF_3_5G_H_GPIO_Port, PLL_ON_OFF_3_5G_H_Pin) == GPIO_PIN_SET){
311
+       temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
312
+       ADF4153_Module_Ctrl(Pll_3_5_H,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
313
+       HAL_Delay(1);
314
+     }
315
+     if(HAL_GPIO_ReadPin(PLL_LD_3_5G_L_GPIO_Port, PLL_LD_3_5G_L_Pin) == GPIO_PIN_RESET
316
+     && HAL_GPIO_ReadPin(PLL_ON_OFF_3_5G_L_GPIO_Port, PLL_ON_OFF_3_5G_L_Pin) == GPIO_PIN_SET){
317
+       temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
318
+       ADF4153_Module_Ctrl(Pll_3_5_L,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
319
+       HAL_Delay(1);
320
+     }
321
+
322
+
323
+}
324
+
325
+void ADF4153_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2,uint32_t R3){
326
+    R3  = R3  & 0x0007FF;
327
+    R2 = R2 & 0x00FFFF;
328
+    R1 = R1 & 0xFFFFFF;
329
+    R0 = R0 & 0xFFFFFF;
330
+//    ADF4153_Freq_Calc(3461500000,40000000,2,5000);
331
+    HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
332
+    HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
333
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
334
+#ifdef DEBUG_PRINT
335
+    printf("YJ :R0: %x  R1:  %x   R2 : %x R3 : %x ",R0,R1,R2,R3);
336
+    printf("\r\n");
337
+#endif /* DEBUG_PRINT */
338
+    /*   R3 Ctrl    */
339
+    for(int i =0; i < 11; i++){
340
+        if(R3 & 0x000400){
341
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_SET);
342
+#ifdef DEBUG_PRINT
343
+            printf("1");
344
+#endif /* DEBUG_PRINT */
345
+        }
346
+        else{
347
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
348
+#ifdef DEBUG_PRINT
349
+            printf("0");
350
+#endif /* DEBUG_PRINT */
351
+        }
352
+        Pol_Delay_us(10);
353
+        HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
354
+        Pol_Delay_us(10);
355
+        HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
356
+        R3 = (R3 << 1);
357
+    }
358
+#ifdef DEBUG_PRINT
359
+    printf("\r\n");
360
+#endif /* DEBUG_PRINT */
361
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
362
+      Pol_Delay_us(10);
363
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
364
+    
365
+    /*   R2 Ctrl    */
366
+     for(int i =0; i < 16; i++){
367
+         if(R2 & 0x008000){
368
+             HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_SET);
369
+#ifdef DEBUG_PRINT
370
+             printf("1");
371
+#endif /* DEBUG_PRINT */
372
+         }
373
+         else{
374
+             HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
375
+#ifdef DEBUG_PRINT
376
+             printf("0");
377
+#endif /* DEBUG_PRINT */
378
+         }
379
+         Pol_Delay_us(10);
380
+         HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
381
+         Pol_Delay_us(10);
382
+         HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
383
+
384
+         R2 = ((R2 << 1) & 0x00FFFF);
385
+     }
386
+#ifdef DEBUG_PRINT
387
+     printf("\r\n");
388
+#endif /* DEBUG_PRINT */
389
+     HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
390
+      Pol_Delay_us(10);
391
+     HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
392
+    
393
+     /*   R1 Ctrl    */
394
+    for(int i =0; i < 24; i++){
395
+        if(R1 & 0x800000){
396
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_SET);
397
+#ifdef DEBUG_PRINT
398
+            printf("1");
399
+#endif /* DEBUG_PRINT */
400
+        }
401
+        else{
402
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
403
+#ifdef DEBUG_PRINT
404
+            printf("0");
405
+#endif /* DEBUG_PRINT */
406
+        }
407
+        Pol_Delay_us(10);
408
+        HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
409
+        Pol_Delay_us(10);
410
+        HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
411
+
412
+        R1 = ((R1 << 1) & 0xFFFFFF);
413
+    }
414
+#ifdef DEBUG_PRINT
415
+    printf("\r\n");
416
+#endif /* DEBUG_PRINT */
417
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
418
+      Pol_Delay_us(10);
419
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
420
+
421
+
422
+        /*   R0 Ctrl    */
423
+   
424
+    for(int i =0; i < 24; i++){
425
+        if(R0 & 0x800000){
426
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_SET);
427
+#ifdef DEBUG_PRINT
428
+            printf("1");
429
+#endif /* DEBUG_PRINT */
430
+        }
431
+        else{
432
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
433
+#ifdef DEBUG_PRINT
434
+            printf("0");
435
+#endif /* DEBUG_PRINT */
436
+        }
437
+        Pol_Delay_us(10);
438
+        HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
439
+        Pol_Delay_us(10);
440
+        HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
441
+
442
+        R0 = ((R0 << 1) & 0xFFFFFF);
443
+    }
444
+#ifdef DEBUG_PRINT
445
+    printf("\r\n");
446
+#endif /* DEBUG_PRINT */
447
+    HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
448
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
449
+    Pol_Delay_us(10);
450
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
451
+
452
+}

+ 78 - 0
insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/adf4153(3306).h

@@ -0,0 +1,78 @@
1
+/**************************************************************************//**
2
+*   @file   adf4153.h
3
+*   @brief  Header file of adf4153 driver.
4
+*
5
+*   @author Istvan Csomortani (istvan.csomortani@analog.com)
6
+*
7
+*******************************************************************************
8
+* Copyright 2013(c) Analog Devices, Inc.
9
+*
10
+* All rights reserved.
11
+*
12
+* Redistribution and use in source and binary forms, with or without modification,
13
+* are permitted provided that the following conditions are met:
14
+*  - Redistributions of source code must retain the above copyright
15
+*    notice, this list of conditions and the following disclaimer.
16
+*  - Redistributions in binary form must reproduce the above copyright
17
+*    notice, this list of conditions and the following disclaimer in
18
+*    the documentation and/or other materials provided with the
19
+*    distribution.
20
+*  - Neither the name of Analog Devices, Inc. nor the names of its
21
+*    contributors may be used to endorse or promote products derived
22
+*    from this software without specific prior written permission.
23
+*  - The use of this software may or may not infringe the patent rights
24
+*    of one or more patent holders.  This license does not release you
25
+*    from the requirement that you obtain separate licenses from these
26
+*    patent holders to use this software.
27
+*  - Use of the software either in source or binary form, must be run
28
+*    on or directly connected to an Analog Devices Inc. component.
29
+*
30
+* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED
31
+* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY
32
+* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
33
+* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
35
+* INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
36
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
37
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
39
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40
+*
41
+******************************************************************************/
42
+#ifndef __ADF4153_H__
43
+#define __ADF4153_H__
44
+
45
+//#include "main.h"
46
+
47
+#include "main.h"
48
+#include "pll_4113.h"
49
+
50
+#define ADF4153_40MHzREFIN 40000000
51
+#define ADF4153_61_44MHzREFIN 61440000
52
+#define ADF4153_122_88MHzREFIN (ADF4153_61_44MHzREFIN * 2)
53
+
54
+
55
+#define ADF4153_2RCOUNTER 2
56
+#define ADF4153_4RCOUNTER 4
57
+#define ADF4153_8RCOUNTER 8
58
+
59
+
60
+#define ADF4153_CHANNEL_SPACING 5000
61
+
62
+
63
+typedef struct {
64
+    uint32_t R_reg;
65
+    uint32_t N_reg;
66
+}ADF4153_R_N_Reg_st;
67
+
68
+//void ADF4153_Freq_Calc(unsigned long long Freq,unsigned long long REFin,uint8_t R_Counter,uint32_t chspacing);
69
+
70
+
71
+//void ADF4153_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2,uint32_t R3);
72
+void ADF4153_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2,uint32_t R3);
73
+ADF4153_R_N_Reg_st ADF4153_Freq_Calc(unsigned long long Freq,unsigned long long REFin,uint8_t R_Counter,uint32_t chspacing);
74
+void ADF4153_Initialize(void);
75
+void ADF4153_Check(void);
76
+
77
+
78
+#endif // __ADF4153_H__

+ 443 - 0
insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/adf4153(4400).c

@@ -0,0 +1,443 @@
1
+/******************************************************************************
2
+*   @file   ADF4153.c
3
+*   @brief  Implementation of ADF4153 Driver for Microblaze processor.
4
+*   @author Istvan Csomortani (istvan.csomortani@analog.com)
5
+*
6
+*******************************************************************************
7
+* Copyright 2013(c) Analog Devices, Inc.
8
+*
9
+* All rights reserved.
10
+*
11
+* Redistribution and use in source and binary forms, with or without modification,
12
+* are permitted provided that the following conditions are met:
13
+*  - Redistributions of source code must retain the above copyright
14
+*    notice, this list of conditions and the following disclaimer.
15
+*  - Redistributions in binary form must reproduce the above copyright
16
+*    notice, this list of conditions and the following disclaimer in
17
+*    the documentation and/or other materials provided with the
18
+*    distribution.
19
+*  - Neither the name of Analog Devices, Inc. nor the names of its
20
+*    contributors may be used to endorse or promote products derived
21
+*    from this software without specific prior written permission.
22
+*  - The use of this software may or may not infringe the patent rights
23
+*    of one or more patent holders.  This license does not release you
24
+*    from the requirement that you obtain separate licenses from these
25
+*    patent holders to use this software.
26
+*  - Use of the software either in source or binary form, must be run
27
+*    on or directly connected to an Analog Devices Inc. component.
28
+*
29
+* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED
30
+* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY
31
+* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
32
+* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
34
+* INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
35
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
36
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
38
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39
+*
40
+******************************************************************************/
41
+
42
+/*****************************************************************************/
43
+/****************************** Include Files ********************************/
44
+/*****************************************************************************/
45
+#include "adf4153.h"
46
+#include "zig_operate.h"
47
+#include "main.h"
48
+#include "pll_4113.h"
49
+
50
+extern void Pol_Delay_us(volatile uint32_t microseconds);
51
+typedef struct _adf4153_st{
52
+    double PFD_Value;
53
+    uint16_t MOD_Value;
54
+    uint32_t FRAC_Value;
55
+    uint16_t INT_Value;    
56
+    double N_Value;
57
+}adf4153_st;
58
+extern PLL_Setting_st Pll_3_5_H;
59
+extern PLL_Setting_st Pll_3_5_L;
60
+
61
+uint32_t pow2(uint32_t val,int32_t val2){
62
+    for(uint8_t i = 0; i < val2 - 1; i++){
63
+        val = val * val;
64
+    }
65
+
66
+    return val;
67
+}
68
+
69
+double round_up( double value, int pos )
70
+{
71
+    double temp;
72
+    temp = value * pow2( 10, pos );  // �썝�븯�뒗 �냼�닔�젏 �옄由ъ닔留뚰겮 10�쓽 �늻�듅�쓣 �븿
73
+    temp =  (int)(temp + 0.5);          // 0.5瑜� �뜑�븳�썑 踰꾨┝�븯硫� 諛섏삱由쇱씠 �맖
74
+    temp *= pow2( 10, -pos );           // �떎�떆 �썝�옒 �냼�닔�젏 �옄由ъ닔濡�
75
+
76
+    return temp;
77
+}
78
+
79
+
80
+double N_Reg_Value_Calc(double val){
81
+    return  val / 1000;
82
+}
83
+uint32_t N_Divider_Reg_Create(uint16_t _FRAC,uint16_t _INT,uint8_t _FASTLOCK){
84
+    uint32_t ret = 0;
85
+    uint32_t shift_bit = 0x01;
86
+    uint8_t control_bit = 0;
87
+    uint8_t i = 0;
88
+#ifdef DEBUG_PRINT
89
+    printf("FRAC : %d INT : %d \r\n",(int)_FRAC,_INT);
90
+#endif /* DEBUG_PRINT */
91
+    for(i = 0; i < 2; i++){
92
+        if(control_bit & 0x01)
93
+            ret += shift_bit << i;
94
+        control_bit = control_bit >> 1;
95
+    }
96
+#ifdef DEBUG_PRINT
97
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);
98
+#endif /* DEBUG_PRINT */
99
+    for(i = 2; i < 14; i++){
100
+        if(_FRAC & 0x01)
101
+            ret += shift_bit << i;
102
+        _FRAC = _FRAC >> 1;
103
+    }
104
+#ifdef DEBUG_PRINT
105
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);    
106
+#endif /* DEBUG_PRINT */
107
+    for(i = 14; i < 22; i++){
108
+        if(_INT & 0x01)
109
+            ret += shift_bit << i;
110
+        _INT = _INT >> 1;
111
+    }  
112
+#ifdef DEBUG_PRINT
113
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);    
114
+#endif /* DEBUG_PRINT */
115
+    if(_FASTLOCK & 0x01)
116
+            ret += shift_bit << i;
117
+#ifdef DEBUG_PRINT
118
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);
119
+#endif /* DEBUG_PRINT */
120
+
121
+    return ret;
122
+}
123
+uint32_t R_Divider_Reg_Create(uint16_t _MOD,uint8_t _RCOUNTER,uint8_t _PRESCALER,uint8_t _RESERVED,uint8_t _MUXOUT,uint8_t LOAD_CONTROL){
124
+    uint32_t ret = 0;
125
+    uint32_t shift_bit = 0x01;
126
+    uint8_t control_bit = 1;
127
+    uint8_t i = 0;
128
+#ifdef DEBUG_PRINT
129
+    printf("_MOD : %d INT : %d \r\n",_MOD,_RCOUNTER);
130
+#endif /* DEBUG_PRINT */
131
+
132
+#ifdef DEBUG_PRINT
133
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);
134
+#endif /* DEBUG_PRINT */
135
+    for(i = 0; i < 2; i++){
136
+        if(control_bit & 0x01)
137
+            ret += shift_bit << i;
138
+        control_bit = control_bit >> 1;
139
+    }
140
+#ifdef DEBUG_PRINT
141
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);
142
+#endif /* DEBUG_PRINT */
143
+    for(i = 2; i < 14; i++){
144
+        if(_MOD & 0x01)
145
+            ret += shift_bit << i;
146
+        _MOD = _MOD >> 1;
147
+    }
148
+    for(i = 14; i < 18; i++){
149
+        if(_RCOUNTER & 0x01)
150
+            ret += shift_bit << i;
151
+        _RCOUNTER = _RCOUNTER >> 1;
152
+    }  
153
+    if(_PRESCALER & 0x01)
154
+            ret += shift_bit << i++;
155
+    if(_RESERVED & 0x01)
156
+            ret += shift_bit << i++;
157
+    for(i = 19; i < 22; i++){
158
+        if(_MUXOUT & 0x01)
159
+            ret += shift_bit << i;
160
+        _MUXOUT = _MUXOUT >> 1;
161
+    }   
162
+    if(LOAD_CONTROL & 0x01)
163
+        ret += shift_bit << i++;
164
+
165
+    return ret;
166
+}
167
+
168
+ADF4153_R_N_Reg_st ADF4153_Freq_Calc(uint32_t Freq,uint32_t REFin,uint8_t R_Counter,uint32_t chspacing){
169
+    adf4153_st temp_adf4153;
170
+    double temp = 0;
171
+    ADF4153_R_N_Reg_st temp_reg;
172
+    temp_adf4153.PFD_Value  =  REFin / (R_Counter  * 100);
173
+    temp_adf4153.MOD_Value  =  ((double)temp_adf4153.PFD_Value / chspacing) * 1000;
174
+    temp_adf4153.N_Value    =  N_Reg_Value_Calc(((double)(Freq * 10) /  (double)(temp_adf4153.PFD_Value / 1000)));
175
+    temp_adf4153.INT_Value  =   temp_adf4153.N_Value ;
176
+    if(Freq == 393432){
177
+      printf("temp_adf4153.PFD_Value : %f \r\ntemp_adf4153.MOD_Value : %f \r\n temp_adf4153.N_Value   : %f \r\n  temp_adf4153.INT_Value : %f \r\n",temp_adf4153.PFD_Value,temp_adf4153.MOD_Value,temp_adf4153.N_Value,temp_adf4153.INT_Value);
178
+    }    
179
+#ifdef DEBUG_PRINT
180
+    printf("\r\ntemp_adf4153.N_Value : %f  temp_adf4153.INT_Value : %f  temp_adf4153.MOD_Value : %f \r\n",temp_adf4153.N_Value,(double)temp_adf4153.INT_Value,(double)temp_adf4153.MOD_Value);
181
+#endif /* DEBUG_PRINT */
182
+    temp = temp_adf4153.N_Value - (double)temp_adf4153.INT_Value;
183
+#ifdef DEBUG_PRINT
184
+    printf("\r\n temp_adf4153.N_Value - (double)temp_adf4153.INT_Value) : %f  temp * (double)temp_adf4153.MOD_Value : %f \r\n",temp,temp * (double)temp_adf4153.MOD_Value);
185
+#endif /* DEBUG_PRINT */
186
+    temp_adf4153.FRAC_Value =  (float)temp * temp_adf4153.MOD_Value;
187
+   
188
+#ifdef DEBUG_PRINT
189
+    printf("\r\ntemp_adf4153.N_Value : %x   : %f ",temp_adf4153.N_Value,((double)(Freq / 1000) /  (double)(temp_adf4153.PFD_Value / 1000)) / 1000);
190
+    printf("temp_adf4153.MOD_Value : %x   : %d \r\n",temp_adf4153.MOD_Value,temp_adf4153.MOD_Value);
191
+#endif /* DEBUG_PRINT */
192
+    uint16_t tempmod = temp_adf4153.FRAC_Value;
193
+    for(uint8_t i = 0; i < 12; i++){
194
+#ifdef DEBUG_PRINT
195
+        if(temp_adf4153.MOD_Value & 0x800){
196
+            printf("1");
197
+        }else{
198
+            printf("0");
199
+        }
200
+#endif /* DEBUG_PRINT */
201
+        tempmod = tempmod << 1;
202
+    }
203
+#ifdef DEBUG_PRINT
204
+    printf("\r\n");
205
+    printf("temp_adf4153.FRAC_Value : %x   : %d\r\n",temp_adf4153.FRAC_Value,temp_adf4153.FRAC_Value);
206
+#endif /* DEBUG_PRINT */
207
+    uint16_t tempfrac = temp_adf4153.FRAC_Value;
208
+    for(uint8_t i = 0; i < 12; i++){
209
+#ifdef DEBUG_PRINT
210
+        if(tempfrac & 0x800){
211
+            printf("1");
212
+        }else{
213
+            printf("0");
214
+        }
215
+#endif /* DEBUG_PRINT */
216
+        tempfrac = tempfrac << 1;
217
+    }
218
+#ifdef DEBUG_PRINT
219
+    printf("\r\n");    
220
+#endif /* DEBUG_PRINT */
221
+#ifdef DEBUG_PRINT
222
+    printf("temp_adf4153.INT_Value : %x   : %d\r\n",temp_adf4153.INT_Value,temp_adf4153.INT_Value); 
223
+#endif /* DEBUG_PRINT */
224
+    uint16_t tempint = temp_adf4153.INT_Value;
225
+    for(uint8_t i = 0; i < 9; i++){
226
+#ifdef DEBUG_PRINT
227
+        if(tempint & 0x100){
228
+            printf("1");
229
+        }else{
230
+            printf("0");
231
+        }
232
+#endif /* DEBUG_PRINT */
233
+        tempint = tempint << 1;
234
+    }
235
+#ifdef DEBUG_PRINT
236
+    printf("\r\n");    
237
+
238
+    printf("R0: %x  R1: %x \r\n",N_Divider_Reg_Create(temp_adf4153.FRAC_Value,temp_adf4153.INT_Value,0),R_Divider_Reg_Create(temp_adf4153.MOD_Value,R_Counter,1,0,2,0));   
239
+#endif /* DEBUG_PRINT */
240
+    temp_reg.N_reg = N_Divider_Reg_Create(temp_adf4153.FRAC_Value,temp_adf4153.INT_Value,0);
241
+    temp_reg.R_reg = R_Divider_Reg_Create(temp_adf4153.MOD_Value,R_Counter,1,0,2,0);
242
+
243
+    return temp_reg;
244
+//    R_Divider_Reg_Create(temp_adf4153.MOD_Value,R_Counter,1,0,1,0); //prescaler 1 : 8/9 0: 4/5
245
+}
246
+void ADF4153_Initialize(void){
247
+#if 0 // PYJ.2019.08.09_BEGIN -- 
248
+PLL_Setting_st Pll_test = {
249
+      PLL_CLK_3_5G_GPIO_Port,
250
+      PLL_CLK_3_5G_Pin,
251
+      PLL_DATA_3_5G_GPIO_Port,
252
+      PLL_DATA_3_5G_Pin,
253
+    PLL_EN_3_5G_L_GPIO_Port,    
254
+    PLL_EN_3_5G_L_Pin,
255
+  };
256
+PLL_Setting_st Pll_test2 = {
257
+    PLL_CLK_3_5G_GPIO_Port,
258
+    PLL_CLK_3_5G_Pin,
259
+    PLL_DATA_3_5G_GPIO_Port,
260
+    PLL_DATA_3_5G_Pin,
261
+    PLL_EN_3_5G_H_GPIO_Port,    
262
+    PLL_EN_3_5G_H_Pin,
263
+  };          
264
+    //  ADF4153_Module_Ctrl(Pll_test,0x2B44B0,0x14BE81,0x0013C2,0x000003);
265
+      ADF4153_R_N_Reg_st temp_reg;
266
+      temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
267
+      ADF4153_Module_Ctrl(Pll_test,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);      
268
+    
269
+      HAL_Delay(1);
270
+#ifdef DEBUG_PRINT
271
+        printf("\r\nPLL_EN_3_5G_H_GPIO_Port\r\n");
272
+#endif /* DEBUG_PRINT */
273
+   
274
+        temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
275
+        ADF4153_Module_Ctrl(Pll_test2,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);                  
276
+    //  ADF4153_Module_Ctrl(Pll_test2,0x313840,0x14BE81,0x13C2,0x3);
277
+      HAL_Delay(1);
278
+#endif // PYJ.2019.08.09_END -- 
279
+  if(  Flash_Save_data[INDEX_PLL_3_5G_LOW_H] == 0 
280
+    && Flash_Save_data[INDEX_PLL_3_5G_LOW_M] == 0
281
+    &&Flash_Save_data[INDEX_PLL_3_5G_LOW_L] == 0)
282
+  {
283
+    Flash_Save_data[INDEX_PLL_3_5G_LOW_H] = ((34655 & 0xFF0000) >> 16);
284
+    Flash_Save_data[INDEX_PLL_3_5G_LOW_M] = ((34655 & 0x00FF00) >> 8);
285
+    Flash_Save_data[INDEX_PLL_3_5G_LOW_L] = (34655 & 0x0000FF);
286
+  }
287
+  if(Flash_Save_data[INDEX_PLL_3_5G_HIGH_H] == 0 
288
+    && Flash_Save_data[INDEX_PLL_3_5G_HIGH_M] == 0 
289
+    && Flash_Save_data[INDEX_PLL_3_5G_HIGH_L] == 0)
290
+  {
291
+    Flash_Save_data[INDEX_PLL_3_5G_HIGH_H] = ((39345 & 0xFF0000) >> 16);
292
+    Flash_Save_data[INDEX_PLL_3_5G_HIGH_M] = ((39345 & 0x00FF00) >> 8);    
293
+    Flash_Save_data[INDEX_PLL_3_5G_HIGH_L] = (39345  & 0x0000FF);    
294
+  }
295
+
296
+
297
+}
298
+void ADF4153_Check(void){
299
+  ADF4153_R_N_Reg_st temp_reg;
300
+  if(HAL_GPIO_ReadPin(PLL_LD_3_5G_H_GPIO_Port, PLL_LD_3_5G_H_Pin) == GPIO_PIN_RESET 
301
+     && HAL_GPIO_ReadPin(PLL_ON_OFF_3_5G_H_GPIO_Port, PLL_ON_OFF_3_5G_H_Pin) == GPIO_PIN_SET){
302
+       temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
303
+       ADF4153_Module_Ctrl(Pll_3_5_H,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
304
+       HAL_Delay(1);
305
+     }
306
+     if(HAL_GPIO_ReadPin(PLL_LD_3_5G_L_GPIO_Port, PLL_LD_3_5G_L_Pin) == GPIO_PIN_RESET
307
+     && HAL_GPIO_ReadPin(PLL_ON_OFF_3_5G_L_GPIO_Port, PLL_ON_OFF_3_5G_L_Pin) == GPIO_PIN_SET){
308
+       temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
309
+       ADF4153_Module_Ctrl(Pll_3_5_L,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
310
+       HAL_Delay(1);
311
+     }
312
+
313
+
314
+}
315
+
316
+void ADF4153_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2,uint32_t R3){
317
+    R3  = R3  & 0x0007FF;
318
+    R2 = R2 & 0x00FFFF;
319
+    R1 = R1 & 0xFFFFFF;
320
+    R0 = R0 & 0xFFFFFF;
321
+//    ADF4153_Freq_Calc(3461500000,40000000,2,5000);
322
+    HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
323
+    HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
324
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
325
+#ifdef DEBUG_PRINT
326
+    printf("YJ :R0: %x  R1:  %x   R2 : %x R3 : %x ",R0,R1,R2,R3);
327
+    printf("\r\n");
328
+#endif /* DEBUG_PRINT */
329
+    /*   R3 Ctrl    */
330
+    for(int i =0; i < 11; i++){
331
+        if(R3 & 0x000400){
332
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_SET);
333
+#ifdef DEBUG_PRINT
334
+            printf("1");
335
+#endif /* DEBUG_PRINT */
336
+        }
337
+        else{
338
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
339
+#ifdef DEBUG_PRINT
340
+            printf("0");
341
+#endif /* DEBUG_PRINT */
342
+        }
343
+        Pol_Delay_us(10);
344
+        HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
345
+        Pol_Delay_us(10);
346
+        HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
347
+        R3 = (R3 << 1);
348
+    }
349
+#ifdef DEBUG_PRINT
350
+    printf("\r\n");
351
+#endif /* DEBUG_PRINT */
352
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
353
+      Pol_Delay_us(10);
354
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
355
+    
356
+    /*   R2 Ctrl    */
357
+     for(int i =0; i < 16; i++){
358
+         if(R2 & 0x008000){
359
+             HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_SET);
360
+#ifdef DEBUG_PRINT
361
+             printf("1");
362
+#endif /* DEBUG_PRINT */
363
+         }
364
+         else{
365
+             HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
366
+#ifdef DEBUG_PRINT
367
+             printf("0");
368
+#endif /* DEBUG_PRINT */
369
+         }
370
+         Pol_Delay_us(10);
371
+         HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
372
+         Pol_Delay_us(10);
373
+         HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
374
+
375
+         R2 = ((R2 << 1) & 0x00FFFF);
376
+     }
377
+#ifdef DEBUG_PRINT
378
+     printf("\r\n");
379
+#endif /* DEBUG_PRINT */
380
+     HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
381
+      Pol_Delay_us(10);
382
+     HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
383
+    
384
+     /*   R1 Ctrl    */
385
+    for(int i =0; i < 24; i++){
386
+        if(R1 & 0x800000){
387
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_SET);
388
+#ifdef DEBUG_PRINT
389
+            printf("1");
390
+#endif /* DEBUG_PRINT */
391
+        }
392
+        else{
393
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
394
+#ifdef DEBUG_PRINT
395
+            printf("0");
396
+#endif /* DEBUG_PRINT */
397
+        }
398
+        Pol_Delay_us(10);
399
+        HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
400
+        Pol_Delay_us(10);
401
+        HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
402
+
403
+        R1 = ((R1 << 1) & 0xFFFFFF);
404
+    }
405
+#ifdef DEBUG_PRINT
406
+    printf("\r\n");
407
+#endif /* DEBUG_PRINT */
408
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
409
+      Pol_Delay_us(10);
410
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
411
+
412
+
413
+        /*   R0 Ctrl    */
414
+   
415
+    for(int i =0; i < 24; i++){
416
+        if(R0 & 0x800000){
417
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_SET);
418
+#ifdef DEBUG_PRINT
419
+            printf("1");
420
+#endif /* DEBUG_PRINT */
421
+        }
422
+        else{
423
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
424
+#ifdef DEBUG_PRINT
425
+            printf("0");
426
+#endif /* DEBUG_PRINT */
427
+        }
428
+        Pol_Delay_us(10);
429
+        HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
430
+        Pol_Delay_us(10);
431
+        HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
432
+
433
+        R0 = ((R0 << 1) & 0xFFFFFF);
434
+    }
435
+#ifdef DEBUG_PRINT
436
+    printf("\r\n");
437
+#endif /* DEBUG_PRINT */
438
+    HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
439
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
440
+    Pol_Delay_us(10);
441
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
442
+
443
+}

+ 440 - 0
insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/adf4153(7026).c

@@ -0,0 +1,440 @@
1
+/******************************************************************************
2
+*   @file   ADF4153.c
3
+*   @brief  Implementation of ADF4153 Driver for Microblaze processor.
4
+*   @author Istvan Csomortani (istvan.csomortani@analog.com)
5
+*
6
+*******************************************************************************
7
+* Copyright 2013(c) Analog Devices, Inc.
8
+*
9
+* All rights reserved.
10
+*
11
+* Redistribution and use in source and binary forms, with or without modification,
12
+* are permitted provided that the following conditions are met:
13
+*  - Redistributions of source code must retain the above copyright
14
+*    notice, this list of conditions and the following disclaimer.
15
+*  - Redistributions in binary form must reproduce the above copyright
16
+*    notice, this list of conditions and the following disclaimer in
17
+*    the documentation and/or other materials provided with the
18
+*    distribution.
19
+*  - Neither the name of Analog Devices, Inc. nor the names of its
20
+*    contributors may be used to endorse or promote products derived
21
+*    from this software without specific prior written permission.
22
+*  - The use of this software may or may not infringe the patent rights
23
+*    of one or more patent holders.  This license does not release you
24
+*    from the requirement that you obtain separate licenses from these
25
+*    patent holders to use this software.
26
+*  - Use of the software either in source or binary form, must be run
27
+*    on or directly connected to an Analog Devices Inc. component.
28
+*
29
+* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED
30
+* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY
31
+* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
32
+* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
34
+* INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
35
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
36
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
38
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39
+*
40
+******************************************************************************/
41
+
42
+/*****************************************************************************/
43
+/****************************** Include Files ********************************/
44
+/*****************************************************************************/
45
+#include "adf4153.h"
46
+#include "zig_operate.h"
47
+#include "main.h"
48
+#include "pll_4113.h"
49
+
50
+extern void Pol_Delay_us(volatile uint32_t microseconds);
51
+typedef struct _adf4153_st{
52
+    unsigned long long PFD_Value;
53
+    uint16_t MOD_Value;
54
+    uint32_t FRAC_Value;
55
+    uint16_t INT_Value;    
56
+    double N_Value;
57
+}adf4153_st;
58
+extern PLL_Setting_st Pll_3_5_H;
59
+extern PLL_Setting_st Pll_3_5_L;
60
+
61
+uint32_t pow2(uint32_t val,int32_t val2){
62
+    for(uint8_t i = 0; i < val2 - 1; i++){
63
+        val = val * val;
64
+    }
65
+
66
+    return val;
67
+}
68
+
69
+double round_up( double value, int pos )
70
+{
71
+    double temp;
72
+    temp = value * pow2( 10, pos );  // �썝�븯�뒗 �냼�닔�젏 �옄由ъ닔留뚰겮 10�쓽 �늻�듅�쓣 �븿
73
+    temp =  (int)(temp + 0.5);          // 0.5瑜� �뜑�븳�썑 踰꾨┝�븯硫� 諛섏삱由쇱씠 �맖
74
+    temp *= pow2( 10, -pos );           // �떎�떆 �썝�옒 �냼�닔�젏 �옄由ъ닔濡�
75
+
76
+    return temp;
77
+}
78
+
79
+
80
+double N_Reg_Value_Calc(double val){
81
+    return  val / 1000;
82
+}
83
+uint32_t N_Divider_Reg_Create(uint16_t _FRAC,uint16_t _INT,uint8_t _FASTLOCK){
84
+    uint32_t ret = 0;
85
+    uint32_t shift_bit = 0x01;
86
+    uint8_t control_bit = 0;
87
+    uint8_t i = 0;
88
+#ifdef DEBUG_PRINT
89
+    printf("FRAC : %d INT : %d \r\n",(int)_FRAC,_INT);
90
+#endif /* DEBUG_PRINT */
91
+    for(i = 0; i < 2; i++){
92
+        if(control_bit & 0x01)
93
+            ret += shift_bit << i;
94
+        control_bit = control_bit >> 1;
95
+    }
96
+#ifdef DEBUG_PRINT
97
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);
98
+#endif /* DEBUG_PRINT */
99
+    for(i = 2; i < 14; i++){
100
+        if(_FRAC & 0x01)
101
+            ret += shift_bit << i;
102
+        _FRAC = _FRAC >> 1;
103
+    }
104
+#ifdef DEBUG_PRINT
105
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);    
106
+#endif /* DEBUG_PRINT */
107
+    for(i = 14; i < 22; i++){
108
+        if(_INT & 0x01)
109
+            ret += shift_bit << i;
110
+        _INT = _INT >> 1;
111
+    }  
112
+#ifdef DEBUG_PRINT
113
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);    
114
+#endif /* DEBUG_PRINT */
115
+    if(_FASTLOCK & 0x01)
116
+            ret += shift_bit << i;
117
+#ifdef DEBUG_PRINT
118
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);
119
+#endif /* DEBUG_PRINT */
120
+
121
+    return ret;
122
+}
123
+uint32_t R_Divider_Reg_Create(uint16_t _MOD,uint8_t _RCOUNTER,uint8_t _PRESCALER,uint8_t _RESERVED,uint8_t _MUXOUT,uint8_t LOAD_CONTROL){
124
+    uint32_t ret = 0;
125
+    uint32_t shift_bit = 0x01;
126
+    uint8_t control_bit = 1;
127
+    uint8_t i = 0;
128
+#ifdef DEBUG_PRINT
129
+    printf("_MOD : %d INT : %d \r\n",_MOD,_RCOUNTER);
130
+#endif /* DEBUG_PRINT */
131
+
132
+#ifdef DEBUG_PRINT
133
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);
134
+#endif /* DEBUG_PRINT */
135
+    for(i = 0; i < 2; i++){
136
+        if(control_bit & 0x01)
137
+            ret += shift_bit << i;
138
+        control_bit = control_bit >> 1;
139
+    }
140
+#ifdef DEBUG_PRINT
141
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);
142
+#endif /* DEBUG_PRINT */
143
+    for(i = 2; i < 14; i++){
144
+        if(_MOD & 0x01)
145
+            ret += shift_bit << i;
146
+        _MOD = _MOD >> 1;
147
+    }
148
+    for(i = 14; i < 18; i++){
149
+        if(_RCOUNTER & 0x01)
150
+            ret += shift_bit << i;
151
+        _RCOUNTER = _RCOUNTER >> 1;
152
+    }  
153
+    if(_PRESCALER & 0x01)
154
+            ret += shift_bit << i++;
155
+    if(_RESERVED & 0x01)
156
+            ret += shift_bit << i++;
157
+    for(i = 19; i < 22; i++){
158
+        if(_MUXOUT & 0x01)
159
+            ret += shift_bit << i;
160
+        _MUXOUT = _MUXOUT >> 1;
161
+    }   
162
+    if(LOAD_CONTROL & 0x01)
163
+        ret += shift_bit << i++;
164
+
165
+    return ret;
166
+}
167
+
168
+ADF4153_R_N_Reg_st ADF4153_Freq_Calc(unsigned long long Freq,unsigned long long REFin,uint8_t R_Counter,uint32_t chspacing){
169
+    adf4153_st temp_adf4153;
170
+    double temp = 0;
171
+    ADF4153_R_N_Reg_st temp_reg;
172
+    temp_adf4153.PFD_Value  =  REFin / (R_Counter * 1000);
173
+    temp_adf4153.MOD_Value  =  (temp_adf4153.PFD_Value / chspacing) * 1000;
174
+    temp_adf4153.N_Value    =  N_Reg_Value_Calc(((double)(Freq / 1000) /  (double)(temp_adf4153.PFD_Value / 1000)));
175
+    temp_adf4153.INT_Value  =   temp_adf4153.N_Value ;
176
+#ifdef DEBUG_PRINT
177
+    printf("\r\ntemp_adf4153.N_Value : %f  temp_adf4153.INT_Value : %f  temp_adf4153.MOD_Value : %f \r\n",temp_adf4153.N_Value,(double)temp_adf4153.INT_Value,(double)temp_adf4153.MOD_Value);
178
+#endif /* DEBUG_PRINT */
179
+    temp = temp_adf4153.N_Value - (double)temp_adf4153.INT_Value;
180
+#ifdef DEBUG_PRINT
181
+    printf("\r\n temp_adf4153.N_Value - (double)temp_adf4153.INT_Value) : %f  temp * (double)temp_adf4153.MOD_Value : %f \r\n",temp,temp * (double)temp_adf4153.MOD_Value);
182
+#endif /* DEBUG_PRINT */
183
+    temp_adf4153.FRAC_Value =  (float)temp * temp_adf4153.MOD_Value;
184
+   
185
+#ifdef DEBUG_PRINT
186
+    printf("\r\ntemp_adf4153.N_Value : %x   : %f ",temp_adf4153.N_Value,((double)(Freq / 1000) /  (double)(temp_adf4153.PFD_Value / 1000)) / 1000);
187
+    printf("temp_adf4153.MOD_Value : %x   : %d \r\n",temp_adf4153.MOD_Value,temp_adf4153.MOD_Value);
188
+#endif /* DEBUG_PRINT */
189
+    uint16_t tempmod = temp_adf4153.FRAC_Value;
190
+    for(uint8_t i = 0; i < 12; i++){
191
+#ifdef DEBUG_PRINT
192
+        if(temp_adf4153.MOD_Value & 0x800){
193
+            printf("1");
194
+        }else{
195
+            printf("0");
196
+        }
197
+#endif /* DEBUG_PRINT */
198
+        tempmod = tempmod << 1;
199
+    }
200
+#ifdef DEBUG_PRINT
201
+    printf("\r\n");
202
+    printf("temp_adf4153.FRAC_Value : %x   : %d\r\n",temp_adf4153.FRAC_Value,temp_adf4153.FRAC_Value);
203
+#endif /* DEBUG_PRINT */
204
+    uint16_t tempfrac = temp_adf4153.FRAC_Value;
205
+    for(uint8_t i = 0; i < 12; i++){
206
+#ifdef DEBUG_PRINT
207
+        if(tempfrac & 0x800){
208
+            printf("1");
209
+        }else{
210
+            printf("0");
211
+        }
212
+#endif /* DEBUG_PRINT */
213
+        tempfrac = tempfrac << 1;
214
+    }
215
+#ifdef DEBUG_PRINT
216
+    printf("\r\n");    
217
+#endif /* DEBUG_PRINT */
218
+#ifdef DEBUG_PRINT
219
+    printf("temp_adf4153.INT_Value : %x   : %d\r\n",temp_adf4153.INT_Value,temp_adf4153.INT_Value); 
220
+#endif /* DEBUG_PRINT */
221
+    uint16_t tempint = temp_adf4153.INT_Value;
222
+    for(uint8_t i = 0; i < 9; i++){
223
+#ifdef DEBUG_PRINT
224
+        if(tempint & 0x100){
225
+            printf("1");
226
+        }else{
227
+            printf("0");
228
+        }
229
+#endif /* DEBUG_PRINT */
230
+        tempint = tempint << 1;
231
+    }
232
+#ifdef DEBUG_PRINT
233
+    printf("\r\n");    
234
+
235
+    printf("R0: %x  R1: %x \r\n",N_Divider_Reg_Create(temp_adf4153.FRAC_Value,temp_adf4153.INT_Value,0),R_Divider_Reg_Create(temp_adf4153.MOD_Value,R_Counter,1,0,2,0));   
236
+#endif /* DEBUG_PRINT */
237
+    temp_reg.N_reg = N_Divider_Reg_Create(temp_adf4153.FRAC_Value,temp_adf4153.INT_Value,0);
238
+    temp_reg.R_reg = R_Divider_Reg_Create(temp_adf4153.MOD_Value,R_Counter,1,0,2,0);
239
+
240
+    return temp_reg;
241
+//    R_Divider_Reg_Create(temp_adf4153.MOD_Value,R_Counter,1,0,1,0); //prescaler 1 : 8/9 0: 4/5
242
+}
243
+void ADF4153_Initialize(void){
244
+#if 0 // PYJ.2019.08.09_BEGIN -- 
245
+PLL_Setting_st Pll_test = {
246
+      PLL_CLK_3_5G_GPIO_Port,
247
+      PLL_CLK_3_5G_Pin,
248
+      PLL_DATA_3_5G_GPIO_Port,
249
+      PLL_DATA_3_5G_Pin,
250
+    PLL_EN_3_5G_L_GPIO_Port,    
251
+    PLL_EN_3_5G_L_Pin,
252
+  };
253
+PLL_Setting_st Pll_test2 = {
254
+    PLL_CLK_3_5G_GPIO_Port,
255
+    PLL_CLK_3_5G_Pin,
256
+    PLL_DATA_3_5G_GPIO_Port,
257
+    PLL_DATA_3_5G_Pin,
258
+    PLL_EN_3_5G_H_GPIO_Port,    
259
+    PLL_EN_3_5G_H_Pin,
260
+  };          
261
+    //  ADF4153_Module_Ctrl(Pll_test,0x2B44B0,0x14BE81,0x0013C2,0x000003);
262
+      ADF4153_R_N_Reg_st temp_reg;
263
+      temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
264
+      ADF4153_Module_Ctrl(Pll_test,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);      
265
+    
266
+      HAL_Delay(1);
267
+#ifdef DEBUG_PRINT
268
+        printf("\r\nPLL_EN_3_5G_H_GPIO_Port\r\n");
269
+#endif /* DEBUG_PRINT */
270
+   
271
+        temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
272
+        ADF4153_Module_Ctrl(Pll_test2,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);                  
273
+    //  ADF4153_Module_Ctrl(Pll_test2,0x313840,0x14BE81,0x13C2,0x3);
274
+      HAL_Delay(1);
275
+#endif // PYJ.2019.08.09_END -- 
276
+  if(  Flash_Save_data[INDEX_PLL_3_5G_LOW_H] == 0 
277
+    && Flash_Save_data[INDEX_PLL_3_5G_LOW_M] == 0
278
+    &&Flash_Save_data[INDEX_PLL_3_5G_LOW_L] == 0)
279
+  {
280
+    Flash_Save_data[INDEX_PLL_3_5G_LOW_H] = ((34655 & 0xFF0000) >> 16);
281
+    Flash_Save_data[INDEX_PLL_3_5G_LOW_M] = ((34655 & 0x00FF00) >> 8);
282
+    Flash_Save_data[INDEX_PLL_3_5G_LOW_L] = (34655 & 0x0000FF);
283
+  }
284
+  if(Flash_Save_data[INDEX_PLL_3_5G_HIGH_H] == 0 
285
+    && Flash_Save_data[INDEX_PLL_3_5G_HIGH_M] == 0 
286
+    && Flash_Save_data[INDEX_PLL_3_5G_HIGH_L] == 0)
287
+  {
288
+    Flash_Save_data[INDEX_PLL_3_5G_HIGH_H] = ((39345 & 0xFF0000) >> 16);
289
+    Flash_Save_data[INDEX_PLL_3_5G_HIGH_M] = ((39345 & 0x00FF00) >> 8);    
290
+    Flash_Save_data[INDEX_PLL_3_5G_HIGH_L] = (39345  & 0x0000FF);    
291
+  }
292
+
293
+
294
+}
295
+void ADF4153_Check(void){
296
+  ADF4153_R_N_Reg_st temp_reg;
297
+  if(HAL_GPIO_ReadPin(PLL_LD_3_5G_H_GPIO_Port, PLL_LD_3_5G_H_Pin) == GPIO_PIN_RESET 
298
+     && HAL_GPIO_ReadPin(PLL_ON_OFF_3_5G_H_GPIO_Port, PLL_ON_OFF_3_5G_H_Pin) == GPIO_PIN_SET){
299
+       temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
300
+       ADF4153_Module_Ctrl(Pll_3_5_H,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
301
+       HAL_Delay(1);
302
+     }
303
+     if(HAL_GPIO_ReadPin(PLL_LD_3_5G_L_GPIO_Port, PLL_LD_3_5G_L_Pin) == GPIO_PIN_RESET
304
+     && HAL_GPIO_ReadPin(PLL_ON_OFF_3_5G_L_GPIO_Port, PLL_ON_OFF_3_5G_L_Pin) == GPIO_PIN_SET){
305
+       temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
306
+       ADF4153_Module_Ctrl(Pll_3_5_L,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
307
+       HAL_Delay(1);
308
+     }
309
+
310
+
311
+}
312
+
313
+void ADF4153_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2,uint32_t R3){
314
+    R3  = R3  & 0x0007FF;
315
+    R2 = R2 & 0x00FFFF;
316
+    R1 = R1 & 0xFFFFFF;
317
+    R0 = R0 & 0xFFFFFF;
318
+//    ADF4153_Freq_Calc(3461500000,40000000,2,5000);
319
+    HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
320
+    HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
321
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
322
+#ifdef DEBUG_PRINT
323
+    printf("YJ :R0: %x  R1:  %x   R2 : %x R3 : %x ",R0,R1,R2,R3);
324
+    printf("\r\n");
325
+#endif /* DEBUG_PRINT */
326
+    /*   R3 Ctrl    */
327
+    for(int i =0; i < 11; i++){
328
+        if(R3 & 0x000400){
329
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_SET);
330
+#ifdef DEBUG_PRINT
331
+            printf("1");
332
+#endif /* DEBUG_PRINT */
333
+        }
334
+        else{
335
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
336
+#ifdef DEBUG_PRINT
337
+            printf("0");
338
+#endif /* DEBUG_PRINT */
339
+        }
340
+        Pol_Delay_us(10);
341
+        HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
342
+        Pol_Delay_us(10);
343
+        HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
344
+        R3 = (R3 << 1);
345
+    }
346
+#ifdef DEBUG_PRINT
347
+    printf("\r\n");
348
+#endif /* DEBUG_PRINT */
349
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
350
+      Pol_Delay_us(10);
351
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
352
+    
353
+    /*   R2 Ctrl    */
354
+     for(int i =0; i < 16; i++){
355
+         if(R2 & 0x008000){
356
+             HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_SET);
357
+#ifdef DEBUG_PRINT
358
+             printf("1");
359
+#endif /* DEBUG_PRINT */
360
+         }
361
+         else{
362
+             HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
363
+#ifdef DEBUG_PRINT
364
+             printf("0");
365
+#endif /* DEBUG_PRINT */
366
+         }
367
+         Pol_Delay_us(10);
368
+         HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
369
+         Pol_Delay_us(10);
370
+         HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
371
+
372
+         R2 = ((R2 << 1) & 0x00FFFF);
373
+     }
374
+#ifdef DEBUG_PRINT
375
+     printf("\r\n");
376
+#endif /* DEBUG_PRINT */
377
+     HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
378
+      Pol_Delay_us(10);
379
+     HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
380
+    
381
+     /*   R1 Ctrl    */
382
+    for(int i =0; i < 24; i++){
383
+        if(R1 & 0x800000){
384
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_SET);
385
+#ifdef DEBUG_PRINT
386
+            printf("1");
387
+#endif /* DEBUG_PRINT */
388
+        }
389
+        else{
390
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
391
+#ifdef DEBUG_PRINT
392
+            printf("0");
393
+#endif /* DEBUG_PRINT */
394
+        }
395
+        Pol_Delay_us(10);
396
+        HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
397
+        Pol_Delay_us(10);
398
+        HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
399
+
400
+        R1 = ((R1 << 1) & 0xFFFFFF);
401
+    }
402
+#ifdef DEBUG_PRINT
403
+    printf("\r\n");
404
+#endif /* DEBUG_PRINT */
405
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
406
+      Pol_Delay_us(10);
407
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
408
+
409
+
410
+        /*   R0 Ctrl    */
411
+   
412
+    for(int i =0; i < 24; i++){
413
+        if(R0 & 0x800000){
414
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_SET);
415
+#ifdef DEBUG_PRINT
416
+            printf("1");
417
+#endif /* DEBUG_PRINT */
418
+        }
419
+        else{
420
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
421
+#ifdef DEBUG_PRINT
422
+            printf("0");
423
+#endif /* DEBUG_PRINT */
424
+        }
425
+        Pol_Delay_us(10);
426
+        HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
427
+        Pol_Delay_us(10);
428
+        HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
429
+
430
+        R0 = ((R0 << 1) & 0xFFFFFF);
431
+    }
432
+#ifdef DEBUG_PRINT
433
+    printf("\r\n");
434
+#endif /* DEBUG_PRINT */
435
+    HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
436
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
437
+    Pol_Delay_us(10);
438
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
439
+
440
+}

+ 449 - 0
insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/adf4153(785).c

@@ -0,0 +1,449 @@
1
+/******************************************************************************
2
+*   @file   ADF4153.c
3
+*   @brief  Implementation of ADF4153 Driver for Microblaze processor.
4
+*   @author Istvan Csomortani (istvan.csomortani@analog.com)
5
+*
6
+*******************************************************************************
7
+* Copyright 2013(c) Analog Devices, Inc.
8
+*
9
+* All rights reserved.
10
+*
11
+* Redistribution and use in source and binary forms, with or without modification,
12
+* are permitted provided that the following conditions are met:
13
+*  - Redistributions of source code must retain the above copyright
14
+*    notice, this list of conditions and the following disclaimer.
15
+*  - Redistributions in binary form must reproduce the above copyright
16
+*    notice, this list of conditions and the following disclaimer in
17
+*    the documentation and/or other materials provided with the
18
+*    distribution.
19
+*  - Neither the name of Analog Devices, Inc. nor the names of its
20
+*    contributors may be used to endorse or promote products derived
21
+*    from this software without specific prior written permission.
22
+*  - The use of this software may or may not infringe the patent rights
23
+*    of one or more patent holders.  This license does not release you
24
+*    from the requirement that you obtain separate licenses from these
25
+*    patent holders to use this software.
26
+*  - Use of the software either in source or binary form, must be run
27
+*    on or directly connected to an Analog Devices Inc. component.
28
+*
29
+* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED
30
+* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY
31
+* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
32
+* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
34
+* INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
35
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
36
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
38
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39
+*
40
+******************************************************************************/
41
+
42
+/*****************************************************************************/
43
+/****************************** Include Files ********************************/
44
+/*****************************************************************************/
45
+#include "adf4153.h"
46
+#include "zig_operate.h"
47
+#include "main.h"
48
+#include "pll_4113.h"
49
+
50
+extern void Pol_Delay_us(volatile uint32_t microseconds);
51
+typedef struct _adf4153_st{
52
+    double PFD_Value;
53
+    uint32_t MOD_Value;
54
+    uint32_t FRAC_Value;
55
+    uint16_t INT_Value;    
56
+    double N_Value;
57
+}adf4153_st;
58
+extern PLL_Setting_st Pll_3_5_H;
59
+extern PLL_Setting_st Pll_3_5_L;
60
+
61
+uint32_t pow2(uint32_t val,int32_t val2){
62
+    for(uint8_t i = 0; i < val2 - 1; i++){
63
+        val = val * val;
64
+    }
65
+
66
+    return val;
67
+}
68
+
69
+double round_up( double value, int pos )
70
+{
71
+    double temp;
72
+    temp = value * pow2( 10, pos );  // �썝�븯�뒗 �냼�닔�젏 �옄由ъ닔留뚰겮 10�쓽 �늻�듅�쓣 �븿
73
+    temp =  (int)(temp + 0.5);          // 0.5瑜� �뜑�븳�썑 踰꾨┝�븯硫� 諛섏삱由쇱씠 �맖
74
+    temp *= pow2( 10, -pos );           // �떎�떆 �썝�옒 �냼�닔�젏 �옄由ъ닔濡�
75
+
76
+    return temp;
77
+}
78
+
79
+
80
+double N_Reg_Value_Calc(double val){
81
+    return  val / 1000;
82
+}
83
+uint32_t N_Divider_Reg_Create(uint16_t _FRAC,uint16_t _INT,uint8_t _FASTLOCK){
84
+    uint32_t ret = 0;
85
+    uint32_t shift_bit = 0x01;
86
+    uint8_t control_bit = 0;
87
+    uint8_t i = 0;
88
+#ifdef DEBUG_PRINT
89
+    printf("FRAC : %d INT : %d \r\n",(int)_FRAC,_INT);
90
+#endif /* DEBUG_PRINT */
91
+    for(i = 0; i < 2; i++){
92
+        if(control_bit & 0x01)
93
+            ret += shift_bit << i;
94
+        control_bit = control_bit >> 1;
95
+    }
96
+#ifdef DEBUG_PRINT
97
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);
98
+#endif /* DEBUG_PRINT */
99
+    for(i = 2; i < 14; i++){
100
+        if(_FRAC & 0x01)
101
+            ret += shift_bit << i;
102
+        _FRAC = _FRAC >> 1;
103
+    }
104
+#ifdef DEBUG_PRINT
105
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);    
106
+#endif /* DEBUG_PRINT */
107
+    for(i = 14; i < 22; i++){
108
+        if(_INT & 0x01)
109
+            ret += shift_bit << i;
110
+        _INT = _INT >> 1;
111
+    }  
112
+#ifdef DEBUG_PRINT
113
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);    
114
+#endif /* DEBUG_PRINT */
115
+    if(_FASTLOCK & 0x01)
116
+            ret += shift_bit << i;
117
+#ifdef DEBUG_PRINT
118
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);
119
+#endif /* DEBUG_PRINT */
120
+
121
+    return ret;
122
+}
123
+uint32_t R_Divider_Reg_Create(uint16_t _MOD,uint8_t _RCOUNTER,uint8_t _PRESCALER,uint8_t _RESERVED,uint8_t _MUXOUT,uint8_t LOAD_CONTROL){
124
+    uint32_t ret = 0;
125
+    uint32_t shift_bit = 0x01;
126
+    uint8_t control_bit = 1;
127
+    uint8_t i = 0;
128
+#ifdef DEBUG_PRINT
129
+    printf("_MOD : %d INT : %d \r\n",_MOD,_RCOUNTER);
130
+#endif /* DEBUG_PRINT */
131
+
132
+#ifdef DEBUG_PRINT
133
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);
134
+#endif /* DEBUG_PRINT */
135
+    for(i = 0; i < 2; i++){
136
+        if(control_bit & 0x01)
137
+            ret += shift_bit << i;
138
+        control_bit = control_bit >> 1;
139
+    }
140
+#ifdef DEBUG_PRINT
141
+    printf("\r\nLINE : %d  ret : %x\r\n",__LINE__,ret);
142
+#endif /* DEBUG_PRINT */
143
+    for(i = 2; i < 14; i++){
144
+        if(_MOD & 0x01)
145
+            ret += shift_bit << i;
146
+        _MOD = _MOD >> 1;
147
+    }
148
+    for(i = 14; i < 18; i++){
149
+        if(_RCOUNTER & 0x01)
150
+            ret += shift_bit << i;
151
+        _RCOUNTER = _RCOUNTER >> 1;
152
+    }  
153
+    if(_PRESCALER & 0x01)
154
+            ret += shift_bit << i++;
155
+    if(_RESERVED & 0x01)
156
+            ret += shift_bit << i++;
157
+    for(i = 19; i < 22; i++){
158
+        if(_MUXOUT & 0x01)
159
+            ret += shift_bit << i;
160
+        _MUXOUT = _MUXOUT >> 1;
161
+    }   
162
+    if(LOAD_CONTROL & 0x01)
163
+        ret += shift_bit << i++;
164
+
165
+    return ret;
166
+}
167
+
168
+ADF4153_R_N_Reg_st ADF4153_Freq_Calc(uint32_t Freq,uint32_t REFin,uint8_t R_Counter,uint32_t chspacing){
169
+    adf4153_st temp_adf4153;
170
+    double temp = 0;
171
+    ADF4153_R_N_Reg_st temp_reg;
172
+    temp_adf4153.PFD_Value  =  (REFin / R_Counter)* 0.01 ;
173
+    printf("chspacing : %d",chspacing);
174
+    printf("(temp_adf4153.PFD_Value / chspacing) : %f",((double)(temp_adf4153.PFD_Value / chspacing)));
175
+    
176
+    temp  =  ((double)(temp_adf4153.PFD_Value / chspacing));
177
+    printf("temp : %f \r\n",temp);
178
+    temp_adf4153.MOD_Value  = temp * 1000000;
179
+    printf("temp_adf4153.MOD_Value : %d \r\n",temp_adf4153.MOD_Value);      
180
+    temp_adf4153.N_Value    =  N_Reg_Value_Calc(((double)(Freq * 10) /  (double)(temp_adf4153.PFD_Value / 1000)));
181
+    temp_adf4153.INT_Value  =   temp_adf4153.N_Value ;
182
+    if(Freq == 393432){
183
+      printf("temp_adf4153.PFD_Value : %f \r\ntemp_adf4153.MOD_Value : %f \r\n temp_adf4153.N_Value   : %f \r\n  temp_adf4153.INT_Value : %f \r\n",temp_adf4153.PFD_Value,temp_adf4153.MOD_Value,temp_adf4153.N_Value,temp_adf4153.INT_Value);
184
+    }    
185
+#ifdef DEBUG_PRINT
186
+    printf("\r\ntemp_adf4153.N_Value : %f  temp_adf4153.INT_Value : %f  temp_adf4153.MOD_Value : %f \r\n",temp_adf4153.N_Value,(double)temp_adf4153.INT_Value,(double)temp_adf4153.MOD_Value);
187
+#endif /* DEBUG_PRINT */
188
+    temp = temp_adf4153.N_Value - (double)temp_adf4153.INT_Value;
189
+#ifdef DEBUG_PRINT
190
+    printf("\r\n temp_adf4153.N_Value - (double)temp_adf4153.INT_Value) : %f  temp * (double)temp_adf4153.MOD_Value : %f \r\n",temp,temp * (double)temp_adf4153.MOD_Value);
191
+#endif /* DEBUG_PRINT */
192
+    temp_adf4153.FRAC_Value =  (float)temp * temp_adf4153.MOD_Value;
193
+   
194
+#ifdef DEBUG_PRINT
195
+    printf("\r\ntemp_adf4153.N_Value : %x   : %f ",temp_adf4153.N_Value,((double)(Freq / 1000) /  (double)(temp_adf4153.PFD_Value / 1000)) / 1000);
196
+    printf("temp_adf4153.MOD_Value : %x   : %d \r\n",temp_adf4153.MOD_Value,temp_adf4153.MOD_Value);
197
+#endif /* DEBUG_PRINT */
198
+    uint16_t tempmod = temp_adf4153.FRAC_Value;
199
+    for(uint8_t i = 0; i < 12; i++){
200
+#ifdef DEBUG_PRINT
201
+        if(temp_adf4153.MOD_Value & 0x800){
202
+            printf("1");
203
+        }else{
204
+            printf("0");
205
+        }
206
+#endif /* DEBUG_PRINT */
207
+        tempmod = tempmod << 1;
208
+    }
209
+#ifdef DEBUG_PRINT
210
+    printf("\r\n");
211
+    printf("temp_adf4153.FRAC_Value : %x   : %d\r\n",temp_adf4153.FRAC_Value,temp_adf4153.FRAC_Value);
212
+#endif /* DEBUG_PRINT */
213
+    uint16_t tempfrac = temp_adf4153.FRAC_Value;
214
+    for(uint8_t i = 0; i < 12; i++){
215
+#ifdef DEBUG_PRINT
216
+        if(tempfrac & 0x800){
217
+            printf("1");
218
+        }else{
219
+            printf("0");
220
+        }
221
+#endif /* DEBUG_PRINT */
222
+        tempfrac = tempfrac << 1;
223
+    }
224
+#ifdef DEBUG_PRINT
225
+    printf("\r\n");    
226
+#endif /* DEBUG_PRINT */
227
+#ifdef DEBUG_PRINT
228
+    printf("temp_adf4153.INT_Value : %x   : %d\r\n",temp_adf4153.INT_Value,temp_adf4153.INT_Value); 
229
+#endif /* DEBUG_PRINT */
230
+    uint16_t tempint = temp_adf4153.INT_Value;
231
+    for(uint8_t i = 0; i < 9; i++){
232
+#ifdef DEBUG_PRINT
233
+        if(tempint & 0x100){
234
+            printf("1");
235
+        }else{
236
+            printf("0");
237
+        }
238
+#endif /* DEBUG_PRINT */
239
+        tempint = tempint << 1;
240
+    }
241
+#ifdef DEBUG_PRINT
242
+    printf("\r\n");    
243
+
244
+    printf("R0: %x  R1: %x \r\n",N_Divider_Reg_Create(temp_adf4153.FRAC_Value,temp_adf4153.INT_Value,0),R_Divider_Reg_Create(temp_adf4153.MOD_Value,R_Counter,1,0,2,0));   
245
+#endif /* DEBUG_PRINT */
246
+    temp_reg.N_reg = N_Divider_Reg_Create(temp_adf4153.FRAC_Value,temp_adf4153.INT_Value,0);
247
+    temp_reg.R_reg = R_Divider_Reg_Create(temp_adf4153.MOD_Value,R_Counter,1,0,2,0);
248
+
249
+    return temp_reg;
250
+//    R_Divider_Reg_Create(temp_adf4153.MOD_Value,R_Counter,1,0,1,0); //prescaler 1 : 8/9 0: 4/5
251
+}
252
+void ADF4153_Initialize(void){
253
+#if 0 // PYJ.2019.08.09_BEGIN -- 
254
+PLL_Setting_st Pll_test = {
255
+      PLL_CLK_3_5G_GPIO_Port,
256
+      PLL_CLK_3_5G_Pin,
257
+      PLL_DATA_3_5G_GPIO_Port,
258
+      PLL_DATA_3_5G_Pin,
259
+    PLL_EN_3_5G_L_GPIO_Port,    
260
+    PLL_EN_3_5G_L_Pin,
261
+  };
262
+PLL_Setting_st Pll_test2 = {
263
+    PLL_CLK_3_5G_GPIO_Port,
264
+    PLL_CLK_3_5G_Pin,
265
+    PLL_DATA_3_5G_GPIO_Port,
266
+    PLL_DATA_3_5G_Pin,
267
+    PLL_EN_3_5G_H_GPIO_Port,    
268
+    PLL_EN_3_5G_H_Pin,
269
+  };          
270
+    //  ADF4153_Module_Ctrl(Pll_test,0x2B44B0,0x14BE81,0x0013C2,0x000003);
271
+      ADF4153_R_N_Reg_st temp_reg;
272
+      temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
273
+      ADF4153_Module_Ctrl(Pll_test,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);      
274
+    
275
+      HAL_Delay(1);
276
+#ifdef DEBUG_PRINT
277
+        printf("\r\nPLL_EN_3_5G_H_GPIO_Port\r\n");
278
+#endif /* DEBUG_PRINT */
279
+   
280
+        temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
281
+        ADF4153_Module_Ctrl(Pll_test2,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);                  
282
+    //  ADF4153_Module_Ctrl(Pll_test2,0x313840,0x14BE81,0x13C2,0x3);
283
+      HAL_Delay(1);
284
+#endif // PYJ.2019.08.09_END -- 
285
+  if(  Flash_Save_data[INDEX_PLL_3_5G_LOW_H] == 0 
286
+    && Flash_Save_data[INDEX_PLL_3_5G_LOW_M] == 0
287
+    &&Flash_Save_data[INDEX_PLL_3_5G_LOW_L] == 0)
288
+  {
289
+    Flash_Save_data[INDEX_PLL_3_5G_LOW_H] = ((34655 & 0xFF0000) >> 16);
290
+    Flash_Save_data[INDEX_PLL_3_5G_LOW_M] = ((34655 & 0x00FF00) >> 8);
291
+    Flash_Save_data[INDEX_PLL_3_5G_LOW_L] = (34655 & 0x0000FF);
292
+  }
293
+  if(Flash_Save_data[INDEX_PLL_3_5G_HIGH_H] == 0 
294
+    && Flash_Save_data[INDEX_PLL_3_5G_HIGH_M] == 0 
295
+    && Flash_Save_data[INDEX_PLL_3_5G_HIGH_L] == 0)
296
+  {
297
+    Flash_Save_data[INDEX_PLL_3_5G_HIGH_H] = ((39345 & 0xFF0000) >> 16);
298
+    Flash_Save_data[INDEX_PLL_3_5G_HIGH_M] = ((39345 & 0x00FF00) >> 8);    
299
+    Flash_Save_data[INDEX_PLL_3_5G_HIGH_L] = (39345  & 0x0000FF);    
300
+  }
301
+
302
+
303
+}
304
+void ADF4153_Check(void){
305
+  ADF4153_R_N_Reg_st temp_reg;
306
+  if(HAL_GPIO_ReadPin(PLL_LD_3_5G_H_GPIO_Port, PLL_LD_3_5G_H_Pin) == GPIO_PIN_RESET 
307
+     && HAL_GPIO_ReadPin(PLL_ON_OFF_3_5G_H_GPIO_Port, PLL_ON_OFF_3_5G_H_Pin) == GPIO_PIN_SET){
308
+       temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
309
+       ADF4153_Module_Ctrl(Pll_3_5_H,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
310
+       HAL_Delay(1);
311
+     }
312
+     if(HAL_GPIO_ReadPin(PLL_LD_3_5G_L_GPIO_Port, PLL_LD_3_5G_L_Pin) == GPIO_PIN_RESET
313
+     && HAL_GPIO_ReadPin(PLL_ON_OFF_3_5G_L_GPIO_Port, PLL_ON_OFF_3_5G_L_Pin) == GPIO_PIN_SET){
314
+       temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
315
+       ADF4153_Module_Ctrl(Pll_3_5_L,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
316
+       HAL_Delay(1);
317
+     }
318
+
319
+
320
+}
321
+
322
+void ADF4153_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2,uint32_t R3){
323
+    R3  = R3  & 0x0007FF;
324
+    R2 = R2 & 0x00FFFF;
325
+    R1 = R1 & 0xFFFFFF;
326
+    R0 = R0 & 0xFFFFFF;
327
+//    ADF4153_Freq_Calc(3461500000,40000000,2,5000);
328
+    HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
329
+    HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
330
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
331
+#ifdef DEBUG_PRINT
332
+    printf("YJ :R0: %x  R1:  %x   R2 : %x R3 : %x ",R0,R1,R2,R3);
333
+    printf("\r\n");
334
+#endif /* DEBUG_PRINT */
335
+    /*   R3 Ctrl    */
336
+    for(int i =0; i < 11; i++){
337
+        if(R3 & 0x000400){
338
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_SET);
339
+#ifdef DEBUG_PRINT
340
+            printf("1");
341
+#endif /* DEBUG_PRINT */
342
+        }
343
+        else{
344
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
345
+#ifdef DEBUG_PRINT
346
+            printf("0");
347
+#endif /* DEBUG_PRINT */
348
+        }
349
+        Pol_Delay_us(10);
350
+        HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
351
+        Pol_Delay_us(10);
352
+        HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
353
+        R3 = (R3 << 1);
354
+    }
355
+#ifdef DEBUG_PRINT
356
+    printf("\r\n");
357
+#endif /* DEBUG_PRINT */
358
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
359
+      Pol_Delay_us(10);
360
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
361
+    
362
+    /*   R2 Ctrl    */
363
+     for(int i =0; i < 16; i++){
364
+         if(R2 & 0x008000){
365
+             HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_SET);
366
+#ifdef DEBUG_PRINT
367
+             printf("1");
368
+#endif /* DEBUG_PRINT */
369
+         }
370
+         else{
371
+             HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
372
+#ifdef DEBUG_PRINT
373
+             printf("0");
374
+#endif /* DEBUG_PRINT */
375
+         }
376
+         Pol_Delay_us(10);
377
+         HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
378
+         Pol_Delay_us(10);
379
+         HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
380
+
381
+         R2 = ((R2 << 1) & 0x00FFFF);
382
+     }
383
+#ifdef DEBUG_PRINT
384
+     printf("\r\n");
385
+#endif /* DEBUG_PRINT */
386
+     HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
387
+      Pol_Delay_us(10);
388
+     HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
389
+    
390
+     /*   R1 Ctrl    */
391
+    for(int i =0; i < 24; i++){
392
+        if(R1 & 0x800000){
393
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_SET);
394
+#ifdef DEBUG_PRINT
395
+            printf("1");
396
+#endif /* DEBUG_PRINT */
397
+        }
398
+        else{
399
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
400
+#ifdef DEBUG_PRINT
401
+            printf("0");
402
+#endif /* DEBUG_PRINT */
403
+        }
404
+        Pol_Delay_us(10);
405
+        HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
406
+        Pol_Delay_us(10);
407
+        HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
408
+
409
+        R1 = ((R1 << 1) & 0xFFFFFF);
410
+    }
411
+#ifdef DEBUG_PRINT
412
+    printf("\r\n");
413
+#endif /* DEBUG_PRINT */
414
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
415
+      Pol_Delay_us(10);
416
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
417
+
418
+
419
+        /*   R0 Ctrl    */
420
+   
421
+    for(int i =0; i < 24; i++){
422
+        if(R0 & 0x800000){
423
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_SET);
424
+#ifdef DEBUG_PRINT
425
+            printf("1");
426
+#endif /* DEBUG_PRINT */
427
+        }
428
+        else{
429
+            HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
430
+#ifdef DEBUG_PRINT
431
+            printf("0");
432
+#endif /* DEBUG_PRINT */
433
+        }
434
+        Pol_Delay_us(10);
435
+        HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_SET);
436
+        Pol_Delay_us(10);
437
+        HAL_GPIO_WritePin(pll.PLL_CLK_PORT, pll.PLL_CLK_PIN, GPIO_PIN_RESET);
438
+
439
+        R0 = ((R0 << 1) & 0xFFFFFF);
440
+    }
441
+#ifdef DEBUG_PRINT
442
+    printf("\r\n");
443
+#endif /* DEBUG_PRINT */
444
+    HAL_GPIO_WritePin(pll.PLL_DATA_PORT, pll.PLL_DATA_PIN, GPIO_PIN_RESET);
445
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_SET);
446
+    Pol_Delay_us(10);
447
+    HAL_GPIO_WritePin(pll.PLL_ENABLE_PORT, pll.PLL_ENABLE_PIN, GPIO_PIN_RESET);
448
+
449
+}

+ 766 - 0
insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/zig_operate(1884).c

@@ -0,0 +1,766 @@
1
+/*
2
+ * zig_operate.c
3
+ *
4
+ *  Created on: 2019. 7. 26.
5
+ *      Author: parkyj
6
+ */
7
+#include "zig_operate.h"
8
+#include "main.h"
9
+#include "pll_4113.h"
10
+#include "ADF4153.h"
11
+#include "PE43711.h"
12
+#include "BDA4601.h"
13
+#include "uart.h"
14
+#include "CRC16.h"
15
+extern void AD5318_Ctrl(uint16_t ShiftTarget) ;
16
+extern etError STH30_CheckCrc(uint8_t *data, uint8_t nbrOfBytes, uint8_t checksum);
17
+extern void ADF4153_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2,uint32_t R3);
18
+extern bool Bluecell_Flash_Read(uint8_t* data);
19
+extern void PE43711_ALL_atten_ctrl(ALL_PE43711_st ATT);
20
+extern void Power_ON_OFF_Ctrl(uint8_t type,uint8_t cmd);
21
+extern uint8_t Bluecell_Flash_Write(uint8_t* data);
22
+uint8_t Prev_data[INDEX_BLUE_EOF + 1];
23
+uint8_t Flash_Save_data[INDEX_BLUE_EOF + 1];
24
+
25
+
26
+/* * * * * * * #define Struct* * * * * * * */
27
+PLL_Setting_st Pll_1_8GHz_DL = {
28
+  PLL_CLK_GPIO_Port,
29
+  PLL_CLK_Pin,
30
+  PLL_DATA_GPIO_Port,
31
+  PLL_DATA_Pin,
32
+  PLL_EN_1_8G_DL_GPIO_Port,    
33
+  PLL_EN_1_8G_DL_Pin,
34
+};
35
+PLL_Setting_st Pll_1_8GHz_UL = {
36
+    PLL_CLK_GPIO_Port,
37
+    PLL_CLK_Pin,
38
+    PLL_DATA_GPIO_Port,
39
+    PLL_DATA_Pin,
40
+    PLL_EN_1_8G_UL_GPIO_Port,    
41
+    PLL_EN_1_8G_UL_Pin,
42
+};
43
+PLL_Setting_st Pll_2_1GHz_DL = {
44
+    PLL_CLK_GPIO_Port,
45
+    PLL_CLK_Pin,
46
+    PLL_DATA_GPIO_Port,
47
+    PLL_DATA_Pin,
48
+    PLL_EN_2_1G_DL_GPIO_Port,    
49
+    PLL_EN_2_1G_DL_Pin,
50
+};
51
+PLL_Setting_st Pll_2_1GHz_UL = {
52
+    PLL_CLK_GPIO_Port,
53
+    PLL_CLK_Pin,
54
+    PLL_DATA_GPIO_Port,
55
+    PLL_DATA_Pin,
56
+    PLL_EN_2_1G_UL_GPIO_Port,    
57
+    PLL_EN_2_1G_UL_Pin,
58
+};
59
+/* * * * * * * * NOT YET * * * * * * * */
60
+PLL_Setting_st Pll_3_5GHz_DL = {
61
+    ATT_CLK_3_5G_GPIO_Port,
62
+    ATT_EN_3_5G_Pin,
63
+    PLL_DATA_GPIO_Port,
64
+    PLL_DATA_Pin,
65
+    PLL_EN_2_1G_DL_GPIO_Port,    
66
+    PLL_EN_2_1G_DL_Pin,
67
+};
68
+PLL_Setting_st Pll_3_5GHz_UL = {
69
+    PLL_CLK_GPIO_Port,
70
+    PLL_CLK_Pin,
71
+    PLL_DATA_GPIO_Port,
72
+    PLL_DATA_Pin,
73
+    PLL_EN_2_1G_UL_GPIO_Port,    
74
+    PLL_EN_2_1G_UL_Pin,
75
+};
76
+/* * * * * * * * ATTEN * * * * * * * */    
77
+ATTEN_Setting_st Atten_1_8Ghz_DL1 ={
78
+    ATT_CLK_GPIO_Port,
79
+    ATT_CLK_Pin,
80
+    ATT_DATA_GPIO_Port,
81
+    ATT_DATA_Pin,
82
+    ATT_EN_1_8G_DL1_GPIO_Port,    
83
+    ATT_EN_1_8G_DL1_Pin,
84
+    PATH_EN_1_8G_DL_GPIO_Port,
85
+    PATH_EN_1_8G_DL_Pin,
86
+};
87
+
88
+ATTEN_Setting_st Atten_1_8Ghz_DL2 ={
89
+    ATT_CLK_GPIO_Port,
90
+    ATT_CLK_Pin,
91
+    ATT_DATA_GPIO_Port,
92
+    ATT_DATA_Pin,
93
+    ATT_EN_1_8G_DL2_GPIO_Port,    
94
+    ATT_EN_1_8G_DL2_Pin,
95
+    PATH_EN_1_8G_DL_GPIO_Port,
96
+    PATH_EN_1_8G_DL_Pin,    
97
+};
98
+ATTEN_Setting_st Atten_1_8Ghz_UL1 ={
99
+    ATT_CLK_GPIO_Port,
100
+    ATT_CLK_Pin,
101
+    ATT_DATA_GPIO_Port,
102
+    ATT_DATA_Pin,
103
+    ATT_EN_1_8G_UL1_GPIO_Port,    
104
+    ATT_EN_1_8G_UL1_Pin,
105
+    PATH_EN_1_8G_UL_GPIO_Port,
106
+    PATH_EN_1_8G_UL_Pin,      
107
+};
108
+ATTEN_Setting_st Atten_1_8Ghz_UL2 ={
109
+    ATT_CLK_GPIO_Port,
110
+    ATT_CLK_Pin,
111
+    ATT_DATA_GPIO_Port,
112
+    ATT_DATA_Pin,
113
+    ATT_EN_1_8G_UL2_GPIO_Port,    
114
+    ATT_EN_1_8G_UL2_Pin,
115
+    PATH_EN_1_8G_UL_GPIO_Port,
116
+    PATH_EN_1_8G_UL_Pin,    
117
+};
118
+ATTEN_Setting_st Atten_1_8Ghz_UL3 ={
119
+    ATT_CLK_GPIO_Port,
120
+    ATT_CLK_Pin,
121
+    ATT_DATA_GPIO_Port,
122
+    ATT_DATA_Pin,
123
+    ATT_EN_1_8G_UL3_GPIO_Port,    
124
+    ATT_EN_1_8G_UL3_Pin,
125
+    PATH_EN_1_8G_UL_GPIO_Port,
126
+    PATH_EN_1_8G_UL_Pin,    
127
+};
128
+ATTEN_Setting_st Atten_1_8Ghz_UL4 ={
129
+    ATT_CLK_GPIO_Port,
130
+    ATT_CLK_Pin,
131
+    ATT_DATA_GPIO_Port,
132
+    ATT_DATA_Pin,
133
+    ATT_EN_1_8G_UL4_GPIO_Port,    
134
+    ATT_EN_1_8G_UL4_Pin,
135
+    PATH_EN_1_8G_UL_GPIO_Port,
136
+    PATH_EN_1_8G_UL_Pin,    
137
+};
138
+ATTEN_Setting_st Atten_2_1Ghz_DL1 ={
139
+    ATT_CLK_GPIO_Port,
140
+    ATT_CLK_Pin,
141
+    ATT_DATA_GPIO_Port,
142
+    ATT_DATA_Pin,
143
+    ATT_EN_2_1G_DL1_GPIO_Port,    
144
+    ATT_EN_2_1G_DL1_Pin,
145
+    PATH_EN_2_1G_DL_GPIO_Port,
146
+    PATH_EN_2_1G_DL_Pin,    
147
+};
148
+ATTEN_Setting_st Atten_2_1Ghz_DL2 ={
149
+    ATT_CLK_GPIO_Port,
150
+    ATT_CLK_Pin,
151
+    ATT_DATA_GPIO_Port,
152
+    ATT_DATA_Pin,
153
+    ATT_EN_2_1G_DL2_GPIO_Port,    
154
+    ATT_EN_2_1G_DL2_Pin,
155
+    PATH_EN_2_1G_DL_GPIO_Port,
156
+    PATH_EN_2_1G_DL_Pin,    
157
+};
158
+
159
+ATTEN_Setting_st Atten_2_1Ghz_UL1 ={
160
+    ATT_CLK_GPIO_Port,
161
+    ATT_CLK_Pin,
162
+    ATT_DATA_GPIO_Port,
163
+    ATT_DATA_Pin,
164
+    ATT_EN_2_1G_UL1_GPIO_Port,    
165
+    ATT_EN_2_1G_UL1_Pin,
166
+    PATH_EN_2_1G_UL_GPIO_Port,
167
+    PATH_EN_2_1G_UL_Pin,    
168
+};
169
+ATTEN_Setting_st Atten_2_1Ghz_UL2 ={
170
+    ATT_CLK_GPIO_Port,
171
+    ATT_CLK_Pin,
172
+    ATT_DATA_GPIO_Port,
173
+    ATT_DATA_Pin,
174
+    ATT_EN_2_1G_UL2_GPIO_Port,    
175
+    ATT_EN_2_1G_UL2_Pin,
176
+    PATH_EN_2_1G_UL_GPIO_Port,
177
+    PATH_EN_2_1G_UL_Pin,    
178
+};
179
+ATTEN_Setting_st Atten_2_1Ghz_UL3 ={
180
+    ATT_CLK_GPIO_Port,
181
+    ATT_CLK_Pin,
182
+    ATT_DATA_GPIO_Port,
183
+    ATT_DATA_Pin,
184
+    ATT_EN_2_1G_UL3_GPIO_Port,    
185
+    ATT_EN_2_1G_UL3_Pin,
186
+    PATH_EN_2_1G_UL_GPIO_Port,
187
+    PATH_EN_2_1G_UL_Pin,    
188
+};
189
+ATTEN_Setting_st Atten_2_1Ghz_UL4 ={
190
+    ATT_CLK_GPIO_Port,
191
+    ATT_CLK_Pin,
192
+    ATT_DATA_GPIO_Port,
193
+    ATT_DATA_Pin,
194
+    ATT_EN_2_1G_UL4_GPIO_Port,    
195
+    ATT_EN_2_1G_UL4_Pin,
196
+    PATH_EN_2_1G_UL_GPIO_Port,
197
+    PATH_EN_2_1G_UL_Pin,    
198
+};
199
+
200
+
201
+bool RF_Data_Check(uint8_t* data_buf){
202
+    bool ret = false;
203
+    bool crcret = STH30_CheckCrc(&data_buf[Type], data_buf[Length], data_buf[data_buf[Crcindex]]);
204
+    if(data_buf[Header] == BLUECELL_HEADER){ /*HEADER CHECK*/
205
+        ret= true;
206
+    }
207
+    if(crcret == true){/*CRC CHECK*/
208
+        ret = true;
209
+    }else{
210
+        ret = false;
211
+//        printf("Recv CRC Value : \"%d\"\r\n Create CRC Value : \"%d\"   \r\n",data_buf[data_buf[Crcindex]],STH30_CreateCrc(&data_buf[Type], data_buf[Length]));
212
+    }
213
+//    printf("CRC Result : \"%d\"   \r\n",ret);
214
+    return ret;
215
+
216
+}
217
+
218
+PLL_Setting_st Pll_3_5_H = {
219
+     PLL_CLK_3_5G_GPIO_Port,
220
+     PLL_CLK_3_5G_Pin,
221
+     PLL_DATA_3_5G_GPIO_Port,
222
+     PLL_DATA_3_5G_Pin,
223
+   PLL_EN_3_5G_H_GPIO_Port,    
224
+   PLL_EN_3_5G_H_Pin,
225
+ };
226
+ PLL_Setting_st Pll_3_5_L = {
227
+     PLL_CLK_3_5G_GPIO_Port,
228
+     PLL_CLK_3_5G_Pin,
229
+     PLL_DATA_3_5G_GPIO_Port,
230
+     PLL_DATA_3_5G_Pin,
231
+       PLL_EN_3_5G_L_GPIO_Port,    
232
+       PLL_EN_3_5G_L_Pin,
233
+ };
234
+void RF_Status_Get(void){
235
+//    printf("\r\nYJ2 : Prev_data[INDEX_DET_1_8G_DL_IN_L ] : %x\r\n",Prev_data[INDEX_DET_1_8G_DL_IN_L]);            
236
+    Prev_data[INDEX_BLUE_HEADER]   = BLUECELL_HEADER;
237
+    Prev_data[INDEX_BLUE_TYPE]     = TYPE_BLUECELL_GET;
238
+    Prev_data[INDEX_BLUE_LENGTH]   = INDEX_BLUE_EOF - 2;
239
+    Prev_data[INDEX_BLUE_CRCINDEX] = INDEX_BLUE_CRC;
240
+    Prev_data[INDEX_BLUE_CRC]      = STH30_CreateCrc(&Prev_data[Type], Prev_data[Length]);
241
+    Prev_data[INDEX_BLUE_EOF] = BLUECELL_TAILER;    
242
+    HAL_UART_Transmit_DMA(&huart1,&Prev_data[INDEX_BLUE_HEADER],INDEX_BLUE_EOF + 1); 
243
+//    printf("\r\nYJ : %x",ADCvalue[0]);
244
+//    printf("\r\n");
245
+
246
+}
247
+static uint8_t Ack_Buf[6];
248
+void RF_Status_Ack(void){
249
+//    printf("\r\nYJ2 : Prev_data[INDEX_DET_1_8G_DL_IN_L ] : %x\r\n",Prev_data[INDEX_DET_1_8G_DL_IN_L]);            
250
+    Ack_Buf[INDEX_BLUE_HEADER]       = BLUECELL_HEADER;
251
+    Ack_Buf[INDEX_BLUE_TYPE]         = TYPE_BLUECELL_ACK;
252
+    Ack_Buf[INDEX_BLUE_LENGTH]       = 3;
253
+    Ack_Buf[INDEX_BLUE_CRCINDEX + 0] = INDEX_BLUE_CRCINDEX + 1;
254
+    Ack_Buf[INDEX_BLUE_CRCINDEX + 1] = STH30_CreateCrc(&Ack_Buf[Type], Ack_Buf[Length]);
255
+    Ack_Buf[INDEX_BLUE_CRCINDEX + 2] = BLUECELL_TAILER;
256
+    HAL_UART_Transmit_DMA(&huart1,&Ack_Buf[INDEX_BLUE_HEADER],Ack_Buf[INDEX_BLUE_LENGTH]  + 3); 
257
+//    printf("\r\nYJ : %x",ADCvalue[0]);
258
+//    printf("\r\n");
259
+
260
+}
261
+
262
+void RF_Operate(uint8_t* data_buf){
263
+    uint32_t temp_val = 0;
264
+    uint8_t  ADC_Modify = 0;
265
+    ADF4153_R_N_Reg_st temp_reg;
266
+//    printf("Prev_data[INDEX_ATT_1_8G_DL1]  : %x  data_buf[INDEX_ATT_1_8G_DL1] : %x\r\n",Prev_data[INDEX_ATT_1_8G_DL1],data_buf[INDEX_ATT_1_8G_DL1]);
267
+    if(Prev_data[INDEX_ATT_1_8G_DL1] != data_buf[INDEX_ATT_1_8G_DL1]){
268
+        BDA4601_atten_ctrl(BDA4601_1_8G_DL1,(data_buf[INDEX_ATT_1_8G_DL1]));
269
+        Prev_data[INDEX_ATT_1_8G_DL1] = data_buf[INDEX_ATT_1_8G_DL1];
270
+    }
271
+    if(Prev_data[INDEX_ATT_1_8G_DL2] != data_buf[INDEX_ATT_1_8G_DL2]){
272
+        BDA4601_atten_ctrl(BDA4601_1_8G_DL2,(data_buf[INDEX_ATT_1_8G_DL2]));
273
+        Prev_data[INDEX_ATT_1_8G_DL2] = data_buf[INDEX_ATT_1_8G_DL2];
274
+    }
275
+    if(Prev_data[INDEX_ATT_1_8G_UL1] != data_buf[INDEX_ATT_1_8G_UL1]){
276
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL1,(data_buf[INDEX_ATT_1_8G_UL1]));
277
+        Prev_data[INDEX_ATT_1_8G_UL1] = data_buf[INDEX_ATT_1_8G_UL1];
278
+    }
279
+    if(Prev_data[INDEX_ATT_1_8G_UL2] != data_buf[INDEX_ATT_1_8G_UL2]){
280
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL2,(data_buf[INDEX_ATT_1_8G_UL2]));
281
+        Prev_data[INDEX_ATT_1_8G_UL2] = data_buf[INDEX_ATT_1_8G_UL2];
282
+    }
283
+    if(Prev_data[INDEX_ATT_1_8G_UL3] != data_buf[INDEX_ATT_1_8G_UL3]){
284
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL3,(data_buf[INDEX_ATT_1_8G_UL3]));
285
+        Prev_data[INDEX_ATT_1_8G_UL3] = data_buf[INDEX_ATT_1_8G_UL3];
286
+    }
287
+    if(Prev_data[INDEX_ATT_1_8G_UL4] != data_buf[INDEX_ATT_1_8G_UL4]){
288
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL4,(data_buf[INDEX_ATT_1_8G_UL4]));
289
+        Prev_data[INDEX_ATT_1_8G_UL4] = data_buf[INDEX_ATT_1_8G_UL4];
290
+    }
291
+    if(Prev_data[INDEX_ATT_2_1G_DL1] != data_buf[INDEX_ATT_2_1G_DL1]){
292
+        BDA4601_atten_ctrl(BDA4601_2_1G_DL1,(data_buf[INDEX_ATT_2_1G_DL1]));
293
+        Prev_data[INDEX_ATT_2_1G_DL1] = data_buf[INDEX_ATT_2_1G_DL1];
294
+
295
+    }
296
+    if(Prev_data[INDEX_ATT_2_1G_DL2] != data_buf[INDEX_ATT_2_1G_DL2]){
297
+        BDA4601_atten_ctrl(BDA4601_2_1G_DL2,(data_buf[INDEX_ATT_2_1G_DL2]));
298
+        Prev_data[INDEX_ATT_2_1G_DL2] = data_buf[INDEX_ATT_2_1G_DL2];
299
+
300
+    }
301
+    if(Prev_data[INDEX_ATT_2_1G_UL1] != data_buf[INDEX_ATT_2_1G_UL1]){
302
+        BDA4601_atten_ctrl(BDA4601_2_1G_UL1,(data_buf[INDEX_ATT_2_1G_UL1]));
303
+        Prev_data[INDEX_ATT_2_1G_UL1] = data_buf[INDEX_ATT_2_1G_UL1];
304
+
305
+    }
306
+    if(Prev_data[INDEX_ATT_2_1G_UL2] != data_buf[INDEX_ATT_2_1G_UL2]){
307
+        BDA4601_atten_ctrl(BDA4601_2_1G_UL2,(data_buf[INDEX_ATT_2_1G_UL2]));
308
+        Prev_data[INDEX_ATT_2_1G_UL2] = data_buf[INDEX_ATT_2_1G_UL2];
309
+
310
+    }
311
+    if(Prev_data[INDEX_ATT_2_1G_UL3] != data_buf[INDEX_ATT_2_1G_UL3]){
312
+        BDA4601_atten_ctrl(BDA4601_2_1G_UL3,(data_buf[INDEX_ATT_2_1G_UL3]));
313
+        Prev_data[INDEX_ATT_2_1G_UL3] = data_buf[INDEX_ATT_2_1G_UL3];
314
+    }
315
+    if(Prev_data[INDEX_ATT_2_1G_UL4] != data_buf[INDEX_ATT_2_1G_UL4]){
316
+        BDA4601_atten_ctrl(BDA4601_2_1G_UL4,(data_buf[INDEX_ATT_2_1G_UL4]));
317
+        Prev_data[INDEX_ATT_2_1G_UL4] = data_buf[INDEX_ATT_2_1G_UL4];
318
+    }
319
+    if(   (Prev_data[INDEX_ATT_3_5G_LOW1] != data_buf[INDEX_ATT_3_5G_LOW1])
320
+        ||(Prev_data[INDEX_ATT_3_5G_HIGH1] != data_buf[INDEX_ATT_3_5G_HIGH1])
321
+        ||(Prev_data[INDEX_ATT_3_5G_COM1] != data_buf[INDEX_ATT_3_5G_COM1])
322
+        ||(Prev_data[INDEX_ATT_3_5G_LOW2] != data_buf[INDEX_ATT_3_5G_LOW2])
323
+        ||(Prev_data[INDEX_ATT_3_5G_HIGH2] != data_buf[INDEX_ATT_3_5G_HIGH2])
324
+        ||(Prev_data[INDEX_ATT_3_5G_COM2] != data_buf[INDEX_ATT_3_5G_COM2])
325
+    ){
326
+        ALL_ATT_3_5G.data0 = Prev_data[INDEX_ATT_3_5G_LOW1]  = data_buf[INDEX_ATT_3_5G_LOW1];
327
+        ALL_ATT_3_5G.data1 = Prev_data[INDEX_ATT_3_5G_HIGH1] = data_buf[INDEX_ATT_3_5G_HIGH1];
328
+        ALL_ATT_3_5G.data2 = Prev_data[INDEX_ATT_3_5G_COM1]  = data_buf[INDEX_ATT_3_5G_COM1];
329
+        ALL_ATT_3_5G.data3 = Prev_data[INDEX_ATT_3_5G_LOW2]  = data_buf[INDEX_ATT_3_5G_LOW2];
330
+        ALL_ATT_3_5G.data4 = Prev_data[INDEX_ATT_3_5G_HIGH2] = data_buf[INDEX_ATT_3_5G_HIGH2];
331
+        ALL_ATT_3_5G.data5 = Prev_data[INDEX_ATT_3_5G_COM2]  = data_buf[INDEX_ATT_3_5G_COM2];
332
+        PE43711_ALL_atten_ctrl(ALL_ATT_3_5G);
333
+    }
334
+    if((Prev_data[INDEX_PLL_1_8G_DL_H] != data_buf[INDEX_PLL_1_8G_DL_H])
335
+        || (Prev_data[INDEX_PLL_1_8G_DL_L] != data_buf[INDEX_PLL_1_8G_DL_L])
336
+    ){
337
+        Prev_data[INDEX_PLL_1_8G_DL_H] = data_buf[INDEX_PLL_1_8G_DL_H];
338
+        Prev_data[INDEX_PLL_1_8G_DL_L] = data_buf[INDEX_PLL_1_8G_DL_L];
339
+//        printf("data_buf[INDEX_PLL_1_8G_DL_H] : %x \r\n",data_buf[INDEX_PLL_1_8G_DL_H]);
340
+//        printf("data_buf[INDEX_PLL_1_8G_DL_L] : %x\r\n",data_buf[INDEX_PLL_1_8G_DL_L]);
341
+        temp_val = (data_buf[INDEX_PLL_1_8G_DL_H] << 8) | (data_buf[INDEX_PLL_1_8G_DL_L]);
342
+        ADF4113_Module_Ctrl(ADF4113_1_8G_DL,0x410,halSynSetFreq(temp_val * 100000),0x9F8092);
343
+//        ADF4113_Module_Ctrl(ADF4113_1_8G_DL,0x410,halSynSetFreq(16050 * 100000),0x9F8092);
344
+        HAL_Delay(1);
345
+        BDA4601_atten_ctrl(BDA4601_1_8G_DL1,(data_buf[INDEX_ATT_1_8G_DL1]));
346
+        BDA4601_atten_ctrl(BDA4601_1_8G_DL2,(data_buf[INDEX_ATT_1_8G_DL2]));
347
+    }
348
+    if((Prev_data[INDEX_PLL_1_8G_UL_H] != data_buf[INDEX_PLL_1_8G_UL_H])
349
+        || (Prev_data[INDEX_PLL_1_8G_UL_L] != data_buf[INDEX_PLL_1_8G_UL_L])){
350
+        temp_val = (data_buf[INDEX_PLL_1_8G_UL_H] << 8) | (data_buf[INDEX_PLL_1_8G_UL_L]);
351
+//        printf("data_buf[INDEX_PLL_1_8G_UL_H] : %x \r\n",data_buf[INDEX_PLL_1_8G_UL_H]);
352
+//        printf("data_buf[INDEX_PLL_1_8G_UL_L] : %x\r\n",data_buf[INDEX_PLL_1_8G_UL_L]);
353
+        Prev_data[INDEX_PLL_1_8G_UL_H] = data_buf[INDEX_PLL_1_8G_UL_H];
354
+        Prev_data[INDEX_PLL_1_8G_UL_L] = data_buf[INDEX_PLL_1_8G_UL_L];
355
+//         ADF4113_Module_Ctrl(ADF4113_1_8G_UL,0x000410,0x038D31,0x9f8092);
356
+         ADF4113_Module_Ctrl(ADF4113_1_8G_UL,0x410,halSynSetFreq(temp_val * 100000),0x9F8092);
357
+//        ADF4113_Module_Ctrl(ADF4113_1_8G_UL,0x410,halSynSetFreq(14485 * 100000),0x9F8092);
358
+
359
+        HAL_Delay(1);
360
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL1,(data_buf[INDEX_ATT_1_8G_UL1]));
361
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL2,(data_buf[INDEX_ATT_1_8G_UL2]));
362
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL3,(data_buf[INDEX_ATT_1_8G_UL3]));
363
+        BDA4601_atten_ctrl(BDA4601_1_8G_UL4,(data_buf[INDEX_ATT_1_8G_UL4]));
364
+    }
365
+    if((Prev_data[INDEX_PLL_2_1G_DL_H] != data_buf[INDEX_PLL_2_1G_DL_H])
366
+        || (Prev_data[INDEX_PLL_2_1G_DL_L] != data_buf[INDEX_PLL_2_1G_DL_L])){
367
+        temp_val = ((data_buf[INDEX_PLL_2_1G_DL_H] << 8) | (data_buf[INDEX_PLL_2_1G_DL_L]));
368
+//        printf("data_buf[INDEX_PLL_2_1G_DL_H] : %x \r\n",data_buf[INDEX_PLL_2_1G_DL_H]);
369
+//        printf("data_buf[INDEX_PLL_2_1G_DL_L] : %x\r\n",data_buf[INDEX_PLL_2_1G_DL_L]);
370
+        Prev_data[INDEX_PLL_2_1G_DL_H] = data_buf[INDEX_PLL_2_1G_DL_H];
371
+        Prev_data[INDEX_PLL_2_1G_DL_L] = data_buf[INDEX_PLL_2_1G_DL_L];        
372
+//         ADF4113_Module_Ctrl(ADF4113_2_1G_DL,0x410,0x4DE71,0x9F8092);
373
+      ADF4113_Module_Ctrl(ADF4113_2_1G_DL,0x410,halSynSetFreq(temp_val * 100000),0x9F8092);
374
+//      ADF4113_Module_Ctrl(ADF4113_2_1G_DL,0x410,halSynSetFreq(19864 * 100000),0x9F8092);
375
+
376
+      HAL_Delay(1);
377
+      BDA4601_atten_ctrl(BDA4601_2_1G_DL1,(data_buf[INDEX_ATT_2_1G_DL1]));
378
+      BDA4601_atten_ctrl(BDA4601_2_1G_DL2,(data_buf[INDEX_ATT_2_1G_DL2]));
379
+    }
380
+    if((Prev_data[INDEX_PLL_2_1G_UL_H] != data_buf[INDEX_PLL_2_1G_UL_H])
381
+        || (Prev_data[INDEX_PLL_2_1G_UL_L] != data_buf[INDEX_PLL_2_1G_UL_L])){
382
+        Prev_data[INDEX_PLL_2_1G_UL_H] = data_buf[INDEX_PLL_2_1G_UL_H];
383
+        Prev_data[INDEX_PLL_2_1G_UL_L] = data_buf[INDEX_PLL_2_1G_UL_L];    
384
+//        printf("data_buf[INDEX_PLL_2_1G_UL_H] : %x \r\n",data_buf[INDEX_PLL_2_1G_UL_H]);
385
+//        printf("data_buf[INDEX_PLL_2_1G_UL_L] : %x\r\n",data_buf[INDEX_PLL_2_1G_UL_L]);
386
+        temp_val = (data_buf[INDEX_PLL_2_1G_UL_H] << 8) | (data_buf[INDEX_PLL_2_1G_UL_L]);
387
+//        ADF4113_Module_Ctrl(ADF4113_2_1G_UL,0x000410,0x59A31,0x9f8092);
388
+      ADF4113_Module_Ctrl(ADF4113_2_1G_UL,0x410,halSynSetFreq(temp_val * 100000),0x9F8092);
389
+//      ADF4113_Module_Ctrl(ADF4113_2_1G_UL,0x410,halSynSetFreq(22879 * 100000),0x9F8092);
390
+      HAL_Delay(1);
391
+      BDA4601_atten_ctrl(BDA4601_2_1G_UL1,(data_buf[INDEX_ATT_2_1G_UL1]));
392
+      BDA4601_atten_ctrl(BDA4601_2_1G_UL2,(data_buf[INDEX_ATT_2_1G_UL2]));
393
+      BDA4601_atten_ctrl(BDA4601_2_1G_UL3,(data_buf[INDEX_ATT_2_1G_UL3]));      
394
+      BDA4601_atten_ctrl(BDA4601_2_1G_UL4,(data_buf[INDEX_ATT_2_1G_UL4]));      
395
+
396
+
397
+    }
398
+    if((Prev_data[INDEX_PLL_3_5G_LOW_H] != data_buf[INDEX_PLL_3_5G_LOW_H])
399
+        ||(Prev_data[INDEX_PLL_3_5G_LOW_M] != data_buf[INDEX_PLL_3_5G_LOW_M])
400
+        || (Prev_data[INDEX_PLL_3_5G_LOW_L] != data_buf[INDEX_PLL_3_5G_LOW_L])){
401
+        Prev_data[INDEX_PLL_3_5G_LOW_H] = data_buf[INDEX_PLL_3_5G_LOW_H];
402
+        Prev_data[INDEX_PLL_3_5G_LOW_M] = data_buf[INDEX_PLL_3_5G_LOW_M];        
403
+        Prev_data[INDEX_PLL_3_5G_LOW_L] = data_buf[INDEX_PLL_3_5G_LOW_L];
404
+        temp_val = (data_buf[INDEX_PLL_3_5G_LOW_H] << 16) | 
405
+                   (data_buf[INDEX_PLL_3_5G_LOW_M] << 8)  | 
406
+                   (data_buf[INDEX_PLL_3_5G_LOW_L]);
407
+#if 1 // PYJ.2019.08.12_BEGIN -- 
408
+        temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
409
+#else
410
+        temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
411
+#endif // PYJ.2019.08.12_END -- 
412
+//        ADF4153_Module_Ctrl(Pll_3_5_L,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
413
+      ADF4153_Module_Ctrl(Pll_3_5_L,0x385E48,0x163001,0x1442,3);
414
+
415
+    }
416
+    if((Prev_data[INDEX_PLL_3_5G_HIGH_H] != data_buf[INDEX_PLL_3_5G_HIGH_H])
417
+        || (Prev_data[INDEX_PLL_3_5G_HIGH_M] != data_buf[INDEX_PLL_3_5G_HIGH_M])
418
+        || (Prev_data[INDEX_PLL_3_5G_HIGH_L] != data_buf[INDEX_PLL_3_5G_HIGH_L])){
419
+        Prev_data[INDEX_PLL_3_5G_HIGH_H] = data_buf[INDEX_PLL_3_5G_HIGH_H];
420
+        Prev_data[INDEX_PLL_3_5G_HIGH_M] = data_buf[INDEX_PLL_3_5G_HIGH_M];
421
+        Prev_data[INDEX_PLL_3_5G_HIGH_L] = data_buf[INDEX_PLL_3_5G_HIGH_L];
422
+        temp_val = (data_buf[INDEX_PLL_3_5G_HIGH_H] << 16) |
423
+                   (data_buf[INDEX_PLL_3_5G_HIGH_M] << 8)  |
424
+                   (data_buf[INDEX_PLL_3_5G_HIGH_L]);
425
+#if 1 // PYJ.2019.08.12_BEGIN -- 
426
+        temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
427
+#else
428
+        temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
429
+#endif // PYJ.2019.08.12_END -- 
430
+//        ADF4153_Module_Ctrl(Pll_3_5_H,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
431
+        ADF4153_Module_Ctrl(Pll_3_5_H,0x4006C0,0x163001,0x14C2,3);
432
+    }
433
+    if(Prev_data[INDEX_PLL_LD_6_BIT] != data_buf[INDEX_PLL_LD_6_BIT]){
434
+
435
+    }
436
+#if 0 // PYJ.2019.07.28_BEGIN -- 
437
+    if(Prev_data[INDEX_DET_1_8G_DL_IN_H] != data_buf[INDEX_DET_1_8G_DL_IN_H]){
438
+
439
+    }
440
+    if(Prev_data[INDEX_DET_1_8G_DL_IN_L] != data_buf[INDEX_DET_1_8G_DL_IN_L]){
441
+
442
+    }
443
+    if(Prev_data[INDEX_DET_1_8G_DL_OUT_H] != data_buf[INDEX_DET_1_8G_DL_OUT_H]){
444
+
445
+    }
446
+    if(Prev_data[INDEX_DET_1_8G_DL_OUT_L] != data_buf[INDEX_DET_1_8G_DL_OUT_L]){
447
+
448
+    }
449
+    if(Prev_data[INDEX_DET_1_8G_UL_IN_H] != data_buf[INDEX_DET_1_8G_UL_IN_H]){
450
+
451
+    }
452
+    if(Prev_data[INDEX_DET_1_8G_UL_IN_L] != data_buf[INDEX_DET_1_8G_UL_IN_L]){
453
+
454
+    }
455
+    if(Prev_data[INDEX_DET_1_8G_UL_OUT_H] != data_buf[INDEX_DET_1_8G_UL_OUT_H]){
456
+
457
+    }
458
+    if(Prev_data[INDEX_DET_1_8G_UL_OUT_L] != data_buf[INDEX_DET_1_8G_UL_OUT_L]){
459
+
460
+    }
461
+    if(Prev_data[INDEX_DET_2_1G_DL_IN_H] != data_buf[INDEX_DET_2_1G_DL_IN_H]){
462
+
463
+    }
464
+    if(Prev_data[INDEX_DET_2_1G_DL_IN_L] != data_buf[INDEX_DET_2_1G_DL_IN_L]){
465
+
466
+    }
467
+    if(Prev_data[INDEX_DET_2_1G_DL_OUT_H] != data_buf[INDEX_DET_2_1G_DL_OUT_H]){
468
+
469
+    }
470
+    if(Prev_data[INDEX_DET_2_1G_DL_OUT_L] != data_buf[INDEX_DET_2_1G_DL_OUT_L]){
471
+
472
+    }
473
+    if(Prev_data[INDEX_DET_2_1G_UL_IN_H] != data_buf[INDEX_DET_2_1G_UL_IN_H]){
474
+
475
+    }
476
+    if(Prev_data[INDEX_DET_2_1G_UL_IN_L] != data_buf[INDEX_DET_2_1G_UL_IN_L]){
477
+
478
+    }
479
+
480
+    if(Prev_data[INDEX_DET_2_1G_UL_OUT_H] != data_buf[INDEX_DET_2_1G_UL_OUT_H]){
481
+
482
+    }
483
+    if(Prev_data[INDEX_DET_2_1G_UL_OUT_L] != data_buf[INDEX_DET_2_1G_UL_OUT_L]){
484
+
485
+    }
486
+    if(Prev_data[INDEX_DET_3_5G_DL_IN_H] != data_buf[INDEX_DET_3_5G_DL_IN_H]){
487
+
488
+    }
489
+    if(Prev_data[INDEX_DET_3_5G_DL_IN_L] != data_buf[INDEX_DET_3_5G_DL_IN_L]){
490
+
491
+    }
492
+    if(Prev_data[INDEX_DET_3_5G_DL_OUT_L] != data_buf[INDEX_DET_3_5G_DL_OUT_L]){
493
+
494
+    }
495
+    if(Prev_data[INDEX_DET_3_5G_DL_OUT_H] != data_buf[INDEX_DET_3_5G_DL_OUT_H]){
496
+
497
+    }
498
+    if(Prev_data[INDEX_DET_3_5G_UL_IN_H] != data_buf[INDEX_DET_3_5G_UL_IN_H]){
499
+
500
+    }
501
+    if(Prev_data[INDEX_DET_3_5G_UL_IN_L] != data_buf[INDEX_DET_3_5G_UL_IN_L]){
502
+
503
+    }
504
+
505
+    if(Prev_data[INDEX_DET_3_5G_UL_OUT_H] != data_buf[INDEX_DET_3_5G_UL_OUT_H]){
506
+
507
+    }
508
+    if(Prev_data[INDEX_DET_3_5G_UL_OUT_L] != data_buf[INDEX_DET_3_5G_UL_OUT_L]){
509
+
510
+    }
511
+    if(Prev_data[INDEX_RFU_TEMP_H] != data_buf[INDEX_RFU_TEMP_H]){
512
+
513
+    }
514
+    if(Prev_data[INDEX_RFU_TEMP_L] != data_buf[INDEX_RFU_TEMP_L]){
515
+
516
+    }
517
+    if(Prev_data[INDEX__28V_DET_H] != data_buf[INDEX__28V_DET_H]){
518
+
519
+    }
520
+    if(Prev_data[INDEX__28V_DET_L] != data_buf[INDEX__28V_DET_L]){
521
+
522
+    }
523
+#endif // PYJ.2019.07.28_END -- 
524
+    if(Prev_data[INDEX_ALARM_AC] != data_buf[INDEX_ALARM_AC]){
525
+
526
+    }
527
+    if(Prev_data[INDEX_ALARM_DC] != data_buf[INDEX_ALARM_DC]){
528
+
529
+    }
530
+    if(Prev_data[INDEX_PATH_EN_1_8G_DL] != data_buf[INDEX_PATH_EN_1_8G_DL]){
531
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_1_8G_DL,data_buf[INDEX_PATH_EN_1_8G_DL]);
532
+        Prev_data[INDEX_PATH_EN_1_8G_DL] = data_buf[INDEX_PATH_EN_1_8G_DL];
533
+    }
534
+    if(Prev_data[INDEX_PATH_EN_1_8G_UL] != data_buf[INDEX_PATH_EN_1_8G_UL]){
535
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_1_8G_UL,data_buf[INDEX_PATH_EN_1_8G_UL]);
536
+        Prev_data[INDEX_PATH_EN_1_8G_UL] = data_buf[INDEX_PATH_EN_1_8G_UL];
537
+
538
+    }
539
+
540
+    if(Prev_data[INDEX_PATH_EN_2_1G_DL] != data_buf[INDEX_PATH_EN_2_1G_DL]){
541
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_2_1G_DL,data_buf[INDEX_PATH_EN_2_1G_DL]);
542
+        Prev_data[INDEX_PATH_EN_2_1G_DL] = data_buf[INDEX_PATH_EN_2_1G_DL];
543
+    }
544
+    if(Prev_data[INDEX_PATH_EN_2_1G_UL] != data_buf[INDEX_PATH_EN_2_1G_UL]){
545
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_2_1G_UL,data_buf[INDEX_PATH_EN_2_1G_UL]);
546
+        Prev_data[INDEX_PATH_EN_2_1G_UL] = data_buf[INDEX_PATH_EN_2_1G_UL];
547
+
548
+    }
549
+    if(Prev_data[INDEX_PATH_EN_3_5G_L] != data_buf[INDEX_PATH_EN_3_5G_L]){
550
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_L,data_buf[INDEX_PATH_EN_3_5G_L]);
551
+        Prev_data[INDEX_PATH_EN_3_5G_L] = data_buf[INDEX_PATH_EN_3_5G_L];
552
+
553
+    }
554
+    if(Prev_data[INDEX_PATH_EN_3_5G_H] != data_buf[INDEX_PATH_EN_3_5G_H]){
555
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_H,data_buf[INDEX_PATH_EN_3_5G_H]);
556
+        Prev_data[INDEX_PATH_EN_3_5G_H] = data_buf[INDEX_PATH_EN_3_5G_H];
557
+    
558
+
559
+    }
560
+    if(Prev_data[INDEX_PATH_EN_3_5G_DL] != data_buf[INDEX_PATH_EN_3_5G_DL]){
561
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_DL,data_buf[INDEX_PATH_EN_3_5G_DL]);
562
+        Prev_data[INDEX_PATH_EN_3_5G_DL] = data_buf[INDEX_PATH_EN_3_5G_DL];
563
+        ADC_Modify = 1;
564
+
565
+    }
566
+    if(Prev_data[INDEX_PATH_EN_3_5G_UL] != data_buf[INDEX_PATH_EN_3_5G_UL]){
567
+        Power_ON_OFF_Ctrl(INDEX_PATH_EN_3_5G_UL,data_buf[INDEX_PATH_EN_3_5G_UL]);
568
+        Prev_data[INDEX_PATH_EN_3_5G_UL] = data_buf[INDEX_PATH_EN_3_5G_UL];
569
+        ADC_Modify = 1;
570
+    }
571
+    if(Prev_data[INDEX_PLL_ON_OFF_3_5G_H] != data_buf[INDEX_PLL_ON_OFF_3_5G_H]){
572
+        Power_ON_OFF_Ctrl(INDEX_PLL_ON_OFF_3_5G_H,data_buf[INDEX_PLL_ON_OFF_3_5G_H]);
573
+        Prev_data[INDEX_PLL_ON_OFF_3_5G_H] = data_buf[INDEX_PLL_ON_OFF_3_5G_H];
574
+        HAL_Delay(1);
575
+//        printf("POWER : %d \r\n",Prev_data[INDEX_PLL_ON_OFF_3_5G_H]);
576
+        if(data_buf[INDEX_PLL_ON_OFF_3_5G_H]){
577
+//            printf("PLL CTRL START !! \r\n");
578
+#if 1 // PYJ.2019.08.12_BEGIN -- 
579
+//            temp_val = (Prev_data[INDEX_PLL_3_5G_LOW_H] << 16) |
580
+//                       (Prev_data[INDEX_PLL_3_5G_LOW_M] << 8) | 
581
+//                       (Prev_data[INDEX_PLL_3_5G_LOW_L]);
582
+            temp_val = (Prev_data[INDEX_PLL_3_5G_HIGH_H] << 16) | 
583
+                       (Prev_data[INDEX_PLL_3_5G_HIGH_M] << 8)  | 
584
+                       (Prev_data[INDEX_PLL_3_5G_HIGH_L]);
585
+
586
+
587
+//            temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
588
+            temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_122_88MHzREFIN,ADF4153_8RCOUNTER,ADF4153_CHANNEL_SPACING);
589
+#else
590
+            temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
591
+#endif // PYJ.2019.08.12_END -- 
592
+//            ADF4153_Module_Ctrl(Pll_3_5_H,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
593
+//            ADF4153_Module_Ctrl(Pll_3_5_H,0x4006C0,0x163001,0x14C2,3);
594
+
595
+            PE43711_ALL_atten_ctrl(ALL_ATT_3_5G);
596
+        }
597
+    }
598
+    if(Prev_data[INDEX_PLL_ON_OFF_3_5G_L] != data_buf[INDEX_PLL_ON_OFF_3_5G_L]){
599
+        Power_ON_OFF_Ctrl(INDEX_PLL_ON_OFF_3_5G_L,data_buf[INDEX_PLL_ON_OFF_3_5G_L]);
600
+        Prev_data[INDEX_PLL_ON_OFF_3_5G_L] = data_buf[INDEX_PLL_ON_OFF_3_5G_L];
601
+        HAL_Delay(1);
602
+//        printf("POWER : %d \r\n",Prev_data[INDEX_PLL_ON_OFF_3_5G_L]);        
603
+        if(data_buf[INDEX_PLL_ON_OFF_3_5G_L]){
604
+//            printf("PLL CTRL START !! \r\n");
605
+#if 1 // PYJ.2019.08.12_BEGIN -- 
606
+//            temp_val = (Prev_data[INDEX_PLL_3_5G_HIGH_H] << 16) | 
607
+//                       (Prev_data[INDEX_PLL_3_5G_HIGH_M] << 8)  | 
608
+//                       (Prev_data[INDEX_PLL_3_5G_HIGH_L]);
609
+            temp_val = (Prev_data[INDEX_PLL_3_5G_LOW_H] << 16) |
610
+                       (Prev_data[INDEX_PLL_3_5G_LOW_M] << 8) | 
611
+                       (Prev_data[INDEX_PLL_3_5G_LOW_L]);
612
+            temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);
613
+//            temp_reg = ADF4153_Freq_Calc(temp_val  * 10000,ADF4153_122_88MHzREFIN,ADF4153_8RCOUNTER,ADF4153_CHANNEL_SPACING);
614
+#else
615
+          temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_40MHzREFIN,ADF4153_2RCOUNTER,ADF4153_CHANNEL_SPACING);            
616
+#endif // PYJ.2019.08.12_END -- 
617
+//            ADF4153_Module_Ctrl(Pll_3_5_L,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
618
+            PE43711_ALL_atten_ctrl(ALL_ATT_3_5G);
619
+        }
620
+    }
621
+
622
+    if(Prev_data[INDEX_T_SYNC_DL] != data_buf[INDEX_T_SYNC_DL]){
623
+        Prev_data[INDEX_T_SYNC_DL] = data_buf[INDEX_T_SYNC_DL];
624
+        Power_ON_OFF_Ctrl(INDEX_T_SYNC_DL,data_buf[INDEX_T_SYNC_DL]);
625
+    }
626
+    if(Prev_data[INDEX__T_SYNC_DL] != data_buf[INDEX__T_SYNC_DL]){
627
+        Prev_data[INDEX__T_SYNC_DL] = data_buf[INDEX__T_SYNC_DL];
628
+        Power_ON_OFF_Ctrl(INDEX__T_SYNC_DL,data_buf[INDEX__T_SYNC_DL]);
629
+    }
630
+    if(Prev_data[INDEX_T_SYNC_UL] != data_buf[INDEX_T_SYNC_UL]){
631
+        Prev_data[INDEX_T_SYNC_UL] = data_buf[INDEX_T_SYNC_UL];
632
+        Power_ON_OFF_Ctrl(INDEX_T_SYNC_UL,data_buf[INDEX_T_SYNC_UL]);
633
+    }
634
+    if(Prev_data[INDEX__T_SYNC_UL] != data_buf[INDEX__T_SYNC_UL]){
635
+        Prev_data[INDEX__T_SYNC_UL] = data_buf[INDEX__T_SYNC_UL];
636
+        Power_ON_OFF_Ctrl(INDEX__T_SYNC_UL,data_buf[INDEX__T_SYNC_UL]);
637
+    }
638
+
639
+
640
+    if((Prev_data[INDEX_DAC_VCtrl_A_H] != data_buf[INDEX_DAC_VCtrl_A_H])
641
+        ||(Prev_data[INDEX_DAC_VCtrl_A_L] != data_buf[INDEX_DAC_VCtrl_A_L])){
642
+        ADC_Modify = 1;
643
+        Prev_data[INDEX_DAC_VCtrl_A_H] = data_buf[INDEX_DAC_VCtrl_A_H];
644
+        Prev_data[INDEX_DAC_VCtrl_A_L] = data_buf[INDEX_DAC_VCtrl_A_L];
645
+    }
646
+    if((Prev_data[INDEX_DAC_VCtrl_B_H] != data_buf[INDEX_DAC_VCtrl_B_H])
647
+        ||(Prev_data[INDEX_DAC_VCtrl_B_L] != data_buf[INDEX_DAC_VCtrl_B_L])){
648
+        ADC_Modify = 1;
649
+        
650
+        Prev_data[INDEX_DAC_VCtrl_B_H] = data_buf[INDEX_DAC_VCtrl_B_H];
651
+        Prev_data[INDEX_DAC_VCtrl_B_L] = data_buf[INDEX_DAC_VCtrl_B_L];        
652
+    }    
653
+    if((Prev_data[INDEX_DAC_VCtrl_C_H] != data_buf[INDEX_DAC_VCtrl_C_H])
654
+        ||(Prev_data[INDEX_DAC_VCtrl_C_L] != data_buf[INDEX_DAC_VCtrl_C_L])){
655
+        ADC_Modify = 1;
656
+//        printf("Prev_data[INDEX_DAC_VCtrl_C_H] : %x \r\n",Prev_data[INDEX_DAC_VCtrl_C_H]);
657
+//        printf("Prev_data[INDEX_DAC_VCtrl_C_L] : %x \r\n",Prev_data[INDEX_DAC_VCtrl_C_L]);
658
+
659
+        Prev_data[INDEX_DAC_VCtrl_C_H] = data_buf[INDEX_DAC_VCtrl_C_H];
660
+        Prev_data[INDEX_DAC_VCtrl_C_L] = data_buf[INDEX_DAC_VCtrl_C_L];        
661
+    }
662
+    if((Prev_data[INDEX_DAC_VCtrl_D_H] != data_buf[INDEX_DAC_VCtrl_D_H])
663
+        ||(Prev_data[INDEX_DAC_VCtrl_D_L] != data_buf[INDEX_DAC_VCtrl_D_L])){
664
+        ADC_Modify = 1;
665
+        Prev_data[INDEX_DAC_VCtrl_D_H] = data_buf[INDEX_DAC_VCtrl_D_H];
666
+        Prev_data[INDEX_DAC_VCtrl_D_L] = data_buf[INDEX_DAC_VCtrl_D_L];
667
+    }
668
+    if((Prev_data[INDEX_DAC_VCtrl_E_H] != data_buf[INDEX_DAC_VCtrl_E_H])
669
+        ||(Prev_data[INDEX_DAC_VCtrl_E_L] != data_buf[INDEX_DAC_VCtrl_E_L])){
670
+        ADC_Modify = 1;
671
+
672
+        Prev_data[INDEX_DAC_VCtrl_E_H] = data_buf[INDEX_DAC_VCtrl_E_H];
673
+        Prev_data[INDEX_DAC_VCtrl_E_L] = data_buf[INDEX_DAC_VCtrl_E_L];        
674
+    }
675
+    if((Prev_data[INDEX_DAC_VCtrl_F_H] != data_buf[INDEX_DAC_VCtrl_F_H])
676
+        ||(Prev_data[INDEX_DAC_VCtrl_F_L] != data_buf[INDEX_DAC_VCtrl_F_L])){
677
+        ADC_Modify = 1;
678
+        Prev_data[INDEX_DAC_VCtrl_F_H] = data_buf[INDEX_DAC_VCtrl_F_H];
679
+        Prev_data[INDEX_DAC_VCtrl_F_L] = data_buf[INDEX_DAC_VCtrl_F_L];        
680
+    }
681
+    if((Prev_data[INDEX_DAC_VCtrl_G_H] != data_buf[INDEX_DAC_VCtrl_G_H])
682
+        ||(Prev_data[INDEX_DAC_VCtrl_G_L] != data_buf[INDEX_DAC_VCtrl_G_L])){
683
+        ADC_Modify = 1;
684
+        Prev_data[INDEX_DAC_VCtrl_G_H] = data_buf[INDEX_DAC_VCtrl_G_H];
685
+        Prev_data[INDEX_DAC_VCtrl_G_L] = data_buf[INDEX_DAC_VCtrl_G_L];        
686
+    }    
687
+    if((Prev_data[INDEX_DAC_VCtrl_H_H] != data_buf[INDEX_DAC_VCtrl_H_H])
688
+        ||(Prev_data[INDEX_DAC_VCtrl_H_L] != data_buf[INDEX_DAC_VCtrl_H_L])){
689
+        ADC_Modify = 1;
690
+        Prev_data[INDEX_DAC_VCtrl_H_H] = data_buf[INDEX_DAC_VCtrl_H_H];
691
+        Prev_data[INDEX_DAC_VCtrl_H_L] = data_buf[INDEX_DAC_VCtrl_H_L];        
692
+    }
693
+    if(ADC_Modify){
694
+//        AD5318_Ctrl(0xF000);
695
+//        HAL_Delay(1);
696
+//        AD5318_Ctrl(0x800C);
697
+//        AD5318_Ctrl(0x2FFF );
698
+//        AD5318_Ctrl(0xA000);
699
+//        printf("DAC CTRL START \r\n");
700
+//        AD5318_Ctrl(0x800C);
701
+//        AD5318_Ctrl(0xA000);
702
+//        printf("DAC Change\r\n");
703
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_A_H] << 8 | Prev_data[INDEX_DAC_VCtrl_A_L]));    
704
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_B_H] << 8 | Prev_data[INDEX_DAC_VCtrl_B_L]));    
705
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_C_H] << 8 | Prev_data[INDEX_DAC_VCtrl_C_L]));
706
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_D_H] << 8 | Prev_data[INDEX_DAC_VCtrl_D_L]));
707
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_E_H] << 8 | Prev_data[INDEX_DAC_VCtrl_E_L]));    
708
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_F_H] << 8 | Prev_data[INDEX_DAC_VCtrl_F_L]));
709
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_G_H] << 8 | Prev_data[INDEX_DAC_VCtrl_G_L]));
710
+        AD5318_Ctrl((Prev_data[INDEX_DAC_VCtrl_H_H] << 8 | Prev_data[INDEX_DAC_VCtrl_H_L]));
711
+    }
712
+    
713
+}
714
+
715
+uint8_t temp_crc = 0;
716
+bool RF_Ctrl_Main(uint8_t* data_buf){
717
+    bool ret = false;
718
+    Bluecell_Prot_t type = data_buf[Type];
719
+    ret = RF_Data_Check(&data_buf[Header]); /* ERROR CHECK */
720
+    if(ret == false){
721
+        HAL_UART_Transmit(&huart1,&data_buf[INDEX_BLUE_HEADER],data_buf[INDEX_BLUE_LENGTH] + 2 + 1,3000); 
722
+        return ret;
723
+    }
724
+    
725
+    switch(type){
726
+    case TYPE_BLUECELL_RESET:
727
+        for(uint8_t i =0 ; i < data_buf[Length] + 6; i++)
728
+            printf("%02x ",data_buf[i]);
729
+        printf("Reset Start \r\n");
730
+        NVIC_SystemReset();
731
+        break;
732
+    case TYPE_BLUECELL_SET:
733
+#if 0 // PYJ.2019.07.31_BEGIN -- 
734
+    printf("TYPE_BLUECELL_SET : ");
735
+    for(uint8_t i =0 ; i < INDEX_BLUE_EOF + 1; i++)
736
+        printf("%02x ",data_buf[i]);
737
+#endif // PYJ.2019.07.31_END -- 
738
+        RF_Operate(&data_buf[Header]);
739
+        RF_Status_Ack();
740
+
741
+//        ADF4153_Freq_Calc(3465500000,40000000,2,5000);
742
+//        ADF4153_Freq_Calc(3993450000,40000000,2,5000);
743
+//        halSynSetFreq(1995000000);
744
+//        halSynSetFreq(1600000000);
745
+//        halSynSetFreq(1455000000);        
746
+        break;
747
+    case TYPE_BLUECELL_GET:
748
+#if 0 // PYJ.2019.08.01_BEGIN -- 
749
+        printf("\r\nTYPE_BLUECELL_GET : \r\n");
750
+#endif // PYJ.2019.08.01_END -- 
751
+        RF_Status_Get();
752
+        break;
753
+    case TYPE_BLUECELL_SAVE:
754
+//        printf("\r\nFLASH Write\r\n");
755
+        Bluecell_Flash_Write(&Prev_data[INDEX_BLUE_HEADER]);
756
+        RF_Status_Ack();
757
+
758
+        break;
759
+        default:
760
+#ifdef DEBUG_PRINT // PYJ.2019.07.27_BEGIN --         
761
+            printf("Function : %s   LINE : %d    type : %d \r\n",__func__,__LINE__,type);
762
+#endif
763
+            break;
764
+    }
765
+    return ret;
766
+}

BIN
insight/STM32F103_ATTEN_PLL_Zig.si4project/STM32F103_ATTEN_PLL_Zig.sip_xm


BIN
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Device_ST_STM32F1xx_Include_stm32f103xe.h.sisc


BIN
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_core_cm7.h.sisc


BIN
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_gpio.h.sisc


BIN
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_adf4153.h.sisc


BIN
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_pll_4113.h.sisc


BIN
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_zig_operate.h.sisc


BIN
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_adf4153.c.sisc


BIN
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_flash.c.sisc


BIN
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_main.c.sisc


BIN
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_pll_4113.c.sisc


BIN
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_zig_operate.c.sisc