LD Search 추가 /

Debug/Src/main.su

@@ -1,6 +1,6 @@
-main.c:81:6:HAL_TIM_PeriodElapsedCallback	0	static
-main.c:90:5:_write	8	static
-main.c:96:6:Pol_Delay_us	8	static
-main.c:313:6:SystemClock_Config	96	static
-main.c:126:5:main	200	static
-main.c:754:6:Error_Handler	0	static
+main.c:84:6:HAL_TIM_PeriodElapsedCallback	0	static
+main.c:93:5:_write	8	static
+main.c:99:6:Pol_Delay_us	8	static
+main.c:332:6:SystemClock_Config	96	static
+main.c:129:5:main	208	static
+main.c:773:6:Error_Handler	0	static

Inc/main.h

@@ -233,6 +233,9 @@ extern void Pol_Delay_us(volatile uint32_t microseconds);
 #define BLUECELL_HEADER 0xBE
 #define BLUECELL_TAILER 0xEB
 //#define DEBUG_PRINT   
+#define ADC_EA     14
+uint32_t ADCvalue[ADC_EA];
+
 /* USER CODE END Private defines */
 
 #ifdef __cplusplus

Inc/pll_4113.h

@@ -7,6 +7,7 @@
 #ifndef HAL_ADF4113_H
 #define HAL_ADF4113_H
 #include "main.h"
+
 typedef struct _PLL_Setting_st{
     GPIO_TypeDef * PLL_CLK_PORT;
     uint16_t       PLL_CLK_PIN;
@@ -15,6 +16,7 @@ typedef struct _PLL_Setting_st{
     GPIO_TypeDef * PLL_ENABLE_PORT;
     uint16_t       PLL_ENABLE_PIN;
 } PLL_Setting_st;
+
 PLL_Setting_st ADF4113_1_8G_DL;
 PLL_Setting_st ADF4113_1_8G_UL;
 PLL_Setting_st ADF4113_2_1G_DL;

Inc/zig_operate.h

@@ -105,7 +105,7 @@ typedef enum{
     INDEX__T_SYNC_UL,    
     INDEX_DAC_VCtrl_A_H,
     INDEX_DAC_VCtrl_A_L,
-    INDEX_DAC_VCtrl_B_H,
+    INDEX_DAC_VCtrl_B_H = 80, 
     INDEX_DAC_VCtrl_B_L,
     INDEX_DAC_VCtrl_C_H,
     INDEX_DAC_VCtrl_C_L,
@@ -115,13 +115,16 @@ typedef enum{
     INDEX_DAC_VCtrl_E_L,
     INDEX_DAC_VCtrl_F_H,
     INDEX_DAC_VCtrl_F_L,
-    INDEX_DAC_VCtrl_G_H,
+    INDEX_DAC_VCtrl_G_H = 90,
     INDEX_DAC_VCtrl_G_L,
     INDEX_DAC_VCtrl_H_H,
     INDEX_DAC_VCtrl_H_L,   
     INDEX_BLUE_CRC, 
-    INDEX_BLUE_EOF,//87
+    INDEX_BLUE_EOF,//95
 }Bluecell_Prot_Index;
 uint8_t Prev_data[INDEX_BLUE_EOF + 1];
+//extern PLL_Setting_st Pll_3_5_H;
+//extern PLL_Setting_st Pll_3_5_L;
+
 
 #endif /* ZIG_OPERATE_H_ */

Src/AD5318.c

@@ -7,7 +7,7 @@
  #include "ad5318.h"
 void SubmitDAC(uint16_t ShiftTarget) {
     char i; /* serial counter */
-    printf("ShiftTarget : %x \r\n",ShiftTarget);
+//    printf("ShiftTarget : %x \r\n",ShiftTarget);
     HAL_GPIO_WritePin(DA_SYNC_GPIO_Port, DA_SYNC_Pin, GPIO_PIN_RESET);    
     for (i=0;i < 16;i++) { /* loop through all 16 data bits */
         HAL_GPIO_WritePin(DA_SCLK_GPIO_Port, DA_SCLK_Pin, GPIO_PIN_SET); /* rise clk line again */

Src/PE43711.c

@@ -77,7 +77,7 @@ void Bit_Compare(PE43711_st ATT,uint8_t data,uint8_t Shift_Index){
 void PE43711_ALL_atten_ctrl(ALL_PE43711_st ATT){
     HAL_GPIO_WritePin(ATT.ATT0.LE_PORT,ATT.ATT0.LE_PIN,GPIO_PIN_RESET);
     Pol_Delay_us(10);
-    printf("why not? \r\n");
+//    printf("why not? \r\n");
     for(uint8_t i = 0; i < 8; i++){
         Bit_Compare(ATT.ATT0,ATT.data0,i);
         Bit_Compare(ATT.ATT1,ATT.data1,i);

Src/main.c

@@ -55,6 +55,9 @@ DMA_HandleTypeDef hdma_usart1_tx;
 volatile uint32_t AdcTimerCnt = 0;
 volatile uint32_t LedTimerCnt = 0;
 volatile uint32_t UartRxTimerCnt = 0;
+extern PLL_Setting_st Pll_3_5_H;
+extern PLL_Setting_st Pll_3_5_L;
+
 //volatile uint32_t UartTxTimerCnt = 0;
 
 /* USER CODE END PV */
@@ -73,7 +76,7 @@ static void MX_NVIC_Init(void);
 
 /* Private user code ---------------------------------------------------------*/
 /* USER CODE BEGIN 0 */
-#define ADC_EA     14
+
 uint32_t ADCvalue[ADC_EA];
 
 #if 1 // PYJ.2019.07.26_BEGIN --
@@ -263,6 +266,7 @@ int main(void)
   ADF4113_Module_Ctrl(Pll_test6,0x000410,0x03E801,0x9F8092);
   BDA4601_Test();
   HAL_ADCEx_Calibration_Start(&hadc1);
+  ADF4153_R_N_Reg_st temp_reg;
 
 
 //  ADF_Module_Ctrl(Pll_test,0x324000,0x144051,0x0017c2,0x0003c7);
@@ -275,20 +279,35 @@ int main(void)
 //   HAL_ADC_Start_DMA(&hadc1, (uint32_t*)ADCvalue, ADC_EA);
   while (1)
   {
+    if(HAL_GPIO_ReadPin(PLL_LD_3_5G_H_GPIO_Port, PLL_LD_3_5G_H_Pin) == GPIO_PIN_RESET){
+        temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
+        ADF4153_Module_Ctrl(Pll_3_5_H,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
+        HAL_Delay(1);
+    }
+    if(HAL_GPIO_ReadPin(PLL_LD_3_5G_L_GPIO_Port, PLL_LD_3_5G_L_Pin) == GPIO_PIN_RESET){
+        temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
+        ADF4153_Module_Ctrl(Pll_3_5_L,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
+        HAL_Delay(1);
+    }
     if(LedTimerCnt > 500){HAL_GPIO_TogglePin(BOOT_LED_GPIO_Port,GPIO_PIN_14);LedTimerCnt = 0;}
     while (TerminalQueue.data > 0 && UartRxTimerCnt > 100) GetDataFromUartQueue(&hTerminal);
-    if(AdcTimerCnt > 3000){
+    if(AdcTimerCnt > 5000){
         HAL_ADC_Start_DMA(&hadc1, (uint32_t*)ADCvalue, 14);  
-        for(uint8_t i = 0; i< ADC_EA; i++){
-            Prev_data[INDEX_DET_1_8G_DL_IN_H + i]     = ((ADCvalue[i] & 0x0F00) >> 8);
-            Prev_data[INDEX_DET_1_8G_DL_IN_L + i] = (ADCvalue[i] & 0x00FF);
+        for(uint8_t i = 0; i< ADC_EA; i += 2 ){
+            Prev_data[INDEX_DET_1_8G_DL_IN_H + i]     = (uint16_t)((ADCvalue[i] & 0xFF00) >> 8);
+            Prev_data[INDEX_DET_1_8G_DL_IN_L + i]     = (uint16_t)(ADCvalue[i] & 0x00FF);
 //            printf("Prev_data[INDEX_DET_1_8G_DL_IN_H + i] : %x\r\n",Prev_data[INDEX_DET_1_8G_DL_IN_H + i]);
-//            printf("Prev_data[INDEX_DET_1_8G_DL_IN_L + i] : %x\r\n",Prev_data[INDEX_DET_1_8G_DL_IN_L + i]);            
+//            printf("Prev_data[INDEX_DET_1_8G_DL_IN_L + i] : %x\r\n",Prev_data[INDEX_DET_1_8G_DL_IN_L]);            
         }
+//        for(int i = 0; i < 14; i++)
+//            printf("\r\nYJ[%d] : %x \r\n",i,ADCvalue[i]);
+//        HAL_Delay(3000);
+        RF_Status_Get();
 #if 1 // PYJ.2019.07.29_BEGIN -- 
 //        printf("====================================\r\n");
 //            for(uint8_t i = 0; i< ADC_EA; i++){
-//                printf("%x ",ADCvalue[i]);
+//                printf("%x",ADCvalue[0]);
+//                printf("\r\n");
 //                printf("%d",ADCvalue[i]);
 //                printf("\r\n");
 //            }

Src/zig_operate.c

@@ -221,19 +221,23 @@ PLL_Setting_st Pll_3_5_H = {
        PLL_EN_3_5G_L_Pin,
  };
 void RF_Status_Get(void){
+//    printf("\r\nYJ2 : Prev_data[INDEX_DET_1_8G_DL_IN_L ] : %x\r\n",Prev_data[INDEX_DET_1_8G_DL_IN_L]);            
     uint8_t data[10];
     Prev_data[INDEX_BLUE_HEADER]   = BLUECELL_HEADER;
     Prev_data[INDEX_BLUE_TYPE]     = TYPE_BLUECELL_GET;
-    Prev_data[INDEX_BLUE_LENGTH]   = INDEX__T_SYNC_UL + 1;
+    Prev_data[INDEX_BLUE_LENGTH]   = INDEX_BLUE_EOF - 3;
     Prev_data[INDEX_BLUE_CRCINDEX] = INDEX_BLUE_CRC;
     Prev_data[INDEX_BLUE_EOF] = BLUECELL_TAILER;    
     HAL_UART_Transmit_DMA(&huart1,&Prev_data[INDEX_BLUE_HEADER],INDEX_BLUE_EOF + 1); 
+//    printf("\r\nYJ : %x",ADCvalue[0]);
+//    printf("\r\n");
 
 }
 
 void RF_Operate(uint8_t* data_buf){
     uint16_t temp_val = 0;
     uint8_t  ADC_Modify = 0;
+    ADF4153_R_N_Reg_st temp_reg;
 
     if(Prev_data[INDEX_ATT_1_8G_DL1] != data_buf[INDEX_ATT_1_8G_DL1]){
         
@@ -367,15 +371,19 @@ void RF_Operate(uint8_t* data_buf){
         (Prev_data[INDEX_PLL_3_5G_DL_H] = data_buf[INDEX_PLL_3_5G_DL_H]);
         (Prev_data[INDEX_PLL_3_5G_DL_L] = data_buf[INDEX_PLL_3_5G_DL_L]);
         temp_val = (data_buf[INDEX_PLL_3_5G_DL_H] << 8) | (data_buf[INDEX_PLL_3_5G_DL_L]);
-        ADF4153_Module_Ctrl(Pll_3_5_L,ADF4153_Freq_Calc(3465500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING),0x14be81,0x13c2,0x3);
+        printf("PLL CTRL \r\n");
+        temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
+        ADF4153_Module_Ctrl(Pll_3_5_L,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
     }
     if((Prev_data[INDEX_PLL_3_5G_UL_H] != data_buf[INDEX_PLL_3_5G_UL_H])
         && (Prev_data[INDEX_PLL_3_5G_UL_L] != data_buf[INDEX_PLL_3_5G_UL_L])){
-
+        printf("PLL CTRL \r\n");
         (Prev_data[INDEX_PLL_3_5G_UL_H] = data_buf[INDEX_PLL_3_5G_UL_H]);
         (Prev_data[INDEX_PLL_3_5G_UL_L] = data_buf[INDEX_PLL_3_5G_UL_L]);
         temp_val = (data_buf[INDEX_PLL_3_5G_UL_H] << 8) | (data_buf[INDEX_PLL_3_5G_UL_L]);
-        ADF4153_Module_Ctrl(Pll_3_5_H,ADF4153_Freq_Calc(3934500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING),0x14be81,0x13c2,0x3);
+        temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
+        ADF4153_Module_Ctrl(Pll_3_5_H,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
+
     }
     if(Prev_data[INDEX_PLL_LD_6_BIT] != data_buf[INDEX_PLL_LD_6_BIT]){
 
@@ -521,8 +529,9 @@ void RF_Operate(uint8_t* data_buf){
         printf("POWER : %d \r\n",Prev_data[INDEX_PLL_ON_OFF_3_5G_H]);
         if(data_buf[INDEX_PLL_ON_OFF_3_5G_H]){
             printf("PLL CTRL START !! \r\n");
-            ADF4153_Module_Ctrl(Pll_3_5_H,ADF4153_Freq_Calc(3934500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING),0x14be81,0x13c2,0x3);
-
+//            ADF4153_Init();
+            temp_reg = ADF4153_Freq_Calc(3934500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);
+            ADF4153_Module_Ctrl(Pll_3_5_H,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
         }
     }
     if(Prev_data[INDEX_PLL_ON_OFF_3_5G_L] != data_buf[INDEX_PLL_ON_OFF_3_5G_L]){
@@ -532,19 +541,22 @@ void RF_Operate(uint8_t* data_buf){
         printf("POWER : %d \r\n",Prev_data[INDEX_PLL_ON_OFF_3_5G_L]);        
         if(data_buf[INDEX_PLL_ON_OFF_3_5G_L]){
             printf("PLL CTRL START !! \r\n");
-            ADF4153_Module_Ctrl(Pll_3_5_L,ADF4153_Freq_Calc(3465500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING),0x14be81,0x13c2,0x3);
+            temp_reg = ADF4153_Freq_Calc(3465500000,ADF4153_REFIN,ADF4153_RCOUNTER,ADF4153_CHANNEL_SPACING);            
+            ADF4153_Module_Ctrl(Pll_3_5_L,temp_reg.N_reg,temp_reg.R_reg,0x13c2,0x3);
         }
-
     }
 
     if(Prev_data[INDEX_T_SYNC_DL] != data_buf[INDEX_T_SYNC_DL]){
         Prev_data[INDEX_T_SYNC_DL] = data_buf[INDEX_T_SYNC_DL];
+        Power_ON_OFF_Ctrl(INDEX_T_SYNC_DL,data_buf[INDEX_T_SYNC_DL]);
     }
     if(Prev_data[INDEX__T_SYNC_DL] != data_buf[INDEX__T_SYNC_DL]){
         Prev_data[INDEX__T_SYNC_DL] = data_buf[INDEX__T_SYNC_DL];
+        Power_ON_OFF_Ctrl(INDEX__T_SYNC_DL,data_buf[INDEX__T_SYNC_DL]);
     }
     if(Prev_data[INDEX_T_SYNC_UL] != data_buf[INDEX_T_SYNC_UL]){
         Prev_data[INDEX_T_SYNC_UL] = data_buf[INDEX_T_SYNC_UL];
+        Power_ON_OFF_Ctrl(INDEX_T_SYNC_UL,data_buf[INDEX_T_SYNC_UL]);
     }
     if(Prev_data[INDEX__T_SYNC_UL] != data_buf[INDEX__T_SYNC_UL]){
         Prev_data[INDEX__T_SYNC_UL] = data_buf[INDEX__T_SYNC_UL];
@@ -653,9 +665,7 @@ bool RF_Ctrl_Main(uint8_t* data_buf){
 //        halSynSetFreq(1455000000);        
         break;
     case TYPE_BLUECELL_GET:
-#ifdef DEBUG_PRINT
         printf("\r\nTYPE_BLUECELL_GET : \r\n");
-#endif /* DEBUG_PRINT */
         RF_Status_Get();
         break;
  

insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/PE43711(3826).c

@@ -0,0 +1,126 @@
+/*
+ * PE43711.c
+ *
+ *  Created on: 2019. 6. 28.
+ *      Author: parkyj
+ */
+ #include "PE43711.h"
+#if 1 // PYJ.2019.07.26_BEGIN -- 
+#define ATTEN_3_5G_Initial_Val 0
+void PE43711_ALL_atten_ctrl(ALL_PE43711_st ATT);
+
+void PE43711_atten_ctrl(PE43711_st ATT ,uint8_t data);
+ALL_PE43711_st ALL_ATT_3_5G;
+
+PE43711_st ATT_3_5G_DL ={
+    ATT_CLK_3_5G_GPIO_Port,
+    ATT_CLK_3_5G_Pin,
+    ATT_DATA_3_5G_DL_GPIO_Port,
+    ATT_DATA_3_5G_DL_Pin,
+    ATT_EN_3_5G_GPIO_Port,
+    ATT_EN_3_5G_Pin,
+}; 
+PE43711_st ATT_3_5G_UL ={
+    ATT_CLK_3_5G_GPIO_Port,
+    ATT_CLK_3_5G_Pin,
+    ATT_DATA_3_5G_UL_GPIO_Port,
+    ATT_DATA_3_5G_UL_Pin,
+    ATT_EN_3_5G_GPIO_Port,
+    ATT_EN_3_5G_Pin,
+}; 
+PE43711_st ATT_3_5G_COM1={
+    ATT_CLK_3_5G_GPIO_Port,
+    ATT_CLK_3_5G_Pin,
+    ATT_DATA_3_5G_COM1_GPIO_Port,
+    ATT_DATA_3_5G_COM1_Pin,
+    ATT_EN_3_5G_GPIO_Port,
+    ATT_EN_3_5G_Pin,
+}; 
+PE43711_st ATT_3_5G_COM2={
+    ATT_CLK_3_5G_GPIO_Port,
+    ATT_CLK_3_5G_Pin,
+    ATT_DATA_3_5G_COM2_GPIO_Port,
+    ATT_DATA_3_5G_COM2_Pin,
+    ATT_EN_3_5G_GPIO_Port,
+    ATT_EN_3_5G_Pin,
+}; 
+PE43711_st ATT_3_5G_COM3={
+    ATT_CLK_3_5G_GPIO_Port,
+    ATT_CLK_3_5G_Pin,
+    ATT_DATA_3_5G_COM3_GPIO_Port,
+    ATT_DATA_3_5G_COM3_Pin,
+    ATT_EN_3_5G_GPIO_Port,
+    ATT_EN_3_5G_Pin,
+}; 
+void PE43711_PinInit(void){
+    ALL_ATT_3_5G.ATT0 = ATT_3_5G_DL;
+    ALL_ATT_3_5G.ATT1 = ATT_3_5G_UL;
+    ALL_ATT_3_5G.ATT2 = ATT_3_5G_COM1;
+    ALL_ATT_3_5G.ATT3 = ATT_3_5G_COM2;
+    ALL_ATT_3_5G.ATT4 = ATT_3_5G_COM3;
+    ALL_ATT_3_5G.data0 = ATTEN_3_5G_Initial_Val;    
+    ALL_ATT_3_5G.data1 = ATTEN_3_5G_Initial_Val;
+    ALL_ATT_3_5G.data2 = ATTEN_3_5G_Initial_Val;
+    ALL_ATT_3_5G.data3 = ATTEN_3_5G_Initial_Val;
+    ALL_ATT_3_5G.data4 = ATTEN_3_5G_Initial_Val;    
+    PE43711_ALL_atten_ctrl(ALL_ATT_3_5G);
+}
+#endif // PYJ.2019.07.26_END -- 
+void Bit_Compare(PE43711_st ATT,uint8_t data,uint8_t Shift_Index){
+    if(data & (0x01 << Shift_Index)){
+        HAL_GPIO_WritePin(ATT.DATA_PORT,ATT.DATA_PIN,GPIO_PIN_SET);//DATA
+    }
+    else{
+        HAL_GPIO_WritePin(ATT.DATA_PORT,ATT.DATA_PIN,GPIO_PIN_RESET);//DATA
+    }
+}
+void PE43711_ALL_atten_ctrl(ALL_PE43711_st ATT){
+    HAL_GPIO_WritePin(ATT.ATT0.LE_PORT,ATT.ATT0.LE_PIN,GPIO_PIN_RESET);
+    Pol_Delay_us(10);
+    printf("why not? \r\n");
+    for(uint8_t i = 0; i < 8; i++){
+        Bit_Compare(ATT.ATT0,ATT.data0,i);
+        Bit_Compare(ATT.ATT1,ATT.data1,i);
+        Bit_Compare(ATT.ATT2,ATT.data2,i);
+        Bit_Compare(ATT.ATT3,ATT.data3,i);
+        Bit_Compare(ATT.ATT4,ATT.data4,i);
+		HAL_GPIO_WritePin(ATT.ATT0.CLK_PORT,ATT.ATT0.CLK_PIN,GPIO_PIN_SET);//CLOCK
+		Pol_Delay_us(10);
+		HAL_GPIO_WritePin(ATT.ATT0.CLK_PORT,ATT.ATT0.CLK_PIN,GPIO_PIN_RESET);//CLOCK
+    }
+    HAL_GPIO_WritePin(GPIOB,GPIO_PIN_15,GPIO_PIN_RESET);//DATA
+    HAL_GPIO_WritePin(ATT.ATT0.LE_PORT,ATT.ATT0.LE_PIN,GPIO_PIN_SET);//LE
+    Pol_Delay_us(10);
+    HAL_GPIO_WritePin(ATT.ATT0.LE_PORT,ATT.ATT0.LE_PIN,GPIO_PIN_RESET);
+}
+
+void PE43711_atten_ctrl(PE43711_st ATT ,uint8_t data){
+    uint8_t i = 0;
+    uint8_t temp = 0;
+    data = 4 * data;
+    temp = (uint8_t)data;
+    
+    HAL_GPIO_WritePin(ATT.LE_PORT,ATT.LE_PIN,GPIO_PIN_RESET);
+    Pol_Delay_us(10);
+    for(i = 0; i < 8; i++){
+        if((uint8_t)temp & 0x01){
+           HAL_GPIO_WritePin(ATT.DATA_PORT,ATT.DATA_PIN,GPIO_PIN_SET);//DATA
+        }
+           else{
+           HAL_GPIO_WritePin(ATT.DATA_PORT,ATT.DATA_PIN,GPIO_PIN_RESET);//DATA
+           }
+
+		HAL_GPIO_WritePin(ATT.CLK_PORT,ATT.CLK_PIN,GPIO_PIN_SET);//CLOCK
+		Pol_Delay_us(10);
+		HAL_GPIO_WritePin(ATT.CLK_PORT,ATT.CLK_PIN,GPIO_PIN_RESET);//CLOCK
+		Pol_Delay_us(10);
+		temp >>= 1;
+    }
+    
+	HAL_GPIO_WritePin(ATT.CLK_PORT,ATT.CLK_PIN,GPIO_PIN_RESET);//CLOCK
+    HAL_GPIO_WritePin(ATT.DATA_PORT,ATT.DATA_PIN,GPIO_PIN_RESET);//DATA
+    HAL_Delay(5);
+    HAL_GPIO_WritePin(ATT.LE_PORT,ATT.LE_PIN,GPIO_PIN_SET);//LE
+    Pol_Delay_us(10);
+    HAL_GPIO_WritePin(ATT.LE_PORT,ATT.LE_PIN,GPIO_PIN_RESET);
+}

insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/pll_4113(838).h

@@ -0,0 +1,28 @@
+/**************************************************************************************************
+  Filename:       hal_adf4113.h
+  Revised:        $Date: 2013-11-17 $
+  Revision:       $Revision: $
+  Description:    This file contains the interface to the ADF4113 frequency synthesizer.
+**************************************************************************************************/
+#ifndef HAL_ADF4113_H
+#define HAL_ADF4113_H
+#include "main.h"
+typedef struct _PLL_Setting_st{
+    GPIO_TypeDef * PLL_CLK_PORT;
+    uint16_t       PLL_CLK_PIN;
+    GPIO_TypeDef * PLL_DATA_PORT;
+    uint16_t       PLL_DATA_PIN;
+    GPIO_TypeDef * PLL_ENABLE_PORT;
+    uint16_t       PLL_ENABLE_PIN;
+} PLL_Setting_st;
+PLL_Setting_st ADF4113_1_8G_DL;
+PLL_Setting_st ADF4113_1_8G_UL;
+PLL_Setting_st ADF4113_2_1G_DL;
+PLL_Setting_st ADF4113_2_1G_UL;
+
+uint8_t halSynSetFreq(uint32_t rf_Freq);
+void ADF4113_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2);
+
+//void ADF4113_Module_Ctrl(PLL_Setting_st pll,uint32_t R0,uint32_t R1,uint32_t R2);
+
+#endif

insight/STM32F103_ATTEN_PLL_Zig.si4project/STM32F103_ATTEN_PLL_Zig.SearchResults

@@ -1,180 +1,2 @@
----- cmd Matches (273 in 7 files) ----
-includes.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) line 96 : void Power_ON_OFF_Ctrl(uint8_t type,uint8_t cmd){
-Power_ON_OFF_Ctrl in includes.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :     printf("\r\ntype : %s cmd : %d\r\n",Bluecell_Prot_IndexStr[type - 4],cmd);
-Power_ON_OFF_Ctrl in includes.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :             if(cmd)
-Power_ON_OFF_Ctrl in includes.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :             if(cmd)
-Power_ON_OFF_Ctrl in includes.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :             if(cmd)
-Power_ON_OFF_Ctrl in includes.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :             if(cmd)
-Power_ON_OFF_Ctrl in includes.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :             if(cmd)
-Power_ON_OFF_Ctrl in includes.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :             if(cmd)
-Power_ON_OFF_Ctrl in includes.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :             if(cmd)
-Power_ON_OFF_Ctrl in includes.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :             if(cmd)
-Power_ON_OFF_Ctrl in includes.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :             if(cmd)
-Power_ON_OFF_Ctrl in includes.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :             if(cmd)
-Power_ON_OFF_Ctrl in includes.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :             if(cmd){
-Power_ON_OFF_Ctrl in includes.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :             printf("TDD SYNC OPERATE ; %d\r\n",cmd);
-includes.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Inc) line 25 : void Power_ON_OFF_Ctrl(uint8_t type,uint8_t cmd);
-{anonSDIO_TypeDef} in stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) :   __IO uint32_t CMD;
-{anonSDIO_TypeDef} in stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) :   __I uint32_t RESPCMD;
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5568 : #define SDIO_ARG_CMDARG_Pos                 (0U)                               
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5569 : #define SDIO_ARG_CMDARG_Msk                 (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5570 : #define SDIO_ARG_CMDARG                     SDIO_ARG_CMDARG_Msk                /*!< Command argument */
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5572 : /*******************  Bit definition for SDIO_CMD register  *******************/
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5573 : #define SDIO_CMD_CMDINDEX_Pos               (0U)                               
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5574 : #define SDIO_CMD_CMDINDEX_Msk               (0x3FU << SDIO_CMD_CMDINDEX_Pos)   /*!< 0x0000003F */
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5575 : #define SDIO_CMD_CMDINDEX                   SDIO_CMD_CMDINDEX_Msk              /*!< Command Index */
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5577 : #define SDIO_CMD_WAITRESP_Pos               (6U)                               
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5578 : #define SDIO_CMD_WAITRESP_Msk               (0x3U << SDIO_CMD_WAITRESP_Pos)    /*!< 0x000000C0 */
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5579 : #define SDIO_CMD_WAITRESP                   SDIO_CMD_WAITRESP_Msk              /*!< WAITRESP[1:0] bits (Wait for response bits) */
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5580 : #define SDIO_CMD_WAITRESP_0                 (0x1U << SDIO_CMD_WAITRESP_Pos)    /*!< 0x0040 */
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5581 : #define SDIO_CMD_WAITRESP_1                 (0x2U << SDIO_CMD_WAITRESP_Pos)    /*!< 0x0080 */
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5583 : #define SDIO_CMD_WAITINT_Pos                (8U)                               
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5584 : #define SDIO_CMD_WAITINT_Msk                (0x1U << SDIO_CMD_WAITINT_Pos)     /*!< 0x00000100 */
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5585 : #define SDIO_CMD_WAITINT                    SDIO_CMD_WAITINT_Msk               /*!< CPSM Waits for Interrupt Request */
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5586 : #define SDIO_CMD_WAITPEND_Pos               (9U)                               
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5587 : #define SDIO_CMD_WAITPEND_Msk               (0x1U << SDIO_CMD_WAITPEND_Pos)    /*!< 0x00000200 */
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5588 : #define SDIO_CMD_WAITPEND                   SDIO_CMD_WAITPEND_Msk              /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5589 : #define SDIO_CMD_CPSMEN_Pos                 (10U)                              
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5590 : #define SDIO_CMD_CPSMEN_Msk                 (0x1U << SDIO_CMD_CPSMEN_Pos)      /*!< 0x00000400 */
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5591 : #define SDIO_CMD_CPSMEN                     SDIO_CMD_CPSMEN_Msk                /*!< Command path state machine (CPSM) Enable bit */
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5592 : #define SDIO_CMD_SDIOSUSPEND_Pos            (11U)                              
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5593 : #define SDIO_CMD_SDIOSUSPEND_Msk            (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5594 : #define SDIO_CMD_SDIOSUSPEND                SDIO_CMD_SDIOSUSPEND_Msk           /*!< SD I/O suspend command */
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5595 : #define SDIO_CMD_ENCMDCOMPL_Pos             (12U)                              
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5596 : #define SDIO_CMD_ENCMDCOMPL_Msk             (0x1U << SDIO_CMD_ENCMDCOMPL_Pos)  /*!< 0x00001000 */
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5597 : #define SDIO_CMD_ENCMDCOMPL                 SDIO_CMD_ENCMDCOMPL_Msk            /*!< Enable CMD completion */
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5598 : #define SDIO_CMD_NIEN_Pos                   (13U)                              
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5599 : #define SDIO_CMD_NIEN_Msk                   (0x1U << SDIO_CMD_NIEN_Pos)        /*!< 0x00002000 */
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5600 : #define SDIO_CMD_NIEN                       SDIO_CMD_NIEN_Msk                  /*!< Not Interrupt Enable */
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5601 : #define SDIO_CMD_CEATACMD_Pos               (14U)                              
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5602 : #define SDIO_CMD_CEATACMD_Msk               (0x1U << SDIO_CMD_CEATACMD_Pos)    /*!< 0x00004000 */
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5603 : #define SDIO_CMD_CEATACMD                   SDIO_CMD_CEATACMD_Msk              /*!< CE-ATA command */
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5605 : /*****************  Bit definition for SDIO_RESPCMD register  *****************/
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5606 : #define SDIO_RESPCMD_RESPCMD_Pos            (0U)                               
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5607 : #define SDIO_RESPCMD_RESPCMD_Msk            (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5608 : #define SDIO_RESPCMD_RESPCMD                SDIO_RESPCMD_RESPCMD_Msk           /*!< Response command index */
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5704 : #define SDIO_STA_CMDREND_Pos                (6U)                               
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5705 : #define SDIO_STA_CMDREND_Msk                (0x1U << SDIO_STA_CMDREND_Pos)     /*!< 0x00000040 */
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5706 : #define SDIO_STA_CMDREND                    SDIO_STA_CMDREND_Msk               /*!< Command response received (CRC check passed) */
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5707 : #define SDIO_STA_CMDSENT_Pos                (7U)                               
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5708 : #define SDIO_STA_CMDSENT_Msk                (0x1U << SDIO_STA_CMDSENT_Pos)     /*!< 0x00000080 */
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5709 : #define SDIO_STA_CMDSENT                    SDIO_STA_CMDSENT_Msk               /*!< Command sent (no response required) */
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5719 : #define SDIO_STA_CMDACT_Pos                 (11U)                              
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5720 : #define SDIO_STA_CMDACT_Msk                 (0x1U << SDIO_STA_CMDACT_Pos)      /*!< 0x00000800 */
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5721 : #define SDIO_STA_CMDACT                     SDIO_STA_CMDACT_Msk                /*!< Command transfer in progress */
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5757 : #define SDIO_STA_CEATAEND                   SDIO_STA_CEATAEND_Msk              /*!< CE-ATA command completion signal received for CMD61 */
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5778 : #define SDIO_ICR_CMDRENDC_Pos               (6U)                               
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5779 : #define SDIO_ICR_CMDRENDC_Msk               (0x1U << SDIO_ICR_CMDRENDC_Pos)    /*!< 0x00000040 */
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5780 : #define SDIO_ICR_CMDRENDC                   SDIO_ICR_CMDRENDC_Msk              /*!< CMDREND flag clear bit */
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5781 : #define SDIO_ICR_CMDSENTC_Pos               (7U)                               
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5782 : #define SDIO_ICR_CMDSENTC_Msk               (0x1U << SDIO_ICR_CMDSENTC_Pos)    /*!< 0x00000080 */
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5783 : #define SDIO_ICR_CMDSENTC                   SDIO_ICR_CMDSENTC_Msk              /*!< CMDSENT flag clear bit */
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5819 : #define SDIO_MASK_CMDRENDIE_Pos             (6U)                               
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5820 : #define SDIO_MASK_CMDRENDIE_Msk             (0x1U << SDIO_MASK_CMDRENDIE_Pos)  /*!< 0x00000040 */
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5821 : #define SDIO_MASK_CMDRENDIE                 SDIO_MASK_CMDRENDIE_Msk            /*!< Command Response Received Interrupt Enable */
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5822 : #define SDIO_MASK_CMDSENTIE_Pos             (7U)                               
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5823 : #define SDIO_MASK_CMDSENTIE_Msk             (0x1U << SDIO_MASK_CMDSENTIE_Pos)  /*!< 0x00000080 */
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5824 : #define SDIO_MASK_CMDSENTIE                 SDIO_MASK_CMDSENTIE_Msk            /*!< Command Sent Interrupt Enable */
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5834 : #define SDIO_MASK_CMDACTIE_Pos              (11U)                              
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5835 : #define SDIO_MASK_CMDACTIE_Msk              (0x1U << SDIO_MASK_CMDACTIE_Pos)   /*!< 0x00000800 */
-stm32f103xe.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\CMSIS\Device\ST\STM32F1xx\Include) line 5836 : #define SDIO_MASK_CMDACTIE                  SDIO_MASK_CMDACTIE_Msk             /*!< Command Acting Interrupt Enable */
-HAL_TIM_OC_Start in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-HAL_TIM_OC_Stop in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-HAL_TIM_OC_Start_IT in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-HAL_TIM_OC_Stop_IT in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-HAL_TIM_OC_Start_DMA in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-HAL_TIM_OC_Stop_DMA in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-HAL_TIM_PWM_Start in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-HAL_TIM_PWM_Stop in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-HAL_TIM_PWM_Start_IT in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-HAL_TIM_PWM_Stop_IT in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-HAL_TIM_PWM_Start_DMA in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-HAL_TIM_PWM_Stop_DMA in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-HAL_TIM_IC_Start in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-HAL_TIM_IC_Stop in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-HAL_TIM_IC_Start_IT in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-HAL_TIM_IC_Stop_IT in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-HAL_TIM_IC_Start_DMA in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-HAL_TIM_IC_Stop_DMA in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-HAL_TIM_OnePulse_Start in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-HAL_TIM_OnePulse_Start in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-HAL_TIM_OnePulse_Stop in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-HAL_TIM_OnePulse_Stop in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-HAL_TIM_OnePulse_Start_IT in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-HAL_TIM_OnePulse_Start_IT in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-HAL_TIM_OnePulse_Stop_IT in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-HAL_TIM_OnePulse_Stop_IT in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-HAL_TIM_Encoder_Start in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-HAL_TIM_Encoder_Start in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-HAL_TIM_Encoder_Start in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-HAL_TIM_Encoder_Start in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-HAL_TIM_Encoder_Stop in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-HAL_TIM_Encoder_Stop in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-HAL_TIM_Encoder_Stop in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-HAL_TIM_Encoder_Stop in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-HAL_TIM_Encoder_Start_IT in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-HAL_TIM_Encoder_Start_IT in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-HAL_TIM_Encoder_Start_IT in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-HAL_TIM_Encoder_Start_IT in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-HAL_TIM_Encoder_Stop_IT in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-HAL_TIM_Encoder_Stop_IT in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-HAL_TIM_Encoder_Stop_IT in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-HAL_TIM_Encoder_Stop_IT in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-HAL_TIM_Encoder_Start_DMA in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-HAL_TIM_Encoder_Start_DMA in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-HAL_TIM_Encoder_Start_DMA in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-HAL_TIM_Encoder_Start_DMA in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-HAL_TIM_Encoder_Stop_DMA in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-HAL_TIM_Encoder_Stop_DMA in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-HAL_TIM_Encoder_Stop_DMA in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-HAL_TIM_Encoder_Stop_DMA in stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-stm32f1xx_hal_tim.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) line 5390 : void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
-stm32f1xx_hal_tim.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Inc) line 1173 : void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
-stm32f1xx_hal_tim_ex.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) line 123 : static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
-HAL_TIMEx_HallSensor_Start in stm32f1xx_hal_tim_ex.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-HAL_TIMEx_HallSensor_Stop in stm32f1xx_hal_tim_ex.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-HAL_TIMEx_HallSensor_Start_IT in stm32f1xx_hal_tim_ex.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-HAL_TIMEx_HallSensor_Stop_IT in stm32f1xx_hal_tim_ex.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-HAL_TIMEx_HallSensor_Start_DMA in stm32f1xx_hal_tim_ex.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-HAL_TIMEx_HallSensor_Stop_DMA in stm32f1xx_hal_tim_ex.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-HAL_TIMEx_OCN_Start in stm32f1xx_hal_tim_ex.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-HAL_TIMEx_OCN_Stop in stm32f1xx_hal_tim_ex.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-HAL_TIMEx_OCN_Start_IT in stm32f1xx_hal_tim_ex.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-HAL_TIMEx_OCN_Stop_IT in stm32f1xx_hal_tim_ex.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-HAL_TIMEx_OCN_Start_DMA in stm32f1xx_hal_tim_ex.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-HAL_TIMEx_OCN_Stop_DMA in stm32f1xx_hal_tim_ex.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-HAL_TIMEx_PWMN_Start in stm32f1xx_hal_tim_ex.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-HAL_TIMEx_PWMN_Stop in stm32f1xx_hal_tim_ex.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-HAL_TIMEx_PWMN_Start_IT in stm32f1xx_hal_tim_ex.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-HAL_TIMEx_PWMN_Stop_IT in stm32f1xx_hal_tim_ex.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-HAL_TIMEx_PWMN_Start_DMA in stm32f1xx_hal_tim_ex.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-HAL_TIMEx_PWMN_Stop_DMA in stm32f1xx_hal_tim_ex.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-HAL_TIMEx_OnePulseN_Start in stm32f1xx_hal_tim_ex.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
-HAL_TIMEx_OnePulseN_Stop in stm32f1xx_hal_tim_ex.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
-HAL_TIMEx_OnePulseN_Start_IT in stm32f1xx_hal_tim_ex.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
-HAL_TIMEx_OnePulseN_Stop_IT in stm32f1xx_hal_tim_ex.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) :   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
-stm32f1xx_hal_tim_ex.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Src) line 1743 : static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
-stm32_hal_legacy.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Inc\Legacy) line 665 : #define CF_STATUS_CMD                 ATA_STATUS_CMD          
-stm32_hal_legacy.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Inc\Legacy) line 666 : #define CF_STATUS_CMD_ALTERNATE       ATA_STATUS_CMD_ALTERNATE
-stm32_hal_legacy.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Inc\Legacy) line 670 : #define CF_READ_SECTOR_CMD            ATA_READ_SECTOR_CMD 
-stm32_hal_legacy.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Inc\Legacy) line 671 : #define CF_WRITE_SECTOR_CMD           ATA_WRITE_SECTOR_CMD
-stm32_hal_legacy.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Inc\Legacy) line 672 : #define CF_ERASE_SECTOR_CMD           ATA_ERASE_SECTOR_CMD
-stm32_hal_legacy.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Inc\Legacy) line 673 : #define CF_IDENTIFY_CMD               ATA_IDENTIFY_CMD
-stm32_hal_legacy.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Inc\Legacy) line 1079 : #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
-stm32_hal_legacy.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Inc\Legacy) line 1081 : #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
-stm32_hal_legacy.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Inc\Legacy) line 1084 : #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
-stm32_hal_legacy.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Inc\Legacy) line 1086 : #define HAL_ADC_EnableBuffer_Cmd(cmd)  (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
-stm32_hal_legacy.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Inc\Legacy) line 1087 : #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ?  HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
-stm32_hal_legacy.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Inc\Legacy) line 1115 : #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
-stm32_hal_legacy.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Inc\Legacy) line 1810 : #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
-stm32_hal_legacy.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Inc\Legacy) line 2370 : #define __CCMDATARAMEN_CLK_ENABLE  __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
-stm32_hal_legacy.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Inc\Legacy) line 2371 : #define __CCMDATARAMEN_CLK_DISABLE  __HAL_RCC_CCMDATARAMEN_CLK_DISABLE  
-stm32_hal_legacy.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Inc\Legacy) line 2928 : #define SD_CMD_SD_APP_STAUS         SD_CMD_SD_APP_STATUS
-stm32_hal_legacy.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Inc\Legacy) line 2935 : #define  SD_CMD_SDMMC_SEN_OP_COND   SD_CMD_SDIO_SEN_OP_COND   
-stm32_hal_legacy.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Inc\Legacy) line 2936 : #define  SD_CMD_SDMMC_RW_DIRECT     SD_CMD_SDIO_RW_DIRECT     
-stm32_hal_legacy.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Inc\Legacy) line 2937 : #define  SD_CMD_SDMMC_RW_EXTENDED   SD_CMD_SDIO_RW_EXTENDED   
-stm32_hal_legacy.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Inc\Legacy) line 2949 : #define  SDMMC_CMD0TIMEOUT          SDIO_CMD0TIMEOUT	       
-stm32_hal_legacy.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Inc\Legacy) line 2961 : #define  SD_CMD_SDIO_SEN_OP_COND    SD_CMD_SDMMC_SEN_OP_COND
-stm32_hal_legacy.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Inc\Legacy) line 2962 : #define  SD_CMD_SDIO_RW_DIRECT      SD_CMD_SDMMC_RW_DIRECT
-stm32_hal_legacy.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Inc\Legacy) line 2963 : #define  SD_CMD_SDIO_RW_EXTENDED    SD_CMD_SDMMC_RW_EXTENDED
-stm32_hal_legacy.h (D:\workspace\STM32F103_ATTEN_PLL_Zig\Drivers\STM32F1xx_HAL_Driver\Inc\Legacy) line 2975 : #define  SDIO_CMD0TIMEOUT	          SDMMC_CMD0TIMEOUT
+---- why not? Matches (1 in 1 files) ----
+PE43711_ALL_atten_ctrl in PE43711.c (D:\workspace\STM32F103_ATTEN_PLL_Zig\Src) :     printf("why not? \r\n");