STM32F103ZET_JDASMBIC/Debug/STM32F103_ATTEN_PLL_Zig.list

STM32F103_ATTEN_PLL_Zig.elf:     file format elf32-littlearm

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .isr_vector   000001e4  08000000  08000000  00010000  2**0
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  1 .text         000012c4  080001e4  080001e4  000101e4  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  2 .rodata       00000028  080014a8  080014a8  000114a8  2**0
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  3 .init_array   00000004  080014d0  080014d0  000114d0  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  4 .fini_array   00000004  080014d4  080014d4  000114d4  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  5 .data         0000000c  20000000  080014d8  00020000  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  6 .bss          00000120  2000000c  080014e4  0002000c  2**2
                  ALLOC
  7 ._user_heap_stack 00000600  2000012c  080014e4  0002012c  2**0
                  ALLOC
  8 .ARM.attributes 00000029  00000000  00000000  0002000c  2**0
                  CONTENTS, READONLY
  9 .debug_info   0000b89a  00000000  00000000  00020035  2**0
                  CONTENTS, READONLY, DEBUGGING
 10 .debug_abbrev 00001b89  00000000  00000000  0002b8cf  2**0
                  CONTENTS, READONLY, DEBUGGING
 11 .debug_loc    000027db  00000000  00000000  0002d458  2**0
                  CONTENTS, READONLY, DEBUGGING
 12 .debug_aranges 00000530  00000000  00000000  0002fc38  2**3
                  CONTENTS, READONLY, DEBUGGING
 13 .debug_ranges 000006f8  00000000  00000000  00030168  2**3
                  CONTENTS, READONLY, DEBUGGING
 14 .debug_line   0000350f  00000000  00000000  00030860  2**0
                  CONTENTS, READONLY, DEBUGGING
 15 .debug_str    00002152  00000000  00000000  00033d6f  2**0
                  CONTENTS, READONLY, DEBUGGING
 16 .comment      0000007c  00000000  00000000  00035ec1  2**0
                  CONTENTS, READONLY
 17 .debug_frame  00000ce8  00000000  00000000  00035f40  2**2
                  CONTENTS, READONLY, DEBUGGING

Disassembly of section .text:

080001e4 <__do_global_dtors_aux>:
 80001e4:	b510      	push	{r4, lr}
 80001e6:	4c05      	ldr	r4, [pc, #20]	; (80001fc <__do_global_dtors_aux+0x18>)
 80001e8:	7823      	ldrb	r3, [r4, #0]
 80001ea:	b933      	cbnz	r3, 80001fa <__do_global_dtors_aux+0x16>
 80001ec:	4b04      	ldr	r3, [pc, #16]	; (8000200 <__do_global_dtors_aux+0x1c>)
 80001ee:	b113      	cbz	r3, 80001f6 <__do_global_dtors_aux+0x12>
 80001f0:	4804      	ldr	r0, [pc, #16]	; (8000204 <__do_global_dtors_aux+0x20>)
 80001f2:	f3af 8000 	nop.w
 80001f6:	2301      	movs	r3, #1
 80001f8:	7023      	strb	r3, [r4, #0]
 80001fa:	bd10      	pop	{r4, pc}
 80001fc:	2000000c 	.word	0x2000000c
 8000200:	00000000 	.word	0x00000000
 8000204:	08001490 	.word	0x08001490

08000208 <frame_dummy>:
 8000208:	b508      	push	{r3, lr}
 800020a:	4b03      	ldr	r3, [pc, #12]	; (8000218 <frame_dummy+0x10>)
 800020c:	b11b      	cbz	r3, 8000216 <frame_dummy+0xe>
 800020e:	4903      	ldr	r1, [pc, #12]	; (800021c <frame_dummy+0x14>)
 8000210:	4803      	ldr	r0, [pc, #12]	; (8000220 <frame_dummy+0x18>)
 8000212:	f3af 8000 	nop.w
 8000216:	bd08      	pop	{r3, pc}
 8000218:	00000000 	.word	0x00000000
 800021c:	20000010 	.word	0x20000010
 8000220:	08001490 	.word	0x08001490

08000224 <HAL_InitTick>:
  *       implementation  in user file.
  * @param TickPriority Tick interrupt priority.
  * @retval HAL status
  */
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
 8000224:	b538      	push	{r3, r4, r5, lr}
  /* Configure the SysTick to have interrupt in 1ms time basis*/
  if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
 8000226:	4b0e      	ldr	r3, [pc, #56]	; (8000260 <HAL_InitTick+0x3c>)
{
 8000228:	4605      	mov	r5, r0
  if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
 800022a:	7818      	ldrb	r0, [r3, #0]
 800022c:	f44f 737a 	mov.w	r3, #1000	; 0x3e8
 8000230:	fbb3 f3f0 	udiv	r3, r3, r0
 8000234:	4a0b      	ldr	r2, [pc, #44]	; (8000264 <HAL_InitTick+0x40>)
 8000236:	6810      	ldr	r0, [r2, #0]
 8000238:	fbb0 f0f3 	udiv	r0, r0, r3
 800023c:	f000 f88c 	bl	8000358 <HAL_SYSTICK_Config>
 8000240:	4604      	mov	r4, r0
 8000242:	b958      	cbnz	r0, 800025c <HAL_InitTick+0x38>
  {
    return HAL_ERROR;
  }

  /* Configure the SysTick IRQ priority */
  if (TickPriority < (1UL << __NVIC_PRIO_BITS))
 8000244:	2d0f      	cmp	r5, #15
 8000246:	d809      	bhi.n	800025c <HAL_InitTick+0x38>
  {
    HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
 8000248:	4602      	mov	r2, r0
 800024a:	4629      	mov	r1, r5
 800024c:	f04f 30ff 	mov.w	r0, #4294967295
 8000250:	f000 f842 	bl	80002d8 <HAL_NVIC_SetPriority>
    uwTickPrio = TickPriority;
 8000254:	4b04      	ldr	r3, [pc, #16]	; (8000268 <HAL_InitTick+0x44>)
 8000256:	4620      	mov	r0, r4
 8000258:	601d      	str	r5, [r3, #0]
 800025a:	bd38      	pop	{r3, r4, r5, pc}
    return HAL_ERROR;
 800025c:	2001      	movs	r0, #1
    return HAL_ERROR;
  }

  /* Return function status */
  return HAL_OK;
}
 800025e:	bd38      	pop	{r3, r4, r5, pc}
 8000260:	20000000 	.word	0x20000000
 8000264:	20000008 	.word	0x20000008
 8000268:	20000004 	.word	0x20000004

0800026c <HAL_Init>:
  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
 800026c:	4a07      	ldr	r2, [pc, #28]	; (800028c <HAL_Init+0x20>)
{
 800026e:	b508      	push	{r3, lr}
  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
 8000270:	6813      	ldr	r3, [r2, #0]
  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
 8000272:	2003      	movs	r0, #3
  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
 8000274:	f043 0310 	orr.w	r3, r3, #16
 8000278:	6013      	str	r3, [r2, #0]
  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
 800027a:	f000 f81b 	bl	80002b4 <HAL_NVIC_SetPriorityGrouping>
  HAL_InitTick(TICK_INT_PRIORITY);
 800027e:	2000      	movs	r0, #0
 8000280:	f7ff ffd0 	bl	8000224 <HAL_InitTick>
  HAL_MspInit();
 8000284:	f000 ffe2 	bl	800124c <HAL_MspInit>
}
 8000288:	2000      	movs	r0, #0
 800028a:	bd08      	pop	{r3, pc}
 800028c:	40022000 	.word	0x40022000

08000290 <HAL_IncTick>:
  *      implementations in user file.
  * @retval None
  */
__weak void HAL_IncTick(void)
{
  uwTick += uwTickFreq;
 8000290:	4a03      	ldr	r2, [pc, #12]	; (80002a0 <HAL_IncTick+0x10>)
 8000292:	4b04      	ldr	r3, [pc, #16]	; (80002a4 <HAL_IncTick+0x14>)
 8000294:	6811      	ldr	r1, [r2, #0]
 8000296:	781b      	ldrb	r3, [r3, #0]
 8000298:	440b      	add	r3, r1
 800029a:	6013      	str	r3, [r2, #0]
 800029c:	4770      	bx	lr
 800029e:	bf00      	nop
 80002a0:	20000028 	.word	0x20000028
 80002a4:	20000000 	.word	0x20000000

080002a8 <HAL_GetTick>:
  *       implementations in user file.
  * @retval tick value
  */
__weak uint32_t HAL_GetTick(void)
{
  return uwTick;
 80002a8:	4b01      	ldr	r3, [pc, #4]	; (80002b0 <HAL_GetTick+0x8>)
 80002aa:	6818      	ldr	r0, [r3, #0]
}
 80002ac:	4770      	bx	lr
 80002ae:	bf00      	nop
 80002b0:	20000028 	.word	0x20000028

080002b4 <HAL_NVIC_SetPriorityGrouping>:
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
  uint32_t reg_value;
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */

  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
 80002b4:	4a07      	ldr	r2, [pc, #28]	; (80002d4 <HAL_NVIC_SetPriorityGrouping+0x20>)
  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
  reg_value  =  (reg_value                                   |
                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
 80002b6:	0200      	lsls	r0, r0, #8
  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
 80002b8:	68d3      	ldr	r3, [r2, #12]
                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
 80002ba:	f400 60e0 	and.w	r0, r0, #1792	; 0x700
  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
 80002be:	f423 63e0 	bic.w	r3, r3, #1792	; 0x700
 80002c2:	041b      	lsls	r3, r3, #16
 80002c4:	0c1b      	lsrs	r3, r3, #16
 80002c6:	f043 63bf 	orr.w	r3, r3, #100139008	; 0x5f80000
 80002ca:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
  reg_value  =  (reg_value                                   |
 80002ce:	4303      	orrs	r3, r0
  SCB->AIRCR =  reg_value;
 80002d0:	60d3      	str	r3, [r2, #12]
 80002d2:	4770      	bx	lr
 80002d4:	e000ed00 	.word	0xe000ed00

080002d8 <HAL_NVIC_SetPriority>:
  \details Reads the priority grouping field from the NVIC Interrupt Controller.
  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
 */
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
{
  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
 80002d8:	4b17      	ldr	r3, [pc, #92]	; (8000338 <HAL_NVIC_SetPriority+0x60>)
  *         This parameter can be a value between 0 and 15
  *         A lower priority value indicates a higher priority.          
  * @retval None
  */
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{ 
 80002da:	b530      	push	{r4, r5, lr}
 80002dc:	68dc      	ldr	r4, [r3, #12]
 80002de:	f3c4 2402 	ubfx	r4, r4, #8, #3
{
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
  uint32_t PreemptPriorityBits;
  uint32_t SubPriorityBits;

  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
 80002e2:	f1c4 0307 	rsb	r3, r4, #7
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 80002e6:	1d25      	adds	r5, r4, #4
  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
 80002e8:	2b04      	cmp	r3, #4
 80002ea:	bf28      	it	cs
 80002ec:	2304      	movcs	r3, #4
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 80002ee:	2d06      	cmp	r5, #6

  return (
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 80002f0:	f04f 0501 	mov.w	r5, #1
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 80002f4:	bf98      	it	ls
 80002f6:	2400      	movls	r4, #0
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 80002f8:	fa05 f303 	lsl.w	r3, r5, r3
 80002fc:	f103 33ff 	add.w	r3, r3, #4294967295
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 8000300:	bf88      	it	hi
 8000302:	3c03      	subhi	r4, #3
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 8000304:	4019      	ands	r1, r3
 8000306:	40a1      	lsls	r1, r4
           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
 8000308:	fa05 f404 	lsl.w	r4, r5, r4
 800030c:	3c01      	subs	r4, #1
 800030e:	4022      	ands	r2, r4
  if ((int32_t)(IRQn) < 0)
 8000310:	2800      	cmp	r0, #0
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 8000312:	ea42 0201 	orr.w	r2, r2, r1
 8000316:	ea4f 1202 	mov.w	r2, r2, lsl #4
    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 800031a:	bfaf      	iteee	ge
 800031c:	f100 4060 	addge.w	r0, r0, #3758096384	; 0xe0000000
    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8000320:	4b06      	ldrlt	r3, [pc, #24]	; (800033c <HAL_NVIC_SetPriority+0x64>)
 8000322:	f000 000f 	andlt.w	r0, r0, #15
 8000326:	b2d2      	uxtblt	r2, r2
    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8000328:	bfa5      	ittet	ge
 800032a:	b2d2      	uxtbge	r2, r2
 800032c:	f500 4061 	addge.w	r0, r0, #57600	; 0xe100
    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8000330:	541a      	strblt	r2, [r3, r0]
    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8000332:	f880 2300 	strbge.w	r2, [r0, #768]	; 0x300
 8000336:	bd30      	pop	{r4, r5, pc}
 8000338:	e000ed00 	.word	0xe000ed00
 800033c:	e000ed14 	.word	0xe000ed14

08000340 <HAL_NVIC_EnableIRQ>:
  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
 8000340:	2301      	movs	r3, #1
 8000342:	0942      	lsrs	r2, r0, #5
 8000344:	f000 001f 	and.w	r0, r0, #31
 8000348:	fa03 f000 	lsl.w	r0, r3, r0
 800034c:	4b01      	ldr	r3, [pc, #4]	; (8000354 <HAL_NVIC_EnableIRQ+0x14>)
 800034e:	f843 0022 	str.w	r0, [r3, r2, lsl #2]
 8000352:	4770      	bx	lr
 8000354:	e000e100 	.word	0xe000e100

08000358 <HAL_SYSTICK_Config>:
           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
           must contain a vendor-specific implementation of this function.
 */
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
 8000358:	3801      	subs	r0, #1
 800035a:	f1b0 7f80 	cmp.w	r0, #16777216	; 0x1000000
 800035e:	d20a      	bcs.n	8000376 <HAL_SYSTICK_Config+0x1e>
    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8000360:	21f0      	movs	r1, #240	; 0xf0
  {
    return (1UL);                                                   /* Reload value impossible */
  }

  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
 8000362:	4b06      	ldr	r3, [pc, #24]	; (800037c <HAL_SYSTICK_Config+0x24>)
    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8000364:	4a06      	ldr	r2, [pc, #24]	; (8000380 <HAL_SYSTICK_Config+0x28>)
  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
 8000366:	6058      	str	r0, [r3, #4]
    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8000368:	f882 1023 	strb.w	r1, [r2, #35]	; 0x23
  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
 800036c:	2000      	movs	r0, #0
  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
 800036e:	2207      	movs	r2, #7
  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
 8000370:	6098      	str	r0, [r3, #8]
  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
 8000372:	601a      	str	r2, [r3, #0]
 8000374:	4770      	bx	lr
    return (1UL);                                                   /* Reload value impossible */
 8000376:	2001      	movs	r0, #1
  *                  - 1  Function failed.
  */
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
   return SysTick_Config(TicksNumb);
}
 8000378:	4770      	bx	lr
 800037a:	bf00      	nop
 800037c:	e000e010 	.word	0xe000e010
 8000380:	e000ed00 	.word	0xe000ed00

08000384 <HAL_DMA_Init>:
  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
  *               the configuration information for the specified DMA Channel.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
{
 8000384:	b510      	push	{r4, lr}
  uint32_t tmp = 0U;

  /* Check the DMA handle allocation */
  if(hdma == NULL)
 8000386:	2800      	cmp	r0, #0
 8000388:	d032      	beq.n	80003f0 <HAL_DMA_Init+0x6c>
  assert_param(IS_DMA_MODE(hdma->Init.Mode));
  assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));

#if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F100xE) || defined (STM32F105xC) || defined (STM32F107xC)
  /* calculation of the channel index */
  if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
 800038a:	6801      	ldr	r1, [r0, #0]
 800038c:	4b19      	ldr	r3, [pc, #100]	; (80003f4 <HAL_DMA_Init+0x70>)
 800038e:	2414      	movs	r4, #20
 8000390:	4299      	cmp	r1, r3
 8000392:	d825      	bhi.n	80003e0 <HAL_DMA_Init+0x5c>
  {
    /* DMA1 */
    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
 8000394:	4a18      	ldr	r2, [pc, #96]	; (80003f8 <HAL_DMA_Init+0x74>)
    hdma->DmaBaseAddress = DMA1;
 8000396:	f2a3 4307 	subw	r3, r3, #1031	; 0x407
    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
 800039a:	440a      	add	r2, r1
 800039c:	fbb2 f2f4 	udiv	r2, r2, r4
 80003a0:	0092      	lsls	r2, r2, #2
 80003a2:	6402      	str	r2, [r0, #64]	; 0x40
  tmp &= ((uint32_t)~(DMA_CCR_PL    | DMA_CCR_MSIZE  | DMA_CCR_PSIZE  | \
                      DMA_CCR_MINC  | DMA_CCR_PINC   | DMA_CCR_CIRC   | \
                      DMA_CCR_DIR));

  /* Prepare the DMA Channel configuration */
  tmp |=  hdma->Init.Direction        |
 80003a4:	6884      	ldr	r4, [r0, #8]
    hdma->DmaBaseAddress = DMA2;
 80003a6:	63c3      	str	r3, [r0, #60]	; 0x3c
  tmp |=  hdma->Init.Direction        |
 80003a8:	6843      	ldr	r3, [r0, #4]
  tmp = hdma->Instance->CCR;
 80003aa:	680a      	ldr	r2, [r1, #0]
  tmp |=  hdma->Init.Direction        |
 80003ac:	4323      	orrs	r3, r4
          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
 80003ae:	68c4      	ldr	r4, [r0, #12]
  tmp &= ((uint32_t)~(DMA_CCR_PL    | DMA_CCR_MSIZE  | DMA_CCR_PSIZE  | \
 80003b0:	f422 527f 	bic.w	r2, r2, #16320	; 0x3fc0
          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
 80003b4:	4323      	orrs	r3, r4
 80003b6:	6904      	ldr	r4, [r0, #16]
  tmp &= ((uint32_t)~(DMA_CCR_PL    | DMA_CCR_MSIZE  | DMA_CCR_PSIZE  | \
 80003b8:	f022 0230 	bic.w	r2, r2, #48	; 0x30
          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
 80003bc:	4323      	orrs	r3, r4
          hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
 80003be:	6944      	ldr	r4, [r0, #20]
 80003c0:	4323      	orrs	r3, r4
 80003c2:	6984      	ldr	r4, [r0, #24]
 80003c4:	4323      	orrs	r3, r4
          hdma->Init.Mode                | hdma->Init.Priority;
 80003c6:	69c4      	ldr	r4, [r0, #28]
 80003c8:	4323      	orrs	r3, r4
  tmp |=  hdma->Init.Direction        |
 80003ca:	4313      	orrs	r3, r2

  /* Write to DMA Channel CR register */
  hdma->Instance->CCR = tmp;
 80003cc:	600b      	str	r3, [r1, #0]

  /* Initialise the error code */
  hdma->ErrorCode = HAL_DMA_ERROR_NONE;

  /* Initialize the DMA state*/
  hdma->State = HAL_DMA_STATE_READY;
 80003ce:	2201      	movs	r2, #1
  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
 80003d0:	2300      	movs	r3, #0
  hdma->State = HAL_DMA_STATE_READY;
 80003d2:	f880 2021 	strb.w	r2, [r0, #33]	; 0x21
  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
 80003d6:	6383      	str	r3, [r0, #56]	; 0x38
  /* Allocate lock resource and initialize it */
  hdma->Lock = HAL_UNLOCKED;
 80003d8:	f880 3020 	strb.w	r3, [r0, #32]

  return HAL_OK;
 80003dc:	4618      	mov	r0, r3
 80003de:	bd10      	pop	{r4, pc}
    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
 80003e0:	4b06      	ldr	r3, [pc, #24]	; (80003fc <HAL_DMA_Init+0x78>)
 80003e2:	440b      	add	r3, r1
 80003e4:	fbb3 f3f4 	udiv	r3, r3, r4
 80003e8:	009b      	lsls	r3, r3, #2
 80003ea:	6403      	str	r3, [r0, #64]	; 0x40
    hdma->DmaBaseAddress = DMA2;
 80003ec:	4b04      	ldr	r3, [pc, #16]	; (8000400 <HAL_DMA_Init+0x7c>)
 80003ee:	e7d9      	b.n	80003a4 <HAL_DMA_Init+0x20>
    return HAL_ERROR;
 80003f0:	2001      	movs	r0, #1
}
 80003f2:	bd10      	pop	{r4, pc}
 80003f4:	40020407 	.word	0x40020407
 80003f8:	bffdfff8 	.word	0xbffdfff8
 80003fc:	bffdfbf8 	.word	0xbffdfbf8
 8000400:	40020400 	.word	0x40020400

08000404 <HAL_DMA_Abort_IT>:
  */
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
{  
  HAL_StatusTypeDef status = HAL_OK;
  
  if(HAL_DMA_STATE_BUSY != hdma->State)
 8000404:	f890 3021 	ldrb.w	r3, [r0, #33]	; 0x21
{  
 8000408:	b510      	push	{r4, lr}
  if(HAL_DMA_STATE_BUSY != hdma->State)
 800040a:	2b02      	cmp	r3, #2
 800040c:	d003      	beq.n	8000416 <HAL_DMA_Abort_IT+0x12>
  {
    /* no transfer ongoing */
    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
 800040e:	2304      	movs	r3, #4
 8000410:	6383      	str	r3, [r0, #56]	; 0x38
        
    status = HAL_ERROR;
 8000412:	2001      	movs	r0, #1
 8000414:	bd10      	pop	{r4, pc}
  }
  else
  { 
    /* Disable DMA IT */
    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
 8000416:	6803      	ldr	r3, [r0, #0]
 8000418:	681a      	ldr	r2, [r3, #0]
 800041a:	f022 020e 	bic.w	r2, r2, #14
 800041e:	601a      	str	r2, [r3, #0]

    /* Disable the channel */
    __HAL_DMA_DISABLE(hdma);
 8000420:	681a      	ldr	r2, [r3, #0]
 8000422:	f022 0201 	bic.w	r2, r2, #1
 8000426:	601a      	str	r2, [r3, #0]

    /* Clear all flags */
    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma));
 8000428:	4a29      	ldr	r2, [pc, #164]	; (80004d0 <HAL_DMA_Abort_IT+0xcc>)
 800042a:	4293      	cmp	r3, r2
 800042c:	d924      	bls.n	8000478 <HAL_DMA_Abort_IT+0x74>
 800042e:	f502 7262 	add.w	r2, r2, #904	; 0x388
 8000432:	4293      	cmp	r3, r2
 8000434:	d019      	beq.n	800046a <HAL_DMA_Abort_IT+0x66>
 8000436:	3214      	adds	r2, #20
 8000438:	4293      	cmp	r3, r2
 800043a:	d018      	beq.n	800046e <HAL_DMA_Abort_IT+0x6a>
 800043c:	3214      	adds	r2, #20
 800043e:	4293      	cmp	r3, r2
 8000440:	d017      	beq.n	8000472 <HAL_DMA_Abort_IT+0x6e>
 8000442:	3214      	adds	r2, #20
 8000444:	4293      	cmp	r3, r2
 8000446:	bf0c      	ite	eq
 8000448:	f44f 5380 	moveq.w	r3, #4096	; 0x1000
 800044c:	f44f 3380 	movne.w	r3, #65536	; 0x10000
 8000450:	4a20      	ldr	r2, [pc, #128]	; (80004d4 <HAL_DMA_Abort_IT+0xd0>)
 8000452:	6053      	str	r3, [r2, #4]

    /* Change the DMA state */
    hdma->State = HAL_DMA_STATE_READY;
 8000454:	2301      	movs	r3, #1

    /* Process Unlocked */
    __HAL_UNLOCK(hdma);
 8000456:	2400      	movs	r4, #0
    hdma->State = HAL_DMA_STATE_READY;
 8000458:	f880 3021 	strb.w	r3, [r0, #33]	; 0x21

    /* Call User Abort callback */
    if(hdma->XferAbortCallback != NULL)
 800045c:	6b43      	ldr	r3, [r0, #52]	; 0x34
    __HAL_UNLOCK(hdma);
 800045e:	f880 4020 	strb.w	r4, [r0, #32]
    if(hdma->XferAbortCallback != NULL)
 8000462:	b39b      	cbz	r3, 80004cc <HAL_DMA_Abort_IT+0xc8>
    {
      hdma->XferAbortCallback(hdma);
 8000464:	4798      	blx	r3
  HAL_StatusTypeDef status = HAL_OK;
 8000466:	4620      	mov	r0, r4
 8000468:	bd10      	pop	{r4, pc}
    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma));
 800046a:	2301      	movs	r3, #1
 800046c:	e7f0      	b.n	8000450 <HAL_DMA_Abort_IT+0x4c>
 800046e:	2310      	movs	r3, #16
 8000470:	e7ee      	b.n	8000450 <HAL_DMA_Abort_IT+0x4c>
 8000472:	f44f 7380 	mov.w	r3, #256	; 0x100
 8000476:	e7eb      	b.n	8000450 <HAL_DMA_Abort_IT+0x4c>
 8000478:	4917      	ldr	r1, [pc, #92]	; (80004d8 <HAL_DMA_Abort_IT+0xd4>)
 800047a:	428b      	cmp	r3, r1
 800047c:	d016      	beq.n	80004ac <HAL_DMA_Abort_IT+0xa8>
 800047e:	3114      	adds	r1, #20
 8000480:	428b      	cmp	r3, r1
 8000482:	d015      	beq.n	80004b0 <HAL_DMA_Abort_IT+0xac>
 8000484:	3114      	adds	r1, #20
 8000486:	428b      	cmp	r3, r1
 8000488:	d014      	beq.n	80004b4 <HAL_DMA_Abort_IT+0xb0>
 800048a:	3114      	adds	r1, #20
 800048c:	428b      	cmp	r3, r1
 800048e:	d014      	beq.n	80004ba <HAL_DMA_Abort_IT+0xb6>
 8000490:	3114      	adds	r1, #20
 8000492:	428b      	cmp	r3, r1
 8000494:	d014      	beq.n	80004c0 <HAL_DMA_Abort_IT+0xbc>
 8000496:	3114      	adds	r1, #20
 8000498:	428b      	cmp	r3, r1
 800049a:	d014      	beq.n	80004c6 <HAL_DMA_Abort_IT+0xc2>
 800049c:	4293      	cmp	r3, r2
 800049e:	bf14      	ite	ne
 80004a0:	f44f 3380 	movne.w	r3, #65536	; 0x10000
 80004a4:	f04f 7380 	moveq.w	r3, #16777216	; 0x1000000
 80004a8:	4a0c      	ldr	r2, [pc, #48]	; (80004dc <HAL_DMA_Abort_IT+0xd8>)
 80004aa:	e7d2      	b.n	8000452 <HAL_DMA_Abort_IT+0x4e>
 80004ac:	2301      	movs	r3, #1
 80004ae:	e7fb      	b.n	80004a8 <HAL_DMA_Abort_IT+0xa4>
 80004b0:	2310      	movs	r3, #16
 80004b2:	e7f9      	b.n	80004a8 <HAL_DMA_Abort_IT+0xa4>
 80004b4:	f44f 7380 	mov.w	r3, #256	; 0x100
 80004b8:	e7f6      	b.n	80004a8 <HAL_DMA_Abort_IT+0xa4>
 80004ba:	f44f 5380 	mov.w	r3, #4096	; 0x1000
 80004be:	e7f3      	b.n	80004a8 <HAL_DMA_Abort_IT+0xa4>
 80004c0:	f44f 3380 	mov.w	r3, #65536	; 0x10000
 80004c4:	e7f0      	b.n	80004a8 <HAL_DMA_Abort_IT+0xa4>
 80004c6:	f44f 1380 	mov.w	r3, #1048576	; 0x100000
 80004ca:	e7ed      	b.n	80004a8 <HAL_DMA_Abort_IT+0xa4>
  HAL_StatusTypeDef status = HAL_OK;
 80004cc:	4618      	mov	r0, r3
    } 
  }
  return status;
}
 80004ce:	bd10      	pop	{r4, pc}
 80004d0:	40020080 	.word	0x40020080
 80004d4:	40020400 	.word	0x40020400
 80004d8:	40020008 	.word	0x40020008
 80004dc:	40020000 	.word	0x40020000

080004e0 <HAL_DMA_IRQHandler>:
  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
  *               the configuration information for the specified DMA Channel.  
  * @retval None
  */
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
{
 80004e0:	b470      	push	{r4, r5, r6}
  uint32_t flag_it = hdma->DmaBaseAddress->ISR;
  uint32_t source_it = hdma->Instance->CCR;
  
  /* Half Transfer Complete Interrupt management ******************************/
  if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET))
 80004e2:	2504      	movs	r5, #4
  uint32_t flag_it = hdma->DmaBaseAddress->ISR;
 80004e4:	6bc6      	ldr	r6, [r0, #60]	; 0x3c
  if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET))
 80004e6:	6c02      	ldr	r2, [r0, #64]	; 0x40
  uint32_t flag_it = hdma->DmaBaseAddress->ISR;
 80004e8:	6834      	ldr	r4, [r6, #0]
  uint32_t source_it = hdma->Instance->CCR;
 80004ea:	6803      	ldr	r3, [r0, #0]
  if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET))
 80004ec:	4095      	lsls	r5, r2
 80004ee:	4225      	tst	r5, r4
  uint32_t source_it = hdma->Instance->CCR;
 80004f0:	6819      	ldr	r1, [r3, #0]
  if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET))
 80004f2:	d055      	beq.n	80005a0 <HAL_DMA_IRQHandler+0xc0>
 80004f4:	074d      	lsls	r5, r1, #29
 80004f6:	d553      	bpl.n	80005a0 <HAL_DMA_IRQHandler+0xc0>
  {
    /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
    if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
 80004f8:	681a      	ldr	r2, [r3, #0]
 80004fa:	0696      	lsls	r6, r2, #26
    {
      /* Disable the half transfer interrupt */
      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
 80004fc:	bf5e      	ittt	pl
 80004fe:	681a      	ldrpl	r2, [r3, #0]
 8000500:	f022 0204 	bicpl.w	r2, r2, #4
 8000504:	601a      	strpl	r2, [r3, #0]
    }
    /* Clear the half transfer complete flag */
    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
 8000506:	4a60      	ldr	r2, [pc, #384]	; (8000688 <HAL_DMA_IRQHandler+0x1a8>)
 8000508:	4293      	cmp	r3, r2
 800050a:	d91f      	bls.n	800054c <HAL_DMA_IRQHandler+0x6c>
 800050c:	f502 7262 	add.w	r2, r2, #904	; 0x388
 8000510:	4293      	cmp	r3, r2
 8000512:	d014      	beq.n	800053e <HAL_DMA_IRQHandler+0x5e>
 8000514:	3214      	adds	r2, #20
 8000516:	4293      	cmp	r3, r2
 8000518:	d013      	beq.n	8000542 <HAL_DMA_IRQHandler+0x62>
 800051a:	3214      	adds	r2, #20
 800051c:	4293      	cmp	r3, r2
 800051e:	d012      	beq.n	8000546 <HAL_DMA_IRQHandler+0x66>
 8000520:	3214      	adds	r2, #20
 8000522:	4293      	cmp	r3, r2
 8000524:	bf0c      	ite	eq
 8000526:	f44f 4380 	moveq.w	r3, #16384	; 0x4000
 800052a:	f44f 2380 	movne.w	r3, #262144	; 0x40000
 800052e:	4a57      	ldr	r2, [pc, #348]	; (800068c <HAL_DMA_IRQHandler+0x1ac>)
 8000530:	6053      	str	r3, [r2, #4]

    /* DMA peripheral state is not updated in Half Transfer */
    /* but in Transfer Complete case */

    if(hdma->XferHalfCpltCallback != NULL)
 8000532:	6ac3      	ldr	r3, [r0, #44]	; 0x2c
    hdma->State = HAL_DMA_STATE_READY;

    /* Process Unlocked */
    __HAL_UNLOCK(hdma);

    if (hdma->XferErrorCallback != NULL)
 8000534:	2b00      	cmp	r3, #0
 8000536:	f000 80a5 	beq.w	8000684 <HAL_DMA_IRQHandler+0x1a4>
      /* Transfer error callback */
      hdma->XferErrorCallback(hdma);
    }
  }
  return;
}
 800053a:	bc70      	pop	{r4, r5, r6}
      hdma->XferErrorCallback(hdma);
 800053c:	4718      	bx	r3
    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
 800053e:	2304      	movs	r3, #4
 8000540:	e7f5      	b.n	800052e <HAL_DMA_IRQHandler+0x4e>
 8000542:	2340      	movs	r3, #64	; 0x40
 8000544:	e7f3      	b.n	800052e <HAL_DMA_IRQHandler+0x4e>
 8000546:	f44f 6380 	mov.w	r3, #1024	; 0x400
 800054a:	e7f0      	b.n	800052e <HAL_DMA_IRQHandler+0x4e>
 800054c:	4950      	ldr	r1, [pc, #320]	; (8000690 <HAL_DMA_IRQHandler+0x1b0>)
 800054e:	428b      	cmp	r3, r1
 8000550:	d016      	beq.n	8000580 <HAL_DMA_IRQHandler+0xa0>
 8000552:	3114      	adds	r1, #20
 8000554:	428b      	cmp	r3, r1
 8000556:	d015      	beq.n	8000584 <HAL_DMA_IRQHandler+0xa4>
 8000558:	3114      	adds	r1, #20
 800055a:	428b      	cmp	r3, r1
 800055c:	d014      	beq.n	8000588 <HAL_DMA_IRQHandler+0xa8>
 800055e:	3114      	adds	r1, #20
 8000560:	428b      	cmp	r3, r1
 8000562:	d014      	beq.n	800058e <HAL_DMA_IRQHandler+0xae>
 8000564:	3114      	adds	r1, #20
 8000566:	428b      	cmp	r3, r1
 8000568:	d014      	beq.n	8000594 <HAL_DMA_IRQHandler+0xb4>
 800056a:	3114      	adds	r1, #20
 800056c:	428b      	cmp	r3, r1
 800056e:	d014      	beq.n	800059a <HAL_DMA_IRQHandler+0xba>
 8000570:	4293      	cmp	r3, r2
 8000572:	bf14      	ite	ne
 8000574:	f44f 2380 	movne.w	r3, #262144	; 0x40000
 8000578:	f04f 6380 	moveq.w	r3, #67108864	; 0x4000000
 800057c:	4a45      	ldr	r2, [pc, #276]	; (8000694 <HAL_DMA_IRQHandler+0x1b4>)
 800057e:	e7d7      	b.n	8000530 <HAL_DMA_IRQHandler+0x50>
 8000580:	2304      	movs	r3, #4
 8000582:	e7fb      	b.n	800057c <HAL_DMA_IRQHandler+0x9c>
 8000584:	2340      	movs	r3, #64	; 0x40
 8000586:	e7f9      	b.n	800057c <HAL_DMA_IRQHandler+0x9c>
 8000588:	f44f 6380 	mov.w	r3, #1024	; 0x400
 800058c:	e7f6      	b.n	800057c <HAL_DMA_IRQHandler+0x9c>
 800058e:	f44f 4380 	mov.w	r3, #16384	; 0x4000
 8000592:	e7f3      	b.n	800057c <HAL_DMA_IRQHandler+0x9c>
 8000594:	f44f 2380 	mov.w	r3, #262144	; 0x40000
 8000598:	e7f0      	b.n	800057c <HAL_DMA_IRQHandler+0x9c>
 800059a:	f44f 0380 	mov.w	r3, #4194304	; 0x400000
 800059e:	e7ed      	b.n	800057c <HAL_DMA_IRQHandler+0x9c>
  else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET))
 80005a0:	2502      	movs	r5, #2
 80005a2:	4095      	lsls	r5, r2
 80005a4:	4225      	tst	r5, r4
 80005a6:	d057      	beq.n	8000658 <HAL_DMA_IRQHandler+0x178>
 80005a8:	078d      	lsls	r5, r1, #30
 80005aa:	d555      	bpl.n	8000658 <HAL_DMA_IRQHandler+0x178>
    if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
 80005ac:	681a      	ldr	r2, [r3, #0]
 80005ae:	0694      	lsls	r4, r2, #26
 80005b0:	d406      	bmi.n	80005c0 <HAL_DMA_IRQHandler+0xe0>
      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);  
 80005b2:	681a      	ldr	r2, [r3, #0]
 80005b4:	f022 020a 	bic.w	r2, r2, #10
 80005b8:	601a      	str	r2, [r3, #0]
      hdma->State = HAL_DMA_STATE_READY;
 80005ba:	2201      	movs	r2, #1
 80005bc:	f880 2021 	strb.w	r2, [r0, #33]	; 0x21
      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
 80005c0:	4a31      	ldr	r2, [pc, #196]	; (8000688 <HAL_DMA_IRQHandler+0x1a8>)
 80005c2:	4293      	cmp	r3, r2
 80005c4:	d91e      	bls.n	8000604 <HAL_DMA_IRQHandler+0x124>
 80005c6:	f502 7262 	add.w	r2, r2, #904	; 0x388
 80005ca:	4293      	cmp	r3, r2
 80005cc:	d013      	beq.n	80005f6 <HAL_DMA_IRQHandler+0x116>
 80005ce:	3214      	adds	r2, #20
 80005d0:	4293      	cmp	r3, r2
 80005d2:	d012      	beq.n	80005fa <HAL_DMA_IRQHandler+0x11a>
 80005d4:	3214      	adds	r2, #20
 80005d6:	4293      	cmp	r3, r2
 80005d8:	d011      	beq.n	80005fe <HAL_DMA_IRQHandler+0x11e>
 80005da:	3214      	adds	r2, #20
 80005dc:	4293      	cmp	r3, r2
 80005de:	bf0c      	ite	eq
 80005e0:	f44f 5300 	moveq.w	r3, #8192	; 0x2000
 80005e4:	f44f 3300 	movne.w	r3, #131072	; 0x20000
 80005e8:	4a28      	ldr	r2, [pc, #160]	; (800068c <HAL_DMA_IRQHandler+0x1ac>)
 80005ea:	6053      	str	r3, [r2, #4]
    __HAL_UNLOCK(hdma);
 80005ec:	2300      	movs	r3, #0
 80005ee:	f880 3020 	strb.w	r3, [r0, #32]
    if(hdma->XferCpltCallback != NULL)
 80005f2:	6a83      	ldr	r3, [r0, #40]	; 0x28
 80005f4:	e79e      	b.n	8000534 <HAL_DMA_IRQHandler+0x54>
      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
 80005f6:	2302      	movs	r3, #2
 80005f8:	e7f6      	b.n	80005e8 <HAL_DMA_IRQHandler+0x108>
 80005fa:	2320      	movs	r3, #32
 80005fc:	e7f4      	b.n	80005e8 <HAL_DMA_IRQHandler+0x108>
 80005fe:	f44f 7300 	mov.w	r3, #512	; 0x200
 8000602:	e7f1      	b.n	80005e8 <HAL_DMA_IRQHandler+0x108>
 8000604:	4922      	ldr	r1, [pc, #136]	; (8000690 <HAL_DMA_IRQHandler+0x1b0>)
 8000606:	428b      	cmp	r3, r1
 8000608:	d016      	beq.n	8000638 <HAL_DMA_IRQHandler+0x158>
 800060a:	3114      	adds	r1, #20
 800060c:	428b      	cmp	r3, r1
 800060e:	d015      	beq.n	800063c <HAL_DMA_IRQHandler+0x15c>
 8000610:	3114      	adds	r1, #20
 8000612:	428b      	cmp	r3, r1
 8000614:	d014      	beq.n	8000640 <HAL_DMA_IRQHandler+0x160>
 8000616:	3114      	adds	r1, #20
 8000618:	428b      	cmp	r3, r1
 800061a:	d014      	beq.n	8000646 <HAL_DMA_IRQHandler+0x166>
 800061c:	3114      	adds	r1, #20
 800061e:	428b      	cmp	r3, r1
 8000620:	d014      	beq.n	800064c <HAL_DMA_IRQHandler+0x16c>
 8000622:	3114      	adds	r1, #20
 8000624:	428b      	cmp	r3, r1
 8000626:	d014      	beq.n	8000652 <HAL_DMA_IRQHandler+0x172>
 8000628:	4293      	cmp	r3, r2
 800062a:	bf14      	ite	ne
 800062c:	f44f 3300 	movne.w	r3, #131072	; 0x20000
 8000630:	f04f 7300 	moveq.w	r3, #33554432	; 0x2000000
 8000634:	4a17      	ldr	r2, [pc, #92]	; (8000694 <HAL_DMA_IRQHandler+0x1b4>)
 8000636:	e7d8      	b.n	80005ea <HAL_DMA_IRQHandler+0x10a>
 8000638:	2302      	movs	r3, #2
 800063a:	e7fb      	b.n	8000634 <HAL_DMA_IRQHandler+0x154>
 800063c:	2320      	movs	r3, #32
 800063e:	e7f9      	b.n	8000634 <HAL_DMA_IRQHandler+0x154>
 8000640:	f44f 7300 	mov.w	r3, #512	; 0x200
 8000644:	e7f6      	b.n	8000634 <HAL_DMA_IRQHandler+0x154>
 8000646:	f44f 5300 	mov.w	r3, #8192	; 0x2000
 800064a:	e7f3      	b.n	8000634 <HAL_DMA_IRQHandler+0x154>
 800064c:	f44f 3300 	mov.w	r3, #131072	; 0x20000
 8000650:	e7f0      	b.n	8000634 <HAL_DMA_IRQHandler+0x154>
 8000652:	f44f 1300 	mov.w	r3, #2097152	; 0x200000
 8000656:	e7ed      	b.n	8000634 <HAL_DMA_IRQHandler+0x154>
  else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
 8000658:	2508      	movs	r5, #8
 800065a:	4095      	lsls	r5, r2
 800065c:	4225      	tst	r5, r4
 800065e:	d011      	beq.n	8000684 <HAL_DMA_IRQHandler+0x1a4>
 8000660:	0709      	lsls	r1, r1, #28
 8000662:	d50f      	bpl.n	8000684 <HAL_DMA_IRQHandler+0x1a4>
    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
 8000664:	6819      	ldr	r1, [r3, #0]
 8000666:	f021 010e 	bic.w	r1, r1, #14
 800066a:	6019      	str	r1, [r3, #0]
    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
 800066c:	2301      	movs	r3, #1
 800066e:	fa03 f202 	lsl.w	r2, r3, r2
 8000672:	6072      	str	r2, [r6, #4]
    hdma->ErrorCode = HAL_DMA_ERROR_TE;
 8000674:	6383      	str	r3, [r0, #56]	; 0x38
    hdma->State = HAL_DMA_STATE_READY;
 8000676:	f880 3021 	strb.w	r3, [r0, #33]	; 0x21
    __HAL_UNLOCK(hdma);
 800067a:	2300      	movs	r3, #0
 800067c:	f880 3020 	strb.w	r3, [r0, #32]
    if (hdma->XferErrorCallback != NULL)
 8000680:	6b03      	ldr	r3, [r0, #48]	; 0x30
 8000682:	e757      	b.n	8000534 <HAL_DMA_IRQHandler+0x54>
}
 8000684:	bc70      	pop	{r4, r5, r6}
 8000686:	4770      	bx	lr
 8000688:	40020080 	.word	0x40020080
 800068c:	40020400 	.word	0x40020400
 8000690:	40020008 	.word	0x40020008
 8000694:	40020000 	.word	0x40020000

08000698 <HAL_GPIO_Init>:
  * @param  GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
  *         the configuration information for the specified GPIO peripheral.
  * @retval None
  */
void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
 8000698:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
  uint32_t position;
  uint32_t ioposition = 0x00U;
  uint32_t iocurrent = 0x00U;
  uint32_t temp = 0x00U;
  uint32_t config = 0x00U;
 800069c:	2200      	movs	r2, #0
  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));

  /* Configure the port pins */
  for (position = 0U; position < GPIO_NUMBER; position++)
 800069e:	4616      	mov	r6, r2
      /*--------------------- EXTI Mode Configuration ------------------------*/
      /* Configure the External Interrupt or event for the current IO */
      if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
      {
        /* Enable AFIO Clock */
        __HAL_RCC_AFIO_CLK_ENABLE();
 80006a0:	4f6c      	ldr	r7, [pc, #432]	; (8000854 <HAL_GPIO_Init+0x1bc>)
 80006a2:	4b6d      	ldr	r3, [pc, #436]	; (8000858 <HAL_GPIO_Init+0x1c0>)
        temp = AFIO->EXTICR[position >> 2U];
        CLEAR_BIT(temp, (0x0FU) << (4U * (position & 0x03U)));
        SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
 80006a4:	f8df e1b8 	ldr.w	lr, [pc, #440]	; 8000860 <HAL_GPIO_Init+0x1c8>
      switch (GPIO_Init->Mode)
 80006a8:	f8df c1b8 	ldr.w	ip, [pc, #440]	; 8000864 <HAL_GPIO_Init+0x1cc>
    ioposition = (0x01U << position);
 80006ac:	f04f 0801 	mov.w	r8, #1
    iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
 80006b0:	680c      	ldr	r4, [r1, #0]
    ioposition = (0x01U << position);
 80006b2:	fa08 f806 	lsl.w	r8, r8, r6
    iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
 80006b6:	ea08 0404 	and.w	r4, r8, r4
    if (iocurrent == ioposition)
 80006ba:	45a0      	cmp	r8, r4
 80006bc:	f040 8085 	bne.w	80007ca <HAL_GPIO_Init+0x132>
      switch (GPIO_Init->Mode)
 80006c0:	684d      	ldr	r5, [r1, #4]
 80006c2:	2d12      	cmp	r5, #18
 80006c4:	f000 80b7 	beq.w	8000836 <HAL_GPIO_Init+0x19e>
 80006c8:	f200 808d 	bhi.w	80007e6 <HAL_GPIO_Init+0x14e>
 80006cc:	2d02      	cmp	r5, #2
 80006ce:	f000 80af 	beq.w	8000830 <HAL_GPIO_Init+0x198>
 80006d2:	f200 8081 	bhi.w	80007d8 <HAL_GPIO_Init+0x140>
 80006d6:	2d00      	cmp	r5, #0
 80006d8:	f000 8091 	beq.w	80007fe <HAL_GPIO_Init+0x166>
 80006dc:	2d01      	cmp	r5, #1
 80006de:	f000 80a5 	beq.w	800082c <HAL_GPIO_Init+0x194>
      MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
 80006e2:	f04f 090f 	mov.w	r9, #15
      configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL     : &GPIOx->CRH;
 80006e6:	2cff      	cmp	r4, #255	; 0xff
 80006e8:	bf93      	iteet	ls
 80006ea:	4682      	movls	sl, r0
 80006ec:	f106 4580 	addhi.w	r5, r6, #1073741824	; 0x40000000
 80006f0:	3d08      	subhi	r5, #8
 80006f2:	f8d0 b000 	ldrls.w	fp, [r0]
 80006f6:	bf92      	itee	ls
 80006f8:	00b5      	lslls	r5, r6, #2
 80006fa:	f8d0 b004 	ldrhi.w	fp, [r0, #4]
 80006fe:	00ad      	lslhi	r5, r5, #2
      MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
 8000700:	fa09 f805 	lsl.w	r8, r9, r5
 8000704:	ea2b 0808 	bic.w	r8, fp, r8
 8000708:	fa02 f505 	lsl.w	r5, r2, r5
      configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL     : &GPIOx->CRH;
 800070c:	bf88      	it	hi
 800070e:	f100 0a04 	addhi.w	sl, r0, #4
      MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
 8000712:	ea48 0505 	orr.w	r5, r8, r5
 8000716:	f8ca 5000 	str.w	r5, [sl]
      if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
 800071a:	f8d1 a004 	ldr.w	sl, [r1, #4]
 800071e:	f01a 5f80 	tst.w	sl, #268435456	; 0x10000000
 8000722:	d052      	beq.n	80007ca <HAL_GPIO_Init+0x132>
        __HAL_RCC_AFIO_CLK_ENABLE();
 8000724:	69bd      	ldr	r5, [r7, #24]
 8000726:	f026 0803 	bic.w	r8, r6, #3
 800072a:	f045 0501 	orr.w	r5, r5, #1
 800072e:	61bd      	str	r5, [r7, #24]
 8000730:	69bd      	ldr	r5, [r7, #24]
 8000732:	f108 4880 	add.w	r8, r8, #1073741824	; 0x40000000
 8000736:	f005 0501 	and.w	r5, r5, #1
 800073a:	9501      	str	r5, [sp, #4]
 800073c:	f508 3880 	add.w	r8, r8, #65536	; 0x10000
        CLEAR_BIT(temp, (0x0FU) << (4U * (position & 0x03U)));
 8000740:	f006 0b03 	and.w	fp, r6, #3
        __HAL_RCC_AFIO_CLK_ENABLE();
 8000744:	9d01      	ldr	r5, [sp, #4]
        CLEAR_BIT(temp, (0x0FU) << (4U * (position & 0x03U)));
 8000746:	ea4f 0b8b 	mov.w	fp, fp, lsl #2
        temp = AFIO->EXTICR[position >> 2U];
 800074a:	f8d8 5008 	ldr.w	r5, [r8, #8]
        CLEAR_BIT(temp, (0x0FU) << (4U * (position & 0x03U)));
 800074e:	fa09 f90b 	lsl.w	r9, r9, fp
 8000752:	ea25 0909 	bic.w	r9, r5, r9
        SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
 8000756:	4d41      	ldr	r5, [pc, #260]	; (800085c <HAL_GPIO_Init+0x1c4>)
 8000758:	42a8      	cmp	r0, r5
 800075a:	d071      	beq.n	8000840 <HAL_GPIO_Init+0x1a8>
 800075c:	f505 6580 	add.w	r5, r5, #1024	; 0x400
 8000760:	42a8      	cmp	r0, r5
 8000762:	d06f      	beq.n	8000844 <HAL_GPIO_Init+0x1ac>
 8000764:	f505 6580 	add.w	r5, r5, #1024	; 0x400
 8000768:	42a8      	cmp	r0, r5
 800076a:	d06d      	beq.n	8000848 <HAL_GPIO_Init+0x1b0>
 800076c:	f505 6580 	add.w	r5, r5, #1024	; 0x400
 8000770:	42a8      	cmp	r0, r5
 8000772:	d06b      	beq.n	800084c <HAL_GPIO_Init+0x1b4>
 8000774:	f505 6580 	add.w	r5, r5, #1024	; 0x400
 8000778:	42a8      	cmp	r0, r5
 800077a:	d069      	beq.n	8000850 <HAL_GPIO_Init+0x1b8>
 800077c:	4570      	cmp	r0, lr
 800077e:	bf0c      	ite	eq
 8000780:	2505      	moveq	r5, #5
 8000782:	2506      	movne	r5, #6
 8000784:	fa05 f50b 	lsl.w	r5, r5, fp
 8000788:	ea45 0509 	orr.w	r5, r5, r9
        AFIO->EXTICR[position >> 2U] = temp;
 800078c:	f8c8 5008 	str.w	r5, [r8, #8]


        /* Configure the interrupt mask */
        if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
        {
          SET_BIT(EXTI->IMR, iocurrent);
 8000790:	681d      	ldr	r5, [r3, #0]
        if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
 8000792:	f41a 3f80 	tst.w	sl, #65536	; 0x10000
          SET_BIT(EXTI->IMR, iocurrent);
 8000796:	bf14      	ite	ne
 8000798:	4325      	orrne	r5, r4
        }
        else
        {
          CLEAR_BIT(EXTI->IMR, iocurrent);
 800079a:	43a5      	biceq	r5, r4
 800079c:	601d      	str	r5, [r3, #0]
        }

        /* Configure the event mask */
        if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
        {
          SET_BIT(EXTI->EMR, iocurrent);
 800079e:	685d      	ldr	r5, [r3, #4]
        if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
 80007a0:	f41a 3f00 	tst.w	sl, #131072	; 0x20000
          SET_BIT(EXTI->EMR, iocurrent);
 80007a4:	bf14      	ite	ne
 80007a6:	4325      	orrne	r5, r4
        }
        else
        {
          CLEAR_BIT(EXTI->EMR, iocurrent);
 80007a8:	43a5      	biceq	r5, r4
 80007aa:	605d      	str	r5, [r3, #4]
        }

        /* Enable or disable the rising trigger */
        if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
        {
          SET_BIT(EXTI->RTSR, iocurrent);
 80007ac:	689d      	ldr	r5, [r3, #8]
        if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
 80007ae:	f41a 1f80 	tst.w	sl, #1048576	; 0x100000
          SET_BIT(EXTI->RTSR, iocurrent);
 80007b2:	bf14      	ite	ne
 80007b4:	4325      	orrne	r5, r4
        }
        else
        {
          CLEAR_BIT(EXTI->RTSR, iocurrent);
 80007b6:	43a5      	biceq	r5, r4
 80007b8:	609d      	str	r5, [r3, #8]
        }

        /* Enable or disable the falling trigger */
        if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
        {
          SET_BIT(EXTI->FTSR, iocurrent);
 80007ba:	68dd      	ldr	r5, [r3, #12]
        if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
 80007bc:	f41a 1f00 	tst.w	sl, #2097152	; 0x200000
          SET_BIT(EXTI->FTSR, iocurrent);
 80007c0:	bf14      	ite	ne
 80007c2:	432c      	orrne	r4, r5
        }
        else
        {
          CLEAR_BIT(EXTI->FTSR, iocurrent);
 80007c4:	ea25 0404 	biceq.w	r4, r5, r4
 80007c8:	60dc      	str	r4, [r3, #12]
  for (position = 0U; position < GPIO_NUMBER; position++)
 80007ca:	3601      	adds	r6, #1
 80007cc:	2e10      	cmp	r6, #16
 80007ce:	f47f af6d 	bne.w	80006ac <HAL_GPIO_Init+0x14>
        }
      }
    }
  }
}
 80007d2:	b003      	add	sp, #12
 80007d4:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
      switch (GPIO_Init->Mode)
 80007d8:	2d03      	cmp	r5, #3
 80007da:	d025      	beq.n	8000828 <HAL_GPIO_Init+0x190>
 80007dc:	2d11      	cmp	r5, #17
 80007de:	d180      	bne.n	80006e2 <HAL_GPIO_Init+0x4a>
          config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;
 80007e0:	68ca      	ldr	r2, [r1, #12]
 80007e2:	3204      	adds	r2, #4
          break;
 80007e4:	e77d      	b.n	80006e2 <HAL_GPIO_Init+0x4a>
      switch (GPIO_Init->Mode)
 80007e6:	4565      	cmp	r5, ip
 80007e8:	d009      	beq.n	80007fe <HAL_GPIO_Init+0x166>
 80007ea:	d812      	bhi.n	8000812 <HAL_GPIO_Init+0x17a>
 80007ec:	f8df 9078 	ldr.w	r9, [pc, #120]	; 8000868 <HAL_GPIO_Init+0x1d0>
 80007f0:	454d      	cmp	r5, r9
 80007f2:	d004      	beq.n	80007fe <HAL_GPIO_Init+0x166>
 80007f4:	f509 3980 	add.w	r9, r9, #65536	; 0x10000
 80007f8:	454d      	cmp	r5, r9
 80007fa:	f47f af72 	bne.w	80006e2 <HAL_GPIO_Init+0x4a>
          if (GPIO_Init->Pull == GPIO_NOPULL)
 80007fe:	688a      	ldr	r2, [r1, #8]
 8000800:	b1e2      	cbz	r2, 800083c <HAL_GPIO_Init+0x1a4>
          else if (GPIO_Init->Pull == GPIO_PULLUP)
 8000802:	2a01      	cmp	r2, #1
            GPIOx->BSRR = ioposition;
 8000804:	bf0c      	ite	eq
 8000806:	f8c0 8010 	streq.w	r8, [r0, #16]
            GPIOx->BRR = ioposition;
 800080a:	f8c0 8014 	strne.w	r8, [r0, #20]
            config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
 800080e:	2208      	movs	r2, #8
 8000810:	e767      	b.n	80006e2 <HAL_GPIO_Init+0x4a>
      switch (GPIO_Init->Mode)
 8000812:	f8df 9058 	ldr.w	r9, [pc, #88]	; 800086c <HAL_GPIO_Init+0x1d4>
 8000816:	454d      	cmp	r5, r9
 8000818:	d0f1      	beq.n	80007fe <HAL_GPIO_Init+0x166>
 800081a:	f509 3980 	add.w	r9, r9, #65536	; 0x10000
 800081e:	454d      	cmp	r5, r9
 8000820:	d0ed      	beq.n	80007fe <HAL_GPIO_Init+0x166>
 8000822:	f5a9 1980 	sub.w	r9, r9, #1048576	; 0x100000
 8000826:	e7e7      	b.n	80007f8 <HAL_GPIO_Init+0x160>
          config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
 8000828:	2200      	movs	r2, #0
 800082a:	e75a      	b.n	80006e2 <HAL_GPIO_Init+0x4a>
          config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;
 800082c:	68ca      	ldr	r2, [r1, #12]
          break;
 800082e:	e758      	b.n	80006e2 <HAL_GPIO_Init+0x4a>
          config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;
 8000830:	68ca      	ldr	r2, [r1, #12]
 8000832:	3208      	adds	r2, #8
          break;
 8000834:	e755      	b.n	80006e2 <HAL_GPIO_Init+0x4a>
          config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;
 8000836:	68ca      	ldr	r2, [r1, #12]
 8000838:	320c      	adds	r2, #12
          break;
 800083a:	e752      	b.n	80006e2 <HAL_GPIO_Init+0x4a>
            config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
 800083c:	2204      	movs	r2, #4
 800083e:	e750      	b.n	80006e2 <HAL_GPIO_Init+0x4a>
        SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
 8000840:	2500      	movs	r5, #0
 8000842:	e79f      	b.n	8000784 <HAL_GPIO_Init+0xec>
 8000844:	2501      	movs	r5, #1
 8000846:	e79d      	b.n	8000784 <HAL_GPIO_Init+0xec>
 8000848:	2502      	movs	r5, #2
 800084a:	e79b      	b.n	8000784 <HAL_GPIO_Init+0xec>
 800084c:	2503      	movs	r5, #3
 800084e:	e799      	b.n	8000784 <HAL_GPIO_Init+0xec>
 8000850:	2504      	movs	r5, #4
 8000852:	e797      	b.n	8000784 <HAL_GPIO_Init+0xec>
 8000854:	40021000 	.word	0x40021000
 8000858:	40010400 	.word	0x40010400
 800085c:	40010800 	.word	0x40010800
 8000860:	40011c00 	.word	0x40011c00
 8000864:	10210000 	.word	0x10210000
 8000868:	10110000 	.word	0x10110000
 800086c:	10310000 	.word	0x10310000

08000870 <HAL_GPIO_WritePin>:
{
  /* Check the parameters */
  assert_param(IS_GPIO_PIN(GPIO_Pin));
  assert_param(IS_GPIO_PIN_ACTION(PinState));

  if (PinState != GPIO_PIN_RESET)
 8000870:	b10a      	cbz	r2, 8000876 <HAL_GPIO_WritePin+0x6>
  {
    GPIOx->BSRR = GPIO_Pin;
  }
  else
  {
    GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
 8000872:	6101      	str	r1, [r0, #16]
 8000874:	4770      	bx	lr
 8000876:	0409      	lsls	r1, r1, #16
 8000878:	e7fb      	b.n	8000872 <HAL_GPIO_WritePin+0x2>
	...

0800087c <HAL_RCC_OscConfig>:
  /* Check the parameters */
  assert_param(RCC_OscInitStruct != NULL);
  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
  
  /*------------------------------- HSE Configuration ------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
 800087c:	6803      	ldr	r3, [r0, #0]
{
 800087e:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
 8000882:	07db      	lsls	r3, r3, #31
{
 8000884:	4605      	mov	r5, r0
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
 8000886:	d410      	bmi.n	80008aa <HAL_RCC_OscConfig+0x2e>
        }
      }
    }
  }
  /*----------------------------- HSI Configuration --------------------------*/ 
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
 8000888:	682b      	ldr	r3, [r5, #0]
 800088a:	079f      	lsls	r7, r3, #30
 800088c:	d45e      	bmi.n	800094c <HAL_RCC_OscConfig+0xd0>
        }
      }
    }
  }
  /*------------------------------ LSI Configuration -------------------------*/ 
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
 800088e:	682b      	ldr	r3, [r5, #0]
 8000890:	0719      	lsls	r1, r3, #28
 8000892:	f100 8095 	bmi.w	80009c0 <HAL_RCC_OscConfig+0x144>
        }
      }
    }
  }
  /*------------------------------ LSE Configuration -------------------------*/ 
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
 8000896:	682b      	ldr	r3, [r5, #0]
 8000898:	075a      	lsls	r2, r3, #29
 800089a:	f100 80bf 	bmi.w	8000a1c <HAL_RCC_OscConfig+0x1a0>

#endif /* RCC_CR_PLL2ON */
  /*-------------------------------- PLL Configuration -----------------------*/
  /* Check the parameters */
  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
 800089e:	69ea      	ldr	r2, [r5, #28]
 80008a0:	2a00      	cmp	r2, #0
 80008a2:	f040 812d 	bne.w	8000b00 <HAL_RCC_OscConfig+0x284>
    {
      return HAL_ERROR;
    }
  }
  
  return HAL_OK;
 80008a6:	2000      	movs	r0, #0
 80008a8:	e014      	b.n	80008d4 <HAL_RCC_OscConfig+0x58>
    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 
 80008aa:	4c90      	ldr	r4, [pc, #576]	; (8000aec <HAL_RCC_OscConfig+0x270>)
 80008ac:	6863      	ldr	r3, [r4, #4]
 80008ae:	f003 030c 	and.w	r3, r3, #12
 80008b2:	2b04      	cmp	r3, #4
 80008b4:	d007      	beq.n	80008c6 <HAL_RCC_OscConfig+0x4a>
       || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
 80008b6:	6863      	ldr	r3, [r4, #4]
 80008b8:	f003 030c 	and.w	r3, r3, #12
 80008bc:	2b08      	cmp	r3, #8
 80008be:	d10c      	bne.n	80008da <HAL_RCC_OscConfig+0x5e>
 80008c0:	6863      	ldr	r3, [r4, #4]
 80008c2:	03de      	lsls	r6, r3, #15
 80008c4:	d509      	bpl.n	80008da <HAL_RCC_OscConfig+0x5e>
      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
 80008c6:	6823      	ldr	r3, [r4, #0]
 80008c8:	039c      	lsls	r4, r3, #14
 80008ca:	d5dd      	bpl.n	8000888 <HAL_RCC_OscConfig+0xc>
 80008cc:	686b      	ldr	r3, [r5, #4]
 80008ce:	2b00      	cmp	r3, #0
 80008d0:	d1da      	bne.n	8000888 <HAL_RCC_OscConfig+0xc>
        return HAL_ERROR;
 80008d2:	2001      	movs	r0, #1
}
 80008d4:	b002      	add	sp, #8
 80008d6:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 80008da:	686b      	ldr	r3, [r5, #4]
 80008dc:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
 80008e0:	d110      	bne.n	8000904 <HAL_RCC_OscConfig+0x88>
 80008e2:	6823      	ldr	r3, [r4, #0]
 80008e4:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
 80008e8:	6023      	str	r3, [r4, #0]
        tickstart = HAL_GetTick();
 80008ea:	f7ff fcdd 	bl	80002a8 <HAL_GetTick>
 80008ee:	4606      	mov	r6, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 80008f0:	6823      	ldr	r3, [r4, #0]
 80008f2:	0398      	lsls	r0, r3, #14
 80008f4:	d4c8      	bmi.n	8000888 <HAL_RCC_OscConfig+0xc>
          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
 80008f6:	f7ff fcd7 	bl	80002a8 <HAL_GetTick>
 80008fa:	1b80      	subs	r0, r0, r6
 80008fc:	2864      	cmp	r0, #100	; 0x64
 80008fe:	d9f7      	bls.n	80008f0 <HAL_RCC_OscConfig+0x74>
            return HAL_TIMEOUT;
 8000900:	2003      	movs	r0, #3
 8000902:	e7e7      	b.n	80008d4 <HAL_RCC_OscConfig+0x58>
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 8000904:	b99b      	cbnz	r3, 800092e <HAL_RCC_OscConfig+0xb2>
 8000906:	6823      	ldr	r3, [r4, #0]
 8000908:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
 800090c:	6023      	str	r3, [r4, #0]
 800090e:	6823      	ldr	r3, [r4, #0]
 8000910:	f423 2380 	bic.w	r3, r3, #262144	; 0x40000
 8000914:	6023      	str	r3, [r4, #0]
        tickstart = HAL_GetTick();
 8000916:	f7ff fcc7 	bl	80002a8 <HAL_GetTick>
 800091a:	4606      	mov	r6, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
 800091c:	6823      	ldr	r3, [r4, #0]
 800091e:	0399      	lsls	r1, r3, #14
 8000920:	d5b2      	bpl.n	8000888 <HAL_RCC_OscConfig+0xc>
           if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
 8000922:	f7ff fcc1 	bl	80002a8 <HAL_GetTick>
 8000926:	1b80      	subs	r0, r0, r6
 8000928:	2864      	cmp	r0, #100	; 0x64
 800092a:	d9f7      	bls.n	800091c <HAL_RCC_OscConfig+0xa0>
 800092c:	e7e8      	b.n	8000900 <HAL_RCC_OscConfig+0x84>
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 800092e:	f5b3 2fa0 	cmp.w	r3, #327680	; 0x50000
 8000932:	6823      	ldr	r3, [r4, #0]
 8000934:	d103      	bne.n	800093e <HAL_RCC_OscConfig+0xc2>
 8000936:	f443 2380 	orr.w	r3, r3, #262144	; 0x40000
 800093a:	6023      	str	r3, [r4, #0]
 800093c:	e7d1      	b.n	80008e2 <HAL_RCC_OscConfig+0x66>
 800093e:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
 8000942:	6023      	str	r3, [r4, #0]
 8000944:	6823      	ldr	r3, [r4, #0]
 8000946:	f423 2380 	bic.w	r3, r3, #262144	; 0x40000
 800094a:	e7cd      	b.n	80008e8 <HAL_RCC_OscConfig+0x6c>
    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 
 800094c:	4c67      	ldr	r4, [pc, #412]	; (8000aec <HAL_RCC_OscConfig+0x270>)
 800094e:	6863      	ldr	r3, [r4, #4]
 8000950:	f013 0f0c 	tst.w	r3, #12
 8000954:	d007      	beq.n	8000966 <HAL_RCC_OscConfig+0xea>
       || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
 8000956:	6863      	ldr	r3, [r4, #4]
 8000958:	f003 030c 	and.w	r3, r3, #12
 800095c:	2b08      	cmp	r3, #8
 800095e:	d110      	bne.n	8000982 <HAL_RCC_OscConfig+0x106>
 8000960:	6863      	ldr	r3, [r4, #4]
 8000962:	03da      	lsls	r2, r3, #15
 8000964:	d40d      	bmi.n	8000982 <HAL_RCC_OscConfig+0x106>
      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
 8000966:	6823      	ldr	r3, [r4, #0]
 8000968:	079b      	lsls	r3, r3, #30
 800096a:	d502      	bpl.n	8000972 <HAL_RCC_OscConfig+0xf6>
 800096c:	692b      	ldr	r3, [r5, #16]
 800096e:	2b01      	cmp	r3, #1
 8000970:	d1af      	bne.n	80008d2 <HAL_RCC_OscConfig+0x56>
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 8000972:	6823      	ldr	r3, [r4, #0]
 8000974:	696a      	ldr	r2, [r5, #20]
 8000976:	f023 03f8 	bic.w	r3, r3, #248	; 0xf8
 800097a:	ea43 03c2 	orr.w	r3, r3, r2, lsl #3
 800097e:	6023      	str	r3, [r4, #0]
 8000980:	e785      	b.n	800088e <HAL_RCC_OscConfig+0x12>
      if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
 8000982:	692a      	ldr	r2, [r5, #16]
 8000984:	4b5a      	ldr	r3, [pc, #360]	; (8000af0 <HAL_RCC_OscConfig+0x274>)
 8000986:	b16a      	cbz	r2, 80009a4 <HAL_RCC_OscConfig+0x128>
        __HAL_RCC_HSI_ENABLE();
 8000988:	2201      	movs	r2, #1
 800098a:	601a      	str	r2, [r3, #0]
        tickstart = HAL_GetTick();
 800098c:	f7ff fc8c 	bl	80002a8 <HAL_GetTick>
 8000990:	4606      	mov	r6, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 8000992:	6823      	ldr	r3, [r4, #0]
 8000994:	079f      	lsls	r7, r3, #30
 8000996:	d4ec      	bmi.n	8000972 <HAL_RCC_OscConfig+0xf6>
          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
 8000998:	f7ff fc86 	bl	80002a8 <HAL_GetTick>
 800099c:	1b80      	subs	r0, r0, r6
 800099e:	2802      	cmp	r0, #2
 80009a0:	d9f7      	bls.n	8000992 <HAL_RCC_OscConfig+0x116>
 80009a2:	e7ad      	b.n	8000900 <HAL_RCC_OscConfig+0x84>
        __HAL_RCC_HSI_DISABLE();
 80009a4:	601a      	str	r2, [r3, #0]
        tickstart = HAL_GetTick();
 80009a6:	f7ff fc7f 	bl	80002a8 <HAL_GetTick>
 80009aa:	4606      	mov	r6, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
 80009ac:	6823      	ldr	r3, [r4, #0]
 80009ae:	0798      	lsls	r0, r3, #30
 80009b0:	f57f af6d 	bpl.w	800088e <HAL_RCC_OscConfig+0x12>
          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
 80009b4:	f7ff fc78 	bl	80002a8 <HAL_GetTick>
 80009b8:	1b80      	subs	r0, r0, r6
 80009ba:	2802      	cmp	r0, #2
 80009bc:	d9f6      	bls.n	80009ac <HAL_RCC_OscConfig+0x130>
 80009be:	e79f      	b.n	8000900 <HAL_RCC_OscConfig+0x84>
    if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
 80009c0:	69aa      	ldr	r2, [r5, #24]
 80009c2:	4c4a      	ldr	r4, [pc, #296]	; (8000aec <HAL_RCC_OscConfig+0x270>)
 80009c4:	4b4b      	ldr	r3, [pc, #300]	; (8000af4 <HAL_RCC_OscConfig+0x278>)
 80009c6:	b1da      	cbz	r2, 8000a00 <HAL_RCC_OscConfig+0x184>
      __HAL_RCC_LSI_ENABLE();
 80009c8:	2201      	movs	r2, #1
 80009ca:	601a      	str	r2, [r3, #0]
      tickstart = HAL_GetTick();
 80009cc:	f7ff fc6c 	bl	80002a8 <HAL_GetTick>
 80009d0:	4606      	mov	r6, r0
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
 80009d2:	6a63      	ldr	r3, [r4, #36]	; 0x24
 80009d4:	079b      	lsls	r3, r3, #30
 80009d6:	d50d      	bpl.n	80009f4 <HAL_RCC_OscConfig+0x178>
  * @param  mdelay: specifies the delay time length, in milliseconds.
  * @retval None
  */
static void RCC_Delay(uint32_t mdelay)
{
  __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
 80009d8:	f44f 52fa 	mov.w	r2, #8000	; 0x1f40
 80009dc:	4b46      	ldr	r3, [pc, #280]	; (8000af8 <HAL_RCC_OscConfig+0x27c>)
 80009de:	681b      	ldr	r3, [r3, #0]
 80009e0:	fbb3 f3f2 	udiv	r3, r3, r2
 80009e4:	9301      	str	r3, [sp, #4]
  \brief   No Operation
  \details No Operation does nothing. This instruction can be used for code alignment purposes.
 */
__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
{
  __ASM volatile ("nop");
 80009e6:	bf00      	nop
  do 
  {
    __NOP();
  } 
  while (Delay --);
 80009e8:	9b01      	ldr	r3, [sp, #4]
 80009ea:	1e5a      	subs	r2, r3, #1
 80009ec:	9201      	str	r2, [sp, #4]
 80009ee:	2b00      	cmp	r3, #0
 80009f0:	d1f9      	bne.n	80009e6 <HAL_RCC_OscConfig+0x16a>
 80009f2:	e750      	b.n	8000896 <HAL_RCC_OscConfig+0x1a>
        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
 80009f4:	f7ff fc58 	bl	80002a8 <HAL_GetTick>
 80009f8:	1b80      	subs	r0, r0, r6
 80009fa:	2802      	cmp	r0, #2
 80009fc:	d9e9      	bls.n	80009d2 <HAL_RCC_OscConfig+0x156>
 80009fe:	e77f      	b.n	8000900 <HAL_RCC_OscConfig+0x84>
      __HAL_RCC_LSI_DISABLE();
 8000a00:	601a      	str	r2, [r3, #0]
      tickstart = HAL_GetTick();
 8000a02:	f7ff fc51 	bl	80002a8 <HAL_GetTick>
 8000a06:	4606      	mov	r6, r0
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
 8000a08:	6a63      	ldr	r3, [r4, #36]	; 0x24
 8000a0a:	079f      	lsls	r7, r3, #30
 8000a0c:	f57f af43 	bpl.w	8000896 <HAL_RCC_OscConfig+0x1a>
        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
 8000a10:	f7ff fc4a 	bl	80002a8 <HAL_GetTick>
 8000a14:	1b80      	subs	r0, r0, r6
 8000a16:	2802      	cmp	r0, #2
 8000a18:	d9f6      	bls.n	8000a08 <HAL_RCC_OscConfig+0x18c>
 8000a1a:	e771      	b.n	8000900 <HAL_RCC_OscConfig+0x84>
    if(__HAL_RCC_PWR_IS_CLK_DISABLED())
 8000a1c:	4c33      	ldr	r4, [pc, #204]	; (8000aec <HAL_RCC_OscConfig+0x270>)
 8000a1e:	69e3      	ldr	r3, [r4, #28]
 8000a20:	00d8      	lsls	r0, r3, #3
 8000a22:	d424      	bmi.n	8000a6e <HAL_RCC_OscConfig+0x1f2>
      pwrclkchanged = SET;
 8000a24:	2701      	movs	r7, #1
      __HAL_RCC_PWR_CLK_ENABLE();
 8000a26:	69e3      	ldr	r3, [r4, #28]
 8000a28:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
 8000a2c:	61e3      	str	r3, [r4, #28]
 8000a2e:	69e3      	ldr	r3, [r4, #28]
 8000a30:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8000a34:	9300      	str	r3, [sp, #0]
 8000a36:	9b00      	ldr	r3, [sp, #0]
    if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 8000a38:	4e30      	ldr	r6, [pc, #192]	; (8000afc <HAL_RCC_OscConfig+0x280>)
 8000a3a:	6833      	ldr	r3, [r6, #0]
 8000a3c:	05d9      	lsls	r1, r3, #23
 8000a3e:	d518      	bpl.n	8000a72 <HAL_RCC_OscConfig+0x1f6>
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 8000a40:	68eb      	ldr	r3, [r5, #12]
 8000a42:	2b01      	cmp	r3, #1
 8000a44:	d126      	bne.n	8000a94 <HAL_RCC_OscConfig+0x218>
 8000a46:	6a23      	ldr	r3, [r4, #32]
 8000a48:	f043 0301 	orr.w	r3, r3, #1
 8000a4c:	6223      	str	r3, [r4, #32]
      tickstart = HAL_GetTick();
 8000a4e:	f7ff fc2b 	bl	80002a8 <HAL_GetTick>
        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
 8000a52:	f241 3688 	movw	r6, #5000	; 0x1388
      tickstart = HAL_GetTick();
 8000a56:	4680      	mov	r8, r0
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
 8000a58:	6a23      	ldr	r3, [r4, #32]
 8000a5a:	079b      	lsls	r3, r3, #30
 8000a5c:	d53f      	bpl.n	8000ade <HAL_RCC_OscConfig+0x262>
    if(pwrclkchanged == SET)
 8000a5e:	2f00      	cmp	r7, #0
 8000a60:	f43f af1d 	beq.w	800089e <HAL_RCC_OscConfig+0x22>
      __HAL_RCC_PWR_CLK_DISABLE();
 8000a64:	69e3      	ldr	r3, [r4, #28]
 8000a66:	f023 5380 	bic.w	r3, r3, #268435456	; 0x10000000
 8000a6a:	61e3      	str	r3, [r4, #28]
 8000a6c:	e717      	b.n	800089e <HAL_RCC_OscConfig+0x22>
    FlagStatus       pwrclkchanged = RESET;
 8000a6e:	2700      	movs	r7, #0
 8000a70:	e7e2      	b.n	8000a38 <HAL_RCC_OscConfig+0x1bc>
      SET_BIT(PWR->CR, PWR_CR_DBP);
 8000a72:	6833      	ldr	r3, [r6, #0]
 8000a74:	f443 7380 	orr.w	r3, r3, #256	; 0x100
 8000a78:	6033      	str	r3, [r6, #0]
      tickstart = HAL_GetTick();
 8000a7a:	f7ff fc15 	bl	80002a8 <HAL_GetTick>
 8000a7e:	4680      	mov	r8, r0
      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 8000a80:	6833      	ldr	r3, [r6, #0]
 8000a82:	05da      	lsls	r2, r3, #23
 8000a84:	d4dc      	bmi.n	8000a40 <HAL_RCC_OscConfig+0x1c4>
        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
 8000a86:	f7ff fc0f 	bl	80002a8 <HAL_GetTick>
 8000a8a:	eba0 0008 	sub.w	r0, r0, r8
 8000a8e:	2864      	cmp	r0, #100	; 0x64
 8000a90:	d9f6      	bls.n	8000a80 <HAL_RCC_OscConfig+0x204>
 8000a92:	e735      	b.n	8000900 <HAL_RCC_OscConfig+0x84>
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 8000a94:	b9ab      	cbnz	r3, 8000ac2 <HAL_RCC_OscConfig+0x246>
 8000a96:	6a23      	ldr	r3, [r4, #32]
        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
 8000a98:	f241 3888 	movw	r8, #5000	; 0x1388
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 8000a9c:	f023 0301 	bic.w	r3, r3, #1
 8000aa0:	6223      	str	r3, [r4, #32]
 8000aa2:	6a23      	ldr	r3, [r4, #32]
 8000aa4:	f023 0304 	bic.w	r3, r3, #4
 8000aa8:	6223      	str	r3, [r4, #32]
      tickstart = HAL_GetTick();
 8000aaa:	f7ff fbfd 	bl	80002a8 <HAL_GetTick>
 8000aae:	4606      	mov	r6, r0
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
 8000ab0:	6a23      	ldr	r3, [r4, #32]
 8000ab2:	0798      	lsls	r0, r3, #30
 8000ab4:	d5d3      	bpl.n	8000a5e <HAL_RCC_OscConfig+0x1e2>
        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
 8000ab6:	f7ff fbf7 	bl	80002a8 <HAL_GetTick>
 8000aba:	1b80      	subs	r0, r0, r6
 8000abc:	4540      	cmp	r0, r8
 8000abe:	d9f7      	bls.n	8000ab0 <HAL_RCC_OscConfig+0x234>
 8000ac0:	e71e      	b.n	8000900 <HAL_RCC_OscConfig+0x84>
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 8000ac2:	2b05      	cmp	r3, #5
 8000ac4:	6a23      	ldr	r3, [r4, #32]
 8000ac6:	d103      	bne.n	8000ad0 <HAL_RCC_OscConfig+0x254>
 8000ac8:	f043 0304 	orr.w	r3, r3, #4
 8000acc:	6223      	str	r3, [r4, #32]
 8000ace:	e7ba      	b.n	8000a46 <HAL_RCC_OscConfig+0x1ca>
 8000ad0:	f023 0301 	bic.w	r3, r3, #1
 8000ad4:	6223      	str	r3, [r4, #32]
 8000ad6:	6a23      	ldr	r3, [r4, #32]
 8000ad8:	f023 0304 	bic.w	r3, r3, #4
 8000adc:	e7b6      	b.n	8000a4c <HAL_RCC_OscConfig+0x1d0>
        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
 8000ade:	f7ff fbe3 	bl	80002a8 <HAL_GetTick>
 8000ae2:	eba0 0008 	sub.w	r0, r0, r8
 8000ae6:	42b0      	cmp	r0, r6
 8000ae8:	d9b6      	bls.n	8000a58 <HAL_RCC_OscConfig+0x1dc>
 8000aea:	e709      	b.n	8000900 <HAL_RCC_OscConfig+0x84>
 8000aec:	40021000 	.word	0x40021000
 8000af0:	42420000 	.word	0x42420000
 8000af4:	42420480 	.word	0x42420480
 8000af8:	20000008 	.word	0x20000008
 8000afc:	40007000 	.word	0x40007000
    if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
 8000b00:	4c22      	ldr	r4, [pc, #136]	; (8000b8c <HAL_RCC_OscConfig+0x310>)
 8000b02:	6863      	ldr	r3, [r4, #4]
 8000b04:	f003 030c 	and.w	r3, r3, #12
 8000b08:	2b08      	cmp	r3, #8
 8000b0a:	f43f aee2 	beq.w	80008d2 <HAL_RCC_OscConfig+0x56>
 8000b0e:	2300      	movs	r3, #0
 8000b10:	4e1f      	ldr	r6, [pc, #124]	; (8000b90 <HAL_RCC_OscConfig+0x314>)
      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
 8000b12:	2a02      	cmp	r2, #2
        __HAL_RCC_PLL_DISABLE();
 8000b14:	6033      	str	r3, [r6, #0]
      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
 8000b16:	d12b      	bne.n	8000b70 <HAL_RCC_OscConfig+0x2f4>
        tickstart = HAL_GetTick();
 8000b18:	f7ff fbc6 	bl	80002a8 <HAL_GetTick>
 8000b1c:	4607      	mov	r7, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
 8000b1e:	6823      	ldr	r3, [r4, #0]
 8000b20:	0199      	lsls	r1, r3, #6
 8000b22:	d41f      	bmi.n	8000b64 <HAL_RCC_OscConfig+0x2e8>
        if(RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
 8000b24:	6a2b      	ldr	r3, [r5, #32]
 8000b26:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
 8000b2a:	d105      	bne.n	8000b38 <HAL_RCC_OscConfig+0x2bc>
          __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
 8000b2c:	6862      	ldr	r2, [r4, #4]
 8000b2e:	68a9      	ldr	r1, [r5, #8]
 8000b30:	f422 3200 	bic.w	r2, r2, #131072	; 0x20000
 8000b34:	430a      	orrs	r2, r1
 8000b36:	6062      	str	r2, [r4, #4]
        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
 8000b38:	6a69      	ldr	r1, [r5, #36]	; 0x24
 8000b3a:	6862      	ldr	r2, [r4, #4]
 8000b3c:	430b      	orrs	r3, r1
 8000b3e:	f422 1274 	bic.w	r2, r2, #3997696	; 0x3d0000
 8000b42:	4313      	orrs	r3, r2
 8000b44:	6063      	str	r3, [r4, #4]
        __HAL_RCC_PLL_ENABLE();
 8000b46:	2301      	movs	r3, #1
 8000b48:	6033      	str	r3, [r6, #0]
        tickstart = HAL_GetTick();
 8000b4a:	f7ff fbad 	bl	80002a8 <HAL_GetTick>
 8000b4e:	4605      	mov	r5, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  == RESET)
 8000b50:	6823      	ldr	r3, [r4, #0]
 8000b52:	019a      	lsls	r2, r3, #6
 8000b54:	f53f aea7 	bmi.w	80008a6 <HAL_RCC_OscConfig+0x2a>
          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
 8000b58:	f7ff fba6 	bl	80002a8 <HAL_GetTick>
 8000b5c:	1b40      	subs	r0, r0, r5
 8000b5e:	2802      	cmp	r0, #2
 8000b60:	d9f6      	bls.n	8000b50 <HAL_RCC_OscConfig+0x2d4>
 8000b62:	e6cd      	b.n	8000900 <HAL_RCC_OscConfig+0x84>
          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
 8000b64:	f7ff fba0 	bl	80002a8 <HAL_GetTick>
 8000b68:	1bc0      	subs	r0, r0, r7
 8000b6a:	2802      	cmp	r0, #2
 8000b6c:	d9d7      	bls.n	8000b1e <HAL_RCC_OscConfig+0x2a2>
 8000b6e:	e6c7      	b.n	8000900 <HAL_RCC_OscConfig+0x84>
        tickstart = HAL_GetTick();
 8000b70:	f7ff fb9a 	bl	80002a8 <HAL_GetTick>
 8000b74:	4605      	mov	r5, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
 8000b76:	6823      	ldr	r3, [r4, #0]
 8000b78:	019b      	lsls	r3, r3, #6
 8000b7a:	f57f ae94 	bpl.w	80008a6 <HAL_RCC_OscConfig+0x2a>
          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
 8000b7e:	f7ff fb93 	bl	80002a8 <HAL_GetTick>
 8000b82:	1b40      	subs	r0, r0, r5
 8000b84:	2802      	cmp	r0, #2
 8000b86:	d9f6      	bls.n	8000b76 <HAL_RCC_OscConfig+0x2fa>
 8000b88:	e6ba      	b.n	8000900 <HAL_RCC_OscConfig+0x84>
 8000b8a:	bf00      	nop
 8000b8c:	40021000 	.word	0x40021000
 8000b90:	42420060 	.word	0x42420060

08000b94 <HAL_RCC_GetSysClockFreq>:
{
 8000b94:	b530      	push	{r4, r5, lr}
  const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
 8000b96:	4b19      	ldr	r3, [pc, #100]	; (8000bfc <HAL_RCC_GetSysClockFreq+0x68>)
{
 8000b98:	b087      	sub	sp, #28
  const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
 8000b9a:	ac02      	add	r4, sp, #8
 8000b9c:	f103 0510 	add.w	r5, r3, #16
 8000ba0:	4622      	mov	r2, r4
 8000ba2:	6818      	ldr	r0, [r3, #0]
 8000ba4:	6859      	ldr	r1, [r3, #4]
 8000ba6:	3308      	adds	r3, #8
 8000ba8:	c203      	stmia	r2!, {r0, r1}
 8000baa:	42ab      	cmp	r3, r5
 8000bac:	4614      	mov	r4, r2
 8000bae:	d1f7      	bne.n	8000ba0 <HAL_RCC_GetSysClockFreq+0xc>
  const uint8_t aPredivFactorTable[2] = {1, 2};
 8000bb0:	2301      	movs	r3, #1
 8000bb2:	f88d 3004 	strb.w	r3, [sp, #4]
 8000bb6:	2302      	movs	r3, #2
  tmpreg = RCC->CFGR;
 8000bb8:	4911      	ldr	r1, [pc, #68]	; (8000c00 <HAL_RCC_GetSysClockFreq+0x6c>)
  const uint8_t aPredivFactorTable[2] = {1, 2};
 8000bba:	f88d 3005 	strb.w	r3, [sp, #5]
  tmpreg = RCC->CFGR;
 8000bbe:	684b      	ldr	r3, [r1, #4]
  switch (tmpreg & RCC_CFGR_SWS)
 8000bc0:	f003 020c 	and.w	r2, r3, #12
 8000bc4:	2a08      	cmp	r2, #8
 8000bc6:	d117      	bne.n	8000bf8 <HAL_RCC_GetSysClockFreq+0x64>
      pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
 8000bc8:	f3c3 4283 	ubfx	r2, r3, #18, #4
 8000bcc:	a806      	add	r0, sp, #24
 8000bce:	4402      	add	r2, r0
      if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
 8000bd0:	03db      	lsls	r3, r3, #15
      pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
 8000bd2:	f812 2c10 	ldrb.w	r2, [r2, #-16]
      if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
 8000bd6:	d50c      	bpl.n	8000bf2 <HAL_RCC_GetSysClockFreq+0x5e>
        prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
 8000bd8:	684b      	ldr	r3, [r1, #4]
        pllclk = (uint32_t)((HSE_VALUE  * pllmul) / prediv);
 8000bda:	480a      	ldr	r0, [pc, #40]	; (8000c04 <HAL_RCC_GetSysClockFreq+0x70>)
        prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
 8000bdc:	f3c3 4340 	ubfx	r3, r3, #17, #1
        pllclk = (uint32_t)((HSE_VALUE  * pllmul) / prediv);
 8000be0:	4350      	muls	r0, r2
        prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
 8000be2:	aa06      	add	r2, sp, #24
 8000be4:	4413      	add	r3, r2
 8000be6:	f813 3c14 	ldrb.w	r3, [r3, #-20]
        pllclk = (uint32_t)((HSE_VALUE  * pllmul) / prediv);
 8000bea:	fbb0 f0f3 	udiv	r0, r0, r3
}
 8000bee:	b007      	add	sp, #28
 8000bf0:	bd30      	pop	{r4, r5, pc}
        pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
 8000bf2:	4805      	ldr	r0, [pc, #20]	; (8000c08 <HAL_RCC_GetSysClockFreq+0x74>)
 8000bf4:	4350      	muls	r0, r2
 8000bf6:	e7fa      	b.n	8000bee <HAL_RCC_GetSysClockFreq+0x5a>
      sysclockfreq = HSE_VALUE;
 8000bf8:	4802      	ldr	r0, [pc, #8]	; (8000c04 <HAL_RCC_GetSysClockFreq+0x70>)
  return sysclockfreq;
 8000bfa:	e7f8      	b.n	8000bee <HAL_RCC_GetSysClockFreq+0x5a>
 8000bfc:	080014a8 	.word	0x080014a8
 8000c00:	40021000 	.word	0x40021000
 8000c04:	007a1200 	.word	0x007a1200
 8000c08:	003d0900 	.word	0x003d0900

08000c0c <HAL_RCC_ClockConfig>:
  if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
 8000c0c:	4a54      	ldr	r2, [pc, #336]	; (8000d60 <HAL_RCC_ClockConfig+0x154>)
{
 8000c0e:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
  if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
 8000c12:	6813      	ldr	r3, [r2, #0]
{
 8000c14:	4605      	mov	r5, r0
  if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
 8000c16:	f003 0307 	and.w	r3, r3, #7
 8000c1a:	428b      	cmp	r3, r1
{
 8000c1c:	460e      	mov	r6, r1
  if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
 8000c1e:	d32a      	bcc.n	8000c76 <HAL_RCC_ClockConfig+0x6a>
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
 8000c20:	6829      	ldr	r1, [r5, #0]
 8000c22:	078c      	lsls	r4, r1, #30
 8000c24:	d434      	bmi.n	8000c90 <HAL_RCC_ClockConfig+0x84>
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
 8000c26:	07ca      	lsls	r2, r1, #31
 8000c28:	d447      	bmi.n	8000cba <HAL_RCC_ClockConfig+0xae>
  if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
 8000c2a:	4a4d      	ldr	r2, [pc, #308]	; (8000d60 <HAL_RCC_ClockConfig+0x154>)
 8000c2c:	6813      	ldr	r3, [r2, #0]
 8000c2e:	f003 0307 	and.w	r3, r3, #7
 8000c32:	429e      	cmp	r6, r3
 8000c34:	f0c0 8082 	bcc.w	8000d3c <HAL_RCC_ClockConfig+0x130>
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 8000c38:	682a      	ldr	r2, [r5, #0]
 8000c3a:	4c4a      	ldr	r4, [pc, #296]	; (8000d64 <HAL_RCC_ClockConfig+0x158>)
 8000c3c:	f012 0f04 	tst.w	r2, #4
 8000c40:	f040 8087 	bne.w	8000d52 <HAL_RCC_ClockConfig+0x146>
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
 8000c44:	0713      	lsls	r3, r2, #28
 8000c46:	d506      	bpl.n	8000c56 <HAL_RCC_ClockConfig+0x4a>
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
 8000c48:	6863      	ldr	r3, [r4, #4]
 8000c4a:	692a      	ldr	r2, [r5, #16]
 8000c4c:	f423 5360 	bic.w	r3, r3, #14336	; 0x3800
 8000c50:	ea43 03c2 	orr.w	r3, r3, r2, lsl #3
 8000c54:	6063      	str	r3, [r4, #4]
  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
 8000c56:	f7ff ff9d 	bl	8000b94 <HAL_RCC_GetSysClockFreq>
 8000c5a:	6863      	ldr	r3, [r4, #4]
 8000c5c:	4a42      	ldr	r2, [pc, #264]	; (8000d68 <HAL_RCC_ClockConfig+0x15c>)
 8000c5e:	f3c3 1303 	ubfx	r3, r3, #4, #4
 8000c62:	5cd3      	ldrb	r3, [r2, r3]
 8000c64:	40d8      	lsrs	r0, r3
 8000c66:	4b41      	ldr	r3, [pc, #260]	; (8000d6c <HAL_RCC_ClockConfig+0x160>)
 8000c68:	6018      	str	r0, [r3, #0]
  HAL_InitTick (TICK_INT_PRIORITY);
 8000c6a:	2000      	movs	r0, #0
 8000c6c:	f7ff fada 	bl	8000224 <HAL_InitTick>
  return HAL_OK;
 8000c70:	2000      	movs	r0, #0
}
 8000c72:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    __HAL_FLASH_SET_LATENCY(FLatency);
 8000c76:	6813      	ldr	r3, [r2, #0]
 8000c78:	f023 0307 	bic.w	r3, r3, #7
 8000c7c:	430b      	orrs	r3, r1
 8000c7e:	6013      	str	r3, [r2, #0]
    if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
 8000c80:	6813      	ldr	r3, [r2, #0]
 8000c82:	f003 0307 	and.w	r3, r3, #7
 8000c86:	4299      	cmp	r1, r3
 8000c88:	d0ca      	beq.n	8000c20 <HAL_RCC_ClockConfig+0x14>
      return HAL_ERROR;
 8000c8a:	2001      	movs	r0, #1
 8000c8c:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
 8000c90:	4b34      	ldr	r3, [pc, #208]	; (8000d64 <HAL_RCC_ClockConfig+0x158>)
    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 8000c92:	f011 0f04 	tst.w	r1, #4
      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
 8000c96:	bf1e      	ittt	ne
 8000c98:	685a      	ldrne	r2, [r3, #4]
 8000c9a:	f442 62e0 	orrne.w	r2, r2, #1792	; 0x700
 8000c9e:	605a      	strne	r2, [r3, #4]
    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
 8000ca0:	0708      	lsls	r0, r1, #28
      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
 8000ca2:	bf42      	ittt	mi
 8000ca4:	685a      	ldrmi	r2, [r3, #4]
 8000ca6:	f442 5260 	orrmi.w	r2, r2, #14336	; 0x3800
 8000caa:	605a      	strmi	r2, [r3, #4]
    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
 8000cac:	685a      	ldr	r2, [r3, #4]
 8000cae:	68a8      	ldr	r0, [r5, #8]
 8000cb0:	f022 02f0 	bic.w	r2, r2, #240	; 0xf0
 8000cb4:	4302      	orrs	r2, r0
 8000cb6:	605a      	str	r2, [r3, #4]
 8000cb8:	e7b5      	b.n	8000c26 <HAL_RCC_ClockConfig+0x1a>
    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 8000cba:	686a      	ldr	r2, [r5, #4]
 8000cbc:	4c29      	ldr	r4, [pc, #164]	; (8000d64 <HAL_RCC_ClockConfig+0x158>)
 8000cbe:	2a01      	cmp	r2, #1
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 8000cc0:	6823      	ldr	r3, [r4, #0]
    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 8000cc2:	d11c      	bne.n	8000cfe <HAL_RCC_ClockConfig+0xf2>
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 8000cc4:	f413 3f00 	tst.w	r3, #131072	; 0x20000
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 8000cc8:	d0df      	beq.n	8000c8a <HAL_RCC_ClockConfig+0x7e>
    __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
 8000cca:	6863      	ldr	r3, [r4, #4]
        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
 8000ccc:	f241 3888 	movw	r8, #5000	; 0x1388
    __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
 8000cd0:	f023 0303 	bic.w	r3, r3, #3
 8000cd4:	4313      	orrs	r3, r2
 8000cd6:	6063      	str	r3, [r4, #4]
    tickstart = HAL_GetTick();
 8000cd8:	f7ff fae6 	bl	80002a8 <HAL_GetTick>
    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 8000cdc:	686b      	ldr	r3, [r5, #4]
    tickstart = HAL_GetTick();
 8000cde:	4607      	mov	r7, r0
    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 8000ce0:	2b01      	cmp	r3, #1
 8000ce2:	d114      	bne.n	8000d0e <HAL_RCC_ClockConfig+0x102>
      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
 8000ce4:	6863      	ldr	r3, [r4, #4]
 8000ce6:	f003 030c 	and.w	r3, r3, #12
 8000cea:	2b04      	cmp	r3, #4
 8000cec:	d09d      	beq.n	8000c2a <HAL_RCC_ClockConfig+0x1e>
        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
 8000cee:	f7ff fadb 	bl	80002a8 <HAL_GetTick>
 8000cf2:	1bc0      	subs	r0, r0, r7
 8000cf4:	4540      	cmp	r0, r8
 8000cf6:	d9f5      	bls.n	8000ce4 <HAL_RCC_ClockConfig+0xd8>
          return HAL_TIMEOUT;
 8000cf8:	2003      	movs	r0, #3
 8000cfa:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
 8000cfe:	2a02      	cmp	r2, #2
 8000d00:	d102      	bne.n	8000d08 <HAL_RCC_ClockConfig+0xfc>
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
 8000d02:	f013 7f00 	tst.w	r3, #33554432	; 0x2000000
 8000d06:	e7df      	b.n	8000cc8 <HAL_RCC_ClockConfig+0xbc>
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 8000d08:	f013 0f02 	tst.w	r3, #2
 8000d0c:	e7dc      	b.n	8000cc8 <HAL_RCC_ClockConfig+0xbc>
    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
 8000d0e:	2b02      	cmp	r3, #2
 8000d10:	d10f      	bne.n	8000d32 <HAL_RCC_ClockConfig+0x126>
      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
 8000d12:	6863      	ldr	r3, [r4, #4]
 8000d14:	f003 030c 	and.w	r3, r3, #12
 8000d18:	2b08      	cmp	r3, #8
 8000d1a:	d086      	beq.n	8000c2a <HAL_RCC_ClockConfig+0x1e>
        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
 8000d1c:	f7ff fac4 	bl	80002a8 <HAL_GetTick>
 8000d20:	1bc0      	subs	r0, r0, r7
 8000d22:	4540      	cmp	r0, r8
 8000d24:	d9f5      	bls.n	8000d12 <HAL_RCC_ClockConfig+0x106>
 8000d26:	e7e7      	b.n	8000cf8 <HAL_RCC_ClockConfig+0xec>
        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
 8000d28:	f7ff fabe 	bl	80002a8 <HAL_GetTick>
 8000d2c:	1bc0      	subs	r0, r0, r7
 8000d2e:	4540      	cmp	r0, r8
 8000d30:	d8e2      	bhi.n	8000cf8 <HAL_RCC_ClockConfig+0xec>
      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
 8000d32:	6863      	ldr	r3, [r4, #4]
 8000d34:	f013 0f0c 	tst.w	r3, #12
 8000d38:	d1f6      	bne.n	8000d28 <HAL_RCC_ClockConfig+0x11c>
 8000d3a:	e776      	b.n	8000c2a <HAL_RCC_ClockConfig+0x1e>
    __HAL_FLASH_SET_LATENCY(FLatency);
 8000d3c:	6813      	ldr	r3, [r2, #0]
 8000d3e:	f023 0307 	bic.w	r3, r3, #7
 8000d42:	4333      	orrs	r3, r6
 8000d44:	6013      	str	r3, [r2, #0]
    if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
 8000d46:	6813      	ldr	r3, [r2, #0]
 8000d48:	f003 0307 	and.w	r3, r3, #7
 8000d4c:	429e      	cmp	r6, r3
 8000d4e:	d19c      	bne.n	8000c8a <HAL_RCC_ClockConfig+0x7e>
 8000d50:	e772      	b.n	8000c38 <HAL_RCC_ClockConfig+0x2c>
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
 8000d52:	6863      	ldr	r3, [r4, #4]
 8000d54:	68e9      	ldr	r1, [r5, #12]
 8000d56:	f423 63e0 	bic.w	r3, r3, #1792	; 0x700
 8000d5a:	430b      	orrs	r3, r1
 8000d5c:	6063      	str	r3, [r4, #4]
 8000d5e:	e771      	b.n	8000c44 <HAL_RCC_ClockConfig+0x38>
 8000d60:	40022000 	.word	0x40022000
 8000d64:	40021000 	.word	0x40021000
 8000d68:	080014b8 	.word	0x080014b8
 8000d6c:	20000008 	.word	0x20000008

08000d70 <HAL_RCC_GetPCLK1Freq>:
  return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
 8000d70:	4b04      	ldr	r3, [pc, #16]	; (8000d84 <HAL_RCC_GetPCLK1Freq+0x14>)
 8000d72:	4a05      	ldr	r2, [pc, #20]	; (8000d88 <HAL_RCC_GetPCLK1Freq+0x18>)
 8000d74:	685b      	ldr	r3, [r3, #4]
 8000d76:	f3c3 2302 	ubfx	r3, r3, #8, #3
 8000d7a:	5cd3      	ldrb	r3, [r2, r3]
 8000d7c:	4a03      	ldr	r2, [pc, #12]	; (8000d8c <HAL_RCC_GetPCLK1Freq+0x1c>)
 8000d7e:	6810      	ldr	r0, [r2, #0]
}    
 8000d80:	40d8      	lsrs	r0, r3
 8000d82:	4770      	bx	lr
 8000d84:	40021000 	.word	0x40021000
 8000d88:	080014c8 	.word	0x080014c8
 8000d8c:	20000008 	.word	0x20000008

08000d90 <HAL_RCC_GetPCLK2Freq>:
  return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
 8000d90:	4b04      	ldr	r3, [pc, #16]	; (8000da4 <HAL_RCC_GetPCLK2Freq+0x14>)
 8000d92:	4a05      	ldr	r2, [pc, #20]	; (8000da8 <HAL_RCC_GetPCLK2Freq+0x18>)
 8000d94:	685b      	ldr	r3, [r3, #4]
 8000d96:	f3c3 23c2 	ubfx	r3, r3, #11, #3
 8000d9a:	5cd3      	ldrb	r3, [r2, r3]
 8000d9c:	4a03      	ldr	r2, [pc, #12]	; (8000dac <HAL_RCC_GetPCLK2Freq+0x1c>)
 8000d9e:	6810      	ldr	r0, [r2, #0]
} 
 8000da0:	40d8      	lsrs	r0, r3
 8000da2:	4770      	bx	lr
 8000da4:	40021000 	.word	0x40021000
 8000da8:	080014c8 	.word	0x080014c8
 8000dac:	20000008 	.word	0x20000008

08000db0 <UART_EndRxTransfer>:
  * @retval None
  */
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
{
  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
 8000db0:	6803      	ldr	r3, [r0, #0]
 8000db2:	68da      	ldr	r2, [r3, #12]
 8000db4:	f422 7290 	bic.w	r2, r2, #288	; 0x120
 8000db8:	60da      	str	r2, [r3, #12]
  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 8000dba:	695a      	ldr	r2, [r3, #20]
 8000dbc:	f022 0201 	bic.w	r2, r2, #1
 8000dc0:	615a      	str	r2, [r3, #20]

  /* At end of Rx process, restore huart->RxState to Ready */
  huart->RxState = HAL_UART_STATE_READY;
 8000dc2:	2320      	movs	r3, #32
 8000dc4:	f880 303a 	strb.w	r3, [r0, #58]	; 0x3a
 8000dc8:	4770      	bx	lr
	...

08000dcc <UART_SetConfig>:
  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
  *                the configuration information for the specified UART module.
  * @retval None
  */
static void UART_SetConfig(UART_HandleTypeDef *huart)
{
 8000dcc:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
  assert_param(IS_UART_MODE(huart->Init.Mode));

  /*------- UART-associated USART registers setting : CR2 Configuration ------*/
  /* Configure the UART Stop Bits: Set STOP[13:12] bits according 
   * to huart->Init.StopBits value */
  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
 8000dd0:	6805      	ldr	r5, [r0, #0]
 8000dd2:	68c2      	ldr	r2, [r0, #12]
 8000dd4:	692b      	ldr	r3, [r5, #16]
  tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
  MODIFY_REG(huart->Instance->CR1, 
             (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), 
             tmpreg);
#else
  tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
 8000dd6:	6901      	ldr	r1, [r0, #16]
  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
 8000dd8:	f423 5340 	bic.w	r3, r3, #12288	; 0x3000
 8000ddc:	4313      	orrs	r3, r2
 8000dde:	612b      	str	r3, [r5, #16]
  tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
 8000de0:	6883      	ldr	r3, [r0, #8]
  MODIFY_REG(huart->Instance->CR1, 
 8000de2:	68ea      	ldr	r2, [r5, #12]
  tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
 8000de4:	430b      	orrs	r3, r1
 8000de6:	6941      	ldr	r1, [r0, #20]
  MODIFY_REG(huart->Instance->CR1, 
 8000de8:	f422 52b0 	bic.w	r2, r2, #5632	; 0x1600
 8000dec:	f022 020c 	bic.w	r2, r2, #12
  tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
 8000df0:	430b      	orrs	r3, r1
  MODIFY_REG(huart->Instance->CR1, 
 8000df2:	4313      	orrs	r3, r2
 8000df4:	60eb      	str	r3, [r5, #12]
             tmpreg);
#endif /* USART_CR1_OVER8 */

  /*------- UART-associated USART registers setting : CR3 Configuration ------*/
  /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
  MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
 8000df6:	696b      	ldr	r3, [r5, #20]
 8000df8:	6982      	ldr	r2, [r0, #24]
 8000dfa:	f423 7340 	bic.w	r3, r3, #768	; 0x300
 8000dfe:	4313      	orrs	r3, r2
 8000e00:	616b      	str	r3, [r5, #20]
      huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
    }
  }
#else
  /*-------------------------- USART BRR Configuration ---------------------*/
  if(huart->Instance == USART1)
 8000e02:	4b40      	ldr	r3, [pc, #256]	; (8000f04 <UART_SetConfig+0x138>)
{
 8000e04:	4681      	mov	r9, r0
  if(huart->Instance == USART1)
 8000e06:	429d      	cmp	r5, r3
 8000e08:	f04f 0419 	mov.w	r4, #25
 8000e0c:	d146      	bne.n	8000e9c <UART_SetConfig+0xd0>
  {
    huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
 8000e0e:	f7ff ffbf 	bl	8000d90 <HAL_RCC_GetPCLK2Freq>
 8000e12:	fb04 f300 	mul.w	r3, r4, r0
 8000e16:	f8d9 6004 	ldr.w	r6, [r9, #4]
 8000e1a:	f04f 0864 	mov.w	r8, #100	; 0x64
 8000e1e:	00b6      	lsls	r6, r6, #2
 8000e20:	fbb3 f3f6 	udiv	r3, r3, r6
 8000e24:	fbb3 f3f8 	udiv	r3, r3, r8
 8000e28:	011e      	lsls	r6, r3, #4
 8000e2a:	f7ff ffb1 	bl	8000d90 <HAL_RCC_GetPCLK2Freq>
 8000e2e:	4360      	muls	r0, r4
 8000e30:	f8d9 3004 	ldr.w	r3, [r9, #4]
 8000e34:	009b      	lsls	r3, r3, #2
 8000e36:	fbb0 f7f3 	udiv	r7, r0, r3
 8000e3a:	f7ff ffa9 	bl	8000d90 <HAL_RCC_GetPCLK2Freq>
 8000e3e:	4360      	muls	r0, r4
 8000e40:	f8d9 3004 	ldr.w	r3, [r9, #4]
 8000e44:	009b      	lsls	r3, r3, #2
 8000e46:	fbb0 f3f3 	udiv	r3, r0, r3
 8000e4a:	fbb3 f3f8 	udiv	r3, r3, r8
 8000e4e:	fb08 7313 	mls	r3, r8, r3, r7
 8000e52:	011b      	lsls	r3, r3, #4
 8000e54:	3332      	adds	r3, #50	; 0x32
 8000e56:	fbb3 f3f8 	udiv	r3, r3, r8
 8000e5a:	f003 07f0 	and.w	r7, r3, #240	; 0xf0
 8000e5e:	f7ff ff97 	bl	8000d90 <HAL_RCC_GetPCLK2Freq>
 8000e62:	4360      	muls	r0, r4
 8000e64:	f8d9 2004 	ldr.w	r2, [r9, #4]
 8000e68:	0092      	lsls	r2, r2, #2
 8000e6a:	fbb0 faf2 	udiv	sl, r0, r2
 8000e6e:	f7ff ff8f 	bl	8000d90 <HAL_RCC_GetPCLK2Freq>
  }
  else
  {
    huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
 8000e72:	4360      	muls	r0, r4
 8000e74:	f8d9 3004 	ldr.w	r3, [r9, #4]
 8000e78:	009b      	lsls	r3, r3, #2
 8000e7a:	fbb0 f3f3 	udiv	r3, r0, r3
 8000e7e:	fbb3 f3f8 	udiv	r3, r3, r8
 8000e82:	fb08 a313 	mls	r3, r8, r3, sl
 8000e86:	011b      	lsls	r3, r3, #4
 8000e88:	3332      	adds	r3, #50	; 0x32
 8000e8a:	fbb3 f3f8 	udiv	r3, r3, r8
 8000e8e:	f003 030f 	and.w	r3, r3, #15
 8000e92:	433b      	orrs	r3, r7
 8000e94:	4433      	add	r3, r6
 8000e96:	60ab      	str	r3, [r5, #8]
 8000e98:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 8000e9c:	f7ff ff68 	bl	8000d70 <HAL_RCC_GetPCLK1Freq>
 8000ea0:	fb04 f300 	mul.w	r3, r4, r0
 8000ea4:	f8d9 6004 	ldr.w	r6, [r9, #4]
 8000ea8:	f04f 0864 	mov.w	r8, #100	; 0x64
 8000eac:	00b6      	lsls	r6, r6, #2
 8000eae:	fbb3 f3f6 	udiv	r3, r3, r6
 8000eb2:	fbb3 f3f8 	udiv	r3, r3, r8
 8000eb6:	011e      	lsls	r6, r3, #4
 8000eb8:	f7ff ff5a 	bl	8000d70 <HAL_RCC_GetPCLK1Freq>
 8000ebc:	4360      	muls	r0, r4
 8000ebe:	f8d9 3004 	ldr.w	r3, [r9, #4]
 8000ec2:	009b      	lsls	r3, r3, #2
 8000ec4:	fbb0 f7f3 	udiv	r7, r0, r3
 8000ec8:	f7ff ff52 	bl	8000d70 <HAL_RCC_GetPCLK1Freq>
 8000ecc:	4360      	muls	r0, r4
 8000ece:	f8d9 3004 	ldr.w	r3, [r9, #4]
 8000ed2:	009b      	lsls	r3, r3, #2
 8000ed4:	fbb0 f3f3 	udiv	r3, r0, r3
 8000ed8:	fbb3 f3f8 	udiv	r3, r3, r8
 8000edc:	fb08 7313 	mls	r3, r8, r3, r7
 8000ee0:	011b      	lsls	r3, r3, #4
 8000ee2:	3332      	adds	r3, #50	; 0x32
 8000ee4:	fbb3 f3f8 	udiv	r3, r3, r8
 8000ee8:	f003 07f0 	and.w	r7, r3, #240	; 0xf0
 8000eec:	f7ff ff40 	bl	8000d70 <HAL_RCC_GetPCLK1Freq>
 8000ef0:	4360      	muls	r0, r4
 8000ef2:	f8d9 2004 	ldr.w	r2, [r9, #4]
 8000ef6:	0092      	lsls	r2, r2, #2
 8000ef8:	fbb0 faf2 	udiv	sl, r0, r2
 8000efc:	f7ff ff38 	bl	8000d70 <HAL_RCC_GetPCLK1Freq>
 8000f00:	e7b7      	b.n	8000e72 <UART_SetConfig+0xa6>
 8000f02:	bf00      	nop
 8000f04:	40013800 	.word	0x40013800

08000f08 <HAL_UART_Init>:
{
 8000f08:	b510      	push	{r4, lr}
  if(huart == NULL)
 8000f0a:	4604      	mov	r4, r0
 8000f0c:	b340      	cbz	r0, 8000f60 <HAL_UART_Init+0x58>
  if(huart->gState == HAL_UART_STATE_RESET)
 8000f0e:	f890 3039 	ldrb.w	r3, [r0, #57]	; 0x39
 8000f12:	f003 02ff 	and.w	r2, r3, #255	; 0xff
 8000f16:	b91b      	cbnz	r3, 8000f20 <HAL_UART_Init+0x18>
    huart->Lock = HAL_UNLOCKED;
 8000f18:	f880 2038 	strb.w	r2, [r0, #56]	; 0x38
    HAL_UART_MspInit(huart);
 8000f1c:	f000 f9b8 	bl	8001290 <HAL_UART_MspInit>
  huart->gState = HAL_UART_STATE_BUSY;
 8000f20:	2324      	movs	r3, #36	; 0x24
  __HAL_UART_DISABLE(huart);
 8000f22:	6822      	ldr	r2, [r4, #0]
  huart->gState = HAL_UART_STATE_BUSY;
 8000f24:	f884 3039 	strb.w	r3, [r4, #57]	; 0x39
  __HAL_UART_DISABLE(huart);
 8000f28:	68d3      	ldr	r3, [r2, #12]
  UART_SetConfig(huart);
 8000f2a:	4620      	mov	r0, r4
  __HAL_UART_DISABLE(huart);
 8000f2c:	f423 5300 	bic.w	r3, r3, #8192	; 0x2000
 8000f30:	60d3      	str	r3, [r2, #12]
  UART_SetConfig(huart);
 8000f32:	f7ff ff4b 	bl	8000dcc <UART_SetConfig>
  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
 8000f36:	6823      	ldr	r3, [r4, #0]
  huart->ErrorCode = HAL_UART_ERROR_NONE;
 8000f38:	2000      	movs	r0, #0
  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
 8000f3a:	691a      	ldr	r2, [r3, #16]
 8000f3c:	f422 4290 	bic.w	r2, r2, #18432	; 0x4800
 8000f40:	611a      	str	r2, [r3, #16]
  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
 8000f42:	695a      	ldr	r2, [r3, #20]
 8000f44:	f022 022a 	bic.w	r2, r2, #42	; 0x2a
 8000f48:	615a      	str	r2, [r3, #20]
  __HAL_UART_ENABLE(huart);
 8000f4a:	68da      	ldr	r2, [r3, #12]
 8000f4c:	f442 5200 	orr.w	r2, r2, #8192	; 0x2000
 8000f50:	60da      	str	r2, [r3, #12]
  huart->gState= HAL_UART_STATE_READY;
 8000f52:	2320      	movs	r3, #32
  huart->ErrorCode = HAL_UART_ERROR_NONE;
 8000f54:	63e0      	str	r0, [r4, #60]	; 0x3c
  huart->gState= HAL_UART_STATE_READY;
 8000f56:	f884 3039 	strb.w	r3, [r4, #57]	; 0x39
  huart->RxState= HAL_UART_STATE_READY;
 8000f5a:	f884 303a 	strb.w	r3, [r4, #58]	; 0x3a
  return HAL_OK;
 8000f5e:	bd10      	pop	{r4, pc}
    return HAL_ERROR;
 8000f60:	2001      	movs	r0, #1
}
 8000f62:	bd10      	pop	{r4, pc}

08000f64 <HAL_UART_TxCpltCallback>:
 8000f64:	4770      	bx	lr

08000f66 <HAL_UART_RxCpltCallback>:
 8000f66:	4770      	bx	lr

08000f68 <UART_Receive_IT>:
  if(huart->RxState == HAL_UART_STATE_BUSY_RX) 
 8000f68:	f890 303a 	ldrb.w	r3, [r0, #58]	; 0x3a
{
 8000f6c:	b510      	push	{r4, lr}
  if(huart->RxState == HAL_UART_STATE_BUSY_RX) 
 8000f6e:	2b22      	cmp	r3, #34	; 0x22
 8000f70:	d136      	bne.n	8000fe0 <UART_Receive_IT+0x78>
    if(huart->Init.WordLength == UART_WORDLENGTH_9B)
 8000f72:	6883      	ldr	r3, [r0, #8]
 8000f74:	6901      	ldr	r1, [r0, #16]
 8000f76:	f5b3 5f80 	cmp.w	r3, #4096	; 0x1000
 8000f7a:	6802      	ldr	r2, [r0, #0]
 8000f7c:	6a83      	ldr	r3, [r0, #40]	; 0x28
 8000f7e:	d123      	bne.n	8000fc8 <UART_Receive_IT+0x60>
        *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
 8000f80:	6852      	ldr	r2, [r2, #4]
      if(huart->Init.Parity == UART_PARITY_NONE)
 8000f82:	b9e9      	cbnz	r1, 8000fc0 <UART_Receive_IT+0x58>
        *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
 8000f84:	f3c2 0208 	ubfx	r2, r2, #0, #9
 8000f88:	f823 2b02 	strh.w	r2, [r3], #2
        huart->pRxBuffPtr += 1U;
 8000f8c:	6283      	str	r3, [r0, #40]	; 0x28
    if(--huart->RxXferCount == 0U)
 8000f8e:	8dc4      	ldrh	r4, [r0, #46]	; 0x2e
 8000f90:	3c01      	subs	r4, #1
 8000f92:	b2a4      	uxth	r4, r4
 8000f94:	85c4      	strh	r4, [r0, #46]	; 0x2e
 8000f96:	b98c      	cbnz	r4, 8000fbc <UART_Receive_IT+0x54>
      __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
 8000f98:	6803      	ldr	r3, [r0, #0]
 8000f9a:	68da      	ldr	r2, [r3, #12]
 8000f9c:	f022 0220 	bic.w	r2, r2, #32
 8000fa0:	60da      	str	r2, [r3, #12]
      __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
 8000fa2:	68da      	ldr	r2, [r3, #12]
 8000fa4:	f422 7280 	bic.w	r2, r2, #256	; 0x100
 8000fa8:	60da      	str	r2, [r3, #12]
        __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
 8000faa:	695a      	ldr	r2, [r3, #20]
 8000fac:	f022 0201 	bic.w	r2, r2, #1
 8000fb0:	615a      	str	r2, [r3, #20]
      huart->RxState = HAL_UART_STATE_READY;
 8000fb2:	2320      	movs	r3, #32
 8000fb4:	f880 303a 	strb.w	r3, [r0, #58]	; 0x3a
      HAL_UART_RxCpltCallback(huart);
 8000fb8:	f7ff ffd5 	bl	8000f66 <HAL_UART_RxCpltCallback>
    if(--huart->RxXferCount == 0U)
 8000fbc:	2000      	movs	r0, #0
}
 8000fbe:	bd10      	pop	{r4, pc}
        *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF);
 8000fc0:	b2d2      	uxtb	r2, r2
 8000fc2:	f823 2b01 	strh.w	r2, [r3], #1
 8000fc6:	e7e1      	b.n	8000f8c <UART_Receive_IT+0x24>
      if(huart->Init.Parity == UART_PARITY_NONE)
 8000fc8:	b921      	cbnz	r1, 8000fd4 <UART_Receive_IT+0x6c>
        *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
 8000fca:	1c59      	adds	r1, r3, #1
 8000fcc:	6852      	ldr	r2, [r2, #4]
 8000fce:	6281      	str	r1, [r0, #40]	; 0x28
        *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
 8000fd0:	701a      	strb	r2, [r3, #0]
 8000fd2:	e7dc      	b.n	8000f8e <UART_Receive_IT+0x26>
 8000fd4:	6852      	ldr	r2, [r2, #4]
 8000fd6:	1c59      	adds	r1, r3, #1
 8000fd8:	6281      	str	r1, [r0, #40]	; 0x28
 8000fda:	f002 027f 	and.w	r2, r2, #127	; 0x7f
 8000fde:	e7f7      	b.n	8000fd0 <UART_Receive_IT+0x68>
    return HAL_BUSY;
 8000fe0:	2002      	movs	r0, #2
 8000fe2:	bd10      	pop	{r4, pc}

08000fe4 <HAL_UART_ErrorCallback>:
 8000fe4:	4770      	bx	lr
	...

08000fe8 <HAL_UART_IRQHandler>:
   uint32_t isrflags   = READ_REG(huart->Instance->SR);
 8000fe8:	6803      	ldr	r3, [r0, #0]
{
 8000fea:	b570      	push	{r4, r5, r6, lr}
   uint32_t isrflags   = READ_REG(huart->Instance->SR);
 8000fec:	681a      	ldr	r2, [r3, #0]
{
 8000fee:	4604      	mov	r4, r0
  if(errorflags == RESET)
 8000ff0:	0716      	lsls	r6, r2, #28
   uint32_t cr1its     = READ_REG(huart->Instance->CR1);
 8000ff2:	68d9      	ldr	r1, [r3, #12]
   uint32_t cr3its     = READ_REG(huart->Instance->CR3);
 8000ff4:	695d      	ldr	r5, [r3, #20]
  if(errorflags == RESET)
 8000ff6:	d107      	bne.n	8001008 <HAL_UART_IRQHandler+0x20>
    if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
 8000ff8:	0696      	lsls	r6, r2, #26
 8000ffa:	d55a      	bpl.n	80010b2 <HAL_UART_IRQHandler+0xca>
 8000ffc:	068d      	lsls	r5, r1, #26
 8000ffe:	d558      	bpl.n	80010b2 <HAL_UART_IRQHandler+0xca>
}
 8001000:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
      UART_Receive_IT(huart);
 8001004:	f7ff bfb0 	b.w	8000f68 <UART_Receive_IT>
  if((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
 8001008:	f015 0501 	ands.w	r5, r5, #1
 800100c:	d102      	bne.n	8001014 <HAL_UART_IRQHandler+0x2c>
 800100e:	f411 7f90 	tst.w	r1, #288	; 0x120
 8001012:	d04e      	beq.n	80010b2 <HAL_UART_IRQHandler+0xca>
    if(((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
 8001014:	07d3      	lsls	r3, r2, #31
 8001016:	d505      	bpl.n	8001024 <HAL_UART_IRQHandler+0x3c>
 8001018:	05ce      	lsls	r6, r1, #23
      huart->ErrorCode |= HAL_UART_ERROR_PE;
 800101a:	bf42      	ittt	mi
 800101c:	6be3      	ldrmi	r3, [r4, #60]	; 0x3c
 800101e:	f043 0301 	orrmi.w	r3, r3, #1
 8001022:	63e3      	strmi	r3, [r4, #60]	; 0x3c
    if(((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
 8001024:	0750      	lsls	r0, r2, #29
 8001026:	d504      	bpl.n	8001032 <HAL_UART_IRQHandler+0x4a>
 8001028:	b11d      	cbz	r5, 8001032 <HAL_UART_IRQHandler+0x4a>
      huart->ErrorCode |= HAL_UART_ERROR_NE;
 800102a:	6be3      	ldr	r3, [r4, #60]	; 0x3c
 800102c:	f043 0302 	orr.w	r3, r3, #2
 8001030:	63e3      	str	r3, [r4, #60]	; 0x3c
    if(((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
 8001032:	0793      	lsls	r3, r2, #30
 8001034:	d504      	bpl.n	8001040 <HAL_UART_IRQHandler+0x58>
 8001036:	b11d      	cbz	r5, 8001040 <HAL_UART_IRQHandler+0x58>
      huart->ErrorCode |= HAL_UART_ERROR_FE;
 8001038:	6be3      	ldr	r3, [r4, #60]	; 0x3c
 800103a:	f043 0304 	orr.w	r3, r3, #4
 800103e:	63e3      	str	r3, [r4, #60]	; 0x3c
    if(((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
 8001040:	0716      	lsls	r6, r2, #28
 8001042:	d504      	bpl.n	800104e <HAL_UART_IRQHandler+0x66>
 8001044:	b11d      	cbz	r5, 800104e <HAL_UART_IRQHandler+0x66>
      huart->ErrorCode |= HAL_UART_ERROR_ORE;
 8001046:	6be3      	ldr	r3, [r4, #60]	; 0x3c
 8001048:	f043 0308 	orr.w	r3, r3, #8
 800104c:	63e3      	str	r3, [r4, #60]	; 0x3c
    if(huart->ErrorCode != HAL_UART_ERROR_NONE)
 800104e:	6be3      	ldr	r3, [r4, #60]	; 0x3c
 8001050:	2b00      	cmp	r3, #0
 8001052:	d066      	beq.n	8001122 <HAL_UART_IRQHandler+0x13a>
      if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
 8001054:	0695      	lsls	r5, r2, #26
 8001056:	d504      	bpl.n	8001062 <HAL_UART_IRQHandler+0x7a>
 8001058:	0688      	lsls	r0, r1, #26
 800105a:	d502      	bpl.n	8001062 <HAL_UART_IRQHandler+0x7a>
        UART_Receive_IT(huart);
 800105c:	4620      	mov	r0, r4
 800105e:	f7ff ff83 	bl	8000f68 <UART_Receive_IT>
      dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
 8001062:	6823      	ldr	r3, [r4, #0]
        UART_EndRxTransfer(huart);
 8001064:	4620      	mov	r0, r4
      dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
 8001066:	695d      	ldr	r5, [r3, #20]
      if(((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest)
 8001068:	6be2      	ldr	r2, [r4, #60]	; 0x3c
 800106a:	0711      	lsls	r1, r2, #28
 800106c:	d402      	bmi.n	8001074 <HAL_UART_IRQHandler+0x8c>
 800106e:	f015 0540 	ands.w	r5, r5, #64	; 0x40
 8001072:	d01a      	beq.n	80010aa <HAL_UART_IRQHandler+0xc2>
        UART_EndRxTransfer(huart);
 8001074:	f7ff fe9c 	bl	8000db0 <UART_EndRxTransfer>
        if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
 8001078:	6823      	ldr	r3, [r4, #0]
 800107a:	695a      	ldr	r2, [r3, #20]
 800107c:	0652      	lsls	r2, r2, #25
 800107e:	d510      	bpl.n	80010a2 <HAL_UART_IRQHandler+0xba>
          CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
 8001080:	695a      	ldr	r2, [r3, #20]
          if(huart->hdmarx != NULL)
 8001082:	6b60      	ldr	r0, [r4, #52]	; 0x34
          CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
 8001084:	f022 0240 	bic.w	r2, r2, #64	; 0x40
 8001088:	615a      	str	r2, [r3, #20]
          if(huart->hdmarx != NULL)
 800108a:	b150      	cbz	r0, 80010a2 <HAL_UART_IRQHandler+0xba>
            huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
 800108c:	4b25      	ldr	r3, [pc, #148]	; (8001124 <HAL_UART_IRQHandler+0x13c>)
 800108e:	6343      	str	r3, [r0, #52]	; 0x34
            if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
 8001090:	f7ff f9b8 	bl	8000404 <HAL_DMA_Abort_IT>
 8001094:	2800      	cmp	r0, #0
 8001096:	d044      	beq.n	8001122 <HAL_UART_IRQHandler+0x13a>
              huart->hdmarx->XferAbortCallback(huart->hdmarx);
 8001098:	6b60      	ldr	r0, [r4, #52]	; 0x34
}
 800109a:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
              huart->hdmarx->XferAbortCallback(huart->hdmarx);
 800109e:	6b43      	ldr	r3, [r0, #52]	; 0x34
 80010a0:	4718      	bx	r3
            HAL_UART_ErrorCallback(huart);
 80010a2:	4620      	mov	r0, r4
 80010a4:	f7ff ff9e 	bl	8000fe4 <HAL_UART_ErrorCallback>
 80010a8:	bd70      	pop	{r4, r5, r6, pc}
        HAL_UART_ErrorCallback(huart);
 80010aa:	f7ff ff9b 	bl	8000fe4 <HAL_UART_ErrorCallback>
        huart->ErrorCode = HAL_UART_ERROR_NONE;
 80010ae:	63e5      	str	r5, [r4, #60]	; 0x3c
 80010b0:	bd70      	pop	{r4, r5, r6, pc}
  if(((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
 80010b2:	0616      	lsls	r6, r2, #24
 80010b4:	d527      	bpl.n	8001106 <HAL_UART_IRQHandler+0x11e>
 80010b6:	060d      	lsls	r5, r1, #24
 80010b8:	d525      	bpl.n	8001106 <HAL_UART_IRQHandler+0x11e>
  if(huart->gState == HAL_UART_STATE_BUSY_TX)
 80010ba:	f894 2039 	ldrb.w	r2, [r4, #57]	; 0x39
 80010be:	2a21      	cmp	r2, #33	; 0x21
 80010c0:	d12f      	bne.n	8001122 <HAL_UART_IRQHandler+0x13a>
    if(huart->Init.WordLength == UART_WORDLENGTH_9B)
 80010c2:	68a2      	ldr	r2, [r4, #8]
 80010c4:	f5b2 5f80 	cmp.w	r2, #4096	; 0x1000
 80010c8:	6a22      	ldr	r2, [r4, #32]
 80010ca:	d117      	bne.n	80010fc <HAL_UART_IRQHandler+0x114>
      huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
 80010cc:	8811      	ldrh	r1, [r2, #0]
 80010ce:	f3c1 0108 	ubfx	r1, r1, #0, #9
 80010d2:	6059      	str	r1, [r3, #4]
      if(huart->Init.Parity == UART_PARITY_NONE)
 80010d4:	6921      	ldr	r1, [r4, #16]
 80010d6:	b979      	cbnz	r1, 80010f8 <HAL_UART_IRQHandler+0x110>
        huart->pTxBuffPtr += 2U;
 80010d8:	3202      	adds	r2, #2
        huart->pTxBuffPtr += 1U;
 80010da:	6222      	str	r2, [r4, #32]
    if(--huart->TxXferCount == 0U)
 80010dc:	8ce2      	ldrh	r2, [r4, #38]	; 0x26
 80010de:	3a01      	subs	r2, #1
 80010e0:	b292      	uxth	r2, r2
 80010e2:	84e2      	strh	r2, [r4, #38]	; 0x26
 80010e4:	b9ea      	cbnz	r2, 8001122 <HAL_UART_IRQHandler+0x13a>
      __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
 80010e6:	68da      	ldr	r2, [r3, #12]
 80010e8:	f022 0280 	bic.w	r2, r2, #128	; 0x80
 80010ec:	60da      	str	r2, [r3, #12]
      __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
 80010ee:	68da      	ldr	r2, [r3, #12]
 80010f0:	f042 0240 	orr.w	r2, r2, #64	; 0x40
 80010f4:	60da      	str	r2, [r3, #12]
 80010f6:	bd70      	pop	{r4, r5, r6, pc}
        huart->pTxBuffPtr += 1U;
 80010f8:	3201      	adds	r2, #1
 80010fa:	e7ee      	b.n	80010da <HAL_UART_IRQHandler+0xf2>
      huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF);
 80010fc:	1c51      	adds	r1, r2, #1
 80010fe:	6221      	str	r1, [r4, #32]
 8001100:	7812      	ldrb	r2, [r2, #0]
 8001102:	605a      	str	r2, [r3, #4]
 8001104:	e7ea      	b.n	80010dc <HAL_UART_IRQHandler+0xf4>
  if(((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
 8001106:	0650      	lsls	r0, r2, #25
 8001108:	d50b      	bpl.n	8001122 <HAL_UART_IRQHandler+0x13a>
 800110a:	064a      	lsls	r2, r1, #25
 800110c:	d509      	bpl.n	8001122 <HAL_UART_IRQHandler+0x13a>
  __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
 800110e:	68da      	ldr	r2, [r3, #12]
  HAL_UART_TxCpltCallback(huart);
 8001110:	4620      	mov	r0, r4
  __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
 8001112:	f022 0240 	bic.w	r2, r2, #64	; 0x40
 8001116:	60da      	str	r2, [r3, #12]
  huart->gState = HAL_UART_STATE_READY;
 8001118:	2320      	movs	r3, #32
 800111a:	f884 3039 	strb.w	r3, [r4, #57]	; 0x39
  HAL_UART_TxCpltCallback(huart);
 800111e:	f7ff ff21 	bl	8000f64 <HAL_UART_TxCpltCallback>
 8001122:	bd70      	pop	{r4, r5, r6, pc}
 8001124:	08001129 	.word	0x08001129

08001128 <UART_DMAAbortOnError>:
{
 8001128:	b508      	push	{r3, lr}
  huart->RxXferCount = 0x00U;
 800112a:	2300      	movs	r3, #0
  UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
 800112c:	6a40      	ldr	r0, [r0, #36]	; 0x24
  huart->RxXferCount = 0x00U;
 800112e:	85c3      	strh	r3, [r0, #46]	; 0x2e
  huart->TxXferCount = 0x00U;
 8001130:	84c3      	strh	r3, [r0, #38]	; 0x26
  HAL_UART_ErrorCallback(huart);
 8001132:	f7ff ff57 	bl	8000fe4 <HAL_UART_ErrorCallback>
 8001136:	bd08      	pop	{r3, pc}

08001138 <SystemClock_Config>:
/**
  * @brief System Clock Configuration
  * @retval None
  */
void SystemClock_Config(void)
{
 8001138:	b510      	push	{r4, lr}
 800113a:	b090      	sub	sp, #64	; 0x40
  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
 800113c:	2228      	movs	r2, #40	; 0x28
 800113e:	2100      	movs	r1, #0
 8001140:	a806      	add	r0, sp, #24
 8001142:	f000 f99d 	bl	8001480 <memset>
  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 8001146:	2214      	movs	r2, #20
 8001148:	2100      	movs	r1, #0
 800114a:	a801      	add	r0, sp, #4
 800114c:	f000 f998 	bl	8001480 <memset>

  /** Initializes the CPU, AHB and APB busses clocks 
  */
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
 8001150:	2301      	movs	r3, #1
 8001152:	930a      	str	r3, [sp, #40]	; 0x28
  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
 8001154:	2310      	movs	r3, #16
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
 8001156:	2402      	movs	r4, #2
  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
 8001158:	930b      	str	r3, [sp, #44]	; 0x2c
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2;
  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL15;
 800115a:	f44f 1350 	mov.w	r3, #3407872	; 0x340000
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 800115e:	a806      	add	r0, sp, #24
  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL15;
 8001160:	930f      	str	r3, [sp, #60]	; 0x3c
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
 8001162:	9406      	str	r4, [sp, #24]
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
 8001164:	940d      	str	r4, [sp, #52]	; 0x34
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 8001166:	f7ff fb89 	bl	800087c <HAL_RCC_OscConfig>
  {
    Error_Handler();
  }
  /** Initializes the CPU, AHB and APB busses clocks 
  */
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
 800116a:	230f      	movs	r3, #15
                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
 800116c:	f44f 6280 	mov.w	r2, #1024	; 0x400
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
 8001170:	9301      	str	r3, [sp, #4]
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
 8001172:	2300      	movs	r3, #0
  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;

  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
 8001174:	4621      	mov	r1, r4
 8001176:	a801      	add	r0, sp, #4
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
 8001178:	9402      	str	r4, [sp, #8]
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
 800117a:	9303      	str	r3, [sp, #12]
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
 800117c:	9204      	str	r2, [sp, #16]
  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
 800117e:	9305      	str	r3, [sp, #20]
  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
 8001180:	f7ff fd44 	bl	8000c0c <HAL_RCC_ClockConfig>
  {
    Error_Handler();
  }
}
 8001184:	b010      	add	sp, #64	; 0x40
 8001186:	bd10      	pop	{r4, pc}

08001188 <main>:
{
 8001188:	b57f      	push	{r0, r1, r2, r3, r4, r5, r6, lr}
static void MX_GPIO_Init(void)
{
  GPIO_InitTypeDef GPIO_InitStruct = {0};

  /* GPIO Ports Clock Enable */
  __HAL_RCC_GPIOA_CLK_ENABLE();
 800118a:	4d2b      	ldr	r5, [pc, #172]	; (8001238 <main+0xb0>)
  HAL_Init();
 800118c:	f7ff f86e 	bl	800026c <HAL_Init>
  SystemClock_Config();
 8001190:	f7ff ffd2 	bl	8001138 <SystemClock_Config>
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8001194:	2210      	movs	r2, #16
 8001196:	2100      	movs	r1, #0
 8001198:	a802      	add	r0, sp, #8
 800119a:	f000 f971 	bl	8001480 <memset>
  __HAL_RCC_GPIOA_CLK_ENABLE();
 800119e:	69ab      	ldr	r3, [r5, #24]

  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(GPIOA, GPIO_PIN_15, GPIO_PIN_RESET);
 80011a0:	2200      	movs	r2, #0
  __HAL_RCC_GPIOA_CLK_ENABLE();
 80011a2:	f043 0304 	orr.w	r3, r3, #4
 80011a6:	61ab      	str	r3, [r5, #24]
 80011a8:	69ab      	ldr	r3, [r5, #24]
  HAL_GPIO_WritePin(GPIOA, GPIO_PIN_15, GPIO_PIN_RESET);
 80011aa:	f44f 4100 	mov.w	r1, #32768	; 0x8000
  __HAL_RCC_GPIOA_CLK_ENABLE();
 80011ae:	f003 0304 	and.w	r3, r3, #4
 80011b2:	9301      	str	r3, [sp, #4]
  HAL_GPIO_WritePin(GPIOA, GPIO_PIN_15, GPIO_PIN_RESET);
 80011b4:	4821      	ldr	r0, [pc, #132]	; (800123c <main+0xb4>)
  __HAL_RCC_GPIOA_CLK_ENABLE();
 80011b6:	9b01      	ldr	r3, [sp, #4]
  HAL_GPIO_WritePin(GPIOA, GPIO_PIN_15, GPIO_PIN_RESET);
 80011b8:	f7ff fb5a 	bl	8000870 <HAL_GPIO_WritePin>

  /*Configure GPIO pin : PA15 */
  GPIO_InitStruct.Pin = GPIO_PIN_15;
 80011bc:	f44f 4300 	mov.w	r3, #32768	; 0x8000
 80011c0:	9302      	str	r3, [sp, #8]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 80011c2:	2301      	movs	r3, #1
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 80011c4:	2400      	movs	r4, #0
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 80011c6:	9303      	str	r3, [sp, #12]
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 80011c8:	2302      	movs	r3, #2
  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 80011ca:	a902      	add	r1, sp, #8
 80011cc:	481b      	ldr	r0, [pc, #108]	; (800123c <main+0xb4>)
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 80011ce:	9305      	str	r3, [sp, #20]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 80011d0:	9404      	str	r4, [sp, #16]
  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 80011d2:	f7ff fa61 	bl	8000698 <HAL_GPIO_Init>
  __HAL_RCC_DMA1_CLK_ENABLE();
 80011d6:	696b      	ldr	r3, [r5, #20]
  huart1.Instance = USART1;
 80011d8:	4819      	ldr	r0, [pc, #100]	; (8001240 <main+0xb8>)
  __HAL_RCC_DMA1_CLK_ENABLE();
 80011da:	f043 0301 	orr.w	r3, r3, #1
 80011de:	616b      	str	r3, [r5, #20]
 80011e0:	696b      	ldr	r3, [r5, #20]
  huart1.Init.BaudRate = 115200;
 80011e2:	4a18      	ldr	r2, [pc, #96]	; (8001244 <main+0xbc>)
  __HAL_RCC_DMA1_CLK_ENABLE();
 80011e4:	f003 0301 	and.w	r3, r3, #1
 80011e8:	9302      	str	r3, [sp, #8]
 80011ea:	9b02      	ldr	r3, [sp, #8]
  huart1.Init.BaudRate = 115200;
 80011ec:	f44f 33e1 	mov.w	r3, #115200	; 0x1c200
 80011f0:	e880 000c 	stmia.w	r0, {r2, r3}
  huart1.Init.Mode = UART_MODE_TX_RX;
 80011f4:	230c      	movs	r3, #12
  huart1.Init.WordLength = UART_WORDLENGTH_8B;
 80011f6:	6084      	str	r4, [r0, #8]
  huart1.Init.Mode = UART_MODE_TX_RX;
 80011f8:	6143      	str	r3, [r0, #20]
  huart1.Init.StopBits = UART_STOPBITS_1;
 80011fa:	60c4      	str	r4, [r0, #12]
  huart1.Init.Parity = UART_PARITY_NONE;
 80011fc:	6104      	str	r4, [r0, #16]
  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
 80011fe:	6184      	str	r4, [r0, #24]
  huart1.Init.OverSampling = UART_OVERSAMPLING_16;
 8001200:	61c4      	str	r4, [r0, #28]
  if (HAL_UART_Init(&huart1) != HAL_OK)
 8001202:	f7ff fe81 	bl	8000f08 <HAL_UART_Init>
  HAL_NVIC_SetPriority(DMA1_Channel5_IRQn, 0, 0);
 8001206:	4622      	mov	r2, r4
 8001208:	4621      	mov	r1, r4
 800120a:	200f      	movs	r0, #15
 800120c:	f7ff f864 	bl	80002d8 <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(DMA1_Channel5_IRQn);
 8001210:	200f      	movs	r0, #15
 8001212:	f7ff f895 	bl	8000340 <HAL_NVIC_EnableIRQ>
  HAL_NVIC_SetPriority(DMA1_Channel4_IRQn, 0, 0);
 8001216:	4622      	mov	r2, r4
 8001218:	4621      	mov	r1, r4
 800121a:	200e      	movs	r0, #14
 800121c:	f7ff f85c 	bl	80002d8 <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(DMA1_Channel4_IRQn);
 8001220:	200e      	movs	r0, #14
 8001222:	f7ff f88d 	bl	8000340 <HAL_NVIC_EnableIRQ>
  HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
 8001226:	2025      	movs	r0, #37	; 0x25
 8001228:	4622      	mov	r2, r4
 800122a:	4621      	mov	r1, r4
 800122c:	f7ff f854 	bl	80002d8 <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(USART1_IRQn);
 8001230:	2025      	movs	r0, #37	; 0x25
 8001232:	f7ff f885 	bl	8000340 <HAL_NVIC_EnableIRQ>
 8001236:	e7fe      	b.n	8001236 <main+0xae>
 8001238:	40021000 	.word	0x40021000
 800123c:	40010800 	.word	0x40010800
 8001240:	200000b4 	.word	0x200000b4
 8001244:	40013800 	.word	0x40013800

08001248 <Error_Handler>:
/**
  * @brief  This function is executed in case of error occurrence.
  * @retval None
  */
void Error_Handler(void)
{
 8001248:	4770      	bx	lr
	...

0800124c <HAL_MspInit>:
{
  /* USER CODE BEGIN MspInit 0 */

  /* USER CODE END MspInit 0 */

  __HAL_RCC_AFIO_CLK_ENABLE();
 800124c:	4b0e      	ldr	r3, [pc, #56]	; (8001288 <HAL_MspInit+0x3c>)
{
 800124e:	b082      	sub	sp, #8
  __HAL_RCC_AFIO_CLK_ENABLE();
 8001250:	699a      	ldr	r2, [r3, #24]
 8001252:	f042 0201 	orr.w	r2, r2, #1
 8001256:	619a      	str	r2, [r3, #24]
 8001258:	699a      	ldr	r2, [r3, #24]
 800125a:	f002 0201 	and.w	r2, r2, #1
 800125e:	9200      	str	r2, [sp, #0]
 8001260:	9a00      	ldr	r2, [sp, #0]
  __HAL_RCC_PWR_CLK_ENABLE();
 8001262:	69da      	ldr	r2, [r3, #28]
 8001264:	f042 5280 	orr.w	r2, r2, #268435456	; 0x10000000
 8001268:	61da      	str	r2, [r3, #28]
 800126a:	69db      	ldr	r3, [r3, #28]

  /* System interrupt init*/

  /** DISABLE: JTAG-DP Disabled and SW-DP Disabled 
  */
  __HAL_AFIO_REMAP_SWJ_DISABLE();
 800126c:	4a07      	ldr	r2, [pc, #28]	; (800128c <HAL_MspInit+0x40>)
  __HAL_RCC_PWR_CLK_ENABLE();
 800126e:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8001272:	9301      	str	r3, [sp, #4]
 8001274:	9b01      	ldr	r3, [sp, #4]
  __HAL_AFIO_REMAP_SWJ_DISABLE();
 8001276:	6853      	ldr	r3, [r2, #4]
 8001278:	f023 63e0 	bic.w	r3, r3, #117440512	; 0x7000000
 800127c:	f043 6380 	orr.w	r3, r3, #67108864	; 0x4000000
 8001280:	6053      	str	r3, [r2, #4]

  /* USER CODE BEGIN MspInit 1 */

  /* USER CODE END MspInit 1 */
}
 8001282:	b002      	add	sp, #8
 8001284:	4770      	bx	lr
 8001286:	bf00      	nop
 8001288:	40021000 	.word	0x40021000
 800128c:	40010000 	.word	0x40010000

08001290 <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
 8001290:	b570      	push	{r4, r5, r6, lr}
 8001292:	4606      	mov	r6, r0
 8001294:	b086      	sub	sp, #24
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8001296:	2210      	movs	r2, #16
 8001298:	2100      	movs	r1, #0
 800129a:	a802      	add	r0, sp, #8
 800129c:	f000 f8f0 	bl	8001480 <memset>
  if(huart->Instance==USART1)
 80012a0:	6832      	ldr	r2, [r6, #0]
 80012a2:	4b2b      	ldr	r3, [pc, #172]	; (8001350 <HAL_UART_MspInit+0xc0>)
 80012a4:	429a      	cmp	r2, r3
 80012a6:	d151      	bne.n	800134c <HAL_UART_MspInit+0xbc>
  {
  /* USER CODE BEGIN USART1_MspInit 0 */

  /* USER CODE END USART1_MspInit 0 */
    /* Peripheral clock enable */
    __HAL_RCC_USART1_CLK_ENABLE();
 80012a8:	f503 4358 	add.w	r3, r3, #55296	; 0xd800
 80012ac:	699a      	ldr	r2, [r3, #24]
    PA10     ------> USART1_RX 
    */
    GPIO_InitStruct.Pin = GPIO_PIN_9;
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 80012ae:	a902      	add	r1, sp, #8
    __HAL_RCC_USART1_CLK_ENABLE();
 80012b0:	f442 4280 	orr.w	r2, r2, #16384	; 0x4000
 80012b4:	619a      	str	r2, [r3, #24]
 80012b6:	699a      	ldr	r2, [r3, #24]
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 80012b8:	4826      	ldr	r0, [pc, #152]	; (8001354 <HAL_UART_MspInit+0xc4>)
    __HAL_RCC_USART1_CLK_ENABLE();
 80012ba:	f402 4280 	and.w	r2, r2, #16384	; 0x4000
 80012be:	9200      	str	r2, [sp, #0]
 80012c0:	9a00      	ldr	r2, [sp, #0]
    __HAL_RCC_GPIOA_CLK_ENABLE();
 80012c2:	699a      	ldr	r2, [r3, #24]

    GPIO_InitStruct.Pin = GPIO_PIN_10;
    GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
 80012c4:	2500      	movs	r5, #0
    __HAL_RCC_GPIOA_CLK_ENABLE();
 80012c6:	f042 0204 	orr.w	r2, r2, #4
 80012ca:	619a      	str	r2, [r3, #24]
 80012cc:	699b      	ldr	r3, [r3, #24]
    GPIO_InitStruct.Pull = GPIO_NOPULL;
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);

    /* USART1 DMA Init */
    /* USART1_RX Init */
    hdma_usart1_rx.Instance = DMA1_Channel5;
 80012ce:	4c22      	ldr	r4, [pc, #136]	; (8001358 <HAL_UART_MspInit+0xc8>)
    __HAL_RCC_GPIOA_CLK_ENABLE();
 80012d0:	f003 0304 	and.w	r3, r3, #4
 80012d4:	9301      	str	r3, [sp, #4]
 80012d6:	9b01      	ldr	r3, [sp, #4]
    GPIO_InitStruct.Pin = GPIO_PIN_9;
 80012d8:	f44f 7300 	mov.w	r3, #512	; 0x200
 80012dc:	9302      	str	r3, [sp, #8]
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 80012de:	2302      	movs	r3, #2
 80012e0:	9303      	str	r3, [sp, #12]
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
 80012e2:	2303      	movs	r3, #3
 80012e4:	9305      	str	r3, [sp, #20]
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 80012e6:	f7ff f9d7 	bl	8000698 <HAL_GPIO_Init>
    GPIO_InitStruct.Pin = GPIO_PIN_10;
 80012ea:	f44f 6380 	mov.w	r3, #1024	; 0x400
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 80012ee:	4819      	ldr	r0, [pc, #100]	; (8001354 <HAL_UART_MspInit+0xc4>)
 80012f0:	a902      	add	r1, sp, #8
    GPIO_InitStruct.Pin = GPIO_PIN_10;
 80012f2:	9302      	str	r3, [sp, #8]
    GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
 80012f4:	9503      	str	r5, [sp, #12]
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 80012f6:	9504      	str	r5, [sp, #16]
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 80012f8:	f7ff f9ce 	bl	8000698 <HAL_GPIO_Init>
    hdma_usart1_rx.Instance = DMA1_Channel5;
 80012fc:	4b17      	ldr	r3, [pc, #92]	; (800135c <HAL_UART_MspInit+0xcc>)
    hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE;
    hdma_usart1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
    hdma_usart1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
    hdma_usart1_rx.Init.Mode = DMA_NORMAL;
    hdma_usart1_rx.Init.Priority = DMA_PRIORITY_LOW;
    if (HAL_DMA_Init(&hdma_usart1_rx) != HAL_OK)
 80012fe:	4620      	mov	r0, r4
    hdma_usart1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
 8001300:	e884 0028 	stmia.w	r4, {r3, r5}
    hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE;
 8001304:	2380      	movs	r3, #128	; 0x80
    hdma_usart1_rx.Init.PeriphInc = DMA_PINC_DISABLE;
 8001306:	60a5      	str	r5, [r4, #8]
    hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE;
 8001308:	60e3      	str	r3, [r4, #12]
    hdma_usart1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
 800130a:	6125      	str	r5, [r4, #16]
    hdma_usart1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
 800130c:	6165      	str	r5, [r4, #20]
    hdma_usart1_rx.Init.Mode = DMA_NORMAL;
 800130e:	61a5      	str	r5, [r4, #24]
    hdma_usart1_rx.Init.Priority = DMA_PRIORITY_LOW;
 8001310:	61e5      	str	r5, [r4, #28]
    if (HAL_DMA_Init(&hdma_usart1_rx) != HAL_OK)
 8001312:	f7ff f837 	bl	8000384 <HAL_DMA_Init>
 8001316:	b108      	cbz	r0, 800131c <HAL_UART_MspInit+0x8c>
    {
      Error_Handler();
 8001318:	f7ff ff96 	bl	8001248 <Error_Handler>

    __HAL_LINKDMA(huart,hdmarx,hdma_usart1_rx);

    /* USART1_TX Init */
    hdma_usart1_tx.Instance = DMA1_Channel4;
    hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
 800131c:	f04f 0c10 	mov.w	ip, #16
 8001320:	4b0f      	ldr	r3, [pc, #60]	; (8001360 <HAL_UART_MspInit+0xd0>)
    __HAL_LINKDMA(huart,hdmarx,hdma_usart1_rx);
 8001322:	6374      	str	r4, [r6, #52]	; 0x34
 8001324:	6266      	str	r6, [r4, #36]	; 0x24
    hdma_usart1_tx.Instance = DMA1_Channel4;
 8001326:	4c0f      	ldr	r4, [pc, #60]	; (8001364 <HAL_UART_MspInit+0xd4>)
    hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
    hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE;
 8001328:	2280      	movs	r2, #128	; 0x80
    hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
 800132a:	e884 1008 	stmia.w	r4, {r3, ip}
    hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
 800132e:	2300      	movs	r3, #0
    hdma_usart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
    hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
    hdma_usart1_tx.Init.Mode = DMA_NORMAL;
    hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW;
    if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK)
 8001330:	4620      	mov	r0, r4
    hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
 8001332:	60a3      	str	r3, [r4, #8]
    hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE;
 8001334:	60e2      	str	r2, [r4, #12]
    hdma_usart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
 8001336:	6123      	str	r3, [r4, #16]
    hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
 8001338:	6163      	str	r3, [r4, #20]
    hdma_usart1_tx.Init.Mode = DMA_NORMAL;
 800133a:	61a3      	str	r3, [r4, #24]
    hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW;
 800133c:	61e3      	str	r3, [r4, #28]
    if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK)
 800133e:	f7ff f821 	bl	8000384 <HAL_DMA_Init>
 8001342:	b108      	cbz	r0, 8001348 <HAL_UART_MspInit+0xb8>
    {
      Error_Handler();
 8001344:	f7ff ff80 	bl	8001248 <Error_Handler>
    }

    __HAL_LINKDMA(huart,hdmatx,hdma_usart1_tx);
 8001348:	6334      	str	r4, [r6, #48]	; 0x30
 800134a:	6266      	str	r6, [r4, #36]	; 0x24
  /* USER CODE BEGIN USART1_MspInit 1 */

  /* USER CODE END USART1_MspInit 1 */
  }

}
 800134c:	b006      	add	sp, #24
 800134e:	bd70      	pop	{r4, r5, r6, pc}
 8001350:	40013800 	.word	0x40013800
 8001354:	40010800 	.word	0x40010800
 8001358:	20000070 	.word	0x20000070
 800135c:	40020058 	.word	0x40020058
 8001360:	40020044 	.word	0x40020044
 8001364:	2000002c 	.word	0x2000002c

08001368 <NMI_Handler>:
 8001368:	4770      	bx	lr

0800136a <HardFault_Handler>:

/**
  * @brief This function handles Hard fault interrupt.
  */
void HardFault_Handler(void)
{
 800136a:	e7fe      	b.n	800136a <HardFault_Handler>

0800136c <MemManage_Handler>:

/**
  * @brief This function handles Memory management fault.
  */
void MemManage_Handler(void)
{
 800136c:	e7fe      	b.n	800136c <MemManage_Handler>

0800136e <BusFault_Handler>:

/**
  * @brief This function handles Prefetch fault, memory access fault.
  */
void BusFault_Handler(void)
{
 800136e:	e7fe      	b.n	800136e <BusFault_Handler>

08001370 <UsageFault_Handler>:

/**
  * @brief This function handles Undefined instruction or illegal state.
  */
void UsageFault_Handler(void)
{
 8001370:	e7fe      	b.n	8001370 <UsageFault_Handler>

08001372 <SVC_Handler>:
 8001372:	4770      	bx	lr

08001374 <DebugMon_Handler>:
 8001374:	4770      	bx	lr

08001376 <PendSV_Handler>:

/**
  * @brief This function handles Pendable request for system service.
  */
void PendSV_Handler(void)
{
 8001376:	4770      	bx	lr

08001378 <SysTick_Handler>:
void SysTick_Handler(void)
{
  /* USER CODE BEGIN SysTick_IRQn 0 */

  /* USER CODE END SysTick_IRQn 0 */
  HAL_IncTick();
 8001378:	f7fe bf8a 	b.w	8000290 <HAL_IncTick>

0800137c <DMA1_Channel4_IRQHandler>:
void DMA1_Channel4_IRQHandler(void)
{
  /* USER CODE BEGIN DMA1_Channel4_IRQn 0 */

  /* USER CODE END DMA1_Channel4_IRQn 0 */
  HAL_DMA_IRQHandler(&hdma_usart1_tx);
 800137c:	4801      	ldr	r0, [pc, #4]	; (8001384 <DMA1_Channel4_IRQHandler+0x8>)
 800137e:	f7ff b8af 	b.w	80004e0 <HAL_DMA_IRQHandler>
 8001382:	bf00      	nop
 8001384:	2000002c 	.word	0x2000002c

08001388 <DMA1_Channel5_IRQHandler>:
void DMA1_Channel5_IRQHandler(void)
{
  /* USER CODE BEGIN DMA1_Channel5_IRQn 0 */

  /* USER CODE END DMA1_Channel5_IRQn 0 */
  HAL_DMA_IRQHandler(&hdma_usart1_rx);
 8001388:	4801      	ldr	r0, [pc, #4]	; (8001390 <DMA1_Channel5_IRQHandler+0x8>)
 800138a:	f7ff b8a9 	b.w	80004e0 <HAL_DMA_IRQHandler>
 800138e:	bf00      	nop
 8001390:	20000070 	.word	0x20000070

08001394 <USART1_IRQHandler>:
void USART1_IRQHandler(void)
{
  /* USER CODE BEGIN USART1_IRQn 0 */

  /* USER CODE END USART1_IRQn 0 */
  HAL_UART_IRQHandler(&huart1);
 8001394:	4801      	ldr	r0, [pc, #4]	; (800139c <USART1_IRQHandler+0x8>)
 8001396:	f7ff be27 	b.w	8000fe8 <HAL_UART_IRQHandler>
 800139a:	bf00      	nop
 800139c:	200000b4 	.word	0x200000b4

080013a0 <SystemInit>:
  */
void SystemInit (void)
{
  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
  /* Set HSION bit */
  RCC->CR |= 0x00000001U;
 80013a0:	4b0f      	ldr	r3, [pc, #60]	; (80013e0 <SystemInit+0x40>)
 80013a2:	681a      	ldr	r2, [r3, #0]
 80013a4:	f042 0201 	orr.w	r2, r2, #1
 80013a8:	601a      	str	r2, [r3, #0]

  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
#if !defined(STM32F105xC) && !defined(STM32F107xC)
  RCC->CFGR &= 0xF8FF0000U;
 80013aa:	6859      	ldr	r1, [r3, #4]
 80013ac:	4a0d      	ldr	r2, [pc, #52]	; (80013e4 <SystemInit+0x44>)
 80013ae:	400a      	ands	r2, r1
 80013b0:	605a      	str	r2, [r3, #4]
#else
  RCC->CFGR &= 0xF0FF0000U;
#endif /* STM32F105xC */   
  
  /* Reset HSEON, CSSON and PLLON bits */
  RCC->CR &= 0xFEF6FFFFU;
 80013b2:	681a      	ldr	r2, [r3, #0]
 80013b4:	f022 7284 	bic.w	r2, r2, #17301504	; 0x1080000
 80013b8:	f422 3280 	bic.w	r2, r2, #65536	; 0x10000
 80013bc:	601a      	str	r2, [r3, #0]

  /* Reset HSEBYP bit */
  RCC->CR &= 0xFFFBFFFFU;
 80013be:	681a      	ldr	r2, [r3, #0]
 80013c0:	f422 2280 	bic.w	r2, r2, #262144	; 0x40000
 80013c4:	601a      	str	r2, [r3, #0]

  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
  RCC->CFGR &= 0xFF80FFFFU;
 80013c6:	685a      	ldr	r2, [r3, #4]
 80013c8:	f422 02fe 	bic.w	r2, r2, #8323072	; 0x7f0000
 80013cc:	605a      	str	r2, [r3, #4]

  /* Reset CFGR2 register */
  RCC->CFGR2 = 0x00000000U;      
#else
  /* Disable all interrupts and clear pending bits  */
  RCC->CIR = 0x009F0000U;
 80013ce:	f44f 021f 	mov.w	r2, #10420224	; 0x9f0000
 80013d2:	609a      	str	r2, [r3, #8]
#endif 

#ifdef VECT_TAB_SRAM
  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#else
  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
 80013d4:	f04f 6200 	mov.w	r2, #134217728	; 0x8000000
 80013d8:	4b03      	ldr	r3, [pc, #12]	; (80013e8 <SystemInit+0x48>)
 80013da:	609a      	str	r2, [r3, #8]
 80013dc:	4770      	bx	lr
 80013de:	bf00      	nop
 80013e0:	40021000 	.word	0x40021000
 80013e4:	f8ff0000 	.word	0xf8ff0000
 80013e8:	e000ed00 	.word	0xe000ed00

080013ec <Reset_Handler>:
  .weak Reset_Handler
  .type Reset_Handler, %function
Reset_Handler:

/* Copy the data segment initializers from flash to SRAM */
  movs r1, #0
 80013ec:	2100      	movs	r1, #0
  b LoopCopyDataInit
 80013ee:	e003      	b.n	80013f8 <LoopCopyDataInit>

080013f0 <CopyDataInit>:

CopyDataInit:
  ldr r3, =_sidata
 80013f0:	4b0b      	ldr	r3, [pc, #44]	; (8001420 <LoopFillZerobss+0x14>)
  ldr r3, [r3, r1]
 80013f2:	585b      	ldr	r3, [r3, r1]
  str r3, [r0, r1]
 80013f4:	5043      	str	r3, [r0, r1]
  adds r1, r1, #4
 80013f6:	3104      	adds	r1, #4

080013f8 <LoopCopyDataInit>:

LoopCopyDataInit:
  ldr r0, =_sdata
 80013f8:	480a      	ldr	r0, [pc, #40]	; (8001424 <LoopFillZerobss+0x18>)
  ldr r3, =_edata
 80013fa:	4b0b      	ldr	r3, [pc, #44]	; (8001428 <LoopFillZerobss+0x1c>)
  adds r2, r0, r1
 80013fc:	1842      	adds	r2, r0, r1
  cmp r2, r3
 80013fe:	429a      	cmp	r2, r3
  bcc CopyDataInit
 8001400:	d3f6      	bcc.n	80013f0 <CopyDataInit>
  ldr r2, =_sbss
 8001402:	4a0a      	ldr	r2, [pc, #40]	; (800142c <LoopFillZerobss+0x20>)
  b LoopFillZerobss
 8001404:	e002      	b.n	800140c <LoopFillZerobss>

08001406 <FillZerobss>:
/* Zero fill the bss segment. */
FillZerobss:
  movs r3, #0
 8001406:	2300      	movs	r3, #0
  str r3, [r2], #4
 8001408:	f842 3b04 	str.w	r3, [r2], #4

0800140c <LoopFillZerobss>:

LoopFillZerobss:
  ldr r3, = _ebss
 800140c:	4b08      	ldr	r3, [pc, #32]	; (8001430 <LoopFillZerobss+0x24>)
  cmp r2, r3
 800140e:	429a      	cmp	r2, r3
  bcc FillZerobss
 8001410:	d3f9      	bcc.n	8001406 <FillZerobss>

/* Call the clock system intitialization function.*/
    bl  SystemInit
 8001412:	f7ff ffc5 	bl	80013a0 <SystemInit>
/* Call static constructors */
    bl __libc_init_array
 8001416:	f000 f80f 	bl	8001438 <__libc_init_array>
/* Call the application's entry point.*/
  bl main
 800141a:	f7ff feb5 	bl	8001188 <main>
  bx lr
 800141e:	4770      	bx	lr
  ldr r3, =_sidata
 8001420:	080014d8 	.word	0x080014d8
  ldr r0, =_sdata
 8001424:	20000000 	.word	0x20000000
  ldr r3, =_edata
 8001428:	2000000c 	.word	0x2000000c
  ldr r2, =_sbss
 800142c:	2000000c 	.word	0x2000000c
  ldr r3, = _ebss
 8001430:	2000012c 	.word	0x2000012c

08001434 <ADC1_2_IRQHandler>:
 * @retval : None
*/
    .section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
  b Infinite_Loop
 8001434:	e7fe      	b.n	8001434 <ADC1_2_IRQHandler>
	...

08001438 <__libc_init_array>:
 8001438:	b570      	push	{r4, r5, r6, lr}
 800143a:	2500      	movs	r5, #0
 800143c:	4e0c      	ldr	r6, [pc, #48]	; (8001470 <__libc_init_array+0x38>)
 800143e:	4c0d      	ldr	r4, [pc, #52]	; (8001474 <__libc_init_array+0x3c>)
 8001440:	1ba4      	subs	r4, r4, r6
 8001442:	10a4      	asrs	r4, r4, #2
 8001444:	42a5      	cmp	r5, r4
 8001446:	d109      	bne.n	800145c <__libc_init_array+0x24>
 8001448:	f000 f822 	bl	8001490 <_init>
 800144c:	2500      	movs	r5, #0
 800144e:	4e0a      	ldr	r6, [pc, #40]	; (8001478 <__libc_init_array+0x40>)
 8001450:	4c0a      	ldr	r4, [pc, #40]	; (800147c <__libc_init_array+0x44>)
 8001452:	1ba4      	subs	r4, r4, r6
 8001454:	10a4      	asrs	r4, r4, #2
 8001456:	42a5      	cmp	r5, r4
 8001458:	d105      	bne.n	8001466 <__libc_init_array+0x2e>
 800145a:	bd70      	pop	{r4, r5, r6, pc}
 800145c:	f856 3025 	ldr.w	r3, [r6, r5, lsl #2]
 8001460:	4798      	blx	r3
 8001462:	3501      	adds	r5, #1
 8001464:	e7ee      	b.n	8001444 <__libc_init_array+0xc>
 8001466:	f856 3025 	ldr.w	r3, [r6, r5, lsl #2]
 800146a:	4798      	blx	r3
 800146c:	3501      	adds	r5, #1
 800146e:	e7f2      	b.n	8001456 <__libc_init_array+0x1e>
 8001470:	080014d0 	.word	0x080014d0
 8001474:	080014d0 	.word	0x080014d0
 8001478:	080014d0 	.word	0x080014d0
 800147c:	080014d4 	.word	0x080014d4

08001480 <memset>:
 8001480:	4603      	mov	r3, r0
 8001482:	4402      	add	r2, r0
 8001484:	4293      	cmp	r3, r2
 8001486:	d100      	bne.n	800148a <memset+0xa>
 8001488:	4770      	bx	lr
 800148a:	f803 1b01 	strb.w	r1, [r3], #1
 800148e:	e7f9      	b.n	8001484 <memset+0x4>

08001490 <_init>:
 8001490:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 8001492:	bf00      	nop
 8001494:	bcf8      	pop	{r3, r4, r5, r6, r7}
 8001496:	bc08      	pop	{r3}
 8001498:	469e      	mov	lr, r3
 800149a:	4770      	bx	lr

0800149c <_fini>:
 800149c:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 800149e:	bf00      	nop
 80014a0:	bcf8      	pop	{r3, r4, r5, r6, r7}
 80014a2:	bc08      	pop	{r3}
 80014a4:	469e      	mov	lr, r3
 80014a6:	4770      	bx	lr