STM32F103ZET_JDASMBIC/Debug/STM32F103_ATTEN_PLL_Zig.list

STM32F103_ATTEN_PLL_Zig.elf:     file format elf32-littlearm

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .isr_vector   000001e4  08000000  08000000  00010000  2**0
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  1 .text         00003508  080001e4  080001e4  000101e4  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  2 .rodata       00000134  080036ec  080036ec  000136ec  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  3 .init_array   00000004  08003820  08003820  00013820  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  4 .fini_array   00000004  08003824  08003824  00013824  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  5 .data         00000280  20000000  08003828  00020000  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  6 .bss          00000ef4  20000280  08003aa8  00020280  2**3
                  ALLOC
  7 ._user_heap_stack 00000600  20001174  08003aa8  00021174  2**0
                  ALLOC
  8 .ARM.attributes 00000029  00000000  00000000  00020280  2**0
                  CONTENTS, READONLY
  9 .debug_info   0001ebe4  00000000  00000000  000202a9  2**0
                  CONTENTS, READONLY, DEBUGGING
 10 .debug_abbrev 00003ea0  00000000  00000000  0003ee8d  2**0
                  CONTENTS, READONLY, DEBUGGING
 11 .debug_loc    0000af09  00000000  00000000  00042d2d  2**0
                  CONTENTS, READONLY, DEBUGGING
 12 .debug_aranges 00000d10  00000000  00000000  0004dc38  2**3
                  CONTENTS, READONLY, DEBUGGING
 13 .debug_ranges 000013e8  00000000  00000000  0004e948  2**3
                  CONTENTS, READONLY, DEBUGGING
 14 .debug_line   00008f4f  00000000  00000000  0004fd30  2**0
                  CONTENTS, READONLY, DEBUGGING
 15 .debug_str    00004e8d  00000000  00000000  00058c7f  2**0
                  CONTENTS, READONLY, DEBUGGING
 16 .comment      0000007c  00000000  00000000  0005db0c  2**0
                  CONTENTS, READONLY
 17 .debug_frame  00002e8c  00000000  00000000  0005db88  2**2
                  CONTENTS, READONLY, DEBUGGING

Disassembly of section .text:

080001e4 <__do_global_dtors_aux>:
 80001e4:	b510      	push	{r4, lr}
 80001e6:	4c05      	ldr	r4, [pc, #20]	; (80001fc <__do_global_dtors_aux+0x18>)
 80001e8:	7823      	ldrb	r3, [r4, #0]
 80001ea:	b933      	cbnz	r3, 80001fa <__do_global_dtors_aux+0x16>
 80001ec:	4b04      	ldr	r3, [pc, #16]	; (8000200 <__do_global_dtors_aux+0x1c>)
 80001ee:	b113      	cbz	r3, 80001f6 <__do_global_dtors_aux+0x12>
 80001f0:	4804      	ldr	r0, [pc, #16]	; (8000204 <__do_global_dtors_aux+0x20>)
 80001f2:	f3af 8000 	nop.w
 80001f6:	2301      	movs	r3, #1
 80001f8:	7023      	strb	r3, [r4, #0]
 80001fa:	bd10      	pop	{r4, pc}
 80001fc:	20000280 	.word	0x20000280
 8000200:	00000000 	.word	0x00000000
 8000204:	080036d4 	.word	0x080036d4

08000208 <frame_dummy>:
 8000208:	b508      	push	{r3, lr}
 800020a:	4b03      	ldr	r3, [pc, #12]	; (8000218 <frame_dummy+0x10>)
 800020c:	b11b      	cbz	r3, 8000216 <frame_dummy+0xe>
 800020e:	4903      	ldr	r1, [pc, #12]	; (800021c <frame_dummy+0x14>)
 8000210:	4803      	ldr	r0, [pc, #12]	; (8000220 <frame_dummy+0x18>)
 8000212:	f3af 8000 	nop.w
 8000216:	bd08      	pop	{r3, pc}
 8000218:	00000000 	.word	0x00000000
 800021c:	20000284 	.word	0x20000284
 8000220:	080036d4 	.word	0x080036d4

08000224 <__aeabi_llsr>:
 8000224:	40d0      	lsrs	r0, r2
 8000226:	1c0b      	adds	r3, r1, #0
 8000228:	40d1      	lsrs	r1, r2
 800022a:	469c      	mov	ip, r3
 800022c:	3a20      	subs	r2, #32
 800022e:	40d3      	lsrs	r3, r2
 8000230:	4318      	orrs	r0, r3
 8000232:	4252      	negs	r2, r2
 8000234:	4663      	mov	r3, ip
 8000236:	4093      	lsls	r3, r2
 8000238:	4318      	orrs	r0, r3
 800023a:	4770      	bx	lr

0800023c <HAL_InitTick>:
  *       implementation  in user file.
  * @param TickPriority Tick interrupt priority.
  * @retval HAL status
  */
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
 800023c:	b538      	push	{r3, r4, r5, lr}
  /* Configure the SysTick to have interrupt in 1ms time basis*/
  if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
 800023e:	4b0e      	ldr	r3, [pc, #56]	; (8000278 <HAL_InitTick+0x3c>)
{
 8000240:	4605      	mov	r5, r0
  if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
 8000242:	7818      	ldrb	r0, [r3, #0]
 8000244:	f44f 737a 	mov.w	r3, #1000	; 0x3e8
 8000248:	fbb3 f3f0 	udiv	r3, r3, r0
 800024c:	4a0b      	ldr	r2, [pc, #44]	; (800027c <HAL_InitTick+0x40>)
 800024e:	6810      	ldr	r0, [r2, #0]
 8000250:	fbb0 f0f3 	udiv	r0, r0, r3
 8000254:	f000 f89e 	bl	8000394 <HAL_SYSTICK_Config>
 8000258:	4604      	mov	r4, r0
 800025a:	b958      	cbnz	r0, 8000274 <HAL_InitTick+0x38>
  {
    return HAL_ERROR;
  }

  /* Configure the SysTick IRQ priority */
  if (TickPriority < (1UL << __NVIC_PRIO_BITS))
 800025c:	2d0f      	cmp	r5, #15
 800025e:	d809      	bhi.n	8000274 <HAL_InitTick+0x38>
  {
    HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
 8000260:	4602      	mov	r2, r0
 8000262:	4629      	mov	r1, r5
 8000264:	f04f 30ff 	mov.w	r0, #4294967295
 8000268:	f000 f854 	bl	8000314 <HAL_NVIC_SetPriority>
    uwTickPrio = TickPriority;
 800026c:	4b04      	ldr	r3, [pc, #16]	; (8000280 <HAL_InitTick+0x44>)
 800026e:	4620      	mov	r0, r4
 8000270:	601d      	str	r5, [r3, #0]
 8000272:	bd38      	pop	{r3, r4, r5, pc}
    return HAL_ERROR;
 8000274:	2001      	movs	r0, #1
    return HAL_ERROR;
  }

  /* Return function status */
  return HAL_OK;
}
 8000276:	bd38      	pop	{r3, r4, r5, pc}
 8000278:	20000000 	.word	0x20000000
 800027c:	20000218 	.word	0x20000218
 8000280:	20000004 	.word	0x20000004

08000284 <HAL_Init>:
  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
 8000284:	4a07      	ldr	r2, [pc, #28]	; (80002a4 <HAL_Init+0x20>)
{
 8000286:	b508      	push	{r3, lr}
  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
 8000288:	6813      	ldr	r3, [r2, #0]
  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
 800028a:	2003      	movs	r0, #3
  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
 800028c:	f043 0310 	orr.w	r3, r3, #16
 8000290:	6013      	str	r3, [r2, #0]
  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
 8000292:	f000 f82d 	bl	80002f0 <HAL_NVIC_SetPriorityGrouping>
  HAL_InitTick(TICK_INT_PRIORITY);
 8000296:	2000      	movs	r0, #0
 8000298:	f7ff ffd0 	bl	800023c <HAL_InitTick>
  HAL_MspInit();
 800029c:	f001 ffac 	bl	80021f8 <HAL_MspInit>
}
 80002a0:	2000      	movs	r0, #0
 80002a2:	bd08      	pop	{r3, pc}
 80002a4:	40022000 	.word	0x40022000

080002a8 <HAL_IncTick>:
  *      implementations in user file.
  * @retval None
  */
__weak void HAL_IncTick(void)
{
  uwTick += uwTickFreq;
 80002a8:	4a03      	ldr	r2, [pc, #12]	; (80002b8 <HAL_IncTick+0x10>)
 80002aa:	4b04      	ldr	r3, [pc, #16]	; (80002bc <HAL_IncTick+0x14>)
 80002ac:	6811      	ldr	r1, [r2, #0]
 80002ae:	781b      	ldrb	r3, [r3, #0]
 80002b0:	440b      	add	r3, r1
 80002b2:	6013      	str	r3, [r2, #0]
 80002b4:	4770      	bx	lr
 80002b6:	bf00      	nop
 80002b8:	200002f4 	.word	0x200002f4
 80002bc:	20000000 	.word	0x20000000

080002c0 <HAL_GetTick>:
  *       implementations in user file.
  * @retval tick value
  */
__weak uint32_t HAL_GetTick(void)
{
  return uwTick;
 80002c0:	4b01      	ldr	r3, [pc, #4]	; (80002c8 <HAL_GetTick+0x8>)
 80002c2:	6818      	ldr	r0, [r3, #0]
}
 80002c4:	4770      	bx	lr
 80002c6:	bf00      	nop
 80002c8:	200002f4 	.word	0x200002f4

080002cc <HAL_Delay>:
  *       implementations in user file.
  * @param Delay specifies the delay time length, in milliseconds.
  * @retval None
  */
__weak void HAL_Delay(uint32_t Delay)
{
 80002cc:	b538      	push	{r3, r4, r5, lr}
 80002ce:	4604      	mov	r4, r0
  uint32_t tickstart = HAL_GetTick();
 80002d0:	f7ff fff6 	bl	80002c0 <HAL_GetTick>
 80002d4:	4605      	mov	r5, r0
  uint32_t wait = Delay;

  /* Add a freq to guarantee minimum wait */
  if (wait < HAL_MAX_DELAY)
 80002d6:	1c63      	adds	r3, r4, #1
  {
    wait += (uint32_t)(uwTickFreq);
 80002d8:	bf1e      	ittt	ne
 80002da:	4b04      	ldrne	r3, [pc, #16]	; (80002ec <HAL_Delay+0x20>)
 80002dc:	781b      	ldrbne	r3, [r3, #0]
 80002de:	18e4      	addne	r4, r4, r3
  }

  while ((HAL_GetTick() - tickstart) < wait)
 80002e0:	f7ff ffee 	bl	80002c0 <HAL_GetTick>
 80002e4:	1b40      	subs	r0, r0, r5
 80002e6:	4284      	cmp	r4, r0
 80002e8:	d8fa      	bhi.n	80002e0 <HAL_Delay+0x14>
  {
  }
}
 80002ea:	bd38      	pop	{r3, r4, r5, pc}
 80002ec:	20000000 	.word	0x20000000

080002f0 <HAL_NVIC_SetPriorityGrouping>:
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
  uint32_t reg_value;
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */

  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
 80002f0:	4a07      	ldr	r2, [pc, #28]	; (8000310 <HAL_NVIC_SetPriorityGrouping+0x20>)
  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
  reg_value  =  (reg_value                                   |
                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
 80002f2:	0200      	lsls	r0, r0, #8
  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
 80002f4:	68d3      	ldr	r3, [r2, #12]
                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
 80002f6:	f400 60e0 	and.w	r0, r0, #1792	; 0x700
  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
 80002fa:	f423 63e0 	bic.w	r3, r3, #1792	; 0x700
 80002fe:	041b      	lsls	r3, r3, #16
 8000300:	0c1b      	lsrs	r3, r3, #16
 8000302:	f043 63bf 	orr.w	r3, r3, #100139008	; 0x5f80000
 8000306:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
  reg_value  =  (reg_value                                   |
 800030a:	4303      	orrs	r3, r0
  SCB->AIRCR =  reg_value;
 800030c:	60d3      	str	r3, [r2, #12]
 800030e:	4770      	bx	lr
 8000310:	e000ed00 	.word	0xe000ed00

08000314 <HAL_NVIC_SetPriority>:
  \details Reads the priority grouping field from the NVIC Interrupt Controller.
  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
 */
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
{
  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
 8000314:	4b17      	ldr	r3, [pc, #92]	; (8000374 <HAL_NVIC_SetPriority+0x60>)
  *         This parameter can be a value between 0 and 15
  *         A lower priority value indicates a higher priority.          
  * @retval None
  */
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{ 
 8000316:	b530      	push	{r4, r5, lr}
 8000318:	68dc      	ldr	r4, [r3, #12]
 800031a:	f3c4 2402 	ubfx	r4, r4, #8, #3
{
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
  uint32_t PreemptPriorityBits;
  uint32_t SubPriorityBits;

  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
 800031e:	f1c4 0307 	rsb	r3, r4, #7
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 8000322:	1d25      	adds	r5, r4, #4
  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
 8000324:	2b04      	cmp	r3, #4
 8000326:	bf28      	it	cs
 8000328:	2304      	movcs	r3, #4
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 800032a:	2d06      	cmp	r5, #6

  return (
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 800032c:	f04f 0501 	mov.w	r5, #1
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 8000330:	bf98      	it	ls
 8000332:	2400      	movls	r4, #0
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 8000334:	fa05 f303 	lsl.w	r3, r5, r3
 8000338:	f103 33ff 	add.w	r3, r3, #4294967295
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 800033c:	bf88      	it	hi
 800033e:	3c03      	subhi	r4, #3
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 8000340:	4019      	ands	r1, r3
 8000342:	40a1      	lsls	r1, r4
           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
 8000344:	fa05 f404 	lsl.w	r4, r5, r4
 8000348:	3c01      	subs	r4, #1
 800034a:	4022      	ands	r2, r4
  if ((int32_t)(IRQn) < 0)
 800034c:	2800      	cmp	r0, #0
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 800034e:	ea42 0201 	orr.w	r2, r2, r1
 8000352:	ea4f 1202 	mov.w	r2, r2, lsl #4
    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8000356:	bfaf      	iteee	ge
 8000358:	f100 4060 	addge.w	r0, r0, #3758096384	; 0xe0000000
    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 800035c:	4b06      	ldrlt	r3, [pc, #24]	; (8000378 <HAL_NVIC_SetPriority+0x64>)
 800035e:	f000 000f 	andlt.w	r0, r0, #15
 8000362:	b2d2      	uxtblt	r2, r2
    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8000364:	bfa5      	ittet	ge
 8000366:	b2d2      	uxtbge	r2, r2
 8000368:	f500 4061 	addge.w	r0, r0, #57600	; 0xe100
    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 800036c:	541a      	strblt	r2, [r3, r0]
    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 800036e:	f880 2300 	strbge.w	r2, [r0, #768]	; 0x300
 8000372:	bd30      	pop	{r4, r5, pc}
 8000374:	e000ed00 	.word	0xe000ed00
 8000378:	e000ed14 	.word	0xe000ed14

0800037c <HAL_NVIC_EnableIRQ>:
  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
 800037c:	2301      	movs	r3, #1
 800037e:	0942      	lsrs	r2, r0, #5
 8000380:	f000 001f 	and.w	r0, r0, #31
 8000384:	fa03 f000 	lsl.w	r0, r3, r0
 8000388:	4b01      	ldr	r3, [pc, #4]	; (8000390 <HAL_NVIC_EnableIRQ+0x14>)
 800038a:	f843 0022 	str.w	r0, [r3, r2, lsl #2]
 800038e:	4770      	bx	lr
 8000390:	e000e100 	.word	0xe000e100

08000394 <HAL_SYSTICK_Config>:
           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
           must contain a vendor-specific implementation of this function.
 */
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
 8000394:	3801      	subs	r0, #1
 8000396:	f1b0 7f80 	cmp.w	r0, #16777216	; 0x1000000
 800039a:	d20a      	bcs.n	80003b2 <HAL_SYSTICK_Config+0x1e>
    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 800039c:	21f0      	movs	r1, #240	; 0xf0
  {
    return (1UL);                                                   /* Reload value impossible */
  }

  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
 800039e:	4b06      	ldr	r3, [pc, #24]	; (80003b8 <HAL_SYSTICK_Config+0x24>)
    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 80003a0:	4a06      	ldr	r2, [pc, #24]	; (80003bc <HAL_SYSTICK_Config+0x28>)
  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
 80003a2:	6058      	str	r0, [r3, #4]
    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 80003a4:	f882 1023 	strb.w	r1, [r2, #35]	; 0x23
  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
 80003a8:	2000      	movs	r0, #0
  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
 80003aa:	2207      	movs	r2, #7
  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
 80003ac:	6098      	str	r0, [r3, #8]
  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
 80003ae:	601a      	str	r2, [r3, #0]
 80003b0:	4770      	bx	lr
    return (1UL);                                                   /* Reload value impossible */
 80003b2:	2001      	movs	r0, #1
  *                  - 1  Function failed.
  */
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
   return SysTick_Config(TicksNumb);
}
 80003b4:	4770      	bx	lr
 80003b6:	bf00      	nop
 80003b8:	e000e010 	.word	0xe000e010
 80003bc:	e000ed00 	.word	0xe000ed00

080003c0 <HAL_DMA_Init>:
  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
  *               the configuration information for the specified DMA Channel.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
{
 80003c0:	b510      	push	{r4, lr}
  uint32_t tmp = 0U;

  /* Check the DMA handle allocation */
  if(hdma == NULL)
 80003c2:	2800      	cmp	r0, #0
 80003c4:	d032      	beq.n	800042c <HAL_DMA_Init+0x6c>
  assert_param(IS_DMA_MODE(hdma->Init.Mode));
  assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));

#if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F100xE) || defined (STM32F105xC) || defined (STM32F107xC)
  /* calculation of the channel index */
  if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
 80003c6:	6801      	ldr	r1, [r0, #0]
 80003c8:	4b19      	ldr	r3, [pc, #100]	; (8000430 <HAL_DMA_Init+0x70>)
 80003ca:	2414      	movs	r4, #20
 80003cc:	4299      	cmp	r1, r3
 80003ce:	d825      	bhi.n	800041c <HAL_DMA_Init+0x5c>
  {
    /* DMA1 */
    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
 80003d0:	4a18      	ldr	r2, [pc, #96]	; (8000434 <HAL_DMA_Init+0x74>)
    hdma->DmaBaseAddress = DMA1;
 80003d2:	f2a3 4307 	subw	r3, r3, #1031	; 0x407
    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
 80003d6:	440a      	add	r2, r1
 80003d8:	fbb2 f2f4 	udiv	r2, r2, r4
 80003dc:	0092      	lsls	r2, r2, #2
 80003de:	6402      	str	r2, [r0, #64]	; 0x40
  tmp &= ((uint32_t)~(DMA_CCR_PL    | DMA_CCR_MSIZE  | DMA_CCR_PSIZE  | \
                      DMA_CCR_MINC  | DMA_CCR_PINC   | DMA_CCR_CIRC   | \
                      DMA_CCR_DIR));

  /* Prepare the DMA Channel configuration */
  tmp |=  hdma->Init.Direction        |
 80003e0:	6884      	ldr	r4, [r0, #8]
    hdma->DmaBaseAddress = DMA2;
 80003e2:	63c3      	str	r3, [r0, #60]	; 0x3c
  tmp |=  hdma->Init.Direction        |
 80003e4:	6843      	ldr	r3, [r0, #4]
  tmp = hdma->Instance->CCR;
 80003e6:	680a      	ldr	r2, [r1, #0]
  tmp |=  hdma->Init.Direction        |
 80003e8:	4323      	orrs	r3, r4
          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
 80003ea:	68c4      	ldr	r4, [r0, #12]
  tmp &= ((uint32_t)~(DMA_CCR_PL    | DMA_CCR_MSIZE  | DMA_CCR_PSIZE  | \
 80003ec:	f422 527f 	bic.w	r2, r2, #16320	; 0x3fc0
          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
 80003f0:	4323      	orrs	r3, r4
 80003f2:	6904      	ldr	r4, [r0, #16]
  tmp &= ((uint32_t)~(DMA_CCR_PL    | DMA_CCR_MSIZE  | DMA_CCR_PSIZE  | \
 80003f4:	f022 0230 	bic.w	r2, r2, #48	; 0x30
          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
 80003f8:	4323      	orrs	r3, r4
          hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
 80003fa:	6944      	ldr	r4, [r0, #20]
 80003fc:	4323      	orrs	r3, r4
 80003fe:	6984      	ldr	r4, [r0, #24]
 8000400:	4323      	orrs	r3, r4
          hdma->Init.Mode                | hdma->Init.Priority;
 8000402:	69c4      	ldr	r4, [r0, #28]
 8000404:	4323      	orrs	r3, r4
  tmp |=  hdma->Init.Direction        |
 8000406:	4313      	orrs	r3, r2

  /* Write to DMA Channel CR register */
  hdma->Instance->CCR = tmp;
 8000408:	600b      	str	r3, [r1, #0]

  /* Initialise the error code */
  hdma->ErrorCode = HAL_DMA_ERROR_NONE;

  /* Initialize the DMA state*/
  hdma->State = HAL_DMA_STATE_READY;
 800040a:	2201      	movs	r2, #1
  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
 800040c:	2300      	movs	r3, #0
  hdma->State = HAL_DMA_STATE_READY;
 800040e:	f880 2021 	strb.w	r2, [r0, #33]	; 0x21
  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
 8000412:	6383      	str	r3, [r0, #56]	; 0x38
  /* Allocate lock resource and initialize it */
  hdma->Lock = HAL_UNLOCKED;
 8000414:	f880 3020 	strb.w	r3, [r0, #32]

  return HAL_OK;
 8000418:	4618      	mov	r0, r3
 800041a:	bd10      	pop	{r4, pc}
    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
 800041c:	4b06      	ldr	r3, [pc, #24]	; (8000438 <HAL_DMA_Init+0x78>)
 800041e:	440b      	add	r3, r1
 8000420:	fbb3 f3f4 	udiv	r3, r3, r4
 8000424:	009b      	lsls	r3, r3, #2
 8000426:	6403      	str	r3, [r0, #64]	; 0x40
    hdma->DmaBaseAddress = DMA2;
 8000428:	4b04      	ldr	r3, [pc, #16]	; (800043c <HAL_DMA_Init+0x7c>)
 800042a:	e7d9      	b.n	80003e0 <HAL_DMA_Init+0x20>
    return HAL_ERROR;
 800042c:	2001      	movs	r0, #1
}
 800042e:	bd10      	pop	{r4, pc}
 8000430:	40020407 	.word	0x40020407
 8000434:	bffdfff8 	.word	0xbffdfff8
 8000438:	bffdfbf8 	.word	0xbffdfbf8
 800043c:	40020400 	.word	0x40020400

08000440 <HAL_DMA_Start_IT>:
  * @param  DstAddress: The destination memory Buffer address
  * @param  DataLength: The length of data to be transferred from source to destination
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
 8000440:	b5f0      	push	{r4, r5, r6, r7, lr}

  /* Check the parameters */
  assert_param(IS_DMA_BUFFER_SIZE(DataLength));

  /* Process locked */
  __HAL_LOCK(hdma);
 8000442:	f890 4020 	ldrb.w	r4, [r0, #32]
 8000446:	2c01      	cmp	r4, #1
 8000448:	d035      	beq.n	80004b6 <HAL_DMA_Start_IT+0x76>
 800044a:	2401      	movs	r4, #1
  
  if(HAL_DMA_STATE_READY == hdma->State)
 800044c:	f890 5021 	ldrb.w	r5, [r0, #33]	; 0x21
  __HAL_LOCK(hdma);
 8000450:	f880 4020 	strb.w	r4, [r0, #32]
  if(HAL_DMA_STATE_READY == hdma->State)
 8000454:	42a5      	cmp	r5, r4
 8000456:	f04f 0600 	mov.w	r6, #0
 800045a:	f04f 0402 	mov.w	r4, #2
 800045e:	d128      	bne.n	80004b2 <HAL_DMA_Start_IT+0x72>
  {
    /* Change DMA peripheral state */
    hdma->State = HAL_DMA_STATE_BUSY;
 8000460:	f880 4021 	strb.w	r4, [r0, #33]	; 0x21
    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
    
    /* Disable the peripheral */
    __HAL_DMA_DISABLE(hdma);
 8000464:	6804      	ldr	r4, [r0, #0]
    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
 8000466:	6386      	str	r6, [r0, #56]	; 0x38
    __HAL_DMA_DISABLE(hdma);
 8000468:	6826      	ldr	r6, [r4, #0]
  * @retval HAL status
  */
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
  /* Clear all flags */
  hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
 800046a:	6c07      	ldr	r7, [r0, #64]	; 0x40
    __HAL_DMA_DISABLE(hdma);
 800046c:	f026 0601 	bic.w	r6, r6, #1
 8000470:	6026      	str	r6, [r4, #0]
  hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
 8000472:	6bc6      	ldr	r6, [r0, #60]	; 0x3c
 8000474:	40bd      	lsls	r5, r7
 8000476:	6075      	str	r5, [r6, #4]

  /* Configure DMA Channel data length */
  hdma->Instance->CNDTR = DataLength;
 8000478:	6063      	str	r3, [r4, #4]

  /* Memory to Peripheral */
  if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
 800047a:	6843      	ldr	r3, [r0, #4]
 800047c:	6805      	ldr	r5, [r0, #0]
 800047e:	2b10      	cmp	r3, #16
    if(NULL != hdma->XferHalfCpltCallback)
 8000480:	6ac3      	ldr	r3, [r0, #44]	; 0x2c
  {
    /* Configure DMA Channel destination address */
    hdma->Instance->CPAR = DstAddress;
 8000482:	bf0b      	itete	eq
 8000484:	60a2      	streq	r2, [r4, #8]
  }
  /* Peripheral to Memory */
  else
  {
    /* Configure DMA Channel source address */
    hdma->Instance->CPAR = SrcAddress;
 8000486:	60a1      	strne	r1, [r4, #8]
    hdma->Instance->CMAR = SrcAddress;
 8000488:	60e1      	streq	r1, [r4, #12]

    /* Configure DMA Channel destination address */
    hdma->Instance->CMAR = DstAddress;
 800048a:	60e2      	strne	r2, [r4, #12]
    if(NULL != hdma->XferHalfCpltCallback)
 800048c:	b14b      	cbz	r3, 80004a2 <HAL_DMA_Start_IT+0x62>
      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
 800048e:	6823      	ldr	r3, [r4, #0]
 8000490:	f043 030e 	orr.w	r3, r3, #14
      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
 8000494:	6023      	str	r3, [r4, #0]
    __HAL_DMA_ENABLE(hdma);
 8000496:	682b      	ldr	r3, [r5, #0]
  HAL_StatusTypeDef status = HAL_OK;
 8000498:	2000      	movs	r0, #0
    __HAL_DMA_ENABLE(hdma);
 800049a:	f043 0301 	orr.w	r3, r3, #1
 800049e:	602b      	str	r3, [r5, #0]
 80004a0:	bdf0      	pop	{r4, r5, r6, r7, pc}
      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
 80004a2:	6823      	ldr	r3, [r4, #0]
 80004a4:	f023 0304 	bic.w	r3, r3, #4
 80004a8:	6023      	str	r3, [r4, #0]
      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
 80004aa:	6823      	ldr	r3, [r4, #0]
 80004ac:	f043 030a 	orr.w	r3, r3, #10
 80004b0:	e7f0      	b.n	8000494 <HAL_DMA_Start_IT+0x54>
    __HAL_UNLOCK(hdma); 
 80004b2:	f880 6020 	strb.w	r6, [r0, #32]
  __HAL_LOCK(hdma);
 80004b6:	2002      	movs	r0, #2
}
 80004b8:	bdf0      	pop	{r4, r5, r6, r7, pc}
	...

080004bc <HAL_DMA_Abort_IT>:
  if(HAL_DMA_STATE_BUSY != hdma->State)
 80004bc:	f890 3021 	ldrb.w	r3, [r0, #33]	; 0x21
{  
 80004c0:	b510      	push	{r4, lr}
  if(HAL_DMA_STATE_BUSY != hdma->State)
 80004c2:	2b02      	cmp	r3, #2
 80004c4:	d003      	beq.n	80004ce <HAL_DMA_Abort_IT+0x12>
    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
 80004c6:	2304      	movs	r3, #4
 80004c8:	6383      	str	r3, [r0, #56]	; 0x38
    status = HAL_ERROR;
 80004ca:	2001      	movs	r0, #1
 80004cc:	bd10      	pop	{r4, pc}
    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
 80004ce:	6803      	ldr	r3, [r0, #0]
 80004d0:	681a      	ldr	r2, [r3, #0]
 80004d2:	f022 020e 	bic.w	r2, r2, #14
 80004d6:	601a      	str	r2, [r3, #0]
    __HAL_DMA_DISABLE(hdma);
 80004d8:	681a      	ldr	r2, [r3, #0]
 80004da:	f022 0201 	bic.w	r2, r2, #1
 80004de:	601a      	str	r2, [r3, #0]
    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma));
 80004e0:	4a29      	ldr	r2, [pc, #164]	; (8000588 <HAL_DMA_Abort_IT+0xcc>)
 80004e2:	4293      	cmp	r3, r2
 80004e4:	d924      	bls.n	8000530 <HAL_DMA_Abort_IT+0x74>
 80004e6:	f502 7262 	add.w	r2, r2, #904	; 0x388
 80004ea:	4293      	cmp	r3, r2
 80004ec:	d019      	beq.n	8000522 <HAL_DMA_Abort_IT+0x66>
 80004ee:	3214      	adds	r2, #20
 80004f0:	4293      	cmp	r3, r2
 80004f2:	d018      	beq.n	8000526 <HAL_DMA_Abort_IT+0x6a>
 80004f4:	3214      	adds	r2, #20
 80004f6:	4293      	cmp	r3, r2
 80004f8:	d017      	beq.n	800052a <HAL_DMA_Abort_IT+0x6e>
 80004fa:	3214      	adds	r2, #20
 80004fc:	4293      	cmp	r3, r2
 80004fe:	bf0c      	ite	eq
 8000500:	f44f 5380 	moveq.w	r3, #4096	; 0x1000
 8000504:	f44f 3380 	movne.w	r3, #65536	; 0x10000
 8000508:	4a20      	ldr	r2, [pc, #128]	; (800058c <HAL_DMA_Abort_IT+0xd0>)
 800050a:	6053      	str	r3, [r2, #4]
    hdma->State = HAL_DMA_STATE_READY;
 800050c:	2301      	movs	r3, #1
    __HAL_UNLOCK(hdma);
 800050e:	2400      	movs	r4, #0
    hdma->State = HAL_DMA_STATE_READY;
 8000510:	f880 3021 	strb.w	r3, [r0, #33]	; 0x21
    if(hdma->XferAbortCallback != NULL)
 8000514:	6b43      	ldr	r3, [r0, #52]	; 0x34
    __HAL_UNLOCK(hdma);
 8000516:	f880 4020 	strb.w	r4, [r0, #32]
    if(hdma->XferAbortCallback != NULL)
 800051a:	b39b      	cbz	r3, 8000584 <HAL_DMA_Abort_IT+0xc8>
      hdma->XferAbortCallback(hdma);
 800051c:	4798      	blx	r3
  HAL_StatusTypeDef status = HAL_OK;
 800051e:	4620      	mov	r0, r4
 8000520:	bd10      	pop	{r4, pc}
    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma));
 8000522:	2301      	movs	r3, #1
 8000524:	e7f0      	b.n	8000508 <HAL_DMA_Abort_IT+0x4c>
 8000526:	2310      	movs	r3, #16
 8000528:	e7ee      	b.n	8000508 <HAL_DMA_Abort_IT+0x4c>
 800052a:	f44f 7380 	mov.w	r3, #256	; 0x100
 800052e:	e7eb      	b.n	8000508 <HAL_DMA_Abort_IT+0x4c>
 8000530:	4917      	ldr	r1, [pc, #92]	; (8000590 <HAL_DMA_Abort_IT+0xd4>)
 8000532:	428b      	cmp	r3, r1
 8000534:	d016      	beq.n	8000564 <HAL_DMA_Abort_IT+0xa8>
 8000536:	3114      	adds	r1, #20
 8000538:	428b      	cmp	r3, r1
 800053a:	d015      	beq.n	8000568 <HAL_DMA_Abort_IT+0xac>
 800053c:	3114      	adds	r1, #20
 800053e:	428b      	cmp	r3, r1
 8000540:	d014      	beq.n	800056c <HAL_DMA_Abort_IT+0xb0>
 8000542:	3114      	adds	r1, #20
 8000544:	428b      	cmp	r3, r1
 8000546:	d014      	beq.n	8000572 <HAL_DMA_Abort_IT+0xb6>
 8000548:	3114      	adds	r1, #20
 800054a:	428b      	cmp	r3, r1
 800054c:	d014      	beq.n	8000578 <HAL_DMA_Abort_IT+0xbc>
 800054e:	3114      	adds	r1, #20
 8000550:	428b      	cmp	r3, r1
 8000552:	d014      	beq.n	800057e <HAL_DMA_Abort_IT+0xc2>
 8000554:	4293      	cmp	r3, r2
 8000556:	bf14      	ite	ne
 8000558:	f44f 3380 	movne.w	r3, #65536	; 0x10000
 800055c:	f04f 7380 	moveq.w	r3, #16777216	; 0x1000000
 8000560:	4a0c      	ldr	r2, [pc, #48]	; (8000594 <HAL_DMA_Abort_IT+0xd8>)
 8000562:	e7d2      	b.n	800050a <HAL_DMA_Abort_IT+0x4e>
 8000564:	2301      	movs	r3, #1
 8000566:	e7fb      	b.n	8000560 <HAL_DMA_Abort_IT+0xa4>
 8000568:	2310      	movs	r3, #16
 800056a:	e7f9      	b.n	8000560 <HAL_DMA_Abort_IT+0xa4>
 800056c:	f44f 7380 	mov.w	r3, #256	; 0x100
 8000570:	e7f6      	b.n	8000560 <HAL_DMA_Abort_IT+0xa4>
 8000572:	f44f 5380 	mov.w	r3, #4096	; 0x1000
 8000576:	e7f3      	b.n	8000560 <HAL_DMA_Abort_IT+0xa4>
 8000578:	f44f 3380 	mov.w	r3, #65536	; 0x10000
 800057c:	e7f0      	b.n	8000560 <HAL_DMA_Abort_IT+0xa4>
 800057e:	f44f 1380 	mov.w	r3, #1048576	; 0x100000
 8000582:	e7ed      	b.n	8000560 <HAL_DMA_Abort_IT+0xa4>
  HAL_StatusTypeDef status = HAL_OK;
 8000584:	4618      	mov	r0, r3
}
 8000586:	bd10      	pop	{r4, pc}
 8000588:	40020080 	.word	0x40020080
 800058c:	40020400 	.word	0x40020400
 8000590:	40020008 	.word	0x40020008
 8000594:	40020000 	.word	0x40020000

08000598 <HAL_DMA_IRQHandler>:
{
 8000598:	b470      	push	{r4, r5, r6}
  if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET))
 800059a:	2504      	movs	r5, #4
  uint32_t flag_it = hdma->DmaBaseAddress->ISR;
 800059c:	6bc6      	ldr	r6, [r0, #60]	; 0x3c
  if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET))
 800059e:	6c02      	ldr	r2, [r0, #64]	; 0x40
  uint32_t flag_it = hdma->DmaBaseAddress->ISR;
 80005a0:	6834      	ldr	r4, [r6, #0]
  uint32_t source_it = hdma->Instance->CCR;
 80005a2:	6803      	ldr	r3, [r0, #0]
  if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET))
 80005a4:	4095      	lsls	r5, r2
 80005a6:	4225      	tst	r5, r4
  uint32_t source_it = hdma->Instance->CCR;
 80005a8:	6819      	ldr	r1, [r3, #0]
  if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET))
 80005aa:	d055      	beq.n	8000658 <HAL_DMA_IRQHandler+0xc0>
 80005ac:	074d      	lsls	r5, r1, #29
 80005ae:	d553      	bpl.n	8000658 <HAL_DMA_IRQHandler+0xc0>
    if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
 80005b0:	681a      	ldr	r2, [r3, #0]
 80005b2:	0696      	lsls	r6, r2, #26
      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
 80005b4:	bf5e      	ittt	pl
 80005b6:	681a      	ldrpl	r2, [r3, #0]
 80005b8:	f022 0204 	bicpl.w	r2, r2, #4
 80005bc:	601a      	strpl	r2, [r3, #0]
    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
 80005be:	4a60      	ldr	r2, [pc, #384]	; (8000740 <HAL_DMA_IRQHandler+0x1a8>)
 80005c0:	4293      	cmp	r3, r2
 80005c2:	d91f      	bls.n	8000604 <HAL_DMA_IRQHandler+0x6c>
 80005c4:	f502 7262 	add.w	r2, r2, #904	; 0x388
 80005c8:	4293      	cmp	r3, r2
 80005ca:	d014      	beq.n	80005f6 <HAL_DMA_IRQHandler+0x5e>
 80005cc:	3214      	adds	r2, #20
 80005ce:	4293      	cmp	r3, r2
 80005d0:	d013      	beq.n	80005fa <HAL_DMA_IRQHandler+0x62>
 80005d2:	3214      	adds	r2, #20
 80005d4:	4293      	cmp	r3, r2
 80005d6:	d012      	beq.n	80005fe <HAL_DMA_IRQHandler+0x66>
 80005d8:	3214      	adds	r2, #20
 80005da:	4293      	cmp	r3, r2
 80005dc:	bf0c      	ite	eq
 80005de:	f44f 4380 	moveq.w	r3, #16384	; 0x4000
 80005e2:	f44f 2380 	movne.w	r3, #262144	; 0x40000
 80005e6:	4a57      	ldr	r2, [pc, #348]	; (8000744 <HAL_DMA_IRQHandler+0x1ac>)
 80005e8:	6053      	str	r3, [r2, #4]
    if(hdma->XferHalfCpltCallback != NULL)
 80005ea:	6ac3      	ldr	r3, [r0, #44]	; 0x2c
    if (hdma->XferErrorCallback != NULL)
 80005ec:	2b00      	cmp	r3, #0
 80005ee:	f000 80a5 	beq.w	800073c <HAL_DMA_IRQHandler+0x1a4>
}
 80005f2:	bc70      	pop	{r4, r5, r6}
      hdma->XferErrorCallback(hdma);
 80005f4:	4718      	bx	r3
    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
 80005f6:	2304      	movs	r3, #4
 80005f8:	e7f5      	b.n	80005e6 <HAL_DMA_IRQHandler+0x4e>
 80005fa:	2340      	movs	r3, #64	; 0x40
 80005fc:	e7f3      	b.n	80005e6 <HAL_DMA_IRQHandler+0x4e>
 80005fe:	f44f 6380 	mov.w	r3, #1024	; 0x400
 8000602:	e7f0      	b.n	80005e6 <HAL_DMA_IRQHandler+0x4e>
 8000604:	4950      	ldr	r1, [pc, #320]	; (8000748 <HAL_DMA_IRQHandler+0x1b0>)
 8000606:	428b      	cmp	r3, r1
 8000608:	d016      	beq.n	8000638 <HAL_DMA_IRQHandler+0xa0>
 800060a:	3114      	adds	r1, #20
 800060c:	428b      	cmp	r3, r1
 800060e:	d015      	beq.n	800063c <HAL_DMA_IRQHandler+0xa4>
 8000610:	3114      	adds	r1, #20
 8000612:	428b      	cmp	r3, r1
 8000614:	d014      	beq.n	8000640 <HAL_DMA_IRQHandler+0xa8>
 8000616:	3114      	adds	r1, #20
 8000618:	428b      	cmp	r3, r1
 800061a:	d014      	beq.n	8000646 <HAL_DMA_IRQHandler+0xae>
 800061c:	3114      	adds	r1, #20
 800061e:	428b      	cmp	r3, r1
 8000620:	d014      	beq.n	800064c <HAL_DMA_IRQHandler+0xb4>
 8000622:	3114      	adds	r1, #20
 8000624:	428b      	cmp	r3, r1
 8000626:	d014      	beq.n	8000652 <HAL_DMA_IRQHandler+0xba>
 8000628:	4293      	cmp	r3, r2
 800062a:	bf14      	ite	ne
 800062c:	f44f 2380 	movne.w	r3, #262144	; 0x40000
 8000630:	f04f 6380 	moveq.w	r3, #67108864	; 0x4000000
 8000634:	4a45      	ldr	r2, [pc, #276]	; (800074c <HAL_DMA_IRQHandler+0x1b4>)
 8000636:	e7d7      	b.n	80005e8 <HAL_DMA_IRQHandler+0x50>
 8000638:	2304      	movs	r3, #4
 800063a:	e7fb      	b.n	8000634 <HAL_DMA_IRQHandler+0x9c>
 800063c:	2340      	movs	r3, #64	; 0x40
 800063e:	e7f9      	b.n	8000634 <HAL_DMA_IRQHandler+0x9c>
 8000640:	f44f 6380 	mov.w	r3, #1024	; 0x400
 8000644:	e7f6      	b.n	8000634 <HAL_DMA_IRQHandler+0x9c>
 8000646:	f44f 4380 	mov.w	r3, #16384	; 0x4000
 800064a:	e7f3      	b.n	8000634 <HAL_DMA_IRQHandler+0x9c>
 800064c:	f44f 2380 	mov.w	r3, #262144	; 0x40000
 8000650:	e7f0      	b.n	8000634 <HAL_DMA_IRQHandler+0x9c>
 8000652:	f44f 0380 	mov.w	r3, #4194304	; 0x400000
 8000656:	e7ed      	b.n	8000634 <HAL_DMA_IRQHandler+0x9c>
  else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET))
 8000658:	2502      	movs	r5, #2
 800065a:	4095      	lsls	r5, r2
 800065c:	4225      	tst	r5, r4
 800065e:	d057      	beq.n	8000710 <HAL_DMA_IRQHandler+0x178>
 8000660:	078d      	lsls	r5, r1, #30
 8000662:	d555      	bpl.n	8000710 <HAL_DMA_IRQHandler+0x178>
    if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
 8000664:	681a      	ldr	r2, [r3, #0]
 8000666:	0694      	lsls	r4, r2, #26
 8000668:	d406      	bmi.n	8000678 <HAL_DMA_IRQHandler+0xe0>
      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);  
 800066a:	681a      	ldr	r2, [r3, #0]
 800066c:	f022 020a 	bic.w	r2, r2, #10
 8000670:	601a      	str	r2, [r3, #0]
      hdma->State = HAL_DMA_STATE_READY;
 8000672:	2201      	movs	r2, #1
 8000674:	f880 2021 	strb.w	r2, [r0, #33]	; 0x21
      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
 8000678:	4a31      	ldr	r2, [pc, #196]	; (8000740 <HAL_DMA_IRQHandler+0x1a8>)
 800067a:	4293      	cmp	r3, r2
 800067c:	d91e      	bls.n	80006bc <HAL_DMA_IRQHandler+0x124>
 800067e:	f502 7262 	add.w	r2, r2, #904	; 0x388
 8000682:	4293      	cmp	r3, r2
 8000684:	d013      	beq.n	80006ae <HAL_DMA_IRQHandler+0x116>
 8000686:	3214      	adds	r2, #20
 8000688:	4293      	cmp	r3, r2
 800068a:	d012      	beq.n	80006b2 <HAL_DMA_IRQHandler+0x11a>
 800068c:	3214      	adds	r2, #20
 800068e:	4293      	cmp	r3, r2
 8000690:	d011      	beq.n	80006b6 <HAL_DMA_IRQHandler+0x11e>
 8000692:	3214      	adds	r2, #20
 8000694:	4293      	cmp	r3, r2
 8000696:	bf0c      	ite	eq
 8000698:	f44f 5300 	moveq.w	r3, #8192	; 0x2000
 800069c:	f44f 3300 	movne.w	r3, #131072	; 0x20000
 80006a0:	4a28      	ldr	r2, [pc, #160]	; (8000744 <HAL_DMA_IRQHandler+0x1ac>)
 80006a2:	6053      	str	r3, [r2, #4]
    __HAL_UNLOCK(hdma);
 80006a4:	2300      	movs	r3, #0
 80006a6:	f880 3020 	strb.w	r3, [r0, #32]
    if(hdma->XferCpltCallback != NULL)
 80006aa:	6a83      	ldr	r3, [r0, #40]	; 0x28
 80006ac:	e79e      	b.n	80005ec <HAL_DMA_IRQHandler+0x54>
      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
 80006ae:	2302      	movs	r3, #2
 80006b0:	e7f6      	b.n	80006a0 <HAL_DMA_IRQHandler+0x108>
 80006b2:	2320      	movs	r3, #32
 80006b4:	e7f4      	b.n	80006a0 <HAL_DMA_IRQHandler+0x108>
 80006b6:	f44f 7300 	mov.w	r3, #512	; 0x200
 80006ba:	e7f1      	b.n	80006a0 <HAL_DMA_IRQHandler+0x108>
 80006bc:	4922      	ldr	r1, [pc, #136]	; (8000748 <HAL_DMA_IRQHandler+0x1b0>)
 80006be:	428b      	cmp	r3, r1
 80006c0:	d016      	beq.n	80006f0 <HAL_DMA_IRQHandler+0x158>
 80006c2:	3114      	adds	r1, #20
 80006c4:	428b      	cmp	r3, r1
 80006c6:	d015      	beq.n	80006f4 <HAL_DMA_IRQHandler+0x15c>
 80006c8:	3114      	adds	r1, #20
 80006ca:	428b      	cmp	r3, r1
 80006cc:	d014      	beq.n	80006f8 <HAL_DMA_IRQHandler+0x160>
 80006ce:	3114      	adds	r1, #20
 80006d0:	428b      	cmp	r3, r1
 80006d2:	d014      	beq.n	80006fe <HAL_DMA_IRQHandler+0x166>
 80006d4:	3114      	adds	r1, #20
 80006d6:	428b      	cmp	r3, r1
 80006d8:	d014      	beq.n	8000704 <HAL_DMA_IRQHandler+0x16c>
 80006da:	3114      	adds	r1, #20
 80006dc:	428b      	cmp	r3, r1
 80006de:	d014      	beq.n	800070a <HAL_DMA_IRQHandler+0x172>
 80006e0:	4293      	cmp	r3, r2
 80006e2:	bf14      	ite	ne
 80006e4:	f44f 3300 	movne.w	r3, #131072	; 0x20000
 80006e8:	f04f 7300 	moveq.w	r3, #33554432	; 0x2000000
 80006ec:	4a17      	ldr	r2, [pc, #92]	; (800074c <HAL_DMA_IRQHandler+0x1b4>)
 80006ee:	e7d8      	b.n	80006a2 <HAL_DMA_IRQHandler+0x10a>
 80006f0:	2302      	movs	r3, #2
 80006f2:	e7fb      	b.n	80006ec <HAL_DMA_IRQHandler+0x154>
 80006f4:	2320      	movs	r3, #32
 80006f6:	e7f9      	b.n	80006ec <HAL_DMA_IRQHandler+0x154>
 80006f8:	f44f 7300 	mov.w	r3, #512	; 0x200
 80006fc:	e7f6      	b.n	80006ec <HAL_DMA_IRQHandler+0x154>
 80006fe:	f44f 5300 	mov.w	r3, #8192	; 0x2000
 8000702:	e7f3      	b.n	80006ec <HAL_DMA_IRQHandler+0x154>
 8000704:	f44f 3300 	mov.w	r3, #131072	; 0x20000
 8000708:	e7f0      	b.n	80006ec <HAL_DMA_IRQHandler+0x154>
 800070a:	f44f 1300 	mov.w	r3, #2097152	; 0x200000
 800070e:	e7ed      	b.n	80006ec <HAL_DMA_IRQHandler+0x154>
  else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
 8000710:	2508      	movs	r5, #8
 8000712:	4095      	lsls	r5, r2
 8000714:	4225      	tst	r5, r4
 8000716:	d011      	beq.n	800073c <HAL_DMA_IRQHandler+0x1a4>
 8000718:	0709      	lsls	r1, r1, #28
 800071a:	d50f      	bpl.n	800073c <HAL_DMA_IRQHandler+0x1a4>
    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
 800071c:	6819      	ldr	r1, [r3, #0]
 800071e:	f021 010e 	bic.w	r1, r1, #14
 8000722:	6019      	str	r1, [r3, #0]
    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
 8000724:	2301      	movs	r3, #1
 8000726:	fa03 f202 	lsl.w	r2, r3, r2
 800072a:	6072      	str	r2, [r6, #4]
    hdma->ErrorCode = HAL_DMA_ERROR_TE;
 800072c:	6383      	str	r3, [r0, #56]	; 0x38
    hdma->State = HAL_DMA_STATE_READY;
 800072e:	f880 3021 	strb.w	r3, [r0, #33]	; 0x21
    __HAL_UNLOCK(hdma);
 8000732:	2300      	movs	r3, #0
 8000734:	f880 3020 	strb.w	r3, [r0, #32]
    if (hdma->XferErrorCallback != NULL)
 8000738:	6b03      	ldr	r3, [r0, #48]	; 0x30
 800073a:	e757      	b.n	80005ec <HAL_DMA_IRQHandler+0x54>
}
 800073c:	bc70      	pop	{r4, r5, r6}
 800073e:	4770      	bx	lr
 8000740:	40020080 	.word	0x40020080
 8000744:	40020400 	.word	0x40020400
 8000748:	40020008 	.word	0x40020008
 800074c:	40020000 	.word	0x40020000

08000750 <FLASH_SetErrorCode>:
  uint32_t flags = 0U;
  
#if defined(FLASH_BANK2_END)
  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2))
#else
  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
 8000750:	4a11      	ldr	r2, [pc, #68]	; (8000798 <FLASH_SetErrorCode+0x48>)
 8000752:	68d3      	ldr	r3, [r2, #12]
 8000754:	f013 0310 	ands.w	r3, r3, #16
 8000758:	d005      	beq.n	8000766 <FLASH_SetErrorCode+0x16>
#endif /* FLASH_BANK2_END */
  {
    pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
 800075a:	4910      	ldr	r1, [pc, #64]	; (800079c <FLASH_SetErrorCode+0x4c>)
 800075c:	69cb      	ldr	r3, [r1, #28]
 800075e:	f043 0302 	orr.w	r3, r3, #2
 8000762:	61cb      	str	r3, [r1, #28]
#if defined(FLASH_BANK2_END)
    flags |= FLASH_FLAG_WRPERR | FLASH_FLAG_WRPERR_BANK2;
#else
    flags |= FLASH_FLAG_WRPERR;
 8000764:	2310      	movs	r3, #16
#endif /* FLASH_BANK2_END */
  }
#if defined(FLASH_BANK2_END)
  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2))
#else
  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
 8000766:	68d2      	ldr	r2, [r2, #12]
 8000768:	0750      	lsls	r0, r2, #29
 800076a:	d506      	bpl.n	800077a <FLASH_SetErrorCode+0x2a>
#endif /* FLASH_BANK2_END */
  {
    pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG;
 800076c:	490b      	ldr	r1, [pc, #44]	; (800079c <FLASH_SetErrorCode+0x4c>)
#if defined(FLASH_BANK2_END)
    flags |= FLASH_FLAG_PGERR | FLASH_FLAG_PGERR_BANK2;
#else
    flags |= FLASH_FLAG_PGERR;
 800076e:	f043 0304 	orr.w	r3, r3, #4
    pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG;
 8000772:	69ca      	ldr	r2, [r1, #28]
 8000774:	f042 0201 	orr.w	r2, r2, #1
 8000778:	61ca      	str	r2, [r1, #28]
#endif /* FLASH_BANK2_END */
  }
  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR))
 800077a:	4a07      	ldr	r2, [pc, #28]	; (8000798 <FLASH_SetErrorCode+0x48>)
 800077c:	69d1      	ldr	r1, [r2, #28]
 800077e:	07c9      	lsls	r1, r1, #31
 8000780:	d508      	bpl.n	8000794 <FLASH_SetErrorCode+0x44>
  {
    pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV;
 8000782:	4806      	ldr	r0, [pc, #24]	; (800079c <FLASH_SetErrorCode+0x4c>)
 8000784:	69c1      	ldr	r1, [r0, #28]
 8000786:	f041 0104 	orr.w	r1, r1, #4
 800078a:	61c1      	str	r1, [r0, #28]
  __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR);
 800078c:	69d1      	ldr	r1, [r2, #28]
 800078e:	f021 0101 	bic.w	r1, r1, #1
 8000792:	61d1      	str	r1, [r2, #28]
  }

  /* Clear FLASH error pending bits */
  __HAL_FLASH_CLEAR_FLAG(flags);
 8000794:	60d3      	str	r3, [r2, #12]
 8000796:	4770      	bx	lr
 8000798:	40022000 	.word	0x40022000
 800079c:	200002f8 	.word	0x200002f8

080007a0 <HAL_FLASH_Unlock>:
  if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
 80007a0:	4b06      	ldr	r3, [pc, #24]	; (80007bc <HAL_FLASH_Unlock+0x1c>)
 80007a2:	6918      	ldr	r0, [r3, #16]
 80007a4:	f010 0080 	ands.w	r0, r0, #128	; 0x80
 80007a8:	d007      	beq.n	80007ba <HAL_FLASH_Unlock+0x1a>
    WRITE_REG(FLASH->KEYR, FLASH_KEY1);
 80007aa:	4a05      	ldr	r2, [pc, #20]	; (80007c0 <HAL_FLASH_Unlock+0x20>)
 80007ac:	605a      	str	r2, [r3, #4]
    WRITE_REG(FLASH->KEYR, FLASH_KEY2);
 80007ae:	f102 3288 	add.w	r2, r2, #2290649224	; 0x88888888
 80007b2:	605a      	str	r2, [r3, #4]
    if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
 80007b4:	6918      	ldr	r0, [r3, #16]
  HAL_StatusTypeDef status = HAL_OK;
 80007b6:	f3c0 10c0 	ubfx	r0, r0, #7, #1
}
 80007ba:	4770      	bx	lr
 80007bc:	40022000 	.word	0x40022000
 80007c0:	45670123 	.word	0x45670123

080007c4 <HAL_FLASH_Lock>:
  SET_BIT(FLASH->CR, FLASH_CR_LOCK);
 80007c4:	4a03      	ldr	r2, [pc, #12]	; (80007d4 <HAL_FLASH_Lock+0x10>)
}
 80007c6:	2000      	movs	r0, #0
  SET_BIT(FLASH->CR, FLASH_CR_LOCK);
 80007c8:	6913      	ldr	r3, [r2, #16]
 80007ca:	f043 0380 	orr.w	r3, r3, #128	; 0x80
 80007ce:	6113      	str	r3, [r2, #16]
}
 80007d0:	4770      	bx	lr
 80007d2:	bf00      	nop
 80007d4:	40022000 	.word	0x40022000

080007d8 <FLASH_WaitForLastOperation>:
{
 80007d8:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 80007da:	4606      	mov	r6, r0
  uint32_t tickstart = HAL_GetTick();
 80007dc:	f7ff fd70 	bl	80002c0 <HAL_GetTick>
  while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) 
 80007e0:	4c11      	ldr	r4, [pc, #68]	; (8000828 <FLASH_WaitForLastOperation+0x50>)
  uint32_t tickstart = HAL_GetTick();
 80007e2:	4607      	mov	r7, r0
 80007e4:	4625      	mov	r5, r4
  while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) 
 80007e6:	68e3      	ldr	r3, [r4, #12]
 80007e8:	07d8      	lsls	r0, r3, #31
 80007ea:	d412      	bmi.n	8000812 <FLASH_WaitForLastOperation+0x3a>
  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
 80007ec:	68e3      	ldr	r3, [r4, #12]
 80007ee:	0699      	lsls	r1, r3, #26
    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
 80007f0:	bf44      	itt	mi
 80007f2:	2320      	movmi	r3, #32
 80007f4:	60e3      	strmi	r3, [r4, #12]
  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)  || 
 80007f6:	68eb      	ldr	r3, [r5, #12]
 80007f8:	06da      	lsls	r2, r3, #27
 80007fa:	d406      	bmi.n	800080a <FLASH_WaitForLastOperation+0x32>
     __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || 
 80007fc:	69eb      	ldr	r3, [r5, #28]
  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)  || 
 80007fe:	07db      	lsls	r3, r3, #31
 8000800:	d403      	bmi.n	800080a <FLASH_WaitForLastOperation+0x32>
     __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
 8000802:	68e8      	ldr	r0, [r5, #12]
     __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || 
 8000804:	f010 0004 	ands.w	r0, r0, #4
 8000808:	d002      	beq.n	8000810 <FLASH_WaitForLastOperation+0x38>
    FLASH_SetErrorCode();
 800080a:	f7ff ffa1 	bl	8000750 <FLASH_SetErrorCode>
    return HAL_ERROR;
 800080e:	2001      	movs	r0, #1
}
 8000810:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    if (Timeout != HAL_MAX_DELAY)
 8000812:	1c73      	adds	r3, r6, #1
 8000814:	d0e7      	beq.n	80007e6 <FLASH_WaitForLastOperation+0xe>
      if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
 8000816:	b90e      	cbnz	r6, 800081c <FLASH_WaitForLastOperation+0x44>
        return HAL_TIMEOUT;
 8000818:	2003      	movs	r0, #3
 800081a:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
      if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
 800081c:	f7ff fd50 	bl	80002c0 <HAL_GetTick>
 8000820:	1bc0      	subs	r0, r0, r7
 8000822:	4286      	cmp	r6, r0
 8000824:	d2df      	bcs.n	80007e6 <FLASH_WaitForLastOperation+0xe>
 8000826:	e7f7      	b.n	8000818 <FLASH_WaitForLastOperation+0x40>
 8000828:	40022000 	.word	0x40022000

0800082c <HAL_FLASH_Program>:
{
 800082c:	e92d 4ff8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
  __HAL_LOCK(&pFlash);
 8000830:	4c1f      	ldr	r4, [pc, #124]	; (80008b0 <HAL_FLASH_Program+0x84>)
{
 8000832:	4699      	mov	r9, r3
  __HAL_LOCK(&pFlash);
 8000834:	7e23      	ldrb	r3, [r4, #24]
{
 8000836:	4605      	mov	r5, r0
  __HAL_LOCK(&pFlash);
 8000838:	2b01      	cmp	r3, #1
{
 800083a:	460f      	mov	r7, r1
 800083c:	4690      	mov	r8, r2
  __HAL_LOCK(&pFlash);
 800083e:	d033      	beq.n	80008a8 <HAL_FLASH_Program+0x7c>
 8000840:	2301      	movs	r3, #1
    status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
 8000842:	f24c 3050 	movw	r0, #50000	; 0xc350
  __HAL_LOCK(&pFlash);
 8000846:	7623      	strb	r3, [r4, #24]
    status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
 8000848:	f7ff ffc6 	bl	80007d8 <FLASH_WaitForLastOperation>
  if(status == HAL_OK)
 800084c:	bb40      	cbnz	r0, 80008a0 <HAL_FLASH_Program+0x74>
    if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
 800084e:	2d01      	cmp	r5, #1
 8000850:	d003      	beq.n	800085a <HAL_FLASH_Program+0x2e>
      nbiterations = 4U;
 8000852:	2d02      	cmp	r5, #2
 8000854:	bf0c      	ite	eq
 8000856:	2502      	moveq	r5, #2
 8000858:	2504      	movne	r5, #4
 800085a:	2600      	movs	r6, #0
  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
 800085c:	46b2      	mov	sl, r6
    SET_BIT(FLASH->CR, FLASH_CR_PG);
 800085e:	f8df b054 	ldr.w	fp, [pc, #84]	; 80008b4 <HAL_FLASH_Program+0x88>
      FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index)));
 8000862:	0132      	lsls	r2, r6, #4
 8000864:	4640      	mov	r0, r8
 8000866:	4649      	mov	r1, r9
 8000868:	f7ff fcdc 	bl	8000224 <__aeabi_llsr>
  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
 800086c:	f8c4 a01c 	str.w	sl, [r4, #28]
    SET_BIT(FLASH->CR, FLASH_CR_PG);
 8000870:	f8db 3010 	ldr.w	r3, [fp, #16]
      FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index)));
 8000874:	b280      	uxth	r0, r0
    SET_BIT(FLASH->CR, FLASH_CR_PG);
 8000876:	f043 0301 	orr.w	r3, r3, #1
 800087a:	f8cb 3010 	str.w	r3, [fp, #16]
  *(__IO uint16_t*)Address = Data;
 800087e:	f827 0016 	strh.w	r0, [r7, r6, lsl #1]
        status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
 8000882:	f24c 3050 	movw	r0, #50000	; 0xc350
 8000886:	f7ff ffa7 	bl	80007d8 <FLASH_WaitForLastOperation>
        CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
 800088a:	f8db 3010 	ldr.w	r3, [fp, #16]
 800088e:	f023 0301 	bic.w	r3, r3, #1
 8000892:	f8cb 3010 	str.w	r3, [fp, #16]
      if (status != HAL_OK)
 8000896:	b918      	cbnz	r0, 80008a0 <HAL_FLASH_Program+0x74>
 8000898:	3601      	adds	r6, #1
    for (index = 0U; index < nbiterations; index++)
 800089a:	b2f3      	uxtb	r3, r6
 800089c:	429d      	cmp	r5, r3
 800089e:	d8e0      	bhi.n	8000862 <HAL_FLASH_Program+0x36>
  __HAL_UNLOCK(&pFlash);
 80008a0:	2300      	movs	r3, #0
 80008a2:	7623      	strb	r3, [r4, #24]
  return status;
 80008a4:	e8bd 8ff8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
  __HAL_LOCK(&pFlash);
 80008a8:	2002      	movs	r0, #2
}
 80008aa:	e8bd 8ff8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
 80008ae:	bf00      	nop
 80008b0:	200002f8 	.word	0x200002f8
 80008b4:	40022000 	.word	0x40022000

080008b8 <FLASH_MassErase.isra.0>:
{
  /* Check the parameters */
  assert_param(IS_FLASH_BANK(Banks));

  /* Clean the error context */
  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
 80008b8:	2200      	movs	r2, #0
 80008ba:	4b06      	ldr	r3, [pc, #24]	; (80008d4 <FLASH_MassErase.isra.0+0x1c>)
 80008bc:	61da      	str	r2, [r3, #28]
#if !defined(FLASH_BANK2_END)
  /* Prevent unused argument(s) compilation warning */
  UNUSED(Banks);
#endif /* FLASH_BANK2_END */  
    /* Only bank1 will be erased*/
    SET_BIT(FLASH->CR, FLASH_CR_MER);
 80008be:	4b06      	ldr	r3, [pc, #24]	; (80008d8 <FLASH_MassErase.isra.0+0x20>)
 80008c0:	691a      	ldr	r2, [r3, #16]
 80008c2:	f042 0204 	orr.w	r2, r2, #4
 80008c6:	611a      	str	r2, [r3, #16]
    SET_BIT(FLASH->CR, FLASH_CR_STRT);
 80008c8:	691a      	ldr	r2, [r3, #16]
 80008ca:	f042 0240 	orr.w	r2, r2, #64	; 0x40
 80008ce:	611a      	str	r2, [r3, #16]
 80008d0:	4770      	bx	lr
 80008d2:	bf00      	nop
 80008d4:	200002f8 	.word	0x200002f8
 80008d8:	40022000 	.word	0x40022000

080008dc <FLASH_PageErase>:
  * @retval None
  */
void FLASH_PageErase(uint32_t PageAddress)
{
  /* Clean the error context */
  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
 80008dc:	2200      	movs	r2, #0
 80008de:	4b06      	ldr	r3, [pc, #24]	; (80008f8 <FLASH_PageErase+0x1c>)
 80008e0:	61da      	str	r2, [r3, #28]
  }
  else
  {
#endif /* FLASH_BANK2_END */
    /* Proceed to erase the page */
    SET_BIT(FLASH->CR, FLASH_CR_PER);
 80008e2:	4b06      	ldr	r3, [pc, #24]	; (80008fc <FLASH_PageErase+0x20>)
 80008e4:	691a      	ldr	r2, [r3, #16]
 80008e6:	f042 0202 	orr.w	r2, r2, #2
 80008ea:	611a      	str	r2, [r3, #16]
    WRITE_REG(FLASH->AR, PageAddress);
 80008ec:	6158      	str	r0, [r3, #20]
    SET_BIT(FLASH->CR, FLASH_CR_STRT);
 80008ee:	691a      	ldr	r2, [r3, #16]
 80008f0:	f042 0240 	orr.w	r2, r2, #64	; 0x40
 80008f4:	611a      	str	r2, [r3, #16]
 80008f6:	4770      	bx	lr
 80008f8:	200002f8 	.word	0x200002f8
 80008fc:	40022000 	.word	0x40022000

08000900 <HAL_FLASHEx_Erase>:
{
 8000900:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
  __HAL_LOCK(&pFlash);
 8000904:	4d23      	ldr	r5, [pc, #140]	; (8000994 <HAL_FLASHEx_Erase+0x94>)
{
 8000906:	4607      	mov	r7, r0
  __HAL_LOCK(&pFlash);
 8000908:	7e2b      	ldrb	r3, [r5, #24]
{
 800090a:	4688      	mov	r8, r1
  __HAL_LOCK(&pFlash);
 800090c:	2b01      	cmp	r3, #1
 800090e:	d03d      	beq.n	800098c <HAL_FLASHEx_Erase+0x8c>
 8000910:	2401      	movs	r4, #1
  if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
 8000912:	6803      	ldr	r3, [r0, #0]
  __HAL_LOCK(&pFlash);
 8000914:	762c      	strb	r4, [r5, #24]
  if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
 8000916:	2b02      	cmp	r3, #2
      if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
 8000918:	f24c 3050 	movw	r0, #50000	; 0xc350
  if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
 800091c:	d113      	bne.n	8000946 <HAL_FLASHEx_Erase+0x46>
      if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
 800091e:	f7ff ff5b 	bl	80007d8 <FLASH_WaitForLastOperation>
 8000922:	b120      	cbz	r0, 800092e <HAL_FLASHEx_Erase+0x2e>
  HAL_StatusTypeDef status = HAL_ERROR;
 8000924:	2001      	movs	r0, #1
  __HAL_UNLOCK(&pFlash);
 8000926:	2300      	movs	r3, #0
 8000928:	762b      	strb	r3, [r5, #24]
  return status;
 800092a:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
        FLASH_MassErase(FLASH_BANK_1);
 800092e:	f7ff ffc3 	bl	80008b8 <FLASH_MassErase.isra.0>
        status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
 8000932:	f24c 3050 	movw	r0, #50000	; 0xc350
 8000936:	f7ff ff4f 	bl	80007d8 <FLASH_WaitForLastOperation>
        CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
 800093a:	4a17      	ldr	r2, [pc, #92]	; (8000998 <HAL_FLASHEx_Erase+0x98>)
 800093c:	6913      	ldr	r3, [r2, #16]
 800093e:	f023 0304 	bic.w	r3, r3, #4
 8000942:	6113      	str	r3, [r2, #16]
 8000944:	e7ef      	b.n	8000926 <HAL_FLASHEx_Erase+0x26>
      if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
 8000946:	f7ff ff47 	bl	80007d8 <FLASH_WaitForLastOperation>
 800094a:	2800      	cmp	r0, #0
 800094c:	d1ea      	bne.n	8000924 <HAL_FLASHEx_Erase+0x24>
        *PageError = 0xFFFFFFFFU;
 800094e:	f04f 33ff 	mov.w	r3, #4294967295
 8000952:	f8c8 3000 	str.w	r3, [r8]
  HAL_StatusTypeDef status = HAL_ERROR;
 8000956:	4620      	mov	r0, r4
        for(address = pEraseInit->PageAddress;
 8000958:	68be      	ldr	r6, [r7, #8]
          CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
 800095a:	4c0f      	ldr	r4, [pc, #60]	; (8000998 <HAL_FLASHEx_Erase+0x98>)
            address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress);
 800095c:	68fa      	ldr	r2, [r7, #12]
 800095e:	68bb      	ldr	r3, [r7, #8]
 8000960:	eb03 23c2 	add.w	r3, r3, r2, lsl #11
        for(address = pEraseInit->PageAddress;
 8000964:	429e      	cmp	r6, r3
 8000966:	d2de      	bcs.n	8000926 <HAL_FLASHEx_Erase+0x26>
          FLASH_PageErase(address);
 8000968:	4630      	mov	r0, r6
 800096a:	f7ff ffb7 	bl	80008dc <FLASH_PageErase>
          status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
 800096e:	f24c 3050 	movw	r0, #50000	; 0xc350
 8000972:	f7ff ff31 	bl	80007d8 <FLASH_WaitForLastOperation>
          CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
 8000976:	6923      	ldr	r3, [r4, #16]
 8000978:	f023 0302 	bic.w	r3, r3, #2
 800097c:	6123      	str	r3, [r4, #16]
          if (status != HAL_OK)
 800097e:	b110      	cbz	r0, 8000986 <HAL_FLASHEx_Erase+0x86>
            *PageError = address;
 8000980:	f8c8 6000 	str.w	r6, [r8]
            break;
 8000984:	e7cf      	b.n	8000926 <HAL_FLASHEx_Erase+0x26>
            address += FLASH_PAGE_SIZE)
 8000986:	f506 6600 	add.w	r6, r6, #2048	; 0x800
 800098a:	e7e7      	b.n	800095c <HAL_FLASHEx_Erase+0x5c>
  __HAL_LOCK(&pFlash);
 800098c:	2002      	movs	r0, #2
}
 800098e:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
 8000992:	bf00      	nop
 8000994:	200002f8 	.word	0x200002f8
 8000998:	40022000 	.word	0x40022000

0800099c <HAL_GPIO_Init>:
  * @param  GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
  *         the configuration information for the specified GPIO peripheral.
  * @retval None
  */
void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
 800099c:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
  uint32_t position;
  uint32_t ioposition = 0x00U;
  uint32_t iocurrent = 0x00U;
  uint32_t temp = 0x00U;
  uint32_t config = 0x00U;
 80009a0:	2200      	movs	r2, #0
  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));

  /* Configure the port pins */
  for (position = 0U; position < GPIO_NUMBER; position++)
 80009a2:	4616      	mov	r6, r2
      /*--------------------- EXTI Mode Configuration ------------------------*/
      /* Configure the External Interrupt or event for the current IO */
      if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
      {
        /* Enable AFIO Clock */
        __HAL_RCC_AFIO_CLK_ENABLE();
 80009a4:	4f6c      	ldr	r7, [pc, #432]	; (8000b58 <HAL_GPIO_Init+0x1bc>)
 80009a6:	4b6d      	ldr	r3, [pc, #436]	; (8000b5c <HAL_GPIO_Init+0x1c0>)
        temp = AFIO->EXTICR[position >> 2U];
        CLEAR_BIT(temp, (0x0FU) << (4U * (position & 0x03U)));
        SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
 80009a8:	f8df e1b8 	ldr.w	lr, [pc, #440]	; 8000b64 <HAL_GPIO_Init+0x1c8>
      switch (GPIO_Init->Mode)
 80009ac:	f8df c1b8 	ldr.w	ip, [pc, #440]	; 8000b68 <HAL_GPIO_Init+0x1cc>
    ioposition = (0x01U << position);
 80009b0:	f04f 0801 	mov.w	r8, #1
    iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
 80009b4:	680c      	ldr	r4, [r1, #0]
    ioposition = (0x01U << position);
 80009b6:	fa08 f806 	lsl.w	r8, r8, r6
    iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
 80009ba:	ea08 0404 	and.w	r4, r8, r4
    if (iocurrent == ioposition)
 80009be:	45a0      	cmp	r8, r4
 80009c0:	f040 8085 	bne.w	8000ace <HAL_GPIO_Init+0x132>
      switch (GPIO_Init->Mode)
 80009c4:	684d      	ldr	r5, [r1, #4]
 80009c6:	2d12      	cmp	r5, #18
 80009c8:	f000 80b7 	beq.w	8000b3a <HAL_GPIO_Init+0x19e>
 80009cc:	f200 808d 	bhi.w	8000aea <HAL_GPIO_Init+0x14e>
 80009d0:	2d02      	cmp	r5, #2
 80009d2:	f000 80af 	beq.w	8000b34 <HAL_GPIO_Init+0x198>
 80009d6:	f200 8081 	bhi.w	8000adc <HAL_GPIO_Init+0x140>
 80009da:	2d00      	cmp	r5, #0
 80009dc:	f000 8091 	beq.w	8000b02 <HAL_GPIO_Init+0x166>
 80009e0:	2d01      	cmp	r5, #1
 80009e2:	f000 80a5 	beq.w	8000b30 <HAL_GPIO_Init+0x194>
      MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
 80009e6:	f04f 090f 	mov.w	r9, #15
      configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL     : &GPIOx->CRH;
 80009ea:	2cff      	cmp	r4, #255	; 0xff
 80009ec:	bf93      	iteet	ls
 80009ee:	4682      	movls	sl, r0
 80009f0:	f106 4580 	addhi.w	r5, r6, #1073741824	; 0x40000000
 80009f4:	3d08      	subhi	r5, #8
 80009f6:	f8d0 b000 	ldrls.w	fp, [r0]
 80009fa:	bf92      	itee	ls
 80009fc:	00b5      	lslls	r5, r6, #2
 80009fe:	f8d0 b004 	ldrhi.w	fp, [r0, #4]
 8000a02:	00ad      	lslhi	r5, r5, #2
      MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
 8000a04:	fa09 f805 	lsl.w	r8, r9, r5
 8000a08:	ea2b 0808 	bic.w	r8, fp, r8
 8000a0c:	fa02 f505 	lsl.w	r5, r2, r5
      configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL     : &GPIOx->CRH;
 8000a10:	bf88      	it	hi
 8000a12:	f100 0a04 	addhi.w	sl, r0, #4
      MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
 8000a16:	ea48 0505 	orr.w	r5, r8, r5
 8000a1a:	f8ca 5000 	str.w	r5, [sl]
      if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
 8000a1e:	f8d1 a004 	ldr.w	sl, [r1, #4]
 8000a22:	f01a 5f80 	tst.w	sl, #268435456	; 0x10000000
 8000a26:	d052      	beq.n	8000ace <HAL_GPIO_Init+0x132>
        __HAL_RCC_AFIO_CLK_ENABLE();
 8000a28:	69bd      	ldr	r5, [r7, #24]
 8000a2a:	f026 0803 	bic.w	r8, r6, #3
 8000a2e:	f045 0501 	orr.w	r5, r5, #1
 8000a32:	61bd      	str	r5, [r7, #24]
 8000a34:	69bd      	ldr	r5, [r7, #24]
 8000a36:	f108 4880 	add.w	r8, r8, #1073741824	; 0x40000000
 8000a3a:	f005 0501 	and.w	r5, r5, #1
 8000a3e:	9501      	str	r5, [sp, #4]
 8000a40:	f508 3880 	add.w	r8, r8, #65536	; 0x10000
        CLEAR_BIT(temp, (0x0FU) << (4U * (position & 0x03U)));
 8000a44:	f006 0b03 	and.w	fp, r6, #3
        __HAL_RCC_AFIO_CLK_ENABLE();
 8000a48:	9d01      	ldr	r5, [sp, #4]
        CLEAR_BIT(temp, (0x0FU) << (4U * (position & 0x03U)));
 8000a4a:	ea4f 0b8b 	mov.w	fp, fp, lsl #2
        temp = AFIO->EXTICR[position >> 2U];
 8000a4e:	f8d8 5008 	ldr.w	r5, [r8, #8]
        CLEAR_BIT(temp, (0x0FU) << (4U * (position & 0x03U)));
 8000a52:	fa09 f90b 	lsl.w	r9, r9, fp
 8000a56:	ea25 0909 	bic.w	r9, r5, r9
        SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
 8000a5a:	4d41      	ldr	r5, [pc, #260]	; (8000b60 <HAL_GPIO_Init+0x1c4>)
 8000a5c:	42a8      	cmp	r0, r5
 8000a5e:	d071      	beq.n	8000b44 <HAL_GPIO_Init+0x1a8>
 8000a60:	f505 6580 	add.w	r5, r5, #1024	; 0x400
 8000a64:	42a8      	cmp	r0, r5
 8000a66:	d06f      	beq.n	8000b48 <HAL_GPIO_Init+0x1ac>
 8000a68:	f505 6580 	add.w	r5, r5, #1024	; 0x400
 8000a6c:	42a8      	cmp	r0, r5
 8000a6e:	d06d      	beq.n	8000b4c <HAL_GPIO_Init+0x1b0>
 8000a70:	f505 6580 	add.w	r5, r5, #1024	; 0x400
 8000a74:	42a8      	cmp	r0, r5
 8000a76:	d06b      	beq.n	8000b50 <HAL_GPIO_Init+0x1b4>
 8000a78:	f505 6580 	add.w	r5, r5, #1024	; 0x400
 8000a7c:	42a8      	cmp	r0, r5
 8000a7e:	d069      	beq.n	8000b54 <HAL_GPIO_Init+0x1b8>
 8000a80:	4570      	cmp	r0, lr
 8000a82:	bf0c      	ite	eq
 8000a84:	2505      	moveq	r5, #5
 8000a86:	2506      	movne	r5, #6
 8000a88:	fa05 f50b 	lsl.w	r5, r5, fp
 8000a8c:	ea45 0509 	orr.w	r5, r5, r9
        AFIO->EXTICR[position >> 2U] = temp;
 8000a90:	f8c8 5008 	str.w	r5, [r8, #8]


        /* Configure the interrupt mask */
        if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
        {
          SET_BIT(EXTI->IMR, iocurrent);
 8000a94:	681d      	ldr	r5, [r3, #0]
        if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
 8000a96:	f41a 3f80 	tst.w	sl, #65536	; 0x10000
          SET_BIT(EXTI->IMR, iocurrent);
 8000a9a:	bf14      	ite	ne
 8000a9c:	4325      	orrne	r5, r4
        }
        else
        {
          CLEAR_BIT(EXTI->IMR, iocurrent);
 8000a9e:	43a5      	biceq	r5, r4
 8000aa0:	601d      	str	r5, [r3, #0]
        }

        /* Configure the event mask */
        if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
        {
          SET_BIT(EXTI->EMR, iocurrent);
 8000aa2:	685d      	ldr	r5, [r3, #4]
        if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
 8000aa4:	f41a 3f00 	tst.w	sl, #131072	; 0x20000
          SET_BIT(EXTI->EMR, iocurrent);
 8000aa8:	bf14      	ite	ne
 8000aaa:	4325      	orrne	r5, r4
        }
        else
        {
          CLEAR_BIT(EXTI->EMR, iocurrent);
 8000aac:	43a5      	biceq	r5, r4
 8000aae:	605d      	str	r5, [r3, #4]
        }

        /* Enable or disable the rising trigger */
        if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
        {
          SET_BIT(EXTI->RTSR, iocurrent);
 8000ab0:	689d      	ldr	r5, [r3, #8]
        if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
 8000ab2:	f41a 1f80 	tst.w	sl, #1048576	; 0x100000
          SET_BIT(EXTI->RTSR, iocurrent);
 8000ab6:	bf14      	ite	ne
 8000ab8:	4325      	orrne	r5, r4
        }
        else
        {
          CLEAR_BIT(EXTI->RTSR, iocurrent);
 8000aba:	43a5      	biceq	r5, r4
 8000abc:	609d      	str	r5, [r3, #8]
        }

        /* Enable or disable the falling trigger */
        if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
        {
          SET_BIT(EXTI->FTSR, iocurrent);
 8000abe:	68dd      	ldr	r5, [r3, #12]
        if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
 8000ac0:	f41a 1f00 	tst.w	sl, #2097152	; 0x200000
          SET_BIT(EXTI->FTSR, iocurrent);
 8000ac4:	bf14      	ite	ne
 8000ac6:	432c      	orrne	r4, r5
        }
        else
        {
          CLEAR_BIT(EXTI->FTSR, iocurrent);
 8000ac8:	ea25 0404 	biceq.w	r4, r5, r4
 8000acc:	60dc      	str	r4, [r3, #12]
  for (position = 0U; position < GPIO_NUMBER; position++)
 8000ace:	3601      	adds	r6, #1
 8000ad0:	2e10      	cmp	r6, #16
 8000ad2:	f47f af6d 	bne.w	80009b0 <HAL_GPIO_Init+0x14>
        }
      }
    }
  }
}
 8000ad6:	b003      	add	sp, #12
 8000ad8:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
      switch (GPIO_Init->Mode)
 8000adc:	2d03      	cmp	r5, #3
 8000ade:	d025      	beq.n	8000b2c <HAL_GPIO_Init+0x190>
 8000ae0:	2d11      	cmp	r5, #17
 8000ae2:	d180      	bne.n	80009e6 <HAL_GPIO_Init+0x4a>
          config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;
 8000ae4:	68ca      	ldr	r2, [r1, #12]
 8000ae6:	3204      	adds	r2, #4
          break;
 8000ae8:	e77d      	b.n	80009e6 <HAL_GPIO_Init+0x4a>
      switch (GPIO_Init->Mode)
 8000aea:	4565      	cmp	r5, ip
 8000aec:	d009      	beq.n	8000b02 <HAL_GPIO_Init+0x166>
 8000aee:	d812      	bhi.n	8000b16 <HAL_GPIO_Init+0x17a>
 8000af0:	f8df 9078 	ldr.w	r9, [pc, #120]	; 8000b6c <HAL_GPIO_Init+0x1d0>
 8000af4:	454d      	cmp	r5, r9
 8000af6:	d004      	beq.n	8000b02 <HAL_GPIO_Init+0x166>
 8000af8:	f509 3980 	add.w	r9, r9, #65536	; 0x10000
 8000afc:	454d      	cmp	r5, r9
 8000afe:	f47f af72 	bne.w	80009e6 <HAL_GPIO_Init+0x4a>
          if (GPIO_Init->Pull == GPIO_NOPULL)
 8000b02:	688a      	ldr	r2, [r1, #8]
 8000b04:	b1e2      	cbz	r2, 8000b40 <HAL_GPIO_Init+0x1a4>
          else if (GPIO_Init->Pull == GPIO_PULLUP)
 8000b06:	2a01      	cmp	r2, #1
            GPIOx->BSRR = ioposition;
 8000b08:	bf0c      	ite	eq
 8000b0a:	f8c0 8010 	streq.w	r8, [r0, #16]
            GPIOx->BRR = ioposition;
 8000b0e:	f8c0 8014 	strne.w	r8, [r0, #20]
            config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
 8000b12:	2208      	movs	r2, #8
 8000b14:	e767      	b.n	80009e6 <HAL_GPIO_Init+0x4a>
      switch (GPIO_Init->Mode)
 8000b16:	f8df 9058 	ldr.w	r9, [pc, #88]	; 8000b70 <HAL_GPIO_Init+0x1d4>
 8000b1a:	454d      	cmp	r5, r9
 8000b1c:	d0f1      	beq.n	8000b02 <HAL_GPIO_Init+0x166>
 8000b1e:	f509 3980 	add.w	r9, r9, #65536	; 0x10000
 8000b22:	454d      	cmp	r5, r9
 8000b24:	d0ed      	beq.n	8000b02 <HAL_GPIO_Init+0x166>
 8000b26:	f5a9 1980 	sub.w	r9, r9, #1048576	; 0x100000
 8000b2a:	e7e7      	b.n	8000afc <HAL_GPIO_Init+0x160>
          config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
 8000b2c:	2200      	movs	r2, #0
 8000b2e:	e75a      	b.n	80009e6 <HAL_GPIO_Init+0x4a>
          config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;
 8000b30:	68ca      	ldr	r2, [r1, #12]
          break;
 8000b32:	e758      	b.n	80009e6 <HAL_GPIO_Init+0x4a>
          config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;
 8000b34:	68ca      	ldr	r2, [r1, #12]
 8000b36:	3208      	adds	r2, #8
          break;
 8000b38:	e755      	b.n	80009e6 <HAL_GPIO_Init+0x4a>
          config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;
 8000b3a:	68ca      	ldr	r2, [r1, #12]
 8000b3c:	320c      	adds	r2, #12
          break;
 8000b3e:	e752      	b.n	80009e6 <HAL_GPIO_Init+0x4a>
            config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
 8000b40:	2204      	movs	r2, #4
 8000b42:	e750      	b.n	80009e6 <HAL_GPIO_Init+0x4a>
        SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
 8000b44:	2500      	movs	r5, #0
 8000b46:	e79f      	b.n	8000a88 <HAL_GPIO_Init+0xec>
 8000b48:	2501      	movs	r5, #1
 8000b4a:	e79d      	b.n	8000a88 <HAL_GPIO_Init+0xec>
 8000b4c:	2502      	movs	r5, #2
 8000b4e:	e79b      	b.n	8000a88 <HAL_GPIO_Init+0xec>
 8000b50:	2503      	movs	r5, #3
 8000b52:	e799      	b.n	8000a88 <HAL_GPIO_Init+0xec>
 8000b54:	2504      	movs	r5, #4
 8000b56:	e797      	b.n	8000a88 <HAL_GPIO_Init+0xec>
 8000b58:	40021000 	.word	0x40021000
 8000b5c:	40010400 	.word	0x40010400
 8000b60:	40010800 	.word	0x40010800
 8000b64:	40011c00 	.word	0x40011c00
 8000b68:	10210000 	.word	0x10210000
 8000b6c:	10110000 	.word	0x10110000
 8000b70:	10310000 	.word	0x10310000

08000b74 <HAL_GPIO_WritePin>:
{
  /* Check the parameters */
  assert_param(IS_GPIO_PIN(GPIO_Pin));
  assert_param(IS_GPIO_PIN_ACTION(PinState));

  if (PinState != GPIO_PIN_RESET)
 8000b74:	b10a      	cbz	r2, 8000b7a <HAL_GPIO_WritePin+0x6>
  {
    GPIOx->BSRR = GPIO_Pin;
  }
  else
  {
    GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
 8000b76:	6101      	str	r1, [r0, #16]
 8000b78:	4770      	bx	lr
 8000b7a:	0409      	lsls	r1, r1, #16
 8000b7c:	e7fb      	b.n	8000b76 <HAL_GPIO_WritePin+0x2>

08000b7e <HAL_GPIO_TogglePin>:
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
  /* Check the parameters */
  assert_param(IS_GPIO_PIN(GPIO_Pin));

  GPIOx->ODR ^= GPIO_Pin;
 8000b7e:	68c3      	ldr	r3, [r0, #12]
 8000b80:	4059      	eors	r1, r3
 8000b82:	60c1      	str	r1, [r0, #12]
 8000b84:	4770      	bx	lr
	...

08000b88 <HAL_I2C_Init>:
  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
  *         the configuration information for I2C module
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
{
 8000b88:	b538      	push	{r3, r4, r5, lr}
  uint32_t freqrange = 0U;
  uint32_t pclk1 = 0U;

  /* Check the I2C handle allocation */
  if(hi2c == NULL)
 8000b8a:	4604      	mov	r4, r0
 8000b8c:	b908      	cbnz	r0, 8000b92 <HAL_I2C_Init+0xa>
  {
    return HAL_ERROR;
 8000b8e:	2001      	movs	r0, #1
 8000b90:	bd38      	pop	{r3, r4, r5, pc}
  assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
  assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
  assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
  assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));

  if(hi2c->State == HAL_I2C_STATE_RESET)
 8000b92:	f890 303d 	ldrb.w	r3, [r0, #61]	; 0x3d
 8000b96:	f003 02ff 	and.w	r2, r3, #255	; 0xff
 8000b9a:	b91b      	cbnz	r3, 8000ba4 <HAL_I2C_Init+0x1c>
  {
    /* Allocate lock resource and initialize it */
    hi2c->Lock = HAL_UNLOCKED;
 8000b9c:	f880 203c 	strb.w	r2, [r0, #60]	; 0x3c
    /* Init the low level hardware : GPIO, CLOCK, NVIC */
    HAL_I2C_MspInit(hi2c);
 8000ba0:	f001 fb4c 	bl	800223c <HAL_I2C_MspInit>
  }

  hi2c->State = HAL_I2C_STATE_BUSY;
 8000ba4:	2324      	movs	r3, #36	; 0x24

  /* Disable the selected I2C peripheral */
  __HAL_I2C_DISABLE(hi2c);
 8000ba6:	6822      	ldr	r2, [r4, #0]
  hi2c->State = HAL_I2C_STATE_BUSY;
 8000ba8:	f884 303d 	strb.w	r3, [r4, #61]	; 0x3d
  __HAL_I2C_DISABLE(hi2c);
 8000bac:	6813      	ldr	r3, [r2, #0]
 8000bae:	f023 0301 	bic.w	r3, r3, #1
 8000bb2:	6013      	str	r3, [r2, #0]

  /* Get PCLK1 frequency */
  pclk1 = HAL_RCC_GetPCLK1Freq();
 8000bb4:	f000 fae2 	bl	800117c <HAL_RCC_GetPCLK1Freq>

  /* Check the minimum allowed PCLK1 frequency */
  if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U)
 8000bb8:	6863      	ldr	r3, [r4, #4]
 8000bba:	4a2f      	ldr	r2, [pc, #188]	; (8000c78 <HAL_I2C_Init+0xf0>)
 8000bbc:	4293      	cmp	r3, r2
 8000bbe:	d830      	bhi.n	8000c22 <HAL_I2C_Init+0x9a>
 8000bc0:	4a2e      	ldr	r2, [pc, #184]	; (8000c7c <HAL_I2C_Init+0xf4>)
 8000bc2:	4290      	cmp	r0, r2
 8000bc4:	d9e3      	bls.n	8000b8e <HAL_I2C_Init+0x6>
  {
    return HAL_ERROR;
  }

  /* Calculate frequency range */
  freqrange = I2C_FREQRANGE(pclk1);
 8000bc6:	4a2e      	ldr	r2, [pc, #184]	; (8000c80 <HAL_I2C_Init+0xf8>)

  /*---------------------------- I2Cx CR2 Configuration ----------------------*/
  /* Configure I2Cx: Frequency range */
  hi2c->Instance->CR2 = freqrange;
 8000bc8:	6821      	ldr	r1, [r4, #0]
  freqrange = I2C_FREQRANGE(pclk1);
 8000bca:	fbb0 f2f2 	udiv	r2, r0, r2
  hi2c->Instance->CR2 = freqrange;
 8000bce:	604a      	str	r2, [r1, #4]

  /*---------------------------- I2Cx TRISE Configuration --------------------*/
  /* Configure I2Cx: Rise Time */
  hi2c->Instance->TRISE = I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed);
 8000bd0:	3201      	adds	r2, #1
 8000bd2:	620a      	str	r2, [r1, #32]

  /*---------------------------- I2Cx CCR Configuration ----------------------*/
  /* Configure I2Cx: Speed */
  hi2c->Instance->CCR = I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle);
 8000bd4:	4a28      	ldr	r2, [pc, #160]	; (8000c78 <HAL_I2C_Init+0xf0>)
 8000bd6:	3801      	subs	r0, #1
 8000bd8:	4293      	cmp	r3, r2
 8000bda:	d832      	bhi.n	8000c42 <HAL_I2C_Init+0xba>
 8000bdc:	005b      	lsls	r3, r3, #1
 8000bde:	fbb0 f0f3 	udiv	r0, r0, r3
 8000be2:	1c43      	adds	r3, r0, #1
 8000be4:	f3c3 030b 	ubfx	r3, r3, #0, #12
 8000be8:	2b04      	cmp	r3, #4
 8000bea:	bf38      	it	cc
 8000bec:	2304      	movcc	r3, #4
 8000bee:	61cb      	str	r3, [r1, #28]

  /*---------------------------- I2Cx CR1 Configuration ----------------------*/
  /* Configure I2Cx: Generalcall and NoStretch mode */
  hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
 8000bf0:	6a22      	ldr	r2, [r4, #32]
 8000bf2:	69e3      	ldr	r3, [r4, #28]
  hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2);

  /* Enable the selected I2C peripheral */
  __HAL_I2C_ENABLE(hi2c);

  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
 8000bf4:	2000      	movs	r0, #0
  hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
 8000bf6:	4313      	orrs	r3, r2
 8000bf8:	600b      	str	r3, [r1, #0]
  hi2c->Instance->OAR1 = (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1);
 8000bfa:	68e2      	ldr	r2, [r4, #12]
 8000bfc:	6923      	ldr	r3, [r4, #16]
 8000bfe:	4313      	orrs	r3, r2
 8000c00:	608b      	str	r3, [r1, #8]
  hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2);
 8000c02:	69a2      	ldr	r2, [r4, #24]
 8000c04:	6963      	ldr	r3, [r4, #20]
 8000c06:	4313      	orrs	r3, r2
 8000c08:	60cb      	str	r3, [r1, #12]
  __HAL_I2C_ENABLE(hi2c);
 8000c0a:	680b      	ldr	r3, [r1, #0]
 8000c0c:	f043 0301 	orr.w	r3, r3, #1
 8000c10:	600b      	str	r3, [r1, #0]
  hi2c->State = HAL_I2C_STATE_READY;
 8000c12:	2320      	movs	r3, #32
  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
 8000c14:	6420      	str	r0, [r4, #64]	; 0x40
  hi2c->State = HAL_I2C_STATE_READY;
 8000c16:	f884 303d 	strb.w	r3, [r4, #61]	; 0x3d
  hi2c->PreviousState = I2C_STATE_NONE;
 8000c1a:	6320      	str	r0, [r4, #48]	; 0x30
  hi2c->Mode = HAL_I2C_MODE_NONE;
 8000c1c:	f884 003e 	strb.w	r0, [r4, #62]	; 0x3e

  return HAL_OK;
 8000c20:	bd38      	pop	{r3, r4, r5, pc}
  if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U)
 8000c22:	4a18      	ldr	r2, [pc, #96]	; (8000c84 <HAL_I2C_Init+0xfc>)
 8000c24:	4290      	cmp	r0, r2
 8000c26:	d9b2      	bls.n	8000b8e <HAL_I2C_Init+0x6>
  freqrange = I2C_FREQRANGE(pclk1);
 8000c28:	4d15      	ldr	r5, [pc, #84]	; (8000c80 <HAL_I2C_Init+0xf8>)
  hi2c->Instance->TRISE = I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed);
 8000c2a:	f44f 7296 	mov.w	r2, #300	; 0x12c
  freqrange = I2C_FREQRANGE(pclk1);
 8000c2e:	fbb0 f5f5 	udiv	r5, r0, r5
  hi2c->Instance->CR2 = freqrange;
 8000c32:	6821      	ldr	r1, [r4, #0]
  hi2c->Instance->TRISE = I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed);
 8000c34:	436a      	muls	r2, r5
  hi2c->Instance->CR2 = freqrange;
 8000c36:	604d      	str	r5, [r1, #4]
  hi2c->Instance->TRISE = I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed);
 8000c38:	f44f 757a 	mov.w	r5, #1000	; 0x3e8
 8000c3c:	fbb2 f2f5 	udiv	r2, r2, r5
 8000c40:	e7c6      	b.n	8000bd0 <HAL_I2C_Init+0x48>
  hi2c->Instance->CCR = I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle);
 8000c42:	68a2      	ldr	r2, [r4, #8]
 8000c44:	b952      	cbnz	r2, 8000c5c <HAL_I2C_Init+0xd4>
 8000c46:	eb03 0343 	add.w	r3, r3, r3, lsl #1
 8000c4a:	fbb0 f0f3 	udiv	r0, r0, r3
 8000c4e:	1c43      	adds	r3, r0, #1
 8000c50:	f3c3 030b 	ubfx	r3, r3, #0, #12
 8000c54:	b16b      	cbz	r3, 8000c72 <HAL_I2C_Init+0xea>
 8000c56:	f443 4300 	orr.w	r3, r3, #32768	; 0x8000
 8000c5a:	e7c8      	b.n	8000bee <HAL_I2C_Init+0x66>
 8000c5c:	2219      	movs	r2, #25
 8000c5e:	4353      	muls	r3, r2
 8000c60:	fbb0 f0f3 	udiv	r0, r0, r3
 8000c64:	1c43      	adds	r3, r0, #1
 8000c66:	f3c3 030b 	ubfx	r3, r3, #0, #12
 8000c6a:	b113      	cbz	r3, 8000c72 <HAL_I2C_Init+0xea>
 8000c6c:	f443 4340 	orr.w	r3, r3, #49152	; 0xc000
 8000c70:	e7bd      	b.n	8000bee <HAL_I2C_Init+0x66>
 8000c72:	2301      	movs	r3, #1
 8000c74:	e7bb      	b.n	8000bee <HAL_I2C_Init+0x66>
 8000c76:	bf00      	nop
 8000c78:	000186a0 	.word	0x000186a0
 8000c7c:	001e847f 	.word	0x001e847f
 8000c80:	000f4240 	.word	0x000f4240
 8000c84:	003d08ff 	.word	0x003d08ff

08000c88 <HAL_RCC_OscConfig>:
  /* Check the parameters */
  assert_param(RCC_OscInitStruct != NULL);
  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
  
  /*------------------------------- HSE Configuration ------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
 8000c88:	6803      	ldr	r3, [r0, #0]
{
 8000c8a:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
 8000c8e:	07db      	lsls	r3, r3, #31
{
 8000c90:	4605      	mov	r5, r0
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
 8000c92:	d410      	bmi.n	8000cb6 <HAL_RCC_OscConfig+0x2e>
        }
      }
    }
  }
  /*----------------------------- HSI Configuration --------------------------*/ 
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
 8000c94:	682b      	ldr	r3, [r5, #0]
 8000c96:	079f      	lsls	r7, r3, #30
 8000c98:	d45e      	bmi.n	8000d58 <HAL_RCC_OscConfig+0xd0>
        }
      }
    }
  }
  /*------------------------------ LSI Configuration -------------------------*/ 
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
 8000c9a:	682b      	ldr	r3, [r5, #0]
 8000c9c:	0719      	lsls	r1, r3, #28
 8000c9e:	f100 8095 	bmi.w	8000dcc <HAL_RCC_OscConfig+0x144>
        }
      }
    }
  }
  /*------------------------------ LSE Configuration -------------------------*/ 
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
 8000ca2:	682b      	ldr	r3, [r5, #0]
 8000ca4:	075a      	lsls	r2, r3, #29
 8000ca6:	f100 80bf 	bmi.w	8000e28 <HAL_RCC_OscConfig+0x1a0>

#endif /* RCC_CR_PLL2ON */
  /*-------------------------------- PLL Configuration -----------------------*/
  /* Check the parameters */
  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
 8000caa:	69ea      	ldr	r2, [r5, #28]
 8000cac:	2a00      	cmp	r2, #0
 8000cae:	f040 812d 	bne.w	8000f0c <HAL_RCC_OscConfig+0x284>
    {
      return HAL_ERROR;
    }
  }
  
  return HAL_OK;
 8000cb2:	2000      	movs	r0, #0
 8000cb4:	e014      	b.n	8000ce0 <HAL_RCC_OscConfig+0x58>
    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 
 8000cb6:	4c90      	ldr	r4, [pc, #576]	; (8000ef8 <HAL_RCC_OscConfig+0x270>)
 8000cb8:	6863      	ldr	r3, [r4, #4]
 8000cba:	f003 030c 	and.w	r3, r3, #12
 8000cbe:	2b04      	cmp	r3, #4
 8000cc0:	d007      	beq.n	8000cd2 <HAL_RCC_OscConfig+0x4a>
       || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
 8000cc2:	6863      	ldr	r3, [r4, #4]
 8000cc4:	f003 030c 	and.w	r3, r3, #12
 8000cc8:	2b08      	cmp	r3, #8
 8000cca:	d10c      	bne.n	8000ce6 <HAL_RCC_OscConfig+0x5e>
 8000ccc:	6863      	ldr	r3, [r4, #4]
 8000cce:	03de      	lsls	r6, r3, #15
 8000cd0:	d509      	bpl.n	8000ce6 <HAL_RCC_OscConfig+0x5e>
      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
 8000cd2:	6823      	ldr	r3, [r4, #0]
 8000cd4:	039c      	lsls	r4, r3, #14
 8000cd6:	d5dd      	bpl.n	8000c94 <HAL_RCC_OscConfig+0xc>
 8000cd8:	686b      	ldr	r3, [r5, #4]
 8000cda:	2b00      	cmp	r3, #0
 8000cdc:	d1da      	bne.n	8000c94 <HAL_RCC_OscConfig+0xc>
        return HAL_ERROR;
 8000cde:	2001      	movs	r0, #1
}
 8000ce0:	b002      	add	sp, #8
 8000ce2:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 8000ce6:	686b      	ldr	r3, [r5, #4]
 8000ce8:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
 8000cec:	d110      	bne.n	8000d10 <HAL_RCC_OscConfig+0x88>
 8000cee:	6823      	ldr	r3, [r4, #0]
 8000cf0:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
 8000cf4:	6023      	str	r3, [r4, #0]
        tickstart = HAL_GetTick();
 8000cf6:	f7ff fae3 	bl	80002c0 <HAL_GetTick>
 8000cfa:	4606      	mov	r6, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 8000cfc:	6823      	ldr	r3, [r4, #0]
 8000cfe:	0398      	lsls	r0, r3, #14
 8000d00:	d4c8      	bmi.n	8000c94 <HAL_RCC_OscConfig+0xc>
          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
 8000d02:	f7ff fadd 	bl	80002c0 <HAL_GetTick>
 8000d06:	1b80      	subs	r0, r0, r6
 8000d08:	2864      	cmp	r0, #100	; 0x64
 8000d0a:	d9f7      	bls.n	8000cfc <HAL_RCC_OscConfig+0x74>
            return HAL_TIMEOUT;
 8000d0c:	2003      	movs	r0, #3
 8000d0e:	e7e7      	b.n	8000ce0 <HAL_RCC_OscConfig+0x58>
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 8000d10:	b99b      	cbnz	r3, 8000d3a <HAL_RCC_OscConfig+0xb2>
 8000d12:	6823      	ldr	r3, [r4, #0]
 8000d14:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
 8000d18:	6023      	str	r3, [r4, #0]
 8000d1a:	6823      	ldr	r3, [r4, #0]
 8000d1c:	f423 2380 	bic.w	r3, r3, #262144	; 0x40000
 8000d20:	6023      	str	r3, [r4, #0]
        tickstart = HAL_GetTick();
 8000d22:	f7ff facd 	bl	80002c0 <HAL_GetTick>
 8000d26:	4606      	mov	r6, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
 8000d28:	6823      	ldr	r3, [r4, #0]
 8000d2a:	0399      	lsls	r1, r3, #14
 8000d2c:	d5b2      	bpl.n	8000c94 <HAL_RCC_OscConfig+0xc>
           if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
 8000d2e:	f7ff fac7 	bl	80002c0 <HAL_GetTick>
 8000d32:	1b80      	subs	r0, r0, r6
 8000d34:	2864      	cmp	r0, #100	; 0x64
 8000d36:	d9f7      	bls.n	8000d28 <HAL_RCC_OscConfig+0xa0>
 8000d38:	e7e8      	b.n	8000d0c <HAL_RCC_OscConfig+0x84>
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 8000d3a:	f5b3 2fa0 	cmp.w	r3, #327680	; 0x50000
 8000d3e:	6823      	ldr	r3, [r4, #0]
 8000d40:	d103      	bne.n	8000d4a <HAL_RCC_OscConfig+0xc2>
 8000d42:	f443 2380 	orr.w	r3, r3, #262144	; 0x40000
 8000d46:	6023      	str	r3, [r4, #0]
 8000d48:	e7d1      	b.n	8000cee <HAL_RCC_OscConfig+0x66>
 8000d4a:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
 8000d4e:	6023      	str	r3, [r4, #0]
 8000d50:	6823      	ldr	r3, [r4, #0]
 8000d52:	f423 2380 	bic.w	r3, r3, #262144	; 0x40000
 8000d56:	e7cd      	b.n	8000cf4 <HAL_RCC_OscConfig+0x6c>
    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 
 8000d58:	4c67      	ldr	r4, [pc, #412]	; (8000ef8 <HAL_RCC_OscConfig+0x270>)
 8000d5a:	6863      	ldr	r3, [r4, #4]
 8000d5c:	f013 0f0c 	tst.w	r3, #12
 8000d60:	d007      	beq.n	8000d72 <HAL_RCC_OscConfig+0xea>
       || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
 8000d62:	6863      	ldr	r3, [r4, #4]
 8000d64:	f003 030c 	and.w	r3, r3, #12
 8000d68:	2b08      	cmp	r3, #8
 8000d6a:	d110      	bne.n	8000d8e <HAL_RCC_OscConfig+0x106>
 8000d6c:	6863      	ldr	r3, [r4, #4]
 8000d6e:	03da      	lsls	r2, r3, #15
 8000d70:	d40d      	bmi.n	8000d8e <HAL_RCC_OscConfig+0x106>
      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
 8000d72:	6823      	ldr	r3, [r4, #0]
 8000d74:	079b      	lsls	r3, r3, #30
 8000d76:	d502      	bpl.n	8000d7e <HAL_RCC_OscConfig+0xf6>
 8000d78:	692b      	ldr	r3, [r5, #16]
 8000d7a:	2b01      	cmp	r3, #1
 8000d7c:	d1af      	bne.n	8000cde <HAL_RCC_OscConfig+0x56>
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 8000d7e:	6823      	ldr	r3, [r4, #0]
 8000d80:	696a      	ldr	r2, [r5, #20]
 8000d82:	f023 03f8 	bic.w	r3, r3, #248	; 0xf8
 8000d86:	ea43 03c2 	orr.w	r3, r3, r2, lsl #3
 8000d8a:	6023      	str	r3, [r4, #0]
 8000d8c:	e785      	b.n	8000c9a <HAL_RCC_OscConfig+0x12>
      if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
 8000d8e:	692a      	ldr	r2, [r5, #16]
 8000d90:	4b5a      	ldr	r3, [pc, #360]	; (8000efc <HAL_RCC_OscConfig+0x274>)
 8000d92:	b16a      	cbz	r2, 8000db0 <HAL_RCC_OscConfig+0x128>
        __HAL_RCC_HSI_ENABLE();
 8000d94:	2201      	movs	r2, #1
 8000d96:	601a      	str	r2, [r3, #0]
        tickstart = HAL_GetTick();
 8000d98:	f7ff fa92 	bl	80002c0 <HAL_GetTick>
 8000d9c:	4606      	mov	r6, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 8000d9e:	6823      	ldr	r3, [r4, #0]
 8000da0:	079f      	lsls	r7, r3, #30
 8000da2:	d4ec      	bmi.n	8000d7e <HAL_RCC_OscConfig+0xf6>
          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
 8000da4:	f7ff fa8c 	bl	80002c0 <HAL_GetTick>
 8000da8:	1b80      	subs	r0, r0, r6
 8000daa:	2802      	cmp	r0, #2
 8000dac:	d9f7      	bls.n	8000d9e <HAL_RCC_OscConfig+0x116>
 8000dae:	e7ad      	b.n	8000d0c <HAL_RCC_OscConfig+0x84>
        __HAL_RCC_HSI_DISABLE();
 8000db0:	601a      	str	r2, [r3, #0]
        tickstart = HAL_GetTick();
 8000db2:	f7ff fa85 	bl	80002c0 <HAL_GetTick>
 8000db6:	4606      	mov	r6, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
 8000db8:	6823      	ldr	r3, [r4, #0]
 8000dba:	0798      	lsls	r0, r3, #30
 8000dbc:	f57f af6d 	bpl.w	8000c9a <HAL_RCC_OscConfig+0x12>
          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
 8000dc0:	f7ff fa7e 	bl	80002c0 <HAL_GetTick>
 8000dc4:	1b80      	subs	r0, r0, r6
 8000dc6:	2802      	cmp	r0, #2
 8000dc8:	d9f6      	bls.n	8000db8 <HAL_RCC_OscConfig+0x130>
 8000dca:	e79f      	b.n	8000d0c <HAL_RCC_OscConfig+0x84>
    if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
 8000dcc:	69aa      	ldr	r2, [r5, #24]
 8000dce:	4c4a      	ldr	r4, [pc, #296]	; (8000ef8 <HAL_RCC_OscConfig+0x270>)
 8000dd0:	4b4b      	ldr	r3, [pc, #300]	; (8000f00 <HAL_RCC_OscConfig+0x278>)
 8000dd2:	b1da      	cbz	r2, 8000e0c <HAL_RCC_OscConfig+0x184>
      __HAL_RCC_LSI_ENABLE();
 8000dd4:	2201      	movs	r2, #1
 8000dd6:	601a      	str	r2, [r3, #0]
      tickstart = HAL_GetTick();
 8000dd8:	f7ff fa72 	bl	80002c0 <HAL_GetTick>
 8000ddc:	4606      	mov	r6, r0
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
 8000dde:	6a63      	ldr	r3, [r4, #36]	; 0x24
 8000de0:	079b      	lsls	r3, r3, #30
 8000de2:	d50d      	bpl.n	8000e00 <HAL_RCC_OscConfig+0x178>
  * @param  mdelay: specifies the delay time length, in milliseconds.
  * @retval None
  */
static void RCC_Delay(uint32_t mdelay)
{
  __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
 8000de4:	f44f 52fa 	mov.w	r2, #8000	; 0x1f40
 8000de8:	4b46      	ldr	r3, [pc, #280]	; (8000f04 <HAL_RCC_OscConfig+0x27c>)
 8000dea:	681b      	ldr	r3, [r3, #0]
 8000dec:	fbb3 f3f2 	udiv	r3, r3, r2
 8000df0:	9301      	str	r3, [sp, #4]
  \brief   No Operation
  \details No Operation does nothing. This instruction can be used for code alignment purposes.
 */
__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
{
  __ASM volatile ("nop");
 8000df2:	bf00      	nop
  do 
  {
    __NOP();
  } 
  while (Delay --);
 8000df4:	9b01      	ldr	r3, [sp, #4]
 8000df6:	1e5a      	subs	r2, r3, #1
 8000df8:	9201      	str	r2, [sp, #4]
 8000dfa:	2b00      	cmp	r3, #0
 8000dfc:	d1f9      	bne.n	8000df2 <HAL_RCC_OscConfig+0x16a>
 8000dfe:	e750      	b.n	8000ca2 <HAL_RCC_OscConfig+0x1a>
        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
 8000e00:	f7ff fa5e 	bl	80002c0 <HAL_GetTick>
 8000e04:	1b80      	subs	r0, r0, r6
 8000e06:	2802      	cmp	r0, #2
 8000e08:	d9e9      	bls.n	8000dde <HAL_RCC_OscConfig+0x156>
 8000e0a:	e77f      	b.n	8000d0c <HAL_RCC_OscConfig+0x84>
      __HAL_RCC_LSI_DISABLE();
 8000e0c:	601a      	str	r2, [r3, #0]
      tickstart = HAL_GetTick();
 8000e0e:	f7ff fa57 	bl	80002c0 <HAL_GetTick>
 8000e12:	4606      	mov	r6, r0
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
 8000e14:	6a63      	ldr	r3, [r4, #36]	; 0x24
 8000e16:	079f      	lsls	r7, r3, #30
 8000e18:	f57f af43 	bpl.w	8000ca2 <HAL_RCC_OscConfig+0x1a>
        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
 8000e1c:	f7ff fa50 	bl	80002c0 <HAL_GetTick>
 8000e20:	1b80      	subs	r0, r0, r6
 8000e22:	2802      	cmp	r0, #2
 8000e24:	d9f6      	bls.n	8000e14 <HAL_RCC_OscConfig+0x18c>
 8000e26:	e771      	b.n	8000d0c <HAL_RCC_OscConfig+0x84>
    if(__HAL_RCC_PWR_IS_CLK_DISABLED())
 8000e28:	4c33      	ldr	r4, [pc, #204]	; (8000ef8 <HAL_RCC_OscConfig+0x270>)
 8000e2a:	69e3      	ldr	r3, [r4, #28]
 8000e2c:	00d8      	lsls	r0, r3, #3
 8000e2e:	d424      	bmi.n	8000e7a <HAL_RCC_OscConfig+0x1f2>
      pwrclkchanged = SET;
 8000e30:	2701      	movs	r7, #1
      __HAL_RCC_PWR_CLK_ENABLE();
 8000e32:	69e3      	ldr	r3, [r4, #28]
 8000e34:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
 8000e38:	61e3      	str	r3, [r4, #28]
 8000e3a:	69e3      	ldr	r3, [r4, #28]
 8000e3c:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8000e40:	9300      	str	r3, [sp, #0]
 8000e42:	9b00      	ldr	r3, [sp, #0]
    if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 8000e44:	4e30      	ldr	r6, [pc, #192]	; (8000f08 <HAL_RCC_OscConfig+0x280>)
 8000e46:	6833      	ldr	r3, [r6, #0]
 8000e48:	05d9      	lsls	r1, r3, #23
 8000e4a:	d518      	bpl.n	8000e7e <HAL_RCC_OscConfig+0x1f6>
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 8000e4c:	68eb      	ldr	r3, [r5, #12]
 8000e4e:	2b01      	cmp	r3, #1
 8000e50:	d126      	bne.n	8000ea0 <HAL_RCC_OscConfig+0x218>
 8000e52:	6a23      	ldr	r3, [r4, #32]
 8000e54:	f043 0301 	orr.w	r3, r3, #1
 8000e58:	6223      	str	r3, [r4, #32]
      tickstart = HAL_GetTick();
 8000e5a:	f7ff fa31 	bl	80002c0 <HAL_GetTick>
        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
 8000e5e:	f241 3688 	movw	r6, #5000	; 0x1388
      tickstart = HAL_GetTick();
 8000e62:	4680      	mov	r8, r0
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
 8000e64:	6a23      	ldr	r3, [r4, #32]
 8000e66:	079b      	lsls	r3, r3, #30
 8000e68:	d53f      	bpl.n	8000eea <HAL_RCC_OscConfig+0x262>
    if(pwrclkchanged == SET)
 8000e6a:	2f00      	cmp	r7, #0
 8000e6c:	f43f af1d 	beq.w	8000caa <HAL_RCC_OscConfig+0x22>
      __HAL_RCC_PWR_CLK_DISABLE();
 8000e70:	69e3      	ldr	r3, [r4, #28]
 8000e72:	f023 5380 	bic.w	r3, r3, #268435456	; 0x10000000
 8000e76:	61e3      	str	r3, [r4, #28]
 8000e78:	e717      	b.n	8000caa <HAL_RCC_OscConfig+0x22>
    FlagStatus       pwrclkchanged = RESET;
 8000e7a:	2700      	movs	r7, #0
 8000e7c:	e7e2      	b.n	8000e44 <HAL_RCC_OscConfig+0x1bc>
      SET_BIT(PWR->CR, PWR_CR_DBP);
 8000e7e:	6833      	ldr	r3, [r6, #0]
 8000e80:	f443 7380 	orr.w	r3, r3, #256	; 0x100
 8000e84:	6033      	str	r3, [r6, #0]
      tickstart = HAL_GetTick();
 8000e86:	f7ff fa1b 	bl	80002c0 <HAL_GetTick>
 8000e8a:	4680      	mov	r8, r0
      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 8000e8c:	6833      	ldr	r3, [r6, #0]
 8000e8e:	05da      	lsls	r2, r3, #23
 8000e90:	d4dc      	bmi.n	8000e4c <HAL_RCC_OscConfig+0x1c4>
        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
 8000e92:	f7ff fa15 	bl	80002c0 <HAL_GetTick>
 8000e96:	eba0 0008 	sub.w	r0, r0, r8
 8000e9a:	2864      	cmp	r0, #100	; 0x64
 8000e9c:	d9f6      	bls.n	8000e8c <HAL_RCC_OscConfig+0x204>
 8000e9e:	e735      	b.n	8000d0c <HAL_RCC_OscConfig+0x84>
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 8000ea0:	b9ab      	cbnz	r3, 8000ece <HAL_RCC_OscConfig+0x246>
 8000ea2:	6a23      	ldr	r3, [r4, #32]
        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
 8000ea4:	f241 3888 	movw	r8, #5000	; 0x1388
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 8000ea8:	f023 0301 	bic.w	r3, r3, #1
 8000eac:	6223      	str	r3, [r4, #32]
 8000eae:	6a23      	ldr	r3, [r4, #32]
 8000eb0:	f023 0304 	bic.w	r3, r3, #4
 8000eb4:	6223      	str	r3, [r4, #32]
      tickstart = HAL_GetTick();
 8000eb6:	f7ff fa03 	bl	80002c0 <HAL_GetTick>
 8000eba:	4606      	mov	r6, r0
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
 8000ebc:	6a23      	ldr	r3, [r4, #32]
 8000ebe:	0798      	lsls	r0, r3, #30
 8000ec0:	d5d3      	bpl.n	8000e6a <HAL_RCC_OscConfig+0x1e2>
        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
 8000ec2:	f7ff f9fd 	bl	80002c0 <HAL_GetTick>
 8000ec6:	1b80      	subs	r0, r0, r6
 8000ec8:	4540      	cmp	r0, r8
 8000eca:	d9f7      	bls.n	8000ebc <HAL_RCC_OscConfig+0x234>
 8000ecc:	e71e      	b.n	8000d0c <HAL_RCC_OscConfig+0x84>
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 8000ece:	2b05      	cmp	r3, #5
 8000ed0:	6a23      	ldr	r3, [r4, #32]
 8000ed2:	d103      	bne.n	8000edc <HAL_RCC_OscConfig+0x254>
 8000ed4:	f043 0304 	orr.w	r3, r3, #4
 8000ed8:	6223      	str	r3, [r4, #32]
 8000eda:	e7ba      	b.n	8000e52 <HAL_RCC_OscConfig+0x1ca>
 8000edc:	f023 0301 	bic.w	r3, r3, #1
 8000ee0:	6223      	str	r3, [r4, #32]
 8000ee2:	6a23      	ldr	r3, [r4, #32]
 8000ee4:	f023 0304 	bic.w	r3, r3, #4
 8000ee8:	e7b6      	b.n	8000e58 <HAL_RCC_OscConfig+0x1d0>
        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
 8000eea:	f7ff f9e9 	bl	80002c0 <HAL_GetTick>
 8000eee:	eba0 0008 	sub.w	r0, r0, r8
 8000ef2:	42b0      	cmp	r0, r6
 8000ef4:	d9b6      	bls.n	8000e64 <HAL_RCC_OscConfig+0x1dc>
 8000ef6:	e709      	b.n	8000d0c <HAL_RCC_OscConfig+0x84>
 8000ef8:	40021000 	.word	0x40021000
 8000efc:	42420000 	.word	0x42420000
 8000f00:	42420480 	.word	0x42420480
 8000f04:	20000218 	.word	0x20000218
 8000f08:	40007000 	.word	0x40007000
    if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
 8000f0c:	4c22      	ldr	r4, [pc, #136]	; (8000f98 <HAL_RCC_OscConfig+0x310>)
 8000f0e:	6863      	ldr	r3, [r4, #4]
 8000f10:	f003 030c 	and.w	r3, r3, #12
 8000f14:	2b08      	cmp	r3, #8
 8000f16:	f43f aee2 	beq.w	8000cde <HAL_RCC_OscConfig+0x56>
 8000f1a:	2300      	movs	r3, #0
 8000f1c:	4e1f      	ldr	r6, [pc, #124]	; (8000f9c <HAL_RCC_OscConfig+0x314>)
      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
 8000f1e:	2a02      	cmp	r2, #2
        __HAL_RCC_PLL_DISABLE();
 8000f20:	6033      	str	r3, [r6, #0]
      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
 8000f22:	d12b      	bne.n	8000f7c <HAL_RCC_OscConfig+0x2f4>
        tickstart = HAL_GetTick();
 8000f24:	f7ff f9cc 	bl	80002c0 <HAL_GetTick>
 8000f28:	4607      	mov	r7, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
 8000f2a:	6823      	ldr	r3, [r4, #0]
 8000f2c:	0199      	lsls	r1, r3, #6
 8000f2e:	d41f      	bmi.n	8000f70 <HAL_RCC_OscConfig+0x2e8>
        if(RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
 8000f30:	6a2b      	ldr	r3, [r5, #32]
 8000f32:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
 8000f36:	d105      	bne.n	8000f44 <HAL_RCC_OscConfig+0x2bc>
          __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
 8000f38:	6862      	ldr	r2, [r4, #4]
 8000f3a:	68a9      	ldr	r1, [r5, #8]
 8000f3c:	f422 3200 	bic.w	r2, r2, #131072	; 0x20000
 8000f40:	430a      	orrs	r2, r1
 8000f42:	6062      	str	r2, [r4, #4]
        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
 8000f44:	6a69      	ldr	r1, [r5, #36]	; 0x24
 8000f46:	6862      	ldr	r2, [r4, #4]
 8000f48:	430b      	orrs	r3, r1
 8000f4a:	f422 1274 	bic.w	r2, r2, #3997696	; 0x3d0000
 8000f4e:	4313      	orrs	r3, r2
 8000f50:	6063      	str	r3, [r4, #4]
        __HAL_RCC_PLL_ENABLE();
 8000f52:	2301      	movs	r3, #1
 8000f54:	6033      	str	r3, [r6, #0]
        tickstart = HAL_GetTick();
 8000f56:	f7ff f9b3 	bl	80002c0 <HAL_GetTick>
 8000f5a:	4605      	mov	r5, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  == RESET)
 8000f5c:	6823      	ldr	r3, [r4, #0]
 8000f5e:	019a      	lsls	r2, r3, #6
 8000f60:	f53f aea7 	bmi.w	8000cb2 <HAL_RCC_OscConfig+0x2a>
          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
 8000f64:	f7ff f9ac 	bl	80002c0 <HAL_GetTick>
 8000f68:	1b40      	subs	r0, r0, r5
 8000f6a:	2802      	cmp	r0, #2
 8000f6c:	d9f6      	bls.n	8000f5c <HAL_RCC_OscConfig+0x2d4>
 8000f6e:	e6cd      	b.n	8000d0c <HAL_RCC_OscConfig+0x84>
          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
 8000f70:	f7ff f9a6 	bl	80002c0 <HAL_GetTick>
 8000f74:	1bc0      	subs	r0, r0, r7
 8000f76:	2802      	cmp	r0, #2
 8000f78:	d9d7      	bls.n	8000f2a <HAL_RCC_OscConfig+0x2a2>
 8000f7a:	e6c7      	b.n	8000d0c <HAL_RCC_OscConfig+0x84>
        tickstart = HAL_GetTick();
 8000f7c:	f7ff f9a0 	bl	80002c0 <HAL_GetTick>
 8000f80:	4605      	mov	r5, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
 8000f82:	6823      	ldr	r3, [r4, #0]
 8000f84:	019b      	lsls	r3, r3, #6
 8000f86:	f57f ae94 	bpl.w	8000cb2 <HAL_RCC_OscConfig+0x2a>
          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
 8000f8a:	f7ff f999 	bl	80002c0 <HAL_GetTick>
 8000f8e:	1b40      	subs	r0, r0, r5
 8000f90:	2802      	cmp	r0, #2
 8000f92:	d9f6      	bls.n	8000f82 <HAL_RCC_OscConfig+0x2fa>
 8000f94:	e6ba      	b.n	8000d0c <HAL_RCC_OscConfig+0x84>
 8000f96:	bf00      	nop
 8000f98:	40021000 	.word	0x40021000
 8000f9c:	42420060 	.word	0x42420060

08000fa0 <HAL_RCC_GetSysClockFreq>:
{
 8000fa0:	b530      	push	{r4, r5, lr}
  const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
 8000fa2:	4b19      	ldr	r3, [pc, #100]	; (8001008 <HAL_RCC_GetSysClockFreq+0x68>)
{
 8000fa4:	b087      	sub	sp, #28
  const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
 8000fa6:	ac02      	add	r4, sp, #8
 8000fa8:	f103 0510 	add.w	r5, r3, #16
 8000fac:	4622      	mov	r2, r4
 8000fae:	6818      	ldr	r0, [r3, #0]
 8000fb0:	6859      	ldr	r1, [r3, #4]
 8000fb2:	3308      	adds	r3, #8
 8000fb4:	c203      	stmia	r2!, {r0, r1}
 8000fb6:	42ab      	cmp	r3, r5
 8000fb8:	4614      	mov	r4, r2
 8000fba:	d1f7      	bne.n	8000fac <HAL_RCC_GetSysClockFreq+0xc>
  const uint8_t aPredivFactorTable[2] = {1, 2};
 8000fbc:	2301      	movs	r3, #1
 8000fbe:	f88d 3004 	strb.w	r3, [sp, #4]
 8000fc2:	2302      	movs	r3, #2
  tmpreg = RCC->CFGR;
 8000fc4:	4911      	ldr	r1, [pc, #68]	; (800100c <HAL_RCC_GetSysClockFreq+0x6c>)
  const uint8_t aPredivFactorTable[2] = {1, 2};
 8000fc6:	f88d 3005 	strb.w	r3, [sp, #5]
  tmpreg = RCC->CFGR;
 8000fca:	684b      	ldr	r3, [r1, #4]
  switch (tmpreg & RCC_CFGR_SWS)
 8000fcc:	f003 020c 	and.w	r2, r3, #12
 8000fd0:	2a08      	cmp	r2, #8
 8000fd2:	d117      	bne.n	8001004 <HAL_RCC_GetSysClockFreq+0x64>
      pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
 8000fd4:	f3c3 4283 	ubfx	r2, r3, #18, #4
 8000fd8:	a806      	add	r0, sp, #24
 8000fda:	4402      	add	r2, r0
      if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
 8000fdc:	03db      	lsls	r3, r3, #15
      pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
 8000fde:	f812 2c10 	ldrb.w	r2, [r2, #-16]
      if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
 8000fe2:	d50c      	bpl.n	8000ffe <HAL_RCC_GetSysClockFreq+0x5e>
        prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
 8000fe4:	684b      	ldr	r3, [r1, #4]
        pllclk = (uint32_t)((HSE_VALUE  * pllmul) / prediv);
 8000fe6:	480a      	ldr	r0, [pc, #40]	; (8001010 <HAL_RCC_GetSysClockFreq+0x70>)
        prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
 8000fe8:	f3c3 4340 	ubfx	r3, r3, #17, #1
        pllclk = (uint32_t)((HSE_VALUE  * pllmul) / prediv);
 8000fec:	4350      	muls	r0, r2
        prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
 8000fee:	aa06      	add	r2, sp, #24
 8000ff0:	4413      	add	r3, r2
 8000ff2:	f813 3c14 	ldrb.w	r3, [r3, #-20]
        pllclk = (uint32_t)((HSE_VALUE  * pllmul) / prediv);
 8000ff6:	fbb0 f0f3 	udiv	r0, r0, r3
}
 8000ffa:	b007      	add	sp, #28
 8000ffc:	bd30      	pop	{r4, r5, pc}
        pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
 8000ffe:	4805      	ldr	r0, [pc, #20]	; (8001014 <HAL_RCC_GetSysClockFreq+0x74>)
 8001000:	4350      	muls	r0, r2
 8001002:	e7fa      	b.n	8000ffa <HAL_RCC_GetSysClockFreq+0x5a>
      sysclockfreq = HSE_VALUE;
 8001004:	4802      	ldr	r0, [pc, #8]	; (8001010 <HAL_RCC_GetSysClockFreq+0x70>)
  return sysclockfreq;
 8001006:	e7f8      	b.n	8000ffa <HAL_RCC_GetSysClockFreq+0x5a>
 8001008:	080036ec 	.word	0x080036ec
 800100c:	40021000 	.word	0x40021000
 8001010:	007a1200 	.word	0x007a1200
 8001014:	003d0900 	.word	0x003d0900

08001018 <HAL_RCC_ClockConfig>:
  if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
 8001018:	4a54      	ldr	r2, [pc, #336]	; (800116c <HAL_RCC_ClockConfig+0x154>)
{
 800101a:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
  if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
 800101e:	6813      	ldr	r3, [r2, #0]
{
 8001020:	4605      	mov	r5, r0
  if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
 8001022:	f003 0307 	and.w	r3, r3, #7
 8001026:	428b      	cmp	r3, r1
{
 8001028:	460e      	mov	r6, r1
  if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
 800102a:	d32a      	bcc.n	8001082 <HAL_RCC_ClockConfig+0x6a>
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
 800102c:	6829      	ldr	r1, [r5, #0]
 800102e:	078c      	lsls	r4, r1, #30
 8001030:	d434      	bmi.n	800109c <HAL_RCC_ClockConfig+0x84>
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
 8001032:	07ca      	lsls	r2, r1, #31
 8001034:	d447      	bmi.n	80010c6 <HAL_RCC_ClockConfig+0xae>
  if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
 8001036:	4a4d      	ldr	r2, [pc, #308]	; (800116c <HAL_RCC_ClockConfig+0x154>)
 8001038:	6813      	ldr	r3, [r2, #0]
 800103a:	f003 0307 	and.w	r3, r3, #7
 800103e:	429e      	cmp	r6, r3
 8001040:	f0c0 8082 	bcc.w	8001148 <HAL_RCC_ClockConfig+0x130>
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 8001044:	682a      	ldr	r2, [r5, #0]
 8001046:	4c4a      	ldr	r4, [pc, #296]	; (8001170 <HAL_RCC_ClockConfig+0x158>)
 8001048:	f012 0f04 	tst.w	r2, #4
 800104c:	f040 8087 	bne.w	800115e <HAL_RCC_ClockConfig+0x146>
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
 8001050:	0713      	lsls	r3, r2, #28
 8001052:	d506      	bpl.n	8001062 <HAL_RCC_ClockConfig+0x4a>
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
 8001054:	6863      	ldr	r3, [r4, #4]
 8001056:	692a      	ldr	r2, [r5, #16]
 8001058:	f423 5360 	bic.w	r3, r3, #14336	; 0x3800
 800105c:	ea43 03c2 	orr.w	r3, r3, r2, lsl #3
 8001060:	6063      	str	r3, [r4, #4]
  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
 8001062:	f7ff ff9d 	bl	8000fa0 <HAL_RCC_GetSysClockFreq>
 8001066:	6863      	ldr	r3, [r4, #4]
 8001068:	4a42      	ldr	r2, [pc, #264]	; (8001174 <HAL_RCC_ClockConfig+0x15c>)
 800106a:	f3c3 1303 	ubfx	r3, r3, #4, #4
 800106e:	5cd3      	ldrb	r3, [r2, r3]
 8001070:	40d8      	lsrs	r0, r3
 8001072:	4b41      	ldr	r3, [pc, #260]	; (8001178 <HAL_RCC_ClockConfig+0x160>)
 8001074:	6018      	str	r0, [r3, #0]
  HAL_InitTick (TICK_INT_PRIORITY);
 8001076:	2000      	movs	r0, #0
 8001078:	f7ff f8e0 	bl	800023c <HAL_InitTick>
  return HAL_OK;
 800107c:	2000      	movs	r0, #0
}
 800107e:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    __HAL_FLASH_SET_LATENCY(FLatency);
 8001082:	6813      	ldr	r3, [r2, #0]
 8001084:	f023 0307 	bic.w	r3, r3, #7
 8001088:	430b      	orrs	r3, r1
 800108a:	6013      	str	r3, [r2, #0]
    if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
 800108c:	6813      	ldr	r3, [r2, #0]
 800108e:	f003 0307 	and.w	r3, r3, #7
 8001092:	4299      	cmp	r1, r3
 8001094:	d0ca      	beq.n	800102c <HAL_RCC_ClockConfig+0x14>
      return HAL_ERROR;
 8001096:	2001      	movs	r0, #1
 8001098:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
 800109c:	4b34      	ldr	r3, [pc, #208]	; (8001170 <HAL_RCC_ClockConfig+0x158>)
    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 800109e:	f011 0f04 	tst.w	r1, #4
      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
 80010a2:	bf1e      	ittt	ne
 80010a4:	685a      	ldrne	r2, [r3, #4]
 80010a6:	f442 62e0 	orrne.w	r2, r2, #1792	; 0x700
 80010aa:	605a      	strne	r2, [r3, #4]
    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
 80010ac:	0708      	lsls	r0, r1, #28
      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
 80010ae:	bf42      	ittt	mi
 80010b0:	685a      	ldrmi	r2, [r3, #4]
 80010b2:	f442 5260 	orrmi.w	r2, r2, #14336	; 0x3800
 80010b6:	605a      	strmi	r2, [r3, #4]
    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
 80010b8:	685a      	ldr	r2, [r3, #4]
 80010ba:	68a8      	ldr	r0, [r5, #8]
 80010bc:	f022 02f0 	bic.w	r2, r2, #240	; 0xf0
 80010c0:	4302      	orrs	r2, r0
 80010c2:	605a      	str	r2, [r3, #4]
 80010c4:	e7b5      	b.n	8001032 <HAL_RCC_ClockConfig+0x1a>
    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 80010c6:	686a      	ldr	r2, [r5, #4]
 80010c8:	4c29      	ldr	r4, [pc, #164]	; (8001170 <HAL_RCC_ClockConfig+0x158>)
 80010ca:	2a01      	cmp	r2, #1
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 80010cc:	6823      	ldr	r3, [r4, #0]
    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 80010ce:	d11c      	bne.n	800110a <HAL_RCC_ClockConfig+0xf2>
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 80010d0:	f413 3f00 	tst.w	r3, #131072	; 0x20000
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 80010d4:	d0df      	beq.n	8001096 <HAL_RCC_ClockConfig+0x7e>
    __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
 80010d6:	6863      	ldr	r3, [r4, #4]
        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
 80010d8:	f241 3888 	movw	r8, #5000	; 0x1388
    __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
 80010dc:	f023 0303 	bic.w	r3, r3, #3
 80010e0:	4313      	orrs	r3, r2
 80010e2:	6063      	str	r3, [r4, #4]
    tickstart = HAL_GetTick();
 80010e4:	f7ff f8ec 	bl	80002c0 <HAL_GetTick>
    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 80010e8:	686b      	ldr	r3, [r5, #4]
    tickstart = HAL_GetTick();
 80010ea:	4607      	mov	r7, r0
    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 80010ec:	2b01      	cmp	r3, #1
 80010ee:	d114      	bne.n	800111a <HAL_RCC_ClockConfig+0x102>
      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
 80010f0:	6863      	ldr	r3, [r4, #4]
 80010f2:	f003 030c 	and.w	r3, r3, #12
 80010f6:	2b04      	cmp	r3, #4
 80010f8:	d09d      	beq.n	8001036 <HAL_RCC_ClockConfig+0x1e>
        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
 80010fa:	f7ff f8e1 	bl	80002c0 <HAL_GetTick>
 80010fe:	1bc0      	subs	r0, r0, r7
 8001100:	4540      	cmp	r0, r8
 8001102:	d9f5      	bls.n	80010f0 <HAL_RCC_ClockConfig+0xd8>
          return HAL_TIMEOUT;
 8001104:	2003      	movs	r0, #3
 8001106:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
 800110a:	2a02      	cmp	r2, #2
 800110c:	d102      	bne.n	8001114 <HAL_RCC_ClockConfig+0xfc>
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
 800110e:	f013 7f00 	tst.w	r3, #33554432	; 0x2000000
 8001112:	e7df      	b.n	80010d4 <HAL_RCC_ClockConfig+0xbc>
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 8001114:	f013 0f02 	tst.w	r3, #2
 8001118:	e7dc      	b.n	80010d4 <HAL_RCC_ClockConfig+0xbc>
    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
 800111a:	2b02      	cmp	r3, #2
 800111c:	d10f      	bne.n	800113e <HAL_RCC_ClockConfig+0x126>
      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
 800111e:	6863      	ldr	r3, [r4, #4]
 8001120:	f003 030c 	and.w	r3, r3, #12
 8001124:	2b08      	cmp	r3, #8
 8001126:	d086      	beq.n	8001036 <HAL_RCC_ClockConfig+0x1e>
        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
 8001128:	f7ff f8ca 	bl	80002c0 <HAL_GetTick>
 800112c:	1bc0      	subs	r0, r0, r7
 800112e:	4540      	cmp	r0, r8
 8001130:	d9f5      	bls.n	800111e <HAL_RCC_ClockConfig+0x106>
 8001132:	e7e7      	b.n	8001104 <HAL_RCC_ClockConfig+0xec>
        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
 8001134:	f7ff f8c4 	bl	80002c0 <HAL_GetTick>
 8001138:	1bc0      	subs	r0, r0, r7
 800113a:	4540      	cmp	r0, r8
 800113c:	d8e2      	bhi.n	8001104 <HAL_RCC_ClockConfig+0xec>
      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
 800113e:	6863      	ldr	r3, [r4, #4]
 8001140:	f013 0f0c 	tst.w	r3, #12
 8001144:	d1f6      	bne.n	8001134 <HAL_RCC_ClockConfig+0x11c>
 8001146:	e776      	b.n	8001036 <HAL_RCC_ClockConfig+0x1e>
    __HAL_FLASH_SET_LATENCY(FLatency);
 8001148:	6813      	ldr	r3, [r2, #0]
 800114a:	f023 0307 	bic.w	r3, r3, #7
 800114e:	4333      	orrs	r3, r6
 8001150:	6013      	str	r3, [r2, #0]
    if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
 8001152:	6813      	ldr	r3, [r2, #0]
 8001154:	f003 0307 	and.w	r3, r3, #7
 8001158:	429e      	cmp	r6, r3
 800115a:	d19c      	bne.n	8001096 <HAL_RCC_ClockConfig+0x7e>
 800115c:	e772      	b.n	8001044 <HAL_RCC_ClockConfig+0x2c>
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
 800115e:	6863      	ldr	r3, [r4, #4]
 8001160:	68e9      	ldr	r1, [r5, #12]
 8001162:	f423 63e0 	bic.w	r3, r3, #1792	; 0x700
 8001166:	430b      	orrs	r3, r1
 8001168:	6063      	str	r3, [r4, #4]
 800116a:	e771      	b.n	8001050 <HAL_RCC_ClockConfig+0x38>
 800116c:	40022000 	.word	0x40022000
 8001170:	40021000 	.word	0x40021000
 8001174:	0800374d 	.word	0x0800374d
 8001178:	20000218 	.word	0x20000218

0800117c <HAL_RCC_GetPCLK1Freq>:
  return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
 800117c:	4b04      	ldr	r3, [pc, #16]	; (8001190 <HAL_RCC_GetPCLK1Freq+0x14>)
 800117e:	4a05      	ldr	r2, [pc, #20]	; (8001194 <HAL_RCC_GetPCLK1Freq+0x18>)
 8001180:	685b      	ldr	r3, [r3, #4]
 8001182:	f3c3 2302 	ubfx	r3, r3, #8, #3
 8001186:	5cd3      	ldrb	r3, [r2, r3]
 8001188:	4a03      	ldr	r2, [pc, #12]	; (8001198 <HAL_RCC_GetPCLK1Freq+0x1c>)
 800118a:	6810      	ldr	r0, [r2, #0]
}    
 800118c:	40d8      	lsrs	r0, r3
 800118e:	4770      	bx	lr
 8001190:	40021000 	.word	0x40021000
 8001194:	0800375d 	.word	0x0800375d
 8001198:	20000218 	.word	0x20000218

0800119c <HAL_RCC_GetPCLK2Freq>:
  return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
 800119c:	4b04      	ldr	r3, [pc, #16]	; (80011b0 <HAL_RCC_GetPCLK2Freq+0x14>)
 800119e:	4a05      	ldr	r2, [pc, #20]	; (80011b4 <HAL_RCC_GetPCLK2Freq+0x18>)
 80011a0:	685b      	ldr	r3, [r3, #4]
 80011a2:	f3c3 23c2 	ubfx	r3, r3, #11, #3
 80011a6:	5cd3      	ldrb	r3, [r2, r3]
 80011a8:	4a03      	ldr	r2, [pc, #12]	; (80011b8 <HAL_RCC_GetPCLK2Freq+0x1c>)
 80011aa:	6810      	ldr	r0, [r2, #0]
} 
 80011ac:	40d8      	lsrs	r0, r3
 80011ae:	4770      	bx	lr
 80011b0:	40021000 	.word	0x40021000
 80011b4:	0800375d 	.word	0x0800375d
 80011b8:	20000218 	.word	0x20000218

080011bc <HAL_TIM_Base_Start_IT>:
{
  /* Check the parameters */
  assert_param(IS_TIM_INSTANCE(htim->Instance));

   /* Enable the TIM Update interrupt */
   __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
 80011bc:	6803      	ldr	r3, [r0, #0]
   /* Enable the Peripheral */
  __HAL_TIM_ENABLE(htim);

  /* Return function status */
  return HAL_OK;
}
 80011be:	2000      	movs	r0, #0
   __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
 80011c0:	68da      	ldr	r2, [r3, #12]
 80011c2:	f042 0201 	orr.w	r2, r2, #1
 80011c6:	60da      	str	r2, [r3, #12]
  __HAL_TIM_ENABLE(htim);
 80011c8:	681a      	ldr	r2, [r3, #0]
 80011ca:	f042 0201 	orr.w	r2, r2, #1
 80011ce:	601a      	str	r2, [r3, #0]
}
 80011d0:	4770      	bx	lr

080011d2 <HAL_TIM_OC_DelayElapsedCallback>:
 80011d2:	4770      	bx	lr

080011d4 <HAL_TIM_IC_CaptureCallback>:
 80011d4:	4770      	bx	lr

080011d6 <HAL_TIM_PWM_PulseFinishedCallback>:
 80011d6:	4770      	bx	lr

080011d8 <HAL_TIM_TriggerCallback>:
 80011d8:	4770      	bx	lr

080011da <HAL_TIM_IRQHandler>:
  * @retval None
  */
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
  /* Capture compare 1 event */
  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
 80011da:	6803      	ldr	r3, [r0, #0]
{
 80011dc:	b510      	push	{r4, lr}
  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
 80011de:	691a      	ldr	r2, [r3, #16]
{
 80011e0:	4604      	mov	r4, r0
  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
 80011e2:	0791      	lsls	r1, r2, #30
 80011e4:	d50e      	bpl.n	8001204 <HAL_TIM_IRQHandler+0x2a>
  {
    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
 80011e6:	68da      	ldr	r2, [r3, #12]
 80011e8:	0792      	lsls	r2, r2, #30
 80011ea:	d50b      	bpl.n	8001204 <HAL_TIM_IRQHandler+0x2a>
    {
      {
        __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
 80011ec:	f06f 0202 	mvn.w	r2, #2
 80011f0:	611a      	str	r2, [r3, #16]
        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
 80011f2:	2201      	movs	r2, #1

        /* Input capture event */
        if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
 80011f4:	699b      	ldr	r3, [r3, #24]
        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
 80011f6:	7702      	strb	r2, [r0, #28]
        if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
 80011f8:	079b      	lsls	r3, r3, #30
 80011fa:	d077      	beq.n	80012ec <HAL_TIM_IRQHandler+0x112>
        {
          HAL_TIM_IC_CaptureCallback(htim);
 80011fc:	f7ff ffea 	bl	80011d4 <HAL_TIM_IC_CaptureCallback>
        else
        {
          HAL_TIM_OC_DelayElapsedCallback(htim);
          HAL_TIM_PWM_PulseFinishedCallback(htim);
        }
        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 8001200:	2300      	movs	r3, #0
 8001202:	7723      	strb	r3, [r4, #28]
      }
    }
  }
  /* Capture compare 2 event */
  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
 8001204:	6823      	ldr	r3, [r4, #0]
 8001206:	691a      	ldr	r2, [r3, #16]
 8001208:	0750      	lsls	r0, r2, #29
 800120a:	d510      	bpl.n	800122e <HAL_TIM_IRQHandler+0x54>
  {
    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
 800120c:	68da      	ldr	r2, [r3, #12]
 800120e:	0751      	lsls	r1, r2, #29
 8001210:	d50d      	bpl.n	800122e <HAL_TIM_IRQHandler+0x54>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
 8001212:	f06f 0204 	mvn.w	r2, #4
 8001216:	611a      	str	r2, [r3, #16]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
 8001218:	2202      	movs	r2, #2
      /* Input capture event */
      if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
 800121a:	699b      	ldr	r3, [r3, #24]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
 800121c:	7722      	strb	r2, [r4, #28]
      if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
 800121e:	f413 7f40 	tst.w	r3, #768	; 0x300
      {
        HAL_TIM_IC_CaptureCallback(htim);
 8001222:	4620      	mov	r0, r4
      if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
 8001224:	d068      	beq.n	80012f8 <HAL_TIM_IRQHandler+0x11e>
        HAL_TIM_IC_CaptureCallback(htim);
 8001226:	f7ff ffd5 	bl	80011d4 <HAL_TIM_IC_CaptureCallback>
      else
      {
        HAL_TIM_OC_DelayElapsedCallback(htim);
        HAL_TIM_PWM_PulseFinishedCallback(htim);
      }
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 800122a:	2300      	movs	r3, #0
 800122c:	7723      	strb	r3, [r4, #28]
    }
  }
  /* Capture compare 3 event */
  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
 800122e:	6823      	ldr	r3, [r4, #0]
 8001230:	691a      	ldr	r2, [r3, #16]
 8001232:	0712      	lsls	r2, r2, #28
 8001234:	d50f      	bpl.n	8001256 <HAL_TIM_IRQHandler+0x7c>
  {
    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
 8001236:	68da      	ldr	r2, [r3, #12]
 8001238:	0710      	lsls	r0, r2, #28
 800123a:	d50c      	bpl.n	8001256 <HAL_TIM_IRQHandler+0x7c>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
 800123c:	f06f 0208 	mvn.w	r2, #8
 8001240:	611a      	str	r2, [r3, #16]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
 8001242:	2204      	movs	r2, #4
      /* Input capture event */
      if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
 8001244:	69db      	ldr	r3, [r3, #28]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
 8001246:	7722      	strb	r2, [r4, #28]
      if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
 8001248:	0799      	lsls	r1, r3, #30
      {
        HAL_TIM_IC_CaptureCallback(htim);
 800124a:	4620      	mov	r0, r4
      if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
 800124c:	d05a      	beq.n	8001304 <HAL_TIM_IRQHandler+0x12a>
        HAL_TIM_IC_CaptureCallback(htim);
 800124e:	f7ff ffc1 	bl	80011d4 <HAL_TIM_IC_CaptureCallback>
      else
      {
        HAL_TIM_OC_DelayElapsedCallback(htim);
        HAL_TIM_PWM_PulseFinishedCallback(htim);
      }
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 8001252:	2300      	movs	r3, #0
 8001254:	7723      	strb	r3, [r4, #28]
    }
  }
  /* Capture compare 4 event */
  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
 8001256:	6823      	ldr	r3, [r4, #0]
 8001258:	691a      	ldr	r2, [r3, #16]
 800125a:	06d2      	lsls	r2, r2, #27
 800125c:	d510      	bpl.n	8001280 <HAL_TIM_IRQHandler+0xa6>
  {
    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
 800125e:	68da      	ldr	r2, [r3, #12]
 8001260:	06d0      	lsls	r0, r2, #27
 8001262:	d50d      	bpl.n	8001280 <HAL_TIM_IRQHandler+0xa6>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
 8001264:	f06f 0210 	mvn.w	r2, #16
 8001268:	611a      	str	r2, [r3, #16]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
 800126a:	2208      	movs	r2, #8
      /* Input capture event */
      if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
 800126c:	69db      	ldr	r3, [r3, #28]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
 800126e:	7722      	strb	r2, [r4, #28]
      if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
 8001270:	f413 7f40 	tst.w	r3, #768	; 0x300
      {
        HAL_TIM_IC_CaptureCallback(htim);
 8001274:	4620      	mov	r0, r4
      if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
 8001276:	d04b      	beq.n	8001310 <HAL_TIM_IRQHandler+0x136>
        HAL_TIM_IC_CaptureCallback(htim);
 8001278:	f7ff ffac 	bl	80011d4 <HAL_TIM_IC_CaptureCallback>
      else
      {
        HAL_TIM_OC_DelayElapsedCallback(htim);
        HAL_TIM_PWM_PulseFinishedCallback(htim);
      }
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 800127c:	2300      	movs	r3, #0
 800127e:	7723      	strb	r3, [r4, #28]
    }
  }
  /* TIM Update event */
  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
 8001280:	6823      	ldr	r3, [r4, #0]
 8001282:	691a      	ldr	r2, [r3, #16]
 8001284:	07d1      	lsls	r1, r2, #31
 8001286:	d508      	bpl.n	800129a <HAL_TIM_IRQHandler+0xc0>
  {
    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
 8001288:	68da      	ldr	r2, [r3, #12]
 800128a:	07d2      	lsls	r2, r2, #31
 800128c:	d505      	bpl.n	800129a <HAL_TIM_IRQHandler+0xc0>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
 800128e:	f06f 0201 	mvn.w	r2, #1
      HAL_TIM_PeriodElapsedCallback(htim);
 8001292:	4620      	mov	r0, r4
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
 8001294:	611a      	str	r2, [r3, #16]
      HAL_TIM_PeriodElapsedCallback(htim);
 8001296:	f000 fe85 	bl	8001fa4 <HAL_TIM_PeriodElapsedCallback>
    }
  }
  /* TIM Break input event */
  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
 800129a:	6823      	ldr	r3, [r4, #0]
 800129c:	691a      	ldr	r2, [r3, #16]
 800129e:	0610      	lsls	r0, r2, #24
 80012a0:	d508      	bpl.n	80012b4 <HAL_TIM_IRQHandler+0xda>
  {
    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
 80012a2:	68da      	ldr	r2, [r3, #12]
 80012a4:	0611      	lsls	r1, r2, #24
 80012a6:	d505      	bpl.n	80012b4 <HAL_TIM_IRQHandler+0xda>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
 80012a8:	f06f 0280 	mvn.w	r2, #128	; 0x80
      HAL_TIMEx_BreakCallback(htim);
 80012ac:	4620      	mov	r0, r4
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
 80012ae:	611a      	str	r2, [r3, #16]
      HAL_TIMEx_BreakCallback(htim);
 80012b0:	f000 f8bf 	bl	8001432 <HAL_TIMEx_BreakCallback>
    }
  }
  /* TIM Trigger detection event */
  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
 80012b4:	6823      	ldr	r3, [r4, #0]
 80012b6:	691a      	ldr	r2, [r3, #16]
 80012b8:	0652      	lsls	r2, r2, #25
 80012ba:	d508      	bpl.n	80012ce <HAL_TIM_IRQHandler+0xf4>
  {
    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
 80012bc:	68da      	ldr	r2, [r3, #12]
 80012be:	0650      	lsls	r0, r2, #25
 80012c0:	d505      	bpl.n	80012ce <HAL_TIM_IRQHandler+0xf4>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
 80012c2:	f06f 0240 	mvn.w	r2, #64	; 0x40
      HAL_TIM_TriggerCallback(htim);
 80012c6:	4620      	mov	r0, r4
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
 80012c8:	611a      	str	r2, [r3, #16]
      HAL_TIM_TriggerCallback(htim);
 80012ca:	f7ff ff85 	bl	80011d8 <HAL_TIM_TriggerCallback>
    }
  }
  /* TIM commutation event */
  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
 80012ce:	6823      	ldr	r3, [r4, #0]
 80012d0:	691a      	ldr	r2, [r3, #16]
 80012d2:	0691      	lsls	r1, r2, #26
 80012d4:	d522      	bpl.n	800131c <HAL_TIM_IRQHandler+0x142>
  {
    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
 80012d6:	68da      	ldr	r2, [r3, #12]
 80012d8:	0692      	lsls	r2, r2, #26
 80012da:	d51f      	bpl.n	800131c <HAL_TIM_IRQHandler+0x142>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
 80012dc:	f06f 0220 	mvn.w	r2, #32
      HAL_TIMEx_CommutationCallback(htim);
 80012e0:	4620      	mov	r0, r4
    }
  }
}
 80012e2:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
      __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
 80012e6:	611a      	str	r2, [r3, #16]
      HAL_TIMEx_CommutationCallback(htim);
 80012e8:	f000 b8a2 	b.w	8001430 <HAL_TIMEx_CommutationCallback>
          HAL_TIM_OC_DelayElapsedCallback(htim);
 80012ec:	f7ff ff71 	bl	80011d2 <HAL_TIM_OC_DelayElapsedCallback>
          HAL_TIM_PWM_PulseFinishedCallback(htim);
 80012f0:	4620      	mov	r0, r4
 80012f2:	f7ff ff70 	bl	80011d6 <HAL_TIM_PWM_PulseFinishedCallback>
 80012f6:	e783      	b.n	8001200 <HAL_TIM_IRQHandler+0x26>
        HAL_TIM_OC_DelayElapsedCallback(htim);
 80012f8:	f7ff ff6b 	bl	80011d2 <HAL_TIM_OC_DelayElapsedCallback>
        HAL_TIM_PWM_PulseFinishedCallback(htim);
 80012fc:	4620      	mov	r0, r4
 80012fe:	f7ff ff6a 	bl	80011d6 <HAL_TIM_PWM_PulseFinishedCallback>
 8001302:	e792      	b.n	800122a <HAL_TIM_IRQHandler+0x50>
        HAL_TIM_OC_DelayElapsedCallback(htim);
 8001304:	f7ff ff65 	bl	80011d2 <HAL_TIM_OC_DelayElapsedCallback>
        HAL_TIM_PWM_PulseFinishedCallback(htim);
 8001308:	4620      	mov	r0, r4
 800130a:	f7ff ff64 	bl	80011d6 <HAL_TIM_PWM_PulseFinishedCallback>
 800130e:	e7a0      	b.n	8001252 <HAL_TIM_IRQHandler+0x78>
        HAL_TIM_OC_DelayElapsedCallback(htim);
 8001310:	f7ff ff5f 	bl	80011d2 <HAL_TIM_OC_DelayElapsedCallback>
        HAL_TIM_PWM_PulseFinishedCallback(htim);
 8001314:	4620      	mov	r0, r4
 8001316:	f7ff ff5e 	bl	80011d6 <HAL_TIM_PWM_PulseFinishedCallback>
 800131a:	e7af      	b.n	800127c <HAL_TIM_IRQHandler+0xa2>
 800131c:	bd10      	pop	{r4, pc}
	...

08001320 <TIM_Base_SetConfig>:
{
  uint32_t tmpcr1 = 0U;
  tmpcr1 = TIMx->CR1;

  /* Set TIM Time Base Unit parameters ---------------------------------------*/
  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
 8001320:	4a24      	ldr	r2, [pc, #144]	; (80013b4 <TIM_Base_SetConfig+0x94>)
  tmpcr1 = TIMx->CR1;
 8001322:	6803      	ldr	r3, [r0, #0]
  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
 8001324:	4290      	cmp	r0, r2
 8001326:	d012      	beq.n	800134e <TIM_Base_SetConfig+0x2e>
 8001328:	f502 6200 	add.w	r2, r2, #2048	; 0x800
 800132c:	4290      	cmp	r0, r2
 800132e:	d00e      	beq.n	800134e <TIM_Base_SetConfig+0x2e>
 8001330:	f1b0 4f80 	cmp.w	r0, #1073741824	; 0x40000000
 8001334:	d00b      	beq.n	800134e <TIM_Base_SetConfig+0x2e>
 8001336:	f5a2 3298 	sub.w	r2, r2, #77824	; 0x13000
 800133a:	4290      	cmp	r0, r2
 800133c:	d007      	beq.n	800134e <TIM_Base_SetConfig+0x2e>
 800133e:	f502 6280 	add.w	r2, r2, #1024	; 0x400
 8001342:	4290      	cmp	r0, r2
 8001344:	d003      	beq.n	800134e <TIM_Base_SetConfig+0x2e>
 8001346:	f502 6280 	add.w	r2, r2, #1024	; 0x400
 800134a:	4290      	cmp	r0, r2
 800134c:	d11d      	bne.n	800138a <TIM_Base_SetConfig+0x6a>
  {
    /* Select the Counter Mode */
    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
    tmpcr1 |= Structure->CounterMode;
 800134e:	684a      	ldr	r2, [r1, #4]
    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
 8001350:	f023 0370 	bic.w	r3, r3, #112	; 0x70
    tmpcr1 |= Structure->CounterMode;
 8001354:	4313      	orrs	r3, r2
  }

  if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
 8001356:	4a17      	ldr	r2, [pc, #92]	; (80013b4 <TIM_Base_SetConfig+0x94>)
 8001358:	4290      	cmp	r0, r2
 800135a:	d012      	beq.n	8001382 <TIM_Base_SetConfig+0x62>
 800135c:	f502 6200 	add.w	r2, r2, #2048	; 0x800
 8001360:	4290      	cmp	r0, r2
 8001362:	d00e      	beq.n	8001382 <TIM_Base_SetConfig+0x62>
 8001364:	f1b0 4f80 	cmp.w	r0, #1073741824	; 0x40000000
 8001368:	d00b      	beq.n	8001382 <TIM_Base_SetConfig+0x62>
 800136a:	f5a2 3298 	sub.w	r2, r2, #77824	; 0x13000
 800136e:	4290      	cmp	r0, r2
 8001370:	d007      	beq.n	8001382 <TIM_Base_SetConfig+0x62>
 8001372:	f502 6280 	add.w	r2, r2, #1024	; 0x400
 8001376:	4290      	cmp	r0, r2
 8001378:	d003      	beq.n	8001382 <TIM_Base_SetConfig+0x62>
 800137a:	f502 6280 	add.w	r2, r2, #1024	; 0x400
 800137e:	4290      	cmp	r0, r2
 8001380:	d103      	bne.n	800138a <TIM_Base_SetConfig+0x6a>
  {
    /* Set the clock division */
    tmpcr1 &= ~TIM_CR1_CKD;
    tmpcr1 |= (uint32_t)Structure->ClockDivision;
 8001382:	68ca      	ldr	r2, [r1, #12]
    tmpcr1 &= ~TIM_CR1_CKD;
 8001384:	f423 7340 	bic.w	r3, r3, #768	; 0x300
    tmpcr1 |= (uint32_t)Structure->ClockDivision;
 8001388:	4313      	orrs	r3, r2
  }

  /* Set the auto-reload preload */
  tmpcr1 &= ~TIM_CR1_ARPE;
  tmpcr1 |= (uint32_t)Structure->AutoReloadPreload;
 800138a:	694a      	ldr	r2, [r1, #20]
  tmpcr1 &= ~TIM_CR1_ARPE;
 800138c:	f023 0380 	bic.w	r3, r3, #128	; 0x80
  tmpcr1 |= (uint32_t)Structure->AutoReloadPreload;
 8001390:	4313      	orrs	r3, r2

  TIMx->CR1 = tmpcr1;
 8001392:	6003      	str	r3, [r0, #0]

  /* Set the Autoreload value */
  TIMx->ARR = (uint32_t)Structure->Period ;
 8001394:	688b      	ldr	r3, [r1, #8]
 8001396:	62c3      	str	r3, [r0, #44]	; 0x2c

  /* Set the Prescaler value */
  TIMx->PSC = (uint32_t)Structure->Prescaler;
 8001398:	680b      	ldr	r3, [r1, #0]
 800139a:	6283      	str	r3, [r0, #40]	; 0x28

  if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
 800139c:	4b05      	ldr	r3, [pc, #20]	; (80013b4 <TIM_Base_SetConfig+0x94>)
 800139e:	4298      	cmp	r0, r3
 80013a0:	d003      	beq.n	80013aa <TIM_Base_SetConfig+0x8a>
 80013a2:	f503 6300 	add.w	r3, r3, #2048	; 0x800
 80013a6:	4298      	cmp	r0, r3
 80013a8:	d101      	bne.n	80013ae <TIM_Base_SetConfig+0x8e>
  {
    /* Set the Repetition Counter value */
    TIMx->RCR = Structure->RepetitionCounter;
 80013aa:	690b      	ldr	r3, [r1, #16]
 80013ac:	6303      	str	r3, [r0, #48]	; 0x30
  }

  /* Generate an update event to reload the Prescaler 
     and the repetition counter(only for TIM1 and TIM8) value immediatly */
  TIMx->EGR = TIM_EGR_UG;
 80013ae:	2301      	movs	r3, #1
 80013b0:	6143      	str	r3, [r0, #20]
 80013b2:	4770      	bx	lr
 80013b4:	40012c00 	.word	0x40012c00

080013b8 <HAL_TIM_Base_Init>:
{
 80013b8:	b510      	push	{r4, lr}
  if(htim == NULL)
 80013ba:	4604      	mov	r4, r0
 80013bc:	b1a0      	cbz	r0, 80013e8 <HAL_TIM_Base_Init+0x30>
  if(htim->State == HAL_TIM_STATE_RESET)
 80013be:	f890 303d 	ldrb.w	r3, [r0, #61]	; 0x3d
 80013c2:	f003 02ff 	and.w	r2, r3, #255	; 0xff
 80013c6:	b91b      	cbnz	r3, 80013d0 <HAL_TIM_Base_Init+0x18>
    htim->Lock = HAL_UNLOCKED;
 80013c8:	f880 203c 	strb.w	r2, [r0, #60]	; 0x3c
    HAL_TIM_Base_MspInit(htim);
 80013cc:	f000 ff68 	bl	80022a0 <HAL_TIM_Base_MspInit>
  htim->State= HAL_TIM_STATE_BUSY;
 80013d0:	2302      	movs	r3, #2
  TIM_Base_SetConfig(htim->Instance, &htim->Init);
 80013d2:	6820      	ldr	r0, [r4, #0]
  htim->State= HAL_TIM_STATE_BUSY;
 80013d4:	f884 303d 	strb.w	r3, [r4, #61]	; 0x3d
  TIM_Base_SetConfig(htim->Instance, &htim->Init);
 80013d8:	1d21      	adds	r1, r4, #4
 80013da:	f7ff ffa1 	bl	8001320 <TIM_Base_SetConfig>
  htim->State= HAL_TIM_STATE_READY;
 80013de:	2301      	movs	r3, #1
  return HAL_OK;
 80013e0:	2000      	movs	r0, #0
  htim->State= HAL_TIM_STATE_READY;
 80013e2:	f884 303d 	strb.w	r3, [r4, #61]	; 0x3d
  return HAL_OK;
 80013e6:	bd10      	pop	{r4, pc}
    return HAL_ERROR;
 80013e8:	2001      	movs	r0, #1
}
 80013ea:	bd10      	pop	{r4, pc}

080013ec <HAL_TIMEx_MasterConfigSynchronization>:
  /* Check the parameters */
  assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
  assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
  assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));

  __HAL_LOCK(htim);
 80013ec:	f890 303c 	ldrb.w	r3, [r0, #60]	; 0x3c
{
 80013f0:	b510      	push	{r4, lr}
  __HAL_LOCK(htim);
 80013f2:	2b01      	cmp	r3, #1
 80013f4:	f04f 0302 	mov.w	r3, #2
 80013f8:	d018      	beq.n	800142c <HAL_TIMEx_MasterConfigSynchronization+0x40>

  htim->State = HAL_TIM_STATE_BUSY;
 80013fa:	f880 303d 	strb.w	r3, [r0, #61]	; 0x3d

  /* Reset the MMS Bits */
  htim->Instance->CR2 &= ~TIM_CR2_MMS;
 80013fe:	6803      	ldr	r3, [r0, #0]
  /* Select the TRGO source */
  htim->Instance->CR2 |=  sMasterConfig->MasterOutputTrigger;
 8001400:	680c      	ldr	r4, [r1, #0]
  htim->Instance->CR2 &= ~TIM_CR2_MMS;
 8001402:	685a      	ldr	r2, [r3, #4]

  /* Reset the MSM Bit */
  htim->Instance->SMCR &= ~TIM_SMCR_MSM;
  /* Set or Reset the MSM Bit */
  htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode;
 8001404:	6849      	ldr	r1, [r1, #4]
  htim->Instance->CR2 &= ~TIM_CR2_MMS;
 8001406:	f022 0270 	bic.w	r2, r2, #112	; 0x70
 800140a:	605a      	str	r2, [r3, #4]
  htim->Instance->CR2 |=  sMasterConfig->MasterOutputTrigger;
 800140c:	685a      	ldr	r2, [r3, #4]
 800140e:	4322      	orrs	r2, r4
 8001410:	605a      	str	r2, [r3, #4]
  htim->Instance->SMCR &= ~TIM_SMCR_MSM;
 8001412:	689a      	ldr	r2, [r3, #8]
 8001414:	f022 0280 	bic.w	r2, r2, #128	; 0x80
 8001418:	609a      	str	r2, [r3, #8]
  htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode;
 800141a:	689a      	ldr	r2, [r3, #8]
 800141c:	430a      	orrs	r2, r1
 800141e:	609a      	str	r2, [r3, #8]

  htim->State = HAL_TIM_STATE_READY;
 8001420:	2301      	movs	r3, #1
 8001422:	f880 303d 	strb.w	r3, [r0, #61]	; 0x3d

  __HAL_UNLOCK(htim);
 8001426:	2300      	movs	r3, #0
 8001428:	f880 303c 	strb.w	r3, [r0, #60]	; 0x3c
  __HAL_LOCK(htim);
 800142c:	4618      	mov	r0, r3

  return HAL_OK;
}
 800142e:	bd10      	pop	{r4, pc}

08001430 <HAL_TIMEx_CommutationCallback>:
 8001430:	4770      	bx	lr

08001432 <HAL_TIMEx_BreakCallback>:
  * @brief  Hall Break detection callback in non blocking mode
  * @param  htim : TIM handle
  * @retval None
  */
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
{
 8001432:	4770      	bx	lr

08001434 <UART_EndRxTransfer>:
  * @retval None
  */
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
{
  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
 8001434:	6803      	ldr	r3, [r0, #0]
 8001436:	68da      	ldr	r2, [r3, #12]
 8001438:	f422 7290 	bic.w	r2, r2, #288	; 0x120
 800143c:	60da      	str	r2, [r3, #12]
  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 800143e:	695a      	ldr	r2, [r3, #20]
 8001440:	f022 0201 	bic.w	r2, r2, #1
 8001444:	615a      	str	r2, [r3, #20]

  /* At end of Rx process, restore huart->RxState to Ready */
  huart->RxState = HAL_UART_STATE_READY;
 8001446:	2320      	movs	r3, #32
 8001448:	f880 303a 	strb.w	r3, [r0, #58]	; 0x3a
 800144c:	4770      	bx	lr
	...

08001450 <UART_SetConfig>:
  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
  *                the configuration information for the specified UART module.
  * @retval None
  */
static void UART_SetConfig(UART_HandleTypeDef *huart)
{
 8001450:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
  assert_param(IS_UART_MODE(huart->Init.Mode));

  /*------- UART-associated USART registers setting : CR2 Configuration ------*/
  /* Configure the UART Stop Bits: Set STOP[13:12] bits according 
   * to huart->Init.StopBits value */
  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
 8001454:	6805      	ldr	r5, [r0, #0]
 8001456:	68c2      	ldr	r2, [r0, #12]
 8001458:	692b      	ldr	r3, [r5, #16]
  tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
  MODIFY_REG(huart->Instance->CR1, 
             (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), 
             tmpreg);
#else
  tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
 800145a:	6901      	ldr	r1, [r0, #16]
  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
 800145c:	f423 5340 	bic.w	r3, r3, #12288	; 0x3000
 8001460:	4313      	orrs	r3, r2
 8001462:	612b      	str	r3, [r5, #16]
  tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
 8001464:	6883      	ldr	r3, [r0, #8]
  MODIFY_REG(huart->Instance->CR1, 
 8001466:	68ea      	ldr	r2, [r5, #12]
  tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
 8001468:	430b      	orrs	r3, r1
 800146a:	6941      	ldr	r1, [r0, #20]
  MODIFY_REG(huart->Instance->CR1, 
 800146c:	f422 52b0 	bic.w	r2, r2, #5632	; 0x1600
 8001470:	f022 020c 	bic.w	r2, r2, #12
  tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
 8001474:	430b      	orrs	r3, r1
  MODIFY_REG(huart->Instance->CR1, 
 8001476:	4313      	orrs	r3, r2
 8001478:	60eb      	str	r3, [r5, #12]
             tmpreg);
#endif /* USART_CR1_OVER8 */

  /*------- UART-associated USART registers setting : CR3 Configuration ------*/
  /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
  MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
 800147a:	696b      	ldr	r3, [r5, #20]
 800147c:	6982      	ldr	r2, [r0, #24]
 800147e:	f423 7340 	bic.w	r3, r3, #768	; 0x300
 8001482:	4313      	orrs	r3, r2
 8001484:	616b      	str	r3, [r5, #20]
      huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
    }
  }
#else
  /*-------------------------- USART BRR Configuration ---------------------*/
  if(huart->Instance == USART1)
 8001486:	4b40      	ldr	r3, [pc, #256]	; (8001588 <UART_SetConfig+0x138>)
{
 8001488:	4681      	mov	r9, r0
  if(huart->Instance == USART1)
 800148a:	429d      	cmp	r5, r3
 800148c:	f04f 0419 	mov.w	r4, #25
 8001490:	d146      	bne.n	8001520 <UART_SetConfig+0xd0>
  {
    huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
 8001492:	f7ff fe83 	bl	800119c <HAL_RCC_GetPCLK2Freq>
 8001496:	fb04 f300 	mul.w	r3, r4, r0
 800149a:	f8d9 6004 	ldr.w	r6, [r9, #4]
 800149e:	f04f 0864 	mov.w	r8, #100	; 0x64
 80014a2:	00b6      	lsls	r6, r6, #2
 80014a4:	fbb3 f3f6 	udiv	r3, r3, r6
 80014a8:	fbb3 f3f8 	udiv	r3, r3, r8
 80014ac:	011e      	lsls	r6, r3, #4
 80014ae:	f7ff fe75 	bl	800119c <HAL_RCC_GetPCLK2Freq>
 80014b2:	4360      	muls	r0, r4
 80014b4:	f8d9 3004 	ldr.w	r3, [r9, #4]
 80014b8:	009b      	lsls	r3, r3, #2
 80014ba:	fbb0 f7f3 	udiv	r7, r0, r3
 80014be:	f7ff fe6d 	bl	800119c <HAL_RCC_GetPCLK2Freq>
 80014c2:	4360      	muls	r0, r4
 80014c4:	f8d9 3004 	ldr.w	r3, [r9, #4]
 80014c8:	009b      	lsls	r3, r3, #2
 80014ca:	fbb0 f3f3 	udiv	r3, r0, r3
 80014ce:	fbb3 f3f8 	udiv	r3, r3, r8
 80014d2:	fb08 7313 	mls	r3, r8, r3, r7
 80014d6:	011b      	lsls	r3, r3, #4
 80014d8:	3332      	adds	r3, #50	; 0x32
 80014da:	fbb3 f3f8 	udiv	r3, r3, r8
 80014de:	f003 07f0 	and.w	r7, r3, #240	; 0xf0
 80014e2:	f7ff fe5b 	bl	800119c <HAL_RCC_GetPCLK2Freq>
 80014e6:	4360      	muls	r0, r4
 80014e8:	f8d9 2004 	ldr.w	r2, [r9, #4]
 80014ec:	0092      	lsls	r2, r2, #2
 80014ee:	fbb0 faf2 	udiv	sl, r0, r2
 80014f2:	f7ff fe53 	bl	800119c <HAL_RCC_GetPCLK2Freq>
  }
  else
  {
    huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
 80014f6:	4360      	muls	r0, r4
 80014f8:	f8d9 3004 	ldr.w	r3, [r9, #4]
 80014fc:	009b      	lsls	r3, r3, #2
 80014fe:	fbb0 f3f3 	udiv	r3, r0, r3
 8001502:	fbb3 f3f8 	udiv	r3, r3, r8
 8001506:	fb08 a313 	mls	r3, r8, r3, sl
 800150a:	011b      	lsls	r3, r3, #4
 800150c:	3332      	adds	r3, #50	; 0x32
 800150e:	fbb3 f3f8 	udiv	r3, r3, r8
 8001512:	f003 030f 	and.w	r3, r3, #15
 8001516:	433b      	orrs	r3, r7
 8001518:	4433      	add	r3, r6
 800151a:	60ab      	str	r3, [r5, #8]
 800151c:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 8001520:	f7ff fe2c 	bl	800117c <HAL_RCC_GetPCLK1Freq>
 8001524:	fb04 f300 	mul.w	r3, r4, r0
 8001528:	f8d9 6004 	ldr.w	r6, [r9, #4]
 800152c:	f04f 0864 	mov.w	r8, #100	; 0x64
 8001530:	00b6      	lsls	r6, r6, #2
 8001532:	fbb3 f3f6 	udiv	r3, r3, r6
 8001536:	fbb3 f3f8 	udiv	r3, r3, r8
 800153a:	011e      	lsls	r6, r3, #4
 800153c:	f7ff fe1e 	bl	800117c <HAL_RCC_GetPCLK1Freq>
 8001540:	4360      	muls	r0, r4
 8001542:	f8d9 3004 	ldr.w	r3, [r9, #4]
 8001546:	009b      	lsls	r3, r3, #2
 8001548:	fbb0 f7f3 	udiv	r7, r0, r3
 800154c:	f7ff fe16 	bl	800117c <HAL_RCC_GetPCLK1Freq>
 8001550:	4360      	muls	r0, r4
 8001552:	f8d9 3004 	ldr.w	r3, [r9, #4]
 8001556:	009b      	lsls	r3, r3, #2
 8001558:	fbb0 f3f3 	udiv	r3, r0, r3
 800155c:	fbb3 f3f8 	udiv	r3, r3, r8
 8001560:	fb08 7313 	mls	r3, r8, r3, r7
 8001564:	011b      	lsls	r3, r3, #4
 8001566:	3332      	adds	r3, #50	; 0x32
 8001568:	fbb3 f3f8 	udiv	r3, r3, r8
 800156c:	f003 07f0 	and.w	r7, r3, #240	; 0xf0
 8001570:	f7ff fe04 	bl	800117c <HAL_RCC_GetPCLK1Freq>
 8001574:	4360      	muls	r0, r4
 8001576:	f8d9 2004 	ldr.w	r2, [r9, #4]
 800157a:	0092      	lsls	r2, r2, #2
 800157c:	fbb0 faf2 	udiv	sl, r0, r2
 8001580:	f7ff fdfc 	bl	800117c <HAL_RCC_GetPCLK1Freq>
 8001584:	e7b7      	b.n	80014f6 <UART_SetConfig+0xa6>
 8001586:	bf00      	nop
 8001588:	40013800 	.word	0x40013800

0800158c <UART_WaitOnFlagUntilTimeout.constprop.3>:
static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
 800158c:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 800158e:	4604      	mov	r4, r0
 8001590:	460e      	mov	r6, r1
 8001592:	4617      	mov	r7, r2
 8001594:	461d      	mov	r5, r3
  while((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 
 8001596:	6821      	ldr	r1, [r4, #0]
 8001598:	680b      	ldr	r3, [r1, #0]
 800159a:	ea36 0303 	bics.w	r3, r6, r3
 800159e:	d101      	bne.n	80015a4 <UART_WaitOnFlagUntilTimeout.constprop.3+0x18>
  return HAL_OK;
 80015a0:	2000      	movs	r0, #0
}
 80015a2:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
    if(Timeout != HAL_MAX_DELAY)
 80015a4:	1c6b      	adds	r3, r5, #1
 80015a6:	d0f7      	beq.n	8001598 <UART_WaitOnFlagUntilTimeout.constprop.3+0xc>
      if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
 80015a8:	b995      	cbnz	r5, 80015d0 <UART_WaitOnFlagUntilTimeout.constprop.3+0x44>
        CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
 80015aa:	6823      	ldr	r3, [r4, #0]
        __HAL_UNLOCK(huart);
 80015ac:	2003      	movs	r0, #3
        CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
 80015ae:	68da      	ldr	r2, [r3, #12]
 80015b0:	f422 72d0 	bic.w	r2, r2, #416	; 0x1a0
 80015b4:	60da      	str	r2, [r3, #12]
        CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 80015b6:	695a      	ldr	r2, [r3, #20]
 80015b8:	f022 0201 	bic.w	r2, r2, #1
 80015bc:	615a      	str	r2, [r3, #20]
        huart->gState  = HAL_UART_STATE_READY;
 80015be:	2320      	movs	r3, #32
 80015c0:	f884 3039 	strb.w	r3, [r4, #57]	; 0x39
        huart->RxState = HAL_UART_STATE_READY;
 80015c4:	f884 303a 	strb.w	r3, [r4, #58]	; 0x3a
        __HAL_UNLOCK(huart);
 80015c8:	2300      	movs	r3, #0
 80015ca:	f884 3038 	strb.w	r3, [r4, #56]	; 0x38
 80015ce:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
      if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
 80015d0:	f7fe fe76 	bl	80002c0 <HAL_GetTick>
 80015d4:	1bc0      	subs	r0, r0, r7
 80015d6:	4285      	cmp	r5, r0
 80015d8:	d2dd      	bcs.n	8001596 <UART_WaitOnFlagUntilTimeout.constprop.3+0xa>
 80015da:	e7e6      	b.n	80015aa <UART_WaitOnFlagUntilTimeout.constprop.3+0x1e>

080015dc <HAL_UART_Init>:
{
 80015dc:	b510      	push	{r4, lr}
  if(huart == NULL)
 80015de:	4604      	mov	r4, r0
 80015e0:	b340      	cbz	r0, 8001634 <HAL_UART_Init+0x58>
  if(huart->gState == HAL_UART_STATE_RESET)
 80015e2:	f890 3039 	ldrb.w	r3, [r0, #57]	; 0x39
 80015e6:	f003 02ff 	and.w	r2, r3, #255	; 0xff
 80015ea:	b91b      	cbnz	r3, 80015f4 <HAL_UART_Init+0x18>
    huart->Lock = HAL_UNLOCKED;
 80015ec:	f880 2038 	strb.w	r2, [r0, #56]	; 0x38
    HAL_UART_MspInit(huart);
 80015f0:	f000 fe6a 	bl	80022c8 <HAL_UART_MspInit>
  huart->gState = HAL_UART_STATE_BUSY;
 80015f4:	2324      	movs	r3, #36	; 0x24
  __HAL_UART_DISABLE(huart);
 80015f6:	6822      	ldr	r2, [r4, #0]
  huart->gState = HAL_UART_STATE_BUSY;
 80015f8:	f884 3039 	strb.w	r3, [r4, #57]	; 0x39
  __HAL_UART_DISABLE(huart);
 80015fc:	68d3      	ldr	r3, [r2, #12]
  UART_SetConfig(huart);
 80015fe:	4620      	mov	r0, r4
  __HAL_UART_DISABLE(huart);
 8001600:	f423 5300 	bic.w	r3, r3, #8192	; 0x2000
 8001604:	60d3      	str	r3, [r2, #12]
  UART_SetConfig(huart);
 8001606:	f7ff ff23 	bl	8001450 <UART_SetConfig>
  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
 800160a:	6823      	ldr	r3, [r4, #0]
  huart->ErrorCode = HAL_UART_ERROR_NONE;
 800160c:	2000      	movs	r0, #0
  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
 800160e:	691a      	ldr	r2, [r3, #16]
 8001610:	f422 4290 	bic.w	r2, r2, #18432	; 0x4800
 8001614:	611a      	str	r2, [r3, #16]
  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
 8001616:	695a      	ldr	r2, [r3, #20]
 8001618:	f022 022a 	bic.w	r2, r2, #42	; 0x2a
 800161c:	615a      	str	r2, [r3, #20]
  __HAL_UART_ENABLE(huart);
 800161e:	68da      	ldr	r2, [r3, #12]
 8001620:	f442 5200 	orr.w	r2, r2, #8192	; 0x2000
 8001624:	60da      	str	r2, [r3, #12]
  huart->gState= HAL_UART_STATE_READY;
 8001626:	2320      	movs	r3, #32
  huart->ErrorCode = HAL_UART_ERROR_NONE;
 8001628:	63e0      	str	r0, [r4, #60]	; 0x3c
  huart->gState= HAL_UART_STATE_READY;
 800162a:	f884 3039 	strb.w	r3, [r4, #57]	; 0x39
  huart->RxState= HAL_UART_STATE_READY;
 800162e:	f884 303a 	strb.w	r3, [r4, #58]	; 0x3a
  return HAL_OK;
 8001632:	bd10      	pop	{r4, pc}
    return HAL_ERROR;
 8001634:	2001      	movs	r0, #1
}
 8001636:	bd10      	pop	{r4, pc}

08001638 <HAL_UART_Transmit>:
{
 8001638:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
 800163c:	461f      	mov	r7, r3
  if(huart->gState == HAL_UART_STATE_READY)
 800163e:	f890 3039 	ldrb.w	r3, [r0, #57]	; 0x39
{
 8001642:	4604      	mov	r4, r0
  if(huart->gState == HAL_UART_STATE_READY)
 8001644:	2b20      	cmp	r3, #32
{
 8001646:	460d      	mov	r5, r1
 8001648:	4690      	mov	r8, r2
  if(huart->gState == HAL_UART_STATE_READY)
 800164a:	d14e      	bne.n	80016ea <HAL_UART_Transmit+0xb2>
    if((pData == NULL) || (Size == 0U))
 800164c:	2900      	cmp	r1, #0
 800164e:	d049      	beq.n	80016e4 <HAL_UART_Transmit+0xac>
 8001650:	2a00      	cmp	r2, #0
 8001652:	d047      	beq.n	80016e4 <HAL_UART_Transmit+0xac>
    __HAL_LOCK(huart);
 8001654:	f890 3038 	ldrb.w	r3, [r0, #56]	; 0x38
 8001658:	2b01      	cmp	r3, #1
 800165a:	d046      	beq.n	80016ea <HAL_UART_Transmit+0xb2>
 800165c:	2301      	movs	r3, #1
 800165e:	f880 3038 	strb.w	r3, [r0, #56]	; 0x38
    huart->ErrorCode = HAL_UART_ERROR_NONE;
 8001662:	2300      	movs	r3, #0
 8001664:	63c3      	str	r3, [r0, #60]	; 0x3c
    huart->gState = HAL_UART_STATE_BUSY_TX;
 8001666:	2321      	movs	r3, #33	; 0x21
 8001668:	f880 3039 	strb.w	r3, [r0, #57]	; 0x39
    tickstart = HAL_GetTick();
 800166c:	f7fe fe28 	bl	80002c0 <HAL_GetTick>
 8001670:	4606      	mov	r6, r0
    huart->TxXferSize = Size;
 8001672:	f8a4 8024 	strh.w	r8, [r4, #36]	; 0x24
    huart->TxXferCount = Size;
 8001676:	f8a4 8026 	strh.w	r8, [r4, #38]	; 0x26
    while(huart->TxXferCount > 0U)
 800167a:	8ce3      	ldrh	r3, [r4, #38]	; 0x26
 800167c:	b29b      	uxth	r3, r3
 800167e:	b96b      	cbnz	r3, 800169c <HAL_UART_Transmit+0x64>
    if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
 8001680:	463b      	mov	r3, r7
 8001682:	4632      	mov	r2, r6
 8001684:	2140      	movs	r1, #64	; 0x40
 8001686:	4620      	mov	r0, r4
 8001688:	f7ff ff80 	bl	800158c <UART_WaitOnFlagUntilTimeout.constprop.3>
 800168c:	b9a8      	cbnz	r0, 80016ba <HAL_UART_Transmit+0x82>
    huart->gState = HAL_UART_STATE_READY;
 800168e:	2320      	movs	r3, #32
    __HAL_UNLOCK(huart);
 8001690:	f884 0038 	strb.w	r0, [r4, #56]	; 0x38
    huart->gState = HAL_UART_STATE_READY;
 8001694:	f884 3039 	strb.w	r3, [r4, #57]	; 0x39
    return HAL_OK;
 8001698:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
      huart->TxXferCount--;
 800169c:	8ce3      	ldrh	r3, [r4, #38]	; 0x26
        if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
 800169e:	4632      	mov	r2, r6
      huart->TxXferCount--;
 80016a0:	3b01      	subs	r3, #1
 80016a2:	b29b      	uxth	r3, r3
 80016a4:	84e3      	strh	r3, [r4, #38]	; 0x26
      if(huart->Init.WordLength == UART_WORDLENGTH_9B)
 80016a6:	68a3      	ldr	r3, [r4, #8]
        if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
 80016a8:	2180      	movs	r1, #128	; 0x80
      if(huart->Init.WordLength == UART_WORDLENGTH_9B)
 80016aa:	f5b3 5f80 	cmp.w	r3, #4096	; 0x1000
        if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
 80016ae:	4620      	mov	r0, r4
 80016b0:	463b      	mov	r3, r7
      if(huart->Init.WordLength == UART_WORDLENGTH_9B)
 80016b2:	d10e      	bne.n	80016d2 <HAL_UART_Transmit+0x9a>
        if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
 80016b4:	f7ff ff6a 	bl	800158c <UART_WaitOnFlagUntilTimeout.constprop.3>
 80016b8:	b110      	cbz	r0, 80016c0 <HAL_UART_Transmit+0x88>
          return HAL_TIMEOUT;
 80016ba:	2003      	movs	r0, #3
 80016bc:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
        huart->Instance->DR = (*tmp & (uint16_t)0x01FF);
 80016c0:	882b      	ldrh	r3, [r5, #0]
 80016c2:	6822      	ldr	r2, [r4, #0]
 80016c4:	f3c3 0308 	ubfx	r3, r3, #0, #9
 80016c8:	6053      	str	r3, [r2, #4]
        if(huart->Init.Parity == UART_PARITY_NONE)
 80016ca:	6923      	ldr	r3, [r4, #16]
 80016cc:	b943      	cbnz	r3, 80016e0 <HAL_UART_Transmit+0xa8>
          pData +=2U;
 80016ce:	3502      	adds	r5, #2
 80016d0:	e7d3      	b.n	800167a <HAL_UART_Transmit+0x42>
        if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
 80016d2:	f7ff ff5b 	bl	800158c <UART_WaitOnFlagUntilTimeout.constprop.3>
 80016d6:	2800      	cmp	r0, #0
 80016d8:	d1ef      	bne.n	80016ba <HAL_UART_Transmit+0x82>
        huart->Instance->DR = (*pData++ & (uint8_t)0xFF);
 80016da:	6823      	ldr	r3, [r4, #0]
 80016dc:	782a      	ldrb	r2, [r5, #0]
 80016de:	605a      	str	r2, [r3, #4]
 80016e0:	3501      	adds	r5, #1
 80016e2:	e7ca      	b.n	800167a <HAL_UART_Transmit+0x42>
      return  HAL_ERROR;
 80016e4:	2001      	movs	r0, #1
 80016e6:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
    return HAL_BUSY;
 80016ea:	2002      	movs	r0, #2
}
 80016ec:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

080016f0 <HAL_UART_Receive_DMA>:
{
 80016f0:	4613      	mov	r3, r2
  if(huart->RxState == HAL_UART_STATE_READY) 
 80016f2:	f890 203a 	ldrb.w	r2, [r0, #58]	; 0x3a
{
 80016f6:	b573      	push	{r0, r1, r4, r5, r6, lr}
  if(huart->RxState == HAL_UART_STATE_READY) 
 80016f8:	2a20      	cmp	r2, #32
{
 80016fa:	4605      	mov	r5, r0
  if(huart->RxState == HAL_UART_STATE_READY) 
 80016fc:	d138      	bne.n	8001770 <HAL_UART_Receive_DMA+0x80>
    if((pData == NULL) || (Size == 0U))
 80016fe:	2900      	cmp	r1, #0
 8001700:	d034      	beq.n	800176c <HAL_UART_Receive_DMA+0x7c>
 8001702:	2b00      	cmp	r3, #0
 8001704:	d032      	beq.n	800176c <HAL_UART_Receive_DMA+0x7c>
    __HAL_LOCK(huart);
 8001706:	f890 2038 	ldrb.w	r2, [r0, #56]	; 0x38
 800170a:	2a01      	cmp	r2, #1
 800170c:	d030      	beq.n	8001770 <HAL_UART_Receive_DMA+0x80>
 800170e:	2201      	movs	r2, #1
    huart->ErrorCode = HAL_UART_ERROR_NONE;
 8001710:	2400      	movs	r4, #0
    __HAL_LOCK(huart);
 8001712:	f880 2038 	strb.w	r2, [r0, #56]	; 0x38
    huart->RxState = HAL_UART_STATE_BUSY_RX;
 8001716:	2222      	movs	r2, #34	; 0x22
    huart->pRxBuffPtr = pData;
 8001718:	6281      	str	r1, [r0, #40]	; 0x28
    huart->RxXferSize = Size;
 800171a:	8583      	strh	r3, [r0, #44]	; 0x2c
    huart->ErrorCode = HAL_UART_ERROR_NONE;
 800171c:	63c4      	str	r4, [r0, #60]	; 0x3c
    huart->RxState = HAL_UART_STATE_BUSY_RX;
 800171e:	f880 203a 	strb.w	r2, [r0, #58]	; 0x3a
    huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
 8001722:	6b40      	ldr	r0, [r0, #52]	; 0x34
 8001724:	4a13      	ldr	r2, [pc, #76]	; (8001774 <HAL_UART_Receive_DMA+0x84>)
    HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t*)tmp, Size);
 8001726:	682e      	ldr	r6, [r5, #0]
    huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
 8001728:	6282      	str	r2, [r0, #40]	; 0x28
    huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
 800172a:	4a13      	ldr	r2, [pc, #76]	; (8001778 <HAL_UART_Receive_DMA+0x88>)
    huart->hdmarx->XferAbortCallback = NULL;
 800172c:	6344      	str	r4, [r0, #52]	; 0x34
    huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
 800172e:	62c2      	str	r2, [r0, #44]	; 0x2c
    huart->hdmarx->XferErrorCallback = UART_DMAError;
 8001730:	4a12      	ldr	r2, [pc, #72]	; (800177c <HAL_UART_Receive_DMA+0x8c>)
 8001732:	6302      	str	r2, [r0, #48]	; 0x30
    HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t*)tmp, Size);
 8001734:	460a      	mov	r2, r1
 8001736:	1d31      	adds	r1, r6, #4
 8001738:	f7fe fe82 	bl	8000440 <HAL_DMA_Start_IT>
    return HAL_OK;
 800173c:	4620      	mov	r0, r4
    __HAL_UART_CLEAR_OREFLAG(huart);
 800173e:	682b      	ldr	r3, [r5, #0]
 8001740:	9401      	str	r4, [sp, #4]
 8001742:	681a      	ldr	r2, [r3, #0]
 8001744:	9201      	str	r2, [sp, #4]
 8001746:	685a      	ldr	r2, [r3, #4]
    __HAL_UNLOCK(huart);
 8001748:	f885 4038 	strb.w	r4, [r5, #56]	; 0x38
    __HAL_UART_CLEAR_OREFLAG(huart);
 800174c:	9201      	str	r2, [sp, #4]
 800174e:	9a01      	ldr	r2, [sp, #4]
    SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
 8001750:	68da      	ldr	r2, [r3, #12]
 8001752:	f442 7280 	orr.w	r2, r2, #256	; 0x100
 8001756:	60da      	str	r2, [r3, #12]
    SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
 8001758:	695a      	ldr	r2, [r3, #20]
 800175a:	f042 0201 	orr.w	r2, r2, #1
 800175e:	615a      	str	r2, [r3, #20]
    SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
 8001760:	695a      	ldr	r2, [r3, #20]
 8001762:	f042 0240 	orr.w	r2, r2, #64	; 0x40
 8001766:	615a      	str	r2, [r3, #20]
}
 8001768:	b002      	add	sp, #8
 800176a:	bd70      	pop	{r4, r5, r6, pc}
      return HAL_ERROR;
 800176c:	2001      	movs	r0, #1
 800176e:	e7fb      	b.n	8001768 <HAL_UART_Receive_DMA+0x78>
    return HAL_BUSY;
 8001770:	2002      	movs	r0, #2
 8001772:	e7f9      	b.n	8001768 <HAL_UART_Receive_DMA+0x78>
 8001774:	08001783 	.word	0x08001783
 8001778:	08001839 	.word	0x08001839
 800177c:	08001845 	.word	0x08001845

08001780 <HAL_UART_TxCpltCallback>:
 8001780:	4770      	bx	lr

08001782 <UART_DMAReceiveCplt>:
{
 8001782:	b508      	push	{r3, lr}
  if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
 8001784:	6803      	ldr	r3, [r0, #0]
  UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
 8001786:	6a42      	ldr	r2, [r0, #36]	; 0x24
  if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
 8001788:	681b      	ldr	r3, [r3, #0]
 800178a:	f013 0320 	ands.w	r3, r3, #32
 800178e:	d110      	bne.n	80017b2 <UART_DMAReceiveCplt+0x30>
    huart->RxXferCount = 0U;
 8001790:	85d3      	strh	r3, [r2, #46]	; 0x2e
    CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
 8001792:	6813      	ldr	r3, [r2, #0]
 8001794:	68d9      	ldr	r1, [r3, #12]
 8001796:	f421 7180 	bic.w	r1, r1, #256	; 0x100
 800179a:	60d9      	str	r1, [r3, #12]
    CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 800179c:	6959      	ldr	r1, [r3, #20]
 800179e:	f021 0101 	bic.w	r1, r1, #1
 80017a2:	6159      	str	r1, [r3, #20]
    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
 80017a4:	6959      	ldr	r1, [r3, #20]
 80017a6:	f021 0140 	bic.w	r1, r1, #64	; 0x40
 80017aa:	6159      	str	r1, [r3, #20]
    huart->RxState = HAL_UART_STATE_READY;
 80017ac:	2320      	movs	r3, #32
 80017ae:	f882 303a 	strb.w	r3, [r2, #58]	; 0x3a
  HAL_UART_RxCpltCallback(huart);
 80017b2:	4610      	mov	r0, r2
 80017b4:	f000 fee0 	bl	8002578 <HAL_UART_RxCpltCallback>
 80017b8:	bd08      	pop	{r3, pc}

080017ba <UART_Receive_IT>:
  if(huart->RxState == HAL_UART_STATE_BUSY_RX) 
 80017ba:	f890 303a 	ldrb.w	r3, [r0, #58]	; 0x3a
{
 80017be:	b510      	push	{r4, lr}
  if(huart->RxState == HAL_UART_STATE_BUSY_RX) 
 80017c0:	2b22      	cmp	r3, #34	; 0x22
 80017c2:	d136      	bne.n	8001832 <UART_Receive_IT+0x78>
    if(huart->Init.WordLength == UART_WORDLENGTH_9B)
 80017c4:	6883      	ldr	r3, [r0, #8]
 80017c6:	6901      	ldr	r1, [r0, #16]
 80017c8:	f5b3 5f80 	cmp.w	r3, #4096	; 0x1000
 80017cc:	6802      	ldr	r2, [r0, #0]
 80017ce:	6a83      	ldr	r3, [r0, #40]	; 0x28
 80017d0:	d123      	bne.n	800181a <UART_Receive_IT+0x60>
        *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
 80017d2:	6852      	ldr	r2, [r2, #4]
      if(huart->Init.Parity == UART_PARITY_NONE)
 80017d4:	b9e9      	cbnz	r1, 8001812 <UART_Receive_IT+0x58>
        *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
 80017d6:	f3c2 0208 	ubfx	r2, r2, #0, #9
 80017da:	f823 2b02 	strh.w	r2, [r3], #2
        huart->pRxBuffPtr += 1U;
 80017de:	6283      	str	r3, [r0, #40]	; 0x28
    if(--huart->RxXferCount == 0U)
 80017e0:	8dc4      	ldrh	r4, [r0, #46]	; 0x2e
 80017e2:	3c01      	subs	r4, #1
 80017e4:	b2a4      	uxth	r4, r4
 80017e6:	85c4      	strh	r4, [r0, #46]	; 0x2e
 80017e8:	b98c      	cbnz	r4, 800180e <UART_Receive_IT+0x54>
      __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
 80017ea:	6803      	ldr	r3, [r0, #0]
 80017ec:	68da      	ldr	r2, [r3, #12]
 80017ee:	f022 0220 	bic.w	r2, r2, #32
 80017f2:	60da      	str	r2, [r3, #12]
      __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
 80017f4:	68da      	ldr	r2, [r3, #12]
 80017f6:	f422 7280 	bic.w	r2, r2, #256	; 0x100
 80017fa:	60da      	str	r2, [r3, #12]
        __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
 80017fc:	695a      	ldr	r2, [r3, #20]
 80017fe:	f022 0201 	bic.w	r2, r2, #1
 8001802:	615a      	str	r2, [r3, #20]
      huart->RxState = HAL_UART_STATE_READY;
 8001804:	2320      	movs	r3, #32
 8001806:	f880 303a 	strb.w	r3, [r0, #58]	; 0x3a
      HAL_UART_RxCpltCallback(huart);
 800180a:	f000 feb5 	bl	8002578 <HAL_UART_RxCpltCallback>
    if(--huart->RxXferCount == 0U)
 800180e:	2000      	movs	r0, #0
}
 8001810:	bd10      	pop	{r4, pc}
        *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF);
 8001812:	b2d2      	uxtb	r2, r2
 8001814:	f823 2b01 	strh.w	r2, [r3], #1
 8001818:	e7e1      	b.n	80017de <UART_Receive_IT+0x24>
      if(huart->Init.Parity == UART_PARITY_NONE)
 800181a:	b921      	cbnz	r1, 8001826 <UART_Receive_IT+0x6c>
        *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
 800181c:	1c59      	adds	r1, r3, #1
 800181e:	6852      	ldr	r2, [r2, #4]
 8001820:	6281      	str	r1, [r0, #40]	; 0x28
        *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
 8001822:	701a      	strb	r2, [r3, #0]
 8001824:	e7dc      	b.n	80017e0 <UART_Receive_IT+0x26>
 8001826:	6852      	ldr	r2, [r2, #4]
 8001828:	1c59      	adds	r1, r3, #1
 800182a:	6281      	str	r1, [r0, #40]	; 0x28
 800182c:	f002 027f 	and.w	r2, r2, #127	; 0x7f
 8001830:	e7f7      	b.n	8001822 <UART_Receive_IT+0x68>
    return HAL_BUSY;
 8001832:	2002      	movs	r0, #2
 8001834:	bd10      	pop	{r4, pc}

08001836 <HAL_UART_RxHalfCpltCallback>:
 8001836:	4770      	bx	lr

08001838 <UART_DMARxHalfCplt>:
{
 8001838:	b508      	push	{r3, lr}
  HAL_UART_RxHalfCpltCallback(huart); 
 800183a:	6a40      	ldr	r0, [r0, #36]	; 0x24
 800183c:	f7ff fffb 	bl	8001836 <HAL_UART_RxHalfCpltCallback>
 8001840:	bd08      	pop	{r3, pc}

08001842 <HAL_UART_ErrorCallback>:
 8001842:	4770      	bx	lr

08001844 <UART_DMAError>:
  UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
 8001844:	6a41      	ldr	r1, [r0, #36]	; 0x24
{
 8001846:	b508      	push	{r3, lr}
  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
 8001848:	680b      	ldr	r3, [r1, #0]
 800184a:	695a      	ldr	r2, [r3, #20]
  if((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
 800184c:	f891 0039 	ldrb.w	r0, [r1, #57]	; 0x39
 8001850:	2821      	cmp	r0, #33	; 0x21
 8001852:	d10a      	bne.n	800186a <UART_DMAError+0x26>
 8001854:	0612      	lsls	r2, r2, #24
 8001856:	d508      	bpl.n	800186a <UART_DMAError+0x26>
    huart->TxXferCount = 0U;
 8001858:	2200      	movs	r2, #0
 800185a:	84ca      	strh	r2, [r1, #38]	; 0x26
  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
 800185c:	68da      	ldr	r2, [r3, #12]
 800185e:	f022 02c0 	bic.w	r2, r2, #192	; 0xc0
 8001862:	60da      	str	r2, [r3, #12]
  huart->gState = HAL_UART_STATE_READY;
 8001864:	2220      	movs	r2, #32
 8001866:	f881 2039 	strb.w	r2, [r1, #57]	; 0x39
  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 
 800186a:	695b      	ldr	r3, [r3, #20]
  if((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
 800186c:	f891 203a 	ldrb.w	r2, [r1, #58]	; 0x3a
 8001870:	2a22      	cmp	r2, #34	; 0x22
 8001872:	d106      	bne.n	8001882 <UART_DMAError+0x3e>
 8001874:	065b      	lsls	r3, r3, #25
 8001876:	d504      	bpl.n	8001882 <UART_DMAError+0x3e>
    huart->RxXferCount = 0U;
 8001878:	2300      	movs	r3, #0
    UART_EndRxTransfer(huart);
 800187a:	4608      	mov	r0, r1
    huart->RxXferCount = 0U;
 800187c:	85cb      	strh	r3, [r1, #46]	; 0x2e
    UART_EndRxTransfer(huart);
 800187e:	f7ff fdd9 	bl	8001434 <UART_EndRxTransfer>
  huart->ErrorCode |= HAL_UART_ERROR_DMA;
 8001882:	6bcb      	ldr	r3, [r1, #60]	; 0x3c
  HAL_UART_ErrorCallback(huart);
 8001884:	4608      	mov	r0, r1
  huart->ErrorCode |= HAL_UART_ERROR_DMA;
 8001886:	f043 0310 	orr.w	r3, r3, #16
 800188a:	63cb      	str	r3, [r1, #60]	; 0x3c
  HAL_UART_ErrorCallback(huart);
 800188c:	f7ff ffd9 	bl	8001842 <HAL_UART_ErrorCallback>
 8001890:	bd08      	pop	{r3, pc}
	...

08001894 <HAL_UART_IRQHandler>:
   uint32_t isrflags   = READ_REG(huart->Instance->SR);
 8001894:	6803      	ldr	r3, [r0, #0]
{
 8001896:	b570      	push	{r4, r5, r6, lr}
   uint32_t isrflags   = READ_REG(huart->Instance->SR);
 8001898:	681a      	ldr	r2, [r3, #0]
{
 800189a:	4604      	mov	r4, r0
  if(errorflags == RESET)
 800189c:	0716      	lsls	r6, r2, #28
   uint32_t cr1its     = READ_REG(huart->Instance->CR1);
 800189e:	68d9      	ldr	r1, [r3, #12]
   uint32_t cr3its     = READ_REG(huart->Instance->CR3);
 80018a0:	695d      	ldr	r5, [r3, #20]
  if(errorflags == RESET)
 80018a2:	d107      	bne.n	80018b4 <HAL_UART_IRQHandler+0x20>
    if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
 80018a4:	0696      	lsls	r6, r2, #26
 80018a6:	d55a      	bpl.n	800195e <HAL_UART_IRQHandler+0xca>
 80018a8:	068d      	lsls	r5, r1, #26
 80018aa:	d558      	bpl.n	800195e <HAL_UART_IRQHandler+0xca>
}
 80018ac:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
      UART_Receive_IT(huart);
 80018b0:	f7ff bf83 	b.w	80017ba <UART_Receive_IT>
  if((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
 80018b4:	f015 0501 	ands.w	r5, r5, #1
 80018b8:	d102      	bne.n	80018c0 <HAL_UART_IRQHandler+0x2c>
 80018ba:	f411 7f90 	tst.w	r1, #288	; 0x120
 80018be:	d04e      	beq.n	800195e <HAL_UART_IRQHandler+0xca>
    if(((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
 80018c0:	07d3      	lsls	r3, r2, #31
 80018c2:	d505      	bpl.n	80018d0 <HAL_UART_IRQHandler+0x3c>
 80018c4:	05ce      	lsls	r6, r1, #23
      huart->ErrorCode |= HAL_UART_ERROR_PE;
 80018c6:	bf42      	ittt	mi
 80018c8:	6be3      	ldrmi	r3, [r4, #60]	; 0x3c
 80018ca:	f043 0301 	orrmi.w	r3, r3, #1
 80018ce:	63e3      	strmi	r3, [r4, #60]	; 0x3c
    if(((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
 80018d0:	0750      	lsls	r0, r2, #29
 80018d2:	d504      	bpl.n	80018de <HAL_UART_IRQHandler+0x4a>
 80018d4:	b11d      	cbz	r5, 80018de <HAL_UART_IRQHandler+0x4a>
      huart->ErrorCode |= HAL_UART_ERROR_NE;
 80018d6:	6be3      	ldr	r3, [r4, #60]	; 0x3c
 80018d8:	f043 0302 	orr.w	r3, r3, #2
 80018dc:	63e3      	str	r3, [r4, #60]	; 0x3c
    if(((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
 80018de:	0793      	lsls	r3, r2, #30
 80018e0:	d504      	bpl.n	80018ec <HAL_UART_IRQHandler+0x58>
 80018e2:	b11d      	cbz	r5, 80018ec <HAL_UART_IRQHandler+0x58>
      huart->ErrorCode |= HAL_UART_ERROR_FE;
 80018e4:	6be3      	ldr	r3, [r4, #60]	; 0x3c
 80018e6:	f043 0304 	orr.w	r3, r3, #4
 80018ea:	63e3      	str	r3, [r4, #60]	; 0x3c
    if(((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
 80018ec:	0716      	lsls	r6, r2, #28
 80018ee:	d504      	bpl.n	80018fa <HAL_UART_IRQHandler+0x66>
 80018f0:	b11d      	cbz	r5, 80018fa <HAL_UART_IRQHandler+0x66>
      huart->ErrorCode |= HAL_UART_ERROR_ORE;
 80018f2:	6be3      	ldr	r3, [r4, #60]	; 0x3c
 80018f4:	f043 0308 	orr.w	r3, r3, #8
 80018f8:	63e3      	str	r3, [r4, #60]	; 0x3c
    if(huart->ErrorCode != HAL_UART_ERROR_NONE)
 80018fa:	6be3      	ldr	r3, [r4, #60]	; 0x3c
 80018fc:	2b00      	cmp	r3, #0
 80018fe:	d066      	beq.n	80019ce <HAL_UART_IRQHandler+0x13a>
      if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
 8001900:	0695      	lsls	r5, r2, #26
 8001902:	d504      	bpl.n	800190e <HAL_UART_IRQHandler+0x7a>
 8001904:	0688      	lsls	r0, r1, #26
 8001906:	d502      	bpl.n	800190e <HAL_UART_IRQHandler+0x7a>
        UART_Receive_IT(huart);
 8001908:	4620      	mov	r0, r4
 800190a:	f7ff ff56 	bl	80017ba <UART_Receive_IT>
      dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
 800190e:	6823      	ldr	r3, [r4, #0]
        UART_EndRxTransfer(huart);
 8001910:	4620      	mov	r0, r4
      dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
 8001912:	695d      	ldr	r5, [r3, #20]
      if(((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest)
 8001914:	6be2      	ldr	r2, [r4, #60]	; 0x3c
 8001916:	0711      	lsls	r1, r2, #28
 8001918:	d402      	bmi.n	8001920 <HAL_UART_IRQHandler+0x8c>
 800191a:	f015 0540 	ands.w	r5, r5, #64	; 0x40
 800191e:	d01a      	beq.n	8001956 <HAL_UART_IRQHandler+0xc2>
        UART_EndRxTransfer(huart);
 8001920:	f7ff fd88 	bl	8001434 <UART_EndRxTransfer>
        if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
 8001924:	6823      	ldr	r3, [r4, #0]
 8001926:	695a      	ldr	r2, [r3, #20]
 8001928:	0652      	lsls	r2, r2, #25
 800192a:	d510      	bpl.n	800194e <HAL_UART_IRQHandler+0xba>
          CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
 800192c:	695a      	ldr	r2, [r3, #20]
          if(huart->hdmarx != NULL)
 800192e:	6b60      	ldr	r0, [r4, #52]	; 0x34
          CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
 8001930:	f022 0240 	bic.w	r2, r2, #64	; 0x40
 8001934:	615a      	str	r2, [r3, #20]
          if(huart->hdmarx != NULL)
 8001936:	b150      	cbz	r0, 800194e <HAL_UART_IRQHandler+0xba>
            huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
 8001938:	4b25      	ldr	r3, [pc, #148]	; (80019d0 <HAL_UART_IRQHandler+0x13c>)
 800193a:	6343      	str	r3, [r0, #52]	; 0x34
            if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
 800193c:	f7fe fdbe 	bl	80004bc <HAL_DMA_Abort_IT>
 8001940:	2800      	cmp	r0, #0
 8001942:	d044      	beq.n	80019ce <HAL_UART_IRQHandler+0x13a>
              huart->hdmarx->XferAbortCallback(huart->hdmarx);
 8001944:	6b60      	ldr	r0, [r4, #52]	; 0x34
}
 8001946:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
              huart->hdmarx->XferAbortCallback(huart->hdmarx);
 800194a:	6b43      	ldr	r3, [r0, #52]	; 0x34
 800194c:	4718      	bx	r3
            HAL_UART_ErrorCallback(huart);
 800194e:	4620      	mov	r0, r4
 8001950:	f7ff ff77 	bl	8001842 <HAL_UART_ErrorCallback>
 8001954:	bd70      	pop	{r4, r5, r6, pc}
        HAL_UART_ErrorCallback(huart);
 8001956:	f7ff ff74 	bl	8001842 <HAL_UART_ErrorCallback>
        huart->ErrorCode = HAL_UART_ERROR_NONE;
 800195a:	63e5      	str	r5, [r4, #60]	; 0x3c
 800195c:	bd70      	pop	{r4, r5, r6, pc}
  if(((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
 800195e:	0616      	lsls	r6, r2, #24
 8001960:	d527      	bpl.n	80019b2 <HAL_UART_IRQHandler+0x11e>
 8001962:	060d      	lsls	r5, r1, #24
 8001964:	d525      	bpl.n	80019b2 <HAL_UART_IRQHandler+0x11e>
  if(huart->gState == HAL_UART_STATE_BUSY_TX)
 8001966:	f894 2039 	ldrb.w	r2, [r4, #57]	; 0x39
 800196a:	2a21      	cmp	r2, #33	; 0x21
 800196c:	d12f      	bne.n	80019ce <HAL_UART_IRQHandler+0x13a>
    if(huart->Init.WordLength == UART_WORDLENGTH_9B)
 800196e:	68a2      	ldr	r2, [r4, #8]
 8001970:	f5b2 5f80 	cmp.w	r2, #4096	; 0x1000
 8001974:	6a22      	ldr	r2, [r4, #32]
 8001976:	d117      	bne.n	80019a8 <HAL_UART_IRQHandler+0x114>
      huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
 8001978:	8811      	ldrh	r1, [r2, #0]
 800197a:	f3c1 0108 	ubfx	r1, r1, #0, #9
 800197e:	6059      	str	r1, [r3, #4]
      if(huart->Init.Parity == UART_PARITY_NONE)
 8001980:	6921      	ldr	r1, [r4, #16]
 8001982:	b979      	cbnz	r1, 80019a4 <HAL_UART_IRQHandler+0x110>
        huart->pTxBuffPtr += 2U;
 8001984:	3202      	adds	r2, #2
        huart->pTxBuffPtr += 1U;
 8001986:	6222      	str	r2, [r4, #32]
    if(--huart->TxXferCount == 0U)
 8001988:	8ce2      	ldrh	r2, [r4, #38]	; 0x26
 800198a:	3a01      	subs	r2, #1
 800198c:	b292      	uxth	r2, r2
 800198e:	84e2      	strh	r2, [r4, #38]	; 0x26
 8001990:	b9ea      	cbnz	r2, 80019ce <HAL_UART_IRQHandler+0x13a>
      __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
 8001992:	68da      	ldr	r2, [r3, #12]
 8001994:	f022 0280 	bic.w	r2, r2, #128	; 0x80
 8001998:	60da      	str	r2, [r3, #12]
      __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
 800199a:	68da      	ldr	r2, [r3, #12]
 800199c:	f042 0240 	orr.w	r2, r2, #64	; 0x40
 80019a0:	60da      	str	r2, [r3, #12]
 80019a2:	bd70      	pop	{r4, r5, r6, pc}
        huart->pTxBuffPtr += 1U;
 80019a4:	3201      	adds	r2, #1
 80019a6:	e7ee      	b.n	8001986 <HAL_UART_IRQHandler+0xf2>
      huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF);
 80019a8:	1c51      	adds	r1, r2, #1
 80019aa:	6221      	str	r1, [r4, #32]
 80019ac:	7812      	ldrb	r2, [r2, #0]
 80019ae:	605a      	str	r2, [r3, #4]
 80019b0:	e7ea      	b.n	8001988 <HAL_UART_IRQHandler+0xf4>
  if(((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
 80019b2:	0650      	lsls	r0, r2, #25
 80019b4:	d50b      	bpl.n	80019ce <HAL_UART_IRQHandler+0x13a>
 80019b6:	064a      	lsls	r2, r1, #25
 80019b8:	d509      	bpl.n	80019ce <HAL_UART_IRQHandler+0x13a>
  __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
 80019ba:	68da      	ldr	r2, [r3, #12]
  HAL_UART_TxCpltCallback(huart);
 80019bc:	4620      	mov	r0, r4
  __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
 80019be:	f022 0240 	bic.w	r2, r2, #64	; 0x40
 80019c2:	60da      	str	r2, [r3, #12]
  huart->gState = HAL_UART_STATE_READY;
 80019c4:	2320      	movs	r3, #32
 80019c6:	f884 3039 	strb.w	r3, [r4, #57]	; 0x39
  HAL_UART_TxCpltCallback(huart);
 80019ca:	f7ff fed9 	bl	8001780 <HAL_UART_TxCpltCallback>
 80019ce:	bd70      	pop	{r4, r5, r6, pc}
 80019d0:	080019d5 	.word	0x080019d5

080019d4 <UART_DMAAbortOnError>:
{
 80019d4:	b508      	push	{r3, lr}
  huart->RxXferCount = 0x00U;
 80019d6:	2300      	movs	r3, #0
  UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
 80019d8:	6a40      	ldr	r0, [r0, #36]	; 0x24
  huart->RxXferCount = 0x00U;
 80019da:	85c3      	strh	r3, [r0, #46]	; 0x2e
  huart->TxXferCount = 0x00U;
 80019dc:	84c3      	strh	r3, [r0, #38]	; 0x26
  HAL_UART_ErrorCallback(huart);
 80019de:	f7ff ff30 	bl	8001842 <HAL_UART_ErrorCallback>
 80019e2:	bd08      	pop	{r3, pc}

080019e4 <Firmware_BootStart_Signal>:
 * ***/
#define Bluecell_BootStart 0x0b


uint8_t BootStartdata[6] = {0xbe,Bluecell_BootStart,0x03,4,0,0xeb};
void Firmware_BootStart_Signal(){
 80019e4:	b510      	push	{r4, lr}
	BootStartdata[bluecell_crc] = STH30_CreateCrc(&BootStartdata[bluecell_type],BootStartdata[bluecell_length]);
 80019e6:	4c06      	ldr	r4, [pc, #24]	; (8001a00 <Firmware_BootStart_Signal+0x1c>)
 80019e8:	78a1      	ldrb	r1, [r4, #2]
 80019ea:	1c60      	adds	r0, r4, #1
 80019ec:	f000 f8c0 	bl	8001b70 <STH30_CreateCrc>
    Uart1_Data_Send(&BootStartdata[bluecell_stx],BootStartdata[bluecell_length] + 3);
 80019f0:	78a1      	ldrb	r1, [r4, #2]
	BootStartdata[bluecell_crc] = STH30_CreateCrc(&BootStartdata[bluecell_type],BootStartdata[bluecell_length]);
 80019f2:	7120      	strb	r0, [r4, #4]
    Uart1_Data_Send(&BootStartdata[bluecell_stx],BootStartdata[bluecell_length] + 3);
 80019f4:	3103      	adds	r1, #3
 80019f6:	4620      	mov	r0, r4
}
 80019f8:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
    Uart1_Data_Send(&BootStartdata[bluecell_stx],BootStartdata[bluecell_length] + 3);
 80019fc:	f000 bde2 	b.w	80025c4 <Uart1_Data_Send>
 8001a00:	2000000e 	.word	0x2000000e

08001a04 <FirmwareUpdateStart>:

    uint8_t AckData_Buf[6] = {0xbe,FirmwareUpdataAck,0x03,5,0,0xbe};
void FirmwareUpdateStart(uint8_t* data){
 8001a04:	b570      	push	{r4, r5, r6, lr}
    uint8_t ret = 0,crccheck = 0;
    crccheck = STH30_CheckCrc(&data[bluecell_type],data[bluecell_length],data[data[bluecell_length] + 1]);
 8001a06:	7881      	ldrb	r1, [r0, #2]
void FirmwareUpdateStart(uint8_t* data){
 8001a08:	4604      	mov	r4, r0
    crccheck = STH30_CheckCrc(&data[bluecell_type],data[bluecell_length],data[data[bluecell_length] + 1]);
 8001a0a:	1843      	adds	r3, r0, r1
 8001a0c:	785a      	ldrb	r2, [r3, #1]
 8001a0e:	3001      	adds	r0, #1
 8001a10:	f000 f8c9 	bl	8001ba6 <STH30_CheckCrc>
    if(crccheck == NO_ERROR){
 8001a14:	b2c0      	uxtb	r0, r0
 8001a16:	2801      	cmp	r0, #1
 8001a18:	d00e      	beq.n	8001a38 <FirmwareUpdateStart+0x34>
 8001a1a:	2300      	movs	r3, #0
            ret = Flash_write(&data[0]);
        if(ret == 1)
            AckData_Buf[bluecell_type] = FirmwareUpdataNak;
    }else{
        for(uint8_t i = 0; i < data[bluecell_length] + 3; i++)
            printf("%02x ",data[i]);
 8001a1c:	4e1e      	ldr	r6, [pc, #120]	; (8001a98 <FirmwareUpdateStart+0x94>)
        for(uint8_t i = 0; i < data[bluecell_length] + 3; i++)
 8001a1e:	78a2      	ldrb	r2, [r4, #2]
 8001a20:	1c5d      	adds	r5, r3, #1
 8001a22:	3202      	adds	r2, #2
 8001a24:	b2db      	uxtb	r3, r3
 8001a26:	429a      	cmp	r2, r3
 8001a28:	da2e      	bge.n	8001a88 <FirmwareUpdateStart+0x84>
        printf("Check Sum error \n");
 8001a2a:	481c      	ldr	r0, [pc, #112]	; (8001a9c <FirmwareUpdateStart+0x98>)
 8001a2c:	f000 fea0 	bl	8002770 <puts>
        AckData_Buf[bluecell_type] = FirmwareUpdataNak;
 8001a30:	2222      	movs	r2, #34	; 0x22
 8001a32:	4b1b      	ldr	r3, [pc, #108]	; (8001aa0 <FirmwareUpdateStart+0x9c>)
 8001a34:	705a      	strb	r2, [r3, #1]
 8001a36:	e00f      	b.n	8001a58 <FirmwareUpdateStart+0x54>
        AckData_Buf[bluecell_type] = FirmwareUpdataAck;
 8001a38:	2211      	movs	r2, #17
 8001a3a:	4d19      	ldr	r5, [pc, #100]	; (8001aa0 <FirmwareUpdateStart+0x9c>)
 8001a3c:	706a      	strb	r2, [r5, #1]
        if(data[bluecell_type] == 0xDD || data[bluecell_type] == 0xEE)//Start Firmware byte
 8001a3e:	7862      	ldrb	r2, [r4, #1]
 8001a40:	2add      	cmp	r2, #221	; 0xdd
 8001a42:	d001      	beq.n	8001a48 <FirmwareUpdateStart+0x44>
 8001a44:	2aee      	cmp	r2, #238	; 0xee
 8001a46:	d107      	bne.n	8001a58 <FirmwareUpdateStart+0x54>
            ret = Flash_write(&data[0]);
 8001a48:	4620      	mov	r0, r4
 8001a4a:	f000 fa21 	bl	8001e90 <Flash_write>
        if(ret == 1)
 8001a4e:	b2c0      	uxtb	r0, r0
 8001a50:	2801      	cmp	r0, #1
 8001a52:	d101      	bne.n	8001a58 <FirmwareUpdateStart+0x54>
            AckData_Buf[bluecell_type] = FirmwareUpdataNak;
 8001a54:	2322      	movs	r3, #34	; 0x22
 8001a56:	706b      	strb	r3, [r5, #1]
    }
    AckData_Buf[bluecell_crc] = STH30_CreateCrc(&AckData_Buf[bluecell_type],AckData_Buf[bluecell_length]);
 8001a58:	4d11      	ldr	r5, [pc, #68]	; (8001aa0 <FirmwareUpdateStart+0x9c>)
 8001a5a:	78a9      	ldrb	r1, [r5, #2]
 8001a5c:	1c68      	adds	r0, r5, #1
 8001a5e:	f000 f887 	bl	8001b70 <STH30_CreateCrc>
 8001a62:	7128      	strb	r0, [r5, #4]
    if(data[bluecell_type] != 0xEE && data[bluecell_type] != Bluecell_Reset){
 8001a64:	7863      	ldrb	r3, [r4, #1]
 8001a66:	2bee      	cmp	r3, #238	; 0xee
 8001a68:	d006      	beq.n	8001a78 <FirmwareUpdateStart+0x74>
 8001a6a:	2b0a      	cmp	r3, #10
 8001a6c:	d004      	beq.n	8001a78 <FirmwareUpdateStart+0x74>
        Uart1_Data_Send(&AckData_Buf[bluecell_stx],AckData_Buf[bluecell_length] + 3);
 8001a6e:	78a9      	ldrb	r1, [r5, #2]
 8001a70:	4628      	mov	r0, r5
 8001a72:	3103      	adds	r1, #3
 8001a74:	f000 fda6 	bl	80025c4 <Uart1_Data_Send>
    }
    if(data[bluecell_type] == 0xEE)
 8001a78:	7863      	ldrb	r3, [r4, #1]
 8001a7a:	2bee      	cmp	r3, #238	; 0xee
 8001a7c:	d10a      	bne.n	8001a94 <FirmwareUpdateStart+0x90>
        printf("update Complete \n");
}
 8001a7e:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
        printf("update Complete \n");
 8001a82:	4808      	ldr	r0, [pc, #32]	; (8001aa4 <FirmwareUpdateStart+0xa0>)
 8001a84:	f000 be74 	b.w	8002770 <puts>
            printf("%02x ",data[i]);
 8001a88:	5ce1      	ldrb	r1, [r4, r3]
 8001a8a:	4630      	mov	r0, r6
 8001a8c:	f000 fdfc 	bl	8002688 <iprintf>
 8001a90:	462b      	mov	r3, r5
 8001a92:	e7c4      	b.n	8001a1e <FirmwareUpdateStart+0x1a>
 8001a94:	bd70      	pop	{r4, r5, r6, pc}
 8001a96:	bf00      	nop
 8001a98:	080036fc 	.word	0x080036fc
 8001a9c:	08003702 	.word	0x08003702
 8001aa0:	20000008 	.word	0x20000008
 8001aa4:	08003713 	.word	0x08003713

08001aa8 <Chksum_Check>:
//-----------------------------------------------
//UART CRC üũ �Լ�
//-----------------------------------------------
bool Chksum_Check(uint8_t *data, uint32_t leng,uint8_t chkdata)
{
   uint8_t dataret = 0;
 8001aa8:	2300      	movs	r3, #0
{
 8001aaa:	b510      	push	{r4, lr}
 8001aac:	1cc1      	adds	r1, r0, #3
 8001aae:	3014      	adds	r0, #20
   bool ret = false;
   for(int i = MBIC_SUBUID_0; i < MBIC_HEADERCHECKSUM_0; i++){
        dataret += data[i];
 8001ab0:	f811 4f01 	ldrb.w	r4, [r1, #1]!
 8001ab4:	4423      	add	r3, r4
   for(int i = MBIC_SUBUID_0; i < MBIC_HEADERCHECKSUM_0; i++){
 8001ab6:	4281      	cmp	r1, r0
        dataret += data[i];
 8001ab8:	b2db      	uxtb	r3, r3
   for(int i = MBIC_SUBUID_0; i < MBIC_HEADERCHECKSUM_0; i++){
 8001aba:	d1f9      	bne.n	8001ab0 <Chksum_Check+0x8>
   if(dataret == chkdata){
        ret = true;
   }
//    printf("dataret : %x   chkdata : %x \r\n",dataret,chkdata);
    return ret;
}
 8001abc:	1a9b      	subs	r3, r3, r2
 8001abe:	4258      	negs	r0, r3
 8001ac0:	4158      	adcs	r0, r3
 8001ac2:	bd10      	pop	{r4, pc}

08001ac4 <Chksum_Create>:
uint8_t Chksum_Create(uint8_t *data)
{
 8001ac4:	1cc2      	adds	r2, r0, #3
 8001ac6:	f100 0314 	add.w	r3, r0, #20
   uint8_t dataret = 0;
 8001aca:	2000      	movs	r0, #0

   for(int i = MBIC_SUBUID_0; i < MBIC_HEADERCHECKSUM_0; i++){
        dataret += data[i];
 8001acc:	f812 1f01 	ldrb.w	r1, [r2, #1]!
 8001ad0:	4408      	add	r0, r1
   for(int i = MBIC_SUBUID_0; i < MBIC_HEADERCHECKSUM_0; i++){
 8001ad2:	429a      	cmp	r2, r3
        dataret += data[i];
 8001ad4:	b2c0      	uxtb	r0, r0
   for(int i = MBIC_SUBUID_0; i < MBIC_HEADERCHECKSUM_0; i++){
 8001ad6:	d1f9      	bne.n	8001acc <Chksum_Create+0x8>
//        printf("dataret : %x data[%d] : %x \r\n",dataret,i,data[i]);
   }
//    printf("dataret : %x \r\n",dataret);
    return dataret;
}
 8001ad8:	4770      	bx	lr
	...

08001adc <CRC16_Generate>:
{
	uint8_t dt = 0U;
	uint16_t crc16 = 0U;

	len *= 8;
	for(crc16 = (uint16_t)0x0000; len >= 8; len -= 8, buf_ptr++)
 8001adc:	2300      	movs	r3, #0
{
 8001ade:	b510      	push	{r4, lr}
	{
		crc16 = (uint16_t)(Table_CRC16[(crc16>>8) ^ (uint16_t)(*buf_ptr)] ^ (crc16<<8));
 8001ae0:	4c0f      	ldr	r4, [pc, #60]	; (8001b20 <CRC16_Generate+0x44>)
	len *= 8;
 8001ae2:	00c9      	lsls	r1, r1, #3
	for(crc16 = (uint16_t)0x0000; len >= 8; len -= 8, buf_ptr++)
 8001ae4:	2907      	cmp	r1, #7
 8001ae6:	dc0f      	bgt.n	8001b08 <CRC16_Generate+0x2c>
	}

	if(len != 0)
 8001ae8:	b161      	cbz	r1, 8001b04 <CRC16_Generate+0x28>
			len--;

			if(((crc16^dt) & ((uint16_t)1 << 15)) != 0)
			{
				crc16 =  (uint16_t)(crc16 << 1);
				crc16 = (uint16_t)(crc16 ^ 0x1021);
 8001aea:	f241 0221 	movw	r2, #4129	; 0x1021
			if(((crc16^dt) & ((uint16_t)1 << 15)) != 0)
 8001aee:	f413 4f00 	tst.w	r3, #32768	; 0x8000
 8001af2:	ea4f 0343 	mov.w	r3, r3, lsl #1
				crc16 =  (uint16_t)(crc16 << 1);
 8001af6:	b29b      	uxth	r3, r3
			len--;
 8001af8:	f101 31ff 	add.w	r1, r1, #4294967295
				crc16 = (uint16_t)(crc16 ^ 0x1021);
 8001afc:	bf18      	it	ne
 8001afe:	4053      	eorne	r3, r2
		while(len != 0)
 8001b00:	2900      	cmp	r1, #0
 8001b02:	d1f4      	bne.n	8001aee <CRC16_Generate+0x12>
			}
			dt = (uint8_t)(dt << 1);
		}
	}
	return(crc16);
}
 8001b04:	4618      	mov	r0, r3
 8001b06:	bd10      	pop	{r4, pc}
		crc16 = (uint16_t)(Table_CRC16[(crc16>>8) ^ (uint16_t)(*buf_ptr)] ^ (crc16<<8));
 8001b08:	f810 2b01 	ldrb.w	r2, [r0], #1
	for(crc16 = (uint16_t)0x0000; len >= 8; len -= 8, buf_ptr++)
 8001b0c:	3908      	subs	r1, #8
		crc16 = (uint16_t)(Table_CRC16[(crc16>>8) ^ (uint16_t)(*buf_ptr)] ^ (crc16<<8));
 8001b0e:	ea82 2213 	eor.w	r2, r2, r3, lsr #8
 8001b12:	f834 2012 	ldrh.w	r2, [r4, r2, lsl #1]
 8001b16:	ea82 2303 	eor.w	r3, r2, r3, lsl #8
 8001b1a:	b29b      	uxth	r3, r3
 8001b1c:	e7e2      	b.n	8001ae4 <CRC16_Generate+0x8>
 8001b1e:	bf00      	nop
 8001b20:	20000014 	.word	0x20000014

08001b24 <CRC16_Check>:
{
	uint8_t dt = 0U;
	uint16_t crc16 = 0U;

	len *= 8;
	for(crc16 = (uint16_t)0x0000; len >= 8; len -= 8, buf_ptr++)
 8001b24:	2300      	movs	r3, #0
{
 8001b26:	b530      	push	{r4, r5, lr}
	{
		crc16 = (uint16_t)(Table_CRC16[(crc16>>8) ^ (uint16_t)(*buf_ptr)] ^ (crc16<<8));
 8001b28:	4d10      	ldr	r5, [pc, #64]	; (8001b6c <CRC16_Check+0x48>)
	len *= 8;
 8001b2a:	00c9      	lsls	r1, r1, #3
	for(crc16 = (uint16_t)0x0000; len >= 8; len -= 8, buf_ptr++)
 8001b2c:	2907      	cmp	r1, #7
 8001b2e:	dc11      	bgt.n	8001b54 <CRC16_Check+0x30>

	}

	if(len != 0)
 8001b30:	b161      	cbz	r1, 8001b4c <CRC16_Check+0x28>
			len--;

			if(((crc16^dt) & ((uint16_t)1 << 15)) != 0)
			{
				crc16 =  (uint16_t)(crc16 << 1);
				crc16 = (uint16_t)(crc16 ^ 0x1021);
 8001b32:	f241 0021 	movw	r0, #4129	; 0x1021
			if(((crc16^dt) & ((uint16_t)1 << 15)) != 0)
 8001b36:	f413 4f00 	tst.w	r3, #32768	; 0x8000
 8001b3a:	ea4f 0343 	mov.w	r3, r3, lsl #1
				crc16 =  (uint16_t)(crc16 << 1);
 8001b3e:	b29b      	uxth	r3, r3
			len--;
 8001b40:	f101 31ff 	add.w	r1, r1, #4294967295
				crc16 = (uint16_t)(crc16 ^ 0x1021);
 8001b44:	bf18      	it	ne
 8001b46:	4043      	eorne	r3, r0
		while(len != 0)
 8001b48:	2900      	cmp	r1, #0
 8001b4a:	d1f4      	bne.n	8001b36 <CRC16_Check+0x12>
			}
			dt = (uint8_t)(dt << 1);
		}
	}
	return(crc16 == checksum ? CHECKSUM_ERROR : NO_ERROR );
}
 8001b4c:	1a98      	subs	r0, r3, r2
 8001b4e:	bf18      	it	ne
 8001b50:	2001      	movne	r0, #1
 8001b52:	bd30      	pop	{r4, r5, pc}
		crc16 = (uint16_t)(Table_CRC16[(crc16>>8) ^ (uint16_t)(*buf_ptr)] ^ (crc16<<8));
 8001b54:	f810 4b01 	ldrb.w	r4, [r0], #1
	for(crc16 = (uint16_t)0x0000; len >= 8; len -= 8, buf_ptr++)
 8001b58:	3908      	subs	r1, #8
		crc16 = (uint16_t)(Table_CRC16[(crc16>>8) ^ (uint16_t)(*buf_ptr)] ^ (crc16<<8));
 8001b5a:	ea84 2413 	eor.w	r4, r4, r3, lsr #8
 8001b5e:	f835 4014 	ldrh.w	r4, [r5, r4, lsl #1]
 8001b62:	ea84 2303 	eor.w	r3, r4, r3, lsl #8
 8001b66:	b29b      	uxth	r3, r3
 8001b68:	e7e0      	b.n	8001b2c <CRC16_Check+0x8>
 8001b6a:	bf00      	nop
 8001b6c:	20000014 	.word	0x20000014

08001b70 <STH30_CreateCrc>:

uint8_t STH30_CreateCrc(uint8_t *data, uint8_t nbrOfBytes)
{
 8001b70:	b510      	push	{r4, lr}
  uint8_t bit;        // bit mask
  uint8_t crc = 0xFF; // calculated checksum
 8001b72:	23ff      	movs	r3, #255	; 0xff
  uint8_t byteCtr;    // byte counter

  // calculates 8-Bit checksum with given polynomial
  for(byteCtr = 0; byteCtr < nbrOfBytes; byteCtr++)
 8001b74:	4604      	mov	r4, r0
 8001b76:	1a22      	subs	r2, r4, r0
 8001b78:	b2d2      	uxtb	r2, r2
 8001b7a:	4291      	cmp	r1, r2
 8001b7c:	d801      	bhi.n	8001b82 <STH30_CreateCrc+0x12>
      if(crc & 0x80) crc = (crc << 1) ^ POLYNOMIAL;
      else           crc = (crc << 1);
    }
  }
  return crc;
}
 8001b7e:	4618      	mov	r0, r3
 8001b80:	bd10      	pop	{r4, pc}
    crc ^= (data[byteCtr]);
 8001b82:	f814 2b01 	ldrb.w	r2, [r4], #1
 8001b86:	4053      	eors	r3, r2
 8001b88:	2208      	movs	r2, #8
      if(crc & 0x80) crc = (crc << 1) ^ POLYNOMIAL;
 8001b8a:	f013 0f80 	tst.w	r3, #128	; 0x80
 8001b8e:	f102 32ff 	add.w	r2, r2, #4294967295
 8001b92:	ea4f 0343 	mov.w	r3, r3, lsl #1
 8001b96:	bf18      	it	ne
 8001b98:	f083 0331 	eorne.w	r3, r3, #49	; 0x31
    for(bit = 8; bit > 0; --bit)
 8001b9c:	f012 02ff 	ands.w	r2, r2, #255	; 0xff
      else           crc = (crc << 1);
 8001ba0:	b2db      	uxtb	r3, r3
    for(bit = 8; bit > 0; --bit)
 8001ba2:	d1f2      	bne.n	8001b8a <STH30_CreateCrc+0x1a>
 8001ba4:	e7e7      	b.n	8001b76 <STH30_CreateCrc+0x6>

08001ba6 <STH30_CheckCrc>:
etError STH30_CheckCrc(uint8_t *data, uint8_t nbrOfBytes, uint8_t checksum)
{
 8001ba6:	b530      	push	{r4, r5, lr}
  uint8_t bit;        // bit mask
  uint8_t crc = 0xFF; // calculated checksum
 8001ba8:	23ff      	movs	r3, #255	; 0xff
  uint8_t byteCtr;    // byte counter

  // calculates 8-Bit checksum with given polynomial
  for(byteCtr = 0; byteCtr < nbrOfBytes; byteCtr++)
 8001baa:	4605      	mov	r5, r0
 8001bac:	1a2c      	subs	r4, r5, r0
 8001bae:	b2e4      	uxtb	r4, r4
 8001bb0:	42a1      	cmp	r1, r4
 8001bb2:	d803      	bhi.n	8001bbc <STH30_CheckCrc+0x16>
      else           crc = (crc << 1);
    }
  }
  if(crc != checksum) return CHECKSUM_ERROR;
  else                return NO_ERROR;
}
 8001bb4:	1a9b      	subs	r3, r3, r2
 8001bb6:	4258      	negs	r0, r3
 8001bb8:	4158      	adcs	r0, r3
 8001bba:	bd30      	pop	{r4, r5, pc}
    crc ^= (data[byteCtr]);
 8001bbc:	f815 4b01 	ldrb.w	r4, [r5], #1
 8001bc0:	4063      	eors	r3, r4
 8001bc2:	2408      	movs	r4, #8
      if(crc & 0x80) crc = (crc << 1) ^ POLYNOMIAL;
 8001bc4:	f013 0f80 	tst.w	r3, #128	; 0x80
 8001bc8:	f104 34ff 	add.w	r4, r4, #4294967295
 8001bcc:	ea4f 0343 	mov.w	r3, r3, lsl #1
 8001bd0:	bf18      	it	ne
 8001bd2:	f083 0331 	eorne.w	r3, r3, #49	; 0x31
    for(bit = 8; bit > 0; --bit)
 8001bd6:	f014 04ff 	ands.w	r4, r4, #255	; 0xff
      else           crc = (crc << 1);
 8001bda:	b2db      	uxtb	r3, r3
    for(bit = 8; bit > 0; --bit)
 8001bdc:	d1f2      	bne.n	8001bc4 <STH30_CheckCrc+0x1e>
 8001bde:	e7e5      	b.n	8001bac <STH30_CheckCrc+0x6>

08001be0 <MBIC_HeaderMergeFunction>:
  Length : Response Data Length
  CRCINDEX : CRC INDEX Number

*/
uint8_t* MBIC_HeaderMergeFunction(uint8_t* data,uint16_t Length )
{
 8001be0:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
    uint8_t ret[Length + 22 + 3];/*Data Length + Header Length + Tail Length*/
 8001be4:	f101 0320 	add.w	r3, r1, #32
 8001be8:	f023 0307 	bic.w	r3, r3, #7
{
 8001bec:	af00      	add	r7, sp, #0
    uint8_t ret[Length + 22 + 3];/*Data Length + Header Length + Tail Length*/
 8001bee:	ebad 0d03 	sub.w	sp, sp, r3
{
 8001bf2:	4604      	mov	r4, r0
 8001bf4:	460e      	mov	r6, r1
    uint16_t CRCData = CRC16_Generate(data,Length);
 8001bf6:	f7ff ff71 	bl	8001adc <CRC16_Generate>
    /*CRC Create*/
    ret[MBIC_PAYLOADSTART + Length + 0] = ((CRCData & 0xFF00) >> 8);
 8001bfa:	eb0d 0306 	add.w	r3, sp, r6
 8001bfe:	0a02      	lsrs	r2, r0, #8
 8001c00:	759a      	strb	r2, [r3, #22]
    ret[MBIC_PAYLOADSTART + Length + 1] = ((CRCData & 0x00FF));
    ret[MBIC_PAYLOADSTART + Length + 2] = 0x03;
 8001c02:	2203      	movs	r2, #3
    ret[MBIC_PAYLOADSTART + Length + 1] = ((CRCData & 0x00FF));
 8001c04:	75d8      	strb	r0, [r3, #23]
    ret[MBIC_PAYLOADSTART + Length + 2] = 0x03;
 8001c06:	761a      	strb	r2, [r3, #24]
    /*Data Mark Create*/
    ret[MBIC_PREAMBLE_0] = MBIC_PREAMBLE0;
 8001c08:	2316      	movs	r3, #22
 8001c0a:	f88d 3000 	strb.w	r3, [sp]
    ret[MBIC_PREAMBLE_1] = MBIC_PREAMBLE1;
 8001c0e:	f88d 3001 	strb.w	r3, [sp, #1]
    ret[MBIC_PREAMBLE_2] = MBIC_PREAMBLE2;
 8001c12:	f88d 3002 	strb.w	r3, [sp, #2]
    ret[MBIC_PREAMBLE_3] = MBIC_PREAMBLE3;
 8001c16:	f88d 3003 	strb.w	r3, [sp, #3]
    /*Data Subid Create*/
    ret[MBIC_SUBUID_0] = MBIC_SUBUID0;
    ret[MBIC_SUBUID_1] = MBIC_SUBUID1;
 8001c1a:	23f1      	movs	r3, #241	; 0xf1
    ret[MBIC_SUBUID_0] = MBIC_SUBUID0;
 8001c1c:	2500      	movs	r5, #0
    ret[MBIC_SUBUID_1] = MBIC_SUBUID1;
 8001c1e:	f88d 3005 	strb.w	r3, [sp, #5]

    ret[MBIC_RCODE_0] = data[MBIC_RCODE_0];
 8001c22:	79a3      	ldrb	r3, [r4, #6]
        

    ret[MBIC_LENGTH_0] = (Length & 0xFF00) << 8;
    ret[MBIC_LENGTH_1] = Length & 0x00FF;

    ret[MBIC_HEADERCHECKSUM_0] = Chksum_Create(ret);
 8001c24:	4668      	mov	r0, sp
    ret[MBIC_RCODE_0] = data[MBIC_RCODE_0];
 8001c26:	f88d 3006 	strb.w	r3, [sp, #6]
    ret[MBIC_TRID_0] = data[MBIC_TRID_0];
 8001c2a:	79e3      	ldrb	r3, [r4, #7]
    ret[MBIC_SUBUID_0] = MBIC_SUBUID0;
 8001c2c:	f88d 5004 	strb.w	r5, [sp, #4]
    ret[MBIC_TRID_0] = data[MBIC_TRID_0];
 8001c30:	f88d 3007 	strb.w	r3, [sp, #7]
    ret[MBIC_TRID_1] = data[MBIC_TRID_1];
 8001c34:	7a23      	ldrb	r3, [r4, #8]
    ret[MBIC_ERRRESPONSE_0] = MBIC_ERRRESPONSE;
 8001c36:	f88d 5011 	strb.w	r5, [sp, #17]
    ret[MBIC_TRID_1] = data[MBIC_TRID_1];
 8001c3a:	f88d 3008 	strb.w	r3, [sp, #8]
    ret[MBIC_SEQSUM_0] = data[MBIC_SEQSUM_0];
 8001c3e:	7a63      	ldrb	r3, [r4, #9]
    uint8_t ret[Length + 22 + 3];/*Data Length + Header Length + Tail Length*/
 8001c40:	46e8      	mov	r8, sp
    ret[MBIC_SEQSUM_0] = data[MBIC_SEQSUM_0];
 8001c42:	f88d 3009 	strb.w	r3, [sp, #9]
    ret[MBIC_TTL_0] = data[MBIC_TTL_0];
 8001c46:	7aa3      	ldrb	r3, [r4, #10]
 8001c48:	f88d 300a 	strb.w	r3, [sp, #10]
    ret[MBIC_TIME_0] = data[MBIC_TIME_0];
 8001c4c:	7ae3      	ldrb	r3, [r4, #11]
 8001c4e:	f88d 300b 	strb.w	r3, [sp, #11]
    ret[MBIC_TIME_1] = data[MBIC_TIME_1];
 8001c52:	7b23      	ldrb	r3, [r4, #12]
 8001c54:	f88d 300c 	strb.w	r3, [sp, #12]
    ret[MBIC_TIME_2] = data[MBIC_TIME_2];
 8001c58:	7b63      	ldrb	r3, [r4, #13]
 8001c5a:	f88d 300d 	strb.w	r3, [sp, #13]
    ret[MBIC_TIME_3] = data[MBIC_TIME_3];
 8001c5e:	7ba3      	ldrb	r3, [r4, #14]
 8001c60:	f88d 300e 	strb.w	r3, [sp, #14]
    ret[MBIC_TIME_4] = data[MBIC_TIME_4];
 8001c64:	7be3      	ldrb	r3, [r4, #15]
 8001c66:	f88d 300f 	strb.w	r3, [sp, #15]
    ret[MBIC_TIME_5] = data[MBIC_TIME_5];
 8001c6a:	7c23      	ldrb	r3, [r4, #16]
 8001c6c:	f88d 3010 	strb.w	r3, [sp, #16]
    ret[MBIC_LENGTH_0] = (Length & 0xFF00) << 8;
 8001c70:	f88d 5013 	strb.w	r5, [sp, #19]
    ret[MBIC_LENGTH_1] = Length & 0x00FF;
 8001c74:	f88d 6014 	strb.w	r6, [sp, #20]
    ret[MBIC_HEADERCHECKSUM_0] = Chksum_Create(ret);
 8001c78:	f7ff ff24 	bl	8001ac4 <Chksum_Create>
//        data[MBIC_PAYLOADSTART + i] = data[i];
//    }
    /*
        MBIC Header Data input
    */
    for(int i = 0; i < MBIC_HEADER_SIZE; i++){
 8001c7c:	462b      	mov	r3, r5
    ret[MBIC_HEADERCHECKSUM_0] = Chksum_Create(ret);
 8001c7e:	f88d 0015 	strb.w	r0, [sp, #21]
        if(i == MBIC_CMD_0) /*cmd exception*/
 8001c82:	2b12      	cmp	r3, #18
            continue;
        data[i] = ret[i];
 8001c84:	bf1c      	itt	ne
 8001c86:	f818 2003 	ldrbne.w	r2, [r8, r3]
 8001c8a:	54e2      	strbne	r2, [r4, r3]
    for(int i = 0; i < MBIC_HEADER_SIZE; i++){
 8001c8c:	3301      	adds	r3, #1
 8001c8e:	2b16      	cmp	r3, #22
 8001c90:	d1f7      	bne.n	8001c82 <MBIC_HeaderMergeFunction+0xa2>
 8001c92:	2300      	movs	r3, #0
 8001c94:	3301      	adds	r3, #1
    }
      /*
          MBIC Tail Data input
      */
    
      for(int i = MBIC_HEADER_SIZE + Length; i < MBIC_HEADER_SIZE + MBIC_TAIL_SIZE + Length; i++){
 8001c96:	2b04      	cmp	r3, #4
 8001c98:	d103      	bne.n	8001ca2 <MBIC_HeaderMergeFunction+0xc2>
//        ret[MBIC_PAYLOADSTART + i] = data[i];
//    for(int i = 0; i < Length; i++)
//        printf("MBIC : %x \r\n",data[i]);

    return data;
}
 8001c9a:	4620      	mov	r0, r4
 8001c9c:	46bd      	mov	sp, r7
 8001c9e:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
        data[i] = ret[i];
 8001ca2:	199a      	adds	r2, r3, r6
 8001ca4:	18a1      	adds	r1, r4, r2
 8001ca6:	4442      	add	r2, r8
 8001ca8:	7d52      	ldrb	r2, [r2, #21]
 8001caa:	754a      	strb	r2, [r1, #21]
 8001cac:	e7f2      	b.n	8001c94 <MBIC_HeaderMergeFunction+0xb4>
	...

08001cb0 <MBIC_FirmwareFile_CrcCheck>:
/*
    MBIC CRC Check Function
*/
void MBIC_FirmwareFile_CrcCheck(void) 
{
 8001cb0:	b570      	push	{r4, r5, r6, lr}
    uint32_t  Address = 0;
    Address = FLASH_USER_START_ADDR - 128;
 8001cb2:	4c06      	ldr	r4, [pc, #24]	; (8001ccc <MBIC_FirmwareFile_CrcCheck+0x1c>)
    for(uint32_t i = 0; i < 300; i++ ){
        printf("%08x : %02X \n",Address ,*(uint8_t*)Address);
 8001cb4:	4e06      	ldr	r6, [pc, #24]	; (8001cd0 <MBIC_FirmwareFile_CrcCheck+0x20>)
    for(uint32_t i = 0; i < 300; i++ ){
 8001cb6:	4d07      	ldr	r5, [pc, #28]	; (8001cd4 <MBIC_FirmwareFile_CrcCheck+0x24>)
        printf("%08x : %02X \n",Address ,*(uint8_t*)Address);
 8001cb8:	7822      	ldrb	r2, [r4, #0]
 8001cba:	4621      	mov	r1, r4
 8001cbc:	4630      	mov	r0, r6
        Address++;
 8001cbe:	3401      	adds	r4, #1
        printf("%08x : %02X \n",Address ,*(uint8_t*)Address);
 8001cc0:	f000 fce2 	bl	8002688 <iprintf>
    for(uint32_t i = 0; i < 300; i++ ){
 8001cc4:	42ac      	cmp	r4, r5
 8001cc6:	d1f7      	bne.n	8001cb8 <MBIC_FirmwareFile_CrcCheck+0x8>
        printf("%02X ",*(uint8_t*)Address);
        Address++;
    }
#endif // PYJ.2019.03.27_END -- 

}
 8001cc8:	bd70      	pop	{r4, r5, r6, pc}
 8001cca:	bf00      	nop
 8001ccc:	08004f80 	.word	0x08004f80
 8001cd0:	08003724 	.word	0x08003724
 8001cd4:	080050ac 	.word	0x080050ac

08001cd8 <MBIC_Bootloader_FirmwareUpdate>:

void MBIC_Bootloader_FirmwareUpdate(uint8_t* data){
 8001cd8:	b510      	push	{r4, lr}
    

//    printf("RX");
//    for(int i = 0; i < 128; i++)
//        printf("%c",*data++);
    switch(cmd){
 8001cda:	7c83      	ldrb	r3, [r0, #18]
void MBIC_Bootloader_FirmwareUpdate(uint8_t* data){
 8001cdc:	4604      	mov	r4, r0
    switch(cmd){
 8001cde:	3b10      	subs	r3, #16
 8001ce0:	2b04      	cmp	r3, #4
 8001ce2:	d859      	bhi.n	8001d98 <MBIC_Bootloader_FirmwareUpdate+0xc0>
 8001ce4:	e8df f003 	tbb	[pc, r3]
 8001ce8:	3e311903 	.word	0x3e311903
 8001cec:	4b          	.byte	0x4b
 8001ced:	00          	.byte	0x00
            data[MBIC_PAYLOADSTART + index++] = data[MBIC_PAYLOADSTART + 3];        
            /*DOWNLOAD OPTION*/        
            data[MBIC_PAYLOADSTART + index++] = data[MBIC_PAYLOADSTART + 4];
            Download_Option = data[MBIC_PAYLOADSTART + 4];
            /*DOWNLOAD DELAY REQUEST*/
            data[MBIC_PAYLOADSTART + index++] = 3;
 8001cee:	2303      	movs	r3, #3
 8001cf0:	76c3      	strb	r3, [r0, #27]
            /*DOWNLOAD Reserve*/
            data[MBIC_PAYLOADSTART + index++] = 0;
 8001cf2:	2300      	movs	r3, #0
 8001cf4:	7703      	strb	r3, [r0, #28]
            data[MBIC_PAYLOADSTART + index++] = 0;
 8001cf6:	7743      	strb	r3, [r0, #29]
            data[MBIC_PAYLOADSTART + index++] = 0;
 8001cf8:	7783      	strb	r3, [r0, #30]
            data[MBIC_PAYLOADSTART + index++] = 0;
 8001cfa:	77c3      	strb	r3, [r0, #31]
            data[MBIC_PAYLOADSTART + index++] = 0;
 8001cfc:	f880 3020 	strb.w	r3, [r0, #32]
            data[MBIC_PAYLOADSTART + index++] = 0;      
 8001d00:	f880 3021 	strb.w	r3, [r0, #33]	; 0x21
            cmd = MBIC_Notice_RSP;
 8001d04:	2390      	movs	r3, #144	; 0x90
            data[MBIC_PAYLOADSTART + index++] = 0;          
            break;
        default:
            return;
    }
    data[MBIC_CMD_0] = cmd;
 8001d06:	74a3      	strb	r3, [r4, #18]
    
    data = MBIC_HeaderMergeFunction(data,index); // reponse
 8001d08:	210c      	movs	r1, #12
 8001d0a:	4620      	mov	r0, r4
 8001d0c:	f7ff ff68 	bl	8001be0 <MBIC_HeaderMergeFunction>
//	HAL_UART_Transmit_DMA(&huart1, data,22 + 3 + index);

    
    Uart1_Data_Send(data ,22 + 3 + index);
}
 8001d10:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
    Uart1_Data_Send(data ,22 + 3 + index);
 8001d14:	2125      	movs	r1, #37	; 0x25
 8001d16:	f000 bc55 	b.w	80025c4 <Uart1_Data_Send>
            Curr_Download_DataIndex += data[MBIC_PAYLOADSTART + 5] << 16;
 8001d1a:	7ec3      	ldrb	r3, [r0, #27]
            Curr_Download_DataIndex = data[MBIC_PAYLOADSTART  + 4] << 24;
 8001d1c:	7e82      	ldrb	r2, [r0, #26]
            Curr_Download_DataIndex += data[MBIC_PAYLOADSTART + 5] << 16;
 8001d1e:	041b      	lsls	r3, r3, #16
 8001d20:	eb03 6302 	add.w	r3, r3, r2, lsl #24
            Curr_Download_DataIndex += data[MBIC_PAYLOADSTART + 7];                        
 8001d24:	7f42      	ldrb	r2, [r0, #29]
            Bank_Flash_write(data,FLASH_USER_START_ADDR);
 8001d26:	491d      	ldr	r1, [pc, #116]	; (8001d9c <MBIC_Bootloader_FirmwareUpdate+0xc4>)
            Curr_Download_DataIndex += data[MBIC_PAYLOADSTART + 7];                        
 8001d28:	4413      	add	r3, r2
            Curr_Download_DataIndex += data[MBIC_PAYLOADSTART + 6] << 8;            
 8001d2a:	7f02      	ldrb	r2, [r0, #28]
            Curr_Download_DataIndex += data[MBIC_PAYLOADSTART + 7];                        
 8001d2c:	eb03 2302 	add.w	r3, r3, r2, lsl #8
 8001d30:	4a1b      	ldr	r2, [pc, #108]	; (8001da0 <MBIC_Bootloader_FirmwareUpdate+0xc8>)
 8001d32:	6013      	str	r3, [r2, #0]
            data[MBIC_PAYLOADSTART + index++] = 0;
 8001d34:	2300      	movs	r3, #0
 8001d36:	7783      	strb	r3, [r0, #30]
            data[MBIC_PAYLOADSTART + index++] = 0;
 8001d38:	77c3      	strb	r3, [r0, #31]
            data[MBIC_PAYLOADSTART + index++] = 0;
 8001d3a:	f880 3020 	strb.w	r3, [r0, #32]
            data[MBIC_PAYLOADSTART + index++] = 0;
 8001d3e:	f880 3021 	strb.w	r3, [r0, #33]	; 0x21
            Bank_Flash_write(data,FLASH_USER_START_ADDR);
 8001d42:	f000 f8cf 	bl	8001ee4 <Bank_Flash_write>
            cmd = MBIC_Download_DATA_RSP;
 8001d46:	2391      	movs	r3, #145	; 0x91
            break;
 8001d48:	e7dd      	b.n	8001d06 <MBIC_Bootloader_FirmwareUpdate+0x2e>
            data[MBIC_PAYLOADSTART + index++] = 3;
 8001d4a:	2303      	movs	r3, #3
 8001d4c:	76c3      	strb	r3, [r0, #27]
            data[MBIC_PAYLOADSTART + index++] = 0;
 8001d4e:	2300      	movs	r3, #0
 8001d50:	7703      	strb	r3, [r0, #28]
            data[MBIC_PAYLOADSTART + index++] = 0;
 8001d52:	7743      	strb	r3, [r0, #29]
            data[MBIC_PAYLOADSTART + index++] = 0;
 8001d54:	7783      	strb	r3, [r0, #30]
            data[MBIC_PAYLOADSTART + index++] = 0;
 8001d56:	77c3      	strb	r3, [r0, #31]
            data[MBIC_PAYLOADSTART + index++] = 0;
 8001d58:	f880 3020 	strb.w	r3, [r0, #32]
            data[MBIC_PAYLOADSTART + index++] = 0;  
 8001d5c:	f880 3021 	strb.w	r3, [r0, #33]	; 0x21
            cmd = MBIC_Download_Confirm_RSP;
 8001d60:	2392      	movs	r3, #146	; 0x92
        break;
 8001d62:	e7d0      	b.n	8001d06 <MBIC_Bootloader_FirmwareUpdate+0x2e>
            data[MBIC_PAYLOADSTART + index++] = 3;
 8001d64:	2303      	movs	r3, #3
 8001d66:	76c3      	strb	r3, [r0, #27]
            data[MBIC_PAYLOADSTART + index++] = 0;
 8001d68:	2300      	movs	r3, #0
 8001d6a:	7703      	strb	r3, [r0, #28]
            data[MBIC_PAYLOADSTART + index++] = 0;
 8001d6c:	7743      	strb	r3, [r0, #29]
            data[MBIC_PAYLOADSTART + index++] = 0;
 8001d6e:	7783      	strb	r3, [r0, #30]
            data[MBIC_PAYLOADSTART + index++] = 0;
 8001d70:	77c3      	strb	r3, [r0, #31]
            data[MBIC_PAYLOADSTART + index++] = 0;
 8001d72:	f880 3020 	strb.w	r3, [r0, #32]
            data[MBIC_PAYLOADSTART + index++] = 0;  
 8001d76:	f880 3021 	strb.w	r3, [r0, #33]	; 0x21
            cmd = MBIC_Complete_Notice_RSP;
 8001d7a:	2393      	movs	r3, #147	; 0x93
            break;
 8001d7c:	e7c3      	b.n	8001d06 <MBIC_Bootloader_FirmwareUpdate+0x2e>
            data[MBIC_PAYLOADSTART + index++] = 3;
 8001d7e:	2303      	movs	r3, #3
 8001d80:	76c3      	strb	r3, [r0, #27]
            data[MBIC_PAYLOADSTART + index++] = 0;
 8001d82:	2300      	movs	r3, #0
 8001d84:	7703      	strb	r3, [r0, #28]
            data[MBIC_PAYLOADSTART + index++] = 0;
 8001d86:	7743      	strb	r3, [r0, #29]
            data[MBIC_PAYLOADSTART + index++] = 0;
 8001d88:	7783      	strb	r3, [r0, #30]
            data[MBIC_PAYLOADSTART + index++] = 0;
 8001d8a:	77c3      	strb	r3, [r0, #31]
            data[MBIC_PAYLOADSTART + index++] = 0;
 8001d8c:	f880 3020 	strb.w	r3, [r0, #32]
            data[MBIC_PAYLOADSTART + index++] = 0;          
 8001d90:	f880 3021 	strb.w	r3, [r0, #33]	; 0x21
            cmd = MBIC_Reboot_Notice_RSP;
 8001d94:	2394      	movs	r3, #148	; 0x94
            break;
 8001d96:	e7b6      	b.n	8001d06 <MBIC_Bootloader_FirmwareUpdate+0x2e>
 8001d98:	bd10      	pop	{r4, pc}
 8001d9a:	bf00      	nop
 8001d9c:	08005000 	.word	0x08005000
 8001da0:	2000029c 	.word	0x2000029c

08001da4 <Flash_RGB_Data_Write>:
#endif // PYJ.2019.03.27_END -- 

}

#if 1 // PYJ.2020.05.20_BEGIN -- 
uint8_t Flash_RGB_Data_Write(uint8_t* data){
 8001da4:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
 8001da8:	4605      	mov	r5, r0
    uint16_t Firmdata = 0;

    uint8_t ret = 0;
    for(int i = 0; i < data[bluecell_length] - 2; i+=2){
 8001daa:	4604      	mov	r4, r0
    uint8_t ret = 0;
 8001dac:	2700      	movs	r7, #0
        Firmdata  = ((data[(bluecell_length + 1) + i]) & 0x00FF);
        Firmdata  += ((data[(bluecell_length + 1) + (i + 1)] << 8) & 0xFF00);
        if(HAL_FLASH_Program(FLASH_TYPEPROGRAM_HALFWORD,Address ,   (uint16_t)Firmdata) != HAL_OK){
 8001dae:	4e0f      	ldr	r6, [pc, #60]	; (8001dec <Flash_RGB_Data_Write+0x48>)
            printf("HAL NOT OK \n");
 8001db0:	f8df 803c 	ldr.w	r8, [pc, #60]	; 8001df0 <Flash_RGB_Data_Write+0x4c>
    for(int i = 0; i < data[bluecell_length] - 2; i+=2){
 8001db4:	78ab      	ldrb	r3, [r5, #2]
 8001db6:	1b62      	subs	r2, r4, r5
 8001db8:	3b02      	subs	r3, #2
 8001dba:	4293      	cmp	r3, r2
 8001dbc:	dc02      	bgt.n	8001dc4 <Flash_RGB_Data_Write+0x20>
        Address += 2;
        //if(!(i%FirmwareUpdateDelay))
      //  HAL_Delay(1);
    }
    return ret;
}
 8001dbe:	4638      	mov	r0, r7
 8001dc0:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
        Firmdata  += ((data[(bluecell_length + 1) + (i + 1)] << 8) & 0xFF00);
 8001dc4:	7923      	ldrb	r3, [r4, #4]
        Firmdata  = ((data[(bluecell_length + 1) + i]) & 0x00FF);
 8001dc6:	78e2      	ldrb	r2, [r4, #3]
        if(HAL_FLASH_Program(FLASH_TYPEPROGRAM_HALFWORD,Address ,   (uint16_t)Firmdata) != HAL_OK){
 8001dc8:	6831      	ldr	r1, [r6, #0]
        Firmdata  += ((data[(bluecell_length + 1) + (i + 1)] << 8) & 0xFF00);
 8001dca:	eb02 2203 	add.w	r2, r2, r3, lsl #8
        if(HAL_FLASH_Program(FLASH_TYPEPROGRAM_HALFWORD,Address ,   (uint16_t)Firmdata) != HAL_OK){
 8001dce:	b292      	uxth	r2, r2
 8001dd0:	2300      	movs	r3, #0
 8001dd2:	2001      	movs	r0, #1
 8001dd4:	f7fe fd2a 	bl	800082c <HAL_FLASH_Program>
 8001dd8:	b118      	cbz	r0, 8001de2 <Flash_RGB_Data_Write+0x3e>
            printf("HAL NOT OK \n");
 8001dda:	4640      	mov	r0, r8
 8001ddc:	f000 fcc8 	bl	8002770 <puts>
            ret = 1;
 8001de0:	2701      	movs	r7, #1
        Address += 2;
 8001de2:	6833      	ldr	r3, [r6, #0]
 8001de4:	3402      	adds	r4, #2
 8001de6:	3302      	adds	r3, #2
 8001de8:	6033      	str	r3, [r6, #0]
 8001dea:	e7e3      	b.n	8001db4 <Flash_RGB_Data_Write+0x10>
 8001dec:	20000214 	.word	0x20000214
 8001df0:	08003732 	.word	0x08003732

08001df4 <Flash_Data_Write>:
uint8_t Flash_Data_Write(uint8_t* data){
 8001df4:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
    uint16_t Firmdata = 0;
    uint8_t ret = 0;
    int i = 0;
 8001df8:	2400      	movs	r4, #0
    Curr_Download_DataIndex += data[MBIC_PAYLOADSTART + 7];      

//    data[MBIC_PAYLOADSTART + 12 +i];
   
    returntoFirst:
    UserAddress -= i;
 8001dfa:	4f21      	ldr	r7, [pc, #132]	; (8001e80 <Flash_Data_Write+0x8c>)
uint8_t Flash_Data_Write(uint8_t* data){
 8001dfc:	4605      	mov	r5, r0
    uint8_t ret = 0;
 8001dfe:	46a0      	mov	r8, r4
 8001e00:	46ba      	mov	sl, r7
    Curr_Download_DataIndex += data[MBIC_PAYLOADSTART + 5] << 16;
 8001e02:	7ec3      	ldrb	r3, [r0, #27]
    Curr_Download_DataIndex = data[MBIC_PAYLOADSTART  + 4] << 24;
 8001e04:	7e82      	ldrb	r2, [r0, #26]
    Curr_Download_DataIndex += data[MBIC_PAYLOADSTART + 5] << 16;
 8001e06:	041b      	lsls	r3, r3, #16
 8001e08:	eb03 6302 	add.w	r3, r3, r2, lsl #24
    Curr_Download_DataIndex += data[MBIC_PAYLOADSTART + 7];      
 8001e0c:	7f42      	ldrb	r2, [r0, #29]
 8001e0e:	4e1d      	ldr	r6, [pc, #116]	; (8001e84 <Flash_Data_Write+0x90>)
 8001e10:	4413      	add	r3, r2
    Curr_Download_DataIndex += data[MBIC_PAYLOADSTART + 6] << 8;            
 8001e12:	7f02      	ldrb	r2, [r0, #28]
    for(i= 0; i <= Curr_Download_DataIndex - Prev_Download_DataIndex; i+=2){
 8001e14:	f8df 9074 	ldr.w	r9, [pc, #116]	; 8001e8c <Flash_Data_Write+0x98>
    Curr_Download_DataIndex += data[MBIC_PAYLOADSTART + 7];      
 8001e18:	eb03 2302 	add.w	r3, r3, r2, lsl #8
 8001e1c:	6033      	str	r3, [r6, #0]
    UserAddress -= i;
 8001e1e:	683b      	ldr	r3, [r7, #0]
 8001e20:	1b1c      	subs	r4, r3, r4
 8001e22:	603c      	str	r4, [r7, #0]
    for(i= 0; i <= Curr_Download_DataIndex - Prev_Download_DataIndex; i+=2){
 8001e24:	2400      	movs	r4, #0
 8001e26:	6833      	ldr	r3, [r6, #0]
 8001e28:	f8d9 2000 	ldr.w	r2, [r9]
 8001e2c:	1a9a      	subs	r2, r3, r2
 8001e2e:	42a2      	cmp	r2, r4
 8001e30:	d205      	bcs.n	8001e3e <Flash_Data_Write+0x4a>
            goto returntoFirst;
        }else{
            UserAddress += 2;
        }
    }
    Prev_Download_DataIndex = Curr_Download_DataIndex + 1;
 8001e32:	3301      	adds	r3, #1
 8001e34:	f8c9 3000 	str.w	r3, [r9]
    return ret;
}
 8001e38:	4640      	mov	r0, r8
 8001e3a:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 8001e3e:	192b      	adds	r3, r5, r4
        Firmdata  = ((data[MBIC_PAYLOADSTART + 12 +i]) & 0x00FF);
 8001e40:	f893 2022 	ldrb.w	r2, [r3, #34]	; 0x22
        Firmdata  += ((data[MBIC_PAYLOADSTART + 12 +i + 1] << 8) & 0xFF00);
 8001e44:	f893 3023 	ldrb.w	r3, [r3, #35]	; 0x23
        if(HAL_FLASH_Program(FLASH_TYPEPROGRAM_HALFWORD,UserAddress ,   (uint16_t)Firmdata) != HAL_OK){
 8001e48:	f8da 1000 	ldr.w	r1, [sl]
        Firmdata  += ((data[MBIC_PAYLOADSTART + 12 +i + 1] << 8) & 0xFF00);
 8001e4c:	eb02 2203 	add.w	r2, r2, r3, lsl #8
        if(HAL_FLASH_Program(FLASH_TYPEPROGRAM_HALFWORD,UserAddress ,   (uint16_t)Firmdata) != HAL_OK){
 8001e50:	b292      	uxth	r2, r2
 8001e52:	2300      	movs	r3, #0
 8001e54:	2001      	movs	r0, #1
 8001e56:	f7fe fce9 	bl	800082c <HAL_FLASH_Program>
 8001e5a:	b148      	cbz	r0, 8001e70 <Flash_Data_Write+0x7c>
            printf("HAL NOT OK \n");
 8001e5c:	480a      	ldr	r0, [pc, #40]	; (8001e88 <Flash_Data_Write+0x94>)
 8001e5e:	f000 fc87 	bl	8002770 <puts>
            HAL_Delay(1000);
 8001e62:	f44f 707a 	mov.w	r0, #1000	; 0x3e8
 8001e66:	f7fe fa31 	bl	80002cc <HAL_Delay>
            ret = 1;
 8001e6a:	f04f 0801 	mov.w	r8, #1
            goto returntoFirst;
 8001e6e:	e7d6      	b.n	8001e1e <Flash_Data_Write+0x2a>
            UserAddress += 2;
 8001e70:	f8da 3000 	ldr.w	r3, [sl]
    for(i= 0; i <= Curr_Download_DataIndex - Prev_Download_DataIndex; i+=2){
 8001e74:	3402      	adds	r4, #2
            UserAddress += 2;
 8001e76:	3302      	adds	r3, #2
 8001e78:	f8ca 3000 	str.w	r3, [sl]
 8001e7c:	e7d3      	b.n	8001e26 <Flash_Data_Write+0x32>
 8001e7e:	bf00      	nop
 8001e80:	200002d0 	.word	0x200002d0
 8001e84:	200002a0 	.word	0x200002a0
 8001e88:	08003732 	.word	0x08003732
 8001e8c:	200002cc 	.word	0x200002cc

08001e90 <Flash_write>:
    return ret;
}


uint8_t Flash_write(uint8_t* data) // ?占쏙옙湲고븿?占쏙옙
{
 8001e90:	b538      	push	{r3, r4, r5, lr}
    /*Variable used for Erase procedure*/
    static FLASH_EraseInitTypeDef EraseInitStruct;
    static uint32_t PAGEError = 0;
    uint8_t ret = 0;
    /* Fill EraseInit structure*/
    EraseInitStruct.TypeErase   = FLASH_TYPEERASE_PAGES;
 8001e92:	2300      	movs	r3, #0
 8001e94:	4c0e      	ldr	r4, [pc, #56]	; (8001ed0 <Flash_write+0x40>)
{
 8001e96:	4605      	mov	r5, r0
    EraseInitStruct.TypeErase   = FLASH_TYPEERASE_PAGES;
 8001e98:	6023      	str	r3, [r4, #0]
    EraseInitStruct.PageAddress = FLASH_USER_START_ADDR;
 8001e9a:	4b0e      	ldr	r3, [pc, #56]	; (8001ed4 <Flash_write+0x44>)
 8001e9c:	60a3      	str	r3, [r4, #8]
    EraseInitStruct.NbPages     = (FLASH_USER_END_ADDR - FLASH_USER_START_ADDR) / FLASH_PAGE_SIZE;
 8001e9e:	231f      	movs	r3, #31
 8001ea0:	60e3      	str	r3, [r4, #12]

//    __HAL_RCC_TIM6_CLK_DISABLE(); // 留ㅼ씤???占쏙옙癒몌옙?? ?占쏙옙占�??占쏙옙?占쏙옙?占쏙옙
    HAL_FLASH_Unlock(); // lock ??占�?
 8001ea2:	f7fe fc7d 	bl	80007a0 <HAL_FLASH_Unlock>
    if(flashinit == 0){
 8001ea6:	4b0c      	ldr	r3, [pc, #48]	; (8001ed8 <Flash_write+0x48>)
 8001ea8:	781a      	ldrb	r2, [r3, #0]
 8001eaa:	b94a      	cbnz	r2, 8001ec0 <Flash_write+0x30>
        flashinit= 1;
 8001eac:	2201      	movs	r2, #1
        //FLASH_PageErase(StartAddr);
        if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK){
 8001eae:	490b      	ldr	r1, [pc, #44]	; (8001edc <Flash_write+0x4c>)
 8001eb0:	4620      	mov	r0, r4
        flashinit= 1;
 8001eb2:	701a      	strb	r2, [r3, #0]
        if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK){
 8001eb4:	f7fe fd24 	bl	8000900 <HAL_FLASHEx_Erase>
 8001eb8:	b110      	cbz	r0, 8001ec0 <Flash_write+0x30>
            printf("Erase Failed \r\n");
 8001eba:	4809      	ldr	r0, [pc, #36]	; (8001ee0 <Flash_write+0x50>)
 8001ebc:	f000 fc58 	bl	8002770 <puts>
        }
    }
//    FLASH_If_Erase();
    ret = Flash_RGB_Data_Write(&data[bluecell_stx]);
 8001ec0:	4628      	mov	r0, r5
 8001ec2:	f7ff ff6f 	bl	8001da4 <Flash_RGB_Data_Write>
 8001ec6:	4604      	mov	r4, r0
//    ret = Flash_DataTest_Write(&data[bluecell_stx]);

    HAL_FLASH_Lock(); // lock ?占쏙옙洹멸린
 8001ec8:	f7fe fc7c 	bl	80007c4 <HAL_FLASH_Lock>
//    __HAL_RCC_TIM6_CLK_ENABLE(); // 留ㅼ씤???占쏙옙癒몌옙?? ?占쏙옙?占쏙옙?占쏙옙?占쏙옙?占쏙옙?占쏙옙

    return ret;
}
 8001ecc:	4620      	mov	r0, r4
 8001ece:	bd38      	pop	{r3, r4, r5, pc}
 8001ed0:	200002a4 	.word	0x200002a4
 8001ed4:	08005000 	.word	0x08005000
 8001ed8:	200002d4 	.word	0x200002d4
 8001edc:	200002c4 	.word	0x200002c4
 8001ee0:	0800373e 	.word	0x0800373e

08001ee4 <Bank_Flash_write>:


uint8_t Bank_Flash_write(uint8_t* data,uint32_t StartBankAddress) // ?占쏙옙湲고븿?占쏙옙
{
 8001ee4:	b538      	push	{r3, r4, r5, lr}
 8001ee6:	4605      	mov	r5, r0
 8001ee8:	460c      	mov	r4, r1
    static FLASH_EraseInitTypeDef EraseInitStruct;
    static uint32_t PAGEError = 0;
    uint8_t ret = 0;


    HAL_FLASH_Unlock(); // lock ??占�?
 8001eea:	f7fe fc59 	bl	80007a0 <HAL_FLASH_Unlock>
    if(flashinit == 0){
 8001eee:	4b1e      	ldr	r3, [pc, #120]	; (8001f68 <Bank_Flash_write+0x84>)
 8001ef0:	781a      	ldrb	r2, [r3, #0]
 8001ef2:	b9a2      	cbnz	r2, 8001f1e <Bank_Flash_write+0x3a>
        
        flashinit= 1;
 8001ef4:	2101      	movs	r1, #1
 8001ef6:	7019      	strb	r1, [r3, #0]
        /* Fill EraseInit structure*/
        switch(StartBankAddress){
 8001ef8:	4b1c      	ldr	r3, [pc, #112]	; (8001f6c <Bank_Flash_write+0x88>)
 8001efa:	429c      	cmp	r4, r3
 8001efc:	4b1c      	ldr	r3, [pc, #112]	; (8001f70 <Bank_Flash_write+0x8c>)
 8001efe:	d028      	beq.n	8001f52 <Bank_Flash_write+0x6e>
 8001f00:	d815      	bhi.n	8001f2e <Bank_Flash_write+0x4a>
 8001f02:	491c      	ldr	r1, [pc, #112]	; (8001f74 <Bank_Flash_write+0x90>)
 8001f04:	428c      	cmp	r4, r1
 8001f06:	d01e      	beq.n	8001f46 <Bank_Flash_write+0x62>
                EraseInitStruct.NbPages     = (FLASH_USER_END_ADDR - FLASH_USER_TEMPBANK_START_ADDR) / FLASH_PAGE_SIZE;
            break;

        }        
        
        UserAddress = EraseInitStruct.PageAddress;
 8001f08:	689a      	ldr	r2, [r3, #8]
 8001f0a:	4b1b      	ldr	r3, [pc, #108]	; (8001f78 <Bank_Flash_write+0x94>)
        //FLASH_PageErase(StartAddr);
        if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK){
 8001f0c:	491b      	ldr	r1, [pc, #108]	; (8001f7c <Bank_Flash_write+0x98>)
 8001f0e:	4818      	ldr	r0, [pc, #96]	; (8001f70 <Bank_Flash_write+0x8c>)
        UserAddress = EraseInitStruct.PageAddress;
 8001f10:	601a      	str	r2, [r3, #0]
        if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK){
 8001f12:	f7fe fcf5 	bl	8000900 <HAL_FLASHEx_Erase>
 8001f16:	b110      	cbz	r0, 8001f1e <Bank_Flash_write+0x3a>
            printf("Erase Failed \r\n");
 8001f18:	4819      	ldr	r0, [pc, #100]	; (8001f80 <Bank_Flash_write+0x9c>)
 8001f1a:	f000 fc29 	bl	8002770 <puts>
        }
    }
    ret = Flash_Data_Write(&data[MBIC_PREAMBLE_0]);
 8001f1e:	4628      	mov	r0, r5
 8001f20:	f7ff ff68 	bl	8001df4 <Flash_Data_Write>
 8001f24:	4604      	mov	r4, r0
    HAL_FLASH_Lock(); // lock ?占쏙옙洹멸린
 8001f26:	f7fe fc4d 	bl	80007c4 <HAL_FLASH_Lock>
    return ret;
}
 8001f2a:	4620      	mov	r0, r4
 8001f2c:	bd38      	pop	{r3, r4, r5, pc}
        switch(StartBankAddress){
 8001f2e:	4915      	ldr	r1, [pc, #84]	; (8001f84 <Bank_Flash_write+0xa0>)
 8001f30:	428c      	cmp	r4, r1
 8001f32:	d013      	beq.n	8001f5c <Bank_Flash_write+0x78>
 8001f34:	f501 3180 	add.w	r1, r1, #65536	; 0x10000
 8001f38:	428c      	cmp	r4, r1
 8001f3a:	d1e5      	bne.n	8001f08 <Bank_Flash_write+0x24>
                EraseInitStruct.TypeErase   = FLASH_TYPEERASE_PAGES;
 8001f3c:	601a      	str	r2, [r3, #0]
                EraseInitStruct.PageAddress = FLASH_USER_TEMPBANK_START_ADDR - 128;
 8001f3e:	4a12      	ldr	r2, [pc, #72]	; (8001f88 <Bank_Flash_write+0xa4>)
 8001f40:	609a      	str	r2, [r3, #8]
                EraseInitStruct.NbPages     = (FLASH_USER_END_ADDR - FLASH_USER_TEMPBANK_START_ADDR) / FLASH_PAGE_SIZE;
 8001f42:	4a12      	ldr	r2, [pc, #72]	; (8001f8c <Bank_Flash_write+0xa8>)
 8001f44:	e003      	b.n	8001f4e <Bank_Flash_write+0x6a>
                EraseInitStruct.TypeErase   = FLASH_TYPEERASE_PAGES;
 8001f46:	601a      	str	r2, [r3, #0]
                EraseInitStruct.PageAddress = FLASH_USER_START_ADDR - 128;
 8001f48:	4a11      	ldr	r2, [pc, #68]	; (8001f90 <Bank_Flash_write+0xac>)
 8001f4a:	609a      	str	r2, [r3, #8]
                EraseInitStruct.NbPages     = (FLASH_USER_END_ADDR - FLASH_USER_START_ADDR) / FLASH_PAGE_SIZE;
 8001f4c:	221f      	movs	r2, #31
                EraseInitStruct.NbPages     = (FLASH_USER_END_ADDR - FLASH_USER_TEMPBANK_START_ADDR) / FLASH_PAGE_SIZE;
 8001f4e:	60da      	str	r2, [r3, #12]
            break;
 8001f50:	e7da      	b.n	8001f08 <Bank_Flash_write+0x24>
                EraseInitStruct.TypeErase   = FLASH_TYPEERASE_PAGES;
 8001f52:	601a      	str	r2, [r3, #0]
                EraseInitStruct.PageAddress = FLASH_USER_BANK1_START_ADDR - 128;
 8001f54:	4a0f      	ldr	r2, [pc, #60]	; (8001f94 <Bank_Flash_write+0xb0>)
 8001f56:	609a      	str	r2, [r3, #8]
                EraseInitStruct.NbPages     = (FLASH_USER_END_ADDR - FLASH_USER_BANK1_START_ADDR) / FLASH_PAGE_SIZE;
 8001f58:	4a0f      	ldr	r2, [pc, #60]	; (8001f98 <Bank_Flash_write+0xb4>)
 8001f5a:	e7f8      	b.n	8001f4e <Bank_Flash_write+0x6a>
                EraseInitStruct.TypeErase   = FLASH_TYPEERASE_PAGES;
 8001f5c:	601a      	str	r2, [r3, #0]
                EraseInitStruct.PageAddress = FLASH_USER_BANK2_START_ADDR - 128;
 8001f5e:	4a0f      	ldr	r2, [pc, #60]	; (8001f9c <Bank_Flash_write+0xb8>)
 8001f60:	609a      	str	r2, [r3, #8]
                EraseInitStruct.NbPages     = (FLASH_USER_END_ADDR - FLASH_USER_BANK2_START_ADDR) / FLASH_PAGE_SIZE;
 8001f62:	4a0f      	ldr	r2, [pc, #60]	; (8001fa0 <Bank_Flash_write+0xbc>)
 8001f64:	e7f3      	b.n	8001f4e <Bank_Flash_write+0x6a>
 8001f66:	bf00      	nop
 8001f68:	200002d4 	.word	0x200002d4
 8001f6c:	08015000 	.word	0x08015000
 8001f70:	200002b4 	.word	0x200002b4
 8001f74:	08005000 	.word	0x08005000
 8001f78:	200002d0 	.word	0x200002d0
 8001f7c:	200002c8 	.word	0x200002c8
 8001f80:	0800373e 	.word	0x0800373e
 8001f84:	08025000 	.word	0x08025000
 8001f88:	08034f80 	.word	0x08034f80
 8001f8c:	001fffbf 	.word	0x001fffbf
 8001f90:	08004f80 	.word	0x08004f80
 8001f94:	08014f80 	.word	0x08014f80
 8001f98:	001fffff 	.word	0x001fffff
 8001f9c:	08024f80 	.word	0x08024f80
 8001fa0:	001fffdf 	.word	0x001fffdf

08001fa4 <HAL_TIM_PeriodElapsedCallback>:
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{

    if(htim->Instance == TIM6){
 8001fa4:	6802      	ldr	r2, [r0, #0]
 8001fa6:	4b08      	ldr	r3, [pc, #32]	; (8001fc8 <HAL_TIM_PeriodElapsedCallback+0x24>)
 8001fa8:	429a      	cmp	r2, r3
 8001faa:	d10b      	bne.n	8001fc4 <HAL_TIM_PeriodElapsedCallback+0x20>
        UartTimerCnt++;
 8001fac:	4a07      	ldr	r2, [pc, #28]	; (8001fcc <HAL_TIM_PeriodElapsedCallback+0x28>)
 8001fae:	6813      	ldr	r3, [r2, #0]
 8001fb0:	3301      	adds	r3, #1
 8001fb2:	6013      	str	r3, [r2, #0]
        LedTimerCnt++;
 8001fb4:	4a06      	ldr	r2, [pc, #24]	; (8001fd0 <HAL_TIM_PeriodElapsedCallback+0x2c>)
 8001fb6:	6813      	ldr	r3, [r2, #0]
 8001fb8:	3301      	adds	r3, #1
 8001fba:	6013      	str	r3, [r2, #0]
        FirmwareTimerCnt++;
 8001fbc:	4a05      	ldr	r2, [pc, #20]	; (8001fd4 <HAL_TIM_PeriodElapsedCallback+0x30>)
 8001fbe:	6813      	ldr	r3, [r2, #0]
 8001fc0:	3301      	adds	r3, #1
 8001fc2:	6013      	str	r3, [r2, #0]
 8001fc4:	4770      	bx	lr
 8001fc6:	bf00      	nop
 8001fc8:	40001000 	.word	0x40001000
 8001fcc:	200002e0 	.word	0x200002e0
 8001fd0:	200002dc 	.word	0x200002dc
 8001fd4:	200002d8 	.word	0x200002d8

08001fd8 <_write>:
    }
}
int _write (int file, uint8_t *ptr, uint16_t len)
{
 8001fd8:	b510      	push	{r4, lr}
 8001fda:	4614      	mov	r4, r2
    HAL_UART_Transmit (&huart1, ptr, len, 10);
 8001fdc:	230a      	movs	r3, #10
 8001fde:	4802      	ldr	r0, [pc, #8]	; (8001fe8 <_write+0x10>)
 8001fe0:	f7ff fb2a 	bl	8001638 <HAL_UART_Transmit>
    return len;
}
 8001fe4:	4620      	mov	r0, r4
 8001fe6:	bd10      	pop	{r4, pc}
 8001fe8:	200003f4 	.word	0x200003f4

08001fec <SystemClock_Config>:
/**
  * @brief System Clock Configuration
  * @retval None
  */
void SystemClock_Config(void)
{
 8001fec:	b510      	push	{r4, lr}
 8001fee:	b090      	sub	sp, #64	; 0x40
  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
 8001ff0:	2228      	movs	r2, #40	; 0x28
 8001ff2:	2100      	movs	r1, #0
 8001ff4:	a806      	add	r0, sp, #24
 8001ff6:	f000 fb3f 	bl	8002678 <memset>
  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 8001ffa:	2214      	movs	r2, #20
 8001ffc:	2100      	movs	r1, #0
 8001ffe:	a801      	add	r0, sp, #4
 8002000:	f000 fb3a 	bl	8002678 <memset>

  /** Initializes the CPU, AHB and APB busses clocks 
  */
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
 8002004:	2301      	movs	r3, #1
 8002006:	930a      	str	r3, [sp, #40]	; 0x28
  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
 8002008:	2310      	movs	r3, #16
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
 800200a:	2402      	movs	r4, #2
  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
 800200c:	930b      	str	r3, [sp, #44]	; 0x2c
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2;
  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL14;
 800200e:	f44f 1340 	mov.w	r3, #3145728	; 0x300000
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 8002012:	a806      	add	r0, sp, #24
  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL14;
 8002014:	930f      	str	r3, [sp, #60]	; 0x3c
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
 8002016:	9406      	str	r4, [sp, #24]
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
 8002018:	940d      	str	r4, [sp, #52]	; 0x34
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 800201a:	f7fe fe35 	bl	8000c88 <HAL_RCC_OscConfig>
  {
    Error_Handler();
  }
  /** Initializes the CPU, AHB and APB busses clocks 
  */
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
 800201e:	230f      	movs	r3, #15
                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
 8002020:	f44f 6280 	mov.w	r2, #1024	; 0x400
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
 8002024:	9301      	str	r3, [sp, #4]
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
 8002026:	2300      	movs	r3, #0
  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;

  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
 8002028:	4621      	mov	r1, r4
 800202a:	a801      	add	r0, sp, #4
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
 800202c:	9402      	str	r4, [sp, #8]
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
 800202e:	9303      	str	r3, [sp, #12]
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
 8002030:	9204      	str	r2, [sp, #16]
  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
 8002032:	9305      	str	r3, [sp, #20]
  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
 8002034:	f7fe fff0 	bl	8001018 <HAL_RCC_ClockConfig>
  {
    Error_Handler();
  }
}
 8002038:	b010      	add	sp, #64	; 0x40
 800203a:	bd10      	pop	{r4, pc}

0800203c <main>:
{
 800203c:	b580      	push	{r7, lr}
 800203e:	b088      	sub	sp, #32
  HAL_Init();
 8002040:	f7fe f920 	bl	8000284 <HAL_Init>
  SystemClock_Config();
 8002044:	f7ff ffd2 	bl	8001fec <SystemClock_Config>
  * @param None
  * @retval None
  */
static void MX_GPIO_Init(void)
{
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8002048:	2210      	movs	r2, #16

  /* GPIO Ports Clock Enable */
  __HAL_RCC_GPIOC_CLK_ENABLE();
 800204a:	4d5d      	ldr	r5, [pc, #372]	; (80021c0 <main+0x184>)
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 800204c:	2100      	movs	r1, #0
 800204e:	eb0d 0002 	add.w	r0, sp, r2
 8002052:	f000 fb11 	bl	8002678 <memset>
  __HAL_RCC_GPIOC_CLK_ENABLE();
 8002056:	69ab      	ldr	r3, [r5, #24]
  __HAL_RCC_GPIOB_CLK_ENABLE();
  __HAL_RCC_GPIOA_CLK_ENABLE();

  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(BOOT_LED_GPIO_Port, BOOT_LED_Pin, GPIO_PIN_RESET);
 8002058:	2200      	movs	r2, #0
  __HAL_RCC_GPIOC_CLK_ENABLE();
 800205a:	f043 0310 	orr.w	r3, r3, #16
 800205e:	61ab      	str	r3, [r5, #24]
 8002060:	69ab      	ldr	r3, [r5, #24]
  HAL_GPIO_WritePin(BOOT_LED_GPIO_Port, BOOT_LED_Pin, GPIO_PIN_RESET);
 8002062:	f44f 4100 	mov.w	r1, #32768	; 0x8000
  __HAL_RCC_GPIOC_CLK_ENABLE();
 8002066:	f003 0310 	and.w	r3, r3, #16
 800206a:	9301      	str	r3, [sp, #4]
 800206c:	9b01      	ldr	r3, [sp, #4]
  __HAL_RCC_GPIOB_CLK_ENABLE();
 800206e:	69ab      	ldr	r3, [r5, #24]
  HAL_GPIO_WritePin(BOOT_LED_GPIO_Port, BOOT_LED_Pin, GPIO_PIN_RESET);
 8002070:	4854      	ldr	r0, [pc, #336]	; (80021c4 <main+0x188>)
  __HAL_RCC_GPIOB_CLK_ENABLE();
 8002072:	f043 0308 	orr.w	r3, r3, #8
 8002076:	61ab      	str	r3, [r5, #24]
 8002078:	69ab      	ldr	r3, [r5, #24]

  /*Configure GPIO pin : BOOT_LED_Pin */
  GPIO_InitStruct.Pin = BOOT_LED_Pin;
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 800207a:	2400      	movs	r4, #0
  __HAL_RCC_GPIOB_CLK_ENABLE();
 800207c:	f003 0308 	and.w	r3, r3, #8
 8002080:	9302      	str	r3, [sp, #8]
 8002082:	9b02      	ldr	r3, [sp, #8]
  __HAL_RCC_GPIOA_CLK_ENABLE();
 8002084:	69ab      	ldr	r3, [r5, #24]
	  if(LedTimerCnt > 500){HAL_GPIO_TogglePin(BOOT_LED_GPIO_Port,BOOT_LED_Pin);LedTimerCnt = 0;}
 8002086:	4e4f      	ldr	r6, [pc, #316]	; (80021c4 <main+0x188>)
  __HAL_RCC_GPIOA_CLK_ENABLE();
 8002088:	f043 0304 	orr.w	r3, r3, #4
 800208c:	61ab      	str	r3, [r5, #24]
 800208e:	69ab      	ldr	r3, [r5, #24]
 8002090:	f003 0304 	and.w	r3, r3, #4
 8002094:	9303      	str	r3, [sp, #12]
 8002096:	9b03      	ldr	r3, [sp, #12]
  HAL_GPIO_WritePin(BOOT_LED_GPIO_Port, BOOT_LED_Pin, GPIO_PIN_RESET);
 8002098:	f7fe fd6c 	bl	8000b74 <HAL_GPIO_WritePin>
  GPIO_InitStruct.Pin = BOOT_LED_Pin;
 800209c:	f44f 4300 	mov.w	r3, #32768	; 0x8000
 80020a0:	9304      	str	r3, [sp, #16]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 80020a2:	2301      	movs	r3, #1
 80020a4:	9305      	str	r3, [sp, #20]
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 80020a6:	2302      	movs	r3, #2
  HAL_GPIO_Init(BOOT_LED_GPIO_Port, &GPIO_InitStruct);
 80020a8:	a904      	add	r1, sp, #16
 80020aa:	4846      	ldr	r0, [pc, #280]	; (80021c4 <main+0x188>)
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 80020ac:	9307      	str	r3, [sp, #28]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 80020ae:	9406      	str	r4, [sp, #24]
  HAL_GPIO_Init(BOOT_LED_GPIO_Port, &GPIO_InitStruct);
 80020b0:	f7fe fc74 	bl	800099c <HAL_GPIO_Init>
  __HAL_RCC_DMA1_CLK_ENABLE();
 80020b4:	696b      	ldr	r3, [r5, #20]
  huart1.Instance = USART1;
 80020b6:	4844      	ldr	r0, [pc, #272]	; (80021c8 <main+0x18c>)
  __HAL_RCC_DMA1_CLK_ENABLE();
 80020b8:	f043 0301 	orr.w	r3, r3, #1
 80020bc:	616b      	str	r3, [r5, #20]
 80020be:	696b      	ldr	r3, [r5, #20]
  huart1.Init.BaudRate = 115200;
 80020c0:	4a42      	ldr	r2, [pc, #264]	; (80021cc <main+0x190>)
  __HAL_RCC_DMA1_CLK_ENABLE();
 80020c2:	f003 0301 	and.w	r3, r3, #1
 80020c6:	9300      	str	r3, [sp, #0]
 80020c8:	9b00      	ldr	r3, [sp, #0]
  huart1.Init.BaudRate = 115200;
 80020ca:	f44f 33e1 	mov.w	r3, #115200	; 0x1c200
 80020ce:	e880 000c 	stmia.w	r0, {r2, r3}
  huart1.Init.Mode = UART_MODE_TX_RX;
 80020d2:	230c      	movs	r3, #12
  huart1.Init.WordLength = UART_WORDLENGTH_8B;
 80020d4:	6084      	str	r4, [r0, #8]
  huart1.Init.Mode = UART_MODE_TX_RX;
 80020d6:	6143      	str	r3, [r0, #20]
  huart1.Init.StopBits = UART_STOPBITS_1;
 80020d8:	60c4      	str	r4, [r0, #12]
  huart1.Init.Parity = UART_PARITY_NONE;
 80020da:	6104      	str	r4, [r0, #16]
  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
 80020dc:	6184      	str	r4, [r0, #24]
  huart1.Init.OverSampling = UART_OVERSAMPLING_16;
 80020de:	61c4      	str	r4, [r0, #28]
  if (HAL_UART_Init(&huart1) != HAL_OK)
 80020e0:	f7ff fa7c 	bl	80015dc <HAL_UART_Init>
  hi2c2.Instance = I2C2;
 80020e4:	483a      	ldr	r0, [pc, #232]	; (80021d0 <main+0x194>)
  hi2c2.Init.ClockSpeed = 400000;
 80020e6:	493b      	ldr	r1, [pc, #236]	; (80021d4 <main+0x198>)
 80020e8:	4b3b      	ldr	r3, [pc, #236]	; (80021d8 <main+0x19c>)
  hi2c2.Init.DutyCycle = I2C_DUTYCYCLE_2;
 80020ea:	6084      	str	r4, [r0, #8]
  hi2c2.Init.ClockSpeed = 400000;
 80020ec:	e880 000a 	stmia.w	r0, {r1, r3}
  hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
 80020f0:	f44f 4380 	mov.w	r3, #16384	; 0x4000
  hi2c2.Init.OwnAddress1 = 0;
 80020f4:	60c4      	str	r4, [r0, #12]
  hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
 80020f6:	6103      	str	r3, [r0, #16]
  hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
 80020f8:	6144      	str	r4, [r0, #20]
  hi2c2.Init.OwnAddress2 = 0;
 80020fa:	6184      	str	r4, [r0, #24]
  hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
 80020fc:	61c4      	str	r4, [r0, #28]
  hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
 80020fe:	6204      	str	r4, [r0, #32]
  if (HAL_I2C_Init(&hi2c2) != HAL_OK)
 8002100:	f7fe fd42 	bl	8000b88 <HAL_I2C_Init>
  htim6.Init.Prescaler = 5600 - 1;
 8002104:	f241 53df 	movw	r3, #5599	; 0x15df
  htim6.Instance = TIM6;
 8002108:	4d34      	ldr	r5, [pc, #208]	; (80021dc <main+0x1a0>)
  htim6.Init.Prescaler = 5600 - 1;
 800210a:	4835      	ldr	r0, [pc, #212]	; (80021e0 <main+0x1a4>)
  htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
 800210c:	60ac      	str	r4, [r5, #8]
  htim6.Init.Prescaler = 5600 - 1;
 800210e:	e885 0009 	stmia.w	r5, {r0, r3}
  htim6.Init.Period = 10 - 1;
 8002112:	2309      	movs	r3, #9
  if (HAL_TIM_Base_Init(&htim6) != HAL_OK)
 8002114:	4628      	mov	r0, r5
  htim6.Init.Period = 10 - 1;
 8002116:	60eb      	str	r3, [r5, #12]
  htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
 8002118:	61ac      	str	r4, [r5, #24]
  TIM_MasterConfigTypeDef sMasterConfig = {0};
 800211a:	9404      	str	r4, [sp, #16]
 800211c:	9405      	str	r4, [sp, #20]
  if (HAL_TIM_Base_Init(&htim6) != HAL_OK)
 800211e:	f7ff f94b 	bl	80013b8 <HAL_TIM_Base_Init>
  if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK)
 8002122:	a904      	add	r1, sp, #16
 8002124:	4628      	mov	r0, r5
  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
 8002126:	9404      	str	r4, [sp, #16]
  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
 8002128:	9405      	str	r4, [sp, #20]
  if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK)
 800212a:	f7ff f95f 	bl	80013ec <HAL_TIMEx_MasterConfigSynchronization>
  HAL_NVIC_SetPriority(DMA1_Channel5_IRQn, 0, 0);
 800212e:	4622      	mov	r2, r4
 8002130:	4621      	mov	r1, r4
 8002132:	200f      	movs	r0, #15
 8002134:	f7fe f8ee 	bl	8000314 <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(DMA1_Channel5_IRQn);
 8002138:	200f      	movs	r0, #15
 800213a:	f7fe f91f 	bl	800037c <HAL_NVIC_EnableIRQ>
  HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
 800213e:	4622      	mov	r2, r4
 8002140:	4621      	mov	r1, r4
 8002142:	2025      	movs	r0, #37	; 0x25
 8002144:	f7fe f8e6 	bl	8000314 <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(USART1_IRQn);
 8002148:	2025      	movs	r0, #37	; 0x25
 800214a:	f7fe f917 	bl	800037c <HAL_NVIC_EnableIRQ>
  HAL_NVIC_SetPriority(TIM6_IRQn, 0, 0);
 800214e:	4622      	mov	r2, r4
 8002150:	4621      	mov	r1, r4
 8002152:	2036      	movs	r0, #54	; 0x36
 8002154:	f7fe f8de 	bl	8000314 <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(TIM6_IRQn);
 8002158:	2036      	movs	r0, #54	; 0x36
 800215a:	f7fe f90f 	bl	800037c <HAL_NVIC_EnableIRQ>
  HAL_NVIC_SetPriority(DMA1_Channel4_IRQn, 0, 0);
 800215e:	4622      	mov	r2, r4
 8002160:	4621      	mov	r1, r4
 8002162:	200e      	movs	r0, #14
 8002164:	f7fe f8d6 	bl	8000314 <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(DMA1_Channel4_IRQn);
 8002168:	200e      	movs	r0, #14
 800216a:	f7fe f907 	bl	800037c <HAL_NVIC_EnableIRQ>
  HAL_TIM_Base_Start_IT(&htim6);
 800216e:	4628      	mov	r0, r5
 8002170:	f7ff f824 	bl	80011bc <HAL_TIM_Base_Start_IT>
  setbuf(stdout, NULL);
 8002174:	4b1b      	ldr	r3, [pc, #108]	; (80021e4 <main+0x1a8>)
 8002176:	4621      	mov	r1, r4
 8002178:	681b      	ldr	r3, [r3, #0]
	  while (TerminalQueue.data > 0 && UartTimerCnt > 30) GetDataFromUartQueue(&hTerminal);
 800217a:	4d1b      	ldr	r5, [pc, #108]	; (80021e8 <main+0x1ac>)
  setbuf(stdout, NULL);
 800217c:	6898      	ldr	r0, [r3, #8]
 800217e:	f000 faff 	bl	8002780 <setbuf>
  Firmware_BootStart_Signal();
 8002182:	f7ff fc2f 	bl	80019e4 <Firmware_BootStart_Signal>
  InitUartQueue(&TerminalQueue);
 8002186:	4819      	ldr	r0, [pc, #100]	; (80021ec <main+0x1b0>)
 8002188:	f000 f986 	bl	8002498 <InitUartQueue>
  MBIC_FirmwareFile_CrcCheck();
 800218c:	f7ff fd90 	bl	8001cb0 <MBIC_FirmwareFile_CrcCheck>
	  if(LedTimerCnt > 500){HAL_GPIO_TogglePin(BOOT_LED_GPIO_Port,BOOT_LED_Pin);LedTimerCnt = 0;}
 8002190:	4c17      	ldr	r4, [pc, #92]	; (80021f0 <main+0x1b4>)
 8002192:	6823      	ldr	r3, [r4, #0]
 8002194:	f5b3 7ffa 	cmp.w	r3, #500	; 0x1f4
 8002198:	d906      	bls.n	80021a8 <main+0x16c>
 800219a:	f44f 4100 	mov.w	r1, #32768	; 0x8000
 800219e:	4630      	mov	r0, r6
 80021a0:	f7fe fced 	bl	8000b7e <HAL_GPIO_TogglePin>
 80021a4:	2300      	movs	r3, #0
 80021a6:	6023      	str	r3, [r4, #0]
	  while (TerminalQueue.data > 0 && UartTimerCnt > 30) GetDataFromUartQueue(&hTerminal);
 80021a8:	4c10      	ldr	r4, [pc, #64]	; (80021ec <main+0x1b0>)
 80021aa:	4f07      	ldr	r7, [pc, #28]	; (80021c8 <main+0x18c>)
 80021ac:	68a3      	ldr	r3, [r4, #8]
 80021ae:	2b00      	cmp	r3, #0
 80021b0:	ddee      	ble.n	8002190 <main+0x154>
 80021b2:	682b      	ldr	r3, [r5, #0]
 80021b4:	2b1e      	cmp	r3, #30
 80021b6:	d9eb      	bls.n	8002190 <main+0x154>
 80021b8:	4638      	mov	r0, r7
 80021ba:	f000 f97b 	bl	80024b4 <GetDataFromUartQueue>
 80021be:	e7f5      	b.n	80021ac <main+0x170>
 80021c0:	40021000 	.word	0x40021000
 80021c4:	40011000 	.word	0x40011000
 80021c8:	200003f4 	.word	0x200003f4
 80021cc:	40013800 	.word	0x40013800
 80021d0:	20000318 	.word	0x20000318
 80021d4:	40005800 	.word	0x40005800
 80021d8:	00061a80 	.word	0x00061a80
 80021dc:	20000434 	.word	0x20000434
 80021e0:	40001000 	.word	0x40001000
 80021e4:	2000021c 	.word	0x2000021c
 80021e8:	200002e0 	.word	0x200002e0
 80021ec:	20000474 	.word	0x20000474
 80021f0:	200002dc 	.word	0x200002dc

080021f4 <Error_Handler>:
/**
  * @brief  This function is executed in case of error occurrence.
  * @retval None
  */
void Error_Handler(void)
{
 80021f4:	4770      	bx	lr
	...

080021f8 <HAL_MspInit>:
{
  /* USER CODE BEGIN MspInit 0 */

  /* USER CODE END MspInit 0 */

  __HAL_RCC_AFIO_CLK_ENABLE();
 80021f8:	4b0e      	ldr	r3, [pc, #56]	; (8002234 <HAL_MspInit+0x3c>)
{
 80021fa:	b082      	sub	sp, #8
  __HAL_RCC_AFIO_CLK_ENABLE();
 80021fc:	699a      	ldr	r2, [r3, #24]
 80021fe:	f042 0201 	orr.w	r2, r2, #1
 8002202:	619a      	str	r2, [r3, #24]
 8002204:	699a      	ldr	r2, [r3, #24]
 8002206:	f002 0201 	and.w	r2, r2, #1
 800220a:	9200      	str	r2, [sp, #0]
 800220c:	9a00      	ldr	r2, [sp, #0]
  __HAL_RCC_PWR_CLK_ENABLE();
 800220e:	69da      	ldr	r2, [r3, #28]
 8002210:	f042 5280 	orr.w	r2, r2, #268435456	; 0x10000000
 8002214:	61da      	str	r2, [r3, #28]
 8002216:	69db      	ldr	r3, [r3, #28]

  /* System interrupt init*/

  /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled 
  */
  __HAL_AFIO_REMAP_SWJ_NOJTAG();
 8002218:	4a07      	ldr	r2, [pc, #28]	; (8002238 <HAL_MspInit+0x40>)
  __HAL_RCC_PWR_CLK_ENABLE();
 800221a:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 800221e:	9301      	str	r3, [sp, #4]
 8002220:	9b01      	ldr	r3, [sp, #4]
  __HAL_AFIO_REMAP_SWJ_NOJTAG();
 8002222:	6853      	ldr	r3, [r2, #4]
 8002224:	f023 63e0 	bic.w	r3, r3, #117440512	; 0x7000000
 8002228:	f043 7300 	orr.w	r3, r3, #33554432	; 0x2000000
 800222c:	6053      	str	r3, [r2, #4]

  /* USER CODE BEGIN MspInit 1 */

  /* USER CODE END MspInit 1 */
}
 800222e:	b002      	add	sp, #8
 8002230:	4770      	bx	lr
 8002232:	bf00      	nop
 8002234:	40021000 	.word	0x40021000
 8002238:	40010000 	.word	0x40010000

0800223c <HAL_I2C_MspInit>:
* This function configures the hardware resources used in this example
* @param hi2c: I2C handle pointer
* @retval None
*/
void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
{
 800223c:	b510      	push	{r4, lr}
 800223e:	4604      	mov	r4, r0
 8002240:	b086      	sub	sp, #24
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8002242:	2210      	movs	r2, #16
 8002244:	2100      	movs	r1, #0
 8002246:	a802      	add	r0, sp, #8
 8002248:	f000 fa16 	bl	8002678 <memset>
  if(hi2c->Instance==I2C2)
 800224c:	6822      	ldr	r2, [r4, #0]
 800224e:	4b11      	ldr	r3, [pc, #68]	; (8002294 <HAL_I2C_MspInit+0x58>)
 8002250:	429a      	cmp	r2, r3
 8002252:	d11d      	bne.n	8002290 <HAL_I2C_MspInit+0x54>
  {
  /* USER CODE BEGIN I2C2_MspInit 0 */

  /* USER CODE END I2C2_MspInit 0 */
  
    __HAL_RCC_GPIOB_CLK_ENABLE();
 8002254:	4c10      	ldr	r4, [pc, #64]	; (8002298 <HAL_I2C_MspInit+0x5c>)
    PB11     ------> I2C2_SDA 
    */
    GPIO_InitStruct.Pin = EEPROM_SCL_Pin|EEPROM_SDA_Pin;
    GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8002256:	a902      	add	r1, sp, #8
    __HAL_RCC_GPIOB_CLK_ENABLE();
 8002258:	69a3      	ldr	r3, [r4, #24]
    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 800225a:	4810      	ldr	r0, [pc, #64]	; (800229c <HAL_I2C_MspInit+0x60>)
    __HAL_RCC_GPIOB_CLK_ENABLE();
 800225c:	f043 0308 	orr.w	r3, r3, #8
 8002260:	61a3      	str	r3, [r4, #24]
 8002262:	69a3      	ldr	r3, [r4, #24]
 8002264:	f003 0308 	and.w	r3, r3, #8
 8002268:	9300      	str	r3, [sp, #0]
 800226a:	9b00      	ldr	r3, [sp, #0]
    GPIO_InitStruct.Pin = EEPROM_SCL_Pin|EEPROM_SDA_Pin;
 800226c:	f44f 6340 	mov.w	r3, #3072	; 0xc00
 8002270:	9302      	str	r3, [sp, #8]
    GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
 8002272:	2312      	movs	r3, #18
 8002274:	9303      	str	r3, [sp, #12]
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
 8002276:	2303      	movs	r3, #3
 8002278:	9305      	str	r3, [sp, #20]
    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 800227a:	f7fe fb8f 	bl	800099c <HAL_GPIO_Init>

    /* Peripheral clock enable */
    __HAL_RCC_I2C2_CLK_ENABLE();
 800227e:	69e3      	ldr	r3, [r4, #28]
 8002280:	f443 0380 	orr.w	r3, r3, #4194304	; 0x400000
 8002284:	61e3      	str	r3, [r4, #28]
 8002286:	69e3      	ldr	r3, [r4, #28]
 8002288:	f403 0380 	and.w	r3, r3, #4194304	; 0x400000
 800228c:	9301      	str	r3, [sp, #4]
 800228e:	9b01      	ldr	r3, [sp, #4]
  /* USER CODE BEGIN I2C2_MspInit 1 */

  /* USER CODE END I2C2_MspInit 1 */
  }

}
 8002290:	b006      	add	sp, #24
 8002292:	bd10      	pop	{r4, pc}
 8002294:	40005800 	.word	0x40005800
 8002298:	40021000 	.word	0x40021000
 800229c:	40010c00 	.word	0x40010c00

080022a0 <HAL_TIM_Base_MspInit>:
* @param htim_base: TIM_Base handle pointer
* @retval None
*/
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
{
  if(htim_base->Instance==TIM6)
 80022a0:	6802      	ldr	r2, [r0, #0]
 80022a2:	4b08      	ldr	r3, [pc, #32]	; (80022c4 <HAL_TIM_Base_MspInit+0x24>)
{
 80022a4:	b082      	sub	sp, #8
  if(htim_base->Instance==TIM6)
 80022a6:	429a      	cmp	r2, r3
 80022a8:	d10a      	bne.n	80022c0 <HAL_TIM_Base_MspInit+0x20>
  {
  /* USER CODE BEGIN TIM6_MspInit 0 */

  /* USER CODE END TIM6_MspInit 0 */
    /* Peripheral clock enable */
    __HAL_RCC_TIM6_CLK_ENABLE();
 80022aa:	f503 3300 	add.w	r3, r3, #131072	; 0x20000
 80022ae:	69da      	ldr	r2, [r3, #28]
 80022b0:	f042 0210 	orr.w	r2, r2, #16
 80022b4:	61da      	str	r2, [r3, #28]
 80022b6:	69db      	ldr	r3, [r3, #28]
 80022b8:	f003 0310 	and.w	r3, r3, #16
 80022bc:	9301      	str	r3, [sp, #4]
 80022be:	9b01      	ldr	r3, [sp, #4]
  /* USER CODE BEGIN TIM6_MspInit 1 */

  /* USER CODE END TIM6_MspInit 1 */
  }

}
 80022c0:	b002      	add	sp, #8
 80022c2:	4770      	bx	lr
 80022c4:	40001000 	.word	0x40001000

080022c8 <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
 80022c8:	b570      	push	{r4, r5, r6, lr}
 80022ca:	4606      	mov	r6, r0
 80022cc:	b086      	sub	sp, #24
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 80022ce:	2210      	movs	r2, #16
 80022d0:	2100      	movs	r1, #0
 80022d2:	a802      	add	r0, sp, #8
 80022d4:	f000 f9d0 	bl	8002678 <memset>
  if(huart->Instance==USART1)
 80022d8:	6832      	ldr	r2, [r6, #0]
 80022da:	4b2b      	ldr	r3, [pc, #172]	; (8002388 <HAL_UART_MspInit+0xc0>)
 80022dc:	429a      	cmp	r2, r3
 80022de:	d151      	bne.n	8002384 <HAL_UART_MspInit+0xbc>
  {
  /* USER CODE BEGIN USART1_MspInit 0 */

  /* USER CODE END USART1_MspInit 0 */
    /* Peripheral clock enable */
    __HAL_RCC_USART1_CLK_ENABLE();
 80022e0:	f503 4358 	add.w	r3, r3, #55296	; 0xd800
 80022e4:	699a      	ldr	r2, [r3, #24]
    PA10     ------> USART1_RX 
    */
    GPIO_InitStruct.Pin = GPIO_PIN_9;
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 80022e6:	a902      	add	r1, sp, #8
    __HAL_RCC_USART1_CLK_ENABLE();
 80022e8:	f442 4280 	orr.w	r2, r2, #16384	; 0x4000
 80022ec:	619a      	str	r2, [r3, #24]
 80022ee:	699a      	ldr	r2, [r3, #24]
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 80022f0:	4826      	ldr	r0, [pc, #152]	; (800238c <HAL_UART_MspInit+0xc4>)
    __HAL_RCC_USART1_CLK_ENABLE();
 80022f2:	f402 4280 	and.w	r2, r2, #16384	; 0x4000
 80022f6:	9200      	str	r2, [sp, #0]
 80022f8:	9a00      	ldr	r2, [sp, #0]
    __HAL_RCC_GPIOA_CLK_ENABLE();
 80022fa:	699a      	ldr	r2, [r3, #24]

    GPIO_InitStruct.Pin = GPIO_PIN_10;
    GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
 80022fc:	2500      	movs	r5, #0
    __HAL_RCC_GPIOA_CLK_ENABLE();
 80022fe:	f042 0204 	orr.w	r2, r2, #4
 8002302:	619a      	str	r2, [r3, #24]
 8002304:	699b      	ldr	r3, [r3, #24]
    GPIO_InitStruct.Pull = GPIO_NOPULL;
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);

    /* USART1 DMA Init */
    /* USART1_RX Init */
    hdma_usart1_rx.Instance = DMA1_Channel5;
 8002306:	4c22      	ldr	r4, [pc, #136]	; (8002390 <HAL_UART_MspInit+0xc8>)
    __HAL_RCC_GPIOA_CLK_ENABLE();
 8002308:	f003 0304 	and.w	r3, r3, #4
 800230c:	9301      	str	r3, [sp, #4]
 800230e:	9b01      	ldr	r3, [sp, #4]
    GPIO_InitStruct.Pin = GPIO_PIN_9;
 8002310:	f44f 7300 	mov.w	r3, #512	; 0x200
 8002314:	9302      	str	r3, [sp, #8]
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 8002316:	2302      	movs	r3, #2
 8002318:	9303      	str	r3, [sp, #12]
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
 800231a:	2303      	movs	r3, #3
 800231c:	9305      	str	r3, [sp, #20]
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 800231e:	f7fe fb3d 	bl	800099c <HAL_GPIO_Init>
    GPIO_InitStruct.Pin = GPIO_PIN_10;
 8002322:	f44f 6380 	mov.w	r3, #1024	; 0x400
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8002326:	4819      	ldr	r0, [pc, #100]	; (800238c <HAL_UART_MspInit+0xc4>)
 8002328:	a902      	add	r1, sp, #8
    GPIO_InitStruct.Pin = GPIO_PIN_10;
 800232a:	9302      	str	r3, [sp, #8]
    GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
 800232c:	9503      	str	r5, [sp, #12]
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 800232e:	9504      	str	r5, [sp, #16]
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8002330:	f7fe fb34 	bl	800099c <HAL_GPIO_Init>
    hdma_usart1_rx.Instance = DMA1_Channel5;
 8002334:	4b17      	ldr	r3, [pc, #92]	; (8002394 <HAL_UART_MspInit+0xcc>)
    hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE;
    hdma_usart1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
    hdma_usart1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
    hdma_usart1_rx.Init.Mode = DMA_NORMAL;
    hdma_usart1_rx.Init.Priority = DMA_PRIORITY_LOW;
    if (HAL_DMA_Init(&hdma_usart1_rx) != HAL_OK)
 8002336:	4620      	mov	r0, r4
    hdma_usart1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
 8002338:	e884 0028 	stmia.w	r4, {r3, r5}
    hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE;
 800233c:	2380      	movs	r3, #128	; 0x80
    hdma_usart1_rx.Init.PeriphInc = DMA_PINC_DISABLE;
 800233e:	60a5      	str	r5, [r4, #8]
    hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE;
 8002340:	60e3      	str	r3, [r4, #12]
    hdma_usart1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
 8002342:	6125      	str	r5, [r4, #16]
    hdma_usart1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
 8002344:	6165      	str	r5, [r4, #20]
    hdma_usart1_rx.Init.Mode = DMA_NORMAL;
 8002346:	61a5      	str	r5, [r4, #24]
    hdma_usart1_rx.Init.Priority = DMA_PRIORITY_LOW;
 8002348:	61e5      	str	r5, [r4, #28]
    if (HAL_DMA_Init(&hdma_usart1_rx) != HAL_OK)
 800234a:	f7fe f839 	bl	80003c0 <HAL_DMA_Init>
 800234e:	b108      	cbz	r0, 8002354 <HAL_UART_MspInit+0x8c>
    {
      Error_Handler();
 8002350:	f7ff ff50 	bl	80021f4 <Error_Handler>

    __HAL_LINKDMA(huart,hdmarx,hdma_usart1_rx);

    /* USART1_TX Init */
    hdma_usart1_tx.Instance = DMA1_Channel4;
    hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
 8002354:	f04f 0c10 	mov.w	ip, #16
 8002358:	4b0f      	ldr	r3, [pc, #60]	; (8002398 <HAL_UART_MspInit+0xd0>)
    __HAL_LINKDMA(huart,hdmarx,hdma_usart1_rx);
 800235a:	6374      	str	r4, [r6, #52]	; 0x34
 800235c:	6266      	str	r6, [r4, #36]	; 0x24
    hdma_usart1_tx.Instance = DMA1_Channel4;
 800235e:	4c0f      	ldr	r4, [pc, #60]	; (800239c <HAL_UART_MspInit+0xd4>)
    hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
    hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE;
 8002360:	2280      	movs	r2, #128	; 0x80
    hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
 8002362:	e884 1008 	stmia.w	r4, {r3, ip}
    hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
 8002366:	2300      	movs	r3, #0
    hdma_usart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
    hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
    hdma_usart1_tx.Init.Mode = DMA_NORMAL;
    hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW;
    if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK)
 8002368:	4620      	mov	r0, r4
    hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
 800236a:	60a3      	str	r3, [r4, #8]
    hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE;
 800236c:	60e2      	str	r2, [r4, #12]
    hdma_usart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
 800236e:	6123      	str	r3, [r4, #16]
    hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
 8002370:	6163      	str	r3, [r4, #20]
    hdma_usart1_tx.Init.Mode = DMA_NORMAL;
 8002372:	61a3      	str	r3, [r4, #24]
    hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW;
 8002374:	61e3      	str	r3, [r4, #28]
    if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK)
 8002376:	f7fe f823 	bl	80003c0 <HAL_DMA_Init>
 800237a:	b108      	cbz	r0, 8002380 <HAL_UART_MspInit+0xb8>
    {
      Error_Handler();
 800237c:	f7ff ff3a 	bl	80021f4 <Error_Handler>
    }

    __HAL_LINKDMA(huart,hdmatx,hdma_usart1_tx);
 8002380:	6334      	str	r4, [r6, #48]	; 0x30
 8002382:	6266      	str	r6, [r4, #36]	; 0x24
  /* USER CODE BEGIN USART1_MspInit 1 */

  /* USER CODE END USART1_MspInit 1 */
  }

}
 8002384:	b006      	add	sp, #24
 8002386:	bd70      	pop	{r4, r5, r6, pc}
 8002388:	40013800 	.word	0x40013800
 800238c:	40010800 	.word	0x40010800
 8002390:	200003b0 	.word	0x200003b0
 8002394:	40020058 	.word	0x40020058
 8002398:	40020044 	.word	0x40020044
 800239c:	2000036c 	.word	0x2000036c

080023a0 <NMI_Handler>:
 80023a0:	4770      	bx	lr

080023a2 <HardFault_Handler>:

/**
  * @brief This function handles Hard fault interrupt.
  */
void HardFault_Handler(void)
{
 80023a2:	e7fe      	b.n	80023a2 <HardFault_Handler>

080023a4 <MemManage_Handler>:

/**
  * @brief This function handles Memory management fault.
  */
void MemManage_Handler(void)
{
 80023a4:	e7fe      	b.n	80023a4 <MemManage_Handler>

080023a6 <BusFault_Handler>:

/**
  * @brief This function handles Prefetch fault, memory access fault.
  */
void BusFault_Handler(void)
{
 80023a6:	e7fe      	b.n	80023a6 <BusFault_Handler>

080023a8 <UsageFault_Handler>:

/**
  * @brief This function handles Undefined instruction or illegal state.
  */
void UsageFault_Handler(void)
{
 80023a8:	e7fe      	b.n	80023a8 <UsageFault_Handler>

080023aa <SVC_Handler>:
 80023aa:	4770      	bx	lr

080023ac <DebugMon_Handler>:
 80023ac:	4770      	bx	lr

080023ae <PendSV_Handler>:

/**
  * @brief This function handles Pendable request for system service.
  */
void PendSV_Handler(void)
{
 80023ae:	4770      	bx	lr

080023b0 <SysTick_Handler>:
void SysTick_Handler(void)
{
  /* USER CODE BEGIN SysTick_IRQn 0 */

  /* USER CODE END SysTick_IRQn 0 */
  HAL_IncTick();
 80023b0:	f7fd bf7a 	b.w	80002a8 <HAL_IncTick>

080023b4 <DMA1_Channel4_IRQHandler>:
void DMA1_Channel4_IRQHandler(void)
{
  /* USER CODE BEGIN DMA1_Channel4_IRQn 0 */

  /* USER CODE END DMA1_Channel4_IRQn 0 */
  HAL_DMA_IRQHandler(&hdma_usart1_tx);
 80023b4:	4801      	ldr	r0, [pc, #4]	; (80023bc <DMA1_Channel4_IRQHandler+0x8>)
 80023b6:	f7fe b8ef 	b.w	8000598 <HAL_DMA_IRQHandler>
 80023ba:	bf00      	nop
 80023bc:	2000036c 	.word	0x2000036c

080023c0 <DMA1_Channel5_IRQHandler>:
void DMA1_Channel5_IRQHandler(void)
{
  /* USER CODE BEGIN DMA1_Channel5_IRQn 0 */

  /* USER CODE END DMA1_Channel5_IRQn 0 */
  HAL_DMA_IRQHandler(&hdma_usart1_rx);
 80023c0:	4801      	ldr	r0, [pc, #4]	; (80023c8 <DMA1_Channel5_IRQHandler+0x8>)
 80023c2:	f7fe b8e9 	b.w	8000598 <HAL_DMA_IRQHandler>
 80023c6:	bf00      	nop
 80023c8:	200003b0 	.word	0x200003b0

080023cc <USART1_IRQHandler>:
void USART1_IRQHandler(void)
{
  /* USER CODE BEGIN USART1_IRQn 0 */

  /* USER CODE END USART1_IRQn 0 */
  HAL_UART_IRQHandler(&huart1);
 80023cc:	4801      	ldr	r0, [pc, #4]	; (80023d4 <USART1_IRQHandler+0x8>)
 80023ce:	f7ff ba61 	b.w	8001894 <HAL_UART_IRQHandler>
 80023d2:	bf00      	nop
 80023d4:	200003f4 	.word	0x200003f4

080023d8 <TIM6_IRQHandler>:
void TIM6_IRQHandler(void)
{
  /* USER CODE BEGIN TIM6_IRQn 0 */

  /* USER CODE END TIM6_IRQn 0 */
  HAL_TIM_IRQHandler(&htim6);
 80023d8:	4801      	ldr	r0, [pc, #4]	; (80023e0 <TIM6_IRQHandler+0x8>)
 80023da:	f7fe befe 	b.w	80011da <HAL_TIM_IRQHandler>
 80023de:	bf00      	nop
 80023e0:	20000434 	.word	0x20000434

080023e4 <_read>:
	_kill(status, -1);
	while (1) {}		/* Make sure we hang here */
}

__attribute__((weak)) int _read(int file, char *ptr, int len)
{
 80023e4:	b570      	push	{r4, r5, r6, lr}
 80023e6:	460e      	mov	r6, r1
 80023e8:	4615      	mov	r5, r2
	int DataIdx;

	for (DataIdx = 0; DataIdx < len; DataIdx++)
 80023ea:	460c      	mov	r4, r1
 80023ec:	1ba3      	subs	r3, r4, r6
 80023ee:	429d      	cmp	r5, r3
 80023f0:	dc01      	bgt.n	80023f6 <_read+0x12>
	{
		*ptr++ = __io_getchar();
	}

return len;
}
 80023f2:	4628      	mov	r0, r5
 80023f4:	bd70      	pop	{r4, r5, r6, pc}
		*ptr++ = __io_getchar();
 80023f6:	f3af 8000 	nop.w
 80023fa:	f804 0b01 	strb.w	r0, [r4], #1
 80023fe:	e7f5      	b.n	80023ec <_read+0x8>

08002400 <_sbrk>:
	}
	return len;
}

caddr_t _sbrk(int incr)
{
 8002400:	b508      	push	{r3, lr}
	extern char end asm("end");
	static char *heap_end;
	char *prev_heap_end;

	if (heap_end == 0)
 8002402:	4b0a      	ldr	r3, [pc, #40]	; (800242c <_sbrk+0x2c>)
{
 8002404:	4602      	mov	r2, r0
	if (heap_end == 0)
 8002406:	6819      	ldr	r1, [r3, #0]
 8002408:	b909      	cbnz	r1, 800240e <_sbrk+0xe>
		heap_end = &end;
 800240a:	4909      	ldr	r1, [pc, #36]	; (8002430 <_sbrk+0x30>)
 800240c:	6019      	str	r1, [r3, #0]

	prev_heap_end = heap_end;
	if (heap_end + incr > stack_ptr)
 800240e:	4669      	mov	r1, sp
	prev_heap_end = heap_end;
 8002410:	6818      	ldr	r0, [r3, #0]
	if (heap_end + incr > stack_ptr)
 8002412:	4402      	add	r2, r0
 8002414:	428a      	cmp	r2, r1
 8002416:	d906      	bls.n	8002426 <_sbrk+0x26>
	{
//		write(1, "Heap and stack collision\n", 25);
//		abort();
		errno = ENOMEM;
 8002418:	f000 f904 	bl	8002624 <__errno>
 800241c:	230c      	movs	r3, #12
 800241e:	6003      	str	r3, [r0, #0]
		return (caddr_t) -1;
 8002420:	f04f 30ff 	mov.w	r0, #4294967295
 8002424:	bd08      	pop	{r3, pc}
	}

	heap_end += incr;
 8002426:	601a      	str	r2, [r3, #0]

	return (caddr_t) prev_heap_end;
}
 8002428:	bd08      	pop	{r3, pc}
 800242a:	bf00      	nop
 800242c:	200002e4 	.word	0x200002e4
 8002430:	20001174 	.word	0x20001174

08002434 <_close>:

int _close(int file)
{
	return -1;
}
 8002434:	f04f 30ff 	mov.w	r0, #4294967295
 8002438:	4770      	bx	lr

0800243a <_fstat>:


int _fstat(int file, struct stat *st)
{
	st->st_mode = S_IFCHR;
 800243a:	f44f 5300 	mov.w	r3, #8192	; 0x2000
	return 0;
}
 800243e:	2000      	movs	r0, #0
	st->st_mode = S_IFCHR;
 8002440:	604b      	str	r3, [r1, #4]
}
 8002442:	4770      	bx	lr

08002444 <_isatty>:

int _isatty(int file)
{
	return 1;
}
 8002444:	2001      	movs	r0, #1
 8002446:	4770      	bx	lr

08002448 <_lseek>:

int _lseek(int file, int ptr, int dir)
{
	return 0;
}
 8002448:	2000      	movs	r0, #0
 800244a:	4770      	bx	lr

0800244c <SystemInit>:
  */
void SystemInit (void)
{
  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
  /* Set HSION bit */
  RCC->CR |= 0x00000001U;
 800244c:	4b0f      	ldr	r3, [pc, #60]	; (800248c <SystemInit+0x40>)
 800244e:	681a      	ldr	r2, [r3, #0]
 8002450:	f042 0201 	orr.w	r2, r2, #1
 8002454:	601a      	str	r2, [r3, #0]

  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
#if !defined(STM32F105xC) && !defined(STM32F107xC)
  RCC->CFGR &= 0xF8FF0000U;
 8002456:	6859      	ldr	r1, [r3, #4]
 8002458:	4a0d      	ldr	r2, [pc, #52]	; (8002490 <SystemInit+0x44>)
 800245a:	400a      	ands	r2, r1
 800245c:	605a      	str	r2, [r3, #4]
#else
  RCC->CFGR &= 0xF0FF0000U;
#endif /* STM32F105xC */   
  
  /* Reset HSEON, CSSON and PLLON bits */
  RCC->CR &= 0xFEF6FFFFU;
 800245e:	681a      	ldr	r2, [r3, #0]
 8002460:	f022 7284 	bic.w	r2, r2, #17301504	; 0x1080000
 8002464:	f422 3280 	bic.w	r2, r2, #65536	; 0x10000
 8002468:	601a      	str	r2, [r3, #0]

  /* Reset HSEBYP bit */
  RCC->CR &= 0xFFFBFFFFU;
 800246a:	681a      	ldr	r2, [r3, #0]
 800246c:	f422 2280 	bic.w	r2, r2, #262144	; 0x40000
 8002470:	601a      	str	r2, [r3, #0]

  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
  RCC->CFGR &= 0xFF80FFFFU;
 8002472:	685a      	ldr	r2, [r3, #4]
 8002474:	f422 02fe 	bic.w	r2, r2, #8323072	; 0x7f0000
 8002478:	605a      	str	r2, [r3, #4]

  /* Reset CFGR2 register */
  RCC->CFGR2 = 0x00000000U;      
#else
  /* Disable all interrupts and clear pending bits  */
  RCC->CIR = 0x009F0000U;
 800247a:	f44f 021f 	mov.w	r2, #10420224	; 0x9f0000
 800247e:	609a      	str	r2, [r3, #8]
#endif 

#ifdef VECT_TAB_SRAM
  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#else
  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
 8002480:	f04f 6200 	mov.w	r2, #134217728	; 0x8000000
 8002484:	4b03      	ldr	r3, [pc, #12]	; (8002494 <SystemInit+0x48>)
 8002486:	609a      	str	r2, [r3, #8]
 8002488:	4770      	bx	lr
 800248a:	bf00      	nop
 800248c:	40021000 	.word	0x40021000
 8002490:	f8ff0000 	.word	0xf8ff0000
 8002494:	e000ed00 	.word	0xe000ed00

08002498 <InitUartQueue>:
UARTQUEUE TerminalQueue;
UARTQUEUE WifiQueue;

void InitUartQueue(pUARTQUEUE pQueue)
{
    pQueue->data = pQueue->head = pQueue->tail = 0;
 8002498:	2300      	movs	r3, #0

    if (HAL_UART_Receive_DMA(&hTerminal, TerminalQueue.Buffer, 1) != HAL_OK)
 800249a:	2201      	movs	r2, #1
    pQueue->data = pQueue->head = pQueue->tail = 0;
 800249c:	6043      	str	r3, [r0, #4]
 800249e:	6003      	str	r3, [r0, #0]
 80024a0:	6083      	str	r3, [r0, #8]
    if (HAL_UART_Receive_DMA(&hTerminal, TerminalQueue.Buffer, 1) != HAL_OK)
 80024a2:	4902      	ldr	r1, [pc, #8]	; (80024ac <InitUartQueue+0x14>)
 80024a4:	4802      	ldr	r0, [pc, #8]	; (80024b0 <InitUartQueue+0x18>)
 80024a6:	f7ff b923 	b.w	80016f0 <HAL_UART_Receive_DMA>
 80024aa:	bf00      	nop
 80024ac:	20000480 	.word	0x20000480
 80024b0:	200003f4 	.word	0x200003f4

080024b4 <GetDataFromUartQueue>:
    pUARTQUEUE pQueue = &TerminalQueue;
//    if (HAL_UART_Transmit(dst, pQueue->Buffer + pQueue->tail, 1, 3000) != HAL_OK)
//    {
//       _Error_Handler(__FILE__, __LINE__);
//    }
    update_data_buf[cnt++] = *(pQueue->Buffer + pQueue->tail);        
 80024b4:	4a29      	ldr	r2, [pc, #164]	; (800255c <GetDataFromUartQueue+0xa8>)
{
 80024b6:	b570      	push	{r4, r5, r6, lr}
    update_data_buf[cnt++] = *(pQueue->Buffer + pQueue->tail);        
 80024b8:	6810      	ldr	r0, [r2, #0]
 80024ba:	4c29      	ldr	r4, [pc, #164]	; (8002560 <GetDataFromUartQueue+0xac>)
 80024bc:	1c43      	adds	r3, r0, #1
 80024be:	6013      	str	r3, [r2, #0]
 80024c0:	4b28      	ldr	r3, [pc, #160]	; (8002564 <GetDataFromUartQueue+0xb0>)
 80024c2:	6859      	ldr	r1, [r3, #4]
 80024c4:	f103 050c 	add.w	r5, r3, #12
 80024c8:	5d4d      	ldrb	r5, [r1, r5]

    pQueue->tail++;
 80024ca:	3101      	adds	r1, #1
    update_data_buf[cnt++] = *(pQueue->Buffer + pQueue->tail);        
 80024cc:	5425      	strb	r5, [r4, r0]
    if (pQueue->tail >= QUEUE_BUFFER_LENGTH) pQueue->tail = 0;
 80024ce:	f240 404b 	movw	r0, #1099	; 0x44b
 80024d2:	4281      	cmp	r1, r0
 80024d4:	bfc8      	it	gt
 80024d6:	2100      	movgt	r1, #0
    pQueue->data--;
 80024d8:	689d      	ldr	r5, [r3, #8]
    if (pQueue->tail >= QUEUE_BUFFER_LENGTH) pQueue->tail = 0;
 80024da:	6059      	str	r1, [r3, #4]
    pQueue->data--;
 80024dc:	3d01      	subs	r5, #1
 80024de:	609d      	str	r5, [r3, #8]
    
    if(pQueue->data == 0){
 80024e0:	b97d      	cbnz	r5, 8002502 <GetDataFromUartQueue+0x4e>
            for(int i = 0; i < 128; i++){
                printf("%02x",update_data_buf[i]);
            }
#endif // PYJ.2019.07.15_END -- 
        cnt = 0;
        if(update_data_buf[0] == 0xbe){
 80024e2:	7823      	ldrb	r3, [r4, #0]
        cnt = 0;
 80024e4:	6015      	str	r5, [r2, #0]
        if(update_data_buf[0] == 0xbe){
 80024e6:	2bbe      	cmp	r3, #190	; 0xbe
 80024e8:	d10c      	bne.n	8002504 <GetDataFromUartQueue+0x50>
            FirmwareUpdateStart(&update_data_buf[0]);
 80024ea:	481d      	ldr	r0, [pc, #116]	; (8002560 <GetDataFromUartQueue+0xac>)
 80024ec:	f7ff fa8a 	bl	8001a04 <FirmwareUpdateStart>
               else{
                    printf("CHECK SUM ERR %x \r\n",update_data_buf[MBIC_CHECKSHUM_INDEX]);
               }
            }
        for(int i  = 0; i < QUEUE_BUFFER_LENGTH; i++)
            update_data_buf[i] = 0;
 80024f0:	2300      	movs	r3, #0
        for(int i  = 0; i < QUEUE_BUFFER_LENGTH; i++)
 80024f2:	f240 424c 	movw	r2, #1100	; 0x44c
            update_data_buf[i] = 0;
 80024f6:	5563      	strb	r3, [r4, r5]
        for(int i  = 0; i < QUEUE_BUFFER_LENGTH; i++)
 80024f8:	3501      	adds	r5, #1
 80024fa:	4295      	cmp	r5, r2
 80024fc:	d1fb      	bne.n	80024f6 <GetDataFromUartQueue+0x42>
        
        FirmwareTimerCnt = 0;
 80024fe:	4a1a      	ldr	r2, [pc, #104]	; (8002568 <GetDataFromUartQueue+0xb4>)
 8002500:	6013      	str	r3, [r2, #0]
 8002502:	bd70      	pop	{r4, r5, r6, pc}
        else if(update_data_buf[0] == MBIC_PREAMBLE0
 8002504:	2b16      	cmp	r3, #22
 8002506:	d1f3      	bne.n	80024f0 <GetDataFromUartQueue+0x3c>
               &&update_data_buf[1] == MBIC_PREAMBLE1
 8002508:	7863      	ldrb	r3, [r4, #1]
 800250a:	2b16      	cmp	r3, #22
 800250c:	d1f0      	bne.n	80024f0 <GetDataFromUartQueue+0x3c>
               &&update_data_buf[2] == MBIC_PREAMBLE2
 800250e:	78a3      	ldrb	r3, [r4, #2]
 8002510:	2b16      	cmp	r3, #22
 8002512:	d1ed      	bne.n	80024f0 <GetDataFromUartQueue+0x3c>
               &&update_data_buf[3] == MBIC_PREAMBLE3){
 8002514:	78e3      	ldrb	r3, [r4, #3]
 8002516:	2b16      	cmp	r3, #22
 8002518:	d1ea      	bne.n	80024f0 <GetDataFromUartQueue+0x3c>
               if(Chksum_Check(update_data_buf,MBIC_HEADER_SIZE - 4,update_data_buf[MBIC_CHECKSHUM_INDEX])){
 800251a:	7d62      	ldrb	r2, [r4, #21]
 800251c:	2112      	movs	r1, #18
 800251e:	4810      	ldr	r0, [pc, #64]	; (8002560 <GetDataFromUartQueue+0xac>)
 8002520:	f7ff fac2 	bl	8001aa8 <Chksum_Check>
 8002524:	b1b0      	cbz	r0, 8002554 <GetDataFromUartQueue+0xa0>
                Length = ((update_data_buf[MBIC_LENGTH_0] << 8) | update_data_buf[MBIC_LENGTH_1]);
 8002526:	7ce3      	ldrb	r3, [r4, #19]
 8002528:	7d21      	ldrb	r1, [r4, #20]
                    if(CRC16_Check(&update_data_buf[MBIC_PAYLOADSTART], Length,CrcChk)){
 800252a:	4810      	ldr	r0, [pc, #64]	; (800256c <GetDataFromUartQueue+0xb8>)
                CrcChk = ((update_data_buf[MBIC_PAYLOADSTART + Length + 1] << 8) | (update_data_buf[MBIC_PAYLOADSTART + Length + 2]));
 800252c:	ea41 2103 	orr.w	r1, r1, r3, lsl #8
 8002530:	1863      	adds	r3, r4, r1
 8002532:	7dda      	ldrb	r2, [r3, #23]
 8002534:	7e1e      	ldrb	r6, [r3, #24]
 8002536:	ea46 2602 	orr.w	r6, r6, r2, lsl #8
                    if(CRC16_Check(&update_data_buf[MBIC_PAYLOADSTART], Length,CrcChk)){
 800253a:	4632      	mov	r2, r6
 800253c:	f7ff faf2 	bl	8001b24 <CRC16_Check>
 8002540:	b118      	cbz	r0, 800254a <GetDataFromUartQueue+0x96>
                       MBIC_Bootloader_FirmwareUpdate(&update_data_buf[0]);
 8002542:	4807      	ldr	r0, [pc, #28]	; (8002560 <GetDataFromUartQueue+0xac>)
 8002544:	f7ff fbc8 	bl	8001cd8 <MBIC_Bootloader_FirmwareUpdate>
 8002548:	e7d2      	b.n	80024f0 <GetDataFromUartQueue+0x3c>
                        printf("CRC ERR %x \r\n",CrcChk);
 800254a:	4631      	mov	r1, r6
 800254c:	4808      	ldr	r0, [pc, #32]	; (8002570 <GetDataFromUartQueue+0xbc>)
                    printf("CHECK SUM ERR %x \r\n",update_data_buf[MBIC_CHECKSHUM_INDEX]);
 800254e:	f000 f89b 	bl	8002688 <iprintf>
 8002552:	e7cd      	b.n	80024f0 <GetDataFromUartQueue+0x3c>
 8002554:	7d61      	ldrb	r1, [r4, #21]
 8002556:	4807      	ldr	r0, [pc, #28]	; (8002574 <GetDataFromUartQueue+0xc0>)
 8002558:	e7f9      	b.n	800254e <GetDataFromUartQueue+0x9a>
 800255a:	bf00      	nop
 800255c:	200002e8 	.word	0x200002e8
 8002560:	200008cc 	.word	0x200008cc
 8002564:	20000474 	.word	0x20000474
 8002568:	200002d8 	.word	0x200002d8
 800256c:	200008e2 	.word	0x200008e2
 8002570:	08003765 	.word	0x08003765
 8002574:	08003773 	.word	0x08003773

08002578 <HAL_UART_RxCpltCallback>:
    UartTimerCnt = 0;
 8002578:	2200      	movs	r2, #0
 800257a:	4b0e      	ldr	r3, [pc, #56]	; (80025b4 <HAL_UART_RxCpltCallback+0x3c>)
{
 800257c:	b510      	push	{r4, lr}
    UartTimerCnt = 0;
 800257e:	601a      	str	r2, [r3, #0]
    if (pQueue->head >= QUEUE_BUFFER_LENGTH) pQueue->head = 0;
 8002580:	f240 424b 	movw	r2, #1099	; 0x44b
    pQueue->head++;
 8002584:	4c0c      	ldr	r4, [pc, #48]	; (80025b8 <HAL_UART_RxCpltCallback+0x40>)
 8002586:	6823      	ldr	r3, [r4, #0]
 8002588:	3301      	adds	r3, #1
 800258a:	4293      	cmp	r3, r2
 800258c:	bfc8      	it	gt
 800258e:	2300      	movgt	r3, #0
 8002590:	6023      	str	r3, [r4, #0]
    pQueue->data++;
 8002592:	68a3      	ldr	r3, [r4, #8]
 8002594:	3301      	adds	r3, #1
    if (pQueue->data >= QUEUE_BUFFER_LENGTH)
 8002596:	4293      	cmp	r3, r2
    pQueue->data++;
 8002598:	60a3      	str	r3, [r4, #8]
    if (pQueue->data >= QUEUE_BUFFER_LENGTH)
 800259a:	dd01      	ble.n	80025a0 <HAL_UART_RxCpltCallback+0x28>
        GetDataFromUartQueue(huart);
 800259c:	f7ff ff8a 	bl	80024b4 <GetDataFromUartQueue>
    HAL_UART_Receive_DMA(&hTerminal, pQueue->Buffer + pQueue->head, 1);
 80025a0:	6823      	ldr	r3, [r4, #0]
 80025a2:	4906      	ldr	r1, [pc, #24]	; (80025bc <HAL_UART_RxCpltCallback+0x44>)
 80025a4:	2201      	movs	r2, #1
}
 80025a6:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
    HAL_UART_Receive_DMA(&hTerminal, pQueue->Buffer + pQueue->head, 1);
 80025aa:	4419      	add	r1, r3
 80025ac:	4804      	ldr	r0, [pc, #16]	; (80025c0 <HAL_UART_RxCpltCallback+0x48>)
 80025ae:	f7ff b89f 	b.w	80016f0 <HAL_UART_Receive_DMA>
 80025b2:	bf00      	nop
 80025b4:	200002e0 	.word	0x200002e0
 80025b8:	20000474 	.word	0x20000474
 80025bc:	20000480 	.word	0x20000480
 80025c0:	200003f4 	.word	0x200003f4

080025c4 <Uart1_Data_Send>:

}

void Uart1_Data_Send(uint8_t* data,uint16_t size){
//    printf("size : %d \r\n",size);
    HAL_UART_Transmit(&huart1, data, size, 0xFFFF);
 80025c4:	460a      	mov	r2, r1
 80025c6:	f64f 73ff 	movw	r3, #65535	; 0xffff
 80025ca:	4601      	mov	r1, r0
 80025cc:	4801      	ldr	r0, [pc, #4]	; (80025d4 <Uart1_Data_Send+0x10>)
 80025ce:	f7ff b833 	b.w	8001638 <HAL_UART_Transmit>
 80025d2:	bf00      	nop
 80025d4:	200003f4 	.word	0x200003f4

080025d8 <Reset_Handler>:
  .weak Reset_Handler
  .type Reset_Handler, %function
Reset_Handler:

/* Copy the data segment initializers from flash to SRAM */
  movs r1, #0
 80025d8:	2100      	movs	r1, #0
  b LoopCopyDataInit
 80025da:	e003      	b.n	80025e4 <LoopCopyDataInit>

080025dc <CopyDataInit>:

CopyDataInit:
  ldr r3, =_sidata
 80025dc:	4b0b      	ldr	r3, [pc, #44]	; (800260c <LoopFillZerobss+0x14>)
  ldr r3, [r3, r1]
 80025de:	585b      	ldr	r3, [r3, r1]
  str r3, [r0, r1]
 80025e0:	5043      	str	r3, [r0, r1]
  adds r1, r1, #4
 80025e2:	3104      	adds	r1, #4

080025e4 <LoopCopyDataInit>:

LoopCopyDataInit:
  ldr r0, =_sdata
 80025e4:	480a      	ldr	r0, [pc, #40]	; (8002610 <LoopFillZerobss+0x18>)
  ldr r3, =_edata
 80025e6:	4b0b      	ldr	r3, [pc, #44]	; (8002614 <LoopFillZerobss+0x1c>)
  adds r2, r0, r1
 80025e8:	1842      	adds	r2, r0, r1
  cmp r2, r3
 80025ea:	429a      	cmp	r2, r3
  bcc CopyDataInit
 80025ec:	d3f6      	bcc.n	80025dc <CopyDataInit>
  ldr r2, =_sbss
 80025ee:	4a0a      	ldr	r2, [pc, #40]	; (8002618 <LoopFillZerobss+0x20>)
  b LoopFillZerobss
 80025f0:	e002      	b.n	80025f8 <LoopFillZerobss>

080025f2 <FillZerobss>:
/* Zero fill the bss segment. */
FillZerobss:
  movs r3, #0
 80025f2:	2300      	movs	r3, #0
  str r3, [r2], #4
 80025f4:	f842 3b04 	str.w	r3, [r2], #4

080025f8 <LoopFillZerobss>:

LoopFillZerobss:
  ldr r3, = _ebss
 80025f8:	4b08      	ldr	r3, [pc, #32]	; (800261c <LoopFillZerobss+0x24>)
  cmp r2, r3
 80025fa:	429a      	cmp	r2, r3
  bcc FillZerobss
 80025fc:	d3f9      	bcc.n	80025f2 <FillZerobss>

/* Call the clock system intitialization function.*/
    bl  SystemInit
 80025fe:	f7ff ff25 	bl	800244c <SystemInit>
/* Call static constructors */
    bl __libc_init_array
 8002602:	f000 f815 	bl	8002630 <__libc_init_array>
/* Call the application's entry point.*/
  bl main
 8002606:	f7ff fd19 	bl	800203c <main>
  bx lr
 800260a:	4770      	bx	lr
  ldr r3, =_sidata
 800260c:	08003828 	.word	0x08003828
  ldr r0, =_sdata
 8002610:	20000000 	.word	0x20000000
  ldr r3, =_edata
 8002614:	20000280 	.word	0x20000280
  ldr r2, =_sbss
 8002618:	20000280 	.word	0x20000280
  ldr r3, = _ebss
 800261c:	20001174 	.word	0x20001174

08002620 <ADC1_2_IRQHandler>:
 * @retval : None
*/
    .section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
  b Infinite_Loop
 8002620:	e7fe      	b.n	8002620 <ADC1_2_IRQHandler>
	...

08002624 <__errno>:
 8002624:	4b01      	ldr	r3, [pc, #4]	; (800262c <__errno+0x8>)
 8002626:	6818      	ldr	r0, [r3, #0]
 8002628:	4770      	bx	lr
 800262a:	bf00      	nop
 800262c:	2000021c 	.word	0x2000021c

08002630 <__libc_init_array>:
 8002630:	b570      	push	{r4, r5, r6, lr}
 8002632:	2500      	movs	r5, #0
 8002634:	4e0c      	ldr	r6, [pc, #48]	; (8002668 <__libc_init_array+0x38>)
 8002636:	4c0d      	ldr	r4, [pc, #52]	; (800266c <__libc_init_array+0x3c>)
 8002638:	1ba4      	subs	r4, r4, r6
 800263a:	10a4      	asrs	r4, r4, #2
 800263c:	42a5      	cmp	r5, r4
 800263e:	d109      	bne.n	8002654 <__libc_init_array+0x24>
 8002640:	f001 f848 	bl	80036d4 <_init>
 8002644:	2500      	movs	r5, #0
 8002646:	4e0a      	ldr	r6, [pc, #40]	; (8002670 <__libc_init_array+0x40>)
 8002648:	4c0a      	ldr	r4, [pc, #40]	; (8002674 <__libc_init_array+0x44>)
 800264a:	1ba4      	subs	r4, r4, r6
 800264c:	10a4      	asrs	r4, r4, #2
 800264e:	42a5      	cmp	r5, r4
 8002650:	d105      	bne.n	800265e <__libc_init_array+0x2e>
 8002652:	bd70      	pop	{r4, r5, r6, pc}
 8002654:	f856 3025 	ldr.w	r3, [r6, r5, lsl #2]
 8002658:	4798      	blx	r3
 800265a:	3501      	adds	r5, #1
 800265c:	e7ee      	b.n	800263c <__libc_init_array+0xc>
 800265e:	f856 3025 	ldr.w	r3, [r6, r5, lsl #2]
 8002662:	4798      	blx	r3
 8002664:	3501      	adds	r5, #1
 8002666:	e7f2      	b.n	800264e <__libc_init_array+0x1e>
 8002668:	08003820 	.word	0x08003820
 800266c:	08003820 	.word	0x08003820
 8002670:	08003820 	.word	0x08003820
 8002674:	08003824 	.word	0x08003824

08002678 <memset>:
 8002678:	4603      	mov	r3, r0
 800267a:	4402      	add	r2, r0
 800267c:	4293      	cmp	r3, r2
 800267e:	d100      	bne.n	8002682 <memset+0xa>
 8002680:	4770      	bx	lr
 8002682:	f803 1b01 	strb.w	r1, [r3], #1
 8002686:	e7f9      	b.n	800267c <memset+0x4>

08002688 <iprintf>:
 8002688:	b40f      	push	{r0, r1, r2, r3}
 800268a:	4b0a      	ldr	r3, [pc, #40]	; (80026b4 <iprintf+0x2c>)
 800268c:	b513      	push	{r0, r1, r4, lr}
 800268e:	681c      	ldr	r4, [r3, #0]
 8002690:	b124      	cbz	r4, 800269c <iprintf+0x14>
 8002692:	69a3      	ldr	r3, [r4, #24]
 8002694:	b913      	cbnz	r3, 800269c <iprintf+0x14>
 8002696:	4620      	mov	r0, r4
 8002698:	f000 fada 	bl	8002c50 <__sinit>
 800269c:	ab05      	add	r3, sp, #20
 800269e:	9a04      	ldr	r2, [sp, #16]
 80026a0:	68a1      	ldr	r1, [r4, #8]
 80026a2:	4620      	mov	r0, r4
 80026a4:	9301      	str	r3, [sp, #4]
 80026a6:	f000 fc9b 	bl	8002fe0 <_vfiprintf_r>
 80026aa:	b002      	add	sp, #8
 80026ac:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
 80026b0:	b004      	add	sp, #16
 80026b2:	4770      	bx	lr
 80026b4:	2000021c 	.word	0x2000021c

080026b8 <_puts_r>:
 80026b8:	b570      	push	{r4, r5, r6, lr}
 80026ba:	460e      	mov	r6, r1
 80026bc:	4605      	mov	r5, r0
 80026be:	b118      	cbz	r0, 80026c8 <_puts_r+0x10>
 80026c0:	6983      	ldr	r3, [r0, #24]
 80026c2:	b90b      	cbnz	r3, 80026c8 <_puts_r+0x10>
 80026c4:	f000 fac4 	bl	8002c50 <__sinit>
 80026c8:	69ab      	ldr	r3, [r5, #24]
 80026ca:	68ac      	ldr	r4, [r5, #8]
 80026cc:	b913      	cbnz	r3, 80026d4 <_puts_r+0x1c>
 80026ce:	4628      	mov	r0, r5
 80026d0:	f000 fabe 	bl	8002c50 <__sinit>
 80026d4:	4b23      	ldr	r3, [pc, #140]	; (8002764 <_puts_r+0xac>)
 80026d6:	429c      	cmp	r4, r3
 80026d8:	d117      	bne.n	800270a <_puts_r+0x52>
 80026da:	686c      	ldr	r4, [r5, #4]
 80026dc:	89a3      	ldrh	r3, [r4, #12]
 80026de:	071b      	lsls	r3, r3, #28
 80026e0:	d51d      	bpl.n	800271e <_puts_r+0x66>
 80026e2:	6923      	ldr	r3, [r4, #16]
 80026e4:	b1db      	cbz	r3, 800271e <_puts_r+0x66>
 80026e6:	3e01      	subs	r6, #1
 80026e8:	68a3      	ldr	r3, [r4, #8]
 80026ea:	f816 1f01 	ldrb.w	r1, [r6, #1]!
 80026ee:	3b01      	subs	r3, #1
 80026f0:	60a3      	str	r3, [r4, #8]
 80026f2:	b9e9      	cbnz	r1, 8002730 <_puts_r+0x78>
 80026f4:	2b00      	cmp	r3, #0
 80026f6:	da2e      	bge.n	8002756 <_puts_r+0x9e>
 80026f8:	4622      	mov	r2, r4
 80026fa:	210a      	movs	r1, #10
 80026fc:	4628      	mov	r0, r5
 80026fe:	f000 f8f5 	bl	80028ec <__swbuf_r>
 8002702:	3001      	adds	r0, #1
 8002704:	d011      	beq.n	800272a <_puts_r+0x72>
 8002706:	200a      	movs	r0, #10
 8002708:	bd70      	pop	{r4, r5, r6, pc}
 800270a:	4b17      	ldr	r3, [pc, #92]	; (8002768 <_puts_r+0xb0>)
 800270c:	429c      	cmp	r4, r3
 800270e:	d101      	bne.n	8002714 <_puts_r+0x5c>
 8002710:	68ac      	ldr	r4, [r5, #8]
 8002712:	e7e3      	b.n	80026dc <_puts_r+0x24>
 8002714:	4b15      	ldr	r3, [pc, #84]	; (800276c <_puts_r+0xb4>)
 8002716:	429c      	cmp	r4, r3
 8002718:	bf08      	it	eq
 800271a:	68ec      	ldreq	r4, [r5, #12]
 800271c:	e7de      	b.n	80026dc <_puts_r+0x24>
 800271e:	4621      	mov	r1, r4
 8002720:	4628      	mov	r0, r5
 8002722:	f000 f935 	bl	8002990 <__swsetup_r>
 8002726:	2800      	cmp	r0, #0
 8002728:	d0dd      	beq.n	80026e6 <_puts_r+0x2e>
 800272a:	f04f 30ff 	mov.w	r0, #4294967295
 800272e:	bd70      	pop	{r4, r5, r6, pc}
 8002730:	2b00      	cmp	r3, #0
 8002732:	da04      	bge.n	800273e <_puts_r+0x86>
 8002734:	69a2      	ldr	r2, [r4, #24]
 8002736:	4293      	cmp	r3, r2
 8002738:	db06      	blt.n	8002748 <_puts_r+0x90>
 800273a:	290a      	cmp	r1, #10
 800273c:	d004      	beq.n	8002748 <_puts_r+0x90>
 800273e:	6823      	ldr	r3, [r4, #0]
 8002740:	1c5a      	adds	r2, r3, #1
 8002742:	6022      	str	r2, [r4, #0]
 8002744:	7019      	strb	r1, [r3, #0]
 8002746:	e7cf      	b.n	80026e8 <_puts_r+0x30>
 8002748:	4622      	mov	r2, r4
 800274a:	4628      	mov	r0, r5
 800274c:	f000 f8ce 	bl	80028ec <__swbuf_r>
 8002750:	3001      	adds	r0, #1
 8002752:	d1c9      	bne.n	80026e8 <_puts_r+0x30>
 8002754:	e7e9      	b.n	800272a <_puts_r+0x72>
 8002756:	200a      	movs	r0, #10
 8002758:	6823      	ldr	r3, [r4, #0]
 800275a:	1c5a      	adds	r2, r3, #1
 800275c:	6022      	str	r2, [r4, #0]
 800275e:	7018      	strb	r0, [r3, #0]
 8002760:	bd70      	pop	{r4, r5, r6, pc}
 8002762:	bf00      	nop
 8002764:	080037ac 	.word	0x080037ac
 8002768:	080037cc 	.word	0x080037cc
 800276c:	0800378c 	.word	0x0800378c

08002770 <puts>:
 8002770:	4b02      	ldr	r3, [pc, #8]	; (800277c <puts+0xc>)
 8002772:	4601      	mov	r1, r0
 8002774:	6818      	ldr	r0, [r3, #0]
 8002776:	f7ff bf9f 	b.w	80026b8 <_puts_r>
 800277a:	bf00      	nop
 800277c:	2000021c 	.word	0x2000021c

08002780 <setbuf>:
 8002780:	2900      	cmp	r1, #0
 8002782:	f44f 6380 	mov.w	r3, #1024	; 0x400
 8002786:	bf0c      	ite	eq
 8002788:	2202      	moveq	r2, #2
 800278a:	2200      	movne	r2, #0
 800278c:	f000 b800 	b.w	8002790 <setvbuf>

08002790 <setvbuf>:
 8002790:	e92d 43f7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
 8002794:	461d      	mov	r5, r3
 8002796:	4b51      	ldr	r3, [pc, #324]	; (80028dc <setvbuf+0x14c>)
 8002798:	4604      	mov	r4, r0
 800279a:	681e      	ldr	r6, [r3, #0]
 800279c:	460f      	mov	r7, r1
 800279e:	4690      	mov	r8, r2
 80027a0:	b126      	cbz	r6, 80027ac <setvbuf+0x1c>
 80027a2:	69b3      	ldr	r3, [r6, #24]
 80027a4:	b913      	cbnz	r3, 80027ac <setvbuf+0x1c>
 80027a6:	4630      	mov	r0, r6
 80027a8:	f000 fa52 	bl	8002c50 <__sinit>
 80027ac:	4b4c      	ldr	r3, [pc, #304]	; (80028e0 <setvbuf+0x150>)
 80027ae:	429c      	cmp	r4, r3
 80027b0:	d152      	bne.n	8002858 <setvbuf+0xc8>
 80027b2:	6874      	ldr	r4, [r6, #4]
 80027b4:	f1b8 0f02 	cmp.w	r8, #2
 80027b8:	d006      	beq.n	80027c8 <setvbuf+0x38>
 80027ba:	f1b8 0f01 	cmp.w	r8, #1
 80027be:	f200 8089 	bhi.w	80028d4 <setvbuf+0x144>
 80027c2:	2d00      	cmp	r5, #0
 80027c4:	f2c0 8086 	blt.w	80028d4 <setvbuf+0x144>
 80027c8:	4621      	mov	r1, r4
 80027ca:	4630      	mov	r0, r6
 80027cc:	f000 f9d6 	bl	8002b7c <_fflush_r>
 80027d0:	6b61      	ldr	r1, [r4, #52]	; 0x34
 80027d2:	b141      	cbz	r1, 80027e6 <setvbuf+0x56>
 80027d4:	f104 0344 	add.w	r3, r4, #68	; 0x44
 80027d8:	4299      	cmp	r1, r3
 80027da:	d002      	beq.n	80027e2 <setvbuf+0x52>
 80027dc:	4630      	mov	r0, r6
 80027de:	f000 fb2d 	bl	8002e3c <_free_r>
 80027e2:	2300      	movs	r3, #0
 80027e4:	6363      	str	r3, [r4, #52]	; 0x34
 80027e6:	2300      	movs	r3, #0
 80027e8:	61a3      	str	r3, [r4, #24]
 80027ea:	6063      	str	r3, [r4, #4]
 80027ec:	89a3      	ldrh	r3, [r4, #12]
 80027ee:	061b      	lsls	r3, r3, #24
 80027f0:	d503      	bpl.n	80027fa <setvbuf+0x6a>
 80027f2:	6921      	ldr	r1, [r4, #16]
 80027f4:	4630      	mov	r0, r6
 80027f6:	f000 fb21 	bl	8002e3c <_free_r>
 80027fa:	89a3      	ldrh	r3, [r4, #12]
 80027fc:	f1b8 0f02 	cmp.w	r8, #2
 8002800:	f423 634a 	bic.w	r3, r3, #3232	; 0xca0
 8002804:	f023 0303 	bic.w	r3, r3, #3
 8002808:	81a3      	strh	r3, [r4, #12]
 800280a:	d05d      	beq.n	80028c8 <setvbuf+0x138>
 800280c:	ab01      	add	r3, sp, #4
 800280e:	466a      	mov	r2, sp
 8002810:	4621      	mov	r1, r4
 8002812:	4630      	mov	r0, r6
 8002814:	f000 faa6 	bl	8002d64 <__swhatbuf_r>
 8002818:	89a3      	ldrh	r3, [r4, #12]
 800281a:	4318      	orrs	r0, r3
 800281c:	81a0      	strh	r0, [r4, #12]
 800281e:	bb2d      	cbnz	r5, 800286c <setvbuf+0xdc>
 8002820:	9d00      	ldr	r5, [sp, #0]
 8002822:	4628      	mov	r0, r5
 8002824:	f000 fb02 	bl	8002e2c <malloc>
 8002828:	4607      	mov	r7, r0
 800282a:	2800      	cmp	r0, #0
 800282c:	d14e      	bne.n	80028cc <setvbuf+0x13c>
 800282e:	f8dd 9000 	ldr.w	r9, [sp]
 8002832:	45a9      	cmp	r9, r5
 8002834:	d13c      	bne.n	80028b0 <setvbuf+0x120>
 8002836:	f04f 30ff 	mov.w	r0, #4294967295
 800283a:	89a3      	ldrh	r3, [r4, #12]
 800283c:	f043 0302 	orr.w	r3, r3, #2
 8002840:	81a3      	strh	r3, [r4, #12]
 8002842:	2300      	movs	r3, #0
 8002844:	60a3      	str	r3, [r4, #8]
 8002846:	f104 0347 	add.w	r3, r4, #71	; 0x47
 800284a:	6023      	str	r3, [r4, #0]
 800284c:	6123      	str	r3, [r4, #16]
 800284e:	2301      	movs	r3, #1
 8002850:	6163      	str	r3, [r4, #20]
 8002852:	b003      	add	sp, #12
 8002854:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
 8002858:	4b22      	ldr	r3, [pc, #136]	; (80028e4 <setvbuf+0x154>)
 800285a:	429c      	cmp	r4, r3
 800285c:	d101      	bne.n	8002862 <setvbuf+0xd2>
 800285e:	68b4      	ldr	r4, [r6, #8]
 8002860:	e7a8      	b.n	80027b4 <setvbuf+0x24>
 8002862:	4b21      	ldr	r3, [pc, #132]	; (80028e8 <setvbuf+0x158>)
 8002864:	429c      	cmp	r4, r3
 8002866:	bf08      	it	eq
 8002868:	68f4      	ldreq	r4, [r6, #12]
 800286a:	e7a3      	b.n	80027b4 <setvbuf+0x24>
 800286c:	2f00      	cmp	r7, #0
 800286e:	d0d8      	beq.n	8002822 <setvbuf+0x92>
 8002870:	69b3      	ldr	r3, [r6, #24]
 8002872:	b913      	cbnz	r3, 800287a <setvbuf+0xea>
 8002874:	4630      	mov	r0, r6
 8002876:	f000 f9eb 	bl	8002c50 <__sinit>
 800287a:	f1b8 0f01 	cmp.w	r8, #1
 800287e:	bf08      	it	eq
 8002880:	89a3      	ldrheq	r3, [r4, #12]
 8002882:	6027      	str	r7, [r4, #0]
 8002884:	bf04      	itt	eq
 8002886:	f043 0301 	orreq.w	r3, r3, #1
 800288a:	81a3      	strheq	r3, [r4, #12]
 800288c:	89a3      	ldrh	r3, [r4, #12]
 800288e:	6127      	str	r7, [r4, #16]
 8002890:	f013 0008 	ands.w	r0, r3, #8
 8002894:	6165      	str	r5, [r4, #20]
 8002896:	d01b      	beq.n	80028d0 <setvbuf+0x140>
 8002898:	f013 0001 	ands.w	r0, r3, #1
 800289c:	f04f 0300 	mov.w	r3, #0
 80028a0:	bf1f      	itttt	ne
 80028a2:	426d      	negne	r5, r5
 80028a4:	60a3      	strne	r3, [r4, #8]
 80028a6:	61a5      	strne	r5, [r4, #24]
 80028a8:	4618      	movne	r0, r3
 80028aa:	bf08      	it	eq
 80028ac:	60a5      	streq	r5, [r4, #8]
 80028ae:	e7d0      	b.n	8002852 <setvbuf+0xc2>
 80028b0:	4648      	mov	r0, r9
 80028b2:	f000 fabb 	bl	8002e2c <malloc>
 80028b6:	4607      	mov	r7, r0
 80028b8:	2800      	cmp	r0, #0
 80028ba:	d0bc      	beq.n	8002836 <setvbuf+0xa6>
 80028bc:	89a3      	ldrh	r3, [r4, #12]
 80028be:	464d      	mov	r5, r9
 80028c0:	f043 0380 	orr.w	r3, r3, #128	; 0x80
 80028c4:	81a3      	strh	r3, [r4, #12]
 80028c6:	e7d3      	b.n	8002870 <setvbuf+0xe0>
 80028c8:	2000      	movs	r0, #0
 80028ca:	e7b6      	b.n	800283a <setvbuf+0xaa>
 80028cc:	46a9      	mov	r9, r5
 80028ce:	e7f5      	b.n	80028bc <setvbuf+0x12c>
 80028d0:	60a0      	str	r0, [r4, #8]
 80028d2:	e7be      	b.n	8002852 <setvbuf+0xc2>
 80028d4:	f04f 30ff 	mov.w	r0, #4294967295
 80028d8:	e7bb      	b.n	8002852 <setvbuf+0xc2>
 80028da:	bf00      	nop
 80028dc:	2000021c 	.word	0x2000021c
 80028e0:	080037ac 	.word	0x080037ac
 80028e4:	080037cc 	.word	0x080037cc
 80028e8:	0800378c 	.word	0x0800378c

080028ec <__swbuf_r>:
 80028ec:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 80028ee:	460e      	mov	r6, r1
 80028f0:	4614      	mov	r4, r2
 80028f2:	4605      	mov	r5, r0
 80028f4:	b118      	cbz	r0, 80028fe <__swbuf_r+0x12>
 80028f6:	6983      	ldr	r3, [r0, #24]
 80028f8:	b90b      	cbnz	r3, 80028fe <__swbuf_r+0x12>
 80028fa:	f000 f9a9 	bl	8002c50 <__sinit>
 80028fe:	4b21      	ldr	r3, [pc, #132]	; (8002984 <__swbuf_r+0x98>)
 8002900:	429c      	cmp	r4, r3
 8002902:	d12a      	bne.n	800295a <__swbuf_r+0x6e>
 8002904:	686c      	ldr	r4, [r5, #4]
 8002906:	69a3      	ldr	r3, [r4, #24]
 8002908:	60a3      	str	r3, [r4, #8]
 800290a:	89a3      	ldrh	r3, [r4, #12]
 800290c:	071a      	lsls	r2, r3, #28
 800290e:	d52e      	bpl.n	800296e <__swbuf_r+0x82>
 8002910:	6923      	ldr	r3, [r4, #16]
 8002912:	b363      	cbz	r3, 800296e <__swbuf_r+0x82>
 8002914:	6923      	ldr	r3, [r4, #16]
 8002916:	6820      	ldr	r0, [r4, #0]
 8002918:	b2f6      	uxtb	r6, r6
 800291a:	1ac0      	subs	r0, r0, r3
 800291c:	6963      	ldr	r3, [r4, #20]
 800291e:	4637      	mov	r7, r6
 8002920:	4298      	cmp	r0, r3
 8002922:	db04      	blt.n	800292e <__swbuf_r+0x42>
 8002924:	4621      	mov	r1, r4
 8002926:	4628      	mov	r0, r5
 8002928:	f000 f928 	bl	8002b7c <_fflush_r>
 800292c:	bb28      	cbnz	r0, 800297a <__swbuf_r+0x8e>
 800292e:	68a3      	ldr	r3, [r4, #8]
 8002930:	3001      	adds	r0, #1
 8002932:	3b01      	subs	r3, #1
 8002934:	60a3      	str	r3, [r4, #8]
 8002936:	6823      	ldr	r3, [r4, #0]
 8002938:	1c5a      	adds	r2, r3, #1
 800293a:	6022      	str	r2, [r4, #0]
 800293c:	701e      	strb	r6, [r3, #0]
 800293e:	6963      	ldr	r3, [r4, #20]
 8002940:	4298      	cmp	r0, r3
 8002942:	d004      	beq.n	800294e <__swbuf_r+0x62>
 8002944:	89a3      	ldrh	r3, [r4, #12]
 8002946:	07db      	lsls	r3, r3, #31
 8002948:	d519      	bpl.n	800297e <__swbuf_r+0x92>
 800294a:	2e0a      	cmp	r6, #10
 800294c:	d117      	bne.n	800297e <__swbuf_r+0x92>
 800294e:	4621      	mov	r1, r4
 8002950:	4628      	mov	r0, r5
 8002952:	f000 f913 	bl	8002b7c <_fflush_r>
 8002956:	b190      	cbz	r0, 800297e <__swbuf_r+0x92>
 8002958:	e00f      	b.n	800297a <__swbuf_r+0x8e>
 800295a:	4b0b      	ldr	r3, [pc, #44]	; (8002988 <__swbuf_r+0x9c>)
 800295c:	429c      	cmp	r4, r3
 800295e:	d101      	bne.n	8002964 <__swbuf_r+0x78>
 8002960:	68ac      	ldr	r4, [r5, #8]
 8002962:	e7d0      	b.n	8002906 <__swbuf_r+0x1a>
 8002964:	4b09      	ldr	r3, [pc, #36]	; (800298c <__swbuf_r+0xa0>)
 8002966:	429c      	cmp	r4, r3
 8002968:	bf08      	it	eq
 800296a:	68ec      	ldreq	r4, [r5, #12]
 800296c:	e7cb      	b.n	8002906 <__swbuf_r+0x1a>
 800296e:	4621      	mov	r1, r4
 8002970:	4628      	mov	r0, r5
 8002972:	f000 f80d 	bl	8002990 <__swsetup_r>
 8002976:	2800      	cmp	r0, #0
 8002978:	d0cc      	beq.n	8002914 <__swbuf_r+0x28>
 800297a:	f04f 37ff 	mov.w	r7, #4294967295
 800297e:	4638      	mov	r0, r7
 8002980:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
 8002982:	bf00      	nop
 8002984:	080037ac 	.word	0x080037ac
 8002988:	080037cc 	.word	0x080037cc
 800298c:	0800378c 	.word	0x0800378c

08002990 <__swsetup_r>:
 8002990:	4b32      	ldr	r3, [pc, #200]	; (8002a5c <__swsetup_r+0xcc>)
 8002992:	b570      	push	{r4, r5, r6, lr}
 8002994:	681d      	ldr	r5, [r3, #0]
 8002996:	4606      	mov	r6, r0
 8002998:	460c      	mov	r4, r1
 800299a:	b125      	cbz	r5, 80029a6 <__swsetup_r+0x16>
 800299c:	69ab      	ldr	r3, [r5, #24]
 800299e:	b913      	cbnz	r3, 80029a6 <__swsetup_r+0x16>
 80029a0:	4628      	mov	r0, r5
 80029a2:	f000 f955 	bl	8002c50 <__sinit>
 80029a6:	4b2e      	ldr	r3, [pc, #184]	; (8002a60 <__swsetup_r+0xd0>)
 80029a8:	429c      	cmp	r4, r3
 80029aa:	d10f      	bne.n	80029cc <__swsetup_r+0x3c>
 80029ac:	686c      	ldr	r4, [r5, #4]
 80029ae:	f9b4 300c 	ldrsh.w	r3, [r4, #12]
 80029b2:	b29a      	uxth	r2, r3
 80029b4:	0715      	lsls	r5, r2, #28
 80029b6:	d42c      	bmi.n	8002a12 <__swsetup_r+0x82>
 80029b8:	06d0      	lsls	r0, r2, #27
 80029ba:	d411      	bmi.n	80029e0 <__swsetup_r+0x50>
 80029bc:	2209      	movs	r2, #9
 80029be:	6032      	str	r2, [r6, #0]
 80029c0:	f043 0340 	orr.w	r3, r3, #64	; 0x40
 80029c4:	81a3      	strh	r3, [r4, #12]
 80029c6:	f04f 30ff 	mov.w	r0, #4294967295
 80029ca:	bd70      	pop	{r4, r5, r6, pc}
 80029cc:	4b25      	ldr	r3, [pc, #148]	; (8002a64 <__swsetup_r+0xd4>)
 80029ce:	429c      	cmp	r4, r3
 80029d0:	d101      	bne.n	80029d6 <__swsetup_r+0x46>
 80029d2:	68ac      	ldr	r4, [r5, #8]
 80029d4:	e7eb      	b.n	80029ae <__swsetup_r+0x1e>
 80029d6:	4b24      	ldr	r3, [pc, #144]	; (8002a68 <__swsetup_r+0xd8>)
 80029d8:	429c      	cmp	r4, r3
 80029da:	bf08      	it	eq
 80029dc:	68ec      	ldreq	r4, [r5, #12]
 80029de:	e7e6      	b.n	80029ae <__swsetup_r+0x1e>
 80029e0:	0751      	lsls	r1, r2, #29
 80029e2:	d512      	bpl.n	8002a0a <__swsetup_r+0x7a>
 80029e4:	6b61      	ldr	r1, [r4, #52]	; 0x34
 80029e6:	b141      	cbz	r1, 80029fa <__swsetup_r+0x6a>
 80029e8:	f104 0344 	add.w	r3, r4, #68	; 0x44
 80029ec:	4299      	cmp	r1, r3
 80029ee:	d002      	beq.n	80029f6 <__swsetup_r+0x66>
 80029f0:	4630      	mov	r0, r6
 80029f2:	f000 fa23 	bl	8002e3c <_free_r>
 80029f6:	2300      	movs	r3, #0
 80029f8:	6363      	str	r3, [r4, #52]	; 0x34
 80029fa:	89a3      	ldrh	r3, [r4, #12]
 80029fc:	f023 0324 	bic.w	r3, r3, #36	; 0x24
 8002a00:	81a3      	strh	r3, [r4, #12]
 8002a02:	2300      	movs	r3, #0
 8002a04:	6063      	str	r3, [r4, #4]
 8002a06:	6923      	ldr	r3, [r4, #16]
 8002a08:	6023      	str	r3, [r4, #0]
 8002a0a:	89a3      	ldrh	r3, [r4, #12]
 8002a0c:	f043 0308 	orr.w	r3, r3, #8
 8002a10:	81a3      	strh	r3, [r4, #12]
 8002a12:	6923      	ldr	r3, [r4, #16]
 8002a14:	b94b      	cbnz	r3, 8002a2a <__swsetup_r+0x9a>
 8002a16:	89a3      	ldrh	r3, [r4, #12]
 8002a18:	f403 7320 	and.w	r3, r3, #640	; 0x280
 8002a1c:	f5b3 7f00 	cmp.w	r3, #512	; 0x200
 8002a20:	d003      	beq.n	8002a2a <__swsetup_r+0x9a>
 8002a22:	4621      	mov	r1, r4
 8002a24:	4630      	mov	r0, r6
 8002a26:	f000 f9c1 	bl	8002dac <__smakebuf_r>
 8002a2a:	89a2      	ldrh	r2, [r4, #12]
 8002a2c:	f012 0301 	ands.w	r3, r2, #1
 8002a30:	d00c      	beq.n	8002a4c <__swsetup_r+0xbc>
 8002a32:	2300      	movs	r3, #0
 8002a34:	60a3      	str	r3, [r4, #8]
 8002a36:	6963      	ldr	r3, [r4, #20]
 8002a38:	425b      	negs	r3, r3
 8002a3a:	61a3      	str	r3, [r4, #24]
 8002a3c:	6923      	ldr	r3, [r4, #16]
 8002a3e:	b953      	cbnz	r3, 8002a56 <__swsetup_r+0xc6>
 8002a40:	f9b4 300c 	ldrsh.w	r3, [r4, #12]
 8002a44:	f013 0080 	ands.w	r0, r3, #128	; 0x80
 8002a48:	d1ba      	bne.n	80029c0 <__swsetup_r+0x30>
 8002a4a:	bd70      	pop	{r4, r5, r6, pc}
 8002a4c:	0792      	lsls	r2, r2, #30
 8002a4e:	bf58      	it	pl
 8002a50:	6963      	ldrpl	r3, [r4, #20]
 8002a52:	60a3      	str	r3, [r4, #8]
 8002a54:	e7f2      	b.n	8002a3c <__swsetup_r+0xac>
 8002a56:	2000      	movs	r0, #0
 8002a58:	e7f7      	b.n	8002a4a <__swsetup_r+0xba>
 8002a5a:	bf00      	nop
 8002a5c:	2000021c 	.word	0x2000021c
 8002a60:	080037ac 	.word	0x080037ac
 8002a64:	080037cc 	.word	0x080037cc
 8002a68:	0800378c 	.word	0x0800378c

08002a6c <__sflush_r>:
 8002a6c:	898a      	ldrh	r2, [r1, #12]
 8002a6e:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
 8002a72:	4605      	mov	r5, r0
 8002a74:	0710      	lsls	r0, r2, #28
 8002a76:	460c      	mov	r4, r1
 8002a78:	d45a      	bmi.n	8002b30 <__sflush_r+0xc4>
 8002a7a:	684b      	ldr	r3, [r1, #4]
 8002a7c:	2b00      	cmp	r3, #0
 8002a7e:	dc05      	bgt.n	8002a8c <__sflush_r+0x20>
 8002a80:	6c0b      	ldr	r3, [r1, #64]	; 0x40
 8002a82:	2b00      	cmp	r3, #0
 8002a84:	dc02      	bgt.n	8002a8c <__sflush_r+0x20>
 8002a86:	2000      	movs	r0, #0
 8002a88:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
 8002a8c:	6ae6      	ldr	r6, [r4, #44]	; 0x2c
 8002a8e:	2e00      	cmp	r6, #0
 8002a90:	d0f9      	beq.n	8002a86 <__sflush_r+0x1a>
 8002a92:	2300      	movs	r3, #0
 8002a94:	f412 5280 	ands.w	r2, r2, #4096	; 0x1000
 8002a98:	682f      	ldr	r7, [r5, #0]
 8002a9a:	602b      	str	r3, [r5, #0]
 8002a9c:	d033      	beq.n	8002b06 <__sflush_r+0x9a>
 8002a9e:	6d60      	ldr	r0, [r4, #84]	; 0x54
 8002aa0:	89a3      	ldrh	r3, [r4, #12]
 8002aa2:	075a      	lsls	r2, r3, #29
 8002aa4:	d505      	bpl.n	8002ab2 <__sflush_r+0x46>
 8002aa6:	6863      	ldr	r3, [r4, #4]
 8002aa8:	1ac0      	subs	r0, r0, r3
 8002aaa:	6b63      	ldr	r3, [r4, #52]	; 0x34
 8002aac:	b10b      	cbz	r3, 8002ab2 <__sflush_r+0x46>
 8002aae:	6c23      	ldr	r3, [r4, #64]	; 0x40
 8002ab0:	1ac0      	subs	r0, r0, r3
 8002ab2:	2300      	movs	r3, #0
 8002ab4:	4602      	mov	r2, r0
 8002ab6:	6ae6      	ldr	r6, [r4, #44]	; 0x2c
 8002ab8:	6a21      	ldr	r1, [r4, #32]
 8002aba:	4628      	mov	r0, r5
 8002abc:	47b0      	blx	r6
 8002abe:	1c43      	adds	r3, r0, #1
 8002ac0:	89a3      	ldrh	r3, [r4, #12]
 8002ac2:	d106      	bne.n	8002ad2 <__sflush_r+0x66>
 8002ac4:	6829      	ldr	r1, [r5, #0]
 8002ac6:	291d      	cmp	r1, #29
 8002ac8:	d84b      	bhi.n	8002b62 <__sflush_r+0xf6>
 8002aca:	4a2b      	ldr	r2, [pc, #172]	; (8002b78 <__sflush_r+0x10c>)
 8002acc:	40ca      	lsrs	r2, r1
 8002ace:	07d6      	lsls	r6, r2, #31
 8002ad0:	d547      	bpl.n	8002b62 <__sflush_r+0xf6>
 8002ad2:	2200      	movs	r2, #0
 8002ad4:	6062      	str	r2, [r4, #4]
 8002ad6:	6922      	ldr	r2, [r4, #16]
 8002ad8:	04d9      	lsls	r1, r3, #19
 8002ada:	6022      	str	r2, [r4, #0]
 8002adc:	d504      	bpl.n	8002ae8 <__sflush_r+0x7c>
 8002ade:	1c42      	adds	r2, r0, #1
 8002ae0:	d101      	bne.n	8002ae6 <__sflush_r+0x7a>
 8002ae2:	682b      	ldr	r3, [r5, #0]
 8002ae4:	b903      	cbnz	r3, 8002ae8 <__sflush_r+0x7c>
 8002ae6:	6560      	str	r0, [r4, #84]	; 0x54
 8002ae8:	6b61      	ldr	r1, [r4, #52]	; 0x34
 8002aea:	602f      	str	r7, [r5, #0]
 8002aec:	2900      	cmp	r1, #0
 8002aee:	d0ca      	beq.n	8002a86 <__sflush_r+0x1a>
 8002af0:	f104 0344 	add.w	r3, r4, #68	; 0x44
 8002af4:	4299      	cmp	r1, r3
 8002af6:	d002      	beq.n	8002afe <__sflush_r+0x92>
 8002af8:	4628      	mov	r0, r5
 8002afa:	f000 f99f 	bl	8002e3c <_free_r>
 8002afe:	2000      	movs	r0, #0
 8002b00:	6360      	str	r0, [r4, #52]	; 0x34
 8002b02:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
 8002b06:	6a21      	ldr	r1, [r4, #32]
 8002b08:	2301      	movs	r3, #1
 8002b0a:	4628      	mov	r0, r5
 8002b0c:	47b0      	blx	r6
 8002b0e:	1c41      	adds	r1, r0, #1
 8002b10:	d1c6      	bne.n	8002aa0 <__sflush_r+0x34>
 8002b12:	682b      	ldr	r3, [r5, #0]
 8002b14:	2b00      	cmp	r3, #0
 8002b16:	d0c3      	beq.n	8002aa0 <__sflush_r+0x34>
 8002b18:	2b1d      	cmp	r3, #29
 8002b1a:	d001      	beq.n	8002b20 <__sflush_r+0xb4>
 8002b1c:	2b16      	cmp	r3, #22
 8002b1e:	d101      	bne.n	8002b24 <__sflush_r+0xb8>
 8002b20:	602f      	str	r7, [r5, #0]
 8002b22:	e7b0      	b.n	8002a86 <__sflush_r+0x1a>
 8002b24:	89a3      	ldrh	r3, [r4, #12]
 8002b26:	f043 0340 	orr.w	r3, r3, #64	; 0x40
 8002b2a:	81a3      	strh	r3, [r4, #12]
 8002b2c:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
 8002b30:	690f      	ldr	r7, [r1, #16]
 8002b32:	2f00      	cmp	r7, #0
 8002b34:	d0a7      	beq.n	8002a86 <__sflush_r+0x1a>
 8002b36:	0793      	lsls	r3, r2, #30
 8002b38:	bf18      	it	ne
 8002b3a:	2300      	movne	r3, #0
 8002b3c:	680e      	ldr	r6, [r1, #0]
 8002b3e:	bf08      	it	eq
 8002b40:	694b      	ldreq	r3, [r1, #20]
 8002b42:	eba6 0807 	sub.w	r8, r6, r7
 8002b46:	600f      	str	r7, [r1, #0]
 8002b48:	608b      	str	r3, [r1, #8]
 8002b4a:	f1b8 0f00 	cmp.w	r8, #0
 8002b4e:	dd9a      	ble.n	8002a86 <__sflush_r+0x1a>
 8002b50:	4643      	mov	r3, r8
 8002b52:	463a      	mov	r2, r7
 8002b54:	6a21      	ldr	r1, [r4, #32]
 8002b56:	4628      	mov	r0, r5
 8002b58:	6aa6      	ldr	r6, [r4, #40]	; 0x28
 8002b5a:	47b0      	blx	r6
 8002b5c:	2800      	cmp	r0, #0
 8002b5e:	dc07      	bgt.n	8002b70 <__sflush_r+0x104>
 8002b60:	89a3      	ldrh	r3, [r4, #12]
 8002b62:	f043 0340 	orr.w	r3, r3, #64	; 0x40
 8002b66:	81a3      	strh	r3, [r4, #12]
 8002b68:	f04f 30ff 	mov.w	r0, #4294967295
 8002b6c:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
 8002b70:	4407      	add	r7, r0
 8002b72:	eba8 0800 	sub.w	r8, r8, r0
 8002b76:	e7e8      	b.n	8002b4a <__sflush_r+0xde>
 8002b78:	20400001 	.word	0x20400001

08002b7c <_fflush_r>:
 8002b7c:	b538      	push	{r3, r4, r5, lr}
 8002b7e:	690b      	ldr	r3, [r1, #16]
 8002b80:	4605      	mov	r5, r0
 8002b82:	460c      	mov	r4, r1
 8002b84:	b1db      	cbz	r3, 8002bbe <_fflush_r+0x42>
 8002b86:	b118      	cbz	r0, 8002b90 <_fflush_r+0x14>
 8002b88:	6983      	ldr	r3, [r0, #24]
 8002b8a:	b90b      	cbnz	r3, 8002b90 <_fflush_r+0x14>
 8002b8c:	f000 f860 	bl	8002c50 <__sinit>
 8002b90:	4b0c      	ldr	r3, [pc, #48]	; (8002bc4 <_fflush_r+0x48>)
 8002b92:	429c      	cmp	r4, r3
 8002b94:	d109      	bne.n	8002baa <_fflush_r+0x2e>
 8002b96:	686c      	ldr	r4, [r5, #4]
 8002b98:	f9b4 300c 	ldrsh.w	r3, [r4, #12]
 8002b9c:	b17b      	cbz	r3, 8002bbe <_fflush_r+0x42>
 8002b9e:	4621      	mov	r1, r4
 8002ba0:	4628      	mov	r0, r5
 8002ba2:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
 8002ba6:	f7ff bf61 	b.w	8002a6c <__sflush_r>
 8002baa:	4b07      	ldr	r3, [pc, #28]	; (8002bc8 <_fflush_r+0x4c>)
 8002bac:	429c      	cmp	r4, r3
 8002bae:	d101      	bne.n	8002bb4 <_fflush_r+0x38>
 8002bb0:	68ac      	ldr	r4, [r5, #8]
 8002bb2:	e7f1      	b.n	8002b98 <_fflush_r+0x1c>
 8002bb4:	4b05      	ldr	r3, [pc, #20]	; (8002bcc <_fflush_r+0x50>)
 8002bb6:	429c      	cmp	r4, r3
 8002bb8:	bf08      	it	eq
 8002bba:	68ec      	ldreq	r4, [r5, #12]
 8002bbc:	e7ec      	b.n	8002b98 <_fflush_r+0x1c>
 8002bbe:	2000      	movs	r0, #0
 8002bc0:	bd38      	pop	{r3, r4, r5, pc}
 8002bc2:	bf00      	nop
 8002bc4:	080037ac 	.word	0x080037ac
 8002bc8:	080037cc 	.word	0x080037cc
 8002bcc:	0800378c 	.word	0x0800378c

08002bd0 <_cleanup_r>:
 8002bd0:	4901      	ldr	r1, [pc, #4]	; (8002bd8 <_cleanup_r+0x8>)
 8002bd2:	f000 b8a9 	b.w	8002d28 <_fwalk_reent>
 8002bd6:	bf00      	nop
 8002bd8:	08002b7d 	.word	0x08002b7d

08002bdc <std.isra.0>:
 8002bdc:	2300      	movs	r3, #0
 8002bde:	b510      	push	{r4, lr}
 8002be0:	4604      	mov	r4, r0
 8002be2:	6003      	str	r3, [r0, #0]
 8002be4:	6043      	str	r3, [r0, #4]
 8002be6:	6083      	str	r3, [r0, #8]
 8002be8:	8181      	strh	r1, [r0, #12]
 8002bea:	6643      	str	r3, [r0, #100]	; 0x64
 8002bec:	81c2      	strh	r2, [r0, #14]
 8002bee:	6103      	str	r3, [r0, #16]
 8002bf0:	6143      	str	r3, [r0, #20]
 8002bf2:	6183      	str	r3, [r0, #24]
 8002bf4:	4619      	mov	r1, r3
 8002bf6:	2208      	movs	r2, #8
 8002bf8:	305c      	adds	r0, #92	; 0x5c
 8002bfa:	f7ff fd3d 	bl	8002678 <memset>
 8002bfe:	4b05      	ldr	r3, [pc, #20]	; (8002c14 <std.isra.0+0x38>)
 8002c00:	6224      	str	r4, [r4, #32]
 8002c02:	6263      	str	r3, [r4, #36]	; 0x24
 8002c04:	4b04      	ldr	r3, [pc, #16]	; (8002c18 <std.isra.0+0x3c>)
 8002c06:	62a3      	str	r3, [r4, #40]	; 0x28
 8002c08:	4b04      	ldr	r3, [pc, #16]	; (8002c1c <std.isra.0+0x40>)
 8002c0a:	62e3      	str	r3, [r4, #44]	; 0x2c
 8002c0c:	4b04      	ldr	r3, [pc, #16]	; (8002c20 <std.isra.0+0x44>)
 8002c0e:	6323      	str	r3, [r4, #48]	; 0x30
 8002c10:	bd10      	pop	{r4, pc}
 8002c12:	bf00      	nop
 8002c14:	0800355d 	.word	0x0800355d
 8002c18:	0800357f 	.word	0x0800357f
 8002c1c:	080035b7 	.word	0x080035b7
 8002c20:	080035db 	.word	0x080035db

08002c24 <__sfmoreglue>:
 8002c24:	b570      	push	{r4, r5, r6, lr}
 8002c26:	2568      	movs	r5, #104	; 0x68
 8002c28:	1e4a      	subs	r2, r1, #1
 8002c2a:	4355      	muls	r5, r2
 8002c2c:	460e      	mov	r6, r1
 8002c2e:	f105 0174 	add.w	r1, r5, #116	; 0x74
 8002c32:	f000 f94f 	bl	8002ed4 <_malloc_r>
 8002c36:	4604      	mov	r4, r0
 8002c38:	b140      	cbz	r0, 8002c4c <__sfmoreglue+0x28>
 8002c3a:	2100      	movs	r1, #0
 8002c3c:	e880 0042 	stmia.w	r0, {r1, r6}
 8002c40:	300c      	adds	r0, #12
 8002c42:	60a0      	str	r0, [r4, #8]
 8002c44:	f105 0268 	add.w	r2, r5, #104	; 0x68
 8002c48:	f7ff fd16 	bl	8002678 <memset>
 8002c4c:	4620      	mov	r0, r4
 8002c4e:	bd70      	pop	{r4, r5, r6, pc}

08002c50 <__sinit>:
 8002c50:	6983      	ldr	r3, [r0, #24]
 8002c52:	b510      	push	{r4, lr}
 8002c54:	4604      	mov	r4, r0
 8002c56:	bb33      	cbnz	r3, 8002ca6 <__sinit+0x56>
 8002c58:	6483      	str	r3, [r0, #72]	; 0x48
 8002c5a:	64c3      	str	r3, [r0, #76]	; 0x4c
 8002c5c:	6503      	str	r3, [r0, #80]	; 0x50
 8002c5e:	4b12      	ldr	r3, [pc, #72]	; (8002ca8 <__sinit+0x58>)
 8002c60:	4a12      	ldr	r2, [pc, #72]	; (8002cac <__sinit+0x5c>)
 8002c62:	681b      	ldr	r3, [r3, #0]
 8002c64:	6282      	str	r2, [r0, #40]	; 0x28
 8002c66:	4298      	cmp	r0, r3
 8002c68:	bf04      	itt	eq
 8002c6a:	2301      	moveq	r3, #1
 8002c6c:	6183      	streq	r3, [r0, #24]
 8002c6e:	f000 f81f 	bl	8002cb0 <__sfp>
 8002c72:	6060      	str	r0, [r4, #4]
 8002c74:	4620      	mov	r0, r4
 8002c76:	f000 f81b 	bl	8002cb0 <__sfp>
 8002c7a:	60a0      	str	r0, [r4, #8]
 8002c7c:	4620      	mov	r0, r4
 8002c7e:	f000 f817 	bl	8002cb0 <__sfp>
 8002c82:	2200      	movs	r2, #0
 8002c84:	60e0      	str	r0, [r4, #12]
 8002c86:	2104      	movs	r1, #4
 8002c88:	6860      	ldr	r0, [r4, #4]
 8002c8a:	f7ff ffa7 	bl	8002bdc <std.isra.0>
 8002c8e:	2201      	movs	r2, #1
 8002c90:	2109      	movs	r1, #9
 8002c92:	68a0      	ldr	r0, [r4, #8]
 8002c94:	f7ff ffa2 	bl	8002bdc <std.isra.0>
 8002c98:	2202      	movs	r2, #2
 8002c9a:	2112      	movs	r1, #18
 8002c9c:	68e0      	ldr	r0, [r4, #12]
 8002c9e:	f7ff ff9d 	bl	8002bdc <std.isra.0>
 8002ca2:	2301      	movs	r3, #1
 8002ca4:	61a3      	str	r3, [r4, #24]
 8002ca6:	bd10      	pop	{r4, pc}
 8002ca8:	08003788 	.word	0x08003788
 8002cac:	08002bd1 	.word	0x08002bd1

08002cb0 <__sfp>:
 8002cb0:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 8002cb2:	4b1c      	ldr	r3, [pc, #112]	; (8002d24 <__sfp+0x74>)
 8002cb4:	4607      	mov	r7, r0
 8002cb6:	681e      	ldr	r6, [r3, #0]
 8002cb8:	69b3      	ldr	r3, [r6, #24]
 8002cba:	b913      	cbnz	r3, 8002cc2 <__sfp+0x12>
 8002cbc:	4630      	mov	r0, r6
 8002cbe:	f7ff ffc7 	bl	8002c50 <__sinit>
 8002cc2:	3648      	adds	r6, #72	; 0x48
 8002cc4:	68b4      	ldr	r4, [r6, #8]
 8002cc6:	6873      	ldr	r3, [r6, #4]
 8002cc8:	3b01      	subs	r3, #1
 8002cca:	d503      	bpl.n	8002cd4 <__sfp+0x24>
 8002ccc:	6833      	ldr	r3, [r6, #0]
 8002cce:	b133      	cbz	r3, 8002cde <__sfp+0x2e>
 8002cd0:	6836      	ldr	r6, [r6, #0]
 8002cd2:	e7f7      	b.n	8002cc4 <__sfp+0x14>
 8002cd4:	f9b4 500c 	ldrsh.w	r5, [r4, #12]
 8002cd8:	b16d      	cbz	r5, 8002cf6 <__sfp+0x46>
 8002cda:	3468      	adds	r4, #104	; 0x68
 8002cdc:	e7f4      	b.n	8002cc8 <__sfp+0x18>
 8002cde:	2104      	movs	r1, #4
 8002ce0:	4638      	mov	r0, r7
 8002ce2:	f7ff ff9f 	bl	8002c24 <__sfmoreglue>
 8002ce6:	6030      	str	r0, [r6, #0]
 8002ce8:	2800      	cmp	r0, #0
 8002cea:	d1f1      	bne.n	8002cd0 <__sfp+0x20>
 8002cec:	230c      	movs	r3, #12
 8002cee:	4604      	mov	r4, r0
 8002cf0:	603b      	str	r3, [r7, #0]
 8002cf2:	4620      	mov	r0, r4
 8002cf4:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
 8002cf6:	f64f 73ff 	movw	r3, #65535	; 0xffff
 8002cfa:	81e3      	strh	r3, [r4, #14]
 8002cfc:	2301      	movs	r3, #1
 8002cfe:	6665      	str	r5, [r4, #100]	; 0x64
 8002d00:	81a3      	strh	r3, [r4, #12]
 8002d02:	6025      	str	r5, [r4, #0]
 8002d04:	60a5      	str	r5, [r4, #8]
 8002d06:	6065      	str	r5, [r4, #4]
 8002d08:	6125      	str	r5, [r4, #16]
 8002d0a:	6165      	str	r5, [r4, #20]
 8002d0c:	61a5      	str	r5, [r4, #24]
 8002d0e:	2208      	movs	r2, #8
 8002d10:	4629      	mov	r1, r5
 8002d12:	f104 005c 	add.w	r0, r4, #92	; 0x5c
 8002d16:	f7ff fcaf 	bl	8002678 <memset>
 8002d1a:	6365      	str	r5, [r4, #52]	; 0x34
 8002d1c:	63a5      	str	r5, [r4, #56]	; 0x38
 8002d1e:	64a5      	str	r5, [r4, #72]	; 0x48
 8002d20:	64e5      	str	r5, [r4, #76]	; 0x4c
 8002d22:	e7e6      	b.n	8002cf2 <__sfp+0x42>
 8002d24:	08003788 	.word	0x08003788

08002d28 <_fwalk_reent>:
 8002d28:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
 8002d2c:	4680      	mov	r8, r0
 8002d2e:	4689      	mov	r9, r1
 8002d30:	2600      	movs	r6, #0
 8002d32:	f100 0448 	add.w	r4, r0, #72	; 0x48
 8002d36:	b914      	cbnz	r4, 8002d3e <_fwalk_reent+0x16>
 8002d38:	4630      	mov	r0, r6
 8002d3a:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
 8002d3e:	68a5      	ldr	r5, [r4, #8]
 8002d40:	6867      	ldr	r7, [r4, #4]
 8002d42:	3f01      	subs	r7, #1
 8002d44:	d501      	bpl.n	8002d4a <_fwalk_reent+0x22>
 8002d46:	6824      	ldr	r4, [r4, #0]
 8002d48:	e7f5      	b.n	8002d36 <_fwalk_reent+0xe>
 8002d4a:	89ab      	ldrh	r3, [r5, #12]
 8002d4c:	2b01      	cmp	r3, #1
 8002d4e:	d907      	bls.n	8002d60 <_fwalk_reent+0x38>
 8002d50:	f9b5 300e 	ldrsh.w	r3, [r5, #14]
 8002d54:	3301      	adds	r3, #1
 8002d56:	d003      	beq.n	8002d60 <_fwalk_reent+0x38>
 8002d58:	4629      	mov	r1, r5
 8002d5a:	4640      	mov	r0, r8
 8002d5c:	47c8      	blx	r9
 8002d5e:	4306      	orrs	r6, r0
 8002d60:	3568      	adds	r5, #104	; 0x68
 8002d62:	e7ee      	b.n	8002d42 <_fwalk_reent+0x1a>

08002d64 <__swhatbuf_r>:
 8002d64:	b570      	push	{r4, r5, r6, lr}
 8002d66:	460e      	mov	r6, r1
 8002d68:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 8002d6c:	b090      	sub	sp, #64	; 0x40
 8002d6e:	2900      	cmp	r1, #0
 8002d70:	4614      	mov	r4, r2
 8002d72:	461d      	mov	r5, r3
 8002d74:	da07      	bge.n	8002d86 <__swhatbuf_r+0x22>
 8002d76:	2300      	movs	r3, #0
 8002d78:	602b      	str	r3, [r5, #0]
 8002d7a:	89b3      	ldrh	r3, [r6, #12]
 8002d7c:	061a      	lsls	r2, r3, #24
 8002d7e:	d410      	bmi.n	8002da2 <__swhatbuf_r+0x3e>
 8002d80:	f44f 6380 	mov.w	r3, #1024	; 0x400
 8002d84:	e00e      	b.n	8002da4 <__swhatbuf_r+0x40>
 8002d86:	aa01      	add	r2, sp, #4
 8002d88:	f000 fc4e 	bl	8003628 <_fstat_r>
 8002d8c:	2800      	cmp	r0, #0
 8002d8e:	dbf2      	blt.n	8002d76 <__swhatbuf_r+0x12>
 8002d90:	9a02      	ldr	r2, [sp, #8]
 8002d92:	f402 4270 	and.w	r2, r2, #61440	; 0xf000
 8002d96:	f5a2 5300 	sub.w	r3, r2, #8192	; 0x2000
 8002d9a:	425a      	negs	r2, r3
 8002d9c:	415a      	adcs	r2, r3
 8002d9e:	602a      	str	r2, [r5, #0]
 8002da0:	e7ee      	b.n	8002d80 <__swhatbuf_r+0x1c>
 8002da2:	2340      	movs	r3, #64	; 0x40
 8002da4:	2000      	movs	r0, #0
 8002da6:	6023      	str	r3, [r4, #0]
 8002da8:	b010      	add	sp, #64	; 0x40
 8002daa:	bd70      	pop	{r4, r5, r6, pc}

08002dac <__smakebuf_r>:
 8002dac:	898b      	ldrh	r3, [r1, #12]
 8002dae:	b573      	push	{r0, r1, r4, r5, r6, lr}
 8002db0:	079d      	lsls	r5, r3, #30
 8002db2:	4606      	mov	r6, r0
 8002db4:	460c      	mov	r4, r1
 8002db6:	d507      	bpl.n	8002dc8 <__smakebuf_r+0x1c>
 8002db8:	f104 0347 	add.w	r3, r4, #71	; 0x47
 8002dbc:	6023      	str	r3, [r4, #0]
 8002dbe:	6123      	str	r3, [r4, #16]
 8002dc0:	2301      	movs	r3, #1
 8002dc2:	6163      	str	r3, [r4, #20]
 8002dc4:	b002      	add	sp, #8
 8002dc6:	bd70      	pop	{r4, r5, r6, pc}
 8002dc8:	ab01      	add	r3, sp, #4
 8002dca:	466a      	mov	r2, sp
 8002dcc:	f7ff ffca 	bl	8002d64 <__swhatbuf_r>
 8002dd0:	9900      	ldr	r1, [sp, #0]
 8002dd2:	4605      	mov	r5, r0
 8002dd4:	4630      	mov	r0, r6
 8002dd6:	f000 f87d 	bl	8002ed4 <_malloc_r>
 8002dda:	b948      	cbnz	r0, 8002df0 <__smakebuf_r+0x44>
 8002ddc:	f9b4 300c 	ldrsh.w	r3, [r4, #12]
 8002de0:	059a      	lsls	r2, r3, #22
 8002de2:	d4ef      	bmi.n	8002dc4 <__smakebuf_r+0x18>
 8002de4:	f023 0303 	bic.w	r3, r3, #3
 8002de8:	f043 0302 	orr.w	r3, r3, #2
 8002dec:	81a3      	strh	r3, [r4, #12]
 8002dee:	e7e3      	b.n	8002db8 <__smakebuf_r+0xc>
 8002df0:	4b0d      	ldr	r3, [pc, #52]	; (8002e28 <__smakebuf_r+0x7c>)
 8002df2:	62b3      	str	r3, [r6, #40]	; 0x28
 8002df4:	89a3      	ldrh	r3, [r4, #12]
 8002df6:	6020      	str	r0, [r4, #0]
 8002df8:	f043 0380 	orr.w	r3, r3, #128	; 0x80
 8002dfc:	81a3      	strh	r3, [r4, #12]
 8002dfe:	9b00      	ldr	r3, [sp, #0]
 8002e00:	6120      	str	r0, [r4, #16]
 8002e02:	6163      	str	r3, [r4, #20]
 8002e04:	9b01      	ldr	r3, [sp, #4]
 8002e06:	b15b      	cbz	r3, 8002e20 <__smakebuf_r+0x74>
 8002e08:	f9b4 100e 	ldrsh.w	r1, [r4, #14]
 8002e0c:	4630      	mov	r0, r6
 8002e0e:	f000 fc1d 	bl	800364c <_isatty_r>
 8002e12:	b128      	cbz	r0, 8002e20 <__smakebuf_r+0x74>
 8002e14:	89a3      	ldrh	r3, [r4, #12]
 8002e16:	f023 0303 	bic.w	r3, r3, #3
 8002e1a:	f043 0301 	orr.w	r3, r3, #1
 8002e1e:	81a3      	strh	r3, [r4, #12]
 8002e20:	89a3      	ldrh	r3, [r4, #12]
 8002e22:	431d      	orrs	r5, r3
 8002e24:	81a5      	strh	r5, [r4, #12]
 8002e26:	e7cd      	b.n	8002dc4 <__smakebuf_r+0x18>
 8002e28:	08002bd1 	.word	0x08002bd1

08002e2c <malloc>:
 8002e2c:	4b02      	ldr	r3, [pc, #8]	; (8002e38 <malloc+0xc>)
 8002e2e:	4601      	mov	r1, r0
 8002e30:	6818      	ldr	r0, [r3, #0]
 8002e32:	f000 b84f 	b.w	8002ed4 <_malloc_r>
 8002e36:	bf00      	nop
 8002e38:	2000021c 	.word	0x2000021c

08002e3c <_free_r>:
 8002e3c:	b538      	push	{r3, r4, r5, lr}
 8002e3e:	4605      	mov	r5, r0
 8002e40:	2900      	cmp	r1, #0
 8002e42:	d043      	beq.n	8002ecc <_free_r+0x90>
 8002e44:	f851 3c04 	ldr.w	r3, [r1, #-4]
 8002e48:	1f0c      	subs	r4, r1, #4
 8002e4a:	2b00      	cmp	r3, #0
 8002e4c:	bfb8      	it	lt
 8002e4e:	18e4      	addlt	r4, r4, r3
 8002e50:	f000 fc2c 	bl	80036ac <__malloc_lock>
 8002e54:	4a1e      	ldr	r2, [pc, #120]	; (8002ed0 <_free_r+0x94>)
 8002e56:	6813      	ldr	r3, [r2, #0]
 8002e58:	4610      	mov	r0, r2
 8002e5a:	b933      	cbnz	r3, 8002e6a <_free_r+0x2e>
 8002e5c:	6063      	str	r3, [r4, #4]
 8002e5e:	6014      	str	r4, [r2, #0]
 8002e60:	4628      	mov	r0, r5
 8002e62:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
 8002e66:	f000 bc22 	b.w	80036ae <__malloc_unlock>
 8002e6a:	42a3      	cmp	r3, r4
 8002e6c:	d90b      	bls.n	8002e86 <_free_r+0x4a>
 8002e6e:	6821      	ldr	r1, [r4, #0]
 8002e70:	1862      	adds	r2, r4, r1
 8002e72:	4293      	cmp	r3, r2
 8002e74:	bf01      	itttt	eq
 8002e76:	681a      	ldreq	r2, [r3, #0]
 8002e78:	685b      	ldreq	r3, [r3, #4]
 8002e7a:	1852      	addeq	r2, r2, r1
 8002e7c:	6022      	streq	r2, [r4, #0]
 8002e7e:	6063      	str	r3, [r4, #4]
 8002e80:	6004      	str	r4, [r0, #0]
 8002e82:	e7ed      	b.n	8002e60 <_free_r+0x24>
 8002e84:	4613      	mov	r3, r2
 8002e86:	685a      	ldr	r2, [r3, #4]
 8002e88:	b10a      	cbz	r2, 8002e8e <_free_r+0x52>
 8002e8a:	42a2      	cmp	r2, r4
 8002e8c:	d9fa      	bls.n	8002e84 <_free_r+0x48>
 8002e8e:	6819      	ldr	r1, [r3, #0]
 8002e90:	1858      	adds	r0, r3, r1
 8002e92:	42a0      	cmp	r0, r4
 8002e94:	d10b      	bne.n	8002eae <_free_r+0x72>
 8002e96:	6820      	ldr	r0, [r4, #0]
 8002e98:	4401      	add	r1, r0
 8002e9a:	1858      	adds	r0, r3, r1
 8002e9c:	4282      	cmp	r2, r0
 8002e9e:	6019      	str	r1, [r3, #0]
 8002ea0:	d1de      	bne.n	8002e60 <_free_r+0x24>
 8002ea2:	6810      	ldr	r0, [r2, #0]
 8002ea4:	6852      	ldr	r2, [r2, #4]
 8002ea6:	4401      	add	r1, r0
 8002ea8:	6019      	str	r1, [r3, #0]
 8002eaa:	605a      	str	r2, [r3, #4]
 8002eac:	e7d8      	b.n	8002e60 <_free_r+0x24>
 8002eae:	d902      	bls.n	8002eb6 <_free_r+0x7a>
 8002eb0:	230c      	movs	r3, #12
 8002eb2:	602b      	str	r3, [r5, #0]
 8002eb4:	e7d4      	b.n	8002e60 <_free_r+0x24>
 8002eb6:	6820      	ldr	r0, [r4, #0]
 8002eb8:	1821      	adds	r1, r4, r0
 8002eba:	428a      	cmp	r2, r1
 8002ebc:	bf01      	itttt	eq
 8002ebe:	6811      	ldreq	r1, [r2, #0]
 8002ec0:	6852      	ldreq	r2, [r2, #4]
 8002ec2:	1809      	addeq	r1, r1, r0
 8002ec4:	6021      	streq	r1, [r4, #0]
 8002ec6:	6062      	str	r2, [r4, #4]
 8002ec8:	605c      	str	r4, [r3, #4]
 8002eca:	e7c9      	b.n	8002e60 <_free_r+0x24>
 8002ecc:	bd38      	pop	{r3, r4, r5, pc}
 8002ece:	bf00      	nop
 8002ed0:	200002ec 	.word	0x200002ec

08002ed4 <_malloc_r>:
 8002ed4:	b570      	push	{r4, r5, r6, lr}
 8002ed6:	1ccd      	adds	r5, r1, #3
 8002ed8:	f025 0503 	bic.w	r5, r5, #3
 8002edc:	3508      	adds	r5, #8
 8002ede:	2d0c      	cmp	r5, #12
 8002ee0:	bf38      	it	cc
 8002ee2:	250c      	movcc	r5, #12
 8002ee4:	2d00      	cmp	r5, #0
 8002ee6:	4606      	mov	r6, r0
 8002ee8:	db01      	blt.n	8002eee <_malloc_r+0x1a>
 8002eea:	42a9      	cmp	r1, r5
 8002eec:	d903      	bls.n	8002ef6 <_malloc_r+0x22>
 8002eee:	230c      	movs	r3, #12
 8002ef0:	6033      	str	r3, [r6, #0]
 8002ef2:	2000      	movs	r0, #0
 8002ef4:	bd70      	pop	{r4, r5, r6, pc}
 8002ef6:	f000 fbd9 	bl	80036ac <__malloc_lock>
 8002efa:	4a23      	ldr	r2, [pc, #140]	; (8002f88 <_malloc_r+0xb4>)
 8002efc:	6814      	ldr	r4, [r2, #0]
 8002efe:	4621      	mov	r1, r4
 8002f00:	b991      	cbnz	r1, 8002f28 <_malloc_r+0x54>
 8002f02:	4c22      	ldr	r4, [pc, #136]	; (8002f8c <_malloc_r+0xb8>)
 8002f04:	6823      	ldr	r3, [r4, #0]
 8002f06:	b91b      	cbnz	r3, 8002f10 <_malloc_r+0x3c>
 8002f08:	4630      	mov	r0, r6
 8002f0a:	f000 fb17 	bl	800353c <_sbrk_r>
 8002f0e:	6020      	str	r0, [r4, #0]
 8002f10:	4629      	mov	r1, r5
 8002f12:	4630      	mov	r0, r6
 8002f14:	f000 fb12 	bl	800353c <_sbrk_r>
 8002f18:	1c43      	adds	r3, r0, #1
 8002f1a:	d126      	bne.n	8002f6a <_malloc_r+0x96>
 8002f1c:	230c      	movs	r3, #12
 8002f1e:	4630      	mov	r0, r6
 8002f20:	6033      	str	r3, [r6, #0]
 8002f22:	f000 fbc4 	bl	80036ae <__malloc_unlock>
 8002f26:	e7e4      	b.n	8002ef2 <_malloc_r+0x1e>
 8002f28:	680b      	ldr	r3, [r1, #0]
 8002f2a:	1b5b      	subs	r3, r3, r5
 8002f2c:	d41a      	bmi.n	8002f64 <_malloc_r+0x90>
 8002f2e:	2b0b      	cmp	r3, #11
 8002f30:	d90f      	bls.n	8002f52 <_malloc_r+0x7e>
 8002f32:	600b      	str	r3, [r1, #0]
 8002f34:	18cc      	adds	r4, r1, r3
 8002f36:	50cd      	str	r5, [r1, r3]
 8002f38:	4630      	mov	r0, r6
 8002f3a:	f000 fbb8 	bl	80036ae <__malloc_unlock>
 8002f3e:	f104 000b 	add.w	r0, r4, #11
 8002f42:	1d23      	adds	r3, r4, #4
 8002f44:	f020 0007 	bic.w	r0, r0, #7
 8002f48:	1ac3      	subs	r3, r0, r3
 8002f4a:	d01b      	beq.n	8002f84 <_malloc_r+0xb0>
 8002f4c:	425a      	negs	r2, r3
 8002f4e:	50e2      	str	r2, [r4, r3]
 8002f50:	bd70      	pop	{r4, r5, r6, pc}
 8002f52:	428c      	cmp	r4, r1
 8002f54:	bf0b      	itete	eq
 8002f56:	6863      	ldreq	r3, [r4, #4]
 8002f58:	684b      	ldrne	r3, [r1, #4]
 8002f5a:	6013      	streq	r3, [r2, #0]
 8002f5c:	6063      	strne	r3, [r4, #4]
 8002f5e:	bf18      	it	ne
 8002f60:	460c      	movne	r4, r1
 8002f62:	e7e9      	b.n	8002f38 <_malloc_r+0x64>
 8002f64:	460c      	mov	r4, r1
 8002f66:	6849      	ldr	r1, [r1, #4]
 8002f68:	e7ca      	b.n	8002f00 <_malloc_r+0x2c>
 8002f6a:	1cc4      	adds	r4, r0, #3
 8002f6c:	f024 0403 	bic.w	r4, r4, #3
 8002f70:	42a0      	cmp	r0, r4
 8002f72:	d005      	beq.n	8002f80 <_malloc_r+0xac>
 8002f74:	1a21      	subs	r1, r4, r0
 8002f76:	4630      	mov	r0, r6
 8002f78:	f000 fae0 	bl	800353c <_sbrk_r>
 8002f7c:	3001      	adds	r0, #1
 8002f7e:	d0cd      	beq.n	8002f1c <_malloc_r+0x48>
 8002f80:	6025      	str	r5, [r4, #0]
 8002f82:	e7d9      	b.n	8002f38 <_malloc_r+0x64>
 8002f84:	bd70      	pop	{r4, r5, r6, pc}
 8002f86:	bf00      	nop
 8002f88:	200002ec 	.word	0x200002ec
 8002f8c:	200002f0 	.word	0x200002f0

08002f90 <__sfputc_r>:
 8002f90:	6893      	ldr	r3, [r2, #8]
 8002f92:	b410      	push	{r4}
 8002f94:	3b01      	subs	r3, #1
 8002f96:	2b00      	cmp	r3, #0
 8002f98:	6093      	str	r3, [r2, #8]
 8002f9a:	da08      	bge.n	8002fae <__sfputc_r+0x1e>
 8002f9c:	6994      	ldr	r4, [r2, #24]
 8002f9e:	42a3      	cmp	r3, r4
 8002fa0:	db02      	blt.n	8002fa8 <__sfputc_r+0x18>
 8002fa2:	b2cb      	uxtb	r3, r1
 8002fa4:	2b0a      	cmp	r3, #10
 8002fa6:	d102      	bne.n	8002fae <__sfputc_r+0x1e>
 8002fa8:	bc10      	pop	{r4}
 8002faa:	f7ff bc9f 	b.w	80028ec <__swbuf_r>
 8002fae:	6813      	ldr	r3, [r2, #0]
 8002fb0:	1c58      	adds	r0, r3, #1
 8002fb2:	6010      	str	r0, [r2, #0]
 8002fb4:	7019      	strb	r1, [r3, #0]
 8002fb6:	b2c8      	uxtb	r0, r1
 8002fb8:	bc10      	pop	{r4}
 8002fba:	4770      	bx	lr

08002fbc <__sfputs_r>:
 8002fbc:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 8002fbe:	4606      	mov	r6, r0
 8002fc0:	460f      	mov	r7, r1
 8002fc2:	4614      	mov	r4, r2
 8002fc4:	18d5      	adds	r5, r2, r3
 8002fc6:	42ac      	cmp	r4, r5
 8002fc8:	d101      	bne.n	8002fce <__sfputs_r+0x12>
 8002fca:	2000      	movs	r0, #0
 8002fcc:	e007      	b.n	8002fde <__sfputs_r+0x22>
 8002fce:	463a      	mov	r2, r7
 8002fd0:	f814 1b01 	ldrb.w	r1, [r4], #1
 8002fd4:	4630      	mov	r0, r6
 8002fd6:	f7ff ffdb 	bl	8002f90 <__sfputc_r>
 8002fda:	1c43      	adds	r3, r0, #1
 8002fdc:	d1f3      	bne.n	8002fc6 <__sfputs_r+0xa>
 8002fde:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}

08002fe0 <_vfiprintf_r>:
 8002fe0:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
 8002fe4:	b09d      	sub	sp, #116	; 0x74
 8002fe6:	460c      	mov	r4, r1
 8002fe8:	4617      	mov	r7, r2
 8002fea:	9303      	str	r3, [sp, #12]
 8002fec:	4606      	mov	r6, r0
 8002fee:	b118      	cbz	r0, 8002ff8 <_vfiprintf_r+0x18>
 8002ff0:	6983      	ldr	r3, [r0, #24]
 8002ff2:	b90b      	cbnz	r3, 8002ff8 <_vfiprintf_r+0x18>
 8002ff4:	f7ff fe2c 	bl	8002c50 <__sinit>
 8002ff8:	4b7c      	ldr	r3, [pc, #496]	; (80031ec <_vfiprintf_r+0x20c>)
 8002ffa:	429c      	cmp	r4, r3
 8002ffc:	d157      	bne.n	80030ae <_vfiprintf_r+0xce>
 8002ffe:	6874      	ldr	r4, [r6, #4]
 8003000:	89a3      	ldrh	r3, [r4, #12]
 8003002:	0718      	lsls	r0, r3, #28
 8003004:	d55d      	bpl.n	80030c2 <_vfiprintf_r+0xe2>
 8003006:	6923      	ldr	r3, [r4, #16]
 8003008:	2b00      	cmp	r3, #0
 800300a:	d05a      	beq.n	80030c2 <_vfiprintf_r+0xe2>
 800300c:	2300      	movs	r3, #0
 800300e:	9309      	str	r3, [sp, #36]	; 0x24
 8003010:	2320      	movs	r3, #32
 8003012:	f88d 3029 	strb.w	r3, [sp, #41]	; 0x29
 8003016:	2330      	movs	r3, #48	; 0x30
 8003018:	f04f 0b01 	mov.w	fp, #1
 800301c:	f88d 302a 	strb.w	r3, [sp, #42]	; 0x2a
 8003020:	46b8      	mov	r8, r7
 8003022:	4645      	mov	r5, r8
 8003024:	f815 3b01 	ldrb.w	r3, [r5], #1
 8003028:	2b00      	cmp	r3, #0
 800302a:	d155      	bne.n	80030d8 <_vfiprintf_r+0xf8>
 800302c:	ebb8 0a07 	subs.w	sl, r8, r7
 8003030:	d00b      	beq.n	800304a <_vfiprintf_r+0x6a>
 8003032:	4653      	mov	r3, sl
 8003034:	463a      	mov	r2, r7
 8003036:	4621      	mov	r1, r4
 8003038:	4630      	mov	r0, r6
 800303a:	f7ff ffbf 	bl	8002fbc <__sfputs_r>
 800303e:	3001      	adds	r0, #1
 8003040:	f000 80c4 	beq.w	80031cc <_vfiprintf_r+0x1ec>
 8003044:	9b09      	ldr	r3, [sp, #36]	; 0x24
 8003046:	4453      	add	r3, sl
 8003048:	9309      	str	r3, [sp, #36]	; 0x24
 800304a:	f898 3000 	ldrb.w	r3, [r8]
 800304e:	2b00      	cmp	r3, #0
 8003050:	f000 80bc 	beq.w	80031cc <_vfiprintf_r+0x1ec>
 8003054:	2300      	movs	r3, #0
 8003056:	f04f 32ff 	mov.w	r2, #4294967295
 800305a:	9304      	str	r3, [sp, #16]
 800305c:	9307      	str	r3, [sp, #28]
 800305e:	9205      	str	r2, [sp, #20]
 8003060:	9306      	str	r3, [sp, #24]
 8003062:	f88d 3053 	strb.w	r3, [sp, #83]	; 0x53
 8003066:	931a      	str	r3, [sp, #104]	; 0x68
 8003068:	2205      	movs	r2, #5
 800306a:	7829      	ldrb	r1, [r5, #0]
 800306c:	4860      	ldr	r0, [pc, #384]	; (80031f0 <_vfiprintf_r+0x210>)
 800306e:	f000 fb0f 	bl	8003690 <memchr>
 8003072:	f105 0801 	add.w	r8, r5, #1
 8003076:	9b04      	ldr	r3, [sp, #16]
 8003078:	2800      	cmp	r0, #0
 800307a:	d131      	bne.n	80030e0 <_vfiprintf_r+0x100>
 800307c:	06d9      	lsls	r1, r3, #27
 800307e:	bf44      	itt	mi
 8003080:	2220      	movmi	r2, #32
 8003082:	f88d 2053 	strbmi.w	r2, [sp, #83]	; 0x53
 8003086:	071a      	lsls	r2, r3, #28
 8003088:	bf44      	itt	mi
 800308a:	222b      	movmi	r2, #43	; 0x2b
 800308c:	f88d 2053 	strbmi.w	r2, [sp, #83]	; 0x53
 8003090:	782a      	ldrb	r2, [r5, #0]
 8003092:	2a2a      	cmp	r2, #42	; 0x2a
 8003094:	d02c      	beq.n	80030f0 <_vfiprintf_r+0x110>
 8003096:	2100      	movs	r1, #0
 8003098:	200a      	movs	r0, #10
 800309a:	9a07      	ldr	r2, [sp, #28]
 800309c:	46a8      	mov	r8, r5
 800309e:	f898 3000 	ldrb.w	r3, [r8]
 80030a2:	3501      	adds	r5, #1
 80030a4:	3b30      	subs	r3, #48	; 0x30
 80030a6:	2b09      	cmp	r3, #9
 80030a8:	d96d      	bls.n	8003186 <_vfiprintf_r+0x1a6>
 80030aa:	b371      	cbz	r1, 800310a <_vfiprintf_r+0x12a>
 80030ac:	e026      	b.n	80030fc <_vfiprintf_r+0x11c>
 80030ae:	4b51      	ldr	r3, [pc, #324]	; (80031f4 <_vfiprintf_r+0x214>)
 80030b0:	429c      	cmp	r4, r3
 80030b2:	d101      	bne.n	80030b8 <_vfiprintf_r+0xd8>
 80030b4:	68b4      	ldr	r4, [r6, #8]
 80030b6:	e7a3      	b.n	8003000 <_vfiprintf_r+0x20>
 80030b8:	4b4f      	ldr	r3, [pc, #316]	; (80031f8 <_vfiprintf_r+0x218>)
 80030ba:	429c      	cmp	r4, r3
 80030bc:	bf08      	it	eq
 80030be:	68f4      	ldreq	r4, [r6, #12]
 80030c0:	e79e      	b.n	8003000 <_vfiprintf_r+0x20>
 80030c2:	4621      	mov	r1, r4
 80030c4:	4630      	mov	r0, r6
 80030c6:	f7ff fc63 	bl	8002990 <__swsetup_r>
 80030ca:	2800      	cmp	r0, #0
 80030cc:	d09e      	beq.n	800300c <_vfiprintf_r+0x2c>
 80030ce:	f04f 30ff 	mov.w	r0, #4294967295
 80030d2:	b01d      	add	sp, #116	; 0x74
 80030d4:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
 80030d8:	2b25      	cmp	r3, #37	; 0x25
 80030da:	d0a7      	beq.n	800302c <_vfiprintf_r+0x4c>
 80030dc:	46a8      	mov	r8, r5
 80030de:	e7a0      	b.n	8003022 <_vfiprintf_r+0x42>
 80030e0:	4a43      	ldr	r2, [pc, #268]	; (80031f0 <_vfiprintf_r+0x210>)
 80030e2:	4645      	mov	r5, r8
 80030e4:	1a80      	subs	r0, r0, r2
 80030e6:	fa0b f000 	lsl.w	r0, fp, r0
 80030ea:	4318      	orrs	r0, r3
 80030ec:	9004      	str	r0, [sp, #16]
 80030ee:	e7bb      	b.n	8003068 <_vfiprintf_r+0x88>
 80030f0:	9a03      	ldr	r2, [sp, #12]
 80030f2:	1d11      	adds	r1, r2, #4
 80030f4:	6812      	ldr	r2, [r2, #0]
 80030f6:	9103      	str	r1, [sp, #12]
 80030f8:	2a00      	cmp	r2, #0
 80030fa:	db01      	blt.n	8003100 <_vfiprintf_r+0x120>
 80030fc:	9207      	str	r2, [sp, #28]
 80030fe:	e004      	b.n	800310a <_vfiprintf_r+0x12a>
 8003100:	4252      	negs	r2, r2
 8003102:	f043 0302 	orr.w	r3, r3, #2
 8003106:	9207      	str	r2, [sp, #28]
 8003108:	9304      	str	r3, [sp, #16]
 800310a:	f898 3000 	ldrb.w	r3, [r8]
 800310e:	2b2e      	cmp	r3, #46	; 0x2e
 8003110:	d110      	bne.n	8003134 <_vfiprintf_r+0x154>
 8003112:	f898 3001 	ldrb.w	r3, [r8, #1]
 8003116:	f108 0101 	add.w	r1, r8, #1
 800311a:	2b2a      	cmp	r3, #42	; 0x2a
 800311c:	d137      	bne.n	800318e <_vfiprintf_r+0x1ae>
 800311e:	9b03      	ldr	r3, [sp, #12]
 8003120:	f108 0802 	add.w	r8, r8, #2
 8003124:	1d1a      	adds	r2, r3, #4
 8003126:	681b      	ldr	r3, [r3, #0]
 8003128:	9203      	str	r2, [sp, #12]
 800312a:	2b00      	cmp	r3, #0
 800312c:	bfb8      	it	lt
 800312e:	f04f 33ff 	movlt.w	r3, #4294967295
 8003132:	9305      	str	r3, [sp, #20]
 8003134:	4d31      	ldr	r5, [pc, #196]	; (80031fc <_vfiprintf_r+0x21c>)
 8003136:	2203      	movs	r2, #3
 8003138:	f898 1000 	ldrb.w	r1, [r8]
 800313c:	4628      	mov	r0, r5
 800313e:	f000 faa7 	bl	8003690 <memchr>
 8003142:	b140      	cbz	r0, 8003156 <_vfiprintf_r+0x176>
 8003144:	2340      	movs	r3, #64	; 0x40
 8003146:	1b40      	subs	r0, r0, r5
 8003148:	fa03 f000 	lsl.w	r0, r3, r0
 800314c:	9b04      	ldr	r3, [sp, #16]
 800314e:	f108 0801 	add.w	r8, r8, #1
 8003152:	4303      	orrs	r3, r0
 8003154:	9304      	str	r3, [sp, #16]
 8003156:	f898 1000 	ldrb.w	r1, [r8]
 800315a:	2206      	movs	r2, #6
 800315c:	4828      	ldr	r0, [pc, #160]	; (8003200 <_vfiprintf_r+0x220>)
 800315e:	f108 0701 	add.w	r7, r8, #1
 8003162:	f88d 1028 	strb.w	r1, [sp, #40]	; 0x28
 8003166:	f000 fa93 	bl	8003690 <memchr>
 800316a:	2800      	cmp	r0, #0
 800316c:	d034      	beq.n	80031d8 <_vfiprintf_r+0x1f8>
 800316e:	4b25      	ldr	r3, [pc, #148]	; (8003204 <_vfiprintf_r+0x224>)
 8003170:	bb03      	cbnz	r3, 80031b4 <_vfiprintf_r+0x1d4>
 8003172:	9b03      	ldr	r3, [sp, #12]
 8003174:	3307      	adds	r3, #7
 8003176:	f023 0307 	bic.w	r3, r3, #7
 800317a:	3308      	adds	r3, #8
 800317c:	9303      	str	r3, [sp, #12]
 800317e:	9b09      	ldr	r3, [sp, #36]	; 0x24
 8003180:	444b      	add	r3, r9
 8003182:	9309      	str	r3, [sp, #36]	; 0x24
 8003184:	e74c      	b.n	8003020 <_vfiprintf_r+0x40>
 8003186:	fb00 3202 	mla	r2, r0, r2, r3
 800318a:	2101      	movs	r1, #1
 800318c:	e786      	b.n	800309c <_vfiprintf_r+0xbc>
 800318e:	2300      	movs	r3, #0
 8003190:	250a      	movs	r5, #10
 8003192:	4618      	mov	r0, r3
 8003194:	9305      	str	r3, [sp, #20]
 8003196:	4688      	mov	r8, r1
 8003198:	f898 2000 	ldrb.w	r2, [r8]
 800319c:	3101      	adds	r1, #1
 800319e:	3a30      	subs	r2, #48	; 0x30
 80031a0:	2a09      	cmp	r2, #9
 80031a2:	d903      	bls.n	80031ac <_vfiprintf_r+0x1cc>
 80031a4:	2b00      	cmp	r3, #0
 80031a6:	d0c5      	beq.n	8003134 <_vfiprintf_r+0x154>
 80031a8:	9005      	str	r0, [sp, #20]
 80031aa:	e7c3      	b.n	8003134 <_vfiprintf_r+0x154>
 80031ac:	fb05 2000 	mla	r0, r5, r0, r2
 80031b0:	2301      	movs	r3, #1
 80031b2:	e7f0      	b.n	8003196 <_vfiprintf_r+0x1b6>
 80031b4:	ab03      	add	r3, sp, #12
 80031b6:	9300      	str	r3, [sp, #0]
 80031b8:	4622      	mov	r2, r4
 80031ba:	4b13      	ldr	r3, [pc, #76]	; (8003208 <_vfiprintf_r+0x228>)
 80031bc:	a904      	add	r1, sp, #16
 80031be:	4630      	mov	r0, r6
 80031c0:	f3af 8000 	nop.w
 80031c4:	f1b0 3fff 	cmp.w	r0, #4294967295
 80031c8:	4681      	mov	r9, r0
 80031ca:	d1d8      	bne.n	800317e <_vfiprintf_r+0x19e>
 80031cc:	89a3      	ldrh	r3, [r4, #12]
 80031ce:	065b      	lsls	r3, r3, #25
 80031d0:	f53f af7d 	bmi.w	80030ce <_vfiprintf_r+0xee>
 80031d4:	9809      	ldr	r0, [sp, #36]	; 0x24
 80031d6:	e77c      	b.n	80030d2 <_vfiprintf_r+0xf2>
 80031d8:	ab03      	add	r3, sp, #12
 80031da:	9300      	str	r3, [sp, #0]
 80031dc:	4622      	mov	r2, r4
 80031de:	4b0a      	ldr	r3, [pc, #40]	; (8003208 <_vfiprintf_r+0x228>)
 80031e0:	a904      	add	r1, sp, #16
 80031e2:	4630      	mov	r0, r6
 80031e4:	f000 f88a 	bl	80032fc <_printf_i>
 80031e8:	e7ec      	b.n	80031c4 <_vfiprintf_r+0x1e4>
 80031ea:	bf00      	nop
 80031ec:	080037ac 	.word	0x080037ac
 80031f0:	080037ec 	.word	0x080037ec
 80031f4:	080037cc 	.word	0x080037cc
 80031f8:	0800378c 	.word	0x0800378c
 80031fc:	080037f2 	.word	0x080037f2
 8003200:	080037f6 	.word	0x080037f6
 8003204:	00000000 	.word	0x00000000
 8003208:	08002fbd 	.word	0x08002fbd

0800320c <_printf_common>:
 800320c:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
 8003210:	4691      	mov	r9, r2
 8003212:	461f      	mov	r7, r3
 8003214:	688a      	ldr	r2, [r1, #8]
 8003216:	690b      	ldr	r3, [r1, #16]
 8003218:	4606      	mov	r6, r0
 800321a:	4293      	cmp	r3, r2
 800321c:	bfb8      	it	lt
 800321e:	4613      	movlt	r3, r2
 8003220:	f8c9 3000 	str.w	r3, [r9]
 8003224:	f891 2043 	ldrb.w	r2, [r1, #67]	; 0x43
 8003228:	460c      	mov	r4, r1
 800322a:	f8dd 8020 	ldr.w	r8, [sp, #32]
 800322e:	b112      	cbz	r2, 8003236 <_printf_common+0x2a>
 8003230:	3301      	adds	r3, #1
 8003232:	f8c9 3000 	str.w	r3, [r9]
 8003236:	6823      	ldr	r3, [r4, #0]
 8003238:	0699      	lsls	r1, r3, #26
 800323a:	bf42      	ittt	mi
 800323c:	f8d9 3000 	ldrmi.w	r3, [r9]
 8003240:	3302      	addmi	r3, #2
 8003242:	f8c9 3000 	strmi.w	r3, [r9]
 8003246:	6825      	ldr	r5, [r4, #0]
 8003248:	f015 0506 	ands.w	r5, r5, #6
 800324c:	d107      	bne.n	800325e <_printf_common+0x52>
 800324e:	f104 0a19 	add.w	sl, r4, #25
 8003252:	68e3      	ldr	r3, [r4, #12]
 8003254:	f8d9 2000 	ldr.w	r2, [r9]
 8003258:	1a9b      	subs	r3, r3, r2
 800325a:	429d      	cmp	r5, r3
 800325c:	db2a      	blt.n	80032b4 <_printf_common+0xa8>
 800325e:	f894 3043 	ldrb.w	r3, [r4, #67]	; 0x43
 8003262:	6822      	ldr	r2, [r4, #0]
 8003264:	3300      	adds	r3, #0
 8003266:	bf18      	it	ne
 8003268:	2301      	movne	r3, #1
 800326a:	0692      	lsls	r2, r2, #26
 800326c:	d42f      	bmi.n	80032ce <_printf_common+0xc2>
 800326e:	f104 0243 	add.w	r2, r4, #67	; 0x43
 8003272:	4639      	mov	r1, r7
 8003274:	4630      	mov	r0, r6
 8003276:	47c0      	blx	r8
 8003278:	3001      	adds	r0, #1
 800327a:	d022      	beq.n	80032c2 <_printf_common+0xb6>
 800327c:	6823      	ldr	r3, [r4, #0]
 800327e:	68e5      	ldr	r5, [r4, #12]
 8003280:	f003 0306 	and.w	r3, r3, #6
 8003284:	2b04      	cmp	r3, #4
 8003286:	bf18      	it	ne
 8003288:	2500      	movne	r5, #0
 800328a:	f8d9 2000 	ldr.w	r2, [r9]
 800328e:	f04f 0900 	mov.w	r9, #0
 8003292:	bf08      	it	eq
 8003294:	1aad      	subeq	r5, r5, r2
 8003296:	68a3      	ldr	r3, [r4, #8]
 8003298:	6922      	ldr	r2, [r4, #16]
 800329a:	bf08      	it	eq
 800329c:	ea25 75e5 	biceq.w	r5, r5, r5, asr #31
 80032a0:	4293      	cmp	r3, r2
 80032a2:	bfc4      	itt	gt
 80032a4:	1a9b      	subgt	r3, r3, r2
 80032a6:	18ed      	addgt	r5, r5, r3
 80032a8:	341a      	adds	r4, #26
 80032aa:	454d      	cmp	r5, r9
 80032ac:	d11b      	bne.n	80032e6 <_printf_common+0xda>
 80032ae:	2000      	movs	r0, #0
 80032b0:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 80032b4:	2301      	movs	r3, #1
 80032b6:	4652      	mov	r2, sl
 80032b8:	4639      	mov	r1, r7
 80032ba:	4630      	mov	r0, r6
 80032bc:	47c0      	blx	r8
 80032be:	3001      	adds	r0, #1
 80032c0:	d103      	bne.n	80032ca <_printf_common+0xbe>
 80032c2:	f04f 30ff 	mov.w	r0, #4294967295
 80032c6:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 80032ca:	3501      	adds	r5, #1
 80032cc:	e7c1      	b.n	8003252 <_printf_common+0x46>
 80032ce:	2030      	movs	r0, #48	; 0x30
 80032d0:	18e1      	adds	r1, r4, r3
 80032d2:	f881 0043 	strb.w	r0, [r1, #67]	; 0x43
 80032d6:	1c5a      	adds	r2, r3, #1
 80032d8:	f894 1045 	ldrb.w	r1, [r4, #69]	; 0x45
 80032dc:	4422      	add	r2, r4
 80032de:	3302      	adds	r3, #2
 80032e0:	f882 1043 	strb.w	r1, [r2, #67]	; 0x43
 80032e4:	e7c3      	b.n	800326e <_printf_common+0x62>
 80032e6:	2301      	movs	r3, #1
 80032e8:	4622      	mov	r2, r4
 80032ea:	4639      	mov	r1, r7
 80032ec:	4630      	mov	r0, r6
 80032ee:	47c0      	blx	r8
 80032f0:	3001      	adds	r0, #1
 80032f2:	d0e6      	beq.n	80032c2 <_printf_common+0xb6>
 80032f4:	f109 0901 	add.w	r9, r9, #1
 80032f8:	e7d7      	b.n	80032aa <_printf_common+0x9e>
	...

080032fc <_printf_i>:
 80032fc:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr}
 8003300:	4617      	mov	r7, r2
 8003302:	7e0a      	ldrb	r2, [r1, #24]
 8003304:	b085      	sub	sp, #20
 8003306:	2a6e      	cmp	r2, #110	; 0x6e
 8003308:	4698      	mov	r8, r3
 800330a:	4606      	mov	r6, r0
 800330c:	460c      	mov	r4, r1
 800330e:	9b0c      	ldr	r3, [sp, #48]	; 0x30
 8003310:	f101 0e43 	add.w	lr, r1, #67	; 0x43
 8003314:	f000 80bc 	beq.w	8003490 <_printf_i+0x194>
 8003318:	d81a      	bhi.n	8003350 <_printf_i+0x54>
 800331a:	2a63      	cmp	r2, #99	; 0x63
 800331c:	d02e      	beq.n	800337c <_printf_i+0x80>
 800331e:	d80a      	bhi.n	8003336 <_printf_i+0x3a>
 8003320:	2a00      	cmp	r2, #0
 8003322:	f000 80c8 	beq.w	80034b6 <_printf_i+0x1ba>
 8003326:	2a58      	cmp	r2, #88	; 0x58
 8003328:	f000 808a 	beq.w	8003440 <_printf_i+0x144>
 800332c:	f104 0542 	add.w	r5, r4, #66	; 0x42
 8003330:	f884 2042 	strb.w	r2, [r4, #66]	; 0x42
 8003334:	e02a      	b.n	800338c <_printf_i+0x90>
 8003336:	2a64      	cmp	r2, #100	; 0x64
 8003338:	d001      	beq.n	800333e <_printf_i+0x42>
 800333a:	2a69      	cmp	r2, #105	; 0x69
 800333c:	d1f6      	bne.n	800332c <_printf_i+0x30>
 800333e:	6821      	ldr	r1, [r4, #0]
 8003340:	681a      	ldr	r2, [r3, #0]
 8003342:	f011 0f80 	tst.w	r1, #128	; 0x80
 8003346:	d023      	beq.n	8003390 <_printf_i+0x94>
 8003348:	1d11      	adds	r1, r2, #4
 800334a:	6019      	str	r1, [r3, #0]
 800334c:	6813      	ldr	r3, [r2, #0]
 800334e:	e027      	b.n	80033a0 <_printf_i+0xa4>
 8003350:	2a73      	cmp	r2, #115	; 0x73
 8003352:	f000 80b4 	beq.w	80034be <_printf_i+0x1c2>
 8003356:	d808      	bhi.n	800336a <_printf_i+0x6e>
 8003358:	2a6f      	cmp	r2, #111	; 0x6f
 800335a:	d02a      	beq.n	80033b2 <_printf_i+0xb6>
 800335c:	2a70      	cmp	r2, #112	; 0x70
 800335e:	d1e5      	bne.n	800332c <_printf_i+0x30>
 8003360:	680a      	ldr	r2, [r1, #0]
 8003362:	f042 0220 	orr.w	r2, r2, #32
 8003366:	600a      	str	r2, [r1, #0]
 8003368:	e003      	b.n	8003372 <_printf_i+0x76>
 800336a:	2a75      	cmp	r2, #117	; 0x75
 800336c:	d021      	beq.n	80033b2 <_printf_i+0xb6>
 800336e:	2a78      	cmp	r2, #120	; 0x78
 8003370:	d1dc      	bne.n	800332c <_printf_i+0x30>
 8003372:	2278      	movs	r2, #120	; 0x78
 8003374:	496f      	ldr	r1, [pc, #444]	; (8003534 <_printf_i+0x238>)
 8003376:	f884 2045 	strb.w	r2, [r4, #69]	; 0x45
 800337a:	e064      	b.n	8003446 <_printf_i+0x14a>
 800337c:	681a      	ldr	r2, [r3, #0]
 800337e:	f101 0542 	add.w	r5, r1, #66	; 0x42
 8003382:	1d11      	adds	r1, r2, #4
 8003384:	6019      	str	r1, [r3, #0]
 8003386:	6813      	ldr	r3, [r2, #0]
 8003388:	f884 3042 	strb.w	r3, [r4, #66]	; 0x42
 800338c:	2301      	movs	r3, #1
 800338e:	e0a3      	b.n	80034d8 <_printf_i+0x1dc>
 8003390:	f011 0f40 	tst.w	r1, #64	; 0x40
 8003394:	f102 0104 	add.w	r1, r2, #4
 8003398:	6019      	str	r1, [r3, #0]
 800339a:	d0d7      	beq.n	800334c <_printf_i+0x50>
 800339c:	f9b2 3000 	ldrsh.w	r3, [r2]
 80033a0:	2b00      	cmp	r3, #0
 80033a2:	da03      	bge.n	80033ac <_printf_i+0xb0>
 80033a4:	222d      	movs	r2, #45	; 0x2d
 80033a6:	425b      	negs	r3, r3
 80033a8:	f884 2043 	strb.w	r2, [r4, #67]	; 0x43
 80033ac:	4962      	ldr	r1, [pc, #392]	; (8003538 <_printf_i+0x23c>)
 80033ae:	220a      	movs	r2, #10
 80033b0:	e017      	b.n	80033e2 <_printf_i+0xe6>
 80033b2:	6820      	ldr	r0, [r4, #0]
 80033b4:	6819      	ldr	r1, [r3, #0]
 80033b6:	f010 0f80 	tst.w	r0, #128	; 0x80
 80033ba:	d003      	beq.n	80033c4 <_printf_i+0xc8>
 80033bc:	1d08      	adds	r0, r1, #4
 80033be:	6018      	str	r0, [r3, #0]
 80033c0:	680b      	ldr	r3, [r1, #0]
 80033c2:	e006      	b.n	80033d2 <_printf_i+0xd6>
 80033c4:	f010 0f40 	tst.w	r0, #64	; 0x40
 80033c8:	f101 0004 	add.w	r0, r1, #4
 80033cc:	6018      	str	r0, [r3, #0]
 80033ce:	d0f7      	beq.n	80033c0 <_printf_i+0xc4>
 80033d0:	880b      	ldrh	r3, [r1, #0]
 80033d2:	2a6f      	cmp	r2, #111	; 0x6f
 80033d4:	bf14      	ite	ne
 80033d6:	220a      	movne	r2, #10
 80033d8:	2208      	moveq	r2, #8
 80033da:	4957      	ldr	r1, [pc, #348]	; (8003538 <_printf_i+0x23c>)
 80033dc:	2000      	movs	r0, #0
 80033de:	f884 0043 	strb.w	r0, [r4, #67]	; 0x43
 80033e2:	6865      	ldr	r5, [r4, #4]
 80033e4:	2d00      	cmp	r5, #0
 80033e6:	60a5      	str	r5, [r4, #8]
 80033e8:	f2c0 809c 	blt.w	8003524 <_printf_i+0x228>
 80033ec:	6820      	ldr	r0, [r4, #0]
 80033ee:	f020 0004 	bic.w	r0, r0, #4
 80033f2:	6020      	str	r0, [r4, #0]
 80033f4:	2b00      	cmp	r3, #0
 80033f6:	d13f      	bne.n	8003478 <_printf_i+0x17c>
 80033f8:	2d00      	cmp	r5, #0
 80033fa:	f040 8095 	bne.w	8003528 <_printf_i+0x22c>
 80033fe:	4675      	mov	r5, lr
 8003400:	2a08      	cmp	r2, #8
 8003402:	d10b      	bne.n	800341c <_printf_i+0x120>
 8003404:	6823      	ldr	r3, [r4, #0]
 8003406:	07da      	lsls	r2, r3, #31
 8003408:	d508      	bpl.n	800341c <_printf_i+0x120>
 800340a:	6923      	ldr	r3, [r4, #16]
 800340c:	6862      	ldr	r2, [r4, #4]
 800340e:	429a      	cmp	r2, r3
 8003410:	bfde      	ittt	le
 8003412:	2330      	movle	r3, #48	; 0x30
 8003414:	f805 3c01 	strble.w	r3, [r5, #-1]
 8003418:	f105 35ff 	addle.w	r5, r5, #4294967295
 800341c:	ebae 0305 	sub.w	r3, lr, r5
 8003420:	6123      	str	r3, [r4, #16]
 8003422:	f8cd 8000 	str.w	r8, [sp]
 8003426:	463b      	mov	r3, r7
 8003428:	aa03      	add	r2, sp, #12
 800342a:	4621      	mov	r1, r4
 800342c:	4630      	mov	r0, r6
 800342e:	f7ff feed 	bl	800320c <_printf_common>
 8003432:	3001      	adds	r0, #1
 8003434:	d155      	bne.n	80034e2 <_printf_i+0x1e6>
 8003436:	f04f 30ff 	mov.w	r0, #4294967295
 800343a:	b005      	add	sp, #20
 800343c:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
 8003440:	f881 2045 	strb.w	r2, [r1, #69]	; 0x45
 8003444:	493c      	ldr	r1, [pc, #240]	; (8003538 <_printf_i+0x23c>)
 8003446:	6822      	ldr	r2, [r4, #0]
 8003448:	6818      	ldr	r0, [r3, #0]
 800344a:	f012 0f80 	tst.w	r2, #128	; 0x80
 800344e:	f100 0504 	add.w	r5, r0, #4
 8003452:	601d      	str	r5, [r3, #0]
 8003454:	d001      	beq.n	800345a <_printf_i+0x15e>
 8003456:	6803      	ldr	r3, [r0, #0]
 8003458:	e002      	b.n	8003460 <_printf_i+0x164>
 800345a:	0655      	lsls	r5, r2, #25
 800345c:	d5fb      	bpl.n	8003456 <_printf_i+0x15a>
 800345e:	8803      	ldrh	r3, [r0, #0]
 8003460:	07d0      	lsls	r0, r2, #31
 8003462:	bf44      	itt	mi
 8003464:	f042 0220 	orrmi.w	r2, r2, #32
 8003468:	6022      	strmi	r2, [r4, #0]
 800346a:	b91b      	cbnz	r3, 8003474 <_printf_i+0x178>
 800346c:	6822      	ldr	r2, [r4, #0]
 800346e:	f022 0220 	bic.w	r2, r2, #32
 8003472:	6022      	str	r2, [r4, #0]
 8003474:	2210      	movs	r2, #16
 8003476:	e7b1      	b.n	80033dc <_printf_i+0xe0>
 8003478:	4675      	mov	r5, lr
 800347a:	fbb3 f0f2 	udiv	r0, r3, r2
 800347e:	fb02 3310 	mls	r3, r2, r0, r3
 8003482:	5ccb      	ldrb	r3, [r1, r3]
 8003484:	f805 3d01 	strb.w	r3, [r5, #-1]!
 8003488:	4603      	mov	r3, r0
 800348a:	2800      	cmp	r0, #0
 800348c:	d1f5      	bne.n	800347a <_printf_i+0x17e>
 800348e:	e7b7      	b.n	8003400 <_printf_i+0x104>
 8003490:	6808      	ldr	r0, [r1, #0]
 8003492:	681a      	ldr	r2, [r3, #0]
 8003494:	f010 0f80 	tst.w	r0, #128	; 0x80
 8003498:	6949      	ldr	r1, [r1, #20]
 800349a:	d004      	beq.n	80034a6 <_printf_i+0x1aa>
 800349c:	1d10      	adds	r0, r2, #4
 800349e:	6018      	str	r0, [r3, #0]
 80034a0:	6813      	ldr	r3, [r2, #0]
 80034a2:	6019      	str	r1, [r3, #0]
 80034a4:	e007      	b.n	80034b6 <_printf_i+0x1ba>
 80034a6:	f010 0f40 	tst.w	r0, #64	; 0x40
 80034aa:	f102 0004 	add.w	r0, r2, #4
 80034ae:	6018      	str	r0, [r3, #0]
 80034b0:	6813      	ldr	r3, [r2, #0]
 80034b2:	d0f6      	beq.n	80034a2 <_printf_i+0x1a6>
 80034b4:	8019      	strh	r1, [r3, #0]
 80034b6:	2300      	movs	r3, #0
 80034b8:	4675      	mov	r5, lr
 80034ba:	6123      	str	r3, [r4, #16]
 80034bc:	e7b1      	b.n	8003422 <_printf_i+0x126>
 80034be:	681a      	ldr	r2, [r3, #0]
 80034c0:	1d11      	adds	r1, r2, #4
 80034c2:	6019      	str	r1, [r3, #0]
 80034c4:	6815      	ldr	r5, [r2, #0]
 80034c6:	2100      	movs	r1, #0
 80034c8:	6862      	ldr	r2, [r4, #4]
 80034ca:	4628      	mov	r0, r5
 80034cc:	f000 f8e0 	bl	8003690 <memchr>
 80034d0:	b108      	cbz	r0, 80034d6 <_printf_i+0x1da>
 80034d2:	1b40      	subs	r0, r0, r5
 80034d4:	6060      	str	r0, [r4, #4]
 80034d6:	6863      	ldr	r3, [r4, #4]
 80034d8:	6123      	str	r3, [r4, #16]
 80034da:	2300      	movs	r3, #0
 80034dc:	f884 3043 	strb.w	r3, [r4, #67]	; 0x43
 80034e0:	e79f      	b.n	8003422 <_printf_i+0x126>
 80034e2:	6923      	ldr	r3, [r4, #16]
 80034e4:	462a      	mov	r2, r5
 80034e6:	4639      	mov	r1, r7
 80034e8:	4630      	mov	r0, r6
 80034ea:	47c0      	blx	r8
 80034ec:	3001      	adds	r0, #1
 80034ee:	d0a2      	beq.n	8003436 <_printf_i+0x13a>
 80034f0:	6823      	ldr	r3, [r4, #0]
 80034f2:	079b      	lsls	r3, r3, #30
 80034f4:	d507      	bpl.n	8003506 <_printf_i+0x20a>
 80034f6:	2500      	movs	r5, #0
 80034f8:	f104 0919 	add.w	r9, r4, #25
 80034fc:	68e3      	ldr	r3, [r4, #12]
 80034fe:	9a03      	ldr	r2, [sp, #12]
 8003500:	1a9b      	subs	r3, r3, r2
 8003502:	429d      	cmp	r5, r3
 8003504:	db05      	blt.n	8003512 <_printf_i+0x216>
 8003506:	68e0      	ldr	r0, [r4, #12]
 8003508:	9b03      	ldr	r3, [sp, #12]
 800350a:	4298      	cmp	r0, r3
 800350c:	bfb8      	it	lt
 800350e:	4618      	movlt	r0, r3
 8003510:	e793      	b.n	800343a <_printf_i+0x13e>
 8003512:	2301      	movs	r3, #1
 8003514:	464a      	mov	r2, r9
 8003516:	4639      	mov	r1, r7
 8003518:	4630      	mov	r0, r6
 800351a:	47c0      	blx	r8
 800351c:	3001      	adds	r0, #1
 800351e:	d08a      	beq.n	8003436 <_printf_i+0x13a>
 8003520:	3501      	adds	r5, #1
 8003522:	e7eb      	b.n	80034fc <_printf_i+0x200>
 8003524:	2b00      	cmp	r3, #0
 8003526:	d1a7      	bne.n	8003478 <_printf_i+0x17c>
 8003528:	780b      	ldrb	r3, [r1, #0]
 800352a:	f104 0542 	add.w	r5, r4, #66	; 0x42
 800352e:	f884 3042 	strb.w	r3, [r4, #66]	; 0x42
 8003532:	e765      	b.n	8003400 <_printf_i+0x104>
 8003534:	0800380e 	.word	0x0800380e
 8003538:	080037fd 	.word	0x080037fd

0800353c <_sbrk_r>:
 800353c:	b538      	push	{r3, r4, r5, lr}
 800353e:	2300      	movs	r3, #0
 8003540:	4c05      	ldr	r4, [pc, #20]	; (8003558 <_sbrk_r+0x1c>)
 8003542:	4605      	mov	r5, r0
 8003544:	4608      	mov	r0, r1
 8003546:	6023      	str	r3, [r4, #0]
 8003548:	f7fe ff5a 	bl	8002400 <_sbrk>
 800354c:	1c43      	adds	r3, r0, #1
 800354e:	d102      	bne.n	8003556 <_sbrk_r+0x1a>
 8003550:	6823      	ldr	r3, [r4, #0]
 8003552:	b103      	cbz	r3, 8003556 <_sbrk_r+0x1a>
 8003554:	602b      	str	r3, [r5, #0]
 8003556:	bd38      	pop	{r3, r4, r5, pc}
 8003558:	20001170 	.word	0x20001170

0800355c <__sread>:
 800355c:	b510      	push	{r4, lr}
 800355e:	460c      	mov	r4, r1
 8003560:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 8003564:	f000 f8a4 	bl	80036b0 <_read_r>
 8003568:	2800      	cmp	r0, #0
 800356a:	bfab      	itete	ge
 800356c:	6d63      	ldrge	r3, [r4, #84]	; 0x54
 800356e:	89a3      	ldrhlt	r3, [r4, #12]
 8003570:	181b      	addge	r3, r3, r0
 8003572:	f423 5380 	biclt.w	r3, r3, #4096	; 0x1000
 8003576:	bfac      	ite	ge
 8003578:	6563      	strge	r3, [r4, #84]	; 0x54
 800357a:	81a3      	strhlt	r3, [r4, #12]
 800357c:	bd10      	pop	{r4, pc}

0800357e <__swrite>:
 800357e:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
 8003582:	461f      	mov	r7, r3
 8003584:	898b      	ldrh	r3, [r1, #12]
 8003586:	4605      	mov	r5, r0
 8003588:	05db      	lsls	r3, r3, #23
 800358a:	460c      	mov	r4, r1
 800358c:	4616      	mov	r6, r2
 800358e:	d505      	bpl.n	800359c <__swrite+0x1e>
 8003590:	2302      	movs	r3, #2
 8003592:	2200      	movs	r2, #0
 8003594:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 8003598:	f000 f868 	bl	800366c <_lseek_r>
 800359c:	89a3      	ldrh	r3, [r4, #12]
 800359e:	4632      	mov	r2, r6
 80035a0:	f423 5380 	bic.w	r3, r3, #4096	; 0x1000
 80035a4:	81a3      	strh	r3, [r4, #12]
 80035a6:	f9b4 100e 	ldrsh.w	r1, [r4, #14]
 80035aa:	463b      	mov	r3, r7
 80035ac:	4628      	mov	r0, r5
 80035ae:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
 80035b2:	f000 b817 	b.w	80035e4 <_write_r>

080035b6 <__sseek>:
 80035b6:	b510      	push	{r4, lr}
 80035b8:	460c      	mov	r4, r1
 80035ba:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 80035be:	f000 f855 	bl	800366c <_lseek_r>
 80035c2:	1c43      	adds	r3, r0, #1
 80035c4:	89a3      	ldrh	r3, [r4, #12]
 80035c6:	bf15      	itete	ne
 80035c8:	6560      	strne	r0, [r4, #84]	; 0x54
 80035ca:	f423 5380 	biceq.w	r3, r3, #4096	; 0x1000
 80035ce:	f443 5380 	orrne.w	r3, r3, #4096	; 0x1000
 80035d2:	81a3      	strheq	r3, [r4, #12]
 80035d4:	bf18      	it	ne
 80035d6:	81a3      	strhne	r3, [r4, #12]
 80035d8:	bd10      	pop	{r4, pc}

080035da <__sclose>:
 80035da:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 80035de:	f000 b813 	b.w	8003608 <_close_r>
	...

080035e4 <_write_r>:
 80035e4:	b538      	push	{r3, r4, r5, lr}
 80035e6:	4605      	mov	r5, r0
 80035e8:	4608      	mov	r0, r1
 80035ea:	4611      	mov	r1, r2
 80035ec:	2200      	movs	r2, #0
 80035ee:	4c05      	ldr	r4, [pc, #20]	; (8003604 <_write_r+0x20>)
 80035f0:	6022      	str	r2, [r4, #0]
 80035f2:	461a      	mov	r2, r3
 80035f4:	f7fe fcf0 	bl	8001fd8 <_write>
 80035f8:	1c43      	adds	r3, r0, #1
 80035fa:	d102      	bne.n	8003602 <_write_r+0x1e>
 80035fc:	6823      	ldr	r3, [r4, #0]
 80035fe:	b103      	cbz	r3, 8003602 <_write_r+0x1e>
 8003600:	602b      	str	r3, [r5, #0]
 8003602:	bd38      	pop	{r3, r4, r5, pc}
 8003604:	20001170 	.word	0x20001170

08003608 <_close_r>:
 8003608:	b538      	push	{r3, r4, r5, lr}
 800360a:	2300      	movs	r3, #0
 800360c:	4c05      	ldr	r4, [pc, #20]	; (8003624 <_close_r+0x1c>)
 800360e:	4605      	mov	r5, r0
 8003610:	4608      	mov	r0, r1
 8003612:	6023      	str	r3, [r4, #0]
 8003614:	f7fe ff0e 	bl	8002434 <_close>
 8003618:	1c43      	adds	r3, r0, #1
 800361a:	d102      	bne.n	8003622 <_close_r+0x1a>
 800361c:	6823      	ldr	r3, [r4, #0]
 800361e:	b103      	cbz	r3, 8003622 <_close_r+0x1a>
 8003620:	602b      	str	r3, [r5, #0]
 8003622:	bd38      	pop	{r3, r4, r5, pc}
 8003624:	20001170 	.word	0x20001170

08003628 <_fstat_r>:
 8003628:	b538      	push	{r3, r4, r5, lr}
 800362a:	2300      	movs	r3, #0
 800362c:	4c06      	ldr	r4, [pc, #24]	; (8003648 <_fstat_r+0x20>)
 800362e:	4605      	mov	r5, r0
 8003630:	4608      	mov	r0, r1
 8003632:	4611      	mov	r1, r2
 8003634:	6023      	str	r3, [r4, #0]
 8003636:	f7fe ff00 	bl	800243a <_fstat>
 800363a:	1c43      	adds	r3, r0, #1
 800363c:	d102      	bne.n	8003644 <_fstat_r+0x1c>
 800363e:	6823      	ldr	r3, [r4, #0]
 8003640:	b103      	cbz	r3, 8003644 <_fstat_r+0x1c>
 8003642:	602b      	str	r3, [r5, #0]
 8003644:	bd38      	pop	{r3, r4, r5, pc}
 8003646:	bf00      	nop
 8003648:	20001170 	.word	0x20001170

0800364c <_isatty_r>:
 800364c:	b538      	push	{r3, r4, r5, lr}
 800364e:	2300      	movs	r3, #0
 8003650:	4c05      	ldr	r4, [pc, #20]	; (8003668 <_isatty_r+0x1c>)
 8003652:	4605      	mov	r5, r0
 8003654:	4608      	mov	r0, r1
 8003656:	6023      	str	r3, [r4, #0]
 8003658:	f7fe fef4 	bl	8002444 <_isatty>
 800365c:	1c43      	adds	r3, r0, #1
 800365e:	d102      	bne.n	8003666 <_isatty_r+0x1a>
 8003660:	6823      	ldr	r3, [r4, #0]
 8003662:	b103      	cbz	r3, 8003666 <_isatty_r+0x1a>
 8003664:	602b      	str	r3, [r5, #0]
 8003666:	bd38      	pop	{r3, r4, r5, pc}
 8003668:	20001170 	.word	0x20001170

0800366c <_lseek_r>:
 800366c:	b538      	push	{r3, r4, r5, lr}
 800366e:	4605      	mov	r5, r0
 8003670:	4608      	mov	r0, r1
 8003672:	4611      	mov	r1, r2
 8003674:	2200      	movs	r2, #0
 8003676:	4c05      	ldr	r4, [pc, #20]	; (800368c <_lseek_r+0x20>)
 8003678:	6022      	str	r2, [r4, #0]
 800367a:	461a      	mov	r2, r3
 800367c:	f7fe fee4 	bl	8002448 <_lseek>
 8003680:	1c43      	adds	r3, r0, #1
 8003682:	d102      	bne.n	800368a <_lseek_r+0x1e>
 8003684:	6823      	ldr	r3, [r4, #0]
 8003686:	b103      	cbz	r3, 800368a <_lseek_r+0x1e>
 8003688:	602b      	str	r3, [r5, #0]
 800368a:	bd38      	pop	{r3, r4, r5, pc}
 800368c:	20001170 	.word	0x20001170

08003690 <memchr>:
 8003690:	b510      	push	{r4, lr}
 8003692:	b2c9      	uxtb	r1, r1
 8003694:	4402      	add	r2, r0
 8003696:	4290      	cmp	r0, r2
 8003698:	4603      	mov	r3, r0
 800369a:	d101      	bne.n	80036a0 <memchr+0x10>
 800369c:	2000      	movs	r0, #0
 800369e:	bd10      	pop	{r4, pc}
 80036a0:	781c      	ldrb	r4, [r3, #0]
 80036a2:	3001      	adds	r0, #1
 80036a4:	428c      	cmp	r4, r1
 80036a6:	d1f6      	bne.n	8003696 <memchr+0x6>
 80036a8:	4618      	mov	r0, r3
 80036aa:	bd10      	pop	{r4, pc}

080036ac <__malloc_lock>:
 80036ac:	4770      	bx	lr

080036ae <__malloc_unlock>:
 80036ae:	4770      	bx	lr

080036b0 <_read_r>:
 80036b0:	b538      	push	{r3, r4, r5, lr}
 80036b2:	4605      	mov	r5, r0
 80036b4:	4608      	mov	r0, r1
 80036b6:	4611      	mov	r1, r2
 80036b8:	2200      	movs	r2, #0
 80036ba:	4c05      	ldr	r4, [pc, #20]	; (80036d0 <_read_r+0x20>)
 80036bc:	6022      	str	r2, [r4, #0]
 80036be:	461a      	mov	r2, r3
 80036c0:	f7fe fe90 	bl	80023e4 <_read>
 80036c4:	1c43      	adds	r3, r0, #1
 80036c6:	d102      	bne.n	80036ce <_read_r+0x1e>
 80036c8:	6823      	ldr	r3, [r4, #0]
 80036ca:	b103      	cbz	r3, 80036ce <_read_r+0x1e>
 80036cc:	602b      	str	r3, [r5, #0]
 80036ce:	bd38      	pop	{r3, r4, r5, pc}
 80036d0:	20001170 	.word	0x20001170

080036d4 <_init>:
 80036d4:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 80036d6:	bf00      	nop
 80036d8:	bcf8      	pop	{r3, r4, r5, r6, r7}
 80036da:	bc08      	pop	{r3}
 80036dc:	469e      	mov	lr, r3
 80036de:	4770      	bx	lr

080036e0 <_fini>:
 80036e0:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 80036e2:	bf00      	nop
 80036e4:	bcf8      	pop	{r3, r4, r5, r6, r7}
 80036e6:	bc08      	pop	{r3}
 80036e8:	469e      	mov	lr, r3
 80036ea:	4770      	bx	lr