STM32F103ZET_JDASMBIC/Bluecell_Inc/Bluecell_operate.h

/*
 * Bluecell_operate.h
 *
 *  Created on: 2020. 4. 3.
 *      Author: YJ
 */

#ifndef BLUECELL_OPERATE_H_
#define BLUECELL_OPERATE_H_


#include <stdbool.h>
#include "Bluecell_operate.h"
/*
SYN
Sub-UID
R-Code
TR-ID
Seq-Num
TTL
Time
���� ����
CMD
Length
Header Checksum
SUB-DATA
SUB-DATA-CRC
ETX
 */


/*
 *
0	80	��ü ���� ��ȸ	��� AID �׸� ���� ���� ��û �� ���� (��û Frame�� SUB-DATA �� ���̴� 0)
1	81	���� ��û	���� ��û�� REQ�� 0x01 �̰� ������ ��ü ������ ���¸� ����

10	90	Download Notification	�ٿ�ε� ����
11	91	Download Data	�ٿ�ε� data
12	92	Download Confirm	�ٿ�ε� Ȯ��
13	93	Download Complete	Download Complete Command
14	94	System-Reboot	System Rebooting Command

40	C0	���̺� ��ȸ �� ����
41	C1	���̺� ���� �� ����

 *
 *
 */
typedef enum{
	AllDataReq = 0,      // -> Response 80
	DataCtrlReq,		 // -> Response 81
	DownNotification,    // -> Response 90
	DownData,            // -> Response 91
	DownConfirm ,        // -> Response 92
	DownComplete,        // -> Response 93
	SystemReboot,        // -> Response 94

	TableDataReq = 40,

}MBICBootProt_st;

typedef enum{
	MBIC_PREAMBLE_0 = 0,
	MBIC_PREAMBLE_1,
	MBIC_PREAMBLE_2,
	MBIC_PREAMBLE_3,
	MBIC_SUBUID_0,
	MBIC_SUBUID_1,
	MBIC_RCODE_0,
	MBIC_TRID_0,
	MBIC_TRID_1,
	MBIC_SEQSUM_0, // 10byte
	MBIC_TTL_0,
	MBIC_TIME_0,
	MBIC_TIME_1,
	MBIC_TIME_2,
	MBIC_TIME_3,
	MBIC_TIME_4,
	MBIC_TIME_5,
	MBIC_ERRRESPONSE_0,
	MBIC_CMD_0,
	MBIC_LENGTH_0, // 20byte
	MBIC_LENGTH_1,
	MBIC_HEADERCHECKSUM_0,
	MBIC_PAYLOADSTART,
	/*
	 * PayLoadSTART
	 */
}MBICProt_st;

typedef enum{
	Alarm_Bit_List = 0xE000,
	Alarm_Mask,
	Alarm_Test_Mode,
	Alarm_Test_Dummy,
	CPU_Version,
	ModuleINFORMATION_null1,
	CPU_Current_Bank,
	CPU_Bank_Select_Reboot_by,
	CPU_Bank1_Image_Version,
	CPU_Bank1_Image_BuildTime,
	CPU_Bank1_Image_Name,
	CPU_Bank2_Image_Version,
	CPU_Bank2_Image_BuildTime,
	CPU_Bank2_Image_Name,
	SW_Reset,
	Factory_Set_Initialization,
}ModuleINFORMATION;

typedef enum{
	Temperature = 0xE010,
	Temperature_Offset,
	Temp_High_Threshold,
	Temp_High_Threshold_Default,
	Temp_High_Alarm,
	LED_TEST,
	Node,
	Type,
	PCB_Version,
	Serial_Number,
	Manufacture,
	Manufacture_Date,
	ENVIRONMENT_INVENTORY_null1,
	Freq_ID,
	Carrier_ID,
	Carrier_ON_OFF,
}ENVIRONMENT_INVENTORY;


typedef enum{
	DLI_P1_Level= 0xE020,
	DLI_P2_Level,
	DLI_P3_Level,
	DLI_P4_Level,
	ULO_P1_Level,
	ULO_P2_Level,
	ULO_P3_Level,
	ULO_P4_Level,
}Current_Volt;
typedef enum{
	DLI_RF_Path1_ON_OFF= 0xE030,
	DLI_RF_Path2_ON_OFF,
	DLI_RF_Path3_ON_OFF,
	DLI_RF_Path4_ON_OFF,
	DLI_Gain_Atten1,
	DLI_Gain_Atten2,
	DLI_Gain_Atten3,
	DLI_Gain_Atten4,
	DLI_Gain_Atten_Offset1,
	DLI_Gain_Atten_Offset2,
	DLI_Gain_Atten_Offset3,
	DLI_Gain_Atten_Offset4,
	DLI_Level_High_Threshold,
	DLI_Level_Low_Threshold,
	DLI_Level_High_Low_Threshold_default,
	DLI_Level,
}DL_Ctrl1;
typedef enum{
	DLI_Level_High_Alarm1= 0xE040,
	DLI_Level_High_Alarm2,
	DLI_Level_High_Alarm3,
	DLI_Level_High_Alarm4,
	DLI_Level_Low_Alarm1,
	DLI_Level_Low_Alarm2,
	DLI_Level_Low_Alarm3,
	DLI_Level_Low_Alarm4,
}DL_Ctrl2;
typedef enum{
	DLI_AGC_ON_OFF= 0xE050,
	DLI_AGC_Threshold,
	DLI_AGC_Threshold_Default,
	DLI_Shutdown_ON_OFF,
	DLI_Shutdown_Threshold,
	DLI_Shutdown_Threshold_Default,
	DLI_Shutdown_Count,
	DLI_AGC_Alarm1,
	DLI_AGC_Alarm2,
	DLI_AGC_Alarm3,
	DLI_AGC_Alarm4,
	DLI_Shutdown_Alarm1,
	DLI_Shutdown_Alarm2,
	DLI_Shutdown_Alarm3,
	DLI_Shutdown_Alarm4,
}DL_Ctrl3;


typedef enum{
	ULO_RF_Path1_ON_OFF= 0xE060,
	ULO_RF_Path2_ON_OFF,
	ULO_RF_Path3_ON_OFF,
	ULO_RF_Path4_ON_OFF,
	ULO_Gain_Atten1,
	ULO_Gain_Atten2,
	ULO_Gain_Atten3,
	ULO_Gain_Atten4,
	ULO_Gain_Atten_Offset1,
	ULO_Gain_Atten_Offset2,
	ULO_Gain_Atten_Offset3,
	ULO_Gain_Atten_Offset4,
	ULO_Level_High_Threshold,
	UL_Ctrl1_null1,
	ULO_Level_High_Threshold_default,
	ULO_Level,

}UL_Ctrl1;
typedef enum{
	ULO_Level_High_Alarm1= 0xE070,
	ULO_Level_High_Alarm2,
	ULO_Level_High_Alarm3,
	ULO_Level_High_Alarm4,

}UL_Ctrl2;
typedef enum{
	ULO_ALC_ON_OFF= 0xE080,
	ULO_ALC_Threshold,
	ULO_ALC_Threshold_Default,
	ULO_Shutdown_ON_OFF,
	ULO_Shutdown_Threshold,
	ULO_Shutdown_Threshold_Default,
	ULO_Shutdown_Retry_Count,
	ULO_ALC_Alarm1,
	ULO_ALC_Alarm2,
	ULO_ALC_Alarm3,
	ULO_ALC_Alarm4,
	ULO_Shutdown_Alarm1,
	ULO_Shutdown_Alarm2,
	ULO_Shutdown_Alarm3,
	ULO_Shutdown_Alarm4,
}UL_Ctrl3;






#define MBIC_PREAMBLE0 0x16
#define MBIC_PREAMBLE1 0x16
#define MBIC_PREAMBLE2 0x16
#define MBIC_PREAMBLE3 0x16
#define MBIC_SUBUID0 0x00
#define MBIC_SUBUID1 0xF1
#define MBIC_RCODE
#define MBIC_TRID
#define MBIC_SEQNUM
#define MBIC_TTL
#define MBIC_TIME
#define MBIC_ERRRESPONSE
#define MBIC_CMD
#define MBIC_LENGTH
#define MBIC_CHECKSHUM
#define MBIC_ETX 0x03




/*
 *
 *
 * ALARM LIST
 *
 */
struct Alarm_ENVIRONMENT {
	uint8_t ENVIRONMENT_Temp_High ;
	uint8_t ENVIRONMENT_Reserved0 ;
	uint8_t ENVIRONMENT_Reserved1 ;
	uint8_t ENVIRONMENT_Reserved2 ;
	uint8_t ENVIRONMENT_Reserved3 ;
	uint8_t ENVIRONMENT_Reserved4 ;
	uint8_t ENVIRONMENT_Reserved5 ;
	uint8_t ENVIRONMENT_Reserved6 ;
};


struct Alarm_DL {
	uint8_t DLI_P4_Level_Low  ;
	uint8_t DLI_P3_Level_Low  ;
	uint8_t DLI_P2_Level_Low  ;
	uint8_t DLI_P1_Level_Low  ;
	uint8_t ULO_P4_Level_High ;
	uint8_t ULO_P3_Level_High ;
	uint8_t ULO_P2_Level_High ;
	uint8_t ULO_P1_Level_High ;
	uint8_t DLI_P4_AGC_Alarm  ;
	uint8_t DLI_P3_AGC_Alarm  ;
	uint8_t DLI_P2_AGC_Alarm  ;
	uint8_t DLI_P1_AGC_Alarm  ;
	uint8_t DLI_P4_Shutdown_Alarm ;
	uint8_t DLI_P3_Shutdown_Alarm ;
	uint8_t DLI_P2_Shutdown_Alarm ;
	uint8_t DLI_P1_Shutdown_Alarm ;
};
struct Alarm_UL {
	uint8_t Reserved0         ;
	uint8_t Reserved1         ;
	uint8_t Reserved2         ;
	uint8_t Reserved3         ;
	uint8_t ULO_P4_Level_High ;
	uint8_t ULO_P3_Level_High ;
	uint8_t ULO_P2_Level_High ;
	uint8_t ULO_P1_Level_High ;
	uint8_t ULO_P4_ALC_Alarm  ;
	uint8_t ULO_P3_ALC_Alarm  ;
	uint8_t ULO_P2_ALC_Alarm  ;
	uint8_t ULO_P1_ALC_Alarm  ;
	uint8_t ULO_P4_Shutdown   ;
	uint8_t ULO_P3_Shutdown   ;
	uint8_t ULO_P2_Shutdown   ;
	uint8_t ULO_P1_Shutdown   ;
};
enum DATATYPE
{
	ATTSET  = 0x11,
	ATT_DL1_PATH = 0x12,
	ATT_UL1_PATH = 0x16,
	ATT_SelfTest1 = 0x18,
	ATT_DL2_PATH = 0x22,
	ATT_UL2_PATH = 0x26,
	ATT_SelfTest2 = 0x28,
	ATT_DL3_PATH = 0x32,
	ATT_UL3_PATH = 0x36,
	ATT_SelfTest3 = 0x38,
	ATT_DL4_PATH = 0x42,
	ATT_UL4_PATH = 0x46,
	ATT_SelfTest4 = 0x48,
	ALC1_EN = 0x51,
	ALC2_EN = 0x52,
	ALC3_EN = 0x53,
	ALC4_EN = 0x54,
    AGC1_EN = 0x61,
    AGC2_EN = 0x62,
    AGC3_EN = 0x63,
    AGC4_EN = 0x64,
	Bluecell_StatusReq = 0x77,
};


#define ALARM_ENVIRONMENT_FLAG 0x80
#define ALARM_DL1_FLAG 0xFF
#define ALARM_DL2_FLAG 0xFF
#define ALARM_UL1_FLAG 0x0F
#define ALARM_UL2_FLAG 0xFF

typedef enum{
	ENVIRONMENT = 0,
	DL1,
	DL2,
	UL1,
	UL2,
	MAX_ALARM_Len,
}AlarmList;


typedef struct{
  uint16_t m15_dBm;
  uint16_t m16_dBm;
  uint16_t m17_dBm;
  uint16_t m18_dBm;
  uint16_t m19_dBm;
  uint16_t m20_dBm;
  uint16_t m21_dBm;
  uint16_t m22_dBm;
  uint16_t m23_dBm;
  uint16_t m24_dBm;
  uint16_t m25_dBm;
  uint16_t m26_dBm;
  uint16_t m27_dBm;
  uint16_t m28_dBm;
  uint16_t m29_dBm;
  uint16_t m30_dBm;
  uint16_t m31_dBm;
  uint16_t m32_dBm;
  uint16_t m33_dBm;
  uint16_t m34_dBm;
  uint16_t m35_dBm;
  uint16_t m36_dBm;
  uint16_t m37_dBm;
  uint16_t m38_dBm;
  uint16_t m39_dBm;
  uint16_t m40_dBm;
  uint16_t m41_dBm;
  uint16_t m42_dBm;
  uint16_t m43_dBm;
  uint16_t m44_dBm;
  uint16_t m45_dBm;
  uint16_t m46_dBm;
  uint16_t m47_dBm;
  uint16_t m48_dBm;
  uint16_t m49_dBm;
  uint16_t m50_dBm;
  uint16_t m51_dBm;
  uint16_t m52_dBm;
  uint16_t m53_dBm;
  uint16_t m54_dBm;
  uint16_t m55_dBm;
  uint16_t m56_dBm;
  uint16_t m57_dBm;
  uint16_t m58_dBm;
  uint16_t m59_dBm;
  uint16_t m60_dBm;
}DET_UL;

typedef struct{
  uint16_t p5_dBm;
  uint16_t p4_dBm;
  uint16_t p3_dBm;
  uint16_t p2_dBm;
  uint16_t p1_dBm;
  uint16_t m0_dBm;
  uint16_t m1_dBm;
  uint16_t m2_dBm;
  uint16_t m3_dBm;
  uint16_t m4_dBm;
  uint16_t m5_dBm;
  uint16_t m6_dBm;
  uint16_t m7_dBm;
  uint16_t m8_dBm;
  uint16_t m9_dBm;
  uint16_t m10_dBm;
  uint16_t m11_dBm;
  uint16_t m12_dBm;
  uint16_t m13_dBm;
  uint16_t m14_dBm;
  uint16_t m15_dBm;
  uint16_t m16_dBm;
  uint16_t m17_dBm;
  uint16_t m18_dBm;
  uint16_t m19_dBm;
  uint16_t m20_dBm;
  uint16_t m21_dBm;
  uint16_t m22_dBm;
  uint16_t m23_dBm;
  uint16_t m24_dBm;
  uint16_t m25_dBm;
}DET_DL;
typedef struct{
    uint8_t bluecell_header;
    uint8_t bluecell_type;
    uint8_t bluecell_length;    
    uint8_t bluecell_crcindex;        
    uint8_t Selftest0;
    uint8_t Selftest1;
    uint8_t Selftest2;
    uint8_t Selftest3;    
    uint8_t ATT_DL1_PATH;    
    uint8_t ATT_DL2_PATH;    
    uint8_t ATT_DL3_PATH;    
    uint8_t ATT_DL4_PATH;        
    uint8_t ATT_UL1_PATH;        
    uint8_t ATT_UL2_PATH;        
    uint8_t ATT_UL3_PATH;        
    uint8_t ATT_UL4_PATH;
    uint8_t ATT_DL1_H;    
    uint8_t ATT_DL1_L;        
    uint8_t ATT_DL2_H;    
    uint8_t ATT_DL2_L;        
    uint8_t ATT_DL3_H;    
    uint8_t ATT_DL3_L;        
    uint8_t ATT_DL4_H;    
    uint8_t ATT_DL4_L;        
    uint8_t ATT_UL1_H;    
    uint8_t ATT_UL1_L;        
    uint8_t ATT_UL2_H;    
    uint8_t ATT_UL2_L;        
    uint8_t ATT_UL3_H;    
    uint8_t ATT_UL3_L;        
    uint8_t ATT_UL4_H;
    uint8_t ATT_UL4_L;
    uint8_t DET_DL1_IN_H;
    uint8_t DET_DL1_IN_L;    
    uint8_t DET_DL2_IN_H;
    uint8_t DET_DL2_IN_L;    
    uint8_t DET_DL3_IN_H;
    uint8_t DET_DL3_IN_L;    
    uint8_t DET_DL4_IN_H;
    uint8_t DET_DL4_IN_L;    
    uint8_t DET_UL1_IN_H;
    uint8_t DET_UL1_IN_L;    
    uint8_t DET_UL2_IN_H;
    uint8_t DET_UL2_IN_L;    
    uint8_t DET_UL3_IN_H;
    uint8_t DET_UL3_IN_L;    
    uint8_t DET_UL4_IN_H;
    uint8_t DET_UL4_IN_L;        
    uint8_t DET_TEMP_H;            
    uint8_t DET_TEMP_L;                
    uint8_t ATT_AGC1_ONOFF;
    uint8_t ATT_ALC1_ONOFF;
    uint8_t ATT_AGC2_ONOFF;
    uint8_t ATT_ALC2_ONOFF;
    uint8_t ATT_AGC3_ONOFF;
    uint8_t ATT_ALC3_ONOFF;
    uint8_t ATT_AGC4_ONOFF;
    uint8_t ATT_ALC4_ONOFF;
    uint8_t ATT_AGC1_H;
    uint8_t ATT_AGC1_L;    
    uint8_t ATT_ALC1_H;
    uint8_t ATT_ALC1_L;    
    uint8_t ATT_AGC2_H;
    uint8_t ATT_AGC2_L;    
    uint8_t ATT_ALC2_H;
    uint8_t ATT_ALC2_L;    
    uint8_t ATT_AGC3_H;
    uint8_t ATT_AGC3_L;    
    uint8_t ATT_ALC3_H;
    uint8_t ATT_ALC3_L;    
    uint8_t ATT_AGC4_H;
    uint8_t ATT_AGC4_L;    
    uint8_t ATT_ALC4_H;
    uint8_t ATT_ALC4_L;    
    uint8_t bluecell_crc;        
}BLUESTATUS_st;
typedef enum{
  Bluecell_DET_UL1_ADC_INDEX_H = 0,
  Bluecell_DET_UL1_ADC_INDEX_L,
  Bluecell_DET_UL2_ADC_INDEX_H,
  Bluecell_DET_UL2_ADC_INDEX_L,
  Bluecell_DET_UL3_ADC_INDEX_H,
  Bluecell_DET_UL3_ADC_INDEX_L,
  Bluecell_RFU_TEMP_ADC_INDEX_H,
  Bluecell_RFU_TEMP_ADC_INDEX_L,
  Bluecell_ADC1_MaxLength,
}Bluecell_ADC1_Index;
typedef enum{
  Bluecell_DET_UL4_ADC_INDEX_H = Bluecell_ADC1_MaxLength,
  Bluecell_DET_UL4_ADC_INDEX_L,
  Bluecell_DET_DL1_ADC_INDEX_H,
  Bluecell_DET_DL1_ADC_INDEX_L,
  Bluecell_DET_DL2_ADC_INDEX_H,
  Bluecell_DET_DL2_ADC_INDEX_L,
  Bluecell_DET_DL3_ADC_INDEX_H,
  Bluecell_DET_DL3_ADC_INDEX_L,
  Bluecell_DET_DL4_ADC_INDEX_H,
  Bluecell_DET_DL4_ADC_INDEX_L,
  Bluecell_ADC3_MaxLength,
}Bluecell_ADC3_Index;
#define ADC1_EA Bluecell_ADC1_MaxLength /2
#define ADC3_EA Bluecell_ADC3_MaxLength /2
#endif /* BLUECELL_OPERATE_H_ */