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DCT 주말 수정 사항

1. PE43711 Data 주고 받는 과정의 계산 식 변경
(블루셀 계산 식 모든 데이터에 100을 곱한 후 부호 없는 2바이트 데이터 전송)
(DCT 계산 식 모든 데이터를 계산 없이 부호 있는 2바이트 데이터 전송)

2. 현재 Level 표시 할 수 있도록 수정

3. 모든 Length  각각 Plus 하도록 수정

4.여러개의 프로토콜이 들어왔을 때 한번에 처리 할 수 있도록 수정
PYJ 5 years ago
parent
commit
a2a6c23ef4

+ 2 - 2
.settings/language.settings.xml

@@ -4,7 +4,7 @@
4
 		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
4
 		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
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 			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
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 			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
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 			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
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 			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
7
-			<provider class="com.atollic.truestudio.mbs.GCCSpecsDetectorAtollicArm" console="false" env-hash="1681877287601945682" id="com.atollic.truestudio.mbs.provider" keep-relative-paths="false" name="Atollic ARM Tools Language Settings" parameter="${COMMAND} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
7
+			<provider class="com.atollic.truestudio.mbs.GCCSpecsDetectorAtollicArm" console="false" env-hash="800489075853895203" id="com.atollic.truestudio.mbs.provider" keep-relative-paths="false" name="Atollic ARM Tools Language Settings" parameter="${COMMAND} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
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 				<language-scope id="org.eclipse.cdt.core.gcc"/>
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 				<language-scope id="org.eclipse.cdt.core.gcc"/>
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 				<language-scope id="org.eclipse.cdt.core.g++"/>
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 				<language-scope id="org.eclipse.cdt.core.g++"/>
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 			</provider>
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 			</provider>
@@ -14,7 +14,7 @@
14
 		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
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 		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
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 			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
15
 			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
16
 			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
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 			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
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-			<provider class="com.atollic.truestudio.mbs.GCCSpecsDetectorAtollicArm" console="false" env-hash="1681877287601945682" id="com.atollic.truestudio.mbs.provider" keep-relative-paths="false" name="Atollic ARM Tools Language Settings" parameter="${COMMAND} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
17
+			<provider class="com.atollic.truestudio.mbs.GCCSpecsDetectorAtollicArm" console="false" env-hash="800489075853895203" id="com.atollic.truestudio.mbs.provider" keep-relative-paths="false" name="Atollic ARM Tools Language Settings" parameter="${COMMAND} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
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 				<language-scope id="org.eclipse.cdt.core.gcc"/>
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 				<language-scope id="org.eclipse.cdt.core.gcc"/>
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 				<language-scope id="org.eclipse.cdt.core.g++"/>
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 				<language-scope id="org.eclipse.cdt.core.g++"/>
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 			</provider>
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 			</provider>

+ 20 - 20
Bluecell_Inc/Bluecell_operate.h

@@ -646,6 +646,25 @@ typedef struct{
646
     uint8_t ATT_UL3_L;
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     uint8_t ATT_UL3_L;
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     uint8_t ATT_UL4_H;
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     uint8_t ATT_UL4_H;
648
     uint8_t ATT_UL4_L;
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     uint8_t ATT_UL4_L;
649
+    uint8_t ULO_P1_Level1_H;
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+    uint8_t ULO_P1_Level1_L;
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+    uint8_t ULO_P2_Level2_H;
652
+    uint8_t ULO_P2_Level2_L;
653
+    uint8_t ULO_P3_Level3_H;
654
+    uint8_t ULO_P3_Level3_L;
655
+    uint8_t ULO_P4_Level4_H;
656
+    uint8_t ULO_P4_Level4_L;
657
+    uint8_t DLI_P1_Level1_H;
658
+    uint8_t DLI_P1_Level1_L;
659
+    uint8_t DLI_P2_Level2_H;
660
+    uint8_t DLI_P2_Level2_L;
661
+    uint8_t DLI_P3_Level3_H;
662
+    uint8_t DLI_P3_Level3_L;
663
+    uint8_t DLI_P4_Level4_H;
664
+    uint8_t DLI_P4_Level4_L;    
665
+    uint8_t DET_TEMP;
666
+    uint8_t DLI_AGC_ON_OFF;
667
+    uint8_t ULO_ALC_ON_OFF;
649
     uint8_t ULO_Level1_H;
668
     uint8_t ULO_Level1_H;
650
     uint8_t ULO_Level1_L;
669
     uint8_t ULO_Level1_L;
651
     uint8_t ULO_Level2_H;
670
     uint8_t ULO_Level2_H;
@@ -661,28 +680,9 @@ typedef struct{
661
     uint8_t DLI_Level3_H;
680
     uint8_t DLI_Level3_H;
662
     uint8_t DLI_Level3_L;
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     uint8_t DLI_Level3_L;
663
     uint8_t DLI_Level4_H;
682
     uint8_t DLI_Level4_H;
664
-    uint8_t DLI_Level4_L;    
665
-    uint8_t BLUECELL_RESERVE1;
666
-    uint8_t DET_TEMP;
667
-    uint8_t DLI_AGC_ON_OFF;
668
-    uint8_t ULO_ALC_ON_OFF;
669
-    uint8_t BLUECELL_RESERVE2;
670
-    uint8_t BLUECELL_RESERVE3;
671
-    uint8_t BLUECELL_RESERVE4;
672
-    uint8_t BLUECELL_RESERVE5;
673
-    uint8_t BLUECELL_RESERVE6;
674
-    uint8_t BLUECELL_RESERVE7;
675
-    uint8_t BLUECELL_RESERVE8;
676
-    uint8_t BLUECELL_RESERVE9;
677
-    uint8_t BLUECELL_RESERVE10;
678
-    uint8_t BLUECELL_RESERVE11;
679
-    uint8_t BLUECELL_RESERVE12;
680
-    uint8_t BLUECELL_RESERVE13;
681
-    uint8_t BLUECELL_RESERVE14;
682
-    uint8_t BLUECELL_RESERVE15;
683
+    uint8_t DLI_Level4_L; 
683
     uint8_t ULO_ALC_Threshold_H;
684
     uint8_t ULO_ALC_Threshold_H;
684
     uint8_t ULO_ALC_Threshold_L;
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     uint8_t ULO_ALC_Threshold_L;
685
-    uint8_t BLUECELL_RESERVE16;
686
     uint8_t BLUECELL_RESERVE17;
686
     uint8_t BLUECELL_RESERVE17;
687
     uint8_t BLUECELL_RESERVE18;
687
     uint8_t BLUECELL_RESERVE18;
688
     uint8_t BLUECELL_RESERVE19;
688
     uint8_t BLUECELL_RESERVE19;

File diff suppressed because it is too large
+ 497 - 211
Bluecell_Src/Bluecell_operate.c


+ 15 - 6
Bluecell_Src/uart.c

@@ -22,7 +22,12 @@ void InitUartQueue(pUARTQUEUE pQueue)
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 {
22
 {
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   pQueue->data = pQueue->head = pQueue->tail = 0;
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   pQueue->data = pQueue->head = pQueue->tail = 0;
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   uart_hal_tx.output_p = uart_hal_tx.input_p = 0;
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   uart_hal_tx.output_p = uart_hal_tx.input_p = 0;
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+//  HAL_UART_Receive_IT(&huart2,rxBuf,5);
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+
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+
28
+
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   if (HAL_UART_Receive_DMA(&hTerminal, TerminalQueue.Buffer, 1) != HAL_OK)
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   if (HAL_UART_Receive_DMA(&hTerminal, TerminalQueue.Buffer, 1) != HAL_OK)
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+  //if (HAL_UART_Receive_IT(&hTerminal, TerminalQueue.Buffer, 1) != HAL_OK)
26
   {
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   {
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 //    _Error_Handler(__FILE__, __LINE__);
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 //    _Error_Handler(__FILE__, __LINE__);
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   }  
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   }  
@@ -92,7 +97,7 @@ void GetDataFromUartQueue(UART_HandleTypeDef *huart)
92
 //        printf("data cnt zero !!!  \r\n");
97
 //        printf("data cnt zero !!!  \r\n");
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         //RF_Ctrl_Main(&uart_buf[Header]);
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         //RF_Ctrl_Main(&uart_buf[Header]);
94
 //        HAL_UART_Transmit(dst, &temp_buf[BLUECELL_HEADER00], 11, 3000);
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 //        HAL_UART_Transmit(dst, &temp_buf[BLUECELL_HEADER00], 11, 3000);
95
-#if 0 // PYJ.2019.07.15_BEGIN --
100
+#if 1 // PYJ.2019.07.15_BEGIN --
96
             for(int i = 0; i < cnt; i++){
101
             for(int i = 0; i < cnt; i++){
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                 printf("%02x ",uart_buf[i]);
102
                 printf("%02x ",uart_buf[i]);
98
             }
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             }
@@ -111,6 +116,8 @@ void GetDataFromUartQueue(UART_HandleTypeDef *huart)
111
                     CrcChk = ((uart_buf[MBIC_PAYLOADSTART + Length + 1] << 8) | (uart_buf[MBIC_PAYLOADSTART + Length + 2]));
116
                     CrcChk = ((uart_buf[MBIC_PAYLOADSTART + Length + 1] << 8) | (uart_buf[MBIC_PAYLOADSTART + Length + 2]));
112
                     if(CRC16_Check(&uart_buf[MBIC_PAYLOADSTART], Length,CrcChk))
117
                     if(CRC16_Check(&uart_buf[MBIC_PAYLOADSTART], Length,CrcChk))
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                         MBIC_Operate(uart_buf);
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                         MBIC_Operate(uart_buf);
119
+                    else
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+                      printf("CRC ERROR \r\n");
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                }
121
                }
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                else
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                else
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                {
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                {
@@ -130,12 +137,14 @@ void Uart_Check(void){
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 }
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 }
131
 
138
 
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 void Uart1_Data_Send(uint8_t* data,uint16_t size){
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 void Uart1_Data_Send(uint8_t* data,uint16_t size){
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-    HAL_UART_Transmit_DMA(&hTerminal, data,size); 
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-    
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-//    printf("\r\n [TX]  ");
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+    HAL_UART_Transmit(&hTerminal, &data[0],size,0xFFFF);
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+  //HAL_UART_Transmit_IT(&hTerminal, &data[0],size);
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+//    printf("data[278] : %x \r\n",data[278]);
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+////    HAL_Delay(1);   
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+//    printf("\r\n [TX] : ");
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 //    for(int i = 0; i< size; i++)
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 //    for(int i = 0; i< size; i++)
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-//        printf(" %02x",data[i]);
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-//    printf("COUNT : %d",size);
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+//        printf(" %02x ",data[i]);
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+//    printf("\r\n\tCOUNT : %d",size);
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 //    printf("\r\n");
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 //    printf("\r\n");
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149
     
141
 }
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 }

File diff suppressed because it is too large
+ 51 - 50
STM32F103ZET_JDASMBIC.elf.launch


+ 69 - 69
STM32F103ZET_JDASMBIC.ioc

@@ -36,67 +36,67 @@ ADC3.SamplingTime-1\#ChannelRegularConversion=ADC_SAMPLETIME_239CYCLES_5
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 ADC3.SamplingTime-2\#ChannelRegularConversion=ADC_SAMPLETIME_239CYCLES_5
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 ADC3.SamplingTime-2\#ChannelRegularConversion=ADC_SAMPLETIME_239CYCLES_5
37
 ADC3.SamplingTime-3\#ChannelRegularConversion=ADC_SAMPLETIME_239CYCLES_5
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 ADC3.SamplingTime-3\#ChannelRegularConversion=ADC_SAMPLETIME_239CYCLES_5
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 ADC3.SamplingTime-4\#ChannelRegularConversion=ADC_SAMPLETIME_239CYCLES_5
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 ADC3.SamplingTime-4\#ChannelRegularConversion=ADC_SAMPLETIME_239CYCLES_5
39
-Dma.ADC1.2.Direction=DMA_PERIPH_TO_MEMORY
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-Dma.ADC1.2.Instance=DMA1_Channel1
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-Dma.ADC1.2.MemDataAlignment=DMA_MDATAALIGN_HALFWORD
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-Dma.ADC1.2.MemInc=DMA_MINC_ENABLE
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-Dma.ADC1.2.Mode=DMA_CIRCULAR
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-Dma.ADC1.2.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD
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-Dma.ADC1.2.PeriphInc=DMA_PINC_DISABLE
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-Dma.ADC1.2.Priority=DMA_PRIORITY_LOW
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-Dma.ADC1.2.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority
48
-Dma.ADC3.3.Direction=DMA_PERIPH_TO_MEMORY
49
-Dma.ADC3.3.Instance=DMA2_Channel5
50
-Dma.ADC3.3.MemDataAlignment=DMA_MDATAALIGN_HALFWORD
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-Dma.ADC3.3.MemInc=DMA_MINC_ENABLE
52
-Dma.ADC3.3.Mode=DMA_CIRCULAR
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-Dma.ADC3.3.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD
54
-Dma.ADC3.3.PeriphInc=DMA_PINC_DISABLE
55
-Dma.ADC3.3.Priority=DMA_PRIORITY_LOW
56
-Dma.ADC3.3.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority
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-Dma.Request0=USART1_RX
58
-Dma.Request1=USART1_TX
59
-Dma.Request2=ADC1
60
-Dma.Request3=ADC3
61
-Dma.Request4=USART2_RX
62
-Dma.Request5=USART2_TX
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+Dma.ADC1.0.Direction=DMA_PERIPH_TO_MEMORY
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+Dma.ADC1.0.Instance=DMA1_Channel1
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+Dma.ADC1.0.MemDataAlignment=DMA_MDATAALIGN_HALFWORD
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+Dma.ADC1.0.MemInc=DMA_MINC_ENABLE
43
+Dma.ADC1.0.Mode=DMA_CIRCULAR
44
+Dma.ADC1.0.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD
45
+Dma.ADC1.0.PeriphInc=DMA_PINC_DISABLE
46
+Dma.ADC1.0.Priority=DMA_PRIORITY_LOW
47
+Dma.ADC1.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority
48
+Dma.ADC3.1.Direction=DMA_PERIPH_TO_MEMORY
49
+Dma.ADC3.1.Instance=DMA2_Channel5
50
+Dma.ADC3.1.MemDataAlignment=DMA_MDATAALIGN_HALFWORD
51
+Dma.ADC3.1.MemInc=DMA_MINC_ENABLE
52
+Dma.ADC3.1.Mode=DMA_CIRCULAR
53
+Dma.ADC3.1.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD
54
+Dma.ADC3.1.PeriphInc=DMA_PINC_DISABLE
55
+Dma.ADC3.1.Priority=DMA_PRIORITY_LOW
56
+Dma.ADC3.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority
57
+Dma.Request0=ADC1
58
+Dma.Request1=ADC3
59
+Dma.Request2=USART2_RX
60
+Dma.Request3=USART2_TX
61
+Dma.Request4=USART1_RX
62
+Dma.Request5=USART1_TX
63
 Dma.RequestsNb=6
63
 Dma.RequestsNb=6
64
-Dma.USART1_RX.0.Direction=DMA_PERIPH_TO_MEMORY
65
-Dma.USART1_RX.0.Instance=DMA1_Channel5
66
-Dma.USART1_RX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE
67
-Dma.USART1_RX.0.MemInc=DMA_MINC_ENABLE
68
-Dma.USART1_RX.0.Mode=DMA_NORMAL
69
-Dma.USART1_RX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
70
-Dma.USART1_RX.0.PeriphInc=DMA_PINC_DISABLE
71
-Dma.USART1_RX.0.Priority=DMA_PRIORITY_LOW
72
-Dma.USART1_RX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority
73
-Dma.USART1_TX.1.Direction=DMA_MEMORY_TO_PERIPH
74
-Dma.USART1_TX.1.Instance=DMA1_Channel4
75
-Dma.USART1_TX.1.MemDataAlignment=DMA_MDATAALIGN_BYTE
76
-Dma.USART1_TX.1.MemInc=DMA_MINC_ENABLE
77
-Dma.USART1_TX.1.Mode=DMA_NORMAL
78
-Dma.USART1_TX.1.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
79
-Dma.USART1_TX.1.PeriphInc=DMA_PINC_DISABLE
80
-Dma.USART1_TX.1.Priority=DMA_PRIORITY_LOW
81
-Dma.USART1_TX.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority
82
-Dma.USART2_RX.4.Direction=DMA_PERIPH_TO_MEMORY
83
-Dma.USART2_RX.4.Instance=DMA1_Channel6
84
-Dma.USART2_RX.4.MemDataAlignment=DMA_MDATAALIGN_BYTE
85
-Dma.USART2_RX.4.MemInc=DMA_MINC_ENABLE
86
-Dma.USART2_RX.4.Mode=DMA_NORMAL
87
-Dma.USART2_RX.4.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
88
-Dma.USART2_RX.4.PeriphInc=DMA_PINC_DISABLE
89
-Dma.USART2_RX.4.Priority=DMA_PRIORITY_LOW
90
-Dma.USART2_RX.4.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority
91
-Dma.USART2_TX.5.Direction=DMA_MEMORY_TO_PERIPH
92
-Dma.USART2_TX.5.Instance=DMA1_Channel7
93
-Dma.USART2_TX.5.MemDataAlignment=DMA_MDATAALIGN_BYTE
94
-Dma.USART2_TX.5.MemInc=DMA_MINC_ENABLE
95
-Dma.USART2_TX.5.Mode=DMA_NORMAL
96
-Dma.USART2_TX.5.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
97
-Dma.USART2_TX.5.PeriphInc=DMA_PINC_DISABLE
98
-Dma.USART2_TX.5.Priority=DMA_PRIORITY_LOW
99
-Dma.USART2_TX.5.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority
64
+Dma.USART1_RX.4.Direction=DMA_PERIPH_TO_MEMORY
65
+Dma.USART1_RX.4.Instance=DMA1_Channel5
66
+Dma.USART1_RX.4.MemDataAlignment=DMA_MDATAALIGN_BYTE
67
+Dma.USART1_RX.4.MemInc=DMA_MINC_ENABLE
68
+Dma.USART1_RX.4.Mode=DMA_NORMAL
69
+Dma.USART1_RX.4.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
70
+Dma.USART1_RX.4.PeriphInc=DMA_PINC_DISABLE
71
+Dma.USART1_RX.4.Priority=DMA_PRIORITY_LOW
72
+Dma.USART1_RX.4.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority
73
+Dma.USART1_TX.5.Direction=DMA_MEMORY_TO_PERIPH
74
+Dma.USART1_TX.5.Instance=DMA1_Channel4
75
+Dma.USART1_TX.5.MemDataAlignment=DMA_MDATAALIGN_BYTE
76
+Dma.USART1_TX.5.MemInc=DMA_MINC_ENABLE
77
+Dma.USART1_TX.5.Mode=DMA_NORMAL
78
+Dma.USART1_TX.5.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
79
+Dma.USART1_TX.5.PeriphInc=DMA_PINC_DISABLE
80
+Dma.USART1_TX.5.Priority=DMA_PRIORITY_LOW
81
+Dma.USART1_TX.5.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority
82
+Dma.USART2_RX.2.Direction=DMA_PERIPH_TO_MEMORY
83
+Dma.USART2_RX.2.Instance=DMA1_Channel6
84
+Dma.USART2_RX.2.MemDataAlignment=DMA_MDATAALIGN_BYTE
85
+Dma.USART2_RX.2.MemInc=DMA_MINC_ENABLE
86
+Dma.USART2_RX.2.Mode=DMA_NORMAL
87
+Dma.USART2_RX.2.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
88
+Dma.USART2_RX.2.PeriphInc=DMA_PINC_DISABLE
89
+Dma.USART2_RX.2.Priority=DMA_PRIORITY_LOW
90
+Dma.USART2_RX.2.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority
91
+Dma.USART2_TX.3.Direction=DMA_MEMORY_TO_PERIPH
92
+Dma.USART2_TX.3.Instance=DMA1_Channel7
93
+Dma.USART2_TX.3.MemDataAlignment=DMA_MDATAALIGN_BYTE
94
+Dma.USART2_TX.3.MemInc=DMA_MINC_ENABLE
95
+Dma.USART2_TX.3.Mode=DMA_NORMAL
96
+Dma.USART2_TX.3.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
97
+Dma.USART2_TX.3.PeriphInc=DMA_PINC_DISABLE
98
+Dma.USART2_TX.3.Priority=DMA_PRIORITY_LOW
99
+Dma.USART2_TX.3.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority
100
 File.Version=6
100
 File.Version=6
101
 GPIO.groupedBy=Group By Peripherals
101
 GPIO.groupedBy=Group By Peripherals
102
 I2C2.I2C_Mode=I2C_Fast
102
 I2C2.I2C_Mode=I2C_Fast
@@ -179,14 +179,14 @@ Mcu.UserName=STM32F103ZETx
179
 MxCube.Version=5.6.1
179
 MxCube.Version=5.6.1
180
 MxDb.Version=DB.5.0.60
180
 MxDb.Version=DB.5.0.60
181
 NVIC.ADC1_2_IRQn=true\:0\:0\:false\:false\:true\:true\:true
181
 NVIC.ADC1_2_IRQn=true\:0\:0\:false\:false\:true\:true\:true
182
-NVIC.ADC3_IRQn=true\:0\:0\:false\:true\:true\:8\:true\:true
182
+NVIC.ADC3_IRQn=true\:0\:0\:false\:true\:true\:6\:true\:true
183
 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
183
 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
184
 NVIC.DMA1_Channel1_IRQn=true\:0\:0\:false\:true\:true\:1\:false\:true
184
 NVIC.DMA1_Channel1_IRQn=true\:0\:0\:false\:true\:true\:1\:false\:true
185
-NVIC.DMA1_Channel4_IRQn=true\:0\:0\:false\:true\:true\:2\:false\:true
186
-NVIC.DMA1_Channel5_IRQn=true\:0\:0\:false\:true\:true\:3\:false\:true
187
-NVIC.DMA1_Channel6_IRQn=true\:0\:0\:false\:true\:true\:9\:false\:true
188
-NVIC.DMA1_Channel7_IRQn=true\:0\:0\:false\:true\:true\:10\:false\:true
189
-NVIC.DMA2_Channel4_5_IRQn=true\:0\:0\:false\:true\:true\:6\:false\:true
185
+NVIC.DMA1_Channel4_IRQn=true\:0\:0\:false\:true\:true\:9\:false\:true
186
+NVIC.DMA1_Channel5_IRQn=true\:0\:0\:false\:true\:true\:10\:false\:true
187
+NVIC.DMA1_Channel6_IRQn=true\:0\:0\:false\:true\:true\:7\:false\:true
188
+NVIC.DMA1_Channel7_IRQn=true\:0\:0\:false\:true\:true\:8\:false\:true
189
+NVIC.DMA2_Channel4_5_IRQn=true\:0\:0\:false\:true\:true\:4\:false\:true
190
 NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
190
 NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
191
 NVIC.ForceEnableDMAVector=true
191
 NVIC.ForceEnableDMAVector=true
192
 NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
192
 NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
@@ -197,11 +197,11 @@ NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
197
 NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
197
 NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
198
 NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
198
 NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
199
 NVIC.TIM2_IRQn=true\:0\:0\:false\:false\:true\:false\:true
199
 NVIC.TIM2_IRQn=true\:0\:0\:false\:false\:true\:false\:true
200
-NVIC.TIM6_IRQn=true\:0\:0\:false\:true\:true\:7\:true\:true
200
+NVIC.TIM6_IRQn=true\:0\:0\:false\:true\:true\:5\:true\:true
201
 NVIC.TimeBase=TIM2_IRQn
201
 NVIC.TimeBase=TIM2_IRQn
202
 NVIC.TimeBaseIP=TIM2
202
 NVIC.TimeBaseIP=TIM2
203
-NVIC.USART1_IRQn=true\:0\:0\:false\:true\:true\:4\:true\:true
204
-NVIC.USART2_IRQn=true\:0\:0\:false\:true\:true\:5\:true\:true
203
+NVIC.USART1_IRQn=true\:0\:0\:false\:true\:true\:2\:true\:true
204
+NVIC.USART2_IRQn=true\:0\:0\:false\:true\:true\:3\:true\:true
205
 NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
205
 NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
206
 PA10.GPIOParameters=GPIO_Label
206
 PA10.GPIOParameters=GPIO_Label
207
 PA10.GPIO_Label=MBIC_DOWN
207
 PA10.GPIO_Label=MBIC_DOWN

+ 1 - 1
STM32F103ZE_FLASH.ld

@@ -62,7 +62,7 @@ _Min_Stack_Size = 0x400; /* required amount of stack */
62
 MEMORY
62
 MEMORY
63
 {
63
 {
64
 RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 64K
64
 RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 64K
65
-FLASH (rx)      : ORIGIN = 0x8005000, LENGTH = 64K
65
+FLASH (rx)      : ORIGIN = 0x8005000, LENGTH = 512K
66
 }
66
 }
67
 
67
 
68
 /* Define output sections */
68
 /* Define output sections */

+ 9 - 9
Src/main.c

@@ -147,7 +147,7 @@ void Pol_Delay_us(volatile uint32_t microseconds)
147
 
147
 
148
 int _write (int file, uint8_t *ptr, uint16_t len)
148
 int _write (int file, uint8_t *ptr, uint16_t len)
149
 {
149
 {
150
-#if 0 // PYJ.2020.06.03_BEGIN -- 
150
+#if 1 // PYJ.2020.06.03_BEGIN --
151
     HAL_UART_Transmit(&hTest, ptr, len,10);
151
     HAL_UART_Transmit(&hTest, ptr, len,10);
152
 #else
152
 #else
153
     HAL_UART_Transmit(&hTerminal, ptr, len,10);    
153
     HAL_UART_Transmit(&hTerminal, ptr, len,10);    
@@ -162,7 +162,7 @@ uint16_t adc3cnt = 0 ;
162
 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
162
 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
163
 {
163
 {
164
 //?��?��?�� 코드 ?��?��
164
 //?��?��?�� 코드 ?��?��
165
-//諤嵸烄 ?嚙踝蕭?嚙踝蕭 adc?嚙踝蕭嚙??????????? 嚙????????????嚙踝蕭?嚙踝蕭 ?嚙踝蕭 ?嚙踝蕭?嚙踝蕭嚙??????????? ?嚙踝蕭?嚙踝蕭嚙??????????? ?嚙踝蕭?嚙踝蕭?? 穈軤𦚯 魽國探嚙??????????? ?嚙踝蕭?嚙踝蕭
165
+//諤嵸烄 ?嚙踝蕭?嚙踝蕭 adc?嚙踝蕭嚙?????????????????????????嚙踝蕭?嚙踝蕭 ?嚙踝蕭 ?嚙踝蕭?嚙踝蕭嚙???????????? ?嚙踝蕭?嚙踝蕭嚙???????????? ?嚙踝蕭?嚙踝蕭?? 穈軤𦚯 魽國探嚙???????????? ?嚙踝蕭?嚙踝蕭
166
 
166
 
167
     if(hadc->Instance == hadc1.Instance)
167
     if(hadc->Instance == hadc1.Instance)
168
     {
168
     {
@@ -399,7 +399,7 @@ int main(void)
399
     AGC_Function();    /*AGC Function*/
399
     AGC_Function();    /*AGC Function*/
400
     Alarm_Check();     /*Function to check all alarm status variables*/
400
     Alarm_Check();     /*Function to check all alarm status variables*/
401
 //    Uart1_Data_Send("A",1);
401
 //    Uart1_Data_Send("A",1);
402
-//    HAL_Delay(500);
402
+//    HAL_Delay(1);
403
     /* USER CODE END WHILE */
403
     /* USER CODE END WHILE */
404
 
404
 
405
     /* USER CODE BEGIN 3 */
405
     /* USER CODE BEGIN 3 */
@@ -459,12 +459,6 @@ static void MX_NVIC_Init(void)
459
   /* DMA1_Channel1_IRQn interrupt configuration */
459
   /* DMA1_Channel1_IRQn interrupt configuration */
460
   HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
460
   HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
461
   HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
461
   HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
462
-  /* DMA1_Channel4_IRQn interrupt configuration */
463
-  HAL_NVIC_SetPriority(DMA1_Channel4_IRQn, 0, 0);
464
-  HAL_NVIC_EnableIRQ(DMA1_Channel4_IRQn);
465
-  /* DMA1_Channel5_IRQn interrupt configuration */
466
-  HAL_NVIC_SetPriority(DMA1_Channel5_IRQn, 0, 0);
467
-  HAL_NVIC_EnableIRQ(DMA1_Channel5_IRQn);
468
   /* USART1_IRQn interrupt configuration */
462
   /* USART1_IRQn interrupt configuration */
469
   HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
463
   HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
470
   HAL_NVIC_EnableIRQ(USART1_IRQn);
464
   HAL_NVIC_EnableIRQ(USART1_IRQn);
@@ -486,6 +480,12 @@ static void MX_NVIC_Init(void)
486
   /* DMA1_Channel7_IRQn interrupt configuration */
480
   /* DMA1_Channel7_IRQn interrupt configuration */
487
   HAL_NVIC_SetPriority(DMA1_Channel7_IRQn, 0, 0);
481
   HAL_NVIC_SetPriority(DMA1_Channel7_IRQn, 0, 0);
488
   HAL_NVIC_EnableIRQ(DMA1_Channel7_IRQn);
482
   HAL_NVIC_EnableIRQ(DMA1_Channel7_IRQn);
483
+  /* DMA1_Channel4_IRQn interrupt configuration */
484
+  HAL_NVIC_SetPriority(DMA1_Channel4_IRQn, 0, 0);
485
+  HAL_NVIC_EnableIRQ(DMA1_Channel4_IRQn);
486
+  /* DMA1_Channel5_IRQn interrupt configuration */
487
+  HAL_NVIC_SetPriority(DMA1_Channel5_IRQn, 0, 0);
488
+  HAL_NVIC_EnableIRQ(DMA1_Channel5_IRQn);
489
 }
489
 }
490
 
490
 
491
 /**
491
 /**