Chip Change First

.settings/com.atollic.truestudio.debug.hardware_device.prefs

@@ -1,7 +1,7 @@
 BOARD=None
 CODE_LOCATION=FLASH
 ENDIAN=Little-endian
-MCU=STM32F103VG
+MCU=STM32F103ZE
 MCU_VENDOR=STMicroelectronics
 MODEL=Lite
 PROBE=ST-LINK

.settings/org.eclipse.cdt.managedbuilder.core.prefs

@@ -0,0 +1,11 @@
+eclipse.preferences.version=1
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.1518366166/CPATH/delimiter=;
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.1518366166/CPATH/operation=remove
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.1518366166/C_INCLUDE_PATH/delimiter=;
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.1518366166/C_INCLUDE_PATH/operation=remove
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.1518366166/append=true
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.1518366166/appendContributed=true
+environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.1518366166/LIBRARY_PATH/delimiter=;
+environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.1518366166/LIBRARY_PATH/operation=remove
+environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.1518366166/append=true
+environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.1518366166/appendContributed=true

Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.su

@@ -0,0 +1,23 @@
+stm32f1xx_hal.c:216:13:HAL_MspInit	0	static
+stm32f1xx_hal.c:227:13:HAL_MspDeInit	0	static
+stm32f1xx_hal.c:191:19:HAL_DeInit	8	static
+stm32f1xx_hal.c:250:26:HAL_InitTick	16	static
+stm32f1xx_hal.c:158:19:HAL_Init	8	static
+stm32f1xx_hal.c:309:13:HAL_IncTick	0	static
+stm32f1xx_hal.c:320:17:HAL_GetTick	0	static
+stm32f1xx_hal.c:329:10:HAL_GetTickPrio	0	static
+stm32f1xx_hal.c:338:19:HAL_SetTickFreq	8	static
+stm32f1xx_hal.c:358:21:HAL_GetTickFreq	0	static
+stm32f1xx_hal.c:374:13:HAL_Delay	16	static
+stm32f1xx_hal.c:400:13:HAL_SuspendTick	0	static
+stm32f1xx_hal.c:416:13:HAL_ResumeTick	0	static
+stm32f1xx_hal.c:426:10:HAL_GetHalVersion	0	static
+stm32f1xx_hal.c:442:10:HAL_GetREVID	0	static
+stm32f1xx_hal.c:458:10:HAL_GetDEVID	0	static
+stm32f1xx_hal.c:467:6:HAL_DBGMCU_EnableDBGSleepMode	0	static
+stm32f1xx_hal.c:483:6:HAL_DBGMCU_DisableDBGSleepMode	0	static
+stm32f1xx_hal.c:513:6:HAL_DBGMCU_EnableDBGStopMode	0	static
+stm32f1xx_hal.c:529:6:HAL_DBGMCU_DisableDBGStopMode	0	static
+stm32f1xx_hal.c:545:6:HAL_DBGMCU_EnableDBGStandbyMode	0	static
+stm32f1xx_hal.c:561:6:HAL_DBGMCU_DisableDBGStandbyMode	0	static
+stm32f1xx_hal.c:571:6:HAL_GetUID	0	static

Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.su

@@ -0,0 +1,27 @@
+stm32f1xx_hal_adc.c:711:13:HAL_ADC_MspInit	0	static
+stm32f1xx_hal_adc.c:725:13:HAL_ADC_MspDeInit	0	static
+stm32f1xx_hal_adc.c:923:19:HAL_ADC_PollForConversion	32	static
+stm32f1xx_hal_adc.c:1054:19:HAL_ADC_PollForEvent	24	static
+stm32f1xx_hal_adc.c:1477:10:HAL_ADC_GetValue	0	static
+stm32f1xx_hal_adc.c:1609:13:HAL_ADC_ConvCpltCallback	0	static
+stm32f1xx_hal_adc.c:2025:6:ADC_DMAConvCplt	8	static
+stm32f1xx_hal_adc.c:1623:13:HAL_ADC_ConvHalfCpltCallback	0	static
+stm32f1xx_hal_adc.c:2068:6:ADC_DMAHalfConvCplt	8	static
+stm32f1xx_hal_adc.c:1637:13:HAL_ADC_LevelOutOfWindowCallback	0	static
+stm32f1xx_hal_adc.c:1494:6:HAL_ADC_IRQHandler	8	static
+stm32f1xx_hal_adc.c:1652:13:HAL_ADC_ErrorCallback	0	static
+stm32f1xx_hal_adc.c:2082:6:ADC_DMAError	8	static
+stm32f1xx_hal_adc.c:1700:19:HAL_ADC_ConfigChannel	24	static
+stm32f1xx_hal_adc.c:1810:19:HAL_ADC_AnalogWDGConfig	12	static
+stm32f1xx_hal_adc.c:1897:10:HAL_ADC_GetState	0	static
+stm32f1xx_hal_adc.c:1908:10:HAL_ADC_GetError	0	static
+stm32f1xx_hal_adc.c:1932:19:ADC_Enable	24	static
+stm32f1xx_hal_adc.c:766:19:HAL_ADC_Start	8	static
+stm32f1xx_hal_adc.c:1103:19:HAL_ADC_Start_IT	8	static
+stm32f1xx_hal_adc.c:1271:19:HAL_ADC_Start_DMA	24	static
+stm32f1xx_hal_adc.c:1987:19:ADC_ConversionStop_Disable	16	static
+stm32f1xx_hal_adc.c:372:19:HAL_ADC_Init	24	static
+stm32f1xx_hal_adc.c:573:19:HAL_ADC_DeInit	16	static
+stm32f1xx_hal_adc.c:879:19:HAL_ADC_Stop	8	static
+stm32f1xx_hal_adc.c:1214:19:HAL_ADC_Stop_IT	8	static
+stm32f1xx_hal_adc.c:1412:19:HAL_ADC_Stop_DMA	8	static

Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.su

@@ -0,0 +1,13 @@
+stm32f1xx_hal_adc_ex.c:142:19:HAL_ADCEx_Calibration_Start	24	static
+stm32f1xx_hal_adc_ex.c:248:19:HAL_ADCEx_InjectedStart	8	static
+stm32f1xx_hal_adc_ex.c:347:19:HAL_ADCEx_InjectedStop	8	static
+stm32f1xx_hal_adc_ex.c:400:19:HAL_ADCEx_InjectedPollForConversion	32	static
+stm32f1xx_hal_adc_ex.c:518:19:HAL_ADCEx_InjectedStart_IT	8	static
+stm32f1xx_hal_adc_ex.c:617:19:HAL_ADCEx_InjectedStop_IT	8	static
+stm32f1xx_hal_adc_ex.c:686:19:HAL_ADCEx_MultiModeStart_DMA	72	static
+stm32f1xx_hal_adc_ex.c:812:19:HAL_ADCEx_MultiModeStop_DMA	64	static
+stm32f1xx_hal_adc_ex.c:901:10:HAL_ADCEx_InjectedGetValue	0	static
+stm32f1xx_hal_adc_ex.c:938:10:HAL_ADCEx_MultiModeGetValue	0	static
+stm32f1xx_hal_adc_ex.c:970:13:HAL_ADCEx_InjectedConvCpltCallback	0	static
+stm32f1xx_hal_adc_ex.c:1012:19:HAL_ADCEx_InjectedConfigChannel	32	static
+stm32f1xx_hal_adc_ex.c:1273:19:HAL_ADCEx_MultiModeConfigChannel	8	static

Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.su

@@ -0,0 +1,15 @@
+stm32f1xx_hal_cortex.c:159:6:HAL_NVIC_SetPriorityGrouping	0	static
+stm32f1xx_hal_cortex.c:181:6:HAL_NVIC_SetPriority	12	static
+stm32f1xx_hal_cortex.c:203:6:HAL_NVIC_EnableIRQ	0	static
+stm32f1xx_hal_cortex.c:219:6:HAL_NVIC_DisableIRQ	0	static
+stm32f1xx_hal_cortex.c:232:6:HAL_NVIC_SystemReset	0	static
+stm32f1xx_hal_cortex.c:245:10:HAL_SYSTICK_Config	0	static
+stm32f1xx_hal_cortex.c:360:10:HAL_NVIC_GetPriorityGrouping	0	static
+stm32f1xx_hal_cortex.c:387:6:HAL_NVIC_GetPriority	16	static
+stm32f1xx_hal_cortex.c:402:6:HAL_NVIC_SetPendingIRQ	0	static
+stm32f1xx_hal_cortex.c:420:10:HAL_NVIC_GetPendingIRQ	0	static
+stm32f1xx_hal_cortex.c:436:6:HAL_NVIC_ClearPendingIRQ	0	static
+stm32f1xx_hal_cortex.c:453:10:HAL_NVIC_GetActive	0	static
+stm32f1xx_hal_cortex.c:470:6:HAL_SYSTICK_CLKSourceConfig	0	static
+stm32f1xx_hal_cortex.c:497:13:HAL_SYSTICK_Callback	0	static
+stm32f1xx_hal_cortex.c:488:6:HAL_SYSTICK_IRQHandler	8	static

Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.su

@@ -0,0 +1,12 @@
+stm32f1xx_hal_dma.c:159:19:HAL_DMA_Init	8	static
+stm32f1xx_hal_dma.c:236:19:HAL_DMA_DeInit	8	static
+stm32f1xx_hal_dma.c:335:19:HAL_DMA_Start	20	static
+stm32f1xx_hal_dma.c:378:19:HAL_DMA_Start_IT	20	static
+stm32f1xx_hal_dma.c:432:19:HAL_DMA_Abort	0	static
+stm32f1xx_hal_dma.c:460:19:HAL_DMA_Abort_IT	8	static
+stm32f1xx_hal_dma.c:505:19:HAL_DMA_PollForTransfer	40	static
+stm32f1xx_hal_dma.c:606:6:HAL_DMA_IRQHandler	12	static
+stm32f1xx_hal_dma.c:696:19:HAL_DMA_RegisterCallback	8	static
+stm32f1xx_hal_dma.c:747:19:HAL_DMA_UnRegisterCallback	0	static
+stm32f1xx_hal_dma.c:823:22:HAL_DMA_GetState	0	static
+stm32f1xx_hal_dma.c:835:10:HAL_DMA_GetError	0	static

Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.su

@@ -0,0 +1,13 @@
+stm32f1xx_hal_flash.c:930:13:FLASH_SetErrorCode	0	static
+stm32f1xx_hal_flash.c:283:19:HAL_FLASH_Program_IT	16	static
+stm32f1xx_hal_flash.c:622:13:HAL_FLASH_EndOfOperationCallback	0	static
+stm32f1xx_hal_flash.c:640:13:HAL_FLASH_OperationErrorCallback	0	static
+stm32f1xx_hal_flash.c:348:6:HAL_FLASH_IRQHandler	16	static
+stm32f1xx_hal_flash.c:673:19:HAL_FLASH_Unlock	0	static
+stm32f1xx_hal_flash.c:711:19:HAL_FLASH_Lock	0	static
+stm32f1xx_hal_flash.c:728:19:HAL_FLASH_OB_Unlock	0	static
+stm32f1xx_hal_flash.c:748:19:HAL_FLASH_OB_Lock	0	static
+stm32f1xx_hal_flash.c:761:6:HAL_FLASH_OB_Launch	0	static
+stm32f1xx_hal_flash.c:790:10:HAL_FLASH_GetError	0	static
+stm32f1xx_hal_flash.c:842:19:FLASH_WaitForLastOperation	24	static
+stm32f1xx_hal_flash.c:184:19:HAL_FLASH_Program	40	static

Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.su

@@ -0,0 +1,9 @@
+stm32f1xx_hal_flash_ex.c:611:13:FLASH_MassErase.isra.0	0	static
+stm32f1xx_hal_flash_ex.c:902:26:FLASH_OB_RDP_LevelConfig	16	static
+stm32f1xx_hal_flash_ex.c:413:19:HAL_FLASHEx_OBErase	16	static
+stm32f1xx_hal_flash_ex.c:462:19:HAL_FLASHEx_OBProgram	24	static
+stm32f1xx_hal_flash_ex.c:543:6:HAL_FLASHEx_OBGetConfig	0	static
+stm32f1xx_hal_flash_ex.c:565:10:HAL_FLASHEx_OBGetUserData	0	static
+stm32f1xx_hal_flash_ex.c:1105:6:FLASH_PageErase	0	static
+stm32f1xx_hal_flash_ex.c:175:19:HAL_FLASHEx_Erase	24	static
+stm32f1xx_hal_flash_ex.c:335:19:HAL_FLASHEx_Erase_IT	16	static

Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.su

@@ -0,0 +1,8 @@
+stm32f1xx_hal_gpio.c:194:6:HAL_GPIO_Init	48	static
+stm32f1xx_hal_gpio.c:365:6:HAL_GPIO_DeInit	36	static
+stm32f1xx_hal_gpio.c:446:15:HAL_GPIO_ReadPin	0	static
+stm32f1xx_hal_gpio.c:480:6:HAL_GPIO_WritePin	0	static
+stm32f1xx_hal_gpio.c:502:6:HAL_GPIO_TogglePin	0	static
+stm32f1xx_hal_gpio.c:520:19:HAL_GPIO_LockPin	8	static
+stm32f1xx_hal_gpio.c:569:13:HAL_GPIO_EXTI_Callback	0	static
+stm32f1xx_hal_gpio.c:554:6:HAL_GPIO_EXTI_IRQHandler	8	static

Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.su

@@ -0,0 +1,3 @@
+stm32f1xx_hal_gpio_ex.c:97:6:HAL_GPIOEx_ConfigEventout	0	static
+stm32f1xx_hal_gpio_ex.c:111:6:HAL_GPIOEx_EnableEventout	0	static
+stm32f1xx_hal_gpio_ex.c:120:6:HAL_GPIOEx_DisableEventout	0	static

Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.su

@@ -0,0 +1,18 @@
+stm32f1xx_hal_pwr.c:133:13:PWR_OverloadWfe	0	static
+stm32f1xx_hal_pwr.c:172:6:HAL_PWR_DeInit	0	static
+stm32f1xx_hal_pwr.c:185:6:HAL_PWR_EnableBkUpAccess	0	static
+stm32f1xx_hal_pwr.c:198:6:HAL_PWR_DisableBkUpAccess	0	static
+stm32f1xx_hal_pwr.c:332:6:HAL_PWR_ConfigPVD	0	static
+stm32f1xx_hal_pwr.c:375:6:HAL_PWR_EnablePVD	0	static
+stm32f1xx_hal_pwr.c:385:6:HAL_PWR_DisablePVD	0	static
+stm32f1xx_hal_pwr.c:398:6:HAL_PWR_EnableWakeUpPin	0	static
+stm32f1xx_hal_pwr.c:413:6:HAL_PWR_DisableWakeUpPin	0	static
+stm32f1xx_hal_pwr.c:433:6:HAL_PWR_EnterSLEEPMode	0	static
+stm32f1xx_hal_pwr.c:479:6:HAL_PWR_EnterSTOPMode	8	static
+stm32f1xx_hal_pwr.c:519:6:HAL_PWR_EnterSTANDBYMode	0	static
+stm32f1xx_hal_pwr.c:544:6:HAL_PWR_EnableSleepOnExit	0	static
+stm32f1xx_hal_pwr.c:557:6:HAL_PWR_DisableSleepOnExit	0	static
+stm32f1xx_hal_pwr.c:570:6:HAL_PWR_EnableSEVOnPend	0	static
+stm32f1xx_hal_pwr.c:583:6:HAL_PWR_DisableSEVOnPend	0	static
+stm32f1xx_hal_pwr.c:613:13:HAL_PWR_PVDCallback	0	static
+stm32f1xx_hal_pwr.c:596:6:HAL_PWR_PVD_IRQHandler	8	static

Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.su

@@ -0,0 +1,14 @@
+stm32f1xx_hal_rcc.c:218:19:HAL_RCC_DeInit	16	static
+stm32f1xx_hal_rcc.c:363:19:HAL_RCC_OscConfig	32	static
+stm32f1xx_hal_rcc.c:1015:6:HAL_RCC_MCOConfig	40	static
+stm32f1xx_hal_rcc.c:1052:6:HAL_RCC_EnableCSS	0	static
+stm32f1xx_hal_rcc.c:1061:6:HAL_RCC_DisableCSS	0	static
+stm32f1xx_hal_rcc.c:1095:10:HAL_RCC_GetSysClockFreq	40	static
+stm32f1xx_hal_rcc.c:809:19:HAL_RCC_ClockConfig	24	static
+stm32f1xx_hal_rcc.c:1189:10:HAL_RCC_GetHCLKFreq	0	static
+stm32f1xx_hal_rcc.c:1200:10:HAL_RCC_GetPCLK1Freq	0	static
+stm32f1xx_hal_rcc.c:1212:10:HAL_RCC_GetPCLK2Freq	0	static
+stm32f1xx_hal_rcc.c:1225:6:HAL_RCC_GetOscConfig	0	static
+stm32f1xx_hal_rcc.c:1325:6:HAL_RCC_GetClockConfig	0	static
+stm32f1xx_hal_rcc.c:1392:13:HAL_RCC_CSSCallback	0	static
+stm32f1xx_hal_rcc.c:1360:6:HAL_RCC_NMI_IRQHandler	8	static

Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.su

@@ -0,0 +1,3 @@
+stm32f1xx_hal_rcc_ex.c:116:19:HAL_RCCEx_PeriphCLKConfig	32	static
+stm32f1xx_hal_rcc_ex.c:310:6:HAL_RCCEx_GetPeriphCLKConfig	0	static
+stm32f1xx_hal_rcc_ex.c:403:10:HAL_RCCEx_GetPeriphCLKFreq	40	static

Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.su

@@ -0,0 +1,52 @@
+stm32f1xx_hal_uart.c:2188:13:UART_EndRxTransfer	0	static
+stm32f1xx_hal_uart.c:2466:13:UART_SetConfig	32	static
+stm32f1xx_hal_uart.c:2141:26:UART_WaitOnFlagUntilTimeout.constprop	24	static
+stm32f1xx_hal_uart.c:549:13:HAL_UART_MspInit	0	static
+stm32f1xx_hal_uart.c:259:19:HAL_UART_Init	8	static
+stm32f1xx_hal_uart.c:324:19:HAL_HalfDuplex_Init	8	static
+stm32f1xx_hal_uart.c:385:19:HAL_LIN_Init	16	static
+stm32f1xx_hal_uart.c:453:19:HAL_MultiProcessor_Init	16	static
+stm32f1xx_hal_uart.c:564:13:HAL_UART_MspDeInit	0	static
+stm32f1xx_hal_uart.c:517:19:HAL_UART_DeInit	8	static
+stm32f1xx_hal_uart.c:643:19:HAL_UART_Transmit	24	static
+stm32f1xx_hal_uart.c:725:19:HAL_UART_Receive	24	static
+stm32f1xx_hal_uart.c:813:19:HAL_UART_Transmit_IT	0	static
+stm32f1xx_hal_uart.c:854:19:HAL_UART_Receive_IT	0	static
+stm32f1xx_hal_uart.c:902:19:HAL_UART_Transmit_DMA	16	static
+stm32f1xx_hal_uart.c:967:19:HAL_UART_Receive_DMA	24	static
+stm32f1xx_hal_uart.c:1034:19:HAL_UART_DMAPause	0	static
+stm32f1xx_hal_uart.c:1071:19:HAL_UART_DMAResume	8	static
+stm32f1xx_hal_uart.c:1107:19:HAL_UART_DMAStop	8	static
+stm32f1xx_hal_uart.c:1159:19:HAL_UART_Abort	8	static
+stm32f1xx_hal_uart.c:1223:19:HAL_UART_AbortTransmit	8	static
+stm32f1xx_hal_uart.c:1265:19:HAL_UART_AbortReceive	8	static
+stm32f1xx_hal_uart.c:1682:14:HAL_UART_TxCpltCallback	0	static
+stm32f1xx_hal_uart.c:2026:13:UART_DMATransmitCplt	8	static
+stm32f1xx_hal_uart.c:1697:14:HAL_UART_TxHalfCpltCallback	0	static
+stm32f1xx_hal_uart.c:2055:13:UART_DMATxHalfCplt	8	static
+stm32f1xx_hal_uart.c:1712:13:HAL_UART_RxCpltCallback	0	static
+stm32f1xx_hal_uart.c:2067:13:UART_DMAReceiveCplt	8	static
+stm32f1xx_hal_uart.c:2402:26:UART_Receive_IT	8	static
+stm32f1xx_hal_uart.c:1727:13:HAL_UART_RxHalfCpltCallback	0	static
+stm32f1xx_hal_uart.c:2095:13:UART_DMARxHalfCplt	8	static
+stm32f1xx_hal_uart.c:1742:14:HAL_UART_ErrorCallback	0	static
+stm32f1xx_hal_uart.c:2106:13:UART_DMAError	8	static
+stm32f1xx_hal_uart.c:1555:6:HAL_UART_IRQHandler	16	static
+stm32f1xx_hal_uart.c:2204:13:UART_DMAAbortOnError	8	static
+stm32f1xx_hal_uart.c:1756:13:HAL_UART_AbortCpltCallback	0	static
+stm32f1xx_hal_uart.c:1310:19:HAL_UART_Abort_IT	8	static
+stm32f1xx_hal_uart.c:2259:13:UART_DMARxAbortCallback	8	static
+stm32f1xx_hal_uart.c:2221:13:UART_DMATxAbortCallback	8	static
+stm32f1xx_hal_uart.c:1770:13:HAL_UART_AbortTransmitCpltCallback	0	static
+stm32f1xx_hal_uart.c:1432:19:HAL_UART_AbortTransmit_IT	8	static
+stm32f1xx_hal_uart.c:2297:13:UART_DMATxOnlyAbortCallback	8	static
+stm32f1xx_hal_uart.c:1785:13:HAL_UART_AbortReceiveCpltCallback	0	static
+stm32f1xx_hal_uart.c:1497:19:HAL_UART_AbortReceive_IT	8	static
+stm32f1xx_hal_uart.c:2318:13:UART_DMARxOnlyAbortCallback	8	static
+stm32f1xx_hal_uart.c:1824:19:HAL_LIN_SendBreak	0	static
+stm32f1xx_hal_uart.c:1851:19:HAL_MultiProcessor_EnterMuteMode	0	static
+stm32f1xx_hal_uart.c:1878:19:HAL_MultiProcessor_ExitMuteMode	0	static
+stm32f1xx_hal_uart.c:1905:19:HAL_HalfDuplex_EnableTransmitter	0	static
+stm32f1xx_hal_uart.c:1940:19:HAL_HalfDuplex_EnableReceiver	0	static
+stm32f1xx_hal_uart.c:1997:23:HAL_UART_GetState	0	static
+stm32f1xx_hal_uart.c:2012:10:HAL_UART_GetError	0	static

Debug/STM32F103_ATTEN_PLL_Zig.hex

@@ -0,0 +1,429 @@
+:020000040800F2
+:100000000000012075190008FD180008FF180008FD
+:100010000119000803190008051900080000000074
+:1000200000000000000000000000000007190008A8
+:1000300009190008000000000B1900080D1900083C
+:10004000BD190008BD190008BD190008BD19000838
+:10005000BD190008BD190008BD190008BD19000828
+:10006000BD190008BD190008BD19000811190008C4
+:10007000BD190008BD190008BD190008BD19000808
+:10008000BD190008BD190008BD190008BD190008F8
+:10009000BD190008BD190008BD190008BD190008E8
+:1000A000BD190008BD190008BD190008BD190008D8
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Debug/Src/PE43711.su

@@ -0,0 +1,2 @@
+PE43711.c:32:6:PE43711_PinInit	0	static
+PE43711.c:78:6:PE43711_atten_ctrl	16	static

Debug/Src/main.su

@@ -0,0 +1,3 @@
+main.c:124:6:SystemClock_Config	96	static
+main.c:74:5:main	56	static
+main.c:415:6:Error_Handler	0	static

Debug/Src/stm32f1xx_hal_msp.su

@@ -0,0 +1,5 @@
+stm32f1xx_hal_msp.c:65:6:HAL_MspInit	8	static
+stm32f1xx_hal_msp.c:91:6:HAL_ADC_MspInit	48	static
+stm32f1xx_hal_msp.c:164:6:HAL_ADC_MspDeInit	8	static
+stm32f1xx_hal_msp.c:212:6:HAL_UART_MspInit	32	static
+stm32f1xx_hal_msp.c:251:6:HAL_UART_MspDeInit	8	static

Debug/Src/stm32f1xx_it.su

@@ -0,0 +1,11 @@
+stm32f1xx_it.c:71:6:NMI_Handler	0	static
+stm32f1xx_it.c:84:6:HardFault_Handler	0	static
+stm32f1xx_it.c:99:6:MemManage_Handler	0	static
+stm32f1xx_it.c:114:6:BusFault_Handler	0	static
+stm32f1xx_it.c:129:6:UsageFault_Handler	0	static
+stm32f1xx_it.c:144:6:SVC_Handler	0	static
+stm32f1xx_it.c:157:6:DebugMon_Handler	0	static
+stm32f1xx_it.c:170:6:PendSV_Handler	0	static
+stm32f1xx_it.c:183:6:SysTick_Handler	0	static
+stm32f1xx_it.c:204:6:DMA1_Channel1_IRQHandler	0	static
+stm32f1xx_it.c:218:6:USART1_IRQHandler	0	static

Debug/Src/syscalls.su

@@ -0,0 +1,19 @@
+syscalls.c:70:6:initialise_monitor_handles	0	static
+syscalls.c:74:5:_getpid	0	static
+syscalls.c:79:5:_kill	8	static
+syscalls.c:85:6:_exit	8	static
+syscalls.c:91:27:_read	16	static
+syscalls.c:103:27:_write	16	static
+syscalls.c:114:9:_sbrk	8	static
+syscalls.c:137:5:_close	0	static
+syscalls.c:143:5:_fstat	0	static
+syscalls.c:149:5:_isatty	0	static
+syscalls.c:154:5:_lseek	0	static
+syscalls.c:159:5:_open	0	static
+syscalls.c:165:5:_wait	8	static
+syscalls.c:171:5:_unlink	8	static
+syscalls.c:177:5:_times	0	static
+syscalls.c:182:5:_stat	0	static
+syscalls.c:188:5:_link	8	static
+syscalls.c:194:5:_fork	8	static
+syscalls.c:200:5:_execve	8	static

Debug/Src/system_stm32f1xx.su

@@ -0,0 +1,2 @@
+system_stm32f1xx.c:175:6:SystemInit	0	static
+system_stm32f1xx.c:265:6:SystemCoreClockUpdate	0	static

Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xg.h

@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    stm32f103xg.h
+  * @file    stm32f103xe.h
   * @author  MCD Application Team
   * @version V4.2.0
   * @date    31-March-2017
@@ -48,12 +48,12 @@
   * @{
   */
 
-/** @addtogroup stm32f103xg
+/** @addtogroup stm32f103xe
   * @{
   */
     
-#ifndef __STM32F103xG_H
-#define __STM32F103xG_H
+#ifndef __STM32F103xE_H
+#define __STM32F103xE_H
 
 #ifdef __cplusplus
  extern "C" {
@@ -66,7 +66,7 @@
   * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 
  */
 #define __CM3_REV                  0x0200U  /*!< Core Revision r2p0                           */
- #define __MPU_PRESENT             1U       /*!< STM32 XL-density devices provide an MPU      */
+ #define __MPU_PRESENT             0U       /*!< Other STM32 devices does not provide an MPU  */
 #define __NVIC_PRIO_BITS           4U       /*!< STM32 uses 4 Bits for the Priority Levels    */
 #define __Vendor_SysTickConfig     0U       /*!< Set to 1 if different SysTick Config is used */
 
@@ -122,9 +122,9 @@ typedef enum
   CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
   CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
-  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break Interrupt and TIM9 global Interrupt       */
-  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global Interrupt     */
-  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                 */
+  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                */
+  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt               */
   TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
   TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
   TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
@@ -141,9 +141,9 @@ typedef enum
   EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
   RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
   USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
-  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global Interrupt      */
-  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global Interrupt     */
-  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+  TIM8_BRK_IRQn               = 43,     /*!< TIM8 Break Interrupt                                 */
+  TIM8_UP_IRQn                = 44,     /*!< TIM8 Update Interrupt                                */
+  TIM8_TRG_COM_IRQn           = 45,     /*!< TIM8 Trigger and Commutation Interrupt               */
   TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                       */
   ADC3_IRQn                   = 47,     /*!< ADC3 global Interrupt                                */
   FSMC_IRQn                   = 48,     /*!< FSMC global Interrupt                                */
@@ -421,12 +421,6 @@ typedef struct
   __IO uint32_t RESERVED;
   __IO uint32_t OBR;
   __IO uint32_t WRPR;
-  uint32_t RESERVED1[8]; 
-  __IO uint32_t KEYR2;
-  uint32_t RESERVED2;   
-  __IO uint32_t SR2;
-  __IO uint32_t CR2;
-  __IO uint32_t AR2; 
 } FLASH_TypeDef;
 
 /** 
@@ -748,7 +742,6 @@ typedef struct
 
 #define FLASH_BASE            0x08000000U /*!< FLASH base address in the alias region */
 #define FLASH_BANK1_END       0x0807FFFFU /*!< FLASH END address of bank1 */
-#define FLASH_BANK2_END       0x080FFFFFU /*!< FLASH END address of bank2 */
 #define SRAM_BASE             0x20000000U /*!< SRAM base address in the alias region */
 #define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region */
 
@@ -769,9 +762,6 @@ typedef struct
 #define TIM5_BASE             (APB1PERIPH_BASE + 0x00000C00U)
 #define TIM6_BASE             (APB1PERIPH_BASE + 0x00001000U)
 #define TIM7_BASE             (APB1PERIPH_BASE + 0x00001400U)
-#define TIM12_BASE            (APB1PERIPH_BASE + 0x00001800U)
-#define TIM13_BASE            (APB1PERIPH_BASE + 0x00001C00U)
-#define TIM14_BASE            (APB1PERIPH_BASE + 0x00002000U)
 #define RTC_BASE              (APB1PERIPH_BASE + 0x00002800U)
 #define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00U)
 #define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000U)
@@ -803,9 +793,6 @@ typedef struct
 #define TIM8_BASE             (APB2PERIPH_BASE + 0x00003400U)
 #define USART1_BASE           (APB2PERIPH_BASE + 0x00003800U)
 #define ADC3_BASE             (APB2PERIPH_BASE + 0x00003C00U)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x00004C00U)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x00005000U)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x00005400U)
 
 #define SDIO_BASE             (PERIPH_BASE + 0x00018000U)
 
@@ -868,9 +855,6 @@ typedef struct
 #define TIM5                ((TIM_TypeDef *)TIM5_BASE)
 #define TIM6                ((TIM_TypeDef *)TIM6_BASE)
 #define TIM7                ((TIM_TypeDef *)TIM7_BASE)
-#define TIM12               ((TIM_TypeDef *)TIM12_BASE)
-#define TIM13               ((TIM_TypeDef *)TIM13_BASE)
-#define TIM14               ((TIM_TypeDef *)TIM14_BASE)
 #define RTC                 ((RTC_TypeDef *)RTC_BASE)
 #define WWDG                ((WWDG_TypeDef *)WWDG_BASE)
 #define IWDG                ((IWDG_TypeDef *)IWDG_BASE)
@@ -905,9 +889,6 @@ typedef struct
 #define SPI1                ((SPI_TypeDef *)SPI1_BASE)
 #define TIM8                ((TIM_TypeDef *)TIM8_BASE)
 #define USART1              ((USART_TypeDef *)USART1_BASE)
-#define TIM9                ((TIM_TypeDef *)TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *)TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *)TIM11_BASE)
 #define SDIO                ((SDIO_TypeDef *)SDIO_BASE)
 #define DMA1                ((DMA_TypeDef *)DMA1_BASE)
 #define DMA2                ((DMA_TypeDef *)DMA2_BASE)
@@ -1617,15 +1598,6 @@ typedef struct
 #define RCC_APB2RSTR_ADC3RST                 RCC_APB2RSTR_ADC3RST_Msk          /*!< ADC3 interface reset */
 
 
-#define RCC_APB2RSTR_TIM9RST_Pos             (19U)                             
-#define RCC_APB2RSTR_TIM9RST_Msk             (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00080000 */
-#define RCC_APB2RSTR_TIM9RST                 RCC_APB2RSTR_TIM9RST_Msk          /*!< TIM9 Timer reset */
-#define RCC_APB2RSTR_TIM10RST_Pos            (20U)                             
-#define RCC_APB2RSTR_TIM10RST_Msk            (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00100000 */
-#define RCC_APB2RSTR_TIM10RST                RCC_APB2RSTR_TIM10RST_Msk         /*!< TIM10 Timer reset */
-#define RCC_APB2RSTR_TIM11RST_Pos            (21U)                             
-#define RCC_APB2RSTR_TIM11RST_Msk            (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00200000 */
-#define RCC_APB2RSTR_TIM11RST                RCC_APB2RSTR_TIM11RST_Msk         /*!< TIM11 Timer reset */
 
 /*****************  Bit definition for RCC_APB1RSTR register  *****************/
 #define RCC_APB1RSTR_TIM2RST_Pos             (0U)                              
@@ -1694,15 +1666,6 @@ typedef struct
 
 
 
-#define RCC_APB1RSTR_TIM12RST_Pos            (6U)                              
-#define RCC_APB1RSTR_TIM12RST_Msk            (0x1U << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
-#define RCC_APB1RSTR_TIM12RST                RCC_APB1RSTR_TIM12RST_Msk         /*!< TIM12 Timer reset */
-#define RCC_APB1RSTR_TIM13RST_Pos            (7U)                              
-#define RCC_APB1RSTR_TIM13RST_Msk            (0x1U << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
-#define RCC_APB1RSTR_TIM13RST                RCC_APB1RSTR_TIM13RST_Msk         /*!< TIM13 Timer reset */
-#define RCC_APB1RSTR_TIM14RST_Pos            (8U)                              
-#define RCC_APB1RSTR_TIM14RST_Msk            (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
-#define RCC_APB1RSTR_TIM14RST                RCC_APB1RSTR_TIM14RST_Msk         /*!< TIM14 Timer reset */
 #define RCC_APB1RSTR_DACRST_Pos              (29U)                             
 #define RCC_APB1RSTR_DACRST_Msk              (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
 #define RCC_APB1RSTR_DACRST                  RCC_APB1RSTR_DACRST_Msk           /*!< DAC interface reset */
@@ -1786,15 +1749,6 @@ typedef struct
 #define RCC_APB2ENR_ADC3EN                   RCC_APB2ENR_ADC3EN_Msk            /*!< DMA1 clock enable */
 
 
-#define RCC_APB2ENR_TIM9EN_Pos               (19U)                             
-#define RCC_APB2ENR_TIM9EN_Msk               (0x1U << RCC_APB2ENR_TIM9EN_Pos)  /*!< 0x00080000 */
-#define RCC_APB2ENR_TIM9EN                   RCC_APB2ENR_TIM9EN_Msk            /*!< TIM9 Timer clock enable  */
-#define RCC_APB2ENR_TIM10EN_Pos              (20U)                             
-#define RCC_APB2ENR_TIM10EN_Msk              (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00100000 */
-#define RCC_APB2ENR_TIM10EN                  RCC_APB2ENR_TIM10EN_Msk           /*!< TIM10 Timer clock enable  */
-#define RCC_APB2ENR_TIM11EN_Pos              (21U)                             
-#define RCC_APB2ENR_TIM11EN_Msk              (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00200000 */
-#define RCC_APB2ENR_TIM11EN                  RCC_APB2ENR_TIM11EN_Msk           /*!< TIM11 Timer clock enable */
 
 /*****************  Bit definition for RCC_APB1ENR register  ******************/
 #define RCC_APB1ENR_TIM2EN_Pos               (0U)                              
@@ -1863,15 +1817,6 @@ typedef struct
 
 
 
-#define RCC_APB1ENR_TIM12EN_Pos              (6U)                              
-#define RCC_APB1ENR_TIM12EN_Msk              (0x1U << RCC_APB1ENR_TIM12EN_Pos) /*!< 0x00000040 */
-#define RCC_APB1ENR_TIM12EN                  RCC_APB1ENR_TIM12EN_Msk           /*!< TIM12 Timer clock enable  */
-#define RCC_APB1ENR_TIM13EN_Pos              (7U)                              
-#define RCC_APB1ENR_TIM13EN_Msk              (0x1U << RCC_APB1ENR_TIM13EN_Pos) /*!< 0x00000080 */
-#define RCC_APB1ENR_TIM13EN                  RCC_APB1ENR_TIM13EN_Msk           /*!< TIM13 Timer clock enable  */
-#define RCC_APB1ENR_TIM14EN_Pos              (8U)                              
-#define RCC_APB1ENR_TIM14EN_Msk              (0x1U << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */
-#define RCC_APB1ENR_TIM14EN                  RCC_APB1ENR_TIM14EN_Msk           /*!< TIM14 Timer clock enable */
 #define RCC_APB1ENR_DACEN_Pos                (29U)                             
 #define RCC_APB1ENR_DACEN_Msk                (0x1U << RCC_APB1ENR_DACEN_Pos)   /*!< 0x20000000 */
 #define RCC_APB1ENR_DACEN                    RCC_APB1ENR_DACEN_Msk             /*!< DAC interface clock enable */
@@ -3070,21 +3015,6 @@ typedef struct
 /******************  Bit definition for AFIO_MAPR2 register  ******************/
 
 
-#define AFIO_MAPR2_TIM9_REMAP_Pos            (5U)                              
-#define AFIO_MAPR2_TIM9_REMAP_Msk            (0x1U << AFIO_MAPR2_TIM9_REMAP_Pos) /*!< 0x00000020 */
-#define AFIO_MAPR2_TIM9_REMAP                AFIO_MAPR2_TIM9_REMAP_Msk         /*!< TIM9 remapping */
-#define AFIO_MAPR2_TIM10_REMAP_Pos           (6U)                              
-#define AFIO_MAPR2_TIM10_REMAP_Msk           (0x1U << AFIO_MAPR2_TIM10_REMAP_Pos) /*!< 0x00000040 */
-#define AFIO_MAPR2_TIM10_REMAP               AFIO_MAPR2_TIM10_REMAP_Msk        /*!< TIM10 remapping */
-#define AFIO_MAPR2_TIM11_REMAP_Pos           (7U)                              
-#define AFIO_MAPR2_TIM11_REMAP_Msk           (0x1U << AFIO_MAPR2_TIM11_REMAP_Pos) /*!< 0x00000080 */
-#define AFIO_MAPR2_TIM11_REMAP               AFIO_MAPR2_TIM11_REMAP_Msk        /*!< TIM11 remapping */
-#define AFIO_MAPR2_TIM13_REMAP_Pos           (8U)                              
-#define AFIO_MAPR2_TIM13_REMAP_Msk           (0x1U << AFIO_MAPR2_TIM13_REMAP_Pos) /*!< 0x00000100 */
-#define AFIO_MAPR2_TIM13_REMAP               AFIO_MAPR2_TIM13_REMAP_Msk        /*!< TIM13 remapping */
-#define AFIO_MAPR2_TIM14_REMAP_Pos           (9U)                              
-#define AFIO_MAPR2_TIM14_REMAP_Msk           (0x1U << AFIO_MAPR2_TIM14_REMAP_Pos) /*!< 0x00000200 */
-#define AFIO_MAPR2_TIM14_REMAP               AFIO_MAPR2_TIM14_REMAP_Msk        /*!< TIM14 remapping */
 #define AFIO_MAPR2_FSMC_NADV_REMAP_Pos       (10U)                             
 #define AFIO_MAPR2_FSMC_NADV_REMAP_Msk       (0x1U << AFIO_MAPR2_FSMC_NADV_REMAP_Pos) /*!< 0x00000400 */
 #define AFIO_MAPR2_FSMC_NADV_REMAP           AFIO_MAPR2_FSMC_NADV_REMAP_Msk    /*!< FSMC NADV remapping */
@@ -11166,24 +11096,6 @@ typedef struct
 #define DBGMCU_CR_DBG_TIM7_STOP_Pos         (20U)                              
 #define DBGMCU_CR_DBG_TIM7_STOP_Msk         (0x1U << DBGMCU_CR_DBG_TIM7_STOP_Pos) /*!< 0x00100000 */
 #define DBGMCU_CR_DBG_TIM7_STOP             DBGMCU_CR_DBG_TIM7_STOP_Msk        /*!< TIM7 counter stopped when core is halted */
-#define DBGMCU_CR_DBG_TIM12_STOP_Pos        (25U)                              
-#define DBGMCU_CR_DBG_TIM12_STOP_Msk        (0x1U << DBGMCU_CR_DBG_TIM12_STOP_Pos) /*!< 0x02000000 */
-#define DBGMCU_CR_DBG_TIM12_STOP            DBGMCU_CR_DBG_TIM12_STOP_Msk       /*!< Debug TIM12 stopped when Core is halted */
-#define DBGMCU_CR_DBG_TIM13_STOP_Pos        (26U)                              
-#define DBGMCU_CR_DBG_TIM13_STOP_Msk        (0x1U << DBGMCU_CR_DBG_TIM13_STOP_Pos) /*!< 0x04000000 */
-#define DBGMCU_CR_DBG_TIM13_STOP            DBGMCU_CR_DBG_TIM13_STOP_Msk       /*!< Debug TIM13 stopped when Core is halted */
-#define DBGMCU_CR_DBG_TIM14_STOP_Pos        (27U)                              
-#define DBGMCU_CR_DBG_TIM14_STOP_Msk        (0x1U << DBGMCU_CR_DBG_TIM14_STOP_Pos) /*!< 0x08000000 */
-#define DBGMCU_CR_DBG_TIM14_STOP            DBGMCU_CR_DBG_TIM14_STOP_Msk       /*!< Debug TIM14 stopped when Core is halted */
-#define DBGMCU_CR_DBG_TIM9_STOP_Pos         (28U)                              
-#define DBGMCU_CR_DBG_TIM9_STOP_Msk         (0x1U << DBGMCU_CR_DBG_TIM9_STOP_Pos) /*!< 0x10000000 */
-#define DBGMCU_CR_DBG_TIM9_STOP             DBGMCU_CR_DBG_TIM9_STOP_Msk        /*!< Debug TIM9 stopped when Core is halted */
-#define DBGMCU_CR_DBG_TIM10_STOP_Pos        (29U)                              
-#define DBGMCU_CR_DBG_TIM10_STOP_Msk        (0x1U << DBGMCU_CR_DBG_TIM10_STOP_Pos) /*!< 0x20000000 */
-#define DBGMCU_CR_DBG_TIM10_STOP            DBGMCU_CR_DBG_TIM10_STOP_Msk       /*!< Debug TIM10 stopped when Core is halted */
-#define DBGMCU_CR_DBG_TIM11_STOP_Pos        (30U)                              
-#define DBGMCU_CR_DBG_TIM11_STOP_Msk        (0x1U << DBGMCU_CR_DBG_TIM11_STOP_Pos) /*!< 0x40000000 */
-#define DBGMCU_CR_DBG_TIM11_STOP            DBGMCU_CR_DBG_TIM11_STOP_Msk       /*!< Debug TIM11 stopped when Core is halted */
 
 /******************************************************************************/
 /*                                                                            */
@@ -11299,11 +11211,8 @@ typedef struct
 #define FLASH_OBR_nRST_STDBY_Pos            (4U)                               
 #define FLASH_OBR_nRST_STDBY_Msk            (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000010 */
 #define FLASH_OBR_nRST_STDBY                FLASH_OBR_nRST_STDBY_Msk           /*!< nRST_STDBY */
-#define FLASH_OBR_BFB2_Pos                  (5U)                               
-#define FLASH_OBR_BFB2_Msk                  (0x1U << FLASH_OBR_BFB2_Pos)       /*!< 0x00000020 */
-#define FLASH_OBR_BFB2                      FLASH_OBR_BFB2_Msk                 /*!< BFB2 */
 #define FLASH_OBR_USER_Pos                  (2U)                               
-#define FLASH_OBR_USER_Msk                  (0xFU << FLASH_OBR_USER_Pos)       /*!< 0x0000003C */
+#define FLASH_OBR_USER_Msk                  (0x7U << FLASH_OBR_USER_Pos)       /*!< 0x0000001C */
 #define FLASH_OBR_USER                      FLASH_OBR_USER_Msk                 /*!< User Option Bytes */
 #define FLASH_OBR_DATA0_Pos                 (10U)                              
 #define FLASH_OBR_DATA0_Msk                 (0xFFU << FLASH_OBR_DATA0_Pos)     /*!< 0x0003FC00 */
@@ -11317,53 +11226,6 @@ typedef struct
 #define FLASH_WRPR_WRP_Msk                  (0xFFFFFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */
 #define FLASH_WRPR_WRP                      FLASH_WRPR_WRP_Msk                 /*!< Write Protect */
 
-/*****************  Bit definition for FLASH_OPTKEYR2 register ****************/
-#define FLASH_OPTKEYR_OPTKEYR2_Pos          (0U)                               
-#define FLASH_OPTKEYR_OPTKEYR2_Msk          (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR2_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_OPTKEYR_OPTKEYR2              FLASH_OPTKEYR_OPTKEYR2_Msk         /*!< Option Byte Key */
-
-/******************  Bit definition for FLASH_SR2 register ********************/
-#define FLASH_SR2_BSY_Pos                   (0U)                               
-#define FLASH_SR2_BSY_Msk                   (0x1U << FLASH_SR2_BSY_Pos)        /*!< 0x00000001 */
-#define FLASH_SR2_BSY                       FLASH_SR2_BSY_Msk                  /*!< Busy */
-#define FLASH_SR2_PGERR_Pos                 (2U)                               
-#define FLASH_SR2_PGERR_Msk                 (0x1U << FLASH_SR2_PGERR_Pos)      /*!< 0x00000004 */
-#define FLASH_SR2_PGERR                     FLASH_SR2_PGERR_Msk                /*!< Programming Error */
-#define FLASH_SR2_WRPRTERR_Pos              (4U)                               
-#define FLASH_SR2_WRPRTERR_Msk              (0x1U << FLASH_SR2_WRPRTERR_Pos)   /*!< 0x00000010 */
-#define FLASH_SR2_WRPRTERR                  FLASH_SR2_WRPRTERR_Msk             /*!< Write Protection Error */
-#define FLASH_SR2_EOP_Pos                   (5U)                               
-#define FLASH_SR2_EOP_Msk                   (0x1U << FLASH_SR2_EOP_Pos)        /*!< 0x00000020 */
-#define FLASH_SR2_EOP                       FLASH_SR2_EOP_Msk                  /*!< End of operation */
-
-/*******************  Bit definition for FLASH_CR2 register *******************/
-#define FLASH_CR2_PG_Pos                    (0U)                               
-#define FLASH_CR2_PG_Msk                    (0x1U << FLASH_CR2_PG_Pos)         /*!< 0x00000001 */
-#define FLASH_CR2_PG                        FLASH_CR2_PG_Msk                   /*!< Programming */
-#define FLASH_CR2_PER_Pos                   (1U)                               
-#define FLASH_CR2_PER_Msk                   (0x1U << FLASH_CR2_PER_Pos)        /*!< 0x00000002 */
-#define FLASH_CR2_PER                       FLASH_CR2_PER_Msk                  /*!< Page Erase */
-#define FLASH_CR2_MER_Pos                   (2U)                               
-#define FLASH_CR2_MER_Msk                   (0x1U << FLASH_CR2_MER_Pos)        /*!< 0x00000004 */
-#define FLASH_CR2_MER                       FLASH_CR2_MER_Msk                  /*!< Mass Erase */
-#define FLASH_CR2_STRT_Pos                  (6U)                               
-#define FLASH_CR2_STRT_Msk                  (0x1U << FLASH_CR2_STRT_Pos)       /*!< 0x00000040 */
-#define FLASH_CR2_STRT                      FLASH_CR2_STRT_Msk                 /*!< Start */
-#define FLASH_CR2_LOCK_Pos                  (7U)                               
-#define FLASH_CR2_LOCK_Msk                  (0x1U << FLASH_CR2_LOCK_Pos)       /*!< 0x00000080 */
-#define FLASH_CR2_LOCK                      FLASH_CR2_LOCK_Msk                 /*!< Lock */
-#define FLASH_CR2_ERRIE_Pos                 (10U)                              
-#define FLASH_CR2_ERRIE_Msk                 (0x1U << FLASH_CR2_ERRIE_Pos)      /*!< 0x00000400 */
-#define FLASH_CR2_ERRIE                     FLASH_CR2_ERRIE_Msk                /*!< Error Interrupt Enable */
-#define FLASH_CR2_EOPIE_Pos                 (12U)                              
-#define FLASH_CR2_EOPIE_Msk                 (0x1U << FLASH_CR2_EOPIE_Pos)      /*!< 0x00001000 */
-#define FLASH_CR2_EOPIE                     FLASH_CR2_EOPIE_Msk                /*!< End of operation interrupt enable */
-
-/*******************  Bit definition for FLASH_AR2 register *******************/
-#define FLASH_AR_FAR2_Pos                   (0U)                               
-#define FLASH_AR_FAR2_Msk                   (0xFFFFFFFFU << FLASH_AR_FAR2_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_AR_FAR2                       FLASH_AR_FAR2_Msk                  /*!< Flash Address */
-
 /*----------------------------------------------------------------------------*/
 
 /******************  Bit definition for FLASH_RDP register  *******************/
@@ -11526,13 +11388,7 @@ typedef struct
    ((INSTANCE) == TIM4)    || \
    ((INSTANCE) == TIM5)    || \
    ((INSTANCE) == TIM6)    || \
-   ((INSTANCE) == TIM7)    || \
-   ((INSTANCE) == TIM9)    || \
-   ((INSTANCE) == TIM10)   || \
-   ((INSTANCE) == TIM11)   || \
-   ((INSTANCE) == TIM12)   || \
-   ((INSTANCE) == TIM13)   || \
-   ((INSTANCE) == TIM14))
+   ((INSTANCE) == TIM7))
 
 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\
   (((INSTANCE) == TIM1)    || \
@@ -11544,13 +11400,7 @@ typedef struct
    ((INSTANCE) == TIM2)    || \
    ((INSTANCE) == TIM3)    || \
    ((INSTANCE) == TIM4)    || \
-   ((INSTANCE) == TIM5)    || \
-   ((INSTANCE) == TIM9)    || \
-   ((INSTANCE) == TIM10)   || \
-   ((INSTANCE) == TIM11)   || \
-   ((INSTANCE) == TIM12)   || \
-   ((INSTANCE) == TIM13)   || \
-   ((INSTANCE) == TIM14))
+   ((INSTANCE) == TIM5))
 
 #define IS_TIM_CC2_INSTANCE(INSTANCE)\
   (((INSTANCE) == TIM1)    || \
@@ -11558,9 +11408,7 @@ typedef struct
    ((INSTANCE) == TIM2)    || \
    ((INSTANCE) == TIM3)    || \
    ((INSTANCE) == TIM4)    || \
-   ((INSTANCE) == TIM5)    || \
-   ((INSTANCE) == TIM9)    || \
-   ((INSTANCE) == TIM12))
+   ((INSTANCE) == TIM5))
 
 #define IS_TIM_CC3_INSTANCE(INSTANCE)\
   (((INSTANCE) == TIM1)    || \
@@ -11600,9 +11448,7 @@ typedef struct
    ((INSTANCE) == TIM2)    || \
    ((INSTANCE) == TIM3)    || \
    ((INSTANCE) == TIM4)    || \
-   ((INSTANCE) == TIM5)    || \
-   ((INSTANCE) == TIM9)    || \
-   ((INSTANCE) == TIM12))
+   ((INSTANCE) == TIM5))
 
 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
   (((INSTANCE) == TIM1)    || \
@@ -11610,9 +11456,7 @@ typedef struct
    ((INSTANCE) == TIM2)    || \
    ((INSTANCE) == TIM3)    || \
    ((INSTANCE) == TIM4)    || \
-   ((INSTANCE) == TIM5)    || \
-   ((INSTANCE) == TIM9)    || \
-   ((INSTANCE) == TIM12))
+   ((INSTANCE) == TIM5))
 
 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
   (((INSTANCE) == TIM1)    || \
@@ -11646,8 +11490,7 @@ typedef struct
    ((INSTANCE) == TIM4)    || \
    ((INSTANCE) == TIM5)    || \
    ((INSTANCE) == TIM6)    || \
-   ((INSTANCE) == TIM7)    || \
-   ((INSTANCE) == TIM12))
+   ((INSTANCE) == TIM7))
 
 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
   (((INSTANCE) == TIM1)    || \
@@ -11655,8 +11498,7 @@ typedef struct
    ((INSTANCE) == TIM2)    || \
    ((INSTANCE) == TIM3)    || \
    ((INSTANCE) == TIM4)    || \
-   ((INSTANCE) == TIM5)    || \
-   ((INSTANCE) == TIM12))
+   ((INSTANCE) == TIM5))
 
 #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)  IS_TIM_MASTER_INSTANCE(INSTANCE)
 
@@ -11707,27 +11549,7 @@ typedef struct
      (((CHANNEL) == TIM_CHANNEL_1) ||          \
       ((CHANNEL) == TIM_CHANNEL_2) ||          \
       ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM10) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM12) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM13) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM14) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
+      ((CHANNEL) == TIM_CHANNEL_4))))
 
 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
    ((((INSTANCE) == TIM1) &&                    \
@@ -11758,13 +11580,7 @@ typedef struct
    ((INSTANCE) == TIM2)    || \
    ((INSTANCE) == TIM3)    || \
    ((INSTANCE) == TIM4)    || \
-   ((INSTANCE) == TIM5)    || \
-   ((INSTANCE) == TIM9)    || \
-   ((INSTANCE) == TIM10)   || \
-   ((INSTANCE) == TIM11)   || \
-   ((INSTANCE) == TIM12)   || \
-   ((INSTANCE) == TIM13)   || \
-   ((INSTANCE) == TIM14))
+   ((INSTANCE) == TIM5))
 
 #define IS_TIM_DMA_INSTANCE(INSTANCE)\
   (((INSTANCE) == TIM1)    || \
@@ -11893,26 +11709,26 @@ typedef struct
 /* Aliases for __IRQn */
 #define ADC1_IRQn               ADC1_2_IRQn
 #define DMA2_Channel4_IRQn      DMA2_Channel4_5_IRQn
-#define TIM1_BRK_IRQn           TIM1_BRK_TIM9_IRQn
-#define TIM1_BRK_TIM15_IRQn     TIM1_BRK_TIM9_IRQn
-#define TIM9_IRQn               TIM1_BRK_TIM9_IRQn
-#define TIM11_IRQn              TIM1_TRG_COM_TIM11_IRQn
-#define TIM1_TRG_COM_IRQn       TIM1_TRG_COM_TIM11_IRQn
-#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_TIM11_IRQn
-#define TIM10_IRQn              TIM1_UP_TIM10_IRQn
-#define TIM1_UP_TIM16_IRQn      TIM1_UP_TIM10_IRQn
-#define TIM1_UP_IRQn            TIM1_UP_TIM10_IRQn
+#define TIM1_BRK_TIM9_IRQn      TIM1_BRK_IRQn
+#define TIM1_BRK_TIM15_IRQn     TIM1_BRK_IRQn
+#define TIM9_IRQn               TIM1_BRK_IRQn
+#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
+#define TIM11_IRQn              TIM1_TRG_COM_IRQn
+#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
+#define TIM10_IRQn              TIM1_UP_IRQn
+#define TIM1_UP_TIM10_IRQn      TIM1_UP_IRQn
+#define TIM1_UP_TIM16_IRQn      TIM1_UP_IRQn
 #define TIM6_DAC_IRQn           TIM6_IRQn
-#define TIM12_IRQn              TIM8_BRK_TIM12_IRQn
-#define TIM8_BRK_IRQn           TIM8_BRK_TIM12_IRQn
-#define TIM8_TRG_COM_IRQn       TIM8_TRG_COM_TIM14_IRQn
-#define TIM14_IRQn              TIM8_TRG_COM_TIM14_IRQn
-#define TIM8_UP_IRQn            TIM8_UP_TIM13_IRQn
-#define TIM13_IRQn              TIM8_UP_TIM13_IRQn
+#define TIM12_IRQn              TIM8_BRK_IRQn
+#define TIM8_BRK_TIM12_IRQn     TIM8_BRK_IRQn
+#define TIM8_TRG_COM_TIM14_IRQn TIM8_TRG_COM_IRQn
+#define TIM14_IRQn              TIM8_TRG_COM_IRQn
+#define TIM8_UP_TIM13_IRQn      TIM8_UP_IRQn
+#define TIM13_IRQn              TIM8_UP_IRQn
 #define CEC_IRQn                USBWakeUp_IRQn
 #define OTG_FS_WKUP_IRQn        USBWakeUp_IRQn
-#define CAN1_TX_IRQn            USB_HP_CAN1_TX_IRQn
 #define USB_HP_IRQn             USB_HP_CAN1_TX_IRQn
+#define CAN1_TX_IRQn            USB_HP_CAN1_TX_IRQn
 #define USB_LP_IRQn             USB_LP_CAN1_RX0_IRQn
 #define CAN1_RX0_IRQn           USB_LP_CAN1_RX0_IRQn
 
@@ -11920,26 +11736,26 @@ typedef struct
 /* Aliases for __IRQHandler */
 #define ADC1_IRQHandler               ADC1_2_IRQHandler
 #define DMA2_Channel4_IRQHandler      DMA2_Channel4_5_IRQHandler
-#define TIM1_BRK_IRQHandler           TIM1_BRK_TIM9_IRQHandler
-#define TIM1_BRK_TIM15_IRQHandler     TIM1_BRK_TIM9_IRQHandler
-#define TIM9_IRQHandler               TIM1_BRK_TIM9_IRQHandler
-#define TIM11_IRQHandler              TIM1_TRG_COM_TIM11_IRQHandler
-#define TIM1_TRG_COM_IRQHandler       TIM1_TRG_COM_TIM11_IRQHandler
-#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_TIM11_IRQHandler
-#define TIM10_IRQHandler              TIM1_UP_TIM10_IRQHandler
-#define TIM1_UP_TIM16_IRQHandler      TIM1_UP_TIM10_IRQHandler
-#define TIM1_UP_IRQHandler            TIM1_UP_TIM10_IRQHandler
+#define TIM1_BRK_TIM9_IRQHandler      TIM1_BRK_IRQHandler
+#define TIM1_BRK_TIM15_IRQHandler     TIM1_BRK_IRQHandler
+#define TIM9_IRQHandler               TIM1_BRK_IRQHandler
+#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
+#define TIM11_IRQHandler              TIM1_TRG_COM_IRQHandler
+#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
+#define TIM10_IRQHandler              TIM1_UP_IRQHandler
+#define TIM1_UP_TIM10_IRQHandler      TIM1_UP_IRQHandler
+#define TIM1_UP_TIM16_IRQHandler      TIM1_UP_IRQHandler
 #define TIM6_DAC_IRQHandler           TIM6_IRQHandler
-#define TIM12_IRQHandler              TIM8_BRK_TIM12_IRQHandler
-#define TIM8_BRK_IRQHandler           TIM8_BRK_TIM12_IRQHandler
-#define TIM8_TRG_COM_IRQHandler       TIM8_TRG_COM_TIM14_IRQHandler
-#define TIM14_IRQHandler              TIM8_TRG_COM_TIM14_IRQHandler
-#define TIM8_UP_IRQHandler            TIM8_UP_TIM13_IRQHandler
-#define TIM13_IRQHandler              TIM8_UP_TIM13_IRQHandler
+#define TIM12_IRQHandler              TIM8_BRK_IRQHandler
+#define TIM8_BRK_TIM12_IRQHandler     TIM8_BRK_IRQHandler
+#define TIM8_TRG_COM_TIM14_IRQHandler TIM8_TRG_COM_IRQHandler
+#define TIM14_IRQHandler              TIM8_TRG_COM_IRQHandler
+#define TIM8_UP_TIM13_IRQHandler      TIM8_UP_IRQHandler
+#define TIM13_IRQHandler              TIM8_UP_IRQHandler
 #define CEC_IRQHandler                USBWakeUp_IRQHandler
 #define OTG_FS_WKUP_IRQHandler        USBWakeUp_IRQHandler
-#define CAN1_TX_IRQHandler            USB_HP_CAN1_TX_IRQHandler
 #define USB_HP_IRQHandler             USB_HP_CAN1_TX_IRQHandler
+#define CAN1_TX_IRQHandler            USB_HP_CAN1_TX_IRQHandler
 #define USB_LP_IRQHandler             USB_LP_CAN1_RX0_IRQHandler
 #define CAN1_RX0_IRQHandler           USB_LP_CAN1_RX0_IRQHandler
 
@@ -11956,7 +11772,7 @@ typedef struct
   }
 #endif /* __cplusplus */
   
-#endif /* __STM32F103xG_H */
+#endif /* __STM32F103xE_H */
   
   
   

Inc/BDA4601.h

@@ -0,0 +1,13 @@
+/*
+ * BDA4601.h
+ *
+ *  Created on: 2019. 6. 28.
+ *      Author: parkyj
+ */
+
+#ifndef BDA4601_H_
+#define BDA4601_H_
+
+
+
+#endif /* BDA4601_H_ */

Inc/PE43711.h

@@ -0,0 +1,13 @@
+/*
+ * PE43711.h
+ *
+ *  Created on: 2019. 6. 28.
+ *      Author: parkyj
+ */
+
+#ifndef PE43711_H_
+#define PE43711_H_
+#include "main.h"
+
+
+#endif /* PE43711_H_ */

Inc/main.h

@@ -29,7 +29,7 @@ extern "C" {
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f1xx_hal.h"
-
+#include "PE43711.h"
 /* Private includes ----------------------------------------------------------*/
 /* USER CODE BEGIN Includes */
 
@@ -74,6 +74,26 @@ void Error_Handler(void);
 #define PATH_EN_1_8G_DL_GPIO_Port GPIOC
 #define PATH_EN_1_8G_UL_Pin GPIO_PIN_15
 #define PATH_EN_1_8G_UL_GPIO_Port GPIOC
+#define PLL_EN_1_8G_DL_Pin GPIO_PIN_0
+#define PLL_EN_1_8G_DL_GPIO_Port GPIOF
+#define PLL_EN_1_8G_UL_Pin GPIO_PIN_1
+#define PLL_EN_1_8G_UL_GPIO_Port GPIOF
+#define PLL_LD_1_8G_DL_Pin GPIO_PIN_2
+#define PLL_LD_1_8G_DL_GPIO_Port GPIOF
+#define PLL_LD_1_8G_UL_Pin GPIO_PIN_3
+#define PLL_LD_1_8G_UL_GPIO_Port GPIOF
+#define ATT_EN_2_1G_DL1_Pin GPIO_PIN_4
+#define ATT_EN_2_1G_DL1_GPIO_Port GPIOF
+#define ATT_EN_2_1G_DL2_Pin GPIO_PIN_5
+#define ATT_EN_2_1G_DL2_GPIO_Port GPIOF
+#define ATT_EN_2_1G_UL1_Pin GPIO_PIN_6
+#define ATT_EN_2_1G_UL1_GPIO_Port GPIOF
+#define ATT_EN_2_1G_UL2_Pin GPIO_PIN_7
+#define ATT_EN_2_1G_UL2_GPIO_Port GPIOF
+#define ATT_EN_2_1G_UL3_Pin GPIO_PIN_8
+#define ATT_EN_2_1G_UL3_GPIO_Port GPIOF
+#define ATT_EN_2_1G_UL4_Pin GPIO_PIN_9
+#define ATT_EN_2_1G_UL4_GPIO_Port GPIOF
 #define DET_3_5G_UL_IN_Pin GPIO_PIN_0
 #define DET_3_5G_UL_IN_GPIO_Port GPIOC
 #define DET_3_5G_UL_OUT_Pin GPIO_PIN_1
@@ -102,100 +122,80 @@ void Error_Handler(void);
 #define DET_3_5G_DL_IN_GPIO_Port GPIOB
 #define DET_3_5G_DL_OUT_Pin GPIO_PIN_1
 #define DET_3_5G_DL_OUT_GPIO_Port GPIOB
+#define PLL_DATA_Pin GPIO_PIN_8
+#define PLL_DATA_GPIO_Port GPIOD
+#define PLL_CLK_Pin GPIO_PIN_9
+#define PLL_CLK_GPIO_Port GPIOD
+#define ATT_DATA_Pin GPIO_PIN_10
+#define ATT_DATA_GPIO_Port GPIOD
 #define ATT_CLK_Pin GPIO_PIN_11
-#define ATT_CLK_GPIO_Port GPIOE
-#define ATT_DATA_Pin GPIO_PIN_12
-#define ATT_DATA_GPIO_Port GPIOE
-#define PLL_CLK_Pin GPIO_PIN_13
-#define PLL_CLK_GPIO_Port GPIOE
-#define PLL_DATA_Pin GPIO_PIN_14
-#define PLL_DATA_GPIO_Port GPIOE
-#define ALARM_DC_Pin GPIO_PIN_15
-#define ALARM_DC_GPIO_Port GPIOE
-#define ALARM_AC_Pin GPIO_PIN_10
-#define ALARM_AC_GPIO_Port GPIOB
-#define DA_LDAC_Pin GPIO_PIN_11
-#define DA_LDAC_GPIO_Port GPIOB
-#define DA_SYNC_Pin GPIO_PIN_12
-#define DA_SYNC_GPIO_Port GPIOB
-#define DA_SCLK_Pin GPIO_PIN_13
-#define DA_SCLK_GPIO_Port GPIOB
-#define DA_DIN_Pin GPIO_PIN_14
-#define DA_DIN_GPIO_Port GPIOB
-#define _T_SYNC_UL_Pin GPIO_PIN_15
-#define _T_SYNC_UL_GPIO_Port GPIOB
-#define T_SYNC_UL_Pin GPIO_PIN_8
-#define T_SYNC_UL_GPIO_Port GPIOD
-#define _T_SYNC_DL_Pin GPIO_PIN_9
-#define _T_SYNC_DL_GPIO_Port GPIOD
-#define T_SYNC_DL_Pin GPIO_PIN_10
-#define T_SYNC_DL_GPIO_Port GPIOD
-#define PLL_LD_3_5G_H_Pin GPIO_PIN_11
-#define PLL_LD_3_5G_H_GPIO_Port GPIOD
-#define PLL_LD_3_5G_L_Pin GPIO_PIN_12
-#define PLL_LD_3_5G_L_GPIO_Port GPIOD
-#define PLL_EN_3_5G_H_Pin GPIO_PIN_13
-#define PLL_EN_3_5G_H_GPIO_Port GPIOD
-#define PLL_EN_3_5G_L_Pin GPIO_PIN_14
-#define PLL_EN_3_5G_L_GPIO_Port GPIOD
-#define PLL_ON_OFF_3_5G_H_Pin GPIO_PIN_15
-#define PLL_ON_OFF_3_5G_H_GPIO_Port GPIOD
-#define PLL_ON_OFF_3_5G_L_Pin GPIO_PIN_6
-#define PLL_ON_OFF_3_5G_L_GPIO_Port GPIOC
-#define PATH_EN_3_5G_UL_Pin GPIO_PIN_7
-#define PATH_EN_3_5G_UL_GPIO_Port GPIOC
-#define PATH_EN_3_5G_DL_Pin GPIO_PIN_8
-#define PATH_EN_3_5G_DL_GPIO_Port GPIOC
+#define ATT_CLK_GPIO_Port GPIOD
+#define ALARM_DC_Pin GPIO_PIN_12
+#define ALARM_DC_GPIO_Port GPIOD
+#define ALARM_AC_Pin GPIO_PIN_13
+#define ALARM_AC_GPIO_Port GPIOD
+#define DA_LDAC_Pin GPIO_PIN_15
+#define DA_LDAC_GPIO_Port GPIOD
+#define DA_SYNC_Pin GPIO_PIN_2
+#define DA_SYNC_GPIO_Port GPIOG
+#define DA_SCLK_Pin GPIO_PIN_3
+#define DA_SCLK_GPIO_Port GPIOG
+#define DA_DIN_Pin GPIO_PIN_4
+#define DA_DIN_GPIO_Port GPIOG
+#define _T_SYNC_UL_Pin GPIO_PIN_5
+#define _T_SYNC_UL_GPIO_Port GPIOG
+#define T_SYNC_UL_Pin GPIO_PIN_6
+#define T_SYNC_UL_GPIO_Port GPIOG
+#define _T_SYNC_DL_Pin GPIO_PIN_7
+#define _T_SYNC_DL_GPIO_Port GPIOG
+#define T_SYNC_DL_Pin GPIO_PIN_8
+#define T_SYNC_DL_GPIO_Port GPIOG
+#define PLL_EN_3_5G_L_Pin GPIO_PIN_6
+#define PLL_EN_3_5G_L_GPIO_Port GPIOC
+#define PLL_EN_3_5G_H_Pin GPIO_PIN_7
+#define PLL_EN_3_5G_H_GPIO_Port GPIOC
+#define PLL_LD_3_5G_L_Pin GPIO_PIN_8
+#define PLL_LD_3_5G_L_GPIO_Port GPIOC
+#define PLL_LD_3_5G_H_Pin GPIO_PIN_9
+#define PLL_LD_3_5G_H_GPIO_Port GPIOC
+#define ATT_CLK_3_5G_Pin GPIO_PIN_0
+#define ATT_CLK_3_5G_GPIO_Port GPIOD
+#define ATT_EN_3_5G_Pin GPIO_PIN_1
+#define ATT_EN_3_5G_GPIO_Port GPIOD
+#define ATT_DATA_3_5G_DL_Pin GPIO_PIN_2
+#define ATT_DATA_3_5G_DL_GPIO_Port GPIOD
+#define ATT_DATA_3_5G_UL_Pin GPIO_PIN_3
+#define ATT_DATA_3_5G_UL_GPIO_Port GPIOD
+#define ATT_DATA_3_5G_COM1_Pin GPIO_PIN_4
+#define ATT_DATA_3_5G_COM1_GPIO_Port GPIOD
+#define ATT_DATA_3_5G_COM2_Pin GPIO_PIN_5
+#define ATT_DATA_3_5G_COM2_GPIO_Port GPIOD
+#define ATT_DATA_3_5G_COM3_Pin GPIO_PIN_6
+#define ATT_DATA_3_5G_COM3_GPIO_Port GPIOD
+#define PATH_EN_3_5G_L_Pin GPIO_PIN_7
+#define PATH_EN_3_5G_L_GPIO_Port GPIOD
 #define PATH_EN_3_5G_H_Pin GPIO_PIN_9
-#define PATH_EN_3_5G_H_GPIO_Port GPIOC
-#define PATH_EN_3_5G_L_Pin GPIO_PIN_8
-#define PATH_EN_3_5G_L_GPIO_Port GPIOA
-#define ATT_DATA_3_5G_COM3_Pin GPIO_PIN_12
-#define ATT_DATA_3_5G_COM3_GPIO_Port GPIOA
-#define ATT_DATA_3_5G_COM2_Pin GPIO_PIN_13
-#define ATT_DATA_3_5G_COM2_GPIO_Port GPIOA
-#define ATT_DATA_3_5G_COM1_Pin GPIO_PIN_14
-#define ATT_DATA_3_5G_COM1_GPIO_Port GPIOA
-#define ATT_DATA_3_5G_UL_Pin GPIO_PIN_15
-#define ATT_DATA_3_5G_UL_GPIO_Port GPIOA
-#define ATT_DATA_3_5G_DL_Pin GPIO_PIN_10
-#define ATT_DATA_3_5G_DL_GPIO_Port GPIOC
-#define ATT_EN_3_5G_Pin GPIO_PIN_11
-#define ATT_EN_3_5G_GPIO_Port GPIOC
-#define ATT_CLK_3_5G_Pin GPIO_PIN_12
-#define ATT_CLK_3_5G_GPIO_Port GPIOC
-#define PLL_LD_2_1G_UL_Pin GPIO_PIN_1
-#define PLL_LD_2_1G_UL_GPIO_Port GPIOD
-#define PLL_LD_2_1G_DL_Pin GPIO_PIN_2
-#define PLL_LD_2_1G_DL_GPIO_Port GPIOD
-#define PLL_EN_2_1G_UL_Pin GPIO_PIN_3
-#define PLL_EN_2_1G_UL_GPIO_Port GPIOD
-#define PLL_EN_2_1G_DL_Pin GPIO_PIN_4
-#define PLL_EN_2_1G_DL_GPIO_Port GPIOD
-#define PATH_EN_2_1G_UL_Pin GPIO_PIN_5
-#define PATH_EN_2_1G_UL_GPIO_Port GPIOD
-#define PATH_EN_2_1G_DL_Pin GPIO_PIN_6
-#define PATH_EN_2_1G_DL_GPIO_Port GPIOD
-#define ATT_EN_2_1G_UL4_Pin GPIO_PIN_7
-#define ATT_EN_2_1G_UL4_GPIO_Port GPIOD
-#define ATT_EN_2_1G_UL3_Pin GPIO_PIN_3
-#define ATT_EN_2_1G_UL3_GPIO_Port GPIOB
-#define ATT_EN_2_1G_UL2_Pin GPIO_PIN_4
-#define ATT_EN_2_1G_UL2_GPIO_Port GPIOB
-#define ATT_EN_2_1G_UL1_Pin GPIO_PIN_5
-#define ATT_EN_2_1G_UL1_GPIO_Port GPIOB
-#define ATT_EN_2_1G_DL2_Pin GPIO_PIN_6
-#define ATT_EN_2_1G_DL2_GPIO_Port GPIOB
-#define ATT_EN_2_1G_DL1_Pin GPIO_PIN_7
-#define ATT_EN_2_1G_DL1_GPIO_Port GPIOB
-#define PLL_LD_1_8G_UL_Pin GPIO_PIN_8
-#define PLL_LD_1_8G_UL_GPIO_Port GPIOB
-#define PLL_LD_1_8G_DL_Pin GPIO_PIN_9
-#define PLL_LD_1_8G_DL_GPIO_Port GPIOB
-#define PLL_EN_1_8G_UL_Pin GPIO_PIN_0
-#define PLL_EN_1_8G_UL_GPIO_Port GPIOE
-#define PLL_EN_1_8G_DL_Pin GPIO_PIN_1
-#define PLL_EN_1_8G_DL_GPIO_Port GPIOE
+#define PATH_EN_3_5G_H_GPIO_Port GPIOG
+#define PATH_EN_3_5G_DL_Pin GPIO_PIN_10
+#define PATH_EN_3_5G_DL_GPIO_Port GPIOG
+#define PATH_EN_3_5G_UL_Pin GPIO_PIN_11
+#define PATH_EN_3_5G_UL_GPIO_Port GPIOG
+#define PLL_ON_OFF_3_5G_L_Pin GPIO_PIN_12
+#define PLL_ON_OFF_3_5G_L_GPIO_Port GPIOG
+#define PLL_ON_OFF_3_5G_H_Pin GPIO_PIN_13
+#define PLL_ON_OFF_3_5G_H_GPIO_Port GPIOG
+#define PLL_EN_2_1G_DL_Pin GPIO_PIN_3
+#define PLL_EN_2_1G_DL_GPIO_Port GPIOB
+#define PLL_EN_2_1G_UL_Pin GPIO_PIN_4
+#define PLL_EN_2_1G_UL_GPIO_Port GPIOB
+#define PLL_LD_2_1G_DL_Pin GPIO_PIN_5
+#define PLL_LD_2_1G_DL_GPIO_Port GPIOB
+#define PLL_LD_2_1G_UL_Pin GPIO_PIN_6
+#define PLL_LD_2_1G_UL_GPIO_Port GPIOB
+#define PATH_EN_2_1G_DL_Pin GPIO_PIN_0
+#define PATH_EN_2_1G_DL_GPIO_Port GPIOE
+#define PATH_EN_2_1G_UL_Pin GPIO_PIN_1
+#define PATH_EN_2_1G_UL_GPIO_Port GPIOE
 /* USER CODE BEGIN Private defines */
 
 /* USER CODE END Private defines */

Inc/stm32f1xx_hal_conf.h

@@ -56,7 +56,7 @@
 /*#define HAL_CORTEX_MODULE_ENABLED   */
 /*#define HAL_CRC_MODULE_ENABLED   */
 /*#define HAL_DAC_MODULE_ENABLED   */
-/*#define HAL_DMA_MODULE_ENABLED   */
+#define HAL_DMA_MODULE_ENABLED
 /*#define HAL_ETH_MODULE_ENABLED   */
 /*#define HAL_FLASH_MODULE_ENABLED   */
 #define HAL_GPIO_MODULE_ENABLED

Inc/stm32f1xx_it.h

@@ -56,6 +56,8 @@ void SVC_Handler(void);
 void DebugMon_Handler(void);
 void PendSV_Handler(void);
 void SysTick_Handler(void);
+void DMA1_Channel1_IRQHandler(void);
+void USART1_IRQHandler(void);
 /* USER CODE BEGIN EFP */
 
 /* USER CODE END EFP */

STM32F103VG_FLASH.ld

@@ -4,8 +4,8 @@
 
 **  File        : stm32_flash.ld
 **
-**  Abstract    : Linker script for STM32F103VG Device with
-**                1024KByte FLASH, 96KByte RAM
+**  Abstract    : Linker script for STM32F103ZE Device with
+**                512KByte FLASH, 64KByte RAM
 **
 **                Set heap size, stack size and stack location according
 **                to application requirements.
@@ -32,7 +32,7 @@
 ENTRY(Reset_Handler)
 
 /* Highest address of the user mode stack */
-_estack = 0x20018000;    /* end of RAM */
+_estack = 0x20010000;    /* end of RAM */
 /* Generate a link error if heap and stack don't fit into RAM */
 _Min_Heap_Size = 0x200;      /* required amount of heap  */
 _Min_Stack_Size = 0x400; /* required amount of stack */
@@ -40,8 +40,8 @@ _Min_Stack_Size = 0x400; /* required amount of stack */
 /* Specify the memory areas */
 MEMORY
 {
-RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 96K
-FLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 1024K
+RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 64K
+FLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 512K
 }
 
 /* Define output sections */

STM32F103_ATTEN_PLL_Zig.elf.launch

@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <launchConfiguration type="com.atollic.hardwaredebug.launch.launchConfigurationType">
 <stringAttribute key="com.atollic.hardwaredebug.jlink_common.cpu_core" value="Cortex-M" />
-<stringAttribute key="com.atollic.hardwaredebug.jlink_common.device" value="STM32F103VG" />
+<stringAttribute key="com.atollic.hardwaredebug.jlink_common.device" value="STM32F103ZE" />
 <stringAttribute key="com.atollic.hardwaredebug.jlink_common.endian" value="little" />
 <stringAttribute key="com.atollic.hardwaredebug.jlink_common.init_speed" value="4000" />
 <booleanAttribute key="com.atollic.hardwaredebug.jlink_common.scan_chain_auto" value="true" />

STM32F103_ATTEN_PLL_Zig.ioc

@@ -1,101 +1,118 @@
 #MicroXplorer Configuration settings - do not modify
 ADC1.Channel-1\#ChannelRegularConversion=ADC_CHANNEL_0
-ADC1.IPParameters=Rank-1\#ChannelRegularConversion,Channel-1\#ChannelRegularConversion,SamplingTime-1\#ChannelRegularConversion,NbrOfConversionFlag,master
+ADC1.Channel-2\#ChannelRegularConversion=ADC_CHANNEL_0
+ADC1.IPParameters=Rank-1\#ChannelRegularConversion,Channel-1\#ChannelRegularConversion,SamplingTime-1\#ChannelRegularConversion,NbrOfConversionFlag,master,NbrOfConversion,Rank-2\#ChannelRegularConversion,Channel-2\#ChannelRegularConversion,SamplingTime-2\#ChannelRegularConversion
+ADC1.NbrOfConversion=2
 ADC1.NbrOfConversionFlag=1
 ADC1.Rank-1\#ChannelRegularConversion=1
+ADC1.Rank-2\#ChannelRegularConversion=2
 ADC1.SamplingTime-1\#ChannelRegularConversion=ADC_SAMPLETIME_1CYCLE_5
+ADC1.SamplingTime-2\#ChannelRegularConversion=ADC_SAMPLETIME_1CYCLE_5
 ADC1.master=1
+Dma.ADC1.0.Direction=DMA_PERIPH_TO_MEMORY
+Dma.ADC1.0.Instance=DMA1_Channel1
+Dma.ADC1.0.MemDataAlignment=DMA_MDATAALIGN_HALFWORD
+Dma.ADC1.0.MemInc=DMA_MINC_ENABLE
+Dma.ADC1.0.Mode=DMA_CIRCULAR
+Dma.ADC1.0.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD
+Dma.ADC1.0.PeriphInc=DMA_PINC_DISABLE
+Dma.ADC1.0.Priority=DMA_PRIORITY_LOW
+Dma.ADC1.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority
+Dma.Request0=ADC1
+Dma.RequestsNb=1
 File.Version=6
 KeepUserPlacement=false
 Mcu.Family=STM32F1
 Mcu.IP0=ADC1
-Mcu.IP1=NVIC
-Mcu.IP2=RCC
-Mcu.IP3=SYS
-Mcu.IP4=USART1
-Mcu.IPNb=5
-Mcu.Name=STM32F103V(F-G)Tx
-Mcu.Package=LQFP100
+Mcu.IP1=DMA
+Mcu.IP2=NVIC
+Mcu.IP3=RCC
+Mcu.IP4=SYS
+Mcu.IP5=USART1
+Mcu.IPNb=6
+Mcu.Name=STM32F103Z(C-D-E)Tx
+Mcu.Package=LQFP144
 Mcu.Pin0=PE2
 Mcu.Pin1=PE3
-Mcu.Pin10=PC2
-Mcu.Pin11=PC3
-Mcu.Pin12=PA0-WKUP
-Mcu.Pin13=PA1
-Mcu.Pin14=PA2
-Mcu.Pin15=PA3
-Mcu.Pin16=PA4
-Mcu.Pin17=PA5
-Mcu.Pin18=PA6
-Mcu.Pin19=PA7
+Mcu.Pin10=PF2
+Mcu.Pin11=PF3
+Mcu.Pin12=PF4
+Mcu.Pin13=PF5
+Mcu.Pin14=PF6
+Mcu.Pin15=PF7
+Mcu.Pin16=PF8
+Mcu.Pin17=PF9
+Mcu.Pin18=PC0
+Mcu.Pin19=PC1
 Mcu.Pin2=PE4
-Mcu.Pin20=PB0
-Mcu.Pin21=PB1
-Mcu.Pin22=PE11
-Mcu.Pin23=PE12
-Mcu.Pin24=PE13
-Mcu.Pin25=PE14
-Mcu.Pin26=PE15
-Mcu.Pin27=PB10
-Mcu.Pin28=PB11
-Mcu.Pin29=PB12
+Mcu.Pin20=PC2
+Mcu.Pin21=PC3
+Mcu.Pin22=PA0-WKUP
+Mcu.Pin23=PA1
+Mcu.Pin24=PA2
+Mcu.Pin25=PA3
+Mcu.Pin26=PA4
+Mcu.Pin27=PA5
+Mcu.Pin28=PA6
+Mcu.Pin29=PA7
 Mcu.Pin3=PE5
-Mcu.Pin30=PB13
-Mcu.Pin31=PB14
-Mcu.Pin32=PB15
-Mcu.Pin33=PD8
-Mcu.Pin34=PD9
-Mcu.Pin35=PD10
-Mcu.Pin36=PD11
-Mcu.Pin37=PD12
-Mcu.Pin38=PD13
-Mcu.Pin39=PD14
+Mcu.Pin30=PB0
+Mcu.Pin31=PB1
+Mcu.Pin32=PD8
+Mcu.Pin33=PD9
+Mcu.Pin34=PD10
+Mcu.Pin35=PD11
+Mcu.Pin36=PD12
+Mcu.Pin37=PD13
+Mcu.Pin38=PD15
+Mcu.Pin39=PG2
 Mcu.Pin4=PE6
-Mcu.Pin40=PD15
-Mcu.Pin41=PC6
-Mcu.Pin42=PC7
-Mcu.Pin43=PC8
-Mcu.Pin44=PC9
-Mcu.Pin45=PA8
-Mcu.Pin46=PA9
-Mcu.Pin47=PA10
-Mcu.Pin48=PA12
-Mcu.Pin49=PA13
+Mcu.Pin40=PG3
+Mcu.Pin41=PG4
+Mcu.Pin42=PG5
+Mcu.Pin43=PG6
+Mcu.Pin44=PG7
+Mcu.Pin45=PG8
+Mcu.Pin46=PC6
+Mcu.Pin47=PC7
+Mcu.Pin48=PC8
+Mcu.Pin49=PC9
 Mcu.Pin5=PC13-TAMPER-RTC
-Mcu.Pin50=PA14
-Mcu.Pin51=PA15
-Mcu.Pin52=PC10
-Mcu.Pin53=PC11
-Mcu.Pin54=PC12
-Mcu.Pin55=PD1
-Mcu.Pin56=PD2
-Mcu.Pin57=PD3
-Mcu.Pin58=PD4
-Mcu.Pin59=PD5
+Mcu.Pin50=PA9
+Mcu.Pin51=PA10
+Mcu.Pin52=PD0
+Mcu.Pin53=PD1
+Mcu.Pin54=PD2
+Mcu.Pin55=PD3
+Mcu.Pin56=PD4
+Mcu.Pin57=PD5
+Mcu.Pin58=PD6
+Mcu.Pin59=PD7
 Mcu.Pin6=PC14-OSC32_IN
-Mcu.Pin60=PD6
-Mcu.Pin61=PD7
-Mcu.Pin62=PB3
-Mcu.Pin63=PB4
-Mcu.Pin64=PB5
-Mcu.Pin65=PB6
-Mcu.Pin66=PB7
-Mcu.Pin67=PB8
-Mcu.Pin68=PB9
+Mcu.Pin60=PG9
+Mcu.Pin61=PG10
+Mcu.Pin62=PG11
+Mcu.Pin63=PG12
+Mcu.Pin64=PG13
+Mcu.Pin65=PB3
+Mcu.Pin66=PB4
+Mcu.Pin67=PB5
+Mcu.Pin68=PB6
 Mcu.Pin69=PE0
 Mcu.Pin7=PC15-OSC32_OUT
 Mcu.Pin70=PE1
 Mcu.Pin71=VP_SYS_VS_ND
 Mcu.Pin72=VP_SYS_VS_Systick
-Mcu.Pin8=PC0
-Mcu.Pin9=PC1
+Mcu.Pin8=PF0
+Mcu.Pin9=PF1
 Mcu.PinsNb=73
 Mcu.ThirdPartyNb=0
 Mcu.UserConstants=
-Mcu.UserName=STM32F103VGTx
+Mcu.UserName=STM32F103ZETx
 MxCube.Version=5.2.1
 MxDb.Version=DB.5.0.21
 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DMA1_Channel1_IRQn=true\:0\:0\:false\:false\:true\:false\:true
 NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
 NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
 NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
@@ -104,6 +121,7 @@ NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
 NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
 NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
 NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.USART1_IRQn=true\:0\:0\:false\:true\:true\:1\:true\:true
 NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
 PA0-WKUP.GPIOParameters=GPIO_Label
 PA0-WKUP.GPIO_Label=DET_1.8G_DL_IN
@@ -113,22 +131,6 @@ PA1.GPIO_Label=DET_1.8G_DL_OUT
 PA1.Signal=ADCx_IN1
 PA10.Mode=Asynchronous
 PA10.Signal=USART1_RX
-PA12.GPIOParameters=GPIO_Label
-PA12.GPIO_Label=ATT_DATA_3.5G_COM3
-PA12.Locked=true
-PA12.Signal=GPIO_Output
-PA13.GPIOParameters=GPIO_Label
-PA13.GPIO_Label=ATT_DATA_3.5G_COM2
-PA13.Locked=true
-PA13.Signal=GPIO_Output
-PA14.GPIOParameters=GPIO_Label
-PA14.GPIO_Label=ATT_DATA_3.5G_COM1
-PA14.Locked=true
-PA14.Signal=GPIO_Output
-PA15.GPIOParameters=GPIO_Label
-PA15.GPIO_Label=ATT_DATA_3.5G_UL
-PA15.Locked=true
-PA15.Signal=GPIO_Output
 PA2.GPIOParameters=GPIO_Label
 PA2.GPIO_Label=DET_1.8G_UL_IN
 PA2.Signal=ADCx_IN2
@@ -147,10 +149,6 @@ PA6.Signal=ADCx_IN6
 PA7.GPIOParameters=GPIO_Label
 PA7.GPIO_Label=DET_2.1G_UL_OUT
 PA7.Signal=ADCx_IN7
-PA8.GPIOParameters=GPIO_Label
-PA8.GPIO_Label=PATH_EN_3.5G_L
-PA8.Locked=true
-PA8.Signal=GPIO_Output
 PA9.Mode=Asynchronous
 PA9.Signal=USART1_TX
 PB0.GPIOParameters=GPIO_Label
@@ -159,76 +157,28 @@ PB0.Signal=ADCx_IN8
 PB1.GPIOParameters=GPIO_Label
 PB1.GPIO_Label=DET_3.5G_DL_OUT
 PB1.Signal=ADCx_IN9
-PB10.GPIOParameters=GPIO_Label
-PB10.GPIO_Label=ALARM_AC
-PB10.Locked=true
-PB10.Signal=GPIO_Input
-PB11.GPIOParameters=GPIO_Label
-PB11.GPIO_Label=DA_LDAC
-PB11.Locked=true
-PB11.Signal=GPIO_Output
-PB12.GPIOParameters=GPIO_Label
-PB12.GPIO_Label=DA_SYNC
-PB12.Locked=true
-PB12.Signal=GPIO_Output
-PB13.GPIOParameters=GPIO_Label
-PB13.GPIO_Label=DA_SCLK
-PB13.Locked=true
-PB13.Signal=GPIO_Output
-PB14.GPIOParameters=GPIO_Label
-PB14.GPIO_Label=DA_DIN
-PB14.Locked=true
-PB14.Signal=GPIO_Output
-PB15.GPIOParameters=GPIO_Label
-PB15.GPIO_Label=_T-SYNC_UL
-PB15.Locked=true
-PB15.Signal=GPIO_Output
 PB3.GPIOParameters=GPIO_Label
-PB3.GPIO_Label=ATT_EN_2.1G_UL3
+PB3.GPIO_Label=PLL_EN_2.1G_DL
 PB3.Locked=true
 PB3.Signal=GPIO_Output
 PB4.GPIOParameters=GPIO_Label
-PB4.GPIO_Label=ATT_EN_2.1G_UL2
+PB4.GPIO_Label=PLL_EN_2.1G_UL
 PB4.Locked=true
 PB4.Signal=GPIO_Output
 PB5.GPIOParameters=GPIO_Label
-PB5.GPIO_Label=ATT_EN_2.1G_UL1
+PB5.GPIO_Label=PLL_LD_2.1G_DL
 PB5.Locked=true
-PB5.Signal=GPIO_Output
+PB5.Signal=GPIO_Input
 PB6.GPIOParameters=GPIO_Label
-PB6.GPIO_Label=ATT_EN_2.1G_DL2
+PB6.GPIO_Label=PLL_LD_2.1G_UL
 PB6.Locked=true
-PB6.Signal=GPIO_Output
-PB7.GPIOParameters=GPIO_Label
-PB7.GPIO_Label=ATT_EN_2.1G_DL1
-PB7.Locked=true
-PB7.Signal=GPIO_Output
-PB8.GPIOParameters=GPIO_Label
-PB8.GPIO_Label=PLL_LD_1.8G_UL
-PB8.Locked=true
-PB8.Signal=GPIO_Input
-PB9.GPIOParameters=GPIO_Label
-PB9.GPIO_Label=PLL_LD_1.8G_DL
-PB9.Locked=true
-PB9.Signal=GPIO_Input
+PB6.Signal=GPIO_Input
 PC0.GPIOParameters=GPIO_Label
 PC0.GPIO_Label=DET_3.5G_UL_IN
 PC0.Signal=ADCx_IN10
 PC1.GPIOParameters=GPIO_Label
 PC1.GPIO_Label=DET_3.5G_UL_OUT
 PC1.Signal=ADCx_IN11
-PC10.GPIOParameters=GPIO_Label
-PC10.GPIO_Label=ATT_DATA_3.5G_DL
-PC10.Locked=true
-PC10.Signal=GPIO_Output
-PC11.GPIOParameters=GPIO_Label
-PC11.GPIO_Label=ATT_EN_3.5G
-PC11.Locked=true
-PC11.Signal=GPIO_Output
-PC12.GPIOParameters=GPIO_Label
-PC12.GPIO_Label=ATT_CLK_3.5G
-PC12.Locked=true
-PC12.Signal=GPIO_Output
 PC13-TAMPER-RTC.GPIOParameters=GPIO_Label
 PC13-TAMPER-RTC.GPIO_Label=ATT_EN_1.8G_UL4
 PC13-TAMPER-RTC.Locked=true
@@ -248,120 +198,98 @@ PC3.GPIOParameters=GPIO_Label
 PC3.GPIO_Label=_28V_DET
 PC3.Signal=ADCx_IN13
 PC6.GPIOParameters=GPIO_Label
-PC6.GPIO_Label=PLL_ON/OFF_3.5G_L
+PC6.GPIO_Label=PLL_EN_3.5G_L
 PC6.Locked=true
 PC6.Signal=GPIO_Output
 PC7.GPIOParameters=GPIO_Label
-PC7.GPIO_Label=PATH_EN_3.5G_UL
+PC7.GPIO_Label=PLL_EN_3.5G_H
 PC7.Locked=true
 PC7.Signal=GPIO_Output
 PC8.GPIOParameters=GPIO_Label
-PC8.GPIO_Label=PATH_EN_3.5G_DL
+PC8.GPIO_Label=PLL_LD_3.5G_L
 PC8.Locked=true
-PC8.Signal=GPIO_Output
+PC8.Signal=GPIO_Input
 PC9.GPIOParameters=GPIO_Label
-PC9.GPIO_Label=PATH_EN_3.5G_H
+PC9.GPIO_Label=PLL_LD_3.5G_H
 PC9.Locked=true
-PC9.Signal=GPIO_Output
+PC9.Signal=GPIO_Input
 PCC.Checker=false
 PCC.Line=STM32F103
-PCC.MCU=STM32F103V(F-G)Tx
-PCC.PartNumber=STM32F103VGTx
+PCC.MCU=STM32F103Z(C-D-E)Tx
+PCC.PartNumber=STM32F103ZETx
 PCC.Seq0=0
 PCC.Series=STM32F1
 PCC.Temperature=25
 PCC.Vdd=3.3
+PD0.GPIOParameters=GPIO_Label
+PD0.GPIO_Label=ATT_CLK_3.5G
+PD0.Locked=true
+PD0.Signal=GPIO_Output
 PD1.GPIOParameters=GPIO_Label
-PD1.GPIO_Label=PLL_LD_2.1G_UL
+PD1.GPIO_Label=ATT_EN_3.5G
 PD1.Locked=true
-PD1.Signal=GPIO_Input
+PD1.Signal=GPIO_Output
 PD10.GPIOParameters=GPIO_Label
-PD10.GPIO_Label=T-SYNC_DL
+PD10.GPIO_Label=ATT_DATA
 PD10.Locked=true
 PD10.Signal=GPIO_Output
 PD11.GPIOParameters=GPIO_Label
-PD11.GPIO_Label=PLL_LD_3.5G_H
+PD11.GPIO_Label=ATT_CLK
 PD11.Locked=true
-PD11.Signal=GPIO_Input
+PD11.Signal=GPIO_Output
 PD12.GPIOParameters=GPIO_Label
-PD12.GPIO_Label=PLL_LD_3.5G_L
+PD12.GPIO_Label=ALARM_DC
 PD12.Locked=true
 PD12.Signal=GPIO_Input
 PD13.GPIOParameters=GPIO_Label
-PD13.GPIO_Label=PLL_EN_3.5G_H
+PD13.GPIO_Label=ALARM_AC
 PD13.Locked=true
-PD13.Signal=GPIO_Output
-PD14.GPIOParameters=GPIO_Label
-PD14.GPIO_Label=PLL_EN_3.5G_L
-PD14.Locked=true
-PD14.Signal=GPIO_Output
+PD13.Signal=GPIO_Input
 PD15.GPIOParameters=GPIO_Label
-PD15.GPIO_Label=PLL_ON/OFF_3.5G_H
+PD15.GPIO_Label=DA_LDAC
 PD15.Locked=true
 PD15.Signal=GPIO_Output
 PD2.GPIOParameters=GPIO_Label
-PD2.GPIO_Label=PLL_LD_2.1G_DL
+PD2.GPIO_Label=ATT_DATA_3.5G_DL
 PD2.Locked=true
-PD2.Signal=GPIO_Input
+PD2.Signal=GPIO_Output
 PD3.GPIOParameters=GPIO_Label
-PD3.GPIO_Label=PLL_EN_2.1G_UL
+PD3.GPIO_Label=ATT_DATA_3.5G_UL
 PD3.Locked=true
 PD3.Signal=GPIO_Output
 PD4.GPIOParameters=GPIO_Label
-PD4.GPIO_Label=PLL_EN_2.1G_DL
+PD4.GPIO_Label=ATT_DATA_3.5G_COM1
 PD4.Locked=true
 PD4.Signal=GPIO_Output
 PD5.GPIOParameters=GPIO_Label
-PD5.GPIO_Label=PATH_EN_2.1G_UL
+PD5.GPIO_Label=ATT_DATA_3.5G_COM2
 PD5.Locked=true
 PD5.Signal=GPIO_Output
 PD6.GPIOParameters=GPIO_Label
-PD6.GPIO_Label=PATH_EN_2.1G_DL
+PD6.GPIO_Label=ATT_DATA_3.5G_COM3
 PD6.Locked=true
 PD6.Signal=GPIO_Output
 PD7.GPIOParameters=GPIO_Label
-PD7.GPIO_Label=ATT_EN_2.1G_UL4
+PD7.GPIO_Label=PATH_EN_3.5G_L
 PD7.Locked=true
 PD7.Signal=GPIO_Output
 PD8.GPIOParameters=GPIO_Label
-PD8.GPIO_Label=T-SYNC_UL
-PD8.Locked=true
+PD8.GPIO_Label=PLL_DATA
 PD8.Signal=GPIO_Output
 PD9.GPIOParameters=GPIO_Label
-PD9.GPIO_Label=_T-SYNC_DL
+PD9.GPIO_Label=PLL_CLK
 PD9.Locked=true
 PD9.Signal=GPIO_Output
 PE0.GPIOParameters=GPIO_Label
-PE0.GPIO_Label=PLL_EN_1.8G_UL
+PE0.GPIO_Label=PATH_EN_2.1G_DL
 PE0.Locked=true
 PE0.Signal=GPIO_Output
 PE1.GPIOParameters=GPIO_Label
-PE1.GPIO_Label=PLL_EN_1.8G_DL
+PE1.GPIO_Label=PATH_EN_2.1G_UL
 PE1.Locked=true
 PE1.Signal=GPIO_Output
-PE11.GPIOParameters=GPIO_Label
-PE11.GPIO_Label=ATT_CLK
-PE11.Locked=true
-PE11.Signal=GPIO_Output
-PE12.GPIOParameters=GPIO_Label
-PE12.GPIO_Label=ATT_DATA
-PE12.Locked=true
-PE12.Signal=GPIO_Output
-PE13.GPIOParameters=GPIO_Label
-PE13.GPIO_Label=PLL_CLK
-PE13.Locked=true
-PE13.Signal=GPIO_Output
-PE14.GPIOParameters=GPIO_Label
-PE14.GPIO_Label=PLL_DATA
-PE14.Locked=true
-PE14.Signal=GPIO_Output
-PE15.GPIOParameters=GPIO_Label
-PE15.GPIO_Label=ALARM_DC
-PE15.Locked=true
-PE15.Signal=GPIO_Input
 PE2.GPIOParameters=GPIO_Label
 PE2.GPIO_Label=ATT_EN_1.8G_DL1
-PE2.Locked=true
 PE2.Signal=GPIO_Output
 PE3.GPIOParameters=GPIO_Label
 PE3.GPIO_Label=ATT_EN_1.8G_DL2
@@ -379,6 +307,94 @@ PE6.GPIOParameters=GPIO_Label
 PE6.GPIO_Label=ATT_EN_1.8G_UL3
 PE6.Locked=true
 PE6.Signal=GPIO_Output
+PF0.GPIOParameters=GPIO_Label
+PF0.GPIO_Label=PLL_EN_1.8G_DL
+PF0.Locked=true
+PF0.Signal=GPIO_Output
+PF1.GPIOParameters=GPIO_Label
+PF1.GPIO_Label=PLL_EN_1.8G_UL
+PF1.Locked=true
+PF1.Signal=GPIO_Output
+PF2.GPIOParameters=GPIO_Label
+PF2.GPIO_Label=PLL_LD_1.8G_DL
+PF2.Locked=true
+PF2.Signal=GPIO_Input
+PF3.GPIOParameters=GPIO_Label
+PF3.GPIO_Label=PLL_LD_1.8G_UL
+PF3.Locked=true
+PF3.Signal=GPIO_Input
+PF4.GPIOParameters=GPIO_Label
+PF4.GPIO_Label=ATT_EN_2.1G_DL1
+PF4.Locked=true
+PF4.Signal=GPIO_Output
+PF5.GPIOParameters=GPIO_Label
+PF5.GPIO_Label=ATT_EN_2.1G_DL2
+PF5.Locked=true
+PF5.Signal=GPIO_Output
+PF6.GPIOParameters=GPIO_Label
+PF6.GPIO_Label=ATT_EN_2.1G_UL1
+PF6.Locked=true
+PF6.Signal=GPIO_Output
+PF7.GPIOParameters=GPIO_Label
+PF7.GPIO_Label=ATT_EN_2.1G_UL2
+PF7.Locked=true
+PF7.Signal=GPIO_Output
+PF8.GPIOParameters=GPIO_Label
+PF8.GPIO_Label=ATT_EN_2.1G_UL3
+PF8.Locked=true
+PF8.Signal=GPIO_Output
+PF9.GPIOParameters=GPIO_Label
+PF9.GPIO_Label=ATT_EN_2.1G_UL4
+PF9.Locked=true
+PF9.Signal=GPIO_Output
+PG10.GPIOParameters=GPIO_Label
+PG10.GPIO_Label=PATH_EN_3.5G_DL
+PG10.Locked=true
+PG10.Signal=GPIO_Output
+PG11.GPIOParameters=GPIO_Label
+PG11.GPIO_Label=PATH_EN_3.5G_UL
+PG11.Locked=true
+PG11.Signal=GPIO_Output
+PG12.GPIOParameters=GPIO_Label
+PG12.GPIO_Label=PLL_ON_OFF_3.5G_L
+PG12.Locked=true
+PG12.Signal=GPIO_Output
+PG13.GPIOParameters=GPIO_Label
+PG13.GPIO_Label=PLL_ON_OFF_3.5G_H
+PG13.Locked=true
+PG13.Signal=GPIO_Output
+PG2.GPIOParameters=GPIO_Label
+PG2.GPIO_Label=DA_SYNC
+PG2.Locked=true
+PG2.Signal=GPIO_Output
+PG3.GPIOParameters=GPIO_Label
+PG3.GPIO_Label=DA_SCLK
+PG3.Locked=true
+PG3.Signal=GPIO_Output
+PG4.GPIOParameters=GPIO_Label
+PG4.GPIO_Label=DA_DIN
+PG4.Locked=true
+PG4.Signal=GPIO_Output
+PG5.GPIOParameters=GPIO_Label
+PG5.GPIO_Label=_T-SYNC_UL
+PG5.Locked=true
+PG5.Signal=GPIO_Output
+PG6.GPIOParameters=GPIO_Label
+PG6.GPIO_Label=T-SYNC_UL
+PG6.Locked=true
+PG6.Signal=GPIO_Output
+PG7.GPIOParameters=GPIO_Label
+PG7.GPIO_Label=_T-SYNC_DL
+PG7.Locked=true
+PG7.Signal=GPIO_Output
+PG8.GPIOParameters=GPIO_Label
+PG8.GPIO_Label=T-SYNC_DL
+PG8.Locked=true
+PG8.Signal=GPIO_Output
+PG9.GPIOParameters=GPIO_Label
+PG9.GPIO_Label=PATH_EN_3.5G_H
+PG9.Locked=true
+PG9.Signal=GPIO_Analog
 PinOutPanel.RotationAngle=0
 ProjectManager.AskForMigrate=true
 ProjectManager.BackupPrevious=false
@@ -388,7 +404,7 @@ ProjectManager.CoupleFile=false
 ProjectManager.CustomerFirmwarePackage=
 ProjectManager.DefaultFWLocation=true
 ProjectManager.DeletePrevious=true
-ProjectManager.DeviceId=STM32F103VGTx
+ProjectManager.DeviceId=STM32F103ZETx
 ProjectManager.FirmwarePackage=STM32Cube FW_F1 V1.7.0
 ProjectManager.FreePins=false
 ProjectManager.HalAssertFull=false
@@ -407,13 +423,31 @@ ProjectManager.TargetToolchain=TrueSTUDIO
 ProjectManager.ToolChainLocation=
 ProjectManager.UnderRoot=true
 ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_ADC1_Init-ADC1-false-HAL-true,4-MX_USART1_UART_Init-USART1-false-HAL-true
-RCC.APB1Freq_Value=8000000
-RCC.APB2Freq_Value=8000000
+RCC.ADCFreqValue=10000000
+RCC.ADCPresc=RCC_ADCPCLK2_DIV6
+RCC.AHBFreq_Value=60000000
+RCC.APB1CLKDivider=RCC_HCLK_DIV2
+RCC.APB1Freq_Value=30000000
+RCC.APB1TimFreq_Value=60000000
+RCC.APB2Freq_Value=60000000
+RCC.APB2TimFreq_Value=60000000
+RCC.FCLKCortexFreq_Value=60000000
+RCC.FSMCFreq_Value=60000000
 RCC.FamilyName=M
-RCC.IPParameters=APB1Freq_Value,APB2Freq_Value,FamilyName,PLLCLKFreq_Value,PLLMCOFreq_Value,TimSysFreq_Value
-RCC.PLLCLKFreq_Value=8000000
-RCC.PLLMCOFreq_Value=4000000
-RCC.TimSysFreq_Value=8000000
+RCC.HCLKFreq_Value=60000000
+RCC.I2S2Freq_Value=60000000
+RCC.I2S3Freq_Value=60000000
+RCC.IPParameters=ADCFreqValue,ADCPresc,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FSMCFreq_Value,FamilyName,HCLKFreq_Value,I2S2Freq_Value,I2S3Freq_Value,MCOFreq_Value,PLLCLKFreq_Value,PLLMCOFreq_Value,PLLMUL,SDIOFreq_Value,SDIOHCLKDiv2FreqValue,SYSCLKFreq_VALUE,SYSCLKSource,TimSysFreq_Value,USBFreq_Value
+RCC.MCOFreq_Value=60000000
+RCC.PLLCLKFreq_Value=60000000
+RCC.PLLMCOFreq_Value=30000000
+RCC.PLLMUL=RCC_PLL_MUL15
+RCC.SDIOFreq_Value=60000000
+RCC.SDIOHCLKDiv2FreqValue=30000000
+RCC.SYSCLKFreq_VALUE=60000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.TimSysFreq_Value=60000000
+RCC.USBFreq_Value=60000000
 SH.ADCx_IN0.0=ADC1_IN0,IN0
 SH.ADCx_IN0.ConfNb=1
 SH.ADCx_IN1.0=ADC1_IN1,IN1

STM32F103_ATTEN_PLL_Zig.txt

@@ -0,0 +1,222 @@
+Configuration	STM32F103_ATTEN_PLL_Zig
+STM32CubeMX 	5.2.1
+Date	07/01/2019
+MCU	STM32F103ZETx
+
+
+
+PERIPHERALS	MODES	FUNCTIONS	PINS
+ADC1	IN0	ADC1_IN0	PA0-WKUP
+ADC1	IN1	ADC1_IN1	PA1
+ADC1	IN2	ADC1_IN2	PA2
+ADC1	IN3	ADC1_IN3	PA3
+ADC1	IN4	ADC1_IN4	PA4
+ADC1	IN5	ADC1_IN5	PA5
+ADC1	IN6	ADC1_IN6	PA6
+ADC1	IN7	ADC1_IN7	PA7
+ADC1	IN8	ADC1_IN8	PB0
+ADC1	IN9	ADC1_IN9	PB1
+ADC1	IN10	ADC1_IN10	PC0
+ADC1	IN11	ADC1_IN11	PC1
+ADC1	IN12	ADC1_IN12	PC2
+ADC1	IN13	ADC1_IN13	PC3
+SYS	No Debug	SYS_VS_ND	VP_SYS_VS_ND
+SYS	SysTick	SYS_VS_Systick	VP_SYS_VS_Systick
+USART1	Asynchronous	USART1_RX	PA10
+USART1	Asynchronous	USART1_TX	PA9
+
+
+
+Pin Nb	PINs	FUNCTIONs	LABELs
+1	PE2	GPIO_Output	ATT_EN_1.8G_DL1
+2	PE3	GPIO_Output	ATT_EN_1.8G_DL2
+3	PE4	GPIO_Output	ATT_EN_1.8G_UL1
+4	PE5	GPIO_Output	ATT_EN_1.8G_UL2
+5	PE6	GPIO_Output	ATT_EN_1.8G_UL3
+7	PC13-TAMPER-RTC	GPIO_Output	ATT_EN_1.8G_UL4
+8	PC14-OSC32_IN	GPIO_Output	PATH_EN_1.8G_DL
+9	PC15-OSC32_OUT	GPIO_Output	PATH_EN_1.8G_UL
+10	PF0	GPIO_Output	PLL_EN_1.8G_DL
+11	PF1	GPIO_Output	PLL_EN_1.8G_UL
+12	PF2	GPIO_Input	PLL_LD_1.8G_DL
+13	PF3	GPIO_Input	PLL_LD_1.8G_UL
+14	PF4	GPIO_Output	ATT_EN_2.1G_DL1
+15	PF5	GPIO_Output	ATT_EN_2.1G_DL2
+18	PF6	GPIO_Output	ATT_EN_2.1G_UL1
+19	PF7	GPIO_Output	ATT_EN_2.1G_UL2
+20	PF8	GPIO_Output	ATT_EN_2.1G_UL3
+21	PF9	GPIO_Output	ATT_EN_2.1G_UL4
+26	PC0	ADC1_IN10	DET_3.5G_UL_IN
+27	PC1	ADC1_IN11	DET_3.5G_UL_OUT
+28	PC2	ADC1_IN12	RFU_TEMP
+29	PC3	ADC1_IN13	_28V_DET
+34	PA0-WKUP	ADC1_IN0	DET_1.8G_DL_IN
+35	PA1	ADC1_IN1	DET_1.8G_DL_OUT
+36	PA2	ADC1_IN2	DET_1.8G_UL_IN
+37	PA3	ADC1_IN3	DET_1.8G_UL_OUT
+40	PA4	ADC1_IN4	DET_2.1G_DL_IN
+41	PA5	ADC1_IN5	DET_2.1G_DL_OUT
+42	PA6	ADC1_IN6	DET_2.1G_UL_IN
+43	PA7	ADC1_IN7	DET_2.1G_UL_OUT
+46	PB0	ADC1_IN8	DET_3.5G_DL_IN
+47	PB1	ADC1_IN9	DET_3.5G_DL_OUT
+77	PD8	GPIO_Output	PLL_DATA
+78	PD9	GPIO_Output	PLL_CLK
+79	PD10	GPIO_Output	ATT_DATA
+80	PD11	GPIO_Output	ATT_CLK
+81	PD12	GPIO_Input	ALARM_DC
+82	PD13	GPIO_Input	ALARM_AC
+86	PD15	GPIO_Output	DA_LDAC
+87	PG2	GPIO_Output	DA_SYNC
+88	PG3	GPIO_Output	DA_SCLK
+89	PG4	GPIO_Output	DA_DIN
+90	PG5	GPIO_Output	_T-SYNC_UL
+91	PG6	GPIO_Output	T-SYNC_UL
+92	PG7	GPIO_Output	_T-SYNC_DL
+93	PG8	GPIO_Output	T-SYNC_DL
+96	PC6	GPIO_Output	PLL_EN_3.5G_L
+97	PC7	GPIO_Output	PLL_EN_3.5G_H
+98	PC8	GPIO_Input	PLL_LD_3.5G_L
+99	PC9	GPIO_Input	PLL_LD_3.5G_H
+101	PA9	USART1_TX	
+102	PA10	USART1_RX	
+114	PD0	GPIO_Output	ATT_CLK_3.5G
+115	PD1	GPIO_Output	ATT_EN_3.5G
+116	PD2	GPIO_Output	ATT_DATA_3.5G_DL
+117	PD3	GPIO_Output	ATT_DATA_3.5G_UL
+118	PD4	GPIO_Output	ATT_DATA_3.5G_COM1
+119	PD5	GPIO_Output	ATT_DATA_3.5G_COM2
+122	PD6	GPIO_Output	ATT_DATA_3.5G_COM3
+123	PD7	GPIO_Output	PATH_EN_3.5G_L
+124	PG9	GPIO_Analog	PATH_EN_3.5G_H
+125	PG10	GPIO_Output	PATH_EN_3.5G_DL
+126	PG11	GPIO_Output	PATH_EN_3.5G_UL
+127	PG12	GPIO_Output	PLL_ON_OFF_3.5G_L
+128	PG13	GPIO_Output	PLL_ON_OFF_3.5G_H
+133	PB3	GPIO_Output	PLL_EN_2.1G_DL
+134	PB4	GPIO_Output	PLL_EN_2.1G_UL
+135	PB5	GPIO_Input	PLL_LD_2.1G_DL
+136	PB6	GPIO_Input	PLL_LD_2.1G_UL
+141	PE0	GPIO_Output	PATH_EN_2.1G_DL
+142	PE1	GPIO_Output	PATH_EN_2.1G_UL
+PERIPHERALS	MODES	FUNCTIONS	PINS
+ADC1	IN0	ADC1_IN0	PA0-WKUP
+ADC1	IN1	ADC1_IN1	PA1
+ADC1	IN2	ADC1_IN2	PA2
+ADC1	IN3	ADC1_IN3	PA3
+ADC1	IN4	ADC1_IN4	PA4
+ADC1	IN5	ADC1_IN5	PA5
+ADC1	IN6	ADC1_IN6	PA6
+ADC1	IN7	ADC1_IN7	PA7
+ADC1	IN8	ADC1_IN8	PB0
+ADC1	IN9	ADC1_IN9	PB1
+ADC1	IN10	ADC1_IN10	PC0
+ADC1	IN11	ADC1_IN11	PC1
+ADC1	IN12	ADC1_IN12	PC2
+ADC1	IN13	ADC1_IN13	PC3
+SYS	No Debug	SYS_VS_ND	VP_SYS_VS_ND
+SYS	SysTick	SYS_VS_Systick	VP_SYS_VS_Systick
+USART1	Asynchronous	USART1_RX	PA10
+USART1	Asynchronous	USART1_TX	PA9
+
+
+
+Pin Nb	PINs	FUNCTIONs	LABELs
+1	PE2	GPIO_Output	ATT_EN_1.8G_DL1
+2	PE3	GPIO_Output	ATT_EN_1.8G_DL2
+3	PE4	GPIO_Output	ATT_EN_1.8G_UL1
+4	PE5	GPIO_Output	ATT_EN_1.8G_UL2
+5	PE6	GPIO_Output	ATT_EN_1.8G_UL3
+7	PC13-TAMPER-RTC	GPIO_Output	ATT_EN_1.8G_UL4
+8	PC14-OSC32_IN	GPIO_Output	PATH_EN_1.8G_DL
+9	PC15-OSC32_OUT	GPIO_Output	PATH_EN_1.8G_UL
+10	PF0	GPIO_Output	PLL_EN_1.8G_DL
+11	PF1	GPIO_Output	PLL_EN_1.8G_UL
+12	PF2	GPIO_Input	PLL_LD_1.8G_DL
+13	PF3	GPIO_Input	PLL_LD_1.8G_UL
+14	PF4	GPIO_Output	ATT_EN_2.1G_DL1
+15	PF5	GPIO_Output	ATT_EN_2.1G_DL2
+18	PF6	GPIO_Output	ATT_EN_2.1G_UL1
+19	PF7	GPIO_Output	ATT_EN_2.1G_UL2
+20	PF8	GPIO_Output	ATT_EN_2.1G_UL3
+21	PF9	GPIO_Output	ATT_EN_2.1G_UL4
+26	PC0	ADC1_IN10	DET_3.5G_UL_IN
+27	PC1	ADC1_IN11	DET_3.5G_UL_OUT
+28	PC2	ADC1_IN12	RFU_TEMP
+29	PC3	ADC1_IN13	_28V_DET
+34	PA0-WKUP	ADC1_IN0	DET_1.8G_DL_IN
+35	PA1	ADC1_IN1	DET_1.8G_DL_OUT
+36	PA2	ADC1_IN2	DET_1.8G_UL_IN
+37	PA3	ADC1_IN3	DET_1.8G_UL_OUT
+40	PA4	ADC1_IN4	DET_2.1G_DL_IN
+41	PA5	ADC1_IN5	DET_2.1G_DL_OUT
+42	PA6	ADC1_IN6	DET_2.1G_UL_IN
+43	PA7	ADC1_IN7	DET_2.1G_UL_OUT
+46	PB0	ADC1_IN8	DET_3.5G_DL_IN
+47	PB1	ADC1_IN9	DET_3.5G_DL_OUT
+77	PD8	GPIO_Output	PLL_DATA
+78	PD9	GPIO_Output	PLL_CLK
+79	PD10	GPIO_Output	ATT_DATA
+80	PD11	GPIO_Output	ATT_CLK
+81	PD12	GPIO_Input	ALARM_DC
+82	PD13	GPIO_Input	ALARM_AC
+86	PD15	GPIO_Output	DA_LDAC
+87	PG2	GPIO_Output	DA_SYNC
+88	PG3	GPIO_Output	DA_SCLK
+89	PG4	GPIO_Output	DA_DIN
+90	PG5	GPIO_Output	_T-SYNC_UL
+91	PG6	GPIO_Output	T-SYNC_UL
+92	PG7	GPIO_Output	_T-SYNC_DL
+93	PG8	GPIO_Output	T-SYNC_DL
+96	PC6	GPIO_Output	PLL_EN_3.5G_L
+97	PC7	GPIO_Output	PLL_EN_3.5G_H
+98	PC8	GPIO_Input	PLL_LD_3.5G_L
+99	PC9	GPIO_Input	PLL_LD_3.5G_H
+101	PA9	USART1_TX	
+102	PA10	USART1_RX	
+114	PD0	GPIO_Output	ATT_CLK_3.5G
+115	PD1	GPIO_Output	ATT_EN_3.5G
+116	PD2	GPIO_Output	ATT_DATA_3.5G_DL
+117	PD3	GPIO_Output	ATT_DATA_3.5G_UL
+118	PD4	GPIO_Output	ATT_DATA_3.5G_COM1
+119	PD5	GPIO_Output	ATT_DATA_3.5G_COM2
+122	PD6	GPIO_Output	ATT_DATA_3.5G_COM3
+123	PD7	GPIO_Output	PATH_EN_3.5G_L
+124	PG9	GPIO_Analog	PATH_EN_3.5G_H
+125	PG10	GPIO_Output	PATH_EN_3.5G_DL
+126	PG11	GPIO_Output	PATH_EN_3.5G_UL
+127	PG12	GPIO_Output	PLL_ON_OFF_3.5G_L
+128	PG13	GPIO_Output	PLL_ON_OFF_3.5G_H
+133	PB3	GPIO_Output	PLL_EN_2.1G_DL
+134	PB4	GPIO_Output	PLL_EN_2.1G_UL
+135	PB5	GPIO_Input	PLL_LD_2.1G_DL
+136	PB6	GPIO_Input	PLL_LD_2.1G_UL
+141	PE0	GPIO_Output	PATH_EN_2.1G_DL
+142	PE1	GPIO_Output	PATH_EN_2.1G_UL
+
+
+
+SOFTWARE PROJECT
+
+Project Settings : 
+Project Name : STM32F103_ATTEN_PLL_Zig
+Project Folder : D:\workspace\STM32F103_ATTEN_PLL_Zig
+Toolchain / IDE : TrueSTUDIO
+Firmware Package Name and Version : STM32Cube FW_F1 V1.7.0
+
+
+Code Generation Settings : 
+STM32Cube Firmware Library Package : Copy only the necessary library files
+Generate peripheral initialization as a pair of '.c/.h' files per peripheral : No
+Backup previously generated files when re-generating : No
+Delete previously generated files when not re-generated : Yes
+Set all free pins as analog (to optimize the power consumption) : No
+
+
+Toolchains Settings : 
+Compiler Optimizations : 
+
+
+
+
+

Src/BDA4601.c

@@ -0,0 +1,8 @@
+/*
+ * BDA4601.c
+ *
+ *  Created on: 2019. 6. 28.
+ *      Author: parkyj
+ */
+
+

Src/PE43711.c

@@ -0,0 +1,105 @@
+/*
+ * PE43711.c
+ *
+ *  Created on: 2019. 6. 28.
+ *      Author: parkyj
+ */
+ #include "PE43711.h"
+ typedef struct{
+    uint16_t ATT_EN_1_8G_DL1_PIN;
+    GPIO_TypeDef *ATT_EN_1_8G_DL1_PORT;
+        
+    uint16_t ATT_EN_1_8G_DL2_PIN;
+    GPIO_TypeDef *ATT_EN_1_8G_DL2_PORT;
+
+    uint16_t ATT_EN_1_8G_UL1_PIN;
+    GPIO_TypeDef *ATT_EN_1_8G_UL1_PORT;
+
+    uint16_t ATT_EN_1_8G_UL2_PIN;
+    GPIO_TypeDef *ATT_EN_1_8G_UL2_PORT;
+
+    uint16_t ATT_EN_1_8G_UL3_PIN;
+    GPIO_TypeDef *ATT_EN_1_8G_UL3_PORT;
+
+    uint16_t ATT_EN_1_8G_UL4_PIN;
+    GPIO_TypeDef *ATT_EN_1_8G_UL4_PORT;
+ }PE43711_st;
+
+PE43711_st *Atten_1_8Ghz; 
+PE43711_st *Atten_2_1Ghz; 
+
+ 
+void PE43711_PinInit(void){
+    Atten_1_8Ghz->ATT_EN_1_8G_DL1_PIN = GPIO_PIN_1;
+    Atten_1_8Ghz->ATT_EN_1_8G_DL1_PORT = GPIOB;
+    
+    Atten_1_8Ghz->ATT_EN_1_8G_DL2_PIN = GPIO_PIN_1;
+    Atten_1_8Ghz->ATT_EN_1_8G_DL2_PORT = GPIOB;
+    
+    Atten_1_8Ghz->ATT_EN_1_8G_UL1_PIN = GPIO_PIN_1;
+    Atten_1_8Ghz->ATT_EN_1_8G_UL1_PORT = GPIOB;
+    
+    Atten_1_8Ghz->ATT_EN_1_8G_DL1_PIN = GPIO_PIN_1;
+    Atten_1_8Ghz->ATT_EN_1_8G_DL1_PORT = GPIOB;
+    
+    Atten_1_8Ghz->ATT_EN_1_8G_UL2_PIN = GPIO_PIN_1;
+    Atten_1_8Ghz->ATT_EN_1_8G_UL2_PORT = GPIOB;
+
+    Atten_1_8Ghz->ATT_EN_1_8G_UL3_PIN = GPIO_PIN_1;
+    Atten_1_8Ghz->ATT_EN_1_8G_UL3_PORT = GPIOB;
+    
+    Atten_1_8Ghz->ATT_EN_1_8G_UL4_PIN = GPIO_PIN_1;
+    Atten_1_8Ghz->ATT_EN_1_8G_UL4_PORT = GPIOB;
+
+
+    Atten_2_1Ghz->ATT_EN_1_8G_DL1_PIN = GPIO_PIN_1;
+    Atten_2_1Ghz->ATT_EN_1_8G_DL1_PORT = GPIOB;
+
+    Atten_2_1Ghz->ATT_EN_1_8G_DL2_PIN = GPIO_PIN_1;
+    Atten_2_1Ghz->ATT_EN_1_8G_DL2_PORT = GPIOB;
+
+    Atten_2_1Ghz->ATT_EN_1_8G_UL1_PIN = GPIO_PIN_1;
+    Atten_2_1Ghz->ATT_EN_1_8G_UL1_PORT = GPIOB;
+
+    Atten_2_1Ghz->ATT_EN_1_8G_DL1_PIN = GPIO_PIN_1;
+    Atten_2_1Ghz->ATT_EN_1_8G_DL1_PORT = GPIOB;
+
+    Atten_2_1Ghz->ATT_EN_1_8G_UL2_PIN = GPIO_PIN_1;
+    Atten_2_1Ghz->ATT_EN_1_8G_UL2_PORT = GPIOB;
+
+    Atten_2_1Ghz->ATT_EN_1_8G_UL3_PIN = GPIO_PIN_1;
+    Atten_2_1Ghz->ATT_EN_1_8G_UL3_PORT = GPIOB;
+
+    Atten_2_1Ghz->ATT_EN_1_8G_UL4_PIN = GPIO_PIN_1;
+    Atten_2_1Ghz->ATT_EN_1_8G_UL4_PORT = GPIOB;
+    
+}
+
+void PE43711_atten_ctrl(PE43711_st* type ,double data){
+    uint8_t i = 0;
+    uint8_t temp = 0;
+    data = 4 * data;
+    temp = (uint8_t)data;
+    HAL_GPIO_WritePin(GPIOB,GPIO_PIN_1,GPIO_PIN_RESET);
+    HAL_Delay(1);
+    for(i = 0; i < 8; i++){
+        if((uint8_t)temp & 0x01){
+           HAL_GPIO_WritePin(GPIOB,GPIO_PIN_15,GPIO_PIN_SET);//DATA
+        }
+           else{
+           HAL_GPIO_WritePin(GPIOB,GPIO_PIN_15,GPIO_PIN_RESET);//DATA
+           }
+
+		HAL_GPIO_WritePin(GPIOB,GPIO_PIN_2,GPIO_PIN_SET);//CLOCK
+		HAL_Delay(1);
+		HAL_GPIO_WritePin(GPIOB,GPIO_PIN_2,GPIO_PIN_RESET);//CLOCK
+		HAL_Delay(1);
+		temp >>= 1;
+    }
+	HAL_GPIO_WritePin(GPIOB,GPIO_PIN_2,GPIO_PIN_RESET);//CLOCK
+    HAL_GPIO_WritePin(GPIOB,GPIO_PIN_15,GPIO_PIN_RESET);//DATA
+    HAL_Delay(5);
+    HAL_GPIO_WritePin(GPIOB,GPIO_PIN_1,GPIO_PIN_SET);//LE
+    HAL_Delay(1);
+    HAL_GPIO_WritePin(GPIOB,GPIO_PIN_1,GPIO_PIN_RESET);
+}

Src/main.c

@@ -43,6 +43,7 @@
 
 /* Private variables ---------------------------------------------------------*/
 ADC_HandleTypeDef hadc1;
+DMA_HandleTypeDef hdma_adc1;
 
 UART_HandleTypeDef huart1;
 
@@ -53,8 +54,10 @@ UART_HandleTypeDef huart1;
 /* Private function prototypes -----------------------------------------------*/
 void SystemClock_Config(void);
 static void MX_GPIO_Init(void);
+static void MX_DMA_Init(void);
 static void MX_ADC1_Init(void);
 static void MX_USART1_UART_Init(void);
+static void MX_NVIC_Init(void);
 /* USER CODE BEGIN PFP */
 
 /* USER CODE END PFP */
@@ -93,8 +96,12 @@ int main(void)
 
   /* Initialize all configured peripherals */
   MX_GPIO_Init();
+  MX_DMA_Init();
   MX_ADC1_Init();
   MX_USART1_UART_Init();
+
+  /* Initialize interrupts */
+  MX_NVIC_Init();
   /* USER CODE BEGIN 2 */
 
   /* USER CODE END 2 */
@@ -125,7 +132,9 @@ void SystemClock_Config(void)
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
   RCC_OscInitStruct.HSIState = RCC_HSI_ON;
   RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2;
+  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL15;
   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
   {
     Error_Handler();
@@ -134,23 +143,34 @@ void SystemClock_Config(void)
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
   RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
 
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
   {
     Error_Handler();
   }
   PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
-  PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV2;
+  PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6;
   if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
   {
     Error_Handler();
   }
 }
 
+/**
+  * @brief NVIC Configuration.
+  * @retval None
+  */
+static void MX_NVIC_Init(void)
+{
+  /* USART1_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(USART1_IRQn);
+}
+
 /**
   * @brief ADC1 Initialization Function
   * @param None
@@ -171,12 +191,12 @@ static void MX_ADC1_Init(void)
   /** Common config 
   */
   hadc1.Instance = ADC1;
-  hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
+  hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE;
   hadc1.Init.ContinuousConvMode = DISABLE;
   hadc1.Init.DiscontinuousConvMode = DISABLE;
   hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
   hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
-  hadc1.Init.NbrOfConversion = 1;
+  hadc1.Init.NbrOfConversion = 2;
   if (HAL_ADC_Init(&hadc1) != HAL_OK)
   {
     Error_Handler();
@@ -190,6 +210,13 @@ static void MX_ADC1_Init(void)
   {
     Error_Handler();
   }
+  /** Configure Regular Channel 
+  */
+  sConfig.Rank = ADC_REGULAR_RANK_2;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
   /* USER CODE BEGIN ADC1_Init 2 */
 
   /* USER CODE END ADC1_Init 2 */
@@ -229,6 +256,21 @@ static void MX_USART1_UART_Init(void)
 
 }
 
+/** 
+  * Enable DMA controller clock
+  */
+static void MX_DMA_Init(void) 
+{
+  /* DMA controller clock enable */
+  __HAL_RCC_DMA1_CLK_ENABLE();
+
+  /* DMA interrupt init */
+  /* DMA1_Channel1_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
+
+}
+
 /**
   * @brief GPIO Initialization Function
   * @param None
@@ -241,104 +283,124 @@ static void MX_GPIO_Init(void)
   /* GPIO Ports Clock Enable */
   __HAL_RCC_GPIOE_CLK_ENABLE();
   __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOF_CLK_ENABLE();
   __HAL_RCC_GPIOA_CLK_ENABLE();
   __HAL_RCC_GPIOB_CLK_ENABLE();
   __HAL_RCC_GPIOD_CLK_ENABLE();
+  __HAL_RCC_GPIOG_CLK_ENABLE();
 
   /*Configure GPIO pin Output Level */
   HAL_GPIO_WritePin(GPIOE, ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin 
-                          |ATT_EN_1_8G_UL3_Pin|ATT_CLK_Pin|ATT_DATA_Pin|PLL_CLK_Pin 
-                          |PLL_DATA_Pin|PLL_EN_1_8G_UL_Pin|PLL_EN_1_8G_DL_Pin, GPIO_PIN_RESET);
+                          |ATT_EN_1_8G_UL3_Pin|PATH_EN_2_1G_DL_Pin|PATH_EN_2_1G_UL_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOC, ATT_EN_1_8G_UL4_Pin|PATH_EN_1_8G_DL_Pin|PATH_EN_1_8G_UL_Pin|PLL_EN_3_5G_L_Pin 
+                          |PLL_EN_3_5G_H_Pin, GPIO_PIN_RESET);
 
   /*Configure GPIO pin Output Level */
-  HAL_GPIO_WritePin(GPIOC, ATT_EN_1_8G_UL4_Pin|PATH_EN_1_8G_DL_Pin|PATH_EN_1_8G_UL_Pin|PLL_ON_OFF_3_5G_L_Pin 
-                          |PATH_EN_3_5G_UL_Pin|PATH_EN_3_5G_DL_Pin|PATH_EN_3_5G_H_Pin|ATT_DATA_3_5G_DL_Pin 
-                          |ATT_EN_3_5G_Pin|ATT_CLK_3_5G_Pin, GPIO_PIN_RESET);
+  HAL_GPIO_WritePin(GPIOF, PLL_EN_1_8G_DL_Pin|PLL_EN_1_8G_UL_Pin|ATT_EN_2_1G_DL1_Pin|ATT_EN_2_1G_DL2_Pin 
+                          |ATT_EN_2_1G_UL1_Pin|ATT_EN_2_1G_UL2_Pin|ATT_EN_2_1G_UL3_Pin|ATT_EN_2_1G_UL4_Pin, GPIO_PIN_RESET);
 
   /*Configure GPIO pin Output Level */
-  HAL_GPIO_WritePin(GPIOB, DA_LDAC_Pin|DA_SYNC_Pin|DA_SCLK_Pin|DA_DIN_Pin 
-                          |_T_SYNC_UL_Pin|ATT_EN_2_1G_UL3_Pin|ATT_EN_2_1G_UL2_Pin|ATT_EN_2_1G_UL1_Pin 
-                          |ATT_EN_2_1G_DL2_Pin|ATT_EN_2_1G_DL1_Pin, GPIO_PIN_RESET);
+  HAL_GPIO_WritePin(GPIOD, PLL_DATA_Pin|PLL_CLK_Pin|ATT_DATA_Pin|ATT_CLK_Pin 
+                          |DA_LDAC_Pin|ATT_CLK_3_5G_Pin|ATT_EN_3_5G_Pin|ATT_DATA_3_5G_DL_Pin 
+                          |ATT_DATA_3_5G_UL_Pin|ATT_DATA_3_5G_COM1_Pin|ATT_DATA_3_5G_COM2_Pin|ATT_DATA_3_5G_COM3_Pin 
+                          |PATH_EN_3_5G_L_Pin, GPIO_PIN_RESET);
 
   /*Configure GPIO pin Output Level */
-  HAL_GPIO_WritePin(GPIOD, T_SYNC_UL_Pin|_T_SYNC_DL_Pin|T_SYNC_DL_Pin|PLL_EN_3_5G_H_Pin 
-                          |PLL_EN_3_5G_L_Pin|PLL_ON_OFF_3_5G_H_Pin|PLL_EN_2_1G_UL_Pin|PLL_EN_2_1G_DL_Pin 
-                          |PATH_EN_2_1G_UL_Pin|PATH_EN_2_1G_DL_Pin|ATT_EN_2_1G_UL4_Pin, GPIO_PIN_RESET);
+  HAL_GPIO_WritePin(GPIOG, DA_SYNC_Pin|DA_SCLK_Pin|DA_DIN_Pin|_T_SYNC_UL_Pin 
+                          |T_SYNC_UL_Pin|_T_SYNC_DL_Pin|T_SYNC_DL_Pin|PATH_EN_3_5G_DL_Pin 
+                          |PATH_EN_3_5G_UL_Pin|PLL_ON_OFF_3_5G_L_Pin|PLL_ON_OFF_3_5G_H_Pin, GPIO_PIN_RESET);
 
   /*Configure GPIO pin Output Level */
-  HAL_GPIO_WritePin(GPIOA, PATH_EN_3_5G_L_Pin|ATT_DATA_3_5G_COM3_Pin|ATT_DATA_3_5G_COM2_Pin|ATT_DATA_3_5G_COM1_Pin 
-                          |ATT_DATA_3_5G_UL_Pin, GPIO_PIN_RESET);
+  HAL_GPIO_WritePin(GPIOB, PLL_EN_2_1G_DL_Pin|PLL_EN_2_1G_UL_Pin, GPIO_PIN_RESET);
 
   /*Configure GPIO pins : ATT_EN_1_8G_DL1_Pin ATT_EN_1_8G_DL2_Pin ATT_EN_1_8G_UL1_Pin ATT_EN_1_8G_UL2_Pin 
-                           ATT_EN_1_8G_UL3_Pin ATT_CLK_Pin ATT_DATA_Pin PLL_CLK_Pin 
-                           PLL_DATA_Pin PLL_EN_1_8G_UL_Pin PLL_EN_1_8G_DL_Pin */
+                           ATT_EN_1_8G_UL3_Pin PATH_EN_2_1G_DL_Pin PATH_EN_2_1G_UL_Pin */
   GPIO_InitStruct.Pin = ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin 
-                          |ATT_EN_1_8G_UL3_Pin|ATT_CLK_Pin|ATT_DATA_Pin|PLL_CLK_Pin 
-                          |PLL_DATA_Pin|PLL_EN_1_8G_UL_Pin|PLL_EN_1_8G_DL_Pin;
+                          |ATT_EN_1_8G_UL3_Pin|PATH_EN_2_1G_DL_Pin|PATH_EN_2_1G_UL_Pin;
   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
   GPIO_InitStruct.Pull = GPIO_NOPULL;
   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
   HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
 
-  /*Configure GPIO pins : ATT_EN_1_8G_UL4_Pin PATH_EN_1_8G_DL_Pin PATH_EN_1_8G_UL_Pin PLL_ON_OFF_3_5G_L_Pin 
-                           PATH_EN_3_5G_UL_Pin PATH_EN_3_5G_DL_Pin PATH_EN_3_5G_H_Pin ATT_DATA_3_5G_DL_Pin 
-                           ATT_EN_3_5G_Pin ATT_CLK_3_5G_Pin */
-  GPIO_InitStruct.Pin = ATT_EN_1_8G_UL4_Pin|PATH_EN_1_8G_DL_Pin|PATH_EN_1_8G_UL_Pin|PLL_ON_OFF_3_5G_L_Pin 
-                          |PATH_EN_3_5G_UL_Pin|PATH_EN_3_5G_DL_Pin|PATH_EN_3_5G_H_Pin|ATT_DATA_3_5G_DL_Pin 
-                          |ATT_EN_3_5G_Pin|ATT_CLK_3_5G_Pin;
+  /*Configure GPIO pins : ATT_EN_1_8G_UL4_Pin PATH_EN_1_8G_DL_Pin PATH_EN_1_8G_UL_Pin PLL_EN_3_5G_L_Pin 
+                           PLL_EN_3_5G_H_Pin */
+  GPIO_InitStruct.Pin = ATT_EN_1_8G_UL4_Pin|PATH_EN_1_8G_DL_Pin|PATH_EN_1_8G_UL_Pin|PLL_EN_3_5G_L_Pin 
+                          |PLL_EN_3_5G_H_Pin;
   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
   GPIO_InitStruct.Pull = GPIO_NOPULL;
   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
   HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 
-  /*Configure GPIO pin : ALARM_DC_Pin */
-  GPIO_InitStruct.Pin = ALARM_DC_Pin;
-  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  /*Configure GPIO pins : PLL_EN_1_8G_DL_Pin PLL_EN_1_8G_UL_Pin ATT_EN_2_1G_DL1_Pin ATT_EN_2_1G_DL2_Pin 
+                           ATT_EN_2_1G_UL1_Pin ATT_EN_2_1G_UL2_Pin ATT_EN_2_1G_UL3_Pin ATT_EN_2_1G_UL4_Pin */
+  GPIO_InitStruct.Pin = PLL_EN_1_8G_DL_Pin|PLL_EN_1_8G_UL_Pin|ATT_EN_2_1G_DL1_Pin|ATT_EN_2_1G_DL2_Pin 
+                          |ATT_EN_2_1G_UL1_Pin|ATT_EN_2_1G_UL2_Pin|ATT_EN_2_1G_UL3_Pin|ATT_EN_2_1G_UL4_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
   GPIO_InitStruct.Pull = GPIO_NOPULL;
-  HAL_GPIO_Init(ALARM_DC_GPIO_Port, &GPIO_InitStruct);
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
 
-  /*Configure GPIO pins : ALARM_AC_Pin PLL_LD_1_8G_UL_Pin PLL_LD_1_8G_DL_Pin */
-  GPIO_InitStruct.Pin = ALARM_AC_Pin|PLL_LD_1_8G_UL_Pin|PLL_LD_1_8G_DL_Pin;
+  /*Configure GPIO pins : PLL_LD_1_8G_DL_Pin PLL_LD_1_8G_UL_Pin */
+  GPIO_InitStruct.Pin = PLL_LD_1_8G_DL_Pin|PLL_LD_1_8G_UL_Pin;
   GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
   GPIO_InitStruct.Pull = GPIO_NOPULL;
-  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
-
-  /*Configure GPIO pins : DA_LDAC_Pin DA_SYNC_Pin DA_SCLK_Pin DA_DIN_Pin 
-                           _T_SYNC_UL_Pin ATT_EN_2_1G_UL3_Pin ATT_EN_2_1G_UL2_Pin ATT_EN_2_1G_UL1_Pin 
-                           ATT_EN_2_1G_DL2_Pin ATT_EN_2_1G_DL1_Pin */
-  GPIO_InitStruct.Pin = DA_LDAC_Pin|DA_SYNC_Pin|DA_SCLK_Pin|DA_DIN_Pin 
-                          |_T_SYNC_UL_Pin|ATT_EN_2_1G_UL3_Pin|ATT_EN_2_1G_UL2_Pin|ATT_EN_2_1G_UL1_Pin 
-                          |ATT_EN_2_1G_DL2_Pin|ATT_EN_2_1G_DL1_Pin;
+  HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : PLL_DATA_Pin PLL_CLK_Pin ATT_DATA_Pin ATT_CLK_Pin 
+                           DA_LDAC_Pin ATT_CLK_3_5G_Pin ATT_EN_3_5G_Pin ATT_DATA_3_5G_DL_Pin 
+                           ATT_DATA_3_5G_UL_Pin ATT_DATA_3_5G_COM1_Pin ATT_DATA_3_5G_COM2_Pin ATT_DATA_3_5G_COM3_Pin 
+                           PATH_EN_3_5G_L_Pin */
+  GPIO_InitStruct.Pin = PLL_DATA_Pin|PLL_CLK_Pin|ATT_DATA_Pin|ATT_CLK_Pin 
+                          |DA_LDAC_Pin|ATT_CLK_3_5G_Pin|ATT_EN_3_5G_Pin|ATT_DATA_3_5G_DL_Pin 
+                          |ATT_DATA_3_5G_UL_Pin|ATT_DATA_3_5G_COM1_Pin|ATT_DATA_3_5G_COM2_Pin|ATT_DATA_3_5G_COM3_Pin 
+                          |PATH_EN_3_5G_L_Pin;
   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
   GPIO_InitStruct.Pull = GPIO_NOPULL;
   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
-  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : ALARM_DC_Pin ALARM_AC_Pin */
+  GPIO_InitStruct.Pin = ALARM_DC_Pin|ALARM_AC_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
 
-  /*Configure GPIO pins : T_SYNC_UL_Pin _T_SYNC_DL_Pin T_SYNC_DL_Pin PLL_EN_3_5G_H_Pin 
-                           PLL_EN_3_5G_L_Pin PLL_ON_OFF_3_5G_H_Pin PLL_EN_2_1G_UL_Pin PLL_EN_2_1G_DL_Pin 
-                           PATH_EN_2_1G_UL_Pin PATH_EN_2_1G_DL_Pin ATT_EN_2_1G_UL4_Pin */
-  GPIO_InitStruct.Pin = T_SYNC_UL_Pin|_T_SYNC_DL_Pin|T_SYNC_DL_Pin|PLL_EN_3_5G_H_Pin 
-                          |PLL_EN_3_5G_L_Pin|PLL_ON_OFF_3_5G_H_Pin|PLL_EN_2_1G_UL_Pin|PLL_EN_2_1G_DL_Pin 
-                          |PATH_EN_2_1G_UL_Pin|PATH_EN_2_1G_DL_Pin|ATT_EN_2_1G_UL4_Pin;
+  /*Configure GPIO pins : DA_SYNC_Pin DA_SCLK_Pin DA_DIN_Pin _T_SYNC_UL_Pin 
+                           T_SYNC_UL_Pin _T_SYNC_DL_Pin T_SYNC_DL_Pin PATH_EN_3_5G_DL_Pin 
+                           PATH_EN_3_5G_UL_Pin PLL_ON_OFF_3_5G_L_Pin PLL_ON_OFF_3_5G_H_Pin */
+  GPIO_InitStruct.Pin = DA_SYNC_Pin|DA_SCLK_Pin|DA_DIN_Pin|_T_SYNC_UL_Pin 
+                          |T_SYNC_UL_Pin|_T_SYNC_DL_Pin|T_SYNC_DL_Pin|PATH_EN_3_5G_DL_Pin 
+                          |PATH_EN_3_5G_UL_Pin|PLL_ON_OFF_3_5G_L_Pin|PLL_ON_OFF_3_5G_H_Pin;
   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
   GPIO_InitStruct.Pull = GPIO_NOPULL;
   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
-  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+  HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
 
-  /*Configure GPIO pins : PLL_LD_3_5G_H_Pin PLL_LD_3_5G_L_Pin PLL_LD_2_1G_UL_Pin PLL_LD_2_1G_DL_Pin */
-  GPIO_InitStruct.Pin = PLL_LD_3_5G_H_Pin|PLL_LD_3_5G_L_Pin|PLL_LD_2_1G_UL_Pin|PLL_LD_2_1G_DL_Pin;
+  /*Configure GPIO pins : PLL_LD_3_5G_L_Pin PLL_LD_3_5G_H_Pin */
+  GPIO_InitStruct.Pin = PLL_LD_3_5G_L_Pin|PLL_LD_3_5G_H_Pin;
   GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
   GPIO_InitStruct.Pull = GPIO_NOPULL;
-  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+  /*Configure GPIO pin : PATH_EN_3_5G_H_Pin */
+  GPIO_InitStruct.Pin = PATH_EN_3_5G_H_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+  HAL_GPIO_Init(PATH_EN_3_5G_H_GPIO_Port, &GPIO_InitStruct);
 
-  /*Configure GPIO pins : PATH_EN_3_5G_L_Pin ATT_DATA_3_5G_COM3_Pin ATT_DATA_3_5G_COM2_Pin ATT_DATA_3_5G_COM1_Pin 
-                           ATT_DATA_3_5G_UL_Pin */
-  GPIO_InitStruct.Pin = PATH_EN_3_5G_L_Pin|ATT_DATA_3_5G_COM3_Pin|ATT_DATA_3_5G_COM2_Pin|ATT_DATA_3_5G_COM1_Pin 
-                          |ATT_DATA_3_5G_UL_Pin;
+  /*Configure GPIO pins : PLL_EN_2_1G_DL_Pin PLL_EN_2_1G_UL_Pin */
+  GPIO_InitStruct.Pin = PLL_EN_2_1G_DL_Pin|PLL_EN_2_1G_UL_Pin;
   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
   GPIO_InitStruct.Pull = GPIO_NOPULL;
   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : PLL_LD_2_1G_DL_Pin PLL_LD_2_1G_UL_Pin */
+  GPIO_InitStruct.Pin = PLL_LD_2_1G_DL_Pin|PLL_LD_2_1G_UL_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 
 }
 

Src/stm32f1xx_hal_msp.c

@@ -24,6 +24,7 @@
 /* USER CODE BEGIN Includes */
 
 /* USER CODE END Includes */
+extern DMA_HandleTypeDef hdma_adc1;
 
 /* Private typedef -----------------------------------------------------------*/
 /* USER CODE BEGIN TD */
@@ -130,6 +131,23 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
     GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
     HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 
+    /* ADC1 DMA Init */
+    /* ADC1 Init */
+    hdma_adc1.Instance = DMA1_Channel1;
+    hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY;
+    hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_adc1.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
+    hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
+    hdma_adc1.Init.Mode = DMA_CIRCULAR;
+    hdma_adc1.Init.Priority = DMA_PRIORITY_LOW;
+    if (HAL_DMA_Init(&hdma_adc1) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc1);
+
   /* USER CODE BEGIN ADC1_MspInit 1 */
 
   /* USER CODE END ADC1_MspInit 1 */
@@ -176,6 +194,8 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
 
     HAL_GPIO_DeInit(GPIOB, DET_3_5G_DL_IN_Pin|DET_3_5G_DL_OUT_Pin);
 
+    /* ADC1 DMA DeInit */
+    HAL_DMA_DeInit(hadc->DMA_Handle);
   /* USER CODE BEGIN ADC1_MspDeInit 1 */
 
   /* USER CODE END ADC1_MspDeInit 1 */
@@ -244,6 +264,8 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
     */
     HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10);
 
+    /* USART1 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(USART1_IRQn);
   /* USER CODE BEGIN USART1_MspDeInit 1 */
 
   /* USER CODE END USART1_MspDeInit 1 */

Src/stm32f1xx_it.c

@@ -56,7 +56,8 @@
 /* USER CODE END 0 */
 
 /* External variables --------------------------------------------------------*/
-
+extern DMA_HandleTypeDef hdma_adc1;
+extern UART_HandleTypeDef huart1;
 /* USER CODE BEGIN EV */
 
 /* USER CODE END EV */
@@ -197,6 +198,34 @@ void SysTick_Handler(void)
 /* please refer to the startup file (startup_stm32f1xx.s).                    */
 /******************************************************************************/
 
+/**
+  * @brief This function handles DMA1 channel1 global interrupt.
+  */
+void DMA1_Channel1_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */
+
+  /* USER CODE END DMA1_Channel1_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_adc1);
+  /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */
+
+  /* USER CODE END DMA1_Channel1_IRQn 1 */
+}
+
+/**
+  * @brief This function handles USART1 global interrupt.
+  */
+void USART1_IRQHandler(void)
+{
+  /* USER CODE BEGIN USART1_IRQn 0 */
+
+  /* USER CODE END USART1_IRQn 0 */
+  HAL_UART_IRQHandler(&huart1);
+  /* USER CODE BEGIN USART1_IRQn 1 */
+
+  /* USER CODE END USART1_IRQn 1 */
+}
+
 /* USER CODE BEGIN 1 */
 
 /* USER CODE END 1 */

insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/PE43711(6308).c

@@ -0,0 +1,105 @@
+/*
+ * PE43711.c
+ *
+ *  Created on: 2019. 6. 28.
+ *      Author: parkyj
+ */
+ #include "PE43711.h"
+ typedef struct{
+    uint16_t ATT_EN_1_8G_DL1_PIN;
+    GPIO_TypeDef *ATT_EN_1_8G_DL1_PORT;
+        
+    uint16_t ATT_EN_1_8G_DL2_PIN;
+    GPIO_TypeDef *ATT_EN_1_8G_DL2_PORT;
+
+    uint16_t ATT_EN_1_8G_UL1_PIN;
+    GPIO_TypeDef *ATT_EN_1_8G_UL1_PORT;
+
+    uint16_t ATT_EN_1_8G_UL2_PIN;
+    GPIO_TypeDef *ATT_EN_1_8G_UL2_PORT;
+
+    uint16_t ATT_EN_1_8G_UL3_PIN;
+    GPIO_TypeDef *ATT_EN_1_8G_UL3_PORT;
+
+    uint16_t ATT_EN_1_8G_UL4_PIN;
+    GPIO_TypeDef *ATT_EN_1_8G_UL4_PORT;
+ }PE43711_st;
+
+PE43711_st *Atten_1_8Ghz; 
+PE43711_st *Atten_2_1Ghz; 
+
+ 
+void PE43711_PinInit(void){
+    Atten_1_8Ghz->ATT_EN_1_8G_DL1_PIN = GPIO_PIN_1;
+    Atten_1_8Ghz->ATT_EN_1_8G_DL1_PORT = GPIOB;
+    
+    Atten_1_8Ghz->ATT_EN_1_8G_DL2_PIN = GPIO_PIN_1;
+    Atten_1_8Ghz->ATT_EN_1_8G_DL2_PORT = GPIOB;
+    
+    Atten_1_8Ghz->ATT_EN_1_8G_UL1_PIN = GPIO_PIN_1;
+    Atten_1_8Ghz->ATT_EN_1_8G_UL1_PORT = GPIOB;
+    
+    Atten_1_8Ghz->ATT_EN_1_8G_DL1_PIN = GPIO_PIN_1;
+    Atten_1_8Ghz->ATT_EN_1_8G_DL1_PIN = GPIOB;
+    
+    Atten_1_8Ghz->ATT_EN_1_8G_UL2_PIN = GPIO_PIN_1;
+    Atten_1_8Ghz->ATT_EN_1_8G_UL2_PORT = GPIOB;
+
+    Atten_1_8Ghz->ATT_EN_1_8G_UL3_PIN = GPIO_PIN_1;
+    Atten_1_8Ghz->ATT_EN_1_8G_UL3_PORT = GPIOB;
+    
+    Atten_1_8Ghz->ATT_EN_1_8G_UL4_PIN = GPIO_PIN_1;
+    Atten_1_8Ghz->ATT_EN_1_8G_UL4_PORT = GPIOB;
+
+
+    Atten_2_1Ghz->ATT_EN_1_8G_DL1_PIN = GPIO_PIN_1;
+    Atten_2_1Ghz->ATT_EN_1_8G_DL1_PORT = GPIOB;
+
+    Atten_2_1Ghz->ATT_EN_1_8G_DL2_PIN = GPIO_PIN_1;
+    Atten_2_1Ghz->ATT_EN_1_8G_DL2_PORT = GPIOB;
+
+    Atten_2_1Ghz->ATT_EN_1_8G_UL1_PIN = GPIO_PIN_1;
+    Atten_2_1Ghz->ATT_EN_1_8G_UL1_PORT = GPIOB;
+
+    Atten_2_1Ghz->ATT_EN_1_8G_DL1_PIN = GPIO_PIN_1;
+    Atten_2_1Ghz->ATT_EN_1_8G_DL1_PIN = GPIOB;
+
+    Atten_2_1Ghz->ATT_EN_1_8G_UL2_PIN = GPIO_PIN_1;
+    Atten_2_1Ghz->ATT_EN_1_8G_UL2_PORT = GPIOB;
+
+    Atten_2_1Ghz->ATT_EN_1_8G_UL3_PIN = GPIO_PIN_1;
+    Atten_2_1Ghz->ATT_EN_1_8G_UL3_PORT = GPIOB;
+
+    Atten_2_1Ghz->ATT_EN_1_8G_UL4_PIN = GPIO_PIN_1;
+    Atten_2_1Ghz->ATT_EN_1_8G_UL4_PORT = GPIOB;
+    
+}
+
+void PE43711_atten_ctrl(PE43711_st* type ,double data){
+    uint8_t i = 0;
+    uint8_t temp = 0;
+    data = 4 * data;
+    temp = (uint8_t)data;
+    HAL_GPIO_WritePin(GPIOB,GPIO_PIN_1,GPIO_PIN_RESET);
+    HAL_Delay(1);
+    for(i = 0; i < 8; i++){
+        if((uint8_t)temp & 0x01){
+           HAL_GPIO_WritePin(GPIOB,GPIO_PIN_15,GPIO_PIN_SET);//DATA
+        }
+           else{
+           HAL_GPIO_WritePin(GPIOB,GPIO_PIN_15,GPIO_PIN_RESET);//DATA
+           }
+
+		HAL_GPIO_WritePin(GPIOB,GPIO_PIN_2,GPIO_PIN_SET);//CLOCK
+		HAL_Delay(1);
+		HAL_GPIO_WritePin(GPIOB,GPIO_PIN_2,GPIO_PIN_RESET);//CLOCK
+		HAL_Delay(1);
+		temp >>= 1;
+    }
+	HAL_GPIO_WritePin(GPIOB,GPIO_PIN_2,GPIO_PIN_RESET);//CLOCK
+    HAL_GPIO_WritePin(GPIOB,GPIO_PIN_15,GPIO_PIN_RESET);//DATA
+    HAL_Delay(5);
+    HAL_GPIO_WritePin(GPIOB,GPIO_PIN_1,GPIO_PIN_SET);//LE
+    HAL_Delay(1);
+    HAL_GPIO_WritePin(GPIOB,GPIO_PIN_1,GPIO_PIN_RESET);
+}

insight/STM32F103_ATTEN_PLL_Zig.si4project/STM32F103_ATTEN_PLL_Zig.bookmarks.xml

@@ -0,0 +1,7 @@
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+	AppVerMinReader="4.00.0009"
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insight/STM32F103_ATTEN_PLL_Zig.si4project/STM32F103_ATTEN_PLL_Zig.siproj_settings.xml

@@ -0,0 +1,22 @@
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+	AppVer="4.00.0084"
+	AppVerMinReader="4.00.0034"
+	GlobalConfiguration="1"
+	GlobalWorkspace="0"
+	LocalsInDb="0"
+	IndexMembers="0"
+	IndexFragments="1"
+	UseMasterFileList="0"
+	SourceDir="."
+	BackupDir="%PROJECT_DATA_DIR%\Backup"
+	MasterFileList="%PROJECT_SOURCE_DIR%\%PROJECT_NAME%_filelist.txt"
+	IsImportProject="0"
+	>
+	<Imports>
+		<ImportedLibs/>
+	</Imports>
+	<ParseConditions>
+		<Defines/>
+	</ParseConditions>
+</ProjectSettings>

insight/STM32F103_ATTEN_PLL_Zig.si4project/STM32F103_ATTEN_PLL_Zig.snippets.xml

@@ -0,0 +1,7 @@
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