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BootLoader First /CRC First / Flash First / Uart First / Setting 변경 / Bootloader Flash Write 범위 설정

YJ před 6 roky
rodič
revize
960322e1df
100 změnil soubory, kde provedl 9288 přidání a 3089 odebrání
  1. 209 199
      .cproject
  2. 2 0
      .gitignore
  3. 3 0
      .settings/com.atollic.truestudio.tsp.prefs
  4. binární
      Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o
  5. 99 0
      Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.su
  6. binární
      Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o
  7. 36 0
      Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.su
  8. binární
      Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o
  9. binární
      Debug/STM32F103_ATTEN_PLL_Zig.elf
  10. 806 325
      Debug/STM32F103_ATTEN_PLL_Zig.hex
  11. 6154 2034
      Debug/STM32F103_ATTEN_PLL_Zig.list
  12. 1325 442
      Debug/STM32F103_ATTEN_PLL_Zig.map
  13. binární
      Debug/Src/CRC16.o
  14. 4 1
      Debug/Src/CRC16.su
  15. binární
      Debug/Src/main.o
  16. 5 3
      Debug/Src/main.su
  17. binární
      Debug/Src/stm32f1xx_hal_msp.o
  18. 5 3
      Debug/Src/stm32f1xx_hal_msp.su
  19. binární
      Debug/Src/stm32f1xx_it.o
  20. 3 3
      Debug/Src/stm32f1xx_it.su
  21. 77 0
      Inc/Bootloader.h
  22. 9 1
      Inc/CRC16.h
  23. 25 0
      Inc/flash.h
  24. 7 2
      Inc/main.h
  25. 1 1
      Inc/stm32f1xx_hal_conf.h
  26. 1 1
      Inc/stm32f1xx_it.h
  27. 35 0
      Inc/uart.h
  28. 1 1
      STM32F103ZE_FLASH.ld
  29. 14 17
      STM32F103_ATTEN_PLL_Zig.ioc
  30. 45 0
      Src/Bootloader.c
  31. 89 14
      Src/CRC16.c
  32. 105 0
      Src/flash.c
  33. 75 8
      Src/main.c
  34. 47 19
      Src/stm32f1xx_hal_msp.c
  35. 15 15
      Src/stm32f1xx_it.c
  36. 91 0
      Src/uart.c
  37. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/STM32F103_ATTEN_PLL_Zig.sip_xc
  38. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/STM32F103_ATTEN_PLL_Zig.sip_xf
  39. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/STM32F103_ATTEN_PLL_Zig.sip_xm
  40. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/STM32F103_ATTEN_PLL_Zig.sip_xr
  41. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/STM32F103_ATTEN_PLL_Zig.siproj
  42. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/STM32F103_ATTEN_PLL_Zig.siwork
  43. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Device_ST_STM32F1xx_Include_stm32f103xe.h.sisc
  44. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Device_ST_STM32F1xx_Include_stm32f1xx.h.sisc
  45. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Device_ST_STM32F1xx_Include_system_stm32f1xx.h.sisc
  46. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_arm_common_tables.h.sisc
  47. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_arm_const_structs.h.sisc
  48. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_arm_math.h.sisc
  49. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_cmsis_armcc.h.sisc
  50. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_cmsis_armcc_V6.h.sisc
  51. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_cmsis_gcc.h.sisc
  52. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_core_cm0.h.sisc
  53. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_core_cm0plus.h.sisc
  54. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_core_cm3.h.sisc
  55. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_core_cm4.h.sisc
  56. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_core_cm7.h.sisc
  57. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_core_cmFunc.h.sisc
  58. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_core_cmInstr.h.sisc
  59. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_core_cmSimd.h.sisc
  60. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_core_sc000.h.sisc
  61. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_core_sc300.h.sisc
  62. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_Legacy_stm32_hal_legacy.h.sisc
  63. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal.h.sisc
  64. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_adc.h.sisc
  65. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_adc_ex.h.sisc
  66. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_cortex.h.sisc
  67. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_def.h.sisc
  68. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_dma.h.sisc
  69. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_dma_ex.h.sisc
  70. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_flash.h.sisc
  71. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_flash_ex.h.sisc
  72. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_gpio.h.sisc
  73. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_gpio_ex.h.sisc
  74. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_pwr.h.sisc
  75. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_rcc.h.sisc
  76. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_rcc_ex.h.sisc
  77. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_tim.h.sisc
  78. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_tim_ex.h.sisc
  79. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_uart.h.sisc
  80. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal.c.sisc
  81. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_adc.c.sisc
  82. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_adc_ex.c.sisc
  83. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_cortex.c.sisc
  84. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_dma.c.sisc
  85. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_flash.c.sisc
  86. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_flash_ex.c.sisc
  87. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_gpio.c.sisc
  88. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_gpio_ex.c.sisc
  89. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_pwr.c.sisc
  90. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_rcc.c.sisc
  91. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_rcc_ex.c.sisc
  92. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_tim.c.sisc
  93. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_tim_ex.c.sisc
  94. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_uart.c.sisc
  95. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_BDA4601.h.sisc
  96. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_PE43711.h.sisc
  97. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_main.h.sisc
  98. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_stm32f1xx_hal_conf.h.sisc
  99. binární
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_stm32f1xx_it.h.sisc
  100. 0 0
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_BDA4601.c.sisc

Diff nebyl zobrazen, protože je příliš veliký
+ 209 - 199
.cproject


+ 2 - 0
.gitignore

@@ -1,3 +1,5 @@
1 1
 insight
2 2
 insight
3 3
 insight
4
+insight
5
+/Debug/

+ 3 - 0
.settings/com.atollic.truestudio.tsp.prefs

@@ -0,0 +1,3 @@
1
+eclipse.preferences.version=1
2
+svd_custom_file_path=
3
+svd_file_path=C\:\\Program Files (x86)\\Atollic\\TrueSTUDIO for STM32 9.3.0\\ide\\plugins\\com.atollic.truestudio.tsp.stm32_1.0.0.20190212-0734\\tsp\\sfr\\STM32F103.svd

binární
Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.o


+ 99 - 0
Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.su

@@ -0,0 +1,99 @@
1
+stm32f1xx_hal_tim.c:4640:13:TIM_OC1_SetConfig	16	static
2
+stm32f1xx_hal_tim.c:4790:13:TIM_OC3_SetConfig	16	static
3
+stm32f1xx_hal_tim.c:4864:13:TIM_OC4_SetConfig	12	static
4
+stm32f1xx_hal_tim.c:4924:13:TIM_SlaveTimer_SetConfig	12	static
5
+stm32f1xx_hal_tim.c:275:13:HAL_TIM_Base_MspInit	0	static
6
+stm32f1xx_hal_tim.c:289:13:HAL_TIM_Base_MspDeInit	0	static
7
+stm32f1xx_hal_tim.c:248:19:HAL_TIM_Base_DeInit	8	static
8
+stm32f1xx_hal_tim.c:304:19:HAL_TIM_Base_Start	0	static
9
+stm32f1xx_hal_tim.c:327:19:HAL_TIM_Base_Stop	0	static
10
+stm32f1xx_hal_tim.c:350:19:HAL_TIM_Base_Start_IT	0	static
11
+stm32f1xx_hal_tim.c:370:19:HAL_TIM_Base_Stop_IT	0	static
12
+stm32f1xx_hal_tim.c:391:19:HAL_TIM_Base_Start_DMA	8	static
13
+stm32f1xx_hal_tim.c:435:19:HAL_TIM_Base_Stop_DMA	0	static
14
+stm32f1xx_hal_tim.c:555:13:HAL_TIM_OC_MspInit	0	static
15
+stm32f1xx_hal_tim.c:569:13:HAL_TIM_OC_MspDeInit	0	static
16
+stm32f1xx_hal_tim.c:528:19:HAL_TIM_OC_DeInit	8	static
17
+stm32f1xx_hal_tim.c:1064:13:HAL_TIM_PWM_MspInit	0	static
18
+stm32f1xx_hal_tim.c:1078:13:HAL_TIM_PWM_MspDeInit	0	static
19
+stm32f1xx_hal_tim.c:1037:19:HAL_TIM_PWM_DeInit	8	static
20
+stm32f1xx_hal_tim.c:1576:13:HAL_TIM_IC_MspInit	0	static
21
+stm32f1xx_hal_tim.c:1590:13:HAL_TIM_IC_MspDeInit	0	static
22
+stm32f1xx_hal_tim.c:1549:19:HAL_TIM_IC_DeInit	8	static
23
+stm32f1xx_hal_tim.c:2061:13:HAL_TIM_OnePulse_MspInit	0	static
24
+stm32f1xx_hal_tim.c:2075:13:HAL_TIM_OnePulse_MspDeInit	0	static
25
+stm32f1xx_hal_tim.c:2034:19:HAL_TIM_OnePulse_DeInit	8	static
26
+stm32f1xx_hal_tim.c:2093:19:HAL_TIM_OnePulse_Start	0	static
27
+stm32f1xx_hal_tim.c:2129:19:HAL_TIM_OnePulse_Stop	0	static
28
+stm32f1xx_hal_tim.c:2165:19:HAL_TIM_OnePulse_Start_IT	0	static
29
+stm32f1xx_hal_tim.c:2207:19:HAL_TIM_OnePulse_Stop_IT	0	static
30
+stm32f1xx_hal_tim.c:2394:13:HAL_TIM_Encoder_MspInit	0	static
31
+stm32f1xx_hal_tim.c:2408:13:HAL_TIM_Encoder_MspDeInit	0	static
32
+stm32f1xx_hal_tim.c:2367:19:HAL_TIM_Encoder_DeInit	8	static
33
+stm32f1xx_hal_tim.c:2427:19:HAL_TIM_Encoder_Start	0	static
34
+stm32f1xx_hal_tim.c:2469:19:HAL_TIM_Encoder_Stop	0	static
35
+stm32f1xx_hal_tim.c:2513:19:HAL_TIM_Encoder_Start_IT	0	static
36
+stm32f1xx_hal_tim.c:2561:19:HAL_TIM_Encoder_Stop_IT	0	static
37
+stm32f1xx_hal_tim.c:2615:19:HAL_TIM_Encoder_Start_DMA	24	static
38
+stm32f1xx_hal_tim.c:2732:19:HAL_TIM_Encoder_Stop_DMA	0	static
39
+stm32f1xx_hal_tim.c:3358:19:HAL_TIM_DMABurst_WriteStart	24	static
40
+stm32f1xx_hal_tim.c:3581:19:HAL_TIM_DMABurst_ReadStart	24	static
41
+stm32f1xx_hal_tim.c:3713:19:HAL_TIM_DMABurst_ReadStop	16	static
42
+stm32f1xx_hal_tim.c:3489:19:HAL_TIM_DMABurst_WriteStop	0	static
43
+stm32f1xx_hal_tim.c:3785:19:HAL_TIM_GenerateEvent	0	static
44
+stm32f1xx_hal_tim.c:3822:19:HAL_TIM_ConfigOCrefClear	16	static
45
+stm32f1xx_hal_tim.c:3943:19:HAL_TIM_ConfigClockSource	16	static
46
+stm32f1xx_hal_tim.c:4117:19:HAL_TIM_ConfigTI1Input	0	static
47
+stm32f1xx_hal_tim.c:4149:19:HAL_TIM_SlaveConfigSynchronization	16	static
48
+stm32f1xx_hal_tim.c:4184:19:HAL_TIM_SlaveConfigSynchronization_IT	16	static
49
+stm32f1xx_hal_tim.c:4222:10:HAL_TIM_ReadCapturedValue	0	static
50
+stm32f1xx_hal_tim.c:4309:13:HAL_TIM_PeriodElapsedCallback	0	static
51
+stm32f1xx_hal_tim.c:4562:13:TIM_DMAPeriodElapsedCplt	8	static
52
+stm32f1xx_hal_tim.c:4323:13:HAL_TIM_OC_DelayElapsedCallback	0	static
53
+stm32f1xx_hal_tim.c:4336:13:HAL_TIM_IC_CaptureCallback	0	static
54
+stm32f1xx_hal_tim.c:4529:6:TIM_DMACaptureCplt	8	static
55
+stm32f1xx_hal_tim.c:4350:13:HAL_TIM_PWM_PulseFinishedCallback	0	static
56
+stm32f1xx_hal_tim.c:4497:6:TIM_DMADelayPulseCplt	8	static
57
+stm32f1xx_hal_tim.c:4364:13:HAL_TIM_TriggerCallback	0	static
58
+stm32f1xx_hal_tim.c:2794:6:HAL_TIM_IRQHandler	8	static
59
+stm32f1xx_hal_tim.c:4576:13:TIM_DMATriggerCplt	8	static
60
+stm32f1xx_hal_tim.c:4378:13:HAL_TIM_ErrorCallback	0	static
61
+stm32f1xx_hal_tim.c:4483:6:TIM_DMAError	8	static
62
+stm32f1xx_hal_tim.c:4411:22:HAL_TIM_Base_GetState	0	static
63
+stm32f1xx_hal_tim.c:4421:22:HAL_TIM_OC_GetState	0	static
64
+stm32f1xx_hal_tim.c:4431:22:HAL_TIM_PWM_GetState	0	static
65
+stm32f1xx_hal_tim.c:4441:22:HAL_TIM_IC_GetState	0	static
66
+stm32f1xx_hal_tim.c:4451:22:HAL_TIM_OnePulse_GetState	0	static
67
+stm32f1xx_hal_tim.c:4461:22:HAL_TIM_Encoder_GetState	0	static
68
+stm32f1xx_hal_tim.c:4591:6:TIM_Base_SetConfig	0	static
69
+stm32f1xx_hal_tim.c:208:19:HAL_TIM_Base_Init	8	static
70
+stm32f1xx_hal_tim.c:488:19:HAL_TIM_OC_Init	8	static
71
+stm32f1xx_hal_tim.c:997:19:HAL_TIM_PWM_Init	8	static
72
+stm32f1xx_hal_tim.c:1509:19:HAL_TIM_IC_Init	8	static
73
+stm32f1xx_hal_tim.c:1987:19:HAL_TIM_OnePulse_Init	16	static
74
+stm32f1xx_hal_tim.c:2274:19:HAL_TIM_Encoder_Init	24	static
75
+stm32f1xx_hal_tim.c:4714:6:TIM_OC2_SetConfig	16	static
76
+stm32f1xx_hal_tim.c:2957:19:HAL_TIM_OC_ConfigChannel	16	static
77
+stm32f1xx_hal_tim.c:3122:19:HAL_TIM_PWM_ConfigChannel	16	static
78
+stm32f1xx_hal_tim.c:5068:6:TIM_TI1_SetConfig	16	static
79
+stm32f1xx_hal_tim.c:3026:19:HAL_TIM_IC_ConfigChannel	24	static
80
+stm32f1xx_hal_tim.c:3222:19:HAL_TIM_OnePulse_ConfigChannel	48	static
81
+stm32f1xx_hal_tim.c:5390:6:TIM_CCxChannelCmd	8	static
82
+stm32f1xx_hal_tim.c:621:19:HAL_TIM_OC_Stop	8	static
83
+stm32f1xx_hal_tim.c:1098:19:HAL_TIM_PWM_Start	8	static
84
+stm32f1xx_hal_tim.c:589:19:HAL_TIM_OC_Start	0	static
85
+stm32f1xx_hal_tim.c:1130:19:HAL_TIM_PWM_Stop	8	static
86
+stm32f1xx_hal_tim.c:1165:19:HAL_TIM_PWM_Start_IT	8	static
87
+stm32f1xx_hal_tim.c:653:19:HAL_TIM_OC_Start_IT	0	static
88
+stm32f1xx_hal_tim.c:1231:19:HAL_TIM_PWM_Stop_IT	8	static
89
+stm32f1xx_hal_tim.c:719:19:HAL_TIM_OC_Stop_IT	0	static
90
+stm32f1xx_hal_tim.c:1299:19:HAL_TIM_PWM_Start_DMA	16	static
91
+stm32f1xx_hal_tim.c:787:19:HAL_TIM_OC_Start_DMA	0	static
92
+stm32f1xx_hal_tim.c:1416:19:HAL_TIM_PWM_Stop_DMA	8	static
93
+stm32f1xx_hal_tim.c:904:19:HAL_TIM_OC_Stop_DMA	0	static
94
+stm32f1xx_hal_tim.c:1610:19:HAL_TIM_IC_Start	8	static
95
+stm32f1xx_hal_tim.c:1636:19:HAL_TIM_IC_Stop	8	static
96
+stm32f1xx_hal_tim.c:1662:19:HAL_TIM_IC_Start_IT	8	static
97
+stm32f1xx_hal_tim.c:1721:19:HAL_TIM_IC_Stop_IT	8	static
98
+stm32f1xx_hal_tim.c:1783:19:HAL_TIM_IC_Start_DMA	16	static
99
+stm32f1xx_hal_tim.c:1896:19:HAL_TIM_IC_Stop_DMA	8	static

binární
Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.o


+ 36 - 0
Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.su

@@ -0,0 +1,36 @@
1
+stm32f1xx_hal_tim_ex.c:1743:13:TIM_CCxNChannelCmd	8	static
2
+stm32f1xx_hal_tim_ex.c:271:13:HAL_TIMEx_HallSensor_MspInit	0	static
3
+stm32f1xx_hal_tim_ex.c:165:19:HAL_TIMEx_HallSensor_Init	48	static
4
+stm32f1xx_hal_tim_ex.c:285:13:HAL_TIMEx_HallSensor_MspDeInit	0	static
5
+stm32f1xx_hal_tim_ex.c:244:19:HAL_TIMEx_HallSensor_DeInit	8	static
6
+stm32f1xx_hal_tim_ex.c:299:19:HAL_TIMEx_HallSensor_Start	8	static
7
+stm32f1xx_hal_tim_ex.c:320:19:HAL_TIMEx_HallSensor_Stop	8	static
8
+stm32f1xx_hal_tim_ex.c:341:19:HAL_TIMEx_HallSensor_Start_IT	8	static
9
+stm32f1xx_hal_tim_ex.c:365:19:HAL_TIMEx_HallSensor_Stop_IT	8	static
10
+stm32f1xx_hal_tim_ex.c:391:19:HAL_TIMEx_HallSensor_Start_DMA	16	static
11
+stm32f1xx_hal_tim_ex.c:438:19:HAL_TIMEx_HallSensor_Stop_DMA	8	static
12
+stm32f1xx_hal_tim_ex.c:871:19:HAL_TIMEx_PWMN_Start	8	static
13
+stm32f1xx_hal_tim_ex.c:497:19:HAL_TIMEx_OCN_Start	0	static
14
+stm32f1xx_hal_tim_ex.c:928:19:HAL_TIMEx_PWMN_Start_IT	8	static
15
+stm32f1xx_hal_tim_ex.c:555:19:HAL_TIMEx_OCN_Start_IT	0	static
16
+stm32f1xx_hal_tim_ex.c:987:19:HAL_TIMEx_PWMN_Stop_IT	8	static
17
+stm32f1xx_hal_tim_ex.c:614:19:HAL_TIMEx_OCN_Stop_IT	0	static
18
+stm32f1xx_hal_tim_ex.c:1054:19:HAL_TIMEx_PWMN_Start_DMA	16	static
19
+stm32f1xx_hal_tim_ex.c:681:19:HAL_TIMEx_OCN_Start_DMA	0	static
20
+stm32f1xx_hal_tim_ex.c:1152:19:HAL_TIMEx_PWMN_Stop_DMA	8	static
21
+stm32f1xx_hal_tim_ex.c:779:19:HAL_TIMEx_OCN_Stop_DMA	0	static
22
+stm32f1xx_hal_tim_ex.c:1232:19:HAL_TIMEx_OnePulseN_Start	8	static
23
+stm32f1xx_hal_tim_ex.c:1257:19:HAL_TIMEx_OnePulseN_Stop	8	static
24
+stm32f1xx_hal_tim_ex.c:899:19:HAL_TIMEx_PWMN_Stop	0	static
25
+stm32f1xx_hal_tim_ex.c:526:19:HAL_TIMEx_OCN_Stop	0	static
26
+stm32f1xx_hal_tim_ex.c:1286:19:HAL_TIMEx_OnePulseN_Start_IT	8	static
27
+stm32f1xx_hal_tim_ex.c:1317:19:HAL_TIMEx_OnePulseN_Stop_IT	8	static
28
+stm32f1xx_hal_tim_ex.c:1392:19:HAL_TIMEx_ConfigCommutationEvent	8	static
29
+stm32f1xx_hal_tim_ex.c:1441:19:HAL_TIMEx_ConfigCommutationEvent_IT	8	static
30
+stm32f1xx_hal_tim_ex.c:1494:19:HAL_TIMEx_ConfigCommutationEvent_DMA	8	static
31
+stm32f1xx_hal_tim_ex.c:1538:19:HAL_TIMEx_ConfigBreakDeadTime	0	static
32
+stm32f1xx_hal_tim_ex.c:1589:19:HAL_TIMEx_MasterConfigSynchronization	8	static
33
+stm32f1xx_hal_tim_ex.c:1642:13:HAL_TIMEx_CommutationCallback	0	static
34
+stm32f1xx_hal_tim_ex.c:1670:6:TIMEx_DMACommutationCplt	8	static
35
+stm32f1xx_hal_tim_ex.c:1656:13:HAL_TIMEx_BreakCallback	0	static
36
+stm32f1xx_hal_tim_ex.c:1707:22:HAL_TIMEx_HallSensor_GetState	0	static

binární
Debug/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.o


binární
Debug/STM32F103_ATTEN_PLL_Zig.elf


Diff nebyl zobrazen, protože je příliš veliký
+ 806 - 325
Debug/STM32F103_ATTEN_PLL_Zig.hex


Diff nebyl zobrazen, protože je příliš veliký
+ 6154 - 2034
Debug/STM32F103_ATTEN_PLL_Zig.list


Diff nebyl zobrazen, protože je příliš veliký
+ 1325 - 442
Debug/STM32F103_ATTEN_PLL_Zig.map


binární
Debug/Src/CRC16.o


+ 4 - 1
Debug/Src/CRC16.su

@@ -1 +1,4 @@
1
-CRC16.c:49:16:genCRC16	8	static
1
+CRC16.c:50:10:CRC16_Generate	8	static
2
+CRC16.c:84:9:CRC16_Check	12	static
3
+CRC16.c:119:9:STH30_CreateCrc	8	static
4
+CRC16.c:137:9:STH30_CheckCrc	12	static

binární
Debug/Src/main.o


+ 5 - 3
Debug/Src/main.su

@@ -1,3 +1,5 @@
1
-main.c:122:6:SystemClock_Config	72	static
2
-main.c:73:5:main	32	static
3
-main.c:246:6:Error_Handler	0	static
1
+main.c:70:6:HAL_TIM_PeriodElapsedCallback	0	static
2
+main.c:79:5:_write	8	static
3
+main.c:151:6:SystemClock_Config	72	static
4
+main.c:91:5:main	32	static
5
+main.c:313:6:Error_Handler	0	static

binární
Debug/Src/stm32f1xx_hal_msp.o


+ 5 - 3
Debug/Src/stm32f1xx_hal_msp.su

@@ -1,3 +1,5 @@
1
-stm32f1xx_hal_msp.c:67:6:HAL_MspInit	8	static
2
-stm32f1xx_hal_msp.c:93:6:HAL_UART_MspInit	40	static
3
-stm32f1xx_hal_msp.c:165:6:HAL_UART_MspDeInit	8	static
1
+stm32f1xx_hal_msp.c:65:6:HAL_MspInit	8	static
2
+stm32f1xx_hal_msp.c:91:6:HAL_TIM_Base_MspInit	8	static
3
+stm32f1xx_hal_msp.c:113:6:HAL_TIM_Base_MspDeInit	0	static
4
+stm32f1xx_hal_msp.c:138:6:HAL_UART_MspInit	40	static
5
+stm32f1xx_hal_msp.c:194:6:HAL_UART_MspDeInit	8	static

binární
Debug/Src/stm32f1xx_it.o


+ 3 - 3
Debug/Src/stm32f1xx_it.su

@@ -7,6 +7,6 @@ stm32f1xx_it.c:145:6:SVC_Handler	0	static
7 7
 stm32f1xx_it.c:158:6:DebugMon_Handler	0	static
8 8
 stm32f1xx_it.c:171:6:PendSV_Handler	0	static
9 9
 stm32f1xx_it.c:184:6:SysTick_Handler	0	static
10
-stm32f1xx_it.c:205:6:DMA1_Channel4_IRQHandler	0	static
11
-stm32f1xx_it.c:219:6:DMA1_Channel5_IRQHandler	0	static
12
-stm32f1xx_it.c:233:6:USART1_IRQHandler	0	static
10
+stm32f1xx_it.c:205:6:DMA1_Channel5_IRQHandler	0	static
11
+stm32f1xx_it.c:219:6:USART1_IRQHandler	0	static
12
+stm32f1xx_it.c:233:6:TIM6_IRQHandler	0	static

+ 77 - 0
Inc/Bootloader.h

@@ -0,0 +1,77 @@
1
+/*
2
+ * Bootloader.h
3
+ *
4
+ *  Created on: Jul 10, 2019
5
+ *      Author: parkyj
6
+ */
7
+
8
+#ifndef BOOTLOADER_H_
9
+#define BOOTLOADER_H_
10
+#include "main.h"
11
+
12
+extern uint8_t * UpdateFiledata;
13
+
14
+typedef struct{
15
+	uint8_t bluecell_header01;
16
+	uint8_t bluecell_header02;
17
+	uint8_t bluecell_header03;
18
+	uint8_t bluecell_header04;
19
+	uint8_t bluecell_type;
20
+	uint8_t bluecell_length_h;
21
+	uint8_t bluecell_length_l;
22
+	uint8_t bluecell_data[2048];
23
+}Blueprotocol_t;
24
+typedef enum {
25
+	BLUECELL_HEADER00 = 0,
26
+	BLUECELL_HEADER01,
27
+	BLUECELL_HEADER02,
28
+	BLUECELL_HEADER03,
29
+	BLUECELL_TYPE,
30
+	BLUECELL_LENGTH_H,
31
+	BLUECELL_LENGTH_L,
32
+	BLUECELL_UPDATACNT_H,
33
+	BLUECELL_UPDATACNT_L,
34
+	BLUECELL_DATA,
35
+}Bluenum;
36
+typedef enum {
37
+	BLUECELL_RESET = 0,
38
+	BLUECELL_START,
39
+	BLUECELL_SENDING,
40
+	BLUECELL_END,
41
+}updateseq;
42
+typedef enum updateseqok
43
+{
44
+    UpdateResetOK = 0,
45
+    UpdateStartOK,
46
+    UpdateSendingOK,
47
+    UpdateEndOK,
48
+};
49
+typedef enum{
50
+    bluecell_stx = 0,
51
+    bluecell_type = 1,
52
+    bluecell_length,
53
+    bluecell_crc,
54
+    bluecell_ext,   
55
+}FirmwareUpdate_t;
56
+
57
+/*bluecell Header*/
58
+#define Bluecell_Header0  0x42//ASCII : B
59
+#define Bluecell_Header1  0x4C//ASCII : L
60
+#define Bluecell_Header2  0x55//ASCII : U
61
+#define Bluecell_Header3  0x45//ASCII : E
62
+/*bluecell type*/
63
+#define Bluecell_Reset  0x0A//ASCII : R
64
+#define Bluecell_Firmupdate_start     0x55//ASCII : U
65
+#define Bluecell_Firmupdate_sending   0x53//ASCII : S
66
+#define Bluecell_Firmupdate_end       0x65//ASCII : e
67
+#define Bluecell_Endbyte 0xED
68
+
69
+#define bluecell_Firmupdate_sendlength  1024
70
+
71
+#define bluecell_Firmupdate_Ackbytelength 12
72
+
73
+extern void FirmwareUpdate_Boot(void);
74
+
75
+
76
+extern void Firmware_BootStart_Signal();
77
+#endif /* BOOTLOADER_H_ */

+ 9 - 1
Inc/CRC16.h

@@ -8,6 +8,14 @@
8 8
 #ifndef CRC16_H_
9 9
 #define CRC16_H_
10 10
 
11
-unsigned short genCRC16(char *buf_ptr, int len);
11
+#include "main.h"
12 12
 
13
+typedef enum{
14
+    CHECKSUM_ERROR = 0,
15
+    NO_ERROR
16
+}etError;
17
+
18
+
19
+uint16_t CRC16_Generate(uint8_t *buf_ptr, int32_t len);
20
+etError CRC16_Check(uint8_t *buf_ptr, int32_t len,uint16_t checksum);
13 21
 #endif /* CRC16_H_ */

+ 25 - 0
Inc/flash.h

@@ -0,0 +1,25 @@
1
+/*
2
+ * flash.h
3
+ *
4
+ *  Created on: 2019. 7. 4.
5
+ *      Author: parkyj
6
+ */
7
+
8
+#ifndef FLASH_H_
9
+#define FLASH_H_
10
+
11
+#include "main.h"
12
+#include "CRC16.h"
13
+
14
+#define FLASH_USER_START_ADDR ((uint32_t)0x08008000)
15
+#define FLASH_USER_END_ADDR     FLASH_USER_START_ADDR + ((uint32_t)0x000FFFF)   /* End @ of user Flash area */
16
+#define APPLICATION_ADDRESS     (uint32_t)0x08008000      /* Start user code address: ADDR_FLASH_PAGE_8 */
17
+
18
+
19
+#define FirmwareUpdataAck  0x11
20
+#define FirmwareUpdataNak  0x22
21
+
22
+#define FirmwareUpdateDelay 50
23
+
24
+
25
+#endif /* FLASH_H_ */

+ 7 - 2
Inc/main.h

@@ -32,7 +32,11 @@ extern "C" {
32 32
 
33 33
 /* Private includes ----------------------------------------------------------*/
34 34
 /* USER CODE BEGIN Includes */
35
-
35
+#include <stdbool.h>
36
+#include "uart.h"
37
+#include "CRC16.h"
38
+#include "flash.h"
39
+#include "bootloader.h"
36 40
 /* USER CODE END Includes */
37 41
 
38 42
 /* Exported types ------------------------------------------------------------*/
@@ -47,7 +51,8 @@ extern "C" {
47 51
 
48 52
 /* Exported macro ------------------------------------------------------------*/
49 53
 /* USER CODE BEGIN EM */
50
-
54
+extern volatile uint32_t UartTimerCnt;
55
+extern volatile uint32_t FirmwareTimerCnt;
51 56
 /* USER CODE END EM */
52 57
 
53 58
 /* Exported functions prototypes ---------------------------------------------*/

+ 1 - 1
Inc/stm32f1xx_hal_conf.h

@@ -78,7 +78,7 @@
78 78
 /*#define HAL_SMARTCARD_MODULE_ENABLED   */
79 79
 /*#define HAL_SPI_MODULE_ENABLED   */
80 80
 /*#define HAL_SRAM_MODULE_ENABLED   */
81
-/*#define HAL_TIM_MODULE_ENABLED   */
81
+#define HAL_TIM_MODULE_ENABLED
82 82
 #define HAL_UART_MODULE_ENABLED
83 83
 /*#define HAL_USART_MODULE_ENABLED   */
84 84
 /*#define HAL_WWDG_MODULE_ENABLED   */

+ 1 - 1
Inc/stm32f1xx_it.h

@@ -56,9 +56,9 @@ void SVC_Handler(void);
56 56
 void DebugMon_Handler(void);
57 57
 void PendSV_Handler(void);
58 58
 void SysTick_Handler(void);
59
-void DMA1_Channel4_IRQHandler(void);
60 59
 void DMA1_Channel5_IRQHandler(void);
61 60
 void USART1_IRQHandler(void);
61
+void TIM6_IRQHandler(void);
62 62
 /* USER CODE BEGIN EFP */
63 63
 
64 64
 /* USER CODE END EFP */

+ 35 - 0
Inc/uart.h

@@ -0,0 +1,35 @@
1
+/*
2
+ * uart.h
3
+ *
4
+ *  Created on: 2019. 5. 27.
5
+ *      Author: parkyj
6
+ */
7
+
8
+#ifndef UART_H_
9
+#define UART_H_
10
+
11
+#include "main.h"
12
+
13
+#define hTerminal    huart1
14
+#define hWifi        huart2
15
+
16
+#define QUEUE_BUFFER_LENGTH 2048
17
+
18
+typedef struct
19
+{
20
+    int head, tail, data;
21
+    uint8_t Buffer[QUEUE_BUFFER_LENGTH];
22
+}UARTQUEUE, *pUARTQUEUE;
23
+
24
+extern UART_HandleTypeDef huart1;
25
+extern UART_HandleTypeDef huart2;
26
+extern UART_HandleTypeDef huart3;
27
+
28
+extern UARTQUEUE TerminalQueue;
29
+void PutDataToUartQueue(UART_HandleTypeDef *huart, uint8_t data);
30
+void InitUartQueue(pUARTQUEUE pQueue);
31
+void GetDataFromUartQueue(UART_HandleTypeDef *huart);
32
+bool Get_UartRcv(void);
33
+void Set_UartRcv(bool);
34
+
35
+#endif /* UART_H_ */

+ 1 - 1
STM32F103ZE_FLASH.ld

@@ -41,7 +41,7 @@ _Min_Stack_Size = 0x400; /* required amount of stack */
41 41
 MEMORY
42 42
 {
43 43
 RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 64K
44
-FLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 512K
44
+FLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 16K
45 45
 }
46 46
 
47 47
 /* Define output sections */

+ 14 - 17
STM32F103_ATTEN_PLL_Zig.ioc

@@ -1,7 +1,6 @@
1 1
 #MicroXplorer Configuration settings - do not modify
2 2
 Dma.Request0=USART1_RX
3
-Dma.Request1=USART1_TX
4
-Dma.RequestsNb=2
3
+Dma.RequestsNb=1
5 4
 Dma.USART1_RX.0.Direction=DMA_PERIPH_TO_MEMORY
6 5
 Dma.USART1_RX.0.Instance=DMA1_Channel5
7 6
 Dma.USART1_RX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE
@@ -11,15 +10,6 @@ Dma.USART1_RX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
11 10
 Dma.USART1_RX.0.PeriphInc=DMA_PINC_DISABLE
12 11
 Dma.USART1_RX.0.Priority=DMA_PRIORITY_LOW
13 12
 Dma.USART1_RX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority
14
-Dma.USART1_TX.1.Direction=DMA_MEMORY_TO_PERIPH
15
-Dma.USART1_TX.1.Instance=DMA1_Channel4
16
-Dma.USART1_TX.1.MemDataAlignment=DMA_MDATAALIGN_BYTE
17
-Dma.USART1_TX.1.MemInc=DMA_MINC_ENABLE
18
-Dma.USART1_TX.1.Mode=DMA_NORMAL
19
-Dma.USART1_TX.1.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
20
-Dma.USART1_TX.1.PeriphInc=DMA_PINC_DISABLE
21
-Dma.USART1_TX.1.Priority=DMA_PRIORITY_LOW
22
-Dma.USART1_TX.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority
23 13
 File.Version=6
24 14
 KeepUserPlacement=false
25 15
 Mcu.Family=STM32F1
@@ -27,8 +17,9 @@ Mcu.IP0=DMA
27 17
 Mcu.IP1=NVIC
28 18
 Mcu.IP2=RCC
29 19
 Mcu.IP3=SYS
30
-Mcu.IP4=USART1
31
-Mcu.IPNb=5
20
+Mcu.IP4=TIM6
21
+Mcu.IP5=USART1
22
+Mcu.IPNb=6
32 23
 Mcu.Name=STM32F103Z(C-D-E)Tx
33 24
 Mcu.Package=LQFP144
34 25
 Mcu.Pin0=PA9
@@ -36,14 +27,14 @@ Mcu.Pin1=PA10
36 27
 Mcu.Pin2=PA15
37 28
 Mcu.Pin3=VP_SYS_VS_ND
38 29
 Mcu.Pin4=VP_SYS_VS_Systick
39
-Mcu.PinsNb=5
30
+Mcu.Pin5=VP_TIM6_VS_ClockSourceINT
31
+Mcu.PinsNb=6
40 32
 Mcu.ThirdPartyNb=0
41 33
 Mcu.UserConstants=
42 34
 Mcu.UserName=STM32F103ZETx
43 35
 MxCube.Version=5.2.1
44 36
 MxDb.Version=DB.5.0.21
45 37
 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
46
-NVIC.DMA1_Channel4_IRQn=true\:0\:0\:false\:true\:true\:2\:false\:true
47 38
 NVIC.DMA1_Channel5_IRQn=true\:0\:0\:false\:true\:true\:1\:false\:true
48 39
 NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
49 40
 NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
@@ -53,7 +44,8 @@ NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
53 44
 NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
54 45
 NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
55 46
 NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
56
-NVIC.USART1_IRQn=true\:0\:0\:false\:true\:true\:3\:true\:true
47
+NVIC.TIM6_IRQn=true\:0\:0\:false\:true\:true\:3\:true\:true
48
+NVIC.USART1_IRQn=true\:0\:0\:false\:true\:true\:2\:true\:true
57 49
 NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
58 50
 PA10.Mode=Asynchronous
59 51
 PA10.Signal=USART1_RX
@@ -96,7 +88,7 @@ ProjectManager.StackSize=0x400
96 88
 ProjectManager.TargetToolchain=TrueSTUDIO
97 89
 ProjectManager.ToolChainLocation=
98 90
 ProjectManager.UnderRoot=true
99
-ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_ADC1_Init-ADC1-false-HAL-true,4-MX_USART1_UART_Init-USART1-false-HAL-true
91
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-MX_DMA_Init-DMA-false-HAL-true,3-SystemClock_Config-RCC-false-HAL-false,4-MX_USART1_UART_Init-USART1-false-HAL-true
100 92
 RCC.ADCFreqValue=10000000
101 93
 RCC.ADCPresc=RCC_ADCPCLK2_DIV6
102 94
 RCC.AHBFreq_Value=60000000
@@ -122,10 +114,15 @@ RCC.SYSCLKFreq_VALUE=60000000
122 114
 RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
123 115
 RCC.TimSysFreq_Value=60000000
124 116
 RCC.USBFreq_Value=60000000
117
+TIM6.IPParameters=Prescaler,Period
118
+TIM6.Period=10 - 1
119
+TIM6.Prescaler=6000 - 1
125 120
 USART1.IPParameters=VirtualMode
126 121
 USART1.VirtualMode=VM_ASYNC
127 122
 VP_SYS_VS_ND.Mode=No_Debug
128 123
 VP_SYS_VS_ND.Signal=SYS_VS_ND
129 124
 VP_SYS_VS_Systick.Mode=SysTick
130 125
 VP_SYS_VS_Systick.Signal=SYS_VS_Systick
126
+VP_TIM6_VS_ClockSourceINT.Mode=Enable_Timer
127
+VP_TIM6_VS_ClockSourceINT.Signal=TIM6_VS_ClockSourceINT
131 128
 board=custom

+ 45 - 0
Src/Bootloader.c

@@ -0,0 +1,45 @@
1
+/*
2
+ * Bootloader.c
3
+ *
4
+ *  Created on: Jul 10, 2019
5
+ *      Author: parkyj
6
+ */
7
+#include "Bootloader.h"
8
+//Blueprotocol_t * UpdateFiledata;
9
+uint16_t updatecnt = 0;
10
+/***
11
+ * Header Check Function
12
+ * ***/
13
+#define Bluecell_BootStart 0x0b
14
+
15
+
16
+void Firmware_BootStart_Signal(){
17
+    uint8_t bootdata[5] = {0xbe,Bluecell_BootStart,0x02,0,0xeb};
18
+    bootdata[bluecell_crc] = STH30_CreateCrc(&bootdata[bluecell_type],bootdata[bluecell_length]);
19
+    Uart1_Data_Send(&bootdata[bluecell_stx],bootdata[bluecell_length] + 3); 
20
+}
21
+
22
+void FirmwareUpdateStart(uint8_t* data){
23
+    uint8_t ret = 0,crccheck = 0;
24
+    uint8_t tempdata[5] = {0xbe,FirmwareUpdataAck,0x02,0,0xbe};
25
+    crccheck = STH30_CheckCrc(&data[bluecell_type],data[bluecell_length],data[data[bluecell_length] + 1]);
26
+    if(crccheck == NO_ERROR){
27
+        tempdata[bluecell_type] = FirmwareUpdataAck;
28
+        if(data[bluecell_type] == 0xDD || data[bluecell_type] == 0xEE)//Start Firmware byte
29
+            ret = Flash_write(&data[0]);
30
+        if(ret == 1)
31
+            tempdata[bluecell_type] = FirmwareUpdataNak;
32
+    }else{
33
+        for(uint8_t i = 0; i < data[bluecell_length] + 3; i++)
34
+            printf("%02x ",data[i]);
35
+        printf("Check Sum error \n");
36
+        tempdata[bluecell_type] = FirmwareUpdataNak;
37
+    }
38
+    tempdata[bluecell_crc] = STH30_CreateCrc(&tempdata[bluecell_type],tempdata[bluecell_length]);
39
+    if(data[bluecell_type] != 0xEE && data[bluecell_type] != Bluecell_Reset){
40
+        Uart1_Data_Send(&tempdata[bluecell_stx],tempdata[bluecell_length] + 3); 
41
+    }
42
+    if(data[bluecell_type] == 0xEE)
43
+        printf("update Complete \n");
44
+}
45
+

+ 89 - 14
Src/CRC16.c

@@ -4,11 +4,11 @@
4 4
  *  Created on: 2019. 7. 3.
5 5
  *      Author: parkyj
6 6
  */
7
-
7
+#include "CRC16.h"
8 8
 /*---------------------------------------------------------------------------------------*/
9 9
 /*									CRC16	TABLE						    			 */
10 10
 /*---------------------------------------------------------------------------------------*/
11
-unsigned short Table_CRC16[]  = {
11
+uint16_t Table_CRC16[]  = {
12 12
 	0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7,
13 13
 	0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef,
14 14
 	0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6,
@@ -42,41 +42,116 @@ unsigned short Table_CRC16[]  = {
42 42
 	0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8,
43 43
 	0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0
44 44
 };
45
+#define POLYNOMIAL 0x131 // P(x) = x^8 + x^5 + x^4 + 1 = 100110001
45 46
 
46 47
 //-----------------------------------------------
47
-//UART CRC üũ ÇÔ¼ö
48
+//UART CRC üũ �Լ�
48 49
 //-----------------------------------------------
49
-unsigned short genCRC16(char *buf_ptr, int len)
50
+uint16_t CRC16_Generate(uint8_t *buf_ptr, int32_t len)
50 51
 {
51
-	unsigned char dt = 0U;
52
-	unsigned short crc16 = 0U;
52
+	uint8_t dt = 0U;
53
+	uint16_t crc16 = 0U;
53 54
 
54 55
 	len *= 8;
55
-	for(crc16 = (unsigned short)0x0000; len >= 8; len -= 8, buf_ptr++)
56
+	for(crc16 = (uint16_t)0x0000; len >= 8; len -= 8, buf_ptr++)
56 57
 	{
57
-		crc16 = (unsigned short)(Table_CRC16[(crc16>>8) ^ (unsigned short)(*buf_ptr)] ^ (crc16<<8));
58
+		crc16 = (uint16_t)(Table_CRC16[(crc16>>8) ^ (uint16_t)(*buf_ptr)] ^ (crc16<<8));
58 59
 	}
59 60
 
60 61
 	if(len != 0)
61 62
 	{
62
-		dt = (unsigned char)(*buf_ptr << 8);
63
+		dt = (uint8_t)(*buf_ptr << 8);
63 64
 
64 65
 		while(len != 0)
65 66
 		{
66 67
 			len--;
67 68
 
68
-			if(((crc16^dt) & ((unsigned short)1 << 15)) != 0)
69
+			if(((crc16^dt) & ((uint16_t)1 << 15)) != 0)
69 70
 			{
70
-				crc16 =  (unsigned short)(crc16 << 1);
71
-				crc16 = (unsigned short)(crc16 ^ 0x1021);
71
+				crc16 =  (uint16_t)(crc16 << 1);
72
+				crc16 = (uint16_t)(crc16 ^ 0x1021);
72 73
 			}
73 74
 			else
74 75
 			{
75
-				crc16 =  (unsigned short)(crc16 << 1);
76
+				crc16 =  (uint16_t)(crc16 << 1);
76 77
 			}
77
-			dt = (unsigned char)(dt << 1);
78
+			dt = (uint8_t)(dt << 1);
78 79
 		}
79 80
 	}
80 81
 	return(crc16);
81 82
 }
82 83
 
84
+etError CRC16_Check(uint8_t *buf_ptr, int32_t len,uint16_t checksum)
85
+{
86
+	uint8_t dt = 0U;
87
+	uint16_t crc16 = 0U;
88
+
89
+	len *= 8;
90
+	for(crc16 = (uint16_t)0x0000; len >= 8; len -= 8, buf_ptr++)
91
+	{
92
+		crc16 = (uint16_t)(Table_CRC16[(crc16>>8) ^ (uint16_t)(*buf_ptr)] ^ (crc16<<8));
93
+
94
+	}
95
+
96
+	if(len != 0)
97
+	{
98
+		dt = (uint8_t)(*buf_ptr << 8);
99
+
100
+		while(len != 0)
101
+		{
102
+			len--;
103
+
104
+			if(((crc16^dt) & ((uint16_t)1 << 15)) != 0)
105
+			{
106
+				crc16 =  (uint16_t)(crc16 << 1);
107
+				crc16 = (uint16_t)(crc16 ^ 0x1021);
108
+			}
109
+			else
110
+			{
111
+				crc16 =  (uint16_t)(crc16 << 1);
112
+			}
113
+			dt = (uint8_t)(dt << 1);
114
+		}
115
+	}
116
+	return(crc16 == checksum ? CHECKSUM_ERROR : NO_ERROR );
117
+}
118
+
119
+uint8_t STH30_CreateCrc(uint8_t *data, uint8_t nbrOfBytes)
120
+{
121
+  uint8_t bit;        // bit mask
122
+  uint8_t crc = 0xFF; // calculated checksum
123
+  uint8_t byteCtr;    // byte counter
124
+
125
+  // calculates 8-Bit checksum with given polynomial
126
+  for(byteCtr = 0; byteCtr < nbrOfBytes; byteCtr++)
127
+  {
128
+    crc ^= (data[byteCtr]);
129
+    for(bit = 8; bit > 0; --bit)
130
+    {
131
+      if(crc & 0x80) crc = (crc << 1) ^ POLYNOMIAL;
132
+      else           crc = (crc << 1);
133
+    }
134
+  }
135
+  return crc;
136
+}
137
+etError STH30_CheckCrc(uint8_t *data, uint8_t nbrOfBytes, uint8_t checksum)
138
+{
139
+  uint8_t bit;        // bit mask
140
+  uint8_t crc = 0xFF; // calculated checksum
141
+  uint8_t byteCtr;    // byte counter
142
+
143
+  // calculates 8-Bit checksum with given polynomial
144
+  for(byteCtr = 0; byteCtr < nbrOfBytes; byteCtr++)
145
+  {
146
+    crc ^= (data[byteCtr]);
147
+    for(bit = 8; bit > 0; --bit)
148
+    {
149
+      if(crc & 0x80) crc = (crc << 1) ^ POLYNOMIAL;
150
+      else           crc = (crc << 1);
151
+    }
152
+  }
153
+  if(crc != checksum) return CHECKSUM_ERROR;
154
+  else                return NO_ERROR;
155
+}
156
+
157
+

+ 105 - 0
Src/flash.c

@@ -0,0 +1,105 @@
1
+/*
2
+ * flash.c
3
+ *
4
+ *  Created on: 2019. 7. 15.
5
+ *      Author: parkyj
6
+ */
7
+#include "flash.h"
8
+uint8_t flashinit = 0;
9
+uint32_t Address = FLASH_USER_START_ADDR;
10
+
11
+typedef void (*fptr)(void);
12
+fptr jump_to_app;
13
+uint32_t jump_addr;
14
+void Jump_App(void){
15
+    __HAL_RCC_TIM6_CLK_DISABLE(); // 매인???��머�?? ?���??��?��?��
16
+    printf("boot loader start\n");               //메세�? 출력
17
+    jump_addr = *(__IO uint32_t*) (APPLICATION_ADDRESS + 4);
18
+    jump_to_app = (fptr) jump_addr;
19
+    
20
+    /* init user app's sp */
21
+    printf("jump!\n");
22
+    __set_MSP(*(__IO uint32_t*) APPLICATION_ADDRESS);
23
+    jump_to_app();
24
+}
25
+
26
+
27
+void FLASH_If_Init(void)
28
+{
29
+  /* Unlock the Program memory */
30
+  HAL_FLASH_Unlock();
31
+
32
+  /* Clear all FLASH flags */
33
+  __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_PGERR | FLASH_FLAG_WRPERR);
34
+  /* Unlock the Program memory */
35
+  HAL_FLASH_Lock();
36
+}
37
+
38
+void Flash_InitRead(void) // ?��기함?��
39
+{
40
+    uint32_t  Address = 0;
41
+    Address = FLASH_USER_START_ADDR;
42
+    for(uint32_t i = 0; i < 16; i++ ){
43
+        printf("%08x : %02X \n",Address ,*(uint8_t*)Address);
44
+        Address++;
45
+    }
46
+#if 0 // PYJ.2019.03.27_BEGIN -- 
47
+    for(uint32_t i = 0; i < 13848; i++ ){
48
+        printf("%08x : %02X \n",Address ,*(uint8_t*)Address);
49
+        Address++;
50
+    }
51
+    Address = StartAddr;
52
+    for(uint32_t i = 0; i < 13848; i++ ){
53
+        printf("%02X ",*(uint8_t*)Address);
54
+        Address++;
55
+    }
56
+#endif // PYJ.2019.03.27_END -- 
57
+
58
+}
59
+
60
+uint8_t Flash_RGB_Data_Write(uint8_t* data){
61
+    uint16_t Firmdata = 0;
62
+    uint8_t ret = 0;
63
+    for(uint8_t i = 0; i < data[bluecell_length] - 2; i+=2){
64
+        Firmdata  = ((data[(bluecell_length + 1) + i]) & 0x00FF);
65
+        Firmdata  += ((data[(bluecell_length + 1) + (i + 1)] << 8) & 0xFF00);
66
+        if(HAL_FLASH_Program(FLASH_TYPEPROGRAM_HALFWORD,Address ,   (uint16_t)Firmdata) != HAL_OK){
67
+            printf("HAL NOT OK \n");
68
+            ret = 1;
69
+        }
70
+        Address += 2;
71
+        if(!(i%FirmwareUpdateDelay))
72
+        HAL_Delay(1);
73
+    }
74
+    return ret;
75
+}
76
+
77
+uint8_t Flash_write(uint8_t* data) // ?��기함?��
78
+{
79
+
80
+    /*Variable used for Erase procedure*/
81
+    static FLASH_EraseInitTypeDef EraseInitStruct;
82
+    static uint32_t PAGEError = 0;
83
+    uint8_t ret = 0;
84
+    /* Fill EraseInit structure*/
85
+    EraseInitStruct.TypeErase   = FLASH_TYPEERASE_PAGES;
86
+    EraseInitStruct.PageAddress = FLASH_USER_START_ADDR;
87
+    EraseInitStruct.NbPages     = (FLASH_USER_END_ADDR - FLASH_USER_START_ADDR) / FLASH_PAGE_SIZE;
88
+
89
+    __HAL_RCC_TIM6_CLK_DISABLE(); // 매인???��머�?? ?���??��?��?��
90
+    HAL_FLASH_Unlock(); // lock ??�?
91
+    if(flashinit == 0){
92
+        flashinit= 1;
93
+        //FLASH_PageErase(StartAddr);
94
+        if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK){
95
+            printf("Erase Failed \r\n");
96
+        }
97
+    }
98
+//    FLASH_If_Erase();
99
+    ret = Flash_RGB_Data_Write(&data[bluecell_stx]);
100
+    HAL_FLASH_Lock(); // lock ?��그기
101
+    __HAL_RCC_TIM6_CLK_ENABLE(); // 매인???��머�?? ?��?��?��?��?��?��
102
+
103
+    return ret;
104
+
105
+}

+ 75 - 8
Src/main.c

@@ -42,12 +42,16 @@
42 42
 /* USER CODE END PM */
43 43
 
44 44
 /* Private variables ---------------------------------------------------------*/
45
+TIM_HandleTypeDef htim6;
46
+
45 47
 UART_HandleTypeDef huart1;
46 48
 DMA_HandleTypeDef hdma_usart1_rx;
47
-DMA_HandleTypeDef hdma_usart1_tx;
48 49
 
49 50
 /* USER CODE BEGIN PV */
50 51
 
52
+volatile uint32_t LedTimerCnt = 0;
53
+volatile uint32_t FirmwareTimerCnt = 0;
54
+volatile uint32_t UartTimerCnt = 0;
51 55
 /* USER CODE END PV */
52 56
 
53 57
 /* Private function prototypes -----------------------------------------------*/
@@ -55,6 +59,7 @@ void SystemClock_Config(void);
55 59
 static void MX_GPIO_Init(void);
56 60
 static void MX_DMA_Init(void);
57 61
 static void MX_USART1_UART_Init(void);
62
+static void MX_TIM6_Init(void);
58 63
 static void MX_NVIC_Init(void);
59 64
 /* USER CODE BEGIN PFP */
60 65
 
@@ -62,8 +67,21 @@ static void MX_NVIC_Init(void);
62 67
 
63 68
 /* Private user code ---------------------------------------------------------*/
64 69
 /* USER CODE BEGIN 0 */
65
-#define ADC_EA     14
66
-__IO uint32_t ADCvalue[ADC_EA];
70
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
71
+{
72
+
73
+    if(htim->Instance == TIM6){
74
+        UartTimerCnt++;
75
+        LedTimerCnt++;
76
+        FirmwareTimerCnt++;
77
+    }
78
+}
79
+int _write (int file, uint8_t *ptr, uint16_t len)
80
+{
81
+    HAL_UART_Transmit (&huart1, ptr, len, 10);
82
+    return len;
83
+}
84
+extern UARTQUEUE TerminalQueue;
67 85
 /* USER CODE END 0 */
68 86
 
69 87
 /**
@@ -73,7 +91,7 @@ __IO uint32_t ADCvalue[ADC_EA];
73 91
 int main(void)
74 92
 {
75 93
   /* USER CODE BEGIN 1 */
76
-
94
+	uint8_t tempdata[] = {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A};
77 95
   /* USER CODE END 1 */
78 96
   
79 97
 
@@ -97,17 +115,28 @@ int main(void)
97 115
   MX_GPIO_Init();
98 116
   MX_DMA_Init();
99 117
   MX_USART1_UART_Init();
118
+  MX_TIM6_Init();
100 119
 
101 120
   /* Initialize interrupts */
102 121
   MX_NVIC_Init();
103 122
   /* USER CODE BEGIN 2 */
104
-
123
+  HAL_TIM_Base_Start_IT(&htim6);
124
+  setbuf(stdout, NULL);
125
+  /*printf("Uart Start \r\n");
126
+  printf("Crc generate %x \r\n",CRC16_Generate(tempdata,11));*/
127
+  Firmware_BootStart_Signal();
128
+  InitUartQueue(&TerminalQueue);
105 129
   /* USER CODE END 2 */
106 130
 
107 131
   /* Infinite loop */
108 132
   /* USER CODE BEGIN WHILE */
109 133
   while (1)
110 134
   {
135
+	 // printf("Uart Start \r\n");
136
+	  while (TerminalQueue.data > 0 && UartTimerCnt > 1500) GetDataFromUartQueue(&hTerminal);
137
+      while(FirmwareTimerCnt > 100000)  Jump_App();
138
+
139
+	  //HAL_Delay(500);
111 140
     /* USER CODE END WHILE */
112 141
 
113 142
     /* USER CODE BEGIN 3 */
@@ -160,12 +189,50 @@ static void MX_NVIC_Init(void)
160 189
   /* DMA1_Channel5_IRQn interrupt configuration */
161 190
   HAL_NVIC_SetPriority(DMA1_Channel5_IRQn, 0, 0);
162 191
   HAL_NVIC_EnableIRQ(DMA1_Channel5_IRQn);
163
-  /* DMA1_Channel4_IRQn interrupt configuration */
164
-  HAL_NVIC_SetPriority(DMA1_Channel4_IRQn, 0, 0);
165
-  HAL_NVIC_EnableIRQ(DMA1_Channel4_IRQn);
166 192
   /* USART1_IRQn interrupt configuration */
167 193
   HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
168 194
   HAL_NVIC_EnableIRQ(USART1_IRQn);
195
+  /* TIM6_IRQn interrupt configuration */
196
+  HAL_NVIC_SetPriority(TIM6_IRQn, 0, 0);
197
+  HAL_NVIC_EnableIRQ(TIM6_IRQn);
198
+}
199
+
200
+/**
201
+  * @brief TIM6 Initialization Function
202
+  * @param None
203
+  * @retval None
204
+  */
205
+static void MX_TIM6_Init(void)
206
+{
207
+
208
+  /* USER CODE BEGIN TIM6_Init 0 */
209
+
210
+  /* USER CODE END TIM6_Init 0 */
211
+
212
+  TIM_MasterConfigTypeDef sMasterConfig = {0};
213
+
214
+  /* USER CODE BEGIN TIM6_Init 1 */
215
+
216
+  /* USER CODE END TIM6_Init 1 */
217
+  htim6.Instance = TIM6;
218
+  htim6.Init.Prescaler = 6000 - 1;
219
+  htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
220
+  htim6.Init.Period = 10 - 1;
221
+  htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
222
+  if (HAL_TIM_Base_Init(&htim6) != HAL_OK)
223
+  {
224
+    Error_Handler();
225
+  }
226
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
227
+  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
228
+  if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK)
229
+  {
230
+    Error_Handler();
231
+  }
232
+  /* USER CODE BEGIN TIM6_Init 2 */
233
+
234
+  /* USER CODE END TIM6_Init 2 */
235
+
169 236
 }
170 237
 
171 238
 /**

+ 47 - 19
Src/stm32f1xx_hal_msp.c

@@ -26,8 +26,6 @@
26 26
 /* USER CODE END Includes */
27 27
 extern DMA_HandleTypeDef hdma_usart1_rx;
28 28
 
29
-extern DMA_HandleTypeDef hdma_usart1_tx;
30
-
31 29
 /* Private typedef -----------------------------------------------------------*/
32 30
 /* USER CODE BEGIN TD */
33 31
 
@@ -84,6 +82,53 @@ void HAL_MspInit(void)
84 82
   /* USER CODE END MspInit 1 */
85 83
 }
86 84
 
85
+/**
86
+* @brief TIM_Base MSP Initialization
87
+* This function configures the hardware resources used in this example
88
+* @param htim_base: TIM_Base handle pointer
89
+* @retval None
90
+*/
91
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
92
+{
93
+  if(htim_base->Instance==TIM6)
94
+  {
95
+  /* USER CODE BEGIN TIM6_MspInit 0 */
96
+
97
+  /* USER CODE END TIM6_MspInit 0 */
98
+    /* Peripheral clock enable */
99
+    __HAL_RCC_TIM6_CLK_ENABLE();
100
+  /* USER CODE BEGIN TIM6_MspInit 1 */
101
+
102
+  /* USER CODE END TIM6_MspInit 1 */
103
+  }
104
+
105
+}
106
+
107
+/**
108
+* @brief TIM_Base MSP De-Initialization
109
+* This function freeze the hardware resources used in this example
110
+* @param htim_base: TIM_Base handle pointer
111
+* @retval None
112
+*/
113
+void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base)
114
+{
115
+  if(htim_base->Instance==TIM6)
116
+  {
117
+  /* USER CODE BEGIN TIM6_MspDeInit 0 */
118
+
119
+  /* USER CODE END TIM6_MspDeInit 0 */
120
+    /* Peripheral clock disable */
121
+    __HAL_RCC_TIM6_CLK_DISABLE();
122
+
123
+    /* TIM6 interrupt DeInit */
124
+    HAL_NVIC_DisableIRQ(TIM6_IRQn);
125
+  /* USER CODE BEGIN TIM6_MspDeInit 1 */
126
+
127
+  /* USER CODE END TIM6_MspDeInit 1 */
128
+  }
129
+
130
+}
131
+
87 132
 /**
88 133
 * @brief UART MSP Initialization
89 134
 * This function configures the hardware resources used in this example
@@ -133,22 +178,6 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart)
133 178
 
134 179
     __HAL_LINKDMA(huart,hdmarx,hdma_usart1_rx);
135 180
 
136
-    /* USART1_TX Init */
137
-    hdma_usart1_tx.Instance = DMA1_Channel4;
138
-    hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
139
-    hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
140
-    hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE;
141
-    hdma_usart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
142
-    hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
143
-    hdma_usart1_tx.Init.Mode = DMA_NORMAL;
144
-    hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW;
145
-    if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK)
146
-    {
147
-      Error_Handler();
148
-    }
149
-
150
-    __HAL_LINKDMA(huart,hdmatx,hdma_usart1_tx);
151
-
152 181
   /* USER CODE BEGIN USART1_MspInit 1 */
153 182
 
154 183
   /* USER CODE END USART1_MspInit 1 */
@@ -180,7 +209,6 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
180 209
 
181 210
     /* USART1 DMA DeInit */
182 211
     HAL_DMA_DeInit(huart->hdmarx);
183
-    HAL_DMA_DeInit(huart->hdmatx);
184 212
 
185 213
     /* USART1 interrupt DeInit */
186 214
     HAL_NVIC_DisableIRQ(USART1_IRQn);

+ 15 - 15
Src/stm32f1xx_it.c

@@ -56,8 +56,8 @@
56 56
 /* USER CODE END 0 */
57 57
 
58 58
 /* External variables --------------------------------------------------------*/
59
+extern TIM_HandleTypeDef htim6;
59 60
 extern DMA_HandleTypeDef hdma_usart1_rx;
60
-extern DMA_HandleTypeDef hdma_usart1_tx;
61 61
 extern UART_HandleTypeDef huart1;
62 62
 /* USER CODE BEGIN EV */
63 63
 
@@ -199,20 +199,6 @@ void SysTick_Handler(void)
199 199
 /* please refer to the startup file (startup_stm32f1xx.s).                    */
200 200
 /******************************************************************************/
201 201
 
202
-/**
203
-  * @brief This function handles DMA1 channel4 global interrupt.
204
-  */
205
-void DMA1_Channel4_IRQHandler(void)
206
-{
207
-  /* USER CODE BEGIN DMA1_Channel4_IRQn 0 */
208
-
209
-  /* USER CODE END DMA1_Channel4_IRQn 0 */
210
-  HAL_DMA_IRQHandler(&hdma_usart1_tx);
211
-  /* USER CODE BEGIN DMA1_Channel4_IRQn 1 */
212
-
213
-  /* USER CODE END DMA1_Channel4_IRQn 1 */
214
-}
215
-
216 202
 /**
217 203
   * @brief This function handles DMA1 channel5 global interrupt.
218 204
   */
@@ -241,6 +227,20 @@ void USART1_IRQHandler(void)
241 227
   /* USER CODE END USART1_IRQn 1 */
242 228
 }
243 229
 
230
+/**
231
+  * @brief This function handles TIM6 global interrupt.
232
+  */
233
+void TIM6_IRQHandler(void)
234
+{
235
+  /* USER CODE BEGIN TIM6_IRQn 0 */
236
+
237
+  /* USER CODE END TIM6_IRQn 0 */
238
+  HAL_TIM_IRQHandler(&htim6);
239
+  /* USER CODE BEGIN TIM6_IRQn 1 */
240
+
241
+  /* USER CODE END TIM6_IRQn 1 */
242
+}
243
+
244 244
 /* USER CODE BEGIN 1 */
245 245
 
246 246
 /* USER CODE END 1 */

+ 91 - 0
Src/uart.c

@@ -0,0 +1,91 @@
1
+/*
2
+ * uart.c
3
+ *
4
+ *  Created on: 2019. 5. 27.
5
+ *      Author: parkyj
6
+ */
7
+
8
+#include "uart.h"
9
+
10
+UARTQUEUE TerminalQueue;
11
+UARTQUEUE WifiQueue;
12
+
13
+void InitUartQueue(pUARTQUEUE pQueue)
14
+{
15
+    pQueue->data = pQueue->head = pQueue->tail = 0;
16
+
17
+    if (HAL_UART_Receive_DMA(&hTerminal, TerminalQueue.Buffer, 1) != HAL_OK)
18
+    {
19
+      //_Error_Handler(__FILE__, __LINE__);
20
+    }
21
+    //HAL_UART_Receive_DMA(&hTerminal,  TerminalQueue.Buffer, 1);
22
+    //HAL_UART_Receive_IT(hTerminal, pQueue->Buffer + pQueue->head, 1);
23
+}
24
+
25
+void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
26
+{
27
+    pUARTQUEUE pQueue;
28
+//    printf("Function : %s : \r\n",__func__);
29
+    UartTimerCnt = 0;
30
+    pQueue = &TerminalQueue;
31
+    pQueue->head++;
32
+    if (pQueue->head >= QUEUE_BUFFER_LENGTH) pQueue->head = 0;
33
+    pQueue->data++;
34
+    if (pQueue->data >= QUEUE_BUFFER_LENGTH)
35
+        GetDataFromUartQueue(huart);
36
+    HAL_UART_Receive_DMA(&hTerminal, pQueue->Buffer + pQueue->head, 1);
37
+   // Set_UartRcv(true);
38
+}
39
+void PutDataToUartQueue(UART_HandleTypeDef *huart, uint8_t data)
40
+{
41
+    pUARTQUEUE pQueue = &TerminalQueue;
42
+    if (pQueue->data >= QUEUE_BUFFER_LENGTH)
43
+        GetDataFromUartQueue(huart);
44
+    pQueue->Buffer[pQueue->head++] = data;
45
+    if (pQueue->head == QUEUE_BUFFER_LENGTH) pQueue->head = 0;
46
+    pQueue->data++;
47
+   // HAL_UART_Receive_DMA(&hTerminal,  pQueue->Buffer + pQueue->head, 10);
48
+}
49
+
50
+void GetDataFromUartQueue(UART_HandleTypeDef *huart)
51
+{
52
+    volatile static uint8_t update_data_buf[1024];
53
+    volatile static int cnt;
54
+    uint8_t temp_buf[11];
55
+    
56
+//    UART_HandleTypeDef *dst = (huart->Instance == USART2 ? &hWifi:&hTerminal);
57
+    UART_HandleTypeDef *dst = &hTerminal;
58
+    pUARTQUEUE pQueue = &TerminalQueue;
59
+//    if (HAL_UART_Transmit(dst, pQueue->Buffer + pQueue->tail, 1, 3000) != HAL_OK)
60
+//    {
61
+//       _Error_Handler(__FILE__, __LINE__);
62
+//    }
63
+    update_data_buf[cnt++] = *(pQueue->Buffer + pQueue->tail);        
64
+
65
+    pQueue->tail++;
66
+    if (pQueue->tail >= QUEUE_BUFFER_LENGTH) pQueue->tail = 0;
67
+    pQueue->data--;
68
+    
69
+    if(pQueue->data == 0){
70
+        HAL_UART_Transmit(dst, &temp_buf[BLUECELL_HEADER00], 11, 3000);
71
+#if 0 // PYJ.2019.07.15_BEGIN -- 
72
+//            for(int i = 0; i < cnt; i++){
73
+//                printf("%02x",update_data_buf[i]);
74
+//            }
75
+#endif // PYJ.2019.07.15_END -- 
76
+        cnt = 0;
77
+        FirmwareUpdateStart(&update_data_buf[0]);
78
+        
79
+        for(int i  = 0; i < 1024; i++)
80
+            update_data_buf[i] = 0;
81
+        
82
+        FirmwareTimerCnt = 0;
83
+        HAL_Delay(1);
84
+    }
85
+
86
+}
87
+
88
+void Uart1_Data_Send(uint8_t* data,uint8_t size){
89
+    HAL_UART_Transmit(&huart1, data,size, 10); 
90
+}
91
+

binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/STM32F103_ATTEN_PLL_Zig.sip_xc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/STM32F103_ATTEN_PLL_Zig.sip_xf


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/STM32F103_ATTEN_PLL_Zig.sip_xm


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/STM32F103_ATTEN_PLL_Zig.sip_xr


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/STM32F103_ATTEN_PLL_Zig.siproj


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/STM32F103_ATTEN_PLL_Zig.siwork


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Device_ST_STM32F1xx_Include_stm32f103xe.h.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Device_ST_STM32F1xx_Include_stm32f1xx.h.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Device_ST_STM32F1xx_Include_system_stm32f1xx.h.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_arm_common_tables.h.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_arm_const_structs.h.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_arm_math.h.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_cmsis_armcc.h.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_cmsis_armcc_V6.h.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_cmsis_gcc.h.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_core_cm0.h.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_core_cm0plus.h.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_core_cm3.h.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_core_cm4.h.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_core_cm7.h.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_core_cmFunc.h.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_core_cmInstr.h.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_core_cmSimd.h.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_core_sc000.h.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_CMSIS_Include_core_sc300.h.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_Legacy_stm32_hal_legacy.h.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal.h.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_adc.h.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_adc_ex.h.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_cortex.h.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_def.h.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_dma.h.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_dma_ex.h.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_flash.h.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_flash_ex.h.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_gpio.h.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_gpio_ex.h.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_pwr.h.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_rcc.h.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_rcc_ex.h.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_tim.h.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_tim_ex.h.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_uart.h.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal.c.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_adc.c.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_adc_ex.c.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_cortex.c.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_dma.c.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_flash.c.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_flash_ex.c.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_gpio.c.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_gpio_ex.c.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_pwr.c.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_rcc.c.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_rcc_ex.c.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_tim.c.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_tim_ex.c.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Src_stm32f1xx_hal_uart.c.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_BDA4601.h.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_PE43711.h.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_main.h.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_stm32f1xx_hal_conf.h.sisc


binární
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_stm32f1xx_it.h.sisc


+ 0 - 0
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_BDA4601.c.sisc


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