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ADC Option 수정 ADC 14개 추가

YJ 6 年之前
父节点
当前提交
17c378afab
共有 21 个文件被更改,包括 866 次插入41 次删除
  1. 1 1
      Inc/main.h
  2. 69 29
      STM32F103_ATTEN_PLL_Zig.ioc
  3. 二进制
      STM32F103_ATTEN_PLL_Zig.pdf
  4. 8 2
      STM32F103_ATTEN_PLL_Zig.txt
  5. 28 0
      Src/BDA4601.c
  6. 3 1
      Src/PE43711.c
  7. 90 3
      Src/main.c
  8. 5 5
      Src/stm32f1xx_hal_msp.c
  9. 8 0
      insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/BDA4601(3412).c
  10. 440 0
      insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/main(5556).c
  11. 214 0
      insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/stm32f1xx_hal_def(7893).h
  12. 二进制
      insight/STM32F103_ATTEN_PLL_Zig.si4project/STM32F103_ATTEN_PLL_Zig.sip_xab
  13. 二进制
      insight/STM32F103_ATTEN_PLL_Zig.si4project/STM32F103_ATTEN_PLL_Zig.sip_xad
  14. 二进制
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_def.h.sisc
  15. 二进制
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_stm32f1xx_hal_conf.h.sisc
  16. 二进制
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_stm32f1xx_it.h.sisc
  17. 二进制
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_BDA4601.c.sisc
  18. 二进制
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_PE43711.c.sisc
  19. 二进制
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_main.c.sisc
  20. 二进制
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_stm32f1xx_hal_msp.c.sisc
  21. 二进制
      insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_stm32f1xx_it.c.sisc

+ 1 - 1
Inc/main.h

@@ -29,7 +29,7 @@ extern "C" {
29 29
 
30 30
 /* Includes ------------------------------------------------------------------*/
31 31
 #include "stm32f1xx_hal.h"
32
-#include "PE43711.h"
32
+
33 33
 /* Private includes ----------------------------------------------------------*/
34 34
 /* USER CODE BEGIN Includes */
35 35
 

文件差异内容过多而无法显示
+ 69 - 29
STM32F103_ATTEN_PLL_Zig.ioc


二进制
STM32F103_ATTEN_PLL_Zig.pdf


+ 8 - 2
STM32F103_ATTEN_PLL_Zig.txt

@@ -20,7 +20,8 @@ ADC1	IN10	ADC1_IN10	PC0
20 20
 ADC1	IN11	ADC1_IN11	PC1
21 21
 ADC1	IN12	ADC1_IN12	PC2
22 22
 ADC1	IN13	ADC1_IN13	PC3
23
-SYS	No Debug	SYS_VS_ND	VP_SYS_VS_ND
23
+SYS	Serial Wire	SYS_JTCK-SWCLK	PA14
24
+SYS	Serial Wire	SYS_JTMS-SWDIO	PA13
24 25
 SYS	SysTick	SYS_VS_Systick	VP_SYS_VS_Systick
25 26
 USART1	Asynchronous	USART1_RX	PA10
26 27
 USART1	Asynchronous	USART1_TX	PA9
@@ -80,6 +81,8 @@ Pin Nb	PINs	FUNCTIONs	LABELs
80 81
 99	PC9	GPIO_Input	PLL_LD_3.5G_H
81 82
 101	PA9	USART1_TX	
82 83
 102	PA10	USART1_RX	
84
+105	PA13	SYS_JTMS-SWDIO	
85
+109	PA14	SYS_JTCK-SWCLK	
83 86
 114	PD0	GPIO_Output	ATT_CLK_3.5G
84 87
 115	PD1	GPIO_Output	ATT_EN_3.5G
85 88
 116	PD2	GPIO_Output	ATT_DATA_3.5G_DL
@@ -114,7 +117,8 @@ ADC1	IN10	ADC1_IN10	PC0
114 117
 ADC1	IN11	ADC1_IN11	PC1
115 118
 ADC1	IN12	ADC1_IN12	PC2
116 119
 ADC1	IN13	ADC1_IN13	PC3
117
-SYS	No Debug	SYS_VS_ND	VP_SYS_VS_ND
120
+SYS	Serial Wire	SYS_JTCK-SWCLK	PA14
121
+SYS	Serial Wire	SYS_JTMS-SWDIO	PA13
118 122
 SYS	SysTick	SYS_VS_Systick	VP_SYS_VS_Systick
119 123
 USART1	Asynchronous	USART1_RX	PA10
120 124
 USART1	Asynchronous	USART1_TX	PA9
@@ -174,6 +178,8 @@ Pin Nb	PINs	FUNCTIONs	LABELs
174 178
 99	PC9	GPIO_Input	PLL_LD_3.5G_H
175 179
 101	PA9	USART1_TX	
176 180
 102	PA10	USART1_RX	
181
+105	PA13	SYS_JTMS-SWDIO	
182
+109	PA14	SYS_JTCK-SWCLK	
177 183
 114	PD0	GPIO_Output	ATT_CLK_3.5G
178 184
 115	PD1	GPIO_Output	ATT_EN_3.5G
179 185
 116	PD2	GPIO_Output	ATT_DATA_3.5G_DL

+ 28 - 0
Src/BDA4601.c

@@ -4,5 +4,33 @@
4 4
  *  Created on: 2019. 6. 28.
5 5
  *      Author: parkyj
6 6
  */
7
+void BDA4601_atten_ctrl(PE43711_st* type ,double data){
8
+    uint8_t i = 0;
9
+    uint8_t temp = 0;
10
+    data = 4 * data;
11
+    temp = (uint8_t)data;
12
+    HAL_GPIO_WritePin(GPIOB,GPIO_PIN_1,GPIO_PIN_RESET);
13
+    HAL_Delay(1);
14
+    for(i = 0; i < 8; i++){
15
+        if((uint8_t)temp & 0x01){
16
+           HAL_GPIO_WritePin(GPIOB,GPIO_PIN_15,GPIO_PIN_SET);//DATA
17
+        }
18
+           else{
19
+           HAL_GPIO_WritePin(GPIOB,GPIO_PIN_15,GPIO_PIN_RESET);//DATA
20
+           }
21
+
22
+        HAL_GPIO_WritePin(GPIOB,GPIO_PIN_2,GPIO_PIN_SET);//CLOCK
23
+        HAL_Delay(1);
24
+        HAL_GPIO_WritePin(GPIOB,GPIO_PIN_2,GPIO_PIN_RESET);//CLOCK
25
+        HAL_Delay(1);
26
+        temp >>= 1;
27
+    }
28
+    HAL_GPIO_WritePin(GPIOB,GPIO_PIN_2,GPIO_PIN_RESET);//CLOCK
29
+    HAL_GPIO_WritePin(GPIOB,GPIO_PIN_15,GPIO_PIN_RESET);//DATA
30
+    HAL_Delay(5);
31
+    HAL_GPIO_WritePin(GPIOB,GPIO_PIN_1,GPIO_PIN_SET);//LE
32
+    HAL_Delay(1);
33
+    HAL_GPIO_WritePin(GPIOB,GPIO_PIN_1,GPIO_PIN_RESET);
34
+}
7 35
 
8 36
 

+ 3 - 1
Src/PE43711.c

@@ -75,11 +75,12 @@ void PE43711_PinInit(void){
75 75
     
76 76
 }
77 77
 
78
-void PE43711_atten_ctrl(PE43711_st* type ,double data){
78
+void PE43711_atten_ctrl(PE43711_st* Atten_xGhz ,double data){
79 79
     uint8_t i = 0;
80 80
     uint8_t temp = 0;
81 81
     data = 4 * data;
82 82
     temp = (uint8_t)data;
83
+    
83 84
     HAL_GPIO_WritePin(GPIOB,GPIO_PIN_1,GPIO_PIN_RESET);
84 85
     HAL_Delay(1);
85 86
     for(i = 0; i < 8; i++){
@@ -96,6 +97,7 @@ void PE43711_atten_ctrl(PE43711_st* type ,double data){
96 97
 		HAL_Delay(1);
97 98
 		temp >>= 1;
98 99
     }
100
+    
99 101
 	HAL_GPIO_WritePin(GPIOB,GPIO_PIN_2,GPIO_PIN_RESET);//CLOCK
100 102
     HAL_GPIO_WritePin(GPIOB,GPIO_PIN_15,GPIO_PIN_RESET);//DATA
101 103
     HAL_Delay(5);

+ 90 - 3
Src/main.c

@@ -64,7 +64,8 @@ static void MX_NVIC_Init(void);
64 64
 
65 65
 /* Private user code ---------------------------------------------------------*/
66 66
 /* USER CODE BEGIN 0 */
67
-
67
+#define ADC_EA     14
68
+__IO uint32_t ADCvalue[ADC_EA];
68 69
 /* USER CODE END 0 */
69 70
 
70 71
 /**
@@ -108,6 +109,8 @@ int main(void)
108 109
 
109 110
   /* Infinite loop */
110 111
   /* USER CODE BEGIN WHILE */
112
+  while(HAL_ADCEx_Calibration_Start(&hadc1) != HAL_OK); //ADC Calibration 
113
+   HAL_ADC_Start_DMA(&hadc1, (uint32_t*)adcVal, ADC_EA);  
111 114
   while (1)
112 115
   {
113 116
     /* USER CODE END WHILE */
@@ -192,11 +195,11 @@ static void MX_ADC1_Init(void)
192 195
   */
193 196
   hadc1.Instance = ADC1;
194 197
   hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE;
195
-  hadc1.Init.ContinuousConvMode = DISABLE;
198
+  hadc1.Init.ContinuousConvMode = ENABLE;
196 199
   hadc1.Init.DiscontinuousConvMode = DISABLE;
197 200
   hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
198 201
   hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
199
-  hadc1.Init.NbrOfConversion = 2;
202
+  hadc1.Init.NbrOfConversion = 14;
200 203
   if (HAL_ADC_Init(&hadc1) != HAL_OK)
201 204
   {
202 205
     Error_Handler();
@@ -217,6 +220,90 @@ static void MX_ADC1_Init(void)
217 220
   {
218 221
     Error_Handler();
219 222
   }
223
+  /** Configure Regular Channel 
224
+  */
225
+  sConfig.Rank = ADC_REGULAR_RANK_3;
226
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
227
+  {
228
+    Error_Handler();
229
+  }
230
+  /** Configure Regular Channel 
231
+  */
232
+  sConfig.Rank = ADC_REGULAR_RANK_4;
233
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
234
+  {
235
+    Error_Handler();
236
+  }
237
+  /** Configure Regular Channel 
238
+  */
239
+  sConfig.Rank = ADC_REGULAR_RANK_5;
240
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
241
+  {
242
+    Error_Handler();
243
+  }
244
+  /** Configure Regular Channel 
245
+  */
246
+  sConfig.Rank = ADC_REGULAR_RANK_6;
247
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
248
+  {
249
+    Error_Handler();
250
+  }
251
+  /** Configure Regular Channel 
252
+  */
253
+  sConfig.Rank = ADC_REGULAR_RANK_7;
254
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
255
+  {
256
+    Error_Handler();
257
+  }
258
+  /** Configure Regular Channel 
259
+  */
260
+  sConfig.Rank = ADC_REGULAR_RANK_8;
261
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
262
+  {
263
+    Error_Handler();
264
+  }
265
+  /** Configure Regular Channel 
266
+  */
267
+  sConfig.Rank = ADC_REGULAR_RANK_9;
268
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
269
+  {
270
+    Error_Handler();
271
+  }
272
+  /** Configure Regular Channel 
273
+  */
274
+  sConfig.Rank = ADC_REGULAR_RANK_10;
275
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
276
+  {
277
+    Error_Handler();
278
+  }
279
+  /** Configure Regular Channel 
280
+  */
281
+  sConfig.Rank = ADC_REGULAR_RANK_11;
282
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
283
+  {
284
+    Error_Handler();
285
+  }
286
+  /** Configure Regular Channel 
287
+  */
288
+  sConfig.Rank = ADC_REGULAR_RANK_12;
289
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
290
+  {
291
+    Error_Handler();
292
+  }
293
+  /** Configure Regular Channel 
294
+  */
295
+  sConfig.Rank = ADC_REGULAR_RANK_13;
296
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
297
+  {
298
+    Error_Handler();
299
+  }
300
+  /** Configure Regular Channel 
301
+  */
302
+  sConfig.Rank = ADC_REGULAR_RANK_14;
303
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
304
+  {
305
+    Error_Handler();
306
+  }
220 307
   /* USER CODE BEGIN ADC1_Init 2 */
221 308
 
222 309
   /* USER CODE END ADC1_Init 2 */

+ 5 - 5
Src/stm32f1xx_hal_msp.c

@@ -73,9 +73,9 @@ void HAL_MspInit(void)
73 73
 
74 74
   /* System interrupt init*/
75 75
 
76
-  /** DISABLE: JTAG-DP Disabled and SW-DP Disabled 
76
+  /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled 
77 77
   */
78
-  __HAL_AFIO_REMAP_SWJ_DISABLE();
78
+  __HAL_AFIO_REMAP_SWJ_NOJTAG();
79 79
 
80 80
   /* USER CODE BEGIN MspInit 1 */
81 81
 
@@ -137,9 +137,9 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
137 137
     hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY;
138 138
     hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE;
139 139
     hdma_adc1.Init.MemInc = DMA_MINC_ENABLE;
140
-    hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
141
-    hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
142
-    hdma_adc1.Init.Mode = DMA_CIRCULAR;
140
+    hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
141
+    hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
142
+    hdma_adc1.Init.Mode = DMA_NORMAL;
143 143
     hdma_adc1.Init.Priority = DMA_PRIORITY_LOW;
144 144
     if (HAL_DMA_Init(&hdma_adc1) != HAL_OK)
145 145
     {

+ 8 - 0
insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/BDA4601(3412).c

@@ -0,0 +1,8 @@
1
+/*
2
+ * BDA4601.c
3
+ *
4
+ *  Created on: 2019. 6. 28.
5
+ *      Author: parkyj
6
+ */
7
+
8
+

+ 440 - 0
insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/main(5556).c

@@ -0,0 +1,440 @@
1
+/* USER CODE BEGIN Header */
2
+/**
3
+  ******************************************************************************
4
+  * @file           : main.c
5
+  * @brief          : Main program body
6
+  ******************************************************************************
7
+  * @attention
8
+  *
9
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
10
+  * All rights reserved.</center></h2>
11
+  *
12
+  * This software component is licensed by ST under BSD 3-Clause license,
13
+  * the "License"; You may not use this file except in compliance with the
14
+  * License. You may obtain a copy of the License at:
15
+  *                        opensource.org/licenses/BSD-3-Clause
16
+  *
17
+  ******************************************************************************
18
+  */
19
+/* USER CODE END Header */
20
+
21
+/* Includes ------------------------------------------------------------------*/
22
+#include "main.h"
23
+
24
+/* Private includes ----------------------------------------------------------*/
25
+/* USER CODE BEGIN Includes */
26
+
27
+/* USER CODE END Includes */
28
+
29
+/* Private typedef -----------------------------------------------------------*/
30
+/* USER CODE BEGIN PTD */
31
+
32
+/* USER CODE END PTD */
33
+
34
+/* Private define ------------------------------------------------------------*/
35
+/* USER CODE BEGIN PD */
36
+
37
+/* USER CODE END PD */
38
+
39
+/* Private macro -------------------------------------------------------------*/
40
+/* USER CODE BEGIN PM */
41
+
42
+/* USER CODE END PM */
43
+
44
+/* Private variables ---------------------------------------------------------*/
45
+ADC_HandleTypeDef hadc1;
46
+DMA_HandleTypeDef hdma_adc1;
47
+
48
+UART_HandleTypeDef huart1;
49
+
50
+/* USER CODE BEGIN PV */
51
+
52
+/* USER CODE END PV */
53
+
54
+/* Private function prototypes -----------------------------------------------*/
55
+void SystemClock_Config(void);
56
+static void MX_GPIO_Init(void);
57
+static void MX_DMA_Init(void);
58
+static void MX_ADC1_Init(void);
59
+static void MX_USART1_UART_Init(void);
60
+static void MX_NVIC_Init(void);
61
+/* USER CODE BEGIN PFP */
62
+
63
+/* USER CODE END PFP */
64
+
65
+/* Private user code ---------------------------------------------------------*/
66
+/* USER CODE BEGIN 0 */
67
+
68
+/* USER CODE END 0 */
69
+
70
+/**
71
+  * @brief  The application entry point.
72
+  * @retval int
73
+  */
74
+int main(void)
75
+{
76
+  /* USER CODE BEGIN 1 */
77
+
78
+  /* USER CODE END 1 */
79
+  
80
+
81
+  /* MCU Configuration--------------------------------------------------------*/
82
+
83
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
84
+  HAL_Init();
85
+
86
+  /* USER CODE BEGIN Init */
87
+
88
+  /* USER CODE END Init */
89
+
90
+  /* Configure the system clock */
91
+  SystemClock_Config();
92
+
93
+  /* USER CODE BEGIN SysInit */
94
+
95
+  /* USER CODE END SysInit */
96
+
97
+  /* Initialize all configured peripherals */
98
+  MX_GPIO_Init();
99
+  MX_DMA_Init();
100
+  MX_ADC1_Init();
101
+  MX_USART1_UART_Init();
102
+
103
+  /* Initialize interrupts */
104
+  MX_NVIC_Init();
105
+  /* USER CODE BEGIN 2 */
106
+
107
+  /* USER CODE END 2 */
108
+
109
+  /* Infinite loop */
110
+  /* USER CODE BEGIN WHILE */
111
+  while (1)
112
+  {
113
+    /* USER CODE END WHILE */
114
+
115
+    /* USER CODE BEGIN 3 */
116
+  }
117
+  /* USER CODE END 3 */
118
+}
119
+
120
+/**
121
+  * @brief System Clock Configuration
122
+  * @retval None
123
+  */
124
+void SystemClock_Config(void)
125
+{
126
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
127
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
128
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
129
+
130
+  /** Initializes the CPU, AHB and APB busses clocks 
131
+  */
132
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
133
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
134
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
135
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
136
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2;
137
+  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL15;
138
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
139
+  {
140
+    Error_Handler();
141
+  }
142
+  /** Initializes the CPU, AHB and APB busses clocks 
143
+  */
144
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
145
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
146
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
147
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
148
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
149
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
150
+
151
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
152
+  {
153
+    Error_Handler();
154
+  }
155
+  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
156
+  PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6;
157
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
158
+  {
159
+    Error_Handler();
160
+  }
161
+}
162
+
163
+/**
164
+  * @brief NVIC Configuration.
165
+  * @retval None
166
+  */
167
+static void MX_NVIC_Init(void)
168
+{
169
+  /* USART1_IRQn interrupt configuration */
170
+  HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
171
+  HAL_NVIC_EnableIRQ(USART1_IRQn);
172
+}
173
+
174
+/**
175
+  * @brief ADC1 Initialization Function
176
+  * @param None
177
+  * @retval None
178
+  */
179
+static void MX_ADC1_Init(void)
180
+{
181
+
182
+  /* USER CODE BEGIN ADC1_Init 0 */
183
+
184
+  /* USER CODE END ADC1_Init 0 */
185
+
186
+  ADC_ChannelConfTypeDef sConfig = {0};
187
+
188
+  /* USER CODE BEGIN ADC1_Init 1 */
189
+
190
+  /* USER CODE END ADC1_Init 1 */
191
+  /** Common config 
192
+  */
193
+  hadc1.Instance = ADC1;
194
+  hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE;
195
+  hadc1.Init.ContinuousConvMode = DISABLE;
196
+  hadc1.Init.DiscontinuousConvMode = DISABLE;
197
+  hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
198
+  hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
199
+  hadc1.Init.NbrOfConversion = 2;
200
+  if (HAL_ADC_Init(&hadc1) != HAL_OK)
201
+  {
202
+    Error_Handler();
203
+  }
204
+  /** Configure Regular Channel 
205
+  */
206
+  sConfig.Channel = ADC_CHANNEL_0;
207
+  sConfig.Rank = ADC_REGULAR_RANK_1;
208
+  sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
209
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
210
+  {
211
+    Error_Handler();
212
+  }
213
+  /** Configure Regular Channel 
214
+  */
215
+  sConfig.Rank = ADC_REGULAR_RANK_2;
216
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
217
+  {
218
+    Error_Handler();
219
+  }
220
+  /* USER CODE BEGIN ADC1_Init 2 */
221
+
222
+  /* USER CODE END ADC1_Init 2 */
223
+
224
+}
225
+
226
+/**
227
+  * @brief USART1 Initialization Function
228
+  * @param None
229
+  * @retval None
230
+  */
231
+static void MX_USART1_UART_Init(void)
232
+{
233
+
234
+  /* USER CODE BEGIN USART1_Init 0 */
235
+
236
+  /* USER CODE END USART1_Init 0 */
237
+
238
+  /* USER CODE BEGIN USART1_Init 1 */
239
+
240
+  /* USER CODE END USART1_Init 1 */
241
+  huart1.Instance = USART1;
242
+  huart1.Init.BaudRate = 115200;
243
+  huart1.Init.WordLength = UART_WORDLENGTH_8B;
244
+  huart1.Init.StopBits = UART_STOPBITS_1;
245
+  huart1.Init.Parity = UART_PARITY_NONE;
246
+  huart1.Init.Mode = UART_MODE_TX_RX;
247
+  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
248
+  huart1.Init.OverSampling = UART_OVERSAMPLING_16;
249
+  if (HAL_UART_Init(&huart1) != HAL_OK)
250
+  {
251
+    Error_Handler();
252
+  }
253
+  /* USER CODE BEGIN USART1_Init 2 */
254
+
255
+  /* USER CODE END USART1_Init 2 */
256
+
257
+}
258
+
259
+/** 
260
+  * Enable DMA controller clock
261
+  */
262
+static void MX_DMA_Init(void) 
263
+{
264
+  /* DMA controller clock enable */
265
+  __HAL_RCC_DMA1_CLK_ENABLE();
266
+
267
+  /* DMA interrupt init */
268
+  /* DMA1_Channel1_IRQn interrupt configuration */
269
+  HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
270
+  HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
271
+
272
+}
273
+
274
+/**
275
+  * @brief GPIO Initialization Function
276
+  * @param None
277
+  * @retval None
278
+  */
279
+static void MX_GPIO_Init(void)
280
+{
281
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
282
+
283
+  /* GPIO Ports Clock Enable */
284
+  __HAL_RCC_GPIOE_CLK_ENABLE();
285
+  __HAL_RCC_GPIOC_CLK_ENABLE();
286
+  __HAL_RCC_GPIOF_CLK_ENABLE();
287
+  __HAL_RCC_GPIOA_CLK_ENABLE();
288
+  __HAL_RCC_GPIOB_CLK_ENABLE();
289
+  __HAL_RCC_GPIOD_CLK_ENABLE();
290
+  __HAL_RCC_GPIOG_CLK_ENABLE();
291
+
292
+  /*Configure GPIO pin Output Level */
293
+  HAL_GPIO_WritePin(GPIOE, ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin 
294
+                          |ATT_EN_1_8G_UL3_Pin|PATH_EN_2_1G_DL_Pin|PATH_EN_2_1G_UL_Pin, GPIO_PIN_RESET);
295
+
296
+  /*Configure GPIO pin Output Level */
297
+  HAL_GPIO_WritePin(GPIOC, ATT_EN_1_8G_UL4_Pin|PATH_EN_1_8G_DL_Pin|PATH_EN_1_8G_UL_Pin|PLL_EN_3_5G_L_Pin 
298
+                          |PLL_EN_3_5G_H_Pin, GPIO_PIN_RESET);
299
+
300
+  /*Configure GPIO pin Output Level */
301
+  HAL_GPIO_WritePin(GPIOF, PLL_EN_1_8G_DL_Pin|PLL_EN_1_8G_UL_Pin|ATT_EN_2_1G_DL1_Pin|ATT_EN_2_1G_DL2_Pin 
302
+                          |ATT_EN_2_1G_UL1_Pin|ATT_EN_2_1G_UL2_Pin|ATT_EN_2_1G_UL3_Pin|ATT_EN_2_1G_UL4_Pin, GPIO_PIN_RESET);
303
+
304
+  /*Configure GPIO pin Output Level */
305
+  HAL_GPIO_WritePin(GPIOD, PLL_DATA_Pin|PLL_CLK_Pin|ATT_DATA_Pin|ATT_CLK_Pin 
306
+                          |DA_LDAC_Pin|ATT_CLK_3_5G_Pin|ATT_EN_3_5G_Pin|ATT_DATA_3_5G_DL_Pin 
307
+                          |ATT_DATA_3_5G_UL_Pin|ATT_DATA_3_5G_COM1_Pin|ATT_DATA_3_5G_COM2_Pin|ATT_DATA_3_5G_COM3_Pin 
308
+                          |PATH_EN_3_5G_L_Pin, GPIO_PIN_RESET);
309
+
310
+  /*Configure GPIO pin Output Level */
311
+  HAL_GPIO_WritePin(GPIOG, DA_SYNC_Pin|DA_SCLK_Pin|DA_DIN_Pin|_T_SYNC_UL_Pin 
312
+                          |T_SYNC_UL_Pin|_T_SYNC_DL_Pin|T_SYNC_DL_Pin|PATH_EN_3_5G_DL_Pin 
313
+                          |PATH_EN_3_5G_UL_Pin|PLL_ON_OFF_3_5G_L_Pin|PLL_ON_OFF_3_5G_H_Pin, GPIO_PIN_RESET);
314
+
315
+  /*Configure GPIO pin Output Level */
316
+  HAL_GPIO_WritePin(GPIOB, PLL_EN_2_1G_DL_Pin|PLL_EN_2_1G_UL_Pin, GPIO_PIN_RESET);
317
+
318
+  /*Configure GPIO pins : ATT_EN_1_8G_DL1_Pin ATT_EN_1_8G_DL2_Pin ATT_EN_1_8G_UL1_Pin ATT_EN_1_8G_UL2_Pin 
319
+                           ATT_EN_1_8G_UL3_Pin PATH_EN_2_1G_DL_Pin PATH_EN_2_1G_UL_Pin */
320
+  GPIO_InitStruct.Pin = ATT_EN_1_8G_DL1_Pin|ATT_EN_1_8G_DL2_Pin|ATT_EN_1_8G_UL1_Pin|ATT_EN_1_8G_UL2_Pin 
321
+                          |ATT_EN_1_8G_UL3_Pin|PATH_EN_2_1G_DL_Pin|PATH_EN_2_1G_UL_Pin;
322
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
323
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
324
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
325
+  HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
326
+
327
+  /*Configure GPIO pins : ATT_EN_1_8G_UL4_Pin PATH_EN_1_8G_DL_Pin PATH_EN_1_8G_UL_Pin PLL_EN_3_5G_L_Pin 
328
+                           PLL_EN_3_5G_H_Pin */
329
+  GPIO_InitStruct.Pin = ATT_EN_1_8G_UL4_Pin|PATH_EN_1_8G_DL_Pin|PATH_EN_1_8G_UL_Pin|PLL_EN_3_5G_L_Pin 
330
+                          |PLL_EN_3_5G_H_Pin;
331
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
332
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
333
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
334
+  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
335
+
336
+  /*Configure GPIO pins : PLL_EN_1_8G_DL_Pin PLL_EN_1_8G_UL_Pin ATT_EN_2_1G_DL1_Pin ATT_EN_2_1G_DL2_Pin 
337
+                           ATT_EN_2_1G_UL1_Pin ATT_EN_2_1G_UL2_Pin ATT_EN_2_1G_UL3_Pin ATT_EN_2_1G_UL4_Pin */
338
+  GPIO_InitStruct.Pin = PLL_EN_1_8G_DL_Pin|PLL_EN_1_8G_UL_Pin|ATT_EN_2_1G_DL1_Pin|ATT_EN_2_1G_DL2_Pin 
339
+                          |ATT_EN_2_1G_UL1_Pin|ATT_EN_2_1G_UL2_Pin|ATT_EN_2_1G_UL3_Pin|ATT_EN_2_1G_UL4_Pin;
340
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
341
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
342
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
343
+  HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
344
+
345
+  /*Configure GPIO pins : PLL_LD_1_8G_DL_Pin PLL_LD_1_8G_UL_Pin */
346
+  GPIO_InitStruct.Pin = PLL_LD_1_8G_DL_Pin|PLL_LD_1_8G_UL_Pin;
347
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
348
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
349
+  HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
350
+
351
+  /*Configure GPIO pins : PLL_DATA_Pin PLL_CLK_Pin ATT_DATA_Pin ATT_CLK_Pin 
352
+                           DA_LDAC_Pin ATT_CLK_3_5G_Pin ATT_EN_3_5G_Pin ATT_DATA_3_5G_DL_Pin 
353
+                           ATT_DATA_3_5G_UL_Pin ATT_DATA_3_5G_COM1_Pin ATT_DATA_3_5G_COM2_Pin ATT_DATA_3_5G_COM3_Pin 
354
+                           PATH_EN_3_5G_L_Pin */
355
+  GPIO_InitStruct.Pin = PLL_DATA_Pin|PLL_CLK_Pin|ATT_DATA_Pin|ATT_CLK_Pin 
356
+                          |DA_LDAC_Pin|ATT_CLK_3_5G_Pin|ATT_EN_3_5G_Pin|ATT_DATA_3_5G_DL_Pin 
357
+                          |ATT_DATA_3_5G_UL_Pin|ATT_DATA_3_5G_COM1_Pin|ATT_DATA_3_5G_COM2_Pin|ATT_DATA_3_5G_COM3_Pin 
358
+                          |PATH_EN_3_5G_L_Pin;
359
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
360
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
361
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
362
+  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
363
+
364
+  /*Configure GPIO pins : ALARM_DC_Pin ALARM_AC_Pin */
365
+  GPIO_InitStruct.Pin = ALARM_DC_Pin|ALARM_AC_Pin;
366
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
367
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
368
+  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
369
+
370
+  /*Configure GPIO pins : DA_SYNC_Pin DA_SCLK_Pin DA_DIN_Pin _T_SYNC_UL_Pin 
371
+                           T_SYNC_UL_Pin _T_SYNC_DL_Pin T_SYNC_DL_Pin PATH_EN_3_5G_DL_Pin 
372
+                           PATH_EN_3_5G_UL_Pin PLL_ON_OFF_3_5G_L_Pin PLL_ON_OFF_3_5G_H_Pin */
373
+  GPIO_InitStruct.Pin = DA_SYNC_Pin|DA_SCLK_Pin|DA_DIN_Pin|_T_SYNC_UL_Pin 
374
+                          |T_SYNC_UL_Pin|_T_SYNC_DL_Pin|T_SYNC_DL_Pin|PATH_EN_3_5G_DL_Pin 
375
+                          |PATH_EN_3_5G_UL_Pin|PLL_ON_OFF_3_5G_L_Pin|PLL_ON_OFF_3_5G_H_Pin;
376
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
377
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
378
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
379
+  HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
380
+
381
+  /*Configure GPIO pins : PLL_LD_3_5G_L_Pin PLL_LD_3_5G_H_Pin */
382
+  GPIO_InitStruct.Pin = PLL_LD_3_5G_L_Pin|PLL_LD_3_5G_H_Pin;
383
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
384
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
385
+  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
386
+
387
+  /*Configure GPIO pin : PATH_EN_3_5G_H_Pin */
388
+  GPIO_InitStruct.Pin = PATH_EN_3_5G_H_Pin;
389
+  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
390
+  HAL_GPIO_Init(PATH_EN_3_5G_H_GPIO_Port, &GPIO_InitStruct);
391
+
392
+  /*Configure GPIO pins : PLL_EN_2_1G_DL_Pin PLL_EN_2_1G_UL_Pin */
393
+  GPIO_InitStruct.Pin = PLL_EN_2_1G_DL_Pin|PLL_EN_2_1G_UL_Pin;
394
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
395
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
396
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
397
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
398
+
399
+  /*Configure GPIO pins : PLL_LD_2_1G_DL_Pin PLL_LD_2_1G_UL_Pin */
400
+  GPIO_InitStruct.Pin = PLL_LD_2_1G_DL_Pin|PLL_LD_2_1G_UL_Pin;
401
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
402
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
403
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
404
+
405
+}
406
+
407
+/* USER CODE BEGIN 4 */
408
+
409
+/* USER CODE END 4 */
410
+
411
+/**
412
+  * @brief  This function is executed in case of error occurrence.
413
+  * @retval None
414
+  */
415
+void Error_Handler(void)
416
+{
417
+  /* USER CODE BEGIN Error_Handler_Debug */
418
+  /* User can add his own implementation to report the HAL error return state */
419
+
420
+  /* USER CODE END Error_Handler_Debug */
421
+}
422
+
423
+#ifdef  USE_FULL_ASSERT
424
+/**
425
+  * @brief  Reports the name of the source file and the source line number
426
+  *         where the assert_param error has occurred.
427
+  * @param  file: pointer to the source file name
428
+  * @param  line: assert_param error line source number
429
+  * @retval None
430
+  */
431
+void assert_failed(uint8_t *file, uint32_t line)
432
+{ 
433
+  /* USER CODE BEGIN 6 */
434
+  /* User can add his own implementation to report the file name and line number,
435
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
436
+  /* USER CODE END 6 */
437
+}
438
+#endif /* USE_FULL_ASSERT */
439
+
440
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 214 - 0
insight/STM32F103_ATTEN_PLL_Zig.si4project/Backup/stm32f1xx_hal_def(7893).h

@@ -0,0 +1,214 @@
1
+/**
2
+  ******************************************************************************
3
+  * @file    stm32f1xx_hal_def.h
4
+  * @author  MCD Application Team
5
+  * @brief   This file contains HAL common defines, enumeration, macros and
6
+  *          structures definitions.
7
+  ******************************************************************************
8
+  * @attention
9
+  *
10
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
11
+  *
12
+  * Redistribution and use in source and binary forms, with or without modification,
13
+  * are permitted provided that the following conditions are met:
14
+  *   1. Redistributions of source code must retain the above copyright notice,
15
+  *      this list of conditions and the following disclaimer.
16
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
17
+  *      this list of conditions and the following disclaimer in the documentation
18
+  *      and/or other materials provided with the distribution.
19
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
20
+  *      may be used to endorse or promote products derived from this software
21
+  *      without specific prior written permission.
22
+  *
23
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
27
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
30
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33
+  *
34
+  ******************************************************************************
35
+  */
36
+
37
+/* Define to prevent recursive inclusion -------------------------------------*/
38
+#ifndef __STM32F1xx_HAL_DEF
39
+#define __STM32F1xx_HAL_DEF
40
+
41
+#ifdef __cplusplus
42
+extern "C" {
43
+#endif
44
+
45
+/* Includes ------------------------------------------------------------------*/
46
+#include "stm32f1xx.h"
47
+#if defined(USE_HAL_LEGACY)
48
+#include "Legacy/stm32_hal_legacy.h"
49
+#endif
50
+#include <stdio.h>
51
+
52
+/* Exported types ------------------------------------------------------------*/
53
+
54
+/**
55
+  * @brief  HAL Status structures definition
56
+  */
57
+typedef enum
58
+{
59
+  HAL_OK       = 0x00U,
60
+  HAL_ERROR    = 0x01U,
61
+  HAL_BUSY     = 0x02U,
62
+  HAL_TIMEOUT  = 0x03U
63
+} HAL_StatusTypeDef;
64
+
65
+/**
66
+  * @brief  HAL Lock structures definition
67
+  */
68
+typedef enum
69
+{
70
+  HAL_UNLOCKED = 0x00U,
71
+  HAL_LOCKED   = 0x01U
72
+} HAL_LockTypeDef;
73
+
74
+/* Exported macro ------------------------------------------------------------*/
75
+#define HAL_MAX_DELAY      0xFFFFFFFFU
76
+
77
+#define HAL_IS_BIT_SET(REG, BIT)         (((REG) & (BIT)) != 0U)
78
+#define HAL_IS_BIT_CLR(REG, BIT)         (((REG) & (BIT)) == 0U)
79
+
80
+#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__)               \
81
+                        do{                                                      \
82
+                              (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
83
+                              (__DMA_HANDLE__).Parent = (__HANDLE__);             \
84
+                          } while(0U)
85
+
86
+#define UNUSED(X) (void)X      /* To avoid gcc/g++ warnings */
87
+
88
+/** @brief Reset the Handle's State field.
89
+  * @param __HANDLE__: specifies the Peripheral Handle.
90
+  * @note  This macro can be used for the following purpose:
91
+  *          - When the Handle is declared as local variable; before passing it as parameter
92
+  *            to HAL_PPP_Init() for the first time, it is mandatory to use this macro
93
+  *            to set to 0 the Handle's "State" field.
94
+  *            Otherwise, "State" field may have any random value and the first time the function
95
+  *            HAL_PPP_Init() is called, the low level hardware initialization will be missed
96
+  *            (i.e. HAL_PPP_MspInit() will not be executed).
97
+  *          - When there is a need to reconfigure the low level hardware: instead of calling
98
+  *            HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
99
+  *            In this later function, when the Handle's "State" field is set to 0, it will execute the function
100
+  *            HAL_PPP_MspInit() which will reconfigure the low level hardware.
101
+  * @retval None
102
+  */
103
+#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
104
+
105
+#if (USE_RTOS == 1U)
106
+/* Reserved for future use */
107
+#error "USE_RTOS should be 0 in the current HAL release"
108
+#else
109
+#define __HAL_LOCK(__HANDLE__)                                           \
110
+                                do{                                        \
111
+                                    if((__HANDLE__)->Lock == HAL_LOCKED)   \
112
+                                    {                                      \
113
+                                       return HAL_BUSY;                    \
114
+                                    }                                      \
115
+                                    else                                   \
116
+                                    {                                      \
117
+                                       (__HANDLE__)->Lock = HAL_LOCKED;    \
118
+                                    }                                      \
119
+                                  }while (0U)
120
+
121
+#define __HAL_UNLOCK(__HANDLE__)                                          \
122
+                                  do{                                       \
123
+                                      (__HANDLE__)->Lock = HAL_UNLOCKED;    \
124
+                                    }while (0U)
125
+#endif /* USE_RTOS */
126
+
127
+#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
128
+#ifndef __weak
129
+#define __weak   __attribute__((weak))
130
+#endif /* __weak */
131
+#ifndef __packed
132
+#define __packed __attribute__((__packed__))
133
+#endif /* __packed */
134
+#endif /* __GNUC__ */
135
+
136
+
137
+/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
138
+#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
139
+#ifndef __ALIGN_END
140
+#define __ALIGN_END    __attribute__ ((aligned (4)))
141
+#endif /* __ALIGN_END */
142
+#ifndef __ALIGN_BEGIN
143
+#define __ALIGN_BEGIN
144
+#endif /* __ALIGN_BEGIN */
145
+#else
146
+#ifndef __ALIGN_END
147
+#define __ALIGN_END
148
+#endif /* __ALIGN_END */
149
+#ifndef __ALIGN_BEGIN
150
+#if defined   (__CC_ARM)      /* ARM Compiler */
151
+#define __ALIGN_BEGIN    __align(4)
152
+#elif defined (__ICCARM__)    /* IAR Compiler */
153
+#define __ALIGN_BEGIN
154
+#endif /* __CC_ARM */
155
+#endif /* __ALIGN_BEGIN */
156
+#endif /* __GNUC__ */
157
+
158
+
159
+/**
160
+  * @brief  __RAM_FUNC definition
161
+  */
162
+#if defined ( __CC_ARM   )
163
+/* ARM Compiler
164
+   ------------
165
+   RAM functions are defined using the toolchain options.
166
+   Functions that are executed in RAM should reside in a separate source module.
167
+   Using the 'Options for File' dialog you can simply change the 'Code / Const'
168
+   area of a module to a memory space in physical RAM.
169
+   Available memory areas are declared in the 'Target' tab of the 'Options for Target'
170
+   dialog.
171
+*/
172
+#define __RAM_FUNC
173
+
174
+#elif defined ( __ICCARM__ )
175
+/* ICCARM Compiler
176
+   ---------------
177
+   RAM functions are defined using a specific toolchain keyword "__ramfunc".
178
+*/
179
+#define __RAM_FUNC __ramfunc
180
+
181
+#elif defined   (  __GNUC__  )
182
+/* GNU Compiler
183
+   ------------
184
+  RAM functions are defined using a specific toolchain attribute
185
+   "__attribute__((section(".RamFunc")))".
186
+*/
187
+#define __RAM_FUNC __attribute__((section(".RamFunc")))
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+
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+#endif
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+
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+/**
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+  * @brief  __NOINLINE definition
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+  */
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+#if defined ( __CC_ARM   ) || defined   (  __GNUC__  )
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+/* ARM & GNUCompiler
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+   ----------------
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+*/
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+#define __NOINLINE __attribute__ ( (noinline) )
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+
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+#elif defined ( __ICCARM__ )
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+/* ICCARM Compiler
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+   ---------------
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+*/
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+#define __NOINLINE _Pragma("optimize = no_inline")
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+
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+#endif
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+
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+#ifdef __cplusplus
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+}
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+#endif
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+
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+#endif /* ___STM32F1xx_HAL_DEF */
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+
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+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

二进制
insight/STM32F103_ATTEN_PLL_Zig.si4project/STM32F103_ATTEN_PLL_Zig.sip_xab


二进制
insight/STM32F103_ATTEN_PLL_Zig.si4project/STM32F103_ATTEN_PLL_Zig.sip_xad


二进制
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Drivers_STM32F1xx_HAL_Driver_Inc_stm32f1xx_hal_def.h.sisc


二进制
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_stm32f1xx_hal_conf.h.sisc


二进制
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Inc_stm32f1xx_it.h.sisc


二进制
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_BDA4601.c.sisc


二进制
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_PE43711.c.sisc


二进制
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_main.c.sisc


二进制
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_stm32f1xx_hal_msp.c.sisc


二进制
insight/STM32F103_ATTEN_PLL_Zig.si4project/cache/parse/.._.._Src_stm32f1xx_it.c.sisc