Nesslab_200M_System/Debug/Nesslab_200M_System.list

Nesslab_200M_System.elf:     file format elf32-littlearm

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .isr_vector   000001d0  08000000  08000000  00010000  2**0
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  1 .text         000080e4  080001d0  080001d0  000101d0  2**3
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  2 .rodata       00000600  080082b8  080082b8  000182b8  2**3
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  3 .ARM.extab    00000000  080088b8  080088b8  000201dc  2**0
                  CONTENTS
  4 .ARM          00000000  080088b8  080088b8  000201dc  2**0
                  CONTENTS
  5 .preinit_array 00000000  080088b8  080088b8  000201dc  2**0
                  CONTENTS, ALLOC, LOAD, DATA
  6 .init_array   00000004  080088b8  080088b8  000188b8  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  7 .fini_array   00000004  080088bc  080088bc  000188bc  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  8 .data         000001dc  20000000  080088c0  00020000  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  9 .bss          00000708  200001e0  08008a9c  000201e0  2**3
                  ALLOC
 10 ._user_heap_stack 00000600  200008e8  08008a9c  000208e8  2**0
                  ALLOC
 11 .ARM.attributes 00000029  00000000  00000000  000201dc  2**0
                  CONTENTS, READONLY
 12 .debug_info   00014194  00000000  00000000  00020205  2**0
                  CONTENTS, READONLY, DEBUGGING
 13 .debug_abbrev 00003508  00000000  00000000  00034399  2**0
                  CONTENTS, READONLY, DEBUGGING
 14 .debug_aranges 00001110  00000000  00000000  000378a8  2**3
                  CONTENTS, READONLY, DEBUGGING
 15 .debug_ranges 00000f68  00000000  00000000  000389b8  2**3
                  CONTENTS, READONLY, DEBUGGING
 16 .debug_macro  00010ee7  00000000  00000000  00039920  2**0
                  CONTENTS, READONLY, DEBUGGING
 17 .debug_line   0000f3c5  00000000  00000000  0004a807  2**0
                  CONTENTS, READONLY, DEBUGGING
 18 .debug_str    0005855e  00000000  00000000  00059bcc  2**0
                  CONTENTS, READONLY, DEBUGGING
 19 .comment      0000007b  00000000  00000000  000b212a  2**0
                  CONTENTS, READONLY
 20 .debug_frame  00005358  00000000  00000000  000b21a8  2**2
                  CONTENTS, READONLY, DEBUGGING

Disassembly of section .text:

080001d0 <__do_global_dtors_aux>:
 80001d0:	b510      	push	{r4, lr}
 80001d2:	4c05      	ldr	r4, [pc, #20]	; (80001e8 <__do_global_dtors_aux+0x18>)
 80001d4:	7823      	ldrb	r3, [r4, #0]
 80001d6:	b933      	cbnz	r3, 80001e6 <__do_global_dtors_aux+0x16>
 80001d8:	4b04      	ldr	r3, [pc, #16]	; (80001ec <__do_global_dtors_aux+0x1c>)
 80001da:	b113      	cbz	r3, 80001e2 <__do_global_dtors_aux+0x12>
 80001dc:	4804      	ldr	r0, [pc, #16]	; (80001f0 <__do_global_dtors_aux+0x20>)
 80001de:	f3af 8000 	nop.w
 80001e2:	2301      	movs	r3, #1
 80001e4:	7023      	strb	r3, [r4, #0]
 80001e6:	bd10      	pop	{r4, pc}
 80001e8:	200001e0 	.word	0x200001e0
 80001ec:	00000000 	.word	0x00000000
 80001f0:	0800829c 	.word	0x0800829c

080001f4 <frame_dummy>:
 80001f4:	b508      	push	{r3, lr}
 80001f6:	4b03      	ldr	r3, [pc, #12]	; (8000204 <frame_dummy+0x10>)
 80001f8:	b11b      	cbz	r3, 8000202 <frame_dummy+0xe>
 80001fa:	4903      	ldr	r1, [pc, #12]	; (8000208 <frame_dummy+0x14>)
 80001fc:	4803      	ldr	r0, [pc, #12]	; (800020c <frame_dummy+0x18>)
 80001fe:	f3af 8000 	nop.w
 8000202:	bd08      	pop	{r3, pc}
 8000204:	00000000 	.word	0x00000000
 8000208:	200001e4 	.word	0x200001e4
 800020c:	0800829c 	.word	0x0800829c

08000210 <strlen>:
 8000210:	4603      	mov	r3, r0
 8000212:	f813 2b01 	ldrb.w	r2, [r3], #1
 8000216:	2a00      	cmp	r2, #0
 8000218:	d1fb      	bne.n	8000212 <strlen+0x2>
 800021a:	1a18      	subs	r0, r3, r0
 800021c:	3801      	subs	r0, #1
 800021e:	4770      	bx	lr

08000220 <__aeabi_drsub>:
 8000220:	f081 4100 	eor.w	r1, r1, #2147483648	; 0x80000000
 8000224:	e002      	b.n	800022c <__adddf3>
 8000226:	bf00      	nop

08000228 <__aeabi_dsub>:
 8000228:	f083 4300 	eor.w	r3, r3, #2147483648	; 0x80000000

0800022c <__adddf3>:
 800022c:	b530      	push	{r4, r5, lr}
 800022e:	ea4f 0441 	mov.w	r4, r1, lsl #1
 8000232:	ea4f 0543 	mov.w	r5, r3, lsl #1
 8000236:	ea94 0f05 	teq	r4, r5
 800023a:	bf08      	it	eq
 800023c:	ea90 0f02 	teqeq	r0, r2
 8000240:	bf1f      	itttt	ne
 8000242:	ea54 0c00 	orrsne.w	ip, r4, r0
 8000246:	ea55 0c02 	orrsne.w	ip, r5, r2
 800024a:	ea7f 5c64 	mvnsne.w	ip, r4, asr #21
 800024e:	ea7f 5c65 	mvnsne.w	ip, r5, asr #21
 8000252:	f000 80e2 	beq.w	800041a <__adddf3+0x1ee>
 8000256:	ea4f 5454 	mov.w	r4, r4, lsr #21
 800025a:	ebd4 5555 	rsbs	r5, r4, r5, lsr #21
 800025e:	bfb8      	it	lt
 8000260:	426d      	neglt	r5, r5
 8000262:	dd0c      	ble.n	800027e <__adddf3+0x52>
 8000264:	442c      	add	r4, r5
 8000266:	ea80 0202 	eor.w	r2, r0, r2
 800026a:	ea81 0303 	eor.w	r3, r1, r3
 800026e:	ea82 0000 	eor.w	r0, r2, r0
 8000272:	ea83 0101 	eor.w	r1, r3, r1
 8000276:	ea80 0202 	eor.w	r2, r0, r2
 800027a:	ea81 0303 	eor.w	r3, r1, r3
 800027e:	2d36      	cmp	r5, #54	; 0x36
 8000280:	bf88      	it	hi
 8000282:	bd30      	pophi	{r4, r5, pc}
 8000284:	f011 4f00 	tst.w	r1, #2147483648	; 0x80000000
 8000288:	ea4f 3101 	mov.w	r1, r1, lsl #12
 800028c:	f44f 1c80 	mov.w	ip, #1048576	; 0x100000
 8000290:	ea4c 3111 	orr.w	r1, ip, r1, lsr #12
 8000294:	d002      	beq.n	800029c <__adddf3+0x70>
 8000296:	4240      	negs	r0, r0
 8000298:	eb61 0141 	sbc.w	r1, r1, r1, lsl #1
 800029c:	f013 4f00 	tst.w	r3, #2147483648	; 0x80000000
 80002a0:	ea4f 3303 	mov.w	r3, r3, lsl #12
 80002a4:	ea4c 3313 	orr.w	r3, ip, r3, lsr #12
 80002a8:	d002      	beq.n	80002b0 <__adddf3+0x84>
 80002aa:	4252      	negs	r2, r2
 80002ac:	eb63 0343 	sbc.w	r3, r3, r3, lsl #1
 80002b0:	ea94 0f05 	teq	r4, r5
 80002b4:	f000 80a7 	beq.w	8000406 <__adddf3+0x1da>
 80002b8:	f1a4 0401 	sub.w	r4, r4, #1
 80002bc:	f1d5 0e20 	rsbs	lr, r5, #32
 80002c0:	db0d      	blt.n	80002de <__adddf3+0xb2>
 80002c2:	fa02 fc0e 	lsl.w	ip, r2, lr
 80002c6:	fa22 f205 	lsr.w	r2, r2, r5
 80002ca:	1880      	adds	r0, r0, r2
 80002cc:	f141 0100 	adc.w	r1, r1, #0
 80002d0:	fa03 f20e 	lsl.w	r2, r3, lr
 80002d4:	1880      	adds	r0, r0, r2
 80002d6:	fa43 f305 	asr.w	r3, r3, r5
 80002da:	4159      	adcs	r1, r3
 80002dc:	e00e      	b.n	80002fc <__adddf3+0xd0>
 80002de:	f1a5 0520 	sub.w	r5, r5, #32
 80002e2:	f10e 0e20 	add.w	lr, lr, #32
 80002e6:	2a01      	cmp	r2, #1
 80002e8:	fa03 fc0e 	lsl.w	ip, r3, lr
 80002ec:	bf28      	it	cs
 80002ee:	f04c 0c02 	orrcs.w	ip, ip, #2
 80002f2:	fa43 f305 	asr.w	r3, r3, r5
 80002f6:	18c0      	adds	r0, r0, r3
 80002f8:	eb51 71e3 	adcs.w	r1, r1, r3, asr #31
 80002fc:	f001 4500 	and.w	r5, r1, #2147483648	; 0x80000000
 8000300:	d507      	bpl.n	8000312 <__adddf3+0xe6>
 8000302:	f04f 0e00 	mov.w	lr, #0
 8000306:	f1dc 0c00 	rsbs	ip, ip, #0
 800030a:	eb7e 0000 	sbcs.w	r0, lr, r0
 800030e:	eb6e 0101 	sbc.w	r1, lr, r1
 8000312:	f5b1 1f80 	cmp.w	r1, #1048576	; 0x100000
 8000316:	d31b      	bcc.n	8000350 <__adddf3+0x124>
 8000318:	f5b1 1f00 	cmp.w	r1, #2097152	; 0x200000
 800031c:	d30c      	bcc.n	8000338 <__adddf3+0x10c>
 800031e:	0849      	lsrs	r1, r1, #1
 8000320:	ea5f 0030 	movs.w	r0, r0, rrx
 8000324:	ea4f 0c3c 	mov.w	ip, ip, rrx
 8000328:	f104 0401 	add.w	r4, r4, #1
 800032c:	ea4f 5244 	mov.w	r2, r4, lsl #21
 8000330:	f512 0f80 	cmn.w	r2, #4194304	; 0x400000
 8000334:	f080 809a 	bcs.w	800046c <__adddf3+0x240>
 8000338:	f1bc 4f00 	cmp.w	ip, #2147483648	; 0x80000000
 800033c:	bf08      	it	eq
 800033e:	ea5f 0c50 	movseq.w	ip, r0, lsr #1
 8000342:	f150 0000 	adcs.w	r0, r0, #0
 8000346:	eb41 5104 	adc.w	r1, r1, r4, lsl #20
 800034a:	ea41 0105 	orr.w	r1, r1, r5
 800034e:	bd30      	pop	{r4, r5, pc}
 8000350:	ea5f 0c4c 	movs.w	ip, ip, lsl #1
 8000354:	4140      	adcs	r0, r0
 8000356:	eb41 0101 	adc.w	r1, r1, r1
 800035a:	f411 1f80 	tst.w	r1, #1048576	; 0x100000
 800035e:	f1a4 0401 	sub.w	r4, r4, #1
 8000362:	d1e9      	bne.n	8000338 <__adddf3+0x10c>
 8000364:	f091 0f00 	teq	r1, #0
 8000368:	bf04      	itt	eq
 800036a:	4601      	moveq	r1, r0
 800036c:	2000      	moveq	r0, #0
 800036e:	fab1 f381 	clz	r3, r1
 8000372:	bf08      	it	eq
 8000374:	3320      	addeq	r3, #32
 8000376:	f1a3 030b 	sub.w	r3, r3, #11
 800037a:	f1b3 0220 	subs.w	r2, r3, #32
 800037e:	da0c      	bge.n	800039a <__adddf3+0x16e>
 8000380:	320c      	adds	r2, #12
 8000382:	dd08      	ble.n	8000396 <__adddf3+0x16a>
 8000384:	f102 0c14 	add.w	ip, r2, #20
 8000388:	f1c2 020c 	rsb	r2, r2, #12
 800038c:	fa01 f00c 	lsl.w	r0, r1, ip
 8000390:	fa21 f102 	lsr.w	r1, r1, r2
 8000394:	e00c      	b.n	80003b0 <__adddf3+0x184>
 8000396:	f102 0214 	add.w	r2, r2, #20
 800039a:	bfd8      	it	le
 800039c:	f1c2 0c20 	rsble	ip, r2, #32
 80003a0:	fa01 f102 	lsl.w	r1, r1, r2
 80003a4:	fa20 fc0c 	lsr.w	ip, r0, ip
 80003a8:	bfdc      	itt	le
 80003aa:	ea41 010c 	orrle.w	r1, r1, ip
 80003ae:	4090      	lslle	r0, r2
 80003b0:	1ae4      	subs	r4, r4, r3
 80003b2:	bfa2      	ittt	ge
 80003b4:	eb01 5104 	addge.w	r1, r1, r4, lsl #20
 80003b8:	4329      	orrge	r1, r5
 80003ba:	bd30      	popge	{r4, r5, pc}
 80003bc:	ea6f 0404 	mvn.w	r4, r4
 80003c0:	3c1f      	subs	r4, #31
 80003c2:	da1c      	bge.n	80003fe <__adddf3+0x1d2>
 80003c4:	340c      	adds	r4, #12
 80003c6:	dc0e      	bgt.n	80003e6 <__adddf3+0x1ba>
 80003c8:	f104 0414 	add.w	r4, r4, #20
 80003cc:	f1c4 0220 	rsb	r2, r4, #32
 80003d0:	fa20 f004 	lsr.w	r0, r0, r4
 80003d4:	fa01 f302 	lsl.w	r3, r1, r2
 80003d8:	ea40 0003 	orr.w	r0, r0, r3
 80003dc:	fa21 f304 	lsr.w	r3, r1, r4
 80003e0:	ea45 0103 	orr.w	r1, r5, r3
 80003e4:	bd30      	pop	{r4, r5, pc}
 80003e6:	f1c4 040c 	rsb	r4, r4, #12
 80003ea:	f1c4 0220 	rsb	r2, r4, #32
 80003ee:	fa20 f002 	lsr.w	r0, r0, r2
 80003f2:	fa01 f304 	lsl.w	r3, r1, r4
 80003f6:	ea40 0003 	orr.w	r0, r0, r3
 80003fa:	4629      	mov	r1, r5
 80003fc:	bd30      	pop	{r4, r5, pc}
 80003fe:	fa21 f004 	lsr.w	r0, r1, r4
 8000402:	4629      	mov	r1, r5
 8000404:	bd30      	pop	{r4, r5, pc}
 8000406:	f094 0f00 	teq	r4, #0
 800040a:	f483 1380 	eor.w	r3, r3, #1048576	; 0x100000
 800040e:	bf06      	itte	eq
 8000410:	f481 1180 	eoreq.w	r1, r1, #1048576	; 0x100000
 8000414:	3401      	addeq	r4, #1
 8000416:	3d01      	subne	r5, #1
 8000418:	e74e      	b.n	80002b8 <__adddf3+0x8c>
 800041a:	ea7f 5c64 	mvns.w	ip, r4, asr #21
 800041e:	bf18      	it	ne
 8000420:	ea7f 5c65 	mvnsne.w	ip, r5, asr #21
 8000424:	d029      	beq.n	800047a <__adddf3+0x24e>
 8000426:	ea94 0f05 	teq	r4, r5
 800042a:	bf08      	it	eq
 800042c:	ea90 0f02 	teqeq	r0, r2
 8000430:	d005      	beq.n	800043e <__adddf3+0x212>
 8000432:	ea54 0c00 	orrs.w	ip, r4, r0
 8000436:	bf04      	itt	eq
 8000438:	4619      	moveq	r1, r3
 800043a:	4610      	moveq	r0, r2
 800043c:	bd30      	pop	{r4, r5, pc}
 800043e:	ea91 0f03 	teq	r1, r3
 8000442:	bf1e      	ittt	ne
 8000444:	2100      	movne	r1, #0
 8000446:	2000      	movne	r0, #0
 8000448:	bd30      	popne	{r4, r5, pc}
 800044a:	ea5f 5c54 	movs.w	ip, r4, lsr #21
 800044e:	d105      	bne.n	800045c <__adddf3+0x230>
 8000450:	0040      	lsls	r0, r0, #1
 8000452:	4149      	adcs	r1, r1
 8000454:	bf28      	it	cs
 8000456:	f041 4100 	orrcs.w	r1, r1, #2147483648	; 0x80000000
 800045a:	bd30      	pop	{r4, r5, pc}
 800045c:	f514 0480 	adds.w	r4, r4, #4194304	; 0x400000
 8000460:	bf3c      	itt	cc
 8000462:	f501 1180 	addcc.w	r1, r1, #1048576	; 0x100000
 8000466:	bd30      	popcc	{r4, r5, pc}
 8000468:	f001 4500 	and.w	r5, r1, #2147483648	; 0x80000000
 800046c:	f045 41fe 	orr.w	r1, r5, #2130706432	; 0x7f000000
 8000470:	f441 0170 	orr.w	r1, r1, #15728640	; 0xf00000
 8000474:	f04f 0000 	mov.w	r0, #0
 8000478:	bd30      	pop	{r4, r5, pc}
 800047a:	ea7f 5c64 	mvns.w	ip, r4, asr #21
 800047e:	bf1a      	itte	ne
 8000480:	4619      	movne	r1, r3
 8000482:	4610      	movne	r0, r2
 8000484:	ea7f 5c65 	mvnseq.w	ip, r5, asr #21
 8000488:	bf1c      	itt	ne
 800048a:	460b      	movne	r3, r1
 800048c:	4602      	movne	r2, r0
 800048e:	ea50 3401 	orrs.w	r4, r0, r1, lsl #12
 8000492:	bf06      	itte	eq
 8000494:	ea52 3503 	orrseq.w	r5, r2, r3, lsl #12
 8000498:	ea91 0f03 	teqeq	r1, r3
 800049c:	f441 2100 	orrne.w	r1, r1, #524288	; 0x80000
 80004a0:	bd30      	pop	{r4, r5, pc}
 80004a2:	bf00      	nop

080004a4 <__aeabi_ui2d>:
 80004a4:	f090 0f00 	teq	r0, #0
 80004a8:	bf04      	itt	eq
 80004aa:	2100      	moveq	r1, #0
 80004ac:	4770      	bxeq	lr
 80004ae:	b530      	push	{r4, r5, lr}
 80004b0:	f44f 6480 	mov.w	r4, #1024	; 0x400
 80004b4:	f104 0432 	add.w	r4, r4, #50	; 0x32
 80004b8:	f04f 0500 	mov.w	r5, #0
 80004bc:	f04f 0100 	mov.w	r1, #0
 80004c0:	e750      	b.n	8000364 <__adddf3+0x138>
 80004c2:	bf00      	nop

080004c4 <__aeabi_i2d>:
 80004c4:	f090 0f00 	teq	r0, #0
 80004c8:	bf04      	itt	eq
 80004ca:	2100      	moveq	r1, #0
 80004cc:	4770      	bxeq	lr
 80004ce:	b530      	push	{r4, r5, lr}
 80004d0:	f44f 6480 	mov.w	r4, #1024	; 0x400
 80004d4:	f104 0432 	add.w	r4, r4, #50	; 0x32
 80004d8:	f010 4500 	ands.w	r5, r0, #2147483648	; 0x80000000
 80004dc:	bf48      	it	mi
 80004de:	4240      	negmi	r0, r0
 80004e0:	f04f 0100 	mov.w	r1, #0
 80004e4:	e73e      	b.n	8000364 <__adddf3+0x138>
 80004e6:	bf00      	nop

080004e8 <__aeabi_f2d>:
 80004e8:	0042      	lsls	r2, r0, #1
 80004ea:	ea4f 01e2 	mov.w	r1, r2, asr #3
 80004ee:	ea4f 0131 	mov.w	r1, r1, rrx
 80004f2:	ea4f 7002 	mov.w	r0, r2, lsl #28
 80004f6:	bf1f      	itttt	ne
 80004f8:	f012 437f 	andsne.w	r3, r2, #4278190080	; 0xff000000
 80004fc:	f093 4f7f 	teqne	r3, #4278190080	; 0xff000000
 8000500:	f081 5160 	eorne.w	r1, r1, #939524096	; 0x38000000
 8000504:	4770      	bxne	lr
 8000506:	f032 427f 	bics.w	r2, r2, #4278190080	; 0xff000000
 800050a:	bf08      	it	eq
 800050c:	4770      	bxeq	lr
 800050e:	f093 4f7f 	teq	r3, #4278190080	; 0xff000000
 8000512:	bf04      	itt	eq
 8000514:	f441 2100 	orreq.w	r1, r1, #524288	; 0x80000
 8000518:	4770      	bxeq	lr
 800051a:	b530      	push	{r4, r5, lr}
 800051c:	f44f 7460 	mov.w	r4, #896	; 0x380
 8000520:	f001 4500 	and.w	r5, r1, #2147483648	; 0x80000000
 8000524:	f021 4100 	bic.w	r1, r1, #2147483648	; 0x80000000
 8000528:	e71c      	b.n	8000364 <__adddf3+0x138>
 800052a:	bf00      	nop

0800052c <__aeabi_ul2d>:
 800052c:	ea50 0201 	orrs.w	r2, r0, r1
 8000530:	bf08      	it	eq
 8000532:	4770      	bxeq	lr
 8000534:	b530      	push	{r4, r5, lr}
 8000536:	f04f 0500 	mov.w	r5, #0
 800053a:	e00a      	b.n	8000552 <__aeabi_l2d+0x16>

0800053c <__aeabi_l2d>:
 800053c:	ea50 0201 	orrs.w	r2, r0, r1
 8000540:	bf08      	it	eq
 8000542:	4770      	bxeq	lr
 8000544:	b530      	push	{r4, r5, lr}
 8000546:	f011 4500 	ands.w	r5, r1, #2147483648	; 0x80000000
 800054a:	d502      	bpl.n	8000552 <__aeabi_l2d+0x16>
 800054c:	4240      	negs	r0, r0
 800054e:	eb61 0141 	sbc.w	r1, r1, r1, lsl #1
 8000552:	f44f 6480 	mov.w	r4, #1024	; 0x400
 8000556:	f104 0432 	add.w	r4, r4, #50	; 0x32
 800055a:	ea5f 5c91 	movs.w	ip, r1, lsr #22
 800055e:	f43f aed8 	beq.w	8000312 <__adddf3+0xe6>
 8000562:	f04f 0203 	mov.w	r2, #3
 8000566:	ea5f 0cdc 	movs.w	ip, ip, lsr #3
 800056a:	bf18      	it	ne
 800056c:	3203      	addne	r2, #3
 800056e:	ea5f 0cdc 	movs.w	ip, ip, lsr #3
 8000572:	bf18      	it	ne
 8000574:	3203      	addne	r2, #3
 8000576:	eb02 02dc 	add.w	r2, r2, ip, lsr #3
 800057a:	f1c2 0320 	rsb	r3, r2, #32
 800057e:	fa00 fc03 	lsl.w	ip, r0, r3
 8000582:	fa20 f002 	lsr.w	r0, r0, r2
 8000586:	fa01 fe03 	lsl.w	lr, r1, r3
 800058a:	ea40 000e 	orr.w	r0, r0, lr
 800058e:	fa21 f102 	lsr.w	r1, r1, r2
 8000592:	4414      	add	r4, r2
 8000594:	e6bd      	b.n	8000312 <__adddf3+0xe6>
 8000596:	bf00      	nop

08000598 <__aeabi_dmul>:
 8000598:	b570      	push	{r4, r5, r6, lr}
 800059a:	f04f 0cff 	mov.w	ip, #255	; 0xff
 800059e:	f44c 6ce0 	orr.w	ip, ip, #1792	; 0x700
 80005a2:	ea1c 5411 	ands.w	r4, ip, r1, lsr #20
 80005a6:	bf1d      	ittte	ne
 80005a8:	ea1c 5513 	andsne.w	r5, ip, r3, lsr #20
 80005ac:	ea94 0f0c 	teqne	r4, ip
 80005b0:	ea95 0f0c 	teqne	r5, ip
 80005b4:	f000 f8de 	bleq	8000774 <__aeabi_dmul+0x1dc>
 80005b8:	442c      	add	r4, r5
 80005ba:	ea81 0603 	eor.w	r6, r1, r3
 80005be:	ea21 514c 	bic.w	r1, r1, ip, lsl #21
 80005c2:	ea23 534c 	bic.w	r3, r3, ip, lsl #21
 80005c6:	ea50 3501 	orrs.w	r5, r0, r1, lsl #12
 80005ca:	bf18      	it	ne
 80005cc:	ea52 3503 	orrsne.w	r5, r2, r3, lsl #12
 80005d0:	f441 1180 	orr.w	r1, r1, #1048576	; 0x100000
 80005d4:	f443 1380 	orr.w	r3, r3, #1048576	; 0x100000
 80005d8:	d038      	beq.n	800064c <__aeabi_dmul+0xb4>
 80005da:	fba0 ce02 	umull	ip, lr, r0, r2
 80005de:	f04f 0500 	mov.w	r5, #0
 80005e2:	fbe1 e502 	umlal	lr, r5, r1, r2
 80005e6:	f006 4200 	and.w	r2, r6, #2147483648	; 0x80000000
 80005ea:	fbe0 e503 	umlal	lr, r5, r0, r3
 80005ee:	f04f 0600 	mov.w	r6, #0
 80005f2:	fbe1 5603 	umlal	r5, r6, r1, r3
 80005f6:	f09c 0f00 	teq	ip, #0
 80005fa:	bf18      	it	ne
 80005fc:	f04e 0e01 	orrne.w	lr, lr, #1
 8000600:	f1a4 04ff 	sub.w	r4, r4, #255	; 0xff
 8000604:	f5b6 7f00 	cmp.w	r6, #512	; 0x200
 8000608:	f564 7440 	sbc.w	r4, r4, #768	; 0x300
 800060c:	d204      	bcs.n	8000618 <__aeabi_dmul+0x80>
 800060e:	ea5f 0e4e 	movs.w	lr, lr, lsl #1
 8000612:	416d      	adcs	r5, r5
 8000614:	eb46 0606 	adc.w	r6, r6, r6
 8000618:	ea42 21c6 	orr.w	r1, r2, r6, lsl #11
 800061c:	ea41 5155 	orr.w	r1, r1, r5, lsr #21
 8000620:	ea4f 20c5 	mov.w	r0, r5, lsl #11
 8000624:	ea40 505e 	orr.w	r0, r0, lr, lsr #21
 8000628:	ea4f 2ece 	mov.w	lr, lr, lsl #11
 800062c:	f1b4 0cfd 	subs.w	ip, r4, #253	; 0xfd
 8000630:	bf88      	it	hi
 8000632:	f5bc 6fe0 	cmphi.w	ip, #1792	; 0x700
 8000636:	d81e      	bhi.n	8000676 <__aeabi_dmul+0xde>
 8000638:	f1be 4f00 	cmp.w	lr, #2147483648	; 0x80000000
 800063c:	bf08      	it	eq
 800063e:	ea5f 0e50 	movseq.w	lr, r0, lsr #1
 8000642:	f150 0000 	adcs.w	r0, r0, #0
 8000646:	eb41 5104 	adc.w	r1, r1, r4, lsl #20
 800064a:	bd70      	pop	{r4, r5, r6, pc}
 800064c:	f006 4600 	and.w	r6, r6, #2147483648	; 0x80000000
 8000650:	ea46 0101 	orr.w	r1, r6, r1
 8000654:	ea40 0002 	orr.w	r0, r0, r2
 8000658:	ea81 0103 	eor.w	r1, r1, r3
 800065c:	ebb4 045c 	subs.w	r4, r4, ip, lsr #1
 8000660:	bfc2      	ittt	gt
 8000662:	ebd4 050c 	rsbsgt	r5, r4, ip
 8000666:	ea41 5104 	orrgt.w	r1, r1, r4, lsl #20
 800066a:	bd70      	popgt	{r4, r5, r6, pc}
 800066c:	f441 1180 	orr.w	r1, r1, #1048576	; 0x100000
 8000670:	f04f 0e00 	mov.w	lr, #0
 8000674:	3c01      	subs	r4, #1
 8000676:	f300 80ab 	bgt.w	80007d0 <__aeabi_dmul+0x238>
 800067a:	f114 0f36 	cmn.w	r4, #54	; 0x36
 800067e:	bfde      	ittt	le
 8000680:	2000      	movle	r0, #0
 8000682:	f001 4100 	andle.w	r1, r1, #2147483648	; 0x80000000
 8000686:	bd70      	pople	{r4, r5, r6, pc}
 8000688:	f1c4 0400 	rsb	r4, r4, #0
 800068c:	3c20      	subs	r4, #32
 800068e:	da35      	bge.n	80006fc <__aeabi_dmul+0x164>
 8000690:	340c      	adds	r4, #12
 8000692:	dc1b      	bgt.n	80006cc <__aeabi_dmul+0x134>
 8000694:	f104 0414 	add.w	r4, r4, #20
 8000698:	f1c4 0520 	rsb	r5, r4, #32
 800069c:	fa00 f305 	lsl.w	r3, r0, r5
 80006a0:	fa20 f004 	lsr.w	r0, r0, r4
 80006a4:	fa01 f205 	lsl.w	r2, r1, r5
 80006a8:	ea40 0002 	orr.w	r0, r0, r2
 80006ac:	f001 4200 	and.w	r2, r1, #2147483648	; 0x80000000
 80006b0:	f021 4100 	bic.w	r1, r1, #2147483648	; 0x80000000
 80006b4:	eb10 70d3 	adds.w	r0, r0, r3, lsr #31
 80006b8:	fa21 f604 	lsr.w	r6, r1, r4
 80006bc:	eb42 0106 	adc.w	r1, r2, r6
 80006c0:	ea5e 0e43 	orrs.w	lr, lr, r3, lsl #1
 80006c4:	bf08      	it	eq
 80006c6:	ea20 70d3 	biceq.w	r0, r0, r3, lsr #31
 80006ca:	bd70      	pop	{r4, r5, r6, pc}
 80006cc:	f1c4 040c 	rsb	r4, r4, #12
 80006d0:	f1c4 0520 	rsb	r5, r4, #32
 80006d4:	fa00 f304 	lsl.w	r3, r0, r4
 80006d8:	fa20 f005 	lsr.w	r0, r0, r5
 80006dc:	fa01 f204 	lsl.w	r2, r1, r4
 80006e0:	ea40 0002 	orr.w	r0, r0, r2
 80006e4:	f001 4100 	and.w	r1, r1, #2147483648	; 0x80000000
 80006e8:	eb10 70d3 	adds.w	r0, r0, r3, lsr #31
 80006ec:	f141 0100 	adc.w	r1, r1, #0
 80006f0:	ea5e 0e43 	orrs.w	lr, lr, r3, lsl #1
 80006f4:	bf08      	it	eq
 80006f6:	ea20 70d3 	biceq.w	r0, r0, r3, lsr #31
 80006fa:	bd70      	pop	{r4, r5, r6, pc}
 80006fc:	f1c4 0520 	rsb	r5, r4, #32
 8000700:	fa00 f205 	lsl.w	r2, r0, r5
 8000704:	ea4e 0e02 	orr.w	lr, lr, r2
 8000708:	fa20 f304 	lsr.w	r3, r0, r4
 800070c:	fa01 f205 	lsl.w	r2, r1, r5
 8000710:	ea43 0302 	orr.w	r3, r3, r2
 8000714:	fa21 f004 	lsr.w	r0, r1, r4
 8000718:	f001 4100 	and.w	r1, r1, #2147483648	; 0x80000000
 800071c:	fa21 f204 	lsr.w	r2, r1, r4
 8000720:	ea20 0002 	bic.w	r0, r0, r2
 8000724:	eb00 70d3 	add.w	r0, r0, r3, lsr #31
 8000728:	ea5e 0e43 	orrs.w	lr, lr, r3, lsl #1
 800072c:	bf08      	it	eq
 800072e:	ea20 70d3 	biceq.w	r0, r0, r3, lsr #31
 8000732:	bd70      	pop	{r4, r5, r6, pc}
 8000734:	f094 0f00 	teq	r4, #0
 8000738:	d10f      	bne.n	800075a <__aeabi_dmul+0x1c2>
 800073a:	f001 4600 	and.w	r6, r1, #2147483648	; 0x80000000
 800073e:	0040      	lsls	r0, r0, #1
 8000740:	eb41 0101 	adc.w	r1, r1, r1
 8000744:	f411 1f80 	tst.w	r1, #1048576	; 0x100000
 8000748:	bf08      	it	eq
 800074a:	3c01      	subeq	r4, #1
 800074c:	d0f7      	beq.n	800073e <__aeabi_dmul+0x1a6>
 800074e:	ea41 0106 	orr.w	r1, r1, r6
 8000752:	f095 0f00 	teq	r5, #0
 8000756:	bf18      	it	ne
 8000758:	4770      	bxne	lr
 800075a:	f003 4600 	and.w	r6, r3, #2147483648	; 0x80000000
 800075e:	0052      	lsls	r2, r2, #1
 8000760:	eb43 0303 	adc.w	r3, r3, r3
 8000764:	f413 1f80 	tst.w	r3, #1048576	; 0x100000
 8000768:	bf08      	it	eq
 800076a:	3d01      	subeq	r5, #1
 800076c:	d0f7      	beq.n	800075e <__aeabi_dmul+0x1c6>
 800076e:	ea43 0306 	orr.w	r3, r3, r6
 8000772:	4770      	bx	lr
 8000774:	ea94 0f0c 	teq	r4, ip
 8000778:	ea0c 5513 	and.w	r5, ip, r3, lsr #20
 800077c:	bf18      	it	ne
 800077e:	ea95 0f0c 	teqne	r5, ip
 8000782:	d00c      	beq.n	800079e <__aeabi_dmul+0x206>
 8000784:	ea50 0641 	orrs.w	r6, r0, r1, lsl #1
 8000788:	bf18      	it	ne
 800078a:	ea52 0643 	orrsne.w	r6, r2, r3, lsl #1
 800078e:	d1d1      	bne.n	8000734 <__aeabi_dmul+0x19c>
 8000790:	ea81 0103 	eor.w	r1, r1, r3
 8000794:	f001 4100 	and.w	r1, r1, #2147483648	; 0x80000000
 8000798:	f04f 0000 	mov.w	r0, #0
 800079c:	bd70      	pop	{r4, r5, r6, pc}
 800079e:	ea50 0641 	orrs.w	r6, r0, r1, lsl #1
 80007a2:	bf06      	itte	eq
 80007a4:	4610      	moveq	r0, r2
 80007a6:	4619      	moveq	r1, r3
 80007a8:	ea52 0643 	orrsne.w	r6, r2, r3, lsl #1
 80007ac:	d019      	beq.n	80007e2 <__aeabi_dmul+0x24a>
 80007ae:	ea94 0f0c 	teq	r4, ip
 80007b2:	d102      	bne.n	80007ba <__aeabi_dmul+0x222>
 80007b4:	ea50 3601 	orrs.w	r6, r0, r1, lsl #12
 80007b8:	d113      	bne.n	80007e2 <__aeabi_dmul+0x24a>
 80007ba:	ea95 0f0c 	teq	r5, ip
 80007be:	d105      	bne.n	80007cc <__aeabi_dmul+0x234>
 80007c0:	ea52 3603 	orrs.w	r6, r2, r3, lsl #12
 80007c4:	bf1c      	itt	ne
 80007c6:	4610      	movne	r0, r2
 80007c8:	4619      	movne	r1, r3
 80007ca:	d10a      	bne.n	80007e2 <__aeabi_dmul+0x24a>
 80007cc:	ea81 0103 	eor.w	r1, r1, r3
 80007d0:	f001 4100 	and.w	r1, r1, #2147483648	; 0x80000000
 80007d4:	f041 41fe 	orr.w	r1, r1, #2130706432	; 0x7f000000
 80007d8:	f441 0170 	orr.w	r1, r1, #15728640	; 0xf00000
 80007dc:	f04f 0000 	mov.w	r0, #0
 80007e0:	bd70      	pop	{r4, r5, r6, pc}
 80007e2:	f041 41fe 	orr.w	r1, r1, #2130706432	; 0x7f000000
 80007e6:	f441 0178 	orr.w	r1, r1, #16252928	; 0xf80000
 80007ea:	bd70      	pop	{r4, r5, r6, pc}

080007ec <__aeabi_ddiv>:
 80007ec:	b570      	push	{r4, r5, r6, lr}
 80007ee:	f04f 0cff 	mov.w	ip, #255	; 0xff
 80007f2:	f44c 6ce0 	orr.w	ip, ip, #1792	; 0x700
 80007f6:	ea1c 5411 	ands.w	r4, ip, r1, lsr #20
 80007fa:	bf1d      	ittte	ne
 80007fc:	ea1c 5513 	andsne.w	r5, ip, r3, lsr #20
 8000800:	ea94 0f0c 	teqne	r4, ip
 8000804:	ea95 0f0c 	teqne	r5, ip
 8000808:	f000 f8a7 	bleq	800095a <__aeabi_ddiv+0x16e>
 800080c:	eba4 0405 	sub.w	r4, r4, r5
 8000810:	ea81 0e03 	eor.w	lr, r1, r3
 8000814:	ea52 3503 	orrs.w	r5, r2, r3, lsl #12
 8000818:	ea4f 3101 	mov.w	r1, r1, lsl #12
 800081c:	f000 8088 	beq.w	8000930 <__aeabi_ddiv+0x144>
 8000820:	ea4f 3303 	mov.w	r3, r3, lsl #12
 8000824:	f04f 5580 	mov.w	r5, #268435456	; 0x10000000
 8000828:	ea45 1313 	orr.w	r3, r5, r3, lsr #4
 800082c:	ea43 6312 	orr.w	r3, r3, r2, lsr #24
 8000830:	ea4f 2202 	mov.w	r2, r2, lsl #8
 8000834:	ea45 1511 	orr.w	r5, r5, r1, lsr #4
 8000838:	ea45 6510 	orr.w	r5, r5, r0, lsr #24
 800083c:	ea4f 2600 	mov.w	r6, r0, lsl #8
 8000840:	f00e 4100 	and.w	r1, lr, #2147483648	; 0x80000000
 8000844:	429d      	cmp	r5, r3
 8000846:	bf08      	it	eq
 8000848:	4296      	cmpeq	r6, r2
 800084a:	f144 04fd 	adc.w	r4, r4, #253	; 0xfd
 800084e:	f504 7440 	add.w	r4, r4, #768	; 0x300
 8000852:	d202      	bcs.n	800085a <__aeabi_ddiv+0x6e>
 8000854:	085b      	lsrs	r3, r3, #1
 8000856:	ea4f 0232 	mov.w	r2, r2, rrx
 800085a:	1ab6      	subs	r6, r6, r2
 800085c:	eb65 0503 	sbc.w	r5, r5, r3
 8000860:	085b      	lsrs	r3, r3, #1
 8000862:	ea4f 0232 	mov.w	r2, r2, rrx
 8000866:	f44f 1080 	mov.w	r0, #1048576	; 0x100000
 800086a:	f44f 2c00 	mov.w	ip, #524288	; 0x80000
 800086e:	ebb6 0e02 	subs.w	lr, r6, r2
 8000872:	eb75 0e03 	sbcs.w	lr, r5, r3
 8000876:	bf22      	ittt	cs
 8000878:	1ab6      	subcs	r6, r6, r2
 800087a:	4675      	movcs	r5, lr
 800087c:	ea40 000c 	orrcs.w	r0, r0, ip
 8000880:	085b      	lsrs	r3, r3, #1
 8000882:	ea4f 0232 	mov.w	r2, r2, rrx
 8000886:	ebb6 0e02 	subs.w	lr, r6, r2
 800088a:	eb75 0e03 	sbcs.w	lr, r5, r3
 800088e:	bf22      	ittt	cs
 8000890:	1ab6      	subcs	r6, r6, r2
 8000892:	4675      	movcs	r5, lr
 8000894:	ea40 005c 	orrcs.w	r0, r0, ip, lsr #1
 8000898:	085b      	lsrs	r3, r3, #1
 800089a:	ea4f 0232 	mov.w	r2, r2, rrx
 800089e:	ebb6 0e02 	subs.w	lr, r6, r2
 80008a2:	eb75 0e03 	sbcs.w	lr, r5, r3
 80008a6:	bf22      	ittt	cs
 80008a8:	1ab6      	subcs	r6, r6, r2
 80008aa:	4675      	movcs	r5, lr
 80008ac:	ea40 009c 	orrcs.w	r0, r0, ip, lsr #2
 80008b0:	085b      	lsrs	r3, r3, #1
 80008b2:	ea4f 0232 	mov.w	r2, r2, rrx
 80008b6:	ebb6 0e02 	subs.w	lr, r6, r2
 80008ba:	eb75 0e03 	sbcs.w	lr, r5, r3
 80008be:	bf22      	ittt	cs
 80008c0:	1ab6      	subcs	r6, r6, r2
 80008c2:	4675      	movcs	r5, lr
 80008c4:	ea40 00dc 	orrcs.w	r0, r0, ip, lsr #3
 80008c8:	ea55 0e06 	orrs.w	lr, r5, r6
 80008cc:	d018      	beq.n	8000900 <__aeabi_ddiv+0x114>
 80008ce:	ea4f 1505 	mov.w	r5, r5, lsl #4
 80008d2:	ea45 7516 	orr.w	r5, r5, r6, lsr #28
 80008d6:	ea4f 1606 	mov.w	r6, r6, lsl #4
 80008da:	ea4f 03c3 	mov.w	r3, r3, lsl #3
 80008de:	ea43 7352 	orr.w	r3, r3, r2, lsr #29
 80008e2:	ea4f 02c2 	mov.w	r2, r2, lsl #3
 80008e6:	ea5f 1c1c 	movs.w	ip, ip, lsr #4
 80008ea:	d1c0      	bne.n	800086e <__aeabi_ddiv+0x82>
 80008ec:	f411 1f80 	tst.w	r1, #1048576	; 0x100000
 80008f0:	d10b      	bne.n	800090a <__aeabi_ddiv+0x11e>
 80008f2:	ea41 0100 	orr.w	r1, r1, r0
 80008f6:	f04f 0000 	mov.w	r0, #0
 80008fa:	f04f 4c00 	mov.w	ip, #2147483648	; 0x80000000
 80008fe:	e7b6      	b.n	800086e <__aeabi_ddiv+0x82>
 8000900:	f411 1f80 	tst.w	r1, #1048576	; 0x100000
 8000904:	bf04      	itt	eq
 8000906:	4301      	orreq	r1, r0
 8000908:	2000      	moveq	r0, #0
 800090a:	f1b4 0cfd 	subs.w	ip, r4, #253	; 0xfd
 800090e:	bf88      	it	hi
 8000910:	f5bc 6fe0 	cmphi.w	ip, #1792	; 0x700
 8000914:	f63f aeaf 	bhi.w	8000676 <__aeabi_dmul+0xde>
 8000918:	ebb5 0c03 	subs.w	ip, r5, r3
 800091c:	bf04      	itt	eq
 800091e:	ebb6 0c02 	subseq.w	ip, r6, r2
 8000922:	ea5f 0c50 	movseq.w	ip, r0, lsr #1
 8000926:	f150 0000 	adcs.w	r0, r0, #0
 800092a:	eb41 5104 	adc.w	r1, r1, r4, lsl #20
 800092e:	bd70      	pop	{r4, r5, r6, pc}
 8000930:	f00e 4e00 	and.w	lr, lr, #2147483648	; 0x80000000
 8000934:	ea4e 3111 	orr.w	r1, lr, r1, lsr #12
 8000938:	eb14 045c 	adds.w	r4, r4, ip, lsr #1
 800093c:	bfc2      	ittt	gt
 800093e:	ebd4 050c 	rsbsgt	r5, r4, ip
 8000942:	ea41 5104 	orrgt.w	r1, r1, r4, lsl #20
 8000946:	bd70      	popgt	{r4, r5, r6, pc}
 8000948:	f441 1180 	orr.w	r1, r1, #1048576	; 0x100000
 800094c:	f04f 0e00 	mov.w	lr, #0
 8000950:	3c01      	subs	r4, #1
 8000952:	e690      	b.n	8000676 <__aeabi_dmul+0xde>
 8000954:	ea45 0e06 	orr.w	lr, r5, r6
 8000958:	e68d      	b.n	8000676 <__aeabi_dmul+0xde>
 800095a:	ea0c 5513 	and.w	r5, ip, r3, lsr #20
 800095e:	ea94 0f0c 	teq	r4, ip
 8000962:	bf08      	it	eq
 8000964:	ea95 0f0c 	teqeq	r5, ip
 8000968:	f43f af3b 	beq.w	80007e2 <__aeabi_dmul+0x24a>
 800096c:	ea94 0f0c 	teq	r4, ip
 8000970:	d10a      	bne.n	8000988 <__aeabi_ddiv+0x19c>
 8000972:	ea50 3401 	orrs.w	r4, r0, r1, lsl #12
 8000976:	f47f af34 	bne.w	80007e2 <__aeabi_dmul+0x24a>
 800097a:	ea95 0f0c 	teq	r5, ip
 800097e:	f47f af25 	bne.w	80007cc <__aeabi_dmul+0x234>
 8000982:	4610      	mov	r0, r2
 8000984:	4619      	mov	r1, r3
 8000986:	e72c      	b.n	80007e2 <__aeabi_dmul+0x24a>
 8000988:	ea95 0f0c 	teq	r5, ip
 800098c:	d106      	bne.n	800099c <__aeabi_ddiv+0x1b0>
 800098e:	ea52 3503 	orrs.w	r5, r2, r3, lsl #12
 8000992:	f43f aefd 	beq.w	8000790 <__aeabi_dmul+0x1f8>
 8000996:	4610      	mov	r0, r2
 8000998:	4619      	mov	r1, r3
 800099a:	e722      	b.n	80007e2 <__aeabi_dmul+0x24a>
 800099c:	ea50 0641 	orrs.w	r6, r0, r1, lsl #1
 80009a0:	bf18      	it	ne
 80009a2:	ea52 0643 	orrsne.w	r6, r2, r3, lsl #1
 80009a6:	f47f aec5 	bne.w	8000734 <__aeabi_dmul+0x19c>
 80009aa:	ea50 0441 	orrs.w	r4, r0, r1, lsl #1
 80009ae:	f47f af0d 	bne.w	80007cc <__aeabi_dmul+0x234>
 80009b2:	ea52 0543 	orrs.w	r5, r2, r3, lsl #1
 80009b6:	f47f aeeb 	bne.w	8000790 <__aeabi_dmul+0x1f8>
 80009ba:	e712      	b.n	80007e2 <__aeabi_dmul+0x24a>

080009bc <__gedf2>:
 80009bc:	f04f 3cff 	mov.w	ip, #4294967295
 80009c0:	e006      	b.n	80009d0 <__cmpdf2+0x4>
 80009c2:	bf00      	nop

080009c4 <__ledf2>:
 80009c4:	f04f 0c01 	mov.w	ip, #1
 80009c8:	e002      	b.n	80009d0 <__cmpdf2+0x4>
 80009ca:	bf00      	nop

080009cc <__cmpdf2>:
 80009cc:	f04f 0c01 	mov.w	ip, #1
 80009d0:	f84d cd04 	str.w	ip, [sp, #-4]!
 80009d4:	ea4f 0c41 	mov.w	ip, r1, lsl #1
 80009d8:	ea7f 5c6c 	mvns.w	ip, ip, asr #21
 80009dc:	ea4f 0c43 	mov.w	ip, r3, lsl #1
 80009e0:	bf18      	it	ne
 80009e2:	ea7f 5c6c 	mvnsne.w	ip, ip, asr #21
 80009e6:	d01b      	beq.n	8000a20 <__cmpdf2+0x54>
 80009e8:	b001      	add	sp, #4
 80009ea:	ea50 0c41 	orrs.w	ip, r0, r1, lsl #1
 80009ee:	bf0c      	ite	eq
 80009f0:	ea52 0c43 	orrseq.w	ip, r2, r3, lsl #1
 80009f4:	ea91 0f03 	teqne	r1, r3
 80009f8:	bf02      	ittt	eq
 80009fa:	ea90 0f02 	teqeq	r0, r2
 80009fe:	2000      	moveq	r0, #0
 8000a00:	4770      	bxeq	lr
 8000a02:	f110 0f00 	cmn.w	r0, #0
 8000a06:	ea91 0f03 	teq	r1, r3
 8000a0a:	bf58      	it	pl
 8000a0c:	4299      	cmppl	r1, r3
 8000a0e:	bf08      	it	eq
 8000a10:	4290      	cmpeq	r0, r2
 8000a12:	bf2c      	ite	cs
 8000a14:	17d8      	asrcs	r0, r3, #31
 8000a16:	ea6f 70e3 	mvncc.w	r0, r3, asr #31
 8000a1a:	f040 0001 	orr.w	r0, r0, #1
 8000a1e:	4770      	bx	lr
 8000a20:	ea4f 0c41 	mov.w	ip, r1, lsl #1
 8000a24:	ea7f 5c6c 	mvns.w	ip, ip, asr #21
 8000a28:	d102      	bne.n	8000a30 <__cmpdf2+0x64>
 8000a2a:	ea50 3c01 	orrs.w	ip, r0, r1, lsl #12
 8000a2e:	d107      	bne.n	8000a40 <__cmpdf2+0x74>
 8000a30:	ea4f 0c43 	mov.w	ip, r3, lsl #1
 8000a34:	ea7f 5c6c 	mvns.w	ip, ip, asr #21
 8000a38:	d1d6      	bne.n	80009e8 <__cmpdf2+0x1c>
 8000a3a:	ea52 3c03 	orrs.w	ip, r2, r3, lsl #12
 8000a3e:	d0d3      	beq.n	80009e8 <__cmpdf2+0x1c>
 8000a40:	f85d 0b04 	ldr.w	r0, [sp], #4
 8000a44:	4770      	bx	lr
 8000a46:	bf00      	nop

08000a48 <__aeabi_cdrcmple>:
 8000a48:	4684      	mov	ip, r0
 8000a4a:	4610      	mov	r0, r2
 8000a4c:	4662      	mov	r2, ip
 8000a4e:	468c      	mov	ip, r1
 8000a50:	4619      	mov	r1, r3
 8000a52:	4663      	mov	r3, ip
 8000a54:	e000      	b.n	8000a58 <__aeabi_cdcmpeq>
 8000a56:	bf00      	nop

08000a58 <__aeabi_cdcmpeq>:
 8000a58:	b501      	push	{r0, lr}
 8000a5a:	f7ff ffb7 	bl	80009cc <__cmpdf2>
 8000a5e:	2800      	cmp	r0, #0
 8000a60:	bf48      	it	mi
 8000a62:	f110 0f00 	cmnmi.w	r0, #0
 8000a66:	bd01      	pop	{r0, pc}

08000a68 <__aeabi_dcmpeq>:
 8000a68:	f84d ed08 	str.w	lr, [sp, #-8]!
 8000a6c:	f7ff fff4 	bl	8000a58 <__aeabi_cdcmpeq>
 8000a70:	bf0c      	ite	eq
 8000a72:	2001      	moveq	r0, #1
 8000a74:	2000      	movne	r0, #0
 8000a76:	f85d fb08 	ldr.w	pc, [sp], #8
 8000a7a:	bf00      	nop

08000a7c <__aeabi_dcmplt>:
 8000a7c:	f84d ed08 	str.w	lr, [sp, #-8]!
 8000a80:	f7ff ffea 	bl	8000a58 <__aeabi_cdcmpeq>
 8000a84:	bf34      	ite	cc
 8000a86:	2001      	movcc	r0, #1
 8000a88:	2000      	movcs	r0, #0
 8000a8a:	f85d fb08 	ldr.w	pc, [sp], #8
 8000a8e:	bf00      	nop

08000a90 <__aeabi_dcmple>:
 8000a90:	f84d ed08 	str.w	lr, [sp, #-8]!
 8000a94:	f7ff ffe0 	bl	8000a58 <__aeabi_cdcmpeq>
 8000a98:	bf94      	ite	ls
 8000a9a:	2001      	movls	r0, #1
 8000a9c:	2000      	movhi	r0, #0
 8000a9e:	f85d fb08 	ldr.w	pc, [sp], #8
 8000aa2:	bf00      	nop

08000aa4 <__aeabi_dcmpge>:
 8000aa4:	f84d ed08 	str.w	lr, [sp, #-8]!
 8000aa8:	f7ff ffce 	bl	8000a48 <__aeabi_cdrcmple>
 8000aac:	bf94      	ite	ls
 8000aae:	2001      	movls	r0, #1
 8000ab0:	2000      	movhi	r0, #0
 8000ab2:	f85d fb08 	ldr.w	pc, [sp], #8
 8000ab6:	bf00      	nop

08000ab8 <__aeabi_dcmpgt>:
 8000ab8:	f84d ed08 	str.w	lr, [sp, #-8]!
 8000abc:	f7ff ffc4 	bl	8000a48 <__aeabi_cdrcmple>
 8000ac0:	bf34      	ite	cc
 8000ac2:	2001      	movcc	r0, #1
 8000ac4:	2000      	movcs	r0, #0
 8000ac6:	f85d fb08 	ldr.w	pc, [sp], #8
 8000aca:	bf00      	nop

08000acc <__aeabi_dcmpun>:
 8000acc:	ea4f 0c41 	mov.w	ip, r1, lsl #1
 8000ad0:	ea7f 5c6c 	mvns.w	ip, ip, asr #21
 8000ad4:	d102      	bne.n	8000adc <__aeabi_dcmpun+0x10>
 8000ad6:	ea50 3c01 	orrs.w	ip, r0, r1, lsl #12
 8000ada:	d10a      	bne.n	8000af2 <__aeabi_dcmpun+0x26>
 8000adc:	ea4f 0c43 	mov.w	ip, r3, lsl #1
 8000ae0:	ea7f 5c6c 	mvns.w	ip, ip, asr #21
 8000ae4:	d102      	bne.n	8000aec <__aeabi_dcmpun+0x20>
 8000ae6:	ea52 3c03 	orrs.w	ip, r2, r3, lsl #12
 8000aea:	d102      	bne.n	8000af2 <__aeabi_dcmpun+0x26>
 8000aec:	f04f 0000 	mov.w	r0, #0
 8000af0:	4770      	bx	lr
 8000af2:	f04f 0001 	mov.w	r0, #1
 8000af6:	4770      	bx	lr

08000af8 <__aeabi_d2iz>:
 8000af8:	ea4f 0241 	mov.w	r2, r1, lsl #1
 8000afc:	f512 1200 	adds.w	r2, r2, #2097152	; 0x200000
 8000b00:	d215      	bcs.n	8000b2e <__aeabi_d2iz+0x36>
 8000b02:	d511      	bpl.n	8000b28 <__aeabi_d2iz+0x30>
 8000b04:	f46f 7378 	mvn.w	r3, #992	; 0x3e0
 8000b08:	ebb3 5262 	subs.w	r2, r3, r2, asr #21
 8000b0c:	d912      	bls.n	8000b34 <__aeabi_d2iz+0x3c>
 8000b0e:	ea4f 23c1 	mov.w	r3, r1, lsl #11
 8000b12:	f043 4300 	orr.w	r3, r3, #2147483648	; 0x80000000
 8000b16:	ea43 5350 	orr.w	r3, r3, r0, lsr #21
 8000b1a:	f011 4f00 	tst.w	r1, #2147483648	; 0x80000000
 8000b1e:	fa23 f002 	lsr.w	r0, r3, r2
 8000b22:	bf18      	it	ne
 8000b24:	4240      	negne	r0, r0
 8000b26:	4770      	bx	lr
 8000b28:	f04f 0000 	mov.w	r0, #0
 8000b2c:	4770      	bx	lr
 8000b2e:	ea50 3001 	orrs.w	r0, r0, r1, lsl #12
 8000b32:	d105      	bne.n	8000b40 <__aeabi_d2iz+0x48>
 8000b34:	f011 4000 	ands.w	r0, r1, #2147483648	; 0x80000000
 8000b38:	bf08      	it	eq
 8000b3a:	f06f 4000 	mvneq.w	r0, #2147483648	; 0x80000000
 8000b3e:	4770      	bx	lr
 8000b40:	f04f 0000 	mov.w	r0, #0
 8000b44:	4770      	bx	lr
 8000b46:	bf00      	nop

08000b48 <__aeabi_d2f>:
 8000b48:	ea4f 0241 	mov.w	r2, r1, lsl #1
 8000b4c:	f1b2 43e0 	subs.w	r3, r2, #1879048192	; 0x70000000
 8000b50:	bf24      	itt	cs
 8000b52:	f5b3 1c00 	subscs.w	ip, r3, #2097152	; 0x200000
 8000b56:	f1dc 5cfe 	rsbscs	ip, ip, #532676608	; 0x1fc00000
 8000b5a:	d90d      	bls.n	8000b78 <__aeabi_d2f+0x30>
 8000b5c:	f001 4c00 	and.w	ip, r1, #2147483648	; 0x80000000
 8000b60:	ea4f 02c0 	mov.w	r2, r0, lsl #3
 8000b64:	ea4c 7050 	orr.w	r0, ip, r0, lsr #29
 8000b68:	f1b2 4f00 	cmp.w	r2, #2147483648	; 0x80000000
 8000b6c:	eb40 0083 	adc.w	r0, r0, r3, lsl #2
 8000b70:	bf08      	it	eq
 8000b72:	f020 0001 	biceq.w	r0, r0, #1
 8000b76:	4770      	bx	lr
 8000b78:	f011 4f80 	tst.w	r1, #1073741824	; 0x40000000
 8000b7c:	d121      	bne.n	8000bc2 <__aeabi_d2f+0x7a>
 8000b7e:	f113 7238 	adds.w	r2, r3, #48234496	; 0x2e00000
 8000b82:	bfbc      	itt	lt
 8000b84:	f001 4000 	andlt.w	r0, r1, #2147483648	; 0x80000000
 8000b88:	4770      	bxlt	lr
 8000b8a:	f441 1180 	orr.w	r1, r1, #1048576	; 0x100000
 8000b8e:	ea4f 5252 	mov.w	r2, r2, lsr #21
 8000b92:	f1c2 0218 	rsb	r2, r2, #24
 8000b96:	f1c2 0c20 	rsb	ip, r2, #32
 8000b9a:	fa10 f30c 	lsls.w	r3, r0, ip
 8000b9e:	fa20 f002 	lsr.w	r0, r0, r2
 8000ba2:	bf18      	it	ne
 8000ba4:	f040 0001 	orrne.w	r0, r0, #1
 8000ba8:	ea4f 23c1 	mov.w	r3, r1, lsl #11
 8000bac:	ea4f 23d3 	mov.w	r3, r3, lsr #11
 8000bb0:	fa03 fc0c 	lsl.w	ip, r3, ip
 8000bb4:	ea40 000c 	orr.w	r0, r0, ip
 8000bb8:	fa23 f302 	lsr.w	r3, r3, r2
 8000bbc:	ea4f 0343 	mov.w	r3, r3, lsl #1
 8000bc0:	e7cc      	b.n	8000b5c <__aeabi_d2f+0x14>
 8000bc2:	ea7f 5362 	mvns.w	r3, r2, asr #21
 8000bc6:	d107      	bne.n	8000bd8 <__aeabi_d2f+0x90>
 8000bc8:	ea50 3301 	orrs.w	r3, r0, r1, lsl #12
 8000bcc:	bf1e      	ittt	ne
 8000bce:	f04f 40fe 	movne.w	r0, #2130706432	; 0x7f000000
 8000bd2:	f440 0040 	orrne.w	r0, r0, #12582912	; 0xc00000
 8000bd6:	4770      	bxne	lr
 8000bd8:	f001 4000 	and.w	r0, r1, #2147483648	; 0x80000000
 8000bdc:	f040 40fe 	orr.w	r0, r0, #2130706432	; 0x7f000000
 8000be0:	f440 0000 	orr.w	r0, r0, #8388608	; 0x800000
 8000be4:	4770      	bx	lr
 8000be6:	bf00      	nop

08000be8 <__aeabi_fmul>:
 8000be8:	f04f 0cff 	mov.w	ip, #255	; 0xff
 8000bec:	ea1c 52d0 	ands.w	r2, ip, r0, lsr #23
 8000bf0:	bf1e      	ittt	ne
 8000bf2:	ea1c 53d1 	andsne.w	r3, ip, r1, lsr #23
 8000bf6:	ea92 0f0c 	teqne	r2, ip
 8000bfa:	ea93 0f0c 	teqne	r3, ip
 8000bfe:	d06f      	beq.n	8000ce0 <__aeabi_fmul+0xf8>
 8000c00:	441a      	add	r2, r3
 8000c02:	ea80 0c01 	eor.w	ip, r0, r1
 8000c06:	0240      	lsls	r0, r0, #9
 8000c08:	bf18      	it	ne
 8000c0a:	ea5f 2141 	movsne.w	r1, r1, lsl #9
 8000c0e:	d01e      	beq.n	8000c4e <__aeabi_fmul+0x66>
 8000c10:	f04f 6300 	mov.w	r3, #134217728	; 0x8000000
 8000c14:	ea43 1050 	orr.w	r0, r3, r0, lsr #5
 8000c18:	ea43 1151 	orr.w	r1, r3, r1, lsr #5
 8000c1c:	fba0 3101 	umull	r3, r1, r0, r1
 8000c20:	f00c 4000 	and.w	r0, ip, #2147483648	; 0x80000000
 8000c24:	f5b1 0f00 	cmp.w	r1, #8388608	; 0x800000
 8000c28:	bf3e      	ittt	cc
 8000c2a:	0049      	lslcc	r1, r1, #1
 8000c2c:	ea41 71d3 	orrcc.w	r1, r1, r3, lsr #31
 8000c30:	005b      	lslcc	r3, r3, #1
 8000c32:	ea40 0001 	orr.w	r0, r0, r1
 8000c36:	f162 027f 	sbc.w	r2, r2, #127	; 0x7f
 8000c3a:	2afd      	cmp	r2, #253	; 0xfd
 8000c3c:	d81d      	bhi.n	8000c7a <__aeabi_fmul+0x92>
 8000c3e:	f1b3 4f00 	cmp.w	r3, #2147483648	; 0x80000000
 8000c42:	eb40 50c2 	adc.w	r0, r0, r2, lsl #23
 8000c46:	bf08      	it	eq
 8000c48:	f020 0001 	biceq.w	r0, r0, #1
 8000c4c:	4770      	bx	lr
 8000c4e:	f090 0f00 	teq	r0, #0
 8000c52:	f00c 4c00 	and.w	ip, ip, #2147483648	; 0x80000000
 8000c56:	bf08      	it	eq
 8000c58:	0249      	lsleq	r1, r1, #9
 8000c5a:	ea4c 2050 	orr.w	r0, ip, r0, lsr #9
 8000c5e:	ea40 2051 	orr.w	r0, r0, r1, lsr #9
 8000c62:	3a7f      	subs	r2, #127	; 0x7f
 8000c64:	bfc2      	ittt	gt
 8000c66:	f1d2 03ff 	rsbsgt	r3, r2, #255	; 0xff
 8000c6a:	ea40 50c2 	orrgt.w	r0, r0, r2, lsl #23
 8000c6e:	4770      	bxgt	lr
 8000c70:	f440 0000 	orr.w	r0, r0, #8388608	; 0x800000
 8000c74:	f04f 0300 	mov.w	r3, #0
 8000c78:	3a01      	subs	r2, #1
 8000c7a:	dc5d      	bgt.n	8000d38 <__aeabi_fmul+0x150>
 8000c7c:	f112 0f19 	cmn.w	r2, #25
 8000c80:	bfdc      	itt	le
 8000c82:	f000 4000 	andle.w	r0, r0, #2147483648	; 0x80000000
 8000c86:	4770      	bxle	lr
 8000c88:	f1c2 0200 	rsb	r2, r2, #0
 8000c8c:	0041      	lsls	r1, r0, #1
 8000c8e:	fa21 f102 	lsr.w	r1, r1, r2
 8000c92:	f1c2 0220 	rsb	r2, r2, #32
 8000c96:	fa00 fc02 	lsl.w	ip, r0, r2
 8000c9a:	ea5f 0031 	movs.w	r0, r1, rrx
 8000c9e:	f140 0000 	adc.w	r0, r0, #0
 8000ca2:	ea53 034c 	orrs.w	r3, r3, ip, lsl #1
 8000ca6:	bf08      	it	eq
 8000ca8:	ea20 70dc 	biceq.w	r0, r0, ip, lsr #31
 8000cac:	4770      	bx	lr
 8000cae:	f092 0f00 	teq	r2, #0
 8000cb2:	f000 4c00 	and.w	ip, r0, #2147483648	; 0x80000000
 8000cb6:	bf02      	ittt	eq
 8000cb8:	0040      	lsleq	r0, r0, #1
 8000cba:	f410 0f00 	tsteq.w	r0, #8388608	; 0x800000
 8000cbe:	3a01      	subeq	r2, #1
 8000cc0:	d0f9      	beq.n	8000cb6 <__aeabi_fmul+0xce>
 8000cc2:	ea40 000c 	orr.w	r0, r0, ip
 8000cc6:	f093 0f00 	teq	r3, #0
 8000cca:	f001 4c00 	and.w	ip, r1, #2147483648	; 0x80000000
 8000cce:	bf02      	ittt	eq
 8000cd0:	0049      	lsleq	r1, r1, #1
 8000cd2:	f411 0f00 	tsteq.w	r1, #8388608	; 0x800000
 8000cd6:	3b01      	subeq	r3, #1
 8000cd8:	d0f9      	beq.n	8000cce <__aeabi_fmul+0xe6>
 8000cda:	ea41 010c 	orr.w	r1, r1, ip
 8000cde:	e78f      	b.n	8000c00 <__aeabi_fmul+0x18>
 8000ce0:	ea0c 53d1 	and.w	r3, ip, r1, lsr #23
 8000ce4:	ea92 0f0c 	teq	r2, ip
 8000ce8:	bf18      	it	ne
 8000cea:	ea93 0f0c 	teqne	r3, ip
 8000cee:	d00a      	beq.n	8000d06 <__aeabi_fmul+0x11e>
 8000cf0:	f030 4c00 	bics.w	ip, r0, #2147483648	; 0x80000000
 8000cf4:	bf18      	it	ne
 8000cf6:	f031 4c00 	bicsne.w	ip, r1, #2147483648	; 0x80000000
 8000cfa:	d1d8      	bne.n	8000cae <__aeabi_fmul+0xc6>
 8000cfc:	ea80 0001 	eor.w	r0, r0, r1
 8000d00:	f000 4000 	and.w	r0, r0, #2147483648	; 0x80000000
 8000d04:	4770      	bx	lr
 8000d06:	f090 0f00 	teq	r0, #0
 8000d0a:	bf17      	itett	ne
 8000d0c:	f090 4f00 	teqne	r0, #2147483648	; 0x80000000
 8000d10:	4608      	moveq	r0, r1
 8000d12:	f091 0f00 	teqne	r1, #0
 8000d16:	f091 4f00 	teqne	r1, #2147483648	; 0x80000000
 8000d1a:	d014      	beq.n	8000d46 <__aeabi_fmul+0x15e>
 8000d1c:	ea92 0f0c 	teq	r2, ip
 8000d20:	d101      	bne.n	8000d26 <__aeabi_fmul+0x13e>
 8000d22:	0242      	lsls	r2, r0, #9
 8000d24:	d10f      	bne.n	8000d46 <__aeabi_fmul+0x15e>
 8000d26:	ea93 0f0c 	teq	r3, ip
 8000d2a:	d103      	bne.n	8000d34 <__aeabi_fmul+0x14c>
 8000d2c:	024b      	lsls	r3, r1, #9
 8000d2e:	bf18      	it	ne
 8000d30:	4608      	movne	r0, r1
 8000d32:	d108      	bne.n	8000d46 <__aeabi_fmul+0x15e>
 8000d34:	ea80 0001 	eor.w	r0, r0, r1
 8000d38:	f000 4000 	and.w	r0, r0, #2147483648	; 0x80000000
 8000d3c:	f040 40fe 	orr.w	r0, r0, #2130706432	; 0x7f000000
 8000d40:	f440 0000 	orr.w	r0, r0, #8388608	; 0x800000
 8000d44:	4770      	bx	lr
 8000d46:	f040 40fe 	orr.w	r0, r0, #2130706432	; 0x7f000000
 8000d4a:	f440 0040 	orr.w	r0, r0, #12582912	; 0xc00000
 8000d4e:	4770      	bx	lr

08000d50 <__aeabi_fdiv>:
 8000d50:	f04f 0cff 	mov.w	ip, #255	; 0xff
 8000d54:	ea1c 52d0 	ands.w	r2, ip, r0, lsr #23
 8000d58:	bf1e      	ittt	ne
 8000d5a:	ea1c 53d1 	andsne.w	r3, ip, r1, lsr #23
 8000d5e:	ea92 0f0c 	teqne	r2, ip
 8000d62:	ea93 0f0c 	teqne	r3, ip
 8000d66:	d069      	beq.n	8000e3c <__aeabi_fdiv+0xec>
 8000d68:	eba2 0203 	sub.w	r2, r2, r3
 8000d6c:	ea80 0c01 	eor.w	ip, r0, r1
 8000d70:	0249      	lsls	r1, r1, #9
 8000d72:	ea4f 2040 	mov.w	r0, r0, lsl #9
 8000d76:	d037      	beq.n	8000de8 <__aeabi_fdiv+0x98>
 8000d78:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
 8000d7c:	ea43 1111 	orr.w	r1, r3, r1, lsr #4
 8000d80:	ea43 1310 	orr.w	r3, r3, r0, lsr #4
 8000d84:	f00c 4000 	and.w	r0, ip, #2147483648	; 0x80000000
 8000d88:	428b      	cmp	r3, r1
 8000d8a:	bf38      	it	cc
 8000d8c:	005b      	lslcc	r3, r3, #1
 8000d8e:	f142 027d 	adc.w	r2, r2, #125	; 0x7d
 8000d92:	f44f 0c00 	mov.w	ip, #8388608	; 0x800000
 8000d96:	428b      	cmp	r3, r1
 8000d98:	bf24      	itt	cs
 8000d9a:	1a5b      	subcs	r3, r3, r1
 8000d9c:	ea40 000c 	orrcs.w	r0, r0, ip
 8000da0:	ebb3 0f51 	cmp.w	r3, r1, lsr #1
 8000da4:	bf24      	itt	cs
 8000da6:	eba3 0351 	subcs.w	r3, r3, r1, lsr #1
 8000daa:	ea40 005c 	orrcs.w	r0, r0, ip, lsr #1
 8000dae:	ebb3 0f91 	cmp.w	r3, r1, lsr #2
 8000db2:	bf24      	itt	cs
 8000db4:	eba3 0391 	subcs.w	r3, r3, r1, lsr #2
 8000db8:	ea40 009c 	orrcs.w	r0, r0, ip, lsr #2
 8000dbc:	ebb3 0fd1 	cmp.w	r3, r1, lsr #3
 8000dc0:	bf24      	itt	cs
 8000dc2:	eba3 03d1 	subcs.w	r3, r3, r1, lsr #3
 8000dc6:	ea40 00dc 	orrcs.w	r0, r0, ip, lsr #3
 8000dca:	011b      	lsls	r3, r3, #4
 8000dcc:	bf18      	it	ne
 8000dce:	ea5f 1c1c 	movsne.w	ip, ip, lsr #4
 8000dd2:	d1e0      	bne.n	8000d96 <__aeabi_fdiv+0x46>
 8000dd4:	2afd      	cmp	r2, #253	; 0xfd
 8000dd6:	f63f af50 	bhi.w	8000c7a <__aeabi_fmul+0x92>
 8000dda:	428b      	cmp	r3, r1
 8000ddc:	eb40 50c2 	adc.w	r0, r0, r2, lsl #23
 8000de0:	bf08      	it	eq
 8000de2:	f020 0001 	biceq.w	r0, r0, #1
 8000de6:	4770      	bx	lr
 8000de8:	f00c 4c00 	and.w	ip, ip, #2147483648	; 0x80000000
 8000dec:	ea4c 2050 	orr.w	r0, ip, r0, lsr #9
 8000df0:	327f      	adds	r2, #127	; 0x7f
 8000df2:	bfc2      	ittt	gt
 8000df4:	f1d2 03ff 	rsbsgt	r3, r2, #255	; 0xff
 8000df8:	ea40 50c2 	orrgt.w	r0, r0, r2, lsl #23
 8000dfc:	4770      	bxgt	lr
 8000dfe:	f440 0000 	orr.w	r0, r0, #8388608	; 0x800000
 8000e02:	f04f 0300 	mov.w	r3, #0
 8000e06:	3a01      	subs	r2, #1
 8000e08:	e737      	b.n	8000c7a <__aeabi_fmul+0x92>
 8000e0a:	f092 0f00 	teq	r2, #0
 8000e0e:	f000 4c00 	and.w	ip, r0, #2147483648	; 0x80000000
 8000e12:	bf02      	ittt	eq
 8000e14:	0040      	lsleq	r0, r0, #1
 8000e16:	f410 0f00 	tsteq.w	r0, #8388608	; 0x800000
 8000e1a:	3a01      	subeq	r2, #1
 8000e1c:	d0f9      	beq.n	8000e12 <__aeabi_fdiv+0xc2>
 8000e1e:	ea40 000c 	orr.w	r0, r0, ip
 8000e22:	f093 0f00 	teq	r3, #0
 8000e26:	f001 4c00 	and.w	ip, r1, #2147483648	; 0x80000000
 8000e2a:	bf02      	ittt	eq
 8000e2c:	0049      	lsleq	r1, r1, #1
 8000e2e:	f411 0f00 	tsteq.w	r1, #8388608	; 0x800000
 8000e32:	3b01      	subeq	r3, #1
 8000e34:	d0f9      	beq.n	8000e2a <__aeabi_fdiv+0xda>
 8000e36:	ea41 010c 	orr.w	r1, r1, ip
 8000e3a:	e795      	b.n	8000d68 <__aeabi_fdiv+0x18>
 8000e3c:	ea0c 53d1 	and.w	r3, ip, r1, lsr #23
 8000e40:	ea92 0f0c 	teq	r2, ip
 8000e44:	d108      	bne.n	8000e58 <__aeabi_fdiv+0x108>
 8000e46:	0242      	lsls	r2, r0, #9
 8000e48:	f47f af7d 	bne.w	8000d46 <__aeabi_fmul+0x15e>
 8000e4c:	ea93 0f0c 	teq	r3, ip
 8000e50:	f47f af70 	bne.w	8000d34 <__aeabi_fmul+0x14c>
 8000e54:	4608      	mov	r0, r1
 8000e56:	e776      	b.n	8000d46 <__aeabi_fmul+0x15e>
 8000e58:	ea93 0f0c 	teq	r3, ip
 8000e5c:	d104      	bne.n	8000e68 <__aeabi_fdiv+0x118>
 8000e5e:	024b      	lsls	r3, r1, #9
 8000e60:	f43f af4c 	beq.w	8000cfc <__aeabi_fmul+0x114>
 8000e64:	4608      	mov	r0, r1
 8000e66:	e76e      	b.n	8000d46 <__aeabi_fmul+0x15e>
 8000e68:	f030 4c00 	bics.w	ip, r0, #2147483648	; 0x80000000
 8000e6c:	bf18      	it	ne
 8000e6e:	f031 4c00 	bicsne.w	ip, r1, #2147483648	; 0x80000000
 8000e72:	d1ca      	bne.n	8000e0a <__aeabi_fdiv+0xba>
 8000e74:	f030 4200 	bics.w	r2, r0, #2147483648	; 0x80000000
 8000e78:	f47f af5c 	bne.w	8000d34 <__aeabi_fmul+0x14c>
 8000e7c:	f031 4300 	bics.w	r3, r1, #2147483648	; 0x80000000
 8000e80:	f47f af3c 	bne.w	8000cfc <__aeabi_fmul+0x114>
 8000e84:	e75f      	b.n	8000d46 <__aeabi_fmul+0x15e>
 8000e86:	bf00      	nop

08000e88 <__aeabi_f2uiz>:
 8000e88:	0042      	lsls	r2, r0, #1
 8000e8a:	d20e      	bcs.n	8000eaa <__aeabi_f2uiz+0x22>
 8000e8c:	f1b2 4ffe 	cmp.w	r2, #2130706432	; 0x7f000000
 8000e90:	d30b      	bcc.n	8000eaa <__aeabi_f2uiz+0x22>
 8000e92:	f04f 039e 	mov.w	r3, #158	; 0x9e
 8000e96:	ebb3 6212 	subs.w	r2, r3, r2, lsr #24
 8000e9a:	d409      	bmi.n	8000eb0 <__aeabi_f2uiz+0x28>
 8000e9c:	ea4f 2300 	mov.w	r3, r0, lsl #8
 8000ea0:	f043 4300 	orr.w	r3, r3, #2147483648	; 0x80000000
 8000ea4:	fa23 f002 	lsr.w	r0, r3, r2
 8000ea8:	4770      	bx	lr
 8000eaa:	f04f 0000 	mov.w	r0, #0
 8000eae:	4770      	bx	lr
 8000eb0:	f112 0f61 	cmn.w	r2, #97	; 0x61
 8000eb4:	d101      	bne.n	8000eba <__aeabi_f2uiz+0x32>
 8000eb6:	0242      	lsls	r2, r0, #9
 8000eb8:	d102      	bne.n	8000ec0 <__aeabi_f2uiz+0x38>
 8000eba:	f04f 30ff 	mov.w	r0, #4294967295
 8000ebe:	4770      	bx	lr
 8000ec0:	f04f 0000 	mov.w	r0, #0
 8000ec4:	4770      	bx	lr
 8000ec6:	bf00      	nop

08000ec8 <NessLab_Operate>:

  

}

void NessLab_Operate(uint8_t* data){
 8000ec8:	b580      	push	{r7, lr}
 8000eca:	b086      	sub	sp, #24
 8000ecc:	af00      	add	r7, sp, #0
 8000ece:	6078      	str	r0, [r7, #4]
	uint8_t datatype = data[NessLab_MsgID0];
 8000ed0:	687b      	ldr	r3, [r7, #4]
 8000ed2:	789b      	ldrb	r3, [r3, #2]
 8000ed4:	73fb      	strb	r3, [r7, #15]
    uint8_t UartLength = 0;
 8000ed6:	2300      	movs	r3, #0
 8000ed8:	75fb      	strb	r3, [r7, #23]
    static uint16_t MSG_SNCnt = 0;
	switch(datatype){
 8000eda:	7bfb      	ldrb	r3, [r7, #15]
 8000edc:	2bc9      	cmp	r3, #201	; 0xc9
 8000ede:	d02c      	beq.n	8000f3a <NessLab_Operate+0x72>
 8000ee0:	2bca      	cmp	r3, #202	; 0xca
 8000ee2:	d034      	beq.n	8000f4e <NessLab_Operate+0x86>
 8000ee4:	2b65      	cmp	r3, #101	; 0x65
 8000ee6:	d16a      	bne.n	8000fbe <NessLab_Operate+0xf6>
		case NessLab_STATUS_REQ:
			ADC_Check();
 8000ee8:	f000 f9c2 	bl	8001270 <ADC_Check>
            
            UartLength = NessLab_MAX_INDEX + 1;
 8000eec:	2316      	movs	r3, #22
 8000eee:	75fb      	strb	r3, [r7, #23]
            MSG_SNCnt = data[NessLab_Req_MsgSN0] << 8 | data[NessLab_Req_MsgSN1];
 8000ef0:	687b      	ldr	r3, [r7, #4]
 8000ef2:	3303      	adds	r3, #3
 8000ef4:	781b      	ldrb	r3, [r3, #0]
 8000ef6:	021b      	lsls	r3, r3, #8
 8000ef8:	b21a      	sxth	r2, r3
 8000efa:	687b      	ldr	r3, [r7, #4]
 8000efc:	3304      	adds	r3, #4
 8000efe:	781b      	ldrb	r3, [r3, #0]
 8000f00:	b21b      	sxth	r3, r3
 8000f02:	4313      	orrs	r3, r2
 8000f04:	b21b      	sxth	r3, r3
 8000f06:	b29a      	uxth	r2, r3
 8000f08:	4b31      	ldr	r3, [pc, #196]	; (8000fd0 <NessLab_Operate+0x108>)
 8000f0a:	801a      	strh	r2, [r3, #0]
            MSG_SNCnt++;
 8000f0c:	4b30      	ldr	r3, [pc, #192]	; (8000fd0 <NessLab_Operate+0x108>)
 8000f0e:	881b      	ldrh	r3, [r3, #0]
 8000f10:	3301      	adds	r3, #1
 8000f12:	b29a      	uxth	r2, r3
 8000f14:	4b2e      	ldr	r3, [pc, #184]	; (8000fd0 <NessLab_Operate+0x108>)
 8000f16:	801a      	strh	r2, [r3, #0]
//            if(data[NessLab_Req_Data_Cnt1] > 0)                
//                NessLab_TxData[NessLab_VSWR_ALARM] = 1;
//            else
//                NessLab_TxData[NessLab_VSWR_ALARM] = 0;
                
            NessLab_TxData[NessLab_MsgSN0] = (uint8_t)((MSG_SNCnt & 0xFF00) >>8);//data[NessLab_Req_MsgSN0];
 8000f18:	4b2d      	ldr	r3, [pc, #180]	; (8000fd0 <NessLab_Operate+0x108>)
 8000f1a:	881b      	ldrh	r3, [r3, #0]
 8000f1c:	0a1b      	lsrs	r3, r3, #8
 8000f1e:	b29b      	uxth	r3, r3
 8000f20:	b2da      	uxtb	r2, r3
 8000f22:	4b2c      	ldr	r3, [pc, #176]	; (8000fd4 <NessLab_Operate+0x10c>)
 8000f24:	70da      	strb	r2, [r3, #3]
            NessLab_TxData[NessLab_MsgSN1] = (uint8_t)((MSG_SNCnt & 0x00FF));//data[NessLab_Req_MsgSN1] ;    
 8000f26:	4b2a      	ldr	r3, [pc, #168]	; (8000fd0 <NessLab_Operate+0x108>)
 8000f28:	881b      	ldrh	r3, [r3, #0]
 8000f2a:	b2da      	uxtb	r2, r3
 8000f2c:	4b29      	ldr	r3, [pc, #164]	; (8000fd4 <NessLab_Operate+0x10c>)
 8000f2e:	711a      	strb	r2, [r3, #4]
            NessLab_Frame_Set(NessLab_TxData,12);
 8000f30:	210c      	movs	r1, #12
 8000f32:	4828      	ldr	r0, [pc, #160]	; (8000fd4 <NessLab_Operate+0x10c>)
 8000f34:	f000 f85c 	bl	8000ff0 <NessLab_Frame_Set>
//            NessLab_TxData[14] = 1;
//            NessLab_TxData[15] = 0;
//            NessLab_TxData[16] = 1;
//            NessLab_TxData[17] = 0;            
                
			break;
 8000f38:	e041      	b.n	8000fbe <NessLab_Operate+0xf6>
            
        case NessLab_Table_REQ:
            UartLength = NESSLAB_TABLE_LENGTH;
 8000f3a:	236e      	movs	r3, #110	; 0x6e
 8000f3c:	75fb      	strb	r3, [r7, #23]
            NessLab_Table_Frame_Set(NessLab_TxData,100);
 8000f3e:	2164      	movs	r1, #100	; 0x64
 8000f40:	4824      	ldr	r0, [pc, #144]	; (8000fd4 <NessLab_Operate+0x10c>)
 8000f42:	f000 f90b 	bl	800115c <NessLab_Table_Frame_Set>
            printf("NessLab_Table_REQ \r\n");
 8000f46:	4824      	ldr	r0, [pc, #144]	; (8000fd8 <NessLab_Operate+0x110>)
 8000f48:	f005 fa2c 	bl	80063a4 <puts>
            break;
 8000f4c:	e037      	b.n	8000fbe <NessLab_Operate+0xf6>
        case NessLab_TableSet_REQ:
            DataErase_Func(FLASH_USER_USE_START_ADDR,200);
 8000f4e:	21c8      	movs	r1, #200	; 0xc8
 8000f50:	4822      	ldr	r0, [pc, #136]	; (8000fdc <NessLab_Operate+0x114>)
 8000f52:	f000 fa5b 	bl	800140c <DataErase_Func>
            printf("Ram Data Display \r\n");
 8000f56:	4822      	ldr	r0, [pc, #136]	; (8000fe0 <NessLab_Operate+0x118>)
 8000f58:	f005 fa24 	bl	80063a4 <puts>
            for(int i = 0; i < data[NessLab_DataLength]; i++){
 8000f5c:	2300      	movs	r3, #0
 8000f5e:	613b      	str	r3, [r7, #16]
 8000f60:	e015      	b.n	8000f8e <NessLab_Operate+0xc6>
                Flash_DataArray[i] = data[NessLab_Data_ADC1_H + i];
 8000f62:	693b      	ldr	r3, [r7, #16]
 8000f64:	3307      	adds	r3, #7
 8000f66:	461a      	mov	r2, r3
 8000f68:	687b      	ldr	r3, [r7, #4]
 8000f6a:	4413      	add	r3, r2
 8000f6c:	7819      	ldrb	r1, [r3, #0]
 8000f6e:	4a1d      	ldr	r2, [pc, #116]	; (8000fe4 <NessLab_Operate+0x11c>)
 8000f70:	693b      	ldr	r3, [r7, #16]
 8000f72:	4413      	add	r3, r2
 8000f74:	460a      	mov	r2, r1
 8000f76:	701a      	strb	r2, [r3, #0]
                printf("%x ",Flash_DataArray[i]);
 8000f78:	4a1a      	ldr	r2, [pc, #104]	; (8000fe4 <NessLab_Operate+0x11c>)
 8000f7a:	693b      	ldr	r3, [r7, #16]
 8000f7c:	4413      	add	r3, r2
 8000f7e:	781b      	ldrb	r3, [r3, #0]
 8000f80:	4619      	mov	r1, r3
 8000f82:	4819      	ldr	r0, [pc, #100]	; (8000fe8 <NessLab_Operate+0x120>)
 8000f84:	f005 f99a 	bl	80062bc <iprintf>
            for(int i = 0; i < data[NessLab_DataLength]; i++){
 8000f88:	693b      	ldr	r3, [r7, #16]
 8000f8a:	3301      	adds	r3, #1
 8000f8c:	613b      	str	r3, [r7, #16]
 8000f8e:	687b      	ldr	r3, [r7, #4]
 8000f90:	3306      	adds	r3, #6
 8000f92:	781b      	ldrb	r3, [r3, #0]
 8000f94:	461a      	mov	r2, r3
 8000f96:	693b      	ldr	r3, [r7, #16]
 8000f98:	4293      	cmp	r3, r2
 8000f9a:	dbe2      	blt.n	8000f62 <NessLab_Operate+0x9a>
            }
            FLASH_Write_Func(&Flash_DataArray[0],data[NessLab_DataLength]);
 8000f9c:	687b      	ldr	r3, [r7, #4]
 8000f9e:	3306      	adds	r3, #6
 8000fa0:	781b      	ldrb	r3, [r3, #0]
 8000fa2:	4619      	mov	r1, r3
 8000fa4:	480f      	ldr	r0, [pc, #60]	; (8000fe4 <NessLab_Operate+0x11c>)
 8000fa6:	f000 fa83 	bl	80014b0 <FLASH_Write_Func>
            UartLength = NESSLAB_TABLE_LENGTH;
 8000faa:	236e      	movs	r3, #110	; 0x6e
 8000fac:	75fb      	strb	r3, [r7, #23]
            NessLab_Table_Frame_Set(NessLab_TxData,100);
 8000fae:	2164      	movs	r1, #100	; 0x64
 8000fb0:	4808      	ldr	r0, [pc, #32]	; (8000fd4 <NessLab_Operate+0x10c>)
 8000fb2:	f000 f8d3 	bl	800115c <NessLab_Table_Frame_Set>
            printf("\r\nNessLab_TableSet_REQ \r\n");            
 8000fb6:	480d      	ldr	r0, [pc, #52]	; (8000fec <NessLab_Operate+0x124>)
 8000fb8:	f005 f9f4 	bl	80063a4 <puts>
            break;
 8000fbc:	bf00      	nop
	}
    Uart1_Data_Send(&NessLab_TxData[NessLab_Header0], UartLength);
 8000fbe:	7dfb      	ldrb	r3, [r7, #23]
 8000fc0:	4619      	mov	r1, r3
 8000fc2:	4804      	ldr	r0, [pc, #16]	; (8000fd4 <NessLab_Operate+0x10c>)
 8000fc4:	f000 fbf2 	bl	80017ac <Uart1_Data_Send>
}
 8000fc8:	bf00      	nop
 8000fca:	3718      	adds	r7, #24
 8000fcc:	46bd      	mov	sp, r7
 8000fce:	bd80      	pop	{r7, pc}
 8000fd0:	2000038c 	.word	0x2000038c
 8000fd4:	200001fc 	.word	0x200001fc
 8000fd8:	080082b8 	.word	0x080082b8
 8000fdc:	0800ff38 	.word	0x0800ff38
 8000fe0:	080082cc 	.word	0x080082cc
 8000fe4:	200002c4 	.word	0x200002c4
 8000fe8:	080082e0 	.word	0x080082e0
 8000fec:	080082e4 	.word	0x080082e4

08000ff0 <NessLab_Frame_Set>:



void NessLab_Frame_Set(uint8_t* data,uint8_t size){
 8000ff0:	b590      	push	{r4, r7, lr}
 8000ff2:	b083      	sub	sp, #12
 8000ff4:	af00      	add	r7, sp, #0
 8000ff6:	6078      	str	r0, [r7, #4]
 8000ff8:	460b      	mov	r3, r1
 8000ffa:	70fb      	strb	r3, [r7, #3]
    data[NessLab_Header0] = 0x7E;
 8000ffc:	687b      	ldr	r3, [r7, #4]
 8000ffe:	227e      	movs	r2, #126	; 0x7e
 8001000:	701a      	strb	r2, [r3, #0]
    data[NessLab_Header1] = 0x7E;
 8001002:	687b      	ldr	r3, [r7, #4]
 8001004:	3301      	adds	r3, #1
 8001006:	227e      	movs	r2, #126	; 0x7e
 8001008:	701a      	strb	r2, [r3, #0]

    data[NessLab_MsgID0] = NessLab_STATUS_RES;// ID
 800100a:	687b      	ldr	r3, [r7, #4]
 800100c:	3302      	adds	r3, #2
 800100e:	2266      	movs	r2, #102	; 0x66
 8001010:	701a      	strb	r2, [r3, #0]
//    data[NessLab_MsgSN0] = 0; // SEQ NUMBER
//    data[NessLab_MsgSN1] = 0; // SEQ NUMBER   
    data[NessLab_Reserve0] = 0; // NessLab_Reserve0
 8001012:	687b      	ldr	r3, [r7, #4]
 8001014:	3305      	adds	r3, #5
 8001016:	2200      	movs	r2, #0
 8001018:	701a      	strb	r2, [r3, #0]
    data[NessLab_DataLength] = size; // Nesslab Size
 800101a:	687b      	ldr	r3, [r7, #4]
 800101c:	3306      	adds	r3, #6
 800101e:	78fa      	ldrb	r2, [r7, #3]
 8001020:	701a      	strb	r2, [r3, #0]
    data[NessLab_Data_ADC1_H] =  Currstatus.DownLink_Forward_Det_H;//(uint8_t)((ADC1value[0] & 0xFF00) >> 8);
 8001022:	687b      	ldr	r3, [r7, #4]
 8001024:	3307      	adds	r3, #7
 8001026:	4a4c      	ldr	r2, [pc, #304]	; (8001158 <NessLab_Frame_Set+0x168>)
 8001028:	79d2      	ldrb	r2, [r2, #7]
 800102a:	701a      	strb	r2, [r3, #0]
    data[NessLab_Data_ADC1_L] =  Currstatus.DownLink_Forward_Det_L;//(uint8_t)(ADC1value[0] & 0x00FF);
 800102c:	687b      	ldr	r3, [r7, #4]
 800102e:	3308      	adds	r3, #8
 8001030:	4a49      	ldr	r2, [pc, #292]	; (8001158 <NessLab_Frame_Set+0x168>)
 8001032:	7a12      	ldrb	r2, [r2, #8]
 8001034:	701a      	strb	r2, [r3, #0]
    data[NessLab_Data_ADC1_L + 1]++;
 8001036:	687b      	ldr	r3, [r7, #4]
 8001038:	3309      	adds	r3, #9
 800103a:	781a      	ldrb	r2, [r3, #0]
 800103c:	3201      	adds	r2, #1
 800103e:	b2d2      	uxtb	r2, r2
 8001040:	701a      	strb	r2, [r3, #0]
    if( data[NessLab_DC_FAIL_ALARM] == 0)
 8001042:	687b      	ldr	r3, [r7, #4]
 8001044:	330a      	adds	r3, #10
 8001046:	781b      	ldrb	r3, [r3, #0]
 8001048:	2b00      	cmp	r3, #0
 800104a:	d104      	bne.n	8001056 <NessLab_Frame_Set+0x66>
        data[NessLab_DC_FAIL_ALARM] = 1;
 800104c:	687b      	ldr	r3, [r7, #4]
 800104e:	330a      	adds	r3, #10
 8001050:	2201      	movs	r2, #1
 8001052:	701a      	strb	r2, [r3, #0]
 8001054:	e003      	b.n	800105e <NessLab_Frame_Set+0x6e>
    else
        data[NessLab_DC_FAIL_ALARM] = 0;
 8001056:	687b      	ldr	r3, [r7, #4]
 8001058:	330a      	adds	r3, #10
 800105a:	2200      	movs	r2, #0
 800105c:	701a      	strb	r2, [r3, #0]
    
    if( data[NessLab_DownLink_Status] == 0)
 800105e:	687b      	ldr	r3, [r7, #4]
 8001060:	330b      	adds	r3, #11
 8001062:	781b      	ldrb	r3, [r3, #0]
 8001064:	2b00      	cmp	r3, #0
 8001066:	d104      	bne.n	8001072 <NessLab_Frame_Set+0x82>
        data[NessLab_DownLink_Status] = 1;
 8001068:	687b      	ldr	r3, [r7, #4]
 800106a:	330b      	adds	r3, #11
 800106c:	2201      	movs	r2, #1
 800106e:	701a      	strb	r2, [r3, #0]
 8001070:	e003      	b.n	800107a <NessLab_Frame_Set+0x8a>
    else
        data[NessLab_DownLink_Status] = 0;
 8001072:	687b      	ldr	r3, [r7, #4]
 8001074:	330b      	adds	r3, #11
 8001076:	2200      	movs	r2, #0
 8001078:	701a      	strb	r2, [r3, #0]


    if( data[NessLab_Over_Power_Alarm] == 0)
 800107a:	687b      	ldr	r3, [r7, #4]
 800107c:	330c      	adds	r3, #12
 800107e:	781b      	ldrb	r3, [r3, #0]
 8001080:	2b00      	cmp	r3, #0
 8001082:	d104      	bne.n	800108e <NessLab_Frame_Set+0x9e>
        data[NessLab_Over_Power_Alarm] = 1;
 8001084:	687b      	ldr	r3, [r7, #4]
 8001086:	330c      	adds	r3, #12
 8001088:	2201      	movs	r2, #1
 800108a:	701a      	strb	r2, [r3, #0]
 800108c:	e003      	b.n	8001096 <NessLab_Frame_Set+0xa6>
    else
        data[NessLab_Over_Power_Alarm] = 0;        
 800108e:	687b      	ldr	r3, [r7, #4]
 8001090:	330c      	adds	r3, #12
 8001092:	2200      	movs	r2, #0
 8001094:	701a      	strb	r2, [r3, #0]
//    data[NessLab_Over_Power_Alarm] = 00;
    if( data[NessLab_VSWR_ALARM] == 0)
 8001096:	687b      	ldr	r3, [r7, #4]
 8001098:	330d      	adds	r3, #13
 800109a:	781b      	ldrb	r3, [r3, #0]
 800109c:	2b00      	cmp	r3, #0
 800109e:	d104      	bne.n	80010aa <NessLab_Frame_Set+0xba>
        data[NessLab_VSWR_ALARM] = 1;
 80010a0:	687b      	ldr	r3, [r7, #4]
 80010a2:	330d      	adds	r3, #13
 80010a4:	2201      	movs	r2, #1
 80010a6:	701a      	strb	r2, [r3, #0]
 80010a8:	e003      	b.n	80010b2 <NessLab_Frame_Set+0xc2>
    else
        data[NessLab_VSWR_ALARM] = 0;  
 80010aa:	687b      	ldr	r3, [r7, #4]
 80010ac:	330d      	adds	r3, #13
 80010ae:	2200      	movs	r2, #0
 80010b0:	701a      	strb	r2, [r3, #0]

//    data[NessLab_VSWR_ALARM] = 0;
    if( data[NessLab_Over_Input_Alarm] == 0)
 80010b2:	687b      	ldr	r3, [r7, #4]
 80010b4:	330e      	adds	r3, #14
 80010b6:	781b      	ldrb	r3, [r3, #0]
 80010b8:	2b00      	cmp	r3, #0
 80010ba:	d104      	bne.n	80010c6 <NessLab_Frame_Set+0xd6>
        data[NessLab_Over_Input_Alarm] = 1;
 80010bc:	687b      	ldr	r3, [r7, #4]
 80010be:	330e      	adds	r3, #14
 80010c0:	2201      	movs	r2, #1
 80010c2:	701a      	strb	r2, [r3, #0]
 80010c4:	e003      	b.n	80010ce <NessLab_Frame_Set+0xde>
    else
        data[NessLab_Over_Input_Alarm] = 0;  
 80010c6:	687b      	ldr	r3, [r7, #4]
 80010c8:	330e      	adds	r3, #14
 80010ca:	2200      	movs	r2, #0
 80010cc:	701a      	strb	r2, [r3, #0]
    
//    data[NessLab_Over_Input_Alarm] = 0;
    if( data[NessLab_Over_Temp_Alarm] == 0)
 80010ce:	687b      	ldr	r3, [r7, #4]
 80010d0:	330f      	adds	r3, #15
 80010d2:	781b      	ldrb	r3, [r3, #0]
 80010d4:	2b00      	cmp	r3, #0
 80010d6:	d104      	bne.n	80010e2 <NessLab_Frame_Set+0xf2>
        data[NessLab_Over_Temp_Alarm] = 1;
 80010d8:	687b      	ldr	r3, [r7, #4]
 80010da:	330f      	adds	r3, #15
 80010dc:	2201      	movs	r2, #1
 80010de:	701a      	strb	r2, [r3, #0]
 80010e0:	e003      	b.n	80010ea <NessLab_Frame_Set+0xfa>
    else
        data[NessLab_Over_Temp_Alarm] = 0; 
 80010e2:	687b      	ldr	r3, [r7, #4]
 80010e4:	330f      	adds	r3, #15
 80010e6:	2200      	movs	r2, #0
 80010e8:	701a      	strb	r2, [r3, #0]

//    data[NessLab_Over_Temp_Alarm] = 0;
    if( data[NessLab_Temp_Monitor] == 0)
 80010ea:	687b      	ldr	r3, [r7, #4]
 80010ec:	3310      	adds	r3, #16
 80010ee:	781b      	ldrb	r3, [r3, #0]
 80010f0:	2b00      	cmp	r3, #0
 80010f2:	d104      	bne.n	80010fe <NessLab_Frame_Set+0x10e>
        data[NessLab_Temp_Monitor] = 1;
 80010f4:	687b      	ldr	r3, [r7, #4]
 80010f6:	3310      	adds	r3, #16
 80010f8:	2201      	movs	r2, #1
 80010fa:	701a      	strb	r2, [r3, #0]
 80010fc:	e003      	b.n	8001106 <NessLab_Frame_Set+0x116>
    else
        data[NessLab_Temp_Monitor] = 0; 
 80010fe:	687b      	ldr	r3, [r7, #4]
 8001100:	3310      	adds	r3, #16
 8001102:	2200      	movs	r2, #0
 8001104:	701a      	strb	r2, [r3, #0]

//    data[NessLab_Temp_Monitor] = 0;
    if( data[NessLab_ALC_ALARM] == 0)
 8001106:	687b      	ldr	r3, [r7, #4]
 8001108:	3311      	adds	r3, #17
 800110a:	781b      	ldrb	r3, [r3, #0]
 800110c:	2b00      	cmp	r3, #0
 800110e:	d104      	bne.n	800111a <NessLab_Frame_Set+0x12a>
        data[NessLab_ALC_ALARM] = 1;
 8001110:	687b      	ldr	r3, [r7, #4]
 8001112:	3311      	adds	r3, #17
 8001114:	2201      	movs	r2, #1
 8001116:	701a      	strb	r2, [r3, #0]
 8001118:	e003      	b.n	8001122 <NessLab_Frame_Set+0x132>
    else
        data[NessLab_ALC_ALARM] = 0; 
 800111a:	687b      	ldr	r3, [r7, #4]
 800111c:	3311      	adds	r3, #17
 800111e:	2200      	movs	r2, #0
 8001120:	701a      	strb	r2, [r3, #0]

//    data[NessLab_ALC_ALARM] = 0;
    data[NessLab_ChecksumVal] = NessLab_Checksum(&data[NessLab_MsgID0], NessLab_MAX_INDEX - 5);
 8001122:	687b      	ldr	r3, [r7, #4]
 8001124:	1c9a      	adds	r2, r3, #2
 8001126:	687b      	ldr	r3, [r7, #4]
 8001128:	f103 0412 	add.w	r4, r3, #18
 800112c:	2110      	movs	r1, #16
 800112e:	4610      	mov	r0, r2
 8001130:	f000 f90f 	bl	8001352 <NessLab_Checksum>
 8001134:	4603      	mov	r3, r0
 8001136:	7023      	strb	r3, [r4, #0]
    /* Exception Header Tail Checksum */
    data[NessLab_Tail0] = 0x7E;
 8001138:	687b      	ldr	r3, [r7, #4]
 800113a:	3313      	adds	r3, #19
 800113c:	227e      	movs	r2, #126	; 0x7e
 800113e:	701a      	strb	r2, [r3, #0]
    data[NessLab_Tail1] = 0x7E; 
 8001140:	687b      	ldr	r3, [r7, #4]
 8001142:	3314      	adds	r3, #20
 8001144:	227e      	movs	r2, #126	; 0x7e
 8001146:	701a      	strb	r2, [r3, #0]
    data[NessLab_Tail1 + 1] = 0x0A; 
 8001148:	687b      	ldr	r3, [r7, #4]
 800114a:	3315      	adds	r3, #21
 800114c:	220a      	movs	r2, #10
 800114e:	701a      	strb	r2, [r3, #0]
}
 8001150:	bf00      	nop
 8001152:	370c      	adds	r7, #12
 8001154:	46bd      	mov	sp, r7
 8001156:	bd90      	pop	{r4, r7, pc}
 8001158:	200003fc 	.word	0x200003fc

0800115c <NessLab_Table_Frame_Set>:


void NessLab_Table_Frame_Set(uint8_t* data,uint8_t size){
 800115c:	b590      	push	{r4, r7, lr}
 800115e:	b087      	sub	sp, #28
 8001160:	af00      	add	r7, sp, #0
 8001162:	6078      	str	r0, [r7, #4]
 8001164:	460b      	mov	r3, r1
 8001166:	70fb      	strb	r3, [r7, #3]
    uint32_t i = 0;
 8001168:	2300      	movs	r3, #0
 800116a:	617b      	str	r3, [r7, #20]
    uint32_t  CurrApiAddress = 0;
 800116c:	2300      	movs	r3, #0
 800116e:	60fb      	str	r3, [r7, #12]
    CurrApiAddress = FLASH_USER_USE_START_ADDR;
 8001170:	4b33      	ldr	r3, [pc, #204]	; (8001240 <NessLab_Table_Frame_Set+0xe4>)
 8001172:	60fb      	str	r3, [r7, #12]
    uint8_t* Currdata = (uint8_t*)CurrApiAddress;
 8001174:	68fb      	ldr	r3, [r7, #12]
 8001176:	60bb      	str	r3, [r7, #8]
    uint8_t* pdata;



    data[i++] = 0x7E;
 8001178:	697b      	ldr	r3, [r7, #20]
 800117a:	1c5a      	adds	r2, r3, #1
 800117c:	617a      	str	r2, [r7, #20]
 800117e:	687a      	ldr	r2, [r7, #4]
 8001180:	4413      	add	r3, r2
 8001182:	227e      	movs	r2, #126	; 0x7e
 8001184:	701a      	strb	r2, [r3, #0]
    data[i++] = 0x7E;
 8001186:	697b      	ldr	r3, [r7, #20]
 8001188:	1c5a      	adds	r2, r3, #1
 800118a:	617a      	str	r2, [r7, #20]
 800118c:	687a      	ldr	r2, [r7, #4]
 800118e:	4413      	add	r3, r2
 8001190:	227e      	movs	r2, #126	; 0x7e
 8001192:	701a      	strb	r2, [r3, #0]

    data[i++] = NessLab_STATUS_RES;// ID
 8001194:	697b      	ldr	r3, [r7, #20]
 8001196:	1c5a      	adds	r2, r3, #1
 8001198:	617a      	str	r2, [r7, #20]
 800119a:	687a      	ldr	r2, [r7, #4]
 800119c:	4413      	add	r3, r2
 800119e:	2266      	movs	r2, #102	; 0x66
 80011a0:	701a      	strb	r2, [r3, #0]
    data[i++] = 0; // SEQ NUMBER
 80011a2:	697b      	ldr	r3, [r7, #20]
 80011a4:	1c5a      	adds	r2, r3, #1
 80011a6:	617a      	str	r2, [r7, #20]
 80011a8:	687a      	ldr	r2, [r7, #4]
 80011aa:	4413      	add	r3, r2
 80011ac:	2200      	movs	r2, #0
 80011ae:	701a      	strb	r2, [r3, #0]
    data[i++] = 0; // SEQ NUMBER   
 80011b0:	697b      	ldr	r3, [r7, #20]
 80011b2:	1c5a      	adds	r2, r3, #1
 80011b4:	617a      	str	r2, [r7, #20]
 80011b6:	687a      	ldr	r2, [r7, #4]
 80011b8:	4413      	add	r3, r2
 80011ba:	2200      	movs	r2, #0
 80011bc:	701a      	strb	r2, [r3, #0]
    data[i++] = 0; // NessLab_Reserve0
 80011be:	697b      	ldr	r3, [r7, #20]
 80011c0:	1c5a      	adds	r2, r3, #1
 80011c2:	617a      	str	r2, [r7, #20]
 80011c4:	687a      	ldr	r2, [r7, #4]
 80011c6:	4413      	add	r3, r2
 80011c8:	2200      	movs	r2, #0
 80011ca:	701a      	strb	r2, [r3, #0]
    data[i++] = size; // Nesslab Size
 80011cc:	697b      	ldr	r3, [r7, #20]
 80011ce:	1c5a      	adds	r2, r3, #1
 80011d0:	617a      	str	r2, [r7, #20]
 80011d2:	687a      	ldr	r2, [r7, #4]
 80011d4:	4413      	add	r3, r2
 80011d6:	78fa      	ldrb	r2, [r7, #3]
 80011d8:	701a      	strb	r2, [r3, #0]
    //    NessLab_TalbleFlash_Read(&data[NessLab_DataLength + 1],100);              

    for(int a = 0; a < size; a++){
 80011da:	2300      	movs	r3, #0
 80011dc:	613b      	str	r3, [r7, #16]
 80011de:	e00c      	b.n	80011fa <NessLab_Table_Frame_Set+0x9e>
        data[i++] = Currdata[a];
 80011e0:	693b      	ldr	r3, [r7, #16]
 80011e2:	68ba      	ldr	r2, [r7, #8]
 80011e4:	441a      	add	r2, r3
 80011e6:	697b      	ldr	r3, [r7, #20]
 80011e8:	1c59      	adds	r1, r3, #1
 80011ea:	6179      	str	r1, [r7, #20]
 80011ec:	6879      	ldr	r1, [r7, #4]
 80011ee:	440b      	add	r3, r1
 80011f0:	7812      	ldrb	r2, [r2, #0]
 80011f2:	701a      	strb	r2, [r3, #0]
    for(int a = 0; a < size; a++){
 80011f4:	693b      	ldr	r3, [r7, #16]
 80011f6:	3301      	adds	r3, #1
 80011f8:	613b      	str	r3, [r7, #16]
 80011fa:	78fb      	ldrb	r3, [r7, #3]
 80011fc:	693a      	ldr	r2, [r7, #16]
 80011fe:	429a      	cmp	r2, r3
 8001200:	dbee      	blt.n	80011e0 <NessLab_Table_Frame_Set+0x84>
//        printf("%02x ",Currdata[i]);
    }
    data[i++] = NessLab_Checksum(&data[NessLab_MsgID0], 100 + 5);
 8001202:	687b      	ldr	r3, [r7, #4]
 8001204:	1c98      	adds	r0, r3, #2
 8001206:	697b      	ldr	r3, [r7, #20]
 8001208:	1c5a      	adds	r2, r3, #1
 800120a:	617a      	str	r2, [r7, #20]
 800120c:	687a      	ldr	r2, [r7, #4]
 800120e:	18d4      	adds	r4, r2, r3
 8001210:	2169      	movs	r1, #105	; 0x69
 8001212:	f000 f89e 	bl	8001352 <NessLab_Checksum>
 8001216:	4603      	mov	r3, r0
 8001218:	7023      	strb	r3, [r4, #0]
    /* Exception Header Tail Checksum */
    data[i++] = 0x7E;
 800121a:	697b      	ldr	r3, [r7, #20]
 800121c:	1c5a      	adds	r2, r3, #1
 800121e:	617a      	str	r2, [r7, #20]
 8001220:	687a      	ldr	r2, [r7, #4]
 8001222:	4413      	add	r3, r2
 8001224:	227e      	movs	r2, #126	; 0x7e
 8001226:	701a      	strb	r2, [r3, #0]
    data[i++] = 0x7E; 
 8001228:	697b      	ldr	r3, [r7, #20]
 800122a:	1c5a      	adds	r2, r3, #1
 800122c:	617a      	str	r2, [r7, #20]
 800122e:	687a      	ldr	r2, [r7, #4]
 8001230:	4413      	add	r3, r2
 8001232:	227e      	movs	r2, #126	; 0x7e
 8001234:	701a      	strb	r2, [r3, #0]
}
 8001236:	bf00      	nop
 8001238:	371c      	adds	r7, #28
 800123a:	46bd      	mov	sp, r7
 800123c:	bd90      	pop	{r4, r7, pc}
 800123e:	bf00      	nop
 8001240:	0800ff38 	.word	0x0800ff38

08001244 <ADC_Initialize>:
	/*Temp Calc*/
	Currstatus.Temp_Monitor = ((ADC1value[1] & 0xFF00) >> 8);


}
void ADC_Initialize(){
 8001244:	b580      	push	{r7, lr}
 8001246:	af00      	add	r7, sp, #0
	while(!(HAL_ADCEx_Calibration_Start(&hadc1)==HAL_OK));
 8001248:	bf00      	nop
 800124a:	4806      	ldr	r0, [pc, #24]	; (8001264 <ADC_Initialize+0x20>)
 800124c:	f000 ff64 	bl	8002118 <HAL_ADCEx_Calibration_Start>
 8001250:	4603      	mov	r3, r0
 8001252:	2b00      	cmp	r3, #0
 8001254:	d1f9      	bne.n	800124a <ADC_Initialize+0x6>
	HAL_ADC_Start_DMA(&hadc1, (uint16_t*)ADC1value,(uint32_t) 3);
 8001256:	2203      	movs	r2, #3
 8001258:	4903      	ldr	r1, [pc, #12]	; (8001268 <ADC_Initialize+0x24>)
 800125a:	4802      	ldr	r0, [pc, #8]	; (8001264 <ADC_Initialize+0x20>)
 800125c:	f000 fbfa 	bl	8001a54 <HAL_ADC_Start_DMA>
}
 8001260:	bf00      	nop
 8001262:	bd80      	pop	{r7, pc}
 8001264:	2000076c 	.word	0x2000076c
 8001268:	20000414 	.word	0x20000414
 800126c:	00000000 	.word	0x00000000

08001270 <ADC_Check>:

void ADC_Check(){
 8001270:	b590      	push	{r4, r7, lr}
 8001272:	b083      	sub	sp, #12
 8001274:	af00      	add	r7, sp, #0
    float tempval = 0;
 8001276:	f04f 0300 	mov.w	r3, #0
 800127a:	607b      	str	r3, [r7, #4]
    for(int i = 0 ; i < 1; i++){
 800127c:	2300      	movs	r3, #0
 800127e:	603b      	str	r3, [r7, #0]
 8001280:	e01d      	b.n	80012be <ADC_Check+0x4e>
        tempval = (ADC1value[i] * (3.3 / 4095));
 8001282:	4a29      	ldr	r2, [pc, #164]	; (8001328 <ADC_Check+0xb8>)
 8001284:	683b      	ldr	r3, [r7, #0]
 8001286:	f832 3013 	ldrh.w	r3, [r2, r3, lsl #1]
 800128a:	b29b      	uxth	r3, r3
 800128c:	4618      	mov	r0, r3
 800128e:	f7ff f919 	bl	80004c4 <__aeabi_i2d>
 8001292:	a323      	add	r3, pc, #140	; (adr r3, 8001320 <ADC_Check+0xb0>)
 8001294:	e9d3 2300 	ldrd	r2, r3, [r3]
 8001298:	f7ff f97e 	bl	8000598 <__aeabi_dmul>
 800129c:	4603      	mov	r3, r0
 800129e:	460c      	mov	r4, r1
 80012a0:	4618      	mov	r0, r3
 80012a2:	4621      	mov	r1, r4
 80012a4:	f7ff fc50 	bl	8000b48 <__aeabi_d2f>
 80012a8:	4603      	mov	r3, r0
 80012aa:	607b      	str	r3, [r7, #4]
        tempval *= 1000;
 80012ac:	491f      	ldr	r1, [pc, #124]	; (800132c <ADC_Check+0xbc>)
 80012ae:	6878      	ldr	r0, [r7, #4]
 80012b0:	f7ff fc9a 	bl	8000be8 <__aeabi_fmul>
 80012b4:	4603      	mov	r3, r0
 80012b6:	607b      	str	r3, [r7, #4]
    for(int i = 0 ; i < 1; i++){
 80012b8:	683b      	ldr	r3, [r7, #0]
 80012ba:	3301      	adds	r3, #1
 80012bc:	603b      	str	r3, [r7, #0]
 80012be:	683b      	ldr	r3, [r7, #0]
 80012c0:	2b00      	cmp	r3, #0
 80012c2:	ddde      	ble.n	8001282 <ADC_Check+0x12>
    }
    printf("ADC1value[%d] : %f \r\n",0,tempval);
 80012c4:	6878      	ldr	r0, [r7, #4]
 80012c6:	f7ff f90f 	bl	80004e8 <__aeabi_f2d>
 80012ca:	4603      	mov	r3, r0
 80012cc:	460c      	mov	r4, r1
 80012ce:	461a      	mov	r2, r3
 80012d0:	4623      	mov	r3, r4
 80012d2:	2100      	movs	r1, #0
 80012d4:	4816      	ldr	r0, [pc, #88]	; (8001330 <ADC_Check+0xc0>)
 80012d6:	f004 fff1 	bl	80062bc <iprintf>
//    printf("ADC1value[%d] : %d \r\n",i,ADC1value[i] );
#if 1 // PYJ.2020.08.26_BEGIN -- 
    Currstatus.DownLink_Forward_Det_H
        = (((uint16_t)tempval & 0xFF00) >> 8);
 80012da:	6878      	ldr	r0, [r7, #4]
 80012dc:	f7ff fdd4 	bl	8000e88 <__aeabi_f2uiz>
 80012e0:	4603      	mov	r3, r0
 80012e2:	b29b      	uxth	r3, r3
 80012e4:	0a1b      	lsrs	r3, r3, #8
 80012e6:	b29b      	uxth	r3, r3
 80012e8:	b2da      	uxtb	r2, r3
 80012ea:	4b12      	ldr	r3, [pc, #72]	; (8001334 <ADC_Check+0xc4>)
 80012ec:	71da      	strb	r2, [r3, #7]
    Currstatus.DownLink_Forward_Det_L
        = (((uint16_t)tempval & 0x00FF) );
 80012ee:	6878      	ldr	r0, [r7, #4]
 80012f0:	f7ff fdca 	bl	8000e88 <__aeabi_f2uiz>
 80012f4:	4603      	mov	r3, r0
 80012f6:	b29b      	uxth	r3, r3
 80012f8:	b2da      	uxtb	r2, r3
 80012fa:	4b0e      	ldr	r3, [pc, #56]	; (8001334 <ADC_Check+0xc4>)
 80012fc:	721a      	strb	r2, [r3, #8]
    printf("Currstatus.DownLink_Forward_Det : %d \r\n",Currstatus.DownLink_Forward_Det_H << 8 | Currstatus.DownLink_Forward_Det_L);
 80012fe:	4b0d      	ldr	r3, [pc, #52]	; (8001334 <ADC_Check+0xc4>)
 8001300:	79db      	ldrb	r3, [r3, #7]
 8001302:	021b      	lsls	r3, r3, #8
 8001304:	4a0b      	ldr	r2, [pc, #44]	; (8001334 <ADC_Check+0xc4>)
 8001306:	7a12      	ldrb	r2, [r2, #8]
 8001308:	4313      	orrs	r3, r2
 800130a:	4619      	mov	r1, r3
 800130c:	480a      	ldr	r0, [pc, #40]	; (8001338 <ADC_Check+0xc8>)
 800130e:	f004 ffd5 	bl	80062bc <iprintf>
#endif // PYJ.2020.08.26_END -- 
    adc1cnt = 0;
 8001312:	4b0a      	ldr	r3, [pc, #40]	; (800133c <ADC_Check+0xcc>)
 8001314:	2200      	movs	r2, #0
 8001316:	801a      	strh	r2, [r3, #0]
}
 8001318:	bf00      	nop
 800131a:	370c      	adds	r7, #12
 800131c:	46bd      	mov	sp, r7
 800131e:	bd90      	pop	{r4, r7, pc}
 8001320:	e734d9b4 	.word	0xe734d9b4
 8001324:	3f4a680c 	.word	0x3f4a680c
 8001328:	20000414 	.word	0x20000414
 800132c:	447a0000 	.word	0x447a0000
 8001330:	08008300 	.word	0x08008300
 8001334:	200003fc 	.word	0x200003fc
 8001338:	08008318 	.word	0x08008318
 800133c:	2000038e 	.word	0x2000038e

08001340 <HAL_ADC_ConvCpltCallback>:
void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
{
 8001340:	b480      	push	{r7}
 8001342:	b083      	sub	sp, #12
 8001344:	af00      	add	r7, sp, #0
 8001346:	6078      	str	r0, [r7, #4]
//                ADC1valuearray[i][adc1cnt] = ADC1value[i];
//            }
//            adc1cnt++;
//        }
    }
}
 8001348:	bf00      	nop
 800134a:	370c      	adds	r7, #12
 800134c:	46bd      	mov	sp, r7
 800134e:	bc80      	pop	{r7}
 8001350:	4770      	bx	lr

08001352 <NessLab_Checksum>:
						
    crcret ^ ~0U;		

    return (crcret == checksum ? CHECKSUM_ERROR : NO_ERROR);
}
uint8_t NessLab_Checksum(uint8_t *data,uint8_t size){
 8001352:	b480      	push	{r7}
 8001354:	b085      	sub	sp, #20
 8001356:	af00      	add	r7, sp, #0
 8001358:	6078      	str	r0, [r7, #4]
 800135a:	460b      	mov	r3, r1
 800135c:	70fb      	strb	r3, [r7, #3]
	uint16_t ret = 0;
 800135e:	2300      	movs	r3, #0
 8001360:	81fb      	strh	r3, [r7, #14]
//    printf("Crc Process : ");
	for(int i = 0; i < size; i++){
 8001362:	2300      	movs	r3, #0
 8001364:	60bb      	str	r3, [r7, #8]
 8001366:	e00c      	b.n	8001382 <NessLab_Checksum+0x30>
		ret = ((ret + data[i]) & 0xFF);
 8001368:	68bb      	ldr	r3, [r7, #8]
 800136a:	687a      	ldr	r2, [r7, #4]
 800136c:	4413      	add	r3, r2
 800136e:	781b      	ldrb	r3, [r3, #0]
 8001370:	b29a      	uxth	r2, r3
 8001372:	89fb      	ldrh	r3, [r7, #14]
 8001374:	4413      	add	r3, r2
 8001376:	b29b      	uxth	r3, r3
 8001378:	b2db      	uxtb	r3, r3
 800137a:	81fb      	strh	r3, [r7, #14]
	for(int i = 0; i < size; i++){
 800137c:	68bb      	ldr	r3, [r7, #8]
 800137e:	3301      	adds	r3, #1
 8001380:	60bb      	str	r3, [r7, #8]
 8001382:	78fb      	ldrb	r3, [r7, #3]
 8001384:	68ba      	ldr	r2, [r7, #8]
 8001386:	429a      	cmp	r2, r3
 8001388:	dbee      	blt.n	8001368 <NessLab_Checksum+0x16>
//        printf(" %x + %x \r\n",ret,data[i]);
	}
//    printf("Result : ");

	ret = (~ret) + 1;
 800138a:	89fb      	ldrh	r3, [r7, #14]
 800138c:	425b      	negs	r3, r3
 800138e:	81fb      	strh	r3, [r7, #14]
//     printf("ret [i] : %x \r\n",ret);
	return (uint8_t)(ret & 0x00FF);
 8001390:	89fb      	ldrh	r3, [r7, #14]
 8001392:	b2db      	uxtb	r3, r3
}
 8001394:	4618      	mov	r0, r3
 8001396:	3714      	adds	r7, #20
 8001398:	46bd      	mov	sp, r7
 800139a:	bc80      	pop	{r7}
 800139c:	4770      	bx	lr
	...

080013a0 <NessLab_CheckSum_Check>:
bool NessLab_CheckSum_Check(uint8_t* data,uint8_t size,uint8_t checksum){
 80013a0:	b580      	push	{r7, lr}
 80013a2:	b084      	sub	sp, #16
 80013a4:	af00      	add	r7, sp, #0
 80013a6:	6078      	str	r0, [r7, #4]
 80013a8:	460b      	mov	r3, r1
 80013aa:	70fb      	strb	r3, [r7, #3]
 80013ac:	4613      	mov	r3, r2
 80013ae:	70bb      	strb	r3, [r7, #2]
	uint8_t dataret = 0;
 80013b0:	2300      	movs	r3, #0
 80013b2:	73fb      	strb	r3, [r7, #15]
	bool ret = false;
 80013b4:	2300      	movs	r3, #0
 80013b6:	73bb      	strb	r3, [r7, #14]
//    printf("size : %d \r\n",size);
	for(int i = 0; i < size; i++){
 80013b8:	2300      	movs	r3, #0
 80013ba:	60bb      	str	r3, [r7, #8]
 80013bc:	e009      	b.n	80013d2 <NessLab_CheckSum_Check+0x32>
		dataret += data[i];
 80013be:	68bb      	ldr	r3, [r7, #8]
 80013c0:	687a      	ldr	r2, [r7, #4]
 80013c2:	4413      	add	r3, r2
 80013c4:	781a      	ldrb	r2, [r3, #0]
 80013c6:	7bfb      	ldrb	r3, [r7, #15]
 80013c8:	4413      	add	r3, r2
 80013ca:	73fb      	strb	r3, [r7, #15]
	for(int i = 0; i < size; i++){
 80013cc:	68bb      	ldr	r3, [r7, #8]
 80013ce:	3301      	adds	r3, #1
 80013d0:	60bb      	str	r3, [r7, #8]
 80013d2:	78fb      	ldrb	r3, [r7, #3]
 80013d4:	68ba      	ldr	r2, [r7, #8]
 80013d6:	429a      	cmp	r2, r3
 80013d8:	dbf1      	blt.n	80013be <NessLab_CheckSum_Check+0x1e>
//        printf("data [i] : %x \r\n",data[i]);
	}

	dataret = (~dataret) + 1;
 80013da:	7bfb      	ldrb	r3, [r7, #15]
 80013dc:	425b      	negs	r3, r3
 80013de:	73fb      	strb	r3, [r7, #15]
    printf("\r\ndataret : %x /// checksum : %x \r\n",dataret,checksum);
 80013e0:	7bfb      	ldrb	r3, [r7, #15]
 80013e2:	78ba      	ldrb	r2, [r7, #2]
 80013e4:	4619      	mov	r1, r3
 80013e6:	4808      	ldr	r0, [pc, #32]	; (8001408 <NessLab_CheckSum_Check+0x68>)
 80013e8:	f004 ff68 	bl	80062bc <iprintf>
	if(dataret != checksum){
 80013ec:	7bfa      	ldrb	r2, [r7, #15]
 80013ee:	78bb      	ldrb	r3, [r7, #2]
 80013f0:	429a      	cmp	r2, r3
 80013f2:	d002      	beq.n	80013fa <NessLab_CheckSum_Check+0x5a>
		ret = false;
 80013f4:	2300      	movs	r3, #0
 80013f6:	73bb      	strb	r3, [r7, #14]
 80013f8:	e001      	b.n	80013fe <NessLab_CheckSum_Check+0x5e>
	}else{
		ret = true;
 80013fa:	2301      	movs	r3, #1
 80013fc:	73bb      	strb	r3, [r7, #14]
	}
	return ret;
 80013fe:	7bbb      	ldrb	r3, [r7, #14]
}
 8001400:	4618      	mov	r0, r3
 8001402:	3710      	adds	r7, #16
 8001404:	46bd      	mov	sp, r7
 8001406:	bd80      	pop	{r7, pc}
 8001408:	08008340 	.word	0x08008340

0800140c <DataErase_Func>:
    __set_MSP(*(__IO uint32_t*) APPLICATION_ADDRESS);
    jump_to_app();
}
bool EraseInit = false;

void DataErase_Func(uint32_t User_Address,uint32_t size){
 800140c:	b580      	push	{r7, lr}
 800140e:	b082      	sub	sp, #8
 8001410:	af00      	add	r7, sp, #0
 8001412:	6078      	str	r0, [r7, #4]
 8001414:	6039      	str	r1, [r7, #0]
    static FLASH_EraseInitTypeDef EraseInitStruct;
    static uint32_t PAGEError = 0;

    HAL_FLASH_Unlock();
 8001416:	f001 fad9 	bl	80029cc <HAL_FLASH_Unlock>

    EraseInitStruct.TypeErase   = FLASH_TYPEERASE_PAGES;
 800141a:	4b1b      	ldr	r3, [pc, #108]	; (8001488 <DataErase_Func+0x7c>)
 800141c:	2200      	movs	r2, #0
 800141e:	601a      	str	r2, [r3, #0]
    EraseInitStruct.PageAddress = FLASH_USER_USE_START_ADDR;
 8001420:	4b19      	ldr	r3, [pc, #100]	; (8001488 <DataErase_Func+0x7c>)
 8001422:	4a1a      	ldr	r2, [pc, #104]	; (800148c <DataErase_Func+0x80>)
 8001424:	609a      	str	r2, [r3, #8]
    EraseInitStruct.NbPages     = ((FLASH_USER_END_ADDR - FLASH_USER_USE_START_ADDR) / FLASH_PAGE_SIZE) + 1;
 8001426:	4b18      	ldr	r3, [pc, #96]	; (8001488 <DataErase_Func+0x7c>)
 8001428:	2201      	movs	r2, #1
 800142a:	60da      	str	r2, [r3, #12]
    UserAddress = User_Address;
 800142c:	4a18      	ldr	r2, [pc, #96]	; (8001490 <DataErase_Func+0x84>)
 800142e:	687b      	ldr	r3, [r7, #4]
 8001430:	6013      	str	r3, [r2, #0]
    printf("NbPages : %x \r\n",EraseInitStruct.NbPages );
 8001432:	4b15      	ldr	r3, [pc, #84]	; (8001488 <DataErase_Func+0x7c>)
 8001434:	68db      	ldr	r3, [r3, #12]
 8001436:	4619      	mov	r1, r3
 8001438:	4816      	ldr	r0, [pc, #88]	; (8001494 <DataErase_Func+0x88>)
 800143a:	f004 ff3f 	bl	80062bc <iprintf>
    printf("EraseInitStruct.PageAddress : %x \r\n",EraseInitStruct.PageAddress);
 800143e:	4b12      	ldr	r3, [pc, #72]	; (8001488 <DataErase_Func+0x7c>)
 8001440:	689b      	ldr	r3, [r3, #8]
 8001442:	4619      	mov	r1, r3
 8001444:	4814      	ldr	r0, [pc, #80]	; (8001498 <DataErase_Func+0x8c>)
 8001446:	f004 ff39 	bl	80062bc <iprintf>

    printf("Erase Start\r\n");
 800144a:	4814      	ldr	r0, [pc, #80]	; (800149c <DataErase_Func+0x90>)
 800144c:	f004 ffaa 	bl	80063a4 <puts>
    if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK)
 8001450:	4913      	ldr	r1, [pc, #76]	; (80014a0 <DataErase_Func+0x94>)
 8001452:	480d      	ldr	r0, [pc, #52]	; (8001488 <DataErase_Func+0x7c>)
 8001454:	f001 fba2 	bl	8002b9c <HAL_FLASHEx_Erase>
 8001458:	4603      	mov	r3, r0
 800145a:	2b00      	cmp	r3, #0
 800145c:	d007      	beq.n	800146e <DataErase_Func+0x62>
      */
      /* Infinite loop */
      while (1)
      {
        /* Make LED2 blink (100ms on, 2s off) to indicate error in Erase operation */
        printf("HAL_FLASHEx_Erase Error\r\n");
 800145e:	4811      	ldr	r0, [pc, #68]	; (80014a4 <DataErase_Func+0x98>)
 8001460:	f004 ffa0 	bl	80063a4 <puts>
        HAL_Delay(2000);
 8001464:	f44f 60fa 	mov.w	r0, #2000	; 0x7d0
 8001468:	f000 f9fa 	bl	8001860 <HAL_Delay>
        printf("HAL_FLASHEx_Erase Error\r\n");
 800146c:	e7f7      	b.n	800145e <DataErase_Func+0x52>
      }
    }
    EraseInit = true;
 800146e:	4b0e      	ldr	r3, [pc, #56]	; (80014a8 <DataErase_Func+0x9c>)
 8001470:	2201      	movs	r2, #1
 8001472:	701a      	strb	r2, [r3, #0]
    printf("Erase End\r\n");
 8001474:	480d      	ldr	r0, [pc, #52]	; (80014ac <DataErase_Func+0xa0>)
 8001476:	f004 ff95 	bl	80063a4 <puts>
     HAL_FLASH_Lock();
 800147a:	f001 facd 	bl	8002a18 <HAL_FLASH_Lock>

}
 800147e:	bf00      	nop
 8001480:	3708      	adds	r7, #8
 8001482:	46bd      	mov	sp, r7
 8001484:	bd80      	pop	{r7, pc}
 8001486:	bf00      	nop
 8001488:	20000398 	.word	0x20000398
 800148c:	0800ff38 	.word	0x0800ff38
 8001490:	20000390 	.word	0x20000390
 8001494:	08008380 	.word	0x08008380
 8001498:	08008390 	.word	0x08008390
 800149c:	080083b4 	.word	0x080083b4
 80014a0:	200003a8 	.word	0x200003a8
 80014a4:	080083c4 	.word	0x080083c4
 80014a8:	20000394 	.word	0x20000394
 80014ac:	080083e0 	.word	0x080083e0

080014b0 <FLASH_Write_Func>:

uint8_t FLASH_Write_Func(uint8_t* data,uint32_t size){
 80014b0:	b590      	push	{r4, r7, lr}
 80014b2:	b089      	sub	sp, #36	; 0x24
 80014b4:	af00      	add	r7, sp, #0
 80014b6:	6078      	str	r0, [r7, #4]
 80014b8:	6039      	str	r1, [r7, #0]
    //static FLASH_EraseInitTypeDef EraseInitStruct;
    //static uint32_t PAGEError = 0;
    static uint32_t DownloadIndex;
    static __IO uint32_t data32 = 0 , MemoryProgramStatus = 0;
    int dataindex = 0;
 80014ba:	2300      	movs	r3, #0
 80014bc:	61bb      	str	r3, [r7, #24]
    uint32_t writedata = 0;
 80014be:	2300      	movs	r3, #0
 80014c0:	617b      	str	r3, [r7, #20]
    uint32_t  CurrApiAddress = 0;
 80014c2:	2300      	movs	r3, #0
 80014c4:	613b      	str	r3, [r7, #16]
    uint8_t ret = 0;
 80014c6:	2300      	movs	r3, #0
 80014c8:	73fb      	strb	r3, [r7, #15]
    CurrApiAddress = FLASH_USER_USE_START_ADDR;
 80014ca:	4b35      	ldr	r3, [pc, #212]	; (80015a0 <FLASH_Write_Func+0xf0>)
 80014cc:	613b      	str	r3, [r7, #16]

    uint8_t* Currdata = (uint8_t*)CurrApiAddress;
 80014ce:	693b      	ldr	r3, [r7, #16]
 80014d0:	60bb      	str	r3, [r7, #8]
    printf("HAL_FLASH_Program Start\r\n");
 80014d2:	4834      	ldr	r0, [pc, #208]	; (80015a4 <FLASH_Write_Func+0xf4>)
 80014d4:	f004 ff66 	bl	80063a4 <puts>
    DownloadIndex += size;
 80014d8:	4b33      	ldr	r3, [pc, #204]	; (80015a8 <FLASH_Write_Func+0xf8>)
 80014da:	681a      	ldr	r2, [r3, #0]
 80014dc:	683b      	ldr	r3, [r7, #0]
 80014de:	4413      	add	r3, r2
 80014e0:	4a31      	ldr	r2, [pc, #196]	; (80015a8 <FLASH_Write_Func+0xf8>)
 80014e2:	6013      	str	r3, [r2, #0]
    printf("User_Address : %x \r\n",UserAddress);
 80014e4:	4b31      	ldr	r3, [pc, #196]	; (80015ac <FLASH_Write_Func+0xfc>)
 80014e6:	681b      	ldr	r3, [r3, #0]
 80014e8:	4619      	mov	r1, r3
 80014ea:	4831      	ldr	r0, [pc, #196]	; (80015b0 <FLASH_Write_Func+0x100>)
 80014ec:	f004 fee6 	bl	80062bc <iprintf>


     HAL_FLASH_Unlock();
 80014f0:	f001 fa6c 	bl	80029cc <HAL_FLASH_Unlock>
     for(int downindex = 0; downindex < size; downindex+=4)
 80014f4:	2300      	movs	r3, #0
 80014f6:	61fb      	str	r3, [r7, #28]
 80014f8:	e041      	b.n	800157e <FLASH_Write_Func+0xce>
     {
       writedata = data[downindex + 0] ;
 80014fa:	69fb      	ldr	r3, [r7, #28]
 80014fc:	687a      	ldr	r2, [r7, #4]
 80014fe:	4413      	add	r3, r2
 8001500:	781b      	ldrb	r3, [r3, #0]
 8001502:	617b      	str	r3, [r7, #20]
       writedata += data[downindex + 1] << 8 ;
 8001504:	69fb      	ldr	r3, [r7, #28]
 8001506:	3301      	adds	r3, #1
 8001508:	687a      	ldr	r2, [r7, #4]
 800150a:	4413      	add	r3, r2
 800150c:	781b      	ldrb	r3, [r3, #0]
 800150e:	021b      	lsls	r3, r3, #8
 8001510:	461a      	mov	r2, r3
 8001512:	697b      	ldr	r3, [r7, #20]
 8001514:	4413      	add	r3, r2
 8001516:	617b      	str	r3, [r7, #20]
       writedata += data[downindex + 2] << 16;
 8001518:	69fb      	ldr	r3, [r7, #28]
 800151a:	3302      	adds	r3, #2
 800151c:	687a      	ldr	r2, [r7, #4]
 800151e:	4413      	add	r3, r2
 8001520:	781b      	ldrb	r3, [r3, #0]
 8001522:	041b      	lsls	r3, r3, #16
 8001524:	461a      	mov	r2, r3
 8001526:	697b      	ldr	r3, [r7, #20]
 8001528:	4413      	add	r3, r2
 800152a:	617b      	str	r3, [r7, #20]
       writedata += data[downindex + 3] << 24;      
 800152c:	69fb      	ldr	r3, [r7, #28]
 800152e:	3303      	adds	r3, #3
 8001530:	687a      	ldr	r2, [r7, #4]
 8001532:	4413      	add	r3, r2
 8001534:	781b      	ldrb	r3, [r3, #0]
 8001536:	061b      	lsls	r3, r3, #24
 8001538:	461a      	mov	r2, r3
 800153a:	697b      	ldr	r3, [r7, #20]
 800153c:	4413      	add	r3, r2
 800153e:	617b      	str	r3, [r7, #20]
       if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, UserAddress,writedata) == HAL_OK)
 8001540:	4b1a      	ldr	r3, [pc, #104]	; (80015ac <FLASH_Write_Func+0xfc>)
 8001542:	6819      	ldr	r1, [r3, #0]
 8001544:	697b      	ldr	r3, [r7, #20]
 8001546:	f04f 0400 	mov.w	r4, #0
 800154a:	461a      	mov	r2, r3
 800154c:	4623      	mov	r3, r4
 800154e:	2002      	movs	r0, #2
 8001550:	f001 f9cc 	bl	80028ec <HAL_FLASH_Program>
 8001554:	4603      	mov	r3, r0
 8001556:	2b00      	cmp	r3, #0
 8001558:	d105      	bne.n	8001566 <FLASH_Write_Func+0xb6>
       {
         UserAddress +=  4;
 800155a:	4b14      	ldr	r3, [pc, #80]	; (80015ac <FLASH_Write_Func+0xfc>)
 800155c:	681b      	ldr	r3, [r3, #0]
 800155e:	3304      	adds	r3, #4
 8001560:	4a12      	ldr	r2, [pc, #72]	; (80015ac <FLASH_Write_Func+0xfc>)
 8001562:	6013      	str	r3, [r2, #0]
 8001564:	e008      	b.n	8001578 <FLASH_Write_Func+0xc8>
       }
       else
       {
           printf("HAL_FLASH_Program Error\r\n");
 8001566:	4813      	ldr	r0, [pc, #76]	; (80015b4 <FLASH_Write_Func+0x104>)
 8001568:	f004 ff1c 	bl	80063a4 <puts>
           printf("Flash Failed %x \r\n",UserAddress);
 800156c:	4b0f      	ldr	r3, [pc, #60]	; (80015ac <FLASH_Write_Func+0xfc>)
 800156e:	681b      	ldr	r3, [r3, #0]
 8001570:	4619      	mov	r1, r3
 8001572:	4811      	ldr	r0, [pc, #68]	; (80015b8 <FLASH_Write_Func+0x108>)
 8001574:	f004 fea2 	bl	80062bc <iprintf>
     for(int downindex = 0; downindex < size; downindex+=4)
 8001578:	69fb      	ldr	r3, [r7, #28]
 800157a:	3304      	adds	r3, #4
 800157c:	61fb      	str	r3, [r7, #28]
 800157e:	69fb      	ldr	r3, [r7, #28]
 8001580:	683a      	ldr	r2, [r7, #0]
 8001582:	429a      	cmp	r2, r3
 8001584:	d8b9      	bhi.n	80014fa <FLASH_Write_Func+0x4a>
       }
     }

     printf("HAL_FLASH_Program END   %x \r\n",UserAddress);
 8001586:	4b09      	ldr	r3, [pc, #36]	; (80015ac <FLASH_Write_Func+0xfc>)
 8001588:	681b      	ldr	r3, [r3, #0]
 800158a:	4619      	mov	r1, r3
 800158c:	480b      	ldr	r0, [pc, #44]	; (80015bc <FLASH_Write_Func+0x10c>)
 800158e:	f004 fe95 	bl	80062bc <iprintf>
    /* Lock the Flash to disable the flash control register access (recommended
       to protect the FLASH memory against possible unwanted operation) *********/
    HAL_FLASH_Lock();
 8001592:	f001 fa41 	bl	8002a18 <HAL_FLASH_Lock>
    return 0;
 8001596:	2300      	movs	r3, #0
    /* Check if the programmed data is OK
        MemoryProgramStatus = 0: data programmed correctly
        MemoryProgramStatus != 0: number of words not programmed correctly ******/
}
 8001598:	4618      	mov	r0, r3
 800159a:	3724      	adds	r7, #36	; 0x24
 800159c:	46bd      	mov	sp, r7
 800159e:	bd90      	pop	{r4, r7, pc}
 80015a0:	0800ff38 	.word	0x0800ff38
 80015a4:	080083ec 	.word	0x080083ec
 80015a8:	200003ac 	.word	0x200003ac
 80015ac:	20000390 	.word	0x20000390
 80015b0:	08008408 	.word	0x08008408
 80015b4:	08008420 	.word	0x08008420
 80015b8:	0800843c 	.word	0x0800843c
 80015bc:	08008450 	.word	0x08008450

080015c0 <InitUartQueue>:
extern bool Bluecell_Operate(uint8_t* data);
extern void MBIC_Operate(uint8_t * data);
extern bool NessLab_CheckSum_Check(uint8_t* data,uint8_t size,uint8_t checksum);

void InitUartQueue(pUARTQUEUE pQueue)
{
 80015c0:	b580      	push	{r7, lr}
 80015c2:	b082      	sub	sp, #8
 80015c4:	af00      	add	r7, sp, #0
 80015c6:	6078      	str	r0, [r7, #4]
  pQueue->data = pQueue->head = pQueue->tail = 0;
 80015c8:	687b      	ldr	r3, [r7, #4]
 80015ca:	2200      	movs	r2, #0
 80015cc:	605a      	str	r2, [r3, #4]
 80015ce:	687b      	ldr	r3, [r7, #4]
 80015d0:	685a      	ldr	r2, [r3, #4]
 80015d2:	687b      	ldr	r3, [r7, #4]
 80015d4:	601a      	str	r2, [r3, #0]
 80015d6:	687b      	ldr	r3, [r7, #4]
 80015d8:	681a      	ldr	r2, [r3, #0]
 80015da:	687b      	ldr	r3, [r7, #4]
 80015dc:	609a      	str	r2, [r3, #8]
  uart_hal_tx.output_p = uart_hal_tx.input_p = 0;
 80015de:	2100      	movs	r1, #0
 80015e0:	4b08      	ldr	r3, [pc, #32]	; (8001604 <InitUartQueue+0x44>)
 80015e2:	460a      	mov	r2, r1
 80015e4:	f8a3 2080 	strh.w	r2, [r3, #128]	; 0x80
 80015e8:	4b06      	ldr	r3, [pc, #24]	; (8001604 <InitUartQueue+0x44>)
 80015ea:	460a      	mov	r2, r1
 80015ec:	f8a3 2082 	strh.w	r2, [r3, #130]	; 0x82
//  HAL_UART_Receive_IT(&huart2,rxBuf,5);



  if (HAL_UART_Receive_DMA(&hMain, MainQueue.Buffer, 1) != HAL_OK)
 80015f0:	2201      	movs	r2, #1
 80015f2:	4905      	ldr	r1, [pc, #20]	; (8001608 <InitUartQueue+0x48>)
 80015f4:	4805      	ldr	r0, [pc, #20]	; (800160c <InitUartQueue+0x4c>)
 80015f6:	f002 fdf7 	bl	80041e8 <HAL_UART_Receive_DMA>
//  {
////    _Error_Handler(__FILE__, __LINE__);
//  }
  //HAL_UART_Receive_DMA(&hTerminal,  TerminalQueue.Buffer, 1);
  //HAL_UART_Receive_IT(hTerminal, pQueue->Buffer + pQueue->head, 1);
}
 80015fa:	bf00      	nop
 80015fc:	3708      	adds	r7, #8
 80015fe:	46bd      	mov	sp, r7
 8001600:	bd80      	pop	{r7, pc}
 8001602:	bf00      	nop
 8001604:	200005b4 	.word	0x200005b4
 8001608:	200004a8 	.word	0x200004a8
 800160c:	200007e0 	.word	0x200007e0

08001610 <HAL_UART_RxCpltCallback>:

void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
{
 8001610:	b580      	push	{r7, lr}
 8001612:	b084      	sub	sp, #16
 8001614:	af00      	add	r7, sp, #0
 8001616:	6078      	str	r0, [r7, #4]
//    UART_HandleTypeDef *dst = (huart->Instance == USART2 ? &hTest:&hTerminal);
    pUARTQUEUE pQueue;
   // printf("Function : %s : \r\n",__func__);
    //printf("%02x ",uart_buf[i]);
    UartRxTimerCnt = 0;
 8001618:	4b15      	ldr	r3, [pc, #84]	; (8001670 <HAL_UART_RxCpltCallback+0x60>)
 800161a:	2200      	movs	r2, #0
 800161c:	601a      	str	r2, [r3, #0]
    pQueue = &MainQueue;
 800161e:	4b15      	ldr	r3, [pc, #84]	; (8001674 <HAL_UART_RxCpltCallback+0x64>)
 8001620:	60fb      	str	r3, [r7, #12]
    pQueue->head++;
 8001622:	68fb      	ldr	r3, [r7, #12]
 8001624:	681b      	ldr	r3, [r3, #0]
 8001626:	1c5a      	adds	r2, r3, #1
 8001628:	68fb      	ldr	r3, [r7, #12]
 800162a:	601a      	str	r2, [r3, #0]
    if (pQueue->head >= QUEUE_BUFFER_LENGTH) pQueue->head = 0;
 800162c:	68fb      	ldr	r3, [r7, #12]
 800162e:	681b      	ldr	r3, [r3, #0]
 8001630:	2b7f      	cmp	r3, #127	; 0x7f
 8001632:	dd02      	ble.n	800163a <HAL_UART_RxCpltCallback+0x2a>
 8001634:	68fb      	ldr	r3, [r7, #12]
 8001636:	2200      	movs	r2, #0
 8001638:	601a      	str	r2, [r3, #0]
    pQueue->data++;
 800163a:	68fb      	ldr	r3, [r7, #12]
 800163c:	689b      	ldr	r3, [r3, #8]
 800163e:	1c5a      	adds	r2, r3, #1
 8001640:	68fb      	ldr	r3, [r7, #12]
 8001642:	609a      	str	r2, [r3, #8]
    if (pQueue->data >= QUEUE_BUFFER_LENGTH)
 8001644:	68fb      	ldr	r3, [r7, #12]
 8001646:	689b      	ldr	r3, [r3, #8]
 8001648:	2b7f      	cmp	r3, #127	; 0x7f
 800164a:	dd02      	ble.n	8001652 <HAL_UART_RxCpltCallback+0x42>
        GetDataFromUartQueue(huart);
 800164c:	6878      	ldr	r0, [r7, #4]
 800164e:	f000 f815 	bl	800167c <GetDataFromUartQueue>
    HAL_UART_Receive_IT(&hMain, pQueue->Buffer + pQueue->head, 1);
 8001652:	68fb      	ldr	r3, [r7, #12]
 8001654:	330c      	adds	r3, #12
 8001656:	68fa      	ldr	r2, [r7, #12]
 8001658:	6812      	ldr	r2, [r2, #0]
 800165a:	4413      	add	r3, r2
 800165c:	2201      	movs	r2, #1
 800165e:	4619      	mov	r1, r3
 8001660:	4805      	ldr	r0, [pc, #20]	; (8001678 <HAL_UART_RxCpltCallback+0x68>)
 8001662:	f002 fd01 	bl	8004068 <HAL_UART_Receive_IT>
//    HAL_UART_Receive_DMA(&hTest, pQueue->Buffer + pQueue->head, 1);
   // Set_UartRcv(true);
}
 8001666:	bf00      	nop
 8001668:	3710      	adds	r7, #16
 800166a:	46bd      	mov	sp, r7
 800166c:	bd80      	pop	{r7, pc}
 800166e:	bf00      	nop
 8001670:	200003b8 	.word	0x200003b8
 8001674:	2000049c 	.word	0x2000049c
 8001678:	200007e0 	.word	0x200007e0

0800167c <GetDataFromUartQueue>:
   // HAL_UART_Receive_DMA(&hTerminal,  pQueue->Buffer + pQueue->head, 10);
}


void GetDataFromUartQueue(UART_HandleTypeDef *huart)
{
 800167c:	b580      	push	{r7, lr}
 800167e:	b086      	sub	sp, #24
 8001680:	af00      	add	r7, sp, #0
 8001682:	6078      	str	r0, [r7, #4]
    volatile static int cnt;
    bool ret = 0;
 8001684:	2300      	movs	r3, #0
 8001686:	74fb      	strb	r3, [r7, #19]
 /*   bool chksumret = 0;
    uint16_t Length = 0;
    uint16_t CrcChk = 0;
    UART_HandleTypeDef *dst = (huart->Instance == USART2 ? &hTest:&hTerminal);*/
//    UART_HandleTypeDef *dst = &hTerminal;
    pUARTQUEUE pQueue = &MainQueue;
 8001688:	4b3d      	ldr	r3, [pc, #244]	; (8001780 <GetDataFromUartQueue+0x104>)
 800168a:	60fb      	str	r3, [r7, #12]
//    if (HAL_UART_Transmit(dst, pQueue->Buffer + pQueue->tail, 1, 3000) != HAL_OK)
//    {
//       _Error_Handler(__FILE__, __LINE__);
//    }
    uart_buf[cnt++] = *(pQueue->Buffer + pQueue->tail); 
 800168c:	68fb      	ldr	r3, [r7, #12]
 800168e:	330c      	adds	r3, #12
 8001690:	68fa      	ldr	r2, [r7, #12]
 8001692:	6852      	ldr	r2, [r2, #4]
 8001694:	441a      	add	r2, r3
 8001696:	4b3b      	ldr	r3, [pc, #236]	; (8001784 <GetDataFromUartQueue+0x108>)
 8001698:	681b      	ldr	r3, [r3, #0]
 800169a:	1c59      	adds	r1, r3, #1
 800169c:	4839      	ldr	r0, [pc, #228]	; (8001784 <GetDataFromUartQueue+0x108>)
 800169e:	6001      	str	r1, [r0, #0]
 80016a0:	7811      	ldrb	r1, [r2, #0]
 80016a2:	4a39      	ldr	r2, [pc, #228]	; (8001788 <GetDataFromUartQueue+0x10c>)
 80016a4:	54d1      	strb	r1, [r2, r3]
//#ifdef DEBUG_PRINT
//    printf("%02x ",*(pQueue->Buffer + pQueue->tail)) ;
//#endif /* DEBUG_PRINT */

    pQueue->tail++;
 80016a6:	68fb      	ldr	r3, [r7, #12]
 80016a8:	685b      	ldr	r3, [r3, #4]
 80016aa:	1c5a      	adds	r2, r3, #1
 80016ac:	68fb      	ldr	r3, [r7, #12]
 80016ae:	605a      	str	r2, [r3, #4]
    if (pQueue->tail >= QUEUE_BUFFER_LENGTH) pQueue->tail = 0;
 80016b0:	68fb      	ldr	r3, [r7, #12]
 80016b2:	685b      	ldr	r3, [r3, #4]
 80016b4:	2b7f      	cmp	r3, #127	; 0x7f
 80016b6:	dd02      	ble.n	80016be <GetDataFromUartQueue+0x42>
 80016b8:	68fb      	ldr	r3, [r7, #12]
 80016ba:	2200      	movs	r2, #0
 80016bc:	605a      	str	r2, [r3, #4]
    pQueue->data--;
 80016be:	68fb      	ldr	r3, [r7, #12]
 80016c0:	689b      	ldr	r3, [r3, #8]
 80016c2:	1e5a      	subs	r2, r3, #1
 80016c4:	68fb      	ldr	r3, [r7, #12]
 80016c6:	609a      	str	r2, [r3, #8]
    
    if(pQueue->data == 0){
 80016c8:	68fb      	ldr	r3, [r7, #12]
 80016ca:	689b      	ldr	r3, [r3, #8]
 80016cc:	2b00      	cmp	r3, #0
 80016ce:	d152      	bne.n	8001776 <GetDataFromUartQueue+0xfa>

//        printf("data cnt zero !!!  \r\n");
        //RF_Ctrl_Main(&uart_buf[Header]);
//        HAL_UART_Transmit(dst, &temp_buf[BLUECELL_HEADER00], 11, 3000);
#if 1// PYJ.2019.07.15_BEGIN --
            printf("\r\n[RX]");
 80016d0:	482e      	ldr	r0, [pc, #184]	; (800178c <GetDataFromUartQueue+0x110>)
 80016d2:	f004 fdf3 	bl	80062bc <iprintf>
            for(int i = 0; i < cnt; i++){
 80016d6:	2300      	movs	r3, #0
 80016d8:	617b      	str	r3, [r7, #20]
 80016da:	e00b      	b.n	80016f4 <GetDataFromUartQueue+0x78>
                printf("%02x ",uart_buf[i]);
 80016dc:	4a2a      	ldr	r2, [pc, #168]	; (8001788 <GetDataFromUartQueue+0x10c>)
 80016de:	697b      	ldr	r3, [r7, #20]
 80016e0:	4413      	add	r3, r2
 80016e2:	781b      	ldrb	r3, [r3, #0]
 80016e4:	b2db      	uxtb	r3, r3
 80016e6:	4619      	mov	r1, r3
 80016e8:	4829      	ldr	r0, [pc, #164]	; (8001790 <GetDataFromUartQueue+0x114>)
 80016ea:	f004 fde7 	bl	80062bc <iprintf>
            for(int i = 0; i < cnt; i++){
 80016ee:	697b      	ldr	r3, [r7, #20]
 80016f0:	3301      	adds	r3, #1
 80016f2:	617b      	str	r3, [r7, #20]
 80016f4:	4b23      	ldr	r3, [pc, #140]	; (8001784 <GetDataFromUartQueue+0x108>)
 80016f6:	681b      	ldr	r3, [r3, #0]
 80016f8:	697a      	ldr	r2, [r7, #20]
 80016fa:	429a      	cmp	r2, r3
 80016fc:	dbee      	blt.n	80016dc <GetDataFromUartQueue+0x60>
            }
//            printf("Checksum Index : %d   %x\r\n",uart_buf[NessLab_Req_DataLength] + NessLab_Req_DataLength + 1,uart_buf[uart_buf[NessLab_Req_DataLength] + NessLab_Req_DataLength + 1]);
//            printf(ANSI_COLOR_GREEN"\r\n CNT : %d \r\n"ANSI_COLOR_RESET,cnt);
#endif // PYJ.2019.07.15_END --
        ret = NessLab_CheckSum_Check(&uart_buf[NessLab_Req_MsgID0],uart_buf[NessLab_DataLength] + 5 ,uart_buf[uart_buf[NessLab_Req_DataLength] + NessLab_Req_DataLength + 1]);
 80016fe:	4b22      	ldr	r3, [pc, #136]	; (8001788 <GetDataFromUartQueue+0x10c>)
 8001700:	799b      	ldrb	r3, [r3, #6]
 8001702:	b2db      	uxtb	r3, r3
 8001704:	3305      	adds	r3, #5
 8001706:	b2d9      	uxtb	r1, r3
 8001708:	4b1f      	ldr	r3, [pc, #124]	; (8001788 <GetDataFromUartQueue+0x10c>)
 800170a:	799b      	ldrb	r3, [r3, #6]
 800170c:	b2db      	uxtb	r3, r3
 800170e:	3307      	adds	r3, #7
 8001710:	4a1d      	ldr	r2, [pc, #116]	; (8001788 <GetDataFromUartQueue+0x10c>)
 8001712:	5cd3      	ldrb	r3, [r2, r3]
 8001714:	b2db      	uxtb	r3, r3
 8001716:	461a      	mov	r2, r3
 8001718:	481e      	ldr	r0, [pc, #120]	; (8001794 <GetDataFromUartQueue+0x118>)
 800171a:	f7ff fe41 	bl	80013a0 <NessLab_CheckSum_Check>
 800171e:	4603      	mov	r3, r0
 8001720:	74fb      	strb	r3, [r7, #19]
        if(ret == true){
 8001722:	7cfb      	ldrb	r3, [r7, #19]
 8001724:	2b00      	cmp	r3, #0
 8001726:	d006      	beq.n	8001736 <GetDataFromUartQueue+0xba>
			NessLab_Operate(&uart_buf[0]);
 8001728:	4817      	ldr	r0, [pc, #92]	; (8001788 <GetDataFromUartQueue+0x10c>)
 800172a:	f7ff fbcd 	bl	8000ec8 <NessLab_Operate>
            printf("Checksum OK \r\n");
 800172e:	481a      	ldr	r0, [pc, #104]	; (8001798 <GetDataFromUartQueue+0x11c>)
 8001730:	f004 fe38 	bl	80063a4 <puts>
 8001734:	e01c      	b.n	8001770 <GetDataFromUartQueue+0xf4>
        }else{
            printf("Checksum Error \r\n");
 8001736:	4819      	ldr	r0, [pc, #100]	; (800179c <GetDataFromUartQueue+0x120>)
 8001738:	f004 fe34 	bl	80063a4 <puts>
            printf("uart_buf[NessLab_Req_DataLength] : %x \r\n",uart_buf[NessLab_Req_DataLength]);
 800173c:	4b12      	ldr	r3, [pc, #72]	; (8001788 <GetDataFromUartQueue+0x10c>)
 800173e:	799b      	ldrb	r3, [r3, #6]
 8001740:	b2db      	uxtb	r3, r3
 8001742:	4619      	mov	r1, r3
 8001744:	4816      	ldr	r0, [pc, #88]	; (80017a0 <GetDataFromUartQueue+0x124>)
 8001746:	f004 fdb9 	bl	80062bc <iprintf>
            printf("NessLab_Req_DataLength : %d \r\n",NessLab_Req_DataLength);
 800174a:	2106      	movs	r1, #6
 800174c:	4815      	ldr	r0, [pc, #84]	; (80017a4 <GetDataFromUartQueue+0x128>)
 800174e:	f004 fdb5 	bl	80062bc <iprintf>
            printf("Checksum Index : %d   %x\r\n",uart_buf[NessLab_Req_DataLength] + NessLab_Req_DataLength + 1,uart_buf[uart_buf[NessLab_Req_DataLength] + NessLab_Req_DataLength + 1]);            
 8001752:	4b0d      	ldr	r3, [pc, #52]	; (8001788 <GetDataFromUartQueue+0x10c>)
 8001754:	799b      	ldrb	r3, [r3, #6]
 8001756:	b2db      	uxtb	r3, r3
 8001758:	1dd9      	adds	r1, r3, #7
 800175a:	4b0b      	ldr	r3, [pc, #44]	; (8001788 <GetDataFromUartQueue+0x10c>)
 800175c:	799b      	ldrb	r3, [r3, #6]
 800175e:	b2db      	uxtb	r3, r3
 8001760:	3307      	adds	r3, #7
 8001762:	4a09      	ldr	r2, [pc, #36]	; (8001788 <GetDataFromUartQueue+0x10c>)
 8001764:	5cd3      	ldrb	r3, [r2, r3]
 8001766:	b2db      	uxtb	r3, r3
 8001768:	461a      	mov	r2, r3
 800176a:	480f      	ldr	r0, [pc, #60]	; (80017a8 <GetDataFromUartQueue+0x12c>)
 800176c:	f004 fda6 	bl	80062bc <iprintf>
        }
		cnt = 0;
 8001770:	4b04      	ldr	r3, [pc, #16]	; (8001784 <GetDataFromUartQueue+0x108>)
 8001772:	2200      	movs	r2, #0
 8001774:	601a      	str	r2, [r3, #0]
    }
}
 8001776:	bf00      	nop
 8001778:	3718      	adds	r7, #24
 800177a:	46bd      	mov	sp, r7
 800177c:	bd80      	pop	{r7, pc}
 800177e:	bf00      	nop
 8001780:	2000049c 	.word	0x2000049c
 8001784:	200003b4 	.word	0x200003b4
 8001788:	2000041c 	.word	0x2000041c
 800178c:	08008488 	.word	0x08008488
 8001790:	08008490 	.word	0x08008490
 8001794:	2000041e 	.word	0x2000041e
 8001798:	08008498 	.word	0x08008498
 800179c:	080084a8 	.word	0x080084a8
 80017a0:	080084bc 	.word	0x080084bc
 80017a4:	080084e8 	.word	0x080084e8
 80017a8:	08008508 	.word	0x08008508

080017ac <Uart1_Data_Send>:
void Uart_Check(void){
  while (MainQueue.data > 0 && UartRxTimerCnt > 50) GetDataFromUartQueue(&hMain);
}


void Uart1_Data_Send(uint8_t* data,uint16_t size){
 80017ac:	b580      	push	{r7, lr}
 80017ae:	b084      	sub	sp, #16
 80017b0:	af00      	add	r7, sp, #0
 80017b2:	6078      	str	r0, [r7, #4]
 80017b4:	460b      	mov	r3, r1
 80017b6:	807b      	strh	r3, [r7, #2]

      HAL_UART_Transmit_DMA(&hMain, &data[0],size);
 80017b8:	887b      	ldrh	r3, [r7, #2]
 80017ba:	461a      	mov	r2, r3
 80017bc:	6879      	ldr	r1, [r7, #4]
 80017be:	480f      	ldr	r0, [pc, #60]	; (80017fc <Uart1_Data_Send+0x50>)
 80017c0:	f002 fca6 	bl	8004110 <HAL_UART_Transmit_DMA>
  //HAL_UART_Transmit_IT(&hTerminal, &data[0],size);
//    printf("data[278] : %x \r\n",data[278]);
////    HAL_Delay(1);   
#if 1 // PYJ.2020.07.19_BEGIN -- 
    printf("\r\n [TX] : ");
 80017c4:	480e      	ldr	r0, [pc, #56]	; (8001800 <Uart1_Data_Send+0x54>)
 80017c6:	f004 fd79 	bl	80062bc <iprintf>
    for(int i = 0; i< size; i++)
 80017ca:	2300      	movs	r3, #0
 80017cc:	60fb      	str	r3, [r7, #12]
 80017ce:	e00a      	b.n	80017e6 <Uart1_Data_Send+0x3a>
        printf("%02x ",data[i]);
 80017d0:	68fb      	ldr	r3, [r7, #12]
 80017d2:	687a      	ldr	r2, [r7, #4]
 80017d4:	4413      	add	r3, r2
 80017d6:	781b      	ldrb	r3, [r3, #0]
 80017d8:	4619      	mov	r1, r3
 80017da:	480a      	ldr	r0, [pc, #40]	; (8001804 <Uart1_Data_Send+0x58>)
 80017dc:	f004 fd6e 	bl	80062bc <iprintf>
    for(int i = 0; i< size; i++)
 80017e0:	68fb      	ldr	r3, [r7, #12]
 80017e2:	3301      	adds	r3, #1
 80017e4:	60fb      	str	r3, [r7, #12]
 80017e6:	887b      	ldrh	r3, [r7, #2]
 80017e8:	68fa      	ldr	r2, [r7, #12]
 80017ea:	429a      	cmp	r2, r3
 80017ec:	dbf0      	blt.n	80017d0 <Uart1_Data_Send+0x24>
//    printf("};\r\n\tCOUNT : %d \r\n",size);
    printf("\r\n");
 80017ee:	4806      	ldr	r0, [pc, #24]	; (8001808 <Uart1_Data_Send+0x5c>)
 80017f0:	f004 fdd8 	bl	80063a4 <puts>
//        data[i] = 0;
//    }
//    printf("};\r\n\tCOUNT : %d \r\n",size);
//    printf("\r\n");
    
}
 80017f4:	bf00      	nop
 80017f6:	3710      	adds	r7, #16
 80017f8:	46bd      	mov	sp, r7
 80017fa:	bd80      	pop	{r7, pc}
 80017fc:	200007e0 	.word	0x200007e0
 8001800:	08008524 	.word	0x08008524
 8001804:	08008490 	.word	0x08008490
 8001808:	08008530 	.word	0x08008530

0800180c <HAL_Init>:
  *         need to ensure that the SysTick time base is always set to 1 millisecond
  *         to have correct HAL operation.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_Init(void)
{
 800180c:	b580      	push	{r7, lr}
 800180e:	af00      	add	r7, sp, #0
  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif
#endif /* PREFETCH_ENABLE */

  /* Set Interrupt Group Priority */
  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
 8001810:	2003      	movs	r0, #3
 8001812:	f000 fdd1 	bl	80023b8 <HAL_NVIC_SetPriorityGrouping>

  /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
  HAL_InitTick(TICK_INT_PRIORITY);
 8001816:	2000      	movs	r0, #0
 8001818:	f003 ff18 	bl	800564c <HAL_InitTick>

  /* Init the low level hardware */
  HAL_MspInit();
 800181c:	f003 fd2e 	bl	800527c <HAL_MspInit>

  /* Return function status */
  return HAL_OK;
 8001820:	2300      	movs	r3, #0
}
 8001822:	4618      	mov	r0, r3
 8001824:	bd80      	pop	{r7, pc}
	...

08001828 <HAL_IncTick>:
  * @note This function is declared as __weak to be overwritten in case of other
  *      implementations in user file.
  * @retval None
  */
__weak void HAL_IncTick(void)
{
 8001828:	b480      	push	{r7}
 800182a:	af00      	add	r7, sp, #0
  uwTick += uwTickFreq;
 800182c:	4b05      	ldr	r3, [pc, #20]	; (8001844 <HAL_IncTick+0x1c>)
 800182e:	781b      	ldrb	r3, [r3, #0]
 8001830:	461a      	mov	r2, r3
 8001832:	4b05      	ldr	r3, [pc, #20]	; (8001848 <HAL_IncTick+0x20>)
 8001834:	681b      	ldr	r3, [r3, #0]
 8001836:	4413      	add	r3, r2
 8001838:	4a03      	ldr	r2, [pc, #12]	; (8001848 <HAL_IncTick+0x20>)
 800183a:	6013      	str	r3, [r2, #0]
}
 800183c:	bf00      	nop
 800183e:	46bd      	mov	sp, r7
 8001840:	bc80      	pop	{r7}
 8001842:	4770      	bx	lr
 8001844:	20000004 	.word	0x20000004
 8001848:	20000638 	.word	0x20000638

0800184c <HAL_GetTick>:
  * @note  This function is declared as __weak to be overwritten in case of other
  *       implementations in user file.
  * @retval tick value
  */
__weak uint32_t HAL_GetTick(void)
{
 800184c:	b480      	push	{r7}
 800184e:	af00      	add	r7, sp, #0
  return uwTick;
 8001850:	4b02      	ldr	r3, [pc, #8]	; (800185c <HAL_GetTick+0x10>)
 8001852:	681b      	ldr	r3, [r3, #0]
}
 8001854:	4618      	mov	r0, r3
 8001856:	46bd      	mov	sp, r7
 8001858:	bc80      	pop	{r7}
 800185a:	4770      	bx	lr
 800185c:	20000638 	.word	0x20000638

08001860 <HAL_Delay>:
  *       implementations in user file.
  * @param Delay specifies the delay time length, in milliseconds.
  * @retval None
  */
__weak void HAL_Delay(uint32_t Delay)
{
 8001860:	b580      	push	{r7, lr}
 8001862:	b084      	sub	sp, #16
 8001864:	af00      	add	r7, sp, #0
 8001866:	6078      	str	r0, [r7, #4]
  uint32_t tickstart = HAL_GetTick();
 8001868:	f7ff fff0 	bl	800184c <HAL_GetTick>
 800186c:	60b8      	str	r0, [r7, #8]
  uint32_t wait = Delay;
 800186e:	687b      	ldr	r3, [r7, #4]
 8001870:	60fb      	str	r3, [r7, #12]

  /* Add a freq to guarantee minimum wait */
  if (wait < HAL_MAX_DELAY)
 8001872:	68fb      	ldr	r3, [r7, #12]
 8001874:	f1b3 3fff 	cmp.w	r3, #4294967295
 8001878:	d005      	beq.n	8001886 <HAL_Delay+0x26>
  {
    wait += (uint32_t)(uwTickFreq);
 800187a:	4b09      	ldr	r3, [pc, #36]	; (80018a0 <HAL_Delay+0x40>)
 800187c:	781b      	ldrb	r3, [r3, #0]
 800187e:	461a      	mov	r2, r3
 8001880:	68fb      	ldr	r3, [r7, #12]
 8001882:	4413      	add	r3, r2
 8001884:	60fb      	str	r3, [r7, #12]
  }

  while ((HAL_GetTick() - tickstart) < wait)
 8001886:	bf00      	nop
 8001888:	f7ff ffe0 	bl	800184c <HAL_GetTick>
 800188c:	4602      	mov	r2, r0
 800188e:	68bb      	ldr	r3, [r7, #8]
 8001890:	1ad3      	subs	r3, r2, r3
 8001892:	68fa      	ldr	r2, [r7, #12]
 8001894:	429a      	cmp	r2, r3
 8001896:	d8f7      	bhi.n	8001888 <HAL_Delay+0x28>
  {
  }
}
 8001898:	bf00      	nop
 800189a:	3710      	adds	r7, #16
 800189c:	46bd      	mov	sp, r7
 800189e:	bd80      	pop	{r7, pc}
 80018a0:	20000004 	.word	0x20000004

080018a4 <HAL_ADC_Init>:
  *         of structure "ADC_InitTypeDef".
  * @param  hadc: ADC handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
{
 80018a4:	b580      	push	{r7, lr}
 80018a6:	b086      	sub	sp, #24
 80018a8:	af00      	add	r7, sp, #0
 80018aa:	6078      	str	r0, [r7, #4]
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
 80018ac:	2300      	movs	r3, #0
 80018ae:	75fb      	strb	r3, [r7, #23]
  uint32_t tmp_cr1 = 0U;
 80018b0:	2300      	movs	r3, #0
 80018b2:	613b      	str	r3, [r7, #16]
  uint32_t tmp_cr2 = 0U;
 80018b4:	2300      	movs	r3, #0
 80018b6:	60bb      	str	r3, [r7, #8]
  uint32_t tmp_sqr1 = 0U;
 80018b8:	2300      	movs	r3, #0
 80018ba:	60fb      	str	r3, [r7, #12]
  
  /* Check ADC handle */
  if(hadc == NULL)
 80018bc:	687b      	ldr	r3, [r7, #4]
 80018be:	2b00      	cmp	r3, #0
 80018c0:	d101      	bne.n	80018c6 <HAL_ADC_Init+0x22>
  {
    return HAL_ERROR;
 80018c2:	2301      	movs	r3, #1
 80018c4:	e0be      	b.n	8001a44 <HAL_ADC_Init+0x1a0>
  assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
  assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
  assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
  
  if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
 80018c6:	687b      	ldr	r3, [r7, #4]
 80018c8:	689b      	ldr	r3, [r3, #8]
 80018ca:	2b00      	cmp	r3, #0
  /* Refer to header of this file for more details on clock enabling          */
  /* procedure.                                                               */

  /* Actions performed only if ADC is coming from state reset:                */
  /* - Initialization of ADC MSP                                              */
  if (hadc->State == HAL_ADC_STATE_RESET)
 80018cc:	687b      	ldr	r3, [r7, #4]
 80018ce:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 80018d0:	2b00      	cmp	r3, #0
 80018d2:	d109      	bne.n	80018e8 <HAL_ADC_Init+0x44>
  {
    /* Initialize ADC error code */
    ADC_CLEAR_ERRORCODE(hadc);
 80018d4:	687b      	ldr	r3, [r7, #4]
 80018d6:	2200      	movs	r2, #0
 80018d8:	62da      	str	r2, [r3, #44]	; 0x2c
    
    /* Allocate lock resource and initialize it */
    hadc->Lock = HAL_UNLOCKED;
 80018da:	687b      	ldr	r3, [r7, #4]
 80018dc:	2200      	movs	r2, #0
 80018de:	f883 2024 	strb.w	r2, [r3, #36]	; 0x24
    
    /* Init the low level hardware */
    hadc->MspInitCallback(hadc);
#else
    /* Init the low level hardware */
    HAL_ADC_MspInit(hadc);
 80018e2:	6878      	ldr	r0, [r7, #4]
 80018e4:	f003 fcfc 	bl	80052e0 <HAL_ADC_MspInit>
  /* Stop potential conversion on going, on regular and injected groups */
  /* Disable ADC peripheral */
  /* Note: In case of ADC already enabled, precaution to not launch an        */
  /*       unwanted conversion while modifying register CR2 by writing 1 to   */
  /*       bit ADON.                                                          */
  tmp_hal_status = ADC_ConversionStop_Disable(hadc);
 80018e8:	6878      	ldr	r0, [r7, #4]
 80018ea:	f000 fb75 	bl	8001fd8 <ADC_ConversionStop_Disable>
 80018ee:	4603      	mov	r3, r0
 80018f0:	75fb      	strb	r3, [r7, #23]
  
  
  /* Configuration of ADC parameters if previous preliminary actions are      */ 
  /* correctly completed.                                                     */
  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
 80018f2:	687b      	ldr	r3, [r7, #4]
 80018f4:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 80018f6:	f003 0310 	and.w	r3, r3, #16
 80018fa:	2b00      	cmp	r3, #0
 80018fc:	f040 8099 	bne.w	8001a32 <HAL_ADC_Init+0x18e>
 8001900:	7dfb      	ldrb	r3, [r7, #23]
 8001902:	2b00      	cmp	r3, #0
 8001904:	f040 8095 	bne.w	8001a32 <HAL_ADC_Init+0x18e>
      (tmp_hal_status == HAL_OK)                                  )
  {
    /* Set ADC state */
    ADC_STATE_CLR_SET(hadc->State,
 8001908:	687b      	ldr	r3, [r7, #4]
 800190a:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 800190c:	f423 5388 	bic.w	r3, r3, #4352	; 0x1100
 8001910:	f023 0302 	bic.w	r3, r3, #2
 8001914:	f043 0202 	orr.w	r2, r3, #2
 8001918:	687b      	ldr	r3, [r7, #4]
 800191a:	629a      	str	r2, [r3, #40]	; 0x28
    /*  - continuous conversion mode                                          */
    /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into          */
    /*       HAL_ADC_Start_xxx functions because if set in this function,     */
    /*       a conversion on injected group would start a conversion also on  */
    /*       regular group after ADC enabling.                                */
    tmp_cr2 |= (hadc->Init.DataAlign                                          |
 800191c:	687b      	ldr	r3, [r7, #4]
 800191e:	685a      	ldr	r2, [r3, #4]
                ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv)            |
 8001920:	687b      	ldr	r3, [r7, #4]
 8001922:	69db      	ldr	r3, [r3, #28]
    tmp_cr2 |= (hadc->Init.DataAlign                                          |
 8001924:	431a      	orrs	r2, r3
                ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode)   );
 8001926:	687b      	ldr	r3, [r7, #4]
 8001928:	7b1b      	ldrb	r3, [r3, #12]
 800192a:	005b      	lsls	r3, r3, #1
                ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv)            |
 800192c:	4313      	orrs	r3, r2
    tmp_cr2 |= (hadc->Init.DataAlign                                          |
 800192e:	68ba      	ldr	r2, [r7, #8]
 8001930:	4313      	orrs	r3, r2
 8001932:	60bb      	str	r3, [r7, #8]

    /* Configuration of ADC:                                                  */
    /*  - scan mode                                                           */
    /*  - discontinuous mode disable/enable                                   */
    /*  - discontinuous mode number of conversions                            */
    tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode));
 8001934:	687b      	ldr	r3, [r7, #4]
 8001936:	689b      	ldr	r3, [r3, #8]
 8001938:	f5b3 7f80 	cmp.w	r3, #256	; 0x100
 800193c:	d003      	beq.n	8001946 <HAL_ADC_Init+0xa2>
 800193e:	687b      	ldr	r3, [r7, #4]
 8001940:	689b      	ldr	r3, [r3, #8]
 8001942:	2b01      	cmp	r3, #1
 8001944:	d102      	bne.n	800194c <HAL_ADC_Init+0xa8>
 8001946:	f44f 7380 	mov.w	r3, #256	; 0x100
 800194a:	e000      	b.n	800194e <HAL_ADC_Init+0xaa>
 800194c:	2300      	movs	r3, #0
 800194e:	693a      	ldr	r2, [r7, #16]
 8001950:	4313      	orrs	r3, r2
 8001952:	613b      	str	r3, [r7, #16]
    
    /* Enable discontinuous mode only if continuous mode is disabled */
    /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter    */
    /*       discontinuous is set anyway, but will have no effect on ADC HW.  */
    if (hadc->Init.DiscontinuousConvMode == ENABLE)
 8001954:	687b      	ldr	r3, [r7, #4]
 8001956:	7d1b      	ldrb	r3, [r3, #20]
 8001958:	2b01      	cmp	r3, #1
 800195a:	d119      	bne.n	8001990 <HAL_ADC_Init+0xec>
    {
      if (hadc->Init.ContinuousConvMode == DISABLE)
 800195c:	687b      	ldr	r3, [r7, #4]
 800195e:	7b1b      	ldrb	r3, [r3, #12]
 8001960:	2b00      	cmp	r3, #0
 8001962:	d109      	bne.n	8001978 <HAL_ADC_Init+0xd4>
      {
        /* Enable the selected ADC regular discontinuous mode */
        /* Set the number of channels to be converted in discontinuous mode */
        SET_BIT(tmp_cr1, ADC_CR1_DISCEN                                            |
 8001964:	687b      	ldr	r3, [r7, #4]
 8001966:	699b      	ldr	r3, [r3, #24]
 8001968:	3b01      	subs	r3, #1
 800196a:	035a      	lsls	r2, r3, #13
 800196c:	693b      	ldr	r3, [r7, #16]
 800196e:	4313      	orrs	r3, r2
 8001970:	f443 6300 	orr.w	r3, r3, #2048	; 0x800
 8001974:	613b      	str	r3, [r7, #16]
 8001976:	e00b      	b.n	8001990 <HAL_ADC_Init+0xec>
      {
        /* ADC regular group settings continuous and sequencer discontinuous*/
        /* cannot be enabled simultaneously.                                */
        
        /* Update ADC state machine to error */
        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
 8001978:	687b      	ldr	r3, [r7, #4]
 800197a:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 800197c:	f043 0220 	orr.w	r2, r3, #32
 8001980:	687b      	ldr	r3, [r7, #4]
 8001982:	629a      	str	r2, [r3, #40]	; 0x28
        
        /* Set ADC error code to ADC IP internal error */
        SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
 8001984:	687b      	ldr	r3, [r7, #4]
 8001986:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 8001988:	f043 0201 	orr.w	r2, r3, #1
 800198c:	687b      	ldr	r3, [r7, #4]
 800198e:	62da      	str	r2, [r3, #44]	; 0x2c
      }
    }
    
    /* Update ADC configuration register CR1 with previous settings */
      MODIFY_REG(hadc->Instance->CR1,
 8001990:	687b      	ldr	r3, [r7, #4]
 8001992:	681b      	ldr	r3, [r3, #0]
 8001994:	685b      	ldr	r3, [r3, #4]
 8001996:	f423 4169 	bic.w	r1, r3, #59648	; 0xe900
 800199a:	687b      	ldr	r3, [r7, #4]
 800199c:	681b      	ldr	r3, [r3, #0]
 800199e:	693a      	ldr	r2, [r7, #16]
 80019a0:	430a      	orrs	r2, r1
 80019a2:	605a      	str	r2, [r3, #4]
                 ADC_CR1_DISCEN  |
                 ADC_CR1_DISCNUM    ,
                 tmp_cr1             );
    
    /* Update ADC configuration register CR2 with previous settings */
      MODIFY_REG(hadc->Instance->CR2,
 80019a4:	687b      	ldr	r3, [r7, #4]
 80019a6:	681b      	ldr	r3, [r3, #0]
 80019a8:	689a      	ldr	r2, [r3, #8]
 80019aa:	4b28      	ldr	r3, [pc, #160]	; (8001a4c <HAL_ADC_Init+0x1a8>)
 80019ac:	4013      	ands	r3, r2
 80019ae:	687a      	ldr	r2, [r7, #4]
 80019b0:	6812      	ldr	r2, [r2, #0]
 80019b2:	68b9      	ldr	r1, [r7, #8]
 80019b4:	430b      	orrs	r3, r1
 80019b6:	6093      	str	r3, [r2, #8]
    /*   Note: Scan mode is present by hardware on this device and, if        */
    /*   disabled, discards automatically nb of conversions. Anyway, nb of    */
    /*   conversions is forced to 0x00 for alignment over all STM32 devices.  */
    /* - if scan mode is enabled, regular channels sequence length is set to  */
    /*   parameter "NbrOfConversion"                                          */
    if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE)
 80019b8:	687b      	ldr	r3, [r7, #4]
 80019ba:	689b      	ldr	r3, [r3, #8]
 80019bc:	f5b3 7f80 	cmp.w	r3, #256	; 0x100
 80019c0:	d003      	beq.n	80019ca <HAL_ADC_Init+0x126>
 80019c2:	687b      	ldr	r3, [r7, #4]
 80019c4:	689b      	ldr	r3, [r3, #8]
 80019c6:	2b01      	cmp	r3, #1
 80019c8:	d104      	bne.n	80019d4 <HAL_ADC_Init+0x130>
    {
      tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion);
 80019ca:	687b      	ldr	r3, [r7, #4]
 80019cc:	691b      	ldr	r3, [r3, #16]
 80019ce:	3b01      	subs	r3, #1
 80019d0:	051b      	lsls	r3, r3, #20
 80019d2:	60fb      	str	r3, [r7, #12]
    }
      
    MODIFY_REG(hadc->Instance->SQR1,
 80019d4:	687b      	ldr	r3, [r7, #4]
 80019d6:	681b      	ldr	r3, [r3, #0]
 80019d8:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 80019da:	f423 0170 	bic.w	r1, r3, #15728640	; 0xf00000
 80019de:	687b      	ldr	r3, [r7, #4]
 80019e0:	681b      	ldr	r3, [r3, #0]
 80019e2:	68fa      	ldr	r2, [r7, #12]
 80019e4:	430a      	orrs	r2, r1
 80019e6:	62da      	str	r2, [r3, #44]	; 0x2c
    /* ensure of no potential problem of ADC core IP clocking.                */
    /* Check through register CR2 (excluding bits set in other functions:     */
    /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits   */
    /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal    */
    /* measurement path bit (TSVREFE).                                        */
    if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
 80019e8:	687b      	ldr	r3, [r7, #4]
 80019ea:	681b      	ldr	r3, [r3, #0]
 80019ec:	689a      	ldr	r2, [r3, #8]
 80019ee:	4b18      	ldr	r3, [pc, #96]	; (8001a50 <HAL_ADC_Init+0x1ac>)
 80019f0:	4013      	ands	r3, r2
 80019f2:	68ba      	ldr	r2, [r7, #8]
 80019f4:	429a      	cmp	r2, r3
 80019f6:	d10b      	bne.n	8001a10 <HAL_ADC_Init+0x16c>
                                        ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL |
                                        ADC_CR2_TSVREFE                     ))
         == tmp_cr2)
    {
      /* Set ADC error code to none */
      ADC_CLEAR_ERRORCODE(hadc);
 80019f8:	687b      	ldr	r3, [r7, #4]
 80019fa:	2200      	movs	r2, #0
 80019fc:	62da      	str	r2, [r3, #44]	; 0x2c
      
      /* Set the ADC state */
      ADC_STATE_CLR_SET(hadc->State,
 80019fe:	687b      	ldr	r3, [r7, #4]
 8001a00:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 8001a02:	f023 0303 	bic.w	r3, r3, #3
 8001a06:	f043 0201 	orr.w	r2, r3, #1
 8001a0a:	687b      	ldr	r3, [r7, #4]
 8001a0c:	629a      	str	r2, [r3, #40]	; 0x28
    if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
 8001a0e:	e018      	b.n	8001a42 <HAL_ADC_Init+0x19e>
                        HAL_ADC_STATE_READY);
    }
    else
    {
      /* Update ADC state machine to error */
      ADC_STATE_CLR_SET(hadc->State,
 8001a10:	687b      	ldr	r3, [r7, #4]
 8001a12:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 8001a14:	f023 0312 	bic.w	r3, r3, #18
 8001a18:	f043 0210 	orr.w	r2, r3, #16
 8001a1c:	687b      	ldr	r3, [r7, #4]
 8001a1e:	629a      	str	r2, [r3, #40]	; 0x28
                        HAL_ADC_STATE_BUSY_INTERNAL,
                        HAL_ADC_STATE_ERROR_INTERNAL);
      
      /* Set ADC error code to ADC IP internal error */
      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
 8001a20:	687b      	ldr	r3, [r7, #4]
 8001a22:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 8001a24:	f043 0201 	orr.w	r2, r3, #1
 8001a28:	687b      	ldr	r3, [r7, #4]
 8001a2a:	62da      	str	r2, [r3, #44]	; 0x2c
      
      tmp_hal_status = HAL_ERROR;
 8001a2c:	2301      	movs	r3, #1
 8001a2e:	75fb      	strb	r3, [r7, #23]
    if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
 8001a30:	e007      	b.n	8001a42 <HAL_ADC_Init+0x19e>
  
  }
  else
  {
    /* Update ADC state machine to error */
    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
 8001a32:	687b      	ldr	r3, [r7, #4]
 8001a34:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 8001a36:	f043 0210 	orr.w	r2, r3, #16
 8001a3a:	687b      	ldr	r3, [r7, #4]
 8001a3c:	629a      	str	r2, [r3, #40]	; 0x28
        
    tmp_hal_status = HAL_ERROR;
 8001a3e:	2301      	movs	r3, #1
 8001a40:	75fb      	strb	r3, [r7, #23]
  }
  
  /* Return function status */
  return tmp_hal_status;
 8001a42:	7dfb      	ldrb	r3, [r7, #23]
}
 8001a44:	4618      	mov	r0, r3
 8001a46:	3718      	adds	r7, #24
 8001a48:	46bd      	mov	sp, r7
 8001a4a:	bd80      	pop	{r7, pc}
 8001a4c:	ffe1f7fd 	.word	0xffe1f7fd
 8001a50:	ff1f0efe 	.word	0xff1f0efe

08001a54 <HAL_ADC_Start_DMA>:
  * @param  pData: The destination Buffer address.
  * @param  Length: The length of data to be transferred from ADC peripheral to memory.
  * @retval None
  */
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
{
 8001a54:	b580      	push	{r7, lr}
 8001a56:	b086      	sub	sp, #24
 8001a58:	af00      	add	r7, sp, #0
 8001a5a:	60f8      	str	r0, [r7, #12]
 8001a5c:	60b9      	str	r1, [r7, #8]
 8001a5e:	607a      	str	r2, [r7, #4]
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
 8001a60:	2300      	movs	r3, #0
 8001a62:	75fb      	strb	r3, [r7, #23]
  /* If multimode is enabled, dedicated function multimode conversion         */
  /* start DMA must be used.                                                  */
  if(ADC_MULTIMODE_IS_ENABLE(hadc) == RESET)
  {
    /* Process locked */
    __HAL_LOCK(hadc);
 8001a64:	68fb      	ldr	r3, [r7, #12]
 8001a66:	f893 3024 	ldrb.w	r3, [r3, #36]	; 0x24
 8001a6a:	2b01      	cmp	r3, #1
 8001a6c:	d101      	bne.n	8001a72 <HAL_ADC_Start_DMA+0x1e>
 8001a6e:	2302      	movs	r3, #2
 8001a70:	e080      	b.n	8001b74 <HAL_ADC_Start_DMA+0x120>
 8001a72:	68fb      	ldr	r3, [r7, #12]
 8001a74:	2201      	movs	r2, #1
 8001a76:	f883 2024 	strb.w	r2, [r3, #36]	; 0x24
    
    /* Enable the ADC peripheral */
    tmp_hal_status = ADC_Enable(hadc);
 8001a7a:	68f8      	ldr	r0, [r7, #12]
 8001a7c:	f000 fa5a 	bl	8001f34 <ADC_Enable>
 8001a80:	4603      	mov	r3, r0
 8001a82:	75fb      	strb	r3, [r7, #23]
    
    /* Start conversion if ADC is effectively enabled */
    if (tmp_hal_status == HAL_OK)
 8001a84:	7dfb      	ldrb	r3, [r7, #23]
 8001a86:	2b00      	cmp	r3, #0
 8001a88:	d16f      	bne.n	8001b6a <HAL_ADC_Start_DMA+0x116>
    {
      /* Set ADC state                                                        */
      /* - Clear state bitfield related to regular group conversion results   */
      /* - Set state bitfield related to regular operation                    */
      ADC_STATE_CLR_SET(hadc->State,
 8001a8a:	68fb      	ldr	r3, [r7, #12]
 8001a8c:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 8001a8e:	f423 6370 	bic.w	r3, r3, #3840	; 0xf00
 8001a92:	f023 0301 	bic.w	r3, r3, #1
 8001a96:	f443 7280 	orr.w	r2, r3, #256	; 0x100
 8001a9a:	68fb      	ldr	r3, [r7, #12]
 8001a9c:	629a      	str	r2, [r3, #40]	; 0x28
    /* for all cases of multimode: independent mode, multimode ADC master     */
    /* or multimode ADC slave (for devices with several ADCs):                */
    if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
    {
      /* Set ADC state (ADC independent or master) */
      CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
 8001a9e:	68fb      	ldr	r3, [r7, #12]
 8001aa0:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 8001aa2:	f423 1280 	bic.w	r2, r3, #1048576	; 0x100000
 8001aa6:	68fb      	ldr	r3, [r7, #12]
 8001aa8:	629a      	str	r2, [r3, #40]	; 0x28
      
      /* If conversions on group regular are also triggering group injected,  */
      /* update ADC state.                                                    */
      if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
 8001aaa:	68fb      	ldr	r3, [r7, #12]
 8001aac:	681b      	ldr	r3, [r3, #0]
 8001aae:	685b      	ldr	r3, [r3, #4]
 8001ab0:	f403 6380 	and.w	r3, r3, #1024	; 0x400
 8001ab4:	2b00      	cmp	r3, #0
 8001ab6:	d007      	beq.n	8001ac8 <HAL_ADC_Start_DMA+0x74>
      {
        ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);  
 8001ab8:	68fb      	ldr	r3, [r7, #12]
 8001aba:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 8001abc:	f423 5340 	bic.w	r3, r3, #12288	; 0x3000
 8001ac0:	f443 5280 	orr.w	r2, r3, #4096	; 0x1000
 8001ac4:	68fb      	ldr	r3, [r7, #12]
 8001ac6:	629a      	str	r2, [r3, #40]	; 0x28
        ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
      }
    }
      
      /* State machine update: Check if an injected conversion is ongoing */
      if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
 8001ac8:	68fb      	ldr	r3, [r7, #12]
 8001aca:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 8001acc:	f403 5380 	and.w	r3, r3, #4096	; 0x1000
 8001ad0:	2b00      	cmp	r3, #0
 8001ad2:	d006      	beq.n	8001ae2 <HAL_ADC_Start_DMA+0x8e>
      {
        /* Reset ADC error code fields related to conversions on group regular */
        CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));         
 8001ad4:	68fb      	ldr	r3, [r7, #12]
 8001ad6:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 8001ad8:	f023 0206 	bic.w	r2, r3, #6
 8001adc:	68fb      	ldr	r3, [r7, #12]
 8001ade:	62da      	str	r2, [r3, #44]	; 0x2c
 8001ae0:	e002      	b.n	8001ae8 <HAL_ADC_Start_DMA+0x94>
      }
      else
      {
        /* Reset ADC all error code fields */
        ADC_CLEAR_ERRORCODE(hadc);
 8001ae2:	68fb      	ldr	r3, [r7, #12]
 8001ae4:	2200      	movs	r2, #0
 8001ae6:	62da      	str	r2, [r3, #44]	; 0x2c
      }
      
      /* Process unlocked */
      /* Unlock before starting ADC conversions: in case of potential         */
      /* interruption, to let the process to ADC IRQ Handler.                 */
      __HAL_UNLOCK(hadc);
 8001ae8:	68fb      	ldr	r3, [r7, #12]
 8001aea:	2200      	movs	r2, #0
 8001aec:	f883 2024 	strb.w	r2, [r3, #36]	; 0x24
      
      /* Set the DMA transfer complete callback */
      hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
 8001af0:	68fb      	ldr	r3, [r7, #12]
 8001af2:	6a1b      	ldr	r3, [r3, #32]
 8001af4:	4a21      	ldr	r2, [pc, #132]	; (8001b7c <HAL_ADC_Start_DMA+0x128>)
 8001af6:	629a      	str	r2, [r3, #40]	; 0x28

      /* Set the DMA half transfer complete callback */
      hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
 8001af8:	68fb      	ldr	r3, [r7, #12]
 8001afa:	6a1b      	ldr	r3, [r3, #32]
 8001afc:	4a20      	ldr	r2, [pc, #128]	; (8001b80 <HAL_ADC_Start_DMA+0x12c>)
 8001afe:	62da      	str	r2, [r3, #44]	; 0x2c
      
      /* Set the DMA error callback */
      hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
 8001b00:	68fb      	ldr	r3, [r7, #12]
 8001b02:	6a1b      	ldr	r3, [r3, #32]
 8001b04:	4a1f      	ldr	r2, [pc, #124]	; (8001b84 <HAL_ADC_Start_DMA+0x130>)
 8001b06:	631a      	str	r2, [r3, #48]	; 0x30
      /* start (in case of SW start):                                         */
      
      /* Clear regular group conversion flag and overrun flag */
      /* (To ensure of no unknown state from potential previous ADC           */
      /* operations)                                                          */
      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
 8001b08:	68fb      	ldr	r3, [r7, #12]
 8001b0a:	681b      	ldr	r3, [r3, #0]
 8001b0c:	f06f 0202 	mvn.w	r2, #2
 8001b10:	601a      	str	r2, [r3, #0]
      
      /* Enable ADC DMA mode */
      SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA);
 8001b12:	68fb      	ldr	r3, [r7, #12]
 8001b14:	681b      	ldr	r3, [r3, #0]
 8001b16:	689a      	ldr	r2, [r3, #8]
 8001b18:	68fb      	ldr	r3, [r7, #12]
 8001b1a:	681b      	ldr	r3, [r3, #0]
 8001b1c:	f442 7280 	orr.w	r2, r2, #256	; 0x100
 8001b20:	609a      	str	r2, [r3, #8]
      
      /* Start the DMA channel */
      HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
 8001b22:	68fb      	ldr	r3, [r7, #12]
 8001b24:	6a18      	ldr	r0, [r3, #32]
 8001b26:	68fb      	ldr	r3, [r7, #12]
 8001b28:	681b      	ldr	r3, [r3, #0]
 8001b2a:	334c      	adds	r3, #76	; 0x4c
 8001b2c:	4619      	mov	r1, r3
 8001b2e:	68ba      	ldr	r2, [r7, #8]
 8001b30:	687b      	ldr	r3, [r7, #4]
 8001b32:	f000 fcd1 	bl	80024d8 <HAL_DMA_Start_IT>
      
      /* Enable conversion of regular group.                                  */
      /* If software start has been selected, conversion starts immediately.  */
      /* If external trigger has been selected, conversion will start at next */
      /* trigger event.                                                       */
      if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
 8001b36:	68fb      	ldr	r3, [r7, #12]
 8001b38:	681b      	ldr	r3, [r3, #0]
 8001b3a:	689b      	ldr	r3, [r3, #8]
 8001b3c:	f403 2360 	and.w	r3, r3, #917504	; 0xe0000
 8001b40:	f5b3 2f60 	cmp.w	r3, #917504	; 0xe0000
 8001b44:	d108      	bne.n	8001b58 <HAL_ADC_Start_DMA+0x104>
      {
        /* Start ADC conversion on regular group with SW start */
        SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
 8001b46:	68fb      	ldr	r3, [r7, #12]
 8001b48:	681b      	ldr	r3, [r3, #0]
 8001b4a:	689a      	ldr	r2, [r3, #8]
 8001b4c:	68fb      	ldr	r3, [r7, #12]
 8001b4e:	681b      	ldr	r3, [r3, #0]
 8001b50:	f442 02a0 	orr.w	r2, r2, #5242880	; 0x500000
 8001b54:	609a      	str	r2, [r3, #8]
 8001b56:	e00c      	b.n	8001b72 <HAL_ADC_Start_DMA+0x11e>
      }
      else
      {
        /* Start ADC conversion on regular group with external trigger */
        SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
 8001b58:	68fb      	ldr	r3, [r7, #12]
 8001b5a:	681b      	ldr	r3, [r3, #0]
 8001b5c:	689a      	ldr	r2, [r3, #8]
 8001b5e:	68fb      	ldr	r3, [r7, #12]
 8001b60:	681b      	ldr	r3, [r3, #0]
 8001b62:	f442 1280 	orr.w	r2, r2, #1048576	; 0x100000
 8001b66:	609a      	str	r2, [r3, #8]
 8001b68:	e003      	b.n	8001b72 <HAL_ADC_Start_DMA+0x11e>
      }
    }
    else
    {
      /* Process unlocked */
      __HAL_UNLOCK(hadc);
 8001b6a:	68fb      	ldr	r3, [r7, #12]
 8001b6c:	2200      	movs	r2, #0
 8001b6e:	f883 2024 	strb.w	r2, [r3, #36]	; 0x24
  {
    tmp_hal_status = HAL_ERROR;
  }
  
  /* Return function status */
  return tmp_hal_status;
 8001b72:	7dfb      	ldrb	r3, [r7, #23]
}
 8001b74:	4618      	mov	r0, r3
 8001b76:	3718      	adds	r7, #24
 8001b78:	46bd      	mov	sp, r7
 8001b7a:	bd80      	pop	{r7, pc}
 8001b7c:	0800204d 	.word	0x0800204d
 8001b80:	080020c9 	.word	0x080020c9
 8001b84:	080020e5 	.word	0x080020e5

08001b88 <HAL_ADC_IRQHandler>:
  * @brief  Handles ADC interrupt request  
  * @param  hadc: ADC handle
  * @retval None
  */
void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
{
 8001b88:	b580      	push	{r7, lr}
 8001b8a:	b082      	sub	sp, #8
 8001b8c:	af00      	add	r7, sp, #0
 8001b8e:	6078      	str	r0, [r7, #4]
  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
  assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
  
  
  /* ========== Check End of Conversion flag for regular group ========== */
  if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC))
 8001b90:	687b      	ldr	r3, [r7, #4]
 8001b92:	681b      	ldr	r3, [r3, #0]
 8001b94:	685b      	ldr	r3, [r3, #4]
 8001b96:	f003 0320 	and.w	r3, r3, #32
 8001b9a:	2b20      	cmp	r3, #32
 8001b9c:	d140      	bne.n	8001c20 <HAL_ADC_IRQHandler+0x98>
  {
    if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) )
 8001b9e:	687b      	ldr	r3, [r7, #4]
 8001ba0:	681b      	ldr	r3, [r3, #0]
 8001ba2:	681b      	ldr	r3, [r3, #0]
 8001ba4:	f003 0302 	and.w	r3, r3, #2
 8001ba8:	2b02      	cmp	r3, #2
 8001baa:	d139      	bne.n	8001c20 <HAL_ADC_IRQHandler+0x98>
    {
      /* Update state machine on conversion status if not in error state */
      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
 8001bac:	687b      	ldr	r3, [r7, #4]
 8001bae:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 8001bb0:	f003 0310 	and.w	r3, r3, #16
 8001bb4:	2b00      	cmp	r3, #0
 8001bb6:	d105      	bne.n	8001bc4 <HAL_ADC_IRQHandler+0x3c>
      {
        /* Set ADC state */
        SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 
 8001bb8:	687b      	ldr	r3, [r7, #4]
 8001bba:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 8001bbc:	f443 7200 	orr.w	r2, r3, #512	; 0x200
 8001bc0:	687b      	ldr	r3, [r7, #4]
 8001bc2:	629a      	str	r2, [r3, #40]	; 0x28
      /* Determine whether any further conversion upcoming on group regular   */
      /* by external trigger, continuous mode or scan sequence on going.      */
      /* Note: On STM32F1 devices, in case of sequencer enabled               */
      /*       (several ranks selected), end of conversion flag is raised     */
      /*       at the end of the sequence.                                    */
      if(ADC_IS_SOFTWARE_START_REGULAR(hadc)        && 
 8001bc4:	687b      	ldr	r3, [r7, #4]
 8001bc6:	681b      	ldr	r3, [r3, #0]
 8001bc8:	689b      	ldr	r3, [r3, #8]
 8001bca:	f403 2360 	and.w	r3, r3, #917504	; 0xe0000
 8001bce:	f5b3 2f60 	cmp.w	r3, #917504	; 0xe0000
 8001bd2:	d11d      	bne.n	8001c10 <HAL_ADC_IRQHandler+0x88>
         (hadc->Init.ContinuousConvMode == DISABLE)   )
 8001bd4:	687b      	ldr	r3, [r7, #4]
 8001bd6:	7b1b      	ldrb	r3, [r3, #12]
      if(ADC_IS_SOFTWARE_START_REGULAR(hadc)        && 
 8001bd8:	2b00      	cmp	r3, #0
 8001bda:	d119      	bne.n	8001c10 <HAL_ADC_IRQHandler+0x88>
      {
        /* Disable ADC end of conversion interrupt on group regular */
        __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
 8001bdc:	687b      	ldr	r3, [r7, #4]
 8001bde:	681b      	ldr	r3, [r3, #0]
 8001be0:	685a      	ldr	r2, [r3, #4]
 8001be2:	687b      	ldr	r3, [r7, #4]
 8001be4:	681b      	ldr	r3, [r3, #0]
 8001be6:	f022 0220 	bic.w	r2, r2, #32
 8001bea:	605a      	str	r2, [r3, #4]
        
        /* Set ADC state */
        CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);   
 8001bec:	687b      	ldr	r3, [r7, #4]
 8001bee:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 8001bf0:	f423 7280 	bic.w	r2, r3, #256	; 0x100
 8001bf4:	687b      	ldr	r3, [r7, #4]
 8001bf6:	629a      	str	r2, [r3, #40]	; 0x28
        
        if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
 8001bf8:	687b      	ldr	r3, [r7, #4]
 8001bfa:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 8001bfc:	f403 5380 	and.w	r3, r3, #4096	; 0x1000
 8001c00:	2b00      	cmp	r3, #0
 8001c02:	d105      	bne.n	8001c10 <HAL_ADC_IRQHandler+0x88>
        {
          SET_BIT(hadc->State, HAL_ADC_STATE_READY);
 8001c04:	687b      	ldr	r3, [r7, #4]
 8001c06:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 8001c08:	f043 0201 	orr.w	r2, r3, #1
 8001c0c:	687b      	ldr	r3, [r7, #4]
 8001c0e:	629a      	str	r2, [r3, #40]	; 0x28

      /* Conversion complete callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
      hadc->ConvCpltCallback(hadc);
#else
      HAL_ADC_ConvCpltCallback(hadc);
 8001c10:	6878      	ldr	r0, [r7, #4]
 8001c12:	f7ff fb95 	bl	8001340 <HAL_ADC_ConvCpltCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
      
      /* Clear regular group conversion flag */
      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
 8001c16:	687b      	ldr	r3, [r7, #4]
 8001c18:	681b      	ldr	r3, [r3, #0]
 8001c1a:	f06f 0212 	mvn.w	r2, #18
 8001c1e:	601a      	str	r2, [r3, #0]
    }
  }
  
  /* ========== Check End of Conversion flag for injected group ========== */
  if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC))
 8001c20:	687b      	ldr	r3, [r7, #4]
 8001c22:	681b      	ldr	r3, [r3, #0]
 8001c24:	685b      	ldr	r3, [r3, #4]
 8001c26:	f003 0380 	and.w	r3, r3, #128	; 0x80
 8001c2a:	2b80      	cmp	r3, #128	; 0x80
 8001c2c:	d14f      	bne.n	8001cce <HAL_ADC_IRQHandler+0x146>
  {
    if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC))
 8001c2e:	687b      	ldr	r3, [r7, #4]
 8001c30:	681b      	ldr	r3, [r3, #0]
 8001c32:	681b      	ldr	r3, [r3, #0]
 8001c34:	f003 0304 	and.w	r3, r3, #4
 8001c38:	2b04      	cmp	r3, #4
 8001c3a:	d148      	bne.n	8001cce <HAL_ADC_IRQHandler+0x146>
    {
      /* Update state machine on conversion status if not in error state */
      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
 8001c3c:	687b      	ldr	r3, [r7, #4]
 8001c3e:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 8001c40:	f003 0310 	and.w	r3, r3, #16
 8001c44:	2b00      	cmp	r3, #0
 8001c46:	d105      	bne.n	8001c54 <HAL_ADC_IRQHandler+0xcc>
      {
        /* Set ADC state */
        SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
 8001c48:	687b      	ldr	r3, [r7, #4]
 8001c4a:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 8001c4c:	f443 5200 	orr.w	r2, r3, #8192	; 0x2000
 8001c50:	687b      	ldr	r3, [r7, #4]
 8001c52:	629a      	str	r2, [r3, #40]	; 0x28
      /* conversion from group regular (same conditions as group regular      */
      /* interruption disabling above).                                       */
      /* Note: On STM32F1 devices, in case of sequencer enabled               */
      /*       (several ranks selected), end of conversion flag is raised     */
      /*       at the end of the sequence.                                    */
      if(ADC_IS_SOFTWARE_START_INJECTED(hadc)                     || 
 8001c54:	687b      	ldr	r3, [r7, #4]
 8001c56:	681b      	ldr	r3, [r3, #0]
 8001c58:	689b      	ldr	r3, [r3, #8]
 8001c5a:	f403 43e0 	and.w	r3, r3, #28672	; 0x7000
 8001c5e:	f5b3 4fe0 	cmp.w	r3, #28672	; 0x7000
 8001c62:	d012      	beq.n	8001c8a <HAL_ADC_IRQHandler+0x102>
         (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&     
 8001c64:	687b      	ldr	r3, [r7, #4]
 8001c66:	681b      	ldr	r3, [r3, #0]
 8001c68:	685b      	ldr	r3, [r3, #4]
 8001c6a:	f403 6380 	and.w	r3, r3, #1024	; 0x400
      if(ADC_IS_SOFTWARE_START_INJECTED(hadc)                     || 
 8001c6e:	2b00      	cmp	r3, #0
 8001c70:	d125      	bne.n	8001cbe <HAL_ADC_IRQHandler+0x136>
         (ADC_IS_SOFTWARE_START_REGULAR(hadc)        &&
 8001c72:	687b      	ldr	r3, [r7, #4]
 8001c74:	681b      	ldr	r3, [r3, #0]
 8001c76:	689b      	ldr	r3, [r3, #8]
 8001c78:	f403 2360 	and.w	r3, r3, #917504	; 0xe0000
         (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&     
 8001c7c:	f5b3 2f60 	cmp.w	r3, #917504	; 0xe0000
 8001c80:	d11d      	bne.n	8001cbe <HAL_ADC_IRQHandler+0x136>
          (hadc->Init.ContinuousConvMode == DISABLE)   )        )   )
 8001c82:	687b      	ldr	r3, [r7, #4]
 8001c84:	7b1b      	ldrb	r3, [r3, #12]
         (ADC_IS_SOFTWARE_START_REGULAR(hadc)        &&
 8001c86:	2b00      	cmp	r3, #0
 8001c88:	d119      	bne.n	8001cbe <HAL_ADC_IRQHandler+0x136>
      {
        /* Disable ADC end of conversion interrupt on group injected */
        __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
 8001c8a:	687b      	ldr	r3, [r7, #4]
 8001c8c:	681b      	ldr	r3, [r3, #0]
 8001c8e:	685a      	ldr	r2, [r3, #4]
 8001c90:	687b      	ldr	r3, [r7, #4]
 8001c92:	681b      	ldr	r3, [r3, #0]
 8001c94:	f022 0280 	bic.w	r2, r2, #128	; 0x80
 8001c98:	605a      	str	r2, [r3, #4]
        
        /* Set ADC state */
        CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);   
 8001c9a:	687b      	ldr	r3, [r7, #4]
 8001c9c:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 8001c9e:	f423 5280 	bic.w	r2, r3, #4096	; 0x1000
 8001ca2:	687b      	ldr	r3, [r7, #4]
 8001ca4:	629a      	str	r2, [r3, #40]	; 0x28

        if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
 8001ca6:	687b      	ldr	r3, [r7, #4]
 8001ca8:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 8001caa:	f403 7380 	and.w	r3, r3, #256	; 0x100
 8001cae:	2b00      	cmp	r3, #0
 8001cb0:	d105      	bne.n	8001cbe <HAL_ADC_IRQHandler+0x136>
        { 
          SET_BIT(hadc->State, HAL_ADC_STATE_READY);
 8001cb2:	687b      	ldr	r3, [r7, #4]
 8001cb4:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 8001cb6:	f043 0201 	orr.w	r2, r3, #1
 8001cba:	687b      	ldr	r3, [r7, #4]
 8001cbc:	629a      	str	r2, [r3, #40]	; 0x28

      /* Conversion complete callback */ 
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
      hadc->InjectedConvCpltCallback(hadc);
#else
      HAL_ADCEx_InjectedConvCpltCallback(hadc);
 8001cbe:	6878      	ldr	r0, [r7, #4]
 8001cc0:	f000 fac6 	bl	8002250 <HAL_ADCEx_InjectedConvCpltCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
      
      /* Clear injected group conversion flag */
      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC));
 8001cc4:	687b      	ldr	r3, [r7, #4]
 8001cc6:	681b      	ldr	r3, [r3, #0]
 8001cc8:	f06f 020c 	mvn.w	r2, #12
 8001ccc:	601a      	str	r2, [r3, #0]
    }
  }
   
  /* ========== Check Analog watchdog flags ========== */
  if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD))
 8001cce:	687b      	ldr	r3, [r7, #4]
 8001cd0:	681b      	ldr	r3, [r3, #0]
 8001cd2:	685b      	ldr	r3, [r3, #4]
 8001cd4:	f003 0340 	and.w	r3, r3, #64	; 0x40
 8001cd8:	2b40      	cmp	r3, #64	; 0x40
 8001cda:	d114      	bne.n	8001d06 <HAL_ADC_IRQHandler+0x17e>
  {
    if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD))
 8001cdc:	687b      	ldr	r3, [r7, #4]
 8001cde:	681b      	ldr	r3, [r3, #0]
 8001ce0:	681b      	ldr	r3, [r3, #0]
 8001ce2:	f003 0301 	and.w	r3, r3, #1
 8001ce6:	2b01      	cmp	r3, #1
 8001ce8:	d10d      	bne.n	8001d06 <HAL_ADC_IRQHandler+0x17e>
    {
      /* Set ADC state */
      SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
 8001cea:	687b      	ldr	r3, [r7, #4]
 8001cec:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 8001cee:	f443 3280 	orr.w	r2, r3, #65536	; 0x10000
 8001cf2:	687b      	ldr	r3, [r7, #4]
 8001cf4:	629a      	str	r2, [r3, #40]	; 0x28
      
      /* Level out of window callback */ 
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
      hadc->LevelOutOfWindowCallback(hadc);
#else
      HAL_ADC_LevelOutOfWindowCallback(hadc);
 8001cf6:	6878      	ldr	r0, [r7, #4]
 8001cf8:	f000 f812 	bl	8001d20 <HAL_ADC_LevelOutOfWindowCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
      
      /* Clear the ADC analog watchdog flag */
      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
 8001cfc:	687b      	ldr	r3, [r7, #4]
 8001cfe:	681b      	ldr	r3, [r3, #0]
 8001d00:	f06f 0201 	mvn.w	r2, #1
 8001d04:	601a      	str	r2, [r3, #0]
    }
  }
  
}
 8001d06:	bf00      	nop
 8001d08:	3708      	adds	r7, #8
 8001d0a:	46bd      	mov	sp, r7
 8001d0c:	bd80      	pop	{r7, pc}

08001d0e <HAL_ADC_ConvHalfCpltCallback>:
  * @brief  Conversion DMA half-transfer callback in non blocking mode 
  * @param  hadc: ADC handle
  * @retval None
  */
__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
{
 8001d0e:	b480      	push	{r7}
 8001d10:	b083      	sub	sp, #12
 8001d12:	af00      	add	r7, sp, #0
 8001d14:	6078      	str	r0, [r7, #4]
  /* Prevent unused argument(s) compilation warning */
  UNUSED(hadc);
  /* NOTE : This function should not be modified. When the callback is needed,
            function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
  */
}
 8001d16:	bf00      	nop
 8001d18:	370c      	adds	r7, #12
 8001d1a:	46bd      	mov	sp, r7
 8001d1c:	bc80      	pop	{r7}
 8001d1e:	4770      	bx	lr

08001d20 <HAL_ADC_LevelOutOfWindowCallback>:
  * @brief  Analog watchdog callback in non blocking mode. 
  * @param  hadc: ADC handle
  * @retval None
  */
__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
{
 8001d20:	b480      	push	{r7}
 8001d22:	b083      	sub	sp, #12
 8001d24:	af00      	add	r7, sp, #0
 8001d26:	6078      	str	r0, [r7, #4]
  /* Prevent unused argument(s) compilation warning */
  UNUSED(hadc);
  /* NOTE : This function should not be modified. When the callback is needed,
            function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
  */
}
 8001d28:	bf00      	nop
 8001d2a:	370c      	adds	r7, #12
 8001d2c:	46bd      	mov	sp, r7
 8001d2e:	bc80      	pop	{r7}
 8001d30:	4770      	bx	lr

08001d32 <HAL_ADC_ErrorCallback>:
  *        (ADC conversion with interruption or transfer by DMA)
  * @param  hadc: ADC handle
  * @retval None
  */
__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
{
 8001d32:	b480      	push	{r7}
 8001d34:	b083      	sub	sp, #12
 8001d36:	af00      	add	r7, sp, #0
 8001d38:	6078      	str	r0, [r7, #4]
  /* Prevent unused argument(s) compilation warning */
  UNUSED(hadc);
  /* NOTE : This function should not be modified. When the callback is needed,
            function HAL_ADC_ErrorCallback must be implemented in the user file.
  */
}
 8001d3a:	bf00      	nop
 8001d3c:	370c      	adds	r7, #12
 8001d3e:	46bd      	mov	sp, r7
 8001d40:	bc80      	pop	{r7}
 8001d42:	4770      	bx	lr

08001d44 <HAL_ADC_ConfigChannel>:
  * @param  hadc: ADC handle
  * @param  sConfig: Structure of ADC channel for regular group.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
{ 
 8001d44:	b480      	push	{r7}
 8001d46:	b085      	sub	sp, #20
 8001d48:	af00      	add	r7, sp, #0
 8001d4a:	6078      	str	r0, [r7, #4]
 8001d4c:	6039      	str	r1, [r7, #0]
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
 8001d4e:	2300      	movs	r3, #0
 8001d50:	73fb      	strb	r3, [r7, #15]
  __IO uint32_t wait_loop_index = 0U;
 8001d52:	2300      	movs	r3, #0
 8001d54:	60bb      	str	r3, [r7, #8]
  assert_param(IS_ADC_CHANNEL(sConfig->Channel));
  assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
  assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
  
  /* Process locked */
  __HAL_LOCK(hadc);
 8001d56:	687b      	ldr	r3, [r7, #4]
 8001d58:	f893 3024 	ldrb.w	r3, [r3, #36]	; 0x24
 8001d5c:	2b01      	cmp	r3, #1
 8001d5e:	d101      	bne.n	8001d64 <HAL_ADC_ConfigChannel+0x20>
 8001d60:	2302      	movs	r3, #2
 8001d62:	e0dc      	b.n	8001f1e <HAL_ADC_ConfigChannel+0x1da>
 8001d64:	687b      	ldr	r3, [r7, #4]
 8001d66:	2201      	movs	r2, #1
 8001d68:	f883 2024 	strb.w	r2, [r3, #36]	; 0x24
  
  
  /* Regular sequence configuration */
  /* For Rank 1 to 6 */
  if (sConfig->Rank < 7U)
 8001d6c:	683b      	ldr	r3, [r7, #0]
 8001d6e:	685b      	ldr	r3, [r3, #4]
 8001d70:	2b06      	cmp	r3, #6
 8001d72:	d81c      	bhi.n	8001dae <HAL_ADC_ConfigChannel+0x6a>
  {
    MODIFY_REG(hadc->Instance->SQR3                        ,
 8001d74:	687b      	ldr	r3, [r7, #4]
 8001d76:	681b      	ldr	r3, [r3, #0]
 8001d78:	6b59      	ldr	r1, [r3, #52]	; 0x34
 8001d7a:	683b      	ldr	r3, [r7, #0]
 8001d7c:	685a      	ldr	r2, [r3, #4]
 8001d7e:	4613      	mov	r3, r2
 8001d80:	009b      	lsls	r3, r3, #2
 8001d82:	4413      	add	r3, r2
 8001d84:	3b05      	subs	r3, #5
 8001d86:	221f      	movs	r2, #31
 8001d88:	fa02 f303 	lsl.w	r3, r2, r3
 8001d8c:	43db      	mvns	r3, r3
 8001d8e:	4019      	ands	r1, r3
 8001d90:	683b      	ldr	r3, [r7, #0]
 8001d92:	6818      	ldr	r0, [r3, #0]
 8001d94:	683b      	ldr	r3, [r7, #0]
 8001d96:	685a      	ldr	r2, [r3, #4]
 8001d98:	4613      	mov	r3, r2
 8001d9a:	009b      	lsls	r3, r3, #2
 8001d9c:	4413      	add	r3, r2
 8001d9e:	3b05      	subs	r3, #5
 8001da0:	fa00 f203 	lsl.w	r2, r0, r3
 8001da4:	687b      	ldr	r3, [r7, #4]
 8001da6:	681b      	ldr	r3, [r3, #0]
 8001da8:	430a      	orrs	r2, r1
 8001daa:	635a      	str	r2, [r3, #52]	; 0x34
 8001dac:	e03c      	b.n	8001e28 <HAL_ADC_ConfigChannel+0xe4>
               ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank)    ,
               ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) );
  }
  /* For Rank 7 to 12 */
  else if (sConfig->Rank < 13U)
 8001dae:	683b      	ldr	r3, [r7, #0]
 8001db0:	685b      	ldr	r3, [r3, #4]
 8001db2:	2b0c      	cmp	r3, #12
 8001db4:	d81c      	bhi.n	8001df0 <HAL_ADC_ConfigChannel+0xac>
  {
    MODIFY_REG(hadc->Instance->SQR2                        ,
 8001db6:	687b      	ldr	r3, [r7, #4]
 8001db8:	681b      	ldr	r3, [r3, #0]
 8001dba:	6b19      	ldr	r1, [r3, #48]	; 0x30
 8001dbc:	683b      	ldr	r3, [r7, #0]
 8001dbe:	685a      	ldr	r2, [r3, #4]
 8001dc0:	4613      	mov	r3, r2
 8001dc2:	009b      	lsls	r3, r3, #2
 8001dc4:	4413      	add	r3, r2
 8001dc6:	3b23      	subs	r3, #35	; 0x23
 8001dc8:	221f      	movs	r2, #31
 8001dca:	fa02 f303 	lsl.w	r3, r2, r3
 8001dce:	43db      	mvns	r3, r3
 8001dd0:	4019      	ands	r1, r3
 8001dd2:	683b      	ldr	r3, [r7, #0]
 8001dd4:	6818      	ldr	r0, [r3, #0]
 8001dd6:	683b      	ldr	r3, [r7, #0]
 8001dd8:	685a      	ldr	r2, [r3, #4]
 8001dda:	4613      	mov	r3, r2
 8001ddc:	009b      	lsls	r3, r3, #2
 8001dde:	4413      	add	r3, r2
 8001de0:	3b23      	subs	r3, #35	; 0x23
 8001de2:	fa00 f203 	lsl.w	r2, r0, r3
 8001de6:	687b      	ldr	r3, [r7, #4]
 8001de8:	681b      	ldr	r3, [r3, #0]
 8001dea:	430a      	orrs	r2, r1
 8001dec:	631a      	str	r2, [r3, #48]	; 0x30
 8001dee:	e01b      	b.n	8001e28 <HAL_ADC_ConfigChannel+0xe4>
               ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) );
  }
  /* For Rank 13 to 16 */
  else
  {
    MODIFY_REG(hadc->Instance->SQR1                        ,
 8001df0:	687b      	ldr	r3, [r7, #4]
 8001df2:	681b      	ldr	r3, [r3, #0]
 8001df4:	6ad9      	ldr	r1, [r3, #44]	; 0x2c
 8001df6:	683b      	ldr	r3, [r7, #0]
 8001df8:	685a      	ldr	r2, [r3, #4]
 8001dfa:	4613      	mov	r3, r2
 8001dfc:	009b      	lsls	r3, r3, #2
 8001dfe:	4413      	add	r3, r2
 8001e00:	3b41      	subs	r3, #65	; 0x41
 8001e02:	221f      	movs	r2, #31
 8001e04:	fa02 f303 	lsl.w	r3, r2, r3
 8001e08:	43db      	mvns	r3, r3
 8001e0a:	4019      	ands	r1, r3
 8001e0c:	683b      	ldr	r3, [r7, #0]
 8001e0e:	6818      	ldr	r0, [r3, #0]
 8001e10:	683b      	ldr	r3, [r7, #0]
 8001e12:	685a      	ldr	r2, [r3, #4]
 8001e14:	4613      	mov	r3, r2
 8001e16:	009b      	lsls	r3, r3, #2
 8001e18:	4413      	add	r3, r2
 8001e1a:	3b41      	subs	r3, #65	; 0x41
 8001e1c:	fa00 f203 	lsl.w	r2, r0, r3
 8001e20:	687b      	ldr	r3, [r7, #4]
 8001e22:	681b      	ldr	r3, [r3, #0]
 8001e24:	430a      	orrs	r2, r1
 8001e26:	62da      	str	r2, [r3, #44]	; 0x2c
  }
  
  
  /* Channel sampling time configuration */
  /* For channels 10 to 17 */
  if (sConfig->Channel >= ADC_CHANNEL_10)
 8001e28:	683b      	ldr	r3, [r7, #0]
 8001e2a:	681b      	ldr	r3, [r3, #0]
 8001e2c:	2b09      	cmp	r3, #9
 8001e2e:	d91c      	bls.n	8001e6a <HAL_ADC_ConfigChannel+0x126>
  {
    MODIFY_REG(hadc->Instance->SMPR1                             ,
 8001e30:	687b      	ldr	r3, [r7, #4]
 8001e32:	681b      	ldr	r3, [r3, #0]
 8001e34:	68d9      	ldr	r1, [r3, #12]
 8001e36:	683b      	ldr	r3, [r7, #0]
 8001e38:	681a      	ldr	r2, [r3, #0]
 8001e3a:	4613      	mov	r3, r2
 8001e3c:	005b      	lsls	r3, r3, #1
 8001e3e:	4413      	add	r3, r2
 8001e40:	3b1e      	subs	r3, #30
 8001e42:	2207      	movs	r2, #7
 8001e44:	fa02 f303 	lsl.w	r3, r2, r3
 8001e48:	43db      	mvns	r3, r3
 8001e4a:	4019      	ands	r1, r3
 8001e4c:	683b      	ldr	r3, [r7, #0]
 8001e4e:	6898      	ldr	r0, [r3, #8]
 8001e50:	683b      	ldr	r3, [r7, #0]
 8001e52:	681a      	ldr	r2, [r3, #0]
 8001e54:	4613      	mov	r3, r2
 8001e56:	005b      	lsls	r3, r3, #1
 8001e58:	4413      	add	r3, r2
 8001e5a:	3b1e      	subs	r3, #30
 8001e5c:	fa00 f203 	lsl.w	r2, r0, r3
 8001e60:	687b      	ldr	r3, [r7, #4]
 8001e62:	681b      	ldr	r3, [r3, #0]
 8001e64:	430a      	orrs	r2, r1
 8001e66:	60da      	str	r2, [r3, #12]
 8001e68:	e019      	b.n	8001e9e <HAL_ADC_ConfigChannel+0x15a>
               ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel)      ,
               ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) );
  }
  else /* For channels 0 to 9 */
  {
    MODIFY_REG(hadc->Instance->SMPR2                             ,
 8001e6a:	687b      	ldr	r3, [r7, #4]
 8001e6c:	681b      	ldr	r3, [r3, #0]
 8001e6e:	6919      	ldr	r1, [r3, #16]
 8001e70:	683b      	ldr	r3, [r7, #0]
 8001e72:	681a      	ldr	r2, [r3, #0]
 8001e74:	4613      	mov	r3, r2
 8001e76:	005b      	lsls	r3, r3, #1
 8001e78:	4413      	add	r3, r2
 8001e7a:	2207      	movs	r2, #7
 8001e7c:	fa02 f303 	lsl.w	r3, r2, r3
 8001e80:	43db      	mvns	r3, r3
 8001e82:	4019      	ands	r1, r3
 8001e84:	683b      	ldr	r3, [r7, #0]
 8001e86:	6898      	ldr	r0, [r3, #8]
 8001e88:	683b      	ldr	r3, [r7, #0]
 8001e8a:	681a      	ldr	r2, [r3, #0]
 8001e8c:	4613      	mov	r3, r2
 8001e8e:	005b      	lsls	r3, r3, #1
 8001e90:	4413      	add	r3, r2
 8001e92:	fa00 f203 	lsl.w	r2, r0, r3
 8001e96:	687b      	ldr	r3, [r7, #4]
 8001e98:	681b      	ldr	r3, [r3, #0]
 8001e9a:	430a      	orrs	r2, r1
 8001e9c:	611a      	str	r2, [r3, #16]
               ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
  }
  
  /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor  */
  /* and VREFINT measurement path.                                            */
  if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
 8001e9e:	683b      	ldr	r3, [r7, #0]
 8001ea0:	681b      	ldr	r3, [r3, #0]
 8001ea2:	2b10      	cmp	r3, #16
 8001ea4:	d003      	beq.n	8001eae <HAL_ADC_ConfigChannel+0x16a>
      (sConfig->Channel == ADC_CHANNEL_VREFINT)      )
 8001ea6:	683b      	ldr	r3, [r7, #0]
 8001ea8:	681b      	ldr	r3, [r3, #0]
  if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
 8001eaa:	2b11      	cmp	r3, #17
 8001eac:	d132      	bne.n	8001f14 <HAL_ADC_ConfigChannel+0x1d0>
  {
    /* For STM32F1 devices with several ADC: Only ADC1 can access internal    */
    /* measurement channels (VrefInt/TempSensor). If these channels are       */
    /* intended to be set on other ADC instances, an error is reported.       */
    if (hadc->Instance == ADC1)
 8001eae:	687b      	ldr	r3, [r7, #4]
 8001eb0:	681b      	ldr	r3, [r3, #0]
 8001eb2:	4a1d      	ldr	r2, [pc, #116]	; (8001f28 <HAL_ADC_ConfigChannel+0x1e4>)
 8001eb4:	4293      	cmp	r3, r2
 8001eb6:	d125      	bne.n	8001f04 <HAL_ADC_ConfigChannel+0x1c0>
    {
      if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET)
 8001eb8:	687b      	ldr	r3, [r7, #4]
 8001eba:	681b      	ldr	r3, [r3, #0]
 8001ebc:	689b      	ldr	r3, [r3, #8]
 8001ebe:	f403 0300 	and.w	r3, r3, #8388608	; 0x800000
 8001ec2:	2b00      	cmp	r3, #0
 8001ec4:	d126      	bne.n	8001f14 <HAL_ADC_ConfigChannel+0x1d0>
      {
        SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
 8001ec6:	687b      	ldr	r3, [r7, #4]
 8001ec8:	681b      	ldr	r3, [r3, #0]
 8001eca:	689a      	ldr	r2, [r3, #8]
 8001ecc:	687b      	ldr	r3, [r7, #4]
 8001ece:	681b      	ldr	r3, [r3, #0]
 8001ed0:	f442 0200 	orr.w	r2, r2, #8388608	; 0x800000
 8001ed4:	609a      	str	r2, [r3, #8]
        
        if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
 8001ed6:	683b      	ldr	r3, [r7, #0]
 8001ed8:	681b      	ldr	r3, [r3, #0]
 8001eda:	2b10      	cmp	r3, #16
 8001edc:	d11a      	bne.n	8001f14 <HAL_ADC_ConfigChannel+0x1d0>
        {
          /* Delay for temperature sensor stabilization time */
          /* Compute number of CPU cycles to wait for */
          wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
 8001ede:	4b13      	ldr	r3, [pc, #76]	; (8001f2c <HAL_ADC_ConfigChannel+0x1e8>)
 8001ee0:	681b      	ldr	r3, [r3, #0]
 8001ee2:	4a13      	ldr	r2, [pc, #76]	; (8001f30 <HAL_ADC_ConfigChannel+0x1ec>)
 8001ee4:	fba2 2303 	umull	r2, r3, r2, r3
 8001ee8:	0c9a      	lsrs	r2, r3, #18
 8001eea:	4613      	mov	r3, r2
 8001eec:	009b      	lsls	r3, r3, #2
 8001eee:	4413      	add	r3, r2
 8001ef0:	005b      	lsls	r3, r3, #1
 8001ef2:	60bb      	str	r3, [r7, #8]
          while(wait_loop_index != 0U)
 8001ef4:	e002      	b.n	8001efc <HAL_ADC_ConfigChannel+0x1b8>
          {
            wait_loop_index--;
 8001ef6:	68bb      	ldr	r3, [r7, #8]
 8001ef8:	3b01      	subs	r3, #1
 8001efa:	60bb      	str	r3, [r7, #8]
          while(wait_loop_index != 0U)
 8001efc:	68bb      	ldr	r3, [r7, #8]
 8001efe:	2b00      	cmp	r3, #0
 8001f00:	d1f9      	bne.n	8001ef6 <HAL_ADC_ConfigChannel+0x1b2>
 8001f02:	e007      	b.n	8001f14 <HAL_ADC_ConfigChannel+0x1d0>
      }
    }
    else
    {
      /* Update ADC state machine to error */
      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
 8001f04:	687b      	ldr	r3, [r7, #4]
 8001f06:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 8001f08:	f043 0220 	orr.w	r2, r3, #32
 8001f0c:	687b      	ldr	r3, [r7, #4]
 8001f0e:	629a      	str	r2, [r3, #40]	; 0x28
      
      tmp_hal_status = HAL_ERROR;
 8001f10:	2301      	movs	r3, #1
 8001f12:	73fb      	strb	r3, [r7, #15]
    }
  }
  
  /* Process unlocked */
  __HAL_UNLOCK(hadc);
 8001f14:	687b      	ldr	r3, [r7, #4]
 8001f16:	2200      	movs	r2, #0
 8001f18:	f883 2024 	strb.w	r2, [r3, #36]	; 0x24
  
  /* Return function status */
  return tmp_hal_status;
 8001f1c:	7bfb      	ldrb	r3, [r7, #15]
}
 8001f1e:	4618      	mov	r0, r3
 8001f20:	3714      	adds	r7, #20
 8001f22:	46bd      	mov	sp, r7
 8001f24:	bc80      	pop	{r7}
 8001f26:	4770      	bx	lr
 8001f28:	40012400 	.word	0x40012400
 8001f2c:	20000008 	.word	0x20000008
 8001f30:	431bde83 	.word	0x431bde83

08001f34 <ADC_Enable>:
  *         and voltage regulator must be enabled (done into HAL_ADC_Init()).
  * @param  hadc: ADC handle
  * @retval HAL status.
  */
HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
{
 8001f34:	b580      	push	{r7, lr}
 8001f36:	b084      	sub	sp, #16
 8001f38:	af00      	add	r7, sp, #0
 8001f3a:	6078      	str	r0, [r7, #4]
  uint32_t tickstart = 0U;
 8001f3c:	2300      	movs	r3, #0
 8001f3e:	60fb      	str	r3, [r7, #12]
  __IO uint32_t wait_loop_index = 0U;
 8001f40:	2300      	movs	r3, #0
 8001f42:	60bb      	str	r3, [r7, #8]
  
  /* ADC enable and wait for ADC ready (in case of ADC is disabled or         */
  /* enabling phase not yet completed: flag ADC ready not yet set).           */
  /* Timeout implemented to not be stuck if ADC cannot be enabled (possible   */
  /* causes: ADC clock not running, ...).                                     */
  if (ADC_IS_ENABLE(hadc) == RESET)
 8001f44:	687b      	ldr	r3, [r7, #4]
 8001f46:	681b      	ldr	r3, [r3, #0]
 8001f48:	689b      	ldr	r3, [r3, #8]
 8001f4a:	f003 0301 	and.w	r3, r3, #1
 8001f4e:	2b01      	cmp	r3, #1
 8001f50:	d039      	beq.n	8001fc6 <ADC_Enable+0x92>
  {
    /* Enable the Peripheral */
    __HAL_ADC_ENABLE(hadc);
 8001f52:	687b      	ldr	r3, [r7, #4]
 8001f54:	681b      	ldr	r3, [r3, #0]
 8001f56:	689a      	ldr	r2, [r3, #8]
 8001f58:	687b      	ldr	r3, [r7, #4]
 8001f5a:	681b      	ldr	r3, [r3, #0]
 8001f5c:	f042 0201 	orr.w	r2, r2, #1
 8001f60:	609a      	str	r2, [r3, #8]
    
    /* Delay for ADC stabilization time */
    /* Compute number of CPU cycles to wait for */
    wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
 8001f62:	4b1b      	ldr	r3, [pc, #108]	; (8001fd0 <ADC_Enable+0x9c>)
 8001f64:	681b      	ldr	r3, [r3, #0]
 8001f66:	4a1b      	ldr	r2, [pc, #108]	; (8001fd4 <ADC_Enable+0xa0>)
 8001f68:	fba2 2303 	umull	r2, r3, r2, r3
 8001f6c:	0c9b      	lsrs	r3, r3, #18
 8001f6e:	60bb      	str	r3, [r7, #8]
    while(wait_loop_index != 0U)
 8001f70:	e002      	b.n	8001f78 <ADC_Enable+0x44>
    {
      wait_loop_index--;
 8001f72:	68bb      	ldr	r3, [r7, #8]
 8001f74:	3b01      	subs	r3, #1
 8001f76:	60bb      	str	r3, [r7, #8]
    while(wait_loop_index != 0U)
 8001f78:	68bb      	ldr	r3, [r7, #8]
 8001f7a:	2b00      	cmp	r3, #0
 8001f7c:	d1f9      	bne.n	8001f72 <ADC_Enable+0x3e>
    }
    
    /* Get tick count */
    tickstart = HAL_GetTick();
 8001f7e:	f7ff fc65 	bl	800184c <HAL_GetTick>
 8001f82:	60f8      	str	r0, [r7, #12]

    /* Wait for ADC effectively enabled */
    while(ADC_IS_ENABLE(hadc) == RESET)
 8001f84:	e018      	b.n	8001fb8 <ADC_Enable+0x84>
    {
      if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
 8001f86:	f7ff fc61 	bl	800184c <HAL_GetTick>
 8001f8a:	4602      	mov	r2, r0
 8001f8c:	68fb      	ldr	r3, [r7, #12]
 8001f8e:	1ad3      	subs	r3, r2, r3
 8001f90:	2b02      	cmp	r3, #2
 8001f92:	d911      	bls.n	8001fb8 <ADC_Enable+0x84>
      {
        /* Update ADC state machine to error */
        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
 8001f94:	687b      	ldr	r3, [r7, #4]
 8001f96:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 8001f98:	f043 0210 	orr.w	r2, r3, #16
 8001f9c:	687b      	ldr	r3, [r7, #4]
 8001f9e:	629a      	str	r2, [r3, #40]	; 0x28
      
        /* Set ADC error code to ADC IP internal error */
        SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
 8001fa0:	687b      	ldr	r3, [r7, #4]
 8001fa2:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 8001fa4:	f043 0201 	orr.w	r2, r3, #1
 8001fa8:	687b      	ldr	r3, [r7, #4]
 8001faa:	62da      	str	r2, [r3, #44]	; 0x2c
        
        /* Process unlocked */
        __HAL_UNLOCK(hadc);
 8001fac:	687b      	ldr	r3, [r7, #4]
 8001fae:	2200      	movs	r2, #0
 8001fb0:	f883 2024 	strb.w	r2, [r3, #36]	; 0x24
      
        return HAL_ERROR;
 8001fb4:	2301      	movs	r3, #1
 8001fb6:	e007      	b.n	8001fc8 <ADC_Enable+0x94>
    while(ADC_IS_ENABLE(hadc) == RESET)
 8001fb8:	687b      	ldr	r3, [r7, #4]
 8001fba:	681b      	ldr	r3, [r3, #0]
 8001fbc:	689b      	ldr	r3, [r3, #8]
 8001fbe:	f003 0301 	and.w	r3, r3, #1
 8001fc2:	2b01      	cmp	r3, #1
 8001fc4:	d1df      	bne.n	8001f86 <ADC_Enable+0x52>
      }
    }
  }
   
  /* Return HAL status */
  return HAL_OK;
 8001fc6:	2300      	movs	r3, #0
}
 8001fc8:	4618      	mov	r0, r3
 8001fca:	3710      	adds	r7, #16
 8001fcc:	46bd      	mov	sp, r7
 8001fce:	bd80      	pop	{r7, pc}
 8001fd0:	20000008 	.word	0x20000008
 8001fd4:	431bde83 	.word	0x431bde83

08001fd8 <ADC_ConversionStop_Disable>:
  *         stopped to disable the ADC.
  * @param  hadc: ADC handle
  * @retval HAL status.
  */
HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc)
{
 8001fd8:	b580      	push	{r7, lr}
 8001fda:	b084      	sub	sp, #16
 8001fdc:	af00      	add	r7, sp, #0
 8001fde:	6078      	str	r0, [r7, #4]
  uint32_t tickstart = 0U;
 8001fe0:	2300      	movs	r3, #0
 8001fe2:	60fb      	str	r3, [r7, #12]
  
  /* Verification if ADC is not already disabled */
  if (ADC_IS_ENABLE(hadc) != RESET)
 8001fe4:	687b      	ldr	r3, [r7, #4]
 8001fe6:	681b      	ldr	r3, [r3, #0]
 8001fe8:	689b      	ldr	r3, [r3, #8]
 8001fea:	f003 0301 	and.w	r3, r3, #1
 8001fee:	2b01      	cmp	r3, #1
 8001ff0:	d127      	bne.n	8002042 <ADC_ConversionStop_Disable+0x6a>
  {
    /* Disable the ADC peripheral */
    __HAL_ADC_DISABLE(hadc);
 8001ff2:	687b      	ldr	r3, [r7, #4]
 8001ff4:	681b      	ldr	r3, [r3, #0]
 8001ff6:	689a      	ldr	r2, [r3, #8]
 8001ff8:	687b      	ldr	r3, [r7, #4]
 8001ffa:	681b      	ldr	r3, [r3, #0]
 8001ffc:	f022 0201 	bic.w	r2, r2, #1
 8002000:	609a      	str	r2, [r3, #8]
     
    /* Get tick count */
    tickstart = HAL_GetTick();
 8002002:	f7ff fc23 	bl	800184c <HAL_GetTick>
 8002006:	60f8      	str	r0, [r7, #12]
    
    /* Wait for ADC effectively disabled */
    while(ADC_IS_ENABLE(hadc) != RESET)
 8002008:	e014      	b.n	8002034 <ADC_ConversionStop_Disable+0x5c>
    {
      if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
 800200a:	f7ff fc1f 	bl	800184c <HAL_GetTick>
 800200e:	4602      	mov	r2, r0
 8002010:	68fb      	ldr	r3, [r7, #12]
 8002012:	1ad3      	subs	r3, r2, r3
 8002014:	2b02      	cmp	r3, #2
 8002016:	d90d      	bls.n	8002034 <ADC_ConversionStop_Disable+0x5c>
      {
        /* Update ADC state machine to error */
        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
 8002018:	687b      	ldr	r3, [r7, #4]
 800201a:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 800201c:	f043 0210 	orr.w	r2, r3, #16
 8002020:	687b      	ldr	r3, [r7, #4]
 8002022:	629a      	str	r2, [r3, #40]	; 0x28
        
        /* Set ADC error code to ADC IP internal error */
        SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
 8002024:	687b      	ldr	r3, [r7, #4]
 8002026:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 8002028:	f043 0201 	orr.w	r2, r3, #1
 800202c:	687b      	ldr	r3, [r7, #4]
 800202e:	62da      	str	r2, [r3, #44]	; 0x2c
        
        return HAL_ERROR;
 8002030:	2301      	movs	r3, #1
 8002032:	e007      	b.n	8002044 <ADC_ConversionStop_Disable+0x6c>
    while(ADC_IS_ENABLE(hadc) != RESET)
 8002034:	687b      	ldr	r3, [r7, #4]
 8002036:	681b      	ldr	r3, [r3, #0]
 8002038:	689b      	ldr	r3, [r3, #8]
 800203a:	f003 0301 	and.w	r3, r3, #1
 800203e:	2b01      	cmp	r3, #1
 8002040:	d0e3      	beq.n	800200a <ADC_ConversionStop_Disable+0x32>
      }
    }
  }
  
  /* Return HAL status */
  return HAL_OK;
 8002042:	2300      	movs	r3, #0
}
 8002044:	4618      	mov	r0, r3
 8002046:	3710      	adds	r7, #16
 8002048:	46bd      	mov	sp, r7
 800204a:	bd80      	pop	{r7, pc}

0800204c <ADC_DMAConvCplt>:
  * @brief  DMA transfer complete callback. 
  * @param  hdma: pointer to DMA handle.
  * @retval None
  */
void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
{
 800204c:	b580      	push	{r7, lr}
 800204e:	b084      	sub	sp, #16
 8002050:	af00      	add	r7, sp, #0
 8002052:	6078      	str	r0, [r7, #4]
  /* Retrieve ADC handle corresponding to current DMA handle */
  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
 8002054:	687b      	ldr	r3, [r7, #4]
 8002056:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8002058:	60fb      	str	r3, [r7, #12]
 
  /* Update state machine on conversion status if not in error state */
  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
 800205a:	68fb      	ldr	r3, [r7, #12]
 800205c:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 800205e:	f003 0350 	and.w	r3, r3, #80	; 0x50
 8002062:	2b00      	cmp	r3, #0
 8002064:	d127      	bne.n	80020b6 <ADC_DMAConvCplt+0x6a>
  {
    /* Update ADC state machine */
    SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
 8002066:	68fb      	ldr	r3, [r7, #12]
 8002068:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 800206a:	f443 7200 	orr.w	r2, r3, #512	; 0x200
 800206e:	68fb      	ldr	r3, [r7, #12]
 8002070:	629a      	str	r2, [r3, #40]	; 0x28
    /* Determine whether any further conversion upcoming on group regular     */
    /* by external trigger, continuous mode or scan sequence on going.        */
    /* Note: On STM32F1 devices, in case of sequencer enabled                 */
    /*       (several ranks selected), end of conversion flag is raised       */
    /*       at the end of the sequence.                                      */
    if(ADC_IS_SOFTWARE_START_REGULAR(hadc)        && 
 8002072:	68fb      	ldr	r3, [r7, #12]
 8002074:	681b      	ldr	r3, [r3, #0]
 8002076:	689b      	ldr	r3, [r3, #8]
 8002078:	f403 2360 	and.w	r3, r3, #917504	; 0xe0000
 800207c:	f5b3 2f60 	cmp.w	r3, #917504	; 0xe0000
 8002080:	d115      	bne.n	80020ae <ADC_DMAConvCplt+0x62>
       (hadc->Init.ContinuousConvMode == DISABLE)   )
 8002082:	68fb      	ldr	r3, [r7, #12]
 8002084:	7b1b      	ldrb	r3, [r3, #12]
    if(ADC_IS_SOFTWARE_START_REGULAR(hadc)        && 
 8002086:	2b00      	cmp	r3, #0
 8002088:	d111      	bne.n	80020ae <ADC_DMAConvCplt+0x62>
    {
      /* Set ADC state */
      CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);   
 800208a:	68fb      	ldr	r3, [r7, #12]
 800208c:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 800208e:	f423 7280 	bic.w	r2, r3, #256	; 0x100
 8002092:	68fb      	ldr	r3, [r7, #12]
 8002094:	629a      	str	r2, [r3, #40]	; 0x28
      
      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
 8002096:	68fb      	ldr	r3, [r7, #12]
 8002098:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 800209a:	f403 5380 	and.w	r3, r3, #4096	; 0x1000
 800209e:	2b00      	cmp	r3, #0
 80020a0:	d105      	bne.n	80020ae <ADC_DMAConvCplt+0x62>
      {
        SET_BIT(hadc->State, HAL_ADC_STATE_READY);
 80020a2:	68fb      	ldr	r3, [r7, #12]
 80020a4:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 80020a6:	f043 0201 	orr.w	r2, r3, #1
 80020aa:	68fb      	ldr	r3, [r7, #12]
 80020ac:	629a      	str	r2, [r3, #40]	; 0x28
    
    /* Conversion complete callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
    hadc->ConvCpltCallback(hadc);
#else
    HAL_ADC_ConvCpltCallback(hadc);
 80020ae:	68f8      	ldr	r0, [r7, #12]
 80020b0:	f7ff f946 	bl	8001340 <HAL_ADC_ConvCpltCallback>
  else
  {
    /* Call DMA error callback */
    hadc->DMA_Handle->XferErrorCallback(hdma);
  }
}
 80020b4:	e004      	b.n	80020c0 <ADC_DMAConvCplt+0x74>
    hadc->DMA_Handle->XferErrorCallback(hdma);
 80020b6:	68fb      	ldr	r3, [r7, #12]
 80020b8:	6a1b      	ldr	r3, [r3, #32]
 80020ba:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 80020bc:	6878      	ldr	r0, [r7, #4]
 80020be:	4798      	blx	r3
}
 80020c0:	bf00      	nop
 80020c2:	3710      	adds	r7, #16
 80020c4:	46bd      	mov	sp, r7
 80020c6:	bd80      	pop	{r7, pc}

080020c8 <ADC_DMAHalfConvCplt>:
  * @brief  DMA half transfer complete callback. 
  * @param  hdma: pointer to DMA handle.
  * @retval None
  */
void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)   
{
 80020c8:	b580      	push	{r7, lr}
 80020ca:	b084      	sub	sp, #16
 80020cc:	af00      	add	r7, sp, #0
 80020ce:	6078      	str	r0, [r7, #4]
  /* Retrieve ADC handle corresponding to current DMA handle */
  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
 80020d0:	687b      	ldr	r3, [r7, #4]
 80020d2:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 80020d4:	60fb      	str	r3, [r7, #12]
  
  /* Half conversion callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
    hadc->ConvHalfCpltCallback(hadc);
#else
  HAL_ADC_ConvHalfCpltCallback(hadc);
 80020d6:	68f8      	ldr	r0, [r7, #12]
 80020d8:	f7ff fe19 	bl	8001d0e <HAL_ADC_ConvHalfCpltCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}
 80020dc:	bf00      	nop
 80020de:	3710      	adds	r7, #16
 80020e0:	46bd      	mov	sp, r7
 80020e2:	bd80      	pop	{r7, pc}

080020e4 <ADC_DMAError>:
  * @brief  DMA error callback 
  * @param  hdma: pointer to DMA handle.
  * @retval None
  */
void ADC_DMAError(DMA_HandleTypeDef *hdma)   
{
 80020e4:	b580      	push	{r7, lr}
 80020e6:	b084      	sub	sp, #16
 80020e8:	af00      	add	r7, sp, #0
 80020ea:	6078      	str	r0, [r7, #4]
  /* Retrieve ADC handle corresponding to current DMA handle */
  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
 80020ec:	687b      	ldr	r3, [r7, #4]
 80020ee:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 80020f0:	60fb      	str	r3, [r7, #12]
  
  /* Set ADC state */
  SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
 80020f2:	68fb      	ldr	r3, [r7, #12]
 80020f4:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 80020f6:	f043 0240 	orr.w	r2, r3, #64	; 0x40
 80020fa:	68fb      	ldr	r3, [r7, #12]
 80020fc:	629a      	str	r2, [r3, #40]	; 0x28
  
  /* Set ADC error code to DMA error */
  SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
 80020fe:	68fb      	ldr	r3, [r7, #12]
 8002100:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 8002102:	f043 0204 	orr.w	r2, r3, #4
 8002106:	68fb      	ldr	r3, [r7, #12]
 8002108:	62da      	str	r2, [r3, #44]	; 0x2c
  
  /* Error callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
  hadc->ErrorCallback(hadc);
#else
  HAL_ADC_ErrorCallback(hadc);
 800210a:	68f8      	ldr	r0, [r7, #12]
 800210c:	f7ff fe11 	bl	8001d32 <HAL_ADC_ErrorCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}
 8002110:	bf00      	nop
 8002112:	3710      	adds	r7, #16
 8002114:	46bd      	mov	sp, r7
 8002116:	bd80      	pop	{r7, pc}

08002118 <HAL_ADCEx_Calibration_Start>:
  *         the completion of this function.
  * @param  hadc: ADC handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc)
{
 8002118:	b590      	push	{r4, r7, lr}
 800211a:	b087      	sub	sp, #28
 800211c:	af00      	add	r7, sp, #0
 800211e:	6078      	str	r0, [r7, #4]
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
 8002120:	2300      	movs	r3, #0
 8002122:	75fb      	strb	r3, [r7, #23]
  uint32_t tickstart;
  __IO uint32_t wait_loop_index = 0U;
 8002124:	2300      	movs	r3, #0
 8002126:	60fb      	str	r3, [r7, #12]
  
  /* Check the parameters */
  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));

  /* Process locked */
  __HAL_LOCK(hadc);
 8002128:	687b      	ldr	r3, [r7, #4]
 800212a:	f893 3024 	ldrb.w	r3, [r3, #36]	; 0x24
 800212e:	2b01      	cmp	r3, #1
 8002130:	d101      	bne.n	8002136 <HAL_ADCEx_Calibration_Start+0x1e>
 8002132:	2302      	movs	r3, #2
 8002134:	e086      	b.n	8002244 <HAL_ADCEx_Calibration_Start+0x12c>
 8002136:	687b      	ldr	r3, [r7, #4]
 8002138:	2201      	movs	r2, #1
 800213a:	f883 2024 	strb.w	r2, [r3, #36]	; 0x24
  /* 1. Calibration prerequisite:                                             */
  /*    - ADC must be disabled for at least two ADC clock cycles in disable   */
  /*      mode before ADC enable                                              */
  /* Stop potential conversion on going, on regular and injected groups       */
  /* Disable ADC peripheral */
  tmp_hal_status = ADC_ConversionStop_Disable(hadc);
 800213e:	6878      	ldr	r0, [r7, #4]
 8002140:	f7ff ff4a 	bl	8001fd8 <ADC_ConversionStop_Disable>
 8002144:	4603      	mov	r3, r0
 8002146:	75fb      	strb	r3, [r7, #23]
  
  /* Check if ADC is effectively disabled */
  if (tmp_hal_status == HAL_OK)
 8002148:	7dfb      	ldrb	r3, [r7, #23]
 800214a:	2b00      	cmp	r3, #0
 800214c:	d175      	bne.n	800223a <HAL_ADCEx_Calibration_Start+0x122>
  {
    /* Set ADC state */
    ADC_STATE_CLR_SET(hadc->State,
 800214e:	687b      	ldr	r3, [r7, #4]
 8002150:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 8002152:	f423 5388 	bic.w	r3, r3, #4352	; 0x1100
 8002156:	f023 0302 	bic.w	r3, r3, #2
 800215a:	f043 0202 	orr.w	r2, r3, #2
 800215e:	687b      	ldr	r3, [r7, #4]
 8002160:	629a      	str	r2, [r3, #40]	; 0x28
    
    /* Hardware prerequisite: delay before starting the calibration.          */
    /*  - Computation of CPU clock cycles corresponding to ADC clock cycles.  */
    /*  - Wait for the expected ADC clock cycles delay */
    wait_loop_index = ((SystemCoreClock
                        / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC))
 8002162:	4b3a      	ldr	r3, [pc, #232]	; (800224c <HAL_ADCEx_Calibration_Start+0x134>)
 8002164:	681c      	ldr	r4, [r3, #0]
 8002166:	2002      	movs	r0, #2
 8002168:	f001 fbf0 	bl	800394c <HAL_RCCEx_GetPeriphCLKFreq>
 800216c:	4603      	mov	r3, r0
 800216e:	fbb4 f3f3 	udiv	r3, r4, r3
                       * ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES        );
 8002172:	005b      	lsls	r3, r3, #1
    wait_loop_index = ((SystemCoreClock
 8002174:	60fb      	str	r3, [r7, #12]

    while(wait_loop_index != 0U)
 8002176:	e002      	b.n	800217e <HAL_ADCEx_Calibration_Start+0x66>
    {
      wait_loop_index--;
 8002178:	68fb      	ldr	r3, [r7, #12]
 800217a:	3b01      	subs	r3, #1
 800217c:	60fb      	str	r3, [r7, #12]
    while(wait_loop_index != 0U)
 800217e:	68fb      	ldr	r3, [r7, #12]
 8002180:	2b00      	cmp	r3, #0
 8002182:	d1f9      	bne.n	8002178 <HAL_ADCEx_Calibration_Start+0x60>
    }
    
    /* 2. Enable the ADC peripheral */
    ADC_Enable(hadc);
 8002184:	6878      	ldr	r0, [r7, #4]
 8002186:	f7ff fed5 	bl	8001f34 <ADC_Enable>
    
    /* 3. Resets ADC calibration registers */  
    SET_BIT(hadc->Instance->CR2, ADC_CR2_RSTCAL);
 800218a:	687b      	ldr	r3, [r7, #4]
 800218c:	681b      	ldr	r3, [r3, #0]
 800218e:	689a      	ldr	r2, [r3, #8]
 8002190:	687b      	ldr	r3, [r7, #4]
 8002192:	681b      	ldr	r3, [r3, #0]
 8002194:	f042 0208 	orr.w	r2, r2, #8
 8002198:	609a      	str	r2, [r3, #8]
    
    tickstart = HAL_GetTick();  
 800219a:	f7ff fb57 	bl	800184c <HAL_GetTick>
 800219e:	6138      	str	r0, [r7, #16]

    /* Wait for calibration reset completion */
    while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL))
 80021a0:	e014      	b.n	80021cc <HAL_ADCEx_Calibration_Start+0xb4>
    {
      if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
 80021a2:	f7ff fb53 	bl	800184c <HAL_GetTick>
 80021a6:	4602      	mov	r2, r0
 80021a8:	693b      	ldr	r3, [r7, #16]
 80021aa:	1ad3      	subs	r3, r2, r3
 80021ac:	2b0a      	cmp	r3, #10
 80021ae:	d90d      	bls.n	80021cc <HAL_ADCEx_Calibration_Start+0xb4>
      {
        /* Update ADC state machine to error */
        ADC_STATE_CLR_SET(hadc->State,
 80021b0:	687b      	ldr	r3, [r7, #4]
 80021b2:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 80021b4:	f023 0312 	bic.w	r3, r3, #18
 80021b8:	f043 0210 	orr.w	r2, r3, #16
 80021bc:	687b      	ldr	r3, [r7, #4]
 80021be:	629a      	str	r2, [r3, #40]	; 0x28
                          HAL_ADC_STATE_BUSY_INTERNAL,
                          HAL_ADC_STATE_ERROR_INTERNAL);
        
        /* Process unlocked */
        __HAL_UNLOCK(hadc);
 80021c0:	687b      	ldr	r3, [r7, #4]
 80021c2:	2200      	movs	r2, #0
 80021c4:	f883 2024 	strb.w	r2, [r3, #36]	; 0x24
        
        return HAL_ERROR;
 80021c8:	2301      	movs	r3, #1
 80021ca:	e03b      	b.n	8002244 <HAL_ADCEx_Calibration_Start+0x12c>
    while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL))
 80021cc:	687b      	ldr	r3, [r7, #4]
 80021ce:	681b      	ldr	r3, [r3, #0]
 80021d0:	689b      	ldr	r3, [r3, #8]
 80021d2:	f003 0308 	and.w	r3, r3, #8
 80021d6:	2b00      	cmp	r3, #0
 80021d8:	d1e3      	bne.n	80021a2 <HAL_ADCEx_Calibration_Start+0x8a>
      }
    }
    
    
    /* 4. Start ADC calibration */
    SET_BIT(hadc->Instance->CR2, ADC_CR2_CAL);
 80021da:	687b      	ldr	r3, [r7, #4]
 80021dc:	681b      	ldr	r3, [r3, #0]
 80021de:	689a      	ldr	r2, [r3, #8]
 80021e0:	687b      	ldr	r3, [r7, #4]
 80021e2:	681b      	ldr	r3, [r3, #0]
 80021e4:	f042 0204 	orr.w	r2, r2, #4
 80021e8:	609a      	str	r2, [r3, #8]
    
    tickstart = HAL_GetTick();  
 80021ea:	f7ff fb2f 	bl	800184c <HAL_GetTick>
 80021ee:	6138      	str	r0, [r7, #16]

    /* Wait for calibration completion */
    while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL))
 80021f0:	e014      	b.n	800221c <HAL_ADCEx_Calibration_Start+0x104>
    {
      if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
 80021f2:	f7ff fb2b 	bl	800184c <HAL_GetTick>
 80021f6:	4602      	mov	r2, r0
 80021f8:	693b      	ldr	r3, [r7, #16]
 80021fa:	1ad3      	subs	r3, r2, r3
 80021fc:	2b0a      	cmp	r3, #10
 80021fe:	d90d      	bls.n	800221c <HAL_ADCEx_Calibration_Start+0x104>
      {
        /* Update ADC state machine to error */
        ADC_STATE_CLR_SET(hadc->State,
 8002200:	687b      	ldr	r3, [r7, #4]
 8002202:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 8002204:	f023 0312 	bic.w	r3, r3, #18
 8002208:	f043 0210 	orr.w	r2, r3, #16
 800220c:	687b      	ldr	r3, [r7, #4]
 800220e:	629a      	str	r2, [r3, #40]	; 0x28
                          HAL_ADC_STATE_BUSY_INTERNAL,
                          HAL_ADC_STATE_ERROR_INTERNAL);
        
        /* Process unlocked */
        __HAL_UNLOCK(hadc);
 8002210:	687b      	ldr	r3, [r7, #4]
 8002212:	2200      	movs	r2, #0
 8002214:	f883 2024 	strb.w	r2, [r3, #36]	; 0x24
        
        return HAL_ERROR;
 8002218:	2301      	movs	r3, #1
 800221a:	e013      	b.n	8002244 <HAL_ADCEx_Calibration_Start+0x12c>
    while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL))
 800221c:	687b      	ldr	r3, [r7, #4]
 800221e:	681b      	ldr	r3, [r3, #0]
 8002220:	689b      	ldr	r3, [r3, #8]
 8002222:	f003 0304 	and.w	r3, r3, #4
 8002226:	2b00      	cmp	r3, #0
 8002228:	d1e3      	bne.n	80021f2 <HAL_ADCEx_Calibration_Start+0xda>
      }
    }
    
    /* Set ADC state */
    ADC_STATE_CLR_SET(hadc->State,
 800222a:	687b      	ldr	r3, [r7, #4]
 800222c:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 800222e:	f023 0303 	bic.w	r3, r3, #3
 8002232:	f043 0201 	orr.w	r2, r3, #1
 8002236:	687b      	ldr	r3, [r7, #4]
 8002238:	629a      	str	r2, [r3, #40]	; 0x28
                      HAL_ADC_STATE_BUSY_INTERNAL,
                      HAL_ADC_STATE_READY);
  }
  
  /* Process unlocked */
  __HAL_UNLOCK(hadc);
 800223a:	687b      	ldr	r3, [r7, #4]
 800223c:	2200      	movs	r2, #0
 800223e:	f883 2024 	strb.w	r2, [r3, #36]	; 0x24
  
  /* Return function status */
  return tmp_hal_status;
 8002242:	7dfb      	ldrb	r3, [r7, #23]
}
 8002244:	4618      	mov	r0, r3
 8002246:	371c      	adds	r7, #28
 8002248:	46bd      	mov	sp, r7
 800224a:	bd90      	pop	{r4, r7, pc}
 800224c:	20000008 	.word	0x20000008

08002250 <HAL_ADCEx_InjectedConvCpltCallback>:
  * @brief  Injected conversion complete callback in non blocking mode 
  * @param  hadc: ADC handle
  * @retval None
  */
__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
{
 8002250:	b480      	push	{r7}
 8002252:	b083      	sub	sp, #12
 8002254:	af00      	add	r7, sp, #0
 8002256:	6078      	str	r0, [r7, #4]
  /* Prevent unused argument(s) compilation warning */
  UNUSED(hadc);
  /* NOTE : This function Should not be modified, when the callback is needed,
            the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file
  */
}
 8002258:	bf00      	nop
 800225a:	370c      	adds	r7, #12
 800225c:	46bd      	mov	sp, r7
 800225e:	bc80      	pop	{r7}
 8002260:	4770      	bx	lr
	...

08002264 <__NVIC_SetPriorityGrouping>:
           In case of a conflict between priority grouping and available
           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
  \param [in]      PriorityGroup  Priority grouping field.
 */
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
 8002264:	b480      	push	{r7}
 8002266:	b085      	sub	sp, #20
 8002268:	af00      	add	r7, sp, #0
 800226a:	6078      	str	r0, [r7, #4]
  uint32_t reg_value;
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
 800226c:	687b      	ldr	r3, [r7, #4]
 800226e:	f003 0307 	and.w	r3, r3, #7
 8002272:	60fb      	str	r3, [r7, #12]

  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
 8002274:	4b0c      	ldr	r3, [pc, #48]	; (80022a8 <__NVIC_SetPriorityGrouping+0x44>)
 8002276:	68db      	ldr	r3, [r3, #12]
 8002278:	60bb      	str	r3, [r7, #8]
  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
 800227a:	68ba      	ldr	r2, [r7, #8]
 800227c:	f64f 03ff 	movw	r3, #63743	; 0xf8ff
 8002280:	4013      	ands	r3, r2
 8002282:	60bb      	str	r3, [r7, #8]
  reg_value  =  (reg_value                                   |
                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) );               /* Insert write key and priority group */
 8002284:	68fb      	ldr	r3, [r7, #12]
 8002286:	021a      	lsls	r2, r3, #8
                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
 8002288:	68bb      	ldr	r3, [r7, #8]
 800228a:	4313      	orrs	r3, r2
  reg_value  =  (reg_value                                   |
 800228c:	f043 63bf 	orr.w	r3, r3, #100139008	; 0x5f80000
 8002290:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
 8002294:	60bb      	str	r3, [r7, #8]
  SCB->AIRCR =  reg_value;
 8002296:	4a04      	ldr	r2, [pc, #16]	; (80022a8 <__NVIC_SetPriorityGrouping+0x44>)
 8002298:	68bb      	ldr	r3, [r7, #8]
 800229a:	60d3      	str	r3, [r2, #12]
}
 800229c:	bf00      	nop
 800229e:	3714      	adds	r7, #20
 80022a0:	46bd      	mov	sp, r7
 80022a2:	bc80      	pop	{r7}
 80022a4:	4770      	bx	lr
 80022a6:	bf00      	nop
 80022a8:	e000ed00 	.word	0xe000ed00

080022ac <__NVIC_GetPriorityGrouping>:
  \brief   Get Priority Grouping
  \details Reads the priority grouping field from the NVIC Interrupt Controller.
  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
 */
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
 80022ac:	b480      	push	{r7}
 80022ae:	af00      	add	r7, sp, #0
  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
 80022b0:	4b04      	ldr	r3, [pc, #16]	; (80022c4 <__NVIC_GetPriorityGrouping+0x18>)
 80022b2:	68db      	ldr	r3, [r3, #12]
 80022b4:	0a1b      	lsrs	r3, r3, #8
 80022b6:	f003 0307 	and.w	r3, r3, #7
}
 80022ba:	4618      	mov	r0, r3
 80022bc:	46bd      	mov	sp, r7
 80022be:	bc80      	pop	{r7}
 80022c0:	4770      	bx	lr
 80022c2:	bf00      	nop
 80022c4:	e000ed00 	.word	0xe000ed00

080022c8 <__NVIC_EnableIRQ>:
  \details Enables a device specific interrupt in the NVIC interrupt controller.
  \param [in]      IRQn  Device specific interrupt number.
  \note    IRQn must not be negative.
 */
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
 80022c8:	b480      	push	{r7}
 80022ca:	b083      	sub	sp, #12
 80022cc:	af00      	add	r7, sp, #0
 80022ce:	4603      	mov	r3, r0
 80022d0:	71fb      	strb	r3, [r7, #7]
  if ((int32_t)(IRQn) >= 0)
 80022d2:	f997 3007 	ldrsb.w	r3, [r7, #7]
 80022d6:	2b00      	cmp	r3, #0
 80022d8:	db0b      	blt.n	80022f2 <__NVIC_EnableIRQ+0x2a>
  {
    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
 80022da:	79fb      	ldrb	r3, [r7, #7]
 80022dc:	f003 021f 	and.w	r2, r3, #31
 80022e0:	4906      	ldr	r1, [pc, #24]	; (80022fc <__NVIC_EnableIRQ+0x34>)
 80022e2:	f997 3007 	ldrsb.w	r3, [r7, #7]
 80022e6:	095b      	lsrs	r3, r3, #5
 80022e8:	2001      	movs	r0, #1
 80022ea:	fa00 f202 	lsl.w	r2, r0, r2
 80022ee:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
  }
}
 80022f2:	bf00      	nop
 80022f4:	370c      	adds	r7, #12
 80022f6:	46bd      	mov	sp, r7
 80022f8:	bc80      	pop	{r7}
 80022fa:	4770      	bx	lr
 80022fc:	e000e100 	.word	0xe000e100

08002300 <__NVIC_SetPriority>:
  \param [in]      IRQn  Interrupt number.
  \param [in]  priority  Priority to set.
  \note    The priority cannot be set for every processor exception.
 */
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
 8002300:	b480      	push	{r7}
 8002302:	b083      	sub	sp, #12
 8002304:	af00      	add	r7, sp, #0
 8002306:	4603      	mov	r3, r0
 8002308:	6039      	str	r1, [r7, #0]
 800230a:	71fb      	strb	r3, [r7, #7]
  if ((int32_t)(IRQn) >= 0)
 800230c:	f997 3007 	ldrsb.w	r3, [r7, #7]
 8002310:	2b00      	cmp	r3, #0
 8002312:	db0a      	blt.n	800232a <__NVIC_SetPriority+0x2a>
  {
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8002314:	683b      	ldr	r3, [r7, #0]
 8002316:	b2da      	uxtb	r2, r3
 8002318:	490c      	ldr	r1, [pc, #48]	; (800234c <__NVIC_SetPriority+0x4c>)
 800231a:	f997 3007 	ldrsb.w	r3, [r7, #7]
 800231e:	0112      	lsls	r2, r2, #4
 8002320:	b2d2      	uxtb	r2, r2
 8002322:	440b      	add	r3, r1
 8002324:	f883 2300 	strb.w	r2, [r3, #768]	; 0x300
  }
  else
  {
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
  }
}
 8002328:	e00a      	b.n	8002340 <__NVIC_SetPriority+0x40>
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 800232a:	683b      	ldr	r3, [r7, #0]
 800232c:	b2da      	uxtb	r2, r3
 800232e:	4908      	ldr	r1, [pc, #32]	; (8002350 <__NVIC_SetPriority+0x50>)
 8002330:	79fb      	ldrb	r3, [r7, #7]
 8002332:	f003 030f 	and.w	r3, r3, #15
 8002336:	3b04      	subs	r3, #4
 8002338:	0112      	lsls	r2, r2, #4
 800233a:	b2d2      	uxtb	r2, r2
 800233c:	440b      	add	r3, r1
 800233e:	761a      	strb	r2, [r3, #24]
}
 8002340:	bf00      	nop
 8002342:	370c      	adds	r7, #12
 8002344:	46bd      	mov	sp, r7
 8002346:	bc80      	pop	{r7}
 8002348:	4770      	bx	lr
 800234a:	bf00      	nop
 800234c:	e000e100 	.word	0xe000e100
 8002350:	e000ed00 	.word	0xe000ed00

08002354 <NVIC_EncodePriority>:
  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
  \param [in]       SubPriority  Subpriority value (starting from 0).
  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
 */
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
 8002354:	b480      	push	{r7}
 8002356:	b089      	sub	sp, #36	; 0x24
 8002358:	af00      	add	r7, sp, #0
 800235a:	60f8      	str	r0, [r7, #12]
 800235c:	60b9      	str	r1, [r7, #8]
 800235e:	607a      	str	r2, [r7, #4]
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
 8002360:	68fb      	ldr	r3, [r7, #12]
 8002362:	f003 0307 	and.w	r3, r3, #7
 8002366:	61fb      	str	r3, [r7, #28]
  uint32_t PreemptPriorityBits;
  uint32_t SubPriorityBits;

  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
 8002368:	69fb      	ldr	r3, [r7, #28]
 800236a:	f1c3 0307 	rsb	r3, r3, #7
 800236e:	2b04      	cmp	r3, #4
 8002370:	bf28      	it	cs
 8002372:	2304      	movcs	r3, #4
 8002374:	61bb      	str	r3, [r7, #24]
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 8002376:	69fb      	ldr	r3, [r7, #28]
 8002378:	3304      	adds	r3, #4
 800237a:	2b06      	cmp	r3, #6
 800237c:	d902      	bls.n	8002384 <NVIC_EncodePriority+0x30>
 800237e:	69fb      	ldr	r3, [r7, #28]
 8002380:	3b03      	subs	r3, #3
 8002382:	e000      	b.n	8002386 <NVIC_EncodePriority+0x32>
 8002384:	2300      	movs	r3, #0
 8002386:	617b      	str	r3, [r7, #20]

  return (
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 8002388:	f04f 32ff 	mov.w	r2, #4294967295
 800238c:	69bb      	ldr	r3, [r7, #24]
 800238e:	fa02 f303 	lsl.w	r3, r2, r3
 8002392:	43da      	mvns	r2, r3
 8002394:	68bb      	ldr	r3, [r7, #8]
 8002396:	401a      	ands	r2, r3
 8002398:	697b      	ldr	r3, [r7, #20]
 800239a:	409a      	lsls	r2, r3
           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
 800239c:	f04f 31ff 	mov.w	r1, #4294967295
 80023a0:	697b      	ldr	r3, [r7, #20]
 80023a2:	fa01 f303 	lsl.w	r3, r1, r3
 80023a6:	43d9      	mvns	r1, r3
 80023a8:	687b      	ldr	r3, [r7, #4]
 80023aa:	400b      	ands	r3, r1
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 80023ac:	4313      	orrs	r3, r2
         );
}
 80023ae:	4618      	mov	r0, r3
 80023b0:	3724      	adds	r7, #36	; 0x24
 80023b2:	46bd      	mov	sp, r7
 80023b4:	bc80      	pop	{r7}
 80023b6:	4770      	bx	lr

080023b8 <HAL_NVIC_SetPriorityGrouping>:
  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. 
  *         The pending IRQ priority will be managed only by the subpriority. 
  * @retval None
  */
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
 80023b8:	b580      	push	{r7, lr}
 80023ba:	b082      	sub	sp, #8
 80023bc:	af00      	add	r7, sp, #0
 80023be:	6078      	str	r0, [r7, #4]
  /* Check the parameters */
  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
  
  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
  NVIC_SetPriorityGrouping(PriorityGroup);
 80023c0:	6878      	ldr	r0, [r7, #4]
 80023c2:	f7ff ff4f 	bl	8002264 <__NVIC_SetPriorityGrouping>
}
 80023c6:	bf00      	nop
 80023c8:	3708      	adds	r7, #8
 80023ca:	46bd      	mov	sp, r7
 80023cc:	bd80      	pop	{r7, pc}

080023ce <HAL_NVIC_SetPriority>:
  *         This parameter can be a value between 0 and 15
  *         A lower priority value indicates a higher priority.          
  * @retval None
  */
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{ 
 80023ce:	b580      	push	{r7, lr}
 80023d0:	b086      	sub	sp, #24
 80023d2:	af00      	add	r7, sp, #0
 80023d4:	4603      	mov	r3, r0
 80023d6:	60b9      	str	r1, [r7, #8]
 80023d8:	607a      	str	r2, [r7, #4]
 80023da:	73fb      	strb	r3, [r7, #15]
  uint32_t prioritygroup = 0x00U;
 80023dc:	2300      	movs	r3, #0
 80023de:	617b      	str	r3, [r7, #20]
  
  /* Check the parameters */
  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
  
  prioritygroup = NVIC_GetPriorityGrouping();
 80023e0:	f7ff ff64 	bl	80022ac <__NVIC_GetPriorityGrouping>
 80023e4:	6178      	str	r0, [r7, #20]
  
  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
 80023e6:	687a      	ldr	r2, [r7, #4]
 80023e8:	68b9      	ldr	r1, [r7, #8]
 80023ea:	6978      	ldr	r0, [r7, #20]
 80023ec:	f7ff ffb2 	bl	8002354 <NVIC_EncodePriority>
 80023f0:	4602      	mov	r2, r0
 80023f2:	f997 300f 	ldrsb.w	r3, [r7, #15]
 80023f6:	4611      	mov	r1, r2
 80023f8:	4618      	mov	r0, r3
 80023fa:	f7ff ff81 	bl	8002300 <__NVIC_SetPriority>
}
 80023fe:	bf00      	nop
 8002400:	3718      	adds	r7, #24
 8002402:	46bd      	mov	sp, r7
 8002404:	bd80      	pop	{r7, pc}

08002406 <HAL_NVIC_EnableIRQ>:
  *         This parameter can be an enumerator of IRQn_Type enumeration
  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
  * @retval None
  */
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
 8002406:	b580      	push	{r7, lr}
 8002408:	b082      	sub	sp, #8
 800240a:	af00      	add	r7, sp, #0
 800240c:	4603      	mov	r3, r0
 800240e:	71fb      	strb	r3, [r7, #7]
  /* Check the parameters */
  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));

  /* Enable interrupt */
  NVIC_EnableIRQ(IRQn);
 8002410:	f997 3007 	ldrsb.w	r3, [r7, #7]
 8002414:	4618      	mov	r0, r3
 8002416:	f7ff ff57 	bl	80022c8 <__NVIC_EnableIRQ>
}
 800241a:	bf00      	nop
 800241c:	3708      	adds	r7, #8
 800241e:	46bd      	mov	sp, r7
 8002420:	bd80      	pop	{r7, pc}
	...

08002424 <HAL_DMA_Init>:
  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
  *               the configuration information for the specified DMA Channel.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
{
 8002424:	b480      	push	{r7}
 8002426:	b085      	sub	sp, #20
 8002428:	af00      	add	r7, sp, #0
 800242a:	6078      	str	r0, [r7, #4]
  uint32_t tmp = 0U;
 800242c:	2300      	movs	r3, #0
 800242e:	60fb      	str	r3, [r7, #12]

  /* Check the DMA handle allocation */
  if(hdma == NULL)
 8002430:	687b      	ldr	r3, [r7, #4]
 8002432:	2b00      	cmp	r3, #0
 8002434:	d101      	bne.n	800243a <HAL_DMA_Init+0x16>
  {
    return HAL_ERROR;
 8002436:	2301      	movs	r3, #1
 8002438:	e043      	b.n	80024c2 <HAL_DMA_Init+0x9e>
    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
    hdma->DmaBaseAddress = DMA2;
  }
#else
  /* DMA1 */
  hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
 800243a:	687b      	ldr	r3, [r7, #4]
 800243c:	681b      	ldr	r3, [r3, #0]
 800243e:	461a      	mov	r2, r3
 8002440:	4b22      	ldr	r3, [pc, #136]	; (80024cc <HAL_DMA_Init+0xa8>)
 8002442:	4413      	add	r3, r2
 8002444:	4a22      	ldr	r2, [pc, #136]	; (80024d0 <HAL_DMA_Init+0xac>)
 8002446:	fba2 2303 	umull	r2, r3, r2, r3
 800244a:	091b      	lsrs	r3, r3, #4
 800244c:	009a      	lsls	r2, r3, #2
 800244e:	687b      	ldr	r3, [r7, #4]
 8002450:	641a      	str	r2, [r3, #64]	; 0x40
  hdma->DmaBaseAddress = DMA1;
 8002452:	687b      	ldr	r3, [r7, #4]
 8002454:	4a1f      	ldr	r2, [pc, #124]	; (80024d4 <HAL_DMA_Init+0xb0>)
 8002456:	63da      	str	r2, [r3, #60]	; 0x3c
#endif /* DMA2 */

  /* Change DMA peripheral state */
  hdma->State = HAL_DMA_STATE_BUSY;
 8002458:	687b      	ldr	r3, [r7, #4]
 800245a:	2202      	movs	r2, #2
 800245c:	f883 2021 	strb.w	r2, [r3, #33]	; 0x21

  /* Get the CR register value */
  tmp = hdma->Instance->CCR;
 8002460:	687b      	ldr	r3, [r7, #4]
 8002462:	681b      	ldr	r3, [r3, #0]
 8002464:	681b      	ldr	r3, [r3, #0]
 8002466:	60fb      	str	r3, [r7, #12]

  /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
  tmp &= ((uint32_t)~(DMA_CCR_PL    | DMA_CCR_MSIZE  | DMA_CCR_PSIZE  | \
 8002468:	68fb      	ldr	r3, [r7, #12]
 800246a:	f423 537f 	bic.w	r3, r3, #16320	; 0x3fc0
 800246e:	f023 0330 	bic.w	r3, r3, #48	; 0x30
 8002472:	60fb      	str	r3, [r7, #12]
                      DMA_CCR_MINC  | DMA_CCR_PINC   | DMA_CCR_CIRC   | \
                      DMA_CCR_DIR));

  /* Prepare the DMA Channel configuration */
  tmp |=  hdma->Init.Direction        |
 8002474:	687b      	ldr	r3, [r7, #4]
 8002476:	685a      	ldr	r2, [r3, #4]
          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
 8002478:	687b      	ldr	r3, [r7, #4]
 800247a:	689b      	ldr	r3, [r3, #8]
  tmp |=  hdma->Init.Direction        |
 800247c:	431a      	orrs	r2, r3
          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
 800247e:	687b      	ldr	r3, [r7, #4]
 8002480:	68db      	ldr	r3, [r3, #12]
 8002482:	431a      	orrs	r2, r3
          hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
 8002484:	687b      	ldr	r3, [r7, #4]
 8002486:	691b      	ldr	r3, [r3, #16]
          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
 8002488:	431a      	orrs	r2, r3
          hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
 800248a:	687b      	ldr	r3, [r7, #4]
 800248c:	695b      	ldr	r3, [r3, #20]
 800248e:	431a      	orrs	r2, r3
          hdma->Init.Mode                | hdma->Init.Priority;
 8002490:	687b      	ldr	r3, [r7, #4]
 8002492:	699b      	ldr	r3, [r3, #24]
          hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
 8002494:	431a      	orrs	r2, r3
          hdma->Init.Mode                | hdma->Init.Priority;
 8002496:	687b      	ldr	r3, [r7, #4]
 8002498:	69db      	ldr	r3, [r3, #28]
 800249a:	4313      	orrs	r3, r2
  tmp |=  hdma->Init.Direction        |
 800249c:	68fa      	ldr	r2, [r7, #12]
 800249e:	4313      	orrs	r3, r2
 80024a0:	60fb      	str	r3, [r7, #12]

  /* Write to DMA Channel CR register */
  hdma->Instance->CCR = tmp;
 80024a2:	687b      	ldr	r3, [r7, #4]
 80024a4:	681b      	ldr	r3, [r3, #0]
 80024a6:	68fa      	ldr	r2, [r7, #12]
 80024a8:	601a      	str	r2, [r3, #0]

  /* Initialise the error code */
  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
 80024aa:	687b      	ldr	r3, [r7, #4]
 80024ac:	2200      	movs	r2, #0
 80024ae:	639a      	str	r2, [r3, #56]	; 0x38

  /* Initialize the DMA state*/
  hdma->State = HAL_DMA_STATE_READY;
 80024b0:	687b      	ldr	r3, [r7, #4]
 80024b2:	2201      	movs	r2, #1
 80024b4:	f883 2021 	strb.w	r2, [r3, #33]	; 0x21
  /* Allocate lock resource and initialize it */
  hdma->Lock = HAL_UNLOCKED;
 80024b8:	687b      	ldr	r3, [r7, #4]
 80024ba:	2200      	movs	r2, #0
 80024bc:	f883 2020 	strb.w	r2, [r3, #32]

  return HAL_OK;
 80024c0:	2300      	movs	r3, #0
}
 80024c2:	4618      	mov	r0, r3
 80024c4:	3714      	adds	r7, #20
 80024c6:	46bd      	mov	sp, r7
 80024c8:	bc80      	pop	{r7}
 80024ca:	4770      	bx	lr
 80024cc:	bffdfff8 	.word	0xbffdfff8
 80024d0:	cccccccd 	.word	0xcccccccd
 80024d4:	40020000 	.word	0x40020000

080024d8 <HAL_DMA_Start_IT>:
  * @param  DstAddress: The destination memory Buffer address
  * @param  DataLength: The length of data to be transferred from source to destination
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
 80024d8:	b580      	push	{r7, lr}
 80024da:	b086      	sub	sp, #24
 80024dc:	af00      	add	r7, sp, #0
 80024de:	60f8      	str	r0, [r7, #12]
 80024e0:	60b9      	str	r1, [r7, #8]
 80024e2:	607a      	str	r2, [r7, #4]
 80024e4:	603b      	str	r3, [r7, #0]
  HAL_StatusTypeDef status = HAL_OK;
 80024e6:	2300      	movs	r3, #0
 80024e8:	75fb      	strb	r3, [r7, #23]

  /* Check the parameters */
  assert_param(IS_DMA_BUFFER_SIZE(DataLength));

  /* Process locked */
  __HAL_LOCK(hdma);
 80024ea:	68fb      	ldr	r3, [r7, #12]
 80024ec:	f893 3020 	ldrb.w	r3, [r3, #32]
 80024f0:	2b01      	cmp	r3, #1
 80024f2:	d101      	bne.n	80024f8 <HAL_DMA_Start_IT+0x20>
 80024f4:	2302      	movs	r3, #2
 80024f6:	e04a      	b.n	800258e <HAL_DMA_Start_IT+0xb6>
 80024f8:	68fb      	ldr	r3, [r7, #12]
 80024fa:	2201      	movs	r2, #1
 80024fc:	f883 2020 	strb.w	r2, [r3, #32]
  
  if(HAL_DMA_STATE_READY == hdma->State)
 8002500:	68fb      	ldr	r3, [r7, #12]
 8002502:	f893 3021 	ldrb.w	r3, [r3, #33]	; 0x21
 8002506:	2b01      	cmp	r3, #1
 8002508:	d13a      	bne.n	8002580 <HAL_DMA_Start_IT+0xa8>
  {
    /* Change DMA peripheral state */
    hdma->State = HAL_DMA_STATE_BUSY;
 800250a:	68fb      	ldr	r3, [r7, #12]
 800250c:	2202      	movs	r2, #2
 800250e:	f883 2021 	strb.w	r2, [r3, #33]	; 0x21
    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
 8002512:	68fb      	ldr	r3, [r7, #12]
 8002514:	2200      	movs	r2, #0
 8002516:	639a      	str	r2, [r3, #56]	; 0x38
    
    /* Disable the peripheral */
    __HAL_DMA_DISABLE(hdma);
 8002518:	68fb      	ldr	r3, [r7, #12]
 800251a:	681b      	ldr	r3, [r3, #0]
 800251c:	681a      	ldr	r2, [r3, #0]
 800251e:	68fb      	ldr	r3, [r7, #12]
 8002520:	681b      	ldr	r3, [r3, #0]
 8002522:	f022 0201 	bic.w	r2, r2, #1
 8002526:	601a      	str	r2, [r3, #0]
    
    /* Configure the source, destination address and the data length & clear flags*/
    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
 8002528:	683b      	ldr	r3, [r7, #0]
 800252a:	687a      	ldr	r2, [r7, #4]
 800252c:	68b9      	ldr	r1, [r7, #8]
 800252e:	68f8      	ldr	r0, [r7, #12]
 8002530:	f000 f9ae 	bl	8002890 <DMA_SetConfig>
    
    /* Enable the transfer complete interrupt */
    /* Enable the transfer Error interrupt */
    if(NULL != hdma->XferHalfCpltCallback)
 8002534:	68fb      	ldr	r3, [r7, #12]
 8002536:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 8002538:	2b00      	cmp	r3, #0
 800253a:	d008      	beq.n	800254e <HAL_DMA_Start_IT+0x76>
    {
      /* Enable the Half transfer complete interrupt as well */
      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
 800253c:	68fb      	ldr	r3, [r7, #12]
 800253e:	681b      	ldr	r3, [r3, #0]
 8002540:	681a      	ldr	r2, [r3, #0]
 8002542:	68fb      	ldr	r3, [r7, #12]
 8002544:	681b      	ldr	r3, [r3, #0]
 8002546:	f042 020e 	orr.w	r2, r2, #14
 800254a:	601a      	str	r2, [r3, #0]
 800254c:	e00f      	b.n	800256e <HAL_DMA_Start_IT+0x96>
    }
    else
    {
      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
 800254e:	68fb      	ldr	r3, [r7, #12]
 8002550:	681b      	ldr	r3, [r3, #0]
 8002552:	681a      	ldr	r2, [r3, #0]
 8002554:	68fb      	ldr	r3, [r7, #12]
 8002556:	681b      	ldr	r3, [r3, #0]
 8002558:	f022 0204 	bic.w	r2, r2, #4
 800255c:	601a      	str	r2, [r3, #0]
      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
 800255e:	68fb      	ldr	r3, [r7, #12]
 8002560:	681b      	ldr	r3, [r3, #0]
 8002562:	681a      	ldr	r2, [r3, #0]
 8002564:	68fb      	ldr	r3, [r7, #12]
 8002566:	681b      	ldr	r3, [r3, #0]
 8002568:	f042 020a 	orr.w	r2, r2, #10
 800256c:	601a      	str	r2, [r3, #0]
    }
    /* Enable the Peripheral */
    __HAL_DMA_ENABLE(hdma);
 800256e:	68fb      	ldr	r3, [r7, #12]
 8002570:	681b      	ldr	r3, [r3, #0]
 8002572:	681a      	ldr	r2, [r3, #0]
 8002574:	68fb      	ldr	r3, [r7, #12]
 8002576:	681b      	ldr	r3, [r3, #0]
 8002578:	f042 0201 	orr.w	r2, r2, #1
 800257c:	601a      	str	r2, [r3, #0]
 800257e:	e005      	b.n	800258c <HAL_DMA_Start_IT+0xb4>
  }
  else
  {      
    /* Process Unlocked */
    __HAL_UNLOCK(hdma); 
 8002580:	68fb      	ldr	r3, [r7, #12]
 8002582:	2200      	movs	r2, #0
 8002584:	f883 2020 	strb.w	r2, [r3, #32]

    /* Remain BUSY */
    status = HAL_BUSY;
 8002588:	2302      	movs	r3, #2
 800258a:	75fb      	strb	r3, [r7, #23]
  }    
  return status;
 800258c:	7dfb      	ldrb	r3, [r7, #23]
}
 800258e:	4618      	mov	r0, r3
 8002590:	3718      	adds	r7, #24
 8002592:	46bd      	mov	sp, r7
 8002594:	bd80      	pop	{r7, pc}
	...

08002598 <HAL_DMA_Abort_IT>:
  * @param  hdma  : pointer to a DMA_HandleTypeDef structure that contains
  *                 the configuration information for the specified DMA Channel.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
{  
 8002598:	b580      	push	{r7, lr}
 800259a:	b084      	sub	sp, #16
 800259c:	af00      	add	r7, sp, #0
 800259e:	6078      	str	r0, [r7, #4]
  HAL_StatusTypeDef status = HAL_OK;
 80025a0:	2300      	movs	r3, #0
 80025a2:	73fb      	strb	r3, [r7, #15]
  
  if(HAL_DMA_STATE_BUSY != hdma->State)
 80025a4:	687b      	ldr	r3, [r7, #4]
 80025a6:	f893 3021 	ldrb.w	r3, [r3, #33]	; 0x21
 80025aa:	2b02      	cmp	r3, #2
 80025ac:	d005      	beq.n	80025ba <HAL_DMA_Abort_IT+0x22>
  {
    /* no transfer ongoing */
    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
 80025ae:	687b      	ldr	r3, [r7, #4]
 80025b0:	2204      	movs	r2, #4
 80025b2:	639a      	str	r2, [r3, #56]	; 0x38
        
    status = HAL_ERROR;
 80025b4:	2301      	movs	r3, #1
 80025b6:	73fb      	strb	r3, [r7, #15]
 80025b8:	e051      	b.n	800265e <HAL_DMA_Abort_IT+0xc6>
  }
  else
  { 
    /* Disable DMA IT */
    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
 80025ba:	687b      	ldr	r3, [r7, #4]
 80025bc:	681b      	ldr	r3, [r3, #0]
 80025be:	681a      	ldr	r2, [r3, #0]
 80025c0:	687b      	ldr	r3, [r7, #4]
 80025c2:	681b      	ldr	r3, [r3, #0]
 80025c4:	f022 020e 	bic.w	r2, r2, #14
 80025c8:	601a      	str	r2, [r3, #0]

    /* Disable the channel */
    __HAL_DMA_DISABLE(hdma);
 80025ca:	687b      	ldr	r3, [r7, #4]
 80025cc:	681b      	ldr	r3, [r3, #0]
 80025ce:	681a      	ldr	r2, [r3, #0]
 80025d0:	687b      	ldr	r3, [r7, #4]
 80025d2:	681b      	ldr	r3, [r3, #0]
 80025d4:	f022 0201 	bic.w	r2, r2, #1
 80025d8:	601a      	str	r2, [r3, #0]

    /* Clear all flags */
    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma));
 80025da:	687b      	ldr	r3, [r7, #4]
 80025dc:	681b      	ldr	r3, [r3, #0]
 80025de:	4a22      	ldr	r2, [pc, #136]	; (8002668 <HAL_DMA_Abort_IT+0xd0>)
 80025e0:	4293      	cmp	r3, r2
 80025e2:	d029      	beq.n	8002638 <HAL_DMA_Abort_IT+0xa0>
 80025e4:	687b      	ldr	r3, [r7, #4]
 80025e6:	681b      	ldr	r3, [r3, #0]
 80025e8:	4a20      	ldr	r2, [pc, #128]	; (800266c <HAL_DMA_Abort_IT+0xd4>)
 80025ea:	4293      	cmp	r3, r2
 80025ec:	d022      	beq.n	8002634 <HAL_DMA_Abort_IT+0x9c>
 80025ee:	687b      	ldr	r3, [r7, #4]
 80025f0:	681b      	ldr	r3, [r3, #0]
 80025f2:	4a1f      	ldr	r2, [pc, #124]	; (8002670 <HAL_DMA_Abort_IT+0xd8>)
 80025f4:	4293      	cmp	r3, r2
 80025f6:	d01a      	beq.n	800262e <HAL_DMA_Abort_IT+0x96>
 80025f8:	687b      	ldr	r3, [r7, #4]
 80025fa:	681b      	ldr	r3, [r3, #0]
 80025fc:	4a1d      	ldr	r2, [pc, #116]	; (8002674 <HAL_DMA_Abort_IT+0xdc>)
 80025fe:	4293      	cmp	r3, r2
 8002600:	d012      	beq.n	8002628 <HAL_DMA_Abort_IT+0x90>
 8002602:	687b      	ldr	r3, [r7, #4]
 8002604:	681b      	ldr	r3, [r3, #0]
 8002606:	4a1c      	ldr	r2, [pc, #112]	; (8002678 <HAL_DMA_Abort_IT+0xe0>)
 8002608:	4293      	cmp	r3, r2
 800260a:	d00a      	beq.n	8002622 <HAL_DMA_Abort_IT+0x8a>
 800260c:	687b      	ldr	r3, [r7, #4]
 800260e:	681b      	ldr	r3, [r3, #0]
 8002610:	4a1a      	ldr	r2, [pc, #104]	; (800267c <HAL_DMA_Abort_IT+0xe4>)
 8002612:	4293      	cmp	r3, r2
 8002614:	d102      	bne.n	800261c <HAL_DMA_Abort_IT+0x84>
 8002616:	f44f 1380 	mov.w	r3, #1048576	; 0x100000
 800261a:	e00e      	b.n	800263a <HAL_DMA_Abort_IT+0xa2>
 800261c:	f04f 7380 	mov.w	r3, #16777216	; 0x1000000
 8002620:	e00b      	b.n	800263a <HAL_DMA_Abort_IT+0xa2>
 8002622:	f44f 3380 	mov.w	r3, #65536	; 0x10000
 8002626:	e008      	b.n	800263a <HAL_DMA_Abort_IT+0xa2>
 8002628:	f44f 5380 	mov.w	r3, #4096	; 0x1000
 800262c:	e005      	b.n	800263a <HAL_DMA_Abort_IT+0xa2>
 800262e:	f44f 7380 	mov.w	r3, #256	; 0x100
 8002632:	e002      	b.n	800263a <HAL_DMA_Abort_IT+0xa2>
 8002634:	2310      	movs	r3, #16
 8002636:	e000      	b.n	800263a <HAL_DMA_Abort_IT+0xa2>
 8002638:	2301      	movs	r3, #1
 800263a:	4a11      	ldr	r2, [pc, #68]	; (8002680 <HAL_DMA_Abort_IT+0xe8>)
 800263c:	6053      	str	r3, [r2, #4]

    /* Change the DMA state */
    hdma->State = HAL_DMA_STATE_READY;
 800263e:	687b      	ldr	r3, [r7, #4]
 8002640:	2201      	movs	r2, #1
 8002642:	f883 2021 	strb.w	r2, [r3, #33]	; 0x21

    /* Process Unlocked */
    __HAL_UNLOCK(hdma);
 8002646:	687b      	ldr	r3, [r7, #4]
 8002648:	2200      	movs	r2, #0
 800264a:	f883 2020 	strb.w	r2, [r3, #32]

    /* Call User Abort callback */
    if(hdma->XferAbortCallback != NULL)
 800264e:	687b      	ldr	r3, [r7, #4]
 8002650:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 8002652:	2b00      	cmp	r3, #0
 8002654:	d003      	beq.n	800265e <HAL_DMA_Abort_IT+0xc6>
    {
      hdma->XferAbortCallback(hdma);
 8002656:	687b      	ldr	r3, [r7, #4]
 8002658:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 800265a:	6878      	ldr	r0, [r7, #4]
 800265c:	4798      	blx	r3
    } 
  }
  return status;
 800265e:	7bfb      	ldrb	r3, [r7, #15]
}
 8002660:	4618      	mov	r0, r3
 8002662:	3710      	adds	r7, #16
 8002664:	46bd      	mov	sp, r7
 8002666:	bd80      	pop	{r7, pc}
 8002668:	40020008 	.word	0x40020008
 800266c:	4002001c 	.word	0x4002001c
 8002670:	40020030 	.word	0x40020030
 8002674:	40020044 	.word	0x40020044
 8002678:	40020058 	.word	0x40020058
 800267c:	4002006c 	.word	0x4002006c
 8002680:	40020000 	.word	0x40020000

08002684 <HAL_DMA_IRQHandler>:
  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
  *               the configuration information for the specified DMA Channel.  
  * @retval None
  */
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
{
 8002684:	b580      	push	{r7, lr}
 8002686:	b084      	sub	sp, #16
 8002688:	af00      	add	r7, sp, #0
 800268a:	6078      	str	r0, [r7, #4]
  uint32_t flag_it = hdma->DmaBaseAddress->ISR;
 800268c:	687b      	ldr	r3, [r7, #4]
 800268e:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
 8002690:	681b      	ldr	r3, [r3, #0]
 8002692:	60fb      	str	r3, [r7, #12]
  uint32_t source_it = hdma->Instance->CCR;
 8002694:	687b      	ldr	r3, [r7, #4]
 8002696:	681b      	ldr	r3, [r3, #0]
 8002698:	681b      	ldr	r3, [r3, #0]
 800269a:	60bb      	str	r3, [r7, #8]
  
  /* Half Transfer Complete Interrupt management ******************************/
  if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET))
 800269c:	687b      	ldr	r3, [r7, #4]
 800269e:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 80026a0:	2204      	movs	r2, #4
 80026a2:	409a      	lsls	r2, r3
 80026a4:	68fb      	ldr	r3, [r7, #12]
 80026a6:	4013      	ands	r3, r2
 80026a8:	2b00      	cmp	r3, #0
 80026aa:	d04f      	beq.n	800274c <HAL_DMA_IRQHandler+0xc8>
 80026ac:	68bb      	ldr	r3, [r7, #8]
 80026ae:	f003 0304 	and.w	r3, r3, #4
 80026b2:	2b00      	cmp	r3, #0
 80026b4:	d04a      	beq.n	800274c <HAL_DMA_IRQHandler+0xc8>
  {
    /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
    if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
 80026b6:	687b      	ldr	r3, [r7, #4]
 80026b8:	681b      	ldr	r3, [r3, #0]
 80026ba:	681b      	ldr	r3, [r3, #0]
 80026bc:	f003 0320 	and.w	r3, r3, #32
 80026c0:	2b00      	cmp	r3, #0
 80026c2:	d107      	bne.n	80026d4 <HAL_DMA_IRQHandler+0x50>
    {
      /* Disable the half transfer interrupt */
      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
 80026c4:	687b      	ldr	r3, [r7, #4]
 80026c6:	681b      	ldr	r3, [r3, #0]
 80026c8:	681a      	ldr	r2, [r3, #0]
 80026ca:	687b      	ldr	r3, [r7, #4]
 80026cc:	681b      	ldr	r3, [r3, #0]
 80026ce:	f022 0204 	bic.w	r2, r2, #4
 80026d2:	601a      	str	r2, [r3, #0]
    }
    /* Clear the half transfer complete flag */
    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
 80026d4:	687b      	ldr	r3, [r7, #4]
 80026d6:	681b      	ldr	r3, [r3, #0]
 80026d8:	4a66      	ldr	r2, [pc, #408]	; (8002874 <HAL_DMA_IRQHandler+0x1f0>)
 80026da:	4293      	cmp	r3, r2
 80026dc:	d029      	beq.n	8002732 <HAL_DMA_IRQHandler+0xae>
 80026de:	687b      	ldr	r3, [r7, #4]
 80026e0:	681b      	ldr	r3, [r3, #0]
 80026e2:	4a65      	ldr	r2, [pc, #404]	; (8002878 <HAL_DMA_IRQHandler+0x1f4>)
 80026e4:	4293      	cmp	r3, r2
 80026e6:	d022      	beq.n	800272e <HAL_DMA_IRQHandler+0xaa>
 80026e8:	687b      	ldr	r3, [r7, #4]
 80026ea:	681b      	ldr	r3, [r3, #0]
 80026ec:	4a63      	ldr	r2, [pc, #396]	; (800287c <HAL_DMA_IRQHandler+0x1f8>)
 80026ee:	4293      	cmp	r3, r2
 80026f0:	d01a      	beq.n	8002728 <HAL_DMA_IRQHandler+0xa4>
 80026f2:	687b      	ldr	r3, [r7, #4]
 80026f4:	681b      	ldr	r3, [r3, #0]
 80026f6:	4a62      	ldr	r2, [pc, #392]	; (8002880 <HAL_DMA_IRQHandler+0x1fc>)
 80026f8:	4293      	cmp	r3, r2
 80026fa:	d012      	beq.n	8002722 <HAL_DMA_IRQHandler+0x9e>
 80026fc:	687b      	ldr	r3, [r7, #4]
 80026fe:	681b      	ldr	r3, [r3, #0]
 8002700:	4a60      	ldr	r2, [pc, #384]	; (8002884 <HAL_DMA_IRQHandler+0x200>)
 8002702:	4293      	cmp	r3, r2
 8002704:	d00a      	beq.n	800271c <HAL_DMA_IRQHandler+0x98>
 8002706:	687b      	ldr	r3, [r7, #4]
 8002708:	681b      	ldr	r3, [r3, #0]
 800270a:	4a5f      	ldr	r2, [pc, #380]	; (8002888 <HAL_DMA_IRQHandler+0x204>)
 800270c:	4293      	cmp	r3, r2
 800270e:	d102      	bne.n	8002716 <HAL_DMA_IRQHandler+0x92>
 8002710:	f44f 0380 	mov.w	r3, #4194304	; 0x400000
 8002714:	e00e      	b.n	8002734 <HAL_DMA_IRQHandler+0xb0>
 8002716:	f04f 6380 	mov.w	r3, #67108864	; 0x4000000
 800271a:	e00b      	b.n	8002734 <HAL_DMA_IRQHandler+0xb0>
 800271c:	f44f 2380 	mov.w	r3, #262144	; 0x40000
 8002720:	e008      	b.n	8002734 <HAL_DMA_IRQHandler+0xb0>
 8002722:	f44f 4380 	mov.w	r3, #16384	; 0x4000
 8002726:	e005      	b.n	8002734 <HAL_DMA_IRQHandler+0xb0>
 8002728:	f44f 6380 	mov.w	r3, #1024	; 0x400
 800272c:	e002      	b.n	8002734 <HAL_DMA_IRQHandler+0xb0>
 800272e:	2340      	movs	r3, #64	; 0x40
 8002730:	e000      	b.n	8002734 <HAL_DMA_IRQHandler+0xb0>
 8002732:	2304      	movs	r3, #4
 8002734:	4a55      	ldr	r2, [pc, #340]	; (800288c <HAL_DMA_IRQHandler+0x208>)
 8002736:	6053      	str	r3, [r2, #4]

    /* DMA peripheral state is not updated in Half Transfer */
    /* but in Transfer Complete case */

    if(hdma->XferHalfCpltCallback != NULL)
 8002738:	687b      	ldr	r3, [r7, #4]
 800273a:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 800273c:	2b00      	cmp	r3, #0
 800273e:	f000 8094 	beq.w	800286a <HAL_DMA_IRQHandler+0x1e6>
    {
      /* Half transfer callback */
      hdma->XferHalfCpltCallback(hdma);
 8002742:	687b      	ldr	r3, [r7, #4]
 8002744:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 8002746:	6878      	ldr	r0, [r7, #4]
 8002748:	4798      	blx	r3
    if(hdma->XferHalfCpltCallback != NULL)
 800274a:	e08e      	b.n	800286a <HAL_DMA_IRQHandler+0x1e6>
    }
  }

  /* Transfer Complete Interrupt management ***********************************/
  else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET))
 800274c:	687b      	ldr	r3, [r7, #4]
 800274e:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8002750:	2202      	movs	r2, #2
 8002752:	409a      	lsls	r2, r3
 8002754:	68fb      	ldr	r3, [r7, #12]
 8002756:	4013      	ands	r3, r2
 8002758:	2b00      	cmp	r3, #0
 800275a:	d056      	beq.n	800280a <HAL_DMA_IRQHandler+0x186>
 800275c:	68bb      	ldr	r3, [r7, #8]
 800275e:	f003 0302 	and.w	r3, r3, #2
 8002762:	2b00      	cmp	r3, #0
 8002764:	d051      	beq.n	800280a <HAL_DMA_IRQHandler+0x186>
  {
    if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
 8002766:	687b      	ldr	r3, [r7, #4]
 8002768:	681b      	ldr	r3, [r3, #0]
 800276a:	681b      	ldr	r3, [r3, #0]
 800276c:	f003 0320 	and.w	r3, r3, #32
 8002770:	2b00      	cmp	r3, #0
 8002772:	d10b      	bne.n	800278c <HAL_DMA_IRQHandler+0x108>
    {
      /* Disable the transfer complete and error interrupt */
      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);  
 8002774:	687b      	ldr	r3, [r7, #4]
 8002776:	681b      	ldr	r3, [r3, #0]
 8002778:	681a      	ldr	r2, [r3, #0]
 800277a:	687b      	ldr	r3, [r7, #4]
 800277c:	681b      	ldr	r3, [r3, #0]
 800277e:	f022 020a 	bic.w	r2, r2, #10
 8002782:	601a      	str	r2, [r3, #0]

      /* Change the DMA state */
      hdma->State = HAL_DMA_STATE_READY;
 8002784:	687b      	ldr	r3, [r7, #4]
 8002786:	2201      	movs	r2, #1
 8002788:	f883 2021 	strb.w	r2, [r3, #33]	; 0x21
    }
    /* Clear the transfer complete flag */
      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
 800278c:	687b      	ldr	r3, [r7, #4]
 800278e:	681b      	ldr	r3, [r3, #0]
 8002790:	4a38      	ldr	r2, [pc, #224]	; (8002874 <HAL_DMA_IRQHandler+0x1f0>)
 8002792:	4293      	cmp	r3, r2
 8002794:	d029      	beq.n	80027ea <HAL_DMA_IRQHandler+0x166>
 8002796:	687b      	ldr	r3, [r7, #4]
 8002798:	681b      	ldr	r3, [r3, #0]
 800279a:	4a37      	ldr	r2, [pc, #220]	; (8002878 <HAL_DMA_IRQHandler+0x1f4>)
 800279c:	4293      	cmp	r3, r2
 800279e:	d022      	beq.n	80027e6 <HAL_DMA_IRQHandler+0x162>
 80027a0:	687b      	ldr	r3, [r7, #4]
 80027a2:	681b      	ldr	r3, [r3, #0]
 80027a4:	4a35      	ldr	r2, [pc, #212]	; (800287c <HAL_DMA_IRQHandler+0x1f8>)
 80027a6:	4293      	cmp	r3, r2
 80027a8:	d01a      	beq.n	80027e0 <HAL_DMA_IRQHandler+0x15c>
 80027aa:	687b      	ldr	r3, [r7, #4]
 80027ac:	681b      	ldr	r3, [r3, #0]
 80027ae:	4a34      	ldr	r2, [pc, #208]	; (8002880 <HAL_DMA_IRQHandler+0x1fc>)
 80027b0:	4293      	cmp	r3, r2
 80027b2:	d012      	beq.n	80027da <HAL_DMA_IRQHandler+0x156>
 80027b4:	687b      	ldr	r3, [r7, #4]
 80027b6:	681b      	ldr	r3, [r3, #0]
 80027b8:	4a32      	ldr	r2, [pc, #200]	; (8002884 <HAL_DMA_IRQHandler+0x200>)
 80027ba:	4293      	cmp	r3, r2
 80027bc:	d00a      	beq.n	80027d4 <HAL_DMA_IRQHandler+0x150>
 80027be:	687b      	ldr	r3, [r7, #4]
 80027c0:	681b      	ldr	r3, [r3, #0]
 80027c2:	4a31      	ldr	r2, [pc, #196]	; (8002888 <HAL_DMA_IRQHandler+0x204>)
 80027c4:	4293      	cmp	r3, r2
 80027c6:	d102      	bne.n	80027ce <HAL_DMA_IRQHandler+0x14a>
 80027c8:	f44f 1300 	mov.w	r3, #2097152	; 0x200000
 80027cc:	e00e      	b.n	80027ec <HAL_DMA_IRQHandler+0x168>
 80027ce:	f04f 7300 	mov.w	r3, #33554432	; 0x2000000
 80027d2:	e00b      	b.n	80027ec <HAL_DMA_IRQHandler+0x168>
 80027d4:	f44f 3300 	mov.w	r3, #131072	; 0x20000
 80027d8:	e008      	b.n	80027ec <HAL_DMA_IRQHandler+0x168>
 80027da:	f44f 5300 	mov.w	r3, #8192	; 0x2000
 80027de:	e005      	b.n	80027ec <HAL_DMA_IRQHandler+0x168>
 80027e0:	f44f 7300 	mov.w	r3, #512	; 0x200
 80027e4:	e002      	b.n	80027ec <HAL_DMA_IRQHandler+0x168>
 80027e6:	2320      	movs	r3, #32
 80027e8:	e000      	b.n	80027ec <HAL_DMA_IRQHandler+0x168>
 80027ea:	2302      	movs	r3, #2
 80027ec:	4a27      	ldr	r2, [pc, #156]	; (800288c <HAL_DMA_IRQHandler+0x208>)
 80027ee:	6053      	str	r3, [r2, #4]

    /* Process Unlocked */
    __HAL_UNLOCK(hdma);
 80027f0:	687b      	ldr	r3, [r7, #4]
 80027f2:	2200      	movs	r2, #0
 80027f4:	f883 2020 	strb.w	r2, [r3, #32]

    if(hdma->XferCpltCallback != NULL)
 80027f8:	687b      	ldr	r3, [r7, #4]
 80027fa:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 80027fc:	2b00      	cmp	r3, #0
 80027fe:	d034      	beq.n	800286a <HAL_DMA_IRQHandler+0x1e6>
    {
      /* Transfer complete callback */
      hdma->XferCpltCallback(hdma);
 8002800:	687b      	ldr	r3, [r7, #4]
 8002802:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 8002804:	6878      	ldr	r0, [r7, #4]
 8002806:	4798      	blx	r3
    if(hdma->XferCpltCallback != NULL)
 8002808:	e02f      	b.n	800286a <HAL_DMA_IRQHandler+0x1e6>
    }
  }

  /* Transfer Error Interrupt management **************************************/
  else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
 800280a:	687b      	ldr	r3, [r7, #4]
 800280c:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 800280e:	2208      	movs	r2, #8
 8002810:	409a      	lsls	r2, r3
 8002812:	68fb      	ldr	r3, [r7, #12]
 8002814:	4013      	ands	r3, r2
 8002816:	2b00      	cmp	r3, #0
 8002818:	d028      	beq.n	800286c <HAL_DMA_IRQHandler+0x1e8>
 800281a:	68bb      	ldr	r3, [r7, #8]
 800281c:	f003 0308 	and.w	r3, r3, #8
 8002820:	2b00      	cmp	r3, #0
 8002822:	d023      	beq.n	800286c <HAL_DMA_IRQHandler+0x1e8>
  {
    /* When a DMA transfer error occurs */
    /* A hardware clear of its EN bits is performed */
    /* Disable ALL DMA IT */
    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
 8002824:	687b      	ldr	r3, [r7, #4]
 8002826:	681b      	ldr	r3, [r3, #0]
 8002828:	681a      	ldr	r2, [r3, #0]
 800282a:	687b      	ldr	r3, [r7, #4]
 800282c:	681b      	ldr	r3, [r3, #0]
 800282e:	f022 020e 	bic.w	r2, r2, #14
 8002832:	601a      	str	r2, [r3, #0]

    /* Clear all flags */
    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
 8002834:	687b      	ldr	r3, [r7, #4]
 8002836:	6c1a      	ldr	r2, [r3, #64]	; 0x40
 8002838:	687b      	ldr	r3, [r7, #4]
 800283a:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
 800283c:	2101      	movs	r1, #1
 800283e:	fa01 f202 	lsl.w	r2, r1, r2
 8002842:	605a      	str	r2, [r3, #4]

    /* Update error code */
    hdma->ErrorCode = HAL_DMA_ERROR_TE;
 8002844:	687b      	ldr	r3, [r7, #4]
 8002846:	2201      	movs	r2, #1
 8002848:	639a      	str	r2, [r3, #56]	; 0x38

    /* Change the DMA state */
    hdma->State = HAL_DMA_STATE_READY;
 800284a:	687b      	ldr	r3, [r7, #4]
 800284c:	2201      	movs	r2, #1
 800284e:	f883 2021 	strb.w	r2, [r3, #33]	; 0x21

    /* Process Unlocked */
    __HAL_UNLOCK(hdma);
 8002852:	687b      	ldr	r3, [r7, #4]
 8002854:	2200      	movs	r2, #0
 8002856:	f883 2020 	strb.w	r2, [r3, #32]

    if (hdma->XferErrorCallback != NULL)
 800285a:	687b      	ldr	r3, [r7, #4]
 800285c:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 800285e:	2b00      	cmp	r3, #0
 8002860:	d004      	beq.n	800286c <HAL_DMA_IRQHandler+0x1e8>
    {
      /* Transfer error callback */
      hdma->XferErrorCallback(hdma);
 8002862:	687b      	ldr	r3, [r7, #4]
 8002864:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 8002866:	6878      	ldr	r0, [r7, #4]
 8002868:	4798      	blx	r3
    }
  }
  return;
 800286a:	bf00      	nop
 800286c:	bf00      	nop
}
 800286e:	3710      	adds	r7, #16
 8002870:	46bd      	mov	sp, r7
 8002872:	bd80      	pop	{r7, pc}
 8002874:	40020008 	.word	0x40020008
 8002878:	4002001c 	.word	0x4002001c
 800287c:	40020030 	.word	0x40020030
 8002880:	40020044 	.word	0x40020044
 8002884:	40020058 	.word	0x40020058
 8002888:	4002006c 	.word	0x4002006c
 800288c:	40020000 	.word	0x40020000

08002890 <DMA_SetConfig>:
  * @param  DstAddress: The destination memory Buffer address
  * @param  DataLength: The length of data to be transferred from source to destination
  * @retval HAL status
  */
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
 8002890:	b480      	push	{r7}
 8002892:	b085      	sub	sp, #20
 8002894:	af00      	add	r7, sp, #0
 8002896:	60f8      	str	r0, [r7, #12]
 8002898:	60b9      	str	r1, [r7, #8]
 800289a:	607a      	str	r2, [r7, #4]
 800289c:	603b      	str	r3, [r7, #0]
  /* Clear all flags */
  hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
 800289e:	68fb      	ldr	r3, [r7, #12]
 80028a0:	6c1a      	ldr	r2, [r3, #64]	; 0x40
 80028a2:	68fb      	ldr	r3, [r7, #12]
 80028a4:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
 80028a6:	2101      	movs	r1, #1
 80028a8:	fa01 f202 	lsl.w	r2, r1, r2
 80028ac:	605a      	str	r2, [r3, #4]

  /* Configure DMA Channel data length */
  hdma->Instance->CNDTR = DataLength;
 80028ae:	68fb      	ldr	r3, [r7, #12]
 80028b0:	681b      	ldr	r3, [r3, #0]
 80028b2:	683a      	ldr	r2, [r7, #0]
 80028b4:	605a      	str	r2, [r3, #4]

  /* Memory to Peripheral */
  if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
 80028b6:	68fb      	ldr	r3, [r7, #12]
 80028b8:	685b      	ldr	r3, [r3, #4]
 80028ba:	2b10      	cmp	r3, #16
 80028bc:	d108      	bne.n	80028d0 <DMA_SetConfig+0x40>
  {
    /* Configure DMA Channel destination address */
    hdma->Instance->CPAR = DstAddress;
 80028be:	68fb      	ldr	r3, [r7, #12]
 80028c0:	681b      	ldr	r3, [r3, #0]
 80028c2:	687a      	ldr	r2, [r7, #4]
 80028c4:	609a      	str	r2, [r3, #8]

    /* Configure DMA Channel source address */
    hdma->Instance->CMAR = SrcAddress;
 80028c6:	68fb      	ldr	r3, [r7, #12]
 80028c8:	681b      	ldr	r3, [r3, #0]
 80028ca:	68ba      	ldr	r2, [r7, #8]
 80028cc:	60da      	str	r2, [r3, #12]
    hdma->Instance->CPAR = SrcAddress;

    /* Configure DMA Channel destination address */
    hdma->Instance->CMAR = DstAddress;
  }
}
 80028ce:	e007      	b.n	80028e0 <DMA_SetConfig+0x50>
    hdma->Instance->CPAR = SrcAddress;
 80028d0:	68fb      	ldr	r3, [r7, #12]
 80028d2:	681b      	ldr	r3, [r3, #0]
 80028d4:	68ba      	ldr	r2, [r7, #8]
 80028d6:	609a      	str	r2, [r3, #8]
    hdma->Instance->CMAR = DstAddress;
 80028d8:	68fb      	ldr	r3, [r7, #12]
 80028da:	681b      	ldr	r3, [r3, #0]
 80028dc:	687a      	ldr	r2, [r7, #4]
 80028de:	60da      	str	r2, [r3, #12]
}
 80028e0:	bf00      	nop
 80028e2:	3714      	adds	r7, #20
 80028e4:	46bd      	mov	sp, r7
 80028e6:	bc80      	pop	{r7}
 80028e8:	4770      	bx	lr
	...

080028ec <HAL_FLASH_Program>:
  * @param  Data:         Specifies the data to be programmed
  * 
  * @retval HAL_StatusTypeDef HAL Status
  */
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
{
 80028ec:	b5f0      	push	{r4, r5, r6, r7, lr}
 80028ee:	b087      	sub	sp, #28
 80028f0:	af00      	add	r7, sp, #0
 80028f2:	60f8      	str	r0, [r7, #12]
 80028f4:	60b9      	str	r1, [r7, #8]
 80028f6:	e9c7 2300 	strd	r2, r3, [r7]
  HAL_StatusTypeDef status = HAL_ERROR;
 80028fa:	2301      	movs	r3, #1
 80028fc:	75fb      	strb	r3, [r7, #23]
  uint8_t index = 0;
 80028fe:	2300      	movs	r3, #0
 8002900:	75bb      	strb	r3, [r7, #22]
  uint8_t nbiterations = 0;
 8002902:	2300      	movs	r3, #0
 8002904:	757b      	strb	r3, [r7, #21]
  
  /* Process Locked */
  __HAL_LOCK(&pFlash);
 8002906:	4b2f      	ldr	r3, [pc, #188]	; (80029c4 <HAL_FLASH_Program+0xd8>)
 8002908:	7e1b      	ldrb	r3, [r3, #24]
 800290a:	2b01      	cmp	r3, #1
 800290c:	d101      	bne.n	8002912 <HAL_FLASH_Program+0x26>
 800290e:	2302      	movs	r3, #2
 8002910:	e054      	b.n	80029bc <HAL_FLASH_Program+0xd0>
 8002912:	4b2c      	ldr	r3, [pc, #176]	; (80029c4 <HAL_FLASH_Program+0xd8>)
 8002914:	2201      	movs	r2, #1
 8002916:	761a      	strb	r2, [r3, #24]
#if defined(FLASH_BANK2_END)
  if(Address <= FLASH_BANK1_END)
  {
#endif /* FLASH_BANK2_END */
    /* Wait for last operation to be completed */
    status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
 8002918:	f24c 3050 	movw	r0, #50000	; 0xc350
 800291c:	f000 f8a8 	bl	8002a70 <FLASH_WaitForLastOperation>
 8002920:	4603      	mov	r3, r0
 8002922:	75fb      	strb	r3, [r7, #23]
    /* Wait for last operation to be completed */
    status = FLASH_WaitForLastOperationBank2(FLASH_TIMEOUT_VALUE);
  }
#endif /* FLASH_BANK2_END */
  
  if(status == HAL_OK)
 8002924:	7dfb      	ldrb	r3, [r7, #23]
 8002926:	2b00      	cmp	r3, #0
 8002928:	d144      	bne.n	80029b4 <HAL_FLASH_Program+0xc8>
  {
    if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
 800292a:	68fb      	ldr	r3, [r7, #12]
 800292c:	2b01      	cmp	r3, #1
 800292e:	d102      	bne.n	8002936 <HAL_FLASH_Program+0x4a>
    {
      /* Program halfword (16-bit) at a specified address. */
      nbiterations = 1U;
 8002930:	2301      	movs	r3, #1
 8002932:	757b      	strb	r3, [r7, #21]
 8002934:	e007      	b.n	8002946 <HAL_FLASH_Program+0x5a>
    }
    else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
 8002936:	68fb      	ldr	r3, [r7, #12]
 8002938:	2b02      	cmp	r3, #2
 800293a:	d102      	bne.n	8002942 <HAL_FLASH_Program+0x56>
    {
      /* Program word (32-bit = 2*16-bit) at a specified address. */
      nbiterations = 2U;
 800293c:	2302      	movs	r3, #2
 800293e:	757b      	strb	r3, [r7, #21]
 8002940:	e001      	b.n	8002946 <HAL_FLASH_Program+0x5a>
    }
    else
    {
      /* Program double word (64-bit = 4*16-bit) at a specified address. */
      nbiterations = 4U;
 8002942:	2304      	movs	r3, #4
 8002944:	757b      	strb	r3, [r7, #21]
    }

    for (index = 0U; index < nbiterations; index++)
 8002946:	2300      	movs	r3, #0
 8002948:	75bb      	strb	r3, [r7, #22]
 800294a:	e02d      	b.n	80029a8 <HAL_FLASH_Program+0xbc>
    {
      FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index)));
 800294c:	7dbb      	ldrb	r3, [r7, #22]
 800294e:	005a      	lsls	r2, r3, #1
 8002950:	68bb      	ldr	r3, [r7, #8]
 8002952:	eb02 0c03 	add.w	ip, r2, r3
 8002956:	7dbb      	ldrb	r3, [r7, #22]
 8002958:	0119      	lsls	r1, r3, #4
 800295a:	e9d7 2300 	ldrd	r2, r3, [r7]
 800295e:	f1c1 0620 	rsb	r6, r1, #32
 8002962:	f1a1 0020 	sub.w	r0, r1, #32
 8002966:	fa22 f401 	lsr.w	r4, r2, r1
 800296a:	fa03 f606 	lsl.w	r6, r3, r6
 800296e:	4334      	orrs	r4, r6
 8002970:	fa23 f000 	lsr.w	r0, r3, r0
 8002974:	4304      	orrs	r4, r0
 8002976:	fa23 f501 	lsr.w	r5, r3, r1
 800297a:	b2a3      	uxth	r3, r4
 800297c:	4619      	mov	r1, r3
 800297e:	4660      	mov	r0, ip
 8002980:	f000 f85a 	bl	8002a38 <FLASH_Program_HalfWord>
#if defined(FLASH_BANK2_END)
      if(Address <= FLASH_BANK1_END)
      {
#endif /* FLASH_BANK2_END */
        /* Wait for last operation to be completed */
        status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
 8002984:	f24c 3050 	movw	r0, #50000	; 0xc350
 8002988:	f000 f872 	bl	8002a70 <FLASH_WaitForLastOperation>
 800298c:	4603      	mov	r3, r0
 800298e:	75fb      	strb	r3, [r7, #23]
    
        /* If the program operation is completed, disable the PG Bit */
        CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
 8002990:	4b0d      	ldr	r3, [pc, #52]	; (80029c8 <HAL_FLASH_Program+0xdc>)
 8002992:	691b      	ldr	r3, [r3, #16]
 8002994:	4a0c      	ldr	r2, [pc, #48]	; (80029c8 <HAL_FLASH_Program+0xdc>)
 8002996:	f023 0301 	bic.w	r3, r3, #1
 800299a:	6113      	str	r3, [r2, #16]
        /* If the program operation is completed, disable the PG Bit */
        CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG);
      }
#endif /* FLASH_BANK2_END */
      /* In case of error, stop programation procedure */
      if (status != HAL_OK)
 800299c:	7dfb      	ldrb	r3, [r7, #23]
 800299e:	2b00      	cmp	r3, #0
 80029a0:	d107      	bne.n	80029b2 <HAL_FLASH_Program+0xc6>
    for (index = 0U; index < nbiterations; index++)
 80029a2:	7dbb      	ldrb	r3, [r7, #22]
 80029a4:	3301      	adds	r3, #1
 80029a6:	75bb      	strb	r3, [r7, #22]
 80029a8:	7dba      	ldrb	r2, [r7, #22]
 80029aa:	7d7b      	ldrb	r3, [r7, #21]
 80029ac:	429a      	cmp	r2, r3
 80029ae:	d3cd      	bcc.n	800294c <HAL_FLASH_Program+0x60>
 80029b0:	e000      	b.n	80029b4 <HAL_FLASH_Program+0xc8>
      {
        break;
 80029b2:	bf00      	nop
      }
    }
  }

  /* Process Unlocked */
  __HAL_UNLOCK(&pFlash);
 80029b4:	4b03      	ldr	r3, [pc, #12]	; (80029c4 <HAL_FLASH_Program+0xd8>)
 80029b6:	2200      	movs	r2, #0
 80029b8:	761a      	strb	r2, [r3, #24]

  return status;
 80029ba:	7dfb      	ldrb	r3, [r7, #23]
}
 80029bc:	4618      	mov	r0, r3
 80029be:	371c      	adds	r7, #28
 80029c0:	46bd      	mov	sp, r7
 80029c2:	bdf0      	pop	{r4, r5, r6, r7, pc}
 80029c4:	20000640 	.word	0x20000640
 80029c8:	40022000 	.word	0x40022000

080029cc <HAL_FLASH_Unlock>:
/**
  * @brief  Unlock the FLASH control register access
  * @retval HAL Status
  */
HAL_StatusTypeDef HAL_FLASH_Unlock(void)
{
 80029cc:	b480      	push	{r7}
 80029ce:	b083      	sub	sp, #12
 80029d0:	af00      	add	r7, sp, #0
  HAL_StatusTypeDef status = HAL_OK;
 80029d2:	2300      	movs	r3, #0
 80029d4:	71fb      	strb	r3, [r7, #7]

  if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
 80029d6:	4b0d      	ldr	r3, [pc, #52]	; (8002a0c <HAL_FLASH_Unlock+0x40>)
 80029d8:	691b      	ldr	r3, [r3, #16]
 80029da:	f003 0380 	and.w	r3, r3, #128	; 0x80
 80029de:	2b00      	cmp	r3, #0
 80029e0:	d00d      	beq.n	80029fe <HAL_FLASH_Unlock+0x32>
  {
    /* Authorize the FLASH Registers access */
    WRITE_REG(FLASH->KEYR, FLASH_KEY1);
 80029e2:	4b0a      	ldr	r3, [pc, #40]	; (8002a0c <HAL_FLASH_Unlock+0x40>)
 80029e4:	4a0a      	ldr	r2, [pc, #40]	; (8002a10 <HAL_FLASH_Unlock+0x44>)
 80029e6:	605a      	str	r2, [r3, #4]
    WRITE_REG(FLASH->KEYR, FLASH_KEY2);
 80029e8:	4b08      	ldr	r3, [pc, #32]	; (8002a0c <HAL_FLASH_Unlock+0x40>)
 80029ea:	4a0a      	ldr	r2, [pc, #40]	; (8002a14 <HAL_FLASH_Unlock+0x48>)
 80029ec:	605a      	str	r2, [r3, #4]

    /* Verify Flash is unlocked */
    if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
 80029ee:	4b07      	ldr	r3, [pc, #28]	; (8002a0c <HAL_FLASH_Unlock+0x40>)
 80029f0:	691b      	ldr	r3, [r3, #16]
 80029f2:	f003 0380 	and.w	r3, r3, #128	; 0x80
 80029f6:	2b00      	cmp	r3, #0
 80029f8:	d001      	beq.n	80029fe <HAL_FLASH_Unlock+0x32>
    {
      status = HAL_ERROR;
 80029fa:	2301      	movs	r3, #1
 80029fc:	71fb      	strb	r3, [r7, #7]
      status = HAL_ERROR;
    }
  }
#endif /* FLASH_BANK2_END */

  return status;
 80029fe:	79fb      	ldrb	r3, [r7, #7]
}
 8002a00:	4618      	mov	r0, r3
 8002a02:	370c      	adds	r7, #12
 8002a04:	46bd      	mov	sp, r7
 8002a06:	bc80      	pop	{r7}
 8002a08:	4770      	bx	lr
 8002a0a:	bf00      	nop
 8002a0c:	40022000 	.word	0x40022000
 8002a10:	45670123 	.word	0x45670123
 8002a14:	cdef89ab 	.word	0xcdef89ab

08002a18 <HAL_FLASH_Lock>:
/**
  * @brief  Locks the FLASH control register access
  * @retval HAL Status
  */
HAL_StatusTypeDef HAL_FLASH_Lock(void)
{
 8002a18:	b480      	push	{r7}
 8002a1a:	af00      	add	r7, sp, #0
  /* Set the LOCK Bit to lock the FLASH Registers access */
  SET_BIT(FLASH->CR, FLASH_CR_LOCK);
 8002a1c:	4b05      	ldr	r3, [pc, #20]	; (8002a34 <HAL_FLASH_Lock+0x1c>)
 8002a1e:	691b      	ldr	r3, [r3, #16]
 8002a20:	4a04      	ldr	r2, [pc, #16]	; (8002a34 <HAL_FLASH_Lock+0x1c>)
 8002a22:	f043 0380 	orr.w	r3, r3, #128	; 0x80
 8002a26:	6113      	str	r3, [r2, #16]
#if defined(FLASH_BANK2_END)
  /* Set the LOCK Bit to lock the FLASH BANK2 Registers access */
  SET_BIT(FLASH->CR2, FLASH_CR2_LOCK);

#endif /* FLASH_BANK2_END */
  return HAL_OK;  
 8002a28:	2300      	movs	r3, #0
}
 8002a2a:	4618      	mov	r0, r3
 8002a2c:	46bd      	mov	sp, r7
 8002a2e:	bc80      	pop	{r7}
 8002a30:	4770      	bx	lr
 8002a32:	bf00      	nop
 8002a34:	40022000 	.word	0x40022000

08002a38 <FLASH_Program_HalfWord>:
  * @param  Address specify the address to be programmed.
  * @param  Data    specify the data to be programmed.
  * @retval None
  */
static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
{
 8002a38:	b480      	push	{r7}
 8002a3a:	b083      	sub	sp, #12
 8002a3c:	af00      	add	r7, sp, #0
 8002a3e:	6078      	str	r0, [r7, #4]
 8002a40:	460b      	mov	r3, r1
 8002a42:	807b      	strh	r3, [r7, #2]
  /* Clean the error context */
  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
 8002a44:	4b08      	ldr	r3, [pc, #32]	; (8002a68 <FLASH_Program_HalfWord+0x30>)
 8002a46:	2200      	movs	r2, #0
 8002a48:	61da      	str	r2, [r3, #28]
#if defined(FLASH_BANK2_END)
  if(Address <= FLASH_BANK1_END)
  {
#endif /* FLASH_BANK2_END */
    /* Proceed to program the new data */
    SET_BIT(FLASH->CR, FLASH_CR_PG);
 8002a4a:	4b08      	ldr	r3, [pc, #32]	; (8002a6c <FLASH_Program_HalfWord+0x34>)
 8002a4c:	691b      	ldr	r3, [r3, #16]
 8002a4e:	4a07      	ldr	r2, [pc, #28]	; (8002a6c <FLASH_Program_HalfWord+0x34>)
 8002a50:	f043 0301 	orr.w	r3, r3, #1
 8002a54:	6113      	str	r3, [r2, #16]
    SET_BIT(FLASH->CR2, FLASH_CR2_PG);
  }
#endif /* FLASH_BANK2_END */

  /* Write data in the address */
  *(__IO uint16_t*)Address = Data;
 8002a56:	687b      	ldr	r3, [r7, #4]
 8002a58:	887a      	ldrh	r2, [r7, #2]
 8002a5a:	801a      	strh	r2, [r3, #0]
}
 8002a5c:	bf00      	nop
 8002a5e:	370c      	adds	r7, #12
 8002a60:	46bd      	mov	sp, r7
 8002a62:	bc80      	pop	{r7}
 8002a64:	4770      	bx	lr
 8002a66:	bf00      	nop
 8002a68:	20000640 	.word	0x20000640
 8002a6c:	40022000 	.word	0x40022000

08002a70 <FLASH_WaitForLastOperation>:
  * @brief  Wait for a FLASH operation to complete.
  * @param  Timeout  maximum flash operation timeout
  * @retval HAL Status
  */
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
{
 8002a70:	b580      	push	{r7, lr}
 8002a72:	b084      	sub	sp, #16
 8002a74:	af00      	add	r7, sp, #0
 8002a76:	6078      	str	r0, [r7, #4]
  /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
     Even if the FLASH operation fails, the BUSY flag will be reset and an error
     flag will be set */
     
  uint32_t tickstart = HAL_GetTick();
 8002a78:	f7fe fee8 	bl	800184c <HAL_GetTick>
 8002a7c:	60f8      	str	r0, [r7, #12]
     
  while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) 
 8002a7e:	e010      	b.n	8002aa2 <FLASH_WaitForLastOperation+0x32>
  { 
    if (Timeout != HAL_MAX_DELAY)
 8002a80:	687b      	ldr	r3, [r7, #4]
 8002a82:	f1b3 3fff 	cmp.w	r3, #4294967295
 8002a86:	d00c      	beq.n	8002aa2 <FLASH_WaitForLastOperation+0x32>
    {
      if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
 8002a88:	687b      	ldr	r3, [r7, #4]
 8002a8a:	2b00      	cmp	r3, #0
 8002a8c:	d007      	beq.n	8002a9e <FLASH_WaitForLastOperation+0x2e>
 8002a8e:	f7fe fedd 	bl	800184c <HAL_GetTick>
 8002a92:	4602      	mov	r2, r0
 8002a94:	68fb      	ldr	r3, [r7, #12]
 8002a96:	1ad3      	subs	r3, r2, r3
 8002a98:	687a      	ldr	r2, [r7, #4]
 8002a9a:	429a      	cmp	r2, r3
 8002a9c:	d201      	bcs.n	8002aa2 <FLASH_WaitForLastOperation+0x32>
      {
        return HAL_TIMEOUT;
 8002a9e:	2303      	movs	r3, #3
 8002aa0:	e025      	b.n	8002aee <FLASH_WaitForLastOperation+0x7e>
  while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) 
 8002aa2:	4b15      	ldr	r3, [pc, #84]	; (8002af8 <FLASH_WaitForLastOperation+0x88>)
 8002aa4:	68db      	ldr	r3, [r3, #12]
 8002aa6:	f003 0301 	and.w	r3, r3, #1
 8002aaa:	2b00      	cmp	r3, #0
 8002aac:	d1e8      	bne.n	8002a80 <FLASH_WaitForLastOperation+0x10>
      }
    }
  }
  
  /* Check FLASH End of Operation flag  */
  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
 8002aae:	4b12      	ldr	r3, [pc, #72]	; (8002af8 <FLASH_WaitForLastOperation+0x88>)
 8002ab0:	68db      	ldr	r3, [r3, #12]
 8002ab2:	f003 0320 	and.w	r3, r3, #32
 8002ab6:	2b00      	cmp	r3, #0
 8002ab8:	d002      	beq.n	8002ac0 <FLASH_WaitForLastOperation+0x50>
  {
    /* Clear FLASH End of Operation pending bit */
    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
 8002aba:	4b0f      	ldr	r3, [pc, #60]	; (8002af8 <FLASH_WaitForLastOperation+0x88>)
 8002abc:	2220      	movs	r2, #32
 8002abe:	60da      	str	r2, [r3, #12]
  }
  
  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)  || 
 8002ac0:	4b0d      	ldr	r3, [pc, #52]	; (8002af8 <FLASH_WaitForLastOperation+0x88>)
 8002ac2:	68db      	ldr	r3, [r3, #12]
 8002ac4:	f003 0310 	and.w	r3, r3, #16
 8002ac8:	2b00      	cmp	r3, #0
 8002aca:	d10b      	bne.n	8002ae4 <FLASH_WaitForLastOperation+0x74>
     __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || 
 8002acc:	4b0a      	ldr	r3, [pc, #40]	; (8002af8 <FLASH_WaitForLastOperation+0x88>)
 8002ace:	69db      	ldr	r3, [r3, #28]
 8002ad0:	f003 0301 	and.w	r3, r3, #1
  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)  || 
 8002ad4:	2b00      	cmp	r3, #0
 8002ad6:	d105      	bne.n	8002ae4 <FLASH_WaitForLastOperation+0x74>
     __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
 8002ad8:	4b07      	ldr	r3, [pc, #28]	; (8002af8 <FLASH_WaitForLastOperation+0x88>)
 8002ada:	68db      	ldr	r3, [r3, #12]
 8002adc:	f003 0304 	and.w	r3, r3, #4
     __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || 
 8002ae0:	2b00      	cmp	r3, #0
 8002ae2:	d003      	beq.n	8002aec <FLASH_WaitForLastOperation+0x7c>
  {
    /*Save the error code*/
    FLASH_SetErrorCode();
 8002ae4:	f000 f80a 	bl	8002afc <FLASH_SetErrorCode>
    return HAL_ERROR;
 8002ae8:	2301      	movs	r3, #1
 8002aea:	e000      	b.n	8002aee <FLASH_WaitForLastOperation+0x7e>
  }

  /* There is no error flag set */
  return HAL_OK;
 8002aec:	2300      	movs	r3, #0
}
 8002aee:	4618      	mov	r0, r3
 8002af0:	3710      	adds	r7, #16
 8002af2:	46bd      	mov	sp, r7
 8002af4:	bd80      	pop	{r7, pc}
 8002af6:	bf00      	nop
 8002af8:	40022000 	.word	0x40022000

08002afc <FLASH_SetErrorCode>:
/**
  * @brief  Set the specific FLASH error flag.
  * @retval None
  */
static void FLASH_SetErrorCode(void)
{
 8002afc:	b480      	push	{r7}
 8002afe:	b083      	sub	sp, #12
 8002b00:	af00      	add	r7, sp, #0
  uint32_t flags = 0U;
 8002b02:	2300      	movs	r3, #0
 8002b04:	607b      	str	r3, [r7, #4]
  
#if defined(FLASH_BANK2_END)
  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2))
#else
  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
 8002b06:	4b23      	ldr	r3, [pc, #140]	; (8002b94 <FLASH_SetErrorCode+0x98>)
 8002b08:	68db      	ldr	r3, [r3, #12]
 8002b0a:	f003 0310 	and.w	r3, r3, #16
 8002b0e:	2b00      	cmp	r3, #0
 8002b10:	d009      	beq.n	8002b26 <FLASH_SetErrorCode+0x2a>
#endif /* FLASH_BANK2_END */
  {
    pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
 8002b12:	4b21      	ldr	r3, [pc, #132]	; (8002b98 <FLASH_SetErrorCode+0x9c>)
 8002b14:	69db      	ldr	r3, [r3, #28]
 8002b16:	f043 0302 	orr.w	r3, r3, #2
 8002b1a:	4a1f      	ldr	r2, [pc, #124]	; (8002b98 <FLASH_SetErrorCode+0x9c>)
 8002b1c:	61d3      	str	r3, [r2, #28]
#if defined(FLASH_BANK2_END)
    flags |= FLASH_FLAG_WRPERR | FLASH_FLAG_WRPERR_BANK2;
#else
    flags |= FLASH_FLAG_WRPERR;
 8002b1e:	687b      	ldr	r3, [r7, #4]
 8002b20:	f043 0310 	orr.w	r3, r3, #16
 8002b24:	607b      	str	r3, [r7, #4]
#endif /* FLASH_BANK2_END */
  }
#if defined(FLASH_BANK2_END)
  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2))
#else
  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
 8002b26:	4b1b      	ldr	r3, [pc, #108]	; (8002b94 <FLASH_SetErrorCode+0x98>)
 8002b28:	68db      	ldr	r3, [r3, #12]
 8002b2a:	f003 0304 	and.w	r3, r3, #4
 8002b2e:	2b00      	cmp	r3, #0
 8002b30:	d009      	beq.n	8002b46 <FLASH_SetErrorCode+0x4a>
#endif /* FLASH_BANK2_END */
  {
    pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG;
 8002b32:	4b19      	ldr	r3, [pc, #100]	; (8002b98 <FLASH_SetErrorCode+0x9c>)
 8002b34:	69db      	ldr	r3, [r3, #28]
 8002b36:	f043 0301 	orr.w	r3, r3, #1
 8002b3a:	4a17      	ldr	r2, [pc, #92]	; (8002b98 <FLASH_SetErrorCode+0x9c>)
 8002b3c:	61d3      	str	r3, [r2, #28]
#if defined(FLASH_BANK2_END)
    flags |= FLASH_FLAG_PGERR | FLASH_FLAG_PGERR_BANK2;
#else
    flags |= FLASH_FLAG_PGERR;
 8002b3e:	687b      	ldr	r3, [r7, #4]
 8002b40:	f043 0304 	orr.w	r3, r3, #4
 8002b44:	607b      	str	r3, [r7, #4]
#endif /* FLASH_BANK2_END */
  }
  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR))
 8002b46:	4b13      	ldr	r3, [pc, #76]	; (8002b94 <FLASH_SetErrorCode+0x98>)
 8002b48:	69db      	ldr	r3, [r3, #28]
 8002b4a:	f003 0301 	and.w	r3, r3, #1
 8002b4e:	2b00      	cmp	r3, #0
 8002b50:	d00b      	beq.n	8002b6a <FLASH_SetErrorCode+0x6e>
  {
    pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV;
 8002b52:	4b11      	ldr	r3, [pc, #68]	; (8002b98 <FLASH_SetErrorCode+0x9c>)
 8002b54:	69db      	ldr	r3, [r3, #28]
 8002b56:	f043 0304 	orr.w	r3, r3, #4
 8002b5a:	4a0f      	ldr	r2, [pc, #60]	; (8002b98 <FLASH_SetErrorCode+0x9c>)
 8002b5c:	61d3      	str	r3, [r2, #28]
  __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR);
 8002b5e:	4b0d      	ldr	r3, [pc, #52]	; (8002b94 <FLASH_SetErrorCode+0x98>)
 8002b60:	69db      	ldr	r3, [r3, #28]
 8002b62:	4a0c      	ldr	r2, [pc, #48]	; (8002b94 <FLASH_SetErrorCode+0x98>)
 8002b64:	f023 0301 	bic.w	r3, r3, #1
 8002b68:	61d3      	str	r3, [r2, #28]
  }

  /* Clear FLASH error pending bits */
  __HAL_FLASH_CLEAR_FLAG(flags);
 8002b6a:	687b      	ldr	r3, [r7, #4]
 8002b6c:	f240 1201 	movw	r2, #257	; 0x101
 8002b70:	4293      	cmp	r3, r2
 8002b72:	d106      	bne.n	8002b82 <FLASH_SetErrorCode+0x86>
 8002b74:	4b07      	ldr	r3, [pc, #28]	; (8002b94 <FLASH_SetErrorCode+0x98>)
 8002b76:	69db      	ldr	r3, [r3, #28]
 8002b78:	4a06      	ldr	r2, [pc, #24]	; (8002b94 <FLASH_SetErrorCode+0x98>)
 8002b7a:	f023 0301 	bic.w	r3, r3, #1
 8002b7e:	61d3      	str	r3, [r2, #28]
}  
 8002b80:	e002      	b.n	8002b88 <FLASH_SetErrorCode+0x8c>
  __HAL_FLASH_CLEAR_FLAG(flags);
 8002b82:	4a04      	ldr	r2, [pc, #16]	; (8002b94 <FLASH_SetErrorCode+0x98>)
 8002b84:	687b      	ldr	r3, [r7, #4]
 8002b86:	60d3      	str	r3, [r2, #12]
}  
 8002b88:	bf00      	nop
 8002b8a:	370c      	adds	r7, #12
 8002b8c:	46bd      	mov	sp, r7
 8002b8e:	bc80      	pop	{r7}
 8002b90:	4770      	bx	lr
 8002b92:	bf00      	nop
 8002b94:	40022000 	.word	0x40022000
 8002b98:	20000640 	.word	0x20000640

08002b9c <HAL_FLASHEx_Erase>:
  *         (0xFFFFFFFF means that all the pages have been correctly erased)
  *
  * @retval HAL_StatusTypeDef HAL Status
  */
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
{
 8002b9c:	b580      	push	{r7, lr}
 8002b9e:	b084      	sub	sp, #16
 8002ba0:	af00      	add	r7, sp, #0
 8002ba2:	6078      	str	r0, [r7, #4]
 8002ba4:	6039      	str	r1, [r7, #0]
  HAL_StatusTypeDef status = HAL_ERROR;
 8002ba6:	2301      	movs	r3, #1
 8002ba8:	73fb      	strb	r3, [r7, #15]
  uint32_t address = 0U;
 8002baa:	2300      	movs	r3, #0
 8002bac:	60bb      	str	r3, [r7, #8]

  /* Process Locked */
  __HAL_LOCK(&pFlash);
 8002bae:	4b2f      	ldr	r3, [pc, #188]	; (8002c6c <HAL_FLASHEx_Erase+0xd0>)
 8002bb0:	7e1b      	ldrb	r3, [r3, #24]
 8002bb2:	2b01      	cmp	r3, #1
 8002bb4:	d101      	bne.n	8002bba <HAL_FLASHEx_Erase+0x1e>
 8002bb6:	2302      	movs	r3, #2
 8002bb8:	e053      	b.n	8002c62 <HAL_FLASHEx_Erase+0xc6>
 8002bba:	4b2c      	ldr	r3, [pc, #176]	; (8002c6c <HAL_FLASHEx_Erase+0xd0>)
 8002bbc:	2201      	movs	r2, #1
 8002bbe:	761a      	strb	r2, [r3, #24]

  /* Check the parameters */
  assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));

  if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
 8002bc0:	687b      	ldr	r3, [r7, #4]
 8002bc2:	681b      	ldr	r3, [r3, #0]
 8002bc4:	2b02      	cmp	r3, #2
 8002bc6:	d116      	bne.n	8002bf6 <HAL_FLASHEx_Erase+0x5a>
    else 
#endif /* FLASH_BANK2_END */
    {
      /* Mass Erase requested for Bank1 */
      /* Wait for last operation to be completed */
      if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
 8002bc8:	f24c 3050 	movw	r0, #50000	; 0xc350
 8002bcc:	f7ff ff50 	bl	8002a70 <FLASH_WaitForLastOperation>
 8002bd0:	4603      	mov	r3, r0
 8002bd2:	2b00      	cmp	r3, #0
 8002bd4:	d141      	bne.n	8002c5a <HAL_FLASHEx_Erase+0xbe>
      {
        /*Mass erase to be done*/
        FLASH_MassErase(FLASH_BANK_1);
 8002bd6:	2001      	movs	r0, #1
 8002bd8:	f000 f84c 	bl	8002c74 <FLASH_MassErase>
        
        /* Wait for last operation to be completed */
        status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
 8002bdc:	f24c 3050 	movw	r0, #50000	; 0xc350
 8002be0:	f7ff ff46 	bl	8002a70 <FLASH_WaitForLastOperation>
 8002be4:	4603      	mov	r3, r0
 8002be6:	73fb      	strb	r3, [r7, #15]
        
        /* If the erase operation is completed, disable the MER Bit */
        CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
 8002be8:	4b21      	ldr	r3, [pc, #132]	; (8002c70 <HAL_FLASHEx_Erase+0xd4>)
 8002bea:	691b      	ldr	r3, [r3, #16]
 8002bec:	4a20      	ldr	r2, [pc, #128]	; (8002c70 <HAL_FLASHEx_Erase+0xd4>)
 8002bee:	f023 0304 	bic.w	r3, r3, #4
 8002bf2:	6113      	str	r3, [r2, #16]
 8002bf4:	e031      	b.n	8002c5a <HAL_FLASHEx_Erase+0xbe>
    else
#endif /* FLASH_BANK2_END */
   {
      /* Page Erase requested on address located on bank1 */
      /* Wait for last operation to be completed */
      if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
 8002bf6:	f24c 3050 	movw	r0, #50000	; 0xc350
 8002bfa:	f7ff ff39 	bl	8002a70 <FLASH_WaitForLastOperation>
 8002bfe:	4603      	mov	r3, r0
 8002c00:	2b00      	cmp	r3, #0
 8002c02:	d12a      	bne.n	8002c5a <HAL_FLASHEx_Erase+0xbe>
      {
        /*Initialization of PageError variable*/
        *PageError = 0xFFFFFFFFU;
 8002c04:	683b      	ldr	r3, [r7, #0]
 8002c06:	f04f 32ff 	mov.w	r2, #4294967295
 8002c0a:	601a      	str	r2, [r3, #0]
        
        /* Erase page by page to be done*/
        for(address = pEraseInit->PageAddress;
 8002c0c:	687b      	ldr	r3, [r7, #4]
 8002c0e:	689b      	ldr	r3, [r3, #8]
 8002c10:	60bb      	str	r3, [r7, #8]
 8002c12:	e019      	b.n	8002c48 <HAL_FLASHEx_Erase+0xac>
            address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress);
            address += FLASH_PAGE_SIZE)
        {
          FLASH_PageErase(address);
 8002c14:	68b8      	ldr	r0, [r7, #8]
 8002c16:	f000 f849 	bl	8002cac <FLASH_PageErase>
          
          /* Wait for last operation to be completed */
          status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
 8002c1a:	f24c 3050 	movw	r0, #50000	; 0xc350
 8002c1e:	f7ff ff27 	bl	8002a70 <FLASH_WaitForLastOperation>
 8002c22:	4603      	mov	r3, r0
 8002c24:	73fb      	strb	r3, [r7, #15]
          
          /* If the erase operation is completed, disable the PER Bit */
          CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
 8002c26:	4b12      	ldr	r3, [pc, #72]	; (8002c70 <HAL_FLASHEx_Erase+0xd4>)
 8002c28:	691b      	ldr	r3, [r3, #16]
 8002c2a:	4a11      	ldr	r2, [pc, #68]	; (8002c70 <HAL_FLASHEx_Erase+0xd4>)
 8002c2c:	f023 0302 	bic.w	r3, r3, #2
 8002c30:	6113      	str	r3, [r2, #16]
          
          if (status != HAL_OK)
 8002c32:	7bfb      	ldrb	r3, [r7, #15]
 8002c34:	2b00      	cmp	r3, #0
 8002c36:	d003      	beq.n	8002c40 <HAL_FLASHEx_Erase+0xa4>
          {
            /* In case of error, stop erase procedure and return the faulty address */
            *PageError = address;
 8002c38:	683b      	ldr	r3, [r7, #0]
 8002c3a:	68ba      	ldr	r2, [r7, #8]
 8002c3c:	601a      	str	r2, [r3, #0]
            break;
 8002c3e:	e00c      	b.n	8002c5a <HAL_FLASHEx_Erase+0xbe>
            address += FLASH_PAGE_SIZE)
 8002c40:	68bb      	ldr	r3, [r7, #8]
 8002c42:	f503 6380 	add.w	r3, r3, #1024	; 0x400
 8002c46:	60bb      	str	r3, [r7, #8]
            address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress);
 8002c48:	687b      	ldr	r3, [r7, #4]
 8002c4a:	68db      	ldr	r3, [r3, #12]
 8002c4c:	029a      	lsls	r2, r3, #10
 8002c4e:	687b      	ldr	r3, [r7, #4]
 8002c50:	689b      	ldr	r3, [r3, #8]
 8002c52:	4413      	add	r3, r2
        for(address = pEraseInit->PageAddress;
 8002c54:	68ba      	ldr	r2, [r7, #8]
 8002c56:	429a      	cmp	r2, r3
 8002c58:	d3dc      	bcc.n	8002c14 <HAL_FLASHEx_Erase+0x78>
      }
    }
  }

  /* Process Unlocked */
  __HAL_UNLOCK(&pFlash);
 8002c5a:	4b04      	ldr	r3, [pc, #16]	; (8002c6c <HAL_FLASHEx_Erase+0xd0>)
 8002c5c:	2200      	movs	r2, #0
 8002c5e:	761a      	strb	r2, [r3, #24]

  return status;
 8002c60:	7bfb      	ldrb	r3, [r7, #15]
}
 8002c62:	4618      	mov	r0, r3
 8002c64:	3710      	adds	r7, #16
 8002c66:	46bd      	mov	sp, r7
 8002c68:	bd80      	pop	{r7, pc}
 8002c6a:	bf00      	nop
 8002c6c:	20000640 	.word	0x20000640
 8002c70:	40022000 	.word	0x40022000

08002c74 <FLASH_MassErase>:
  @endif
  *
  * @retval None
  */
static void FLASH_MassErase(uint32_t Banks)
{
 8002c74:	b480      	push	{r7}
 8002c76:	b083      	sub	sp, #12
 8002c78:	af00      	add	r7, sp, #0
 8002c7a:	6078      	str	r0, [r7, #4]
  /* Check the parameters */
  assert_param(IS_FLASH_BANK(Banks));

  /* Clean the error context */
  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
 8002c7c:	4b09      	ldr	r3, [pc, #36]	; (8002ca4 <FLASH_MassErase+0x30>)
 8002c7e:	2200      	movs	r2, #0
 8002c80:	61da      	str	r2, [r3, #28]
#if !defined(FLASH_BANK2_END)
  /* Prevent unused argument(s) compilation warning */
  UNUSED(Banks);
#endif /* FLASH_BANK2_END */  
    /* Only bank1 will be erased*/
    SET_BIT(FLASH->CR, FLASH_CR_MER);
 8002c82:	4b09      	ldr	r3, [pc, #36]	; (8002ca8 <FLASH_MassErase+0x34>)
 8002c84:	691b      	ldr	r3, [r3, #16]
 8002c86:	4a08      	ldr	r2, [pc, #32]	; (8002ca8 <FLASH_MassErase+0x34>)
 8002c88:	f043 0304 	orr.w	r3, r3, #4
 8002c8c:	6113      	str	r3, [r2, #16]
    SET_BIT(FLASH->CR, FLASH_CR_STRT);
 8002c8e:	4b06      	ldr	r3, [pc, #24]	; (8002ca8 <FLASH_MassErase+0x34>)
 8002c90:	691b      	ldr	r3, [r3, #16]
 8002c92:	4a05      	ldr	r2, [pc, #20]	; (8002ca8 <FLASH_MassErase+0x34>)
 8002c94:	f043 0340 	orr.w	r3, r3, #64	; 0x40
 8002c98:	6113      	str	r3, [r2, #16]
#if defined(FLASH_BANK2_END)
  }
#endif /* FLASH_BANK2_END */
}
 8002c9a:	bf00      	nop
 8002c9c:	370c      	adds	r7, #12
 8002c9e:	46bd      	mov	sp, r7
 8002ca0:	bc80      	pop	{r7}
 8002ca2:	4770      	bx	lr
 8002ca4:	20000640 	.word	0x20000640
 8002ca8:	40022000 	.word	0x40022000

08002cac <FLASH_PageErase>:
  *         The value of this parameter depend on device used within the same series      
  * 
  * @retval None
  */
void FLASH_PageErase(uint32_t PageAddress)
{
 8002cac:	b480      	push	{r7}
 8002cae:	b083      	sub	sp, #12
 8002cb0:	af00      	add	r7, sp, #0
 8002cb2:	6078      	str	r0, [r7, #4]
  /* Clean the error context */
  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
 8002cb4:	4b0b      	ldr	r3, [pc, #44]	; (8002ce4 <FLASH_PageErase+0x38>)
 8002cb6:	2200      	movs	r2, #0
 8002cb8:	61da      	str	r2, [r3, #28]
  }
  else
  {
#endif /* FLASH_BANK2_END */
    /* Proceed to erase the page */
    SET_BIT(FLASH->CR, FLASH_CR_PER);
 8002cba:	4b0b      	ldr	r3, [pc, #44]	; (8002ce8 <FLASH_PageErase+0x3c>)
 8002cbc:	691b      	ldr	r3, [r3, #16]
 8002cbe:	4a0a      	ldr	r2, [pc, #40]	; (8002ce8 <FLASH_PageErase+0x3c>)
 8002cc0:	f043 0302 	orr.w	r3, r3, #2
 8002cc4:	6113      	str	r3, [r2, #16]
    WRITE_REG(FLASH->AR, PageAddress);
 8002cc6:	4a08      	ldr	r2, [pc, #32]	; (8002ce8 <FLASH_PageErase+0x3c>)
 8002cc8:	687b      	ldr	r3, [r7, #4]
 8002cca:	6153      	str	r3, [r2, #20]
    SET_BIT(FLASH->CR, FLASH_CR_STRT);
 8002ccc:	4b06      	ldr	r3, [pc, #24]	; (8002ce8 <FLASH_PageErase+0x3c>)
 8002cce:	691b      	ldr	r3, [r3, #16]
 8002cd0:	4a05      	ldr	r2, [pc, #20]	; (8002ce8 <FLASH_PageErase+0x3c>)
 8002cd2:	f043 0340 	orr.w	r3, r3, #64	; 0x40
 8002cd6:	6113      	str	r3, [r2, #16]
#if defined(FLASH_BANK2_END)
  }
#endif /* FLASH_BANK2_END */
}
 8002cd8:	bf00      	nop
 8002cda:	370c      	adds	r7, #12
 8002cdc:	46bd      	mov	sp, r7
 8002cde:	bc80      	pop	{r7}
 8002ce0:	4770      	bx	lr
 8002ce2:	bf00      	nop
 8002ce4:	20000640 	.word	0x20000640
 8002ce8:	40022000 	.word	0x40022000

08002cec <HAL_GPIO_Init>:
  * @param  GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
  *         the configuration information for the specified GPIO peripheral.
  * @retval None
  */
void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
 8002cec:	b480      	push	{r7}
 8002cee:	b08b      	sub	sp, #44	; 0x2c
 8002cf0:	af00      	add	r7, sp, #0
 8002cf2:	6078      	str	r0, [r7, #4]
 8002cf4:	6039      	str	r1, [r7, #0]
  uint32_t position = 0x00u;
 8002cf6:	2300      	movs	r3, #0
 8002cf8:	627b      	str	r3, [r7, #36]	; 0x24
  uint32_t ioposition;
  uint32_t iocurrent;
  uint32_t temp;
  uint32_t config = 0x00u;
 8002cfa:	2300      	movs	r3, #0
 8002cfc:	623b      	str	r3, [r7, #32]
  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));

  /* Configure the port pins */
  while (((GPIO_Init->Pin) >> position) != 0x00u)
 8002cfe:	e127      	b.n	8002f50 <HAL_GPIO_Init+0x264>
  {
    /* Get the IO position */
    ioposition = (0x01uL << position);
 8002d00:	2201      	movs	r2, #1
 8002d02:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 8002d04:	fa02 f303 	lsl.w	r3, r2, r3
 8002d08:	61fb      	str	r3, [r7, #28]

    /* Get the current IO position */
    iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
 8002d0a:	683b      	ldr	r3, [r7, #0]
 8002d0c:	681b      	ldr	r3, [r3, #0]
 8002d0e:	69fa      	ldr	r2, [r7, #28]
 8002d10:	4013      	ands	r3, r2
 8002d12:	61bb      	str	r3, [r7, #24]

    if (iocurrent == ioposition)
 8002d14:	69ba      	ldr	r2, [r7, #24]
 8002d16:	69fb      	ldr	r3, [r7, #28]
 8002d18:	429a      	cmp	r2, r3
 8002d1a:	f040 8116 	bne.w	8002f4a <HAL_GPIO_Init+0x25e>
    {
      /* Check the Alternate function parameters */
      assert_param(IS_GPIO_AF_INSTANCE(GPIOx));

      /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */
      switch (GPIO_Init->Mode)
 8002d1e:	683b      	ldr	r3, [r7, #0]
 8002d20:	685b      	ldr	r3, [r3, #4]
 8002d22:	2b12      	cmp	r3, #18
 8002d24:	d034      	beq.n	8002d90 <HAL_GPIO_Init+0xa4>
 8002d26:	2b12      	cmp	r3, #18
 8002d28:	d80d      	bhi.n	8002d46 <HAL_GPIO_Init+0x5a>
 8002d2a:	2b02      	cmp	r3, #2
 8002d2c:	d02b      	beq.n	8002d86 <HAL_GPIO_Init+0x9a>
 8002d2e:	2b02      	cmp	r3, #2
 8002d30:	d804      	bhi.n	8002d3c <HAL_GPIO_Init+0x50>
 8002d32:	2b00      	cmp	r3, #0
 8002d34:	d031      	beq.n	8002d9a <HAL_GPIO_Init+0xae>
 8002d36:	2b01      	cmp	r3, #1
 8002d38:	d01c      	beq.n	8002d74 <HAL_GPIO_Init+0x88>
          config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
          break;

        /* Parameters are checked with assert_param */
        default:
          break;
 8002d3a:	e048      	b.n	8002dce <HAL_GPIO_Init+0xe2>
      switch (GPIO_Init->Mode)
 8002d3c:	2b03      	cmp	r3, #3
 8002d3e:	d043      	beq.n	8002dc8 <HAL_GPIO_Init+0xdc>
 8002d40:	2b11      	cmp	r3, #17
 8002d42:	d01b      	beq.n	8002d7c <HAL_GPIO_Init+0x90>
          break;
 8002d44:	e043      	b.n	8002dce <HAL_GPIO_Init+0xe2>
      switch (GPIO_Init->Mode)
 8002d46:	4a89      	ldr	r2, [pc, #548]	; (8002f6c <HAL_GPIO_Init+0x280>)
 8002d48:	4293      	cmp	r3, r2
 8002d4a:	d026      	beq.n	8002d9a <HAL_GPIO_Init+0xae>
 8002d4c:	4a87      	ldr	r2, [pc, #540]	; (8002f6c <HAL_GPIO_Init+0x280>)
 8002d4e:	4293      	cmp	r3, r2
 8002d50:	d806      	bhi.n	8002d60 <HAL_GPIO_Init+0x74>
 8002d52:	4a87      	ldr	r2, [pc, #540]	; (8002f70 <HAL_GPIO_Init+0x284>)
 8002d54:	4293      	cmp	r3, r2
 8002d56:	d020      	beq.n	8002d9a <HAL_GPIO_Init+0xae>
 8002d58:	4a86      	ldr	r2, [pc, #536]	; (8002f74 <HAL_GPIO_Init+0x288>)
 8002d5a:	4293      	cmp	r3, r2
 8002d5c:	d01d      	beq.n	8002d9a <HAL_GPIO_Init+0xae>
          break;
 8002d5e:	e036      	b.n	8002dce <HAL_GPIO_Init+0xe2>
      switch (GPIO_Init->Mode)
 8002d60:	4a85      	ldr	r2, [pc, #532]	; (8002f78 <HAL_GPIO_Init+0x28c>)
 8002d62:	4293      	cmp	r3, r2
 8002d64:	d019      	beq.n	8002d9a <HAL_GPIO_Init+0xae>
 8002d66:	4a85      	ldr	r2, [pc, #532]	; (8002f7c <HAL_GPIO_Init+0x290>)
 8002d68:	4293      	cmp	r3, r2
 8002d6a:	d016      	beq.n	8002d9a <HAL_GPIO_Init+0xae>
 8002d6c:	4a84      	ldr	r2, [pc, #528]	; (8002f80 <HAL_GPIO_Init+0x294>)
 8002d6e:	4293      	cmp	r3, r2
 8002d70:	d013      	beq.n	8002d9a <HAL_GPIO_Init+0xae>
          break;
 8002d72:	e02c      	b.n	8002dce <HAL_GPIO_Init+0xe2>
          config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;
 8002d74:	683b      	ldr	r3, [r7, #0]
 8002d76:	68db      	ldr	r3, [r3, #12]
 8002d78:	623b      	str	r3, [r7, #32]
          break;
 8002d7a:	e028      	b.n	8002dce <HAL_GPIO_Init+0xe2>
          config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;
 8002d7c:	683b      	ldr	r3, [r7, #0]
 8002d7e:	68db      	ldr	r3, [r3, #12]
 8002d80:	3304      	adds	r3, #4
 8002d82:	623b      	str	r3, [r7, #32]
          break;
 8002d84:	e023      	b.n	8002dce <HAL_GPIO_Init+0xe2>
          config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;
 8002d86:	683b      	ldr	r3, [r7, #0]
 8002d88:	68db      	ldr	r3, [r3, #12]
 8002d8a:	3308      	adds	r3, #8
 8002d8c:	623b      	str	r3, [r7, #32]
          break;
 8002d8e:	e01e      	b.n	8002dce <HAL_GPIO_Init+0xe2>
          config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;
 8002d90:	683b      	ldr	r3, [r7, #0]
 8002d92:	68db      	ldr	r3, [r3, #12]
 8002d94:	330c      	adds	r3, #12
 8002d96:	623b      	str	r3, [r7, #32]
          break;
 8002d98:	e019      	b.n	8002dce <HAL_GPIO_Init+0xe2>
          if (GPIO_Init->Pull == GPIO_NOPULL)
 8002d9a:	683b      	ldr	r3, [r7, #0]
 8002d9c:	689b      	ldr	r3, [r3, #8]
 8002d9e:	2b00      	cmp	r3, #0
 8002da0:	d102      	bne.n	8002da8 <HAL_GPIO_Init+0xbc>
            config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
 8002da2:	2304      	movs	r3, #4
 8002da4:	623b      	str	r3, [r7, #32]
          break;
 8002da6:	e012      	b.n	8002dce <HAL_GPIO_Init+0xe2>
          else if (GPIO_Init->Pull == GPIO_PULLUP)
 8002da8:	683b      	ldr	r3, [r7, #0]
 8002daa:	689b      	ldr	r3, [r3, #8]
 8002dac:	2b01      	cmp	r3, #1
 8002dae:	d105      	bne.n	8002dbc <HAL_GPIO_Init+0xd0>
            config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
 8002db0:	2308      	movs	r3, #8
 8002db2:	623b      	str	r3, [r7, #32]
            GPIOx->BSRR = ioposition;
 8002db4:	687b      	ldr	r3, [r7, #4]
 8002db6:	69fa      	ldr	r2, [r7, #28]
 8002db8:	611a      	str	r2, [r3, #16]
          break;
 8002dba:	e008      	b.n	8002dce <HAL_GPIO_Init+0xe2>
            config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
 8002dbc:	2308      	movs	r3, #8
 8002dbe:	623b      	str	r3, [r7, #32]
            GPIOx->BRR = ioposition;
 8002dc0:	687b      	ldr	r3, [r7, #4]
 8002dc2:	69fa      	ldr	r2, [r7, #28]
 8002dc4:	615a      	str	r2, [r3, #20]
          break;
 8002dc6:	e002      	b.n	8002dce <HAL_GPIO_Init+0xe2>
          config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
 8002dc8:	2300      	movs	r3, #0
 8002dca:	623b      	str	r3, [r7, #32]
          break;
 8002dcc:	bf00      	nop
      }

      /* Check if the current bit belongs to first half or last half of the pin count number
       in order to address CRH or CRL register*/
      configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL     : &GPIOx->CRH;
 8002dce:	69bb      	ldr	r3, [r7, #24]
 8002dd0:	2bff      	cmp	r3, #255	; 0xff
 8002dd2:	d801      	bhi.n	8002dd8 <HAL_GPIO_Init+0xec>
 8002dd4:	687b      	ldr	r3, [r7, #4]
 8002dd6:	e001      	b.n	8002ddc <HAL_GPIO_Init+0xf0>
 8002dd8:	687b      	ldr	r3, [r7, #4]
 8002dda:	3304      	adds	r3, #4
 8002ddc:	617b      	str	r3, [r7, #20]
      registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u);
 8002dde:	69bb      	ldr	r3, [r7, #24]
 8002de0:	2bff      	cmp	r3, #255	; 0xff
 8002de2:	d802      	bhi.n	8002dea <HAL_GPIO_Init+0xfe>
 8002de4:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 8002de6:	009b      	lsls	r3, r3, #2
 8002de8:	e002      	b.n	8002df0 <HAL_GPIO_Init+0x104>
 8002dea:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 8002dec:	3b08      	subs	r3, #8
 8002dee:	009b      	lsls	r3, r3, #2
 8002df0:	613b      	str	r3, [r7, #16]

      /* Apply the new configuration of the pin to the register */
      MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
 8002df2:	697b      	ldr	r3, [r7, #20]
 8002df4:	681a      	ldr	r2, [r3, #0]
 8002df6:	210f      	movs	r1, #15
 8002df8:	693b      	ldr	r3, [r7, #16]
 8002dfa:	fa01 f303 	lsl.w	r3, r1, r3
 8002dfe:	43db      	mvns	r3, r3
 8002e00:	401a      	ands	r2, r3
 8002e02:	6a39      	ldr	r1, [r7, #32]
 8002e04:	693b      	ldr	r3, [r7, #16]
 8002e06:	fa01 f303 	lsl.w	r3, r1, r3
 8002e0a:	431a      	orrs	r2, r3
 8002e0c:	697b      	ldr	r3, [r7, #20]
 8002e0e:	601a      	str	r2, [r3, #0]

      /*--------------------- EXTI Mode Configuration ------------------------*/
      /* Configure the External Interrupt or event for the current IO */
      if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
 8002e10:	683b      	ldr	r3, [r7, #0]
 8002e12:	685b      	ldr	r3, [r3, #4]
 8002e14:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8002e18:	2b00      	cmp	r3, #0
 8002e1a:	f000 8096 	beq.w	8002f4a <HAL_GPIO_Init+0x25e>
      {
        /* Enable AFIO Clock */
        __HAL_RCC_AFIO_CLK_ENABLE();
 8002e1e:	4b59      	ldr	r3, [pc, #356]	; (8002f84 <HAL_GPIO_Init+0x298>)
 8002e20:	699b      	ldr	r3, [r3, #24]
 8002e22:	4a58      	ldr	r2, [pc, #352]	; (8002f84 <HAL_GPIO_Init+0x298>)
 8002e24:	f043 0301 	orr.w	r3, r3, #1
 8002e28:	6193      	str	r3, [r2, #24]
 8002e2a:	4b56      	ldr	r3, [pc, #344]	; (8002f84 <HAL_GPIO_Init+0x298>)
 8002e2c:	699b      	ldr	r3, [r3, #24]
 8002e2e:	f003 0301 	and.w	r3, r3, #1
 8002e32:	60bb      	str	r3, [r7, #8]
 8002e34:	68bb      	ldr	r3, [r7, #8]
        temp = AFIO->EXTICR[position >> 2u];
 8002e36:	4a54      	ldr	r2, [pc, #336]	; (8002f88 <HAL_GPIO_Init+0x29c>)
 8002e38:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 8002e3a:	089b      	lsrs	r3, r3, #2
 8002e3c:	3302      	adds	r3, #2
 8002e3e:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
 8002e42:	60fb      	str	r3, [r7, #12]
        CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u)));
 8002e44:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 8002e46:	f003 0303 	and.w	r3, r3, #3
 8002e4a:	009b      	lsls	r3, r3, #2
 8002e4c:	220f      	movs	r2, #15
 8002e4e:	fa02 f303 	lsl.w	r3, r2, r3
 8002e52:	43db      	mvns	r3, r3
 8002e54:	68fa      	ldr	r2, [r7, #12]
 8002e56:	4013      	ands	r3, r2
 8002e58:	60fb      	str	r3, [r7, #12]
        SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u)));
 8002e5a:	687b      	ldr	r3, [r7, #4]
 8002e5c:	4a4b      	ldr	r2, [pc, #300]	; (8002f8c <HAL_GPIO_Init+0x2a0>)
 8002e5e:	4293      	cmp	r3, r2
 8002e60:	d013      	beq.n	8002e8a <HAL_GPIO_Init+0x19e>
 8002e62:	687b      	ldr	r3, [r7, #4]
 8002e64:	4a4a      	ldr	r2, [pc, #296]	; (8002f90 <HAL_GPIO_Init+0x2a4>)
 8002e66:	4293      	cmp	r3, r2
 8002e68:	d00d      	beq.n	8002e86 <HAL_GPIO_Init+0x19a>
 8002e6a:	687b      	ldr	r3, [r7, #4]
 8002e6c:	4a49      	ldr	r2, [pc, #292]	; (8002f94 <HAL_GPIO_Init+0x2a8>)
 8002e6e:	4293      	cmp	r3, r2
 8002e70:	d007      	beq.n	8002e82 <HAL_GPIO_Init+0x196>
 8002e72:	687b      	ldr	r3, [r7, #4]
 8002e74:	4a48      	ldr	r2, [pc, #288]	; (8002f98 <HAL_GPIO_Init+0x2ac>)
 8002e76:	4293      	cmp	r3, r2
 8002e78:	d101      	bne.n	8002e7e <HAL_GPIO_Init+0x192>
 8002e7a:	2303      	movs	r3, #3
 8002e7c:	e006      	b.n	8002e8c <HAL_GPIO_Init+0x1a0>
 8002e7e:	2304      	movs	r3, #4
 8002e80:	e004      	b.n	8002e8c <HAL_GPIO_Init+0x1a0>
 8002e82:	2302      	movs	r3, #2
 8002e84:	e002      	b.n	8002e8c <HAL_GPIO_Init+0x1a0>
 8002e86:	2301      	movs	r3, #1
 8002e88:	e000      	b.n	8002e8c <HAL_GPIO_Init+0x1a0>
 8002e8a:	2300      	movs	r3, #0
 8002e8c:	6a7a      	ldr	r2, [r7, #36]	; 0x24
 8002e8e:	f002 0203 	and.w	r2, r2, #3
 8002e92:	0092      	lsls	r2, r2, #2
 8002e94:	4093      	lsls	r3, r2
 8002e96:	68fa      	ldr	r2, [r7, #12]
 8002e98:	4313      	orrs	r3, r2
 8002e9a:	60fb      	str	r3, [r7, #12]
        AFIO->EXTICR[position >> 2u] = temp;
 8002e9c:	493a      	ldr	r1, [pc, #232]	; (8002f88 <HAL_GPIO_Init+0x29c>)
 8002e9e:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 8002ea0:	089b      	lsrs	r3, r3, #2
 8002ea2:	3302      	adds	r3, #2
 8002ea4:	68fa      	ldr	r2, [r7, #12]
 8002ea6:	f841 2023 	str.w	r2, [r1, r3, lsl #2]


        /* Configure the interrupt mask */
        if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
 8002eaa:	683b      	ldr	r3, [r7, #0]
 8002eac:	685b      	ldr	r3, [r3, #4]
 8002eae:	f403 3380 	and.w	r3, r3, #65536	; 0x10000
 8002eb2:	2b00      	cmp	r3, #0
 8002eb4:	d006      	beq.n	8002ec4 <HAL_GPIO_Init+0x1d8>
        {
          SET_BIT(EXTI->IMR, iocurrent);
 8002eb6:	4b39      	ldr	r3, [pc, #228]	; (8002f9c <HAL_GPIO_Init+0x2b0>)
 8002eb8:	681a      	ldr	r2, [r3, #0]
 8002eba:	4938      	ldr	r1, [pc, #224]	; (8002f9c <HAL_GPIO_Init+0x2b0>)
 8002ebc:	69bb      	ldr	r3, [r7, #24]
 8002ebe:	4313      	orrs	r3, r2
 8002ec0:	600b      	str	r3, [r1, #0]
 8002ec2:	e006      	b.n	8002ed2 <HAL_GPIO_Init+0x1e6>
        }
        else
        {
          CLEAR_BIT(EXTI->IMR, iocurrent);
 8002ec4:	4b35      	ldr	r3, [pc, #212]	; (8002f9c <HAL_GPIO_Init+0x2b0>)
 8002ec6:	681a      	ldr	r2, [r3, #0]
 8002ec8:	69bb      	ldr	r3, [r7, #24]
 8002eca:	43db      	mvns	r3, r3
 8002ecc:	4933      	ldr	r1, [pc, #204]	; (8002f9c <HAL_GPIO_Init+0x2b0>)
 8002ece:	4013      	ands	r3, r2
 8002ed0:	600b      	str	r3, [r1, #0]
        }

        /* Configure the event mask */
        if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
 8002ed2:	683b      	ldr	r3, [r7, #0]
 8002ed4:	685b      	ldr	r3, [r3, #4]
 8002ed6:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 8002eda:	2b00      	cmp	r3, #0
 8002edc:	d006      	beq.n	8002eec <HAL_GPIO_Init+0x200>
        {
          SET_BIT(EXTI->EMR, iocurrent);
 8002ede:	4b2f      	ldr	r3, [pc, #188]	; (8002f9c <HAL_GPIO_Init+0x2b0>)
 8002ee0:	685a      	ldr	r2, [r3, #4]
 8002ee2:	492e      	ldr	r1, [pc, #184]	; (8002f9c <HAL_GPIO_Init+0x2b0>)
 8002ee4:	69bb      	ldr	r3, [r7, #24]
 8002ee6:	4313      	orrs	r3, r2
 8002ee8:	604b      	str	r3, [r1, #4]
 8002eea:	e006      	b.n	8002efa <HAL_GPIO_Init+0x20e>
        }
        else
        {
          CLEAR_BIT(EXTI->EMR, iocurrent);
 8002eec:	4b2b      	ldr	r3, [pc, #172]	; (8002f9c <HAL_GPIO_Init+0x2b0>)
 8002eee:	685a      	ldr	r2, [r3, #4]
 8002ef0:	69bb      	ldr	r3, [r7, #24]
 8002ef2:	43db      	mvns	r3, r3
 8002ef4:	4929      	ldr	r1, [pc, #164]	; (8002f9c <HAL_GPIO_Init+0x2b0>)
 8002ef6:	4013      	ands	r3, r2
 8002ef8:	604b      	str	r3, [r1, #4]
        }

        /* Enable or disable the rising trigger */
        if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
 8002efa:	683b      	ldr	r3, [r7, #0]
 8002efc:	685b      	ldr	r3, [r3, #4]
 8002efe:	f403 1380 	and.w	r3, r3, #1048576	; 0x100000
 8002f02:	2b00      	cmp	r3, #0
 8002f04:	d006      	beq.n	8002f14 <HAL_GPIO_Init+0x228>
        {
          SET_BIT(EXTI->RTSR, iocurrent);
 8002f06:	4b25      	ldr	r3, [pc, #148]	; (8002f9c <HAL_GPIO_Init+0x2b0>)
 8002f08:	689a      	ldr	r2, [r3, #8]
 8002f0a:	4924      	ldr	r1, [pc, #144]	; (8002f9c <HAL_GPIO_Init+0x2b0>)
 8002f0c:	69bb      	ldr	r3, [r7, #24]
 8002f0e:	4313      	orrs	r3, r2
 8002f10:	608b      	str	r3, [r1, #8]
 8002f12:	e006      	b.n	8002f22 <HAL_GPIO_Init+0x236>
        }
        else
        {
          CLEAR_BIT(EXTI->RTSR, iocurrent);
 8002f14:	4b21      	ldr	r3, [pc, #132]	; (8002f9c <HAL_GPIO_Init+0x2b0>)
 8002f16:	689a      	ldr	r2, [r3, #8]
 8002f18:	69bb      	ldr	r3, [r7, #24]
 8002f1a:	43db      	mvns	r3, r3
 8002f1c:	491f      	ldr	r1, [pc, #124]	; (8002f9c <HAL_GPIO_Init+0x2b0>)
 8002f1e:	4013      	ands	r3, r2
 8002f20:	608b      	str	r3, [r1, #8]
        }

        /* Enable or disable the falling trigger */
        if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
 8002f22:	683b      	ldr	r3, [r7, #0]
 8002f24:	685b      	ldr	r3, [r3, #4]
 8002f26:	f403 1300 	and.w	r3, r3, #2097152	; 0x200000
 8002f2a:	2b00      	cmp	r3, #0
 8002f2c:	d006      	beq.n	8002f3c <HAL_GPIO_Init+0x250>
        {
          SET_BIT(EXTI->FTSR, iocurrent);
 8002f2e:	4b1b      	ldr	r3, [pc, #108]	; (8002f9c <HAL_GPIO_Init+0x2b0>)
 8002f30:	68da      	ldr	r2, [r3, #12]
 8002f32:	491a      	ldr	r1, [pc, #104]	; (8002f9c <HAL_GPIO_Init+0x2b0>)
 8002f34:	69bb      	ldr	r3, [r7, #24]
 8002f36:	4313      	orrs	r3, r2
 8002f38:	60cb      	str	r3, [r1, #12]
 8002f3a:	e006      	b.n	8002f4a <HAL_GPIO_Init+0x25e>
        }
        else
        {
          CLEAR_BIT(EXTI->FTSR, iocurrent);
 8002f3c:	4b17      	ldr	r3, [pc, #92]	; (8002f9c <HAL_GPIO_Init+0x2b0>)
 8002f3e:	68da      	ldr	r2, [r3, #12]
 8002f40:	69bb      	ldr	r3, [r7, #24]
 8002f42:	43db      	mvns	r3, r3
 8002f44:	4915      	ldr	r1, [pc, #84]	; (8002f9c <HAL_GPIO_Init+0x2b0>)
 8002f46:	4013      	ands	r3, r2
 8002f48:	60cb      	str	r3, [r1, #12]
        }
      }
    }

	position++;
 8002f4a:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 8002f4c:	3301      	adds	r3, #1
 8002f4e:	627b      	str	r3, [r7, #36]	; 0x24
  while (((GPIO_Init->Pin) >> position) != 0x00u)
 8002f50:	683b      	ldr	r3, [r7, #0]
 8002f52:	681a      	ldr	r2, [r3, #0]
 8002f54:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 8002f56:	fa22 f303 	lsr.w	r3, r2, r3
 8002f5a:	2b00      	cmp	r3, #0
 8002f5c:	f47f aed0 	bne.w	8002d00 <HAL_GPIO_Init+0x14>
  }
}
 8002f60:	bf00      	nop
 8002f62:	372c      	adds	r7, #44	; 0x2c
 8002f64:	46bd      	mov	sp, r7
 8002f66:	bc80      	pop	{r7}
 8002f68:	4770      	bx	lr
 8002f6a:	bf00      	nop
 8002f6c:	10210000 	.word	0x10210000
 8002f70:	10110000 	.word	0x10110000
 8002f74:	10120000 	.word	0x10120000
 8002f78:	10310000 	.word	0x10310000
 8002f7c:	10320000 	.word	0x10320000
 8002f80:	10220000 	.word	0x10220000
 8002f84:	40021000 	.word	0x40021000
 8002f88:	40010000 	.word	0x40010000
 8002f8c:	40010800 	.word	0x40010800
 8002f90:	40010c00 	.word	0x40010c00
 8002f94:	40011000 	.word	0x40011000
 8002f98:	40011400 	.word	0x40011400
 8002f9c:	40010400 	.word	0x40010400

08002fa0 <HAL_GPIO_WritePin>:
  *            @arg GPIO_PIN_RESET: to clear the port pin
  *            @arg GPIO_PIN_SET: to set the port pin
  * @retval None
  */
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
 8002fa0:	b480      	push	{r7}
 8002fa2:	b083      	sub	sp, #12
 8002fa4:	af00      	add	r7, sp, #0
 8002fa6:	6078      	str	r0, [r7, #4]
 8002fa8:	460b      	mov	r3, r1
 8002faa:	807b      	strh	r3, [r7, #2]
 8002fac:	4613      	mov	r3, r2
 8002fae:	707b      	strb	r3, [r7, #1]
  /* Check the parameters */
  assert_param(IS_GPIO_PIN(GPIO_Pin));
  assert_param(IS_GPIO_PIN_ACTION(PinState));

  if (PinState != GPIO_PIN_RESET)
 8002fb0:	787b      	ldrb	r3, [r7, #1]
 8002fb2:	2b00      	cmp	r3, #0
 8002fb4:	d003      	beq.n	8002fbe <HAL_GPIO_WritePin+0x1e>
  {
    GPIOx->BSRR = GPIO_Pin;
 8002fb6:	887a      	ldrh	r2, [r7, #2]
 8002fb8:	687b      	ldr	r3, [r7, #4]
 8002fba:	611a      	str	r2, [r3, #16]
  }
  else
  {
    GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u;
  }
}
 8002fbc:	e003      	b.n	8002fc6 <HAL_GPIO_WritePin+0x26>
    GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u;
 8002fbe:	887b      	ldrh	r3, [r7, #2]
 8002fc0:	041a      	lsls	r2, r3, #16
 8002fc2:	687b      	ldr	r3, [r7, #4]
 8002fc4:	611a      	str	r2, [r3, #16]
}
 8002fc6:	bf00      	nop
 8002fc8:	370c      	adds	r7, #12
 8002fca:	46bd      	mov	sp, r7
 8002fcc:	bc80      	pop	{r7}
 8002fce:	4770      	bx	lr

08002fd0 <HAL_RCC_OscConfig>:
  *         supported by this macro. User should request a transition to HSE Off
  *         first and then HSE On or HSE Bypass.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
{
 8002fd0:	b580      	push	{r7, lr}
 8002fd2:	b086      	sub	sp, #24
 8002fd4:	af00      	add	r7, sp, #0
 8002fd6:	6078      	str	r0, [r7, #4]
  uint32_t tickstart;
  uint32_t pll_config;

  /* Check Null pointer */
  if (RCC_OscInitStruct == NULL)
 8002fd8:	687b      	ldr	r3, [r7, #4]
 8002fda:	2b00      	cmp	r3, #0
 8002fdc:	d101      	bne.n	8002fe2 <HAL_RCC_OscConfig+0x12>
  {
    return HAL_ERROR;
 8002fde:	2301      	movs	r3, #1
 8002fe0:	e26c      	b.n	80034bc <HAL_RCC_OscConfig+0x4ec>

  /* Check the parameters */
  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));

  /*------------------------------- HSE Configuration ------------------------*/
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
 8002fe2:	687b      	ldr	r3, [r7, #4]
 8002fe4:	681b      	ldr	r3, [r3, #0]
 8002fe6:	f003 0301 	and.w	r3, r3, #1
 8002fea:	2b00      	cmp	r3, #0
 8002fec:	f000 8087 	beq.w	80030fe <HAL_RCC_OscConfig+0x12e>
  {
    /* Check the parameters */
    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));

    /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
    if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
 8002ff0:	4b92      	ldr	r3, [pc, #584]	; (800323c <HAL_RCC_OscConfig+0x26c>)
 8002ff2:	685b      	ldr	r3, [r3, #4]
 8002ff4:	f003 030c 	and.w	r3, r3, #12
 8002ff8:	2b04      	cmp	r3, #4
 8002ffa:	d00c      	beq.n	8003016 <HAL_RCC_OscConfig+0x46>
        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
 8002ffc:	4b8f      	ldr	r3, [pc, #572]	; (800323c <HAL_RCC_OscConfig+0x26c>)
 8002ffe:	685b      	ldr	r3, [r3, #4]
 8003000:	f003 030c 	and.w	r3, r3, #12
 8003004:	2b08      	cmp	r3, #8
 8003006:	d112      	bne.n	800302e <HAL_RCC_OscConfig+0x5e>
 8003008:	4b8c      	ldr	r3, [pc, #560]	; (800323c <HAL_RCC_OscConfig+0x26c>)
 800300a:	685b      	ldr	r3, [r3, #4]
 800300c:	f403 3380 	and.w	r3, r3, #65536	; 0x10000
 8003010:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
 8003014:	d10b      	bne.n	800302e <HAL_RCC_OscConfig+0x5e>
    {
      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
 8003016:	4b89      	ldr	r3, [pc, #548]	; (800323c <HAL_RCC_OscConfig+0x26c>)
 8003018:	681b      	ldr	r3, [r3, #0]
 800301a:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 800301e:	2b00      	cmp	r3, #0
 8003020:	d06c      	beq.n	80030fc <HAL_RCC_OscConfig+0x12c>
 8003022:	687b      	ldr	r3, [r7, #4]
 8003024:	685b      	ldr	r3, [r3, #4]
 8003026:	2b00      	cmp	r3, #0
 8003028:	d168      	bne.n	80030fc <HAL_RCC_OscConfig+0x12c>
      {
        return HAL_ERROR;
 800302a:	2301      	movs	r3, #1
 800302c:	e246      	b.n	80034bc <HAL_RCC_OscConfig+0x4ec>
      }
    }
    else
    {
      /* Set the new HSE configuration ---------------------------------------*/
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 800302e:	687b      	ldr	r3, [r7, #4]
 8003030:	685b      	ldr	r3, [r3, #4]
 8003032:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
 8003036:	d106      	bne.n	8003046 <HAL_RCC_OscConfig+0x76>
 8003038:	4b80      	ldr	r3, [pc, #512]	; (800323c <HAL_RCC_OscConfig+0x26c>)
 800303a:	681b      	ldr	r3, [r3, #0]
 800303c:	4a7f      	ldr	r2, [pc, #508]	; (800323c <HAL_RCC_OscConfig+0x26c>)
 800303e:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
 8003042:	6013      	str	r3, [r2, #0]
 8003044:	e02e      	b.n	80030a4 <HAL_RCC_OscConfig+0xd4>
 8003046:	687b      	ldr	r3, [r7, #4]
 8003048:	685b      	ldr	r3, [r3, #4]
 800304a:	2b00      	cmp	r3, #0
 800304c:	d10c      	bne.n	8003068 <HAL_RCC_OscConfig+0x98>
 800304e:	4b7b      	ldr	r3, [pc, #492]	; (800323c <HAL_RCC_OscConfig+0x26c>)
 8003050:	681b      	ldr	r3, [r3, #0]
 8003052:	4a7a      	ldr	r2, [pc, #488]	; (800323c <HAL_RCC_OscConfig+0x26c>)
 8003054:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
 8003058:	6013      	str	r3, [r2, #0]
 800305a:	4b78      	ldr	r3, [pc, #480]	; (800323c <HAL_RCC_OscConfig+0x26c>)
 800305c:	681b      	ldr	r3, [r3, #0]
 800305e:	4a77      	ldr	r2, [pc, #476]	; (800323c <HAL_RCC_OscConfig+0x26c>)
 8003060:	f423 2380 	bic.w	r3, r3, #262144	; 0x40000
 8003064:	6013      	str	r3, [r2, #0]
 8003066:	e01d      	b.n	80030a4 <HAL_RCC_OscConfig+0xd4>
 8003068:	687b      	ldr	r3, [r7, #4]
 800306a:	685b      	ldr	r3, [r3, #4]
 800306c:	f5b3 2fa0 	cmp.w	r3, #327680	; 0x50000
 8003070:	d10c      	bne.n	800308c <HAL_RCC_OscConfig+0xbc>
 8003072:	4b72      	ldr	r3, [pc, #456]	; (800323c <HAL_RCC_OscConfig+0x26c>)
 8003074:	681b      	ldr	r3, [r3, #0]
 8003076:	4a71      	ldr	r2, [pc, #452]	; (800323c <HAL_RCC_OscConfig+0x26c>)
 8003078:	f443 2380 	orr.w	r3, r3, #262144	; 0x40000
 800307c:	6013      	str	r3, [r2, #0]
 800307e:	4b6f      	ldr	r3, [pc, #444]	; (800323c <HAL_RCC_OscConfig+0x26c>)
 8003080:	681b      	ldr	r3, [r3, #0]
 8003082:	4a6e      	ldr	r2, [pc, #440]	; (800323c <HAL_RCC_OscConfig+0x26c>)
 8003084:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
 8003088:	6013      	str	r3, [r2, #0]
 800308a:	e00b      	b.n	80030a4 <HAL_RCC_OscConfig+0xd4>
 800308c:	4b6b      	ldr	r3, [pc, #428]	; (800323c <HAL_RCC_OscConfig+0x26c>)
 800308e:	681b      	ldr	r3, [r3, #0]
 8003090:	4a6a      	ldr	r2, [pc, #424]	; (800323c <HAL_RCC_OscConfig+0x26c>)
 8003092:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
 8003096:	6013      	str	r3, [r2, #0]
 8003098:	4b68      	ldr	r3, [pc, #416]	; (800323c <HAL_RCC_OscConfig+0x26c>)
 800309a:	681b      	ldr	r3, [r3, #0]
 800309c:	4a67      	ldr	r2, [pc, #412]	; (800323c <HAL_RCC_OscConfig+0x26c>)
 800309e:	f423 2380 	bic.w	r3, r3, #262144	; 0x40000
 80030a2:	6013      	str	r3, [r2, #0]


      /* Check the HSE State */
      if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
 80030a4:	687b      	ldr	r3, [r7, #4]
 80030a6:	685b      	ldr	r3, [r3, #4]
 80030a8:	2b00      	cmp	r3, #0
 80030aa:	d013      	beq.n	80030d4 <HAL_RCC_OscConfig+0x104>
      {
        /* Get Start Tick */
        tickstart = HAL_GetTick();
 80030ac:	f7fe fbce 	bl	800184c <HAL_GetTick>
 80030b0:	6138      	str	r0, [r7, #16]

        /* Wait till HSE is ready */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 80030b2:	e008      	b.n	80030c6 <HAL_RCC_OscConfig+0xf6>
        {
          if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
 80030b4:	f7fe fbca 	bl	800184c <HAL_GetTick>
 80030b8:	4602      	mov	r2, r0
 80030ba:	693b      	ldr	r3, [r7, #16]
 80030bc:	1ad3      	subs	r3, r2, r3
 80030be:	2b64      	cmp	r3, #100	; 0x64
 80030c0:	d901      	bls.n	80030c6 <HAL_RCC_OscConfig+0xf6>
          {
            return HAL_TIMEOUT;
 80030c2:	2303      	movs	r3, #3
 80030c4:	e1fa      	b.n	80034bc <HAL_RCC_OscConfig+0x4ec>
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 80030c6:	4b5d      	ldr	r3, [pc, #372]	; (800323c <HAL_RCC_OscConfig+0x26c>)
 80030c8:	681b      	ldr	r3, [r3, #0]
 80030ca:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 80030ce:	2b00      	cmp	r3, #0
 80030d0:	d0f0      	beq.n	80030b4 <HAL_RCC_OscConfig+0xe4>
 80030d2:	e014      	b.n	80030fe <HAL_RCC_OscConfig+0x12e>
        }
      }
      else
      {
        /* Get Start Tick */
        tickstart = HAL_GetTick();
 80030d4:	f7fe fbba 	bl	800184c <HAL_GetTick>
 80030d8:	6138      	str	r0, [r7, #16]

        /* Wait till HSE is disabled */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
 80030da:	e008      	b.n	80030ee <HAL_RCC_OscConfig+0x11e>
        {
          if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
 80030dc:	f7fe fbb6 	bl	800184c <HAL_GetTick>
 80030e0:	4602      	mov	r2, r0
 80030e2:	693b      	ldr	r3, [r7, #16]
 80030e4:	1ad3      	subs	r3, r2, r3
 80030e6:	2b64      	cmp	r3, #100	; 0x64
 80030e8:	d901      	bls.n	80030ee <HAL_RCC_OscConfig+0x11e>
          {
            return HAL_TIMEOUT;
 80030ea:	2303      	movs	r3, #3
 80030ec:	e1e6      	b.n	80034bc <HAL_RCC_OscConfig+0x4ec>
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
 80030ee:	4b53      	ldr	r3, [pc, #332]	; (800323c <HAL_RCC_OscConfig+0x26c>)
 80030f0:	681b      	ldr	r3, [r3, #0]
 80030f2:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 80030f6:	2b00      	cmp	r3, #0
 80030f8:	d1f0      	bne.n	80030dc <HAL_RCC_OscConfig+0x10c>
 80030fa:	e000      	b.n	80030fe <HAL_RCC_OscConfig+0x12e>
      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
 80030fc:	bf00      	nop
        }
      }
    }
  }
  /*----------------------------- HSI Configuration --------------------------*/
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
 80030fe:	687b      	ldr	r3, [r7, #4]
 8003100:	681b      	ldr	r3, [r3, #0]
 8003102:	f003 0302 	and.w	r3, r3, #2
 8003106:	2b00      	cmp	r3, #0
 8003108:	d063      	beq.n	80031d2 <HAL_RCC_OscConfig+0x202>
    /* Check the parameters */
    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
    assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));

    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
    if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
 800310a:	4b4c      	ldr	r3, [pc, #304]	; (800323c <HAL_RCC_OscConfig+0x26c>)
 800310c:	685b      	ldr	r3, [r3, #4]
 800310e:	f003 030c 	and.w	r3, r3, #12
 8003112:	2b00      	cmp	r3, #0
 8003114:	d00b      	beq.n	800312e <HAL_RCC_OscConfig+0x15e>
        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
 8003116:	4b49      	ldr	r3, [pc, #292]	; (800323c <HAL_RCC_OscConfig+0x26c>)
 8003118:	685b      	ldr	r3, [r3, #4]
 800311a:	f003 030c 	and.w	r3, r3, #12
 800311e:	2b08      	cmp	r3, #8
 8003120:	d11c      	bne.n	800315c <HAL_RCC_OscConfig+0x18c>
 8003122:	4b46      	ldr	r3, [pc, #280]	; (800323c <HAL_RCC_OscConfig+0x26c>)
 8003124:	685b      	ldr	r3, [r3, #4]
 8003126:	f403 3380 	and.w	r3, r3, #65536	; 0x10000
 800312a:	2b00      	cmp	r3, #0
 800312c:	d116      	bne.n	800315c <HAL_RCC_OscConfig+0x18c>
    {
      /* When HSI is used as system clock it will not disabled */
      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
 800312e:	4b43      	ldr	r3, [pc, #268]	; (800323c <HAL_RCC_OscConfig+0x26c>)
 8003130:	681b      	ldr	r3, [r3, #0]
 8003132:	f003 0302 	and.w	r3, r3, #2
 8003136:	2b00      	cmp	r3, #0
 8003138:	d005      	beq.n	8003146 <HAL_RCC_OscConfig+0x176>
 800313a:	687b      	ldr	r3, [r7, #4]
 800313c:	691b      	ldr	r3, [r3, #16]
 800313e:	2b01      	cmp	r3, #1
 8003140:	d001      	beq.n	8003146 <HAL_RCC_OscConfig+0x176>
      {
        return HAL_ERROR;
 8003142:	2301      	movs	r3, #1
 8003144:	e1ba      	b.n	80034bc <HAL_RCC_OscConfig+0x4ec>
      }
      /* Otherwise, just the calibration is allowed */
      else
      {
        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 8003146:	4b3d      	ldr	r3, [pc, #244]	; (800323c <HAL_RCC_OscConfig+0x26c>)
 8003148:	681b      	ldr	r3, [r3, #0]
 800314a:	f023 02f8 	bic.w	r2, r3, #248	; 0xf8
 800314e:	687b      	ldr	r3, [r7, #4]
 8003150:	695b      	ldr	r3, [r3, #20]
 8003152:	00db      	lsls	r3, r3, #3
 8003154:	4939      	ldr	r1, [pc, #228]	; (800323c <HAL_RCC_OscConfig+0x26c>)
 8003156:	4313      	orrs	r3, r2
 8003158:	600b      	str	r3, [r1, #0]
      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
 800315a:	e03a      	b.n	80031d2 <HAL_RCC_OscConfig+0x202>
      }
    }
    else
    {
      /* Check the HSI State */
      if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
 800315c:	687b      	ldr	r3, [r7, #4]
 800315e:	691b      	ldr	r3, [r3, #16]
 8003160:	2b00      	cmp	r3, #0
 8003162:	d020      	beq.n	80031a6 <HAL_RCC_OscConfig+0x1d6>
      {
        /* Enable the Internal High Speed oscillator (HSI). */
        __HAL_RCC_HSI_ENABLE();
 8003164:	4b36      	ldr	r3, [pc, #216]	; (8003240 <HAL_RCC_OscConfig+0x270>)
 8003166:	2201      	movs	r2, #1
 8003168:	601a      	str	r2, [r3, #0]

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 800316a:	f7fe fb6f 	bl	800184c <HAL_GetTick>
 800316e:	6138      	str	r0, [r7, #16]

        /* Wait till HSI is ready */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 8003170:	e008      	b.n	8003184 <HAL_RCC_OscConfig+0x1b4>
        {
          if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
 8003172:	f7fe fb6b 	bl	800184c <HAL_GetTick>
 8003176:	4602      	mov	r2, r0
 8003178:	693b      	ldr	r3, [r7, #16]
 800317a:	1ad3      	subs	r3, r2, r3
 800317c:	2b02      	cmp	r3, #2
 800317e:	d901      	bls.n	8003184 <HAL_RCC_OscConfig+0x1b4>
          {
            return HAL_TIMEOUT;
 8003180:	2303      	movs	r3, #3
 8003182:	e19b      	b.n	80034bc <HAL_RCC_OscConfig+0x4ec>
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 8003184:	4b2d      	ldr	r3, [pc, #180]	; (800323c <HAL_RCC_OscConfig+0x26c>)
 8003186:	681b      	ldr	r3, [r3, #0]
 8003188:	f003 0302 	and.w	r3, r3, #2
 800318c:	2b00      	cmp	r3, #0
 800318e:	d0f0      	beq.n	8003172 <HAL_RCC_OscConfig+0x1a2>
          }
        }

        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 8003190:	4b2a      	ldr	r3, [pc, #168]	; (800323c <HAL_RCC_OscConfig+0x26c>)
 8003192:	681b      	ldr	r3, [r3, #0]
 8003194:	f023 02f8 	bic.w	r2, r3, #248	; 0xf8
 8003198:	687b      	ldr	r3, [r7, #4]
 800319a:	695b      	ldr	r3, [r3, #20]
 800319c:	00db      	lsls	r3, r3, #3
 800319e:	4927      	ldr	r1, [pc, #156]	; (800323c <HAL_RCC_OscConfig+0x26c>)
 80031a0:	4313      	orrs	r3, r2
 80031a2:	600b      	str	r3, [r1, #0]
 80031a4:	e015      	b.n	80031d2 <HAL_RCC_OscConfig+0x202>
      }
      else
      {
        /* Disable the Internal High Speed oscillator (HSI). */
        __HAL_RCC_HSI_DISABLE();
 80031a6:	4b26      	ldr	r3, [pc, #152]	; (8003240 <HAL_RCC_OscConfig+0x270>)
 80031a8:	2200      	movs	r2, #0
 80031aa:	601a      	str	r2, [r3, #0]

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 80031ac:	f7fe fb4e 	bl	800184c <HAL_GetTick>
 80031b0:	6138      	str	r0, [r7, #16]

        /* Wait till HSI is disabled */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
 80031b2:	e008      	b.n	80031c6 <HAL_RCC_OscConfig+0x1f6>
        {
          if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
 80031b4:	f7fe fb4a 	bl	800184c <HAL_GetTick>
 80031b8:	4602      	mov	r2, r0
 80031ba:	693b      	ldr	r3, [r7, #16]
 80031bc:	1ad3      	subs	r3, r2, r3
 80031be:	2b02      	cmp	r3, #2
 80031c0:	d901      	bls.n	80031c6 <HAL_RCC_OscConfig+0x1f6>
          {
            return HAL_TIMEOUT;
 80031c2:	2303      	movs	r3, #3
 80031c4:	e17a      	b.n	80034bc <HAL_RCC_OscConfig+0x4ec>
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
 80031c6:	4b1d      	ldr	r3, [pc, #116]	; (800323c <HAL_RCC_OscConfig+0x26c>)
 80031c8:	681b      	ldr	r3, [r3, #0]
 80031ca:	f003 0302 	and.w	r3, r3, #2
 80031ce:	2b00      	cmp	r3, #0
 80031d0:	d1f0      	bne.n	80031b4 <HAL_RCC_OscConfig+0x1e4>
        }
      }
    }
  }
  /*------------------------------ LSI Configuration -------------------------*/
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
 80031d2:	687b      	ldr	r3, [r7, #4]
 80031d4:	681b      	ldr	r3, [r3, #0]
 80031d6:	f003 0308 	and.w	r3, r3, #8
 80031da:	2b00      	cmp	r3, #0
 80031dc:	d03a      	beq.n	8003254 <HAL_RCC_OscConfig+0x284>
  {
    /* Check the parameters */
    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));

    /* Check the LSI State */
    if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
 80031de:	687b      	ldr	r3, [r7, #4]
 80031e0:	699b      	ldr	r3, [r3, #24]
 80031e2:	2b00      	cmp	r3, #0
 80031e4:	d019      	beq.n	800321a <HAL_RCC_OscConfig+0x24a>
    {
      /* Enable the Internal Low Speed oscillator (LSI). */
      __HAL_RCC_LSI_ENABLE();
 80031e6:	4b17      	ldr	r3, [pc, #92]	; (8003244 <HAL_RCC_OscConfig+0x274>)
 80031e8:	2201      	movs	r2, #1
 80031ea:	601a      	str	r2, [r3, #0]

      /* Get Start Tick */
      tickstart = HAL_GetTick();
 80031ec:	f7fe fb2e 	bl	800184c <HAL_GetTick>
 80031f0:	6138      	str	r0, [r7, #16]

      /* Wait till LSI is ready */
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
 80031f2:	e008      	b.n	8003206 <HAL_RCC_OscConfig+0x236>
      {
        if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
 80031f4:	f7fe fb2a 	bl	800184c <HAL_GetTick>
 80031f8:	4602      	mov	r2, r0
 80031fa:	693b      	ldr	r3, [r7, #16]
 80031fc:	1ad3      	subs	r3, r2, r3
 80031fe:	2b02      	cmp	r3, #2
 8003200:	d901      	bls.n	8003206 <HAL_RCC_OscConfig+0x236>
        {
          return HAL_TIMEOUT;
 8003202:	2303      	movs	r3, #3
 8003204:	e15a      	b.n	80034bc <HAL_RCC_OscConfig+0x4ec>
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
 8003206:	4b0d      	ldr	r3, [pc, #52]	; (800323c <HAL_RCC_OscConfig+0x26c>)
 8003208:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 800320a:	f003 0302 	and.w	r3, r3, #2
 800320e:	2b00      	cmp	r3, #0
 8003210:	d0f0      	beq.n	80031f4 <HAL_RCC_OscConfig+0x224>
        }
      }
      /*  To have a fully stabilized clock in the specified range, a software delay of 1ms
          should be added.*/
      RCC_Delay(1);
 8003212:	2001      	movs	r0, #1
 8003214:	f000 fad6 	bl	80037c4 <RCC_Delay>
 8003218:	e01c      	b.n	8003254 <HAL_RCC_OscConfig+0x284>
    }
    else
    {
      /* Disable the Internal Low Speed oscillator (LSI). */
      __HAL_RCC_LSI_DISABLE();
 800321a:	4b0a      	ldr	r3, [pc, #40]	; (8003244 <HAL_RCC_OscConfig+0x274>)
 800321c:	2200      	movs	r2, #0
 800321e:	601a      	str	r2, [r3, #0]

      /* Get Start Tick */
      tickstart = HAL_GetTick();
 8003220:	f7fe fb14 	bl	800184c <HAL_GetTick>
 8003224:	6138      	str	r0, [r7, #16]

      /* Wait till LSI is disabled */
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
 8003226:	e00f      	b.n	8003248 <HAL_RCC_OscConfig+0x278>
      {
        if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
 8003228:	f7fe fb10 	bl	800184c <HAL_GetTick>
 800322c:	4602      	mov	r2, r0
 800322e:	693b      	ldr	r3, [r7, #16]
 8003230:	1ad3      	subs	r3, r2, r3
 8003232:	2b02      	cmp	r3, #2
 8003234:	d908      	bls.n	8003248 <HAL_RCC_OscConfig+0x278>
        {
          return HAL_TIMEOUT;
 8003236:	2303      	movs	r3, #3
 8003238:	e140      	b.n	80034bc <HAL_RCC_OscConfig+0x4ec>
 800323a:	bf00      	nop
 800323c:	40021000 	.word	0x40021000
 8003240:	42420000 	.word	0x42420000
 8003244:	42420480 	.word	0x42420480
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
 8003248:	4b9e      	ldr	r3, [pc, #632]	; (80034c4 <HAL_RCC_OscConfig+0x4f4>)
 800324a:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 800324c:	f003 0302 	and.w	r3, r3, #2
 8003250:	2b00      	cmp	r3, #0
 8003252:	d1e9      	bne.n	8003228 <HAL_RCC_OscConfig+0x258>
        }
      }
    }
  }
  /*------------------------------ LSE Configuration -------------------------*/
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
 8003254:	687b      	ldr	r3, [r7, #4]
 8003256:	681b      	ldr	r3, [r3, #0]
 8003258:	f003 0304 	and.w	r3, r3, #4
 800325c:	2b00      	cmp	r3, #0
 800325e:	f000 80a6 	beq.w	80033ae <HAL_RCC_OscConfig+0x3de>
  {
    FlagStatus       pwrclkchanged = RESET;
 8003262:	2300      	movs	r3, #0
 8003264:	75fb      	strb	r3, [r7, #23]
    /* Check the parameters */
    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));

    /* Update LSE configuration in Backup Domain control register    */
    /* Requires to enable write access to Backup Domain of necessary */
    if (__HAL_RCC_PWR_IS_CLK_DISABLED())
 8003266:	4b97      	ldr	r3, [pc, #604]	; (80034c4 <HAL_RCC_OscConfig+0x4f4>)
 8003268:	69db      	ldr	r3, [r3, #28]
 800326a:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 800326e:	2b00      	cmp	r3, #0
 8003270:	d10d      	bne.n	800328e <HAL_RCC_OscConfig+0x2be>
    {
      __HAL_RCC_PWR_CLK_ENABLE();
 8003272:	4b94      	ldr	r3, [pc, #592]	; (80034c4 <HAL_RCC_OscConfig+0x4f4>)
 8003274:	69db      	ldr	r3, [r3, #28]
 8003276:	4a93      	ldr	r2, [pc, #588]	; (80034c4 <HAL_RCC_OscConfig+0x4f4>)
 8003278:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
 800327c:	61d3      	str	r3, [r2, #28]
 800327e:	4b91      	ldr	r3, [pc, #580]	; (80034c4 <HAL_RCC_OscConfig+0x4f4>)
 8003280:	69db      	ldr	r3, [r3, #28]
 8003282:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8003286:	60bb      	str	r3, [r7, #8]
 8003288:	68bb      	ldr	r3, [r7, #8]
      pwrclkchanged = SET;
 800328a:	2301      	movs	r3, #1
 800328c:	75fb      	strb	r3, [r7, #23]
    }

    if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 800328e:	4b8e      	ldr	r3, [pc, #568]	; (80034c8 <HAL_RCC_OscConfig+0x4f8>)
 8003290:	681b      	ldr	r3, [r3, #0]
 8003292:	f403 7380 	and.w	r3, r3, #256	; 0x100
 8003296:	2b00      	cmp	r3, #0
 8003298:	d118      	bne.n	80032cc <HAL_RCC_OscConfig+0x2fc>
    {
      /* Enable write access to Backup domain */
      SET_BIT(PWR->CR, PWR_CR_DBP);
 800329a:	4b8b      	ldr	r3, [pc, #556]	; (80034c8 <HAL_RCC_OscConfig+0x4f8>)
 800329c:	681b      	ldr	r3, [r3, #0]
 800329e:	4a8a      	ldr	r2, [pc, #552]	; (80034c8 <HAL_RCC_OscConfig+0x4f8>)
 80032a0:	f443 7380 	orr.w	r3, r3, #256	; 0x100
 80032a4:	6013      	str	r3, [r2, #0]

      /* Wait for Backup domain Write protection disable */
      tickstart = HAL_GetTick();
 80032a6:	f7fe fad1 	bl	800184c <HAL_GetTick>
 80032aa:	6138      	str	r0, [r7, #16]

      while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 80032ac:	e008      	b.n	80032c0 <HAL_RCC_OscConfig+0x2f0>
      {
        if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
 80032ae:	f7fe facd 	bl	800184c <HAL_GetTick>
 80032b2:	4602      	mov	r2, r0
 80032b4:	693b      	ldr	r3, [r7, #16]
 80032b6:	1ad3      	subs	r3, r2, r3
 80032b8:	2b64      	cmp	r3, #100	; 0x64
 80032ba:	d901      	bls.n	80032c0 <HAL_RCC_OscConfig+0x2f0>
        {
          return HAL_TIMEOUT;
 80032bc:	2303      	movs	r3, #3
 80032be:	e0fd      	b.n	80034bc <HAL_RCC_OscConfig+0x4ec>
      while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 80032c0:	4b81      	ldr	r3, [pc, #516]	; (80034c8 <HAL_RCC_OscConfig+0x4f8>)
 80032c2:	681b      	ldr	r3, [r3, #0]
 80032c4:	f403 7380 	and.w	r3, r3, #256	; 0x100
 80032c8:	2b00      	cmp	r3, #0
 80032ca:	d0f0      	beq.n	80032ae <HAL_RCC_OscConfig+0x2de>
        }
      }
    }

    /* Set the new LSE configuration -----------------------------------------*/
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 80032cc:	687b      	ldr	r3, [r7, #4]
 80032ce:	68db      	ldr	r3, [r3, #12]
 80032d0:	2b01      	cmp	r3, #1
 80032d2:	d106      	bne.n	80032e2 <HAL_RCC_OscConfig+0x312>
 80032d4:	4b7b      	ldr	r3, [pc, #492]	; (80034c4 <HAL_RCC_OscConfig+0x4f4>)
 80032d6:	6a1b      	ldr	r3, [r3, #32]
 80032d8:	4a7a      	ldr	r2, [pc, #488]	; (80034c4 <HAL_RCC_OscConfig+0x4f4>)
 80032da:	f043 0301 	orr.w	r3, r3, #1
 80032de:	6213      	str	r3, [r2, #32]
 80032e0:	e02d      	b.n	800333e <HAL_RCC_OscConfig+0x36e>
 80032e2:	687b      	ldr	r3, [r7, #4]
 80032e4:	68db      	ldr	r3, [r3, #12]
 80032e6:	2b00      	cmp	r3, #0
 80032e8:	d10c      	bne.n	8003304 <HAL_RCC_OscConfig+0x334>
 80032ea:	4b76      	ldr	r3, [pc, #472]	; (80034c4 <HAL_RCC_OscConfig+0x4f4>)
 80032ec:	6a1b      	ldr	r3, [r3, #32]
 80032ee:	4a75      	ldr	r2, [pc, #468]	; (80034c4 <HAL_RCC_OscConfig+0x4f4>)
 80032f0:	f023 0301 	bic.w	r3, r3, #1
 80032f4:	6213      	str	r3, [r2, #32]
 80032f6:	4b73      	ldr	r3, [pc, #460]	; (80034c4 <HAL_RCC_OscConfig+0x4f4>)
 80032f8:	6a1b      	ldr	r3, [r3, #32]
 80032fa:	4a72      	ldr	r2, [pc, #456]	; (80034c4 <HAL_RCC_OscConfig+0x4f4>)
 80032fc:	f023 0304 	bic.w	r3, r3, #4
 8003300:	6213      	str	r3, [r2, #32]
 8003302:	e01c      	b.n	800333e <HAL_RCC_OscConfig+0x36e>
 8003304:	687b      	ldr	r3, [r7, #4]
 8003306:	68db      	ldr	r3, [r3, #12]
 8003308:	2b05      	cmp	r3, #5
 800330a:	d10c      	bne.n	8003326 <HAL_RCC_OscConfig+0x356>
 800330c:	4b6d      	ldr	r3, [pc, #436]	; (80034c4 <HAL_RCC_OscConfig+0x4f4>)
 800330e:	6a1b      	ldr	r3, [r3, #32]
 8003310:	4a6c      	ldr	r2, [pc, #432]	; (80034c4 <HAL_RCC_OscConfig+0x4f4>)
 8003312:	f043 0304 	orr.w	r3, r3, #4
 8003316:	6213      	str	r3, [r2, #32]
 8003318:	4b6a      	ldr	r3, [pc, #424]	; (80034c4 <HAL_RCC_OscConfig+0x4f4>)
 800331a:	6a1b      	ldr	r3, [r3, #32]
 800331c:	4a69      	ldr	r2, [pc, #420]	; (80034c4 <HAL_RCC_OscConfig+0x4f4>)
 800331e:	f043 0301 	orr.w	r3, r3, #1
 8003322:	6213      	str	r3, [r2, #32]
 8003324:	e00b      	b.n	800333e <HAL_RCC_OscConfig+0x36e>
 8003326:	4b67      	ldr	r3, [pc, #412]	; (80034c4 <HAL_RCC_OscConfig+0x4f4>)
 8003328:	6a1b      	ldr	r3, [r3, #32]
 800332a:	4a66      	ldr	r2, [pc, #408]	; (80034c4 <HAL_RCC_OscConfig+0x4f4>)
 800332c:	f023 0301 	bic.w	r3, r3, #1
 8003330:	6213      	str	r3, [r2, #32]
 8003332:	4b64      	ldr	r3, [pc, #400]	; (80034c4 <HAL_RCC_OscConfig+0x4f4>)
 8003334:	6a1b      	ldr	r3, [r3, #32]
 8003336:	4a63      	ldr	r2, [pc, #396]	; (80034c4 <HAL_RCC_OscConfig+0x4f4>)
 8003338:	f023 0304 	bic.w	r3, r3, #4
 800333c:	6213      	str	r3, [r2, #32]
    /* Check the LSE State */
    if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
 800333e:	687b      	ldr	r3, [r7, #4]
 8003340:	68db      	ldr	r3, [r3, #12]
 8003342:	2b00      	cmp	r3, #0
 8003344:	d015      	beq.n	8003372 <HAL_RCC_OscConfig+0x3a2>
    {
      /* Get Start Tick */
      tickstart = HAL_GetTick();
 8003346:	f7fe fa81 	bl	800184c <HAL_GetTick>
 800334a:	6138      	str	r0, [r7, #16]

      /* Wait till LSE is ready */
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
 800334c:	e00a      	b.n	8003364 <HAL_RCC_OscConfig+0x394>
      {
        if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 800334e:	f7fe fa7d 	bl	800184c <HAL_GetTick>
 8003352:	4602      	mov	r2, r0
 8003354:	693b      	ldr	r3, [r7, #16]
 8003356:	1ad3      	subs	r3, r2, r3
 8003358:	f241 3288 	movw	r2, #5000	; 0x1388
 800335c:	4293      	cmp	r3, r2
 800335e:	d901      	bls.n	8003364 <HAL_RCC_OscConfig+0x394>
        {
          return HAL_TIMEOUT;
 8003360:	2303      	movs	r3, #3
 8003362:	e0ab      	b.n	80034bc <HAL_RCC_OscConfig+0x4ec>
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
 8003364:	4b57      	ldr	r3, [pc, #348]	; (80034c4 <HAL_RCC_OscConfig+0x4f4>)
 8003366:	6a1b      	ldr	r3, [r3, #32]
 8003368:	f003 0302 	and.w	r3, r3, #2
 800336c:	2b00      	cmp	r3, #0
 800336e:	d0ee      	beq.n	800334e <HAL_RCC_OscConfig+0x37e>
 8003370:	e014      	b.n	800339c <HAL_RCC_OscConfig+0x3cc>
      }
    }
    else
    {
      /* Get Start Tick */
      tickstart = HAL_GetTick();
 8003372:	f7fe fa6b 	bl	800184c <HAL_GetTick>
 8003376:	6138      	str	r0, [r7, #16]

      /* Wait till LSE is disabled */
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
 8003378:	e00a      	b.n	8003390 <HAL_RCC_OscConfig+0x3c0>
      {
        if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 800337a:	f7fe fa67 	bl	800184c <HAL_GetTick>
 800337e:	4602      	mov	r2, r0
 8003380:	693b      	ldr	r3, [r7, #16]
 8003382:	1ad3      	subs	r3, r2, r3
 8003384:	f241 3288 	movw	r2, #5000	; 0x1388
 8003388:	4293      	cmp	r3, r2
 800338a:	d901      	bls.n	8003390 <HAL_RCC_OscConfig+0x3c0>
        {
          return HAL_TIMEOUT;
 800338c:	2303      	movs	r3, #3
 800338e:	e095      	b.n	80034bc <HAL_RCC_OscConfig+0x4ec>
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
 8003390:	4b4c      	ldr	r3, [pc, #304]	; (80034c4 <HAL_RCC_OscConfig+0x4f4>)
 8003392:	6a1b      	ldr	r3, [r3, #32]
 8003394:	f003 0302 	and.w	r3, r3, #2
 8003398:	2b00      	cmp	r3, #0
 800339a:	d1ee      	bne.n	800337a <HAL_RCC_OscConfig+0x3aa>
        }
      }
    }

    /* Require to disable power clock if necessary */
    if (pwrclkchanged == SET)
 800339c:	7dfb      	ldrb	r3, [r7, #23]
 800339e:	2b01      	cmp	r3, #1
 80033a0:	d105      	bne.n	80033ae <HAL_RCC_OscConfig+0x3de>
    {
      __HAL_RCC_PWR_CLK_DISABLE();
 80033a2:	4b48      	ldr	r3, [pc, #288]	; (80034c4 <HAL_RCC_OscConfig+0x4f4>)
 80033a4:	69db      	ldr	r3, [r3, #28]
 80033a6:	4a47      	ldr	r2, [pc, #284]	; (80034c4 <HAL_RCC_OscConfig+0x4f4>)
 80033a8:	f023 5380 	bic.w	r3, r3, #268435456	; 0x10000000
 80033ac:	61d3      	str	r3, [r2, #28]

#endif /* RCC_CR_PLL2ON */
  /*-------------------------------- PLL Configuration -----------------------*/
  /* Check the parameters */
  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
 80033ae:	687b      	ldr	r3, [r7, #4]
 80033b0:	69db      	ldr	r3, [r3, #28]
 80033b2:	2b00      	cmp	r3, #0
 80033b4:	f000 8081 	beq.w	80034ba <HAL_RCC_OscConfig+0x4ea>
  {
    /* Check if the PLL is used as system clock or not */
    if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
 80033b8:	4b42      	ldr	r3, [pc, #264]	; (80034c4 <HAL_RCC_OscConfig+0x4f4>)
 80033ba:	685b      	ldr	r3, [r3, #4]
 80033bc:	f003 030c 	and.w	r3, r3, #12
 80033c0:	2b08      	cmp	r3, #8
 80033c2:	d061      	beq.n	8003488 <HAL_RCC_OscConfig+0x4b8>
    {
      if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
 80033c4:	687b      	ldr	r3, [r7, #4]
 80033c6:	69db      	ldr	r3, [r3, #28]
 80033c8:	2b02      	cmp	r3, #2
 80033ca:	d146      	bne.n	800345a <HAL_RCC_OscConfig+0x48a>
        /* Check the parameters */
        assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
        assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));

        /* Disable the main PLL. */
        __HAL_RCC_PLL_DISABLE();
 80033cc:	4b3f      	ldr	r3, [pc, #252]	; (80034cc <HAL_RCC_OscConfig+0x4fc>)
 80033ce:	2200      	movs	r2, #0
 80033d0:	601a      	str	r2, [r3, #0]

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 80033d2:	f7fe fa3b 	bl	800184c <HAL_GetTick>
 80033d6:	6138      	str	r0, [r7, #16]

        /* Wait till PLL is disabled */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
 80033d8:	e008      	b.n	80033ec <HAL_RCC_OscConfig+0x41c>
        {
          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
 80033da:	f7fe fa37 	bl	800184c <HAL_GetTick>
 80033de:	4602      	mov	r2, r0
 80033e0:	693b      	ldr	r3, [r7, #16]
 80033e2:	1ad3      	subs	r3, r2, r3
 80033e4:	2b02      	cmp	r3, #2
 80033e6:	d901      	bls.n	80033ec <HAL_RCC_OscConfig+0x41c>
          {
            return HAL_TIMEOUT;
 80033e8:	2303      	movs	r3, #3
 80033ea:	e067      	b.n	80034bc <HAL_RCC_OscConfig+0x4ec>
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
 80033ec:	4b35      	ldr	r3, [pc, #212]	; (80034c4 <HAL_RCC_OscConfig+0x4f4>)
 80033ee:	681b      	ldr	r3, [r3, #0]
 80033f0:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
 80033f4:	2b00      	cmp	r3, #0
 80033f6:	d1f0      	bne.n	80033da <HAL_RCC_OscConfig+0x40a>
          }
        }

        /* Configure the HSE prediv factor --------------------------------*/
        /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
        if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
 80033f8:	687b      	ldr	r3, [r7, #4]
 80033fa:	6a1b      	ldr	r3, [r3, #32]
 80033fc:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
 8003400:	d108      	bne.n	8003414 <HAL_RCC_OscConfig+0x444>
          /* Set PREDIV1 source */
          SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);
#endif /* RCC_CFGR2_PREDIV1SRC */

          /* Set PREDIV1 Value */
          __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
 8003402:	4b30      	ldr	r3, [pc, #192]	; (80034c4 <HAL_RCC_OscConfig+0x4f4>)
 8003404:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 8003406:	f023 020f 	bic.w	r2, r3, #15
 800340a:	687b      	ldr	r3, [r7, #4]
 800340c:	689b      	ldr	r3, [r3, #8]
 800340e:	492d      	ldr	r1, [pc, #180]	; (80034c4 <HAL_RCC_OscConfig+0x4f4>)
 8003410:	4313      	orrs	r3, r2
 8003412:	62cb      	str	r3, [r1, #44]	; 0x2c
        }

        /* Configure the main PLL clock source and multiplication factors. */
        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
 8003414:	4b2b      	ldr	r3, [pc, #172]	; (80034c4 <HAL_RCC_OscConfig+0x4f4>)
 8003416:	685b      	ldr	r3, [r3, #4]
 8003418:	f423 1274 	bic.w	r2, r3, #3997696	; 0x3d0000
 800341c:	687b      	ldr	r3, [r7, #4]
 800341e:	6a19      	ldr	r1, [r3, #32]
 8003420:	687b      	ldr	r3, [r7, #4]
 8003422:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8003424:	430b      	orrs	r3, r1
 8003426:	4927      	ldr	r1, [pc, #156]	; (80034c4 <HAL_RCC_OscConfig+0x4f4>)
 8003428:	4313      	orrs	r3, r2
 800342a:	604b      	str	r3, [r1, #4]
                             RCC_OscInitStruct->PLL.PLLMUL);
        /* Enable the main PLL. */
        __HAL_RCC_PLL_ENABLE();
 800342c:	4b27      	ldr	r3, [pc, #156]	; (80034cc <HAL_RCC_OscConfig+0x4fc>)
 800342e:	2201      	movs	r2, #1
 8003430:	601a      	str	r2, [r3, #0]

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8003432:	f7fe fa0b 	bl	800184c <HAL_GetTick>
 8003436:	6138      	str	r0, [r7, #16]

        /* Wait till PLL is ready */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  == RESET)
 8003438:	e008      	b.n	800344c <HAL_RCC_OscConfig+0x47c>
        {
          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
 800343a:	f7fe fa07 	bl	800184c <HAL_GetTick>
 800343e:	4602      	mov	r2, r0
 8003440:	693b      	ldr	r3, [r7, #16]
 8003442:	1ad3      	subs	r3, r2, r3
 8003444:	2b02      	cmp	r3, #2
 8003446:	d901      	bls.n	800344c <HAL_RCC_OscConfig+0x47c>
          {
            return HAL_TIMEOUT;
 8003448:	2303      	movs	r3, #3
 800344a:	e037      	b.n	80034bc <HAL_RCC_OscConfig+0x4ec>
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  == RESET)
 800344c:	4b1d      	ldr	r3, [pc, #116]	; (80034c4 <HAL_RCC_OscConfig+0x4f4>)
 800344e:	681b      	ldr	r3, [r3, #0]
 8003450:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
 8003454:	2b00      	cmp	r3, #0
 8003456:	d0f0      	beq.n	800343a <HAL_RCC_OscConfig+0x46a>
 8003458:	e02f      	b.n	80034ba <HAL_RCC_OscConfig+0x4ea>
        }
      }
      else
      {
        /* Disable the main PLL. */
        __HAL_RCC_PLL_DISABLE();
 800345a:	4b1c      	ldr	r3, [pc, #112]	; (80034cc <HAL_RCC_OscConfig+0x4fc>)
 800345c:	2200      	movs	r2, #0
 800345e:	601a      	str	r2, [r3, #0]

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8003460:	f7fe f9f4 	bl	800184c <HAL_GetTick>
 8003464:	6138      	str	r0, [r7, #16]

        /* Wait till PLL is disabled */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
 8003466:	e008      	b.n	800347a <HAL_RCC_OscConfig+0x4aa>
        {
          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
 8003468:	f7fe f9f0 	bl	800184c <HAL_GetTick>
 800346c:	4602      	mov	r2, r0
 800346e:	693b      	ldr	r3, [r7, #16]
 8003470:	1ad3      	subs	r3, r2, r3
 8003472:	2b02      	cmp	r3, #2
 8003474:	d901      	bls.n	800347a <HAL_RCC_OscConfig+0x4aa>
          {
            return HAL_TIMEOUT;
 8003476:	2303      	movs	r3, #3
 8003478:	e020      	b.n	80034bc <HAL_RCC_OscConfig+0x4ec>
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
 800347a:	4b12      	ldr	r3, [pc, #72]	; (80034c4 <HAL_RCC_OscConfig+0x4f4>)
 800347c:	681b      	ldr	r3, [r3, #0]
 800347e:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
 8003482:	2b00      	cmp	r3, #0
 8003484:	d1f0      	bne.n	8003468 <HAL_RCC_OscConfig+0x498>
 8003486:	e018      	b.n	80034ba <HAL_RCC_OscConfig+0x4ea>
      }
    }
    else
    {
      /* Check if there is a request to disable the PLL used as System clock source */
      if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
 8003488:	687b      	ldr	r3, [r7, #4]
 800348a:	69db      	ldr	r3, [r3, #28]
 800348c:	2b01      	cmp	r3, #1
 800348e:	d101      	bne.n	8003494 <HAL_RCC_OscConfig+0x4c4>
      {
        return HAL_ERROR;
 8003490:	2301      	movs	r3, #1
 8003492:	e013      	b.n	80034bc <HAL_RCC_OscConfig+0x4ec>
      }
      else
      {
        /* Do not return HAL_ERROR if request repeats the current configuration */
        pll_config = RCC->CFGR;
 8003494:	4b0b      	ldr	r3, [pc, #44]	; (80034c4 <HAL_RCC_OscConfig+0x4f4>)
 8003496:	685b      	ldr	r3, [r3, #4]
 8003498:	60fb      	str	r3, [r7, #12]
        if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
 800349a:	68fb      	ldr	r3, [r7, #12]
 800349c:	f403 3280 	and.w	r2, r3, #65536	; 0x10000
 80034a0:	687b      	ldr	r3, [r7, #4]
 80034a2:	6a1b      	ldr	r3, [r3, #32]
 80034a4:	429a      	cmp	r2, r3
 80034a6:	d106      	bne.n	80034b6 <HAL_RCC_OscConfig+0x4e6>
            (READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL))
 80034a8:	68fb      	ldr	r3, [r7, #12]
 80034aa:	f403 1270 	and.w	r2, r3, #3932160	; 0x3c0000
 80034ae:	687b      	ldr	r3, [r7, #4]
 80034b0:	6a5b      	ldr	r3, [r3, #36]	; 0x24
        if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
 80034b2:	429a      	cmp	r2, r3
 80034b4:	d001      	beq.n	80034ba <HAL_RCC_OscConfig+0x4ea>
        {
          return HAL_ERROR;
 80034b6:	2301      	movs	r3, #1
 80034b8:	e000      	b.n	80034bc <HAL_RCC_OscConfig+0x4ec>
        }
      }
    }
  }

  return HAL_OK;
 80034ba:	2300      	movs	r3, #0
}
 80034bc:	4618      	mov	r0, r3
 80034be:	3718      	adds	r7, #24
 80034c0:	46bd      	mov	sp, r7
 80034c2:	bd80      	pop	{r7, pc}
 80034c4:	40021000 	.word	0x40021000
 80034c8:	40007000 	.word	0x40007000
 80034cc:	42420060 	.word	0x42420060

080034d0 <HAL_RCC_ClockConfig>:
  *         You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
  *         currently used as system clock source.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
{
 80034d0:	b580      	push	{r7, lr}
 80034d2:	b084      	sub	sp, #16
 80034d4:	af00      	add	r7, sp, #0
 80034d6:	6078      	str	r0, [r7, #4]
 80034d8:	6039      	str	r1, [r7, #0]
  uint32_t tickstart;

  /* Check Null pointer */
  if (RCC_ClkInitStruct == NULL)
 80034da:	687b      	ldr	r3, [r7, #4]
 80034dc:	2b00      	cmp	r3, #0
 80034de:	d101      	bne.n	80034e4 <HAL_RCC_ClockConfig+0x14>
  {
    return HAL_ERROR;
 80034e0:	2301      	movs	r3, #1
 80034e2:	e0a0      	b.n	8003626 <HAL_RCC_ClockConfig+0x156>
  }
}

#endif /* FLASH_ACR_LATENCY */
/*-------------------------- HCLK Configuration --------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
 80034e4:	687b      	ldr	r3, [r7, #4]
 80034e6:	681b      	ldr	r3, [r3, #0]
 80034e8:	f003 0302 	and.w	r3, r3, #2
 80034ec:	2b00      	cmp	r3, #0
 80034ee:	d020      	beq.n	8003532 <HAL_RCC_ClockConfig+0x62>
  {
    /* Set the highest APBx dividers in order to ensure that we do not go through
    a non-spec phase whatever we decrease or increase HCLK. */
    if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 80034f0:	687b      	ldr	r3, [r7, #4]
 80034f2:	681b      	ldr	r3, [r3, #0]
 80034f4:	f003 0304 	and.w	r3, r3, #4
 80034f8:	2b00      	cmp	r3, #0
 80034fa:	d005      	beq.n	8003508 <HAL_RCC_ClockConfig+0x38>
    {
      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
 80034fc:	4b4c      	ldr	r3, [pc, #304]	; (8003630 <HAL_RCC_ClockConfig+0x160>)
 80034fe:	685b      	ldr	r3, [r3, #4]
 8003500:	4a4b      	ldr	r2, [pc, #300]	; (8003630 <HAL_RCC_ClockConfig+0x160>)
 8003502:	f443 63e0 	orr.w	r3, r3, #1792	; 0x700
 8003506:	6053      	str	r3, [r2, #4]
    }

    if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
 8003508:	687b      	ldr	r3, [r7, #4]
 800350a:	681b      	ldr	r3, [r3, #0]
 800350c:	f003 0308 	and.w	r3, r3, #8
 8003510:	2b00      	cmp	r3, #0
 8003512:	d005      	beq.n	8003520 <HAL_RCC_ClockConfig+0x50>
    {
      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
 8003514:	4b46      	ldr	r3, [pc, #280]	; (8003630 <HAL_RCC_ClockConfig+0x160>)
 8003516:	685b      	ldr	r3, [r3, #4]
 8003518:	4a45      	ldr	r2, [pc, #276]	; (8003630 <HAL_RCC_ClockConfig+0x160>)
 800351a:	f443 5360 	orr.w	r3, r3, #14336	; 0x3800
 800351e:	6053      	str	r3, [r2, #4]
    }

    /* Set the new HCLK clock divider */
    assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
 8003520:	4b43      	ldr	r3, [pc, #268]	; (8003630 <HAL_RCC_ClockConfig+0x160>)
 8003522:	685b      	ldr	r3, [r3, #4]
 8003524:	f023 02f0 	bic.w	r2, r3, #240	; 0xf0
 8003528:	687b      	ldr	r3, [r7, #4]
 800352a:	689b      	ldr	r3, [r3, #8]
 800352c:	4940      	ldr	r1, [pc, #256]	; (8003630 <HAL_RCC_ClockConfig+0x160>)
 800352e:	4313      	orrs	r3, r2
 8003530:	604b      	str	r3, [r1, #4]
  }

  /*------------------------- SYSCLK Configuration ---------------------------*/
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
 8003532:	687b      	ldr	r3, [r7, #4]
 8003534:	681b      	ldr	r3, [r3, #0]
 8003536:	f003 0301 	and.w	r3, r3, #1
 800353a:	2b00      	cmp	r3, #0
 800353c:	d040      	beq.n	80035c0 <HAL_RCC_ClockConfig+0xf0>
  {
    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));

    /* HSE is selected as System Clock Source */
    if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 800353e:	687b      	ldr	r3, [r7, #4]
 8003540:	685b      	ldr	r3, [r3, #4]
 8003542:	2b01      	cmp	r3, #1
 8003544:	d107      	bne.n	8003556 <HAL_RCC_ClockConfig+0x86>
    {
      /* Check the HSE ready flag */
      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 8003546:	4b3a      	ldr	r3, [pc, #232]	; (8003630 <HAL_RCC_ClockConfig+0x160>)
 8003548:	681b      	ldr	r3, [r3, #0]
 800354a:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 800354e:	2b00      	cmp	r3, #0
 8003550:	d115      	bne.n	800357e <HAL_RCC_ClockConfig+0xae>
      {
        return HAL_ERROR;
 8003552:	2301      	movs	r3, #1
 8003554:	e067      	b.n	8003626 <HAL_RCC_ClockConfig+0x156>
      }
    }
    /* PLL is selected as System Clock Source */
    else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
 8003556:	687b      	ldr	r3, [r7, #4]
 8003558:	685b      	ldr	r3, [r3, #4]
 800355a:	2b02      	cmp	r3, #2
 800355c:	d107      	bne.n	800356e <HAL_RCC_ClockConfig+0x9e>
    {
      /* Check the PLL ready flag */
      if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
 800355e:	4b34      	ldr	r3, [pc, #208]	; (8003630 <HAL_RCC_ClockConfig+0x160>)
 8003560:	681b      	ldr	r3, [r3, #0]
 8003562:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
 8003566:	2b00      	cmp	r3, #0
 8003568:	d109      	bne.n	800357e <HAL_RCC_ClockConfig+0xae>
      {
        return HAL_ERROR;
 800356a:	2301      	movs	r3, #1
 800356c:	e05b      	b.n	8003626 <HAL_RCC_ClockConfig+0x156>
    }
    /* HSI is selected as System Clock Source */
    else
    {
      /* Check the HSI ready flag */
      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 800356e:	4b30      	ldr	r3, [pc, #192]	; (8003630 <HAL_RCC_ClockConfig+0x160>)
 8003570:	681b      	ldr	r3, [r3, #0]
 8003572:	f003 0302 	and.w	r3, r3, #2
 8003576:	2b00      	cmp	r3, #0
 8003578:	d101      	bne.n	800357e <HAL_RCC_ClockConfig+0xae>
      {
        return HAL_ERROR;
 800357a:	2301      	movs	r3, #1
 800357c:	e053      	b.n	8003626 <HAL_RCC_ClockConfig+0x156>
      }
    }
    __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
 800357e:	4b2c      	ldr	r3, [pc, #176]	; (8003630 <HAL_RCC_ClockConfig+0x160>)
 8003580:	685b      	ldr	r3, [r3, #4]
 8003582:	f023 0203 	bic.w	r2, r3, #3
 8003586:	687b      	ldr	r3, [r7, #4]
 8003588:	685b      	ldr	r3, [r3, #4]
 800358a:	4929      	ldr	r1, [pc, #164]	; (8003630 <HAL_RCC_ClockConfig+0x160>)
 800358c:	4313      	orrs	r3, r2
 800358e:	604b      	str	r3, [r1, #4]

    /* Get Start Tick */
    tickstart = HAL_GetTick();
 8003590:	f7fe f95c 	bl	800184c <HAL_GetTick>
 8003594:	60f8      	str	r0, [r7, #12]

    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
 8003596:	e00a      	b.n	80035ae <HAL_RCC_ClockConfig+0xde>
    {
      if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
 8003598:	f7fe f958 	bl	800184c <HAL_GetTick>
 800359c:	4602      	mov	r2, r0
 800359e:	68fb      	ldr	r3, [r7, #12]
 80035a0:	1ad3      	subs	r3, r2, r3
 80035a2:	f241 3288 	movw	r2, #5000	; 0x1388
 80035a6:	4293      	cmp	r3, r2
 80035a8:	d901      	bls.n	80035ae <HAL_RCC_ClockConfig+0xde>
      {
        return HAL_TIMEOUT;
 80035aa:	2303      	movs	r3, #3
 80035ac:	e03b      	b.n	8003626 <HAL_RCC_ClockConfig+0x156>
    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
 80035ae:	4b20      	ldr	r3, [pc, #128]	; (8003630 <HAL_RCC_ClockConfig+0x160>)
 80035b0:	685b      	ldr	r3, [r3, #4]
 80035b2:	f003 020c 	and.w	r2, r3, #12
 80035b6:	687b      	ldr	r3, [r7, #4]
 80035b8:	685b      	ldr	r3, [r3, #4]
 80035ba:	009b      	lsls	r3, r3, #2
 80035bc:	429a      	cmp	r2, r3
 80035be:	d1eb      	bne.n	8003598 <HAL_RCC_ClockConfig+0xc8>
  }
}
#endif /* FLASH_ACR_LATENCY */

/*-------------------------- PCLK1 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 80035c0:	687b      	ldr	r3, [r7, #4]
 80035c2:	681b      	ldr	r3, [r3, #0]
 80035c4:	f003 0304 	and.w	r3, r3, #4
 80035c8:	2b00      	cmp	r3, #0
 80035ca:	d008      	beq.n	80035de <HAL_RCC_ClockConfig+0x10e>
  {
    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
 80035cc:	4b18      	ldr	r3, [pc, #96]	; (8003630 <HAL_RCC_ClockConfig+0x160>)
 80035ce:	685b      	ldr	r3, [r3, #4]
 80035d0:	f423 62e0 	bic.w	r2, r3, #1792	; 0x700
 80035d4:	687b      	ldr	r3, [r7, #4]
 80035d6:	68db      	ldr	r3, [r3, #12]
 80035d8:	4915      	ldr	r1, [pc, #84]	; (8003630 <HAL_RCC_ClockConfig+0x160>)
 80035da:	4313      	orrs	r3, r2
 80035dc:	604b      	str	r3, [r1, #4]
  }

  /*-------------------------- PCLK2 Configuration ---------------------------*/
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
 80035de:	687b      	ldr	r3, [r7, #4]
 80035e0:	681b      	ldr	r3, [r3, #0]
 80035e2:	f003 0308 	and.w	r3, r3, #8
 80035e6:	2b00      	cmp	r3, #0
 80035e8:	d009      	beq.n	80035fe <HAL_RCC_ClockConfig+0x12e>
  {
    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
 80035ea:	4b11      	ldr	r3, [pc, #68]	; (8003630 <HAL_RCC_ClockConfig+0x160>)
 80035ec:	685b      	ldr	r3, [r3, #4]
 80035ee:	f423 5260 	bic.w	r2, r3, #14336	; 0x3800
 80035f2:	687b      	ldr	r3, [r7, #4]
 80035f4:	691b      	ldr	r3, [r3, #16]
 80035f6:	00db      	lsls	r3, r3, #3
 80035f8:	490d      	ldr	r1, [pc, #52]	; (8003630 <HAL_RCC_ClockConfig+0x160>)
 80035fa:	4313      	orrs	r3, r2
 80035fc:	604b      	str	r3, [r1, #4]
  }

  /* Update the SystemCoreClock global variable */
  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
 80035fe:	f000 f81f 	bl	8003640 <HAL_RCC_GetSysClockFreq>
 8003602:	4601      	mov	r1, r0
 8003604:	4b0a      	ldr	r3, [pc, #40]	; (8003630 <HAL_RCC_ClockConfig+0x160>)
 8003606:	685b      	ldr	r3, [r3, #4]
 8003608:	091b      	lsrs	r3, r3, #4
 800360a:	f003 030f 	and.w	r3, r3, #15
 800360e:	4a09      	ldr	r2, [pc, #36]	; (8003634 <HAL_RCC_ClockConfig+0x164>)
 8003610:	5cd3      	ldrb	r3, [r2, r3]
 8003612:	fa21 f303 	lsr.w	r3, r1, r3
 8003616:	4a08      	ldr	r2, [pc, #32]	; (8003638 <HAL_RCC_ClockConfig+0x168>)
 8003618:	6013      	str	r3, [r2, #0]

  /* Configure the source of time base considering new system clocks settings*/
  HAL_InitTick(uwTickPrio);
 800361a:	4b08      	ldr	r3, [pc, #32]	; (800363c <HAL_RCC_ClockConfig+0x16c>)
 800361c:	681b      	ldr	r3, [r3, #0]
 800361e:	4618      	mov	r0, r3
 8003620:	f002 f814 	bl	800564c <HAL_InitTick>

  return HAL_OK;
 8003624:	2300      	movs	r3, #0
}
 8003626:	4618      	mov	r0, r3
 8003628:	3710      	adds	r7, #16
 800362a:	46bd      	mov	sp, r7
 800362c:	bd80      	pop	{r7, pc}
 800362e:	bf00      	nop
 8003630:	40021000 	.word	0x40021000
 8003634:	080085e0 	.word	0x080085e0
 8003638:	20000008 	.word	0x20000008
 800363c:	20000000 	.word	0x20000000

08003640 <HAL_RCC_GetSysClockFreq>:
  *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
  *
  * @retval SYSCLK frequency
  */
uint32_t HAL_RCC_GetSysClockFreq(void)
{
 8003640:	b490      	push	{r4, r7}
 8003642:	b08e      	sub	sp, #56	; 0x38
 8003644:	af00      	add	r7, sp, #0
#if defined(RCC_CFGR2_PREDIV1SRC)
  const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13};
  const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
#else
  const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
 8003646:	4b2b      	ldr	r3, [pc, #172]	; (80036f4 <HAL_RCC_GetSysClockFreq+0xb4>)
 8003648:	f107 0414 	add.w	r4, r7, #20
 800364c:	cb0f      	ldmia	r3, {r0, r1, r2, r3}
 800364e:	e884 000f 	stmia.w	r4, {r0, r1, r2, r3}
#if defined(RCC_CFGR2_PREDIV1)
  const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
 8003652:	4b29      	ldr	r3, [pc, #164]	; (80036f8 <HAL_RCC_GetSysClockFreq+0xb8>)
 8003654:	1d3c      	adds	r4, r7, #4
 8003656:	cb0f      	ldmia	r3, {r0, r1, r2, r3}
 8003658:	e884 000f 	stmia.w	r4, {r0, r1, r2, r3}
#else
  const uint8_t aPredivFactorTable[2] = {1, 2};
#endif /*RCC_CFGR2_PREDIV1*/

#endif
  uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
 800365c:	2300      	movs	r3, #0
 800365e:	62fb      	str	r3, [r7, #44]	; 0x2c
 8003660:	2300      	movs	r3, #0
 8003662:	62bb      	str	r3, [r7, #40]	; 0x28
 8003664:	2300      	movs	r3, #0
 8003666:	637b      	str	r3, [r7, #52]	; 0x34
 8003668:	2300      	movs	r3, #0
 800366a:	627b      	str	r3, [r7, #36]	; 0x24
  uint32_t sysclockfreq = 0U;
 800366c:	2300      	movs	r3, #0
 800366e:	633b      	str	r3, [r7, #48]	; 0x30
#if defined(RCC_CFGR2_PREDIV1SRC)
  uint32_t prediv2 = 0U, pll2mul = 0U;
#endif /*RCC_CFGR2_PREDIV1SRC*/

  tmpreg = RCC->CFGR;
 8003670:	4b22      	ldr	r3, [pc, #136]	; (80036fc <HAL_RCC_GetSysClockFreq+0xbc>)
 8003672:	685b      	ldr	r3, [r3, #4]
 8003674:	62fb      	str	r3, [r7, #44]	; 0x2c

  /* Get SYSCLK source -------------------------------------------------------*/
  switch (tmpreg & RCC_CFGR_SWS)
 8003676:	6afb      	ldr	r3, [r7, #44]	; 0x2c
 8003678:	f003 030c 	and.w	r3, r3, #12
 800367c:	2b04      	cmp	r3, #4
 800367e:	d002      	beq.n	8003686 <HAL_RCC_GetSysClockFreq+0x46>
 8003680:	2b08      	cmp	r3, #8
 8003682:	d003      	beq.n	800368c <HAL_RCC_GetSysClockFreq+0x4c>
 8003684:	e02c      	b.n	80036e0 <HAL_RCC_GetSysClockFreq+0xa0>
  {
    case RCC_SYSCLKSOURCE_STATUS_HSE:  /* HSE used as system clock */
    {
      sysclockfreq = HSE_VALUE;
 8003686:	4b1e      	ldr	r3, [pc, #120]	; (8003700 <HAL_RCC_GetSysClockFreq+0xc0>)
 8003688:	633b      	str	r3, [r7, #48]	; 0x30
      break;
 800368a:	e02c      	b.n	80036e6 <HAL_RCC_GetSysClockFreq+0xa6>
    }
    case RCC_SYSCLKSOURCE_STATUS_PLLCLK:  /* PLL used as system clock */
    {
      pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
 800368c:	6afb      	ldr	r3, [r7, #44]	; 0x2c
 800368e:	0c9b      	lsrs	r3, r3, #18
 8003690:	f003 030f 	and.w	r3, r3, #15
 8003694:	f107 0238 	add.w	r2, r7, #56	; 0x38
 8003698:	4413      	add	r3, r2
 800369a:	f813 3c24 	ldrb.w	r3, [r3, #-36]
 800369e:	627b      	str	r3, [r7, #36]	; 0x24
      if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
 80036a0:	6afb      	ldr	r3, [r7, #44]	; 0x2c
 80036a2:	f403 3380 	and.w	r3, r3, #65536	; 0x10000
 80036a6:	2b00      	cmp	r3, #0
 80036a8:	d012      	beq.n	80036d0 <HAL_RCC_GetSysClockFreq+0x90>
      {
#if defined(RCC_CFGR2_PREDIV1)
        prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
 80036aa:	4b14      	ldr	r3, [pc, #80]	; (80036fc <HAL_RCC_GetSysClockFreq+0xbc>)
 80036ac:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 80036ae:	f003 030f 	and.w	r3, r3, #15
 80036b2:	f107 0238 	add.w	r2, r7, #56	; 0x38
 80036b6:	4413      	add	r3, r2
 80036b8:	f813 3c34 	ldrb.w	r3, [r3, #-52]
 80036bc:	62bb      	str	r3, [r7, #40]	; 0x28
        {
          pllclk = pllclk / 2;
        }
#else
        /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
        pllclk = (uint32_t)((HSE_VALUE  * pllmul) / prediv);
 80036be:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 80036c0:	4a0f      	ldr	r2, [pc, #60]	; (8003700 <HAL_RCC_GetSysClockFreq+0xc0>)
 80036c2:	fb02 f203 	mul.w	r2, r2, r3
 80036c6:	6abb      	ldr	r3, [r7, #40]	; 0x28
 80036c8:	fbb2 f3f3 	udiv	r3, r2, r3
 80036cc:	637b      	str	r3, [r7, #52]	; 0x34
 80036ce:	e004      	b.n	80036da <HAL_RCC_GetSysClockFreq+0x9a>
#endif /*RCC_CFGR2_PREDIV1SRC*/
      }
      else
      {
        /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
        pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
 80036d0:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 80036d2:	4a0c      	ldr	r2, [pc, #48]	; (8003704 <HAL_RCC_GetSysClockFreq+0xc4>)
 80036d4:	fb02 f303 	mul.w	r3, r2, r3
 80036d8:	637b      	str	r3, [r7, #52]	; 0x34
      }
      sysclockfreq = pllclk;
 80036da:	6b7b      	ldr	r3, [r7, #52]	; 0x34
 80036dc:	633b      	str	r3, [r7, #48]	; 0x30
      break;
 80036de:	e002      	b.n	80036e6 <HAL_RCC_GetSysClockFreq+0xa6>
    }
    case RCC_SYSCLKSOURCE_STATUS_HSI:  /* HSI used as system clock source */
    default: /* HSI used as system clock */
    {
      sysclockfreq = HSI_VALUE;
 80036e0:	4b07      	ldr	r3, [pc, #28]	; (8003700 <HAL_RCC_GetSysClockFreq+0xc0>)
 80036e2:	633b      	str	r3, [r7, #48]	; 0x30
      break;
 80036e4:	bf00      	nop
    }
  }
  return sysclockfreq;
 80036e6:	6b3b      	ldr	r3, [r7, #48]	; 0x30
}
 80036e8:	4618      	mov	r0, r3
 80036ea:	3738      	adds	r7, #56	; 0x38
 80036ec:	46bd      	mov	sp, r7
 80036ee:	bc90      	pop	{r4, r7}
 80036f0:	4770      	bx	lr
 80036f2:	bf00      	nop
 80036f4:	08008534 	.word	0x08008534
 80036f8:	08008544 	.word	0x08008544
 80036fc:	40021000 	.word	0x40021000
 8003700:	007a1200 	.word	0x007a1200
 8003704:	003d0900 	.word	0x003d0900

08003708 <HAL_RCC_GetHCLKFreq>:
  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
  *         and updated within this function
  * @retval HCLK frequency
  */
uint32_t HAL_RCC_GetHCLKFreq(void)
{
 8003708:	b480      	push	{r7}
 800370a:	af00      	add	r7, sp, #0
  return SystemCoreClock;
 800370c:	4b02      	ldr	r3, [pc, #8]	; (8003718 <HAL_RCC_GetHCLKFreq+0x10>)
 800370e:	681b      	ldr	r3, [r3, #0]
}
 8003710:	4618      	mov	r0, r3
 8003712:	46bd      	mov	sp, r7
 8003714:	bc80      	pop	{r7}
 8003716:	4770      	bx	lr
 8003718:	20000008 	.word	0x20000008

0800371c <HAL_RCC_GetPCLK1Freq>:
  * @note   Each time PCLK1 changes, this function must be called to update the
  *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
  * @retval PCLK1 frequency
  */
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
 800371c:	b580      	push	{r7, lr}
 800371e:	af00      	add	r7, sp, #0
  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
  return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
 8003720:	f7ff fff2 	bl	8003708 <HAL_RCC_GetHCLKFreq>
 8003724:	4601      	mov	r1, r0
 8003726:	4b05      	ldr	r3, [pc, #20]	; (800373c <HAL_RCC_GetPCLK1Freq+0x20>)
 8003728:	685b      	ldr	r3, [r3, #4]
 800372a:	0a1b      	lsrs	r3, r3, #8
 800372c:	f003 0307 	and.w	r3, r3, #7
 8003730:	4a03      	ldr	r2, [pc, #12]	; (8003740 <HAL_RCC_GetPCLK1Freq+0x24>)
 8003732:	5cd3      	ldrb	r3, [r2, r3]
 8003734:	fa21 f303 	lsr.w	r3, r1, r3
}
 8003738:	4618      	mov	r0, r3
 800373a:	bd80      	pop	{r7, pc}
 800373c:	40021000 	.word	0x40021000
 8003740:	080085f0 	.word	0x080085f0

08003744 <HAL_RCC_GetPCLK2Freq>:
  * @note   Each time PCLK2 changes, this function must be called to update the
  *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
  * @retval PCLK2 frequency
  */
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
 8003744:	b580      	push	{r7, lr}
 8003746:	af00      	add	r7, sp, #0
  /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
  return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
 8003748:	f7ff ffde 	bl	8003708 <HAL_RCC_GetHCLKFreq>
 800374c:	4601      	mov	r1, r0
 800374e:	4b05      	ldr	r3, [pc, #20]	; (8003764 <HAL_RCC_GetPCLK2Freq+0x20>)
 8003750:	685b      	ldr	r3, [r3, #4]
 8003752:	0adb      	lsrs	r3, r3, #11
 8003754:	f003 0307 	and.w	r3, r3, #7
 8003758:	4a03      	ldr	r2, [pc, #12]	; (8003768 <HAL_RCC_GetPCLK2Freq+0x24>)
 800375a:	5cd3      	ldrb	r3, [r2, r3]
 800375c:	fa21 f303 	lsr.w	r3, r1, r3
}
 8003760:	4618      	mov	r0, r3
 8003762:	bd80      	pop	{r7, pc}
 8003764:	40021000 	.word	0x40021000
 8003768:	080085f0 	.word	0x080085f0

0800376c <HAL_RCC_GetClockConfig>:
  * contains the current clock configuration.
  * @param  pFLatency Pointer on the Flash Latency.
  * @retval None
  */
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
{
 800376c:	b480      	push	{r7}
 800376e:	b083      	sub	sp, #12
 8003770:	af00      	add	r7, sp, #0
 8003772:	6078      	str	r0, [r7, #4]
 8003774:	6039      	str	r1, [r7, #0]
  /* Check the parameters */
  assert_param(RCC_ClkInitStruct != NULL);
  assert_param(pFLatency != NULL);

  /* Set all possible values for the Clock type parameter --------------------*/
  RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
 8003776:	687b      	ldr	r3, [r7, #4]
 8003778:	220f      	movs	r2, #15
 800377a:	601a      	str	r2, [r3, #0]

  /* Get the SYSCLK configuration --------------------------------------------*/
  RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
 800377c:	4b10      	ldr	r3, [pc, #64]	; (80037c0 <HAL_RCC_GetClockConfig+0x54>)
 800377e:	685b      	ldr	r3, [r3, #4]
 8003780:	f003 0203 	and.w	r2, r3, #3
 8003784:	687b      	ldr	r3, [r7, #4]
 8003786:	605a      	str	r2, [r3, #4]

  /* Get the HCLK configuration ----------------------------------------------*/
  RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
 8003788:	4b0d      	ldr	r3, [pc, #52]	; (80037c0 <HAL_RCC_GetClockConfig+0x54>)
 800378a:	685b      	ldr	r3, [r3, #4]
 800378c:	f003 02f0 	and.w	r2, r3, #240	; 0xf0
 8003790:	687b      	ldr	r3, [r7, #4]
 8003792:	609a      	str	r2, [r3, #8]

  /* Get the APB1 configuration ----------------------------------------------*/
  RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
 8003794:	4b0a      	ldr	r3, [pc, #40]	; (80037c0 <HAL_RCC_GetClockConfig+0x54>)
 8003796:	685b      	ldr	r3, [r3, #4]
 8003798:	f403 62e0 	and.w	r2, r3, #1792	; 0x700
 800379c:	687b      	ldr	r3, [r7, #4]
 800379e:	60da      	str	r2, [r3, #12]

  /* Get the APB2 configuration ----------------------------------------------*/
  RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
 80037a0:	4b07      	ldr	r3, [pc, #28]	; (80037c0 <HAL_RCC_GetClockConfig+0x54>)
 80037a2:	685b      	ldr	r3, [r3, #4]
 80037a4:	08db      	lsrs	r3, r3, #3
 80037a6:	f403 62e0 	and.w	r2, r3, #1792	; 0x700
 80037aa:	687b      	ldr	r3, [r7, #4]
 80037ac:	611a      	str	r2, [r3, #16]
#if   defined(FLASH_ACR_LATENCY)
  /* Get the Flash Wait State (Latency) configuration ------------------------*/
  *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
#else
  /* For VALUE lines devices, only LATENCY_0 can be set*/
  *pFLatency = (uint32_t)FLASH_LATENCY_0;
 80037ae:	683b      	ldr	r3, [r7, #0]
 80037b0:	2200      	movs	r2, #0
 80037b2:	601a      	str	r2, [r3, #0]
#endif
}
 80037b4:	bf00      	nop
 80037b6:	370c      	adds	r7, #12
 80037b8:	46bd      	mov	sp, r7
 80037ba:	bc80      	pop	{r7}
 80037bc:	4770      	bx	lr
 80037be:	bf00      	nop
 80037c0:	40021000 	.word	0x40021000

080037c4 <RCC_Delay>:
  * @brief  This function provides delay (in milliseconds) based on CPU cycles method.
  * @param  mdelay: specifies the delay time length, in milliseconds.
  * @retval None
  */
static void RCC_Delay(uint32_t mdelay)
{
 80037c4:	b480      	push	{r7}
 80037c6:	b085      	sub	sp, #20
 80037c8:	af00      	add	r7, sp, #0
 80037ca:	6078      	str	r0, [r7, #4]
  __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
 80037cc:	4b0a      	ldr	r3, [pc, #40]	; (80037f8 <RCC_Delay+0x34>)
 80037ce:	681b      	ldr	r3, [r3, #0]
 80037d0:	4a0a      	ldr	r2, [pc, #40]	; (80037fc <RCC_Delay+0x38>)
 80037d2:	fba2 2303 	umull	r2, r3, r2, r3
 80037d6:	0a5b      	lsrs	r3, r3, #9
 80037d8:	687a      	ldr	r2, [r7, #4]
 80037da:	fb02 f303 	mul.w	r3, r2, r3
 80037de:	60fb      	str	r3, [r7, #12]
  do
  {
    __NOP();
 80037e0:	bf00      	nop
  }
  while (Delay --);
 80037e2:	68fb      	ldr	r3, [r7, #12]
 80037e4:	1e5a      	subs	r2, r3, #1
 80037e6:	60fa      	str	r2, [r7, #12]
 80037e8:	2b00      	cmp	r3, #0
 80037ea:	d1f9      	bne.n	80037e0 <RCC_Delay+0x1c>
}
 80037ec:	bf00      	nop
 80037ee:	3714      	adds	r7, #20
 80037f0:	46bd      	mov	sp, r7
 80037f2:	bc80      	pop	{r7}
 80037f4:	4770      	bx	lr
 80037f6:	bf00      	nop
 80037f8:	20000008 	.word	0x20000008
 80037fc:	10624dd3 	.word	0x10624dd3

08003800 <HAL_RCCEx_PeriphCLKConfig>:
  *         manually disable it.
  *
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
{
 8003800:	b580      	push	{r7, lr}
 8003802:	b086      	sub	sp, #24
 8003804:	af00      	add	r7, sp, #0
 8003806:	6078      	str	r0, [r7, #4]
  uint32_t tickstart = 0U, temp_reg = 0U;
 8003808:	2300      	movs	r3, #0
 800380a:	613b      	str	r3, [r7, #16]
 800380c:	2300      	movs	r3, #0
 800380e:	60fb      	str	r3, [r7, #12]

  /* Check the parameters */
  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));

  /*------------------------------- RTC/LCD Configuration ------------------------*/
  if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
 8003810:	687b      	ldr	r3, [r7, #4]
 8003812:	681b      	ldr	r3, [r3, #0]
 8003814:	f003 0301 	and.w	r3, r3, #1
 8003818:	2b00      	cmp	r3, #0
 800381a:	d07d      	beq.n	8003918 <HAL_RCCEx_PeriphCLKConfig+0x118>
  {
    /* check for RTC Parameters used to output RTCCLK */
    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));

    FlagStatus       pwrclkchanged = RESET;
 800381c:	2300      	movs	r3, #0
 800381e:	75fb      	strb	r3, [r7, #23]

    /* As soon as function is called to change RTC clock source, activation of the
       power domain is done. */
    /* Requires to enable write access to Backup Domain of necessary */
    if (__HAL_RCC_PWR_IS_CLK_DISABLED())
 8003820:	4b47      	ldr	r3, [pc, #284]	; (8003940 <HAL_RCCEx_PeriphCLKConfig+0x140>)
 8003822:	69db      	ldr	r3, [r3, #28]
 8003824:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8003828:	2b00      	cmp	r3, #0
 800382a:	d10d      	bne.n	8003848 <HAL_RCCEx_PeriphCLKConfig+0x48>
    {
      __HAL_RCC_PWR_CLK_ENABLE();
 800382c:	4b44      	ldr	r3, [pc, #272]	; (8003940 <HAL_RCCEx_PeriphCLKConfig+0x140>)
 800382e:	69db      	ldr	r3, [r3, #28]
 8003830:	4a43      	ldr	r2, [pc, #268]	; (8003940 <HAL_RCCEx_PeriphCLKConfig+0x140>)
 8003832:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
 8003836:	61d3      	str	r3, [r2, #28]
 8003838:	4b41      	ldr	r3, [pc, #260]	; (8003940 <HAL_RCCEx_PeriphCLKConfig+0x140>)
 800383a:	69db      	ldr	r3, [r3, #28]
 800383c:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8003840:	60bb      	str	r3, [r7, #8]
 8003842:	68bb      	ldr	r3, [r7, #8]
      pwrclkchanged = SET;
 8003844:	2301      	movs	r3, #1
 8003846:	75fb      	strb	r3, [r7, #23]
    }

    if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 8003848:	4b3e      	ldr	r3, [pc, #248]	; (8003944 <HAL_RCCEx_PeriphCLKConfig+0x144>)
 800384a:	681b      	ldr	r3, [r3, #0]
 800384c:	f403 7380 	and.w	r3, r3, #256	; 0x100
 8003850:	2b00      	cmp	r3, #0
 8003852:	d118      	bne.n	8003886 <HAL_RCCEx_PeriphCLKConfig+0x86>
    {
      /* Enable write access to Backup domain */
      SET_BIT(PWR->CR, PWR_CR_DBP);
 8003854:	4b3b      	ldr	r3, [pc, #236]	; (8003944 <HAL_RCCEx_PeriphCLKConfig+0x144>)
 8003856:	681b      	ldr	r3, [r3, #0]
 8003858:	4a3a      	ldr	r2, [pc, #232]	; (8003944 <HAL_RCCEx_PeriphCLKConfig+0x144>)
 800385a:	f443 7380 	orr.w	r3, r3, #256	; 0x100
 800385e:	6013      	str	r3, [r2, #0]

      /* Wait for Backup domain Write protection disable */
      tickstart = HAL_GetTick();
 8003860:	f7fd fff4 	bl	800184c <HAL_GetTick>
 8003864:	6138      	str	r0, [r7, #16]

      while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 8003866:	e008      	b.n	800387a <HAL_RCCEx_PeriphCLKConfig+0x7a>
      {
        if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
 8003868:	f7fd fff0 	bl	800184c <HAL_GetTick>
 800386c:	4602      	mov	r2, r0
 800386e:	693b      	ldr	r3, [r7, #16]
 8003870:	1ad3      	subs	r3, r2, r3
 8003872:	2b64      	cmp	r3, #100	; 0x64
 8003874:	d901      	bls.n	800387a <HAL_RCCEx_PeriphCLKConfig+0x7a>
        {
          return HAL_TIMEOUT;
 8003876:	2303      	movs	r3, #3
 8003878:	e05e      	b.n	8003938 <HAL_RCCEx_PeriphCLKConfig+0x138>
      while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 800387a:	4b32      	ldr	r3, [pc, #200]	; (8003944 <HAL_RCCEx_PeriphCLKConfig+0x144>)
 800387c:	681b      	ldr	r3, [r3, #0]
 800387e:	f403 7380 	and.w	r3, r3, #256	; 0x100
 8003882:	2b00      	cmp	r3, #0
 8003884:	d0f0      	beq.n	8003868 <HAL_RCCEx_PeriphCLKConfig+0x68>
        }
      }
    }

    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
    temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
 8003886:	4b2e      	ldr	r3, [pc, #184]	; (8003940 <HAL_RCCEx_PeriphCLKConfig+0x140>)
 8003888:	6a1b      	ldr	r3, [r3, #32]
 800388a:	f403 7340 	and.w	r3, r3, #768	; 0x300
 800388e:	60fb      	str	r3, [r7, #12]
    if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
 8003890:	68fb      	ldr	r3, [r7, #12]
 8003892:	2b00      	cmp	r3, #0
 8003894:	d02e      	beq.n	80038f4 <HAL_RCCEx_PeriphCLKConfig+0xf4>
 8003896:	687b      	ldr	r3, [r7, #4]
 8003898:	685b      	ldr	r3, [r3, #4]
 800389a:	f403 7340 	and.w	r3, r3, #768	; 0x300
 800389e:	68fa      	ldr	r2, [r7, #12]
 80038a0:	429a      	cmp	r2, r3
 80038a2:	d027      	beq.n	80038f4 <HAL_RCCEx_PeriphCLKConfig+0xf4>
    {
      /* Store the content of BDCR register before the reset of Backup Domain */
      temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
 80038a4:	4b26      	ldr	r3, [pc, #152]	; (8003940 <HAL_RCCEx_PeriphCLKConfig+0x140>)
 80038a6:	6a1b      	ldr	r3, [r3, #32]
 80038a8:	f423 7340 	bic.w	r3, r3, #768	; 0x300
 80038ac:	60fb      	str	r3, [r7, #12]
      /* RTC Clock selection can be changed only if the Backup Domain is reset */
      __HAL_RCC_BACKUPRESET_FORCE();
 80038ae:	4b26      	ldr	r3, [pc, #152]	; (8003948 <HAL_RCCEx_PeriphCLKConfig+0x148>)
 80038b0:	2201      	movs	r2, #1
 80038b2:	601a      	str	r2, [r3, #0]
      __HAL_RCC_BACKUPRESET_RELEASE();
 80038b4:	4b24      	ldr	r3, [pc, #144]	; (8003948 <HAL_RCCEx_PeriphCLKConfig+0x148>)
 80038b6:	2200      	movs	r2, #0
 80038b8:	601a      	str	r2, [r3, #0]
      /* Restore the Content of BDCR register */
      RCC->BDCR = temp_reg;
 80038ba:	4a21      	ldr	r2, [pc, #132]	; (8003940 <HAL_RCCEx_PeriphCLKConfig+0x140>)
 80038bc:	68fb      	ldr	r3, [r7, #12]
 80038be:	6213      	str	r3, [r2, #32]

      /* Wait for LSERDY if LSE was enabled */
      if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
 80038c0:	68fb      	ldr	r3, [r7, #12]
 80038c2:	f003 0301 	and.w	r3, r3, #1
 80038c6:	2b00      	cmp	r3, #0
 80038c8:	d014      	beq.n	80038f4 <HAL_RCCEx_PeriphCLKConfig+0xf4>
      {
        /* Get Start Tick */
        tickstart = HAL_GetTick();
 80038ca:	f7fd ffbf 	bl	800184c <HAL_GetTick>
 80038ce:	6138      	str	r0, [r7, #16]

        /* Wait till LSE is ready */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
 80038d0:	e00a      	b.n	80038e8 <HAL_RCCEx_PeriphCLKConfig+0xe8>
        {
          if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 80038d2:	f7fd ffbb 	bl	800184c <HAL_GetTick>
 80038d6:	4602      	mov	r2, r0
 80038d8:	693b      	ldr	r3, [r7, #16]
 80038da:	1ad3      	subs	r3, r2, r3
 80038dc:	f241 3288 	movw	r2, #5000	; 0x1388
 80038e0:	4293      	cmp	r3, r2
 80038e2:	d901      	bls.n	80038e8 <HAL_RCCEx_PeriphCLKConfig+0xe8>
          {
            return HAL_TIMEOUT;
 80038e4:	2303      	movs	r3, #3
 80038e6:	e027      	b.n	8003938 <HAL_RCCEx_PeriphCLKConfig+0x138>
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
 80038e8:	4b15      	ldr	r3, [pc, #84]	; (8003940 <HAL_RCCEx_PeriphCLKConfig+0x140>)
 80038ea:	6a1b      	ldr	r3, [r3, #32]
 80038ec:	f003 0302 	and.w	r3, r3, #2
 80038f0:	2b00      	cmp	r3, #0
 80038f2:	d0ee      	beq.n	80038d2 <HAL_RCCEx_PeriphCLKConfig+0xd2>
          }
        }
      }
    }
    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
 80038f4:	4b12      	ldr	r3, [pc, #72]	; (8003940 <HAL_RCCEx_PeriphCLKConfig+0x140>)
 80038f6:	6a1b      	ldr	r3, [r3, #32]
 80038f8:	f423 7240 	bic.w	r2, r3, #768	; 0x300
 80038fc:	687b      	ldr	r3, [r7, #4]
 80038fe:	685b      	ldr	r3, [r3, #4]
 8003900:	490f      	ldr	r1, [pc, #60]	; (8003940 <HAL_RCCEx_PeriphCLKConfig+0x140>)
 8003902:	4313      	orrs	r3, r2
 8003904:	620b      	str	r3, [r1, #32]

    /* Require to disable power clock if necessary */
    if (pwrclkchanged == SET)
 8003906:	7dfb      	ldrb	r3, [r7, #23]
 8003908:	2b01      	cmp	r3, #1
 800390a:	d105      	bne.n	8003918 <HAL_RCCEx_PeriphCLKConfig+0x118>
    {
      __HAL_RCC_PWR_CLK_DISABLE();
 800390c:	4b0c      	ldr	r3, [pc, #48]	; (8003940 <HAL_RCCEx_PeriphCLKConfig+0x140>)
 800390e:	69db      	ldr	r3, [r3, #28]
 8003910:	4a0b      	ldr	r2, [pc, #44]	; (8003940 <HAL_RCCEx_PeriphCLKConfig+0x140>)
 8003912:	f023 5380 	bic.w	r3, r3, #268435456	; 0x10000000
 8003916:	61d3      	str	r3, [r2, #28]
    }
  }

  /*------------------------------ ADC clock Configuration ------------------*/
  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
 8003918:	687b      	ldr	r3, [r7, #4]
 800391a:	681b      	ldr	r3, [r3, #0]
 800391c:	f003 0302 	and.w	r3, r3, #2
 8003920:	2b00      	cmp	r3, #0
 8003922:	d008      	beq.n	8003936 <HAL_RCCEx_PeriphCLKConfig+0x136>
  {
    /* Check the parameters */
    assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection));

    /* Configure the ADC clock source */
    __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
 8003924:	4b06      	ldr	r3, [pc, #24]	; (8003940 <HAL_RCCEx_PeriphCLKConfig+0x140>)
 8003926:	685b      	ldr	r3, [r3, #4]
 8003928:	f423 4240 	bic.w	r2, r3, #49152	; 0xc000
 800392c:	687b      	ldr	r3, [r7, #4]
 800392e:	689b      	ldr	r3, [r3, #8]
 8003930:	4903      	ldr	r1, [pc, #12]	; (8003940 <HAL_RCCEx_PeriphCLKConfig+0x140>)
 8003932:	4313      	orrs	r3, r2
 8003934:	604b      	str	r3, [r1, #4]
    /* Configure the USB clock source */
    __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
  }
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */

  return HAL_OK;
 8003936:	2300      	movs	r3, #0
}
 8003938:	4618      	mov	r0, r3
 800393a:	3718      	adds	r7, #24
 800393c:	46bd      	mov	sp, r7
 800393e:	bd80      	pop	{r7, pc}
 8003940:	40021000 	.word	0x40021000
 8003944:	40007000 	.word	0x40007000
 8003948:	42420440 	.word	0x42420440

0800394c <HAL_RCCEx_GetPeriphCLKFreq>:
  *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock
  @endif
  * @retval Frequency in Hz (0: means that no available frequency for the peripheral)
  */
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
{
 800394c:	b580      	push	{r7, lr}
 800394e:	b084      	sub	sp, #16
 8003950:	af00      	add	r7, sp, #0
 8003952:	6078      	str	r0, [r7, #4]
  const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
  const uint8_t aPredivFactorTable[2] = {1, 2};

  uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U;
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
  uint32_t temp_reg = 0U, frequency = 0U;
 8003954:	2300      	movs	r3, #0
 8003956:	60bb      	str	r3, [r7, #8]
 8003958:	2300      	movs	r3, #0
 800395a:	60fb      	str	r3, [r7, #12]

  /* Check the parameters */
  assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));

  switch (PeriphClk)
 800395c:	687b      	ldr	r3, [r7, #4]
 800395e:	2b01      	cmp	r3, #1
 8003960:	d002      	beq.n	8003968 <HAL_RCCEx_GetPeriphCLKFreq+0x1c>
 8003962:	2b02      	cmp	r3, #2
 8003964:	d033      	beq.n	80039ce <HAL_RCCEx_GetPeriphCLKFreq+0x82>
      frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2);
      break;
    }
    default:
    {
      break;
 8003966:	e041      	b.n	80039ec <HAL_RCCEx_GetPeriphCLKFreq+0xa0>
      temp_reg = RCC->BDCR;
 8003968:	4b23      	ldr	r3, [pc, #140]	; (80039f8 <HAL_RCCEx_GetPeriphCLKFreq+0xac>)
 800396a:	6a1b      	ldr	r3, [r3, #32]
 800396c:	60bb      	str	r3, [r7, #8]
      if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY)))
 800396e:	68bb      	ldr	r3, [r7, #8]
 8003970:	f403 7340 	and.w	r3, r3, #768	; 0x300
 8003974:	f5b3 7f80 	cmp.w	r3, #256	; 0x100
 8003978:	d108      	bne.n	800398c <HAL_RCCEx_GetPeriphCLKFreq+0x40>
 800397a:	68bb      	ldr	r3, [r7, #8]
 800397c:	f003 0302 	and.w	r3, r3, #2
 8003980:	2b00      	cmp	r3, #0
 8003982:	d003      	beq.n	800398c <HAL_RCCEx_GetPeriphCLKFreq+0x40>
        frequency = LSE_VALUE;
 8003984:	f44f 4300 	mov.w	r3, #32768	; 0x8000
 8003988:	60fb      	str	r3, [r7, #12]
 800398a:	e01f      	b.n	80039cc <HAL_RCCEx_GetPeriphCLKFreq+0x80>
      else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
 800398c:	68bb      	ldr	r3, [r7, #8]
 800398e:	f403 7340 	and.w	r3, r3, #768	; 0x300
 8003992:	f5b3 7f00 	cmp.w	r3, #512	; 0x200
 8003996:	d109      	bne.n	80039ac <HAL_RCCEx_GetPeriphCLKFreq+0x60>
 8003998:	4b17      	ldr	r3, [pc, #92]	; (80039f8 <HAL_RCCEx_GetPeriphCLKFreq+0xac>)
 800399a:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 800399c:	f003 0302 	and.w	r3, r3, #2
 80039a0:	2b00      	cmp	r3, #0
 80039a2:	d003      	beq.n	80039ac <HAL_RCCEx_GetPeriphCLKFreq+0x60>
        frequency = LSI_VALUE;
 80039a4:	f649 4340 	movw	r3, #40000	; 0x9c40
 80039a8:	60fb      	str	r3, [r7, #12]
 80039aa:	e00f      	b.n	80039cc <HAL_RCCEx_GetPeriphCLKFreq+0x80>
      else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)))
 80039ac:	68bb      	ldr	r3, [r7, #8]
 80039ae:	f403 7340 	and.w	r3, r3, #768	; 0x300
 80039b2:	f5b3 7f40 	cmp.w	r3, #768	; 0x300
 80039b6:	d118      	bne.n	80039ea <HAL_RCCEx_GetPeriphCLKFreq+0x9e>
 80039b8:	4b0f      	ldr	r3, [pc, #60]	; (80039f8 <HAL_RCCEx_GetPeriphCLKFreq+0xac>)
 80039ba:	681b      	ldr	r3, [r3, #0]
 80039bc:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 80039c0:	2b00      	cmp	r3, #0
 80039c2:	d012      	beq.n	80039ea <HAL_RCCEx_GetPeriphCLKFreq+0x9e>
        frequency = HSE_VALUE / 128U;
 80039c4:	f24f 4324 	movw	r3, #62500	; 0xf424
 80039c8:	60fb      	str	r3, [r7, #12]
      break;
 80039ca:	e00e      	b.n	80039ea <HAL_RCCEx_GetPeriphCLKFreq+0x9e>
 80039cc:	e00d      	b.n	80039ea <HAL_RCCEx_GetPeriphCLKFreq+0x9e>
      frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2);
 80039ce:	f7ff feb9 	bl	8003744 <HAL_RCC_GetPCLK2Freq>
 80039d2:	4602      	mov	r2, r0
 80039d4:	4b08      	ldr	r3, [pc, #32]	; (80039f8 <HAL_RCCEx_GetPeriphCLKFreq+0xac>)
 80039d6:	685b      	ldr	r3, [r3, #4]
 80039d8:	0b9b      	lsrs	r3, r3, #14
 80039da:	f003 0303 	and.w	r3, r3, #3
 80039de:	3301      	adds	r3, #1
 80039e0:	005b      	lsls	r3, r3, #1
 80039e2:	fbb2 f3f3 	udiv	r3, r2, r3
 80039e6:	60fb      	str	r3, [r7, #12]
      break;
 80039e8:	e000      	b.n	80039ec <HAL_RCCEx_GetPeriphCLKFreq+0xa0>
      break;
 80039ea:	bf00      	nop
    }
  }
  return (frequency);
 80039ec:	68fb      	ldr	r3, [r7, #12]
}
 80039ee:	4618      	mov	r0, r3
 80039f0:	3710      	adds	r7, #16
 80039f2:	46bd      	mov	sp, r7
 80039f4:	bd80      	pop	{r7, pc}
 80039f6:	bf00      	nop
 80039f8:	40021000 	.word	0x40021000

080039fc <HAL_TIM_Base_Init>:
  *         Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
  * @param  htim TIM Base handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
 80039fc:	b580      	push	{r7, lr}
 80039fe:	b082      	sub	sp, #8
 8003a00:	af00      	add	r7, sp, #0
 8003a02:	6078      	str	r0, [r7, #4]
  /* Check the TIM handle allocation */
  if (htim == NULL)
 8003a04:	687b      	ldr	r3, [r7, #4]
 8003a06:	2b00      	cmp	r3, #0
 8003a08:	d101      	bne.n	8003a0e <HAL_TIM_Base_Init+0x12>
  {
    return HAL_ERROR;
 8003a0a:	2301      	movs	r3, #1
 8003a0c:	e01d      	b.n	8003a4a <HAL_TIM_Base_Init+0x4e>
  assert_param(IS_TIM_INSTANCE(htim->Instance));
  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));

  if (htim->State == HAL_TIM_STATE_RESET)
 8003a0e:	687b      	ldr	r3, [r7, #4]
 8003a10:	f893 303d 	ldrb.w	r3, [r3, #61]	; 0x3d
 8003a14:	b2db      	uxtb	r3, r3
 8003a16:	2b00      	cmp	r3, #0
 8003a18:	d106      	bne.n	8003a28 <HAL_TIM_Base_Init+0x2c>
  {
    /* Allocate lock resource and initialize it */
    htim->Lock = HAL_UNLOCKED;
 8003a1a:	687b      	ldr	r3, [r7, #4]
 8003a1c:	2200      	movs	r2, #0
 8003a1e:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c
    }
    /* Init the low level hardware : GPIO, CLOCK, NVIC */
    htim->Base_MspInitCallback(htim);
#else
    /* Init the low level hardware : GPIO, CLOCK, NVIC */
    HAL_TIM_Base_MspInit(htim);
 8003a22:	6878      	ldr	r0, [r7, #4]
 8003a24:	f001 fcc4 	bl	80053b0 <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  }

  /* Set the TIM state */
  htim->State = HAL_TIM_STATE_BUSY;
 8003a28:	687b      	ldr	r3, [r7, #4]
 8003a2a:	2202      	movs	r2, #2
 8003a2c:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d

  /* Set the Time Base configuration */
  TIM_Base_SetConfig(htim->Instance, &htim->Init);
 8003a30:	687b      	ldr	r3, [r7, #4]
 8003a32:	681a      	ldr	r2, [r3, #0]
 8003a34:	687b      	ldr	r3, [r7, #4]
 8003a36:	3304      	adds	r3, #4
 8003a38:	4619      	mov	r1, r3
 8003a3a:	4610      	mov	r0, r2
 8003a3c:	f000 f958 	bl	8003cf0 <TIM_Base_SetConfig>

  /* Initialize the TIM state*/
  htim->State = HAL_TIM_STATE_READY;
 8003a40:	687b      	ldr	r3, [r7, #4]
 8003a42:	2201      	movs	r2, #1
 8003a44:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d

  return HAL_OK;
 8003a48:	2300      	movs	r3, #0
}
 8003a4a:	4618      	mov	r0, r3
 8003a4c:	3708      	adds	r7, #8
 8003a4e:	46bd      	mov	sp, r7
 8003a50:	bd80      	pop	{r7, pc}

08003a52 <HAL_TIM_Base_Start_IT>:
  * @brief  Starts the TIM Base generation in interrupt mode.
  * @param  htim TIM Base handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
{
 8003a52:	b480      	push	{r7}
 8003a54:	b085      	sub	sp, #20
 8003a56:	af00      	add	r7, sp, #0
 8003a58:	6078      	str	r0, [r7, #4]

  /* Check the parameters */
  assert_param(IS_TIM_INSTANCE(htim->Instance));

  /* Enable the TIM Update interrupt */
  __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
 8003a5a:	687b      	ldr	r3, [r7, #4]
 8003a5c:	681b      	ldr	r3, [r3, #0]
 8003a5e:	68da      	ldr	r2, [r3, #12]
 8003a60:	687b      	ldr	r3, [r7, #4]
 8003a62:	681b      	ldr	r3, [r3, #0]
 8003a64:	f042 0201 	orr.w	r2, r2, #1
 8003a68:	60da      	str	r2, [r3, #12]

  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
 8003a6a:	687b      	ldr	r3, [r7, #4]
 8003a6c:	681b      	ldr	r3, [r3, #0]
 8003a6e:	689b      	ldr	r3, [r3, #8]
 8003a70:	f003 0307 	and.w	r3, r3, #7
 8003a74:	60fb      	str	r3, [r7, #12]
  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
 8003a76:	68fb      	ldr	r3, [r7, #12]
 8003a78:	2b06      	cmp	r3, #6
 8003a7a:	d007      	beq.n	8003a8c <HAL_TIM_Base_Start_IT+0x3a>
  {
    __HAL_TIM_ENABLE(htim);
 8003a7c:	687b      	ldr	r3, [r7, #4]
 8003a7e:	681b      	ldr	r3, [r3, #0]
 8003a80:	681a      	ldr	r2, [r3, #0]
 8003a82:	687b      	ldr	r3, [r7, #4]
 8003a84:	681b      	ldr	r3, [r3, #0]
 8003a86:	f042 0201 	orr.w	r2, r2, #1
 8003a8a:	601a      	str	r2, [r3, #0]
  }

  /* Return function status */
  return HAL_OK;
 8003a8c:	2300      	movs	r3, #0
}
 8003a8e:	4618      	mov	r0, r3
 8003a90:	3714      	adds	r7, #20
 8003a92:	46bd      	mov	sp, r7
 8003a94:	bc80      	pop	{r7}
 8003a96:	4770      	bx	lr

08003a98 <HAL_TIM_IRQHandler>:
  * @brief  This function handles TIM interrupts requests.
  * @param  htim TIM  handle
  * @retval None
  */
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
 8003a98:	b580      	push	{r7, lr}
 8003a9a:	b082      	sub	sp, #8
 8003a9c:	af00      	add	r7, sp, #0
 8003a9e:	6078      	str	r0, [r7, #4]
  /* Capture compare 1 event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
 8003aa0:	687b      	ldr	r3, [r7, #4]
 8003aa2:	681b      	ldr	r3, [r3, #0]
 8003aa4:	691b      	ldr	r3, [r3, #16]
 8003aa6:	f003 0302 	and.w	r3, r3, #2
 8003aaa:	2b02      	cmp	r3, #2
 8003aac:	d122      	bne.n	8003af4 <HAL_TIM_IRQHandler+0x5c>
  {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
 8003aae:	687b      	ldr	r3, [r7, #4]
 8003ab0:	681b      	ldr	r3, [r3, #0]
 8003ab2:	68db      	ldr	r3, [r3, #12]
 8003ab4:	f003 0302 	and.w	r3, r3, #2
 8003ab8:	2b02      	cmp	r3, #2
 8003aba:	d11b      	bne.n	8003af4 <HAL_TIM_IRQHandler+0x5c>
    {
      {
        __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
 8003abc:	687b      	ldr	r3, [r7, #4]
 8003abe:	681b      	ldr	r3, [r3, #0]
 8003ac0:	f06f 0202 	mvn.w	r2, #2
 8003ac4:	611a      	str	r2, [r3, #16]
        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
 8003ac6:	687b      	ldr	r3, [r7, #4]
 8003ac8:	2201      	movs	r2, #1
 8003aca:	771a      	strb	r2, [r3, #28]

        /* Input capture event */
        if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
 8003acc:	687b      	ldr	r3, [r7, #4]
 8003ace:	681b      	ldr	r3, [r3, #0]
 8003ad0:	699b      	ldr	r3, [r3, #24]
 8003ad2:	f003 0303 	and.w	r3, r3, #3
 8003ad6:	2b00      	cmp	r3, #0
 8003ad8:	d003      	beq.n	8003ae2 <HAL_TIM_IRQHandler+0x4a>
        {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
          htim->IC_CaptureCallback(htim);
#else
          HAL_TIM_IC_CaptureCallback(htim);
 8003ada:	6878      	ldr	r0, [r7, #4]
 8003adc:	f000 f8ed 	bl	8003cba <HAL_TIM_IC_CaptureCallback>
 8003ae0:	e005      	b.n	8003aee <HAL_TIM_IRQHandler+0x56>
        {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
          htim->OC_DelayElapsedCallback(htim);
          htim->PWM_PulseFinishedCallback(htim);
#else
          HAL_TIM_OC_DelayElapsedCallback(htim);
 8003ae2:	6878      	ldr	r0, [r7, #4]
 8003ae4:	f000 f8e0 	bl	8003ca8 <HAL_TIM_OC_DelayElapsedCallback>
          HAL_TIM_PWM_PulseFinishedCallback(htim);
 8003ae8:	6878      	ldr	r0, [r7, #4]
 8003aea:	f000 f8ef 	bl	8003ccc <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
        }
        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 8003aee:	687b      	ldr	r3, [r7, #4]
 8003af0:	2200      	movs	r2, #0
 8003af2:	771a      	strb	r2, [r3, #28]
      }
    }
  }
  /* Capture compare 2 event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
 8003af4:	687b      	ldr	r3, [r7, #4]
 8003af6:	681b      	ldr	r3, [r3, #0]
 8003af8:	691b      	ldr	r3, [r3, #16]
 8003afa:	f003 0304 	and.w	r3, r3, #4
 8003afe:	2b04      	cmp	r3, #4
 8003b00:	d122      	bne.n	8003b48 <HAL_TIM_IRQHandler+0xb0>
  {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
 8003b02:	687b      	ldr	r3, [r7, #4]
 8003b04:	681b      	ldr	r3, [r3, #0]
 8003b06:	68db      	ldr	r3, [r3, #12]
 8003b08:	f003 0304 	and.w	r3, r3, #4
 8003b0c:	2b04      	cmp	r3, #4
 8003b0e:	d11b      	bne.n	8003b48 <HAL_TIM_IRQHandler+0xb0>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
 8003b10:	687b      	ldr	r3, [r7, #4]
 8003b12:	681b      	ldr	r3, [r3, #0]
 8003b14:	f06f 0204 	mvn.w	r2, #4
 8003b18:	611a      	str	r2, [r3, #16]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
 8003b1a:	687b      	ldr	r3, [r7, #4]
 8003b1c:	2202      	movs	r2, #2
 8003b1e:	771a      	strb	r2, [r3, #28]
      /* Input capture event */
      if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
 8003b20:	687b      	ldr	r3, [r7, #4]
 8003b22:	681b      	ldr	r3, [r3, #0]
 8003b24:	699b      	ldr	r3, [r3, #24]
 8003b26:	f403 7340 	and.w	r3, r3, #768	; 0x300
 8003b2a:	2b00      	cmp	r3, #0
 8003b2c:	d003      	beq.n	8003b36 <HAL_TIM_IRQHandler+0x9e>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->IC_CaptureCallback(htim);
#else
        HAL_TIM_IC_CaptureCallback(htim);
 8003b2e:	6878      	ldr	r0, [r7, #4]
 8003b30:	f000 f8c3 	bl	8003cba <HAL_TIM_IC_CaptureCallback>
 8003b34:	e005      	b.n	8003b42 <HAL_TIM_IRQHandler+0xaa>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->OC_DelayElapsedCallback(htim);
        htim->PWM_PulseFinishedCallback(htim);
#else
        HAL_TIM_OC_DelayElapsedCallback(htim);
 8003b36:	6878      	ldr	r0, [r7, #4]
 8003b38:	f000 f8b6 	bl	8003ca8 <HAL_TIM_OC_DelayElapsedCallback>
        HAL_TIM_PWM_PulseFinishedCallback(htim);
 8003b3c:	6878      	ldr	r0, [r7, #4]
 8003b3e:	f000 f8c5 	bl	8003ccc <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
      }
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 8003b42:	687b      	ldr	r3, [r7, #4]
 8003b44:	2200      	movs	r2, #0
 8003b46:	771a      	strb	r2, [r3, #28]
    }
  }
  /* Capture compare 3 event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
 8003b48:	687b      	ldr	r3, [r7, #4]
 8003b4a:	681b      	ldr	r3, [r3, #0]
 8003b4c:	691b      	ldr	r3, [r3, #16]
 8003b4e:	f003 0308 	and.w	r3, r3, #8
 8003b52:	2b08      	cmp	r3, #8
 8003b54:	d122      	bne.n	8003b9c <HAL_TIM_IRQHandler+0x104>
  {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
 8003b56:	687b      	ldr	r3, [r7, #4]
 8003b58:	681b      	ldr	r3, [r3, #0]
 8003b5a:	68db      	ldr	r3, [r3, #12]
 8003b5c:	f003 0308 	and.w	r3, r3, #8
 8003b60:	2b08      	cmp	r3, #8
 8003b62:	d11b      	bne.n	8003b9c <HAL_TIM_IRQHandler+0x104>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
 8003b64:	687b      	ldr	r3, [r7, #4]
 8003b66:	681b      	ldr	r3, [r3, #0]
 8003b68:	f06f 0208 	mvn.w	r2, #8
 8003b6c:	611a      	str	r2, [r3, #16]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
 8003b6e:	687b      	ldr	r3, [r7, #4]
 8003b70:	2204      	movs	r2, #4
 8003b72:	771a      	strb	r2, [r3, #28]
      /* Input capture event */
      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
 8003b74:	687b      	ldr	r3, [r7, #4]
 8003b76:	681b      	ldr	r3, [r3, #0]
 8003b78:	69db      	ldr	r3, [r3, #28]
 8003b7a:	f003 0303 	and.w	r3, r3, #3
 8003b7e:	2b00      	cmp	r3, #0
 8003b80:	d003      	beq.n	8003b8a <HAL_TIM_IRQHandler+0xf2>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->IC_CaptureCallback(htim);
#else
        HAL_TIM_IC_CaptureCallback(htim);
 8003b82:	6878      	ldr	r0, [r7, #4]
 8003b84:	f000 f899 	bl	8003cba <HAL_TIM_IC_CaptureCallback>
 8003b88:	e005      	b.n	8003b96 <HAL_TIM_IRQHandler+0xfe>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->OC_DelayElapsedCallback(htim);
        htim->PWM_PulseFinishedCallback(htim);
#else
        HAL_TIM_OC_DelayElapsedCallback(htim);
 8003b8a:	6878      	ldr	r0, [r7, #4]
 8003b8c:	f000 f88c 	bl	8003ca8 <HAL_TIM_OC_DelayElapsedCallback>
        HAL_TIM_PWM_PulseFinishedCallback(htim);
 8003b90:	6878      	ldr	r0, [r7, #4]
 8003b92:	f000 f89b 	bl	8003ccc <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
      }
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 8003b96:	687b      	ldr	r3, [r7, #4]
 8003b98:	2200      	movs	r2, #0
 8003b9a:	771a      	strb	r2, [r3, #28]
    }
  }
  /* Capture compare 4 event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
 8003b9c:	687b      	ldr	r3, [r7, #4]
 8003b9e:	681b      	ldr	r3, [r3, #0]
 8003ba0:	691b      	ldr	r3, [r3, #16]
 8003ba2:	f003 0310 	and.w	r3, r3, #16
 8003ba6:	2b10      	cmp	r3, #16
 8003ba8:	d122      	bne.n	8003bf0 <HAL_TIM_IRQHandler+0x158>
  {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
 8003baa:	687b      	ldr	r3, [r7, #4]
 8003bac:	681b      	ldr	r3, [r3, #0]
 8003bae:	68db      	ldr	r3, [r3, #12]
 8003bb0:	f003 0310 	and.w	r3, r3, #16
 8003bb4:	2b10      	cmp	r3, #16
 8003bb6:	d11b      	bne.n	8003bf0 <HAL_TIM_IRQHandler+0x158>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
 8003bb8:	687b      	ldr	r3, [r7, #4]
 8003bba:	681b      	ldr	r3, [r3, #0]
 8003bbc:	f06f 0210 	mvn.w	r2, #16
 8003bc0:	611a      	str	r2, [r3, #16]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
 8003bc2:	687b      	ldr	r3, [r7, #4]
 8003bc4:	2208      	movs	r2, #8
 8003bc6:	771a      	strb	r2, [r3, #28]
      /* Input capture event */
      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
 8003bc8:	687b      	ldr	r3, [r7, #4]
 8003bca:	681b      	ldr	r3, [r3, #0]
 8003bcc:	69db      	ldr	r3, [r3, #28]
 8003bce:	f403 7340 	and.w	r3, r3, #768	; 0x300
 8003bd2:	2b00      	cmp	r3, #0
 8003bd4:	d003      	beq.n	8003bde <HAL_TIM_IRQHandler+0x146>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->IC_CaptureCallback(htim);
#else
        HAL_TIM_IC_CaptureCallback(htim);
 8003bd6:	6878      	ldr	r0, [r7, #4]
 8003bd8:	f000 f86f 	bl	8003cba <HAL_TIM_IC_CaptureCallback>
 8003bdc:	e005      	b.n	8003bea <HAL_TIM_IRQHandler+0x152>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->OC_DelayElapsedCallback(htim);
        htim->PWM_PulseFinishedCallback(htim);
#else
        HAL_TIM_OC_DelayElapsedCallback(htim);
 8003bde:	6878      	ldr	r0, [r7, #4]
 8003be0:	f000 f862 	bl	8003ca8 <HAL_TIM_OC_DelayElapsedCallback>
        HAL_TIM_PWM_PulseFinishedCallback(htim);
 8003be4:	6878      	ldr	r0, [r7, #4]
 8003be6:	f000 f871 	bl	8003ccc <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
      }
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 8003bea:	687b      	ldr	r3, [r7, #4]
 8003bec:	2200      	movs	r2, #0
 8003bee:	771a      	strb	r2, [r3, #28]
    }
  }
  /* TIM Update event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
 8003bf0:	687b      	ldr	r3, [r7, #4]
 8003bf2:	681b      	ldr	r3, [r3, #0]
 8003bf4:	691b      	ldr	r3, [r3, #16]
 8003bf6:	f003 0301 	and.w	r3, r3, #1
 8003bfa:	2b01      	cmp	r3, #1
 8003bfc:	d10e      	bne.n	8003c1c <HAL_TIM_IRQHandler+0x184>
  {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
 8003bfe:	687b      	ldr	r3, [r7, #4]
 8003c00:	681b      	ldr	r3, [r3, #0]
 8003c02:	68db      	ldr	r3, [r3, #12]
 8003c04:	f003 0301 	and.w	r3, r3, #1
 8003c08:	2b01      	cmp	r3, #1
 8003c0a:	d107      	bne.n	8003c1c <HAL_TIM_IRQHandler+0x184>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
 8003c0c:	687b      	ldr	r3, [r7, #4]
 8003c0e:	681b      	ldr	r3, [r3, #0]
 8003c10:	f06f 0201 	mvn.w	r2, #1
 8003c14:	611a      	str	r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
      htim->PeriodElapsedCallback(htim);
#else
      HAL_TIM_PeriodElapsedCallback(htim);
 8003c16:	6878      	ldr	r0, [r7, #4]
 8003c18:	f001 fb06 	bl	8005228 <HAL_TIM_PeriodElapsedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
    }
  }
  /* TIM Break input event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
 8003c1c:	687b      	ldr	r3, [r7, #4]
 8003c1e:	681b      	ldr	r3, [r3, #0]
 8003c20:	691b      	ldr	r3, [r3, #16]
 8003c22:	f003 0380 	and.w	r3, r3, #128	; 0x80
 8003c26:	2b80      	cmp	r3, #128	; 0x80
 8003c28:	d10e      	bne.n	8003c48 <HAL_TIM_IRQHandler+0x1b0>
  {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
 8003c2a:	687b      	ldr	r3, [r7, #4]
 8003c2c:	681b      	ldr	r3, [r3, #0]
 8003c2e:	68db      	ldr	r3, [r3, #12]
 8003c30:	f003 0380 	and.w	r3, r3, #128	; 0x80
 8003c34:	2b80      	cmp	r3, #128	; 0x80
 8003c36:	d107      	bne.n	8003c48 <HAL_TIM_IRQHandler+0x1b0>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
 8003c38:	687b      	ldr	r3, [r7, #4]
 8003c3a:	681b      	ldr	r3, [r3, #0]
 8003c3c:	f06f 0280 	mvn.w	r2, #128	; 0x80
 8003c40:	611a      	str	r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
      htim->BreakCallback(htim);
#else
      HAL_TIMEx_BreakCallback(htim);
 8003c42:	6878      	ldr	r0, [r7, #4]
 8003c44:	f000 f921 	bl	8003e8a <HAL_TIMEx_BreakCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
    }
  }
  /* TIM Trigger detection event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
 8003c48:	687b      	ldr	r3, [r7, #4]
 8003c4a:	681b      	ldr	r3, [r3, #0]
 8003c4c:	691b      	ldr	r3, [r3, #16]
 8003c4e:	f003 0340 	and.w	r3, r3, #64	; 0x40
 8003c52:	2b40      	cmp	r3, #64	; 0x40
 8003c54:	d10e      	bne.n	8003c74 <HAL_TIM_IRQHandler+0x1dc>
  {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
 8003c56:	687b      	ldr	r3, [r7, #4]
 8003c58:	681b      	ldr	r3, [r3, #0]
 8003c5a:	68db      	ldr	r3, [r3, #12]
 8003c5c:	f003 0340 	and.w	r3, r3, #64	; 0x40
 8003c60:	2b40      	cmp	r3, #64	; 0x40
 8003c62:	d107      	bne.n	8003c74 <HAL_TIM_IRQHandler+0x1dc>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
 8003c64:	687b      	ldr	r3, [r7, #4]
 8003c66:	681b      	ldr	r3, [r3, #0]
 8003c68:	f06f 0240 	mvn.w	r2, #64	; 0x40
 8003c6c:	611a      	str	r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
      htim->TriggerCallback(htim);
#else
      HAL_TIM_TriggerCallback(htim);
 8003c6e:	6878      	ldr	r0, [r7, #4]
 8003c70:	f000 f835 	bl	8003cde <HAL_TIM_TriggerCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
    }
  }
  /* TIM commutation event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
 8003c74:	687b      	ldr	r3, [r7, #4]
 8003c76:	681b      	ldr	r3, [r3, #0]
 8003c78:	691b      	ldr	r3, [r3, #16]
 8003c7a:	f003 0320 	and.w	r3, r3, #32
 8003c7e:	2b20      	cmp	r3, #32
 8003c80:	d10e      	bne.n	8003ca0 <HAL_TIM_IRQHandler+0x208>
  {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
 8003c82:	687b      	ldr	r3, [r7, #4]
 8003c84:	681b      	ldr	r3, [r3, #0]
 8003c86:	68db      	ldr	r3, [r3, #12]
 8003c88:	f003 0320 	and.w	r3, r3, #32
 8003c8c:	2b20      	cmp	r3, #32
 8003c8e:	d107      	bne.n	8003ca0 <HAL_TIM_IRQHandler+0x208>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
 8003c90:	687b      	ldr	r3, [r7, #4]
 8003c92:	681b      	ldr	r3, [r3, #0]
 8003c94:	f06f 0220 	mvn.w	r2, #32
 8003c98:	611a      	str	r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
      htim->CommutationCallback(htim);
#else
      HAL_TIMEx_CommutCallback(htim);
 8003c9a:	6878      	ldr	r0, [r7, #4]
 8003c9c:	f000 f8ec 	bl	8003e78 <HAL_TIMEx_CommutCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
    }
  }
}
 8003ca0:	bf00      	nop
 8003ca2:	3708      	adds	r7, #8
 8003ca4:	46bd      	mov	sp, r7
 8003ca6:	bd80      	pop	{r7, pc}

08003ca8 <HAL_TIM_OC_DelayElapsedCallback>:
  * @brief  Output Compare callback in non-blocking mode
  * @param  htim TIM OC handle
  * @retval None
  */
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
{
 8003ca8:	b480      	push	{r7}
 8003caa:	b083      	sub	sp, #12
 8003cac:	af00      	add	r7, sp, #0
 8003cae:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
   */
}
 8003cb0:	bf00      	nop
 8003cb2:	370c      	adds	r7, #12
 8003cb4:	46bd      	mov	sp, r7
 8003cb6:	bc80      	pop	{r7}
 8003cb8:	4770      	bx	lr

08003cba <HAL_TIM_IC_CaptureCallback>:
  * @brief  Input Capture callback in non-blocking mode
  * @param  htim TIM IC handle
  * @retval None
  */
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
{
 8003cba:	b480      	push	{r7}
 8003cbc:	b083      	sub	sp, #12
 8003cbe:	af00      	add	r7, sp, #0
 8003cc0:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_IC_CaptureCallback could be implemented in the user file
   */
}
 8003cc2:	bf00      	nop
 8003cc4:	370c      	adds	r7, #12
 8003cc6:	46bd      	mov	sp, r7
 8003cc8:	bc80      	pop	{r7}
 8003cca:	4770      	bx	lr

08003ccc <HAL_TIM_PWM_PulseFinishedCallback>:
  * @brief  PWM Pulse finished callback in non-blocking mode
  * @param  htim TIM handle
  * @retval None
  */
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
{
 8003ccc:	b480      	push	{r7}
 8003cce:	b083      	sub	sp, #12
 8003cd0:	af00      	add	r7, sp, #0
 8003cd2:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
   */
}
 8003cd4:	bf00      	nop
 8003cd6:	370c      	adds	r7, #12
 8003cd8:	46bd      	mov	sp, r7
 8003cda:	bc80      	pop	{r7}
 8003cdc:	4770      	bx	lr

08003cde <HAL_TIM_TriggerCallback>:
  * @brief  Hall Trigger detection callback in non-blocking mode
  * @param  htim TIM handle
  * @retval None
  */
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
{
 8003cde:	b480      	push	{r7}
 8003ce0:	b083      	sub	sp, #12
 8003ce2:	af00      	add	r7, sp, #0
 8003ce4:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_TriggerCallback could be implemented in the user file
   */
}
 8003ce6:	bf00      	nop
 8003ce8:	370c      	adds	r7, #12
 8003cea:	46bd      	mov	sp, r7
 8003cec:	bc80      	pop	{r7}
 8003cee:	4770      	bx	lr

08003cf0 <TIM_Base_SetConfig>:
  * @param  TIMx TIM peripheral
  * @param  Structure TIM Base configuration structure
  * @retval None
  */
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
{
 8003cf0:	b480      	push	{r7}
 8003cf2:	b085      	sub	sp, #20
 8003cf4:	af00      	add	r7, sp, #0
 8003cf6:	6078      	str	r0, [r7, #4]
 8003cf8:	6039      	str	r1, [r7, #0]
  uint32_t tmpcr1;
  tmpcr1 = TIMx->CR1;
 8003cfa:	687b      	ldr	r3, [r7, #4]
 8003cfc:	681b      	ldr	r3, [r3, #0]
 8003cfe:	60fb      	str	r3, [r7, #12]

  /* Set TIM Time Base Unit parameters ---------------------------------------*/
  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
 8003d00:	687b      	ldr	r3, [r7, #4]
 8003d02:	4a35      	ldr	r2, [pc, #212]	; (8003dd8 <TIM_Base_SetConfig+0xe8>)
 8003d04:	4293      	cmp	r3, r2
 8003d06:	d00b      	beq.n	8003d20 <TIM_Base_SetConfig+0x30>
 8003d08:	687b      	ldr	r3, [r7, #4]
 8003d0a:	f1b3 4f80 	cmp.w	r3, #1073741824	; 0x40000000
 8003d0e:	d007      	beq.n	8003d20 <TIM_Base_SetConfig+0x30>
 8003d10:	687b      	ldr	r3, [r7, #4]
 8003d12:	4a32      	ldr	r2, [pc, #200]	; (8003ddc <TIM_Base_SetConfig+0xec>)
 8003d14:	4293      	cmp	r3, r2
 8003d16:	d003      	beq.n	8003d20 <TIM_Base_SetConfig+0x30>
 8003d18:	687b      	ldr	r3, [r7, #4]
 8003d1a:	4a31      	ldr	r2, [pc, #196]	; (8003de0 <TIM_Base_SetConfig+0xf0>)
 8003d1c:	4293      	cmp	r3, r2
 8003d1e:	d108      	bne.n	8003d32 <TIM_Base_SetConfig+0x42>
  {
    /* Select the Counter Mode */
    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
 8003d20:	68fb      	ldr	r3, [r7, #12]
 8003d22:	f023 0370 	bic.w	r3, r3, #112	; 0x70
 8003d26:	60fb      	str	r3, [r7, #12]
    tmpcr1 |= Structure->CounterMode;
 8003d28:	683b      	ldr	r3, [r7, #0]
 8003d2a:	685b      	ldr	r3, [r3, #4]
 8003d2c:	68fa      	ldr	r2, [r7, #12]
 8003d2e:	4313      	orrs	r3, r2
 8003d30:	60fb      	str	r3, [r7, #12]
  }

  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
 8003d32:	687b      	ldr	r3, [r7, #4]
 8003d34:	4a28      	ldr	r2, [pc, #160]	; (8003dd8 <TIM_Base_SetConfig+0xe8>)
 8003d36:	4293      	cmp	r3, r2
 8003d38:	d017      	beq.n	8003d6a <TIM_Base_SetConfig+0x7a>
 8003d3a:	687b      	ldr	r3, [r7, #4]
 8003d3c:	f1b3 4f80 	cmp.w	r3, #1073741824	; 0x40000000
 8003d40:	d013      	beq.n	8003d6a <TIM_Base_SetConfig+0x7a>
 8003d42:	687b      	ldr	r3, [r7, #4]
 8003d44:	4a25      	ldr	r2, [pc, #148]	; (8003ddc <TIM_Base_SetConfig+0xec>)
 8003d46:	4293      	cmp	r3, r2
 8003d48:	d00f      	beq.n	8003d6a <TIM_Base_SetConfig+0x7a>
 8003d4a:	687b      	ldr	r3, [r7, #4]
 8003d4c:	4a24      	ldr	r2, [pc, #144]	; (8003de0 <TIM_Base_SetConfig+0xf0>)
 8003d4e:	4293      	cmp	r3, r2
 8003d50:	d00b      	beq.n	8003d6a <TIM_Base_SetConfig+0x7a>
 8003d52:	687b      	ldr	r3, [r7, #4]
 8003d54:	4a23      	ldr	r2, [pc, #140]	; (8003de4 <TIM_Base_SetConfig+0xf4>)
 8003d56:	4293      	cmp	r3, r2
 8003d58:	d007      	beq.n	8003d6a <TIM_Base_SetConfig+0x7a>
 8003d5a:	687b      	ldr	r3, [r7, #4]
 8003d5c:	4a22      	ldr	r2, [pc, #136]	; (8003de8 <TIM_Base_SetConfig+0xf8>)
 8003d5e:	4293      	cmp	r3, r2
 8003d60:	d003      	beq.n	8003d6a <TIM_Base_SetConfig+0x7a>
 8003d62:	687b      	ldr	r3, [r7, #4]
 8003d64:	4a21      	ldr	r2, [pc, #132]	; (8003dec <TIM_Base_SetConfig+0xfc>)
 8003d66:	4293      	cmp	r3, r2
 8003d68:	d108      	bne.n	8003d7c <TIM_Base_SetConfig+0x8c>
  {
    /* Set the clock division */
    tmpcr1 &= ~TIM_CR1_CKD;
 8003d6a:	68fb      	ldr	r3, [r7, #12]
 8003d6c:	f423 7340 	bic.w	r3, r3, #768	; 0x300
 8003d70:	60fb      	str	r3, [r7, #12]
    tmpcr1 |= (uint32_t)Structure->ClockDivision;
 8003d72:	683b      	ldr	r3, [r7, #0]
 8003d74:	68db      	ldr	r3, [r3, #12]
 8003d76:	68fa      	ldr	r2, [r7, #12]
 8003d78:	4313      	orrs	r3, r2
 8003d7a:	60fb      	str	r3, [r7, #12]
  }

  /* Set the auto-reload preload */
  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
 8003d7c:	68fb      	ldr	r3, [r7, #12]
 8003d7e:	f023 0280 	bic.w	r2, r3, #128	; 0x80
 8003d82:	683b      	ldr	r3, [r7, #0]
 8003d84:	695b      	ldr	r3, [r3, #20]
 8003d86:	4313      	orrs	r3, r2
 8003d88:	60fb      	str	r3, [r7, #12]

  TIMx->CR1 = tmpcr1;
 8003d8a:	687b      	ldr	r3, [r7, #4]
 8003d8c:	68fa      	ldr	r2, [r7, #12]
 8003d8e:	601a      	str	r2, [r3, #0]

  /* Set the Autoreload value */
  TIMx->ARR = (uint32_t)Structure->Period ;
 8003d90:	683b      	ldr	r3, [r7, #0]
 8003d92:	689a      	ldr	r2, [r3, #8]
 8003d94:	687b      	ldr	r3, [r7, #4]
 8003d96:	62da      	str	r2, [r3, #44]	; 0x2c

  /* Set the Prescaler value */
  TIMx->PSC = Structure->Prescaler;
 8003d98:	683b      	ldr	r3, [r7, #0]
 8003d9a:	681a      	ldr	r2, [r3, #0]
 8003d9c:	687b      	ldr	r3, [r7, #4]
 8003d9e:	629a      	str	r2, [r3, #40]	; 0x28

  if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
 8003da0:	687b      	ldr	r3, [r7, #4]
 8003da2:	4a0d      	ldr	r2, [pc, #52]	; (8003dd8 <TIM_Base_SetConfig+0xe8>)
 8003da4:	4293      	cmp	r3, r2
 8003da6:	d00b      	beq.n	8003dc0 <TIM_Base_SetConfig+0xd0>
 8003da8:	687b      	ldr	r3, [r7, #4]
 8003daa:	4a0e      	ldr	r2, [pc, #56]	; (8003de4 <TIM_Base_SetConfig+0xf4>)
 8003dac:	4293      	cmp	r3, r2
 8003dae:	d007      	beq.n	8003dc0 <TIM_Base_SetConfig+0xd0>
 8003db0:	687b      	ldr	r3, [r7, #4]
 8003db2:	4a0d      	ldr	r2, [pc, #52]	; (8003de8 <TIM_Base_SetConfig+0xf8>)
 8003db4:	4293      	cmp	r3, r2
 8003db6:	d003      	beq.n	8003dc0 <TIM_Base_SetConfig+0xd0>
 8003db8:	687b      	ldr	r3, [r7, #4]
 8003dba:	4a0c      	ldr	r2, [pc, #48]	; (8003dec <TIM_Base_SetConfig+0xfc>)
 8003dbc:	4293      	cmp	r3, r2
 8003dbe:	d103      	bne.n	8003dc8 <TIM_Base_SetConfig+0xd8>
  {
    /* Set the Repetition Counter value */
    TIMx->RCR = Structure->RepetitionCounter;
 8003dc0:	683b      	ldr	r3, [r7, #0]
 8003dc2:	691a      	ldr	r2, [r3, #16]
 8003dc4:	687b      	ldr	r3, [r7, #4]
 8003dc6:	631a      	str	r2, [r3, #48]	; 0x30
  }

  /* Generate an update event to reload the Prescaler
     and the repetition counter (only for advanced timer) value immediately */
  TIMx->EGR = TIM_EGR_UG;
 8003dc8:	687b      	ldr	r3, [r7, #4]
 8003dca:	2201      	movs	r2, #1
 8003dcc:	615a      	str	r2, [r3, #20]
}
 8003dce:	bf00      	nop
 8003dd0:	3714      	adds	r7, #20
 8003dd2:	46bd      	mov	sp, r7
 8003dd4:	bc80      	pop	{r7}
 8003dd6:	4770      	bx	lr
 8003dd8:	40012c00 	.word	0x40012c00
 8003ddc:	40000400 	.word	0x40000400
 8003de0:	40000800 	.word	0x40000800
 8003de4:	40014000 	.word	0x40014000
 8003de8:	40014400 	.word	0x40014400
 8003dec:	40014800 	.word	0x40014800

08003df0 <HAL_TIMEx_MasterConfigSynchronization>:
  *         mode.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
                                                        TIM_MasterConfigTypeDef *sMasterConfig)
{
 8003df0:	b480      	push	{r7}
 8003df2:	b085      	sub	sp, #20
 8003df4:	af00      	add	r7, sp, #0
 8003df6:	6078      	str	r0, [r7, #4]
 8003df8:	6039      	str	r1, [r7, #0]
  assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));
  assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
  assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));

  /* Check input state */
  __HAL_LOCK(htim);
 8003dfa:	687b      	ldr	r3, [r7, #4]
 8003dfc:	f893 303c 	ldrb.w	r3, [r3, #60]	; 0x3c
 8003e00:	2b01      	cmp	r3, #1
 8003e02:	d101      	bne.n	8003e08 <HAL_TIMEx_MasterConfigSynchronization+0x18>
 8003e04:	2302      	movs	r3, #2
 8003e06:	e032      	b.n	8003e6e <HAL_TIMEx_MasterConfigSynchronization+0x7e>
 8003e08:	687b      	ldr	r3, [r7, #4]
 8003e0a:	2201      	movs	r2, #1
 8003e0c:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c

  /* Change the handler state */
  htim->State = HAL_TIM_STATE_BUSY;
 8003e10:	687b      	ldr	r3, [r7, #4]
 8003e12:	2202      	movs	r2, #2
 8003e14:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d

  /* Get the TIMx CR2 register value */
  tmpcr2 = htim->Instance->CR2;
 8003e18:	687b      	ldr	r3, [r7, #4]
 8003e1a:	681b      	ldr	r3, [r3, #0]
 8003e1c:	685b      	ldr	r3, [r3, #4]
 8003e1e:	60fb      	str	r3, [r7, #12]

  /* Get the TIMx SMCR register value */
  tmpsmcr = htim->Instance->SMCR;
 8003e20:	687b      	ldr	r3, [r7, #4]
 8003e22:	681b      	ldr	r3, [r3, #0]
 8003e24:	689b      	ldr	r3, [r3, #8]
 8003e26:	60bb      	str	r3, [r7, #8]

  /* Reset the MMS Bits */
  tmpcr2 &= ~TIM_CR2_MMS;
 8003e28:	68fb      	ldr	r3, [r7, #12]
 8003e2a:	f023 0370 	bic.w	r3, r3, #112	; 0x70
 8003e2e:	60fb      	str	r3, [r7, #12]
  /* Select the TRGO source */
  tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
 8003e30:	683b      	ldr	r3, [r7, #0]
 8003e32:	681b      	ldr	r3, [r3, #0]
 8003e34:	68fa      	ldr	r2, [r7, #12]
 8003e36:	4313      	orrs	r3, r2
 8003e38:	60fb      	str	r3, [r7, #12]

  /* Reset the MSM Bit */
  tmpsmcr &= ~TIM_SMCR_MSM;
 8003e3a:	68bb      	ldr	r3, [r7, #8]
 8003e3c:	f023 0380 	bic.w	r3, r3, #128	; 0x80
 8003e40:	60bb      	str	r3, [r7, #8]
  /* Set master mode */
  tmpsmcr |= sMasterConfig->MasterSlaveMode;
 8003e42:	683b      	ldr	r3, [r7, #0]
 8003e44:	685b      	ldr	r3, [r3, #4]
 8003e46:	68ba      	ldr	r2, [r7, #8]
 8003e48:	4313      	orrs	r3, r2
 8003e4a:	60bb      	str	r3, [r7, #8]

  /* Update TIMx CR2 */
  htim->Instance->CR2 = tmpcr2;
 8003e4c:	687b      	ldr	r3, [r7, #4]
 8003e4e:	681b      	ldr	r3, [r3, #0]
 8003e50:	68fa      	ldr	r2, [r7, #12]
 8003e52:	605a      	str	r2, [r3, #4]

  /* Update TIMx SMCR */
  htim->Instance->SMCR = tmpsmcr;
 8003e54:	687b      	ldr	r3, [r7, #4]
 8003e56:	681b      	ldr	r3, [r3, #0]
 8003e58:	68ba      	ldr	r2, [r7, #8]
 8003e5a:	609a      	str	r2, [r3, #8]

  /* Change the htim state */
  htim->State = HAL_TIM_STATE_READY;
 8003e5c:	687b      	ldr	r3, [r7, #4]
 8003e5e:	2201      	movs	r2, #1
 8003e60:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d

  __HAL_UNLOCK(htim);
 8003e64:	687b      	ldr	r3, [r7, #4]
 8003e66:	2200      	movs	r2, #0
 8003e68:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c

  return HAL_OK;
 8003e6c:	2300      	movs	r3, #0
}
 8003e6e:	4618      	mov	r0, r3
 8003e70:	3714      	adds	r7, #20
 8003e72:	46bd      	mov	sp, r7
 8003e74:	bc80      	pop	{r7}
 8003e76:	4770      	bx	lr

08003e78 <HAL_TIMEx_CommutCallback>:
  * @brief  Hall commutation changed callback in non-blocking mode
  * @param  htim TIM handle
  * @retval None
  */
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
{
 8003e78:	b480      	push	{r7}
 8003e7a:	b083      	sub	sp, #12
 8003e7c:	af00      	add	r7, sp, #0
 8003e7e:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIMEx_CommutCallback could be implemented in the user file
   */
}
 8003e80:	bf00      	nop
 8003e82:	370c      	adds	r7, #12
 8003e84:	46bd      	mov	sp, r7
 8003e86:	bc80      	pop	{r7}
 8003e88:	4770      	bx	lr

08003e8a <HAL_TIMEx_BreakCallback>:
  * @brief  Hall Break detection callback in non-blocking mode
  * @param  htim TIM handle
  * @retval None
  */
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
{
 8003e8a:	b480      	push	{r7}
 8003e8c:	b083      	sub	sp, #12
 8003e8e:	af00      	add	r7, sp, #0
 8003e90:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIMEx_BreakCallback could be implemented in the user file
   */
}
 8003e92:	bf00      	nop
 8003e94:	370c      	adds	r7, #12
 8003e96:	46bd      	mov	sp, r7
 8003e98:	bc80      	pop	{r7}
 8003e9a:	4770      	bx	lr

08003e9c <HAL_UART_Init>:
  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
  *                the configuration information for the specified UART module.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
 8003e9c:	b580      	push	{r7, lr}
 8003e9e:	b082      	sub	sp, #8
 8003ea0:	af00      	add	r7, sp, #0
 8003ea2:	6078      	str	r0, [r7, #4]
  /* Check the UART handle allocation */
  if (huart == NULL)
 8003ea4:	687b      	ldr	r3, [r7, #4]
 8003ea6:	2b00      	cmp	r3, #0
 8003ea8:	d101      	bne.n	8003eae <HAL_UART_Init+0x12>
  {
    return HAL_ERROR;
 8003eaa:	2301      	movs	r3, #1
 8003eac:	e03f      	b.n	8003f2e <HAL_UART_Init+0x92>
  assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
#if defined(USART_CR1_OVER8)
  assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
#endif /* USART_CR1_OVER8 */

  if (huart->gState == HAL_UART_STATE_RESET)
 8003eae:	687b      	ldr	r3, [r7, #4]
 8003eb0:	f893 3039 	ldrb.w	r3, [r3, #57]	; 0x39
 8003eb4:	b2db      	uxtb	r3, r3
 8003eb6:	2b00      	cmp	r3, #0
 8003eb8:	d106      	bne.n	8003ec8 <HAL_UART_Init+0x2c>
  {
    /* Allocate lock resource and initialize it */
    huart->Lock = HAL_UNLOCKED;
 8003eba:	687b      	ldr	r3, [r7, #4]
 8003ebc:	2200      	movs	r2, #0
 8003ebe:	f883 2038 	strb.w	r2, [r3, #56]	; 0x38

    /* Init the low level hardware */
    huart->MspInitCallback(huart);
#else
    /* Init the low level hardware : GPIO, CLOCK */
    HAL_UART_MspInit(huart);
 8003ec2:	6878      	ldr	r0, [r7, #4]
 8003ec4:	f001 fa92 	bl	80053ec <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
  }

  huart->gState = HAL_UART_STATE_BUSY;
 8003ec8:	687b      	ldr	r3, [r7, #4]
 8003eca:	2224      	movs	r2, #36	; 0x24
 8003ecc:	f883 2039 	strb.w	r2, [r3, #57]	; 0x39

  /* Disable the peripheral */
  __HAL_UART_DISABLE(huart);
 8003ed0:	687b      	ldr	r3, [r7, #4]
 8003ed2:	681b      	ldr	r3, [r3, #0]
 8003ed4:	68da      	ldr	r2, [r3, #12]
 8003ed6:	687b      	ldr	r3, [r7, #4]
 8003ed8:	681b      	ldr	r3, [r3, #0]
 8003eda:	f422 5200 	bic.w	r2, r2, #8192	; 0x2000
 8003ede:	60da      	str	r2, [r3, #12]

  /* Set the UART Communication parameters */
  UART_SetConfig(huart);
 8003ee0:	6878      	ldr	r0, [r7, #4]
 8003ee2:	f000 fd63 	bl	80049ac <UART_SetConfig>

  /* In asynchronous mode, the following bits must be kept cleared:
     - LINEN and CLKEN bits in the USART_CR2 register,
     - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
 8003ee6:	687b      	ldr	r3, [r7, #4]
 8003ee8:	681b      	ldr	r3, [r3, #0]
 8003eea:	691a      	ldr	r2, [r3, #16]
 8003eec:	687b      	ldr	r3, [r7, #4]
 8003eee:	681b      	ldr	r3, [r3, #0]
 8003ef0:	f422 4290 	bic.w	r2, r2, #18432	; 0x4800
 8003ef4:	611a      	str	r2, [r3, #16]
  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
 8003ef6:	687b      	ldr	r3, [r7, #4]
 8003ef8:	681b      	ldr	r3, [r3, #0]
 8003efa:	695a      	ldr	r2, [r3, #20]
 8003efc:	687b      	ldr	r3, [r7, #4]
 8003efe:	681b      	ldr	r3, [r3, #0]
 8003f00:	f022 022a 	bic.w	r2, r2, #42	; 0x2a
 8003f04:	615a      	str	r2, [r3, #20]

  /* Enable the peripheral */
  __HAL_UART_ENABLE(huart);
 8003f06:	687b      	ldr	r3, [r7, #4]
 8003f08:	681b      	ldr	r3, [r3, #0]
 8003f0a:	68da      	ldr	r2, [r3, #12]
 8003f0c:	687b      	ldr	r3, [r7, #4]
 8003f0e:	681b      	ldr	r3, [r3, #0]
 8003f10:	f442 5200 	orr.w	r2, r2, #8192	; 0x2000
 8003f14:	60da      	str	r2, [r3, #12]

  /* Initialize the UART state */
  huart->ErrorCode = HAL_UART_ERROR_NONE;
 8003f16:	687b      	ldr	r3, [r7, #4]
 8003f18:	2200      	movs	r2, #0
 8003f1a:	63da      	str	r2, [r3, #60]	; 0x3c
  huart->gState = HAL_UART_STATE_READY;
 8003f1c:	687b      	ldr	r3, [r7, #4]
 8003f1e:	2220      	movs	r2, #32
 8003f20:	f883 2039 	strb.w	r2, [r3, #57]	; 0x39
  huart->RxState = HAL_UART_STATE_READY;
 8003f24:	687b      	ldr	r3, [r7, #4]
 8003f26:	2220      	movs	r2, #32
 8003f28:	f883 203a 	strb.w	r2, [r3, #58]	; 0x3a

  return HAL_OK;
 8003f2c:	2300      	movs	r3, #0
}
 8003f2e:	4618      	mov	r0, r3
 8003f30:	3708      	adds	r7, #8
 8003f32:	46bd      	mov	sp, r7
 8003f34:	bd80      	pop	{r7, pc}

08003f36 <HAL_UART_Transmit>:
  * @param  Size  Amount of data elements (u8 or u16) to be sent
  * @param  Timeout Timeout duration
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
 8003f36:	b580      	push	{r7, lr}
 8003f38:	b088      	sub	sp, #32
 8003f3a:	af02      	add	r7, sp, #8
 8003f3c:	60f8      	str	r0, [r7, #12]
 8003f3e:	60b9      	str	r1, [r7, #8]
 8003f40:	603b      	str	r3, [r7, #0]
 8003f42:	4613      	mov	r3, r2
 8003f44:	80fb      	strh	r3, [r7, #6]
  uint16_t *tmp;
  uint32_t tickstart = 0U;
 8003f46:	2300      	movs	r3, #0
 8003f48:	617b      	str	r3, [r7, #20]

  /* Check that a Tx process is not already ongoing */
  if (huart->gState == HAL_UART_STATE_READY)
 8003f4a:	68fb      	ldr	r3, [r7, #12]
 8003f4c:	f893 3039 	ldrb.w	r3, [r3, #57]	; 0x39
 8003f50:	b2db      	uxtb	r3, r3
 8003f52:	2b20      	cmp	r3, #32
 8003f54:	f040 8083 	bne.w	800405e <HAL_UART_Transmit+0x128>
  {
    if ((pData == NULL) || (Size == 0U))
 8003f58:	68bb      	ldr	r3, [r7, #8]
 8003f5a:	2b00      	cmp	r3, #0
 8003f5c:	d002      	beq.n	8003f64 <HAL_UART_Transmit+0x2e>
 8003f5e:	88fb      	ldrh	r3, [r7, #6]
 8003f60:	2b00      	cmp	r3, #0
 8003f62:	d101      	bne.n	8003f68 <HAL_UART_Transmit+0x32>
    {
      return  HAL_ERROR;
 8003f64:	2301      	movs	r3, #1
 8003f66:	e07b      	b.n	8004060 <HAL_UART_Transmit+0x12a>
    }

    /* Process Locked */
    __HAL_LOCK(huart);
 8003f68:	68fb      	ldr	r3, [r7, #12]
 8003f6a:	f893 3038 	ldrb.w	r3, [r3, #56]	; 0x38
 8003f6e:	2b01      	cmp	r3, #1
 8003f70:	d101      	bne.n	8003f76 <HAL_UART_Transmit+0x40>
 8003f72:	2302      	movs	r3, #2
 8003f74:	e074      	b.n	8004060 <HAL_UART_Transmit+0x12a>
 8003f76:	68fb      	ldr	r3, [r7, #12]
 8003f78:	2201      	movs	r2, #1
 8003f7a:	f883 2038 	strb.w	r2, [r3, #56]	; 0x38

    huart->ErrorCode = HAL_UART_ERROR_NONE;
 8003f7e:	68fb      	ldr	r3, [r7, #12]
 8003f80:	2200      	movs	r2, #0
 8003f82:	63da      	str	r2, [r3, #60]	; 0x3c
    huart->gState = HAL_UART_STATE_BUSY_TX;
 8003f84:	68fb      	ldr	r3, [r7, #12]
 8003f86:	2221      	movs	r2, #33	; 0x21
 8003f88:	f883 2039 	strb.w	r2, [r3, #57]	; 0x39

    /* Init tickstart for timeout managment */
    tickstart = HAL_GetTick();
 8003f8c:	f7fd fc5e 	bl	800184c <HAL_GetTick>
 8003f90:	6178      	str	r0, [r7, #20]

    huart->TxXferSize = Size;
 8003f92:	68fb      	ldr	r3, [r7, #12]
 8003f94:	88fa      	ldrh	r2, [r7, #6]
 8003f96:	849a      	strh	r2, [r3, #36]	; 0x24
    huart->TxXferCount = Size;
 8003f98:	68fb      	ldr	r3, [r7, #12]
 8003f9a:	88fa      	ldrh	r2, [r7, #6]
 8003f9c:	84da      	strh	r2, [r3, #38]	; 0x26
    while (huart->TxXferCount > 0U)
 8003f9e:	e042      	b.n	8004026 <HAL_UART_Transmit+0xf0>
    {
      huart->TxXferCount--;
 8003fa0:	68fb      	ldr	r3, [r7, #12]
 8003fa2:	8cdb      	ldrh	r3, [r3, #38]	; 0x26
 8003fa4:	b29b      	uxth	r3, r3
 8003fa6:	3b01      	subs	r3, #1
 8003fa8:	b29a      	uxth	r2, r3
 8003faa:	68fb      	ldr	r3, [r7, #12]
 8003fac:	84da      	strh	r2, [r3, #38]	; 0x26
      if (huart->Init.WordLength == UART_WORDLENGTH_9B)
 8003fae:	68fb      	ldr	r3, [r7, #12]
 8003fb0:	689b      	ldr	r3, [r3, #8]
 8003fb2:	f5b3 5f80 	cmp.w	r3, #4096	; 0x1000
 8003fb6:	d122      	bne.n	8003ffe <HAL_UART_Transmit+0xc8>
      {
        if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
 8003fb8:	683b      	ldr	r3, [r7, #0]
 8003fba:	9300      	str	r3, [sp, #0]
 8003fbc:	697b      	ldr	r3, [r7, #20]
 8003fbe:	2200      	movs	r2, #0
 8003fc0:	2180      	movs	r1, #128	; 0x80
 8003fc2:	68f8      	ldr	r0, [r7, #12]
 8003fc4:	f000 fb73 	bl	80046ae <UART_WaitOnFlagUntilTimeout>
 8003fc8:	4603      	mov	r3, r0
 8003fca:	2b00      	cmp	r3, #0
 8003fcc:	d001      	beq.n	8003fd2 <HAL_UART_Transmit+0x9c>
        {
          return HAL_TIMEOUT;
 8003fce:	2303      	movs	r3, #3
 8003fd0:	e046      	b.n	8004060 <HAL_UART_Transmit+0x12a>
        }
        tmp = (uint16_t *) pData;
 8003fd2:	68bb      	ldr	r3, [r7, #8]
 8003fd4:	613b      	str	r3, [r7, #16]
        huart->Instance->DR = (*tmp & (uint16_t)0x01FF);
 8003fd6:	693b      	ldr	r3, [r7, #16]
 8003fd8:	881b      	ldrh	r3, [r3, #0]
 8003fda:	461a      	mov	r2, r3
 8003fdc:	68fb      	ldr	r3, [r7, #12]
 8003fde:	681b      	ldr	r3, [r3, #0]
 8003fe0:	f3c2 0208 	ubfx	r2, r2, #0, #9
 8003fe4:	605a      	str	r2, [r3, #4]
        if (huart->Init.Parity == UART_PARITY_NONE)
 8003fe6:	68fb      	ldr	r3, [r7, #12]
 8003fe8:	691b      	ldr	r3, [r3, #16]
 8003fea:	2b00      	cmp	r3, #0
 8003fec:	d103      	bne.n	8003ff6 <HAL_UART_Transmit+0xc0>
        {
          pData += 2U;
 8003fee:	68bb      	ldr	r3, [r7, #8]
 8003ff0:	3302      	adds	r3, #2
 8003ff2:	60bb      	str	r3, [r7, #8]
 8003ff4:	e017      	b.n	8004026 <HAL_UART_Transmit+0xf0>
        }
        else
        {
          pData += 1U;
 8003ff6:	68bb      	ldr	r3, [r7, #8]
 8003ff8:	3301      	adds	r3, #1
 8003ffa:	60bb      	str	r3, [r7, #8]
 8003ffc:	e013      	b.n	8004026 <HAL_UART_Transmit+0xf0>
        }
      }
      else
      {
        if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
 8003ffe:	683b      	ldr	r3, [r7, #0]
 8004000:	9300      	str	r3, [sp, #0]
 8004002:	697b      	ldr	r3, [r7, #20]
 8004004:	2200      	movs	r2, #0
 8004006:	2180      	movs	r1, #128	; 0x80
 8004008:	68f8      	ldr	r0, [r7, #12]
 800400a:	f000 fb50 	bl	80046ae <UART_WaitOnFlagUntilTimeout>
 800400e:	4603      	mov	r3, r0
 8004010:	2b00      	cmp	r3, #0
 8004012:	d001      	beq.n	8004018 <HAL_UART_Transmit+0xe2>
        {
          return HAL_TIMEOUT;
 8004014:	2303      	movs	r3, #3
 8004016:	e023      	b.n	8004060 <HAL_UART_Transmit+0x12a>
        }
        huart->Instance->DR = (*pData++ & (uint8_t)0xFF);
 8004018:	68bb      	ldr	r3, [r7, #8]
 800401a:	1c5a      	adds	r2, r3, #1
 800401c:	60ba      	str	r2, [r7, #8]
 800401e:	781a      	ldrb	r2, [r3, #0]
 8004020:	68fb      	ldr	r3, [r7, #12]
 8004022:	681b      	ldr	r3, [r3, #0]
 8004024:	605a      	str	r2, [r3, #4]
    while (huart->TxXferCount > 0U)
 8004026:	68fb      	ldr	r3, [r7, #12]
 8004028:	8cdb      	ldrh	r3, [r3, #38]	; 0x26
 800402a:	b29b      	uxth	r3, r3
 800402c:	2b00      	cmp	r3, #0
 800402e:	d1b7      	bne.n	8003fa0 <HAL_UART_Transmit+0x6a>
      }
    }

    if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
 8004030:	683b      	ldr	r3, [r7, #0]
 8004032:	9300      	str	r3, [sp, #0]
 8004034:	697b      	ldr	r3, [r7, #20]
 8004036:	2200      	movs	r2, #0
 8004038:	2140      	movs	r1, #64	; 0x40
 800403a:	68f8      	ldr	r0, [r7, #12]
 800403c:	f000 fb37 	bl	80046ae <UART_WaitOnFlagUntilTimeout>
 8004040:	4603      	mov	r3, r0
 8004042:	2b00      	cmp	r3, #0
 8004044:	d001      	beq.n	800404a <HAL_UART_Transmit+0x114>
    {
      return HAL_TIMEOUT;
 8004046:	2303      	movs	r3, #3
 8004048:	e00a      	b.n	8004060 <HAL_UART_Transmit+0x12a>
    }

    /* At end of Tx process, restore huart->gState to Ready */
    huart->gState = HAL_UART_STATE_READY;
 800404a:	68fb      	ldr	r3, [r7, #12]
 800404c:	2220      	movs	r2, #32
 800404e:	f883 2039 	strb.w	r2, [r3, #57]	; 0x39

    /* Process Unlocked */
    __HAL_UNLOCK(huart);
 8004052:	68fb      	ldr	r3, [r7, #12]
 8004054:	2200      	movs	r2, #0
 8004056:	f883 2038 	strb.w	r2, [r3, #56]	; 0x38

    return HAL_OK;
 800405a:	2300      	movs	r3, #0
 800405c:	e000      	b.n	8004060 <HAL_UART_Transmit+0x12a>
  }
  else
  {
    return HAL_BUSY;
 800405e:	2302      	movs	r3, #2
  }
}
 8004060:	4618      	mov	r0, r3
 8004062:	3718      	adds	r7, #24
 8004064:	46bd      	mov	sp, r7
 8004066:	bd80      	pop	{r7, pc}

08004068 <HAL_UART_Receive_IT>:
  * @param  pData Pointer to data buffer (u8 or u16 data elements).
  * @param  Size  Amount of data elements (u8 or u16) to be received.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
 8004068:	b480      	push	{r7}
 800406a:	b085      	sub	sp, #20
 800406c:	af00      	add	r7, sp, #0
 800406e:	60f8      	str	r0, [r7, #12]
 8004070:	60b9      	str	r1, [r7, #8]
 8004072:	4613      	mov	r3, r2
 8004074:	80fb      	strh	r3, [r7, #6]
  /* Check that a Rx process is not already ongoing */
  if (huart->RxState == HAL_UART_STATE_READY)
 8004076:	68fb      	ldr	r3, [r7, #12]
 8004078:	f893 303a 	ldrb.w	r3, [r3, #58]	; 0x3a
 800407c:	b2db      	uxtb	r3, r3
 800407e:	2b20      	cmp	r3, #32
 8004080:	d140      	bne.n	8004104 <HAL_UART_Receive_IT+0x9c>
  {
    if ((pData == NULL) || (Size == 0U))
 8004082:	68bb      	ldr	r3, [r7, #8]
 8004084:	2b00      	cmp	r3, #0
 8004086:	d002      	beq.n	800408e <HAL_UART_Receive_IT+0x26>
 8004088:	88fb      	ldrh	r3, [r7, #6]
 800408a:	2b00      	cmp	r3, #0
 800408c:	d101      	bne.n	8004092 <HAL_UART_Receive_IT+0x2a>
    {
      return HAL_ERROR;
 800408e:	2301      	movs	r3, #1
 8004090:	e039      	b.n	8004106 <HAL_UART_Receive_IT+0x9e>
    }

    /* Process Locked */
    __HAL_LOCK(huart);
 8004092:	68fb      	ldr	r3, [r7, #12]
 8004094:	f893 3038 	ldrb.w	r3, [r3, #56]	; 0x38
 8004098:	2b01      	cmp	r3, #1
 800409a:	d101      	bne.n	80040a0 <HAL_UART_Receive_IT+0x38>
 800409c:	2302      	movs	r3, #2
 800409e:	e032      	b.n	8004106 <HAL_UART_Receive_IT+0x9e>
 80040a0:	68fb      	ldr	r3, [r7, #12]
 80040a2:	2201      	movs	r2, #1
 80040a4:	f883 2038 	strb.w	r2, [r3, #56]	; 0x38

    huart->pRxBuffPtr = pData;
 80040a8:	68fb      	ldr	r3, [r7, #12]
 80040aa:	68ba      	ldr	r2, [r7, #8]
 80040ac:	629a      	str	r2, [r3, #40]	; 0x28
    huart->RxXferSize = Size;
 80040ae:	68fb      	ldr	r3, [r7, #12]
 80040b0:	88fa      	ldrh	r2, [r7, #6]
 80040b2:	859a      	strh	r2, [r3, #44]	; 0x2c
    huart->RxXferCount = Size;
 80040b4:	68fb      	ldr	r3, [r7, #12]
 80040b6:	88fa      	ldrh	r2, [r7, #6]
 80040b8:	85da      	strh	r2, [r3, #46]	; 0x2e

    huart->ErrorCode = HAL_UART_ERROR_NONE;
 80040ba:	68fb      	ldr	r3, [r7, #12]
 80040bc:	2200      	movs	r2, #0
 80040be:	63da      	str	r2, [r3, #60]	; 0x3c
    huart->RxState = HAL_UART_STATE_BUSY_RX;
 80040c0:	68fb      	ldr	r3, [r7, #12]
 80040c2:	2222      	movs	r2, #34	; 0x22
 80040c4:	f883 203a 	strb.w	r2, [r3, #58]	; 0x3a

    /* Process Unlocked */
    __HAL_UNLOCK(huart);
 80040c8:	68fb      	ldr	r3, [r7, #12]
 80040ca:	2200      	movs	r2, #0
 80040cc:	f883 2038 	strb.w	r2, [r3, #56]	; 0x38

    /* Enable the UART Parity Error Interrupt */
    __HAL_UART_ENABLE_IT(huart, UART_IT_PE);
 80040d0:	68fb      	ldr	r3, [r7, #12]
 80040d2:	681b      	ldr	r3, [r3, #0]
 80040d4:	68da      	ldr	r2, [r3, #12]
 80040d6:	68fb      	ldr	r3, [r7, #12]
 80040d8:	681b      	ldr	r3, [r3, #0]
 80040da:	f442 7280 	orr.w	r2, r2, #256	; 0x100
 80040de:	60da      	str	r2, [r3, #12]

    /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
    __HAL_UART_ENABLE_IT(huart, UART_IT_ERR);
 80040e0:	68fb      	ldr	r3, [r7, #12]
 80040e2:	681b      	ldr	r3, [r3, #0]
 80040e4:	695a      	ldr	r2, [r3, #20]
 80040e6:	68fb      	ldr	r3, [r7, #12]
 80040e8:	681b      	ldr	r3, [r3, #0]
 80040ea:	f042 0201 	orr.w	r2, r2, #1
 80040ee:	615a      	str	r2, [r3, #20]

    /* Enable the UART Data Register not empty Interrupt */
    __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE);
 80040f0:	68fb      	ldr	r3, [r7, #12]
 80040f2:	681b      	ldr	r3, [r3, #0]
 80040f4:	68da      	ldr	r2, [r3, #12]
 80040f6:	68fb      	ldr	r3, [r7, #12]
 80040f8:	681b      	ldr	r3, [r3, #0]
 80040fa:	f042 0220 	orr.w	r2, r2, #32
 80040fe:	60da      	str	r2, [r3, #12]

    return HAL_OK;
 8004100:	2300      	movs	r3, #0
 8004102:	e000      	b.n	8004106 <HAL_UART_Receive_IT+0x9e>
  }
  else
  {
    return HAL_BUSY;
 8004104:	2302      	movs	r3, #2
  }
}
 8004106:	4618      	mov	r0, r3
 8004108:	3714      	adds	r7, #20
 800410a:	46bd      	mov	sp, r7
 800410c:	bc80      	pop	{r7}
 800410e:	4770      	bx	lr

08004110 <HAL_UART_Transmit_DMA>:
  * @param  pData Pointer to data buffer (u8 or u16 data elements).
  * @param  Size  Amount of data elements (u8 or u16) to be sent
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
 8004110:	b580      	push	{r7, lr}
 8004112:	b086      	sub	sp, #24
 8004114:	af00      	add	r7, sp, #0
 8004116:	60f8      	str	r0, [r7, #12]
 8004118:	60b9      	str	r1, [r7, #8]
 800411a:	4613      	mov	r3, r2
 800411c:	80fb      	strh	r3, [r7, #6]
  uint32_t *tmp;

  /* Check that a Tx process is not already ongoing */
  if (huart->gState == HAL_UART_STATE_READY)
 800411e:	68fb      	ldr	r3, [r7, #12]
 8004120:	f893 3039 	ldrb.w	r3, [r3, #57]	; 0x39
 8004124:	b2db      	uxtb	r3, r3
 8004126:	2b20      	cmp	r3, #32
 8004128:	d153      	bne.n	80041d2 <HAL_UART_Transmit_DMA+0xc2>
  {
    if ((pData == NULL) || (Size == 0U))
 800412a:	68bb      	ldr	r3, [r7, #8]
 800412c:	2b00      	cmp	r3, #0
 800412e:	d002      	beq.n	8004136 <HAL_UART_Transmit_DMA+0x26>
 8004130:	88fb      	ldrh	r3, [r7, #6]
 8004132:	2b00      	cmp	r3, #0
 8004134:	d101      	bne.n	800413a <HAL_UART_Transmit_DMA+0x2a>
    {
      return HAL_ERROR;
 8004136:	2301      	movs	r3, #1
 8004138:	e04c      	b.n	80041d4 <HAL_UART_Transmit_DMA+0xc4>
    }

    /* Process Locked */
    __HAL_LOCK(huart);
 800413a:	68fb      	ldr	r3, [r7, #12]
 800413c:	f893 3038 	ldrb.w	r3, [r3, #56]	; 0x38
 8004140:	2b01      	cmp	r3, #1
 8004142:	d101      	bne.n	8004148 <HAL_UART_Transmit_DMA+0x38>
 8004144:	2302      	movs	r3, #2
 8004146:	e045      	b.n	80041d4 <HAL_UART_Transmit_DMA+0xc4>
 8004148:	68fb      	ldr	r3, [r7, #12]
 800414a:	2201      	movs	r2, #1
 800414c:	f883 2038 	strb.w	r2, [r3, #56]	; 0x38

    huart->pTxBuffPtr = pData;
 8004150:	68ba      	ldr	r2, [r7, #8]
 8004152:	68fb      	ldr	r3, [r7, #12]
 8004154:	621a      	str	r2, [r3, #32]
    huart->TxXferSize = Size;
 8004156:	68fb      	ldr	r3, [r7, #12]
 8004158:	88fa      	ldrh	r2, [r7, #6]
 800415a:	849a      	strh	r2, [r3, #36]	; 0x24
    huart->TxXferCount = Size;
 800415c:	68fb      	ldr	r3, [r7, #12]
 800415e:	88fa      	ldrh	r2, [r7, #6]
 8004160:	84da      	strh	r2, [r3, #38]	; 0x26

    huart->ErrorCode = HAL_UART_ERROR_NONE;
 8004162:	68fb      	ldr	r3, [r7, #12]
 8004164:	2200      	movs	r2, #0
 8004166:	63da      	str	r2, [r3, #60]	; 0x3c
    huart->gState = HAL_UART_STATE_BUSY_TX;
 8004168:	68fb      	ldr	r3, [r7, #12]
 800416a:	2221      	movs	r2, #33	; 0x21
 800416c:	f883 2039 	strb.w	r2, [r3, #57]	; 0x39

    /* Set the UART DMA transfer complete callback */
    huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
 8004170:	68fb      	ldr	r3, [r7, #12]
 8004172:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 8004174:	4a19      	ldr	r2, [pc, #100]	; (80041dc <HAL_UART_Transmit_DMA+0xcc>)
 8004176:	629a      	str	r2, [r3, #40]	; 0x28

    /* Set the UART DMA Half transfer complete callback */
    huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
 8004178:	68fb      	ldr	r3, [r7, #12]
 800417a:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 800417c:	4a18      	ldr	r2, [pc, #96]	; (80041e0 <HAL_UART_Transmit_DMA+0xd0>)
 800417e:	62da      	str	r2, [r3, #44]	; 0x2c

    /* Set the DMA error callback */
    huart->hdmatx->XferErrorCallback = UART_DMAError;
 8004180:	68fb      	ldr	r3, [r7, #12]
 8004182:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 8004184:	4a17      	ldr	r2, [pc, #92]	; (80041e4 <HAL_UART_Transmit_DMA+0xd4>)
 8004186:	631a      	str	r2, [r3, #48]	; 0x30

    /* Set the DMA abort callback */
    huart->hdmatx->XferAbortCallback = NULL;
 8004188:	68fb      	ldr	r3, [r7, #12]
 800418a:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 800418c:	2200      	movs	r2, #0
 800418e:	635a      	str	r2, [r3, #52]	; 0x34

    /* Enable the UART transmit DMA channel */
    tmp = (uint32_t *)&pData;
 8004190:	f107 0308 	add.w	r3, r7, #8
 8004194:	617b      	str	r3, [r7, #20]
    HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t *)tmp, (uint32_t)&huart->Instance->DR, Size);
 8004196:	68fb      	ldr	r3, [r7, #12]
 8004198:	6b18      	ldr	r0, [r3, #48]	; 0x30
 800419a:	697b      	ldr	r3, [r7, #20]
 800419c:	6819      	ldr	r1, [r3, #0]
 800419e:	68fb      	ldr	r3, [r7, #12]
 80041a0:	681b      	ldr	r3, [r3, #0]
 80041a2:	3304      	adds	r3, #4
 80041a4:	461a      	mov	r2, r3
 80041a6:	88fb      	ldrh	r3, [r7, #6]
 80041a8:	f7fe f996 	bl	80024d8 <HAL_DMA_Start_IT>

    /* Clear the TC flag in the SR register by writing 0 to it */
    __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
 80041ac:	68fb      	ldr	r3, [r7, #12]
 80041ae:	681b      	ldr	r3, [r3, #0]
 80041b0:	f06f 0240 	mvn.w	r2, #64	; 0x40
 80041b4:	601a      	str	r2, [r3, #0]

    /* Process Unlocked */
    __HAL_UNLOCK(huart);
 80041b6:	68fb      	ldr	r3, [r7, #12]
 80041b8:	2200      	movs	r2, #0
 80041ba:	f883 2038 	strb.w	r2, [r3, #56]	; 0x38

    /* Enable the DMA transfer for transmit request by setting the DMAT bit
       in the UART CR3 register */
    SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
 80041be:	68fb      	ldr	r3, [r7, #12]
 80041c0:	681b      	ldr	r3, [r3, #0]
 80041c2:	695a      	ldr	r2, [r3, #20]
 80041c4:	68fb      	ldr	r3, [r7, #12]
 80041c6:	681b      	ldr	r3, [r3, #0]
 80041c8:	f042 0280 	orr.w	r2, r2, #128	; 0x80
 80041cc:	615a      	str	r2, [r3, #20]

    return HAL_OK;
 80041ce:	2300      	movs	r3, #0
 80041d0:	e000      	b.n	80041d4 <HAL_UART_Transmit_DMA+0xc4>
  }
  else
  {
    return HAL_BUSY;
 80041d2:	2302      	movs	r3, #2
  }
}
 80041d4:	4618      	mov	r0, r3
 80041d6:	3718      	adds	r7, #24
 80041d8:	46bd      	mov	sp, r7
 80041da:	bd80      	pop	{r7, pc}
 80041dc:	08004529 	.word	0x08004529
 80041e0:	0800457b 	.word	0x0800457b
 80041e4:	0800461b 	.word	0x0800461b

080041e8 <HAL_UART_Receive_DMA>:
  * @param  Size  Amount of data elements (u8 or u16) to be received.
  * @note   When the UART parity is enabled (PCE = 1) the received data contains the parity bit.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
 80041e8:	b580      	push	{r7, lr}
 80041ea:	b086      	sub	sp, #24
 80041ec:	af00      	add	r7, sp, #0
 80041ee:	60f8      	str	r0, [r7, #12]
 80041f0:	60b9      	str	r1, [r7, #8]
 80041f2:	4613      	mov	r3, r2
 80041f4:	80fb      	strh	r3, [r7, #6]
  uint32_t *tmp;

  /* Check that a Rx process is not already ongoing */
  if (huart->RxState == HAL_UART_STATE_READY)
 80041f6:	68fb      	ldr	r3, [r7, #12]
 80041f8:	f893 303a 	ldrb.w	r3, [r3, #58]	; 0x3a
 80041fc:	b2db      	uxtb	r3, r3
 80041fe:	2b20      	cmp	r3, #32
 8004200:	d166      	bne.n	80042d0 <HAL_UART_Receive_DMA+0xe8>
  {
    if ((pData == NULL) || (Size == 0U))
 8004202:	68bb      	ldr	r3, [r7, #8]
 8004204:	2b00      	cmp	r3, #0
 8004206:	d002      	beq.n	800420e <HAL_UART_Receive_DMA+0x26>
 8004208:	88fb      	ldrh	r3, [r7, #6]
 800420a:	2b00      	cmp	r3, #0
 800420c:	d101      	bne.n	8004212 <HAL_UART_Receive_DMA+0x2a>
    {
      return HAL_ERROR;
 800420e:	2301      	movs	r3, #1
 8004210:	e05f      	b.n	80042d2 <HAL_UART_Receive_DMA+0xea>
    }

    /* Process Locked */
    __HAL_LOCK(huart);
 8004212:	68fb      	ldr	r3, [r7, #12]
 8004214:	f893 3038 	ldrb.w	r3, [r3, #56]	; 0x38
 8004218:	2b01      	cmp	r3, #1
 800421a:	d101      	bne.n	8004220 <HAL_UART_Receive_DMA+0x38>
 800421c:	2302      	movs	r3, #2
 800421e:	e058      	b.n	80042d2 <HAL_UART_Receive_DMA+0xea>
 8004220:	68fb      	ldr	r3, [r7, #12]
 8004222:	2201      	movs	r2, #1
 8004224:	f883 2038 	strb.w	r2, [r3, #56]	; 0x38

    huart->pRxBuffPtr = pData;
 8004228:	68ba      	ldr	r2, [r7, #8]
 800422a:	68fb      	ldr	r3, [r7, #12]
 800422c:	629a      	str	r2, [r3, #40]	; 0x28
    huart->RxXferSize = Size;
 800422e:	68fb      	ldr	r3, [r7, #12]
 8004230:	88fa      	ldrh	r2, [r7, #6]
 8004232:	859a      	strh	r2, [r3, #44]	; 0x2c

    huart->ErrorCode = HAL_UART_ERROR_NONE;
 8004234:	68fb      	ldr	r3, [r7, #12]
 8004236:	2200      	movs	r2, #0
 8004238:	63da      	str	r2, [r3, #60]	; 0x3c
    huart->RxState = HAL_UART_STATE_BUSY_RX;
 800423a:	68fb      	ldr	r3, [r7, #12]
 800423c:	2222      	movs	r2, #34	; 0x22
 800423e:	f883 203a 	strb.w	r2, [r3, #58]	; 0x3a

    /* Set the UART DMA transfer complete callback */
    huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
 8004242:	68fb      	ldr	r3, [r7, #12]
 8004244:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 8004246:	4a25      	ldr	r2, [pc, #148]	; (80042dc <HAL_UART_Receive_DMA+0xf4>)
 8004248:	629a      	str	r2, [r3, #40]	; 0x28

    /* Set the UART DMA Half transfer complete callback */
    huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
 800424a:	68fb      	ldr	r3, [r7, #12]
 800424c:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 800424e:	4a24      	ldr	r2, [pc, #144]	; (80042e0 <HAL_UART_Receive_DMA+0xf8>)
 8004250:	62da      	str	r2, [r3, #44]	; 0x2c

    /* Set the DMA error callback */
    huart->hdmarx->XferErrorCallback = UART_DMAError;
 8004252:	68fb      	ldr	r3, [r7, #12]
 8004254:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 8004256:	4a23      	ldr	r2, [pc, #140]	; (80042e4 <HAL_UART_Receive_DMA+0xfc>)
 8004258:	631a      	str	r2, [r3, #48]	; 0x30

    /* Set the DMA abort callback */
    huart->hdmarx->XferAbortCallback = NULL;
 800425a:	68fb      	ldr	r3, [r7, #12]
 800425c:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 800425e:	2200      	movs	r2, #0
 8004260:	635a      	str	r2, [r3, #52]	; 0x34

    /* Enable the DMA channel */
    tmp = (uint32_t *)&pData;
 8004262:	f107 0308 	add.w	r3, r7, #8
 8004266:	617b      	str	r3, [r7, #20]
    HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t *)tmp, Size);
 8004268:	68fb      	ldr	r3, [r7, #12]
 800426a:	6b58      	ldr	r0, [r3, #52]	; 0x34
 800426c:	68fb      	ldr	r3, [r7, #12]
 800426e:	681b      	ldr	r3, [r3, #0]
 8004270:	3304      	adds	r3, #4
 8004272:	4619      	mov	r1, r3
 8004274:	697b      	ldr	r3, [r7, #20]
 8004276:	681a      	ldr	r2, [r3, #0]
 8004278:	88fb      	ldrh	r3, [r7, #6]
 800427a:	f7fe f92d 	bl	80024d8 <HAL_DMA_Start_IT>

    /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */
    __HAL_UART_CLEAR_OREFLAG(huart);
 800427e:	2300      	movs	r3, #0
 8004280:	613b      	str	r3, [r7, #16]
 8004282:	68fb      	ldr	r3, [r7, #12]
 8004284:	681b      	ldr	r3, [r3, #0]
 8004286:	681b      	ldr	r3, [r3, #0]
 8004288:	613b      	str	r3, [r7, #16]
 800428a:	68fb      	ldr	r3, [r7, #12]
 800428c:	681b      	ldr	r3, [r3, #0]
 800428e:	685b      	ldr	r3, [r3, #4]
 8004290:	613b      	str	r3, [r7, #16]
 8004292:	693b      	ldr	r3, [r7, #16]

    /* Process Unlocked */
    __HAL_UNLOCK(huart);
 8004294:	68fb      	ldr	r3, [r7, #12]
 8004296:	2200      	movs	r2, #0
 8004298:	f883 2038 	strb.w	r2, [r3, #56]	; 0x38

    /* Enable the UART Parity Error Interrupt */
    SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
 800429c:	68fb      	ldr	r3, [r7, #12]
 800429e:	681b      	ldr	r3, [r3, #0]
 80042a0:	68da      	ldr	r2, [r3, #12]
 80042a2:	68fb      	ldr	r3, [r7, #12]
 80042a4:	681b      	ldr	r3, [r3, #0]
 80042a6:	f442 7280 	orr.w	r2, r2, #256	; 0x100
 80042aa:	60da      	str	r2, [r3, #12]

    /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
    SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
 80042ac:	68fb      	ldr	r3, [r7, #12]
 80042ae:	681b      	ldr	r3, [r3, #0]
 80042b0:	695a      	ldr	r2, [r3, #20]
 80042b2:	68fb      	ldr	r3, [r7, #12]
 80042b4:	681b      	ldr	r3, [r3, #0]
 80042b6:	f042 0201 	orr.w	r2, r2, #1
 80042ba:	615a      	str	r2, [r3, #20]

    /* Enable the DMA transfer for the receiver request by setting the DMAR bit
    in the UART CR3 register */
    SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
 80042bc:	68fb      	ldr	r3, [r7, #12]
 80042be:	681b      	ldr	r3, [r3, #0]
 80042c0:	695a      	ldr	r2, [r3, #20]
 80042c2:	68fb      	ldr	r3, [r7, #12]
 80042c4:	681b      	ldr	r3, [r3, #0]
 80042c6:	f042 0240 	orr.w	r2, r2, #64	; 0x40
 80042ca:	615a      	str	r2, [r3, #20]

    return HAL_OK;
 80042cc:	2300      	movs	r3, #0
 80042ce:	e000      	b.n	80042d2 <HAL_UART_Receive_DMA+0xea>
  }
  else
  {
    return HAL_BUSY;
 80042d0:	2302      	movs	r3, #2
  }
}
 80042d2:	4618      	mov	r0, r3
 80042d4:	3718      	adds	r7, #24
 80042d6:	46bd      	mov	sp, r7
 80042d8:	bd80      	pop	{r7, pc}
 80042da:	bf00      	nop
 80042dc:	08004597 	.word	0x08004597
 80042e0:	080045ff 	.word	0x080045ff
 80042e4:	0800461b 	.word	0x0800461b

080042e8 <HAL_UART_IRQHandler>:
  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
  *                the configuration information for the specified UART module.
  * @retval None
  */
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
{
 80042e8:	b580      	push	{r7, lr}
 80042ea:	b088      	sub	sp, #32
 80042ec:	af00      	add	r7, sp, #0
 80042ee:	6078      	str	r0, [r7, #4]
  uint32_t isrflags   = READ_REG(huart->Instance->SR);
 80042f0:	687b      	ldr	r3, [r7, #4]
 80042f2:	681b      	ldr	r3, [r3, #0]
 80042f4:	681b      	ldr	r3, [r3, #0]
 80042f6:	61fb      	str	r3, [r7, #28]
  uint32_t cr1its     = READ_REG(huart->Instance->CR1);
 80042f8:	687b      	ldr	r3, [r7, #4]
 80042fa:	681b      	ldr	r3, [r3, #0]
 80042fc:	68db      	ldr	r3, [r3, #12]
 80042fe:	61bb      	str	r3, [r7, #24]
  uint32_t cr3its     = READ_REG(huart->Instance->CR3);
 8004300:	687b      	ldr	r3, [r7, #4]
 8004302:	681b      	ldr	r3, [r3, #0]
 8004304:	695b      	ldr	r3, [r3, #20]
 8004306:	617b      	str	r3, [r7, #20]
  uint32_t errorflags = 0x00U;
 8004308:	2300      	movs	r3, #0
 800430a:	613b      	str	r3, [r7, #16]
  uint32_t dmarequest = 0x00U;
 800430c:	2300      	movs	r3, #0
 800430e:	60fb      	str	r3, [r7, #12]

  /* If no error occurs */
  errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
 8004310:	69fb      	ldr	r3, [r7, #28]
 8004312:	f003 030f 	and.w	r3, r3, #15
 8004316:	613b      	str	r3, [r7, #16]
  if (errorflags == RESET)
 8004318:	693b      	ldr	r3, [r7, #16]
 800431a:	2b00      	cmp	r3, #0
 800431c:	d10d      	bne.n	800433a <HAL_UART_IRQHandler+0x52>
  {
    /* UART in mode Receiver -------------------------------------------------*/
    if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
 800431e:	69fb      	ldr	r3, [r7, #28]
 8004320:	f003 0320 	and.w	r3, r3, #32
 8004324:	2b00      	cmp	r3, #0
 8004326:	d008      	beq.n	800433a <HAL_UART_IRQHandler+0x52>
 8004328:	69bb      	ldr	r3, [r7, #24]
 800432a:	f003 0320 	and.w	r3, r3, #32
 800432e:	2b00      	cmp	r3, #0
 8004330:	d003      	beq.n	800433a <HAL_UART_IRQHandler+0x52>
    {
      UART_Receive_IT(huart);
 8004332:	6878      	ldr	r0, [r7, #4]
 8004334:	f000 fab8 	bl	80048a8 <UART_Receive_IT>
      return;
 8004338:	e0cc      	b.n	80044d4 <HAL_UART_IRQHandler+0x1ec>
    }
  }

  /* If some errors occur */
  if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
 800433a:	693b      	ldr	r3, [r7, #16]
 800433c:	2b00      	cmp	r3, #0
 800433e:	f000 80ab 	beq.w	8004498 <HAL_UART_IRQHandler+0x1b0>
 8004342:	697b      	ldr	r3, [r7, #20]
 8004344:	f003 0301 	and.w	r3, r3, #1
 8004348:	2b00      	cmp	r3, #0
 800434a:	d105      	bne.n	8004358 <HAL_UART_IRQHandler+0x70>
 800434c:	69bb      	ldr	r3, [r7, #24]
 800434e:	f403 7390 	and.w	r3, r3, #288	; 0x120
 8004352:	2b00      	cmp	r3, #0
 8004354:	f000 80a0 	beq.w	8004498 <HAL_UART_IRQHandler+0x1b0>
  {
    /* UART parity error interrupt occurred ----------------------------------*/
    if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
 8004358:	69fb      	ldr	r3, [r7, #28]
 800435a:	f003 0301 	and.w	r3, r3, #1
 800435e:	2b00      	cmp	r3, #0
 8004360:	d00a      	beq.n	8004378 <HAL_UART_IRQHandler+0x90>
 8004362:	69bb      	ldr	r3, [r7, #24]
 8004364:	f403 7380 	and.w	r3, r3, #256	; 0x100
 8004368:	2b00      	cmp	r3, #0
 800436a:	d005      	beq.n	8004378 <HAL_UART_IRQHandler+0x90>
    {
      huart->ErrorCode |= HAL_UART_ERROR_PE;
 800436c:	687b      	ldr	r3, [r7, #4]
 800436e:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
 8004370:	f043 0201 	orr.w	r2, r3, #1
 8004374:	687b      	ldr	r3, [r7, #4]
 8004376:	63da      	str	r2, [r3, #60]	; 0x3c
    }

    /* UART noise error interrupt occurred -----------------------------------*/
    if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
 8004378:	69fb      	ldr	r3, [r7, #28]
 800437a:	f003 0304 	and.w	r3, r3, #4
 800437e:	2b00      	cmp	r3, #0
 8004380:	d00a      	beq.n	8004398 <HAL_UART_IRQHandler+0xb0>
 8004382:	697b      	ldr	r3, [r7, #20]
 8004384:	f003 0301 	and.w	r3, r3, #1
 8004388:	2b00      	cmp	r3, #0
 800438a:	d005      	beq.n	8004398 <HAL_UART_IRQHandler+0xb0>
    {
      huart->ErrorCode |= HAL_UART_ERROR_NE;
 800438c:	687b      	ldr	r3, [r7, #4]
 800438e:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
 8004390:	f043 0202 	orr.w	r2, r3, #2
 8004394:	687b      	ldr	r3, [r7, #4]
 8004396:	63da      	str	r2, [r3, #60]	; 0x3c
    }

    /* UART frame error interrupt occurred -----------------------------------*/
    if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
 8004398:	69fb      	ldr	r3, [r7, #28]
 800439a:	f003 0302 	and.w	r3, r3, #2
 800439e:	2b00      	cmp	r3, #0
 80043a0:	d00a      	beq.n	80043b8 <HAL_UART_IRQHandler+0xd0>
 80043a2:	697b      	ldr	r3, [r7, #20]
 80043a4:	f003 0301 	and.w	r3, r3, #1
 80043a8:	2b00      	cmp	r3, #0
 80043aa:	d005      	beq.n	80043b8 <HAL_UART_IRQHandler+0xd0>
    {
      huart->ErrorCode |= HAL_UART_ERROR_FE;
 80043ac:	687b      	ldr	r3, [r7, #4]
 80043ae:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
 80043b0:	f043 0204 	orr.w	r2, r3, #4
 80043b4:	687b      	ldr	r3, [r7, #4]
 80043b6:	63da      	str	r2, [r3, #60]	; 0x3c
    }

    /* UART Over-Run interrupt occurred --------------------------------------*/
    if (((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
 80043b8:	69fb      	ldr	r3, [r7, #28]
 80043ba:	f003 0308 	and.w	r3, r3, #8
 80043be:	2b00      	cmp	r3, #0
 80043c0:	d00a      	beq.n	80043d8 <HAL_UART_IRQHandler+0xf0>
 80043c2:	697b      	ldr	r3, [r7, #20]
 80043c4:	f003 0301 	and.w	r3, r3, #1
 80043c8:	2b00      	cmp	r3, #0
 80043ca:	d005      	beq.n	80043d8 <HAL_UART_IRQHandler+0xf0>
    {
      huart->ErrorCode |= HAL_UART_ERROR_ORE;
 80043cc:	687b      	ldr	r3, [r7, #4]
 80043ce:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
 80043d0:	f043 0208 	orr.w	r2, r3, #8
 80043d4:	687b      	ldr	r3, [r7, #4]
 80043d6:	63da      	str	r2, [r3, #60]	; 0x3c
    }

    /* Call UART Error Call back function if need be --------------------------*/
    if (huart->ErrorCode != HAL_UART_ERROR_NONE)
 80043d8:	687b      	ldr	r3, [r7, #4]
 80043da:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
 80043dc:	2b00      	cmp	r3, #0
 80043de:	d078      	beq.n	80044d2 <HAL_UART_IRQHandler+0x1ea>
    {
      /* UART in mode Receiver -----------------------------------------------*/
      if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
 80043e0:	69fb      	ldr	r3, [r7, #28]
 80043e2:	f003 0320 	and.w	r3, r3, #32
 80043e6:	2b00      	cmp	r3, #0
 80043e8:	d007      	beq.n	80043fa <HAL_UART_IRQHandler+0x112>
 80043ea:	69bb      	ldr	r3, [r7, #24]
 80043ec:	f003 0320 	and.w	r3, r3, #32
 80043f0:	2b00      	cmp	r3, #0
 80043f2:	d002      	beq.n	80043fa <HAL_UART_IRQHandler+0x112>
      {
        UART_Receive_IT(huart);
 80043f4:	6878      	ldr	r0, [r7, #4]
 80043f6:	f000 fa57 	bl	80048a8 <UART_Receive_IT>
      }

      /* If Overrun error occurs, or if any error occurs in DMA mode reception,
         consider error as blocking */
      dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
 80043fa:	687b      	ldr	r3, [r7, #4]
 80043fc:	681b      	ldr	r3, [r3, #0]
 80043fe:	695b      	ldr	r3, [r3, #20]
 8004400:	f003 0340 	and.w	r3, r3, #64	; 0x40
 8004404:	2b00      	cmp	r3, #0
 8004406:	bf14      	ite	ne
 8004408:	2301      	movne	r3, #1
 800440a:	2300      	moveq	r3, #0
 800440c:	b2db      	uxtb	r3, r3
 800440e:	60fb      	str	r3, [r7, #12]
      if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest)
 8004410:	687b      	ldr	r3, [r7, #4]
 8004412:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
 8004414:	f003 0308 	and.w	r3, r3, #8
 8004418:	2b00      	cmp	r3, #0
 800441a:	d102      	bne.n	8004422 <HAL_UART_IRQHandler+0x13a>
 800441c:	68fb      	ldr	r3, [r7, #12]
 800441e:	2b00      	cmp	r3, #0
 8004420:	d031      	beq.n	8004486 <HAL_UART_IRQHandler+0x19e>
      {
        /* Blocking error : transfer is aborted
           Set the UART state ready to be able to start again the process,
           Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
        UART_EndRxTransfer(huart);
 8004422:	6878      	ldr	r0, [r7, #4]
 8004424:	f000 f9a2 	bl	800476c <UART_EndRxTransfer>

        /* Disable the UART DMA Rx request if enabled */
        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
 8004428:	687b      	ldr	r3, [r7, #4]
 800442a:	681b      	ldr	r3, [r3, #0]
 800442c:	695b      	ldr	r3, [r3, #20]
 800442e:	f003 0340 	and.w	r3, r3, #64	; 0x40
 8004432:	2b00      	cmp	r3, #0
 8004434:	d023      	beq.n	800447e <HAL_UART_IRQHandler+0x196>
        {
          CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
 8004436:	687b      	ldr	r3, [r7, #4]
 8004438:	681b      	ldr	r3, [r3, #0]
 800443a:	695a      	ldr	r2, [r3, #20]
 800443c:	687b      	ldr	r3, [r7, #4]
 800443e:	681b      	ldr	r3, [r3, #0]
 8004440:	f022 0240 	bic.w	r2, r2, #64	; 0x40
 8004444:	615a      	str	r2, [r3, #20]

          /* Abort the UART DMA Rx channel */
          if (huart->hdmarx != NULL)
 8004446:	687b      	ldr	r3, [r7, #4]
 8004448:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 800444a:	2b00      	cmp	r3, #0
 800444c:	d013      	beq.n	8004476 <HAL_UART_IRQHandler+0x18e>
          {
            /* Set the UART DMA Abort callback :
               will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
            huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
 800444e:	687b      	ldr	r3, [r7, #4]
 8004450:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 8004452:	4a22      	ldr	r2, [pc, #136]	; (80044dc <HAL_UART_IRQHandler+0x1f4>)
 8004454:	635a      	str	r2, [r3, #52]	; 0x34
            if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
 8004456:	687b      	ldr	r3, [r7, #4]
 8004458:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 800445a:	4618      	mov	r0, r3
 800445c:	f7fe f89c 	bl	8002598 <HAL_DMA_Abort_IT>
 8004460:	4603      	mov	r3, r0
 8004462:	2b00      	cmp	r3, #0
 8004464:	d016      	beq.n	8004494 <HAL_UART_IRQHandler+0x1ac>
            {
              /* Call Directly XferAbortCallback function in case of error */
              huart->hdmarx->XferAbortCallback(huart->hdmarx);
 8004466:	687b      	ldr	r3, [r7, #4]
 8004468:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 800446a:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 800446c:	687a      	ldr	r2, [r7, #4]
 800446e:	6b52      	ldr	r2, [r2, #52]	; 0x34
 8004470:	4610      	mov	r0, r2
 8004472:	4798      	blx	r3
        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
 8004474:	e00e      	b.n	8004494 <HAL_UART_IRQHandler+0x1ac>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
            /*Call registered error callback*/
            huart->ErrorCallback(huart);
#else
            /*Call legacy weak error callback*/
            HAL_UART_ErrorCallback(huart);
 8004476:	6878      	ldr	r0, [r7, #4]
 8004478:	f000 f84d 	bl	8004516 <HAL_UART_ErrorCallback>
        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
 800447c:	e00a      	b.n	8004494 <HAL_UART_IRQHandler+0x1ac>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
          /*Call registered error callback*/
          huart->ErrorCallback(huart);
#else
          /*Call legacy weak error callback*/
          HAL_UART_ErrorCallback(huart);
 800447e:	6878      	ldr	r0, [r7, #4]
 8004480:	f000 f849 	bl	8004516 <HAL_UART_ErrorCallback>
        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
 8004484:	e006      	b.n	8004494 <HAL_UART_IRQHandler+0x1ac>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
        /*Call registered error callback*/
        huart->ErrorCallback(huart);
#else
        /*Call legacy weak error callback*/
        HAL_UART_ErrorCallback(huart);
 8004486:	6878      	ldr	r0, [r7, #4]
 8004488:	f000 f845 	bl	8004516 <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */

        huart->ErrorCode = HAL_UART_ERROR_NONE;
 800448c:	687b      	ldr	r3, [r7, #4]
 800448e:	2200      	movs	r2, #0
 8004490:	63da      	str	r2, [r3, #60]	; 0x3c
      }
    }
    return;
 8004492:	e01e      	b.n	80044d2 <HAL_UART_IRQHandler+0x1ea>
        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
 8004494:	bf00      	nop
    return;
 8004496:	e01c      	b.n	80044d2 <HAL_UART_IRQHandler+0x1ea>
  } /* End if some error occurs */

  /* UART in mode Transmitter ------------------------------------------------*/
  if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
 8004498:	69fb      	ldr	r3, [r7, #28]
 800449a:	f003 0380 	and.w	r3, r3, #128	; 0x80
 800449e:	2b00      	cmp	r3, #0
 80044a0:	d008      	beq.n	80044b4 <HAL_UART_IRQHandler+0x1cc>
 80044a2:	69bb      	ldr	r3, [r7, #24]
 80044a4:	f003 0380 	and.w	r3, r3, #128	; 0x80
 80044a8:	2b00      	cmp	r3, #0
 80044aa:	d003      	beq.n	80044b4 <HAL_UART_IRQHandler+0x1cc>
  {
    UART_Transmit_IT(huart);
 80044ac:	6878      	ldr	r0, [r7, #4]
 80044ae:	f000 f98e 	bl	80047ce <UART_Transmit_IT>
    return;
 80044b2:	e00f      	b.n	80044d4 <HAL_UART_IRQHandler+0x1ec>
  }

  /* UART in mode Transmitter end --------------------------------------------*/
  if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
 80044b4:	69fb      	ldr	r3, [r7, #28]
 80044b6:	f003 0340 	and.w	r3, r3, #64	; 0x40
 80044ba:	2b00      	cmp	r3, #0
 80044bc:	d00a      	beq.n	80044d4 <HAL_UART_IRQHandler+0x1ec>
 80044be:	69bb      	ldr	r3, [r7, #24]
 80044c0:	f003 0340 	and.w	r3, r3, #64	; 0x40
 80044c4:	2b00      	cmp	r3, #0
 80044c6:	d005      	beq.n	80044d4 <HAL_UART_IRQHandler+0x1ec>
  {
    UART_EndTransmit_IT(huart);
 80044c8:	6878      	ldr	r0, [r7, #4]
 80044ca:	f000 f9d5 	bl	8004878 <UART_EndTransmit_IT>
    return;
 80044ce:	bf00      	nop
 80044d0:	e000      	b.n	80044d4 <HAL_UART_IRQHandler+0x1ec>
    return;
 80044d2:	bf00      	nop
  }
}
 80044d4:	3720      	adds	r7, #32
 80044d6:	46bd      	mov	sp, r7
 80044d8:	bd80      	pop	{r7, pc}
 80044da:	bf00      	nop
 80044dc:	080047a7 	.word	0x080047a7

080044e0 <HAL_UART_TxCpltCallback>:
  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
  *                the configuration information for the specified UART module.
  * @retval None
  */
__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
{
 80044e0:	b480      	push	{r7}
 80044e2:	b083      	sub	sp, #12
 80044e4:	af00      	add	r7, sp, #0
 80044e6:	6078      	str	r0, [r7, #4]
  /* Prevent unused argument(s) compilation warning */
  UNUSED(huart);
  /* NOTE: This function should not be modified, when the callback is needed,
           the HAL_UART_TxCpltCallback could be implemented in the user file
   */
}
 80044e8:	bf00      	nop
 80044ea:	370c      	adds	r7, #12
 80044ec:	46bd      	mov	sp, r7
 80044ee:	bc80      	pop	{r7}
 80044f0:	4770      	bx	lr

080044f2 <HAL_UART_TxHalfCpltCallback>:
  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
  *                the configuration information for the specified UART module.
  * @retval None
  */
__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
{
 80044f2:	b480      	push	{r7}
 80044f4:	b083      	sub	sp, #12
 80044f6:	af00      	add	r7, sp, #0
 80044f8:	6078      	str	r0, [r7, #4]
  /* Prevent unused argument(s) compilation warning */
  UNUSED(huart);
  /* NOTE: This function should not be modified, when the callback is needed,
           the HAL_UART_TxHalfCpltCallback could be implemented in the user file
   */
}
 80044fa:	bf00      	nop
 80044fc:	370c      	adds	r7, #12
 80044fe:	46bd      	mov	sp, r7
 8004500:	bc80      	pop	{r7}
 8004502:	4770      	bx	lr

08004504 <HAL_UART_RxHalfCpltCallback>:
  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
  *                the configuration information for the specified UART module.
  * @retval None
  */
__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
{
 8004504:	b480      	push	{r7}
 8004506:	b083      	sub	sp, #12
 8004508:	af00      	add	r7, sp, #0
 800450a:	6078      	str	r0, [r7, #4]
  /* Prevent unused argument(s) compilation warning */
  UNUSED(huart);
  /* NOTE: This function should not be modified, when the callback is needed,
           the HAL_UART_RxHalfCpltCallback could be implemented in the user file
   */
}
 800450c:	bf00      	nop
 800450e:	370c      	adds	r7, #12
 8004510:	46bd      	mov	sp, r7
 8004512:	bc80      	pop	{r7}
 8004514:	4770      	bx	lr

08004516 <HAL_UART_ErrorCallback>:
  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
  *                the configuration information for the specified UART module.
  * @retval None
  */
__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
{
 8004516:	b480      	push	{r7}
 8004518:	b083      	sub	sp, #12
 800451a:	af00      	add	r7, sp, #0
 800451c:	6078      	str	r0, [r7, #4]
  /* Prevent unused argument(s) compilation warning */
  UNUSED(huart);
  /* NOTE: This function should not be modified, when the callback is needed,
           the HAL_UART_ErrorCallback could be implemented in the user file
   */
}
 800451e:	bf00      	nop
 8004520:	370c      	adds	r7, #12
 8004522:	46bd      	mov	sp, r7
 8004524:	bc80      	pop	{r7}
 8004526:	4770      	bx	lr

08004528 <UART_DMATransmitCplt>:
  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
  *               the configuration information for the specified DMA module.
  * @retval None
  */
static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
 8004528:	b580      	push	{r7, lr}
 800452a:	b084      	sub	sp, #16
 800452c:	af00      	add	r7, sp, #0
 800452e:	6078      	str	r0, [r7, #4]
  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 8004530:	687b      	ldr	r3, [r7, #4]
 8004532:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8004534:	60fb      	str	r3, [r7, #12]
  /* DMA Normal mode*/
  if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
 8004536:	687b      	ldr	r3, [r7, #4]
 8004538:	681b      	ldr	r3, [r3, #0]
 800453a:	681b      	ldr	r3, [r3, #0]
 800453c:	f003 0320 	and.w	r3, r3, #32
 8004540:	2b00      	cmp	r3, #0
 8004542:	d113      	bne.n	800456c <UART_DMATransmitCplt+0x44>
  {
    huart->TxXferCount = 0x00U;
 8004544:	68fb      	ldr	r3, [r7, #12]
 8004546:	2200      	movs	r2, #0
 8004548:	84da      	strh	r2, [r3, #38]	; 0x26

    /* Disable the DMA transfer for transmit request by setting the DMAT bit
       in the UART CR3 register */
    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
 800454a:	68fb      	ldr	r3, [r7, #12]
 800454c:	681b      	ldr	r3, [r3, #0]
 800454e:	695a      	ldr	r2, [r3, #20]
 8004550:	68fb      	ldr	r3, [r7, #12]
 8004552:	681b      	ldr	r3, [r3, #0]
 8004554:	f022 0280 	bic.w	r2, r2, #128	; 0x80
 8004558:	615a      	str	r2, [r3, #20]

    /* Enable the UART Transmit Complete Interrupt */
    SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
 800455a:	68fb      	ldr	r3, [r7, #12]
 800455c:	681b      	ldr	r3, [r3, #0]
 800455e:	68da      	ldr	r2, [r3, #12]
 8004560:	68fb      	ldr	r3, [r7, #12]
 8004562:	681b      	ldr	r3, [r3, #0]
 8004564:	f042 0240 	orr.w	r2, r2, #64	; 0x40
 8004568:	60da      	str	r2, [r3, #12]
#else
    /*Call legacy weak Tx complete callback*/
    HAL_UART_TxCpltCallback(huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
  }
}
 800456a:	e002      	b.n	8004572 <UART_DMATransmitCplt+0x4a>
    HAL_UART_TxCpltCallback(huart);
 800456c:	68f8      	ldr	r0, [r7, #12]
 800456e:	f7ff ffb7 	bl	80044e0 <HAL_UART_TxCpltCallback>
}
 8004572:	bf00      	nop
 8004574:	3710      	adds	r7, #16
 8004576:	46bd      	mov	sp, r7
 8004578:	bd80      	pop	{r7, pc}

0800457a <UART_DMATxHalfCplt>:
  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
  *               the configuration information for the specified DMA module.
  * @retval None
  */
static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
{
 800457a:	b580      	push	{r7, lr}
 800457c:	b084      	sub	sp, #16
 800457e:	af00      	add	r7, sp, #0
 8004580:	6078      	str	r0, [r7, #4]
  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 8004582:	687b      	ldr	r3, [r7, #4]
 8004584:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8004586:	60fb      	str	r3, [r7, #12]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
  /*Call registered Tx complete callback*/
  huart->TxHalfCpltCallback(huart);
#else
  /*Call legacy weak Tx complete callback*/
  HAL_UART_TxHalfCpltCallback(huart);
 8004588:	68f8      	ldr	r0, [r7, #12]
 800458a:	f7ff ffb2 	bl	80044f2 <HAL_UART_TxHalfCpltCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
 800458e:	bf00      	nop
 8004590:	3710      	adds	r7, #16
 8004592:	46bd      	mov	sp, r7
 8004594:	bd80      	pop	{r7, pc}

08004596 <UART_DMAReceiveCplt>:
  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
  *               the configuration information for the specified DMA module.
  * @retval None
  */
static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
 8004596:	b580      	push	{r7, lr}
 8004598:	b084      	sub	sp, #16
 800459a:	af00      	add	r7, sp, #0
 800459c:	6078      	str	r0, [r7, #4]
  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 800459e:	687b      	ldr	r3, [r7, #4]
 80045a0:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 80045a2:	60fb      	str	r3, [r7, #12]
  /* DMA Normal mode*/
  if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
 80045a4:	687b      	ldr	r3, [r7, #4]
 80045a6:	681b      	ldr	r3, [r3, #0]
 80045a8:	681b      	ldr	r3, [r3, #0]
 80045aa:	f003 0320 	and.w	r3, r3, #32
 80045ae:	2b00      	cmp	r3, #0
 80045b0:	d11e      	bne.n	80045f0 <UART_DMAReceiveCplt+0x5a>
  {
    huart->RxXferCount = 0U;
 80045b2:	68fb      	ldr	r3, [r7, #12]
 80045b4:	2200      	movs	r2, #0
 80045b6:	85da      	strh	r2, [r3, #46]	; 0x2e

    /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
    CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
 80045b8:	68fb      	ldr	r3, [r7, #12]
 80045ba:	681b      	ldr	r3, [r3, #0]
 80045bc:	68da      	ldr	r2, [r3, #12]
 80045be:	68fb      	ldr	r3, [r7, #12]
 80045c0:	681b      	ldr	r3, [r3, #0]
 80045c2:	f422 7280 	bic.w	r2, r2, #256	; 0x100
 80045c6:	60da      	str	r2, [r3, #12]
    CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 80045c8:	68fb      	ldr	r3, [r7, #12]
 80045ca:	681b      	ldr	r3, [r3, #0]
 80045cc:	695a      	ldr	r2, [r3, #20]
 80045ce:	68fb      	ldr	r3, [r7, #12]
 80045d0:	681b      	ldr	r3, [r3, #0]
 80045d2:	f022 0201 	bic.w	r2, r2, #1
 80045d6:	615a      	str	r2, [r3, #20]

    /* Disable the DMA transfer for the receiver request by setting the DMAR bit
       in the UART CR3 register */
    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
 80045d8:	68fb      	ldr	r3, [r7, #12]
 80045da:	681b      	ldr	r3, [r3, #0]
 80045dc:	695a      	ldr	r2, [r3, #20]
 80045de:	68fb      	ldr	r3, [r7, #12]
 80045e0:	681b      	ldr	r3, [r3, #0]
 80045e2:	f022 0240 	bic.w	r2, r2, #64	; 0x40
 80045e6:	615a      	str	r2, [r3, #20]

    /* At end of Rx process, restore huart->RxState to Ready */
    huart->RxState = HAL_UART_STATE_READY;
 80045e8:	68fb      	ldr	r3, [r7, #12]
 80045ea:	2220      	movs	r2, #32
 80045ec:	f883 203a 	strb.w	r2, [r3, #58]	; 0x3a
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
  /*Call registered Rx complete callback*/
  huart->RxCpltCallback(huart);
#else
  /*Call legacy weak Rx complete callback*/
  HAL_UART_RxCpltCallback(huart);
 80045f0:	68f8      	ldr	r0, [r7, #12]
 80045f2:	f7fd f80d 	bl	8001610 <HAL_UART_RxCpltCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
 80045f6:	bf00      	nop
 80045f8:	3710      	adds	r7, #16
 80045fa:	46bd      	mov	sp, r7
 80045fc:	bd80      	pop	{r7, pc}

080045fe <UART_DMARxHalfCplt>:
  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
  *               the configuration information for the specified DMA module.
  * @retval None
  */
static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
{
 80045fe:	b580      	push	{r7, lr}
 8004600:	b084      	sub	sp, #16
 8004602:	af00      	add	r7, sp, #0
 8004604:	6078      	str	r0, [r7, #4]
  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 8004606:	687b      	ldr	r3, [r7, #4]
 8004608:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 800460a:	60fb      	str	r3, [r7, #12]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
  /*Call registered Rx Half complete callback*/
  huart->RxHalfCpltCallback(huart);
#else
  /*Call legacy weak Rx Half complete callback*/
  HAL_UART_RxHalfCpltCallback(huart);
 800460c:	68f8      	ldr	r0, [r7, #12]
 800460e:	f7ff ff79 	bl	8004504 <HAL_UART_RxHalfCpltCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
 8004612:	bf00      	nop
 8004614:	3710      	adds	r7, #16
 8004616:	46bd      	mov	sp, r7
 8004618:	bd80      	pop	{r7, pc}

0800461a <UART_DMAError>:
  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
  *               the configuration information for the specified DMA module.
  * @retval None
  */
static void UART_DMAError(DMA_HandleTypeDef *hdma)
{
 800461a:	b580      	push	{r7, lr}
 800461c:	b084      	sub	sp, #16
 800461e:	af00      	add	r7, sp, #0
 8004620:	6078      	str	r0, [r7, #4]
  uint32_t dmarequest = 0x00U;
 8004622:	2300      	movs	r3, #0
 8004624:	60fb      	str	r3, [r7, #12]
  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 8004626:	687b      	ldr	r3, [r7, #4]
 8004628:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 800462a:	60bb      	str	r3, [r7, #8]

  /* Stop UART DMA Tx request if ongoing */
  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
 800462c:	68bb      	ldr	r3, [r7, #8]
 800462e:	681b      	ldr	r3, [r3, #0]
 8004630:	695b      	ldr	r3, [r3, #20]
 8004632:	f003 0380 	and.w	r3, r3, #128	; 0x80
 8004636:	2b00      	cmp	r3, #0
 8004638:	bf14      	ite	ne
 800463a:	2301      	movne	r3, #1
 800463c:	2300      	moveq	r3, #0
 800463e:	b2db      	uxtb	r3, r3
 8004640:	60fb      	str	r3, [r7, #12]
  if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
 8004642:	68bb      	ldr	r3, [r7, #8]
 8004644:	f893 3039 	ldrb.w	r3, [r3, #57]	; 0x39
 8004648:	b2db      	uxtb	r3, r3
 800464a:	2b21      	cmp	r3, #33	; 0x21
 800464c:	d108      	bne.n	8004660 <UART_DMAError+0x46>
 800464e:	68fb      	ldr	r3, [r7, #12]
 8004650:	2b00      	cmp	r3, #0
 8004652:	d005      	beq.n	8004660 <UART_DMAError+0x46>
  {
    huart->TxXferCount = 0x00U;
 8004654:	68bb      	ldr	r3, [r7, #8]
 8004656:	2200      	movs	r2, #0
 8004658:	84da      	strh	r2, [r3, #38]	; 0x26
    UART_EndTxTransfer(huart);
 800465a:	68b8      	ldr	r0, [r7, #8]
 800465c:	f000 f871 	bl	8004742 <UART_EndTxTransfer>
  }

  /* Stop UART DMA Rx request if ongoing */
  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
 8004660:	68bb      	ldr	r3, [r7, #8]
 8004662:	681b      	ldr	r3, [r3, #0]
 8004664:	695b      	ldr	r3, [r3, #20]
 8004666:	f003 0340 	and.w	r3, r3, #64	; 0x40
 800466a:	2b00      	cmp	r3, #0
 800466c:	bf14      	ite	ne
 800466e:	2301      	movne	r3, #1
 8004670:	2300      	moveq	r3, #0
 8004672:	b2db      	uxtb	r3, r3
 8004674:	60fb      	str	r3, [r7, #12]
  if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
 8004676:	68bb      	ldr	r3, [r7, #8]
 8004678:	f893 303a 	ldrb.w	r3, [r3, #58]	; 0x3a
 800467c:	b2db      	uxtb	r3, r3
 800467e:	2b22      	cmp	r3, #34	; 0x22
 8004680:	d108      	bne.n	8004694 <UART_DMAError+0x7a>
 8004682:	68fb      	ldr	r3, [r7, #12]
 8004684:	2b00      	cmp	r3, #0
 8004686:	d005      	beq.n	8004694 <UART_DMAError+0x7a>
  {
    huart->RxXferCount = 0x00U;
 8004688:	68bb      	ldr	r3, [r7, #8]
 800468a:	2200      	movs	r2, #0
 800468c:	85da      	strh	r2, [r3, #46]	; 0x2e
    UART_EndRxTransfer(huart);
 800468e:	68b8      	ldr	r0, [r7, #8]
 8004690:	f000 f86c 	bl	800476c <UART_EndRxTransfer>
  }

  huart->ErrorCode |= HAL_UART_ERROR_DMA;
 8004694:	68bb      	ldr	r3, [r7, #8]
 8004696:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
 8004698:	f043 0210 	orr.w	r2, r3, #16
 800469c:	68bb      	ldr	r3, [r7, #8]
 800469e:	63da      	str	r2, [r3, #60]	; 0x3c
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
  /*Call registered error callback*/
  huart->ErrorCallback(huart);
#else
  /*Call legacy weak error callback*/
  HAL_UART_ErrorCallback(huart);
 80046a0:	68b8      	ldr	r0, [r7, #8]
 80046a2:	f7ff ff38 	bl	8004516 <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
 80046a6:	bf00      	nop
 80046a8:	3710      	adds	r7, #16
 80046aa:	46bd      	mov	sp, r7
 80046ac:	bd80      	pop	{r7, pc}

080046ae <UART_WaitOnFlagUntilTimeout>:
  * @param  Tickstart Tick start value
  * @param  Timeout Timeout duration
  * @retval HAL status
  */
static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
{
 80046ae:	b580      	push	{r7, lr}
 80046b0:	b084      	sub	sp, #16
 80046b2:	af00      	add	r7, sp, #0
 80046b4:	60f8      	str	r0, [r7, #12]
 80046b6:	60b9      	str	r1, [r7, #8]
 80046b8:	603b      	str	r3, [r7, #0]
 80046ba:	4613      	mov	r3, r2
 80046bc:	71fb      	strb	r3, [r7, #7]
  /* Wait until flag is set */
  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
 80046be:	e02c      	b.n	800471a <UART_WaitOnFlagUntilTimeout+0x6c>
  {
    /* Check for the Timeout */
    if (Timeout != HAL_MAX_DELAY)
 80046c0:	69bb      	ldr	r3, [r7, #24]
 80046c2:	f1b3 3fff 	cmp.w	r3, #4294967295
 80046c6:	d028      	beq.n	800471a <UART_WaitOnFlagUntilTimeout+0x6c>
    {
      if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
 80046c8:	69bb      	ldr	r3, [r7, #24]
 80046ca:	2b00      	cmp	r3, #0
 80046cc:	d007      	beq.n	80046de <UART_WaitOnFlagUntilTimeout+0x30>
 80046ce:	f7fd f8bd 	bl	800184c <HAL_GetTick>
 80046d2:	4602      	mov	r2, r0
 80046d4:	683b      	ldr	r3, [r7, #0]
 80046d6:	1ad3      	subs	r3, r2, r3
 80046d8:	69ba      	ldr	r2, [r7, #24]
 80046da:	429a      	cmp	r2, r3
 80046dc:	d21d      	bcs.n	800471a <UART_WaitOnFlagUntilTimeout+0x6c>
      {
        /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
        CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
 80046de:	68fb      	ldr	r3, [r7, #12]
 80046e0:	681b      	ldr	r3, [r3, #0]
 80046e2:	68da      	ldr	r2, [r3, #12]
 80046e4:	68fb      	ldr	r3, [r7, #12]
 80046e6:	681b      	ldr	r3, [r3, #0]
 80046e8:	f422 72d0 	bic.w	r2, r2, #416	; 0x1a0
 80046ec:	60da      	str	r2, [r3, #12]
        CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 80046ee:	68fb      	ldr	r3, [r7, #12]
 80046f0:	681b      	ldr	r3, [r3, #0]
 80046f2:	695a      	ldr	r2, [r3, #20]
 80046f4:	68fb      	ldr	r3, [r7, #12]
 80046f6:	681b      	ldr	r3, [r3, #0]
 80046f8:	f022 0201 	bic.w	r2, r2, #1
 80046fc:	615a      	str	r2, [r3, #20]

        huart->gState  = HAL_UART_STATE_READY;
 80046fe:	68fb      	ldr	r3, [r7, #12]
 8004700:	2220      	movs	r2, #32
 8004702:	f883 2039 	strb.w	r2, [r3, #57]	; 0x39
        huart->RxState = HAL_UART_STATE_READY;
 8004706:	68fb      	ldr	r3, [r7, #12]
 8004708:	2220      	movs	r2, #32
 800470a:	f883 203a 	strb.w	r2, [r3, #58]	; 0x3a

        /* Process Unlocked */
        __HAL_UNLOCK(huart);
 800470e:	68fb      	ldr	r3, [r7, #12]
 8004710:	2200      	movs	r2, #0
 8004712:	f883 2038 	strb.w	r2, [r3, #56]	; 0x38

        return HAL_TIMEOUT;
 8004716:	2303      	movs	r3, #3
 8004718:	e00f      	b.n	800473a <UART_WaitOnFlagUntilTimeout+0x8c>
  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
 800471a:	68fb      	ldr	r3, [r7, #12]
 800471c:	681b      	ldr	r3, [r3, #0]
 800471e:	681a      	ldr	r2, [r3, #0]
 8004720:	68bb      	ldr	r3, [r7, #8]
 8004722:	4013      	ands	r3, r2
 8004724:	68ba      	ldr	r2, [r7, #8]
 8004726:	429a      	cmp	r2, r3
 8004728:	bf0c      	ite	eq
 800472a:	2301      	moveq	r3, #1
 800472c:	2300      	movne	r3, #0
 800472e:	b2db      	uxtb	r3, r3
 8004730:	461a      	mov	r2, r3
 8004732:	79fb      	ldrb	r3, [r7, #7]
 8004734:	429a      	cmp	r2, r3
 8004736:	d0c3      	beq.n	80046c0 <UART_WaitOnFlagUntilTimeout+0x12>
      }
    }
  }
  return HAL_OK;
 8004738:	2300      	movs	r3, #0
}
 800473a:	4618      	mov	r0, r3
 800473c:	3710      	adds	r7, #16
 800473e:	46bd      	mov	sp, r7
 8004740:	bd80      	pop	{r7, pc}

08004742 <UART_EndTxTransfer>:
  * @brief  End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
  * @param  huart UART handle.
  * @retval None
  */
static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
{
 8004742:	b480      	push	{r7}
 8004744:	b083      	sub	sp, #12
 8004746:	af00      	add	r7, sp, #0
 8004748:	6078      	str	r0, [r7, #4]
  /* Disable TXEIE and TCIE interrupts */
  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
 800474a:	687b      	ldr	r3, [r7, #4]
 800474c:	681b      	ldr	r3, [r3, #0]
 800474e:	68da      	ldr	r2, [r3, #12]
 8004750:	687b      	ldr	r3, [r7, #4]
 8004752:	681b      	ldr	r3, [r3, #0]
 8004754:	f022 02c0 	bic.w	r2, r2, #192	; 0xc0
 8004758:	60da      	str	r2, [r3, #12]

  /* At end of Tx process, restore huart->gState to Ready */
  huart->gState = HAL_UART_STATE_READY;
 800475a:	687b      	ldr	r3, [r7, #4]
 800475c:	2220      	movs	r2, #32
 800475e:	f883 2039 	strb.w	r2, [r3, #57]	; 0x39
}
 8004762:	bf00      	nop
 8004764:	370c      	adds	r7, #12
 8004766:	46bd      	mov	sp, r7
 8004768:	bc80      	pop	{r7}
 800476a:	4770      	bx	lr

0800476c <UART_EndRxTransfer>:
  * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
  * @param  huart UART handle.
  * @retval None
  */
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
{
 800476c:	b480      	push	{r7}
 800476e:	b083      	sub	sp, #12
 8004770:	af00      	add	r7, sp, #0
 8004772:	6078      	str	r0, [r7, #4]
  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
 8004774:	687b      	ldr	r3, [r7, #4]
 8004776:	681b      	ldr	r3, [r3, #0]
 8004778:	68da      	ldr	r2, [r3, #12]
 800477a:	687b      	ldr	r3, [r7, #4]
 800477c:	681b      	ldr	r3, [r3, #0]
 800477e:	f422 7290 	bic.w	r2, r2, #288	; 0x120
 8004782:	60da      	str	r2, [r3, #12]
  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 8004784:	687b      	ldr	r3, [r7, #4]
 8004786:	681b      	ldr	r3, [r3, #0]
 8004788:	695a      	ldr	r2, [r3, #20]
 800478a:	687b      	ldr	r3, [r7, #4]
 800478c:	681b      	ldr	r3, [r3, #0]
 800478e:	f022 0201 	bic.w	r2, r2, #1
 8004792:	615a      	str	r2, [r3, #20]

  /* At end of Rx process, restore huart->RxState to Ready */
  huart->RxState = HAL_UART_STATE_READY;
 8004794:	687b      	ldr	r3, [r7, #4]
 8004796:	2220      	movs	r2, #32
 8004798:	f883 203a 	strb.w	r2, [r3, #58]	; 0x3a
}
 800479c:	bf00      	nop
 800479e:	370c      	adds	r7, #12
 80047a0:	46bd      	mov	sp, r7
 80047a2:	bc80      	pop	{r7}
 80047a4:	4770      	bx	lr

080047a6 <UART_DMAAbortOnError>:
  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
  *               the configuration information for the specified DMA module.
  * @retval None
  */
static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
 80047a6:	b580      	push	{r7, lr}
 80047a8:	b084      	sub	sp, #16
 80047aa:	af00      	add	r7, sp, #0
 80047ac:	6078      	str	r0, [r7, #4]
  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 80047ae:	687b      	ldr	r3, [r7, #4]
 80047b0:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 80047b2:	60fb      	str	r3, [r7, #12]
  huart->RxXferCount = 0x00U;
 80047b4:	68fb      	ldr	r3, [r7, #12]
 80047b6:	2200      	movs	r2, #0
 80047b8:	85da      	strh	r2, [r3, #46]	; 0x2e
  huart->TxXferCount = 0x00U;
 80047ba:	68fb      	ldr	r3, [r7, #12]
 80047bc:	2200      	movs	r2, #0
 80047be:	84da      	strh	r2, [r3, #38]	; 0x26
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
  /*Call registered error callback*/
  huart->ErrorCallback(huart);
#else
  /*Call legacy weak error callback*/
  HAL_UART_ErrorCallback(huart);
 80047c0:	68f8      	ldr	r0, [r7, #12]
 80047c2:	f7ff fea8 	bl	8004516 <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
 80047c6:	bf00      	nop
 80047c8:	3710      	adds	r7, #16
 80047ca:	46bd      	mov	sp, r7
 80047cc:	bd80      	pop	{r7, pc}

080047ce <UART_Transmit_IT>:
  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
  *                the configuration information for the specified UART module.
  * @retval HAL status
  */
static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
{
 80047ce:	b480      	push	{r7}
 80047d0:	b085      	sub	sp, #20
 80047d2:	af00      	add	r7, sp, #0
 80047d4:	6078      	str	r0, [r7, #4]
  uint16_t *tmp;

  /* Check that a Tx process is ongoing */
  if (huart->gState == HAL_UART_STATE_BUSY_TX)
 80047d6:	687b      	ldr	r3, [r7, #4]
 80047d8:	f893 3039 	ldrb.w	r3, [r3, #57]	; 0x39
 80047dc:	b2db      	uxtb	r3, r3
 80047de:	2b21      	cmp	r3, #33	; 0x21
 80047e0:	d144      	bne.n	800486c <UART_Transmit_IT+0x9e>
  {
    if (huart->Init.WordLength == UART_WORDLENGTH_9B)
 80047e2:	687b      	ldr	r3, [r7, #4]
 80047e4:	689b      	ldr	r3, [r3, #8]
 80047e6:	f5b3 5f80 	cmp.w	r3, #4096	; 0x1000
 80047ea:	d11a      	bne.n	8004822 <UART_Transmit_IT+0x54>
    {
      tmp = (uint16_t *) huart->pTxBuffPtr;
 80047ec:	687b      	ldr	r3, [r7, #4]
 80047ee:	6a1b      	ldr	r3, [r3, #32]
 80047f0:	60fb      	str	r3, [r7, #12]
      huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
 80047f2:	68fb      	ldr	r3, [r7, #12]
 80047f4:	881b      	ldrh	r3, [r3, #0]
 80047f6:	461a      	mov	r2, r3
 80047f8:	687b      	ldr	r3, [r7, #4]
 80047fa:	681b      	ldr	r3, [r3, #0]
 80047fc:	f3c2 0208 	ubfx	r2, r2, #0, #9
 8004800:	605a      	str	r2, [r3, #4]
      if (huart->Init.Parity == UART_PARITY_NONE)
 8004802:	687b      	ldr	r3, [r7, #4]
 8004804:	691b      	ldr	r3, [r3, #16]
 8004806:	2b00      	cmp	r3, #0
 8004808:	d105      	bne.n	8004816 <UART_Transmit_IT+0x48>
      {
        huart->pTxBuffPtr += 2U;
 800480a:	687b      	ldr	r3, [r7, #4]
 800480c:	6a1b      	ldr	r3, [r3, #32]
 800480e:	1c9a      	adds	r2, r3, #2
 8004810:	687b      	ldr	r3, [r7, #4]
 8004812:	621a      	str	r2, [r3, #32]
 8004814:	e00e      	b.n	8004834 <UART_Transmit_IT+0x66>
      }
      else
      {
        huart->pTxBuffPtr += 1U;
 8004816:	687b      	ldr	r3, [r7, #4]
 8004818:	6a1b      	ldr	r3, [r3, #32]
 800481a:	1c5a      	adds	r2, r3, #1
 800481c:	687b      	ldr	r3, [r7, #4]
 800481e:	621a      	str	r2, [r3, #32]
 8004820:	e008      	b.n	8004834 <UART_Transmit_IT+0x66>
      }
    }
    else
    {
      huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF);
 8004822:	687b      	ldr	r3, [r7, #4]
 8004824:	6a1b      	ldr	r3, [r3, #32]
 8004826:	1c59      	adds	r1, r3, #1
 8004828:	687a      	ldr	r2, [r7, #4]
 800482a:	6211      	str	r1, [r2, #32]
 800482c:	781a      	ldrb	r2, [r3, #0]
 800482e:	687b      	ldr	r3, [r7, #4]
 8004830:	681b      	ldr	r3, [r3, #0]
 8004832:	605a      	str	r2, [r3, #4]
    }

    if (--huart->TxXferCount == 0U)
 8004834:	687b      	ldr	r3, [r7, #4]
 8004836:	8cdb      	ldrh	r3, [r3, #38]	; 0x26
 8004838:	b29b      	uxth	r3, r3
 800483a:	3b01      	subs	r3, #1
 800483c:	b29b      	uxth	r3, r3
 800483e:	687a      	ldr	r2, [r7, #4]
 8004840:	4619      	mov	r1, r3
 8004842:	84d1      	strh	r1, [r2, #38]	; 0x26
 8004844:	2b00      	cmp	r3, #0
 8004846:	d10f      	bne.n	8004868 <UART_Transmit_IT+0x9a>
    {
      /* Disable the UART Transmit Complete Interrupt */
      __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
 8004848:	687b      	ldr	r3, [r7, #4]
 800484a:	681b      	ldr	r3, [r3, #0]
 800484c:	68da      	ldr	r2, [r3, #12]
 800484e:	687b      	ldr	r3, [r7, #4]
 8004850:	681b      	ldr	r3, [r3, #0]
 8004852:	f022 0280 	bic.w	r2, r2, #128	; 0x80
 8004856:	60da      	str	r2, [r3, #12]

      /* Enable the UART Transmit Complete Interrupt */
      __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
 8004858:	687b      	ldr	r3, [r7, #4]
 800485a:	681b      	ldr	r3, [r3, #0]
 800485c:	68da      	ldr	r2, [r3, #12]
 800485e:	687b      	ldr	r3, [r7, #4]
 8004860:	681b      	ldr	r3, [r3, #0]
 8004862:	f042 0240 	orr.w	r2, r2, #64	; 0x40
 8004866:	60da      	str	r2, [r3, #12]
    }
    return HAL_OK;
 8004868:	2300      	movs	r3, #0
 800486a:	e000      	b.n	800486e <UART_Transmit_IT+0xa0>
  }
  else
  {
    return HAL_BUSY;
 800486c:	2302      	movs	r3, #2
  }
}
 800486e:	4618      	mov	r0, r3
 8004870:	3714      	adds	r7, #20
 8004872:	46bd      	mov	sp, r7
 8004874:	bc80      	pop	{r7}
 8004876:	4770      	bx	lr

08004878 <UART_EndTransmit_IT>:
  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
  *                the configuration information for the specified UART module.
  * @retval HAL status
  */
static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
{
 8004878:	b580      	push	{r7, lr}
 800487a:	b082      	sub	sp, #8
 800487c:	af00      	add	r7, sp, #0
 800487e:	6078      	str	r0, [r7, #4]
  /* Disable the UART Transmit Complete Interrupt */
  __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
 8004880:	687b      	ldr	r3, [r7, #4]
 8004882:	681b      	ldr	r3, [r3, #0]
 8004884:	68da      	ldr	r2, [r3, #12]
 8004886:	687b      	ldr	r3, [r7, #4]
 8004888:	681b      	ldr	r3, [r3, #0]
 800488a:	f022 0240 	bic.w	r2, r2, #64	; 0x40
 800488e:	60da      	str	r2, [r3, #12]

  /* Tx process is ended, restore huart->gState to Ready */
  huart->gState = HAL_UART_STATE_READY;
 8004890:	687b      	ldr	r3, [r7, #4]
 8004892:	2220      	movs	r2, #32
 8004894:	f883 2039 	strb.w	r2, [r3, #57]	; 0x39
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
  /*Call registered Tx complete callback*/
  huart->TxCpltCallback(huart);
#else
  /*Call legacy weak Tx complete callback*/
  HAL_UART_TxCpltCallback(huart);
 8004898:	6878      	ldr	r0, [r7, #4]
 800489a:	f7ff fe21 	bl	80044e0 <HAL_UART_TxCpltCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */

  return HAL_OK;
 800489e:	2300      	movs	r3, #0
}
 80048a0:	4618      	mov	r0, r3
 80048a2:	3708      	adds	r7, #8
 80048a4:	46bd      	mov	sp, r7
 80048a6:	bd80      	pop	{r7, pc}

080048a8 <UART_Receive_IT>:
  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
  *                the configuration information for the specified UART module.
  * @retval HAL status
  */
static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
{
 80048a8:	b580      	push	{r7, lr}
 80048aa:	b084      	sub	sp, #16
 80048ac:	af00      	add	r7, sp, #0
 80048ae:	6078      	str	r0, [r7, #4]
  uint16_t *tmp;

  /* Check that a Rx process is ongoing */
  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
 80048b0:	687b      	ldr	r3, [r7, #4]
 80048b2:	f893 303a 	ldrb.w	r3, [r3, #58]	; 0x3a
 80048b6:	b2db      	uxtb	r3, r3
 80048b8:	2b22      	cmp	r3, #34	; 0x22
 80048ba:	d171      	bne.n	80049a0 <UART_Receive_IT+0xf8>
  {
    if (huart->Init.WordLength == UART_WORDLENGTH_9B)
 80048bc:	687b      	ldr	r3, [r7, #4]
 80048be:	689b      	ldr	r3, [r3, #8]
 80048c0:	f5b3 5f80 	cmp.w	r3, #4096	; 0x1000
 80048c4:	d123      	bne.n	800490e <UART_Receive_IT+0x66>
    {
      tmp = (uint16_t *) huart->pRxBuffPtr;
 80048c6:	687b      	ldr	r3, [r7, #4]
 80048c8:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 80048ca:	60fb      	str	r3, [r7, #12]
      if (huart->Init.Parity == UART_PARITY_NONE)
 80048cc:	687b      	ldr	r3, [r7, #4]
 80048ce:	691b      	ldr	r3, [r3, #16]
 80048d0:	2b00      	cmp	r3, #0
 80048d2:	d10e      	bne.n	80048f2 <UART_Receive_IT+0x4a>
      {
        *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
 80048d4:	687b      	ldr	r3, [r7, #4]
 80048d6:	681b      	ldr	r3, [r3, #0]
 80048d8:	685b      	ldr	r3, [r3, #4]
 80048da:	b29b      	uxth	r3, r3
 80048dc:	f3c3 0308 	ubfx	r3, r3, #0, #9
 80048e0:	b29a      	uxth	r2, r3
 80048e2:	68fb      	ldr	r3, [r7, #12]
 80048e4:	801a      	strh	r2, [r3, #0]
        huart->pRxBuffPtr += 2U;
 80048e6:	687b      	ldr	r3, [r7, #4]
 80048e8:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 80048ea:	1c9a      	adds	r2, r3, #2
 80048ec:	687b      	ldr	r3, [r7, #4]
 80048ee:	629a      	str	r2, [r3, #40]	; 0x28
 80048f0:	e029      	b.n	8004946 <UART_Receive_IT+0x9e>
      }
      else
      {
        *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF);
 80048f2:	687b      	ldr	r3, [r7, #4]
 80048f4:	681b      	ldr	r3, [r3, #0]
 80048f6:	685b      	ldr	r3, [r3, #4]
 80048f8:	b29b      	uxth	r3, r3
 80048fa:	b2db      	uxtb	r3, r3
 80048fc:	b29a      	uxth	r2, r3
 80048fe:	68fb      	ldr	r3, [r7, #12]
 8004900:	801a      	strh	r2, [r3, #0]
        huart->pRxBuffPtr += 1U;
 8004902:	687b      	ldr	r3, [r7, #4]
 8004904:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 8004906:	1c5a      	adds	r2, r3, #1
 8004908:	687b      	ldr	r3, [r7, #4]
 800490a:	629a      	str	r2, [r3, #40]	; 0x28
 800490c:	e01b      	b.n	8004946 <UART_Receive_IT+0x9e>
      }
    }
    else
    {
      if (huart->Init.Parity == UART_PARITY_NONE)
 800490e:	687b      	ldr	r3, [r7, #4]
 8004910:	691b      	ldr	r3, [r3, #16]
 8004912:	2b00      	cmp	r3, #0
 8004914:	d10a      	bne.n	800492c <UART_Receive_IT+0x84>
      {
        *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
 8004916:	687b      	ldr	r3, [r7, #4]
 8004918:	681b      	ldr	r3, [r3, #0]
 800491a:	6858      	ldr	r0, [r3, #4]
 800491c:	687b      	ldr	r3, [r7, #4]
 800491e:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 8004920:	1c59      	adds	r1, r3, #1
 8004922:	687a      	ldr	r2, [r7, #4]
 8004924:	6291      	str	r1, [r2, #40]	; 0x28
 8004926:	b2c2      	uxtb	r2, r0
 8004928:	701a      	strb	r2, [r3, #0]
 800492a:	e00c      	b.n	8004946 <UART_Receive_IT+0x9e>
      }
      else
      {
        *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
 800492c:	687b      	ldr	r3, [r7, #4]
 800492e:	681b      	ldr	r3, [r3, #0]
 8004930:	685b      	ldr	r3, [r3, #4]
 8004932:	b2da      	uxtb	r2, r3
 8004934:	687b      	ldr	r3, [r7, #4]
 8004936:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 8004938:	1c58      	adds	r0, r3, #1
 800493a:	6879      	ldr	r1, [r7, #4]
 800493c:	6288      	str	r0, [r1, #40]	; 0x28
 800493e:	f002 027f 	and.w	r2, r2, #127	; 0x7f
 8004942:	b2d2      	uxtb	r2, r2
 8004944:	701a      	strb	r2, [r3, #0]
      }
    }

    if (--huart->RxXferCount == 0U)
 8004946:	687b      	ldr	r3, [r7, #4]
 8004948:	8ddb      	ldrh	r3, [r3, #46]	; 0x2e
 800494a:	b29b      	uxth	r3, r3
 800494c:	3b01      	subs	r3, #1
 800494e:	b29b      	uxth	r3, r3
 8004950:	687a      	ldr	r2, [r7, #4]
 8004952:	4619      	mov	r1, r3
 8004954:	85d1      	strh	r1, [r2, #46]	; 0x2e
 8004956:	2b00      	cmp	r3, #0
 8004958:	d120      	bne.n	800499c <UART_Receive_IT+0xf4>
    {
      /* Disable the UART Data Register not empty Interrupt */
      __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
 800495a:	687b      	ldr	r3, [r7, #4]
 800495c:	681b      	ldr	r3, [r3, #0]
 800495e:	68da      	ldr	r2, [r3, #12]
 8004960:	687b      	ldr	r3, [r7, #4]
 8004962:	681b      	ldr	r3, [r3, #0]
 8004964:	f022 0220 	bic.w	r2, r2, #32
 8004968:	60da      	str	r2, [r3, #12]

      /* Disable the UART Parity Error Interrupt */
      __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
 800496a:	687b      	ldr	r3, [r7, #4]
 800496c:	681b      	ldr	r3, [r3, #0]
 800496e:	68da      	ldr	r2, [r3, #12]
 8004970:	687b      	ldr	r3, [r7, #4]
 8004972:	681b      	ldr	r3, [r3, #0]
 8004974:	f422 7280 	bic.w	r2, r2, #256	; 0x100
 8004978:	60da      	str	r2, [r3, #12]

      /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
      __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
 800497a:	687b      	ldr	r3, [r7, #4]
 800497c:	681b      	ldr	r3, [r3, #0]
 800497e:	695a      	ldr	r2, [r3, #20]
 8004980:	687b      	ldr	r3, [r7, #4]
 8004982:	681b      	ldr	r3, [r3, #0]
 8004984:	f022 0201 	bic.w	r2, r2, #1
 8004988:	615a      	str	r2, [r3, #20]

      /* Rx process is completed, restore huart->RxState to Ready */
      huart->RxState = HAL_UART_STATE_READY;
 800498a:	687b      	ldr	r3, [r7, #4]
 800498c:	2220      	movs	r2, #32
 800498e:	f883 203a 	strb.w	r2, [r3, #58]	; 0x3a
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
      /*Call registered Rx complete callback*/
      huart->RxCpltCallback(huart);
#else
      /*Call legacy weak Rx complete callback*/
      HAL_UART_RxCpltCallback(huart);
 8004992:	6878      	ldr	r0, [r7, #4]
 8004994:	f7fc fe3c 	bl	8001610 <HAL_UART_RxCpltCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */

      return HAL_OK;
 8004998:	2300      	movs	r3, #0
 800499a:	e002      	b.n	80049a2 <UART_Receive_IT+0xfa>
    }
    return HAL_OK;
 800499c:	2300      	movs	r3, #0
 800499e:	e000      	b.n	80049a2 <UART_Receive_IT+0xfa>
  }
  else
  {
    return HAL_BUSY;
 80049a0:	2302      	movs	r3, #2
  }
}
 80049a2:	4618      	mov	r0, r3
 80049a4:	3710      	adds	r7, #16
 80049a6:	46bd      	mov	sp, r7
 80049a8:	bd80      	pop	{r7, pc}
	...

080049ac <UART_SetConfig>:
  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
  *                the configuration information for the specified UART module.
  * @retval None
  */
static void UART_SetConfig(UART_HandleTypeDef *huart)
{
 80049ac:	b580      	push	{r7, lr}
 80049ae:	b084      	sub	sp, #16
 80049b0:	af00      	add	r7, sp, #0
 80049b2:	6078      	str	r0, [r7, #4]
  assert_param(IS_UART_MODE(huart->Init.Mode));

  /*-------------------------- USART CR2 Configuration -----------------------*/
  /* Configure the UART Stop Bits: Set STOP[13:12] bits
     according to huart->Init.StopBits value */
  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
 80049b4:	687b      	ldr	r3, [r7, #4]
 80049b6:	681b      	ldr	r3, [r3, #0]
 80049b8:	691b      	ldr	r3, [r3, #16]
 80049ba:	f423 5140 	bic.w	r1, r3, #12288	; 0x3000
 80049be:	687b      	ldr	r3, [r7, #4]
 80049c0:	68da      	ldr	r2, [r3, #12]
 80049c2:	687b      	ldr	r3, [r7, #4]
 80049c4:	681b      	ldr	r3, [r3, #0]
 80049c6:	430a      	orrs	r2, r1
 80049c8:	611a      	str	r2, [r3, #16]
     Set PCE and PS bits according to huart->Init.Parity value
     Set TE and RE bits according to huart->Init.Mode value
     Set OVER8 bit according to huart->Init.OverSampling value */

#if defined(USART_CR1_OVER8)
  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
 80049ca:	687b      	ldr	r3, [r7, #4]
 80049cc:	689a      	ldr	r2, [r3, #8]
 80049ce:	687b      	ldr	r3, [r7, #4]
 80049d0:	691b      	ldr	r3, [r3, #16]
 80049d2:	431a      	orrs	r2, r3
 80049d4:	687b      	ldr	r3, [r7, #4]
 80049d6:	695b      	ldr	r3, [r3, #20]
 80049d8:	431a      	orrs	r2, r3
 80049da:	687b      	ldr	r3, [r7, #4]
 80049dc:	69db      	ldr	r3, [r3, #28]
 80049de:	4313      	orrs	r3, r2
 80049e0:	60fb      	str	r3, [r7, #12]
  MODIFY_REG(huart->Instance->CR1,
 80049e2:	687b      	ldr	r3, [r7, #4]
 80049e4:	681b      	ldr	r3, [r3, #0]
 80049e6:	68db      	ldr	r3, [r3, #12]
 80049e8:	f423 4316 	bic.w	r3, r3, #38400	; 0x9600
 80049ec:	f023 030c 	bic.w	r3, r3, #12
 80049f0:	687a      	ldr	r2, [r7, #4]
 80049f2:	6812      	ldr	r2, [r2, #0]
 80049f4:	68f9      	ldr	r1, [r7, #12]
 80049f6:	430b      	orrs	r3, r1
 80049f8:	60d3      	str	r3, [r2, #12]
             tmpreg);
#endif /* USART_CR1_OVER8 */

  /*-------------------------- USART CR3 Configuration -----------------------*/
  /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
  MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
 80049fa:	687b      	ldr	r3, [r7, #4]
 80049fc:	681b      	ldr	r3, [r3, #0]
 80049fe:	695b      	ldr	r3, [r3, #20]
 8004a00:	f423 7140 	bic.w	r1, r3, #768	; 0x300
 8004a04:	687b      	ldr	r3, [r7, #4]
 8004a06:	699a      	ldr	r2, [r3, #24]
 8004a08:	687b      	ldr	r3, [r7, #4]
 8004a0a:	681b      	ldr	r3, [r3, #0]
 8004a0c:	430a      	orrs	r2, r1
 8004a0e:	615a      	str	r2, [r3, #20]

#if defined(USART_CR1_OVER8)
  /* Check the Over Sampling */
  if(huart->Init.OverSampling == UART_OVERSAMPLING_8)
 8004a10:	687b      	ldr	r3, [r7, #4]
 8004a12:	69db      	ldr	r3, [r3, #28]
 8004a14:	f5b3 4f00 	cmp.w	r3, #32768	; 0x8000
 8004a18:	f040 80a5 	bne.w	8004b66 <UART_SetConfig+0x1ba>
  {
    /*-------------------------- USART BRR Configuration ---------------------*/
    if(huart->Instance == USART1)
 8004a1c:	687b      	ldr	r3, [r7, #4]
 8004a1e:	681b      	ldr	r3, [r3, #0]
 8004a20:	4aa4      	ldr	r2, [pc, #656]	; (8004cb4 <UART_SetConfig+0x308>)
 8004a22:	4293      	cmp	r3, r2
 8004a24:	d14f      	bne.n	8004ac6 <UART_SetConfig+0x11a>
    {
      pclk = HAL_RCC_GetPCLK2Freq();
 8004a26:	f7fe fe8d 	bl	8003744 <HAL_RCC_GetPCLK2Freq>
 8004a2a:	60b8      	str	r0, [r7, #8]
      huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
 8004a2c:	68ba      	ldr	r2, [r7, #8]
 8004a2e:	4613      	mov	r3, r2
 8004a30:	009b      	lsls	r3, r3, #2
 8004a32:	4413      	add	r3, r2
 8004a34:	009a      	lsls	r2, r3, #2
 8004a36:	441a      	add	r2, r3
 8004a38:	687b      	ldr	r3, [r7, #4]
 8004a3a:	685b      	ldr	r3, [r3, #4]
 8004a3c:	005b      	lsls	r3, r3, #1
 8004a3e:	fbb2 f3f3 	udiv	r3, r2, r3
 8004a42:	4a9d      	ldr	r2, [pc, #628]	; (8004cb8 <UART_SetConfig+0x30c>)
 8004a44:	fba2 2303 	umull	r2, r3, r2, r3
 8004a48:	095b      	lsrs	r3, r3, #5
 8004a4a:	0119      	lsls	r1, r3, #4
 8004a4c:	68ba      	ldr	r2, [r7, #8]
 8004a4e:	4613      	mov	r3, r2
 8004a50:	009b      	lsls	r3, r3, #2
 8004a52:	4413      	add	r3, r2
 8004a54:	009a      	lsls	r2, r3, #2
 8004a56:	441a      	add	r2, r3
 8004a58:	687b      	ldr	r3, [r7, #4]
 8004a5a:	685b      	ldr	r3, [r3, #4]
 8004a5c:	005b      	lsls	r3, r3, #1
 8004a5e:	fbb2 f2f3 	udiv	r2, r2, r3
 8004a62:	4b95      	ldr	r3, [pc, #596]	; (8004cb8 <UART_SetConfig+0x30c>)
 8004a64:	fba3 0302 	umull	r0, r3, r3, r2
 8004a68:	095b      	lsrs	r3, r3, #5
 8004a6a:	2064      	movs	r0, #100	; 0x64
 8004a6c:	fb00 f303 	mul.w	r3, r0, r3
 8004a70:	1ad3      	subs	r3, r2, r3
 8004a72:	00db      	lsls	r3, r3, #3
 8004a74:	3332      	adds	r3, #50	; 0x32
 8004a76:	4a90      	ldr	r2, [pc, #576]	; (8004cb8 <UART_SetConfig+0x30c>)
 8004a78:	fba2 2303 	umull	r2, r3, r2, r3
 8004a7c:	095b      	lsrs	r3, r3, #5
 8004a7e:	005b      	lsls	r3, r3, #1
 8004a80:	f403 73f8 	and.w	r3, r3, #496	; 0x1f0
 8004a84:	4419      	add	r1, r3
 8004a86:	68ba      	ldr	r2, [r7, #8]
 8004a88:	4613      	mov	r3, r2
 8004a8a:	009b      	lsls	r3, r3, #2
 8004a8c:	4413      	add	r3, r2
 8004a8e:	009a      	lsls	r2, r3, #2
 8004a90:	441a      	add	r2, r3
 8004a92:	687b      	ldr	r3, [r7, #4]
 8004a94:	685b      	ldr	r3, [r3, #4]
 8004a96:	005b      	lsls	r3, r3, #1
 8004a98:	fbb2 f2f3 	udiv	r2, r2, r3
 8004a9c:	4b86      	ldr	r3, [pc, #536]	; (8004cb8 <UART_SetConfig+0x30c>)
 8004a9e:	fba3 0302 	umull	r0, r3, r3, r2
 8004aa2:	095b      	lsrs	r3, r3, #5
 8004aa4:	2064      	movs	r0, #100	; 0x64
 8004aa6:	fb00 f303 	mul.w	r3, r0, r3
 8004aaa:	1ad3      	subs	r3, r2, r3
 8004aac:	00db      	lsls	r3, r3, #3
 8004aae:	3332      	adds	r3, #50	; 0x32
 8004ab0:	4a81      	ldr	r2, [pc, #516]	; (8004cb8 <UART_SetConfig+0x30c>)
 8004ab2:	fba2 2303 	umull	r2, r3, r2, r3
 8004ab6:	095b      	lsrs	r3, r3, #5
 8004ab8:	f003 0207 	and.w	r2, r3, #7
 8004abc:	687b      	ldr	r3, [r7, #4]
 8004abe:	681b      	ldr	r3, [r3, #0]
 8004ac0:	440a      	add	r2, r1
 8004ac2:	609a      	str	r2, [r3, #8]
  {
    pclk = HAL_RCC_GetPCLK1Freq();
    huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
  }
#endif /* USART_CR1_OVER8 */
}
 8004ac4:	e0f1      	b.n	8004caa <UART_SetConfig+0x2fe>
      pclk = HAL_RCC_GetPCLK1Freq();
 8004ac6:	f7fe fe29 	bl	800371c <HAL_RCC_GetPCLK1Freq>
 8004aca:	60b8      	str	r0, [r7, #8]
      huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
 8004acc:	68ba      	ldr	r2, [r7, #8]
 8004ace:	4613      	mov	r3, r2
 8004ad0:	009b      	lsls	r3, r3, #2
 8004ad2:	4413      	add	r3, r2
 8004ad4:	009a      	lsls	r2, r3, #2
 8004ad6:	441a      	add	r2, r3
 8004ad8:	687b      	ldr	r3, [r7, #4]
 8004ada:	685b      	ldr	r3, [r3, #4]
 8004adc:	005b      	lsls	r3, r3, #1
 8004ade:	fbb2 f3f3 	udiv	r3, r2, r3
 8004ae2:	4a75      	ldr	r2, [pc, #468]	; (8004cb8 <UART_SetConfig+0x30c>)
 8004ae4:	fba2 2303 	umull	r2, r3, r2, r3
 8004ae8:	095b      	lsrs	r3, r3, #5
 8004aea:	0119      	lsls	r1, r3, #4
 8004aec:	68ba      	ldr	r2, [r7, #8]
 8004aee:	4613      	mov	r3, r2
 8004af0:	009b      	lsls	r3, r3, #2
 8004af2:	4413      	add	r3, r2
 8004af4:	009a      	lsls	r2, r3, #2
 8004af6:	441a      	add	r2, r3
 8004af8:	687b      	ldr	r3, [r7, #4]
 8004afa:	685b      	ldr	r3, [r3, #4]
 8004afc:	005b      	lsls	r3, r3, #1
 8004afe:	fbb2 f2f3 	udiv	r2, r2, r3
 8004b02:	4b6d      	ldr	r3, [pc, #436]	; (8004cb8 <UART_SetConfig+0x30c>)
 8004b04:	fba3 0302 	umull	r0, r3, r3, r2
 8004b08:	095b      	lsrs	r3, r3, #5
 8004b0a:	2064      	movs	r0, #100	; 0x64
 8004b0c:	fb00 f303 	mul.w	r3, r0, r3
 8004b10:	1ad3      	subs	r3, r2, r3
 8004b12:	00db      	lsls	r3, r3, #3
 8004b14:	3332      	adds	r3, #50	; 0x32
 8004b16:	4a68      	ldr	r2, [pc, #416]	; (8004cb8 <UART_SetConfig+0x30c>)
 8004b18:	fba2 2303 	umull	r2, r3, r2, r3
 8004b1c:	095b      	lsrs	r3, r3, #5
 8004b1e:	005b      	lsls	r3, r3, #1
 8004b20:	f403 73f8 	and.w	r3, r3, #496	; 0x1f0
 8004b24:	4419      	add	r1, r3
 8004b26:	68ba      	ldr	r2, [r7, #8]
 8004b28:	4613      	mov	r3, r2
 8004b2a:	009b      	lsls	r3, r3, #2
 8004b2c:	4413      	add	r3, r2
 8004b2e:	009a      	lsls	r2, r3, #2
 8004b30:	441a      	add	r2, r3
 8004b32:	687b      	ldr	r3, [r7, #4]
 8004b34:	685b      	ldr	r3, [r3, #4]
 8004b36:	005b      	lsls	r3, r3, #1
 8004b38:	fbb2 f2f3 	udiv	r2, r2, r3
 8004b3c:	4b5e      	ldr	r3, [pc, #376]	; (8004cb8 <UART_SetConfig+0x30c>)
 8004b3e:	fba3 0302 	umull	r0, r3, r3, r2
 8004b42:	095b      	lsrs	r3, r3, #5
 8004b44:	2064      	movs	r0, #100	; 0x64
 8004b46:	fb00 f303 	mul.w	r3, r0, r3
 8004b4a:	1ad3      	subs	r3, r2, r3
 8004b4c:	00db      	lsls	r3, r3, #3
 8004b4e:	3332      	adds	r3, #50	; 0x32
 8004b50:	4a59      	ldr	r2, [pc, #356]	; (8004cb8 <UART_SetConfig+0x30c>)
 8004b52:	fba2 2303 	umull	r2, r3, r2, r3
 8004b56:	095b      	lsrs	r3, r3, #5
 8004b58:	f003 0207 	and.w	r2, r3, #7
 8004b5c:	687b      	ldr	r3, [r7, #4]
 8004b5e:	681b      	ldr	r3, [r3, #0]
 8004b60:	440a      	add	r2, r1
 8004b62:	609a      	str	r2, [r3, #8]
}
 8004b64:	e0a1      	b.n	8004caa <UART_SetConfig+0x2fe>
    if(huart->Instance == USART1)
 8004b66:	687b      	ldr	r3, [r7, #4]
 8004b68:	681b      	ldr	r3, [r3, #0]
 8004b6a:	4a52      	ldr	r2, [pc, #328]	; (8004cb4 <UART_SetConfig+0x308>)
 8004b6c:	4293      	cmp	r3, r2
 8004b6e:	d14e      	bne.n	8004c0e <UART_SetConfig+0x262>
      pclk = HAL_RCC_GetPCLK2Freq();
 8004b70:	f7fe fde8 	bl	8003744 <HAL_RCC_GetPCLK2Freq>
 8004b74:	60b8      	str	r0, [r7, #8]
      huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
 8004b76:	68ba      	ldr	r2, [r7, #8]
 8004b78:	4613      	mov	r3, r2
 8004b7a:	009b      	lsls	r3, r3, #2
 8004b7c:	4413      	add	r3, r2
 8004b7e:	009a      	lsls	r2, r3, #2
 8004b80:	441a      	add	r2, r3
 8004b82:	687b      	ldr	r3, [r7, #4]
 8004b84:	685b      	ldr	r3, [r3, #4]
 8004b86:	009b      	lsls	r3, r3, #2
 8004b88:	fbb2 f3f3 	udiv	r3, r2, r3
 8004b8c:	4a4a      	ldr	r2, [pc, #296]	; (8004cb8 <UART_SetConfig+0x30c>)
 8004b8e:	fba2 2303 	umull	r2, r3, r2, r3
 8004b92:	095b      	lsrs	r3, r3, #5
 8004b94:	0119      	lsls	r1, r3, #4
 8004b96:	68ba      	ldr	r2, [r7, #8]
 8004b98:	4613      	mov	r3, r2
 8004b9a:	009b      	lsls	r3, r3, #2
 8004b9c:	4413      	add	r3, r2
 8004b9e:	009a      	lsls	r2, r3, #2
 8004ba0:	441a      	add	r2, r3
 8004ba2:	687b      	ldr	r3, [r7, #4]
 8004ba4:	685b      	ldr	r3, [r3, #4]
 8004ba6:	009b      	lsls	r3, r3, #2
 8004ba8:	fbb2 f2f3 	udiv	r2, r2, r3
 8004bac:	4b42      	ldr	r3, [pc, #264]	; (8004cb8 <UART_SetConfig+0x30c>)
 8004bae:	fba3 0302 	umull	r0, r3, r3, r2
 8004bb2:	095b      	lsrs	r3, r3, #5
 8004bb4:	2064      	movs	r0, #100	; 0x64
 8004bb6:	fb00 f303 	mul.w	r3, r0, r3
 8004bba:	1ad3      	subs	r3, r2, r3
 8004bbc:	011b      	lsls	r3, r3, #4
 8004bbe:	3332      	adds	r3, #50	; 0x32
 8004bc0:	4a3d      	ldr	r2, [pc, #244]	; (8004cb8 <UART_SetConfig+0x30c>)
 8004bc2:	fba2 2303 	umull	r2, r3, r2, r3
 8004bc6:	095b      	lsrs	r3, r3, #5
 8004bc8:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
 8004bcc:	4419      	add	r1, r3
 8004bce:	68ba      	ldr	r2, [r7, #8]
 8004bd0:	4613      	mov	r3, r2
 8004bd2:	009b      	lsls	r3, r3, #2
 8004bd4:	4413      	add	r3, r2
 8004bd6:	009a      	lsls	r2, r3, #2
 8004bd8:	441a      	add	r2, r3
 8004bda:	687b      	ldr	r3, [r7, #4]
 8004bdc:	685b      	ldr	r3, [r3, #4]
 8004bde:	009b      	lsls	r3, r3, #2
 8004be0:	fbb2 f2f3 	udiv	r2, r2, r3
 8004be4:	4b34      	ldr	r3, [pc, #208]	; (8004cb8 <UART_SetConfig+0x30c>)
 8004be6:	fba3 0302 	umull	r0, r3, r3, r2
 8004bea:	095b      	lsrs	r3, r3, #5
 8004bec:	2064      	movs	r0, #100	; 0x64
 8004bee:	fb00 f303 	mul.w	r3, r0, r3
 8004bf2:	1ad3      	subs	r3, r2, r3
 8004bf4:	011b      	lsls	r3, r3, #4
 8004bf6:	3332      	adds	r3, #50	; 0x32
 8004bf8:	4a2f      	ldr	r2, [pc, #188]	; (8004cb8 <UART_SetConfig+0x30c>)
 8004bfa:	fba2 2303 	umull	r2, r3, r2, r3
 8004bfe:	095b      	lsrs	r3, r3, #5
 8004c00:	f003 020f 	and.w	r2, r3, #15
 8004c04:	687b      	ldr	r3, [r7, #4]
 8004c06:	681b      	ldr	r3, [r3, #0]
 8004c08:	440a      	add	r2, r1
 8004c0a:	609a      	str	r2, [r3, #8]
}
 8004c0c:	e04d      	b.n	8004caa <UART_SetConfig+0x2fe>
      pclk = HAL_RCC_GetPCLK1Freq();
 8004c0e:	f7fe fd85 	bl	800371c <HAL_RCC_GetPCLK1Freq>
 8004c12:	60b8      	str	r0, [r7, #8]
      huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
 8004c14:	68ba      	ldr	r2, [r7, #8]
 8004c16:	4613      	mov	r3, r2
 8004c18:	009b      	lsls	r3, r3, #2
 8004c1a:	4413      	add	r3, r2
 8004c1c:	009a      	lsls	r2, r3, #2
 8004c1e:	441a      	add	r2, r3
 8004c20:	687b      	ldr	r3, [r7, #4]
 8004c22:	685b      	ldr	r3, [r3, #4]
 8004c24:	009b      	lsls	r3, r3, #2
 8004c26:	fbb2 f3f3 	udiv	r3, r2, r3
 8004c2a:	4a23      	ldr	r2, [pc, #140]	; (8004cb8 <UART_SetConfig+0x30c>)
 8004c2c:	fba2 2303 	umull	r2, r3, r2, r3
 8004c30:	095b      	lsrs	r3, r3, #5
 8004c32:	0119      	lsls	r1, r3, #4
 8004c34:	68ba      	ldr	r2, [r7, #8]
 8004c36:	4613      	mov	r3, r2
 8004c38:	009b      	lsls	r3, r3, #2
 8004c3a:	4413      	add	r3, r2
 8004c3c:	009a      	lsls	r2, r3, #2
 8004c3e:	441a      	add	r2, r3
 8004c40:	687b      	ldr	r3, [r7, #4]
 8004c42:	685b      	ldr	r3, [r3, #4]
 8004c44:	009b      	lsls	r3, r3, #2
 8004c46:	fbb2 f2f3 	udiv	r2, r2, r3
 8004c4a:	4b1b      	ldr	r3, [pc, #108]	; (8004cb8 <UART_SetConfig+0x30c>)
 8004c4c:	fba3 0302 	umull	r0, r3, r3, r2
 8004c50:	095b      	lsrs	r3, r3, #5
 8004c52:	2064      	movs	r0, #100	; 0x64
 8004c54:	fb00 f303 	mul.w	r3, r0, r3
 8004c58:	1ad3      	subs	r3, r2, r3
 8004c5a:	011b      	lsls	r3, r3, #4
 8004c5c:	3332      	adds	r3, #50	; 0x32
 8004c5e:	4a16      	ldr	r2, [pc, #88]	; (8004cb8 <UART_SetConfig+0x30c>)
 8004c60:	fba2 2303 	umull	r2, r3, r2, r3
 8004c64:	095b      	lsrs	r3, r3, #5
 8004c66:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
 8004c6a:	4419      	add	r1, r3
 8004c6c:	68ba      	ldr	r2, [r7, #8]
 8004c6e:	4613      	mov	r3, r2
 8004c70:	009b      	lsls	r3, r3, #2
 8004c72:	4413      	add	r3, r2
 8004c74:	009a      	lsls	r2, r3, #2
 8004c76:	441a      	add	r2, r3
 8004c78:	687b      	ldr	r3, [r7, #4]
 8004c7a:	685b      	ldr	r3, [r3, #4]
 8004c7c:	009b      	lsls	r3, r3, #2
 8004c7e:	fbb2 f2f3 	udiv	r2, r2, r3
 8004c82:	4b0d      	ldr	r3, [pc, #52]	; (8004cb8 <UART_SetConfig+0x30c>)
 8004c84:	fba3 0302 	umull	r0, r3, r3, r2
 8004c88:	095b      	lsrs	r3, r3, #5
 8004c8a:	2064      	movs	r0, #100	; 0x64
 8004c8c:	fb00 f303 	mul.w	r3, r0, r3
 8004c90:	1ad3      	subs	r3, r2, r3
 8004c92:	011b      	lsls	r3, r3, #4
 8004c94:	3332      	adds	r3, #50	; 0x32
 8004c96:	4a08      	ldr	r2, [pc, #32]	; (8004cb8 <UART_SetConfig+0x30c>)
 8004c98:	fba2 2303 	umull	r2, r3, r2, r3
 8004c9c:	095b      	lsrs	r3, r3, #5
 8004c9e:	f003 020f 	and.w	r2, r3, #15
 8004ca2:	687b      	ldr	r3, [r7, #4]
 8004ca4:	681b      	ldr	r3, [r3, #0]
 8004ca6:	440a      	add	r2, r1
 8004ca8:	609a      	str	r2, [r3, #8]
}
 8004caa:	bf00      	nop
 8004cac:	3710      	adds	r7, #16
 8004cae:	46bd      	mov	sp, r7
 8004cb0:	bd80      	pop	{r7, pc}
 8004cb2:	bf00      	nop
 8004cb4:	40013800 	.word	0x40013800
 8004cb8:	51eb851f 	.word	0x51eb851f

08004cbc <_write>:
/* USER CODE END PFP */

/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
int _write (int file, uint8_t *ptr, uint16_t len)
{
 8004cbc:	b580      	push	{r7, lr}
 8004cbe:	b084      	sub	sp, #16
 8004cc0:	af00      	add	r7, sp, #0
 8004cc2:	60f8      	str	r0, [r7, #12]
 8004cc4:	60b9      	str	r1, [r7, #8]
 8004cc6:	4613      	mov	r3, r2
 8004cc8:	80fb      	strh	r3, [r7, #6]
#if 0 // PYJ.2020.06.03_BEGIN --
    HAL_UART_Transmit(&hTest, ptr, len,10);
#else
    HAL_UART_Transmit(&hTerminal, ptr, len,10);
 8004cca:	88fa      	ldrh	r2, [r7, #6]
 8004ccc:	230a      	movs	r3, #10
 8004cce:	68b9      	ldr	r1, [r7, #8]
 8004cd0:	4803      	ldr	r0, [pc, #12]	; (8004ce0 <_write+0x24>)
 8004cd2:	f7ff f930 	bl	8003f36 <HAL_UART_Transmit>
#endif // PYJ.2020.06.03_END --

    return len;
 8004cd6:	88fb      	ldrh	r3, [r7, #6]
}
 8004cd8:	4618      	mov	r0, r3
 8004cda:	3710      	adds	r7, #16
 8004cdc:	46bd      	mov	sp, r7
 8004cde:	bd80      	pop	{r7, pc}
 8004ce0:	200006a4 	.word	0x200006a4

08004ce4 <main>:
  * @brief  The application entry point.
  * @retval int
  */
uint8_t datatest[50] = {0,};
int main(void)
{
 8004ce4:	b580      	push	{r7, lr}
 8004ce6:	af00      	add	r7, sp, #0
  /* USER CODE END 1 */

  /* MCU Configuration--------------------------------------------------------*/

  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
  HAL_Init();
 8004ce8:	f7fc fd90 	bl	800180c <HAL_Init>
  /* USER CODE BEGIN Init */

  /* USER CODE END Init */

  /* Configure the system clock */
  SystemClock_Config();
 8004cec:	f000 f86c 	bl	8004dc8 <SystemClock_Config>
  /* USER CODE BEGIN SysInit */

  /* USER CODE END SysInit */

  /* Initialize all configured peripherals */
  MX_GPIO_Init();
 8004cf0:	f000 fa06 	bl	8005100 <MX_GPIO_Init>
  MX_DMA_Init();
 8004cf4:	f000 f9ee 	bl	80050d4 <MX_DMA_Init>
  MX_ADC1_Init();
 8004cf8:	f000 f906 	bl	8004f08 <MX_ADC1_Init>
  MX_TIM6_Init();
 8004cfc:	f000 f960 	bl	8004fc0 <MX_TIM6_Init>
  MX_USART1_UART_Init();
 8004d00:	f000 f994 	bl	800502c <MX_USART1_UART_Init>
  MX_USART3_UART_Init();
 8004d04:	f000 f9bc 	bl	8005080 <MX_USART3_UART_Init>

  /* Initialize interrupts */
  MX_NVIC_Init();
 8004d08:	f000 f8b2 	bl	8004e70 <MX_NVIC_Init>
  /* USER CODE BEGIN 2 */
  HAL_TIM_Base_Start_IT(&htim6);
 8004d0c:	4824      	ldr	r0, [pc, #144]	; (8004da0 <main+0xbc>)
 8004d0e:	f7fe fea0 	bl	8003a52 <HAL_TIM_Base_Start_IT>

  setbuf(stdout, NULL);
 8004d12:	4b24      	ldr	r3, [pc, #144]	; (8004da4 <main+0xc0>)
 8004d14:	681b      	ldr	r3, [r3, #0]
 8004d16:	689b      	ldr	r3, [r3, #8]
 8004d18:	2100      	movs	r1, #0
 8004d1a:	4618      	mov	r0, r3
 8004d1c:	f001 fb4a 	bl	80063b4 <setbuf>
  InitUartQueue(&MainQueue);
 8004d20:	4821      	ldr	r0, [pc, #132]	; (8004da8 <main+0xc4>)
 8004d22:	f7fc fc4d 	bl	80015c0 <InitUartQueue>
  ADC_Initialize();
 8004d26:	f7fc fa8d 	bl	8001244 <ADC_Initialize>
#if 1 // PYJ.2020.05.06_BEGIN --
    printf("****************************************\r\n");
 8004d2a:	4820      	ldr	r0, [pc, #128]	; (8004dac <main+0xc8>)
 8004d2c:	f001 fb3a 	bl	80063a4 <puts>
    printf("NESSLAB Project\r\n");
 8004d30:	481f      	ldr	r0, [pc, #124]	; (8004db0 <main+0xcc>)
 8004d32:	f001 fb37 	bl	80063a4 <puts>
    printf("Build at %s %s\r\n", __DATE__, __TIME__);
 8004d36:	4a1f      	ldr	r2, [pc, #124]	; (8004db4 <main+0xd0>)
 8004d38:	491f      	ldr	r1, [pc, #124]	; (8004db8 <main+0xd4>)
 8004d3a:	4820      	ldr	r0, [pc, #128]	; (8004dbc <main+0xd8>)
 8004d3c:	f001 fabe 	bl	80062bc <iprintf>
    printf("Copyright (c) 2020. BLUECELL\r\n");
 8004d40:	481f      	ldr	r0, [pc, #124]	; (8004dc0 <main+0xdc>)
 8004d42:	f001 fb2f 	bl	80063a4 <puts>
    printf("****************************************\r\n");
 8004d46:	4819      	ldr	r0, [pc, #100]	; (8004dac <main+0xc8>)
 8004d48:	f001 fb2c 	bl	80063a4 <puts>
#endif // PYJ.2020.05.06_END --  
  /* USER CODE END 2 */

  /* Infinite loop */
  /* USER CODE BEGIN WHILE */
  datatest[2] = 101;
 8004d4c:	4b1d      	ldr	r3, [pc, #116]	; (8004dc4 <main+0xe0>)
 8004d4e:	2265      	movs	r2, #101	; 0x65
 8004d50:	709a      	strb	r2, [r3, #2]


    datatest[10] = 1;
 8004d52:	4b1c      	ldr	r3, [pc, #112]	; (8004dc4 <main+0xe0>)
 8004d54:	2201      	movs	r2, #1
 8004d56:	729a      	strb	r2, [r3, #10]
    datatest[11] = 0;
 8004d58:	4b1a      	ldr	r3, [pc, #104]	; (8004dc4 <main+0xe0>)
 8004d5a:	2200      	movs	r2, #0
 8004d5c:	72da      	strb	r2, [r3, #11]
    datatest[12] = 1;
 8004d5e:	4b19      	ldr	r3, [pc, #100]	; (8004dc4 <main+0xe0>)
 8004d60:	2201      	movs	r2, #1
 8004d62:	731a      	strb	r2, [r3, #12]
    datatest[13] = 0;
 8004d64:	4b17      	ldr	r3, [pc, #92]	; (8004dc4 <main+0xe0>)
 8004d66:	2200      	movs	r2, #0
 8004d68:	735a      	strb	r2, [r3, #13]
    datatest[14] = 1;
 8004d6a:	4b16      	ldr	r3, [pc, #88]	; (8004dc4 <main+0xe0>)
 8004d6c:	2201      	movs	r2, #1
 8004d6e:	739a      	strb	r2, [r3, #14]
    datatest[15] = 0;
 8004d70:	4b14      	ldr	r3, [pc, #80]	; (8004dc4 <main+0xe0>)
 8004d72:	2200      	movs	r2, #0
 8004d74:	73da      	strb	r2, [r3, #15]
    datatest[16] = 1;
 8004d76:	4b13      	ldr	r3, [pc, #76]	; (8004dc4 <main+0xe0>)
 8004d78:	2201      	movs	r2, #1
 8004d7a:	741a      	strb	r2, [r3, #16]
    datatest[17] = 0;
 8004d7c:	4b11      	ldr	r3, [pc, #68]	; (8004dc4 <main+0xe0>)
 8004d7e:	2200      	movs	r2, #0
 8004d80:	745a      	strb	r2, [r3, #17]
  {
#if 0 // PYJ.2020.08.31_BEGIN -- 
    Boot_LED_Toggle(); /*LED Check*/
    Uart_Check();      /*Usart Rx*/
#else
    NessLab_Operate(datatest);
 8004d82:	4810      	ldr	r0, [pc, #64]	; (8004dc4 <main+0xe0>)
 8004d84:	f7fc f8a0 	bl	8000ec8 <NessLab_Operate>
    datatest[4]++;
 8004d88:	4b0e      	ldr	r3, [pc, #56]	; (8004dc4 <main+0xe0>)
 8004d8a:	791b      	ldrb	r3, [r3, #4]
 8004d8c:	3301      	adds	r3, #1
 8004d8e:	b2da      	uxtb	r2, r3
 8004d90:	4b0c      	ldr	r3, [pc, #48]	; (8004dc4 <main+0xe0>)
 8004d92:	711a      	strb	r2, [r3, #4]

    HAL_Delay(3000);
 8004d94:	f640 30b8 	movw	r0, #3000	; 0xbb8
 8004d98:	f7fc fd62 	bl	8001860 <HAL_Delay>
  {
 8004d9c:	e7f1      	b.n	8004d82 <main+0x9e>
 8004d9e:	bf00      	nop
 8004da0:	20000864 	.word	0x20000864
 8004da4:	2000000c 	.word	0x2000000c
 8004da8:	2000049c 	.word	0x2000049c
 8004dac:	08008554 	.word	0x08008554
 8004db0:	08008580 	.word	0x08008580
 8004db4:	08008594 	.word	0x08008594
 8004db8:	080085a0 	.word	0x080085a0
 8004dbc:	080085ac 	.word	0x080085ac
 8004dc0:	080085c0 	.word	0x080085c0
 8004dc4:	200003bc 	.word	0x200003bc

08004dc8 <SystemClock_Config>:
/**
  * @brief System Clock Configuration
  * @retval None
  */
void SystemClock_Config(void)
{
 8004dc8:	b580      	push	{r7, lr}
 8004dca:	b092      	sub	sp, #72	; 0x48
 8004dcc:	af00      	add	r7, sp, #0
  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
 8004dce:	f107 0320 	add.w	r3, r7, #32
 8004dd2:	2228      	movs	r2, #40	; 0x28
 8004dd4:	2100      	movs	r1, #0
 8004dd6:	4618      	mov	r0, r3
 8004dd8:	f000 fe18 	bl	8005a0c <memset>
  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 8004ddc:	f107 030c 	add.w	r3, r7, #12
 8004de0:	2200      	movs	r2, #0
 8004de2:	601a      	str	r2, [r3, #0]
 8004de4:	605a      	str	r2, [r3, #4]
 8004de6:	609a      	str	r2, [r3, #8]
 8004de8:	60da      	str	r2, [r3, #12]
 8004dea:	611a      	str	r2, [r3, #16]
  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 8004dec:	463b      	mov	r3, r7
 8004dee:	2200      	movs	r2, #0
 8004df0:	601a      	str	r2, [r3, #0]
 8004df2:	605a      	str	r2, [r3, #4]
 8004df4:	609a      	str	r2, [r3, #8]

  /** Initializes the CPU, AHB and APB busses clocks 
  */
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
 8004df6:	2302      	movs	r3, #2
 8004df8:	623b      	str	r3, [r7, #32]
  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
 8004dfa:	2301      	movs	r3, #1
 8004dfc:	633b      	str	r3, [r7, #48]	; 0x30
  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
 8004dfe:	2310      	movs	r3, #16
 8004e00:	637b      	str	r3, [r7, #52]	; 0x34
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
 8004e02:	2302      	movs	r3, #2
 8004e04:	63fb      	str	r3, [r7, #60]	; 0x3c
  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2;
 8004e06:	2300      	movs	r3, #0
 8004e08:	643b      	str	r3, [r7, #64]	; 0x40
  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6;
 8004e0a:	f44f 1380 	mov.w	r3, #1048576	; 0x100000
 8004e0e:	647b      	str	r3, [r7, #68]	; 0x44
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 8004e10:	f107 0320 	add.w	r3, r7, #32
 8004e14:	4618      	mov	r0, r3
 8004e16:	f7fe f8db 	bl	8002fd0 <HAL_RCC_OscConfig>
 8004e1a:	4603      	mov	r3, r0
 8004e1c:	2b00      	cmp	r3, #0
 8004e1e:	d001      	beq.n	8004e24 <SystemClock_Config+0x5c>
  {
    Error_Handler();
 8004e20:	f000 fa26 	bl	8005270 <Error_Handler>
  }
  /** Initializes the CPU, AHB and APB busses clocks 
  */
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
 8004e24:	230f      	movs	r3, #15
 8004e26:	60fb      	str	r3, [r7, #12]
                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
 8004e28:	2302      	movs	r3, #2
 8004e2a:	613b      	str	r3, [r7, #16]
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
 8004e2c:	2300      	movs	r3, #0
 8004e2e:	617b      	str	r3, [r7, #20]
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
 8004e30:	2300      	movs	r3, #0
 8004e32:	61bb      	str	r3, [r7, #24]
  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
 8004e34:	2300      	movs	r3, #0
 8004e36:	61fb      	str	r3, [r7, #28]

  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
 8004e38:	f107 030c 	add.w	r3, r7, #12
 8004e3c:	2100      	movs	r1, #0
 8004e3e:	4618      	mov	r0, r3
 8004e40:	f7fe fb46 	bl	80034d0 <HAL_RCC_ClockConfig>
 8004e44:	4603      	mov	r3, r0
 8004e46:	2b00      	cmp	r3, #0
 8004e48:	d001      	beq.n	8004e4e <SystemClock_Config+0x86>
  {
    Error_Handler();
 8004e4a:	f000 fa11 	bl	8005270 <Error_Handler>
  }
  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
 8004e4e:	2302      	movs	r3, #2
 8004e50:	603b      	str	r3, [r7, #0]
  PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV2;
 8004e52:	2300      	movs	r3, #0
 8004e54:	60bb      	str	r3, [r7, #8]
  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
 8004e56:	463b      	mov	r3, r7
 8004e58:	4618      	mov	r0, r3
 8004e5a:	f7fe fcd1 	bl	8003800 <HAL_RCCEx_PeriphCLKConfig>
 8004e5e:	4603      	mov	r3, r0
 8004e60:	2b00      	cmp	r3, #0
 8004e62:	d001      	beq.n	8004e68 <SystemClock_Config+0xa0>
  {
    Error_Handler();
 8004e64:	f000 fa04 	bl	8005270 <Error_Handler>
  }
}
 8004e68:	bf00      	nop
 8004e6a:	3748      	adds	r7, #72	; 0x48
 8004e6c:	46bd      	mov	sp, r7
 8004e6e:	bd80      	pop	{r7, pc}

08004e70 <MX_NVIC_Init>:
/**
  * @brief NVIC Configuration.
  * @retval None
  */
static void MX_NVIC_Init(void)
{
 8004e70:	b580      	push	{r7, lr}
 8004e72:	af00      	add	r7, sp, #0
  /* ADC1_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(ADC1_IRQn, 0, 0);
 8004e74:	2200      	movs	r2, #0
 8004e76:	2100      	movs	r1, #0
 8004e78:	2012      	movs	r0, #18
 8004e7a:	f7fd faa8 	bl	80023ce <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(ADC1_IRQn);
 8004e7e:	2012      	movs	r0, #18
 8004e80:	f7fd fac1 	bl	8002406 <HAL_NVIC_EnableIRQ>
  /* USART1_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
 8004e84:	2200      	movs	r2, #0
 8004e86:	2100      	movs	r1, #0
 8004e88:	2025      	movs	r0, #37	; 0x25
 8004e8a:	f7fd faa0 	bl	80023ce <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(USART1_IRQn);
 8004e8e:	2025      	movs	r0, #37	; 0x25
 8004e90:	f7fd fab9 	bl	8002406 <HAL_NVIC_EnableIRQ>
  /* USART3_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(USART3_IRQn, 0, 0);
 8004e94:	2200      	movs	r2, #0
 8004e96:	2100      	movs	r1, #0
 8004e98:	2027      	movs	r0, #39	; 0x27
 8004e9a:	f7fd fa98 	bl	80023ce <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(USART3_IRQn);
 8004e9e:	2027      	movs	r0, #39	; 0x27
 8004ea0:	f7fd fab1 	bl	8002406 <HAL_NVIC_EnableIRQ>
  /* TIM6_DAC_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 0, 0);
 8004ea4:	2200      	movs	r2, #0
 8004ea6:	2100      	movs	r1, #0
 8004ea8:	2036      	movs	r0, #54	; 0x36
 8004eaa:	f7fd fa90 	bl	80023ce <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
 8004eae:	2036      	movs	r0, #54	; 0x36
 8004eb0:	f7fd faa9 	bl	8002406 <HAL_NVIC_EnableIRQ>
  /* DMA1_Channel2_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(DMA1_Channel2_IRQn, 0, 0);
 8004eb4:	2200      	movs	r2, #0
 8004eb6:	2100      	movs	r1, #0
 8004eb8:	200c      	movs	r0, #12
 8004eba:	f7fd fa88 	bl	80023ce <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(DMA1_Channel2_IRQn);
 8004ebe:	200c      	movs	r0, #12
 8004ec0:	f7fd faa1 	bl	8002406 <HAL_NVIC_EnableIRQ>
  /* DMA1_Channel4_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(DMA1_Channel4_IRQn, 0, 0);
 8004ec4:	2200      	movs	r2, #0
 8004ec6:	2100      	movs	r1, #0
 8004ec8:	200e      	movs	r0, #14
 8004eca:	f7fd fa80 	bl	80023ce <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(DMA1_Channel4_IRQn);
 8004ece:	200e      	movs	r0, #14
 8004ed0:	f7fd fa99 	bl	8002406 <HAL_NVIC_EnableIRQ>
  /* DMA1_Channel3_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(DMA1_Channel3_IRQn, 0, 0);
 8004ed4:	2200      	movs	r2, #0
 8004ed6:	2100      	movs	r1, #0
 8004ed8:	200d      	movs	r0, #13
 8004eda:	f7fd fa78 	bl	80023ce <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(DMA1_Channel3_IRQn);
 8004ede:	200d      	movs	r0, #13
 8004ee0:	f7fd fa91 	bl	8002406 <HAL_NVIC_EnableIRQ>
  /* DMA1_Channel1_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
 8004ee4:	2200      	movs	r2, #0
 8004ee6:	2100      	movs	r1, #0
 8004ee8:	200b      	movs	r0, #11
 8004eea:	f7fd fa70 	bl	80023ce <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
 8004eee:	200b      	movs	r0, #11
 8004ef0:	f7fd fa89 	bl	8002406 <HAL_NVIC_EnableIRQ>
  /* DMA1_Channel5_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(DMA1_Channel5_IRQn, 0, 0);
 8004ef4:	2200      	movs	r2, #0
 8004ef6:	2100      	movs	r1, #0
 8004ef8:	200f      	movs	r0, #15
 8004efa:	f7fd fa68 	bl	80023ce <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(DMA1_Channel5_IRQn);
 8004efe:	200f      	movs	r0, #15
 8004f00:	f7fd fa81 	bl	8002406 <HAL_NVIC_EnableIRQ>
}
 8004f04:	bf00      	nop
 8004f06:	bd80      	pop	{r7, pc}

08004f08 <MX_ADC1_Init>:
  * @brief ADC1 Initialization Function
  * @param None
  * @retval None
  */
static void MX_ADC1_Init(void)
{
 8004f08:	b580      	push	{r7, lr}
 8004f0a:	b084      	sub	sp, #16
 8004f0c:	af00      	add	r7, sp, #0

  /* USER CODE BEGIN ADC1_Init 0 */

  /* USER CODE END ADC1_Init 0 */

  ADC_ChannelConfTypeDef sConfig = {0};
 8004f0e:	1d3b      	adds	r3, r7, #4
 8004f10:	2200      	movs	r2, #0
 8004f12:	601a      	str	r2, [r3, #0]
 8004f14:	605a      	str	r2, [r3, #4]
 8004f16:	609a      	str	r2, [r3, #8]
  /* USER CODE BEGIN ADC1_Init 1 */

  /* USER CODE END ADC1_Init 1 */
  /** Common config 
  */
  hadc1.Instance = ADC1;
 8004f18:	4b27      	ldr	r3, [pc, #156]	; (8004fb8 <MX_ADC1_Init+0xb0>)
 8004f1a:	4a28      	ldr	r2, [pc, #160]	; (8004fbc <MX_ADC1_Init+0xb4>)
 8004f1c:	601a      	str	r2, [r3, #0]
  hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE;
 8004f1e:	4b26      	ldr	r3, [pc, #152]	; (8004fb8 <MX_ADC1_Init+0xb0>)
 8004f20:	f44f 7280 	mov.w	r2, #256	; 0x100
 8004f24:	609a      	str	r2, [r3, #8]
  hadc1.Init.ContinuousConvMode = ENABLE;
 8004f26:	4b24      	ldr	r3, [pc, #144]	; (8004fb8 <MX_ADC1_Init+0xb0>)
 8004f28:	2201      	movs	r2, #1
 8004f2a:	731a      	strb	r2, [r3, #12]
  hadc1.Init.DiscontinuousConvMode = DISABLE;
 8004f2c:	4b22      	ldr	r3, [pc, #136]	; (8004fb8 <MX_ADC1_Init+0xb0>)
 8004f2e:	2200      	movs	r2, #0
 8004f30:	751a      	strb	r2, [r3, #20]
  hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
 8004f32:	4b21      	ldr	r3, [pc, #132]	; (8004fb8 <MX_ADC1_Init+0xb0>)
 8004f34:	f44f 2260 	mov.w	r2, #917504	; 0xe0000
 8004f38:	61da      	str	r2, [r3, #28]
  hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
 8004f3a:	4b1f      	ldr	r3, [pc, #124]	; (8004fb8 <MX_ADC1_Init+0xb0>)
 8004f3c:	2200      	movs	r2, #0
 8004f3e:	605a      	str	r2, [r3, #4]
  hadc1.Init.NbrOfConversion = 3;
 8004f40:	4b1d      	ldr	r3, [pc, #116]	; (8004fb8 <MX_ADC1_Init+0xb0>)
 8004f42:	2203      	movs	r2, #3
 8004f44:	611a      	str	r2, [r3, #16]
  if (HAL_ADC_Init(&hadc1) != HAL_OK)
 8004f46:	481c      	ldr	r0, [pc, #112]	; (8004fb8 <MX_ADC1_Init+0xb0>)
 8004f48:	f7fc fcac 	bl	80018a4 <HAL_ADC_Init>
 8004f4c:	4603      	mov	r3, r0
 8004f4e:	2b00      	cmp	r3, #0
 8004f50:	d001      	beq.n	8004f56 <MX_ADC1_Init+0x4e>
  {
    Error_Handler();
 8004f52:	f000 f98d 	bl	8005270 <Error_Handler>
  }
  /** Configure Regular Channel 
  */
  sConfig.Channel = ADC_CHANNEL_0;
 8004f56:	2300      	movs	r3, #0
 8004f58:	607b      	str	r3, [r7, #4]
  sConfig.Rank = ADC_REGULAR_RANK_1;
 8004f5a:	2301      	movs	r3, #1
 8004f5c:	60bb      	str	r3, [r7, #8]
  sConfig.SamplingTime = ADC_SAMPLETIME_239CYCLES_5;
 8004f5e:	2307      	movs	r3, #7
 8004f60:	60fb      	str	r3, [r7, #12]
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8004f62:	1d3b      	adds	r3, r7, #4
 8004f64:	4619      	mov	r1, r3
 8004f66:	4814      	ldr	r0, [pc, #80]	; (8004fb8 <MX_ADC1_Init+0xb0>)
 8004f68:	f7fc feec 	bl	8001d44 <HAL_ADC_ConfigChannel>
 8004f6c:	4603      	mov	r3, r0
 8004f6e:	2b00      	cmp	r3, #0
 8004f70:	d001      	beq.n	8004f76 <MX_ADC1_Init+0x6e>
  {
    Error_Handler();
 8004f72:	f000 f97d 	bl	8005270 <Error_Handler>
  }
  /** Configure Regular Channel 
  */
  sConfig.Channel = ADC_CHANNEL_1;
 8004f76:	2301      	movs	r3, #1
 8004f78:	607b      	str	r3, [r7, #4]
  sConfig.Rank = ADC_REGULAR_RANK_2;
 8004f7a:	2302      	movs	r3, #2
 8004f7c:	60bb      	str	r3, [r7, #8]
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8004f7e:	1d3b      	adds	r3, r7, #4
 8004f80:	4619      	mov	r1, r3
 8004f82:	480d      	ldr	r0, [pc, #52]	; (8004fb8 <MX_ADC1_Init+0xb0>)
 8004f84:	f7fc fede 	bl	8001d44 <HAL_ADC_ConfigChannel>
 8004f88:	4603      	mov	r3, r0
 8004f8a:	2b00      	cmp	r3, #0
 8004f8c:	d001      	beq.n	8004f92 <MX_ADC1_Init+0x8a>
  {
    Error_Handler();
 8004f8e:	f000 f96f 	bl	8005270 <Error_Handler>
  }
  /** Configure Regular Channel 
  */
  sConfig.Channel = ADC_CHANNEL_3;
 8004f92:	2303      	movs	r3, #3
 8004f94:	607b      	str	r3, [r7, #4]
  sConfig.Rank = ADC_REGULAR_RANK_3;
 8004f96:	2303      	movs	r3, #3
 8004f98:	60bb      	str	r3, [r7, #8]
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 8004f9a:	1d3b      	adds	r3, r7, #4
 8004f9c:	4619      	mov	r1, r3
 8004f9e:	4806      	ldr	r0, [pc, #24]	; (8004fb8 <MX_ADC1_Init+0xb0>)
 8004fa0:	f7fc fed0 	bl	8001d44 <HAL_ADC_ConfigChannel>
 8004fa4:	4603      	mov	r3, r0
 8004fa6:	2b00      	cmp	r3, #0
 8004fa8:	d001      	beq.n	8004fae <MX_ADC1_Init+0xa6>
  {
    Error_Handler();
 8004faa:	f000 f961 	bl	8005270 <Error_Handler>
  }
  /* USER CODE BEGIN ADC1_Init 2 */

  /* USER CODE END ADC1_Init 2 */

}
 8004fae:	bf00      	nop
 8004fb0:	3710      	adds	r7, #16
 8004fb2:	46bd      	mov	sp, r7
 8004fb4:	bd80      	pop	{r7, pc}
 8004fb6:	bf00      	nop
 8004fb8:	2000076c 	.word	0x2000076c
 8004fbc:	40012400 	.word	0x40012400

08004fc0 <MX_TIM6_Init>:
  * @brief TIM6 Initialization Function
  * @param None
  * @retval None
  */
static void MX_TIM6_Init(void)
{
 8004fc0:	b580      	push	{r7, lr}
 8004fc2:	b082      	sub	sp, #8
 8004fc4:	af00      	add	r7, sp, #0

  /* USER CODE BEGIN TIM6_Init 0 */

  /* USER CODE END TIM6_Init 0 */

  TIM_MasterConfigTypeDef sMasterConfig = {0};
 8004fc6:	463b      	mov	r3, r7
 8004fc8:	2200      	movs	r2, #0
 8004fca:	601a      	str	r2, [r3, #0]
 8004fcc:	605a      	str	r2, [r3, #4]

  /* USER CODE BEGIN TIM6_Init 1 */

  /* USER CODE END TIM6_Init 1 */
  htim6.Instance = TIM6;
 8004fce:	4b15      	ldr	r3, [pc, #84]	; (8005024 <MX_TIM6_Init+0x64>)
 8004fd0:	4a15      	ldr	r2, [pc, #84]	; (8005028 <MX_TIM6_Init+0x68>)
 8004fd2:	601a      	str	r2, [r3, #0]
  htim6.Init.Prescaler = 2400-1;
 8004fd4:	4b13      	ldr	r3, [pc, #76]	; (8005024 <MX_TIM6_Init+0x64>)
 8004fd6:	f640 125f 	movw	r2, #2399	; 0x95f
 8004fda:	605a      	str	r2, [r3, #4]
  htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
 8004fdc:	4b11      	ldr	r3, [pc, #68]	; (8005024 <MX_TIM6_Init+0x64>)
 8004fde:	2200      	movs	r2, #0
 8004fe0:	609a      	str	r2, [r3, #8]
  htim6.Init.Period = 10;
 8004fe2:	4b10      	ldr	r3, [pc, #64]	; (8005024 <MX_TIM6_Init+0x64>)
 8004fe4:	220a      	movs	r2, #10
 8004fe6:	60da      	str	r2, [r3, #12]
  htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
 8004fe8:	4b0e      	ldr	r3, [pc, #56]	; (8005024 <MX_TIM6_Init+0x64>)
 8004fea:	2200      	movs	r2, #0
 8004fec:	619a      	str	r2, [r3, #24]
  if (HAL_TIM_Base_Init(&htim6) != HAL_OK)
 8004fee:	480d      	ldr	r0, [pc, #52]	; (8005024 <MX_TIM6_Init+0x64>)
 8004ff0:	f7fe fd04 	bl	80039fc <HAL_TIM_Base_Init>
 8004ff4:	4603      	mov	r3, r0
 8004ff6:	2b00      	cmp	r3, #0
 8004ff8:	d001      	beq.n	8004ffe <MX_TIM6_Init+0x3e>
  {
    Error_Handler();
 8004ffa:	f000 f939 	bl	8005270 <Error_Handler>
  }
  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
 8004ffe:	2300      	movs	r3, #0
 8005000:	603b      	str	r3, [r7, #0]
  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
 8005002:	2300      	movs	r3, #0
 8005004:	607b      	str	r3, [r7, #4]
  if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK)
 8005006:	463b      	mov	r3, r7
 8005008:	4619      	mov	r1, r3
 800500a:	4806      	ldr	r0, [pc, #24]	; (8005024 <MX_TIM6_Init+0x64>)
 800500c:	f7fe fef0 	bl	8003df0 <HAL_TIMEx_MasterConfigSynchronization>
 8005010:	4603      	mov	r3, r0
 8005012:	2b00      	cmp	r3, #0
 8005014:	d001      	beq.n	800501a <MX_TIM6_Init+0x5a>
  {
    Error_Handler();
 8005016:	f000 f92b 	bl	8005270 <Error_Handler>
  }
  /* USER CODE BEGIN TIM6_Init 2 */

  /* USER CODE END TIM6_Init 2 */

}
 800501a:	bf00      	nop
 800501c:	3708      	adds	r7, #8
 800501e:	46bd      	mov	sp, r7
 8005020:	bd80      	pop	{r7, pc}
 8005022:	bf00      	nop
 8005024:	20000864 	.word	0x20000864
 8005028:	40001000 	.word	0x40001000

0800502c <MX_USART1_UART_Init>:
  * @brief USART1 Initialization Function
  * @param None
  * @retval None
  */
static void MX_USART1_UART_Init(void)
{
 800502c:	b580      	push	{r7, lr}
 800502e:	af00      	add	r7, sp, #0
  /* USER CODE END USART1_Init 0 */

  /* USER CODE BEGIN USART1_Init 1 */

  /* USER CODE END USART1_Init 1 */
  huart1.Instance = USART1;
 8005030:	4b11      	ldr	r3, [pc, #68]	; (8005078 <MX_USART1_UART_Init+0x4c>)
 8005032:	4a12      	ldr	r2, [pc, #72]	; (800507c <MX_USART1_UART_Init+0x50>)
 8005034:	601a      	str	r2, [r3, #0]
  huart1.Init.BaudRate = 115200;
 8005036:	4b10      	ldr	r3, [pc, #64]	; (8005078 <MX_USART1_UART_Init+0x4c>)
 8005038:	f44f 32e1 	mov.w	r2, #115200	; 0x1c200
 800503c:	605a      	str	r2, [r3, #4]
  huart1.Init.WordLength = UART_WORDLENGTH_8B;
 800503e:	4b0e      	ldr	r3, [pc, #56]	; (8005078 <MX_USART1_UART_Init+0x4c>)
 8005040:	2200      	movs	r2, #0
 8005042:	609a      	str	r2, [r3, #8]
  huart1.Init.StopBits = UART_STOPBITS_1;
 8005044:	4b0c      	ldr	r3, [pc, #48]	; (8005078 <MX_USART1_UART_Init+0x4c>)
 8005046:	2200      	movs	r2, #0
 8005048:	60da      	str	r2, [r3, #12]
  huart1.Init.Parity = UART_PARITY_NONE;
 800504a:	4b0b      	ldr	r3, [pc, #44]	; (8005078 <MX_USART1_UART_Init+0x4c>)
 800504c:	2200      	movs	r2, #0
 800504e:	611a      	str	r2, [r3, #16]
  huart1.Init.Mode = UART_MODE_TX_RX;
 8005050:	4b09      	ldr	r3, [pc, #36]	; (8005078 <MX_USART1_UART_Init+0x4c>)
 8005052:	220c      	movs	r2, #12
 8005054:	615a      	str	r2, [r3, #20]
  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
 8005056:	4b08      	ldr	r3, [pc, #32]	; (8005078 <MX_USART1_UART_Init+0x4c>)
 8005058:	2200      	movs	r2, #0
 800505a:	619a      	str	r2, [r3, #24]
  huart1.Init.OverSampling = UART_OVERSAMPLING_16;
 800505c:	4b06      	ldr	r3, [pc, #24]	; (8005078 <MX_USART1_UART_Init+0x4c>)
 800505e:	2200      	movs	r2, #0
 8005060:	61da      	str	r2, [r3, #28]
  if (HAL_UART_Init(&huart1) != HAL_OK)
 8005062:	4805      	ldr	r0, [pc, #20]	; (8005078 <MX_USART1_UART_Init+0x4c>)
 8005064:	f7fe ff1a 	bl	8003e9c <HAL_UART_Init>
 8005068:	4603      	mov	r3, r0
 800506a:	2b00      	cmp	r3, #0
 800506c:	d001      	beq.n	8005072 <MX_USART1_UART_Init+0x46>
  {
    Error_Handler();
 800506e:	f000 f8ff 	bl	8005270 <Error_Handler>
  }
  /* USER CODE BEGIN USART1_Init 2 */

  /* USER CODE END USART1_Init 2 */

}
 8005072:	bf00      	nop
 8005074:	bd80      	pop	{r7, pc}
 8005076:	bf00      	nop
 8005078:	200007e0 	.word	0x200007e0
 800507c:	40013800 	.word	0x40013800

08005080 <MX_USART3_UART_Init>:
  * @brief USART3 Initialization Function
  * @param None
  * @retval None
  */
static void MX_USART3_UART_Init(void)
{
 8005080:	b580      	push	{r7, lr}
 8005082:	af00      	add	r7, sp, #0
  /* USER CODE END USART3_Init 0 */

  /* USER CODE BEGIN USART3_Init 1 */

  /* USER CODE END USART3_Init 1 */
  huart3.Instance = USART3;
 8005084:	4b11      	ldr	r3, [pc, #68]	; (80050cc <MX_USART3_UART_Init+0x4c>)
 8005086:	4a12      	ldr	r2, [pc, #72]	; (80050d0 <MX_USART3_UART_Init+0x50>)
 8005088:	601a      	str	r2, [r3, #0]
  huart3.Init.BaudRate = 115200;
 800508a:	4b10      	ldr	r3, [pc, #64]	; (80050cc <MX_USART3_UART_Init+0x4c>)
 800508c:	f44f 32e1 	mov.w	r2, #115200	; 0x1c200
 8005090:	605a      	str	r2, [r3, #4]
  huart3.Init.WordLength = UART_WORDLENGTH_8B;
 8005092:	4b0e      	ldr	r3, [pc, #56]	; (80050cc <MX_USART3_UART_Init+0x4c>)
 8005094:	2200      	movs	r2, #0
 8005096:	609a      	str	r2, [r3, #8]
  huart3.Init.StopBits = UART_STOPBITS_1;
 8005098:	4b0c      	ldr	r3, [pc, #48]	; (80050cc <MX_USART3_UART_Init+0x4c>)
 800509a:	2200      	movs	r2, #0
 800509c:	60da      	str	r2, [r3, #12]
  huart3.Init.Parity = UART_PARITY_NONE;
 800509e:	4b0b      	ldr	r3, [pc, #44]	; (80050cc <MX_USART3_UART_Init+0x4c>)
 80050a0:	2200      	movs	r2, #0
 80050a2:	611a      	str	r2, [r3, #16]
  huart3.Init.Mode = UART_MODE_TX_RX;
 80050a4:	4b09      	ldr	r3, [pc, #36]	; (80050cc <MX_USART3_UART_Init+0x4c>)
 80050a6:	220c      	movs	r2, #12
 80050a8:	615a      	str	r2, [r3, #20]
  huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE;
 80050aa:	4b08      	ldr	r3, [pc, #32]	; (80050cc <MX_USART3_UART_Init+0x4c>)
 80050ac:	2200      	movs	r2, #0
 80050ae:	619a      	str	r2, [r3, #24]
  huart3.Init.OverSampling = UART_OVERSAMPLING_16;
 80050b0:	4b06      	ldr	r3, [pc, #24]	; (80050cc <MX_USART3_UART_Init+0x4c>)
 80050b2:	2200      	movs	r2, #0
 80050b4:	61da      	str	r2, [r3, #28]
  if (HAL_UART_Init(&huart3) != HAL_OK)
 80050b6:	4805      	ldr	r0, [pc, #20]	; (80050cc <MX_USART3_UART_Init+0x4c>)
 80050b8:	f7fe fef0 	bl	8003e9c <HAL_UART_Init>
 80050bc:	4603      	mov	r3, r0
 80050be:	2b00      	cmp	r3, #0
 80050c0:	d001      	beq.n	80050c6 <MX_USART3_UART_Init+0x46>
  {
    Error_Handler();
 80050c2:	f000 f8d5 	bl	8005270 <Error_Handler>
  }
  /* USER CODE BEGIN USART3_Init 2 */

  /* USER CODE END USART3_Init 2 */

}
 80050c6:	bf00      	nop
 80050c8:	bd80      	pop	{r7, pc}
 80050ca:	bf00      	nop
 80050cc:	200006a4 	.word	0x200006a4
 80050d0:	40004800 	.word	0x40004800

080050d4 <MX_DMA_Init>:

/** 
  * Enable DMA controller clock
  */
static void MX_DMA_Init(void) 
{
 80050d4:	b480      	push	{r7}
 80050d6:	b083      	sub	sp, #12
 80050d8:	af00      	add	r7, sp, #0

  /* DMA controller clock enable */
  __HAL_RCC_DMA1_CLK_ENABLE();
 80050da:	4b08      	ldr	r3, [pc, #32]	; (80050fc <MX_DMA_Init+0x28>)
 80050dc:	695b      	ldr	r3, [r3, #20]
 80050de:	4a07      	ldr	r2, [pc, #28]	; (80050fc <MX_DMA_Init+0x28>)
 80050e0:	f043 0301 	orr.w	r3, r3, #1
 80050e4:	6153      	str	r3, [r2, #20]
 80050e6:	4b05      	ldr	r3, [pc, #20]	; (80050fc <MX_DMA_Init+0x28>)
 80050e8:	695b      	ldr	r3, [r3, #20]
 80050ea:	f003 0301 	and.w	r3, r3, #1
 80050ee:	607b      	str	r3, [r7, #4]
 80050f0:	687b      	ldr	r3, [r7, #4]

}
 80050f2:	bf00      	nop
 80050f4:	370c      	adds	r7, #12
 80050f6:	46bd      	mov	sp, r7
 80050f8:	bc80      	pop	{r7}
 80050fa:	4770      	bx	lr
 80050fc:	40021000 	.word	0x40021000

08005100 <MX_GPIO_Init>:
  * @brief GPIO Initialization Function
  * @param None
  * @retval None
  */
static void MX_GPIO_Init(void)
{
 8005100:	b580      	push	{r7, lr}
 8005102:	b088      	sub	sp, #32
 8005104:	af00      	add	r7, sp, #0
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8005106:	f107 0310 	add.w	r3, r7, #16
 800510a:	2200      	movs	r2, #0
 800510c:	601a      	str	r2, [r3, #0]
 800510e:	605a      	str	r2, [r3, #4]
 8005110:	609a      	str	r2, [r3, #8]
 8005112:	60da      	str	r2, [r3, #12]

  /* GPIO Ports Clock Enable */
  __HAL_RCC_GPIOC_CLK_ENABLE();
 8005114:	4b40      	ldr	r3, [pc, #256]	; (8005218 <MX_GPIO_Init+0x118>)
 8005116:	699b      	ldr	r3, [r3, #24]
 8005118:	4a3f      	ldr	r2, [pc, #252]	; (8005218 <MX_GPIO_Init+0x118>)
 800511a:	f043 0310 	orr.w	r3, r3, #16
 800511e:	6193      	str	r3, [r2, #24]
 8005120:	4b3d      	ldr	r3, [pc, #244]	; (8005218 <MX_GPIO_Init+0x118>)
 8005122:	699b      	ldr	r3, [r3, #24]
 8005124:	f003 0310 	and.w	r3, r3, #16
 8005128:	60fb      	str	r3, [r7, #12]
 800512a:	68fb      	ldr	r3, [r7, #12]
  __HAL_RCC_GPIOA_CLK_ENABLE();
 800512c:	4b3a      	ldr	r3, [pc, #232]	; (8005218 <MX_GPIO_Init+0x118>)
 800512e:	699b      	ldr	r3, [r3, #24]
 8005130:	4a39      	ldr	r2, [pc, #228]	; (8005218 <MX_GPIO_Init+0x118>)
 8005132:	f043 0304 	orr.w	r3, r3, #4
 8005136:	6193      	str	r3, [r2, #24]
 8005138:	4b37      	ldr	r3, [pc, #220]	; (8005218 <MX_GPIO_Init+0x118>)
 800513a:	699b      	ldr	r3, [r3, #24]
 800513c:	f003 0304 	and.w	r3, r3, #4
 8005140:	60bb      	str	r3, [r7, #8]
 8005142:	68bb      	ldr	r3, [r7, #8]
  __HAL_RCC_GPIOB_CLK_ENABLE();
 8005144:	4b34      	ldr	r3, [pc, #208]	; (8005218 <MX_GPIO_Init+0x118>)
 8005146:	699b      	ldr	r3, [r3, #24]
 8005148:	4a33      	ldr	r2, [pc, #204]	; (8005218 <MX_GPIO_Init+0x118>)
 800514a:	f043 0308 	orr.w	r3, r3, #8
 800514e:	6193      	str	r3, [r2, #24]
 8005150:	4b31      	ldr	r3, [pc, #196]	; (8005218 <MX_GPIO_Init+0x118>)
 8005152:	699b      	ldr	r3, [r3, #24]
 8005154:	f003 0308 	and.w	r3, r3, #8
 8005158:	607b      	str	r3, [r7, #4]
 800515a:	687b      	ldr	r3, [r7, #4]

  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(BOOT_LED_GPIO_Port, BOOT_LED_Pin, GPIO_PIN_RESET);
 800515c:	2200      	movs	r2, #0
 800515e:	f44f 4100 	mov.w	r1, #32768	; 0x8000
 8005162:	482e      	ldr	r0, [pc, #184]	; (800521c <MX_GPIO_Init+0x11c>)
 8005164:	f7fd ff1c 	bl	8002fa0 <HAL_GPIO_WritePin>

  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(GPIOA, PAU_RESERVED0_Pin|PAU_RESERVED1_Pin|AMP_EN_Pin, GPIO_PIN_RESET);
 8005168:	2200      	movs	r2, #0
 800516a:	f44f 71e0 	mov.w	r1, #448	; 0x1c0
 800516e:	482c      	ldr	r0, [pc, #176]	; (8005220 <MX_GPIO_Init+0x120>)
 8005170:	f7fd ff16 	bl	8002fa0 <HAL_GPIO_WritePin>

  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(GPIOB, PAU_RESERVED3_Pin|PAU_RESERVED2_Pin|PAU_RESET_Pin, GPIO_PIN_RESET);
 8005174:	2200      	movs	r2, #0
 8005176:	f244 0103 	movw	r1, #16387	; 0x4003
 800517a:	482a      	ldr	r0, [pc, #168]	; (8005224 <MX_GPIO_Init+0x124>)
 800517c:	f7fd ff10 	bl	8002fa0 <HAL_GPIO_WritePin>

  /*Configure GPIO pin : BOOT_LED_Pin */
  GPIO_InitStruct.Pin = BOOT_LED_Pin;
 8005180:	f44f 4300 	mov.w	r3, #32768	; 0x8000
 8005184:	613b      	str	r3, [r7, #16]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 8005186:	2301      	movs	r3, #1
 8005188:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 800518a:	2300      	movs	r3, #0
 800518c:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 800518e:	2302      	movs	r3, #2
 8005190:	61fb      	str	r3, [r7, #28]
  HAL_GPIO_Init(BOOT_LED_GPIO_Port, &GPIO_InitStruct);
 8005192:	f107 0310 	add.w	r3, r7, #16
 8005196:	4619      	mov	r1, r3
 8005198:	4820      	ldr	r0, [pc, #128]	; (800521c <MX_GPIO_Init+0x11c>)
 800519a:	f7fd fda7 	bl	8002cec <HAL_GPIO_Init>

  /*Configure GPIO pins : DC_FAIL_ALARM_Pin OVER_INPUT_ALARM_Pin OVER_TEMP_ALARM_Pin */
  GPIO_InitStruct.Pin = DC_FAIL_ALARM_Pin|OVER_INPUT_ALARM_Pin|OVER_TEMP_ALARM_Pin;
 800519e:	f641 0304 	movw	r3, #6148	; 0x1804
 80051a2:	613b      	str	r3, [r7, #16]
  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
 80051a4:	2300      	movs	r3, #0
 80051a6:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 80051a8:	2300      	movs	r3, #0
 80051aa:	61bb      	str	r3, [r7, #24]
  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 80051ac:	f107 0310 	add.w	r3, r7, #16
 80051b0:	4619      	mov	r1, r3
 80051b2:	481b      	ldr	r0, [pc, #108]	; (8005220 <MX_GPIO_Init+0x120>)
 80051b4:	f7fd fd9a 	bl	8002cec <HAL_GPIO_Init>

  /*Configure GPIO pins : PAU_RESERVED0_Pin PAU_RESERVED1_Pin AMP_EN_Pin */
  GPIO_InitStruct.Pin = PAU_RESERVED0_Pin|PAU_RESERVED1_Pin|AMP_EN_Pin;
 80051b8:	f44f 73e0 	mov.w	r3, #448	; 0x1c0
 80051bc:	613b      	str	r3, [r7, #16]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 80051be:	2301      	movs	r3, #1
 80051c0:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 80051c2:	2300      	movs	r3, #0
 80051c4:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 80051c6:	2302      	movs	r3, #2
 80051c8:	61fb      	str	r3, [r7, #28]
  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 80051ca:	f107 0310 	add.w	r3, r7, #16
 80051ce:	4619      	mov	r1, r3
 80051d0:	4813      	ldr	r0, [pc, #76]	; (8005220 <MX_GPIO_Init+0x120>)
 80051d2:	f7fd fd8b 	bl	8002cec <HAL_GPIO_Init>

  /*Configure GPIO pins : PAU_RESERVED3_Pin PAU_RESERVED2_Pin PAU_RESET_Pin */
  GPIO_InitStruct.Pin = PAU_RESERVED3_Pin|PAU_RESERVED2_Pin|PAU_RESET_Pin;
 80051d6:	f244 0303 	movw	r3, #16387	; 0x4003
 80051da:	613b      	str	r3, [r7, #16]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 80051dc:	2301      	movs	r3, #1
 80051de:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 80051e0:	2300      	movs	r3, #0
 80051e2:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 80051e4:	2302      	movs	r3, #2
 80051e6:	61fb      	str	r3, [r7, #28]
  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 80051e8:	f107 0310 	add.w	r3, r7, #16
 80051ec:	4619      	mov	r1, r3
 80051ee:	480d      	ldr	r0, [pc, #52]	; (8005224 <MX_GPIO_Init+0x124>)
 80051f0:	f7fd fd7c 	bl	8002cec <HAL_GPIO_Init>

  /*Configure GPIO pins : OVER_POWER_ALARM_Pin VSWR_ALARM_Pin PAU_EN_Pin ALC_ALARM_Pin */
  GPIO_InitStruct.Pin = OVER_POWER_ALARM_Pin|VSWR_ALARM_Pin|PAU_EN_Pin|ALC_ALARM_Pin;
 80051f4:	f24b 0308 	movw	r3, #45064	; 0xb008
 80051f8:	613b      	str	r3, [r7, #16]
  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
 80051fa:	2300      	movs	r3, #0
 80051fc:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 80051fe:	2300      	movs	r3, #0
 8005200:	61bb      	str	r3, [r7, #24]
  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8005202:	f107 0310 	add.w	r3, r7, #16
 8005206:	4619      	mov	r1, r3
 8005208:	4806      	ldr	r0, [pc, #24]	; (8005224 <MX_GPIO_Init+0x124>)
 800520a:	f7fd fd6f 	bl	8002cec <HAL_GPIO_Init>

}
 800520e:	bf00      	nop
 8005210:	3720      	adds	r7, #32
 8005212:	46bd      	mov	sp, r7
 8005214:	bd80      	pop	{r7, pc}
 8005216:	bf00      	nop
 8005218:	40021000 	.word	0x40021000
 800521c:	40011000 	.word	0x40011000
 8005220:	40010800 	.word	0x40010800
 8005224:	40010c00 	.word	0x40010c00

08005228 <HAL_TIM_PeriodElapsedCallback>:
  * a global variable "uwTick" used as application time base.
  * @param  htim : TIM handle
  * @retval None
  */
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
 8005228:	b580      	push	{r7, lr}
 800522a:	b082      	sub	sp, #8
 800522c:	af00      	add	r7, sp, #0
 800522e:	6078      	str	r0, [r7, #4]
  /* USER CODE BEGIN Callback 0 */

  /* USER CODE END Callback 0 */
  if (htim->Instance == TIM2) {
 8005230:	687b      	ldr	r3, [r7, #4]
 8005232:	681b      	ldr	r3, [r3, #0]
 8005234:	f1b3 4f80 	cmp.w	r3, #1073741824	; 0x40000000
 8005238:	d101      	bne.n	800523e <HAL_TIM_PeriodElapsedCallback+0x16>
    HAL_IncTick();
 800523a:	f7fc faf5 	bl	8001828 <HAL_IncTick>
  }
  /* USER CODE BEGIN Callback 1 */
  if(htim->Instance == TIM6){
 800523e:	687b      	ldr	r3, [r7, #4]
 8005240:	681b      	ldr	r3, [r3, #0]
 8005242:	4a08      	ldr	r2, [pc, #32]	; (8005264 <HAL_TIM_PeriodElapsedCallback+0x3c>)
 8005244:	4293      	cmp	r3, r2
 8005246:	d109      	bne.n	800525c <HAL_TIM_PeriodElapsedCallback+0x34>
      UartRxTimerCnt++;
 8005248:	4b07      	ldr	r3, [pc, #28]	; (8005268 <HAL_TIM_PeriodElapsedCallback+0x40>)
 800524a:	681b      	ldr	r3, [r3, #0]
 800524c:	3301      	adds	r3, #1
 800524e:	4a06      	ldr	r2, [pc, #24]	; (8005268 <HAL_TIM_PeriodElapsedCallback+0x40>)
 8005250:	6013      	str	r3, [r2, #0]
      LED_TimerCnt++;
 8005252:	4b06      	ldr	r3, [pc, #24]	; (800526c <HAL_TIM_PeriodElapsedCallback+0x44>)
 8005254:	681b      	ldr	r3, [r3, #0]
 8005256:	3301      	adds	r3, #1
 8005258:	4a04      	ldr	r2, [pc, #16]	; (800526c <HAL_TIM_PeriodElapsedCallback+0x44>)
 800525a:	6013      	str	r3, [r2, #0]
  }
  /* USER CODE END Callback 1 */
}
 800525c:	bf00      	nop
 800525e:	3708      	adds	r7, #8
 8005260:	46bd      	mov	sp, r7
 8005262:	bd80      	pop	{r7, pc}
 8005264:	40001000 	.word	0x40001000
 8005268:	200003b8 	.word	0x200003b8
 800526c:	200003b0 	.word	0x200003b0

08005270 <Error_Handler>:
/**
  * @brief  This function is executed in case of error occurrence.
  * @retval None
  */
void Error_Handler(void)
{
 8005270:	b480      	push	{r7}
 8005272:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN Error_Handler_Debug */
  /* User can add his own implementation to report the HAL error return state */

  /* USER CODE END Error_Handler_Debug */
}
 8005274:	bf00      	nop
 8005276:	46bd      	mov	sp, r7
 8005278:	bc80      	pop	{r7}
 800527a:	4770      	bx	lr

0800527c <HAL_MspInit>:
/* USER CODE END 0 */
/**
  * Initializes the Global MSP.
  */
void HAL_MspInit(void)
{
 800527c:	b480      	push	{r7}
 800527e:	b085      	sub	sp, #20
 8005280:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN MspInit 0 */

  /* USER CODE END MspInit 0 */

  __HAL_RCC_AFIO_CLK_ENABLE();
 8005282:	4b15      	ldr	r3, [pc, #84]	; (80052d8 <HAL_MspInit+0x5c>)
 8005284:	699b      	ldr	r3, [r3, #24]
 8005286:	4a14      	ldr	r2, [pc, #80]	; (80052d8 <HAL_MspInit+0x5c>)
 8005288:	f043 0301 	orr.w	r3, r3, #1
 800528c:	6193      	str	r3, [r2, #24]
 800528e:	4b12      	ldr	r3, [pc, #72]	; (80052d8 <HAL_MspInit+0x5c>)
 8005290:	699b      	ldr	r3, [r3, #24]
 8005292:	f003 0301 	and.w	r3, r3, #1
 8005296:	60bb      	str	r3, [r7, #8]
 8005298:	68bb      	ldr	r3, [r7, #8]
  __HAL_RCC_PWR_CLK_ENABLE();
 800529a:	4b0f      	ldr	r3, [pc, #60]	; (80052d8 <HAL_MspInit+0x5c>)
 800529c:	69db      	ldr	r3, [r3, #28]
 800529e:	4a0e      	ldr	r2, [pc, #56]	; (80052d8 <HAL_MspInit+0x5c>)
 80052a0:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
 80052a4:	61d3      	str	r3, [r2, #28]
 80052a6:	4b0c      	ldr	r3, [pc, #48]	; (80052d8 <HAL_MspInit+0x5c>)
 80052a8:	69db      	ldr	r3, [r3, #28]
 80052aa:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 80052ae:	607b      	str	r3, [r7, #4]
 80052b0:	687b      	ldr	r3, [r7, #4]

  /* System interrupt init*/

  /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled 
  */
  __HAL_AFIO_REMAP_SWJ_NOJTAG();
 80052b2:	4b0a      	ldr	r3, [pc, #40]	; (80052dc <HAL_MspInit+0x60>)
 80052b4:	685b      	ldr	r3, [r3, #4]
 80052b6:	60fb      	str	r3, [r7, #12]
 80052b8:	68fb      	ldr	r3, [r7, #12]
 80052ba:	f023 63e0 	bic.w	r3, r3, #117440512	; 0x7000000
 80052be:	60fb      	str	r3, [r7, #12]
 80052c0:	68fb      	ldr	r3, [r7, #12]
 80052c2:	f043 7300 	orr.w	r3, r3, #33554432	; 0x2000000
 80052c6:	60fb      	str	r3, [r7, #12]
 80052c8:	4a04      	ldr	r2, [pc, #16]	; (80052dc <HAL_MspInit+0x60>)
 80052ca:	68fb      	ldr	r3, [r7, #12]
 80052cc:	6053      	str	r3, [r2, #4]

  /* USER CODE BEGIN MspInit 1 */

  /* USER CODE END MspInit 1 */
}
 80052ce:	bf00      	nop
 80052d0:	3714      	adds	r7, #20
 80052d2:	46bd      	mov	sp, r7
 80052d4:	bc80      	pop	{r7}
 80052d6:	4770      	bx	lr
 80052d8:	40021000 	.word	0x40021000
 80052dc:	40010000 	.word	0x40010000

080052e0 <HAL_ADC_MspInit>:
* This function configures the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
{
 80052e0:	b580      	push	{r7, lr}
 80052e2:	b088      	sub	sp, #32
 80052e4:	af00      	add	r7, sp, #0
 80052e6:	6078      	str	r0, [r7, #4]
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 80052e8:	f107 0310 	add.w	r3, r7, #16
 80052ec:	2200      	movs	r2, #0
 80052ee:	601a      	str	r2, [r3, #0]
 80052f0:	605a      	str	r2, [r3, #4]
 80052f2:	609a      	str	r2, [r3, #8]
 80052f4:	60da      	str	r2, [r3, #12]
  if(hadc->Instance==ADC1)
 80052f6:	687b      	ldr	r3, [r7, #4]
 80052f8:	681b      	ldr	r3, [r3, #0]
 80052fa:	4a28      	ldr	r2, [pc, #160]	; (800539c <HAL_ADC_MspInit+0xbc>)
 80052fc:	4293      	cmp	r3, r2
 80052fe:	d149      	bne.n	8005394 <HAL_ADC_MspInit+0xb4>
  {
  /* USER CODE BEGIN ADC1_MspInit 0 */

  /* USER CODE END ADC1_MspInit 0 */
    /* Peripheral clock enable */
    __HAL_RCC_ADC1_CLK_ENABLE();
 8005300:	4b27      	ldr	r3, [pc, #156]	; (80053a0 <HAL_ADC_MspInit+0xc0>)
 8005302:	699b      	ldr	r3, [r3, #24]
 8005304:	4a26      	ldr	r2, [pc, #152]	; (80053a0 <HAL_ADC_MspInit+0xc0>)
 8005306:	f443 7300 	orr.w	r3, r3, #512	; 0x200
 800530a:	6193      	str	r3, [r2, #24]
 800530c:	4b24      	ldr	r3, [pc, #144]	; (80053a0 <HAL_ADC_MspInit+0xc0>)
 800530e:	699b      	ldr	r3, [r3, #24]
 8005310:	f403 7300 	and.w	r3, r3, #512	; 0x200
 8005314:	60fb      	str	r3, [r7, #12]
 8005316:	68fb      	ldr	r3, [r7, #12]
  
    __HAL_RCC_GPIOA_CLK_ENABLE();
 8005318:	4b21      	ldr	r3, [pc, #132]	; (80053a0 <HAL_ADC_MspInit+0xc0>)
 800531a:	699b      	ldr	r3, [r3, #24]
 800531c:	4a20      	ldr	r2, [pc, #128]	; (80053a0 <HAL_ADC_MspInit+0xc0>)
 800531e:	f043 0304 	orr.w	r3, r3, #4
 8005322:	6193      	str	r3, [r2, #24]
 8005324:	4b1e      	ldr	r3, [pc, #120]	; (80053a0 <HAL_ADC_MspInit+0xc0>)
 8005326:	699b      	ldr	r3, [r3, #24]
 8005328:	f003 0304 	and.w	r3, r3, #4
 800532c:	60bb      	str	r3, [r7, #8]
 800532e:	68bb      	ldr	r3, [r7, #8]
    /**ADC1 GPIO Configuration    
    PA0-WKUP     ------> ADC1_IN0
    PA1     ------> ADC1_IN1
    PA3     ------> ADC1_IN3 
    */
    GPIO_InitStruct.Pin = DL_TX_DET_Pin|DL_RX_DET_Pin|PAU_TEMP_Pin;
 8005330:	230b      	movs	r3, #11
 8005332:	613b      	str	r3, [r7, #16]
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
 8005334:	2303      	movs	r3, #3
 8005336:	617b      	str	r3, [r7, #20]
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8005338:	f107 0310 	add.w	r3, r7, #16
 800533c:	4619      	mov	r1, r3
 800533e:	4819      	ldr	r0, [pc, #100]	; (80053a4 <HAL_ADC_MspInit+0xc4>)
 8005340:	f7fd fcd4 	bl	8002cec <HAL_GPIO_Init>

    /* ADC1 DMA Init */
    /* ADC1 Init */
    hdma_adc1.Instance = DMA1_Channel1;
 8005344:	4b18      	ldr	r3, [pc, #96]	; (80053a8 <HAL_ADC_MspInit+0xc8>)
 8005346:	4a19      	ldr	r2, [pc, #100]	; (80053ac <HAL_ADC_MspInit+0xcc>)
 8005348:	601a      	str	r2, [r3, #0]
    hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY;
 800534a:	4b17      	ldr	r3, [pc, #92]	; (80053a8 <HAL_ADC_MspInit+0xc8>)
 800534c:	2200      	movs	r2, #0
 800534e:	605a      	str	r2, [r3, #4]
    hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE;
 8005350:	4b15      	ldr	r3, [pc, #84]	; (80053a8 <HAL_ADC_MspInit+0xc8>)
 8005352:	2200      	movs	r2, #0
 8005354:	609a      	str	r2, [r3, #8]
    hdma_adc1.Init.MemInc = DMA_MINC_ENABLE;
 8005356:	4b14      	ldr	r3, [pc, #80]	; (80053a8 <HAL_ADC_MspInit+0xc8>)
 8005358:	2280      	movs	r2, #128	; 0x80
 800535a:	60da      	str	r2, [r3, #12]
    hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
 800535c:	4b12      	ldr	r3, [pc, #72]	; (80053a8 <HAL_ADC_MspInit+0xc8>)
 800535e:	f44f 7280 	mov.w	r2, #256	; 0x100
 8005362:	611a      	str	r2, [r3, #16]
    hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
 8005364:	4b10      	ldr	r3, [pc, #64]	; (80053a8 <HAL_ADC_MspInit+0xc8>)
 8005366:	f44f 6280 	mov.w	r2, #1024	; 0x400
 800536a:	615a      	str	r2, [r3, #20]
    hdma_adc1.Init.Mode = DMA_CIRCULAR;
 800536c:	4b0e      	ldr	r3, [pc, #56]	; (80053a8 <HAL_ADC_MspInit+0xc8>)
 800536e:	2220      	movs	r2, #32
 8005370:	619a      	str	r2, [r3, #24]
    hdma_adc1.Init.Priority = DMA_PRIORITY_LOW;
 8005372:	4b0d      	ldr	r3, [pc, #52]	; (80053a8 <HAL_ADC_MspInit+0xc8>)
 8005374:	2200      	movs	r2, #0
 8005376:	61da      	str	r2, [r3, #28]
    if (HAL_DMA_Init(&hdma_adc1) != HAL_OK)
 8005378:	480b      	ldr	r0, [pc, #44]	; (80053a8 <HAL_ADC_MspInit+0xc8>)
 800537a:	f7fd f853 	bl	8002424 <HAL_DMA_Init>
 800537e:	4603      	mov	r3, r0
 8005380:	2b00      	cmp	r3, #0
 8005382:	d001      	beq.n	8005388 <HAL_ADC_MspInit+0xa8>
    {
      Error_Handler();
 8005384:	f7ff ff74 	bl	8005270 <Error_Handler>
    }

    __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc1);
 8005388:	687b      	ldr	r3, [r7, #4]
 800538a:	4a07      	ldr	r2, [pc, #28]	; (80053a8 <HAL_ADC_MspInit+0xc8>)
 800538c:	621a      	str	r2, [r3, #32]
 800538e:	4a06      	ldr	r2, [pc, #24]	; (80053a8 <HAL_ADC_MspInit+0xc8>)
 8005390:	687b      	ldr	r3, [r7, #4]
 8005392:	6253      	str	r3, [r2, #36]	; 0x24
  /* USER CODE BEGIN ADC1_MspInit 1 */

  /* USER CODE END ADC1_MspInit 1 */
  }

}
 8005394:	bf00      	nop
 8005396:	3720      	adds	r7, #32
 8005398:	46bd      	mov	sp, r7
 800539a:	bd80      	pop	{r7, pc}
 800539c:	40012400 	.word	0x40012400
 80053a0:	40021000 	.word	0x40021000
 80053a4:	40010800 	.word	0x40010800
 80053a8:	20000820 	.word	0x20000820
 80053ac:	40020008 	.word	0x40020008

080053b0 <HAL_TIM_Base_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_base: TIM_Base handle pointer
* @retval None
*/
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
{
 80053b0:	b480      	push	{r7}
 80053b2:	b085      	sub	sp, #20
 80053b4:	af00      	add	r7, sp, #0
 80053b6:	6078      	str	r0, [r7, #4]
  if(htim_base->Instance==TIM6)
 80053b8:	687b      	ldr	r3, [r7, #4]
 80053ba:	681b      	ldr	r3, [r3, #0]
 80053bc:	4a09      	ldr	r2, [pc, #36]	; (80053e4 <HAL_TIM_Base_MspInit+0x34>)
 80053be:	4293      	cmp	r3, r2
 80053c0:	d10b      	bne.n	80053da <HAL_TIM_Base_MspInit+0x2a>
  {
  /* USER CODE BEGIN TIM6_MspInit 0 */

  /* USER CODE END TIM6_MspInit 0 */
    /* Peripheral clock enable */
    __HAL_RCC_TIM6_CLK_ENABLE();
 80053c2:	4b09      	ldr	r3, [pc, #36]	; (80053e8 <HAL_TIM_Base_MspInit+0x38>)
 80053c4:	69db      	ldr	r3, [r3, #28]
 80053c6:	4a08      	ldr	r2, [pc, #32]	; (80053e8 <HAL_TIM_Base_MspInit+0x38>)
 80053c8:	f043 0310 	orr.w	r3, r3, #16
 80053cc:	61d3      	str	r3, [r2, #28]
 80053ce:	4b06      	ldr	r3, [pc, #24]	; (80053e8 <HAL_TIM_Base_MspInit+0x38>)
 80053d0:	69db      	ldr	r3, [r3, #28]
 80053d2:	f003 0310 	and.w	r3, r3, #16
 80053d6:	60fb      	str	r3, [r7, #12]
 80053d8:	68fb      	ldr	r3, [r7, #12]
  /* USER CODE BEGIN TIM6_MspInit 1 */

  /* USER CODE END TIM6_MspInit 1 */
  }

}
 80053da:	bf00      	nop
 80053dc:	3714      	adds	r7, #20
 80053de:	46bd      	mov	sp, r7
 80053e0:	bc80      	pop	{r7}
 80053e2:	4770      	bx	lr
 80053e4:	40001000 	.word	0x40001000
 80053e8:	40021000 	.word	0x40021000

080053ec <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
 80053ec:	b580      	push	{r7, lr}
 80053ee:	b08a      	sub	sp, #40	; 0x28
 80053f0:	af00      	add	r7, sp, #0
 80053f2:	6078      	str	r0, [r7, #4]
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 80053f4:	f107 0318 	add.w	r3, r7, #24
 80053f8:	2200      	movs	r2, #0
 80053fa:	601a      	str	r2, [r3, #0]
 80053fc:	605a      	str	r2, [r3, #4]
 80053fe:	609a      	str	r2, [r3, #8]
 8005400:	60da      	str	r2, [r3, #12]
  if(huart->Instance==USART1)
 8005402:	687b      	ldr	r3, [r7, #4]
 8005404:	681b      	ldr	r3, [r3, #0]
 8005406:	4a84      	ldr	r2, [pc, #528]	; (8005618 <HAL_UART_MspInit+0x22c>)
 8005408:	4293      	cmp	r3, r2
 800540a:	d17e      	bne.n	800550a <HAL_UART_MspInit+0x11e>
  {
  /* USER CODE BEGIN USART1_MspInit 0 */

  /* USER CODE END USART1_MspInit 0 */
    /* Peripheral clock enable */
    __HAL_RCC_USART1_CLK_ENABLE();
 800540c:	4b83      	ldr	r3, [pc, #524]	; (800561c <HAL_UART_MspInit+0x230>)
 800540e:	699b      	ldr	r3, [r3, #24]
 8005410:	4a82      	ldr	r2, [pc, #520]	; (800561c <HAL_UART_MspInit+0x230>)
 8005412:	f443 4380 	orr.w	r3, r3, #16384	; 0x4000
 8005416:	6193      	str	r3, [r2, #24]
 8005418:	4b80      	ldr	r3, [pc, #512]	; (800561c <HAL_UART_MspInit+0x230>)
 800541a:	699b      	ldr	r3, [r3, #24]
 800541c:	f403 4380 	and.w	r3, r3, #16384	; 0x4000
 8005420:	617b      	str	r3, [r7, #20]
 8005422:	697b      	ldr	r3, [r7, #20]
  
    __HAL_RCC_GPIOA_CLK_ENABLE();
 8005424:	4b7d      	ldr	r3, [pc, #500]	; (800561c <HAL_UART_MspInit+0x230>)
 8005426:	699b      	ldr	r3, [r3, #24]
 8005428:	4a7c      	ldr	r2, [pc, #496]	; (800561c <HAL_UART_MspInit+0x230>)
 800542a:	f043 0304 	orr.w	r3, r3, #4
 800542e:	6193      	str	r3, [r2, #24]
 8005430:	4b7a      	ldr	r3, [pc, #488]	; (800561c <HAL_UART_MspInit+0x230>)
 8005432:	699b      	ldr	r3, [r3, #24]
 8005434:	f003 0304 	and.w	r3, r3, #4
 8005438:	613b      	str	r3, [r7, #16]
 800543a:	693b      	ldr	r3, [r7, #16]
    /**USART1 GPIO Configuration    
    PA9     ------> USART1_TX
    PA10     ------> USART1_RX 
    */
    GPIO_InitStruct.Pin = GPIO_PIN_9;
 800543c:	f44f 7300 	mov.w	r3, #512	; 0x200
 8005440:	61bb      	str	r3, [r7, #24]
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 8005442:	2302      	movs	r3, #2
 8005444:	61fb      	str	r3, [r7, #28]
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
 8005446:	2303      	movs	r3, #3
 8005448:	627b      	str	r3, [r7, #36]	; 0x24
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 800544a:	f107 0318 	add.w	r3, r7, #24
 800544e:	4619      	mov	r1, r3
 8005450:	4873      	ldr	r0, [pc, #460]	; (8005620 <HAL_UART_MspInit+0x234>)
 8005452:	f7fd fc4b 	bl	8002cec <HAL_GPIO_Init>

    GPIO_InitStruct.Pin = GPIO_PIN_10;
 8005456:	f44f 6380 	mov.w	r3, #1024	; 0x400
 800545a:	61bb      	str	r3, [r7, #24]
    GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
 800545c:	2300      	movs	r3, #0
 800545e:	61fb      	str	r3, [r7, #28]
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 8005460:	2300      	movs	r3, #0
 8005462:	623b      	str	r3, [r7, #32]
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8005464:	f107 0318 	add.w	r3, r7, #24
 8005468:	4619      	mov	r1, r3
 800546a:	486d      	ldr	r0, [pc, #436]	; (8005620 <HAL_UART_MspInit+0x234>)
 800546c:	f7fd fc3e 	bl	8002cec <HAL_GPIO_Init>

    /* USART1 DMA Init */
    /* USART1_TX Init */
    hdma_usart1_tx.Instance = DMA1_Channel4;
 8005470:	4b6c      	ldr	r3, [pc, #432]	; (8005624 <HAL_UART_MspInit+0x238>)
 8005472:	4a6d      	ldr	r2, [pc, #436]	; (8005628 <HAL_UART_MspInit+0x23c>)
 8005474:	601a      	str	r2, [r3, #0]
    hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
 8005476:	4b6b      	ldr	r3, [pc, #428]	; (8005624 <HAL_UART_MspInit+0x238>)
 8005478:	2210      	movs	r2, #16
 800547a:	605a      	str	r2, [r3, #4]
    hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
 800547c:	4b69      	ldr	r3, [pc, #420]	; (8005624 <HAL_UART_MspInit+0x238>)
 800547e:	2200      	movs	r2, #0
 8005480:	609a      	str	r2, [r3, #8]
    hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE;
 8005482:	4b68      	ldr	r3, [pc, #416]	; (8005624 <HAL_UART_MspInit+0x238>)
 8005484:	2280      	movs	r2, #128	; 0x80
 8005486:	60da      	str	r2, [r3, #12]
    hdma_usart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
 8005488:	4b66      	ldr	r3, [pc, #408]	; (8005624 <HAL_UART_MspInit+0x238>)
 800548a:	2200      	movs	r2, #0
 800548c:	611a      	str	r2, [r3, #16]
    hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
 800548e:	4b65      	ldr	r3, [pc, #404]	; (8005624 <HAL_UART_MspInit+0x238>)
 8005490:	2200      	movs	r2, #0
 8005492:	615a      	str	r2, [r3, #20]
    hdma_usart1_tx.Init.Mode = DMA_NORMAL;
 8005494:	4b63      	ldr	r3, [pc, #396]	; (8005624 <HAL_UART_MspInit+0x238>)
 8005496:	2200      	movs	r2, #0
 8005498:	619a      	str	r2, [r3, #24]
    hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW;
 800549a:	4b62      	ldr	r3, [pc, #392]	; (8005624 <HAL_UART_MspInit+0x238>)
 800549c:	2200      	movs	r2, #0
 800549e:	61da      	str	r2, [r3, #28]
    if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK)
 80054a0:	4860      	ldr	r0, [pc, #384]	; (8005624 <HAL_UART_MspInit+0x238>)
 80054a2:	f7fc ffbf 	bl	8002424 <HAL_DMA_Init>
 80054a6:	4603      	mov	r3, r0
 80054a8:	2b00      	cmp	r3, #0
 80054aa:	d001      	beq.n	80054b0 <HAL_UART_MspInit+0xc4>
    {
      Error_Handler();
 80054ac:	f7ff fee0 	bl	8005270 <Error_Handler>
    }

    __HAL_LINKDMA(huart,hdmatx,hdma_usart1_tx);
 80054b0:	687b      	ldr	r3, [r7, #4]
 80054b2:	4a5c      	ldr	r2, [pc, #368]	; (8005624 <HAL_UART_MspInit+0x238>)
 80054b4:	631a      	str	r2, [r3, #48]	; 0x30
 80054b6:	4a5b      	ldr	r2, [pc, #364]	; (8005624 <HAL_UART_MspInit+0x238>)
 80054b8:	687b      	ldr	r3, [r7, #4]
 80054ba:	6253      	str	r3, [r2, #36]	; 0x24

    /* USART1_RX Init */
    hdma_usart1_rx.Instance = DMA1_Channel5;
 80054bc:	4b5b      	ldr	r3, [pc, #364]	; (800562c <HAL_UART_MspInit+0x240>)
 80054be:	4a5c      	ldr	r2, [pc, #368]	; (8005630 <HAL_UART_MspInit+0x244>)
 80054c0:	601a      	str	r2, [r3, #0]
    hdma_usart1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
 80054c2:	4b5a      	ldr	r3, [pc, #360]	; (800562c <HAL_UART_MspInit+0x240>)
 80054c4:	2200      	movs	r2, #0
 80054c6:	605a      	str	r2, [r3, #4]
    hdma_usart1_rx.Init.PeriphInc = DMA_PINC_DISABLE;
 80054c8:	4b58      	ldr	r3, [pc, #352]	; (800562c <HAL_UART_MspInit+0x240>)
 80054ca:	2200      	movs	r2, #0
 80054cc:	609a      	str	r2, [r3, #8]
    hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE;
 80054ce:	4b57      	ldr	r3, [pc, #348]	; (800562c <HAL_UART_MspInit+0x240>)
 80054d0:	2280      	movs	r2, #128	; 0x80
 80054d2:	60da      	str	r2, [r3, #12]
    hdma_usart1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
 80054d4:	4b55      	ldr	r3, [pc, #340]	; (800562c <HAL_UART_MspInit+0x240>)
 80054d6:	2200      	movs	r2, #0
 80054d8:	611a      	str	r2, [r3, #16]
    hdma_usart1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
 80054da:	4b54      	ldr	r3, [pc, #336]	; (800562c <HAL_UART_MspInit+0x240>)
 80054dc:	2200      	movs	r2, #0
 80054de:	615a      	str	r2, [r3, #20]
    hdma_usart1_rx.Init.Mode = DMA_NORMAL;
 80054e0:	4b52      	ldr	r3, [pc, #328]	; (800562c <HAL_UART_MspInit+0x240>)
 80054e2:	2200      	movs	r2, #0
 80054e4:	619a      	str	r2, [r3, #24]
    hdma_usart1_rx.Init.Priority = DMA_PRIORITY_LOW;
 80054e6:	4b51      	ldr	r3, [pc, #324]	; (800562c <HAL_UART_MspInit+0x240>)
 80054e8:	2200      	movs	r2, #0
 80054ea:	61da      	str	r2, [r3, #28]
    if (HAL_DMA_Init(&hdma_usart1_rx) != HAL_OK)
 80054ec:	484f      	ldr	r0, [pc, #316]	; (800562c <HAL_UART_MspInit+0x240>)
 80054ee:	f7fc ff99 	bl	8002424 <HAL_DMA_Init>
 80054f2:	4603      	mov	r3, r0
 80054f4:	2b00      	cmp	r3, #0
 80054f6:	d001      	beq.n	80054fc <HAL_UART_MspInit+0x110>
    {
      Error_Handler();
 80054f8:	f7ff feba 	bl	8005270 <Error_Handler>
    }

    __HAL_LINKDMA(huart,hdmarx,hdma_usart1_rx);
 80054fc:	687b      	ldr	r3, [r7, #4]
 80054fe:	4a4b      	ldr	r2, [pc, #300]	; (800562c <HAL_UART_MspInit+0x240>)
 8005500:	635a      	str	r2, [r3, #52]	; 0x34
 8005502:	4a4a      	ldr	r2, [pc, #296]	; (800562c <HAL_UART_MspInit+0x240>)
 8005504:	687b      	ldr	r3, [r7, #4]
 8005506:	6253      	str	r3, [r2, #36]	; 0x24
  /* USER CODE BEGIN USART3_MspInit 1 */

  /* USER CODE END USART3_MspInit 1 */
  }

}
 8005508:	e082      	b.n	8005610 <HAL_UART_MspInit+0x224>
  else if(huart->Instance==USART3)
 800550a:	687b      	ldr	r3, [r7, #4]
 800550c:	681b      	ldr	r3, [r3, #0]
 800550e:	4a49      	ldr	r2, [pc, #292]	; (8005634 <HAL_UART_MspInit+0x248>)
 8005510:	4293      	cmp	r3, r2
 8005512:	d17d      	bne.n	8005610 <HAL_UART_MspInit+0x224>
    __HAL_RCC_USART3_CLK_ENABLE();
 8005514:	4b41      	ldr	r3, [pc, #260]	; (800561c <HAL_UART_MspInit+0x230>)
 8005516:	69db      	ldr	r3, [r3, #28]
 8005518:	4a40      	ldr	r2, [pc, #256]	; (800561c <HAL_UART_MspInit+0x230>)
 800551a:	f443 2380 	orr.w	r3, r3, #262144	; 0x40000
 800551e:	61d3      	str	r3, [r2, #28]
 8005520:	4b3e      	ldr	r3, [pc, #248]	; (800561c <HAL_UART_MspInit+0x230>)
 8005522:	69db      	ldr	r3, [r3, #28]
 8005524:	f403 2380 	and.w	r3, r3, #262144	; 0x40000
 8005528:	60fb      	str	r3, [r7, #12]
 800552a:	68fb      	ldr	r3, [r7, #12]
    __HAL_RCC_GPIOB_CLK_ENABLE();
 800552c:	4b3b      	ldr	r3, [pc, #236]	; (800561c <HAL_UART_MspInit+0x230>)
 800552e:	699b      	ldr	r3, [r3, #24]
 8005530:	4a3a      	ldr	r2, [pc, #232]	; (800561c <HAL_UART_MspInit+0x230>)
 8005532:	f043 0308 	orr.w	r3, r3, #8
 8005536:	6193      	str	r3, [r2, #24]
 8005538:	4b38      	ldr	r3, [pc, #224]	; (800561c <HAL_UART_MspInit+0x230>)
 800553a:	699b      	ldr	r3, [r3, #24]
 800553c:	f003 0308 	and.w	r3, r3, #8
 8005540:	60bb      	str	r3, [r7, #8]
 8005542:	68bb      	ldr	r3, [r7, #8]
    GPIO_InitStruct.Pin = GPIO_PIN_10;
 8005544:	f44f 6380 	mov.w	r3, #1024	; 0x400
 8005548:	61bb      	str	r3, [r7, #24]
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 800554a:	2302      	movs	r3, #2
 800554c:	61fb      	str	r3, [r7, #28]
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
 800554e:	2303      	movs	r3, #3
 8005550:	627b      	str	r3, [r7, #36]	; 0x24
    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8005552:	f107 0318 	add.w	r3, r7, #24
 8005556:	4619      	mov	r1, r3
 8005558:	4837      	ldr	r0, [pc, #220]	; (8005638 <HAL_UART_MspInit+0x24c>)
 800555a:	f7fd fbc7 	bl	8002cec <HAL_GPIO_Init>
    GPIO_InitStruct.Pin = GPIO_PIN_11;
 800555e:	f44f 6300 	mov.w	r3, #2048	; 0x800
 8005562:	61bb      	str	r3, [r7, #24]
    GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
 8005564:	2300      	movs	r3, #0
 8005566:	61fb      	str	r3, [r7, #28]
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 8005568:	2300      	movs	r3, #0
 800556a:	623b      	str	r3, [r7, #32]
    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 800556c:	f107 0318 	add.w	r3, r7, #24
 8005570:	4619      	mov	r1, r3
 8005572:	4831      	ldr	r0, [pc, #196]	; (8005638 <HAL_UART_MspInit+0x24c>)
 8005574:	f7fd fbba 	bl	8002cec <HAL_GPIO_Init>
    hdma_usart3_tx.Instance = DMA1_Channel2;
 8005578:	4b30      	ldr	r3, [pc, #192]	; (800563c <HAL_UART_MspInit+0x250>)
 800557a:	4a31      	ldr	r2, [pc, #196]	; (8005640 <HAL_UART_MspInit+0x254>)
 800557c:	601a      	str	r2, [r3, #0]
    hdma_usart3_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
 800557e:	4b2f      	ldr	r3, [pc, #188]	; (800563c <HAL_UART_MspInit+0x250>)
 8005580:	2210      	movs	r2, #16
 8005582:	605a      	str	r2, [r3, #4]
    hdma_usart3_tx.Init.PeriphInc = DMA_PINC_DISABLE;
 8005584:	4b2d      	ldr	r3, [pc, #180]	; (800563c <HAL_UART_MspInit+0x250>)
 8005586:	2200      	movs	r2, #0
 8005588:	609a      	str	r2, [r3, #8]
    hdma_usart3_tx.Init.MemInc = DMA_MINC_ENABLE;
 800558a:	4b2c      	ldr	r3, [pc, #176]	; (800563c <HAL_UART_MspInit+0x250>)
 800558c:	2280      	movs	r2, #128	; 0x80
 800558e:	60da      	str	r2, [r3, #12]
    hdma_usart3_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
 8005590:	4b2a      	ldr	r3, [pc, #168]	; (800563c <HAL_UART_MspInit+0x250>)
 8005592:	2200      	movs	r2, #0
 8005594:	611a      	str	r2, [r3, #16]
    hdma_usart3_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
 8005596:	4b29      	ldr	r3, [pc, #164]	; (800563c <HAL_UART_MspInit+0x250>)
 8005598:	2200      	movs	r2, #0
 800559a:	615a      	str	r2, [r3, #20]
    hdma_usart3_tx.Init.Mode = DMA_NORMAL;
 800559c:	4b27      	ldr	r3, [pc, #156]	; (800563c <HAL_UART_MspInit+0x250>)
 800559e:	2200      	movs	r2, #0
 80055a0:	619a      	str	r2, [r3, #24]
    hdma_usart3_tx.Init.Priority = DMA_PRIORITY_LOW;
 80055a2:	4b26      	ldr	r3, [pc, #152]	; (800563c <HAL_UART_MspInit+0x250>)
 80055a4:	2200      	movs	r2, #0
 80055a6:	61da      	str	r2, [r3, #28]
    if (HAL_DMA_Init(&hdma_usart3_tx) != HAL_OK)
 80055a8:	4824      	ldr	r0, [pc, #144]	; (800563c <HAL_UART_MspInit+0x250>)
 80055aa:	f7fc ff3b 	bl	8002424 <HAL_DMA_Init>
 80055ae:	4603      	mov	r3, r0
 80055b0:	2b00      	cmp	r3, #0
 80055b2:	d001      	beq.n	80055b8 <HAL_UART_MspInit+0x1cc>
      Error_Handler();
 80055b4:	f7ff fe5c 	bl	8005270 <Error_Handler>
    __HAL_LINKDMA(huart,hdmatx,hdma_usart3_tx);
 80055b8:	687b      	ldr	r3, [r7, #4]
 80055ba:	4a20      	ldr	r2, [pc, #128]	; (800563c <HAL_UART_MspInit+0x250>)
 80055bc:	631a      	str	r2, [r3, #48]	; 0x30
 80055be:	4a1f      	ldr	r2, [pc, #124]	; (800563c <HAL_UART_MspInit+0x250>)
 80055c0:	687b      	ldr	r3, [r7, #4]
 80055c2:	6253      	str	r3, [r2, #36]	; 0x24
    hdma_usart3_rx.Instance = DMA1_Channel3;
 80055c4:	4b1f      	ldr	r3, [pc, #124]	; (8005644 <HAL_UART_MspInit+0x258>)
 80055c6:	4a20      	ldr	r2, [pc, #128]	; (8005648 <HAL_UART_MspInit+0x25c>)
 80055c8:	601a      	str	r2, [r3, #0]
    hdma_usart3_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
 80055ca:	4b1e      	ldr	r3, [pc, #120]	; (8005644 <HAL_UART_MspInit+0x258>)
 80055cc:	2200      	movs	r2, #0
 80055ce:	605a      	str	r2, [r3, #4]
    hdma_usart3_rx.Init.PeriphInc = DMA_PINC_DISABLE;
 80055d0:	4b1c      	ldr	r3, [pc, #112]	; (8005644 <HAL_UART_MspInit+0x258>)
 80055d2:	2200      	movs	r2, #0
 80055d4:	609a      	str	r2, [r3, #8]
    hdma_usart3_rx.Init.MemInc = DMA_MINC_ENABLE;
 80055d6:	4b1b      	ldr	r3, [pc, #108]	; (8005644 <HAL_UART_MspInit+0x258>)
 80055d8:	2280      	movs	r2, #128	; 0x80
 80055da:	60da      	str	r2, [r3, #12]
    hdma_usart3_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
 80055dc:	4b19      	ldr	r3, [pc, #100]	; (8005644 <HAL_UART_MspInit+0x258>)
 80055de:	2200      	movs	r2, #0
 80055e0:	611a      	str	r2, [r3, #16]
    hdma_usart3_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
 80055e2:	4b18      	ldr	r3, [pc, #96]	; (8005644 <HAL_UART_MspInit+0x258>)
 80055e4:	2200      	movs	r2, #0
 80055e6:	615a      	str	r2, [r3, #20]
    hdma_usart3_rx.Init.Mode = DMA_NORMAL;
 80055e8:	4b16      	ldr	r3, [pc, #88]	; (8005644 <HAL_UART_MspInit+0x258>)
 80055ea:	2200      	movs	r2, #0
 80055ec:	619a      	str	r2, [r3, #24]
    hdma_usart3_rx.Init.Priority = DMA_PRIORITY_LOW;
 80055ee:	4b15      	ldr	r3, [pc, #84]	; (8005644 <HAL_UART_MspInit+0x258>)
 80055f0:	2200      	movs	r2, #0
 80055f2:	61da      	str	r2, [r3, #28]
    if (HAL_DMA_Init(&hdma_usart3_rx) != HAL_OK)
 80055f4:	4813      	ldr	r0, [pc, #76]	; (8005644 <HAL_UART_MspInit+0x258>)
 80055f6:	f7fc ff15 	bl	8002424 <HAL_DMA_Init>
 80055fa:	4603      	mov	r3, r0
 80055fc:	2b00      	cmp	r3, #0
 80055fe:	d001      	beq.n	8005604 <HAL_UART_MspInit+0x218>
      Error_Handler();
 8005600:	f7ff fe36 	bl	8005270 <Error_Handler>
    __HAL_LINKDMA(huart,hdmarx,hdma_usart3_rx);
 8005604:	687b      	ldr	r3, [r7, #4]
 8005606:	4a0f      	ldr	r2, [pc, #60]	; (8005644 <HAL_UART_MspInit+0x258>)
 8005608:	635a      	str	r2, [r3, #52]	; 0x34
 800560a:	4a0e      	ldr	r2, [pc, #56]	; (8005644 <HAL_UART_MspInit+0x258>)
 800560c:	687b      	ldr	r3, [r7, #4]
 800560e:	6253      	str	r3, [r2, #36]	; 0x24
}
 8005610:	bf00      	nop
 8005612:	3728      	adds	r7, #40	; 0x28
 8005614:	46bd      	mov	sp, r7
 8005616:	bd80      	pop	{r7, pc}
 8005618:	40013800 	.word	0x40013800
 800561c:	40021000 	.word	0x40021000
 8005620:	40010800 	.word	0x40010800
 8005624:	20000728 	.word	0x20000728
 8005628:	40020044 	.word	0x40020044
 800562c:	2000079c 	.word	0x2000079c
 8005630:	40020058 	.word	0x40020058
 8005634:	40004800 	.word	0x40004800
 8005638:	40010c00 	.word	0x40010c00
 800563c:	200006e4 	.word	0x200006e4
 8005640:	4002001c 	.word	0x4002001c
 8005644:	20000660 	.word	0x20000660
 8005648:	40020030 	.word	0x40020030

0800564c <HAL_InitTick>:
  *         reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). 
  * @param  TickPriority: Tick interrupt priority.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
 800564c:	b580      	push	{r7, lr}
 800564e:	b08c      	sub	sp, #48	; 0x30
 8005650:	af00      	add	r7, sp, #0
 8005652:	6078      	str	r0, [r7, #4]
  RCC_ClkInitTypeDef    clkconfig;
  uint32_t              uwTimclock = 0;
 8005654:	2300      	movs	r3, #0
 8005656:	62fb      	str	r3, [r7, #44]	; 0x2c
  uint32_t              uwPrescalerValue = 0;
 8005658:	2300      	movs	r3, #0
 800565a:	62bb      	str	r3, [r7, #40]	; 0x28
  uint32_t              pFLatency;
  
  /*Configure the TIM2 IRQ priority */
  HAL_NVIC_SetPriority(TIM2_IRQn, TickPriority ,0); 
 800565c:	2200      	movs	r2, #0
 800565e:	6879      	ldr	r1, [r7, #4]
 8005660:	201c      	movs	r0, #28
 8005662:	f7fc feb4 	bl	80023ce <HAL_NVIC_SetPriority>
  
  /* Enable the TIM2 global Interrupt */
  HAL_NVIC_EnableIRQ(TIM2_IRQn); 
 8005666:	201c      	movs	r0, #28
 8005668:	f7fc fecd 	bl	8002406 <HAL_NVIC_EnableIRQ>
  
  /* Enable TIM2 clock */
  __HAL_RCC_TIM2_CLK_ENABLE();
 800566c:	4b1f      	ldr	r3, [pc, #124]	; (80056ec <HAL_InitTick+0xa0>)
 800566e:	69db      	ldr	r3, [r3, #28]
 8005670:	4a1e      	ldr	r2, [pc, #120]	; (80056ec <HAL_InitTick+0xa0>)
 8005672:	f043 0301 	orr.w	r3, r3, #1
 8005676:	61d3      	str	r3, [r2, #28]
 8005678:	4b1c      	ldr	r3, [pc, #112]	; (80056ec <HAL_InitTick+0xa0>)
 800567a:	69db      	ldr	r3, [r3, #28]
 800567c:	f003 0301 	and.w	r3, r3, #1
 8005680:	60fb      	str	r3, [r7, #12]
 8005682:	68fb      	ldr	r3, [r7, #12]
  
  /* Get clock configuration */
  HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
 8005684:	f107 0210 	add.w	r2, r7, #16
 8005688:	f107 0314 	add.w	r3, r7, #20
 800568c:	4611      	mov	r1, r2
 800568e:	4618      	mov	r0, r3
 8005690:	f7fe f86c 	bl	800376c <HAL_RCC_GetClockConfig>
  
  /* Compute TIM2 clock */
  uwTimclock = HAL_RCC_GetPCLK1Freq();
 8005694:	f7fe f842 	bl	800371c <HAL_RCC_GetPCLK1Freq>
 8005698:	62f8      	str	r0, [r7, #44]	; 0x2c
   
  /* Compute the prescaler value to have TIM2 counter clock equal to 1MHz */
  uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000) - 1);
 800569a:	6afb      	ldr	r3, [r7, #44]	; 0x2c
 800569c:	4a14      	ldr	r2, [pc, #80]	; (80056f0 <HAL_InitTick+0xa4>)
 800569e:	fba2 2303 	umull	r2, r3, r2, r3
 80056a2:	0c9b      	lsrs	r3, r3, #18
 80056a4:	3b01      	subs	r3, #1
 80056a6:	62bb      	str	r3, [r7, #40]	; 0x28
  
  /* Initialize TIM2 */
  htim2.Instance = TIM2;
 80056a8:	4b12      	ldr	r3, [pc, #72]	; (80056f4 <HAL_InitTick+0xa8>)
 80056aa:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
 80056ae:	601a      	str	r2, [r3, #0]
  + Period = [(TIM2CLK/1000) - 1]. to have a (1/1000) s time base.
  + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
  + ClockDivision = 0
  + Counter direction = Up
  */
  htim2.Init.Period = (1000000 / 1000) - 1;
 80056b0:	4b10      	ldr	r3, [pc, #64]	; (80056f4 <HAL_InitTick+0xa8>)
 80056b2:	f240 32e7 	movw	r2, #999	; 0x3e7
 80056b6:	60da      	str	r2, [r3, #12]
  htim2.Init.Prescaler = uwPrescalerValue;
 80056b8:	4a0e      	ldr	r2, [pc, #56]	; (80056f4 <HAL_InitTick+0xa8>)
 80056ba:	6abb      	ldr	r3, [r7, #40]	; 0x28
 80056bc:	6053      	str	r3, [r2, #4]
  htim2.Init.ClockDivision = 0;
 80056be:	4b0d      	ldr	r3, [pc, #52]	; (80056f4 <HAL_InitTick+0xa8>)
 80056c0:	2200      	movs	r2, #0
 80056c2:	611a      	str	r2, [r3, #16]
  htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
 80056c4:	4b0b      	ldr	r3, [pc, #44]	; (80056f4 <HAL_InitTick+0xa8>)
 80056c6:	2200      	movs	r2, #0
 80056c8:	609a      	str	r2, [r3, #8]
  if(HAL_TIM_Base_Init(&htim2) == HAL_OK)
 80056ca:	480a      	ldr	r0, [pc, #40]	; (80056f4 <HAL_InitTick+0xa8>)
 80056cc:	f7fe f996 	bl	80039fc <HAL_TIM_Base_Init>
 80056d0:	4603      	mov	r3, r0
 80056d2:	2b00      	cmp	r3, #0
 80056d4:	d104      	bne.n	80056e0 <HAL_InitTick+0x94>
  {
    /* Start the TIM time Base generation in interrupt mode */
    return HAL_TIM_Base_Start_IT(&htim2);
 80056d6:	4807      	ldr	r0, [pc, #28]	; (80056f4 <HAL_InitTick+0xa8>)
 80056d8:	f7fe f9bb 	bl	8003a52 <HAL_TIM_Base_Start_IT>
 80056dc:	4603      	mov	r3, r0
 80056de:	e000      	b.n	80056e2 <HAL_InitTick+0x96>
  }
  
  /* Return function status */
  return HAL_ERROR;
 80056e0:	2301      	movs	r3, #1
}
 80056e2:	4618      	mov	r0, r3
 80056e4:	3730      	adds	r7, #48	; 0x30
 80056e6:	46bd      	mov	sp, r7
 80056e8:	bd80      	pop	{r7, pc}
 80056ea:	bf00      	nop
 80056ec:	40021000 	.word	0x40021000
 80056f0:	431bde83 	.word	0x431bde83
 80056f4:	200008a4 	.word	0x200008a4

080056f8 <NMI_Handler>:
/******************************************************************************/
/**
  * @brief This function handles Non maskable interrupt.
  */
void NMI_Handler(void)
{
 80056f8:	b480      	push	{r7}
 80056fa:	af00      	add	r7, sp, #0

  /* USER CODE END NonMaskableInt_IRQn 0 */
  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */

  /* USER CODE END NonMaskableInt_IRQn 1 */
}
 80056fc:	bf00      	nop
 80056fe:	46bd      	mov	sp, r7
 8005700:	bc80      	pop	{r7}
 8005702:	4770      	bx	lr

08005704 <HardFault_Handler>:

/**
  * @brief This function handles Hard fault interrupt.
  */
void HardFault_Handler(void)
{
 8005704:	b480      	push	{r7}
 8005706:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN HardFault_IRQn 0 */

  /* USER CODE END HardFault_IRQn 0 */
  while (1)
 8005708:	e7fe      	b.n	8005708 <HardFault_Handler+0x4>

0800570a <MemManage_Handler>:

/**
  * @brief This function handles Memory management fault.
  */
void MemManage_Handler(void)
{
 800570a:	b480      	push	{r7}
 800570c:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN MemoryManagement_IRQn 0 */

  /* USER CODE END MemoryManagement_IRQn 0 */
  while (1)
 800570e:	e7fe      	b.n	800570e <MemManage_Handler+0x4>

08005710 <BusFault_Handler>:

/**
  * @brief This function handles Prefetch fault, memory access fault.
  */
void BusFault_Handler(void)
{
 8005710:	b480      	push	{r7}
 8005712:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN BusFault_IRQn 0 */

  /* USER CODE END BusFault_IRQn 0 */
  while (1)
 8005714:	e7fe      	b.n	8005714 <BusFault_Handler+0x4>

08005716 <UsageFault_Handler>:

/**
  * @brief This function handles Undefined instruction or illegal state.
  */
void UsageFault_Handler(void)
{
 8005716:	b480      	push	{r7}
 8005718:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN UsageFault_IRQn 0 */

  /* USER CODE END UsageFault_IRQn 0 */
  while (1)
 800571a:	e7fe      	b.n	800571a <UsageFault_Handler+0x4>

0800571c <SVC_Handler>:

/**
  * @brief This function handles System service call via SWI instruction.
  */
void SVC_Handler(void)
{
 800571c:	b480      	push	{r7}
 800571e:	af00      	add	r7, sp, #0

  /* USER CODE END SVCall_IRQn 0 */
  /* USER CODE BEGIN SVCall_IRQn 1 */

  /* USER CODE END SVCall_IRQn 1 */
}
 8005720:	bf00      	nop
 8005722:	46bd      	mov	sp, r7
 8005724:	bc80      	pop	{r7}
 8005726:	4770      	bx	lr

08005728 <DebugMon_Handler>:

/**
  * @brief This function handles Debug monitor.
  */
void DebugMon_Handler(void)
{
 8005728:	b480      	push	{r7}
 800572a:	af00      	add	r7, sp, #0

  /* USER CODE END DebugMonitor_IRQn 0 */
  /* USER CODE BEGIN DebugMonitor_IRQn 1 */

  /* USER CODE END DebugMonitor_IRQn 1 */
}
 800572c:	bf00      	nop
 800572e:	46bd      	mov	sp, r7
 8005730:	bc80      	pop	{r7}
 8005732:	4770      	bx	lr

08005734 <PendSV_Handler>:

/**
  * @brief This function handles Pendable request for system service.
  */
void PendSV_Handler(void)
{
 8005734:	b480      	push	{r7}
 8005736:	af00      	add	r7, sp, #0

  /* USER CODE END PendSV_IRQn 0 */
  /* USER CODE BEGIN PendSV_IRQn 1 */

  /* USER CODE END PendSV_IRQn 1 */
}
 8005738:	bf00      	nop
 800573a:	46bd      	mov	sp, r7
 800573c:	bc80      	pop	{r7}
 800573e:	4770      	bx	lr

08005740 <DMA1_Channel1_IRQHandler>:

/**
  * @brief This function handles DMA1 channel1 global interrupt.
  */
void DMA1_Channel1_IRQHandler(void)
{
 8005740:	b580      	push	{r7, lr}
 8005742:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */

  /* USER CODE END DMA1_Channel1_IRQn 0 */
  HAL_DMA_IRQHandler(&hdma_adc1);
 8005744:	4802      	ldr	r0, [pc, #8]	; (8005750 <DMA1_Channel1_IRQHandler+0x10>)
 8005746:	f7fc ff9d 	bl	8002684 <HAL_DMA_IRQHandler>
  /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */

  /* USER CODE END DMA1_Channel1_IRQn 1 */
}
 800574a:	bf00      	nop
 800574c:	bd80      	pop	{r7, pc}
 800574e:	bf00      	nop
 8005750:	20000820 	.word	0x20000820

08005754 <DMA1_Channel2_IRQHandler>:

/**
  * @brief This function handles DMA1 channel2 global interrupt.
  */
void DMA1_Channel2_IRQHandler(void)
{
 8005754:	b580      	push	{r7, lr}
 8005756:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN DMA1_Channel2_IRQn 0 */

  /* USER CODE END DMA1_Channel2_IRQn 0 */
  HAL_DMA_IRQHandler(&hdma_usart3_tx);
 8005758:	4802      	ldr	r0, [pc, #8]	; (8005764 <DMA1_Channel2_IRQHandler+0x10>)
 800575a:	f7fc ff93 	bl	8002684 <HAL_DMA_IRQHandler>
  /* USER CODE BEGIN DMA1_Channel2_IRQn 1 */

  /* USER CODE END DMA1_Channel2_IRQn 1 */
}
 800575e:	bf00      	nop
 8005760:	bd80      	pop	{r7, pc}
 8005762:	bf00      	nop
 8005764:	200006e4 	.word	0x200006e4

08005768 <DMA1_Channel3_IRQHandler>:

/**
  * @brief This function handles DMA1 channel3 global interrupt.
  */
void DMA1_Channel3_IRQHandler(void)
{
 8005768:	b580      	push	{r7, lr}
 800576a:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN DMA1_Channel3_IRQn 0 */

  /* USER CODE END DMA1_Channel3_IRQn 0 */
  HAL_DMA_IRQHandler(&hdma_usart3_rx);
 800576c:	4802      	ldr	r0, [pc, #8]	; (8005778 <DMA1_Channel3_IRQHandler+0x10>)
 800576e:	f7fc ff89 	bl	8002684 <HAL_DMA_IRQHandler>
  /* USER CODE BEGIN DMA1_Channel3_IRQn 1 */

  /* USER CODE END DMA1_Channel3_IRQn 1 */
}
 8005772:	bf00      	nop
 8005774:	bd80      	pop	{r7, pc}
 8005776:	bf00      	nop
 8005778:	20000660 	.word	0x20000660

0800577c <DMA1_Channel4_IRQHandler>:

/**
  * @brief This function handles DMA1 channel4 global interrupt.
  */
void DMA1_Channel4_IRQHandler(void)
{
 800577c:	b580      	push	{r7, lr}
 800577e:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN DMA1_Channel4_IRQn 0 */

  /* USER CODE END DMA1_Channel4_IRQn 0 */
  HAL_DMA_IRQHandler(&hdma_usart1_tx);
 8005780:	4802      	ldr	r0, [pc, #8]	; (800578c <DMA1_Channel4_IRQHandler+0x10>)
 8005782:	f7fc ff7f 	bl	8002684 <HAL_DMA_IRQHandler>
  /* USER CODE BEGIN DMA1_Channel4_IRQn 1 */

  /* USER CODE END DMA1_Channel4_IRQn 1 */
}
 8005786:	bf00      	nop
 8005788:	bd80      	pop	{r7, pc}
 800578a:	bf00      	nop
 800578c:	20000728 	.word	0x20000728

08005790 <DMA1_Channel5_IRQHandler>:

/**
  * @brief This function handles DMA1 channel5 global interrupt.
  */
void DMA1_Channel5_IRQHandler(void)
{
 8005790:	b580      	push	{r7, lr}
 8005792:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN DMA1_Channel5_IRQn 0 */

  /* USER CODE END DMA1_Channel5_IRQn 0 */
  HAL_DMA_IRQHandler(&hdma_usart1_rx);
 8005794:	4802      	ldr	r0, [pc, #8]	; (80057a0 <DMA1_Channel5_IRQHandler+0x10>)
 8005796:	f7fc ff75 	bl	8002684 <HAL_DMA_IRQHandler>
  /* USER CODE BEGIN DMA1_Channel5_IRQn 1 */

  /* USER CODE END DMA1_Channel5_IRQn 1 */
}
 800579a:	bf00      	nop
 800579c:	bd80      	pop	{r7, pc}
 800579e:	bf00      	nop
 80057a0:	2000079c 	.word	0x2000079c

080057a4 <ADC1_IRQHandler>:

/**
  * @brief This function handles ADC1 global interrupt.
  */
void ADC1_IRQHandler(void)
{
 80057a4:	b580      	push	{r7, lr}
 80057a6:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN ADC1_IRQn 0 */

  /* USER CODE END ADC1_IRQn 0 */
  HAL_ADC_IRQHandler(&hadc1);
 80057a8:	4802      	ldr	r0, [pc, #8]	; (80057b4 <ADC1_IRQHandler+0x10>)
 80057aa:	f7fc f9ed 	bl	8001b88 <HAL_ADC_IRQHandler>
  /* USER CODE BEGIN ADC1_IRQn 1 */

  /* USER CODE END ADC1_IRQn 1 */
}
 80057ae:	bf00      	nop
 80057b0:	bd80      	pop	{r7, pc}
 80057b2:	bf00      	nop
 80057b4:	2000076c 	.word	0x2000076c

080057b8 <TIM2_IRQHandler>:

/**
  * @brief This function handles TIM2 global interrupt.
  */
void TIM2_IRQHandler(void)
{
 80057b8:	b580      	push	{r7, lr}
 80057ba:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN TIM2_IRQn 0 */

  /* USER CODE END TIM2_IRQn 0 */
  HAL_TIM_IRQHandler(&htim2);
 80057bc:	4802      	ldr	r0, [pc, #8]	; (80057c8 <TIM2_IRQHandler+0x10>)
 80057be:	f7fe f96b 	bl	8003a98 <HAL_TIM_IRQHandler>
  /* USER CODE BEGIN TIM2_IRQn 1 */

  /* USER CODE END TIM2_IRQn 1 */
}
 80057c2:	bf00      	nop
 80057c4:	bd80      	pop	{r7, pc}
 80057c6:	bf00      	nop
 80057c8:	200008a4 	.word	0x200008a4

080057cc <USART1_IRQHandler>:

/**
  * @brief This function handles USART1 global interrupt.
  */
void USART1_IRQHandler(void)
{
 80057cc:	b580      	push	{r7, lr}
 80057ce:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN USART1_IRQn 0 */

  /* USER CODE END USART1_IRQn 0 */
  HAL_UART_IRQHandler(&huart1);
 80057d0:	4802      	ldr	r0, [pc, #8]	; (80057dc <USART1_IRQHandler+0x10>)
 80057d2:	f7fe fd89 	bl	80042e8 <HAL_UART_IRQHandler>
  /* USER CODE BEGIN USART1_IRQn 1 */

  /* USER CODE END USART1_IRQn 1 */
}
 80057d6:	bf00      	nop
 80057d8:	bd80      	pop	{r7, pc}
 80057da:	bf00      	nop
 80057dc:	200007e0 	.word	0x200007e0

080057e0 <USART3_IRQHandler>:

/**
  * @brief This function handles USART3 global interrupt.
  */
void USART3_IRQHandler(void)
{
 80057e0:	b580      	push	{r7, lr}
 80057e2:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN USART3_IRQn 0 */

  /* USER CODE END USART3_IRQn 0 */
  HAL_UART_IRQHandler(&huart3);
 80057e4:	4802      	ldr	r0, [pc, #8]	; (80057f0 <USART3_IRQHandler+0x10>)
 80057e6:	f7fe fd7f 	bl	80042e8 <HAL_UART_IRQHandler>
  /* USER CODE BEGIN USART3_IRQn 1 */

  /* USER CODE END USART3_IRQn 1 */
}
 80057ea:	bf00      	nop
 80057ec:	bd80      	pop	{r7, pc}
 80057ee:	bf00      	nop
 80057f0:	200006a4 	.word	0x200006a4

080057f4 <TIM6_DAC_IRQHandler>:

/**
  * @brief This function handles TIM6 global interrupt and DAC underrun error interrupts.
  */
void TIM6_DAC_IRQHandler(void)
{
 80057f4:	b580      	push	{r7, lr}
 80057f6:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN TIM6_DAC_IRQn 0 */

  /* USER CODE END TIM6_DAC_IRQn 0 */
  HAL_TIM_IRQHandler(&htim6);
 80057f8:	4802      	ldr	r0, [pc, #8]	; (8005804 <TIM6_DAC_IRQHandler+0x10>)
 80057fa:	f7fe f94d 	bl	8003a98 <HAL_TIM_IRQHandler>
  /* USER CODE BEGIN TIM6_DAC_IRQn 1 */

  /* USER CODE END TIM6_DAC_IRQn 1 */
}
 80057fe:	bf00      	nop
 8005800:	bd80      	pop	{r7, pc}
 8005802:	bf00      	nop
 8005804:	20000864 	.word	0x20000864

08005808 <_read>:
	_kill(status, -1);
	while (1) {}		/* Make sure we hang here */
}

__attribute__((weak)) int _read(int file, char *ptr, int len)
{
 8005808:	b580      	push	{r7, lr}
 800580a:	b086      	sub	sp, #24
 800580c:	af00      	add	r7, sp, #0
 800580e:	60f8      	str	r0, [r7, #12]
 8005810:	60b9      	str	r1, [r7, #8]
 8005812:	607a      	str	r2, [r7, #4]
	int DataIdx;

	for (DataIdx = 0; DataIdx < len; DataIdx++)
 8005814:	2300      	movs	r3, #0
 8005816:	617b      	str	r3, [r7, #20]
 8005818:	e00a      	b.n	8005830 <_read+0x28>
	{
		*ptr++ = __io_getchar();
 800581a:	f3af 8000 	nop.w
 800581e:	4601      	mov	r1, r0
 8005820:	68bb      	ldr	r3, [r7, #8]
 8005822:	1c5a      	adds	r2, r3, #1
 8005824:	60ba      	str	r2, [r7, #8]
 8005826:	b2ca      	uxtb	r2, r1
 8005828:	701a      	strb	r2, [r3, #0]
	for (DataIdx = 0; DataIdx < len; DataIdx++)
 800582a:	697b      	ldr	r3, [r7, #20]
 800582c:	3301      	adds	r3, #1
 800582e:	617b      	str	r3, [r7, #20]
 8005830:	697a      	ldr	r2, [r7, #20]
 8005832:	687b      	ldr	r3, [r7, #4]
 8005834:	429a      	cmp	r2, r3
 8005836:	dbf0      	blt.n	800581a <_read+0x12>
	}

return len;
 8005838:	687b      	ldr	r3, [r7, #4]
}
 800583a:	4618      	mov	r0, r3
 800583c:	3718      	adds	r7, #24
 800583e:	46bd      	mov	sp, r7
 8005840:	bd80      	pop	{r7, pc}

08005842 <_close>:
	}
	return len;
}

int _close(int file)
{
 8005842:	b480      	push	{r7}
 8005844:	b083      	sub	sp, #12
 8005846:	af00      	add	r7, sp, #0
 8005848:	6078      	str	r0, [r7, #4]
	return -1;
 800584a:	f04f 33ff 	mov.w	r3, #4294967295
}
 800584e:	4618      	mov	r0, r3
 8005850:	370c      	adds	r7, #12
 8005852:	46bd      	mov	sp, r7
 8005854:	bc80      	pop	{r7}
 8005856:	4770      	bx	lr

08005858 <_fstat>:


int _fstat(int file, struct stat *st)
{
 8005858:	b480      	push	{r7}
 800585a:	b083      	sub	sp, #12
 800585c:	af00      	add	r7, sp, #0
 800585e:	6078      	str	r0, [r7, #4]
 8005860:	6039      	str	r1, [r7, #0]
	st->st_mode = S_IFCHR;
 8005862:	683b      	ldr	r3, [r7, #0]
 8005864:	f44f 5200 	mov.w	r2, #8192	; 0x2000
 8005868:	605a      	str	r2, [r3, #4]
	return 0;
 800586a:	2300      	movs	r3, #0
}
 800586c:	4618      	mov	r0, r3
 800586e:	370c      	adds	r7, #12
 8005870:	46bd      	mov	sp, r7
 8005872:	bc80      	pop	{r7}
 8005874:	4770      	bx	lr

08005876 <_isatty>:

int _isatty(int file)
{
 8005876:	b480      	push	{r7}
 8005878:	b083      	sub	sp, #12
 800587a:	af00      	add	r7, sp, #0
 800587c:	6078      	str	r0, [r7, #4]
	return 1;
 800587e:	2301      	movs	r3, #1
}
 8005880:	4618      	mov	r0, r3
 8005882:	370c      	adds	r7, #12
 8005884:	46bd      	mov	sp, r7
 8005886:	bc80      	pop	{r7}
 8005888:	4770      	bx	lr

0800588a <_lseek>:

int _lseek(int file, int ptr, int dir)
{
 800588a:	b480      	push	{r7}
 800588c:	b085      	sub	sp, #20
 800588e:	af00      	add	r7, sp, #0
 8005890:	60f8      	str	r0, [r7, #12]
 8005892:	60b9      	str	r1, [r7, #8]
 8005894:	607a      	str	r2, [r7, #4]
	return 0;
 8005896:	2300      	movs	r3, #0
}
 8005898:	4618      	mov	r0, r3
 800589a:	3714      	adds	r7, #20
 800589c:	46bd      	mov	sp, r7
 800589e:	bc80      	pop	{r7}
 80058a0:	4770      	bx	lr
	...

080058a4 <_sbrk>:
/**
 _sbrk
 Increase program data space. Malloc and related functions depend on this
**/
caddr_t _sbrk(int incr)
{
 80058a4:	b580      	push	{r7, lr}
 80058a6:	b084      	sub	sp, #16
 80058a8:	af00      	add	r7, sp, #0
 80058aa:	6078      	str	r0, [r7, #4]
	extern char end asm("end");
	static char *heap_end;
	char *prev_heap_end;

	if (heap_end == 0)
 80058ac:	4b11      	ldr	r3, [pc, #68]	; (80058f4 <_sbrk+0x50>)
 80058ae:	681b      	ldr	r3, [r3, #0]
 80058b0:	2b00      	cmp	r3, #0
 80058b2:	d102      	bne.n	80058ba <_sbrk+0x16>
		heap_end = &end;
 80058b4:	4b0f      	ldr	r3, [pc, #60]	; (80058f4 <_sbrk+0x50>)
 80058b6:	4a10      	ldr	r2, [pc, #64]	; (80058f8 <_sbrk+0x54>)
 80058b8:	601a      	str	r2, [r3, #0]

	prev_heap_end = heap_end;
 80058ba:	4b0e      	ldr	r3, [pc, #56]	; (80058f4 <_sbrk+0x50>)
 80058bc:	681b      	ldr	r3, [r3, #0]
 80058be:	60fb      	str	r3, [r7, #12]
	if (heap_end + incr > stack_ptr)
 80058c0:	4b0c      	ldr	r3, [pc, #48]	; (80058f4 <_sbrk+0x50>)
 80058c2:	681a      	ldr	r2, [r3, #0]
 80058c4:	687b      	ldr	r3, [r7, #4]
 80058c6:	4413      	add	r3, r2
 80058c8:	466a      	mov	r2, sp
 80058ca:	4293      	cmp	r3, r2
 80058cc:	d907      	bls.n	80058de <_sbrk+0x3a>
	{
		errno = ENOMEM;
 80058ce:	f000 f873 	bl	80059b8 <__errno>
 80058d2:	4602      	mov	r2, r0
 80058d4:	230c      	movs	r3, #12
 80058d6:	6013      	str	r3, [r2, #0]
		return (caddr_t) -1;
 80058d8:	f04f 33ff 	mov.w	r3, #4294967295
 80058dc:	e006      	b.n	80058ec <_sbrk+0x48>
	}

	heap_end += incr;
 80058de:	4b05      	ldr	r3, [pc, #20]	; (80058f4 <_sbrk+0x50>)
 80058e0:	681a      	ldr	r2, [r3, #0]
 80058e2:	687b      	ldr	r3, [r7, #4]
 80058e4:	4413      	add	r3, r2
 80058e6:	4a03      	ldr	r2, [pc, #12]	; (80058f4 <_sbrk+0x50>)
 80058e8:	6013      	str	r3, [r2, #0]

	return (caddr_t) prev_heap_end;
 80058ea:	68fb      	ldr	r3, [r7, #12]
}
 80058ec:	4618      	mov	r0, r3
 80058ee:	3710      	adds	r7, #16
 80058f0:	46bd      	mov	sp, r7
 80058f2:	bd80      	pop	{r7, pc}
 80058f4:	200003f0 	.word	0x200003f0
 80058f8:	200008e8 	.word	0x200008e8

080058fc <SystemInit>:
  * @note   This function should be used only after reset.
  * @param  None
  * @retval None
  */
void SystemInit (void)
{
 80058fc:	b480      	push	{r7}
 80058fe:	af00      	add	r7, sp, #0
  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
  /* Set HSION bit */
  RCC->CR |= 0x00000001U;
 8005900:	4b17      	ldr	r3, [pc, #92]	; (8005960 <SystemInit+0x64>)
 8005902:	681b      	ldr	r3, [r3, #0]
 8005904:	4a16      	ldr	r2, [pc, #88]	; (8005960 <SystemInit+0x64>)
 8005906:	f043 0301 	orr.w	r3, r3, #1
 800590a:	6013      	str	r3, [r2, #0]

  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
#if !defined(STM32F105xC) && !defined(STM32F107xC)
  RCC->CFGR &= 0xF8FF0000U;
 800590c:	4b14      	ldr	r3, [pc, #80]	; (8005960 <SystemInit+0x64>)
 800590e:	685a      	ldr	r2, [r3, #4]
 8005910:	4913      	ldr	r1, [pc, #76]	; (8005960 <SystemInit+0x64>)
 8005912:	4b14      	ldr	r3, [pc, #80]	; (8005964 <SystemInit+0x68>)
 8005914:	4013      	ands	r3, r2
 8005916:	604b      	str	r3, [r1, #4]
#else
  RCC->CFGR &= 0xF0FF0000U;
#endif /* STM32F105xC */   
  
  /* Reset HSEON, CSSON and PLLON bits */
  RCC->CR &= 0xFEF6FFFFU;
 8005918:	4b11      	ldr	r3, [pc, #68]	; (8005960 <SystemInit+0x64>)
 800591a:	681b      	ldr	r3, [r3, #0]
 800591c:	4a10      	ldr	r2, [pc, #64]	; (8005960 <SystemInit+0x64>)
 800591e:	f023 7384 	bic.w	r3, r3, #17301504	; 0x1080000
 8005922:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
 8005926:	6013      	str	r3, [r2, #0]

  /* Reset HSEBYP bit */
  RCC->CR &= 0xFFFBFFFFU;
 8005928:	4b0d      	ldr	r3, [pc, #52]	; (8005960 <SystemInit+0x64>)
 800592a:	681b      	ldr	r3, [r3, #0]
 800592c:	4a0c      	ldr	r2, [pc, #48]	; (8005960 <SystemInit+0x64>)
 800592e:	f423 2380 	bic.w	r3, r3, #262144	; 0x40000
 8005932:	6013      	str	r3, [r2, #0]

  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
  RCC->CFGR &= 0xFF80FFFFU;
 8005934:	4b0a      	ldr	r3, [pc, #40]	; (8005960 <SystemInit+0x64>)
 8005936:	685b      	ldr	r3, [r3, #4]
 8005938:	4a09      	ldr	r2, [pc, #36]	; (8005960 <SystemInit+0x64>)
 800593a:	f423 03fe 	bic.w	r3, r3, #8323072	; 0x7f0000
 800593e:	6053      	str	r3, [r2, #4]

  /* Reset CFGR2 register */
  RCC->CFGR2 = 0x00000000U;
#elif defined(STM32F100xB) || defined(STM32F100xE)
  /* Disable all interrupts and clear pending bits  */
  RCC->CIR = 0x009F0000U;
 8005940:	4b07      	ldr	r3, [pc, #28]	; (8005960 <SystemInit+0x64>)
 8005942:	f44f 021f 	mov.w	r2, #10420224	; 0x9f0000
 8005946:	609a      	str	r2, [r3, #8]

  /* Reset CFGR2 register */
  RCC->CFGR2 = 0x00000000U;      
 8005948:	4b05      	ldr	r3, [pc, #20]	; (8005960 <SystemInit+0x64>)
 800594a:	2200      	movs	r2, #0
 800594c:	62da      	str	r2, [r3, #44]	; 0x2c
#endif 

#ifdef VECT_TAB_SRAM
  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#else
  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
 800594e:	4b06      	ldr	r3, [pc, #24]	; (8005968 <SystemInit+0x6c>)
 8005950:	f04f 6200 	mov.w	r2, #134217728	; 0x8000000
 8005954:	609a      	str	r2, [r3, #8]
#endif 
}
 8005956:	bf00      	nop
 8005958:	46bd      	mov	sp, r7
 800595a:	bc80      	pop	{r7}
 800595c:	4770      	bx	lr
 800595e:	bf00      	nop
 8005960:	40021000 	.word	0x40021000
 8005964:	f8ff0000 	.word	0xf8ff0000
 8005968:	e000ed00 	.word	0xe000ed00

0800596c <Reset_Handler>:
  .weak Reset_Handler
  .type Reset_Handler, %function
Reset_Handler:

/* Copy the data segment initializers from flash to SRAM */
  movs r1, #0
 800596c:	2100      	movs	r1, #0
  b LoopCopyDataInit
 800596e:	e003      	b.n	8005978 <LoopCopyDataInit>

08005970 <CopyDataInit>:

CopyDataInit:
  ldr r3, =_sidata
 8005970:	4b0b      	ldr	r3, [pc, #44]	; (80059a0 <LoopFillZerobss+0x14>)
  ldr r3, [r3, r1]
 8005972:	585b      	ldr	r3, [r3, r1]
  str r3, [r0, r1]
 8005974:	5043      	str	r3, [r0, r1]
  adds r1, r1, #4
 8005976:	3104      	adds	r1, #4

08005978 <LoopCopyDataInit>:

LoopCopyDataInit:
  ldr r0, =_sdata
 8005978:	480a      	ldr	r0, [pc, #40]	; (80059a4 <LoopFillZerobss+0x18>)
  ldr r3, =_edata
 800597a:	4b0b      	ldr	r3, [pc, #44]	; (80059a8 <LoopFillZerobss+0x1c>)
  adds r2, r0, r1
 800597c:	1842      	adds	r2, r0, r1
  cmp r2, r3
 800597e:	429a      	cmp	r2, r3
  bcc CopyDataInit
 8005980:	d3f6      	bcc.n	8005970 <CopyDataInit>
  ldr r2, =_sbss
 8005982:	4a0a      	ldr	r2, [pc, #40]	; (80059ac <LoopFillZerobss+0x20>)
  b LoopFillZerobss
 8005984:	e002      	b.n	800598c <LoopFillZerobss>

08005986 <FillZerobss>:
/* Zero fill the bss segment. */
FillZerobss:
  movs r3, #0
 8005986:	2300      	movs	r3, #0
  str r3, [r2], #4
 8005988:	f842 3b04 	str.w	r3, [r2], #4

0800598c <LoopFillZerobss>:

LoopFillZerobss:
  ldr r3, = _ebss
 800598c:	4b08      	ldr	r3, [pc, #32]	; (80059b0 <LoopFillZerobss+0x24>)
  cmp r2, r3
 800598e:	429a      	cmp	r2, r3
  bcc FillZerobss
 8005990:	d3f9      	bcc.n	8005986 <FillZerobss>

/* Call the clock system intitialization function.*/
    bl  SystemInit
 8005992:	f7ff ffb3 	bl	80058fc <SystemInit>
/* Call static constructors */
    bl __libc_init_array
 8005996:	f000 f815 	bl	80059c4 <__libc_init_array>
/* Call the application's entry point.*/
  bl main
 800599a:	f7ff f9a3 	bl	8004ce4 <main>
  bx lr
 800599e:	4770      	bx	lr
  ldr r3, =_sidata
 80059a0:	080088c0 	.word	0x080088c0
  ldr r0, =_sdata
 80059a4:	20000000 	.word	0x20000000
  ldr r3, =_edata
 80059a8:	200001dc 	.word	0x200001dc
  ldr r2, =_sbss
 80059ac:	200001e0 	.word	0x200001e0
  ldr r3, = _ebss
 80059b0:	200008e8 	.word	0x200008e8

080059b4 <CEC_IRQHandler>:
 * @retval : None
*/
    .section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
  b Infinite_Loop
 80059b4:	e7fe      	b.n	80059b4 <CEC_IRQHandler>
	...

080059b8 <__errno>:
 80059b8:	4b01      	ldr	r3, [pc, #4]	; (80059c0 <__errno+0x8>)
 80059ba:	6818      	ldr	r0, [r3, #0]
 80059bc:	4770      	bx	lr
 80059be:	bf00      	nop
 80059c0:	2000000c 	.word	0x2000000c

080059c4 <__libc_init_array>:
 80059c4:	b570      	push	{r4, r5, r6, lr}
 80059c6:	2500      	movs	r5, #0
 80059c8:	4e0c      	ldr	r6, [pc, #48]	; (80059fc <__libc_init_array+0x38>)
 80059ca:	4c0d      	ldr	r4, [pc, #52]	; (8005a00 <__libc_init_array+0x3c>)
 80059cc:	1ba4      	subs	r4, r4, r6
 80059ce:	10a4      	asrs	r4, r4, #2
 80059d0:	42a5      	cmp	r5, r4
 80059d2:	d109      	bne.n	80059e8 <__libc_init_array+0x24>
 80059d4:	f002 fc62 	bl	800829c <_init>
 80059d8:	2500      	movs	r5, #0
 80059da:	4e0a      	ldr	r6, [pc, #40]	; (8005a04 <__libc_init_array+0x40>)
 80059dc:	4c0a      	ldr	r4, [pc, #40]	; (8005a08 <__libc_init_array+0x44>)
 80059de:	1ba4      	subs	r4, r4, r6
 80059e0:	10a4      	asrs	r4, r4, #2
 80059e2:	42a5      	cmp	r5, r4
 80059e4:	d105      	bne.n	80059f2 <__libc_init_array+0x2e>
 80059e6:	bd70      	pop	{r4, r5, r6, pc}
 80059e8:	f856 3025 	ldr.w	r3, [r6, r5, lsl #2]
 80059ec:	4798      	blx	r3
 80059ee:	3501      	adds	r5, #1
 80059f0:	e7ee      	b.n	80059d0 <__libc_init_array+0xc>
 80059f2:	f856 3025 	ldr.w	r3, [r6, r5, lsl #2]
 80059f6:	4798      	blx	r3
 80059f8:	3501      	adds	r5, #1
 80059fa:	e7f2      	b.n	80059e2 <__libc_init_array+0x1e>
 80059fc:	080088b8 	.word	0x080088b8
 8005a00:	080088b8 	.word	0x080088b8
 8005a04:	080088b8 	.word	0x080088b8
 8005a08:	080088bc 	.word	0x080088bc

08005a0c <memset>:
 8005a0c:	4603      	mov	r3, r0
 8005a0e:	4402      	add	r2, r0
 8005a10:	4293      	cmp	r3, r2
 8005a12:	d100      	bne.n	8005a16 <memset+0xa>
 8005a14:	4770      	bx	lr
 8005a16:	f803 1b01 	strb.w	r1, [r3], #1
 8005a1a:	e7f9      	b.n	8005a10 <memset+0x4>

08005a1c <__cvt>:
 8005a1c:	2b00      	cmp	r3, #0
 8005a1e:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
 8005a22:	461e      	mov	r6, r3
 8005a24:	bfbb      	ittet	lt
 8005a26:	f103 4300 	addlt.w	r3, r3, #2147483648	; 0x80000000
 8005a2a:	461e      	movlt	r6, r3
 8005a2c:	2300      	movge	r3, #0
 8005a2e:	232d      	movlt	r3, #45	; 0x2d
 8005a30:	b088      	sub	sp, #32
 8005a32:	9f14      	ldr	r7, [sp, #80]	; 0x50
 8005a34:	e9dd 1a12 	ldrd	r1, sl, [sp, #72]	; 0x48
 8005a38:	f027 0720 	bic.w	r7, r7, #32
 8005a3c:	2f46      	cmp	r7, #70	; 0x46
 8005a3e:	4614      	mov	r4, r2
 8005a40:	9d10      	ldr	r5, [sp, #64]	; 0x40
 8005a42:	700b      	strb	r3, [r1, #0]
 8005a44:	d004      	beq.n	8005a50 <__cvt+0x34>
 8005a46:	2f45      	cmp	r7, #69	; 0x45
 8005a48:	d100      	bne.n	8005a4c <__cvt+0x30>
 8005a4a:	3501      	adds	r5, #1
 8005a4c:	2302      	movs	r3, #2
 8005a4e:	e000      	b.n	8005a52 <__cvt+0x36>
 8005a50:	2303      	movs	r3, #3
 8005a52:	aa07      	add	r2, sp, #28
 8005a54:	9204      	str	r2, [sp, #16]
 8005a56:	aa06      	add	r2, sp, #24
 8005a58:	e9cd a202 	strd	sl, r2, [sp, #8]
 8005a5c:	e9cd 3500 	strd	r3, r5, [sp]
 8005a60:	4622      	mov	r2, r4
 8005a62:	4633      	mov	r3, r6
 8005a64:	f000 feac 	bl	80067c0 <_dtoa_r>
 8005a68:	2f47      	cmp	r7, #71	; 0x47
 8005a6a:	4680      	mov	r8, r0
 8005a6c:	d102      	bne.n	8005a74 <__cvt+0x58>
 8005a6e:	9b11      	ldr	r3, [sp, #68]	; 0x44
 8005a70:	07db      	lsls	r3, r3, #31
 8005a72:	d526      	bpl.n	8005ac2 <__cvt+0xa6>
 8005a74:	2f46      	cmp	r7, #70	; 0x46
 8005a76:	eb08 0905 	add.w	r9, r8, r5
 8005a7a:	d111      	bne.n	8005aa0 <__cvt+0x84>
 8005a7c:	f898 3000 	ldrb.w	r3, [r8]
 8005a80:	2b30      	cmp	r3, #48	; 0x30
 8005a82:	d10a      	bne.n	8005a9a <__cvt+0x7e>
 8005a84:	2200      	movs	r2, #0
 8005a86:	2300      	movs	r3, #0
 8005a88:	4620      	mov	r0, r4
 8005a8a:	4631      	mov	r1, r6
 8005a8c:	f7fa ffec 	bl	8000a68 <__aeabi_dcmpeq>
 8005a90:	b918      	cbnz	r0, 8005a9a <__cvt+0x7e>
 8005a92:	f1c5 0501 	rsb	r5, r5, #1
 8005a96:	f8ca 5000 	str.w	r5, [sl]
 8005a9a:	f8da 3000 	ldr.w	r3, [sl]
 8005a9e:	4499      	add	r9, r3
 8005aa0:	2200      	movs	r2, #0
 8005aa2:	2300      	movs	r3, #0
 8005aa4:	4620      	mov	r0, r4
 8005aa6:	4631      	mov	r1, r6
 8005aa8:	f7fa ffde 	bl	8000a68 <__aeabi_dcmpeq>
 8005aac:	b938      	cbnz	r0, 8005abe <__cvt+0xa2>
 8005aae:	2230      	movs	r2, #48	; 0x30
 8005ab0:	9b07      	ldr	r3, [sp, #28]
 8005ab2:	454b      	cmp	r3, r9
 8005ab4:	d205      	bcs.n	8005ac2 <__cvt+0xa6>
 8005ab6:	1c59      	adds	r1, r3, #1
 8005ab8:	9107      	str	r1, [sp, #28]
 8005aba:	701a      	strb	r2, [r3, #0]
 8005abc:	e7f8      	b.n	8005ab0 <__cvt+0x94>
 8005abe:	f8cd 901c 	str.w	r9, [sp, #28]
 8005ac2:	4640      	mov	r0, r8
 8005ac4:	9b07      	ldr	r3, [sp, #28]
 8005ac6:	9a15      	ldr	r2, [sp, #84]	; 0x54
 8005ac8:	eba3 0308 	sub.w	r3, r3, r8
 8005acc:	6013      	str	r3, [r2, #0]
 8005ace:	b008      	add	sp, #32
 8005ad0:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}

08005ad4 <__exponent>:
 8005ad4:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
 8005ad6:	2900      	cmp	r1, #0
 8005ad8:	bfb4      	ite	lt
 8005ada:	232d      	movlt	r3, #45	; 0x2d
 8005adc:	232b      	movge	r3, #43	; 0x2b
 8005ade:	4604      	mov	r4, r0
 8005ae0:	bfb8      	it	lt
 8005ae2:	4249      	neglt	r1, r1
 8005ae4:	2909      	cmp	r1, #9
 8005ae6:	f804 2b02 	strb.w	r2, [r4], #2
 8005aea:	7043      	strb	r3, [r0, #1]
 8005aec:	dd21      	ble.n	8005b32 <__exponent+0x5e>
 8005aee:	f10d 0307 	add.w	r3, sp, #7
 8005af2:	461f      	mov	r7, r3
 8005af4:	260a      	movs	r6, #10
 8005af6:	fb91 f5f6 	sdiv	r5, r1, r6
 8005afa:	fb06 1115 	mls	r1, r6, r5, r1
 8005afe:	2d09      	cmp	r5, #9
 8005b00:	f101 0130 	add.w	r1, r1, #48	; 0x30
 8005b04:	f803 1c01 	strb.w	r1, [r3, #-1]
 8005b08:	f103 32ff 	add.w	r2, r3, #4294967295
 8005b0c:	4629      	mov	r1, r5
 8005b0e:	dc09      	bgt.n	8005b24 <__exponent+0x50>
 8005b10:	3130      	adds	r1, #48	; 0x30
 8005b12:	3b02      	subs	r3, #2
 8005b14:	f802 1c01 	strb.w	r1, [r2, #-1]
 8005b18:	42bb      	cmp	r3, r7
 8005b1a:	4622      	mov	r2, r4
 8005b1c:	d304      	bcc.n	8005b28 <__exponent+0x54>
 8005b1e:	1a10      	subs	r0, r2, r0
 8005b20:	b003      	add	sp, #12
 8005b22:	bdf0      	pop	{r4, r5, r6, r7, pc}
 8005b24:	4613      	mov	r3, r2
 8005b26:	e7e6      	b.n	8005af6 <__exponent+0x22>
 8005b28:	f813 2b01 	ldrb.w	r2, [r3], #1
 8005b2c:	f804 2b01 	strb.w	r2, [r4], #1
 8005b30:	e7f2      	b.n	8005b18 <__exponent+0x44>
 8005b32:	2330      	movs	r3, #48	; 0x30
 8005b34:	4419      	add	r1, r3
 8005b36:	7083      	strb	r3, [r0, #2]
 8005b38:	1d02      	adds	r2, r0, #4
 8005b3a:	70c1      	strb	r1, [r0, #3]
 8005b3c:	e7ef      	b.n	8005b1e <__exponent+0x4a>
	...

08005b40 <_printf_float>:
 8005b40:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
 8005b44:	b091      	sub	sp, #68	; 0x44
 8005b46:	460c      	mov	r4, r1
 8005b48:	9f1a      	ldr	r7, [sp, #104]	; 0x68
 8005b4a:	4693      	mov	fp, r2
 8005b4c:	461e      	mov	r6, r3
 8005b4e:	4605      	mov	r5, r0
 8005b50:	f001 fd64 	bl	800761c <_localeconv_r>
 8005b54:	6803      	ldr	r3, [r0, #0]
 8005b56:	4618      	mov	r0, r3
 8005b58:	9309      	str	r3, [sp, #36]	; 0x24
 8005b5a:	f7fa fb59 	bl	8000210 <strlen>
 8005b5e:	2300      	movs	r3, #0
 8005b60:	930e      	str	r3, [sp, #56]	; 0x38
 8005b62:	683b      	ldr	r3, [r7, #0]
 8005b64:	900a      	str	r0, [sp, #40]	; 0x28
 8005b66:	3307      	adds	r3, #7
 8005b68:	f023 0307 	bic.w	r3, r3, #7
 8005b6c:	f103 0208 	add.w	r2, r3, #8
 8005b70:	f894 8018 	ldrb.w	r8, [r4, #24]
 8005b74:	f8d4 a000 	ldr.w	sl, [r4]
 8005b78:	603a      	str	r2, [r7, #0]
 8005b7a:	e9d3 2300 	ldrd	r2, r3, [r3]
 8005b7e:	e9c4 2312 	strd	r2, r3, [r4, #72]	; 0x48
 8005b82:	e9d4 7912 	ldrd	r7, r9, [r4, #72]	; 0x48
 8005b86:	f029 4300 	bic.w	r3, r9, #2147483648	; 0x80000000
 8005b8a:	930b      	str	r3, [sp, #44]	; 0x2c
 8005b8c:	f04f 32ff 	mov.w	r2, #4294967295
 8005b90:	4ba6      	ldr	r3, [pc, #664]	; (8005e2c <_printf_float+0x2ec>)
 8005b92:	4638      	mov	r0, r7
 8005b94:	990b      	ldr	r1, [sp, #44]	; 0x2c
 8005b96:	f7fa ff99 	bl	8000acc <__aeabi_dcmpun>
 8005b9a:	bb68      	cbnz	r0, 8005bf8 <_printf_float+0xb8>
 8005b9c:	f04f 32ff 	mov.w	r2, #4294967295
 8005ba0:	4ba2      	ldr	r3, [pc, #648]	; (8005e2c <_printf_float+0x2ec>)
 8005ba2:	4638      	mov	r0, r7
 8005ba4:	990b      	ldr	r1, [sp, #44]	; 0x2c
 8005ba6:	f7fa ff73 	bl	8000a90 <__aeabi_dcmple>
 8005baa:	bb28      	cbnz	r0, 8005bf8 <_printf_float+0xb8>
 8005bac:	2200      	movs	r2, #0
 8005bae:	2300      	movs	r3, #0
 8005bb0:	4638      	mov	r0, r7
 8005bb2:	4649      	mov	r1, r9
 8005bb4:	f7fa ff62 	bl	8000a7c <__aeabi_dcmplt>
 8005bb8:	b110      	cbz	r0, 8005bc0 <_printf_float+0x80>
 8005bba:	232d      	movs	r3, #45	; 0x2d
 8005bbc:	f884 3043 	strb.w	r3, [r4, #67]	; 0x43
 8005bc0:	4f9b      	ldr	r7, [pc, #620]	; (8005e30 <_printf_float+0x2f0>)
 8005bc2:	4b9c      	ldr	r3, [pc, #624]	; (8005e34 <_printf_float+0x2f4>)
 8005bc4:	f1b8 0f47 	cmp.w	r8, #71	; 0x47
 8005bc8:	bf98      	it	ls
 8005bca:	461f      	movls	r7, r3
 8005bcc:	2303      	movs	r3, #3
 8005bce:	f04f 0900 	mov.w	r9, #0
 8005bd2:	6123      	str	r3, [r4, #16]
 8005bd4:	f02a 0304 	bic.w	r3, sl, #4
 8005bd8:	6023      	str	r3, [r4, #0]
 8005bda:	9600      	str	r6, [sp, #0]
 8005bdc:	465b      	mov	r3, fp
 8005bde:	aa0f      	add	r2, sp, #60	; 0x3c
 8005be0:	4621      	mov	r1, r4
 8005be2:	4628      	mov	r0, r5
 8005be4:	f000 f9e2 	bl	8005fac <_printf_common>
 8005be8:	3001      	adds	r0, #1
 8005bea:	f040 8090 	bne.w	8005d0e <_printf_float+0x1ce>
 8005bee:	f04f 30ff 	mov.w	r0, #4294967295
 8005bf2:	b011      	add	sp, #68	; 0x44
 8005bf4:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
 8005bf8:	463a      	mov	r2, r7
 8005bfa:	464b      	mov	r3, r9
 8005bfc:	4638      	mov	r0, r7
 8005bfe:	4649      	mov	r1, r9
 8005c00:	f7fa ff64 	bl	8000acc <__aeabi_dcmpun>
 8005c04:	b110      	cbz	r0, 8005c0c <_printf_float+0xcc>
 8005c06:	4f8c      	ldr	r7, [pc, #560]	; (8005e38 <_printf_float+0x2f8>)
 8005c08:	4b8c      	ldr	r3, [pc, #560]	; (8005e3c <_printf_float+0x2fc>)
 8005c0a:	e7db      	b.n	8005bc4 <_printf_float+0x84>
 8005c0c:	6863      	ldr	r3, [r4, #4]
 8005c0e:	f44a 6280 	orr.w	r2, sl, #1024	; 0x400
 8005c12:	1c59      	adds	r1, r3, #1
 8005c14:	a80d      	add	r0, sp, #52	; 0x34
 8005c16:	a90e      	add	r1, sp, #56	; 0x38
 8005c18:	d140      	bne.n	8005c9c <_printf_float+0x15c>
 8005c1a:	2306      	movs	r3, #6
 8005c1c:	6063      	str	r3, [r4, #4]
 8005c1e:	f04f 0c00 	mov.w	ip, #0
 8005c22:	f10d 0333 	add.w	r3, sp, #51	; 0x33
 8005c26:	e9cd 2301 	strd	r2, r3, [sp, #4]
 8005c2a:	6863      	ldr	r3, [r4, #4]
 8005c2c:	6022      	str	r2, [r4, #0]
 8005c2e:	e9cd 0803 	strd	r0, r8, [sp, #12]
 8005c32:	9300      	str	r3, [sp, #0]
 8005c34:	463a      	mov	r2, r7
 8005c36:	464b      	mov	r3, r9
 8005c38:	e9cd 1c05 	strd	r1, ip, [sp, #20]
 8005c3c:	4628      	mov	r0, r5
 8005c3e:	f7ff feed 	bl	8005a1c <__cvt>
 8005c42:	f008 03df 	and.w	r3, r8, #223	; 0xdf
 8005c46:	2b47      	cmp	r3, #71	; 0x47
 8005c48:	4607      	mov	r7, r0
 8005c4a:	d109      	bne.n	8005c60 <_printf_float+0x120>
 8005c4c:	9b0d      	ldr	r3, [sp, #52]	; 0x34
 8005c4e:	1cd8      	adds	r0, r3, #3
 8005c50:	db02      	blt.n	8005c58 <_printf_float+0x118>
 8005c52:	6862      	ldr	r2, [r4, #4]
 8005c54:	4293      	cmp	r3, r2
 8005c56:	dd47      	ble.n	8005ce8 <_printf_float+0x1a8>
 8005c58:	f1a8 0802 	sub.w	r8, r8, #2
 8005c5c:	fa5f f888 	uxtb.w	r8, r8
 8005c60:	f1b8 0f65 	cmp.w	r8, #101	; 0x65
 8005c64:	990d      	ldr	r1, [sp, #52]	; 0x34
 8005c66:	d824      	bhi.n	8005cb2 <_printf_float+0x172>
 8005c68:	3901      	subs	r1, #1
 8005c6a:	4642      	mov	r2, r8
 8005c6c:	f104 0050 	add.w	r0, r4, #80	; 0x50
 8005c70:	910d      	str	r1, [sp, #52]	; 0x34
 8005c72:	f7ff ff2f 	bl	8005ad4 <__exponent>
 8005c76:	9a0e      	ldr	r2, [sp, #56]	; 0x38
 8005c78:	4681      	mov	r9, r0
 8005c7a:	1813      	adds	r3, r2, r0
 8005c7c:	2a01      	cmp	r2, #1
 8005c7e:	6123      	str	r3, [r4, #16]
 8005c80:	dc02      	bgt.n	8005c88 <_printf_float+0x148>
 8005c82:	6822      	ldr	r2, [r4, #0]
 8005c84:	07d1      	lsls	r1, r2, #31
 8005c86:	d501      	bpl.n	8005c8c <_printf_float+0x14c>
 8005c88:	3301      	adds	r3, #1
 8005c8a:	6123      	str	r3, [r4, #16]
 8005c8c:	f89d 3033 	ldrb.w	r3, [sp, #51]	; 0x33
 8005c90:	2b00      	cmp	r3, #0
 8005c92:	d0a2      	beq.n	8005bda <_printf_float+0x9a>
 8005c94:	232d      	movs	r3, #45	; 0x2d
 8005c96:	f884 3043 	strb.w	r3, [r4, #67]	; 0x43
 8005c9a:	e79e      	b.n	8005bda <_printf_float+0x9a>
 8005c9c:	f1b8 0f67 	cmp.w	r8, #103	; 0x67
 8005ca0:	f000 816e 	beq.w	8005f80 <_printf_float+0x440>
 8005ca4:	f1b8 0f47 	cmp.w	r8, #71	; 0x47
 8005ca8:	d1b9      	bne.n	8005c1e <_printf_float+0xde>
 8005caa:	2b00      	cmp	r3, #0
 8005cac:	d1b7      	bne.n	8005c1e <_printf_float+0xde>
 8005cae:	2301      	movs	r3, #1
 8005cb0:	e7b4      	b.n	8005c1c <_printf_float+0xdc>
 8005cb2:	f1b8 0f66 	cmp.w	r8, #102	; 0x66
 8005cb6:	d119      	bne.n	8005cec <_printf_float+0x1ac>
 8005cb8:	2900      	cmp	r1, #0
 8005cba:	6863      	ldr	r3, [r4, #4]
 8005cbc:	dd0c      	ble.n	8005cd8 <_printf_float+0x198>
 8005cbe:	6121      	str	r1, [r4, #16]
 8005cc0:	b913      	cbnz	r3, 8005cc8 <_printf_float+0x188>
 8005cc2:	6822      	ldr	r2, [r4, #0]
 8005cc4:	07d2      	lsls	r2, r2, #31
 8005cc6:	d502      	bpl.n	8005cce <_printf_float+0x18e>
 8005cc8:	3301      	adds	r3, #1
 8005cca:	440b      	add	r3, r1
 8005ccc:	6123      	str	r3, [r4, #16]
 8005cce:	9b0d      	ldr	r3, [sp, #52]	; 0x34
 8005cd0:	f04f 0900 	mov.w	r9, #0
 8005cd4:	65a3      	str	r3, [r4, #88]	; 0x58
 8005cd6:	e7d9      	b.n	8005c8c <_printf_float+0x14c>
 8005cd8:	b913      	cbnz	r3, 8005ce0 <_printf_float+0x1a0>
 8005cda:	6822      	ldr	r2, [r4, #0]
 8005cdc:	07d0      	lsls	r0, r2, #31
 8005cde:	d501      	bpl.n	8005ce4 <_printf_float+0x1a4>
 8005ce0:	3302      	adds	r3, #2
 8005ce2:	e7f3      	b.n	8005ccc <_printf_float+0x18c>
 8005ce4:	2301      	movs	r3, #1
 8005ce6:	e7f1      	b.n	8005ccc <_printf_float+0x18c>
 8005ce8:	f04f 0867 	mov.w	r8, #103	; 0x67
 8005cec:	e9dd 320d 	ldrd	r3, r2, [sp, #52]	; 0x34
 8005cf0:	4293      	cmp	r3, r2
 8005cf2:	db05      	blt.n	8005d00 <_printf_float+0x1c0>
 8005cf4:	6822      	ldr	r2, [r4, #0]
 8005cf6:	6123      	str	r3, [r4, #16]
 8005cf8:	07d1      	lsls	r1, r2, #31
 8005cfa:	d5e8      	bpl.n	8005cce <_printf_float+0x18e>
 8005cfc:	3301      	adds	r3, #1
 8005cfe:	e7e5      	b.n	8005ccc <_printf_float+0x18c>
 8005d00:	2b00      	cmp	r3, #0
 8005d02:	bfcc      	ite	gt
 8005d04:	2301      	movgt	r3, #1
 8005d06:	f1c3 0302 	rsble	r3, r3, #2
 8005d0a:	4413      	add	r3, r2
 8005d0c:	e7de      	b.n	8005ccc <_printf_float+0x18c>
 8005d0e:	6823      	ldr	r3, [r4, #0]
 8005d10:	055a      	lsls	r2, r3, #21
 8005d12:	d407      	bmi.n	8005d24 <_printf_float+0x1e4>
 8005d14:	6923      	ldr	r3, [r4, #16]
 8005d16:	463a      	mov	r2, r7
 8005d18:	4659      	mov	r1, fp
 8005d1a:	4628      	mov	r0, r5
 8005d1c:	47b0      	blx	r6
 8005d1e:	3001      	adds	r0, #1
 8005d20:	d129      	bne.n	8005d76 <_printf_float+0x236>
 8005d22:	e764      	b.n	8005bee <_printf_float+0xae>
 8005d24:	f1b8 0f65 	cmp.w	r8, #101	; 0x65
 8005d28:	f240 80d7 	bls.w	8005eda <_printf_float+0x39a>
 8005d2c:	e9d4 0112 	ldrd	r0, r1, [r4, #72]	; 0x48
 8005d30:	2200      	movs	r2, #0
 8005d32:	2300      	movs	r3, #0
 8005d34:	f7fa fe98 	bl	8000a68 <__aeabi_dcmpeq>
 8005d38:	b388      	cbz	r0, 8005d9e <_printf_float+0x25e>
 8005d3a:	2301      	movs	r3, #1
 8005d3c:	4a40      	ldr	r2, [pc, #256]	; (8005e40 <_printf_float+0x300>)
 8005d3e:	4659      	mov	r1, fp
 8005d40:	4628      	mov	r0, r5
 8005d42:	47b0      	blx	r6
 8005d44:	3001      	adds	r0, #1
 8005d46:	f43f af52 	beq.w	8005bee <_printf_float+0xae>
 8005d4a:	e9dd 230d 	ldrd	r2, r3, [sp, #52]	; 0x34
 8005d4e:	429a      	cmp	r2, r3
 8005d50:	db02      	blt.n	8005d58 <_printf_float+0x218>
 8005d52:	6823      	ldr	r3, [r4, #0]
 8005d54:	07d8      	lsls	r0, r3, #31
 8005d56:	d50e      	bpl.n	8005d76 <_printf_float+0x236>
 8005d58:	e9dd 2309 	ldrd	r2, r3, [sp, #36]	; 0x24
 8005d5c:	4659      	mov	r1, fp
 8005d5e:	4628      	mov	r0, r5
 8005d60:	47b0      	blx	r6
 8005d62:	3001      	adds	r0, #1
 8005d64:	f43f af43 	beq.w	8005bee <_printf_float+0xae>
 8005d68:	2700      	movs	r7, #0
 8005d6a:	f104 081a 	add.w	r8, r4, #26
 8005d6e:	9b0e      	ldr	r3, [sp, #56]	; 0x38
 8005d70:	3b01      	subs	r3, #1
 8005d72:	42bb      	cmp	r3, r7
 8005d74:	dc09      	bgt.n	8005d8a <_printf_float+0x24a>
 8005d76:	6823      	ldr	r3, [r4, #0]
 8005d78:	079f      	lsls	r7, r3, #30
 8005d7a:	f100 80fd 	bmi.w	8005f78 <_printf_float+0x438>
 8005d7e:	68e0      	ldr	r0, [r4, #12]
 8005d80:	9b0f      	ldr	r3, [sp, #60]	; 0x3c
 8005d82:	4298      	cmp	r0, r3
 8005d84:	bfb8      	it	lt
 8005d86:	4618      	movlt	r0, r3
 8005d88:	e733      	b.n	8005bf2 <_printf_float+0xb2>
 8005d8a:	2301      	movs	r3, #1
 8005d8c:	4642      	mov	r2, r8
 8005d8e:	4659      	mov	r1, fp
 8005d90:	4628      	mov	r0, r5
 8005d92:	47b0      	blx	r6
 8005d94:	3001      	adds	r0, #1
 8005d96:	f43f af2a 	beq.w	8005bee <_printf_float+0xae>
 8005d9a:	3701      	adds	r7, #1
 8005d9c:	e7e7      	b.n	8005d6e <_printf_float+0x22e>
 8005d9e:	9b0d      	ldr	r3, [sp, #52]	; 0x34
 8005da0:	2b00      	cmp	r3, #0
 8005da2:	dc2b      	bgt.n	8005dfc <_printf_float+0x2bc>
 8005da4:	2301      	movs	r3, #1
 8005da6:	4a26      	ldr	r2, [pc, #152]	; (8005e40 <_printf_float+0x300>)
 8005da8:	4659      	mov	r1, fp
 8005daa:	4628      	mov	r0, r5
 8005dac:	47b0      	blx	r6
 8005dae:	3001      	adds	r0, #1
 8005db0:	f43f af1d 	beq.w	8005bee <_printf_float+0xae>
 8005db4:	9b0d      	ldr	r3, [sp, #52]	; 0x34
 8005db6:	b923      	cbnz	r3, 8005dc2 <_printf_float+0x282>
 8005db8:	9b0e      	ldr	r3, [sp, #56]	; 0x38
 8005dba:	b913      	cbnz	r3, 8005dc2 <_printf_float+0x282>
 8005dbc:	6823      	ldr	r3, [r4, #0]
 8005dbe:	07d9      	lsls	r1, r3, #31
 8005dc0:	d5d9      	bpl.n	8005d76 <_printf_float+0x236>
 8005dc2:	e9dd 2309 	ldrd	r2, r3, [sp, #36]	; 0x24
 8005dc6:	4659      	mov	r1, fp
 8005dc8:	4628      	mov	r0, r5
 8005dca:	47b0      	blx	r6
 8005dcc:	3001      	adds	r0, #1
 8005dce:	f43f af0e 	beq.w	8005bee <_printf_float+0xae>
 8005dd2:	f04f 0800 	mov.w	r8, #0
 8005dd6:	f104 091a 	add.w	r9, r4, #26
 8005dda:	9b0d      	ldr	r3, [sp, #52]	; 0x34
 8005ddc:	425b      	negs	r3, r3
 8005dde:	4543      	cmp	r3, r8
 8005de0:	dc01      	bgt.n	8005de6 <_printf_float+0x2a6>
 8005de2:	9b0e      	ldr	r3, [sp, #56]	; 0x38
 8005de4:	e797      	b.n	8005d16 <_printf_float+0x1d6>
 8005de6:	2301      	movs	r3, #1
 8005de8:	464a      	mov	r2, r9
 8005dea:	4659      	mov	r1, fp
 8005dec:	4628      	mov	r0, r5
 8005dee:	47b0      	blx	r6
 8005df0:	3001      	adds	r0, #1
 8005df2:	f43f aefc 	beq.w	8005bee <_printf_float+0xae>
 8005df6:	f108 0801 	add.w	r8, r8, #1
 8005dfa:	e7ee      	b.n	8005dda <_printf_float+0x29a>
 8005dfc:	9a0e      	ldr	r2, [sp, #56]	; 0x38
 8005dfe:	6da3      	ldr	r3, [r4, #88]	; 0x58
 8005e00:	429a      	cmp	r2, r3
 8005e02:	bfa8      	it	ge
 8005e04:	461a      	movge	r2, r3
 8005e06:	2a00      	cmp	r2, #0
 8005e08:	4690      	mov	r8, r2
 8005e0a:	dd07      	ble.n	8005e1c <_printf_float+0x2dc>
 8005e0c:	4613      	mov	r3, r2
 8005e0e:	4659      	mov	r1, fp
 8005e10:	463a      	mov	r2, r7
 8005e12:	4628      	mov	r0, r5
 8005e14:	47b0      	blx	r6
 8005e16:	3001      	adds	r0, #1
 8005e18:	f43f aee9 	beq.w	8005bee <_printf_float+0xae>
 8005e1c:	f104 031a 	add.w	r3, r4, #26
 8005e20:	f04f 0a00 	mov.w	sl, #0
 8005e24:	ea28 78e8 	bic.w	r8, r8, r8, asr #31
 8005e28:	930b      	str	r3, [sp, #44]	; 0x2c
 8005e2a:	e015      	b.n	8005e58 <_printf_float+0x318>
 8005e2c:	7fefffff 	.word	0x7fefffff
 8005e30:	08008600 	.word	0x08008600
 8005e34:	080085fc 	.word	0x080085fc
 8005e38:	08008608 	.word	0x08008608
 8005e3c:	08008604 	.word	0x08008604
 8005e40:	0800860c 	.word	0x0800860c
 8005e44:	2301      	movs	r3, #1
 8005e46:	9a0b      	ldr	r2, [sp, #44]	; 0x2c
 8005e48:	4659      	mov	r1, fp
 8005e4a:	4628      	mov	r0, r5
 8005e4c:	47b0      	blx	r6
 8005e4e:	3001      	adds	r0, #1
 8005e50:	f43f aecd 	beq.w	8005bee <_printf_float+0xae>
 8005e54:	f10a 0a01 	add.w	sl, sl, #1
 8005e58:	f8d4 9058 	ldr.w	r9, [r4, #88]	; 0x58
 8005e5c:	eba9 0308 	sub.w	r3, r9, r8
 8005e60:	4553      	cmp	r3, sl
 8005e62:	dcef      	bgt.n	8005e44 <_printf_float+0x304>
 8005e64:	e9dd 230d 	ldrd	r2, r3, [sp, #52]	; 0x34
 8005e68:	429a      	cmp	r2, r3
 8005e6a:	444f      	add	r7, r9
 8005e6c:	db14      	blt.n	8005e98 <_printf_float+0x358>
 8005e6e:	6823      	ldr	r3, [r4, #0]
 8005e70:	07da      	lsls	r2, r3, #31
 8005e72:	d411      	bmi.n	8005e98 <_printf_float+0x358>
 8005e74:	9b0e      	ldr	r3, [sp, #56]	; 0x38
 8005e76:	990d      	ldr	r1, [sp, #52]	; 0x34
 8005e78:	eba3 0209 	sub.w	r2, r3, r9
 8005e7c:	eba3 0901 	sub.w	r9, r3, r1
 8005e80:	4591      	cmp	r9, r2
 8005e82:	bfa8      	it	ge
 8005e84:	4691      	movge	r9, r2
 8005e86:	f1b9 0f00 	cmp.w	r9, #0
 8005e8a:	dc0d      	bgt.n	8005ea8 <_printf_float+0x368>
 8005e8c:	2700      	movs	r7, #0
 8005e8e:	ea29 79e9 	bic.w	r9, r9, r9, asr #31
 8005e92:	f104 081a 	add.w	r8, r4, #26
 8005e96:	e018      	b.n	8005eca <_printf_float+0x38a>
 8005e98:	e9dd 2309 	ldrd	r2, r3, [sp, #36]	; 0x24
 8005e9c:	4659      	mov	r1, fp
 8005e9e:	4628      	mov	r0, r5
 8005ea0:	47b0      	blx	r6
 8005ea2:	3001      	adds	r0, #1
 8005ea4:	d1e6      	bne.n	8005e74 <_printf_float+0x334>
 8005ea6:	e6a2      	b.n	8005bee <_printf_float+0xae>
 8005ea8:	464b      	mov	r3, r9
 8005eaa:	463a      	mov	r2, r7
 8005eac:	4659      	mov	r1, fp
 8005eae:	4628      	mov	r0, r5
 8005eb0:	47b0      	blx	r6
 8005eb2:	3001      	adds	r0, #1
 8005eb4:	d1ea      	bne.n	8005e8c <_printf_float+0x34c>
 8005eb6:	e69a      	b.n	8005bee <_printf_float+0xae>
 8005eb8:	2301      	movs	r3, #1
 8005eba:	4642      	mov	r2, r8
 8005ebc:	4659      	mov	r1, fp
 8005ebe:	4628      	mov	r0, r5
 8005ec0:	47b0      	blx	r6
 8005ec2:	3001      	adds	r0, #1
 8005ec4:	f43f ae93 	beq.w	8005bee <_printf_float+0xae>
 8005ec8:	3701      	adds	r7, #1
 8005eca:	e9dd 230d 	ldrd	r2, r3, [sp, #52]	; 0x34
 8005ece:	1a9b      	subs	r3, r3, r2
 8005ed0:	eba3 0309 	sub.w	r3, r3, r9
 8005ed4:	42bb      	cmp	r3, r7
 8005ed6:	dcef      	bgt.n	8005eb8 <_printf_float+0x378>
 8005ed8:	e74d      	b.n	8005d76 <_printf_float+0x236>
 8005eda:	9a0e      	ldr	r2, [sp, #56]	; 0x38
 8005edc:	2a01      	cmp	r2, #1
 8005ede:	dc01      	bgt.n	8005ee4 <_printf_float+0x3a4>
 8005ee0:	07db      	lsls	r3, r3, #31
 8005ee2:	d538      	bpl.n	8005f56 <_printf_float+0x416>
 8005ee4:	2301      	movs	r3, #1
 8005ee6:	463a      	mov	r2, r7
 8005ee8:	4659      	mov	r1, fp
 8005eea:	4628      	mov	r0, r5
 8005eec:	47b0      	blx	r6
 8005eee:	3001      	adds	r0, #1
 8005ef0:	f43f ae7d 	beq.w	8005bee <_printf_float+0xae>
 8005ef4:	e9dd 2309 	ldrd	r2, r3, [sp, #36]	; 0x24
 8005ef8:	4659      	mov	r1, fp
 8005efa:	4628      	mov	r0, r5
 8005efc:	47b0      	blx	r6
 8005efe:	3001      	adds	r0, #1
 8005f00:	f107 0701 	add.w	r7, r7, #1
 8005f04:	f43f ae73 	beq.w	8005bee <_printf_float+0xae>
 8005f08:	e9d4 0112 	ldrd	r0, r1, [r4, #72]	; 0x48
 8005f0c:	9b0e      	ldr	r3, [sp, #56]	; 0x38
 8005f0e:	2200      	movs	r2, #0
 8005f10:	f103 38ff 	add.w	r8, r3, #4294967295
 8005f14:	2300      	movs	r3, #0
 8005f16:	f7fa fda7 	bl	8000a68 <__aeabi_dcmpeq>
 8005f1a:	b9c0      	cbnz	r0, 8005f4e <_printf_float+0x40e>
 8005f1c:	4643      	mov	r3, r8
 8005f1e:	463a      	mov	r2, r7
 8005f20:	4659      	mov	r1, fp
 8005f22:	4628      	mov	r0, r5
 8005f24:	47b0      	blx	r6
 8005f26:	3001      	adds	r0, #1
 8005f28:	d10d      	bne.n	8005f46 <_printf_float+0x406>
 8005f2a:	e660      	b.n	8005bee <_printf_float+0xae>
 8005f2c:	2301      	movs	r3, #1
 8005f2e:	4642      	mov	r2, r8
 8005f30:	4659      	mov	r1, fp
 8005f32:	4628      	mov	r0, r5
 8005f34:	47b0      	blx	r6
 8005f36:	3001      	adds	r0, #1
 8005f38:	f43f ae59 	beq.w	8005bee <_printf_float+0xae>
 8005f3c:	3701      	adds	r7, #1
 8005f3e:	9b0e      	ldr	r3, [sp, #56]	; 0x38
 8005f40:	3b01      	subs	r3, #1
 8005f42:	42bb      	cmp	r3, r7
 8005f44:	dcf2      	bgt.n	8005f2c <_printf_float+0x3ec>
 8005f46:	464b      	mov	r3, r9
 8005f48:	f104 0250 	add.w	r2, r4, #80	; 0x50
 8005f4c:	e6e4      	b.n	8005d18 <_printf_float+0x1d8>
 8005f4e:	2700      	movs	r7, #0
 8005f50:	f104 081a 	add.w	r8, r4, #26
 8005f54:	e7f3      	b.n	8005f3e <_printf_float+0x3fe>
 8005f56:	2301      	movs	r3, #1
 8005f58:	e7e1      	b.n	8005f1e <_printf_float+0x3de>
 8005f5a:	2301      	movs	r3, #1
 8005f5c:	4642      	mov	r2, r8
 8005f5e:	4659      	mov	r1, fp
 8005f60:	4628      	mov	r0, r5
 8005f62:	47b0      	blx	r6
 8005f64:	3001      	adds	r0, #1
 8005f66:	f43f ae42 	beq.w	8005bee <_printf_float+0xae>
 8005f6a:	3701      	adds	r7, #1
 8005f6c:	68e3      	ldr	r3, [r4, #12]
 8005f6e:	9a0f      	ldr	r2, [sp, #60]	; 0x3c
 8005f70:	1a9b      	subs	r3, r3, r2
 8005f72:	42bb      	cmp	r3, r7
 8005f74:	dcf1      	bgt.n	8005f5a <_printf_float+0x41a>
 8005f76:	e702      	b.n	8005d7e <_printf_float+0x23e>
 8005f78:	2700      	movs	r7, #0
 8005f7a:	f104 0819 	add.w	r8, r4, #25
 8005f7e:	e7f5      	b.n	8005f6c <_printf_float+0x42c>
 8005f80:	2b00      	cmp	r3, #0
 8005f82:	f43f ae94 	beq.w	8005cae <_printf_float+0x16e>
 8005f86:	f04f 0c00 	mov.w	ip, #0
 8005f8a:	e9cd 1c05 	strd	r1, ip, [sp, #20]
 8005f8e:	f10d 0133 	add.w	r1, sp, #51	; 0x33
 8005f92:	6022      	str	r2, [r4, #0]
 8005f94:	e9cd 0803 	strd	r0, r8, [sp, #12]
 8005f98:	e9cd 2101 	strd	r2, r1, [sp, #4]
 8005f9c:	9300      	str	r3, [sp, #0]
 8005f9e:	463a      	mov	r2, r7
 8005fa0:	464b      	mov	r3, r9
 8005fa2:	4628      	mov	r0, r5
 8005fa4:	f7ff fd3a 	bl	8005a1c <__cvt>
 8005fa8:	4607      	mov	r7, r0
 8005faa:	e64f      	b.n	8005c4c <_printf_float+0x10c>

08005fac <_printf_common>:
 8005fac:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
 8005fb0:	4691      	mov	r9, r2
 8005fb2:	461f      	mov	r7, r3
 8005fb4:	688a      	ldr	r2, [r1, #8]
 8005fb6:	690b      	ldr	r3, [r1, #16]
 8005fb8:	4606      	mov	r6, r0
 8005fba:	4293      	cmp	r3, r2
 8005fbc:	bfb8      	it	lt
 8005fbe:	4613      	movlt	r3, r2
 8005fc0:	f8c9 3000 	str.w	r3, [r9]
 8005fc4:	f891 2043 	ldrb.w	r2, [r1, #67]	; 0x43
 8005fc8:	460c      	mov	r4, r1
 8005fca:	f8dd 8020 	ldr.w	r8, [sp, #32]
 8005fce:	b112      	cbz	r2, 8005fd6 <_printf_common+0x2a>
 8005fd0:	3301      	adds	r3, #1
 8005fd2:	f8c9 3000 	str.w	r3, [r9]
 8005fd6:	6823      	ldr	r3, [r4, #0]
 8005fd8:	0699      	lsls	r1, r3, #26
 8005fda:	bf42      	ittt	mi
 8005fdc:	f8d9 3000 	ldrmi.w	r3, [r9]
 8005fe0:	3302      	addmi	r3, #2
 8005fe2:	f8c9 3000 	strmi.w	r3, [r9]
 8005fe6:	6825      	ldr	r5, [r4, #0]
 8005fe8:	f015 0506 	ands.w	r5, r5, #6
 8005fec:	d107      	bne.n	8005ffe <_printf_common+0x52>
 8005fee:	f104 0a19 	add.w	sl, r4, #25
 8005ff2:	68e3      	ldr	r3, [r4, #12]
 8005ff4:	f8d9 2000 	ldr.w	r2, [r9]
 8005ff8:	1a9b      	subs	r3, r3, r2
 8005ffa:	42ab      	cmp	r3, r5
 8005ffc:	dc29      	bgt.n	8006052 <_printf_common+0xa6>
 8005ffe:	f894 3043 	ldrb.w	r3, [r4, #67]	; 0x43
 8006002:	6822      	ldr	r2, [r4, #0]
 8006004:	3300      	adds	r3, #0
 8006006:	bf18      	it	ne
 8006008:	2301      	movne	r3, #1
 800600a:	0692      	lsls	r2, r2, #26
 800600c:	d42e      	bmi.n	800606c <_printf_common+0xc0>
 800600e:	f104 0243 	add.w	r2, r4, #67	; 0x43
 8006012:	4639      	mov	r1, r7
 8006014:	4630      	mov	r0, r6
 8006016:	47c0      	blx	r8
 8006018:	3001      	adds	r0, #1
 800601a:	d021      	beq.n	8006060 <_printf_common+0xb4>
 800601c:	6823      	ldr	r3, [r4, #0]
 800601e:	68e5      	ldr	r5, [r4, #12]
 8006020:	f003 0306 	and.w	r3, r3, #6
 8006024:	2b04      	cmp	r3, #4
 8006026:	bf18      	it	ne
 8006028:	2500      	movne	r5, #0
 800602a:	f8d9 2000 	ldr.w	r2, [r9]
 800602e:	f04f 0900 	mov.w	r9, #0
 8006032:	bf08      	it	eq
 8006034:	1aad      	subeq	r5, r5, r2
 8006036:	68a3      	ldr	r3, [r4, #8]
 8006038:	6922      	ldr	r2, [r4, #16]
 800603a:	bf08      	it	eq
 800603c:	ea25 75e5 	biceq.w	r5, r5, r5, asr #31
 8006040:	4293      	cmp	r3, r2
 8006042:	bfc4      	itt	gt
 8006044:	1a9b      	subgt	r3, r3, r2
 8006046:	18ed      	addgt	r5, r5, r3
 8006048:	341a      	adds	r4, #26
 800604a:	454d      	cmp	r5, r9
 800604c:	d11a      	bne.n	8006084 <_printf_common+0xd8>
 800604e:	2000      	movs	r0, #0
 8006050:	e008      	b.n	8006064 <_printf_common+0xb8>
 8006052:	2301      	movs	r3, #1
 8006054:	4652      	mov	r2, sl
 8006056:	4639      	mov	r1, r7
 8006058:	4630      	mov	r0, r6
 800605a:	47c0      	blx	r8
 800605c:	3001      	adds	r0, #1
 800605e:	d103      	bne.n	8006068 <_printf_common+0xbc>
 8006060:	f04f 30ff 	mov.w	r0, #4294967295
 8006064:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 8006068:	3501      	adds	r5, #1
 800606a:	e7c2      	b.n	8005ff2 <_printf_common+0x46>
 800606c:	2030      	movs	r0, #48	; 0x30
 800606e:	18e1      	adds	r1, r4, r3
 8006070:	f881 0043 	strb.w	r0, [r1, #67]	; 0x43
 8006074:	1c5a      	adds	r2, r3, #1
 8006076:	f894 1045 	ldrb.w	r1, [r4, #69]	; 0x45
 800607a:	4422      	add	r2, r4
 800607c:	3302      	adds	r3, #2
 800607e:	f882 1043 	strb.w	r1, [r2, #67]	; 0x43
 8006082:	e7c4      	b.n	800600e <_printf_common+0x62>
 8006084:	2301      	movs	r3, #1
 8006086:	4622      	mov	r2, r4
 8006088:	4639      	mov	r1, r7
 800608a:	4630      	mov	r0, r6
 800608c:	47c0      	blx	r8
 800608e:	3001      	adds	r0, #1
 8006090:	d0e6      	beq.n	8006060 <_printf_common+0xb4>
 8006092:	f109 0901 	add.w	r9, r9, #1
 8006096:	e7d8      	b.n	800604a <_printf_common+0x9e>

08006098 <_printf_i>:
 8006098:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr}
 800609c:	f101 0c43 	add.w	ip, r1, #67	; 0x43
 80060a0:	460c      	mov	r4, r1
 80060a2:	7e09      	ldrb	r1, [r1, #24]
 80060a4:	b085      	sub	sp, #20
 80060a6:	296e      	cmp	r1, #110	; 0x6e
 80060a8:	4617      	mov	r7, r2
 80060aa:	4606      	mov	r6, r0
 80060ac:	4698      	mov	r8, r3
 80060ae:	9a0c      	ldr	r2, [sp, #48]	; 0x30
 80060b0:	f000 80b3 	beq.w	800621a <_printf_i+0x182>
 80060b4:	d822      	bhi.n	80060fc <_printf_i+0x64>
 80060b6:	2963      	cmp	r1, #99	; 0x63
 80060b8:	d036      	beq.n	8006128 <_printf_i+0x90>
 80060ba:	d80a      	bhi.n	80060d2 <_printf_i+0x3a>
 80060bc:	2900      	cmp	r1, #0
 80060be:	f000 80b9 	beq.w	8006234 <_printf_i+0x19c>
 80060c2:	2958      	cmp	r1, #88	; 0x58
 80060c4:	f000 8083 	beq.w	80061ce <_printf_i+0x136>
 80060c8:	f104 0542 	add.w	r5, r4, #66	; 0x42
 80060cc:	f884 1042 	strb.w	r1, [r4, #66]	; 0x42
 80060d0:	e032      	b.n	8006138 <_printf_i+0xa0>
 80060d2:	2964      	cmp	r1, #100	; 0x64
 80060d4:	d001      	beq.n	80060da <_printf_i+0x42>
 80060d6:	2969      	cmp	r1, #105	; 0x69
 80060d8:	d1f6      	bne.n	80060c8 <_printf_i+0x30>
 80060da:	6820      	ldr	r0, [r4, #0]
 80060dc:	6813      	ldr	r3, [r2, #0]
 80060de:	0605      	lsls	r5, r0, #24
 80060e0:	f103 0104 	add.w	r1, r3, #4
 80060e4:	d52a      	bpl.n	800613c <_printf_i+0xa4>
 80060e6:	681b      	ldr	r3, [r3, #0]
 80060e8:	6011      	str	r1, [r2, #0]
 80060ea:	2b00      	cmp	r3, #0
 80060ec:	da03      	bge.n	80060f6 <_printf_i+0x5e>
 80060ee:	222d      	movs	r2, #45	; 0x2d
 80060f0:	425b      	negs	r3, r3
 80060f2:	f884 2043 	strb.w	r2, [r4, #67]	; 0x43
 80060f6:	486f      	ldr	r0, [pc, #444]	; (80062b4 <_printf_i+0x21c>)
 80060f8:	220a      	movs	r2, #10
 80060fa:	e039      	b.n	8006170 <_printf_i+0xd8>
 80060fc:	2973      	cmp	r1, #115	; 0x73
 80060fe:	f000 809d 	beq.w	800623c <_printf_i+0x1a4>
 8006102:	d808      	bhi.n	8006116 <_printf_i+0x7e>
 8006104:	296f      	cmp	r1, #111	; 0x6f
 8006106:	d020      	beq.n	800614a <_printf_i+0xb2>
 8006108:	2970      	cmp	r1, #112	; 0x70
 800610a:	d1dd      	bne.n	80060c8 <_printf_i+0x30>
 800610c:	6823      	ldr	r3, [r4, #0]
 800610e:	f043 0320 	orr.w	r3, r3, #32
 8006112:	6023      	str	r3, [r4, #0]
 8006114:	e003      	b.n	800611e <_printf_i+0x86>
 8006116:	2975      	cmp	r1, #117	; 0x75
 8006118:	d017      	beq.n	800614a <_printf_i+0xb2>
 800611a:	2978      	cmp	r1, #120	; 0x78
 800611c:	d1d4      	bne.n	80060c8 <_printf_i+0x30>
 800611e:	2378      	movs	r3, #120	; 0x78
 8006120:	4865      	ldr	r0, [pc, #404]	; (80062b8 <_printf_i+0x220>)
 8006122:	f884 3045 	strb.w	r3, [r4, #69]	; 0x45
 8006126:	e055      	b.n	80061d4 <_printf_i+0x13c>
 8006128:	6813      	ldr	r3, [r2, #0]
 800612a:	f104 0542 	add.w	r5, r4, #66	; 0x42
 800612e:	1d19      	adds	r1, r3, #4
 8006130:	681b      	ldr	r3, [r3, #0]
 8006132:	6011      	str	r1, [r2, #0]
 8006134:	f884 3042 	strb.w	r3, [r4, #66]	; 0x42
 8006138:	2301      	movs	r3, #1
 800613a:	e08c      	b.n	8006256 <_printf_i+0x1be>
 800613c:	681b      	ldr	r3, [r3, #0]
 800613e:	f010 0f40 	tst.w	r0, #64	; 0x40
 8006142:	6011      	str	r1, [r2, #0]
 8006144:	bf18      	it	ne
 8006146:	b21b      	sxthne	r3, r3
 8006148:	e7cf      	b.n	80060ea <_printf_i+0x52>
 800614a:	6813      	ldr	r3, [r2, #0]
 800614c:	6825      	ldr	r5, [r4, #0]
 800614e:	1d18      	adds	r0, r3, #4
 8006150:	6010      	str	r0, [r2, #0]
 8006152:	0628      	lsls	r0, r5, #24
 8006154:	d501      	bpl.n	800615a <_printf_i+0xc2>
 8006156:	681b      	ldr	r3, [r3, #0]
 8006158:	e002      	b.n	8006160 <_printf_i+0xc8>
 800615a:	0668      	lsls	r0, r5, #25
 800615c:	d5fb      	bpl.n	8006156 <_printf_i+0xbe>
 800615e:	881b      	ldrh	r3, [r3, #0]
 8006160:	296f      	cmp	r1, #111	; 0x6f
 8006162:	bf14      	ite	ne
 8006164:	220a      	movne	r2, #10
 8006166:	2208      	moveq	r2, #8
 8006168:	4852      	ldr	r0, [pc, #328]	; (80062b4 <_printf_i+0x21c>)
 800616a:	2100      	movs	r1, #0
 800616c:	f884 1043 	strb.w	r1, [r4, #67]	; 0x43
 8006170:	6865      	ldr	r5, [r4, #4]
 8006172:	2d00      	cmp	r5, #0
 8006174:	60a5      	str	r5, [r4, #8]
 8006176:	f2c0 8095 	blt.w	80062a4 <_printf_i+0x20c>
 800617a:	6821      	ldr	r1, [r4, #0]
 800617c:	f021 0104 	bic.w	r1, r1, #4
 8006180:	6021      	str	r1, [r4, #0]
 8006182:	2b00      	cmp	r3, #0
 8006184:	d13d      	bne.n	8006202 <_printf_i+0x16a>
 8006186:	2d00      	cmp	r5, #0
 8006188:	f040 808e 	bne.w	80062a8 <_printf_i+0x210>
 800618c:	4665      	mov	r5, ip
 800618e:	2a08      	cmp	r2, #8
 8006190:	d10b      	bne.n	80061aa <_printf_i+0x112>
 8006192:	6823      	ldr	r3, [r4, #0]
 8006194:	07db      	lsls	r3, r3, #31
 8006196:	d508      	bpl.n	80061aa <_printf_i+0x112>
 8006198:	6923      	ldr	r3, [r4, #16]
 800619a:	6862      	ldr	r2, [r4, #4]
 800619c:	429a      	cmp	r2, r3
 800619e:	bfde      	ittt	le
 80061a0:	2330      	movle	r3, #48	; 0x30
 80061a2:	f805 3c01 	strble.w	r3, [r5, #-1]
 80061a6:	f105 35ff 	addle.w	r5, r5, #4294967295
 80061aa:	ebac 0305 	sub.w	r3, ip, r5
 80061ae:	6123      	str	r3, [r4, #16]
 80061b0:	f8cd 8000 	str.w	r8, [sp]
 80061b4:	463b      	mov	r3, r7
 80061b6:	aa03      	add	r2, sp, #12
 80061b8:	4621      	mov	r1, r4
 80061ba:	4630      	mov	r0, r6
 80061bc:	f7ff fef6 	bl	8005fac <_printf_common>
 80061c0:	3001      	adds	r0, #1
 80061c2:	d14d      	bne.n	8006260 <_printf_i+0x1c8>
 80061c4:	f04f 30ff 	mov.w	r0, #4294967295
 80061c8:	b005      	add	sp, #20
 80061ca:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
 80061ce:	4839      	ldr	r0, [pc, #228]	; (80062b4 <_printf_i+0x21c>)
 80061d0:	f884 1045 	strb.w	r1, [r4, #69]	; 0x45
 80061d4:	6813      	ldr	r3, [r2, #0]
 80061d6:	6821      	ldr	r1, [r4, #0]
 80061d8:	1d1d      	adds	r5, r3, #4
 80061da:	681b      	ldr	r3, [r3, #0]
 80061dc:	6015      	str	r5, [r2, #0]
 80061de:	060a      	lsls	r2, r1, #24
 80061e0:	d50b      	bpl.n	80061fa <_printf_i+0x162>
 80061e2:	07ca      	lsls	r2, r1, #31
 80061e4:	bf44      	itt	mi
 80061e6:	f041 0120 	orrmi.w	r1, r1, #32
 80061ea:	6021      	strmi	r1, [r4, #0]
 80061ec:	b91b      	cbnz	r3, 80061f6 <_printf_i+0x15e>
 80061ee:	6822      	ldr	r2, [r4, #0]
 80061f0:	f022 0220 	bic.w	r2, r2, #32
 80061f4:	6022      	str	r2, [r4, #0]
 80061f6:	2210      	movs	r2, #16
 80061f8:	e7b7      	b.n	800616a <_printf_i+0xd2>
 80061fa:	064d      	lsls	r5, r1, #25
 80061fc:	bf48      	it	mi
 80061fe:	b29b      	uxthmi	r3, r3
 8006200:	e7ef      	b.n	80061e2 <_printf_i+0x14a>
 8006202:	4665      	mov	r5, ip
 8006204:	fbb3 f1f2 	udiv	r1, r3, r2
 8006208:	fb02 3311 	mls	r3, r2, r1, r3
 800620c:	5cc3      	ldrb	r3, [r0, r3]
 800620e:	f805 3d01 	strb.w	r3, [r5, #-1]!
 8006212:	460b      	mov	r3, r1
 8006214:	2900      	cmp	r1, #0
 8006216:	d1f5      	bne.n	8006204 <_printf_i+0x16c>
 8006218:	e7b9      	b.n	800618e <_printf_i+0xf6>
 800621a:	6813      	ldr	r3, [r2, #0]
 800621c:	6825      	ldr	r5, [r4, #0]
 800621e:	1d18      	adds	r0, r3, #4
 8006220:	6961      	ldr	r1, [r4, #20]
 8006222:	6010      	str	r0, [r2, #0]
 8006224:	0628      	lsls	r0, r5, #24
 8006226:	681b      	ldr	r3, [r3, #0]
 8006228:	d501      	bpl.n	800622e <_printf_i+0x196>
 800622a:	6019      	str	r1, [r3, #0]
 800622c:	e002      	b.n	8006234 <_printf_i+0x19c>
 800622e:	066a      	lsls	r2, r5, #25
 8006230:	d5fb      	bpl.n	800622a <_printf_i+0x192>
 8006232:	8019      	strh	r1, [r3, #0]
 8006234:	2300      	movs	r3, #0
 8006236:	4665      	mov	r5, ip
 8006238:	6123      	str	r3, [r4, #16]
 800623a:	e7b9      	b.n	80061b0 <_printf_i+0x118>
 800623c:	6813      	ldr	r3, [r2, #0]
 800623e:	1d19      	adds	r1, r3, #4
 8006240:	6011      	str	r1, [r2, #0]
 8006242:	681d      	ldr	r5, [r3, #0]
 8006244:	6862      	ldr	r2, [r4, #4]
 8006246:	2100      	movs	r1, #0
 8006248:	4628      	mov	r0, r5
 800624a:	f001 fa61 	bl	8007710 <memchr>
 800624e:	b108      	cbz	r0, 8006254 <_printf_i+0x1bc>
 8006250:	1b40      	subs	r0, r0, r5
 8006252:	6060      	str	r0, [r4, #4]
 8006254:	6863      	ldr	r3, [r4, #4]
 8006256:	6123      	str	r3, [r4, #16]
 8006258:	2300      	movs	r3, #0
 800625a:	f884 3043 	strb.w	r3, [r4, #67]	; 0x43
 800625e:	e7a7      	b.n	80061b0 <_printf_i+0x118>
 8006260:	6923      	ldr	r3, [r4, #16]
 8006262:	462a      	mov	r2, r5
 8006264:	4639      	mov	r1, r7
 8006266:	4630      	mov	r0, r6
 8006268:	47c0      	blx	r8
 800626a:	3001      	adds	r0, #1
 800626c:	d0aa      	beq.n	80061c4 <_printf_i+0x12c>
 800626e:	6823      	ldr	r3, [r4, #0]
 8006270:	079b      	lsls	r3, r3, #30
 8006272:	d413      	bmi.n	800629c <_printf_i+0x204>
 8006274:	68e0      	ldr	r0, [r4, #12]
 8006276:	9b03      	ldr	r3, [sp, #12]
 8006278:	4298      	cmp	r0, r3
 800627a:	bfb8      	it	lt
 800627c:	4618      	movlt	r0, r3
 800627e:	e7a3      	b.n	80061c8 <_printf_i+0x130>
 8006280:	2301      	movs	r3, #1
 8006282:	464a      	mov	r2, r9
 8006284:	4639      	mov	r1, r7
 8006286:	4630      	mov	r0, r6
 8006288:	47c0      	blx	r8
 800628a:	3001      	adds	r0, #1
 800628c:	d09a      	beq.n	80061c4 <_printf_i+0x12c>
 800628e:	3501      	adds	r5, #1
 8006290:	68e3      	ldr	r3, [r4, #12]
 8006292:	9a03      	ldr	r2, [sp, #12]
 8006294:	1a9b      	subs	r3, r3, r2
 8006296:	42ab      	cmp	r3, r5
 8006298:	dcf2      	bgt.n	8006280 <_printf_i+0x1e8>
 800629a:	e7eb      	b.n	8006274 <_printf_i+0x1dc>
 800629c:	2500      	movs	r5, #0
 800629e:	f104 0919 	add.w	r9, r4, #25
 80062a2:	e7f5      	b.n	8006290 <_printf_i+0x1f8>
 80062a4:	2b00      	cmp	r3, #0
 80062a6:	d1ac      	bne.n	8006202 <_printf_i+0x16a>
 80062a8:	7803      	ldrb	r3, [r0, #0]
 80062aa:	f104 0542 	add.w	r5, r4, #66	; 0x42
 80062ae:	f884 3042 	strb.w	r3, [r4, #66]	; 0x42
 80062b2:	e76c      	b.n	800618e <_printf_i+0xf6>
 80062b4:	0800860e 	.word	0x0800860e
 80062b8:	0800861f 	.word	0x0800861f

080062bc <iprintf>:
 80062bc:	b40f      	push	{r0, r1, r2, r3}
 80062be:	4b0a      	ldr	r3, [pc, #40]	; (80062e8 <iprintf+0x2c>)
 80062c0:	b513      	push	{r0, r1, r4, lr}
 80062c2:	681c      	ldr	r4, [r3, #0]
 80062c4:	b124      	cbz	r4, 80062d0 <iprintf+0x14>
 80062c6:	69a3      	ldr	r3, [r4, #24]
 80062c8:	b913      	cbnz	r3, 80062d0 <iprintf+0x14>
 80062ca:	4620      	mov	r0, r4
 80062cc:	f001 f91c 	bl	8007508 <__sinit>
 80062d0:	ab05      	add	r3, sp, #20
 80062d2:	9a04      	ldr	r2, [sp, #16]
 80062d4:	68a1      	ldr	r1, [r4, #8]
 80062d6:	4620      	mov	r0, r4
 80062d8:	9301      	str	r3, [sp, #4]
 80062da:	f001 fdeb 	bl	8007eb4 <_vfiprintf_r>
 80062de:	b002      	add	sp, #8
 80062e0:	e8bd 4010 	ldmia.w	sp!, {r4, lr}
 80062e4:	b004      	add	sp, #16
 80062e6:	4770      	bx	lr
 80062e8:	2000000c 	.word	0x2000000c

080062ec <_puts_r>:
 80062ec:	b570      	push	{r4, r5, r6, lr}
 80062ee:	460e      	mov	r6, r1
 80062f0:	4605      	mov	r5, r0
 80062f2:	b118      	cbz	r0, 80062fc <_puts_r+0x10>
 80062f4:	6983      	ldr	r3, [r0, #24]
 80062f6:	b90b      	cbnz	r3, 80062fc <_puts_r+0x10>
 80062f8:	f001 f906 	bl	8007508 <__sinit>
 80062fc:	69ab      	ldr	r3, [r5, #24]
 80062fe:	68ac      	ldr	r4, [r5, #8]
 8006300:	b913      	cbnz	r3, 8006308 <_puts_r+0x1c>
 8006302:	4628      	mov	r0, r5
 8006304:	f001 f900 	bl	8007508 <__sinit>
 8006308:	4b23      	ldr	r3, [pc, #140]	; (8006398 <_puts_r+0xac>)
 800630a:	429c      	cmp	r4, r3
 800630c:	d117      	bne.n	800633e <_puts_r+0x52>
 800630e:	686c      	ldr	r4, [r5, #4]
 8006310:	89a3      	ldrh	r3, [r4, #12]
 8006312:	071b      	lsls	r3, r3, #28
 8006314:	d51d      	bpl.n	8006352 <_puts_r+0x66>
 8006316:	6923      	ldr	r3, [r4, #16]
 8006318:	b1db      	cbz	r3, 8006352 <_puts_r+0x66>
 800631a:	3e01      	subs	r6, #1
 800631c:	68a3      	ldr	r3, [r4, #8]
 800631e:	f816 1f01 	ldrb.w	r1, [r6, #1]!
 8006322:	3b01      	subs	r3, #1
 8006324:	60a3      	str	r3, [r4, #8]
 8006326:	b9e9      	cbnz	r1, 8006364 <_puts_r+0x78>
 8006328:	2b00      	cmp	r3, #0
 800632a:	da2e      	bge.n	800638a <_puts_r+0x9e>
 800632c:	4622      	mov	r2, r4
 800632e:	210a      	movs	r1, #10
 8006330:	4628      	mov	r0, r5
 8006332:	f000 f8f5 	bl	8006520 <__swbuf_r>
 8006336:	3001      	adds	r0, #1
 8006338:	d011      	beq.n	800635e <_puts_r+0x72>
 800633a:	200a      	movs	r0, #10
 800633c:	e011      	b.n	8006362 <_puts_r+0x76>
 800633e:	4b17      	ldr	r3, [pc, #92]	; (800639c <_puts_r+0xb0>)
 8006340:	429c      	cmp	r4, r3
 8006342:	d101      	bne.n	8006348 <_puts_r+0x5c>
 8006344:	68ac      	ldr	r4, [r5, #8]
 8006346:	e7e3      	b.n	8006310 <_puts_r+0x24>
 8006348:	4b15      	ldr	r3, [pc, #84]	; (80063a0 <_puts_r+0xb4>)
 800634a:	429c      	cmp	r4, r3
 800634c:	bf08      	it	eq
 800634e:	68ec      	ldreq	r4, [r5, #12]
 8006350:	e7de      	b.n	8006310 <_puts_r+0x24>
 8006352:	4621      	mov	r1, r4
 8006354:	4628      	mov	r0, r5
 8006356:	f000 f935 	bl	80065c4 <__swsetup_r>
 800635a:	2800      	cmp	r0, #0
 800635c:	d0dd      	beq.n	800631a <_puts_r+0x2e>
 800635e:	f04f 30ff 	mov.w	r0, #4294967295
 8006362:	bd70      	pop	{r4, r5, r6, pc}
 8006364:	2b00      	cmp	r3, #0
 8006366:	da04      	bge.n	8006372 <_puts_r+0x86>
 8006368:	69a2      	ldr	r2, [r4, #24]
 800636a:	429a      	cmp	r2, r3
 800636c:	dc06      	bgt.n	800637c <_puts_r+0x90>
 800636e:	290a      	cmp	r1, #10
 8006370:	d004      	beq.n	800637c <_puts_r+0x90>
 8006372:	6823      	ldr	r3, [r4, #0]
 8006374:	1c5a      	adds	r2, r3, #1
 8006376:	6022      	str	r2, [r4, #0]
 8006378:	7019      	strb	r1, [r3, #0]
 800637a:	e7cf      	b.n	800631c <_puts_r+0x30>
 800637c:	4622      	mov	r2, r4
 800637e:	4628      	mov	r0, r5
 8006380:	f000 f8ce 	bl	8006520 <__swbuf_r>
 8006384:	3001      	adds	r0, #1
 8006386:	d1c9      	bne.n	800631c <_puts_r+0x30>
 8006388:	e7e9      	b.n	800635e <_puts_r+0x72>
 800638a:	200a      	movs	r0, #10
 800638c:	6823      	ldr	r3, [r4, #0]
 800638e:	1c5a      	adds	r2, r3, #1
 8006390:	6022      	str	r2, [r4, #0]
 8006392:	7018      	strb	r0, [r3, #0]
 8006394:	e7e5      	b.n	8006362 <_puts_r+0x76>
 8006396:	bf00      	nop
 8006398:	08008660 	.word	0x08008660
 800639c:	08008680 	.word	0x08008680
 80063a0:	08008640 	.word	0x08008640

080063a4 <puts>:
 80063a4:	4b02      	ldr	r3, [pc, #8]	; (80063b0 <puts+0xc>)
 80063a6:	4601      	mov	r1, r0
 80063a8:	6818      	ldr	r0, [r3, #0]
 80063aa:	f7ff bf9f 	b.w	80062ec <_puts_r>
 80063ae:	bf00      	nop
 80063b0:	2000000c 	.word	0x2000000c

080063b4 <setbuf>:
 80063b4:	2900      	cmp	r1, #0
 80063b6:	f44f 6380 	mov.w	r3, #1024	; 0x400
 80063ba:	bf0c      	ite	eq
 80063bc:	2202      	moveq	r2, #2
 80063be:	2200      	movne	r2, #0
 80063c0:	f000 b800 	b.w	80063c4 <setvbuf>

080063c4 <setvbuf>:
 80063c4:	e92d 43f7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
 80063c8:	461d      	mov	r5, r3
 80063ca:	4b51      	ldr	r3, [pc, #324]	; (8006510 <setvbuf+0x14c>)
 80063cc:	4604      	mov	r4, r0
 80063ce:	681e      	ldr	r6, [r3, #0]
 80063d0:	460f      	mov	r7, r1
 80063d2:	4690      	mov	r8, r2
 80063d4:	b126      	cbz	r6, 80063e0 <setvbuf+0x1c>
 80063d6:	69b3      	ldr	r3, [r6, #24]
 80063d8:	b913      	cbnz	r3, 80063e0 <setvbuf+0x1c>
 80063da:	4630      	mov	r0, r6
 80063dc:	f001 f894 	bl	8007508 <__sinit>
 80063e0:	4b4c      	ldr	r3, [pc, #304]	; (8006514 <setvbuf+0x150>)
 80063e2:	429c      	cmp	r4, r3
 80063e4:	d152      	bne.n	800648c <setvbuf+0xc8>
 80063e6:	6874      	ldr	r4, [r6, #4]
 80063e8:	f1b8 0f02 	cmp.w	r8, #2
 80063ec:	d006      	beq.n	80063fc <setvbuf+0x38>
 80063ee:	f1b8 0f01 	cmp.w	r8, #1
 80063f2:	f200 8089 	bhi.w	8006508 <setvbuf+0x144>
 80063f6:	2d00      	cmp	r5, #0
 80063f8:	f2c0 8086 	blt.w	8006508 <setvbuf+0x144>
 80063fc:	4621      	mov	r1, r4
 80063fe:	4630      	mov	r0, r6
 8006400:	f001 f818 	bl	8007434 <_fflush_r>
 8006404:	6b61      	ldr	r1, [r4, #52]	; 0x34
 8006406:	b141      	cbz	r1, 800641a <setvbuf+0x56>
 8006408:	f104 0344 	add.w	r3, r4, #68	; 0x44
 800640c:	4299      	cmp	r1, r3
 800640e:	d002      	beq.n	8006416 <setvbuf+0x52>
 8006410:	4630      	mov	r0, r6
 8006412:	f001 fc81 	bl	8007d18 <_free_r>
 8006416:	2300      	movs	r3, #0
 8006418:	6363      	str	r3, [r4, #52]	; 0x34
 800641a:	2300      	movs	r3, #0
 800641c:	61a3      	str	r3, [r4, #24]
 800641e:	6063      	str	r3, [r4, #4]
 8006420:	89a3      	ldrh	r3, [r4, #12]
 8006422:	061b      	lsls	r3, r3, #24
 8006424:	d503      	bpl.n	800642e <setvbuf+0x6a>
 8006426:	6921      	ldr	r1, [r4, #16]
 8006428:	4630      	mov	r0, r6
 800642a:	f001 fc75 	bl	8007d18 <_free_r>
 800642e:	89a3      	ldrh	r3, [r4, #12]
 8006430:	f1b8 0f02 	cmp.w	r8, #2
 8006434:	f423 634a 	bic.w	r3, r3, #3232	; 0xca0
 8006438:	f023 0303 	bic.w	r3, r3, #3
 800643c:	81a3      	strh	r3, [r4, #12]
 800643e:	d05d      	beq.n	80064fc <setvbuf+0x138>
 8006440:	ab01      	add	r3, sp, #4
 8006442:	466a      	mov	r2, sp
 8006444:	4621      	mov	r1, r4
 8006446:	4630      	mov	r0, r6
 8006448:	f001 f8f6 	bl	8007638 <__swhatbuf_r>
 800644c:	89a3      	ldrh	r3, [r4, #12]
 800644e:	4318      	orrs	r0, r3
 8006450:	81a0      	strh	r0, [r4, #12]
 8006452:	bb2d      	cbnz	r5, 80064a0 <setvbuf+0xdc>
 8006454:	9d00      	ldr	r5, [sp, #0]
 8006456:	4628      	mov	r0, r5
 8006458:	f001 f952 	bl	8007700 <malloc>
 800645c:	4607      	mov	r7, r0
 800645e:	2800      	cmp	r0, #0
 8006460:	d14e      	bne.n	8006500 <setvbuf+0x13c>
 8006462:	f8dd 9000 	ldr.w	r9, [sp]
 8006466:	45a9      	cmp	r9, r5
 8006468:	d13c      	bne.n	80064e4 <setvbuf+0x120>
 800646a:	f04f 30ff 	mov.w	r0, #4294967295
 800646e:	89a3      	ldrh	r3, [r4, #12]
 8006470:	f043 0302 	orr.w	r3, r3, #2
 8006474:	81a3      	strh	r3, [r4, #12]
 8006476:	2300      	movs	r3, #0
 8006478:	60a3      	str	r3, [r4, #8]
 800647a:	f104 0347 	add.w	r3, r4, #71	; 0x47
 800647e:	6023      	str	r3, [r4, #0]
 8006480:	6123      	str	r3, [r4, #16]
 8006482:	2301      	movs	r3, #1
 8006484:	6163      	str	r3, [r4, #20]
 8006486:	b003      	add	sp, #12
 8006488:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
 800648c:	4b22      	ldr	r3, [pc, #136]	; (8006518 <setvbuf+0x154>)
 800648e:	429c      	cmp	r4, r3
 8006490:	d101      	bne.n	8006496 <setvbuf+0xd2>
 8006492:	68b4      	ldr	r4, [r6, #8]
 8006494:	e7a8      	b.n	80063e8 <setvbuf+0x24>
 8006496:	4b21      	ldr	r3, [pc, #132]	; (800651c <setvbuf+0x158>)
 8006498:	429c      	cmp	r4, r3
 800649a:	bf08      	it	eq
 800649c:	68f4      	ldreq	r4, [r6, #12]
 800649e:	e7a3      	b.n	80063e8 <setvbuf+0x24>
 80064a0:	2f00      	cmp	r7, #0
 80064a2:	d0d8      	beq.n	8006456 <setvbuf+0x92>
 80064a4:	69b3      	ldr	r3, [r6, #24]
 80064a6:	b913      	cbnz	r3, 80064ae <setvbuf+0xea>
 80064a8:	4630      	mov	r0, r6
 80064aa:	f001 f82d 	bl	8007508 <__sinit>
 80064ae:	f1b8 0f01 	cmp.w	r8, #1
 80064b2:	bf08      	it	eq
 80064b4:	89a3      	ldrheq	r3, [r4, #12]
 80064b6:	6027      	str	r7, [r4, #0]
 80064b8:	bf04      	itt	eq
 80064ba:	f043 0301 	orreq.w	r3, r3, #1
 80064be:	81a3      	strheq	r3, [r4, #12]
 80064c0:	89a3      	ldrh	r3, [r4, #12]
 80064c2:	e9c4 7504 	strd	r7, r5, [r4, #16]
 80064c6:	f013 0008 	ands.w	r0, r3, #8
 80064ca:	d01b      	beq.n	8006504 <setvbuf+0x140>
 80064cc:	f013 0001 	ands.w	r0, r3, #1
 80064d0:	f04f 0300 	mov.w	r3, #0
 80064d4:	bf1f      	itttt	ne
 80064d6:	426d      	negne	r5, r5
 80064d8:	60a3      	strne	r3, [r4, #8]
 80064da:	61a5      	strne	r5, [r4, #24]
 80064dc:	4618      	movne	r0, r3
 80064de:	bf08      	it	eq
 80064e0:	60a5      	streq	r5, [r4, #8]
 80064e2:	e7d0      	b.n	8006486 <setvbuf+0xc2>
 80064e4:	4648      	mov	r0, r9
 80064e6:	f001 f90b 	bl	8007700 <malloc>
 80064ea:	4607      	mov	r7, r0
 80064ec:	2800      	cmp	r0, #0
 80064ee:	d0bc      	beq.n	800646a <setvbuf+0xa6>
 80064f0:	89a3      	ldrh	r3, [r4, #12]
 80064f2:	464d      	mov	r5, r9
 80064f4:	f043 0380 	orr.w	r3, r3, #128	; 0x80
 80064f8:	81a3      	strh	r3, [r4, #12]
 80064fa:	e7d3      	b.n	80064a4 <setvbuf+0xe0>
 80064fc:	2000      	movs	r0, #0
 80064fe:	e7b6      	b.n	800646e <setvbuf+0xaa>
 8006500:	46a9      	mov	r9, r5
 8006502:	e7f5      	b.n	80064f0 <setvbuf+0x12c>
 8006504:	60a0      	str	r0, [r4, #8]
 8006506:	e7be      	b.n	8006486 <setvbuf+0xc2>
 8006508:	f04f 30ff 	mov.w	r0, #4294967295
 800650c:	e7bb      	b.n	8006486 <setvbuf+0xc2>
 800650e:	bf00      	nop
 8006510:	2000000c 	.word	0x2000000c
 8006514:	08008660 	.word	0x08008660
 8006518:	08008680 	.word	0x08008680
 800651c:	08008640 	.word	0x08008640

08006520 <__swbuf_r>:
 8006520:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 8006522:	460e      	mov	r6, r1
 8006524:	4614      	mov	r4, r2
 8006526:	4605      	mov	r5, r0
 8006528:	b118      	cbz	r0, 8006532 <__swbuf_r+0x12>
 800652a:	6983      	ldr	r3, [r0, #24]
 800652c:	b90b      	cbnz	r3, 8006532 <__swbuf_r+0x12>
 800652e:	f000 ffeb 	bl	8007508 <__sinit>
 8006532:	4b21      	ldr	r3, [pc, #132]	; (80065b8 <__swbuf_r+0x98>)
 8006534:	429c      	cmp	r4, r3
 8006536:	d12a      	bne.n	800658e <__swbuf_r+0x6e>
 8006538:	686c      	ldr	r4, [r5, #4]
 800653a:	69a3      	ldr	r3, [r4, #24]
 800653c:	60a3      	str	r3, [r4, #8]
 800653e:	89a3      	ldrh	r3, [r4, #12]
 8006540:	071a      	lsls	r2, r3, #28
 8006542:	d52e      	bpl.n	80065a2 <__swbuf_r+0x82>
 8006544:	6923      	ldr	r3, [r4, #16]
 8006546:	b363      	cbz	r3, 80065a2 <__swbuf_r+0x82>
 8006548:	6923      	ldr	r3, [r4, #16]
 800654a:	6820      	ldr	r0, [r4, #0]
 800654c:	b2f6      	uxtb	r6, r6
 800654e:	1ac0      	subs	r0, r0, r3
 8006550:	6963      	ldr	r3, [r4, #20]
 8006552:	4637      	mov	r7, r6
 8006554:	4283      	cmp	r3, r0
 8006556:	dc04      	bgt.n	8006562 <__swbuf_r+0x42>
 8006558:	4621      	mov	r1, r4
 800655a:	4628      	mov	r0, r5
 800655c:	f000 ff6a 	bl	8007434 <_fflush_r>
 8006560:	bb28      	cbnz	r0, 80065ae <__swbuf_r+0x8e>
 8006562:	68a3      	ldr	r3, [r4, #8]
 8006564:	3001      	adds	r0, #1
 8006566:	3b01      	subs	r3, #1
 8006568:	60a3      	str	r3, [r4, #8]
 800656a:	6823      	ldr	r3, [r4, #0]
 800656c:	1c5a      	adds	r2, r3, #1
 800656e:	6022      	str	r2, [r4, #0]
 8006570:	701e      	strb	r6, [r3, #0]
 8006572:	6963      	ldr	r3, [r4, #20]
 8006574:	4283      	cmp	r3, r0
 8006576:	d004      	beq.n	8006582 <__swbuf_r+0x62>
 8006578:	89a3      	ldrh	r3, [r4, #12]
 800657a:	07db      	lsls	r3, r3, #31
 800657c:	d519      	bpl.n	80065b2 <__swbuf_r+0x92>
 800657e:	2e0a      	cmp	r6, #10
 8006580:	d117      	bne.n	80065b2 <__swbuf_r+0x92>
 8006582:	4621      	mov	r1, r4
 8006584:	4628      	mov	r0, r5
 8006586:	f000 ff55 	bl	8007434 <_fflush_r>
 800658a:	b190      	cbz	r0, 80065b2 <__swbuf_r+0x92>
 800658c:	e00f      	b.n	80065ae <__swbuf_r+0x8e>
 800658e:	4b0b      	ldr	r3, [pc, #44]	; (80065bc <__swbuf_r+0x9c>)
 8006590:	429c      	cmp	r4, r3
 8006592:	d101      	bne.n	8006598 <__swbuf_r+0x78>
 8006594:	68ac      	ldr	r4, [r5, #8]
 8006596:	e7d0      	b.n	800653a <__swbuf_r+0x1a>
 8006598:	4b09      	ldr	r3, [pc, #36]	; (80065c0 <__swbuf_r+0xa0>)
 800659a:	429c      	cmp	r4, r3
 800659c:	bf08      	it	eq
 800659e:	68ec      	ldreq	r4, [r5, #12]
 80065a0:	e7cb      	b.n	800653a <__swbuf_r+0x1a>
 80065a2:	4621      	mov	r1, r4
 80065a4:	4628      	mov	r0, r5
 80065a6:	f000 f80d 	bl	80065c4 <__swsetup_r>
 80065aa:	2800      	cmp	r0, #0
 80065ac:	d0cc      	beq.n	8006548 <__swbuf_r+0x28>
 80065ae:	f04f 37ff 	mov.w	r7, #4294967295
 80065b2:	4638      	mov	r0, r7
 80065b4:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
 80065b6:	bf00      	nop
 80065b8:	08008660 	.word	0x08008660
 80065bc:	08008680 	.word	0x08008680
 80065c0:	08008640 	.word	0x08008640

080065c4 <__swsetup_r>:
 80065c4:	4b32      	ldr	r3, [pc, #200]	; (8006690 <__swsetup_r+0xcc>)
 80065c6:	b570      	push	{r4, r5, r6, lr}
 80065c8:	681d      	ldr	r5, [r3, #0]
 80065ca:	4606      	mov	r6, r0
 80065cc:	460c      	mov	r4, r1
 80065ce:	b125      	cbz	r5, 80065da <__swsetup_r+0x16>
 80065d0:	69ab      	ldr	r3, [r5, #24]
 80065d2:	b913      	cbnz	r3, 80065da <__swsetup_r+0x16>
 80065d4:	4628      	mov	r0, r5
 80065d6:	f000 ff97 	bl	8007508 <__sinit>
 80065da:	4b2e      	ldr	r3, [pc, #184]	; (8006694 <__swsetup_r+0xd0>)
 80065dc:	429c      	cmp	r4, r3
 80065de:	d10f      	bne.n	8006600 <__swsetup_r+0x3c>
 80065e0:	686c      	ldr	r4, [r5, #4]
 80065e2:	f9b4 300c 	ldrsh.w	r3, [r4, #12]
 80065e6:	b29a      	uxth	r2, r3
 80065e8:	0715      	lsls	r5, r2, #28
 80065ea:	d42c      	bmi.n	8006646 <__swsetup_r+0x82>
 80065ec:	06d0      	lsls	r0, r2, #27
 80065ee:	d411      	bmi.n	8006614 <__swsetup_r+0x50>
 80065f0:	2209      	movs	r2, #9
 80065f2:	6032      	str	r2, [r6, #0]
 80065f4:	f043 0340 	orr.w	r3, r3, #64	; 0x40
 80065f8:	81a3      	strh	r3, [r4, #12]
 80065fa:	f04f 30ff 	mov.w	r0, #4294967295
 80065fe:	e03e      	b.n	800667e <__swsetup_r+0xba>
 8006600:	4b25      	ldr	r3, [pc, #148]	; (8006698 <__swsetup_r+0xd4>)
 8006602:	429c      	cmp	r4, r3
 8006604:	d101      	bne.n	800660a <__swsetup_r+0x46>
 8006606:	68ac      	ldr	r4, [r5, #8]
 8006608:	e7eb      	b.n	80065e2 <__swsetup_r+0x1e>
 800660a:	4b24      	ldr	r3, [pc, #144]	; (800669c <__swsetup_r+0xd8>)
 800660c:	429c      	cmp	r4, r3
 800660e:	bf08      	it	eq
 8006610:	68ec      	ldreq	r4, [r5, #12]
 8006612:	e7e6      	b.n	80065e2 <__swsetup_r+0x1e>
 8006614:	0751      	lsls	r1, r2, #29
 8006616:	d512      	bpl.n	800663e <__swsetup_r+0x7a>
 8006618:	6b61      	ldr	r1, [r4, #52]	; 0x34
 800661a:	b141      	cbz	r1, 800662e <__swsetup_r+0x6a>
 800661c:	f104 0344 	add.w	r3, r4, #68	; 0x44
 8006620:	4299      	cmp	r1, r3
 8006622:	d002      	beq.n	800662a <__swsetup_r+0x66>
 8006624:	4630      	mov	r0, r6
 8006626:	f001 fb77 	bl	8007d18 <_free_r>
 800662a:	2300      	movs	r3, #0
 800662c:	6363      	str	r3, [r4, #52]	; 0x34
 800662e:	89a3      	ldrh	r3, [r4, #12]
 8006630:	f023 0324 	bic.w	r3, r3, #36	; 0x24
 8006634:	81a3      	strh	r3, [r4, #12]
 8006636:	2300      	movs	r3, #0
 8006638:	6063      	str	r3, [r4, #4]
 800663a:	6923      	ldr	r3, [r4, #16]
 800663c:	6023      	str	r3, [r4, #0]
 800663e:	89a3      	ldrh	r3, [r4, #12]
 8006640:	f043 0308 	orr.w	r3, r3, #8
 8006644:	81a3      	strh	r3, [r4, #12]
 8006646:	6923      	ldr	r3, [r4, #16]
 8006648:	b94b      	cbnz	r3, 800665e <__swsetup_r+0x9a>
 800664a:	89a3      	ldrh	r3, [r4, #12]
 800664c:	f403 7320 	and.w	r3, r3, #640	; 0x280
 8006650:	f5b3 7f00 	cmp.w	r3, #512	; 0x200
 8006654:	d003      	beq.n	800665e <__swsetup_r+0x9a>
 8006656:	4621      	mov	r1, r4
 8006658:	4630      	mov	r0, r6
 800665a:	f001 f811 	bl	8007680 <__smakebuf_r>
 800665e:	89a2      	ldrh	r2, [r4, #12]
 8006660:	f012 0301 	ands.w	r3, r2, #1
 8006664:	d00c      	beq.n	8006680 <__swsetup_r+0xbc>
 8006666:	2300      	movs	r3, #0
 8006668:	60a3      	str	r3, [r4, #8]
 800666a:	6963      	ldr	r3, [r4, #20]
 800666c:	425b      	negs	r3, r3
 800666e:	61a3      	str	r3, [r4, #24]
 8006670:	6923      	ldr	r3, [r4, #16]
 8006672:	b953      	cbnz	r3, 800668a <__swsetup_r+0xc6>
 8006674:	f9b4 300c 	ldrsh.w	r3, [r4, #12]
 8006678:	f013 0080 	ands.w	r0, r3, #128	; 0x80
 800667c:	d1ba      	bne.n	80065f4 <__swsetup_r+0x30>
 800667e:	bd70      	pop	{r4, r5, r6, pc}
 8006680:	0792      	lsls	r2, r2, #30
 8006682:	bf58      	it	pl
 8006684:	6963      	ldrpl	r3, [r4, #20]
 8006686:	60a3      	str	r3, [r4, #8]
 8006688:	e7f2      	b.n	8006670 <__swsetup_r+0xac>
 800668a:	2000      	movs	r0, #0
 800668c:	e7f7      	b.n	800667e <__swsetup_r+0xba>
 800668e:	bf00      	nop
 8006690:	2000000c 	.word	0x2000000c
 8006694:	08008660 	.word	0x08008660
 8006698:	08008680 	.word	0x08008680
 800669c:	08008640 	.word	0x08008640

080066a0 <quorem>:
 80066a0:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
 80066a4:	6903      	ldr	r3, [r0, #16]
 80066a6:	690c      	ldr	r4, [r1, #16]
 80066a8:	4680      	mov	r8, r0
 80066aa:	42a3      	cmp	r3, r4
 80066ac:	f2c0 8084 	blt.w	80067b8 <quorem+0x118>
 80066b0:	3c01      	subs	r4, #1
 80066b2:	f101 0714 	add.w	r7, r1, #20
 80066b6:	f100 0614 	add.w	r6, r0, #20
 80066ba:	f857 5024 	ldr.w	r5, [r7, r4, lsl #2]
 80066be:	f856 0024 	ldr.w	r0, [r6, r4, lsl #2]
 80066c2:	3501      	adds	r5, #1
 80066c4:	fbb0 f5f5 	udiv	r5, r0, r5
 80066c8:	ea4f 0c84 	mov.w	ip, r4, lsl #2
 80066cc:	eb06 030c 	add.w	r3, r6, ip
 80066d0:	eb07 090c 	add.w	r9, r7, ip
 80066d4:	9301      	str	r3, [sp, #4]
 80066d6:	b39d      	cbz	r5, 8006740 <quorem+0xa0>
 80066d8:	f04f 0a00 	mov.w	sl, #0
 80066dc:	4638      	mov	r0, r7
 80066de:	46b6      	mov	lr, r6
 80066e0:	46d3      	mov	fp, sl
 80066e2:	f850 2b04 	ldr.w	r2, [r0], #4
 80066e6:	b293      	uxth	r3, r2
 80066e8:	fb05 a303 	mla	r3, r5, r3, sl
 80066ec:	0c12      	lsrs	r2, r2, #16
 80066ee:	ea4f 4a13 	mov.w	sl, r3, lsr #16
 80066f2:	fb05 a202 	mla	r2, r5, r2, sl
 80066f6:	b29b      	uxth	r3, r3
 80066f8:	ebab 0303 	sub.w	r3, fp, r3
 80066fc:	f8de b000 	ldr.w	fp, [lr]
 8006700:	ea4f 4a12 	mov.w	sl, r2, lsr #16
 8006704:	fa1f fb8b 	uxth.w	fp, fp
 8006708:	445b      	add	r3, fp
 800670a:	fa1f fb82 	uxth.w	fp, r2
 800670e:	f8de 2000 	ldr.w	r2, [lr]
 8006712:	4581      	cmp	r9, r0
 8006714:	ebcb 4212 	rsb	r2, fp, r2, lsr #16
 8006718:	eb02 4223 	add.w	r2, r2, r3, asr #16
 800671c:	b29b      	uxth	r3, r3
 800671e:	ea43 4302 	orr.w	r3, r3, r2, lsl #16
 8006722:	ea4f 4b22 	mov.w	fp, r2, asr #16
 8006726:	f84e 3b04 	str.w	r3, [lr], #4
 800672a:	d2da      	bcs.n	80066e2 <quorem+0x42>
 800672c:	f856 300c 	ldr.w	r3, [r6, ip]
 8006730:	b933      	cbnz	r3, 8006740 <quorem+0xa0>
 8006732:	9b01      	ldr	r3, [sp, #4]
 8006734:	3b04      	subs	r3, #4
 8006736:	429e      	cmp	r6, r3
 8006738:	461a      	mov	r2, r3
 800673a:	d331      	bcc.n	80067a0 <quorem+0x100>
 800673c:	f8c8 4010 	str.w	r4, [r8, #16]
 8006740:	4640      	mov	r0, r8
 8006742:	f001 fa13 	bl	8007b6c <__mcmp>
 8006746:	2800      	cmp	r0, #0
 8006748:	db26      	blt.n	8006798 <quorem+0xf8>
 800674a:	4630      	mov	r0, r6
 800674c:	f04f 0c00 	mov.w	ip, #0
 8006750:	3501      	adds	r5, #1
 8006752:	f857 1b04 	ldr.w	r1, [r7], #4
 8006756:	f8d0 e000 	ldr.w	lr, [r0]
 800675a:	b28b      	uxth	r3, r1
 800675c:	ebac 0303 	sub.w	r3, ip, r3
 8006760:	fa1f f28e 	uxth.w	r2, lr
 8006764:	4413      	add	r3, r2
 8006766:	0c0a      	lsrs	r2, r1, #16
 8006768:	ebc2 421e 	rsb	r2, r2, lr, lsr #16
 800676c:	eb02 4223 	add.w	r2, r2, r3, asr #16
 8006770:	b29b      	uxth	r3, r3
 8006772:	ea43 4302 	orr.w	r3, r3, r2, lsl #16
 8006776:	45b9      	cmp	r9, r7
 8006778:	ea4f 4c22 	mov.w	ip, r2, asr #16
 800677c:	f840 3b04 	str.w	r3, [r0], #4
 8006780:	d2e7      	bcs.n	8006752 <quorem+0xb2>
 8006782:	f856 2024 	ldr.w	r2, [r6, r4, lsl #2]
 8006786:	eb06 0384 	add.w	r3, r6, r4, lsl #2
 800678a:	b92a      	cbnz	r2, 8006798 <quorem+0xf8>
 800678c:	3b04      	subs	r3, #4
 800678e:	429e      	cmp	r6, r3
 8006790:	461a      	mov	r2, r3
 8006792:	d30b      	bcc.n	80067ac <quorem+0x10c>
 8006794:	f8c8 4010 	str.w	r4, [r8, #16]
 8006798:	4628      	mov	r0, r5
 800679a:	b003      	add	sp, #12
 800679c:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
 80067a0:	6812      	ldr	r2, [r2, #0]
 80067a2:	3b04      	subs	r3, #4
 80067a4:	2a00      	cmp	r2, #0
 80067a6:	d1c9      	bne.n	800673c <quorem+0x9c>
 80067a8:	3c01      	subs	r4, #1
 80067aa:	e7c4      	b.n	8006736 <quorem+0x96>
 80067ac:	6812      	ldr	r2, [r2, #0]
 80067ae:	3b04      	subs	r3, #4
 80067b0:	2a00      	cmp	r2, #0
 80067b2:	d1ef      	bne.n	8006794 <quorem+0xf4>
 80067b4:	3c01      	subs	r4, #1
 80067b6:	e7ea      	b.n	800678e <quorem+0xee>
 80067b8:	2000      	movs	r0, #0
 80067ba:	e7ee      	b.n	800679a <quorem+0xfa>
 80067bc:	0000      	movs	r0, r0
	...

080067c0 <_dtoa_r>:
 80067c0:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
 80067c4:	4616      	mov	r6, r2
 80067c6:	461f      	mov	r7, r3
 80067c8:	6a45      	ldr	r5, [r0, #36]	; 0x24
 80067ca:	b095      	sub	sp, #84	; 0x54
 80067cc:	4604      	mov	r4, r0
 80067ce:	f8dd 8084 	ldr.w	r8, [sp, #132]	; 0x84
 80067d2:	e9cd 6702 	strd	r6, r7, [sp, #8]
 80067d6:	b93d      	cbnz	r5, 80067e8 <_dtoa_r+0x28>
 80067d8:	2010      	movs	r0, #16
 80067da:	f000 ff91 	bl	8007700 <malloc>
 80067de:	6260      	str	r0, [r4, #36]	; 0x24
 80067e0:	e9c0 5501 	strd	r5, r5, [r0, #4]
 80067e4:	6005      	str	r5, [r0, #0]
 80067e6:	60c5      	str	r5, [r0, #12]
 80067e8:	6a63      	ldr	r3, [r4, #36]	; 0x24
 80067ea:	6819      	ldr	r1, [r3, #0]
 80067ec:	b151      	cbz	r1, 8006804 <_dtoa_r+0x44>
 80067ee:	685a      	ldr	r2, [r3, #4]
 80067f0:	2301      	movs	r3, #1
 80067f2:	4093      	lsls	r3, r2
 80067f4:	604a      	str	r2, [r1, #4]
 80067f6:	608b      	str	r3, [r1, #8]
 80067f8:	4620      	mov	r0, r4
 80067fa:	f000 ffd6 	bl	80077aa <_Bfree>
 80067fe:	2200      	movs	r2, #0
 8006800:	6a63      	ldr	r3, [r4, #36]	; 0x24
 8006802:	601a      	str	r2, [r3, #0]
 8006804:	1e3b      	subs	r3, r7, #0
 8006806:	bfaf      	iteee	ge
 8006808:	2300      	movge	r3, #0
 800680a:	2201      	movlt	r2, #1
 800680c:	f023 4300 	biclt.w	r3, r3, #2147483648	; 0x80000000
 8006810:	9303      	strlt	r3, [sp, #12]
 8006812:	bfac      	ite	ge
 8006814:	f8c8 3000 	strge.w	r3, [r8]
 8006818:	f8c8 2000 	strlt.w	r2, [r8]
 800681c:	4bae      	ldr	r3, [pc, #696]	; (8006ad8 <_dtoa_r+0x318>)
 800681e:	f8dd 800c 	ldr.w	r8, [sp, #12]
 8006822:	ea33 0308 	bics.w	r3, r3, r8
 8006826:	d11b      	bne.n	8006860 <_dtoa_r+0xa0>
 8006828:	f242 730f 	movw	r3, #9999	; 0x270f
 800682c:	9a20      	ldr	r2, [sp, #128]	; 0x80
 800682e:	6013      	str	r3, [r2, #0]
 8006830:	9b02      	ldr	r3, [sp, #8]
 8006832:	b923      	cbnz	r3, 800683e <_dtoa_r+0x7e>
 8006834:	f3c8 0013 	ubfx	r0, r8, #0, #20
 8006838:	2800      	cmp	r0, #0
 800683a:	f000 8545 	beq.w	80072c8 <_dtoa_r+0xb08>
 800683e:	9b22      	ldr	r3, [sp, #136]	; 0x88
 8006840:	b953      	cbnz	r3, 8006858 <_dtoa_r+0x98>
 8006842:	4ba6      	ldr	r3, [pc, #664]	; (8006adc <_dtoa_r+0x31c>)
 8006844:	e021      	b.n	800688a <_dtoa_r+0xca>
 8006846:	4ba6      	ldr	r3, [pc, #664]	; (8006ae0 <_dtoa_r+0x320>)
 8006848:	9306      	str	r3, [sp, #24]
 800684a:	3308      	adds	r3, #8
 800684c:	9a22      	ldr	r2, [sp, #136]	; 0x88
 800684e:	6013      	str	r3, [r2, #0]
 8006850:	9806      	ldr	r0, [sp, #24]
 8006852:	b015      	add	sp, #84	; 0x54
 8006854:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
 8006858:	4ba0      	ldr	r3, [pc, #640]	; (8006adc <_dtoa_r+0x31c>)
 800685a:	9306      	str	r3, [sp, #24]
 800685c:	3303      	adds	r3, #3
 800685e:	e7f5      	b.n	800684c <_dtoa_r+0x8c>
 8006860:	e9dd 6702 	ldrd	r6, r7, [sp, #8]
 8006864:	2200      	movs	r2, #0
 8006866:	2300      	movs	r3, #0
 8006868:	4630      	mov	r0, r6
 800686a:	4639      	mov	r1, r7
 800686c:	f7fa f8fc 	bl	8000a68 <__aeabi_dcmpeq>
 8006870:	4682      	mov	sl, r0
 8006872:	b160      	cbz	r0, 800688e <_dtoa_r+0xce>
 8006874:	2301      	movs	r3, #1
 8006876:	9a20      	ldr	r2, [sp, #128]	; 0x80
 8006878:	6013      	str	r3, [r2, #0]
 800687a:	9b22      	ldr	r3, [sp, #136]	; 0x88
 800687c:	2b00      	cmp	r3, #0
 800687e:	f000 8520 	beq.w	80072c2 <_dtoa_r+0xb02>
 8006882:	4b98      	ldr	r3, [pc, #608]	; (8006ae4 <_dtoa_r+0x324>)
 8006884:	9a22      	ldr	r2, [sp, #136]	; 0x88
 8006886:	6013      	str	r3, [r2, #0]
 8006888:	3b01      	subs	r3, #1
 800688a:	9306      	str	r3, [sp, #24]
 800688c:	e7e0      	b.n	8006850 <_dtoa_r+0x90>
 800688e:	ab12      	add	r3, sp, #72	; 0x48
 8006890:	9301      	str	r3, [sp, #4]
 8006892:	ab13      	add	r3, sp, #76	; 0x4c
 8006894:	9300      	str	r3, [sp, #0]
 8006896:	4632      	mov	r2, r6
 8006898:	463b      	mov	r3, r7
 800689a:	4620      	mov	r0, r4
 800689c:	f001 f9de 	bl	8007c5c <__d2b>
 80068a0:	f3c8 550a 	ubfx	r5, r8, #20, #11
 80068a4:	4683      	mov	fp, r0
 80068a6:	2d00      	cmp	r5, #0
 80068a8:	d07d      	beq.n	80069a6 <_dtoa_r+0x1e6>
 80068aa:	46b0      	mov	r8, r6
 80068ac:	f3c7 0313 	ubfx	r3, r7, #0, #20
 80068b0:	f043 597f 	orr.w	r9, r3, #1069547520	; 0x3fc00000
 80068b4:	f449 1940 	orr.w	r9, r9, #3145728	; 0x300000
 80068b8:	f2a5 35ff 	subw	r5, r5, #1023	; 0x3ff
 80068bc:	f8cd a040 	str.w	sl, [sp, #64]	; 0x40
 80068c0:	2200      	movs	r2, #0
 80068c2:	4b89      	ldr	r3, [pc, #548]	; (8006ae8 <_dtoa_r+0x328>)
 80068c4:	4640      	mov	r0, r8
 80068c6:	4649      	mov	r1, r9
 80068c8:	f7f9 fcae 	bl	8000228 <__aeabi_dsub>
 80068cc:	a37c      	add	r3, pc, #496	; (adr r3, 8006ac0 <_dtoa_r+0x300>)
 80068ce:	e9d3 2300 	ldrd	r2, r3, [r3]
 80068d2:	f7f9 fe61 	bl	8000598 <__aeabi_dmul>
 80068d6:	a37c      	add	r3, pc, #496	; (adr r3, 8006ac8 <_dtoa_r+0x308>)
 80068d8:	e9d3 2300 	ldrd	r2, r3, [r3]
 80068dc:	f7f9 fca6 	bl	800022c <__adddf3>
 80068e0:	4606      	mov	r6, r0
 80068e2:	4628      	mov	r0, r5
 80068e4:	460f      	mov	r7, r1
 80068e6:	f7f9 fded 	bl	80004c4 <__aeabi_i2d>
 80068ea:	a379      	add	r3, pc, #484	; (adr r3, 8006ad0 <_dtoa_r+0x310>)
 80068ec:	e9d3 2300 	ldrd	r2, r3, [r3]
 80068f0:	f7f9 fe52 	bl	8000598 <__aeabi_dmul>
 80068f4:	4602      	mov	r2, r0
 80068f6:	460b      	mov	r3, r1
 80068f8:	4630      	mov	r0, r6
 80068fa:	4639      	mov	r1, r7
 80068fc:	f7f9 fc96 	bl	800022c <__adddf3>
 8006900:	4606      	mov	r6, r0
 8006902:	460f      	mov	r7, r1
 8006904:	f7fa f8f8 	bl	8000af8 <__aeabi_d2iz>
 8006908:	2200      	movs	r2, #0
 800690a:	4682      	mov	sl, r0
 800690c:	2300      	movs	r3, #0
 800690e:	4630      	mov	r0, r6
 8006910:	4639      	mov	r1, r7
 8006912:	f7fa f8b3 	bl	8000a7c <__aeabi_dcmplt>
 8006916:	b148      	cbz	r0, 800692c <_dtoa_r+0x16c>
 8006918:	4650      	mov	r0, sl
 800691a:	f7f9 fdd3 	bl	80004c4 <__aeabi_i2d>
 800691e:	4632      	mov	r2, r6
 8006920:	463b      	mov	r3, r7
 8006922:	f7fa f8a1 	bl	8000a68 <__aeabi_dcmpeq>
 8006926:	b908      	cbnz	r0, 800692c <_dtoa_r+0x16c>
 8006928:	f10a 3aff 	add.w	sl, sl, #4294967295
 800692c:	f1ba 0f16 	cmp.w	sl, #22
 8006930:	d85a      	bhi.n	80069e8 <_dtoa_r+0x228>
 8006932:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
 8006936:	496d      	ldr	r1, [pc, #436]	; (8006aec <_dtoa_r+0x32c>)
 8006938:	eb01 01ca 	add.w	r1, r1, sl, lsl #3
 800693c:	e9d1 0100 	ldrd	r0, r1, [r1]
 8006940:	f7fa f8ba 	bl	8000ab8 <__aeabi_dcmpgt>
 8006944:	2800      	cmp	r0, #0
 8006946:	d051      	beq.n	80069ec <_dtoa_r+0x22c>
 8006948:	2300      	movs	r3, #0
 800694a:	f10a 3aff 	add.w	sl, sl, #4294967295
 800694e:	930d      	str	r3, [sp, #52]	; 0x34
 8006950:	9b12      	ldr	r3, [sp, #72]	; 0x48
 8006952:	1b5d      	subs	r5, r3, r5
 8006954:	1e6b      	subs	r3, r5, #1
 8006956:	9307      	str	r3, [sp, #28]
 8006958:	bf43      	ittte	mi
 800695a:	2300      	movmi	r3, #0
 800695c:	f1c5 0901 	rsbmi	r9, r5, #1
 8006960:	9307      	strmi	r3, [sp, #28]
 8006962:	f04f 0900 	movpl.w	r9, #0
 8006966:	f1ba 0f00 	cmp.w	sl, #0
 800696a:	db41      	blt.n	80069f0 <_dtoa_r+0x230>
 800696c:	9b07      	ldr	r3, [sp, #28]
 800696e:	f8cd a030 	str.w	sl, [sp, #48]	; 0x30
 8006972:	4453      	add	r3, sl
 8006974:	9307      	str	r3, [sp, #28]
 8006976:	2300      	movs	r3, #0
 8006978:	9308      	str	r3, [sp, #32]
 800697a:	9b1e      	ldr	r3, [sp, #120]	; 0x78
 800697c:	2b09      	cmp	r3, #9
 800697e:	f200 808f 	bhi.w	8006aa0 <_dtoa_r+0x2e0>
 8006982:	2b05      	cmp	r3, #5
 8006984:	bfc4      	itt	gt
 8006986:	3b04      	subgt	r3, #4
 8006988:	931e      	strgt	r3, [sp, #120]	; 0x78
 800698a:	9b1e      	ldr	r3, [sp, #120]	; 0x78
 800698c:	bfc8      	it	gt
 800698e:	2500      	movgt	r5, #0
 8006990:	f1a3 0302 	sub.w	r3, r3, #2
 8006994:	bfd8      	it	le
 8006996:	2501      	movle	r5, #1
 8006998:	2b03      	cmp	r3, #3
 800699a:	f200 808d 	bhi.w	8006ab8 <_dtoa_r+0x2f8>
 800699e:	e8df f003 	tbb	[pc, r3]
 80069a2:	7d7b      	.short	0x7d7b
 80069a4:	6f2f      	.short	0x6f2f
 80069a6:	e9dd 5312 	ldrd	r5, r3, [sp, #72]	; 0x48
 80069aa:	441d      	add	r5, r3
 80069ac:	f205 4032 	addw	r0, r5, #1074	; 0x432
 80069b0:	2820      	cmp	r0, #32
 80069b2:	dd13      	ble.n	80069dc <_dtoa_r+0x21c>
 80069b4:	f1c0 0040 	rsb	r0, r0, #64	; 0x40
 80069b8:	9b02      	ldr	r3, [sp, #8]
 80069ba:	fa08 f800 	lsl.w	r8, r8, r0
 80069be:	f205 4012 	addw	r0, r5, #1042	; 0x412
 80069c2:	fa23 f000 	lsr.w	r0, r3, r0
 80069c6:	ea48 0000 	orr.w	r0, r8, r0
 80069ca:	f7f9 fd6b 	bl	80004a4 <__aeabi_ui2d>
 80069ce:	2301      	movs	r3, #1
 80069d0:	4680      	mov	r8, r0
 80069d2:	f1a1 79f8 	sub.w	r9, r1, #32505856	; 0x1f00000
 80069d6:	3d01      	subs	r5, #1
 80069d8:	9310      	str	r3, [sp, #64]	; 0x40
 80069da:	e771      	b.n	80068c0 <_dtoa_r+0x100>
 80069dc:	9b02      	ldr	r3, [sp, #8]
 80069de:	f1c0 0020 	rsb	r0, r0, #32
 80069e2:	fa03 f000 	lsl.w	r0, r3, r0
 80069e6:	e7f0      	b.n	80069ca <_dtoa_r+0x20a>
 80069e8:	2301      	movs	r3, #1
 80069ea:	e7b0      	b.n	800694e <_dtoa_r+0x18e>
 80069ec:	900d      	str	r0, [sp, #52]	; 0x34
 80069ee:	e7af      	b.n	8006950 <_dtoa_r+0x190>
 80069f0:	f1ca 0300 	rsb	r3, sl, #0
 80069f4:	9308      	str	r3, [sp, #32]
 80069f6:	2300      	movs	r3, #0
 80069f8:	eba9 090a 	sub.w	r9, r9, sl
 80069fc:	930c      	str	r3, [sp, #48]	; 0x30
 80069fe:	e7bc      	b.n	800697a <_dtoa_r+0x1ba>
 8006a00:	2301      	movs	r3, #1
 8006a02:	9309      	str	r3, [sp, #36]	; 0x24
 8006a04:	9b1f      	ldr	r3, [sp, #124]	; 0x7c
 8006a06:	2b00      	cmp	r3, #0
 8006a08:	dd74      	ble.n	8006af4 <_dtoa_r+0x334>
 8006a0a:	4698      	mov	r8, r3
 8006a0c:	9304      	str	r3, [sp, #16]
 8006a0e:	2200      	movs	r2, #0
 8006a10:	6a66      	ldr	r6, [r4, #36]	; 0x24
 8006a12:	6072      	str	r2, [r6, #4]
 8006a14:	2204      	movs	r2, #4
 8006a16:	f102 0014 	add.w	r0, r2, #20
 8006a1a:	4298      	cmp	r0, r3
 8006a1c:	6871      	ldr	r1, [r6, #4]
 8006a1e:	d96e      	bls.n	8006afe <_dtoa_r+0x33e>
 8006a20:	4620      	mov	r0, r4
 8006a22:	f000 fe8e 	bl	8007742 <_Balloc>
 8006a26:	6a63      	ldr	r3, [r4, #36]	; 0x24
 8006a28:	6030      	str	r0, [r6, #0]
 8006a2a:	681b      	ldr	r3, [r3, #0]
 8006a2c:	f1b8 0f0e 	cmp.w	r8, #14
 8006a30:	9306      	str	r3, [sp, #24]
 8006a32:	f200 80ed 	bhi.w	8006c10 <_dtoa_r+0x450>
 8006a36:	2d00      	cmp	r5, #0
 8006a38:	f000 80ea 	beq.w	8006c10 <_dtoa_r+0x450>
 8006a3c:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
 8006a40:	f1ba 0f00 	cmp.w	sl, #0
 8006a44:	e9cd 230e 	strd	r2, r3, [sp, #56]	; 0x38
 8006a48:	dd77      	ble.n	8006b3a <_dtoa_r+0x37a>
 8006a4a:	4a28      	ldr	r2, [pc, #160]	; (8006aec <_dtoa_r+0x32c>)
 8006a4c:	f00a 030f 	and.w	r3, sl, #15
 8006a50:	ea4f 162a 	mov.w	r6, sl, asr #4
 8006a54:	eb02 03c3 	add.w	r3, r2, r3, lsl #3
 8006a58:	06f0      	lsls	r0, r6, #27
 8006a5a:	e9d3 2300 	ldrd	r2, r3, [r3]
 8006a5e:	e9cd 230a 	strd	r2, r3, [sp, #40]	; 0x28
 8006a62:	d568      	bpl.n	8006b36 <_dtoa_r+0x376>
 8006a64:	e9dd 010e 	ldrd	r0, r1, [sp, #56]	; 0x38
 8006a68:	4b21      	ldr	r3, [pc, #132]	; (8006af0 <_dtoa_r+0x330>)
 8006a6a:	2503      	movs	r5, #3
 8006a6c:	e9d3 2308 	ldrd	r2, r3, [r3, #32]
 8006a70:	f7f9 febc 	bl	80007ec <__aeabi_ddiv>
 8006a74:	e9cd 0102 	strd	r0, r1, [sp, #8]
 8006a78:	f006 060f 	and.w	r6, r6, #15
 8006a7c:	4f1c      	ldr	r7, [pc, #112]	; (8006af0 <_dtoa_r+0x330>)
 8006a7e:	e04f      	b.n	8006b20 <_dtoa_r+0x360>
 8006a80:	2301      	movs	r3, #1
 8006a82:	9309      	str	r3, [sp, #36]	; 0x24
 8006a84:	9b1f      	ldr	r3, [sp, #124]	; 0x7c
 8006a86:	4453      	add	r3, sl
 8006a88:	f103 0801 	add.w	r8, r3, #1
 8006a8c:	9304      	str	r3, [sp, #16]
 8006a8e:	4643      	mov	r3, r8
 8006a90:	2b01      	cmp	r3, #1
 8006a92:	bfb8      	it	lt
 8006a94:	2301      	movlt	r3, #1
 8006a96:	e7ba      	b.n	8006a0e <_dtoa_r+0x24e>
 8006a98:	2300      	movs	r3, #0
 8006a9a:	e7b2      	b.n	8006a02 <_dtoa_r+0x242>
 8006a9c:	2300      	movs	r3, #0
 8006a9e:	e7f0      	b.n	8006a82 <_dtoa_r+0x2c2>
 8006aa0:	2501      	movs	r5, #1
 8006aa2:	2300      	movs	r3, #0
 8006aa4:	9509      	str	r5, [sp, #36]	; 0x24
 8006aa6:	931e      	str	r3, [sp, #120]	; 0x78
 8006aa8:	f04f 33ff 	mov.w	r3, #4294967295
 8006aac:	2200      	movs	r2, #0
 8006aae:	9304      	str	r3, [sp, #16]
 8006ab0:	4698      	mov	r8, r3
 8006ab2:	2312      	movs	r3, #18
 8006ab4:	921f      	str	r2, [sp, #124]	; 0x7c
 8006ab6:	e7aa      	b.n	8006a0e <_dtoa_r+0x24e>
 8006ab8:	2301      	movs	r3, #1
 8006aba:	9309      	str	r3, [sp, #36]	; 0x24
 8006abc:	e7f4      	b.n	8006aa8 <_dtoa_r+0x2e8>
 8006abe:	bf00      	nop
 8006ac0:	636f4361 	.word	0x636f4361
 8006ac4:	3fd287a7 	.word	0x3fd287a7
 8006ac8:	8b60c8b3 	.word	0x8b60c8b3
 8006acc:	3fc68a28 	.word	0x3fc68a28
 8006ad0:	509f79fb 	.word	0x509f79fb
 8006ad4:	3fd34413 	.word	0x3fd34413
 8006ad8:	7ff00000 	.word	0x7ff00000
 8006adc:	08008639 	.word	0x08008639
 8006ae0:	08008630 	.word	0x08008630
 8006ae4:	0800860d 	.word	0x0800860d
 8006ae8:	3ff80000 	.word	0x3ff80000
 8006aec:	080086c8 	.word	0x080086c8
 8006af0:	080086a0 	.word	0x080086a0
 8006af4:	2301      	movs	r3, #1
 8006af6:	9304      	str	r3, [sp, #16]
 8006af8:	4698      	mov	r8, r3
 8006afa:	461a      	mov	r2, r3
 8006afc:	e7da      	b.n	8006ab4 <_dtoa_r+0x2f4>
 8006afe:	3101      	adds	r1, #1
 8006b00:	6071      	str	r1, [r6, #4]
 8006b02:	0052      	lsls	r2, r2, #1
 8006b04:	e787      	b.n	8006a16 <_dtoa_r+0x256>
 8006b06:	07f1      	lsls	r1, r6, #31
 8006b08:	d508      	bpl.n	8006b1c <_dtoa_r+0x35c>
 8006b0a:	e9dd 010a 	ldrd	r0, r1, [sp, #40]	; 0x28
 8006b0e:	e9d7 2300 	ldrd	r2, r3, [r7]
 8006b12:	f7f9 fd41 	bl	8000598 <__aeabi_dmul>
 8006b16:	e9cd 010a 	strd	r0, r1, [sp, #40]	; 0x28
 8006b1a:	3501      	adds	r5, #1
 8006b1c:	1076      	asrs	r6, r6, #1
 8006b1e:	3708      	adds	r7, #8
 8006b20:	2e00      	cmp	r6, #0
 8006b22:	d1f0      	bne.n	8006b06 <_dtoa_r+0x346>
 8006b24:	e9dd 230a 	ldrd	r2, r3, [sp, #40]	; 0x28
 8006b28:	e9dd 0102 	ldrd	r0, r1, [sp, #8]
 8006b2c:	f7f9 fe5e 	bl	80007ec <__aeabi_ddiv>
 8006b30:	e9cd 0102 	strd	r0, r1, [sp, #8]
 8006b34:	e01b      	b.n	8006b6e <_dtoa_r+0x3ae>
 8006b36:	2502      	movs	r5, #2
 8006b38:	e7a0      	b.n	8006a7c <_dtoa_r+0x2bc>
 8006b3a:	f000 80a4 	beq.w	8006c86 <_dtoa_r+0x4c6>
 8006b3e:	e9dd 010e 	ldrd	r0, r1, [sp, #56]	; 0x38
 8006b42:	f1ca 0600 	rsb	r6, sl, #0
 8006b46:	4ba0      	ldr	r3, [pc, #640]	; (8006dc8 <_dtoa_r+0x608>)
 8006b48:	f006 020f 	and.w	r2, r6, #15
 8006b4c:	eb03 03c2 	add.w	r3, r3, r2, lsl #3
 8006b50:	e9d3 2300 	ldrd	r2, r3, [r3]
 8006b54:	f7f9 fd20 	bl	8000598 <__aeabi_dmul>
 8006b58:	2502      	movs	r5, #2
 8006b5a:	2300      	movs	r3, #0
 8006b5c:	e9cd 0102 	strd	r0, r1, [sp, #8]
 8006b60:	4f9a      	ldr	r7, [pc, #616]	; (8006dcc <_dtoa_r+0x60c>)
 8006b62:	1136      	asrs	r6, r6, #4
 8006b64:	2e00      	cmp	r6, #0
 8006b66:	f040 8083 	bne.w	8006c70 <_dtoa_r+0x4b0>
 8006b6a:	2b00      	cmp	r3, #0
 8006b6c:	d1e0      	bne.n	8006b30 <_dtoa_r+0x370>
 8006b6e:	9b0d      	ldr	r3, [sp, #52]	; 0x34
 8006b70:	2b00      	cmp	r3, #0
 8006b72:	f000 808a 	beq.w	8006c8a <_dtoa_r+0x4ca>
 8006b76:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
 8006b7a:	e9cd 230a 	strd	r2, r3, [sp, #40]	; 0x28
 8006b7e:	e9dd 010a 	ldrd	r0, r1, [sp, #40]	; 0x28
 8006b82:	2200      	movs	r2, #0
 8006b84:	4b92      	ldr	r3, [pc, #584]	; (8006dd0 <_dtoa_r+0x610>)
 8006b86:	f7f9 ff79 	bl	8000a7c <__aeabi_dcmplt>
 8006b8a:	2800      	cmp	r0, #0
 8006b8c:	d07d      	beq.n	8006c8a <_dtoa_r+0x4ca>
 8006b8e:	f1b8 0f00 	cmp.w	r8, #0
 8006b92:	d07a      	beq.n	8006c8a <_dtoa_r+0x4ca>
 8006b94:	9b04      	ldr	r3, [sp, #16]
 8006b96:	2b00      	cmp	r3, #0
 8006b98:	dd36      	ble.n	8006c08 <_dtoa_r+0x448>
 8006b9a:	e9dd 010a 	ldrd	r0, r1, [sp, #40]	; 0x28
 8006b9e:	2200      	movs	r2, #0
 8006ba0:	4b8c      	ldr	r3, [pc, #560]	; (8006dd4 <_dtoa_r+0x614>)
 8006ba2:	f7f9 fcf9 	bl	8000598 <__aeabi_dmul>
 8006ba6:	e9cd 0102 	strd	r0, r1, [sp, #8]
 8006baa:	9e04      	ldr	r6, [sp, #16]
 8006bac:	f10a 37ff 	add.w	r7, sl, #4294967295
 8006bb0:	3501      	adds	r5, #1
 8006bb2:	4628      	mov	r0, r5
 8006bb4:	f7f9 fc86 	bl	80004c4 <__aeabi_i2d>
 8006bb8:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
 8006bbc:	f7f9 fcec 	bl	8000598 <__aeabi_dmul>
 8006bc0:	2200      	movs	r2, #0
 8006bc2:	4b85      	ldr	r3, [pc, #532]	; (8006dd8 <_dtoa_r+0x618>)
 8006bc4:	f7f9 fb32 	bl	800022c <__adddf3>
 8006bc8:	f1a1 7550 	sub.w	r5, r1, #54525952	; 0x3400000
 8006bcc:	e9cd 010a 	strd	r0, r1, [sp, #40]	; 0x28
 8006bd0:	950b      	str	r5, [sp, #44]	; 0x2c
 8006bd2:	2e00      	cmp	r6, #0
 8006bd4:	d15c      	bne.n	8006c90 <_dtoa_r+0x4d0>
 8006bd6:	e9dd 0102 	ldrd	r0, r1, [sp, #8]
 8006bda:	2200      	movs	r2, #0
 8006bdc:	4b7f      	ldr	r3, [pc, #508]	; (8006ddc <_dtoa_r+0x61c>)
 8006bde:	f7f9 fb23 	bl	8000228 <__aeabi_dsub>
 8006be2:	9a0a      	ldr	r2, [sp, #40]	; 0x28
 8006be4:	462b      	mov	r3, r5
 8006be6:	e9cd 0102 	strd	r0, r1, [sp, #8]
 8006bea:	f7f9 ff65 	bl	8000ab8 <__aeabi_dcmpgt>
 8006bee:	2800      	cmp	r0, #0
 8006bf0:	f040 8281 	bne.w	80070f6 <_dtoa_r+0x936>
 8006bf4:	e9dd 0102 	ldrd	r0, r1, [sp, #8]
 8006bf8:	9a0a      	ldr	r2, [sp, #40]	; 0x28
 8006bfa:	f105 4300 	add.w	r3, r5, #2147483648	; 0x80000000
 8006bfe:	f7f9 ff3d 	bl	8000a7c <__aeabi_dcmplt>
 8006c02:	2800      	cmp	r0, #0
 8006c04:	f040 8275 	bne.w	80070f2 <_dtoa_r+0x932>
 8006c08:	e9dd 230e 	ldrd	r2, r3, [sp, #56]	; 0x38
 8006c0c:	e9cd 2302 	strd	r2, r3, [sp, #8]
 8006c10:	9b13      	ldr	r3, [sp, #76]	; 0x4c
 8006c12:	2b00      	cmp	r3, #0
 8006c14:	f2c0 814b 	blt.w	8006eae <_dtoa_r+0x6ee>
 8006c18:	f1ba 0f0e 	cmp.w	sl, #14
 8006c1c:	f300 8147 	bgt.w	8006eae <_dtoa_r+0x6ee>
 8006c20:	4b69      	ldr	r3, [pc, #420]	; (8006dc8 <_dtoa_r+0x608>)
 8006c22:	eb03 03ca 	add.w	r3, r3, sl, lsl #3
 8006c26:	e9d3 2300 	ldrd	r2, r3, [r3]
 8006c2a:	e9cd 2304 	strd	r2, r3, [sp, #16]
 8006c2e:	9b1f      	ldr	r3, [sp, #124]	; 0x7c
 8006c30:	2b00      	cmp	r3, #0
 8006c32:	f280 80d7 	bge.w	8006de4 <_dtoa_r+0x624>
 8006c36:	f1b8 0f00 	cmp.w	r8, #0
 8006c3a:	f300 80d3 	bgt.w	8006de4 <_dtoa_r+0x624>
 8006c3e:	f040 8257 	bne.w	80070f0 <_dtoa_r+0x930>
 8006c42:	e9dd 0104 	ldrd	r0, r1, [sp, #16]
 8006c46:	2200      	movs	r2, #0
 8006c48:	4b64      	ldr	r3, [pc, #400]	; (8006ddc <_dtoa_r+0x61c>)
 8006c4a:	f7f9 fca5 	bl	8000598 <__aeabi_dmul>
 8006c4e:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
 8006c52:	f7f9 ff27 	bl	8000aa4 <__aeabi_dcmpge>
 8006c56:	4646      	mov	r6, r8
 8006c58:	4647      	mov	r7, r8
 8006c5a:	2800      	cmp	r0, #0
 8006c5c:	f040 822d 	bne.w	80070ba <_dtoa_r+0x8fa>
 8006c60:	9b06      	ldr	r3, [sp, #24]
 8006c62:	9a06      	ldr	r2, [sp, #24]
 8006c64:	1c5d      	adds	r5, r3, #1
 8006c66:	2331      	movs	r3, #49	; 0x31
 8006c68:	f10a 0a01 	add.w	sl, sl, #1
 8006c6c:	7013      	strb	r3, [r2, #0]
 8006c6e:	e228      	b.n	80070c2 <_dtoa_r+0x902>
 8006c70:	07f2      	lsls	r2, r6, #31
 8006c72:	d505      	bpl.n	8006c80 <_dtoa_r+0x4c0>
 8006c74:	e9d7 2300 	ldrd	r2, r3, [r7]
 8006c78:	f7f9 fc8e 	bl	8000598 <__aeabi_dmul>
 8006c7c:	2301      	movs	r3, #1
 8006c7e:	3501      	adds	r5, #1
 8006c80:	1076      	asrs	r6, r6, #1
 8006c82:	3708      	adds	r7, #8
 8006c84:	e76e      	b.n	8006b64 <_dtoa_r+0x3a4>
 8006c86:	2502      	movs	r5, #2
 8006c88:	e771      	b.n	8006b6e <_dtoa_r+0x3ae>
 8006c8a:	4657      	mov	r7, sl
 8006c8c:	4646      	mov	r6, r8
 8006c8e:	e790      	b.n	8006bb2 <_dtoa_r+0x3f2>
 8006c90:	4b4d      	ldr	r3, [pc, #308]	; (8006dc8 <_dtoa_r+0x608>)
 8006c92:	eb03 03c6 	add.w	r3, r3, r6, lsl #3
 8006c96:	e953 0102 	ldrd	r0, r1, [r3, #-8]
 8006c9a:	9b09      	ldr	r3, [sp, #36]	; 0x24
 8006c9c:	2b00      	cmp	r3, #0
 8006c9e:	d048      	beq.n	8006d32 <_dtoa_r+0x572>
 8006ca0:	4602      	mov	r2, r0
 8006ca2:	460b      	mov	r3, r1
 8006ca4:	2000      	movs	r0, #0
 8006ca6:	494e      	ldr	r1, [pc, #312]	; (8006de0 <_dtoa_r+0x620>)
 8006ca8:	f7f9 fda0 	bl	80007ec <__aeabi_ddiv>
 8006cac:	e9dd 230a 	ldrd	r2, r3, [sp, #40]	; 0x28
 8006cb0:	f7f9 faba 	bl	8000228 <__aeabi_dsub>
 8006cb4:	e9cd 010a 	strd	r0, r1, [sp, #40]	; 0x28
 8006cb8:	9d06      	ldr	r5, [sp, #24]
 8006cba:	e9dd 0102 	ldrd	r0, r1, [sp, #8]
 8006cbe:	f7f9 ff1b 	bl	8000af8 <__aeabi_d2iz>
 8006cc2:	9011      	str	r0, [sp, #68]	; 0x44
 8006cc4:	f7f9 fbfe 	bl	80004c4 <__aeabi_i2d>
 8006cc8:	4602      	mov	r2, r0
 8006cca:	460b      	mov	r3, r1
 8006ccc:	e9dd 0102 	ldrd	r0, r1, [sp, #8]
 8006cd0:	f7f9 faaa 	bl	8000228 <__aeabi_dsub>
 8006cd4:	9b11      	ldr	r3, [sp, #68]	; 0x44
 8006cd6:	e9cd 0102 	strd	r0, r1, [sp, #8]
 8006cda:	3330      	adds	r3, #48	; 0x30
 8006cdc:	f805 3b01 	strb.w	r3, [r5], #1
 8006ce0:	e9dd 230a 	ldrd	r2, r3, [sp, #40]	; 0x28
 8006ce4:	f7f9 feca 	bl	8000a7c <__aeabi_dcmplt>
 8006ce8:	2800      	cmp	r0, #0
 8006cea:	d163      	bne.n	8006db4 <_dtoa_r+0x5f4>
 8006cec:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
 8006cf0:	2000      	movs	r0, #0
 8006cf2:	4937      	ldr	r1, [pc, #220]	; (8006dd0 <_dtoa_r+0x610>)
 8006cf4:	f7f9 fa98 	bl	8000228 <__aeabi_dsub>
 8006cf8:	e9dd 230a 	ldrd	r2, r3, [sp, #40]	; 0x28
 8006cfc:	f7f9 febe 	bl	8000a7c <__aeabi_dcmplt>
 8006d00:	2800      	cmp	r0, #0
 8006d02:	f040 80b5 	bne.w	8006e70 <_dtoa_r+0x6b0>
 8006d06:	9b06      	ldr	r3, [sp, #24]
 8006d08:	1aeb      	subs	r3, r5, r3
 8006d0a:	429e      	cmp	r6, r3
 8006d0c:	f77f af7c 	ble.w	8006c08 <_dtoa_r+0x448>
 8006d10:	e9dd 010a 	ldrd	r0, r1, [sp, #40]	; 0x28
 8006d14:	2200      	movs	r2, #0
 8006d16:	4b2f      	ldr	r3, [pc, #188]	; (8006dd4 <_dtoa_r+0x614>)
 8006d18:	f7f9 fc3e 	bl	8000598 <__aeabi_dmul>
 8006d1c:	2200      	movs	r2, #0
 8006d1e:	e9cd 010a 	strd	r0, r1, [sp, #40]	; 0x28
 8006d22:	e9dd 0102 	ldrd	r0, r1, [sp, #8]
 8006d26:	4b2b      	ldr	r3, [pc, #172]	; (8006dd4 <_dtoa_r+0x614>)
 8006d28:	f7f9 fc36 	bl	8000598 <__aeabi_dmul>
 8006d2c:	e9cd 0102 	strd	r0, r1, [sp, #8]
 8006d30:	e7c3      	b.n	8006cba <_dtoa_r+0x4fa>
 8006d32:	e9dd 230a 	ldrd	r2, r3, [sp, #40]	; 0x28
 8006d36:	f7f9 fc2f 	bl	8000598 <__aeabi_dmul>
 8006d3a:	9b06      	ldr	r3, [sp, #24]
 8006d3c:	e9cd 010a 	strd	r0, r1, [sp, #40]	; 0x28
 8006d40:	199d      	adds	r5, r3, r6
 8006d42:	461e      	mov	r6, r3
 8006d44:	e9dd 0102 	ldrd	r0, r1, [sp, #8]
 8006d48:	f7f9 fed6 	bl	8000af8 <__aeabi_d2iz>
 8006d4c:	9011      	str	r0, [sp, #68]	; 0x44
 8006d4e:	f7f9 fbb9 	bl	80004c4 <__aeabi_i2d>
 8006d52:	4602      	mov	r2, r0
 8006d54:	460b      	mov	r3, r1
 8006d56:	e9dd 0102 	ldrd	r0, r1, [sp, #8]
 8006d5a:	f7f9 fa65 	bl	8000228 <__aeabi_dsub>
 8006d5e:	9b11      	ldr	r3, [sp, #68]	; 0x44
 8006d60:	e9cd 0102 	strd	r0, r1, [sp, #8]
 8006d64:	3330      	adds	r3, #48	; 0x30
 8006d66:	f806 3b01 	strb.w	r3, [r6], #1
 8006d6a:	42ae      	cmp	r6, r5
 8006d6c:	f04f 0200 	mov.w	r2, #0
 8006d70:	d124      	bne.n	8006dbc <_dtoa_r+0x5fc>
 8006d72:	e9dd 010a 	ldrd	r0, r1, [sp, #40]	; 0x28
 8006d76:	4b1a      	ldr	r3, [pc, #104]	; (8006de0 <_dtoa_r+0x620>)
 8006d78:	f7f9 fa58 	bl	800022c <__adddf3>
 8006d7c:	4602      	mov	r2, r0
 8006d7e:	460b      	mov	r3, r1
 8006d80:	e9dd 0102 	ldrd	r0, r1, [sp, #8]
 8006d84:	f7f9 fe98 	bl	8000ab8 <__aeabi_dcmpgt>
 8006d88:	2800      	cmp	r0, #0
 8006d8a:	d171      	bne.n	8006e70 <_dtoa_r+0x6b0>
 8006d8c:	e9dd 230a 	ldrd	r2, r3, [sp, #40]	; 0x28
 8006d90:	2000      	movs	r0, #0
 8006d92:	4913      	ldr	r1, [pc, #76]	; (8006de0 <_dtoa_r+0x620>)
 8006d94:	f7f9 fa48 	bl	8000228 <__aeabi_dsub>
 8006d98:	4602      	mov	r2, r0
 8006d9a:	460b      	mov	r3, r1
 8006d9c:	e9dd 0102 	ldrd	r0, r1, [sp, #8]
 8006da0:	f7f9 fe6c 	bl	8000a7c <__aeabi_dcmplt>
 8006da4:	2800      	cmp	r0, #0
 8006da6:	f43f af2f 	beq.w	8006c08 <_dtoa_r+0x448>
 8006daa:	f815 3c01 	ldrb.w	r3, [r5, #-1]
 8006dae:	1e6a      	subs	r2, r5, #1
 8006db0:	2b30      	cmp	r3, #48	; 0x30
 8006db2:	d001      	beq.n	8006db8 <_dtoa_r+0x5f8>
 8006db4:	46ba      	mov	sl, r7
 8006db6:	e04a      	b.n	8006e4e <_dtoa_r+0x68e>
 8006db8:	4615      	mov	r5, r2
 8006dba:	e7f6      	b.n	8006daa <_dtoa_r+0x5ea>
 8006dbc:	4b05      	ldr	r3, [pc, #20]	; (8006dd4 <_dtoa_r+0x614>)
 8006dbe:	f7f9 fbeb 	bl	8000598 <__aeabi_dmul>
 8006dc2:	e9cd 0102 	strd	r0, r1, [sp, #8]
 8006dc6:	e7bd      	b.n	8006d44 <_dtoa_r+0x584>
 8006dc8:	080086c8 	.word	0x080086c8
 8006dcc:	080086a0 	.word	0x080086a0
 8006dd0:	3ff00000 	.word	0x3ff00000
 8006dd4:	40240000 	.word	0x40240000
 8006dd8:	401c0000 	.word	0x401c0000
 8006ddc:	40140000 	.word	0x40140000
 8006de0:	3fe00000 	.word	0x3fe00000
 8006de4:	9d06      	ldr	r5, [sp, #24]
 8006de6:	e9dd 6702 	ldrd	r6, r7, [sp, #8]
 8006dea:	e9dd 2304 	ldrd	r2, r3, [sp, #16]
 8006dee:	4630      	mov	r0, r6
 8006df0:	4639      	mov	r1, r7
 8006df2:	f7f9 fcfb 	bl	80007ec <__aeabi_ddiv>
 8006df6:	f7f9 fe7f 	bl	8000af8 <__aeabi_d2iz>
 8006dfa:	4681      	mov	r9, r0
 8006dfc:	f7f9 fb62 	bl	80004c4 <__aeabi_i2d>
 8006e00:	e9dd 2304 	ldrd	r2, r3, [sp, #16]
 8006e04:	f7f9 fbc8 	bl	8000598 <__aeabi_dmul>
 8006e08:	4602      	mov	r2, r0
 8006e0a:	460b      	mov	r3, r1
 8006e0c:	4630      	mov	r0, r6
 8006e0e:	4639      	mov	r1, r7
 8006e10:	f7f9 fa0a 	bl	8000228 <__aeabi_dsub>
 8006e14:	f109 0630 	add.w	r6, r9, #48	; 0x30
 8006e18:	f805 6b01 	strb.w	r6, [r5], #1
 8006e1c:	9e06      	ldr	r6, [sp, #24]
 8006e1e:	4602      	mov	r2, r0
 8006e20:	1bae      	subs	r6, r5, r6
 8006e22:	45b0      	cmp	r8, r6
 8006e24:	460b      	mov	r3, r1
 8006e26:	d135      	bne.n	8006e94 <_dtoa_r+0x6d4>
 8006e28:	f7f9 fa00 	bl	800022c <__adddf3>
 8006e2c:	e9dd 2304 	ldrd	r2, r3, [sp, #16]
 8006e30:	4606      	mov	r6, r0
 8006e32:	460f      	mov	r7, r1
 8006e34:	f7f9 fe40 	bl	8000ab8 <__aeabi_dcmpgt>
 8006e38:	b9c8      	cbnz	r0, 8006e6e <_dtoa_r+0x6ae>
 8006e3a:	e9dd 2304 	ldrd	r2, r3, [sp, #16]
 8006e3e:	4630      	mov	r0, r6
 8006e40:	4639      	mov	r1, r7
 8006e42:	f7f9 fe11 	bl	8000a68 <__aeabi_dcmpeq>
 8006e46:	b110      	cbz	r0, 8006e4e <_dtoa_r+0x68e>
 8006e48:	f019 0f01 	tst.w	r9, #1
 8006e4c:	d10f      	bne.n	8006e6e <_dtoa_r+0x6ae>
 8006e4e:	4659      	mov	r1, fp
 8006e50:	4620      	mov	r0, r4
 8006e52:	f000 fcaa 	bl	80077aa <_Bfree>
 8006e56:	2300      	movs	r3, #0
 8006e58:	9a20      	ldr	r2, [sp, #128]	; 0x80
 8006e5a:	702b      	strb	r3, [r5, #0]
 8006e5c:	f10a 0301 	add.w	r3, sl, #1
 8006e60:	6013      	str	r3, [r2, #0]
 8006e62:	9b22      	ldr	r3, [sp, #136]	; 0x88
 8006e64:	2b00      	cmp	r3, #0
 8006e66:	f43f acf3 	beq.w	8006850 <_dtoa_r+0x90>
 8006e6a:	601d      	str	r5, [r3, #0]
 8006e6c:	e4f0      	b.n	8006850 <_dtoa_r+0x90>
 8006e6e:	4657      	mov	r7, sl
 8006e70:	f815 2c01 	ldrb.w	r2, [r5, #-1]
 8006e74:	1e6b      	subs	r3, r5, #1
 8006e76:	2a39      	cmp	r2, #57	; 0x39
 8006e78:	d106      	bne.n	8006e88 <_dtoa_r+0x6c8>
 8006e7a:	9a06      	ldr	r2, [sp, #24]
 8006e7c:	429a      	cmp	r2, r3
 8006e7e:	d107      	bne.n	8006e90 <_dtoa_r+0x6d0>
 8006e80:	2330      	movs	r3, #48	; 0x30
 8006e82:	7013      	strb	r3, [r2, #0]
 8006e84:	4613      	mov	r3, r2
 8006e86:	3701      	adds	r7, #1
 8006e88:	781a      	ldrb	r2, [r3, #0]
 8006e8a:	3201      	adds	r2, #1
 8006e8c:	701a      	strb	r2, [r3, #0]
 8006e8e:	e791      	b.n	8006db4 <_dtoa_r+0x5f4>
 8006e90:	461d      	mov	r5, r3
 8006e92:	e7ed      	b.n	8006e70 <_dtoa_r+0x6b0>
 8006e94:	2200      	movs	r2, #0
 8006e96:	4b99      	ldr	r3, [pc, #612]	; (80070fc <_dtoa_r+0x93c>)
 8006e98:	f7f9 fb7e 	bl	8000598 <__aeabi_dmul>
 8006e9c:	2200      	movs	r2, #0
 8006e9e:	2300      	movs	r3, #0
 8006ea0:	4606      	mov	r6, r0
 8006ea2:	460f      	mov	r7, r1
 8006ea4:	f7f9 fde0 	bl	8000a68 <__aeabi_dcmpeq>
 8006ea8:	2800      	cmp	r0, #0
 8006eaa:	d09e      	beq.n	8006dea <_dtoa_r+0x62a>
 8006eac:	e7cf      	b.n	8006e4e <_dtoa_r+0x68e>
 8006eae:	9a09      	ldr	r2, [sp, #36]	; 0x24
 8006eb0:	2a00      	cmp	r2, #0
 8006eb2:	f000 8088 	beq.w	8006fc6 <_dtoa_r+0x806>
 8006eb6:	9a1e      	ldr	r2, [sp, #120]	; 0x78
 8006eb8:	2a01      	cmp	r2, #1
 8006eba:	dc6d      	bgt.n	8006f98 <_dtoa_r+0x7d8>
 8006ebc:	9a10      	ldr	r2, [sp, #64]	; 0x40
 8006ebe:	2a00      	cmp	r2, #0
 8006ec0:	d066      	beq.n	8006f90 <_dtoa_r+0x7d0>
 8006ec2:	f203 4333 	addw	r3, r3, #1075	; 0x433
 8006ec6:	464d      	mov	r5, r9
 8006ec8:	9e08      	ldr	r6, [sp, #32]
 8006eca:	9a07      	ldr	r2, [sp, #28]
 8006ecc:	2101      	movs	r1, #1
 8006ece:	441a      	add	r2, r3
 8006ed0:	4620      	mov	r0, r4
 8006ed2:	4499      	add	r9, r3
 8006ed4:	9207      	str	r2, [sp, #28]
 8006ed6:	f000 fd08 	bl	80078ea <__i2b>
 8006eda:	4607      	mov	r7, r0
 8006edc:	2d00      	cmp	r5, #0
 8006ede:	dd0b      	ble.n	8006ef8 <_dtoa_r+0x738>
 8006ee0:	9b07      	ldr	r3, [sp, #28]
 8006ee2:	2b00      	cmp	r3, #0
 8006ee4:	dd08      	ble.n	8006ef8 <_dtoa_r+0x738>
 8006ee6:	42ab      	cmp	r3, r5
 8006ee8:	bfa8      	it	ge
 8006eea:	462b      	movge	r3, r5
 8006eec:	9a07      	ldr	r2, [sp, #28]
 8006eee:	eba9 0903 	sub.w	r9, r9, r3
 8006ef2:	1aed      	subs	r5, r5, r3
 8006ef4:	1ad3      	subs	r3, r2, r3
 8006ef6:	9307      	str	r3, [sp, #28]
 8006ef8:	9b08      	ldr	r3, [sp, #32]
 8006efa:	b1eb      	cbz	r3, 8006f38 <_dtoa_r+0x778>
 8006efc:	9b09      	ldr	r3, [sp, #36]	; 0x24
 8006efe:	2b00      	cmp	r3, #0
 8006f00:	d065      	beq.n	8006fce <_dtoa_r+0x80e>
 8006f02:	b18e      	cbz	r6, 8006f28 <_dtoa_r+0x768>
 8006f04:	4639      	mov	r1, r7
 8006f06:	4632      	mov	r2, r6
 8006f08:	4620      	mov	r0, r4
 8006f0a:	f000 fd8d 	bl	8007a28 <__pow5mult>
 8006f0e:	465a      	mov	r2, fp
 8006f10:	4601      	mov	r1, r0
 8006f12:	4607      	mov	r7, r0
 8006f14:	4620      	mov	r0, r4
 8006f16:	f000 fcf1 	bl	80078fc <__multiply>
 8006f1a:	4659      	mov	r1, fp
 8006f1c:	900a      	str	r0, [sp, #40]	; 0x28
 8006f1e:	4620      	mov	r0, r4
 8006f20:	f000 fc43 	bl	80077aa <_Bfree>
 8006f24:	9b0a      	ldr	r3, [sp, #40]	; 0x28
 8006f26:	469b      	mov	fp, r3
 8006f28:	9b08      	ldr	r3, [sp, #32]
 8006f2a:	1b9a      	subs	r2, r3, r6
 8006f2c:	d004      	beq.n	8006f38 <_dtoa_r+0x778>
 8006f2e:	4659      	mov	r1, fp
 8006f30:	4620      	mov	r0, r4
 8006f32:	f000 fd79 	bl	8007a28 <__pow5mult>
 8006f36:	4683      	mov	fp, r0
 8006f38:	2101      	movs	r1, #1
 8006f3a:	4620      	mov	r0, r4
 8006f3c:	f000 fcd5 	bl	80078ea <__i2b>
 8006f40:	9b0c      	ldr	r3, [sp, #48]	; 0x30
 8006f42:	4606      	mov	r6, r0
 8006f44:	2b00      	cmp	r3, #0
 8006f46:	f000 81c6 	beq.w	80072d6 <_dtoa_r+0xb16>
 8006f4a:	461a      	mov	r2, r3
 8006f4c:	4601      	mov	r1, r0
 8006f4e:	4620      	mov	r0, r4
 8006f50:	f000 fd6a 	bl	8007a28 <__pow5mult>
 8006f54:	9b1e      	ldr	r3, [sp, #120]	; 0x78
 8006f56:	4606      	mov	r6, r0
 8006f58:	2b01      	cmp	r3, #1
 8006f5a:	dc3e      	bgt.n	8006fda <_dtoa_r+0x81a>
 8006f5c:	9b02      	ldr	r3, [sp, #8]
 8006f5e:	2b00      	cmp	r3, #0
 8006f60:	d137      	bne.n	8006fd2 <_dtoa_r+0x812>
 8006f62:	9b03      	ldr	r3, [sp, #12]
 8006f64:	f3c3 0313 	ubfx	r3, r3, #0, #20
 8006f68:	2b00      	cmp	r3, #0
 8006f6a:	d134      	bne.n	8006fd6 <_dtoa_r+0x816>
 8006f6c:	9b03      	ldr	r3, [sp, #12]
 8006f6e:	f023 4300 	bic.w	r3, r3, #2147483648	; 0x80000000
 8006f72:	0d1b      	lsrs	r3, r3, #20
 8006f74:	051b      	lsls	r3, r3, #20
 8006f76:	b12b      	cbz	r3, 8006f84 <_dtoa_r+0x7c4>
 8006f78:	9b07      	ldr	r3, [sp, #28]
 8006f7a:	f109 0901 	add.w	r9, r9, #1
 8006f7e:	3301      	adds	r3, #1
 8006f80:	9307      	str	r3, [sp, #28]
 8006f82:	2301      	movs	r3, #1
 8006f84:	9308      	str	r3, [sp, #32]
 8006f86:	9b0c      	ldr	r3, [sp, #48]	; 0x30
 8006f88:	2b00      	cmp	r3, #0
 8006f8a:	d128      	bne.n	8006fde <_dtoa_r+0x81e>
 8006f8c:	2001      	movs	r0, #1
 8006f8e:	e02e      	b.n	8006fee <_dtoa_r+0x82e>
 8006f90:	9b12      	ldr	r3, [sp, #72]	; 0x48
 8006f92:	f1c3 0336 	rsb	r3, r3, #54	; 0x36
 8006f96:	e796      	b.n	8006ec6 <_dtoa_r+0x706>
 8006f98:	9b08      	ldr	r3, [sp, #32]
 8006f9a:	f108 36ff 	add.w	r6, r8, #4294967295
 8006f9e:	42b3      	cmp	r3, r6
 8006fa0:	bfb7      	itett	lt
 8006fa2:	9b08      	ldrlt	r3, [sp, #32]
 8006fa4:	1b9e      	subge	r6, r3, r6
 8006fa6:	1af2      	sublt	r2, r6, r3
 8006fa8:	9b0c      	ldrlt	r3, [sp, #48]	; 0x30
 8006faa:	bfbf      	itttt	lt
 8006fac:	9608      	strlt	r6, [sp, #32]
 8006fae:	189b      	addlt	r3, r3, r2
 8006fb0:	930c      	strlt	r3, [sp, #48]	; 0x30
 8006fb2:	2600      	movlt	r6, #0
 8006fb4:	f1b8 0f00 	cmp.w	r8, #0
 8006fb8:	bfb9      	ittee	lt
 8006fba:	eba9 0508 	sublt.w	r5, r9, r8
 8006fbe:	2300      	movlt	r3, #0
 8006fc0:	464d      	movge	r5, r9
 8006fc2:	4643      	movge	r3, r8
 8006fc4:	e781      	b.n	8006eca <_dtoa_r+0x70a>
 8006fc6:	9e08      	ldr	r6, [sp, #32]
 8006fc8:	464d      	mov	r5, r9
 8006fca:	9f09      	ldr	r7, [sp, #36]	; 0x24
 8006fcc:	e786      	b.n	8006edc <_dtoa_r+0x71c>
 8006fce:	9a08      	ldr	r2, [sp, #32]
 8006fd0:	e7ad      	b.n	8006f2e <_dtoa_r+0x76e>
 8006fd2:	2300      	movs	r3, #0
 8006fd4:	e7d6      	b.n	8006f84 <_dtoa_r+0x7c4>
 8006fd6:	9b02      	ldr	r3, [sp, #8]
 8006fd8:	e7d4      	b.n	8006f84 <_dtoa_r+0x7c4>
 8006fda:	2300      	movs	r3, #0
 8006fdc:	9308      	str	r3, [sp, #32]
 8006fde:	6933      	ldr	r3, [r6, #16]
 8006fe0:	eb06 0383 	add.w	r3, r6, r3, lsl #2
 8006fe4:	6918      	ldr	r0, [r3, #16]
 8006fe6:	f000 fc32 	bl	800784e <__hi0bits>
 8006fea:	f1c0 0020 	rsb	r0, r0, #32
 8006fee:	9b07      	ldr	r3, [sp, #28]
 8006ff0:	4418      	add	r0, r3
 8006ff2:	f010 001f 	ands.w	r0, r0, #31
 8006ff6:	d047      	beq.n	8007088 <_dtoa_r+0x8c8>
 8006ff8:	f1c0 0320 	rsb	r3, r0, #32
 8006ffc:	2b04      	cmp	r3, #4
 8006ffe:	dd3b      	ble.n	8007078 <_dtoa_r+0x8b8>
 8007000:	9b07      	ldr	r3, [sp, #28]
 8007002:	f1c0 001c 	rsb	r0, r0, #28
 8007006:	4481      	add	r9, r0
 8007008:	4405      	add	r5, r0
 800700a:	4403      	add	r3, r0
 800700c:	9307      	str	r3, [sp, #28]
 800700e:	f1b9 0f00 	cmp.w	r9, #0
 8007012:	dd05      	ble.n	8007020 <_dtoa_r+0x860>
 8007014:	4659      	mov	r1, fp
 8007016:	464a      	mov	r2, r9
 8007018:	4620      	mov	r0, r4
 800701a:	f000 fd53 	bl	8007ac4 <__lshift>
 800701e:	4683      	mov	fp, r0
 8007020:	9b07      	ldr	r3, [sp, #28]
 8007022:	2b00      	cmp	r3, #0
 8007024:	dd05      	ble.n	8007032 <_dtoa_r+0x872>
 8007026:	4631      	mov	r1, r6
 8007028:	461a      	mov	r2, r3
 800702a:	4620      	mov	r0, r4
 800702c:	f000 fd4a 	bl	8007ac4 <__lshift>
 8007030:	4606      	mov	r6, r0
 8007032:	9b0d      	ldr	r3, [sp, #52]	; 0x34
 8007034:	b353      	cbz	r3, 800708c <_dtoa_r+0x8cc>
 8007036:	4631      	mov	r1, r6
 8007038:	4658      	mov	r0, fp
 800703a:	f000 fd97 	bl	8007b6c <__mcmp>
 800703e:	2800      	cmp	r0, #0
 8007040:	da24      	bge.n	800708c <_dtoa_r+0x8cc>
 8007042:	2300      	movs	r3, #0
 8007044:	4659      	mov	r1, fp
 8007046:	220a      	movs	r2, #10
 8007048:	4620      	mov	r0, r4
 800704a:	f000 fbc5 	bl	80077d8 <__multadd>
 800704e:	9b09      	ldr	r3, [sp, #36]	; 0x24
 8007050:	f10a 3aff 	add.w	sl, sl, #4294967295
 8007054:	4683      	mov	fp, r0
 8007056:	2b00      	cmp	r3, #0
 8007058:	f000 8144 	beq.w	80072e4 <_dtoa_r+0xb24>
 800705c:	2300      	movs	r3, #0
 800705e:	4639      	mov	r1, r7
 8007060:	220a      	movs	r2, #10
 8007062:	4620      	mov	r0, r4
 8007064:	f000 fbb8 	bl	80077d8 <__multadd>
 8007068:	9b04      	ldr	r3, [sp, #16]
 800706a:	4607      	mov	r7, r0
 800706c:	2b00      	cmp	r3, #0
 800706e:	dc4d      	bgt.n	800710c <_dtoa_r+0x94c>
 8007070:	9b1e      	ldr	r3, [sp, #120]	; 0x78
 8007072:	2b02      	cmp	r3, #2
 8007074:	dd4a      	ble.n	800710c <_dtoa_r+0x94c>
 8007076:	e011      	b.n	800709c <_dtoa_r+0x8dc>
 8007078:	d0c9      	beq.n	800700e <_dtoa_r+0x84e>
 800707a:	9a07      	ldr	r2, [sp, #28]
 800707c:	331c      	adds	r3, #28
 800707e:	441a      	add	r2, r3
 8007080:	4499      	add	r9, r3
 8007082:	441d      	add	r5, r3
 8007084:	4613      	mov	r3, r2
 8007086:	e7c1      	b.n	800700c <_dtoa_r+0x84c>
 8007088:	4603      	mov	r3, r0
 800708a:	e7f6      	b.n	800707a <_dtoa_r+0x8ba>
 800708c:	f1b8 0f00 	cmp.w	r8, #0
 8007090:	dc36      	bgt.n	8007100 <_dtoa_r+0x940>
 8007092:	9b1e      	ldr	r3, [sp, #120]	; 0x78
 8007094:	2b02      	cmp	r3, #2
 8007096:	dd33      	ble.n	8007100 <_dtoa_r+0x940>
 8007098:	f8cd 8010 	str.w	r8, [sp, #16]
 800709c:	9b04      	ldr	r3, [sp, #16]
 800709e:	b963      	cbnz	r3, 80070ba <_dtoa_r+0x8fa>
 80070a0:	4631      	mov	r1, r6
 80070a2:	2205      	movs	r2, #5
 80070a4:	4620      	mov	r0, r4
 80070a6:	f000 fb97 	bl	80077d8 <__multadd>
 80070aa:	4601      	mov	r1, r0
 80070ac:	4606      	mov	r6, r0
 80070ae:	4658      	mov	r0, fp
 80070b0:	f000 fd5c 	bl	8007b6c <__mcmp>
 80070b4:	2800      	cmp	r0, #0
 80070b6:	f73f add3 	bgt.w	8006c60 <_dtoa_r+0x4a0>
 80070ba:	9b1f      	ldr	r3, [sp, #124]	; 0x7c
 80070bc:	9d06      	ldr	r5, [sp, #24]
 80070be:	ea6f 0a03 	mvn.w	sl, r3
 80070c2:	f04f 0900 	mov.w	r9, #0
 80070c6:	4631      	mov	r1, r6
 80070c8:	4620      	mov	r0, r4
 80070ca:	f000 fb6e 	bl	80077aa <_Bfree>
 80070ce:	2f00      	cmp	r7, #0
 80070d0:	f43f aebd 	beq.w	8006e4e <_dtoa_r+0x68e>
 80070d4:	f1b9 0f00 	cmp.w	r9, #0
 80070d8:	d005      	beq.n	80070e6 <_dtoa_r+0x926>
 80070da:	45b9      	cmp	r9, r7
 80070dc:	d003      	beq.n	80070e6 <_dtoa_r+0x926>
 80070de:	4649      	mov	r1, r9
 80070e0:	4620      	mov	r0, r4
 80070e2:	f000 fb62 	bl	80077aa <_Bfree>
 80070e6:	4639      	mov	r1, r7
 80070e8:	4620      	mov	r0, r4
 80070ea:	f000 fb5e 	bl	80077aa <_Bfree>
 80070ee:	e6ae      	b.n	8006e4e <_dtoa_r+0x68e>
 80070f0:	2600      	movs	r6, #0
 80070f2:	4637      	mov	r7, r6
 80070f4:	e7e1      	b.n	80070ba <_dtoa_r+0x8fa>
 80070f6:	46ba      	mov	sl, r7
 80070f8:	4637      	mov	r7, r6
 80070fa:	e5b1      	b.n	8006c60 <_dtoa_r+0x4a0>
 80070fc:	40240000 	.word	0x40240000
 8007100:	9b09      	ldr	r3, [sp, #36]	; 0x24
 8007102:	f8cd 8010 	str.w	r8, [sp, #16]
 8007106:	2b00      	cmp	r3, #0
 8007108:	f000 80f3 	beq.w	80072f2 <_dtoa_r+0xb32>
 800710c:	2d00      	cmp	r5, #0
 800710e:	dd05      	ble.n	800711c <_dtoa_r+0x95c>
 8007110:	4639      	mov	r1, r7
 8007112:	462a      	mov	r2, r5
 8007114:	4620      	mov	r0, r4
 8007116:	f000 fcd5 	bl	8007ac4 <__lshift>
 800711a:	4607      	mov	r7, r0
 800711c:	9b08      	ldr	r3, [sp, #32]
 800711e:	2b00      	cmp	r3, #0
 8007120:	d04c      	beq.n	80071bc <_dtoa_r+0x9fc>
 8007122:	6879      	ldr	r1, [r7, #4]
 8007124:	4620      	mov	r0, r4
 8007126:	f000 fb0c 	bl	8007742 <_Balloc>
 800712a:	4605      	mov	r5, r0
 800712c:	693a      	ldr	r2, [r7, #16]
 800712e:	f107 010c 	add.w	r1, r7, #12
 8007132:	3202      	adds	r2, #2
 8007134:	0092      	lsls	r2, r2, #2
 8007136:	300c      	adds	r0, #12
 8007138:	f000 faf8 	bl	800772c <memcpy>
 800713c:	2201      	movs	r2, #1
 800713e:	4629      	mov	r1, r5
 8007140:	4620      	mov	r0, r4
 8007142:	f000 fcbf 	bl	8007ac4 <__lshift>
 8007146:	46b9      	mov	r9, r7
 8007148:	4607      	mov	r7, r0
 800714a:	9b06      	ldr	r3, [sp, #24]
 800714c:	9307      	str	r3, [sp, #28]
 800714e:	9b02      	ldr	r3, [sp, #8]
 8007150:	f003 0301 	and.w	r3, r3, #1
 8007154:	9308      	str	r3, [sp, #32]
 8007156:	4631      	mov	r1, r6
 8007158:	4658      	mov	r0, fp
 800715a:	f7ff faa1 	bl	80066a0 <quorem>
 800715e:	4649      	mov	r1, r9
 8007160:	4605      	mov	r5, r0
 8007162:	f100 0830 	add.w	r8, r0, #48	; 0x30
 8007166:	4658      	mov	r0, fp
 8007168:	f000 fd00 	bl	8007b6c <__mcmp>
 800716c:	463a      	mov	r2, r7
 800716e:	9002      	str	r0, [sp, #8]
 8007170:	4631      	mov	r1, r6
 8007172:	4620      	mov	r0, r4
 8007174:	f000 fd14 	bl	8007ba0 <__mdiff>
 8007178:	68c3      	ldr	r3, [r0, #12]
 800717a:	4602      	mov	r2, r0
 800717c:	bb03      	cbnz	r3, 80071c0 <_dtoa_r+0xa00>
 800717e:	4601      	mov	r1, r0
 8007180:	9009      	str	r0, [sp, #36]	; 0x24
 8007182:	4658      	mov	r0, fp
 8007184:	f000 fcf2 	bl	8007b6c <__mcmp>
 8007188:	4603      	mov	r3, r0
 800718a:	9a09      	ldr	r2, [sp, #36]	; 0x24
 800718c:	4611      	mov	r1, r2
 800718e:	4620      	mov	r0, r4
 8007190:	9309      	str	r3, [sp, #36]	; 0x24
 8007192:	f000 fb0a 	bl	80077aa <_Bfree>
 8007196:	9b09      	ldr	r3, [sp, #36]	; 0x24
 8007198:	b9a3      	cbnz	r3, 80071c4 <_dtoa_r+0xa04>
 800719a:	9a1e      	ldr	r2, [sp, #120]	; 0x78
 800719c:	b992      	cbnz	r2, 80071c4 <_dtoa_r+0xa04>
 800719e:	9a08      	ldr	r2, [sp, #32]
 80071a0:	b982      	cbnz	r2, 80071c4 <_dtoa_r+0xa04>
 80071a2:	f1b8 0f39 	cmp.w	r8, #57	; 0x39
 80071a6:	d029      	beq.n	80071fc <_dtoa_r+0xa3c>
 80071a8:	9b02      	ldr	r3, [sp, #8]
 80071aa:	2b00      	cmp	r3, #0
 80071ac:	dd01      	ble.n	80071b2 <_dtoa_r+0x9f2>
 80071ae:	f105 0831 	add.w	r8, r5, #49	; 0x31
 80071b2:	9b07      	ldr	r3, [sp, #28]
 80071b4:	1c5d      	adds	r5, r3, #1
 80071b6:	f883 8000 	strb.w	r8, [r3]
 80071ba:	e784      	b.n	80070c6 <_dtoa_r+0x906>
 80071bc:	4638      	mov	r0, r7
 80071be:	e7c2      	b.n	8007146 <_dtoa_r+0x986>
 80071c0:	2301      	movs	r3, #1
 80071c2:	e7e3      	b.n	800718c <_dtoa_r+0x9cc>
 80071c4:	9a02      	ldr	r2, [sp, #8]
 80071c6:	2a00      	cmp	r2, #0
 80071c8:	db04      	blt.n	80071d4 <_dtoa_r+0xa14>
 80071ca:	d123      	bne.n	8007214 <_dtoa_r+0xa54>
 80071cc:	9a1e      	ldr	r2, [sp, #120]	; 0x78
 80071ce:	bb0a      	cbnz	r2, 8007214 <_dtoa_r+0xa54>
 80071d0:	9a08      	ldr	r2, [sp, #32]
 80071d2:	b9fa      	cbnz	r2, 8007214 <_dtoa_r+0xa54>
 80071d4:	2b00      	cmp	r3, #0
 80071d6:	ddec      	ble.n	80071b2 <_dtoa_r+0x9f2>
 80071d8:	4659      	mov	r1, fp
 80071da:	2201      	movs	r2, #1
 80071dc:	4620      	mov	r0, r4
 80071de:	f000 fc71 	bl	8007ac4 <__lshift>
 80071e2:	4631      	mov	r1, r6
 80071e4:	4683      	mov	fp, r0
 80071e6:	f000 fcc1 	bl	8007b6c <__mcmp>
 80071ea:	2800      	cmp	r0, #0
 80071ec:	dc03      	bgt.n	80071f6 <_dtoa_r+0xa36>
 80071ee:	d1e0      	bne.n	80071b2 <_dtoa_r+0x9f2>
 80071f0:	f018 0f01 	tst.w	r8, #1
 80071f4:	d0dd      	beq.n	80071b2 <_dtoa_r+0x9f2>
 80071f6:	f1b8 0f39 	cmp.w	r8, #57	; 0x39
 80071fa:	d1d8      	bne.n	80071ae <_dtoa_r+0x9ee>
 80071fc:	9b07      	ldr	r3, [sp, #28]
 80071fe:	9a07      	ldr	r2, [sp, #28]
 8007200:	1c5d      	adds	r5, r3, #1
 8007202:	2339      	movs	r3, #57	; 0x39
 8007204:	7013      	strb	r3, [r2, #0]
 8007206:	f815 3c01 	ldrb.w	r3, [r5, #-1]
 800720a:	1e6a      	subs	r2, r5, #1
 800720c:	2b39      	cmp	r3, #57	; 0x39
 800720e:	d04d      	beq.n	80072ac <_dtoa_r+0xaec>
 8007210:	3301      	adds	r3, #1
 8007212:	e052      	b.n	80072ba <_dtoa_r+0xafa>
 8007214:	9a07      	ldr	r2, [sp, #28]
 8007216:	2b00      	cmp	r3, #0
 8007218:	f102 0501 	add.w	r5, r2, #1
 800721c:	dd06      	ble.n	800722c <_dtoa_r+0xa6c>
 800721e:	f1b8 0f39 	cmp.w	r8, #57	; 0x39
 8007222:	d0eb      	beq.n	80071fc <_dtoa_r+0xa3c>
 8007224:	f108 0801 	add.w	r8, r8, #1
 8007228:	9b07      	ldr	r3, [sp, #28]
 800722a:	e7c4      	b.n	80071b6 <_dtoa_r+0x9f6>
 800722c:	9b06      	ldr	r3, [sp, #24]
 800722e:	9a04      	ldr	r2, [sp, #16]
 8007230:	1aeb      	subs	r3, r5, r3
 8007232:	4293      	cmp	r3, r2
 8007234:	f805 8c01 	strb.w	r8, [r5, #-1]
 8007238:	d021      	beq.n	800727e <_dtoa_r+0xabe>
 800723a:	4659      	mov	r1, fp
 800723c:	2300      	movs	r3, #0
 800723e:	220a      	movs	r2, #10
 8007240:	4620      	mov	r0, r4
 8007242:	f000 fac9 	bl	80077d8 <__multadd>
 8007246:	45b9      	cmp	r9, r7
 8007248:	4683      	mov	fp, r0
 800724a:	f04f 0300 	mov.w	r3, #0
 800724e:	f04f 020a 	mov.w	r2, #10
 8007252:	4649      	mov	r1, r9
 8007254:	4620      	mov	r0, r4
 8007256:	d105      	bne.n	8007264 <_dtoa_r+0xaa4>
 8007258:	f000 fabe 	bl	80077d8 <__multadd>
 800725c:	4681      	mov	r9, r0
 800725e:	4607      	mov	r7, r0
 8007260:	9507      	str	r5, [sp, #28]
 8007262:	e778      	b.n	8007156 <_dtoa_r+0x996>
 8007264:	f000 fab8 	bl	80077d8 <__multadd>
 8007268:	4639      	mov	r1, r7
 800726a:	4681      	mov	r9, r0
 800726c:	2300      	movs	r3, #0
 800726e:	220a      	movs	r2, #10
 8007270:	4620      	mov	r0, r4
 8007272:	f000 fab1 	bl	80077d8 <__multadd>
 8007276:	4607      	mov	r7, r0
 8007278:	e7f2      	b.n	8007260 <_dtoa_r+0xaa0>
 800727a:	f04f 0900 	mov.w	r9, #0
 800727e:	4659      	mov	r1, fp
 8007280:	2201      	movs	r2, #1
 8007282:	4620      	mov	r0, r4
 8007284:	f000 fc1e 	bl	8007ac4 <__lshift>
 8007288:	4631      	mov	r1, r6
 800728a:	4683      	mov	fp, r0
 800728c:	f000 fc6e 	bl	8007b6c <__mcmp>
 8007290:	2800      	cmp	r0, #0
 8007292:	dcb8      	bgt.n	8007206 <_dtoa_r+0xa46>
 8007294:	d102      	bne.n	800729c <_dtoa_r+0xadc>
 8007296:	f018 0f01 	tst.w	r8, #1
 800729a:	d1b4      	bne.n	8007206 <_dtoa_r+0xa46>
 800729c:	f815 3c01 	ldrb.w	r3, [r5, #-1]
 80072a0:	1e6a      	subs	r2, r5, #1
 80072a2:	2b30      	cmp	r3, #48	; 0x30
 80072a4:	f47f af0f 	bne.w	80070c6 <_dtoa_r+0x906>
 80072a8:	4615      	mov	r5, r2
 80072aa:	e7f7      	b.n	800729c <_dtoa_r+0xadc>
 80072ac:	9b06      	ldr	r3, [sp, #24]
 80072ae:	4293      	cmp	r3, r2
 80072b0:	d105      	bne.n	80072be <_dtoa_r+0xafe>
 80072b2:	2331      	movs	r3, #49	; 0x31
 80072b4:	9a06      	ldr	r2, [sp, #24]
 80072b6:	f10a 0a01 	add.w	sl, sl, #1
 80072ba:	7013      	strb	r3, [r2, #0]
 80072bc:	e703      	b.n	80070c6 <_dtoa_r+0x906>
 80072be:	4615      	mov	r5, r2
 80072c0:	e7a1      	b.n	8007206 <_dtoa_r+0xa46>
 80072c2:	4b17      	ldr	r3, [pc, #92]	; (8007320 <_dtoa_r+0xb60>)
 80072c4:	f7ff bae1 	b.w	800688a <_dtoa_r+0xca>
 80072c8:	9b22      	ldr	r3, [sp, #136]	; 0x88
 80072ca:	2b00      	cmp	r3, #0
 80072cc:	f47f aabb 	bne.w	8006846 <_dtoa_r+0x86>
 80072d0:	4b14      	ldr	r3, [pc, #80]	; (8007324 <_dtoa_r+0xb64>)
 80072d2:	f7ff bada 	b.w	800688a <_dtoa_r+0xca>
 80072d6:	9b1e      	ldr	r3, [sp, #120]	; 0x78
 80072d8:	2b01      	cmp	r3, #1
 80072da:	f77f ae3f 	ble.w	8006f5c <_dtoa_r+0x79c>
 80072de:	9b0c      	ldr	r3, [sp, #48]	; 0x30
 80072e0:	9308      	str	r3, [sp, #32]
 80072e2:	e653      	b.n	8006f8c <_dtoa_r+0x7cc>
 80072e4:	9b04      	ldr	r3, [sp, #16]
 80072e6:	2b00      	cmp	r3, #0
 80072e8:	dc03      	bgt.n	80072f2 <_dtoa_r+0xb32>
 80072ea:	9b1e      	ldr	r3, [sp, #120]	; 0x78
 80072ec:	2b02      	cmp	r3, #2
 80072ee:	f73f aed5 	bgt.w	800709c <_dtoa_r+0x8dc>
 80072f2:	9d06      	ldr	r5, [sp, #24]
 80072f4:	4631      	mov	r1, r6
 80072f6:	4658      	mov	r0, fp
 80072f8:	f7ff f9d2 	bl	80066a0 <quorem>
 80072fc:	9b06      	ldr	r3, [sp, #24]
 80072fe:	f100 0830 	add.w	r8, r0, #48	; 0x30
 8007302:	f805 8b01 	strb.w	r8, [r5], #1
 8007306:	9a04      	ldr	r2, [sp, #16]
 8007308:	1aeb      	subs	r3, r5, r3
 800730a:	429a      	cmp	r2, r3
 800730c:	ddb5      	ble.n	800727a <_dtoa_r+0xaba>
 800730e:	4659      	mov	r1, fp
 8007310:	2300      	movs	r3, #0
 8007312:	220a      	movs	r2, #10
 8007314:	4620      	mov	r0, r4
 8007316:	f000 fa5f 	bl	80077d8 <__multadd>
 800731a:	4683      	mov	fp, r0
 800731c:	e7ea      	b.n	80072f4 <_dtoa_r+0xb34>
 800731e:	bf00      	nop
 8007320:	0800860c 	.word	0x0800860c
 8007324:	08008630 	.word	0x08008630

08007328 <__sflush_r>:
 8007328:	898a      	ldrh	r2, [r1, #12]
 800732a:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
 800732e:	4605      	mov	r5, r0
 8007330:	0710      	lsls	r0, r2, #28
 8007332:	460c      	mov	r4, r1
 8007334:	d458      	bmi.n	80073e8 <__sflush_r+0xc0>
 8007336:	684b      	ldr	r3, [r1, #4]
 8007338:	2b00      	cmp	r3, #0
 800733a:	dc05      	bgt.n	8007348 <__sflush_r+0x20>
 800733c:	6c0b      	ldr	r3, [r1, #64]	; 0x40
 800733e:	2b00      	cmp	r3, #0
 8007340:	dc02      	bgt.n	8007348 <__sflush_r+0x20>
 8007342:	2000      	movs	r0, #0
 8007344:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
 8007348:	6ae6      	ldr	r6, [r4, #44]	; 0x2c
 800734a:	2e00      	cmp	r6, #0
 800734c:	d0f9      	beq.n	8007342 <__sflush_r+0x1a>
 800734e:	2300      	movs	r3, #0
 8007350:	f412 5280 	ands.w	r2, r2, #4096	; 0x1000
 8007354:	682f      	ldr	r7, [r5, #0]
 8007356:	6a21      	ldr	r1, [r4, #32]
 8007358:	602b      	str	r3, [r5, #0]
 800735a:	d032      	beq.n	80073c2 <__sflush_r+0x9a>
 800735c:	6d60      	ldr	r0, [r4, #84]	; 0x54
 800735e:	89a3      	ldrh	r3, [r4, #12]
 8007360:	075a      	lsls	r2, r3, #29
 8007362:	d505      	bpl.n	8007370 <__sflush_r+0x48>
 8007364:	6863      	ldr	r3, [r4, #4]
 8007366:	1ac0      	subs	r0, r0, r3
 8007368:	6b63      	ldr	r3, [r4, #52]	; 0x34
 800736a:	b10b      	cbz	r3, 8007370 <__sflush_r+0x48>
 800736c:	6c23      	ldr	r3, [r4, #64]	; 0x40
 800736e:	1ac0      	subs	r0, r0, r3
 8007370:	2300      	movs	r3, #0
 8007372:	4602      	mov	r2, r0
 8007374:	6ae6      	ldr	r6, [r4, #44]	; 0x2c
 8007376:	6a21      	ldr	r1, [r4, #32]
 8007378:	4628      	mov	r0, r5
 800737a:	47b0      	blx	r6
 800737c:	1c43      	adds	r3, r0, #1
 800737e:	89a3      	ldrh	r3, [r4, #12]
 8007380:	d106      	bne.n	8007390 <__sflush_r+0x68>
 8007382:	6829      	ldr	r1, [r5, #0]
 8007384:	291d      	cmp	r1, #29
 8007386:	d848      	bhi.n	800741a <__sflush_r+0xf2>
 8007388:	4a29      	ldr	r2, [pc, #164]	; (8007430 <__sflush_r+0x108>)
 800738a:	40ca      	lsrs	r2, r1
 800738c:	07d6      	lsls	r6, r2, #31
 800738e:	d544      	bpl.n	800741a <__sflush_r+0xf2>
 8007390:	2200      	movs	r2, #0
 8007392:	6062      	str	r2, [r4, #4]
 8007394:	6922      	ldr	r2, [r4, #16]
 8007396:	04d9      	lsls	r1, r3, #19
 8007398:	6022      	str	r2, [r4, #0]
 800739a:	d504      	bpl.n	80073a6 <__sflush_r+0x7e>
 800739c:	1c42      	adds	r2, r0, #1
 800739e:	d101      	bne.n	80073a4 <__sflush_r+0x7c>
 80073a0:	682b      	ldr	r3, [r5, #0]
 80073a2:	b903      	cbnz	r3, 80073a6 <__sflush_r+0x7e>
 80073a4:	6560      	str	r0, [r4, #84]	; 0x54
 80073a6:	6b61      	ldr	r1, [r4, #52]	; 0x34
 80073a8:	602f      	str	r7, [r5, #0]
 80073aa:	2900      	cmp	r1, #0
 80073ac:	d0c9      	beq.n	8007342 <__sflush_r+0x1a>
 80073ae:	f104 0344 	add.w	r3, r4, #68	; 0x44
 80073b2:	4299      	cmp	r1, r3
 80073b4:	d002      	beq.n	80073bc <__sflush_r+0x94>
 80073b6:	4628      	mov	r0, r5
 80073b8:	f000 fcae 	bl	8007d18 <_free_r>
 80073bc:	2000      	movs	r0, #0
 80073be:	6360      	str	r0, [r4, #52]	; 0x34
 80073c0:	e7c0      	b.n	8007344 <__sflush_r+0x1c>
 80073c2:	2301      	movs	r3, #1
 80073c4:	4628      	mov	r0, r5
 80073c6:	47b0      	blx	r6
 80073c8:	1c41      	adds	r1, r0, #1
 80073ca:	d1c8      	bne.n	800735e <__sflush_r+0x36>
 80073cc:	682b      	ldr	r3, [r5, #0]
 80073ce:	2b00      	cmp	r3, #0
 80073d0:	d0c5      	beq.n	800735e <__sflush_r+0x36>
 80073d2:	2b1d      	cmp	r3, #29
 80073d4:	d001      	beq.n	80073da <__sflush_r+0xb2>
 80073d6:	2b16      	cmp	r3, #22
 80073d8:	d101      	bne.n	80073de <__sflush_r+0xb6>
 80073da:	602f      	str	r7, [r5, #0]
 80073dc:	e7b1      	b.n	8007342 <__sflush_r+0x1a>
 80073de:	89a3      	ldrh	r3, [r4, #12]
 80073e0:	f043 0340 	orr.w	r3, r3, #64	; 0x40
 80073e4:	81a3      	strh	r3, [r4, #12]
 80073e6:	e7ad      	b.n	8007344 <__sflush_r+0x1c>
 80073e8:	690f      	ldr	r7, [r1, #16]
 80073ea:	2f00      	cmp	r7, #0
 80073ec:	d0a9      	beq.n	8007342 <__sflush_r+0x1a>
 80073ee:	0793      	lsls	r3, r2, #30
 80073f0:	bf18      	it	ne
 80073f2:	2300      	movne	r3, #0
 80073f4:	680e      	ldr	r6, [r1, #0]
 80073f6:	bf08      	it	eq
 80073f8:	694b      	ldreq	r3, [r1, #20]
 80073fa:	eba6 0807 	sub.w	r8, r6, r7
 80073fe:	600f      	str	r7, [r1, #0]
 8007400:	608b      	str	r3, [r1, #8]
 8007402:	f1b8 0f00 	cmp.w	r8, #0
 8007406:	dd9c      	ble.n	8007342 <__sflush_r+0x1a>
 8007408:	4643      	mov	r3, r8
 800740a:	463a      	mov	r2, r7
 800740c:	6a21      	ldr	r1, [r4, #32]
 800740e:	4628      	mov	r0, r5
 8007410:	6aa6      	ldr	r6, [r4, #40]	; 0x28
 8007412:	47b0      	blx	r6
 8007414:	2800      	cmp	r0, #0
 8007416:	dc06      	bgt.n	8007426 <__sflush_r+0xfe>
 8007418:	89a3      	ldrh	r3, [r4, #12]
 800741a:	f043 0340 	orr.w	r3, r3, #64	; 0x40
 800741e:	81a3      	strh	r3, [r4, #12]
 8007420:	f04f 30ff 	mov.w	r0, #4294967295
 8007424:	e78e      	b.n	8007344 <__sflush_r+0x1c>
 8007426:	4407      	add	r7, r0
 8007428:	eba8 0800 	sub.w	r8, r8, r0
 800742c:	e7e9      	b.n	8007402 <__sflush_r+0xda>
 800742e:	bf00      	nop
 8007430:	20400001 	.word	0x20400001

08007434 <_fflush_r>:
 8007434:	b538      	push	{r3, r4, r5, lr}
 8007436:	690b      	ldr	r3, [r1, #16]
 8007438:	4605      	mov	r5, r0
 800743a:	460c      	mov	r4, r1
 800743c:	b1db      	cbz	r3, 8007476 <_fflush_r+0x42>
 800743e:	b118      	cbz	r0, 8007448 <_fflush_r+0x14>
 8007440:	6983      	ldr	r3, [r0, #24]
 8007442:	b90b      	cbnz	r3, 8007448 <_fflush_r+0x14>
 8007444:	f000 f860 	bl	8007508 <__sinit>
 8007448:	4b0c      	ldr	r3, [pc, #48]	; (800747c <_fflush_r+0x48>)
 800744a:	429c      	cmp	r4, r3
 800744c:	d109      	bne.n	8007462 <_fflush_r+0x2e>
 800744e:	686c      	ldr	r4, [r5, #4]
 8007450:	f9b4 300c 	ldrsh.w	r3, [r4, #12]
 8007454:	b17b      	cbz	r3, 8007476 <_fflush_r+0x42>
 8007456:	4621      	mov	r1, r4
 8007458:	4628      	mov	r0, r5
 800745a:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
 800745e:	f7ff bf63 	b.w	8007328 <__sflush_r>
 8007462:	4b07      	ldr	r3, [pc, #28]	; (8007480 <_fflush_r+0x4c>)
 8007464:	429c      	cmp	r4, r3
 8007466:	d101      	bne.n	800746c <_fflush_r+0x38>
 8007468:	68ac      	ldr	r4, [r5, #8]
 800746a:	e7f1      	b.n	8007450 <_fflush_r+0x1c>
 800746c:	4b05      	ldr	r3, [pc, #20]	; (8007484 <_fflush_r+0x50>)
 800746e:	429c      	cmp	r4, r3
 8007470:	bf08      	it	eq
 8007472:	68ec      	ldreq	r4, [r5, #12]
 8007474:	e7ec      	b.n	8007450 <_fflush_r+0x1c>
 8007476:	2000      	movs	r0, #0
 8007478:	bd38      	pop	{r3, r4, r5, pc}
 800747a:	bf00      	nop
 800747c:	08008660 	.word	0x08008660
 8007480:	08008680 	.word	0x08008680
 8007484:	08008640 	.word	0x08008640

08007488 <std>:
 8007488:	2300      	movs	r3, #0
 800748a:	b510      	push	{r4, lr}
 800748c:	4604      	mov	r4, r0
 800748e:	e9c0 3300 	strd	r3, r3, [r0]
 8007492:	6083      	str	r3, [r0, #8]
 8007494:	8181      	strh	r1, [r0, #12]
 8007496:	6643      	str	r3, [r0, #100]	; 0x64
 8007498:	81c2      	strh	r2, [r0, #14]
 800749a:	e9c0 3304 	strd	r3, r3, [r0, #16]
 800749e:	6183      	str	r3, [r0, #24]
 80074a0:	4619      	mov	r1, r3
 80074a2:	2208      	movs	r2, #8
 80074a4:	305c      	adds	r0, #92	; 0x5c
 80074a6:	f7fe fab1 	bl	8005a0c <memset>
 80074aa:	4b05      	ldr	r3, [pc, #20]	; (80074c0 <std+0x38>)
 80074ac:	6224      	str	r4, [r4, #32]
 80074ae:	6263      	str	r3, [r4, #36]	; 0x24
 80074b0:	4b04      	ldr	r3, [pc, #16]	; (80074c4 <std+0x3c>)
 80074b2:	62a3      	str	r3, [r4, #40]	; 0x28
 80074b4:	4b04      	ldr	r3, [pc, #16]	; (80074c8 <std+0x40>)
 80074b6:	62e3      	str	r3, [r4, #44]	; 0x2c
 80074b8:	4b04      	ldr	r3, [pc, #16]	; (80074cc <std+0x44>)
 80074ba:	6323      	str	r3, [r4, #48]	; 0x30
 80074bc:	bd10      	pop	{r4, pc}
 80074be:	bf00      	nop
 80074c0:	08008101 	.word	0x08008101
 80074c4:	08008123 	.word	0x08008123
 80074c8:	0800815b 	.word	0x0800815b
 80074cc:	0800817f 	.word	0x0800817f

080074d0 <_cleanup_r>:
 80074d0:	4901      	ldr	r1, [pc, #4]	; (80074d8 <_cleanup_r+0x8>)
 80074d2:	f000 b885 	b.w	80075e0 <_fwalk_reent>
 80074d6:	bf00      	nop
 80074d8:	08007435 	.word	0x08007435

080074dc <__sfmoreglue>:
 80074dc:	b570      	push	{r4, r5, r6, lr}
 80074de:	2568      	movs	r5, #104	; 0x68
 80074e0:	1e4a      	subs	r2, r1, #1
 80074e2:	4355      	muls	r5, r2
 80074e4:	460e      	mov	r6, r1
 80074e6:	f105 0174 	add.w	r1, r5, #116	; 0x74
 80074ea:	f000 fc61 	bl	8007db0 <_malloc_r>
 80074ee:	4604      	mov	r4, r0
 80074f0:	b140      	cbz	r0, 8007504 <__sfmoreglue+0x28>
 80074f2:	2100      	movs	r1, #0
 80074f4:	e9c0 1600 	strd	r1, r6, [r0]
 80074f8:	300c      	adds	r0, #12
 80074fa:	60a0      	str	r0, [r4, #8]
 80074fc:	f105 0268 	add.w	r2, r5, #104	; 0x68
 8007500:	f7fe fa84 	bl	8005a0c <memset>
 8007504:	4620      	mov	r0, r4
 8007506:	bd70      	pop	{r4, r5, r6, pc}

08007508 <__sinit>:
 8007508:	6983      	ldr	r3, [r0, #24]
 800750a:	b510      	push	{r4, lr}
 800750c:	4604      	mov	r4, r0
 800750e:	bb33      	cbnz	r3, 800755e <__sinit+0x56>
 8007510:	e9c0 3312 	strd	r3, r3, [r0, #72]	; 0x48
 8007514:	6503      	str	r3, [r0, #80]	; 0x50
 8007516:	4b12      	ldr	r3, [pc, #72]	; (8007560 <__sinit+0x58>)
 8007518:	4a12      	ldr	r2, [pc, #72]	; (8007564 <__sinit+0x5c>)
 800751a:	681b      	ldr	r3, [r3, #0]
 800751c:	6282      	str	r2, [r0, #40]	; 0x28
 800751e:	4298      	cmp	r0, r3
 8007520:	bf04      	itt	eq
 8007522:	2301      	moveq	r3, #1
 8007524:	6183      	streq	r3, [r0, #24]
 8007526:	f000 f81f 	bl	8007568 <__sfp>
 800752a:	6060      	str	r0, [r4, #4]
 800752c:	4620      	mov	r0, r4
 800752e:	f000 f81b 	bl	8007568 <__sfp>
 8007532:	60a0      	str	r0, [r4, #8]
 8007534:	4620      	mov	r0, r4
 8007536:	f000 f817 	bl	8007568 <__sfp>
 800753a:	2200      	movs	r2, #0
 800753c:	60e0      	str	r0, [r4, #12]
 800753e:	2104      	movs	r1, #4
 8007540:	6860      	ldr	r0, [r4, #4]
 8007542:	f7ff ffa1 	bl	8007488 <std>
 8007546:	2201      	movs	r2, #1
 8007548:	2109      	movs	r1, #9
 800754a:	68a0      	ldr	r0, [r4, #8]
 800754c:	f7ff ff9c 	bl	8007488 <std>
 8007550:	2202      	movs	r2, #2
 8007552:	2112      	movs	r1, #18
 8007554:	68e0      	ldr	r0, [r4, #12]
 8007556:	f7ff ff97 	bl	8007488 <std>
 800755a:	2301      	movs	r3, #1
 800755c:	61a3      	str	r3, [r4, #24]
 800755e:	bd10      	pop	{r4, pc}
 8007560:	080085f8 	.word	0x080085f8
 8007564:	080074d1 	.word	0x080074d1

08007568 <__sfp>:
 8007568:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 800756a:	4b1b      	ldr	r3, [pc, #108]	; (80075d8 <__sfp+0x70>)
 800756c:	4607      	mov	r7, r0
 800756e:	681e      	ldr	r6, [r3, #0]
 8007570:	69b3      	ldr	r3, [r6, #24]
 8007572:	b913      	cbnz	r3, 800757a <__sfp+0x12>
 8007574:	4630      	mov	r0, r6
 8007576:	f7ff ffc7 	bl	8007508 <__sinit>
 800757a:	3648      	adds	r6, #72	; 0x48
 800757c:	e9d6 3401 	ldrd	r3, r4, [r6, #4]
 8007580:	3b01      	subs	r3, #1
 8007582:	d503      	bpl.n	800758c <__sfp+0x24>
 8007584:	6833      	ldr	r3, [r6, #0]
 8007586:	b133      	cbz	r3, 8007596 <__sfp+0x2e>
 8007588:	6836      	ldr	r6, [r6, #0]
 800758a:	e7f7      	b.n	800757c <__sfp+0x14>
 800758c:	f9b4 500c 	ldrsh.w	r5, [r4, #12]
 8007590:	b16d      	cbz	r5, 80075ae <__sfp+0x46>
 8007592:	3468      	adds	r4, #104	; 0x68
 8007594:	e7f4      	b.n	8007580 <__sfp+0x18>
 8007596:	2104      	movs	r1, #4
 8007598:	4638      	mov	r0, r7
 800759a:	f7ff ff9f 	bl	80074dc <__sfmoreglue>
 800759e:	6030      	str	r0, [r6, #0]
 80075a0:	2800      	cmp	r0, #0
 80075a2:	d1f1      	bne.n	8007588 <__sfp+0x20>
 80075a4:	230c      	movs	r3, #12
 80075a6:	4604      	mov	r4, r0
 80075a8:	603b      	str	r3, [r7, #0]
 80075aa:	4620      	mov	r0, r4
 80075ac:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
 80075ae:	4b0b      	ldr	r3, [pc, #44]	; (80075dc <__sfp+0x74>)
 80075b0:	6665      	str	r5, [r4, #100]	; 0x64
 80075b2:	e9c4 5500 	strd	r5, r5, [r4]
 80075b6:	60a5      	str	r5, [r4, #8]
 80075b8:	e9c4 3503 	strd	r3, r5, [r4, #12]
 80075bc:	e9c4 5505 	strd	r5, r5, [r4, #20]
 80075c0:	2208      	movs	r2, #8
 80075c2:	4629      	mov	r1, r5
 80075c4:	f104 005c 	add.w	r0, r4, #92	; 0x5c
 80075c8:	f7fe fa20 	bl	8005a0c <memset>
 80075cc:	e9c4 550d 	strd	r5, r5, [r4, #52]	; 0x34
 80075d0:	e9c4 5512 	strd	r5, r5, [r4, #72]	; 0x48
 80075d4:	e7e9      	b.n	80075aa <__sfp+0x42>
 80075d6:	bf00      	nop
 80075d8:	080085f8 	.word	0x080085f8
 80075dc:	ffff0001 	.word	0xffff0001

080075e0 <_fwalk_reent>:
 80075e0:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
 80075e4:	4680      	mov	r8, r0
 80075e6:	4689      	mov	r9, r1
 80075e8:	2600      	movs	r6, #0
 80075ea:	f100 0448 	add.w	r4, r0, #72	; 0x48
 80075ee:	b914      	cbnz	r4, 80075f6 <_fwalk_reent+0x16>
 80075f0:	4630      	mov	r0, r6
 80075f2:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
 80075f6:	e9d4 7501 	ldrd	r7, r5, [r4, #4]
 80075fa:	3f01      	subs	r7, #1
 80075fc:	d501      	bpl.n	8007602 <_fwalk_reent+0x22>
 80075fe:	6824      	ldr	r4, [r4, #0]
 8007600:	e7f5      	b.n	80075ee <_fwalk_reent+0xe>
 8007602:	89ab      	ldrh	r3, [r5, #12]
 8007604:	2b01      	cmp	r3, #1
 8007606:	d907      	bls.n	8007618 <_fwalk_reent+0x38>
 8007608:	f9b5 300e 	ldrsh.w	r3, [r5, #14]
 800760c:	3301      	adds	r3, #1
 800760e:	d003      	beq.n	8007618 <_fwalk_reent+0x38>
 8007610:	4629      	mov	r1, r5
 8007612:	4640      	mov	r0, r8
 8007614:	47c8      	blx	r9
 8007616:	4306      	orrs	r6, r0
 8007618:	3568      	adds	r5, #104	; 0x68
 800761a:	e7ee      	b.n	80075fa <_fwalk_reent+0x1a>

0800761c <_localeconv_r>:
 800761c:	4b04      	ldr	r3, [pc, #16]	; (8007630 <_localeconv_r+0x14>)
 800761e:	681b      	ldr	r3, [r3, #0]
 8007620:	6a18      	ldr	r0, [r3, #32]
 8007622:	4b04      	ldr	r3, [pc, #16]	; (8007634 <_localeconv_r+0x18>)
 8007624:	2800      	cmp	r0, #0
 8007626:	bf08      	it	eq
 8007628:	4618      	moveq	r0, r3
 800762a:	30f0      	adds	r0, #240	; 0xf0
 800762c:	4770      	bx	lr
 800762e:	bf00      	nop
 8007630:	2000000c 	.word	0x2000000c
 8007634:	20000070 	.word	0x20000070

08007638 <__swhatbuf_r>:
 8007638:	b570      	push	{r4, r5, r6, lr}
 800763a:	460e      	mov	r6, r1
 800763c:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 8007640:	b096      	sub	sp, #88	; 0x58
 8007642:	2900      	cmp	r1, #0
 8007644:	4614      	mov	r4, r2
 8007646:	461d      	mov	r5, r3
 8007648:	da07      	bge.n	800765a <__swhatbuf_r+0x22>
 800764a:	2300      	movs	r3, #0
 800764c:	602b      	str	r3, [r5, #0]
 800764e:	89b3      	ldrh	r3, [r6, #12]
 8007650:	061a      	lsls	r2, r3, #24
 8007652:	d410      	bmi.n	8007676 <__swhatbuf_r+0x3e>
 8007654:	f44f 6380 	mov.w	r3, #1024	; 0x400
 8007658:	e00e      	b.n	8007678 <__swhatbuf_r+0x40>
 800765a:	466a      	mov	r2, sp
 800765c:	f000 fdb6 	bl	80081cc <_fstat_r>
 8007660:	2800      	cmp	r0, #0
 8007662:	dbf2      	blt.n	800764a <__swhatbuf_r+0x12>
 8007664:	9a01      	ldr	r2, [sp, #4]
 8007666:	f402 4270 	and.w	r2, r2, #61440	; 0xf000
 800766a:	f5a2 5300 	sub.w	r3, r2, #8192	; 0x2000
 800766e:	425a      	negs	r2, r3
 8007670:	415a      	adcs	r2, r3
 8007672:	602a      	str	r2, [r5, #0]
 8007674:	e7ee      	b.n	8007654 <__swhatbuf_r+0x1c>
 8007676:	2340      	movs	r3, #64	; 0x40
 8007678:	2000      	movs	r0, #0
 800767a:	6023      	str	r3, [r4, #0]
 800767c:	b016      	add	sp, #88	; 0x58
 800767e:	bd70      	pop	{r4, r5, r6, pc}

08007680 <__smakebuf_r>:
 8007680:	898b      	ldrh	r3, [r1, #12]
 8007682:	b573      	push	{r0, r1, r4, r5, r6, lr}
 8007684:	079d      	lsls	r5, r3, #30
 8007686:	4606      	mov	r6, r0
 8007688:	460c      	mov	r4, r1
 800768a:	d507      	bpl.n	800769c <__smakebuf_r+0x1c>
 800768c:	f104 0347 	add.w	r3, r4, #71	; 0x47
 8007690:	6023      	str	r3, [r4, #0]
 8007692:	6123      	str	r3, [r4, #16]
 8007694:	2301      	movs	r3, #1
 8007696:	6163      	str	r3, [r4, #20]
 8007698:	b002      	add	sp, #8
 800769a:	bd70      	pop	{r4, r5, r6, pc}
 800769c:	ab01      	add	r3, sp, #4
 800769e:	466a      	mov	r2, sp
 80076a0:	f7ff ffca 	bl	8007638 <__swhatbuf_r>
 80076a4:	9900      	ldr	r1, [sp, #0]
 80076a6:	4605      	mov	r5, r0
 80076a8:	4630      	mov	r0, r6
 80076aa:	f000 fb81 	bl	8007db0 <_malloc_r>
 80076ae:	b948      	cbnz	r0, 80076c4 <__smakebuf_r+0x44>
 80076b0:	f9b4 300c 	ldrsh.w	r3, [r4, #12]
 80076b4:	059a      	lsls	r2, r3, #22
 80076b6:	d4ef      	bmi.n	8007698 <__smakebuf_r+0x18>
 80076b8:	f023 0303 	bic.w	r3, r3, #3
 80076bc:	f043 0302 	orr.w	r3, r3, #2
 80076c0:	81a3      	strh	r3, [r4, #12]
 80076c2:	e7e3      	b.n	800768c <__smakebuf_r+0xc>
 80076c4:	4b0d      	ldr	r3, [pc, #52]	; (80076fc <__smakebuf_r+0x7c>)
 80076c6:	62b3      	str	r3, [r6, #40]	; 0x28
 80076c8:	89a3      	ldrh	r3, [r4, #12]
 80076ca:	6020      	str	r0, [r4, #0]
 80076cc:	f043 0380 	orr.w	r3, r3, #128	; 0x80
 80076d0:	81a3      	strh	r3, [r4, #12]
 80076d2:	9b00      	ldr	r3, [sp, #0]
 80076d4:	6120      	str	r0, [r4, #16]
 80076d6:	6163      	str	r3, [r4, #20]
 80076d8:	9b01      	ldr	r3, [sp, #4]
 80076da:	b15b      	cbz	r3, 80076f4 <__smakebuf_r+0x74>
 80076dc:	f9b4 100e 	ldrsh.w	r1, [r4, #14]
 80076e0:	4630      	mov	r0, r6
 80076e2:	f000 fd85 	bl	80081f0 <_isatty_r>
 80076e6:	b128      	cbz	r0, 80076f4 <__smakebuf_r+0x74>
 80076e8:	89a3      	ldrh	r3, [r4, #12]
 80076ea:	f023 0303 	bic.w	r3, r3, #3
 80076ee:	f043 0301 	orr.w	r3, r3, #1
 80076f2:	81a3      	strh	r3, [r4, #12]
 80076f4:	89a3      	ldrh	r3, [r4, #12]
 80076f6:	431d      	orrs	r5, r3
 80076f8:	81a5      	strh	r5, [r4, #12]
 80076fa:	e7cd      	b.n	8007698 <__smakebuf_r+0x18>
 80076fc:	080074d1 	.word	0x080074d1

08007700 <malloc>:
 8007700:	4b02      	ldr	r3, [pc, #8]	; (800770c <malloc+0xc>)
 8007702:	4601      	mov	r1, r0
 8007704:	6818      	ldr	r0, [r3, #0]
 8007706:	f000 bb53 	b.w	8007db0 <_malloc_r>
 800770a:	bf00      	nop
 800770c:	2000000c 	.word	0x2000000c

08007710 <memchr>:
 8007710:	b510      	push	{r4, lr}
 8007712:	b2c9      	uxtb	r1, r1
 8007714:	4402      	add	r2, r0
 8007716:	4290      	cmp	r0, r2
 8007718:	4603      	mov	r3, r0
 800771a:	d101      	bne.n	8007720 <memchr+0x10>
 800771c:	2300      	movs	r3, #0
 800771e:	e003      	b.n	8007728 <memchr+0x18>
 8007720:	781c      	ldrb	r4, [r3, #0]
 8007722:	3001      	adds	r0, #1
 8007724:	428c      	cmp	r4, r1
 8007726:	d1f6      	bne.n	8007716 <memchr+0x6>
 8007728:	4618      	mov	r0, r3
 800772a:	bd10      	pop	{r4, pc}

0800772c <memcpy>:
 800772c:	b510      	push	{r4, lr}
 800772e:	1e43      	subs	r3, r0, #1
 8007730:	440a      	add	r2, r1
 8007732:	4291      	cmp	r1, r2
 8007734:	d100      	bne.n	8007738 <memcpy+0xc>
 8007736:	bd10      	pop	{r4, pc}
 8007738:	f811 4b01 	ldrb.w	r4, [r1], #1
 800773c:	f803 4f01 	strb.w	r4, [r3, #1]!
 8007740:	e7f7      	b.n	8007732 <memcpy+0x6>

08007742 <_Balloc>:
 8007742:	b570      	push	{r4, r5, r6, lr}
 8007744:	6a45      	ldr	r5, [r0, #36]	; 0x24
 8007746:	4604      	mov	r4, r0
 8007748:	460e      	mov	r6, r1
 800774a:	b93d      	cbnz	r5, 800775c <_Balloc+0x1a>
 800774c:	2010      	movs	r0, #16
 800774e:	f7ff ffd7 	bl	8007700 <malloc>
 8007752:	6260      	str	r0, [r4, #36]	; 0x24
 8007754:	e9c0 5501 	strd	r5, r5, [r0, #4]
 8007758:	6005      	str	r5, [r0, #0]
 800775a:	60c5      	str	r5, [r0, #12]
 800775c:	6a65      	ldr	r5, [r4, #36]	; 0x24
 800775e:	68eb      	ldr	r3, [r5, #12]
 8007760:	b183      	cbz	r3, 8007784 <_Balloc+0x42>
 8007762:	6a63      	ldr	r3, [r4, #36]	; 0x24
 8007764:	68db      	ldr	r3, [r3, #12]
 8007766:	f853 0026 	ldr.w	r0, [r3, r6, lsl #2]
 800776a:	b9b8      	cbnz	r0, 800779c <_Balloc+0x5a>
 800776c:	2101      	movs	r1, #1
 800776e:	fa01 f506 	lsl.w	r5, r1, r6
 8007772:	1d6a      	adds	r2, r5, #5
 8007774:	0092      	lsls	r2, r2, #2
 8007776:	4620      	mov	r0, r4
 8007778:	f000 fabf 	bl	8007cfa <_calloc_r>
 800777c:	b160      	cbz	r0, 8007798 <_Balloc+0x56>
 800777e:	e9c0 6501 	strd	r6, r5, [r0, #4]
 8007782:	e00e      	b.n	80077a2 <_Balloc+0x60>
 8007784:	2221      	movs	r2, #33	; 0x21
 8007786:	2104      	movs	r1, #4
 8007788:	4620      	mov	r0, r4
 800778a:	f000 fab6 	bl	8007cfa <_calloc_r>
 800778e:	6a63      	ldr	r3, [r4, #36]	; 0x24
 8007790:	60e8      	str	r0, [r5, #12]
 8007792:	68db      	ldr	r3, [r3, #12]
 8007794:	2b00      	cmp	r3, #0
 8007796:	d1e4      	bne.n	8007762 <_Balloc+0x20>
 8007798:	2000      	movs	r0, #0
 800779a:	bd70      	pop	{r4, r5, r6, pc}
 800779c:	6802      	ldr	r2, [r0, #0]
 800779e:	f843 2026 	str.w	r2, [r3, r6, lsl #2]
 80077a2:	2300      	movs	r3, #0
 80077a4:	e9c0 3303 	strd	r3, r3, [r0, #12]
 80077a8:	e7f7      	b.n	800779a <_Balloc+0x58>

080077aa <_Bfree>:
 80077aa:	b570      	push	{r4, r5, r6, lr}
 80077ac:	6a44      	ldr	r4, [r0, #36]	; 0x24
 80077ae:	4606      	mov	r6, r0
 80077b0:	460d      	mov	r5, r1
 80077b2:	b93c      	cbnz	r4, 80077c4 <_Bfree+0x1a>
 80077b4:	2010      	movs	r0, #16
 80077b6:	f7ff ffa3 	bl	8007700 <malloc>
 80077ba:	6270      	str	r0, [r6, #36]	; 0x24
 80077bc:	e9c0 4401 	strd	r4, r4, [r0, #4]
 80077c0:	6004      	str	r4, [r0, #0]
 80077c2:	60c4      	str	r4, [r0, #12]
 80077c4:	b13d      	cbz	r5, 80077d6 <_Bfree+0x2c>
 80077c6:	6a73      	ldr	r3, [r6, #36]	; 0x24
 80077c8:	686a      	ldr	r2, [r5, #4]
 80077ca:	68db      	ldr	r3, [r3, #12]
 80077cc:	f853 1022 	ldr.w	r1, [r3, r2, lsl #2]
 80077d0:	6029      	str	r1, [r5, #0]
 80077d2:	f843 5022 	str.w	r5, [r3, r2, lsl #2]
 80077d6:	bd70      	pop	{r4, r5, r6, pc}

080077d8 <__multadd>:
 80077d8:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
 80077dc:	461f      	mov	r7, r3
 80077de:	4606      	mov	r6, r0
 80077e0:	460c      	mov	r4, r1
 80077e2:	2300      	movs	r3, #0
 80077e4:	690d      	ldr	r5, [r1, #16]
 80077e6:	f101 0c14 	add.w	ip, r1, #20
 80077ea:	f8dc 0000 	ldr.w	r0, [ip]
 80077ee:	3301      	adds	r3, #1
 80077f0:	b281      	uxth	r1, r0
 80077f2:	fb02 7101 	mla	r1, r2, r1, r7
 80077f6:	0c00      	lsrs	r0, r0, #16
 80077f8:	0c0f      	lsrs	r7, r1, #16
 80077fa:	fb02 7000 	mla	r0, r2, r0, r7
 80077fe:	b289      	uxth	r1, r1
 8007800:	eb01 4100 	add.w	r1, r1, r0, lsl #16
 8007804:	429d      	cmp	r5, r3
 8007806:	ea4f 4710 	mov.w	r7, r0, lsr #16
 800780a:	f84c 1b04 	str.w	r1, [ip], #4
 800780e:	dcec      	bgt.n	80077ea <__multadd+0x12>
 8007810:	b1d7      	cbz	r7, 8007848 <__multadd+0x70>
 8007812:	68a3      	ldr	r3, [r4, #8]
 8007814:	42ab      	cmp	r3, r5
 8007816:	dc12      	bgt.n	800783e <__multadd+0x66>
 8007818:	6861      	ldr	r1, [r4, #4]
 800781a:	4630      	mov	r0, r6
 800781c:	3101      	adds	r1, #1
 800781e:	f7ff ff90 	bl	8007742 <_Balloc>
 8007822:	4680      	mov	r8, r0
 8007824:	6922      	ldr	r2, [r4, #16]
 8007826:	f104 010c 	add.w	r1, r4, #12
 800782a:	3202      	adds	r2, #2
 800782c:	0092      	lsls	r2, r2, #2
 800782e:	300c      	adds	r0, #12
 8007830:	f7ff ff7c 	bl	800772c <memcpy>
 8007834:	4621      	mov	r1, r4
 8007836:	4630      	mov	r0, r6
 8007838:	f7ff ffb7 	bl	80077aa <_Bfree>
 800783c:	4644      	mov	r4, r8
 800783e:	eb04 0385 	add.w	r3, r4, r5, lsl #2
 8007842:	3501      	adds	r5, #1
 8007844:	615f      	str	r7, [r3, #20]
 8007846:	6125      	str	r5, [r4, #16]
 8007848:	4620      	mov	r0, r4
 800784a:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}

0800784e <__hi0bits>:
 800784e:	0c02      	lsrs	r2, r0, #16
 8007850:	0412      	lsls	r2, r2, #16
 8007852:	4603      	mov	r3, r0
 8007854:	b9b2      	cbnz	r2, 8007884 <__hi0bits+0x36>
 8007856:	0403      	lsls	r3, r0, #16
 8007858:	2010      	movs	r0, #16
 800785a:	f013 4f7f 	tst.w	r3, #4278190080	; 0xff000000
 800785e:	bf04      	itt	eq
 8007860:	021b      	lsleq	r3, r3, #8
 8007862:	3008      	addeq	r0, #8
 8007864:	f013 4f70 	tst.w	r3, #4026531840	; 0xf0000000
 8007868:	bf04      	itt	eq
 800786a:	011b      	lsleq	r3, r3, #4
 800786c:	3004      	addeq	r0, #4
 800786e:	f013 4f40 	tst.w	r3, #3221225472	; 0xc0000000
 8007872:	bf04      	itt	eq
 8007874:	009b      	lsleq	r3, r3, #2
 8007876:	3002      	addeq	r0, #2
 8007878:	2b00      	cmp	r3, #0
 800787a:	db06      	blt.n	800788a <__hi0bits+0x3c>
 800787c:	005b      	lsls	r3, r3, #1
 800787e:	d503      	bpl.n	8007888 <__hi0bits+0x3a>
 8007880:	3001      	adds	r0, #1
 8007882:	4770      	bx	lr
 8007884:	2000      	movs	r0, #0
 8007886:	e7e8      	b.n	800785a <__hi0bits+0xc>
 8007888:	2020      	movs	r0, #32
 800788a:	4770      	bx	lr

0800788c <__lo0bits>:
 800788c:	6803      	ldr	r3, [r0, #0]
 800788e:	4601      	mov	r1, r0
 8007890:	f013 0207 	ands.w	r2, r3, #7
 8007894:	d00b      	beq.n	80078ae <__lo0bits+0x22>
 8007896:	07da      	lsls	r2, r3, #31
 8007898:	d423      	bmi.n	80078e2 <__lo0bits+0x56>
 800789a:	0798      	lsls	r0, r3, #30
 800789c:	bf49      	itett	mi
 800789e:	085b      	lsrmi	r3, r3, #1
 80078a0:	089b      	lsrpl	r3, r3, #2
 80078a2:	2001      	movmi	r0, #1
 80078a4:	600b      	strmi	r3, [r1, #0]
 80078a6:	bf5c      	itt	pl
 80078a8:	600b      	strpl	r3, [r1, #0]
 80078aa:	2002      	movpl	r0, #2
 80078ac:	4770      	bx	lr
 80078ae:	b298      	uxth	r0, r3
 80078b0:	b9a8      	cbnz	r0, 80078de <__lo0bits+0x52>
 80078b2:	2010      	movs	r0, #16
 80078b4:	0c1b      	lsrs	r3, r3, #16
 80078b6:	f013 0fff 	tst.w	r3, #255	; 0xff
 80078ba:	bf04      	itt	eq
 80078bc:	0a1b      	lsreq	r3, r3, #8
 80078be:	3008      	addeq	r0, #8
 80078c0:	071a      	lsls	r2, r3, #28
 80078c2:	bf04      	itt	eq
 80078c4:	091b      	lsreq	r3, r3, #4
 80078c6:	3004      	addeq	r0, #4
 80078c8:	079a      	lsls	r2, r3, #30
 80078ca:	bf04      	itt	eq
 80078cc:	089b      	lsreq	r3, r3, #2
 80078ce:	3002      	addeq	r0, #2
 80078d0:	07da      	lsls	r2, r3, #31
 80078d2:	d402      	bmi.n	80078da <__lo0bits+0x4e>
 80078d4:	085b      	lsrs	r3, r3, #1
 80078d6:	d006      	beq.n	80078e6 <__lo0bits+0x5a>
 80078d8:	3001      	adds	r0, #1
 80078da:	600b      	str	r3, [r1, #0]
 80078dc:	4770      	bx	lr
 80078de:	4610      	mov	r0, r2
 80078e0:	e7e9      	b.n	80078b6 <__lo0bits+0x2a>
 80078e2:	2000      	movs	r0, #0
 80078e4:	4770      	bx	lr
 80078e6:	2020      	movs	r0, #32
 80078e8:	4770      	bx	lr

080078ea <__i2b>:
 80078ea:	b510      	push	{r4, lr}
 80078ec:	460c      	mov	r4, r1
 80078ee:	2101      	movs	r1, #1
 80078f0:	f7ff ff27 	bl	8007742 <_Balloc>
 80078f4:	2201      	movs	r2, #1
 80078f6:	6144      	str	r4, [r0, #20]
 80078f8:	6102      	str	r2, [r0, #16]
 80078fa:	bd10      	pop	{r4, pc}

080078fc <__multiply>:
 80078fc:	e92d 4ff7 	stmdb	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
 8007900:	4614      	mov	r4, r2
 8007902:	690a      	ldr	r2, [r1, #16]
 8007904:	6923      	ldr	r3, [r4, #16]
 8007906:	4688      	mov	r8, r1
 8007908:	429a      	cmp	r2, r3
 800790a:	bfbe      	ittt	lt
 800790c:	460b      	movlt	r3, r1
 800790e:	46a0      	movlt	r8, r4
 8007910:	461c      	movlt	r4, r3
 8007912:	f8d8 7010 	ldr.w	r7, [r8, #16]
 8007916:	f8d4 9010 	ldr.w	r9, [r4, #16]
 800791a:	f8d8 3008 	ldr.w	r3, [r8, #8]
 800791e:	f8d8 1004 	ldr.w	r1, [r8, #4]
 8007922:	eb07 0609 	add.w	r6, r7, r9
 8007926:	42b3      	cmp	r3, r6
 8007928:	bfb8      	it	lt
 800792a:	3101      	addlt	r1, #1
 800792c:	f7ff ff09 	bl	8007742 <_Balloc>
 8007930:	f100 0514 	add.w	r5, r0, #20
 8007934:	462b      	mov	r3, r5
 8007936:	2200      	movs	r2, #0
 8007938:	eb05 0e86 	add.w	lr, r5, r6, lsl #2
 800793c:	4573      	cmp	r3, lr
 800793e:	d316      	bcc.n	800796e <__multiply+0x72>
 8007940:	f104 0214 	add.w	r2, r4, #20
 8007944:	f108 0114 	add.w	r1, r8, #20
 8007948:	eb02 0389 	add.w	r3, r2, r9, lsl #2
 800794c:	eb01 0787 	add.w	r7, r1, r7, lsl #2
 8007950:	9300      	str	r3, [sp, #0]
 8007952:	9b00      	ldr	r3, [sp, #0]
 8007954:	9201      	str	r2, [sp, #4]
 8007956:	4293      	cmp	r3, r2
 8007958:	d80c      	bhi.n	8007974 <__multiply+0x78>
 800795a:	2e00      	cmp	r6, #0
 800795c:	dd03      	ble.n	8007966 <__multiply+0x6a>
 800795e:	f85e 3d04 	ldr.w	r3, [lr, #-4]!
 8007962:	2b00      	cmp	r3, #0
 8007964:	d05d      	beq.n	8007a22 <__multiply+0x126>
 8007966:	6106      	str	r6, [r0, #16]
 8007968:	b003      	add	sp, #12
 800796a:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
 800796e:	f843 2b04 	str.w	r2, [r3], #4
 8007972:	e7e3      	b.n	800793c <__multiply+0x40>
 8007974:	f8b2 b000 	ldrh.w	fp, [r2]
 8007978:	f1bb 0f00 	cmp.w	fp, #0
 800797c:	d023      	beq.n	80079c6 <__multiply+0xca>
 800797e:	4689      	mov	r9, r1
 8007980:	46ac      	mov	ip, r5
 8007982:	f04f 0800 	mov.w	r8, #0
 8007986:	f859 4b04 	ldr.w	r4, [r9], #4
 800798a:	f8dc a000 	ldr.w	sl, [ip]
 800798e:	b2a3      	uxth	r3, r4
 8007990:	fa1f fa8a 	uxth.w	sl, sl
 8007994:	fb0b a303 	mla	r3, fp, r3, sl
 8007998:	ea4f 4a14 	mov.w	sl, r4, lsr #16
 800799c:	f8dc 4000 	ldr.w	r4, [ip]
 80079a0:	4443      	add	r3, r8
 80079a2:	ea4f 4814 	mov.w	r8, r4, lsr #16
 80079a6:	fb0b 840a 	mla	r4, fp, sl, r8
 80079aa:	46e2      	mov	sl, ip
 80079ac:	eb04 4413 	add.w	r4, r4, r3, lsr #16
 80079b0:	b29b      	uxth	r3, r3
 80079b2:	ea43 4304 	orr.w	r3, r3, r4, lsl #16
 80079b6:	454f      	cmp	r7, r9
 80079b8:	ea4f 4814 	mov.w	r8, r4, lsr #16
 80079bc:	f84a 3b04 	str.w	r3, [sl], #4
 80079c0:	d82b      	bhi.n	8007a1a <__multiply+0x11e>
 80079c2:	f8cc 8004 	str.w	r8, [ip, #4]
 80079c6:	9b01      	ldr	r3, [sp, #4]
 80079c8:	3204      	adds	r2, #4
 80079ca:	f8b3 a002 	ldrh.w	sl, [r3, #2]
 80079ce:	f1ba 0f00 	cmp.w	sl, #0
 80079d2:	d020      	beq.n	8007a16 <__multiply+0x11a>
 80079d4:	4689      	mov	r9, r1
 80079d6:	46a8      	mov	r8, r5
 80079d8:	f04f 0b00 	mov.w	fp, #0
 80079dc:	682b      	ldr	r3, [r5, #0]
 80079de:	f8b9 c000 	ldrh.w	ip, [r9]
 80079e2:	f8b8 4002 	ldrh.w	r4, [r8, #2]
 80079e6:	b29b      	uxth	r3, r3
 80079e8:	fb0a 440c 	mla	r4, sl, ip, r4
 80079ec:	46c4      	mov	ip, r8
 80079ee:	445c      	add	r4, fp
 80079f0:	ea43 4304 	orr.w	r3, r3, r4, lsl #16
 80079f4:	f84c 3b04 	str.w	r3, [ip], #4
 80079f8:	f859 3b04 	ldr.w	r3, [r9], #4
 80079fc:	f8b8 b004 	ldrh.w	fp, [r8, #4]
 8007a00:	0c1b      	lsrs	r3, r3, #16
 8007a02:	fb0a b303 	mla	r3, sl, r3, fp
 8007a06:	454f      	cmp	r7, r9
 8007a08:	eb03 4314 	add.w	r3, r3, r4, lsr #16
 8007a0c:	ea4f 4b13 	mov.w	fp, r3, lsr #16
 8007a10:	d805      	bhi.n	8007a1e <__multiply+0x122>
 8007a12:	f8c8 3004 	str.w	r3, [r8, #4]
 8007a16:	3504      	adds	r5, #4
 8007a18:	e79b      	b.n	8007952 <__multiply+0x56>
 8007a1a:	46d4      	mov	ip, sl
 8007a1c:	e7b3      	b.n	8007986 <__multiply+0x8a>
 8007a1e:	46e0      	mov	r8, ip
 8007a20:	e7dd      	b.n	80079de <__multiply+0xe2>
 8007a22:	3e01      	subs	r6, #1
 8007a24:	e799      	b.n	800795a <__multiply+0x5e>
	...

08007a28 <__pow5mult>:
 8007a28:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
 8007a2c:	4615      	mov	r5, r2
 8007a2e:	f012 0203 	ands.w	r2, r2, #3
 8007a32:	4606      	mov	r6, r0
 8007a34:	460f      	mov	r7, r1
 8007a36:	d007      	beq.n	8007a48 <__pow5mult+0x20>
 8007a38:	4c21      	ldr	r4, [pc, #132]	; (8007ac0 <__pow5mult+0x98>)
 8007a3a:	3a01      	subs	r2, #1
 8007a3c:	2300      	movs	r3, #0
 8007a3e:	f854 2022 	ldr.w	r2, [r4, r2, lsl #2]
 8007a42:	f7ff fec9 	bl	80077d8 <__multadd>
 8007a46:	4607      	mov	r7, r0
 8007a48:	10ad      	asrs	r5, r5, #2
 8007a4a:	d035      	beq.n	8007ab8 <__pow5mult+0x90>
 8007a4c:	6a74      	ldr	r4, [r6, #36]	; 0x24
 8007a4e:	b93c      	cbnz	r4, 8007a60 <__pow5mult+0x38>
 8007a50:	2010      	movs	r0, #16
 8007a52:	f7ff fe55 	bl	8007700 <malloc>
 8007a56:	6270      	str	r0, [r6, #36]	; 0x24
 8007a58:	e9c0 4401 	strd	r4, r4, [r0, #4]
 8007a5c:	6004      	str	r4, [r0, #0]
 8007a5e:	60c4      	str	r4, [r0, #12]
 8007a60:	f8d6 8024 	ldr.w	r8, [r6, #36]	; 0x24
 8007a64:	f8d8 4008 	ldr.w	r4, [r8, #8]
 8007a68:	b94c      	cbnz	r4, 8007a7e <__pow5mult+0x56>
 8007a6a:	f240 2171 	movw	r1, #625	; 0x271
 8007a6e:	4630      	mov	r0, r6
 8007a70:	f7ff ff3b 	bl	80078ea <__i2b>
 8007a74:	2300      	movs	r3, #0
 8007a76:	4604      	mov	r4, r0
 8007a78:	f8c8 0008 	str.w	r0, [r8, #8]
 8007a7c:	6003      	str	r3, [r0, #0]
 8007a7e:	f04f 0800 	mov.w	r8, #0
 8007a82:	07eb      	lsls	r3, r5, #31
 8007a84:	d50a      	bpl.n	8007a9c <__pow5mult+0x74>
 8007a86:	4639      	mov	r1, r7
 8007a88:	4622      	mov	r2, r4
 8007a8a:	4630      	mov	r0, r6
 8007a8c:	f7ff ff36 	bl	80078fc <__multiply>
 8007a90:	4681      	mov	r9, r0
 8007a92:	4639      	mov	r1, r7
 8007a94:	4630      	mov	r0, r6
 8007a96:	f7ff fe88 	bl	80077aa <_Bfree>
 8007a9a:	464f      	mov	r7, r9
 8007a9c:	106d      	asrs	r5, r5, #1
 8007a9e:	d00b      	beq.n	8007ab8 <__pow5mult+0x90>
 8007aa0:	6820      	ldr	r0, [r4, #0]
 8007aa2:	b938      	cbnz	r0, 8007ab4 <__pow5mult+0x8c>
 8007aa4:	4622      	mov	r2, r4
 8007aa6:	4621      	mov	r1, r4
 8007aa8:	4630      	mov	r0, r6
 8007aaa:	f7ff ff27 	bl	80078fc <__multiply>
 8007aae:	6020      	str	r0, [r4, #0]
 8007ab0:	f8c0 8000 	str.w	r8, [r0]
 8007ab4:	4604      	mov	r4, r0
 8007ab6:	e7e4      	b.n	8007a82 <__pow5mult+0x5a>
 8007ab8:	4638      	mov	r0, r7
 8007aba:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
 8007abe:	bf00      	nop
 8007ac0:	08008790 	.word	0x08008790

08007ac4 <__lshift>:
 8007ac4:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
 8007ac8:	460c      	mov	r4, r1
 8007aca:	4607      	mov	r7, r0
 8007acc:	4616      	mov	r6, r2
 8007ace:	6923      	ldr	r3, [r4, #16]
 8007ad0:	ea4f 1a62 	mov.w	sl, r2, asr #5
 8007ad4:	eb0a 0903 	add.w	r9, sl, r3
 8007ad8:	6849      	ldr	r1, [r1, #4]
 8007ada:	68a3      	ldr	r3, [r4, #8]
 8007adc:	f109 0501 	add.w	r5, r9, #1
 8007ae0:	42ab      	cmp	r3, r5
 8007ae2:	db32      	blt.n	8007b4a <__lshift+0x86>
 8007ae4:	4638      	mov	r0, r7
 8007ae6:	f7ff fe2c 	bl	8007742 <_Balloc>
 8007aea:	2300      	movs	r3, #0
 8007aec:	4680      	mov	r8, r0
 8007aee:	461a      	mov	r2, r3
 8007af0:	f100 0114 	add.w	r1, r0, #20
 8007af4:	4553      	cmp	r3, sl
 8007af6:	db2b      	blt.n	8007b50 <__lshift+0x8c>
 8007af8:	6920      	ldr	r0, [r4, #16]
 8007afa:	ea2a 7aea 	bic.w	sl, sl, sl, asr #31
 8007afe:	f104 0314 	add.w	r3, r4, #20
 8007b02:	f016 021f 	ands.w	r2, r6, #31
 8007b06:	eb01 018a 	add.w	r1, r1, sl, lsl #2
 8007b0a:	eb03 0c80 	add.w	ip, r3, r0, lsl #2
 8007b0e:	d025      	beq.n	8007b5c <__lshift+0x98>
 8007b10:	2000      	movs	r0, #0
 8007b12:	f1c2 0e20 	rsb	lr, r2, #32
 8007b16:	468a      	mov	sl, r1
 8007b18:	681e      	ldr	r6, [r3, #0]
 8007b1a:	4096      	lsls	r6, r2
 8007b1c:	4330      	orrs	r0, r6
 8007b1e:	f84a 0b04 	str.w	r0, [sl], #4
 8007b22:	f853 0b04 	ldr.w	r0, [r3], #4
 8007b26:	459c      	cmp	ip, r3
 8007b28:	fa20 f00e 	lsr.w	r0, r0, lr
 8007b2c:	d814      	bhi.n	8007b58 <__lshift+0x94>
 8007b2e:	6048      	str	r0, [r1, #4]
 8007b30:	b108      	cbz	r0, 8007b36 <__lshift+0x72>
 8007b32:	f109 0502 	add.w	r5, r9, #2
 8007b36:	3d01      	subs	r5, #1
 8007b38:	4638      	mov	r0, r7
 8007b3a:	f8c8 5010 	str.w	r5, [r8, #16]
 8007b3e:	4621      	mov	r1, r4
 8007b40:	f7ff fe33 	bl	80077aa <_Bfree>
 8007b44:	4640      	mov	r0, r8
 8007b46:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 8007b4a:	3101      	adds	r1, #1
 8007b4c:	005b      	lsls	r3, r3, #1
 8007b4e:	e7c7      	b.n	8007ae0 <__lshift+0x1c>
 8007b50:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
 8007b54:	3301      	adds	r3, #1
 8007b56:	e7cd      	b.n	8007af4 <__lshift+0x30>
 8007b58:	4651      	mov	r1, sl
 8007b5a:	e7dc      	b.n	8007b16 <__lshift+0x52>
 8007b5c:	3904      	subs	r1, #4
 8007b5e:	f853 2b04 	ldr.w	r2, [r3], #4
 8007b62:	459c      	cmp	ip, r3
 8007b64:	f841 2f04 	str.w	r2, [r1, #4]!
 8007b68:	d8f9      	bhi.n	8007b5e <__lshift+0x9a>
 8007b6a:	e7e4      	b.n	8007b36 <__lshift+0x72>

08007b6c <__mcmp>:
 8007b6c:	6903      	ldr	r3, [r0, #16]
 8007b6e:	690a      	ldr	r2, [r1, #16]
 8007b70:	b530      	push	{r4, r5, lr}
 8007b72:	1a9b      	subs	r3, r3, r2
 8007b74:	d10c      	bne.n	8007b90 <__mcmp+0x24>
 8007b76:	0092      	lsls	r2, r2, #2
 8007b78:	3014      	adds	r0, #20
 8007b7a:	3114      	adds	r1, #20
 8007b7c:	1884      	adds	r4, r0, r2
 8007b7e:	4411      	add	r1, r2
 8007b80:	f854 5d04 	ldr.w	r5, [r4, #-4]!
 8007b84:	f851 2d04 	ldr.w	r2, [r1, #-4]!
 8007b88:	4295      	cmp	r5, r2
 8007b8a:	d003      	beq.n	8007b94 <__mcmp+0x28>
 8007b8c:	d305      	bcc.n	8007b9a <__mcmp+0x2e>
 8007b8e:	2301      	movs	r3, #1
 8007b90:	4618      	mov	r0, r3
 8007b92:	bd30      	pop	{r4, r5, pc}
 8007b94:	42a0      	cmp	r0, r4
 8007b96:	d3f3      	bcc.n	8007b80 <__mcmp+0x14>
 8007b98:	e7fa      	b.n	8007b90 <__mcmp+0x24>
 8007b9a:	f04f 33ff 	mov.w	r3, #4294967295
 8007b9e:	e7f7      	b.n	8007b90 <__mcmp+0x24>

08007ba0 <__mdiff>:
 8007ba0:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
 8007ba4:	460d      	mov	r5, r1
 8007ba6:	4607      	mov	r7, r0
 8007ba8:	4611      	mov	r1, r2
 8007baa:	4628      	mov	r0, r5
 8007bac:	4614      	mov	r4, r2
 8007bae:	f7ff ffdd 	bl	8007b6c <__mcmp>
 8007bb2:	1e06      	subs	r6, r0, #0
 8007bb4:	d108      	bne.n	8007bc8 <__mdiff+0x28>
 8007bb6:	4631      	mov	r1, r6
 8007bb8:	4638      	mov	r0, r7
 8007bba:	f7ff fdc2 	bl	8007742 <_Balloc>
 8007bbe:	2301      	movs	r3, #1
 8007bc0:	e9c0 3604 	strd	r3, r6, [r0, #16]
 8007bc4:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 8007bc8:	bfa4      	itt	ge
 8007bca:	4623      	movge	r3, r4
 8007bcc:	462c      	movge	r4, r5
 8007bce:	4638      	mov	r0, r7
 8007bd0:	6861      	ldr	r1, [r4, #4]
 8007bd2:	bfa6      	itte	ge
 8007bd4:	461d      	movge	r5, r3
 8007bd6:	2600      	movge	r6, #0
 8007bd8:	2601      	movlt	r6, #1
 8007bda:	f7ff fdb2 	bl	8007742 <_Balloc>
 8007bde:	f04f 0e00 	mov.w	lr, #0
 8007be2:	60c6      	str	r6, [r0, #12]
 8007be4:	692b      	ldr	r3, [r5, #16]
 8007be6:	6926      	ldr	r6, [r4, #16]
 8007be8:	f104 0214 	add.w	r2, r4, #20
 8007bec:	f105 0914 	add.w	r9, r5, #20
 8007bf0:	eb02 0786 	add.w	r7, r2, r6, lsl #2
 8007bf4:	eb09 0883 	add.w	r8, r9, r3, lsl #2
 8007bf8:	f100 0114 	add.w	r1, r0, #20
 8007bfc:	f852 ab04 	ldr.w	sl, [r2], #4
 8007c00:	f859 5b04 	ldr.w	r5, [r9], #4
 8007c04:	fa1f f38a 	uxth.w	r3, sl
 8007c08:	4473      	add	r3, lr
 8007c0a:	b2ac      	uxth	r4, r5
 8007c0c:	1b1b      	subs	r3, r3, r4
 8007c0e:	0c2c      	lsrs	r4, r5, #16
 8007c10:	ebc4 441a 	rsb	r4, r4, sl, lsr #16
 8007c14:	eb04 4423 	add.w	r4, r4, r3, asr #16
 8007c18:	b29b      	uxth	r3, r3
 8007c1a:	ea4f 4e24 	mov.w	lr, r4, asr #16
 8007c1e:	45c8      	cmp	r8, r9
 8007c20:	ea43 4404 	orr.w	r4, r3, r4, lsl #16
 8007c24:	4694      	mov	ip, r2
 8007c26:	f841 4b04 	str.w	r4, [r1], #4
 8007c2a:	d8e7      	bhi.n	8007bfc <__mdiff+0x5c>
 8007c2c:	45bc      	cmp	ip, r7
 8007c2e:	d304      	bcc.n	8007c3a <__mdiff+0x9a>
 8007c30:	f851 3d04 	ldr.w	r3, [r1, #-4]!
 8007c34:	b183      	cbz	r3, 8007c58 <__mdiff+0xb8>
 8007c36:	6106      	str	r6, [r0, #16]
 8007c38:	e7c4      	b.n	8007bc4 <__mdiff+0x24>
 8007c3a:	f85c 4b04 	ldr.w	r4, [ip], #4
 8007c3e:	b2a2      	uxth	r2, r4
 8007c40:	4472      	add	r2, lr
 8007c42:	1413      	asrs	r3, r2, #16
 8007c44:	eb03 4314 	add.w	r3, r3, r4, lsr #16
 8007c48:	b292      	uxth	r2, r2
 8007c4a:	ea42 4203 	orr.w	r2, r2, r3, lsl #16
 8007c4e:	ea4f 4e23 	mov.w	lr, r3, asr #16
 8007c52:	f841 2b04 	str.w	r2, [r1], #4
 8007c56:	e7e9      	b.n	8007c2c <__mdiff+0x8c>
 8007c58:	3e01      	subs	r6, #1
 8007c5a:	e7e9      	b.n	8007c30 <__mdiff+0x90>

08007c5c <__d2b>:
 8007c5c:	e92d 41f3 	stmdb	sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
 8007c60:	461c      	mov	r4, r3
 8007c62:	e9dd 6508 	ldrd	r6, r5, [sp, #32]
 8007c66:	2101      	movs	r1, #1
 8007c68:	4690      	mov	r8, r2
 8007c6a:	f7ff fd6a 	bl	8007742 <_Balloc>
 8007c6e:	f3c4 0213 	ubfx	r2, r4, #0, #20
 8007c72:	f3c4 540a 	ubfx	r4, r4, #20, #11
 8007c76:	4607      	mov	r7, r0
 8007c78:	bb34      	cbnz	r4, 8007cc8 <__d2b+0x6c>
 8007c7a:	9201      	str	r2, [sp, #4]
 8007c7c:	f1b8 0200 	subs.w	r2, r8, #0
 8007c80:	d027      	beq.n	8007cd2 <__d2b+0x76>
 8007c82:	a802      	add	r0, sp, #8
 8007c84:	f840 2d08 	str.w	r2, [r0, #-8]!
 8007c88:	f7ff fe00 	bl	800788c <__lo0bits>
 8007c8c:	9900      	ldr	r1, [sp, #0]
 8007c8e:	b1f0      	cbz	r0, 8007cce <__d2b+0x72>
 8007c90:	9a01      	ldr	r2, [sp, #4]
 8007c92:	f1c0 0320 	rsb	r3, r0, #32
 8007c96:	fa02 f303 	lsl.w	r3, r2, r3
 8007c9a:	430b      	orrs	r3, r1
 8007c9c:	40c2      	lsrs	r2, r0
 8007c9e:	617b      	str	r3, [r7, #20]
 8007ca0:	9201      	str	r2, [sp, #4]
 8007ca2:	9b01      	ldr	r3, [sp, #4]
 8007ca4:	2b00      	cmp	r3, #0
 8007ca6:	bf14      	ite	ne
 8007ca8:	2102      	movne	r1, #2
 8007caa:	2101      	moveq	r1, #1
 8007cac:	61bb      	str	r3, [r7, #24]
 8007cae:	6139      	str	r1, [r7, #16]
 8007cb0:	b1c4      	cbz	r4, 8007ce4 <__d2b+0x88>
 8007cb2:	f2a4 4433 	subw	r4, r4, #1075	; 0x433
 8007cb6:	4404      	add	r4, r0
 8007cb8:	6034      	str	r4, [r6, #0]
 8007cba:	f1c0 0035 	rsb	r0, r0, #53	; 0x35
 8007cbe:	6028      	str	r0, [r5, #0]
 8007cc0:	4638      	mov	r0, r7
 8007cc2:	b002      	add	sp, #8
 8007cc4:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
 8007cc8:	f442 1280 	orr.w	r2, r2, #1048576	; 0x100000
 8007ccc:	e7d5      	b.n	8007c7a <__d2b+0x1e>
 8007cce:	6179      	str	r1, [r7, #20]
 8007cd0:	e7e7      	b.n	8007ca2 <__d2b+0x46>
 8007cd2:	a801      	add	r0, sp, #4
 8007cd4:	f7ff fdda 	bl	800788c <__lo0bits>
 8007cd8:	2101      	movs	r1, #1
 8007cda:	9b01      	ldr	r3, [sp, #4]
 8007cdc:	6139      	str	r1, [r7, #16]
 8007cde:	617b      	str	r3, [r7, #20]
 8007ce0:	3020      	adds	r0, #32
 8007ce2:	e7e5      	b.n	8007cb0 <__d2b+0x54>
 8007ce4:	f2a0 4032 	subw	r0, r0, #1074	; 0x432
 8007ce8:	eb07 0381 	add.w	r3, r7, r1, lsl #2
 8007cec:	6030      	str	r0, [r6, #0]
 8007cee:	6918      	ldr	r0, [r3, #16]
 8007cf0:	f7ff fdad 	bl	800784e <__hi0bits>
 8007cf4:	ebc0 1041 	rsb	r0, r0, r1, lsl #5
 8007cf8:	e7e1      	b.n	8007cbe <__d2b+0x62>

08007cfa <_calloc_r>:
 8007cfa:	b538      	push	{r3, r4, r5, lr}
 8007cfc:	fb02 f401 	mul.w	r4, r2, r1
 8007d00:	4621      	mov	r1, r4
 8007d02:	f000 f855 	bl	8007db0 <_malloc_r>
 8007d06:	4605      	mov	r5, r0
 8007d08:	b118      	cbz	r0, 8007d12 <_calloc_r+0x18>
 8007d0a:	4622      	mov	r2, r4
 8007d0c:	2100      	movs	r1, #0
 8007d0e:	f7fd fe7d 	bl	8005a0c <memset>
 8007d12:	4628      	mov	r0, r5
 8007d14:	bd38      	pop	{r3, r4, r5, pc}
	...

08007d18 <_free_r>:
 8007d18:	b538      	push	{r3, r4, r5, lr}
 8007d1a:	4605      	mov	r5, r0
 8007d1c:	2900      	cmp	r1, #0
 8007d1e:	d043      	beq.n	8007da8 <_free_r+0x90>
 8007d20:	f851 3c04 	ldr.w	r3, [r1, #-4]
 8007d24:	1f0c      	subs	r4, r1, #4
 8007d26:	2b00      	cmp	r3, #0
 8007d28:	bfb8      	it	lt
 8007d2a:	18e4      	addlt	r4, r4, r3
 8007d2c:	f000 fa94 	bl	8008258 <__malloc_lock>
 8007d30:	4a1e      	ldr	r2, [pc, #120]	; (8007dac <_free_r+0x94>)
 8007d32:	6813      	ldr	r3, [r2, #0]
 8007d34:	4610      	mov	r0, r2
 8007d36:	b933      	cbnz	r3, 8007d46 <_free_r+0x2e>
 8007d38:	6063      	str	r3, [r4, #4]
 8007d3a:	6014      	str	r4, [r2, #0]
 8007d3c:	4628      	mov	r0, r5
 8007d3e:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
 8007d42:	f000 ba8a 	b.w	800825a <__malloc_unlock>
 8007d46:	42a3      	cmp	r3, r4
 8007d48:	d90b      	bls.n	8007d62 <_free_r+0x4a>
 8007d4a:	6821      	ldr	r1, [r4, #0]
 8007d4c:	1862      	adds	r2, r4, r1
 8007d4e:	4293      	cmp	r3, r2
 8007d50:	bf01      	itttt	eq
 8007d52:	681a      	ldreq	r2, [r3, #0]
 8007d54:	685b      	ldreq	r3, [r3, #4]
 8007d56:	1852      	addeq	r2, r2, r1
 8007d58:	6022      	streq	r2, [r4, #0]
 8007d5a:	6063      	str	r3, [r4, #4]
 8007d5c:	6004      	str	r4, [r0, #0]
 8007d5e:	e7ed      	b.n	8007d3c <_free_r+0x24>
 8007d60:	4613      	mov	r3, r2
 8007d62:	685a      	ldr	r2, [r3, #4]
 8007d64:	b10a      	cbz	r2, 8007d6a <_free_r+0x52>
 8007d66:	42a2      	cmp	r2, r4
 8007d68:	d9fa      	bls.n	8007d60 <_free_r+0x48>
 8007d6a:	6819      	ldr	r1, [r3, #0]
 8007d6c:	1858      	adds	r0, r3, r1
 8007d6e:	42a0      	cmp	r0, r4
 8007d70:	d10b      	bne.n	8007d8a <_free_r+0x72>
 8007d72:	6820      	ldr	r0, [r4, #0]
 8007d74:	4401      	add	r1, r0
 8007d76:	1858      	adds	r0, r3, r1
 8007d78:	4282      	cmp	r2, r0
 8007d7a:	6019      	str	r1, [r3, #0]
 8007d7c:	d1de      	bne.n	8007d3c <_free_r+0x24>
 8007d7e:	6810      	ldr	r0, [r2, #0]
 8007d80:	6852      	ldr	r2, [r2, #4]
 8007d82:	4401      	add	r1, r0
 8007d84:	6019      	str	r1, [r3, #0]
 8007d86:	605a      	str	r2, [r3, #4]
 8007d88:	e7d8      	b.n	8007d3c <_free_r+0x24>
 8007d8a:	d902      	bls.n	8007d92 <_free_r+0x7a>
 8007d8c:	230c      	movs	r3, #12
 8007d8e:	602b      	str	r3, [r5, #0]
 8007d90:	e7d4      	b.n	8007d3c <_free_r+0x24>
 8007d92:	6820      	ldr	r0, [r4, #0]
 8007d94:	1821      	adds	r1, r4, r0
 8007d96:	428a      	cmp	r2, r1
 8007d98:	bf01      	itttt	eq
 8007d9a:	6811      	ldreq	r1, [r2, #0]
 8007d9c:	6852      	ldreq	r2, [r2, #4]
 8007d9e:	1809      	addeq	r1, r1, r0
 8007da0:	6021      	streq	r1, [r4, #0]
 8007da2:	6062      	str	r2, [r4, #4]
 8007da4:	605c      	str	r4, [r3, #4]
 8007da6:	e7c9      	b.n	8007d3c <_free_r+0x24>
 8007da8:	bd38      	pop	{r3, r4, r5, pc}
 8007daa:	bf00      	nop
 8007dac:	200003f4 	.word	0x200003f4

08007db0 <_malloc_r>:
 8007db0:	b570      	push	{r4, r5, r6, lr}
 8007db2:	1ccd      	adds	r5, r1, #3
 8007db4:	f025 0503 	bic.w	r5, r5, #3
 8007db8:	3508      	adds	r5, #8
 8007dba:	2d0c      	cmp	r5, #12
 8007dbc:	bf38      	it	cc
 8007dbe:	250c      	movcc	r5, #12
 8007dc0:	2d00      	cmp	r5, #0
 8007dc2:	4606      	mov	r6, r0
 8007dc4:	db01      	blt.n	8007dca <_malloc_r+0x1a>
 8007dc6:	42a9      	cmp	r1, r5
 8007dc8:	d903      	bls.n	8007dd2 <_malloc_r+0x22>
 8007dca:	230c      	movs	r3, #12
 8007dcc:	6033      	str	r3, [r6, #0]
 8007dce:	2000      	movs	r0, #0
 8007dd0:	bd70      	pop	{r4, r5, r6, pc}
 8007dd2:	f000 fa41 	bl	8008258 <__malloc_lock>
 8007dd6:	4a21      	ldr	r2, [pc, #132]	; (8007e5c <_malloc_r+0xac>)
 8007dd8:	6814      	ldr	r4, [r2, #0]
 8007dda:	4621      	mov	r1, r4
 8007ddc:	b991      	cbnz	r1, 8007e04 <_malloc_r+0x54>
 8007dde:	4c20      	ldr	r4, [pc, #128]	; (8007e60 <_malloc_r+0xb0>)
 8007de0:	6823      	ldr	r3, [r4, #0]
 8007de2:	b91b      	cbnz	r3, 8007dec <_malloc_r+0x3c>
 8007de4:	4630      	mov	r0, r6
 8007de6:	f000 f97b 	bl	80080e0 <_sbrk_r>
 8007dea:	6020      	str	r0, [r4, #0]
 8007dec:	4629      	mov	r1, r5
 8007dee:	4630      	mov	r0, r6
 8007df0:	f000 f976 	bl	80080e0 <_sbrk_r>
 8007df4:	1c43      	adds	r3, r0, #1
 8007df6:	d124      	bne.n	8007e42 <_malloc_r+0x92>
 8007df8:	230c      	movs	r3, #12
 8007dfa:	4630      	mov	r0, r6
 8007dfc:	6033      	str	r3, [r6, #0]
 8007dfe:	f000 fa2c 	bl	800825a <__malloc_unlock>
 8007e02:	e7e4      	b.n	8007dce <_malloc_r+0x1e>
 8007e04:	680b      	ldr	r3, [r1, #0]
 8007e06:	1b5b      	subs	r3, r3, r5
 8007e08:	d418      	bmi.n	8007e3c <_malloc_r+0x8c>
 8007e0a:	2b0b      	cmp	r3, #11
 8007e0c:	d90f      	bls.n	8007e2e <_malloc_r+0x7e>
 8007e0e:	600b      	str	r3, [r1, #0]
 8007e10:	18cc      	adds	r4, r1, r3
 8007e12:	50cd      	str	r5, [r1, r3]
 8007e14:	4630      	mov	r0, r6
 8007e16:	f000 fa20 	bl	800825a <__malloc_unlock>
 8007e1a:	f104 000b 	add.w	r0, r4, #11
 8007e1e:	1d23      	adds	r3, r4, #4
 8007e20:	f020 0007 	bic.w	r0, r0, #7
 8007e24:	1ac3      	subs	r3, r0, r3
 8007e26:	d0d3      	beq.n	8007dd0 <_malloc_r+0x20>
 8007e28:	425a      	negs	r2, r3
 8007e2a:	50e2      	str	r2, [r4, r3]
 8007e2c:	e7d0      	b.n	8007dd0 <_malloc_r+0x20>
 8007e2e:	684b      	ldr	r3, [r1, #4]
 8007e30:	428c      	cmp	r4, r1
 8007e32:	bf16      	itet	ne
 8007e34:	6063      	strne	r3, [r4, #4]
 8007e36:	6013      	streq	r3, [r2, #0]
 8007e38:	460c      	movne	r4, r1
 8007e3a:	e7eb      	b.n	8007e14 <_malloc_r+0x64>
 8007e3c:	460c      	mov	r4, r1
 8007e3e:	6849      	ldr	r1, [r1, #4]
 8007e40:	e7cc      	b.n	8007ddc <_malloc_r+0x2c>
 8007e42:	1cc4      	adds	r4, r0, #3
 8007e44:	f024 0403 	bic.w	r4, r4, #3
 8007e48:	42a0      	cmp	r0, r4
 8007e4a:	d005      	beq.n	8007e58 <_malloc_r+0xa8>
 8007e4c:	1a21      	subs	r1, r4, r0
 8007e4e:	4630      	mov	r0, r6
 8007e50:	f000 f946 	bl	80080e0 <_sbrk_r>
 8007e54:	3001      	adds	r0, #1
 8007e56:	d0cf      	beq.n	8007df8 <_malloc_r+0x48>
 8007e58:	6025      	str	r5, [r4, #0]
 8007e5a:	e7db      	b.n	8007e14 <_malloc_r+0x64>
 8007e5c:	200003f4 	.word	0x200003f4
 8007e60:	200003f8 	.word	0x200003f8

08007e64 <__sfputc_r>:
 8007e64:	6893      	ldr	r3, [r2, #8]
 8007e66:	b410      	push	{r4}
 8007e68:	3b01      	subs	r3, #1
 8007e6a:	2b00      	cmp	r3, #0
 8007e6c:	6093      	str	r3, [r2, #8]
 8007e6e:	da07      	bge.n	8007e80 <__sfputc_r+0x1c>
 8007e70:	6994      	ldr	r4, [r2, #24]
 8007e72:	42a3      	cmp	r3, r4
 8007e74:	db01      	blt.n	8007e7a <__sfputc_r+0x16>
 8007e76:	290a      	cmp	r1, #10
 8007e78:	d102      	bne.n	8007e80 <__sfputc_r+0x1c>
 8007e7a:	bc10      	pop	{r4}
 8007e7c:	f7fe bb50 	b.w	8006520 <__swbuf_r>
 8007e80:	6813      	ldr	r3, [r2, #0]
 8007e82:	1c58      	adds	r0, r3, #1
 8007e84:	6010      	str	r0, [r2, #0]
 8007e86:	7019      	strb	r1, [r3, #0]
 8007e88:	4608      	mov	r0, r1
 8007e8a:	bc10      	pop	{r4}
 8007e8c:	4770      	bx	lr

08007e8e <__sfputs_r>:
 8007e8e:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 8007e90:	4606      	mov	r6, r0
 8007e92:	460f      	mov	r7, r1
 8007e94:	4614      	mov	r4, r2
 8007e96:	18d5      	adds	r5, r2, r3
 8007e98:	42ac      	cmp	r4, r5
 8007e9a:	d101      	bne.n	8007ea0 <__sfputs_r+0x12>
 8007e9c:	2000      	movs	r0, #0
 8007e9e:	e007      	b.n	8007eb0 <__sfputs_r+0x22>
 8007ea0:	463a      	mov	r2, r7
 8007ea2:	f814 1b01 	ldrb.w	r1, [r4], #1
 8007ea6:	4630      	mov	r0, r6
 8007ea8:	f7ff ffdc 	bl	8007e64 <__sfputc_r>
 8007eac:	1c43      	adds	r3, r0, #1
 8007eae:	d1f3      	bne.n	8007e98 <__sfputs_r+0xa>
 8007eb0:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
	...

08007eb4 <_vfiprintf_r>:
 8007eb4:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
 8007eb8:	460c      	mov	r4, r1
 8007eba:	b09d      	sub	sp, #116	; 0x74
 8007ebc:	4617      	mov	r7, r2
 8007ebe:	461d      	mov	r5, r3
 8007ec0:	4606      	mov	r6, r0
 8007ec2:	b118      	cbz	r0, 8007ecc <_vfiprintf_r+0x18>
 8007ec4:	6983      	ldr	r3, [r0, #24]
 8007ec6:	b90b      	cbnz	r3, 8007ecc <_vfiprintf_r+0x18>
 8007ec8:	f7ff fb1e 	bl	8007508 <__sinit>
 8007ecc:	4b7c      	ldr	r3, [pc, #496]	; (80080c0 <_vfiprintf_r+0x20c>)
 8007ece:	429c      	cmp	r4, r3
 8007ed0:	d158      	bne.n	8007f84 <_vfiprintf_r+0xd0>
 8007ed2:	6874      	ldr	r4, [r6, #4]
 8007ed4:	89a3      	ldrh	r3, [r4, #12]
 8007ed6:	0718      	lsls	r0, r3, #28
 8007ed8:	d55e      	bpl.n	8007f98 <_vfiprintf_r+0xe4>
 8007eda:	6923      	ldr	r3, [r4, #16]
 8007edc:	2b00      	cmp	r3, #0
 8007ede:	d05b      	beq.n	8007f98 <_vfiprintf_r+0xe4>
 8007ee0:	2300      	movs	r3, #0
 8007ee2:	9309      	str	r3, [sp, #36]	; 0x24
 8007ee4:	2320      	movs	r3, #32
 8007ee6:	f88d 3029 	strb.w	r3, [sp, #41]	; 0x29
 8007eea:	2330      	movs	r3, #48	; 0x30
 8007eec:	f04f 0b01 	mov.w	fp, #1
 8007ef0:	f88d 302a 	strb.w	r3, [sp, #42]	; 0x2a
 8007ef4:	9503      	str	r5, [sp, #12]
 8007ef6:	46b8      	mov	r8, r7
 8007ef8:	4645      	mov	r5, r8
 8007efa:	f815 3b01 	ldrb.w	r3, [r5], #1
 8007efe:	b10b      	cbz	r3, 8007f04 <_vfiprintf_r+0x50>
 8007f00:	2b25      	cmp	r3, #37	; 0x25
 8007f02:	d154      	bne.n	8007fae <_vfiprintf_r+0xfa>
 8007f04:	ebb8 0a07 	subs.w	sl, r8, r7
 8007f08:	d00b      	beq.n	8007f22 <_vfiprintf_r+0x6e>
 8007f0a:	4653      	mov	r3, sl
 8007f0c:	463a      	mov	r2, r7
 8007f0e:	4621      	mov	r1, r4
 8007f10:	4630      	mov	r0, r6
 8007f12:	f7ff ffbc 	bl	8007e8e <__sfputs_r>
 8007f16:	3001      	adds	r0, #1
 8007f18:	f000 80c2 	beq.w	80080a0 <_vfiprintf_r+0x1ec>
 8007f1c:	9b09      	ldr	r3, [sp, #36]	; 0x24
 8007f1e:	4453      	add	r3, sl
 8007f20:	9309      	str	r3, [sp, #36]	; 0x24
 8007f22:	f898 3000 	ldrb.w	r3, [r8]
 8007f26:	2b00      	cmp	r3, #0
 8007f28:	f000 80ba 	beq.w	80080a0 <_vfiprintf_r+0x1ec>
 8007f2c:	2300      	movs	r3, #0
 8007f2e:	f04f 32ff 	mov.w	r2, #4294967295
 8007f32:	e9cd 2305 	strd	r2, r3, [sp, #20]
 8007f36:	9304      	str	r3, [sp, #16]
 8007f38:	9307      	str	r3, [sp, #28]
 8007f3a:	f88d 3053 	strb.w	r3, [sp, #83]	; 0x53
 8007f3e:	931a      	str	r3, [sp, #104]	; 0x68
 8007f40:	46a8      	mov	r8, r5
 8007f42:	2205      	movs	r2, #5
 8007f44:	f818 1b01 	ldrb.w	r1, [r8], #1
 8007f48:	485e      	ldr	r0, [pc, #376]	; (80080c4 <_vfiprintf_r+0x210>)
 8007f4a:	f7ff fbe1 	bl	8007710 <memchr>
 8007f4e:	9b04      	ldr	r3, [sp, #16]
 8007f50:	bb78      	cbnz	r0, 8007fb2 <_vfiprintf_r+0xfe>
 8007f52:	06d9      	lsls	r1, r3, #27
 8007f54:	bf44      	itt	mi
 8007f56:	2220      	movmi	r2, #32
 8007f58:	f88d 2053 	strbmi.w	r2, [sp, #83]	; 0x53
 8007f5c:	071a      	lsls	r2, r3, #28
 8007f5e:	bf44      	itt	mi
 8007f60:	222b      	movmi	r2, #43	; 0x2b
 8007f62:	f88d 2053 	strbmi.w	r2, [sp, #83]	; 0x53
 8007f66:	782a      	ldrb	r2, [r5, #0]
 8007f68:	2a2a      	cmp	r2, #42	; 0x2a
 8007f6a:	d02a      	beq.n	8007fc2 <_vfiprintf_r+0x10e>
 8007f6c:	46a8      	mov	r8, r5
 8007f6e:	2000      	movs	r0, #0
 8007f70:	250a      	movs	r5, #10
 8007f72:	9a07      	ldr	r2, [sp, #28]
 8007f74:	4641      	mov	r1, r8
 8007f76:	f811 3b01 	ldrb.w	r3, [r1], #1
 8007f7a:	3b30      	subs	r3, #48	; 0x30
 8007f7c:	2b09      	cmp	r3, #9
 8007f7e:	d969      	bls.n	8008054 <_vfiprintf_r+0x1a0>
 8007f80:	b360      	cbz	r0, 8007fdc <_vfiprintf_r+0x128>
 8007f82:	e024      	b.n	8007fce <_vfiprintf_r+0x11a>
 8007f84:	4b50      	ldr	r3, [pc, #320]	; (80080c8 <_vfiprintf_r+0x214>)
 8007f86:	429c      	cmp	r4, r3
 8007f88:	d101      	bne.n	8007f8e <_vfiprintf_r+0xda>
 8007f8a:	68b4      	ldr	r4, [r6, #8]
 8007f8c:	e7a2      	b.n	8007ed4 <_vfiprintf_r+0x20>
 8007f8e:	4b4f      	ldr	r3, [pc, #316]	; (80080cc <_vfiprintf_r+0x218>)
 8007f90:	429c      	cmp	r4, r3
 8007f92:	bf08      	it	eq
 8007f94:	68f4      	ldreq	r4, [r6, #12]
 8007f96:	e79d      	b.n	8007ed4 <_vfiprintf_r+0x20>
 8007f98:	4621      	mov	r1, r4
 8007f9a:	4630      	mov	r0, r6
 8007f9c:	f7fe fb12 	bl	80065c4 <__swsetup_r>
 8007fa0:	2800      	cmp	r0, #0
 8007fa2:	d09d      	beq.n	8007ee0 <_vfiprintf_r+0x2c>
 8007fa4:	f04f 30ff 	mov.w	r0, #4294967295
 8007fa8:	b01d      	add	sp, #116	; 0x74
 8007faa:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
 8007fae:	46a8      	mov	r8, r5
 8007fb0:	e7a2      	b.n	8007ef8 <_vfiprintf_r+0x44>
 8007fb2:	4a44      	ldr	r2, [pc, #272]	; (80080c4 <_vfiprintf_r+0x210>)
 8007fb4:	4645      	mov	r5, r8
 8007fb6:	1a80      	subs	r0, r0, r2
 8007fb8:	fa0b f000 	lsl.w	r0, fp, r0
 8007fbc:	4318      	orrs	r0, r3
 8007fbe:	9004      	str	r0, [sp, #16]
 8007fc0:	e7be      	b.n	8007f40 <_vfiprintf_r+0x8c>
 8007fc2:	9a03      	ldr	r2, [sp, #12]
 8007fc4:	1d11      	adds	r1, r2, #4
 8007fc6:	6812      	ldr	r2, [r2, #0]
 8007fc8:	9103      	str	r1, [sp, #12]
 8007fca:	2a00      	cmp	r2, #0
 8007fcc:	db01      	blt.n	8007fd2 <_vfiprintf_r+0x11e>
 8007fce:	9207      	str	r2, [sp, #28]
 8007fd0:	e004      	b.n	8007fdc <_vfiprintf_r+0x128>
 8007fd2:	4252      	negs	r2, r2
 8007fd4:	f043 0302 	orr.w	r3, r3, #2
 8007fd8:	9207      	str	r2, [sp, #28]
 8007fda:	9304      	str	r3, [sp, #16]
 8007fdc:	f898 3000 	ldrb.w	r3, [r8]
 8007fe0:	2b2e      	cmp	r3, #46	; 0x2e
 8007fe2:	d10e      	bne.n	8008002 <_vfiprintf_r+0x14e>
 8007fe4:	f898 3001 	ldrb.w	r3, [r8, #1]
 8007fe8:	2b2a      	cmp	r3, #42	; 0x2a
 8007fea:	d138      	bne.n	800805e <_vfiprintf_r+0x1aa>
 8007fec:	9b03      	ldr	r3, [sp, #12]
 8007fee:	f108 0802 	add.w	r8, r8, #2
 8007ff2:	1d1a      	adds	r2, r3, #4
 8007ff4:	681b      	ldr	r3, [r3, #0]
 8007ff6:	9203      	str	r2, [sp, #12]
 8007ff8:	2b00      	cmp	r3, #0
 8007ffa:	bfb8      	it	lt
 8007ffc:	f04f 33ff 	movlt.w	r3, #4294967295
 8008000:	9305      	str	r3, [sp, #20]
 8008002:	4d33      	ldr	r5, [pc, #204]	; (80080d0 <_vfiprintf_r+0x21c>)
 8008004:	2203      	movs	r2, #3
 8008006:	f898 1000 	ldrb.w	r1, [r8]
 800800a:	4628      	mov	r0, r5
 800800c:	f7ff fb80 	bl	8007710 <memchr>
 8008010:	b140      	cbz	r0, 8008024 <_vfiprintf_r+0x170>
 8008012:	2340      	movs	r3, #64	; 0x40
 8008014:	1b40      	subs	r0, r0, r5
 8008016:	fa03 f000 	lsl.w	r0, r3, r0
 800801a:	9b04      	ldr	r3, [sp, #16]
 800801c:	f108 0801 	add.w	r8, r8, #1
 8008020:	4303      	orrs	r3, r0
 8008022:	9304      	str	r3, [sp, #16]
 8008024:	f898 1000 	ldrb.w	r1, [r8]
 8008028:	2206      	movs	r2, #6
 800802a:	482a      	ldr	r0, [pc, #168]	; (80080d4 <_vfiprintf_r+0x220>)
 800802c:	f108 0701 	add.w	r7, r8, #1
 8008030:	f88d 1028 	strb.w	r1, [sp, #40]	; 0x28
 8008034:	f7ff fb6c 	bl	8007710 <memchr>
 8008038:	2800      	cmp	r0, #0
 800803a:	d037      	beq.n	80080ac <_vfiprintf_r+0x1f8>
 800803c:	4b26      	ldr	r3, [pc, #152]	; (80080d8 <_vfiprintf_r+0x224>)
 800803e:	bb1b      	cbnz	r3, 8008088 <_vfiprintf_r+0x1d4>
 8008040:	9b03      	ldr	r3, [sp, #12]
 8008042:	3307      	adds	r3, #7
 8008044:	f023 0307 	bic.w	r3, r3, #7
 8008048:	3308      	adds	r3, #8
 800804a:	9303      	str	r3, [sp, #12]
 800804c:	9b09      	ldr	r3, [sp, #36]	; 0x24
 800804e:	444b      	add	r3, r9
 8008050:	9309      	str	r3, [sp, #36]	; 0x24
 8008052:	e750      	b.n	8007ef6 <_vfiprintf_r+0x42>
 8008054:	fb05 3202 	mla	r2, r5, r2, r3
 8008058:	2001      	movs	r0, #1
 800805a:	4688      	mov	r8, r1
 800805c:	e78a      	b.n	8007f74 <_vfiprintf_r+0xc0>
 800805e:	2300      	movs	r3, #0
 8008060:	250a      	movs	r5, #10
 8008062:	4619      	mov	r1, r3
 8008064:	f108 0801 	add.w	r8, r8, #1
 8008068:	9305      	str	r3, [sp, #20]
 800806a:	4640      	mov	r0, r8
 800806c:	f810 2b01 	ldrb.w	r2, [r0], #1
 8008070:	3a30      	subs	r2, #48	; 0x30
 8008072:	2a09      	cmp	r2, #9
 8008074:	d903      	bls.n	800807e <_vfiprintf_r+0x1ca>
 8008076:	2b00      	cmp	r3, #0
 8008078:	d0c3      	beq.n	8008002 <_vfiprintf_r+0x14e>
 800807a:	9105      	str	r1, [sp, #20]
 800807c:	e7c1      	b.n	8008002 <_vfiprintf_r+0x14e>
 800807e:	fb05 2101 	mla	r1, r5, r1, r2
 8008082:	2301      	movs	r3, #1
 8008084:	4680      	mov	r8, r0
 8008086:	e7f0      	b.n	800806a <_vfiprintf_r+0x1b6>
 8008088:	ab03      	add	r3, sp, #12
 800808a:	9300      	str	r3, [sp, #0]
 800808c:	4622      	mov	r2, r4
 800808e:	4b13      	ldr	r3, [pc, #76]	; (80080dc <_vfiprintf_r+0x228>)
 8008090:	a904      	add	r1, sp, #16
 8008092:	4630      	mov	r0, r6
 8008094:	f7fd fd54 	bl	8005b40 <_printf_float>
 8008098:	f1b0 3fff 	cmp.w	r0, #4294967295
 800809c:	4681      	mov	r9, r0
 800809e:	d1d5      	bne.n	800804c <_vfiprintf_r+0x198>
 80080a0:	89a3      	ldrh	r3, [r4, #12]
 80080a2:	065b      	lsls	r3, r3, #25
 80080a4:	f53f af7e 	bmi.w	8007fa4 <_vfiprintf_r+0xf0>
 80080a8:	9809      	ldr	r0, [sp, #36]	; 0x24
 80080aa:	e77d      	b.n	8007fa8 <_vfiprintf_r+0xf4>
 80080ac:	ab03      	add	r3, sp, #12
 80080ae:	9300      	str	r3, [sp, #0]
 80080b0:	4622      	mov	r2, r4
 80080b2:	4b0a      	ldr	r3, [pc, #40]	; (80080dc <_vfiprintf_r+0x228>)
 80080b4:	a904      	add	r1, sp, #16
 80080b6:	4630      	mov	r0, r6
 80080b8:	f7fd ffee 	bl	8006098 <_printf_i>
 80080bc:	e7ec      	b.n	8008098 <_vfiprintf_r+0x1e4>
 80080be:	bf00      	nop
 80080c0:	08008660 	.word	0x08008660
 80080c4:	0800879c 	.word	0x0800879c
 80080c8:	08008680 	.word	0x08008680
 80080cc:	08008640 	.word	0x08008640
 80080d0:	080087a2 	.word	0x080087a2
 80080d4:	080087a6 	.word	0x080087a6
 80080d8:	08005b41 	.word	0x08005b41
 80080dc:	08007e8f 	.word	0x08007e8f

080080e0 <_sbrk_r>:
 80080e0:	b538      	push	{r3, r4, r5, lr}
 80080e2:	2300      	movs	r3, #0
 80080e4:	4c05      	ldr	r4, [pc, #20]	; (80080fc <_sbrk_r+0x1c>)
 80080e6:	4605      	mov	r5, r0
 80080e8:	4608      	mov	r0, r1
 80080ea:	6023      	str	r3, [r4, #0]
 80080ec:	f7fd fbda 	bl	80058a4 <_sbrk>
 80080f0:	1c43      	adds	r3, r0, #1
 80080f2:	d102      	bne.n	80080fa <_sbrk_r+0x1a>
 80080f4:	6823      	ldr	r3, [r4, #0]
 80080f6:	b103      	cbz	r3, 80080fa <_sbrk_r+0x1a>
 80080f8:	602b      	str	r3, [r5, #0]
 80080fa:	bd38      	pop	{r3, r4, r5, pc}
 80080fc:	200008e4 	.word	0x200008e4

08008100 <__sread>:
 8008100:	b510      	push	{r4, lr}
 8008102:	460c      	mov	r4, r1
 8008104:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 8008108:	f000 f8a8 	bl	800825c <_read_r>
 800810c:	2800      	cmp	r0, #0
 800810e:	bfab      	itete	ge
 8008110:	6d63      	ldrge	r3, [r4, #84]	; 0x54
 8008112:	89a3      	ldrhlt	r3, [r4, #12]
 8008114:	181b      	addge	r3, r3, r0
 8008116:	f423 5380 	biclt.w	r3, r3, #4096	; 0x1000
 800811a:	bfac      	ite	ge
 800811c:	6563      	strge	r3, [r4, #84]	; 0x54
 800811e:	81a3      	strhlt	r3, [r4, #12]
 8008120:	bd10      	pop	{r4, pc}

08008122 <__swrite>:
 8008122:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
 8008126:	461f      	mov	r7, r3
 8008128:	898b      	ldrh	r3, [r1, #12]
 800812a:	4605      	mov	r5, r0
 800812c:	05db      	lsls	r3, r3, #23
 800812e:	460c      	mov	r4, r1
 8008130:	4616      	mov	r6, r2
 8008132:	d505      	bpl.n	8008140 <__swrite+0x1e>
 8008134:	2302      	movs	r3, #2
 8008136:	2200      	movs	r2, #0
 8008138:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 800813c:	f000 f868 	bl	8008210 <_lseek_r>
 8008140:	89a3      	ldrh	r3, [r4, #12]
 8008142:	4632      	mov	r2, r6
 8008144:	f423 5380 	bic.w	r3, r3, #4096	; 0x1000
 8008148:	81a3      	strh	r3, [r4, #12]
 800814a:	f9b4 100e 	ldrsh.w	r1, [r4, #14]
 800814e:	463b      	mov	r3, r7
 8008150:	4628      	mov	r0, r5
 8008152:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
 8008156:	f000 b817 	b.w	8008188 <_write_r>

0800815a <__sseek>:
 800815a:	b510      	push	{r4, lr}
 800815c:	460c      	mov	r4, r1
 800815e:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 8008162:	f000 f855 	bl	8008210 <_lseek_r>
 8008166:	1c43      	adds	r3, r0, #1
 8008168:	89a3      	ldrh	r3, [r4, #12]
 800816a:	bf15      	itete	ne
 800816c:	6560      	strne	r0, [r4, #84]	; 0x54
 800816e:	f423 5380 	biceq.w	r3, r3, #4096	; 0x1000
 8008172:	f443 5380 	orrne.w	r3, r3, #4096	; 0x1000
 8008176:	81a3      	strheq	r3, [r4, #12]
 8008178:	bf18      	it	ne
 800817a:	81a3      	strhne	r3, [r4, #12]
 800817c:	bd10      	pop	{r4, pc}

0800817e <__sclose>:
 800817e:	f9b1 100e 	ldrsh.w	r1, [r1, #14]
 8008182:	f000 b813 	b.w	80081ac <_close_r>
	...

08008188 <_write_r>:
 8008188:	b538      	push	{r3, r4, r5, lr}
 800818a:	4605      	mov	r5, r0
 800818c:	4608      	mov	r0, r1
 800818e:	4611      	mov	r1, r2
 8008190:	2200      	movs	r2, #0
 8008192:	4c05      	ldr	r4, [pc, #20]	; (80081a8 <_write_r+0x20>)
 8008194:	6022      	str	r2, [r4, #0]
 8008196:	461a      	mov	r2, r3
 8008198:	f7fc fd90 	bl	8004cbc <_write>
 800819c:	1c43      	adds	r3, r0, #1
 800819e:	d102      	bne.n	80081a6 <_write_r+0x1e>
 80081a0:	6823      	ldr	r3, [r4, #0]
 80081a2:	b103      	cbz	r3, 80081a6 <_write_r+0x1e>
 80081a4:	602b      	str	r3, [r5, #0]
 80081a6:	bd38      	pop	{r3, r4, r5, pc}
 80081a8:	200008e4 	.word	0x200008e4

080081ac <_close_r>:
 80081ac:	b538      	push	{r3, r4, r5, lr}
 80081ae:	2300      	movs	r3, #0
 80081b0:	4c05      	ldr	r4, [pc, #20]	; (80081c8 <_close_r+0x1c>)
 80081b2:	4605      	mov	r5, r0
 80081b4:	4608      	mov	r0, r1
 80081b6:	6023      	str	r3, [r4, #0]
 80081b8:	f7fd fb43 	bl	8005842 <_close>
 80081bc:	1c43      	adds	r3, r0, #1
 80081be:	d102      	bne.n	80081c6 <_close_r+0x1a>
 80081c0:	6823      	ldr	r3, [r4, #0]
 80081c2:	b103      	cbz	r3, 80081c6 <_close_r+0x1a>
 80081c4:	602b      	str	r3, [r5, #0]
 80081c6:	bd38      	pop	{r3, r4, r5, pc}
 80081c8:	200008e4 	.word	0x200008e4

080081cc <_fstat_r>:
 80081cc:	b538      	push	{r3, r4, r5, lr}
 80081ce:	2300      	movs	r3, #0
 80081d0:	4c06      	ldr	r4, [pc, #24]	; (80081ec <_fstat_r+0x20>)
 80081d2:	4605      	mov	r5, r0
 80081d4:	4608      	mov	r0, r1
 80081d6:	4611      	mov	r1, r2
 80081d8:	6023      	str	r3, [r4, #0]
 80081da:	f7fd fb3d 	bl	8005858 <_fstat>
 80081de:	1c43      	adds	r3, r0, #1
 80081e0:	d102      	bne.n	80081e8 <_fstat_r+0x1c>
 80081e2:	6823      	ldr	r3, [r4, #0]
 80081e4:	b103      	cbz	r3, 80081e8 <_fstat_r+0x1c>
 80081e6:	602b      	str	r3, [r5, #0]
 80081e8:	bd38      	pop	{r3, r4, r5, pc}
 80081ea:	bf00      	nop
 80081ec:	200008e4 	.word	0x200008e4

080081f0 <_isatty_r>:
 80081f0:	b538      	push	{r3, r4, r5, lr}
 80081f2:	2300      	movs	r3, #0
 80081f4:	4c05      	ldr	r4, [pc, #20]	; (800820c <_isatty_r+0x1c>)
 80081f6:	4605      	mov	r5, r0
 80081f8:	4608      	mov	r0, r1
 80081fa:	6023      	str	r3, [r4, #0]
 80081fc:	f7fd fb3b 	bl	8005876 <_isatty>
 8008200:	1c43      	adds	r3, r0, #1
 8008202:	d102      	bne.n	800820a <_isatty_r+0x1a>
 8008204:	6823      	ldr	r3, [r4, #0]
 8008206:	b103      	cbz	r3, 800820a <_isatty_r+0x1a>
 8008208:	602b      	str	r3, [r5, #0]
 800820a:	bd38      	pop	{r3, r4, r5, pc}
 800820c:	200008e4 	.word	0x200008e4

08008210 <_lseek_r>:
 8008210:	b538      	push	{r3, r4, r5, lr}
 8008212:	4605      	mov	r5, r0
 8008214:	4608      	mov	r0, r1
 8008216:	4611      	mov	r1, r2
 8008218:	2200      	movs	r2, #0
 800821a:	4c05      	ldr	r4, [pc, #20]	; (8008230 <_lseek_r+0x20>)
 800821c:	6022      	str	r2, [r4, #0]
 800821e:	461a      	mov	r2, r3
 8008220:	f7fd fb33 	bl	800588a <_lseek>
 8008224:	1c43      	adds	r3, r0, #1
 8008226:	d102      	bne.n	800822e <_lseek_r+0x1e>
 8008228:	6823      	ldr	r3, [r4, #0]
 800822a:	b103      	cbz	r3, 800822e <_lseek_r+0x1e>
 800822c:	602b      	str	r3, [r5, #0]
 800822e:	bd38      	pop	{r3, r4, r5, pc}
 8008230:	200008e4 	.word	0x200008e4

08008234 <__ascii_mbtowc>:
 8008234:	b082      	sub	sp, #8
 8008236:	b901      	cbnz	r1, 800823a <__ascii_mbtowc+0x6>
 8008238:	a901      	add	r1, sp, #4
 800823a:	b142      	cbz	r2, 800824e <__ascii_mbtowc+0x1a>
 800823c:	b14b      	cbz	r3, 8008252 <__ascii_mbtowc+0x1e>
 800823e:	7813      	ldrb	r3, [r2, #0]
 8008240:	600b      	str	r3, [r1, #0]
 8008242:	7812      	ldrb	r2, [r2, #0]
 8008244:	1c10      	adds	r0, r2, #0
 8008246:	bf18      	it	ne
 8008248:	2001      	movne	r0, #1
 800824a:	b002      	add	sp, #8
 800824c:	4770      	bx	lr
 800824e:	4610      	mov	r0, r2
 8008250:	e7fb      	b.n	800824a <__ascii_mbtowc+0x16>
 8008252:	f06f 0001 	mvn.w	r0, #1
 8008256:	e7f8      	b.n	800824a <__ascii_mbtowc+0x16>

08008258 <__malloc_lock>:
 8008258:	4770      	bx	lr

0800825a <__malloc_unlock>:
 800825a:	4770      	bx	lr

0800825c <_read_r>:
 800825c:	b538      	push	{r3, r4, r5, lr}
 800825e:	4605      	mov	r5, r0
 8008260:	4608      	mov	r0, r1
 8008262:	4611      	mov	r1, r2
 8008264:	2200      	movs	r2, #0
 8008266:	4c05      	ldr	r4, [pc, #20]	; (800827c <_read_r+0x20>)
 8008268:	6022      	str	r2, [r4, #0]
 800826a:	461a      	mov	r2, r3
 800826c:	f7fd facc 	bl	8005808 <_read>
 8008270:	1c43      	adds	r3, r0, #1
 8008272:	d102      	bne.n	800827a <_read_r+0x1e>
 8008274:	6823      	ldr	r3, [r4, #0]
 8008276:	b103      	cbz	r3, 800827a <_read_r+0x1e>
 8008278:	602b      	str	r3, [r5, #0]
 800827a:	bd38      	pop	{r3, r4, r5, pc}
 800827c:	200008e4 	.word	0x200008e4

08008280 <__ascii_wctomb>:
 8008280:	b149      	cbz	r1, 8008296 <__ascii_wctomb+0x16>
 8008282:	2aff      	cmp	r2, #255	; 0xff
 8008284:	bf8b      	itete	hi
 8008286:	238a      	movhi	r3, #138	; 0x8a
 8008288:	700a      	strbls	r2, [r1, #0]
 800828a:	6003      	strhi	r3, [r0, #0]
 800828c:	2001      	movls	r0, #1
 800828e:	bf88      	it	hi
 8008290:	f04f 30ff 	movhi.w	r0, #4294967295
 8008294:	4770      	bx	lr
 8008296:	4608      	mov	r0, r1
 8008298:	4770      	bx	lr
	...

0800829c <_init>:
 800829c:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 800829e:	bf00      	nop
 80082a0:	bcf8      	pop	{r3, r4, r5, r6, r7}
 80082a2:	bc08      	pop	{r3}
 80082a4:	469e      	mov	lr, r3
 80082a6:	4770      	bx	lr

080082a8 <_fini>:
 80082a8:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 80082aa:	bf00      	nop
 80082ac:	bcf8      	pop	{r3, r4, r5, r6, r7}
 80082ae:	bc08      	pop	{r3}
 80082b0:	469e      	mov	lr, r3
 80082b2:	4770      	bx	lr