Nesslab_200M_System.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000001d0 08000000 08000000 00010000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 0000861c 080001d0 080001d0 000101d0 2**3 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000680 080087f0 080087f0 000187f0 2**3 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 08008e70 08008e70 000201dc 2**0 CONTENTS 4 .ARM 00000000 08008e70 08008e70 000201dc 2**0 CONTENTS 5 .preinit_array 00000000 08008e70 08008e70 000201dc 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 08008e70 08008e70 00018e70 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .fini_array 00000004 08008e74 08008e74 00018e74 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .data 000001dc 20000000 08008e78 00020000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 000009b8 200001e0 08009054 000201e0 2**3 ALLOC 10 ._user_heap_stack 00000600 20000b98 08009054 00020b98 2**0 ALLOC 11 .ARM.attributes 00000029 00000000 00000000 000201dc 2**0 CONTENTS, READONLY 12 .debug_info 000147b9 00000000 00000000 00020205 2**0 CONTENTS, READONLY, DEBUGGING 13 .debug_abbrev 0000363e 00000000 00000000 000349be 2**0 CONTENTS, READONLY, DEBUGGING 14 .debug_aranges 00001160 00000000 00000000 00038000 2**3 CONTENTS, READONLY, DEBUGGING 15 .debug_ranges 00000fb8 00000000 00000000 00039160 2**3 CONTENTS, READONLY, DEBUGGING 16 .debug_macro 00010efd 00000000 00000000 0003a118 2**0 CONTENTS, READONLY, DEBUGGING 17 .debug_line 0000f58d 00000000 00000000 0004b015 2**0 CONTENTS, READONLY, DEBUGGING 18 .debug_str 000587b4 00000000 00000000 0005a5a2 2**0 CONTENTS, READONLY, DEBUGGING 19 .comment 0000007b 00000000 00000000 000b2d56 2**0 CONTENTS, READONLY 20 .debug_frame 00005490 00000000 00000000 000b2dd4 2**2 CONTENTS, READONLY, DEBUGGING Disassembly of section .text: 080001d0 <__do_global_dtors_aux>: 80001d0: b510 push {r4, lr} 80001d2: 4c05 ldr r4, [pc, #20] ; (80001e8 <__do_global_dtors_aux+0x18>) 80001d4: 7823 ldrb r3, [r4, #0] 80001d6: b933 cbnz r3, 80001e6 <__do_global_dtors_aux+0x16> 80001d8: 4b04 ldr r3, [pc, #16] ; (80001ec <__do_global_dtors_aux+0x1c>) 80001da: b113 cbz r3, 80001e2 <__do_global_dtors_aux+0x12> 80001dc: 4804 ldr r0, [pc, #16] ; (80001f0 <__do_global_dtors_aux+0x20>) 80001de: f3af 8000 nop.w 80001e2: 2301 movs r3, #1 80001e4: 7023 strb r3, [r4, #0] 80001e6: bd10 pop {r4, pc} 80001e8: 200001e0 .word 0x200001e0 80001ec: 00000000 .word 0x00000000 80001f0: 080087d4 .word 0x080087d4 080001f4 : 80001f4: b508 push {r3, lr} 80001f6: 4b03 ldr r3, [pc, #12] ; (8000204 ) 80001f8: b11b cbz r3, 8000202 80001fa: 4903 ldr r1, [pc, #12] ; (8000208 ) 80001fc: 4803 ldr r0, [pc, #12] ; (800020c ) 80001fe: f3af 8000 nop.w 8000202: bd08 pop {r3, pc} 8000204: 00000000 .word 0x00000000 8000208: 200001e4 .word 0x200001e4 800020c: 080087d4 .word 0x080087d4 08000210 : 8000210: 4603 mov r3, r0 8000212: f813 2b01 ldrb.w r2, [r3], #1 8000216: 2a00 cmp r2, #0 8000218: d1fb bne.n 8000212 800021a: 1a18 subs r0, r3, r0 800021c: 3801 subs r0, #1 800021e: 4770 bx lr 08000220 <__aeabi_drsub>: 8000220: f081 4100 eor.w r1, r1, #2147483648 ; 0x80000000 8000224: e002 b.n 800022c <__adddf3> 8000226: bf00 nop 08000228 <__aeabi_dsub>: 8000228: f083 4300 eor.w r3, r3, #2147483648 ; 0x80000000 0800022c <__adddf3>: 800022c: b530 push {r4, r5, lr} 800022e: ea4f 0441 mov.w r4, r1, lsl #1 8000232: ea4f 0543 mov.w r5, r3, lsl #1 8000236: ea94 0f05 teq r4, r5 800023a: bf08 it eq 800023c: ea90 0f02 teqeq r0, r2 8000240: bf1f itttt ne 8000242: ea54 0c00 orrsne.w ip, r4, r0 8000246: ea55 0c02 orrsne.w ip, r5, r2 800024a: ea7f 5c64 mvnsne.w ip, r4, asr #21 800024e: ea7f 5c65 mvnsne.w ip, r5, asr #21 8000252: f000 80e2 beq.w 800041a <__adddf3+0x1ee> 8000256: ea4f 5454 mov.w r4, r4, lsr #21 800025a: ebd4 5555 rsbs r5, r4, r5, lsr #21 800025e: bfb8 it lt 8000260: 426d neglt r5, r5 8000262: dd0c ble.n 800027e <__adddf3+0x52> 8000264: 442c add r4, r5 8000266: ea80 0202 eor.w r2, r0, r2 800026a: ea81 0303 eor.w r3, r1, r3 800026e: ea82 0000 eor.w r0, r2, r0 8000272: ea83 0101 eor.w r1, r3, r1 8000276: ea80 0202 eor.w r2, r0, r2 800027a: ea81 0303 eor.w r3, r1, r3 800027e: 2d36 cmp r5, #54 ; 0x36 8000280: bf88 it hi 8000282: bd30 pophi {r4, r5, pc} 8000284: f011 4f00 tst.w r1, #2147483648 ; 0x80000000 8000288: ea4f 3101 mov.w r1, r1, lsl #12 800028c: f44f 1c80 mov.w ip, #1048576 ; 0x100000 8000290: ea4c 3111 orr.w r1, ip, r1, lsr #12 8000294: d002 beq.n 800029c <__adddf3+0x70> 8000296: 4240 negs r0, r0 8000298: eb61 0141 sbc.w r1, r1, r1, lsl #1 800029c: f013 4f00 tst.w r3, #2147483648 ; 0x80000000 80002a0: ea4f 3303 mov.w r3, r3, lsl #12 80002a4: ea4c 3313 orr.w r3, ip, r3, lsr #12 80002a8: d002 beq.n 80002b0 <__adddf3+0x84> 80002aa: 4252 negs r2, r2 80002ac: eb63 0343 sbc.w r3, r3, r3, lsl #1 80002b0: ea94 0f05 teq r4, r5 80002b4: f000 80a7 beq.w 8000406 <__adddf3+0x1da> 80002b8: f1a4 0401 sub.w r4, r4, #1 80002bc: f1d5 0e20 rsbs lr, r5, #32 80002c0: db0d blt.n 80002de <__adddf3+0xb2> 80002c2: fa02 fc0e lsl.w ip, r2, lr 80002c6: fa22 f205 lsr.w r2, r2, r5 80002ca: 1880 adds r0, r0, r2 80002cc: f141 0100 adc.w r1, r1, #0 80002d0: fa03 f20e lsl.w r2, r3, lr 80002d4: 1880 adds r0, r0, r2 80002d6: fa43 f305 asr.w r3, r3, r5 80002da: 4159 adcs r1, r3 80002dc: e00e b.n 80002fc <__adddf3+0xd0> 80002de: f1a5 0520 sub.w r5, r5, #32 80002e2: f10e 0e20 add.w lr, lr, #32 80002e6: 2a01 cmp r2, #1 80002e8: fa03 fc0e lsl.w ip, r3, lr 80002ec: bf28 it cs 80002ee: f04c 0c02 orrcs.w ip, ip, #2 80002f2: fa43 f305 asr.w r3, r3, r5 80002f6: 18c0 adds r0, r0, r3 80002f8: eb51 71e3 adcs.w r1, r1, r3, asr #31 80002fc: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 8000300: d507 bpl.n 8000312 <__adddf3+0xe6> 8000302: f04f 0e00 mov.w lr, #0 8000306: f1dc 0c00 rsbs ip, ip, #0 800030a: eb7e 0000 sbcs.w r0, lr, r0 800030e: eb6e 0101 sbc.w r1, lr, r1 8000312: f5b1 1f80 cmp.w r1, #1048576 ; 0x100000 8000316: d31b bcc.n 8000350 <__adddf3+0x124> 8000318: f5b1 1f00 cmp.w r1, #2097152 ; 0x200000 800031c: d30c bcc.n 8000338 <__adddf3+0x10c> 800031e: 0849 lsrs r1, r1, #1 8000320: ea5f 0030 movs.w r0, r0, rrx 8000324: ea4f 0c3c mov.w ip, ip, rrx 8000328: f104 0401 add.w r4, r4, #1 800032c: ea4f 5244 mov.w r2, r4, lsl #21 8000330: f512 0f80 cmn.w r2, #4194304 ; 0x400000 8000334: f080 809a bcs.w 800046c <__adddf3+0x240> 8000338: f1bc 4f00 cmp.w ip, #2147483648 ; 0x80000000 800033c: bf08 it eq 800033e: ea5f 0c50 movseq.w ip, r0, lsr #1 8000342: f150 0000 adcs.w r0, r0, #0 8000346: eb41 5104 adc.w r1, r1, r4, lsl #20 800034a: ea41 0105 orr.w r1, r1, r5 800034e: bd30 pop {r4, r5, pc} 8000350: ea5f 0c4c movs.w ip, ip, lsl #1 8000354: 4140 adcs r0, r0 8000356: eb41 0101 adc.w r1, r1, r1 800035a: f411 1f80 tst.w r1, #1048576 ; 0x100000 800035e: f1a4 0401 sub.w r4, r4, #1 8000362: d1e9 bne.n 8000338 <__adddf3+0x10c> 8000364: f091 0f00 teq r1, #0 8000368: bf04 itt eq 800036a: 4601 moveq r1, r0 800036c: 2000 moveq r0, #0 800036e: fab1 f381 clz r3, r1 8000372: bf08 it eq 8000374: 3320 addeq r3, #32 8000376: f1a3 030b sub.w r3, r3, #11 800037a: f1b3 0220 subs.w r2, r3, #32 800037e: da0c bge.n 800039a <__adddf3+0x16e> 8000380: 320c adds r2, #12 8000382: dd08 ble.n 8000396 <__adddf3+0x16a> 8000384: f102 0c14 add.w ip, r2, #20 8000388: f1c2 020c rsb r2, r2, #12 800038c: fa01 f00c lsl.w r0, r1, ip 8000390: fa21 f102 lsr.w r1, r1, r2 8000394: e00c b.n 80003b0 <__adddf3+0x184> 8000396: f102 0214 add.w r2, r2, #20 800039a: bfd8 it le 800039c: f1c2 0c20 rsble ip, r2, #32 80003a0: fa01 f102 lsl.w r1, r1, r2 80003a4: fa20 fc0c lsr.w ip, r0, ip 80003a8: bfdc itt le 80003aa: ea41 010c orrle.w r1, r1, ip 80003ae: 4090 lslle r0, r2 80003b0: 1ae4 subs r4, r4, r3 80003b2: bfa2 ittt ge 80003b4: eb01 5104 addge.w r1, r1, r4, lsl #20 80003b8: 4329 orrge r1, r5 80003ba: bd30 popge {r4, r5, pc} 80003bc: ea6f 0404 mvn.w r4, r4 80003c0: 3c1f subs r4, #31 80003c2: da1c bge.n 80003fe <__adddf3+0x1d2> 80003c4: 340c adds r4, #12 80003c6: dc0e bgt.n 80003e6 <__adddf3+0x1ba> 80003c8: f104 0414 add.w r4, r4, #20 80003cc: f1c4 0220 rsb r2, r4, #32 80003d0: fa20 f004 lsr.w r0, r0, r4 80003d4: fa01 f302 lsl.w r3, r1, r2 80003d8: ea40 0003 orr.w r0, r0, r3 80003dc: fa21 f304 lsr.w r3, r1, r4 80003e0: ea45 0103 orr.w r1, r5, r3 80003e4: bd30 pop {r4, r5, pc} 80003e6: f1c4 040c rsb r4, r4, #12 80003ea: f1c4 0220 rsb r2, r4, #32 80003ee: fa20 f002 lsr.w r0, r0, r2 80003f2: fa01 f304 lsl.w r3, r1, r4 80003f6: ea40 0003 orr.w r0, r0, r3 80003fa: 4629 mov r1, r5 80003fc: bd30 pop {r4, r5, pc} 80003fe: fa21 f004 lsr.w r0, r1, r4 8000402: 4629 mov r1, r5 8000404: bd30 pop {r4, r5, pc} 8000406: f094 0f00 teq r4, #0 800040a: f483 1380 eor.w r3, r3, #1048576 ; 0x100000 800040e: bf06 itte eq 8000410: f481 1180 eoreq.w r1, r1, #1048576 ; 0x100000 8000414: 3401 addeq r4, #1 8000416: 3d01 subne r5, #1 8000418: e74e b.n 80002b8 <__adddf3+0x8c> 800041a: ea7f 5c64 mvns.w ip, r4, asr #21 800041e: bf18 it ne 8000420: ea7f 5c65 mvnsne.w ip, r5, asr #21 8000424: d029 beq.n 800047a <__adddf3+0x24e> 8000426: ea94 0f05 teq r4, r5 800042a: bf08 it eq 800042c: ea90 0f02 teqeq r0, r2 8000430: d005 beq.n 800043e <__adddf3+0x212> 8000432: ea54 0c00 orrs.w ip, r4, r0 8000436: bf04 itt eq 8000438: 4619 moveq r1, r3 800043a: 4610 moveq r0, r2 800043c: bd30 pop {r4, r5, pc} 800043e: ea91 0f03 teq r1, r3 8000442: bf1e ittt ne 8000444: 2100 movne r1, #0 8000446: 2000 movne r0, #0 8000448: bd30 popne {r4, r5, pc} 800044a: ea5f 5c54 movs.w ip, r4, lsr #21 800044e: d105 bne.n 800045c <__adddf3+0x230> 8000450: 0040 lsls r0, r0, #1 8000452: 4149 adcs r1, r1 8000454: bf28 it cs 8000456: f041 4100 orrcs.w r1, r1, #2147483648 ; 0x80000000 800045a: bd30 pop {r4, r5, pc} 800045c: f514 0480 adds.w r4, r4, #4194304 ; 0x400000 8000460: bf3c itt cc 8000462: f501 1180 addcc.w r1, r1, #1048576 ; 0x100000 8000466: bd30 popcc {r4, r5, pc} 8000468: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 800046c: f045 41fe orr.w r1, r5, #2130706432 ; 0x7f000000 8000470: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000 8000474: f04f 0000 mov.w r0, #0 8000478: bd30 pop {r4, r5, pc} 800047a: ea7f 5c64 mvns.w ip, r4, asr #21 800047e: bf1a itte ne 8000480: 4619 movne r1, r3 8000482: 4610 movne r0, r2 8000484: ea7f 5c65 mvnseq.w ip, r5, asr #21 8000488: bf1c itt ne 800048a: 460b movne r3, r1 800048c: 4602 movne r2, r0 800048e: ea50 3401 orrs.w r4, r0, r1, lsl #12 8000492: bf06 itte eq 8000494: ea52 3503 orrseq.w r5, r2, r3, lsl #12 8000498: ea91 0f03 teqeq r1, r3 800049c: f441 2100 orrne.w r1, r1, #524288 ; 0x80000 80004a0: bd30 pop {r4, r5, pc} 80004a2: bf00 nop 080004a4 <__aeabi_ui2d>: 80004a4: f090 0f00 teq r0, #0 80004a8: bf04 itt eq 80004aa: 2100 moveq r1, #0 80004ac: 4770 bxeq lr 80004ae: b530 push {r4, r5, lr} 80004b0: f44f 6480 mov.w r4, #1024 ; 0x400 80004b4: f104 0432 add.w r4, r4, #50 ; 0x32 80004b8: f04f 0500 mov.w r5, #0 80004bc: f04f 0100 mov.w r1, #0 80004c0: e750 b.n 8000364 <__adddf3+0x138> 80004c2: bf00 nop 080004c4 <__aeabi_i2d>: 80004c4: f090 0f00 teq r0, #0 80004c8: bf04 itt eq 80004ca: 2100 moveq r1, #0 80004cc: 4770 bxeq lr 80004ce: b530 push {r4, r5, lr} 80004d0: f44f 6480 mov.w r4, #1024 ; 0x400 80004d4: f104 0432 add.w r4, r4, #50 ; 0x32 80004d8: f010 4500 ands.w r5, r0, #2147483648 ; 0x80000000 80004dc: bf48 it mi 80004de: 4240 negmi r0, r0 80004e0: f04f 0100 mov.w r1, #0 80004e4: e73e b.n 8000364 <__adddf3+0x138> 80004e6: bf00 nop 080004e8 <__aeabi_f2d>: 80004e8: 0042 lsls r2, r0, #1 80004ea: ea4f 01e2 mov.w r1, r2, asr #3 80004ee: ea4f 0131 mov.w r1, r1, rrx 80004f2: ea4f 7002 mov.w r0, r2, lsl #28 80004f6: bf1f itttt ne 80004f8: f012 437f andsne.w r3, r2, #4278190080 ; 0xff000000 80004fc: f093 4f7f teqne r3, #4278190080 ; 0xff000000 8000500: f081 5160 eorne.w r1, r1, #939524096 ; 0x38000000 8000504: 4770 bxne lr 8000506: f032 427f bics.w r2, r2, #4278190080 ; 0xff000000 800050a: bf08 it eq 800050c: 4770 bxeq lr 800050e: f093 4f7f teq r3, #4278190080 ; 0xff000000 8000512: bf04 itt eq 8000514: f441 2100 orreq.w r1, r1, #524288 ; 0x80000 8000518: 4770 bxeq lr 800051a: b530 push {r4, r5, lr} 800051c: f44f 7460 mov.w r4, #896 ; 0x380 8000520: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 8000524: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000 8000528: e71c b.n 8000364 <__adddf3+0x138> 800052a: bf00 nop 0800052c <__aeabi_ul2d>: 800052c: ea50 0201 orrs.w r2, r0, r1 8000530: bf08 it eq 8000532: 4770 bxeq lr 8000534: b530 push {r4, r5, lr} 8000536: f04f 0500 mov.w r5, #0 800053a: e00a b.n 8000552 <__aeabi_l2d+0x16> 0800053c <__aeabi_l2d>: 800053c: ea50 0201 orrs.w r2, r0, r1 8000540: bf08 it eq 8000542: 4770 bxeq lr 8000544: b530 push {r4, r5, lr} 8000546: f011 4500 ands.w r5, r1, #2147483648 ; 0x80000000 800054a: d502 bpl.n 8000552 <__aeabi_l2d+0x16> 800054c: 4240 negs r0, r0 800054e: eb61 0141 sbc.w r1, r1, r1, lsl #1 8000552: f44f 6480 mov.w r4, #1024 ; 0x400 8000556: f104 0432 add.w r4, r4, #50 ; 0x32 800055a: ea5f 5c91 movs.w ip, r1, lsr #22 800055e: f43f aed8 beq.w 8000312 <__adddf3+0xe6> 8000562: f04f 0203 mov.w r2, #3 8000566: ea5f 0cdc movs.w ip, ip, lsr #3 800056a: bf18 it ne 800056c: 3203 addne r2, #3 800056e: ea5f 0cdc movs.w ip, ip, lsr #3 8000572: bf18 it ne 8000574: 3203 addne r2, #3 8000576: eb02 02dc add.w r2, r2, ip, lsr #3 800057a: f1c2 0320 rsb r3, r2, #32 800057e: fa00 fc03 lsl.w ip, r0, r3 8000582: fa20 f002 lsr.w r0, r0, r2 8000586: fa01 fe03 lsl.w lr, r1, r3 800058a: ea40 000e orr.w r0, r0, lr 800058e: fa21 f102 lsr.w r1, r1, r2 8000592: 4414 add r4, r2 8000594: e6bd b.n 8000312 <__adddf3+0xe6> 8000596: bf00 nop 08000598 <__aeabi_dmul>: 8000598: b570 push {r4, r5, r6, lr} 800059a: f04f 0cff mov.w ip, #255 ; 0xff 800059e: f44c 6ce0 orr.w ip, ip, #1792 ; 0x700 80005a2: ea1c 5411 ands.w r4, ip, r1, lsr #20 80005a6: bf1d ittte ne 80005a8: ea1c 5513 andsne.w r5, ip, r3, lsr #20 80005ac: ea94 0f0c teqne r4, ip 80005b0: ea95 0f0c teqne r5, ip 80005b4: f000 f8de bleq 8000774 <__aeabi_dmul+0x1dc> 80005b8: 442c add r4, r5 80005ba: ea81 0603 eor.w r6, r1, r3 80005be: ea21 514c bic.w r1, r1, ip, lsl #21 80005c2: ea23 534c bic.w r3, r3, ip, lsl #21 80005c6: ea50 3501 orrs.w r5, r0, r1, lsl #12 80005ca: bf18 it ne 80005cc: ea52 3503 orrsne.w r5, r2, r3, lsl #12 80005d0: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 80005d4: f443 1380 orr.w r3, r3, #1048576 ; 0x100000 80005d8: d038 beq.n 800064c <__aeabi_dmul+0xb4> 80005da: fba0 ce02 umull ip, lr, r0, r2 80005de: f04f 0500 mov.w r5, #0 80005e2: fbe1 e502 umlal lr, r5, r1, r2 80005e6: f006 4200 and.w r2, r6, #2147483648 ; 0x80000000 80005ea: fbe0 e503 umlal lr, r5, r0, r3 80005ee: f04f 0600 mov.w r6, #0 80005f2: fbe1 5603 umlal r5, r6, r1, r3 80005f6: f09c 0f00 teq ip, #0 80005fa: bf18 it ne 80005fc: f04e 0e01 orrne.w lr, lr, #1 8000600: f1a4 04ff sub.w r4, r4, #255 ; 0xff 8000604: f5b6 7f00 cmp.w r6, #512 ; 0x200 8000608: f564 7440 sbc.w r4, r4, #768 ; 0x300 800060c: d204 bcs.n 8000618 <__aeabi_dmul+0x80> 800060e: ea5f 0e4e movs.w lr, lr, lsl #1 8000612: 416d adcs r5, r5 8000614: eb46 0606 adc.w r6, r6, r6 8000618: ea42 21c6 orr.w r1, r2, r6, lsl #11 800061c: ea41 5155 orr.w r1, r1, r5, lsr #21 8000620: ea4f 20c5 mov.w r0, r5, lsl #11 8000624: ea40 505e orr.w r0, r0, lr, lsr #21 8000628: ea4f 2ece mov.w lr, lr, lsl #11 800062c: f1b4 0cfd subs.w ip, r4, #253 ; 0xfd 8000630: bf88 it hi 8000632: f5bc 6fe0 cmphi.w ip, #1792 ; 0x700 8000636: d81e bhi.n 8000676 <__aeabi_dmul+0xde> 8000638: f1be 4f00 cmp.w lr, #2147483648 ; 0x80000000 800063c: bf08 it eq 800063e: ea5f 0e50 movseq.w lr, r0, lsr #1 8000642: f150 0000 adcs.w r0, r0, #0 8000646: eb41 5104 adc.w r1, r1, r4, lsl #20 800064a: bd70 pop {r4, r5, r6, pc} 800064c: f006 4600 and.w r6, r6, #2147483648 ; 0x80000000 8000650: ea46 0101 orr.w r1, r6, r1 8000654: ea40 0002 orr.w r0, r0, r2 8000658: ea81 0103 eor.w r1, r1, r3 800065c: ebb4 045c subs.w r4, r4, ip, lsr #1 8000660: bfc2 ittt gt 8000662: ebd4 050c rsbsgt r5, r4, ip 8000666: ea41 5104 orrgt.w r1, r1, r4, lsl #20 800066a: bd70 popgt {r4, r5, r6, pc} 800066c: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 8000670: f04f 0e00 mov.w lr, #0 8000674: 3c01 subs r4, #1 8000676: f300 80ab bgt.w 80007d0 <__aeabi_dmul+0x238> 800067a: f114 0f36 cmn.w r4, #54 ; 0x36 800067e: bfde ittt le 8000680: 2000 movle r0, #0 8000682: f001 4100 andle.w r1, r1, #2147483648 ; 0x80000000 8000686: bd70 pople {r4, r5, r6, pc} 8000688: f1c4 0400 rsb r4, r4, #0 800068c: 3c20 subs r4, #32 800068e: da35 bge.n 80006fc <__aeabi_dmul+0x164> 8000690: 340c adds r4, #12 8000692: dc1b bgt.n 80006cc <__aeabi_dmul+0x134> 8000694: f104 0414 add.w r4, r4, #20 8000698: f1c4 0520 rsb r5, r4, #32 800069c: fa00 f305 lsl.w r3, r0, r5 80006a0: fa20 f004 lsr.w r0, r0, r4 80006a4: fa01 f205 lsl.w r2, r1, r5 80006a8: ea40 0002 orr.w r0, r0, r2 80006ac: f001 4200 and.w r2, r1, #2147483648 ; 0x80000000 80006b0: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000 80006b4: eb10 70d3 adds.w r0, r0, r3, lsr #31 80006b8: fa21 f604 lsr.w r6, r1, r4 80006bc: eb42 0106 adc.w r1, r2, r6 80006c0: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 80006c4: bf08 it eq 80006c6: ea20 70d3 biceq.w r0, r0, r3, lsr #31 80006ca: bd70 pop {r4, r5, r6, pc} 80006cc: f1c4 040c rsb r4, r4, #12 80006d0: f1c4 0520 rsb r5, r4, #32 80006d4: fa00 f304 lsl.w r3, r0, r4 80006d8: fa20 f005 lsr.w r0, r0, r5 80006dc: fa01 f204 lsl.w r2, r1, r4 80006e0: ea40 0002 orr.w r0, r0, r2 80006e4: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 80006e8: eb10 70d3 adds.w r0, r0, r3, lsr #31 80006ec: f141 0100 adc.w r1, r1, #0 80006f0: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 80006f4: bf08 it eq 80006f6: ea20 70d3 biceq.w r0, r0, r3, lsr #31 80006fa: bd70 pop {r4, r5, r6, pc} 80006fc: f1c4 0520 rsb r5, r4, #32 8000700: fa00 f205 lsl.w r2, r0, r5 8000704: ea4e 0e02 orr.w lr, lr, r2 8000708: fa20 f304 lsr.w r3, r0, r4 800070c: fa01 f205 lsl.w r2, r1, r5 8000710: ea43 0302 orr.w r3, r3, r2 8000714: fa21 f004 lsr.w r0, r1, r4 8000718: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 800071c: fa21 f204 lsr.w r2, r1, r4 8000720: ea20 0002 bic.w r0, r0, r2 8000724: eb00 70d3 add.w r0, r0, r3, lsr #31 8000728: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 800072c: bf08 it eq 800072e: ea20 70d3 biceq.w r0, r0, r3, lsr #31 8000732: bd70 pop {r4, r5, r6, pc} 8000734: f094 0f00 teq r4, #0 8000738: d10f bne.n 800075a <__aeabi_dmul+0x1c2> 800073a: f001 4600 and.w r6, r1, #2147483648 ; 0x80000000 800073e: 0040 lsls r0, r0, #1 8000740: eb41 0101 adc.w r1, r1, r1 8000744: f411 1f80 tst.w r1, #1048576 ; 0x100000 8000748: bf08 it eq 800074a: 3c01 subeq r4, #1 800074c: d0f7 beq.n 800073e <__aeabi_dmul+0x1a6> 800074e: ea41 0106 orr.w r1, r1, r6 8000752: f095 0f00 teq r5, #0 8000756: bf18 it ne 8000758: 4770 bxne lr 800075a: f003 4600 and.w r6, r3, #2147483648 ; 0x80000000 800075e: 0052 lsls r2, r2, #1 8000760: eb43 0303 adc.w r3, r3, r3 8000764: f413 1f80 tst.w r3, #1048576 ; 0x100000 8000768: bf08 it eq 800076a: 3d01 subeq r5, #1 800076c: d0f7 beq.n 800075e <__aeabi_dmul+0x1c6> 800076e: ea43 0306 orr.w r3, r3, r6 8000772: 4770 bx lr 8000774: ea94 0f0c teq r4, ip 8000778: ea0c 5513 and.w r5, ip, r3, lsr #20 800077c: bf18 it ne 800077e: ea95 0f0c teqne r5, ip 8000782: d00c beq.n 800079e <__aeabi_dmul+0x206> 8000784: ea50 0641 orrs.w r6, r0, r1, lsl #1 8000788: bf18 it ne 800078a: ea52 0643 orrsne.w r6, r2, r3, lsl #1 800078e: d1d1 bne.n 8000734 <__aeabi_dmul+0x19c> 8000790: ea81 0103 eor.w r1, r1, r3 8000794: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 8000798: f04f 0000 mov.w r0, #0 800079c: bd70 pop {r4, r5, r6, pc} 800079e: ea50 0641 orrs.w r6, r0, r1, lsl #1 80007a2: bf06 itte eq 80007a4: 4610 moveq r0, r2 80007a6: 4619 moveq r1, r3 80007a8: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80007ac: d019 beq.n 80007e2 <__aeabi_dmul+0x24a> 80007ae: ea94 0f0c teq r4, ip 80007b2: d102 bne.n 80007ba <__aeabi_dmul+0x222> 80007b4: ea50 3601 orrs.w r6, r0, r1, lsl #12 80007b8: d113 bne.n 80007e2 <__aeabi_dmul+0x24a> 80007ba: ea95 0f0c teq r5, ip 80007be: d105 bne.n 80007cc <__aeabi_dmul+0x234> 80007c0: ea52 3603 orrs.w r6, r2, r3, lsl #12 80007c4: bf1c itt ne 80007c6: 4610 movne r0, r2 80007c8: 4619 movne r1, r3 80007ca: d10a bne.n 80007e2 <__aeabi_dmul+0x24a> 80007cc: ea81 0103 eor.w r1, r1, r3 80007d0: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 80007d4: f041 41fe orr.w r1, r1, #2130706432 ; 0x7f000000 80007d8: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000 80007dc: f04f 0000 mov.w r0, #0 80007e0: bd70 pop {r4, r5, r6, pc} 80007e2: f041 41fe orr.w r1, r1, #2130706432 ; 0x7f000000 80007e6: f441 0178 orr.w r1, r1, #16252928 ; 0xf80000 80007ea: bd70 pop {r4, r5, r6, pc} 080007ec <__aeabi_ddiv>: 80007ec: b570 push {r4, r5, r6, lr} 80007ee: f04f 0cff mov.w ip, #255 ; 0xff 80007f2: f44c 6ce0 orr.w ip, ip, #1792 ; 0x700 80007f6: ea1c 5411 ands.w r4, ip, r1, lsr #20 80007fa: bf1d ittte ne 80007fc: ea1c 5513 andsne.w r5, ip, r3, lsr #20 8000800: ea94 0f0c teqne r4, ip 8000804: ea95 0f0c teqne r5, ip 8000808: f000 f8a7 bleq 800095a <__aeabi_ddiv+0x16e> 800080c: eba4 0405 sub.w r4, r4, r5 8000810: ea81 0e03 eor.w lr, r1, r3 8000814: ea52 3503 orrs.w r5, r2, r3, lsl #12 8000818: ea4f 3101 mov.w r1, r1, lsl #12 800081c: f000 8088 beq.w 8000930 <__aeabi_ddiv+0x144> 8000820: ea4f 3303 mov.w r3, r3, lsl #12 8000824: f04f 5580 mov.w r5, #268435456 ; 0x10000000 8000828: ea45 1313 orr.w r3, r5, r3, lsr #4 800082c: ea43 6312 orr.w r3, r3, r2, lsr #24 8000830: ea4f 2202 mov.w r2, r2, lsl #8 8000834: ea45 1511 orr.w r5, r5, r1, lsr #4 8000838: ea45 6510 orr.w r5, r5, r0, lsr #24 800083c: ea4f 2600 mov.w r6, r0, lsl #8 8000840: f00e 4100 and.w r1, lr, #2147483648 ; 0x80000000 8000844: 429d cmp r5, r3 8000846: bf08 it eq 8000848: 4296 cmpeq r6, r2 800084a: f144 04fd adc.w r4, r4, #253 ; 0xfd 800084e: f504 7440 add.w r4, r4, #768 ; 0x300 8000852: d202 bcs.n 800085a <__aeabi_ddiv+0x6e> 8000854: 085b lsrs r3, r3, #1 8000856: ea4f 0232 mov.w r2, r2, rrx 800085a: 1ab6 subs r6, r6, r2 800085c: eb65 0503 sbc.w r5, r5, r3 8000860: 085b lsrs r3, r3, #1 8000862: ea4f 0232 mov.w r2, r2, rrx 8000866: f44f 1080 mov.w r0, #1048576 ; 0x100000 800086a: f44f 2c00 mov.w ip, #524288 ; 0x80000 800086e: ebb6 0e02 subs.w lr, r6, r2 8000872: eb75 0e03 sbcs.w lr, r5, r3 8000876: bf22 ittt cs 8000878: 1ab6 subcs r6, r6, r2 800087a: 4675 movcs r5, lr 800087c: ea40 000c orrcs.w r0, r0, ip 8000880: 085b lsrs r3, r3, #1 8000882: ea4f 0232 mov.w r2, r2, rrx 8000886: ebb6 0e02 subs.w lr, r6, r2 800088a: eb75 0e03 sbcs.w lr, r5, r3 800088e: bf22 ittt cs 8000890: 1ab6 subcs r6, r6, r2 8000892: 4675 movcs r5, lr 8000894: ea40 005c orrcs.w r0, r0, ip, lsr #1 8000898: 085b lsrs r3, r3, #1 800089a: ea4f 0232 mov.w r2, r2, rrx 800089e: ebb6 0e02 subs.w lr, r6, r2 80008a2: eb75 0e03 sbcs.w lr, r5, r3 80008a6: bf22 ittt cs 80008a8: 1ab6 subcs r6, r6, r2 80008aa: 4675 movcs r5, lr 80008ac: ea40 009c orrcs.w r0, r0, ip, lsr #2 80008b0: 085b lsrs r3, r3, #1 80008b2: ea4f 0232 mov.w r2, r2, rrx 80008b6: ebb6 0e02 subs.w lr, r6, r2 80008ba: eb75 0e03 sbcs.w lr, r5, r3 80008be: bf22 ittt cs 80008c0: 1ab6 subcs r6, r6, r2 80008c2: 4675 movcs r5, lr 80008c4: ea40 00dc orrcs.w r0, r0, ip, lsr #3 80008c8: ea55 0e06 orrs.w lr, r5, r6 80008cc: d018 beq.n 8000900 <__aeabi_ddiv+0x114> 80008ce: ea4f 1505 mov.w r5, r5, lsl #4 80008d2: ea45 7516 orr.w r5, r5, r6, lsr #28 80008d6: ea4f 1606 mov.w r6, r6, lsl #4 80008da: ea4f 03c3 mov.w r3, r3, lsl #3 80008de: ea43 7352 orr.w r3, r3, r2, lsr #29 80008e2: ea4f 02c2 mov.w r2, r2, lsl #3 80008e6: ea5f 1c1c movs.w ip, ip, lsr #4 80008ea: d1c0 bne.n 800086e <__aeabi_ddiv+0x82> 80008ec: f411 1f80 tst.w r1, #1048576 ; 0x100000 80008f0: d10b bne.n 800090a <__aeabi_ddiv+0x11e> 80008f2: ea41 0100 orr.w r1, r1, r0 80008f6: f04f 0000 mov.w r0, #0 80008fa: f04f 4c00 mov.w ip, #2147483648 ; 0x80000000 80008fe: e7b6 b.n 800086e <__aeabi_ddiv+0x82> 8000900: f411 1f80 tst.w r1, #1048576 ; 0x100000 8000904: bf04 itt eq 8000906: 4301 orreq r1, r0 8000908: 2000 moveq r0, #0 800090a: f1b4 0cfd subs.w ip, r4, #253 ; 0xfd 800090e: bf88 it hi 8000910: f5bc 6fe0 cmphi.w ip, #1792 ; 0x700 8000914: f63f aeaf bhi.w 8000676 <__aeabi_dmul+0xde> 8000918: ebb5 0c03 subs.w ip, r5, r3 800091c: bf04 itt eq 800091e: ebb6 0c02 subseq.w ip, r6, r2 8000922: ea5f 0c50 movseq.w ip, r0, lsr #1 8000926: f150 0000 adcs.w r0, r0, #0 800092a: eb41 5104 adc.w r1, r1, r4, lsl #20 800092e: bd70 pop {r4, r5, r6, pc} 8000930: f00e 4e00 and.w lr, lr, #2147483648 ; 0x80000000 8000934: ea4e 3111 orr.w r1, lr, r1, lsr #12 8000938: eb14 045c adds.w r4, r4, ip, lsr #1 800093c: bfc2 ittt gt 800093e: ebd4 050c rsbsgt r5, r4, ip 8000942: ea41 5104 orrgt.w r1, r1, r4, lsl #20 8000946: bd70 popgt {r4, r5, r6, pc} 8000948: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 800094c: f04f 0e00 mov.w lr, #0 8000950: 3c01 subs r4, #1 8000952: e690 b.n 8000676 <__aeabi_dmul+0xde> 8000954: ea45 0e06 orr.w lr, r5, r6 8000958: e68d b.n 8000676 <__aeabi_dmul+0xde> 800095a: ea0c 5513 and.w r5, ip, r3, lsr #20 800095e: ea94 0f0c teq r4, ip 8000962: bf08 it eq 8000964: ea95 0f0c teqeq r5, ip 8000968: f43f af3b beq.w 80007e2 <__aeabi_dmul+0x24a> 800096c: ea94 0f0c teq r4, ip 8000970: d10a bne.n 8000988 <__aeabi_ddiv+0x19c> 8000972: ea50 3401 orrs.w r4, r0, r1, lsl #12 8000976: f47f af34 bne.w 80007e2 <__aeabi_dmul+0x24a> 800097a: ea95 0f0c teq r5, ip 800097e: f47f af25 bne.w 80007cc <__aeabi_dmul+0x234> 8000982: 4610 mov r0, r2 8000984: 4619 mov r1, r3 8000986: e72c b.n 80007e2 <__aeabi_dmul+0x24a> 8000988: ea95 0f0c teq r5, ip 800098c: d106 bne.n 800099c <__aeabi_ddiv+0x1b0> 800098e: ea52 3503 orrs.w r5, r2, r3, lsl #12 8000992: f43f aefd beq.w 8000790 <__aeabi_dmul+0x1f8> 8000996: 4610 mov r0, r2 8000998: 4619 mov r1, r3 800099a: e722 b.n 80007e2 <__aeabi_dmul+0x24a> 800099c: ea50 0641 orrs.w r6, r0, r1, lsl #1 80009a0: bf18 it ne 80009a2: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80009a6: f47f aec5 bne.w 8000734 <__aeabi_dmul+0x19c> 80009aa: ea50 0441 orrs.w r4, r0, r1, lsl #1 80009ae: f47f af0d bne.w 80007cc <__aeabi_dmul+0x234> 80009b2: ea52 0543 orrs.w r5, r2, r3, lsl #1 80009b6: f47f aeeb bne.w 8000790 <__aeabi_dmul+0x1f8> 80009ba: e712 b.n 80007e2 <__aeabi_dmul+0x24a> 080009bc <__gedf2>: 80009bc: f04f 3cff mov.w ip, #4294967295 80009c0: e006 b.n 80009d0 <__cmpdf2+0x4> 80009c2: bf00 nop 080009c4 <__ledf2>: 80009c4: f04f 0c01 mov.w ip, #1 80009c8: e002 b.n 80009d0 <__cmpdf2+0x4> 80009ca: bf00 nop 080009cc <__cmpdf2>: 80009cc: f04f 0c01 mov.w ip, #1 80009d0: f84d cd04 str.w ip, [sp, #-4]! 80009d4: ea4f 0c41 mov.w ip, r1, lsl #1 80009d8: ea7f 5c6c mvns.w ip, ip, asr #21 80009dc: ea4f 0c43 mov.w ip, r3, lsl #1 80009e0: bf18 it ne 80009e2: ea7f 5c6c mvnsne.w ip, ip, asr #21 80009e6: d01b beq.n 8000a20 <__cmpdf2+0x54> 80009e8: b001 add sp, #4 80009ea: ea50 0c41 orrs.w ip, r0, r1, lsl #1 80009ee: bf0c ite eq 80009f0: ea52 0c43 orrseq.w ip, r2, r3, lsl #1 80009f4: ea91 0f03 teqne r1, r3 80009f8: bf02 ittt eq 80009fa: ea90 0f02 teqeq r0, r2 80009fe: 2000 moveq r0, #0 8000a00: 4770 bxeq lr 8000a02: f110 0f00 cmn.w r0, #0 8000a06: ea91 0f03 teq r1, r3 8000a0a: bf58 it pl 8000a0c: 4299 cmppl r1, r3 8000a0e: bf08 it eq 8000a10: 4290 cmpeq r0, r2 8000a12: bf2c ite cs 8000a14: 17d8 asrcs r0, r3, #31 8000a16: ea6f 70e3 mvncc.w r0, r3, asr #31 8000a1a: f040 0001 orr.w r0, r0, #1 8000a1e: 4770 bx lr 8000a20: ea4f 0c41 mov.w ip, r1, lsl #1 8000a24: ea7f 5c6c mvns.w ip, ip, asr #21 8000a28: d102 bne.n 8000a30 <__cmpdf2+0x64> 8000a2a: ea50 3c01 orrs.w ip, r0, r1, lsl #12 8000a2e: d107 bne.n 8000a40 <__cmpdf2+0x74> 8000a30: ea4f 0c43 mov.w ip, r3, lsl #1 8000a34: ea7f 5c6c mvns.w ip, ip, asr #21 8000a38: d1d6 bne.n 80009e8 <__cmpdf2+0x1c> 8000a3a: ea52 3c03 orrs.w ip, r2, r3, lsl #12 8000a3e: d0d3 beq.n 80009e8 <__cmpdf2+0x1c> 8000a40: f85d 0b04 ldr.w r0, [sp], #4 8000a44: 4770 bx lr 8000a46: bf00 nop 08000a48 <__aeabi_cdrcmple>: 8000a48: 4684 mov ip, r0 8000a4a: 4610 mov r0, r2 8000a4c: 4662 mov r2, ip 8000a4e: 468c mov ip, r1 8000a50: 4619 mov r1, r3 8000a52: 4663 mov r3, ip 8000a54: e000 b.n 8000a58 <__aeabi_cdcmpeq> 8000a56: bf00 nop 08000a58 <__aeabi_cdcmpeq>: 8000a58: b501 push {r0, lr} 8000a5a: f7ff ffb7 bl 80009cc <__cmpdf2> 8000a5e: 2800 cmp r0, #0 8000a60: bf48 it mi 8000a62: f110 0f00 cmnmi.w r0, #0 8000a66: bd01 pop {r0, pc} 08000a68 <__aeabi_dcmpeq>: 8000a68: f84d ed08 str.w lr, [sp, #-8]! 8000a6c: f7ff fff4 bl 8000a58 <__aeabi_cdcmpeq> 8000a70: bf0c ite eq 8000a72: 2001 moveq r0, #1 8000a74: 2000 movne r0, #0 8000a76: f85d fb08 ldr.w pc, [sp], #8 8000a7a: bf00 nop 08000a7c <__aeabi_dcmplt>: 8000a7c: f84d ed08 str.w lr, [sp, #-8]! 8000a80: f7ff ffea bl 8000a58 <__aeabi_cdcmpeq> 8000a84: bf34 ite cc 8000a86: 2001 movcc r0, #1 8000a88: 2000 movcs r0, #0 8000a8a: f85d fb08 ldr.w pc, [sp], #8 8000a8e: bf00 nop 08000a90 <__aeabi_dcmple>: 8000a90: f84d ed08 str.w lr, [sp, #-8]! 8000a94: f7ff ffe0 bl 8000a58 <__aeabi_cdcmpeq> 8000a98: bf94 ite ls 8000a9a: 2001 movls r0, #1 8000a9c: 2000 movhi r0, #0 8000a9e: f85d fb08 ldr.w pc, [sp], #8 8000aa2: bf00 nop 08000aa4 <__aeabi_dcmpge>: 8000aa4: f84d ed08 str.w lr, [sp, #-8]! 8000aa8: f7ff ffce bl 8000a48 <__aeabi_cdrcmple> 8000aac: bf94 ite ls 8000aae: 2001 movls r0, #1 8000ab0: 2000 movhi r0, #0 8000ab2: f85d fb08 ldr.w pc, [sp], #8 8000ab6: bf00 nop 08000ab8 <__aeabi_dcmpgt>: 8000ab8: f84d ed08 str.w lr, [sp, #-8]! 8000abc: f7ff ffc4 bl 8000a48 <__aeabi_cdrcmple> 8000ac0: bf34 ite cc 8000ac2: 2001 movcc r0, #1 8000ac4: 2000 movcs r0, #0 8000ac6: f85d fb08 ldr.w pc, [sp], #8 8000aca: bf00 nop 08000acc <__aeabi_dcmpun>: 8000acc: ea4f 0c41 mov.w ip, r1, lsl #1 8000ad0: ea7f 5c6c mvns.w ip, ip, asr #21 8000ad4: d102 bne.n 8000adc <__aeabi_dcmpun+0x10> 8000ad6: ea50 3c01 orrs.w ip, r0, r1, lsl #12 8000ada: d10a bne.n 8000af2 <__aeabi_dcmpun+0x26> 8000adc: ea4f 0c43 mov.w ip, r3, lsl #1 8000ae0: ea7f 5c6c mvns.w ip, ip, asr #21 8000ae4: d102 bne.n 8000aec <__aeabi_dcmpun+0x20> 8000ae6: ea52 3c03 orrs.w ip, r2, r3, lsl #12 8000aea: d102 bne.n 8000af2 <__aeabi_dcmpun+0x26> 8000aec: f04f 0000 mov.w r0, #0 8000af0: 4770 bx lr 8000af2: f04f 0001 mov.w r0, #1 8000af6: 4770 bx lr 08000af8 <__aeabi_d2iz>: 8000af8: ea4f 0241 mov.w r2, r1, lsl #1 8000afc: f512 1200 adds.w r2, r2, #2097152 ; 0x200000 8000b00: d215 bcs.n 8000b2e <__aeabi_d2iz+0x36> 8000b02: d511 bpl.n 8000b28 <__aeabi_d2iz+0x30> 8000b04: f46f 7378 mvn.w r3, #992 ; 0x3e0 8000b08: ebb3 5262 subs.w r2, r3, r2, asr #21 8000b0c: d912 bls.n 8000b34 <__aeabi_d2iz+0x3c> 8000b0e: ea4f 23c1 mov.w r3, r1, lsl #11 8000b12: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 8000b16: ea43 5350 orr.w r3, r3, r0, lsr #21 8000b1a: f011 4f00 tst.w r1, #2147483648 ; 0x80000000 8000b1e: fa23 f002 lsr.w r0, r3, r2 8000b22: bf18 it ne 8000b24: 4240 negne r0, r0 8000b26: 4770 bx lr 8000b28: f04f 0000 mov.w r0, #0 8000b2c: 4770 bx lr 8000b2e: ea50 3001 orrs.w r0, r0, r1, lsl #12 8000b32: d105 bne.n 8000b40 <__aeabi_d2iz+0x48> 8000b34: f011 4000 ands.w r0, r1, #2147483648 ; 0x80000000 8000b38: bf08 it eq 8000b3a: f06f 4000 mvneq.w r0, #2147483648 ; 0x80000000 8000b3e: 4770 bx lr 8000b40: f04f 0000 mov.w r0, #0 8000b44: 4770 bx lr 8000b46: bf00 nop 08000b48 <__aeabi_d2uiz>: 8000b48: 004a lsls r2, r1, #1 8000b4a: d211 bcs.n 8000b70 <__aeabi_d2uiz+0x28> 8000b4c: f512 1200 adds.w r2, r2, #2097152 ; 0x200000 8000b50: d211 bcs.n 8000b76 <__aeabi_d2uiz+0x2e> 8000b52: d50d bpl.n 8000b70 <__aeabi_d2uiz+0x28> 8000b54: f46f 7378 mvn.w r3, #992 ; 0x3e0 8000b58: ebb3 5262 subs.w r2, r3, r2, asr #21 8000b5c: d40e bmi.n 8000b7c <__aeabi_d2uiz+0x34> 8000b5e: ea4f 23c1 mov.w r3, r1, lsl #11 8000b62: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 8000b66: ea43 5350 orr.w r3, r3, r0, lsr #21 8000b6a: fa23 f002 lsr.w r0, r3, r2 8000b6e: 4770 bx lr 8000b70: f04f 0000 mov.w r0, #0 8000b74: 4770 bx lr 8000b76: ea50 3001 orrs.w r0, r0, r1, lsl #12 8000b7a: d102 bne.n 8000b82 <__aeabi_d2uiz+0x3a> 8000b7c: f04f 30ff mov.w r0, #4294967295 8000b80: 4770 bx lr 8000b82: f04f 0000 mov.w r0, #0 8000b86: 4770 bx lr 08000b88 <__aeabi_d2f>: 8000b88: ea4f 0241 mov.w r2, r1, lsl #1 8000b8c: f1b2 43e0 subs.w r3, r2, #1879048192 ; 0x70000000 8000b90: bf24 itt cs 8000b92: f5b3 1c00 subscs.w ip, r3, #2097152 ; 0x200000 8000b96: f1dc 5cfe rsbscs ip, ip, #532676608 ; 0x1fc00000 8000b9a: d90d bls.n 8000bb8 <__aeabi_d2f+0x30> 8000b9c: f001 4c00 and.w ip, r1, #2147483648 ; 0x80000000 8000ba0: ea4f 02c0 mov.w r2, r0, lsl #3 8000ba4: ea4c 7050 orr.w r0, ip, r0, lsr #29 8000ba8: f1b2 4f00 cmp.w r2, #2147483648 ; 0x80000000 8000bac: eb40 0083 adc.w r0, r0, r3, lsl #2 8000bb0: bf08 it eq 8000bb2: f020 0001 biceq.w r0, r0, #1 8000bb6: 4770 bx lr 8000bb8: f011 4f80 tst.w r1, #1073741824 ; 0x40000000 8000bbc: d121 bne.n 8000c02 <__aeabi_d2f+0x7a> 8000bbe: f113 7238 adds.w r2, r3, #48234496 ; 0x2e00000 8000bc2: bfbc itt lt 8000bc4: f001 4000 andlt.w r0, r1, #2147483648 ; 0x80000000 8000bc8: 4770 bxlt lr 8000bca: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 8000bce: ea4f 5252 mov.w r2, r2, lsr #21 8000bd2: f1c2 0218 rsb r2, r2, #24 8000bd6: f1c2 0c20 rsb ip, r2, #32 8000bda: fa10 f30c lsls.w r3, r0, ip 8000bde: fa20 f002 lsr.w r0, r0, r2 8000be2: bf18 it ne 8000be4: f040 0001 orrne.w r0, r0, #1 8000be8: ea4f 23c1 mov.w r3, r1, lsl #11 8000bec: ea4f 23d3 mov.w r3, r3, lsr #11 8000bf0: fa03 fc0c lsl.w ip, r3, ip 8000bf4: ea40 000c orr.w r0, r0, ip 8000bf8: fa23 f302 lsr.w r3, r3, r2 8000bfc: ea4f 0343 mov.w r3, r3, lsl #1 8000c00: e7cc b.n 8000b9c <__aeabi_d2f+0x14> 8000c02: ea7f 5362 mvns.w r3, r2, asr #21 8000c06: d107 bne.n 8000c18 <__aeabi_d2f+0x90> 8000c08: ea50 3301 orrs.w r3, r0, r1, lsl #12 8000c0c: bf1e ittt ne 8000c0e: f04f 40fe movne.w r0, #2130706432 ; 0x7f000000 8000c12: f440 0040 orrne.w r0, r0, #12582912 ; 0xc00000 8000c16: 4770 bxne lr 8000c18: f001 4000 and.w r0, r1, #2147483648 ; 0x80000000 8000c1c: f040 40fe orr.w r0, r0, #2130706432 ; 0x7f000000 8000c20: f440 0000 orr.w r0, r0, #8388608 ; 0x800000 8000c24: 4770 bx lr 8000c26: bf00 nop 08000c28 : void NessLab_Init(){ FLASH_Read_Func(FLASH_USER_USE_START_ADDR + 2,&DB_Define[0],104); HAL_GPIO_WritePin(PAU_RESET_GPIO_Port,PAU_RESET_Pin, GPIO_PIN_SET); } double Round_Function(double value){ 8000c28: b590 push {r4, r7, lr} 8000c2a: b085 sub sp, #20 8000c2c: af00 add r7, sp, #0 8000c2e: e9c7 0100 strd r0, r1, [r7] double val = value * 100; 8000c32: f04f 0200 mov.w r2, #0 8000c36: 4b2a ldr r3, [pc, #168] ; (8000ce0 ) 8000c38: e9d7 0100 ldrd r0, r1, [r7] 8000c3c: f7ff fcac bl 8000598 <__aeabi_dmul> 8000c40: 4603 mov r3, r0 8000c42: 460c mov r4, r1 8000c44: e9c7 3402 strd r3, r4, [r7, #8] val = (int)(val + 0.5); 8000c48: f04f 0200 mov.w r2, #0 8000c4c: 4b25 ldr r3, [pc, #148] ; (8000ce4 ) 8000c4e: e9d7 0102 ldrd r0, r1, [r7, #8] 8000c52: f7ff faeb bl 800022c <__adddf3> 8000c56: 4603 mov r3, r0 8000c58: 460c mov r4, r1 8000c5a: 4618 mov r0, r3 8000c5c: 4621 mov r1, r4 8000c5e: f7ff ff4b bl 8000af8 <__aeabi_d2iz> 8000c62: 4603 mov r3, r0 8000c64: 4618 mov r0, r3 8000c66: f7ff fc2d bl 80004c4 <__aeabi_i2d> 8000c6a: 4603 mov r3, r0 8000c6c: 460c mov r4, r1 8000c6e: e9c7 3402 strd r3, r4, [r7, #8] val *= 0.1; 8000c72: a319 add r3, pc, #100 ; (adr r3, 8000cd8 ) 8000c74: e9d3 2300 ldrd r2, r3, [r3] 8000c78: e9d7 0102 ldrd r0, r1, [r7, #8] 8000c7c: f7ff fc8c bl 8000598 <__aeabi_dmul> 8000c80: 4603 mov r3, r0 8000c82: 460c mov r4, r1 8000c84: e9c7 3402 strd r3, r4, [r7, #8] val = (int)(val + 0.5); 8000c88: f04f 0200 mov.w r2, #0 8000c8c: 4b15 ldr r3, [pc, #84] ; (8000ce4 ) 8000c8e: e9d7 0102 ldrd r0, r1, [r7, #8] 8000c92: f7ff facb bl 800022c <__adddf3> 8000c96: 4603 mov r3, r0 8000c98: 460c mov r4, r1 8000c9a: 4618 mov r0, r3 8000c9c: 4621 mov r1, r4 8000c9e: f7ff ff2b bl 8000af8 <__aeabi_d2iz> 8000ca2: 4603 mov r3, r0 8000ca4: 4618 mov r0, r3 8000ca6: f7ff fc0d bl 80004c4 <__aeabi_i2d> 8000caa: 4603 mov r3, r0 8000cac: 460c mov r4, r1 8000cae: e9c7 3402 strd r3, r4, [r7, #8] val *= 0.1; 8000cb2: a309 add r3, pc, #36 ; (adr r3, 8000cd8 ) 8000cb4: e9d3 2300 ldrd r2, r3, [r3] 8000cb8: e9d7 0102 ldrd r0, r1, [r7, #8] 8000cbc: f7ff fc6c bl 8000598 <__aeabi_dmul> 8000cc0: 4603 mov r3, r0 8000cc2: 460c mov r4, r1 8000cc4: e9c7 3402 strd r3, r4, [r7, #8] return val; 8000cc8: e9d7 3402 ldrd r3, r4, [r7, #8] } 8000ccc: 4618 mov r0, r3 8000cce: 4621 mov r1, r4 8000cd0: 3714 adds r7, #20 8000cd2: 46bd mov sp, r7 8000cd4: bd90 pop {r4, r7, pc} 8000cd6: bf00 nop 8000cd8: 9999999a .word 0x9999999a 8000cdc: 3fb99999 .word 0x3fb99999 8000ce0: 40590000 .word 0x40590000 8000ce4: 3fe00000 .word 0x3fe00000 08000ce8 : uint16_t Absolute_value_Convert(int16_t val){ 8000ce8: b480 push {r7} 8000cea: b083 sub sp, #12 8000cec: af00 add r7, sp, #0 8000cee: 4603 mov r3, r0 8000cf0: 80fb strh r3, [r7, #6] if(val < 0) 8000cf2: f9b7 3006 ldrsh.w r3, [r7, #6] 8000cf6: 2b00 cmp r3, #0 8000cf8: da03 bge.n 8000d02 val *= -1; 8000cfa: 88fb ldrh r3, [r7, #6] 8000cfc: 425b negs r3, r3 8000cfe: b29b uxth r3, r3 8000d00: 80fb strh r3, [r7, #6] return val; 8000d02: 88fb ldrh r3, [r7, #6] } 8000d04: 4618 mov r0, r3 8000d06: 370c adds r7, #12 8000d08: 46bd mov sp, r7 8000d0a: bc80 pop {r7} 8000d0c: 4770 bx lr ... 08000d10 : uint8_t NessLab_Adc_Convert_db() // ?占쏙옙湲고븿?占쏙옙 { 8000d10: b590 push {r4, r7, lr} 8000d12: b08b sub sp, #44 ; 0x2c 8000d14: af00 add r7, sp, #0 double CurrAdc = (float)((Currstatus.DownLink_Forward_Det_H << 8 | Currstatus.DownLink_Forward_Det_L)*0.001); 8000d16: 4b4a ldr r3, [pc, #296] ; (8000e40 ) 8000d18: 79db ldrb r3, [r3, #7] 8000d1a: 021b lsls r3, r3, #8 8000d1c: 4a48 ldr r2, [pc, #288] ; (8000e40 ) 8000d1e: 7a12 ldrb r2, [r2, #8] 8000d20: 4313 orrs r3, r2 8000d22: 4618 mov r0, r3 8000d24: f7ff fbce bl 80004c4 <__aeabi_i2d> 8000d28: a343 add r3, pc, #268 ; (adr r3, 8000e38 ) 8000d2a: e9d3 2300 ldrd r2, r3, [r3] 8000d2e: f7ff fc33 bl 8000598 <__aeabi_dmul> 8000d32: 4603 mov r3, r0 8000d34: 460c mov r4, r1 8000d36: 4618 mov r0, r3 8000d38: 4621 mov r1, r4 8000d3a: f7ff ff25 bl 8000b88 <__aeabi_d2f> 8000d3e: 4603 mov r3, r0 8000d40: 4618 mov r0, r3 8000d42: f7ff fbd1 bl 80004e8 <__aeabi_f2d> 8000d46: 4603 mov r3, r0 8000d48: 460c mov r4, r1 8000d4a: e9c7 3406 strd r3, r4, [r7, #24] double TableVal = 0; 8000d4e: f04f 0300 mov.w r3, #0 8000d52: f04f 0400 mov.w r4, #0 8000d56: e9c7 3404 strd r3, r4, [r7, #16] float ret = 0; 8000d5a: f04f 0300 mov.w r3, #0 8000d5e: 60fb str r3, [r7, #12] int16_t calc_val = 0,Prev_calc_val = 3300 ; 8000d60: 2300 movs r3, #0 8000d62: 817b strh r3, [r7, #10] 8000d64: f640 43e4 movw r3, #3300 ; 0xce4 8000d68: 84fb strh r3, [r7, #38] ; 0x26 uint8_t Curr_DB = 0 ; 8000d6a: 2300 movs r3, #0 8000d6c: f887 3025 strb.w r3, [r7, #37] ; 0x25 uint16_t CurrAdc_Temp = 0,TableVal_Temp = 0; 8000d70: 2300 movs r3, #0 8000d72: 813b strh r3, [r7, #8] 8000d74: 2300 movs r3, #0 8000d76: 80fb strh r3, [r7, #6] ret = Round_Function(CurrAdc); 8000d78: e9d7 0106 ldrd r0, r1, [r7, #24] 8000d7c: f7ff ff54 bl 8000c28 8000d80: 4603 mov r3, r0 8000d82: 460c mov r4, r1 8000d84: 4618 mov r0, r3 8000d86: 4621 mov r1, r4 8000d88: f7ff fefe bl 8000b88 <__aeabi_d2f> 8000d8c: 4603 mov r3, r0 8000d8e: 60fb str r3, [r7, #12] // CurrAdc *= 1000; CurrAdc_Temp = CurrAdc * 1000; 8000d90: f04f 0200 mov.w r2, #0 8000d94: 4b2b ldr r3, [pc, #172] ; (8000e44 ) 8000d96: e9d7 0106 ldrd r0, r1, [r7, #24] 8000d9a: f7ff fbfd bl 8000598 <__aeabi_dmul> 8000d9e: 4603 mov r3, r0 8000da0: 460c mov r4, r1 8000da2: 4618 mov r0, r3 8000da4: 4621 mov r1, r4 8000da6: f7ff fecf bl 8000b48 <__aeabi_d2uiz> 8000daa: 4603 mov r3, r0 8000dac: 813b strh r3, [r7, #8] for(int i = 0; i <= 50; i++){ 8000dae: 2300 movs r3, #0 8000db0: 623b str r3, [r7, #32] 8000db2: e032 b.n 8000e1a TableVal_Temp = ((DB_Define[i * 2] << 8 | DB_Define[(i * 2)+ 1])); 8000db4: 6a3b ldr r3, [r7, #32] 8000db6: 005b lsls r3, r3, #1 8000db8: 4a23 ldr r2, [pc, #140] ; (8000e48 ) 8000dba: 5cd3 ldrb r3, [r2, r3] 8000dbc: 021b lsls r3, r3, #8 8000dbe: b21a sxth r2, r3 8000dc0: 6a3b ldr r3, [r7, #32] 8000dc2: 005b lsls r3, r3, #1 8000dc4: 3301 adds r3, #1 8000dc6: 4920 ldr r1, [pc, #128] ; (8000e48 ) 8000dc8: 5ccb ldrb r3, [r1, r3] 8000dca: b21b sxth r3, r3 8000dcc: 4313 orrs r3, r2 8000dce: b21b sxth r3, r3 8000dd0: 80fb strh r3, [r7, #6] if(TableVal_Temp == 0) 8000dd2: 88fb ldrh r3, [r7, #6] 8000dd4: 2b00 cmp r3, #0 8000dd6: d01c beq.n 8000e12 continue; calc_val = CurrAdc_Temp - TableVal_Temp; 8000dd8: 893a ldrh r2, [r7, #8] 8000dda: 88fb ldrh r3, [r7, #6] 8000ddc: 1ad3 subs r3, r2, r3 8000dde: b29b uxth r3, r3 8000de0: 817b strh r3, [r7, #10] calc_val = Absolute_value_Convert(calc_val); 8000de2: f9b7 300a ldrsh.w r3, [r7, #10] 8000de6: 4618 mov r0, r3 8000de8: f7ff ff7e bl 8000ce8 8000dec: 4603 mov r3, r0 8000dee: 817b strh r3, [r7, #10] // printf("%d - %d calc_val : %d \r\n",CurrAdc_Temp,TableVal_Temp,calc_val); if(Prev_calc_val > calc_val && TableVal_Temp != 0){ 8000df0: f9b7 2026 ldrsh.w r2, [r7, #38] ; 0x26 8000df4: f9b7 300a ldrsh.w r3, [r7, #10] 8000df8: 429a cmp r2, r3 8000dfa: dd0b ble.n 8000e14 8000dfc: 88fb ldrh r3, [r7, #6] 8000dfe: 2b00 cmp r3, #0 8000e00: d008 beq.n 8000e14 Prev_calc_val = calc_val; 8000e02: 897b ldrh r3, [r7, #10] 8000e04: 84fb strh r3, [r7, #38] ; 0x26 Curr_DB = i + 2; 8000e06: 6a3b ldr r3, [r7, #32] 8000e08: b2db uxtb r3, r3 8000e0a: 3302 adds r3, #2 8000e0c: f887 3025 strb.w r3, [r7, #37] ; 0x25 8000e10: e000 b.n 8000e14 continue; 8000e12: bf00 nop for(int i = 0; i <= 50; i++){ 8000e14: 6a3b ldr r3, [r7, #32] 8000e16: 3301 adds r3, #1 8000e18: 623b str r3, [r7, #32] 8000e1a: 6a3b ldr r3, [r7, #32] 8000e1c: 2b32 cmp r3, #50 ; 0x32 8000e1e: ddc9 ble.n 8000db4 // printf("%d %d \r\n",Prev_calc_val , calc_val); } } // DB_Define[] printf("Curr Db : %d \r\n",Curr_DB); 8000e20: f897 3025 ldrb.w r3, [r7, #37] ; 0x25 8000e24: 4619 mov r1, r3 8000e26: 4809 ldr r0, [pc, #36] ; (8000e4c ) 8000e28: f005 fce4 bl 80067f4 return Curr_DB; 8000e2c: f897 3025 ldrb.w r3, [r7, #37] ; 0x25 } 8000e30: 4618 mov r0, r3 8000e32: 372c adds r7, #44 ; 0x2c 8000e34: 46bd mov sp, r7 8000e36: bd90 pop {r4, r7, pc} 8000e38: d2f1a9fc .word 0xd2f1a9fc 8000e3c: 3f50624d .word 0x3f50624d 8000e40: 200006ac .word 0x200006ac 8000e44: 408f4000 .word 0x408f4000 8000e48: 20000648 .word 0x20000648 8000e4c: 080087f0 .word 0x080087f0 08000e50 : void NessLab_Operate(uint8_t* data){ 8000e50: b580 push {r7, lr} 8000e52: b086 sub sp, #24 8000e54: af00 add r7, sp, #0 8000e56: 6078 str r0, [r7, #4] uint8_t datatype = data[NessLab_MsgID0]; 8000e58: 687b ldr r3, [r7, #4] 8000e5a: 789b ldrb r3, [r3, #2] 8000e5c: 73fb strb r3, [r7, #15] uint8_t UartLength = 0; 8000e5e: 2300 movs r3, #0 8000e60: 75fb strb r3, [r7, #23] static uint16_t MSG_SNCnt = 0; switch(datatype){ 8000e62: 7bfb ldrb r3, [r7, #15] 8000e64: 2bcb cmp r3, #203 ; 0xcb 8000e66: d049 beq.n 8000efc 8000e68: 2bcb cmp r3, #203 ; 0xcb 8000e6a: dc04 bgt.n 8000e76 8000e6c: 2b65 cmp r3, #101 ; 0x65 8000e6e: d008 beq.n 8000e82 8000e70: 2bc9 cmp r3, #201 ; 0xc9 8000e72: d030 beq.n 8000ed6 8000e74: e08f b.n 8000f96 8000e76: 2bcd cmp r3, #205 ; 0xcd 8000e78: d07f beq.n 8000f7a 8000e7a: 2bce cmp r3, #206 ; 0xce 8000e7c: f000 8084 beq.w 8000f88 8000e80: e089 b.n 8000f96 case NessLab_STATUS_REQ: ADC_Check(); 8000e82: f000 fb5f bl 8001544 UartLength = NessLab_MAX_INDEX + 1; 8000e86: 2316 movs r3, #22 8000e88: 75fb strb r3, [r7, #23] MSG_SNCnt = data[NessLab_Req_MsgSN0] << 8 | data[NessLab_Req_MsgSN1]; 8000e8a: 687b ldr r3, [r7, #4] 8000e8c: 3303 adds r3, #3 8000e8e: 781b ldrb r3, [r3, #0] 8000e90: 021b lsls r3, r3, #8 8000e92: b21a sxth r2, r3 8000e94: 687b ldr r3, [r7, #4] 8000e96: 3304 adds r3, #4 8000e98: 781b ldrb r3, [r3, #0] 8000e9a: b21b sxth r3, r3 8000e9c: 4313 orrs r3, r2 8000e9e: b21b sxth r3, r3 8000ea0: b29a uxth r2, r3 8000ea2: 4b41 ldr r3, [pc, #260] ; (8000fa8 ) 8000ea4: 801a strh r2, [r3, #0] MSG_SNCnt++; 8000ea6: 4b40 ldr r3, [pc, #256] ; (8000fa8 ) 8000ea8: 881b ldrh r3, [r3, #0] 8000eaa: 3301 adds r3, #1 8000eac: b29a uxth r2, r3 8000eae: 4b3e ldr r3, [pc, #248] ; (8000fa8 ) 8000eb0: 801a strh r2, [r3, #0] // if(data[NessLab_Req_Data_Cnt1] > 0) // NessLab_TxData[NessLab_VSWR_ALARM] = 1; // else // NessLab_TxData[NessLab_VSWR_ALARM] = 0; NessLab_TxData[NessLab_MsgSN0] = (uint8_t)((MSG_SNCnt & 0xFF00) >>8);//data[NessLab_Req_MsgSN0]; 8000eb2: 4b3d ldr r3, [pc, #244] ; (8000fa8 ) 8000eb4: 881b ldrh r3, [r3, #0] 8000eb6: 0a1b lsrs r3, r3, #8 8000eb8: b29b uxth r3, r3 8000eba: b2da uxtb r2, r3 8000ebc: 4b3b ldr r3, [pc, #236] ; (8000fac ) 8000ebe: 70da strb r2, [r3, #3] NessLab_TxData[NessLab_MsgSN1] = (uint8_t)((MSG_SNCnt & 0x00FF));//data[NessLab_Req_MsgSN1] ; 8000ec0: 4b39 ldr r3, [pc, #228] ; (8000fa8 ) 8000ec2: 881b ldrh r3, [r3, #0] 8000ec4: b2da uxtb r2, r3 8000ec6: 4b39 ldr r3, [pc, #228] ; (8000fac ) 8000ec8: 711a strb r2, [r3, #4] NessLab_Frame_Set(NessLab_TxData,12,NessLab_STATUS_RES); 8000eca: 2266 movs r2, #102 ; 0x66 8000ecc: 210c movs r1, #12 8000ece: 4837 ldr r0, [pc, #220] ; (8000fac ) 8000ed0: f000 f882 bl 8000fd8 // NessLab_TxData[14] = 1; // NessLab_TxData[15] = 0; // NessLab_TxData[16] = 1; // NessLab_TxData[17] = 0; break; 8000ed4: e05f b.n 8000f96 case NessLab_Table_REQ: UartLength = NESSLAB_TABLE_LENGTH; 8000ed6: 236e movs r3, #110 ; 0x6e 8000ed8: 75fb strb r3, [r7, #23] FLASH_Read_Func(FLASH_USER_USE_START_ADDR,&NessLab_TxData[NessLab_Req_Data_Cnt0],data[NessLab_DataLength]); 8000eda: 687b ldr r3, [r7, #4] 8000edc: 3306 adds r3, #6 8000ede: 781b ldrb r3, [r3, #0] 8000ee0: 461a mov r2, r3 8000ee2: 4933 ldr r1, [pc, #204] ; (8000fb0 ) 8000ee4: 4833 ldr r0, [pc, #204] ; (8000fb4 ) 8000ee6: f000 fceb bl 80018c0 NessLab_Table_Frame_Set(NessLab_TxData,102,NessLab_Table_RES); 8000eea: 22ca movs r2, #202 ; 0xca 8000eec: 2166 movs r1, #102 ; 0x66 8000eee: 482f ldr r0, [pc, #188] ; (8000fac ) 8000ef0: f000 f97e bl 80011f0 printf("NessLab_Table_REQ \r\n"); 8000ef4: 4830 ldr r0, [pc, #192] ; (8000fb8 ) 8000ef6: f005 fcf1 bl 80068dc break; 8000efa: e04c b.n 8000f96 case NessLab_TableSet_REQ: DataErase_Func(FLASH_USER_USE_START_ADDR,200); 8000efc: 21c8 movs r1, #200 ; 0xc8 8000efe: 482d ldr r0, [pc, #180] ; (8000fb4 ) 8000f00: f000 fc04 bl 800170c printf("Ram Data Display \r\n"); 8000f04: 482d ldr r0, [pc, #180] ; (8000fbc ) 8000f06: f005 fce9 bl 80068dc for(int i = 0; i < data[NessLab_DataLength]; i++){ 8000f0a: 2300 movs r3, #0 8000f0c: 613b str r3, [r7, #16] 8000f0e: e015 b.n 8000f3c Flash_DataArray[i] = data[NessLab_Data_ADC1_H + i]; 8000f10: 693b ldr r3, [r7, #16] 8000f12: 3307 adds r3, #7 8000f14: 461a mov r2, r3 8000f16: 687b ldr r3, [r7, #4] 8000f18: 4413 add r3, r2 8000f1a: 7819 ldrb r1, [r3, #0] 8000f1c: 4a28 ldr r2, [pc, #160] ; (8000fc0 ) 8000f1e: 693b ldr r3, [r7, #16] 8000f20: 4413 add r3, r2 8000f22: 460a mov r2, r1 8000f24: 701a strb r2, [r3, #0] printf("%x ",Flash_DataArray[i]); 8000f26: 4a26 ldr r2, [pc, #152] ; (8000fc0 ) 8000f28: 693b ldr r3, [r7, #16] 8000f2a: 4413 add r3, r2 8000f2c: 781b ldrb r3, [r3, #0] 8000f2e: 4619 mov r1, r3 8000f30: 4824 ldr r0, [pc, #144] ; (8000fc4 ) 8000f32: f005 fc5f bl 80067f4 for(int i = 0; i < data[NessLab_DataLength]; i++){ 8000f36: 693b ldr r3, [r7, #16] 8000f38: 3301 adds r3, #1 8000f3a: 613b str r3, [r7, #16] 8000f3c: 687b ldr r3, [r7, #4] 8000f3e: 3306 adds r3, #6 8000f40: 781b ldrb r3, [r3, #0] 8000f42: 461a mov r2, r3 8000f44: 693b ldr r3, [r7, #16] 8000f46: 4293 cmp r3, r2 8000f48: dbe2 blt.n 8000f10 } FLASH_Write_Func(FLASH_USER_USE_START_ADDR,&Flash_DataArray[0],data[NessLab_DataLength]); 8000f4a: 687b ldr r3, [r7, #4] 8000f4c: 3306 adds r3, #6 8000f4e: 781b ldrb r3, [r3, #0] 8000f50: 461a mov r2, r3 8000f52: 491b ldr r1, [pc, #108] ; (8000fc0 ) 8000f54: 4817 ldr r0, [pc, #92] ; (8000fb4 ) 8000f56: f000 fc2b bl 80017b0 UartLength = NESSLAB_TABLE_LENGTH; 8000f5a: 236e movs r3, #110 ; 0x6e 8000f5c: 75fb strb r3, [r7, #23] NessLab_Table_Frame_Set(NessLab_TxData,104,NessLab_TableSet_RES); 8000f5e: 22cc movs r2, #204 ; 0xcc 8000f60: 2168 movs r1, #104 ; 0x68 8000f62: 4812 ldr r0, [pc, #72] ; (8000fac ) 8000f64: f000 f944 bl 80011f0 FLASH_Read_Func(FLASH_USER_USE_START_ADDR + 2,&DB_Define[0],104); 8000f68: 2268 movs r2, #104 ; 0x68 8000f6a: 4917 ldr r1, [pc, #92] ; (8000fc8 ) 8000f6c: 4817 ldr r0, [pc, #92] ; (8000fcc ) 8000f6e: f000 fca7 bl 80018c0 // NessLab_Init(); printf("\r\nNessLab_TableSet_REQ \r\n"); 8000f72: 4817 ldr r0, [pc, #92] ; (8000fd0 ) 8000f74: f005 fcb2 bl 80068dc break; 8000f78: e00d b.n 8000f96 case NessLab_PAU_Enable_Req: HAL_GPIO_WritePin(AMP_EN_GPIO_Port,AMP_EN_Pin, GPIO_PIN_SET); 8000f7a: 2201 movs r2, #1 8000f7c: f44f 7180 mov.w r1, #256 ; 0x100 8000f80: 4814 ldr r0, [pc, #80] ; (8000fd4 ) 8000f82: f002 fa34 bl 80033ee break; 8000f86: e006 b.n 8000f96 case NessLab_PAU_Disable_Req: HAL_GPIO_WritePin(AMP_EN_GPIO_Port,AMP_EN_Pin, GPIO_PIN_RESET); 8000f88: 2200 movs r2, #0 8000f8a: f44f 7180 mov.w r1, #256 ; 0x100 8000f8e: 4811 ldr r0, [pc, #68] ; (8000fd4 ) 8000f90: f002 fa2d bl 80033ee break; 8000f94: bf00 nop } Uart1_Data_Send(&NessLab_TxData[NessLab_Header0], UartLength); 8000f96: 7dfb ldrb r3, [r7, #23] 8000f98: 4619 mov r1, r3 8000f9a: 4804 ldr r0, [pc, #16] ; (8000fac ) 8000f9c: f000 fe16 bl 8001bcc } 8000fa0: bf00 nop 8000fa2: 3718 adds r7, #24 8000fa4: 46bd mov sp, r7 8000fa6: bd80 pop {r7, pc} 8000fa8: 2000038c .word 0x2000038c 8000fac: 200001fc .word 0x200001fc 8000fb0: 20000203 .word 0x20000203 8000fb4: 0800ff38 .word 0x0800ff38 8000fb8: 08008800 .word 0x08008800 8000fbc: 08008814 .word 0x08008814 8000fc0: 200002c4 .word 0x200002c4 8000fc4: 08008828 .word 0x08008828 8000fc8: 20000648 .word 0x20000648 8000fcc: 0800ff3a .word 0x0800ff3a 8000fd0: 0800882c .word 0x0800882c 8000fd4: 40010800 .word 0x40010800 08000fd8 : 7e 7e 66 00 02 00 0c 04 20 00 00 00 00 00 00 00 00 00 68 7e 7e 0a */ void NessLab_Frame_Set(uint8_t* data,uint8_t size){ 8000fd8: b590 push {r4, r7, lr} 8000fda: b083 sub sp, #12 8000fdc: af00 add r7, sp, #0 8000fde: 6078 str r0, [r7, #4] 8000fe0: 460b mov r3, r1 8000fe2: 70fb strb r3, [r7, #3] data[NessLab_Header0] = 0x7E; 8000fe4: 687b ldr r3, [r7, #4] 8000fe6: 227e movs r2, #126 ; 0x7e 8000fe8: 701a strb r2, [r3, #0] data[NessLab_Header1] = 0x7E; 8000fea: 687b ldr r3, [r7, #4] 8000fec: 3301 adds r3, #1 8000fee: 227e movs r2, #126 ; 0x7e 8000ff0: 701a strb r2, [r3, #0] data[NessLab_MsgID0] = NessLab_STATUS_RES;// ID 8000ff2: 687b ldr r3, [r7, #4] 8000ff4: 3302 adds r3, #2 8000ff6: 2266 movs r2, #102 ; 0x66 8000ff8: 701a strb r2, [r3, #0] // data[NessLab_MsgSN0] = 0; // SEQ NUMBER // data[NessLab_MsgSN1] = 0; // SEQ NUMBER data[NessLab_Reserve0] = 0; // NessLab_Reserve0 8000ffa: 687b ldr r3, [r7, #4] 8000ffc: 3305 adds r3, #5 8000ffe: 2200 movs r2, #0 8001000: 701a strb r2, [r3, #0] data[NessLab_DataLength] = size; // Nesslab Size 8001002: 687b ldr r3, [r7, #4] 8001004: 3306 adds r3, #6 8001006: 78fa ldrb r2, [r7, #3] 8001008: 701a strb r2, [r3, #0] data[NessLab_Data_ADC1_H] = Currstatus.DownLink_Forward_Det_H;//(uint8_t)((ADC1value[0] & 0xFF00) >> 8); 800100a: 687b ldr r3, [r7, #4] 800100c: 3307 adds r3, #7 800100e: 4a49 ldr r2, [pc, #292] ; (8001134 ) 8001010: 79d2 ldrb r2, [r2, #7] 8001012: 701a strb r2, [r3, #0] data[NessLab_Data_ADC1_L] = Currstatus.DownLink_Forward_Det_L;//(uint8_t)(ADC1value[0] & 0x00FF); 8001014: 687b ldr r3, [r7, #4] 8001016: 3308 adds r3, #8 8001018: 4a46 ldr r2, [pc, #280] ; (8001134 ) 800101a: 7a12 ldrb r2, [r2, #8] 800101c: 701a strb r2, [r3, #0] data[NessLab_Data_ADC1_Table_Value] = NessLab_Adc_Convert_db(); 800101e: 687b ldr r3, [r7, #4] 8001020: f103 0409 add.w r4, r3, #9 8001024: f7ff fe74 bl 8000d10 8001028: 4603 mov r3, r0 800102a: 7023 strb r3, [r4, #0] if(DC_FAIL_ALARM_CNT > 3000) 800102c: 4b42 ldr r3, [pc, #264] ; (8001138 ) 800102e: 681b ldr r3, [r3, #0] 8001030: f640 32b8 movw r2, #3000 ; 0xbb8 8001034: 4293 cmp r3, r2 8001036: d904 bls.n 8001042 data[NessLab_DC_FAIL_ALARM] = 1; 8001038: 687b ldr r3, [r7, #4] 800103a: 330a adds r3, #10 800103c: 2201 movs r2, #1 800103e: 701a strb r2, [r3, #0] 8001040: e003 b.n 800104a else data[NessLab_DC_FAIL_ALARM] = 0; 8001042: 687b ldr r3, [r7, #4] 8001044: 330a adds r3, #10 8001046: 2200 movs r2, #0 8001048: 701a strb r2, [r3, #0] if(OVER_INPUT_ALARM_CNT > 3000) 800104a: 4b3c ldr r3, [pc, #240] ; (800113c ) 800104c: 681b ldr r3, [r3, #0] 800104e: f640 32b8 movw r2, #3000 ; 0xbb8 8001052: 4293 cmp r3, r2 8001054: d904 bls.n 8001060 data[NessLab_Over_Input_Alarm] = 1; 8001056: 687b ldr r3, [r7, #4] 8001058: 330e adds r3, #14 800105a: 2201 movs r2, #1 800105c: 701a strb r2, [r3, #0] 800105e: e003 b.n 8001068 else data[NessLab_Over_Input_Alarm] = 0; 8001060: 687b ldr r3, [r7, #4] 8001062: 330e adds r3, #14 8001064: 2200 movs r2, #0 8001066: 701a strb r2, [r3, #0] if(OVER_TEMP_ALARM_CNT > 3000) 8001068: 4b35 ldr r3, [pc, #212] ; (8001140 ) 800106a: 681b ldr r3, [r3, #0] 800106c: f640 32b8 movw r2, #3000 ; 0xbb8 8001070: 4293 cmp r3, r2 8001072: d904 bls.n 800107e data[NessLab_Over_Temp_Alarm] = 1; 8001074: 687b ldr r3, [r7, #4] 8001076: 330f adds r3, #15 8001078: 2201 movs r2, #1 800107a: 701a strb r2, [r3, #0] 800107c: e003 b.n 8001086 else data[NessLab_Over_Temp_Alarm] = 0; 800107e: 687b ldr r3, [r7, #4] 8001080: 330f adds r3, #15 8001082: 2200 movs r2, #0 8001084: 701a strb r2, [r3, #0] if(ALC_ALARM_CNT > 3000) 8001086: 4b2f ldr r3, [pc, #188] ; (8001144 ) 8001088: 681b ldr r3, [r3, #0] 800108a: f640 32b8 movw r2, #3000 ; 0xbb8 800108e: 4293 cmp r3, r2 8001090: d904 bls.n 800109c data[NessLab_ALC_ALARM] = 1; 8001092: 687b ldr r3, [r7, #4] 8001094: 3311 adds r3, #17 8001096: 2201 movs r2, #1 8001098: 701a strb r2, [r3, #0] 800109a: e003 b.n 80010a4 else data[NessLab_ALC_ALARM] = 0; 800109c: 687b ldr r3, [r7, #4] 800109e: 3311 adds r3, #17 80010a0: 2200 movs r2, #0 80010a2: 701a strb r2, [r3, #0] if(OVER_POWER_ALARM_CNT > 3000) 80010a4: 4b28 ldr r3, [pc, #160] ; (8001148 ) 80010a6: 681b ldr r3, [r3, #0] 80010a8: f640 32b8 movw r2, #3000 ; 0xbb8 80010ac: 4293 cmp r3, r2 80010ae: d904 bls.n 80010ba data[NessLab_Over_Power_Alarm] = 1; 80010b0: 687b ldr r3, [r7, #4] 80010b2: 330c adds r3, #12 80010b4: 2201 movs r2, #1 80010b6: 701a strb r2, [r3, #0] 80010b8: e003 b.n 80010c2 else data[NessLab_Over_Power_Alarm] = 0; 80010ba: 687b ldr r3, [r7, #4] 80010bc: 330c adds r3, #12 80010be: 2200 movs r2, #0 80010c0: 701a strb r2, [r3, #0] if(VSWR_ALARM_CNT > 3000) 80010c2: 4b22 ldr r3, [pc, #136] ; (800114c ) 80010c4: 681b ldr r3, [r3, #0] 80010c6: f640 32b8 movw r2, #3000 ; 0xbb8 80010ca: 4293 cmp r3, r2 80010cc: d904 bls.n 80010d8 data[NessLab_VSWR_ALARM] = 1; 80010ce: 687b ldr r3, [r7, #4] 80010d0: 330d adds r3, #13 80010d2: 2201 movs r2, #1 80010d4: 701a strb r2, [r3, #0] 80010d6: e003 b.n 80010e0 else data[NessLab_VSWR_ALARM] = 0; 80010d8: 687b ldr r3, [r7, #4] 80010da: 330d adds r3, #13 80010dc: 2200 movs r2, #0 80010de: 701a strb r2, [r3, #0] data[NessLab_DownLink_Status] = 0; 80010e0: 687b ldr r3, [r7, #4] 80010e2: 330b adds r3, #11 80010e4: 2200 movs r2, #0 80010e6: 701a strb r2, [r3, #0] data[NessLab_Temp_Monitor] = Currstatus.Temp_Monitor; 80010e8: 687b ldr r3, [r7, #4] 80010ea: 3310 adds r3, #16 80010ec: 4a11 ldr r2, [pc, #68] ; (8001134 ) 80010ee: 7c52 ldrb r2, [r2, #17] 80010f0: 701a strb r2, [r3, #0] data[NessLab_ChecksumVal] = NessLab_Checksum(&data[NessLab_MsgID0], NessLab_MAX_INDEX - 5); 80010f2: 687b ldr r3, [r7, #4] 80010f4: 1c9a adds r2, r3, #2 80010f6: 687b ldr r3, [r7, #4] 80010f8: f103 0412 add.w r4, r3, #18 80010fc: 2110 movs r1, #16 80010fe: 4610 mov r0, r2 8001100: f000 faa8 bl 8001654 8001104: 4603 mov r3, r0 8001106: 7023 strb r3, [r4, #0] /* Exception Header Tail Checksum */ data[NessLab_Tail0] = 0x7E; 8001108: 687b ldr r3, [r7, #4] 800110a: 3313 adds r3, #19 800110c: 227e movs r2, #126 ; 0x7e 800110e: 701a strb r2, [r3, #0] data[NessLab_Tail1] = 0x7E; 8001110: 687b ldr r3, [r7, #4] 8001112: 3314 adds r3, #20 8001114: 227e movs r2, #126 ; 0x7e 8001116: 701a strb r2, [r3, #0] data[NessLab_Tail1 + 1] = 0x0A; 8001118: 687b ldr r3, [r7, #4] 800111a: 3315 adds r3, #21 800111c: 220a movs r2, #10 800111e: 701a strb r2, [r3, #0] NessLab_Protocol_LastCheck(&data[NessLab_MsgID0],16); 8001120: 687b ldr r3, [r7, #4] 8001122: 3302 adds r3, #2 8001124: 2110 movs r1, #16 8001126: 4618 mov r0, r3 8001128: f000 f812 bl 8001150 } 800112c: bf00 nop 800112e: 370c adds r7, #12 8001130: 46bd mov sp, r7 8001132: bd90 pop {r4, r7, pc} 8001134: 200006ac .word 0x200006ac 8001138: 2000061c .word 0x2000061c 800113c: 20000620 .word 0x20000620 8001140: 20000624 .word 0x20000624 8001144: 20000628 .word 0x20000628 8001148: 2000062c .word 0x2000062c 800114c: 20000630 .word 0x20000630 08001150 : void NessLab_Protocol_LastCheck(uint8_t* data,uint8_t size){ 8001150: b480 push {r7} 8001152: b085 sub sp, #20 8001154: af00 add r7, sp, #0 8001156: 6078 str r0, [r7, #4] 8001158: 460b mov r3, r1 800115a: 70fb strb r3, [r7, #3] int cnt = NessLab_MsgID0; 800115c: 2302 movs r3, #2 800115e: 60fb str r3, [r7, #12] for(int i = cnt; i < 17; i++){ 8001160: 68fb ldr r3, [r7, #12] 8001162: 60bb str r3, [r7, #8] 8001164: e03b b.n 80011de if(data[i] == 0x7e){ 8001166: 68bb ldr r3, [r7, #8] 8001168: 687a ldr r2, [r7, #4] 800116a: 4413 add r3, r2 800116c: 781b ldrb r3, [r3, #0] 800116e: 2b7e cmp r3, #126 ; 0x7e 8001170: d110 bne.n 8001194 data[cnt++] = 0x7d; 8001172: 68fb ldr r3, [r7, #12] 8001174: 1c5a adds r2, r3, #1 8001176: 60fa str r2, [r7, #12] 8001178: 461a mov r2, r3 800117a: 687b ldr r3, [r7, #4] 800117c: 4413 add r3, r2 800117e: 227d movs r2, #125 ; 0x7d 8001180: 701a strb r2, [r3, #0] data[cnt++] = 0x5e; 8001182: 68fb ldr r3, [r7, #12] 8001184: 1c5a adds r2, r3, #1 8001186: 60fa str r2, [r7, #12] 8001188: 461a mov r2, r3 800118a: 687b ldr r3, [r7, #4] 800118c: 4413 add r3, r2 800118e: 225e movs r2, #94 ; 0x5e 8001190: 701a strb r2, [r3, #0] 8001192: e021 b.n 80011d8 } else if(data[i] == 0x7d){ 8001194: 68bb ldr r3, [r7, #8] 8001196: 687a ldr r2, [r7, #4] 8001198: 4413 add r3, r2 800119a: 781b ldrb r3, [r3, #0] 800119c: 2b7d cmp r3, #125 ; 0x7d 800119e: d110 bne.n 80011c2 data[cnt++] = 0x7d; 80011a0: 68fb ldr r3, [r7, #12] 80011a2: 1c5a adds r2, r3, #1 80011a4: 60fa str r2, [r7, #12] 80011a6: 461a mov r2, r3 80011a8: 687b ldr r3, [r7, #4] 80011aa: 4413 add r3, r2 80011ac: 227d movs r2, #125 ; 0x7d 80011ae: 701a strb r2, [r3, #0] data[cnt++] = 0x5d; 80011b0: 68fb ldr r3, [r7, #12] 80011b2: 1c5a adds r2, r3, #1 80011b4: 60fa str r2, [r7, #12] 80011b6: 461a mov r2, r3 80011b8: 687b ldr r3, [r7, #4] 80011ba: 4413 add r3, r2 80011bc: 225d movs r2, #93 ; 0x5d 80011be: 701a strb r2, [r3, #0] 80011c0: e00a b.n 80011d8 }else{ data[i++] = data[i]; 80011c2: 68bb ldr r3, [r7, #8] 80011c4: 687a ldr r2, [r7, #4] 80011c6: 441a add r2, r3 80011c8: 68bb ldr r3, [r7, #8] 80011ca: 1c59 adds r1, r3, #1 80011cc: 60b9 str r1, [r7, #8] 80011ce: 4619 mov r1, r3 80011d0: 687b ldr r3, [r7, #4] 80011d2: 440b add r3, r1 80011d4: 7812 ldrb r2, [r2, #0] 80011d6: 701a strb r2, [r3, #0] for(int i = cnt; i < 17; i++){ 80011d8: 68bb ldr r3, [r7, #8] 80011da: 3301 adds r3, #1 80011dc: 60bb str r3, [r7, #8] 80011de: 68bb ldr r3, [r7, #8] 80011e0: 2b10 cmp r3, #16 80011e2: ddc0 ble.n 8001166 } } } 80011e4: bf00 nop 80011e6: 3714 adds r7, #20 80011e8: 46bd mov sp, r7 80011ea: bc80 pop {r7} 80011ec: 4770 bx lr ... 080011f0 : void NessLab_Table_Frame_Set(uint8_t* data,uint8_t size,uint8_t mode){ 80011f0: b590 push {r4, r7, lr} 80011f2: b087 sub sp, #28 80011f4: af00 add r7, sp, #0 80011f6: 6078 str r0, [r7, #4] 80011f8: 460b mov r3, r1 80011fa: 70fb strb r3, [r7, #3] 80011fc: 4613 mov r3, r2 80011fe: 70bb strb r3, [r7, #2] uint32_t i = 0; 8001200: 2300 movs r3, #0 8001202: 617b str r3, [r7, #20] uint32_t CurrApiAddress = 0; 8001204: 2300 movs r3, #0 8001206: 60fb str r3, [r7, #12] CurrApiAddress = FLASH_USER_USE_START_ADDR; 8001208: 4b33 ldr r3, [pc, #204] ; (80012d8 ) 800120a: 60fb str r3, [r7, #12] uint8_t* Currdata = (uint8_t*)CurrApiAddress; 800120c: 68fb ldr r3, [r7, #12] 800120e: 60bb str r3, [r7, #8] uint8_t* pdata; data[i++] = 0x7E; 8001210: 697b ldr r3, [r7, #20] 8001212: 1c5a adds r2, r3, #1 8001214: 617a str r2, [r7, #20] 8001216: 687a ldr r2, [r7, #4] 8001218: 4413 add r3, r2 800121a: 227e movs r2, #126 ; 0x7e 800121c: 701a strb r2, [r3, #0] data[i++] = 0x7E; 800121e: 697b ldr r3, [r7, #20] 8001220: 1c5a adds r2, r3, #1 8001222: 617a str r2, [r7, #20] 8001224: 687a ldr r2, [r7, #4] 8001226: 4413 add r3, r2 8001228: 227e movs r2, #126 ; 0x7e 800122a: 701a strb r2, [r3, #0] data[i++] = mode;// ID 800122c: 697b ldr r3, [r7, #20] 800122e: 1c5a adds r2, r3, #1 8001230: 617a str r2, [r7, #20] 8001232: 687a ldr r2, [r7, #4] 8001234: 4413 add r3, r2 8001236: 78ba ldrb r2, [r7, #2] 8001238: 701a strb r2, [r3, #0] data[i++] = 0; // SEQ NUMBER 800123a: 697b ldr r3, [r7, #20] 800123c: 1c5a adds r2, r3, #1 800123e: 617a str r2, [r7, #20] 8001240: 687a ldr r2, [r7, #4] 8001242: 4413 add r3, r2 8001244: 2200 movs r2, #0 8001246: 701a strb r2, [r3, #0] data[i++] = 0; // SEQ NUMBER 8001248: 697b ldr r3, [r7, #20] 800124a: 1c5a adds r2, r3, #1 800124c: 617a str r2, [r7, #20] 800124e: 687a ldr r2, [r7, #4] 8001250: 4413 add r3, r2 8001252: 2200 movs r2, #0 8001254: 701a strb r2, [r3, #0] data[i++] = 0; // NessLab_Reserve0 8001256: 697b ldr r3, [r7, #20] 8001258: 1c5a adds r2, r3, #1 800125a: 617a str r2, [r7, #20] 800125c: 687a ldr r2, [r7, #4] 800125e: 4413 add r3, r2 8001260: 2200 movs r2, #0 8001262: 701a strb r2, [r3, #0] data[i++] = size; // Nesslab Size 8001264: 697b ldr r3, [r7, #20] 8001266: 1c5a adds r2, r3, #1 8001268: 617a str r2, [r7, #20] 800126a: 687a ldr r2, [r7, #4] 800126c: 4413 add r3, r2 800126e: 78fa ldrb r2, [r7, #3] 8001270: 701a strb r2, [r3, #0] // NessLab_TalbleFlash_Read(&data[NessLab_DataLength + 1],100); for(int a = 0; a < size; a++){ 8001272: 2300 movs r3, #0 8001274: 613b str r3, [r7, #16] 8001276: e00c b.n 8001292 data[i++] = Currdata[a]; 8001278: 693b ldr r3, [r7, #16] 800127a: 68ba ldr r2, [r7, #8] 800127c: 441a add r2, r3 800127e: 697b ldr r3, [r7, #20] 8001280: 1c59 adds r1, r3, #1 8001282: 6179 str r1, [r7, #20] 8001284: 6879 ldr r1, [r7, #4] 8001286: 440b add r3, r1 8001288: 7812 ldrb r2, [r2, #0] 800128a: 701a strb r2, [r3, #0] for(int a = 0; a < size; a++){ 800128c: 693b ldr r3, [r7, #16] 800128e: 3301 adds r3, #1 8001290: 613b str r3, [r7, #16] 8001292: 78fb ldrb r3, [r7, #3] 8001294: 693a ldr r2, [r7, #16] 8001296: 429a cmp r2, r3 8001298: dbee blt.n 8001278 // printf("%02x ",Currdata[i]); } data[i++] = NessLab_Checksum(&data[NessLab_MsgID0], 100 + 5); 800129a: 687b ldr r3, [r7, #4] 800129c: 1c98 adds r0, r3, #2 800129e: 697b ldr r3, [r7, #20] 80012a0: 1c5a adds r2, r3, #1 80012a2: 617a str r2, [r7, #20] 80012a4: 687a ldr r2, [r7, #4] 80012a6: 18d4 adds r4, r2, r3 80012a8: 2169 movs r1, #105 ; 0x69 80012aa: f000 f9d3 bl 8001654 80012ae: 4603 mov r3, r0 80012b0: 7023 strb r3, [r4, #0] /* Exception Header Tail Checksum */ data[i++] = 0x7E; 80012b2: 697b ldr r3, [r7, #20] 80012b4: 1c5a adds r2, r3, #1 80012b6: 617a str r2, [r7, #20] 80012b8: 687a ldr r2, [r7, #4] 80012ba: 4413 add r3, r2 80012bc: 227e movs r2, #126 ; 0x7e 80012be: 701a strb r2, [r3, #0] data[i++] = 0x7E; 80012c0: 697b ldr r3, [r7, #20] 80012c2: 1c5a adds r2, r3, #1 80012c4: 617a str r2, [r7, #20] 80012c6: 687a ldr r2, [r7, #4] 80012c8: 4413 add r3, r2 80012ca: 227e movs r2, #126 ; 0x7e 80012cc: 701a strb r2, [r3, #0] } 80012ce: bf00 nop 80012d0: 371c adds r7, #28 80012d2: 46bd mov sp, r7 80012d4: bd90 pop {r4, r7, pc} 80012d6: bf00 nop 80012d8: 0800ff38 .word 0x0800ff38 80012dc: 00000000 .word 0x00000000 080012e0 : * ADC 0 :DL TX * ADC 1 :DL RX * ADC 2 :TEMP * */ void ADC_Value_Get(){ 80012e0: b590 push {r4, r7, lr} 80012e2: b083 sub sp, #12 80012e4: af00 add r7, sp, #0 uint16_t CalcRet = 0 ; 80012e6: 2300 movs r3, #0 80012e8: 80fb strh r3, [r7, #6] uint16_t Tx_Det_Volt = ((ADC1value[0] * (3.3 / 4095))* 1000); 80012ea: 4b37 ldr r3, [pc, #220] ; (80013c8 ) 80012ec: 881b ldrh r3, [r3, #0] 80012ee: b29b uxth r3, r3 80012f0: 4618 mov r0, r3 80012f2: f7ff f8e7 bl 80004c4 <__aeabi_i2d> 80012f6: a332 add r3, pc, #200 ; (adr r3, 80013c0 ) 80012f8: e9d3 2300 ldrd r2, r3, [r3] 80012fc: f7ff f94c bl 8000598 <__aeabi_dmul> 8001300: 4603 mov r3, r0 8001302: 460c mov r4, r1 8001304: 4618 mov r0, r3 8001306: 4621 mov r1, r4 8001308: f04f 0200 mov.w r2, #0 800130c: 4b2f ldr r3, [pc, #188] ; (80013cc ) 800130e: f7ff f943 bl 8000598 <__aeabi_dmul> 8001312: 4603 mov r3, r0 8001314: 460c mov r4, r1 8001316: 4618 mov r0, r3 8001318: 4621 mov r1, r4 800131a: f7ff fc15 bl 8000b48 <__aeabi_d2uiz> 800131e: 4603 mov r3, r0 8001320: 80bb strh r3, [r7, #4] uint16_t Rx_Det_Volt = ((ADC1value[1] * (3.3 / 4095))* 1000); 8001322: 4b29 ldr r3, [pc, #164] ; (80013c8 ) 8001324: 885b ldrh r3, [r3, #2] 8001326: b29b uxth r3, r3 8001328: 4618 mov r0, r3 800132a: f7ff f8cb bl 80004c4 <__aeabi_i2d> 800132e: a324 add r3, pc, #144 ; (adr r3, 80013c0 ) 8001330: e9d3 2300 ldrd r2, r3, [r3] 8001334: f7ff f930 bl 8000598 <__aeabi_dmul> 8001338: 4603 mov r3, r0 800133a: 460c mov r4, r1 800133c: 4618 mov r0, r3 800133e: 4621 mov r1, r4 8001340: f04f 0200 mov.w r2, #0 8001344: 4b21 ldr r3, [pc, #132] ; (80013cc ) 8001346: f7ff f927 bl 8000598 <__aeabi_dmul> 800134a: 4603 mov r3, r0 800134c: 460c mov r4, r1 800134e: 4618 mov r0, r3 8001350: 4621 mov r1, r4 8001352: f7ff fbf9 bl 8000b48 <__aeabi_d2uiz> 8001356: 4603 mov r3, r0 8001358: 807b strh r3, [r7, #2] int8_t Real_Temperature = ADC_Convert_Temperature((ADC1value[2] * (3.3 / 4095))); 800135a: 4b1b ldr r3, [pc, #108] ; (80013c8 ) 800135c: 889b ldrh r3, [r3, #4] 800135e: b29b uxth r3, r3 8001360: 4618 mov r0, r3 8001362: f7ff f8af bl 80004c4 <__aeabi_i2d> 8001366: a316 add r3, pc, #88 ; (adr r3, 80013c0 ) 8001368: e9d3 2300 ldrd r2, r3, [r3] 800136c: f7ff f914 bl 8000598 <__aeabi_dmul> 8001370: 4603 mov r3, r0 8001372: 460c mov r4, r1 8001374: 4618 mov r0, r3 8001376: 4621 mov r1, r4 8001378: f000 f842 bl 8001400 800137c: 4603 mov r3, r0 800137e: 707b strb r3, [r7, #1] /*DL TX Calc*/ Currstatus.DownLink_Forward_Det_H = ((Tx_Det_Volt & 0xFF00) >> 8); 8001380: 88bb ldrh r3, [r7, #4] 8001382: 0a1b lsrs r3, r3, #8 8001384: b29b uxth r3, r3 8001386: b2da uxtb r2, r3 8001388: 4b11 ldr r3, [pc, #68] ; (80013d0 ) 800138a: 71da strb r2, [r3, #7] Currstatus.DownLink_Forward_Det_L = (Tx_Det_Volt & 0x00FF); 800138c: 88bb ldrh r3, [r7, #4] 800138e: b2da uxtb r2, r3 8001390: 4b0f ldr r3, [pc, #60] ; (80013d0 ) 8001392: 721a strb r2, [r3, #8] printf("Tx_Det_Volt : %d \r\n",Tx_Det_Volt); 8001394: 88bb ldrh r3, [r7, #4] 8001396: 4619 mov r1, r3 8001398: 480e ldr r0, [pc, #56] ; (80013d4 ) 800139a: f005 fa2b bl 80067f4 /*DL RX Calc*/ Currstatus.DownLink_Reverse_Det_H = ((Rx_Det_Volt & 0xFF00) >> 8); 800139e: 887b ldrh r3, [r7, #2] 80013a0: 0a1b lsrs r3, r3, #8 80013a2: b29b uxth r3, r3 80013a4: b2da uxtb r2, r3 80013a6: 4b0a ldr r3, [pc, #40] ; (80013d0 ) 80013a8: 725a strb r2, [r3, #9] Currstatus.DownLink_Reverse_Det_L = (Rx_Det_Volt & 0x00FF); 80013aa: 887b ldrh r3, [r7, #2] 80013ac: b2da uxtb r2, r3 80013ae: 4b08 ldr r3, [pc, #32] ; (80013d0 ) 80013b0: 729a strb r2, [r3, #10] /*Temp Calc*/ Currstatus.Temp_Monitor = Real_Temperature; 80013b2: 787a ldrb r2, [r7, #1] 80013b4: 4b06 ldr r3, [pc, #24] ; (80013d0 ) 80013b6: 745a strb r2, [r3, #17] } 80013b8: bf00 nop 80013ba: 370c adds r7, #12 80013bc: 46bd mov sp, r7 80013be: bd90 pop {r4, r7, pc} 80013c0: e734d9b4 .word 0xe734d9b4 80013c4: 3f4a680c .word 0x3f4a680c 80013c8: 200006c4 .word 0x200006c4 80013cc: 408f4000 .word 0x408f4000 80013d0: 200006ac .word 0x200006ac 80013d4: 0800889c .word 0x0800889c 080013d8 : void ADC_Initialize(){ 80013d8: b580 push {r7, lr} 80013da: af00 add r7, sp, #0 while(!(HAL_ADCEx_Calibration_Start(&hadc1)==HAL_OK)); 80013dc: bf00 nop 80013de: 4806 ldr r0, [pc, #24] ; (80013f8 ) 80013e0: f001 f8aa bl 8002538 80013e4: 4603 mov r3, r0 80013e6: 2b00 cmp r3, #0 80013e8: d1f9 bne.n 80013de HAL_ADC_Start_DMA(&hadc1, (uint16_t*)ADC1value,(uint32_t) 3); 80013ea: 2203 movs r2, #3 80013ec: 4903 ldr r1, [pc, #12] ; (80013fc ) 80013ee: 4802 ldr r0, [pc, #8] ; (80013f8 ) 80013f0: f000 fd40 bl 8001e74 } 80013f4: bf00 nop 80013f6: bd80 pop {r7, pc} 80013f8: 20000a1c .word 0x20000a1c 80013fc: 200006c4 .word 0x200006c4 08001400 : uint8_t ADC_Convert_Temperature(double val){ 8001400: b590 push {r4, r7, lr} 8001402: b087 sub sp, #28 8001404: af00 add r7, sp, #0 8001406: e9c7 0100 strd r0, r1, [r7] int16_t ref_0temp = 500; 800140a: f44f 73fa mov.w r3, #500 ; 0x1f4 800140e: 817b strh r3, [r7, #10] int16_t ret = val * 1000; 8001410: f04f 0200 mov.w r2, #0 8001414: 4b27 ldr r3, [pc, #156] ; (80014b4 ) 8001416: e9d7 0100 ldrd r0, r1, [r7] 800141a: f7ff f8bd bl 8000598 <__aeabi_dmul> 800141e: 4603 mov r3, r0 8001420: 460c mov r4, r1 8001422: 4618 mov r0, r3 8001424: 4621 mov r1, r4 8001426: f7ff fb67 bl 8000af8 <__aeabi_d2iz> 800142a: 4603 mov r3, r0 800142c: 813b strh r3, [r7, #8] int8_t cnt = 0; 800142e: 2300 movs r3, #0 8001430: 75fb strb r3, [r7, #23] printf("ret : %d \r\n", ret); 8001432: f9b7 3008 ldrsh.w r3, [r7, #8] 8001436: 4619 mov r1, r3 8001438: 481f ldr r0, [pc, #124] ; (80014b8 ) 800143a: f005 f9db bl 80067f4 if( ret - ref_0temp > 0){ 800143e: f9b7 2008 ldrsh.w r2, [r7, #8] 8001442: f9b7 300a ldrsh.w r3, [r7, #10] 8001446: 1ad3 subs r3, r2, r3 8001448: 2b00 cmp r3, #0 800144a: dd14 ble.n 8001476 for(int i = 0; i < ret - ref_0temp; i += 10){ 800144c: 2300 movs r3, #0 800144e: 613b str r3, [r7, #16] 8001450: e008 b.n 8001464 cnt++; 8001452: f997 3017 ldrsb.w r3, [r7, #23] 8001456: b2db uxtb r3, r3 8001458: 3301 adds r3, #1 800145a: b2db uxtb r3, r3 800145c: 75fb strb r3, [r7, #23] for(int i = 0; i < ret - ref_0temp; i += 10){ 800145e: 693b ldr r3, [r7, #16] 8001460: 330a adds r3, #10 8001462: 613b str r3, [r7, #16] 8001464: f9b7 2008 ldrsh.w r2, [r7, #8] 8001468: f9b7 300a ldrsh.w r3, [r7, #10] 800146c: 1ad3 subs r3, r2, r3 800146e: 693a ldr r2, [r7, #16] 8001470: 429a cmp r2, r3 8001472: dbee blt.n 8001452 8001474: e013 b.n 800149e } }else{ for(int i = 0; i > ret - ref_0temp; i -= 10){ 8001476: 2300 movs r3, #0 8001478: 60fb str r3, [r7, #12] 800147a: e008 b.n 800148e cnt--; 800147c: f997 3017 ldrsb.w r3, [r7, #23] 8001480: b2db uxtb r3, r3 8001482: 3b01 subs r3, #1 8001484: b2db uxtb r3, r3 8001486: 75fb strb r3, [r7, #23] for(int i = 0; i > ret - ref_0temp; i -= 10){ 8001488: 68fb ldr r3, [r7, #12] 800148a: 3b0a subs r3, #10 800148c: 60fb str r3, [r7, #12] 800148e: f9b7 2008 ldrsh.w r2, [r7, #8] 8001492: f9b7 300a ldrsh.w r3, [r7, #10] 8001496: 1ad3 subs r3, r2, r3 8001498: 68fa ldr r2, [r7, #12] 800149a: 429a cmp r2, r3 800149c: dcee bgt.n 800147c } } printf("Temp : %d\r\n",cnt); 800149e: f997 3017 ldrsb.w r3, [r7, #23] 80014a2: 4619 mov r1, r3 80014a4: 4805 ldr r0, [pc, #20] ; (80014bc ) 80014a6: f005 f9a5 bl 80067f4 return cnt; 80014aa: 7dfb ldrb r3, [r7, #23] } 80014ac: 4618 mov r0, r3 80014ae: 371c adds r7, #28 80014b0: 46bd mov sp, r7 80014b2: bd90 pop {r4, r7, pc} 80014b4: 408f4000 .word 0x408f4000 80014b8: 080088b0 .word 0x080088b0 80014bc: 080088bc .word 0x080088bc 080014c0 : } return ret; } void DascendigFunc(int32_t* src,uint32_t size ){ 80014c0: b480 push {r7} 80014c2: b087 sub sp, #28 80014c4: af00 add r7, sp, #0 80014c6: 6078 str r0, [r7, #4] 80014c8: 6039 str r1, [r7, #0] int32_t temp; for(int i = 0 ; i < size - 1 ; i ++) { 80014ca: 2300 movs r3, #0 80014cc: 617b str r3, [r7, #20] 80014ce: e02f b.n 8001530 for(int j = i+1 ; j < size ; j ++) { 80014d0: 697b ldr r3, [r7, #20] 80014d2: 3301 adds r3, #1 80014d4: 613b str r3, [r7, #16] 80014d6: e024 b.n 8001522 if(src[i] < src[j]) { 80014d8: 697b ldr r3, [r7, #20] 80014da: 009b lsls r3, r3, #2 80014dc: 687a ldr r2, [r7, #4] 80014de: 4413 add r3, r2 80014e0: 681a ldr r2, [r3, #0] 80014e2: 693b ldr r3, [r7, #16] 80014e4: 009b lsls r3, r3, #2 80014e6: 6879 ldr r1, [r7, #4] 80014e8: 440b add r3, r1 80014ea: 681b ldr r3, [r3, #0] 80014ec: 429a cmp r2, r3 80014ee: da15 bge.n 800151c temp = src[j]; 80014f0: 693b ldr r3, [r7, #16] 80014f2: 009b lsls r3, r3, #2 80014f4: 687a ldr r2, [r7, #4] 80014f6: 4413 add r3, r2 80014f8: 681b ldr r3, [r3, #0] 80014fa: 60fb str r3, [r7, #12] src[j] = src[i]; 80014fc: 697b ldr r3, [r7, #20] 80014fe: 009b lsls r3, r3, #2 8001500: 687a ldr r2, [r7, #4] 8001502: 441a add r2, r3 8001504: 693b ldr r3, [r7, #16] 8001506: 009b lsls r3, r3, #2 8001508: 6879 ldr r1, [r7, #4] 800150a: 440b add r3, r1 800150c: 6812 ldr r2, [r2, #0] 800150e: 601a str r2, [r3, #0] src[i] = temp; 8001510: 697b ldr r3, [r7, #20] 8001512: 009b lsls r3, r3, #2 8001514: 687a ldr r2, [r7, #4] 8001516: 4413 add r3, r2 8001518: 68fa ldr r2, [r7, #12] 800151a: 601a str r2, [r3, #0] for(int j = i+1 ; j < size ; j ++) { 800151c: 693b ldr r3, [r7, #16] 800151e: 3301 adds r3, #1 8001520: 613b str r3, [r7, #16] 8001522: 693b ldr r3, [r7, #16] 8001524: 683a ldr r2, [r7, #0] 8001526: 429a cmp r2, r3 8001528: d8d6 bhi.n 80014d8 for(int i = 0 ; i < size - 1 ; i ++) { 800152a: 697b ldr r3, [r7, #20] 800152c: 3301 adds r3, #1 800152e: 617b str r3, [r7, #20] 8001530: 683b ldr r3, [r7, #0] 8001532: 1e5a subs r2, r3, #1 8001534: 697b ldr r3, [r7, #20] 8001536: 429a cmp r2, r3 8001538: d8ca bhi.n 80014d0 // printf("temp"); } } } } 800153a: bf00 nop 800153c: 371c adds r7, #28 800153e: 46bd mov sp, r7 8001540: bc80 pop {r7} 8001542: 4770 bx lr 08001544 : #define Percent100 5 void ADC_Check(){ 8001544: b580 push {r7, lr} 8001546: b082 sub sp, #8 8001548: af00 add r7, sp, #0 float tempval = 0; 800154a: f04f 0300 mov.w r3, #0 800154e: 603b str r3, [r7, #0] for(int i = 0; i < 3 ; i++) 8001550: 2300 movs r3, #0 8001552: 607b str r3, [r7, #4] 8001554: e00c b.n 8001570 printf("ADC1value[%d] : %d \r\n",i,ADC1value[i]); 8001556: 4a0b ldr r2, [pc, #44] ; (8001584 ) 8001558: 687b ldr r3, [r7, #4] 800155a: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 800155e: b29b uxth r3, r3 8001560: 461a mov r2, r3 8001562: 6879 ldr r1, [r7, #4] 8001564: 4808 ldr r0, [pc, #32] ; (8001588 ) 8001566: f005 f945 bl 80067f4 for(int i = 0; i < 3 ; i++) 800156a: 687b ldr r3, [r7, #4] 800156c: 3301 adds r3, #1 800156e: 607b str r3, [r7, #4] 8001570: 687b ldr r3, [r7, #4] 8001572: 2b02 cmp r3, #2 8001574: ddef ble.n 8001556 Currstatus.DownLink_Forward_Det_H = (((uint16_t)tempval & 0xFF00) >> 8); Currstatus.DownLink_Forward_Det_L = (((uint16_t)tempval & 0x00FF) ); #endif // PYJ.2020.09.09_END -- ADC_Value_Get(); 8001576: f7ff feb3 bl 80012e0 // Currstatus.Temp_Monitor = ADC_Convert_Temperature((ADC1value[2]/1000)); // printf("Currstatus.DownLink_Forward_Det : %d \r\n",Currstatus.DownLink_Forward_Det_H << 8 | Currstatus.DownLink_Forward_Det_L); } 800157a: bf00 nop 800157c: 3708 adds r7, #8 800157e: 46bd mov sp, r7 8001580: bd80 pop {r7, pc} 8001582: bf00 nop 8001584: 200006c4 .word 0x200006c4 8001588: 080088c8 .word 0x080088c8 0800158c : } } void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) { 800158c: b580 push {r7, lr} 800158e: b084 sub sp, #16 8001590: af00 add r7, sp, #0 8001592: 6078 str r0, [r7, #4] if(hadc->Instance == hadc1.Instance && TDD_125ms_Cnt < 125) 8001594: 687b ldr r3, [r7, #4] 8001596: 681a ldr r2, [r3, #0] 8001598: 4b27 ldr r3, [pc, #156] ; (8001638 ) 800159a: 681b ldr r3, [r3, #0] 800159c: 429a cmp r2, r3 800159e: d147 bne.n 8001630 80015a0: 4b26 ldr r3, [pc, #152] ; (800163c ) 80015a2: 681b ldr r3, [r3, #0] 80015a4: 2b7c cmp r3, #124 ; 0x7c 80015a6: d843 bhi.n 8001630 { ADC1_Arrage[adc1cnt] = ADC1value[0]; 80015a8: 4b25 ldr r3, [pc, #148] ; (8001640 ) 80015aa: 881b ldrh r3, [r3, #0] 80015ac: 461a mov r2, r3 80015ae: 4b25 ldr r3, [pc, #148] ; (8001644 ) 80015b0: 881b ldrh r3, [r3, #0] 80015b2: b299 uxth r1, r3 80015b4: 4b24 ldr r3, [pc, #144] ; (8001648 ) 80015b6: f823 1012 strh.w r1, [r3, r2, lsl #1] // for(int i = 0; i < 2; i++){ // printf("ADC1value[%d] : %d , %f\r\n",i,ADC1value[i],(float)((ADC1value[i]) *3.3 /4095)); // } adc1cnt++; 80015ba: 4b21 ldr r3, [pc, #132] ; (8001640 ) 80015bc: 881b ldrh r3, [r3, #0] 80015be: 3301 adds r3, #1 80015c0: b29a uxth r2, r3 80015c2: 4b1f ldr r3, [pc, #124] ; (8001640 ) 80015c4: 801a strh r2, [r3, #0] if(adc1cnt == ADC_AVERAGECNT){ 80015c6: 4b1e ldr r3, [pc, #120] ; (8001640 ) 80015c8: 881b ldrh r3, [r3, #0] 80015ca: 2b64 cmp r3, #100 ; 0x64 80015cc: d130 bne.n 8001630 // DascendigFunc(&ADC1_Arrage[0],ADC_AVERAGECNT); adc1cnt = 0; 80015ce: 4b1c ldr r3, [pc, #112] ; (8001640 ) 80015d0: 2200 movs r2, #0 80015d2: 801a strh r2, [r3, #0] TotalCnt++; 80015d4: 4b1d ldr r3, [pc, #116] ; (800164c ) 80015d6: 681b ldr r3, [r3, #0] 80015d8: 3301 adds r3, #1 80015da: 4a1c ldr r2, [pc, #112] ; (800164c ) 80015dc: 6013 str r3, [r2, #0] if(TotalCnt > 2) 80015de: 4b1b ldr r3, [pc, #108] ; (800164c ) 80015e0: 681b ldr r3, [r3, #0] 80015e2: 2b02 cmp r3, #2 80015e4: d902 bls.n 80015ec TotalCnt = 2; 80015e6: 4b19 ldr r3, [pc, #100] ; (800164c ) 80015e8: 2202 movs r2, #2 80015ea: 601a str r2, [r3, #0] for(int i = 0; i < 100; i++){/*ADC Data Dascending Complete*/ 80015ec: 2300 movs r3, #0 80015ee: 60fb str r3, [r7, #12] 80015f0: e017 b.n 8001622 if(ADC1_Arrage_Ret[i] <= ADC1_Arrage[i]) 80015f2: 4a17 ldr r2, [pc, #92] ; (8001650 ) 80015f4: 68fb ldr r3, [r7, #12] 80015f6: f852 3023 ldr.w r3, [r2, r3, lsl #2] 80015fa: 4913 ldr r1, [pc, #76] ; (8001648 ) 80015fc: 68fa ldr r2, [r7, #12] 80015fe: f831 2012 ldrh.w r2, [r1, r2, lsl #1] 8001602: b292 uxth r2, r2 8001604: 4293 cmp r3, r2 8001606: d809 bhi.n 800161c ADC1_Arrage_Ret[i] = ADC1_Arrage[i]; 8001608: 4a0f ldr r2, [pc, #60] ; (8001648 ) 800160a: 68fb ldr r3, [r7, #12] 800160c: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8001610: b29b uxth r3, r3 8001612: 4619 mov r1, r3 8001614: 4a0e ldr r2, [pc, #56] ; (8001650 ) 8001616: 68fb ldr r3, [r7, #12] 8001618: f842 1023 str.w r1, [r2, r3, lsl #2] for(int i = 0; i < 100; i++){/*ADC Data Dascending Complete*/ 800161c: 68fb ldr r3, [r7, #12] 800161e: 3301 adds r3, #1 8001620: 60fb str r3, [r7, #12] 8001622: 68fb ldr r3, [r7, #12] 8001624: 2b63 cmp r3, #99 ; 0x63 8001626: dde4 ble.n 80015f2 } DascendigFunc(&ADC1_Arrage_Ret[0],ADC_AVERAGECNT); 8001628: 2164 movs r1, #100 ; 0x64 800162a: 4809 ldr r0, [pc, #36] ; (8001650 ) 800162c: f7ff ff48 bl 80014c0 // ADC1valuearray[i][adc1cnt] = ADC1value[i]; // } // adc1cnt++; // } } } 8001630: bf00 nop 8001632: 3710 adds r7, #16 8001634: 46bd mov sp, r7 8001636: bd80 pop {r7, pc} 8001638: 20000a1c .word 0x20000a1c 800163c: 20000634 .word 0x20000634 8001640: 200005e8 .word 0x200005e8 8001644: 200006c4 .word 0x200006c4 8001648: 20000390 .word 0x20000390 800164c: 200005ec .word 0x200005ec 8001650: 20000458 .word 0x20000458 08001654 : crcret ^ ~0U; return (crcret == checksum ? CHECKSUM_ERROR : NO_ERROR); } uint8_t NessLab_Checksum(uint8_t *data,uint8_t size){ 8001654: b480 push {r7} 8001656: b085 sub sp, #20 8001658: af00 add r7, sp, #0 800165a: 6078 str r0, [r7, #4] 800165c: 460b mov r3, r1 800165e: 70fb strb r3, [r7, #3] uint16_t ret = 0; 8001660: 2300 movs r3, #0 8001662: 81fb strh r3, [r7, #14] // printf("Crc Process : "); for(int i = 0; i < size; i++){ 8001664: 2300 movs r3, #0 8001666: 60bb str r3, [r7, #8] 8001668: e00c b.n 8001684 ret = ((ret + data[i]) & 0xFF); 800166a: 68bb ldr r3, [r7, #8] 800166c: 687a ldr r2, [r7, #4] 800166e: 4413 add r3, r2 8001670: 781b ldrb r3, [r3, #0] 8001672: b29a uxth r2, r3 8001674: 89fb ldrh r3, [r7, #14] 8001676: 4413 add r3, r2 8001678: b29b uxth r3, r3 800167a: b2db uxtb r3, r3 800167c: 81fb strh r3, [r7, #14] for(int i = 0; i < size; i++){ 800167e: 68bb ldr r3, [r7, #8] 8001680: 3301 adds r3, #1 8001682: 60bb str r3, [r7, #8] 8001684: 78fb ldrb r3, [r7, #3] 8001686: 68ba ldr r2, [r7, #8] 8001688: 429a cmp r2, r3 800168a: dbee blt.n 800166a // printf(" %x + %x \r\n",ret,data[i]); } // printf("Result : "); ret = (~ret) + 1; 800168c: 89fb ldrh r3, [r7, #14] 800168e: 425b negs r3, r3 8001690: 81fb strh r3, [r7, #14] // printf("ret [i] : %x \r\n",ret); return (uint8_t)(ret & 0x00FF); 8001692: 89fb ldrh r3, [r7, #14] 8001694: b2db uxtb r3, r3 } 8001696: 4618 mov r0, r3 8001698: 3714 adds r7, #20 800169a: 46bd mov sp, r7 800169c: bc80 pop {r7} 800169e: 4770 bx lr 080016a0 : bool NessLab_CheckSum_Check(uint8_t* data,uint8_t size,uint8_t checksum){ 80016a0: b580 push {r7, lr} 80016a2: b084 sub sp, #16 80016a4: af00 add r7, sp, #0 80016a6: 6078 str r0, [r7, #4] 80016a8: 460b mov r3, r1 80016aa: 70fb strb r3, [r7, #3] 80016ac: 4613 mov r3, r2 80016ae: 70bb strb r3, [r7, #2] uint8_t dataret = 0; 80016b0: 2300 movs r3, #0 80016b2: 73fb strb r3, [r7, #15] bool ret = false; 80016b4: 2300 movs r3, #0 80016b6: 73bb strb r3, [r7, #14] // printf("size : %d \r\n",size); for(int i = 0; i < size; i++){ 80016b8: 2300 movs r3, #0 80016ba: 60bb str r3, [r7, #8] 80016bc: e009 b.n 80016d2 dataret += data[i]; 80016be: 68bb ldr r3, [r7, #8] 80016c0: 687a ldr r2, [r7, #4] 80016c2: 4413 add r3, r2 80016c4: 781a ldrb r2, [r3, #0] 80016c6: 7bfb ldrb r3, [r7, #15] 80016c8: 4413 add r3, r2 80016ca: 73fb strb r3, [r7, #15] for(int i = 0; i < size; i++){ 80016cc: 68bb ldr r3, [r7, #8] 80016ce: 3301 adds r3, #1 80016d0: 60bb str r3, [r7, #8] 80016d2: 78fb ldrb r3, [r7, #3] 80016d4: 68ba ldr r2, [r7, #8] 80016d6: 429a cmp r2, r3 80016d8: dbf1 blt.n 80016be // printf("data [i] : %x \r\n",data[i]); } dataret = (~dataret) + 1; 80016da: 7bfb ldrb r3, [r7, #15] 80016dc: 425b negs r3, r3 80016de: 73fb strb r3, [r7, #15] printf("\r\ndataret : %x /// checksum : %x \r\n",dataret,checksum); 80016e0: 7bfb ldrb r3, [r7, #15] 80016e2: 78ba ldrb r2, [r7, #2] 80016e4: 4619 mov r1, r3 80016e6: 4808 ldr r0, [pc, #32] ; (8001708 ) 80016e8: f005 f884 bl 80067f4 if(dataret != checksum){ 80016ec: 7bfa ldrb r2, [r7, #15] 80016ee: 78bb ldrb r3, [r7, #2] 80016f0: 429a cmp r2, r3 80016f2: d002 beq.n 80016fa ret = false; 80016f4: 2300 movs r3, #0 80016f6: 73bb strb r3, [r7, #14] 80016f8: e001 b.n 80016fe }else{ ret = true; 80016fa: 2301 movs r3, #1 80016fc: 73bb strb r3, [r7, #14] } return ret; 80016fe: 7bbb ldrb r3, [r7, #14] } 8001700: 4618 mov r0, r3 8001702: 3710 adds r7, #16 8001704: 46bd mov sp, r7 8001706: bd80 pop {r7, pc} 8001708: 080088e0 .word 0x080088e0 0800170c : __set_MSP(*(__IO uint32_t*) APPLICATION_ADDRESS); jump_to_app(); } bool EraseInit = false; void DataErase_Func(uint32_t User_Address,uint32_t size){ 800170c: b580 push {r7, lr} 800170e: b082 sub sp, #8 8001710: af00 add r7, sp, #0 8001712: 6078 str r0, [r7, #4] 8001714: 6039 str r1, [r7, #0] static FLASH_EraseInitTypeDef EraseInitStruct; static uint32_t PAGEError = 0; HAL_FLASH_Unlock(); 8001716: f001 fb69 bl 8002dec EraseInitStruct.TypeErase = FLASH_TYPEERASE_PAGES; 800171a: 4b1b ldr r3, [pc, #108] ; (8001788 ) 800171c: 2200 movs r2, #0 800171e: 601a str r2, [r3, #0] EraseInitStruct.PageAddress = FLASH_USER_USE_START_ADDR; 8001720: 4b19 ldr r3, [pc, #100] ; (8001788 ) 8001722: 4a1a ldr r2, [pc, #104] ; (800178c ) 8001724: 609a str r2, [r3, #8] EraseInitStruct.NbPages = ((FLASH_USER_END_ADDR - FLASH_USER_USE_START_ADDR) / FLASH_PAGE_SIZE) + 1; 8001726: 4b18 ldr r3, [pc, #96] ; (8001788 ) 8001728: 2201 movs r2, #1 800172a: 60da str r2, [r3, #12] UserAddress = User_Address; 800172c: 4a18 ldr r2, [pc, #96] ; (8001790 ) 800172e: 687b ldr r3, [r7, #4] 8001730: 6013 str r3, [r2, #0] printf("NbPages : %x \r\n",EraseInitStruct.NbPages ); 8001732: 4b15 ldr r3, [pc, #84] ; (8001788 ) 8001734: 68db ldr r3, [r3, #12] 8001736: 4619 mov r1, r3 8001738: 4816 ldr r0, [pc, #88] ; (8001794 ) 800173a: f005 f85b bl 80067f4 printf("EraseInitStruct.PageAddress : %x \r\n",EraseInitStruct.PageAddress); 800173e: 4b12 ldr r3, [pc, #72] ; (8001788 ) 8001740: 689b ldr r3, [r3, #8] 8001742: 4619 mov r1, r3 8001744: 4814 ldr r0, [pc, #80] ; (8001798 ) 8001746: f005 f855 bl 80067f4 printf("Erase Start\r\n"); 800174a: 4814 ldr r0, [pc, #80] ; (800179c ) 800174c: f005 f8c6 bl 80068dc if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK) 8001750: 4913 ldr r1, [pc, #76] ; (80017a0 ) 8001752: 480d ldr r0, [pc, #52] ; (8001788 ) 8001754: f001 fc32 bl 8002fbc 8001758: 4603 mov r3, r0 800175a: 2b00 cmp r3, #0 800175c: d007 beq.n 800176e */ /* Infinite loop */ while (1) { /* Make LED2 blink (100ms on, 2s off) to indicate error in Erase operation */ printf("HAL_FLASHEx_Erase Error\r\n"); 800175e: 4811 ldr r0, [pc, #68] ; (80017a4 ) 8001760: f005 f8bc bl 80068dc HAL_Delay(2000); 8001764: f44f 60fa mov.w r0, #2000 ; 0x7d0 8001768: f000 fa8a bl 8001c80 printf("HAL_FLASHEx_Erase Error\r\n"); 800176c: e7f7 b.n 800175e } } EraseInit = true; 800176e: 4b0e ldr r3, [pc, #56] ; (80017a8 ) 8001770: 2201 movs r2, #1 8001772: 701a strb r2, [r3, #0] printf("Erase End\r\n"); 8001774: 480d ldr r0, [pc, #52] ; (80017ac ) 8001776: f005 f8b1 bl 80068dc HAL_FLASH_Lock(); 800177a: f001 fb5d bl 8002e38 } 800177e: bf00 nop 8001780: 3708 adds r7, #8 8001782: 46bd mov sp, r7 8001784: bd80 pop {r7, pc} 8001786: bf00 nop 8001788: 200005f8 .word 0x200005f8 800178c: 0800ff38 .word 0x0800ff38 8001790: 200005f0 .word 0x200005f0 8001794: 08008920 .word 0x08008920 8001798: 08008930 .word 0x08008930 800179c: 08008954 .word 0x08008954 80017a0: 20000608 .word 0x20000608 80017a4: 08008964 .word 0x08008964 80017a8: 200005f4 .word 0x200005f4 80017ac: 08008980 .word 0x08008980 080017b0 : uint8_t FLASH_Write_Func(uint32_t User_Address,uint8_t* data,uint32_t size){ 80017b0: b590 push {r4, r7, lr} 80017b2: b08b sub sp, #44 ; 0x2c 80017b4: af00 add r7, sp, #0 80017b6: 60f8 str r0, [r7, #12] 80017b8: 60b9 str r1, [r7, #8] 80017ba: 607a str r2, [r7, #4] //static FLASH_EraseInitTypeDef EraseInitStruct; //static uint32_t PAGEError = 0; static uint32_t DownloadIndex; static __IO uint32_t data32 = 0 , MemoryProgramStatus = 0; int dataindex = 0; 80017bc: 2300 movs r3, #0 80017be: 623b str r3, [r7, #32] uint32_t writedata = 0; 80017c0: 2300 movs r3, #0 80017c2: 61fb str r3, [r7, #28] uint32_t CurrApiAddress = 0; 80017c4: 2300 movs r3, #0 80017c6: 61bb str r3, [r7, #24] uint8_t ret = 0; 80017c8: 2300 movs r3, #0 80017ca: 75fb strb r3, [r7, #23] CurrApiAddress = User_Address; 80017cc: 68fb ldr r3, [r7, #12] 80017ce: 61bb str r3, [r7, #24] uint8_t* Currdata = (uint8_t*)CurrApiAddress; 80017d0: 69bb ldr r3, [r7, #24] 80017d2: 613b str r3, [r7, #16] printf("HAL_FLASH_Program Start\r\n"); 80017d4: 4833 ldr r0, [pc, #204] ; (80018a4 ) 80017d6: f005 f881 bl 80068dc DownloadIndex += size; 80017da: 4b33 ldr r3, [pc, #204] ; (80018a8 ) 80017dc: 681a ldr r2, [r3, #0] 80017de: 687b ldr r3, [r7, #4] 80017e0: 4413 add r3, r2 80017e2: 4a31 ldr r2, [pc, #196] ; (80018a8 ) 80017e4: 6013 str r3, [r2, #0] printf("User_Address : %x \r\n",UserAddress); 80017e6: 4b31 ldr r3, [pc, #196] ; (80018ac ) 80017e8: 681b ldr r3, [r3, #0] 80017ea: 4619 mov r1, r3 80017ec: 4830 ldr r0, [pc, #192] ; (80018b0 ) 80017ee: f005 f801 bl 80067f4 HAL_FLASH_Unlock(); 80017f2: f001 fafb bl 8002dec for(int downindex = 0; downindex < size; downindex+=4) 80017f6: 2300 movs r3, #0 80017f8: 627b str r3, [r7, #36] ; 0x24 80017fa: e041 b.n 8001880 { writedata = data[downindex + 0] ; 80017fc: 6a7b ldr r3, [r7, #36] ; 0x24 80017fe: 68ba ldr r2, [r7, #8] 8001800: 4413 add r3, r2 8001802: 781b ldrb r3, [r3, #0] 8001804: 61fb str r3, [r7, #28] writedata += data[downindex + 1] << 8 ; 8001806: 6a7b ldr r3, [r7, #36] ; 0x24 8001808: 3301 adds r3, #1 800180a: 68ba ldr r2, [r7, #8] 800180c: 4413 add r3, r2 800180e: 781b ldrb r3, [r3, #0] 8001810: 021b lsls r3, r3, #8 8001812: 461a mov r2, r3 8001814: 69fb ldr r3, [r7, #28] 8001816: 4413 add r3, r2 8001818: 61fb str r3, [r7, #28] writedata += data[downindex + 2] << 16; 800181a: 6a7b ldr r3, [r7, #36] ; 0x24 800181c: 3302 adds r3, #2 800181e: 68ba ldr r2, [r7, #8] 8001820: 4413 add r3, r2 8001822: 781b ldrb r3, [r3, #0] 8001824: 041b lsls r3, r3, #16 8001826: 461a mov r2, r3 8001828: 69fb ldr r3, [r7, #28] 800182a: 4413 add r3, r2 800182c: 61fb str r3, [r7, #28] writedata += data[downindex + 3] << 24; 800182e: 6a7b ldr r3, [r7, #36] ; 0x24 8001830: 3303 adds r3, #3 8001832: 68ba ldr r2, [r7, #8] 8001834: 4413 add r3, r2 8001836: 781b ldrb r3, [r3, #0] 8001838: 061b lsls r3, r3, #24 800183a: 461a mov r2, r3 800183c: 69fb ldr r3, [r7, #28] 800183e: 4413 add r3, r2 8001840: 61fb str r3, [r7, #28] if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, UserAddress,writedata) == HAL_OK) 8001842: 4b1a ldr r3, [pc, #104] ; (80018ac ) 8001844: 6819 ldr r1, [r3, #0] 8001846: 69fb ldr r3, [r7, #28] 8001848: f04f 0400 mov.w r4, #0 800184c: 461a mov r2, r3 800184e: 4623 mov r3, r4 8001850: 2002 movs r0, #2 8001852: f001 fa5b bl 8002d0c 8001856: 4603 mov r3, r0 8001858: 2b00 cmp r3, #0 800185a: d105 bne.n 8001868 { UserAddress += 4; 800185c: 4b13 ldr r3, [pc, #76] ; (80018ac ) 800185e: 681b ldr r3, [r3, #0] 8001860: 3304 adds r3, #4 8001862: 4a12 ldr r2, [pc, #72] ; (80018ac ) 8001864: 6013 str r3, [r2, #0] 8001866: e008 b.n 800187a } else { printf("HAL_FLASH_Program Error\r\n"); 8001868: 4812 ldr r0, [pc, #72] ; (80018b4 ) 800186a: f005 f837 bl 80068dc printf("Flash Failed %x \r\n",UserAddress); 800186e: 4b0f ldr r3, [pc, #60] ; (80018ac ) 8001870: 681b ldr r3, [r3, #0] 8001872: 4619 mov r1, r3 8001874: 4810 ldr r0, [pc, #64] ; (80018b8 ) 8001876: f004 ffbd bl 80067f4 for(int downindex = 0; downindex < size; downindex+=4) 800187a: 6a7b ldr r3, [r7, #36] ; 0x24 800187c: 3304 adds r3, #4 800187e: 627b str r3, [r7, #36] ; 0x24 8001880: 6a7b ldr r3, [r7, #36] ; 0x24 8001882: 687a ldr r2, [r7, #4] 8001884: 429a cmp r2, r3 8001886: d8b9 bhi.n 80017fc } } printf("HAL_FLASH_Program END %x \r\n",UserAddress); 8001888: 4b08 ldr r3, [pc, #32] ; (80018ac ) 800188a: 681b ldr r3, [r3, #0] 800188c: 4619 mov r1, r3 800188e: 480b ldr r0, [pc, #44] ; (80018bc ) 8001890: f004 ffb0 bl 80067f4 /* Lock the Flash to disable the flash control register access (recommended to protect the FLASH memory against possible unwanted operation) *********/ HAL_FLASH_Lock(); 8001894: f001 fad0 bl 8002e38 return 0; 8001898: 2300 movs r3, #0 /* Check if the programmed data is OK MemoryProgramStatus = 0: data programmed correctly MemoryProgramStatus != 0: number of words not programmed correctly ******/ } 800189a: 4618 mov r0, r3 800189c: 372c adds r7, #44 ; 0x2c 800189e: 46bd mov sp, r7 80018a0: bd90 pop {r4, r7, pc} 80018a2: bf00 nop 80018a4: 0800898c .word 0x0800898c 80018a8: 2000060c .word 0x2000060c 80018ac: 200005f0 .word 0x200005f0 80018b0: 080089a8 .word 0x080089a8 80018b4: 080089c0 .word 0x080089c0 80018b8: 080089dc .word 0x080089dc 80018bc: 080089f0 .word 0x080089f0 080018c0 : void FLASH_Read_Func(uint32_t User_Address,uint8_t* dst,uint32_t size){ 80018c0: b580 push {r7, lr} 80018c2: b088 sub sp, #32 80018c4: af00 add r7, sp, #0 80018c6: 60f8 str r0, [r7, #12] 80018c8: 60b9 str r1, [r7, #8] 80018ca: 607a str r2, [r7, #4] uint32_t CurrApiAddress = 0; 80018cc: 2300 movs r3, #0 80018ce: 61bb str r3, [r7, #24] uint32_t i = 0; 80018d0: 2300 movs r3, #0 80018d2: 617b str r3, [r7, #20] //uint8_t ret = 0; CurrApiAddress = User_Address; 80018d4: 68fb ldr r3, [r7, #12] 80018d6: 61bb str r3, [r7, #24] uint8_t* Currdata = (uint8_t*)CurrApiAddress; 80018d8: 69bb ldr r3, [r7, #24] 80018da: 613b str r3, [r7, #16] printf("Flash Read size : %d \r\n",size); 80018dc: 6879 ldr r1, [r7, #4] 80018de: 4810 ldr r0, [pc, #64] ; (8001920 ) 80018e0: f004 ff88 bl 80067f4 for(int i = 0; i < size; i++){ 80018e4: 2300 movs r3, #0 80018e6: 61fb str r3, [r7, #28] 80018e8: e012 b.n 8001910 dst[i] = Currdata[i]; 80018ea: 69fb ldr r3, [r7, #28] 80018ec: 693a ldr r2, [r7, #16] 80018ee: 441a add r2, r3 80018f0: 69fb ldr r3, [r7, #28] 80018f2: 68b9 ldr r1, [r7, #8] 80018f4: 440b add r3, r1 80018f6: 7812 ldrb r2, [r2, #0] 80018f8: 701a strb r2, [r3, #0] printf("%02x ",dst[i]); 80018fa: 69fb ldr r3, [r7, #28] 80018fc: 68ba ldr r2, [r7, #8] 80018fe: 4413 add r3, r2 8001900: 781b ldrb r3, [r3, #0] 8001902: 4619 mov r1, r3 8001904: 4807 ldr r0, [pc, #28] ; (8001924 ) 8001906: f004 ff75 bl 80067f4 for(int i = 0; i < size; i++){ 800190a: 69fb ldr r3, [r7, #28] 800190c: 3301 adds r3, #1 800190e: 61fb str r3, [r7, #28] 8001910: 69fb ldr r3, [r7, #28] 8001912: 687a ldr r2, [r7, #4] 8001914: 429a cmp r2, r3 8001916: d8e8 bhi.n 80018ea } } 8001918: bf00 nop 800191a: 3720 adds r7, #32 800191c: 46bd mov sp, r7 800191e: bd80 pop {r7, pc} 8001920: 08008a10 .word 0x08008a10 8001924: 08008a28 .word 0x08008a28 08001928 : #include "main.h" #include "led.h" volatile uint32_t LED_TimerCnt = 0; uint32_t LedTimerCnt_Get(){ 8001928: b480 push {r7} 800192a: af00 add r7, sp, #0 return LED_TimerCnt; 800192c: 4b02 ldr r3, [pc, #8] ; (8001938 ) 800192e: 681b ldr r3, [r3, #0] } 8001930: 4618 mov r0, r3 8001932: 46bd mov sp, r7 8001934: bc80 pop {r7} 8001936: 4770 bx lr 8001938: 20000610 .word 0x20000610 0800193c : void LedTimerCnt_Set(uint32_t val){ 800193c: b480 push {r7} 800193e: b083 sub sp, #12 8001940: af00 add r7, sp, #0 8001942: 6078 str r0, [r7, #4] LED_TimerCnt = val; 8001944: 4a03 ldr r2, [pc, #12] ; (8001954 ) 8001946: 687b ldr r3, [r7, #4] 8001948: 6013 str r3, [r2, #0] } 800194a: bf00 nop 800194c: 370c adds r7, #12 800194e: 46bd mov sp, r7 8001950: bc80 pop {r7} 8001952: 4770 bx lr 8001954: 20000610 .word 0x20000610 08001958 : void Boot_LED_Toggle(){ /*LED Check*/ 8001958: b580 push {r7, lr} 800195a: b082 sub sp, #8 800195c: af00 add r7, sp, #0 uint32_t Led_Cnt = LedTimerCnt_Get(); 800195e: f7ff ffe3 bl 8001928 8001962: 6078 str r0, [r7, #4] if(Led_Cnt >= LED_TOGGLE_CNT_REF){ 8001964: 687b ldr r3, [r7, #4] 8001966: f5b3 7ffa cmp.w r3, #500 ; 0x1f4 800196a: d307 bcc.n 800197c HAL_GPIO_TogglePin(BOOT_LED_GPIO_Port, BOOT_LED_Pin); 800196c: f44f 4100 mov.w r1, #32768 ; 0x8000 8001970: 4804 ldr r0, [pc, #16] ; (8001984 ) 8001972: f001 fd54 bl 800341e LedTimerCnt_Set(0); 8001976: 2000 movs r0, #0 8001978: f7ff ffe0 bl 800193c } } 800197c: bf00 nop 800197e: 3708 adds r7, #8 8001980: 46bd mov sp, r7 8001982: bd80 pop {r7, pc} 8001984: 40011000 .word 0x40011000 08001988 : extern bool Bluecell_Operate(uint8_t* data); extern void MBIC_Operate(uint8_t * data); extern bool NessLab_CheckSum_Check(uint8_t* data,uint8_t size,uint8_t checksum); void InitUartQueue(pUARTQUEUE pQueue) { 8001988: b580 push {r7, lr} 800198a: b082 sub sp, #8 800198c: af00 add r7, sp, #0 800198e: 6078 str r0, [r7, #4] pQueue->data = pQueue->head = pQueue->tail = 0; 8001990: 687b ldr r3, [r7, #4] 8001992: 2200 movs r2, #0 8001994: 605a str r2, [r3, #4] 8001996: 687b ldr r3, [r7, #4] 8001998: 685a ldr r2, [r3, #4] 800199a: 687b ldr r3, [r7, #4] 800199c: 601a str r2, [r3, #0] 800199e: 687b ldr r3, [r7, #4] 80019a0: 681a ldr r2, [r3, #0] 80019a2: 687b ldr r3, [r7, #4] 80019a4: 609a str r2, [r3, #8] uart_hal_tx.output_p = uart_hal_tx.input_p = 0; 80019a6: 2100 movs r1, #0 80019a8: 4b08 ldr r3, [pc, #32] ; (80019cc ) 80019aa: 460a mov r2, r1 80019ac: f8a3 2080 strh.w r2, [r3, #128] ; 0x80 80019b0: 4b06 ldr r3, [pc, #24] ; (80019cc ) 80019b2: 460a mov r2, r1 80019b4: f8a3 2082 strh.w r2, [r3, #130] ; 0x82 // HAL_UART_Receive_IT(&huart2,rxBuf,5); if (HAL_UART_Receive_DMA(&hMain, MainQueue.Buffer, 1) != HAL_OK) 80019b8: 2201 movs r2, #1 80019ba: 4905 ldr r1, [pc, #20] ; (80019d0 ) 80019bc: 4805 ldr r0, [pc, #20] ; (80019d4 ) 80019be: f002 fe53 bl 8004668 // { //// _Error_Handler(__FILE__, __LINE__); // } //HAL_UART_Receive_DMA(&hTerminal, TerminalQueue.Buffer, 1); //HAL_UART_Receive_IT(hTerminal, pQueue->Buffer + pQueue->head, 1); } 80019c2: bf00 nop 80019c4: 3708 adds r7, #8 80019c6: 46bd mov sp, r7 80019c8: bd80 pop {r7, pc} 80019ca: bf00 nop 80019cc: 20000864 .word 0x20000864 80019d0: 20000758 .word 0x20000758 80019d4: 20000a90 .word 0x20000a90 080019d8 : void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { 80019d8: b580 push {r7, lr} 80019da: b084 sub sp, #16 80019dc: af00 add r7, sp, #0 80019de: 6078 str r0, [r7, #4] // UART_HandleTypeDef *dst = (huart->Instance == USART2 ? &hTest:&hTerminal); pUARTQUEUE pQueue; // printf("Function : %s : \r\n",__func__); //printf("%02x ",uart_buf[i]); UartRxTimerCnt = 0; 80019e0: 4b15 ldr r3, [pc, #84] ; (8001a38 ) 80019e2: 2200 movs r2, #0 80019e4: 601a str r2, [r3, #0] pQueue = &MainQueue; 80019e6: 4b15 ldr r3, [pc, #84] ; (8001a3c ) 80019e8: 60fb str r3, [r7, #12] pQueue->head++; 80019ea: 68fb ldr r3, [r7, #12] 80019ec: 681b ldr r3, [r3, #0] 80019ee: 1c5a adds r2, r3, #1 80019f0: 68fb ldr r3, [r7, #12] 80019f2: 601a str r2, [r3, #0] if (pQueue->head >= QUEUE_BUFFER_LENGTH) pQueue->head = 0; 80019f4: 68fb ldr r3, [r7, #12] 80019f6: 681b ldr r3, [r3, #0] 80019f8: 2b7f cmp r3, #127 ; 0x7f 80019fa: dd02 ble.n 8001a02 80019fc: 68fb ldr r3, [r7, #12] 80019fe: 2200 movs r2, #0 8001a00: 601a str r2, [r3, #0] pQueue->data++; 8001a02: 68fb ldr r3, [r7, #12] 8001a04: 689b ldr r3, [r3, #8] 8001a06: 1c5a adds r2, r3, #1 8001a08: 68fb ldr r3, [r7, #12] 8001a0a: 609a str r2, [r3, #8] if (pQueue->data >= QUEUE_BUFFER_LENGTH) 8001a0c: 68fb ldr r3, [r7, #12] 8001a0e: 689b ldr r3, [r3, #8] 8001a10: 2b7f cmp r3, #127 ; 0x7f 8001a12: dd02 ble.n 8001a1a GetDataFromUartQueue(huart); 8001a14: 6878 ldr r0, [r7, #4] 8001a16: f000 f815 bl 8001a44 HAL_UART_Receive_IT(&hMain, pQueue->Buffer + pQueue->head, 1); 8001a1a: 68fb ldr r3, [r7, #12] 8001a1c: 330c adds r3, #12 8001a1e: 68fa ldr r2, [r7, #12] 8001a20: 6812 ldr r2, [r2, #0] 8001a22: 4413 add r3, r2 8001a24: 2201 movs r2, #1 8001a26: 4619 mov r1, r3 8001a28: 4805 ldr r0, [pc, #20] ; (8001a40 ) 8001a2a: f002 fd5d bl 80044e8 // HAL_UART_Receive_DMA(&hTest, pQueue->Buffer + pQueue->head, 1); // Set_UartRcv(true); } 8001a2e: bf00 nop 8001a30: 3710 adds r7, #16 8001a32: 46bd mov sp, r7 8001a34: bd80 pop {r7, pc} 8001a36: bf00 nop 8001a38: 20000618 .word 0x20000618 8001a3c: 2000074c .word 0x2000074c 8001a40: 20000a90 .word 0x20000a90 08001a44 : // HAL_UART_Receive_DMA(&hTerminal, pQueue->Buffer + pQueue->head, 10); } void GetDataFromUartQueue(UART_HandleTypeDef *huart) { 8001a44: b580 push {r7, lr} 8001a46: b086 sub sp, #24 8001a48: af00 add r7, sp, #0 8001a4a: 6078 str r0, [r7, #4] volatile static int cnt; bool ret = 0; 8001a4c: 2300 movs r3, #0 8001a4e: 75fb strb r3, [r7, #23] /* bool chksumret = 0; uint16_t Length = 0; uint16_t CrcChk = 0; UART_HandleTypeDef *dst = (huart->Instance == USART2 ? &hTest:&hTerminal);*/ // UART_HandleTypeDef *dst = &hTerminal; pUARTQUEUE pQueue = &MainQueue; 8001a50: 4b47 ldr r3, [pc, #284] ; (8001b70 ) 8001a52: 60fb str r3, [r7, #12] // if (HAL_UART_Transmit(dst, pQueue->Buffer + pQueue->tail, 1, 3000) != HAL_OK) // { // _Error_Handler(__FILE__, __LINE__); // } uart_buf[cnt++] = *(pQueue->Buffer + pQueue->tail); 8001a54: 68fb ldr r3, [r7, #12] 8001a56: 330c adds r3, #12 8001a58: 68fa ldr r2, [r7, #12] 8001a5a: 6852 ldr r2, [r2, #4] 8001a5c: 441a add r2, r3 8001a5e: 4b45 ldr r3, [pc, #276] ; (8001b74 ) 8001a60: 681b ldr r3, [r3, #0] 8001a62: 1c59 adds r1, r3, #1 8001a64: 4843 ldr r0, [pc, #268] ; (8001b74 ) 8001a66: 6001 str r1, [r0, #0] 8001a68: 7811 ldrb r1, [r2, #0] 8001a6a: 4a43 ldr r2, [pc, #268] ; (8001b78 ) 8001a6c: 54d1 strb r1, [r2, r3] //#ifdef DEBUG_PRINT // printf("%02x ",*(pQueue->Buffer + pQueue->tail)) ; //#endif /* DEBUG_PRINT */ pQueue->tail++; 8001a6e: 68fb ldr r3, [r7, #12] 8001a70: 685b ldr r3, [r3, #4] 8001a72: 1c5a adds r2, r3, #1 8001a74: 68fb ldr r3, [r7, #12] 8001a76: 605a str r2, [r3, #4] if (pQueue->tail >= QUEUE_BUFFER_LENGTH) pQueue->tail = 0; 8001a78: 68fb ldr r3, [r7, #12] 8001a7a: 685b ldr r3, [r3, #4] 8001a7c: 2b7f cmp r3, #127 ; 0x7f 8001a7e: dd02 ble.n 8001a86 8001a80: 68fb ldr r3, [r7, #12] 8001a82: 2200 movs r2, #0 8001a84: 605a str r2, [r3, #4] pQueue->data--; 8001a86: 68fb ldr r3, [r7, #12] 8001a88: 689b ldr r3, [r3, #8] 8001a8a: 1e5a subs r2, r3, #1 8001a8c: 68fb ldr r3, [r7, #12] 8001a8e: 609a str r2, [r3, #8] if(pQueue->data == 0){ 8001a90: 68fb ldr r3, [r7, #12] 8001a92: 689b ldr r3, [r3, #8] 8001a94: 2b00 cmp r3, #0 8001a96: d167 bne.n 8001b68 // printf("data cnt zero !!! \r\n"); //RF_Ctrl_Main(&uart_buf[Header]); // HAL_UART_Transmit(dst, &temp_buf[BLUECELL_HEADER00], 11, 3000); #if 1// PYJ.2019.07.15_BEGIN -- printf("\r\n[RX]"); 8001a98: 4838 ldr r0, [pc, #224] ; (8001b7c ) 8001a9a: f004 feab bl 80067f4 for(int i = 0; i < cnt; i++){ 8001a9e: 2300 movs r3, #0 8001aa0: 613b str r3, [r7, #16] 8001aa2: e00b b.n 8001abc printf("%02x ",uart_buf[i]); 8001aa4: 4a34 ldr r2, [pc, #208] ; (8001b78 ) 8001aa6: 693b ldr r3, [r7, #16] 8001aa8: 4413 add r3, r2 8001aaa: 781b ldrb r3, [r3, #0] 8001aac: b2db uxtb r3, r3 8001aae: 4619 mov r1, r3 8001ab0: 4833 ldr r0, [pc, #204] ; (8001b80 ) 8001ab2: f004 fe9f bl 80067f4 for(int i = 0; i < cnt; i++){ 8001ab6: 693b ldr r3, [r7, #16] 8001ab8: 3301 adds r3, #1 8001aba: 613b str r3, [r7, #16] 8001abc: 4b2d ldr r3, [pc, #180] ; (8001b74 ) 8001abe: 681b ldr r3, [r3, #0] 8001ac0: 693a ldr r2, [r7, #16] 8001ac2: 429a cmp r2, r3 8001ac4: dbee blt.n 8001aa4 } printf("\r\n"); 8001ac6: 482f ldr r0, [pc, #188] ; (8001b84 ) 8001ac8: f004 ff08 bl 80068dc // printf("Checksum Index : %d %x\r\n",uart_buf[NessLab_Req_DataLength] + NessLab_Req_DataLength + 1,uart_buf[uart_buf[NessLab_Req_DataLength] + NessLab_Req_DataLength + 1]); // printf(ANSI_COLOR_GREEN"\r\n CNT : %d \r\n"ANSI_COLOR_RESET,cnt); #endif // PYJ.2019.07.15_END -- if(uart_buf[NessLab_Req_MsgID0] == NessLab_Table_REQ) 8001acc: 4b2a ldr r3, [pc, #168] ; (8001b78 ) 8001ace: 789b ldrb r3, [r3, #2] 8001ad0: b2db uxtb r3, r3 8001ad2: 2bc9 cmp r3, #201 ; 0xc9 8001ad4: d10c bne.n 8001af0 ret = NessLab_CheckSum_Check(&uart_buf[NessLab_Req_MsgID0],uart_buf[NessLab_Req_DataLength] ,uart_buf[NessLab_Req_ChecksumVal]); 8001ad6: 4b28 ldr r3, [pc, #160] ; (8001b78 ) 8001ad8: 799b ldrb r3, [r3, #6] 8001ada: b2d9 uxtb r1, r3 8001adc: 4b26 ldr r3, [pc, #152] ; (8001b78 ) 8001ade: 7a5b ldrb r3, [r3, #9] 8001ae0: b2db uxtb r3, r3 8001ae2: 461a mov r2, r3 8001ae4: 4828 ldr r0, [pc, #160] ; (8001b88 ) 8001ae6: f7ff fddb bl 80016a0 8001aea: 4603 mov r3, r0 8001aec: 75fb strb r3, [r7, #23] 8001aee: e011 b.n 8001b14 else ret = NessLab_CheckSum_Check(&uart_buf[NessLab_Req_MsgID0],uart_buf[NessLab_DataLength] + 5 ,uart_buf[uart_buf[NessLab_Req_DataLength] + NessLab_Req_DataLength + 1]); 8001af0: 4b21 ldr r3, [pc, #132] ; (8001b78 ) 8001af2: 799b ldrb r3, [r3, #6] 8001af4: b2db uxtb r3, r3 8001af6: 3305 adds r3, #5 8001af8: b2d9 uxtb r1, r3 8001afa: 4b1f ldr r3, [pc, #124] ; (8001b78 ) 8001afc: 799b ldrb r3, [r3, #6] 8001afe: b2db uxtb r3, r3 8001b00: 3307 adds r3, #7 8001b02: 4a1d ldr r2, [pc, #116] ; (8001b78 ) 8001b04: 5cd3 ldrb r3, [r2, r3] 8001b06: b2db uxtb r3, r3 8001b08: 461a mov r2, r3 8001b0a: 481f ldr r0, [pc, #124] ; (8001b88 ) 8001b0c: f7ff fdc8 bl 80016a0 8001b10: 4603 mov r3, r0 8001b12: 75fb strb r3, [r7, #23] if(ret == true){ 8001b14: 7dfb ldrb r3, [r7, #23] 8001b16: 2b00 cmp r3, #0 8001b18: d006 beq.n 8001b28 NessLab_Operate(&uart_buf[0]); 8001b1a: 4817 ldr r0, [pc, #92] ; (8001b78 ) 8001b1c: f7ff f998 bl 8000e50 printf("Checksum OK \r\n"); 8001b20: 481a ldr r0, [pc, #104] ; (8001b8c ) 8001b22: f004 fedb bl 80068dc 8001b26: e01c b.n 8001b62 }else{ printf("Checksum Error \r\n"); 8001b28: 4819 ldr r0, [pc, #100] ; (8001b90 ) 8001b2a: f004 fed7 bl 80068dc printf("uart_buf[NessLab_Req_DataLength] : %x \r\n",uart_buf[NessLab_Req_DataLength]); 8001b2e: 4b12 ldr r3, [pc, #72] ; (8001b78 ) 8001b30: 799b ldrb r3, [r3, #6] 8001b32: b2db uxtb r3, r3 8001b34: 4619 mov r1, r3 8001b36: 4817 ldr r0, [pc, #92] ; (8001b94 ) 8001b38: f004 fe5c bl 80067f4 printf("NessLab_Req_DataLength : %d \r\n",NessLab_Req_DataLength); 8001b3c: 2106 movs r1, #6 8001b3e: 4816 ldr r0, [pc, #88] ; (8001b98 ) 8001b40: f004 fe58 bl 80067f4 printf("Checksum Index : %d %x\r\n",uart_buf[NessLab_Req_DataLength] + NessLab_Req_DataLength + 1,uart_buf[uart_buf[NessLab_Req_DataLength] + NessLab_Req_DataLength + 1]); 8001b44: 4b0c ldr r3, [pc, #48] ; (8001b78 ) 8001b46: 799b ldrb r3, [r3, #6] 8001b48: b2db uxtb r3, r3 8001b4a: 1dd9 adds r1, r3, #7 8001b4c: 4b0a ldr r3, [pc, #40] ; (8001b78 ) 8001b4e: 799b ldrb r3, [r3, #6] 8001b50: b2db uxtb r3, r3 8001b52: 3307 adds r3, #7 8001b54: 4a08 ldr r2, [pc, #32] ; (8001b78 ) 8001b56: 5cd3 ldrb r3, [r2, r3] 8001b58: b2db uxtb r3, r3 8001b5a: 461a mov r2, r3 8001b5c: 480f ldr r0, [pc, #60] ; (8001b9c ) 8001b5e: f004 fe49 bl 80067f4 } cnt = 0; 8001b62: 4b04 ldr r3, [pc, #16] ; (8001b74 ) 8001b64: 2200 movs r2, #0 8001b66: 601a str r2, [r3, #0] } } 8001b68: bf00 nop 8001b6a: 3718 adds r7, #24 8001b6c: 46bd mov sp, r7 8001b6e: bd80 pop {r7, pc} 8001b70: 2000074c .word 0x2000074c 8001b74: 20000614 .word 0x20000614 8001b78: 200006cc .word 0x200006cc 8001b7c: 08008a40 .word 0x08008a40 8001b80: 08008a48 .word 0x08008a48 8001b84: 08008a50 .word 0x08008a50 8001b88: 200006ce .word 0x200006ce 8001b8c: 08008a54 .word 0x08008a54 8001b90: 08008a64 .word 0x08008a64 8001b94: 08008a78 .word 0x08008a78 8001b98: 08008aa4 .word 0x08008aa4 8001b9c: 08008ac4 .word 0x08008ac4 08001ba0 : void Uart_Check(void){ 8001ba0: b580 push {r7, lr} 8001ba2: af00 add r7, sp, #0 while (MainQueue.data > 0 && UartRxTimerCnt > 50) GetDataFromUartQueue(&hMain); 8001ba4: e002 b.n 8001bac 8001ba6: 4806 ldr r0, [pc, #24] ; (8001bc0 ) 8001ba8: f7ff ff4c bl 8001a44 8001bac: 4b05 ldr r3, [pc, #20] ; (8001bc4 ) 8001bae: 689b ldr r3, [r3, #8] 8001bb0: 2b00 cmp r3, #0 8001bb2: dd03 ble.n 8001bbc 8001bb4: 4b04 ldr r3, [pc, #16] ; (8001bc8 ) 8001bb6: 681b ldr r3, [r3, #0] 8001bb8: 2b32 cmp r3, #50 ; 0x32 8001bba: d8f4 bhi.n 8001ba6 } 8001bbc: bf00 nop 8001bbe: bd80 pop {r7, pc} 8001bc0: 20000a90 .word 0x20000a90 8001bc4: 2000074c .word 0x2000074c 8001bc8: 20000618 .word 0x20000618 08001bcc : void Uart1_Data_Send(uint8_t* data,uint16_t size){ 8001bcc: b580 push {r7, lr} 8001bce: b084 sub sp, #16 8001bd0: af00 add r7, sp, #0 8001bd2: 6078 str r0, [r7, #4] 8001bd4: 460b mov r3, r1 8001bd6: 807b strh r3, [r7, #2] HAL_UART_Transmit_DMA(&hMain, &data[0],size); 8001bd8: 887b ldrh r3, [r7, #2] 8001bda: 461a mov r2, r3 8001bdc: 6879 ldr r1, [r7, #4] 8001bde: 480f ldr r0, [pc, #60] ; (8001c1c ) 8001be0: f002 fcd6 bl 8004590 //HAL_UART_Transmit_IT(&hTerminal, &data[0],size); // printf("data[278] : %x \r\n",data[278]); //// HAL_Delay(1); #if 1 // PYJ.2020.07.19_BEGIN -- printf("\r\n [TX] : "); 8001be4: 480e ldr r0, [pc, #56] ; (8001c20 ) 8001be6: f004 fe05 bl 80067f4 for(int i = 0; i< size; i++) 8001bea: 2300 movs r3, #0 8001bec: 60fb str r3, [r7, #12] 8001bee: e00a b.n 8001c06 printf("%02x ",data[i]); 8001bf0: 68fb ldr r3, [r7, #12] 8001bf2: 687a ldr r2, [r7, #4] 8001bf4: 4413 add r3, r2 8001bf6: 781b ldrb r3, [r3, #0] 8001bf8: 4619 mov r1, r3 8001bfa: 480a ldr r0, [pc, #40] ; (8001c24 ) 8001bfc: f004 fdfa bl 80067f4 for(int i = 0; i< size; i++) 8001c00: 68fb ldr r3, [r7, #12] 8001c02: 3301 adds r3, #1 8001c04: 60fb str r3, [r7, #12] 8001c06: 887b ldrh r3, [r7, #2] 8001c08: 68fa ldr r2, [r7, #12] 8001c0a: 429a cmp r2, r3 8001c0c: dbf0 blt.n 8001bf0 // printf("};\r\n\tCOUNT : %d \r\n",size); printf("\r\n"); 8001c0e: 4806 ldr r0, [pc, #24] ; (8001c28 ) 8001c10: f004 fe64 bl 80068dc // data[i] = 0; // } // printf("};\r\n\tCOUNT : %d \r\n",size); // printf("\r\n"); } 8001c14: bf00 nop 8001c16: 3710 adds r7, #16 8001c18: 46bd mov sp, r7 8001c1a: bd80 pop {r7, pc} 8001c1c: 20000a90 .word 0x20000a90 8001c20: 08008ae0 .word 0x08008ae0 8001c24: 08008a48 .word 0x08008a48 8001c28: 08008a50 .word 0x08008a50 08001c2c : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8001c2c: b580 push {r7, lr} 8001c2e: af00 add r7, sp, #0 __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); #endif #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8001c30: 2003 movs r0, #3 8001c32: f000 fdd1 bl 80027d8 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 8001c36: 2000 movs r0, #0 8001c38: f003 ffa4 bl 8005b84 /* Init the low level hardware */ HAL_MspInit(); 8001c3c: f003 fdba bl 80057b4 /* Return function status */ return HAL_OK; 8001c40: 2300 movs r3, #0 } 8001c42: 4618 mov r0, r3 8001c44: bd80 pop {r7, pc} ... 08001c48 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8001c48: b480 push {r7} 8001c4a: af00 add r7, sp, #0 uwTick += uwTickFreq; 8001c4c: 4b05 ldr r3, [pc, #20] ; (8001c64 ) 8001c4e: 781b ldrb r3, [r3, #0] 8001c50: 461a mov r2, r3 8001c52: 4b05 ldr r3, [pc, #20] ; (8001c68 ) 8001c54: 681b ldr r3, [r3, #0] 8001c56: 4413 add r3, r2 8001c58: 4a03 ldr r2, [pc, #12] ; (8001c68 ) 8001c5a: 6013 str r3, [r2, #0] } 8001c5c: bf00 nop 8001c5e: 46bd mov sp, r7 8001c60: bc80 pop {r7} 8001c62: 4770 bx lr 8001c64: 20000004 .word 0x20000004 8001c68: 200008e8 .word 0x200008e8 08001c6c : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8001c6c: b480 push {r7} 8001c6e: af00 add r7, sp, #0 return uwTick; 8001c70: 4b02 ldr r3, [pc, #8] ; (8001c7c ) 8001c72: 681b ldr r3, [r3, #0] } 8001c74: 4618 mov r0, r3 8001c76: 46bd mov sp, r7 8001c78: bc80 pop {r7} 8001c7a: 4770 bx lr 8001c7c: 200008e8 .word 0x200008e8 08001c80 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 8001c80: b580 push {r7, lr} 8001c82: b084 sub sp, #16 8001c84: af00 add r7, sp, #0 8001c86: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 8001c88: f7ff fff0 bl 8001c6c 8001c8c: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 8001c8e: 687b ldr r3, [r7, #4] 8001c90: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 8001c92: 68fb ldr r3, [r7, #12] 8001c94: f1b3 3fff cmp.w r3, #4294967295 8001c98: d005 beq.n 8001ca6 { wait += (uint32_t)(uwTickFreq); 8001c9a: 4b09 ldr r3, [pc, #36] ; (8001cc0 ) 8001c9c: 781b ldrb r3, [r3, #0] 8001c9e: 461a mov r2, r3 8001ca0: 68fb ldr r3, [r7, #12] 8001ca2: 4413 add r3, r2 8001ca4: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 8001ca6: bf00 nop 8001ca8: f7ff ffe0 bl 8001c6c 8001cac: 4602 mov r2, r0 8001cae: 68bb ldr r3, [r7, #8] 8001cb0: 1ad3 subs r3, r2, r3 8001cb2: 68fa ldr r2, [r7, #12] 8001cb4: 429a cmp r2, r3 8001cb6: d8f7 bhi.n 8001ca8 { } } 8001cb8: bf00 nop 8001cba: 3710 adds r7, #16 8001cbc: 46bd mov sp, r7 8001cbe: bd80 pop {r7, pc} 8001cc0: 20000004 .word 0x20000004 08001cc4 : * of structure "ADC_InitTypeDef". * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { 8001cc4: b580 push {r7, lr} 8001cc6: b086 sub sp, #24 8001cc8: af00 add r7, sp, #0 8001cca: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8001ccc: 2300 movs r3, #0 8001cce: 75fb strb r3, [r7, #23] uint32_t tmp_cr1 = 0U; 8001cd0: 2300 movs r3, #0 8001cd2: 613b str r3, [r7, #16] uint32_t tmp_cr2 = 0U; 8001cd4: 2300 movs r3, #0 8001cd6: 60bb str r3, [r7, #8] uint32_t tmp_sqr1 = 0U; 8001cd8: 2300 movs r3, #0 8001cda: 60fb str r3, [r7, #12] /* Check ADC handle */ if(hadc == NULL) 8001cdc: 687b ldr r3, [r7, #4] 8001cde: 2b00 cmp r3, #0 8001ce0: d101 bne.n 8001ce6 { return HAL_ERROR; 8001ce2: 2301 movs r3, #1 8001ce4: e0be b.n 8001e64 assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) 8001ce6: 687b ldr r3, [r7, #4] 8001ce8: 689b ldr r3, [r3, #8] 8001cea: 2b00 cmp r3, #0 /* Refer to header of this file for more details on clock enabling */ /* procedure. */ /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) 8001cec: 687b ldr r3, [r7, #4] 8001cee: 6a9b ldr r3, [r3, #40] ; 0x28 8001cf0: 2b00 cmp r3, #0 8001cf2: d109 bne.n 8001d08 { /* Initialize ADC error code */ ADC_CLEAR_ERRORCODE(hadc); 8001cf4: 687b ldr r3, [r7, #4] 8001cf6: 2200 movs r2, #0 8001cf8: 62da str r2, [r3, #44] ; 0x2c /* Allocate lock resource and initialize it */ hadc->Lock = HAL_UNLOCKED; 8001cfa: 687b ldr r3, [r7, #4] 8001cfc: 2200 movs r2, #0 8001cfe: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); 8001d02: 6878 ldr r0, [r7, #4] 8001d04: f003 fd88 bl 8005818 /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ /* Note: In case of ADC already enabled, precaution to not launch an */ /* unwanted conversion while modifying register CR2 by writing 1 to */ /* bit ADON. */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 8001d08: 6878 ldr r0, [r7, #4] 8001d0a: f000 fb75 bl 80023f8 8001d0e: 4603 mov r3, r0 8001d10: 75fb strb r3, [r7, #23] /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && 8001d12: 687b ldr r3, [r7, #4] 8001d14: 6a9b ldr r3, [r3, #40] ; 0x28 8001d16: f003 0310 and.w r3, r3, #16 8001d1a: 2b00 cmp r3, #0 8001d1c: f040 8099 bne.w 8001e52 8001d20: 7dfb ldrb r3, [r7, #23] 8001d22: 2b00 cmp r3, #0 8001d24: f040 8095 bne.w 8001e52 (tmp_hal_status == HAL_OK) ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8001d28: 687b ldr r3, [r7, #4] 8001d2a: 6a9b ldr r3, [r3, #40] ; 0x28 8001d2c: f423 5388 bic.w r3, r3, #4352 ; 0x1100 8001d30: f023 0302 bic.w r3, r3, #2 8001d34: f043 0202 orr.w r2, r3, #2 8001d38: 687b ldr r3, [r7, #4] 8001d3a: 629a str r2, [r3, #40] ; 0x28 /* - continuous conversion mode */ /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */ /* HAL_ADC_Start_xxx functions because if set in this function, */ /* a conversion on injected group would start a conversion also on */ /* regular group after ADC enabling. */ tmp_cr2 |= (hadc->Init.DataAlign | 8001d3c: 687b ldr r3, [r7, #4] 8001d3e: 685a ldr r2, [r3, #4] ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 8001d40: 687b ldr r3, [r7, #4] 8001d42: 69db ldr r3, [r3, #28] tmp_cr2 |= (hadc->Init.DataAlign | 8001d44: 431a orrs r2, r3 ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) ); 8001d46: 687b ldr r3, [r7, #4] 8001d48: 7b1b ldrb r3, [r3, #12] 8001d4a: 005b lsls r3, r3, #1 ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 8001d4c: 4313 orrs r3, r2 tmp_cr2 |= (hadc->Init.DataAlign | 8001d4e: 68ba ldr r2, [r7, #8] 8001d50: 4313 orrs r3, r2 8001d52: 60bb str r3, [r7, #8] /* Configuration of ADC: */ /* - scan mode */ /* - discontinuous mode disable/enable */ /* - discontinuous mode number of conversions */ tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode)); 8001d54: 687b ldr r3, [r7, #4] 8001d56: 689b ldr r3, [r3, #8] 8001d58: f5b3 7f80 cmp.w r3, #256 ; 0x100 8001d5c: d003 beq.n 8001d66 8001d5e: 687b ldr r3, [r7, #4] 8001d60: 689b ldr r3, [r3, #8] 8001d62: 2b01 cmp r3, #1 8001d64: d102 bne.n 8001d6c 8001d66: f44f 7380 mov.w r3, #256 ; 0x100 8001d6a: e000 b.n 8001d6e 8001d6c: 2300 movs r3, #0 8001d6e: 693a ldr r2, [r7, #16] 8001d70: 4313 orrs r3, r2 8001d72: 613b str r3, [r7, #16] /* Enable discontinuous mode only if continuous mode is disabled */ /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */ /* discontinuous is set anyway, but will have no effect on ADC HW. */ if (hadc->Init.DiscontinuousConvMode == ENABLE) 8001d74: 687b ldr r3, [r7, #4] 8001d76: 7d1b ldrb r3, [r3, #20] 8001d78: 2b01 cmp r3, #1 8001d7a: d119 bne.n 8001db0 { if (hadc->Init.ContinuousConvMode == DISABLE) 8001d7c: 687b ldr r3, [r7, #4] 8001d7e: 7b1b ldrb r3, [r3, #12] 8001d80: 2b00 cmp r3, #0 8001d82: d109 bne.n 8001d98 { /* Enable the selected ADC regular discontinuous mode */ /* Set the number of channels to be converted in discontinuous mode */ SET_BIT(tmp_cr1, ADC_CR1_DISCEN | 8001d84: 687b ldr r3, [r7, #4] 8001d86: 699b ldr r3, [r3, #24] 8001d88: 3b01 subs r3, #1 8001d8a: 035a lsls r2, r3, #13 8001d8c: 693b ldr r3, [r7, #16] 8001d8e: 4313 orrs r3, r2 8001d90: f443 6300 orr.w r3, r3, #2048 ; 0x800 8001d94: 613b str r3, [r7, #16] 8001d96: e00b b.n 8001db0 { /* ADC regular group settings continuous and sequencer discontinuous*/ /* cannot be enabled simultaneously. */ /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8001d98: 687b ldr r3, [r7, #4] 8001d9a: 6a9b ldr r3, [r3, #40] ; 0x28 8001d9c: f043 0220 orr.w r2, r3, #32 8001da0: 687b ldr r3, [r7, #4] 8001da2: 629a str r2, [r3, #40] ; 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8001da4: 687b ldr r3, [r7, #4] 8001da6: 6adb ldr r3, [r3, #44] ; 0x2c 8001da8: f043 0201 orr.w r2, r3, #1 8001dac: 687b ldr r3, [r7, #4] 8001dae: 62da str r2, [r3, #44] ; 0x2c } } /* Update ADC configuration register CR1 with previous settings */ MODIFY_REG(hadc->Instance->CR1, 8001db0: 687b ldr r3, [r7, #4] 8001db2: 681b ldr r3, [r3, #0] 8001db4: 685b ldr r3, [r3, #4] 8001db6: f423 4169 bic.w r1, r3, #59648 ; 0xe900 8001dba: 687b ldr r3, [r7, #4] 8001dbc: 681b ldr r3, [r3, #0] 8001dbe: 693a ldr r2, [r7, #16] 8001dc0: 430a orrs r2, r1 8001dc2: 605a str r2, [r3, #4] ADC_CR1_DISCEN | ADC_CR1_DISCNUM , tmp_cr1 ); /* Update ADC configuration register CR2 with previous settings */ MODIFY_REG(hadc->Instance->CR2, 8001dc4: 687b ldr r3, [r7, #4] 8001dc6: 681b ldr r3, [r3, #0] 8001dc8: 689a ldr r2, [r3, #8] 8001dca: 4b28 ldr r3, [pc, #160] ; (8001e6c ) 8001dcc: 4013 ands r3, r2 8001dce: 687a ldr r2, [r7, #4] 8001dd0: 6812 ldr r2, [r2, #0] 8001dd2: 68b9 ldr r1, [r7, #8] 8001dd4: 430b orrs r3, r1 8001dd6: 6093 str r3, [r2, #8] /* Note: Scan mode is present by hardware on this device and, if */ /* disabled, discards automatically nb of conversions. Anyway, nb of */ /* conversions is forced to 0x00 for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion" */ if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE) 8001dd8: 687b ldr r3, [r7, #4] 8001dda: 689b ldr r3, [r3, #8] 8001ddc: f5b3 7f80 cmp.w r3, #256 ; 0x100 8001de0: d003 beq.n 8001dea 8001de2: 687b ldr r3, [r7, #4] 8001de4: 689b ldr r3, [r3, #8] 8001de6: 2b01 cmp r3, #1 8001de8: d104 bne.n 8001df4 { tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion); 8001dea: 687b ldr r3, [r7, #4] 8001dec: 691b ldr r3, [r3, #16] 8001dee: 3b01 subs r3, #1 8001df0: 051b lsls r3, r3, #20 8001df2: 60fb str r3, [r7, #12] } MODIFY_REG(hadc->Instance->SQR1, 8001df4: 687b ldr r3, [r7, #4] 8001df6: 681b ldr r3, [r3, #0] 8001df8: 6adb ldr r3, [r3, #44] ; 0x2c 8001dfa: f423 0170 bic.w r1, r3, #15728640 ; 0xf00000 8001dfe: 687b ldr r3, [r7, #4] 8001e00: 681b ldr r3, [r3, #0] 8001e02: 68fa ldr r2, [r7, #12] 8001e04: 430a orrs r2, r1 8001e06: 62da str r2, [r3, #44] ; 0x2c /* ensure of no potential problem of ADC core IP clocking. */ /* Check through register CR2 (excluding bits set in other functions: */ /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */ /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */ /* measurement path bit (TSVREFE). */ if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 8001e08: 687b ldr r3, [r7, #4] 8001e0a: 681b ldr r3, [r3, #0] 8001e0c: 689a ldr r2, [r3, #8] 8001e0e: 4b18 ldr r3, [pc, #96] ; (8001e70 ) 8001e10: 4013 ands r3, r2 8001e12: 68ba ldr r2, [r7, #8] 8001e14: 429a cmp r2, r3 8001e16: d10b bne.n 8001e30 ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL | ADC_CR2_TSVREFE )) == tmp_cr2) { /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 8001e18: 687b ldr r3, [r7, #4] 8001e1a: 2200 movs r2, #0 8001e1c: 62da str r2, [r3, #44] ; 0x2c /* Set the ADC state */ ADC_STATE_CLR_SET(hadc->State, 8001e1e: 687b ldr r3, [r7, #4] 8001e20: 6a9b ldr r3, [r3, #40] ; 0x28 8001e22: f023 0303 bic.w r3, r3, #3 8001e26: f043 0201 orr.w r2, r3, #1 8001e2a: 687b ldr r3, [r7, #4] 8001e2c: 629a str r2, [r3, #40] ; 0x28 if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 8001e2e: e018 b.n 8001e62 HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 8001e30: 687b ldr r3, [r7, #4] 8001e32: 6a9b ldr r3, [r3, #40] ; 0x28 8001e34: f023 0312 bic.w r3, r3, #18 8001e38: f043 0210 orr.w r2, r3, #16 8001e3c: 687b ldr r3, [r7, #4] 8001e3e: 629a str r2, [r3, #40] ; 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8001e40: 687b ldr r3, [r7, #4] 8001e42: 6adb ldr r3, [r3, #44] ; 0x2c 8001e44: f043 0201 orr.w r2, r3, #1 8001e48: 687b ldr r3, [r7, #4] 8001e4a: 62da str r2, [r3, #44] ; 0x2c tmp_hal_status = HAL_ERROR; 8001e4c: 2301 movs r3, #1 8001e4e: 75fb strb r3, [r7, #23] if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 8001e50: e007 b.n 8001e62 } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8001e52: 687b ldr r3, [r7, #4] 8001e54: 6a9b ldr r3, [r3, #40] ; 0x28 8001e56: f043 0210 orr.w r2, r3, #16 8001e5a: 687b ldr r3, [r7, #4] 8001e5c: 629a str r2, [r3, #40] ; 0x28 tmp_hal_status = HAL_ERROR; 8001e5e: 2301 movs r3, #1 8001e60: 75fb strb r3, [r7, #23] } /* Return function status */ return tmp_hal_status; 8001e62: 7dfb ldrb r3, [r7, #23] } 8001e64: 4618 mov r0, r3 8001e66: 3718 adds r7, #24 8001e68: 46bd mov sp, r7 8001e6a: bd80 pop {r7, pc} 8001e6c: ffe1f7fd .word 0xffe1f7fd 8001e70: ff1f0efe .word 0xff1f0efe 08001e74 : * @param pData: The destination Buffer address. * @param Length: The length of data to be transferred from ADC peripheral to memory. * @retval None */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) { 8001e74: b580 push {r7, lr} 8001e76: b086 sub sp, #24 8001e78: af00 add r7, sp, #0 8001e7a: 60f8 str r0, [r7, #12] 8001e7c: 60b9 str r1, [r7, #8] 8001e7e: 607a str r2, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8001e80: 2300 movs r3, #0 8001e82: 75fb strb r3, [r7, #23] /* If multimode is enabled, dedicated function multimode conversion */ /* start DMA must be used. */ if(ADC_MULTIMODE_IS_ENABLE(hadc) == RESET) { /* Process locked */ __HAL_LOCK(hadc); 8001e84: 68fb ldr r3, [r7, #12] 8001e86: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 8001e8a: 2b01 cmp r3, #1 8001e8c: d101 bne.n 8001e92 8001e8e: 2302 movs r3, #2 8001e90: e080 b.n 8001f94 8001e92: 68fb ldr r3, [r7, #12] 8001e94: 2201 movs r2, #1 8001e96: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); 8001e9a: 68f8 ldr r0, [r7, #12] 8001e9c: f000 fa5a bl 8002354 8001ea0: 4603 mov r3, r0 8001ea2: 75fb strb r3, [r7, #23] /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) 8001ea4: 7dfb ldrb r3, [r7, #23] 8001ea6: 2b00 cmp r3, #0 8001ea8: d16f bne.n 8001f8a { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, 8001eaa: 68fb ldr r3, [r7, #12] 8001eac: 6a9b ldr r3, [r3, #40] ; 0x28 8001eae: f423 6370 bic.w r3, r3, #3840 ; 0xf00 8001eb2: f023 0301 bic.w r3, r3, #1 8001eb6: f443 7280 orr.w r2, r3, #256 ; 0x100 8001eba: 68fb ldr r3, [r7, #12] 8001ebc: 629a str r2, [r3, #40] ; 0x28 /* for all cases of multimode: independent mode, multimode ADC master */ /* or multimode ADC slave (for devices with several ADCs): */ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) { /* Set ADC state (ADC independent or master) */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 8001ebe: 68fb ldr r3, [r7, #12] 8001ec0: 6a9b ldr r3, [r3, #40] ; 0x28 8001ec2: f423 1280 bic.w r2, r3, #1048576 ; 0x100000 8001ec6: 68fb ldr r3, [r7, #12] 8001ec8: 629a str r2, [r3, #40] ; 0x28 /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) 8001eca: 68fb ldr r3, [r7, #12] 8001ecc: 681b ldr r3, [r3, #0] 8001ece: 685b ldr r3, [r3, #4] 8001ed0: f403 6380 and.w r3, r3, #1024 ; 0x400 8001ed4: 2b00 cmp r3, #0 8001ed6: d007 beq.n 8001ee8 { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 8001ed8: 68fb ldr r3, [r7, #12] 8001eda: 6a9b ldr r3, [r3, #40] ; 0x28 8001edc: f423 5340 bic.w r3, r3, #12288 ; 0x3000 8001ee0: f443 5280 orr.w r2, r3, #4096 ; 0x1000 8001ee4: 68fb ldr r3, [r7, #12] 8001ee6: 629a str r2, [r3, #40] ; 0x28 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } } /* State machine update: Check if an injected conversion is ongoing */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 8001ee8: 68fb ldr r3, [r7, #12] 8001eea: 6a9b ldr r3, [r3, #40] ; 0x28 8001eec: f403 5380 and.w r3, r3, #4096 ; 0x1000 8001ef0: 2b00 cmp r3, #0 8001ef2: d006 beq.n 8001f02 { /* Reset ADC error code fields related to conversions on group regular */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); 8001ef4: 68fb ldr r3, [r7, #12] 8001ef6: 6adb ldr r3, [r3, #44] ; 0x2c 8001ef8: f023 0206 bic.w r2, r3, #6 8001efc: 68fb ldr r3, [r7, #12] 8001efe: 62da str r2, [r3, #44] ; 0x2c 8001f00: e002 b.n 8001f08 } else { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); 8001f02: 68fb ldr r3, [r7, #12] 8001f04: 2200 movs r2, #0 8001f06: 62da str r2, [r3, #44] ; 0x2c } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); 8001f08: 68fb ldr r3, [r7, #12] 8001f0a: 2200 movs r2, #0 8001f0c: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; 8001f10: 68fb ldr r3, [r7, #12] 8001f12: 6a1b ldr r3, [r3, #32] 8001f14: 4a21 ldr r2, [pc, #132] ; (8001f9c ) 8001f16: 629a str r2, [r3, #40] ; 0x28 /* Set the DMA half transfer complete callback */ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; 8001f18: 68fb ldr r3, [r7, #12] 8001f1a: 6a1b ldr r3, [r3, #32] 8001f1c: 4a20 ldr r2, [pc, #128] ; (8001fa0 ) 8001f1e: 62da str r2, [r3, #44] ; 0x2c /* Set the DMA error callback */ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; 8001f20: 68fb ldr r3, [r7, #12] 8001f22: 6a1b ldr r3, [r3, #32] 8001f24: 4a1f ldr r2, [pc, #124] ; (8001fa4 ) 8001f26: 631a str r2, [r3, #48] ; 0x30 /* start (in case of SW start): */ /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC */ /* operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); 8001f28: 68fb ldr r3, [r7, #12] 8001f2a: 681b ldr r3, [r3, #0] 8001f2c: f06f 0202 mvn.w r2, #2 8001f30: 601a str r2, [r3, #0] /* Enable ADC DMA mode */ SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA); 8001f32: 68fb ldr r3, [r7, #12] 8001f34: 681b ldr r3, [r3, #0] 8001f36: 689a ldr r2, [r3, #8] 8001f38: 68fb ldr r3, [r7, #12] 8001f3a: 681b ldr r3, [r3, #0] 8001f3c: f442 7280 orr.w r2, r2, #256 ; 0x100 8001f40: 609a str r2, [r3, #8] /* Start the DMA channel */ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); 8001f42: 68fb ldr r3, [r7, #12] 8001f44: 6a18 ldr r0, [r3, #32] 8001f46: 68fb ldr r3, [r7, #12] 8001f48: 681b ldr r3, [r3, #0] 8001f4a: 334c adds r3, #76 ; 0x4c 8001f4c: 4619 mov r1, r3 8001f4e: 68ba ldr r2, [r7, #8] 8001f50: 687b ldr r3, [r7, #4] 8001f52: f000 fcd1 bl 80028f8 /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ if (ADC_IS_SOFTWARE_START_REGULAR(hadc)) 8001f56: 68fb ldr r3, [r7, #12] 8001f58: 681b ldr r3, [r3, #0] 8001f5a: 689b ldr r3, [r3, #8] 8001f5c: f403 2360 and.w r3, r3, #917504 ; 0xe0000 8001f60: f5b3 2f60 cmp.w r3, #917504 ; 0xe0000 8001f64: d108 bne.n 8001f78 { /* Start ADC conversion on regular group with SW start */ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); 8001f66: 68fb ldr r3, [r7, #12] 8001f68: 681b ldr r3, [r3, #0] 8001f6a: 689a ldr r2, [r3, #8] 8001f6c: 68fb ldr r3, [r7, #12] 8001f6e: 681b ldr r3, [r3, #0] 8001f70: f442 02a0 orr.w r2, r2, #5242880 ; 0x500000 8001f74: 609a str r2, [r3, #8] 8001f76: e00c b.n 8001f92 } else { /* Start ADC conversion on regular group with external trigger */ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); 8001f78: 68fb ldr r3, [r7, #12] 8001f7a: 681b ldr r3, [r3, #0] 8001f7c: 689a ldr r2, [r3, #8] 8001f7e: 68fb ldr r3, [r7, #12] 8001f80: 681b ldr r3, [r3, #0] 8001f82: f442 1280 orr.w r2, r2, #1048576 ; 0x100000 8001f86: 609a str r2, [r3, #8] 8001f88: e003 b.n 8001f92 } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); 8001f8a: 68fb ldr r3, [r7, #12] 8001f8c: 2200 movs r2, #0 8001f8e: f883 2024 strb.w r2, [r3, #36] ; 0x24 { tmp_hal_status = HAL_ERROR; } /* Return function status */ return tmp_hal_status; 8001f92: 7dfb ldrb r3, [r7, #23] } 8001f94: 4618 mov r0, r3 8001f96: 3718 adds r7, #24 8001f98: 46bd mov sp, r7 8001f9a: bd80 pop {r7, pc} 8001f9c: 0800246d .word 0x0800246d 8001fa0: 080024e9 .word 0x080024e9 8001fa4: 08002505 .word 0x08002505 08001fa8 : * @brief Handles ADC interrupt request * @param hadc: ADC handle * @retval None */ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) { 8001fa8: b580 push {r7, lr} 8001faa: b082 sub sp, #8 8001fac: af00 add r7, sp, #0 8001fae: 6078 str r0, [r7, #4] assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); /* ========== Check End of Conversion flag for regular group ========== */ if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) 8001fb0: 687b ldr r3, [r7, #4] 8001fb2: 681b ldr r3, [r3, #0] 8001fb4: 685b ldr r3, [r3, #4] 8001fb6: f003 0320 and.w r3, r3, #32 8001fba: 2b20 cmp r3, #32 8001fbc: d140 bne.n 8002040 { if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) ) 8001fbe: 687b ldr r3, [r7, #4] 8001fc0: 681b ldr r3, [r3, #0] 8001fc2: 681b ldr r3, [r3, #0] 8001fc4: f003 0302 and.w r3, r3, #2 8001fc8: 2b02 cmp r3, #2 8001fca: d139 bne.n 8002040 { /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) 8001fcc: 687b ldr r3, [r7, #4] 8001fce: 6a9b ldr r3, [r3, #40] ; 0x28 8001fd0: f003 0310 and.w r3, r3, #16 8001fd4: 2b00 cmp r3, #0 8001fd6: d105 bne.n 8001fe4 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 8001fd8: 687b ldr r3, [r7, #4] 8001fda: 6a9b ldr r3, [r3, #40] ; 0x28 8001fdc: f443 7200 orr.w r2, r3, #512 ; 0x200 8001fe0: 687b ldr r3, [r7, #4] 8001fe2: 629a str r2, [r3, #40] ; 0x28 /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 8001fe4: 687b ldr r3, [r7, #4] 8001fe6: 681b ldr r3, [r3, #0] 8001fe8: 689b ldr r3, [r3, #8] 8001fea: f403 2360 and.w r3, r3, #917504 ; 0xe0000 8001fee: f5b3 2f60 cmp.w r3, #917504 ; 0xe0000 8001ff2: d11d bne.n 8002030 (hadc->Init.ContinuousConvMode == DISABLE) ) 8001ff4: 687b ldr r3, [r7, #4] 8001ff6: 7b1b ldrb r3, [r3, #12] if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 8001ff8: 2b00 cmp r3, #0 8001ffa: d119 bne.n 8002030 { /* Disable ADC end of conversion interrupt on group regular */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); 8001ffc: 687b ldr r3, [r7, #4] 8001ffe: 681b ldr r3, [r3, #0] 8002000: 685a ldr r2, [r3, #4] 8002002: 687b ldr r3, [r7, #4] 8002004: 681b ldr r3, [r3, #0] 8002006: f022 0220 bic.w r2, r2, #32 800200a: 605a str r2, [r3, #4] /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 800200c: 687b ldr r3, [r7, #4] 800200e: 6a9b ldr r3, [r3, #40] ; 0x28 8002010: f423 7280 bic.w r2, r3, #256 ; 0x100 8002014: 687b ldr r3, [r7, #4] 8002016: 629a str r2, [r3, #40] ; 0x28 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 8002018: 687b ldr r3, [r7, #4] 800201a: 6a9b ldr r3, [r3, #40] ; 0x28 800201c: f403 5380 and.w r3, r3, #4096 ; 0x1000 8002020: 2b00 cmp r3, #0 8002022: d105 bne.n 8002030 { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 8002024: 687b ldr r3, [r7, #4] 8002026: 6a9b ldr r3, [r3, #40] ; 0x28 8002028: f043 0201 orr.w r2, r3, #1 800202c: 687b ldr r3, [r7, #4] 800202e: 629a str r2, [r3, #40] ; 0x28 /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); 8002030: 6878 ldr r0, [r7, #4] 8002032: f7ff faab bl 800158c #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear regular group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); 8002036: 687b ldr r3, [r7, #4] 8002038: 681b ldr r3, [r3, #0] 800203a: f06f 0212 mvn.w r2, #18 800203e: 601a str r2, [r3, #0] } } /* ========== Check End of Conversion flag for injected group ========== */ if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC)) 8002040: 687b ldr r3, [r7, #4] 8002042: 681b ldr r3, [r3, #0] 8002044: 685b ldr r3, [r3, #4] 8002046: f003 0380 and.w r3, r3, #128 ; 0x80 800204a: 2b80 cmp r3, #128 ; 0x80 800204c: d14f bne.n 80020ee { if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC)) 800204e: 687b ldr r3, [r7, #4] 8002050: 681b ldr r3, [r3, #0] 8002052: 681b ldr r3, [r3, #0] 8002054: f003 0304 and.w r3, r3, #4 8002058: 2b04 cmp r3, #4 800205a: d148 bne.n 80020ee { /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) 800205c: 687b ldr r3, [r7, #4] 800205e: 6a9b ldr r3, [r3, #40] ; 0x28 8002060: f003 0310 and.w r3, r3, #16 8002064: 2b00 cmp r3, #0 8002066: d105 bne.n 8002074 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); 8002068: 687b ldr r3, [r7, #4] 800206a: 6a9b ldr r3, [r3, #40] ; 0x28 800206c: f443 5200 orr.w r2, r3, #8192 ; 0x2000 8002070: 687b ldr r3, [r7, #4] 8002072: 629a str r2, [r3, #40] ; 0x28 /* conversion from group regular (same conditions as group regular */ /* interruption disabling above). */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_INJECTED(hadc) || 8002074: 687b ldr r3, [r7, #4] 8002076: 681b ldr r3, [r3, #0] 8002078: 689b ldr r3, [r3, #8] 800207a: f403 43e0 and.w r3, r3, #28672 ; 0x7000 800207e: f5b3 4fe0 cmp.w r3, #28672 ; 0x7000 8002082: d012 beq.n 80020aa (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && 8002084: 687b ldr r3, [r7, #4] 8002086: 681b ldr r3, [r3, #0] 8002088: 685b ldr r3, [r3, #4] 800208a: f403 6380 and.w r3, r3, #1024 ; 0x400 if(ADC_IS_SOFTWARE_START_INJECTED(hadc) || 800208e: 2b00 cmp r3, #0 8002090: d125 bne.n 80020de (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 8002092: 687b ldr r3, [r7, #4] 8002094: 681b ldr r3, [r3, #0] 8002096: 689b ldr r3, [r3, #8] 8002098: f403 2360 and.w r3, r3, #917504 ; 0xe0000 (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && 800209c: f5b3 2f60 cmp.w r3, #917504 ; 0xe0000 80020a0: d11d bne.n 80020de (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) 80020a2: 687b ldr r3, [r7, #4] 80020a4: 7b1b ldrb r3, [r3, #12] (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 80020a6: 2b00 cmp r3, #0 80020a8: d119 bne.n 80020de { /* Disable ADC end of conversion interrupt on group injected */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); 80020aa: 687b ldr r3, [r7, #4] 80020ac: 681b ldr r3, [r3, #0] 80020ae: 685a ldr r2, [r3, #4] 80020b0: 687b ldr r3, [r7, #4] 80020b2: 681b ldr r3, [r3, #0] 80020b4: f022 0280 bic.w r2, r2, #128 ; 0x80 80020b8: 605a str r2, [r3, #4] /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); 80020ba: 687b ldr r3, [r7, #4] 80020bc: 6a9b ldr r3, [r3, #40] ; 0x28 80020be: f423 5280 bic.w r2, r3, #4096 ; 0x1000 80020c2: 687b ldr r3, [r7, #4] 80020c4: 629a str r2, [r3, #40] ; 0x28 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) 80020c6: 687b ldr r3, [r7, #4] 80020c8: 6a9b ldr r3, [r3, #40] ; 0x28 80020ca: f403 7380 and.w r3, r3, #256 ; 0x100 80020ce: 2b00 cmp r3, #0 80020d0: d105 bne.n 80020de { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 80020d2: 687b ldr r3, [r7, #4] 80020d4: 6a9b ldr r3, [r3, #40] ; 0x28 80020d6: f043 0201 orr.w r2, r3, #1 80020da: 687b ldr r3, [r7, #4] 80020dc: 629a str r2, [r3, #40] ; 0x28 /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->InjectedConvCpltCallback(hadc); #else HAL_ADCEx_InjectedConvCpltCallback(hadc); 80020de: 6878 ldr r0, [r7, #4] 80020e0: f000 fac6 bl 8002670 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear injected group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC)); 80020e4: 687b ldr r3, [r7, #4] 80020e6: 681b ldr r3, [r3, #0] 80020e8: f06f 020c mvn.w r2, #12 80020ec: 601a str r2, [r3, #0] } } /* ========== Check Analog watchdog flags ========== */ if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD)) 80020ee: 687b ldr r3, [r7, #4] 80020f0: 681b ldr r3, [r3, #0] 80020f2: 685b ldr r3, [r3, #4] 80020f4: f003 0340 and.w r3, r3, #64 ; 0x40 80020f8: 2b40 cmp r3, #64 ; 0x40 80020fa: d114 bne.n 8002126 { if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD)) 80020fc: 687b ldr r3, [r7, #4] 80020fe: 681b ldr r3, [r3, #0] 8002100: 681b ldr r3, [r3, #0] 8002102: f003 0301 and.w r3, r3, #1 8002106: 2b01 cmp r3, #1 8002108: d10d bne.n 8002126 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); 800210a: 687b ldr r3, [r7, #4] 800210c: 6a9b ldr r3, [r3, #40] ; 0x28 800210e: f443 3280 orr.w r2, r3, #65536 ; 0x10000 8002112: 687b ldr r3, [r7, #4] 8002114: 629a str r2, [r3, #40] ; 0x28 /* Level out of window callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->LevelOutOfWindowCallback(hadc); #else HAL_ADC_LevelOutOfWindowCallback(hadc); 8002116: 6878 ldr r0, [r7, #4] 8002118: f000 f812 bl 8002140 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear the ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); 800211c: 687b ldr r3, [r7, #4] 800211e: 681b ldr r3, [r3, #0] 8002120: f06f 0201 mvn.w r2, #1 8002124: 601a str r2, [r3, #0] } } } 8002126: bf00 nop 8002128: 3708 adds r7, #8 800212a: 46bd mov sp, r7 800212c: bd80 pop {r7, pc} 0800212e : * @brief Conversion DMA half-transfer callback in non blocking mode * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) { 800212e: b480 push {r7} 8002130: b083 sub sp, #12 8002132: af00 add r7, sp, #0 8002134: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. */ } 8002136: bf00 nop 8002138: 370c adds r7, #12 800213a: 46bd mov sp, r7 800213c: bc80 pop {r7} 800213e: 4770 bx lr 08002140 : * @brief Analog watchdog callback in non blocking mode. * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) { 8002140: b480 push {r7} 8002142: b083 sub sp, #12 8002144: af00 add r7, sp, #0 8002146: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file. */ } 8002148: bf00 nop 800214a: 370c adds r7, #12 800214c: 46bd mov sp, r7 800214e: bc80 pop {r7} 8002150: 4770 bx lr 08002152 : * (ADC conversion with interruption or transfer by DMA) * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) { 8002152: b480 push {r7} 8002154: b083 sub sp, #12 8002156: af00 add r7, sp, #0 8002158: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ErrorCallback must be implemented in the user file. */ } 800215a: bf00 nop 800215c: 370c adds r7, #12 800215e: 46bd mov sp, r7 8002160: bc80 pop {r7} 8002162: 4770 bx lr 08002164 : * @param hadc: ADC handle * @param sConfig: Structure of ADC channel for regular group. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { 8002164: b480 push {r7} 8002166: b085 sub sp, #20 8002168: af00 add r7, sp, #0 800216a: 6078 str r0, [r7, #4] 800216c: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800216e: 2300 movs r3, #0 8002170: 73fb strb r3, [r7, #15] __IO uint32_t wait_loop_index = 0U; 8002172: 2300 movs r3, #0 8002174: 60bb str r3, [r7, #8] assert_param(IS_ADC_CHANNEL(sConfig->Channel)); assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); /* Process locked */ __HAL_LOCK(hadc); 8002176: 687b ldr r3, [r7, #4] 8002178: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 800217c: 2b01 cmp r3, #1 800217e: d101 bne.n 8002184 8002180: 2302 movs r3, #2 8002182: e0dc b.n 800233e 8002184: 687b ldr r3, [r7, #4] 8002186: 2201 movs r2, #1 8002188: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Regular sequence configuration */ /* For Rank 1 to 6 */ if (sConfig->Rank < 7U) 800218c: 683b ldr r3, [r7, #0] 800218e: 685b ldr r3, [r3, #4] 8002190: 2b06 cmp r3, #6 8002192: d81c bhi.n 80021ce { MODIFY_REG(hadc->Instance->SQR3 , 8002194: 687b ldr r3, [r7, #4] 8002196: 681b ldr r3, [r3, #0] 8002198: 6b59 ldr r1, [r3, #52] ; 0x34 800219a: 683b ldr r3, [r7, #0] 800219c: 685a ldr r2, [r3, #4] 800219e: 4613 mov r3, r2 80021a0: 009b lsls r3, r3, #2 80021a2: 4413 add r3, r2 80021a4: 3b05 subs r3, #5 80021a6: 221f movs r2, #31 80021a8: fa02 f303 lsl.w r3, r2, r3 80021ac: 43db mvns r3, r3 80021ae: 4019 ands r1, r3 80021b0: 683b ldr r3, [r7, #0] 80021b2: 6818 ldr r0, [r3, #0] 80021b4: 683b ldr r3, [r7, #0] 80021b6: 685a ldr r2, [r3, #4] 80021b8: 4613 mov r3, r2 80021ba: 009b lsls r3, r3, #2 80021bc: 4413 add r3, r2 80021be: 3b05 subs r3, #5 80021c0: fa00 f203 lsl.w r2, r0, r3 80021c4: 687b ldr r3, [r7, #4] 80021c6: 681b ldr r3, [r3, #0] 80021c8: 430a orrs r2, r1 80021ca: 635a str r2, [r3, #52] ; 0x34 80021cc: e03c b.n 8002248 ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) , ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 7 to 12 */ else if (sConfig->Rank < 13U) 80021ce: 683b ldr r3, [r7, #0] 80021d0: 685b ldr r3, [r3, #4] 80021d2: 2b0c cmp r3, #12 80021d4: d81c bhi.n 8002210 { MODIFY_REG(hadc->Instance->SQR2 , 80021d6: 687b ldr r3, [r7, #4] 80021d8: 681b ldr r3, [r3, #0] 80021da: 6b19 ldr r1, [r3, #48] ; 0x30 80021dc: 683b ldr r3, [r7, #0] 80021de: 685a ldr r2, [r3, #4] 80021e0: 4613 mov r3, r2 80021e2: 009b lsls r3, r3, #2 80021e4: 4413 add r3, r2 80021e6: 3b23 subs r3, #35 ; 0x23 80021e8: 221f movs r2, #31 80021ea: fa02 f303 lsl.w r3, r2, r3 80021ee: 43db mvns r3, r3 80021f0: 4019 ands r1, r3 80021f2: 683b ldr r3, [r7, #0] 80021f4: 6818 ldr r0, [r3, #0] 80021f6: 683b ldr r3, [r7, #0] 80021f8: 685a ldr r2, [r3, #4] 80021fa: 4613 mov r3, r2 80021fc: 009b lsls r3, r3, #2 80021fe: 4413 add r3, r2 8002200: 3b23 subs r3, #35 ; 0x23 8002202: fa00 f203 lsl.w r2, r0, r3 8002206: 687b ldr r3, [r7, #4] 8002208: 681b ldr r3, [r3, #0] 800220a: 430a orrs r2, r1 800220c: 631a str r2, [r3, #48] ; 0x30 800220e: e01b b.n 8002248 ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 13 to 16 */ else { MODIFY_REG(hadc->Instance->SQR1 , 8002210: 687b ldr r3, [r7, #4] 8002212: 681b ldr r3, [r3, #0] 8002214: 6ad9 ldr r1, [r3, #44] ; 0x2c 8002216: 683b ldr r3, [r7, #0] 8002218: 685a ldr r2, [r3, #4] 800221a: 4613 mov r3, r2 800221c: 009b lsls r3, r3, #2 800221e: 4413 add r3, r2 8002220: 3b41 subs r3, #65 ; 0x41 8002222: 221f movs r2, #31 8002224: fa02 f303 lsl.w r3, r2, r3 8002228: 43db mvns r3, r3 800222a: 4019 ands r1, r3 800222c: 683b ldr r3, [r7, #0] 800222e: 6818 ldr r0, [r3, #0] 8002230: 683b ldr r3, [r7, #0] 8002232: 685a ldr r2, [r3, #4] 8002234: 4613 mov r3, r2 8002236: 009b lsls r3, r3, #2 8002238: 4413 add r3, r2 800223a: 3b41 subs r3, #65 ; 0x41 800223c: fa00 f203 lsl.w r2, r0, r3 8002240: 687b ldr r3, [r7, #4] 8002242: 681b ldr r3, [r3, #0] 8002244: 430a orrs r2, r1 8002246: 62da str r2, [r3, #44] ; 0x2c } /* Channel sampling time configuration */ /* For channels 10 to 17 */ if (sConfig->Channel >= ADC_CHANNEL_10) 8002248: 683b ldr r3, [r7, #0] 800224a: 681b ldr r3, [r3, #0] 800224c: 2b09 cmp r3, #9 800224e: d91c bls.n 800228a { MODIFY_REG(hadc->Instance->SMPR1 , 8002250: 687b ldr r3, [r7, #4] 8002252: 681b ldr r3, [r3, #0] 8002254: 68d9 ldr r1, [r3, #12] 8002256: 683b ldr r3, [r7, #0] 8002258: 681a ldr r2, [r3, #0] 800225a: 4613 mov r3, r2 800225c: 005b lsls r3, r3, #1 800225e: 4413 add r3, r2 8002260: 3b1e subs r3, #30 8002262: 2207 movs r2, #7 8002264: fa02 f303 lsl.w r3, r2, r3 8002268: 43db mvns r3, r3 800226a: 4019 ands r1, r3 800226c: 683b ldr r3, [r7, #0] 800226e: 6898 ldr r0, [r3, #8] 8002270: 683b ldr r3, [r7, #0] 8002272: 681a ldr r2, [r3, #0] 8002274: 4613 mov r3, r2 8002276: 005b lsls r3, r3, #1 8002278: 4413 add r3, r2 800227a: 3b1e subs r3, #30 800227c: fa00 f203 lsl.w r2, r0, r3 8002280: 687b ldr r3, [r7, #4] 8002282: 681b ldr r3, [r3, #0] 8002284: 430a orrs r2, r1 8002286: 60da str r2, [r3, #12] 8002288: e019 b.n 80022be ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) , ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) ); } else /* For channels 0 to 9 */ { MODIFY_REG(hadc->Instance->SMPR2 , 800228a: 687b ldr r3, [r7, #4] 800228c: 681b ldr r3, [r3, #0] 800228e: 6919 ldr r1, [r3, #16] 8002290: 683b ldr r3, [r7, #0] 8002292: 681a ldr r2, [r3, #0] 8002294: 4613 mov r3, r2 8002296: 005b lsls r3, r3, #1 8002298: 4413 add r3, r2 800229a: 2207 movs r2, #7 800229c: fa02 f303 lsl.w r3, r2, r3 80022a0: 43db mvns r3, r3 80022a2: 4019 ands r1, r3 80022a4: 683b ldr r3, [r7, #0] 80022a6: 6898 ldr r0, [r3, #8] 80022a8: 683b ldr r3, [r7, #0] 80022aa: 681a ldr r2, [r3, #0] 80022ac: 4613 mov r3, r2 80022ae: 005b lsls r3, r3, #1 80022b0: 4413 add r3, r2 80022b2: fa00 f203 lsl.w r2, r0, r3 80022b6: 687b ldr r3, [r7, #4] 80022b8: 681b ldr r3, [r3, #0] 80022ba: 430a orrs r2, r1 80022bc: 611a str r2, [r3, #16] ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); } /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ /* and VREFINT measurement path. */ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 80022be: 683b ldr r3, [r7, #0] 80022c0: 681b ldr r3, [r3, #0] 80022c2: 2b10 cmp r3, #16 80022c4: d003 beq.n 80022ce (sConfig->Channel == ADC_CHANNEL_VREFINT) ) 80022c6: 683b ldr r3, [r7, #0] 80022c8: 681b ldr r3, [r3, #0] if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 80022ca: 2b11 cmp r3, #17 80022cc: d132 bne.n 8002334 { /* For STM32F1 devices with several ADC: Only ADC1 can access internal */ /* measurement channels (VrefInt/TempSensor). If these channels are */ /* intended to be set on other ADC instances, an error is reported. */ if (hadc->Instance == ADC1) 80022ce: 687b ldr r3, [r7, #4] 80022d0: 681b ldr r3, [r3, #0] 80022d2: 4a1d ldr r2, [pc, #116] ; (8002348 ) 80022d4: 4293 cmp r3, r2 80022d6: d125 bne.n 8002324 { if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET) 80022d8: 687b ldr r3, [r7, #4] 80022da: 681b ldr r3, [r3, #0] 80022dc: 689b ldr r3, [r3, #8] 80022de: f403 0300 and.w r3, r3, #8388608 ; 0x800000 80022e2: 2b00 cmp r3, #0 80022e4: d126 bne.n 8002334 { SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); 80022e6: 687b ldr r3, [r7, #4] 80022e8: 681b ldr r3, [r3, #0] 80022ea: 689a ldr r2, [r3, #8] 80022ec: 687b ldr r3, [r7, #4] 80022ee: 681b ldr r3, [r3, #0] 80022f0: f442 0200 orr.w r2, r2, #8388608 ; 0x800000 80022f4: 609a str r2, [r3, #8] if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)) 80022f6: 683b ldr r3, [r7, #0] 80022f8: 681b ldr r3, [r3, #0] 80022fa: 2b10 cmp r3, #16 80022fc: d11a bne.n 8002334 { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); 80022fe: 4b13 ldr r3, [pc, #76] ; (800234c ) 8002300: 681b ldr r3, [r3, #0] 8002302: 4a13 ldr r2, [pc, #76] ; (8002350 ) 8002304: fba2 2303 umull r2, r3, r2, r3 8002308: 0c9a lsrs r2, r3, #18 800230a: 4613 mov r3, r2 800230c: 009b lsls r3, r3, #2 800230e: 4413 add r3, r2 8002310: 005b lsls r3, r3, #1 8002312: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 8002314: e002 b.n 800231c { wait_loop_index--; 8002316: 68bb ldr r3, [r7, #8] 8002318: 3b01 subs r3, #1 800231a: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800231c: 68bb ldr r3, [r7, #8] 800231e: 2b00 cmp r3, #0 8002320: d1f9 bne.n 8002316 8002322: e007 b.n 8002334 } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8002324: 687b ldr r3, [r7, #4] 8002326: 6a9b ldr r3, [r3, #40] ; 0x28 8002328: f043 0220 orr.w r2, r3, #32 800232c: 687b ldr r3, [r7, #4] 800232e: 629a str r2, [r3, #40] ; 0x28 tmp_hal_status = HAL_ERROR; 8002330: 2301 movs r3, #1 8002332: 73fb strb r3, [r7, #15] } } /* Process unlocked */ __HAL_UNLOCK(hadc); 8002334: 687b ldr r3, [r7, #4] 8002336: 2200 movs r2, #0 8002338: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Return function status */ return tmp_hal_status; 800233c: 7bfb ldrb r3, [r7, #15] } 800233e: 4618 mov r0, r3 8002340: 3714 adds r7, #20 8002342: 46bd mov sp, r7 8002344: bc80 pop {r7} 8002346: 4770 bx lr 8002348: 40012400 .word 0x40012400 800234c: 20000008 .word 0x20000008 8002350: 431bde83 .word 0x431bde83 08002354 : * and voltage regulator must be enabled (done into HAL_ADC_Init()). * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) { 8002354: b580 push {r7, lr} 8002356: b084 sub sp, #16 8002358: af00 add r7, sp, #0 800235a: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 800235c: 2300 movs r3, #0 800235e: 60fb str r3, [r7, #12] __IO uint32_t wait_loop_index = 0U; 8002360: 2300 movs r3, #0 8002362: 60bb str r3, [r7, #8] /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ if (ADC_IS_ENABLE(hadc) == RESET) 8002364: 687b ldr r3, [r7, #4] 8002366: 681b ldr r3, [r3, #0] 8002368: 689b ldr r3, [r3, #8] 800236a: f003 0301 and.w r3, r3, #1 800236e: 2b01 cmp r3, #1 8002370: d039 beq.n 80023e6 { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); 8002372: 687b ldr r3, [r7, #4] 8002374: 681b ldr r3, [r3, #0] 8002376: 689a ldr r2, [r3, #8] 8002378: 687b ldr r3, [r7, #4] 800237a: 681b ldr r3, [r3, #0] 800237c: f042 0201 orr.w r2, r2, #1 8002380: 609a str r2, [r3, #8] /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); 8002382: 4b1b ldr r3, [pc, #108] ; (80023f0 ) 8002384: 681b ldr r3, [r3, #0] 8002386: 4a1b ldr r2, [pc, #108] ; (80023f4 ) 8002388: fba2 2303 umull r2, r3, r2, r3 800238c: 0c9b lsrs r3, r3, #18 800238e: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 8002390: e002 b.n 8002398 { wait_loop_index--; 8002392: 68bb ldr r3, [r7, #8] 8002394: 3b01 subs r3, #1 8002396: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 8002398: 68bb ldr r3, [r7, #8] 800239a: 2b00 cmp r3, #0 800239c: d1f9 bne.n 8002392 } /* Get tick count */ tickstart = HAL_GetTick(); 800239e: f7ff fc65 bl 8001c6c 80023a2: 60f8 str r0, [r7, #12] /* Wait for ADC effectively enabled */ while(ADC_IS_ENABLE(hadc) == RESET) 80023a4: e018 b.n 80023d8 { if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) 80023a6: f7ff fc61 bl 8001c6c 80023aa: 4602 mov r2, r0 80023ac: 68fb ldr r3, [r7, #12] 80023ae: 1ad3 subs r3, r2, r3 80023b0: 2b02 cmp r3, #2 80023b2: d911 bls.n 80023d8 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 80023b4: 687b ldr r3, [r7, #4] 80023b6: 6a9b ldr r3, [r3, #40] ; 0x28 80023b8: f043 0210 orr.w r2, r3, #16 80023bc: 687b ldr r3, [r7, #4] 80023be: 629a str r2, [r3, #40] ; 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 80023c0: 687b ldr r3, [r7, #4] 80023c2: 6adb ldr r3, [r3, #44] ; 0x2c 80023c4: f043 0201 orr.w r2, r3, #1 80023c8: 687b ldr r3, [r7, #4] 80023ca: 62da str r2, [r3, #44] ; 0x2c /* Process unlocked */ __HAL_UNLOCK(hadc); 80023cc: 687b ldr r3, [r7, #4] 80023ce: 2200 movs r2, #0 80023d0: f883 2024 strb.w r2, [r3, #36] ; 0x24 return HAL_ERROR; 80023d4: 2301 movs r3, #1 80023d6: e007 b.n 80023e8 while(ADC_IS_ENABLE(hadc) == RESET) 80023d8: 687b ldr r3, [r7, #4] 80023da: 681b ldr r3, [r3, #0] 80023dc: 689b ldr r3, [r3, #8] 80023de: f003 0301 and.w r3, r3, #1 80023e2: 2b01 cmp r3, #1 80023e4: d1df bne.n 80023a6 } } } /* Return HAL status */ return HAL_OK; 80023e6: 2300 movs r3, #0 } 80023e8: 4618 mov r0, r3 80023ea: 3710 adds r7, #16 80023ec: 46bd mov sp, r7 80023ee: bd80 pop {r7, pc} 80023f0: 20000008 .word 0x20000008 80023f4: 431bde83 .word 0x431bde83 080023f8 : * stopped to disable the ADC. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc) { 80023f8: b580 push {r7, lr} 80023fa: b084 sub sp, #16 80023fc: af00 add r7, sp, #0 80023fe: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8002400: 2300 movs r3, #0 8002402: 60fb str r3, [r7, #12] /* Verification if ADC is not already disabled */ if (ADC_IS_ENABLE(hadc) != RESET) 8002404: 687b ldr r3, [r7, #4] 8002406: 681b ldr r3, [r3, #0] 8002408: 689b ldr r3, [r3, #8] 800240a: f003 0301 and.w r3, r3, #1 800240e: 2b01 cmp r3, #1 8002410: d127 bne.n 8002462 { /* Disable the ADC peripheral */ __HAL_ADC_DISABLE(hadc); 8002412: 687b ldr r3, [r7, #4] 8002414: 681b ldr r3, [r3, #0] 8002416: 689a ldr r2, [r3, #8] 8002418: 687b ldr r3, [r7, #4] 800241a: 681b ldr r3, [r3, #0] 800241c: f022 0201 bic.w r2, r2, #1 8002420: 609a str r2, [r3, #8] /* Get tick count */ tickstart = HAL_GetTick(); 8002422: f7ff fc23 bl 8001c6c 8002426: 60f8 str r0, [r7, #12] /* Wait for ADC effectively disabled */ while(ADC_IS_ENABLE(hadc) != RESET) 8002428: e014 b.n 8002454 { if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 800242a: f7ff fc1f bl 8001c6c 800242e: 4602 mov r2, r0 8002430: 68fb ldr r3, [r7, #12] 8002432: 1ad3 subs r3, r2, r3 8002434: 2b02 cmp r3, #2 8002436: d90d bls.n 8002454 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8002438: 687b ldr r3, [r7, #4] 800243a: 6a9b ldr r3, [r3, #40] ; 0x28 800243c: f043 0210 orr.w r2, r3, #16 8002440: 687b ldr r3, [r7, #4] 8002442: 629a str r2, [r3, #40] ; 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8002444: 687b ldr r3, [r7, #4] 8002446: 6adb ldr r3, [r3, #44] ; 0x2c 8002448: f043 0201 orr.w r2, r3, #1 800244c: 687b ldr r3, [r7, #4] 800244e: 62da str r2, [r3, #44] ; 0x2c return HAL_ERROR; 8002450: 2301 movs r3, #1 8002452: e007 b.n 8002464 while(ADC_IS_ENABLE(hadc) != RESET) 8002454: 687b ldr r3, [r7, #4] 8002456: 681b ldr r3, [r3, #0] 8002458: 689b ldr r3, [r3, #8] 800245a: f003 0301 and.w r3, r3, #1 800245e: 2b01 cmp r3, #1 8002460: d0e3 beq.n 800242a } } } /* Return HAL status */ return HAL_OK; 8002462: 2300 movs r3, #0 } 8002464: 4618 mov r0, r3 8002466: 3710 adds r7, #16 8002468: 46bd mov sp, r7 800246a: bd80 pop {r7, pc} 0800246c : * @brief DMA transfer complete callback. * @param hdma: pointer to DMA handle. * @retval None */ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) { 800246c: b580 push {r7, lr} 800246e: b084 sub sp, #16 8002470: af00 add r7, sp, #0 8002472: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 8002474: 687b ldr r3, [r7, #4] 8002476: 6a5b ldr r3, [r3, #36] ; 0x24 8002478: 60fb str r3, [r7, #12] /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) 800247a: 68fb ldr r3, [r7, #12] 800247c: 6a9b ldr r3, [r3, #40] ; 0x28 800247e: f003 0350 and.w r3, r3, #80 ; 0x50 8002482: 2b00 cmp r3, #0 8002484: d127 bne.n 80024d6 { /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 8002486: 68fb ldr r3, [r7, #12] 8002488: 6a9b ldr r3, [r3, #40] ; 0x28 800248a: f443 7200 orr.w r2, r3, #512 ; 0x200 800248e: 68fb ldr r3, [r7, #12] 8002490: 629a str r2, [r3, #40] ; 0x28 /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 8002492: 68fb ldr r3, [r7, #12] 8002494: 681b ldr r3, [r3, #0] 8002496: 689b ldr r3, [r3, #8] 8002498: f403 2360 and.w r3, r3, #917504 ; 0xe0000 800249c: f5b3 2f60 cmp.w r3, #917504 ; 0xe0000 80024a0: d115 bne.n 80024ce (hadc->Init.ContinuousConvMode == DISABLE) ) 80024a2: 68fb ldr r3, [r7, #12] 80024a4: 7b1b ldrb r3, [r3, #12] if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 80024a6: 2b00 cmp r3, #0 80024a8: d111 bne.n 80024ce { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 80024aa: 68fb ldr r3, [r7, #12] 80024ac: 6a9b ldr r3, [r3, #40] ; 0x28 80024ae: f423 7280 bic.w r2, r3, #256 ; 0x100 80024b2: 68fb ldr r3, [r7, #12] 80024b4: 629a str r2, [r3, #40] ; 0x28 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 80024b6: 68fb ldr r3, [r7, #12] 80024b8: 6a9b ldr r3, [r3, #40] ; 0x28 80024ba: f403 5380 and.w r3, r3, #4096 ; 0x1000 80024be: 2b00 cmp r3, #0 80024c0: d105 bne.n 80024ce { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 80024c2: 68fb ldr r3, [r7, #12] 80024c4: 6a9b ldr r3, [r3, #40] ; 0x28 80024c6: f043 0201 orr.w r2, r3, #1 80024ca: 68fb ldr r3, [r7, #12] 80024cc: 629a str r2, [r3, #40] ; 0x28 /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); 80024ce: 68f8 ldr r0, [r7, #12] 80024d0: f7ff f85c bl 800158c else { /* Call DMA error callback */ hadc->DMA_Handle->XferErrorCallback(hdma); } } 80024d4: e004 b.n 80024e0 hadc->DMA_Handle->XferErrorCallback(hdma); 80024d6: 68fb ldr r3, [r7, #12] 80024d8: 6a1b ldr r3, [r3, #32] 80024da: 6b1b ldr r3, [r3, #48] ; 0x30 80024dc: 6878 ldr r0, [r7, #4] 80024de: 4798 blx r3 } 80024e0: bf00 nop 80024e2: 3710 adds r7, #16 80024e4: 46bd mov sp, r7 80024e6: bd80 pop {r7, pc} 080024e8 : * @brief DMA half transfer complete callback. * @param hdma: pointer to DMA handle. * @retval None */ void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) { 80024e8: b580 push {r7, lr} 80024ea: b084 sub sp, #16 80024ec: af00 add r7, sp, #0 80024ee: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 80024f0: 687b ldr r3, [r7, #4] 80024f2: 6a5b ldr r3, [r3, #36] ; 0x24 80024f4: 60fb str r3, [r7, #12] /* Half conversion callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvHalfCpltCallback(hadc); #else HAL_ADC_ConvHalfCpltCallback(hadc); 80024f6: 68f8 ldr r0, [r7, #12] 80024f8: f7ff fe19 bl 800212e #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } 80024fc: bf00 nop 80024fe: 3710 adds r7, #16 8002500: 46bd mov sp, r7 8002502: bd80 pop {r7, pc} 08002504 : * @brief DMA error callback * @param hdma: pointer to DMA handle. * @retval None */ void ADC_DMAError(DMA_HandleTypeDef *hdma) { 8002504: b580 push {r7, lr} 8002506: b084 sub sp, #16 8002508: af00 add r7, sp, #0 800250a: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 800250c: 687b ldr r3, [r7, #4] 800250e: 6a5b ldr r3, [r3, #36] ; 0x24 8002510: 60fb str r3, [r7, #12] /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); 8002512: 68fb ldr r3, [r7, #12] 8002514: 6a9b ldr r3, [r3, #40] ; 0x28 8002516: f043 0240 orr.w r2, r3, #64 ; 0x40 800251a: 68fb ldr r3, [r7, #12] 800251c: 629a str r2, [r3, #40] ; 0x28 /* Set ADC error code to DMA error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); 800251e: 68fb ldr r3, [r7, #12] 8002520: 6adb ldr r3, [r3, #44] ; 0x2c 8002522: f043 0204 orr.w r2, r3, #4 8002526: 68fb ldr r3, [r7, #12] 8002528: 62da str r2, [r3, #44] ; 0x2c /* Error callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ErrorCallback(hadc); #else HAL_ADC_ErrorCallback(hadc); 800252a: 68f8 ldr r0, [r7, #12] 800252c: f7ff fe11 bl 8002152 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } 8002530: bf00 nop 8002532: 3710 adds r7, #16 8002534: 46bd mov sp, r7 8002536: bd80 pop {r7, pc} 08002538 : * the completion of this function. * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc) { 8002538: b590 push {r4, r7, lr} 800253a: b087 sub sp, #28 800253c: af00 add r7, sp, #0 800253e: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8002540: 2300 movs r3, #0 8002542: 75fb strb r3, [r7, #23] uint32_t tickstart; __IO uint32_t wait_loop_index = 0U; 8002544: 2300 movs r3, #0 8002546: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); 8002548: 687b ldr r3, [r7, #4] 800254a: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 800254e: 2b01 cmp r3, #1 8002550: d101 bne.n 8002556 8002552: 2302 movs r3, #2 8002554: e086 b.n 8002664 8002556: 687b ldr r3, [r7, #4] 8002558: 2201 movs r2, #1 800255a: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* 1. Calibration prerequisite: */ /* - ADC must be disabled for at least two ADC clock cycles in disable */ /* mode before ADC enable */ /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 800255e: 6878 ldr r0, [r7, #4] 8002560: f7ff ff4a bl 80023f8 8002564: 4603 mov r3, r0 8002566: 75fb strb r3, [r7, #23] /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) 8002568: 7dfb ldrb r3, [r7, #23] 800256a: 2b00 cmp r3, #0 800256c: d175 bne.n 800265a { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800256e: 687b ldr r3, [r7, #4] 8002570: 6a9b ldr r3, [r3, #40] ; 0x28 8002572: f423 5388 bic.w r3, r3, #4352 ; 0x1100 8002576: f023 0302 bic.w r3, r3, #2 800257a: f043 0202 orr.w r2, r3, #2 800257e: 687b ldr r3, [r7, #4] 8002580: 629a str r2, [r3, #40] ; 0x28 /* Hardware prerequisite: delay before starting the calibration. */ /* - Computation of CPU clock cycles corresponding to ADC clock cycles. */ /* - Wait for the expected ADC clock cycles delay */ wait_loop_index = ((SystemCoreClock / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) 8002582: 4b3a ldr r3, [pc, #232] ; (800266c ) 8002584: 681c ldr r4, [r3, #0] 8002586: 2002 movs r0, #2 8002588: f001 fc20 bl 8003dcc 800258c: 4603 mov r3, r0 800258e: fbb4 f3f3 udiv r3, r4, r3 * ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES ); 8002592: 005b lsls r3, r3, #1 wait_loop_index = ((SystemCoreClock 8002594: 60fb str r3, [r7, #12] while(wait_loop_index != 0U) 8002596: e002 b.n 800259e { wait_loop_index--; 8002598: 68fb ldr r3, [r7, #12] 800259a: 3b01 subs r3, #1 800259c: 60fb str r3, [r7, #12] while(wait_loop_index != 0U) 800259e: 68fb ldr r3, [r7, #12] 80025a0: 2b00 cmp r3, #0 80025a2: d1f9 bne.n 8002598 } /* 2. Enable the ADC peripheral */ ADC_Enable(hadc); 80025a4: 6878 ldr r0, [r7, #4] 80025a6: f7ff fed5 bl 8002354 /* 3. Resets ADC calibration registers */ SET_BIT(hadc->Instance->CR2, ADC_CR2_RSTCAL); 80025aa: 687b ldr r3, [r7, #4] 80025ac: 681b ldr r3, [r3, #0] 80025ae: 689a ldr r2, [r3, #8] 80025b0: 687b ldr r3, [r7, #4] 80025b2: 681b ldr r3, [r3, #0] 80025b4: f042 0208 orr.w r2, r2, #8 80025b8: 609a str r2, [r3, #8] tickstart = HAL_GetTick(); 80025ba: f7ff fb57 bl 8001c6c 80025be: 6138 str r0, [r7, #16] /* Wait for calibration reset completion */ while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 80025c0: e014 b.n 80025ec { if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) 80025c2: f7ff fb53 bl 8001c6c 80025c6: 4602 mov r2, r0 80025c8: 693b ldr r3, [r7, #16] 80025ca: 1ad3 subs r3, r2, r3 80025cc: 2b0a cmp r3, #10 80025ce: d90d bls.n 80025ec { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 80025d0: 687b ldr r3, [r7, #4] 80025d2: 6a9b ldr r3, [r3, #40] ; 0x28 80025d4: f023 0312 bic.w r3, r3, #18 80025d8: f043 0210 orr.w r2, r3, #16 80025dc: 687b ldr r3, [r7, #4] 80025de: 629a str r2, [r3, #40] ; 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); 80025e0: 687b ldr r3, [r7, #4] 80025e2: 2200 movs r2, #0 80025e4: f883 2024 strb.w r2, [r3, #36] ; 0x24 return HAL_ERROR; 80025e8: 2301 movs r3, #1 80025ea: e03b b.n 8002664 while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 80025ec: 687b ldr r3, [r7, #4] 80025ee: 681b ldr r3, [r3, #0] 80025f0: 689b ldr r3, [r3, #8] 80025f2: f003 0308 and.w r3, r3, #8 80025f6: 2b00 cmp r3, #0 80025f8: d1e3 bne.n 80025c2 } } /* 4. Start ADC calibration */ SET_BIT(hadc->Instance->CR2, ADC_CR2_CAL); 80025fa: 687b ldr r3, [r7, #4] 80025fc: 681b ldr r3, [r3, #0] 80025fe: 689a ldr r2, [r3, #8] 8002600: 687b ldr r3, [r7, #4] 8002602: 681b ldr r3, [r3, #0] 8002604: f042 0204 orr.w r2, r2, #4 8002608: 609a str r2, [r3, #8] tickstart = HAL_GetTick(); 800260a: f7ff fb2f bl 8001c6c 800260e: 6138 str r0, [r7, #16] /* Wait for calibration completion */ while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 8002610: e014 b.n 800263c { if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) 8002612: f7ff fb2b bl 8001c6c 8002616: 4602 mov r2, r0 8002618: 693b ldr r3, [r7, #16] 800261a: 1ad3 subs r3, r2, r3 800261c: 2b0a cmp r3, #10 800261e: d90d bls.n 800263c { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 8002620: 687b ldr r3, [r7, #4] 8002622: 6a9b ldr r3, [r3, #40] ; 0x28 8002624: f023 0312 bic.w r3, r3, #18 8002628: f043 0210 orr.w r2, r3, #16 800262c: 687b ldr r3, [r7, #4] 800262e: 629a str r2, [r3, #40] ; 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); 8002630: 687b ldr r3, [r7, #4] 8002632: 2200 movs r2, #0 8002634: f883 2024 strb.w r2, [r3, #36] ; 0x24 return HAL_ERROR; 8002638: 2301 movs r3, #1 800263a: e013 b.n 8002664 while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 800263c: 687b ldr r3, [r7, #4] 800263e: 681b ldr r3, [r3, #0] 8002640: 689b ldr r3, [r3, #8] 8002642: f003 0304 and.w r3, r3, #4 8002646: 2b00 cmp r3, #0 8002648: d1e3 bne.n 8002612 } } /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800264a: 687b ldr r3, [r7, #4] 800264c: 6a9b ldr r3, [r3, #40] ; 0x28 800264e: f023 0303 bic.w r3, r3, #3 8002652: f043 0201 orr.w r2, r3, #1 8002656: 687b ldr r3, [r7, #4] 8002658: 629a str r2, [r3, #40] ; 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); } /* Process unlocked */ __HAL_UNLOCK(hadc); 800265a: 687b ldr r3, [r7, #4] 800265c: 2200 movs r2, #0 800265e: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Return function status */ return tmp_hal_status; 8002662: 7dfb ldrb r3, [r7, #23] } 8002664: 4618 mov r0, r3 8002666: 371c adds r7, #28 8002668: 46bd mov sp, r7 800266a: bd90 pop {r4, r7, pc} 800266c: 20000008 .word 0x20000008 08002670 : * @brief Injected conversion complete callback in non blocking mode * @param hadc: ADC handle * @retval None */ __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) { 8002670: b480 push {r7} 8002672: b083 sub sp, #12 8002674: af00 add r7, sp, #0 8002676: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file */ } 8002678: bf00 nop 800267a: 370c adds r7, #12 800267c: 46bd mov sp, r7 800267e: bc80 pop {r7} 8002680: 4770 bx lr ... 08002684 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8002684: b480 push {r7} 8002686: b085 sub sp, #20 8002688: af00 add r7, sp, #0 800268a: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 800268c: 687b ldr r3, [r7, #4] 800268e: f003 0307 and.w r3, r3, #7 8002692: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 8002694: 4b0c ldr r3, [pc, #48] ; (80026c8 <__NVIC_SetPriorityGrouping+0x44>) 8002696: 68db ldr r3, [r3, #12] 8002698: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 800269a: 68ba ldr r2, [r7, #8] 800269c: f64f 03ff movw r3, #63743 ; 0xf8ff 80026a0: 4013 ands r3, r2 80026a2: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 80026a4: 68fb ldr r3, [r7, #12] 80026a6: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 80026a8: 68bb ldr r3, [r7, #8] 80026aa: 4313 orrs r3, r2 reg_value = (reg_value | 80026ac: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 80026b0: f443 3300 orr.w r3, r3, #131072 ; 0x20000 80026b4: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 80026b6: 4a04 ldr r2, [pc, #16] ; (80026c8 <__NVIC_SetPriorityGrouping+0x44>) 80026b8: 68bb ldr r3, [r7, #8] 80026ba: 60d3 str r3, [r2, #12] } 80026bc: bf00 nop 80026be: 3714 adds r7, #20 80026c0: 46bd mov sp, r7 80026c2: bc80 pop {r7} 80026c4: 4770 bx lr 80026c6: bf00 nop 80026c8: e000ed00 .word 0xe000ed00 080026cc <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 80026cc: b480 push {r7} 80026ce: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 80026d0: 4b04 ldr r3, [pc, #16] ; (80026e4 <__NVIC_GetPriorityGrouping+0x18>) 80026d2: 68db ldr r3, [r3, #12] 80026d4: 0a1b lsrs r3, r3, #8 80026d6: f003 0307 and.w r3, r3, #7 } 80026da: 4618 mov r0, r3 80026dc: 46bd mov sp, r7 80026de: bc80 pop {r7} 80026e0: 4770 bx lr 80026e2: bf00 nop 80026e4: e000ed00 .word 0xe000ed00 080026e8 <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 80026e8: b480 push {r7} 80026ea: b083 sub sp, #12 80026ec: af00 add r7, sp, #0 80026ee: 4603 mov r3, r0 80026f0: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 80026f2: f997 3007 ldrsb.w r3, [r7, #7] 80026f6: 2b00 cmp r3, #0 80026f8: db0b blt.n 8002712 <__NVIC_EnableIRQ+0x2a> { NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 80026fa: 79fb ldrb r3, [r7, #7] 80026fc: f003 021f and.w r2, r3, #31 8002700: 4906 ldr r1, [pc, #24] ; (800271c <__NVIC_EnableIRQ+0x34>) 8002702: f997 3007 ldrsb.w r3, [r7, #7] 8002706: 095b lsrs r3, r3, #5 8002708: 2001 movs r0, #1 800270a: fa00 f202 lsl.w r2, r0, r2 800270e: f841 2023 str.w r2, [r1, r3, lsl #2] } } 8002712: bf00 nop 8002714: 370c adds r7, #12 8002716: 46bd mov sp, r7 8002718: bc80 pop {r7} 800271a: 4770 bx lr 800271c: e000e100 .word 0xe000e100 08002720 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8002720: b480 push {r7} 8002722: b083 sub sp, #12 8002724: af00 add r7, sp, #0 8002726: 4603 mov r3, r0 8002728: 6039 str r1, [r7, #0] 800272a: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 800272c: f997 3007 ldrsb.w r3, [r7, #7] 8002730: 2b00 cmp r3, #0 8002732: db0a blt.n 800274a <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8002734: 683b ldr r3, [r7, #0] 8002736: b2da uxtb r2, r3 8002738: 490c ldr r1, [pc, #48] ; (800276c <__NVIC_SetPriority+0x4c>) 800273a: f997 3007 ldrsb.w r3, [r7, #7] 800273e: 0112 lsls r2, r2, #4 8002740: b2d2 uxtb r2, r2 8002742: 440b add r3, r1 8002744: f883 2300 strb.w r2, [r3, #768] ; 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 8002748: e00a b.n 8002760 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800274a: 683b ldr r3, [r7, #0] 800274c: b2da uxtb r2, r3 800274e: 4908 ldr r1, [pc, #32] ; (8002770 <__NVIC_SetPriority+0x50>) 8002750: 79fb ldrb r3, [r7, #7] 8002752: f003 030f and.w r3, r3, #15 8002756: 3b04 subs r3, #4 8002758: 0112 lsls r2, r2, #4 800275a: b2d2 uxtb r2, r2 800275c: 440b add r3, r1 800275e: 761a strb r2, [r3, #24] } 8002760: bf00 nop 8002762: 370c adds r7, #12 8002764: 46bd mov sp, r7 8002766: bc80 pop {r7} 8002768: 4770 bx lr 800276a: bf00 nop 800276c: e000e100 .word 0xe000e100 8002770: e000ed00 .word 0xe000ed00 08002774 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 8002774: b480 push {r7} 8002776: b089 sub sp, #36 ; 0x24 8002778: af00 add r7, sp, #0 800277a: 60f8 str r0, [r7, #12] 800277c: 60b9 str r1, [r7, #8] 800277e: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8002780: 68fb ldr r3, [r7, #12] 8002782: f003 0307 and.w r3, r3, #7 8002786: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8002788: 69fb ldr r3, [r7, #28] 800278a: f1c3 0307 rsb r3, r3, #7 800278e: 2b04 cmp r3, #4 8002790: bf28 it cs 8002792: 2304 movcs r3, #4 8002794: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8002796: 69fb ldr r3, [r7, #28] 8002798: 3304 adds r3, #4 800279a: 2b06 cmp r3, #6 800279c: d902 bls.n 80027a4 800279e: 69fb ldr r3, [r7, #28] 80027a0: 3b03 subs r3, #3 80027a2: e000 b.n 80027a6 80027a4: 2300 movs r3, #0 80027a6: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80027a8: f04f 32ff mov.w r2, #4294967295 80027ac: 69bb ldr r3, [r7, #24] 80027ae: fa02 f303 lsl.w r3, r2, r3 80027b2: 43da mvns r2, r3 80027b4: 68bb ldr r3, [r7, #8] 80027b6: 401a ands r2, r3 80027b8: 697b ldr r3, [r7, #20] 80027ba: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 80027bc: f04f 31ff mov.w r1, #4294967295 80027c0: 697b ldr r3, [r7, #20] 80027c2: fa01 f303 lsl.w r3, r1, r3 80027c6: 43d9 mvns r1, r3 80027c8: 687b ldr r3, [r7, #4] 80027ca: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80027cc: 4313 orrs r3, r2 ); } 80027ce: 4618 mov r0, r3 80027d0: 3724 adds r7, #36 ; 0x24 80027d2: 46bd mov sp, r7 80027d4: bc80 pop {r7} 80027d6: 4770 bx lr 080027d8 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 80027d8: b580 push {r7, lr} 80027da: b082 sub sp, #8 80027dc: af00 add r7, sp, #0 80027de: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 80027e0: 6878 ldr r0, [r7, #4] 80027e2: f7ff ff4f bl 8002684 <__NVIC_SetPriorityGrouping> } 80027e6: bf00 nop 80027e8: 3708 adds r7, #8 80027ea: 46bd mov sp, r7 80027ec: bd80 pop {r7, pc} 080027ee : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 80027ee: b580 push {r7, lr} 80027f0: b086 sub sp, #24 80027f2: af00 add r7, sp, #0 80027f4: 4603 mov r3, r0 80027f6: 60b9 str r1, [r7, #8] 80027f8: 607a str r2, [r7, #4] 80027fa: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 80027fc: 2300 movs r3, #0 80027fe: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8002800: f7ff ff64 bl 80026cc <__NVIC_GetPriorityGrouping> 8002804: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8002806: 687a ldr r2, [r7, #4] 8002808: 68b9 ldr r1, [r7, #8] 800280a: 6978 ldr r0, [r7, #20] 800280c: f7ff ffb2 bl 8002774 8002810: 4602 mov r2, r0 8002812: f997 300f ldrsb.w r3, [r7, #15] 8002816: 4611 mov r1, r2 8002818: 4618 mov r0, r3 800281a: f7ff ff81 bl 8002720 <__NVIC_SetPriority> } 800281e: bf00 nop 8002820: 3718 adds r7, #24 8002822: 46bd mov sp, r7 8002824: bd80 pop {r7, pc} 08002826 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 8002826: b580 push {r7, lr} 8002828: b082 sub sp, #8 800282a: af00 add r7, sp, #0 800282c: 4603 mov r3, r0 800282e: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 8002830: f997 3007 ldrsb.w r3, [r7, #7] 8002834: 4618 mov r0, r3 8002836: f7ff ff57 bl 80026e8 <__NVIC_EnableIRQ> } 800283a: bf00 nop 800283c: 3708 adds r7, #8 800283e: 46bd mov sp, r7 8002840: bd80 pop {r7, pc} ... 08002844 : * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { 8002844: b480 push {r7} 8002846: b085 sub sp, #20 8002848: af00 add r7, sp, #0 800284a: 6078 str r0, [r7, #4] uint32_t tmp = 0U; 800284c: 2300 movs r3, #0 800284e: 60fb str r3, [r7, #12] /* Check the DMA handle allocation */ if(hdma == NULL) 8002850: 687b ldr r3, [r7, #4] 8002852: 2b00 cmp r3, #0 8002854: d101 bne.n 800285a { return HAL_ERROR; 8002856: 2301 movs r3, #1 8002858: e043 b.n 80028e2 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; hdma->DmaBaseAddress = DMA2; } #else /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; 800285a: 687b ldr r3, [r7, #4] 800285c: 681b ldr r3, [r3, #0] 800285e: 461a mov r2, r3 8002860: 4b22 ldr r3, [pc, #136] ; (80028ec ) 8002862: 4413 add r3, r2 8002864: 4a22 ldr r2, [pc, #136] ; (80028f0 ) 8002866: fba2 2303 umull r2, r3, r2, r3 800286a: 091b lsrs r3, r3, #4 800286c: 009a lsls r2, r3, #2 800286e: 687b ldr r3, [r7, #4] 8002870: 641a str r2, [r3, #64] ; 0x40 hdma->DmaBaseAddress = DMA1; 8002872: 687b ldr r3, [r7, #4] 8002874: 4a1f ldr r2, [pc, #124] ; (80028f4 ) 8002876: 63da str r2, [r3, #60] ; 0x3c #endif /* DMA2 */ /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8002878: 687b ldr r3, [r7, #4] 800287a: 2202 movs r2, #2 800287c: f883 2021 strb.w r2, [r3, #33] ; 0x21 /* Get the CR register value */ tmp = hdma->Instance->CCR; 8002880: 687b ldr r3, [r7, #4] 8002882: 681b ldr r3, [r3, #0] 8002884: 681b ldr r3, [r3, #0] 8002886: 60fb str r3, [r7, #12] /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ 8002888: 68fb ldr r3, [r7, #12] 800288a: f423 537f bic.w r3, r3, #16320 ; 0x3fc0 800288e: f023 0330 bic.w r3, r3, #48 ; 0x30 8002892: 60fb str r3, [r7, #12] DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ DMA_CCR_DIR)); /* Prepare the DMA Channel configuration */ tmp |= hdma->Init.Direction | 8002894: 687b ldr r3, [r7, #4] 8002896: 685a ldr r2, [r3, #4] hdma->Init.PeriphInc | hdma->Init.MemInc | 8002898: 687b ldr r3, [r7, #4] 800289a: 689b ldr r3, [r3, #8] tmp |= hdma->Init.Direction | 800289c: 431a orrs r2, r3 hdma->Init.PeriphInc | hdma->Init.MemInc | 800289e: 687b ldr r3, [r7, #4] 80028a0: 68db ldr r3, [r3, #12] 80028a2: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 80028a4: 687b ldr r3, [r7, #4] 80028a6: 691b ldr r3, [r3, #16] hdma->Init.PeriphInc | hdma->Init.MemInc | 80028a8: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 80028aa: 687b ldr r3, [r7, #4] 80028ac: 695b ldr r3, [r3, #20] 80028ae: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 80028b0: 687b ldr r3, [r7, #4] 80028b2: 699b ldr r3, [r3, #24] hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 80028b4: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 80028b6: 687b ldr r3, [r7, #4] 80028b8: 69db ldr r3, [r3, #28] 80028ba: 4313 orrs r3, r2 tmp |= hdma->Init.Direction | 80028bc: 68fa ldr r2, [r7, #12] 80028be: 4313 orrs r3, r2 80028c0: 60fb str r3, [r7, #12] /* Write to DMA Channel CR register */ hdma->Instance->CCR = tmp; 80028c2: 687b ldr r3, [r7, #4] 80028c4: 681b ldr r3, [r3, #0] 80028c6: 68fa ldr r2, [r7, #12] 80028c8: 601a str r2, [r3, #0] /* Initialise the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 80028ca: 687b ldr r3, [r7, #4] 80028cc: 2200 movs r2, #0 80028ce: 639a str r2, [r3, #56] ; 0x38 /* Initialize the DMA state*/ hdma->State = HAL_DMA_STATE_READY; 80028d0: 687b ldr r3, [r7, #4] 80028d2: 2201 movs r2, #1 80028d4: f883 2021 strb.w r2, [r3, #33] ; 0x21 /* Allocate lock resource and initialize it */ hdma->Lock = HAL_UNLOCKED; 80028d8: 687b ldr r3, [r7, #4] 80028da: 2200 movs r2, #0 80028dc: f883 2020 strb.w r2, [r3, #32] return HAL_OK; 80028e0: 2300 movs r3, #0 } 80028e2: 4618 mov r0, r3 80028e4: 3714 adds r7, #20 80028e6: 46bd mov sp, r7 80028e8: bc80 pop {r7} 80028ea: 4770 bx lr 80028ec: bffdfff8 .word 0xbffdfff8 80028f0: cccccccd .word 0xcccccccd 80028f4: 40020000 .word 0x40020000 080028f8 : * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 80028f8: b580 push {r7, lr} 80028fa: b086 sub sp, #24 80028fc: af00 add r7, sp, #0 80028fe: 60f8 str r0, [r7, #12] 8002900: 60b9 str r1, [r7, #8] 8002902: 607a str r2, [r7, #4] 8002904: 603b str r3, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 8002906: 2300 movs r3, #0 8002908: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Process locked */ __HAL_LOCK(hdma); 800290a: 68fb ldr r3, [r7, #12] 800290c: f893 3020 ldrb.w r3, [r3, #32] 8002910: 2b01 cmp r3, #1 8002912: d101 bne.n 8002918 8002914: 2302 movs r3, #2 8002916: e04a b.n 80029ae 8002918: 68fb ldr r3, [r7, #12] 800291a: 2201 movs r2, #1 800291c: f883 2020 strb.w r2, [r3, #32] if(HAL_DMA_STATE_READY == hdma->State) 8002920: 68fb ldr r3, [r7, #12] 8002922: f893 3021 ldrb.w r3, [r3, #33] ; 0x21 8002926: 2b01 cmp r3, #1 8002928: d13a bne.n 80029a0 { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 800292a: 68fb ldr r3, [r7, #12] 800292c: 2202 movs r2, #2 800292e: f883 2021 strb.w r2, [r3, #33] ; 0x21 hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8002932: 68fb ldr r3, [r7, #12] 8002934: 2200 movs r2, #0 8002936: 639a str r2, [r3, #56] ; 0x38 /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); 8002938: 68fb ldr r3, [r7, #12] 800293a: 681b ldr r3, [r3, #0] 800293c: 681a ldr r2, [r3, #0] 800293e: 68fb ldr r3, [r7, #12] 8002940: 681b ldr r3, [r3, #0] 8002942: f022 0201 bic.w r2, r2, #1 8002946: 601a str r2, [r3, #0] /* Configure the source, destination address and the data length & clear flags*/ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); 8002948: 683b ldr r3, [r7, #0] 800294a: 687a ldr r2, [r7, #4] 800294c: 68b9 ldr r1, [r7, #8] 800294e: 68f8 ldr r0, [r7, #12] 8002950: f000 f9ae bl 8002cb0 /* Enable the transfer complete interrupt */ /* Enable the transfer Error interrupt */ if(NULL != hdma->XferHalfCpltCallback) 8002954: 68fb ldr r3, [r7, #12] 8002956: 6adb ldr r3, [r3, #44] ; 0x2c 8002958: 2b00 cmp r3, #0 800295a: d008 beq.n 800296e { /* Enable the Half transfer complete interrupt as well */ __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 800295c: 68fb ldr r3, [r7, #12] 800295e: 681b ldr r3, [r3, #0] 8002960: 681a ldr r2, [r3, #0] 8002962: 68fb ldr r3, [r7, #12] 8002964: 681b ldr r3, [r3, #0] 8002966: f042 020e orr.w r2, r2, #14 800296a: 601a str r2, [r3, #0] 800296c: e00f b.n 800298e } else { __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 800296e: 68fb ldr r3, [r7, #12] 8002970: 681b ldr r3, [r3, #0] 8002972: 681a ldr r2, [r3, #0] 8002974: 68fb ldr r3, [r7, #12] 8002976: 681b ldr r3, [r3, #0] 8002978: f022 0204 bic.w r2, r2, #4 800297c: 601a str r2, [r3, #0] __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); 800297e: 68fb ldr r3, [r7, #12] 8002980: 681b ldr r3, [r3, #0] 8002982: 681a ldr r2, [r3, #0] 8002984: 68fb ldr r3, [r7, #12] 8002986: 681b ldr r3, [r3, #0] 8002988: f042 020a orr.w r2, r2, #10 800298c: 601a str r2, [r3, #0] } /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); 800298e: 68fb ldr r3, [r7, #12] 8002990: 681b ldr r3, [r3, #0] 8002992: 681a ldr r2, [r3, #0] 8002994: 68fb ldr r3, [r7, #12] 8002996: 681b ldr r3, [r3, #0] 8002998: f042 0201 orr.w r2, r2, #1 800299c: 601a str r2, [r3, #0] 800299e: e005 b.n 80029ac } else { /* Process Unlocked */ __HAL_UNLOCK(hdma); 80029a0: 68fb ldr r3, [r7, #12] 80029a2: 2200 movs r2, #0 80029a4: f883 2020 strb.w r2, [r3, #32] /* Remain BUSY */ status = HAL_BUSY; 80029a8: 2302 movs r3, #2 80029aa: 75fb strb r3, [r7, #23] } return status; 80029ac: 7dfb ldrb r3, [r7, #23] } 80029ae: 4618 mov r0, r3 80029b0: 3718 adds r7, #24 80029b2: 46bd mov sp, r7 80029b4: bd80 pop {r7, pc} ... 080029b8 : * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 80029b8: b580 push {r7, lr} 80029ba: b084 sub sp, #16 80029bc: af00 add r7, sp, #0 80029be: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 80029c0: 2300 movs r3, #0 80029c2: 73fb strb r3, [r7, #15] if(HAL_DMA_STATE_BUSY != hdma->State) 80029c4: 687b ldr r3, [r7, #4] 80029c6: f893 3021 ldrb.w r3, [r3, #33] ; 0x21 80029ca: 2b02 cmp r3, #2 80029cc: d005 beq.n 80029da { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 80029ce: 687b ldr r3, [r7, #4] 80029d0: 2204 movs r2, #4 80029d2: 639a str r2, [r3, #56] ; 0x38 status = HAL_ERROR; 80029d4: 2301 movs r3, #1 80029d6: 73fb strb r3, [r7, #15] 80029d8: e051 b.n 8002a7e } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 80029da: 687b ldr r3, [r7, #4] 80029dc: 681b ldr r3, [r3, #0] 80029de: 681a ldr r2, [r3, #0] 80029e0: 687b ldr r3, [r7, #4] 80029e2: 681b ldr r3, [r3, #0] 80029e4: f022 020e bic.w r2, r2, #14 80029e8: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 80029ea: 687b ldr r3, [r7, #4] 80029ec: 681b ldr r3, [r3, #0] 80029ee: 681a ldr r2, [r3, #0] 80029f0: 687b ldr r3, [r7, #4] 80029f2: 681b ldr r3, [r3, #0] 80029f4: f022 0201 bic.w r2, r2, #1 80029f8: 601a str r2, [r3, #0] /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); 80029fa: 687b ldr r3, [r7, #4] 80029fc: 681b ldr r3, [r3, #0] 80029fe: 4a22 ldr r2, [pc, #136] ; (8002a88 ) 8002a00: 4293 cmp r3, r2 8002a02: d029 beq.n 8002a58 8002a04: 687b ldr r3, [r7, #4] 8002a06: 681b ldr r3, [r3, #0] 8002a08: 4a20 ldr r2, [pc, #128] ; (8002a8c ) 8002a0a: 4293 cmp r3, r2 8002a0c: d022 beq.n 8002a54 8002a0e: 687b ldr r3, [r7, #4] 8002a10: 681b ldr r3, [r3, #0] 8002a12: 4a1f ldr r2, [pc, #124] ; (8002a90 ) 8002a14: 4293 cmp r3, r2 8002a16: d01a beq.n 8002a4e 8002a18: 687b ldr r3, [r7, #4] 8002a1a: 681b ldr r3, [r3, #0] 8002a1c: 4a1d ldr r2, [pc, #116] ; (8002a94 ) 8002a1e: 4293 cmp r3, r2 8002a20: d012 beq.n 8002a48 8002a22: 687b ldr r3, [r7, #4] 8002a24: 681b ldr r3, [r3, #0] 8002a26: 4a1c ldr r2, [pc, #112] ; (8002a98 ) 8002a28: 4293 cmp r3, r2 8002a2a: d00a beq.n 8002a42 8002a2c: 687b ldr r3, [r7, #4] 8002a2e: 681b ldr r3, [r3, #0] 8002a30: 4a1a ldr r2, [pc, #104] ; (8002a9c ) 8002a32: 4293 cmp r3, r2 8002a34: d102 bne.n 8002a3c 8002a36: f44f 1380 mov.w r3, #1048576 ; 0x100000 8002a3a: e00e b.n 8002a5a 8002a3c: f04f 7380 mov.w r3, #16777216 ; 0x1000000 8002a40: e00b b.n 8002a5a 8002a42: f44f 3380 mov.w r3, #65536 ; 0x10000 8002a46: e008 b.n 8002a5a 8002a48: f44f 5380 mov.w r3, #4096 ; 0x1000 8002a4c: e005 b.n 8002a5a 8002a4e: f44f 7380 mov.w r3, #256 ; 0x100 8002a52: e002 b.n 8002a5a 8002a54: 2310 movs r3, #16 8002a56: e000 b.n 8002a5a 8002a58: 2301 movs r3, #1 8002a5a: 4a11 ldr r2, [pc, #68] ; (8002aa0 ) 8002a5c: 6053 str r3, [r2, #4] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8002a5e: 687b ldr r3, [r7, #4] 8002a60: 2201 movs r2, #1 8002a62: f883 2021 strb.w r2, [r3, #33] ; 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8002a66: 687b ldr r3, [r7, #4] 8002a68: 2200 movs r2, #0 8002a6a: f883 2020 strb.w r2, [r3, #32] /* Call User Abort callback */ if(hdma->XferAbortCallback != NULL) 8002a6e: 687b ldr r3, [r7, #4] 8002a70: 6b5b ldr r3, [r3, #52] ; 0x34 8002a72: 2b00 cmp r3, #0 8002a74: d003 beq.n 8002a7e { hdma->XferAbortCallback(hdma); 8002a76: 687b ldr r3, [r7, #4] 8002a78: 6b5b ldr r3, [r3, #52] ; 0x34 8002a7a: 6878 ldr r0, [r7, #4] 8002a7c: 4798 blx r3 } } return status; 8002a7e: 7bfb ldrb r3, [r7, #15] } 8002a80: 4618 mov r0, r3 8002a82: 3710 adds r7, #16 8002a84: 46bd mov sp, r7 8002a86: bd80 pop {r7, pc} 8002a88: 40020008 .word 0x40020008 8002a8c: 4002001c .word 0x4002001c 8002a90: 40020030 .word 0x40020030 8002a94: 40020044 .word 0x40020044 8002a98: 40020058 .word 0x40020058 8002a9c: 4002006c .word 0x4002006c 8002aa0: 40020000 .word 0x40020000 08002aa4 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { 8002aa4: b580 push {r7, lr} 8002aa6: b084 sub sp, #16 8002aa8: af00 add r7, sp, #0 8002aaa: 6078 str r0, [r7, #4] uint32_t flag_it = hdma->DmaBaseAddress->ISR; 8002aac: 687b ldr r3, [r7, #4] 8002aae: 6bdb ldr r3, [r3, #60] ; 0x3c 8002ab0: 681b ldr r3, [r3, #0] 8002ab2: 60fb str r3, [r7, #12] uint32_t source_it = hdma->Instance->CCR; 8002ab4: 687b ldr r3, [r7, #4] 8002ab6: 681b ldr r3, [r3, #0] 8002ab8: 681b ldr r3, [r3, #0] 8002aba: 60bb str r3, [r7, #8] /* Half Transfer Complete Interrupt management ******************************/ if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET)) 8002abc: 687b ldr r3, [r7, #4] 8002abe: 6c1b ldr r3, [r3, #64] ; 0x40 8002ac0: 2204 movs r2, #4 8002ac2: 409a lsls r2, r3 8002ac4: 68fb ldr r3, [r7, #12] 8002ac6: 4013 ands r3, r2 8002ac8: 2b00 cmp r3, #0 8002aca: d04f beq.n 8002b6c 8002acc: 68bb ldr r3, [r7, #8] 8002ace: f003 0304 and.w r3, r3, #4 8002ad2: 2b00 cmp r3, #0 8002ad4: d04a beq.n 8002b6c { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 8002ad6: 687b ldr r3, [r7, #4] 8002ad8: 681b ldr r3, [r3, #0] 8002ada: 681b ldr r3, [r3, #0] 8002adc: f003 0320 and.w r3, r3, #32 8002ae0: 2b00 cmp r3, #0 8002ae2: d107 bne.n 8002af4 { /* Disable the half transfer interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 8002ae4: 687b ldr r3, [r7, #4] 8002ae6: 681b ldr r3, [r3, #0] 8002ae8: 681a ldr r2, [r3, #0] 8002aea: 687b ldr r3, [r7, #4] 8002aec: 681b ldr r3, [r3, #0] 8002aee: f022 0204 bic.w r2, r2, #4 8002af2: 601a str r2, [r3, #0] } /* Clear the half transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); 8002af4: 687b ldr r3, [r7, #4] 8002af6: 681b ldr r3, [r3, #0] 8002af8: 4a66 ldr r2, [pc, #408] ; (8002c94 ) 8002afa: 4293 cmp r3, r2 8002afc: d029 beq.n 8002b52 8002afe: 687b ldr r3, [r7, #4] 8002b00: 681b ldr r3, [r3, #0] 8002b02: 4a65 ldr r2, [pc, #404] ; (8002c98 ) 8002b04: 4293 cmp r3, r2 8002b06: d022 beq.n 8002b4e 8002b08: 687b ldr r3, [r7, #4] 8002b0a: 681b ldr r3, [r3, #0] 8002b0c: 4a63 ldr r2, [pc, #396] ; (8002c9c ) 8002b0e: 4293 cmp r3, r2 8002b10: d01a beq.n 8002b48 8002b12: 687b ldr r3, [r7, #4] 8002b14: 681b ldr r3, [r3, #0] 8002b16: 4a62 ldr r2, [pc, #392] ; (8002ca0 ) 8002b18: 4293 cmp r3, r2 8002b1a: d012 beq.n 8002b42 8002b1c: 687b ldr r3, [r7, #4] 8002b1e: 681b ldr r3, [r3, #0] 8002b20: 4a60 ldr r2, [pc, #384] ; (8002ca4 ) 8002b22: 4293 cmp r3, r2 8002b24: d00a beq.n 8002b3c 8002b26: 687b ldr r3, [r7, #4] 8002b28: 681b ldr r3, [r3, #0] 8002b2a: 4a5f ldr r2, [pc, #380] ; (8002ca8 ) 8002b2c: 4293 cmp r3, r2 8002b2e: d102 bne.n 8002b36 8002b30: f44f 0380 mov.w r3, #4194304 ; 0x400000 8002b34: e00e b.n 8002b54 8002b36: f04f 6380 mov.w r3, #67108864 ; 0x4000000 8002b3a: e00b b.n 8002b54 8002b3c: f44f 2380 mov.w r3, #262144 ; 0x40000 8002b40: e008 b.n 8002b54 8002b42: f44f 4380 mov.w r3, #16384 ; 0x4000 8002b46: e005 b.n 8002b54 8002b48: f44f 6380 mov.w r3, #1024 ; 0x400 8002b4c: e002 b.n 8002b54 8002b4e: 2340 movs r3, #64 ; 0x40 8002b50: e000 b.n 8002b54 8002b52: 2304 movs r3, #4 8002b54: 4a55 ldr r2, [pc, #340] ; (8002cac ) 8002b56: 6053 str r3, [r2, #4] /* DMA peripheral state is not updated in Half Transfer */ /* but in Transfer Complete case */ if(hdma->XferHalfCpltCallback != NULL) 8002b58: 687b ldr r3, [r7, #4] 8002b5a: 6adb ldr r3, [r3, #44] ; 0x2c 8002b5c: 2b00 cmp r3, #0 8002b5e: f000 8094 beq.w 8002c8a { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 8002b62: 687b ldr r3, [r7, #4] 8002b64: 6adb ldr r3, [r3, #44] ; 0x2c 8002b66: 6878 ldr r0, [r7, #4] 8002b68: 4798 blx r3 if(hdma->XferHalfCpltCallback != NULL) 8002b6a: e08e b.n 8002c8a } } /* Transfer Complete Interrupt management ***********************************/ else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET)) 8002b6c: 687b ldr r3, [r7, #4] 8002b6e: 6c1b ldr r3, [r3, #64] ; 0x40 8002b70: 2202 movs r2, #2 8002b72: 409a lsls r2, r3 8002b74: 68fb ldr r3, [r7, #12] 8002b76: 4013 ands r3, r2 8002b78: 2b00 cmp r3, #0 8002b7a: d056 beq.n 8002c2a 8002b7c: 68bb ldr r3, [r7, #8] 8002b7e: f003 0302 and.w r3, r3, #2 8002b82: 2b00 cmp r3, #0 8002b84: d051 beq.n 8002c2a { if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 8002b86: 687b ldr r3, [r7, #4] 8002b88: 681b ldr r3, [r3, #0] 8002b8a: 681b ldr r3, [r3, #0] 8002b8c: f003 0320 and.w r3, r3, #32 8002b90: 2b00 cmp r3, #0 8002b92: d10b bne.n 8002bac { /* Disable the transfer complete and error interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); 8002b94: 687b ldr r3, [r7, #4] 8002b96: 681b ldr r3, [r3, #0] 8002b98: 681a ldr r2, [r3, #0] 8002b9a: 687b ldr r3, [r7, #4] 8002b9c: 681b ldr r3, [r3, #0] 8002b9e: f022 020a bic.w r2, r2, #10 8002ba2: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8002ba4: 687b ldr r3, [r7, #4] 8002ba6: 2201 movs r2, #1 8002ba8: f883 2021 strb.w r2, [r3, #33] ; 0x21 } /* Clear the transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); 8002bac: 687b ldr r3, [r7, #4] 8002bae: 681b ldr r3, [r3, #0] 8002bb0: 4a38 ldr r2, [pc, #224] ; (8002c94 ) 8002bb2: 4293 cmp r3, r2 8002bb4: d029 beq.n 8002c0a 8002bb6: 687b ldr r3, [r7, #4] 8002bb8: 681b ldr r3, [r3, #0] 8002bba: 4a37 ldr r2, [pc, #220] ; (8002c98 ) 8002bbc: 4293 cmp r3, r2 8002bbe: d022 beq.n 8002c06 8002bc0: 687b ldr r3, [r7, #4] 8002bc2: 681b ldr r3, [r3, #0] 8002bc4: 4a35 ldr r2, [pc, #212] ; (8002c9c ) 8002bc6: 4293 cmp r3, r2 8002bc8: d01a beq.n 8002c00 8002bca: 687b ldr r3, [r7, #4] 8002bcc: 681b ldr r3, [r3, #0] 8002bce: 4a34 ldr r2, [pc, #208] ; (8002ca0 ) 8002bd0: 4293 cmp r3, r2 8002bd2: d012 beq.n 8002bfa 8002bd4: 687b ldr r3, [r7, #4] 8002bd6: 681b ldr r3, [r3, #0] 8002bd8: 4a32 ldr r2, [pc, #200] ; (8002ca4 ) 8002bda: 4293 cmp r3, r2 8002bdc: d00a beq.n 8002bf4 8002bde: 687b ldr r3, [r7, #4] 8002be0: 681b ldr r3, [r3, #0] 8002be2: 4a31 ldr r2, [pc, #196] ; (8002ca8 ) 8002be4: 4293 cmp r3, r2 8002be6: d102 bne.n 8002bee 8002be8: f44f 1300 mov.w r3, #2097152 ; 0x200000 8002bec: e00e b.n 8002c0c 8002bee: f04f 7300 mov.w r3, #33554432 ; 0x2000000 8002bf2: e00b b.n 8002c0c 8002bf4: f44f 3300 mov.w r3, #131072 ; 0x20000 8002bf8: e008 b.n 8002c0c 8002bfa: f44f 5300 mov.w r3, #8192 ; 0x2000 8002bfe: e005 b.n 8002c0c 8002c00: f44f 7300 mov.w r3, #512 ; 0x200 8002c04: e002 b.n 8002c0c 8002c06: 2320 movs r3, #32 8002c08: e000 b.n 8002c0c 8002c0a: 2302 movs r3, #2 8002c0c: 4a27 ldr r2, [pc, #156] ; (8002cac ) 8002c0e: 6053 str r3, [r2, #4] /* Process Unlocked */ __HAL_UNLOCK(hdma); 8002c10: 687b ldr r3, [r7, #4] 8002c12: 2200 movs r2, #0 8002c14: f883 2020 strb.w r2, [r3, #32] if(hdma->XferCpltCallback != NULL) 8002c18: 687b ldr r3, [r7, #4] 8002c1a: 6a9b ldr r3, [r3, #40] ; 0x28 8002c1c: 2b00 cmp r3, #0 8002c1e: d034 beq.n 8002c8a { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 8002c20: 687b ldr r3, [r7, #4] 8002c22: 6a9b ldr r3, [r3, #40] ; 0x28 8002c24: 6878 ldr r0, [r7, #4] 8002c26: 4798 blx r3 if(hdma->XferCpltCallback != NULL) 8002c28: e02f b.n 8002c8a } } /* Transfer Error Interrupt management **************************************/ else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE))) 8002c2a: 687b ldr r3, [r7, #4] 8002c2c: 6c1b ldr r3, [r3, #64] ; 0x40 8002c2e: 2208 movs r2, #8 8002c30: 409a lsls r2, r3 8002c32: 68fb ldr r3, [r7, #12] 8002c34: 4013 ands r3, r2 8002c36: 2b00 cmp r3, #0 8002c38: d028 beq.n 8002c8c 8002c3a: 68bb ldr r3, [r7, #8] 8002c3c: f003 0308 and.w r3, r3, #8 8002c40: 2b00 cmp r3, #0 8002c42: d023 beq.n 8002c8c { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ /* Disable ALL DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8002c44: 687b ldr r3, [r7, #4] 8002c46: 681b ldr r3, [r3, #0] 8002c48: 681a ldr r2, [r3, #0] 8002c4a: 687b ldr r3, [r7, #4] 8002c4c: 681b ldr r3, [r3, #0] 8002c4e: f022 020e bic.w r2, r2, #14 8002c52: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); 8002c54: 687b ldr r3, [r7, #4] 8002c56: 6c1a ldr r2, [r3, #64] ; 0x40 8002c58: 687b ldr r3, [r7, #4] 8002c5a: 6bdb ldr r3, [r3, #60] ; 0x3c 8002c5c: 2101 movs r1, #1 8002c5e: fa01 f202 lsl.w r2, r1, r2 8002c62: 605a str r2, [r3, #4] /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; 8002c64: 687b ldr r3, [r7, #4] 8002c66: 2201 movs r2, #1 8002c68: 639a str r2, [r3, #56] ; 0x38 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8002c6a: 687b ldr r3, [r7, #4] 8002c6c: 2201 movs r2, #1 8002c6e: f883 2021 strb.w r2, [r3, #33] ; 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8002c72: 687b ldr r3, [r7, #4] 8002c74: 2200 movs r2, #0 8002c76: f883 2020 strb.w r2, [r3, #32] if (hdma->XferErrorCallback != NULL) 8002c7a: 687b ldr r3, [r7, #4] 8002c7c: 6b1b ldr r3, [r3, #48] ; 0x30 8002c7e: 2b00 cmp r3, #0 8002c80: d004 beq.n 8002c8c { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 8002c82: 687b ldr r3, [r7, #4] 8002c84: 6b1b ldr r3, [r3, #48] ; 0x30 8002c86: 6878 ldr r0, [r7, #4] 8002c88: 4798 blx r3 } } return; 8002c8a: bf00 nop 8002c8c: bf00 nop } 8002c8e: 3710 adds r7, #16 8002c90: 46bd mov sp, r7 8002c92: bd80 pop {r7, pc} 8002c94: 40020008 .word 0x40020008 8002c98: 4002001c .word 0x4002001c 8002c9c: 40020030 .word 0x40020030 8002ca0: 40020044 .word 0x40020044 8002ca4: 40020058 .word 0x40020058 8002ca8: 4002006c .word 0x4002006c 8002cac: 40020000 .word 0x40020000 08002cb0 : * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval HAL status */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 8002cb0: b480 push {r7} 8002cb2: b085 sub sp, #20 8002cb4: af00 add r7, sp, #0 8002cb6: 60f8 str r0, [r7, #12] 8002cb8: 60b9 str r1, [r7, #8] 8002cba: 607a str r2, [r7, #4] 8002cbc: 603b str r3, [r7, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); 8002cbe: 68fb ldr r3, [r7, #12] 8002cc0: 6c1a ldr r2, [r3, #64] ; 0x40 8002cc2: 68fb ldr r3, [r7, #12] 8002cc4: 6bdb ldr r3, [r3, #60] ; 0x3c 8002cc6: 2101 movs r1, #1 8002cc8: fa01 f202 lsl.w r2, r1, r2 8002ccc: 605a str r2, [r3, #4] /* Configure DMA Channel data length */ hdma->Instance->CNDTR = DataLength; 8002cce: 68fb ldr r3, [r7, #12] 8002cd0: 681b ldr r3, [r3, #0] 8002cd2: 683a ldr r2, [r7, #0] 8002cd4: 605a str r2, [r3, #4] /* Memory to Peripheral */ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 8002cd6: 68fb ldr r3, [r7, #12] 8002cd8: 685b ldr r3, [r3, #4] 8002cda: 2b10 cmp r3, #16 8002cdc: d108 bne.n 8002cf0 { /* Configure DMA Channel destination address */ hdma->Instance->CPAR = DstAddress; 8002cde: 68fb ldr r3, [r7, #12] 8002ce0: 681b ldr r3, [r3, #0] 8002ce2: 687a ldr r2, [r7, #4] 8002ce4: 609a str r2, [r3, #8] /* Configure DMA Channel source address */ hdma->Instance->CMAR = SrcAddress; 8002ce6: 68fb ldr r3, [r7, #12] 8002ce8: 681b ldr r3, [r3, #0] 8002cea: 68ba ldr r2, [r7, #8] 8002cec: 60da str r2, [r3, #12] hdma->Instance->CPAR = SrcAddress; /* Configure DMA Channel destination address */ hdma->Instance->CMAR = DstAddress; } } 8002cee: e007 b.n 8002d00 hdma->Instance->CPAR = SrcAddress; 8002cf0: 68fb ldr r3, [r7, #12] 8002cf2: 681b ldr r3, [r3, #0] 8002cf4: 68ba ldr r2, [r7, #8] 8002cf6: 609a str r2, [r3, #8] hdma->Instance->CMAR = DstAddress; 8002cf8: 68fb ldr r3, [r7, #12] 8002cfa: 681b ldr r3, [r3, #0] 8002cfc: 687a ldr r2, [r7, #4] 8002cfe: 60da str r2, [r3, #12] } 8002d00: bf00 nop 8002d02: 3714 adds r7, #20 8002d04: 46bd mov sp, r7 8002d06: bc80 pop {r7} 8002d08: 4770 bx lr ... 08002d0c : * @param Data: Specifies the data to be programmed * * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) { 8002d0c: b5f0 push {r4, r5, r6, r7, lr} 8002d0e: b087 sub sp, #28 8002d10: af00 add r7, sp, #0 8002d12: 60f8 str r0, [r7, #12] 8002d14: 60b9 str r1, [r7, #8] 8002d16: e9c7 2300 strd r2, r3, [r7] HAL_StatusTypeDef status = HAL_ERROR; 8002d1a: 2301 movs r3, #1 8002d1c: 75fb strb r3, [r7, #23] uint8_t index = 0; 8002d1e: 2300 movs r3, #0 8002d20: 75bb strb r3, [r7, #22] uint8_t nbiterations = 0; 8002d22: 2300 movs r3, #0 8002d24: 757b strb r3, [r7, #21] /* Process Locked */ __HAL_LOCK(&pFlash); 8002d26: 4b2f ldr r3, [pc, #188] ; (8002de4 ) 8002d28: 7e1b ldrb r3, [r3, #24] 8002d2a: 2b01 cmp r3, #1 8002d2c: d101 bne.n 8002d32 8002d2e: 2302 movs r3, #2 8002d30: e054 b.n 8002ddc 8002d32: 4b2c ldr r3, [pc, #176] ; (8002de4 ) 8002d34: 2201 movs r2, #1 8002d36: 761a strb r2, [r3, #24] #if defined(FLASH_BANK2_END) if(Address <= FLASH_BANK1_END) { #endif /* FLASH_BANK2_END */ /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); 8002d38: f24c 3050 movw r0, #50000 ; 0xc350 8002d3c: f000 f8a8 bl 8002e90 8002d40: 4603 mov r3, r0 8002d42: 75fb strb r3, [r7, #23] /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperationBank2(FLASH_TIMEOUT_VALUE); } #endif /* FLASH_BANK2_END */ if(status == HAL_OK) 8002d44: 7dfb ldrb r3, [r7, #23] 8002d46: 2b00 cmp r3, #0 8002d48: d144 bne.n 8002dd4 { if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) 8002d4a: 68fb ldr r3, [r7, #12] 8002d4c: 2b01 cmp r3, #1 8002d4e: d102 bne.n 8002d56 { /* Program halfword (16-bit) at a specified address. */ nbiterations = 1U; 8002d50: 2301 movs r3, #1 8002d52: 757b strb r3, [r7, #21] 8002d54: e007 b.n 8002d66 } else if(TypeProgram == FLASH_TYPEPROGRAM_WORD) 8002d56: 68fb ldr r3, [r7, #12] 8002d58: 2b02 cmp r3, #2 8002d5a: d102 bne.n 8002d62 { /* Program word (32-bit = 2*16-bit) at a specified address. */ nbiterations = 2U; 8002d5c: 2302 movs r3, #2 8002d5e: 757b strb r3, [r7, #21] 8002d60: e001 b.n 8002d66 } else { /* Program double word (64-bit = 4*16-bit) at a specified address. */ nbiterations = 4U; 8002d62: 2304 movs r3, #4 8002d64: 757b strb r3, [r7, #21] } for (index = 0U; index < nbiterations; index++) 8002d66: 2300 movs r3, #0 8002d68: 75bb strb r3, [r7, #22] 8002d6a: e02d b.n 8002dc8 { FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index))); 8002d6c: 7dbb ldrb r3, [r7, #22] 8002d6e: 005a lsls r2, r3, #1 8002d70: 68bb ldr r3, [r7, #8] 8002d72: eb02 0c03 add.w ip, r2, r3 8002d76: 7dbb ldrb r3, [r7, #22] 8002d78: 0119 lsls r1, r3, #4 8002d7a: e9d7 2300 ldrd r2, r3, [r7] 8002d7e: f1c1 0620 rsb r6, r1, #32 8002d82: f1a1 0020 sub.w r0, r1, #32 8002d86: fa22 f401 lsr.w r4, r2, r1 8002d8a: fa03 f606 lsl.w r6, r3, r6 8002d8e: 4334 orrs r4, r6 8002d90: fa23 f000 lsr.w r0, r3, r0 8002d94: 4304 orrs r4, r0 8002d96: fa23 f501 lsr.w r5, r3, r1 8002d9a: b2a3 uxth r3, r4 8002d9c: 4619 mov r1, r3 8002d9e: 4660 mov r0, ip 8002da0: f000 f85a bl 8002e58 #if defined(FLASH_BANK2_END) if(Address <= FLASH_BANK1_END) { #endif /* FLASH_BANK2_END */ /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); 8002da4: f24c 3050 movw r0, #50000 ; 0xc350 8002da8: f000 f872 bl 8002e90 8002dac: 4603 mov r3, r0 8002dae: 75fb strb r3, [r7, #23] /* If the program operation is completed, disable the PG Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_PG); 8002db0: 4b0d ldr r3, [pc, #52] ; (8002de8 ) 8002db2: 691b ldr r3, [r3, #16] 8002db4: 4a0c ldr r2, [pc, #48] ; (8002de8 ) 8002db6: f023 0301 bic.w r3, r3, #1 8002dba: 6113 str r3, [r2, #16] /* If the program operation is completed, disable the PG Bit */ CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG); } #endif /* FLASH_BANK2_END */ /* In case of error, stop programation procedure */ if (status != HAL_OK) 8002dbc: 7dfb ldrb r3, [r7, #23] 8002dbe: 2b00 cmp r3, #0 8002dc0: d107 bne.n 8002dd2 for (index = 0U; index < nbiterations; index++) 8002dc2: 7dbb ldrb r3, [r7, #22] 8002dc4: 3301 adds r3, #1 8002dc6: 75bb strb r3, [r7, #22] 8002dc8: 7dba ldrb r2, [r7, #22] 8002dca: 7d7b ldrb r3, [r7, #21] 8002dcc: 429a cmp r2, r3 8002dce: d3cd bcc.n 8002d6c 8002dd0: e000 b.n 8002dd4 { break; 8002dd2: bf00 nop } } } /* Process Unlocked */ __HAL_UNLOCK(&pFlash); 8002dd4: 4b03 ldr r3, [pc, #12] ; (8002de4 ) 8002dd6: 2200 movs r2, #0 8002dd8: 761a strb r2, [r3, #24] return status; 8002dda: 7dfb ldrb r3, [r7, #23] } 8002ddc: 4618 mov r0, r3 8002dde: 371c adds r7, #28 8002de0: 46bd mov sp, r7 8002de2: bdf0 pop {r4, r5, r6, r7, pc} 8002de4: 200008f0 .word 0x200008f0 8002de8: 40022000 .word 0x40022000 08002dec : /** * @brief Unlock the FLASH control register access * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_Unlock(void) { 8002dec: b480 push {r7} 8002dee: b083 sub sp, #12 8002df0: af00 add r7, sp, #0 HAL_StatusTypeDef status = HAL_OK; 8002df2: 2300 movs r3, #0 8002df4: 71fb strb r3, [r7, #7] if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) 8002df6: 4b0d ldr r3, [pc, #52] ; (8002e2c ) 8002df8: 691b ldr r3, [r3, #16] 8002dfa: f003 0380 and.w r3, r3, #128 ; 0x80 8002dfe: 2b00 cmp r3, #0 8002e00: d00d beq.n 8002e1e { /* Authorize the FLASH Registers access */ WRITE_REG(FLASH->KEYR, FLASH_KEY1); 8002e02: 4b0a ldr r3, [pc, #40] ; (8002e2c ) 8002e04: 4a0a ldr r2, [pc, #40] ; (8002e30 ) 8002e06: 605a str r2, [r3, #4] WRITE_REG(FLASH->KEYR, FLASH_KEY2); 8002e08: 4b08 ldr r3, [pc, #32] ; (8002e2c ) 8002e0a: 4a0a ldr r2, [pc, #40] ; (8002e34 ) 8002e0c: 605a str r2, [r3, #4] /* Verify Flash is unlocked */ if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) 8002e0e: 4b07 ldr r3, [pc, #28] ; (8002e2c ) 8002e10: 691b ldr r3, [r3, #16] 8002e12: f003 0380 and.w r3, r3, #128 ; 0x80 8002e16: 2b00 cmp r3, #0 8002e18: d001 beq.n 8002e1e { status = HAL_ERROR; 8002e1a: 2301 movs r3, #1 8002e1c: 71fb strb r3, [r7, #7] status = HAL_ERROR; } } #endif /* FLASH_BANK2_END */ return status; 8002e1e: 79fb ldrb r3, [r7, #7] } 8002e20: 4618 mov r0, r3 8002e22: 370c adds r7, #12 8002e24: 46bd mov sp, r7 8002e26: bc80 pop {r7} 8002e28: 4770 bx lr 8002e2a: bf00 nop 8002e2c: 40022000 .word 0x40022000 8002e30: 45670123 .word 0x45670123 8002e34: cdef89ab .word 0xcdef89ab 08002e38 : /** * @brief Locks the FLASH control register access * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_Lock(void) { 8002e38: b480 push {r7} 8002e3a: af00 add r7, sp, #0 /* Set the LOCK Bit to lock the FLASH Registers access */ SET_BIT(FLASH->CR, FLASH_CR_LOCK); 8002e3c: 4b05 ldr r3, [pc, #20] ; (8002e54 ) 8002e3e: 691b ldr r3, [r3, #16] 8002e40: 4a04 ldr r2, [pc, #16] ; (8002e54 ) 8002e42: f043 0380 orr.w r3, r3, #128 ; 0x80 8002e46: 6113 str r3, [r2, #16] #if defined(FLASH_BANK2_END) /* Set the LOCK Bit to lock the FLASH BANK2 Registers access */ SET_BIT(FLASH->CR2, FLASH_CR2_LOCK); #endif /* FLASH_BANK2_END */ return HAL_OK; 8002e48: 2300 movs r3, #0 } 8002e4a: 4618 mov r0, r3 8002e4c: 46bd mov sp, r7 8002e4e: bc80 pop {r7} 8002e50: 4770 bx lr 8002e52: bf00 nop 8002e54: 40022000 .word 0x40022000 08002e58 : * @param Address specify the address to be programmed. * @param Data specify the data to be programmed. * @retval None */ static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) { 8002e58: b480 push {r7} 8002e5a: b083 sub sp, #12 8002e5c: af00 add r7, sp, #0 8002e5e: 6078 str r0, [r7, #4] 8002e60: 460b mov r3, r1 8002e62: 807b strh r3, [r7, #2] /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; 8002e64: 4b08 ldr r3, [pc, #32] ; (8002e88 ) 8002e66: 2200 movs r2, #0 8002e68: 61da str r2, [r3, #28] #if defined(FLASH_BANK2_END) if(Address <= FLASH_BANK1_END) { #endif /* FLASH_BANK2_END */ /* Proceed to program the new data */ SET_BIT(FLASH->CR, FLASH_CR_PG); 8002e6a: 4b08 ldr r3, [pc, #32] ; (8002e8c ) 8002e6c: 691b ldr r3, [r3, #16] 8002e6e: 4a07 ldr r2, [pc, #28] ; (8002e8c ) 8002e70: f043 0301 orr.w r3, r3, #1 8002e74: 6113 str r3, [r2, #16] SET_BIT(FLASH->CR2, FLASH_CR2_PG); } #endif /* FLASH_BANK2_END */ /* Write data in the address */ *(__IO uint16_t*)Address = Data; 8002e76: 687b ldr r3, [r7, #4] 8002e78: 887a ldrh r2, [r7, #2] 8002e7a: 801a strh r2, [r3, #0] } 8002e7c: bf00 nop 8002e7e: 370c adds r7, #12 8002e80: 46bd mov sp, r7 8002e82: bc80 pop {r7} 8002e84: 4770 bx lr 8002e86: bf00 nop 8002e88: 200008f0 .word 0x200008f0 8002e8c: 40022000 .word 0x40022000 08002e90 : * @brief Wait for a FLASH operation to complete. * @param Timeout maximum flash operation timeout * @retval HAL Status */ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) { 8002e90: b580 push {r7, lr} 8002e92: b084 sub sp, #16 8002e94: af00 add r7, sp, #0 8002e96: 6078 str r0, [r7, #4] /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. Even if the FLASH operation fails, the BUSY flag will be reset and an error flag will be set */ uint32_t tickstart = HAL_GetTick(); 8002e98: f7fe fee8 bl 8001c6c 8002e9c: 60f8 str r0, [r7, #12] while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) 8002e9e: e010 b.n 8002ec2 { if (Timeout != HAL_MAX_DELAY) 8002ea0: 687b ldr r3, [r7, #4] 8002ea2: f1b3 3fff cmp.w r3, #4294967295 8002ea6: d00c beq.n 8002ec2 { if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) 8002ea8: 687b ldr r3, [r7, #4] 8002eaa: 2b00 cmp r3, #0 8002eac: d007 beq.n 8002ebe 8002eae: f7fe fedd bl 8001c6c 8002eb2: 4602 mov r2, r0 8002eb4: 68fb ldr r3, [r7, #12] 8002eb6: 1ad3 subs r3, r2, r3 8002eb8: 687a ldr r2, [r7, #4] 8002eba: 429a cmp r2, r3 8002ebc: d201 bcs.n 8002ec2 { return HAL_TIMEOUT; 8002ebe: 2303 movs r3, #3 8002ec0: e025 b.n 8002f0e while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) 8002ec2: 4b15 ldr r3, [pc, #84] ; (8002f18 ) 8002ec4: 68db ldr r3, [r3, #12] 8002ec6: f003 0301 and.w r3, r3, #1 8002eca: 2b00 cmp r3, #0 8002ecc: d1e8 bne.n 8002ea0 } } } /* Check FLASH End of Operation flag */ if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) 8002ece: 4b12 ldr r3, [pc, #72] ; (8002f18 ) 8002ed0: 68db ldr r3, [r3, #12] 8002ed2: f003 0320 and.w r3, r3, #32 8002ed6: 2b00 cmp r3, #0 8002ed8: d002 beq.n 8002ee0 { /* Clear FLASH End of Operation pending bit */ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); 8002eda: 4b0f ldr r3, [pc, #60] ; (8002f18 ) 8002edc: 2220 movs r2, #32 8002ede: 60da str r2, [r3, #12] } if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || 8002ee0: 4b0d ldr r3, [pc, #52] ; (8002f18 ) 8002ee2: 68db ldr r3, [r3, #12] 8002ee4: f003 0310 and.w r3, r3, #16 8002ee8: 2b00 cmp r3, #0 8002eea: d10b bne.n 8002f04 __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || 8002eec: 4b0a ldr r3, [pc, #40] ; (8002f18 ) 8002eee: 69db ldr r3, [r3, #28] 8002ef0: f003 0301 and.w r3, r3, #1 if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || 8002ef4: 2b00 cmp r3, #0 8002ef6: d105 bne.n 8002f04 __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) 8002ef8: 4b07 ldr r3, [pc, #28] ; (8002f18 ) 8002efa: 68db ldr r3, [r3, #12] 8002efc: f003 0304 and.w r3, r3, #4 __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || 8002f00: 2b00 cmp r3, #0 8002f02: d003 beq.n 8002f0c { /*Save the error code*/ FLASH_SetErrorCode(); 8002f04: f000 f80a bl 8002f1c return HAL_ERROR; 8002f08: 2301 movs r3, #1 8002f0a: e000 b.n 8002f0e } /* There is no error flag set */ return HAL_OK; 8002f0c: 2300 movs r3, #0 } 8002f0e: 4618 mov r0, r3 8002f10: 3710 adds r7, #16 8002f12: 46bd mov sp, r7 8002f14: bd80 pop {r7, pc} 8002f16: bf00 nop 8002f18: 40022000 .word 0x40022000 08002f1c : /** * @brief Set the specific FLASH error flag. * @retval None */ static void FLASH_SetErrorCode(void) { 8002f1c: b480 push {r7} 8002f1e: b083 sub sp, #12 8002f20: af00 add r7, sp, #0 uint32_t flags = 0U; 8002f22: 2300 movs r3, #0 8002f24: 607b str r3, [r7, #4] #if defined(FLASH_BANK2_END) if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2)) #else if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) 8002f26: 4b23 ldr r3, [pc, #140] ; (8002fb4 ) 8002f28: 68db ldr r3, [r3, #12] 8002f2a: f003 0310 and.w r3, r3, #16 8002f2e: 2b00 cmp r3, #0 8002f30: d009 beq.n 8002f46 #endif /* FLASH_BANK2_END */ { pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; 8002f32: 4b21 ldr r3, [pc, #132] ; (8002fb8 ) 8002f34: 69db ldr r3, [r3, #28] 8002f36: f043 0302 orr.w r3, r3, #2 8002f3a: 4a1f ldr r2, [pc, #124] ; (8002fb8 ) 8002f3c: 61d3 str r3, [r2, #28] #if defined(FLASH_BANK2_END) flags |= FLASH_FLAG_WRPERR | FLASH_FLAG_WRPERR_BANK2; #else flags |= FLASH_FLAG_WRPERR; 8002f3e: 687b ldr r3, [r7, #4] 8002f40: f043 0310 orr.w r3, r3, #16 8002f44: 607b str r3, [r7, #4] #endif /* FLASH_BANK2_END */ } #if defined(FLASH_BANK2_END) if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2)) #else if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) 8002f46: 4b1b ldr r3, [pc, #108] ; (8002fb4 ) 8002f48: 68db ldr r3, [r3, #12] 8002f4a: f003 0304 and.w r3, r3, #4 8002f4e: 2b00 cmp r3, #0 8002f50: d009 beq.n 8002f66 #endif /* FLASH_BANK2_END */ { pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG; 8002f52: 4b19 ldr r3, [pc, #100] ; (8002fb8 ) 8002f54: 69db ldr r3, [r3, #28] 8002f56: f043 0301 orr.w r3, r3, #1 8002f5a: 4a17 ldr r2, [pc, #92] ; (8002fb8 ) 8002f5c: 61d3 str r3, [r2, #28] #if defined(FLASH_BANK2_END) flags |= FLASH_FLAG_PGERR | FLASH_FLAG_PGERR_BANK2; #else flags |= FLASH_FLAG_PGERR; 8002f5e: 687b ldr r3, [r7, #4] 8002f60: f043 0304 orr.w r3, r3, #4 8002f64: 607b str r3, [r7, #4] #endif /* FLASH_BANK2_END */ } if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) 8002f66: 4b13 ldr r3, [pc, #76] ; (8002fb4 ) 8002f68: 69db ldr r3, [r3, #28] 8002f6a: f003 0301 and.w r3, r3, #1 8002f6e: 2b00 cmp r3, #0 8002f70: d00b beq.n 8002f8a { pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV; 8002f72: 4b11 ldr r3, [pc, #68] ; (8002fb8 ) 8002f74: 69db ldr r3, [r3, #28] 8002f76: f043 0304 orr.w r3, r3, #4 8002f7a: 4a0f ldr r2, [pc, #60] ; (8002fb8 ) 8002f7c: 61d3 str r3, [r2, #28] __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR); 8002f7e: 4b0d ldr r3, [pc, #52] ; (8002fb4 ) 8002f80: 69db ldr r3, [r3, #28] 8002f82: 4a0c ldr r2, [pc, #48] ; (8002fb4 ) 8002f84: f023 0301 bic.w r3, r3, #1 8002f88: 61d3 str r3, [r2, #28] } /* Clear FLASH error pending bits */ __HAL_FLASH_CLEAR_FLAG(flags); 8002f8a: 687b ldr r3, [r7, #4] 8002f8c: f240 1201 movw r2, #257 ; 0x101 8002f90: 4293 cmp r3, r2 8002f92: d106 bne.n 8002fa2 8002f94: 4b07 ldr r3, [pc, #28] ; (8002fb4 ) 8002f96: 69db ldr r3, [r3, #28] 8002f98: 4a06 ldr r2, [pc, #24] ; (8002fb4 ) 8002f9a: f023 0301 bic.w r3, r3, #1 8002f9e: 61d3 str r3, [r2, #28] } 8002fa0: e002 b.n 8002fa8 __HAL_FLASH_CLEAR_FLAG(flags); 8002fa2: 4a04 ldr r2, [pc, #16] ; (8002fb4 ) 8002fa4: 687b ldr r3, [r7, #4] 8002fa6: 60d3 str r3, [r2, #12] } 8002fa8: bf00 nop 8002faa: 370c adds r7, #12 8002fac: 46bd mov sp, r7 8002fae: bc80 pop {r7} 8002fb0: 4770 bx lr 8002fb2: bf00 nop 8002fb4: 40022000 .word 0x40022000 8002fb8: 200008f0 .word 0x200008f0 08002fbc : * (0xFFFFFFFF means that all the pages have been correctly erased) * * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) { 8002fbc: b580 push {r7, lr} 8002fbe: b084 sub sp, #16 8002fc0: af00 add r7, sp, #0 8002fc2: 6078 str r0, [r7, #4] 8002fc4: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_ERROR; 8002fc6: 2301 movs r3, #1 8002fc8: 73fb strb r3, [r7, #15] uint32_t address = 0U; 8002fca: 2300 movs r3, #0 8002fcc: 60bb str r3, [r7, #8] /* Process Locked */ __HAL_LOCK(&pFlash); 8002fce: 4b2f ldr r3, [pc, #188] ; (800308c ) 8002fd0: 7e1b ldrb r3, [r3, #24] 8002fd2: 2b01 cmp r3, #1 8002fd4: d101 bne.n 8002fda 8002fd6: 2302 movs r3, #2 8002fd8: e053 b.n 8003082 8002fda: 4b2c ldr r3, [pc, #176] ; (800308c ) 8002fdc: 2201 movs r2, #1 8002fde: 761a strb r2, [r3, #24] /* Check the parameters */ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) 8002fe0: 687b ldr r3, [r7, #4] 8002fe2: 681b ldr r3, [r3, #0] 8002fe4: 2b02 cmp r3, #2 8002fe6: d116 bne.n 8003016 else #endif /* FLASH_BANK2_END */ { /* Mass Erase requested for Bank1 */ /* Wait for last operation to be completed */ if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) 8002fe8: f24c 3050 movw r0, #50000 ; 0xc350 8002fec: f7ff ff50 bl 8002e90 8002ff0: 4603 mov r3, r0 8002ff2: 2b00 cmp r3, #0 8002ff4: d141 bne.n 800307a { /*Mass erase to be done*/ FLASH_MassErase(FLASH_BANK_1); 8002ff6: 2001 movs r0, #1 8002ff8: f000 f84c bl 8003094 /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); 8002ffc: f24c 3050 movw r0, #50000 ; 0xc350 8003000: f7ff ff46 bl 8002e90 8003004: 4603 mov r3, r0 8003006: 73fb strb r3, [r7, #15] /* If the erase operation is completed, disable the MER Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_MER); 8003008: 4b21 ldr r3, [pc, #132] ; (8003090 ) 800300a: 691b ldr r3, [r3, #16] 800300c: 4a20 ldr r2, [pc, #128] ; (8003090 ) 800300e: f023 0304 bic.w r3, r3, #4 8003012: 6113 str r3, [r2, #16] 8003014: e031 b.n 800307a else #endif /* FLASH_BANK2_END */ { /* Page Erase requested on address located on bank1 */ /* Wait for last operation to be completed */ if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) 8003016: f24c 3050 movw r0, #50000 ; 0xc350 800301a: f7ff ff39 bl 8002e90 800301e: 4603 mov r3, r0 8003020: 2b00 cmp r3, #0 8003022: d12a bne.n 800307a { /*Initialization of PageError variable*/ *PageError = 0xFFFFFFFFU; 8003024: 683b ldr r3, [r7, #0] 8003026: f04f 32ff mov.w r2, #4294967295 800302a: 601a str r2, [r3, #0] /* Erase page by page to be done*/ for(address = pEraseInit->PageAddress; 800302c: 687b ldr r3, [r7, #4] 800302e: 689b ldr r3, [r3, #8] 8003030: 60bb str r3, [r7, #8] 8003032: e019 b.n 8003068 address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress); address += FLASH_PAGE_SIZE) { FLASH_PageErase(address); 8003034: 68b8 ldr r0, [r7, #8] 8003036: f000 f849 bl 80030cc /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); 800303a: f24c 3050 movw r0, #50000 ; 0xc350 800303e: f7ff ff27 bl 8002e90 8003042: 4603 mov r3, r0 8003044: 73fb strb r3, [r7, #15] /* If the erase operation is completed, disable the PER Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_PER); 8003046: 4b12 ldr r3, [pc, #72] ; (8003090 ) 8003048: 691b ldr r3, [r3, #16] 800304a: 4a11 ldr r2, [pc, #68] ; (8003090 ) 800304c: f023 0302 bic.w r3, r3, #2 8003050: 6113 str r3, [r2, #16] if (status != HAL_OK) 8003052: 7bfb ldrb r3, [r7, #15] 8003054: 2b00 cmp r3, #0 8003056: d003 beq.n 8003060 { /* In case of error, stop erase procedure and return the faulty address */ *PageError = address; 8003058: 683b ldr r3, [r7, #0] 800305a: 68ba ldr r2, [r7, #8] 800305c: 601a str r2, [r3, #0] break; 800305e: e00c b.n 800307a address += FLASH_PAGE_SIZE) 8003060: 68bb ldr r3, [r7, #8] 8003062: f503 6380 add.w r3, r3, #1024 ; 0x400 8003066: 60bb str r3, [r7, #8] address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress); 8003068: 687b ldr r3, [r7, #4] 800306a: 68db ldr r3, [r3, #12] 800306c: 029a lsls r2, r3, #10 800306e: 687b ldr r3, [r7, #4] 8003070: 689b ldr r3, [r3, #8] 8003072: 4413 add r3, r2 for(address = pEraseInit->PageAddress; 8003074: 68ba ldr r2, [r7, #8] 8003076: 429a cmp r2, r3 8003078: d3dc bcc.n 8003034 } } } /* Process Unlocked */ __HAL_UNLOCK(&pFlash); 800307a: 4b04 ldr r3, [pc, #16] ; (800308c ) 800307c: 2200 movs r2, #0 800307e: 761a strb r2, [r3, #24] return status; 8003080: 7bfb ldrb r3, [r7, #15] } 8003082: 4618 mov r0, r3 8003084: 3710 adds r7, #16 8003086: 46bd mov sp, r7 8003088: bd80 pop {r7, pc} 800308a: bf00 nop 800308c: 200008f0 .word 0x200008f0 8003090: 40022000 .word 0x40022000 08003094 : @endif * * @retval None */ static void FLASH_MassErase(uint32_t Banks) { 8003094: b480 push {r7} 8003096: b083 sub sp, #12 8003098: af00 add r7, sp, #0 800309a: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_FLASH_BANK(Banks)); /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; 800309c: 4b09 ldr r3, [pc, #36] ; (80030c4 ) 800309e: 2200 movs r2, #0 80030a0: 61da str r2, [r3, #28] #if !defined(FLASH_BANK2_END) /* Prevent unused argument(s) compilation warning */ UNUSED(Banks); #endif /* FLASH_BANK2_END */ /* Only bank1 will be erased*/ SET_BIT(FLASH->CR, FLASH_CR_MER); 80030a2: 4b09 ldr r3, [pc, #36] ; (80030c8 ) 80030a4: 691b ldr r3, [r3, #16] 80030a6: 4a08 ldr r2, [pc, #32] ; (80030c8 ) 80030a8: f043 0304 orr.w r3, r3, #4 80030ac: 6113 str r3, [r2, #16] SET_BIT(FLASH->CR, FLASH_CR_STRT); 80030ae: 4b06 ldr r3, [pc, #24] ; (80030c8 ) 80030b0: 691b ldr r3, [r3, #16] 80030b2: 4a05 ldr r2, [pc, #20] ; (80030c8 ) 80030b4: f043 0340 orr.w r3, r3, #64 ; 0x40 80030b8: 6113 str r3, [r2, #16] #if defined(FLASH_BANK2_END) } #endif /* FLASH_BANK2_END */ } 80030ba: bf00 nop 80030bc: 370c adds r7, #12 80030be: 46bd mov sp, r7 80030c0: bc80 pop {r7} 80030c2: 4770 bx lr 80030c4: 200008f0 .word 0x200008f0 80030c8: 40022000 .word 0x40022000 080030cc : * The value of this parameter depend on device used within the same series * * @retval None */ void FLASH_PageErase(uint32_t PageAddress) { 80030cc: b480 push {r7} 80030ce: b083 sub sp, #12 80030d0: af00 add r7, sp, #0 80030d2: 6078 str r0, [r7, #4] /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; 80030d4: 4b0b ldr r3, [pc, #44] ; (8003104 ) 80030d6: 2200 movs r2, #0 80030d8: 61da str r2, [r3, #28] } else { #endif /* FLASH_BANK2_END */ /* Proceed to erase the page */ SET_BIT(FLASH->CR, FLASH_CR_PER); 80030da: 4b0b ldr r3, [pc, #44] ; (8003108 ) 80030dc: 691b ldr r3, [r3, #16] 80030de: 4a0a ldr r2, [pc, #40] ; (8003108 ) 80030e0: f043 0302 orr.w r3, r3, #2 80030e4: 6113 str r3, [r2, #16] WRITE_REG(FLASH->AR, PageAddress); 80030e6: 4a08 ldr r2, [pc, #32] ; (8003108 ) 80030e8: 687b ldr r3, [r7, #4] 80030ea: 6153 str r3, [r2, #20] SET_BIT(FLASH->CR, FLASH_CR_STRT); 80030ec: 4b06 ldr r3, [pc, #24] ; (8003108 ) 80030ee: 691b ldr r3, [r3, #16] 80030f0: 4a05 ldr r2, [pc, #20] ; (8003108 ) 80030f2: f043 0340 orr.w r3, r3, #64 ; 0x40 80030f6: 6113 str r3, [r2, #16] #if defined(FLASH_BANK2_END) } #endif /* FLASH_BANK2_END */ } 80030f8: bf00 nop 80030fa: 370c adds r7, #12 80030fc: 46bd mov sp, r7 80030fe: bc80 pop {r7} 8003100: 4770 bx lr 8003102: bf00 nop 8003104: 200008f0 .word 0x200008f0 8003108: 40022000 .word 0x40022000 0800310c : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 800310c: b480 push {r7} 800310e: b08b sub sp, #44 ; 0x2c 8003110: af00 add r7, sp, #0 8003112: 6078 str r0, [r7, #4] 8003114: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 8003116: 2300 movs r3, #0 8003118: 627b str r3, [r7, #36] ; 0x24 uint32_t ioposition; uint32_t iocurrent; uint32_t temp; uint32_t config = 0x00u; 800311a: 2300 movs r3, #0 800311c: 623b str r3, [r7, #32] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 800311e: e127 b.n 8003370 { /* Get the IO position */ ioposition = (0x01uL << position); 8003120: 2201 movs r2, #1 8003122: 6a7b ldr r3, [r7, #36] ; 0x24 8003124: fa02 f303 lsl.w r3, r2, r3 8003128: 61fb str r3, [r7, #28] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 800312a: 683b ldr r3, [r7, #0] 800312c: 681b ldr r3, [r3, #0] 800312e: 69fa ldr r2, [r7, #28] 8003130: 4013 ands r3, r2 8003132: 61bb str r3, [r7, #24] if (iocurrent == ioposition) 8003134: 69ba ldr r2, [r7, #24] 8003136: 69fb ldr r3, [r7, #28] 8003138: 429a cmp r2, r3 800313a: f040 8116 bne.w 800336a { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ switch (GPIO_Init->Mode) 800313e: 683b ldr r3, [r7, #0] 8003140: 685b ldr r3, [r3, #4] 8003142: 2b12 cmp r3, #18 8003144: d034 beq.n 80031b0 8003146: 2b12 cmp r3, #18 8003148: d80d bhi.n 8003166 800314a: 2b02 cmp r3, #2 800314c: d02b beq.n 80031a6 800314e: 2b02 cmp r3, #2 8003150: d804 bhi.n 800315c 8003152: 2b00 cmp r3, #0 8003154: d031 beq.n 80031ba 8003156: 2b01 cmp r3, #1 8003158: d01c beq.n 8003194 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; break; /* Parameters are checked with assert_param */ default: break; 800315a: e048 b.n 80031ee switch (GPIO_Init->Mode) 800315c: 2b03 cmp r3, #3 800315e: d043 beq.n 80031e8 8003160: 2b11 cmp r3, #17 8003162: d01b beq.n 800319c break; 8003164: e043 b.n 80031ee switch (GPIO_Init->Mode) 8003166: 4a89 ldr r2, [pc, #548] ; (800338c ) 8003168: 4293 cmp r3, r2 800316a: d026 beq.n 80031ba 800316c: 4a87 ldr r2, [pc, #540] ; (800338c ) 800316e: 4293 cmp r3, r2 8003170: d806 bhi.n 8003180 8003172: 4a87 ldr r2, [pc, #540] ; (8003390 ) 8003174: 4293 cmp r3, r2 8003176: d020 beq.n 80031ba 8003178: 4a86 ldr r2, [pc, #536] ; (8003394 ) 800317a: 4293 cmp r3, r2 800317c: d01d beq.n 80031ba break; 800317e: e036 b.n 80031ee switch (GPIO_Init->Mode) 8003180: 4a85 ldr r2, [pc, #532] ; (8003398 ) 8003182: 4293 cmp r3, r2 8003184: d019 beq.n 80031ba 8003186: 4a85 ldr r2, [pc, #532] ; (800339c ) 8003188: 4293 cmp r3, r2 800318a: d016 beq.n 80031ba 800318c: 4a84 ldr r2, [pc, #528] ; (80033a0 ) 800318e: 4293 cmp r3, r2 8003190: d013 beq.n 80031ba break; 8003192: e02c b.n 80031ee config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; 8003194: 683b ldr r3, [r7, #0] 8003196: 68db ldr r3, [r3, #12] 8003198: 623b str r3, [r7, #32] break; 800319a: e028 b.n 80031ee config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; 800319c: 683b ldr r3, [r7, #0] 800319e: 68db ldr r3, [r3, #12] 80031a0: 3304 adds r3, #4 80031a2: 623b str r3, [r7, #32] break; 80031a4: e023 b.n 80031ee config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; 80031a6: 683b ldr r3, [r7, #0] 80031a8: 68db ldr r3, [r3, #12] 80031aa: 3308 adds r3, #8 80031ac: 623b str r3, [r7, #32] break; 80031ae: e01e b.n 80031ee config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; 80031b0: 683b ldr r3, [r7, #0] 80031b2: 68db ldr r3, [r3, #12] 80031b4: 330c adds r3, #12 80031b6: 623b str r3, [r7, #32] break; 80031b8: e019 b.n 80031ee if (GPIO_Init->Pull == GPIO_NOPULL) 80031ba: 683b ldr r3, [r7, #0] 80031bc: 689b ldr r3, [r3, #8] 80031be: 2b00 cmp r3, #0 80031c0: d102 bne.n 80031c8 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; 80031c2: 2304 movs r3, #4 80031c4: 623b str r3, [r7, #32] break; 80031c6: e012 b.n 80031ee else if (GPIO_Init->Pull == GPIO_PULLUP) 80031c8: 683b ldr r3, [r7, #0] 80031ca: 689b ldr r3, [r3, #8] 80031cc: 2b01 cmp r3, #1 80031ce: d105 bne.n 80031dc config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 80031d0: 2308 movs r3, #8 80031d2: 623b str r3, [r7, #32] GPIOx->BSRR = ioposition; 80031d4: 687b ldr r3, [r7, #4] 80031d6: 69fa ldr r2, [r7, #28] 80031d8: 611a str r2, [r3, #16] break; 80031da: e008 b.n 80031ee config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 80031dc: 2308 movs r3, #8 80031de: 623b str r3, [r7, #32] GPIOx->BRR = ioposition; 80031e0: 687b ldr r3, [r7, #4] 80031e2: 69fa ldr r2, [r7, #28] 80031e4: 615a str r2, [r3, #20] break; 80031e6: e002 b.n 80031ee config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; 80031e8: 2300 movs r3, #0 80031ea: 623b str r3, [r7, #32] break; 80031ec: bf00 nop } /* Check if the current bit belongs to first half or last half of the pin count number in order to address CRH or CRL register*/ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; 80031ee: 69bb ldr r3, [r7, #24] 80031f0: 2bff cmp r3, #255 ; 0xff 80031f2: d801 bhi.n 80031f8 80031f4: 687b ldr r3, [r7, #4] 80031f6: e001 b.n 80031fc 80031f8: 687b ldr r3, [r7, #4] 80031fa: 3304 adds r3, #4 80031fc: 617b str r3, [r7, #20] registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); 80031fe: 69bb ldr r3, [r7, #24] 8003200: 2bff cmp r3, #255 ; 0xff 8003202: d802 bhi.n 800320a 8003204: 6a7b ldr r3, [r7, #36] ; 0x24 8003206: 009b lsls r3, r3, #2 8003208: e002 b.n 8003210 800320a: 6a7b ldr r3, [r7, #36] ; 0x24 800320c: 3b08 subs r3, #8 800320e: 009b lsls r3, r3, #2 8003210: 613b str r3, [r7, #16] /* Apply the new configuration of the pin to the register */ MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); 8003212: 697b ldr r3, [r7, #20] 8003214: 681a ldr r2, [r3, #0] 8003216: 210f movs r1, #15 8003218: 693b ldr r3, [r7, #16] 800321a: fa01 f303 lsl.w r3, r1, r3 800321e: 43db mvns r3, r3 8003220: 401a ands r2, r3 8003222: 6a39 ldr r1, [r7, #32] 8003224: 693b ldr r3, [r7, #16] 8003226: fa01 f303 lsl.w r3, r1, r3 800322a: 431a orrs r2, r3 800322c: 697b ldr r3, [r7, #20] 800322e: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 8003230: 683b ldr r3, [r7, #0] 8003232: 685b ldr r3, [r3, #4] 8003234: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8003238: 2b00 cmp r3, #0 800323a: f000 8096 beq.w 800336a { /* Enable AFIO Clock */ __HAL_RCC_AFIO_CLK_ENABLE(); 800323e: 4b59 ldr r3, [pc, #356] ; (80033a4 ) 8003240: 699b ldr r3, [r3, #24] 8003242: 4a58 ldr r2, [pc, #352] ; (80033a4 ) 8003244: f043 0301 orr.w r3, r3, #1 8003248: 6193 str r3, [r2, #24] 800324a: 4b56 ldr r3, [pc, #344] ; (80033a4 ) 800324c: 699b ldr r3, [r3, #24] 800324e: f003 0301 and.w r3, r3, #1 8003252: 60bb str r3, [r7, #8] 8003254: 68bb ldr r3, [r7, #8] temp = AFIO->EXTICR[position >> 2u]; 8003256: 4a54 ldr r2, [pc, #336] ; (80033a8 ) 8003258: 6a7b ldr r3, [r7, #36] ; 0x24 800325a: 089b lsrs r3, r3, #2 800325c: 3302 adds r3, #2 800325e: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8003262: 60fb str r3, [r7, #12] CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u))); 8003264: 6a7b ldr r3, [r7, #36] ; 0x24 8003266: f003 0303 and.w r3, r3, #3 800326a: 009b lsls r3, r3, #2 800326c: 220f movs r2, #15 800326e: fa02 f303 lsl.w r3, r2, r3 8003272: 43db mvns r3, r3 8003274: 68fa ldr r2, [r7, #12] 8003276: 4013 ands r3, r2 8003278: 60fb str r3, [r7, #12] SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u))); 800327a: 687b ldr r3, [r7, #4] 800327c: 4a4b ldr r2, [pc, #300] ; (80033ac ) 800327e: 4293 cmp r3, r2 8003280: d013 beq.n 80032aa 8003282: 687b ldr r3, [r7, #4] 8003284: 4a4a ldr r2, [pc, #296] ; (80033b0 ) 8003286: 4293 cmp r3, r2 8003288: d00d beq.n 80032a6 800328a: 687b ldr r3, [r7, #4] 800328c: 4a49 ldr r2, [pc, #292] ; (80033b4 ) 800328e: 4293 cmp r3, r2 8003290: d007 beq.n 80032a2 8003292: 687b ldr r3, [r7, #4] 8003294: 4a48 ldr r2, [pc, #288] ; (80033b8 ) 8003296: 4293 cmp r3, r2 8003298: d101 bne.n 800329e 800329a: 2303 movs r3, #3 800329c: e006 b.n 80032ac 800329e: 2304 movs r3, #4 80032a0: e004 b.n 80032ac 80032a2: 2302 movs r3, #2 80032a4: e002 b.n 80032ac 80032a6: 2301 movs r3, #1 80032a8: e000 b.n 80032ac 80032aa: 2300 movs r3, #0 80032ac: 6a7a ldr r2, [r7, #36] ; 0x24 80032ae: f002 0203 and.w r2, r2, #3 80032b2: 0092 lsls r2, r2, #2 80032b4: 4093 lsls r3, r2 80032b6: 68fa ldr r2, [r7, #12] 80032b8: 4313 orrs r3, r2 80032ba: 60fb str r3, [r7, #12] AFIO->EXTICR[position >> 2u] = temp; 80032bc: 493a ldr r1, [pc, #232] ; (80033a8 ) 80032be: 6a7b ldr r3, [r7, #36] ; 0x24 80032c0: 089b lsrs r3, r3, #2 80032c2: 3302 adds r3, #2 80032c4: 68fa ldr r2, [r7, #12] 80032c6: f841 2023 str.w r2, [r1, r3, lsl #2] /* Configure the interrupt mask */ if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) 80032ca: 683b ldr r3, [r7, #0] 80032cc: 685b ldr r3, [r3, #4] 80032ce: f403 3380 and.w r3, r3, #65536 ; 0x10000 80032d2: 2b00 cmp r3, #0 80032d4: d006 beq.n 80032e4 { SET_BIT(EXTI->IMR, iocurrent); 80032d6: 4b39 ldr r3, [pc, #228] ; (80033bc ) 80032d8: 681a ldr r2, [r3, #0] 80032da: 4938 ldr r1, [pc, #224] ; (80033bc ) 80032dc: 69bb ldr r3, [r7, #24] 80032de: 4313 orrs r3, r2 80032e0: 600b str r3, [r1, #0] 80032e2: e006 b.n 80032f2 } else { CLEAR_BIT(EXTI->IMR, iocurrent); 80032e4: 4b35 ldr r3, [pc, #212] ; (80033bc ) 80032e6: 681a ldr r2, [r3, #0] 80032e8: 69bb ldr r3, [r7, #24] 80032ea: 43db mvns r3, r3 80032ec: 4933 ldr r1, [pc, #204] ; (80033bc ) 80032ee: 4013 ands r3, r2 80032f0: 600b str r3, [r1, #0] } /* Configure the event mask */ if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) 80032f2: 683b ldr r3, [r7, #0] 80032f4: 685b ldr r3, [r3, #4] 80032f6: f403 3300 and.w r3, r3, #131072 ; 0x20000 80032fa: 2b00 cmp r3, #0 80032fc: d006 beq.n 800330c { SET_BIT(EXTI->EMR, iocurrent); 80032fe: 4b2f ldr r3, [pc, #188] ; (80033bc ) 8003300: 685a ldr r2, [r3, #4] 8003302: 492e ldr r1, [pc, #184] ; (80033bc ) 8003304: 69bb ldr r3, [r7, #24] 8003306: 4313 orrs r3, r2 8003308: 604b str r3, [r1, #4] 800330a: e006 b.n 800331a } else { CLEAR_BIT(EXTI->EMR, iocurrent); 800330c: 4b2b ldr r3, [pc, #172] ; (80033bc ) 800330e: 685a ldr r2, [r3, #4] 8003310: 69bb ldr r3, [r7, #24] 8003312: 43db mvns r3, r3 8003314: 4929 ldr r1, [pc, #164] ; (80033bc ) 8003316: 4013 ands r3, r2 8003318: 604b str r3, [r1, #4] } /* Enable or disable the rising trigger */ if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) 800331a: 683b ldr r3, [r7, #0] 800331c: 685b ldr r3, [r3, #4] 800331e: f403 1380 and.w r3, r3, #1048576 ; 0x100000 8003322: 2b00 cmp r3, #0 8003324: d006 beq.n 8003334 { SET_BIT(EXTI->RTSR, iocurrent); 8003326: 4b25 ldr r3, [pc, #148] ; (80033bc ) 8003328: 689a ldr r2, [r3, #8] 800332a: 4924 ldr r1, [pc, #144] ; (80033bc ) 800332c: 69bb ldr r3, [r7, #24] 800332e: 4313 orrs r3, r2 8003330: 608b str r3, [r1, #8] 8003332: e006 b.n 8003342 } else { CLEAR_BIT(EXTI->RTSR, iocurrent); 8003334: 4b21 ldr r3, [pc, #132] ; (80033bc ) 8003336: 689a ldr r2, [r3, #8] 8003338: 69bb ldr r3, [r7, #24] 800333a: 43db mvns r3, r3 800333c: 491f ldr r1, [pc, #124] ; (80033bc ) 800333e: 4013 ands r3, r2 8003340: 608b str r3, [r1, #8] } /* Enable or disable the falling trigger */ if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) 8003342: 683b ldr r3, [r7, #0] 8003344: 685b ldr r3, [r3, #4] 8003346: f403 1300 and.w r3, r3, #2097152 ; 0x200000 800334a: 2b00 cmp r3, #0 800334c: d006 beq.n 800335c { SET_BIT(EXTI->FTSR, iocurrent); 800334e: 4b1b ldr r3, [pc, #108] ; (80033bc ) 8003350: 68da ldr r2, [r3, #12] 8003352: 491a ldr r1, [pc, #104] ; (80033bc ) 8003354: 69bb ldr r3, [r7, #24] 8003356: 4313 orrs r3, r2 8003358: 60cb str r3, [r1, #12] 800335a: e006 b.n 800336a } else { CLEAR_BIT(EXTI->FTSR, iocurrent); 800335c: 4b17 ldr r3, [pc, #92] ; (80033bc ) 800335e: 68da ldr r2, [r3, #12] 8003360: 69bb ldr r3, [r7, #24] 8003362: 43db mvns r3, r3 8003364: 4915 ldr r1, [pc, #84] ; (80033bc ) 8003366: 4013 ands r3, r2 8003368: 60cb str r3, [r1, #12] } } } position++; 800336a: 6a7b ldr r3, [r7, #36] ; 0x24 800336c: 3301 adds r3, #1 800336e: 627b str r3, [r7, #36] ; 0x24 while (((GPIO_Init->Pin) >> position) != 0x00u) 8003370: 683b ldr r3, [r7, #0] 8003372: 681a ldr r2, [r3, #0] 8003374: 6a7b ldr r3, [r7, #36] ; 0x24 8003376: fa22 f303 lsr.w r3, r2, r3 800337a: 2b00 cmp r3, #0 800337c: f47f aed0 bne.w 8003120 } } 8003380: bf00 nop 8003382: 372c adds r7, #44 ; 0x2c 8003384: 46bd mov sp, r7 8003386: bc80 pop {r7} 8003388: 4770 bx lr 800338a: bf00 nop 800338c: 10210000 .word 0x10210000 8003390: 10110000 .word 0x10110000 8003394: 10120000 .word 0x10120000 8003398: 10310000 .word 0x10310000 800339c: 10320000 .word 0x10320000 80033a0: 10220000 .word 0x10220000 80033a4: 40021000 .word 0x40021000 80033a8: 40010000 .word 0x40010000 80033ac: 40010800 .word 0x40010800 80033b0: 40010c00 .word 0x40010c00 80033b4: 40011000 .word 0x40011000 80033b8: 40011400 .word 0x40011400 80033bc: 40010400 .word 0x40010400 080033c0 : * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 80033c0: b480 push {r7} 80033c2: b085 sub sp, #20 80033c4: af00 add r7, sp, #0 80033c6: 6078 str r0, [r7, #4] 80033c8: 460b mov r3, r1 80033ca: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) 80033cc: 687b ldr r3, [r7, #4] 80033ce: 689a ldr r2, [r3, #8] 80033d0: 887b ldrh r3, [r7, #2] 80033d2: 4013 ands r3, r2 80033d4: 2b00 cmp r3, #0 80033d6: d002 beq.n 80033de { bitstatus = GPIO_PIN_SET; 80033d8: 2301 movs r3, #1 80033da: 73fb strb r3, [r7, #15] 80033dc: e001 b.n 80033e2 } else { bitstatus = GPIO_PIN_RESET; 80033de: 2300 movs r3, #0 80033e0: 73fb strb r3, [r7, #15] } return bitstatus; 80033e2: 7bfb ldrb r3, [r7, #15] } 80033e4: 4618 mov r0, r3 80033e6: 3714 adds r7, #20 80033e8: 46bd mov sp, r7 80033ea: bc80 pop {r7} 80033ec: 4770 bx lr 080033ee : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 80033ee: b480 push {r7} 80033f0: b083 sub sp, #12 80033f2: af00 add r7, sp, #0 80033f4: 6078 str r0, [r7, #4] 80033f6: 460b mov r3, r1 80033f8: 807b strh r3, [r7, #2] 80033fa: 4613 mov r3, r2 80033fc: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 80033fe: 787b ldrb r3, [r7, #1] 8003400: 2b00 cmp r3, #0 8003402: d003 beq.n 800340c { GPIOx->BSRR = GPIO_Pin; 8003404: 887a ldrh r2, [r7, #2] 8003406: 687b ldr r3, [r7, #4] 8003408: 611a str r2, [r3, #16] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; } } 800340a: e003 b.n 8003414 GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; 800340c: 887b ldrh r3, [r7, #2] 800340e: 041a lsls r2, r3, #16 8003410: 687b ldr r3, [r7, #4] 8003412: 611a str r2, [r3, #16] } 8003414: bf00 nop 8003416: 370c adds r7, #12 8003418: 46bd mov sp, r7 800341a: bc80 pop {r7} 800341c: 4770 bx lr 0800341e : * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral * @param GPIO_Pin: Specifies the pins to be toggled. * @retval None */ void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 800341e: b480 push {r7} 8003420: b083 sub sp, #12 8003422: af00 add r7, sp, #0 8003424: 6078 str r0, [r7, #4] 8003426: 460b mov r3, r1 8003428: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->ODR & GPIO_Pin) != 0x00u) 800342a: 687b ldr r3, [r7, #4] 800342c: 68da ldr r2, [r3, #12] 800342e: 887b ldrh r3, [r7, #2] 8003430: 4013 ands r3, r2 8003432: 2b00 cmp r3, #0 8003434: d003 beq.n 800343e { GPIOx->BRR = (uint32_t)GPIO_Pin; 8003436: 887a ldrh r2, [r7, #2] 8003438: 687b ldr r3, [r7, #4] 800343a: 615a str r2, [r3, #20] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin; } } 800343c: e002 b.n 8003444 GPIOx->BSRR = (uint32_t)GPIO_Pin; 800343e: 887a ldrh r2, [r7, #2] 8003440: 687b ldr r3, [r7, #4] 8003442: 611a str r2, [r3, #16] } 8003444: bf00 nop 8003446: 370c adds r7, #12 8003448: 46bd mov sp, r7 800344a: bc80 pop {r7} 800344c: 4770 bx lr ... 08003450 : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 8003450: b580 push {r7, lr} 8003452: b086 sub sp, #24 8003454: af00 add r7, sp, #0 8003456: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 8003458: 687b ldr r3, [r7, #4] 800345a: 2b00 cmp r3, #0 800345c: d101 bne.n 8003462 { return HAL_ERROR; 800345e: 2301 movs r3, #1 8003460: e26c b.n 800393c /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8003462: 687b ldr r3, [r7, #4] 8003464: 681b ldr r3, [r3, #0] 8003466: f003 0301 and.w r3, r3, #1 800346a: 2b00 cmp r3, #0 800346c: f000 8087 beq.w 800357e { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 8003470: 4b92 ldr r3, [pc, #584] ; (80036bc ) 8003472: 685b ldr r3, [r3, #4] 8003474: f003 030c and.w r3, r3, #12 8003478: 2b04 cmp r3, #4 800347a: d00c beq.n 8003496 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 800347c: 4b8f ldr r3, [pc, #572] ; (80036bc ) 800347e: 685b ldr r3, [r3, #4] 8003480: f003 030c and.w r3, r3, #12 8003484: 2b08 cmp r3, #8 8003486: d112 bne.n 80034ae 8003488: 4b8c ldr r3, [pc, #560] ; (80036bc ) 800348a: 685b ldr r3, [r3, #4] 800348c: f403 3380 and.w r3, r3, #65536 ; 0x10000 8003490: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8003494: d10b bne.n 80034ae { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8003496: 4b89 ldr r3, [pc, #548] ; (80036bc ) 8003498: 681b ldr r3, [r3, #0] 800349a: f403 3300 and.w r3, r3, #131072 ; 0x20000 800349e: 2b00 cmp r3, #0 80034a0: d06c beq.n 800357c 80034a2: 687b ldr r3, [r7, #4] 80034a4: 685b ldr r3, [r3, #4] 80034a6: 2b00 cmp r3, #0 80034a8: d168 bne.n 800357c { return HAL_ERROR; 80034aa: 2301 movs r3, #1 80034ac: e246 b.n 800393c } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 80034ae: 687b ldr r3, [r7, #4] 80034b0: 685b ldr r3, [r3, #4] 80034b2: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 80034b6: d106 bne.n 80034c6 80034b8: 4b80 ldr r3, [pc, #512] ; (80036bc ) 80034ba: 681b ldr r3, [r3, #0] 80034bc: 4a7f ldr r2, [pc, #508] ; (80036bc ) 80034be: f443 3380 orr.w r3, r3, #65536 ; 0x10000 80034c2: 6013 str r3, [r2, #0] 80034c4: e02e b.n 8003524 80034c6: 687b ldr r3, [r7, #4] 80034c8: 685b ldr r3, [r3, #4] 80034ca: 2b00 cmp r3, #0 80034cc: d10c bne.n 80034e8 80034ce: 4b7b ldr r3, [pc, #492] ; (80036bc ) 80034d0: 681b ldr r3, [r3, #0] 80034d2: 4a7a ldr r2, [pc, #488] ; (80036bc ) 80034d4: f423 3380 bic.w r3, r3, #65536 ; 0x10000 80034d8: 6013 str r3, [r2, #0] 80034da: 4b78 ldr r3, [pc, #480] ; (80036bc ) 80034dc: 681b ldr r3, [r3, #0] 80034de: 4a77 ldr r2, [pc, #476] ; (80036bc ) 80034e0: f423 2380 bic.w r3, r3, #262144 ; 0x40000 80034e4: 6013 str r3, [r2, #0] 80034e6: e01d b.n 8003524 80034e8: 687b ldr r3, [r7, #4] 80034ea: 685b ldr r3, [r3, #4] 80034ec: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 80034f0: d10c bne.n 800350c 80034f2: 4b72 ldr r3, [pc, #456] ; (80036bc ) 80034f4: 681b ldr r3, [r3, #0] 80034f6: 4a71 ldr r2, [pc, #452] ; (80036bc ) 80034f8: f443 2380 orr.w r3, r3, #262144 ; 0x40000 80034fc: 6013 str r3, [r2, #0] 80034fe: 4b6f ldr r3, [pc, #444] ; (80036bc ) 8003500: 681b ldr r3, [r3, #0] 8003502: 4a6e ldr r2, [pc, #440] ; (80036bc ) 8003504: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8003508: 6013 str r3, [r2, #0] 800350a: e00b b.n 8003524 800350c: 4b6b ldr r3, [pc, #428] ; (80036bc ) 800350e: 681b ldr r3, [r3, #0] 8003510: 4a6a ldr r2, [pc, #424] ; (80036bc ) 8003512: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8003516: 6013 str r3, [r2, #0] 8003518: 4b68 ldr r3, [pc, #416] ; (80036bc ) 800351a: 681b ldr r3, [r3, #0] 800351c: 4a67 ldr r2, [pc, #412] ; (80036bc ) 800351e: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8003522: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8003524: 687b ldr r3, [r7, #4] 8003526: 685b ldr r3, [r3, #4] 8003528: 2b00 cmp r3, #0 800352a: d013 beq.n 8003554 { /* Get Start Tick */ tickstart = HAL_GetTick(); 800352c: f7fe fb9e bl 8001c6c 8003530: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8003532: e008 b.n 8003546 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8003534: f7fe fb9a bl 8001c6c 8003538: 4602 mov r2, r0 800353a: 693b ldr r3, [r7, #16] 800353c: 1ad3 subs r3, r2, r3 800353e: 2b64 cmp r3, #100 ; 0x64 8003540: d901 bls.n 8003546 { return HAL_TIMEOUT; 8003542: 2303 movs r3, #3 8003544: e1fa b.n 800393c while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8003546: 4b5d ldr r3, [pc, #372] ; (80036bc ) 8003548: 681b ldr r3, [r3, #0] 800354a: f403 3300 and.w r3, r3, #131072 ; 0x20000 800354e: 2b00 cmp r3, #0 8003550: d0f0 beq.n 8003534 8003552: e014 b.n 800357e } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8003554: f7fe fb8a bl 8001c6c 8003558: 6138 str r0, [r7, #16] /* Wait till HSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 800355a: e008 b.n 800356e { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 800355c: f7fe fb86 bl 8001c6c 8003560: 4602 mov r2, r0 8003562: 693b ldr r3, [r7, #16] 8003564: 1ad3 subs r3, r2, r3 8003566: 2b64 cmp r3, #100 ; 0x64 8003568: d901 bls.n 800356e { return HAL_TIMEOUT; 800356a: 2303 movs r3, #3 800356c: e1e6 b.n 800393c while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 800356e: 4b53 ldr r3, [pc, #332] ; (80036bc ) 8003570: 681b ldr r3, [r3, #0] 8003572: f403 3300 and.w r3, r3, #131072 ; 0x20000 8003576: 2b00 cmp r3, #0 8003578: d1f0 bne.n 800355c 800357a: e000 b.n 800357e if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 800357c: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 800357e: 687b ldr r3, [r7, #4] 8003580: 681b ldr r3, [r3, #0] 8003582: f003 0302 and.w r3, r3, #2 8003586: 2b00 cmp r3, #0 8003588: d063 beq.n 8003652 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 800358a: 4b4c ldr r3, [pc, #304] ; (80036bc ) 800358c: 685b ldr r3, [r3, #4] 800358e: f003 030c and.w r3, r3, #12 8003592: 2b00 cmp r3, #0 8003594: d00b beq.n 80035ae || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) 8003596: 4b49 ldr r3, [pc, #292] ; (80036bc ) 8003598: 685b ldr r3, [r3, #4] 800359a: f003 030c and.w r3, r3, #12 800359e: 2b08 cmp r3, #8 80035a0: d11c bne.n 80035dc 80035a2: 4b46 ldr r3, [pc, #280] ; (80036bc ) 80035a4: 685b ldr r3, [r3, #4] 80035a6: f403 3380 and.w r3, r3, #65536 ; 0x10000 80035aa: 2b00 cmp r3, #0 80035ac: d116 bne.n 80035dc { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 80035ae: 4b43 ldr r3, [pc, #268] ; (80036bc ) 80035b0: 681b ldr r3, [r3, #0] 80035b2: f003 0302 and.w r3, r3, #2 80035b6: 2b00 cmp r3, #0 80035b8: d005 beq.n 80035c6 80035ba: 687b ldr r3, [r7, #4] 80035bc: 691b ldr r3, [r3, #16] 80035be: 2b01 cmp r3, #1 80035c0: d001 beq.n 80035c6 { return HAL_ERROR; 80035c2: 2301 movs r3, #1 80035c4: e1ba b.n 800393c } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 80035c6: 4b3d ldr r3, [pc, #244] ; (80036bc ) 80035c8: 681b ldr r3, [r3, #0] 80035ca: f023 02f8 bic.w r2, r3, #248 ; 0xf8 80035ce: 687b ldr r3, [r7, #4] 80035d0: 695b ldr r3, [r3, #20] 80035d2: 00db lsls r3, r3, #3 80035d4: 4939 ldr r1, [pc, #228] ; (80036bc ) 80035d6: 4313 orrs r3, r2 80035d8: 600b str r3, [r1, #0] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 80035da: e03a b.n 8003652 } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 80035dc: 687b ldr r3, [r7, #4] 80035de: 691b ldr r3, [r3, #16] 80035e0: 2b00 cmp r3, #0 80035e2: d020 beq.n 8003626 { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 80035e4: 4b36 ldr r3, [pc, #216] ; (80036c0 ) 80035e6: 2201 movs r2, #1 80035e8: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80035ea: f7fe fb3f bl 8001c6c 80035ee: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 80035f0: e008 b.n 8003604 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 80035f2: f7fe fb3b bl 8001c6c 80035f6: 4602 mov r2, r0 80035f8: 693b ldr r3, [r7, #16] 80035fa: 1ad3 subs r3, r2, r3 80035fc: 2b02 cmp r3, #2 80035fe: d901 bls.n 8003604 { return HAL_TIMEOUT; 8003600: 2303 movs r3, #3 8003602: e19b b.n 800393c while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8003604: 4b2d ldr r3, [pc, #180] ; (80036bc ) 8003606: 681b ldr r3, [r3, #0] 8003608: f003 0302 and.w r3, r3, #2 800360c: 2b00 cmp r3, #0 800360e: d0f0 beq.n 80035f2 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8003610: 4b2a ldr r3, [pc, #168] ; (80036bc ) 8003612: 681b ldr r3, [r3, #0] 8003614: f023 02f8 bic.w r2, r3, #248 ; 0xf8 8003618: 687b ldr r3, [r7, #4] 800361a: 695b ldr r3, [r3, #20] 800361c: 00db lsls r3, r3, #3 800361e: 4927 ldr r1, [pc, #156] ; (80036bc ) 8003620: 4313 orrs r3, r2 8003622: 600b str r3, [r1, #0] 8003624: e015 b.n 8003652 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8003626: 4b26 ldr r3, [pc, #152] ; (80036c0 ) 8003628: 2200 movs r2, #0 800362a: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800362c: f7fe fb1e bl 8001c6c 8003630: 6138 str r0, [r7, #16] /* Wait till HSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8003632: e008 b.n 8003646 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8003634: f7fe fb1a bl 8001c6c 8003638: 4602 mov r2, r0 800363a: 693b ldr r3, [r7, #16] 800363c: 1ad3 subs r3, r2, r3 800363e: 2b02 cmp r3, #2 8003640: d901 bls.n 8003646 { return HAL_TIMEOUT; 8003642: 2303 movs r3, #3 8003644: e17a b.n 800393c while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8003646: 4b1d ldr r3, [pc, #116] ; (80036bc ) 8003648: 681b ldr r3, [r3, #0] 800364a: f003 0302 and.w r3, r3, #2 800364e: 2b00 cmp r3, #0 8003650: d1f0 bne.n 8003634 } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8003652: 687b ldr r3, [r7, #4] 8003654: 681b ldr r3, [r3, #0] 8003656: f003 0308 and.w r3, r3, #8 800365a: 2b00 cmp r3, #0 800365c: d03a beq.n 80036d4 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 800365e: 687b ldr r3, [r7, #4] 8003660: 699b ldr r3, [r3, #24] 8003662: 2b00 cmp r3, #0 8003664: d019 beq.n 800369a { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8003666: 4b17 ldr r3, [pc, #92] ; (80036c4 ) 8003668: 2201 movs r2, #1 800366a: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800366c: f7fe fafe bl 8001c6c 8003670: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8003672: e008 b.n 8003686 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8003674: f7fe fafa bl 8001c6c 8003678: 4602 mov r2, r0 800367a: 693b ldr r3, [r7, #16] 800367c: 1ad3 subs r3, r2, r3 800367e: 2b02 cmp r3, #2 8003680: d901 bls.n 8003686 { return HAL_TIMEOUT; 8003682: 2303 movs r3, #3 8003684: e15a b.n 800393c while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8003686: 4b0d ldr r3, [pc, #52] ; (80036bc ) 8003688: 6a5b ldr r3, [r3, #36] ; 0x24 800368a: f003 0302 and.w r3, r3, #2 800368e: 2b00 cmp r3, #0 8003690: d0f0 beq.n 8003674 } } /* To have a fully stabilized clock in the specified range, a software delay of 1ms should be added.*/ RCC_Delay(1); 8003692: 2001 movs r0, #1 8003694: f000 fad6 bl 8003c44 8003698: e01c b.n 80036d4 } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 800369a: 4b0a ldr r3, [pc, #40] ; (80036c4 ) 800369c: 2200 movs r2, #0 800369e: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80036a0: f7fe fae4 bl 8001c6c 80036a4: 6138 str r0, [r7, #16] /* Wait till LSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 80036a6: e00f b.n 80036c8 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 80036a8: f7fe fae0 bl 8001c6c 80036ac: 4602 mov r2, r0 80036ae: 693b ldr r3, [r7, #16] 80036b0: 1ad3 subs r3, r2, r3 80036b2: 2b02 cmp r3, #2 80036b4: d908 bls.n 80036c8 { return HAL_TIMEOUT; 80036b6: 2303 movs r3, #3 80036b8: e140 b.n 800393c 80036ba: bf00 nop 80036bc: 40021000 .word 0x40021000 80036c0: 42420000 .word 0x42420000 80036c4: 42420480 .word 0x42420480 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 80036c8: 4b9e ldr r3, [pc, #632] ; (8003944 ) 80036ca: 6a5b ldr r3, [r3, #36] ; 0x24 80036cc: f003 0302 and.w r3, r3, #2 80036d0: 2b00 cmp r3, #0 80036d2: d1e9 bne.n 80036a8 } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 80036d4: 687b ldr r3, [r7, #4] 80036d6: 681b ldr r3, [r3, #0] 80036d8: f003 0304 and.w r3, r3, #4 80036dc: 2b00 cmp r3, #0 80036de: f000 80a6 beq.w 800382e { FlagStatus pwrclkchanged = RESET; 80036e2: 2300 movs r3, #0 80036e4: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 80036e6: 4b97 ldr r3, [pc, #604] ; (8003944 ) 80036e8: 69db ldr r3, [r3, #28] 80036ea: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 80036ee: 2b00 cmp r3, #0 80036f0: d10d bne.n 800370e { __HAL_RCC_PWR_CLK_ENABLE(); 80036f2: 4b94 ldr r3, [pc, #592] ; (8003944 ) 80036f4: 69db ldr r3, [r3, #28] 80036f6: 4a93 ldr r2, [pc, #588] ; (8003944 ) 80036f8: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 80036fc: 61d3 str r3, [r2, #28] 80036fe: 4b91 ldr r3, [pc, #580] ; (8003944 ) 8003700: 69db ldr r3, [r3, #28] 8003702: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8003706: 60bb str r3, [r7, #8] 8003708: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 800370a: 2301 movs r3, #1 800370c: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 800370e: 4b8e ldr r3, [pc, #568] ; (8003948 ) 8003710: 681b ldr r3, [r3, #0] 8003712: f403 7380 and.w r3, r3, #256 ; 0x100 8003716: 2b00 cmp r3, #0 8003718: d118 bne.n 800374c { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 800371a: 4b8b ldr r3, [pc, #556] ; (8003948 ) 800371c: 681b ldr r3, [r3, #0] 800371e: 4a8a ldr r2, [pc, #552] ; (8003948 ) 8003720: f443 7380 orr.w r3, r3, #256 ; 0x100 8003724: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8003726: f7fe faa1 bl 8001c6c 800372a: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 800372c: e008 b.n 8003740 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 800372e: f7fe fa9d bl 8001c6c 8003732: 4602 mov r2, r0 8003734: 693b ldr r3, [r7, #16] 8003736: 1ad3 subs r3, r2, r3 8003738: 2b64 cmp r3, #100 ; 0x64 800373a: d901 bls.n 8003740 { return HAL_TIMEOUT; 800373c: 2303 movs r3, #3 800373e: e0fd b.n 800393c while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8003740: 4b81 ldr r3, [pc, #516] ; (8003948 ) 8003742: 681b ldr r3, [r3, #0] 8003744: f403 7380 and.w r3, r3, #256 ; 0x100 8003748: 2b00 cmp r3, #0 800374a: d0f0 beq.n 800372e } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 800374c: 687b ldr r3, [r7, #4] 800374e: 68db ldr r3, [r3, #12] 8003750: 2b01 cmp r3, #1 8003752: d106 bne.n 8003762 8003754: 4b7b ldr r3, [pc, #492] ; (8003944 ) 8003756: 6a1b ldr r3, [r3, #32] 8003758: 4a7a ldr r2, [pc, #488] ; (8003944 ) 800375a: f043 0301 orr.w r3, r3, #1 800375e: 6213 str r3, [r2, #32] 8003760: e02d b.n 80037be 8003762: 687b ldr r3, [r7, #4] 8003764: 68db ldr r3, [r3, #12] 8003766: 2b00 cmp r3, #0 8003768: d10c bne.n 8003784 800376a: 4b76 ldr r3, [pc, #472] ; (8003944 ) 800376c: 6a1b ldr r3, [r3, #32] 800376e: 4a75 ldr r2, [pc, #468] ; (8003944 ) 8003770: f023 0301 bic.w r3, r3, #1 8003774: 6213 str r3, [r2, #32] 8003776: 4b73 ldr r3, [pc, #460] ; (8003944 ) 8003778: 6a1b ldr r3, [r3, #32] 800377a: 4a72 ldr r2, [pc, #456] ; (8003944 ) 800377c: f023 0304 bic.w r3, r3, #4 8003780: 6213 str r3, [r2, #32] 8003782: e01c b.n 80037be 8003784: 687b ldr r3, [r7, #4] 8003786: 68db ldr r3, [r3, #12] 8003788: 2b05 cmp r3, #5 800378a: d10c bne.n 80037a6 800378c: 4b6d ldr r3, [pc, #436] ; (8003944 ) 800378e: 6a1b ldr r3, [r3, #32] 8003790: 4a6c ldr r2, [pc, #432] ; (8003944 ) 8003792: f043 0304 orr.w r3, r3, #4 8003796: 6213 str r3, [r2, #32] 8003798: 4b6a ldr r3, [pc, #424] ; (8003944 ) 800379a: 6a1b ldr r3, [r3, #32] 800379c: 4a69 ldr r2, [pc, #420] ; (8003944 ) 800379e: f043 0301 orr.w r3, r3, #1 80037a2: 6213 str r3, [r2, #32] 80037a4: e00b b.n 80037be 80037a6: 4b67 ldr r3, [pc, #412] ; (8003944 ) 80037a8: 6a1b ldr r3, [r3, #32] 80037aa: 4a66 ldr r2, [pc, #408] ; (8003944 ) 80037ac: f023 0301 bic.w r3, r3, #1 80037b0: 6213 str r3, [r2, #32] 80037b2: 4b64 ldr r3, [pc, #400] ; (8003944 ) 80037b4: 6a1b ldr r3, [r3, #32] 80037b6: 4a63 ldr r2, [pc, #396] ; (8003944 ) 80037b8: f023 0304 bic.w r3, r3, #4 80037bc: 6213 str r3, [r2, #32] /* Check the LSE State */ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 80037be: 687b ldr r3, [r7, #4] 80037c0: 68db ldr r3, [r3, #12] 80037c2: 2b00 cmp r3, #0 80037c4: d015 beq.n 80037f2 { /* Get Start Tick */ tickstart = HAL_GetTick(); 80037c6: f7fe fa51 bl 8001c6c 80037ca: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80037cc: e00a b.n 80037e4 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 80037ce: f7fe fa4d bl 8001c6c 80037d2: 4602 mov r2, r0 80037d4: 693b ldr r3, [r7, #16] 80037d6: 1ad3 subs r3, r2, r3 80037d8: f241 3288 movw r2, #5000 ; 0x1388 80037dc: 4293 cmp r3, r2 80037de: d901 bls.n 80037e4 { return HAL_TIMEOUT; 80037e0: 2303 movs r3, #3 80037e2: e0ab b.n 800393c while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80037e4: 4b57 ldr r3, [pc, #348] ; (8003944 ) 80037e6: 6a1b ldr r3, [r3, #32] 80037e8: f003 0302 and.w r3, r3, #2 80037ec: 2b00 cmp r3, #0 80037ee: d0ee beq.n 80037ce 80037f0: e014 b.n 800381c } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 80037f2: f7fe fa3b bl 8001c6c 80037f6: 6138 str r0, [r7, #16] /* Wait till LSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 80037f8: e00a b.n 8003810 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 80037fa: f7fe fa37 bl 8001c6c 80037fe: 4602 mov r2, r0 8003800: 693b ldr r3, [r7, #16] 8003802: 1ad3 subs r3, r2, r3 8003804: f241 3288 movw r2, #5000 ; 0x1388 8003808: 4293 cmp r3, r2 800380a: d901 bls.n 8003810 { return HAL_TIMEOUT; 800380c: 2303 movs r3, #3 800380e: e095 b.n 800393c while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8003810: 4b4c ldr r3, [pc, #304] ; (8003944 ) 8003812: 6a1b ldr r3, [r3, #32] 8003814: f003 0302 and.w r3, r3, #2 8003818: 2b00 cmp r3, #0 800381a: d1ee bne.n 80037fa } } } /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 800381c: 7dfb ldrb r3, [r7, #23] 800381e: 2b01 cmp r3, #1 8003820: d105 bne.n 800382e { __HAL_RCC_PWR_CLK_DISABLE(); 8003822: 4b48 ldr r3, [pc, #288] ; (8003944 ) 8003824: 69db ldr r3, [r3, #28] 8003826: 4a47 ldr r2, [pc, #284] ; (8003944 ) 8003828: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 800382c: 61d3 str r3, [r2, #28] #endif /* RCC_CR_PLL2ON */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 800382e: 687b ldr r3, [r7, #4] 8003830: 69db ldr r3, [r3, #28] 8003832: 2b00 cmp r3, #0 8003834: f000 8081 beq.w 800393a { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 8003838: 4b42 ldr r3, [pc, #264] ; (8003944 ) 800383a: 685b ldr r3, [r3, #4] 800383c: f003 030c and.w r3, r3, #12 8003840: 2b08 cmp r3, #8 8003842: d061 beq.n 8003908 { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 8003844: 687b ldr r3, [r7, #4] 8003846: 69db ldr r3, [r3, #28] 8003848: 2b02 cmp r3, #2 800384a: d146 bne.n 80038da /* Check the parameters */ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 800384c: 4b3f ldr r3, [pc, #252] ; (800394c ) 800384e: 2200 movs r2, #0 8003850: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8003852: f7fe fa0b bl 8001c6c 8003856: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8003858: e008 b.n 800386c { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800385a: f7fe fa07 bl 8001c6c 800385e: 4602 mov r2, r0 8003860: 693b ldr r3, [r7, #16] 8003862: 1ad3 subs r3, r2, r3 8003864: 2b02 cmp r3, #2 8003866: d901 bls.n 800386c { return HAL_TIMEOUT; 8003868: 2303 movs r3, #3 800386a: e067 b.n 800393c while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 800386c: 4b35 ldr r3, [pc, #212] ; (8003944 ) 800386e: 681b ldr r3, [r3, #0] 8003870: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8003874: 2b00 cmp r3, #0 8003876: d1f0 bne.n 800385a } } /* Configure the HSE prediv factor --------------------------------*/ /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */ if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE) 8003878: 687b ldr r3, [r7, #4] 800387a: 6a1b ldr r3, [r3, #32] 800387c: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8003880: d108 bne.n 8003894 /* Set PREDIV1 source */ SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source); #endif /* RCC_CFGR2_PREDIV1SRC */ /* Set PREDIV1 Value */ __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); 8003882: 4b30 ldr r3, [pc, #192] ; (8003944 ) 8003884: 6adb ldr r3, [r3, #44] ; 0x2c 8003886: f023 020f bic.w r2, r3, #15 800388a: 687b ldr r3, [r7, #4] 800388c: 689b ldr r3, [r3, #8] 800388e: 492d ldr r1, [pc, #180] ; (8003944 ) 8003890: 4313 orrs r3, r2 8003892: 62cb str r3, [r1, #44] ; 0x2c } /* Configure the main PLL clock source and multiplication factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 8003894: 4b2b ldr r3, [pc, #172] ; (8003944 ) 8003896: 685b ldr r3, [r3, #4] 8003898: f423 1274 bic.w r2, r3, #3997696 ; 0x3d0000 800389c: 687b ldr r3, [r7, #4] 800389e: 6a19 ldr r1, [r3, #32] 80038a0: 687b ldr r3, [r7, #4] 80038a2: 6a5b ldr r3, [r3, #36] ; 0x24 80038a4: 430b orrs r3, r1 80038a6: 4927 ldr r1, [pc, #156] ; (8003944 ) 80038a8: 4313 orrs r3, r2 80038aa: 604b str r3, [r1, #4] RCC_OscInitStruct->PLL.PLLMUL); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 80038ac: 4b27 ldr r3, [pc, #156] ; (800394c ) 80038ae: 2201 movs r2, #1 80038b0: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80038b2: f7fe f9db bl 8001c6c 80038b6: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 80038b8: e008 b.n 80038cc { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80038ba: f7fe f9d7 bl 8001c6c 80038be: 4602 mov r2, r0 80038c0: 693b ldr r3, [r7, #16] 80038c2: 1ad3 subs r3, r2, r3 80038c4: 2b02 cmp r3, #2 80038c6: d901 bls.n 80038cc { return HAL_TIMEOUT; 80038c8: 2303 movs r3, #3 80038ca: e037 b.n 800393c while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 80038cc: 4b1d ldr r3, [pc, #116] ; (8003944 ) 80038ce: 681b ldr r3, [r3, #0] 80038d0: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 80038d4: 2b00 cmp r3, #0 80038d6: d0f0 beq.n 80038ba 80038d8: e02f b.n 800393a } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 80038da: 4b1c ldr r3, [pc, #112] ; (800394c ) 80038dc: 2200 movs r2, #0 80038de: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80038e0: f7fe f9c4 bl 8001c6c 80038e4: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80038e6: e008 b.n 80038fa { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80038e8: f7fe f9c0 bl 8001c6c 80038ec: 4602 mov r2, r0 80038ee: 693b ldr r3, [r7, #16] 80038f0: 1ad3 subs r3, r2, r3 80038f2: 2b02 cmp r3, #2 80038f4: d901 bls.n 80038fa { return HAL_TIMEOUT; 80038f6: 2303 movs r3, #3 80038f8: e020 b.n 800393c while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80038fa: 4b12 ldr r3, [pc, #72] ; (8003944 ) 80038fc: 681b ldr r3, [r3, #0] 80038fe: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8003902: 2b00 cmp r3, #0 8003904: d1f0 bne.n 80038e8 8003906: e018 b.n 800393a } } else { /* Check if there is a request to disable the PLL used as System clock source */ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 8003908: 687b ldr r3, [r7, #4] 800390a: 69db ldr r3, [r3, #28] 800390c: 2b01 cmp r3, #1 800390e: d101 bne.n 8003914 { return HAL_ERROR; 8003910: 2301 movs r3, #1 8003912: e013 b.n 800393c } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->CFGR; 8003914: 4b0b ldr r3, [pc, #44] ; (8003944 ) 8003916: 685b ldr r3, [r3, #4] 8003918: 60fb str r3, [r7, #12] if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 800391a: 68fb ldr r3, [r7, #12] 800391c: f403 3280 and.w r2, r3, #65536 ; 0x10000 8003920: 687b ldr r3, [r7, #4] 8003922: 6a1b ldr r3, [r3, #32] 8003924: 429a cmp r2, r3 8003926: d106 bne.n 8003936 (READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL)) 8003928: 68fb ldr r3, [r7, #12] 800392a: f403 1270 and.w r2, r3, #3932160 ; 0x3c0000 800392e: 687b ldr r3, [r7, #4] 8003930: 6a5b ldr r3, [r3, #36] ; 0x24 if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8003932: 429a cmp r2, r3 8003934: d001 beq.n 800393a { return HAL_ERROR; 8003936: 2301 movs r3, #1 8003938: e000 b.n 800393c } } } } return HAL_OK; 800393a: 2300 movs r3, #0 } 800393c: 4618 mov r0, r3 800393e: 3718 adds r7, #24 8003940: 46bd mov sp, r7 8003942: bd80 pop {r7, pc} 8003944: 40021000 .word 0x40021000 8003948: 40007000 .word 0x40007000 800394c: 42420060 .word 0x42420060 08003950 : * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8003950: b580 push {r7, lr} 8003952: b084 sub sp, #16 8003954: af00 add r7, sp, #0 8003956: 6078 str r0, [r7, #4] 8003958: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 800395a: 687b ldr r3, [r7, #4] 800395c: 2b00 cmp r3, #0 800395e: d101 bne.n 8003964 { return HAL_ERROR; 8003960: 2301 movs r3, #1 8003962: e0a0 b.n 8003aa6 } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8003964: 687b ldr r3, [r7, #4] 8003966: 681b ldr r3, [r3, #0] 8003968: f003 0302 and.w r3, r3, #2 800396c: 2b00 cmp r3, #0 800396e: d020 beq.n 80039b2 { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8003970: 687b ldr r3, [r7, #4] 8003972: 681b ldr r3, [r3, #0] 8003974: f003 0304 and.w r3, r3, #4 8003978: 2b00 cmp r3, #0 800397a: d005 beq.n 8003988 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 800397c: 4b4c ldr r3, [pc, #304] ; (8003ab0 ) 800397e: 685b ldr r3, [r3, #4] 8003980: 4a4b ldr r2, [pc, #300] ; (8003ab0 ) 8003982: f443 63e0 orr.w r3, r3, #1792 ; 0x700 8003986: 6053 str r3, [r2, #4] } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8003988: 687b ldr r3, [r7, #4] 800398a: 681b ldr r3, [r3, #0] 800398c: f003 0308 and.w r3, r3, #8 8003990: 2b00 cmp r3, #0 8003992: d005 beq.n 80039a0 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); 8003994: 4b46 ldr r3, [pc, #280] ; (8003ab0 ) 8003996: 685b ldr r3, [r3, #4] 8003998: 4a45 ldr r2, [pc, #276] ; (8003ab0 ) 800399a: f443 5360 orr.w r3, r3, #14336 ; 0x3800 800399e: 6053 str r3, [r2, #4] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 80039a0: 4b43 ldr r3, [pc, #268] ; (8003ab0 ) 80039a2: 685b ldr r3, [r3, #4] 80039a4: f023 02f0 bic.w r2, r3, #240 ; 0xf0 80039a8: 687b ldr r3, [r7, #4] 80039aa: 689b ldr r3, [r3, #8] 80039ac: 4940 ldr r1, [pc, #256] ; (8003ab0 ) 80039ae: 4313 orrs r3, r2 80039b0: 604b str r3, [r1, #4] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 80039b2: 687b ldr r3, [r7, #4] 80039b4: 681b ldr r3, [r3, #0] 80039b6: f003 0301 and.w r3, r3, #1 80039ba: 2b00 cmp r3, #0 80039bc: d040 beq.n 8003a40 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 80039be: 687b ldr r3, [r7, #4] 80039c0: 685b ldr r3, [r3, #4] 80039c2: 2b01 cmp r3, #1 80039c4: d107 bne.n 80039d6 { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 80039c6: 4b3a ldr r3, [pc, #232] ; (8003ab0 ) 80039c8: 681b ldr r3, [r3, #0] 80039ca: f403 3300 and.w r3, r3, #131072 ; 0x20000 80039ce: 2b00 cmp r3, #0 80039d0: d115 bne.n 80039fe { return HAL_ERROR; 80039d2: 2301 movs r3, #1 80039d4: e067 b.n 8003aa6 } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 80039d6: 687b ldr r3, [r7, #4] 80039d8: 685b ldr r3, [r3, #4] 80039da: 2b02 cmp r3, #2 80039dc: d107 bne.n 80039ee { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 80039de: 4b34 ldr r3, [pc, #208] ; (8003ab0 ) 80039e0: 681b ldr r3, [r3, #0] 80039e2: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 80039e6: 2b00 cmp r3, #0 80039e8: d109 bne.n 80039fe { return HAL_ERROR; 80039ea: 2301 movs r3, #1 80039ec: e05b b.n 8003aa6 } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 80039ee: 4b30 ldr r3, [pc, #192] ; (8003ab0 ) 80039f0: 681b ldr r3, [r3, #0] 80039f2: f003 0302 and.w r3, r3, #2 80039f6: 2b00 cmp r3, #0 80039f8: d101 bne.n 80039fe { return HAL_ERROR; 80039fa: 2301 movs r3, #1 80039fc: e053 b.n 8003aa6 } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 80039fe: 4b2c ldr r3, [pc, #176] ; (8003ab0 ) 8003a00: 685b ldr r3, [r3, #4] 8003a02: f023 0203 bic.w r2, r3, #3 8003a06: 687b ldr r3, [r7, #4] 8003a08: 685b ldr r3, [r3, #4] 8003a0a: 4929 ldr r1, [pc, #164] ; (8003ab0 ) 8003a0c: 4313 orrs r3, r2 8003a0e: 604b str r3, [r1, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); 8003a10: f7fe f92c bl 8001c6c 8003a14: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8003a16: e00a b.n 8003a2e { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8003a18: f7fe f928 bl 8001c6c 8003a1c: 4602 mov r2, r0 8003a1e: 68fb ldr r3, [r7, #12] 8003a20: 1ad3 subs r3, r2, r3 8003a22: f241 3288 movw r2, #5000 ; 0x1388 8003a26: 4293 cmp r3, r2 8003a28: d901 bls.n 8003a2e { return HAL_TIMEOUT; 8003a2a: 2303 movs r3, #3 8003a2c: e03b b.n 8003aa6 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8003a2e: 4b20 ldr r3, [pc, #128] ; (8003ab0 ) 8003a30: 685b ldr r3, [r3, #4] 8003a32: f003 020c and.w r2, r3, #12 8003a36: 687b ldr r3, [r7, #4] 8003a38: 685b ldr r3, [r3, #4] 8003a3a: 009b lsls r3, r3, #2 8003a3c: 429a cmp r2, r3 8003a3e: d1eb bne.n 8003a18 } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8003a40: 687b ldr r3, [r7, #4] 8003a42: 681b ldr r3, [r3, #0] 8003a44: f003 0304 and.w r3, r3, #4 8003a48: 2b00 cmp r3, #0 8003a4a: d008 beq.n 8003a5e { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 8003a4c: 4b18 ldr r3, [pc, #96] ; (8003ab0 ) 8003a4e: 685b ldr r3, [r3, #4] 8003a50: f423 62e0 bic.w r2, r3, #1792 ; 0x700 8003a54: 687b ldr r3, [r7, #4] 8003a56: 68db ldr r3, [r3, #12] 8003a58: 4915 ldr r1, [pc, #84] ; (8003ab0 ) 8003a5a: 4313 orrs r3, r2 8003a5c: 604b str r3, [r1, #4] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8003a5e: 687b ldr r3, [r7, #4] 8003a60: 681b ldr r3, [r3, #0] 8003a62: f003 0308 and.w r3, r3, #8 8003a66: 2b00 cmp r3, #0 8003a68: d009 beq.n 8003a7e { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); 8003a6a: 4b11 ldr r3, [pc, #68] ; (8003ab0 ) 8003a6c: 685b ldr r3, [r3, #4] 8003a6e: f423 5260 bic.w r2, r3, #14336 ; 0x3800 8003a72: 687b ldr r3, [r7, #4] 8003a74: 691b ldr r3, [r3, #16] 8003a76: 00db lsls r3, r3, #3 8003a78: 490d ldr r1, [pc, #52] ; (8003ab0 ) 8003a7a: 4313 orrs r3, r2 8003a7c: 604b str r3, [r1, #4] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; 8003a7e: f000 f81f bl 8003ac0 8003a82: 4601 mov r1, r0 8003a84: 4b0a ldr r3, [pc, #40] ; (8003ab0 ) 8003a86: 685b ldr r3, [r3, #4] 8003a88: 091b lsrs r3, r3, #4 8003a8a: f003 030f and.w r3, r3, #15 8003a8e: 4a09 ldr r2, [pc, #36] ; (8003ab4 ) 8003a90: 5cd3 ldrb r3, [r2, r3] 8003a92: fa21 f303 lsr.w r3, r1, r3 8003a96: 4a08 ldr r2, [pc, #32] ; (8003ab8 ) 8003a98: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick(uwTickPrio); 8003a9a: 4b08 ldr r3, [pc, #32] ; (8003abc ) 8003a9c: 681b ldr r3, [r3, #0] 8003a9e: 4618 mov r0, r3 8003aa0: f002 f870 bl 8005b84 return HAL_OK; 8003aa4: 2300 movs r3, #0 } 8003aa6: 4618 mov r0, r3 8003aa8: 3710 adds r7, #16 8003aaa: 46bd mov sp, r7 8003aac: bd80 pop {r7, pc} 8003aae: bf00 nop 8003ab0: 40021000 .word 0x40021000 8003ab4: 08008b98 .word 0x08008b98 8003ab8: 20000008 .word 0x20000008 8003abc: 20000000 .word 0x20000000 08003ac0 : * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 8003ac0: b490 push {r4, r7} 8003ac2: b08e sub sp, #56 ; 0x38 8003ac4: af00 add r7, sp, #0 #if defined(RCC_CFGR2_PREDIV1SRC) const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13}; const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; #else const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; 8003ac6: 4b2b ldr r3, [pc, #172] ; (8003b74 ) 8003ac8: f107 0414 add.w r4, r7, #20 8003acc: cb0f ldmia r3, {r0, r1, r2, r3} 8003ace: e884 000f stmia.w r4, {r0, r1, r2, r3} #if defined(RCC_CFGR2_PREDIV1) const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; 8003ad2: 4b29 ldr r3, [pc, #164] ; (8003b78 ) 8003ad4: 1d3c adds r4, r7, #4 8003ad6: cb0f ldmia r3, {r0, r1, r2, r3} 8003ad8: e884 000f stmia.w r4, {r0, r1, r2, r3} #else const uint8_t aPredivFactorTable[2] = {1, 2}; #endif /*RCC_CFGR2_PREDIV1*/ #endif uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; 8003adc: 2300 movs r3, #0 8003ade: 62fb str r3, [r7, #44] ; 0x2c 8003ae0: 2300 movs r3, #0 8003ae2: 62bb str r3, [r7, #40] ; 0x28 8003ae4: 2300 movs r3, #0 8003ae6: 637b str r3, [r7, #52] ; 0x34 8003ae8: 2300 movs r3, #0 8003aea: 627b str r3, [r7, #36] ; 0x24 uint32_t sysclockfreq = 0U; 8003aec: 2300 movs r3, #0 8003aee: 633b str r3, [r7, #48] ; 0x30 #if defined(RCC_CFGR2_PREDIV1SRC) uint32_t prediv2 = 0U, pll2mul = 0U; #endif /*RCC_CFGR2_PREDIV1SRC*/ tmpreg = RCC->CFGR; 8003af0: 4b22 ldr r3, [pc, #136] ; (8003b7c ) 8003af2: 685b ldr r3, [r3, #4] 8003af4: 62fb str r3, [r7, #44] ; 0x2c /* Get SYSCLK source -------------------------------------------------------*/ switch (tmpreg & RCC_CFGR_SWS) 8003af6: 6afb ldr r3, [r7, #44] ; 0x2c 8003af8: f003 030c and.w r3, r3, #12 8003afc: 2b04 cmp r3, #4 8003afe: d002 beq.n 8003b06 8003b00: 2b08 cmp r3, #8 8003b02: d003 beq.n 8003b0c 8003b04: e02c b.n 8003b60 { case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ { sysclockfreq = HSE_VALUE; 8003b06: 4b1e ldr r3, [pc, #120] ; (8003b80 ) 8003b08: 633b str r3, [r7, #48] ; 0x30 break; 8003b0a: e02c b.n 8003b66 } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ { pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; 8003b0c: 6afb ldr r3, [r7, #44] ; 0x2c 8003b0e: 0c9b lsrs r3, r3, #18 8003b10: f003 030f and.w r3, r3, #15 8003b14: f107 0238 add.w r2, r7, #56 ; 0x38 8003b18: 4413 add r3, r2 8003b1a: f813 3c24 ldrb.w r3, [r3, #-36] 8003b1e: 627b str r3, [r7, #36] ; 0x24 if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) 8003b20: 6afb ldr r3, [r7, #44] ; 0x2c 8003b22: f403 3380 and.w r3, r3, #65536 ; 0x10000 8003b26: 2b00 cmp r3, #0 8003b28: d012 beq.n 8003b50 { #if defined(RCC_CFGR2_PREDIV1) prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; 8003b2a: 4b14 ldr r3, [pc, #80] ; (8003b7c ) 8003b2c: 6adb ldr r3, [r3, #44] ; 0x2c 8003b2e: f003 030f and.w r3, r3, #15 8003b32: f107 0238 add.w r2, r7, #56 ; 0x38 8003b36: 4413 add r3, r2 8003b38: f813 3c34 ldrb.w r3, [r3, #-52] 8003b3c: 62bb str r3, [r7, #40] ; 0x28 { pllclk = pllclk / 2; } #else /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv); 8003b3e: 6a7b ldr r3, [r7, #36] ; 0x24 8003b40: 4a0f ldr r2, [pc, #60] ; (8003b80 ) 8003b42: fb02 f203 mul.w r2, r2, r3 8003b46: 6abb ldr r3, [r7, #40] ; 0x28 8003b48: fbb2 f3f3 udiv r3, r2, r3 8003b4c: 637b str r3, [r7, #52] ; 0x34 8003b4e: e004 b.n 8003b5a #endif /*RCC_CFGR2_PREDIV1SRC*/ } else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); 8003b50: 6a7b ldr r3, [r7, #36] ; 0x24 8003b52: 4a0c ldr r2, [pc, #48] ; (8003b84 ) 8003b54: fb02 f303 mul.w r3, r2, r3 8003b58: 637b str r3, [r7, #52] ; 0x34 } sysclockfreq = pllclk; 8003b5a: 6b7b ldr r3, [r7, #52] ; 0x34 8003b5c: 633b str r3, [r7, #48] ; 0x30 break; 8003b5e: e002 b.n 8003b66 } case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ default: /* HSI used as system clock */ { sysclockfreq = HSI_VALUE; 8003b60: 4b07 ldr r3, [pc, #28] ; (8003b80 ) 8003b62: 633b str r3, [r7, #48] ; 0x30 break; 8003b64: bf00 nop } } return sysclockfreq; 8003b66: 6b3b ldr r3, [r7, #48] ; 0x30 } 8003b68: 4618 mov r0, r3 8003b6a: 3738 adds r7, #56 ; 0x38 8003b6c: 46bd mov sp, r7 8003b6e: bc90 pop {r4, r7} 8003b70: 4770 bx lr 8003b72: bf00 nop 8003b74: 08008aec .word 0x08008aec 8003b78: 08008afc .word 0x08008afc 8003b7c: 40021000 .word 0x40021000 8003b80: 007a1200 .word 0x007a1200 8003b84: 003d0900 .word 0x003d0900 08003b88 : * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 8003b88: b480 push {r7} 8003b8a: af00 add r7, sp, #0 return SystemCoreClock; 8003b8c: 4b02 ldr r3, [pc, #8] ; (8003b98 ) 8003b8e: 681b ldr r3, [r3, #0] } 8003b90: 4618 mov r0, r3 8003b92: 46bd mov sp, r7 8003b94: bc80 pop {r7} 8003b96: 4770 bx lr 8003b98: 20000008 .word 0x20000008 08003b9c : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 8003b9c: b580 push {r7, lr} 8003b9e: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); 8003ba0: f7ff fff2 bl 8003b88 8003ba4: 4601 mov r1, r0 8003ba6: 4b05 ldr r3, [pc, #20] ; (8003bbc ) 8003ba8: 685b ldr r3, [r3, #4] 8003baa: 0a1b lsrs r3, r3, #8 8003bac: f003 0307 and.w r3, r3, #7 8003bb0: 4a03 ldr r2, [pc, #12] ; (8003bc0 ) 8003bb2: 5cd3 ldrb r3, [r2, r3] 8003bb4: fa21 f303 lsr.w r3, r1, r3 } 8003bb8: 4618 mov r0, r3 8003bba: bd80 pop {r7, pc} 8003bbc: 40021000 .word 0x40021000 8003bc0: 08008ba8 .word 0x08008ba8 08003bc4 : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 8003bc4: b580 push {r7, lr} 8003bc6: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); 8003bc8: f7ff ffde bl 8003b88 8003bcc: 4601 mov r1, r0 8003bce: 4b05 ldr r3, [pc, #20] ; (8003be4 ) 8003bd0: 685b ldr r3, [r3, #4] 8003bd2: 0adb lsrs r3, r3, #11 8003bd4: f003 0307 and.w r3, r3, #7 8003bd8: 4a03 ldr r2, [pc, #12] ; (8003be8 ) 8003bda: 5cd3 ldrb r3, [r2, r3] 8003bdc: fa21 f303 lsr.w r3, r1, r3 } 8003be0: 4618 mov r0, r3 8003be2: bd80 pop {r7, pc} 8003be4: 40021000 .word 0x40021000 8003be8: 08008ba8 .word 0x08008ba8 08003bec : * contains the current clock configuration. * @param pFLatency Pointer on the Flash Latency. * @retval None */ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) { 8003bec: b480 push {r7} 8003bee: b083 sub sp, #12 8003bf0: af00 add r7, sp, #0 8003bf2: 6078 str r0, [r7, #4] 8003bf4: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(RCC_ClkInitStruct != NULL); assert_param(pFLatency != NULL); /* Set all possible values for the Clock type parameter --------------------*/ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; 8003bf6: 687b ldr r3, [r7, #4] 8003bf8: 220f movs r2, #15 8003bfa: 601a str r2, [r3, #0] /* Get the SYSCLK configuration --------------------------------------------*/ RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); 8003bfc: 4b10 ldr r3, [pc, #64] ; (8003c40 ) 8003bfe: 685b ldr r3, [r3, #4] 8003c00: f003 0203 and.w r2, r3, #3 8003c04: 687b ldr r3, [r7, #4] 8003c06: 605a str r2, [r3, #4] /* Get the HCLK configuration ----------------------------------------------*/ RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); 8003c08: 4b0d ldr r3, [pc, #52] ; (8003c40 ) 8003c0a: 685b ldr r3, [r3, #4] 8003c0c: f003 02f0 and.w r2, r3, #240 ; 0xf0 8003c10: 687b ldr r3, [r7, #4] 8003c12: 609a str r2, [r3, #8] /* Get the APB1 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); 8003c14: 4b0a ldr r3, [pc, #40] ; (8003c40 ) 8003c16: 685b ldr r3, [r3, #4] 8003c18: f403 62e0 and.w r2, r3, #1792 ; 0x700 8003c1c: 687b ldr r3, [r7, #4] 8003c1e: 60da str r2, [r3, #12] /* Get the APB2 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3); 8003c20: 4b07 ldr r3, [pc, #28] ; (8003c40 ) 8003c22: 685b ldr r3, [r3, #4] 8003c24: 08db lsrs r3, r3, #3 8003c26: f403 62e0 and.w r2, r3, #1792 ; 0x700 8003c2a: 687b ldr r3, [r7, #4] 8003c2c: 611a str r2, [r3, #16] #if defined(FLASH_ACR_LATENCY) /* Get the Flash Wait State (Latency) configuration ------------------------*/ *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); #else /* For VALUE lines devices, only LATENCY_0 can be set*/ *pFLatency = (uint32_t)FLASH_LATENCY_0; 8003c2e: 683b ldr r3, [r7, #0] 8003c30: 2200 movs r2, #0 8003c32: 601a str r2, [r3, #0] #endif } 8003c34: bf00 nop 8003c36: 370c adds r7, #12 8003c38: 46bd mov sp, r7 8003c3a: bc80 pop {r7} 8003c3c: 4770 bx lr 8003c3e: bf00 nop 8003c40: 40021000 .word 0x40021000 08003c44 : * @brief This function provides delay (in milliseconds) based on CPU cycles method. * @param mdelay: specifies the delay time length, in milliseconds. * @retval None */ static void RCC_Delay(uint32_t mdelay) { 8003c44: b480 push {r7} 8003c46: b085 sub sp, #20 8003c48: af00 add r7, sp, #0 8003c4a: 6078 str r0, [r7, #4] __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U); 8003c4c: 4b0a ldr r3, [pc, #40] ; (8003c78 ) 8003c4e: 681b ldr r3, [r3, #0] 8003c50: 4a0a ldr r2, [pc, #40] ; (8003c7c ) 8003c52: fba2 2303 umull r2, r3, r2, r3 8003c56: 0a5b lsrs r3, r3, #9 8003c58: 687a ldr r2, [r7, #4] 8003c5a: fb02 f303 mul.w r3, r2, r3 8003c5e: 60fb str r3, [r7, #12] do { __NOP(); 8003c60: bf00 nop } while (Delay --); 8003c62: 68fb ldr r3, [r7, #12] 8003c64: 1e5a subs r2, r3, #1 8003c66: 60fa str r2, [r7, #12] 8003c68: 2b00 cmp r3, #0 8003c6a: d1f9 bne.n 8003c60 } 8003c6c: bf00 nop 8003c6e: 3714 adds r7, #20 8003c70: 46bd mov sp, r7 8003c72: bc80 pop {r7} 8003c74: 4770 bx lr 8003c76: bf00 nop 8003c78: 20000008 .word 0x20000008 8003c7c: 10624dd3 .word 0x10624dd3 08003c80 : * manually disable it. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 8003c80: b580 push {r7, lr} 8003c82: b086 sub sp, #24 8003c84: af00 add r7, sp, #0 8003c86: 6078 str r0, [r7, #4] uint32_t tickstart = 0U, temp_reg = 0U; 8003c88: 2300 movs r3, #0 8003c8a: 613b str r3, [r7, #16] 8003c8c: 2300 movs r3, #0 8003c8e: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*------------------------------- RTC/LCD Configuration ------------------------*/ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 8003c90: 687b ldr r3, [r7, #4] 8003c92: 681b ldr r3, [r3, #0] 8003c94: f003 0301 and.w r3, r3, #1 8003c98: 2b00 cmp r3, #0 8003c9a: d07d beq.n 8003d98 { /* check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); FlagStatus pwrclkchanged = RESET; 8003c9c: 2300 movs r3, #0 8003c9e: 75fb strb r3, [r7, #23] /* As soon as function is called to change RTC clock source, activation of the power domain is done. */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 8003ca0: 4b47 ldr r3, [pc, #284] ; (8003dc0 ) 8003ca2: 69db ldr r3, [r3, #28] 8003ca4: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8003ca8: 2b00 cmp r3, #0 8003caa: d10d bne.n 8003cc8 { __HAL_RCC_PWR_CLK_ENABLE(); 8003cac: 4b44 ldr r3, [pc, #272] ; (8003dc0 ) 8003cae: 69db ldr r3, [r3, #28] 8003cb0: 4a43 ldr r2, [pc, #268] ; (8003dc0 ) 8003cb2: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8003cb6: 61d3 str r3, [r2, #28] 8003cb8: 4b41 ldr r3, [pc, #260] ; (8003dc0 ) 8003cba: 69db ldr r3, [r3, #28] 8003cbc: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8003cc0: 60bb str r3, [r7, #8] 8003cc2: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 8003cc4: 2301 movs r3, #1 8003cc6: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8003cc8: 4b3e ldr r3, [pc, #248] ; (8003dc4 ) 8003cca: 681b ldr r3, [r3, #0] 8003ccc: f403 7380 and.w r3, r3, #256 ; 0x100 8003cd0: 2b00 cmp r3, #0 8003cd2: d118 bne.n 8003d06 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8003cd4: 4b3b ldr r3, [pc, #236] ; (8003dc4 ) 8003cd6: 681b ldr r3, [r3, #0] 8003cd8: 4a3a ldr r2, [pc, #232] ; (8003dc4 ) 8003cda: f443 7380 orr.w r3, r3, #256 ; 0x100 8003cde: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8003ce0: f7fd ffc4 bl 8001c6c 8003ce4: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8003ce6: e008 b.n 8003cfa { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8003ce8: f7fd ffc0 bl 8001c6c 8003cec: 4602 mov r2, r0 8003cee: 693b ldr r3, [r7, #16] 8003cf0: 1ad3 subs r3, r2, r3 8003cf2: 2b64 cmp r3, #100 ; 0x64 8003cf4: d901 bls.n 8003cfa { return HAL_TIMEOUT; 8003cf6: 2303 movs r3, #3 8003cf8: e05e b.n 8003db8 while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8003cfa: 4b32 ldr r3, [pc, #200] ; (8003dc4 ) 8003cfc: 681b ldr r3, [r3, #0] 8003cfe: f403 7380 and.w r3, r3, #256 ; 0x100 8003d02: 2b00 cmp r3, #0 8003d04: d0f0 beq.n 8003ce8 } } } /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); 8003d06: 4b2e ldr r3, [pc, #184] ; (8003dc0 ) 8003d08: 6a1b ldr r3, [r3, #32] 8003d0a: f403 7340 and.w r3, r3, #768 ; 0x300 8003d0e: 60fb str r3, [r7, #12] if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) 8003d10: 68fb ldr r3, [r7, #12] 8003d12: 2b00 cmp r3, #0 8003d14: d02e beq.n 8003d74 8003d16: 687b ldr r3, [r7, #4] 8003d18: 685b ldr r3, [r3, #4] 8003d1a: f403 7340 and.w r3, r3, #768 ; 0x300 8003d1e: 68fa ldr r2, [r7, #12] 8003d20: 429a cmp r2, r3 8003d22: d027 beq.n 8003d74 { /* Store the content of BDCR register before the reset of Backup Domain */ temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 8003d24: 4b26 ldr r3, [pc, #152] ; (8003dc0 ) 8003d26: 6a1b ldr r3, [r3, #32] 8003d28: f423 7340 bic.w r3, r3, #768 ; 0x300 8003d2c: 60fb str r3, [r7, #12] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 8003d2e: 4b26 ldr r3, [pc, #152] ; (8003dc8 ) 8003d30: 2201 movs r2, #1 8003d32: 601a str r2, [r3, #0] __HAL_RCC_BACKUPRESET_RELEASE(); 8003d34: 4b24 ldr r3, [pc, #144] ; (8003dc8 ) 8003d36: 2200 movs r2, #0 8003d38: 601a str r2, [r3, #0] /* Restore the Content of BDCR register */ RCC->BDCR = temp_reg; 8003d3a: 4a21 ldr r2, [pc, #132] ; (8003dc0 ) 8003d3c: 68fb ldr r3, [r7, #12] 8003d3e: 6213 str r3, [r2, #32] /* Wait for LSERDY if LSE was enabled */ if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) 8003d40: 68fb ldr r3, [r7, #12] 8003d42: f003 0301 and.w r3, r3, #1 8003d46: 2b00 cmp r3, #0 8003d48: d014 beq.n 8003d74 { /* Get Start Tick */ tickstart = HAL_GetTick(); 8003d4a: f7fd ff8f bl 8001c6c 8003d4e: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8003d50: e00a b.n 8003d68 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8003d52: f7fd ff8b bl 8001c6c 8003d56: 4602 mov r2, r0 8003d58: 693b ldr r3, [r7, #16] 8003d5a: 1ad3 subs r3, r2, r3 8003d5c: f241 3288 movw r2, #5000 ; 0x1388 8003d60: 4293 cmp r3, r2 8003d62: d901 bls.n 8003d68 { return HAL_TIMEOUT; 8003d64: 2303 movs r3, #3 8003d66: e027 b.n 8003db8 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8003d68: 4b15 ldr r3, [pc, #84] ; (8003dc0 ) 8003d6a: 6a1b ldr r3, [r3, #32] 8003d6c: f003 0302 and.w r3, r3, #2 8003d70: 2b00 cmp r3, #0 8003d72: d0ee beq.n 8003d52 } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 8003d74: 4b12 ldr r3, [pc, #72] ; (8003dc0 ) 8003d76: 6a1b ldr r3, [r3, #32] 8003d78: f423 7240 bic.w r2, r3, #768 ; 0x300 8003d7c: 687b ldr r3, [r7, #4] 8003d7e: 685b ldr r3, [r3, #4] 8003d80: 490f ldr r1, [pc, #60] ; (8003dc0 ) 8003d82: 4313 orrs r3, r2 8003d84: 620b str r3, [r1, #32] /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 8003d86: 7dfb ldrb r3, [r7, #23] 8003d88: 2b01 cmp r3, #1 8003d8a: d105 bne.n 8003d98 { __HAL_RCC_PWR_CLK_DISABLE(); 8003d8c: 4b0c ldr r3, [pc, #48] ; (8003dc0 ) 8003d8e: 69db ldr r3, [r3, #28] 8003d90: 4a0b ldr r2, [pc, #44] ; (8003dc0 ) 8003d92: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 8003d96: 61d3 str r3, [r2, #28] } } /*------------------------------ ADC clock Configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 8003d98: 687b ldr r3, [r7, #4] 8003d9a: 681b ldr r3, [r3, #0] 8003d9c: f003 0302 and.w r3, r3, #2 8003da0: 2b00 cmp r3, #0 8003da2: d008 beq.n 8003db6 { /* Check the parameters */ assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection)); /* Configure the ADC clock source */ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 8003da4: 4b06 ldr r3, [pc, #24] ; (8003dc0 ) 8003da6: 685b ldr r3, [r3, #4] 8003da8: f423 4240 bic.w r2, r3, #49152 ; 0xc000 8003dac: 687b ldr r3, [r7, #4] 8003dae: 689b ldr r3, [r3, #8] 8003db0: 4903 ldr r1, [pc, #12] ; (8003dc0 ) 8003db2: 4313 orrs r3, r2 8003db4: 604b str r3, [r1, #4] /* Configure the USB clock source */ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); } #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ return HAL_OK; 8003db6: 2300 movs r3, #0 } 8003db8: 4618 mov r0, r3 8003dba: 3718 adds r7, #24 8003dbc: 46bd mov sp, r7 8003dbe: bd80 pop {r7, pc} 8003dc0: 40021000 .word 0x40021000 8003dc4: 40007000 .word 0x40007000 8003dc8: 42420440 .word 0x42420440 08003dcc : * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock @endif * @retval Frequency in Hz (0: means that no available frequency for the peripheral) */ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { 8003dcc: b580 push {r7, lr} 8003dce: b084 sub sp, #16 8003dd0: af00 add r7, sp, #0 8003dd2: 6078 str r0, [r7, #4] const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; const uint8_t aPredivFactorTable[2] = {1, 2}; uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ uint32_t temp_reg = 0U, frequency = 0U; 8003dd4: 2300 movs r3, #0 8003dd6: 60bb str r3, [r7, #8] 8003dd8: 2300 movs r3, #0 8003dda: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); switch (PeriphClk) 8003ddc: 687b ldr r3, [r7, #4] 8003dde: 2b01 cmp r3, #1 8003de0: d002 beq.n 8003de8 8003de2: 2b02 cmp r3, #2 8003de4: d033 beq.n 8003e4e frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2); break; } default: { break; 8003de6: e041 b.n 8003e6c temp_reg = RCC->BDCR; 8003de8: 4b23 ldr r3, [pc, #140] ; (8003e78 ) 8003dea: 6a1b ldr r3, [r3, #32] 8003dec: 60bb str r3, [r7, #8] if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY))) 8003dee: 68bb ldr r3, [r7, #8] 8003df0: f403 7340 and.w r3, r3, #768 ; 0x300 8003df4: f5b3 7f80 cmp.w r3, #256 ; 0x100 8003df8: d108 bne.n 8003e0c 8003dfa: 68bb ldr r3, [r7, #8] 8003dfc: f003 0302 and.w r3, r3, #2 8003e00: 2b00 cmp r3, #0 8003e02: d003 beq.n 8003e0c frequency = LSE_VALUE; 8003e04: f44f 4300 mov.w r3, #32768 ; 0x8000 8003e08: 60fb str r3, [r7, #12] 8003e0a: e01f b.n 8003e4c else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) 8003e0c: 68bb ldr r3, [r7, #8] 8003e0e: f403 7340 and.w r3, r3, #768 ; 0x300 8003e12: f5b3 7f00 cmp.w r3, #512 ; 0x200 8003e16: d109 bne.n 8003e2c 8003e18: 4b17 ldr r3, [pc, #92] ; (8003e78 ) 8003e1a: 6a5b ldr r3, [r3, #36] ; 0x24 8003e1c: f003 0302 and.w r3, r3, #2 8003e20: 2b00 cmp r3, #0 8003e22: d003 beq.n 8003e2c frequency = LSI_VALUE; 8003e24: f649 4340 movw r3, #40000 ; 0x9c40 8003e28: 60fb str r3, [r7, #12] 8003e2a: e00f b.n 8003e4c else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) 8003e2c: 68bb ldr r3, [r7, #8] 8003e2e: f403 7340 and.w r3, r3, #768 ; 0x300 8003e32: f5b3 7f40 cmp.w r3, #768 ; 0x300 8003e36: d118 bne.n 8003e6a 8003e38: 4b0f ldr r3, [pc, #60] ; (8003e78 ) 8003e3a: 681b ldr r3, [r3, #0] 8003e3c: f403 3300 and.w r3, r3, #131072 ; 0x20000 8003e40: 2b00 cmp r3, #0 8003e42: d012 beq.n 8003e6a frequency = HSE_VALUE / 128U; 8003e44: f24f 4324 movw r3, #62500 ; 0xf424 8003e48: 60fb str r3, [r7, #12] break; 8003e4a: e00e b.n 8003e6a 8003e4c: e00d b.n 8003e6a frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2); 8003e4e: f7ff feb9 bl 8003bc4 8003e52: 4602 mov r2, r0 8003e54: 4b08 ldr r3, [pc, #32] ; (8003e78 ) 8003e56: 685b ldr r3, [r3, #4] 8003e58: 0b9b lsrs r3, r3, #14 8003e5a: f003 0303 and.w r3, r3, #3 8003e5e: 3301 adds r3, #1 8003e60: 005b lsls r3, r3, #1 8003e62: fbb2 f3f3 udiv r3, r2, r3 8003e66: 60fb str r3, [r7, #12] break; 8003e68: e000 b.n 8003e6c break; 8003e6a: bf00 nop } } return (frequency); 8003e6c: 68fb ldr r3, [r7, #12] } 8003e6e: 4618 mov r0, r3 8003e70: 3710 adds r7, #16 8003e72: 46bd mov sp, r7 8003e74: bd80 pop {r7, pc} 8003e76: bf00 nop 8003e78: 40021000 .word 0x40021000 08003e7c : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { 8003e7c: b580 push {r7, lr} 8003e7e: b082 sub sp, #8 8003e80: af00 add r7, sp, #0 8003e82: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8003e84: 687b ldr r3, [r7, #4] 8003e86: 2b00 cmp r3, #0 8003e88: d101 bne.n 8003e8e { return HAL_ERROR; 8003e8a: 2301 movs r3, #1 8003e8c: e01d b.n 8003eca assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8003e8e: 687b ldr r3, [r7, #4] 8003e90: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 8003e94: b2db uxtb r3, r3 8003e96: 2b00 cmp r3, #0 8003e98: d106 bne.n 8003ea8 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8003e9a: 687b ldr r3, [r7, #4] 8003e9c: 2200 movs r2, #0 8003e9e: f883 203c strb.w r2, [r3, #60] ; 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); 8003ea2: 6878 ldr r0, [r7, #4] 8003ea4: f001 fd20 bl 80058e8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8003ea8: 687b ldr r3, [r7, #4] 8003eaa: 2202 movs r2, #2 8003eac: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8003eb0: 687b ldr r3, [r7, #4] 8003eb2: 681a ldr r2, [r3, #0] 8003eb4: 687b ldr r3, [r7, #4] 8003eb6: 3304 adds r3, #4 8003eb8: 4619 mov r1, r3 8003eba: 4610 mov r0, r2 8003ebc: f000 f958 bl 8004170 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8003ec0: 687b ldr r3, [r7, #4] 8003ec2: 2201 movs r2, #1 8003ec4: f883 203d strb.w r2, [r3, #61] ; 0x3d return HAL_OK; 8003ec8: 2300 movs r3, #0 } 8003eca: 4618 mov r0, r3 8003ecc: 3708 adds r7, #8 8003ece: 46bd mov sp, r7 8003ed0: bd80 pop {r7, pc} 08003ed2 : * @brief Starts the TIM Base generation in interrupt mode. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) { 8003ed2: b480 push {r7} 8003ed4: b085 sub sp, #20 8003ed6: af00 add r7, sp, #0 8003ed8: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Enable the TIM Update interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); 8003eda: 687b ldr r3, [r7, #4] 8003edc: 681b ldr r3, [r3, #0] 8003ede: 68da ldr r2, [r3, #12] 8003ee0: 687b ldr r3, [r7, #4] 8003ee2: 681b ldr r3, [r3, #0] 8003ee4: f042 0201 orr.w r2, r2, #1 8003ee8: 60da str r2, [r3, #12] /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 8003eea: 687b ldr r3, [r7, #4] 8003eec: 681b ldr r3, [r3, #0] 8003eee: 689b ldr r3, [r3, #8] 8003ef0: f003 0307 and.w r3, r3, #7 8003ef4: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8003ef6: 68fb ldr r3, [r7, #12] 8003ef8: 2b06 cmp r3, #6 8003efa: d007 beq.n 8003f0c { __HAL_TIM_ENABLE(htim); 8003efc: 687b ldr r3, [r7, #4] 8003efe: 681b ldr r3, [r3, #0] 8003f00: 681a ldr r2, [r3, #0] 8003f02: 687b ldr r3, [r7, #4] 8003f04: 681b ldr r3, [r3, #0] 8003f06: f042 0201 orr.w r2, r2, #1 8003f0a: 601a str r2, [r3, #0] } /* Return function status */ return HAL_OK; 8003f0c: 2300 movs r3, #0 } 8003f0e: 4618 mov r0, r3 8003f10: 3714 adds r7, #20 8003f12: 46bd mov sp, r7 8003f14: bc80 pop {r7} 8003f16: 4770 bx lr 08003f18 : * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { 8003f18: b580 push {r7, lr} 8003f1a: b082 sub sp, #8 8003f1c: af00 add r7, sp, #0 8003f1e: 6078 str r0, [r7, #4] /* Capture compare 1 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) 8003f20: 687b ldr r3, [r7, #4] 8003f22: 681b ldr r3, [r3, #0] 8003f24: 691b ldr r3, [r3, #16] 8003f26: f003 0302 and.w r3, r3, #2 8003f2a: 2b02 cmp r3, #2 8003f2c: d122 bne.n 8003f74 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) 8003f2e: 687b ldr r3, [r7, #4] 8003f30: 681b ldr r3, [r3, #0] 8003f32: 68db ldr r3, [r3, #12] 8003f34: f003 0302 and.w r3, r3, #2 8003f38: 2b02 cmp r3, #2 8003f3a: d11b bne.n 8003f74 { { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); 8003f3c: 687b ldr r3, [r7, #4] 8003f3e: 681b ldr r3, [r3, #0] 8003f40: f06f 0202 mvn.w r2, #2 8003f44: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 8003f46: 687b ldr r3, [r7, #4] 8003f48: 2201 movs r2, #1 8003f4a: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 8003f4c: 687b ldr r3, [r7, #4] 8003f4e: 681b ldr r3, [r3, #0] 8003f50: 699b ldr r3, [r3, #24] 8003f52: f003 0303 and.w r3, r3, #3 8003f56: 2b00 cmp r3, #0 8003f58: d003 beq.n 8003f62 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8003f5a: 6878 ldr r0, [r7, #4] 8003f5c: f000 f8ed bl 800413a 8003f60: e005 b.n 8003f6e { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8003f62: 6878 ldr r0, [r7, #4] 8003f64: f000 f8e0 bl 8004128 HAL_TIM_PWM_PulseFinishedCallback(htim); 8003f68: 6878 ldr r0, [r7, #4] 8003f6a: f000 f8ef bl 800414c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8003f6e: 687b ldr r3, [r7, #4] 8003f70: 2200 movs r2, #0 8003f72: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) 8003f74: 687b ldr r3, [r7, #4] 8003f76: 681b ldr r3, [r3, #0] 8003f78: 691b ldr r3, [r3, #16] 8003f7a: f003 0304 and.w r3, r3, #4 8003f7e: 2b04 cmp r3, #4 8003f80: d122 bne.n 8003fc8 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) 8003f82: 687b ldr r3, [r7, #4] 8003f84: 681b ldr r3, [r3, #0] 8003f86: 68db ldr r3, [r3, #12] 8003f88: f003 0304 and.w r3, r3, #4 8003f8c: 2b04 cmp r3, #4 8003f8e: d11b bne.n 8003fc8 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); 8003f90: 687b ldr r3, [r7, #4] 8003f92: 681b ldr r3, [r3, #0] 8003f94: f06f 0204 mvn.w r2, #4 8003f98: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 8003f9a: 687b ldr r3, [r7, #4] 8003f9c: 2202 movs r2, #2 8003f9e: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 8003fa0: 687b ldr r3, [r7, #4] 8003fa2: 681b ldr r3, [r3, #0] 8003fa4: 699b ldr r3, [r3, #24] 8003fa6: f403 7340 and.w r3, r3, #768 ; 0x300 8003faa: 2b00 cmp r3, #0 8003fac: d003 beq.n 8003fb6 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8003fae: 6878 ldr r0, [r7, #4] 8003fb0: f000 f8c3 bl 800413a 8003fb4: e005 b.n 8003fc2 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8003fb6: 6878 ldr r0, [r7, #4] 8003fb8: f000 f8b6 bl 8004128 HAL_TIM_PWM_PulseFinishedCallback(htim); 8003fbc: 6878 ldr r0, [r7, #4] 8003fbe: f000 f8c5 bl 800414c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8003fc2: 687b ldr r3, [r7, #4] 8003fc4: 2200 movs r2, #0 8003fc6: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) 8003fc8: 687b ldr r3, [r7, #4] 8003fca: 681b ldr r3, [r3, #0] 8003fcc: 691b ldr r3, [r3, #16] 8003fce: f003 0308 and.w r3, r3, #8 8003fd2: 2b08 cmp r3, #8 8003fd4: d122 bne.n 800401c { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) 8003fd6: 687b ldr r3, [r7, #4] 8003fd8: 681b ldr r3, [r3, #0] 8003fda: 68db ldr r3, [r3, #12] 8003fdc: f003 0308 and.w r3, r3, #8 8003fe0: 2b08 cmp r3, #8 8003fe2: d11b bne.n 800401c { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); 8003fe4: 687b ldr r3, [r7, #4] 8003fe6: 681b ldr r3, [r3, #0] 8003fe8: f06f 0208 mvn.w r2, #8 8003fec: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 8003fee: 687b ldr r3, [r7, #4] 8003ff0: 2204 movs r2, #4 8003ff2: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 8003ff4: 687b ldr r3, [r7, #4] 8003ff6: 681b ldr r3, [r3, #0] 8003ff8: 69db ldr r3, [r3, #28] 8003ffa: f003 0303 and.w r3, r3, #3 8003ffe: 2b00 cmp r3, #0 8004000: d003 beq.n 800400a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8004002: 6878 ldr r0, [r7, #4] 8004004: f000 f899 bl 800413a 8004008: e005 b.n 8004016 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800400a: 6878 ldr r0, [r7, #4] 800400c: f000 f88c bl 8004128 HAL_TIM_PWM_PulseFinishedCallback(htim); 8004010: 6878 ldr r0, [r7, #4] 8004012: f000 f89b bl 800414c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8004016: 687b ldr r3, [r7, #4] 8004018: 2200 movs r2, #0 800401a: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) 800401c: 687b ldr r3, [r7, #4] 800401e: 681b ldr r3, [r3, #0] 8004020: 691b ldr r3, [r3, #16] 8004022: f003 0310 and.w r3, r3, #16 8004026: 2b10 cmp r3, #16 8004028: d122 bne.n 8004070 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) 800402a: 687b ldr r3, [r7, #4] 800402c: 681b ldr r3, [r3, #0] 800402e: 68db ldr r3, [r3, #12] 8004030: f003 0310 and.w r3, r3, #16 8004034: 2b10 cmp r3, #16 8004036: d11b bne.n 8004070 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); 8004038: 687b ldr r3, [r7, #4] 800403a: 681b ldr r3, [r3, #0] 800403c: f06f 0210 mvn.w r2, #16 8004040: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 8004042: 687b ldr r3, [r7, #4] 8004044: 2208 movs r2, #8 8004046: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 8004048: 687b ldr r3, [r7, #4] 800404a: 681b ldr r3, [r3, #0] 800404c: 69db ldr r3, [r3, #28] 800404e: f403 7340 and.w r3, r3, #768 ; 0x300 8004052: 2b00 cmp r3, #0 8004054: d003 beq.n 800405e { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8004056: 6878 ldr r0, [r7, #4] 8004058: f000 f86f bl 800413a 800405c: e005 b.n 800406a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800405e: 6878 ldr r0, [r7, #4] 8004060: f000 f862 bl 8004128 HAL_TIM_PWM_PulseFinishedCallback(htim); 8004064: 6878 ldr r0, [r7, #4] 8004066: f000 f871 bl 800414c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800406a: 687b ldr r3, [r7, #4] 800406c: 2200 movs r2, #0 800406e: 771a strb r2, [r3, #28] } } /* TIM Update event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) 8004070: 687b ldr r3, [r7, #4] 8004072: 681b ldr r3, [r3, #0] 8004074: 691b ldr r3, [r3, #16] 8004076: f003 0301 and.w r3, r3, #1 800407a: 2b01 cmp r3, #1 800407c: d10e bne.n 800409c { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) 800407e: 687b ldr r3, [r7, #4] 8004080: 681b ldr r3, [r3, #0] 8004082: 68db ldr r3, [r3, #12] 8004084: f003 0301 and.w r3, r3, #1 8004088: 2b01 cmp r3, #1 800408a: d107 bne.n 800409c { __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); 800408c: 687b ldr r3, [r7, #4] 800408e: 681b ldr r3, [r3, #0] 8004090: f06f 0201 mvn.w r2, #1 8004094: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); 8004096: 6878 ldr r0, [r7, #4] 8004098: f001 fae0 bl 800565c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) 800409c: 687b ldr r3, [r7, #4] 800409e: 681b ldr r3, [r3, #0] 80040a0: 691b ldr r3, [r3, #16] 80040a2: f003 0380 and.w r3, r3, #128 ; 0x80 80040a6: 2b80 cmp r3, #128 ; 0x80 80040a8: d10e bne.n 80040c8 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) 80040aa: 687b ldr r3, [r7, #4] 80040ac: 681b ldr r3, [r3, #0] 80040ae: 68db ldr r3, [r3, #12] 80040b0: f003 0380 and.w r3, r3, #128 ; 0x80 80040b4: 2b80 cmp r3, #128 ; 0x80 80040b6: d107 bne.n 80040c8 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); 80040b8: 687b ldr r3, [r7, #4] 80040ba: 681b ldr r3, [r3, #0] 80040bc: f06f 0280 mvn.w r2, #128 ; 0x80 80040c0: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); 80040c2: 6878 ldr r0, [r7, #4] 80040c4: f000 f921 bl 800430a #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) 80040c8: 687b ldr r3, [r7, #4] 80040ca: 681b ldr r3, [r3, #0] 80040cc: 691b ldr r3, [r3, #16] 80040ce: f003 0340 and.w r3, r3, #64 ; 0x40 80040d2: 2b40 cmp r3, #64 ; 0x40 80040d4: d10e bne.n 80040f4 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) 80040d6: 687b ldr r3, [r7, #4] 80040d8: 681b ldr r3, [r3, #0] 80040da: 68db ldr r3, [r3, #12] 80040dc: f003 0340 and.w r3, r3, #64 ; 0x40 80040e0: 2b40 cmp r3, #64 ; 0x40 80040e2: d107 bne.n 80040f4 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); 80040e4: 687b ldr r3, [r7, #4] 80040e6: 681b ldr r3, [r3, #0] 80040e8: f06f 0240 mvn.w r2, #64 ; 0x40 80040ec: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); 80040ee: 6878 ldr r0, [r7, #4] 80040f0: f000 f835 bl 800415e #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) 80040f4: 687b ldr r3, [r7, #4] 80040f6: 681b ldr r3, [r3, #0] 80040f8: 691b ldr r3, [r3, #16] 80040fa: f003 0320 and.w r3, r3, #32 80040fe: 2b20 cmp r3, #32 8004100: d10e bne.n 8004120 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET) 8004102: 687b ldr r3, [r7, #4] 8004104: 681b ldr r3, [r3, #0] 8004106: 68db ldr r3, [r3, #12] 8004108: f003 0320 and.w r3, r3, #32 800410c: 2b20 cmp r3, #32 800410e: d107 bne.n 8004120 { __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); 8004110: 687b ldr r3, [r7, #4] 8004112: 681b ldr r3, [r3, #0] 8004114: f06f 0220 mvn.w r2, #32 8004118: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); 800411a: 6878 ldr r0, [r7, #4] 800411c: f000 f8ec bl 80042f8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } 8004120: bf00 nop 8004122: 3708 adds r7, #8 8004124: 46bd mov sp, r7 8004126: bd80 pop {r7, pc} 08004128 : * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { 8004128: b480 push {r7} 800412a: b083 sub sp, #12 800412c: af00 add r7, sp, #0 800412e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } 8004130: bf00 nop 8004132: 370c adds r7, #12 8004134: 46bd mov sp, r7 8004136: bc80 pop {r7} 8004138: 4770 bx lr 0800413a : * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { 800413a: b480 push {r7} 800413c: b083 sub sp, #12 800413e: af00 add r7, sp, #0 8004140: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } 8004142: bf00 nop 8004144: 370c adds r7, #12 8004146: 46bd mov sp, r7 8004148: bc80 pop {r7} 800414a: 4770 bx lr 0800414c : * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { 800414c: b480 push {r7} 800414e: b083 sub sp, #12 8004150: af00 add r7, sp, #0 8004152: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } 8004154: bf00 nop 8004156: 370c adds r7, #12 8004158: 46bd mov sp, r7 800415a: bc80 pop {r7} 800415c: 4770 bx lr 0800415e : * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { 800415e: b480 push {r7} 8004160: b083 sub sp, #12 8004162: af00 add r7, sp, #0 8004164: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } 8004166: bf00 nop 8004168: 370c adds r7, #12 800416a: 46bd mov sp, r7 800416c: bc80 pop {r7} 800416e: 4770 bx lr 08004170 : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) { 8004170: b480 push {r7} 8004172: b085 sub sp, #20 8004174: af00 add r7, sp, #0 8004176: 6078 str r0, [r7, #4] 8004178: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 800417a: 687b ldr r3, [r7, #4] 800417c: 681b ldr r3, [r3, #0] 800417e: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 8004180: 687b ldr r3, [r7, #4] 8004182: 4a35 ldr r2, [pc, #212] ; (8004258 ) 8004184: 4293 cmp r3, r2 8004186: d00b beq.n 80041a0 8004188: 687b ldr r3, [r7, #4] 800418a: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 800418e: d007 beq.n 80041a0 8004190: 687b ldr r3, [r7, #4] 8004192: 4a32 ldr r2, [pc, #200] ; (800425c ) 8004194: 4293 cmp r3, r2 8004196: d003 beq.n 80041a0 8004198: 687b ldr r3, [r7, #4] 800419a: 4a31 ldr r2, [pc, #196] ; (8004260 ) 800419c: 4293 cmp r3, r2 800419e: d108 bne.n 80041b2 { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 80041a0: 68fb ldr r3, [r7, #12] 80041a2: f023 0370 bic.w r3, r3, #112 ; 0x70 80041a6: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 80041a8: 683b ldr r3, [r7, #0] 80041aa: 685b ldr r3, [r3, #4] 80041ac: 68fa ldr r2, [r7, #12] 80041ae: 4313 orrs r3, r2 80041b0: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 80041b2: 687b ldr r3, [r7, #4] 80041b4: 4a28 ldr r2, [pc, #160] ; (8004258 ) 80041b6: 4293 cmp r3, r2 80041b8: d017 beq.n 80041ea 80041ba: 687b ldr r3, [r7, #4] 80041bc: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 80041c0: d013 beq.n 80041ea 80041c2: 687b ldr r3, [r7, #4] 80041c4: 4a25 ldr r2, [pc, #148] ; (800425c ) 80041c6: 4293 cmp r3, r2 80041c8: d00f beq.n 80041ea 80041ca: 687b ldr r3, [r7, #4] 80041cc: 4a24 ldr r2, [pc, #144] ; (8004260 ) 80041ce: 4293 cmp r3, r2 80041d0: d00b beq.n 80041ea 80041d2: 687b ldr r3, [r7, #4] 80041d4: 4a23 ldr r2, [pc, #140] ; (8004264 ) 80041d6: 4293 cmp r3, r2 80041d8: d007 beq.n 80041ea 80041da: 687b ldr r3, [r7, #4] 80041dc: 4a22 ldr r2, [pc, #136] ; (8004268 ) 80041de: 4293 cmp r3, r2 80041e0: d003 beq.n 80041ea 80041e2: 687b ldr r3, [r7, #4] 80041e4: 4a21 ldr r2, [pc, #132] ; (800426c ) 80041e6: 4293 cmp r3, r2 80041e8: d108 bne.n 80041fc { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 80041ea: 68fb ldr r3, [r7, #12] 80041ec: f423 7340 bic.w r3, r3, #768 ; 0x300 80041f0: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 80041f2: 683b ldr r3, [r7, #0] 80041f4: 68db ldr r3, [r3, #12] 80041f6: 68fa ldr r2, [r7, #12] 80041f8: 4313 orrs r3, r2 80041fa: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 80041fc: 68fb ldr r3, [r7, #12] 80041fe: f023 0280 bic.w r2, r3, #128 ; 0x80 8004202: 683b ldr r3, [r7, #0] 8004204: 695b ldr r3, [r3, #20] 8004206: 4313 orrs r3, r2 8004208: 60fb str r3, [r7, #12] TIMx->CR1 = tmpcr1; 800420a: 687b ldr r3, [r7, #4] 800420c: 68fa ldr r2, [r7, #12] 800420e: 601a str r2, [r3, #0] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 8004210: 683b ldr r3, [r7, #0] 8004212: 689a ldr r2, [r3, #8] 8004214: 687b ldr r3, [r7, #4] 8004216: 62da str r2, [r3, #44] ; 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 8004218: 683b ldr r3, [r7, #0] 800421a: 681a ldr r2, [r3, #0] 800421c: 687b ldr r3, [r7, #4] 800421e: 629a str r2, [r3, #40] ; 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 8004220: 687b ldr r3, [r7, #4] 8004222: 4a0d ldr r2, [pc, #52] ; (8004258 ) 8004224: 4293 cmp r3, r2 8004226: d00b beq.n 8004240 8004228: 687b ldr r3, [r7, #4] 800422a: 4a0e ldr r2, [pc, #56] ; (8004264 ) 800422c: 4293 cmp r3, r2 800422e: d007 beq.n 8004240 8004230: 687b ldr r3, [r7, #4] 8004232: 4a0d ldr r2, [pc, #52] ; (8004268 ) 8004234: 4293 cmp r3, r2 8004236: d003 beq.n 8004240 8004238: 687b ldr r3, [r7, #4] 800423a: 4a0c ldr r2, [pc, #48] ; (800426c ) 800423c: 4293 cmp r3, r2 800423e: d103 bne.n 8004248 { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 8004240: 683b ldr r3, [r7, #0] 8004242: 691a ldr r2, [r3, #16] 8004244: 687b ldr r3, [r7, #4] 8004246: 631a str r2, [r3, #48] ; 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 8004248: 687b ldr r3, [r7, #4] 800424a: 2201 movs r2, #1 800424c: 615a str r2, [r3, #20] } 800424e: bf00 nop 8004250: 3714 adds r7, #20 8004252: 46bd mov sp, r7 8004254: bc80 pop {r7} 8004256: 4770 bx lr 8004258: 40012c00 .word 0x40012c00 800425c: 40000400 .word 0x40000400 8004260: 40000800 .word 0x40000800 8004264: 40014000 .word 0x40014000 8004268: 40014400 .word 0x40014400 800426c: 40014800 .word 0x40014800 08004270 : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig) { 8004270: b480 push {r7} 8004272: b085 sub sp, #20 8004274: af00 add r7, sp, #0 8004276: 6078 str r0, [r7, #4] 8004278: 6039 str r1, [r7, #0] assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 800427a: 687b ldr r3, [r7, #4] 800427c: f893 303c ldrb.w r3, [r3, #60] ; 0x3c 8004280: 2b01 cmp r3, #1 8004282: d101 bne.n 8004288 8004284: 2302 movs r3, #2 8004286: e032 b.n 80042ee 8004288: 687b ldr r3, [r7, #4] 800428a: 2201 movs r2, #1 800428c: f883 203c strb.w r2, [r3, #60] ; 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 8004290: 687b ldr r3, [r7, #4] 8004292: 2202 movs r2, #2 8004294: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 8004298: 687b ldr r3, [r7, #4] 800429a: 681b ldr r3, [r3, #0] 800429c: 685b ldr r3, [r3, #4] 800429e: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 80042a0: 687b ldr r3, [r7, #4] 80042a2: 681b ldr r3, [r3, #0] 80042a4: 689b ldr r3, [r3, #8] 80042a6: 60bb str r3, [r7, #8] /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 80042a8: 68fb ldr r3, [r7, #12] 80042aa: f023 0370 bic.w r3, r3, #112 ; 0x70 80042ae: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 80042b0: 683b ldr r3, [r7, #0] 80042b2: 681b ldr r3, [r3, #0] 80042b4: 68fa ldr r2, [r7, #12] 80042b6: 4313 orrs r3, r2 80042b8: 60fb str r3, [r7, #12] /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 80042ba: 68bb ldr r3, [r7, #8] 80042bc: f023 0380 bic.w r3, r3, #128 ; 0x80 80042c0: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 80042c2: 683b ldr r3, [r7, #0] 80042c4: 685b ldr r3, [r3, #4] 80042c6: 68ba ldr r2, [r7, #8] 80042c8: 4313 orrs r3, r2 80042ca: 60bb str r3, [r7, #8] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 80042cc: 687b ldr r3, [r7, #4] 80042ce: 681b ldr r3, [r3, #0] 80042d0: 68fa ldr r2, [r7, #12] 80042d2: 605a str r2, [r3, #4] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 80042d4: 687b ldr r3, [r7, #4] 80042d6: 681b ldr r3, [r3, #0] 80042d8: 68ba ldr r2, [r7, #8] 80042da: 609a str r2, [r3, #8] /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 80042dc: 687b ldr r3, [r7, #4] 80042de: 2201 movs r2, #1 80042e0: f883 203d strb.w r2, [r3, #61] ; 0x3d __HAL_UNLOCK(htim); 80042e4: 687b ldr r3, [r7, #4] 80042e6: 2200 movs r2, #0 80042e8: f883 203c strb.w r2, [r3, #60] ; 0x3c return HAL_OK; 80042ec: 2300 movs r3, #0 } 80042ee: 4618 mov r0, r3 80042f0: 3714 adds r7, #20 80042f2: 46bd mov sp, r7 80042f4: bc80 pop {r7} 80042f6: 4770 bx lr 080042f8 : * @brief Hall commutation changed callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { 80042f8: b480 push {r7} 80042fa: b083 sub sp, #12 80042fc: af00 add r7, sp, #0 80042fe: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } 8004300: bf00 nop 8004302: 370c adds r7, #12 8004304: 46bd mov sp, r7 8004306: bc80 pop {r7} 8004308: 4770 bx lr 0800430a : * @brief Hall Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { 800430a: b480 push {r7} 800430c: b083 sub sp, #12 800430e: af00 add r7, sp, #0 8004310: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } 8004312: bf00 nop 8004314: 370c adds r7, #12 8004316: 46bd mov sp, r7 8004318: bc80 pop {r7} 800431a: 4770 bx lr 0800431c : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 800431c: b580 push {r7, lr} 800431e: b082 sub sp, #8 8004320: af00 add r7, sp, #0 8004322: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 8004324: 687b ldr r3, [r7, #4] 8004326: 2b00 cmp r3, #0 8004328: d101 bne.n 800432e { return HAL_ERROR; 800432a: 2301 movs r3, #1 800432c: e03f b.n 80043ae assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); #if defined(USART_CR1_OVER8) assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); #endif /* USART_CR1_OVER8 */ if (huart->gState == HAL_UART_STATE_RESET) 800432e: 687b ldr r3, [r7, #4] 8004330: f893 3039 ldrb.w r3, [r3, #57] ; 0x39 8004334: b2db uxtb r3, r3 8004336: 2b00 cmp r3, #0 8004338: d106 bne.n 8004348 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 800433a: 687b ldr r3, [r7, #4] 800433c: 2200 movs r2, #0 800433e: f883 2038 strb.w r2, [r3, #56] ; 0x38 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 8004342: 6878 ldr r0, [r7, #4] 8004344: f001 faee bl 8005924 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 8004348: 687b ldr r3, [r7, #4] 800434a: 2224 movs r2, #36 ; 0x24 800434c: f883 2039 strb.w r2, [r3, #57] ; 0x39 /* Disable the peripheral */ __HAL_UART_DISABLE(huart); 8004350: 687b ldr r3, [r7, #4] 8004352: 681b ldr r3, [r3, #0] 8004354: 68da ldr r2, [r3, #12] 8004356: 687b ldr r3, [r7, #4] 8004358: 681b ldr r3, [r3, #0] 800435a: f422 5200 bic.w r2, r2, #8192 ; 0x2000 800435e: 60da str r2, [r3, #12] /* Set the UART Communication parameters */ UART_SetConfig(huart); 8004360: 6878 ldr r0, [r7, #4] 8004362: f000 fd63 bl 8004e2c /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 8004366: 687b ldr r3, [r7, #4] 8004368: 681b ldr r3, [r3, #0] 800436a: 691a ldr r2, [r3, #16] 800436c: 687b ldr r3, [r7, #4] 800436e: 681b ldr r3, [r3, #0] 8004370: f422 4290 bic.w r2, r2, #18432 ; 0x4800 8004374: 611a str r2, [r3, #16] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 8004376: 687b ldr r3, [r7, #4] 8004378: 681b ldr r3, [r3, #0] 800437a: 695a ldr r2, [r3, #20] 800437c: 687b ldr r3, [r7, #4] 800437e: 681b ldr r3, [r3, #0] 8004380: f022 022a bic.w r2, r2, #42 ; 0x2a 8004384: 615a str r2, [r3, #20] /* Enable the peripheral */ __HAL_UART_ENABLE(huart); 8004386: 687b ldr r3, [r7, #4] 8004388: 681b ldr r3, [r3, #0] 800438a: 68da ldr r2, [r3, #12] 800438c: 687b ldr r3, [r7, #4] 800438e: 681b ldr r3, [r3, #0] 8004390: f442 5200 orr.w r2, r2, #8192 ; 0x2000 8004394: 60da str r2, [r3, #12] /* Initialize the UART state */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8004396: 687b ldr r3, [r7, #4] 8004398: 2200 movs r2, #0 800439a: 63da str r2, [r3, #60] ; 0x3c huart->gState = HAL_UART_STATE_READY; 800439c: 687b ldr r3, [r7, #4] 800439e: 2220 movs r2, #32 80043a0: f883 2039 strb.w r2, [r3, #57] ; 0x39 huart->RxState = HAL_UART_STATE_READY; 80043a4: 687b ldr r3, [r7, #4] 80043a6: 2220 movs r2, #32 80043a8: f883 203a strb.w r2, [r3, #58] ; 0x3a return HAL_OK; 80043ac: 2300 movs r3, #0 } 80043ae: 4618 mov r0, r3 80043b0: 3708 adds r7, #8 80043b2: 46bd mov sp, r7 80043b4: bd80 pop {r7, pc} 080043b6 : * @param Size Amount of data elements (u8 or u16) to be sent * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) { 80043b6: b580 push {r7, lr} 80043b8: b088 sub sp, #32 80043ba: af02 add r7, sp, #8 80043bc: 60f8 str r0, [r7, #12] 80043be: 60b9 str r1, [r7, #8] 80043c0: 603b str r3, [r7, #0] 80043c2: 4613 mov r3, r2 80043c4: 80fb strh r3, [r7, #6] uint16_t *tmp; uint32_t tickstart = 0U; 80043c6: 2300 movs r3, #0 80043c8: 617b str r3, [r7, #20] /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 80043ca: 68fb ldr r3, [r7, #12] 80043cc: f893 3039 ldrb.w r3, [r3, #57] ; 0x39 80043d0: b2db uxtb r3, r3 80043d2: 2b20 cmp r3, #32 80043d4: f040 8083 bne.w 80044de { if ((pData == NULL) || (Size == 0U)) 80043d8: 68bb ldr r3, [r7, #8] 80043da: 2b00 cmp r3, #0 80043dc: d002 beq.n 80043e4 80043de: 88fb ldrh r3, [r7, #6] 80043e0: 2b00 cmp r3, #0 80043e2: d101 bne.n 80043e8 { return HAL_ERROR; 80043e4: 2301 movs r3, #1 80043e6: e07b b.n 80044e0 } /* Process Locked */ __HAL_LOCK(huart); 80043e8: 68fb ldr r3, [r7, #12] 80043ea: f893 3038 ldrb.w r3, [r3, #56] ; 0x38 80043ee: 2b01 cmp r3, #1 80043f0: d101 bne.n 80043f6 80043f2: 2302 movs r3, #2 80043f4: e074 b.n 80044e0 80043f6: 68fb ldr r3, [r7, #12] 80043f8: 2201 movs r2, #1 80043fa: f883 2038 strb.w r2, [r3, #56] ; 0x38 huart->ErrorCode = HAL_UART_ERROR_NONE; 80043fe: 68fb ldr r3, [r7, #12] 8004400: 2200 movs r2, #0 8004402: 63da str r2, [r3, #60] ; 0x3c huart->gState = HAL_UART_STATE_BUSY_TX; 8004404: 68fb ldr r3, [r7, #12] 8004406: 2221 movs r2, #33 ; 0x21 8004408: f883 2039 strb.w r2, [r3, #57] ; 0x39 /* Init tickstart for timeout managment */ tickstart = HAL_GetTick(); 800440c: f7fd fc2e bl 8001c6c 8004410: 6178 str r0, [r7, #20] huart->TxXferSize = Size; 8004412: 68fb ldr r3, [r7, #12] 8004414: 88fa ldrh r2, [r7, #6] 8004416: 849a strh r2, [r3, #36] ; 0x24 huart->TxXferCount = Size; 8004418: 68fb ldr r3, [r7, #12] 800441a: 88fa ldrh r2, [r7, #6] 800441c: 84da strh r2, [r3, #38] ; 0x26 while (huart->TxXferCount > 0U) 800441e: e042 b.n 80044a6 { huart->TxXferCount--; 8004420: 68fb ldr r3, [r7, #12] 8004422: 8cdb ldrh r3, [r3, #38] ; 0x26 8004424: b29b uxth r3, r3 8004426: 3b01 subs r3, #1 8004428: b29a uxth r2, r3 800442a: 68fb ldr r3, [r7, #12] 800442c: 84da strh r2, [r3, #38] ; 0x26 if (huart->Init.WordLength == UART_WORDLENGTH_9B) 800442e: 68fb ldr r3, [r7, #12] 8004430: 689b ldr r3, [r3, #8] 8004432: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8004436: d122 bne.n 800447e { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) 8004438: 683b ldr r3, [r7, #0] 800443a: 9300 str r3, [sp, #0] 800443c: 697b ldr r3, [r7, #20] 800443e: 2200 movs r2, #0 8004440: 2180 movs r1, #128 ; 0x80 8004442: 68f8 ldr r0, [r7, #12] 8004444: f000 fb73 bl 8004b2e 8004448: 4603 mov r3, r0 800444a: 2b00 cmp r3, #0 800444c: d001 beq.n 8004452 { return HAL_TIMEOUT; 800444e: 2303 movs r3, #3 8004450: e046 b.n 80044e0 } tmp = (uint16_t *) pData; 8004452: 68bb ldr r3, [r7, #8] 8004454: 613b str r3, [r7, #16] huart->Instance->DR = (*tmp & (uint16_t)0x01FF); 8004456: 693b ldr r3, [r7, #16] 8004458: 881b ldrh r3, [r3, #0] 800445a: 461a mov r2, r3 800445c: 68fb ldr r3, [r7, #12] 800445e: 681b ldr r3, [r3, #0] 8004460: f3c2 0208 ubfx r2, r2, #0, #9 8004464: 605a str r2, [r3, #4] if (huart->Init.Parity == UART_PARITY_NONE) 8004466: 68fb ldr r3, [r7, #12] 8004468: 691b ldr r3, [r3, #16] 800446a: 2b00 cmp r3, #0 800446c: d103 bne.n 8004476 { pData += 2U; 800446e: 68bb ldr r3, [r7, #8] 8004470: 3302 adds r3, #2 8004472: 60bb str r3, [r7, #8] 8004474: e017 b.n 80044a6 } else { pData += 1U; 8004476: 68bb ldr r3, [r7, #8] 8004478: 3301 adds r3, #1 800447a: 60bb str r3, [r7, #8] 800447c: e013 b.n 80044a6 } } else { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) 800447e: 683b ldr r3, [r7, #0] 8004480: 9300 str r3, [sp, #0] 8004482: 697b ldr r3, [r7, #20] 8004484: 2200 movs r2, #0 8004486: 2180 movs r1, #128 ; 0x80 8004488: 68f8 ldr r0, [r7, #12] 800448a: f000 fb50 bl 8004b2e 800448e: 4603 mov r3, r0 8004490: 2b00 cmp r3, #0 8004492: d001 beq.n 8004498 { return HAL_TIMEOUT; 8004494: 2303 movs r3, #3 8004496: e023 b.n 80044e0 } huart->Instance->DR = (*pData++ & (uint8_t)0xFF); 8004498: 68bb ldr r3, [r7, #8] 800449a: 1c5a adds r2, r3, #1 800449c: 60ba str r2, [r7, #8] 800449e: 781a ldrb r2, [r3, #0] 80044a0: 68fb ldr r3, [r7, #12] 80044a2: 681b ldr r3, [r3, #0] 80044a4: 605a str r2, [r3, #4] while (huart->TxXferCount > 0U) 80044a6: 68fb ldr r3, [r7, #12] 80044a8: 8cdb ldrh r3, [r3, #38] ; 0x26 80044aa: b29b uxth r3, r3 80044ac: 2b00 cmp r3, #0 80044ae: d1b7 bne.n 8004420 } } if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) 80044b0: 683b ldr r3, [r7, #0] 80044b2: 9300 str r3, [sp, #0] 80044b4: 697b ldr r3, [r7, #20] 80044b6: 2200 movs r2, #0 80044b8: 2140 movs r1, #64 ; 0x40 80044ba: 68f8 ldr r0, [r7, #12] 80044bc: f000 fb37 bl 8004b2e 80044c0: 4603 mov r3, r0 80044c2: 2b00 cmp r3, #0 80044c4: d001 beq.n 80044ca { return HAL_TIMEOUT; 80044c6: 2303 movs r3, #3 80044c8: e00a b.n 80044e0 } /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 80044ca: 68fb ldr r3, [r7, #12] 80044cc: 2220 movs r2, #32 80044ce: f883 2039 strb.w r2, [r3, #57] ; 0x39 /* Process Unlocked */ __HAL_UNLOCK(huart); 80044d2: 68fb ldr r3, [r7, #12] 80044d4: 2200 movs r2, #0 80044d6: f883 2038 strb.w r2, [r3, #56] ; 0x38 return HAL_OK; 80044da: 2300 movs r3, #0 80044dc: e000 b.n 80044e0 } else { return HAL_BUSY; 80044de: 2302 movs r3, #2 } } 80044e0: 4618 mov r0, r3 80044e2: 3718 adds r7, #24 80044e4: 46bd mov sp, r7 80044e6: bd80 pop {r7, pc} 080044e8 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 80044e8: b480 push {r7} 80044ea: b085 sub sp, #20 80044ec: af00 add r7, sp, #0 80044ee: 60f8 str r0, [r7, #12] 80044f0: 60b9 str r1, [r7, #8] 80044f2: 4613 mov r3, r2 80044f4: 80fb strh r3, [r7, #6] /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) 80044f6: 68fb ldr r3, [r7, #12] 80044f8: f893 303a ldrb.w r3, [r3, #58] ; 0x3a 80044fc: b2db uxtb r3, r3 80044fe: 2b20 cmp r3, #32 8004500: d140 bne.n 8004584 { if ((pData == NULL) || (Size == 0U)) 8004502: 68bb ldr r3, [r7, #8] 8004504: 2b00 cmp r3, #0 8004506: d002 beq.n 800450e 8004508: 88fb ldrh r3, [r7, #6] 800450a: 2b00 cmp r3, #0 800450c: d101 bne.n 8004512 { return HAL_ERROR; 800450e: 2301 movs r3, #1 8004510: e039 b.n 8004586 } /* Process Locked */ __HAL_LOCK(huart); 8004512: 68fb ldr r3, [r7, #12] 8004514: f893 3038 ldrb.w r3, [r3, #56] ; 0x38 8004518: 2b01 cmp r3, #1 800451a: d101 bne.n 8004520 800451c: 2302 movs r3, #2 800451e: e032 b.n 8004586 8004520: 68fb ldr r3, [r7, #12] 8004522: 2201 movs r2, #1 8004524: f883 2038 strb.w r2, [r3, #56] ; 0x38 huart->pRxBuffPtr = pData; 8004528: 68fb ldr r3, [r7, #12] 800452a: 68ba ldr r2, [r7, #8] 800452c: 629a str r2, [r3, #40] ; 0x28 huart->RxXferSize = Size; 800452e: 68fb ldr r3, [r7, #12] 8004530: 88fa ldrh r2, [r7, #6] 8004532: 859a strh r2, [r3, #44] ; 0x2c huart->RxXferCount = Size; 8004534: 68fb ldr r3, [r7, #12] 8004536: 88fa ldrh r2, [r7, #6] 8004538: 85da strh r2, [r3, #46] ; 0x2e huart->ErrorCode = HAL_UART_ERROR_NONE; 800453a: 68fb ldr r3, [r7, #12] 800453c: 2200 movs r2, #0 800453e: 63da str r2, [r3, #60] ; 0x3c huart->RxState = HAL_UART_STATE_BUSY_RX; 8004540: 68fb ldr r3, [r7, #12] 8004542: 2222 movs r2, #34 ; 0x22 8004544: f883 203a strb.w r2, [r3, #58] ; 0x3a /* Process Unlocked */ __HAL_UNLOCK(huart); 8004548: 68fb ldr r3, [r7, #12] 800454a: 2200 movs r2, #0 800454c: f883 2038 strb.w r2, [r3, #56] ; 0x38 /* Enable the UART Parity Error Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_PE); 8004550: 68fb ldr r3, [r7, #12] 8004552: 681b ldr r3, [r3, #0] 8004554: 68da ldr r2, [r3, #12] 8004556: 68fb ldr r3, [r7, #12] 8004558: 681b ldr r3, [r3, #0] 800455a: f442 7280 orr.w r2, r2, #256 ; 0x100 800455e: 60da str r2, [r3, #12] /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_ENABLE_IT(huart, UART_IT_ERR); 8004560: 68fb ldr r3, [r7, #12] 8004562: 681b ldr r3, [r3, #0] 8004564: 695a ldr r2, [r3, #20] 8004566: 68fb ldr r3, [r7, #12] 8004568: 681b ldr r3, [r3, #0] 800456a: f042 0201 orr.w r2, r2, #1 800456e: 615a str r2, [r3, #20] /* Enable the UART Data Register not empty Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE); 8004570: 68fb ldr r3, [r7, #12] 8004572: 681b ldr r3, [r3, #0] 8004574: 68da ldr r2, [r3, #12] 8004576: 68fb ldr r3, [r7, #12] 8004578: 681b ldr r3, [r3, #0] 800457a: f042 0220 orr.w r2, r2, #32 800457e: 60da str r2, [r3, #12] return HAL_OK; 8004580: 2300 movs r3, #0 8004582: e000 b.n 8004586 } else { return HAL_BUSY; 8004584: 2302 movs r3, #2 } } 8004586: 4618 mov r0, r3 8004588: 3714 adds r7, #20 800458a: 46bd mov sp, r7 800458c: bc80 pop {r7} 800458e: 4770 bx lr 08004590 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8004590: b580 push {r7, lr} 8004592: b086 sub sp, #24 8004594: af00 add r7, sp, #0 8004596: 60f8 str r0, [r7, #12] 8004598: 60b9 str r1, [r7, #8] 800459a: 4613 mov r3, r2 800459c: 80fb strh r3, [r7, #6] uint32_t *tmp; /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 800459e: 68fb ldr r3, [r7, #12] 80045a0: f893 3039 ldrb.w r3, [r3, #57] ; 0x39 80045a4: b2db uxtb r3, r3 80045a6: 2b20 cmp r3, #32 80045a8: d153 bne.n 8004652 { if ((pData == NULL) || (Size == 0U)) 80045aa: 68bb ldr r3, [r7, #8] 80045ac: 2b00 cmp r3, #0 80045ae: d002 beq.n 80045b6 80045b0: 88fb ldrh r3, [r7, #6] 80045b2: 2b00 cmp r3, #0 80045b4: d101 bne.n 80045ba { return HAL_ERROR; 80045b6: 2301 movs r3, #1 80045b8: e04c b.n 8004654 } /* Process Locked */ __HAL_LOCK(huart); 80045ba: 68fb ldr r3, [r7, #12] 80045bc: f893 3038 ldrb.w r3, [r3, #56] ; 0x38 80045c0: 2b01 cmp r3, #1 80045c2: d101 bne.n 80045c8 80045c4: 2302 movs r3, #2 80045c6: e045 b.n 8004654 80045c8: 68fb ldr r3, [r7, #12] 80045ca: 2201 movs r2, #1 80045cc: f883 2038 strb.w r2, [r3, #56] ; 0x38 huart->pTxBuffPtr = pData; 80045d0: 68ba ldr r2, [r7, #8] 80045d2: 68fb ldr r3, [r7, #12] 80045d4: 621a str r2, [r3, #32] huart->TxXferSize = Size; 80045d6: 68fb ldr r3, [r7, #12] 80045d8: 88fa ldrh r2, [r7, #6] 80045da: 849a strh r2, [r3, #36] ; 0x24 huart->TxXferCount = Size; 80045dc: 68fb ldr r3, [r7, #12] 80045de: 88fa ldrh r2, [r7, #6] 80045e0: 84da strh r2, [r3, #38] ; 0x26 huart->ErrorCode = HAL_UART_ERROR_NONE; 80045e2: 68fb ldr r3, [r7, #12] 80045e4: 2200 movs r2, #0 80045e6: 63da str r2, [r3, #60] ; 0x3c huart->gState = HAL_UART_STATE_BUSY_TX; 80045e8: 68fb ldr r3, [r7, #12] 80045ea: 2221 movs r2, #33 ; 0x21 80045ec: f883 2039 strb.w r2, [r3, #57] ; 0x39 /* Set the UART DMA transfer complete callback */ huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; 80045f0: 68fb ldr r3, [r7, #12] 80045f2: 6b1b ldr r3, [r3, #48] ; 0x30 80045f4: 4a19 ldr r2, [pc, #100] ; (800465c ) 80045f6: 629a str r2, [r3, #40] ; 0x28 /* Set the UART DMA Half transfer complete callback */ huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; 80045f8: 68fb ldr r3, [r7, #12] 80045fa: 6b1b ldr r3, [r3, #48] ; 0x30 80045fc: 4a18 ldr r2, [pc, #96] ; (8004660 ) 80045fe: 62da str r2, [r3, #44] ; 0x2c /* Set the DMA error callback */ huart->hdmatx->XferErrorCallback = UART_DMAError; 8004600: 68fb ldr r3, [r7, #12] 8004602: 6b1b ldr r3, [r3, #48] ; 0x30 8004604: 4a17 ldr r2, [pc, #92] ; (8004664 ) 8004606: 631a str r2, [r3, #48] ; 0x30 /* Set the DMA abort callback */ huart->hdmatx->XferAbortCallback = NULL; 8004608: 68fb ldr r3, [r7, #12] 800460a: 6b1b ldr r3, [r3, #48] ; 0x30 800460c: 2200 movs r2, #0 800460e: 635a str r2, [r3, #52] ; 0x34 /* Enable the UART transmit DMA channel */ tmp = (uint32_t *)&pData; 8004610: f107 0308 add.w r3, r7, #8 8004614: 617b str r3, [r7, #20] HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t *)tmp, (uint32_t)&huart->Instance->DR, Size); 8004616: 68fb ldr r3, [r7, #12] 8004618: 6b18 ldr r0, [r3, #48] ; 0x30 800461a: 697b ldr r3, [r7, #20] 800461c: 6819 ldr r1, [r3, #0] 800461e: 68fb ldr r3, [r7, #12] 8004620: 681b ldr r3, [r3, #0] 8004622: 3304 adds r3, #4 8004624: 461a mov r2, r3 8004626: 88fb ldrh r3, [r7, #6] 8004628: f7fe f966 bl 80028f8 /* Clear the TC flag in the SR register by writing 0 to it */ __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC); 800462c: 68fb ldr r3, [r7, #12] 800462e: 681b ldr r3, [r3, #0] 8004630: f06f 0240 mvn.w r2, #64 ; 0x40 8004634: 601a str r2, [r3, #0] /* Process Unlocked */ __HAL_UNLOCK(huart); 8004636: 68fb ldr r3, [r7, #12] 8004638: 2200 movs r2, #0 800463a: f883 2038 strb.w r2, [r3, #56] ; 0x38 /* Enable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); 800463e: 68fb ldr r3, [r7, #12] 8004640: 681b ldr r3, [r3, #0] 8004642: 695a ldr r2, [r3, #20] 8004644: 68fb ldr r3, [r7, #12] 8004646: 681b ldr r3, [r3, #0] 8004648: f042 0280 orr.w r2, r2, #128 ; 0x80 800464c: 615a str r2, [r3, #20] return HAL_OK; 800464e: 2300 movs r3, #0 8004650: e000 b.n 8004654 } else { return HAL_BUSY; 8004652: 2302 movs r3, #2 } } 8004654: 4618 mov r0, r3 8004656: 3718 adds r7, #24 8004658: 46bd mov sp, r7 800465a: bd80 pop {r7, pc} 800465c: 080049a9 .word 0x080049a9 8004660: 080049fb .word 0x080049fb 8004664: 08004a9b .word 0x08004a9b 08004668 : * @param Size Amount of data elements (u8 or u16) to be received. * @note When the UART parity is enabled (PCE = 1) the received data contains the parity bit. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8004668: b580 push {r7, lr} 800466a: b086 sub sp, #24 800466c: af00 add r7, sp, #0 800466e: 60f8 str r0, [r7, #12] 8004670: 60b9 str r1, [r7, #8] 8004672: 4613 mov r3, r2 8004674: 80fb strh r3, [r7, #6] uint32_t *tmp; /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) 8004676: 68fb ldr r3, [r7, #12] 8004678: f893 303a ldrb.w r3, [r3, #58] ; 0x3a 800467c: b2db uxtb r3, r3 800467e: 2b20 cmp r3, #32 8004680: d166 bne.n 8004750 { if ((pData == NULL) || (Size == 0U)) 8004682: 68bb ldr r3, [r7, #8] 8004684: 2b00 cmp r3, #0 8004686: d002 beq.n 800468e 8004688: 88fb ldrh r3, [r7, #6] 800468a: 2b00 cmp r3, #0 800468c: d101 bne.n 8004692 { return HAL_ERROR; 800468e: 2301 movs r3, #1 8004690: e05f b.n 8004752 } /* Process Locked */ __HAL_LOCK(huart); 8004692: 68fb ldr r3, [r7, #12] 8004694: f893 3038 ldrb.w r3, [r3, #56] ; 0x38 8004698: 2b01 cmp r3, #1 800469a: d101 bne.n 80046a0 800469c: 2302 movs r3, #2 800469e: e058 b.n 8004752 80046a0: 68fb ldr r3, [r7, #12] 80046a2: 2201 movs r2, #1 80046a4: f883 2038 strb.w r2, [r3, #56] ; 0x38 huart->pRxBuffPtr = pData; 80046a8: 68ba ldr r2, [r7, #8] 80046aa: 68fb ldr r3, [r7, #12] 80046ac: 629a str r2, [r3, #40] ; 0x28 huart->RxXferSize = Size; 80046ae: 68fb ldr r3, [r7, #12] 80046b0: 88fa ldrh r2, [r7, #6] 80046b2: 859a strh r2, [r3, #44] ; 0x2c huart->ErrorCode = HAL_UART_ERROR_NONE; 80046b4: 68fb ldr r3, [r7, #12] 80046b6: 2200 movs r2, #0 80046b8: 63da str r2, [r3, #60] ; 0x3c huart->RxState = HAL_UART_STATE_BUSY_RX; 80046ba: 68fb ldr r3, [r7, #12] 80046bc: 2222 movs r2, #34 ; 0x22 80046be: f883 203a strb.w r2, [r3, #58] ; 0x3a /* Set the UART DMA transfer complete callback */ huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; 80046c2: 68fb ldr r3, [r7, #12] 80046c4: 6b5b ldr r3, [r3, #52] ; 0x34 80046c6: 4a25 ldr r2, [pc, #148] ; (800475c ) 80046c8: 629a str r2, [r3, #40] ; 0x28 /* Set the UART DMA Half transfer complete callback */ huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; 80046ca: 68fb ldr r3, [r7, #12] 80046cc: 6b5b ldr r3, [r3, #52] ; 0x34 80046ce: 4a24 ldr r2, [pc, #144] ; (8004760 ) 80046d0: 62da str r2, [r3, #44] ; 0x2c /* Set the DMA error callback */ huart->hdmarx->XferErrorCallback = UART_DMAError; 80046d2: 68fb ldr r3, [r7, #12] 80046d4: 6b5b ldr r3, [r3, #52] ; 0x34 80046d6: 4a23 ldr r2, [pc, #140] ; (8004764 ) 80046d8: 631a str r2, [r3, #48] ; 0x30 /* Set the DMA abort callback */ huart->hdmarx->XferAbortCallback = NULL; 80046da: 68fb ldr r3, [r7, #12] 80046dc: 6b5b ldr r3, [r3, #52] ; 0x34 80046de: 2200 movs r2, #0 80046e0: 635a str r2, [r3, #52] ; 0x34 /* Enable the DMA channel */ tmp = (uint32_t *)&pData; 80046e2: f107 0308 add.w r3, r7, #8 80046e6: 617b str r3, [r7, #20] HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t *)tmp, Size); 80046e8: 68fb ldr r3, [r7, #12] 80046ea: 6b58 ldr r0, [r3, #52] ; 0x34 80046ec: 68fb ldr r3, [r7, #12] 80046ee: 681b ldr r3, [r3, #0] 80046f0: 3304 adds r3, #4 80046f2: 4619 mov r1, r3 80046f4: 697b ldr r3, [r7, #20] 80046f6: 681a ldr r2, [r3, #0] 80046f8: 88fb ldrh r3, [r7, #6] 80046fa: f7fe f8fd bl 80028f8 /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */ __HAL_UART_CLEAR_OREFLAG(huart); 80046fe: 2300 movs r3, #0 8004700: 613b str r3, [r7, #16] 8004702: 68fb ldr r3, [r7, #12] 8004704: 681b ldr r3, [r3, #0] 8004706: 681b ldr r3, [r3, #0] 8004708: 613b str r3, [r7, #16] 800470a: 68fb ldr r3, [r7, #12] 800470c: 681b ldr r3, [r3, #0] 800470e: 685b ldr r3, [r3, #4] 8004710: 613b str r3, [r7, #16] 8004712: 693b ldr r3, [r7, #16] /* Process Unlocked */ __HAL_UNLOCK(huart); 8004714: 68fb ldr r3, [r7, #12] 8004716: 2200 movs r2, #0 8004718: f883 2038 strb.w r2, [r3, #56] ; 0x38 /* Enable the UART Parity Error Interrupt */ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); 800471c: 68fb ldr r3, [r7, #12] 800471e: 681b ldr r3, [r3, #0] 8004720: 68da ldr r2, [r3, #12] 8004722: 68fb ldr r3, [r7, #12] 8004724: 681b ldr r3, [r3, #0] 8004726: f442 7280 orr.w r2, r2, #256 ; 0x100 800472a: 60da str r2, [r3, #12] /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(huart->Instance->CR3, USART_CR3_EIE); 800472c: 68fb ldr r3, [r7, #12] 800472e: 681b ldr r3, [r3, #0] 8004730: 695a ldr r2, [r3, #20] 8004732: 68fb ldr r3, [r7, #12] 8004734: 681b ldr r3, [r3, #0] 8004736: f042 0201 orr.w r2, r2, #1 800473a: 615a str r2, [r3, #20] /* Enable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); 800473c: 68fb ldr r3, [r7, #12] 800473e: 681b ldr r3, [r3, #0] 8004740: 695a ldr r2, [r3, #20] 8004742: 68fb ldr r3, [r7, #12] 8004744: 681b ldr r3, [r3, #0] 8004746: f042 0240 orr.w r2, r2, #64 ; 0x40 800474a: 615a str r2, [r3, #20] return HAL_OK; 800474c: 2300 movs r3, #0 800474e: e000 b.n 8004752 } else { return HAL_BUSY; 8004750: 2302 movs r3, #2 } } 8004752: 4618 mov r0, r3 8004754: 3718 adds r7, #24 8004756: 46bd mov sp, r7 8004758: bd80 pop {r7, pc} 800475a: bf00 nop 800475c: 08004a17 .word 0x08004a17 8004760: 08004a7f .word 0x08004a7f 8004764: 08004a9b .word 0x08004a9b 08004768 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { 8004768: b580 push {r7, lr} 800476a: b088 sub sp, #32 800476c: af00 add r7, sp, #0 800476e: 6078 str r0, [r7, #4] uint32_t isrflags = READ_REG(huart->Instance->SR); 8004770: 687b ldr r3, [r7, #4] 8004772: 681b ldr r3, [r3, #0] 8004774: 681b ldr r3, [r3, #0] 8004776: 61fb str r3, [r7, #28] uint32_t cr1its = READ_REG(huart->Instance->CR1); 8004778: 687b ldr r3, [r7, #4] 800477a: 681b ldr r3, [r3, #0] 800477c: 68db ldr r3, [r3, #12] 800477e: 61bb str r3, [r7, #24] uint32_t cr3its = READ_REG(huart->Instance->CR3); 8004780: 687b ldr r3, [r7, #4] 8004782: 681b ldr r3, [r3, #0] 8004784: 695b ldr r3, [r3, #20] 8004786: 617b str r3, [r7, #20] uint32_t errorflags = 0x00U; 8004788: 2300 movs r3, #0 800478a: 613b str r3, [r7, #16] uint32_t dmarequest = 0x00U; 800478c: 2300 movs r3, #0 800478e: 60fb str r3, [r7, #12] /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE)); 8004790: 69fb ldr r3, [r7, #28] 8004792: f003 030f and.w r3, r3, #15 8004796: 613b str r3, [r7, #16] if (errorflags == RESET) 8004798: 693b ldr r3, [r7, #16] 800479a: 2b00 cmp r3, #0 800479c: d10d bne.n 80047ba { /* UART in mode Receiver -------------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 800479e: 69fb ldr r3, [r7, #28] 80047a0: f003 0320 and.w r3, r3, #32 80047a4: 2b00 cmp r3, #0 80047a6: d008 beq.n 80047ba 80047a8: 69bb ldr r3, [r7, #24] 80047aa: f003 0320 and.w r3, r3, #32 80047ae: 2b00 cmp r3, #0 80047b0: d003 beq.n 80047ba { UART_Receive_IT(huart); 80047b2: 6878 ldr r0, [r7, #4] 80047b4: f000 fab8 bl 8004d28 return; 80047b8: e0cc b.n 8004954 } } /* If some errors occur */ if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) 80047ba: 693b ldr r3, [r7, #16] 80047bc: 2b00 cmp r3, #0 80047be: f000 80ab beq.w 8004918 80047c2: 697b ldr r3, [r7, #20] 80047c4: f003 0301 and.w r3, r3, #1 80047c8: 2b00 cmp r3, #0 80047ca: d105 bne.n 80047d8 80047cc: 69bb ldr r3, [r7, #24] 80047ce: f403 7390 and.w r3, r3, #288 ; 0x120 80047d2: 2b00 cmp r3, #0 80047d4: f000 80a0 beq.w 8004918 { /* UART parity error interrupt occurred ----------------------------------*/ if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) 80047d8: 69fb ldr r3, [r7, #28] 80047da: f003 0301 and.w r3, r3, #1 80047de: 2b00 cmp r3, #0 80047e0: d00a beq.n 80047f8 80047e2: 69bb ldr r3, [r7, #24] 80047e4: f403 7380 and.w r3, r3, #256 ; 0x100 80047e8: 2b00 cmp r3, #0 80047ea: d005 beq.n 80047f8 { huart->ErrorCode |= HAL_UART_ERROR_PE; 80047ec: 687b ldr r3, [r7, #4] 80047ee: 6bdb ldr r3, [r3, #60] ; 0x3c 80047f0: f043 0201 orr.w r2, r3, #1 80047f4: 687b ldr r3, [r7, #4] 80047f6: 63da str r2, [r3, #60] ; 0x3c } /* UART noise error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 80047f8: 69fb ldr r3, [r7, #28] 80047fa: f003 0304 and.w r3, r3, #4 80047fe: 2b00 cmp r3, #0 8004800: d00a beq.n 8004818 8004802: 697b ldr r3, [r7, #20] 8004804: f003 0301 and.w r3, r3, #1 8004808: 2b00 cmp r3, #0 800480a: d005 beq.n 8004818 { huart->ErrorCode |= HAL_UART_ERROR_NE; 800480c: 687b ldr r3, [r7, #4] 800480e: 6bdb ldr r3, [r3, #60] ; 0x3c 8004810: f043 0202 orr.w r2, r3, #2 8004814: 687b ldr r3, [r7, #4] 8004816: 63da str r2, [r3, #60] ; 0x3c } /* UART frame error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 8004818: 69fb ldr r3, [r7, #28] 800481a: f003 0302 and.w r3, r3, #2 800481e: 2b00 cmp r3, #0 8004820: d00a beq.n 8004838 8004822: 697b ldr r3, [r7, #20] 8004824: f003 0301 and.w r3, r3, #1 8004828: 2b00 cmp r3, #0 800482a: d005 beq.n 8004838 { huart->ErrorCode |= HAL_UART_ERROR_FE; 800482c: 687b ldr r3, [r7, #4] 800482e: 6bdb ldr r3, [r3, #60] ; 0x3c 8004830: f043 0204 orr.w r2, r3, #4 8004834: 687b ldr r3, [r7, #4] 8004836: 63da str r2, [r3, #60] ; 0x3c } /* UART Over-Run interrupt occurred --------------------------------------*/ if (((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 8004838: 69fb ldr r3, [r7, #28] 800483a: f003 0308 and.w r3, r3, #8 800483e: 2b00 cmp r3, #0 8004840: d00a beq.n 8004858 8004842: 697b ldr r3, [r7, #20] 8004844: f003 0301 and.w r3, r3, #1 8004848: 2b00 cmp r3, #0 800484a: d005 beq.n 8004858 { huart->ErrorCode |= HAL_UART_ERROR_ORE; 800484c: 687b ldr r3, [r7, #4] 800484e: 6bdb ldr r3, [r3, #60] ; 0x3c 8004850: f043 0208 orr.w r2, r3, #8 8004854: 687b ldr r3, [r7, #4] 8004856: 63da str r2, [r3, #60] ; 0x3c } /* Call UART Error Call back function if need be --------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 8004858: 687b ldr r3, [r7, #4] 800485a: 6bdb ldr r3, [r3, #60] ; 0x3c 800485c: 2b00 cmp r3, #0 800485e: d078 beq.n 8004952 { /* UART in mode Receiver -----------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 8004860: 69fb ldr r3, [r7, #28] 8004862: f003 0320 and.w r3, r3, #32 8004866: 2b00 cmp r3, #0 8004868: d007 beq.n 800487a 800486a: 69bb ldr r3, [r7, #24] 800486c: f003 0320 and.w r3, r3, #32 8004870: 2b00 cmp r3, #0 8004872: d002 beq.n 800487a { UART_Receive_IT(huart); 8004874: 6878 ldr r0, [r7, #4] 8004876: f000 fa57 bl 8004d28 } /* If Overrun error occurs, or if any error occurs in DMA mode reception, consider error as blocking */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 800487a: 687b ldr r3, [r7, #4] 800487c: 681b ldr r3, [r3, #0] 800487e: 695b ldr r3, [r3, #20] 8004880: f003 0340 and.w r3, r3, #64 ; 0x40 8004884: 2b00 cmp r3, #0 8004886: bf14 ite ne 8004888: 2301 movne r3, #1 800488a: 2300 moveq r3, #0 800488c: b2db uxtb r3, r3 800488e: 60fb str r3, [r7, #12] if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest) 8004890: 687b ldr r3, [r7, #4] 8004892: 6bdb ldr r3, [r3, #60] ; 0x3c 8004894: f003 0308 and.w r3, r3, #8 8004898: 2b00 cmp r3, #0 800489a: d102 bne.n 80048a2 800489c: 68fb ldr r3, [r7, #12] 800489e: 2b00 cmp r3, #0 80048a0: d031 beq.n 8004906 { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); 80048a2: 6878 ldr r0, [r7, #4] 80048a4: f000 f9a2 bl 8004bec /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80048a8: 687b ldr r3, [r7, #4] 80048aa: 681b ldr r3, [r3, #0] 80048ac: 695b ldr r3, [r3, #20] 80048ae: f003 0340 and.w r3, r3, #64 ; 0x40 80048b2: 2b00 cmp r3, #0 80048b4: d023 beq.n 80048fe { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 80048b6: 687b ldr r3, [r7, #4] 80048b8: 681b ldr r3, [r3, #0] 80048ba: 695a ldr r2, [r3, #20] 80048bc: 687b ldr r3, [r7, #4] 80048be: 681b ldr r3, [r3, #0] 80048c0: f022 0240 bic.w r2, r2, #64 ; 0x40 80048c4: 615a str r2, [r3, #20] /* Abort the UART DMA Rx channel */ if (huart->hdmarx != NULL) 80048c6: 687b ldr r3, [r7, #4] 80048c8: 6b5b ldr r3, [r3, #52] ; 0x34 80048ca: 2b00 cmp r3, #0 80048cc: d013 beq.n 80048f6 { /* Set the UART DMA Abort callback : will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; 80048ce: 687b ldr r3, [r7, #4] 80048d0: 6b5b ldr r3, [r3, #52] ; 0x34 80048d2: 4a22 ldr r2, [pc, #136] ; (800495c ) 80048d4: 635a str r2, [r3, #52] ; 0x34 if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 80048d6: 687b ldr r3, [r7, #4] 80048d8: 6b5b ldr r3, [r3, #52] ; 0x34 80048da: 4618 mov r0, r3 80048dc: f7fe f86c bl 80029b8 80048e0: 4603 mov r3, r0 80048e2: 2b00 cmp r3, #0 80048e4: d016 beq.n 8004914 { /* Call Directly XferAbortCallback function in case of error */ huart->hdmarx->XferAbortCallback(huart->hdmarx); 80048e6: 687b ldr r3, [r7, #4] 80048e8: 6b5b ldr r3, [r3, #52] ; 0x34 80048ea: 6b5b ldr r3, [r3, #52] ; 0x34 80048ec: 687a ldr r2, [r7, #4] 80048ee: 6b52 ldr r2, [r2, #52] ; 0x34 80048f0: 4610 mov r0, r2 80048f2: 4798 blx r3 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80048f4: e00e b.n 8004914 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 80048f6: 6878 ldr r0, [r7, #4] 80048f8: f000 f84d bl 8004996 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80048fc: e00a b.n 8004914 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 80048fe: 6878 ldr r0, [r7, #4] 8004900: f000 f849 bl 8004996 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8004904: e006 b.n 8004914 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8004906: 6878 ldr r0, [r7, #4] 8004908: f000 f845 bl 8004996 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 800490c: 687b ldr r3, [r7, #4] 800490e: 2200 movs r2, #0 8004910: 63da str r2, [r3, #60] ; 0x3c } } return; 8004912: e01e b.n 8004952 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8004914: bf00 nop return; 8004916: e01c b.n 8004952 } /* End if some error occurs */ /* UART in mode Transmitter ------------------------------------------------*/ if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) 8004918: 69fb ldr r3, [r7, #28] 800491a: f003 0380 and.w r3, r3, #128 ; 0x80 800491e: 2b00 cmp r3, #0 8004920: d008 beq.n 8004934 8004922: 69bb ldr r3, [r7, #24] 8004924: f003 0380 and.w r3, r3, #128 ; 0x80 8004928: 2b00 cmp r3, #0 800492a: d003 beq.n 8004934 { UART_Transmit_IT(huart); 800492c: 6878 ldr r0, [r7, #4] 800492e: f000 f98e bl 8004c4e return; 8004932: e00f b.n 8004954 } /* UART in mode Transmitter end --------------------------------------------*/ if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) 8004934: 69fb ldr r3, [r7, #28] 8004936: f003 0340 and.w r3, r3, #64 ; 0x40 800493a: 2b00 cmp r3, #0 800493c: d00a beq.n 8004954 800493e: 69bb ldr r3, [r7, #24] 8004940: f003 0340 and.w r3, r3, #64 ; 0x40 8004944: 2b00 cmp r3, #0 8004946: d005 beq.n 8004954 { UART_EndTransmit_IT(huart); 8004948: 6878 ldr r0, [r7, #4] 800494a: f000 f9d5 bl 8004cf8 return; 800494e: bf00 nop 8004950: e000 b.n 8004954 return; 8004952: bf00 nop } } 8004954: 3720 adds r7, #32 8004956: 46bd mov sp, r7 8004958: bd80 pop {r7, pc} 800495a: bf00 nop 800495c: 08004c27 .word 0x08004c27 08004960 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { 8004960: b480 push {r7} 8004962: b083 sub sp, #12 8004964: af00 add r7, sp, #0 8004966: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_TxCpltCallback could be implemented in the user file */ } 8004968: bf00 nop 800496a: 370c adds r7, #12 800496c: 46bd mov sp, r7 800496e: bc80 pop {r7} 8004970: 4770 bx lr 08004972 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) { 8004972: b480 push {r7} 8004974: b083 sub sp, #12 8004976: af00 add r7, sp, #0 8004978: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_TxHalfCpltCallback could be implemented in the user file */ } 800497a: bf00 nop 800497c: 370c adds r7, #12 800497e: 46bd mov sp, r7 8004980: bc80 pop {r7} 8004982: 4770 bx lr 08004984 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) { 8004984: b480 push {r7} 8004986: b083 sub sp, #12 8004988: af00 add r7, sp, #0 800498a: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_RxHalfCpltCallback could be implemented in the user file */ } 800498c: bf00 nop 800498e: 370c adds r7, #12 8004990: 46bd mov sp, r7 8004992: bc80 pop {r7} 8004994: 4770 bx lr 08004996 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { 8004996: b480 push {r7} 8004998: b083 sub sp, #12 800499a: af00 add r7, sp, #0 800499c: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_ErrorCallback could be implemented in the user file */ } 800499e: bf00 nop 80049a0: 370c adds r7, #12 80049a2: 46bd mov sp, r7 80049a4: bc80 pop {r7} 80049a6: 4770 bx lr 080049a8 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) { 80049a8: b580 push {r7, lr} 80049aa: b084 sub sp, #16 80049ac: af00 add r7, sp, #0 80049ae: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 80049b0: 687b ldr r3, [r7, #4] 80049b2: 6a5b ldr r3, [r3, #36] ; 0x24 80049b4: 60fb str r3, [r7, #12] /* DMA Normal mode*/ if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 80049b6: 687b ldr r3, [r7, #4] 80049b8: 681b ldr r3, [r3, #0] 80049ba: 681b ldr r3, [r3, #0] 80049bc: f003 0320 and.w r3, r3, #32 80049c0: 2b00 cmp r3, #0 80049c2: d113 bne.n 80049ec { huart->TxXferCount = 0x00U; 80049c4: 68fb ldr r3, [r7, #12] 80049c6: 2200 movs r2, #0 80049c8: 84da strh r2, [r3, #38] ; 0x26 /* Disable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); 80049ca: 68fb ldr r3, [r7, #12] 80049cc: 681b ldr r3, [r3, #0] 80049ce: 695a ldr r2, [r3, #20] 80049d0: 68fb ldr r3, [r7, #12] 80049d2: 681b ldr r3, [r3, #0] 80049d4: f022 0280 bic.w r2, r2, #128 ; 0x80 80049d8: 615a str r2, [r3, #20] /* Enable the UART Transmit Complete Interrupt */ SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 80049da: 68fb ldr r3, [r7, #12] 80049dc: 681b ldr r3, [r3, #0] 80049de: 68da ldr r2, [r3, #12] 80049e0: 68fb ldr r3, [r7, #12] 80049e2: 681b ldr r3, [r3, #0] 80049e4: f042 0240 orr.w r2, r2, #64 ; 0x40 80049e8: 60da str r2, [r3, #12] #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } 80049ea: e002 b.n 80049f2 HAL_UART_TxCpltCallback(huart); 80049ec: 68f8 ldr r0, [r7, #12] 80049ee: f7ff ffb7 bl 8004960 } 80049f2: bf00 nop 80049f4: 3710 adds r7, #16 80049f6: 46bd mov sp, r7 80049f8: bd80 pop {r7, pc} 080049fa : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) { 80049fa: b580 push {r7, lr} 80049fc: b084 sub sp, #16 80049fe: af00 add r7, sp, #0 8004a00: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8004a02: 687b ldr r3, [r7, #4] 8004a04: 6a5b ldr r3, [r3, #36] ; 0x24 8004a06: 60fb str r3, [r7, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxHalfCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxHalfCpltCallback(huart); 8004a08: 68f8 ldr r0, [r7, #12] 8004a0a: f7ff ffb2 bl 8004972 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8004a0e: bf00 nop 8004a10: 3710 adds r7, #16 8004a12: 46bd mov sp, r7 8004a14: bd80 pop {r7, pc} 08004a16 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { 8004a16: b580 push {r7, lr} 8004a18: b084 sub sp, #16 8004a1a: af00 add r7, sp, #0 8004a1c: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8004a1e: 687b ldr r3, [r7, #4] 8004a20: 6a5b ldr r3, [r3, #36] ; 0x24 8004a22: 60fb str r3, [r7, #12] /* DMA Normal mode*/ if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 8004a24: 687b ldr r3, [r7, #4] 8004a26: 681b ldr r3, [r3, #0] 8004a28: 681b ldr r3, [r3, #0] 8004a2a: f003 0320 and.w r3, r3, #32 8004a2e: 2b00 cmp r3, #0 8004a30: d11e bne.n 8004a70 { huart->RxXferCount = 0U; 8004a32: 68fb ldr r3, [r7, #12] 8004a34: 2200 movs r2, #0 8004a36: 85da strh r2, [r3, #46] ; 0x2e /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8004a38: 68fb ldr r3, [r7, #12] 8004a3a: 681b ldr r3, [r3, #0] 8004a3c: 68da ldr r2, [r3, #12] 8004a3e: 68fb ldr r3, [r7, #12] 8004a40: 681b ldr r3, [r3, #0] 8004a42: f422 7280 bic.w r2, r2, #256 ; 0x100 8004a46: 60da str r2, [r3, #12] CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8004a48: 68fb ldr r3, [r7, #12] 8004a4a: 681b ldr r3, [r3, #0] 8004a4c: 695a ldr r2, [r3, #20] 8004a4e: 68fb ldr r3, [r7, #12] 8004a50: 681b ldr r3, [r3, #0] 8004a52: f022 0201 bic.w r2, r2, #1 8004a56: 615a str r2, [r3, #20] /* Disable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8004a58: 68fb ldr r3, [r7, #12] 8004a5a: 681b ldr r3, [r3, #0] 8004a5c: 695a ldr r2, [r3, #20] 8004a5e: 68fb ldr r3, [r7, #12] 8004a60: 681b ldr r3, [r3, #0] 8004a62: f022 0240 bic.w r2, r2, #64 ; 0x40 8004a66: 615a str r2, [r3, #20] /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8004a68: 68fb ldr r3, [r7, #12] 8004a6a: 2220 movs r2, #32 8004a6c: f883 203a strb.w r2, [r3, #58] ; 0x3a #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 8004a70: 68f8 ldr r0, [r7, #12] 8004a72: f7fc ffb1 bl 80019d8 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8004a76: bf00 nop 8004a78: 3710 adds r7, #16 8004a7a: 46bd mov sp, r7 8004a7c: bd80 pop {r7, pc} 08004a7e : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { 8004a7e: b580 push {r7, lr} 8004a80: b084 sub sp, #16 8004a82: af00 add r7, sp, #0 8004a84: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8004a86: 687b ldr r3, [r7, #4] 8004a88: 6a5b ldr r3, [r3, #36] ; 0x24 8004a8a: 60fb str r3, [r7, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Half complete callback*/ huart->RxHalfCpltCallback(huart); #else /*Call legacy weak Rx Half complete callback*/ HAL_UART_RxHalfCpltCallback(huart); 8004a8c: 68f8 ldr r0, [r7, #12] 8004a8e: f7ff ff79 bl 8004984 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8004a92: bf00 nop 8004a94: 3710 adds r7, #16 8004a96: 46bd mov sp, r7 8004a98: bd80 pop {r7, pc} 08004a9a : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAError(DMA_HandleTypeDef *hdma) { 8004a9a: b580 push {r7, lr} 8004a9c: b084 sub sp, #16 8004a9e: af00 add r7, sp, #0 8004aa0: 6078 str r0, [r7, #4] uint32_t dmarequest = 0x00U; 8004aa2: 2300 movs r3, #0 8004aa4: 60fb str r3, [r7, #12] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8004aa6: 687b ldr r3, [r7, #4] 8004aa8: 6a5b ldr r3, [r3, #36] ; 0x24 8004aaa: 60bb str r3, [r7, #8] /* Stop UART DMA Tx request if ongoing */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT); 8004aac: 68bb ldr r3, [r7, #8] 8004aae: 681b ldr r3, [r3, #0] 8004ab0: 695b ldr r3, [r3, #20] 8004ab2: f003 0380 and.w r3, r3, #128 ; 0x80 8004ab6: 2b00 cmp r3, #0 8004ab8: bf14 ite ne 8004aba: 2301 movne r3, #1 8004abc: 2300 moveq r3, #0 8004abe: b2db uxtb r3, r3 8004ac0: 60fb str r3, [r7, #12] if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) 8004ac2: 68bb ldr r3, [r7, #8] 8004ac4: f893 3039 ldrb.w r3, [r3, #57] ; 0x39 8004ac8: b2db uxtb r3, r3 8004aca: 2b21 cmp r3, #33 ; 0x21 8004acc: d108 bne.n 8004ae0 8004ace: 68fb ldr r3, [r7, #12] 8004ad0: 2b00 cmp r3, #0 8004ad2: d005 beq.n 8004ae0 { huart->TxXferCount = 0x00U; 8004ad4: 68bb ldr r3, [r7, #8] 8004ad6: 2200 movs r2, #0 8004ad8: 84da strh r2, [r3, #38] ; 0x26 UART_EndTxTransfer(huart); 8004ada: 68b8 ldr r0, [r7, #8] 8004adc: f000 f871 bl 8004bc2 } /* Stop UART DMA Rx request if ongoing */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 8004ae0: 68bb ldr r3, [r7, #8] 8004ae2: 681b ldr r3, [r3, #0] 8004ae4: 695b ldr r3, [r3, #20] 8004ae6: f003 0340 and.w r3, r3, #64 ; 0x40 8004aea: 2b00 cmp r3, #0 8004aec: bf14 ite ne 8004aee: 2301 movne r3, #1 8004af0: 2300 moveq r3, #0 8004af2: b2db uxtb r3, r3 8004af4: 60fb str r3, [r7, #12] if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest) 8004af6: 68bb ldr r3, [r7, #8] 8004af8: f893 303a ldrb.w r3, [r3, #58] ; 0x3a 8004afc: b2db uxtb r3, r3 8004afe: 2b22 cmp r3, #34 ; 0x22 8004b00: d108 bne.n 8004b14 8004b02: 68fb ldr r3, [r7, #12] 8004b04: 2b00 cmp r3, #0 8004b06: d005 beq.n 8004b14 { huart->RxXferCount = 0x00U; 8004b08: 68bb ldr r3, [r7, #8] 8004b0a: 2200 movs r2, #0 8004b0c: 85da strh r2, [r3, #46] ; 0x2e UART_EndRxTransfer(huart); 8004b0e: 68b8 ldr r0, [r7, #8] 8004b10: f000 f86c bl 8004bec } huart->ErrorCode |= HAL_UART_ERROR_DMA; 8004b14: 68bb ldr r3, [r7, #8] 8004b16: 6bdb ldr r3, [r3, #60] ; 0x3c 8004b18: f043 0210 orr.w r2, r3, #16 8004b1c: 68bb ldr r3, [r7, #8] 8004b1e: 63da str r2, [r3, #60] ; 0x3c #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8004b20: 68b8 ldr r0, [r7, #8] 8004b22: f7ff ff38 bl 8004996 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8004b26: bf00 nop 8004b28: 3710 adds r7, #16 8004b2a: 46bd mov sp, r7 8004b2c: bd80 pop {r7, pc} 08004b2e : * @param Tickstart Tick start value * @param Timeout Timeout duration * @retval HAL status */ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { 8004b2e: b580 push {r7, lr} 8004b30: b084 sub sp, #16 8004b32: af00 add r7, sp, #0 8004b34: 60f8 str r0, [r7, #12] 8004b36: 60b9 str r1, [r7, #8] 8004b38: 603b str r3, [r7, #0] 8004b3a: 4613 mov r3, r2 8004b3c: 71fb strb r3, [r7, #7] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8004b3e: e02c b.n 8004b9a { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 8004b40: 69bb ldr r3, [r7, #24] 8004b42: f1b3 3fff cmp.w r3, #4294967295 8004b46: d028 beq.n 8004b9a { if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) 8004b48: 69bb ldr r3, [r7, #24] 8004b4a: 2b00 cmp r3, #0 8004b4c: d007 beq.n 8004b5e 8004b4e: f7fd f88d bl 8001c6c 8004b52: 4602 mov r2, r0 8004b54: 683b ldr r3, [r7, #0] 8004b56: 1ad3 subs r3, r2, r3 8004b58: 69ba ldr r2, [r7, #24] 8004b5a: 429a cmp r2, r3 8004b5c: d21d bcs.n 8004b9a { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); 8004b5e: 68fb ldr r3, [r7, #12] 8004b60: 681b ldr r3, [r3, #0] 8004b62: 68da ldr r2, [r3, #12] 8004b64: 68fb ldr r3, [r7, #12] 8004b66: 681b ldr r3, [r3, #0] 8004b68: f422 72d0 bic.w r2, r2, #416 ; 0x1a0 8004b6c: 60da str r2, [r3, #12] CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8004b6e: 68fb ldr r3, [r7, #12] 8004b70: 681b ldr r3, [r3, #0] 8004b72: 695a ldr r2, [r3, #20] 8004b74: 68fb ldr r3, [r7, #12] 8004b76: 681b ldr r3, [r3, #0] 8004b78: f022 0201 bic.w r2, r2, #1 8004b7c: 615a str r2, [r3, #20] huart->gState = HAL_UART_STATE_READY; 8004b7e: 68fb ldr r3, [r7, #12] 8004b80: 2220 movs r2, #32 8004b82: f883 2039 strb.w r2, [r3, #57] ; 0x39 huart->RxState = HAL_UART_STATE_READY; 8004b86: 68fb ldr r3, [r7, #12] 8004b88: 2220 movs r2, #32 8004b8a: f883 203a strb.w r2, [r3, #58] ; 0x3a /* Process Unlocked */ __HAL_UNLOCK(huart); 8004b8e: 68fb ldr r3, [r7, #12] 8004b90: 2200 movs r2, #0 8004b92: f883 2038 strb.w r2, [r3, #56] ; 0x38 return HAL_TIMEOUT; 8004b96: 2303 movs r3, #3 8004b98: e00f b.n 8004bba while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8004b9a: 68fb ldr r3, [r7, #12] 8004b9c: 681b ldr r3, [r3, #0] 8004b9e: 681a ldr r2, [r3, #0] 8004ba0: 68bb ldr r3, [r7, #8] 8004ba2: 4013 ands r3, r2 8004ba4: 68ba ldr r2, [r7, #8] 8004ba6: 429a cmp r2, r3 8004ba8: bf0c ite eq 8004baa: 2301 moveq r3, #1 8004bac: 2300 movne r3, #0 8004bae: b2db uxtb r3, r3 8004bb0: 461a mov r2, r3 8004bb2: 79fb ldrb r3, [r7, #7] 8004bb4: 429a cmp r2, r3 8004bb6: d0c3 beq.n 8004b40 } } } return HAL_OK; 8004bb8: 2300 movs r3, #0 } 8004bba: 4618 mov r0, r3 8004bbc: 3710 adds r7, #16 8004bbe: 46bd mov sp, r7 8004bc0: bd80 pop {r7, pc} 08004bc2 : * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). * @param huart UART handle. * @retval None */ static void UART_EndTxTransfer(UART_HandleTypeDef *huart) { 8004bc2: b480 push {r7} 8004bc4: b083 sub sp, #12 8004bc6: af00 add r7, sp, #0 8004bc8: 6078 str r0, [r7, #4] /* Disable TXEIE and TCIE interrupts */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); 8004bca: 687b ldr r3, [r7, #4] 8004bcc: 681b ldr r3, [r3, #0] 8004bce: 68da ldr r2, [r3, #12] 8004bd0: 687b ldr r3, [r7, #4] 8004bd2: 681b ldr r3, [r3, #0] 8004bd4: f022 02c0 bic.w r2, r2, #192 ; 0xc0 8004bd8: 60da str r2, [r3, #12] /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8004bda: 687b ldr r3, [r7, #4] 8004bdc: 2220 movs r2, #32 8004bde: f883 2039 strb.w r2, [r3, #57] ; 0x39 } 8004be2: bf00 nop 8004be4: 370c adds r7, #12 8004be6: 46bd mov sp, r7 8004be8: bc80 pop {r7} 8004bea: 4770 bx lr 08004bec : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 8004bec: b480 push {r7} 8004bee: b083 sub sp, #12 8004bf0: af00 add r7, sp, #0 8004bf2: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 8004bf4: 687b ldr r3, [r7, #4] 8004bf6: 681b ldr r3, [r3, #0] 8004bf8: 68da ldr r2, [r3, #12] 8004bfa: 687b ldr r3, [r7, #4] 8004bfc: 681b ldr r3, [r3, #0] 8004bfe: f422 7290 bic.w r2, r2, #288 ; 0x120 8004c02: 60da str r2, [r3, #12] CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8004c04: 687b ldr r3, [r7, #4] 8004c06: 681b ldr r3, [r3, #0] 8004c08: 695a ldr r2, [r3, #20] 8004c0a: 687b ldr r3, [r7, #4] 8004c0c: 681b ldr r3, [r3, #0] 8004c0e: f022 0201 bic.w r2, r2, #1 8004c12: 615a str r2, [r3, #20] /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8004c14: 687b ldr r3, [r7, #4] 8004c16: 2220 movs r2, #32 8004c18: f883 203a strb.w r2, [r3, #58] ; 0x3a } 8004c1c: bf00 nop 8004c1e: 370c adds r7, #12 8004c20: 46bd mov sp, r7 8004c22: bc80 pop {r7} 8004c24: 4770 bx lr 08004c26 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { 8004c26: b580 push {r7, lr} 8004c28: b084 sub sp, #16 8004c2a: af00 add r7, sp, #0 8004c2c: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8004c2e: 687b ldr r3, [r7, #4] 8004c30: 6a5b ldr r3, [r3, #36] ; 0x24 8004c32: 60fb str r3, [r7, #12] huart->RxXferCount = 0x00U; 8004c34: 68fb ldr r3, [r7, #12] 8004c36: 2200 movs r2, #0 8004c38: 85da strh r2, [r3, #46] ; 0x2e huart->TxXferCount = 0x00U; 8004c3a: 68fb ldr r3, [r7, #12] 8004c3c: 2200 movs r2, #0 8004c3e: 84da strh r2, [r3, #38] ; 0x26 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8004c40: 68f8 ldr r0, [r7, #12] 8004c42: f7ff fea8 bl 8004996 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8004c46: bf00 nop 8004c48: 3710 adds r7, #16 8004c4a: 46bd mov sp, r7 8004c4c: bd80 pop {r7, pc} 08004c4e : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) { 8004c4e: b480 push {r7} 8004c50: b085 sub sp, #20 8004c52: af00 add r7, sp, #0 8004c54: 6078 str r0, [r7, #4] uint16_t *tmp; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 8004c56: 687b ldr r3, [r7, #4] 8004c58: f893 3039 ldrb.w r3, [r3, #57] ; 0x39 8004c5c: b2db uxtb r3, r3 8004c5e: 2b21 cmp r3, #33 ; 0x21 8004c60: d144 bne.n 8004cec { if (huart->Init.WordLength == UART_WORDLENGTH_9B) 8004c62: 687b ldr r3, [r7, #4] 8004c64: 689b ldr r3, [r3, #8] 8004c66: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8004c6a: d11a bne.n 8004ca2 { tmp = (uint16_t *) huart->pTxBuffPtr; 8004c6c: 687b ldr r3, [r7, #4] 8004c6e: 6a1b ldr r3, [r3, #32] 8004c70: 60fb str r3, [r7, #12] huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); 8004c72: 68fb ldr r3, [r7, #12] 8004c74: 881b ldrh r3, [r3, #0] 8004c76: 461a mov r2, r3 8004c78: 687b ldr r3, [r7, #4] 8004c7a: 681b ldr r3, [r3, #0] 8004c7c: f3c2 0208 ubfx r2, r2, #0, #9 8004c80: 605a str r2, [r3, #4] if (huart->Init.Parity == UART_PARITY_NONE) 8004c82: 687b ldr r3, [r7, #4] 8004c84: 691b ldr r3, [r3, #16] 8004c86: 2b00 cmp r3, #0 8004c88: d105 bne.n 8004c96 { huart->pTxBuffPtr += 2U; 8004c8a: 687b ldr r3, [r7, #4] 8004c8c: 6a1b ldr r3, [r3, #32] 8004c8e: 1c9a adds r2, r3, #2 8004c90: 687b ldr r3, [r7, #4] 8004c92: 621a str r2, [r3, #32] 8004c94: e00e b.n 8004cb4 } else { huart->pTxBuffPtr += 1U; 8004c96: 687b ldr r3, [r7, #4] 8004c98: 6a1b ldr r3, [r3, #32] 8004c9a: 1c5a adds r2, r3, #1 8004c9c: 687b ldr r3, [r7, #4] 8004c9e: 621a str r2, [r3, #32] 8004ca0: e008 b.n 8004cb4 } } else { huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF); 8004ca2: 687b ldr r3, [r7, #4] 8004ca4: 6a1b ldr r3, [r3, #32] 8004ca6: 1c59 adds r1, r3, #1 8004ca8: 687a ldr r2, [r7, #4] 8004caa: 6211 str r1, [r2, #32] 8004cac: 781a ldrb r2, [r3, #0] 8004cae: 687b ldr r3, [r7, #4] 8004cb0: 681b ldr r3, [r3, #0] 8004cb2: 605a str r2, [r3, #4] } if (--huart->TxXferCount == 0U) 8004cb4: 687b ldr r3, [r7, #4] 8004cb6: 8cdb ldrh r3, [r3, #38] ; 0x26 8004cb8: b29b uxth r3, r3 8004cba: 3b01 subs r3, #1 8004cbc: b29b uxth r3, r3 8004cbe: 687a ldr r2, [r7, #4] 8004cc0: 4619 mov r1, r3 8004cc2: 84d1 strh r1, [r2, #38] ; 0x26 8004cc4: 2b00 cmp r3, #0 8004cc6: d10f bne.n 8004ce8 { /* Disable the UART Transmit Complete Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); 8004cc8: 687b ldr r3, [r7, #4] 8004cca: 681b ldr r3, [r3, #0] 8004ccc: 68da ldr r2, [r3, #12] 8004cce: 687b ldr r3, [r7, #4] 8004cd0: 681b ldr r3, [r3, #0] 8004cd2: f022 0280 bic.w r2, r2, #128 ; 0x80 8004cd6: 60da str r2, [r3, #12] /* Enable the UART Transmit Complete Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_TC); 8004cd8: 687b ldr r3, [r7, #4] 8004cda: 681b ldr r3, [r3, #0] 8004cdc: 68da ldr r2, [r3, #12] 8004cde: 687b ldr r3, [r7, #4] 8004ce0: 681b ldr r3, [r3, #0] 8004ce2: f042 0240 orr.w r2, r2, #64 ; 0x40 8004ce6: 60da str r2, [r3, #12] } return HAL_OK; 8004ce8: 2300 movs r3, #0 8004cea: e000 b.n 8004cee } else { return HAL_BUSY; 8004cec: 2302 movs r3, #2 } } 8004cee: 4618 mov r0, r3 8004cf0: 3714 adds r7, #20 8004cf2: 46bd mov sp, r7 8004cf4: bc80 pop {r7} 8004cf6: 4770 bx lr 08004cf8 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) { 8004cf8: b580 push {r7, lr} 8004cfa: b082 sub sp, #8 8004cfc: af00 add r7, sp, #0 8004cfe: 6078 str r0, [r7, #4] /* Disable the UART Transmit Complete Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TC); 8004d00: 687b ldr r3, [r7, #4] 8004d02: 681b ldr r3, [r3, #0] 8004d04: 68da ldr r2, [r3, #12] 8004d06: 687b ldr r3, [r7, #4] 8004d08: 681b ldr r3, [r3, #0] 8004d0a: f022 0240 bic.w r2, r2, #64 ; 0x40 8004d0e: 60da str r2, [r3, #12] /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8004d10: 687b ldr r3, [r7, #4] 8004d12: 2220 movs r2, #32 8004d14: f883 2039 strb.w r2, [r3, #57] ; 0x39 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); 8004d18: 6878 ldr r0, [r7, #4] 8004d1a: f7ff fe21 bl 8004960 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return HAL_OK; 8004d1e: 2300 movs r3, #0 } 8004d20: 4618 mov r0, r3 8004d22: 3708 adds r7, #8 8004d24: 46bd mov sp, r7 8004d26: bd80 pop {r7, pc} 08004d28 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) { 8004d28: b580 push {r7, lr} 8004d2a: b084 sub sp, #16 8004d2c: af00 add r7, sp, #0 8004d2e: 6078 str r0, [r7, #4] uint16_t *tmp; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 8004d30: 687b ldr r3, [r7, #4] 8004d32: f893 303a ldrb.w r3, [r3, #58] ; 0x3a 8004d36: b2db uxtb r3, r3 8004d38: 2b22 cmp r3, #34 ; 0x22 8004d3a: d171 bne.n 8004e20 { if (huart->Init.WordLength == UART_WORDLENGTH_9B) 8004d3c: 687b ldr r3, [r7, #4] 8004d3e: 689b ldr r3, [r3, #8] 8004d40: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8004d44: d123 bne.n 8004d8e { tmp = (uint16_t *) huart->pRxBuffPtr; 8004d46: 687b ldr r3, [r7, #4] 8004d48: 6a9b ldr r3, [r3, #40] ; 0x28 8004d4a: 60fb str r3, [r7, #12] if (huart->Init.Parity == UART_PARITY_NONE) 8004d4c: 687b ldr r3, [r7, #4] 8004d4e: 691b ldr r3, [r3, #16] 8004d50: 2b00 cmp r3, #0 8004d52: d10e bne.n 8004d72 { *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); 8004d54: 687b ldr r3, [r7, #4] 8004d56: 681b ldr r3, [r3, #0] 8004d58: 685b ldr r3, [r3, #4] 8004d5a: b29b uxth r3, r3 8004d5c: f3c3 0308 ubfx r3, r3, #0, #9 8004d60: b29a uxth r2, r3 8004d62: 68fb ldr r3, [r7, #12] 8004d64: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 8004d66: 687b ldr r3, [r7, #4] 8004d68: 6a9b ldr r3, [r3, #40] ; 0x28 8004d6a: 1c9a adds r2, r3, #2 8004d6c: 687b ldr r3, [r7, #4] 8004d6e: 629a str r2, [r3, #40] ; 0x28 8004d70: e029 b.n 8004dc6 } else { *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF); 8004d72: 687b ldr r3, [r7, #4] 8004d74: 681b ldr r3, [r3, #0] 8004d76: 685b ldr r3, [r3, #4] 8004d78: b29b uxth r3, r3 8004d7a: b2db uxtb r3, r3 8004d7c: b29a uxth r2, r3 8004d7e: 68fb ldr r3, [r7, #12] 8004d80: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 1U; 8004d82: 687b ldr r3, [r7, #4] 8004d84: 6a9b ldr r3, [r3, #40] ; 0x28 8004d86: 1c5a adds r2, r3, #1 8004d88: 687b ldr r3, [r7, #4] 8004d8a: 629a str r2, [r3, #40] ; 0x28 8004d8c: e01b b.n 8004dc6 } } else { if (huart->Init.Parity == UART_PARITY_NONE) 8004d8e: 687b ldr r3, [r7, #4] 8004d90: 691b ldr r3, [r3, #16] 8004d92: 2b00 cmp r3, #0 8004d94: d10a bne.n 8004dac { *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); 8004d96: 687b ldr r3, [r7, #4] 8004d98: 681b ldr r3, [r3, #0] 8004d9a: 6858 ldr r0, [r3, #4] 8004d9c: 687b ldr r3, [r7, #4] 8004d9e: 6a9b ldr r3, [r3, #40] ; 0x28 8004da0: 1c59 adds r1, r3, #1 8004da2: 687a ldr r2, [r7, #4] 8004da4: 6291 str r1, [r2, #40] ; 0x28 8004da6: b2c2 uxtb r2, r0 8004da8: 701a strb r2, [r3, #0] 8004daa: e00c b.n 8004dc6 } else { *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); 8004dac: 687b ldr r3, [r7, #4] 8004dae: 681b ldr r3, [r3, #0] 8004db0: 685b ldr r3, [r3, #4] 8004db2: b2da uxtb r2, r3 8004db4: 687b ldr r3, [r7, #4] 8004db6: 6a9b ldr r3, [r3, #40] ; 0x28 8004db8: 1c58 adds r0, r3, #1 8004dba: 6879 ldr r1, [r7, #4] 8004dbc: 6288 str r0, [r1, #40] ; 0x28 8004dbe: f002 027f and.w r2, r2, #127 ; 0x7f 8004dc2: b2d2 uxtb r2, r2 8004dc4: 701a strb r2, [r3, #0] } } if (--huart->RxXferCount == 0U) 8004dc6: 687b ldr r3, [r7, #4] 8004dc8: 8ddb ldrh r3, [r3, #46] ; 0x2e 8004dca: b29b uxth r3, r3 8004dcc: 3b01 subs r3, #1 8004dce: b29b uxth r3, r3 8004dd0: 687a ldr r2, [r7, #4] 8004dd2: 4619 mov r1, r3 8004dd4: 85d1 strh r1, [r2, #46] ; 0x2e 8004dd6: 2b00 cmp r3, #0 8004dd8: d120 bne.n 8004e1c { /* Disable the UART Data Register not empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); 8004dda: 687b ldr r3, [r7, #4] 8004ddc: 681b ldr r3, [r3, #0] 8004dde: 68da ldr r2, [r3, #12] 8004de0: 687b ldr r3, [r7, #4] 8004de2: 681b ldr r3, [r3, #0] 8004de4: f022 0220 bic.w r2, r2, #32 8004de8: 60da str r2, [r3, #12] /* Disable the UART Parity Error Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_PE); 8004dea: 687b ldr r3, [r7, #4] 8004dec: 681b ldr r3, [r3, #0] 8004dee: 68da ldr r2, [r3, #12] 8004df0: 687b ldr r3, [r7, #4] 8004df2: 681b ldr r3, [r3, #0] 8004df4: f422 7280 bic.w r2, r2, #256 ; 0x100 8004df8: 60da str r2, [r3, #12] /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); 8004dfa: 687b ldr r3, [r7, #4] 8004dfc: 681b ldr r3, [r3, #0] 8004dfe: 695a ldr r2, [r3, #20] 8004e00: 687b ldr r3, [r7, #4] 8004e02: 681b ldr r3, [r3, #0] 8004e04: f022 0201 bic.w r2, r2, #1 8004e08: 615a str r2, [r3, #20] /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8004e0a: 687b ldr r3, [r7, #4] 8004e0c: 2220 movs r2, #32 8004e0e: f883 203a strb.w r2, [r3, #58] ; 0x3a #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 8004e12: 6878 ldr r0, [r7, #4] 8004e14: f7fc fde0 bl 80019d8 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return HAL_OK; 8004e18: 2300 movs r3, #0 8004e1a: e002 b.n 8004e22 } return HAL_OK; 8004e1c: 2300 movs r3, #0 8004e1e: e000 b.n 8004e22 } else { return HAL_BUSY; 8004e20: 2302 movs r3, #2 } } 8004e22: 4618 mov r0, r3 8004e24: 3710 adds r7, #16 8004e26: 46bd mov sp, r7 8004e28: bd80 pop {r7, pc} ... 08004e2c : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_SetConfig(UART_HandleTypeDef *huart) { 8004e2c: b580 push {r7, lr} 8004e2e: b084 sub sp, #16 8004e30: af00 add r7, sp, #0 8004e32: 6078 str r0, [r7, #4] assert_param(IS_UART_MODE(huart->Init.Mode)); /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 8004e34: 687b ldr r3, [r7, #4] 8004e36: 681b ldr r3, [r3, #0] 8004e38: 691b ldr r3, [r3, #16] 8004e3a: f423 5140 bic.w r1, r3, #12288 ; 0x3000 8004e3e: 687b ldr r3, [r7, #4] 8004e40: 68da ldr r2, [r3, #12] 8004e42: 687b ldr r3, [r7, #4] 8004e44: 681b ldr r3, [r3, #0] 8004e46: 430a orrs r2, r1 8004e48: 611a str r2, [r3, #16] Set PCE and PS bits according to huart->Init.Parity value Set TE and RE bits according to huart->Init.Mode value Set OVER8 bit according to huart->Init.OverSampling value */ #if defined(USART_CR1_OVER8) tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; 8004e4a: 687b ldr r3, [r7, #4] 8004e4c: 689a ldr r2, [r3, #8] 8004e4e: 687b ldr r3, [r7, #4] 8004e50: 691b ldr r3, [r3, #16] 8004e52: 431a orrs r2, r3 8004e54: 687b ldr r3, [r7, #4] 8004e56: 695b ldr r3, [r3, #20] 8004e58: 431a orrs r2, r3 8004e5a: 687b ldr r3, [r7, #4] 8004e5c: 69db ldr r3, [r3, #28] 8004e5e: 4313 orrs r3, r2 8004e60: 60fb str r3, [r7, #12] MODIFY_REG(huart->Instance->CR1, 8004e62: 687b ldr r3, [r7, #4] 8004e64: 681b ldr r3, [r3, #0] 8004e66: 68db ldr r3, [r3, #12] 8004e68: f423 4316 bic.w r3, r3, #38400 ; 0x9600 8004e6c: f023 030c bic.w r3, r3, #12 8004e70: 687a ldr r2, [r7, #4] 8004e72: 6812 ldr r2, [r2, #0] 8004e74: 68f9 ldr r1, [r7, #12] 8004e76: 430b orrs r3, r1 8004e78: 60d3 str r3, [r2, #12] tmpreg); #endif /* USART_CR1_OVER8 */ /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); 8004e7a: 687b ldr r3, [r7, #4] 8004e7c: 681b ldr r3, [r3, #0] 8004e7e: 695b ldr r3, [r3, #20] 8004e80: f423 7140 bic.w r1, r3, #768 ; 0x300 8004e84: 687b ldr r3, [r7, #4] 8004e86: 699a ldr r2, [r3, #24] 8004e88: 687b ldr r3, [r7, #4] 8004e8a: 681b ldr r3, [r3, #0] 8004e8c: 430a orrs r2, r1 8004e8e: 615a str r2, [r3, #20] #if defined(USART_CR1_OVER8) /* Check the Over Sampling */ if(huart->Init.OverSampling == UART_OVERSAMPLING_8) 8004e90: 687b ldr r3, [r7, #4] 8004e92: 69db ldr r3, [r3, #28] 8004e94: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 8004e98: f040 80a5 bne.w 8004fe6 { /*-------------------------- USART BRR Configuration ---------------------*/ if(huart->Instance == USART1) 8004e9c: 687b ldr r3, [r7, #4] 8004e9e: 681b ldr r3, [r3, #0] 8004ea0: 4aa4 ldr r2, [pc, #656] ; (8005134 ) 8004ea2: 4293 cmp r3, r2 8004ea4: d14f bne.n 8004f46 { pclk = HAL_RCC_GetPCLK2Freq(); 8004ea6: f7fe fe8d bl 8003bc4 8004eaa: 60b8 str r0, [r7, #8] huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate); 8004eac: 68ba ldr r2, [r7, #8] 8004eae: 4613 mov r3, r2 8004eb0: 009b lsls r3, r3, #2 8004eb2: 4413 add r3, r2 8004eb4: 009a lsls r2, r3, #2 8004eb6: 441a add r2, r3 8004eb8: 687b ldr r3, [r7, #4] 8004eba: 685b ldr r3, [r3, #4] 8004ebc: 005b lsls r3, r3, #1 8004ebe: fbb2 f3f3 udiv r3, r2, r3 8004ec2: 4a9d ldr r2, [pc, #628] ; (8005138 ) 8004ec4: fba2 2303 umull r2, r3, r2, r3 8004ec8: 095b lsrs r3, r3, #5 8004eca: 0119 lsls r1, r3, #4 8004ecc: 68ba ldr r2, [r7, #8] 8004ece: 4613 mov r3, r2 8004ed0: 009b lsls r3, r3, #2 8004ed2: 4413 add r3, r2 8004ed4: 009a lsls r2, r3, #2 8004ed6: 441a add r2, r3 8004ed8: 687b ldr r3, [r7, #4] 8004eda: 685b ldr r3, [r3, #4] 8004edc: 005b lsls r3, r3, #1 8004ede: fbb2 f2f3 udiv r2, r2, r3 8004ee2: 4b95 ldr r3, [pc, #596] ; (8005138 ) 8004ee4: fba3 0302 umull r0, r3, r3, r2 8004ee8: 095b lsrs r3, r3, #5 8004eea: 2064 movs r0, #100 ; 0x64 8004eec: fb00 f303 mul.w r3, r0, r3 8004ef0: 1ad3 subs r3, r2, r3 8004ef2: 00db lsls r3, r3, #3 8004ef4: 3332 adds r3, #50 ; 0x32 8004ef6: 4a90 ldr r2, [pc, #576] ; (8005138 ) 8004ef8: fba2 2303 umull r2, r3, r2, r3 8004efc: 095b lsrs r3, r3, #5 8004efe: 005b lsls r3, r3, #1 8004f00: f403 73f8 and.w r3, r3, #496 ; 0x1f0 8004f04: 4419 add r1, r3 8004f06: 68ba ldr r2, [r7, #8] 8004f08: 4613 mov r3, r2 8004f0a: 009b lsls r3, r3, #2 8004f0c: 4413 add r3, r2 8004f0e: 009a lsls r2, r3, #2 8004f10: 441a add r2, r3 8004f12: 687b ldr r3, [r7, #4] 8004f14: 685b ldr r3, [r3, #4] 8004f16: 005b lsls r3, r3, #1 8004f18: fbb2 f2f3 udiv r2, r2, r3 8004f1c: 4b86 ldr r3, [pc, #536] ; (8005138 ) 8004f1e: fba3 0302 umull r0, r3, r3, r2 8004f22: 095b lsrs r3, r3, #5 8004f24: 2064 movs r0, #100 ; 0x64 8004f26: fb00 f303 mul.w r3, r0, r3 8004f2a: 1ad3 subs r3, r2, r3 8004f2c: 00db lsls r3, r3, #3 8004f2e: 3332 adds r3, #50 ; 0x32 8004f30: 4a81 ldr r2, [pc, #516] ; (8005138 ) 8004f32: fba2 2303 umull r2, r3, r2, r3 8004f36: 095b lsrs r3, r3, #5 8004f38: f003 0207 and.w r2, r3, #7 8004f3c: 687b ldr r3, [r7, #4] 8004f3e: 681b ldr r3, [r3, #0] 8004f40: 440a add r2, r1 8004f42: 609a str r2, [r3, #8] { pclk = HAL_RCC_GetPCLK1Freq(); huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); } #endif /* USART_CR1_OVER8 */ } 8004f44: e0f1 b.n 800512a pclk = HAL_RCC_GetPCLK1Freq(); 8004f46: f7fe fe29 bl 8003b9c 8004f4a: 60b8 str r0, [r7, #8] huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate); 8004f4c: 68ba ldr r2, [r7, #8] 8004f4e: 4613 mov r3, r2 8004f50: 009b lsls r3, r3, #2 8004f52: 4413 add r3, r2 8004f54: 009a lsls r2, r3, #2 8004f56: 441a add r2, r3 8004f58: 687b ldr r3, [r7, #4] 8004f5a: 685b ldr r3, [r3, #4] 8004f5c: 005b lsls r3, r3, #1 8004f5e: fbb2 f3f3 udiv r3, r2, r3 8004f62: 4a75 ldr r2, [pc, #468] ; (8005138 ) 8004f64: fba2 2303 umull r2, r3, r2, r3 8004f68: 095b lsrs r3, r3, #5 8004f6a: 0119 lsls r1, r3, #4 8004f6c: 68ba ldr r2, [r7, #8] 8004f6e: 4613 mov r3, r2 8004f70: 009b lsls r3, r3, #2 8004f72: 4413 add r3, r2 8004f74: 009a lsls r2, r3, #2 8004f76: 441a add r2, r3 8004f78: 687b ldr r3, [r7, #4] 8004f7a: 685b ldr r3, [r3, #4] 8004f7c: 005b lsls r3, r3, #1 8004f7e: fbb2 f2f3 udiv r2, r2, r3 8004f82: 4b6d ldr r3, [pc, #436] ; (8005138 ) 8004f84: fba3 0302 umull r0, r3, r3, r2 8004f88: 095b lsrs r3, r3, #5 8004f8a: 2064 movs r0, #100 ; 0x64 8004f8c: fb00 f303 mul.w r3, r0, r3 8004f90: 1ad3 subs r3, r2, r3 8004f92: 00db lsls r3, r3, #3 8004f94: 3332 adds r3, #50 ; 0x32 8004f96: 4a68 ldr r2, [pc, #416] ; (8005138 ) 8004f98: fba2 2303 umull r2, r3, r2, r3 8004f9c: 095b lsrs r3, r3, #5 8004f9e: 005b lsls r3, r3, #1 8004fa0: f403 73f8 and.w r3, r3, #496 ; 0x1f0 8004fa4: 4419 add r1, r3 8004fa6: 68ba ldr r2, [r7, #8] 8004fa8: 4613 mov r3, r2 8004faa: 009b lsls r3, r3, #2 8004fac: 4413 add r3, r2 8004fae: 009a lsls r2, r3, #2 8004fb0: 441a add r2, r3 8004fb2: 687b ldr r3, [r7, #4] 8004fb4: 685b ldr r3, [r3, #4] 8004fb6: 005b lsls r3, r3, #1 8004fb8: fbb2 f2f3 udiv r2, r2, r3 8004fbc: 4b5e ldr r3, [pc, #376] ; (8005138 ) 8004fbe: fba3 0302 umull r0, r3, r3, r2 8004fc2: 095b lsrs r3, r3, #5 8004fc4: 2064 movs r0, #100 ; 0x64 8004fc6: fb00 f303 mul.w r3, r0, r3 8004fca: 1ad3 subs r3, r2, r3 8004fcc: 00db lsls r3, r3, #3 8004fce: 3332 adds r3, #50 ; 0x32 8004fd0: 4a59 ldr r2, [pc, #356] ; (8005138 ) 8004fd2: fba2 2303 umull r2, r3, r2, r3 8004fd6: 095b lsrs r3, r3, #5 8004fd8: f003 0207 and.w r2, r3, #7 8004fdc: 687b ldr r3, [r7, #4] 8004fde: 681b ldr r3, [r3, #0] 8004fe0: 440a add r2, r1 8004fe2: 609a str r2, [r3, #8] } 8004fe4: e0a1 b.n 800512a if(huart->Instance == USART1) 8004fe6: 687b ldr r3, [r7, #4] 8004fe8: 681b ldr r3, [r3, #0] 8004fea: 4a52 ldr r2, [pc, #328] ; (8005134 ) 8004fec: 4293 cmp r3, r2 8004fee: d14e bne.n 800508e pclk = HAL_RCC_GetPCLK2Freq(); 8004ff0: f7fe fde8 bl 8003bc4 8004ff4: 60b8 str r0, [r7, #8] huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); 8004ff6: 68ba ldr r2, [r7, #8] 8004ff8: 4613 mov r3, r2 8004ffa: 009b lsls r3, r3, #2 8004ffc: 4413 add r3, r2 8004ffe: 009a lsls r2, r3, #2 8005000: 441a add r2, r3 8005002: 687b ldr r3, [r7, #4] 8005004: 685b ldr r3, [r3, #4] 8005006: 009b lsls r3, r3, #2 8005008: fbb2 f3f3 udiv r3, r2, r3 800500c: 4a4a ldr r2, [pc, #296] ; (8005138 ) 800500e: fba2 2303 umull r2, r3, r2, r3 8005012: 095b lsrs r3, r3, #5 8005014: 0119 lsls r1, r3, #4 8005016: 68ba ldr r2, [r7, #8] 8005018: 4613 mov r3, r2 800501a: 009b lsls r3, r3, #2 800501c: 4413 add r3, r2 800501e: 009a lsls r2, r3, #2 8005020: 441a add r2, r3 8005022: 687b ldr r3, [r7, #4] 8005024: 685b ldr r3, [r3, #4] 8005026: 009b lsls r3, r3, #2 8005028: fbb2 f2f3 udiv r2, r2, r3 800502c: 4b42 ldr r3, [pc, #264] ; (8005138 ) 800502e: fba3 0302 umull r0, r3, r3, r2 8005032: 095b lsrs r3, r3, #5 8005034: 2064 movs r0, #100 ; 0x64 8005036: fb00 f303 mul.w r3, r0, r3 800503a: 1ad3 subs r3, r2, r3 800503c: 011b lsls r3, r3, #4 800503e: 3332 adds r3, #50 ; 0x32 8005040: 4a3d ldr r2, [pc, #244] ; (8005138 ) 8005042: fba2 2303 umull r2, r3, r2, r3 8005046: 095b lsrs r3, r3, #5 8005048: f003 03f0 and.w r3, r3, #240 ; 0xf0 800504c: 4419 add r1, r3 800504e: 68ba ldr r2, [r7, #8] 8005050: 4613 mov r3, r2 8005052: 009b lsls r3, r3, #2 8005054: 4413 add r3, r2 8005056: 009a lsls r2, r3, #2 8005058: 441a add r2, r3 800505a: 687b ldr r3, [r7, #4] 800505c: 685b ldr r3, [r3, #4] 800505e: 009b lsls r3, r3, #2 8005060: fbb2 f2f3 udiv r2, r2, r3 8005064: 4b34 ldr r3, [pc, #208] ; (8005138 ) 8005066: fba3 0302 umull r0, r3, r3, r2 800506a: 095b lsrs r3, r3, #5 800506c: 2064 movs r0, #100 ; 0x64 800506e: fb00 f303 mul.w r3, r0, r3 8005072: 1ad3 subs r3, r2, r3 8005074: 011b lsls r3, r3, #4 8005076: 3332 adds r3, #50 ; 0x32 8005078: 4a2f ldr r2, [pc, #188] ; (8005138 ) 800507a: fba2 2303 umull r2, r3, r2, r3 800507e: 095b lsrs r3, r3, #5 8005080: f003 020f and.w r2, r3, #15 8005084: 687b ldr r3, [r7, #4] 8005086: 681b ldr r3, [r3, #0] 8005088: 440a add r2, r1 800508a: 609a str r2, [r3, #8] } 800508c: e04d b.n 800512a pclk = HAL_RCC_GetPCLK1Freq(); 800508e: f7fe fd85 bl 8003b9c 8005092: 60b8 str r0, [r7, #8] huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); 8005094: 68ba ldr r2, [r7, #8] 8005096: 4613 mov r3, r2 8005098: 009b lsls r3, r3, #2 800509a: 4413 add r3, r2 800509c: 009a lsls r2, r3, #2 800509e: 441a add r2, r3 80050a0: 687b ldr r3, [r7, #4] 80050a2: 685b ldr r3, [r3, #4] 80050a4: 009b lsls r3, r3, #2 80050a6: fbb2 f3f3 udiv r3, r2, r3 80050aa: 4a23 ldr r2, [pc, #140] ; (8005138 ) 80050ac: fba2 2303 umull r2, r3, r2, r3 80050b0: 095b lsrs r3, r3, #5 80050b2: 0119 lsls r1, r3, #4 80050b4: 68ba ldr r2, [r7, #8] 80050b6: 4613 mov r3, r2 80050b8: 009b lsls r3, r3, #2 80050ba: 4413 add r3, r2 80050bc: 009a lsls r2, r3, #2 80050be: 441a add r2, r3 80050c0: 687b ldr r3, [r7, #4] 80050c2: 685b ldr r3, [r3, #4] 80050c4: 009b lsls r3, r3, #2 80050c6: fbb2 f2f3 udiv r2, r2, r3 80050ca: 4b1b ldr r3, [pc, #108] ; (8005138 ) 80050cc: fba3 0302 umull r0, r3, r3, r2 80050d0: 095b lsrs r3, r3, #5 80050d2: 2064 movs r0, #100 ; 0x64 80050d4: fb00 f303 mul.w r3, r0, r3 80050d8: 1ad3 subs r3, r2, r3 80050da: 011b lsls r3, r3, #4 80050dc: 3332 adds r3, #50 ; 0x32 80050de: 4a16 ldr r2, [pc, #88] ; (8005138 ) 80050e0: fba2 2303 umull r2, r3, r2, r3 80050e4: 095b lsrs r3, r3, #5 80050e6: f003 03f0 and.w r3, r3, #240 ; 0xf0 80050ea: 4419 add r1, r3 80050ec: 68ba ldr r2, [r7, #8] 80050ee: 4613 mov r3, r2 80050f0: 009b lsls r3, r3, #2 80050f2: 4413 add r3, r2 80050f4: 009a lsls r2, r3, #2 80050f6: 441a add r2, r3 80050f8: 687b ldr r3, [r7, #4] 80050fa: 685b ldr r3, [r3, #4] 80050fc: 009b lsls r3, r3, #2 80050fe: fbb2 f2f3 udiv r2, r2, r3 8005102: 4b0d ldr r3, [pc, #52] ; (8005138 ) 8005104: fba3 0302 umull r0, r3, r3, r2 8005108: 095b lsrs r3, r3, #5 800510a: 2064 movs r0, #100 ; 0x64 800510c: fb00 f303 mul.w r3, r0, r3 8005110: 1ad3 subs r3, r2, r3 8005112: 011b lsls r3, r3, #4 8005114: 3332 adds r3, #50 ; 0x32 8005116: 4a08 ldr r2, [pc, #32] ; (8005138 ) 8005118: fba2 2303 umull r2, r3, r2, r3 800511c: 095b lsrs r3, r3, #5 800511e: f003 020f and.w r2, r3, #15 8005122: 687b ldr r3, [r7, #4] 8005124: 681b ldr r3, [r3, #0] 8005126: 440a add r2, r1 8005128: 609a str r2, [r3, #8] } 800512a: bf00 nop 800512c: 3710 adds r7, #16 800512e: 46bd mov sp, r7 8005130: bd80 pop {r7, pc} 8005132: bf00 nop 8005134: 40013800 .word 0x40013800 8005138: 51eb851f .word 0x51eb851f 0800513c <_write>: /* USER CODE END PFP */ /* Private user code ---------------------------------------------------------*/ /* USER CODE BEGIN 0 */ int _write (int file, uint8_t *ptr, uint16_t len) { 800513c: b580 push {r7, lr} 800513e: b084 sub sp, #16 8005140: af00 add r7, sp, #0 8005142: 60f8 str r0, [r7, #12] 8005144: 60b9 str r1, [r7, #8] 8005146: 4613 mov r3, r2 8005148: 80fb strh r3, [r7, #6] #if 0 // PYJ.2020.06.03_BEGIN -- HAL_UART_Transmit(&hTest, ptr, len,10); #else HAL_UART_Transmit(&hTerminal, ptr, len,10); 800514a: 88fa ldrh r2, [r7, #6] 800514c: 230a movs r3, #10 800514e: 68b9 ldr r1, [r7, #8] 8005150: 4803 ldr r0, [pc, #12] ; (8005160 <_write+0x24>) 8005152: f7ff f930 bl 80043b6 #endif // PYJ.2020.06.03_END -- return len; 8005156: 88fb ldrh r3, [r7, #6] } 8005158: 4618 mov r0, r3 800515a: 3710 adds r7, #16 800515c: 46bd mov sp, r7 800515e: bd80 pop {r7, pc} 8005160: 20000954 .word 0x20000954 08005164
: /** * @brief The application entry point. * @retval int */ int main(void) { 8005164: b580 push {r7, lr} 8005166: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 8005168: f7fc fd60 bl 8001c2c /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 800516c: f000 f846 bl 80051fc /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8005170: f000 f9e0 bl 8005534 MX_DMA_Init(); 8005174: f000 f9c8 bl 8005508 MX_ADC1_Init(); 8005178: f000 f8e0 bl 800533c MX_TIM6_Init(); 800517c: f000 f93a bl 80053f4 MX_USART1_UART_Init(); 8005180: f000 f96e bl 8005460 MX_USART3_UART_Init(); 8005184: f000 f996 bl 80054b4 /* Initialize interrupts */ MX_NVIC_Init(); 8005188: f000 f88c bl 80052a4 /* USER CODE BEGIN 2 */ HAL_TIM_Base_Start_IT(&htim6); 800518c: 4812 ldr r0, [pc, #72] ; (80051d8 ) 800518e: f7fe fea0 bl 8003ed2 setbuf(stdout, NULL); 8005192: 4b12 ldr r3, [pc, #72] ; (80051dc ) 8005194: 681b ldr r3, [r3, #0] 8005196: 689b ldr r3, [r3, #8] 8005198: 2100 movs r1, #0 800519a: 4618 mov r0, r3 800519c: f001 fba6 bl 80068ec InitUartQueue(&MainQueue); 80051a0: 480f ldr r0, [pc, #60] ; (80051e0 ) 80051a2: f7fc fbf1 bl 8001988 ADC_Initialize(); 80051a6: f7fc f917 bl 80013d8 #if 1 // PYJ.2020.05.06_BEGIN -- printf("****************************************\r\n"); 80051aa: 480e ldr r0, [pc, #56] ; (80051e4 ) 80051ac: f001 fb96 bl 80068dc printf("NESSLAB Project\r\n"); 80051b0: 480d ldr r0, [pc, #52] ; (80051e8 ) 80051b2: f001 fb93 bl 80068dc printf("Build at %s %s\r\n", __DATE__, __TIME__); 80051b6: 4a0d ldr r2, [pc, #52] ; (80051ec ) 80051b8: 490d ldr r1, [pc, #52] ; (80051f0 ) 80051ba: 480e ldr r0, [pc, #56] ; (80051f4 ) 80051bc: f001 fb1a bl 80067f4 printf("Copyright (c) 2020. BLUECELL\r\n"); 80051c0: 480d ldr r0, [pc, #52] ; (80051f8 ) 80051c2: f001 fb8b bl 80068dc printf("****************************************\r\n"); 80051c6: 4807 ldr r0, [pc, #28] ; (80051e4 ) 80051c8: f001 fb88 bl 80068dc while (1) { #if 1 // PYJ.2020.08.31_BEGIN -- Boot_LED_Toggle(); /*LED Check*/ 80051cc: f7fc fbc4 bl 8001958 Uart_Check(); /*Usart Rx*/ 80051d0: f7fc fce6 bl 8001ba0 Boot_LED_Toggle(); /*LED Check*/ 80051d4: e7fa b.n 80051cc 80051d6: bf00 nop 80051d8: 20000b14 .word 0x20000b14 80051dc: 2000000c .word 0x2000000c 80051e0: 2000074c .word 0x2000074c 80051e4: 08008b0c .word 0x08008b0c 80051e8: 08008b38 .word 0x08008b38 80051ec: 08008b4c .word 0x08008b4c 80051f0: 08008b58 .word 0x08008b58 80051f4: 08008b64 .word 0x08008b64 80051f8: 08008b78 .word 0x08008b78 080051fc : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 80051fc: b580 push {r7, lr} 80051fe: b092 sub sp, #72 ; 0x48 8005200: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8005202: f107 0320 add.w r3, r7, #32 8005206: 2228 movs r2, #40 ; 0x28 8005208: 2100 movs r1, #0 800520a: 4618 mov r0, r3 800520c: f000 fe9a bl 8005f44 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8005210: f107 030c add.w r3, r7, #12 8005214: 2200 movs r2, #0 8005216: 601a str r2, [r3, #0] 8005218: 605a str r2, [r3, #4] 800521a: 609a str r2, [r3, #8] 800521c: 60da str r2, [r3, #12] 800521e: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 8005220: 463b mov r3, r7 8005222: 2200 movs r2, #0 8005224: 601a str r2, [r3, #0] 8005226: 605a str r2, [r3, #4] 8005228: 609a str r2, [r3, #8] /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; 800522a: 2302 movs r3, #2 800522c: 623b str r3, [r7, #32] RCC_OscInitStruct.HSIState = RCC_HSI_ON; 800522e: 2301 movs r3, #1 8005230: 633b str r3, [r7, #48] ; 0x30 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 8005232: 2310 movs r3, #16 8005234: 637b str r3, [r7, #52] ; 0x34 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 8005236: 2302 movs r3, #2 8005238: 63fb str r3, [r7, #60] ; 0x3c RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2; 800523a: 2300 movs r3, #0 800523c: 643b str r3, [r7, #64] ; 0x40 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6; 800523e: f44f 1380 mov.w r3, #1048576 ; 0x100000 8005242: 647b str r3, [r7, #68] ; 0x44 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8005244: f107 0320 add.w r3, r7, #32 8005248: 4618 mov r0, r3 800524a: f7fe f901 bl 8003450 800524e: 4603 mov r3, r0 8005250: 2b00 cmp r3, #0 8005252: d001 beq.n 8005258 { Error_Handler(); 8005254: f000 faa8 bl 80057a8 } /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8005258: 230f movs r3, #15 800525a: 60fb str r3, [r7, #12] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 800525c: 2302 movs r3, #2 800525e: 613b str r3, [r7, #16] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 8005260: 2300 movs r3, #0 8005262: 617b str r3, [r7, #20] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 8005264: 2300 movs r3, #0 8005266: 61bb str r3, [r7, #24] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 8005268: 2300 movs r3, #0 800526a: 61fb str r3, [r7, #28] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) 800526c: f107 030c add.w r3, r7, #12 8005270: 2100 movs r1, #0 8005272: 4618 mov r0, r3 8005274: f7fe fb6c bl 8003950 8005278: 4603 mov r3, r0 800527a: 2b00 cmp r3, #0 800527c: d001 beq.n 8005282 { Error_Handler(); 800527e: f000 fa93 bl 80057a8 } PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; 8005282: 2302 movs r3, #2 8005284: 603b str r3, [r7, #0] PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV2; 8005286: 2300 movs r3, #0 8005288: 60bb str r3, [r7, #8] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 800528a: 463b mov r3, r7 800528c: 4618 mov r0, r3 800528e: f7fe fcf7 bl 8003c80 8005292: 4603 mov r3, r0 8005294: 2b00 cmp r3, #0 8005296: d001 beq.n 800529c { Error_Handler(); 8005298: f000 fa86 bl 80057a8 } } 800529c: bf00 nop 800529e: 3748 adds r7, #72 ; 0x48 80052a0: 46bd mov sp, r7 80052a2: bd80 pop {r7, pc} 080052a4 : /** * @brief NVIC Configuration. * @retval None */ static void MX_NVIC_Init(void) { 80052a4: b580 push {r7, lr} 80052a6: af00 add r7, sp, #0 /* ADC1_IRQn interrupt configuration */ HAL_NVIC_SetPriority(ADC1_IRQn, 0, 0); 80052a8: 2200 movs r2, #0 80052aa: 2100 movs r1, #0 80052ac: 2012 movs r0, #18 80052ae: f7fd fa9e bl 80027ee HAL_NVIC_EnableIRQ(ADC1_IRQn); 80052b2: 2012 movs r0, #18 80052b4: f7fd fab7 bl 8002826 /* USART1_IRQn interrupt configuration */ HAL_NVIC_SetPriority(USART1_IRQn, 0, 0); 80052b8: 2200 movs r2, #0 80052ba: 2100 movs r1, #0 80052bc: 2025 movs r0, #37 ; 0x25 80052be: f7fd fa96 bl 80027ee HAL_NVIC_EnableIRQ(USART1_IRQn); 80052c2: 2025 movs r0, #37 ; 0x25 80052c4: f7fd faaf bl 8002826 /* USART3_IRQn interrupt configuration */ HAL_NVIC_SetPriority(USART3_IRQn, 0, 0); 80052c8: 2200 movs r2, #0 80052ca: 2100 movs r1, #0 80052cc: 2027 movs r0, #39 ; 0x27 80052ce: f7fd fa8e bl 80027ee HAL_NVIC_EnableIRQ(USART3_IRQn); 80052d2: 2027 movs r0, #39 ; 0x27 80052d4: f7fd faa7 bl 8002826 /* TIM6_DAC_IRQn interrupt configuration */ HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 0, 0); 80052d8: 2200 movs r2, #0 80052da: 2100 movs r1, #0 80052dc: 2036 movs r0, #54 ; 0x36 80052de: f7fd fa86 bl 80027ee HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); 80052e2: 2036 movs r0, #54 ; 0x36 80052e4: f7fd fa9f bl 8002826 /* DMA1_Channel2_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel2_IRQn, 0, 0); 80052e8: 2200 movs r2, #0 80052ea: 2100 movs r1, #0 80052ec: 200c movs r0, #12 80052ee: f7fd fa7e bl 80027ee HAL_NVIC_EnableIRQ(DMA1_Channel2_IRQn); 80052f2: 200c movs r0, #12 80052f4: f7fd fa97 bl 8002826 /* DMA1_Channel4_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel4_IRQn, 0, 0); 80052f8: 2200 movs r2, #0 80052fa: 2100 movs r1, #0 80052fc: 200e movs r0, #14 80052fe: f7fd fa76 bl 80027ee HAL_NVIC_EnableIRQ(DMA1_Channel4_IRQn); 8005302: 200e movs r0, #14 8005304: f7fd fa8f bl 8002826 /* DMA1_Channel3_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel3_IRQn, 0, 0); 8005308: 2200 movs r2, #0 800530a: 2100 movs r1, #0 800530c: 200d movs r0, #13 800530e: f7fd fa6e bl 80027ee HAL_NVIC_EnableIRQ(DMA1_Channel3_IRQn); 8005312: 200d movs r0, #13 8005314: f7fd fa87 bl 8002826 /* DMA1_Channel1_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0); 8005318: 2200 movs r2, #0 800531a: 2100 movs r1, #0 800531c: 200b movs r0, #11 800531e: f7fd fa66 bl 80027ee HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn); 8005322: 200b movs r0, #11 8005324: f7fd fa7f bl 8002826 /* DMA1_Channel5_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel5_IRQn, 0, 0); 8005328: 2200 movs r2, #0 800532a: 2100 movs r1, #0 800532c: 200f movs r0, #15 800532e: f7fd fa5e bl 80027ee HAL_NVIC_EnableIRQ(DMA1_Channel5_IRQn); 8005332: 200f movs r0, #15 8005334: f7fd fa77 bl 8002826 } 8005338: bf00 nop 800533a: bd80 pop {r7, pc} 0800533c : * @brief ADC1 Initialization Function * @param None * @retval None */ static void MX_ADC1_Init(void) { 800533c: b580 push {r7, lr} 800533e: b084 sub sp, #16 8005340: af00 add r7, sp, #0 /* USER CODE BEGIN ADC1_Init 0 */ /* USER CODE END ADC1_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 8005342: 1d3b adds r3, r7, #4 8005344: 2200 movs r2, #0 8005346: 601a str r2, [r3, #0] 8005348: 605a str r2, [r3, #4] 800534a: 609a str r2, [r3, #8] /* USER CODE BEGIN ADC1_Init 1 */ /* USER CODE END ADC1_Init 1 */ /** Common config */ hadc1.Instance = ADC1; 800534c: 4b27 ldr r3, [pc, #156] ; (80053ec ) 800534e: 4a28 ldr r2, [pc, #160] ; (80053f0 ) 8005350: 601a str r2, [r3, #0] hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; 8005352: 4b26 ldr r3, [pc, #152] ; (80053ec ) 8005354: f44f 7280 mov.w r2, #256 ; 0x100 8005358: 609a str r2, [r3, #8] hadc1.Init.ContinuousConvMode = ENABLE; 800535a: 4b24 ldr r3, [pc, #144] ; (80053ec ) 800535c: 2201 movs r2, #1 800535e: 731a strb r2, [r3, #12] hadc1.Init.DiscontinuousConvMode = DISABLE; 8005360: 4b22 ldr r3, [pc, #136] ; (80053ec ) 8005362: 2200 movs r2, #0 8005364: 751a strb r2, [r3, #20] hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; 8005366: 4b21 ldr r3, [pc, #132] ; (80053ec ) 8005368: f44f 2260 mov.w r2, #917504 ; 0xe0000 800536c: 61da str r2, [r3, #28] hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; 800536e: 4b1f ldr r3, [pc, #124] ; (80053ec ) 8005370: 2200 movs r2, #0 8005372: 605a str r2, [r3, #4] hadc1.Init.NbrOfConversion = 3; 8005374: 4b1d ldr r3, [pc, #116] ; (80053ec ) 8005376: 2203 movs r2, #3 8005378: 611a str r2, [r3, #16] if (HAL_ADC_Init(&hadc1) != HAL_OK) 800537a: 481c ldr r0, [pc, #112] ; (80053ec ) 800537c: f7fc fca2 bl 8001cc4 8005380: 4603 mov r3, r0 8005382: 2b00 cmp r3, #0 8005384: d001 beq.n 800538a { Error_Handler(); 8005386: f000 fa0f bl 80057a8 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_0; 800538a: 2300 movs r3, #0 800538c: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_1; 800538e: 2301 movs r3, #1 8005390: 60bb str r3, [r7, #8] sConfig.SamplingTime = ADC_SAMPLETIME_239CYCLES_5; 8005392: 2307 movs r3, #7 8005394: 60fb str r3, [r7, #12] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8005396: 1d3b adds r3, r7, #4 8005398: 4619 mov r1, r3 800539a: 4814 ldr r0, [pc, #80] ; (80053ec ) 800539c: f7fc fee2 bl 8002164 80053a0: 4603 mov r3, r0 80053a2: 2b00 cmp r3, #0 80053a4: d001 beq.n 80053aa { Error_Handler(); 80053a6: f000 f9ff bl 80057a8 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_1; 80053aa: 2301 movs r3, #1 80053ac: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_2; 80053ae: 2302 movs r3, #2 80053b0: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 80053b2: 1d3b adds r3, r7, #4 80053b4: 4619 mov r1, r3 80053b6: 480d ldr r0, [pc, #52] ; (80053ec ) 80053b8: f7fc fed4 bl 8002164 80053bc: 4603 mov r3, r0 80053be: 2b00 cmp r3, #0 80053c0: d001 beq.n 80053c6 { Error_Handler(); 80053c2: f000 f9f1 bl 80057a8 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_3; 80053c6: 2303 movs r3, #3 80053c8: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_3; 80053ca: 2303 movs r3, #3 80053cc: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 80053ce: 1d3b adds r3, r7, #4 80053d0: 4619 mov r1, r3 80053d2: 4806 ldr r0, [pc, #24] ; (80053ec ) 80053d4: f7fc fec6 bl 8002164 80053d8: 4603 mov r3, r0 80053da: 2b00 cmp r3, #0 80053dc: d001 beq.n 80053e2 { Error_Handler(); 80053de: f000 f9e3 bl 80057a8 } /* USER CODE BEGIN ADC1_Init 2 */ /* USER CODE END ADC1_Init 2 */ } 80053e2: bf00 nop 80053e4: 3710 adds r7, #16 80053e6: 46bd mov sp, r7 80053e8: bd80 pop {r7, pc} 80053ea: bf00 nop 80053ec: 20000a1c .word 0x20000a1c 80053f0: 40012400 .word 0x40012400 080053f4 : * @brief TIM6 Initialization Function * @param None * @retval None */ static void MX_TIM6_Init(void) { 80053f4: b580 push {r7, lr} 80053f6: b082 sub sp, #8 80053f8: af00 add r7, sp, #0 /* USER CODE BEGIN TIM6_Init 0 */ /* USER CODE END TIM6_Init 0 */ TIM_MasterConfigTypeDef sMasterConfig = {0}; 80053fa: 463b mov r3, r7 80053fc: 2200 movs r2, #0 80053fe: 601a str r2, [r3, #0] 8005400: 605a str r2, [r3, #4] /* USER CODE BEGIN TIM6_Init 1 */ /* USER CODE END TIM6_Init 1 */ htim6.Instance = TIM6; 8005402: 4b15 ldr r3, [pc, #84] ; (8005458 ) 8005404: 4a15 ldr r2, [pc, #84] ; (800545c ) 8005406: 601a str r2, [r3, #0] htim6.Init.Prescaler = 2400-1; 8005408: 4b13 ldr r3, [pc, #76] ; (8005458 ) 800540a: f640 125f movw r2, #2399 ; 0x95f 800540e: 605a str r2, [r3, #4] htim6.Init.CounterMode = TIM_COUNTERMODE_UP; 8005410: 4b11 ldr r3, [pc, #68] ; (8005458 ) 8005412: 2200 movs r2, #0 8005414: 609a str r2, [r3, #8] htim6.Init.Period = 10; 8005416: 4b10 ldr r3, [pc, #64] ; (8005458 ) 8005418: 220a movs r2, #10 800541a: 60da str r2, [r3, #12] htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 800541c: 4b0e ldr r3, [pc, #56] ; (8005458 ) 800541e: 2200 movs r2, #0 8005420: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim6) != HAL_OK) 8005422: 480d ldr r0, [pc, #52] ; (8005458 ) 8005424: f7fe fd2a bl 8003e7c 8005428: 4603 mov r3, r0 800542a: 2b00 cmp r3, #0 800542c: d001 beq.n 8005432 { Error_Handler(); 800542e: f000 f9bb bl 80057a8 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8005432: 2300 movs r3, #0 8005434: 603b str r3, [r7, #0] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8005436: 2300 movs r3, #0 8005438: 607b str r3, [r7, #4] if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK) 800543a: 463b mov r3, r7 800543c: 4619 mov r1, r3 800543e: 4806 ldr r0, [pc, #24] ; (8005458 ) 8005440: f7fe ff16 bl 8004270 8005444: 4603 mov r3, r0 8005446: 2b00 cmp r3, #0 8005448: d001 beq.n 800544e { Error_Handler(); 800544a: f000 f9ad bl 80057a8 } /* USER CODE BEGIN TIM6_Init 2 */ /* USER CODE END TIM6_Init 2 */ } 800544e: bf00 nop 8005450: 3708 adds r7, #8 8005452: 46bd mov sp, r7 8005454: bd80 pop {r7, pc} 8005456: bf00 nop 8005458: 20000b14 .word 0x20000b14 800545c: 40001000 .word 0x40001000 08005460 : * @brief USART1 Initialization Function * @param None * @retval None */ static void MX_USART1_UART_Init(void) { 8005460: b580 push {r7, lr} 8005462: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 8005464: 4b11 ldr r3, [pc, #68] ; (80054ac ) 8005466: 4a12 ldr r2, [pc, #72] ; (80054b0 ) 8005468: 601a str r2, [r3, #0] huart1.Init.BaudRate = 115200; 800546a: 4b10 ldr r3, [pc, #64] ; (80054ac ) 800546c: f44f 32e1 mov.w r2, #115200 ; 0x1c200 8005470: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 8005472: 4b0e ldr r3, [pc, #56] ; (80054ac ) 8005474: 2200 movs r2, #0 8005476: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 8005478: 4b0c ldr r3, [pc, #48] ; (80054ac ) 800547a: 2200 movs r2, #0 800547c: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 800547e: 4b0b ldr r3, [pc, #44] ; (80054ac ) 8005480: 2200 movs r2, #0 8005482: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 8005484: 4b09 ldr r3, [pc, #36] ; (80054ac ) 8005486: 220c movs r2, #12 8005488: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800548a: 4b08 ldr r3, [pc, #32] ; (80054ac ) 800548c: 2200 movs r2, #0 800548e: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 8005490: 4b06 ldr r3, [pc, #24] ; (80054ac ) 8005492: 2200 movs r2, #0 8005494: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart1) != HAL_OK) 8005496: 4805 ldr r0, [pc, #20] ; (80054ac ) 8005498: f7fe ff40 bl 800431c 800549c: 4603 mov r3, r0 800549e: 2b00 cmp r3, #0 80054a0: d001 beq.n 80054a6 { Error_Handler(); 80054a2: f000 f981 bl 80057a8 } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 80054a6: bf00 nop 80054a8: bd80 pop {r7, pc} 80054aa: bf00 nop 80054ac: 20000a90 .word 0x20000a90 80054b0: 40013800 .word 0x40013800 080054b4 : * @brief USART3 Initialization Function * @param None * @retval None */ static void MX_USART3_UART_Init(void) { 80054b4: b580 push {r7, lr} 80054b6: af00 add r7, sp, #0 /* USER CODE END USART3_Init 0 */ /* USER CODE BEGIN USART3_Init 1 */ /* USER CODE END USART3_Init 1 */ huart3.Instance = USART3; 80054b8: 4b11 ldr r3, [pc, #68] ; (8005500 ) 80054ba: 4a12 ldr r2, [pc, #72] ; (8005504 ) 80054bc: 601a str r2, [r3, #0] huart3.Init.BaudRate = 115200; 80054be: 4b10 ldr r3, [pc, #64] ; (8005500 ) 80054c0: f44f 32e1 mov.w r2, #115200 ; 0x1c200 80054c4: 605a str r2, [r3, #4] huart3.Init.WordLength = UART_WORDLENGTH_8B; 80054c6: 4b0e ldr r3, [pc, #56] ; (8005500 ) 80054c8: 2200 movs r2, #0 80054ca: 609a str r2, [r3, #8] huart3.Init.StopBits = UART_STOPBITS_1; 80054cc: 4b0c ldr r3, [pc, #48] ; (8005500 ) 80054ce: 2200 movs r2, #0 80054d0: 60da str r2, [r3, #12] huart3.Init.Parity = UART_PARITY_NONE; 80054d2: 4b0b ldr r3, [pc, #44] ; (8005500 ) 80054d4: 2200 movs r2, #0 80054d6: 611a str r2, [r3, #16] huart3.Init.Mode = UART_MODE_TX_RX; 80054d8: 4b09 ldr r3, [pc, #36] ; (8005500 ) 80054da: 220c movs r2, #12 80054dc: 615a str r2, [r3, #20] huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE; 80054de: 4b08 ldr r3, [pc, #32] ; (8005500 ) 80054e0: 2200 movs r2, #0 80054e2: 619a str r2, [r3, #24] huart3.Init.OverSampling = UART_OVERSAMPLING_16; 80054e4: 4b06 ldr r3, [pc, #24] ; (8005500 ) 80054e6: 2200 movs r2, #0 80054e8: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart3) != HAL_OK) 80054ea: 4805 ldr r0, [pc, #20] ; (8005500 ) 80054ec: f7fe ff16 bl 800431c 80054f0: 4603 mov r3, r0 80054f2: 2b00 cmp r3, #0 80054f4: d001 beq.n 80054fa { Error_Handler(); 80054f6: f000 f957 bl 80057a8 } /* USER CODE BEGIN USART3_Init 2 */ /* USER CODE END USART3_Init 2 */ } 80054fa: bf00 nop 80054fc: bd80 pop {r7, pc} 80054fe: bf00 nop 8005500: 20000954 .word 0x20000954 8005504: 40004800 .word 0x40004800 08005508 : /** * Enable DMA controller clock */ static void MX_DMA_Init(void) { 8005508: b480 push {r7} 800550a: b083 sub sp, #12 800550c: af00 add r7, sp, #0 /* DMA controller clock enable */ __HAL_RCC_DMA1_CLK_ENABLE(); 800550e: 4b08 ldr r3, [pc, #32] ; (8005530 ) 8005510: 695b ldr r3, [r3, #20] 8005512: 4a07 ldr r2, [pc, #28] ; (8005530 ) 8005514: f043 0301 orr.w r3, r3, #1 8005518: 6153 str r3, [r2, #20] 800551a: 4b05 ldr r3, [pc, #20] ; (8005530 ) 800551c: 695b ldr r3, [r3, #20] 800551e: f003 0301 and.w r3, r3, #1 8005522: 607b str r3, [r7, #4] 8005524: 687b ldr r3, [r7, #4] } 8005526: bf00 nop 8005528: 370c adds r7, #12 800552a: 46bd mov sp, r7 800552c: bc80 pop {r7} 800552e: 4770 bx lr 8005530: 40021000 .word 0x40021000 08005534 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 8005534: b580 push {r7, lr} 8005536: b088 sub sp, #32 8005538: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 800553a: f107 0310 add.w r3, r7, #16 800553e: 2200 movs r2, #0 8005540: 601a str r2, [r3, #0] 8005542: 605a str r2, [r3, #4] 8005544: 609a str r2, [r3, #8] 8005546: 60da str r2, [r3, #12] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); 8005548: 4b40 ldr r3, [pc, #256] ; (800564c ) 800554a: 699b ldr r3, [r3, #24] 800554c: 4a3f ldr r2, [pc, #252] ; (800564c ) 800554e: f043 0310 orr.w r3, r3, #16 8005552: 6193 str r3, [r2, #24] 8005554: 4b3d ldr r3, [pc, #244] ; (800564c ) 8005556: 699b ldr r3, [r3, #24] 8005558: f003 0310 and.w r3, r3, #16 800555c: 60fb str r3, [r7, #12] 800555e: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 8005560: 4b3a ldr r3, [pc, #232] ; (800564c ) 8005562: 699b ldr r3, [r3, #24] 8005564: 4a39 ldr r2, [pc, #228] ; (800564c ) 8005566: f043 0304 orr.w r3, r3, #4 800556a: 6193 str r3, [r2, #24] 800556c: 4b37 ldr r3, [pc, #220] ; (800564c ) 800556e: 699b ldr r3, [r3, #24] 8005570: f003 0304 and.w r3, r3, #4 8005574: 60bb str r3, [r7, #8] 8005576: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOB_CLK_ENABLE(); 8005578: 4b34 ldr r3, [pc, #208] ; (800564c ) 800557a: 699b ldr r3, [r3, #24] 800557c: 4a33 ldr r2, [pc, #204] ; (800564c ) 800557e: f043 0308 orr.w r3, r3, #8 8005582: 6193 str r3, [r2, #24] 8005584: 4b31 ldr r3, [pc, #196] ; (800564c ) 8005586: 699b ldr r3, [r3, #24] 8005588: f003 0308 and.w r3, r3, #8 800558c: 607b str r3, [r7, #4] 800558e: 687b ldr r3, [r7, #4] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(BOOT_LED_GPIO_Port, BOOT_LED_Pin, GPIO_PIN_RESET); 8005590: 2200 movs r2, #0 8005592: f44f 4100 mov.w r1, #32768 ; 0x8000 8005596: 482e ldr r0, [pc, #184] ; (8005650 ) 8005598: f7fd ff29 bl 80033ee /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOA, PAU_RESERVED0_Pin|PAU_RESERVED1_Pin|AMP_EN_Pin, GPIO_PIN_RESET); 800559c: 2200 movs r2, #0 800559e: f44f 71e0 mov.w r1, #448 ; 0x1c0 80055a2: 482c ldr r0, [pc, #176] ; (8005654 ) 80055a4: f7fd ff23 bl 80033ee /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOB, PAU_RESERVED3_Pin|PAU_RESERVED2_Pin|PAU_RESET_Pin, GPIO_PIN_RESET); 80055a8: 2200 movs r2, #0 80055aa: f244 0103 movw r1, #16387 ; 0x4003 80055ae: 482a ldr r0, [pc, #168] ; (8005658 ) 80055b0: f7fd ff1d bl 80033ee /*Configure GPIO pin : BOOT_LED_Pin */ GPIO_InitStruct.Pin = BOOT_LED_Pin; 80055b4: f44f 4300 mov.w r3, #32768 ; 0x8000 80055b8: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80055ba: 2301 movs r3, #1 80055bc: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 80055be: 2300 movs r3, #0 80055c0: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80055c2: 2302 movs r3, #2 80055c4: 61fb str r3, [r7, #28] HAL_GPIO_Init(BOOT_LED_GPIO_Port, &GPIO_InitStruct); 80055c6: f107 0310 add.w r3, r7, #16 80055ca: 4619 mov r1, r3 80055cc: 4820 ldr r0, [pc, #128] ; (8005650 ) 80055ce: f7fd fd9d bl 800310c /*Configure GPIO pins : DC_FAIL_ALARM_Pin OVER_INPUT_ALARM_Pin OVER_TEMP_ALARM_Pin */ GPIO_InitStruct.Pin = DC_FAIL_ALARM_Pin|OVER_INPUT_ALARM_Pin|OVER_TEMP_ALARM_Pin; 80055d2: f641 0304 movw r3, #6148 ; 0x1804 80055d6: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80055d8: 2300 movs r3, #0 80055da: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 80055dc: 2300 movs r3, #0 80055de: 61bb str r3, [r7, #24] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80055e0: f107 0310 add.w r3, r7, #16 80055e4: 4619 mov r1, r3 80055e6: 481b ldr r0, [pc, #108] ; (8005654 ) 80055e8: f7fd fd90 bl 800310c /*Configure GPIO pins : PAU_RESERVED0_Pin PAU_RESERVED1_Pin AMP_EN_Pin */ GPIO_InitStruct.Pin = PAU_RESERVED0_Pin|PAU_RESERVED1_Pin|AMP_EN_Pin; 80055ec: f44f 73e0 mov.w r3, #448 ; 0x1c0 80055f0: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80055f2: 2301 movs r3, #1 80055f4: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 80055f6: 2300 movs r3, #0 80055f8: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80055fa: 2302 movs r3, #2 80055fc: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80055fe: f107 0310 add.w r3, r7, #16 8005602: 4619 mov r1, r3 8005604: 4813 ldr r0, [pc, #76] ; (8005654 ) 8005606: f7fd fd81 bl 800310c /*Configure GPIO pins : PAU_RESERVED3_Pin PAU_RESERVED2_Pin PAU_RESET_Pin */ GPIO_InitStruct.Pin = PAU_RESERVED3_Pin|PAU_RESERVED2_Pin|PAU_RESET_Pin; 800560a: f244 0303 movw r3, #16387 ; 0x4003 800560e: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8005610: 2301 movs r3, #1 8005612: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 8005614: 2300 movs r3, #0 8005616: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8005618: 2302 movs r3, #2 800561a: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800561c: f107 0310 add.w r3, r7, #16 8005620: 4619 mov r1, r3 8005622: 480d ldr r0, [pc, #52] ; (8005658 ) 8005624: f7fd fd72 bl 800310c /*Configure GPIO pins : OVER_POWER_ALARM_Pin VSWR_ALARM_Pin PAU_EN_Pin ALC_ALARM_Pin */ GPIO_InitStruct.Pin = OVER_POWER_ALARM_Pin|VSWR_ALARM_Pin|PAU_EN_Pin|ALC_ALARM_Pin; 8005628: f24b 0308 movw r3, #45064 ; 0xb008 800562c: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800562e: 2300 movs r3, #0 8005630: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 8005632: 2300 movs r3, #0 8005634: 61bb str r3, [r7, #24] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8005636: f107 0310 add.w r3, r7, #16 800563a: 4619 mov r1, r3 800563c: 4806 ldr r0, [pc, #24] ; (8005658 ) 800563e: f7fd fd65 bl 800310c } 8005642: bf00 nop 8005644: 3720 adds r7, #32 8005646: 46bd mov sp, r7 8005648: bd80 pop {r7, pc} 800564a: bf00 nop 800564c: 40021000 .word 0x40021000 8005650: 40011000 .word 0x40011000 8005654: 40010800 .word 0x40010800 8005658: 40010c00 .word 0x40010c00 0800565c : * a global variable "uwTick" used as application time base. * @param htim : TIM handle * @retval None */ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { 800565c: b580 push {r7, lr} 800565e: b082 sub sp, #8 8005660: af00 add r7, sp, #0 8005662: 6078 str r0, [r7, #4] /* USER CODE BEGIN Callback 0 */ /* USER CODE END Callback 0 */ if (htim->Instance == TIM2) { 8005664: 687b ldr r3, [r7, #4] 8005666: 681b ldr r3, [r3, #0] 8005668: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 800566c: d101 bne.n 8005672 HAL_IncTick(); 800566e: f7fc faeb bl 8001c48 } /* USER CODE BEGIN Callback 1 */ if(htim->Instance == TIM6){ 8005672: 687b ldr r3, [r7, #4] 8005674: 681b ldr r3, [r3, #0] 8005676: 4a3f ldr r2, [pc, #252] ; (8005774 ) 8005678: 4293 cmp r3, r2 800567a: d177 bne.n 800576c UartRxTimerCnt++; 800567c: 4b3e ldr r3, [pc, #248] ; (8005778 ) 800567e: 681b ldr r3, [r3, #0] 8005680: 3301 adds r3, #1 8005682: 4a3d ldr r2, [pc, #244] ; (8005778 ) 8005684: 6013 str r3, [r2, #0] LED_TimerCnt++; 8005686: 4b3d ldr r3, [pc, #244] ; (800577c ) 8005688: 681b ldr r3, [r3, #0] 800568a: 3301 adds r3, #1 800568c: 4a3b ldr r2, [pc, #236] ; (800577c ) 800568e: 6013 str r3, [r2, #0] TDD_125ms_Cnt++; 8005690: 4b3b ldr r3, [pc, #236] ; (8005780 ) 8005692: 681b ldr r3, [r3, #0] 8005694: 3301 adds r3, #1 8005696: 4a3a ldr r2, [pc, #232] ; (8005780 ) 8005698: 6013 str r3, [r2, #0] TestTimer++; 800569a: 4b3a ldr r3, [pc, #232] ; (8005784 ) 800569c: 681b ldr r3, [r3, #0] 800569e: 3301 adds r3, #1 80056a0: 4a38 ldr r2, [pc, #224] ; (8005784 ) 80056a2: 6013 str r3, [r2, #0] if(HAL_GPIO_ReadPin(DC_FAIL_ALARM_GPIO_Port, DC_FAIL_ALARM_Pin) == GPIO_PIN_SET) 80056a4: 2104 movs r1, #4 80056a6: 4838 ldr r0, [pc, #224] ; (8005788 ) 80056a8: f7fd fe8a bl 80033c0 80056ac: 4603 mov r3, r0 80056ae: 2b01 cmp r3, #1 80056b0: d105 bne.n 80056be DC_FAIL_ALARM_CNT++; 80056b2: 4b36 ldr r3, [pc, #216] ; (800578c ) 80056b4: 681b ldr r3, [r3, #0] 80056b6: 3301 adds r3, #1 80056b8: 4a34 ldr r2, [pc, #208] ; (800578c ) 80056ba: 6013 str r3, [r2, #0] 80056bc: e002 b.n 80056c4 else DC_FAIL_ALARM_CNT = 0; 80056be: 4b33 ldr r3, [pc, #204] ; (800578c ) 80056c0: 2200 movs r2, #0 80056c2: 601a str r2, [r3, #0] if(HAL_GPIO_ReadPin(OVER_INPUT_ALARM_GPIO_Port, OVER_INPUT_ALARM_Pin)== GPIO_PIN_SET) 80056c4: f44f 6100 mov.w r1, #2048 ; 0x800 80056c8: 482f ldr r0, [pc, #188] ; (8005788 ) 80056ca: f7fd fe79 bl 80033c0 80056ce: 4603 mov r3, r0 80056d0: 2b01 cmp r3, #1 80056d2: d105 bne.n 80056e0 OVER_INPUT_ALARM_CNT++; 80056d4: 4b2e ldr r3, [pc, #184] ; (8005790 ) 80056d6: 681b ldr r3, [r3, #0] 80056d8: 3301 adds r3, #1 80056da: 4a2d ldr r2, [pc, #180] ; (8005790 ) 80056dc: 6013 str r3, [r2, #0] 80056de: e002 b.n 80056e6 else OVER_INPUT_ALARM_CNT = 0; 80056e0: 4b2b ldr r3, [pc, #172] ; (8005790 ) 80056e2: 2200 movs r2, #0 80056e4: 601a str r2, [r3, #0] if(HAL_GPIO_ReadPin(OVER_TEMP_ALARM_GPIO_Port, OVER_TEMP_ALARM_Pin)== GPIO_PIN_SET) 80056e6: f44f 5180 mov.w r1, #4096 ; 0x1000 80056ea: 4827 ldr r0, [pc, #156] ; (8005788 ) 80056ec: f7fd fe68 bl 80033c0 80056f0: 4603 mov r3, r0 80056f2: 2b01 cmp r3, #1 80056f4: d105 bne.n 8005702 OVER_TEMP_ALARM_CNT++; 80056f6: 4b27 ldr r3, [pc, #156] ; (8005794 ) 80056f8: 681b ldr r3, [r3, #0] 80056fa: 3301 adds r3, #1 80056fc: 4a25 ldr r2, [pc, #148] ; (8005794 ) 80056fe: 6013 str r3, [r2, #0] 8005700: e002 b.n 8005708 else OVER_TEMP_ALARM_CNT = 0; 8005702: 4b24 ldr r3, [pc, #144] ; (8005794 ) 8005704: 2200 movs r2, #0 8005706: 601a str r2, [r3, #0] if(HAL_GPIO_ReadPin(ALC_ALARM_GPIO_Port, ALC_ALARM_Pin)== GPIO_PIN_SET) 8005708: 2108 movs r1, #8 800570a: 4823 ldr r0, [pc, #140] ; (8005798 ) 800570c: f7fd fe58 bl 80033c0 8005710: 4603 mov r3, r0 8005712: 2b01 cmp r3, #1 8005714: d105 bne.n 8005722 ALC_ALARM_CNT++; 8005716: 4b21 ldr r3, [pc, #132] ; (800579c ) 8005718: 681b ldr r3, [r3, #0] 800571a: 3301 adds r3, #1 800571c: 4a1f ldr r2, [pc, #124] ; (800579c ) 800571e: 6013 str r3, [r2, #0] 8005720: e002 b.n 8005728 else ALC_ALARM_CNT = 0; 8005722: 4b1e ldr r3, [pc, #120] ; (800579c ) 8005724: 2200 movs r2, #0 8005726: 601a str r2, [r3, #0] if(HAL_GPIO_ReadPin(OVER_POWER_ALARM_GPIO_Port, OVER_POWER_ALARM_Pin)== GPIO_PIN_SET) 8005728: f44f 5180 mov.w r1, #4096 ; 0x1000 800572c: 481a ldr r0, [pc, #104] ; (8005798 ) 800572e: f7fd fe47 bl 80033c0 8005732: 4603 mov r3, r0 8005734: 2b01 cmp r3, #1 8005736: d105 bne.n 8005744 OVER_POWER_ALARM_CNT++; 8005738: 4b19 ldr r3, [pc, #100] ; (80057a0 ) 800573a: 681b ldr r3, [r3, #0] 800573c: 3301 adds r3, #1 800573e: 4a18 ldr r2, [pc, #96] ; (80057a0 ) 8005740: 6013 str r3, [r2, #0] 8005742: e002 b.n 800574a else OVER_POWER_ALARM_CNT = 0; 8005744: 4b16 ldr r3, [pc, #88] ; (80057a0 ) 8005746: 2200 movs r2, #0 8005748: 601a str r2, [r3, #0] if(HAL_GPIO_ReadPin(VSWR_ALARM_GPIO_Port, VSWR_ALARM_Pin)== GPIO_PIN_SET) 800574a: f44f 5100 mov.w r1, #8192 ; 0x2000 800574e: 4812 ldr r0, [pc, #72] ; (8005798 ) 8005750: f7fd fe36 bl 80033c0 8005754: 4603 mov r3, r0 8005756: 2b01 cmp r3, #1 8005758: d105 bne.n 8005766 VSWR_ALARM_CNT++; 800575a: 4b12 ldr r3, [pc, #72] ; (80057a4 ) 800575c: 681b ldr r3, [r3, #0] 800575e: 3301 adds r3, #1 8005760: 4a10 ldr r2, [pc, #64] ; (80057a4 ) 8005762: 6013 str r3, [r2, #0] else VSWR_ALARM_CNT = 0; } /* USER CODE END Callback 1 */ } 8005764: e002 b.n 800576c VSWR_ALARM_CNT = 0; 8005766: 4b0f ldr r3, [pc, #60] ; (80057a4 ) 8005768: 2200 movs r2, #0 800576a: 601a str r2, [r3, #0] } 800576c: bf00 nop 800576e: 3708 adds r7, #8 8005770: 46bd mov sp, r7 8005772: bd80 pop {r7, pc} 8005774: 40001000 .word 0x40001000 8005778: 20000618 .word 0x20000618 800577c: 20000610 .word 0x20000610 8005780: 20000634 .word 0x20000634 8005784: 20000638 .word 0x20000638 8005788: 40010800 .word 0x40010800 800578c: 2000061c .word 0x2000061c 8005790: 20000620 .word 0x20000620 8005794: 20000624 .word 0x20000624 8005798: 40010c00 .word 0x40010c00 800579c: 20000628 .word 0x20000628 80057a0: 2000062c .word 0x2000062c 80057a4: 20000630 .word 0x20000630 080057a8 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 80057a8: b480 push {r7} 80057aa: af00 add r7, sp, #0 /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ /* USER CODE END Error_Handler_Debug */ } 80057ac: bf00 nop 80057ae: 46bd mov sp, r7 80057b0: bc80 pop {r7} 80057b2: 4770 bx lr 080057b4 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 80057b4: b480 push {r7} 80057b6: b085 sub sp, #20 80057b8: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_AFIO_CLK_ENABLE(); 80057ba: 4b15 ldr r3, [pc, #84] ; (8005810 ) 80057bc: 699b ldr r3, [r3, #24] 80057be: 4a14 ldr r2, [pc, #80] ; (8005810 ) 80057c0: f043 0301 orr.w r3, r3, #1 80057c4: 6193 str r3, [r2, #24] 80057c6: 4b12 ldr r3, [pc, #72] ; (8005810 ) 80057c8: 699b ldr r3, [r3, #24] 80057ca: f003 0301 and.w r3, r3, #1 80057ce: 60bb str r3, [r7, #8] 80057d0: 68bb ldr r3, [r7, #8] __HAL_RCC_PWR_CLK_ENABLE(); 80057d2: 4b0f ldr r3, [pc, #60] ; (8005810 ) 80057d4: 69db ldr r3, [r3, #28] 80057d6: 4a0e ldr r2, [pc, #56] ; (8005810 ) 80057d8: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 80057dc: 61d3 str r3, [r2, #28] 80057de: 4b0c ldr r3, [pc, #48] ; (8005810 ) 80057e0: 69db ldr r3, [r3, #28] 80057e2: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 80057e6: 607b str r3, [r7, #4] 80057e8: 687b ldr r3, [r7, #4] /* System interrupt init*/ /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled */ __HAL_AFIO_REMAP_SWJ_NOJTAG(); 80057ea: 4b0a ldr r3, [pc, #40] ; (8005814 ) 80057ec: 685b ldr r3, [r3, #4] 80057ee: 60fb str r3, [r7, #12] 80057f0: 68fb ldr r3, [r7, #12] 80057f2: f023 63e0 bic.w r3, r3, #117440512 ; 0x7000000 80057f6: 60fb str r3, [r7, #12] 80057f8: 68fb ldr r3, [r7, #12] 80057fa: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000 80057fe: 60fb str r3, [r7, #12] 8005800: 4a04 ldr r2, [pc, #16] ; (8005814 ) 8005802: 68fb ldr r3, [r7, #12] 8005804: 6053 str r3, [r2, #4] /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8005806: bf00 nop 8005808: 3714 adds r7, #20 800580a: 46bd mov sp, r7 800580c: bc80 pop {r7} 800580e: 4770 bx lr 8005810: 40021000 .word 0x40021000 8005814: 40010000 .word 0x40010000 08005818 : * This function configures the hardware resources used in this example * @param hadc: ADC handle pointer * @retval None */ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) { 8005818: b580 push {r7, lr} 800581a: b088 sub sp, #32 800581c: af00 add r7, sp, #0 800581e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8005820: f107 0310 add.w r3, r7, #16 8005824: 2200 movs r2, #0 8005826: 601a str r2, [r3, #0] 8005828: 605a str r2, [r3, #4] 800582a: 609a str r2, [r3, #8] 800582c: 60da str r2, [r3, #12] if(hadc->Instance==ADC1) 800582e: 687b ldr r3, [r7, #4] 8005830: 681b ldr r3, [r3, #0] 8005832: 4a28 ldr r2, [pc, #160] ; (80058d4 ) 8005834: 4293 cmp r3, r2 8005836: d149 bne.n 80058cc { /* USER CODE BEGIN ADC1_MspInit 0 */ /* USER CODE END ADC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_ADC1_CLK_ENABLE(); 8005838: 4b27 ldr r3, [pc, #156] ; (80058d8 ) 800583a: 699b ldr r3, [r3, #24] 800583c: 4a26 ldr r2, [pc, #152] ; (80058d8 ) 800583e: f443 7300 orr.w r3, r3, #512 ; 0x200 8005842: 6193 str r3, [r2, #24] 8005844: 4b24 ldr r3, [pc, #144] ; (80058d8 ) 8005846: 699b ldr r3, [r3, #24] 8005848: f403 7300 and.w r3, r3, #512 ; 0x200 800584c: 60fb str r3, [r7, #12] 800584e: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 8005850: 4b21 ldr r3, [pc, #132] ; (80058d8 ) 8005852: 699b ldr r3, [r3, #24] 8005854: 4a20 ldr r2, [pc, #128] ; (80058d8 ) 8005856: f043 0304 orr.w r3, r3, #4 800585a: 6193 str r3, [r2, #24] 800585c: 4b1e ldr r3, [pc, #120] ; (80058d8 ) 800585e: 699b ldr r3, [r3, #24] 8005860: f003 0304 and.w r3, r3, #4 8005864: 60bb str r3, [r7, #8] 8005866: 68bb ldr r3, [r7, #8] /**ADC1 GPIO Configuration PA0-WKUP ------> ADC1_IN0 PA1 ------> ADC1_IN1 PA3 ------> ADC1_IN3 */ GPIO_InitStruct.Pin = DL_TX_DET_Pin|DL_RX_DET_Pin|PAU_TEMP_Pin; 8005868: 230b movs r3, #11 800586a: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 800586c: 2303 movs r3, #3 800586e: 617b str r3, [r7, #20] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8005870: f107 0310 add.w r3, r7, #16 8005874: 4619 mov r1, r3 8005876: 4819 ldr r0, [pc, #100] ; (80058dc ) 8005878: f7fd fc48 bl 800310c /* ADC1 DMA Init */ /* ADC1 Init */ hdma_adc1.Instance = DMA1_Channel1; 800587c: 4b18 ldr r3, [pc, #96] ; (80058e0 ) 800587e: 4a19 ldr r2, [pc, #100] ; (80058e4 ) 8005880: 601a str r2, [r3, #0] hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY; 8005882: 4b17 ldr r3, [pc, #92] ; (80058e0 ) 8005884: 2200 movs r2, #0 8005886: 605a str r2, [r3, #4] hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE; 8005888: 4b15 ldr r3, [pc, #84] ; (80058e0 ) 800588a: 2200 movs r2, #0 800588c: 609a str r2, [r3, #8] hdma_adc1.Init.MemInc = DMA_MINC_ENABLE; 800588e: 4b14 ldr r3, [pc, #80] ; (80058e0 ) 8005890: 2280 movs r2, #128 ; 0x80 8005892: 60da str r2, [r3, #12] hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 8005894: 4b12 ldr r3, [pc, #72] ; (80058e0 ) 8005896: f44f 7280 mov.w r2, #256 ; 0x100 800589a: 611a str r2, [r3, #16] hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 800589c: 4b10 ldr r3, [pc, #64] ; (80058e0 ) 800589e: f44f 6280 mov.w r2, #1024 ; 0x400 80058a2: 615a str r2, [r3, #20] hdma_adc1.Init.Mode = DMA_CIRCULAR; 80058a4: 4b0e ldr r3, [pc, #56] ; (80058e0 ) 80058a6: 2220 movs r2, #32 80058a8: 619a str r2, [r3, #24] hdma_adc1.Init.Priority = DMA_PRIORITY_LOW; 80058aa: 4b0d ldr r3, [pc, #52] ; (80058e0 ) 80058ac: 2200 movs r2, #0 80058ae: 61da str r2, [r3, #28] if (HAL_DMA_Init(&hdma_adc1) != HAL_OK) 80058b0: 480b ldr r0, [pc, #44] ; (80058e0 ) 80058b2: f7fc ffc7 bl 8002844 80058b6: 4603 mov r3, r0 80058b8: 2b00 cmp r3, #0 80058ba: d001 beq.n 80058c0 { Error_Handler(); 80058bc: f7ff ff74 bl 80057a8 } __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc1); 80058c0: 687b ldr r3, [r7, #4] 80058c2: 4a07 ldr r2, [pc, #28] ; (80058e0 ) 80058c4: 621a str r2, [r3, #32] 80058c6: 4a06 ldr r2, [pc, #24] ; (80058e0 ) 80058c8: 687b ldr r3, [r7, #4] 80058ca: 6253 str r3, [r2, #36] ; 0x24 /* USER CODE BEGIN ADC1_MspInit 1 */ /* USER CODE END ADC1_MspInit 1 */ } } 80058cc: bf00 nop 80058ce: 3720 adds r7, #32 80058d0: 46bd mov sp, r7 80058d2: bd80 pop {r7, pc} 80058d4: 40012400 .word 0x40012400 80058d8: 40021000 .word 0x40021000 80058dc: 40010800 .word 0x40010800 80058e0: 20000ad0 .word 0x20000ad0 80058e4: 40020008 .word 0x40020008 080058e8 : * This function configures the hardware resources used in this example * @param htim_base: TIM_Base handle pointer * @retval None */ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) { 80058e8: b480 push {r7} 80058ea: b085 sub sp, #20 80058ec: af00 add r7, sp, #0 80058ee: 6078 str r0, [r7, #4] if(htim_base->Instance==TIM6) 80058f0: 687b ldr r3, [r7, #4] 80058f2: 681b ldr r3, [r3, #0] 80058f4: 4a09 ldr r2, [pc, #36] ; (800591c ) 80058f6: 4293 cmp r3, r2 80058f8: d10b bne.n 8005912 { /* USER CODE BEGIN TIM6_MspInit 0 */ /* USER CODE END TIM6_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM6_CLK_ENABLE(); 80058fa: 4b09 ldr r3, [pc, #36] ; (8005920 ) 80058fc: 69db ldr r3, [r3, #28] 80058fe: 4a08 ldr r2, [pc, #32] ; (8005920 ) 8005900: f043 0310 orr.w r3, r3, #16 8005904: 61d3 str r3, [r2, #28] 8005906: 4b06 ldr r3, [pc, #24] ; (8005920 ) 8005908: 69db ldr r3, [r3, #28] 800590a: f003 0310 and.w r3, r3, #16 800590e: 60fb str r3, [r7, #12] 8005910: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN TIM6_MspInit 1 */ /* USER CODE END TIM6_MspInit 1 */ } } 8005912: bf00 nop 8005914: 3714 adds r7, #20 8005916: 46bd mov sp, r7 8005918: bc80 pop {r7} 800591a: 4770 bx lr 800591c: 40001000 .word 0x40001000 8005920: 40021000 .word 0x40021000 08005924 : * This function configures the hardware resources used in this example * @param huart: UART handle pointer * @retval None */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { 8005924: b580 push {r7, lr} 8005926: b08a sub sp, #40 ; 0x28 8005928: af00 add r7, sp, #0 800592a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800592c: f107 0318 add.w r3, r7, #24 8005930: 2200 movs r2, #0 8005932: 601a str r2, [r3, #0] 8005934: 605a str r2, [r3, #4] 8005936: 609a str r2, [r3, #8] 8005938: 60da str r2, [r3, #12] if(huart->Instance==USART1) 800593a: 687b ldr r3, [r7, #4] 800593c: 681b ldr r3, [r3, #0] 800593e: 4a84 ldr r2, [pc, #528] ; (8005b50 ) 8005940: 4293 cmp r3, r2 8005942: d17e bne.n 8005a42 { /* USER CODE BEGIN USART1_MspInit 0 */ /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); 8005944: 4b83 ldr r3, [pc, #524] ; (8005b54 ) 8005946: 699b ldr r3, [r3, #24] 8005948: 4a82 ldr r2, [pc, #520] ; (8005b54 ) 800594a: f443 4380 orr.w r3, r3, #16384 ; 0x4000 800594e: 6193 str r3, [r2, #24] 8005950: 4b80 ldr r3, [pc, #512] ; (8005b54 ) 8005952: 699b ldr r3, [r3, #24] 8005954: f403 4380 and.w r3, r3, #16384 ; 0x4000 8005958: 617b str r3, [r7, #20] 800595a: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 800595c: 4b7d ldr r3, [pc, #500] ; (8005b54 ) 800595e: 699b ldr r3, [r3, #24] 8005960: 4a7c ldr r2, [pc, #496] ; (8005b54 ) 8005962: f043 0304 orr.w r3, r3, #4 8005966: 6193 str r3, [r2, #24] 8005968: 4b7a ldr r3, [pc, #488] ; (8005b54 ) 800596a: 699b ldr r3, [r3, #24] 800596c: f003 0304 and.w r3, r3, #4 8005970: 613b str r3, [r7, #16] 8005972: 693b ldr r3, [r7, #16] /**USART1 GPIO Configuration PA9 ------> USART1_TX PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_9; 8005974: f44f 7300 mov.w r3, #512 ; 0x200 8005978: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800597a: 2302 movs r3, #2 800597c: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800597e: 2303 movs r3, #3 8005980: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8005982: f107 0318 add.w r3, r7, #24 8005986: 4619 mov r1, r3 8005988: 4873 ldr r0, [pc, #460] ; (8005b58 ) 800598a: f7fd fbbf bl 800310c GPIO_InitStruct.Pin = GPIO_PIN_10; 800598e: f44f 6380 mov.w r3, #1024 ; 0x400 8005992: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8005994: 2300 movs r3, #0 8005996: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 8005998: 2300 movs r3, #0 800599a: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800599c: f107 0318 add.w r3, r7, #24 80059a0: 4619 mov r1, r3 80059a2: 486d ldr r0, [pc, #436] ; (8005b58 ) 80059a4: f7fd fbb2 bl 800310c /* USART1 DMA Init */ /* USART1_TX Init */ hdma_usart1_tx.Instance = DMA1_Channel4; 80059a8: 4b6c ldr r3, [pc, #432] ; (8005b5c ) 80059aa: 4a6d ldr r2, [pc, #436] ; (8005b60 ) 80059ac: 601a str r2, [r3, #0] hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 80059ae: 4b6b ldr r3, [pc, #428] ; (8005b5c ) 80059b0: 2210 movs r2, #16 80059b2: 605a str r2, [r3, #4] hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE; 80059b4: 4b69 ldr r3, [pc, #420] ; (8005b5c ) 80059b6: 2200 movs r2, #0 80059b8: 609a str r2, [r3, #8] hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE; 80059ba: 4b68 ldr r3, [pc, #416] ; (8005b5c ) 80059bc: 2280 movs r2, #128 ; 0x80 80059be: 60da str r2, [r3, #12] hdma_usart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 80059c0: 4b66 ldr r3, [pc, #408] ; (8005b5c ) 80059c2: 2200 movs r2, #0 80059c4: 611a str r2, [r3, #16] hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 80059c6: 4b65 ldr r3, [pc, #404] ; (8005b5c ) 80059c8: 2200 movs r2, #0 80059ca: 615a str r2, [r3, #20] hdma_usart1_tx.Init.Mode = DMA_NORMAL; 80059cc: 4b63 ldr r3, [pc, #396] ; (8005b5c ) 80059ce: 2200 movs r2, #0 80059d0: 619a str r2, [r3, #24] hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW; 80059d2: 4b62 ldr r3, [pc, #392] ; (8005b5c ) 80059d4: 2200 movs r2, #0 80059d6: 61da str r2, [r3, #28] if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK) 80059d8: 4860 ldr r0, [pc, #384] ; (8005b5c ) 80059da: f7fc ff33 bl 8002844 80059de: 4603 mov r3, r0 80059e0: 2b00 cmp r3, #0 80059e2: d001 beq.n 80059e8 { Error_Handler(); 80059e4: f7ff fee0 bl 80057a8 } __HAL_LINKDMA(huart,hdmatx,hdma_usart1_tx); 80059e8: 687b ldr r3, [r7, #4] 80059ea: 4a5c ldr r2, [pc, #368] ; (8005b5c ) 80059ec: 631a str r2, [r3, #48] ; 0x30 80059ee: 4a5b ldr r2, [pc, #364] ; (8005b5c ) 80059f0: 687b ldr r3, [r7, #4] 80059f2: 6253 str r3, [r2, #36] ; 0x24 /* USART1_RX Init */ hdma_usart1_rx.Instance = DMA1_Channel5; 80059f4: 4b5b ldr r3, [pc, #364] ; (8005b64 ) 80059f6: 4a5c ldr r2, [pc, #368] ; (8005b68 ) 80059f8: 601a str r2, [r3, #0] hdma_usart1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 80059fa: 4b5a ldr r3, [pc, #360] ; (8005b64 ) 80059fc: 2200 movs r2, #0 80059fe: 605a str r2, [r3, #4] hdma_usart1_rx.Init.PeriphInc = DMA_PINC_DISABLE; 8005a00: 4b58 ldr r3, [pc, #352] ; (8005b64 ) 8005a02: 2200 movs r2, #0 8005a04: 609a str r2, [r3, #8] hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE; 8005a06: 4b57 ldr r3, [pc, #348] ; (8005b64 ) 8005a08: 2280 movs r2, #128 ; 0x80 8005a0a: 60da str r2, [r3, #12] hdma_usart1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8005a0c: 4b55 ldr r3, [pc, #340] ; (8005b64 ) 8005a0e: 2200 movs r2, #0 8005a10: 611a str r2, [r3, #16] hdma_usart1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8005a12: 4b54 ldr r3, [pc, #336] ; (8005b64 ) 8005a14: 2200 movs r2, #0 8005a16: 615a str r2, [r3, #20] hdma_usart1_rx.Init.Mode = DMA_NORMAL; 8005a18: 4b52 ldr r3, [pc, #328] ; (8005b64 ) 8005a1a: 2200 movs r2, #0 8005a1c: 619a str r2, [r3, #24] hdma_usart1_rx.Init.Priority = DMA_PRIORITY_LOW; 8005a1e: 4b51 ldr r3, [pc, #324] ; (8005b64 ) 8005a20: 2200 movs r2, #0 8005a22: 61da str r2, [r3, #28] if (HAL_DMA_Init(&hdma_usart1_rx) != HAL_OK) 8005a24: 484f ldr r0, [pc, #316] ; (8005b64 ) 8005a26: f7fc ff0d bl 8002844 8005a2a: 4603 mov r3, r0 8005a2c: 2b00 cmp r3, #0 8005a2e: d001 beq.n 8005a34 { Error_Handler(); 8005a30: f7ff feba bl 80057a8 } __HAL_LINKDMA(huart,hdmarx,hdma_usart1_rx); 8005a34: 687b ldr r3, [r7, #4] 8005a36: 4a4b ldr r2, [pc, #300] ; (8005b64 ) 8005a38: 635a str r2, [r3, #52] ; 0x34 8005a3a: 4a4a ldr r2, [pc, #296] ; (8005b64 ) 8005a3c: 687b ldr r3, [r7, #4] 8005a3e: 6253 str r3, [r2, #36] ; 0x24 /* USER CODE BEGIN USART3_MspInit 1 */ /* USER CODE END USART3_MspInit 1 */ } } 8005a40: e082 b.n 8005b48 else if(huart->Instance==USART3) 8005a42: 687b ldr r3, [r7, #4] 8005a44: 681b ldr r3, [r3, #0] 8005a46: 4a49 ldr r2, [pc, #292] ; (8005b6c ) 8005a48: 4293 cmp r3, r2 8005a4a: d17d bne.n 8005b48 __HAL_RCC_USART3_CLK_ENABLE(); 8005a4c: 4b41 ldr r3, [pc, #260] ; (8005b54 ) 8005a4e: 69db ldr r3, [r3, #28] 8005a50: 4a40 ldr r2, [pc, #256] ; (8005b54 ) 8005a52: f443 2380 orr.w r3, r3, #262144 ; 0x40000 8005a56: 61d3 str r3, [r2, #28] 8005a58: 4b3e ldr r3, [pc, #248] ; (8005b54 ) 8005a5a: 69db ldr r3, [r3, #28] 8005a5c: f403 2380 and.w r3, r3, #262144 ; 0x40000 8005a60: 60fb str r3, [r7, #12] 8005a62: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOB_CLK_ENABLE(); 8005a64: 4b3b ldr r3, [pc, #236] ; (8005b54 ) 8005a66: 699b ldr r3, [r3, #24] 8005a68: 4a3a ldr r2, [pc, #232] ; (8005b54 ) 8005a6a: f043 0308 orr.w r3, r3, #8 8005a6e: 6193 str r3, [r2, #24] 8005a70: 4b38 ldr r3, [pc, #224] ; (8005b54 ) 8005a72: 699b ldr r3, [r3, #24] 8005a74: f003 0308 and.w r3, r3, #8 8005a78: 60bb str r3, [r7, #8] 8005a7a: 68bb ldr r3, [r7, #8] GPIO_InitStruct.Pin = GPIO_PIN_10; 8005a7c: f44f 6380 mov.w r3, #1024 ; 0x400 8005a80: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8005a82: 2302 movs r3, #2 8005a84: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8005a86: 2303 movs r3, #3 8005a88: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8005a8a: f107 0318 add.w r3, r7, #24 8005a8e: 4619 mov r1, r3 8005a90: 4837 ldr r0, [pc, #220] ; (8005b70 ) 8005a92: f7fd fb3b bl 800310c GPIO_InitStruct.Pin = GPIO_PIN_11; 8005a96: f44f 6300 mov.w r3, #2048 ; 0x800 8005a9a: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8005a9c: 2300 movs r3, #0 8005a9e: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 8005aa0: 2300 movs r3, #0 8005aa2: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8005aa4: f107 0318 add.w r3, r7, #24 8005aa8: 4619 mov r1, r3 8005aaa: 4831 ldr r0, [pc, #196] ; (8005b70 ) 8005aac: f7fd fb2e bl 800310c hdma_usart3_tx.Instance = DMA1_Channel2; 8005ab0: 4b30 ldr r3, [pc, #192] ; (8005b74 ) 8005ab2: 4a31 ldr r2, [pc, #196] ; (8005b78 ) 8005ab4: 601a str r2, [r3, #0] hdma_usart3_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 8005ab6: 4b2f ldr r3, [pc, #188] ; (8005b74 ) 8005ab8: 2210 movs r2, #16 8005aba: 605a str r2, [r3, #4] hdma_usart3_tx.Init.PeriphInc = DMA_PINC_DISABLE; 8005abc: 4b2d ldr r3, [pc, #180] ; (8005b74 ) 8005abe: 2200 movs r2, #0 8005ac0: 609a str r2, [r3, #8] hdma_usart3_tx.Init.MemInc = DMA_MINC_ENABLE; 8005ac2: 4b2c ldr r3, [pc, #176] ; (8005b74 ) 8005ac4: 2280 movs r2, #128 ; 0x80 8005ac6: 60da str r2, [r3, #12] hdma_usart3_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8005ac8: 4b2a ldr r3, [pc, #168] ; (8005b74 ) 8005aca: 2200 movs r2, #0 8005acc: 611a str r2, [r3, #16] hdma_usart3_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8005ace: 4b29 ldr r3, [pc, #164] ; (8005b74 ) 8005ad0: 2200 movs r2, #0 8005ad2: 615a str r2, [r3, #20] hdma_usart3_tx.Init.Mode = DMA_NORMAL; 8005ad4: 4b27 ldr r3, [pc, #156] ; (8005b74 ) 8005ad6: 2200 movs r2, #0 8005ad8: 619a str r2, [r3, #24] hdma_usart3_tx.Init.Priority = DMA_PRIORITY_LOW; 8005ada: 4b26 ldr r3, [pc, #152] ; (8005b74 ) 8005adc: 2200 movs r2, #0 8005ade: 61da str r2, [r3, #28] if (HAL_DMA_Init(&hdma_usart3_tx) != HAL_OK) 8005ae0: 4824 ldr r0, [pc, #144] ; (8005b74 ) 8005ae2: f7fc feaf bl 8002844 8005ae6: 4603 mov r3, r0 8005ae8: 2b00 cmp r3, #0 8005aea: d001 beq.n 8005af0 Error_Handler(); 8005aec: f7ff fe5c bl 80057a8 __HAL_LINKDMA(huart,hdmatx,hdma_usart3_tx); 8005af0: 687b ldr r3, [r7, #4] 8005af2: 4a20 ldr r2, [pc, #128] ; (8005b74 ) 8005af4: 631a str r2, [r3, #48] ; 0x30 8005af6: 4a1f ldr r2, [pc, #124] ; (8005b74 ) 8005af8: 687b ldr r3, [r7, #4] 8005afa: 6253 str r3, [r2, #36] ; 0x24 hdma_usart3_rx.Instance = DMA1_Channel3; 8005afc: 4b1f ldr r3, [pc, #124] ; (8005b7c ) 8005afe: 4a20 ldr r2, [pc, #128] ; (8005b80 ) 8005b00: 601a str r2, [r3, #0] hdma_usart3_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 8005b02: 4b1e ldr r3, [pc, #120] ; (8005b7c ) 8005b04: 2200 movs r2, #0 8005b06: 605a str r2, [r3, #4] hdma_usart3_rx.Init.PeriphInc = DMA_PINC_DISABLE; 8005b08: 4b1c ldr r3, [pc, #112] ; (8005b7c ) 8005b0a: 2200 movs r2, #0 8005b0c: 609a str r2, [r3, #8] hdma_usart3_rx.Init.MemInc = DMA_MINC_ENABLE; 8005b0e: 4b1b ldr r3, [pc, #108] ; (8005b7c ) 8005b10: 2280 movs r2, #128 ; 0x80 8005b12: 60da str r2, [r3, #12] hdma_usart3_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8005b14: 4b19 ldr r3, [pc, #100] ; (8005b7c ) 8005b16: 2200 movs r2, #0 8005b18: 611a str r2, [r3, #16] hdma_usart3_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8005b1a: 4b18 ldr r3, [pc, #96] ; (8005b7c ) 8005b1c: 2200 movs r2, #0 8005b1e: 615a str r2, [r3, #20] hdma_usart3_rx.Init.Mode = DMA_NORMAL; 8005b20: 4b16 ldr r3, [pc, #88] ; (8005b7c ) 8005b22: 2200 movs r2, #0 8005b24: 619a str r2, [r3, #24] hdma_usart3_rx.Init.Priority = DMA_PRIORITY_LOW; 8005b26: 4b15 ldr r3, [pc, #84] ; (8005b7c ) 8005b28: 2200 movs r2, #0 8005b2a: 61da str r2, [r3, #28] if (HAL_DMA_Init(&hdma_usart3_rx) != HAL_OK) 8005b2c: 4813 ldr r0, [pc, #76] ; (8005b7c ) 8005b2e: f7fc fe89 bl 8002844 8005b32: 4603 mov r3, r0 8005b34: 2b00 cmp r3, #0 8005b36: d001 beq.n 8005b3c Error_Handler(); 8005b38: f7ff fe36 bl 80057a8 __HAL_LINKDMA(huart,hdmarx,hdma_usart3_rx); 8005b3c: 687b ldr r3, [r7, #4] 8005b3e: 4a0f ldr r2, [pc, #60] ; (8005b7c ) 8005b40: 635a str r2, [r3, #52] ; 0x34 8005b42: 4a0e ldr r2, [pc, #56] ; (8005b7c ) 8005b44: 687b ldr r3, [r7, #4] 8005b46: 6253 str r3, [r2, #36] ; 0x24 } 8005b48: bf00 nop 8005b4a: 3728 adds r7, #40 ; 0x28 8005b4c: 46bd mov sp, r7 8005b4e: bd80 pop {r7, pc} 8005b50: 40013800 .word 0x40013800 8005b54: 40021000 .word 0x40021000 8005b58: 40010800 .word 0x40010800 8005b5c: 200009d8 .word 0x200009d8 8005b60: 40020044 .word 0x40020044 8005b64: 20000a4c .word 0x20000a4c 8005b68: 40020058 .word 0x40020058 8005b6c: 40004800 .word 0x40004800 8005b70: 40010c00 .word 0x40010c00 8005b74: 20000994 .word 0x20000994 8005b78: 4002001c .word 0x4002001c 8005b7c: 20000910 .word 0x20000910 8005b80: 40020030 .word 0x40020030 08005b84 : * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). * @param TickPriority: Tick interrupt priority. * @retval HAL status */ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8005b84: b580 push {r7, lr} 8005b86: b08c sub sp, #48 ; 0x30 8005b88: af00 add r7, sp, #0 8005b8a: 6078 str r0, [r7, #4] RCC_ClkInitTypeDef clkconfig; uint32_t uwTimclock = 0; 8005b8c: 2300 movs r3, #0 8005b8e: 62fb str r3, [r7, #44] ; 0x2c uint32_t uwPrescalerValue = 0; 8005b90: 2300 movs r3, #0 8005b92: 62bb str r3, [r7, #40] ; 0x28 uint32_t pFLatency; /*Configure the TIM2 IRQ priority */ HAL_NVIC_SetPriority(TIM2_IRQn, TickPriority ,0); 8005b94: 2200 movs r2, #0 8005b96: 6879 ldr r1, [r7, #4] 8005b98: 201c movs r0, #28 8005b9a: f7fc fe28 bl 80027ee /* Enable the TIM2 global Interrupt */ HAL_NVIC_EnableIRQ(TIM2_IRQn); 8005b9e: 201c movs r0, #28 8005ba0: f7fc fe41 bl 8002826 /* Enable TIM2 clock */ __HAL_RCC_TIM2_CLK_ENABLE(); 8005ba4: 4b1f ldr r3, [pc, #124] ; (8005c24 ) 8005ba6: 69db ldr r3, [r3, #28] 8005ba8: 4a1e ldr r2, [pc, #120] ; (8005c24 ) 8005baa: f043 0301 orr.w r3, r3, #1 8005bae: 61d3 str r3, [r2, #28] 8005bb0: 4b1c ldr r3, [pc, #112] ; (8005c24 ) 8005bb2: 69db ldr r3, [r3, #28] 8005bb4: f003 0301 and.w r3, r3, #1 8005bb8: 60fb str r3, [r7, #12] 8005bba: 68fb ldr r3, [r7, #12] /* Get clock configuration */ HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); 8005bbc: f107 0210 add.w r2, r7, #16 8005bc0: f107 0314 add.w r3, r7, #20 8005bc4: 4611 mov r1, r2 8005bc6: 4618 mov r0, r3 8005bc8: f7fe f810 bl 8003bec /* Compute TIM2 clock */ uwTimclock = HAL_RCC_GetPCLK1Freq(); 8005bcc: f7fd ffe6 bl 8003b9c 8005bd0: 62f8 str r0, [r7, #44] ; 0x2c /* Compute the prescaler value to have TIM2 counter clock equal to 1MHz */ uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000) - 1); 8005bd2: 6afb ldr r3, [r7, #44] ; 0x2c 8005bd4: 4a14 ldr r2, [pc, #80] ; (8005c28 ) 8005bd6: fba2 2303 umull r2, r3, r2, r3 8005bda: 0c9b lsrs r3, r3, #18 8005bdc: 3b01 subs r3, #1 8005bde: 62bb str r3, [r7, #40] ; 0x28 /* Initialize TIM2 */ htim2.Instance = TIM2; 8005be0: 4b12 ldr r3, [pc, #72] ; (8005c2c ) 8005be2: f04f 4280 mov.w r2, #1073741824 ; 0x40000000 8005be6: 601a str r2, [r3, #0] + Period = [(TIM2CLK/1000) - 1]. to have a (1/1000) s time base. + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. + ClockDivision = 0 + Counter direction = Up */ htim2.Init.Period = (1000000 / 1000) - 1; 8005be8: 4b10 ldr r3, [pc, #64] ; (8005c2c ) 8005bea: f240 32e7 movw r2, #999 ; 0x3e7 8005bee: 60da str r2, [r3, #12] htim2.Init.Prescaler = uwPrescalerValue; 8005bf0: 4a0e ldr r2, [pc, #56] ; (8005c2c ) 8005bf2: 6abb ldr r3, [r7, #40] ; 0x28 8005bf4: 6053 str r3, [r2, #4] htim2.Init.ClockDivision = 0; 8005bf6: 4b0d ldr r3, [pc, #52] ; (8005c2c ) 8005bf8: 2200 movs r2, #0 8005bfa: 611a str r2, [r3, #16] htim2.Init.CounterMode = TIM_COUNTERMODE_UP; 8005bfc: 4b0b ldr r3, [pc, #44] ; (8005c2c ) 8005bfe: 2200 movs r2, #0 8005c00: 609a str r2, [r3, #8] if(HAL_TIM_Base_Init(&htim2) == HAL_OK) 8005c02: 480a ldr r0, [pc, #40] ; (8005c2c ) 8005c04: f7fe f93a bl 8003e7c 8005c08: 4603 mov r3, r0 8005c0a: 2b00 cmp r3, #0 8005c0c: d104 bne.n 8005c18 { /* Start the TIM time Base generation in interrupt mode */ return HAL_TIM_Base_Start_IT(&htim2); 8005c0e: 4807 ldr r0, [pc, #28] ; (8005c2c ) 8005c10: f7fe f95f bl 8003ed2 8005c14: 4603 mov r3, r0 8005c16: e000 b.n 8005c1a } /* Return function status */ return HAL_ERROR; 8005c18: 2301 movs r3, #1 } 8005c1a: 4618 mov r0, r3 8005c1c: 3730 adds r7, #48 ; 0x30 8005c1e: 46bd mov sp, r7 8005c20: bd80 pop {r7, pc} 8005c22: bf00 nop 8005c24: 40021000 .word 0x40021000 8005c28: 431bde83 .word 0x431bde83 8005c2c: 20000b54 .word 0x20000b54 08005c30 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8005c30: b480 push {r7} 8005c32: af00 add r7, sp, #0 /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ /* USER CODE END NonMaskableInt_IRQn 1 */ } 8005c34: bf00 nop 8005c36: 46bd mov sp, r7 8005c38: bc80 pop {r7} 8005c3a: 4770 bx lr 08005c3c : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8005c3c: b480 push {r7} 8005c3e: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8005c40: e7fe b.n 8005c40 08005c42 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8005c42: b480 push {r7} 8005c44: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8005c46: e7fe b.n 8005c46 08005c48 : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { 8005c48: b480 push {r7} 8005c4a: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 8005c4c: e7fe b.n 8005c4c 08005c4e : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8005c4e: b480 push {r7} 8005c50: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8005c52: e7fe b.n 8005c52 08005c54 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 8005c54: b480 push {r7} 8005c56: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 8005c58: bf00 nop 8005c5a: 46bd mov sp, r7 8005c5c: bc80 pop {r7} 8005c5e: 4770 bx lr 08005c60 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 8005c60: b480 push {r7} 8005c62: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8005c64: bf00 nop 8005c66: 46bd mov sp, r7 8005c68: bc80 pop {r7} 8005c6a: 4770 bx lr 08005c6c : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8005c6c: b480 push {r7} 8005c6e: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 8005c70: bf00 nop 8005c72: 46bd mov sp, r7 8005c74: bc80 pop {r7} 8005c76: 4770 bx lr 08005c78 : /** * @brief This function handles DMA1 channel1 global interrupt. */ void DMA1_Channel1_IRQHandler(void) { 8005c78: b580 push {r7, lr} 8005c7a: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */ /* USER CODE END DMA1_Channel1_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc1); 8005c7c: 4802 ldr r0, [pc, #8] ; (8005c88 ) 8005c7e: f7fc ff11 bl 8002aa4 /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */ /* USER CODE END DMA1_Channel1_IRQn 1 */ } 8005c82: bf00 nop 8005c84: bd80 pop {r7, pc} 8005c86: bf00 nop 8005c88: 20000ad0 .word 0x20000ad0 08005c8c : /** * @brief This function handles DMA1 channel2 global interrupt. */ void DMA1_Channel2_IRQHandler(void) { 8005c8c: b580 push {r7, lr} 8005c8e: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Channel2_IRQn 0 */ /* USER CODE END DMA1_Channel2_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart3_tx); 8005c90: 4802 ldr r0, [pc, #8] ; (8005c9c ) 8005c92: f7fc ff07 bl 8002aa4 /* USER CODE BEGIN DMA1_Channel2_IRQn 1 */ /* USER CODE END DMA1_Channel2_IRQn 1 */ } 8005c96: bf00 nop 8005c98: bd80 pop {r7, pc} 8005c9a: bf00 nop 8005c9c: 20000994 .word 0x20000994 08005ca0 : /** * @brief This function handles DMA1 channel3 global interrupt. */ void DMA1_Channel3_IRQHandler(void) { 8005ca0: b580 push {r7, lr} 8005ca2: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Channel3_IRQn 0 */ /* USER CODE END DMA1_Channel3_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart3_rx); 8005ca4: 4802 ldr r0, [pc, #8] ; (8005cb0 ) 8005ca6: f7fc fefd bl 8002aa4 /* USER CODE BEGIN DMA1_Channel3_IRQn 1 */ /* USER CODE END DMA1_Channel3_IRQn 1 */ } 8005caa: bf00 nop 8005cac: bd80 pop {r7, pc} 8005cae: bf00 nop 8005cb0: 20000910 .word 0x20000910 08005cb4 : /** * @brief This function handles DMA1 channel4 global interrupt. */ void DMA1_Channel4_IRQHandler(void) { 8005cb4: b580 push {r7, lr} 8005cb6: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Channel4_IRQn 0 */ /* USER CODE END DMA1_Channel4_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart1_tx); 8005cb8: 4802 ldr r0, [pc, #8] ; (8005cc4 ) 8005cba: f7fc fef3 bl 8002aa4 /* USER CODE BEGIN DMA1_Channel4_IRQn 1 */ /* USER CODE END DMA1_Channel4_IRQn 1 */ } 8005cbe: bf00 nop 8005cc0: bd80 pop {r7, pc} 8005cc2: bf00 nop 8005cc4: 200009d8 .word 0x200009d8 08005cc8 : /** * @brief This function handles DMA1 channel5 global interrupt. */ void DMA1_Channel5_IRQHandler(void) { 8005cc8: b580 push {r7, lr} 8005cca: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Channel5_IRQn 0 */ /* USER CODE END DMA1_Channel5_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart1_rx); 8005ccc: 4802 ldr r0, [pc, #8] ; (8005cd8 ) 8005cce: f7fc fee9 bl 8002aa4 /* USER CODE BEGIN DMA1_Channel5_IRQn 1 */ /* USER CODE END DMA1_Channel5_IRQn 1 */ } 8005cd2: bf00 nop 8005cd4: bd80 pop {r7, pc} 8005cd6: bf00 nop 8005cd8: 20000a4c .word 0x20000a4c 08005cdc : /** * @brief This function handles ADC1 global interrupt. */ void ADC1_IRQHandler(void) { 8005cdc: b580 push {r7, lr} 8005cde: af00 add r7, sp, #0 /* USER CODE BEGIN ADC1_IRQn 0 */ /* USER CODE END ADC1_IRQn 0 */ HAL_ADC_IRQHandler(&hadc1); 8005ce0: 4802 ldr r0, [pc, #8] ; (8005cec ) 8005ce2: f7fc f961 bl 8001fa8 /* USER CODE BEGIN ADC1_IRQn 1 */ /* USER CODE END ADC1_IRQn 1 */ } 8005ce6: bf00 nop 8005ce8: bd80 pop {r7, pc} 8005cea: bf00 nop 8005cec: 20000a1c .word 0x20000a1c 08005cf0 : /** * @brief This function handles TIM2 global interrupt. */ void TIM2_IRQHandler(void) { 8005cf0: b580 push {r7, lr} 8005cf2: af00 add r7, sp, #0 /* USER CODE BEGIN TIM2_IRQn 0 */ /* USER CODE END TIM2_IRQn 0 */ HAL_TIM_IRQHandler(&htim2); 8005cf4: 4802 ldr r0, [pc, #8] ; (8005d00 ) 8005cf6: f7fe f90f bl 8003f18 /* USER CODE BEGIN TIM2_IRQn 1 */ /* USER CODE END TIM2_IRQn 1 */ } 8005cfa: bf00 nop 8005cfc: bd80 pop {r7, pc} 8005cfe: bf00 nop 8005d00: 20000b54 .word 0x20000b54 08005d04 : /** * @brief This function handles USART1 global interrupt. */ void USART1_IRQHandler(void) { 8005d04: b580 push {r7, lr} 8005d06: af00 add r7, sp, #0 /* USER CODE BEGIN USART1_IRQn 0 */ /* USER CODE END USART1_IRQn 0 */ HAL_UART_IRQHandler(&huart1); 8005d08: 4802 ldr r0, [pc, #8] ; (8005d14 ) 8005d0a: f7fe fd2d bl 8004768 /* USER CODE BEGIN USART1_IRQn 1 */ /* USER CODE END USART1_IRQn 1 */ } 8005d0e: bf00 nop 8005d10: bd80 pop {r7, pc} 8005d12: bf00 nop 8005d14: 20000a90 .word 0x20000a90 08005d18 : /** * @brief This function handles USART3 global interrupt. */ void USART3_IRQHandler(void) { 8005d18: b580 push {r7, lr} 8005d1a: af00 add r7, sp, #0 /* USER CODE BEGIN USART3_IRQn 0 */ /* USER CODE END USART3_IRQn 0 */ HAL_UART_IRQHandler(&huart3); 8005d1c: 4802 ldr r0, [pc, #8] ; (8005d28 ) 8005d1e: f7fe fd23 bl 8004768 /* USER CODE BEGIN USART3_IRQn 1 */ /* USER CODE END USART3_IRQn 1 */ } 8005d22: bf00 nop 8005d24: bd80 pop {r7, pc} 8005d26: bf00 nop 8005d28: 20000954 .word 0x20000954 08005d2c : /** * @brief This function handles TIM6 global interrupt and DAC underrun error interrupts. */ void TIM6_DAC_IRQHandler(void) { 8005d2c: b580 push {r7, lr} 8005d2e: af00 add r7, sp, #0 /* USER CODE BEGIN TIM6_DAC_IRQn 0 */ /* USER CODE END TIM6_DAC_IRQn 0 */ HAL_TIM_IRQHandler(&htim6); 8005d30: 4802 ldr r0, [pc, #8] ; (8005d3c ) 8005d32: f7fe f8f1 bl 8003f18 /* USER CODE BEGIN TIM6_DAC_IRQn 1 */ /* USER CODE END TIM6_DAC_IRQn 1 */ } 8005d36: bf00 nop 8005d38: bd80 pop {r7, pc} 8005d3a: bf00 nop 8005d3c: 20000b14 .word 0x20000b14 08005d40 <_read>: _kill(status, -1); while (1) {} /* Make sure we hang here */ } __attribute__((weak)) int _read(int file, char *ptr, int len) { 8005d40: b580 push {r7, lr} 8005d42: b086 sub sp, #24 8005d44: af00 add r7, sp, #0 8005d46: 60f8 str r0, [r7, #12] 8005d48: 60b9 str r1, [r7, #8] 8005d4a: 607a str r2, [r7, #4] int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 8005d4c: 2300 movs r3, #0 8005d4e: 617b str r3, [r7, #20] 8005d50: e00a b.n 8005d68 <_read+0x28> { *ptr++ = __io_getchar(); 8005d52: f3af 8000 nop.w 8005d56: 4601 mov r1, r0 8005d58: 68bb ldr r3, [r7, #8] 8005d5a: 1c5a adds r2, r3, #1 8005d5c: 60ba str r2, [r7, #8] 8005d5e: b2ca uxtb r2, r1 8005d60: 701a strb r2, [r3, #0] for (DataIdx = 0; DataIdx < len; DataIdx++) 8005d62: 697b ldr r3, [r7, #20] 8005d64: 3301 adds r3, #1 8005d66: 617b str r3, [r7, #20] 8005d68: 697a ldr r2, [r7, #20] 8005d6a: 687b ldr r3, [r7, #4] 8005d6c: 429a cmp r2, r3 8005d6e: dbf0 blt.n 8005d52 <_read+0x12> } return len; 8005d70: 687b ldr r3, [r7, #4] } 8005d72: 4618 mov r0, r3 8005d74: 3718 adds r7, #24 8005d76: 46bd mov sp, r7 8005d78: bd80 pop {r7, pc} 08005d7a <_close>: } return len; } int _close(int file) { 8005d7a: b480 push {r7} 8005d7c: b083 sub sp, #12 8005d7e: af00 add r7, sp, #0 8005d80: 6078 str r0, [r7, #4] return -1; 8005d82: f04f 33ff mov.w r3, #4294967295 } 8005d86: 4618 mov r0, r3 8005d88: 370c adds r7, #12 8005d8a: 46bd mov sp, r7 8005d8c: bc80 pop {r7} 8005d8e: 4770 bx lr 08005d90 <_fstat>: int _fstat(int file, struct stat *st) { 8005d90: b480 push {r7} 8005d92: b083 sub sp, #12 8005d94: af00 add r7, sp, #0 8005d96: 6078 str r0, [r7, #4] 8005d98: 6039 str r1, [r7, #0] st->st_mode = S_IFCHR; 8005d9a: 683b ldr r3, [r7, #0] 8005d9c: f44f 5200 mov.w r2, #8192 ; 0x2000 8005da0: 605a str r2, [r3, #4] return 0; 8005da2: 2300 movs r3, #0 } 8005da4: 4618 mov r0, r3 8005da6: 370c adds r7, #12 8005da8: 46bd mov sp, r7 8005daa: bc80 pop {r7} 8005dac: 4770 bx lr 08005dae <_isatty>: int _isatty(int file) { 8005dae: b480 push {r7} 8005db0: b083 sub sp, #12 8005db2: af00 add r7, sp, #0 8005db4: 6078 str r0, [r7, #4] return 1; 8005db6: 2301 movs r3, #1 } 8005db8: 4618 mov r0, r3 8005dba: 370c adds r7, #12 8005dbc: 46bd mov sp, r7 8005dbe: bc80 pop {r7} 8005dc0: 4770 bx lr 08005dc2 <_lseek>: int _lseek(int file, int ptr, int dir) { 8005dc2: b480 push {r7} 8005dc4: b085 sub sp, #20 8005dc6: af00 add r7, sp, #0 8005dc8: 60f8 str r0, [r7, #12] 8005dca: 60b9 str r1, [r7, #8] 8005dcc: 607a str r2, [r7, #4] return 0; 8005dce: 2300 movs r3, #0 } 8005dd0: 4618 mov r0, r3 8005dd2: 3714 adds r7, #20 8005dd4: 46bd mov sp, r7 8005dd6: bc80 pop {r7} 8005dd8: 4770 bx lr ... 08005ddc <_sbrk>: /** _sbrk Increase program data space. Malloc and related functions depend on this **/ caddr_t _sbrk(int incr) { 8005ddc: b580 push {r7, lr} 8005dde: b084 sub sp, #16 8005de0: af00 add r7, sp, #0 8005de2: 6078 str r0, [r7, #4] extern char end asm("end"); static char *heap_end; char *prev_heap_end; if (heap_end == 0) 8005de4: 4b11 ldr r3, [pc, #68] ; (8005e2c <_sbrk+0x50>) 8005de6: 681b ldr r3, [r3, #0] 8005de8: 2b00 cmp r3, #0 8005dea: d102 bne.n 8005df2 <_sbrk+0x16> heap_end = &end; 8005dec: 4b0f ldr r3, [pc, #60] ; (8005e2c <_sbrk+0x50>) 8005dee: 4a10 ldr r2, [pc, #64] ; (8005e30 <_sbrk+0x54>) 8005df0: 601a str r2, [r3, #0] prev_heap_end = heap_end; 8005df2: 4b0e ldr r3, [pc, #56] ; (8005e2c <_sbrk+0x50>) 8005df4: 681b ldr r3, [r3, #0] 8005df6: 60fb str r3, [r7, #12] if (heap_end + incr > stack_ptr) 8005df8: 4b0c ldr r3, [pc, #48] ; (8005e2c <_sbrk+0x50>) 8005dfa: 681a ldr r2, [r3, #0] 8005dfc: 687b ldr r3, [r7, #4] 8005dfe: 4413 add r3, r2 8005e00: 466a mov r2, sp 8005e02: 4293 cmp r3, r2 8005e04: d907 bls.n 8005e16 <_sbrk+0x3a> { errno = ENOMEM; 8005e06: f000 f873 bl 8005ef0 <__errno> 8005e0a: 4602 mov r2, r0 8005e0c: 230c movs r3, #12 8005e0e: 6013 str r3, [r2, #0] return (caddr_t) -1; 8005e10: f04f 33ff mov.w r3, #4294967295 8005e14: e006 b.n 8005e24 <_sbrk+0x48> } heap_end += incr; 8005e16: 4b05 ldr r3, [pc, #20] ; (8005e2c <_sbrk+0x50>) 8005e18: 681a ldr r2, [r3, #0] 8005e1a: 687b ldr r3, [r7, #4] 8005e1c: 4413 add r3, r2 8005e1e: 4a03 ldr r2, [pc, #12] ; (8005e2c <_sbrk+0x50>) 8005e20: 6013 str r3, [r2, #0] return (caddr_t) prev_heap_end; 8005e22: 68fb ldr r3, [r7, #12] } 8005e24: 4618 mov r0, r3 8005e26: 3710 adds r7, #16 8005e28: 46bd mov sp, r7 8005e2a: bd80 pop {r7, pc} 8005e2c: 2000063c .word 0x2000063c 8005e30: 20000b98 .word 0x20000b98 08005e34 : * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit (void) { 8005e34: b480 push {r7} 8005e36: af00 add r7, sp, #0 /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ /* Set HSION bit */ RCC->CR |= 0x00000001U; 8005e38: 4b17 ldr r3, [pc, #92] ; (8005e98 ) 8005e3a: 681b ldr r3, [r3, #0] 8005e3c: 4a16 ldr r2, [pc, #88] ; (8005e98 ) 8005e3e: f043 0301 orr.w r3, r3, #1 8005e42: 6013 str r3, [r2, #0] /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ #if !defined(STM32F105xC) && !defined(STM32F107xC) RCC->CFGR &= 0xF8FF0000U; 8005e44: 4b14 ldr r3, [pc, #80] ; (8005e98 ) 8005e46: 685a ldr r2, [r3, #4] 8005e48: 4913 ldr r1, [pc, #76] ; (8005e98 ) 8005e4a: 4b14 ldr r3, [pc, #80] ; (8005e9c ) 8005e4c: 4013 ands r3, r2 8005e4e: 604b str r3, [r1, #4] #else RCC->CFGR &= 0xF0FF0000U; #endif /* STM32F105xC */ /* Reset HSEON, CSSON and PLLON bits */ RCC->CR &= 0xFEF6FFFFU; 8005e50: 4b11 ldr r3, [pc, #68] ; (8005e98 ) 8005e52: 681b ldr r3, [r3, #0] 8005e54: 4a10 ldr r2, [pc, #64] ; (8005e98 ) 8005e56: f023 7384 bic.w r3, r3, #17301504 ; 0x1080000 8005e5a: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8005e5e: 6013 str r3, [r2, #0] /* Reset HSEBYP bit */ RCC->CR &= 0xFFFBFFFFU; 8005e60: 4b0d ldr r3, [pc, #52] ; (8005e98 ) 8005e62: 681b ldr r3, [r3, #0] 8005e64: 4a0c ldr r2, [pc, #48] ; (8005e98 ) 8005e66: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8005e6a: 6013 str r3, [r2, #0] /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ RCC->CFGR &= 0xFF80FFFFU; 8005e6c: 4b0a ldr r3, [pc, #40] ; (8005e98 ) 8005e6e: 685b ldr r3, [r3, #4] 8005e70: 4a09 ldr r2, [pc, #36] ; (8005e98 ) 8005e72: f423 03fe bic.w r3, r3, #8323072 ; 0x7f0000 8005e76: 6053 str r3, [r2, #4] /* Reset CFGR2 register */ RCC->CFGR2 = 0x00000000U; #elif defined(STM32F100xB) || defined(STM32F100xE) /* Disable all interrupts and clear pending bits */ RCC->CIR = 0x009F0000U; 8005e78: 4b07 ldr r3, [pc, #28] ; (8005e98 ) 8005e7a: f44f 021f mov.w r2, #10420224 ; 0x9f0000 8005e7e: 609a str r2, [r3, #8] /* Reset CFGR2 register */ RCC->CFGR2 = 0x00000000U; 8005e80: 4b05 ldr r3, [pc, #20] ; (8005e98 ) 8005e82: 2200 movs r2, #0 8005e84: 62da str r2, [r3, #44] ; 0x2c #endif #ifdef VECT_TAB_SRAM SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #else SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ 8005e86: 4b06 ldr r3, [pc, #24] ; (8005ea0 ) 8005e88: f04f 6200 mov.w r2, #134217728 ; 0x8000000 8005e8c: 609a str r2, [r3, #8] #endif } 8005e8e: bf00 nop 8005e90: 46bd mov sp, r7 8005e92: bc80 pop {r7} 8005e94: 4770 bx lr 8005e96: bf00 nop 8005e98: 40021000 .word 0x40021000 8005e9c: f8ff0000 .word 0xf8ff0000 8005ea0: e000ed00 .word 0xe000ed00 08005ea4 : .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 8005ea4: 2100 movs r1, #0 b LoopCopyDataInit 8005ea6: e003 b.n 8005eb0 08005ea8 : CopyDataInit: ldr r3, =_sidata 8005ea8: 4b0b ldr r3, [pc, #44] ; (8005ed8 ) ldr r3, [r3, r1] 8005eaa: 585b ldr r3, [r3, r1] str r3, [r0, r1] 8005eac: 5043 str r3, [r0, r1] adds r1, r1, #4 8005eae: 3104 adds r1, #4 08005eb0 : LoopCopyDataInit: ldr r0, =_sdata 8005eb0: 480a ldr r0, [pc, #40] ; (8005edc ) ldr r3, =_edata 8005eb2: 4b0b ldr r3, [pc, #44] ; (8005ee0 ) adds r2, r0, r1 8005eb4: 1842 adds r2, r0, r1 cmp r2, r3 8005eb6: 429a cmp r2, r3 bcc CopyDataInit 8005eb8: d3f6 bcc.n 8005ea8 ldr r2, =_sbss 8005eba: 4a0a ldr r2, [pc, #40] ; (8005ee4 ) b LoopFillZerobss 8005ebc: e002 b.n 8005ec4 08005ebe : /* Zero fill the bss segment. */ FillZerobss: movs r3, #0 8005ebe: 2300 movs r3, #0 str r3, [r2], #4 8005ec0: f842 3b04 str.w r3, [r2], #4 08005ec4 : LoopFillZerobss: ldr r3, = _ebss 8005ec4: 4b08 ldr r3, [pc, #32] ; (8005ee8 ) cmp r2, r3 8005ec6: 429a cmp r2, r3 bcc FillZerobss 8005ec8: d3f9 bcc.n 8005ebe /* Call the clock system intitialization function.*/ bl SystemInit 8005eca: f7ff ffb3 bl 8005e34 /* Call static constructors */ bl __libc_init_array 8005ece: f000 f815 bl 8005efc <__libc_init_array> /* Call the application's entry point.*/ bl main 8005ed2: f7ff f947 bl 8005164
bx lr 8005ed6: 4770 bx lr ldr r3, =_sidata 8005ed8: 08008e78 .word 0x08008e78 ldr r0, =_sdata 8005edc: 20000000 .word 0x20000000 ldr r3, =_edata 8005ee0: 200001dc .word 0x200001dc ldr r2, =_sbss 8005ee4: 200001e0 .word 0x200001e0 ldr r3, = _ebss 8005ee8: 20000b98 .word 0x20000b98 08005eec : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8005eec: e7fe b.n 8005eec ... 08005ef0 <__errno>: 8005ef0: 4b01 ldr r3, [pc, #4] ; (8005ef8 <__errno+0x8>) 8005ef2: 6818 ldr r0, [r3, #0] 8005ef4: 4770 bx lr 8005ef6: bf00 nop 8005ef8: 2000000c .word 0x2000000c 08005efc <__libc_init_array>: 8005efc: b570 push {r4, r5, r6, lr} 8005efe: 2500 movs r5, #0 8005f00: 4e0c ldr r6, [pc, #48] ; (8005f34 <__libc_init_array+0x38>) 8005f02: 4c0d ldr r4, [pc, #52] ; (8005f38 <__libc_init_array+0x3c>) 8005f04: 1ba4 subs r4, r4, r6 8005f06: 10a4 asrs r4, r4, #2 8005f08: 42a5 cmp r5, r4 8005f0a: d109 bne.n 8005f20 <__libc_init_array+0x24> 8005f0c: f002 fc62 bl 80087d4 <_init> 8005f10: 2500 movs r5, #0 8005f12: 4e0a ldr r6, [pc, #40] ; (8005f3c <__libc_init_array+0x40>) 8005f14: 4c0a ldr r4, [pc, #40] ; (8005f40 <__libc_init_array+0x44>) 8005f16: 1ba4 subs r4, r4, r6 8005f18: 10a4 asrs r4, r4, #2 8005f1a: 42a5 cmp r5, r4 8005f1c: d105 bne.n 8005f2a <__libc_init_array+0x2e> 8005f1e: bd70 pop {r4, r5, r6, pc} 8005f20: f856 3025 ldr.w r3, [r6, r5, lsl #2] 8005f24: 4798 blx r3 8005f26: 3501 adds r5, #1 8005f28: e7ee b.n 8005f08 <__libc_init_array+0xc> 8005f2a: f856 3025 ldr.w r3, [r6, r5, lsl #2] 8005f2e: 4798 blx r3 8005f30: 3501 adds r5, #1 8005f32: e7f2 b.n 8005f1a <__libc_init_array+0x1e> 8005f34: 08008e70 .word 0x08008e70 8005f38: 08008e70 .word 0x08008e70 8005f3c: 08008e70 .word 0x08008e70 8005f40: 08008e74 .word 0x08008e74 08005f44 : 8005f44: 4603 mov r3, r0 8005f46: 4402 add r2, r0 8005f48: 4293 cmp r3, r2 8005f4a: d100 bne.n 8005f4e 8005f4c: 4770 bx lr 8005f4e: f803 1b01 strb.w r1, [r3], #1 8005f52: e7f9 b.n 8005f48 08005f54 <__cvt>: 8005f54: 2b00 cmp r3, #0 8005f56: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8005f5a: 461e mov r6, r3 8005f5c: bfbb ittet lt 8005f5e: f103 4300 addlt.w r3, r3, #2147483648 ; 0x80000000 8005f62: 461e movlt r6, r3 8005f64: 2300 movge r3, #0 8005f66: 232d movlt r3, #45 ; 0x2d 8005f68: b088 sub sp, #32 8005f6a: 9f14 ldr r7, [sp, #80] ; 0x50 8005f6c: e9dd 1a12 ldrd r1, sl, [sp, #72] ; 0x48 8005f70: f027 0720 bic.w r7, r7, #32 8005f74: 2f46 cmp r7, #70 ; 0x46 8005f76: 4614 mov r4, r2 8005f78: 9d10 ldr r5, [sp, #64] ; 0x40 8005f7a: 700b strb r3, [r1, #0] 8005f7c: d004 beq.n 8005f88 <__cvt+0x34> 8005f7e: 2f45 cmp r7, #69 ; 0x45 8005f80: d100 bne.n 8005f84 <__cvt+0x30> 8005f82: 3501 adds r5, #1 8005f84: 2302 movs r3, #2 8005f86: e000 b.n 8005f8a <__cvt+0x36> 8005f88: 2303 movs r3, #3 8005f8a: aa07 add r2, sp, #28 8005f8c: 9204 str r2, [sp, #16] 8005f8e: aa06 add r2, sp, #24 8005f90: e9cd a202 strd sl, r2, [sp, #8] 8005f94: e9cd 3500 strd r3, r5, [sp] 8005f98: 4622 mov r2, r4 8005f9a: 4633 mov r3, r6 8005f9c: f000 feac bl 8006cf8 <_dtoa_r> 8005fa0: 2f47 cmp r7, #71 ; 0x47 8005fa2: 4680 mov r8, r0 8005fa4: d102 bne.n 8005fac <__cvt+0x58> 8005fa6: 9b11 ldr r3, [sp, #68] ; 0x44 8005fa8: 07db lsls r3, r3, #31 8005faa: d526 bpl.n 8005ffa <__cvt+0xa6> 8005fac: 2f46 cmp r7, #70 ; 0x46 8005fae: eb08 0905 add.w r9, r8, r5 8005fb2: d111 bne.n 8005fd8 <__cvt+0x84> 8005fb4: f898 3000 ldrb.w r3, [r8] 8005fb8: 2b30 cmp r3, #48 ; 0x30 8005fba: d10a bne.n 8005fd2 <__cvt+0x7e> 8005fbc: 2200 movs r2, #0 8005fbe: 2300 movs r3, #0 8005fc0: 4620 mov r0, r4 8005fc2: 4631 mov r1, r6 8005fc4: f7fa fd50 bl 8000a68 <__aeabi_dcmpeq> 8005fc8: b918 cbnz r0, 8005fd2 <__cvt+0x7e> 8005fca: f1c5 0501 rsb r5, r5, #1 8005fce: f8ca 5000 str.w r5, [sl] 8005fd2: f8da 3000 ldr.w r3, [sl] 8005fd6: 4499 add r9, r3 8005fd8: 2200 movs r2, #0 8005fda: 2300 movs r3, #0 8005fdc: 4620 mov r0, r4 8005fde: 4631 mov r1, r6 8005fe0: f7fa fd42 bl 8000a68 <__aeabi_dcmpeq> 8005fe4: b938 cbnz r0, 8005ff6 <__cvt+0xa2> 8005fe6: 2230 movs r2, #48 ; 0x30 8005fe8: 9b07 ldr r3, [sp, #28] 8005fea: 454b cmp r3, r9 8005fec: d205 bcs.n 8005ffa <__cvt+0xa6> 8005fee: 1c59 adds r1, r3, #1 8005ff0: 9107 str r1, [sp, #28] 8005ff2: 701a strb r2, [r3, #0] 8005ff4: e7f8 b.n 8005fe8 <__cvt+0x94> 8005ff6: f8cd 901c str.w r9, [sp, #28] 8005ffa: 4640 mov r0, r8 8005ffc: 9b07 ldr r3, [sp, #28] 8005ffe: 9a15 ldr r2, [sp, #84] ; 0x54 8006000: eba3 0308 sub.w r3, r3, r8 8006004: 6013 str r3, [r2, #0] 8006006: b008 add sp, #32 8006008: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 0800600c <__exponent>: 800600c: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} 800600e: 2900 cmp r1, #0 8006010: bfb4 ite lt 8006012: 232d movlt r3, #45 ; 0x2d 8006014: 232b movge r3, #43 ; 0x2b 8006016: 4604 mov r4, r0 8006018: bfb8 it lt 800601a: 4249 neglt r1, r1 800601c: 2909 cmp r1, #9 800601e: f804 2b02 strb.w r2, [r4], #2 8006022: 7043 strb r3, [r0, #1] 8006024: dd21 ble.n 800606a <__exponent+0x5e> 8006026: f10d 0307 add.w r3, sp, #7 800602a: 461f mov r7, r3 800602c: 260a movs r6, #10 800602e: fb91 f5f6 sdiv r5, r1, r6 8006032: fb06 1115 mls r1, r6, r5, r1 8006036: 2d09 cmp r5, #9 8006038: f101 0130 add.w r1, r1, #48 ; 0x30 800603c: f803 1c01 strb.w r1, [r3, #-1] 8006040: f103 32ff add.w r2, r3, #4294967295 8006044: 4629 mov r1, r5 8006046: dc09 bgt.n 800605c <__exponent+0x50> 8006048: 3130 adds r1, #48 ; 0x30 800604a: 3b02 subs r3, #2 800604c: f802 1c01 strb.w r1, [r2, #-1] 8006050: 42bb cmp r3, r7 8006052: 4622 mov r2, r4 8006054: d304 bcc.n 8006060 <__exponent+0x54> 8006056: 1a10 subs r0, r2, r0 8006058: b003 add sp, #12 800605a: bdf0 pop {r4, r5, r6, r7, pc} 800605c: 4613 mov r3, r2 800605e: e7e6 b.n 800602e <__exponent+0x22> 8006060: f813 2b01 ldrb.w r2, [r3], #1 8006064: f804 2b01 strb.w r2, [r4], #1 8006068: e7f2 b.n 8006050 <__exponent+0x44> 800606a: 2330 movs r3, #48 ; 0x30 800606c: 4419 add r1, r3 800606e: 7083 strb r3, [r0, #2] 8006070: 1d02 adds r2, r0, #4 8006072: 70c1 strb r1, [r0, #3] 8006074: e7ef b.n 8006056 <__exponent+0x4a> ... 08006078 <_printf_float>: 8006078: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 800607c: b091 sub sp, #68 ; 0x44 800607e: 460c mov r4, r1 8006080: 9f1a ldr r7, [sp, #104] ; 0x68 8006082: 4693 mov fp, r2 8006084: 461e mov r6, r3 8006086: 4605 mov r5, r0 8006088: f001 fd64 bl 8007b54 <_localeconv_r> 800608c: 6803 ldr r3, [r0, #0] 800608e: 4618 mov r0, r3 8006090: 9309 str r3, [sp, #36] ; 0x24 8006092: f7fa f8bd bl 8000210 8006096: 2300 movs r3, #0 8006098: 930e str r3, [sp, #56] ; 0x38 800609a: 683b ldr r3, [r7, #0] 800609c: 900a str r0, [sp, #40] ; 0x28 800609e: 3307 adds r3, #7 80060a0: f023 0307 bic.w r3, r3, #7 80060a4: f103 0208 add.w r2, r3, #8 80060a8: f894 8018 ldrb.w r8, [r4, #24] 80060ac: f8d4 a000 ldr.w sl, [r4] 80060b0: 603a str r2, [r7, #0] 80060b2: e9d3 2300 ldrd r2, r3, [r3] 80060b6: e9c4 2312 strd r2, r3, [r4, #72] ; 0x48 80060ba: e9d4 7912 ldrd r7, r9, [r4, #72] ; 0x48 80060be: f029 4300 bic.w r3, r9, #2147483648 ; 0x80000000 80060c2: 930b str r3, [sp, #44] ; 0x2c 80060c4: f04f 32ff mov.w r2, #4294967295 80060c8: 4ba6 ldr r3, [pc, #664] ; (8006364 <_printf_float+0x2ec>) 80060ca: 4638 mov r0, r7 80060cc: 990b ldr r1, [sp, #44] ; 0x2c 80060ce: f7fa fcfd bl 8000acc <__aeabi_dcmpun> 80060d2: bb68 cbnz r0, 8006130 <_printf_float+0xb8> 80060d4: f04f 32ff mov.w r2, #4294967295 80060d8: 4ba2 ldr r3, [pc, #648] ; (8006364 <_printf_float+0x2ec>) 80060da: 4638 mov r0, r7 80060dc: 990b ldr r1, [sp, #44] ; 0x2c 80060de: f7fa fcd7 bl 8000a90 <__aeabi_dcmple> 80060e2: bb28 cbnz r0, 8006130 <_printf_float+0xb8> 80060e4: 2200 movs r2, #0 80060e6: 2300 movs r3, #0 80060e8: 4638 mov r0, r7 80060ea: 4649 mov r1, r9 80060ec: f7fa fcc6 bl 8000a7c <__aeabi_dcmplt> 80060f0: b110 cbz r0, 80060f8 <_printf_float+0x80> 80060f2: 232d movs r3, #45 ; 0x2d 80060f4: f884 3043 strb.w r3, [r4, #67] ; 0x43 80060f8: 4f9b ldr r7, [pc, #620] ; (8006368 <_printf_float+0x2f0>) 80060fa: 4b9c ldr r3, [pc, #624] ; (800636c <_printf_float+0x2f4>) 80060fc: f1b8 0f47 cmp.w r8, #71 ; 0x47 8006100: bf98 it ls 8006102: 461f movls r7, r3 8006104: 2303 movs r3, #3 8006106: f04f 0900 mov.w r9, #0 800610a: 6123 str r3, [r4, #16] 800610c: f02a 0304 bic.w r3, sl, #4 8006110: 6023 str r3, [r4, #0] 8006112: 9600 str r6, [sp, #0] 8006114: 465b mov r3, fp 8006116: aa0f add r2, sp, #60 ; 0x3c 8006118: 4621 mov r1, r4 800611a: 4628 mov r0, r5 800611c: f000 f9e2 bl 80064e4 <_printf_common> 8006120: 3001 adds r0, #1 8006122: f040 8090 bne.w 8006246 <_printf_float+0x1ce> 8006126: f04f 30ff mov.w r0, #4294967295 800612a: b011 add sp, #68 ; 0x44 800612c: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8006130: 463a mov r2, r7 8006132: 464b mov r3, r9 8006134: 4638 mov r0, r7 8006136: 4649 mov r1, r9 8006138: f7fa fcc8 bl 8000acc <__aeabi_dcmpun> 800613c: b110 cbz r0, 8006144 <_printf_float+0xcc> 800613e: 4f8c ldr r7, [pc, #560] ; (8006370 <_printf_float+0x2f8>) 8006140: 4b8c ldr r3, [pc, #560] ; (8006374 <_printf_float+0x2fc>) 8006142: e7db b.n 80060fc <_printf_float+0x84> 8006144: 6863 ldr r3, [r4, #4] 8006146: f44a 6280 orr.w r2, sl, #1024 ; 0x400 800614a: 1c59 adds r1, r3, #1 800614c: a80d add r0, sp, #52 ; 0x34 800614e: a90e add r1, sp, #56 ; 0x38 8006150: d140 bne.n 80061d4 <_printf_float+0x15c> 8006152: 2306 movs r3, #6 8006154: 6063 str r3, [r4, #4] 8006156: f04f 0c00 mov.w ip, #0 800615a: f10d 0333 add.w r3, sp, #51 ; 0x33 800615e: e9cd 2301 strd r2, r3, [sp, #4] 8006162: 6863 ldr r3, [r4, #4] 8006164: 6022 str r2, [r4, #0] 8006166: e9cd 0803 strd r0, r8, [sp, #12] 800616a: 9300 str r3, [sp, #0] 800616c: 463a mov r2, r7 800616e: 464b mov r3, r9 8006170: e9cd 1c05 strd r1, ip, [sp, #20] 8006174: 4628 mov r0, r5 8006176: f7ff feed bl 8005f54 <__cvt> 800617a: f008 03df and.w r3, r8, #223 ; 0xdf 800617e: 2b47 cmp r3, #71 ; 0x47 8006180: 4607 mov r7, r0 8006182: d109 bne.n 8006198 <_printf_float+0x120> 8006184: 9b0d ldr r3, [sp, #52] ; 0x34 8006186: 1cd8 adds r0, r3, #3 8006188: db02 blt.n 8006190 <_printf_float+0x118> 800618a: 6862 ldr r2, [r4, #4] 800618c: 4293 cmp r3, r2 800618e: dd47 ble.n 8006220 <_printf_float+0x1a8> 8006190: f1a8 0802 sub.w r8, r8, #2 8006194: fa5f f888 uxtb.w r8, r8 8006198: f1b8 0f65 cmp.w r8, #101 ; 0x65 800619c: 990d ldr r1, [sp, #52] ; 0x34 800619e: d824 bhi.n 80061ea <_printf_float+0x172> 80061a0: 3901 subs r1, #1 80061a2: 4642 mov r2, r8 80061a4: f104 0050 add.w r0, r4, #80 ; 0x50 80061a8: 910d str r1, [sp, #52] ; 0x34 80061aa: f7ff ff2f bl 800600c <__exponent> 80061ae: 9a0e ldr r2, [sp, #56] ; 0x38 80061b0: 4681 mov r9, r0 80061b2: 1813 adds r3, r2, r0 80061b4: 2a01 cmp r2, #1 80061b6: 6123 str r3, [r4, #16] 80061b8: dc02 bgt.n 80061c0 <_printf_float+0x148> 80061ba: 6822 ldr r2, [r4, #0] 80061bc: 07d1 lsls r1, r2, #31 80061be: d501 bpl.n 80061c4 <_printf_float+0x14c> 80061c0: 3301 adds r3, #1 80061c2: 6123 str r3, [r4, #16] 80061c4: f89d 3033 ldrb.w r3, [sp, #51] ; 0x33 80061c8: 2b00 cmp r3, #0 80061ca: d0a2 beq.n 8006112 <_printf_float+0x9a> 80061cc: 232d movs r3, #45 ; 0x2d 80061ce: f884 3043 strb.w r3, [r4, #67] ; 0x43 80061d2: e79e b.n 8006112 <_printf_float+0x9a> 80061d4: f1b8 0f67 cmp.w r8, #103 ; 0x67 80061d8: f000 816e beq.w 80064b8 <_printf_float+0x440> 80061dc: f1b8 0f47 cmp.w r8, #71 ; 0x47 80061e0: d1b9 bne.n 8006156 <_printf_float+0xde> 80061e2: 2b00 cmp r3, #0 80061e4: d1b7 bne.n 8006156 <_printf_float+0xde> 80061e6: 2301 movs r3, #1 80061e8: e7b4 b.n 8006154 <_printf_float+0xdc> 80061ea: f1b8 0f66 cmp.w r8, #102 ; 0x66 80061ee: d119 bne.n 8006224 <_printf_float+0x1ac> 80061f0: 2900 cmp r1, #0 80061f2: 6863 ldr r3, [r4, #4] 80061f4: dd0c ble.n 8006210 <_printf_float+0x198> 80061f6: 6121 str r1, [r4, #16] 80061f8: b913 cbnz r3, 8006200 <_printf_float+0x188> 80061fa: 6822 ldr r2, [r4, #0] 80061fc: 07d2 lsls r2, r2, #31 80061fe: d502 bpl.n 8006206 <_printf_float+0x18e> 8006200: 3301 adds r3, #1 8006202: 440b add r3, r1 8006204: 6123 str r3, [r4, #16] 8006206: 9b0d ldr r3, [sp, #52] ; 0x34 8006208: f04f 0900 mov.w r9, #0 800620c: 65a3 str r3, [r4, #88] ; 0x58 800620e: e7d9 b.n 80061c4 <_printf_float+0x14c> 8006210: b913 cbnz r3, 8006218 <_printf_float+0x1a0> 8006212: 6822 ldr r2, [r4, #0] 8006214: 07d0 lsls r0, r2, #31 8006216: d501 bpl.n 800621c <_printf_float+0x1a4> 8006218: 3302 adds r3, #2 800621a: e7f3 b.n 8006204 <_printf_float+0x18c> 800621c: 2301 movs r3, #1 800621e: e7f1 b.n 8006204 <_printf_float+0x18c> 8006220: f04f 0867 mov.w r8, #103 ; 0x67 8006224: e9dd 320d ldrd r3, r2, [sp, #52] ; 0x34 8006228: 4293 cmp r3, r2 800622a: db05 blt.n 8006238 <_printf_float+0x1c0> 800622c: 6822 ldr r2, [r4, #0] 800622e: 6123 str r3, [r4, #16] 8006230: 07d1 lsls r1, r2, #31 8006232: d5e8 bpl.n 8006206 <_printf_float+0x18e> 8006234: 3301 adds r3, #1 8006236: e7e5 b.n 8006204 <_printf_float+0x18c> 8006238: 2b00 cmp r3, #0 800623a: bfcc ite gt 800623c: 2301 movgt r3, #1 800623e: f1c3 0302 rsble r3, r3, #2 8006242: 4413 add r3, r2 8006244: e7de b.n 8006204 <_printf_float+0x18c> 8006246: 6823 ldr r3, [r4, #0] 8006248: 055a lsls r2, r3, #21 800624a: d407 bmi.n 800625c <_printf_float+0x1e4> 800624c: 6923 ldr r3, [r4, #16] 800624e: 463a mov r2, r7 8006250: 4659 mov r1, fp 8006252: 4628 mov r0, r5 8006254: 47b0 blx r6 8006256: 3001 adds r0, #1 8006258: d129 bne.n 80062ae <_printf_float+0x236> 800625a: e764 b.n 8006126 <_printf_float+0xae> 800625c: f1b8 0f65 cmp.w r8, #101 ; 0x65 8006260: f240 80d7 bls.w 8006412 <_printf_float+0x39a> 8006264: e9d4 0112 ldrd r0, r1, [r4, #72] ; 0x48 8006268: 2200 movs r2, #0 800626a: 2300 movs r3, #0 800626c: f7fa fbfc bl 8000a68 <__aeabi_dcmpeq> 8006270: b388 cbz r0, 80062d6 <_printf_float+0x25e> 8006272: 2301 movs r3, #1 8006274: 4a40 ldr r2, [pc, #256] ; (8006378 <_printf_float+0x300>) 8006276: 4659 mov r1, fp 8006278: 4628 mov r0, r5 800627a: 47b0 blx r6 800627c: 3001 adds r0, #1 800627e: f43f af52 beq.w 8006126 <_printf_float+0xae> 8006282: e9dd 230d ldrd r2, r3, [sp, #52] ; 0x34 8006286: 429a cmp r2, r3 8006288: db02 blt.n 8006290 <_printf_float+0x218> 800628a: 6823 ldr r3, [r4, #0] 800628c: 07d8 lsls r0, r3, #31 800628e: d50e bpl.n 80062ae <_printf_float+0x236> 8006290: e9dd 2309 ldrd r2, r3, [sp, #36] ; 0x24 8006294: 4659 mov r1, fp 8006296: 4628 mov r0, r5 8006298: 47b0 blx r6 800629a: 3001 adds r0, #1 800629c: f43f af43 beq.w 8006126 <_printf_float+0xae> 80062a0: 2700 movs r7, #0 80062a2: f104 081a add.w r8, r4, #26 80062a6: 9b0e ldr r3, [sp, #56] ; 0x38 80062a8: 3b01 subs r3, #1 80062aa: 42bb cmp r3, r7 80062ac: dc09 bgt.n 80062c2 <_printf_float+0x24a> 80062ae: 6823 ldr r3, [r4, #0] 80062b0: 079f lsls r7, r3, #30 80062b2: f100 80fd bmi.w 80064b0 <_printf_float+0x438> 80062b6: 68e0 ldr r0, [r4, #12] 80062b8: 9b0f ldr r3, [sp, #60] ; 0x3c 80062ba: 4298 cmp r0, r3 80062bc: bfb8 it lt 80062be: 4618 movlt r0, r3 80062c0: e733 b.n 800612a <_printf_float+0xb2> 80062c2: 2301 movs r3, #1 80062c4: 4642 mov r2, r8 80062c6: 4659 mov r1, fp 80062c8: 4628 mov r0, r5 80062ca: 47b0 blx r6 80062cc: 3001 adds r0, #1 80062ce: f43f af2a beq.w 8006126 <_printf_float+0xae> 80062d2: 3701 adds r7, #1 80062d4: e7e7 b.n 80062a6 <_printf_float+0x22e> 80062d6: 9b0d ldr r3, [sp, #52] ; 0x34 80062d8: 2b00 cmp r3, #0 80062da: dc2b bgt.n 8006334 <_printf_float+0x2bc> 80062dc: 2301 movs r3, #1 80062de: 4a26 ldr r2, [pc, #152] ; (8006378 <_printf_float+0x300>) 80062e0: 4659 mov r1, fp 80062e2: 4628 mov r0, r5 80062e4: 47b0 blx r6 80062e6: 3001 adds r0, #1 80062e8: f43f af1d beq.w 8006126 <_printf_float+0xae> 80062ec: 9b0d ldr r3, [sp, #52] ; 0x34 80062ee: b923 cbnz r3, 80062fa <_printf_float+0x282> 80062f0: 9b0e ldr r3, [sp, #56] ; 0x38 80062f2: b913 cbnz r3, 80062fa <_printf_float+0x282> 80062f4: 6823 ldr r3, [r4, #0] 80062f6: 07d9 lsls r1, r3, #31 80062f8: d5d9 bpl.n 80062ae <_printf_float+0x236> 80062fa: e9dd 2309 ldrd r2, r3, [sp, #36] ; 0x24 80062fe: 4659 mov r1, fp 8006300: 4628 mov r0, r5 8006302: 47b0 blx r6 8006304: 3001 adds r0, #1 8006306: f43f af0e beq.w 8006126 <_printf_float+0xae> 800630a: f04f 0800 mov.w r8, #0 800630e: f104 091a add.w r9, r4, #26 8006312: 9b0d ldr r3, [sp, #52] ; 0x34 8006314: 425b negs r3, r3 8006316: 4543 cmp r3, r8 8006318: dc01 bgt.n 800631e <_printf_float+0x2a6> 800631a: 9b0e ldr r3, [sp, #56] ; 0x38 800631c: e797 b.n 800624e <_printf_float+0x1d6> 800631e: 2301 movs r3, #1 8006320: 464a mov r2, r9 8006322: 4659 mov r1, fp 8006324: 4628 mov r0, r5 8006326: 47b0 blx r6 8006328: 3001 adds r0, #1 800632a: f43f aefc beq.w 8006126 <_printf_float+0xae> 800632e: f108 0801 add.w r8, r8, #1 8006332: e7ee b.n 8006312 <_printf_float+0x29a> 8006334: 9a0e ldr r2, [sp, #56] ; 0x38 8006336: 6da3 ldr r3, [r4, #88] ; 0x58 8006338: 429a cmp r2, r3 800633a: bfa8 it ge 800633c: 461a movge r2, r3 800633e: 2a00 cmp r2, #0 8006340: 4690 mov r8, r2 8006342: dd07 ble.n 8006354 <_printf_float+0x2dc> 8006344: 4613 mov r3, r2 8006346: 4659 mov r1, fp 8006348: 463a mov r2, r7 800634a: 4628 mov r0, r5 800634c: 47b0 blx r6 800634e: 3001 adds r0, #1 8006350: f43f aee9 beq.w 8006126 <_printf_float+0xae> 8006354: f104 031a add.w r3, r4, #26 8006358: f04f 0a00 mov.w sl, #0 800635c: ea28 78e8 bic.w r8, r8, r8, asr #31 8006360: 930b str r3, [sp, #44] ; 0x2c 8006362: e015 b.n 8006390 <_printf_float+0x318> 8006364: 7fefffff .word 0x7fefffff 8006368: 08008bb8 .word 0x08008bb8 800636c: 08008bb4 .word 0x08008bb4 8006370: 08008bc0 .word 0x08008bc0 8006374: 08008bbc .word 0x08008bbc 8006378: 08008bc4 .word 0x08008bc4 800637c: 2301 movs r3, #1 800637e: 9a0b ldr r2, [sp, #44] ; 0x2c 8006380: 4659 mov r1, fp 8006382: 4628 mov r0, r5 8006384: 47b0 blx r6 8006386: 3001 adds r0, #1 8006388: f43f aecd beq.w 8006126 <_printf_float+0xae> 800638c: f10a 0a01 add.w sl, sl, #1 8006390: f8d4 9058 ldr.w r9, [r4, #88] ; 0x58 8006394: eba9 0308 sub.w r3, r9, r8 8006398: 4553 cmp r3, sl 800639a: dcef bgt.n 800637c <_printf_float+0x304> 800639c: e9dd 230d ldrd r2, r3, [sp, #52] ; 0x34 80063a0: 429a cmp r2, r3 80063a2: 444f add r7, r9 80063a4: db14 blt.n 80063d0 <_printf_float+0x358> 80063a6: 6823 ldr r3, [r4, #0] 80063a8: 07da lsls r2, r3, #31 80063aa: d411 bmi.n 80063d0 <_printf_float+0x358> 80063ac: 9b0e ldr r3, [sp, #56] ; 0x38 80063ae: 990d ldr r1, [sp, #52] ; 0x34 80063b0: eba3 0209 sub.w r2, r3, r9 80063b4: eba3 0901 sub.w r9, r3, r1 80063b8: 4591 cmp r9, r2 80063ba: bfa8 it ge 80063bc: 4691 movge r9, r2 80063be: f1b9 0f00 cmp.w r9, #0 80063c2: dc0d bgt.n 80063e0 <_printf_float+0x368> 80063c4: 2700 movs r7, #0 80063c6: ea29 79e9 bic.w r9, r9, r9, asr #31 80063ca: f104 081a add.w r8, r4, #26 80063ce: e018 b.n 8006402 <_printf_float+0x38a> 80063d0: e9dd 2309 ldrd r2, r3, [sp, #36] ; 0x24 80063d4: 4659 mov r1, fp 80063d6: 4628 mov r0, r5 80063d8: 47b0 blx r6 80063da: 3001 adds r0, #1 80063dc: d1e6 bne.n 80063ac <_printf_float+0x334> 80063de: e6a2 b.n 8006126 <_printf_float+0xae> 80063e0: 464b mov r3, r9 80063e2: 463a mov r2, r7 80063e4: 4659 mov r1, fp 80063e6: 4628 mov r0, r5 80063e8: 47b0 blx r6 80063ea: 3001 adds r0, #1 80063ec: d1ea bne.n 80063c4 <_printf_float+0x34c> 80063ee: e69a b.n 8006126 <_printf_float+0xae> 80063f0: 2301 movs r3, #1 80063f2: 4642 mov r2, r8 80063f4: 4659 mov r1, fp 80063f6: 4628 mov r0, r5 80063f8: 47b0 blx r6 80063fa: 3001 adds r0, #1 80063fc: f43f ae93 beq.w 8006126 <_printf_float+0xae> 8006400: 3701 adds r7, #1 8006402: e9dd 230d ldrd r2, r3, [sp, #52] ; 0x34 8006406: 1a9b subs r3, r3, r2 8006408: eba3 0309 sub.w r3, r3, r9 800640c: 42bb cmp r3, r7 800640e: dcef bgt.n 80063f0 <_printf_float+0x378> 8006410: e74d b.n 80062ae <_printf_float+0x236> 8006412: 9a0e ldr r2, [sp, #56] ; 0x38 8006414: 2a01 cmp r2, #1 8006416: dc01 bgt.n 800641c <_printf_float+0x3a4> 8006418: 07db lsls r3, r3, #31 800641a: d538 bpl.n 800648e <_printf_float+0x416> 800641c: 2301 movs r3, #1 800641e: 463a mov r2, r7 8006420: 4659 mov r1, fp 8006422: 4628 mov r0, r5 8006424: 47b0 blx r6 8006426: 3001 adds r0, #1 8006428: f43f ae7d beq.w 8006126 <_printf_float+0xae> 800642c: e9dd 2309 ldrd r2, r3, [sp, #36] ; 0x24 8006430: 4659 mov r1, fp 8006432: 4628 mov r0, r5 8006434: 47b0 blx r6 8006436: 3001 adds r0, #1 8006438: f107 0701 add.w r7, r7, #1 800643c: f43f ae73 beq.w 8006126 <_printf_float+0xae> 8006440: e9d4 0112 ldrd r0, r1, [r4, #72] ; 0x48 8006444: 9b0e ldr r3, [sp, #56] ; 0x38 8006446: 2200 movs r2, #0 8006448: f103 38ff add.w r8, r3, #4294967295 800644c: 2300 movs r3, #0 800644e: f7fa fb0b bl 8000a68 <__aeabi_dcmpeq> 8006452: b9c0 cbnz r0, 8006486 <_printf_float+0x40e> 8006454: 4643 mov r3, r8 8006456: 463a mov r2, r7 8006458: 4659 mov r1, fp 800645a: 4628 mov r0, r5 800645c: 47b0 blx r6 800645e: 3001 adds r0, #1 8006460: d10d bne.n 800647e <_printf_float+0x406> 8006462: e660 b.n 8006126 <_printf_float+0xae> 8006464: 2301 movs r3, #1 8006466: 4642 mov r2, r8 8006468: 4659 mov r1, fp 800646a: 4628 mov r0, r5 800646c: 47b0 blx r6 800646e: 3001 adds r0, #1 8006470: f43f ae59 beq.w 8006126 <_printf_float+0xae> 8006474: 3701 adds r7, #1 8006476: 9b0e ldr r3, [sp, #56] ; 0x38 8006478: 3b01 subs r3, #1 800647a: 42bb cmp r3, r7 800647c: dcf2 bgt.n 8006464 <_printf_float+0x3ec> 800647e: 464b mov r3, r9 8006480: f104 0250 add.w r2, r4, #80 ; 0x50 8006484: e6e4 b.n 8006250 <_printf_float+0x1d8> 8006486: 2700 movs r7, #0 8006488: f104 081a add.w r8, r4, #26 800648c: e7f3 b.n 8006476 <_printf_float+0x3fe> 800648e: 2301 movs r3, #1 8006490: e7e1 b.n 8006456 <_printf_float+0x3de> 8006492: 2301 movs r3, #1 8006494: 4642 mov r2, r8 8006496: 4659 mov r1, fp 8006498: 4628 mov r0, r5 800649a: 47b0 blx r6 800649c: 3001 adds r0, #1 800649e: f43f ae42 beq.w 8006126 <_printf_float+0xae> 80064a2: 3701 adds r7, #1 80064a4: 68e3 ldr r3, [r4, #12] 80064a6: 9a0f ldr r2, [sp, #60] ; 0x3c 80064a8: 1a9b subs r3, r3, r2 80064aa: 42bb cmp r3, r7 80064ac: dcf1 bgt.n 8006492 <_printf_float+0x41a> 80064ae: e702 b.n 80062b6 <_printf_float+0x23e> 80064b0: 2700 movs r7, #0 80064b2: f104 0819 add.w r8, r4, #25 80064b6: e7f5 b.n 80064a4 <_printf_float+0x42c> 80064b8: 2b00 cmp r3, #0 80064ba: f43f ae94 beq.w 80061e6 <_printf_float+0x16e> 80064be: f04f 0c00 mov.w ip, #0 80064c2: e9cd 1c05 strd r1, ip, [sp, #20] 80064c6: f10d 0133 add.w r1, sp, #51 ; 0x33 80064ca: 6022 str r2, [r4, #0] 80064cc: e9cd 0803 strd r0, r8, [sp, #12] 80064d0: e9cd 2101 strd r2, r1, [sp, #4] 80064d4: 9300 str r3, [sp, #0] 80064d6: 463a mov r2, r7 80064d8: 464b mov r3, r9 80064da: 4628 mov r0, r5 80064dc: f7ff fd3a bl 8005f54 <__cvt> 80064e0: 4607 mov r7, r0 80064e2: e64f b.n 8006184 <_printf_float+0x10c> 080064e4 <_printf_common>: 80064e4: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 80064e8: 4691 mov r9, r2 80064ea: 461f mov r7, r3 80064ec: 688a ldr r2, [r1, #8] 80064ee: 690b ldr r3, [r1, #16] 80064f0: 4606 mov r6, r0 80064f2: 4293 cmp r3, r2 80064f4: bfb8 it lt 80064f6: 4613 movlt r3, r2 80064f8: f8c9 3000 str.w r3, [r9] 80064fc: f891 2043 ldrb.w r2, [r1, #67] ; 0x43 8006500: 460c mov r4, r1 8006502: f8dd 8020 ldr.w r8, [sp, #32] 8006506: b112 cbz r2, 800650e <_printf_common+0x2a> 8006508: 3301 adds r3, #1 800650a: f8c9 3000 str.w r3, [r9] 800650e: 6823 ldr r3, [r4, #0] 8006510: 0699 lsls r1, r3, #26 8006512: bf42 ittt mi 8006514: f8d9 3000 ldrmi.w r3, [r9] 8006518: 3302 addmi r3, #2 800651a: f8c9 3000 strmi.w r3, [r9] 800651e: 6825 ldr r5, [r4, #0] 8006520: f015 0506 ands.w r5, r5, #6 8006524: d107 bne.n 8006536 <_printf_common+0x52> 8006526: f104 0a19 add.w sl, r4, #25 800652a: 68e3 ldr r3, [r4, #12] 800652c: f8d9 2000 ldr.w r2, [r9] 8006530: 1a9b subs r3, r3, r2 8006532: 42ab cmp r3, r5 8006534: dc29 bgt.n 800658a <_printf_common+0xa6> 8006536: f894 3043 ldrb.w r3, [r4, #67] ; 0x43 800653a: 6822 ldr r2, [r4, #0] 800653c: 3300 adds r3, #0 800653e: bf18 it ne 8006540: 2301 movne r3, #1 8006542: 0692 lsls r2, r2, #26 8006544: d42e bmi.n 80065a4 <_printf_common+0xc0> 8006546: f104 0243 add.w r2, r4, #67 ; 0x43 800654a: 4639 mov r1, r7 800654c: 4630 mov r0, r6 800654e: 47c0 blx r8 8006550: 3001 adds r0, #1 8006552: d021 beq.n 8006598 <_printf_common+0xb4> 8006554: 6823 ldr r3, [r4, #0] 8006556: 68e5 ldr r5, [r4, #12] 8006558: f003 0306 and.w r3, r3, #6 800655c: 2b04 cmp r3, #4 800655e: bf18 it ne 8006560: 2500 movne r5, #0 8006562: f8d9 2000 ldr.w r2, [r9] 8006566: f04f 0900 mov.w r9, #0 800656a: bf08 it eq 800656c: 1aad subeq r5, r5, r2 800656e: 68a3 ldr r3, [r4, #8] 8006570: 6922 ldr r2, [r4, #16] 8006572: bf08 it eq 8006574: ea25 75e5 biceq.w r5, r5, r5, asr #31 8006578: 4293 cmp r3, r2 800657a: bfc4 itt gt 800657c: 1a9b subgt r3, r3, r2 800657e: 18ed addgt r5, r5, r3 8006580: 341a adds r4, #26 8006582: 454d cmp r5, r9 8006584: d11a bne.n 80065bc <_printf_common+0xd8> 8006586: 2000 movs r0, #0 8006588: e008 b.n 800659c <_printf_common+0xb8> 800658a: 2301 movs r3, #1 800658c: 4652 mov r2, sl 800658e: 4639 mov r1, r7 8006590: 4630 mov r0, r6 8006592: 47c0 blx r8 8006594: 3001 adds r0, #1 8006596: d103 bne.n 80065a0 <_printf_common+0xbc> 8006598: f04f 30ff mov.w r0, #4294967295 800659c: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80065a0: 3501 adds r5, #1 80065a2: e7c2 b.n 800652a <_printf_common+0x46> 80065a4: 2030 movs r0, #48 ; 0x30 80065a6: 18e1 adds r1, r4, r3 80065a8: f881 0043 strb.w r0, [r1, #67] ; 0x43 80065ac: 1c5a adds r2, r3, #1 80065ae: f894 1045 ldrb.w r1, [r4, #69] ; 0x45 80065b2: 4422 add r2, r4 80065b4: 3302 adds r3, #2 80065b6: f882 1043 strb.w r1, [r2, #67] ; 0x43 80065ba: e7c4 b.n 8006546 <_printf_common+0x62> 80065bc: 2301 movs r3, #1 80065be: 4622 mov r2, r4 80065c0: 4639 mov r1, r7 80065c2: 4630 mov r0, r6 80065c4: 47c0 blx r8 80065c6: 3001 adds r0, #1 80065c8: d0e6 beq.n 8006598 <_printf_common+0xb4> 80065ca: f109 0901 add.w r9, r9, #1 80065ce: e7d8 b.n 8006582 <_printf_common+0x9e> 080065d0 <_printf_i>: 80065d0: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} 80065d4: f101 0c43 add.w ip, r1, #67 ; 0x43 80065d8: 460c mov r4, r1 80065da: 7e09 ldrb r1, [r1, #24] 80065dc: b085 sub sp, #20 80065de: 296e cmp r1, #110 ; 0x6e 80065e0: 4617 mov r7, r2 80065e2: 4606 mov r6, r0 80065e4: 4698 mov r8, r3 80065e6: 9a0c ldr r2, [sp, #48] ; 0x30 80065e8: f000 80b3 beq.w 8006752 <_printf_i+0x182> 80065ec: d822 bhi.n 8006634 <_printf_i+0x64> 80065ee: 2963 cmp r1, #99 ; 0x63 80065f0: d036 beq.n 8006660 <_printf_i+0x90> 80065f2: d80a bhi.n 800660a <_printf_i+0x3a> 80065f4: 2900 cmp r1, #0 80065f6: f000 80b9 beq.w 800676c <_printf_i+0x19c> 80065fa: 2958 cmp r1, #88 ; 0x58 80065fc: f000 8083 beq.w 8006706 <_printf_i+0x136> 8006600: f104 0542 add.w r5, r4, #66 ; 0x42 8006604: f884 1042 strb.w r1, [r4, #66] ; 0x42 8006608: e032 b.n 8006670 <_printf_i+0xa0> 800660a: 2964 cmp r1, #100 ; 0x64 800660c: d001 beq.n 8006612 <_printf_i+0x42> 800660e: 2969 cmp r1, #105 ; 0x69 8006610: d1f6 bne.n 8006600 <_printf_i+0x30> 8006612: 6820 ldr r0, [r4, #0] 8006614: 6813 ldr r3, [r2, #0] 8006616: 0605 lsls r5, r0, #24 8006618: f103 0104 add.w r1, r3, #4 800661c: d52a bpl.n 8006674 <_printf_i+0xa4> 800661e: 681b ldr r3, [r3, #0] 8006620: 6011 str r1, [r2, #0] 8006622: 2b00 cmp r3, #0 8006624: da03 bge.n 800662e <_printf_i+0x5e> 8006626: 222d movs r2, #45 ; 0x2d 8006628: 425b negs r3, r3 800662a: f884 2043 strb.w r2, [r4, #67] ; 0x43 800662e: 486f ldr r0, [pc, #444] ; (80067ec <_printf_i+0x21c>) 8006630: 220a movs r2, #10 8006632: e039 b.n 80066a8 <_printf_i+0xd8> 8006634: 2973 cmp r1, #115 ; 0x73 8006636: f000 809d beq.w 8006774 <_printf_i+0x1a4> 800663a: d808 bhi.n 800664e <_printf_i+0x7e> 800663c: 296f cmp r1, #111 ; 0x6f 800663e: d020 beq.n 8006682 <_printf_i+0xb2> 8006640: 2970 cmp r1, #112 ; 0x70 8006642: d1dd bne.n 8006600 <_printf_i+0x30> 8006644: 6823 ldr r3, [r4, #0] 8006646: f043 0320 orr.w r3, r3, #32 800664a: 6023 str r3, [r4, #0] 800664c: e003 b.n 8006656 <_printf_i+0x86> 800664e: 2975 cmp r1, #117 ; 0x75 8006650: d017 beq.n 8006682 <_printf_i+0xb2> 8006652: 2978 cmp r1, #120 ; 0x78 8006654: d1d4 bne.n 8006600 <_printf_i+0x30> 8006656: 2378 movs r3, #120 ; 0x78 8006658: 4865 ldr r0, [pc, #404] ; (80067f0 <_printf_i+0x220>) 800665a: f884 3045 strb.w r3, [r4, #69] ; 0x45 800665e: e055 b.n 800670c <_printf_i+0x13c> 8006660: 6813 ldr r3, [r2, #0] 8006662: f104 0542 add.w r5, r4, #66 ; 0x42 8006666: 1d19 adds r1, r3, #4 8006668: 681b ldr r3, [r3, #0] 800666a: 6011 str r1, [r2, #0] 800666c: f884 3042 strb.w r3, [r4, #66] ; 0x42 8006670: 2301 movs r3, #1 8006672: e08c b.n 800678e <_printf_i+0x1be> 8006674: 681b ldr r3, [r3, #0] 8006676: f010 0f40 tst.w r0, #64 ; 0x40 800667a: 6011 str r1, [r2, #0] 800667c: bf18 it ne 800667e: b21b sxthne r3, r3 8006680: e7cf b.n 8006622 <_printf_i+0x52> 8006682: 6813 ldr r3, [r2, #0] 8006684: 6825 ldr r5, [r4, #0] 8006686: 1d18 adds r0, r3, #4 8006688: 6010 str r0, [r2, #0] 800668a: 0628 lsls r0, r5, #24 800668c: d501 bpl.n 8006692 <_printf_i+0xc2> 800668e: 681b ldr r3, [r3, #0] 8006690: e002 b.n 8006698 <_printf_i+0xc8> 8006692: 0668 lsls r0, r5, #25 8006694: d5fb bpl.n 800668e <_printf_i+0xbe> 8006696: 881b ldrh r3, [r3, #0] 8006698: 296f cmp r1, #111 ; 0x6f 800669a: bf14 ite ne 800669c: 220a movne r2, #10 800669e: 2208 moveq r2, #8 80066a0: 4852 ldr r0, [pc, #328] ; (80067ec <_printf_i+0x21c>) 80066a2: 2100 movs r1, #0 80066a4: f884 1043 strb.w r1, [r4, #67] ; 0x43 80066a8: 6865 ldr r5, [r4, #4] 80066aa: 2d00 cmp r5, #0 80066ac: 60a5 str r5, [r4, #8] 80066ae: f2c0 8095 blt.w 80067dc <_printf_i+0x20c> 80066b2: 6821 ldr r1, [r4, #0] 80066b4: f021 0104 bic.w r1, r1, #4 80066b8: 6021 str r1, [r4, #0] 80066ba: 2b00 cmp r3, #0 80066bc: d13d bne.n 800673a <_printf_i+0x16a> 80066be: 2d00 cmp r5, #0 80066c0: f040 808e bne.w 80067e0 <_printf_i+0x210> 80066c4: 4665 mov r5, ip 80066c6: 2a08 cmp r2, #8 80066c8: d10b bne.n 80066e2 <_printf_i+0x112> 80066ca: 6823 ldr r3, [r4, #0] 80066cc: 07db lsls r3, r3, #31 80066ce: d508 bpl.n 80066e2 <_printf_i+0x112> 80066d0: 6923 ldr r3, [r4, #16] 80066d2: 6862 ldr r2, [r4, #4] 80066d4: 429a cmp r2, r3 80066d6: bfde ittt le 80066d8: 2330 movle r3, #48 ; 0x30 80066da: f805 3c01 strble.w r3, [r5, #-1] 80066de: f105 35ff addle.w r5, r5, #4294967295 80066e2: ebac 0305 sub.w r3, ip, r5 80066e6: 6123 str r3, [r4, #16] 80066e8: f8cd 8000 str.w r8, [sp] 80066ec: 463b mov r3, r7 80066ee: aa03 add r2, sp, #12 80066f0: 4621 mov r1, r4 80066f2: 4630 mov r0, r6 80066f4: f7ff fef6 bl 80064e4 <_printf_common> 80066f8: 3001 adds r0, #1 80066fa: d14d bne.n 8006798 <_printf_i+0x1c8> 80066fc: f04f 30ff mov.w r0, #4294967295 8006700: b005 add sp, #20 8006702: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} 8006706: 4839 ldr r0, [pc, #228] ; (80067ec <_printf_i+0x21c>) 8006708: f884 1045 strb.w r1, [r4, #69] ; 0x45 800670c: 6813 ldr r3, [r2, #0] 800670e: 6821 ldr r1, [r4, #0] 8006710: 1d1d adds r5, r3, #4 8006712: 681b ldr r3, [r3, #0] 8006714: 6015 str r5, [r2, #0] 8006716: 060a lsls r2, r1, #24 8006718: d50b bpl.n 8006732 <_printf_i+0x162> 800671a: 07ca lsls r2, r1, #31 800671c: bf44 itt mi 800671e: f041 0120 orrmi.w r1, r1, #32 8006722: 6021 strmi r1, [r4, #0] 8006724: b91b cbnz r3, 800672e <_printf_i+0x15e> 8006726: 6822 ldr r2, [r4, #0] 8006728: f022 0220 bic.w r2, r2, #32 800672c: 6022 str r2, [r4, #0] 800672e: 2210 movs r2, #16 8006730: e7b7 b.n 80066a2 <_printf_i+0xd2> 8006732: 064d lsls r5, r1, #25 8006734: bf48 it mi 8006736: b29b uxthmi r3, r3 8006738: e7ef b.n 800671a <_printf_i+0x14a> 800673a: 4665 mov r5, ip 800673c: fbb3 f1f2 udiv r1, r3, r2 8006740: fb02 3311 mls r3, r2, r1, r3 8006744: 5cc3 ldrb r3, [r0, r3] 8006746: f805 3d01 strb.w r3, [r5, #-1]! 800674a: 460b mov r3, r1 800674c: 2900 cmp r1, #0 800674e: d1f5 bne.n 800673c <_printf_i+0x16c> 8006750: e7b9 b.n 80066c6 <_printf_i+0xf6> 8006752: 6813 ldr r3, [r2, #0] 8006754: 6825 ldr r5, [r4, #0] 8006756: 1d18 adds r0, r3, #4 8006758: 6961 ldr r1, [r4, #20] 800675a: 6010 str r0, [r2, #0] 800675c: 0628 lsls r0, r5, #24 800675e: 681b ldr r3, [r3, #0] 8006760: d501 bpl.n 8006766 <_printf_i+0x196> 8006762: 6019 str r1, [r3, #0] 8006764: e002 b.n 800676c <_printf_i+0x19c> 8006766: 066a lsls r2, r5, #25 8006768: d5fb bpl.n 8006762 <_printf_i+0x192> 800676a: 8019 strh r1, [r3, #0] 800676c: 2300 movs r3, #0 800676e: 4665 mov r5, ip 8006770: 6123 str r3, [r4, #16] 8006772: e7b9 b.n 80066e8 <_printf_i+0x118> 8006774: 6813 ldr r3, [r2, #0] 8006776: 1d19 adds r1, r3, #4 8006778: 6011 str r1, [r2, #0] 800677a: 681d ldr r5, [r3, #0] 800677c: 6862 ldr r2, [r4, #4] 800677e: 2100 movs r1, #0 8006780: 4628 mov r0, r5 8006782: f001 fa61 bl 8007c48 8006786: b108 cbz r0, 800678c <_printf_i+0x1bc> 8006788: 1b40 subs r0, r0, r5 800678a: 6060 str r0, [r4, #4] 800678c: 6863 ldr r3, [r4, #4] 800678e: 6123 str r3, [r4, #16] 8006790: 2300 movs r3, #0 8006792: f884 3043 strb.w r3, [r4, #67] ; 0x43 8006796: e7a7 b.n 80066e8 <_printf_i+0x118> 8006798: 6923 ldr r3, [r4, #16] 800679a: 462a mov r2, r5 800679c: 4639 mov r1, r7 800679e: 4630 mov r0, r6 80067a0: 47c0 blx r8 80067a2: 3001 adds r0, #1 80067a4: d0aa beq.n 80066fc <_printf_i+0x12c> 80067a6: 6823 ldr r3, [r4, #0] 80067a8: 079b lsls r3, r3, #30 80067aa: d413 bmi.n 80067d4 <_printf_i+0x204> 80067ac: 68e0 ldr r0, [r4, #12] 80067ae: 9b03 ldr r3, [sp, #12] 80067b0: 4298 cmp r0, r3 80067b2: bfb8 it lt 80067b4: 4618 movlt r0, r3 80067b6: e7a3 b.n 8006700 <_printf_i+0x130> 80067b8: 2301 movs r3, #1 80067ba: 464a mov r2, r9 80067bc: 4639 mov r1, r7 80067be: 4630 mov r0, r6 80067c0: 47c0 blx r8 80067c2: 3001 adds r0, #1 80067c4: d09a beq.n 80066fc <_printf_i+0x12c> 80067c6: 3501 adds r5, #1 80067c8: 68e3 ldr r3, [r4, #12] 80067ca: 9a03 ldr r2, [sp, #12] 80067cc: 1a9b subs r3, r3, r2 80067ce: 42ab cmp r3, r5 80067d0: dcf2 bgt.n 80067b8 <_printf_i+0x1e8> 80067d2: e7eb b.n 80067ac <_printf_i+0x1dc> 80067d4: 2500 movs r5, #0 80067d6: f104 0919 add.w r9, r4, #25 80067da: e7f5 b.n 80067c8 <_printf_i+0x1f8> 80067dc: 2b00 cmp r3, #0 80067de: d1ac bne.n 800673a <_printf_i+0x16a> 80067e0: 7803 ldrb r3, [r0, #0] 80067e2: f104 0542 add.w r5, r4, #66 ; 0x42 80067e6: f884 3042 strb.w r3, [r4, #66] ; 0x42 80067ea: e76c b.n 80066c6 <_printf_i+0xf6> 80067ec: 08008bc6 .word 0x08008bc6 80067f0: 08008bd7 .word 0x08008bd7 080067f4 : 80067f4: b40f push {r0, r1, r2, r3} 80067f6: 4b0a ldr r3, [pc, #40] ; (8006820 ) 80067f8: b513 push {r0, r1, r4, lr} 80067fa: 681c ldr r4, [r3, #0] 80067fc: b124 cbz r4, 8006808 80067fe: 69a3 ldr r3, [r4, #24] 8006800: b913 cbnz r3, 8006808 8006802: 4620 mov r0, r4 8006804: f001 f91c bl 8007a40 <__sinit> 8006808: ab05 add r3, sp, #20 800680a: 9a04 ldr r2, [sp, #16] 800680c: 68a1 ldr r1, [r4, #8] 800680e: 4620 mov r0, r4 8006810: 9301 str r3, [sp, #4] 8006812: f001 fdeb bl 80083ec <_vfiprintf_r> 8006816: b002 add sp, #8 8006818: e8bd 4010 ldmia.w sp!, {r4, lr} 800681c: b004 add sp, #16 800681e: 4770 bx lr 8006820: 2000000c .word 0x2000000c 08006824 <_puts_r>: 8006824: b570 push {r4, r5, r6, lr} 8006826: 460e mov r6, r1 8006828: 4605 mov r5, r0 800682a: b118 cbz r0, 8006834 <_puts_r+0x10> 800682c: 6983 ldr r3, [r0, #24] 800682e: b90b cbnz r3, 8006834 <_puts_r+0x10> 8006830: f001 f906 bl 8007a40 <__sinit> 8006834: 69ab ldr r3, [r5, #24] 8006836: 68ac ldr r4, [r5, #8] 8006838: b913 cbnz r3, 8006840 <_puts_r+0x1c> 800683a: 4628 mov r0, r5 800683c: f001 f900 bl 8007a40 <__sinit> 8006840: 4b23 ldr r3, [pc, #140] ; (80068d0 <_puts_r+0xac>) 8006842: 429c cmp r4, r3 8006844: d117 bne.n 8006876 <_puts_r+0x52> 8006846: 686c ldr r4, [r5, #4] 8006848: 89a3 ldrh r3, [r4, #12] 800684a: 071b lsls r3, r3, #28 800684c: d51d bpl.n 800688a <_puts_r+0x66> 800684e: 6923 ldr r3, [r4, #16] 8006850: b1db cbz r3, 800688a <_puts_r+0x66> 8006852: 3e01 subs r6, #1 8006854: 68a3 ldr r3, [r4, #8] 8006856: f816 1f01 ldrb.w r1, [r6, #1]! 800685a: 3b01 subs r3, #1 800685c: 60a3 str r3, [r4, #8] 800685e: b9e9 cbnz r1, 800689c <_puts_r+0x78> 8006860: 2b00 cmp r3, #0 8006862: da2e bge.n 80068c2 <_puts_r+0x9e> 8006864: 4622 mov r2, r4 8006866: 210a movs r1, #10 8006868: 4628 mov r0, r5 800686a: f000 f8f5 bl 8006a58 <__swbuf_r> 800686e: 3001 adds r0, #1 8006870: d011 beq.n 8006896 <_puts_r+0x72> 8006872: 200a movs r0, #10 8006874: e011 b.n 800689a <_puts_r+0x76> 8006876: 4b17 ldr r3, [pc, #92] ; (80068d4 <_puts_r+0xb0>) 8006878: 429c cmp r4, r3 800687a: d101 bne.n 8006880 <_puts_r+0x5c> 800687c: 68ac ldr r4, [r5, #8] 800687e: e7e3 b.n 8006848 <_puts_r+0x24> 8006880: 4b15 ldr r3, [pc, #84] ; (80068d8 <_puts_r+0xb4>) 8006882: 429c cmp r4, r3 8006884: bf08 it eq 8006886: 68ec ldreq r4, [r5, #12] 8006888: e7de b.n 8006848 <_puts_r+0x24> 800688a: 4621 mov r1, r4 800688c: 4628 mov r0, r5 800688e: f000 f935 bl 8006afc <__swsetup_r> 8006892: 2800 cmp r0, #0 8006894: d0dd beq.n 8006852 <_puts_r+0x2e> 8006896: f04f 30ff mov.w r0, #4294967295 800689a: bd70 pop {r4, r5, r6, pc} 800689c: 2b00 cmp r3, #0 800689e: da04 bge.n 80068aa <_puts_r+0x86> 80068a0: 69a2 ldr r2, [r4, #24] 80068a2: 429a cmp r2, r3 80068a4: dc06 bgt.n 80068b4 <_puts_r+0x90> 80068a6: 290a cmp r1, #10 80068a8: d004 beq.n 80068b4 <_puts_r+0x90> 80068aa: 6823 ldr r3, [r4, #0] 80068ac: 1c5a adds r2, r3, #1 80068ae: 6022 str r2, [r4, #0] 80068b0: 7019 strb r1, [r3, #0] 80068b2: e7cf b.n 8006854 <_puts_r+0x30> 80068b4: 4622 mov r2, r4 80068b6: 4628 mov r0, r5 80068b8: f000 f8ce bl 8006a58 <__swbuf_r> 80068bc: 3001 adds r0, #1 80068be: d1c9 bne.n 8006854 <_puts_r+0x30> 80068c0: e7e9 b.n 8006896 <_puts_r+0x72> 80068c2: 200a movs r0, #10 80068c4: 6823 ldr r3, [r4, #0] 80068c6: 1c5a adds r2, r3, #1 80068c8: 6022 str r2, [r4, #0] 80068ca: 7018 strb r0, [r3, #0] 80068cc: e7e5 b.n 800689a <_puts_r+0x76> 80068ce: bf00 nop 80068d0: 08008c18 .word 0x08008c18 80068d4: 08008c38 .word 0x08008c38 80068d8: 08008bf8 .word 0x08008bf8 080068dc : 80068dc: 4b02 ldr r3, [pc, #8] ; (80068e8 ) 80068de: 4601 mov r1, r0 80068e0: 6818 ldr r0, [r3, #0] 80068e2: f7ff bf9f b.w 8006824 <_puts_r> 80068e6: bf00 nop 80068e8: 2000000c .word 0x2000000c 080068ec : 80068ec: 2900 cmp r1, #0 80068ee: f44f 6380 mov.w r3, #1024 ; 0x400 80068f2: bf0c ite eq 80068f4: 2202 moveq r2, #2 80068f6: 2200 movne r2, #0 80068f8: f000 b800 b.w 80068fc 080068fc : 80068fc: e92d 43f7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr} 8006900: 461d mov r5, r3 8006902: 4b51 ldr r3, [pc, #324] ; (8006a48 ) 8006904: 4604 mov r4, r0 8006906: 681e ldr r6, [r3, #0] 8006908: 460f mov r7, r1 800690a: 4690 mov r8, r2 800690c: b126 cbz r6, 8006918 800690e: 69b3 ldr r3, [r6, #24] 8006910: b913 cbnz r3, 8006918 8006912: 4630 mov r0, r6 8006914: f001 f894 bl 8007a40 <__sinit> 8006918: 4b4c ldr r3, [pc, #304] ; (8006a4c ) 800691a: 429c cmp r4, r3 800691c: d152 bne.n 80069c4 800691e: 6874 ldr r4, [r6, #4] 8006920: f1b8 0f02 cmp.w r8, #2 8006924: d006 beq.n 8006934 8006926: f1b8 0f01 cmp.w r8, #1 800692a: f200 8089 bhi.w 8006a40 800692e: 2d00 cmp r5, #0 8006930: f2c0 8086 blt.w 8006a40 8006934: 4621 mov r1, r4 8006936: 4630 mov r0, r6 8006938: f001 f818 bl 800796c <_fflush_r> 800693c: 6b61 ldr r1, [r4, #52] ; 0x34 800693e: b141 cbz r1, 8006952 8006940: f104 0344 add.w r3, r4, #68 ; 0x44 8006944: 4299 cmp r1, r3 8006946: d002 beq.n 800694e 8006948: 4630 mov r0, r6 800694a: f001 fc81 bl 8008250 <_free_r> 800694e: 2300 movs r3, #0 8006950: 6363 str r3, [r4, #52] ; 0x34 8006952: 2300 movs r3, #0 8006954: 61a3 str r3, [r4, #24] 8006956: 6063 str r3, [r4, #4] 8006958: 89a3 ldrh r3, [r4, #12] 800695a: 061b lsls r3, r3, #24 800695c: d503 bpl.n 8006966 800695e: 6921 ldr r1, [r4, #16] 8006960: 4630 mov r0, r6 8006962: f001 fc75 bl 8008250 <_free_r> 8006966: 89a3 ldrh r3, [r4, #12] 8006968: f1b8 0f02 cmp.w r8, #2 800696c: f423 634a bic.w r3, r3, #3232 ; 0xca0 8006970: f023 0303 bic.w r3, r3, #3 8006974: 81a3 strh r3, [r4, #12] 8006976: d05d beq.n 8006a34 8006978: ab01 add r3, sp, #4 800697a: 466a mov r2, sp 800697c: 4621 mov r1, r4 800697e: 4630 mov r0, r6 8006980: f001 f8f6 bl 8007b70 <__swhatbuf_r> 8006984: 89a3 ldrh r3, [r4, #12] 8006986: 4318 orrs r0, r3 8006988: 81a0 strh r0, [r4, #12] 800698a: bb2d cbnz r5, 80069d8 800698c: 9d00 ldr r5, [sp, #0] 800698e: 4628 mov r0, r5 8006990: f001 f952 bl 8007c38 8006994: 4607 mov r7, r0 8006996: 2800 cmp r0, #0 8006998: d14e bne.n 8006a38 800699a: f8dd 9000 ldr.w r9, [sp] 800699e: 45a9 cmp r9, r5 80069a0: d13c bne.n 8006a1c 80069a2: f04f 30ff mov.w r0, #4294967295 80069a6: 89a3 ldrh r3, [r4, #12] 80069a8: f043 0302 orr.w r3, r3, #2 80069ac: 81a3 strh r3, [r4, #12] 80069ae: 2300 movs r3, #0 80069b0: 60a3 str r3, [r4, #8] 80069b2: f104 0347 add.w r3, r4, #71 ; 0x47 80069b6: 6023 str r3, [r4, #0] 80069b8: 6123 str r3, [r4, #16] 80069ba: 2301 movs r3, #1 80069bc: 6163 str r3, [r4, #20] 80069be: b003 add sp, #12 80069c0: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} 80069c4: 4b22 ldr r3, [pc, #136] ; (8006a50 ) 80069c6: 429c cmp r4, r3 80069c8: d101 bne.n 80069ce 80069ca: 68b4 ldr r4, [r6, #8] 80069cc: e7a8 b.n 8006920 80069ce: 4b21 ldr r3, [pc, #132] ; (8006a54 ) 80069d0: 429c cmp r4, r3 80069d2: bf08 it eq 80069d4: 68f4 ldreq r4, [r6, #12] 80069d6: e7a3 b.n 8006920 80069d8: 2f00 cmp r7, #0 80069da: d0d8 beq.n 800698e 80069dc: 69b3 ldr r3, [r6, #24] 80069de: b913 cbnz r3, 80069e6 80069e0: 4630 mov r0, r6 80069e2: f001 f82d bl 8007a40 <__sinit> 80069e6: f1b8 0f01 cmp.w r8, #1 80069ea: bf08 it eq 80069ec: 89a3 ldrheq r3, [r4, #12] 80069ee: 6027 str r7, [r4, #0] 80069f0: bf04 itt eq 80069f2: f043 0301 orreq.w r3, r3, #1 80069f6: 81a3 strheq r3, [r4, #12] 80069f8: 89a3 ldrh r3, [r4, #12] 80069fa: e9c4 7504 strd r7, r5, [r4, #16] 80069fe: f013 0008 ands.w r0, r3, #8 8006a02: d01b beq.n 8006a3c 8006a04: f013 0001 ands.w r0, r3, #1 8006a08: f04f 0300 mov.w r3, #0 8006a0c: bf1f itttt ne 8006a0e: 426d negne r5, r5 8006a10: 60a3 strne r3, [r4, #8] 8006a12: 61a5 strne r5, [r4, #24] 8006a14: 4618 movne r0, r3 8006a16: bf08 it eq 8006a18: 60a5 streq r5, [r4, #8] 8006a1a: e7d0 b.n 80069be 8006a1c: 4648 mov r0, r9 8006a1e: f001 f90b bl 8007c38 8006a22: 4607 mov r7, r0 8006a24: 2800 cmp r0, #0 8006a26: d0bc beq.n 80069a2 8006a28: 89a3 ldrh r3, [r4, #12] 8006a2a: 464d mov r5, r9 8006a2c: f043 0380 orr.w r3, r3, #128 ; 0x80 8006a30: 81a3 strh r3, [r4, #12] 8006a32: e7d3 b.n 80069dc 8006a34: 2000 movs r0, #0 8006a36: e7b6 b.n 80069a6 8006a38: 46a9 mov r9, r5 8006a3a: e7f5 b.n 8006a28 8006a3c: 60a0 str r0, [r4, #8] 8006a3e: e7be b.n 80069be 8006a40: f04f 30ff mov.w r0, #4294967295 8006a44: e7bb b.n 80069be 8006a46: bf00 nop 8006a48: 2000000c .word 0x2000000c 8006a4c: 08008c18 .word 0x08008c18 8006a50: 08008c38 .word 0x08008c38 8006a54: 08008bf8 .word 0x08008bf8 08006a58 <__swbuf_r>: 8006a58: b5f8 push {r3, r4, r5, r6, r7, lr} 8006a5a: 460e mov r6, r1 8006a5c: 4614 mov r4, r2 8006a5e: 4605 mov r5, r0 8006a60: b118 cbz r0, 8006a6a <__swbuf_r+0x12> 8006a62: 6983 ldr r3, [r0, #24] 8006a64: b90b cbnz r3, 8006a6a <__swbuf_r+0x12> 8006a66: f000 ffeb bl 8007a40 <__sinit> 8006a6a: 4b21 ldr r3, [pc, #132] ; (8006af0 <__swbuf_r+0x98>) 8006a6c: 429c cmp r4, r3 8006a6e: d12a bne.n 8006ac6 <__swbuf_r+0x6e> 8006a70: 686c ldr r4, [r5, #4] 8006a72: 69a3 ldr r3, [r4, #24] 8006a74: 60a3 str r3, [r4, #8] 8006a76: 89a3 ldrh r3, [r4, #12] 8006a78: 071a lsls r2, r3, #28 8006a7a: d52e bpl.n 8006ada <__swbuf_r+0x82> 8006a7c: 6923 ldr r3, [r4, #16] 8006a7e: b363 cbz r3, 8006ada <__swbuf_r+0x82> 8006a80: 6923 ldr r3, [r4, #16] 8006a82: 6820 ldr r0, [r4, #0] 8006a84: b2f6 uxtb r6, r6 8006a86: 1ac0 subs r0, r0, r3 8006a88: 6963 ldr r3, [r4, #20] 8006a8a: 4637 mov r7, r6 8006a8c: 4283 cmp r3, r0 8006a8e: dc04 bgt.n 8006a9a <__swbuf_r+0x42> 8006a90: 4621 mov r1, r4 8006a92: 4628 mov r0, r5 8006a94: f000 ff6a bl 800796c <_fflush_r> 8006a98: bb28 cbnz r0, 8006ae6 <__swbuf_r+0x8e> 8006a9a: 68a3 ldr r3, [r4, #8] 8006a9c: 3001 adds r0, #1 8006a9e: 3b01 subs r3, #1 8006aa0: 60a3 str r3, [r4, #8] 8006aa2: 6823 ldr r3, [r4, #0] 8006aa4: 1c5a adds r2, r3, #1 8006aa6: 6022 str r2, [r4, #0] 8006aa8: 701e strb r6, [r3, #0] 8006aaa: 6963 ldr r3, [r4, #20] 8006aac: 4283 cmp r3, r0 8006aae: d004 beq.n 8006aba <__swbuf_r+0x62> 8006ab0: 89a3 ldrh r3, [r4, #12] 8006ab2: 07db lsls r3, r3, #31 8006ab4: d519 bpl.n 8006aea <__swbuf_r+0x92> 8006ab6: 2e0a cmp r6, #10 8006ab8: d117 bne.n 8006aea <__swbuf_r+0x92> 8006aba: 4621 mov r1, r4 8006abc: 4628 mov r0, r5 8006abe: f000 ff55 bl 800796c <_fflush_r> 8006ac2: b190 cbz r0, 8006aea <__swbuf_r+0x92> 8006ac4: e00f b.n 8006ae6 <__swbuf_r+0x8e> 8006ac6: 4b0b ldr r3, [pc, #44] ; (8006af4 <__swbuf_r+0x9c>) 8006ac8: 429c cmp r4, r3 8006aca: d101 bne.n 8006ad0 <__swbuf_r+0x78> 8006acc: 68ac ldr r4, [r5, #8] 8006ace: e7d0 b.n 8006a72 <__swbuf_r+0x1a> 8006ad0: 4b09 ldr r3, [pc, #36] ; (8006af8 <__swbuf_r+0xa0>) 8006ad2: 429c cmp r4, r3 8006ad4: bf08 it eq 8006ad6: 68ec ldreq r4, [r5, #12] 8006ad8: e7cb b.n 8006a72 <__swbuf_r+0x1a> 8006ada: 4621 mov r1, r4 8006adc: 4628 mov r0, r5 8006ade: f000 f80d bl 8006afc <__swsetup_r> 8006ae2: 2800 cmp r0, #0 8006ae4: d0cc beq.n 8006a80 <__swbuf_r+0x28> 8006ae6: f04f 37ff mov.w r7, #4294967295 8006aea: 4638 mov r0, r7 8006aec: bdf8 pop {r3, r4, r5, r6, r7, pc} 8006aee: bf00 nop 8006af0: 08008c18 .word 0x08008c18 8006af4: 08008c38 .word 0x08008c38 8006af8: 08008bf8 .word 0x08008bf8 08006afc <__swsetup_r>: 8006afc: 4b32 ldr r3, [pc, #200] ; (8006bc8 <__swsetup_r+0xcc>) 8006afe: b570 push {r4, r5, r6, lr} 8006b00: 681d ldr r5, [r3, #0] 8006b02: 4606 mov r6, r0 8006b04: 460c mov r4, r1 8006b06: b125 cbz r5, 8006b12 <__swsetup_r+0x16> 8006b08: 69ab ldr r3, [r5, #24] 8006b0a: b913 cbnz r3, 8006b12 <__swsetup_r+0x16> 8006b0c: 4628 mov r0, r5 8006b0e: f000 ff97 bl 8007a40 <__sinit> 8006b12: 4b2e ldr r3, [pc, #184] ; (8006bcc <__swsetup_r+0xd0>) 8006b14: 429c cmp r4, r3 8006b16: d10f bne.n 8006b38 <__swsetup_r+0x3c> 8006b18: 686c ldr r4, [r5, #4] 8006b1a: f9b4 300c ldrsh.w r3, [r4, #12] 8006b1e: b29a uxth r2, r3 8006b20: 0715 lsls r5, r2, #28 8006b22: d42c bmi.n 8006b7e <__swsetup_r+0x82> 8006b24: 06d0 lsls r0, r2, #27 8006b26: d411 bmi.n 8006b4c <__swsetup_r+0x50> 8006b28: 2209 movs r2, #9 8006b2a: 6032 str r2, [r6, #0] 8006b2c: f043 0340 orr.w r3, r3, #64 ; 0x40 8006b30: 81a3 strh r3, [r4, #12] 8006b32: f04f 30ff mov.w r0, #4294967295 8006b36: e03e b.n 8006bb6 <__swsetup_r+0xba> 8006b38: 4b25 ldr r3, [pc, #148] ; (8006bd0 <__swsetup_r+0xd4>) 8006b3a: 429c cmp r4, r3 8006b3c: d101 bne.n 8006b42 <__swsetup_r+0x46> 8006b3e: 68ac ldr r4, [r5, #8] 8006b40: e7eb b.n 8006b1a <__swsetup_r+0x1e> 8006b42: 4b24 ldr r3, [pc, #144] ; (8006bd4 <__swsetup_r+0xd8>) 8006b44: 429c cmp r4, r3 8006b46: bf08 it eq 8006b48: 68ec ldreq r4, [r5, #12] 8006b4a: e7e6 b.n 8006b1a <__swsetup_r+0x1e> 8006b4c: 0751 lsls r1, r2, #29 8006b4e: d512 bpl.n 8006b76 <__swsetup_r+0x7a> 8006b50: 6b61 ldr r1, [r4, #52] ; 0x34 8006b52: b141 cbz r1, 8006b66 <__swsetup_r+0x6a> 8006b54: f104 0344 add.w r3, r4, #68 ; 0x44 8006b58: 4299 cmp r1, r3 8006b5a: d002 beq.n 8006b62 <__swsetup_r+0x66> 8006b5c: 4630 mov r0, r6 8006b5e: f001 fb77 bl 8008250 <_free_r> 8006b62: 2300 movs r3, #0 8006b64: 6363 str r3, [r4, #52] ; 0x34 8006b66: 89a3 ldrh r3, [r4, #12] 8006b68: f023 0324 bic.w r3, r3, #36 ; 0x24 8006b6c: 81a3 strh r3, [r4, #12] 8006b6e: 2300 movs r3, #0 8006b70: 6063 str r3, [r4, #4] 8006b72: 6923 ldr r3, [r4, #16] 8006b74: 6023 str r3, [r4, #0] 8006b76: 89a3 ldrh r3, [r4, #12] 8006b78: f043 0308 orr.w r3, r3, #8 8006b7c: 81a3 strh r3, [r4, #12] 8006b7e: 6923 ldr r3, [r4, #16] 8006b80: b94b cbnz r3, 8006b96 <__swsetup_r+0x9a> 8006b82: 89a3 ldrh r3, [r4, #12] 8006b84: f403 7320 and.w r3, r3, #640 ; 0x280 8006b88: f5b3 7f00 cmp.w r3, #512 ; 0x200 8006b8c: d003 beq.n 8006b96 <__swsetup_r+0x9a> 8006b8e: 4621 mov r1, r4 8006b90: 4630 mov r0, r6 8006b92: f001 f811 bl 8007bb8 <__smakebuf_r> 8006b96: 89a2 ldrh r2, [r4, #12] 8006b98: f012 0301 ands.w r3, r2, #1 8006b9c: d00c beq.n 8006bb8 <__swsetup_r+0xbc> 8006b9e: 2300 movs r3, #0 8006ba0: 60a3 str r3, [r4, #8] 8006ba2: 6963 ldr r3, [r4, #20] 8006ba4: 425b negs r3, r3 8006ba6: 61a3 str r3, [r4, #24] 8006ba8: 6923 ldr r3, [r4, #16] 8006baa: b953 cbnz r3, 8006bc2 <__swsetup_r+0xc6> 8006bac: f9b4 300c ldrsh.w r3, [r4, #12] 8006bb0: f013 0080 ands.w r0, r3, #128 ; 0x80 8006bb4: d1ba bne.n 8006b2c <__swsetup_r+0x30> 8006bb6: bd70 pop {r4, r5, r6, pc} 8006bb8: 0792 lsls r2, r2, #30 8006bba: bf58 it pl 8006bbc: 6963 ldrpl r3, [r4, #20] 8006bbe: 60a3 str r3, [r4, #8] 8006bc0: e7f2 b.n 8006ba8 <__swsetup_r+0xac> 8006bc2: 2000 movs r0, #0 8006bc4: e7f7 b.n 8006bb6 <__swsetup_r+0xba> 8006bc6: bf00 nop 8006bc8: 2000000c .word 0x2000000c 8006bcc: 08008c18 .word 0x08008c18 8006bd0: 08008c38 .word 0x08008c38 8006bd4: 08008bf8 .word 0x08008bf8 08006bd8 : 8006bd8: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} 8006bdc: 6903 ldr r3, [r0, #16] 8006bde: 690c ldr r4, [r1, #16] 8006be0: 4680 mov r8, r0 8006be2: 42a3 cmp r3, r4 8006be4: f2c0 8084 blt.w 8006cf0 8006be8: 3c01 subs r4, #1 8006bea: f101 0714 add.w r7, r1, #20 8006bee: f100 0614 add.w r6, r0, #20 8006bf2: f857 5024 ldr.w r5, [r7, r4, lsl #2] 8006bf6: f856 0024 ldr.w r0, [r6, r4, lsl #2] 8006bfa: 3501 adds r5, #1 8006bfc: fbb0 f5f5 udiv r5, r0, r5 8006c00: ea4f 0c84 mov.w ip, r4, lsl #2 8006c04: eb06 030c add.w r3, r6, ip 8006c08: eb07 090c add.w r9, r7, ip 8006c0c: 9301 str r3, [sp, #4] 8006c0e: b39d cbz r5, 8006c78 8006c10: f04f 0a00 mov.w sl, #0 8006c14: 4638 mov r0, r7 8006c16: 46b6 mov lr, r6 8006c18: 46d3 mov fp, sl 8006c1a: f850 2b04 ldr.w r2, [r0], #4 8006c1e: b293 uxth r3, r2 8006c20: fb05 a303 mla r3, r5, r3, sl 8006c24: 0c12 lsrs r2, r2, #16 8006c26: ea4f 4a13 mov.w sl, r3, lsr #16 8006c2a: fb05 a202 mla r2, r5, r2, sl 8006c2e: b29b uxth r3, r3 8006c30: ebab 0303 sub.w r3, fp, r3 8006c34: f8de b000 ldr.w fp, [lr] 8006c38: ea4f 4a12 mov.w sl, r2, lsr #16 8006c3c: fa1f fb8b uxth.w fp, fp 8006c40: 445b add r3, fp 8006c42: fa1f fb82 uxth.w fp, r2 8006c46: f8de 2000 ldr.w r2, [lr] 8006c4a: 4581 cmp r9, r0 8006c4c: ebcb 4212 rsb r2, fp, r2, lsr #16 8006c50: eb02 4223 add.w r2, r2, r3, asr #16 8006c54: b29b uxth r3, r3 8006c56: ea43 4302 orr.w r3, r3, r2, lsl #16 8006c5a: ea4f 4b22 mov.w fp, r2, asr #16 8006c5e: f84e 3b04 str.w r3, [lr], #4 8006c62: d2da bcs.n 8006c1a 8006c64: f856 300c ldr.w r3, [r6, ip] 8006c68: b933 cbnz r3, 8006c78 8006c6a: 9b01 ldr r3, [sp, #4] 8006c6c: 3b04 subs r3, #4 8006c6e: 429e cmp r6, r3 8006c70: 461a mov r2, r3 8006c72: d331 bcc.n 8006cd8 8006c74: f8c8 4010 str.w r4, [r8, #16] 8006c78: 4640 mov r0, r8 8006c7a: f001 fa13 bl 80080a4 <__mcmp> 8006c7e: 2800 cmp r0, #0 8006c80: db26 blt.n 8006cd0 8006c82: 4630 mov r0, r6 8006c84: f04f 0c00 mov.w ip, #0 8006c88: 3501 adds r5, #1 8006c8a: f857 1b04 ldr.w r1, [r7], #4 8006c8e: f8d0 e000 ldr.w lr, [r0] 8006c92: b28b uxth r3, r1 8006c94: ebac 0303 sub.w r3, ip, r3 8006c98: fa1f f28e uxth.w r2, lr 8006c9c: 4413 add r3, r2 8006c9e: 0c0a lsrs r2, r1, #16 8006ca0: ebc2 421e rsb r2, r2, lr, lsr #16 8006ca4: eb02 4223 add.w r2, r2, r3, asr #16 8006ca8: b29b uxth r3, r3 8006caa: ea43 4302 orr.w r3, r3, r2, lsl #16 8006cae: 45b9 cmp r9, r7 8006cb0: ea4f 4c22 mov.w ip, r2, asr #16 8006cb4: f840 3b04 str.w r3, [r0], #4 8006cb8: d2e7 bcs.n 8006c8a 8006cba: f856 2024 ldr.w r2, [r6, r4, lsl #2] 8006cbe: eb06 0384 add.w r3, r6, r4, lsl #2 8006cc2: b92a cbnz r2, 8006cd0 8006cc4: 3b04 subs r3, #4 8006cc6: 429e cmp r6, r3 8006cc8: 461a mov r2, r3 8006cca: d30b bcc.n 8006ce4 8006ccc: f8c8 4010 str.w r4, [r8, #16] 8006cd0: 4628 mov r0, r5 8006cd2: b003 add sp, #12 8006cd4: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8006cd8: 6812 ldr r2, [r2, #0] 8006cda: 3b04 subs r3, #4 8006cdc: 2a00 cmp r2, #0 8006cde: d1c9 bne.n 8006c74 8006ce0: 3c01 subs r4, #1 8006ce2: e7c4 b.n 8006c6e 8006ce4: 6812 ldr r2, [r2, #0] 8006ce6: 3b04 subs r3, #4 8006ce8: 2a00 cmp r2, #0 8006cea: d1ef bne.n 8006ccc 8006cec: 3c01 subs r4, #1 8006cee: e7ea b.n 8006cc6 8006cf0: 2000 movs r0, #0 8006cf2: e7ee b.n 8006cd2 8006cf4: 0000 movs r0, r0 ... 08006cf8 <_dtoa_r>: 8006cf8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8006cfc: 4616 mov r6, r2 8006cfe: 461f mov r7, r3 8006d00: 6a45 ldr r5, [r0, #36] ; 0x24 8006d02: b095 sub sp, #84 ; 0x54 8006d04: 4604 mov r4, r0 8006d06: f8dd 8084 ldr.w r8, [sp, #132] ; 0x84 8006d0a: e9cd 6702 strd r6, r7, [sp, #8] 8006d0e: b93d cbnz r5, 8006d20 <_dtoa_r+0x28> 8006d10: 2010 movs r0, #16 8006d12: f000 ff91 bl 8007c38 8006d16: 6260 str r0, [r4, #36] ; 0x24 8006d18: e9c0 5501 strd r5, r5, [r0, #4] 8006d1c: 6005 str r5, [r0, #0] 8006d1e: 60c5 str r5, [r0, #12] 8006d20: 6a63 ldr r3, [r4, #36] ; 0x24 8006d22: 6819 ldr r1, [r3, #0] 8006d24: b151 cbz r1, 8006d3c <_dtoa_r+0x44> 8006d26: 685a ldr r2, [r3, #4] 8006d28: 2301 movs r3, #1 8006d2a: 4093 lsls r3, r2 8006d2c: 604a str r2, [r1, #4] 8006d2e: 608b str r3, [r1, #8] 8006d30: 4620 mov r0, r4 8006d32: f000 ffd6 bl 8007ce2 <_Bfree> 8006d36: 2200 movs r2, #0 8006d38: 6a63 ldr r3, [r4, #36] ; 0x24 8006d3a: 601a str r2, [r3, #0] 8006d3c: 1e3b subs r3, r7, #0 8006d3e: bfaf iteee ge 8006d40: 2300 movge r3, #0 8006d42: 2201 movlt r2, #1 8006d44: f023 4300 biclt.w r3, r3, #2147483648 ; 0x80000000 8006d48: 9303 strlt r3, [sp, #12] 8006d4a: bfac ite ge 8006d4c: f8c8 3000 strge.w r3, [r8] 8006d50: f8c8 2000 strlt.w r2, [r8] 8006d54: 4bae ldr r3, [pc, #696] ; (8007010 <_dtoa_r+0x318>) 8006d56: f8dd 800c ldr.w r8, [sp, #12] 8006d5a: ea33 0308 bics.w r3, r3, r8 8006d5e: d11b bne.n 8006d98 <_dtoa_r+0xa0> 8006d60: f242 730f movw r3, #9999 ; 0x270f 8006d64: 9a20 ldr r2, [sp, #128] ; 0x80 8006d66: 6013 str r3, [r2, #0] 8006d68: 9b02 ldr r3, [sp, #8] 8006d6a: b923 cbnz r3, 8006d76 <_dtoa_r+0x7e> 8006d6c: f3c8 0013 ubfx r0, r8, #0, #20 8006d70: 2800 cmp r0, #0 8006d72: f000 8545 beq.w 8007800 <_dtoa_r+0xb08> 8006d76: 9b22 ldr r3, [sp, #136] ; 0x88 8006d78: b953 cbnz r3, 8006d90 <_dtoa_r+0x98> 8006d7a: 4ba6 ldr r3, [pc, #664] ; (8007014 <_dtoa_r+0x31c>) 8006d7c: e021 b.n 8006dc2 <_dtoa_r+0xca> 8006d7e: 4ba6 ldr r3, [pc, #664] ; (8007018 <_dtoa_r+0x320>) 8006d80: 9306 str r3, [sp, #24] 8006d82: 3308 adds r3, #8 8006d84: 9a22 ldr r2, [sp, #136] ; 0x88 8006d86: 6013 str r3, [r2, #0] 8006d88: 9806 ldr r0, [sp, #24] 8006d8a: b015 add sp, #84 ; 0x54 8006d8c: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8006d90: 4ba0 ldr r3, [pc, #640] ; (8007014 <_dtoa_r+0x31c>) 8006d92: 9306 str r3, [sp, #24] 8006d94: 3303 adds r3, #3 8006d96: e7f5 b.n 8006d84 <_dtoa_r+0x8c> 8006d98: e9dd 6702 ldrd r6, r7, [sp, #8] 8006d9c: 2200 movs r2, #0 8006d9e: 2300 movs r3, #0 8006da0: 4630 mov r0, r6 8006da2: 4639 mov r1, r7 8006da4: f7f9 fe60 bl 8000a68 <__aeabi_dcmpeq> 8006da8: 4682 mov sl, r0 8006daa: b160 cbz r0, 8006dc6 <_dtoa_r+0xce> 8006dac: 2301 movs r3, #1 8006dae: 9a20 ldr r2, [sp, #128] ; 0x80 8006db0: 6013 str r3, [r2, #0] 8006db2: 9b22 ldr r3, [sp, #136] ; 0x88 8006db4: 2b00 cmp r3, #0 8006db6: f000 8520 beq.w 80077fa <_dtoa_r+0xb02> 8006dba: 4b98 ldr r3, [pc, #608] ; (800701c <_dtoa_r+0x324>) 8006dbc: 9a22 ldr r2, [sp, #136] ; 0x88 8006dbe: 6013 str r3, [r2, #0] 8006dc0: 3b01 subs r3, #1 8006dc2: 9306 str r3, [sp, #24] 8006dc4: e7e0 b.n 8006d88 <_dtoa_r+0x90> 8006dc6: ab12 add r3, sp, #72 ; 0x48 8006dc8: 9301 str r3, [sp, #4] 8006dca: ab13 add r3, sp, #76 ; 0x4c 8006dcc: 9300 str r3, [sp, #0] 8006dce: 4632 mov r2, r6 8006dd0: 463b mov r3, r7 8006dd2: 4620 mov r0, r4 8006dd4: f001 f9de bl 8008194 <__d2b> 8006dd8: f3c8 550a ubfx r5, r8, #20, #11 8006ddc: 4683 mov fp, r0 8006dde: 2d00 cmp r5, #0 8006de0: d07d beq.n 8006ede <_dtoa_r+0x1e6> 8006de2: 46b0 mov r8, r6 8006de4: f3c7 0313 ubfx r3, r7, #0, #20 8006de8: f043 597f orr.w r9, r3, #1069547520 ; 0x3fc00000 8006dec: f449 1940 orr.w r9, r9, #3145728 ; 0x300000 8006df0: f2a5 35ff subw r5, r5, #1023 ; 0x3ff 8006df4: f8cd a040 str.w sl, [sp, #64] ; 0x40 8006df8: 2200 movs r2, #0 8006dfa: 4b89 ldr r3, [pc, #548] ; (8007020 <_dtoa_r+0x328>) 8006dfc: 4640 mov r0, r8 8006dfe: 4649 mov r1, r9 8006e00: f7f9 fa12 bl 8000228 <__aeabi_dsub> 8006e04: a37c add r3, pc, #496 ; (adr r3, 8006ff8 <_dtoa_r+0x300>) 8006e06: e9d3 2300 ldrd r2, r3, [r3] 8006e0a: f7f9 fbc5 bl 8000598 <__aeabi_dmul> 8006e0e: a37c add r3, pc, #496 ; (adr r3, 8007000 <_dtoa_r+0x308>) 8006e10: e9d3 2300 ldrd r2, r3, [r3] 8006e14: f7f9 fa0a bl 800022c <__adddf3> 8006e18: 4606 mov r6, r0 8006e1a: 4628 mov r0, r5 8006e1c: 460f mov r7, r1 8006e1e: f7f9 fb51 bl 80004c4 <__aeabi_i2d> 8006e22: a379 add r3, pc, #484 ; (adr r3, 8007008 <_dtoa_r+0x310>) 8006e24: e9d3 2300 ldrd r2, r3, [r3] 8006e28: f7f9 fbb6 bl 8000598 <__aeabi_dmul> 8006e2c: 4602 mov r2, r0 8006e2e: 460b mov r3, r1 8006e30: 4630 mov r0, r6 8006e32: 4639 mov r1, r7 8006e34: f7f9 f9fa bl 800022c <__adddf3> 8006e38: 4606 mov r6, r0 8006e3a: 460f mov r7, r1 8006e3c: f7f9 fe5c bl 8000af8 <__aeabi_d2iz> 8006e40: 2200 movs r2, #0 8006e42: 4682 mov sl, r0 8006e44: 2300 movs r3, #0 8006e46: 4630 mov r0, r6 8006e48: 4639 mov r1, r7 8006e4a: f7f9 fe17 bl 8000a7c <__aeabi_dcmplt> 8006e4e: b148 cbz r0, 8006e64 <_dtoa_r+0x16c> 8006e50: 4650 mov r0, sl 8006e52: f7f9 fb37 bl 80004c4 <__aeabi_i2d> 8006e56: 4632 mov r2, r6 8006e58: 463b mov r3, r7 8006e5a: f7f9 fe05 bl 8000a68 <__aeabi_dcmpeq> 8006e5e: b908 cbnz r0, 8006e64 <_dtoa_r+0x16c> 8006e60: f10a 3aff add.w sl, sl, #4294967295 8006e64: f1ba 0f16 cmp.w sl, #22 8006e68: d85a bhi.n 8006f20 <_dtoa_r+0x228> 8006e6a: e9dd 2302 ldrd r2, r3, [sp, #8] 8006e6e: 496d ldr r1, [pc, #436] ; (8007024 <_dtoa_r+0x32c>) 8006e70: eb01 01ca add.w r1, r1, sl, lsl #3 8006e74: e9d1 0100 ldrd r0, r1, [r1] 8006e78: f7f9 fe1e bl 8000ab8 <__aeabi_dcmpgt> 8006e7c: 2800 cmp r0, #0 8006e7e: d051 beq.n 8006f24 <_dtoa_r+0x22c> 8006e80: 2300 movs r3, #0 8006e82: f10a 3aff add.w sl, sl, #4294967295 8006e86: 930d str r3, [sp, #52] ; 0x34 8006e88: 9b12 ldr r3, [sp, #72] ; 0x48 8006e8a: 1b5d subs r5, r3, r5 8006e8c: 1e6b subs r3, r5, #1 8006e8e: 9307 str r3, [sp, #28] 8006e90: bf43 ittte mi 8006e92: 2300 movmi r3, #0 8006e94: f1c5 0901 rsbmi r9, r5, #1 8006e98: 9307 strmi r3, [sp, #28] 8006e9a: f04f 0900 movpl.w r9, #0 8006e9e: f1ba 0f00 cmp.w sl, #0 8006ea2: db41 blt.n 8006f28 <_dtoa_r+0x230> 8006ea4: 9b07 ldr r3, [sp, #28] 8006ea6: f8cd a030 str.w sl, [sp, #48] ; 0x30 8006eaa: 4453 add r3, sl 8006eac: 9307 str r3, [sp, #28] 8006eae: 2300 movs r3, #0 8006eb0: 9308 str r3, [sp, #32] 8006eb2: 9b1e ldr r3, [sp, #120] ; 0x78 8006eb4: 2b09 cmp r3, #9 8006eb6: f200 808f bhi.w 8006fd8 <_dtoa_r+0x2e0> 8006eba: 2b05 cmp r3, #5 8006ebc: bfc4 itt gt 8006ebe: 3b04 subgt r3, #4 8006ec0: 931e strgt r3, [sp, #120] ; 0x78 8006ec2: 9b1e ldr r3, [sp, #120] ; 0x78 8006ec4: bfc8 it gt 8006ec6: 2500 movgt r5, #0 8006ec8: f1a3 0302 sub.w r3, r3, #2 8006ecc: bfd8 it le 8006ece: 2501 movle r5, #1 8006ed0: 2b03 cmp r3, #3 8006ed2: f200 808d bhi.w 8006ff0 <_dtoa_r+0x2f8> 8006ed6: e8df f003 tbb [pc, r3] 8006eda: 7d7b .short 0x7d7b 8006edc: 6f2f .short 0x6f2f 8006ede: e9dd 5312 ldrd r5, r3, [sp, #72] ; 0x48 8006ee2: 441d add r5, r3 8006ee4: f205 4032 addw r0, r5, #1074 ; 0x432 8006ee8: 2820 cmp r0, #32 8006eea: dd13 ble.n 8006f14 <_dtoa_r+0x21c> 8006eec: f1c0 0040 rsb r0, r0, #64 ; 0x40 8006ef0: 9b02 ldr r3, [sp, #8] 8006ef2: fa08 f800 lsl.w r8, r8, r0 8006ef6: f205 4012 addw r0, r5, #1042 ; 0x412 8006efa: fa23 f000 lsr.w r0, r3, r0 8006efe: ea48 0000 orr.w r0, r8, r0 8006f02: f7f9 facf bl 80004a4 <__aeabi_ui2d> 8006f06: 2301 movs r3, #1 8006f08: 4680 mov r8, r0 8006f0a: f1a1 79f8 sub.w r9, r1, #32505856 ; 0x1f00000 8006f0e: 3d01 subs r5, #1 8006f10: 9310 str r3, [sp, #64] ; 0x40 8006f12: e771 b.n 8006df8 <_dtoa_r+0x100> 8006f14: 9b02 ldr r3, [sp, #8] 8006f16: f1c0 0020 rsb r0, r0, #32 8006f1a: fa03 f000 lsl.w r0, r3, r0 8006f1e: e7f0 b.n 8006f02 <_dtoa_r+0x20a> 8006f20: 2301 movs r3, #1 8006f22: e7b0 b.n 8006e86 <_dtoa_r+0x18e> 8006f24: 900d str r0, [sp, #52] ; 0x34 8006f26: e7af b.n 8006e88 <_dtoa_r+0x190> 8006f28: f1ca 0300 rsb r3, sl, #0 8006f2c: 9308 str r3, [sp, #32] 8006f2e: 2300 movs r3, #0 8006f30: eba9 090a sub.w r9, r9, sl 8006f34: 930c str r3, [sp, #48] ; 0x30 8006f36: e7bc b.n 8006eb2 <_dtoa_r+0x1ba> 8006f38: 2301 movs r3, #1 8006f3a: 9309 str r3, [sp, #36] ; 0x24 8006f3c: 9b1f ldr r3, [sp, #124] ; 0x7c 8006f3e: 2b00 cmp r3, #0 8006f40: dd74 ble.n 800702c <_dtoa_r+0x334> 8006f42: 4698 mov r8, r3 8006f44: 9304 str r3, [sp, #16] 8006f46: 2200 movs r2, #0 8006f48: 6a66 ldr r6, [r4, #36] ; 0x24 8006f4a: 6072 str r2, [r6, #4] 8006f4c: 2204 movs r2, #4 8006f4e: f102 0014 add.w r0, r2, #20 8006f52: 4298 cmp r0, r3 8006f54: 6871 ldr r1, [r6, #4] 8006f56: d96e bls.n 8007036 <_dtoa_r+0x33e> 8006f58: 4620 mov r0, r4 8006f5a: f000 fe8e bl 8007c7a <_Balloc> 8006f5e: 6a63 ldr r3, [r4, #36] ; 0x24 8006f60: 6030 str r0, [r6, #0] 8006f62: 681b ldr r3, [r3, #0] 8006f64: f1b8 0f0e cmp.w r8, #14 8006f68: 9306 str r3, [sp, #24] 8006f6a: f200 80ed bhi.w 8007148 <_dtoa_r+0x450> 8006f6e: 2d00 cmp r5, #0 8006f70: f000 80ea beq.w 8007148 <_dtoa_r+0x450> 8006f74: e9dd 2302 ldrd r2, r3, [sp, #8] 8006f78: f1ba 0f00 cmp.w sl, #0 8006f7c: e9cd 230e strd r2, r3, [sp, #56] ; 0x38 8006f80: dd77 ble.n 8007072 <_dtoa_r+0x37a> 8006f82: 4a28 ldr r2, [pc, #160] ; (8007024 <_dtoa_r+0x32c>) 8006f84: f00a 030f and.w r3, sl, #15 8006f88: ea4f 162a mov.w r6, sl, asr #4 8006f8c: eb02 03c3 add.w r3, r2, r3, lsl #3 8006f90: 06f0 lsls r0, r6, #27 8006f92: e9d3 2300 ldrd r2, r3, [r3] 8006f96: e9cd 230a strd r2, r3, [sp, #40] ; 0x28 8006f9a: d568 bpl.n 800706e <_dtoa_r+0x376> 8006f9c: e9dd 010e ldrd r0, r1, [sp, #56] ; 0x38 8006fa0: 4b21 ldr r3, [pc, #132] ; (8007028 <_dtoa_r+0x330>) 8006fa2: 2503 movs r5, #3 8006fa4: e9d3 2308 ldrd r2, r3, [r3, #32] 8006fa8: f7f9 fc20 bl 80007ec <__aeabi_ddiv> 8006fac: e9cd 0102 strd r0, r1, [sp, #8] 8006fb0: f006 060f and.w r6, r6, #15 8006fb4: 4f1c ldr r7, [pc, #112] ; (8007028 <_dtoa_r+0x330>) 8006fb6: e04f b.n 8007058 <_dtoa_r+0x360> 8006fb8: 2301 movs r3, #1 8006fba: 9309 str r3, [sp, #36] ; 0x24 8006fbc: 9b1f ldr r3, [sp, #124] ; 0x7c 8006fbe: 4453 add r3, sl 8006fc0: f103 0801 add.w r8, r3, #1 8006fc4: 9304 str r3, [sp, #16] 8006fc6: 4643 mov r3, r8 8006fc8: 2b01 cmp r3, #1 8006fca: bfb8 it lt 8006fcc: 2301 movlt r3, #1 8006fce: e7ba b.n 8006f46 <_dtoa_r+0x24e> 8006fd0: 2300 movs r3, #0 8006fd2: e7b2 b.n 8006f3a <_dtoa_r+0x242> 8006fd4: 2300 movs r3, #0 8006fd6: e7f0 b.n 8006fba <_dtoa_r+0x2c2> 8006fd8: 2501 movs r5, #1 8006fda: 2300 movs r3, #0 8006fdc: 9509 str r5, [sp, #36] ; 0x24 8006fde: 931e str r3, [sp, #120] ; 0x78 8006fe0: f04f 33ff mov.w r3, #4294967295 8006fe4: 2200 movs r2, #0 8006fe6: 9304 str r3, [sp, #16] 8006fe8: 4698 mov r8, r3 8006fea: 2312 movs r3, #18 8006fec: 921f str r2, [sp, #124] ; 0x7c 8006fee: e7aa b.n 8006f46 <_dtoa_r+0x24e> 8006ff0: 2301 movs r3, #1 8006ff2: 9309 str r3, [sp, #36] ; 0x24 8006ff4: e7f4 b.n 8006fe0 <_dtoa_r+0x2e8> 8006ff6: bf00 nop 8006ff8: 636f4361 .word 0x636f4361 8006ffc: 3fd287a7 .word 0x3fd287a7 8007000: 8b60c8b3 .word 0x8b60c8b3 8007004: 3fc68a28 .word 0x3fc68a28 8007008: 509f79fb .word 0x509f79fb 800700c: 3fd34413 .word 0x3fd34413 8007010: 7ff00000 .word 0x7ff00000 8007014: 08008bf1 .word 0x08008bf1 8007018: 08008be8 .word 0x08008be8 800701c: 08008bc5 .word 0x08008bc5 8007020: 3ff80000 .word 0x3ff80000 8007024: 08008c80 .word 0x08008c80 8007028: 08008c58 .word 0x08008c58 800702c: 2301 movs r3, #1 800702e: 9304 str r3, [sp, #16] 8007030: 4698 mov r8, r3 8007032: 461a mov r2, r3 8007034: e7da b.n 8006fec <_dtoa_r+0x2f4> 8007036: 3101 adds r1, #1 8007038: 6071 str r1, [r6, #4] 800703a: 0052 lsls r2, r2, #1 800703c: e787 b.n 8006f4e <_dtoa_r+0x256> 800703e: 07f1 lsls r1, r6, #31 8007040: d508 bpl.n 8007054 <_dtoa_r+0x35c> 8007042: e9dd 010a ldrd r0, r1, [sp, #40] ; 0x28 8007046: e9d7 2300 ldrd r2, r3, [r7] 800704a: f7f9 faa5 bl 8000598 <__aeabi_dmul> 800704e: e9cd 010a strd r0, r1, [sp, #40] ; 0x28 8007052: 3501 adds r5, #1 8007054: 1076 asrs r6, r6, #1 8007056: 3708 adds r7, #8 8007058: 2e00 cmp r6, #0 800705a: d1f0 bne.n 800703e <_dtoa_r+0x346> 800705c: e9dd 230a ldrd r2, r3, [sp, #40] ; 0x28 8007060: e9dd 0102 ldrd r0, r1, [sp, #8] 8007064: f7f9 fbc2 bl 80007ec <__aeabi_ddiv> 8007068: e9cd 0102 strd r0, r1, [sp, #8] 800706c: e01b b.n 80070a6 <_dtoa_r+0x3ae> 800706e: 2502 movs r5, #2 8007070: e7a0 b.n 8006fb4 <_dtoa_r+0x2bc> 8007072: f000 80a4 beq.w 80071be <_dtoa_r+0x4c6> 8007076: e9dd 010e ldrd r0, r1, [sp, #56] ; 0x38 800707a: f1ca 0600 rsb r6, sl, #0 800707e: 4ba0 ldr r3, [pc, #640] ; (8007300 <_dtoa_r+0x608>) 8007080: f006 020f and.w r2, r6, #15 8007084: eb03 03c2 add.w r3, r3, r2, lsl #3 8007088: e9d3 2300 ldrd r2, r3, [r3] 800708c: f7f9 fa84 bl 8000598 <__aeabi_dmul> 8007090: 2502 movs r5, #2 8007092: 2300 movs r3, #0 8007094: e9cd 0102 strd r0, r1, [sp, #8] 8007098: 4f9a ldr r7, [pc, #616] ; (8007304 <_dtoa_r+0x60c>) 800709a: 1136 asrs r6, r6, #4 800709c: 2e00 cmp r6, #0 800709e: f040 8083 bne.w 80071a8 <_dtoa_r+0x4b0> 80070a2: 2b00 cmp r3, #0 80070a4: d1e0 bne.n 8007068 <_dtoa_r+0x370> 80070a6: 9b0d ldr r3, [sp, #52] ; 0x34 80070a8: 2b00 cmp r3, #0 80070aa: f000 808a beq.w 80071c2 <_dtoa_r+0x4ca> 80070ae: e9dd 2302 ldrd r2, r3, [sp, #8] 80070b2: e9cd 230a strd r2, r3, [sp, #40] ; 0x28 80070b6: e9dd 010a ldrd r0, r1, [sp, #40] ; 0x28 80070ba: 2200 movs r2, #0 80070bc: 4b92 ldr r3, [pc, #584] ; (8007308 <_dtoa_r+0x610>) 80070be: f7f9 fcdd bl 8000a7c <__aeabi_dcmplt> 80070c2: 2800 cmp r0, #0 80070c4: d07d beq.n 80071c2 <_dtoa_r+0x4ca> 80070c6: f1b8 0f00 cmp.w r8, #0 80070ca: d07a beq.n 80071c2 <_dtoa_r+0x4ca> 80070cc: 9b04 ldr r3, [sp, #16] 80070ce: 2b00 cmp r3, #0 80070d0: dd36 ble.n 8007140 <_dtoa_r+0x448> 80070d2: e9dd 010a ldrd r0, r1, [sp, #40] ; 0x28 80070d6: 2200 movs r2, #0 80070d8: 4b8c ldr r3, [pc, #560] ; (800730c <_dtoa_r+0x614>) 80070da: f7f9 fa5d bl 8000598 <__aeabi_dmul> 80070de: e9cd 0102 strd r0, r1, [sp, #8] 80070e2: 9e04 ldr r6, [sp, #16] 80070e4: f10a 37ff add.w r7, sl, #4294967295 80070e8: 3501 adds r5, #1 80070ea: 4628 mov r0, r5 80070ec: f7f9 f9ea bl 80004c4 <__aeabi_i2d> 80070f0: e9dd 2302 ldrd r2, r3, [sp, #8] 80070f4: f7f9 fa50 bl 8000598 <__aeabi_dmul> 80070f8: 2200 movs r2, #0 80070fa: 4b85 ldr r3, [pc, #532] ; (8007310 <_dtoa_r+0x618>) 80070fc: f7f9 f896 bl 800022c <__adddf3> 8007100: f1a1 7550 sub.w r5, r1, #54525952 ; 0x3400000 8007104: e9cd 010a strd r0, r1, [sp, #40] ; 0x28 8007108: 950b str r5, [sp, #44] ; 0x2c 800710a: 2e00 cmp r6, #0 800710c: d15c bne.n 80071c8 <_dtoa_r+0x4d0> 800710e: e9dd 0102 ldrd r0, r1, [sp, #8] 8007112: 2200 movs r2, #0 8007114: 4b7f ldr r3, [pc, #508] ; (8007314 <_dtoa_r+0x61c>) 8007116: f7f9 f887 bl 8000228 <__aeabi_dsub> 800711a: 9a0a ldr r2, [sp, #40] ; 0x28 800711c: 462b mov r3, r5 800711e: e9cd 0102 strd r0, r1, [sp, #8] 8007122: f7f9 fcc9 bl 8000ab8 <__aeabi_dcmpgt> 8007126: 2800 cmp r0, #0 8007128: f040 8281 bne.w 800762e <_dtoa_r+0x936> 800712c: e9dd 0102 ldrd r0, r1, [sp, #8] 8007130: 9a0a ldr r2, [sp, #40] ; 0x28 8007132: f105 4300 add.w r3, r5, #2147483648 ; 0x80000000 8007136: f7f9 fca1 bl 8000a7c <__aeabi_dcmplt> 800713a: 2800 cmp r0, #0 800713c: f040 8275 bne.w 800762a <_dtoa_r+0x932> 8007140: e9dd 230e ldrd r2, r3, [sp, #56] ; 0x38 8007144: e9cd 2302 strd r2, r3, [sp, #8] 8007148: 9b13 ldr r3, [sp, #76] ; 0x4c 800714a: 2b00 cmp r3, #0 800714c: f2c0 814b blt.w 80073e6 <_dtoa_r+0x6ee> 8007150: f1ba 0f0e cmp.w sl, #14 8007154: f300 8147 bgt.w 80073e6 <_dtoa_r+0x6ee> 8007158: 4b69 ldr r3, [pc, #420] ; (8007300 <_dtoa_r+0x608>) 800715a: eb03 03ca add.w r3, r3, sl, lsl #3 800715e: e9d3 2300 ldrd r2, r3, [r3] 8007162: e9cd 2304 strd r2, r3, [sp, #16] 8007166: 9b1f ldr r3, [sp, #124] ; 0x7c 8007168: 2b00 cmp r3, #0 800716a: f280 80d7 bge.w 800731c <_dtoa_r+0x624> 800716e: f1b8 0f00 cmp.w r8, #0 8007172: f300 80d3 bgt.w 800731c <_dtoa_r+0x624> 8007176: f040 8257 bne.w 8007628 <_dtoa_r+0x930> 800717a: e9dd 0104 ldrd r0, r1, [sp, #16] 800717e: 2200 movs r2, #0 8007180: 4b64 ldr r3, [pc, #400] ; (8007314 <_dtoa_r+0x61c>) 8007182: f7f9 fa09 bl 8000598 <__aeabi_dmul> 8007186: e9dd 2302 ldrd r2, r3, [sp, #8] 800718a: f7f9 fc8b bl 8000aa4 <__aeabi_dcmpge> 800718e: 4646 mov r6, r8 8007190: 4647 mov r7, r8 8007192: 2800 cmp r0, #0 8007194: f040 822d bne.w 80075f2 <_dtoa_r+0x8fa> 8007198: 9b06 ldr r3, [sp, #24] 800719a: 9a06 ldr r2, [sp, #24] 800719c: 1c5d adds r5, r3, #1 800719e: 2331 movs r3, #49 ; 0x31 80071a0: f10a 0a01 add.w sl, sl, #1 80071a4: 7013 strb r3, [r2, #0] 80071a6: e228 b.n 80075fa <_dtoa_r+0x902> 80071a8: 07f2 lsls r2, r6, #31 80071aa: d505 bpl.n 80071b8 <_dtoa_r+0x4c0> 80071ac: e9d7 2300 ldrd r2, r3, [r7] 80071b0: f7f9 f9f2 bl 8000598 <__aeabi_dmul> 80071b4: 2301 movs r3, #1 80071b6: 3501 adds r5, #1 80071b8: 1076 asrs r6, r6, #1 80071ba: 3708 adds r7, #8 80071bc: e76e b.n 800709c <_dtoa_r+0x3a4> 80071be: 2502 movs r5, #2 80071c0: e771 b.n 80070a6 <_dtoa_r+0x3ae> 80071c2: 4657 mov r7, sl 80071c4: 4646 mov r6, r8 80071c6: e790 b.n 80070ea <_dtoa_r+0x3f2> 80071c8: 4b4d ldr r3, [pc, #308] ; (8007300 <_dtoa_r+0x608>) 80071ca: eb03 03c6 add.w r3, r3, r6, lsl #3 80071ce: e953 0102 ldrd r0, r1, [r3, #-8] 80071d2: 9b09 ldr r3, [sp, #36] ; 0x24 80071d4: 2b00 cmp r3, #0 80071d6: d048 beq.n 800726a <_dtoa_r+0x572> 80071d8: 4602 mov r2, r0 80071da: 460b mov r3, r1 80071dc: 2000 movs r0, #0 80071de: 494e ldr r1, [pc, #312] ; (8007318 <_dtoa_r+0x620>) 80071e0: f7f9 fb04 bl 80007ec <__aeabi_ddiv> 80071e4: e9dd 230a ldrd r2, r3, [sp, #40] ; 0x28 80071e8: f7f9 f81e bl 8000228 <__aeabi_dsub> 80071ec: e9cd 010a strd r0, r1, [sp, #40] ; 0x28 80071f0: 9d06 ldr r5, [sp, #24] 80071f2: e9dd 0102 ldrd r0, r1, [sp, #8] 80071f6: f7f9 fc7f bl 8000af8 <__aeabi_d2iz> 80071fa: 9011 str r0, [sp, #68] ; 0x44 80071fc: f7f9 f962 bl 80004c4 <__aeabi_i2d> 8007200: 4602 mov r2, r0 8007202: 460b mov r3, r1 8007204: e9dd 0102 ldrd r0, r1, [sp, #8] 8007208: f7f9 f80e bl 8000228 <__aeabi_dsub> 800720c: 9b11 ldr r3, [sp, #68] ; 0x44 800720e: e9cd 0102 strd r0, r1, [sp, #8] 8007212: 3330 adds r3, #48 ; 0x30 8007214: f805 3b01 strb.w r3, [r5], #1 8007218: e9dd 230a ldrd r2, r3, [sp, #40] ; 0x28 800721c: f7f9 fc2e bl 8000a7c <__aeabi_dcmplt> 8007220: 2800 cmp r0, #0 8007222: d163 bne.n 80072ec <_dtoa_r+0x5f4> 8007224: e9dd 2302 ldrd r2, r3, [sp, #8] 8007228: 2000 movs r0, #0 800722a: 4937 ldr r1, [pc, #220] ; (8007308 <_dtoa_r+0x610>) 800722c: f7f8 fffc bl 8000228 <__aeabi_dsub> 8007230: e9dd 230a ldrd r2, r3, [sp, #40] ; 0x28 8007234: f7f9 fc22 bl 8000a7c <__aeabi_dcmplt> 8007238: 2800 cmp r0, #0 800723a: f040 80b5 bne.w 80073a8 <_dtoa_r+0x6b0> 800723e: 9b06 ldr r3, [sp, #24] 8007240: 1aeb subs r3, r5, r3 8007242: 429e cmp r6, r3 8007244: f77f af7c ble.w 8007140 <_dtoa_r+0x448> 8007248: e9dd 010a ldrd r0, r1, [sp, #40] ; 0x28 800724c: 2200 movs r2, #0 800724e: 4b2f ldr r3, [pc, #188] ; (800730c <_dtoa_r+0x614>) 8007250: f7f9 f9a2 bl 8000598 <__aeabi_dmul> 8007254: 2200 movs r2, #0 8007256: e9cd 010a strd r0, r1, [sp, #40] ; 0x28 800725a: e9dd 0102 ldrd r0, r1, [sp, #8] 800725e: 4b2b ldr r3, [pc, #172] ; (800730c <_dtoa_r+0x614>) 8007260: f7f9 f99a bl 8000598 <__aeabi_dmul> 8007264: e9cd 0102 strd r0, r1, [sp, #8] 8007268: e7c3 b.n 80071f2 <_dtoa_r+0x4fa> 800726a: e9dd 230a ldrd r2, r3, [sp, #40] ; 0x28 800726e: f7f9 f993 bl 8000598 <__aeabi_dmul> 8007272: 9b06 ldr r3, [sp, #24] 8007274: e9cd 010a strd r0, r1, [sp, #40] ; 0x28 8007278: 199d adds r5, r3, r6 800727a: 461e mov r6, r3 800727c: e9dd 0102 ldrd r0, r1, [sp, #8] 8007280: f7f9 fc3a bl 8000af8 <__aeabi_d2iz> 8007284: 9011 str r0, [sp, #68] ; 0x44 8007286: f7f9 f91d bl 80004c4 <__aeabi_i2d> 800728a: 4602 mov r2, r0 800728c: 460b mov r3, r1 800728e: e9dd 0102 ldrd r0, r1, [sp, #8] 8007292: f7f8 ffc9 bl 8000228 <__aeabi_dsub> 8007296: 9b11 ldr r3, [sp, #68] ; 0x44 8007298: e9cd 0102 strd r0, r1, [sp, #8] 800729c: 3330 adds r3, #48 ; 0x30 800729e: f806 3b01 strb.w r3, [r6], #1 80072a2: 42ae cmp r6, r5 80072a4: f04f 0200 mov.w r2, #0 80072a8: d124 bne.n 80072f4 <_dtoa_r+0x5fc> 80072aa: e9dd 010a ldrd r0, r1, [sp, #40] ; 0x28 80072ae: 4b1a ldr r3, [pc, #104] ; (8007318 <_dtoa_r+0x620>) 80072b0: f7f8 ffbc bl 800022c <__adddf3> 80072b4: 4602 mov r2, r0 80072b6: 460b mov r3, r1 80072b8: e9dd 0102 ldrd r0, r1, [sp, #8] 80072bc: f7f9 fbfc bl 8000ab8 <__aeabi_dcmpgt> 80072c0: 2800 cmp r0, #0 80072c2: d171 bne.n 80073a8 <_dtoa_r+0x6b0> 80072c4: e9dd 230a ldrd r2, r3, [sp, #40] ; 0x28 80072c8: 2000 movs r0, #0 80072ca: 4913 ldr r1, [pc, #76] ; (8007318 <_dtoa_r+0x620>) 80072cc: f7f8 ffac bl 8000228 <__aeabi_dsub> 80072d0: 4602 mov r2, r0 80072d2: 460b mov r3, r1 80072d4: e9dd 0102 ldrd r0, r1, [sp, #8] 80072d8: f7f9 fbd0 bl 8000a7c <__aeabi_dcmplt> 80072dc: 2800 cmp r0, #0 80072de: f43f af2f beq.w 8007140 <_dtoa_r+0x448> 80072e2: f815 3c01 ldrb.w r3, [r5, #-1] 80072e6: 1e6a subs r2, r5, #1 80072e8: 2b30 cmp r3, #48 ; 0x30 80072ea: d001 beq.n 80072f0 <_dtoa_r+0x5f8> 80072ec: 46ba mov sl, r7 80072ee: e04a b.n 8007386 <_dtoa_r+0x68e> 80072f0: 4615 mov r5, r2 80072f2: e7f6 b.n 80072e2 <_dtoa_r+0x5ea> 80072f4: 4b05 ldr r3, [pc, #20] ; (800730c <_dtoa_r+0x614>) 80072f6: f7f9 f94f bl 8000598 <__aeabi_dmul> 80072fa: e9cd 0102 strd r0, r1, [sp, #8] 80072fe: e7bd b.n 800727c <_dtoa_r+0x584> 8007300: 08008c80 .word 0x08008c80 8007304: 08008c58 .word 0x08008c58 8007308: 3ff00000 .word 0x3ff00000 800730c: 40240000 .word 0x40240000 8007310: 401c0000 .word 0x401c0000 8007314: 40140000 .word 0x40140000 8007318: 3fe00000 .word 0x3fe00000 800731c: 9d06 ldr r5, [sp, #24] 800731e: e9dd 6702 ldrd r6, r7, [sp, #8] 8007322: e9dd 2304 ldrd r2, r3, [sp, #16] 8007326: 4630 mov r0, r6 8007328: 4639 mov r1, r7 800732a: f7f9 fa5f bl 80007ec <__aeabi_ddiv> 800732e: f7f9 fbe3 bl 8000af8 <__aeabi_d2iz> 8007332: 4681 mov r9, r0 8007334: f7f9 f8c6 bl 80004c4 <__aeabi_i2d> 8007338: e9dd 2304 ldrd r2, r3, [sp, #16] 800733c: f7f9 f92c bl 8000598 <__aeabi_dmul> 8007340: 4602 mov r2, r0 8007342: 460b mov r3, r1 8007344: 4630 mov r0, r6 8007346: 4639 mov r1, r7 8007348: f7f8 ff6e bl 8000228 <__aeabi_dsub> 800734c: f109 0630 add.w r6, r9, #48 ; 0x30 8007350: f805 6b01 strb.w r6, [r5], #1 8007354: 9e06 ldr r6, [sp, #24] 8007356: 4602 mov r2, r0 8007358: 1bae subs r6, r5, r6 800735a: 45b0 cmp r8, r6 800735c: 460b mov r3, r1 800735e: d135 bne.n 80073cc <_dtoa_r+0x6d4> 8007360: f7f8 ff64 bl 800022c <__adddf3> 8007364: e9dd 2304 ldrd r2, r3, [sp, #16] 8007368: 4606 mov r6, r0 800736a: 460f mov r7, r1 800736c: f7f9 fba4 bl 8000ab8 <__aeabi_dcmpgt> 8007370: b9c8 cbnz r0, 80073a6 <_dtoa_r+0x6ae> 8007372: e9dd 2304 ldrd r2, r3, [sp, #16] 8007376: 4630 mov r0, r6 8007378: 4639 mov r1, r7 800737a: f7f9 fb75 bl 8000a68 <__aeabi_dcmpeq> 800737e: b110 cbz r0, 8007386 <_dtoa_r+0x68e> 8007380: f019 0f01 tst.w r9, #1 8007384: d10f bne.n 80073a6 <_dtoa_r+0x6ae> 8007386: 4659 mov r1, fp 8007388: 4620 mov r0, r4 800738a: f000 fcaa bl 8007ce2 <_Bfree> 800738e: 2300 movs r3, #0 8007390: 9a20 ldr r2, [sp, #128] ; 0x80 8007392: 702b strb r3, [r5, #0] 8007394: f10a 0301 add.w r3, sl, #1 8007398: 6013 str r3, [r2, #0] 800739a: 9b22 ldr r3, [sp, #136] ; 0x88 800739c: 2b00 cmp r3, #0 800739e: f43f acf3 beq.w 8006d88 <_dtoa_r+0x90> 80073a2: 601d str r5, [r3, #0] 80073a4: e4f0 b.n 8006d88 <_dtoa_r+0x90> 80073a6: 4657 mov r7, sl 80073a8: f815 2c01 ldrb.w r2, [r5, #-1] 80073ac: 1e6b subs r3, r5, #1 80073ae: 2a39 cmp r2, #57 ; 0x39 80073b0: d106 bne.n 80073c0 <_dtoa_r+0x6c8> 80073b2: 9a06 ldr r2, [sp, #24] 80073b4: 429a cmp r2, r3 80073b6: d107 bne.n 80073c8 <_dtoa_r+0x6d0> 80073b8: 2330 movs r3, #48 ; 0x30 80073ba: 7013 strb r3, [r2, #0] 80073bc: 4613 mov r3, r2 80073be: 3701 adds r7, #1 80073c0: 781a ldrb r2, [r3, #0] 80073c2: 3201 adds r2, #1 80073c4: 701a strb r2, [r3, #0] 80073c6: e791 b.n 80072ec <_dtoa_r+0x5f4> 80073c8: 461d mov r5, r3 80073ca: e7ed b.n 80073a8 <_dtoa_r+0x6b0> 80073cc: 2200 movs r2, #0 80073ce: 4b99 ldr r3, [pc, #612] ; (8007634 <_dtoa_r+0x93c>) 80073d0: f7f9 f8e2 bl 8000598 <__aeabi_dmul> 80073d4: 2200 movs r2, #0 80073d6: 2300 movs r3, #0 80073d8: 4606 mov r6, r0 80073da: 460f mov r7, r1 80073dc: f7f9 fb44 bl 8000a68 <__aeabi_dcmpeq> 80073e0: 2800 cmp r0, #0 80073e2: d09e beq.n 8007322 <_dtoa_r+0x62a> 80073e4: e7cf b.n 8007386 <_dtoa_r+0x68e> 80073e6: 9a09 ldr r2, [sp, #36] ; 0x24 80073e8: 2a00 cmp r2, #0 80073ea: f000 8088 beq.w 80074fe <_dtoa_r+0x806> 80073ee: 9a1e ldr r2, [sp, #120] ; 0x78 80073f0: 2a01 cmp r2, #1 80073f2: dc6d bgt.n 80074d0 <_dtoa_r+0x7d8> 80073f4: 9a10 ldr r2, [sp, #64] ; 0x40 80073f6: 2a00 cmp r2, #0 80073f8: d066 beq.n 80074c8 <_dtoa_r+0x7d0> 80073fa: f203 4333 addw r3, r3, #1075 ; 0x433 80073fe: 464d mov r5, r9 8007400: 9e08 ldr r6, [sp, #32] 8007402: 9a07 ldr r2, [sp, #28] 8007404: 2101 movs r1, #1 8007406: 441a add r2, r3 8007408: 4620 mov r0, r4 800740a: 4499 add r9, r3 800740c: 9207 str r2, [sp, #28] 800740e: f000 fd08 bl 8007e22 <__i2b> 8007412: 4607 mov r7, r0 8007414: 2d00 cmp r5, #0 8007416: dd0b ble.n 8007430 <_dtoa_r+0x738> 8007418: 9b07 ldr r3, [sp, #28] 800741a: 2b00 cmp r3, #0 800741c: dd08 ble.n 8007430 <_dtoa_r+0x738> 800741e: 42ab cmp r3, r5 8007420: bfa8 it ge 8007422: 462b movge r3, r5 8007424: 9a07 ldr r2, [sp, #28] 8007426: eba9 0903 sub.w r9, r9, r3 800742a: 1aed subs r5, r5, r3 800742c: 1ad3 subs r3, r2, r3 800742e: 9307 str r3, [sp, #28] 8007430: 9b08 ldr r3, [sp, #32] 8007432: b1eb cbz r3, 8007470 <_dtoa_r+0x778> 8007434: 9b09 ldr r3, [sp, #36] ; 0x24 8007436: 2b00 cmp r3, #0 8007438: d065 beq.n 8007506 <_dtoa_r+0x80e> 800743a: b18e cbz r6, 8007460 <_dtoa_r+0x768> 800743c: 4639 mov r1, r7 800743e: 4632 mov r2, r6 8007440: 4620 mov r0, r4 8007442: f000 fd8d bl 8007f60 <__pow5mult> 8007446: 465a mov r2, fp 8007448: 4601 mov r1, r0 800744a: 4607 mov r7, r0 800744c: 4620 mov r0, r4 800744e: f000 fcf1 bl 8007e34 <__multiply> 8007452: 4659 mov r1, fp 8007454: 900a str r0, [sp, #40] ; 0x28 8007456: 4620 mov r0, r4 8007458: f000 fc43 bl 8007ce2 <_Bfree> 800745c: 9b0a ldr r3, [sp, #40] ; 0x28 800745e: 469b mov fp, r3 8007460: 9b08 ldr r3, [sp, #32] 8007462: 1b9a subs r2, r3, r6 8007464: d004 beq.n 8007470 <_dtoa_r+0x778> 8007466: 4659 mov r1, fp 8007468: 4620 mov r0, r4 800746a: f000 fd79 bl 8007f60 <__pow5mult> 800746e: 4683 mov fp, r0 8007470: 2101 movs r1, #1 8007472: 4620 mov r0, r4 8007474: f000 fcd5 bl 8007e22 <__i2b> 8007478: 9b0c ldr r3, [sp, #48] ; 0x30 800747a: 4606 mov r6, r0 800747c: 2b00 cmp r3, #0 800747e: f000 81c6 beq.w 800780e <_dtoa_r+0xb16> 8007482: 461a mov r2, r3 8007484: 4601 mov r1, r0 8007486: 4620 mov r0, r4 8007488: f000 fd6a bl 8007f60 <__pow5mult> 800748c: 9b1e ldr r3, [sp, #120] ; 0x78 800748e: 4606 mov r6, r0 8007490: 2b01 cmp r3, #1 8007492: dc3e bgt.n 8007512 <_dtoa_r+0x81a> 8007494: 9b02 ldr r3, [sp, #8] 8007496: 2b00 cmp r3, #0 8007498: d137 bne.n 800750a <_dtoa_r+0x812> 800749a: 9b03 ldr r3, [sp, #12] 800749c: f3c3 0313 ubfx r3, r3, #0, #20 80074a0: 2b00 cmp r3, #0 80074a2: d134 bne.n 800750e <_dtoa_r+0x816> 80074a4: 9b03 ldr r3, [sp, #12] 80074a6: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000 80074aa: 0d1b lsrs r3, r3, #20 80074ac: 051b lsls r3, r3, #20 80074ae: b12b cbz r3, 80074bc <_dtoa_r+0x7c4> 80074b0: 9b07 ldr r3, [sp, #28] 80074b2: f109 0901 add.w r9, r9, #1 80074b6: 3301 adds r3, #1 80074b8: 9307 str r3, [sp, #28] 80074ba: 2301 movs r3, #1 80074bc: 9308 str r3, [sp, #32] 80074be: 9b0c ldr r3, [sp, #48] ; 0x30 80074c0: 2b00 cmp r3, #0 80074c2: d128 bne.n 8007516 <_dtoa_r+0x81e> 80074c4: 2001 movs r0, #1 80074c6: e02e b.n 8007526 <_dtoa_r+0x82e> 80074c8: 9b12 ldr r3, [sp, #72] ; 0x48 80074ca: f1c3 0336 rsb r3, r3, #54 ; 0x36 80074ce: e796 b.n 80073fe <_dtoa_r+0x706> 80074d0: 9b08 ldr r3, [sp, #32] 80074d2: f108 36ff add.w r6, r8, #4294967295 80074d6: 42b3 cmp r3, r6 80074d8: bfb7 itett lt 80074da: 9b08 ldrlt r3, [sp, #32] 80074dc: 1b9e subge r6, r3, r6 80074de: 1af2 sublt r2, r6, r3 80074e0: 9b0c ldrlt r3, [sp, #48] ; 0x30 80074e2: bfbf itttt lt 80074e4: 9608 strlt r6, [sp, #32] 80074e6: 189b addlt r3, r3, r2 80074e8: 930c strlt r3, [sp, #48] ; 0x30 80074ea: 2600 movlt r6, #0 80074ec: f1b8 0f00 cmp.w r8, #0 80074f0: bfb9 ittee lt 80074f2: eba9 0508 sublt.w r5, r9, r8 80074f6: 2300 movlt r3, #0 80074f8: 464d movge r5, r9 80074fa: 4643 movge r3, r8 80074fc: e781 b.n 8007402 <_dtoa_r+0x70a> 80074fe: 9e08 ldr r6, [sp, #32] 8007500: 464d mov r5, r9 8007502: 9f09 ldr r7, [sp, #36] ; 0x24 8007504: e786 b.n 8007414 <_dtoa_r+0x71c> 8007506: 9a08 ldr r2, [sp, #32] 8007508: e7ad b.n 8007466 <_dtoa_r+0x76e> 800750a: 2300 movs r3, #0 800750c: e7d6 b.n 80074bc <_dtoa_r+0x7c4> 800750e: 9b02 ldr r3, [sp, #8] 8007510: e7d4 b.n 80074bc <_dtoa_r+0x7c4> 8007512: 2300 movs r3, #0 8007514: 9308 str r3, [sp, #32] 8007516: 6933 ldr r3, [r6, #16] 8007518: eb06 0383 add.w r3, r6, r3, lsl #2 800751c: 6918 ldr r0, [r3, #16] 800751e: f000 fc32 bl 8007d86 <__hi0bits> 8007522: f1c0 0020 rsb r0, r0, #32 8007526: 9b07 ldr r3, [sp, #28] 8007528: 4418 add r0, r3 800752a: f010 001f ands.w r0, r0, #31 800752e: d047 beq.n 80075c0 <_dtoa_r+0x8c8> 8007530: f1c0 0320 rsb r3, r0, #32 8007534: 2b04 cmp r3, #4 8007536: dd3b ble.n 80075b0 <_dtoa_r+0x8b8> 8007538: 9b07 ldr r3, [sp, #28] 800753a: f1c0 001c rsb r0, r0, #28 800753e: 4481 add r9, r0 8007540: 4405 add r5, r0 8007542: 4403 add r3, r0 8007544: 9307 str r3, [sp, #28] 8007546: f1b9 0f00 cmp.w r9, #0 800754a: dd05 ble.n 8007558 <_dtoa_r+0x860> 800754c: 4659 mov r1, fp 800754e: 464a mov r2, r9 8007550: 4620 mov r0, r4 8007552: f000 fd53 bl 8007ffc <__lshift> 8007556: 4683 mov fp, r0 8007558: 9b07 ldr r3, [sp, #28] 800755a: 2b00 cmp r3, #0 800755c: dd05 ble.n 800756a <_dtoa_r+0x872> 800755e: 4631 mov r1, r6 8007560: 461a mov r2, r3 8007562: 4620 mov r0, r4 8007564: f000 fd4a bl 8007ffc <__lshift> 8007568: 4606 mov r6, r0 800756a: 9b0d ldr r3, [sp, #52] ; 0x34 800756c: b353 cbz r3, 80075c4 <_dtoa_r+0x8cc> 800756e: 4631 mov r1, r6 8007570: 4658 mov r0, fp 8007572: f000 fd97 bl 80080a4 <__mcmp> 8007576: 2800 cmp r0, #0 8007578: da24 bge.n 80075c4 <_dtoa_r+0x8cc> 800757a: 2300 movs r3, #0 800757c: 4659 mov r1, fp 800757e: 220a movs r2, #10 8007580: 4620 mov r0, r4 8007582: f000 fbc5 bl 8007d10 <__multadd> 8007586: 9b09 ldr r3, [sp, #36] ; 0x24 8007588: f10a 3aff add.w sl, sl, #4294967295 800758c: 4683 mov fp, r0 800758e: 2b00 cmp r3, #0 8007590: f000 8144 beq.w 800781c <_dtoa_r+0xb24> 8007594: 2300 movs r3, #0 8007596: 4639 mov r1, r7 8007598: 220a movs r2, #10 800759a: 4620 mov r0, r4 800759c: f000 fbb8 bl 8007d10 <__multadd> 80075a0: 9b04 ldr r3, [sp, #16] 80075a2: 4607 mov r7, r0 80075a4: 2b00 cmp r3, #0 80075a6: dc4d bgt.n 8007644 <_dtoa_r+0x94c> 80075a8: 9b1e ldr r3, [sp, #120] ; 0x78 80075aa: 2b02 cmp r3, #2 80075ac: dd4a ble.n 8007644 <_dtoa_r+0x94c> 80075ae: e011 b.n 80075d4 <_dtoa_r+0x8dc> 80075b0: d0c9 beq.n 8007546 <_dtoa_r+0x84e> 80075b2: 9a07 ldr r2, [sp, #28] 80075b4: 331c adds r3, #28 80075b6: 441a add r2, r3 80075b8: 4499 add r9, r3 80075ba: 441d add r5, r3 80075bc: 4613 mov r3, r2 80075be: e7c1 b.n 8007544 <_dtoa_r+0x84c> 80075c0: 4603 mov r3, r0 80075c2: e7f6 b.n 80075b2 <_dtoa_r+0x8ba> 80075c4: f1b8 0f00 cmp.w r8, #0 80075c8: dc36 bgt.n 8007638 <_dtoa_r+0x940> 80075ca: 9b1e ldr r3, [sp, #120] ; 0x78 80075cc: 2b02 cmp r3, #2 80075ce: dd33 ble.n 8007638 <_dtoa_r+0x940> 80075d0: f8cd 8010 str.w r8, [sp, #16] 80075d4: 9b04 ldr r3, [sp, #16] 80075d6: b963 cbnz r3, 80075f2 <_dtoa_r+0x8fa> 80075d8: 4631 mov r1, r6 80075da: 2205 movs r2, #5 80075dc: 4620 mov r0, r4 80075de: f000 fb97 bl 8007d10 <__multadd> 80075e2: 4601 mov r1, r0 80075e4: 4606 mov r6, r0 80075e6: 4658 mov r0, fp 80075e8: f000 fd5c bl 80080a4 <__mcmp> 80075ec: 2800 cmp r0, #0 80075ee: f73f add3 bgt.w 8007198 <_dtoa_r+0x4a0> 80075f2: 9b1f ldr r3, [sp, #124] ; 0x7c 80075f4: 9d06 ldr r5, [sp, #24] 80075f6: ea6f 0a03 mvn.w sl, r3 80075fa: f04f 0900 mov.w r9, #0 80075fe: 4631 mov r1, r6 8007600: 4620 mov r0, r4 8007602: f000 fb6e bl 8007ce2 <_Bfree> 8007606: 2f00 cmp r7, #0 8007608: f43f aebd beq.w 8007386 <_dtoa_r+0x68e> 800760c: f1b9 0f00 cmp.w r9, #0 8007610: d005 beq.n 800761e <_dtoa_r+0x926> 8007612: 45b9 cmp r9, r7 8007614: d003 beq.n 800761e <_dtoa_r+0x926> 8007616: 4649 mov r1, r9 8007618: 4620 mov r0, r4 800761a: f000 fb62 bl 8007ce2 <_Bfree> 800761e: 4639 mov r1, r7 8007620: 4620 mov r0, r4 8007622: f000 fb5e bl 8007ce2 <_Bfree> 8007626: e6ae b.n 8007386 <_dtoa_r+0x68e> 8007628: 2600 movs r6, #0 800762a: 4637 mov r7, r6 800762c: e7e1 b.n 80075f2 <_dtoa_r+0x8fa> 800762e: 46ba mov sl, r7 8007630: 4637 mov r7, r6 8007632: e5b1 b.n 8007198 <_dtoa_r+0x4a0> 8007634: 40240000 .word 0x40240000 8007638: 9b09 ldr r3, [sp, #36] ; 0x24 800763a: f8cd 8010 str.w r8, [sp, #16] 800763e: 2b00 cmp r3, #0 8007640: f000 80f3 beq.w 800782a <_dtoa_r+0xb32> 8007644: 2d00 cmp r5, #0 8007646: dd05 ble.n 8007654 <_dtoa_r+0x95c> 8007648: 4639 mov r1, r7 800764a: 462a mov r2, r5 800764c: 4620 mov r0, r4 800764e: f000 fcd5 bl 8007ffc <__lshift> 8007652: 4607 mov r7, r0 8007654: 9b08 ldr r3, [sp, #32] 8007656: 2b00 cmp r3, #0 8007658: d04c beq.n 80076f4 <_dtoa_r+0x9fc> 800765a: 6879 ldr r1, [r7, #4] 800765c: 4620 mov r0, r4 800765e: f000 fb0c bl 8007c7a <_Balloc> 8007662: 4605 mov r5, r0 8007664: 693a ldr r2, [r7, #16] 8007666: f107 010c add.w r1, r7, #12 800766a: 3202 adds r2, #2 800766c: 0092 lsls r2, r2, #2 800766e: 300c adds r0, #12 8007670: f000 faf8 bl 8007c64 8007674: 2201 movs r2, #1 8007676: 4629 mov r1, r5 8007678: 4620 mov r0, r4 800767a: f000 fcbf bl 8007ffc <__lshift> 800767e: 46b9 mov r9, r7 8007680: 4607 mov r7, r0 8007682: 9b06 ldr r3, [sp, #24] 8007684: 9307 str r3, [sp, #28] 8007686: 9b02 ldr r3, [sp, #8] 8007688: f003 0301 and.w r3, r3, #1 800768c: 9308 str r3, [sp, #32] 800768e: 4631 mov r1, r6 8007690: 4658 mov r0, fp 8007692: f7ff faa1 bl 8006bd8 8007696: 4649 mov r1, r9 8007698: 4605 mov r5, r0 800769a: f100 0830 add.w r8, r0, #48 ; 0x30 800769e: 4658 mov r0, fp 80076a0: f000 fd00 bl 80080a4 <__mcmp> 80076a4: 463a mov r2, r7 80076a6: 9002 str r0, [sp, #8] 80076a8: 4631 mov r1, r6 80076aa: 4620 mov r0, r4 80076ac: f000 fd14 bl 80080d8 <__mdiff> 80076b0: 68c3 ldr r3, [r0, #12] 80076b2: 4602 mov r2, r0 80076b4: bb03 cbnz r3, 80076f8 <_dtoa_r+0xa00> 80076b6: 4601 mov r1, r0 80076b8: 9009 str r0, [sp, #36] ; 0x24 80076ba: 4658 mov r0, fp 80076bc: f000 fcf2 bl 80080a4 <__mcmp> 80076c0: 4603 mov r3, r0 80076c2: 9a09 ldr r2, [sp, #36] ; 0x24 80076c4: 4611 mov r1, r2 80076c6: 4620 mov r0, r4 80076c8: 9309 str r3, [sp, #36] ; 0x24 80076ca: f000 fb0a bl 8007ce2 <_Bfree> 80076ce: 9b09 ldr r3, [sp, #36] ; 0x24 80076d0: b9a3 cbnz r3, 80076fc <_dtoa_r+0xa04> 80076d2: 9a1e ldr r2, [sp, #120] ; 0x78 80076d4: b992 cbnz r2, 80076fc <_dtoa_r+0xa04> 80076d6: 9a08 ldr r2, [sp, #32] 80076d8: b982 cbnz r2, 80076fc <_dtoa_r+0xa04> 80076da: f1b8 0f39 cmp.w r8, #57 ; 0x39 80076de: d029 beq.n 8007734 <_dtoa_r+0xa3c> 80076e0: 9b02 ldr r3, [sp, #8] 80076e2: 2b00 cmp r3, #0 80076e4: dd01 ble.n 80076ea <_dtoa_r+0x9f2> 80076e6: f105 0831 add.w r8, r5, #49 ; 0x31 80076ea: 9b07 ldr r3, [sp, #28] 80076ec: 1c5d adds r5, r3, #1 80076ee: f883 8000 strb.w r8, [r3] 80076f2: e784 b.n 80075fe <_dtoa_r+0x906> 80076f4: 4638 mov r0, r7 80076f6: e7c2 b.n 800767e <_dtoa_r+0x986> 80076f8: 2301 movs r3, #1 80076fa: e7e3 b.n 80076c4 <_dtoa_r+0x9cc> 80076fc: 9a02 ldr r2, [sp, #8] 80076fe: 2a00 cmp r2, #0 8007700: db04 blt.n 800770c <_dtoa_r+0xa14> 8007702: d123 bne.n 800774c <_dtoa_r+0xa54> 8007704: 9a1e ldr r2, [sp, #120] ; 0x78 8007706: bb0a cbnz r2, 800774c <_dtoa_r+0xa54> 8007708: 9a08 ldr r2, [sp, #32] 800770a: b9fa cbnz r2, 800774c <_dtoa_r+0xa54> 800770c: 2b00 cmp r3, #0 800770e: ddec ble.n 80076ea <_dtoa_r+0x9f2> 8007710: 4659 mov r1, fp 8007712: 2201 movs r2, #1 8007714: 4620 mov r0, r4 8007716: f000 fc71 bl 8007ffc <__lshift> 800771a: 4631 mov r1, r6 800771c: 4683 mov fp, r0 800771e: f000 fcc1 bl 80080a4 <__mcmp> 8007722: 2800 cmp r0, #0 8007724: dc03 bgt.n 800772e <_dtoa_r+0xa36> 8007726: d1e0 bne.n 80076ea <_dtoa_r+0x9f2> 8007728: f018 0f01 tst.w r8, #1 800772c: d0dd beq.n 80076ea <_dtoa_r+0x9f2> 800772e: f1b8 0f39 cmp.w r8, #57 ; 0x39 8007732: d1d8 bne.n 80076e6 <_dtoa_r+0x9ee> 8007734: 9b07 ldr r3, [sp, #28] 8007736: 9a07 ldr r2, [sp, #28] 8007738: 1c5d adds r5, r3, #1 800773a: 2339 movs r3, #57 ; 0x39 800773c: 7013 strb r3, [r2, #0] 800773e: f815 3c01 ldrb.w r3, [r5, #-1] 8007742: 1e6a subs r2, r5, #1 8007744: 2b39 cmp r3, #57 ; 0x39 8007746: d04d beq.n 80077e4 <_dtoa_r+0xaec> 8007748: 3301 adds r3, #1 800774a: e052 b.n 80077f2 <_dtoa_r+0xafa> 800774c: 9a07 ldr r2, [sp, #28] 800774e: 2b00 cmp r3, #0 8007750: f102 0501 add.w r5, r2, #1 8007754: dd06 ble.n 8007764 <_dtoa_r+0xa6c> 8007756: f1b8 0f39 cmp.w r8, #57 ; 0x39 800775a: d0eb beq.n 8007734 <_dtoa_r+0xa3c> 800775c: f108 0801 add.w r8, r8, #1 8007760: 9b07 ldr r3, [sp, #28] 8007762: e7c4 b.n 80076ee <_dtoa_r+0x9f6> 8007764: 9b06 ldr r3, [sp, #24] 8007766: 9a04 ldr r2, [sp, #16] 8007768: 1aeb subs r3, r5, r3 800776a: 4293 cmp r3, r2 800776c: f805 8c01 strb.w r8, [r5, #-1] 8007770: d021 beq.n 80077b6 <_dtoa_r+0xabe> 8007772: 4659 mov r1, fp 8007774: 2300 movs r3, #0 8007776: 220a movs r2, #10 8007778: 4620 mov r0, r4 800777a: f000 fac9 bl 8007d10 <__multadd> 800777e: 45b9 cmp r9, r7 8007780: 4683 mov fp, r0 8007782: f04f 0300 mov.w r3, #0 8007786: f04f 020a mov.w r2, #10 800778a: 4649 mov r1, r9 800778c: 4620 mov r0, r4 800778e: d105 bne.n 800779c <_dtoa_r+0xaa4> 8007790: f000 fabe bl 8007d10 <__multadd> 8007794: 4681 mov r9, r0 8007796: 4607 mov r7, r0 8007798: 9507 str r5, [sp, #28] 800779a: e778 b.n 800768e <_dtoa_r+0x996> 800779c: f000 fab8 bl 8007d10 <__multadd> 80077a0: 4639 mov r1, r7 80077a2: 4681 mov r9, r0 80077a4: 2300 movs r3, #0 80077a6: 220a movs r2, #10 80077a8: 4620 mov r0, r4 80077aa: f000 fab1 bl 8007d10 <__multadd> 80077ae: 4607 mov r7, r0 80077b0: e7f2 b.n 8007798 <_dtoa_r+0xaa0> 80077b2: f04f 0900 mov.w r9, #0 80077b6: 4659 mov r1, fp 80077b8: 2201 movs r2, #1 80077ba: 4620 mov r0, r4 80077bc: f000 fc1e bl 8007ffc <__lshift> 80077c0: 4631 mov r1, r6 80077c2: 4683 mov fp, r0 80077c4: f000 fc6e bl 80080a4 <__mcmp> 80077c8: 2800 cmp r0, #0 80077ca: dcb8 bgt.n 800773e <_dtoa_r+0xa46> 80077cc: d102 bne.n 80077d4 <_dtoa_r+0xadc> 80077ce: f018 0f01 tst.w r8, #1 80077d2: d1b4 bne.n 800773e <_dtoa_r+0xa46> 80077d4: f815 3c01 ldrb.w r3, [r5, #-1] 80077d8: 1e6a subs r2, r5, #1 80077da: 2b30 cmp r3, #48 ; 0x30 80077dc: f47f af0f bne.w 80075fe <_dtoa_r+0x906> 80077e0: 4615 mov r5, r2 80077e2: e7f7 b.n 80077d4 <_dtoa_r+0xadc> 80077e4: 9b06 ldr r3, [sp, #24] 80077e6: 4293 cmp r3, r2 80077e8: d105 bne.n 80077f6 <_dtoa_r+0xafe> 80077ea: 2331 movs r3, #49 ; 0x31 80077ec: 9a06 ldr r2, [sp, #24] 80077ee: f10a 0a01 add.w sl, sl, #1 80077f2: 7013 strb r3, [r2, #0] 80077f4: e703 b.n 80075fe <_dtoa_r+0x906> 80077f6: 4615 mov r5, r2 80077f8: e7a1 b.n 800773e <_dtoa_r+0xa46> 80077fa: 4b17 ldr r3, [pc, #92] ; (8007858 <_dtoa_r+0xb60>) 80077fc: f7ff bae1 b.w 8006dc2 <_dtoa_r+0xca> 8007800: 9b22 ldr r3, [sp, #136] ; 0x88 8007802: 2b00 cmp r3, #0 8007804: f47f aabb bne.w 8006d7e <_dtoa_r+0x86> 8007808: 4b14 ldr r3, [pc, #80] ; (800785c <_dtoa_r+0xb64>) 800780a: f7ff bada b.w 8006dc2 <_dtoa_r+0xca> 800780e: 9b1e ldr r3, [sp, #120] ; 0x78 8007810: 2b01 cmp r3, #1 8007812: f77f ae3f ble.w 8007494 <_dtoa_r+0x79c> 8007816: 9b0c ldr r3, [sp, #48] ; 0x30 8007818: 9308 str r3, [sp, #32] 800781a: e653 b.n 80074c4 <_dtoa_r+0x7cc> 800781c: 9b04 ldr r3, [sp, #16] 800781e: 2b00 cmp r3, #0 8007820: dc03 bgt.n 800782a <_dtoa_r+0xb32> 8007822: 9b1e ldr r3, [sp, #120] ; 0x78 8007824: 2b02 cmp r3, #2 8007826: f73f aed5 bgt.w 80075d4 <_dtoa_r+0x8dc> 800782a: 9d06 ldr r5, [sp, #24] 800782c: 4631 mov r1, r6 800782e: 4658 mov r0, fp 8007830: f7ff f9d2 bl 8006bd8 8007834: 9b06 ldr r3, [sp, #24] 8007836: f100 0830 add.w r8, r0, #48 ; 0x30 800783a: f805 8b01 strb.w r8, [r5], #1 800783e: 9a04 ldr r2, [sp, #16] 8007840: 1aeb subs r3, r5, r3 8007842: 429a cmp r2, r3 8007844: ddb5 ble.n 80077b2 <_dtoa_r+0xaba> 8007846: 4659 mov r1, fp 8007848: 2300 movs r3, #0 800784a: 220a movs r2, #10 800784c: 4620 mov r0, r4 800784e: f000 fa5f bl 8007d10 <__multadd> 8007852: 4683 mov fp, r0 8007854: e7ea b.n 800782c <_dtoa_r+0xb34> 8007856: bf00 nop 8007858: 08008bc4 .word 0x08008bc4 800785c: 08008be8 .word 0x08008be8 08007860 <__sflush_r>: 8007860: 898a ldrh r2, [r1, #12] 8007862: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 8007866: 4605 mov r5, r0 8007868: 0710 lsls r0, r2, #28 800786a: 460c mov r4, r1 800786c: d458 bmi.n 8007920 <__sflush_r+0xc0> 800786e: 684b ldr r3, [r1, #4] 8007870: 2b00 cmp r3, #0 8007872: dc05 bgt.n 8007880 <__sflush_r+0x20> 8007874: 6c0b ldr r3, [r1, #64] ; 0x40 8007876: 2b00 cmp r3, #0 8007878: dc02 bgt.n 8007880 <__sflush_r+0x20> 800787a: 2000 movs r0, #0 800787c: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8007880: 6ae6 ldr r6, [r4, #44] ; 0x2c 8007882: 2e00 cmp r6, #0 8007884: d0f9 beq.n 800787a <__sflush_r+0x1a> 8007886: 2300 movs r3, #0 8007888: f412 5280 ands.w r2, r2, #4096 ; 0x1000 800788c: 682f ldr r7, [r5, #0] 800788e: 6a21 ldr r1, [r4, #32] 8007890: 602b str r3, [r5, #0] 8007892: d032 beq.n 80078fa <__sflush_r+0x9a> 8007894: 6d60 ldr r0, [r4, #84] ; 0x54 8007896: 89a3 ldrh r3, [r4, #12] 8007898: 075a lsls r2, r3, #29 800789a: d505 bpl.n 80078a8 <__sflush_r+0x48> 800789c: 6863 ldr r3, [r4, #4] 800789e: 1ac0 subs r0, r0, r3 80078a0: 6b63 ldr r3, [r4, #52] ; 0x34 80078a2: b10b cbz r3, 80078a8 <__sflush_r+0x48> 80078a4: 6c23 ldr r3, [r4, #64] ; 0x40 80078a6: 1ac0 subs r0, r0, r3 80078a8: 2300 movs r3, #0 80078aa: 4602 mov r2, r0 80078ac: 6ae6 ldr r6, [r4, #44] ; 0x2c 80078ae: 6a21 ldr r1, [r4, #32] 80078b0: 4628 mov r0, r5 80078b2: 47b0 blx r6 80078b4: 1c43 adds r3, r0, #1 80078b6: 89a3 ldrh r3, [r4, #12] 80078b8: d106 bne.n 80078c8 <__sflush_r+0x68> 80078ba: 6829 ldr r1, [r5, #0] 80078bc: 291d cmp r1, #29 80078be: d848 bhi.n 8007952 <__sflush_r+0xf2> 80078c0: 4a29 ldr r2, [pc, #164] ; (8007968 <__sflush_r+0x108>) 80078c2: 40ca lsrs r2, r1 80078c4: 07d6 lsls r6, r2, #31 80078c6: d544 bpl.n 8007952 <__sflush_r+0xf2> 80078c8: 2200 movs r2, #0 80078ca: 6062 str r2, [r4, #4] 80078cc: 6922 ldr r2, [r4, #16] 80078ce: 04d9 lsls r1, r3, #19 80078d0: 6022 str r2, [r4, #0] 80078d2: d504 bpl.n 80078de <__sflush_r+0x7e> 80078d4: 1c42 adds r2, r0, #1 80078d6: d101 bne.n 80078dc <__sflush_r+0x7c> 80078d8: 682b ldr r3, [r5, #0] 80078da: b903 cbnz r3, 80078de <__sflush_r+0x7e> 80078dc: 6560 str r0, [r4, #84] ; 0x54 80078de: 6b61 ldr r1, [r4, #52] ; 0x34 80078e0: 602f str r7, [r5, #0] 80078e2: 2900 cmp r1, #0 80078e4: d0c9 beq.n 800787a <__sflush_r+0x1a> 80078e6: f104 0344 add.w r3, r4, #68 ; 0x44 80078ea: 4299 cmp r1, r3 80078ec: d002 beq.n 80078f4 <__sflush_r+0x94> 80078ee: 4628 mov r0, r5 80078f0: f000 fcae bl 8008250 <_free_r> 80078f4: 2000 movs r0, #0 80078f6: 6360 str r0, [r4, #52] ; 0x34 80078f8: e7c0 b.n 800787c <__sflush_r+0x1c> 80078fa: 2301 movs r3, #1 80078fc: 4628 mov r0, r5 80078fe: 47b0 blx r6 8007900: 1c41 adds r1, r0, #1 8007902: d1c8 bne.n 8007896 <__sflush_r+0x36> 8007904: 682b ldr r3, [r5, #0] 8007906: 2b00 cmp r3, #0 8007908: d0c5 beq.n 8007896 <__sflush_r+0x36> 800790a: 2b1d cmp r3, #29 800790c: d001 beq.n 8007912 <__sflush_r+0xb2> 800790e: 2b16 cmp r3, #22 8007910: d101 bne.n 8007916 <__sflush_r+0xb6> 8007912: 602f str r7, [r5, #0] 8007914: e7b1 b.n 800787a <__sflush_r+0x1a> 8007916: 89a3 ldrh r3, [r4, #12] 8007918: f043 0340 orr.w r3, r3, #64 ; 0x40 800791c: 81a3 strh r3, [r4, #12] 800791e: e7ad b.n 800787c <__sflush_r+0x1c> 8007920: 690f ldr r7, [r1, #16] 8007922: 2f00 cmp r7, #0 8007924: d0a9 beq.n 800787a <__sflush_r+0x1a> 8007926: 0793 lsls r3, r2, #30 8007928: bf18 it ne 800792a: 2300 movne r3, #0 800792c: 680e ldr r6, [r1, #0] 800792e: bf08 it eq 8007930: 694b ldreq r3, [r1, #20] 8007932: eba6 0807 sub.w r8, r6, r7 8007936: 600f str r7, [r1, #0] 8007938: 608b str r3, [r1, #8] 800793a: f1b8 0f00 cmp.w r8, #0 800793e: dd9c ble.n 800787a <__sflush_r+0x1a> 8007940: 4643 mov r3, r8 8007942: 463a mov r2, r7 8007944: 6a21 ldr r1, [r4, #32] 8007946: 4628 mov r0, r5 8007948: 6aa6 ldr r6, [r4, #40] ; 0x28 800794a: 47b0 blx r6 800794c: 2800 cmp r0, #0 800794e: dc06 bgt.n 800795e <__sflush_r+0xfe> 8007950: 89a3 ldrh r3, [r4, #12] 8007952: f043 0340 orr.w r3, r3, #64 ; 0x40 8007956: 81a3 strh r3, [r4, #12] 8007958: f04f 30ff mov.w r0, #4294967295 800795c: e78e b.n 800787c <__sflush_r+0x1c> 800795e: 4407 add r7, r0 8007960: eba8 0800 sub.w r8, r8, r0 8007964: e7e9 b.n 800793a <__sflush_r+0xda> 8007966: bf00 nop 8007968: 20400001 .word 0x20400001 0800796c <_fflush_r>: 800796c: b538 push {r3, r4, r5, lr} 800796e: 690b ldr r3, [r1, #16] 8007970: 4605 mov r5, r0 8007972: 460c mov r4, r1 8007974: b1db cbz r3, 80079ae <_fflush_r+0x42> 8007976: b118 cbz r0, 8007980 <_fflush_r+0x14> 8007978: 6983 ldr r3, [r0, #24] 800797a: b90b cbnz r3, 8007980 <_fflush_r+0x14> 800797c: f000 f860 bl 8007a40 <__sinit> 8007980: 4b0c ldr r3, [pc, #48] ; (80079b4 <_fflush_r+0x48>) 8007982: 429c cmp r4, r3 8007984: d109 bne.n 800799a <_fflush_r+0x2e> 8007986: 686c ldr r4, [r5, #4] 8007988: f9b4 300c ldrsh.w r3, [r4, #12] 800798c: b17b cbz r3, 80079ae <_fflush_r+0x42> 800798e: 4621 mov r1, r4 8007990: 4628 mov r0, r5 8007992: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 8007996: f7ff bf63 b.w 8007860 <__sflush_r> 800799a: 4b07 ldr r3, [pc, #28] ; (80079b8 <_fflush_r+0x4c>) 800799c: 429c cmp r4, r3 800799e: d101 bne.n 80079a4 <_fflush_r+0x38> 80079a0: 68ac ldr r4, [r5, #8] 80079a2: e7f1 b.n 8007988 <_fflush_r+0x1c> 80079a4: 4b05 ldr r3, [pc, #20] ; (80079bc <_fflush_r+0x50>) 80079a6: 429c cmp r4, r3 80079a8: bf08 it eq 80079aa: 68ec ldreq r4, [r5, #12] 80079ac: e7ec b.n 8007988 <_fflush_r+0x1c> 80079ae: 2000 movs r0, #0 80079b0: bd38 pop {r3, r4, r5, pc} 80079b2: bf00 nop 80079b4: 08008c18 .word 0x08008c18 80079b8: 08008c38 .word 0x08008c38 80079bc: 08008bf8 .word 0x08008bf8 080079c0 : 80079c0: 2300 movs r3, #0 80079c2: b510 push {r4, lr} 80079c4: 4604 mov r4, r0 80079c6: e9c0 3300 strd r3, r3, [r0] 80079ca: 6083 str r3, [r0, #8] 80079cc: 8181 strh r1, [r0, #12] 80079ce: 6643 str r3, [r0, #100] ; 0x64 80079d0: 81c2 strh r2, [r0, #14] 80079d2: e9c0 3304 strd r3, r3, [r0, #16] 80079d6: 6183 str r3, [r0, #24] 80079d8: 4619 mov r1, r3 80079da: 2208 movs r2, #8 80079dc: 305c adds r0, #92 ; 0x5c 80079de: f7fe fab1 bl 8005f44 80079e2: 4b05 ldr r3, [pc, #20] ; (80079f8 ) 80079e4: 6224 str r4, [r4, #32] 80079e6: 6263 str r3, [r4, #36] ; 0x24 80079e8: 4b04 ldr r3, [pc, #16] ; (80079fc ) 80079ea: 62a3 str r3, [r4, #40] ; 0x28 80079ec: 4b04 ldr r3, [pc, #16] ; (8007a00 ) 80079ee: 62e3 str r3, [r4, #44] ; 0x2c 80079f0: 4b04 ldr r3, [pc, #16] ; (8007a04 ) 80079f2: 6323 str r3, [r4, #48] ; 0x30 80079f4: bd10 pop {r4, pc} 80079f6: bf00 nop 80079f8: 08008639 .word 0x08008639 80079fc: 0800865b .word 0x0800865b 8007a00: 08008693 .word 0x08008693 8007a04: 080086b7 .word 0x080086b7 08007a08 <_cleanup_r>: 8007a08: 4901 ldr r1, [pc, #4] ; (8007a10 <_cleanup_r+0x8>) 8007a0a: f000 b885 b.w 8007b18 <_fwalk_reent> 8007a0e: bf00 nop 8007a10: 0800796d .word 0x0800796d 08007a14 <__sfmoreglue>: 8007a14: b570 push {r4, r5, r6, lr} 8007a16: 2568 movs r5, #104 ; 0x68 8007a18: 1e4a subs r2, r1, #1 8007a1a: 4355 muls r5, r2 8007a1c: 460e mov r6, r1 8007a1e: f105 0174 add.w r1, r5, #116 ; 0x74 8007a22: f000 fc61 bl 80082e8 <_malloc_r> 8007a26: 4604 mov r4, r0 8007a28: b140 cbz r0, 8007a3c <__sfmoreglue+0x28> 8007a2a: 2100 movs r1, #0 8007a2c: e9c0 1600 strd r1, r6, [r0] 8007a30: 300c adds r0, #12 8007a32: 60a0 str r0, [r4, #8] 8007a34: f105 0268 add.w r2, r5, #104 ; 0x68 8007a38: f7fe fa84 bl 8005f44 8007a3c: 4620 mov r0, r4 8007a3e: bd70 pop {r4, r5, r6, pc} 08007a40 <__sinit>: 8007a40: 6983 ldr r3, [r0, #24] 8007a42: b510 push {r4, lr} 8007a44: 4604 mov r4, r0 8007a46: bb33 cbnz r3, 8007a96 <__sinit+0x56> 8007a48: e9c0 3312 strd r3, r3, [r0, #72] ; 0x48 8007a4c: 6503 str r3, [r0, #80] ; 0x50 8007a4e: 4b12 ldr r3, [pc, #72] ; (8007a98 <__sinit+0x58>) 8007a50: 4a12 ldr r2, [pc, #72] ; (8007a9c <__sinit+0x5c>) 8007a52: 681b ldr r3, [r3, #0] 8007a54: 6282 str r2, [r0, #40] ; 0x28 8007a56: 4298 cmp r0, r3 8007a58: bf04 itt eq 8007a5a: 2301 moveq r3, #1 8007a5c: 6183 streq r3, [r0, #24] 8007a5e: f000 f81f bl 8007aa0 <__sfp> 8007a62: 6060 str r0, [r4, #4] 8007a64: 4620 mov r0, r4 8007a66: f000 f81b bl 8007aa0 <__sfp> 8007a6a: 60a0 str r0, [r4, #8] 8007a6c: 4620 mov r0, r4 8007a6e: f000 f817 bl 8007aa0 <__sfp> 8007a72: 2200 movs r2, #0 8007a74: 60e0 str r0, [r4, #12] 8007a76: 2104 movs r1, #4 8007a78: 6860 ldr r0, [r4, #4] 8007a7a: f7ff ffa1 bl 80079c0 8007a7e: 2201 movs r2, #1 8007a80: 2109 movs r1, #9 8007a82: 68a0 ldr r0, [r4, #8] 8007a84: f7ff ff9c bl 80079c0 8007a88: 2202 movs r2, #2 8007a8a: 2112 movs r1, #18 8007a8c: 68e0 ldr r0, [r4, #12] 8007a8e: f7ff ff97 bl 80079c0 8007a92: 2301 movs r3, #1 8007a94: 61a3 str r3, [r4, #24] 8007a96: bd10 pop {r4, pc} 8007a98: 08008bb0 .word 0x08008bb0 8007a9c: 08007a09 .word 0x08007a09 08007aa0 <__sfp>: 8007aa0: b5f8 push {r3, r4, r5, r6, r7, lr} 8007aa2: 4b1b ldr r3, [pc, #108] ; (8007b10 <__sfp+0x70>) 8007aa4: 4607 mov r7, r0 8007aa6: 681e ldr r6, [r3, #0] 8007aa8: 69b3 ldr r3, [r6, #24] 8007aaa: b913 cbnz r3, 8007ab2 <__sfp+0x12> 8007aac: 4630 mov r0, r6 8007aae: f7ff ffc7 bl 8007a40 <__sinit> 8007ab2: 3648 adds r6, #72 ; 0x48 8007ab4: e9d6 3401 ldrd r3, r4, [r6, #4] 8007ab8: 3b01 subs r3, #1 8007aba: d503 bpl.n 8007ac4 <__sfp+0x24> 8007abc: 6833 ldr r3, [r6, #0] 8007abe: b133 cbz r3, 8007ace <__sfp+0x2e> 8007ac0: 6836 ldr r6, [r6, #0] 8007ac2: e7f7 b.n 8007ab4 <__sfp+0x14> 8007ac4: f9b4 500c ldrsh.w r5, [r4, #12] 8007ac8: b16d cbz r5, 8007ae6 <__sfp+0x46> 8007aca: 3468 adds r4, #104 ; 0x68 8007acc: e7f4 b.n 8007ab8 <__sfp+0x18> 8007ace: 2104 movs r1, #4 8007ad0: 4638 mov r0, r7 8007ad2: f7ff ff9f bl 8007a14 <__sfmoreglue> 8007ad6: 6030 str r0, [r6, #0] 8007ad8: 2800 cmp r0, #0 8007ada: d1f1 bne.n 8007ac0 <__sfp+0x20> 8007adc: 230c movs r3, #12 8007ade: 4604 mov r4, r0 8007ae0: 603b str r3, [r7, #0] 8007ae2: 4620 mov r0, r4 8007ae4: bdf8 pop {r3, r4, r5, r6, r7, pc} 8007ae6: 4b0b ldr r3, [pc, #44] ; (8007b14 <__sfp+0x74>) 8007ae8: 6665 str r5, [r4, #100] ; 0x64 8007aea: e9c4 5500 strd r5, r5, [r4] 8007aee: 60a5 str r5, [r4, #8] 8007af0: e9c4 3503 strd r3, r5, [r4, #12] 8007af4: e9c4 5505 strd r5, r5, [r4, #20] 8007af8: 2208 movs r2, #8 8007afa: 4629 mov r1, r5 8007afc: f104 005c add.w r0, r4, #92 ; 0x5c 8007b00: f7fe fa20 bl 8005f44 8007b04: e9c4 550d strd r5, r5, [r4, #52] ; 0x34 8007b08: e9c4 5512 strd r5, r5, [r4, #72] ; 0x48 8007b0c: e7e9 b.n 8007ae2 <__sfp+0x42> 8007b0e: bf00 nop 8007b10: 08008bb0 .word 0x08008bb0 8007b14: ffff0001 .word 0xffff0001 08007b18 <_fwalk_reent>: 8007b18: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 8007b1c: 4680 mov r8, r0 8007b1e: 4689 mov r9, r1 8007b20: 2600 movs r6, #0 8007b22: f100 0448 add.w r4, r0, #72 ; 0x48 8007b26: b914 cbnz r4, 8007b2e <_fwalk_reent+0x16> 8007b28: 4630 mov r0, r6 8007b2a: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 8007b2e: e9d4 7501 ldrd r7, r5, [r4, #4] 8007b32: 3f01 subs r7, #1 8007b34: d501 bpl.n 8007b3a <_fwalk_reent+0x22> 8007b36: 6824 ldr r4, [r4, #0] 8007b38: e7f5 b.n 8007b26 <_fwalk_reent+0xe> 8007b3a: 89ab ldrh r3, [r5, #12] 8007b3c: 2b01 cmp r3, #1 8007b3e: d907 bls.n 8007b50 <_fwalk_reent+0x38> 8007b40: f9b5 300e ldrsh.w r3, [r5, #14] 8007b44: 3301 adds r3, #1 8007b46: d003 beq.n 8007b50 <_fwalk_reent+0x38> 8007b48: 4629 mov r1, r5 8007b4a: 4640 mov r0, r8 8007b4c: 47c8 blx r9 8007b4e: 4306 orrs r6, r0 8007b50: 3568 adds r5, #104 ; 0x68 8007b52: e7ee b.n 8007b32 <_fwalk_reent+0x1a> 08007b54 <_localeconv_r>: 8007b54: 4b04 ldr r3, [pc, #16] ; (8007b68 <_localeconv_r+0x14>) 8007b56: 681b ldr r3, [r3, #0] 8007b58: 6a18 ldr r0, [r3, #32] 8007b5a: 4b04 ldr r3, [pc, #16] ; (8007b6c <_localeconv_r+0x18>) 8007b5c: 2800 cmp r0, #0 8007b5e: bf08 it eq 8007b60: 4618 moveq r0, r3 8007b62: 30f0 adds r0, #240 ; 0xf0 8007b64: 4770 bx lr 8007b66: bf00 nop 8007b68: 2000000c .word 0x2000000c 8007b6c: 20000070 .word 0x20000070 08007b70 <__swhatbuf_r>: 8007b70: b570 push {r4, r5, r6, lr} 8007b72: 460e mov r6, r1 8007b74: f9b1 100e ldrsh.w r1, [r1, #14] 8007b78: b096 sub sp, #88 ; 0x58 8007b7a: 2900 cmp r1, #0 8007b7c: 4614 mov r4, r2 8007b7e: 461d mov r5, r3 8007b80: da07 bge.n 8007b92 <__swhatbuf_r+0x22> 8007b82: 2300 movs r3, #0 8007b84: 602b str r3, [r5, #0] 8007b86: 89b3 ldrh r3, [r6, #12] 8007b88: 061a lsls r2, r3, #24 8007b8a: d410 bmi.n 8007bae <__swhatbuf_r+0x3e> 8007b8c: f44f 6380 mov.w r3, #1024 ; 0x400 8007b90: e00e b.n 8007bb0 <__swhatbuf_r+0x40> 8007b92: 466a mov r2, sp 8007b94: f000 fdb6 bl 8008704 <_fstat_r> 8007b98: 2800 cmp r0, #0 8007b9a: dbf2 blt.n 8007b82 <__swhatbuf_r+0x12> 8007b9c: 9a01 ldr r2, [sp, #4] 8007b9e: f402 4270 and.w r2, r2, #61440 ; 0xf000 8007ba2: f5a2 5300 sub.w r3, r2, #8192 ; 0x2000 8007ba6: 425a negs r2, r3 8007ba8: 415a adcs r2, r3 8007baa: 602a str r2, [r5, #0] 8007bac: e7ee b.n 8007b8c <__swhatbuf_r+0x1c> 8007bae: 2340 movs r3, #64 ; 0x40 8007bb0: 2000 movs r0, #0 8007bb2: 6023 str r3, [r4, #0] 8007bb4: b016 add sp, #88 ; 0x58 8007bb6: bd70 pop {r4, r5, r6, pc} 08007bb8 <__smakebuf_r>: 8007bb8: 898b ldrh r3, [r1, #12] 8007bba: b573 push {r0, r1, r4, r5, r6, lr} 8007bbc: 079d lsls r5, r3, #30 8007bbe: 4606 mov r6, r0 8007bc0: 460c mov r4, r1 8007bc2: d507 bpl.n 8007bd4 <__smakebuf_r+0x1c> 8007bc4: f104 0347 add.w r3, r4, #71 ; 0x47 8007bc8: 6023 str r3, [r4, #0] 8007bca: 6123 str r3, [r4, #16] 8007bcc: 2301 movs r3, #1 8007bce: 6163 str r3, [r4, #20] 8007bd0: b002 add sp, #8 8007bd2: bd70 pop {r4, r5, r6, pc} 8007bd4: ab01 add r3, sp, #4 8007bd6: 466a mov r2, sp 8007bd8: f7ff ffca bl 8007b70 <__swhatbuf_r> 8007bdc: 9900 ldr r1, [sp, #0] 8007bde: 4605 mov r5, r0 8007be0: 4630 mov r0, r6 8007be2: f000 fb81 bl 80082e8 <_malloc_r> 8007be6: b948 cbnz r0, 8007bfc <__smakebuf_r+0x44> 8007be8: f9b4 300c ldrsh.w r3, [r4, #12] 8007bec: 059a lsls r2, r3, #22 8007bee: d4ef bmi.n 8007bd0 <__smakebuf_r+0x18> 8007bf0: f023 0303 bic.w r3, r3, #3 8007bf4: f043 0302 orr.w r3, r3, #2 8007bf8: 81a3 strh r3, [r4, #12] 8007bfa: e7e3 b.n 8007bc4 <__smakebuf_r+0xc> 8007bfc: 4b0d ldr r3, [pc, #52] ; (8007c34 <__smakebuf_r+0x7c>) 8007bfe: 62b3 str r3, [r6, #40] ; 0x28 8007c00: 89a3 ldrh r3, [r4, #12] 8007c02: 6020 str r0, [r4, #0] 8007c04: f043 0380 orr.w r3, r3, #128 ; 0x80 8007c08: 81a3 strh r3, [r4, #12] 8007c0a: 9b00 ldr r3, [sp, #0] 8007c0c: 6120 str r0, [r4, #16] 8007c0e: 6163 str r3, [r4, #20] 8007c10: 9b01 ldr r3, [sp, #4] 8007c12: b15b cbz r3, 8007c2c <__smakebuf_r+0x74> 8007c14: f9b4 100e ldrsh.w r1, [r4, #14] 8007c18: 4630 mov r0, r6 8007c1a: f000 fd85 bl 8008728 <_isatty_r> 8007c1e: b128 cbz r0, 8007c2c <__smakebuf_r+0x74> 8007c20: 89a3 ldrh r3, [r4, #12] 8007c22: f023 0303 bic.w r3, r3, #3 8007c26: f043 0301 orr.w r3, r3, #1 8007c2a: 81a3 strh r3, [r4, #12] 8007c2c: 89a3 ldrh r3, [r4, #12] 8007c2e: 431d orrs r5, r3 8007c30: 81a5 strh r5, [r4, #12] 8007c32: e7cd b.n 8007bd0 <__smakebuf_r+0x18> 8007c34: 08007a09 .word 0x08007a09 08007c38 : 8007c38: 4b02 ldr r3, [pc, #8] ; (8007c44 ) 8007c3a: 4601 mov r1, r0 8007c3c: 6818 ldr r0, [r3, #0] 8007c3e: f000 bb53 b.w 80082e8 <_malloc_r> 8007c42: bf00 nop 8007c44: 2000000c .word 0x2000000c 08007c48 : 8007c48: b510 push {r4, lr} 8007c4a: b2c9 uxtb r1, r1 8007c4c: 4402 add r2, r0 8007c4e: 4290 cmp r0, r2 8007c50: 4603 mov r3, r0 8007c52: d101 bne.n 8007c58 8007c54: 2300 movs r3, #0 8007c56: e003 b.n 8007c60 8007c58: 781c ldrb r4, [r3, #0] 8007c5a: 3001 adds r0, #1 8007c5c: 428c cmp r4, r1 8007c5e: d1f6 bne.n 8007c4e 8007c60: 4618 mov r0, r3 8007c62: bd10 pop {r4, pc} 08007c64 : 8007c64: b510 push {r4, lr} 8007c66: 1e43 subs r3, r0, #1 8007c68: 440a add r2, r1 8007c6a: 4291 cmp r1, r2 8007c6c: d100 bne.n 8007c70 8007c6e: bd10 pop {r4, pc} 8007c70: f811 4b01 ldrb.w r4, [r1], #1 8007c74: f803 4f01 strb.w r4, [r3, #1]! 8007c78: e7f7 b.n 8007c6a 08007c7a <_Balloc>: 8007c7a: b570 push {r4, r5, r6, lr} 8007c7c: 6a45 ldr r5, [r0, #36] ; 0x24 8007c7e: 4604 mov r4, r0 8007c80: 460e mov r6, r1 8007c82: b93d cbnz r5, 8007c94 <_Balloc+0x1a> 8007c84: 2010 movs r0, #16 8007c86: f7ff ffd7 bl 8007c38 8007c8a: 6260 str r0, [r4, #36] ; 0x24 8007c8c: e9c0 5501 strd r5, r5, [r0, #4] 8007c90: 6005 str r5, [r0, #0] 8007c92: 60c5 str r5, [r0, #12] 8007c94: 6a65 ldr r5, [r4, #36] ; 0x24 8007c96: 68eb ldr r3, [r5, #12] 8007c98: b183 cbz r3, 8007cbc <_Balloc+0x42> 8007c9a: 6a63 ldr r3, [r4, #36] ; 0x24 8007c9c: 68db ldr r3, [r3, #12] 8007c9e: f853 0026 ldr.w r0, [r3, r6, lsl #2] 8007ca2: b9b8 cbnz r0, 8007cd4 <_Balloc+0x5a> 8007ca4: 2101 movs r1, #1 8007ca6: fa01 f506 lsl.w r5, r1, r6 8007caa: 1d6a adds r2, r5, #5 8007cac: 0092 lsls r2, r2, #2 8007cae: 4620 mov r0, r4 8007cb0: f000 fabf bl 8008232 <_calloc_r> 8007cb4: b160 cbz r0, 8007cd0 <_Balloc+0x56> 8007cb6: e9c0 6501 strd r6, r5, [r0, #4] 8007cba: e00e b.n 8007cda <_Balloc+0x60> 8007cbc: 2221 movs r2, #33 ; 0x21 8007cbe: 2104 movs r1, #4 8007cc0: 4620 mov r0, r4 8007cc2: f000 fab6 bl 8008232 <_calloc_r> 8007cc6: 6a63 ldr r3, [r4, #36] ; 0x24 8007cc8: 60e8 str r0, [r5, #12] 8007cca: 68db ldr r3, [r3, #12] 8007ccc: 2b00 cmp r3, #0 8007cce: d1e4 bne.n 8007c9a <_Balloc+0x20> 8007cd0: 2000 movs r0, #0 8007cd2: bd70 pop {r4, r5, r6, pc} 8007cd4: 6802 ldr r2, [r0, #0] 8007cd6: f843 2026 str.w r2, [r3, r6, lsl #2] 8007cda: 2300 movs r3, #0 8007cdc: e9c0 3303 strd r3, r3, [r0, #12] 8007ce0: e7f7 b.n 8007cd2 <_Balloc+0x58> 08007ce2 <_Bfree>: 8007ce2: b570 push {r4, r5, r6, lr} 8007ce4: 6a44 ldr r4, [r0, #36] ; 0x24 8007ce6: 4606 mov r6, r0 8007ce8: 460d mov r5, r1 8007cea: b93c cbnz r4, 8007cfc <_Bfree+0x1a> 8007cec: 2010 movs r0, #16 8007cee: f7ff ffa3 bl 8007c38 8007cf2: 6270 str r0, [r6, #36] ; 0x24 8007cf4: e9c0 4401 strd r4, r4, [r0, #4] 8007cf8: 6004 str r4, [r0, #0] 8007cfa: 60c4 str r4, [r0, #12] 8007cfc: b13d cbz r5, 8007d0e <_Bfree+0x2c> 8007cfe: 6a73 ldr r3, [r6, #36] ; 0x24 8007d00: 686a ldr r2, [r5, #4] 8007d02: 68db ldr r3, [r3, #12] 8007d04: f853 1022 ldr.w r1, [r3, r2, lsl #2] 8007d08: 6029 str r1, [r5, #0] 8007d0a: f843 5022 str.w r5, [r3, r2, lsl #2] 8007d0e: bd70 pop {r4, r5, r6, pc} 08007d10 <__multadd>: 8007d10: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 8007d14: 461f mov r7, r3 8007d16: 4606 mov r6, r0 8007d18: 460c mov r4, r1 8007d1a: 2300 movs r3, #0 8007d1c: 690d ldr r5, [r1, #16] 8007d1e: f101 0c14 add.w ip, r1, #20 8007d22: f8dc 0000 ldr.w r0, [ip] 8007d26: 3301 adds r3, #1 8007d28: b281 uxth r1, r0 8007d2a: fb02 7101 mla r1, r2, r1, r7 8007d2e: 0c00 lsrs r0, r0, #16 8007d30: 0c0f lsrs r7, r1, #16 8007d32: fb02 7000 mla r0, r2, r0, r7 8007d36: b289 uxth r1, r1 8007d38: eb01 4100 add.w r1, r1, r0, lsl #16 8007d3c: 429d cmp r5, r3 8007d3e: ea4f 4710 mov.w r7, r0, lsr #16 8007d42: f84c 1b04 str.w r1, [ip], #4 8007d46: dcec bgt.n 8007d22 <__multadd+0x12> 8007d48: b1d7 cbz r7, 8007d80 <__multadd+0x70> 8007d4a: 68a3 ldr r3, [r4, #8] 8007d4c: 42ab cmp r3, r5 8007d4e: dc12 bgt.n 8007d76 <__multadd+0x66> 8007d50: 6861 ldr r1, [r4, #4] 8007d52: 4630 mov r0, r6 8007d54: 3101 adds r1, #1 8007d56: f7ff ff90 bl 8007c7a <_Balloc> 8007d5a: 4680 mov r8, r0 8007d5c: 6922 ldr r2, [r4, #16] 8007d5e: f104 010c add.w r1, r4, #12 8007d62: 3202 adds r2, #2 8007d64: 0092 lsls r2, r2, #2 8007d66: 300c adds r0, #12 8007d68: f7ff ff7c bl 8007c64 8007d6c: 4621 mov r1, r4 8007d6e: 4630 mov r0, r6 8007d70: f7ff ffb7 bl 8007ce2 <_Bfree> 8007d74: 4644 mov r4, r8 8007d76: eb04 0385 add.w r3, r4, r5, lsl #2 8007d7a: 3501 adds r5, #1 8007d7c: 615f str r7, [r3, #20] 8007d7e: 6125 str r5, [r4, #16] 8007d80: 4620 mov r0, r4 8007d82: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 08007d86 <__hi0bits>: 8007d86: 0c02 lsrs r2, r0, #16 8007d88: 0412 lsls r2, r2, #16 8007d8a: 4603 mov r3, r0 8007d8c: b9b2 cbnz r2, 8007dbc <__hi0bits+0x36> 8007d8e: 0403 lsls r3, r0, #16 8007d90: 2010 movs r0, #16 8007d92: f013 4f7f tst.w r3, #4278190080 ; 0xff000000 8007d96: bf04 itt eq 8007d98: 021b lsleq r3, r3, #8 8007d9a: 3008 addeq r0, #8 8007d9c: f013 4f70 tst.w r3, #4026531840 ; 0xf0000000 8007da0: bf04 itt eq 8007da2: 011b lsleq r3, r3, #4 8007da4: 3004 addeq r0, #4 8007da6: f013 4f40 tst.w r3, #3221225472 ; 0xc0000000 8007daa: bf04 itt eq 8007dac: 009b lsleq r3, r3, #2 8007dae: 3002 addeq r0, #2 8007db0: 2b00 cmp r3, #0 8007db2: db06 blt.n 8007dc2 <__hi0bits+0x3c> 8007db4: 005b lsls r3, r3, #1 8007db6: d503 bpl.n 8007dc0 <__hi0bits+0x3a> 8007db8: 3001 adds r0, #1 8007dba: 4770 bx lr 8007dbc: 2000 movs r0, #0 8007dbe: e7e8 b.n 8007d92 <__hi0bits+0xc> 8007dc0: 2020 movs r0, #32 8007dc2: 4770 bx lr 08007dc4 <__lo0bits>: 8007dc4: 6803 ldr r3, [r0, #0] 8007dc6: 4601 mov r1, r0 8007dc8: f013 0207 ands.w r2, r3, #7 8007dcc: d00b beq.n 8007de6 <__lo0bits+0x22> 8007dce: 07da lsls r2, r3, #31 8007dd0: d423 bmi.n 8007e1a <__lo0bits+0x56> 8007dd2: 0798 lsls r0, r3, #30 8007dd4: bf49 itett mi 8007dd6: 085b lsrmi r3, r3, #1 8007dd8: 089b lsrpl r3, r3, #2 8007dda: 2001 movmi r0, #1 8007ddc: 600b strmi r3, [r1, #0] 8007dde: bf5c itt pl 8007de0: 600b strpl r3, [r1, #0] 8007de2: 2002 movpl r0, #2 8007de4: 4770 bx lr 8007de6: b298 uxth r0, r3 8007de8: b9a8 cbnz r0, 8007e16 <__lo0bits+0x52> 8007dea: 2010 movs r0, #16 8007dec: 0c1b lsrs r3, r3, #16 8007dee: f013 0fff tst.w r3, #255 ; 0xff 8007df2: bf04 itt eq 8007df4: 0a1b lsreq r3, r3, #8 8007df6: 3008 addeq r0, #8 8007df8: 071a lsls r2, r3, #28 8007dfa: bf04 itt eq 8007dfc: 091b lsreq r3, r3, #4 8007dfe: 3004 addeq r0, #4 8007e00: 079a lsls r2, r3, #30 8007e02: bf04 itt eq 8007e04: 089b lsreq r3, r3, #2 8007e06: 3002 addeq r0, #2 8007e08: 07da lsls r2, r3, #31 8007e0a: d402 bmi.n 8007e12 <__lo0bits+0x4e> 8007e0c: 085b lsrs r3, r3, #1 8007e0e: d006 beq.n 8007e1e <__lo0bits+0x5a> 8007e10: 3001 adds r0, #1 8007e12: 600b str r3, [r1, #0] 8007e14: 4770 bx lr 8007e16: 4610 mov r0, r2 8007e18: e7e9 b.n 8007dee <__lo0bits+0x2a> 8007e1a: 2000 movs r0, #0 8007e1c: 4770 bx lr 8007e1e: 2020 movs r0, #32 8007e20: 4770 bx lr 08007e22 <__i2b>: 8007e22: b510 push {r4, lr} 8007e24: 460c mov r4, r1 8007e26: 2101 movs r1, #1 8007e28: f7ff ff27 bl 8007c7a <_Balloc> 8007e2c: 2201 movs r2, #1 8007e2e: 6144 str r4, [r0, #20] 8007e30: 6102 str r2, [r0, #16] 8007e32: bd10 pop {r4, pc} 08007e34 <__multiply>: 8007e34: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} 8007e38: 4614 mov r4, r2 8007e3a: 690a ldr r2, [r1, #16] 8007e3c: 6923 ldr r3, [r4, #16] 8007e3e: 4688 mov r8, r1 8007e40: 429a cmp r2, r3 8007e42: bfbe ittt lt 8007e44: 460b movlt r3, r1 8007e46: 46a0 movlt r8, r4 8007e48: 461c movlt r4, r3 8007e4a: f8d8 7010 ldr.w r7, [r8, #16] 8007e4e: f8d4 9010 ldr.w r9, [r4, #16] 8007e52: f8d8 3008 ldr.w r3, [r8, #8] 8007e56: f8d8 1004 ldr.w r1, [r8, #4] 8007e5a: eb07 0609 add.w r6, r7, r9 8007e5e: 42b3 cmp r3, r6 8007e60: bfb8 it lt 8007e62: 3101 addlt r1, #1 8007e64: f7ff ff09 bl 8007c7a <_Balloc> 8007e68: f100 0514 add.w r5, r0, #20 8007e6c: 462b mov r3, r5 8007e6e: 2200 movs r2, #0 8007e70: eb05 0e86 add.w lr, r5, r6, lsl #2 8007e74: 4573 cmp r3, lr 8007e76: d316 bcc.n 8007ea6 <__multiply+0x72> 8007e78: f104 0214 add.w r2, r4, #20 8007e7c: f108 0114 add.w r1, r8, #20 8007e80: eb02 0389 add.w r3, r2, r9, lsl #2 8007e84: eb01 0787 add.w r7, r1, r7, lsl #2 8007e88: 9300 str r3, [sp, #0] 8007e8a: 9b00 ldr r3, [sp, #0] 8007e8c: 9201 str r2, [sp, #4] 8007e8e: 4293 cmp r3, r2 8007e90: d80c bhi.n 8007eac <__multiply+0x78> 8007e92: 2e00 cmp r6, #0 8007e94: dd03 ble.n 8007e9e <__multiply+0x6a> 8007e96: f85e 3d04 ldr.w r3, [lr, #-4]! 8007e9a: 2b00 cmp r3, #0 8007e9c: d05d beq.n 8007f5a <__multiply+0x126> 8007e9e: 6106 str r6, [r0, #16] 8007ea0: b003 add sp, #12 8007ea2: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8007ea6: f843 2b04 str.w r2, [r3], #4 8007eaa: e7e3 b.n 8007e74 <__multiply+0x40> 8007eac: f8b2 b000 ldrh.w fp, [r2] 8007eb0: f1bb 0f00 cmp.w fp, #0 8007eb4: d023 beq.n 8007efe <__multiply+0xca> 8007eb6: 4689 mov r9, r1 8007eb8: 46ac mov ip, r5 8007eba: f04f 0800 mov.w r8, #0 8007ebe: f859 4b04 ldr.w r4, [r9], #4 8007ec2: f8dc a000 ldr.w sl, [ip] 8007ec6: b2a3 uxth r3, r4 8007ec8: fa1f fa8a uxth.w sl, sl 8007ecc: fb0b a303 mla r3, fp, r3, sl 8007ed0: ea4f 4a14 mov.w sl, r4, lsr #16 8007ed4: f8dc 4000 ldr.w r4, [ip] 8007ed8: 4443 add r3, r8 8007eda: ea4f 4814 mov.w r8, r4, lsr #16 8007ede: fb0b 840a mla r4, fp, sl, r8 8007ee2: 46e2 mov sl, ip 8007ee4: eb04 4413 add.w r4, r4, r3, lsr #16 8007ee8: b29b uxth r3, r3 8007eea: ea43 4304 orr.w r3, r3, r4, lsl #16 8007eee: 454f cmp r7, r9 8007ef0: ea4f 4814 mov.w r8, r4, lsr #16 8007ef4: f84a 3b04 str.w r3, [sl], #4 8007ef8: d82b bhi.n 8007f52 <__multiply+0x11e> 8007efa: f8cc 8004 str.w r8, [ip, #4] 8007efe: 9b01 ldr r3, [sp, #4] 8007f00: 3204 adds r2, #4 8007f02: f8b3 a002 ldrh.w sl, [r3, #2] 8007f06: f1ba 0f00 cmp.w sl, #0 8007f0a: d020 beq.n 8007f4e <__multiply+0x11a> 8007f0c: 4689 mov r9, r1 8007f0e: 46a8 mov r8, r5 8007f10: f04f 0b00 mov.w fp, #0 8007f14: 682b ldr r3, [r5, #0] 8007f16: f8b9 c000 ldrh.w ip, [r9] 8007f1a: f8b8 4002 ldrh.w r4, [r8, #2] 8007f1e: b29b uxth r3, r3 8007f20: fb0a 440c mla r4, sl, ip, r4 8007f24: 46c4 mov ip, r8 8007f26: 445c add r4, fp 8007f28: ea43 4304 orr.w r3, r3, r4, lsl #16 8007f2c: f84c 3b04 str.w r3, [ip], #4 8007f30: f859 3b04 ldr.w r3, [r9], #4 8007f34: f8b8 b004 ldrh.w fp, [r8, #4] 8007f38: 0c1b lsrs r3, r3, #16 8007f3a: fb0a b303 mla r3, sl, r3, fp 8007f3e: 454f cmp r7, r9 8007f40: eb03 4314 add.w r3, r3, r4, lsr #16 8007f44: ea4f 4b13 mov.w fp, r3, lsr #16 8007f48: d805 bhi.n 8007f56 <__multiply+0x122> 8007f4a: f8c8 3004 str.w r3, [r8, #4] 8007f4e: 3504 adds r5, #4 8007f50: e79b b.n 8007e8a <__multiply+0x56> 8007f52: 46d4 mov ip, sl 8007f54: e7b3 b.n 8007ebe <__multiply+0x8a> 8007f56: 46e0 mov r8, ip 8007f58: e7dd b.n 8007f16 <__multiply+0xe2> 8007f5a: 3e01 subs r6, #1 8007f5c: e799 b.n 8007e92 <__multiply+0x5e> ... 08007f60 <__pow5mult>: 8007f60: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 8007f64: 4615 mov r5, r2 8007f66: f012 0203 ands.w r2, r2, #3 8007f6a: 4606 mov r6, r0 8007f6c: 460f mov r7, r1 8007f6e: d007 beq.n 8007f80 <__pow5mult+0x20> 8007f70: 4c21 ldr r4, [pc, #132] ; (8007ff8 <__pow5mult+0x98>) 8007f72: 3a01 subs r2, #1 8007f74: 2300 movs r3, #0 8007f76: f854 2022 ldr.w r2, [r4, r2, lsl #2] 8007f7a: f7ff fec9 bl 8007d10 <__multadd> 8007f7e: 4607 mov r7, r0 8007f80: 10ad asrs r5, r5, #2 8007f82: d035 beq.n 8007ff0 <__pow5mult+0x90> 8007f84: 6a74 ldr r4, [r6, #36] ; 0x24 8007f86: b93c cbnz r4, 8007f98 <__pow5mult+0x38> 8007f88: 2010 movs r0, #16 8007f8a: f7ff fe55 bl 8007c38 8007f8e: 6270 str r0, [r6, #36] ; 0x24 8007f90: e9c0 4401 strd r4, r4, [r0, #4] 8007f94: 6004 str r4, [r0, #0] 8007f96: 60c4 str r4, [r0, #12] 8007f98: f8d6 8024 ldr.w r8, [r6, #36] ; 0x24 8007f9c: f8d8 4008 ldr.w r4, [r8, #8] 8007fa0: b94c cbnz r4, 8007fb6 <__pow5mult+0x56> 8007fa2: f240 2171 movw r1, #625 ; 0x271 8007fa6: 4630 mov r0, r6 8007fa8: f7ff ff3b bl 8007e22 <__i2b> 8007fac: 2300 movs r3, #0 8007fae: 4604 mov r4, r0 8007fb0: f8c8 0008 str.w r0, [r8, #8] 8007fb4: 6003 str r3, [r0, #0] 8007fb6: f04f 0800 mov.w r8, #0 8007fba: 07eb lsls r3, r5, #31 8007fbc: d50a bpl.n 8007fd4 <__pow5mult+0x74> 8007fbe: 4639 mov r1, r7 8007fc0: 4622 mov r2, r4 8007fc2: 4630 mov r0, r6 8007fc4: f7ff ff36 bl 8007e34 <__multiply> 8007fc8: 4681 mov r9, r0 8007fca: 4639 mov r1, r7 8007fcc: 4630 mov r0, r6 8007fce: f7ff fe88 bl 8007ce2 <_Bfree> 8007fd2: 464f mov r7, r9 8007fd4: 106d asrs r5, r5, #1 8007fd6: d00b beq.n 8007ff0 <__pow5mult+0x90> 8007fd8: 6820 ldr r0, [r4, #0] 8007fda: b938 cbnz r0, 8007fec <__pow5mult+0x8c> 8007fdc: 4622 mov r2, r4 8007fde: 4621 mov r1, r4 8007fe0: 4630 mov r0, r6 8007fe2: f7ff ff27 bl 8007e34 <__multiply> 8007fe6: 6020 str r0, [r4, #0] 8007fe8: f8c0 8000 str.w r8, [r0] 8007fec: 4604 mov r4, r0 8007fee: e7e4 b.n 8007fba <__pow5mult+0x5a> 8007ff0: 4638 mov r0, r7 8007ff2: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 8007ff6: bf00 nop 8007ff8: 08008d48 .word 0x08008d48 08007ffc <__lshift>: 8007ffc: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8008000: 460c mov r4, r1 8008002: 4607 mov r7, r0 8008004: 4616 mov r6, r2 8008006: 6923 ldr r3, [r4, #16] 8008008: ea4f 1a62 mov.w sl, r2, asr #5 800800c: eb0a 0903 add.w r9, sl, r3 8008010: 6849 ldr r1, [r1, #4] 8008012: 68a3 ldr r3, [r4, #8] 8008014: f109 0501 add.w r5, r9, #1 8008018: 42ab cmp r3, r5 800801a: db32 blt.n 8008082 <__lshift+0x86> 800801c: 4638 mov r0, r7 800801e: f7ff fe2c bl 8007c7a <_Balloc> 8008022: 2300 movs r3, #0 8008024: 4680 mov r8, r0 8008026: 461a mov r2, r3 8008028: f100 0114 add.w r1, r0, #20 800802c: 4553 cmp r3, sl 800802e: db2b blt.n 8008088 <__lshift+0x8c> 8008030: 6920 ldr r0, [r4, #16] 8008032: ea2a 7aea bic.w sl, sl, sl, asr #31 8008036: f104 0314 add.w r3, r4, #20 800803a: f016 021f ands.w r2, r6, #31 800803e: eb01 018a add.w r1, r1, sl, lsl #2 8008042: eb03 0c80 add.w ip, r3, r0, lsl #2 8008046: d025 beq.n 8008094 <__lshift+0x98> 8008048: 2000 movs r0, #0 800804a: f1c2 0e20 rsb lr, r2, #32 800804e: 468a mov sl, r1 8008050: 681e ldr r6, [r3, #0] 8008052: 4096 lsls r6, r2 8008054: 4330 orrs r0, r6 8008056: f84a 0b04 str.w r0, [sl], #4 800805a: f853 0b04 ldr.w r0, [r3], #4 800805e: 459c cmp ip, r3 8008060: fa20 f00e lsr.w r0, r0, lr 8008064: d814 bhi.n 8008090 <__lshift+0x94> 8008066: 6048 str r0, [r1, #4] 8008068: b108 cbz r0, 800806e <__lshift+0x72> 800806a: f109 0502 add.w r5, r9, #2 800806e: 3d01 subs r5, #1 8008070: 4638 mov r0, r7 8008072: f8c8 5010 str.w r5, [r8, #16] 8008076: 4621 mov r1, r4 8008078: f7ff fe33 bl 8007ce2 <_Bfree> 800807c: 4640 mov r0, r8 800807e: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8008082: 3101 adds r1, #1 8008084: 005b lsls r3, r3, #1 8008086: e7c7 b.n 8008018 <__lshift+0x1c> 8008088: f841 2023 str.w r2, [r1, r3, lsl #2] 800808c: 3301 adds r3, #1 800808e: e7cd b.n 800802c <__lshift+0x30> 8008090: 4651 mov r1, sl 8008092: e7dc b.n 800804e <__lshift+0x52> 8008094: 3904 subs r1, #4 8008096: f853 2b04 ldr.w r2, [r3], #4 800809a: 459c cmp ip, r3 800809c: f841 2f04 str.w r2, [r1, #4]! 80080a0: d8f9 bhi.n 8008096 <__lshift+0x9a> 80080a2: e7e4 b.n 800806e <__lshift+0x72> 080080a4 <__mcmp>: 80080a4: 6903 ldr r3, [r0, #16] 80080a6: 690a ldr r2, [r1, #16] 80080a8: b530 push {r4, r5, lr} 80080aa: 1a9b subs r3, r3, r2 80080ac: d10c bne.n 80080c8 <__mcmp+0x24> 80080ae: 0092 lsls r2, r2, #2 80080b0: 3014 adds r0, #20 80080b2: 3114 adds r1, #20 80080b4: 1884 adds r4, r0, r2 80080b6: 4411 add r1, r2 80080b8: f854 5d04 ldr.w r5, [r4, #-4]! 80080bc: f851 2d04 ldr.w r2, [r1, #-4]! 80080c0: 4295 cmp r5, r2 80080c2: d003 beq.n 80080cc <__mcmp+0x28> 80080c4: d305 bcc.n 80080d2 <__mcmp+0x2e> 80080c6: 2301 movs r3, #1 80080c8: 4618 mov r0, r3 80080ca: bd30 pop {r4, r5, pc} 80080cc: 42a0 cmp r0, r4 80080ce: d3f3 bcc.n 80080b8 <__mcmp+0x14> 80080d0: e7fa b.n 80080c8 <__mcmp+0x24> 80080d2: f04f 33ff mov.w r3, #4294967295 80080d6: e7f7 b.n 80080c8 <__mcmp+0x24> 080080d8 <__mdiff>: 80080d8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 80080dc: 460d mov r5, r1 80080de: 4607 mov r7, r0 80080e0: 4611 mov r1, r2 80080e2: 4628 mov r0, r5 80080e4: 4614 mov r4, r2 80080e6: f7ff ffdd bl 80080a4 <__mcmp> 80080ea: 1e06 subs r6, r0, #0 80080ec: d108 bne.n 8008100 <__mdiff+0x28> 80080ee: 4631 mov r1, r6 80080f0: 4638 mov r0, r7 80080f2: f7ff fdc2 bl 8007c7a <_Balloc> 80080f6: 2301 movs r3, #1 80080f8: e9c0 3604 strd r3, r6, [r0, #16] 80080fc: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8008100: bfa4 itt ge 8008102: 4623 movge r3, r4 8008104: 462c movge r4, r5 8008106: 4638 mov r0, r7 8008108: 6861 ldr r1, [r4, #4] 800810a: bfa6 itte ge 800810c: 461d movge r5, r3 800810e: 2600 movge r6, #0 8008110: 2601 movlt r6, #1 8008112: f7ff fdb2 bl 8007c7a <_Balloc> 8008116: f04f 0e00 mov.w lr, #0 800811a: 60c6 str r6, [r0, #12] 800811c: 692b ldr r3, [r5, #16] 800811e: 6926 ldr r6, [r4, #16] 8008120: f104 0214 add.w r2, r4, #20 8008124: f105 0914 add.w r9, r5, #20 8008128: eb02 0786 add.w r7, r2, r6, lsl #2 800812c: eb09 0883 add.w r8, r9, r3, lsl #2 8008130: f100 0114 add.w r1, r0, #20 8008134: f852 ab04 ldr.w sl, [r2], #4 8008138: f859 5b04 ldr.w r5, [r9], #4 800813c: fa1f f38a uxth.w r3, sl 8008140: 4473 add r3, lr 8008142: b2ac uxth r4, r5 8008144: 1b1b subs r3, r3, r4 8008146: 0c2c lsrs r4, r5, #16 8008148: ebc4 441a rsb r4, r4, sl, lsr #16 800814c: eb04 4423 add.w r4, r4, r3, asr #16 8008150: b29b uxth r3, r3 8008152: ea4f 4e24 mov.w lr, r4, asr #16 8008156: 45c8 cmp r8, r9 8008158: ea43 4404 orr.w r4, r3, r4, lsl #16 800815c: 4694 mov ip, r2 800815e: f841 4b04 str.w r4, [r1], #4 8008162: d8e7 bhi.n 8008134 <__mdiff+0x5c> 8008164: 45bc cmp ip, r7 8008166: d304 bcc.n 8008172 <__mdiff+0x9a> 8008168: f851 3d04 ldr.w r3, [r1, #-4]! 800816c: b183 cbz r3, 8008190 <__mdiff+0xb8> 800816e: 6106 str r6, [r0, #16] 8008170: e7c4 b.n 80080fc <__mdiff+0x24> 8008172: f85c 4b04 ldr.w r4, [ip], #4 8008176: b2a2 uxth r2, r4 8008178: 4472 add r2, lr 800817a: 1413 asrs r3, r2, #16 800817c: eb03 4314 add.w r3, r3, r4, lsr #16 8008180: b292 uxth r2, r2 8008182: ea42 4203 orr.w r2, r2, r3, lsl #16 8008186: ea4f 4e23 mov.w lr, r3, asr #16 800818a: f841 2b04 str.w r2, [r1], #4 800818e: e7e9 b.n 8008164 <__mdiff+0x8c> 8008190: 3e01 subs r6, #1 8008192: e7e9 b.n 8008168 <__mdiff+0x90> 08008194 <__d2b>: 8008194: e92d 41f3 stmdb sp!, {r0, r1, r4, r5, r6, r7, r8, lr} 8008198: 461c mov r4, r3 800819a: e9dd 6508 ldrd r6, r5, [sp, #32] 800819e: 2101 movs r1, #1 80081a0: 4690 mov r8, r2 80081a2: f7ff fd6a bl 8007c7a <_Balloc> 80081a6: f3c4 0213 ubfx r2, r4, #0, #20 80081aa: f3c4 540a ubfx r4, r4, #20, #11 80081ae: 4607 mov r7, r0 80081b0: bb34 cbnz r4, 8008200 <__d2b+0x6c> 80081b2: 9201 str r2, [sp, #4] 80081b4: f1b8 0200 subs.w r2, r8, #0 80081b8: d027 beq.n 800820a <__d2b+0x76> 80081ba: a802 add r0, sp, #8 80081bc: f840 2d08 str.w r2, [r0, #-8]! 80081c0: f7ff fe00 bl 8007dc4 <__lo0bits> 80081c4: 9900 ldr r1, [sp, #0] 80081c6: b1f0 cbz r0, 8008206 <__d2b+0x72> 80081c8: 9a01 ldr r2, [sp, #4] 80081ca: f1c0 0320 rsb r3, r0, #32 80081ce: fa02 f303 lsl.w r3, r2, r3 80081d2: 430b orrs r3, r1 80081d4: 40c2 lsrs r2, r0 80081d6: 617b str r3, [r7, #20] 80081d8: 9201 str r2, [sp, #4] 80081da: 9b01 ldr r3, [sp, #4] 80081dc: 2b00 cmp r3, #0 80081de: bf14 ite ne 80081e0: 2102 movne r1, #2 80081e2: 2101 moveq r1, #1 80081e4: 61bb str r3, [r7, #24] 80081e6: 6139 str r1, [r7, #16] 80081e8: b1c4 cbz r4, 800821c <__d2b+0x88> 80081ea: f2a4 4433 subw r4, r4, #1075 ; 0x433 80081ee: 4404 add r4, r0 80081f0: 6034 str r4, [r6, #0] 80081f2: f1c0 0035 rsb r0, r0, #53 ; 0x35 80081f6: 6028 str r0, [r5, #0] 80081f8: 4638 mov r0, r7 80081fa: b002 add sp, #8 80081fc: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8008200: f442 1280 orr.w r2, r2, #1048576 ; 0x100000 8008204: e7d5 b.n 80081b2 <__d2b+0x1e> 8008206: 6179 str r1, [r7, #20] 8008208: e7e7 b.n 80081da <__d2b+0x46> 800820a: a801 add r0, sp, #4 800820c: f7ff fdda bl 8007dc4 <__lo0bits> 8008210: 2101 movs r1, #1 8008212: 9b01 ldr r3, [sp, #4] 8008214: 6139 str r1, [r7, #16] 8008216: 617b str r3, [r7, #20] 8008218: 3020 adds r0, #32 800821a: e7e5 b.n 80081e8 <__d2b+0x54> 800821c: f2a0 4032 subw r0, r0, #1074 ; 0x432 8008220: eb07 0381 add.w r3, r7, r1, lsl #2 8008224: 6030 str r0, [r6, #0] 8008226: 6918 ldr r0, [r3, #16] 8008228: f7ff fdad bl 8007d86 <__hi0bits> 800822c: ebc0 1041 rsb r0, r0, r1, lsl #5 8008230: e7e1 b.n 80081f6 <__d2b+0x62> 08008232 <_calloc_r>: 8008232: b538 push {r3, r4, r5, lr} 8008234: fb02 f401 mul.w r4, r2, r1 8008238: 4621 mov r1, r4 800823a: f000 f855 bl 80082e8 <_malloc_r> 800823e: 4605 mov r5, r0 8008240: b118 cbz r0, 800824a <_calloc_r+0x18> 8008242: 4622 mov r2, r4 8008244: 2100 movs r1, #0 8008246: f7fd fe7d bl 8005f44 800824a: 4628 mov r0, r5 800824c: bd38 pop {r3, r4, r5, pc} ... 08008250 <_free_r>: 8008250: b538 push {r3, r4, r5, lr} 8008252: 4605 mov r5, r0 8008254: 2900 cmp r1, #0 8008256: d043 beq.n 80082e0 <_free_r+0x90> 8008258: f851 3c04 ldr.w r3, [r1, #-4] 800825c: 1f0c subs r4, r1, #4 800825e: 2b00 cmp r3, #0 8008260: bfb8 it lt 8008262: 18e4 addlt r4, r4, r3 8008264: f000 fa94 bl 8008790 <__malloc_lock> 8008268: 4a1e ldr r2, [pc, #120] ; (80082e4 <_free_r+0x94>) 800826a: 6813 ldr r3, [r2, #0] 800826c: 4610 mov r0, r2 800826e: b933 cbnz r3, 800827e <_free_r+0x2e> 8008270: 6063 str r3, [r4, #4] 8008272: 6014 str r4, [r2, #0] 8008274: 4628 mov r0, r5 8008276: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 800827a: f000 ba8a b.w 8008792 <__malloc_unlock> 800827e: 42a3 cmp r3, r4 8008280: d90b bls.n 800829a <_free_r+0x4a> 8008282: 6821 ldr r1, [r4, #0] 8008284: 1862 adds r2, r4, r1 8008286: 4293 cmp r3, r2 8008288: bf01 itttt eq 800828a: 681a ldreq r2, [r3, #0] 800828c: 685b ldreq r3, [r3, #4] 800828e: 1852 addeq r2, r2, r1 8008290: 6022 streq r2, [r4, #0] 8008292: 6063 str r3, [r4, #4] 8008294: 6004 str r4, [r0, #0] 8008296: e7ed b.n 8008274 <_free_r+0x24> 8008298: 4613 mov r3, r2 800829a: 685a ldr r2, [r3, #4] 800829c: b10a cbz r2, 80082a2 <_free_r+0x52> 800829e: 42a2 cmp r2, r4 80082a0: d9fa bls.n 8008298 <_free_r+0x48> 80082a2: 6819 ldr r1, [r3, #0] 80082a4: 1858 adds r0, r3, r1 80082a6: 42a0 cmp r0, r4 80082a8: d10b bne.n 80082c2 <_free_r+0x72> 80082aa: 6820 ldr r0, [r4, #0] 80082ac: 4401 add r1, r0 80082ae: 1858 adds r0, r3, r1 80082b0: 4282 cmp r2, r0 80082b2: 6019 str r1, [r3, #0] 80082b4: d1de bne.n 8008274 <_free_r+0x24> 80082b6: 6810 ldr r0, [r2, #0] 80082b8: 6852 ldr r2, [r2, #4] 80082ba: 4401 add r1, r0 80082bc: 6019 str r1, [r3, #0] 80082be: 605a str r2, [r3, #4] 80082c0: e7d8 b.n 8008274 <_free_r+0x24> 80082c2: d902 bls.n 80082ca <_free_r+0x7a> 80082c4: 230c movs r3, #12 80082c6: 602b str r3, [r5, #0] 80082c8: e7d4 b.n 8008274 <_free_r+0x24> 80082ca: 6820 ldr r0, [r4, #0] 80082cc: 1821 adds r1, r4, r0 80082ce: 428a cmp r2, r1 80082d0: bf01 itttt eq 80082d2: 6811 ldreq r1, [r2, #0] 80082d4: 6852 ldreq r2, [r2, #4] 80082d6: 1809 addeq r1, r1, r0 80082d8: 6021 streq r1, [r4, #0] 80082da: 6062 str r2, [r4, #4] 80082dc: 605c str r4, [r3, #4] 80082de: e7c9 b.n 8008274 <_free_r+0x24> 80082e0: bd38 pop {r3, r4, r5, pc} 80082e2: bf00 nop 80082e4: 20000640 .word 0x20000640 080082e8 <_malloc_r>: 80082e8: b570 push {r4, r5, r6, lr} 80082ea: 1ccd adds r5, r1, #3 80082ec: f025 0503 bic.w r5, r5, #3 80082f0: 3508 adds r5, #8 80082f2: 2d0c cmp r5, #12 80082f4: bf38 it cc 80082f6: 250c movcc r5, #12 80082f8: 2d00 cmp r5, #0 80082fa: 4606 mov r6, r0 80082fc: db01 blt.n 8008302 <_malloc_r+0x1a> 80082fe: 42a9 cmp r1, r5 8008300: d903 bls.n 800830a <_malloc_r+0x22> 8008302: 230c movs r3, #12 8008304: 6033 str r3, [r6, #0] 8008306: 2000 movs r0, #0 8008308: bd70 pop {r4, r5, r6, pc} 800830a: f000 fa41 bl 8008790 <__malloc_lock> 800830e: 4a21 ldr r2, [pc, #132] ; (8008394 <_malloc_r+0xac>) 8008310: 6814 ldr r4, [r2, #0] 8008312: 4621 mov r1, r4 8008314: b991 cbnz r1, 800833c <_malloc_r+0x54> 8008316: 4c20 ldr r4, [pc, #128] ; (8008398 <_malloc_r+0xb0>) 8008318: 6823 ldr r3, [r4, #0] 800831a: b91b cbnz r3, 8008324 <_malloc_r+0x3c> 800831c: 4630 mov r0, r6 800831e: f000 f97b bl 8008618 <_sbrk_r> 8008322: 6020 str r0, [r4, #0] 8008324: 4629 mov r1, r5 8008326: 4630 mov r0, r6 8008328: f000 f976 bl 8008618 <_sbrk_r> 800832c: 1c43 adds r3, r0, #1 800832e: d124 bne.n 800837a <_malloc_r+0x92> 8008330: 230c movs r3, #12 8008332: 4630 mov r0, r6 8008334: 6033 str r3, [r6, #0] 8008336: f000 fa2c bl 8008792 <__malloc_unlock> 800833a: e7e4 b.n 8008306 <_malloc_r+0x1e> 800833c: 680b ldr r3, [r1, #0] 800833e: 1b5b subs r3, r3, r5 8008340: d418 bmi.n 8008374 <_malloc_r+0x8c> 8008342: 2b0b cmp r3, #11 8008344: d90f bls.n 8008366 <_malloc_r+0x7e> 8008346: 600b str r3, [r1, #0] 8008348: 18cc adds r4, r1, r3 800834a: 50cd str r5, [r1, r3] 800834c: 4630 mov r0, r6 800834e: f000 fa20 bl 8008792 <__malloc_unlock> 8008352: f104 000b add.w r0, r4, #11 8008356: 1d23 adds r3, r4, #4 8008358: f020 0007 bic.w r0, r0, #7 800835c: 1ac3 subs r3, r0, r3 800835e: d0d3 beq.n 8008308 <_malloc_r+0x20> 8008360: 425a negs r2, r3 8008362: 50e2 str r2, [r4, r3] 8008364: e7d0 b.n 8008308 <_malloc_r+0x20> 8008366: 684b ldr r3, [r1, #4] 8008368: 428c cmp r4, r1 800836a: bf16 itet ne 800836c: 6063 strne r3, [r4, #4] 800836e: 6013 streq r3, [r2, #0] 8008370: 460c movne r4, r1 8008372: e7eb b.n 800834c <_malloc_r+0x64> 8008374: 460c mov r4, r1 8008376: 6849 ldr r1, [r1, #4] 8008378: e7cc b.n 8008314 <_malloc_r+0x2c> 800837a: 1cc4 adds r4, r0, #3 800837c: f024 0403 bic.w r4, r4, #3 8008380: 42a0 cmp r0, r4 8008382: d005 beq.n 8008390 <_malloc_r+0xa8> 8008384: 1a21 subs r1, r4, r0 8008386: 4630 mov r0, r6 8008388: f000 f946 bl 8008618 <_sbrk_r> 800838c: 3001 adds r0, #1 800838e: d0cf beq.n 8008330 <_malloc_r+0x48> 8008390: 6025 str r5, [r4, #0] 8008392: e7db b.n 800834c <_malloc_r+0x64> 8008394: 20000640 .word 0x20000640 8008398: 20000644 .word 0x20000644 0800839c <__sfputc_r>: 800839c: 6893 ldr r3, [r2, #8] 800839e: b410 push {r4} 80083a0: 3b01 subs r3, #1 80083a2: 2b00 cmp r3, #0 80083a4: 6093 str r3, [r2, #8] 80083a6: da07 bge.n 80083b8 <__sfputc_r+0x1c> 80083a8: 6994 ldr r4, [r2, #24] 80083aa: 42a3 cmp r3, r4 80083ac: db01 blt.n 80083b2 <__sfputc_r+0x16> 80083ae: 290a cmp r1, #10 80083b0: d102 bne.n 80083b8 <__sfputc_r+0x1c> 80083b2: bc10 pop {r4} 80083b4: f7fe bb50 b.w 8006a58 <__swbuf_r> 80083b8: 6813 ldr r3, [r2, #0] 80083ba: 1c58 adds r0, r3, #1 80083bc: 6010 str r0, [r2, #0] 80083be: 7019 strb r1, [r3, #0] 80083c0: 4608 mov r0, r1 80083c2: bc10 pop {r4} 80083c4: 4770 bx lr 080083c6 <__sfputs_r>: 80083c6: b5f8 push {r3, r4, r5, r6, r7, lr} 80083c8: 4606 mov r6, r0 80083ca: 460f mov r7, r1 80083cc: 4614 mov r4, r2 80083ce: 18d5 adds r5, r2, r3 80083d0: 42ac cmp r4, r5 80083d2: d101 bne.n 80083d8 <__sfputs_r+0x12> 80083d4: 2000 movs r0, #0 80083d6: e007 b.n 80083e8 <__sfputs_r+0x22> 80083d8: 463a mov r2, r7 80083da: f814 1b01 ldrb.w r1, [r4], #1 80083de: 4630 mov r0, r6 80083e0: f7ff ffdc bl 800839c <__sfputc_r> 80083e4: 1c43 adds r3, r0, #1 80083e6: d1f3 bne.n 80083d0 <__sfputs_r+0xa> 80083e8: bdf8 pop {r3, r4, r5, r6, r7, pc} ... 080083ec <_vfiprintf_r>: 80083ec: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 80083f0: 460c mov r4, r1 80083f2: b09d sub sp, #116 ; 0x74 80083f4: 4617 mov r7, r2 80083f6: 461d mov r5, r3 80083f8: 4606 mov r6, r0 80083fa: b118 cbz r0, 8008404 <_vfiprintf_r+0x18> 80083fc: 6983 ldr r3, [r0, #24] 80083fe: b90b cbnz r3, 8008404 <_vfiprintf_r+0x18> 8008400: f7ff fb1e bl 8007a40 <__sinit> 8008404: 4b7c ldr r3, [pc, #496] ; (80085f8 <_vfiprintf_r+0x20c>) 8008406: 429c cmp r4, r3 8008408: d158 bne.n 80084bc <_vfiprintf_r+0xd0> 800840a: 6874 ldr r4, [r6, #4] 800840c: 89a3 ldrh r3, [r4, #12] 800840e: 0718 lsls r0, r3, #28 8008410: d55e bpl.n 80084d0 <_vfiprintf_r+0xe4> 8008412: 6923 ldr r3, [r4, #16] 8008414: 2b00 cmp r3, #0 8008416: d05b beq.n 80084d0 <_vfiprintf_r+0xe4> 8008418: 2300 movs r3, #0 800841a: 9309 str r3, [sp, #36] ; 0x24 800841c: 2320 movs r3, #32 800841e: f88d 3029 strb.w r3, [sp, #41] ; 0x29 8008422: 2330 movs r3, #48 ; 0x30 8008424: f04f 0b01 mov.w fp, #1 8008428: f88d 302a strb.w r3, [sp, #42] ; 0x2a 800842c: 9503 str r5, [sp, #12] 800842e: 46b8 mov r8, r7 8008430: 4645 mov r5, r8 8008432: f815 3b01 ldrb.w r3, [r5], #1 8008436: b10b cbz r3, 800843c <_vfiprintf_r+0x50> 8008438: 2b25 cmp r3, #37 ; 0x25 800843a: d154 bne.n 80084e6 <_vfiprintf_r+0xfa> 800843c: ebb8 0a07 subs.w sl, r8, r7 8008440: d00b beq.n 800845a <_vfiprintf_r+0x6e> 8008442: 4653 mov r3, sl 8008444: 463a mov r2, r7 8008446: 4621 mov r1, r4 8008448: 4630 mov r0, r6 800844a: f7ff ffbc bl 80083c6 <__sfputs_r> 800844e: 3001 adds r0, #1 8008450: f000 80c2 beq.w 80085d8 <_vfiprintf_r+0x1ec> 8008454: 9b09 ldr r3, [sp, #36] ; 0x24 8008456: 4453 add r3, sl 8008458: 9309 str r3, [sp, #36] ; 0x24 800845a: f898 3000 ldrb.w r3, [r8] 800845e: 2b00 cmp r3, #0 8008460: f000 80ba beq.w 80085d8 <_vfiprintf_r+0x1ec> 8008464: 2300 movs r3, #0 8008466: f04f 32ff mov.w r2, #4294967295 800846a: e9cd 2305 strd r2, r3, [sp, #20] 800846e: 9304 str r3, [sp, #16] 8008470: 9307 str r3, [sp, #28] 8008472: f88d 3053 strb.w r3, [sp, #83] ; 0x53 8008476: 931a str r3, [sp, #104] ; 0x68 8008478: 46a8 mov r8, r5 800847a: 2205 movs r2, #5 800847c: f818 1b01 ldrb.w r1, [r8], #1 8008480: 485e ldr r0, [pc, #376] ; (80085fc <_vfiprintf_r+0x210>) 8008482: f7ff fbe1 bl 8007c48 8008486: 9b04 ldr r3, [sp, #16] 8008488: bb78 cbnz r0, 80084ea <_vfiprintf_r+0xfe> 800848a: 06d9 lsls r1, r3, #27 800848c: bf44 itt mi 800848e: 2220 movmi r2, #32 8008490: f88d 2053 strbmi.w r2, [sp, #83] ; 0x53 8008494: 071a lsls r2, r3, #28 8008496: bf44 itt mi 8008498: 222b movmi r2, #43 ; 0x2b 800849a: f88d 2053 strbmi.w r2, [sp, #83] ; 0x53 800849e: 782a ldrb r2, [r5, #0] 80084a0: 2a2a cmp r2, #42 ; 0x2a 80084a2: d02a beq.n 80084fa <_vfiprintf_r+0x10e> 80084a4: 46a8 mov r8, r5 80084a6: 2000 movs r0, #0 80084a8: 250a movs r5, #10 80084aa: 9a07 ldr r2, [sp, #28] 80084ac: 4641 mov r1, r8 80084ae: f811 3b01 ldrb.w r3, [r1], #1 80084b2: 3b30 subs r3, #48 ; 0x30 80084b4: 2b09 cmp r3, #9 80084b6: d969 bls.n 800858c <_vfiprintf_r+0x1a0> 80084b8: b360 cbz r0, 8008514 <_vfiprintf_r+0x128> 80084ba: e024 b.n 8008506 <_vfiprintf_r+0x11a> 80084bc: 4b50 ldr r3, [pc, #320] ; (8008600 <_vfiprintf_r+0x214>) 80084be: 429c cmp r4, r3 80084c0: d101 bne.n 80084c6 <_vfiprintf_r+0xda> 80084c2: 68b4 ldr r4, [r6, #8] 80084c4: e7a2 b.n 800840c <_vfiprintf_r+0x20> 80084c6: 4b4f ldr r3, [pc, #316] ; (8008604 <_vfiprintf_r+0x218>) 80084c8: 429c cmp r4, r3 80084ca: bf08 it eq 80084cc: 68f4 ldreq r4, [r6, #12] 80084ce: e79d b.n 800840c <_vfiprintf_r+0x20> 80084d0: 4621 mov r1, r4 80084d2: 4630 mov r0, r6 80084d4: f7fe fb12 bl 8006afc <__swsetup_r> 80084d8: 2800 cmp r0, #0 80084da: d09d beq.n 8008418 <_vfiprintf_r+0x2c> 80084dc: f04f 30ff mov.w r0, #4294967295 80084e0: b01d add sp, #116 ; 0x74 80084e2: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 80084e6: 46a8 mov r8, r5 80084e8: e7a2 b.n 8008430 <_vfiprintf_r+0x44> 80084ea: 4a44 ldr r2, [pc, #272] ; (80085fc <_vfiprintf_r+0x210>) 80084ec: 4645 mov r5, r8 80084ee: 1a80 subs r0, r0, r2 80084f0: fa0b f000 lsl.w r0, fp, r0 80084f4: 4318 orrs r0, r3 80084f6: 9004 str r0, [sp, #16] 80084f8: e7be b.n 8008478 <_vfiprintf_r+0x8c> 80084fa: 9a03 ldr r2, [sp, #12] 80084fc: 1d11 adds r1, r2, #4 80084fe: 6812 ldr r2, [r2, #0] 8008500: 9103 str r1, [sp, #12] 8008502: 2a00 cmp r2, #0 8008504: db01 blt.n 800850a <_vfiprintf_r+0x11e> 8008506: 9207 str r2, [sp, #28] 8008508: e004 b.n 8008514 <_vfiprintf_r+0x128> 800850a: 4252 negs r2, r2 800850c: f043 0302 orr.w r3, r3, #2 8008510: 9207 str r2, [sp, #28] 8008512: 9304 str r3, [sp, #16] 8008514: f898 3000 ldrb.w r3, [r8] 8008518: 2b2e cmp r3, #46 ; 0x2e 800851a: d10e bne.n 800853a <_vfiprintf_r+0x14e> 800851c: f898 3001 ldrb.w r3, [r8, #1] 8008520: 2b2a cmp r3, #42 ; 0x2a 8008522: d138 bne.n 8008596 <_vfiprintf_r+0x1aa> 8008524: 9b03 ldr r3, [sp, #12] 8008526: f108 0802 add.w r8, r8, #2 800852a: 1d1a adds r2, r3, #4 800852c: 681b ldr r3, [r3, #0] 800852e: 9203 str r2, [sp, #12] 8008530: 2b00 cmp r3, #0 8008532: bfb8 it lt 8008534: f04f 33ff movlt.w r3, #4294967295 8008538: 9305 str r3, [sp, #20] 800853a: 4d33 ldr r5, [pc, #204] ; (8008608 <_vfiprintf_r+0x21c>) 800853c: 2203 movs r2, #3 800853e: f898 1000 ldrb.w r1, [r8] 8008542: 4628 mov r0, r5 8008544: f7ff fb80 bl 8007c48 8008548: b140 cbz r0, 800855c <_vfiprintf_r+0x170> 800854a: 2340 movs r3, #64 ; 0x40 800854c: 1b40 subs r0, r0, r5 800854e: fa03 f000 lsl.w r0, r3, r0 8008552: 9b04 ldr r3, [sp, #16] 8008554: f108 0801 add.w r8, r8, #1 8008558: 4303 orrs r3, r0 800855a: 9304 str r3, [sp, #16] 800855c: f898 1000 ldrb.w r1, [r8] 8008560: 2206 movs r2, #6 8008562: 482a ldr r0, [pc, #168] ; (800860c <_vfiprintf_r+0x220>) 8008564: f108 0701 add.w r7, r8, #1 8008568: f88d 1028 strb.w r1, [sp, #40] ; 0x28 800856c: f7ff fb6c bl 8007c48 8008570: 2800 cmp r0, #0 8008572: d037 beq.n 80085e4 <_vfiprintf_r+0x1f8> 8008574: 4b26 ldr r3, [pc, #152] ; (8008610 <_vfiprintf_r+0x224>) 8008576: bb1b cbnz r3, 80085c0 <_vfiprintf_r+0x1d4> 8008578: 9b03 ldr r3, [sp, #12] 800857a: 3307 adds r3, #7 800857c: f023 0307 bic.w r3, r3, #7 8008580: 3308 adds r3, #8 8008582: 9303 str r3, [sp, #12] 8008584: 9b09 ldr r3, [sp, #36] ; 0x24 8008586: 444b add r3, r9 8008588: 9309 str r3, [sp, #36] ; 0x24 800858a: e750 b.n 800842e <_vfiprintf_r+0x42> 800858c: fb05 3202 mla r2, r5, r2, r3 8008590: 2001 movs r0, #1 8008592: 4688 mov r8, r1 8008594: e78a b.n 80084ac <_vfiprintf_r+0xc0> 8008596: 2300 movs r3, #0 8008598: 250a movs r5, #10 800859a: 4619 mov r1, r3 800859c: f108 0801 add.w r8, r8, #1 80085a0: 9305 str r3, [sp, #20] 80085a2: 4640 mov r0, r8 80085a4: f810 2b01 ldrb.w r2, [r0], #1 80085a8: 3a30 subs r2, #48 ; 0x30 80085aa: 2a09 cmp r2, #9 80085ac: d903 bls.n 80085b6 <_vfiprintf_r+0x1ca> 80085ae: 2b00 cmp r3, #0 80085b0: d0c3 beq.n 800853a <_vfiprintf_r+0x14e> 80085b2: 9105 str r1, [sp, #20] 80085b4: e7c1 b.n 800853a <_vfiprintf_r+0x14e> 80085b6: fb05 2101 mla r1, r5, r1, r2 80085ba: 2301 movs r3, #1 80085bc: 4680 mov r8, r0 80085be: e7f0 b.n 80085a2 <_vfiprintf_r+0x1b6> 80085c0: ab03 add r3, sp, #12 80085c2: 9300 str r3, [sp, #0] 80085c4: 4622 mov r2, r4 80085c6: 4b13 ldr r3, [pc, #76] ; (8008614 <_vfiprintf_r+0x228>) 80085c8: a904 add r1, sp, #16 80085ca: 4630 mov r0, r6 80085cc: f7fd fd54 bl 8006078 <_printf_float> 80085d0: f1b0 3fff cmp.w r0, #4294967295 80085d4: 4681 mov r9, r0 80085d6: d1d5 bne.n 8008584 <_vfiprintf_r+0x198> 80085d8: 89a3 ldrh r3, [r4, #12] 80085da: 065b lsls r3, r3, #25 80085dc: f53f af7e bmi.w 80084dc <_vfiprintf_r+0xf0> 80085e0: 9809 ldr r0, [sp, #36] ; 0x24 80085e2: e77d b.n 80084e0 <_vfiprintf_r+0xf4> 80085e4: ab03 add r3, sp, #12 80085e6: 9300 str r3, [sp, #0] 80085e8: 4622 mov r2, r4 80085ea: 4b0a ldr r3, [pc, #40] ; (8008614 <_vfiprintf_r+0x228>) 80085ec: a904 add r1, sp, #16 80085ee: 4630 mov r0, r6 80085f0: f7fd ffee bl 80065d0 <_printf_i> 80085f4: e7ec b.n 80085d0 <_vfiprintf_r+0x1e4> 80085f6: bf00 nop 80085f8: 08008c18 .word 0x08008c18 80085fc: 08008d54 .word 0x08008d54 8008600: 08008c38 .word 0x08008c38 8008604: 08008bf8 .word 0x08008bf8 8008608: 08008d5a .word 0x08008d5a 800860c: 08008d5e .word 0x08008d5e 8008610: 08006079 .word 0x08006079 8008614: 080083c7 .word 0x080083c7 08008618 <_sbrk_r>: 8008618: b538 push {r3, r4, r5, lr} 800861a: 2300 movs r3, #0 800861c: 4c05 ldr r4, [pc, #20] ; (8008634 <_sbrk_r+0x1c>) 800861e: 4605 mov r5, r0 8008620: 4608 mov r0, r1 8008622: 6023 str r3, [r4, #0] 8008624: f7fd fbda bl 8005ddc <_sbrk> 8008628: 1c43 adds r3, r0, #1 800862a: d102 bne.n 8008632 <_sbrk_r+0x1a> 800862c: 6823 ldr r3, [r4, #0] 800862e: b103 cbz r3, 8008632 <_sbrk_r+0x1a> 8008630: 602b str r3, [r5, #0] 8008632: bd38 pop {r3, r4, r5, pc} 8008634: 20000b94 .word 0x20000b94 08008638 <__sread>: 8008638: b510 push {r4, lr} 800863a: 460c mov r4, r1 800863c: f9b1 100e ldrsh.w r1, [r1, #14] 8008640: f000 f8a8 bl 8008794 <_read_r> 8008644: 2800 cmp r0, #0 8008646: bfab itete ge 8008648: 6d63 ldrge r3, [r4, #84] ; 0x54 800864a: 89a3 ldrhlt r3, [r4, #12] 800864c: 181b addge r3, r3, r0 800864e: f423 5380 biclt.w r3, r3, #4096 ; 0x1000 8008652: bfac ite ge 8008654: 6563 strge r3, [r4, #84] ; 0x54 8008656: 81a3 strhlt r3, [r4, #12] 8008658: bd10 pop {r4, pc} 0800865a <__swrite>: 800865a: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 800865e: 461f mov r7, r3 8008660: 898b ldrh r3, [r1, #12] 8008662: 4605 mov r5, r0 8008664: 05db lsls r3, r3, #23 8008666: 460c mov r4, r1 8008668: 4616 mov r6, r2 800866a: d505 bpl.n 8008678 <__swrite+0x1e> 800866c: 2302 movs r3, #2 800866e: 2200 movs r2, #0 8008670: f9b1 100e ldrsh.w r1, [r1, #14] 8008674: f000 f868 bl 8008748 <_lseek_r> 8008678: 89a3 ldrh r3, [r4, #12] 800867a: 4632 mov r2, r6 800867c: f423 5380 bic.w r3, r3, #4096 ; 0x1000 8008680: 81a3 strh r3, [r4, #12] 8008682: f9b4 100e ldrsh.w r1, [r4, #14] 8008686: 463b mov r3, r7 8008688: 4628 mov r0, r5 800868a: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 800868e: f000 b817 b.w 80086c0 <_write_r> 08008692 <__sseek>: 8008692: b510 push {r4, lr} 8008694: 460c mov r4, r1 8008696: f9b1 100e ldrsh.w r1, [r1, #14] 800869a: f000 f855 bl 8008748 <_lseek_r> 800869e: 1c43 adds r3, r0, #1 80086a0: 89a3 ldrh r3, [r4, #12] 80086a2: bf15 itete ne 80086a4: 6560 strne r0, [r4, #84] ; 0x54 80086a6: f423 5380 biceq.w r3, r3, #4096 ; 0x1000 80086aa: f443 5380 orrne.w r3, r3, #4096 ; 0x1000 80086ae: 81a3 strheq r3, [r4, #12] 80086b0: bf18 it ne 80086b2: 81a3 strhne r3, [r4, #12] 80086b4: bd10 pop {r4, pc} 080086b6 <__sclose>: 80086b6: f9b1 100e ldrsh.w r1, [r1, #14] 80086ba: f000 b813 b.w 80086e4 <_close_r> ... 080086c0 <_write_r>: 80086c0: b538 push {r3, r4, r5, lr} 80086c2: 4605 mov r5, r0 80086c4: 4608 mov r0, r1 80086c6: 4611 mov r1, r2 80086c8: 2200 movs r2, #0 80086ca: 4c05 ldr r4, [pc, #20] ; (80086e0 <_write_r+0x20>) 80086cc: 6022 str r2, [r4, #0] 80086ce: 461a mov r2, r3 80086d0: f7fc fd34 bl 800513c <_write> 80086d4: 1c43 adds r3, r0, #1 80086d6: d102 bne.n 80086de <_write_r+0x1e> 80086d8: 6823 ldr r3, [r4, #0] 80086da: b103 cbz r3, 80086de <_write_r+0x1e> 80086dc: 602b str r3, [r5, #0] 80086de: bd38 pop {r3, r4, r5, pc} 80086e0: 20000b94 .word 0x20000b94 080086e4 <_close_r>: 80086e4: b538 push {r3, r4, r5, lr} 80086e6: 2300 movs r3, #0 80086e8: 4c05 ldr r4, [pc, #20] ; (8008700 <_close_r+0x1c>) 80086ea: 4605 mov r5, r0 80086ec: 4608 mov r0, r1 80086ee: 6023 str r3, [r4, #0] 80086f0: f7fd fb43 bl 8005d7a <_close> 80086f4: 1c43 adds r3, r0, #1 80086f6: d102 bne.n 80086fe <_close_r+0x1a> 80086f8: 6823 ldr r3, [r4, #0] 80086fa: b103 cbz r3, 80086fe <_close_r+0x1a> 80086fc: 602b str r3, [r5, #0] 80086fe: bd38 pop {r3, r4, r5, pc} 8008700: 20000b94 .word 0x20000b94 08008704 <_fstat_r>: 8008704: b538 push {r3, r4, r5, lr} 8008706: 2300 movs r3, #0 8008708: 4c06 ldr r4, [pc, #24] ; (8008724 <_fstat_r+0x20>) 800870a: 4605 mov r5, r0 800870c: 4608 mov r0, r1 800870e: 4611 mov r1, r2 8008710: 6023 str r3, [r4, #0] 8008712: f7fd fb3d bl 8005d90 <_fstat> 8008716: 1c43 adds r3, r0, #1 8008718: d102 bne.n 8008720 <_fstat_r+0x1c> 800871a: 6823 ldr r3, [r4, #0] 800871c: b103 cbz r3, 8008720 <_fstat_r+0x1c> 800871e: 602b str r3, [r5, #0] 8008720: bd38 pop {r3, r4, r5, pc} 8008722: bf00 nop 8008724: 20000b94 .word 0x20000b94 08008728 <_isatty_r>: 8008728: b538 push {r3, r4, r5, lr} 800872a: 2300 movs r3, #0 800872c: 4c05 ldr r4, [pc, #20] ; (8008744 <_isatty_r+0x1c>) 800872e: 4605 mov r5, r0 8008730: 4608 mov r0, r1 8008732: 6023 str r3, [r4, #0] 8008734: f7fd fb3b bl 8005dae <_isatty> 8008738: 1c43 adds r3, r0, #1 800873a: d102 bne.n 8008742 <_isatty_r+0x1a> 800873c: 6823 ldr r3, [r4, #0] 800873e: b103 cbz r3, 8008742 <_isatty_r+0x1a> 8008740: 602b str r3, [r5, #0] 8008742: bd38 pop {r3, r4, r5, pc} 8008744: 20000b94 .word 0x20000b94 08008748 <_lseek_r>: 8008748: b538 push {r3, r4, r5, lr} 800874a: 4605 mov r5, r0 800874c: 4608 mov r0, r1 800874e: 4611 mov r1, r2 8008750: 2200 movs r2, #0 8008752: 4c05 ldr r4, [pc, #20] ; (8008768 <_lseek_r+0x20>) 8008754: 6022 str r2, [r4, #0] 8008756: 461a mov r2, r3 8008758: f7fd fb33 bl 8005dc2 <_lseek> 800875c: 1c43 adds r3, r0, #1 800875e: d102 bne.n 8008766 <_lseek_r+0x1e> 8008760: 6823 ldr r3, [r4, #0] 8008762: b103 cbz r3, 8008766 <_lseek_r+0x1e> 8008764: 602b str r3, [r5, #0] 8008766: bd38 pop {r3, r4, r5, pc} 8008768: 20000b94 .word 0x20000b94 0800876c <__ascii_mbtowc>: 800876c: b082 sub sp, #8 800876e: b901 cbnz r1, 8008772 <__ascii_mbtowc+0x6> 8008770: a901 add r1, sp, #4 8008772: b142 cbz r2, 8008786 <__ascii_mbtowc+0x1a> 8008774: b14b cbz r3, 800878a <__ascii_mbtowc+0x1e> 8008776: 7813 ldrb r3, [r2, #0] 8008778: 600b str r3, [r1, #0] 800877a: 7812 ldrb r2, [r2, #0] 800877c: 1c10 adds r0, r2, #0 800877e: bf18 it ne 8008780: 2001 movne r0, #1 8008782: b002 add sp, #8 8008784: 4770 bx lr 8008786: 4610 mov r0, r2 8008788: e7fb b.n 8008782 <__ascii_mbtowc+0x16> 800878a: f06f 0001 mvn.w r0, #1 800878e: e7f8 b.n 8008782 <__ascii_mbtowc+0x16> 08008790 <__malloc_lock>: 8008790: 4770 bx lr 08008792 <__malloc_unlock>: 8008792: 4770 bx lr 08008794 <_read_r>: 8008794: b538 push {r3, r4, r5, lr} 8008796: 4605 mov r5, r0 8008798: 4608 mov r0, r1 800879a: 4611 mov r1, r2 800879c: 2200 movs r2, #0 800879e: 4c05 ldr r4, [pc, #20] ; (80087b4 <_read_r+0x20>) 80087a0: 6022 str r2, [r4, #0] 80087a2: 461a mov r2, r3 80087a4: f7fd facc bl 8005d40 <_read> 80087a8: 1c43 adds r3, r0, #1 80087aa: d102 bne.n 80087b2 <_read_r+0x1e> 80087ac: 6823 ldr r3, [r4, #0] 80087ae: b103 cbz r3, 80087b2 <_read_r+0x1e> 80087b0: 602b str r3, [r5, #0] 80087b2: bd38 pop {r3, r4, r5, pc} 80087b4: 20000b94 .word 0x20000b94 080087b8 <__ascii_wctomb>: 80087b8: b149 cbz r1, 80087ce <__ascii_wctomb+0x16> 80087ba: 2aff cmp r2, #255 ; 0xff 80087bc: bf8b itete hi 80087be: 238a movhi r3, #138 ; 0x8a 80087c0: 700a strbls r2, [r1, #0] 80087c2: 6003 strhi r3, [r0, #0] 80087c4: 2001 movls r0, #1 80087c6: bf88 it hi 80087c8: f04f 30ff movhi.w r0, #4294967295 80087cc: 4770 bx lr 80087ce: 4608 mov r0, r1 80087d0: 4770 bx lr ... 080087d4 <_init>: 80087d4: b5f8 push {r3, r4, r5, r6, r7, lr} 80087d6: bf00 nop 80087d8: bcf8 pop {r3, r4, r5, r6, r7} 80087da: bc08 pop {r3} 80087dc: 469e mov lr, r3 80087de: 4770 bx lr 080087e0 <_fini>: 80087e0: b5f8 push {r3, r4, r5, r6, r7, lr} 80087e2: bf00 nop 80087e4: bcf8 pop {r3, r4, r5, r6, r7} 80087e6: bc08 pop {r3} 80087e8: 469e mov lr, r3 80087ea: 4770 bx lr