Nesslab_200M_System.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000001d0 08000000 08000000 00010000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 00008784 080001d0 080001d0 000101d0 2**3 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000670 08008958 08008958 00018958 2**3 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 08008fc8 08008fc8 000201dc 2**0 CONTENTS 4 .ARM 00000000 08008fc8 08008fc8 000201dc 2**0 CONTENTS 5 .preinit_array 00000000 08008fc8 08008fc8 000201dc 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 08008fc8 08008fc8 00018fc8 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .fini_array 00000004 08008fcc 08008fcc 00018fcc 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .data 000001dc 20000000 08008fd0 00020000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 000009b8 200001e0 080091ac 000201e0 2**3 ALLOC 10 ._user_heap_stack 00000600 20000b98 080091ac 00020b98 2**0 ALLOC 11 .ARM.attributes 00000029 00000000 00000000 000201dc 2**0 CONTENTS, READONLY 12 .debug_info 000147e5 00000000 00000000 00020205 2**0 CONTENTS, READONLY, DEBUGGING 13 .debug_abbrev 00003669 00000000 00000000 000349ea 2**0 CONTENTS, READONLY, DEBUGGING 14 .debug_aranges 00001160 00000000 00000000 00038058 2**3 CONTENTS, READONLY, DEBUGGING 15 .debug_ranges 00000fb8 00000000 00000000 000391b8 2**3 CONTENTS, READONLY, DEBUGGING 16 .debug_macro 00010efd 00000000 00000000 0003a170 2**0 CONTENTS, READONLY, DEBUGGING 17 .debug_line 0000f594 00000000 00000000 0004b06d 2**0 CONTENTS, READONLY, DEBUGGING 18 .debug_str 000587b4 00000000 00000000 0005a601 2**0 CONTENTS, READONLY, DEBUGGING 19 .comment 0000007b 00000000 00000000 000b2db5 2**0 CONTENTS, READONLY 20 .debug_frame 00005490 00000000 00000000 000b2e30 2**2 CONTENTS, READONLY, DEBUGGING Disassembly of section .text: 080001d0 <__do_global_dtors_aux>: 80001d0: b510 push {r4, lr} 80001d2: 4c05 ldr r4, [pc, #20] ; (80001e8 <__do_global_dtors_aux+0x18>) 80001d4: 7823 ldrb r3, [r4, #0] 80001d6: b933 cbnz r3, 80001e6 <__do_global_dtors_aux+0x16> 80001d8: 4b04 ldr r3, [pc, #16] ; (80001ec <__do_global_dtors_aux+0x1c>) 80001da: b113 cbz r3, 80001e2 <__do_global_dtors_aux+0x12> 80001dc: 4804 ldr r0, [pc, #16] ; (80001f0 <__do_global_dtors_aux+0x20>) 80001de: f3af 8000 nop.w 80001e2: 2301 movs r3, #1 80001e4: 7023 strb r3, [r4, #0] 80001e6: bd10 pop {r4, pc} 80001e8: 200001e0 .word 0x200001e0 80001ec: 00000000 .word 0x00000000 80001f0: 0800893c .word 0x0800893c 080001f4 : 80001f4: b508 push {r3, lr} 80001f6: 4b03 ldr r3, [pc, #12] ; (8000204 ) 80001f8: b11b cbz r3, 8000202 80001fa: 4903 ldr r1, [pc, #12] ; (8000208 ) 80001fc: 4803 ldr r0, [pc, #12] ; (800020c ) 80001fe: f3af 8000 nop.w 8000202: bd08 pop {r3, pc} 8000204: 00000000 .word 0x00000000 8000208: 200001e4 .word 0x200001e4 800020c: 0800893c .word 0x0800893c 08000210 : 8000210: 4603 mov r3, r0 8000212: f813 2b01 ldrb.w r2, [r3], #1 8000216: 2a00 cmp r2, #0 8000218: d1fb bne.n 8000212 800021a: 1a18 subs r0, r3, r0 800021c: 3801 subs r0, #1 800021e: 4770 bx lr 08000220 <__aeabi_drsub>: 8000220: f081 4100 eor.w r1, r1, #2147483648 ; 0x80000000 8000224: e002 b.n 800022c <__adddf3> 8000226: bf00 nop 08000228 <__aeabi_dsub>: 8000228: f083 4300 eor.w r3, r3, #2147483648 ; 0x80000000 0800022c <__adddf3>: 800022c: b530 push {r4, r5, lr} 800022e: ea4f 0441 mov.w r4, r1, lsl #1 8000232: ea4f 0543 mov.w r5, r3, lsl #1 8000236: ea94 0f05 teq r4, r5 800023a: bf08 it eq 800023c: ea90 0f02 teqeq r0, r2 8000240: bf1f itttt ne 8000242: ea54 0c00 orrsne.w ip, r4, r0 8000246: ea55 0c02 orrsne.w ip, r5, r2 800024a: ea7f 5c64 mvnsne.w ip, r4, asr #21 800024e: ea7f 5c65 mvnsne.w ip, r5, asr #21 8000252: f000 80e2 beq.w 800041a <__adddf3+0x1ee> 8000256: ea4f 5454 mov.w r4, r4, lsr #21 800025a: ebd4 5555 rsbs r5, r4, r5, lsr #21 800025e: bfb8 it lt 8000260: 426d neglt r5, r5 8000262: dd0c ble.n 800027e <__adddf3+0x52> 8000264: 442c add r4, r5 8000266: ea80 0202 eor.w r2, r0, r2 800026a: ea81 0303 eor.w r3, r1, r3 800026e: ea82 0000 eor.w r0, r2, r0 8000272: ea83 0101 eor.w r1, r3, r1 8000276: ea80 0202 eor.w r2, r0, r2 800027a: ea81 0303 eor.w r3, r1, r3 800027e: 2d36 cmp r5, #54 ; 0x36 8000280: bf88 it hi 8000282: bd30 pophi {r4, r5, pc} 8000284: f011 4f00 tst.w r1, #2147483648 ; 0x80000000 8000288: ea4f 3101 mov.w r1, r1, lsl #12 800028c: f44f 1c80 mov.w ip, #1048576 ; 0x100000 8000290: ea4c 3111 orr.w r1, ip, r1, lsr #12 8000294: d002 beq.n 800029c <__adddf3+0x70> 8000296: 4240 negs r0, r0 8000298: eb61 0141 sbc.w r1, r1, r1, lsl #1 800029c: f013 4f00 tst.w r3, #2147483648 ; 0x80000000 80002a0: ea4f 3303 mov.w r3, r3, lsl #12 80002a4: ea4c 3313 orr.w r3, ip, r3, lsr #12 80002a8: d002 beq.n 80002b0 <__adddf3+0x84> 80002aa: 4252 negs r2, r2 80002ac: eb63 0343 sbc.w r3, r3, r3, lsl #1 80002b0: ea94 0f05 teq r4, r5 80002b4: f000 80a7 beq.w 8000406 <__adddf3+0x1da> 80002b8: f1a4 0401 sub.w r4, r4, #1 80002bc: f1d5 0e20 rsbs lr, r5, #32 80002c0: db0d blt.n 80002de <__adddf3+0xb2> 80002c2: fa02 fc0e lsl.w ip, r2, lr 80002c6: fa22 f205 lsr.w r2, r2, r5 80002ca: 1880 adds r0, r0, r2 80002cc: f141 0100 adc.w r1, r1, #0 80002d0: fa03 f20e lsl.w r2, r3, lr 80002d4: 1880 adds r0, r0, r2 80002d6: fa43 f305 asr.w r3, r3, r5 80002da: 4159 adcs r1, r3 80002dc: e00e b.n 80002fc <__adddf3+0xd0> 80002de: f1a5 0520 sub.w r5, r5, #32 80002e2: f10e 0e20 add.w lr, lr, #32 80002e6: 2a01 cmp r2, #1 80002e8: fa03 fc0e lsl.w ip, r3, lr 80002ec: bf28 it cs 80002ee: f04c 0c02 orrcs.w ip, ip, #2 80002f2: fa43 f305 asr.w r3, r3, r5 80002f6: 18c0 adds r0, r0, r3 80002f8: eb51 71e3 adcs.w r1, r1, r3, asr #31 80002fc: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 8000300: d507 bpl.n 8000312 <__adddf3+0xe6> 8000302: f04f 0e00 mov.w lr, #0 8000306: f1dc 0c00 rsbs ip, ip, #0 800030a: eb7e 0000 sbcs.w r0, lr, r0 800030e: eb6e 0101 sbc.w r1, lr, r1 8000312: f5b1 1f80 cmp.w r1, #1048576 ; 0x100000 8000316: d31b bcc.n 8000350 <__adddf3+0x124> 8000318: f5b1 1f00 cmp.w r1, #2097152 ; 0x200000 800031c: d30c bcc.n 8000338 <__adddf3+0x10c> 800031e: 0849 lsrs r1, r1, #1 8000320: ea5f 0030 movs.w r0, r0, rrx 8000324: ea4f 0c3c mov.w ip, ip, rrx 8000328: f104 0401 add.w r4, r4, #1 800032c: ea4f 5244 mov.w r2, r4, lsl #21 8000330: f512 0f80 cmn.w r2, #4194304 ; 0x400000 8000334: f080 809a bcs.w 800046c <__adddf3+0x240> 8000338: f1bc 4f00 cmp.w ip, #2147483648 ; 0x80000000 800033c: bf08 it eq 800033e: ea5f 0c50 movseq.w ip, r0, lsr #1 8000342: f150 0000 adcs.w r0, r0, #0 8000346: eb41 5104 adc.w r1, r1, r4, lsl #20 800034a: ea41 0105 orr.w r1, r1, r5 800034e: bd30 pop {r4, r5, pc} 8000350: ea5f 0c4c movs.w ip, ip, lsl #1 8000354: 4140 adcs r0, r0 8000356: eb41 0101 adc.w r1, r1, r1 800035a: f411 1f80 tst.w r1, #1048576 ; 0x100000 800035e: f1a4 0401 sub.w r4, r4, #1 8000362: d1e9 bne.n 8000338 <__adddf3+0x10c> 8000364: f091 0f00 teq r1, #0 8000368: bf04 itt eq 800036a: 4601 moveq r1, r0 800036c: 2000 moveq r0, #0 800036e: fab1 f381 clz r3, r1 8000372: bf08 it eq 8000374: 3320 addeq r3, #32 8000376: f1a3 030b sub.w r3, r3, #11 800037a: f1b3 0220 subs.w r2, r3, #32 800037e: da0c bge.n 800039a <__adddf3+0x16e> 8000380: 320c adds r2, #12 8000382: dd08 ble.n 8000396 <__adddf3+0x16a> 8000384: f102 0c14 add.w ip, r2, #20 8000388: f1c2 020c rsb r2, r2, #12 800038c: fa01 f00c lsl.w r0, r1, ip 8000390: fa21 f102 lsr.w r1, r1, r2 8000394: e00c b.n 80003b0 <__adddf3+0x184> 8000396: f102 0214 add.w r2, r2, #20 800039a: bfd8 it le 800039c: f1c2 0c20 rsble ip, r2, #32 80003a0: fa01 f102 lsl.w r1, r1, r2 80003a4: fa20 fc0c lsr.w ip, r0, ip 80003a8: bfdc itt le 80003aa: ea41 010c orrle.w r1, r1, ip 80003ae: 4090 lslle r0, r2 80003b0: 1ae4 subs r4, r4, r3 80003b2: bfa2 ittt ge 80003b4: eb01 5104 addge.w r1, r1, r4, lsl #20 80003b8: 4329 orrge r1, r5 80003ba: bd30 popge {r4, r5, pc} 80003bc: ea6f 0404 mvn.w r4, r4 80003c0: 3c1f subs r4, #31 80003c2: da1c bge.n 80003fe <__adddf3+0x1d2> 80003c4: 340c adds r4, #12 80003c6: dc0e bgt.n 80003e6 <__adddf3+0x1ba> 80003c8: f104 0414 add.w r4, r4, #20 80003cc: f1c4 0220 rsb r2, r4, #32 80003d0: fa20 f004 lsr.w r0, r0, r4 80003d4: fa01 f302 lsl.w r3, r1, r2 80003d8: ea40 0003 orr.w r0, r0, r3 80003dc: fa21 f304 lsr.w r3, r1, r4 80003e0: ea45 0103 orr.w r1, r5, r3 80003e4: bd30 pop {r4, r5, pc} 80003e6: f1c4 040c rsb r4, r4, #12 80003ea: f1c4 0220 rsb r2, r4, #32 80003ee: fa20 f002 lsr.w r0, r0, r2 80003f2: fa01 f304 lsl.w r3, r1, r4 80003f6: ea40 0003 orr.w r0, r0, r3 80003fa: 4629 mov r1, r5 80003fc: bd30 pop {r4, r5, pc} 80003fe: fa21 f004 lsr.w r0, r1, r4 8000402: 4629 mov r1, r5 8000404: bd30 pop {r4, r5, pc} 8000406: f094 0f00 teq r4, #0 800040a: f483 1380 eor.w r3, r3, #1048576 ; 0x100000 800040e: bf06 itte eq 8000410: f481 1180 eoreq.w r1, r1, #1048576 ; 0x100000 8000414: 3401 addeq r4, #1 8000416: 3d01 subne r5, #1 8000418: e74e b.n 80002b8 <__adddf3+0x8c> 800041a: ea7f 5c64 mvns.w ip, r4, asr #21 800041e: bf18 it ne 8000420: ea7f 5c65 mvnsne.w ip, r5, asr #21 8000424: d029 beq.n 800047a <__adddf3+0x24e> 8000426: ea94 0f05 teq r4, r5 800042a: bf08 it eq 800042c: ea90 0f02 teqeq r0, r2 8000430: d005 beq.n 800043e <__adddf3+0x212> 8000432: ea54 0c00 orrs.w ip, r4, r0 8000436: bf04 itt eq 8000438: 4619 moveq r1, r3 800043a: 4610 moveq r0, r2 800043c: bd30 pop {r4, r5, pc} 800043e: ea91 0f03 teq r1, r3 8000442: bf1e ittt ne 8000444: 2100 movne r1, #0 8000446: 2000 movne r0, #0 8000448: bd30 popne {r4, r5, pc} 800044a: ea5f 5c54 movs.w ip, r4, lsr #21 800044e: d105 bne.n 800045c <__adddf3+0x230> 8000450: 0040 lsls r0, r0, #1 8000452: 4149 adcs r1, r1 8000454: bf28 it cs 8000456: f041 4100 orrcs.w r1, r1, #2147483648 ; 0x80000000 800045a: bd30 pop {r4, r5, pc} 800045c: f514 0480 adds.w r4, r4, #4194304 ; 0x400000 8000460: bf3c itt cc 8000462: f501 1180 addcc.w r1, r1, #1048576 ; 0x100000 8000466: bd30 popcc {r4, r5, pc} 8000468: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 800046c: f045 41fe orr.w r1, r5, #2130706432 ; 0x7f000000 8000470: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000 8000474: f04f 0000 mov.w r0, #0 8000478: bd30 pop {r4, r5, pc} 800047a: ea7f 5c64 mvns.w ip, r4, asr #21 800047e: bf1a itte ne 8000480: 4619 movne r1, r3 8000482: 4610 movne r0, r2 8000484: ea7f 5c65 mvnseq.w ip, r5, asr #21 8000488: bf1c itt ne 800048a: 460b movne r3, r1 800048c: 4602 movne r2, r0 800048e: ea50 3401 orrs.w r4, r0, r1, lsl #12 8000492: bf06 itte eq 8000494: ea52 3503 orrseq.w r5, r2, r3, lsl #12 8000498: ea91 0f03 teqeq r1, r3 800049c: f441 2100 orrne.w r1, r1, #524288 ; 0x80000 80004a0: bd30 pop {r4, r5, pc} 80004a2: bf00 nop 080004a4 <__aeabi_ui2d>: 80004a4: f090 0f00 teq r0, #0 80004a8: bf04 itt eq 80004aa: 2100 moveq r1, #0 80004ac: 4770 bxeq lr 80004ae: b530 push {r4, r5, lr} 80004b0: f44f 6480 mov.w r4, #1024 ; 0x400 80004b4: f104 0432 add.w r4, r4, #50 ; 0x32 80004b8: f04f 0500 mov.w r5, #0 80004bc: f04f 0100 mov.w r1, #0 80004c0: e750 b.n 8000364 <__adddf3+0x138> 80004c2: bf00 nop 080004c4 <__aeabi_i2d>: 80004c4: f090 0f00 teq r0, #0 80004c8: bf04 itt eq 80004ca: 2100 moveq r1, #0 80004cc: 4770 bxeq lr 80004ce: b530 push {r4, r5, lr} 80004d0: f44f 6480 mov.w r4, #1024 ; 0x400 80004d4: f104 0432 add.w r4, r4, #50 ; 0x32 80004d8: f010 4500 ands.w r5, r0, #2147483648 ; 0x80000000 80004dc: bf48 it mi 80004de: 4240 negmi r0, r0 80004e0: f04f 0100 mov.w r1, #0 80004e4: e73e b.n 8000364 <__adddf3+0x138> 80004e6: bf00 nop 080004e8 <__aeabi_f2d>: 80004e8: 0042 lsls r2, r0, #1 80004ea: ea4f 01e2 mov.w r1, r2, asr #3 80004ee: ea4f 0131 mov.w r1, r1, rrx 80004f2: ea4f 7002 mov.w r0, r2, lsl #28 80004f6: bf1f itttt ne 80004f8: f012 437f andsne.w r3, r2, #4278190080 ; 0xff000000 80004fc: f093 4f7f teqne r3, #4278190080 ; 0xff000000 8000500: f081 5160 eorne.w r1, r1, #939524096 ; 0x38000000 8000504: 4770 bxne lr 8000506: f032 427f bics.w r2, r2, #4278190080 ; 0xff000000 800050a: bf08 it eq 800050c: 4770 bxeq lr 800050e: f093 4f7f teq r3, #4278190080 ; 0xff000000 8000512: bf04 itt eq 8000514: f441 2100 orreq.w r1, r1, #524288 ; 0x80000 8000518: 4770 bxeq lr 800051a: b530 push {r4, r5, lr} 800051c: f44f 7460 mov.w r4, #896 ; 0x380 8000520: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 8000524: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000 8000528: e71c b.n 8000364 <__adddf3+0x138> 800052a: bf00 nop 0800052c <__aeabi_ul2d>: 800052c: ea50 0201 orrs.w r2, r0, r1 8000530: bf08 it eq 8000532: 4770 bxeq lr 8000534: b530 push {r4, r5, lr} 8000536: f04f 0500 mov.w r5, #0 800053a: e00a b.n 8000552 <__aeabi_l2d+0x16> 0800053c <__aeabi_l2d>: 800053c: ea50 0201 orrs.w r2, r0, r1 8000540: bf08 it eq 8000542: 4770 bxeq lr 8000544: b530 push {r4, r5, lr} 8000546: f011 4500 ands.w r5, r1, #2147483648 ; 0x80000000 800054a: d502 bpl.n 8000552 <__aeabi_l2d+0x16> 800054c: 4240 negs r0, r0 800054e: eb61 0141 sbc.w r1, r1, r1, lsl #1 8000552: f44f 6480 mov.w r4, #1024 ; 0x400 8000556: f104 0432 add.w r4, r4, #50 ; 0x32 800055a: ea5f 5c91 movs.w ip, r1, lsr #22 800055e: f43f aed8 beq.w 8000312 <__adddf3+0xe6> 8000562: f04f 0203 mov.w r2, #3 8000566: ea5f 0cdc movs.w ip, ip, lsr #3 800056a: bf18 it ne 800056c: 3203 addne r2, #3 800056e: ea5f 0cdc movs.w ip, ip, lsr #3 8000572: bf18 it ne 8000574: 3203 addne r2, #3 8000576: eb02 02dc add.w r2, r2, ip, lsr #3 800057a: f1c2 0320 rsb r3, r2, #32 800057e: fa00 fc03 lsl.w ip, r0, r3 8000582: fa20 f002 lsr.w r0, r0, r2 8000586: fa01 fe03 lsl.w lr, r1, r3 800058a: ea40 000e orr.w r0, r0, lr 800058e: fa21 f102 lsr.w r1, r1, r2 8000592: 4414 add r4, r2 8000594: e6bd b.n 8000312 <__adddf3+0xe6> 8000596: bf00 nop 08000598 <__aeabi_dmul>: 8000598: b570 push {r4, r5, r6, lr} 800059a: f04f 0cff mov.w ip, #255 ; 0xff 800059e: f44c 6ce0 orr.w ip, ip, #1792 ; 0x700 80005a2: ea1c 5411 ands.w r4, ip, r1, lsr #20 80005a6: bf1d ittte ne 80005a8: ea1c 5513 andsne.w r5, ip, r3, lsr #20 80005ac: ea94 0f0c teqne r4, ip 80005b0: ea95 0f0c teqne r5, ip 80005b4: f000 f8de bleq 8000774 <__aeabi_dmul+0x1dc> 80005b8: 442c add r4, r5 80005ba: ea81 0603 eor.w r6, r1, r3 80005be: ea21 514c bic.w r1, r1, ip, lsl #21 80005c2: ea23 534c bic.w r3, r3, ip, lsl #21 80005c6: ea50 3501 orrs.w r5, r0, r1, lsl #12 80005ca: bf18 it ne 80005cc: ea52 3503 orrsne.w r5, r2, r3, lsl #12 80005d0: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 80005d4: f443 1380 orr.w r3, r3, #1048576 ; 0x100000 80005d8: d038 beq.n 800064c <__aeabi_dmul+0xb4> 80005da: fba0 ce02 umull ip, lr, r0, r2 80005de: f04f 0500 mov.w r5, #0 80005e2: fbe1 e502 umlal lr, r5, r1, r2 80005e6: f006 4200 and.w r2, r6, #2147483648 ; 0x80000000 80005ea: fbe0 e503 umlal lr, r5, r0, r3 80005ee: f04f 0600 mov.w r6, #0 80005f2: fbe1 5603 umlal r5, r6, r1, r3 80005f6: f09c 0f00 teq ip, #0 80005fa: bf18 it ne 80005fc: f04e 0e01 orrne.w lr, lr, #1 8000600: f1a4 04ff sub.w r4, r4, #255 ; 0xff 8000604: f5b6 7f00 cmp.w r6, #512 ; 0x200 8000608: f564 7440 sbc.w r4, r4, #768 ; 0x300 800060c: d204 bcs.n 8000618 <__aeabi_dmul+0x80> 800060e: ea5f 0e4e movs.w lr, lr, lsl #1 8000612: 416d adcs r5, r5 8000614: eb46 0606 adc.w r6, r6, r6 8000618: ea42 21c6 orr.w r1, r2, r6, lsl #11 800061c: ea41 5155 orr.w r1, r1, r5, lsr #21 8000620: ea4f 20c5 mov.w r0, r5, lsl #11 8000624: ea40 505e orr.w r0, r0, lr, lsr #21 8000628: ea4f 2ece mov.w lr, lr, lsl #11 800062c: f1b4 0cfd subs.w ip, r4, #253 ; 0xfd 8000630: bf88 it hi 8000632: f5bc 6fe0 cmphi.w ip, #1792 ; 0x700 8000636: d81e bhi.n 8000676 <__aeabi_dmul+0xde> 8000638: f1be 4f00 cmp.w lr, #2147483648 ; 0x80000000 800063c: bf08 it eq 800063e: ea5f 0e50 movseq.w lr, r0, lsr #1 8000642: f150 0000 adcs.w r0, r0, #0 8000646: eb41 5104 adc.w r1, r1, r4, lsl #20 800064a: bd70 pop {r4, r5, r6, pc} 800064c: f006 4600 and.w r6, r6, #2147483648 ; 0x80000000 8000650: ea46 0101 orr.w r1, r6, r1 8000654: ea40 0002 orr.w r0, r0, r2 8000658: ea81 0103 eor.w r1, r1, r3 800065c: ebb4 045c subs.w r4, r4, ip, lsr #1 8000660: bfc2 ittt gt 8000662: ebd4 050c rsbsgt r5, r4, ip 8000666: ea41 5104 orrgt.w r1, r1, r4, lsl #20 800066a: bd70 popgt {r4, r5, r6, pc} 800066c: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 8000670: f04f 0e00 mov.w lr, #0 8000674: 3c01 subs r4, #1 8000676: f300 80ab bgt.w 80007d0 <__aeabi_dmul+0x238> 800067a: f114 0f36 cmn.w r4, #54 ; 0x36 800067e: bfde ittt le 8000680: 2000 movle r0, #0 8000682: f001 4100 andle.w r1, r1, #2147483648 ; 0x80000000 8000686: bd70 pople {r4, r5, r6, pc} 8000688: f1c4 0400 rsb r4, r4, #0 800068c: 3c20 subs r4, #32 800068e: da35 bge.n 80006fc <__aeabi_dmul+0x164> 8000690: 340c adds r4, #12 8000692: dc1b bgt.n 80006cc <__aeabi_dmul+0x134> 8000694: f104 0414 add.w r4, r4, #20 8000698: f1c4 0520 rsb r5, r4, #32 800069c: fa00 f305 lsl.w r3, r0, r5 80006a0: fa20 f004 lsr.w r0, r0, r4 80006a4: fa01 f205 lsl.w r2, r1, r5 80006a8: ea40 0002 orr.w r0, r0, r2 80006ac: f001 4200 and.w r2, r1, #2147483648 ; 0x80000000 80006b0: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000 80006b4: eb10 70d3 adds.w r0, r0, r3, lsr #31 80006b8: fa21 f604 lsr.w r6, r1, r4 80006bc: eb42 0106 adc.w r1, r2, r6 80006c0: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 80006c4: bf08 it eq 80006c6: ea20 70d3 biceq.w r0, r0, r3, lsr #31 80006ca: bd70 pop {r4, r5, r6, pc} 80006cc: f1c4 040c rsb r4, r4, #12 80006d0: f1c4 0520 rsb r5, r4, #32 80006d4: fa00 f304 lsl.w r3, r0, r4 80006d8: fa20 f005 lsr.w r0, r0, r5 80006dc: fa01 f204 lsl.w r2, r1, r4 80006e0: ea40 0002 orr.w r0, r0, r2 80006e4: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 80006e8: eb10 70d3 adds.w r0, r0, r3, lsr #31 80006ec: f141 0100 adc.w r1, r1, #0 80006f0: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 80006f4: bf08 it eq 80006f6: ea20 70d3 biceq.w r0, r0, r3, lsr #31 80006fa: bd70 pop {r4, r5, r6, pc} 80006fc: f1c4 0520 rsb r5, r4, #32 8000700: fa00 f205 lsl.w r2, r0, r5 8000704: ea4e 0e02 orr.w lr, lr, r2 8000708: fa20 f304 lsr.w r3, r0, r4 800070c: fa01 f205 lsl.w r2, r1, r5 8000710: ea43 0302 orr.w r3, r3, r2 8000714: fa21 f004 lsr.w r0, r1, r4 8000718: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 800071c: fa21 f204 lsr.w r2, r1, r4 8000720: ea20 0002 bic.w r0, r0, r2 8000724: eb00 70d3 add.w r0, r0, r3, lsr #31 8000728: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 800072c: bf08 it eq 800072e: ea20 70d3 biceq.w r0, r0, r3, lsr #31 8000732: bd70 pop {r4, r5, r6, pc} 8000734: f094 0f00 teq r4, #0 8000738: d10f bne.n 800075a <__aeabi_dmul+0x1c2> 800073a: f001 4600 and.w r6, r1, #2147483648 ; 0x80000000 800073e: 0040 lsls r0, r0, #1 8000740: eb41 0101 adc.w r1, r1, r1 8000744: f411 1f80 tst.w r1, #1048576 ; 0x100000 8000748: bf08 it eq 800074a: 3c01 subeq r4, #1 800074c: d0f7 beq.n 800073e <__aeabi_dmul+0x1a6> 800074e: ea41 0106 orr.w r1, r1, r6 8000752: f095 0f00 teq r5, #0 8000756: bf18 it ne 8000758: 4770 bxne lr 800075a: f003 4600 and.w r6, r3, #2147483648 ; 0x80000000 800075e: 0052 lsls r2, r2, #1 8000760: eb43 0303 adc.w r3, r3, r3 8000764: f413 1f80 tst.w r3, #1048576 ; 0x100000 8000768: bf08 it eq 800076a: 3d01 subeq r5, #1 800076c: d0f7 beq.n 800075e <__aeabi_dmul+0x1c6> 800076e: ea43 0306 orr.w r3, r3, r6 8000772: 4770 bx lr 8000774: ea94 0f0c teq r4, ip 8000778: ea0c 5513 and.w r5, ip, r3, lsr #20 800077c: bf18 it ne 800077e: ea95 0f0c teqne r5, ip 8000782: d00c beq.n 800079e <__aeabi_dmul+0x206> 8000784: ea50 0641 orrs.w r6, r0, r1, lsl #1 8000788: bf18 it ne 800078a: ea52 0643 orrsne.w r6, r2, r3, lsl #1 800078e: d1d1 bne.n 8000734 <__aeabi_dmul+0x19c> 8000790: ea81 0103 eor.w r1, r1, r3 8000794: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 8000798: f04f 0000 mov.w r0, #0 800079c: bd70 pop {r4, r5, r6, pc} 800079e: ea50 0641 orrs.w r6, r0, r1, lsl #1 80007a2: bf06 itte eq 80007a4: 4610 moveq r0, r2 80007a6: 4619 moveq r1, r3 80007a8: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80007ac: d019 beq.n 80007e2 <__aeabi_dmul+0x24a> 80007ae: ea94 0f0c teq r4, ip 80007b2: d102 bne.n 80007ba <__aeabi_dmul+0x222> 80007b4: ea50 3601 orrs.w r6, r0, r1, lsl #12 80007b8: d113 bne.n 80007e2 <__aeabi_dmul+0x24a> 80007ba: ea95 0f0c teq r5, ip 80007be: d105 bne.n 80007cc <__aeabi_dmul+0x234> 80007c0: ea52 3603 orrs.w r6, r2, r3, lsl #12 80007c4: bf1c itt ne 80007c6: 4610 movne r0, r2 80007c8: 4619 movne r1, r3 80007ca: d10a bne.n 80007e2 <__aeabi_dmul+0x24a> 80007cc: ea81 0103 eor.w r1, r1, r3 80007d0: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 80007d4: f041 41fe orr.w r1, r1, #2130706432 ; 0x7f000000 80007d8: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000 80007dc: f04f 0000 mov.w r0, #0 80007e0: bd70 pop {r4, r5, r6, pc} 80007e2: f041 41fe orr.w r1, r1, #2130706432 ; 0x7f000000 80007e6: f441 0178 orr.w r1, r1, #16252928 ; 0xf80000 80007ea: bd70 pop {r4, r5, r6, pc} 080007ec <__aeabi_ddiv>: 80007ec: b570 push {r4, r5, r6, lr} 80007ee: f04f 0cff mov.w ip, #255 ; 0xff 80007f2: f44c 6ce0 orr.w ip, ip, #1792 ; 0x700 80007f6: ea1c 5411 ands.w r4, ip, r1, lsr #20 80007fa: bf1d ittte ne 80007fc: ea1c 5513 andsne.w r5, ip, r3, lsr #20 8000800: ea94 0f0c teqne r4, ip 8000804: ea95 0f0c teqne r5, ip 8000808: f000 f8a7 bleq 800095a <__aeabi_ddiv+0x16e> 800080c: eba4 0405 sub.w r4, r4, r5 8000810: ea81 0e03 eor.w lr, r1, r3 8000814: ea52 3503 orrs.w r5, r2, r3, lsl #12 8000818: ea4f 3101 mov.w r1, r1, lsl #12 800081c: f000 8088 beq.w 8000930 <__aeabi_ddiv+0x144> 8000820: ea4f 3303 mov.w r3, r3, lsl #12 8000824: f04f 5580 mov.w r5, #268435456 ; 0x10000000 8000828: ea45 1313 orr.w r3, r5, r3, lsr #4 800082c: ea43 6312 orr.w r3, r3, r2, lsr #24 8000830: ea4f 2202 mov.w r2, r2, lsl #8 8000834: ea45 1511 orr.w r5, r5, r1, lsr #4 8000838: ea45 6510 orr.w r5, r5, r0, lsr #24 800083c: ea4f 2600 mov.w r6, r0, lsl #8 8000840: f00e 4100 and.w r1, lr, #2147483648 ; 0x80000000 8000844: 429d cmp r5, r3 8000846: bf08 it eq 8000848: 4296 cmpeq r6, r2 800084a: f144 04fd adc.w r4, r4, #253 ; 0xfd 800084e: f504 7440 add.w r4, r4, #768 ; 0x300 8000852: d202 bcs.n 800085a <__aeabi_ddiv+0x6e> 8000854: 085b lsrs r3, r3, #1 8000856: ea4f 0232 mov.w r2, r2, rrx 800085a: 1ab6 subs r6, r6, r2 800085c: eb65 0503 sbc.w r5, r5, r3 8000860: 085b lsrs r3, r3, #1 8000862: ea4f 0232 mov.w r2, r2, rrx 8000866: f44f 1080 mov.w r0, #1048576 ; 0x100000 800086a: f44f 2c00 mov.w ip, #524288 ; 0x80000 800086e: ebb6 0e02 subs.w lr, r6, r2 8000872: eb75 0e03 sbcs.w lr, r5, r3 8000876: bf22 ittt cs 8000878: 1ab6 subcs r6, r6, r2 800087a: 4675 movcs r5, lr 800087c: ea40 000c orrcs.w r0, r0, ip 8000880: 085b lsrs r3, r3, #1 8000882: ea4f 0232 mov.w r2, r2, rrx 8000886: ebb6 0e02 subs.w lr, r6, r2 800088a: eb75 0e03 sbcs.w lr, r5, r3 800088e: bf22 ittt cs 8000890: 1ab6 subcs r6, r6, r2 8000892: 4675 movcs r5, lr 8000894: ea40 005c orrcs.w r0, r0, ip, lsr #1 8000898: 085b lsrs r3, r3, #1 800089a: ea4f 0232 mov.w r2, r2, rrx 800089e: ebb6 0e02 subs.w lr, r6, r2 80008a2: eb75 0e03 sbcs.w lr, r5, r3 80008a6: bf22 ittt cs 80008a8: 1ab6 subcs r6, r6, r2 80008aa: 4675 movcs r5, lr 80008ac: ea40 009c orrcs.w r0, r0, ip, lsr #2 80008b0: 085b lsrs r3, r3, #1 80008b2: ea4f 0232 mov.w r2, r2, rrx 80008b6: ebb6 0e02 subs.w lr, r6, r2 80008ba: eb75 0e03 sbcs.w lr, r5, r3 80008be: bf22 ittt cs 80008c0: 1ab6 subcs r6, r6, r2 80008c2: 4675 movcs r5, lr 80008c4: ea40 00dc orrcs.w r0, r0, ip, lsr #3 80008c8: ea55 0e06 orrs.w lr, r5, r6 80008cc: d018 beq.n 8000900 <__aeabi_ddiv+0x114> 80008ce: ea4f 1505 mov.w r5, r5, lsl #4 80008d2: ea45 7516 orr.w r5, r5, r6, lsr #28 80008d6: ea4f 1606 mov.w r6, r6, lsl #4 80008da: ea4f 03c3 mov.w r3, r3, lsl #3 80008de: ea43 7352 orr.w r3, r3, r2, lsr #29 80008e2: ea4f 02c2 mov.w r2, r2, lsl #3 80008e6: ea5f 1c1c movs.w ip, ip, lsr #4 80008ea: d1c0 bne.n 800086e <__aeabi_ddiv+0x82> 80008ec: f411 1f80 tst.w r1, #1048576 ; 0x100000 80008f0: d10b bne.n 800090a <__aeabi_ddiv+0x11e> 80008f2: ea41 0100 orr.w r1, r1, r0 80008f6: f04f 0000 mov.w r0, #0 80008fa: f04f 4c00 mov.w ip, #2147483648 ; 0x80000000 80008fe: e7b6 b.n 800086e <__aeabi_ddiv+0x82> 8000900: f411 1f80 tst.w r1, #1048576 ; 0x100000 8000904: bf04 itt eq 8000906: 4301 orreq r1, r0 8000908: 2000 moveq r0, #0 800090a: f1b4 0cfd subs.w ip, r4, #253 ; 0xfd 800090e: bf88 it hi 8000910: f5bc 6fe0 cmphi.w ip, #1792 ; 0x700 8000914: f63f aeaf bhi.w 8000676 <__aeabi_dmul+0xde> 8000918: ebb5 0c03 subs.w ip, r5, r3 800091c: bf04 itt eq 800091e: ebb6 0c02 subseq.w ip, r6, r2 8000922: ea5f 0c50 movseq.w ip, r0, lsr #1 8000926: f150 0000 adcs.w r0, r0, #0 800092a: eb41 5104 adc.w r1, r1, r4, lsl #20 800092e: bd70 pop {r4, r5, r6, pc} 8000930: f00e 4e00 and.w lr, lr, #2147483648 ; 0x80000000 8000934: ea4e 3111 orr.w r1, lr, r1, lsr #12 8000938: eb14 045c adds.w r4, r4, ip, lsr #1 800093c: bfc2 ittt gt 800093e: ebd4 050c rsbsgt r5, r4, ip 8000942: ea41 5104 orrgt.w r1, r1, r4, lsl #20 8000946: bd70 popgt {r4, r5, r6, pc} 8000948: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 800094c: f04f 0e00 mov.w lr, #0 8000950: 3c01 subs r4, #1 8000952: e690 b.n 8000676 <__aeabi_dmul+0xde> 8000954: ea45 0e06 orr.w lr, r5, r6 8000958: e68d b.n 8000676 <__aeabi_dmul+0xde> 800095a: ea0c 5513 and.w r5, ip, r3, lsr #20 800095e: ea94 0f0c teq r4, ip 8000962: bf08 it eq 8000964: ea95 0f0c teqeq r5, ip 8000968: f43f af3b beq.w 80007e2 <__aeabi_dmul+0x24a> 800096c: ea94 0f0c teq r4, ip 8000970: d10a bne.n 8000988 <__aeabi_ddiv+0x19c> 8000972: ea50 3401 orrs.w r4, r0, r1, lsl #12 8000976: f47f af34 bne.w 80007e2 <__aeabi_dmul+0x24a> 800097a: ea95 0f0c teq r5, ip 800097e: f47f af25 bne.w 80007cc <__aeabi_dmul+0x234> 8000982: 4610 mov r0, r2 8000984: 4619 mov r1, r3 8000986: e72c b.n 80007e2 <__aeabi_dmul+0x24a> 8000988: ea95 0f0c teq r5, ip 800098c: d106 bne.n 800099c <__aeabi_ddiv+0x1b0> 800098e: ea52 3503 orrs.w r5, r2, r3, lsl #12 8000992: f43f aefd beq.w 8000790 <__aeabi_dmul+0x1f8> 8000996: 4610 mov r0, r2 8000998: 4619 mov r1, r3 800099a: e722 b.n 80007e2 <__aeabi_dmul+0x24a> 800099c: ea50 0641 orrs.w r6, r0, r1, lsl #1 80009a0: bf18 it ne 80009a2: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80009a6: f47f aec5 bne.w 8000734 <__aeabi_dmul+0x19c> 80009aa: ea50 0441 orrs.w r4, r0, r1, lsl #1 80009ae: f47f af0d bne.w 80007cc <__aeabi_dmul+0x234> 80009b2: ea52 0543 orrs.w r5, r2, r3, lsl #1 80009b6: f47f aeeb bne.w 8000790 <__aeabi_dmul+0x1f8> 80009ba: e712 b.n 80007e2 <__aeabi_dmul+0x24a> 080009bc <__gedf2>: 80009bc: f04f 3cff mov.w ip, #4294967295 80009c0: e006 b.n 80009d0 <__cmpdf2+0x4> 80009c2: bf00 nop 080009c4 <__ledf2>: 80009c4: f04f 0c01 mov.w ip, #1 80009c8: e002 b.n 80009d0 <__cmpdf2+0x4> 80009ca: bf00 nop 080009cc <__cmpdf2>: 80009cc: f04f 0c01 mov.w ip, #1 80009d0: f84d cd04 str.w ip, [sp, #-4]! 80009d4: ea4f 0c41 mov.w ip, r1, lsl #1 80009d8: ea7f 5c6c mvns.w ip, ip, asr #21 80009dc: ea4f 0c43 mov.w ip, r3, lsl #1 80009e0: bf18 it ne 80009e2: ea7f 5c6c mvnsne.w ip, ip, asr #21 80009e6: d01b beq.n 8000a20 <__cmpdf2+0x54> 80009e8: b001 add sp, #4 80009ea: ea50 0c41 orrs.w ip, r0, r1, lsl #1 80009ee: bf0c ite eq 80009f0: ea52 0c43 orrseq.w ip, r2, r3, lsl #1 80009f4: ea91 0f03 teqne r1, r3 80009f8: bf02 ittt eq 80009fa: ea90 0f02 teqeq r0, r2 80009fe: 2000 moveq r0, #0 8000a00: 4770 bxeq lr 8000a02: f110 0f00 cmn.w r0, #0 8000a06: ea91 0f03 teq r1, r3 8000a0a: bf58 it pl 8000a0c: 4299 cmppl r1, r3 8000a0e: bf08 it eq 8000a10: 4290 cmpeq r0, r2 8000a12: bf2c ite cs 8000a14: 17d8 asrcs r0, r3, #31 8000a16: ea6f 70e3 mvncc.w r0, r3, asr #31 8000a1a: f040 0001 orr.w r0, r0, #1 8000a1e: 4770 bx lr 8000a20: ea4f 0c41 mov.w ip, r1, lsl #1 8000a24: ea7f 5c6c mvns.w ip, ip, asr #21 8000a28: d102 bne.n 8000a30 <__cmpdf2+0x64> 8000a2a: ea50 3c01 orrs.w ip, r0, r1, lsl #12 8000a2e: d107 bne.n 8000a40 <__cmpdf2+0x74> 8000a30: ea4f 0c43 mov.w ip, r3, lsl #1 8000a34: ea7f 5c6c mvns.w ip, ip, asr #21 8000a38: d1d6 bne.n 80009e8 <__cmpdf2+0x1c> 8000a3a: ea52 3c03 orrs.w ip, r2, r3, lsl #12 8000a3e: d0d3 beq.n 80009e8 <__cmpdf2+0x1c> 8000a40: f85d 0b04 ldr.w r0, [sp], #4 8000a44: 4770 bx lr 8000a46: bf00 nop 08000a48 <__aeabi_cdrcmple>: 8000a48: 4684 mov ip, r0 8000a4a: 4610 mov r0, r2 8000a4c: 4662 mov r2, ip 8000a4e: 468c mov ip, r1 8000a50: 4619 mov r1, r3 8000a52: 4663 mov r3, ip 8000a54: e000 b.n 8000a58 <__aeabi_cdcmpeq> 8000a56: bf00 nop 08000a58 <__aeabi_cdcmpeq>: 8000a58: b501 push {r0, lr} 8000a5a: f7ff ffb7 bl 80009cc <__cmpdf2> 8000a5e: 2800 cmp r0, #0 8000a60: bf48 it mi 8000a62: f110 0f00 cmnmi.w r0, #0 8000a66: bd01 pop {r0, pc} 08000a68 <__aeabi_dcmpeq>: 8000a68: f84d ed08 str.w lr, [sp, #-8]! 8000a6c: f7ff fff4 bl 8000a58 <__aeabi_cdcmpeq> 8000a70: bf0c ite eq 8000a72: 2001 moveq r0, #1 8000a74: 2000 movne r0, #0 8000a76: f85d fb08 ldr.w pc, [sp], #8 8000a7a: bf00 nop 08000a7c <__aeabi_dcmplt>: 8000a7c: f84d ed08 str.w lr, [sp, #-8]! 8000a80: f7ff ffea bl 8000a58 <__aeabi_cdcmpeq> 8000a84: bf34 ite cc 8000a86: 2001 movcc r0, #1 8000a88: 2000 movcs r0, #0 8000a8a: f85d fb08 ldr.w pc, [sp], #8 8000a8e: bf00 nop 08000a90 <__aeabi_dcmple>: 8000a90: f84d ed08 str.w lr, [sp, #-8]! 8000a94: f7ff ffe0 bl 8000a58 <__aeabi_cdcmpeq> 8000a98: bf94 ite ls 8000a9a: 2001 movls r0, #1 8000a9c: 2000 movhi r0, #0 8000a9e: f85d fb08 ldr.w pc, [sp], #8 8000aa2: bf00 nop 08000aa4 <__aeabi_dcmpge>: 8000aa4: f84d ed08 str.w lr, [sp, #-8]! 8000aa8: f7ff ffce bl 8000a48 <__aeabi_cdrcmple> 8000aac: bf94 ite ls 8000aae: 2001 movls r0, #1 8000ab0: 2000 movhi r0, #0 8000ab2: f85d fb08 ldr.w pc, [sp], #8 8000ab6: bf00 nop 08000ab8 <__aeabi_dcmpgt>: 8000ab8: f84d ed08 str.w lr, [sp, #-8]! 8000abc: f7ff ffc4 bl 8000a48 <__aeabi_cdrcmple> 8000ac0: bf34 ite cc 8000ac2: 2001 movcc r0, #1 8000ac4: 2000 movcs r0, #0 8000ac6: f85d fb08 ldr.w pc, [sp], #8 8000aca: bf00 nop 08000acc <__aeabi_dcmpun>: 8000acc: ea4f 0c41 mov.w ip, r1, lsl #1 8000ad0: ea7f 5c6c mvns.w ip, ip, asr #21 8000ad4: d102 bne.n 8000adc <__aeabi_dcmpun+0x10> 8000ad6: ea50 3c01 orrs.w ip, r0, r1, lsl #12 8000ada: d10a bne.n 8000af2 <__aeabi_dcmpun+0x26> 8000adc: ea4f 0c43 mov.w ip, r3, lsl #1 8000ae0: ea7f 5c6c mvns.w ip, ip, asr #21 8000ae4: d102 bne.n 8000aec <__aeabi_dcmpun+0x20> 8000ae6: ea52 3c03 orrs.w ip, r2, r3, lsl #12 8000aea: d102 bne.n 8000af2 <__aeabi_dcmpun+0x26> 8000aec: f04f 0000 mov.w r0, #0 8000af0: 4770 bx lr 8000af2: f04f 0001 mov.w r0, #1 8000af6: 4770 bx lr 08000af8 <__aeabi_d2iz>: 8000af8: ea4f 0241 mov.w r2, r1, lsl #1 8000afc: f512 1200 adds.w r2, r2, #2097152 ; 0x200000 8000b00: d215 bcs.n 8000b2e <__aeabi_d2iz+0x36> 8000b02: d511 bpl.n 8000b28 <__aeabi_d2iz+0x30> 8000b04: f46f 7378 mvn.w r3, #992 ; 0x3e0 8000b08: ebb3 5262 subs.w r2, r3, r2, asr #21 8000b0c: d912 bls.n 8000b34 <__aeabi_d2iz+0x3c> 8000b0e: ea4f 23c1 mov.w r3, r1, lsl #11 8000b12: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 8000b16: ea43 5350 orr.w r3, r3, r0, lsr #21 8000b1a: f011 4f00 tst.w r1, #2147483648 ; 0x80000000 8000b1e: fa23 f002 lsr.w r0, r3, r2 8000b22: bf18 it ne 8000b24: 4240 negne r0, r0 8000b26: 4770 bx lr 8000b28: f04f 0000 mov.w r0, #0 8000b2c: 4770 bx lr 8000b2e: ea50 3001 orrs.w r0, r0, r1, lsl #12 8000b32: d105 bne.n 8000b40 <__aeabi_d2iz+0x48> 8000b34: f011 4000 ands.w r0, r1, #2147483648 ; 0x80000000 8000b38: bf08 it eq 8000b3a: f06f 4000 mvneq.w r0, #2147483648 ; 0x80000000 8000b3e: 4770 bx lr 8000b40: f04f 0000 mov.w r0, #0 8000b44: 4770 bx lr 8000b46: bf00 nop 08000b48 <__aeabi_d2uiz>: 8000b48: 004a lsls r2, r1, #1 8000b4a: d211 bcs.n 8000b70 <__aeabi_d2uiz+0x28> 8000b4c: f512 1200 adds.w r2, r2, #2097152 ; 0x200000 8000b50: d211 bcs.n 8000b76 <__aeabi_d2uiz+0x2e> 8000b52: d50d bpl.n 8000b70 <__aeabi_d2uiz+0x28> 8000b54: f46f 7378 mvn.w r3, #992 ; 0x3e0 8000b58: ebb3 5262 subs.w r2, r3, r2, asr #21 8000b5c: d40e bmi.n 8000b7c <__aeabi_d2uiz+0x34> 8000b5e: ea4f 23c1 mov.w r3, r1, lsl #11 8000b62: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 8000b66: ea43 5350 orr.w r3, r3, r0, lsr #21 8000b6a: fa23 f002 lsr.w r0, r3, r2 8000b6e: 4770 bx lr 8000b70: f04f 0000 mov.w r0, #0 8000b74: 4770 bx lr 8000b76: ea50 3001 orrs.w r0, r0, r1, lsl #12 8000b7a: d102 bne.n 8000b82 <__aeabi_d2uiz+0x3a> 8000b7c: f04f 30ff mov.w r0, #4294967295 8000b80: 4770 bx lr 8000b82: f04f 0000 mov.w r0, #0 8000b86: 4770 bx lr 08000b88 <__aeabi_d2f>: 8000b88: ea4f 0241 mov.w r2, r1, lsl #1 8000b8c: f1b2 43e0 subs.w r3, r2, #1879048192 ; 0x70000000 8000b90: bf24 itt cs 8000b92: f5b3 1c00 subscs.w ip, r3, #2097152 ; 0x200000 8000b96: f1dc 5cfe rsbscs ip, ip, #532676608 ; 0x1fc00000 8000b9a: d90d bls.n 8000bb8 <__aeabi_d2f+0x30> 8000b9c: f001 4c00 and.w ip, r1, #2147483648 ; 0x80000000 8000ba0: ea4f 02c0 mov.w r2, r0, lsl #3 8000ba4: ea4c 7050 orr.w r0, ip, r0, lsr #29 8000ba8: f1b2 4f00 cmp.w r2, #2147483648 ; 0x80000000 8000bac: eb40 0083 adc.w r0, r0, r3, lsl #2 8000bb0: bf08 it eq 8000bb2: f020 0001 biceq.w r0, r0, #1 8000bb6: 4770 bx lr 8000bb8: f011 4f80 tst.w r1, #1073741824 ; 0x40000000 8000bbc: d121 bne.n 8000c02 <__aeabi_d2f+0x7a> 8000bbe: f113 7238 adds.w r2, r3, #48234496 ; 0x2e00000 8000bc2: bfbc itt lt 8000bc4: f001 4000 andlt.w r0, r1, #2147483648 ; 0x80000000 8000bc8: 4770 bxlt lr 8000bca: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 8000bce: ea4f 5252 mov.w r2, r2, lsr #21 8000bd2: f1c2 0218 rsb r2, r2, #24 8000bd6: f1c2 0c20 rsb ip, r2, #32 8000bda: fa10 f30c lsls.w r3, r0, ip 8000bde: fa20 f002 lsr.w r0, r0, r2 8000be2: bf18 it ne 8000be4: f040 0001 orrne.w r0, r0, #1 8000be8: ea4f 23c1 mov.w r3, r1, lsl #11 8000bec: ea4f 23d3 mov.w r3, r3, lsr #11 8000bf0: fa03 fc0c lsl.w ip, r3, ip 8000bf4: ea40 000c orr.w r0, r0, ip 8000bf8: fa23 f302 lsr.w r3, r3, r2 8000bfc: ea4f 0343 mov.w r3, r3, lsl #1 8000c00: e7cc b.n 8000b9c <__aeabi_d2f+0x14> 8000c02: ea7f 5362 mvns.w r3, r2, asr #21 8000c06: d107 bne.n 8000c18 <__aeabi_d2f+0x90> 8000c08: ea50 3301 orrs.w r3, r0, r1, lsl #12 8000c0c: bf1e ittt ne 8000c0e: f04f 40fe movne.w r0, #2130706432 ; 0x7f000000 8000c12: f440 0040 orrne.w r0, r0, #12582912 ; 0xc00000 8000c16: 4770 bxne lr 8000c18: f001 4000 and.w r0, r1, #2147483648 ; 0x80000000 8000c1c: f040 40fe orr.w r0, r0, #2130706432 ; 0x7f000000 8000c20: f440 0000 orr.w r0, r0, #8388608 ; 0x800000 8000c24: 4770 bx lr 8000c26: bf00 nop 08000c28 : volatile uint8_t NessLab_TxData[200] = {0,}; uint8_t Flash_DataArray[200] = {0,}; uint8_t DB_Define[100]; void NessLab_Init(){ 8000c28: b580 push {r7, lr} 8000c2a: af00 add r7, sp, #0 FLASH_Read_Func(FLASH_USER_USE_START_ADDR + 2,&DB_Define[0],104); 8000c2c: 2268 movs r2, #104 ; 0x68 8000c2e: 4906 ldr r1, [pc, #24] ; (8000c48 ) 8000c30: 4806 ldr r0, [pc, #24] ; (8000c4c ) 8000c32: f000 fef5 bl 8001a20 HAL_GPIO_WritePin(PAU_RESET_GPIO_Port,PAU_RESET_Pin, GPIO_PIN_SET); 8000c36: 2201 movs r2, #1 8000c38: f44f 4180 mov.w r1, #16384 ; 0x4000 8000c3c: 4804 ldr r0, [pc, #16] ; (8000c50 ) 8000c3e: f002 fc86 bl 800354e } 8000c42: bf00 nop 8000c44: bd80 pop {r7, pc} 8000c46: bf00 nop 8000c48: 20000648 .word 0x20000648 8000c4c: 0800ff3a .word 0x0800ff3a 8000c50: 40010c00 .word 0x40010c00 8000c54: 00000000 .word 0x00000000 08000c58 : double Round_Function(double value){ 8000c58: b590 push {r4, r7, lr} 8000c5a: b085 sub sp, #20 8000c5c: af00 add r7, sp, #0 8000c5e: e9c7 0100 strd r0, r1, [r7] double val = value * 100; 8000c62: f04f 0200 mov.w r2, #0 8000c66: 4b2a ldr r3, [pc, #168] ; (8000d10 ) 8000c68: e9d7 0100 ldrd r0, r1, [r7] 8000c6c: f7ff fc94 bl 8000598 <__aeabi_dmul> 8000c70: 4603 mov r3, r0 8000c72: 460c mov r4, r1 8000c74: e9c7 3402 strd r3, r4, [r7, #8] val = (int)(val + 0.5); 8000c78: f04f 0200 mov.w r2, #0 8000c7c: 4b25 ldr r3, [pc, #148] ; (8000d14 ) 8000c7e: e9d7 0102 ldrd r0, r1, [r7, #8] 8000c82: f7ff fad3 bl 800022c <__adddf3> 8000c86: 4603 mov r3, r0 8000c88: 460c mov r4, r1 8000c8a: 4618 mov r0, r3 8000c8c: 4621 mov r1, r4 8000c8e: f7ff ff33 bl 8000af8 <__aeabi_d2iz> 8000c92: 4603 mov r3, r0 8000c94: 4618 mov r0, r3 8000c96: f7ff fc15 bl 80004c4 <__aeabi_i2d> 8000c9a: 4603 mov r3, r0 8000c9c: 460c mov r4, r1 8000c9e: e9c7 3402 strd r3, r4, [r7, #8] val *= 0.1; 8000ca2: a319 add r3, pc, #100 ; (adr r3, 8000d08 ) 8000ca4: e9d3 2300 ldrd r2, r3, [r3] 8000ca8: e9d7 0102 ldrd r0, r1, [r7, #8] 8000cac: f7ff fc74 bl 8000598 <__aeabi_dmul> 8000cb0: 4603 mov r3, r0 8000cb2: 460c mov r4, r1 8000cb4: e9c7 3402 strd r3, r4, [r7, #8] val = (int)(val + 0.5); 8000cb8: f04f 0200 mov.w r2, #0 8000cbc: 4b15 ldr r3, [pc, #84] ; (8000d14 ) 8000cbe: e9d7 0102 ldrd r0, r1, [r7, #8] 8000cc2: f7ff fab3 bl 800022c <__adddf3> 8000cc6: 4603 mov r3, r0 8000cc8: 460c mov r4, r1 8000cca: 4618 mov r0, r3 8000ccc: 4621 mov r1, r4 8000cce: f7ff ff13 bl 8000af8 <__aeabi_d2iz> 8000cd2: 4603 mov r3, r0 8000cd4: 4618 mov r0, r3 8000cd6: f7ff fbf5 bl 80004c4 <__aeabi_i2d> 8000cda: 4603 mov r3, r0 8000cdc: 460c mov r4, r1 8000cde: e9c7 3402 strd r3, r4, [r7, #8] val *= 0.1; 8000ce2: a309 add r3, pc, #36 ; (adr r3, 8000d08 ) 8000ce4: e9d3 2300 ldrd r2, r3, [r3] 8000ce8: e9d7 0102 ldrd r0, r1, [r7, #8] 8000cec: f7ff fc54 bl 8000598 <__aeabi_dmul> 8000cf0: 4603 mov r3, r0 8000cf2: 460c mov r4, r1 8000cf4: e9c7 3402 strd r3, r4, [r7, #8] return val; 8000cf8: e9d7 3402 ldrd r3, r4, [r7, #8] } 8000cfc: 4618 mov r0, r3 8000cfe: 4621 mov r1, r4 8000d00: 3714 adds r7, #20 8000d02: 46bd mov sp, r7 8000d04: bd90 pop {r4, r7, pc} 8000d06: bf00 nop 8000d08: 9999999a .word 0x9999999a 8000d0c: 3fb99999 .word 0x3fb99999 8000d10: 40590000 .word 0x40590000 8000d14: 3fe00000 .word 0x3fe00000 08000d18 : uint16_t Absolute_value_Convert(int16_t val){ 8000d18: b480 push {r7} 8000d1a: b083 sub sp, #12 8000d1c: af00 add r7, sp, #0 8000d1e: 4603 mov r3, r0 8000d20: 80fb strh r3, [r7, #6] if(val < 0) 8000d22: f9b7 3006 ldrsh.w r3, [r7, #6] 8000d26: 2b00 cmp r3, #0 8000d28: da03 bge.n 8000d32 val *= -1; 8000d2a: 88fb ldrh r3, [r7, #6] 8000d2c: 425b negs r3, r3 8000d2e: b29b uxth r3, r3 8000d30: 80fb strh r3, [r7, #6] return val; 8000d32: 88fb ldrh r3, [r7, #6] } 8000d34: 4618 mov r0, r3 8000d36: 370c adds r7, #12 8000d38: 46bd mov sp, r7 8000d3a: bc80 pop {r7} 8000d3c: 4770 bx lr ... 08000d40 : uint8_t NessLab_Adc_Convert_db() // ?占쏙옙湲고븿?占쏙옙 { 8000d40: b590 push {r4, r7, lr} 8000d42: b08b sub sp, #44 ; 0x2c 8000d44: af00 add r7, sp, #0 double CurrAdc = (float)((Currstatus.DownLink_Forward_Det_H << 8 | Currstatus.DownLink_Forward_Det_L)*0.001); 8000d46: 4b4a ldr r3, [pc, #296] ; (8000e70 ) 8000d48: 79db ldrb r3, [r3, #7] 8000d4a: 021b lsls r3, r3, #8 8000d4c: 4a48 ldr r2, [pc, #288] ; (8000e70 ) 8000d4e: 7a12 ldrb r2, [r2, #8] 8000d50: 4313 orrs r3, r2 8000d52: 4618 mov r0, r3 8000d54: f7ff fbb6 bl 80004c4 <__aeabi_i2d> 8000d58: a343 add r3, pc, #268 ; (adr r3, 8000e68 ) 8000d5a: e9d3 2300 ldrd r2, r3, [r3] 8000d5e: f7ff fc1b bl 8000598 <__aeabi_dmul> 8000d62: 4603 mov r3, r0 8000d64: 460c mov r4, r1 8000d66: 4618 mov r0, r3 8000d68: 4621 mov r1, r4 8000d6a: f7ff ff0d bl 8000b88 <__aeabi_d2f> 8000d6e: 4603 mov r3, r0 8000d70: 4618 mov r0, r3 8000d72: f7ff fbb9 bl 80004e8 <__aeabi_f2d> 8000d76: 4603 mov r3, r0 8000d78: 460c mov r4, r1 8000d7a: e9c7 3406 strd r3, r4, [r7, #24] double TableVal = 0; 8000d7e: f04f 0300 mov.w r3, #0 8000d82: f04f 0400 mov.w r4, #0 8000d86: e9c7 3404 strd r3, r4, [r7, #16] float ret = 0; 8000d8a: f04f 0300 mov.w r3, #0 8000d8e: 60fb str r3, [r7, #12] int16_t calc_val = 0,Prev_calc_val = 3300 ; 8000d90: 2300 movs r3, #0 8000d92: 817b strh r3, [r7, #10] 8000d94: f640 43e4 movw r3, #3300 ; 0xce4 8000d98: 84fb strh r3, [r7, #38] ; 0x26 uint8_t Curr_DB = 0 ; 8000d9a: 2300 movs r3, #0 8000d9c: f887 3025 strb.w r3, [r7, #37] ; 0x25 uint16_t CurrAdc_Temp = 0,TableVal_Temp = 0; 8000da0: 2300 movs r3, #0 8000da2: 813b strh r3, [r7, #8] 8000da4: 2300 movs r3, #0 8000da6: 80fb strh r3, [r7, #6] ret = Round_Function(CurrAdc); 8000da8: e9d7 0106 ldrd r0, r1, [r7, #24] 8000dac: f7ff ff54 bl 8000c58 8000db0: 4603 mov r3, r0 8000db2: 460c mov r4, r1 8000db4: 4618 mov r0, r3 8000db6: 4621 mov r1, r4 8000db8: f7ff fee6 bl 8000b88 <__aeabi_d2f> 8000dbc: 4603 mov r3, r0 8000dbe: 60fb str r3, [r7, #12] // CurrAdc *= 1000; CurrAdc_Temp = CurrAdc * 1000; 8000dc0: f04f 0200 mov.w r2, #0 8000dc4: 4b2b ldr r3, [pc, #172] ; (8000e74 ) 8000dc6: e9d7 0106 ldrd r0, r1, [r7, #24] 8000dca: f7ff fbe5 bl 8000598 <__aeabi_dmul> 8000dce: 4603 mov r3, r0 8000dd0: 460c mov r4, r1 8000dd2: 4618 mov r0, r3 8000dd4: 4621 mov r1, r4 8000dd6: f7ff feb7 bl 8000b48 <__aeabi_d2uiz> 8000dda: 4603 mov r3, r0 8000ddc: 813b strh r3, [r7, #8] for(int i = 0; i <= 50; i++){ 8000dde: 2300 movs r3, #0 8000de0: 623b str r3, [r7, #32] 8000de2: e030 b.n 8000e46 TableVal_Temp = ((DB_Define[i * 2] << 8 | DB_Define[(i * 2)+ 1])); 8000de4: 6a3b ldr r3, [r7, #32] 8000de6: 005b lsls r3, r3, #1 8000de8: 4a23 ldr r2, [pc, #140] ; (8000e78 ) 8000dea: 5cd3 ldrb r3, [r2, r3] 8000dec: 021b lsls r3, r3, #8 8000dee: b21a sxth r2, r3 8000df0: 6a3b ldr r3, [r7, #32] 8000df2: 005b lsls r3, r3, #1 8000df4: 3301 adds r3, #1 8000df6: 4920 ldr r1, [pc, #128] ; (8000e78 ) 8000df8: 5ccb ldrb r3, [r1, r3] 8000dfa: b21b sxth r3, r3 8000dfc: 4313 orrs r3, r2 8000dfe: b21b sxth r3, r3 8000e00: 80fb strh r3, [r7, #6] if(TableVal_Temp == 0) 8000e02: 88fb ldrh r3, [r7, #6] 8000e04: 2b00 cmp r3, #0 8000e06: d01a beq.n 8000e3e continue; calc_val = CurrAdc_Temp - TableVal_Temp; 8000e08: 893a ldrh r2, [r7, #8] 8000e0a: 88fb ldrh r3, [r7, #6] 8000e0c: 1ad3 subs r3, r2, r3 8000e0e: b29b uxth r3, r3 8000e10: 817b strh r3, [r7, #10] calc_val = Absolute_value_Convert(calc_val); 8000e12: f9b7 300a ldrsh.w r3, [r7, #10] 8000e16: 4618 mov r0, r3 8000e18: f7ff ff7e bl 8000d18 8000e1c: 4603 mov r3, r0 8000e1e: 817b strh r3, [r7, #10] // printf("%d - %d calc_val : %d \r\n",CurrAdc_Temp,TableVal_Temp,calc_val); if(Prev_calc_val > calc_val && TableVal_Temp != 0){ 8000e20: f9b7 2026 ldrsh.w r2, [r7, #38] ; 0x26 8000e24: f9b7 300a ldrsh.w r3, [r7, #10] 8000e28: 429a cmp r2, r3 8000e2a: dd09 ble.n 8000e40 8000e2c: 88fb ldrh r3, [r7, #6] 8000e2e: 2b00 cmp r3, #0 8000e30: d006 beq.n 8000e40 Prev_calc_val = calc_val; 8000e32: 897b ldrh r3, [r7, #10] 8000e34: 84fb strh r3, [r7, #38] ; 0x26 Curr_DB = i ; 8000e36: 6a3b ldr r3, [r7, #32] 8000e38: f887 3025 strb.w r3, [r7, #37] ; 0x25 8000e3c: e000 b.n 8000e40 continue; 8000e3e: bf00 nop for(int i = 0; i <= 50; i++){ 8000e40: 6a3b ldr r3, [r7, #32] 8000e42: 3301 adds r3, #1 8000e44: 623b str r3, [r7, #32] 8000e46: 6a3b ldr r3, [r7, #32] 8000e48: 2b32 cmp r3, #50 ; 0x32 8000e4a: ddcb ble.n 8000de4 // printf("%d %d \r\n",Prev_calc_val , calc_val); } } // DB_Define[] printf("Curr Db : %d \r\n",Curr_DB); 8000e4c: f897 3025 ldrb.w r3, [r7, #37] ; 0x25 8000e50: 4619 mov r1, r3 8000e52: 480a ldr r0, [pc, #40] ; (8000e7c ) 8000e54: f005 fd84 bl 8006960 return Curr_DB; 8000e58: f897 3025 ldrb.w r3, [r7, #37] ; 0x25 } 8000e5c: 4618 mov r0, r3 8000e5e: 372c adds r7, #44 ; 0x2c 8000e60: 46bd mov sp, r7 8000e62: bd90 pop {r4, r7, pc} 8000e64: f3af 8000 nop.w 8000e68: d2f1a9fc .word 0xd2f1a9fc 8000e6c: 3f50624d .word 0x3f50624d 8000e70: 200006ac .word 0x200006ac 8000e74: 408f4000 .word 0x408f4000 8000e78: 20000648 .word 0x20000648 8000e7c: 08008958 .word 0x08008958 08000e80 : void NessLab_Operate(uint8_t* data){ 8000e80: b580 push {r7, lr} 8000e82: b086 sub sp, #24 8000e84: af00 add r7, sp, #0 8000e86: 6078 str r0, [r7, #4] uint8_t datatype = data[NessLab_MsgID0]; 8000e88: 687b ldr r3, [r7, #4] 8000e8a: 789b ldrb r3, [r3, #2] 8000e8c: 73fb strb r3, [r7, #15] uint8_t UartLength = 0; 8000e8e: 2300 movs r3, #0 8000e90: 75fb strb r3, [r7, #23] static uint16_t MSG_SNCnt = 0; switch(datatype){ 8000e92: 7bfb ldrb r3, [r7, #15] 8000e94: 2bcb cmp r3, #203 ; 0xcb 8000e96: d049 beq.n 8000f2c 8000e98: 2bcb cmp r3, #203 ; 0xcb 8000e9a: dc04 bgt.n 8000ea6 8000e9c: 2b65 cmp r3, #101 ; 0x65 8000e9e: d008 beq.n 8000eb2 8000ea0: 2bc9 cmp r3, #201 ; 0xc9 8000ea2: d030 beq.n 8000f06 8000ea4: e08f b.n 8000fc6 8000ea6: 2bcd cmp r3, #205 ; 0xcd 8000ea8: d07f beq.n 8000faa 8000eaa: 2bce cmp r3, #206 ; 0xce 8000eac: f000 8084 beq.w 8000fb8 8000eb0: e089 b.n 8000fc6 case NessLab_STATUS_REQ: ADC_Check(); 8000eb2: f000 fbb1 bl 8001618 UartLength = NessLab_MAX_INDEX + 1; 8000eb6: 2316 movs r3, #22 8000eb8: 75fb strb r3, [r7, #23] MSG_SNCnt = data[NessLab_Req_MsgSN0] << 8 | data[NessLab_Req_MsgSN1]; 8000eba: 687b ldr r3, [r7, #4] 8000ebc: 3303 adds r3, #3 8000ebe: 781b ldrb r3, [r3, #0] 8000ec0: 021b lsls r3, r3, #8 8000ec2: b21a sxth r2, r3 8000ec4: 687b ldr r3, [r7, #4] 8000ec6: 3304 adds r3, #4 8000ec8: 781b ldrb r3, [r3, #0] 8000eca: b21b sxth r3, r3 8000ecc: 4313 orrs r3, r2 8000ece: b21b sxth r3, r3 8000ed0: b29a uxth r2, r3 8000ed2: 4b41 ldr r3, [pc, #260] ; (8000fd8 ) 8000ed4: 801a strh r2, [r3, #0] MSG_SNCnt++; 8000ed6: 4b40 ldr r3, [pc, #256] ; (8000fd8 ) 8000ed8: 881b ldrh r3, [r3, #0] 8000eda: 3301 adds r3, #1 8000edc: b29a uxth r2, r3 8000ede: 4b3e ldr r3, [pc, #248] ; (8000fd8 ) 8000ee0: 801a strh r2, [r3, #0] // if(data[NessLab_Req_Data_Cnt1] > 0) // NessLab_TxData[NessLab_VSWR_ALARM] = 1; // else // NessLab_TxData[NessLab_VSWR_ALARM] = 0; NessLab_TxData[NessLab_MsgSN0] = (uint8_t)((MSG_SNCnt & 0xFF00) >>8);//data[NessLab_Req_MsgSN0]; 8000ee2: 4b3d ldr r3, [pc, #244] ; (8000fd8 ) 8000ee4: 881b ldrh r3, [r3, #0] 8000ee6: 0a1b lsrs r3, r3, #8 8000ee8: b29b uxth r3, r3 8000eea: b2da uxtb r2, r3 8000eec: 4b3b ldr r3, [pc, #236] ; (8000fdc ) 8000eee: 70da strb r2, [r3, #3] NessLab_TxData[NessLab_MsgSN1] = (uint8_t)((MSG_SNCnt & 0x00FF));//data[NessLab_Req_MsgSN1] ; 8000ef0: 4b39 ldr r3, [pc, #228] ; (8000fd8 ) 8000ef2: 881b ldrh r3, [r3, #0] 8000ef4: b2da uxtb r2, r3 8000ef6: 4b39 ldr r3, [pc, #228] ; (8000fdc ) 8000ef8: 711a strb r2, [r3, #4] NessLab_Frame_Set(NessLab_TxData,12,NessLab_STATUS_RES); 8000efa: 2266 movs r2, #102 ; 0x66 8000efc: 210c movs r1, #12 8000efe: 4837 ldr r0, [pc, #220] ; (8000fdc ) 8000f00: f000 f882 bl 8001008 // NessLab_TxData[14] = 1; // NessLab_TxData[15] = 0; // NessLab_TxData[16] = 1; // NessLab_TxData[17] = 0; break; 8000f04: e05f b.n 8000fc6 case NessLab_Table_REQ: UartLength = NESSLAB_TABLE_LENGTH; 8000f06: 236e movs r3, #110 ; 0x6e 8000f08: 75fb strb r3, [r7, #23] FLASH_Read_Func(FLASH_USER_USE_START_ADDR,&NessLab_TxData[NessLab_Req_Data_Cnt0],data[NessLab_DataLength]); 8000f0a: 687b ldr r3, [r7, #4] 8000f0c: 3306 adds r3, #6 8000f0e: 781b ldrb r3, [r3, #0] 8000f10: 461a mov r2, r3 8000f12: 4933 ldr r1, [pc, #204] ; (8000fe0 ) 8000f14: 4833 ldr r0, [pc, #204] ; (8000fe4 ) 8000f16: f000 fd83 bl 8001a20 NessLab_Table_Frame_Set(NessLab_TxData,102,NessLab_Table_RES); 8000f1a: 22ca movs r2, #202 ; 0xca 8000f1c: 2166 movs r1, #102 ; 0x66 8000f1e: 482f ldr r0, [pc, #188] ; (8000fdc ) 8000f20: f000 f97e bl 8001220 printf("NessLab_Table_REQ \r\n"); 8000f24: 4830 ldr r0, [pc, #192] ; (8000fe8 ) 8000f26: f005 fd8f bl 8006a48 break; 8000f2a: e04c b.n 8000fc6 case NessLab_TableSet_REQ: DataErase_Func(FLASH_USER_USE_START_ADDR,200); 8000f2c: 21c8 movs r1, #200 ; 0xc8 8000f2e: 482d ldr r0, [pc, #180] ; (8000fe4 ) 8000f30: f000 fc9c bl 800186c printf("Ram Data Display \r\n"); 8000f34: 482d ldr r0, [pc, #180] ; (8000fec ) 8000f36: f005 fd87 bl 8006a48 for(int i = 0; i < data[NessLab_DataLength]; i++){ 8000f3a: 2300 movs r3, #0 8000f3c: 613b str r3, [r7, #16] 8000f3e: e015 b.n 8000f6c Flash_DataArray[i] = data[NessLab_Data_ADC1_H + i]; 8000f40: 693b ldr r3, [r7, #16] 8000f42: 3307 adds r3, #7 8000f44: 461a mov r2, r3 8000f46: 687b ldr r3, [r7, #4] 8000f48: 4413 add r3, r2 8000f4a: 7819 ldrb r1, [r3, #0] 8000f4c: 4a28 ldr r2, [pc, #160] ; (8000ff0 ) 8000f4e: 693b ldr r3, [r7, #16] 8000f50: 4413 add r3, r2 8000f52: 460a mov r2, r1 8000f54: 701a strb r2, [r3, #0] printf("%x ",Flash_DataArray[i]); 8000f56: 4a26 ldr r2, [pc, #152] ; (8000ff0 ) 8000f58: 693b ldr r3, [r7, #16] 8000f5a: 4413 add r3, r2 8000f5c: 781b ldrb r3, [r3, #0] 8000f5e: 4619 mov r1, r3 8000f60: 4824 ldr r0, [pc, #144] ; (8000ff4 ) 8000f62: f005 fcfd bl 8006960 for(int i = 0; i < data[NessLab_DataLength]; i++){ 8000f66: 693b ldr r3, [r7, #16] 8000f68: 3301 adds r3, #1 8000f6a: 613b str r3, [r7, #16] 8000f6c: 687b ldr r3, [r7, #4] 8000f6e: 3306 adds r3, #6 8000f70: 781b ldrb r3, [r3, #0] 8000f72: 461a mov r2, r3 8000f74: 693b ldr r3, [r7, #16] 8000f76: 4293 cmp r3, r2 8000f78: dbe2 blt.n 8000f40 } FLASH_Write_Func(FLASH_USER_USE_START_ADDR,&Flash_DataArray[0],data[NessLab_DataLength]); 8000f7a: 687b ldr r3, [r7, #4] 8000f7c: 3306 adds r3, #6 8000f7e: 781b ldrb r3, [r3, #0] 8000f80: 461a mov r2, r3 8000f82: 491b ldr r1, [pc, #108] ; (8000ff0 ) 8000f84: 4817 ldr r0, [pc, #92] ; (8000fe4 ) 8000f86: f000 fcc3 bl 8001910 UartLength = NESSLAB_TABLE_LENGTH; 8000f8a: 236e movs r3, #110 ; 0x6e 8000f8c: 75fb strb r3, [r7, #23] NessLab_Table_Frame_Set(NessLab_TxData,104,NessLab_TableSet_RES); 8000f8e: 22cc movs r2, #204 ; 0xcc 8000f90: 2168 movs r1, #104 ; 0x68 8000f92: 4812 ldr r0, [pc, #72] ; (8000fdc ) 8000f94: f000 f944 bl 8001220 FLASH_Read_Func(FLASH_USER_USE_START_ADDR + 2,&DB_Define[0],104); 8000f98: 2268 movs r2, #104 ; 0x68 8000f9a: 4917 ldr r1, [pc, #92] ; (8000ff8 ) 8000f9c: 4817 ldr r0, [pc, #92] ; (8000ffc ) 8000f9e: f000 fd3f bl 8001a20 // NessLab_Init(); printf("\r\nNessLab_TableSet_REQ \r\n"); 8000fa2: 4817 ldr r0, [pc, #92] ; (8001000 ) 8000fa4: f005 fd50 bl 8006a48 break; 8000fa8: e00d b.n 8000fc6 case NessLab_PAU_Enable_Req: HAL_GPIO_WritePin(AMP_EN_GPIO_Port,AMP_EN_Pin, GPIO_PIN_SET); 8000faa: 2201 movs r2, #1 8000fac: f44f 7180 mov.w r1, #256 ; 0x100 8000fb0: 4814 ldr r0, [pc, #80] ; (8001004 ) 8000fb2: f002 facc bl 800354e break; 8000fb6: e006 b.n 8000fc6 case NessLab_PAU_Disable_Req: HAL_GPIO_WritePin(AMP_EN_GPIO_Port,AMP_EN_Pin, GPIO_PIN_RESET); 8000fb8: 2200 movs r2, #0 8000fba: f44f 7180 mov.w r1, #256 ; 0x100 8000fbe: 4811 ldr r0, [pc, #68] ; (8001004 ) 8000fc0: f002 fac5 bl 800354e break; 8000fc4: bf00 nop } Uart1_Data_Send(&NessLab_TxData[NessLab_Header0], UartLength); 8000fc6: 7dfb ldrb r3, [r7, #23] 8000fc8: 4619 mov r1, r3 8000fca: 4804 ldr r0, [pc, #16] ; (8000fdc ) 8000fcc: f000 feae bl 8001d2c } 8000fd0: bf00 nop 8000fd2: 3718 adds r7, #24 8000fd4: 46bd mov sp, r7 8000fd6: bd80 pop {r7, pc} 8000fd8: 2000038c .word 0x2000038c 8000fdc: 200001fc .word 0x200001fc 8000fe0: 20000203 .word 0x20000203 8000fe4: 0800ff38 .word 0x0800ff38 8000fe8: 08008968 .word 0x08008968 8000fec: 0800897c .word 0x0800897c 8000ff0: 200002c4 .word 0x200002c4 8000ff4: 08008990 .word 0x08008990 8000ff8: 20000648 .word 0x20000648 8000ffc: 0800ff3a .word 0x0800ff3a 8001000: 08008994 .word 0x08008994 8001004: 40010800 .word 0x40010800 08001008 : 7e 7e 66 00 02 00 0c 04 20 00 00 00 00 00 00 00 00 00 68 7e 7e 0a */ void NessLab_Frame_Set(uint8_t* data,uint8_t size){ 8001008: b590 push {r4, r7, lr} 800100a: b083 sub sp, #12 800100c: af00 add r7, sp, #0 800100e: 6078 str r0, [r7, #4] 8001010: 460b mov r3, r1 8001012: 70fb strb r3, [r7, #3] data[NessLab_Header0] = 0x7E; 8001014: 687b ldr r3, [r7, #4] 8001016: 227e movs r2, #126 ; 0x7e 8001018: 701a strb r2, [r3, #0] data[NessLab_Header1] = 0x7E; 800101a: 687b ldr r3, [r7, #4] 800101c: 3301 adds r3, #1 800101e: 227e movs r2, #126 ; 0x7e 8001020: 701a strb r2, [r3, #0] data[NessLab_MsgID0] = NessLab_STATUS_RES;// ID 8001022: 687b ldr r3, [r7, #4] 8001024: 3302 adds r3, #2 8001026: 2266 movs r2, #102 ; 0x66 8001028: 701a strb r2, [r3, #0] // data[NessLab_MsgSN0] = 0; // SEQ NUMBER // data[NessLab_MsgSN1] = 0; // SEQ NUMBER data[NessLab_Reserve0] = 0; // NessLab_Reserve0 800102a: 687b ldr r3, [r7, #4] 800102c: 3305 adds r3, #5 800102e: 2200 movs r2, #0 8001030: 701a strb r2, [r3, #0] data[NessLab_DataLength] = size; // Nesslab Size 8001032: 687b ldr r3, [r7, #4] 8001034: 3306 adds r3, #6 8001036: 78fa ldrb r2, [r7, #3] 8001038: 701a strb r2, [r3, #0] data[NessLab_Data_ADC1_H] = Currstatus.DownLink_Forward_Det_H;//(uint8_t)((ADC1value[0] & 0xFF00) >> 8); 800103a: 687b ldr r3, [r7, #4] 800103c: 3307 adds r3, #7 800103e: 4a49 ldr r2, [pc, #292] ; (8001164 ) 8001040: 79d2 ldrb r2, [r2, #7] 8001042: 701a strb r2, [r3, #0] data[NessLab_Data_ADC1_L] = Currstatus.DownLink_Forward_Det_L;//(uint8_t)(ADC1value[0] & 0x00FF); 8001044: 687b ldr r3, [r7, #4] 8001046: 3308 adds r3, #8 8001048: 4a46 ldr r2, [pc, #280] ; (8001164 ) 800104a: 7a12 ldrb r2, [r2, #8] 800104c: 701a strb r2, [r3, #0] data[NessLab_Data_ADC1_Table_Value] = NessLab_Adc_Convert_db(); 800104e: 687b ldr r3, [r7, #4] 8001050: f103 0409 add.w r4, r3, #9 8001054: f7ff fe74 bl 8000d40 8001058: 4603 mov r3, r0 800105a: 7023 strb r3, [r4, #0] if(DC_FAIL_ALARM_CNT > 3000) 800105c: 4b42 ldr r3, [pc, #264] ; (8001168 ) 800105e: 681b ldr r3, [r3, #0] 8001060: f640 32b8 movw r2, #3000 ; 0xbb8 8001064: 4293 cmp r3, r2 8001066: d904 bls.n 8001072 data[NessLab_DC_FAIL_ALARM] = 1; 8001068: 687b ldr r3, [r7, #4] 800106a: 330a adds r3, #10 800106c: 2201 movs r2, #1 800106e: 701a strb r2, [r3, #0] 8001070: e003 b.n 800107a else data[NessLab_DC_FAIL_ALARM] = 0; 8001072: 687b ldr r3, [r7, #4] 8001074: 330a adds r3, #10 8001076: 2200 movs r2, #0 8001078: 701a strb r2, [r3, #0] if(OVER_INPUT_ALARM_CNT > 3000) 800107a: 4b3c ldr r3, [pc, #240] ; (800116c ) 800107c: 681b ldr r3, [r3, #0] 800107e: f640 32b8 movw r2, #3000 ; 0xbb8 8001082: 4293 cmp r3, r2 8001084: d904 bls.n 8001090 data[NessLab_Over_Input_Alarm] = 1; 8001086: 687b ldr r3, [r7, #4] 8001088: 330e adds r3, #14 800108a: 2201 movs r2, #1 800108c: 701a strb r2, [r3, #0] 800108e: e003 b.n 8001098 else data[NessLab_Over_Input_Alarm] = 0; 8001090: 687b ldr r3, [r7, #4] 8001092: 330e adds r3, #14 8001094: 2200 movs r2, #0 8001096: 701a strb r2, [r3, #0] if(OVER_TEMP_ALARM_CNT > 3000) 8001098: 4b35 ldr r3, [pc, #212] ; (8001170 ) 800109a: 681b ldr r3, [r3, #0] 800109c: f640 32b8 movw r2, #3000 ; 0xbb8 80010a0: 4293 cmp r3, r2 80010a2: d904 bls.n 80010ae data[NessLab_Over_Temp_Alarm] = 1; 80010a4: 687b ldr r3, [r7, #4] 80010a6: 330f adds r3, #15 80010a8: 2201 movs r2, #1 80010aa: 701a strb r2, [r3, #0] 80010ac: e003 b.n 80010b6 else data[NessLab_Over_Temp_Alarm] = 0; 80010ae: 687b ldr r3, [r7, #4] 80010b0: 330f adds r3, #15 80010b2: 2200 movs r2, #0 80010b4: 701a strb r2, [r3, #0] if(ALC_ALARM_CNT > 3000) 80010b6: 4b2f ldr r3, [pc, #188] ; (8001174 ) 80010b8: 681b ldr r3, [r3, #0] 80010ba: f640 32b8 movw r2, #3000 ; 0xbb8 80010be: 4293 cmp r3, r2 80010c0: d904 bls.n 80010cc data[NessLab_ALC_ALARM] = 1; 80010c2: 687b ldr r3, [r7, #4] 80010c4: 3311 adds r3, #17 80010c6: 2201 movs r2, #1 80010c8: 701a strb r2, [r3, #0] 80010ca: e003 b.n 80010d4 else data[NessLab_ALC_ALARM] = 0; 80010cc: 687b ldr r3, [r7, #4] 80010ce: 3311 adds r3, #17 80010d0: 2200 movs r2, #0 80010d2: 701a strb r2, [r3, #0] if(OVER_POWER_ALARM_CNT > 3000) 80010d4: 4b28 ldr r3, [pc, #160] ; (8001178 ) 80010d6: 681b ldr r3, [r3, #0] 80010d8: f640 32b8 movw r2, #3000 ; 0xbb8 80010dc: 4293 cmp r3, r2 80010de: d904 bls.n 80010ea data[NessLab_Over_Power_Alarm] = 1; 80010e0: 687b ldr r3, [r7, #4] 80010e2: 330c adds r3, #12 80010e4: 2201 movs r2, #1 80010e6: 701a strb r2, [r3, #0] 80010e8: e003 b.n 80010f2 else data[NessLab_Over_Power_Alarm] = 0; 80010ea: 687b ldr r3, [r7, #4] 80010ec: 330c adds r3, #12 80010ee: 2200 movs r2, #0 80010f0: 701a strb r2, [r3, #0] if(VSWR_ALARM_CNT > 3000) 80010f2: 4b22 ldr r3, [pc, #136] ; (800117c ) 80010f4: 681b ldr r3, [r3, #0] 80010f6: f640 32b8 movw r2, #3000 ; 0xbb8 80010fa: 4293 cmp r3, r2 80010fc: d904 bls.n 8001108 data[NessLab_VSWR_ALARM] = 1; 80010fe: 687b ldr r3, [r7, #4] 8001100: 330d adds r3, #13 8001102: 2201 movs r2, #1 8001104: 701a strb r2, [r3, #0] 8001106: e003 b.n 8001110 else data[NessLab_VSWR_ALARM] = 0; 8001108: 687b ldr r3, [r7, #4] 800110a: 330d adds r3, #13 800110c: 2200 movs r2, #0 800110e: 701a strb r2, [r3, #0] data[NessLab_DownLink_Status] = 0; 8001110: 687b ldr r3, [r7, #4] 8001112: 330b adds r3, #11 8001114: 2200 movs r2, #0 8001116: 701a strb r2, [r3, #0] data[NessLab_Temp_Monitor] = Currstatus.Temp_Monitor; 8001118: 687b ldr r3, [r7, #4] 800111a: 3310 adds r3, #16 800111c: 4a11 ldr r2, [pc, #68] ; (8001164 ) 800111e: 7c52 ldrb r2, [r2, #17] 8001120: 701a strb r2, [r3, #0] data[NessLab_ChecksumVal] = NessLab_Checksum(&data[NessLab_MsgID0], NessLab_MAX_INDEX - 5); 8001122: 687b ldr r3, [r7, #4] 8001124: 1c9a adds r2, r3, #2 8001126: 687b ldr r3, [r7, #4] 8001128: f103 0412 add.w r4, r3, #18 800112c: 2110 movs r1, #16 800112e: 4610 mov r0, r2 8001130: f000 fb40 bl 80017b4 8001134: 4603 mov r3, r0 8001136: 7023 strb r3, [r4, #0] /* Exception Header Tail Checksum */ data[NessLab_Tail0] = 0x7E; 8001138: 687b ldr r3, [r7, #4] 800113a: 3313 adds r3, #19 800113c: 227e movs r2, #126 ; 0x7e 800113e: 701a strb r2, [r3, #0] data[NessLab_Tail1] = 0x7E; 8001140: 687b ldr r3, [r7, #4] 8001142: 3314 adds r3, #20 8001144: 227e movs r2, #126 ; 0x7e 8001146: 701a strb r2, [r3, #0] data[NessLab_Tail1 + 1] = 0x0A; 8001148: 687b ldr r3, [r7, #4] 800114a: 3315 adds r3, #21 800114c: 220a movs r2, #10 800114e: 701a strb r2, [r3, #0] NessLab_Protocol_LastCheck(&data[NessLab_MsgID0],16); 8001150: 687b ldr r3, [r7, #4] 8001152: 3302 adds r3, #2 8001154: 2110 movs r1, #16 8001156: 4618 mov r0, r3 8001158: f000 f812 bl 8001180 } 800115c: bf00 nop 800115e: 370c adds r7, #12 8001160: 46bd mov sp, r7 8001162: bd90 pop {r4, r7, pc} 8001164: 200006ac .word 0x200006ac 8001168: 2000061c .word 0x2000061c 800116c: 20000620 .word 0x20000620 8001170: 20000624 .word 0x20000624 8001174: 20000628 .word 0x20000628 8001178: 2000062c .word 0x2000062c 800117c: 20000630 .word 0x20000630 08001180 : void NessLab_Protocol_LastCheck(uint8_t* data,uint8_t size){ 8001180: b480 push {r7} 8001182: b085 sub sp, #20 8001184: af00 add r7, sp, #0 8001186: 6078 str r0, [r7, #4] 8001188: 460b mov r3, r1 800118a: 70fb strb r3, [r7, #3] int cnt = NessLab_MsgID0; 800118c: 2302 movs r3, #2 800118e: 60fb str r3, [r7, #12] for(int i = cnt; i < 17; i++){ 8001190: 68fb ldr r3, [r7, #12] 8001192: 60bb str r3, [r7, #8] 8001194: e03b b.n 800120e if(data[i] == 0x7e){ 8001196: 68bb ldr r3, [r7, #8] 8001198: 687a ldr r2, [r7, #4] 800119a: 4413 add r3, r2 800119c: 781b ldrb r3, [r3, #0] 800119e: 2b7e cmp r3, #126 ; 0x7e 80011a0: d110 bne.n 80011c4 data[cnt++] = 0x7d; 80011a2: 68fb ldr r3, [r7, #12] 80011a4: 1c5a adds r2, r3, #1 80011a6: 60fa str r2, [r7, #12] 80011a8: 461a mov r2, r3 80011aa: 687b ldr r3, [r7, #4] 80011ac: 4413 add r3, r2 80011ae: 227d movs r2, #125 ; 0x7d 80011b0: 701a strb r2, [r3, #0] data[cnt++] = 0x5e; 80011b2: 68fb ldr r3, [r7, #12] 80011b4: 1c5a adds r2, r3, #1 80011b6: 60fa str r2, [r7, #12] 80011b8: 461a mov r2, r3 80011ba: 687b ldr r3, [r7, #4] 80011bc: 4413 add r3, r2 80011be: 225e movs r2, #94 ; 0x5e 80011c0: 701a strb r2, [r3, #0] 80011c2: e021 b.n 8001208 } else if(data[i] == 0x7d){ 80011c4: 68bb ldr r3, [r7, #8] 80011c6: 687a ldr r2, [r7, #4] 80011c8: 4413 add r3, r2 80011ca: 781b ldrb r3, [r3, #0] 80011cc: 2b7d cmp r3, #125 ; 0x7d 80011ce: d110 bne.n 80011f2 data[cnt++] = 0x7d; 80011d0: 68fb ldr r3, [r7, #12] 80011d2: 1c5a adds r2, r3, #1 80011d4: 60fa str r2, [r7, #12] 80011d6: 461a mov r2, r3 80011d8: 687b ldr r3, [r7, #4] 80011da: 4413 add r3, r2 80011dc: 227d movs r2, #125 ; 0x7d 80011de: 701a strb r2, [r3, #0] data[cnt++] = 0x5d; 80011e0: 68fb ldr r3, [r7, #12] 80011e2: 1c5a adds r2, r3, #1 80011e4: 60fa str r2, [r7, #12] 80011e6: 461a mov r2, r3 80011e8: 687b ldr r3, [r7, #4] 80011ea: 4413 add r3, r2 80011ec: 225d movs r2, #93 ; 0x5d 80011ee: 701a strb r2, [r3, #0] 80011f0: e00a b.n 8001208 }else{ data[i++] = data[i]; 80011f2: 68bb ldr r3, [r7, #8] 80011f4: 687a ldr r2, [r7, #4] 80011f6: 441a add r2, r3 80011f8: 68bb ldr r3, [r7, #8] 80011fa: 1c59 adds r1, r3, #1 80011fc: 60b9 str r1, [r7, #8] 80011fe: 4619 mov r1, r3 8001200: 687b ldr r3, [r7, #4] 8001202: 440b add r3, r1 8001204: 7812 ldrb r2, [r2, #0] 8001206: 701a strb r2, [r3, #0] for(int i = cnt; i < 17; i++){ 8001208: 68bb ldr r3, [r7, #8] 800120a: 3301 adds r3, #1 800120c: 60bb str r3, [r7, #8] 800120e: 68bb ldr r3, [r7, #8] 8001210: 2b10 cmp r3, #16 8001212: ddc0 ble.n 8001196 } } } 8001214: bf00 nop 8001216: 3714 adds r7, #20 8001218: 46bd mov sp, r7 800121a: bc80 pop {r7} 800121c: 4770 bx lr ... 08001220 : void NessLab_Table_Frame_Set(uint8_t* data,uint8_t size,uint8_t mode){ 8001220: b590 push {r4, r7, lr} 8001222: b087 sub sp, #28 8001224: af00 add r7, sp, #0 8001226: 6078 str r0, [r7, #4] 8001228: 460b mov r3, r1 800122a: 70fb strb r3, [r7, #3] 800122c: 4613 mov r3, r2 800122e: 70bb strb r3, [r7, #2] uint32_t i = 0; 8001230: 2300 movs r3, #0 8001232: 617b str r3, [r7, #20] uint32_t CurrApiAddress = 0; 8001234: 2300 movs r3, #0 8001236: 60fb str r3, [r7, #12] CurrApiAddress = FLASH_USER_USE_START_ADDR; 8001238: 4b33 ldr r3, [pc, #204] ; (8001308 ) 800123a: 60fb str r3, [r7, #12] uint8_t* Currdata = (uint8_t*)CurrApiAddress; 800123c: 68fb ldr r3, [r7, #12] 800123e: 60bb str r3, [r7, #8] uint8_t* pdata; data[i++] = 0x7E; 8001240: 697b ldr r3, [r7, #20] 8001242: 1c5a adds r2, r3, #1 8001244: 617a str r2, [r7, #20] 8001246: 687a ldr r2, [r7, #4] 8001248: 4413 add r3, r2 800124a: 227e movs r2, #126 ; 0x7e 800124c: 701a strb r2, [r3, #0] data[i++] = 0x7E; 800124e: 697b ldr r3, [r7, #20] 8001250: 1c5a adds r2, r3, #1 8001252: 617a str r2, [r7, #20] 8001254: 687a ldr r2, [r7, #4] 8001256: 4413 add r3, r2 8001258: 227e movs r2, #126 ; 0x7e 800125a: 701a strb r2, [r3, #0] data[i++] = mode;// ID 800125c: 697b ldr r3, [r7, #20] 800125e: 1c5a adds r2, r3, #1 8001260: 617a str r2, [r7, #20] 8001262: 687a ldr r2, [r7, #4] 8001264: 4413 add r3, r2 8001266: 78ba ldrb r2, [r7, #2] 8001268: 701a strb r2, [r3, #0] data[i++] = 0; // SEQ NUMBER 800126a: 697b ldr r3, [r7, #20] 800126c: 1c5a adds r2, r3, #1 800126e: 617a str r2, [r7, #20] 8001270: 687a ldr r2, [r7, #4] 8001272: 4413 add r3, r2 8001274: 2200 movs r2, #0 8001276: 701a strb r2, [r3, #0] data[i++] = 0; // SEQ NUMBER 8001278: 697b ldr r3, [r7, #20] 800127a: 1c5a adds r2, r3, #1 800127c: 617a str r2, [r7, #20] 800127e: 687a ldr r2, [r7, #4] 8001280: 4413 add r3, r2 8001282: 2200 movs r2, #0 8001284: 701a strb r2, [r3, #0] data[i++] = 0; // NessLab_Reserve0 8001286: 697b ldr r3, [r7, #20] 8001288: 1c5a adds r2, r3, #1 800128a: 617a str r2, [r7, #20] 800128c: 687a ldr r2, [r7, #4] 800128e: 4413 add r3, r2 8001290: 2200 movs r2, #0 8001292: 701a strb r2, [r3, #0] data[i++] = size; // Nesslab Size 8001294: 697b ldr r3, [r7, #20] 8001296: 1c5a adds r2, r3, #1 8001298: 617a str r2, [r7, #20] 800129a: 687a ldr r2, [r7, #4] 800129c: 4413 add r3, r2 800129e: 78fa ldrb r2, [r7, #3] 80012a0: 701a strb r2, [r3, #0] // NessLab_TalbleFlash_Read(&data[NessLab_DataLength + 1],100); for(int a = 0; a < size; a++){ 80012a2: 2300 movs r3, #0 80012a4: 613b str r3, [r7, #16] 80012a6: e00c b.n 80012c2 data[i++] = Currdata[a]; 80012a8: 693b ldr r3, [r7, #16] 80012aa: 68ba ldr r2, [r7, #8] 80012ac: 441a add r2, r3 80012ae: 697b ldr r3, [r7, #20] 80012b0: 1c59 adds r1, r3, #1 80012b2: 6179 str r1, [r7, #20] 80012b4: 6879 ldr r1, [r7, #4] 80012b6: 440b add r3, r1 80012b8: 7812 ldrb r2, [r2, #0] 80012ba: 701a strb r2, [r3, #0] for(int a = 0; a < size; a++){ 80012bc: 693b ldr r3, [r7, #16] 80012be: 3301 adds r3, #1 80012c0: 613b str r3, [r7, #16] 80012c2: 78fb ldrb r3, [r7, #3] 80012c4: 693a ldr r2, [r7, #16] 80012c6: 429a cmp r2, r3 80012c8: dbee blt.n 80012a8 // printf("%02x ",Currdata[i]); } data[i++] = NessLab_Checksum(&data[NessLab_MsgID0], 100 + 5); 80012ca: 687b ldr r3, [r7, #4] 80012cc: 1c98 adds r0, r3, #2 80012ce: 697b ldr r3, [r7, #20] 80012d0: 1c5a adds r2, r3, #1 80012d2: 617a str r2, [r7, #20] 80012d4: 687a ldr r2, [r7, #4] 80012d6: 18d4 adds r4, r2, r3 80012d8: 2169 movs r1, #105 ; 0x69 80012da: f000 fa6b bl 80017b4 80012de: 4603 mov r3, r0 80012e0: 7023 strb r3, [r4, #0] /* Exception Header Tail Checksum */ data[i++] = 0x7E; 80012e2: 697b ldr r3, [r7, #20] 80012e4: 1c5a adds r2, r3, #1 80012e6: 617a str r2, [r7, #20] 80012e8: 687a ldr r2, [r7, #4] 80012ea: 4413 add r3, r2 80012ec: 227e movs r2, #126 ; 0x7e 80012ee: 701a strb r2, [r3, #0] data[i++] = 0x7E; 80012f0: 697b ldr r3, [r7, #20] 80012f2: 1c5a adds r2, r3, #1 80012f4: 617a str r2, [r7, #20] 80012f6: 687a ldr r2, [r7, #4] 80012f8: 4413 add r3, r2 80012fa: 227e movs r2, #126 ; 0x7e 80012fc: 701a strb r2, [r3, #0] } 80012fe: bf00 nop 8001300: 371c adds r7, #28 8001302: 46bd mov sp, r7 8001304: bd90 pop {r4, r7, pc} 8001306: bf00 nop 8001308: 0800ff38 .word 0x0800ff38 0800130c : void NessLab_Status_Check(){ //HAL_GPIO_ReadPin(, GPIO_Pin) } void NessLab_PAU_Enable(){ 800130c: b598 push {r3, r4, r7, lr} 800130e: af00 add r7, sp, #0 #if 1 if( HAL_GPIO_ReadPin(PAU_EN_GPIO_Port, PAU_EN_Pin) != HAL_GPIO_ReadPin(AMP_EN_GPIO_Port, AMP_EN_Pin) ){ 8001310: f44f 4100 mov.w r1, #32768 ; 0x8000 8001314: 4817 ldr r0, [pc, #92] ; (8001374 ) 8001316: f002 f903 bl 8003520 800131a: 4603 mov r3, r0 800131c: 461c mov r4, r3 800131e: f44f 7180 mov.w r1, #256 ; 0x100 8001322: 4815 ldr r0, [pc, #84] ; (8001378 ) 8001324: f002 f8fc bl 8003520 8001328: 4603 mov r3, r0 800132a: 429c cmp r4, r3 800132c: d01f beq.n 800136e HAL_GPIO_WritePin(AMP_EN_GPIO_Port,AMP_EN_Pin, HAL_GPIO_ReadPin(PAU_EN_GPIO_Port, PAU_EN_Pin)); 800132e: f44f 4100 mov.w r1, #32768 ; 0x8000 8001332: 4810 ldr r0, [pc, #64] ; (8001374 ) 8001334: f002 f8f4 bl 8003520 8001338: 4603 mov r3, r0 800133a: 461a mov r2, r3 800133c: f44f 7180 mov.w r1, #256 ; 0x100 8001340: 480d ldr r0, [pc, #52] ; (8001378 ) 8001342: f002 f904 bl 800354e printf("HAL_GPIO_ReadPin(PAU_EN_GPIO_Port, PAU_EN_Pin) : %d \r\n",HAL_GPIO_ReadPin(PAU_EN_GPIO_Port, PAU_EN_Pin)); 8001346: f44f 4100 mov.w r1, #32768 ; 0x8000 800134a: 480a ldr r0, [pc, #40] ; (8001374 ) 800134c: f002 f8e8 bl 8003520 8001350: 4603 mov r3, r0 8001352: 4619 mov r1, r3 8001354: 4809 ldr r0, [pc, #36] ; (800137c ) 8001356: f005 fb03 bl 8006960 printf("AMP_EN_GPIO_Port : %d \r\n",HAL_GPIO_ReadPin(AMP_EN_GPIO_Port, AMP_EN_Pin)); 800135a: f44f 7180 mov.w r1, #256 ; 0x100 800135e: 4806 ldr r0, [pc, #24] ; (8001378 ) 8001360: f002 f8de bl 8003520 8001364: 4603 mov r3, r0 8001366: 4619 mov r1, r3 8001368: 4805 ldr r0, [pc, #20] ; (8001380 ) 800136a: f005 faf9 bl 8006960 #else HAL_GPIO_WritePin(AMP_EN_GPIO_Port,AMP_EN_Pin, 0); printf("AMP_EN_GPIO_Port : %d \r\n",HAL_GPIO_ReadPin(AMP_EN_GPIO_Port, AMP_EN_Pin)); #endif } 800136e: bf00 nop 8001370: bd98 pop {r3, r4, r7, pc} 8001372: bf00 nop 8001374: 40010c00 .word 0x40010c00 8001378: 40010800 .word 0x40010800 800137c: 080089b0 .word 0x080089b0 8001380: 080089e8 .word 0x080089e8 08001384 : void NessLab_GPIO_Operate(){ 8001384: b580 push {r7, lr} 8001386: af00 add r7, sp, #0 NessLab_PAU_Enable(); 8001388: f7ff ffc0 bl 800130c } 800138c: bf00 nop 800138e: bd80 pop {r7, pc} 08001390 : * ADC 0 :DL TX * ADC 1 :DL RX * ADC 2 :TEMP * */ void ADC_Value_Get(){ 8001390: b590 push {r4, r7, lr} 8001392: b083 sub sp, #12 8001394: af00 add r7, sp, #0 uint16_t CalcRet = 0 ; 8001396: 2300 movs r3, #0 8001398: 80fb strh r3, [r7, #6] uint16_t Tx_Det_Volt = ((ADC1value[0] * (3.3 / 4095))* 1000); 800139a: 4b31 ldr r3, [pc, #196] ; (8001460 ) 800139c: 881b ldrh r3, [r3, #0] 800139e: b29b uxth r3, r3 80013a0: 4618 mov r0, r3 80013a2: f7ff f88f bl 80004c4 <__aeabi_i2d> 80013a6: a32c add r3, pc, #176 ; (adr r3, 8001458 ) 80013a8: e9d3 2300 ldrd r2, r3, [r3] 80013ac: f7ff f8f4 bl 8000598 <__aeabi_dmul> 80013b0: 4603 mov r3, r0 80013b2: 460c mov r4, r1 80013b4: 4618 mov r0, r3 80013b6: 4621 mov r1, r4 80013b8: f04f 0200 mov.w r2, #0 80013bc: 4b29 ldr r3, [pc, #164] ; (8001464 ) 80013be: f7ff f8eb bl 8000598 <__aeabi_dmul> 80013c2: 4603 mov r3, r0 80013c4: 460c mov r4, r1 80013c6: 4618 mov r0, r3 80013c8: 4621 mov r1, r4 80013ca: f7ff fbbd bl 8000b48 <__aeabi_d2uiz> 80013ce: 4603 mov r3, r0 80013d0: 80bb strh r3, [r7, #4] uint16_t Rx_Det_Volt = ((ADC1value[1] * (3.3 / 4095))* 1000); 80013d2: 4b23 ldr r3, [pc, #140] ; (8001460 ) 80013d4: 885b ldrh r3, [r3, #2] 80013d6: b29b uxth r3, r3 80013d8: 4618 mov r0, r3 80013da: f7ff f873 bl 80004c4 <__aeabi_i2d> 80013de: a31e add r3, pc, #120 ; (adr r3, 8001458 ) 80013e0: e9d3 2300 ldrd r2, r3, [r3] 80013e4: f7ff f8d8 bl 8000598 <__aeabi_dmul> 80013e8: 4603 mov r3, r0 80013ea: 460c mov r4, r1 80013ec: 4618 mov r0, r3 80013ee: 4621 mov r1, r4 80013f0: f04f 0200 mov.w r2, #0 80013f4: 4b1b ldr r3, [pc, #108] ; (8001464 ) 80013f6: f7ff f8cf bl 8000598 <__aeabi_dmul> 80013fa: 4603 mov r3, r0 80013fc: 460c mov r4, r1 80013fe: 4618 mov r0, r3 8001400: 4621 mov r1, r4 8001402: f7ff fba1 bl 8000b48 <__aeabi_d2uiz> 8001406: 4603 mov r3, r0 8001408: 807b strh r3, [r7, #2] int8_t Real_Temperature = ADC_Convert_Temperature((ADC1value[2] * (3.3 / 4095))); 800140a: 4b15 ldr r3, [pc, #84] ; (8001460 ) 800140c: 889b ldrh r3, [r3, #4] 800140e: b29b uxth r3, r3 8001410: 4618 mov r0, r3 8001412: f7ff f857 bl 80004c4 <__aeabi_i2d> 8001416: a310 add r3, pc, #64 ; (adr r3, 8001458 ) 8001418: e9d3 2300 ldrd r2, r3, [r3] 800141c: f7ff f8bc bl 8000598 <__aeabi_dmul> 8001420: 4603 mov r3, r0 8001422: 460c mov r4, r1 8001424: 4618 mov r0, r3 8001426: 4621 mov r1, r4 8001428: f000 f834 bl 8001494 800142c: 4603 mov r3, r0 800142e: 707b strb r3, [r7, #1] // Currstatus.DownLink_Forward_Det_H = ((Tx_Det_Volt & 0xFF00) >> 8); // Currstatus.DownLink_Forward_Det_L = (Tx_Det_Volt & 0x00FF); // printf("Tx_Det_Volt : %d \r\n",Tx_Det_Volt); /*DL RX Calc*/ Currstatus.DownLink_Reverse_Det_H = ((Rx_Det_Volt & 0xFF00) >> 8); 8001430: 887b ldrh r3, [r7, #2] 8001432: 0a1b lsrs r3, r3, #8 8001434: b29b uxth r3, r3 8001436: b2da uxtb r2, r3 8001438: 4b0b ldr r3, [pc, #44] ; (8001468 ) 800143a: 725a strb r2, [r3, #9] Currstatus.DownLink_Reverse_Det_L = (Rx_Det_Volt & 0x00FF); 800143c: 887b ldrh r3, [r7, #2] 800143e: b2da uxtb r2, r3 8001440: 4b09 ldr r3, [pc, #36] ; (8001468 ) 8001442: 729a strb r2, [r3, #10] /*Temp Calc*/ Currstatus.Temp_Monitor = Real_Temperature; 8001444: 787a ldrb r2, [r7, #1] 8001446: 4b08 ldr r3, [pc, #32] ; (8001468 ) 8001448: 745a strb r2, [r3, #17] } 800144a: bf00 nop 800144c: 370c adds r7, #12 800144e: 46bd mov sp, r7 8001450: bd90 pop {r4, r7, pc} 8001452: bf00 nop 8001454: f3af 8000 nop.w 8001458: e734d9b4 .word 0xe734d9b4 800145c: 3f4a680c .word 0x3f4a680c 8001460: 200006c4 .word 0x200006c4 8001464: 408f4000 .word 0x408f4000 8001468: 200006ac .word 0x200006ac 0800146c : void ADC_Initialize(){ 800146c: b580 push {r7, lr} 800146e: af00 add r7, sp, #0 while(!(HAL_ADCEx_Calibration_Start(&hadc1)==HAL_OK)); 8001470: bf00 nop 8001472: 4806 ldr r0, [pc, #24] ; (800148c ) 8001474: f001 f910 bl 8002698 8001478: 4603 mov r3, r0 800147a: 2b00 cmp r3, #0 800147c: d1f9 bne.n 8001472 HAL_ADC_Start_DMA(&hadc1, (uint16_t*)ADC1value,(uint32_t) 3); 800147e: 2203 movs r2, #3 8001480: 4903 ldr r1, [pc, #12] ; (8001490 ) 8001482: 4802 ldr r0, [pc, #8] ; (800148c ) 8001484: f000 fda6 bl 8001fd4 } 8001488: bf00 nop 800148a: bd80 pop {r7, pc} 800148c: 20000a1c .word 0x20000a1c 8001490: 200006c4 .word 0x200006c4 08001494 : uint8_t ADC_Convert_Temperature(double val){ 8001494: b590 push {r4, r7, lr} 8001496: b087 sub sp, #28 8001498: af00 add r7, sp, #0 800149a: e9c7 0100 strd r0, r1, [r7] int16_t ref_0temp = 500; 800149e: f44f 73fa mov.w r3, #500 ; 0x1f4 80014a2: 817b strh r3, [r7, #10] int16_t ret = val * 1000; 80014a4: f04f 0200 mov.w r2, #0 80014a8: 4b27 ldr r3, [pc, #156] ; (8001548 ) 80014aa: e9d7 0100 ldrd r0, r1, [r7] 80014ae: f7ff f873 bl 8000598 <__aeabi_dmul> 80014b2: 4603 mov r3, r0 80014b4: 460c mov r4, r1 80014b6: 4618 mov r0, r3 80014b8: 4621 mov r1, r4 80014ba: f7ff fb1d bl 8000af8 <__aeabi_d2iz> 80014be: 4603 mov r3, r0 80014c0: 813b strh r3, [r7, #8] int8_t cnt = 0; 80014c2: 2300 movs r3, #0 80014c4: 75fb strb r3, [r7, #23] printf("ret : %d \r\n", ret); 80014c6: f9b7 3008 ldrsh.w r3, [r7, #8] 80014ca: 4619 mov r1, r3 80014cc: 481f ldr r0, [pc, #124] ; (800154c ) 80014ce: f005 fa47 bl 8006960 if( ret - ref_0temp > 0){ 80014d2: f9b7 2008 ldrsh.w r2, [r7, #8] 80014d6: f9b7 300a ldrsh.w r3, [r7, #10] 80014da: 1ad3 subs r3, r2, r3 80014dc: 2b00 cmp r3, #0 80014de: dd14 ble.n 800150a for(int i = 0; i < ret - ref_0temp; i += 10){ 80014e0: 2300 movs r3, #0 80014e2: 613b str r3, [r7, #16] 80014e4: e008 b.n 80014f8 cnt++; 80014e6: f997 3017 ldrsb.w r3, [r7, #23] 80014ea: b2db uxtb r3, r3 80014ec: 3301 adds r3, #1 80014ee: b2db uxtb r3, r3 80014f0: 75fb strb r3, [r7, #23] for(int i = 0; i < ret - ref_0temp; i += 10){ 80014f2: 693b ldr r3, [r7, #16] 80014f4: 330a adds r3, #10 80014f6: 613b str r3, [r7, #16] 80014f8: f9b7 2008 ldrsh.w r2, [r7, #8] 80014fc: f9b7 300a ldrsh.w r3, [r7, #10] 8001500: 1ad3 subs r3, r2, r3 8001502: 693a ldr r2, [r7, #16] 8001504: 429a cmp r2, r3 8001506: dbee blt.n 80014e6 8001508: e013 b.n 8001532 } }else{ for(int i = 0; i > ret - ref_0temp; i -= 10){ 800150a: 2300 movs r3, #0 800150c: 60fb str r3, [r7, #12] 800150e: e008 b.n 8001522 cnt--; 8001510: f997 3017 ldrsb.w r3, [r7, #23] 8001514: b2db uxtb r3, r3 8001516: 3b01 subs r3, #1 8001518: b2db uxtb r3, r3 800151a: 75fb strb r3, [r7, #23] for(int i = 0; i > ret - ref_0temp; i -= 10){ 800151c: 68fb ldr r3, [r7, #12] 800151e: 3b0a subs r3, #10 8001520: 60fb str r3, [r7, #12] 8001522: f9b7 2008 ldrsh.w r2, [r7, #8] 8001526: f9b7 300a ldrsh.w r3, [r7, #10] 800152a: 1ad3 subs r3, r2, r3 800152c: 68fa ldr r2, [r7, #12] 800152e: 429a cmp r2, r3 8001530: dcee bgt.n 8001510 } } printf("Temp : %d\r\n",cnt); 8001532: f997 3017 ldrsb.w r3, [r7, #23] 8001536: 4619 mov r1, r3 8001538: 4805 ldr r0, [pc, #20] ; (8001550 ) 800153a: f005 fa11 bl 8006960 return cnt; 800153e: 7dfb ldrb r3, [r7, #23] } 8001540: 4618 mov r0, r3 8001542: 371c adds r7, #28 8001544: 46bd mov sp, r7 8001546: bd90 pop {r4, r7, pc} 8001548: 408f4000 .word 0x408f4000 800154c: 08008a04 .word 0x08008a04 8001550: 08008a10 .word 0x08008a10 08001554 : uint32_t SumFunc(uint32_t* data,uint16_t size){ 8001554: b480 push {r7} 8001556: b085 sub sp, #20 8001558: af00 add r7, sp, #0 800155a: 6078 str r0, [r7, #4] 800155c: 460b mov r3, r1 800155e: 807b strh r3, [r7, #2] uint32_t ret = 0; 8001560: 2300 movs r3, #0 8001562: 60fb str r3, [r7, #12] for (uint16_t i = 0; i < size; i++) // 배열의 요소 개수만큼 반복 8001564: 2300 movs r3, #0 8001566: 817b strh r3, [r7, #10] 8001568: e00a b.n 8001580 { ret += data[i]; // sum과 배열의 요소를 더해서 다시 sum에 저장 800156a: 897b ldrh r3, [r7, #10] 800156c: 009b lsls r3, r3, #2 800156e: 687a ldr r2, [r7, #4] 8001570: 4413 add r3, r2 8001572: 681b ldr r3, [r3, #0] 8001574: 68fa ldr r2, [r7, #12] 8001576: 4413 add r3, r2 8001578: 60fb str r3, [r7, #12] for (uint16_t i = 0; i < size; i++) // 배열의 요소 개수만큼 반복 800157a: 897b ldrh r3, [r7, #10] 800157c: 3301 adds r3, #1 800157e: 817b strh r3, [r7, #10] 8001580: 897a ldrh r2, [r7, #10] 8001582: 887b ldrh r3, [r7, #2] 8001584: 429a cmp r2, r3 8001586: d3f0 bcc.n 800156a // printf("ret : %d data[%d] \r\n",ret,i,data[i]); } return ret; 8001588: 68fb ldr r3, [r7, #12] } 800158a: 4618 mov r0, r3 800158c: 3714 adds r7, #20 800158e: 46bd mov sp, r7 8001590: bc80 pop {r7} 8001592: 4770 bx lr 08001594 : void DascendigFunc(int32_t* src,uint32_t size ){ 8001594: b480 push {r7} 8001596: b087 sub sp, #28 8001598: af00 add r7, sp, #0 800159a: 6078 str r0, [r7, #4] 800159c: 6039 str r1, [r7, #0] int32_t temp; for(int i = 0 ; i < size - 1 ; i ++) { 800159e: 2300 movs r3, #0 80015a0: 617b str r3, [r7, #20] 80015a2: e02f b.n 8001604 for(int j = i+1 ; j < size ; j ++) { 80015a4: 697b ldr r3, [r7, #20] 80015a6: 3301 adds r3, #1 80015a8: 613b str r3, [r7, #16] 80015aa: e024 b.n 80015f6 if(src[i] < src[j]) { 80015ac: 697b ldr r3, [r7, #20] 80015ae: 009b lsls r3, r3, #2 80015b0: 687a ldr r2, [r7, #4] 80015b2: 4413 add r3, r2 80015b4: 681a ldr r2, [r3, #0] 80015b6: 693b ldr r3, [r7, #16] 80015b8: 009b lsls r3, r3, #2 80015ba: 6879 ldr r1, [r7, #4] 80015bc: 440b add r3, r1 80015be: 681b ldr r3, [r3, #0] 80015c0: 429a cmp r2, r3 80015c2: da15 bge.n 80015f0 temp = src[j]; 80015c4: 693b ldr r3, [r7, #16] 80015c6: 009b lsls r3, r3, #2 80015c8: 687a ldr r2, [r7, #4] 80015ca: 4413 add r3, r2 80015cc: 681b ldr r3, [r3, #0] 80015ce: 60fb str r3, [r7, #12] src[j] = src[i]; 80015d0: 697b ldr r3, [r7, #20] 80015d2: 009b lsls r3, r3, #2 80015d4: 687a ldr r2, [r7, #4] 80015d6: 441a add r2, r3 80015d8: 693b ldr r3, [r7, #16] 80015da: 009b lsls r3, r3, #2 80015dc: 6879 ldr r1, [r7, #4] 80015de: 440b add r3, r1 80015e0: 6812 ldr r2, [r2, #0] 80015e2: 601a str r2, [r3, #0] src[i] = temp; 80015e4: 697b ldr r3, [r7, #20] 80015e6: 009b lsls r3, r3, #2 80015e8: 687a ldr r2, [r7, #4] 80015ea: 4413 add r3, r2 80015ec: 68fa ldr r2, [r7, #12] 80015ee: 601a str r2, [r3, #0] for(int j = i+1 ; j < size ; j ++) { 80015f0: 693b ldr r3, [r7, #16] 80015f2: 3301 adds r3, #1 80015f4: 613b str r3, [r7, #16] 80015f6: 693b ldr r3, [r7, #16] 80015f8: 683a ldr r2, [r7, #0] 80015fa: 429a cmp r2, r3 80015fc: d8d6 bhi.n 80015ac for(int i = 0 ; i < size - 1 ; i ++) { 80015fe: 697b ldr r3, [r7, #20] 8001600: 3301 adds r3, #1 8001602: 617b str r3, [r7, #20] 8001604: 683b ldr r3, [r7, #0] 8001606: 1e5a subs r2, r3, #1 8001608: 697b ldr r3, [r7, #20] 800160a: 429a cmp r2, r3 800160c: d8ca bhi.n 80015a4 // printf("temp"); } } } } 800160e: bf00 nop 8001610: 371c adds r7, #28 8001612: 46bd mov sp, r7 8001614: bc80 pop {r7} 8001616: 4770 bx lr 08001618 : #define Percent100 5 void ADC_Check(){ 8001618: b580 push {r7, lr} 800161a: b082 sub sp, #8 800161c: af00 add r7, sp, #0 float tempval = 0; 800161e: f04f 0300 mov.w r3, #0 8001622: 603b str r3, [r7, #0] for(int i = 0; i < 3 ; i++) 8001624: 2300 movs r3, #0 8001626: 607b str r3, [r7, #4] 8001628: e00c b.n 8001644 printf("ADC1value[%d] : %d \r\n",i,ADC1value[i]); 800162a: 4a0b ldr r2, [pc, #44] ; (8001658 ) 800162c: 687b ldr r3, [r7, #4] 800162e: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8001632: b29b uxth r3, r3 8001634: 461a mov r2, r3 8001636: 6879 ldr r1, [r7, #4] 8001638: 4808 ldr r0, [pc, #32] ; (800165c ) 800163a: f005 f991 bl 8006960 for(int i = 0; i < 3 ; i++) 800163e: 687b ldr r3, [r7, #4] 8001640: 3301 adds r3, #1 8001642: 607b str r3, [r7, #4] 8001644: 687b ldr r3, [r7, #4] 8001646: 2b02 cmp r3, #2 8001648: ddef ble.n 800162a Currstatus.DownLink_Forward_Det_H = (((uint16_t)tempval & 0xFF00) >> 8); Currstatus.DownLink_Forward_Det_L = (((uint16_t)tempval & 0x00FF) ); #endif // PYJ.2020.09.09_END -- ADC_Value_Get(); 800164a: f7ff fea1 bl 8001390 // Currstatus.Temp_Monitor = ADC_Convert_Temperature((ADC1value[2]/1000)); // printf("Currstatus.DownLink_Forward_Det : %d \r\n",Currstatus.DownLink_Forward_Det_H << 8 | Currstatus.DownLink_Forward_Det_L); } 800164e: bf00 nop 8001650: 3708 adds r7, #8 8001652: 46bd mov sp, r7 8001654: bd80 pop {r7, pc} 8001656: bf00 nop 8001658: 200006c4 .word 0x200006c4 800165c: 08008a1c .word 0x08008a1c 08001660 : void ADC_TDD_Arrange(){ 8001660: b580 push {r7, lr} 8001662: b082 sub sp, #8 8001664: af00 add r7, sp, #0 uint32_t ADC1_Average_value = 0; 8001666: 2300 movs r3, #0 8001668: 603b str r3, [r7, #0] if(TDD_125ms_Cnt > 125) 800166a: 4b1b ldr r3, [pc, #108] ; (80016d8 ) 800166c: 681b ldr r3, [r3, #0] 800166e: 2b7d cmp r3, #125 ; 0x7d 8001670: d92d bls.n 80016ce { // printf("================TotalCnt %d =================\r\n",TotalCnt); #if 1 // PYJ.2020.09.09_BEGIN -- DascendigFunc(&ADC1_Arrage_Ret[0],ADC_AVERAGECNT); 8001672: 2164 movs r1, #100 ; 0x64 8001674: 4819 ldr r0, [pc, #100] ; (80016dc ) 8001676: f7ff ff8d bl 8001594 // for(int i = 0; i < 100; i++){/*ADC Data Dascending Complete*/ // printf("ADC1_Arrage_Ret[%d] : %d \r\n",i,ADC1_Arrage_Ret[i]); // } ADC1_Average_value = SumFunc(&ADC1_Arrage_Ret[0],Percent100); 800167a: 2105 movs r1, #5 800167c: 4817 ldr r0, [pc, #92] ; (80016dc ) 800167e: f7ff ff69 bl 8001554 8001682: 6038 str r0, [r7, #0] // printf("ADC1_Average_value Sum : %d \r\n",ADC1_Average_value); ADC1_Average_value /=Percent100; 8001684: 683b ldr r3, [r7, #0] 8001686: 4a16 ldr r2, [pc, #88] ; (80016e0 ) 8001688: fba2 2303 umull r2, r3, r2, r3 800168c: 089b lsrs r3, r3, #2 800168e: 603b str r3, [r7, #0] // printf("ADC1_Average_value : %d \r\n",ADC1_Average_value); for(int i = 0; i < ADC_AVERAGECNT; i++){ 8001690: 2300 movs r3, #0 8001692: 607b str r3, [r7, #4] 8001694: e007 b.n 80016a6 ADC1_Arrage_Ret[i] = 0; 8001696: 4a11 ldr r2, [pc, #68] ; (80016dc ) 8001698: 687b ldr r3, [r7, #4] 800169a: 2100 movs r1, #0 800169c: f842 1023 str.w r1, [r2, r3, lsl #2] for(int i = 0; i < ADC_AVERAGECNT; i++){ 80016a0: 687b ldr r3, [r7, #4] 80016a2: 3301 adds r3, #1 80016a4: 607b str r3, [r7, #4] 80016a6: 687b ldr r3, [r7, #4] 80016a8: 2b63 cmp r3, #99 ; 0x63 80016aa: ddf4 ble.n 8001696 } Currstatus.DownLink_Forward_Det_H = (((uint16_t)ADC1_Average_value & 0xFF00) >> 8); 80016ac: 683b ldr r3, [r7, #0] 80016ae: b29b uxth r3, r3 80016b0: 0a1b lsrs r3, r3, #8 80016b2: b29b uxth r3, r3 80016b4: b2da uxtb r2, r3 80016b6: 4b0b ldr r3, [pc, #44] ; (80016e4 ) 80016b8: 71da strb r2, [r3, #7] Currstatus.DownLink_Forward_Det_L = (((uint16_t)ADC1_Average_value & 0x00FF) ); 80016ba: 683b ldr r3, [r7, #0] 80016bc: b2da uxtb r2, r3 80016be: 4b09 ldr r3, [pc, #36] ; (80016e4 ) 80016c0: 721a strb r2, [r3, #8] ADC1_Arrage_Ret[i] = ADC1_Arrage[i]; } #endif // PYJ.2020.09.09_END -- TotalCnt = 0; 80016c2: 4b09 ldr r3, [pc, #36] ; (80016e8 ) 80016c4: 2200 movs r2, #0 80016c6: 601a str r2, [r3, #0] TDD_125ms_Cnt = 0; 80016c8: 4b03 ldr r3, [pc, #12] ; (80016d8 ) 80016ca: 2200 movs r2, #0 80016cc: 601a str r2, [r3, #0] } } 80016ce: bf00 nop 80016d0: 3708 adds r7, #8 80016d2: 46bd mov sp, r7 80016d4: bd80 pop {r7, pc} 80016d6: bf00 nop 80016d8: 20000634 .word 0x20000634 80016dc: 20000458 .word 0x20000458 80016e0: cccccccd .word 0xcccccccd 80016e4: 200006ac .word 0x200006ac 80016e8: 200005ec .word 0x200005ec 080016ec : void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) { 80016ec: b580 push {r7, lr} 80016ee: b084 sub sp, #16 80016f0: af00 add r7, sp, #0 80016f2: 6078 str r0, [r7, #4] if(hadc->Instance == hadc1.Instance && TDD_125ms_Cnt < 125) 80016f4: 687b ldr r3, [r7, #4] 80016f6: 681a ldr r2, [r3, #0] 80016f8: 4b27 ldr r3, [pc, #156] ; (8001798 ) 80016fa: 681b ldr r3, [r3, #0] 80016fc: 429a cmp r2, r3 80016fe: d147 bne.n 8001790 8001700: 4b26 ldr r3, [pc, #152] ; (800179c ) 8001702: 681b ldr r3, [r3, #0] 8001704: 2b7c cmp r3, #124 ; 0x7c 8001706: d843 bhi.n 8001790 { ADC1_Arrage[adc1cnt] = ADC1value[0]; 8001708: 4b25 ldr r3, [pc, #148] ; (80017a0 ) 800170a: 881b ldrh r3, [r3, #0] 800170c: 461a mov r2, r3 800170e: 4b25 ldr r3, [pc, #148] ; (80017a4 ) 8001710: 881b ldrh r3, [r3, #0] 8001712: b299 uxth r1, r3 8001714: 4b24 ldr r3, [pc, #144] ; (80017a8 ) 8001716: f823 1012 strh.w r1, [r3, r2, lsl #1] // for(int i = 0; i < 2; i++){ // printf("ADC1value[%d] : %d , %f\r\n",i,ADC1value[i],(float)((ADC1value[i]) *3.3 /4095)); // } adc1cnt++; 800171a: 4b21 ldr r3, [pc, #132] ; (80017a0 ) 800171c: 881b ldrh r3, [r3, #0] 800171e: 3301 adds r3, #1 8001720: b29a uxth r2, r3 8001722: 4b1f ldr r3, [pc, #124] ; (80017a0 ) 8001724: 801a strh r2, [r3, #0] if(adc1cnt == ADC_AVERAGECNT){ 8001726: 4b1e ldr r3, [pc, #120] ; (80017a0 ) 8001728: 881b ldrh r3, [r3, #0] 800172a: 2b64 cmp r3, #100 ; 0x64 800172c: d130 bne.n 8001790 // DascendigFunc(&ADC1_Arrage[0],ADC_AVERAGECNT); adc1cnt = 0; 800172e: 4b1c ldr r3, [pc, #112] ; (80017a0 ) 8001730: 2200 movs r2, #0 8001732: 801a strh r2, [r3, #0] TotalCnt++; 8001734: 4b1d ldr r3, [pc, #116] ; (80017ac ) 8001736: 681b ldr r3, [r3, #0] 8001738: 3301 adds r3, #1 800173a: 4a1c ldr r2, [pc, #112] ; (80017ac ) 800173c: 6013 str r3, [r2, #0] if(TotalCnt > 2) 800173e: 4b1b ldr r3, [pc, #108] ; (80017ac ) 8001740: 681b ldr r3, [r3, #0] 8001742: 2b02 cmp r3, #2 8001744: d902 bls.n 800174c TotalCnt = 2; 8001746: 4b19 ldr r3, [pc, #100] ; (80017ac ) 8001748: 2202 movs r2, #2 800174a: 601a str r2, [r3, #0] for(int i = 0; i < 100; i++){/*ADC Data Dascending Complete*/ 800174c: 2300 movs r3, #0 800174e: 60fb str r3, [r7, #12] 8001750: e017 b.n 8001782 if(ADC1_Arrage_Ret[i] <= ADC1_Arrage[i]) 8001752: 4a17 ldr r2, [pc, #92] ; (80017b0 ) 8001754: 68fb ldr r3, [r7, #12] 8001756: f852 3023 ldr.w r3, [r2, r3, lsl #2] 800175a: 4913 ldr r1, [pc, #76] ; (80017a8 ) 800175c: 68fa ldr r2, [r7, #12] 800175e: f831 2012 ldrh.w r2, [r1, r2, lsl #1] 8001762: b292 uxth r2, r2 8001764: 4293 cmp r3, r2 8001766: d809 bhi.n 800177c ADC1_Arrage_Ret[i] = ADC1_Arrage[i]; 8001768: 4a0f ldr r2, [pc, #60] ; (80017a8 ) 800176a: 68fb ldr r3, [r7, #12] 800176c: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8001770: b29b uxth r3, r3 8001772: 4619 mov r1, r3 8001774: 4a0e ldr r2, [pc, #56] ; (80017b0 ) 8001776: 68fb ldr r3, [r7, #12] 8001778: f842 1023 str.w r1, [r2, r3, lsl #2] for(int i = 0; i < 100; i++){/*ADC Data Dascending Complete*/ 800177c: 68fb ldr r3, [r7, #12] 800177e: 3301 adds r3, #1 8001780: 60fb str r3, [r7, #12] 8001782: 68fb ldr r3, [r7, #12] 8001784: 2b63 cmp r3, #99 ; 0x63 8001786: dde4 ble.n 8001752 } DascendigFunc(&ADC1_Arrage_Ret[0],ADC_AVERAGECNT); 8001788: 2164 movs r1, #100 ; 0x64 800178a: 4809 ldr r0, [pc, #36] ; (80017b0 ) 800178c: f7ff ff02 bl 8001594 // ADC1valuearray[i][adc1cnt] = ADC1value[i]; // } // adc1cnt++; // } } } 8001790: bf00 nop 8001792: 3710 adds r7, #16 8001794: 46bd mov sp, r7 8001796: bd80 pop {r7, pc} 8001798: 20000a1c .word 0x20000a1c 800179c: 20000634 .word 0x20000634 80017a0: 200005e8 .word 0x200005e8 80017a4: 200006c4 .word 0x200006c4 80017a8: 20000390 .word 0x20000390 80017ac: 200005ec .word 0x200005ec 80017b0: 20000458 .word 0x20000458 080017b4 : crcret ^ ~0U; return (crcret == checksum ? CHECKSUM_ERROR : NO_ERROR); } uint8_t NessLab_Checksum(uint8_t *data,uint8_t size){ 80017b4: b480 push {r7} 80017b6: b085 sub sp, #20 80017b8: af00 add r7, sp, #0 80017ba: 6078 str r0, [r7, #4] 80017bc: 460b mov r3, r1 80017be: 70fb strb r3, [r7, #3] uint16_t ret = 0; 80017c0: 2300 movs r3, #0 80017c2: 81fb strh r3, [r7, #14] // printf("Crc Process : "); for(int i = 0; i < size; i++){ 80017c4: 2300 movs r3, #0 80017c6: 60bb str r3, [r7, #8] 80017c8: e00c b.n 80017e4 ret = ((ret + data[i]) & 0xFF); 80017ca: 68bb ldr r3, [r7, #8] 80017cc: 687a ldr r2, [r7, #4] 80017ce: 4413 add r3, r2 80017d0: 781b ldrb r3, [r3, #0] 80017d2: b29a uxth r2, r3 80017d4: 89fb ldrh r3, [r7, #14] 80017d6: 4413 add r3, r2 80017d8: b29b uxth r3, r3 80017da: b2db uxtb r3, r3 80017dc: 81fb strh r3, [r7, #14] for(int i = 0; i < size; i++){ 80017de: 68bb ldr r3, [r7, #8] 80017e0: 3301 adds r3, #1 80017e2: 60bb str r3, [r7, #8] 80017e4: 78fb ldrb r3, [r7, #3] 80017e6: 68ba ldr r2, [r7, #8] 80017e8: 429a cmp r2, r3 80017ea: dbee blt.n 80017ca // printf(" %x + %x \r\n",ret,data[i]); } // printf("Result : "); ret = (~ret) + 1; 80017ec: 89fb ldrh r3, [r7, #14] 80017ee: 425b negs r3, r3 80017f0: 81fb strh r3, [r7, #14] // printf("ret [i] : %x \r\n",ret); return (uint8_t)(ret & 0x00FF); 80017f2: 89fb ldrh r3, [r7, #14] 80017f4: b2db uxtb r3, r3 } 80017f6: 4618 mov r0, r3 80017f8: 3714 adds r7, #20 80017fa: 46bd mov sp, r7 80017fc: bc80 pop {r7} 80017fe: 4770 bx lr 08001800 : bool NessLab_CheckSum_Check(uint8_t* data,uint8_t size,uint8_t checksum){ 8001800: b580 push {r7, lr} 8001802: b084 sub sp, #16 8001804: af00 add r7, sp, #0 8001806: 6078 str r0, [r7, #4] 8001808: 460b mov r3, r1 800180a: 70fb strb r3, [r7, #3] 800180c: 4613 mov r3, r2 800180e: 70bb strb r3, [r7, #2] uint8_t dataret = 0; 8001810: 2300 movs r3, #0 8001812: 73fb strb r3, [r7, #15] bool ret = false; 8001814: 2300 movs r3, #0 8001816: 73bb strb r3, [r7, #14] // printf("size : %d \r\n",size); for(int i = 0; i < size; i++){ 8001818: 2300 movs r3, #0 800181a: 60bb str r3, [r7, #8] 800181c: e009 b.n 8001832 dataret += data[i]; 800181e: 68bb ldr r3, [r7, #8] 8001820: 687a ldr r2, [r7, #4] 8001822: 4413 add r3, r2 8001824: 781a ldrb r2, [r3, #0] 8001826: 7bfb ldrb r3, [r7, #15] 8001828: 4413 add r3, r2 800182a: 73fb strb r3, [r7, #15] for(int i = 0; i < size; i++){ 800182c: 68bb ldr r3, [r7, #8] 800182e: 3301 adds r3, #1 8001830: 60bb str r3, [r7, #8] 8001832: 78fb ldrb r3, [r7, #3] 8001834: 68ba ldr r2, [r7, #8] 8001836: 429a cmp r2, r3 8001838: dbf1 blt.n 800181e // printf("data [i] : %x \r\n",data[i]); } dataret = (~dataret) + 1; 800183a: 7bfb ldrb r3, [r7, #15] 800183c: 425b negs r3, r3 800183e: 73fb strb r3, [r7, #15] printf("\r\ndataret : %x /// checksum : %x \r\n",dataret,checksum); 8001840: 7bfb ldrb r3, [r7, #15] 8001842: 78ba ldrb r2, [r7, #2] 8001844: 4619 mov r1, r3 8001846: 4808 ldr r0, [pc, #32] ; (8001868 ) 8001848: f005 f88a bl 8006960 if(dataret != checksum){ 800184c: 7bfa ldrb r2, [r7, #15] 800184e: 78bb ldrb r3, [r7, #2] 8001850: 429a cmp r2, r3 8001852: d002 beq.n 800185a ret = false; 8001854: 2300 movs r3, #0 8001856: 73bb strb r3, [r7, #14] 8001858: e001 b.n 800185e }else{ ret = true; 800185a: 2301 movs r3, #1 800185c: 73bb strb r3, [r7, #14] } return ret; 800185e: 7bbb ldrb r3, [r7, #14] } 8001860: 4618 mov r0, r3 8001862: 3710 adds r7, #16 8001864: 46bd mov sp, r7 8001866: bd80 pop {r7, pc} 8001868: 08008a34 .word 0x08008a34 0800186c : __set_MSP(*(__IO uint32_t*) APPLICATION_ADDRESS); jump_to_app(); } bool EraseInit = false; void DataErase_Func(uint32_t User_Address,uint32_t size){ 800186c: b580 push {r7, lr} 800186e: b082 sub sp, #8 8001870: af00 add r7, sp, #0 8001872: 6078 str r0, [r7, #4] 8001874: 6039 str r1, [r7, #0] static FLASH_EraseInitTypeDef EraseInitStruct; static uint32_t PAGEError = 0; HAL_FLASH_Unlock(); 8001876: f001 fb69 bl 8002f4c EraseInitStruct.TypeErase = FLASH_TYPEERASE_PAGES; 800187a: 4b1b ldr r3, [pc, #108] ; (80018e8 ) 800187c: 2200 movs r2, #0 800187e: 601a str r2, [r3, #0] EraseInitStruct.PageAddress = FLASH_USER_USE_START_ADDR; 8001880: 4b19 ldr r3, [pc, #100] ; (80018e8 ) 8001882: 4a1a ldr r2, [pc, #104] ; (80018ec ) 8001884: 609a str r2, [r3, #8] EraseInitStruct.NbPages = ((FLASH_USER_END_ADDR - FLASH_USER_USE_START_ADDR) / FLASH_PAGE_SIZE) + 1; 8001886: 4b18 ldr r3, [pc, #96] ; (80018e8 ) 8001888: 2201 movs r2, #1 800188a: 60da str r2, [r3, #12] UserAddress = User_Address; 800188c: 4a18 ldr r2, [pc, #96] ; (80018f0 ) 800188e: 687b ldr r3, [r7, #4] 8001890: 6013 str r3, [r2, #0] printf("NbPages : %x \r\n",EraseInitStruct.NbPages ); 8001892: 4b15 ldr r3, [pc, #84] ; (80018e8 ) 8001894: 68db ldr r3, [r3, #12] 8001896: 4619 mov r1, r3 8001898: 4816 ldr r0, [pc, #88] ; (80018f4 ) 800189a: f005 f861 bl 8006960 printf("EraseInitStruct.PageAddress : %x \r\n",EraseInitStruct.PageAddress); 800189e: 4b12 ldr r3, [pc, #72] ; (80018e8 ) 80018a0: 689b ldr r3, [r3, #8] 80018a2: 4619 mov r1, r3 80018a4: 4814 ldr r0, [pc, #80] ; (80018f8 ) 80018a6: f005 f85b bl 8006960 printf("Erase Start\r\n"); 80018aa: 4814 ldr r0, [pc, #80] ; (80018fc ) 80018ac: f005 f8cc bl 8006a48 if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK) 80018b0: 4913 ldr r1, [pc, #76] ; (8001900 ) 80018b2: 480d ldr r0, [pc, #52] ; (80018e8 ) 80018b4: f001 fc32 bl 800311c 80018b8: 4603 mov r3, r0 80018ba: 2b00 cmp r3, #0 80018bc: d007 beq.n 80018ce */ /* Infinite loop */ while (1) { /* Make LED2 blink (100ms on, 2s off) to indicate error in Erase operation */ printf("HAL_FLASHEx_Erase Error\r\n"); 80018be: 4811 ldr r0, [pc, #68] ; (8001904 ) 80018c0: f005 f8c2 bl 8006a48 HAL_Delay(2000); 80018c4: f44f 60fa mov.w r0, #2000 ; 0x7d0 80018c8: f000 fa8a bl 8001de0 printf("HAL_FLASHEx_Erase Error\r\n"); 80018cc: e7f7 b.n 80018be } } EraseInit = true; 80018ce: 4b0e ldr r3, [pc, #56] ; (8001908 ) 80018d0: 2201 movs r2, #1 80018d2: 701a strb r2, [r3, #0] printf("Erase End\r\n"); 80018d4: 480d ldr r0, [pc, #52] ; (800190c ) 80018d6: f005 f8b7 bl 8006a48 HAL_FLASH_Lock(); 80018da: f001 fb5d bl 8002f98 } 80018de: bf00 nop 80018e0: 3708 adds r7, #8 80018e2: 46bd mov sp, r7 80018e4: bd80 pop {r7, pc} 80018e6: bf00 nop 80018e8: 200005f8 .word 0x200005f8 80018ec: 0800ff38 .word 0x0800ff38 80018f0: 200005f0 .word 0x200005f0 80018f4: 08008a74 .word 0x08008a74 80018f8: 08008a84 .word 0x08008a84 80018fc: 08008aa8 .word 0x08008aa8 8001900: 20000608 .word 0x20000608 8001904: 08008ab8 .word 0x08008ab8 8001908: 200005f4 .word 0x200005f4 800190c: 08008ad4 .word 0x08008ad4 08001910 : uint8_t FLASH_Write_Func(uint32_t User_Address,uint8_t* data,uint32_t size){ 8001910: b590 push {r4, r7, lr} 8001912: b08b sub sp, #44 ; 0x2c 8001914: af00 add r7, sp, #0 8001916: 60f8 str r0, [r7, #12] 8001918: 60b9 str r1, [r7, #8] 800191a: 607a str r2, [r7, #4] //static FLASH_EraseInitTypeDef EraseInitStruct; //static uint32_t PAGEError = 0; static uint32_t DownloadIndex; static __IO uint32_t data32 = 0 , MemoryProgramStatus = 0; int dataindex = 0; 800191c: 2300 movs r3, #0 800191e: 623b str r3, [r7, #32] uint32_t writedata = 0; 8001920: 2300 movs r3, #0 8001922: 61fb str r3, [r7, #28] uint32_t CurrApiAddress = 0; 8001924: 2300 movs r3, #0 8001926: 61bb str r3, [r7, #24] uint8_t ret = 0; 8001928: 2300 movs r3, #0 800192a: 75fb strb r3, [r7, #23] CurrApiAddress = User_Address; 800192c: 68fb ldr r3, [r7, #12] 800192e: 61bb str r3, [r7, #24] uint8_t* Currdata = (uint8_t*)CurrApiAddress; 8001930: 69bb ldr r3, [r7, #24] 8001932: 613b str r3, [r7, #16] printf("HAL_FLASH_Program Start\r\n"); 8001934: 4833 ldr r0, [pc, #204] ; (8001a04 ) 8001936: f005 f887 bl 8006a48 DownloadIndex += size; 800193a: 4b33 ldr r3, [pc, #204] ; (8001a08 ) 800193c: 681a ldr r2, [r3, #0] 800193e: 687b ldr r3, [r7, #4] 8001940: 4413 add r3, r2 8001942: 4a31 ldr r2, [pc, #196] ; (8001a08 ) 8001944: 6013 str r3, [r2, #0] printf("User_Address : %x \r\n",UserAddress); 8001946: 4b31 ldr r3, [pc, #196] ; (8001a0c ) 8001948: 681b ldr r3, [r3, #0] 800194a: 4619 mov r1, r3 800194c: 4830 ldr r0, [pc, #192] ; (8001a10 ) 800194e: f005 f807 bl 8006960 HAL_FLASH_Unlock(); 8001952: f001 fafb bl 8002f4c for(int downindex = 0; downindex < size; downindex+=4) 8001956: 2300 movs r3, #0 8001958: 627b str r3, [r7, #36] ; 0x24 800195a: e041 b.n 80019e0 { writedata = data[downindex + 0] ; 800195c: 6a7b ldr r3, [r7, #36] ; 0x24 800195e: 68ba ldr r2, [r7, #8] 8001960: 4413 add r3, r2 8001962: 781b ldrb r3, [r3, #0] 8001964: 61fb str r3, [r7, #28] writedata += data[downindex + 1] << 8 ; 8001966: 6a7b ldr r3, [r7, #36] ; 0x24 8001968: 3301 adds r3, #1 800196a: 68ba ldr r2, [r7, #8] 800196c: 4413 add r3, r2 800196e: 781b ldrb r3, [r3, #0] 8001970: 021b lsls r3, r3, #8 8001972: 461a mov r2, r3 8001974: 69fb ldr r3, [r7, #28] 8001976: 4413 add r3, r2 8001978: 61fb str r3, [r7, #28] writedata += data[downindex + 2] << 16; 800197a: 6a7b ldr r3, [r7, #36] ; 0x24 800197c: 3302 adds r3, #2 800197e: 68ba ldr r2, [r7, #8] 8001980: 4413 add r3, r2 8001982: 781b ldrb r3, [r3, #0] 8001984: 041b lsls r3, r3, #16 8001986: 461a mov r2, r3 8001988: 69fb ldr r3, [r7, #28] 800198a: 4413 add r3, r2 800198c: 61fb str r3, [r7, #28] writedata += data[downindex + 3] << 24; 800198e: 6a7b ldr r3, [r7, #36] ; 0x24 8001990: 3303 adds r3, #3 8001992: 68ba ldr r2, [r7, #8] 8001994: 4413 add r3, r2 8001996: 781b ldrb r3, [r3, #0] 8001998: 061b lsls r3, r3, #24 800199a: 461a mov r2, r3 800199c: 69fb ldr r3, [r7, #28] 800199e: 4413 add r3, r2 80019a0: 61fb str r3, [r7, #28] if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, UserAddress,writedata) == HAL_OK) 80019a2: 4b1a ldr r3, [pc, #104] ; (8001a0c ) 80019a4: 6819 ldr r1, [r3, #0] 80019a6: 69fb ldr r3, [r7, #28] 80019a8: f04f 0400 mov.w r4, #0 80019ac: 461a mov r2, r3 80019ae: 4623 mov r3, r4 80019b0: 2002 movs r0, #2 80019b2: f001 fa5b bl 8002e6c 80019b6: 4603 mov r3, r0 80019b8: 2b00 cmp r3, #0 80019ba: d105 bne.n 80019c8 { UserAddress += 4; 80019bc: 4b13 ldr r3, [pc, #76] ; (8001a0c ) 80019be: 681b ldr r3, [r3, #0] 80019c0: 3304 adds r3, #4 80019c2: 4a12 ldr r2, [pc, #72] ; (8001a0c ) 80019c4: 6013 str r3, [r2, #0] 80019c6: e008 b.n 80019da } else { printf("HAL_FLASH_Program Error\r\n"); 80019c8: 4812 ldr r0, [pc, #72] ; (8001a14 ) 80019ca: f005 f83d bl 8006a48 printf("Flash Failed %x \r\n",UserAddress); 80019ce: 4b0f ldr r3, [pc, #60] ; (8001a0c ) 80019d0: 681b ldr r3, [r3, #0] 80019d2: 4619 mov r1, r3 80019d4: 4810 ldr r0, [pc, #64] ; (8001a18 ) 80019d6: f004 ffc3 bl 8006960 for(int downindex = 0; downindex < size; downindex+=4) 80019da: 6a7b ldr r3, [r7, #36] ; 0x24 80019dc: 3304 adds r3, #4 80019de: 627b str r3, [r7, #36] ; 0x24 80019e0: 6a7b ldr r3, [r7, #36] ; 0x24 80019e2: 687a ldr r2, [r7, #4] 80019e4: 429a cmp r2, r3 80019e6: d8b9 bhi.n 800195c } } printf("HAL_FLASH_Program END %x \r\n",UserAddress); 80019e8: 4b08 ldr r3, [pc, #32] ; (8001a0c ) 80019ea: 681b ldr r3, [r3, #0] 80019ec: 4619 mov r1, r3 80019ee: 480b ldr r0, [pc, #44] ; (8001a1c ) 80019f0: f004 ffb6 bl 8006960 /* Lock the Flash to disable the flash control register access (recommended to protect the FLASH memory against possible unwanted operation) *********/ HAL_FLASH_Lock(); 80019f4: f001 fad0 bl 8002f98 return 0; 80019f8: 2300 movs r3, #0 /* Check if the programmed data is OK MemoryProgramStatus = 0: data programmed correctly MemoryProgramStatus != 0: number of words not programmed correctly ******/ } 80019fa: 4618 mov r0, r3 80019fc: 372c adds r7, #44 ; 0x2c 80019fe: 46bd mov sp, r7 8001a00: bd90 pop {r4, r7, pc} 8001a02: bf00 nop 8001a04: 08008ae0 .word 0x08008ae0 8001a08: 2000060c .word 0x2000060c 8001a0c: 200005f0 .word 0x200005f0 8001a10: 08008afc .word 0x08008afc 8001a14: 08008b14 .word 0x08008b14 8001a18: 08008b30 .word 0x08008b30 8001a1c: 08008b44 .word 0x08008b44 08001a20 : void FLASH_Read_Func(uint32_t User_Address,uint8_t* dst,uint32_t size){ 8001a20: b580 push {r7, lr} 8001a22: b088 sub sp, #32 8001a24: af00 add r7, sp, #0 8001a26: 60f8 str r0, [r7, #12] 8001a28: 60b9 str r1, [r7, #8] 8001a2a: 607a str r2, [r7, #4] uint32_t CurrApiAddress = 0; 8001a2c: 2300 movs r3, #0 8001a2e: 61bb str r3, [r7, #24] uint32_t i = 0; 8001a30: 2300 movs r3, #0 8001a32: 617b str r3, [r7, #20] //uint8_t ret = 0; CurrApiAddress = User_Address; 8001a34: 68fb ldr r3, [r7, #12] 8001a36: 61bb str r3, [r7, #24] uint8_t* Currdata = (uint8_t*)CurrApiAddress; 8001a38: 69bb ldr r3, [r7, #24] 8001a3a: 613b str r3, [r7, #16] printf("Flash Read size : %d \r\n",size); 8001a3c: 6879 ldr r1, [r7, #4] 8001a3e: 4810 ldr r0, [pc, #64] ; (8001a80 ) 8001a40: f004 ff8e bl 8006960 for(int i = 0; i < size; i++){ 8001a44: 2300 movs r3, #0 8001a46: 61fb str r3, [r7, #28] 8001a48: e012 b.n 8001a70 dst[i] = Currdata[i]; 8001a4a: 69fb ldr r3, [r7, #28] 8001a4c: 693a ldr r2, [r7, #16] 8001a4e: 441a add r2, r3 8001a50: 69fb ldr r3, [r7, #28] 8001a52: 68b9 ldr r1, [r7, #8] 8001a54: 440b add r3, r1 8001a56: 7812 ldrb r2, [r2, #0] 8001a58: 701a strb r2, [r3, #0] printf("%02x ",dst[i]); 8001a5a: 69fb ldr r3, [r7, #28] 8001a5c: 68ba ldr r2, [r7, #8] 8001a5e: 4413 add r3, r2 8001a60: 781b ldrb r3, [r3, #0] 8001a62: 4619 mov r1, r3 8001a64: 4807 ldr r0, [pc, #28] ; (8001a84 ) 8001a66: f004 ff7b bl 8006960 for(int i = 0; i < size; i++){ 8001a6a: 69fb ldr r3, [r7, #28] 8001a6c: 3301 adds r3, #1 8001a6e: 61fb str r3, [r7, #28] 8001a70: 69fb ldr r3, [r7, #28] 8001a72: 687a ldr r2, [r7, #4] 8001a74: 429a cmp r2, r3 8001a76: d8e8 bhi.n 8001a4a } } 8001a78: bf00 nop 8001a7a: 3720 adds r7, #32 8001a7c: 46bd mov sp, r7 8001a7e: bd80 pop {r7, pc} 8001a80: 08008b64 .word 0x08008b64 8001a84: 08008b7c .word 0x08008b7c 08001a88 : #include "main.h" #include "led.h" volatile uint32_t LED_TimerCnt = 0; uint32_t LedTimerCnt_Get(){ 8001a88: b480 push {r7} 8001a8a: af00 add r7, sp, #0 return LED_TimerCnt; 8001a8c: 4b02 ldr r3, [pc, #8] ; (8001a98 ) 8001a8e: 681b ldr r3, [r3, #0] } 8001a90: 4618 mov r0, r3 8001a92: 46bd mov sp, r7 8001a94: bc80 pop {r7} 8001a96: 4770 bx lr 8001a98: 20000610 .word 0x20000610 08001a9c : void LedTimerCnt_Set(uint32_t val){ 8001a9c: b480 push {r7} 8001a9e: b083 sub sp, #12 8001aa0: af00 add r7, sp, #0 8001aa2: 6078 str r0, [r7, #4] LED_TimerCnt = val; 8001aa4: 4a03 ldr r2, [pc, #12] ; (8001ab4 ) 8001aa6: 687b ldr r3, [r7, #4] 8001aa8: 6013 str r3, [r2, #0] } 8001aaa: bf00 nop 8001aac: 370c adds r7, #12 8001aae: 46bd mov sp, r7 8001ab0: bc80 pop {r7} 8001ab2: 4770 bx lr 8001ab4: 20000610 .word 0x20000610 08001ab8 : void Boot_LED_Toggle(){ /*LED Check*/ 8001ab8: b580 push {r7, lr} 8001aba: b082 sub sp, #8 8001abc: af00 add r7, sp, #0 uint32_t Led_Cnt = LedTimerCnt_Get(); 8001abe: f7ff ffe3 bl 8001a88 8001ac2: 6078 str r0, [r7, #4] if(Led_Cnt >= LED_TOGGLE_CNT_REF){ 8001ac4: 687b ldr r3, [r7, #4] 8001ac6: f5b3 7ffa cmp.w r3, #500 ; 0x1f4 8001aca: d307 bcc.n 8001adc HAL_GPIO_TogglePin(BOOT_LED_GPIO_Port, BOOT_LED_Pin); 8001acc: f44f 4100 mov.w r1, #32768 ; 0x8000 8001ad0: 4804 ldr r0, [pc, #16] ; (8001ae4 ) 8001ad2: f001 fd54 bl 800357e LedTimerCnt_Set(0); 8001ad6: 2000 movs r0, #0 8001ad8: f7ff ffe0 bl 8001a9c } } 8001adc: bf00 nop 8001ade: 3708 adds r7, #8 8001ae0: 46bd mov sp, r7 8001ae2: bd80 pop {r7, pc} 8001ae4: 40011000 .word 0x40011000 08001ae8 : extern bool Bluecell_Operate(uint8_t* data); extern void MBIC_Operate(uint8_t * data); extern bool NessLab_CheckSum_Check(uint8_t* data,uint8_t size,uint8_t checksum); void InitUartQueue(pUARTQUEUE pQueue) { 8001ae8: b580 push {r7, lr} 8001aea: b082 sub sp, #8 8001aec: af00 add r7, sp, #0 8001aee: 6078 str r0, [r7, #4] pQueue->data = pQueue->head = pQueue->tail = 0; 8001af0: 687b ldr r3, [r7, #4] 8001af2: 2200 movs r2, #0 8001af4: 605a str r2, [r3, #4] 8001af6: 687b ldr r3, [r7, #4] 8001af8: 685a ldr r2, [r3, #4] 8001afa: 687b ldr r3, [r7, #4] 8001afc: 601a str r2, [r3, #0] 8001afe: 687b ldr r3, [r7, #4] 8001b00: 681a ldr r2, [r3, #0] 8001b02: 687b ldr r3, [r7, #4] 8001b04: 609a str r2, [r3, #8] uart_hal_tx.output_p = uart_hal_tx.input_p = 0; 8001b06: 2100 movs r1, #0 8001b08: 4b08 ldr r3, [pc, #32] ; (8001b2c ) 8001b0a: 460a mov r2, r1 8001b0c: f8a3 2080 strh.w r2, [r3, #128] ; 0x80 8001b10: 4b06 ldr r3, [pc, #24] ; (8001b2c ) 8001b12: 460a mov r2, r1 8001b14: f8a3 2082 strh.w r2, [r3, #130] ; 0x82 // HAL_UART_Receive_IT(&huart2,rxBuf,5); if (HAL_UART_Receive_DMA(&hMain, MainQueue.Buffer, 1) != HAL_OK) 8001b18: 2201 movs r2, #1 8001b1a: 4905 ldr r1, [pc, #20] ; (8001b30 ) 8001b1c: 4805 ldr r0, [pc, #20] ; (8001b34 ) 8001b1e: f002 fe53 bl 80047c8 // { //// _Error_Handler(__FILE__, __LINE__); // } //HAL_UART_Receive_DMA(&hTerminal, TerminalQueue.Buffer, 1); //HAL_UART_Receive_IT(hTerminal, pQueue->Buffer + pQueue->head, 1); } 8001b22: bf00 nop 8001b24: 3708 adds r7, #8 8001b26: 46bd mov sp, r7 8001b28: bd80 pop {r7, pc} 8001b2a: bf00 nop 8001b2c: 20000864 .word 0x20000864 8001b30: 20000758 .word 0x20000758 8001b34: 20000a90 .word 0x20000a90 08001b38 : void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { 8001b38: b580 push {r7, lr} 8001b3a: b084 sub sp, #16 8001b3c: af00 add r7, sp, #0 8001b3e: 6078 str r0, [r7, #4] // UART_HandleTypeDef *dst = (huart->Instance == USART2 ? &hTest:&hTerminal); pUARTQUEUE pQueue; // printf("Function : %s : \r\n",__func__); //printf("%02x ",uart_buf[i]); UartRxTimerCnt = 0; 8001b40: 4b15 ldr r3, [pc, #84] ; (8001b98 ) 8001b42: 2200 movs r2, #0 8001b44: 601a str r2, [r3, #0] pQueue = &MainQueue; 8001b46: 4b15 ldr r3, [pc, #84] ; (8001b9c ) 8001b48: 60fb str r3, [r7, #12] pQueue->head++; 8001b4a: 68fb ldr r3, [r7, #12] 8001b4c: 681b ldr r3, [r3, #0] 8001b4e: 1c5a adds r2, r3, #1 8001b50: 68fb ldr r3, [r7, #12] 8001b52: 601a str r2, [r3, #0] if (pQueue->head >= QUEUE_BUFFER_LENGTH) pQueue->head = 0; 8001b54: 68fb ldr r3, [r7, #12] 8001b56: 681b ldr r3, [r3, #0] 8001b58: 2b7f cmp r3, #127 ; 0x7f 8001b5a: dd02 ble.n 8001b62 8001b5c: 68fb ldr r3, [r7, #12] 8001b5e: 2200 movs r2, #0 8001b60: 601a str r2, [r3, #0] pQueue->data++; 8001b62: 68fb ldr r3, [r7, #12] 8001b64: 689b ldr r3, [r3, #8] 8001b66: 1c5a adds r2, r3, #1 8001b68: 68fb ldr r3, [r7, #12] 8001b6a: 609a str r2, [r3, #8] if (pQueue->data >= QUEUE_BUFFER_LENGTH) 8001b6c: 68fb ldr r3, [r7, #12] 8001b6e: 689b ldr r3, [r3, #8] 8001b70: 2b7f cmp r3, #127 ; 0x7f 8001b72: dd02 ble.n 8001b7a GetDataFromUartQueue(huart); 8001b74: 6878 ldr r0, [r7, #4] 8001b76: f000 f815 bl 8001ba4 HAL_UART_Receive_IT(&hMain, pQueue->Buffer + pQueue->head, 1); 8001b7a: 68fb ldr r3, [r7, #12] 8001b7c: 330c adds r3, #12 8001b7e: 68fa ldr r2, [r7, #12] 8001b80: 6812 ldr r2, [r2, #0] 8001b82: 4413 add r3, r2 8001b84: 2201 movs r2, #1 8001b86: 4619 mov r1, r3 8001b88: 4805 ldr r0, [pc, #20] ; (8001ba0 ) 8001b8a: f002 fd5d bl 8004648 // HAL_UART_Receive_DMA(&hTest, pQueue->Buffer + pQueue->head, 1); // Set_UartRcv(true); } 8001b8e: bf00 nop 8001b90: 3710 adds r7, #16 8001b92: 46bd mov sp, r7 8001b94: bd80 pop {r7, pc} 8001b96: bf00 nop 8001b98: 20000618 .word 0x20000618 8001b9c: 2000074c .word 0x2000074c 8001ba0: 20000a90 .word 0x20000a90 08001ba4 : // HAL_UART_Receive_DMA(&hTerminal, pQueue->Buffer + pQueue->head, 10); } void GetDataFromUartQueue(UART_HandleTypeDef *huart) { 8001ba4: b580 push {r7, lr} 8001ba6: b086 sub sp, #24 8001ba8: af00 add r7, sp, #0 8001baa: 6078 str r0, [r7, #4] volatile static int cnt; bool ret = 0; 8001bac: 2300 movs r3, #0 8001bae: 75fb strb r3, [r7, #23] /* bool chksumret = 0; uint16_t Length = 0; uint16_t CrcChk = 0; UART_HandleTypeDef *dst = (huart->Instance == USART2 ? &hTest:&hTerminal);*/ // UART_HandleTypeDef *dst = &hTerminal; pUARTQUEUE pQueue = &MainQueue; 8001bb0: 4b47 ldr r3, [pc, #284] ; (8001cd0 ) 8001bb2: 60fb str r3, [r7, #12] // if (HAL_UART_Transmit(dst, pQueue->Buffer + pQueue->tail, 1, 3000) != HAL_OK) // { // _Error_Handler(__FILE__, __LINE__); // } uart_buf[cnt++] = *(pQueue->Buffer + pQueue->tail); 8001bb4: 68fb ldr r3, [r7, #12] 8001bb6: 330c adds r3, #12 8001bb8: 68fa ldr r2, [r7, #12] 8001bba: 6852 ldr r2, [r2, #4] 8001bbc: 441a add r2, r3 8001bbe: 4b45 ldr r3, [pc, #276] ; (8001cd4 ) 8001bc0: 681b ldr r3, [r3, #0] 8001bc2: 1c59 adds r1, r3, #1 8001bc4: 4843 ldr r0, [pc, #268] ; (8001cd4 ) 8001bc6: 6001 str r1, [r0, #0] 8001bc8: 7811 ldrb r1, [r2, #0] 8001bca: 4a43 ldr r2, [pc, #268] ; (8001cd8 ) 8001bcc: 54d1 strb r1, [r2, r3] //#ifdef DEBUG_PRINT // printf("%02x ",*(pQueue->Buffer + pQueue->tail)) ; //#endif /* DEBUG_PRINT */ pQueue->tail++; 8001bce: 68fb ldr r3, [r7, #12] 8001bd0: 685b ldr r3, [r3, #4] 8001bd2: 1c5a adds r2, r3, #1 8001bd4: 68fb ldr r3, [r7, #12] 8001bd6: 605a str r2, [r3, #4] if (pQueue->tail >= QUEUE_BUFFER_LENGTH) pQueue->tail = 0; 8001bd8: 68fb ldr r3, [r7, #12] 8001bda: 685b ldr r3, [r3, #4] 8001bdc: 2b7f cmp r3, #127 ; 0x7f 8001bde: dd02 ble.n 8001be6 8001be0: 68fb ldr r3, [r7, #12] 8001be2: 2200 movs r2, #0 8001be4: 605a str r2, [r3, #4] pQueue->data--; 8001be6: 68fb ldr r3, [r7, #12] 8001be8: 689b ldr r3, [r3, #8] 8001bea: 1e5a subs r2, r3, #1 8001bec: 68fb ldr r3, [r7, #12] 8001bee: 609a str r2, [r3, #8] if(pQueue->data == 0){ 8001bf0: 68fb ldr r3, [r7, #12] 8001bf2: 689b ldr r3, [r3, #8] 8001bf4: 2b00 cmp r3, #0 8001bf6: d167 bne.n 8001cc8 // printf("data cnt zero !!! \r\n"); //RF_Ctrl_Main(&uart_buf[Header]); // HAL_UART_Transmit(dst, &temp_buf[BLUECELL_HEADER00], 11, 3000); #if 1// PYJ.2019.07.15_BEGIN -- printf("\r\n[RX]"); 8001bf8: 4838 ldr r0, [pc, #224] ; (8001cdc ) 8001bfa: f004 feb1 bl 8006960 for(int i = 0; i < cnt; i++){ 8001bfe: 2300 movs r3, #0 8001c00: 613b str r3, [r7, #16] 8001c02: e00b b.n 8001c1c printf("%02x ",uart_buf[i]); 8001c04: 4a34 ldr r2, [pc, #208] ; (8001cd8 ) 8001c06: 693b ldr r3, [r7, #16] 8001c08: 4413 add r3, r2 8001c0a: 781b ldrb r3, [r3, #0] 8001c0c: b2db uxtb r3, r3 8001c0e: 4619 mov r1, r3 8001c10: 4833 ldr r0, [pc, #204] ; (8001ce0 ) 8001c12: f004 fea5 bl 8006960 for(int i = 0; i < cnt; i++){ 8001c16: 693b ldr r3, [r7, #16] 8001c18: 3301 adds r3, #1 8001c1a: 613b str r3, [r7, #16] 8001c1c: 4b2d ldr r3, [pc, #180] ; (8001cd4 ) 8001c1e: 681b ldr r3, [r3, #0] 8001c20: 693a ldr r2, [r7, #16] 8001c22: 429a cmp r2, r3 8001c24: dbee blt.n 8001c04 } printf("\r\n"); 8001c26: 482f ldr r0, [pc, #188] ; (8001ce4 ) 8001c28: f004 ff0e bl 8006a48 // printf("Checksum Index : %d %x\r\n",uart_buf[NessLab_Req_DataLength] + NessLab_Req_DataLength + 1,uart_buf[uart_buf[NessLab_Req_DataLength] + NessLab_Req_DataLength + 1]); // printf(ANSI_COLOR_GREEN"\r\n CNT : %d \r\n"ANSI_COLOR_RESET,cnt); #endif // PYJ.2019.07.15_END -- if(uart_buf[NessLab_Req_MsgID0] == NessLab_Table_REQ) 8001c2c: 4b2a ldr r3, [pc, #168] ; (8001cd8 ) 8001c2e: 789b ldrb r3, [r3, #2] 8001c30: b2db uxtb r3, r3 8001c32: 2bc9 cmp r3, #201 ; 0xc9 8001c34: d10c bne.n 8001c50 ret = NessLab_CheckSum_Check(&uart_buf[NessLab_Req_MsgID0],uart_buf[NessLab_Req_DataLength] ,uart_buf[NessLab_Req_ChecksumVal]); 8001c36: 4b28 ldr r3, [pc, #160] ; (8001cd8 ) 8001c38: 799b ldrb r3, [r3, #6] 8001c3a: b2d9 uxtb r1, r3 8001c3c: 4b26 ldr r3, [pc, #152] ; (8001cd8 ) 8001c3e: 7a5b ldrb r3, [r3, #9] 8001c40: b2db uxtb r3, r3 8001c42: 461a mov r2, r3 8001c44: 4828 ldr r0, [pc, #160] ; (8001ce8 ) 8001c46: f7ff fddb bl 8001800 8001c4a: 4603 mov r3, r0 8001c4c: 75fb strb r3, [r7, #23] 8001c4e: e011 b.n 8001c74 else ret = NessLab_CheckSum_Check(&uart_buf[NessLab_Req_MsgID0],uart_buf[NessLab_DataLength] + 5 ,uart_buf[uart_buf[NessLab_Req_DataLength] + NessLab_Req_DataLength + 1]); 8001c50: 4b21 ldr r3, [pc, #132] ; (8001cd8 ) 8001c52: 799b ldrb r3, [r3, #6] 8001c54: b2db uxtb r3, r3 8001c56: 3305 adds r3, #5 8001c58: b2d9 uxtb r1, r3 8001c5a: 4b1f ldr r3, [pc, #124] ; (8001cd8 ) 8001c5c: 799b ldrb r3, [r3, #6] 8001c5e: b2db uxtb r3, r3 8001c60: 3307 adds r3, #7 8001c62: 4a1d ldr r2, [pc, #116] ; (8001cd8 ) 8001c64: 5cd3 ldrb r3, [r2, r3] 8001c66: b2db uxtb r3, r3 8001c68: 461a mov r2, r3 8001c6a: 481f ldr r0, [pc, #124] ; (8001ce8 ) 8001c6c: f7ff fdc8 bl 8001800 8001c70: 4603 mov r3, r0 8001c72: 75fb strb r3, [r7, #23] if(ret == true){ 8001c74: 7dfb ldrb r3, [r7, #23] 8001c76: 2b00 cmp r3, #0 8001c78: d006 beq.n 8001c88 NessLab_Operate(&uart_buf[0]); 8001c7a: 4817 ldr r0, [pc, #92] ; (8001cd8 ) 8001c7c: f7ff f900 bl 8000e80 printf("Checksum OK \r\n"); 8001c80: 481a ldr r0, [pc, #104] ; (8001cec ) 8001c82: f004 fee1 bl 8006a48 8001c86: e01c b.n 8001cc2 }else{ printf("Checksum Error \r\n"); 8001c88: 4819 ldr r0, [pc, #100] ; (8001cf0 ) 8001c8a: f004 fedd bl 8006a48 printf("uart_buf[NessLab_Req_DataLength] : %x \r\n",uart_buf[NessLab_Req_DataLength]); 8001c8e: 4b12 ldr r3, [pc, #72] ; (8001cd8 ) 8001c90: 799b ldrb r3, [r3, #6] 8001c92: b2db uxtb r3, r3 8001c94: 4619 mov r1, r3 8001c96: 4817 ldr r0, [pc, #92] ; (8001cf4 ) 8001c98: f004 fe62 bl 8006960 printf("NessLab_Req_DataLength : %d \r\n",NessLab_Req_DataLength); 8001c9c: 2106 movs r1, #6 8001c9e: 4816 ldr r0, [pc, #88] ; (8001cf8 ) 8001ca0: f004 fe5e bl 8006960 printf("Checksum Index : %d %x\r\n",uart_buf[NessLab_Req_DataLength] + NessLab_Req_DataLength + 1,uart_buf[uart_buf[NessLab_Req_DataLength] + NessLab_Req_DataLength + 1]); 8001ca4: 4b0c ldr r3, [pc, #48] ; (8001cd8 ) 8001ca6: 799b ldrb r3, [r3, #6] 8001ca8: b2db uxtb r3, r3 8001caa: 1dd9 adds r1, r3, #7 8001cac: 4b0a ldr r3, [pc, #40] ; (8001cd8 ) 8001cae: 799b ldrb r3, [r3, #6] 8001cb0: b2db uxtb r3, r3 8001cb2: 3307 adds r3, #7 8001cb4: 4a08 ldr r2, [pc, #32] ; (8001cd8 ) 8001cb6: 5cd3 ldrb r3, [r2, r3] 8001cb8: b2db uxtb r3, r3 8001cba: 461a mov r2, r3 8001cbc: 480f ldr r0, [pc, #60] ; (8001cfc ) 8001cbe: f004 fe4f bl 8006960 } cnt = 0; 8001cc2: 4b04 ldr r3, [pc, #16] ; (8001cd4 ) 8001cc4: 2200 movs r2, #0 8001cc6: 601a str r2, [r3, #0] } } 8001cc8: bf00 nop 8001cca: 3718 adds r7, #24 8001ccc: 46bd mov sp, r7 8001cce: bd80 pop {r7, pc} 8001cd0: 2000074c .word 0x2000074c 8001cd4: 20000614 .word 0x20000614 8001cd8: 200006cc .word 0x200006cc 8001cdc: 08008b94 .word 0x08008b94 8001ce0: 08008b9c .word 0x08008b9c 8001ce4: 08008ba4 .word 0x08008ba4 8001ce8: 200006ce .word 0x200006ce 8001cec: 08008ba8 .word 0x08008ba8 8001cf0: 08008bb8 .word 0x08008bb8 8001cf4: 08008bcc .word 0x08008bcc 8001cf8: 08008bf8 .word 0x08008bf8 8001cfc: 08008c18 .word 0x08008c18 08001d00 : void Uart_Check(void){ 8001d00: b580 push {r7, lr} 8001d02: af00 add r7, sp, #0 while (MainQueue.data > 0 && UartRxTimerCnt > 50) GetDataFromUartQueue(&hMain); 8001d04: e002 b.n 8001d0c 8001d06: 4806 ldr r0, [pc, #24] ; (8001d20 ) 8001d08: f7ff ff4c bl 8001ba4 8001d0c: 4b05 ldr r3, [pc, #20] ; (8001d24 ) 8001d0e: 689b ldr r3, [r3, #8] 8001d10: 2b00 cmp r3, #0 8001d12: dd03 ble.n 8001d1c 8001d14: 4b04 ldr r3, [pc, #16] ; (8001d28 ) 8001d16: 681b ldr r3, [r3, #0] 8001d18: 2b32 cmp r3, #50 ; 0x32 8001d1a: d8f4 bhi.n 8001d06 } 8001d1c: bf00 nop 8001d1e: bd80 pop {r7, pc} 8001d20: 20000a90 .word 0x20000a90 8001d24: 2000074c .word 0x2000074c 8001d28: 20000618 .word 0x20000618 08001d2c : void Uart1_Data_Send(uint8_t* data,uint16_t size){ 8001d2c: b580 push {r7, lr} 8001d2e: b084 sub sp, #16 8001d30: af00 add r7, sp, #0 8001d32: 6078 str r0, [r7, #4] 8001d34: 460b mov r3, r1 8001d36: 807b strh r3, [r7, #2] HAL_UART_Transmit_DMA(&hMain, &data[0],size); 8001d38: 887b ldrh r3, [r7, #2] 8001d3a: 461a mov r2, r3 8001d3c: 6879 ldr r1, [r7, #4] 8001d3e: 480f ldr r0, [pc, #60] ; (8001d7c ) 8001d40: f002 fcd6 bl 80046f0 //HAL_UART_Transmit_IT(&hTerminal, &data[0],size); // printf("data[278] : %x \r\n",data[278]); //// HAL_Delay(1); #if 1 // PYJ.2020.07.19_BEGIN -- printf("\r\n [TX] : "); 8001d44: 480e ldr r0, [pc, #56] ; (8001d80 ) 8001d46: f004 fe0b bl 8006960 for(int i = 0; i< size; i++) 8001d4a: 2300 movs r3, #0 8001d4c: 60fb str r3, [r7, #12] 8001d4e: e00a b.n 8001d66 printf("%02x ",data[i]); 8001d50: 68fb ldr r3, [r7, #12] 8001d52: 687a ldr r2, [r7, #4] 8001d54: 4413 add r3, r2 8001d56: 781b ldrb r3, [r3, #0] 8001d58: 4619 mov r1, r3 8001d5a: 480a ldr r0, [pc, #40] ; (8001d84 ) 8001d5c: f004 fe00 bl 8006960 for(int i = 0; i< size; i++) 8001d60: 68fb ldr r3, [r7, #12] 8001d62: 3301 adds r3, #1 8001d64: 60fb str r3, [r7, #12] 8001d66: 887b ldrh r3, [r7, #2] 8001d68: 68fa ldr r2, [r7, #12] 8001d6a: 429a cmp r2, r3 8001d6c: dbf0 blt.n 8001d50 // printf("};\r\n\tCOUNT : %d \r\n",size); printf("\r\n"); 8001d6e: 4806 ldr r0, [pc, #24] ; (8001d88 ) 8001d70: f004 fe6a bl 8006a48 // data[i] = 0; // } // printf("};\r\n\tCOUNT : %d \r\n",size); // printf("\r\n"); } 8001d74: bf00 nop 8001d76: 3710 adds r7, #16 8001d78: 46bd mov sp, r7 8001d7a: bd80 pop {r7, pc} 8001d7c: 20000a90 .word 0x20000a90 8001d80: 08008c34 .word 0x08008c34 8001d84: 08008b9c .word 0x08008b9c 8001d88: 08008ba4 .word 0x08008ba4 08001d8c : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8001d8c: b580 push {r7, lr} 8001d8e: af00 add r7, sp, #0 __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); #endif #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8001d90: 2003 movs r0, #3 8001d92: f000 fdd1 bl 8002938 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 8001d96: 2000 movs r0, #0 8001d98: f003 ffaa bl 8005cf0 /* Init the low level hardware */ HAL_MspInit(); 8001d9c: f003 fdc0 bl 8005920 /* Return function status */ return HAL_OK; 8001da0: 2300 movs r3, #0 } 8001da2: 4618 mov r0, r3 8001da4: bd80 pop {r7, pc} ... 08001da8 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8001da8: b480 push {r7} 8001daa: af00 add r7, sp, #0 uwTick += uwTickFreq; 8001dac: 4b05 ldr r3, [pc, #20] ; (8001dc4 ) 8001dae: 781b ldrb r3, [r3, #0] 8001db0: 461a mov r2, r3 8001db2: 4b05 ldr r3, [pc, #20] ; (8001dc8 ) 8001db4: 681b ldr r3, [r3, #0] 8001db6: 4413 add r3, r2 8001db8: 4a03 ldr r2, [pc, #12] ; (8001dc8 ) 8001dba: 6013 str r3, [r2, #0] } 8001dbc: bf00 nop 8001dbe: 46bd mov sp, r7 8001dc0: bc80 pop {r7} 8001dc2: 4770 bx lr 8001dc4: 20000004 .word 0x20000004 8001dc8: 200008e8 .word 0x200008e8 08001dcc : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8001dcc: b480 push {r7} 8001dce: af00 add r7, sp, #0 return uwTick; 8001dd0: 4b02 ldr r3, [pc, #8] ; (8001ddc ) 8001dd2: 681b ldr r3, [r3, #0] } 8001dd4: 4618 mov r0, r3 8001dd6: 46bd mov sp, r7 8001dd8: bc80 pop {r7} 8001dda: 4770 bx lr 8001ddc: 200008e8 .word 0x200008e8 08001de0 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 8001de0: b580 push {r7, lr} 8001de2: b084 sub sp, #16 8001de4: af00 add r7, sp, #0 8001de6: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 8001de8: f7ff fff0 bl 8001dcc 8001dec: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 8001dee: 687b ldr r3, [r7, #4] 8001df0: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 8001df2: 68fb ldr r3, [r7, #12] 8001df4: f1b3 3fff cmp.w r3, #4294967295 8001df8: d005 beq.n 8001e06 { wait += (uint32_t)(uwTickFreq); 8001dfa: 4b09 ldr r3, [pc, #36] ; (8001e20 ) 8001dfc: 781b ldrb r3, [r3, #0] 8001dfe: 461a mov r2, r3 8001e00: 68fb ldr r3, [r7, #12] 8001e02: 4413 add r3, r2 8001e04: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 8001e06: bf00 nop 8001e08: f7ff ffe0 bl 8001dcc 8001e0c: 4602 mov r2, r0 8001e0e: 68bb ldr r3, [r7, #8] 8001e10: 1ad3 subs r3, r2, r3 8001e12: 68fa ldr r2, [r7, #12] 8001e14: 429a cmp r2, r3 8001e16: d8f7 bhi.n 8001e08 { } } 8001e18: bf00 nop 8001e1a: 3710 adds r7, #16 8001e1c: 46bd mov sp, r7 8001e1e: bd80 pop {r7, pc} 8001e20: 20000004 .word 0x20000004 08001e24 : * of structure "ADC_InitTypeDef". * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { 8001e24: b580 push {r7, lr} 8001e26: b086 sub sp, #24 8001e28: af00 add r7, sp, #0 8001e2a: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8001e2c: 2300 movs r3, #0 8001e2e: 75fb strb r3, [r7, #23] uint32_t tmp_cr1 = 0U; 8001e30: 2300 movs r3, #0 8001e32: 613b str r3, [r7, #16] uint32_t tmp_cr2 = 0U; 8001e34: 2300 movs r3, #0 8001e36: 60bb str r3, [r7, #8] uint32_t tmp_sqr1 = 0U; 8001e38: 2300 movs r3, #0 8001e3a: 60fb str r3, [r7, #12] /* Check ADC handle */ if(hadc == NULL) 8001e3c: 687b ldr r3, [r7, #4] 8001e3e: 2b00 cmp r3, #0 8001e40: d101 bne.n 8001e46 { return HAL_ERROR; 8001e42: 2301 movs r3, #1 8001e44: e0be b.n 8001fc4 assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) 8001e46: 687b ldr r3, [r7, #4] 8001e48: 689b ldr r3, [r3, #8] 8001e4a: 2b00 cmp r3, #0 /* Refer to header of this file for more details on clock enabling */ /* procedure. */ /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) 8001e4c: 687b ldr r3, [r7, #4] 8001e4e: 6a9b ldr r3, [r3, #40] ; 0x28 8001e50: 2b00 cmp r3, #0 8001e52: d109 bne.n 8001e68 { /* Initialize ADC error code */ ADC_CLEAR_ERRORCODE(hadc); 8001e54: 687b ldr r3, [r7, #4] 8001e56: 2200 movs r2, #0 8001e58: 62da str r2, [r3, #44] ; 0x2c /* Allocate lock resource and initialize it */ hadc->Lock = HAL_UNLOCKED; 8001e5a: 687b ldr r3, [r7, #4] 8001e5c: 2200 movs r2, #0 8001e5e: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); 8001e62: 6878 ldr r0, [r7, #4] 8001e64: f003 fd8e bl 8005984 /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ /* Note: In case of ADC already enabled, precaution to not launch an */ /* unwanted conversion while modifying register CR2 by writing 1 to */ /* bit ADON. */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 8001e68: 6878 ldr r0, [r7, #4] 8001e6a: f000 fb75 bl 8002558 8001e6e: 4603 mov r3, r0 8001e70: 75fb strb r3, [r7, #23] /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && 8001e72: 687b ldr r3, [r7, #4] 8001e74: 6a9b ldr r3, [r3, #40] ; 0x28 8001e76: f003 0310 and.w r3, r3, #16 8001e7a: 2b00 cmp r3, #0 8001e7c: f040 8099 bne.w 8001fb2 8001e80: 7dfb ldrb r3, [r7, #23] 8001e82: 2b00 cmp r3, #0 8001e84: f040 8095 bne.w 8001fb2 (tmp_hal_status == HAL_OK) ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8001e88: 687b ldr r3, [r7, #4] 8001e8a: 6a9b ldr r3, [r3, #40] ; 0x28 8001e8c: f423 5388 bic.w r3, r3, #4352 ; 0x1100 8001e90: f023 0302 bic.w r3, r3, #2 8001e94: f043 0202 orr.w r2, r3, #2 8001e98: 687b ldr r3, [r7, #4] 8001e9a: 629a str r2, [r3, #40] ; 0x28 /* - continuous conversion mode */ /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */ /* HAL_ADC_Start_xxx functions because if set in this function, */ /* a conversion on injected group would start a conversion also on */ /* regular group after ADC enabling. */ tmp_cr2 |= (hadc->Init.DataAlign | 8001e9c: 687b ldr r3, [r7, #4] 8001e9e: 685a ldr r2, [r3, #4] ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 8001ea0: 687b ldr r3, [r7, #4] 8001ea2: 69db ldr r3, [r3, #28] tmp_cr2 |= (hadc->Init.DataAlign | 8001ea4: 431a orrs r2, r3 ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) ); 8001ea6: 687b ldr r3, [r7, #4] 8001ea8: 7b1b ldrb r3, [r3, #12] 8001eaa: 005b lsls r3, r3, #1 ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 8001eac: 4313 orrs r3, r2 tmp_cr2 |= (hadc->Init.DataAlign | 8001eae: 68ba ldr r2, [r7, #8] 8001eb0: 4313 orrs r3, r2 8001eb2: 60bb str r3, [r7, #8] /* Configuration of ADC: */ /* - scan mode */ /* - discontinuous mode disable/enable */ /* - discontinuous mode number of conversions */ tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode)); 8001eb4: 687b ldr r3, [r7, #4] 8001eb6: 689b ldr r3, [r3, #8] 8001eb8: f5b3 7f80 cmp.w r3, #256 ; 0x100 8001ebc: d003 beq.n 8001ec6 8001ebe: 687b ldr r3, [r7, #4] 8001ec0: 689b ldr r3, [r3, #8] 8001ec2: 2b01 cmp r3, #1 8001ec4: d102 bne.n 8001ecc 8001ec6: f44f 7380 mov.w r3, #256 ; 0x100 8001eca: e000 b.n 8001ece 8001ecc: 2300 movs r3, #0 8001ece: 693a ldr r2, [r7, #16] 8001ed0: 4313 orrs r3, r2 8001ed2: 613b str r3, [r7, #16] /* Enable discontinuous mode only if continuous mode is disabled */ /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */ /* discontinuous is set anyway, but will have no effect on ADC HW. */ if (hadc->Init.DiscontinuousConvMode == ENABLE) 8001ed4: 687b ldr r3, [r7, #4] 8001ed6: 7d1b ldrb r3, [r3, #20] 8001ed8: 2b01 cmp r3, #1 8001eda: d119 bne.n 8001f10 { if (hadc->Init.ContinuousConvMode == DISABLE) 8001edc: 687b ldr r3, [r7, #4] 8001ede: 7b1b ldrb r3, [r3, #12] 8001ee0: 2b00 cmp r3, #0 8001ee2: d109 bne.n 8001ef8 { /* Enable the selected ADC regular discontinuous mode */ /* Set the number of channels to be converted in discontinuous mode */ SET_BIT(tmp_cr1, ADC_CR1_DISCEN | 8001ee4: 687b ldr r3, [r7, #4] 8001ee6: 699b ldr r3, [r3, #24] 8001ee8: 3b01 subs r3, #1 8001eea: 035a lsls r2, r3, #13 8001eec: 693b ldr r3, [r7, #16] 8001eee: 4313 orrs r3, r2 8001ef0: f443 6300 orr.w r3, r3, #2048 ; 0x800 8001ef4: 613b str r3, [r7, #16] 8001ef6: e00b b.n 8001f10 { /* ADC regular group settings continuous and sequencer discontinuous*/ /* cannot be enabled simultaneously. */ /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8001ef8: 687b ldr r3, [r7, #4] 8001efa: 6a9b ldr r3, [r3, #40] ; 0x28 8001efc: f043 0220 orr.w r2, r3, #32 8001f00: 687b ldr r3, [r7, #4] 8001f02: 629a str r2, [r3, #40] ; 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8001f04: 687b ldr r3, [r7, #4] 8001f06: 6adb ldr r3, [r3, #44] ; 0x2c 8001f08: f043 0201 orr.w r2, r3, #1 8001f0c: 687b ldr r3, [r7, #4] 8001f0e: 62da str r2, [r3, #44] ; 0x2c } } /* Update ADC configuration register CR1 with previous settings */ MODIFY_REG(hadc->Instance->CR1, 8001f10: 687b ldr r3, [r7, #4] 8001f12: 681b ldr r3, [r3, #0] 8001f14: 685b ldr r3, [r3, #4] 8001f16: f423 4169 bic.w r1, r3, #59648 ; 0xe900 8001f1a: 687b ldr r3, [r7, #4] 8001f1c: 681b ldr r3, [r3, #0] 8001f1e: 693a ldr r2, [r7, #16] 8001f20: 430a orrs r2, r1 8001f22: 605a str r2, [r3, #4] ADC_CR1_DISCEN | ADC_CR1_DISCNUM , tmp_cr1 ); /* Update ADC configuration register CR2 with previous settings */ MODIFY_REG(hadc->Instance->CR2, 8001f24: 687b ldr r3, [r7, #4] 8001f26: 681b ldr r3, [r3, #0] 8001f28: 689a ldr r2, [r3, #8] 8001f2a: 4b28 ldr r3, [pc, #160] ; (8001fcc ) 8001f2c: 4013 ands r3, r2 8001f2e: 687a ldr r2, [r7, #4] 8001f30: 6812 ldr r2, [r2, #0] 8001f32: 68b9 ldr r1, [r7, #8] 8001f34: 430b orrs r3, r1 8001f36: 6093 str r3, [r2, #8] /* Note: Scan mode is present by hardware on this device and, if */ /* disabled, discards automatically nb of conversions. Anyway, nb of */ /* conversions is forced to 0x00 for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion" */ if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE) 8001f38: 687b ldr r3, [r7, #4] 8001f3a: 689b ldr r3, [r3, #8] 8001f3c: f5b3 7f80 cmp.w r3, #256 ; 0x100 8001f40: d003 beq.n 8001f4a 8001f42: 687b ldr r3, [r7, #4] 8001f44: 689b ldr r3, [r3, #8] 8001f46: 2b01 cmp r3, #1 8001f48: d104 bne.n 8001f54 { tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion); 8001f4a: 687b ldr r3, [r7, #4] 8001f4c: 691b ldr r3, [r3, #16] 8001f4e: 3b01 subs r3, #1 8001f50: 051b lsls r3, r3, #20 8001f52: 60fb str r3, [r7, #12] } MODIFY_REG(hadc->Instance->SQR1, 8001f54: 687b ldr r3, [r7, #4] 8001f56: 681b ldr r3, [r3, #0] 8001f58: 6adb ldr r3, [r3, #44] ; 0x2c 8001f5a: f423 0170 bic.w r1, r3, #15728640 ; 0xf00000 8001f5e: 687b ldr r3, [r7, #4] 8001f60: 681b ldr r3, [r3, #0] 8001f62: 68fa ldr r2, [r7, #12] 8001f64: 430a orrs r2, r1 8001f66: 62da str r2, [r3, #44] ; 0x2c /* ensure of no potential problem of ADC core IP clocking. */ /* Check through register CR2 (excluding bits set in other functions: */ /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */ /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */ /* measurement path bit (TSVREFE). */ if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 8001f68: 687b ldr r3, [r7, #4] 8001f6a: 681b ldr r3, [r3, #0] 8001f6c: 689a ldr r2, [r3, #8] 8001f6e: 4b18 ldr r3, [pc, #96] ; (8001fd0 ) 8001f70: 4013 ands r3, r2 8001f72: 68ba ldr r2, [r7, #8] 8001f74: 429a cmp r2, r3 8001f76: d10b bne.n 8001f90 ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL | ADC_CR2_TSVREFE )) == tmp_cr2) { /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 8001f78: 687b ldr r3, [r7, #4] 8001f7a: 2200 movs r2, #0 8001f7c: 62da str r2, [r3, #44] ; 0x2c /* Set the ADC state */ ADC_STATE_CLR_SET(hadc->State, 8001f7e: 687b ldr r3, [r7, #4] 8001f80: 6a9b ldr r3, [r3, #40] ; 0x28 8001f82: f023 0303 bic.w r3, r3, #3 8001f86: f043 0201 orr.w r2, r3, #1 8001f8a: 687b ldr r3, [r7, #4] 8001f8c: 629a str r2, [r3, #40] ; 0x28 if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 8001f8e: e018 b.n 8001fc2 HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 8001f90: 687b ldr r3, [r7, #4] 8001f92: 6a9b ldr r3, [r3, #40] ; 0x28 8001f94: f023 0312 bic.w r3, r3, #18 8001f98: f043 0210 orr.w r2, r3, #16 8001f9c: 687b ldr r3, [r7, #4] 8001f9e: 629a str r2, [r3, #40] ; 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8001fa0: 687b ldr r3, [r7, #4] 8001fa2: 6adb ldr r3, [r3, #44] ; 0x2c 8001fa4: f043 0201 orr.w r2, r3, #1 8001fa8: 687b ldr r3, [r7, #4] 8001faa: 62da str r2, [r3, #44] ; 0x2c tmp_hal_status = HAL_ERROR; 8001fac: 2301 movs r3, #1 8001fae: 75fb strb r3, [r7, #23] if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 8001fb0: e007 b.n 8001fc2 } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8001fb2: 687b ldr r3, [r7, #4] 8001fb4: 6a9b ldr r3, [r3, #40] ; 0x28 8001fb6: f043 0210 orr.w r2, r3, #16 8001fba: 687b ldr r3, [r7, #4] 8001fbc: 629a str r2, [r3, #40] ; 0x28 tmp_hal_status = HAL_ERROR; 8001fbe: 2301 movs r3, #1 8001fc0: 75fb strb r3, [r7, #23] } /* Return function status */ return tmp_hal_status; 8001fc2: 7dfb ldrb r3, [r7, #23] } 8001fc4: 4618 mov r0, r3 8001fc6: 3718 adds r7, #24 8001fc8: 46bd mov sp, r7 8001fca: bd80 pop {r7, pc} 8001fcc: ffe1f7fd .word 0xffe1f7fd 8001fd0: ff1f0efe .word 0xff1f0efe 08001fd4 : * @param pData: The destination Buffer address. * @param Length: The length of data to be transferred from ADC peripheral to memory. * @retval None */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) { 8001fd4: b580 push {r7, lr} 8001fd6: b086 sub sp, #24 8001fd8: af00 add r7, sp, #0 8001fda: 60f8 str r0, [r7, #12] 8001fdc: 60b9 str r1, [r7, #8] 8001fde: 607a str r2, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8001fe0: 2300 movs r3, #0 8001fe2: 75fb strb r3, [r7, #23] /* If multimode is enabled, dedicated function multimode conversion */ /* start DMA must be used. */ if(ADC_MULTIMODE_IS_ENABLE(hadc) == RESET) { /* Process locked */ __HAL_LOCK(hadc); 8001fe4: 68fb ldr r3, [r7, #12] 8001fe6: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 8001fea: 2b01 cmp r3, #1 8001fec: d101 bne.n 8001ff2 8001fee: 2302 movs r3, #2 8001ff0: e080 b.n 80020f4 8001ff2: 68fb ldr r3, [r7, #12] 8001ff4: 2201 movs r2, #1 8001ff6: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); 8001ffa: 68f8 ldr r0, [r7, #12] 8001ffc: f000 fa5a bl 80024b4 8002000: 4603 mov r3, r0 8002002: 75fb strb r3, [r7, #23] /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) 8002004: 7dfb ldrb r3, [r7, #23] 8002006: 2b00 cmp r3, #0 8002008: d16f bne.n 80020ea { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, 800200a: 68fb ldr r3, [r7, #12] 800200c: 6a9b ldr r3, [r3, #40] ; 0x28 800200e: f423 6370 bic.w r3, r3, #3840 ; 0xf00 8002012: f023 0301 bic.w r3, r3, #1 8002016: f443 7280 orr.w r2, r3, #256 ; 0x100 800201a: 68fb ldr r3, [r7, #12] 800201c: 629a str r2, [r3, #40] ; 0x28 /* for all cases of multimode: independent mode, multimode ADC master */ /* or multimode ADC slave (for devices with several ADCs): */ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) { /* Set ADC state (ADC independent or master) */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 800201e: 68fb ldr r3, [r7, #12] 8002020: 6a9b ldr r3, [r3, #40] ; 0x28 8002022: f423 1280 bic.w r2, r3, #1048576 ; 0x100000 8002026: 68fb ldr r3, [r7, #12] 8002028: 629a str r2, [r3, #40] ; 0x28 /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) 800202a: 68fb ldr r3, [r7, #12] 800202c: 681b ldr r3, [r3, #0] 800202e: 685b ldr r3, [r3, #4] 8002030: f403 6380 and.w r3, r3, #1024 ; 0x400 8002034: 2b00 cmp r3, #0 8002036: d007 beq.n 8002048 { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 8002038: 68fb ldr r3, [r7, #12] 800203a: 6a9b ldr r3, [r3, #40] ; 0x28 800203c: f423 5340 bic.w r3, r3, #12288 ; 0x3000 8002040: f443 5280 orr.w r2, r3, #4096 ; 0x1000 8002044: 68fb ldr r3, [r7, #12] 8002046: 629a str r2, [r3, #40] ; 0x28 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } } /* State machine update: Check if an injected conversion is ongoing */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 8002048: 68fb ldr r3, [r7, #12] 800204a: 6a9b ldr r3, [r3, #40] ; 0x28 800204c: f403 5380 and.w r3, r3, #4096 ; 0x1000 8002050: 2b00 cmp r3, #0 8002052: d006 beq.n 8002062 { /* Reset ADC error code fields related to conversions on group regular */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); 8002054: 68fb ldr r3, [r7, #12] 8002056: 6adb ldr r3, [r3, #44] ; 0x2c 8002058: f023 0206 bic.w r2, r3, #6 800205c: 68fb ldr r3, [r7, #12] 800205e: 62da str r2, [r3, #44] ; 0x2c 8002060: e002 b.n 8002068 } else { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); 8002062: 68fb ldr r3, [r7, #12] 8002064: 2200 movs r2, #0 8002066: 62da str r2, [r3, #44] ; 0x2c } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); 8002068: 68fb ldr r3, [r7, #12] 800206a: 2200 movs r2, #0 800206c: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; 8002070: 68fb ldr r3, [r7, #12] 8002072: 6a1b ldr r3, [r3, #32] 8002074: 4a21 ldr r2, [pc, #132] ; (80020fc ) 8002076: 629a str r2, [r3, #40] ; 0x28 /* Set the DMA half transfer complete callback */ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; 8002078: 68fb ldr r3, [r7, #12] 800207a: 6a1b ldr r3, [r3, #32] 800207c: 4a20 ldr r2, [pc, #128] ; (8002100 ) 800207e: 62da str r2, [r3, #44] ; 0x2c /* Set the DMA error callback */ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; 8002080: 68fb ldr r3, [r7, #12] 8002082: 6a1b ldr r3, [r3, #32] 8002084: 4a1f ldr r2, [pc, #124] ; (8002104 ) 8002086: 631a str r2, [r3, #48] ; 0x30 /* start (in case of SW start): */ /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC */ /* operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); 8002088: 68fb ldr r3, [r7, #12] 800208a: 681b ldr r3, [r3, #0] 800208c: f06f 0202 mvn.w r2, #2 8002090: 601a str r2, [r3, #0] /* Enable ADC DMA mode */ SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA); 8002092: 68fb ldr r3, [r7, #12] 8002094: 681b ldr r3, [r3, #0] 8002096: 689a ldr r2, [r3, #8] 8002098: 68fb ldr r3, [r7, #12] 800209a: 681b ldr r3, [r3, #0] 800209c: f442 7280 orr.w r2, r2, #256 ; 0x100 80020a0: 609a str r2, [r3, #8] /* Start the DMA channel */ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); 80020a2: 68fb ldr r3, [r7, #12] 80020a4: 6a18 ldr r0, [r3, #32] 80020a6: 68fb ldr r3, [r7, #12] 80020a8: 681b ldr r3, [r3, #0] 80020aa: 334c adds r3, #76 ; 0x4c 80020ac: 4619 mov r1, r3 80020ae: 68ba ldr r2, [r7, #8] 80020b0: 687b ldr r3, [r7, #4] 80020b2: f000 fcd1 bl 8002a58 /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ if (ADC_IS_SOFTWARE_START_REGULAR(hadc)) 80020b6: 68fb ldr r3, [r7, #12] 80020b8: 681b ldr r3, [r3, #0] 80020ba: 689b ldr r3, [r3, #8] 80020bc: f403 2360 and.w r3, r3, #917504 ; 0xe0000 80020c0: f5b3 2f60 cmp.w r3, #917504 ; 0xe0000 80020c4: d108 bne.n 80020d8 { /* Start ADC conversion on regular group with SW start */ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); 80020c6: 68fb ldr r3, [r7, #12] 80020c8: 681b ldr r3, [r3, #0] 80020ca: 689a ldr r2, [r3, #8] 80020cc: 68fb ldr r3, [r7, #12] 80020ce: 681b ldr r3, [r3, #0] 80020d0: f442 02a0 orr.w r2, r2, #5242880 ; 0x500000 80020d4: 609a str r2, [r3, #8] 80020d6: e00c b.n 80020f2 } else { /* Start ADC conversion on regular group with external trigger */ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); 80020d8: 68fb ldr r3, [r7, #12] 80020da: 681b ldr r3, [r3, #0] 80020dc: 689a ldr r2, [r3, #8] 80020de: 68fb ldr r3, [r7, #12] 80020e0: 681b ldr r3, [r3, #0] 80020e2: f442 1280 orr.w r2, r2, #1048576 ; 0x100000 80020e6: 609a str r2, [r3, #8] 80020e8: e003 b.n 80020f2 } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); 80020ea: 68fb ldr r3, [r7, #12] 80020ec: 2200 movs r2, #0 80020ee: f883 2024 strb.w r2, [r3, #36] ; 0x24 { tmp_hal_status = HAL_ERROR; } /* Return function status */ return tmp_hal_status; 80020f2: 7dfb ldrb r3, [r7, #23] } 80020f4: 4618 mov r0, r3 80020f6: 3718 adds r7, #24 80020f8: 46bd mov sp, r7 80020fa: bd80 pop {r7, pc} 80020fc: 080025cd .word 0x080025cd 8002100: 08002649 .word 0x08002649 8002104: 08002665 .word 0x08002665 08002108 : * @brief Handles ADC interrupt request * @param hadc: ADC handle * @retval None */ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) { 8002108: b580 push {r7, lr} 800210a: b082 sub sp, #8 800210c: af00 add r7, sp, #0 800210e: 6078 str r0, [r7, #4] assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); /* ========== Check End of Conversion flag for regular group ========== */ if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) 8002110: 687b ldr r3, [r7, #4] 8002112: 681b ldr r3, [r3, #0] 8002114: 685b ldr r3, [r3, #4] 8002116: f003 0320 and.w r3, r3, #32 800211a: 2b20 cmp r3, #32 800211c: d140 bne.n 80021a0 { if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) ) 800211e: 687b ldr r3, [r7, #4] 8002120: 681b ldr r3, [r3, #0] 8002122: 681b ldr r3, [r3, #0] 8002124: f003 0302 and.w r3, r3, #2 8002128: 2b02 cmp r3, #2 800212a: d139 bne.n 80021a0 { /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) 800212c: 687b ldr r3, [r7, #4] 800212e: 6a9b ldr r3, [r3, #40] ; 0x28 8002130: f003 0310 and.w r3, r3, #16 8002134: 2b00 cmp r3, #0 8002136: d105 bne.n 8002144 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 8002138: 687b ldr r3, [r7, #4] 800213a: 6a9b ldr r3, [r3, #40] ; 0x28 800213c: f443 7200 orr.w r2, r3, #512 ; 0x200 8002140: 687b ldr r3, [r7, #4] 8002142: 629a str r2, [r3, #40] ; 0x28 /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 8002144: 687b ldr r3, [r7, #4] 8002146: 681b ldr r3, [r3, #0] 8002148: 689b ldr r3, [r3, #8] 800214a: f403 2360 and.w r3, r3, #917504 ; 0xe0000 800214e: f5b3 2f60 cmp.w r3, #917504 ; 0xe0000 8002152: d11d bne.n 8002190 (hadc->Init.ContinuousConvMode == DISABLE) ) 8002154: 687b ldr r3, [r7, #4] 8002156: 7b1b ldrb r3, [r3, #12] if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 8002158: 2b00 cmp r3, #0 800215a: d119 bne.n 8002190 { /* Disable ADC end of conversion interrupt on group regular */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); 800215c: 687b ldr r3, [r7, #4] 800215e: 681b ldr r3, [r3, #0] 8002160: 685a ldr r2, [r3, #4] 8002162: 687b ldr r3, [r7, #4] 8002164: 681b ldr r3, [r3, #0] 8002166: f022 0220 bic.w r2, r2, #32 800216a: 605a str r2, [r3, #4] /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 800216c: 687b ldr r3, [r7, #4] 800216e: 6a9b ldr r3, [r3, #40] ; 0x28 8002170: f423 7280 bic.w r2, r3, #256 ; 0x100 8002174: 687b ldr r3, [r7, #4] 8002176: 629a str r2, [r3, #40] ; 0x28 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 8002178: 687b ldr r3, [r7, #4] 800217a: 6a9b ldr r3, [r3, #40] ; 0x28 800217c: f403 5380 and.w r3, r3, #4096 ; 0x1000 8002180: 2b00 cmp r3, #0 8002182: d105 bne.n 8002190 { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 8002184: 687b ldr r3, [r7, #4] 8002186: 6a9b ldr r3, [r3, #40] ; 0x28 8002188: f043 0201 orr.w r2, r3, #1 800218c: 687b ldr r3, [r7, #4] 800218e: 629a str r2, [r3, #40] ; 0x28 /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); 8002190: 6878 ldr r0, [r7, #4] 8002192: f7ff faab bl 80016ec #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear regular group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); 8002196: 687b ldr r3, [r7, #4] 8002198: 681b ldr r3, [r3, #0] 800219a: f06f 0212 mvn.w r2, #18 800219e: 601a str r2, [r3, #0] } } /* ========== Check End of Conversion flag for injected group ========== */ if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC)) 80021a0: 687b ldr r3, [r7, #4] 80021a2: 681b ldr r3, [r3, #0] 80021a4: 685b ldr r3, [r3, #4] 80021a6: f003 0380 and.w r3, r3, #128 ; 0x80 80021aa: 2b80 cmp r3, #128 ; 0x80 80021ac: d14f bne.n 800224e { if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC)) 80021ae: 687b ldr r3, [r7, #4] 80021b0: 681b ldr r3, [r3, #0] 80021b2: 681b ldr r3, [r3, #0] 80021b4: f003 0304 and.w r3, r3, #4 80021b8: 2b04 cmp r3, #4 80021ba: d148 bne.n 800224e { /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) 80021bc: 687b ldr r3, [r7, #4] 80021be: 6a9b ldr r3, [r3, #40] ; 0x28 80021c0: f003 0310 and.w r3, r3, #16 80021c4: 2b00 cmp r3, #0 80021c6: d105 bne.n 80021d4 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); 80021c8: 687b ldr r3, [r7, #4] 80021ca: 6a9b ldr r3, [r3, #40] ; 0x28 80021cc: f443 5200 orr.w r2, r3, #8192 ; 0x2000 80021d0: 687b ldr r3, [r7, #4] 80021d2: 629a str r2, [r3, #40] ; 0x28 /* conversion from group regular (same conditions as group regular */ /* interruption disabling above). */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_INJECTED(hadc) || 80021d4: 687b ldr r3, [r7, #4] 80021d6: 681b ldr r3, [r3, #0] 80021d8: 689b ldr r3, [r3, #8] 80021da: f403 43e0 and.w r3, r3, #28672 ; 0x7000 80021de: f5b3 4fe0 cmp.w r3, #28672 ; 0x7000 80021e2: d012 beq.n 800220a (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && 80021e4: 687b ldr r3, [r7, #4] 80021e6: 681b ldr r3, [r3, #0] 80021e8: 685b ldr r3, [r3, #4] 80021ea: f403 6380 and.w r3, r3, #1024 ; 0x400 if(ADC_IS_SOFTWARE_START_INJECTED(hadc) || 80021ee: 2b00 cmp r3, #0 80021f0: d125 bne.n 800223e (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 80021f2: 687b ldr r3, [r7, #4] 80021f4: 681b ldr r3, [r3, #0] 80021f6: 689b ldr r3, [r3, #8] 80021f8: f403 2360 and.w r3, r3, #917504 ; 0xe0000 (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && 80021fc: f5b3 2f60 cmp.w r3, #917504 ; 0xe0000 8002200: d11d bne.n 800223e (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) 8002202: 687b ldr r3, [r7, #4] 8002204: 7b1b ldrb r3, [r3, #12] (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 8002206: 2b00 cmp r3, #0 8002208: d119 bne.n 800223e { /* Disable ADC end of conversion interrupt on group injected */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); 800220a: 687b ldr r3, [r7, #4] 800220c: 681b ldr r3, [r3, #0] 800220e: 685a ldr r2, [r3, #4] 8002210: 687b ldr r3, [r7, #4] 8002212: 681b ldr r3, [r3, #0] 8002214: f022 0280 bic.w r2, r2, #128 ; 0x80 8002218: 605a str r2, [r3, #4] /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); 800221a: 687b ldr r3, [r7, #4] 800221c: 6a9b ldr r3, [r3, #40] ; 0x28 800221e: f423 5280 bic.w r2, r3, #4096 ; 0x1000 8002222: 687b ldr r3, [r7, #4] 8002224: 629a str r2, [r3, #40] ; 0x28 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) 8002226: 687b ldr r3, [r7, #4] 8002228: 6a9b ldr r3, [r3, #40] ; 0x28 800222a: f403 7380 and.w r3, r3, #256 ; 0x100 800222e: 2b00 cmp r3, #0 8002230: d105 bne.n 800223e { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 8002232: 687b ldr r3, [r7, #4] 8002234: 6a9b ldr r3, [r3, #40] ; 0x28 8002236: f043 0201 orr.w r2, r3, #1 800223a: 687b ldr r3, [r7, #4] 800223c: 629a str r2, [r3, #40] ; 0x28 /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->InjectedConvCpltCallback(hadc); #else HAL_ADCEx_InjectedConvCpltCallback(hadc); 800223e: 6878 ldr r0, [r7, #4] 8002240: f000 fac6 bl 80027d0 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear injected group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC)); 8002244: 687b ldr r3, [r7, #4] 8002246: 681b ldr r3, [r3, #0] 8002248: f06f 020c mvn.w r2, #12 800224c: 601a str r2, [r3, #0] } } /* ========== Check Analog watchdog flags ========== */ if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD)) 800224e: 687b ldr r3, [r7, #4] 8002250: 681b ldr r3, [r3, #0] 8002252: 685b ldr r3, [r3, #4] 8002254: f003 0340 and.w r3, r3, #64 ; 0x40 8002258: 2b40 cmp r3, #64 ; 0x40 800225a: d114 bne.n 8002286 { if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD)) 800225c: 687b ldr r3, [r7, #4] 800225e: 681b ldr r3, [r3, #0] 8002260: 681b ldr r3, [r3, #0] 8002262: f003 0301 and.w r3, r3, #1 8002266: 2b01 cmp r3, #1 8002268: d10d bne.n 8002286 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); 800226a: 687b ldr r3, [r7, #4] 800226c: 6a9b ldr r3, [r3, #40] ; 0x28 800226e: f443 3280 orr.w r2, r3, #65536 ; 0x10000 8002272: 687b ldr r3, [r7, #4] 8002274: 629a str r2, [r3, #40] ; 0x28 /* Level out of window callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->LevelOutOfWindowCallback(hadc); #else HAL_ADC_LevelOutOfWindowCallback(hadc); 8002276: 6878 ldr r0, [r7, #4] 8002278: f000 f812 bl 80022a0 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear the ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); 800227c: 687b ldr r3, [r7, #4] 800227e: 681b ldr r3, [r3, #0] 8002280: f06f 0201 mvn.w r2, #1 8002284: 601a str r2, [r3, #0] } } } 8002286: bf00 nop 8002288: 3708 adds r7, #8 800228a: 46bd mov sp, r7 800228c: bd80 pop {r7, pc} 0800228e : * @brief Conversion DMA half-transfer callback in non blocking mode * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) { 800228e: b480 push {r7} 8002290: b083 sub sp, #12 8002292: af00 add r7, sp, #0 8002294: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. */ } 8002296: bf00 nop 8002298: 370c adds r7, #12 800229a: 46bd mov sp, r7 800229c: bc80 pop {r7} 800229e: 4770 bx lr 080022a0 : * @brief Analog watchdog callback in non blocking mode. * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) { 80022a0: b480 push {r7} 80022a2: b083 sub sp, #12 80022a4: af00 add r7, sp, #0 80022a6: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file. */ } 80022a8: bf00 nop 80022aa: 370c adds r7, #12 80022ac: 46bd mov sp, r7 80022ae: bc80 pop {r7} 80022b0: 4770 bx lr 080022b2 : * (ADC conversion with interruption or transfer by DMA) * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) { 80022b2: b480 push {r7} 80022b4: b083 sub sp, #12 80022b6: af00 add r7, sp, #0 80022b8: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ErrorCallback must be implemented in the user file. */ } 80022ba: bf00 nop 80022bc: 370c adds r7, #12 80022be: 46bd mov sp, r7 80022c0: bc80 pop {r7} 80022c2: 4770 bx lr 080022c4 : * @param hadc: ADC handle * @param sConfig: Structure of ADC channel for regular group. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { 80022c4: b480 push {r7} 80022c6: b085 sub sp, #20 80022c8: af00 add r7, sp, #0 80022ca: 6078 str r0, [r7, #4] 80022cc: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 80022ce: 2300 movs r3, #0 80022d0: 73fb strb r3, [r7, #15] __IO uint32_t wait_loop_index = 0U; 80022d2: 2300 movs r3, #0 80022d4: 60bb str r3, [r7, #8] assert_param(IS_ADC_CHANNEL(sConfig->Channel)); assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); /* Process locked */ __HAL_LOCK(hadc); 80022d6: 687b ldr r3, [r7, #4] 80022d8: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 80022dc: 2b01 cmp r3, #1 80022de: d101 bne.n 80022e4 80022e0: 2302 movs r3, #2 80022e2: e0dc b.n 800249e 80022e4: 687b ldr r3, [r7, #4] 80022e6: 2201 movs r2, #1 80022e8: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Regular sequence configuration */ /* For Rank 1 to 6 */ if (sConfig->Rank < 7U) 80022ec: 683b ldr r3, [r7, #0] 80022ee: 685b ldr r3, [r3, #4] 80022f0: 2b06 cmp r3, #6 80022f2: d81c bhi.n 800232e { MODIFY_REG(hadc->Instance->SQR3 , 80022f4: 687b ldr r3, [r7, #4] 80022f6: 681b ldr r3, [r3, #0] 80022f8: 6b59 ldr r1, [r3, #52] ; 0x34 80022fa: 683b ldr r3, [r7, #0] 80022fc: 685a ldr r2, [r3, #4] 80022fe: 4613 mov r3, r2 8002300: 009b lsls r3, r3, #2 8002302: 4413 add r3, r2 8002304: 3b05 subs r3, #5 8002306: 221f movs r2, #31 8002308: fa02 f303 lsl.w r3, r2, r3 800230c: 43db mvns r3, r3 800230e: 4019 ands r1, r3 8002310: 683b ldr r3, [r7, #0] 8002312: 6818 ldr r0, [r3, #0] 8002314: 683b ldr r3, [r7, #0] 8002316: 685a ldr r2, [r3, #4] 8002318: 4613 mov r3, r2 800231a: 009b lsls r3, r3, #2 800231c: 4413 add r3, r2 800231e: 3b05 subs r3, #5 8002320: fa00 f203 lsl.w r2, r0, r3 8002324: 687b ldr r3, [r7, #4] 8002326: 681b ldr r3, [r3, #0] 8002328: 430a orrs r2, r1 800232a: 635a str r2, [r3, #52] ; 0x34 800232c: e03c b.n 80023a8 ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) , ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 7 to 12 */ else if (sConfig->Rank < 13U) 800232e: 683b ldr r3, [r7, #0] 8002330: 685b ldr r3, [r3, #4] 8002332: 2b0c cmp r3, #12 8002334: d81c bhi.n 8002370 { MODIFY_REG(hadc->Instance->SQR2 , 8002336: 687b ldr r3, [r7, #4] 8002338: 681b ldr r3, [r3, #0] 800233a: 6b19 ldr r1, [r3, #48] ; 0x30 800233c: 683b ldr r3, [r7, #0] 800233e: 685a ldr r2, [r3, #4] 8002340: 4613 mov r3, r2 8002342: 009b lsls r3, r3, #2 8002344: 4413 add r3, r2 8002346: 3b23 subs r3, #35 ; 0x23 8002348: 221f movs r2, #31 800234a: fa02 f303 lsl.w r3, r2, r3 800234e: 43db mvns r3, r3 8002350: 4019 ands r1, r3 8002352: 683b ldr r3, [r7, #0] 8002354: 6818 ldr r0, [r3, #0] 8002356: 683b ldr r3, [r7, #0] 8002358: 685a ldr r2, [r3, #4] 800235a: 4613 mov r3, r2 800235c: 009b lsls r3, r3, #2 800235e: 4413 add r3, r2 8002360: 3b23 subs r3, #35 ; 0x23 8002362: fa00 f203 lsl.w r2, r0, r3 8002366: 687b ldr r3, [r7, #4] 8002368: 681b ldr r3, [r3, #0] 800236a: 430a orrs r2, r1 800236c: 631a str r2, [r3, #48] ; 0x30 800236e: e01b b.n 80023a8 ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 13 to 16 */ else { MODIFY_REG(hadc->Instance->SQR1 , 8002370: 687b ldr r3, [r7, #4] 8002372: 681b ldr r3, [r3, #0] 8002374: 6ad9 ldr r1, [r3, #44] ; 0x2c 8002376: 683b ldr r3, [r7, #0] 8002378: 685a ldr r2, [r3, #4] 800237a: 4613 mov r3, r2 800237c: 009b lsls r3, r3, #2 800237e: 4413 add r3, r2 8002380: 3b41 subs r3, #65 ; 0x41 8002382: 221f movs r2, #31 8002384: fa02 f303 lsl.w r3, r2, r3 8002388: 43db mvns r3, r3 800238a: 4019 ands r1, r3 800238c: 683b ldr r3, [r7, #0] 800238e: 6818 ldr r0, [r3, #0] 8002390: 683b ldr r3, [r7, #0] 8002392: 685a ldr r2, [r3, #4] 8002394: 4613 mov r3, r2 8002396: 009b lsls r3, r3, #2 8002398: 4413 add r3, r2 800239a: 3b41 subs r3, #65 ; 0x41 800239c: fa00 f203 lsl.w r2, r0, r3 80023a0: 687b ldr r3, [r7, #4] 80023a2: 681b ldr r3, [r3, #0] 80023a4: 430a orrs r2, r1 80023a6: 62da str r2, [r3, #44] ; 0x2c } /* Channel sampling time configuration */ /* For channels 10 to 17 */ if (sConfig->Channel >= ADC_CHANNEL_10) 80023a8: 683b ldr r3, [r7, #0] 80023aa: 681b ldr r3, [r3, #0] 80023ac: 2b09 cmp r3, #9 80023ae: d91c bls.n 80023ea { MODIFY_REG(hadc->Instance->SMPR1 , 80023b0: 687b ldr r3, [r7, #4] 80023b2: 681b ldr r3, [r3, #0] 80023b4: 68d9 ldr r1, [r3, #12] 80023b6: 683b ldr r3, [r7, #0] 80023b8: 681a ldr r2, [r3, #0] 80023ba: 4613 mov r3, r2 80023bc: 005b lsls r3, r3, #1 80023be: 4413 add r3, r2 80023c0: 3b1e subs r3, #30 80023c2: 2207 movs r2, #7 80023c4: fa02 f303 lsl.w r3, r2, r3 80023c8: 43db mvns r3, r3 80023ca: 4019 ands r1, r3 80023cc: 683b ldr r3, [r7, #0] 80023ce: 6898 ldr r0, [r3, #8] 80023d0: 683b ldr r3, [r7, #0] 80023d2: 681a ldr r2, [r3, #0] 80023d4: 4613 mov r3, r2 80023d6: 005b lsls r3, r3, #1 80023d8: 4413 add r3, r2 80023da: 3b1e subs r3, #30 80023dc: fa00 f203 lsl.w r2, r0, r3 80023e0: 687b ldr r3, [r7, #4] 80023e2: 681b ldr r3, [r3, #0] 80023e4: 430a orrs r2, r1 80023e6: 60da str r2, [r3, #12] 80023e8: e019 b.n 800241e ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) , ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) ); } else /* For channels 0 to 9 */ { MODIFY_REG(hadc->Instance->SMPR2 , 80023ea: 687b ldr r3, [r7, #4] 80023ec: 681b ldr r3, [r3, #0] 80023ee: 6919 ldr r1, [r3, #16] 80023f0: 683b ldr r3, [r7, #0] 80023f2: 681a ldr r2, [r3, #0] 80023f4: 4613 mov r3, r2 80023f6: 005b lsls r3, r3, #1 80023f8: 4413 add r3, r2 80023fa: 2207 movs r2, #7 80023fc: fa02 f303 lsl.w r3, r2, r3 8002400: 43db mvns r3, r3 8002402: 4019 ands r1, r3 8002404: 683b ldr r3, [r7, #0] 8002406: 6898 ldr r0, [r3, #8] 8002408: 683b ldr r3, [r7, #0] 800240a: 681a ldr r2, [r3, #0] 800240c: 4613 mov r3, r2 800240e: 005b lsls r3, r3, #1 8002410: 4413 add r3, r2 8002412: fa00 f203 lsl.w r2, r0, r3 8002416: 687b ldr r3, [r7, #4] 8002418: 681b ldr r3, [r3, #0] 800241a: 430a orrs r2, r1 800241c: 611a str r2, [r3, #16] ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); } /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ /* and VREFINT measurement path. */ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 800241e: 683b ldr r3, [r7, #0] 8002420: 681b ldr r3, [r3, #0] 8002422: 2b10 cmp r3, #16 8002424: d003 beq.n 800242e (sConfig->Channel == ADC_CHANNEL_VREFINT) ) 8002426: 683b ldr r3, [r7, #0] 8002428: 681b ldr r3, [r3, #0] if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 800242a: 2b11 cmp r3, #17 800242c: d132 bne.n 8002494 { /* For STM32F1 devices with several ADC: Only ADC1 can access internal */ /* measurement channels (VrefInt/TempSensor). If these channels are */ /* intended to be set on other ADC instances, an error is reported. */ if (hadc->Instance == ADC1) 800242e: 687b ldr r3, [r7, #4] 8002430: 681b ldr r3, [r3, #0] 8002432: 4a1d ldr r2, [pc, #116] ; (80024a8 ) 8002434: 4293 cmp r3, r2 8002436: d125 bne.n 8002484 { if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET) 8002438: 687b ldr r3, [r7, #4] 800243a: 681b ldr r3, [r3, #0] 800243c: 689b ldr r3, [r3, #8] 800243e: f403 0300 and.w r3, r3, #8388608 ; 0x800000 8002442: 2b00 cmp r3, #0 8002444: d126 bne.n 8002494 { SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); 8002446: 687b ldr r3, [r7, #4] 8002448: 681b ldr r3, [r3, #0] 800244a: 689a ldr r2, [r3, #8] 800244c: 687b ldr r3, [r7, #4] 800244e: 681b ldr r3, [r3, #0] 8002450: f442 0200 orr.w r2, r2, #8388608 ; 0x800000 8002454: 609a str r2, [r3, #8] if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)) 8002456: 683b ldr r3, [r7, #0] 8002458: 681b ldr r3, [r3, #0] 800245a: 2b10 cmp r3, #16 800245c: d11a bne.n 8002494 { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); 800245e: 4b13 ldr r3, [pc, #76] ; (80024ac ) 8002460: 681b ldr r3, [r3, #0] 8002462: 4a13 ldr r2, [pc, #76] ; (80024b0 ) 8002464: fba2 2303 umull r2, r3, r2, r3 8002468: 0c9a lsrs r2, r3, #18 800246a: 4613 mov r3, r2 800246c: 009b lsls r3, r3, #2 800246e: 4413 add r3, r2 8002470: 005b lsls r3, r3, #1 8002472: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 8002474: e002 b.n 800247c { wait_loop_index--; 8002476: 68bb ldr r3, [r7, #8] 8002478: 3b01 subs r3, #1 800247a: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800247c: 68bb ldr r3, [r7, #8] 800247e: 2b00 cmp r3, #0 8002480: d1f9 bne.n 8002476 8002482: e007 b.n 8002494 } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8002484: 687b ldr r3, [r7, #4] 8002486: 6a9b ldr r3, [r3, #40] ; 0x28 8002488: f043 0220 orr.w r2, r3, #32 800248c: 687b ldr r3, [r7, #4] 800248e: 629a str r2, [r3, #40] ; 0x28 tmp_hal_status = HAL_ERROR; 8002490: 2301 movs r3, #1 8002492: 73fb strb r3, [r7, #15] } } /* Process unlocked */ __HAL_UNLOCK(hadc); 8002494: 687b ldr r3, [r7, #4] 8002496: 2200 movs r2, #0 8002498: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Return function status */ return tmp_hal_status; 800249c: 7bfb ldrb r3, [r7, #15] } 800249e: 4618 mov r0, r3 80024a0: 3714 adds r7, #20 80024a2: 46bd mov sp, r7 80024a4: bc80 pop {r7} 80024a6: 4770 bx lr 80024a8: 40012400 .word 0x40012400 80024ac: 20000008 .word 0x20000008 80024b0: 431bde83 .word 0x431bde83 080024b4 : * and voltage regulator must be enabled (done into HAL_ADC_Init()). * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) { 80024b4: b580 push {r7, lr} 80024b6: b084 sub sp, #16 80024b8: af00 add r7, sp, #0 80024ba: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 80024bc: 2300 movs r3, #0 80024be: 60fb str r3, [r7, #12] __IO uint32_t wait_loop_index = 0U; 80024c0: 2300 movs r3, #0 80024c2: 60bb str r3, [r7, #8] /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ if (ADC_IS_ENABLE(hadc) == RESET) 80024c4: 687b ldr r3, [r7, #4] 80024c6: 681b ldr r3, [r3, #0] 80024c8: 689b ldr r3, [r3, #8] 80024ca: f003 0301 and.w r3, r3, #1 80024ce: 2b01 cmp r3, #1 80024d0: d039 beq.n 8002546 { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); 80024d2: 687b ldr r3, [r7, #4] 80024d4: 681b ldr r3, [r3, #0] 80024d6: 689a ldr r2, [r3, #8] 80024d8: 687b ldr r3, [r7, #4] 80024da: 681b ldr r3, [r3, #0] 80024dc: f042 0201 orr.w r2, r2, #1 80024e0: 609a str r2, [r3, #8] /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); 80024e2: 4b1b ldr r3, [pc, #108] ; (8002550 ) 80024e4: 681b ldr r3, [r3, #0] 80024e6: 4a1b ldr r2, [pc, #108] ; (8002554 ) 80024e8: fba2 2303 umull r2, r3, r2, r3 80024ec: 0c9b lsrs r3, r3, #18 80024ee: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 80024f0: e002 b.n 80024f8 { wait_loop_index--; 80024f2: 68bb ldr r3, [r7, #8] 80024f4: 3b01 subs r3, #1 80024f6: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 80024f8: 68bb ldr r3, [r7, #8] 80024fa: 2b00 cmp r3, #0 80024fc: d1f9 bne.n 80024f2 } /* Get tick count */ tickstart = HAL_GetTick(); 80024fe: f7ff fc65 bl 8001dcc 8002502: 60f8 str r0, [r7, #12] /* Wait for ADC effectively enabled */ while(ADC_IS_ENABLE(hadc) == RESET) 8002504: e018 b.n 8002538 { if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) 8002506: f7ff fc61 bl 8001dcc 800250a: 4602 mov r2, r0 800250c: 68fb ldr r3, [r7, #12] 800250e: 1ad3 subs r3, r2, r3 8002510: 2b02 cmp r3, #2 8002512: d911 bls.n 8002538 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8002514: 687b ldr r3, [r7, #4] 8002516: 6a9b ldr r3, [r3, #40] ; 0x28 8002518: f043 0210 orr.w r2, r3, #16 800251c: 687b ldr r3, [r7, #4] 800251e: 629a str r2, [r3, #40] ; 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8002520: 687b ldr r3, [r7, #4] 8002522: 6adb ldr r3, [r3, #44] ; 0x2c 8002524: f043 0201 orr.w r2, r3, #1 8002528: 687b ldr r3, [r7, #4] 800252a: 62da str r2, [r3, #44] ; 0x2c /* Process unlocked */ __HAL_UNLOCK(hadc); 800252c: 687b ldr r3, [r7, #4] 800252e: 2200 movs r2, #0 8002530: f883 2024 strb.w r2, [r3, #36] ; 0x24 return HAL_ERROR; 8002534: 2301 movs r3, #1 8002536: e007 b.n 8002548 while(ADC_IS_ENABLE(hadc) == RESET) 8002538: 687b ldr r3, [r7, #4] 800253a: 681b ldr r3, [r3, #0] 800253c: 689b ldr r3, [r3, #8] 800253e: f003 0301 and.w r3, r3, #1 8002542: 2b01 cmp r3, #1 8002544: d1df bne.n 8002506 } } } /* Return HAL status */ return HAL_OK; 8002546: 2300 movs r3, #0 } 8002548: 4618 mov r0, r3 800254a: 3710 adds r7, #16 800254c: 46bd mov sp, r7 800254e: bd80 pop {r7, pc} 8002550: 20000008 .word 0x20000008 8002554: 431bde83 .word 0x431bde83 08002558 : * stopped to disable the ADC. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc) { 8002558: b580 push {r7, lr} 800255a: b084 sub sp, #16 800255c: af00 add r7, sp, #0 800255e: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8002560: 2300 movs r3, #0 8002562: 60fb str r3, [r7, #12] /* Verification if ADC is not already disabled */ if (ADC_IS_ENABLE(hadc) != RESET) 8002564: 687b ldr r3, [r7, #4] 8002566: 681b ldr r3, [r3, #0] 8002568: 689b ldr r3, [r3, #8] 800256a: f003 0301 and.w r3, r3, #1 800256e: 2b01 cmp r3, #1 8002570: d127 bne.n 80025c2 { /* Disable the ADC peripheral */ __HAL_ADC_DISABLE(hadc); 8002572: 687b ldr r3, [r7, #4] 8002574: 681b ldr r3, [r3, #0] 8002576: 689a ldr r2, [r3, #8] 8002578: 687b ldr r3, [r7, #4] 800257a: 681b ldr r3, [r3, #0] 800257c: f022 0201 bic.w r2, r2, #1 8002580: 609a str r2, [r3, #8] /* Get tick count */ tickstart = HAL_GetTick(); 8002582: f7ff fc23 bl 8001dcc 8002586: 60f8 str r0, [r7, #12] /* Wait for ADC effectively disabled */ while(ADC_IS_ENABLE(hadc) != RESET) 8002588: e014 b.n 80025b4 { if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 800258a: f7ff fc1f bl 8001dcc 800258e: 4602 mov r2, r0 8002590: 68fb ldr r3, [r7, #12] 8002592: 1ad3 subs r3, r2, r3 8002594: 2b02 cmp r3, #2 8002596: d90d bls.n 80025b4 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8002598: 687b ldr r3, [r7, #4] 800259a: 6a9b ldr r3, [r3, #40] ; 0x28 800259c: f043 0210 orr.w r2, r3, #16 80025a0: 687b ldr r3, [r7, #4] 80025a2: 629a str r2, [r3, #40] ; 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 80025a4: 687b ldr r3, [r7, #4] 80025a6: 6adb ldr r3, [r3, #44] ; 0x2c 80025a8: f043 0201 orr.w r2, r3, #1 80025ac: 687b ldr r3, [r7, #4] 80025ae: 62da str r2, [r3, #44] ; 0x2c return HAL_ERROR; 80025b0: 2301 movs r3, #1 80025b2: e007 b.n 80025c4 while(ADC_IS_ENABLE(hadc) != RESET) 80025b4: 687b ldr r3, [r7, #4] 80025b6: 681b ldr r3, [r3, #0] 80025b8: 689b ldr r3, [r3, #8] 80025ba: f003 0301 and.w r3, r3, #1 80025be: 2b01 cmp r3, #1 80025c0: d0e3 beq.n 800258a } } } /* Return HAL status */ return HAL_OK; 80025c2: 2300 movs r3, #0 } 80025c4: 4618 mov r0, r3 80025c6: 3710 adds r7, #16 80025c8: 46bd mov sp, r7 80025ca: bd80 pop {r7, pc} 080025cc : * @brief DMA transfer complete callback. * @param hdma: pointer to DMA handle. * @retval None */ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) { 80025cc: b580 push {r7, lr} 80025ce: b084 sub sp, #16 80025d0: af00 add r7, sp, #0 80025d2: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 80025d4: 687b ldr r3, [r7, #4] 80025d6: 6a5b ldr r3, [r3, #36] ; 0x24 80025d8: 60fb str r3, [r7, #12] /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) 80025da: 68fb ldr r3, [r7, #12] 80025dc: 6a9b ldr r3, [r3, #40] ; 0x28 80025de: f003 0350 and.w r3, r3, #80 ; 0x50 80025e2: 2b00 cmp r3, #0 80025e4: d127 bne.n 8002636 { /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 80025e6: 68fb ldr r3, [r7, #12] 80025e8: 6a9b ldr r3, [r3, #40] ; 0x28 80025ea: f443 7200 orr.w r2, r3, #512 ; 0x200 80025ee: 68fb ldr r3, [r7, #12] 80025f0: 629a str r2, [r3, #40] ; 0x28 /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 80025f2: 68fb ldr r3, [r7, #12] 80025f4: 681b ldr r3, [r3, #0] 80025f6: 689b ldr r3, [r3, #8] 80025f8: f403 2360 and.w r3, r3, #917504 ; 0xe0000 80025fc: f5b3 2f60 cmp.w r3, #917504 ; 0xe0000 8002600: d115 bne.n 800262e (hadc->Init.ContinuousConvMode == DISABLE) ) 8002602: 68fb ldr r3, [r7, #12] 8002604: 7b1b ldrb r3, [r3, #12] if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 8002606: 2b00 cmp r3, #0 8002608: d111 bne.n 800262e { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 800260a: 68fb ldr r3, [r7, #12] 800260c: 6a9b ldr r3, [r3, #40] ; 0x28 800260e: f423 7280 bic.w r2, r3, #256 ; 0x100 8002612: 68fb ldr r3, [r7, #12] 8002614: 629a str r2, [r3, #40] ; 0x28 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 8002616: 68fb ldr r3, [r7, #12] 8002618: 6a9b ldr r3, [r3, #40] ; 0x28 800261a: f403 5380 and.w r3, r3, #4096 ; 0x1000 800261e: 2b00 cmp r3, #0 8002620: d105 bne.n 800262e { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 8002622: 68fb ldr r3, [r7, #12] 8002624: 6a9b ldr r3, [r3, #40] ; 0x28 8002626: f043 0201 orr.w r2, r3, #1 800262a: 68fb ldr r3, [r7, #12] 800262c: 629a str r2, [r3, #40] ; 0x28 /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); 800262e: 68f8 ldr r0, [r7, #12] 8002630: f7ff f85c bl 80016ec else { /* Call DMA error callback */ hadc->DMA_Handle->XferErrorCallback(hdma); } } 8002634: e004 b.n 8002640 hadc->DMA_Handle->XferErrorCallback(hdma); 8002636: 68fb ldr r3, [r7, #12] 8002638: 6a1b ldr r3, [r3, #32] 800263a: 6b1b ldr r3, [r3, #48] ; 0x30 800263c: 6878 ldr r0, [r7, #4] 800263e: 4798 blx r3 } 8002640: bf00 nop 8002642: 3710 adds r7, #16 8002644: 46bd mov sp, r7 8002646: bd80 pop {r7, pc} 08002648 : * @brief DMA half transfer complete callback. * @param hdma: pointer to DMA handle. * @retval None */ void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) { 8002648: b580 push {r7, lr} 800264a: b084 sub sp, #16 800264c: af00 add r7, sp, #0 800264e: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 8002650: 687b ldr r3, [r7, #4] 8002652: 6a5b ldr r3, [r3, #36] ; 0x24 8002654: 60fb str r3, [r7, #12] /* Half conversion callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvHalfCpltCallback(hadc); #else HAL_ADC_ConvHalfCpltCallback(hadc); 8002656: 68f8 ldr r0, [r7, #12] 8002658: f7ff fe19 bl 800228e #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } 800265c: bf00 nop 800265e: 3710 adds r7, #16 8002660: 46bd mov sp, r7 8002662: bd80 pop {r7, pc} 08002664 : * @brief DMA error callback * @param hdma: pointer to DMA handle. * @retval None */ void ADC_DMAError(DMA_HandleTypeDef *hdma) { 8002664: b580 push {r7, lr} 8002666: b084 sub sp, #16 8002668: af00 add r7, sp, #0 800266a: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 800266c: 687b ldr r3, [r7, #4] 800266e: 6a5b ldr r3, [r3, #36] ; 0x24 8002670: 60fb str r3, [r7, #12] /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); 8002672: 68fb ldr r3, [r7, #12] 8002674: 6a9b ldr r3, [r3, #40] ; 0x28 8002676: f043 0240 orr.w r2, r3, #64 ; 0x40 800267a: 68fb ldr r3, [r7, #12] 800267c: 629a str r2, [r3, #40] ; 0x28 /* Set ADC error code to DMA error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); 800267e: 68fb ldr r3, [r7, #12] 8002680: 6adb ldr r3, [r3, #44] ; 0x2c 8002682: f043 0204 orr.w r2, r3, #4 8002686: 68fb ldr r3, [r7, #12] 8002688: 62da str r2, [r3, #44] ; 0x2c /* Error callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ErrorCallback(hadc); #else HAL_ADC_ErrorCallback(hadc); 800268a: 68f8 ldr r0, [r7, #12] 800268c: f7ff fe11 bl 80022b2 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } 8002690: bf00 nop 8002692: 3710 adds r7, #16 8002694: 46bd mov sp, r7 8002696: bd80 pop {r7, pc} 08002698 : * the completion of this function. * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc) { 8002698: b590 push {r4, r7, lr} 800269a: b087 sub sp, #28 800269c: af00 add r7, sp, #0 800269e: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 80026a0: 2300 movs r3, #0 80026a2: 75fb strb r3, [r7, #23] uint32_t tickstart; __IO uint32_t wait_loop_index = 0U; 80026a4: 2300 movs r3, #0 80026a6: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); 80026a8: 687b ldr r3, [r7, #4] 80026aa: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 80026ae: 2b01 cmp r3, #1 80026b0: d101 bne.n 80026b6 80026b2: 2302 movs r3, #2 80026b4: e086 b.n 80027c4 80026b6: 687b ldr r3, [r7, #4] 80026b8: 2201 movs r2, #1 80026ba: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* 1. Calibration prerequisite: */ /* - ADC must be disabled for at least two ADC clock cycles in disable */ /* mode before ADC enable */ /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 80026be: 6878 ldr r0, [r7, #4] 80026c0: f7ff ff4a bl 8002558 80026c4: 4603 mov r3, r0 80026c6: 75fb strb r3, [r7, #23] /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) 80026c8: 7dfb ldrb r3, [r7, #23] 80026ca: 2b00 cmp r3, #0 80026cc: d175 bne.n 80027ba { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 80026ce: 687b ldr r3, [r7, #4] 80026d0: 6a9b ldr r3, [r3, #40] ; 0x28 80026d2: f423 5388 bic.w r3, r3, #4352 ; 0x1100 80026d6: f023 0302 bic.w r3, r3, #2 80026da: f043 0202 orr.w r2, r3, #2 80026de: 687b ldr r3, [r7, #4] 80026e0: 629a str r2, [r3, #40] ; 0x28 /* Hardware prerequisite: delay before starting the calibration. */ /* - Computation of CPU clock cycles corresponding to ADC clock cycles. */ /* - Wait for the expected ADC clock cycles delay */ wait_loop_index = ((SystemCoreClock / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) 80026e2: 4b3a ldr r3, [pc, #232] ; (80027cc ) 80026e4: 681c ldr r4, [r3, #0] 80026e6: 2002 movs r0, #2 80026e8: f001 fc20 bl 8003f2c 80026ec: 4603 mov r3, r0 80026ee: fbb4 f3f3 udiv r3, r4, r3 * ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES ); 80026f2: 005b lsls r3, r3, #1 wait_loop_index = ((SystemCoreClock 80026f4: 60fb str r3, [r7, #12] while(wait_loop_index != 0U) 80026f6: e002 b.n 80026fe { wait_loop_index--; 80026f8: 68fb ldr r3, [r7, #12] 80026fa: 3b01 subs r3, #1 80026fc: 60fb str r3, [r7, #12] while(wait_loop_index != 0U) 80026fe: 68fb ldr r3, [r7, #12] 8002700: 2b00 cmp r3, #0 8002702: d1f9 bne.n 80026f8 } /* 2. Enable the ADC peripheral */ ADC_Enable(hadc); 8002704: 6878 ldr r0, [r7, #4] 8002706: f7ff fed5 bl 80024b4 /* 3. Resets ADC calibration registers */ SET_BIT(hadc->Instance->CR2, ADC_CR2_RSTCAL); 800270a: 687b ldr r3, [r7, #4] 800270c: 681b ldr r3, [r3, #0] 800270e: 689a ldr r2, [r3, #8] 8002710: 687b ldr r3, [r7, #4] 8002712: 681b ldr r3, [r3, #0] 8002714: f042 0208 orr.w r2, r2, #8 8002718: 609a str r2, [r3, #8] tickstart = HAL_GetTick(); 800271a: f7ff fb57 bl 8001dcc 800271e: 6138 str r0, [r7, #16] /* Wait for calibration reset completion */ while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 8002720: e014 b.n 800274c { if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) 8002722: f7ff fb53 bl 8001dcc 8002726: 4602 mov r2, r0 8002728: 693b ldr r3, [r7, #16] 800272a: 1ad3 subs r3, r2, r3 800272c: 2b0a cmp r3, #10 800272e: d90d bls.n 800274c { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 8002730: 687b ldr r3, [r7, #4] 8002732: 6a9b ldr r3, [r3, #40] ; 0x28 8002734: f023 0312 bic.w r3, r3, #18 8002738: f043 0210 orr.w r2, r3, #16 800273c: 687b ldr r3, [r7, #4] 800273e: 629a str r2, [r3, #40] ; 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); 8002740: 687b ldr r3, [r7, #4] 8002742: 2200 movs r2, #0 8002744: f883 2024 strb.w r2, [r3, #36] ; 0x24 return HAL_ERROR; 8002748: 2301 movs r3, #1 800274a: e03b b.n 80027c4 while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 800274c: 687b ldr r3, [r7, #4] 800274e: 681b ldr r3, [r3, #0] 8002750: 689b ldr r3, [r3, #8] 8002752: f003 0308 and.w r3, r3, #8 8002756: 2b00 cmp r3, #0 8002758: d1e3 bne.n 8002722 } } /* 4. Start ADC calibration */ SET_BIT(hadc->Instance->CR2, ADC_CR2_CAL); 800275a: 687b ldr r3, [r7, #4] 800275c: 681b ldr r3, [r3, #0] 800275e: 689a ldr r2, [r3, #8] 8002760: 687b ldr r3, [r7, #4] 8002762: 681b ldr r3, [r3, #0] 8002764: f042 0204 orr.w r2, r2, #4 8002768: 609a str r2, [r3, #8] tickstart = HAL_GetTick(); 800276a: f7ff fb2f bl 8001dcc 800276e: 6138 str r0, [r7, #16] /* Wait for calibration completion */ while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 8002770: e014 b.n 800279c { if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) 8002772: f7ff fb2b bl 8001dcc 8002776: 4602 mov r2, r0 8002778: 693b ldr r3, [r7, #16] 800277a: 1ad3 subs r3, r2, r3 800277c: 2b0a cmp r3, #10 800277e: d90d bls.n 800279c { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 8002780: 687b ldr r3, [r7, #4] 8002782: 6a9b ldr r3, [r3, #40] ; 0x28 8002784: f023 0312 bic.w r3, r3, #18 8002788: f043 0210 orr.w r2, r3, #16 800278c: 687b ldr r3, [r7, #4] 800278e: 629a str r2, [r3, #40] ; 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); 8002790: 687b ldr r3, [r7, #4] 8002792: 2200 movs r2, #0 8002794: f883 2024 strb.w r2, [r3, #36] ; 0x24 return HAL_ERROR; 8002798: 2301 movs r3, #1 800279a: e013 b.n 80027c4 while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 800279c: 687b ldr r3, [r7, #4] 800279e: 681b ldr r3, [r3, #0] 80027a0: 689b ldr r3, [r3, #8] 80027a2: f003 0304 and.w r3, r3, #4 80027a6: 2b00 cmp r3, #0 80027a8: d1e3 bne.n 8002772 } } /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 80027aa: 687b ldr r3, [r7, #4] 80027ac: 6a9b ldr r3, [r3, #40] ; 0x28 80027ae: f023 0303 bic.w r3, r3, #3 80027b2: f043 0201 orr.w r2, r3, #1 80027b6: 687b ldr r3, [r7, #4] 80027b8: 629a str r2, [r3, #40] ; 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); } /* Process unlocked */ __HAL_UNLOCK(hadc); 80027ba: 687b ldr r3, [r7, #4] 80027bc: 2200 movs r2, #0 80027be: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Return function status */ return tmp_hal_status; 80027c2: 7dfb ldrb r3, [r7, #23] } 80027c4: 4618 mov r0, r3 80027c6: 371c adds r7, #28 80027c8: 46bd mov sp, r7 80027ca: bd90 pop {r4, r7, pc} 80027cc: 20000008 .word 0x20000008 080027d0 : * @brief Injected conversion complete callback in non blocking mode * @param hadc: ADC handle * @retval None */ __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) { 80027d0: b480 push {r7} 80027d2: b083 sub sp, #12 80027d4: af00 add r7, sp, #0 80027d6: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file */ } 80027d8: bf00 nop 80027da: 370c adds r7, #12 80027dc: 46bd mov sp, r7 80027de: bc80 pop {r7} 80027e0: 4770 bx lr ... 080027e4 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 80027e4: b480 push {r7} 80027e6: b085 sub sp, #20 80027e8: af00 add r7, sp, #0 80027ea: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 80027ec: 687b ldr r3, [r7, #4] 80027ee: f003 0307 and.w r3, r3, #7 80027f2: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 80027f4: 4b0c ldr r3, [pc, #48] ; (8002828 <__NVIC_SetPriorityGrouping+0x44>) 80027f6: 68db ldr r3, [r3, #12] 80027f8: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 80027fa: 68ba ldr r2, [r7, #8] 80027fc: f64f 03ff movw r3, #63743 ; 0xf8ff 8002800: 4013 ands r3, r2 8002802: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8002804: 68fb ldr r3, [r7, #12] 8002806: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8002808: 68bb ldr r3, [r7, #8] 800280a: 4313 orrs r3, r2 reg_value = (reg_value | 800280c: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 8002810: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8002814: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 8002816: 4a04 ldr r2, [pc, #16] ; (8002828 <__NVIC_SetPriorityGrouping+0x44>) 8002818: 68bb ldr r3, [r7, #8] 800281a: 60d3 str r3, [r2, #12] } 800281c: bf00 nop 800281e: 3714 adds r7, #20 8002820: 46bd mov sp, r7 8002822: bc80 pop {r7} 8002824: 4770 bx lr 8002826: bf00 nop 8002828: e000ed00 .word 0xe000ed00 0800282c <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 800282c: b480 push {r7} 800282e: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8002830: 4b04 ldr r3, [pc, #16] ; (8002844 <__NVIC_GetPriorityGrouping+0x18>) 8002832: 68db ldr r3, [r3, #12] 8002834: 0a1b lsrs r3, r3, #8 8002836: f003 0307 and.w r3, r3, #7 } 800283a: 4618 mov r0, r3 800283c: 46bd mov sp, r7 800283e: bc80 pop {r7} 8002840: 4770 bx lr 8002842: bf00 nop 8002844: e000ed00 .word 0xe000ed00 08002848 <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 8002848: b480 push {r7} 800284a: b083 sub sp, #12 800284c: af00 add r7, sp, #0 800284e: 4603 mov r3, r0 8002850: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8002852: f997 3007 ldrsb.w r3, [r7, #7] 8002856: 2b00 cmp r3, #0 8002858: db0b blt.n 8002872 <__NVIC_EnableIRQ+0x2a> { NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 800285a: 79fb ldrb r3, [r7, #7] 800285c: f003 021f and.w r2, r3, #31 8002860: 4906 ldr r1, [pc, #24] ; (800287c <__NVIC_EnableIRQ+0x34>) 8002862: f997 3007 ldrsb.w r3, [r7, #7] 8002866: 095b lsrs r3, r3, #5 8002868: 2001 movs r0, #1 800286a: fa00 f202 lsl.w r2, r0, r2 800286e: f841 2023 str.w r2, [r1, r3, lsl #2] } } 8002872: bf00 nop 8002874: 370c adds r7, #12 8002876: 46bd mov sp, r7 8002878: bc80 pop {r7} 800287a: 4770 bx lr 800287c: e000e100 .word 0xe000e100 08002880 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8002880: b480 push {r7} 8002882: b083 sub sp, #12 8002884: af00 add r7, sp, #0 8002886: 4603 mov r3, r0 8002888: 6039 str r1, [r7, #0] 800288a: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 800288c: f997 3007 ldrsb.w r3, [r7, #7] 8002890: 2b00 cmp r3, #0 8002892: db0a blt.n 80028aa <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8002894: 683b ldr r3, [r7, #0] 8002896: b2da uxtb r2, r3 8002898: 490c ldr r1, [pc, #48] ; (80028cc <__NVIC_SetPriority+0x4c>) 800289a: f997 3007 ldrsb.w r3, [r7, #7] 800289e: 0112 lsls r2, r2, #4 80028a0: b2d2 uxtb r2, r2 80028a2: 440b add r3, r1 80028a4: f883 2300 strb.w r2, [r3, #768] ; 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 80028a8: e00a b.n 80028c0 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80028aa: 683b ldr r3, [r7, #0] 80028ac: b2da uxtb r2, r3 80028ae: 4908 ldr r1, [pc, #32] ; (80028d0 <__NVIC_SetPriority+0x50>) 80028b0: 79fb ldrb r3, [r7, #7] 80028b2: f003 030f and.w r3, r3, #15 80028b6: 3b04 subs r3, #4 80028b8: 0112 lsls r2, r2, #4 80028ba: b2d2 uxtb r2, r2 80028bc: 440b add r3, r1 80028be: 761a strb r2, [r3, #24] } 80028c0: bf00 nop 80028c2: 370c adds r7, #12 80028c4: 46bd mov sp, r7 80028c6: bc80 pop {r7} 80028c8: 4770 bx lr 80028ca: bf00 nop 80028cc: e000e100 .word 0xe000e100 80028d0: e000ed00 .word 0xe000ed00 080028d4 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 80028d4: b480 push {r7} 80028d6: b089 sub sp, #36 ; 0x24 80028d8: af00 add r7, sp, #0 80028da: 60f8 str r0, [r7, #12] 80028dc: 60b9 str r1, [r7, #8] 80028de: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 80028e0: 68fb ldr r3, [r7, #12] 80028e2: f003 0307 and.w r3, r3, #7 80028e6: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 80028e8: 69fb ldr r3, [r7, #28] 80028ea: f1c3 0307 rsb r3, r3, #7 80028ee: 2b04 cmp r3, #4 80028f0: bf28 it cs 80028f2: 2304 movcs r3, #4 80028f4: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 80028f6: 69fb ldr r3, [r7, #28] 80028f8: 3304 adds r3, #4 80028fa: 2b06 cmp r3, #6 80028fc: d902 bls.n 8002904 80028fe: 69fb ldr r3, [r7, #28] 8002900: 3b03 subs r3, #3 8002902: e000 b.n 8002906 8002904: 2300 movs r3, #0 8002906: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8002908: f04f 32ff mov.w r2, #4294967295 800290c: 69bb ldr r3, [r7, #24] 800290e: fa02 f303 lsl.w r3, r2, r3 8002912: 43da mvns r2, r3 8002914: 68bb ldr r3, [r7, #8] 8002916: 401a ands r2, r3 8002918: 697b ldr r3, [r7, #20] 800291a: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 800291c: f04f 31ff mov.w r1, #4294967295 8002920: 697b ldr r3, [r7, #20] 8002922: fa01 f303 lsl.w r3, r1, r3 8002926: 43d9 mvns r1, r3 8002928: 687b ldr r3, [r7, #4] 800292a: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 800292c: 4313 orrs r3, r2 ); } 800292e: 4618 mov r0, r3 8002930: 3724 adds r7, #36 ; 0x24 8002932: 46bd mov sp, r7 8002934: bc80 pop {r7} 8002936: 4770 bx lr 08002938 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8002938: b580 push {r7, lr} 800293a: b082 sub sp, #8 800293c: af00 add r7, sp, #0 800293e: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8002940: 6878 ldr r0, [r7, #4] 8002942: f7ff ff4f bl 80027e4 <__NVIC_SetPriorityGrouping> } 8002946: bf00 nop 8002948: 3708 adds r7, #8 800294a: 46bd mov sp, r7 800294c: bd80 pop {r7, pc} 0800294e : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 800294e: b580 push {r7, lr} 8002950: b086 sub sp, #24 8002952: af00 add r7, sp, #0 8002954: 4603 mov r3, r0 8002956: 60b9 str r1, [r7, #8] 8002958: 607a str r2, [r7, #4] 800295a: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 800295c: 2300 movs r3, #0 800295e: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8002960: f7ff ff64 bl 800282c <__NVIC_GetPriorityGrouping> 8002964: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8002966: 687a ldr r2, [r7, #4] 8002968: 68b9 ldr r1, [r7, #8] 800296a: 6978 ldr r0, [r7, #20] 800296c: f7ff ffb2 bl 80028d4 8002970: 4602 mov r2, r0 8002972: f997 300f ldrsb.w r3, [r7, #15] 8002976: 4611 mov r1, r2 8002978: 4618 mov r0, r3 800297a: f7ff ff81 bl 8002880 <__NVIC_SetPriority> } 800297e: bf00 nop 8002980: 3718 adds r7, #24 8002982: 46bd mov sp, r7 8002984: bd80 pop {r7, pc} 08002986 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 8002986: b580 push {r7, lr} 8002988: b082 sub sp, #8 800298a: af00 add r7, sp, #0 800298c: 4603 mov r3, r0 800298e: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 8002990: f997 3007 ldrsb.w r3, [r7, #7] 8002994: 4618 mov r0, r3 8002996: f7ff ff57 bl 8002848 <__NVIC_EnableIRQ> } 800299a: bf00 nop 800299c: 3708 adds r7, #8 800299e: 46bd mov sp, r7 80029a0: bd80 pop {r7, pc} ... 080029a4 : * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { 80029a4: b480 push {r7} 80029a6: b085 sub sp, #20 80029a8: af00 add r7, sp, #0 80029aa: 6078 str r0, [r7, #4] uint32_t tmp = 0U; 80029ac: 2300 movs r3, #0 80029ae: 60fb str r3, [r7, #12] /* Check the DMA handle allocation */ if(hdma == NULL) 80029b0: 687b ldr r3, [r7, #4] 80029b2: 2b00 cmp r3, #0 80029b4: d101 bne.n 80029ba { return HAL_ERROR; 80029b6: 2301 movs r3, #1 80029b8: e043 b.n 8002a42 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; hdma->DmaBaseAddress = DMA2; } #else /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; 80029ba: 687b ldr r3, [r7, #4] 80029bc: 681b ldr r3, [r3, #0] 80029be: 461a mov r2, r3 80029c0: 4b22 ldr r3, [pc, #136] ; (8002a4c ) 80029c2: 4413 add r3, r2 80029c4: 4a22 ldr r2, [pc, #136] ; (8002a50 ) 80029c6: fba2 2303 umull r2, r3, r2, r3 80029ca: 091b lsrs r3, r3, #4 80029cc: 009a lsls r2, r3, #2 80029ce: 687b ldr r3, [r7, #4] 80029d0: 641a str r2, [r3, #64] ; 0x40 hdma->DmaBaseAddress = DMA1; 80029d2: 687b ldr r3, [r7, #4] 80029d4: 4a1f ldr r2, [pc, #124] ; (8002a54 ) 80029d6: 63da str r2, [r3, #60] ; 0x3c #endif /* DMA2 */ /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 80029d8: 687b ldr r3, [r7, #4] 80029da: 2202 movs r2, #2 80029dc: f883 2021 strb.w r2, [r3, #33] ; 0x21 /* Get the CR register value */ tmp = hdma->Instance->CCR; 80029e0: 687b ldr r3, [r7, #4] 80029e2: 681b ldr r3, [r3, #0] 80029e4: 681b ldr r3, [r3, #0] 80029e6: 60fb str r3, [r7, #12] /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ 80029e8: 68fb ldr r3, [r7, #12] 80029ea: f423 537f bic.w r3, r3, #16320 ; 0x3fc0 80029ee: f023 0330 bic.w r3, r3, #48 ; 0x30 80029f2: 60fb str r3, [r7, #12] DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ DMA_CCR_DIR)); /* Prepare the DMA Channel configuration */ tmp |= hdma->Init.Direction | 80029f4: 687b ldr r3, [r7, #4] 80029f6: 685a ldr r2, [r3, #4] hdma->Init.PeriphInc | hdma->Init.MemInc | 80029f8: 687b ldr r3, [r7, #4] 80029fa: 689b ldr r3, [r3, #8] tmp |= hdma->Init.Direction | 80029fc: 431a orrs r2, r3 hdma->Init.PeriphInc | hdma->Init.MemInc | 80029fe: 687b ldr r3, [r7, #4] 8002a00: 68db ldr r3, [r3, #12] 8002a02: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8002a04: 687b ldr r3, [r7, #4] 8002a06: 691b ldr r3, [r3, #16] hdma->Init.PeriphInc | hdma->Init.MemInc | 8002a08: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8002a0a: 687b ldr r3, [r7, #4] 8002a0c: 695b ldr r3, [r3, #20] 8002a0e: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 8002a10: 687b ldr r3, [r7, #4] 8002a12: 699b ldr r3, [r3, #24] hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8002a14: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 8002a16: 687b ldr r3, [r7, #4] 8002a18: 69db ldr r3, [r3, #28] 8002a1a: 4313 orrs r3, r2 tmp |= hdma->Init.Direction | 8002a1c: 68fa ldr r2, [r7, #12] 8002a1e: 4313 orrs r3, r2 8002a20: 60fb str r3, [r7, #12] /* Write to DMA Channel CR register */ hdma->Instance->CCR = tmp; 8002a22: 687b ldr r3, [r7, #4] 8002a24: 681b ldr r3, [r3, #0] 8002a26: 68fa ldr r2, [r7, #12] 8002a28: 601a str r2, [r3, #0] /* Initialise the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8002a2a: 687b ldr r3, [r7, #4] 8002a2c: 2200 movs r2, #0 8002a2e: 639a str r2, [r3, #56] ; 0x38 /* Initialize the DMA state*/ hdma->State = HAL_DMA_STATE_READY; 8002a30: 687b ldr r3, [r7, #4] 8002a32: 2201 movs r2, #1 8002a34: f883 2021 strb.w r2, [r3, #33] ; 0x21 /* Allocate lock resource and initialize it */ hdma->Lock = HAL_UNLOCKED; 8002a38: 687b ldr r3, [r7, #4] 8002a3a: 2200 movs r2, #0 8002a3c: f883 2020 strb.w r2, [r3, #32] return HAL_OK; 8002a40: 2300 movs r3, #0 } 8002a42: 4618 mov r0, r3 8002a44: 3714 adds r7, #20 8002a46: 46bd mov sp, r7 8002a48: bc80 pop {r7} 8002a4a: 4770 bx lr 8002a4c: bffdfff8 .word 0xbffdfff8 8002a50: cccccccd .word 0xcccccccd 8002a54: 40020000 .word 0x40020000 08002a58 : * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 8002a58: b580 push {r7, lr} 8002a5a: b086 sub sp, #24 8002a5c: af00 add r7, sp, #0 8002a5e: 60f8 str r0, [r7, #12] 8002a60: 60b9 str r1, [r7, #8] 8002a62: 607a str r2, [r7, #4] 8002a64: 603b str r3, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 8002a66: 2300 movs r3, #0 8002a68: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Process locked */ __HAL_LOCK(hdma); 8002a6a: 68fb ldr r3, [r7, #12] 8002a6c: f893 3020 ldrb.w r3, [r3, #32] 8002a70: 2b01 cmp r3, #1 8002a72: d101 bne.n 8002a78 8002a74: 2302 movs r3, #2 8002a76: e04a b.n 8002b0e 8002a78: 68fb ldr r3, [r7, #12] 8002a7a: 2201 movs r2, #1 8002a7c: f883 2020 strb.w r2, [r3, #32] if(HAL_DMA_STATE_READY == hdma->State) 8002a80: 68fb ldr r3, [r7, #12] 8002a82: f893 3021 ldrb.w r3, [r3, #33] ; 0x21 8002a86: 2b01 cmp r3, #1 8002a88: d13a bne.n 8002b00 { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8002a8a: 68fb ldr r3, [r7, #12] 8002a8c: 2202 movs r2, #2 8002a8e: f883 2021 strb.w r2, [r3, #33] ; 0x21 hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8002a92: 68fb ldr r3, [r7, #12] 8002a94: 2200 movs r2, #0 8002a96: 639a str r2, [r3, #56] ; 0x38 /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); 8002a98: 68fb ldr r3, [r7, #12] 8002a9a: 681b ldr r3, [r3, #0] 8002a9c: 681a ldr r2, [r3, #0] 8002a9e: 68fb ldr r3, [r7, #12] 8002aa0: 681b ldr r3, [r3, #0] 8002aa2: f022 0201 bic.w r2, r2, #1 8002aa6: 601a str r2, [r3, #0] /* Configure the source, destination address and the data length & clear flags*/ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); 8002aa8: 683b ldr r3, [r7, #0] 8002aaa: 687a ldr r2, [r7, #4] 8002aac: 68b9 ldr r1, [r7, #8] 8002aae: 68f8 ldr r0, [r7, #12] 8002ab0: f000 f9ae bl 8002e10 /* Enable the transfer complete interrupt */ /* Enable the transfer Error interrupt */ if(NULL != hdma->XferHalfCpltCallback) 8002ab4: 68fb ldr r3, [r7, #12] 8002ab6: 6adb ldr r3, [r3, #44] ; 0x2c 8002ab8: 2b00 cmp r3, #0 8002aba: d008 beq.n 8002ace { /* Enable the Half transfer complete interrupt as well */ __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8002abc: 68fb ldr r3, [r7, #12] 8002abe: 681b ldr r3, [r3, #0] 8002ac0: 681a ldr r2, [r3, #0] 8002ac2: 68fb ldr r3, [r7, #12] 8002ac4: 681b ldr r3, [r3, #0] 8002ac6: f042 020e orr.w r2, r2, #14 8002aca: 601a str r2, [r3, #0] 8002acc: e00f b.n 8002aee } else { __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 8002ace: 68fb ldr r3, [r7, #12] 8002ad0: 681b ldr r3, [r3, #0] 8002ad2: 681a ldr r2, [r3, #0] 8002ad4: 68fb ldr r3, [r7, #12] 8002ad6: 681b ldr r3, [r3, #0] 8002ad8: f022 0204 bic.w r2, r2, #4 8002adc: 601a str r2, [r3, #0] __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); 8002ade: 68fb ldr r3, [r7, #12] 8002ae0: 681b ldr r3, [r3, #0] 8002ae2: 681a ldr r2, [r3, #0] 8002ae4: 68fb ldr r3, [r7, #12] 8002ae6: 681b ldr r3, [r3, #0] 8002ae8: f042 020a orr.w r2, r2, #10 8002aec: 601a str r2, [r3, #0] } /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); 8002aee: 68fb ldr r3, [r7, #12] 8002af0: 681b ldr r3, [r3, #0] 8002af2: 681a ldr r2, [r3, #0] 8002af4: 68fb ldr r3, [r7, #12] 8002af6: 681b ldr r3, [r3, #0] 8002af8: f042 0201 orr.w r2, r2, #1 8002afc: 601a str r2, [r3, #0] 8002afe: e005 b.n 8002b0c } else { /* Process Unlocked */ __HAL_UNLOCK(hdma); 8002b00: 68fb ldr r3, [r7, #12] 8002b02: 2200 movs r2, #0 8002b04: f883 2020 strb.w r2, [r3, #32] /* Remain BUSY */ status = HAL_BUSY; 8002b08: 2302 movs r3, #2 8002b0a: 75fb strb r3, [r7, #23] } return status; 8002b0c: 7dfb ldrb r3, [r7, #23] } 8002b0e: 4618 mov r0, r3 8002b10: 3718 adds r7, #24 8002b12: 46bd mov sp, r7 8002b14: bd80 pop {r7, pc} ... 08002b18 : * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 8002b18: b580 push {r7, lr} 8002b1a: b084 sub sp, #16 8002b1c: af00 add r7, sp, #0 8002b1e: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8002b20: 2300 movs r3, #0 8002b22: 73fb strb r3, [r7, #15] if(HAL_DMA_STATE_BUSY != hdma->State) 8002b24: 687b ldr r3, [r7, #4] 8002b26: f893 3021 ldrb.w r3, [r3, #33] ; 0x21 8002b2a: 2b02 cmp r3, #2 8002b2c: d005 beq.n 8002b3a { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8002b2e: 687b ldr r3, [r7, #4] 8002b30: 2204 movs r2, #4 8002b32: 639a str r2, [r3, #56] ; 0x38 status = HAL_ERROR; 8002b34: 2301 movs r3, #1 8002b36: 73fb strb r3, [r7, #15] 8002b38: e051 b.n 8002bde } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8002b3a: 687b ldr r3, [r7, #4] 8002b3c: 681b ldr r3, [r3, #0] 8002b3e: 681a ldr r2, [r3, #0] 8002b40: 687b ldr r3, [r7, #4] 8002b42: 681b ldr r3, [r3, #0] 8002b44: f022 020e bic.w r2, r2, #14 8002b48: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 8002b4a: 687b ldr r3, [r7, #4] 8002b4c: 681b ldr r3, [r3, #0] 8002b4e: 681a ldr r2, [r3, #0] 8002b50: 687b ldr r3, [r7, #4] 8002b52: 681b ldr r3, [r3, #0] 8002b54: f022 0201 bic.w r2, r2, #1 8002b58: 601a str r2, [r3, #0] /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); 8002b5a: 687b ldr r3, [r7, #4] 8002b5c: 681b ldr r3, [r3, #0] 8002b5e: 4a22 ldr r2, [pc, #136] ; (8002be8 ) 8002b60: 4293 cmp r3, r2 8002b62: d029 beq.n 8002bb8 8002b64: 687b ldr r3, [r7, #4] 8002b66: 681b ldr r3, [r3, #0] 8002b68: 4a20 ldr r2, [pc, #128] ; (8002bec ) 8002b6a: 4293 cmp r3, r2 8002b6c: d022 beq.n 8002bb4 8002b6e: 687b ldr r3, [r7, #4] 8002b70: 681b ldr r3, [r3, #0] 8002b72: 4a1f ldr r2, [pc, #124] ; (8002bf0 ) 8002b74: 4293 cmp r3, r2 8002b76: d01a beq.n 8002bae 8002b78: 687b ldr r3, [r7, #4] 8002b7a: 681b ldr r3, [r3, #0] 8002b7c: 4a1d ldr r2, [pc, #116] ; (8002bf4 ) 8002b7e: 4293 cmp r3, r2 8002b80: d012 beq.n 8002ba8 8002b82: 687b ldr r3, [r7, #4] 8002b84: 681b ldr r3, [r3, #0] 8002b86: 4a1c ldr r2, [pc, #112] ; (8002bf8 ) 8002b88: 4293 cmp r3, r2 8002b8a: d00a beq.n 8002ba2 8002b8c: 687b ldr r3, [r7, #4] 8002b8e: 681b ldr r3, [r3, #0] 8002b90: 4a1a ldr r2, [pc, #104] ; (8002bfc ) 8002b92: 4293 cmp r3, r2 8002b94: d102 bne.n 8002b9c 8002b96: f44f 1380 mov.w r3, #1048576 ; 0x100000 8002b9a: e00e b.n 8002bba 8002b9c: f04f 7380 mov.w r3, #16777216 ; 0x1000000 8002ba0: e00b b.n 8002bba 8002ba2: f44f 3380 mov.w r3, #65536 ; 0x10000 8002ba6: e008 b.n 8002bba 8002ba8: f44f 5380 mov.w r3, #4096 ; 0x1000 8002bac: e005 b.n 8002bba 8002bae: f44f 7380 mov.w r3, #256 ; 0x100 8002bb2: e002 b.n 8002bba 8002bb4: 2310 movs r3, #16 8002bb6: e000 b.n 8002bba 8002bb8: 2301 movs r3, #1 8002bba: 4a11 ldr r2, [pc, #68] ; (8002c00 ) 8002bbc: 6053 str r3, [r2, #4] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8002bbe: 687b ldr r3, [r7, #4] 8002bc0: 2201 movs r2, #1 8002bc2: f883 2021 strb.w r2, [r3, #33] ; 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8002bc6: 687b ldr r3, [r7, #4] 8002bc8: 2200 movs r2, #0 8002bca: f883 2020 strb.w r2, [r3, #32] /* Call User Abort callback */ if(hdma->XferAbortCallback != NULL) 8002bce: 687b ldr r3, [r7, #4] 8002bd0: 6b5b ldr r3, [r3, #52] ; 0x34 8002bd2: 2b00 cmp r3, #0 8002bd4: d003 beq.n 8002bde { hdma->XferAbortCallback(hdma); 8002bd6: 687b ldr r3, [r7, #4] 8002bd8: 6b5b ldr r3, [r3, #52] ; 0x34 8002bda: 6878 ldr r0, [r7, #4] 8002bdc: 4798 blx r3 } } return status; 8002bde: 7bfb ldrb r3, [r7, #15] } 8002be0: 4618 mov r0, r3 8002be2: 3710 adds r7, #16 8002be4: 46bd mov sp, r7 8002be6: bd80 pop {r7, pc} 8002be8: 40020008 .word 0x40020008 8002bec: 4002001c .word 0x4002001c 8002bf0: 40020030 .word 0x40020030 8002bf4: 40020044 .word 0x40020044 8002bf8: 40020058 .word 0x40020058 8002bfc: 4002006c .word 0x4002006c 8002c00: 40020000 .word 0x40020000 08002c04 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { 8002c04: b580 push {r7, lr} 8002c06: b084 sub sp, #16 8002c08: af00 add r7, sp, #0 8002c0a: 6078 str r0, [r7, #4] uint32_t flag_it = hdma->DmaBaseAddress->ISR; 8002c0c: 687b ldr r3, [r7, #4] 8002c0e: 6bdb ldr r3, [r3, #60] ; 0x3c 8002c10: 681b ldr r3, [r3, #0] 8002c12: 60fb str r3, [r7, #12] uint32_t source_it = hdma->Instance->CCR; 8002c14: 687b ldr r3, [r7, #4] 8002c16: 681b ldr r3, [r3, #0] 8002c18: 681b ldr r3, [r3, #0] 8002c1a: 60bb str r3, [r7, #8] /* Half Transfer Complete Interrupt management ******************************/ if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET)) 8002c1c: 687b ldr r3, [r7, #4] 8002c1e: 6c1b ldr r3, [r3, #64] ; 0x40 8002c20: 2204 movs r2, #4 8002c22: 409a lsls r2, r3 8002c24: 68fb ldr r3, [r7, #12] 8002c26: 4013 ands r3, r2 8002c28: 2b00 cmp r3, #0 8002c2a: d04f beq.n 8002ccc 8002c2c: 68bb ldr r3, [r7, #8] 8002c2e: f003 0304 and.w r3, r3, #4 8002c32: 2b00 cmp r3, #0 8002c34: d04a beq.n 8002ccc { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 8002c36: 687b ldr r3, [r7, #4] 8002c38: 681b ldr r3, [r3, #0] 8002c3a: 681b ldr r3, [r3, #0] 8002c3c: f003 0320 and.w r3, r3, #32 8002c40: 2b00 cmp r3, #0 8002c42: d107 bne.n 8002c54 { /* Disable the half transfer interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 8002c44: 687b ldr r3, [r7, #4] 8002c46: 681b ldr r3, [r3, #0] 8002c48: 681a ldr r2, [r3, #0] 8002c4a: 687b ldr r3, [r7, #4] 8002c4c: 681b ldr r3, [r3, #0] 8002c4e: f022 0204 bic.w r2, r2, #4 8002c52: 601a str r2, [r3, #0] } /* Clear the half transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); 8002c54: 687b ldr r3, [r7, #4] 8002c56: 681b ldr r3, [r3, #0] 8002c58: 4a66 ldr r2, [pc, #408] ; (8002df4 ) 8002c5a: 4293 cmp r3, r2 8002c5c: d029 beq.n 8002cb2 8002c5e: 687b ldr r3, [r7, #4] 8002c60: 681b ldr r3, [r3, #0] 8002c62: 4a65 ldr r2, [pc, #404] ; (8002df8 ) 8002c64: 4293 cmp r3, r2 8002c66: d022 beq.n 8002cae 8002c68: 687b ldr r3, [r7, #4] 8002c6a: 681b ldr r3, [r3, #0] 8002c6c: 4a63 ldr r2, [pc, #396] ; (8002dfc ) 8002c6e: 4293 cmp r3, r2 8002c70: d01a beq.n 8002ca8 8002c72: 687b ldr r3, [r7, #4] 8002c74: 681b ldr r3, [r3, #0] 8002c76: 4a62 ldr r2, [pc, #392] ; (8002e00 ) 8002c78: 4293 cmp r3, r2 8002c7a: d012 beq.n 8002ca2 8002c7c: 687b ldr r3, [r7, #4] 8002c7e: 681b ldr r3, [r3, #0] 8002c80: 4a60 ldr r2, [pc, #384] ; (8002e04 ) 8002c82: 4293 cmp r3, r2 8002c84: d00a beq.n 8002c9c 8002c86: 687b ldr r3, [r7, #4] 8002c88: 681b ldr r3, [r3, #0] 8002c8a: 4a5f ldr r2, [pc, #380] ; (8002e08 ) 8002c8c: 4293 cmp r3, r2 8002c8e: d102 bne.n 8002c96 8002c90: f44f 0380 mov.w r3, #4194304 ; 0x400000 8002c94: e00e b.n 8002cb4 8002c96: f04f 6380 mov.w r3, #67108864 ; 0x4000000 8002c9a: e00b b.n 8002cb4 8002c9c: f44f 2380 mov.w r3, #262144 ; 0x40000 8002ca0: e008 b.n 8002cb4 8002ca2: f44f 4380 mov.w r3, #16384 ; 0x4000 8002ca6: e005 b.n 8002cb4 8002ca8: f44f 6380 mov.w r3, #1024 ; 0x400 8002cac: e002 b.n 8002cb4 8002cae: 2340 movs r3, #64 ; 0x40 8002cb0: e000 b.n 8002cb4 8002cb2: 2304 movs r3, #4 8002cb4: 4a55 ldr r2, [pc, #340] ; (8002e0c ) 8002cb6: 6053 str r3, [r2, #4] /* DMA peripheral state is not updated in Half Transfer */ /* but in Transfer Complete case */ if(hdma->XferHalfCpltCallback != NULL) 8002cb8: 687b ldr r3, [r7, #4] 8002cba: 6adb ldr r3, [r3, #44] ; 0x2c 8002cbc: 2b00 cmp r3, #0 8002cbe: f000 8094 beq.w 8002dea { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 8002cc2: 687b ldr r3, [r7, #4] 8002cc4: 6adb ldr r3, [r3, #44] ; 0x2c 8002cc6: 6878 ldr r0, [r7, #4] 8002cc8: 4798 blx r3 if(hdma->XferHalfCpltCallback != NULL) 8002cca: e08e b.n 8002dea } } /* Transfer Complete Interrupt management ***********************************/ else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET)) 8002ccc: 687b ldr r3, [r7, #4] 8002cce: 6c1b ldr r3, [r3, #64] ; 0x40 8002cd0: 2202 movs r2, #2 8002cd2: 409a lsls r2, r3 8002cd4: 68fb ldr r3, [r7, #12] 8002cd6: 4013 ands r3, r2 8002cd8: 2b00 cmp r3, #0 8002cda: d056 beq.n 8002d8a 8002cdc: 68bb ldr r3, [r7, #8] 8002cde: f003 0302 and.w r3, r3, #2 8002ce2: 2b00 cmp r3, #0 8002ce4: d051 beq.n 8002d8a { if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 8002ce6: 687b ldr r3, [r7, #4] 8002ce8: 681b ldr r3, [r3, #0] 8002cea: 681b ldr r3, [r3, #0] 8002cec: f003 0320 and.w r3, r3, #32 8002cf0: 2b00 cmp r3, #0 8002cf2: d10b bne.n 8002d0c { /* Disable the transfer complete and error interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); 8002cf4: 687b ldr r3, [r7, #4] 8002cf6: 681b ldr r3, [r3, #0] 8002cf8: 681a ldr r2, [r3, #0] 8002cfa: 687b ldr r3, [r7, #4] 8002cfc: 681b ldr r3, [r3, #0] 8002cfe: f022 020a bic.w r2, r2, #10 8002d02: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8002d04: 687b ldr r3, [r7, #4] 8002d06: 2201 movs r2, #1 8002d08: f883 2021 strb.w r2, [r3, #33] ; 0x21 } /* Clear the transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); 8002d0c: 687b ldr r3, [r7, #4] 8002d0e: 681b ldr r3, [r3, #0] 8002d10: 4a38 ldr r2, [pc, #224] ; (8002df4 ) 8002d12: 4293 cmp r3, r2 8002d14: d029 beq.n 8002d6a 8002d16: 687b ldr r3, [r7, #4] 8002d18: 681b ldr r3, [r3, #0] 8002d1a: 4a37 ldr r2, [pc, #220] ; (8002df8 ) 8002d1c: 4293 cmp r3, r2 8002d1e: d022 beq.n 8002d66 8002d20: 687b ldr r3, [r7, #4] 8002d22: 681b ldr r3, [r3, #0] 8002d24: 4a35 ldr r2, [pc, #212] ; (8002dfc ) 8002d26: 4293 cmp r3, r2 8002d28: d01a beq.n 8002d60 8002d2a: 687b ldr r3, [r7, #4] 8002d2c: 681b ldr r3, [r3, #0] 8002d2e: 4a34 ldr r2, [pc, #208] ; (8002e00 ) 8002d30: 4293 cmp r3, r2 8002d32: d012 beq.n 8002d5a 8002d34: 687b ldr r3, [r7, #4] 8002d36: 681b ldr r3, [r3, #0] 8002d38: 4a32 ldr r2, [pc, #200] ; (8002e04 ) 8002d3a: 4293 cmp r3, r2 8002d3c: d00a beq.n 8002d54 8002d3e: 687b ldr r3, [r7, #4] 8002d40: 681b ldr r3, [r3, #0] 8002d42: 4a31 ldr r2, [pc, #196] ; (8002e08 ) 8002d44: 4293 cmp r3, r2 8002d46: d102 bne.n 8002d4e 8002d48: f44f 1300 mov.w r3, #2097152 ; 0x200000 8002d4c: e00e b.n 8002d6c 8002d4e: f04f 7300 mov.w r3, #33554432 ; 0x2000000 8002d52: e00b b.n 8002d6c 8002d54: f44f 3300 mov.w r3, #131072 ; 0x20000 8002d58: e008 b.n 8002d6c 8002d5a: f44f 5300 mov.w r3, #8192 ; 0x2000 8002d5e: e005 b.n 8002d6c 8002d60: f44f 7300 mov.w r3, #512 ; 0x200 8002d64: e002 b.n 8002d6c 8002d66: 2320 movs r3, #32 8002d68: e000 b.n 8002d6c 8002d6a: 2302 movs r3, #2 8002d6c: 4a27 ldr r2, [pc, #156] ; (8002e0c ) 8002d6e: 6053 str r3, [r2, #4] /* Process Unlocked */ __HAL_UNLOCK(hdma); 8002d70: 687b ldr r3, [r7, #4] 8002d72: 2200 movs r2, #0 8002d74: f883 2020 strb.w r2, [r3, #32] if(hdma->XferCpltCallback != NULL) 8002d78: 687b ldr r3, [r7, #4] 8002d7a: 6a9b ldr r3, [r3, #40] ; 0x28 8002d7c: 2b00 cmp r3, #0 8002d7e: d034 beq.n 8002dea { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 8002d80: 687b ldr r3, [r7, #4] 8002d82: 6a9b ldr r3, [r3, #40] ; 0x28 8002d84: 6878 ldr r0, [r7, #4] 8002d86: 4798 blx r3 if(hdma->XferCpltCallback != NULL) 8002d88: e02f b.n 8002dea } } /* Transfer Error Interrupt management **************************************/ else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE))) 8002d8a: 687b ldr r3, [r7, #4] 8002d8c: 6c1b ldr r3, [r3, #64] ; 0x40 8002d8e: 2208 movs r2, #8 8002d90: 409a lsls r2, r3 8002d92: 68fb ldr r3, [r7, #12] 8002d94: 4013 ands r3, r2 8002d96: 2b00 cmp r3, #0 8002d98: d028 beq.n 8002dec 8002d9a: 68bb ldr r3, [r7, #8] 8002d9c: f003 0308 and.w r3, r3, #8 8002da0: 2b00 cmp r3, #0 8002da2: d023 beq.n 8002dec { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ /* Disable ALL DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8002da4: 687b ldr r3, [r7, #4] 8002da6: 681b ldr r3, [r3, #0] 8002da8: 681a ldr r2, [r3, #0] 8002daa: 687b ldr r3, [r7, #4] 8002dac: 681b ldr r3, [r3, #0] 8002dae: f022 020e bic.w r2, r2, #14 8002db2: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); 8002db4: 687b ldr r3, [r7, #4] 8002db6: 6c1a ldr r2, [r3, #64] ; 0x40 8002db8: 687b ldr r3, [r7, #4] 8002dba: 6bdb ldr r3, [r3, #60] ; 0x3c 8002dbc: 2101 movs r1, #1 8002dbe: fa01 f202 lsl.w r2, r1, r2 8002dc2: 605a str r2, [r3, #4] /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; 8002dc4: 687b ldr r3, [r7, #4] 8002dc6: 2201 movs r2, #1 8002dc8: 639a str r2, [r3, #56] ; 0x38 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8002dca: 687b ldr r3, [r7, #4] 8002dcc: 2201 movs r2, #1 8002dce: f883 2021 strb.w r2, [r3, #33] ; 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8002dd2: 687b ldr r3, [r7, #4] 8002dd4: 2200 movs r2, #0 8002dd6: f883 2020 strb.w r2, [r3, #32] if (hdma->XferErrorCallback != NULL) 8002dda: 687b ldr r3, [r7, #4] 8002ddc: 6b1b ldr r3, [r3, #48] ; 0x30 8002dde: 2b00 cmp r3, #0 8002de0: d004 beq.n 8002dec { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 8002de2: 687b ldr r3, [r7, #4] 8002de4: 6b1b ldr r3, [r3, #48] ; 0x30 8002de6: 6878 ldr r0, [r7, #4] 8002de8: 4798 blx r3 } } return; 8002dea: bf00 nop 8002dec: bf00 nop } 8002dee: 3710 adds r7, #16 8002df0: 46bd mov sp, r7 8002df2: bd80 pop {r7, pc} 8002df4: 40020008 .word 0x40020008 8002df8: 4002001c .word 0x4002001c 8002dfc: 40020030 .word 0x40020030 8002e00: 40020044 .word 0x40020044 8002e04: 40020058 .word 0x40020058 8002e08: 4002006c .word 0x4002006c 8002e0c: 40020000 .word 0x40020000 08002e10 : * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval HAL status */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 8002e10: b480 push {r7} 8002e12: b085 sub sp, #20 8002e14: af00 add r7, sp, #0 8002e16: 60f8 str r0, [r7, #12] 8002e18: 60b9 str r1, [r7, #8] 8002e1a: 607a str r2, [r7, #4] 8002e1c: 603b str r3, [r7, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); 8002e1e: 68fb ldr r3, [r7, #12] 8002e20: 6c1a ldr r2, [r3, #64] ; 0x40 8002e22: 68fb ldr r3, [r7, #12] 8002e24: 6bdb ldr r3, [r3, #60] ; 0x3c 8002e26: 2101 movs r1, #1 8002e28: fa01 f202 lsl.w r2, r1, r2 8002e2c: 605a str r2, [r3, #4] /* Configure DMA Channel data length */ hdma->Instance->CNDTR = DataLength; 8002e2e: 68fb ldr r3, [r7, #12] 8002e30: 681b ldr r3, [r3, #0] 8002e32: 683a ldr r2, [r7, #0] 8002e34: 605a str r2, [r3, #4] /* Memory to Peripheral */ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 8002e36: 68fb ldr r3, [r7, #12] 8002e38: 685b ldr r3, [r3, #4] 8002e3a: 2b10 cmp r3, #16 8002e3c: d108 bne.n 8002e50 { /* Configure DMA Channel destination address */ hdma->Instance->CPAR = DstAddress; 8002e3e: 68fb ldr r3, [r7, #12] 8002e40: 681b ldr r3, [r3, #0] 8002e42: 687a ldr r2, [r7, #4] 8002e44: 609a str r2, [r3, #8] /* Configure DMA Channel source address */ hdma->Instance->CMAR = SrcAddress; 8002e46: 68fb ldr r3, [r7, #12] 8002e48: 681b ldr r3, [r3, #0] 8002e4a: 68ba ldr r2, [r7, #8] 8002e4c: 60da str r2, [r3, #12] hdma->Instance->CPAR = SrcAddress; /* Configure DMA Channel destination address */ hdma->Instance->CMAR = DstAddress; } } 8002e4e: e007 b.n 8002e60 hdma->Instance->CPAR = SrcAddress; 8002e50: 68fb ldr r3, [r7, #12] 8002e52: 681b ldr r3, [r3, #0] 8002e54: 68ba ldr r2, [r7, #8] 8002e56: 609a str r2, [r3, #8] hdma->Instance->CMAR = DstAddress; 8002e58: 68fb ldr r3, [r7, #12] 8002e5a: 681b ldr r3, [r3, #0] 8002e5c: 687a ldr r2, [r7, #4] 8002e5e: 60da str r2, [r3, #12] } 8002e60: bf00 nop 8002e62: 3714 adds r7, #20 8002e64: 46bd mov sp, r7 8002e66: bc80 pop {r7} 8002e68: 4770 bx lr ... 08002e6c : * @param Data: Specifies the data to be programmed * * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) { 8002e6c: b5f0 push {r4, r5, r6, r7, lr} 8002e6e: b087 sub sp, #28 8002e70: af00 add r7, sp, #0 8002e72: 60f8 str r0, [r7, #12] 8002e74: 60b9 str r1, [r7, #8] 8002e76: e9c7 2300 strd r2, r3, [r7] HAL_StatusTypeDef status = HAL_ERROR; 8002e7a: 2301 movs r3, #1 8002e7c: 75fb strb r3, [r7, #23] uint8_t index = 0; 8002e7e: 2300 movs r3, #0 8002e80: 75bb strb r3, [r7, #22] uint8_t nbiterations = 0; 8002e82: 2300 movs r3, #0 8002e84: 757b strb r3, [r7, #21] /* Process Locked */ __HAL_LOCK(&pFlash); 8002e86: 4b2f ldr r3, [pc, #188] ; (8002f44 ) 8002e88: 7e1b ldrb r3, [r3, #24] 8002e8a: 2b01 cmp r3, #1 8002e8c: d101 bne.n 8002e92 8002e8e: 2302 movs r3, #2 8002e90: e054 b.n 8002f3c 8002e92: 4b2c ldr r3, [pc, #176] ; (8002f44 ) 8002e94: 2201 movs r2, #1 8002e96: 761a strb r2, [r3, #24] #if defined(FLASH_BANK2_END) if(Address <= FLASH_BANK1_END) { #endif /* FLASH_BANK2_END */ /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); 8002e98: f24c 3050 movw r0, #50000 ; 0xc350 8002e9c: f000 f8a8 bl 8002ff0 8002ea0: 4603 mov r3, r0 8002ea2: 75fb strb r3, [r7, #23] /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperationBank2(FLASH_TIMEOUT_VALUE); } #endif /* FLASH_BANK2_END */ if(status == HAL_OK) 8002ea4: 7dfb ldrb r3, [r7, #23] 8002ea6: 2b00 cmp r3, #0 8002ea8: d144 bne.n 8002f34 { if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) 8002eaa: 68fb ldr r3, [r7, #12] 8002eac: 2b01 cmp r3, #1 8002eae: d102 bne.n 8002eb6 { /* Program halfword (16-bit) at a specified address. */ nbiterations = 1U; 8002eb0: 2301 movs r3, #1 8002eb2: 757b strb r3, [r7, #21] 8002eb4: e007 b.n 8002ec6 } else if(TypeProgram == FLASH_TYPEPROGRAM_WORD) 8002eb6: 68fb ldr r3, [r7, #12] 8002eb8: 2b02 cmp r3, #2 8002eba: d102 bne.n 8002ec2 { /* Program word (32-bit = 2*16-bit) at a specified address. */ nbiterations = 2U; 8002ebc: 2302 movs r3, #2 8002ebe: 757b strb r3, [r7, #21] 8002ec0: e001 b.n 8002ec6 } else { /* Program double word (64-bit = 4*16-bit) at a specified address. */ nbiterations = 4U; 8002ec2: 2304 movs r3, #4 8002ec4: 757b strb r3, [r7, #21] } for (index = 0U; index < nbiterations; index++) 8002ec6: 2300 movs r3, #0 8002ec8: 75bb strb r3, [r7, #22] 8002eca: e02d b.n 8002f28 { FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index))); 8002ecc: 7dbb ldrb r3, [r7, #22] 8002ece: 005a lsls r2, r3, #1 8002ed0: 68bb ldr r3, [r7, #8] 8002ed2: eb02 0c03 add.w ip, r2, r3 8002ed6: 7dbb ldrb r3, [r7, #22] 8002ed8: 0119 lsls r1, r3, #4 8002eda: e9d7 2300 ldrd r2, r3, [r7] 8002ede: f1c1 0620 rsb r6, r1, #32 8002ee2: f1a1 0020 sub.w r0, r1, #32 8002ee6: fa22 f401 lsr.w r4, r2, r1 8002eea: fa03 f606 lsl.w r6, r3, r6 8002eee: 4334 orrs r4, r6 8002ef0: fa23 f000 lsr.w r0, r3, r0 8002ef4: 4304 orrs r4, r0 8002ef6: fa23 f501 lsr.w r5, r3, r1 8002efa: b2a3 uxth r3, r4 8002efc: 4619 mov r1, r3 8002efe: 4660 mov r0, ip 8002f00: f000 f85a bl 8002fb8 #if defined(FLASH_BANK2_END) if(Address <= FLASH_BANK1_END) { #endif /* FLASH_BANK2_END */ /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); 8002f04: f24c 3050 movw r0, #50000 ; 0xc350 8002f08: f000 f872 bl 8002ff0 8002f0c: 4603 mov r3, r0 8002f0e: 75fb strb r3, [r7, #23] /* If the program operation is completed, disable the PG Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_PG); 8002f10: 4b0d ldr r3, [pc, #52] ; (8002f48 ) 8002f12: 691b ldr r3, [r3, #16] 8002f14: 4a0c ldr r2, [pc, #48] ; (8002f48 ) 8002f16: f023 0301 bic.w r3, r3, #1 8002f1a: 6113 str r3, [r2, #16] /* If the program operation is completed, disable the PG Bit */ CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG); } #endif /* FLASH_BANK2_END */ /* In case of error, stop programation procedure */ if (status != HAL_OK) 8002f1c: 7dfb ldrb r3, [r7, #23] 8002f1e: 2b00 cmp r3, #0 8002f20: d107 bne.n 8002f32 for (index = 0U; index < nbiterations; index++) 8002f22: 7dbb ldrb r3, [r7, #22] 8002f24: 3301 adds r3, #1 8002f26: 75bb strb r3, [r7, #22] 8002f28: 7dba ldrb r2, [r7, #22] 8002f2a: 7d7b ldrb r3, [r7, #21] 8002f2c: 429a cmp r2, r3 8002f2e: d3cd bcc.n 8002ecc 8002f30: e000 b.n 8002f34 { break; 8002f32: bf00 nop } } } /* Process Unlocked */ __HAL_UNLOCK(&pFlash); 8002f34: 4b03 ldr r3, [pc, #12] ; (8002f44 ) 8002f36: 2200 movs r2, #0 8002f38: 761a strb r2, [r3, #24] return status; 8002f3a: 7dfb ldrb r3, [r7, #23] } 8002f3c: 4618 mov r0, r3 8002f3e: 371c adds r7, #28 8002f40: 46bd mov sp, r7 8002f42: bdf0 pop {r4, r5, r6, r7, pc} 8002f44: 200008f0 .word 0x200008f0 8002f48: 40022000 .word 0x40022000 08002f4c : /** * @brief Unlock the FLASH control register access * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_Unlock(void) { 8002f4c: b480 push {r7} 8002f4e: b083 sub sp, #12 8002f50: af00 add r7, sp, #0 HAL_StatusTypeDef status = HAL_OK; 8002f52: 2300 movs r3, #0 8002f54: 71fb strb r3, [r7, #7] if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) 8002f56: 4b0d ldr r3, [pc, #52] ; (8002f8c ) 8002f58: 691b ldr r3, [r3, #16] 8002f5a: f003 0380 and.w r3, r3, #128 ; 0x80 8002f5e: 2b00 cmp r3, #0 8002f60: d00d beq.n 8002f7e { /* Authorize the FLASH Registers access */ WRITE_REG(FLASH->KEYR, FLASH_KEY1); 8002f62: 4b0a ldr r3, [pc, #40] ; (8002f8c ) 8002f64: 4a0a ldr r2, [pc, #40] ; (8002f90 ) 8002f66: 605a str r2, [r3, #4] WRITE_REG(FLASH->KEYR, FLASH_KEY2); 8002f68: 4b08 ldr r3, [pc, #32] ; (8002f8c ) 8002f6a: 4a0a ldr r2, [pc, #40] ; (8002f94 ) 8002f6c: 605a str r2, [r3, #4] /* Verify Flash is unlocked */ if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) 8002f6e: 4b07 ldr r3, [pc, #28] ; (8002f8c ) 8002f70: 691b ldr r3, [r3, #16] 8002f72: f003 0380 and.w r3, r3, #128 ; 0x80 8002f76: 2b00 cmp r3, #0 8002f78: d001 beq.n 8002f7e { status = HAL_ERROR; 8002f7a: 2301 movs r3, #1 8002f7c: 71fb strb r3, [r7, #7] status = HAL_ERROR; } } #endif /* FLASH_BANK2_END */ return status; 8002f7e: 79fb ldrb r3, [r7, #7] } 8002f80: 4618 mov r0, r3 8002f82: 370c adds r7, #12 8002f84: 46bd mov sp, r7 8002f86: bc80 pop {r7} 8002f88: 4770 bx lr 8002f8a: bf00 nop 8002f8c: 40022000 .word 0x40022000 8002f90: 45670123 .word 0x45670123 8002f94: cdef89ab .word 0xcdef89ab 08002f98 : /** * @brief Locks the FLASH control register access * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_Lock(void) { 8002f98: b480 push {r7} 8002f9a: af00 add r7, sp, #0 /* Set the LOCK Bit to lock the FLASH Registers access */ SET_BIT(FLASH->CR, FLASH_CR_LOCK); 8002f9c: 4b05 ldr r3, [pc, #20] ; (8002fb4 ) 8002f9e: 691b ldr r3, [r3, #16] 8002fa0: 4a04 ldr r2, [pc, #16] ; (8002fb4 ) 8002fa2: f043 0380 orr.w r3, r3, #128 ; 0x80 8002fa6: 6113 str r3, [r2, #16] #if defined(FLASH_BANK2_END) /* Set the LOCK Bit to lock the FLASH BANK2 Registers access */ SET_BIT(FLASH->CR2, FLASH_CR2_LOCK); #endif /* FLASH_BANK2_END */ return HAL_OK; 8002fa8: 2300 movs r3, #0 } 8002faa: 4618 mov r0, r3 8002fac: 46bd mov sp, r7 8002fae: bc80 pop {r7} 8002fb0: 4770 bx lr 8002fb2: bf00 nop 8002fb4: 40022000 .word 0x40022000 08002fb8 : * @param Address specify the address to be programmed. * @param Data specify the data to be programmed. * @retval None */ static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) { 8002fb8: b480 push {r7} 8002fba: b083 sub sp, #12 8002fbc: af00 add r7, sp, #0 8002fbe: 6078 str r0, [r7, #4] 8002fc0: 460b mov r3, r1 8002fc2: 807b strh r3, [r7, #2] /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; 8002fc4: 4b08 ldr r3, [pc, #32] ; (8002fe8 ) 8002fc6: 2200 movs r2, #0 8002fc8: 61da str r2, [r3, #28] #if defined(FLASH_BANK2_END) if(Address <= FLASH_BANK1_END) { #endif /* FLASH_BANK2_END */ /* Proceed to program the new data */ SET_BIT(FLASH->CR, FLASH_CR_PG); 8002fca: 4b08 ldr r3, [pc, #32] ; (8002fec ) 8002fcc: 691b ldr r3, [r3, #16] 8002fce: 4a07 ldr r2, [pc, #28] ; (8002fec ) 8002fd0: f043 0301 orr.w r3, r3, #1 8002fd4: 6113 str r3, [r2, #16] SET_BIT(FLASH->CR2, FLASH_CR2_PG); } #endif /* FLASH_BANK2_END */ /* Write data in the address */ *(__IO uint16_t*)Address = Data; 8002fd6: 687b ldr r3, [r7, #4] 8002fd8: 887a ldrh r2, [r7, #2] 8002fda: 801a strh r2, [r3, #0] } 8002fdc: bf00 nop 8002fde: 370c adds r7, #12 8002fe0: 46bd mov sp, r7 8002fe2: bc80 pop {r7} 8002fe4: 4770 bx lr 8002fe6: bf00 nop 8002fe8: 200008f0 .word 0x200008f0 8002fec: 40022000 .word 0x40022000 08002ff0 : * @brief Wait for a FLASH operation to complete. * @param Timeout maximum flash operation timeout * @retval HAL Status */ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) { 8002ff0: b580 push {r7, lr} 8002ff2: b084 sub sp, #16 8002ff4: af00 add r7, sp, #0 8002ff6: 6078 str r0, [r7, #4] /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. Even if the FLASH operation fails, the BUSY flag will be reset and an error flag will be set */ uint32_t tickstart = HAL_GetTick(); 8002ff8: f7fe fee8 bl 8001dcc 8002ffc: 60f8 str r0, [r7, #12] while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) 8002ffe: e010 b.n 8003022 { if (Timeout != HAL_MAX_DELAY) 8003000: 687b ldr r3, [r7, #4] 8003002: f1b3 3fff cmp.w r3, #4294967295 8003006: d00c beq.n 8003022 { if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) 8003008: 687b ldr r3, [r7, #4] 800300a: 2b00 cmp r3, #0 800300c: d007 beq.n 800301e 800300e: f7fe fedd bl 8001dcc 8003012: 4602 mov r2, r0 8003014: 68fb ldr r3, [r7, #12] 8003016: 1ad3 subs r3, r2, r3 8003018: 687a ldr r2, [r7, #4] 800301a: 429a cmp r2, r3 800301c: d201 bcs.n 8003022 { return HAL_TIMEOUT; 800301e: 2303 movs r3, #3 8003020: e025 b.n 800306e while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) 8003022: 4b15 ldr r3, [pc, #84] ; (8003078 ) 8003024: 68db ldr r3, [r3, #12] 8003026: f003 0301 and.w r3, r3, #1 800302a: 2b00 cmp r3, #0 800302c: d1e8 bne.n 8003000 } } } /* Check FLASH End of Operation flag */ if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) 800302e: 4b12 ldr r3, [pc, #72] ; (8003078 ) 8003030: 68db ldr r3, [r3, #12] 8003032: f003 0320 and.w r3, r3, #32 8003036: 2b00 cmp r3, #0 8003038: d002 beq.n 8003040 { /* Clear FLASH End of Operation pending bit */ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); 800303a: 4b0f ldr r3, [pc, #60] ; (8003078 ) 800303c: 2220 movs r2, #32 800303e: 60da str r2, [r3, #12] } if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || 8003040: 4b0d ldr r3, [pc, #52] ; (8003078 ) 8003042: 68db ldr r3, [r3, #12] 8003044: f003 0310 and.w r3, r3, #16 8003048: 2b00 cmp r3, #0 800304a: d10b bne.n 8003064 __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || 800304c: 4b0a ldr r3, [pc, #40] ; (8003078 ) 800304e: 69db ldr r3, [r3, #28] 8003050: f003 0301 and.w r3, r3, #1 if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || 8003054: 2b00 cmp r3, #0 8003056: d105 bne.n 8003064 __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) 8003058: 4b07 ldr r3, [pc, #28] ; (8003078 ) 800305a: 68db ldr r3, [r3, #12] 800305c: f003 0304 and.w r3, r3, #4 __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || 8003060: 2b00 cmp r3, #0 8003062: d003 beq.n 800306c { /*Save the error code*/ FLASH_SetErrorCode(); 8003064: f000 f80a bl 800307c return HAL_ERROR; 8003068: 2301 movs r3, #1 800306a: e000 b.n 800306e } /* There is no error flag set */ return HAL_OK; 800306c: 2300 movs r3, #0 } 800306e: 4618 mov r0, r3 8003070: 3710 adds r7, #16 8003072: 46bd mov sp, r7 8003074: bd80 pop {r7, pc} 8003076: bf00 nop 8003078: 40022000 .word 0x40022000 0800307c : /** * @brief Set the specific FLASH error flag. * @retval None */ static void FLASH_SetErrorCode(void) { 800307c: b480 push {r7} 800307e: b083 sub sp, #12 8003080: af00 add r7, sp, #0 uint32_t flags = 0U; 8003082: 2300 movs r3, #0 8003084: 607b str r3, [r7, #4] #if defined(FLASH_BANK2_END) if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2)) #else if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) 8003086: 4b23 ldr r3, [pc, #140] ; (8003114 ) 8003088: 68db ldr r3, [r3, #12] 800308a: f003 0310 and.w r3, r3, #16 800308e: 2b00 cmp r3, #0 8003090: d009 beq.n 80030a6 #endif /* FLASH_BANK2_END */ { pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; 8003092: 4b21 ldr r3, [pc, #132] ; (8003118 ) 8003094: 69db ldr r3, [r3, #28] 8003096: f043 0302 orr.w r3, r3, #2 800309a: 4a1f ldr r2, [pc, #124] ; (8003118 ) 800309c: 61d3 str r3, [r2, #28] #if defined(FLASH_BANK2_END) flags |= FLASH_FLAG_WRPERR | FLASH_FLAG_WRPERR_BANK2; #else flags |= FLASH_FLAG_WRPERR; 800309e: 687b ldr r3, [r7, #4] 80030a0: f043 0310 orr.w r3, r3, #16 80030a4: 607b str r3, [r7, #4] #endif /* FLASH_BANK2_END */ } #if defined(FLASH_BANK2_END) if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2)) #else if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) 80030a6: 4b1b ldr r3, [pc, #108] ; (8003114 ) 80030a8: 68db ldr r3, [r3, #12] 80030aa: f003 0304 and.w r3, r3, #4 80030ae: 2b00 cmp r3, #0 80030b0: d009 beq.n 80030c6 #endif /* FLASH_BANK2_END */ { pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG; 80030b2: 4b19 ldr r3, [pc, #100] ; (8003118 ) 80030b4: 69db ldr r3, [r3, #28] 80030b6: f043 0301 orr.w r3, r3, #1 80030ba: 4a17 ldr r2, [pc, #92] ; (8003118 ) 80030bc: 61d3 str r3, [r2, #28] #if defined(FLASH_BANK2_END) flags |= FLASH_FLAG_PGERR | FLASH_FLAG_PGERR_BANK2; #else flags |= FLASH_FLAG_PGERR; 80030be: 687b ldr r3, [r7, #4] 80030c0: f043 0304 orr.w r3, r3, #4 80030c4: 607b str r3, [r7, #4] #endif /* FLASH_BANK2_END */ } if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) 80030c6: 4b13 ldr r3, [pc, #76] ; (8003114 ) 80030c8: 69db ldr r3, [r3, #28] 80030ca: f003 0301 and.w r3, r3, #1 80030ce: 2b00 cmp r3, #0 80030d0: d00b beq.n 80030ea { pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV; 80030d2: 4b11 ldr r3, [pc, #68] ; (8003118 ) 80030d4: 69db ldr r3, [r3, #28] 80030d6: f043 0304 orr.w r3, r3, #4 80030da: 4a0f ldr r2, [pc, #60] ; (8003118 ) 80030dc: 61d3 str r3, [r2, #28] __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR); 80030de: 4b0d ldr r3, [pc, #52] ; (8003114 ) 80030e0: 69db ldr r3, [r3, #28] 80030e2: 4a0c ldr r2, [pc, #48] ; (8003114 ) 80030e4: f023 0301 bic.w r3, r3, #1 80030e8: 61d3 str r3, [r2, #28] } /* Clear FLASH error pending bits */ __HAL_FLASH_CLEAR_FLAG(flags); 80030ea: 687b ldr r3, [r7, #4] 80030ec: f240 1201 movw r2, #257 ; 0x101 80030f0: 4293 cmp r3, r2 80030f2: d106 bne.n 8003102 80030f4: 4b07 ldr r3, [pc, #28] ; (8003114 ) 80030f6: 69db ldr r3, [r3, #28] 80030f8: 4a06 ldr r2, [pc, #24] ; (8003114 ) 80030fa: f023 0301 bic.w r3, r3, #1 80030fe: 61d3 str r3, [r2, #28] } 8003100: e002 b.n 8003108 __HAL_FLASH_CLEAR_FLAG(flags); 8003102: 4a04 ldr r2, [pc, #16] ; (8003114 ) 8003104: 687b ldr r3, [r7, #4] 8003106: 60d3 str r3, [r2, #12] } 8003108: bf00 nop 800310a: 370c adds r7, #12 800310c: 46bd mov sp, r7 800310e: bc80 pop {r7} 8003110: 4770 bx lr 8003112: bf00 nop 8003114: 40022000 .word 0x40022000 8003118: 200008f0 .word 0x200008f0 0800311c : * (0xFFFFFFFF means that all the pages have been correctly erased) * * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) { 800311c: b580 push {r7, lr} 800311e: b084 sub sp, #16 8003120: af00 add r7, sp, #0 8003122: 6078 str r0, [r7, #4] 8003124: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_ERROR; 8003126: 2301 movs r3, #1 8003128: 73fb strb r3, [r7, #15] uint32_t address = 0U; 800312a: 2300 movs r3, #0 800312c: 60bb str r3, [r7, #8] /* Process Locked */ __HAL_LOCK(&pFlash); 800312e: 4b2f ldr r3, [pc, #188] ; (80031ec ) 8003130: 7e1b ldrb r3, [r3, #24] 8003132: 2b01 cmp r3, #1 8003134: d101 bne.n 800313a 8003136: 2302 movs r3, #2 8003138: e053 b.n 80031e2 800313a: 4b2c ldr r3, [pc, #176] ; (80031ec ) 800313c: 2201 movs r2, #1 800313e: 761a strb r2, [r3, #24] /* Check the parameters */ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) 8003140: 687b ldr r3, [r7, #4] 8003142: 681b ldr r3, [r3, #0] 8003144: 2b02 cmp r3, #2 8003146: d116 bne.n 8003176 else #endif /* FLASH_BANK2_END */ { /* Mass Erase requested for Bank1 */ /* Wait for last operation to be completed */ if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) 8003148: f24c 3050 movw r0, #50000 ; 0xc350 800314c: f7ff ff50 bl 8002ff0 8003150: 4603 mov r3, r0 8003152: 2b00 cmp r3, #0 8003154: d141 bne.n 80031da { /*Mass erase to be done*/ FLASH_MassErase(FLASH_BANK_1); 8003156: 2001 movs r0, #1 8003158: f000 f84c bl 80031f4 /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); 800315c: f24c 3050 movw r0, #50000 ; 0xc350 8003160: f7ff ff46 bl 8002ff0 8003164: 4603 mov r3, r0 8003166: 73fb strb r3, [r7, #15] /* If the erase operation is completed, disable the MER Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_MER); 8003168: 4b21 ldr r3, [pc, #132] ; (80031f0 ) 800316a: 691b ldr r3, [r3, #16] 800316c: 4a20 ldr r2, [pc, #128] ; (80031f0 ) 800316e: f023 0304 bic.w r3, r3, #4 8003172: 6113 str r3, [r2, #16] 8003174: e031 b.n 80031da else #endif /* FLASH_BANK2_END */ { /* Page Erase requested on address located on bank1 */ /* Wait for last operation to be completed */ if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) 8003176: f24c 3050 movw r0, #50000 ; 0xc350 800317a: f7ff ff39 bl 8002ff0 800317e: 4603 mov r3, r0 8003180: 2b00 cmp r3, #0 8003182: d12a bne.n 80031da { /*Initialization of PageError variable*/ *PageError = 0xFFFFFFFFU; 8003184: 683b ldr r3, [r7, #0] 8003186: f04f 32ff mov.w r2, #4294967295 800318a: 601a str r2, [r3, #0] /* Erase page by page to be done*/ for(address = pEraseInit->PageAddress; 800318c: 687b ldr r3, [r7, #4] 800318e: 689b ldr r3, [r3, #8] 8003190: 60bb str r3, [r7, #8] 8003192: e019 b.n 80031c8 address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress); address += FLASH_PAGE_SIZE) { FLASH_PageErase(address); 8003194: 68b8 ldr r0, [r7, #8] 8003196: f000 f849 bl 800322c /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); 800319a: f24c 3050 movw r0, #50000 ; 0xc350 800319e: f7ff ff27 bl 8002ff0 80031a2: 4603 mov r3, r0 80031a4: 73fb strb r3, [r7, #15] /* If the erase operation is completed, disable the PER Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_PER); 80031a6: 4b12 ldr r3, [pc, #72] ; (80031f0 ) 80031a8: 691b ldr r3, [r3, #16] 80031aa: 4a11 ldr r2, [pc, #68] ; (80031f0 ) 80031ac: f023 0302 bic.w r3, r3, #2 80031b0: 6113 str r3, [r2, #16] if (status != HAL_OK) 80031b2: 7bfb ldrb r3, [r7, #15] 80031b4: 2b00 cmp r3, #0 80031b6: d003 beq.n 80031c0 { /* In case of error, stop erase procedure and return the faulty address */ *PageError = address; 80031b8: 683b ldr r3, [r7, #0] 80031ba: 68ba ldr r2, [r7, #8] 80031bc: 601a str r2, [r3, #0] break; 80031be: e00c b.n 80031da address += FLASH_PAGE_SIZE) 80031c0: 68bb ldr r3, [r7, #8] 80031c2: f503 6380 add.w r3, r3, #1024 ; 0x400 80031c6: 60bb str r3, [r7, #8] address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress); 80031c8: 687b ldr r3, [r7, #4] 80031ca: 68db ldr r3, [r3, #12] 80031cc: 029a lsls r2, r3, #10 80031ce: 687b ldr r3, [r7, #4] 80031d0: 689b ldr r3, [r3, #8] 80031d2: 4413 add r3, r2 for(address = pEraseInit->PageAddress; 80031d4: 68ba ldr r2, [r7, #8] 80031d6: 429a cmp r2, r3 80031d8: d3dc bcc.n 8003194 } } } /* Process Unlocked */ __HAL_UNLOCK(&pFlash); 80031da: 4b04 ldr r3, [pc, #16] ; (80031ec ) 80031dc: 2200 movs r2, #0 80031de: 761a strb r2, [r3, #24] return status; 80031e0: 7bfb ldrb r3, [r7, #15] } 80031e2: 4618 mov r0, r3 80031e4: 3710 adds r7, #16 80031e6: 46bd mov sp, r7 80031e8: bd80 pop {r7, pc} 80031ea: bf00 nop 80031ec: 200008f0 .word 0x200008f0 80031f0: 40022000 .word 0x40022000 080031f4 : @endif * * @retval None */ static void FLASH_MassErase(uint32_t Banks) { 80031f4: b480 push {r7} 80031f6: b083 sub sp, #12 80031f8: af00 add r7, sp, #0 80031fa: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_FLASH_BANK(Banks)); /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; 80031fc: 4b09 ldr r3, [pc, #36] ; (8003224 ) 80031fe: 2200 movs r2, #0 8003200: 61da str r2, [r3, #28] #if !defined(FLASH_BANK2_END) /* Prevent unused argument(s) compilation warning */ UNUSED(Banks); #endif /* FLASH_BANK2_END */ /* Only bank1 will be erased*/ SET_BIT(FLASH->CR, FLASH_CR_MER); 8003202: 4b09 ldr r3, [pc, #36] ; (8003228 ) 8003204: 691b ldr r3, [r3, #16] 8003206: 4a08 ldr r2, [pc, #32] ; (8003228 ) 8003208: f043 0304 orr.w r3, r3, #4 800320c: 6113 str r3, [r2, #16] SET_BIT(FLASH->CR, FLASH_CR_STRT); 800320e: 4b06 ldr r3, [pc, #24] ; (8003228 ) 8003210: 691b ldr r3, [r3, #16] 8003212: 4a05 ldr r2, [pc, #20] ; (8003228 ) 8003214: f043 0340 orr.w r3, r3, #64 ; 0x40 8003218: 6113 str r3, [r2, #16] #if defined(FLASH_BANK2_END) } #endif /* FLASH_BANK2_END */ } 800321a: bf00 nop 800321c: 370c adds r7, #12 800321e: 46bd mov sp, r7 8003220: bc80 pop {r7} 8003222: 4770 bx lr 8003224: 200008f0 .word 0x200008f0 8003228: 40022000 .word 0x40022000 0800322c : * The value of this parameter depend on device used within the same series * * @retval None */ void FLASH_PageErase(uint32_t PageAddress) { 800322c: b480 push {r7} 800322e: b083 sub sp, #12 8003230: af00 add r7, sp, #0 8003232: 6078 str r0, [r7, #4] /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; 8003234: 4b0b ldr r3, [pc, #44] ; (8003264 ) 8003236: 2200 movs r2, #0 8003238: 61da str r2, [r3, #28] } else { #endif /* FLASH_BANK2_END */ /* Proceed to erase the page */ SET_BIT(FLASH->CR, FLASH_CR_PER); 800323a: 4b0b ldr r3, [pc, #44] ; (8003268 ) 800323c: 691b ldr r3, [r3, #16] 800323e: 4a0a ldr r2, [pc, #40] ; (8003268 ) 8003240: f043 0302 orr.w r3, r3, #2 8003244: 6113 str r3, [r2, #16] WRITE_REG(FLASH->AR, PageAddress); 8003246: 4a08 ldr r2, [pc, #32] ; (8003268 ) 8003248: 687b ldr r3, [r7, #4] 800324a: 6153 str r3, [r2, #20] SET_BIT(FLASH->CR, FLASH_CR_STRT); 800324c: 4b06 ldr r3, [pc, #24] ; (8003268 ) 800324e: 691b ldr r3, [r3, #16] 8003250: 4a05 ldr r2, [pc, #20] ; (8003268 ) 8003252: f043 0340 orr.w r3, r3, #64 ; 0x40 8003256: 6113 str r3, [r2, #16] #if defined(FLASH_BANK2_END) } #endif /* FLASH_BANK2_END */ } 8003258: bf00 nop 800325a: 370c adds r7, #12 800325c: 46bd mov sp, r7 800325e: bc80 pop {r7} 8003260: 4770 bx lr 8003262: bf00 nop 8003264: 200008f0 .word 0x200008f0 8003268: 40022000 .word 0x40022000 0800326c : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 800326c: b480 push {r7} 800326e: b08b sub sp, #44 ; 0x2c 8003270: af00 add r7, sp, #0 8003272: 6078 str r0, [r7, #4] 8003274: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 8003276: 2300 movs r3, #0 8003278: 627b str r3, [r7, #36] ; 0x24 uint32_t ioposition; uint32_t iocurrent; uint32_t temp; uint32_t config = 0x00u; 800327a: 2300 movs r3, #0 800327c: 623b str r3, [r7, #32] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 800327e: e127 b.n 80034d0 { /* Get the IO position */ ioposition = (0x01uL << position); 8003280: 2201 movs r2, #1 8003282: 6a7b ldr r3, [r7, #36] ; 0x24 8003284: fa02 f303 lsl.w r3, r2, r3 8003288: 61fb str r3, [r7, #28] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 800328a: 683b ldr r3, [r7, #0] 800328c: 681b ldr r3, [r3, #0] 800328e: 69fa ldr r2, [r7, #28] 8003290: 4013 ands r3, r2 8003292: 61bb str r3, [r7, #24] if (iocurrent == ioposition) 8003294: 69ba ldr r2, [r7, #24] 8003296: 69fb ldr r3, [r7, #28] 8003298: 429a cmp r2, r3 800329a: f040 8116 bne.w 80034ca { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ switch (GPIO_Init->Mode) 800329e: 683b ldr r3, [r7, #0] 80032a0: 685b ldr r3, [r3, #4] 80032a2: 2b12 cmp r3, #18 80032a4: d034 beq.n 8003310 80032a6: 2b12 cmp r3, #18 80032a8: d80d bhi.n 80032c6 80032aa: 2b02 cmp r3, #2 80032ac: d02b beq.n 8003306 80032ae: 2b02 cmp r3, #2 80032b0: d804 bhi.n 80032bc 80032b2: 2b00 cmp r3, #0 80032b4: d031 beq.n 800331a 80032b6: 2b01 cmp r3, #1 80032b8: d01c beq.n 80032f4 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; break; /* Parameters are checked with assert_param */ default: break; 80032ba: e048 b.n 800334e switch (GPIO_Init->Mode) 80032bc: 2b03 cmp r3, #3 80032be: d043 beq.n 8003348 80032c0: 2b11 cmp r3, #17 80032c2: d01b beq.n 80032fc break; 80032c4: e043 b.n 800334e switch (GPIO_Init->Mode) 80032c6: 4a89 ldr r2, [pc, #548] ; (80034ec ) 80032c8: 4293 cmp r3, r2 80032ca: d026 beq.n 800331a 80032cc: 4a87 ldr r2, [pc, #540] ; (80034ec ) 80032ce: 4293 cmp r3, r2 80032d0: d806 bhi.n 80032e0 80032d2: 4a87 ldr r2, [pc, #540] ; (80034f0 ) 80032d4: 4293 cmp r3, r2 80032d6: d020 beq.n 800331a 80032d8: 4a86 ldr r2, [pc, #536] ; (80034f4 ) 80032da: 4293 cmp r3, r2 80032dc: d01d beq.n 800331a break; 80032de: e036 b.n 800334e switch (GPIO_Init->Mode) 80032e0: 4a85 ldr r2, [pc, #532] ; (80034f8 ) 80032e2: 4293 cmp r3, r2 80032e4: d019 beq.n 800331a 80032e6: 4a85 ldr r2, [pc, #532] ; (80034fc ) 80032e8: 4293 cmp r3, r2 80032ea: d016 beq.n 800331a 80032ec: 4a84 ldr r2, [pc, #528] ; (8003500 ) 80032ee: 4293 cmp r3, r2 80032f0: d013 beq.n 800331a break; 80032f2: e02c b.n 800334e config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; 80032f4: 683b ldr r3, [r7, #0] 80032f6: 68db ldr r3, [r3, #12] 80032f8: 623b str r3, [r7, #32] break; 80032fa: e028 b.n 800334e config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; 80032fc: 683b ldr r3, [r7, #0] 80032fe: 68db ldr r3, [r3, #12] 8003300: 3304 adds r3, #4 8003302: 623b str r3, [r7, #32] break; 8003304: e023 b.n 800334e config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; 8003306: 683b ldr r3, [r7, #0] 8003308: 68db ldr r3, [r3, #12] 800330a: 3308 adds r3, #8 800330c: 623b str r3, [r7, #32] break; 800330e: e01e b.n 800334e config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; 8003310: 683b ldr r3, [r7, #0] 8003312: 68db ldr r3, [r3, #12] 8003314: 330c adds r3, #12 8003316: 623b str r3, [r7, #32] break; 8003318: e019 b.n 800334e if (GPIO_Init->Pull == GPIO_NOPULL) 800331a: 683b ldr r3, [r7, #0] 800331c: 689b ldr r3, [r3, #8] 800331e: 2b00 cmp r3, #0 8003320: d102 bne.n 8003328 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; 8003322: 2304 movs r3, #4 8003324: 623b str r3, [r7, #32] break; 8003326: e012 b.n 800334e else if (GPIO_Init->Pull == GPIO_PULLUP) 8003328: 683b ldr r3, [r7, #0] 800332a: 689b ldr r3, [r3, #8] 800332c: 2b01 cmp r3, #1 800332e: d105 bne.n 800333c config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 8003330: 2308 movs r3, #8 8003332: 623b str r3, [r7, #32] GPIOx->BSRR = ioposition; 8003334: 687b ldr r3, [r7, #4] 8003336: 69fa ldr r2, [r7, #28] 8003338: 611a str r2, [r3, #16] break; 800333a: e008 b.n 800334e config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 800333c: 2308 movs r3, #8 800333e: 623b str r3, [r7, #32] GPIOx->BRR = ioposition; 8003340: 687b ldr r3, [r7, #4] 8003342: 69fa ldr r2, [r7, #28] 8003344: 615a str r2, [r3, #20] break; 8003346: e002 b.n 800334e config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; 8003348: 2300 movs r3, #0 800334a: 623b str r3, [r7, #32] break; 800334c: bf00 nop } /* Check if the current bit belongs to first half or last half of the pin count number in order to address CRH or CRL register*/ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; 800334e: 69bb ldr r3, [r7, #24] 8003350: 2bff cmp r3, #255 ; 0xff 8003352: d801 bhi.n 8003358 8003354: 687b ldr r3, [r7, #4] 8003356: e001 b.n 800335c 8003358: 687b ldr r3, [r7, #4] 800335a: 3304 adds r3, #4 800335c: 617b str r3, [r7, #20] registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); 800335e: 69bb ldr r3, [r7, #24] 8003360: 2bff cmp r3, #255 ; 0xff 8003362: d802 bhi.n 800336a 8003364: 6a7b ldr r3, [r7, #36] ; 0x24 8003366: 009b lsls r3, r3, #2 8003368: e002 b.n 8003370 800336a: 6a7b ldr r3, [r7, #36] ; 0x24 800336c: 3b08 subs r3, #8 800336e: 009b lsls r3, r3, #2 8003370: 613b str r3, [r7, #16] /* Apply the new configuration of the pin to the register */ MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); 8003372: 697b ldr r3, [r7, #20] 8003374: 681a ldr r2, [r3, #0] 8003376: 210f movs r1, #15 8003378: 693b ldr r3, [r7, #16] 800337a: fa01 f303 lsl.w r3, r1, r3 800337e: 43db mvns r3, r3 8003380: 401a ands r2, r3 8003382: 6a39 ldr r1, [r7, #32] 8003384: 693b ldr r3, [r7, #16] 8003386: fa01 f303 lsl.w r3, r1, r3 800338a: 431a orrs r2, r3 800338c: 697b ldr r3, [r7, #20] 800338e: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 8003390: 683b ldr r3, [r7, #0] 8003392: 685b ldr r3, [r3, #4] 8003394: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8003398: 2b00 cmp r3, #0 800339a: f000 8096 beq.w 80034ca { /* Enable AFIO Clock */ __HAL_RCC_AFIO_CLK_ENABLE(); 800339e: 4b59 ldr r3, [pc, #356] ; (8003504 ) 80033a0: 699b ldr r3, [r3, #24] 80033a2: 4a58 ldr r2, [pc, #352] ; (8003504 ) 80033a4: f043 0301 orr.w r3, r3, #1 80033a8: 6193 str r3, [r2, #24] 80033aa: 4b56 ldr r3, [pc, #344] ; (8003504 ) 80033ac: 699b ldr r3, [r3, #24] 80033ae: f003 0301 and.w r3, r3, #1 80033b2: 60bb str r3, [r7, #8] 80033b4: 68bb ldr r3, [r7, #8] temp = AFIO->EXTICR[position >> 2u]; 80033b6: 4a54 ldr r2, [pc, #336] ; (8003508 ) 80033b8: 6a7b ldr r3, [r7, #36] ; 0x24 80033ba: 089b lsrs r3, r3, #2 80033bc: 3302 adds r3, #2 80033be: f852 3023 ldr.w r3, [r2, r3, lsl #2] 80033c2: 60fb str r3, [r7, #12] CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u))); 80033c4: 6a7b ldr r3, [r7, #36] ; 0x24 80033c6: f003 0303 and.w r3, r3, #3 80033ca: 009b lsls r3, r3, #2 80033cc: 220f movs r2, #15 80033ce: fa02 f303 lsl.w r3, r2, r3 80033d2: 43db mvns r3, r3 80033d4: 68fa ldr r2, [r7, #12] 80033d6: 4013 ands r3, r2 80033d8: 60fb str r3, [r7, #12] SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u))); 80033da: 687b ldr r3, [r7, #4] 80033dc: 4a4b ldr r2, [pc, #300] ; (800350c ) 80033de: 4293 cmp r3, r2 80033e0: d013 beq.n 800340a 80033e2: 687b ldr r3, [r7, #4] 80033e4: 4a4a ldr r2, [pc, #296] ; (8003510 ) 80033e6: 4293 cmp r3, r2 80033e8: d00d beq.n 8003406 80033ea: 687b ldr r3, [r7, #4] 80033ec: 4a49 ldr r2, [pc, #292] ; (8003514 ) 80033ee: 4293 cmp r3, r2 80033f0: d007 beq.n 8003402 80033f2: 687b ldr r3, [r7, #4] 80033f4: 4a48 ldr r2, [pc, #288] ; (8003518 ) 80033f6: 4293 cmp r3, r2 80033f8: d101 bne.n 80033fe 80033fa: 2303 movs r3, #3 80033fc: e006 b.n 800340c 80033fe: 2304 movs r3, #4 8003400: e004 b.n 800340c 8003402: 2302 movs r3, #2 8003404: e002 b.n 800340c 8003406: 2301 movs r3, #1 8003408: e000 b.n 800340c 800340a: 2300 movs r3, #0 800340c: 6a7a ldr r2, [r7, #36] ; 0x24 800340e: f002 0203 and.w r2, r2, #3 8003412: 0092 lsls r2, r2, #2 8003414: 4093 lsls r3, r2 8003416: 68fa ldr r2, [r7, #12] 8003418: 4313 orrs r3, r2 800341a: 60fb str r3, [r7, #12] AFIO->EXTICR[position >> 2u] = temp; 800341c: 493a ldr r1, [pc, #232] ; (8003508 ) 800341e: 6a7b ldr r3, [r7, #36] ; 0x24 8003420: 089b lsrs r3, r3, #2 8003422: 3302 adds r3, #2 8003424: 68fa ldr r2, [r7, #12] 8003426: f841 2023 str.w r2, [r1, r3, lsl #2] /* Configure the interrupt mask */ if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) 800342a: 683b ldr r3, [r7, #0] 800342c: 685b ldr r3, [r3, #4] 800342e: f403 3380 and.w r3, r3, #65536 ; 0x10000 8003432: 2b00 cmp r3, #0 8003434: d006 beq.n 8003444 { SET_BIT(EXTI->IMR, iocurrent); 8003436: 4b39 ldr r3, [pc, #228] ; (800351c ) 8003438: 681a ldr r2, [r3, #0] 800343a: 4938 ldr r1, [pc, #224] ; (800351c ) 800343c: 69bb ldr r3, [r7, #24] 800343e: 4313 orrs r3, r2 8003440: 600b str r3, [r1, #0] 8003442: e006 b.n 8003452 } else { CLEAR_BIT(EXTI->IMR, iocurrent); 8003444: 4b35 ldr r3, [pc, #212] ; (800351c ) 8003446: 681a ldr r2, [r3, #0] 8003448: 69bb ldr r3, [r7, #24] 800344a: 43db mvns r3, r3 800344c: 4933 ldr r1, [pc, #204] ; (800351c ) 800344e: 4013 ands r3, r2 8003450: 600b str r3, [r1, #0] } /* Configure the event mask */ if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) 8003452: 683b ldr r3, [r7, #0] 8003454: 685b ldr r3, [r3, #4] 8003456: f403 3300 and.w r3, r3, #131072 ; 0x20000 800345a: 2b00 cmp r3, #0 800345c: d006 beq.n 800346c { SET_BIT(EXTI->EMR, iocurrent); 800345e: 4b2f ldr r3, [pc, #188] ; (800351c ) 8003460: 685a ldr r2, [r3, #4] 8003462: 492e ldr r1, [pc, #184] ; (800351c ) 8003464: 69bb ldr r3, [r7, #24] 8003466: 4313 orrs r3, r2 8003468: 604b str r3, [r1, #4] 800346a: e006 b.n 800347a } else { CLEAR_BIT(EXTI->EMR, iocurrent); 800346c: 4b2b ldr r3, [pc, #172] ; (800351c ) 800346e: 685a ldr r2, [r3, #4] 8003470: 69bb ldr r3, [r7, #24] 8003472: 43db mvns r3, r3 8003474: 4929 ldr r1, [pc, #164] ; (800351c ) 8003476: 4013 ands r3, r2 8003478: 604b str r3, [r1, #4] } /* Enable or disable the rising trigger */ if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) 800347a: 683b ldr r3, [r7, #0] 800347c: 685b ldr r3, [r3, #4] 800347e: f403 1380 and.w r3, r3, #1048576 ; 0x100000 8003482: 2b00 cmp r3, #0 8003484: d006 beq.n 8003494 { SET_BIT(EXTI->RTSR, iocurrent); 8003486: 4b25 ldr r3, [pc, #148] ; (800351c ) 8003488: 689a ldr r2, [r3, #8] 800348a: 4924 ldr r1, [pc, #144] ; (800351c ) 800348c: 69bb ldr r3, [r7, #24] 800348e: 4313 orrs r3, r2 8003490: 608b str r3, [r1, #8] 8003492: e006 b.n 80034a2 } else { CLEAR_BIT(EXTI->RTSR, iocurrent); 8003494: 4b21 ldr r3, [pc, #132] ; (800351c ) 8003496: 689a ldr r2, [r3, #8] 8003498: 69bb ldr r3, [r7, #24] 800349a: 43db mvns r3, r3 800349c: 491f ldr r1, [pc, #124] ; (800351c ) 800349e: 4013 ands r3, r2 80034a0: 608b str r3, [r1, #8] } /* Enable or disable the falling trigger */ if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) 80034a2: 683b ldr r3, [r7, #0] 80034a4: 685b ldr r3, [r3, #4] 80034a6: f403 1300 and.w r3, r3, #2097152 ; 0x200000 80034aa: 2b00 cmp r3, #0 80034ac: d006 beq.n 80034bc { SET_BIT(EXTI->FTSR, iocurrent); 80034ae: 4b1b ldr r3, [pc, #108] ; (800351c ) 80034b0: 68da ldr r2, [r3, #12] 80034b2: 491a ldr r1, [pc, #104] ; (800351c ) 80034b4: 69bb ldr r3, [r7, #24] 80034b6: 4313 orrs r3, r2 80034b8: 60cb str r3, [r1, #12] 80034ba: e006 b.n 80034ca } else { CLEAR_BIT(EXTI->FTSR, iocurrent); 80034bc: 4b17 ldr r3, [pc, #92] ; (800351c ) 80034be: 68da ldr r2, [r3, #12] 80034c0: 69bb ldr r3, [r7, #24] 80034c2: 43db mvns r3, r3 80034c4: 4915 ldr r1, [pc, #84] ; (800351c ) 80034c6: 4013 ands r3, r2 80034c8: 60cb str r3, [r1, #12] } } } position++; 80034ca: 6a7b ldr r3, [r7, #36] ; 0x24 80034cc: 3301 adds r3, #1 80034ce: 627b str r3, [r7, #36] ; 0x24 while (((GPIO_Init->Pin) >> position) != 0x00u) 80034d0: 683b ldr r3, [r7, #0] 80034d2: 681a ldr r2, [r3, #0] 80034d4: 6a7b ldr r3, [r7, #36] ; 0x24 80034d6: fa22 f303 lsr.w r3, r2, r3 80034da: 2b00 cmp r3, #0 80034dc: f47f aed0 bne.w 8003280 } } 80034e0: bf00 nop 80034e2: 372c adds r7, #44 ; 0x2c 80034e4: 46bd mov sp, r7 80034e6: bc80 pop {r7} 80034e8: 4770 bx lr 80034ea: bf00 nop 80034ec: 10210000 .word 0x10210000 80034f0: 10110000 .word 0x10110000 80034f4: 10120000 .word 0x10120000 80034f8: 10310000 .word 0x10310000 80034fc: 10320000 .word 0x10320000 8003500: 10220000 .word 0x10220000 8003504: 40021000 .word 0x40021000 8003508: 40010000 .word 0x40010000 800350c: 40010800 .word 0x40010800 8003510: 40010c00 .word 0x40010c00 8003514: 40011000 .word 0x40011000 8003518: 40011400 .word 0x40011400 800351c: 40010400 .word 0x40010400 08003520 : * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 8003520: b480 push {r7} 8003522: b085 sub sp, #20 8003524: af00 add r7, sp, #0 8003526: 6078 str r0, [r7, #4] 8003528: 460b mov r3, r1 800352a: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) 800352c: 687b ldr r3, [r7, #4] 800352e: 689a ldr r2, [r3, #8] 8003530: 887b ldrh r3, [r7, #2] 8003532: 4013 ands r3, r2 8003534: 2b00 cmp r3, #0 8003536: d002 beq.n 800353e { bitstatus = GPIO_PIN_SET; 8003538: 2301 movs r3, #1 800353a: 73fb strb r3, [r7, #15] 800353c: e001 b.n 8003542 } else { bitstatus = GPIO_PIN_RESET; 800353e: 2300 movs r3, #0 8003540: 73fb strb r3, [r7, #15] } return bitstatus; 8003542: 7bfb ldrb r3, [r7, #15] } 8003544: 4618 mov r0, r3 8003546: 3714 adds r7, #20 8003548: 46bd mov sp, r7 800354a: bc80 pop {r7} 800354c: 4770 bx lr 0800354e : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 800354e: b480 push {r7} 8003550: b083 sub sp, #12 8003552: af00 add r7, sp, #0 8003554: 6078 str r0, [r7, #4] 8003556: 460b mov r3, r1 8003558: 807b strh r3, [r7, #2] 800355a: 4613 mov r3, r2 800355c: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 800355e: 787b ldrb r3, [r7, #1] 8003560: 2b00 cmp r3, #0 8003562: d003 beq.n 800356c { GPIOx->BSRR = GPIO_Pin; 8003564: 887a ldrh r2, [r7, #2] 8003566: 687b ldr r3, [r7, #4] 8003568: 611a str r2, [r3, #16] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; } } 800356a: e003 b.n 8003574 GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; 800356c: 887b ldrh r3, [r7, #2] 800356e: 041a lsls r2, r3, #16 8003570: 687b ldr r3, [r7, #4] 8003572: 611a str r2, [r3, #16] } 8003574: bf00 nop 8003576: 370c adds r7, #12 8003578: 46bd mov sp, r7 800357a: bc80 pop {r7} 800357c: 4770 bx lr 0800357e : * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral * @param GPIO_Pin: Specifies the pins to be toggled. * @retval None */ void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 800357e: b480 push {r7} 8003580: b083 sub sp, #12 8003582: af00 add r7, sp, #0 8003584: 6078 str r0, [r7, #4] 8003586: 460b mov r3, r1 8003588: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->ODR & GPIO_Pin) != 0x00u) 800358a: 687b ldr r3, [r7, #4] 800358c: 68da ldr r2, [r3, #12] 800358e: 887b ldrh r3, [r7, #2] 8003590: 4013 ands r3, r2 8003592: 2b00 cmp r3, #0 8003594: d003 beq.n 800359e { GPIOx->BRR = (uint32_t)GPIO_Pin; 8003596: 887a ldrh r2, [r7, #2] 8003598: 687b ldr r3, [r7, #4] 800359a: 615a str r2, [r3, #20] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin; } } 800359c: e002 b.n 80035a4 GPIOx->BSRR = (uint32_t)GPIO_Pin; 800359e: 887a ldrh r2, [r7, #2] 80035a0: 687b ldr r3, [r7, #4] 80035a2: 611a str r2, [r3, #16] } 80035a4: bf00 nop 80035a6: 370c adds r7, #12 80035a8: 46bd mov sp, r7 80035aa: bc80 pop {r7} 80035ac: 4770 bx lr ... 080035b0 : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 80035b0: b580 push {r7, lr} 80035b2: b086 sub sp, #24 80035b4: af00 add r7, sp, #0 80035b6: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 80035b8: 687b ldr r3, [r7, #4] 80035ba: 2b00 cmp r3, #0 80035bc: d101 bne.n 80035c2 { return HAL_ERROR; 80035be: 2301 movs r3, #1 80035c0: e26c b.n 8003a9c /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 80035c2: 687b ldr r3, [r7, #4] 80035c4: 681b ldr r3, [r3, #0] 80035c6: f003 0301 and.w r3, r3, #1 80035ca: 2b00 cmp r3, #0 80035cc: f000 8087 beq.w 80036de { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 80035d0: 4b92 ldr r3, [pc, #584] ; (800381c ) 80035d2: 685b ldr r3, [r3, #4] 80035d4: f003 030c and.w r3, r3, #12 80035d8: 2b04 cmp r3, #4 80035da: d00c beq.n 80035f6 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 80035dc: 4b8f ldr r3, [pc, #572] ; (800381c ) 80035de: 685b ldr r3, [r3, #4] 80035e0: f003 030c and.w r3, r3, #12 80035e4: 2b08 cmp r3, #8 80035e6: d112 bne.n 800360e 80035e8: 4b8c ldr r3, [pc, #560] ; (800381c ) 80035ea: 685b ldr r3, [r3, #4] 80035ec: f403 3380 and.w r3, r3, #65536 ; 0x10000 80035f0: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 80035f4: d10b bne.n 800360e { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 80035f6: 4b89 ldr r3, [pc, #548] ; (800381c ) 80035f8: 681b ldr r3, [r3, #0] 80035fa: f403 3300 and.w r3, r3, #131072 ; 0x20000 80035fe: 2b00 cmp r3, #0 8003600: d06c beq.n 80036dc 8003602: 687b ldr r3, [r7, #4] 8003604: 685b ldr r3, [r3, #4] 8003606: 2b00 cmp r3, #0 8003608: d168 bne.n 80036dc { return HAL_ERROR; 800360a: 2301 movs r3, #1 800360c: e246 b.n 8003a9c } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 800360e: 687b ldr r3, [r7, #4] 8003610: 685b ldr r3, [r3, #4] 8003612: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8003616: d106 bne.n 8003626 8003618: 4b80 ldr r3, [pc, #512] ; (800381c ) 800361a: 681b ldr r3, [r3, #0] 800361c: 4a7f ldr r2, [pc, #508] ; (800381c ) 800361e: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8003622: 6013 str r3, [r2, #0] 8003624: e02e b.n 8003684 8003626: 687b ldr r3, [r7, #4] 8003628: 685b ldr r3, [r3, #4] 800362a: 2b00 cmp r3, #0 800362c: d10c bne.n 8003648 800362e: 4b7b ldr r3, [pc, #492] ; (800381c ) 8003630: 681b ldr r3, [r3, #0] 8003632: 4a7a ldr r2, [pc, #488] ; (800381c ) 8003634: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8003638: 6013 str r3, [r2, #0] 800363a: 4b78 ldr r3, [pc, #480] ; (800381c ) 800363c: 681b ldr r3, [r3, #0] 800363e: 4a77 ldr r2, [pc, #476] ; (800381c ) 8003640: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8003644: 6013 str r3, [r2, #0] 8003646: e01d b.n 8003684 8003648: 687b ldr r3, [r7, #4] 800364a: 685b ldr r3, [r3, #4] 800364c: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 8003650: d10c bne.n 800366c 8003652: 4b72 ldr r3, [pc, #456] ; (800381c ) 8003654: 681b ldr r3, [r3, #0] 8003656: 4a71 ldr r2, [pc, #452] ; (800381c ) 8003658: f443 2380 orr.w r3, r3, #262144 ; 0x40000 800365c: 6013 str r3, [r2, #0] 800365e: 4b6f ldr r3, [pc, #444] ; (800381c ) 8003660: 681b ldr r3, [r3, #0] 8003662: 4a6e ldr r2, [pc, #440] ; (800381c ) 8003664: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8003668: 6013 str r3, [r2, #0] 800366a: e00b b.n 8003684 800366c: 4b6b ldr r3, [pc, #428] ; (800381c ) 800366e: 681b ldr r3, [r3, #0] 8003670: 4a6a ldr r2, [pc, #424] ; (800381c ) 8003672: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8003676: 6013 str r3, [r2, #0] 8003678: 4b68 ldr r3, [pc, #416] ; (800381c ) 800367a: 681b ldr r3, [r3, #0] 800367c: 4a67 ldr r2, [pc, #412] ; (800381c ) 800367e: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8003682: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8003684: 687b ldr r3, [r7, #4] 8003686: 685b ldr r3, [r3, #4] 8003688: 2b00 cmp r3, #0 800368a: d013 beq.n 80036b4 { /* Get Start Tick */ tickstart = HAL_GetTick(); 800368c: f7fe fb9e bl 8001dcc 8003690: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8003692: e008 b.n 80036a6 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8003694: f7fe fb9a bl 8001dcc 8003698: 4602 mov r2, r0 800369a: 693b ldr r3, [r7, #16] 800369c: 1ad3 subs r3, r2, r3 800369e: 2b64 cmp r3, #100 ; 0x64 80036a0: d901 bls.n 80036a6 { return HAL_TIMEOUT; 80036a2: 2303 movs r3, #3 80036a4: e1fa b.n 8003a9c while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 80036a6: 4b5d ldr r3, [pc, #372] ; (800381c ) 80036a8: 681b ldr r3, [r3, #0] 80036aa: f403 3300 and.w r3, r3, #131072 ; 0x20000 80036ae: 2b00 cmp r3, #0 80036b0: d0f0 beq.n 8003694 80036b2: e014 b.n 80036de } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 80036b4: f7fe fb8a bl 8001dcc 80036b8: 6138 str r0, [r7, #16] /* Wait till HSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 80036ba: e008 b.n 80036ce { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 80036bc: f7fe fb86 bl 8001dcc 80036c0: 4602 mov r2, r0 80036c2: 693b ldr r3, [r7, #16] 80036c4: 1ad3 subs r3, r2, r3 80036c6: 2b64 cmp r3, #100 ; 0x64 80036c8: d901 bls.n 80036ce { return HAL_TIMEOUT; 80036ca: 2303 movs r3, #3 80036cc: e1e6 b.n 8003a9c while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 80036ce: 4b53 ldr r3, [pc, #332] ; (800381c ) 80036d0: 681b ldr r3, [r3, #0] 80036d2: f403 3300 and.w r3, r3, #131072 ; 0x20000 80036d6: 2b00 cmp r3, #0 80036d8: d1f0 bne.n 80036bc 80036da: e000 b.n 80036de if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 80036dc: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 80036de: 687b ldr r3, [r7, #4] 80036e0: 681b ldr r3, [r3, #0] 80036e2: f003 0302 and.w r3, r3, #2 80036e6: 2b00 cmp r3, #0 80036e8: d063 beq.n 80037b2 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 80036ea: 4b4c ldr r3, [pc, #304] ; (800381c ) 80036ec: 685b ldr r3, [r3, #4] 80036ee: f003 030c and.w r3, r3, #12 80036f2: 2b00 cmp r3, #0 80036f4: d00b beq.n 800370e || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) 80036f6: 4b49 ldr r3, [pc, #292] ; (800381c ) 80036f8: 685b ldr r3, [r3, #4] 80036fa: f003 030c and.w r3, r3, #12 80036fe: 2b08 cmp r3, #8 8003700: d11c bne.n 800373c 8003702: 4b46 ldr r3, [pc, #280] ; (800381c ) 8003704: 685b ldr r3, [r3, #4] 8003706: f403 3380 and.w r3, r3, #65536 ; 0x10000 800370a: 2b00 cmp r3, #0 800370c: d116 bne.n 800373c { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 800370e: 4b43 ldr r3, [pc, #268] ; (800381c ) 8003710: 681b ldr r3, [r3, #0] 8003712: f003 0302 and.w r3, r3, #2 8003716: 2b00 cmp r3, #0 8003718: d005 beq.n 8003726 800371a: 687b ldr r3, [r7, #4] 800371c: 691b ldr r3, [r3, #16] 800371e: 2b01 cmp r3, #1 8003720: d001 beq.n 8003726 { return HAL_ERROR; 8003722: 2301 movs r3, #1 8003724: e1ba b.n 8003a9c } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8003726: 4b3d ldr r3, [pc, #244] ; (800381c ) 8003728: 681b ldr r3, [r3, #0] 800372a: f023 02f8 bic.w r2, r3, #248 ; 0xf8 800372e: 687b ldr r3, [r7, #4] 8003730: 695b ldr r3, [r3, #20] 8003732: 00db lsls r3, r3, #3 8003734: 4939 ldr r1, [pc, #228] ; (800381c ) 8003736: 4313 orrs r3, r2 8003738: 600b str r3, [r1, #0] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 800373a: e03a b.n 80037b2 } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 800373c: 687b ldr r3, [r7, #4] 800373e: 691b ldr r3, [r3, #16] 8003740: 2b00 cmp r3, #0 8003742: d020 beq.n 8003786 { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 8003744: 4b36 ldr r3, [pc, #216] ; (8003820 ) 8003746: 2201 movs r2, #1 8003748: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800374a: f7fe fb3f bl 8001dcc 800374e: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8003750: e008 b.n 8003764 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8003752: f7fe fb3b bl 8001dcc 8003756: 4602 mov r2, r0 8003758: 693b ldr r3, [r7, #16] 800375a: 1ad3 subs r3, r2, r3 800375c: 2b02 cmp r3, #2 800375e: d901 bls.n 8003764 { return HAL_TIMEOUT; 8003760: 2303 movs r3, #3 8003762: e19b b.n 8003a9c while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8003764: 4b2d ldr r3, [pc, #180] ; (800381c ) 8003766: 681b ldr r3, [r3, #0] 8003768: f003 0302 and.w r3, r3, #2 800376c: 2b00 cmp r3, #0 800376e: d0f0 beq.n 8003752 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8003770: 4b2a ldr r3, [pc, #168] ; (800381c ) 8003772: 681b ldr r3, [r3, #0] 8003774: f023 02f8 bic.w r2, r3, #248 ; 0xf8 8003778: 687b ldr r3, [r7, #4] 800377a: 695b ldr r3, [r3, #20] 800377c: 00db lsls r3, r3, #3 800377e: 4927 ldr r1, [pc, #156] ; (800381c ) 8003780: 4313 orrs r3, r2 8003782: 600b str r3, [r1, #0] 8003784: e015 b.n 80037b2 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8003786: 4b26 ldr r3, [pc, #152] ; (8003820 ) 8003788: 2200 movs r2, #0 800378a: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800378c: f7fe fb1e bl 8001dcc 8003790: 6138 str r0, [r7, #16] /* Wait till HSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8003792: e008 b.n 80037a6 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8003794: f7fe fb1a bl 8001dcc 8003798: 4602 mov r2, r0 800379a: 693b ldr r3, [r7, #16] 800379c: 1ad3 subs r3, r2, r3 800379e: 2b02 cmp r3, #2 80037a0: d901 bls.n 80037a6 { return HAL_TIMEOUT; 80037a2: 2303 movs r3, #3 80037a4: e17a b.n 8003a9c while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 80037a6: 4b1d ldr r3, [pc, #116] ; (800381c ) 80037a8: 681b ldr r3, [r3, #0] 80037aa: f003 0302 and.w r3, r3, #2 80037ae: 2b00 cmp r3, #0 80037b0: d1f0 bne.n 8003794 } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 80037b2: 687b ldr r3, [r7, #4] 80037b4: 681b ldr r3, [r3, #0] 80037b6: f003 0308 and.w r3, r3, #8 80037ba: 2b00 cmp r3, #0 80037bc: d03a beq.n 8003834 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 80037be: 687b ldr r3, [r7, #4] 80037c0: 699b ldr r3, [r3, #24] 80037c2: 2b00 cmp r3, #0 80037c4: d019 beq.n 80037fa { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 80037c6: 4b17 ldr r3, [pc, #92] ; (8003824 ) 80037c8: 2201 movs r2, #1 80037ca: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80037cc: f7fe fafe bl 8001dcc 80037d0: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 80037d2: e008 b.n 80037e6 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 80037d4: f7fe fafa bl 8001dcc 80037d8: 4602 mov r2, r0 80037da: 693b ldr r3, [r7, #16] 80037dc: 1ad3 subs r3, r2, r3 80037de: 2b02 cmp r3, #2 80037e0: d901 bls.n 80037e6 { return HAL_TIMEOUT; 80037e2: 2303 movs r3, #3 80037e4: e15a b.n 8003a9c while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 80037e6: 4b0d ldr r3, [pc, #52] ; (800381c ) 80037e8: 6a5b ldr r3, [r3, #36] ; 0x24 80037ea: f003 0302 and.w r3, r3, #2 80037ee: 2b00 cmp r3, #0 80037f0: d0f0 beq.n 80037d4 } } /* To have a fully stabilized clock in the specified range, a software delay of 1ms should be added.*/ RCC_Delay(1); 80037f2: 2001 movs r0, #1 80037f4: f000 fad6 bl 8003da4 80037f8: e01c b.n 8003834 } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 80037fa: 4b0a ldr r3, [pc, #40] ; (8003824 ) 80037fc: 2200 movs r2, #0 80037fe: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8003800: f7fe fae4 bl 8001dcc 8003804: 6138 str r0, [r7, #16] /* Wait till LSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8003806: e00f b.n 8003828 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8003808: f7fe fae0 bl 8001dcc 800380c: 4602 mov r2, r0 800380e: 693b ldr r3, [r7, #16] 8003810: 1ad3 subs r3, r2, r3 8003812: 2b02 cmp r3, #2 8003814: d908 bls.n 8003828 { return HAL_TIMEOUT; 8003816: 2303 movs r3, #3 8003818: e140 b.n 8003a9c 800381a: bf00 nop 800381c: 40021000 .word 0x40021000 8003820: 42420000 .word 0x42420000 8003824: 42420480 .word 0x42420480 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8003828: 4b9e ldr r3, [pc, #632] ; (8003aa4 ) 800382a: 6a5b ldr r3, [r3, #36] ; 0x24 800382c: f003 0302 and.w r3, r3, #2 8003830: 2b00 cmp r3, #0 8003832: d1e9 bne.n 8003808 } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8003834: 687b ldr r3, [r7, #4] 8003836: 681b ldr r3, [r3, #0] 8003838: f003 0304 and.w r3, r3, #4 800383c: 2b00 cmp r3, #0 800383e: f000 80a6 beq.w 800398e { FlagStatus pwrclkchanged = RESET; 8003842: 2300 movs r3, #0 8003844: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 8003846: 4b97 ldr r3, [pc, #604] ; (8003aa4 ) 8003848: 69db ldr r3, [r3, #28] 800384a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 800384e: 2b00 cmp r3, #0 8003850: d10d bne.n 800386e { __HAL_RCC_PWR_CLK_ENABLE(); 8003852: 4b94 ldr r3, [pc, #592] ; (8003aa4 ) 8003854: 69db ldr r3, [r3, #28] 8003856: 4a93 ldr r2, [pc, #588] ; (8003aa4 ) 8003858: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 800385c: 61d3 str r3, [r2, #28] 800385e: 4b91 ldr r3, [pc, #580] ; (8003aa4 ) 8003860: 69db ldr r3, [r3, #28] 8003862: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8003866: 60bb str r3, [r7, #8] 8003868: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 800386a: 2301 movs r3, #1 800386c: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 800386e: 4b8e ldr r3, [pc, #568] ; (8003aa8 ) 8003870: 681b ldr r3, [r3, #0] 8003872: f403 7380 and.w r3, r3, #256 ; 0x100 8003876: 2b00 cmp r3, #0 8003878: d118 bne.n 80038ac { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 800387a: 4b8b ldr r3, [pc, #556] ; (8003aa8 ) 800387c: 681b ldr r3, [r3, #0] 800387e: 4a8a ldr r2, [pc, #552] ; (8003aa8 ) 8003880: f443 7380 orr.w r3, r3, #256 ; 0x100 8003884: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8003886: f7fe faa1 bl 8001dcc 800388a: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 800388c: e008 b.n 80038a0 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 800388e: f7fe fa9d bl 8001dcc 8003892: 4602 mov r2, r0 8003894: 693b ldr r3, [r7, #16] 8003896: 1ad3 subs r3, r2, r3 8003898: 2b64 cmp r3, #100 ; 0x64 800389a: d901 bls.n 80038a0 { return HAL_TIMEOUT; 800389c: 2303 movs r3, #3 800389e: e0fd b.n 8003a9c while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80038a0: 4b81 ldr r3, [pc, #516] ; (8003aa8 ) 80038a2: 681b ldr r3, [r3, #0] 80038a4: f403 7380 and.w r3, r3, #256 ; 0x100 80038a8: 2b00 cmp r3, #0 80038aa: d0f0 beq.n 800388e } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 80038ac: 687b ldr r3, [r7, #4] 80038ae: 68db ldr r3, [r3, #12] 80038b0: 2b01 cmp r3, #1 80038b2: d106 bne.n 80038c2 80038b4: 4b7b ldr r3, [pc, #492] ; (8003aa4 ) 80038b6: 6a1b ldr r3, [r3, #32] 80038b8: 4a7a ldr r2, [pc, #488] ; (8003aa4 ) 80038ba: f043 0301 orr.w r3, r3, #1 80038be: 6213 str r3, [r2, #32] 80038c0: e02d b.n 800391e 80038c2: 687b ldr r3, [r7, #4] 80038c4: 68db ldr r3, [r3, #12] 80038c6: 2b00 cmp r3, #0 80038c8: d10c bne.n 80038e4 80038ca: 4b76 ldr r3, [pc, #472] ; (8003aa4 ) 80038cc: 6a1b ldr r3, [r3, #32] 80038ce: 4a75 ldr r2, [pc, #468] ; (8003aa4 ) 80038d0: f023 0301 bic.w r3, r3, #1 80038d4: 6213 str r3, [r2, #32] 80038d6: 4b73 ldr r3, [pc, #460] ; (8003aa4 ) 80038d8: 6a1b ldr r3, [r3, #32] 80038da: 4a72 ldr r2, [pc, #456] ; (8003aa4 ) 80038dc: f023 0304 bic.w r3, r3, #4 80038e0: 6213 str r3, [r2, #32] 80038e2: e01c b.n 800391e 80038e4: 687b ldr r3, [r7, #4] 80038e6: 68db ldr r3, [r3, #12] 80038e8: 2b05 cmp r3, #5 80038ea: d10c bne.n 8003906 80038ec: 4b6d ldr r3, [pc, #436] ; (8003aa4 ) 80038ee: 6a1b ldr r3, [r3, #32] 80038f0: 4a6c ldr r2, [pc, #432] ; (8003aa4 ) 80038f2: f043 0304 orr.w r3, r3, #4 80038f6: 6213 str r3, [r2, #32] 80038f8: 4b6a ldr r3, [pc, #424] ; (8003aa4 ) 80038fa: 6a1b ldr r3, [r3, #32] 80038fc: 4a69 ldr r2, [pc, #420] ; (8003aa4 ) 80038fe: f043 0301 orr.w r3, r3, #1 8003902: 6213 str r3, [r2, #32] 8003904: e00b b.n 800391e 8003906: 4b67 ldr r3, [pc, #412] ; (8003aa4 ) 8003908: 6a1b ldr r3, [r3, #32] 800390a: 4a66 ldr r2, [pc, #408] ; (8003aa4 ) 800390c: f023 0301 bic.w r3, r3, #1 8003910: 6213 str r3, [r2, #32] 8003912: 4b64 ldr r3, [pc, #400] ; (8003aa4 ) 8003914: 6a1b ldr r3, [r3, #32] 8003916: 4a63 ldr r2, [pc, #396] ; (8003aa4 ) 8003918: f023 0304 bic.w r3, r3, #4 800391c: 6213 str r3, [r2, #32] /* Check the LSE State */ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 800391e: 687b ldr r3, [r7, #4] 8003920: 68db ldr r3, [r3, #12] 8003922: 2b00 cmp r3, #0 8003924: d015 beq.n 8003952 { /* Get Start Tick */ tickstart = HAL_GetTick(); 8003926: f7fe fa51 bl 8001dcc 800392a: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 800392c: e00a b.n 8003944 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800392e: f7fe fa4d bl 8001dcc 8003932: 4602 mov r2, r0 8003934: 693b ldr r3, [r7, #16] 8003936: 1ad3 subs r3, r2, r3 8003938: f241 3288 movw r2, #5000 ; 0x1388 800393c: 4293 cmp r3, r2 800393e: d901 bls.n 8003944 { return HAL_TIMEOUT; 8003940: 2303 movs r3, #3 8003942: e0ab b.n 8003a9c while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8003944: 4b57 ldr r3, [pc, #348] ; (8003aa4 ) 8003946: 6a1b ldr r3, [r3, #32] 8003948: f003 0302 and.w r3, r3, #2 800394c: 2b00 cmp r3, #0 800394e: d0ee beq.n 800392e 8003950: e014 b.n 800397c } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8003952: f7fe fa3b bl 8001dcc 8003956: 6138 str r0, [r7, #16] /* Wait till LSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8003958: e00a b.n 8003970 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800395a: f7fe fa37 bl 8001dcc 800395e: 4602 mov r2, r0 8003960: 693b ldr r3, [r7, #16] 8003962: 1ad3 subs r3, r2, r3 8003964: f241 3288 movw r2, #5000 ; 0x1388 8003968: 4293 cmp r3, r2 800396a: d901 bls.n 8003970 { return HAL_TIMEOUT; 800396c: 2303 movs r3, #3 800396e: e095 b.n 8003a9c while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8003970: 4b4c ldr r3, [pc, #304] ; (8003aa4 ) 8003972: 6a1b ldr r3, [r3, #32] 8003974: f003 0302 and.w r3, r3, #2 8003978: 2b00 cmp r3, #0 800397a: d1ee bne.n 800395a } } } /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 800397c: 7dfb ldrb r3, [r7, #23] 800397e: 2b01 cmp r3, #1 8003980: d105 bne.n 800398e { __HAL_RCC_PWR_CLK_DISABLE(); 8003982: 4b48 ldr r3, [pc, #288] ; (8003aa4 ) 8003984: 69db ldr r3, [r3, #28] 8003986: 4a47 ldr r2, [pc, #284] ; (8003aa4 ) 8003988: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 800398c: 61d3 str r3, [r2, #28] #endif /* RCC_CR_PLL2ON */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 800398e: 687b ldr r3, [r7, #4] 8003990: 69db ldr r3, [r3, #28] 8003992: 2b00 cmp r3, #0 8003994: f000 8081 beq.w 8003a9a { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 8003998: 4b42 ldr r3, [pc, #264] ; (8003aa4 ) 800399a: 685b ldr r3, [r3, #4] 800399c: f003 030c and.w r3, r3, #12 80039a0: 2b08 cmp r3, #8 80039a2: d061 beq.n 8003a68 { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 80039a4: 687b ldr r3, [r7, #4] 80039a6: 69db ldr r3, [r3, #28] 80039a8: 2b02 cmp r3, #2 80039aa: d146 bne.n 8003a3a /* Check the parameters */ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 80039ac: 4b3f ldr r3, [pc, #252] ; (8003aac ) 80039ae: 2200 movs r2, #0 80039b0: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80039b2: f7fe fa0b bl 8001dcc 80039b6: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80039b8: e008 b.n 80039cc { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80039ba: f7fe fa07 bl 8001dcc 80039be: 4602 mov r2, r0 80039c0: 693b ldr r3, [r7, #16] 80039c2: 1ad3 subs r3, r2, r3 80039c4: 2b02 cmp r3, #2 80039c6: d901 bls.n 80039cc { return HAL_TIMEOUT; 80039c8: 2303 movs r3, #3 80039ca: e067 b.n 8003a9c while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80039cc: 4b35 ldr r3, [pc, #212] ; (8003aa4 ) 80039ce: 681b ldr r3, [r3, #0] 80039d0: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 80039d4: 2b00 cmp r3, #0 80039d6: d1f0 bne.n 80039ba } } /* Configure the HSE prediv factor --------------------------------*/ /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */ if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE) 80039d8: 687b ldr r3, [r7, #4] 80039da: 6a1b ldr r3, [r3, #32] 80039dc: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 80039e0: d108 bne.n 80039f4 /* Set PREDIV1 source */ SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source); #endif /* RCC_CFGR2_PREDIV1SRC */ /* Set PREDIV1 Value */ __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); 80039e2: 4b30 ldr r3, [pc, #192] ; (8003aa4 ) 80039e4: 6adb ldr r3, [r3, #44] ; 0x2c 80039e6: f023 020f bic.w r2, r3, #15 80039ea: 687b ldr r3, [r7, #4] 80039ec: 689b ldr r3, [r3, #8] 80039ee: 492d ldr r1, [pc, #180] ; (8003aa4 ) 80039f0: 4313 orrs r3, r2 80039f2: 62cb str r3, [r1, #44] ; 0x2c } /* Configure the main PLL clock source and multiplication factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 80039f4: 4b2b ldr r3, [pc, #172] ; (8003aa4 ) 80039f6: 685b ldr r3, [r3, #4] 80039f8: f423 1274 bic.w r2, r3, #3997696 ; 0x3d0000 80039fc: 687b ldr r3, [r7, #4] 80039fe: 6a19 ldr r1, [r3, #32] 8003a00: 687b ldr r3, [r7, #4] 8003a02: 6a5b ldr r3, [r3, #36] ; 0x24 8003a04: 430b orrs r3, r1 8003a06: 4927 ldr r1, [pc, #156] ; (8003aa4 ) 8003a08: 4313 orrs r3, r2 8003a0a: 604b str r3, [r1, #4] RCC_OscInitStruct->PLL.PLLMUL); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 8003a0c: 4b27 ldr r3, [pc, #156] ; (8003aac ) 8003a0e: 2201 movs r2, #1 8003a10: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8003a12: f7fe f9db bl 8001dcc 8003a16: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8003a18: e008 b.n 8003a2c { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8003a1a: f7fe f9d7 bl 8001dcc 8003a1e: 4602 mov r2, r0 8003a20: 693b ldr r3, [r7, #16] 8003a22: 1ad3 subs r3, r2, r3 8003a24: 2b02 cmp r3, #2 8003a26: d901 bls.n 8003a2c { return HAL_TIMEOUT; 8003a28: 2303 movs r3, #3 8003a2a: e037 b.n 8003a9c while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8003a2c: 4b1d ldr r3, [pc, #116] ; (8003aa4 ) 8003a2e: 681b ldr r3, [r3, #0] 8003a30: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8003a34: 2b00 cmp r3, #0 8003a36: d0f0 beq.n 8003a1a 8003a38: e02f b.n 8003a9a } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8003a3a: 4b1c ldr r3, [pc, #112] ; (8003aac ) 8003a3c: 2200 movs r2, #0 8003a3e: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8003a40: f7fe f9c4 bl 8001dcc 8003a44: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8003a46: e008 b.n 8003a5a { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8003a48: f7fe f9c0 bl 8001dcc 8003a4c: 4602 mov r2, r0 8003a4e: 693b ldr r3, [r7, #16] 8003a50: 1ad3 subs r3, r2, r3 8003a52: 2b02 cmp r3, #2 8003a54: d901 bls.n 8003a5a { return HAL_TIMEOUT; 8003a56: 2303 movs r3, #3 8003a58: e020 b.n 8003a9c while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8003a5a: 4b12 ldr r3, [pc, #72] ; (8003aa4 ) 8003a5c: 681b ldr r3, [r3, #0] 8003a5e: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8003a62: 2b00 cmp r3, #0 8003a64: d1f0 bne.n 8003a48 8003a66: e018 b.n 8003a9a } } else { /* Check if there is a request to disable the PLL used as System clock source */ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 8003a68: 687b ldr r3, [r7, #4] 8003a6a: 69db ldr r3, [r3, #28] 8003a6c: 2b01 cmp r3, #1 8003a6e: d101 bne.n 8003a74 { return HAL_ERROR; 8003a70: 2301 movs r3, #1 8003a72: e013 b.n 8003a9c } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->CFGR; 8003a74: 4b0b ldr r3, [pc, #44] ; (8003aa4 ) 8003a76: 685b ldr r3, [r3, #4] 8003a78: 60fb str r3, [r7, #12] if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8003a7a: 68fb ldr r3, [r7, #12] 8003a7c: f403 3280 and.w r2, r3, #65536 ; 0x10000 8003a80: 687b ldr r3, [r7, #4] 8003a82: 6a1b ldr r3, [r3, #32] 8003a84: 429a cmp r2, r3 8003a86: d106 bne.n 8003a96 (READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL)) 8003a88: 68fb ldr r3, [r7, #12] 8003a8a: f403 1270 and.w r2, r3, #3932160 ; 0x3c0000 8003a8e: 687b ldr r3, [r7, #4] 8003a90: 6a5b ldr r3, [r3, #36] ; 0x24 if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8003a92: 429a cmp r2, r3 8003a94: d001 beq.n 8003a9a { return HAL_ERROR; 8003a96: 2301 movs r3, #1 8003a98: e000 b.n 8003a9c } } } } return HAL_OK; 8003a9a: 2300 movs r3, #0 } 8003a9c: 4618 mov r0, r3 8003a9e: 3718 adds r7, #24 8003aa0: 46bd mov sp, r7 8003aa2: bd80 pop {r7, pc} 8003aa4: 40021000 .word 0x40021000 8003aa8: 40007000 .word 0x40007000 8003aac: 42420060 .word 0x42420060 08003ab0 : * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8003ab0: b580 push {r7, lr} 8003ab2: b084 sub sp, #16 8003ab4: af00 add r7, sp, #0 8003ab6: 6078 str r0, [r7, #4] 8003ab8: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 8003aba: 687b ldr r3, [r7, #4] 8003abc: 2b00 cmp r3, #0 8003abe: d101 bne.n 8003ac4 { return HAL_ERROR; 8003ac0: 2301 movs r3, #1 8003ac2: e0a0 b.n 8003c06 } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8003ac4: 687b ldr r3, [r7, #4] 8003ac6: 681b ldr r3, [r3, #0] 8003ac8: f003 0302 and.w r3, r3, #2 8003acc: 2b00 cmp r3, #0 8003ace: d020 beq.n 8003b12 { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8003ad0: 687b ldr r3, [r7, #4] 8003ad2: 681b ldr r3, [r3, #0] 8003ad4: f003 0304 and.w r3, r3, #4 8003ad8: 2b00 cmp r3, #0 8003ada: d005 beq.n 8003ae8 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 8003adc: 4b4c ldr r3, [pc, #304] ; (8003c10 ) 8003ade: 685b ldr r3, [r3, #4] 8003ae0: 4a4b ldr r2, [pc, #300] ; (8003c10 ) 8003ae2: f443 63e0 orr.w r3, r3, #1792 ; 0x700 8003ae6: 6053 str r3, [r2, #4] } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8003ae8: 687b ldr r3, [r7, #4] 8003aea: 681b ldr r3, [r3, #0] 8003aec: f003 0308 and.w r3, r3, #8 8003af0: 2b00 cmp r3, #0 8003af2: d005 beq.n 8003b00 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); 8003af4: 4b46 ldr r3, [pc, #280] ; (8003c10 ) 8003af6: 685b ldr r3, [r3, #4] 8003af8: 4a45 ldr r2, [pc, #276] ; (8003c10 ) 8003afa: f443 5360 orr.w r3, r3, #14336 ; 0x3800 8003afe: 6053 str r3, [r2, #4] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8003b00: 4b43 ldr r3, [pc, #268] ; (8003c10 ) 8003b02: 685b ldr r3, [r3, #4] 8003b04: f023 02f0 bic.w r2, r3, #240 ; 0xf0 8003b08: 687b ldr r3, [r7, #4] 8003b0a: 689b ldr r3, [r3, #8] 8003b0c: 4940 ldr r1, [pc, #256] ; (8003c10 ) 8003b0e: 4313 orrs r3, r2 8003b10: 604b str r3, [r1, #4] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 8003b12: 687b ldr r3, [r7, #4] 8003b14: 681b ldr r3, [r3, #0] 8003b16: f003 0301 and.w r3, r3, #1 8003b1a: 2b00 cmp r3, #0 8003b1c: d040 beq.n 8003ba0 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8003b1e: 687b ldr r3, [r7, #4] 8003b20: 685b ldr r3, [r3, #4] 8003b22: 2b01 cmp r3, #1 8003b24: d107 bne.n 8003b36 { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8003b26: 4b3a ldr r3, [pc, #232] ; (8003c10 ) 8003b28: 681b ldr r3, [r3, #0] 8003b2a: f403 3300 and.w r3, r3, #131072 ; 0x20000 8003b2e: 2b00 cmp r3, #0 8003b30: d115 bne.n 8003b5e { return HAL_ERROR; 8003b32: 2301 movs r3, #1 8003b34: e067 b.n 8003c06 } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 8003b36: 687b ldr r3, [r7, #4] 8003b38: 685b ldr r3, [r3, #4] 8003b3a: 2b02 cmp r3, #2 8003b3c: d107 bne.n 8003b4e { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8003b3e: 4b34 ldr r3, [pc, #208] ; (8003c10 ) 8003b40: 681b ldr r3, [r3, #0] 8003b42: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8003b46: 2b00 cmp r3, #0 8003b48: d109 bne.n 8003b5e { return HAL_ERROR; 8003b4a: 2301 movs r3, #1 8003b4c: e05b b.n 8003c06 } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8003b4e: 4b30 ldr r3, [pc, #192] ; (8003c10 ) 8003b50: 681b ldr r3, [r3, #0] 8003b52: f003 0302 and.w r3, r3, #2 8003b56: 2b00 cmp r3, #0 8003b58: d101 bne.n 8003b5e { return HAL_ERROR; 8003b5a: 2301 movs r3, #1 8003b5c: e053 b.n 8003c06 } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 8003b5e: 4b2c ldr r3, [pc, #176] ; (8003c10 ) 8003b60: 685b ldr r3, [r3, #4] 8003b62: f023 0203 bic.w r2, r3, #3 8003b66: 687b ldr r3, [r7, #4] 8003b68: 685b ldr r3, [r3, #4] 8003b6a: 4929 ldr r1, [pc, #164] ; (8003c10 ) 8003b6c: 4313 orrs r3, r2 8003b6e: 604b str r3, [r1, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); 8003b70: f7fe f92c bl 8001dcc 8003b74: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8003b76: e00a b.n 8003b8e { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8003b78: f7fe f928 bl 8001dcc 8003b7c: 4602 mov r2, r0 8003b7e: 68fb ldr r3, [r7, #12] 8003b80: 1ad3 subs r3, r2, r3 8003b82: f241 3288 movw r2, #5000 ; 0x1388 8003b86: 4293 cmp r3, r2 8003b88: d901 bls.n 8003b8e { return HAL_TIMEOUT; 8003b8a: 2303 movs r3, #3 8003b8c: e03b b.n 8003c06 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8003b8e: 4b20 ldr r3, [pc, #128] ; (8003c10 ) 8003b90: 685b ldr r3, [r3, #4] 8003b92: f003 020c and.w r2, r3, #12 8003b96: 687b ldr r3, [r7, #4] 8003b98: 685b ldr r3, [r3, #4] 8003b9a: 009b lsls r3, r3, #2 8003b9c: 429a cmp r2, r3 8003b9e: d1eb bne.n 8003b78 } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8003ba0: 687b ldr r3, [r7, #4] 8003ba2: 681b ldr r3, [r3, #0] 8003ba4: f003 0304 and.w r3, r3, #4 8003ba8: 2b00 cmp r3, #0 8003baa: d008 beq.n 8003bbe { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 8003bac: 4b18 ldr r3, [pc, #96] ; (8003c10 ) 8003bae: 685b ldr r3, [r3, #4] 8003bb0: f423 62e0 bic.w r2, r3, #1792 ; 0x700 8003bb4: 687b ldr r3, [r7, #4] 8003bb6: 68db ldr r3, [r3, #12] 8003bb8: 4915 ldr r1, [pc, #84] ; (8003c10 ) 8003bba: 4313 orrs r3, r2 8003bbc: 604b str r3, [r1, #4] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8003bbe: 687b ldr r3, [r7, #4] 8003bc0: 681b ldr r3, [r3, #0] 8003bc2: f003 0308 and.w r3, r3, #8 8003bc6: 2b00 cmp r3, #0 8003bc8: d009 beq.n 8003bde { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); 8003bca: 4b11 ldr r3, [pc, #68] ; (8003c10 ) 8003bcc: 685b ldr r3, [r3, #4] 8003bce: f423 5260 bic.w r2, r3, #14336 ; 0x3800 8003bd2: 687b ldr r3, [r7, #4] 8003bd4: 691b ldr r3, [r3, #16] 8003bd6: 00db lsls r3, r3, #3 8003bd8: 490d ldr r1, [pc, #52] ; (8003c10 ) 8003bda: 4313 orrs r3, r2 8003bdc: 604b str r3, [r1, #4] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; 8003bde: f000 f81f bl 8003c20 8003be2: 4601 mov r1, r0 8003be4: 4b0a ldr r3, [pc, #40] ; (8003c10 ) 8003be6: 685b ldr r3, [r3, #4] 8003be8: 091b lsrs r3, r3, #4 8003bea: f003 030f and.w r3, r3, #15 8003bee: 4a09 ldr r2, [pc, #36] ; (8003c14 ) 8003bf0: 5cd3 ldrb r3, [r2, r3] 8003bf2: fa21 f303 lsr.w r3, r1, r3 8003bf6: 4a08 ldr r2, [pc, #32] ; (8003c18 ) 8003bf8: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick(uwTickPrio); 8003bfa: 4b08 ldr r3, [pc, #32] ; (8003c1c ) 8003bfc: 681b ldr r3, [r3, #0] 8003bfe: 4618 mov r0, r3 8003c00: f002 f876 bl 8005cf0 return HAL_OK; 8003c04: 2300 movs r3, #0 } 8003c06: 4618 mov r0, r3 8003c08: 3710 adds r7, #16 8003c0a: 46bd mov sp, r7 8003c0c: bd80 pop {r7, pc} 8003c0e: bf00 nop 8003c10: 40021000 .word 0x40021000 8003c14: 08008cec .word 0x08008cec 8003c18: 20000008 .word 0x20000008 8003c1c: 20000000 .word 0x20000000 08003c20 : * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 8003c20: b490 push {r4, r7} 8003c22: b08e sub sp, #56 ; 0x38 8003c24: af00 add r7, sp, #0 #if defined(RCC_CFGR2_PREDIV1SRC) const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13}; const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; #else const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; 8003c26: 4b2b ldr r3, [pc, #172] ; (8003cd4 ) 8003c28: f107 0414 add.w r4, r7, #20 8003c2c: cb0f ldmia r3, {r0, r1, r2, r3} 8003c2e: e884 000f stmia.w r4, {r0, r1, r2, r3} #if defined(RCC_CFGR2_PREDIV1) const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; 8003c32: 4b29 ldr r3, [pc, #164] ; (8003cd8 ) 8003c34: 1d3c adds r4, r7, #4 8003c36: cb0f ldmia r3, {r0, r1, r2, r3} 8003c38: e884 000f stmia.w r4, {r0, r1, r2, r3} #else const uint8_t aPredivFactorTable[2] = {1, 2}; #endif /*RCC_CFGR2_PREDIV1*/ #endif uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; 8003c3c: 2300 movs r3, #0 8003c3e: 62fb str r3, [r7, #44] ; 0x2c 8003c40: 2300 movs r3, #0 8003c42: 62bb str r3, [r7, #40] ; 0x28 8003c44: 2300 movs r3, #0 8003c46: 637b str r3, [r7, #52] ; 0x34 8003c48: 2300 movs r3, #0 8003c4a: 627b str r3, [r7, #36] ; 0x24 uint32_t sysclockfreq = 0U; 8003c4c: 2300 movs r3, #0 8003c4e: 633b str r3, [r7, #48] ; 0x30 #if defined(RCC_CFGR2_PREDIV1SRC) uint32_t prediv2 = 0U, pll2mul = 0U; #endif /*RCC_CFGR2_PREDIV1SRC*/ tmpreg = RCC->CFGR; 8003c50: 4b22 ldr r3, [pc, #136] ; (8003cdc ) 8003c52: 685b ldr r3, [r3, #4] 8003c54: 62fb str r3, [r7, #44] ; 0x2c /* Get SYSCLK source -------------------------------------------------------*/ switch (tmpreg & RCC_CFGR_SWS) 8003c56: 6afb ldr r3, [r7, #44] ; 0x2c 8003c58: f003 030c and.w r3, r3, #12 8003c5c: 2b04 cmp r3, #4 8003c5e: d002 beq.n 8003c66 8003c60: 2b08 cmp r3, #8 8003c62: d003 beq.n 8003c6c 8003c64: e02c b.n 8003cc0 { case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ { sysclockfreq = HSE_VALUE; 8003c66: 4b1e ldr r3, [pc, #120] ; (8003ce0 ) 8003c68: 633b str r3, [r7, #48] ; 0x30 break; 8003c6a: e02c b.n 8003cc6 } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ { pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; 8003c6c: 6afb ldr r3, [r7, #44] ; 0x2c 8003c6e: 0c9b lsrs r3, r3, #18 8003c70: f003 030f and.w r3, r3, #15 8003c74: f107 0238 add.w r2, r7, #56 ; 0x38 8003c78: 4413 add r3, r2 8003c7a: f813 3c24 ldrb.w r3, [r3, #-36] 8003c7e: 627b str r3, [r7, #36] ; 0x24 if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) 8003c80: 6afb ldr r3, [r7, #44] ; 0x2c 8003c82: f403 3380 and.w r3, r3, #65536 ; 0x10000 8003c86: 2b00 cmp r3, #0 8003c88: d012 beq.n 8003cb0 { #if defined(RCC_CFGR2_PREDIV1) prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; 8003c8a: 4b14 ldr r3, [pc, #80] ; (8003cdc ) 8003c8c: 6adb ldr r3, [r3, #44] ; 0x2c 8003c8e: f003 030f and.w r3, r3, #15 8003c92: f107 0238 add.w r2, r7, #56 ; 0x38 8003c96: 4413 add r3, r2 8003c98: f813 3c34 ldrb.w r3, [r3, #-52] 8003c9c: 62bb str r3, [r7, #40] ; 0x28 { pllclk = pllclk / 2; } #else /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv); 8003c9e: 6a7b ldr r3, [r7, #36] ; 0x24 8003ca0: 4a0f ldr r2, [pc, #60] ; (8003ce0 ) 8003ca2: fb02 f203 mul.w r2, r2, r3 8003ca6: 6abb ldr r3, [r7, #40] ; 0x28 8003ca8: fbb2 f3f3 udiv r3, r2, r3 8003cac: 637b str r3, [r7, #52] ; 0x34 8003cae: e004 b.n 8003cba #endif /*RCC_CFGR2_PREDIV1SRC*/ } else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); 8003cb0: 6a7b ldr r3, [r7, #36] ; 0x24 8003cb2: 4a0c ldr r2, [pc, #48] ; (8003ce4 ) 8003cb4: fb02 f303 mul.w r3, r2, r3 8003cb8: 637b str r3, [r7, #52] ; 0x34 } sysclockfreq = pllclk; 8003cba: 6b7b ldr r3, [r7, #52] ; 0x34 8003cbc: 633b str r3, [r7, #48] ; 0x30 break; 8003cbe: e002 b.n 8003cc6 } case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ default: /* HSI used as system clock */ { sysclockfreq = HSI_VALUE; 8003cc0: 4b07 ldr r3, [pc, #28] ; (8003ce0 ) 8003cc2: 633b str r3, [r7, #48] ; 0x30 break; 8003cc4: bf00 nop } } return sysclockfreq; 8003cc6: 6b3b ldr r3, [r7, #48] ; 0x30 } 8003cc8: 4618 mov r0, r3 8003cca: 3738 adds r7, #56 ; 0x38 8003ccc: 46bd mov sp, r7 8003cce: bc90 pop {r4, r7} 8003cd0: 4770 bx lr 8003cd2: bf00 nop 8003cd4: 08008c40 .word 0x08008c40 8003cd8: 08008c50 .word 0x08008c50 8003cdc: 40021000 .word 0x40021000 8003ce0: 007a1200 .word 0x007a1200 8003ce4: 003d0900 .word 0x003d0900 08003ce8 : * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 8003ce8: b480 push {r7} 8003cea: af00 add r7, sp, #0 return SystemCoreClock; 8003cec: 4b02 ldr r3, [pc, #8] ; (8003cf8 ) 8003cee: 681b ldr r3, [r3, #0] } 8003cf0: 4618 mov r0, r3 8003cf2: 46bd mov sp, r7 8003cf4: bc80 pop {r7} 8003cf6: 4770 bx lr 8003cf8: 20000008 .word 0x20000008 08003cfc : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 8003cfc: b580 push {r7, lr} 8003cfe: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); 8003d00: f7ff fff2 bl 8003ce8 8003d04: 4601 mov r1, r0 8003d06: 4b05 ldr r3, [pc, #20] ; (8003d1c ) 8003d08: 685b ldr r3, [r3, #4] 8003d0a: 0a1b lsrs r3, r3, #8 8003d0c: f003 0307 and.w r3, r3, #7 8003d10: 4a03 ldr r2, [pc, #12] ; (8003d20 ) 8003d12: 5cd3 ldrb r3, [r2, r3] 8003d14: fa21 f303 lsr.w r3, r1, r3 } 8003d18: 4618 mov r0, r3 8003d1a: bd80 pop {r7, pc} 8003d1c: 40021000 .word 0x40021000 8003d20: 08008cfc .word 0x08008cfc 08003d24 : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 8003d24: b580 push {r7, lr} 8003d26: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); 8003d28: f7ff ffde bl 8003ce8 8003d2c: 4601 mov r1, r0 8003d2e: 4b05 ldr r3, [pc, #20] ; (8003d44 ) 8003d30: 685b ldr r3, [r3, #4] 8003d32: 0adb lsrs r3, r3, #11 8003d34: f003 0307 and.w r3, r3, #7 8003d38: 4a03 ldr r2, [pc, #12] ; (8003d48 ) 8003d3a: 5cd3 ldrb r3, [r2, r3] 8003d3c: fa21 f303 lsr.w r3, r1, r3 } 8003d40: 4618 mov r0, r3 8003d42: bd80 pop {r7, pc} 8003d44: 40021000 .word 0x40021000 8003d48: 08008cfc .word 0x08008cfc 08003d4c : * contains the current clock configuration. * @param pFLatency Pointer on the Flash Latency. * @retval None */ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) { 8003d4c: b480 push {r7} 8003d4e: b083 sub sp, #12 8003d50: af00 add r7, sp, #0 8003d52: 6078 str r0, [r7, #4] 8003d54: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(RCC_ClkInitStruct != NULL); assert_param(pFLatency != NULL); /* Set all possible values for the Clock type parameter --------------------*/ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; 8003d56: 687b ldr r3, [r7, #4] 8003d58: 220f movs r2, #15 8003d5a: 601a str r2, [r3, #0] /* Get the SYSCLK configuration --------------------------------------------*/ RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); 8003d5c: 4b10 ldr r3, [pc, #64] ; (8003da0 ) 8003d5e: 685b ldr r3, [r3, #4] 8003d60: f003 0203 and.w r2, r3, #3 8003d64: 687b ldr r3, [r7, #4] 8003d66: 605a str r2, [r3, #4] /* Get the HCLK configuration ----------------------------------------------*/ RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); 8003d68: 4b0d ldr r3, [pc, #52] ; (8003da0 ) 8003d6a: 685b ldr r3, [r3, #4] 8003d6c: f003 02f0 and.w r2, r3, #240 ; 0xf0 8003d70: 687b ldr r3, [r7, #4] 8003d72: 609a str r2, [r3, #8] /* Get the APB1 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); 8003d74: 4b0a ldr r3, [pc, #40] ; (8003da0 ) 8003d76: 685b ldr r3, [r3, #4] 8003d78: f403 62e0 and.w r2, r3, #1792 ; 0x700 8003d7c: 687b ldr r3, [r7, #4] 8003d7e: 60da str r2, [r3, #12] /* Get the APB2 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3); 8003d80: 4b07 ldr r3, [pc, #28] ; (8003da0 ) 8003d82: 685b ldr r3, [r3, #4] 8003d84: 08db lsrs r3, r3, #3 8003d86: f403 62e0 and.w r2, r3, #1792 ; 0x700 8003d8a: 687b ldr r3, [r7, #4] 8003d8c: 611a str r2, [r3, #16] #if defined(FLASH_ACR_LATENCY) /* Get the Flash Wait State (Latency) configuration ------------------------*/ *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); #else /* For VALUE lines devices, only LATENCY_0 can be set*/ *pFLatency = (uint32_t)FLASH_LATENCY_0; 8003d8e: 683b ldr r3, [r7, #0] 8003d90: 2200 movs r2, #0 8003d92: 601a str r2, [r3, #0] #endif } 8003d94: bf00 nop 8003d96: 370c adds r7, #12 8003d98: 46bd mov sp, r7 8003d9a: bc80 pop {r7} 8003d9c: 4770 bx lr 8003d9e: bf00 nop 8003da0: 40021000 .word 0x40021000 08003da4 : * @brief This function provides delay (in milliseconds) based on CPU cycles method. * @param mdelay: specifies the delay time length, in milliseconds. * @retval None */ static void RCC_Delay(uint32_t mdelay) { 8003da4: b480 push {r7} 8003da6: b085 sub sp, #20 8003da8: af00 add r7, sp, #0 8003daa: 6078 str r0, [r7, #4] __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U); 8003dac: 4b0a ldr r3, [pc, #40] ; (8003dd8 ) 8003dae: 681b ldr r3, [r3, #0] 8003db0: 4a0a ldr r2, [pc, #40] ; (8003ddc ) 8003db2: fba2 2303 umull r2, r3, r2, r3 8003db6: 0a5b lsrs r3, r3, #9 8003db8: 687a ldr r2, [r7, #4] 8003dba: fb02 f303 mul.w r3, r2, r3 8003dbe: 60fb str r3, [r7, #12] do { __NOP(); 8003dc0: bf00 nop } while (Delay --); 8003dc2: 68fb ldr r3, [r7, #12] 8003dc4: 1e5a subs r2, r3, #1 8003dc6: 60fa str r2, [r7, #12] 8003dc8: 2b00 cmp r3, #0 8003dca: d1f9 bne.n 8003dc0 } 8003dcc: bf00 nop 8003dce: 3714 adds r7, #20 8003dd0: 46bd mov sp, r7 8003dd2: bc80 pop {r7} 8003dd4: 4770 bx lr 8003dd6: bf00 nop 8003dd8: 20000008 .word 0x20000008 8003ddc: 10624dd3 .word 0x10624dd3 08003de0 : * manually disable it. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 8003de0: b580 push {r7, lr} 8003de2: b086 sub sp, #24 8003de4: af00 add r7, sp, #0 8003de6: 6078 str r0, [r7, #4] uint32_t tickstart = 0U, temp_reg = 0U; 8003de8: 2300 movs r3, #0 8003dea: 613b str r3, [r7, #16] 8003dec: 2300 movs r3, #0 8003dee: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*------------------------------- RTC/LCD Configuration ------------------------*/ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 8003df0: 687b ldr r3, [r7, #4] 8003df2: 681b ldr r3, [r3, #0] 8003df4: f003 0301 and.w r3, r3, #1 8003df8: 2b00 cmp r3, #0 8003dfa: d07d beq.n 8003ef8 { /* check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); FlagStatus pwrclkchanged = RESET; 8003dfc: 2300 movs r3, #0 8003dfe: 75fb strb r3, [r7, #23] /* As soon as function is called to change RTC clock source, activation of the power domain is done. */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 8003e00: 4b47 ldr r3, [pc, #284] ; (8003f20 ) 8003e02: 69db ldr r3, [r3, #28] 8003e04: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8003e08: 2b00 cmp r3, #0 8003e0a: d10d bne.n 8003e28 { __HAL_RCC_PWR_CLK_ENABLE(); 8003e0c: 4b44 ldr r3, [pc, #272] ; (8003f20 ) 8003e0e: 69db ldr r3, [r3, #28] 8003e10: 4a43 ldr r2, [pc, #268] ; (8003f20 ) 8003e12: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8003e16: 61d3 str r3, [r2, #28] 8003e18: 4b41 ldr r3, [pc, #260] ; (8003f20 ) 8003e1a: 69db ldr r3, [r3, #28] 8003e1c: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8003e20: 60bb str r3, [r7, #8] 8003e22: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 8003e24: 2301 movs r3, #1 8003e26: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8003e28: 4b3e ldr r3, [pc, #248] ; (8003f24 ) 8003e2a: 681b ldr r3, [r3, #0] 8003e2c: f403 7380 and.w r3, r3, #256 ; 0x100 8003e30: 2b00 cmp r3, #0 8003e32: d118 bne.n 8003e66 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8003e34: 4b3b ldr r3, [pc, #236] ; (8003f24 ) 8003e36: 681b ldr r3, [r3, #0] 8003e38: 4a3a ldr r2, [pc, #232] ; (8003f24 ) 8003e3a: f443 7380 orr.w r3, r3, #256 ; 0x100 8003e3e: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8003e40: f7fd ffc4 bl 8001dcc 8003e44: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8003e46: e008 b.n 8003e5a { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8003e48: f7fd ffc0 bl 8001dcc 8003e4c: 4602 mov r2, r0 8003e4e: 693b ldr r3, [r7, #16] 8003e50: 1ad3 subs r3, r2, r3 8003e52: 2b64 cmp r3, #100 ; 0x64 8003e54: d901 bls.n 8003e5a { return HAL_TIMEOUT; 8003e56: 2303 movs r3, #3 8003e58: e05e b.n 8003f18 while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8003e5a: 4b32 ldr r3, [pc, #200] ; (8003f24 ) 8003e5c: 681b ldr r3, [r3, #0] 8003e5e: f403 7380 and.w r3, r3, #256 ; 0x100 8003e62: 2b00 cmp r3, #0 8003e64: d0f0 beq.n 8003e48 } } } /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); 8003e66: 4b2e ldr r3, [pc, #184] ; (8003f20 ) 8003e68: 6a1b ldr r3, [r3, #32] 8003e6a: f403 7340 and.w r3, r3, #768 ; 0x300 8003e6e: 60fb str r3, [r7, #12] if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) 8003e70: 68fb ldr r3, [r7, #12] 8003e72: 2b00 cmp r3, #0 8003e74: d02e beq.n 8003ed4 8003e76: 687b ldr r3, [r7, #4] 8003e78: 685b ldr r3, [r3, #4] 8003e7a: f403 7340 and.w r3, r3, #768 ; 0x300 8003e7e: 68fa ldr r2, [r7, #12] 8003e80: 429a cmp r2, r3 8003e82: d027 beq.n 8003ed4 { /* Store the content of BDCR register before the reset of Backup Domain */ temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 8003e84: 4b26 ldr r3, [pc, #152] ; (8003f20 ) 8003e86: 6a1b ldr r3, [r3, #32] 8003e88: f423 7340 bic.w r3, r3, #768 ; 0x300 8003e8c: 60fb str r3, [r7, #12] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 8003e8e: 4b26 ldr r3, [pc, #152] ; (8003f28 ) 8003e90: 2201 movs r2, #1 8003e92: 601a str r2, [r3, #0] __HAL_RCC_BACKUPRESET_RELEASE(); 8003e94: 4b24 ldr r3, [pc, #144] ; (8003f28 ) 8003e96: 2200 movs r2, #0 8003e98: 601a str r2, [r3, #0] /* Restore the Content of BDCR register */ RCC->BDCR = temp_reg; 8003e9a: 4a21 ldr r2, [pc, #132] ; (8003f20 ) 8003e9c: 68fb ldr r3, [r7, #12] 8003e9e: 6213 str r3, [r2, #32] /* Wait for LSERDY if LSE was enabled */ if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) 8003ea0: 68fb ldr r3, [r7, #12] 8003ea2: f003 0301 and.w r3, r3, #1 8003ea6: 2b00 cmp r3, #0 8003ea8: d014 beq.n 8003ed4 { /* Get Start Tick */ tickstart = HAL_GetTick(); 8003eaa: f7fd ff8f bl 8001dcc 8003eae: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8003eb0: e00a b.n 8003ec8 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8003eb2: f7fd ff8b bl 8001dcc 8003eb6: 4602 mov r2, r0 8003eb8: 693b ldr r3, [r7, #16] 8003eba: 1ad3 subs r3, r2, r3 8003ebc: f241 3288 movw r2, #5000 ; 0x1388 8003ec0: 4293 cmp r3, r2 8003ec2: d901 bls.n 8003ec8 { return HAL_TIMEOUT; 8003ec4: 2303 movs r3, #3 8003ec6: e027 b.n 8003f18 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8003ec8: 4b15 ldr r3, [pc, #84] ; (8003f20 ) 8003eca: 6a1b ldr r3, [r3, #32] 8003ecc: f003 0302 and.w r3, r3, #2 8003ed0: 2b00 cmp r3, #0 8003ed2: d0ee beq.n 8003eb2 } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 8003ed4: 4b12 ldr r3, [pc, #72] ; (8003f20 ) 8003ed6: 6a1b ldr r3, [r3, #32] 8003ed8: f423 7240 bic.w r2, r3, #768 ; 0x300 8003edc: 687b ldr r3, [r7, #4] 8003ede: 685b ldr r3, [r3, #4] 8003ee0: 490f ldr r1, [pc, #60] ; (8003f20 ) 8003ee2: 4313 orrs r3, r2 8003ee4: 620b str r3, [r1, #32] /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 8003ee6: 7dfb ldrb r3, [r7, #23] 8003ee8: 2b01 cmp r3, #1 8003eea: d105 bne.n 8003ef8 { __HAL_RCC_PWR_CLK_DISABLE(); 8003eec: 4b0c ldr r3, [pc, #48] ; (8003f20 ) 8003eee: 69db ldr r3, [r3, #28] 8003ef0: 4a0b ldr r2, [pc, #44] ; (8003f20 ) 8003ef2: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 8003ef6: 61d3 str r3, [r2, #28] } } /*------------------------------ ADC clock Configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 8003ef8: 687b ldr r3, [r7, #4] 8003efa: 681b ldr r3, [r3, #0] 8003efc: f003 0302 and.w r3, r3, #2 8003f00: 2b00 cmp r3, #0 8003f02: d008 beq.n 8003f16 { /* Check the parameters */ assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection)); /* Configure the ADC clock source */ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 8003f04: 4b06 ldr r3, [pc, #24] ; (8003f20 ) 8003f06: 685b ldr r3, [r3, #4] 8003f08: f423 4240 bic.w r2, r3, #49152 ; 0xc000 8003f0c: 687b ldr r3, [r7, #4] 8003f0e: 689b ldr r3, [r3, #8] 8003f10: 4903 ldr r1, [pc, #12] ; (8003f20 ) 8003f12: 4313 orrs r3, r2 8003f14: 604b str r3, [r1, #4] /* Configure the USB clock source */ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); } #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ return HAL_OK; 8003f16: 2300 movs r3, #0 } 8003f18: 4618 mov r0, r3 8003f1a: 3718 adds r7, #24 8003f1c: 46bd mov sp, r7 8003f1e: bd80 pop {r7, pc} 8003f20: 40021000 .word 0x40021000 8003f24: 40007000 .word 0x40007000 8003f28: 42420440 .word 0x42420440 08003f2c : * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock @endif * @retval Frequency in Hz (0: means that no available frequency for the peripheral) */ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { 8003f2c: b580 push {r7, lr} 8003f2e: b084 sub sp, #16 8003f30: af00 add r7, sp, #0 8003f32: 6078 str r0, [r7, #4] const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; const uint8_t aPredivFactorTable[2] = {1, 2}; uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ uint32_t temp_reg = 0U, frequency = 0U; 8003f34: 2300 movs r3, #0 8003f36: 60bb str r3, [r7, #8] 8003f38: 2300 movs r3, #0 8003f3a: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); switch (PeriphClk) 8003f3c: 687b ldr r3, [r7, #4] 8003f3e: 2b01 cmp r3, #1 8003f40: d002 beq.n 8003f48 8003f42: 2b02 cmp r3, #2 8003f44: d033 beq.n 8003fae frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2); break; } default: { break; 8003f46: e041 b.n 8003fcc temp_reg = RCC->BDCR; 8003f48: 4b23 ldr r3, [pc, #140] ; (8003fd8 ) 8003f4a: 6a1b ldr r3, [r3, #32] 8003f4c: 60bb str r3, [r7, #8] if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY))) 8003f4e: 68bb ldr r3, [r7, #8] 8003f50: f403 7340 and.w r3, r3, #768 ; 0x300 8003f54: f5b3 7f80 cmp.w r3, #256 ; 0x100 8003f58: d108 bne.n 8003f6c 8003f5a: 68bb ldr r3, [r7, #8] 8003f5c: f003 0302 and.w r3, r3, #2 8003f60: 2b00 cmp r3, #0 8003f62: d003 beq.n 8003f6c frequency = LSE_VALUE; 8003f64: f44f 4300 mov.w r3, #32768 ; 0x8000 8003f68: 60fb str r3, [r7, #12] 8003f6a: e01f b.n 8003fac else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) 8003f6c: 68bb ldr r3, [r7, #8] 8003f6e: f403 7340 and.w r3, r3, #768 ; 0x300 8003f72: f5b3 7f00 cmp.w r3, #512 ; 0x200 8003f76: d109 bne.n 8003f8c 8003f78: 4b17 ldr r3, [pc, #92] ; (8003fd8 ) 8003f7a: 6a5b ldr r3, [r3, #36] ; 0x24 8003f7c: f003 0302 and.w r3, r3, #2 8003f80: 2b00 cmp r3, #0 8003f82: d003 beq.n 8003f8c frequency = LSI_VALUE; 8003f84: f649 4340 movw r3, #40000 ; 0x9c40 8003f88: 60fb str r3, [r7, #12] 8003f8a: e00f b.n 8003fac else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) 8003f8c: 68bb ldr r3, [r7, #8] 8003f8e: f403 7340 and.w r3, r3, #768 ; 0x300 8003f92: f5b3 7f40 cmp.w r3, #768 ; 0x300 8003f96: d118 bne.n 8003fca 8003f98: 4b0f ldr r3, [pc, #60] ; (8003fd8 ) 8003f9a: 681b ldr r3, [r3, #0] 8003f9c: f403 3300 and.w r3, r3, #131072 ; 0x20000 8003fa0: 2b00 cmp r3, #0 8003fa2: d012 beq.n 8003fca frequency = HSE_VALUE / 128U; 8003fa4: f24f 4324 movw r3, #62500 ; 0xf424 8003fa8: 60fb str r3, [r7, #12] break; 8003faa: e00e b.n 8003fca 8003fac: e00d b.n 8003fca frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2); 8003fae: f7ff feb9 bl 8003d24 8003fb2: 4602 mov r2, r0 8003fb4: 4b08 ldr r3, [pc, #32] ; (8003fd8 ) 8003fb6: 685b ldr r3, [r3, #4] 8003fb8: 0b9b lsrs r3, r3, #14 8003fba: f003 0303 and.w r3, r3, #3 8003fbe: 3301 adds r3, #1 8003fc0: 005b lsls r3, r3, #1 8003fc2: fbb2 f3f3 udiv r3, r2, r3 8003fc6: 60fb str r3, [r7, #12] break; 8003fc8: e000 b.n 8003fcc break; 8003fca: bf00 nop } } return (frequency); 8003fcc: 68fb ldr r3, [r7, #12] } 8003fce: 4618 mov r0, r3 8003fd0: 3710 adds r7, #16 8003fd2: 46bd mov sp, r7 8003fd4: bd80 pop {r7, pc} 8003fd6: bf00 nop 8003fd8: 40021000 .word 0x40021000 08003fdc : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { 8003fdc: b580 push {r7, lr} 8003fde: b082 sub sp, #8 8003fe0: af00 add r7, sp, #0 8003fe2: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8003fe4: 687b ldr r3, [r7, #4] 8003fe6: 2b00 cmp r3, #0 8003fe8: d101 bne.n 8003fee { return HAL_ERROR; 8003fea: 2301 movs r3, #1 8003fec: e01d b.n 800402a assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8003fee: 687b ldr r3, [r7, #4] 8003ff0: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 8003ff4: b2db uxtb r3, r3 8003ff6: 2b00 cmp r3, #0 8003ff8: d106 bne.n 8004008 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8003ffa: 687b ldr r3, [r7, #4] 8003ffc: 2200 movs r2, #0 8003ffe: f883 203c strb.w r2, [r3, #60] ; 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); 8004002: 6878 ldr r0, [r7, #4] 8004004: f001 fd26 bl 8005a54 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8004008: 687b ldr r3, [r7, #4] 800400a: 2202 movs r2, #2 800400c: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8004010: 687b ldr r3, [r7, #4] 8004012: 681a ldr r2, [r3, #0] 8004014: 687b ldr r3, [r7, #4] 8004016: 3304 adds r3, #4 8004018: 4619 mov r1, r3 800401a: 4610 mov r0, r2 800401c: f000 f958 bl 80042d0 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8004020: 687b ldr r3, [r7, #4] 8004022: 2201 movs r2, #1 8004024: f883 203d strb.w r2, [r3, #61] ; 0x3d return HAL_OK; 8004028: 2300 movs r3, #0 } 800402a: 4618 mov r0, r3 800402c: 3708 adds r7, #8 800402e: 46bd mov sp, r7 8004030: bd80 pop {r7, pc} 08004032 : * @brief Starts the TIM Base generation in interrupt mode. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) { 8004032: b480 push {r7} 8004034: b085 sub sp, #20 8004036: af00 add r7, sp, #0 8004038: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Enable the TIM Update interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); 800403a: 687b ldr r3, [r7, #4] 800403c: 681b ldr r3, [r3, #0] 800403e: 68da ldr r2, [r3, #12] 8004040: 687b ldr r3, [r7, #4] 8004042: 681b ldr r3, [r3, #0] 8004044: f042 0201 orr.w r2, r2, #1 8004048: 60da str r2, [r3, #12] /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 800404a: 687b ldr r3, [r7, #4] 800404c: 681b ldr r3, [r3, #0] 800404e: 689b ldr r3, [r3, #8] 8004050: f003 0307 and.w r3, r3, #7 8004054: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8004056: 68fb ldr r3, [r7, #12] 8004058: 2b06 cmp r3, #6 800405a: d007 beq.n 800406c { __HAL_TIM_ENABLE(htim); 800405c: 687b ldr r3, [r7, #4] 800405e: 681b ldr r3, [r3, #0] 8004060: 681a ldr r2, [r3, #0] 8004062: 687b ldr r3, [r7, #4] 8004064: 681b ldr r3, [r3, #0] 8004066: f042 0201 orr.w r2, r2, #1 800406a: 601a str r2, [r3, #0] } /* Return function status */ return HAL_OK; 800406c: 2300 movs r3, #0 } 800406e: 4618 mov r0, r3 8004070: 3714 adds r7, #20 8004072: 46bd mov sp, r7 8004074: bc80 pop {r7} 8004076: 4770 bx lr 08004078 : * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { 8004078: b580 push {r7, lr} 800407a: b082 sub sp, #8 800407c: af00 add r7, sp, #0 800407e: 6078 str r0, [r7, #4] /* Capture compare 1 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) 8004080: 687b ldr r3, [r7, #4] 8004082: 681b ldr r3, [r3, #0] 8004084: 691b ldr r3, [r3, #16] 8004086: f003 0302 and.w r3, r3, #2 800408a: 2b02 cmp r3, #2 800408c: d122 bne.n 80040d4 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) 800408e: 687b ldr r3, [r7, #4] 8004090: 681b ldr r3, [r3, #0] 8004092: 68db ldr r3, [r3, #12] 8004094: f003 0302 and.w r3, r3, #2 8004098: 2b02 cmp r3, #2 800409a: d11b bne.n 80040d4 { { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); 800409c: 687b ldr r3, [r7, #4] 800409e: 681b ldr r3, [r3, #0] 80040a0: f06f 0202 mvn.w r2, #2 80040a4: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 80040a6: 687b ldr r3, [r7, #4] 80040a8: 2201 movs r2, #1 80040aa: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 80040ac: 687b ldr r3, [r7, #4] 80040ae: 681b ldr r3, [r3, #0] 80040b0: 699b ldr r3, [r3, #24] 80040b2: f003 0303 and.w r3, r3, #3 80040b6: 2b00 cmp r3, #0 80040b8: d003 beq.n 80040c2 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 80040ba: 6878 ldr r0, [r7, #4] 80040bc: f000 f8ed bl 800429a 80040c0: e005 b.n 80040ce { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 80040c2: 6878 ldr r0, [r7, #4] 80040c4: f000 f8e0 bl 8004288 HAL_TIM_PWM_PulseFinishedCallback(htim); 80040c8: 6878 ldr r0, [r7, #4] 80040ca: f000 f8ef bl 80042ac #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 80040ce: 687b ldr r3, [r7, #4] 80040d0: 2200 movs r2, #0 80040d2: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) 80040d4: 687b ldr r3, [r7, #4] 80040d6: 681b ldr r3, [r3, #0] 80040d8: 691b ldr r3, [r3, #16] 80040da: f003 0304 and.w r3, r3, #4 80040de: 2b04 cmp r3, #4 80040e0: d122 bne.n 8004128 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) 80040e2: 687b ldr r3, [r7, #4] 80040e4: 681b ldr r3, [r3, #0] 80040e6: 68db ldr r3, [r3, #12] 80040e8: f003 0304 and.w r3, r3, #4 80040ec: 2b04 cmp r3, #4 80040ee: d11b bne.n 8004128 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); 80040f0: 687b ldr r3, [r7, #4] 80040f2: 681b ldr r3, [r3, #0] 80040f4: f06f 0204 mvn.w r2, #4 80040f8: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 80040fa: 687b ldr r3, [r7, #4] 80040fc: 2202 movs r2, #2 80040fe: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 8004100: 687b ldr r3, [r7, #4] 8004102: 681b ldr r3, [r3, #0] 8004104: 699b ldr r3, [r3, #24] 8004106: f403 7340 and.w r3, r3, #768 ; 0x300 800410a: 2b00 cmp r3, #0 800410c: d003 beq.n 8004116 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800410e: 6878 ldr r0, [r7, #4] 8004110: f000 f8c3 bl 800429a 8004114: e005 b.n 8004122 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8004116: 6878 ldr r0, [r7, #4] 8004118: f000 f8b6 bl 8004288 HAL_TIM_PWM_PulseFinishedCallback(htim); 800411c: 6878 ldr r0, [r7, #4] 800411e: f000 f8c5 bl 80042ac #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8004122: 687b ldr r3, [r7, #4] 8004124: 2200 movs r2, #0 8004126: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) 8004128: 687b ldr r3, [r7, #4] 800412a: 681b ldr r3, [r3, #0] 800412c: 691b ldr r3, [r3, #16] 800412e: f003 0308 and.w r3, r3, #8 8004132: 2b08 cmp r3, #8 8004134: d122 bne.n 800417c { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) 8004136: 687b ldr r3, [r7, #4] 8004138: 681b ldr r3, [r3, #0] 800413a: 68db ldr r3, [r3, #12] 800413c: f003 0308 and.w r3, r3, #8 8004140: 2b08 cmp r3, #8 8004142: d11b bne.n 800417c { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); 8004144: 687b ldr r3, [r7, #4] 8004146: 681b ldr r3, [r3, #0] 8004148: f06f 0208 mvn.w r2, #8 800414c: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 800414e: 687b ldr r3, [r7, #4] 8004150: 2204 movs r2, #4 8004152: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 8004154: 687b ldr r3, [r7, #4] 8004156: 681b ldr r3, [r3, #0] 8004158: 69db ldr r3, [r3, #28] 800415a: f003 0303 and.w r3, r3, #3 800415e: 2b00 cmp r3, #0 8004160: d003 beq.n 800416a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8004162: 6878 ldr r0, [r7, #4] 8004164: f000 f899 bl 800429a 8004168: e005 b.n 8004176 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800416a: 6878 ldr r0, [r7, #4] 800416c: f000 f88c bl 8004288 HAL_TIM_PWM_PulseFinishedCallback(htim); 8004170: 6878 ldr r0, [r7, #4] 8004172: f000 f89b bl 80042ac #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8004176: 687b ldr r3, [r7, #4] 8004178: 2200 movs r2, #0 800417a: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) 800417c: 687b ldr r3, [r7, #4] 800417e: 681b ldr r3, [r3, #0] 8004180: 691b ldr r3, [r3, #16] 8004182: f003 0310 and.w r3, r3, #16 8004186: 2b10 cmp r3, #16 8004188: d122 bne.n 80041d0 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) 800418a: 687b ldr r3, [r7, #4] 800418c: 681b ldr r3, [r3, #0] 800418e: 68db ldr r3, [r3, #12] 8004190: f003 0310 and.w r3, r3, #16 8004194: 2b10 cmp r3, #16 8004196: d11b bne.n 80041d0 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); 8004198: 687b ldr r3, [r7, #4] 800419a: 681b ldr r3, [r3, #0] 800419c: f06f 0210 mvn.w r2, #16 80041a0: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 80041a2: 687b ldr r3, [r7, #4] 80041a4: 2208 movs r2, #8 80041a6: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 80041a8: 687b ldr r3, [r7, #4] 80041aa: 681b ldr r3, [r3, #0] 80041ac: 69db ldr r3, [r3, #28] 80041ae: f403 7340 and.w r3, r3, #768 ; 0x300 80041b2: 2b00 cmp r3, #0 80041b4: d003 beq.n 80041be { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 80041b6: 6878 ldr r0, [r7, #4] 80041b8: f000 f86f bl 800429a 80041bc: e005 b.n 80041ca { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 80041be: 6878 ldr r0, [r7, #4] 80041c0: f000 f862 bl 8004288 HAL_TIM_PWM_PulseFinishedCallback(htim); 80041c4: 6878 ldr r0, [r7, #4] 80041c6: f000 f871 bl 80042ac #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 80041ca: 687b ldr r3, [r7, #4] 80041cc: 2200 movs r2, #0 80041ce: 771a strb r2, [r3, #28] } } /* TIM Update event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) 80041d0: 687b ldr r3, [r7, #4] 80041d2: 681b ldr r3, [r3, #0] 80041d4: 691b ldr r3, [r3, #16] 80041d6: f003 0301 and.w r3, r3, #1 80041da: 2b01 cmp r3, #1 80041dc: d10e bne.n 80041fc { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) 80041de: 687b ldr r3, [r7, #4] 80041e0: 681b ldr r3, [r3, #0] 80041e2: 68db ldr r3, [r3, #12] 80041e4: f003 0301 and.w r3, r3, #1 80041e8: 2b01 cmp r3, #1 80041ea: d107 bne.n 80041fc { __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); 80041ec: 687b ldr r3, [r7, #4] 80041ee: 681b ldr r3, [r3, #0] 80041f0: f06f 0201 mvn.w r2, #1 80041f4: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); 80041f6: 6878 ldr r0, [r7, #4] 80041f8: f001 fae6 bl 80057c8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) 80041fc: 687b ldr r3, [r7, #4] 80041fe: 681b ldr r3, [r3, #0] 8004200: 691b ldr r3, [r3, #16] 8004202: f003 0380 and.w r3, r3, #128 ; 0x80 8004206: 2b80 cmp r3, #128 ; 0x80 8004208: d10e bne.n 8004228 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) 800420a: 687b ldr r3, [r7, #4] 800420c: 681b ldr r3, [r3, #0] 800420e: 68db ldr r3, [r3, #12] 8004210: f003 0380 and.w r3, r3, #128 ; 0x80 8004214: 2b80 cmp r3, #128 ; 0x80 8004216: d107 bne.n 8004228 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); 8004218: 687b ldr r3, [r7, #4] 800421a: 681b ldr r3, [r3, #0] 800421c: f06f 0280 mvn.w r2, #128 ; 0x80 8004220: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); 8004222: 6878 ldr r0, [r7, #4] 8004224: f000 f921 bl 800446a #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) 8004228: 687b ldr r3, [r7, #4] 800422a: 681b ldr r3, [r3, #0] 800422c: 691b ldr r3, [r3, #16] 800422e: f003 0340 and.w r3, r3, #64 ; 0x40 8004232: 2b40 cmp r3, #64 ; 0x40 8004234: d10e bne.n 8004254 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) 8004236: 687b ldr r3, [r7, #4] 8004238: 681b ldr r3, [r3, #0] 800423a: 68db ldr r3, [r3, #12] 800423c: f003 0340 and.w r3, r3, #64 ; 0x40 8004240: 2b40 cmp r3, #64 ; 0x40 8004242: d107 bne.n 8004254 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); 8004244: 687b ldr r3, [r7, #4] 8004246: 681b ldr r3, [r3, #0] 8004248: f06f 0240 mvn.w r2, #64 ; 0x40 800424c: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); 800424e: 6878 ldr r0, [r7, #4] 8004250: f000 f835 bl 80042be #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) 8004254: 687b ldr r3, [r7, #4] 8004256: 681b ldr r3, [r3, #0] 8004258: 691b ldr r3, [r3, #16] 800425a: f003 0320 and.w r3, r3, #32 800425e: 2b20 cmp r3, #32 8004260: d10e bne.n 8004280 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET) 8004262: 687b ldr r3, [r7, #4] 8004264: 681b ldr r3, [r3, #0] 8004266: 68db ldr r3, [r3, #12] 8004268: f003 0320 and.w r3, r3, #32 800426c: 2b20 cmp r3, #32 800426e: d107 bne.n 8004280 { __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); 8004270: 687b ldr r3, [r7, #4] 8004272: 681b ldr r3, [r3, #0] 8004274: f06f 0220 mvn.w r2, #32 8004278: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); 800427a: 6878 ldr r0, [r7, #4] 800427c: f000 f8ec bl 8004458 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } 8004280: bf00 nop 8004282: 3708 adds r7, #8 8004284: 46bd mov sp, r7 8004286: bd80 pop {r7, pc} 08004288 : * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { 8004288: b480 push {r7} 800428a: b083 sub sp, #12 800428c: af00 add r7, sp, #0 800428e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } 8004290: bf00 nop 8004292: 370c adds r7, #12 8004294: 46bd mov sp, r7 8004296: bc80 pop {r7} 8004298: 4770 bx lr 0800429a : * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { 800429a: b480 push {r7} 800429c: b083 sub sp, #12 800429e: af00 add r7, sp, #0 80042a0: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } 80042a2: bf00 nop 80042a4: 370c adds r7, #12 80042a6: 46bd mov sp, r7 80042a8: bc80 pop {r7} 80042aa: 4770 bx lr 080042ac : * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { 80042ac: b480 push {r7} 80042ae: b083 sub sp, #12 80042b0: af00 add r7, sp, #0 80042b2: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } 80042b4: bf00 nop 80042b6: 370c adds r7, #12 80042b8: 46bd mov sp, r7 80042ba: bc80 pop {r7} 80042bc: 4770 bx lr 080042be : * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { 80042be: b480 push {r7} 80042c0: b083 sub sp, #12 80042c2: af00 add r7, sp, #0 80042c4: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } 80042c6: bf00 nop 80042c8: 370c adds r7, #12 80042ca: 46bd mov sp, r7 80042cc: bc80 pop {r7} 80042ce: 4770 bx lr 080042d0 : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) { 80042d0: b480 push {r7} 80042d2: b085 sub sp, #20 80042d4: af00 add r7, sp, #0 80042d6: 6078 str r0, [r7, #4] 80042d8: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 80042da: 687b ldr r3, [r7, #4] 80042dc: 681b ldr r3, [r3, #0] 80042de: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 80042e0: 687b ldr r3, [r7, #4] 80042e2: 4a35 ldr r2, [pc, #212] ; (80043b8 ) 80042e4: 4293 cmp r3, r2 80042e6: d00b beq.n 8004300 80042e8: 687b ldr r3, [r7, #4] 80042ea: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 80042ee: d007 beq.n 8004300 80042f0: 687b ldr r3, [r7, #4] 80042f2: 4a32 ldr r2, [pc, #200] ; (80043bc ) 80042f4: 4293 cmp r3, r2 80042f6: d003 beq.n 8004300 80042f8: 687b ldr r3, [r7, #4] 80042fa: 4a31 ldr r2, [pc, #196] ; (80043c0 ) 80042fc: 4293 cmp r3, r2 80042fe: d108 bne.n 8004312 { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 8004300: 68fb ldr r3, [r7, #12] 8004302: f023 0370 bic.w r3, r3, #112 ; 0x70 8004306: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 8004308: 683b ldr r3, [r7, #0] 800430a: 685b ldr r3, [r3, #4] 800430c: 68fa ldr r2, [r7, #12] 800430e: 4313 orrs r3, r2 8004310: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 8004312: 687b ldr r3, [r7, #4] 8004314: 4a28 ldr r2, [pc, #160] ; (80043b8 ) 8004316: 4293 cmp r3, r2 8004318: d017 beq.n 800434a 800431a: 687b ldr r3, [r7, #4] 800431c: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 8004320: d013 beq.n 800434a 8004322: 687b ldr r3, [r7, #4] 8004324: 4a25 ldr r2, [pc, #148] ; (80043bc ) 8004326: 4293 cmp r3, r2 8004328: d00f beq.n 800434a 800432a: 687b ldr r3, [r7, #4] 800432c: 4a24 ldr r2, [pc, #144] ; (80043c0 ) 800432e: 4293 cmp r3, r2 8004330: d00b beq.n 800434a 8004332: 687b ldr r3, [r7, #4] 8004334: 4a23 ldr r2, [pc, #140] ; (80043c4 ) 8004336: 4293 cmp r3, r2 8004338: d007 beq.n 800434a 800433a: 687b ldr r3, [r7, #4] 800433c: 4a22 ldr r2, [pc, #136] ; (80043c8 ) 800433e: 4293 cmp r3, r2 8004340: d003 beq.n 800434a 8004342: 687b ldr r3, [r7, #4] 8004344: 4a21 ldr r2, [pc, #132] ; (80043cc ) 8004346: 4293 cmp r3, r2 8004348: d108 bne.n 800435c { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 800434a: 68fb ldr r3, [r7, #12] 800434c: f423 7340 bic.w r3, r3, #768 ; 0x300 8004350: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 8004352: 683b ldr r3, [r7, #0] 8004354: 68db ldr r3, [r3, #12] 8004356: 68fa ldr r2, [r7, #12] 8004358: 4313 orrs r3, r2 800435a: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 800435c: 68fb ldr r3, [r7, #12] 800435e: f023 0280 bic.w r2, r3, #128 ; 0x80 8004362: 683b ldr r3, [r7, #0] 8004364: 695b ldr r3, [r3, #20] 8004366: 4313 orrs r3, r2 8004368: 60fb str r3, [r7, #12] TIMx->CR1 = tmpcr1; 800436a: 687b ldr r3, [r7, #4] 800436c: 68fa ldr r2, [r7, #12] 800436e: 601a str r2, [r3, #0] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 8004370: 683b ldr r3, [r7, #0] 8004372: 689a ldr r2, [r3, #8] 8004374: 687b ldr r3, [r7, #4] 8004376: 62da str r2, [r3, #44] ; 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 8004378: 683b ldr r3, [r7, #0] 800437a: 681a ldr r2, [r3, #0] 800437c: 687b ldr r3, [r7, #4] 800437e: 629a str r2, [r3, #40] ; 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 8004380: 687b ldr r3, [r7, #4] 8004382: 4a0d ldr r2, [pc, #52] ; (80043b8 ) 8004384: 4293 cmp r3, r2 8004386: d00b beq.n 80043a0 8004388: 687b ldr r3, [r7, #4] 800438a: 4a0e ldr r2, [pc, #56] ; (80043c4 ) 800438c: 4293 cmp r3, r2 800438e: d007 beq.n 80043a0 8004390: 687b ldr r3, [r7, #4] 8004392: 4a0d ldr r2, [pc, #52] ; (80043c8 ) 8004394: 4293 cmp r3, r2 8004396: d003 beq.n 80043a0 8004398: 687b ldr r3, [r7, #4] 800439a: 4a0c ldr r2, [pc, #48] ; (80043cc ) 800439c: 4293 cmp r3, r2 800439e: d103 bne.n 80043a8 { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 80043a0: 683b ldr r3, [r7, #0] 80043a2: 691a ldr r2, [r3, #16] 80043a4: 687b ldr r3, [r7, #4] 80043a6: 631a str r2, [r3, #48] ; 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 80043a8: 687b ldr r3, [r7, #4] 80043aa: 2201 movs r2, #1 80043ac: 615a str r2, [r3, #20] } 80043ae: bf00 nop 80043b0: 3714 adds r7, #20 80043b2: 46bd mov sp, r7 80043b4: bc80 pop {r7} 80043b6: 4770 bx lr 80043b8: 40012c00 .word 0x40012c00 80043bc: 40000400 .word 0x40000400 80043c0: 40000800 .word 0x40000800 80043c4: 40014000 .word 0x40014000 80043c8: 40014400 .word 0x40014400 80043cc: 40014800 .word 0x40014800 080043d0 : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig) { 80043d0: b480 push {r7} 80043d2: b085 sub sp, #20 80043d4: af00 add r7, sp, #0 80043d6: 6078 str r0, [r7, #4] 80043d8: 6039 str r1, [r7, #0] assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 80043da: 687b ldr r3, [r7, #4] 80043dc: f893 303c ldrb.w r3, [r3, #60] ; 0x3c 80043e0: 2b01 cmp r3, #1 80043e2: d101 bne.n 80043e8 80043e4: 2302 movs r3, #2 80043e6: e032 b.n 800444e 80043e8: 687b ldr r3, [r7, #4] 80043ea: 2201 movs r2, #1 80043ec: f883 203c strb.w r2, [r3, #60] ; 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 80043f0: 687b ldr r3, [r7, #4] 80043f2: 2202 movs r2, #2 80043f4: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 80043f8: 687b ldr r3, [r7, #4] 80043fa: 681b ldr r3, [r3, #0] 80043fc: 685b ldr r3, [r3, #4] 80043fe: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 8004400: 687b ldr r3, [r7, #4] 8004402: 681b ldr r3, [r3, #0] 8004404: 689b ldr r3, [r3, #8] 8004406: 60bb str r3, [r7, #8] /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 8004408: 68fb ldr r3, [r7, #12] 800440a: f023 0370 bic.w r3, r3, #112 ; 0x70 800440e: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 8004410: 683b ldr r3, [r7, #0] 8004412: 681b ldr r3, [r3, #0] 8004414: 68fa ldr r2, [r7, #12] 8004416: 4313 orrs r3, r2 8004418: 60fb str r3, [r7, #12] /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 800441a: 68bb ldr r3, [r7, #8] 800441c: f023 0380 bic.w r3, r3, #128 ; 0x80 8004420: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 8004422: 683b ldr r3, [r7, #0] 8004424: 685b ldr r3, [r3, #4] 8004426: 68ba ldr r2, [r7, #8] 8004428: 4313 orrs r3, r2 800442a: 60bb str r3, [r7, #8] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 800442c: 687b ldr r3, [r7, #4] 800442e: 681b ldr r3, [r3, #0] 8004430: 68fa ldr r2, [r7, #12] 8004432: 605a str r2, [r3, #4] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 8004434: 687b ldr r3, [r7, #4] 8004436: 681b ldr r3, [r3, #0] 8004438: 68ba ldr r2, [r7, #8] 800443a: 609a str r2, [r3, #8] /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 800443c: 687b ldr r3, [r7, #4] 800443e: 2201 movs r2, #1 8004440: f883 203d strb.w r2, [r3, #61] ; 0x3d __HAL_UNLOCK(htim); 8004444: 687b ldr r3, [r7, #4] 8004446: 2200 movs r2, #0 8004448: f883 203c strb.w r2, [r3, #60] ; 0x3c return HAL_OK; 800444c: 2300 movs r3, #0 } 800444e: 4618 mov r0, r3 8004450: 3714 adds r7, #20 8004452: 46bd mov sp, r7 8004454: bc80 pop {r7} 8004456: 4770 bx lr 08004458 : * @brief Hall commutation changed callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { 8004458: b480 push {r7} 800445a: b083 sub sp, #12 800445c: af00 add r7, sp, #0 800445e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } 8004460: bf00 nop 8004462: 370c adds r7, #12 8004464: 46bd mov sp, r7 8004466: bc80 pop {r7} 8004468: 4770 bx lr 0800446a : * @brief Hall Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { 800446a: b480 push {r7} 800446c: b083 sub sp, #12 800446e: af00 add r7, sp, #0 8004470: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } 8004472: bf00 nop 8004474: 370c adds r7, #12 8004476: 46bd mov sp, r7 8004478: bc80 pop {r7} 800447a: 4770 bx lr 0800447c : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 800447c: b580 push {r7, lr} 800447e: b082 sub sp, #8 8004480: af00 add r7, sp, #0 8004482: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 8004484: 687b ldr r3, [r7, #4] 8004486: 2b00 cmp r3, #0 8004488: d101 bne.n 800448e { return HAL_ERROR; 800448a: 2301 movs r3, #1 800448c: e03f b.n 800450e assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); #if defined(USART_CR1_OVER8) assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); #endif /* USART_CR1_OVER8 */ if (huart->gState == HAL_UART_STATE_RESET) 800448e: 687b ldr r3, [r7, #4] 8004490: f893 3039 ldrb.w r3, [r3, #57] ; 0x39 8004494: b2db uxtb r3, r3 8004496: 2b00 cmp r3, #0 8004498: d106 bne.n 80044a8 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 800449a: 687b ldr r3, [r7, #4] 800449c: 2200 movs r2, #0 800449e: f883 2038 strb.w r2, [r3, #56] ; 0x38 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 80044a2: 6878 ldr r0, [r7, #4] 80044a4: f001 faf4 bl 8005a90 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 80044a8: 687b ldr r3, [r7, #4] 80044aa: 2224 movs r2, #36 ; 0x24 80044ac: f883 2039 strb.w r2, [r3, #57] ; 0x39 /* Disable the peripheral */ __HAL_UART_DISABLE(huart); 80044b0: 687b ldr r3, [r7, #4] 80044b2: 681b ldr r3, [r3, #0] 80044b4: 68da ldr r2, [r3, #12] 80044b6: 687b ldr r3, [r7, #4] 80044b8: 681b ldr r3, [r3, #0] 80044ba: f422 5200 bic.w r2, r2, #8192 ; 0x2000 80044be: 60da str r2, [r3, #12] /* Set the UART Communication parameters */ UART_SetConfig(huart); 80044c0: 6878 ldr r0, [r7, #4] 80044c2: f000 fd63 bl 8004f8c /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 80044c6: 687b ldr r3, [r7, #4] 80044c8: 681b ldr r3, [r3, #0] 80044ca: 691a ldr r2, [r3, #16] 80044cc: 687b ldr r3, [r7, #4] 80044ce: 681b ldr r3, [r3, #0] 80044d0: f422 4290 bic.w r2, r2, #18432 ; 0x4800 80044d4: 611a str r2, [r3, #16] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 80044d6: 687b ldr r3, [r7, #4] 80044d8: 681b ldr r3, [r3, #0] 80044da: 695a ldr r2, [r3, #20] 80044dc: 687b ldr r3, [r7, #4] 80044de: 681b ldr r3, [r3, #0] 80044e0: f022 022a bic.w r2, r2, #42 ; 0x2a 80044e4: 615a str r2, [r3, #20] /* Enable the peripheral */ __HAL_UART_ENABLE(huart); 80044e6: 687b ldr r3, [r7, #4] 80044e8: 681b ldr r3, [r3, #0] 80044ea: 68da ldr r2, [r3, #12] 80044ec: 687b ldr r3, [r7, #4] 80044ee: 681b ldr r3, [r3, #0] 80044f0: f442 5200 orr.w r2, r2, #8192 ; 0x2000 80044f4: 60da str r2, [r3, #12] /* Initialize the UART state */ huart->ErrorCode = HAL_UART_ERROR_NONE; 80044f6: 687b ldr r3, [r7, #4] 80044f8: 2200 movs r2, #0 80044fa: 63da str r2, [r3, #60] ; 0x3c huart->gState = HAL_UART_STATE_READY; 80044fc: 687b ldr r3, [r7, #4] 80044fe: 2220 movs r2, #32 8004500: f883 2039 strb.w r2, [r3, #57] ; 0x39 huart->RxState = HAL_UART_STATE_READY; 8004504: 687b ldr r3, [r7, #4] 8004506: 2220 movs r2, #32 8004508: f883 203a strb.w r2, [r3, #58] ; 0x3a return HAL_OK; 800450c: 2300 movs r3, #0 } 800450e: 4618 mov r0, r3 8004510: 3708 adds r7, #8 8004512: 46bd mov sp, r7 8004514: bd80 pop {r7, pc} 08004516 : * @param Size Amount of data elements (u8 or u16) to be sent * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) { 8004516: b580 push {r7, lr} 8004518: b088 sub sp, #32 800451a: af02 add r7, sp, #8 800451c: 60f8 str r0, [r7, #12] 800451e: 60b9 str r1, [r7, #8] 8004520: 603b str r3, [r7, #0] 8004522: 4613 mov r3, r2 8004524: 80fb strh r3, [r7, #6] uint16_t *tmp; uint32_t tickstart = 0U; 8004526: 2300 movs r3, #0 8004528: 617b str r3, [r7, #20] /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 800452a: 68fb ldr r3, [r7, #12] 800452c: f893 3039 ldrb.w r3, [r3, #57] ; 0x39 8004530: b2db uxtb r3, r3 8004532: 2b20 cmp r3, #32 8004534: f040 8083 bne.w 800463e { if ((pData == NULL) || (Size == 0U)) 8004538: 68bb ldr r3, [r7, #8] 800453a: 2b00 cmp r3, #0 800453c: d002 beq.n 8004544 800453e: 88fb ldrh r3, [r7, #6] 8004540: 2b00 cmp r3, #0 8004542: d101 bne.n 8004548 { return HAL_ERROR; 8004544: 2301 movs r3, #1 8004546: e07b b.n 8004640 } /* Process Locked */ __HAL_LOCK(huart); 8004548: 68fb ldr r3, [r7, #12] 800454a: f893 3038 ldrb.w r3, [r3, #56] ; 0x38 800454e: 2b01 cmp r3, #1 8004550: d101 bne.n 8004556 8004552: 2302 movs r3, #2 8004554: e074 b.n 8004640 8004556: 68fb ldr r3, [r7, #12] 8004558: 2201 movs r2, #1 800455a: f883 2038 strb.w r2, [r3, #56] ; 0x38 huart->ErrorCode = HAL_UART_ERROR_NONE; 800455e: 68fb ldr r3, [r7, #12] 8004560: 2200 movs r2, #0 8004562: 63da str r2, [r3, #60] ; 0x3c huart->gState = HAL_UART_STATE_BUSY_TX; 8004564: 68fb ldr r3, [r7, #12] 8004566: 2221 movs r2, #33 ; 0x21 8004568: f883 2039 strb.w r2, [r3, #57] ; 0x39 /* Init tickstart for timeout managment */ tickstart = HAL_GetTick(); 800456c: f7fd fc2e bl 8001dcc 8004570: 6178 str r0, [r7, #20] huart->TxXferSize = Size; 8004572: 68fb ldr r3, [r7, #12] 8004574: 88fa ldrh r2, [r7, #6] 8004576: 849a strh r2, [r3, #36] ; 0x24 huart->TxXferCount = Size; 8004578: 68fb ldr r3, [r7, #12] 800457a: 88fa ldrh r2, [r7, #6] 800457c: 84da strh r2, [r3, #38] ; 0x26 while (huart->TxXferCount > 0U) 800457e: e042 b.n 8004606 { huart->TxXferCount--; 8004580: 68fb ldr r3, [r7, #12] 8004582: 8cdb ldrh r3, [r3, #38] ; 0x26 8004584: b29b uxth r3, r3 8004586: 3b01 subs r3, #1 8004588: b29a uxth r2, r3 800458a: 68fb ldr r3, [r7, #12] 800458c: 84da strh r2, [r3, #38] ; 0x26 if (huart->Init.WordLength == UART_WORDLENGTH_9B) 800458e: 68fb ldr r3, [r7, #12] 8004590: 689b ldr r3, [r3, #8] 8004592: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8004596: d122 bne.n 80045de { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) 8004598: 683b ldr r3, [r7, #0] 800459a: 9300 str r3, [sp, #0] 800459c: 697b ldr r3, [r7, #20] 800459e: 2200 movs r2, #0 80045a0: 2180 movs r1, #128 ; 0x80 80045a2: 68f8 ldr r0, [r7, #12] 80045a4: f000 fb73 bl 8004c8e 80045a8: 4603 mov r3, r0 80045aa: 2b00 cmp r3, #0 80045ac: d001 beq.n 80045b2 { return HAL_TIMEOUT; 80045ae: 2303 movs r3, #3 80045b0: e046 b.n 8004640 } tmp = (uint16_t *) pData; 80045b2: 68bb ldr r3, [r7, #8] 80045b4: 613b str r3, [r7, #16] huart->Instance->DR = (*tmp & (uint16_t)0x01FF); 80045b6: 693b ldr r3, [r7, #16] 80045b8: 881b ldrh r3, [r3, #0] 80045ba: 461a mov r2, r3 80045bc: 68fb ldr r3, [r7, #12] 80045be: 681b ldr r3, [r3, #0] 80045c0: f3c2 0208 ubfx r2, r2, #0, #9 80045c4: 605a str r2, [r3, #4] if (huart->Init.Parity == UART_PARITY_NONE) 80045c6: 68fb ldr r3, [r7, #12] 80045c8: 691b ldr r3, [r3, #16] 80045ca: 2b00 cmp r3, #0 80045cc: d103 bne.n 80045d6 { pData += 2U; 80045ce: 68bb ldr r3, [r7, #8] 80045d0: 3302 adds r3, #2 80045d2: 60bb str r3, [r7, #8] 80045d4: e017 b.n 8004606 } else { pData += 1U; 80045d6: 68bb ldr r3, [r7, #8] 80045d8: 3301 adds r3, #1 80045da: 60bb str r3, [r7, #8] 80045dc: e013 b.n 8004606 } } else { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) 80045de: 683b ldr r3, [r7, #0] 80045e0: 9300 str r3, [sp, #0] 80045e2: 697b ldr r3, [r7, #20] 80045e4: 2200 movs r2, #0 80045e6: 2180 movs r1, #128 ; 0x80 80045e8: 68f8 ldr r0, [r7, #12] 80045ea: f000 fb50 bl 8004c8e 80045ee: 4603 mov r3, r0 80045f0: 2b00 cmp r3, #0 80045f2: d001 beq.n 80045f8 { return HAL_TIMEOUT; 80045f4: 2303 movs r3, #3 80045f6: e023 b.n 8004640 } huart->Instance->DR = (*pData++ & (uint8_t)0xFF); 80045f8: 68bb ldr r3, [r7, #8] 80045fa: 1c5a adds r2, r3, #1 80045fc: 60ba str r2, [r7, #8] 80045fe: 781a ldrb r2, [r3, #0] 8004600: 68fb ldr r3, [r7, #12] 8004602: 681b ldr r3, [r3, #0] 8004604: 605a str r2, [r3, #4] while (huart->TxXferCount > 0U) 8004606: 68fb ldr r3, [r7, #12] 8004608: 8cdb ldrh r3, [r3, #38] ; 0x26 800460a: b29b uxth r3, r3 800460c: 2b00 cmp r3, #0 800460e: d1b7 bne.n 8004580 } } if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) 8004610: 683b ldr r3, [r7, #0] 8004612: 9300 str r3, [sp, #0] 8004614: 697b ldr r3, [r7, #20] 8004616: 2200 movs r2, #0 8004618: 2140 movs r1, #64 ; 0x40 800461a: 68f8 ldr r0, [r7, #12] 800461c: f000 fb37 bl 8004c8e 8004620: 4603 mov r3, r0 8004622: 2b00 cmp r3, #0 8004624: d001 beq.n 800462a { return HAL_TIMEOUT; 8004626: 2303 movs r3, #3 8004628: e00a b.n 8004640 } /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 800462a: 68fb ldr r3, [r7, #12] 800462c: 2220 movs r2, #32 800462e: f883 2039 strb.w r2, [r3, #57] ; 0x39 /* Process Unlocked */ __HAL_UNLOCK(huart); 8004632: 68fb ldr r3, [r7, #12] 8004634: 2200 movs r2, #0 8004636: f883 2038 strb.w r2, [r3, #56] ; 0x38 return HAL_OK; 800463a: 2300 movs r3, #0 800463c: e000 b.n 8004640 } else { return HAL_BUSY; 800463e: 2302 movs r3, #2 } } 8004640: 4618 mov r0, r3 8004642: 3718 adds r7, #24 8004644: 46bd mov sp, r7 8004646: bd80 pop {r7, pc} 08004648 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8004648: b480 push {r7} 800464a: b085 sub sp, #20 800464c: af00 add r7, sp, #0 800464e: 60f8 str r0, [r7, #12] 8004650: 60b9 str r1, [r7, #8] 8004652: 4613 mov r3, r2 8004654: 80fb strh r3, [r7, #6] /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) 8004656: 68fb ldr r3, [r7, #12] 8004658: f893 303a ldrb.w r3, [r3, #58] ; 0x3a 800465c: b2db uxtb r3, r3 800465e: 2b20 cmp r3, #32 8004660: d140 bne.n 80046e4 { if ((pData == NULL) || (Size == 0U)) 8004662: 68bb ldr r3, [r7, #8] 8004664: 2b00 cmp r3, #0 8004666: d002 beq.n 800466e 8004668: 88fb ldrh r3, [r7, #6] 800466a: 2b00 cmp r3, #0 800466c: d101 bne.n 8004672 { return HAL_ERROR; 800466e: 2301 movs r3, #1 8004670: e039 b.n 80046e6 } /* Process Locked */ __HAL_LOCK(huart); 8004672: 68fb ldr r3, [r7, #12] 8004674: f893 3038 ldrb.w r3, [r3, #56] ; 0x38 8004678: 2b01 cmp r3, #1 800467a: d101 bne.n 8004680 800467c: 2302 movs r3, #2 800467e: e032 b.n 80046e6 8004680: 68fb ldr r3, [r7, #12] 8004682: 2201 movs r2, #1 8004684: f883 2038 strb.w r2, [r3, #56] ; 0x38 huart->pRxBuffPtr = pData; 8004688: 68fb ldr r3, [r7, #12] 800468a: 68ba ldr r2, [r7, #8] 800468c: 629a str r2, [r3, #40] ; 0x28 huart->RxXferSize = Size; 800468e: 68fb ldr r3, [r7, #12] 8004690: 88fa ldrh r2, [r7, #6] 8004692: 859a strh r2, [r3, #44] ; 0x2c huart->RxXferCount = Size; 8004694: 68fb ldr r3, [r7, #12] 8004696: 88fa ldrh r2, [r7, #6] 8004698: 85da strh r2, [r3, #46] ; 0x2e huart->ErrorCode = HAL_UART_ERROR_NONE; 800469a: 68fb ldr r3, [r7, #12] 800469c: 2200 movs r2, #0 800469e: 63da str r2, [r3, #60] ; 0x3c huart->RxState = HAL_UART_STATE_BUSY_RX; 80046a0: 68fb ldr r3, [r7, #12] 80046a2: 2222 movs r2, #34 ; 0x22 80046a4: f883 203a strb.w r2, [r3, #58] ; 0x3a /* Process Unlocked */ __HAL_UNLOCK(huart); 80046a8: 68fb ldr r3, [r7, #12] 80046aa: 2200 movs r2, #0 80046ac: f883 2038 strb.w r2, [r3, #56] ; 0x38 /* Enable the UART Parity Error Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_PE); 80046b0: 68fb ldr r3, [r7, #12] 80046b2: 681b ldr r3, [r3, #0] 80046b4: 68da ldr r2, [r3, #12] 80046b6: 68fb ldr r3, [r7, #12] 80046b8: 681b ldr r3, [r3, #0] 80046ba: f442 7280 orr.w r2, r2, #256 ; 0x100 80046be: 60da str r2, [r3, #12] /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_ENABLE_IT(huart, UART_IT_ERR); 80046c0: 68fb ldr r3, [r7, #12] 80046c2: 681b ldr r3, [r3, #0] 80046c4: 695a ldr r2, [r3, #20] 80046c6: 68fb ldr r3, [r7, #12] 80046c8: 681b ldr r3, [r3, #0] 80046ca: f042 0201 orr.w r2, r2, #1 80046ce: 615a str r2, [r3, #20] /* Enable the UART Data Register not empty Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE); 80046d0: 68fb ldr r3, [r7, #12] 80046d2: 681b ldr r3, [r3, #0] 80046d4: 68da ldr r2, [r3, #12] 80046d6: 68fb ldr r3, [r7, #12] 80046d8: 681b ldr r3, [r3, #0] 80046da: f042 0220 orr.w r2, r2, #32 80046de: 60da str r2, [r3, #12] return HAL_OK; 80046e0: 2300 movs r3, #0 80046e2: e000 b.n 80046e6 } else { return HAL_BUSY; 80046e4: 2302 movs r3, #2 } } 80046e6: 4618 mov r0, r3 80046e8: 3714 adds r7, #20 80046ea: 46bd mov sp, r7 80046ec: bc80 pop {r7} 80046ee: 4770 bx lr 080046f0 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 80046f0: b580 push {r7, lr} 80046f2: b086 sub sp, #24 80046f4: af00 add r7, sp, #0 80046f6: 60f8 str r0, [r7, #12] 80046f8: 60b9 str r1, [r7, #8] 80046fa: 4613 mov r3, r2 80046fc: 80fb strh r3, [r7, #6] uint32_t *tmp; /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 80046fe: 68fb ldr r3, [r7, #12] 8004700: f893 3039 ldrb.w r3, [r3, #57] ; 0x39 8004704: b2db uxtb r3, r3 8004706: 2b20 cmp r3, #32 8004708: d153 bne.n 80047b2 { if ((pData == NULL) || (Size == 0U)) 800470a: 68bb ldr r3, [r7, #8] 800470c: 2b00 cmp r3, #0 800470e: d002 beq.n 8004716 8004710: 88fb ldrh r3, [r7, #6] 8004712: 2b00 cmp r3, #0 8004714: d101 bne.n 800471a { return HAL_ERROR; 8004716: 2301 movs r3, #1 8004718: e04c b.n 80047b4 } /* Process Locked */ __HAL_LOCK(huart); 800471a: 68fb ldr r3, [r7, #12] 800471c: f893 3038 ldrb.w r3, [r3, #56] ; 0x38 8004720: 2b01 cmp r3, #1 8004722: d101 bne.n 8004728 8004724: 2302 movs r3, #2 8004726: e045 b.n 80047b4 8004728: 68fb ldr r3, [r7, #12] 800472a: 2201 movs r2, #1 800472c: f883 2038 strb.w r2, [r3, #56] ; 0x38 huart->pTxBuffPtr = pData; 8004730: 68ba ldr r2, [r7, #8] 8004732: 68fb ldr r3, [r7, #12] 8004734: 621a str r2, [r3, #32] huart->TxXferSize = Size; 8004736: 68fb ldr r3, [r7, #12] 8004738: 88fa ldrh r2, [r7, #6] 800473a: 849a strh r2, [r3, #36] ; 0x24 huart->TxXferCount = Size; 800473c: 68fb ldr r3, [r7, #12] 800473e: 88fa ldrh r2, [r7, #6] 8004740: 84da strh r2, [r3, #38] ; 0x26 huart->ErrorCode = HAL_UART_ERROR_NONE; 8004742: 68fb ldr r3, [r7, #12] 8004744: 2200 movs r2, #0 8004746: 63da str r2, [r3, #60] ; 0x3c huart->gState = HAL_UART_STATE_BUSY_TX; 8004748: 68fb ldr r3, [r7, #12] 800474a: 2221 movs r2, #33 ; 0x21 800474c: f883 2039 strb.w r2, [r3, #57] ; 0x39 /* Set the UART DMA transfer complete callback */ huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; 8004750: 68fb ldr r3, [r7, #12] 8004752: 6b1b ldr r3, [r3, #48] ; 0x30 8004754: 4a19 ldr r2, [pc, #100] ; (80047bc ) 8004756: 629a str r2, [r3, #40] ; 0x28 /* Set the UART DMA Half transfer complete callback */ huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; 8004758: 68fb ldr r3, [r7, #12] 800475a: 6b1b ldr r3, [r3, #48] ; 0x30 800475c: 4a18 ldr r2, [pc, #96] ; (80047c0 ) 800475e: 62da str r2, [r3, #44] ; 0x2c /* Set the DMA error callback */ huart->hdmatx->XferErrorCallback = UART_DMAError; 8004760: 68fb ldr r3, [r7, #12] 8004762: 6b1b ldr r3, [r3, #48] ; 0x30 8004764: 4a17 ldr r2, [pc, #92] ; (80047c4 ) 8004766: 631a str r2, [r3, #48] ; 0x30 /* Set the DMA abort callback */ huart->hdmatx->XferAbortCallback = NULL; 8004768: 68fb ldr r3, [r7, #12] 800476a: 6b1b ldr r3, [r3, #48] ; 0x30 800476c: 2200 movs r2, #0 800476e: 635a str r2, [r3, #52] ; 0x34 /* Enable the UART transmit DMA channel */ tmp = (uint32_t *)&pData; 8004770: f107 0308 add.w r3, r7, #8 8004774: 617b str r3, [r7, #20] HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t *)tmp, (uint32_t)&huart->Instance->DR, Size); 8004776: 68fb ldr r3, [r7, #12] 8004778: 6b18 ldr r0, [r3, #48] ; 0x30 800477a: 697b ldr r3, [r7, #20] 800477c: 6819 ldr r1, [r3, #0] 800477e: 68fb ldr r3, [r7, #12] 8004780: 681b ldr r3, [r3, #0] 8004782: 3304 adds r3, #4 8004784: 461a mov r2, r3 8004786: 88fb ldrh r3, [r7, #6] 8004788: f7fe f966 bl 8002a58 /* Clear the TC flag in the SR register by writing 0 to it */ __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC); 800478c: 68fb ldr r3, [r7, #12] 800478e: 681b ldr r3, [r3, #0] 8004790: f06f 0240 mvn.w r2, #64 ; 0x40 8004794: 601a str r2, [r3, #0] /* Process Unlocked */ __HAL_UNLOCK(huart); 8004796: 68fb ldr r3, [r7, #12] 8004798: 2200 movs r2, #0 800479a: f883 2038 strb.w r2, [r3, #56] ; 0x38 /* Enable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); 800479e: 68fb ldr r3, [r7, #12] 80047a0: 681b ldr r3, [r3, #0] 80047a2: 695a ldr r2, [r3, #20] 80047a4: 68fb ldr r3, [r7, #12] 80047a6: 681b ldr r3, [r3, #0] 80047a8: f042 0280 orr.w r2, r2, #128 ; 0x80 80047ac: 615a str r2, [r3, #20] return HAL_OK; 80047ae: 2300 movs r3, #0 80047b0: e000 b.n 80047b4 } else { return HAL_BUSY; 80047b2: 2302 movs r3, #2 } } 80047b4: 4618 mov r0, r3 80047b6: 3718 adds r7, #24 80047b8: 46bd mov sp, r7 80047ba: bd80 pop {r7, pc} 80047bc: 08004b09 .word 0x08004b09 80047c0: 08004b5b .word 0x08004b5b 80047c4: 08004bfb .word 0x08004bfb 080047c8 : * @param Size Amount of data elements (u8 or u16) to be received. * @note When the UART parity is enabled (PCE = 1) the received data contains the parity bit. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 80047c8: b580 push {r7, lr} 80047ca: b086 sub sp, #24 80047cc: af00 add r7, sp, #0 80047ce: 60f8 str r0, [r7, #12] 80047d0: 60b9 str r1, [r7, #8] 80047d2: 4613 mov r3, r2 80047d4: 80fb strh r3, [r7, #6] uint32_t *tmp; /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) 80047d6: 68fb ldr r3, [r7, #12] 80047d8: f893 303a ldrb.w r3, [r3, #58] ; 0x3a 80047dc: b2db uxtb r3, r3 80047de: 2b20 cmp r3, #32 80047e0: d166 bne.n 80048b0 { if ((pData == NULL) || (Size == 0U)) 80047e2: 68bb ldr r3, [r7, #8] 80047e4: 2b00 cmp r3, #0 80047e6: d002 beq.n 80047ee 80047e8: 88fb ldrh r3, [r7, #6] 80047ea: 2b00 cmp r3, #0 80047ec: d101 bne.n 80047f2 { return HAL_ERROR; 80047ee: 2301 movs r3, #1 80047f0: e05f b.n 80048b2 } /* Process Locked */ __HAL_LOCK(huart); 80047f2: 68fb ldr r3, [r7, #12] 80047f4: f893 3038 ldrb.w r3, [r3, #56] ; 0x38 80047f8: 2b01 cmp r3, #1 80047fa: d101 bne.n 8004800 80047fc: 2302 movs r3, #2 80047fe: e058 b.n 80048b2 8004800: 68fb ldr r3, [r7, #12] 8004802: 2201 movs r2, #1 8004804: f883 2038 strb.w r2, [r3, #56] ; 0x38 huart->pRxBuffPtr = pData; 8004808: 68ba ldr r2, [r7, #8] 800480a: 68fb ldr r3, [r7, #12] 800480c: 629a str r2, [r3, #40] ; 0x28 huart->RxXferSize = Size; 800480e: 68fb ldr r3, [r7, #12] 8004810: 88fa ldrh r2, [r7, #6] 8004812: 859a strh r2, [r3, #44] ; 0x2c huart->ErrorCode = HAL_UART_ERROR_NONE; 8004814: 68fb ldr r3, [r7, #12] 8004816: 2200 movs r2, #0 8004818: 63da str r2, [r3, #60] ; 0x3c huart->RxState = HAL_UART_STATE_BUSY_RX; 800481a: 68fb ldr r3, [r7, #12] 800481c: 2222 movs r2, #34 ; 0x22 800481e: f883 203a strb.w r2, [r3, #58] ; 0x3a /* Set the UART DMA transfer complete callback */ huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; 8004822: 68fb ldr r3, [r7, #12] 8004824: 6b5b ldr r3, [r3, #52] ; 0x34 8004826: 4a25 ldr r2, [pc, #148] ; (80048bc ) 8004828: 629a str r2, [r3, #40] ; 0x28 /* Set the UART DMA Half transfer complete callback */ huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; 800482a: 68fb ldr r3, [r7, #12] 800482c: 6b5b ldr r3, [r3, #52] ; 0x34 800482e: 4a24 ldr r2, [pc, #144] ; (80048c0 ) 8004830: 62da str r2, [r3, #44] ; 0x2c /* Set the DMA error callback */ huart->hdmarx->XferErrorCallback = UART_DMAError; 8004832: 68fb ldr r3, [r7, #12] 8004834: 6b5b ldr r3, [r3, #52] ; 0x34 8004836: 4a23 ldr r2, [pc, #140] ; (80048c4 ) 8004838: 631a str r2, [r3, #48] ; 0x30 /* Set the DMA abort callback */ huart->hdmarx->XferAbortCallback = NULL; 800483a: 68fb ldr r3, [r7, #12] 800483c: 6b5b ldr r3, [r3, #52] ; 0x34 800483e: 2200 movs r2, #0 8004840: 635a str r2, [r3, #52] ; 0x34 /* Enable the DMA channel */ tmp = (uint32_t *)&pData; 8004842: f107 0308 add.w r3, r7, #8 8004846: 617b str r3, [r7, #20] HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t *)tmp, Size); 8004848: 68fb ldr r3, [r7, #12] 800484a: 6b58 ldr r0, [r3, #52] ; 0x34 800484c: 68fb ldr r3, [r7, #12] 800484e: 681b ldr r3, [r3, #0] 8004850: 3304 adds r3, #4 8004852: 4619 mov r1, r3 8004854: 697b ldr r3, [r7, #20] 8004856: 681a ldr r2, [r3, #0] 8004858: 88fb ldrh r3, [r7, #6] 800485a: f7fe f8fd bl 8002a58 /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */ __HAL_UART_CLEAR_OREFLAG(huart); 800485e: 2300 movs r3, #0 8004860: 613b str r3, [r7, #16] 8004862: 68fb ldr r3, [r7, #12] 8004864: 681b ldr r3, [r3, #0] 8004866: 681b ldr r3, [r3, #0] 8004868: 613b str r3, [r7, #16] 800486a: 68fb ldr r3, [r7, #12] 800486c: 681b ldr r3, [r3, #0] 800486e: 685b ldr r3, [r3, #4] 8004870: 613b str r3, [r7, #16] 8004872: 693b ldr r3, [r7, #16] /* Process Unlocked */ __HAL_UNLOCK(huart); 8004874: 68fb ldr r3, [r7, #12] 8004876: 2200 movs r2, #0 8004878: f883 2038 strb.w r2, [r3, #56] ; 0x38 /* Enable the UART Parity Error Interrupt */ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); 800487c: 68fb ldr r3, [r7, #12] 800487e: 681b ldr r3, [r3, #0] 8004880: 68da ldr r2, [r3, #12] 8004882: 68fb ldr r3, [r7, #12] 8004884: 681b ldr r3, [r3, #0] 8004886: f442 7280 orr.w r2, r2, #256 ; 0x100 800488a: 60da str r2, [r3, #12] /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(huart->Instance->CR3, USART_CR3_EIE); 800488c: 68fb ldr r3, [r7, #12] 800488e: 681b ldr r3, [r3, #0] 8004890: 695a ldr r2, [r3, #20] 8004892: 68fb ldr r3, [r7, #12] 8004894: 681b ldr r3, [r3, #0] 8004896: f042 0201 orr.w r2, r2, #1 800489a: 615a str r2, [r3, #20] /* Enable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); 800489c: 68fb ldr r3, [r7, #12] 800489e: 681b ldr r3, [r3, #0] 80048a0: 695a ldr r2, [r3, #20] 80048a2: 68fb ldr r3, [r7, #12] 80048a4: 681b ldr r3, [r3, #0] 80048a6: f042 0240 orr.w r2, r2, #64 ; 0x40 80048aa: 615a str r2, [r3, #20] return HAL_OK; 80048ac: 2300 movs r3, #0 80048ae: e000 b.n 80048b2 } else { return HAL_BUSY; 80048b0: 2302 movs r3, #2 } } 80048b2: 4618 mov r0, r3 80048b4: 3718 adds r7, #24 80048b6: 46bd mov sp, r7 80048b8: bd80 pop {r7, pc} 80048ba: bf00 nop 80048bc: 08004b77 .word 0x08004b77 80048c0: 08004bdf .word 0x08004bdf 80048c4: 08004bfb .word 0x08004bfb 080048c8 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { 80048c8: b580 push {r7, lr} 80048ca: b088 sub sp, #32 80048cc: af00 add r7, sp, #0 80048ce: 6078 str r0, [r7, #4] uint32_t isrflags = READ_REG(huart->Instance->SR); 80048d0: 687b ldr r3, [r7, #4] 80048d2: 681b ldr r3, [r3, #0] 80048d4: 681b ldr r3, [r3, #0] 80048d6: 61fb str r3, [r7, #28] uint32_t cr1its = READ_REG(huart->Instance->CR1); 80048d8: 687b ldr r3, [r7, #4] 80048da: 681b ldr r3, [r3, #0] 80048dc: 68db ldr r3, [r3, #12] 80048de: 61bb str r3, [r7, #24] uint32_t cr3its = READ_REG(huart->Instance->CR3); 80048e0: 687b ldr r3, [r7, #4] 80048e2: 681b ldr r3, [r3, #0] 80048e4: 695b ldr r3, [r3, #20] 80048e6: 617b str r3, [r7, #20] uint32_t errorflags = 0x00U; 80048e8: 2300 movs r3, #0 80048ea: 613b str r3, [r7, #16] uint32_t dmarequest = 0x00U; 80048ec: 2300 movs r3, #0 80048ee: 60fb str r3, [r7, #12] /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE)); 80048f0: 69fb ldr r3, [r7, #28] 80048f2: f003 030f and.w r3, r3, #15 80048f6: 613b str r3, [r7, #16] if (errorflags == RESET) 80048f8: 693b ldr r3, [r7, #16] 80048fa: 2b00 cmp r3, #0 80048fc: d10d bne.n 800491a { /* UART in mode Receiver -------------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 80048fe: 69fb ldr r3, [r7, #28] 8004900: f003 0320 and.w r3, r3, #32 8004904: 2b00 cmp r3, #0 8004906: d008 beq.n 800491a 8004908: 69bb ldr r3, [r7, #24] 800490a: f003 0320 and.w r3, r3, #32 800490e: 2b00 cmp r3, #0 8004910: d003 beq.n 800491a { UART_Receive_IT(huart); 8004912: 6878 ldr r0, [r7, #4] 8004914: f000 fab8 bl 8004e88 return; 8004918: e0cc b.n 8004ab4 } } /* If some errors occur */ if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) 800491a: 693b ldr r3, [r7, #16] 800491c: 2b00 cmp r3, #0 800491e: f000 80ab beq.w 8004a78 8004922: 697b ldr r3, [r7, #20] 8004924: f003 0301 and.w r3, r3, #1 8004928: 2b00 cmp r3, #0 800492a: d105 bne.n 8004938 800492c: 69bb ldr r3, [r7, #24] 800492e: f403 7390 and.w r3, r3, #288 ; 0x120 8004932: 2b00 cmp r3, #0 8004934: f000 80a0 beq.w 8004a78 { /* UART parity error interrupt occurred ----------------------------------*/ if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) 8004938: 69fb ldr r3, [r7, #28] 800493a: f003 0301 and.w r3, r3, #1 800493e: 2b00 cmp r3, #0 8004940: d00a beq.n 8004958 8004942: 69bb ldr r3, [r7, #24] 8004944: f403 7380 and.w r3, r3, #256 ; 0x100 8004948: 2b00 cmp r3, #0 800494a: d005 beq.n 8004958 { huart->ErrorCode |= HAL_UART_ERROR_PE; 800494c: 687b ldr r3, [r7, #4] 800494e: 6bdb ldr r3, [r3, #60] ; 0x3c 8004950: f043 0201 orr.w r2, r3, #1 8004954: 687b ldr r3, [r7, #4] 8004956: 63da str r2, [r3, #60] ; 0x3c } /* UART noise error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 8004958: 69fb ldr r3, [r7, #28] 800495a: f003 0304 and.w r3, r3, #4 800495e: 2b00 cmp r3, #0 8004960: d00a beq.n 8004978 8004962: 697b ldr r3, [r7, #20] 8004964: f003 0301 and.w r3, r3, #1 8004968: 2b00 cmp r3, #0 800496a: d005 beq.n 8004978 { huart->ErrorCode |= HAL_UART_ERROR_NE; 800496c: 687b ldr r3, [r7, #4] 800496e: 6bdb ldr r3, [r3, #60] ; 0x3c 8004970: f043 0202 orr.w r2, r3, #2 8004974: 687b ldr r3, [r7, #4] 8004976: 63da str r2, [r3, #60] ; 0x3c } /* UART frame error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 8004978: 69fb ldr r3, [r7, #28] 800497a: f003 0302 and.w r3, r3, #2 800497e: 2b00 cmp r3, #0 8004980: d00a beq.n 8004998 8004982: 697b ldr r3, [r7, #20] 8004984: f003 0301 and.w r3, r3, #1 8004988: 2b00 cmp r3, #0 800498a: d005 beq.n 8004998 { huart->ErrorCode |= HAL_UART_ERROR_FE; 800498c: 687b ldr r3, [r7, #4] 800498e: 6bdb ldr r3, [r3, #60] ; 0x3c 8004990: f043 0204 orr.w r2, r3, #4 8004994: 687b ldr r3, [r7, #4] 8004996: 63da str r2, [r3, #60] ; 0x3c } /* UART Over-Run interrupt occurred --------------------------------------*/ if (((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 8004998: 69fb ldr r3, [r7, #28] 800499a: f003 0308 and.w r3, r3, #8 800499e: 2b00 cmp r3, #0 80049a0: d00a beq.n 80049b8 80049a2: 697b ldr r3, [r7, #20] 80049a4: f003 0301 and.w r3, r3, #1 80049a8: 2b00 cmp r3, #0 80049aa: d005 beq.n 80049b8 { huart->ErrorCode |= HAL_UART_ERROR_ORE; 80049ac: 687b ldr r3, [r7, #4] 80049ae: 6bdb ldr r3, [r3, #60] ; 0x3c 80049b0: f043 0208 orr.w r2, r3, #8 80049b4: 687b ldr r3, [r7, #4] 80049b6: 63da str r2, [r3, #60] ; 0x3c } /* Call UART Error Call back function if need be --------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 80049b8: 687b ldr r3, [r7, #4] 80049ba: 6bdb ldr r3, [r3, #60] ; 0x3c 80049bc: 2b00 cmp r3, #0 80049be: d078 beq.n 8004ab2 { /* UART in mode Receiver -----------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 80049c0: 69fb ldr r3, [r7, #28] 80049c2: f003 0320 and.w r3, r3, #32 80049c6: 2b00 cmp r3, #0 80049c8: d007 beq.n 80049da 80049ca: 69bb ldr r3, [r7, #24] 80049cc: f003 0320 and.w r3, r3, #32 80049d0: 2b00 cmp r3, #0 80049d2: d002 beq.n 80049da { UART_Receive_IT(huart); 80049d4: 6878 ldr r0, [r7, #4] 80049d6: f000 fa57 bl 8004e88 } /* If Overrun error occurs, or if any error occurs in DMA mode reception, consider error as blocking */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 80049da: 687b ldr r3, [r7, #4] 80049dc: 681b ldr r3, [r3, #0] 80049de: 695b ldr r3, [r3, #20] 80049e0: f003 0340 and.w r3, r3, #64 ; 0x40 80049e4: 2b00 cmp r3, #0 80049e6: bf14 ite ne 80049e8: 2301 movne r3, #1 80049ea: 2300 moveq r3, #0 80049ec: b2db uxtb r3, r3 80049ee: 60fb str r3, [r7, #12] if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest) 80049f0: 687b ldr r3, [r7, #4] 80049f2: 6bdb ldr r3, [r3, #60] ; 0x3c 80049f4: f003 0308 and.w r3, r3, #8 80049f8: 2b00 cmp r3, #0 80049fa: d102 bne.n 8004a02 80049fc: 68fb ldr r3, [r7, #12] 80049fe: 2b00 cmp r3, #0 8004a00: d031 beq.n 8004a66 { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); 8004a02: 6878 ldr r0, [r7, #4] 8004a04: f000 f9a2 bl 8004d4c /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8004a08: 687b ldr r3, [r7, #4] 8004a0a: 681b ldr r3, [r3, #0] 8004a0c: 695b ldr r3, [r3, #20] 8004a0e: f003 0340 and.w r3, r3, #64 ; 0x40 8004a12: 2b00 cmp r3, #0 8004a14: d023 beq.n 8004a5e { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8004a16: 687b ldr r3, [r7, #4] 8004a18: 681b ldr r3, [r3, #0] 8004a1a: 695a ldr r2, [r3, #20] 8004a1c: 687b ldr r3, [r7, #4] 8004a1e: 681b ldr r3, [r3, #0] 8004a20: f022 0240 bic.w r2, r2, #64 ; 0x40 8004a24: 615a str r2, [r3, #20] /* Abort the UART DMA Rx channel */ if (huart->hdmarx != NULL) 8004a26: 687b ldr r3, [r7, #4] 8004a28: 6b5b ldr r3, [r3, #52] ; 0x34 8004a2a: 2b00 cmp r3, #0 8004a2c: d013 beq.n 8004a56 { /* Set the UART DMA Abort callback : will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; 8004a2e: 687b ldr r3, [r7, #4] 8004a30: 6b5b ldr r3, [r3, #52] ; 0x34 8004a32: 4a22 ldr r2, [pc, #136] ; (8004abc ) 8004a34: 635a str r2, [r3, #52] ; 0x34 if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 8004a36: 687b ldr r3, [r7, #4] 8004a38: 6b5b ldr r3, [r3, #52] ; 0x34 8004a3a: 4618 mov r0, r3 8004a3c: f7fe f86c bl 8002b18 8004a40: 4603 mov r3, r0 8004a42: 2b00 cmp r3, #0 8004a44: d016 beq.n 8004a74 { /* Call Directly XferAbortCallback function in case of error */ huart->hdmarx->XferAbortCallback(huart->hdmarx); 8004a46: 687b ldr r3, [r7, #4] 8004a48: 6b5b ldr r3, [r3, #52] ; 0x34 8004a4a: 6b5b ldr r3, [r3, #52] ; 0x34 8004a4c: 687a ldr r2, [r7, #4] 8004a4e: 6b52 ldr r2, [r2, #52] ; 0x34 8004a50: 4610 mov r0, r2 8004a52: 4798 blx r3 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8004a54: e00e b.n 8004a74 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8004a56: 6878 ldr r0, [r7, #4] 8004a58: f000 f84d bl 8004af6 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8004a5c: e00a b.n 8004a74 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8004a5e: 6878 ldr r0, [r7, #4] 8004a60: f000 f849 bl 8004af6 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8004a64: e006 b.n 8004a74 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8004a66: 6878 ldr r0, [r7, #4] 8004a68: f000 f845 bl 8004af6 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8004a6c: 687b ldr r3, [r7, #4] 8004a6e: 2200 movs r2, #0 8004a70: 63da str r2, [r3, #60] ; 0x3c } } return; 8004a72: e01e b.n 8004ab2 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8004a74: bf00 nop return; 8004a76: e01c b.n 8004ab2 } /* End if some error occurs */ /* UART in mode Transmitter ------------------------------------------------*/ if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) 8004a78: 69fb ldr r3, [r7, #28] 8004a7a: f003 0380 and.w r3, r3, #128 ; 0x80 8004a7e: 2b00 cmp r3, #0 8004a80: d008 beq.n 8004a94 8004a82: 69bb ldr r3, [r7, #24] 8004a84: f003 0380 and.w r3, r3, #128 ; 0x80 8004a88: 2b00 cmp r3, #0 8004a8a: d003 beq.n 8004a94 { UART_Transmit_IT(huart); 8004a8c: 6878 ldr r0, [r7, #4] 8004a8e: f000 f98e bl 8004dae return; 8004a92: e00f b.n 8004ab4 } /* UART in mode Transmitter end --------------------------------------------*/ if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) 8004a94: 69fb ldr r3, [r7, #28] 8004a96: f003 0340 and.w r3, r3, #64 ; 0x40 8004a9a: 2b00 cmp r3, #0 8004a9c: d00a beq.n 8004ab4 8004a9e: 69bb ldr r3, [r7, #24] 8004aa0: f003 0340 and.w r3, r3, #64 ; 0x40 8004aa4: 2b00 cmp r3, #0 8004aa6: d005 beq.n 8004ab4 { UART_EndTransmit_IT(huart); 8004aa8: 6878 ldr r0, [r7, #4] 8004aaa: f000 f9d5 bl 8004e58 return; 8004aae: bf00 nop 8004ab0: e000 b.n 8004ab4 return; 8004ab2: bf00 nop } } 8004ab4: 3720 adds r7, #32 8004ab6: 46bd mov sp, r7 8004ab8: bd80 pop {r7, pc} 8004aba: bf00 nop 8004abc: 08004d87 .word 0x08004d87 08004ac0 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { 8004ac0: b480 push {r7} 8004ac2: b083 sub sp, #12 8004ac4: af00 add r7, sp, #0 8004ac6: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_TxCpltCallback could be implemented in the user file */ } 8004ac8: bf00 nop 8004aca: 370c adds r7, #12 8004acc: 46bd mov sp, r7 8004ace: bc80 pop {r7} 8004ad0: 4770 bx lr 08004ad2 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) { 8004ad2: b480 push {r7} 8004ad4: b083 sub sp, #12 8004ad6: af00 add r7, sp, #0 8004ad8: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_TxHalfCpltCallback could be implemented in the user file */ } 8004ada: bf00 nop 8004adc: 370c adds r7, #12 8004ade: 46bd mov sp, r7 8004ae0: bc80 pop {r7} 8004ae2: 4770 bx lr 08004ae4 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) { 8004ae4: b480 push {r7} 8004ae6: b083 sub sp, #12 8004ae8: af00 add r7, sp, #0 8004aea: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_RxHalfCpltCallback could be implemented in the user file */ } 8004aec: bf00 nop 8004aee: 370c adds r7, #12 8004af0: 46bd mov sp, r7 8004af2: bc80 pop {r7} 8004af4: 4770 bx lr 08004af6 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { 8004af6: b480 push {r7} 8004af8: b083 sub sp, #12 8004afa: af00 add r7, sp, #0 8004afc: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_ErrorCallback could be implemented in the user file */ } 8004afe: bf00 nop 8004b00: 370c adds r7, #12 8004b02: 46bd mov sp, r7 8004b04: bc80 pop {r7} 8004b06: 4770 bx lr 08004b08 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) { 8004b08: b580 push {r7, lr} 8004b0a: b084 sub sp, #16 8004b0c: af00 add r7, sp, #0 8004b0e: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8004b10: 687b ldr r3, [r7, #4] 8004b12: 6a5b ldr r3, [r3, #36] ; 0x24 8004b14: 60fb str r3, [r7, #12] /* DMA Normal mode*/ if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 8004b16: 687b ldr r3, [r7, #4] 8004b18: 681b ldr r3, [r3, #0] 8004b1a: 681b ldr r3, [r3, #0] 8004b1c: f003 0320 and.w r3, r3, #32 8004b20: 2b00 cmp r3, #0 8004b22: d113 bne.n 8004b4c { huart->TxXferCount = 0x00U; 8004b24: 68fb ldr r3, [r7, #12] 8004b26: 2200 movs r2, #0 8004b28: 84da strh r2, [r3, #38] ; 0x26 /* Disable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); 8004b2a: 68fb ldr r3, [r7, #12] 8004b2c: 681b ldr r3, [r3, #0] 8004b2e: 695a ldr r2, [r3, #20] 8004b30: 68fb ldr r3, [r7, #12] 8004b32: 681b ldr r3, [r3, #0] 8004b34: f022 0280 bic.w r2, r2, #128 ; 0x80 8004b38: 615a str r2, [r3, #20] /* Enable the UART Transmit Complete Interrupt */ SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 8004b3a: 68fb ldr r3, [r7, #12] 8004b3c: 681b ldr r3, [r3, #0] 8004b3e: 68da ldr r2, [r3, #12] 8004b40: 68fb ldr r3, [r7, #12] 8004b42: 681b ldr r3, [r3, #0] 8004b44: f042 0240 orr.w r2, r2, #64 ; 0x40 8004b48: 60da str r2, [r3, #12] #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } 8004b4a: e002 b.n 8004b52 HAL_UART_TxCpltCallback(huart); 8004b4c: 68f8 ldr r0, [r7, #12] 8004b4e: f7ff ffb7 bl 8004ac0 } 8004b52: bf00 nop 8004b54: 3710 adds r7, #16 8004b56: 46bd mov sp, r7 8004b58: bd80 pop {r7, pc} 08004b5a : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) { 8004b5a: b580 push {r7, lr} 8004b5c: b084 sub sp, #16 8004b5e: af00 add r7, sp, #0 8004b60: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8004b62: 687b ldr r3, [r7, #4] 8004b64: 6a5b ldr r3, [r3, #36] ; 0x24 8004b66: 60fb str r3, [r7, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxHalfCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxHalfCpltCallback(huart); 8004b68: 68f8 ldr r0, [r7, #12] 8004b6a: f7ff ffb2 bl 8004ad2 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8004b6e: bf00 nop 8004b70: 3710 adds r7, #16 8004b72: 46bd mov sp, r7 8004b74: bd80 pop {r7, pc} 08004b76 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { 8004b76: b580 push {r7, lr} 8004b78: b084 sub sp, #16 8004b7a: af00 add r7, sp, #0 8004b7c: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8004b7e: 687b ldr r3, [r7, #4] 8004b80: 6a5b ldr r3, [r3, #36] ; 0x24 8004b82: 60fb str r3, [r7, #12] /* DMA Normal mode*/ if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 8004b84: 687b ldr r3, [r7, #4] 8004b86: 681b ldr r3, [r3, #0] 8004b88: 681b ldr r3, [r3, #0] 8004b8a: f003 0320 and.w r3, r3, #32 8004b8e: 2b00 cmp r3, #0 8004b90: d11e bne.n 8004bd0 { huart->RxXferCount = 0U; 8004b92: 68fb ldr r3, [r7, #12] 8004b94: 2200 movs r2, #0 8004b96: 85da strh r2, [r3, #46] ; 0x2e /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8004b98: 68fb ldr r3, [r7, #12] 8004b9a: 681b ldr r3, [r3, #0] 8004b9c: 68da ldr r2, [r3, #12] 8004b9e: 68fb ldr r3, [r7, #12] 8004ba0: 681b ldr r3, [r3, #0] 8004ba2: f422 7280 bic.w r2, r2, #256 ; 0x100 8004ba6: 60da str r2, [r3, #12] CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8004ba8: 68fb ldr r3, [r7, #12] 8004baa: 681b ldr r3, [r3, #0] 8004bac: 695a ldr r2, [r3, #20] 8004bae: 68fb ldr r3, [r7, #12] 8004bb0: 681b ldr r3, [r3, #0] 8004bb2: f022 0201 bic.w r2, r2, #1 8004bb6: 615a str r2, [r3, #20] /* Disable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8004bb8: 68fb ldr r3, [r7, #12] 8004bba: 681b ldr r3, [r3, #0] 8004bbc: 695a ldr r2, [r3, #20] 8004bbe: 68fb ldr r3, [r7, #12] 8004bc0: 681b ldr r3, [r3, #0] 8004bc2: f022 0240 bic.w r2, r2, #64 ; 0x40 8004bc6: 615a str r2, [r3, #20] /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8004bc8: 68fb ldr r3, [r7, #12] 8004bca: 2220 movs r2, #32 8004bcc: f883 203a strb.w r2, [r3, #58] ; 0x3a #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 8004bd0: 68f8 ldr r0, [r7, #12] 8004bd2: f7fc ffb1 bl 8001b38 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8004bd6: bf00 nop 8004bd8: 3710 adds r7, #16 8004bda: 46bd mov sp, r7 8004bdc: bd80 pop {r7, pc} 08004bde : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { 8004bde: b580 push {r7, lr} 8004be0: b084 sub sp, #16 8004be2: af00 add r7, sp, #0 8004be4: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8004be6: 687b ldr r3, [r7, #4] 8004be8: 6a5b ldr r3, [r3, #36] ; 0x24 8004bea: 60fb str r3, [r7, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Half complete callback*/ huart->RxHalfCpltCallback(huart); #else /*Call legacy weak Rx Half complete callback*/ HAL_UART_RxHalfCpltCallback(huart); 8004bec: 68f8 ldr r0, [r7, #12] 8004bee: f7ff ff79 bl 8004ae4 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8004bf2: bf00 nop 8004bf4: 3710 adds r7, #16 8004bf6: 46bd mov sp, r7 8004bf8: bd80 pop {r7, pc} 08004bfa : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAError(DMA_HandleTypeDef *hdma) { 8004bfa: b580 push {r7, lr} 8004bfc: b084 sub sp, #16 8004bfe: af00 add r7, sp, #0 8004c00: 6078 str r0, [r7, #4] uint32_t dmarequest = 0x00U; 8004c02: 2300 movs r3, #0 8004c04: 60fb str r3, [r7, #12] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8004c06: 687b ldr r3, [r7, #4] 8004c08: 6a5b ldr r3, [r3, #36] ; 0x24 8004c0a: 60bb str r3, [r7, #8] /* Stop UART DMA Tx request if ongoing */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT); 8004c0c: 68bb ldr r3, [r7, #8] 8004c0e: 681b ldr r3, [r3, #0] 8004c10: 695b ldr r3, [r3, #20] 8004c12: f003 0380 and.w r3, r3, #128 ; 0x80 8004c16: 2b00 cmp r3, #0 8004c18: bf14 ite ne 8004c1a: 2301 movne r3, #1 8004c1c: 2300 moveq r3, #0 8004c1e: b2db uxtb r3, r3 8004c20: 60fb str r3, [r7, #12] if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) 8004c22: 68bb ldr r3, [r7, #8] 8004c24: f893 3039 ldrb.w r3, [r3, #57] ; 0x39 8004c28: b2db uxtb r3, r3 8004c2a: 2b21 cmp r3, #33 ; 0x21 8004c2c: d108 bne.n 8004c40 8004c2e: 68fb ldr r3, [r7, #12] 8004c30: 2b00 cmp r3, #0 8004c32: d005 beq.n 8004c40 { huart->TxXferCount = 0x00U; 8004c34: 68bb ldr r3, [r7, #8] 8004c36: 2200 movs r2, #0 8004c38: 84da strh r2, [r3, #38] ; 0x26 UART_EndTxTransfer(huart); 8004c3a: 68b8 ldr r0, [r7, #8] 8004c3c: f000 f871 bl 8004d22 } /* Stop UART DMA Rx request if ongoing */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 8004c40: 68bb ldr r3, [r7, #8] 8004c42: 681b ldr r3, [r3, #0] 8004c44: 695b ldr r3, [r3, #20] 8004c46: f003 0340 and.w r3, r3, #64 ; 0x40 8004c4a: 2b00 cmp r3, #0 8004c4c: bf14 ite ne 8004c4e: 2301 movne r3, #1 8004c50: 2300 moveq r3, #0 8004c52: b2db uxtb r3, r3 8004c54: 60fb str r3, [r7, #12] if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest) 8004c56: 68bb ldr r3, [r7, #8] 8004c58: f893 303a ldrb.w r3, [r3, #58] ; 0x3a 8004c5c: b2db uxtb r3, r3 8004c5e: 2b22 cmp r3, #34 ; 0x22 8004c60: d108 bne.n 8004c74 8004c62: 68fb ldr r3, [r7, #12] 8004c64: 2b00 cmp r3, #0 8004c66: d005 beq.n 8004c74 { huart->RxXferCount = 0x00U; 8004c68: 68bb ldr r3, [r7, #8] 8004c6a: 2200 movs r2, #0 8004c6c: 85da strh r2, [r3, #46] ; 0x2e UART_EndRxTransfer(huart); 8004c6e: 68b8 ldr r0, [r7, #8] 8004c70: f000 f86c bl 8004d4c } huart->ErrorCode |= HAL_UART_ERROR_DMA; 8004c74: 68bb ldr r3, [r7, #8] 8004c76: 6bdb ldr r3, [r3, #60] ; 0x3c 8004c78: f043 0210 orr.w r2, r3, #16 8004c7c: 68bb ldr r3, [r7, #8] 8004c7e: 63da str r2, [r3, #60] ; 0x3c #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8004c80: 68b8 ldr r0, [r7, #8] 8004c82: f7ff ff38 bl 8004af6 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8004c86: bf00 nop 8004c88: 3710 adds r7, #16 8004c8a: 46bd mov sp, r7 8004c8c: bd80 pop {r7, pc} 08004c8e : * @param Tickstart Tick start value * @param Timeout Timeout duration * @retval HAL status */ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { 8004c8e: b580 push {r7, lr} 8004c90: b084 sub sp, #16 8004c92: af00 add r7, sp, #0 8004c94: 60f8 str r0, [r7, #12] 8004c96: 60b9 str r1, [r7, #8] 8004c98: 603b str r3, [r7, #0] 8004c9a: 4613 mov r3, r2 8004c9c: 71fb strb r3, [r7, #7] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8004c9e: e02c b.n 8004cfa { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 8004ca0: 69bb ldr r3, [r7, #24] 8004ca2: f1b3 3fff cmp.w r3, #4294967295 8004ca6: d028 beq.n 8004cfa { if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) 8004ca8: 69bb ldr r3, [r7, #24] 8004caa: 2b00 cmp r3, #0 8004cac: d007 beq.n 8004cbe 8004cae: f7fd f88d bl 8001dcc 8004cb2: 4602 mov r2, r0 8004cb4: 683b ldr r3, [r7, #0] 8004cb6: 1ad3 subs r3, r2, r3 8004cb8: 69ba ldr r2, [r7, #24] 8004cba: 429a cmp r2, r3 8004cbc: d21d bcs.n 8004cfa { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); 8004cbe: 68fb ldr r3, [r7, #12] 8004cc0: 681b ldr r3, [r3, #0] 8004cc2: 68da ldr r2, [r3, #12] 8004cc4: 68fb ldr r3, [r7, #12] 8004cc6: 681b ldr r3, [r3, #0] 8004cc8: f422 72d0 bic.w r2, r2, #416 ; 0x1a0 8004ccc: 60da str r2, [r3, #12] CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8004cce: 68fb ldr r3, [r7, #12] 8004cd0: 681b ldr r3, [r3, #0] 8004cd2: 695a ldr r2, [r3, #20] 8004cd4: 68fb ldr r3, [r7, #12] 8004cd6: 681b ldr r3, [r3, #0] 8004cd8: f022 0201 bic.w r2, r2, #1 8004cdc: 615a str r2, [r3, #20] huart->gState = HAL_UART_STATE_READY; 8004cde: 68fb ldr r3, [r7, #12] 8004ce0: 2220 movs r2, #32 8004ce2: f883 2039 strb.w r2, [r3, #57] ; 0x39 huart->RxState = HAL_UART_STATE_READY; 8004ce6: 68fb ldr r3, [r7, #12] 8004ce8: 2220 movs r2, #32 8004cea: f883 203a strb.w r2, [r3, #58] ; 0x3a /* Process Unlocked */ __HAL_UNLOCK(huart); 8004cee: 68fb ldr r3, [r7, #12] 8004cf0: 2200 movs r2, #0 8004cf2: f883 2038 strb.w r2, [r3, #56] ; 0x38 return HAL_TIMEOUT; 8004cf6: 2303 movs r3, #3 8004cf8: e00f b.n 8004d1a while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8004cfa: 68fb ldr r3, [r7, #12] 8004cfc: 681b ldr r3, [r3, #0] 8004cfe: 681a ldr r2, [r3, #0] 8004d00: 68bb ldr r3, [r7, #8] 8004d02: 4013 ands r3, r2 8004d04: 68ba ldr r2, [r7, #8] 8004d06: 429a cmp r2, r3 8004d08: bf0c ite eq 8004d0a: 2301 moveq r3, #1 8004d0c: 2300 movne r3, #0 8004d0e: b2db uxtb r3, r3 8004d10: 461a mov r2, r3 8004d12: 79fb ldrb r3, [r7, #7] 8004d14: 429a cmp r2, r3 8004d16: d0c3 beq.n 8004ca0 } } } return HAL_OK; 8004d18: 2300 movs r3, #0 } 8004d1a: 4618 mov r0, r3 8004d1c: 3710 adds r7, #16 8004d1e: 46bd mov sp, r7 8004d20: bd80 pop {r7, pc} 08004d22 : * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). * @param huart UART handle. * @retval None */ static void UART_EndTxTransfer(UART_HandleTypeDef *huart) { 8004d22: b480 push {r7} 8004d24: b083 sub sp, #12 8004d26: af00 add r7, sp, #0 8004d28: 6078 str r0, [r7, #4] /* Disable TXEIE and TCIE interrupts */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); 8004d2a: 687b ldr r3, [r7, #4] 8004d2c: 681b ldr r3, [r3, #0] 8004d2e: 68da ldr r2, [r3, #12] 8004d30: 687b ldr r3, [r7, #4] 8004d32: 681b ldr r3, [r3, #0] 8004d34: f022 02c0 bic.w r2, r2, #192 ; 0xc0 8004d38: 60da str r2, [r3, #12] /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8004d3a: 687b ldr r3, [r7, #4] 8004d3c: 2220 movs r2, #32 8004d3e: f883 2039 strb.w r2, [r3, #57] ; 0x39 } 8004d42: bf00 nop 8004d44: 370c adds r7, #12 8004d46: 46bd mov sp, r7 8004d48: bc80 pop {r7} 8004d4a: 4770 bx lr 08004d4c : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 8004d4c: b480 push {r7} 8004d4e: b083 sub sp, #12 8004d50: af00 add r7, sp, #0 8004d52: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 8004d54: 687b ldr r3, [r7, #4] 8004d56: 681b ldr r3, [r3, #0] 8004d58: 68da ldr r2, [r3, #12] 8004d5a: 687b ldr r3, [r7, #4] 8004d5c: 681b ldr r3, [r3, #0] 8004d5e: f422 7290 bic.w r2, r2, #288 ; 0x120 8004d62: 60da str r2, [r3, #12] CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8004d64: 687b ldr r3, [r7, #4] 8004d66: 681b ldr r3, [r3, #0] 8004d68: 695a ldr r2, [r3, #20] 8004d6a: 687b ldr r3, [r7, #4] 8004d6c: 681b ldr r3, [r3, #0] 8004d6e: f022 0201 bic.w r2, r2, #1 8004d72: 615a str r2, [r3, #20] /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8004d74: 687b ldr r3, [r7, #4] 8004d76: 2220 movs r2, #32 8004d78: f883 203a strb.w r2, [r3, #58] ; 0x3a } 8004d7c: bf00 nop 8004d7e: 370c adds r7, #12 8004d80: 46bd mov sp, r7 8004d82: bc80 pop {r7} 8004d84: 4770 bx lr 08004d86 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { 8004d86: b580 push {r7, lr} 8004d88: b084 sub sp, #16 8004d8a: af00 add r7, sp, #0 8004d8c: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8004d8e: 687b ldr r3, [r7, #4] 8004d90: 6a5b ldr r3, [r3, #36] ; 0x24 8004d92: 60fb str r3, [r7, #12] huart->RxXferCount = 0x00U; 8004d94: 68fb ldr r3, [r7, #12] 8004d96: 2200 movs r2, #0 8004d98: 85da strh r2, [r3, #46] ; 0x2e huart->TxXferCount = 0x00U; 8004d9a: 68fb ldr r3, [r7, #12] 8004d9c: 2200 movs r2, #0 8004d9e: 84da strh r2, [r3, #38] ; 0x26 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8004da0: 68f8 ldr r0, [r7, #12] 8004da2: f7ff fea8 bl 8004af6 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8004da6: bf00 nop 8004da8: 3710 adds r7, #16 8004daa: 46bd mov sp, r7 8004dac: bd80 pop {r7, pc} 08004dae : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) { 8004dae: b480 push {r7} 8004db0: b085 sub sp, #20 8004db2: af00 add r7, sp, #0 8004db4: 6078 str r0, [r7, #4] uint16_t *tmp; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 8004db6: 687b ldr r3, [r7, #4] 8004db8: f893 3039 ldrb.w r3, [r3, #57] ; 0x39 8004dbc: b2db uxtb r3, r3 8004dbe: 2b21 cmp r3, #33 ; 0x21 8004dc0: d144 bne.n 8004e4c { if (huart->Init.WordLength == UART_WORDLENGTH_9B) 8004dc2: 687b ldr r3, [r7, #4] 8004dc4: 689b ldr r3, [r3, #8] 8004dc6: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8004dca: d11a bne.n 8004e02 { tmp = (uint16_t *) huart->pTxBuffPtr; 8004dcc: 687b ldr r3, [r7, #4] 8004dce: 6a1b ldr r3, [r3, #32] 8004dd0: 60fb str r3, [r7, #12] huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); 8004dd2: 68fb ldr r3, [r7, #12] 8004dd4: 881b ldrh r3, [r3, #0] 8004dd6: 461a mov r2, r3 8004dd8: 687b ldr r3, [r7, #4] 8004dda: 681b ldr r3, [r3, #0] 8004ddc: f3c2 0208 ubfx r2, r2, #0, #9 8004de0: 605a str r2, [r3, #4] if (huart->Init.Parity == UART_PARITY_NONE) 8004de2: 687b ldr r3, [r7, #4] 8004de4: 691b ldr r3, [r3, #16] 8004de6: 2b00 cmp r3, #0 8004de8: d105 bne.n 8004df6 { huart->pTxBuffPtr += 2U; 8004dea: 687b ldr r3, [r7, #4] 8004dec: 6a1b ldr r3, [r3, #32] 8004dee: 1c9a adds r2, r3, #2 8004df0: 687b ldr r3, [r7, #4] 8004df2: 621a str r2, [r3, #32] 8004df4: e00e b.n 8004e14 } else { huart->pTxBuffPtr += 1U; 8004df6: 687b ldr r3, [r7, #4] 8004df8: 6a1b ldr r3, [r3, #32] 8004dfa: 1c5a adds r2, r3, #1 8004dfc: 687b ldr r3, [r7, #4] 8004dfe: 621a str r2, [r3, #32] 8004e00: e008 b.n 8004e14 } } else { huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF); 8004e02: 687b ldr r3, [r7, #4] 8004e04: 6a1b ldr r3, [r3, #32] 8004e06: 1c59 adds r1, r3, #1 8004e08: 687a ldr r2, [r7, #4] 8004e0a: 6211 str r1, [r2, #32] 8004e0c: 781a ldrb r2, [r3, #0] 8004e0e: 687b ldr r3, [r7, #4] 8004e10: 681b ldr r3, [r3, #0] 8004e12: 605a str r2, [r3, #4] } if (--huart->TxXferCount == 0U) 8004e14: 687b ldr r3, [r7, #4] 8004e16: 8cdb ldrh r3, [r3, #38] ; 0x26 8004e18: b29b uxth r3, r3 8004e1a: 3b01 subs r3, #1 8004e1c: b29b uxth r3, r3 8004e1e: 687a ldr r2, [r7, #4] 8004e20: 4619 mov r1, r3 8004e22: 84d1 strh r1, [r2, #38] ; 0x26 8004e24: 2b00 cmp r3, #0 8004e26: d10f bne.n 8004e48 { /* Disable the UART Transmit Complete Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); 8004e28: 687b ldr r3, [r7, #4] 8004e2a: 681b ldr r3, [r3, #0] 8004e2c: 68da ldr r2, [r3, #12] 8004e2e: 687b ldr r3, [r7, #4] 8004e30: 681b ldr r3, [r3, #0] 8004e32: f022 0280 bic.w r2, r2, #128 ; 0x80 8004e36: 60da str r2, [r3, #12] /* Enable the UART Transmit Complete Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_TC); 8004e38: 687b ldr r3, [r7, #4] 8004e3a: 681b ldr r3, [r3, #0] 8004e3c: 68da ldr r2, [r3, #12] 8004e3e: 687b ldr r3, [r7, #4] 8004e40: 681b ldr r3, [r3, #0] 8004e42: f042 0240 orr.w r2, r2, #64 ; 0x40 8004e46: 60da str r2, [r3, #12] } return HAL_OK; 8004e48: 2300 movs r3, #0 8004e4a: e000 b.n 8004e4e } else { return HAL_BUSY; 8004e4c: 2302 movs r3, #2 } } 8004e4e: 4618 mov r0, r3 8004e50: 3714 adds r7, #20 8004e52: 46bd mov sp, r7 8004e54: bc80 pop {r7} 8004e56: 4770 bx lr 08004e58 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) { 8004e58: b580 push {r7, lr} 8004e5a: b082 sub sp, #8 8004e5c: af00 add r7, sp, #0 8004e5e: 6078 str r0, [r7, #4] /* Disable the UART Transmit Complete Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TC); 8004e60: 687b ldr r3, [r7, #4] 8004e62: 681b ldr r3, [r3, #0] 8004e64: 68da ldr r2, [r3, #12] 8004e66: 687b ldr r3, [r7, #4] 8004e68: 681b ldr r3, [r3, #0] 8004e6a: f022 0240 bic.w r2, r2, #64 ; 0x40 8004e6e: 60da str r2, [r3, #12] /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8004e70: 687b ldr r3, [r7, #4] 8004e72: 2220 movs r2, #32 8004e74: f883 2039 strb.w r2, [r3, #57] ; 0x39 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); 8004e78: 6878 ldr r0, [r7, #4] 8004e7a: f7ff fe21 bl 8004ac0 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return HAL_OK; 8004e7e: 2300 movs r3, #0 } 8004e80: 4618 mov r0, r3 8004e82: 3708 adds r7, #8 8004e84: 46bd mov sp, r7 8004e86: bd80 pop {r7, pc} 08004e88 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) { 8004e88: b580 push {r7, lr} 8004e8a: b084 sub sp, #16 8004e8c: af00 add r7, sp, #0 8004e8e: 6078 str r0, [r7, #4] uint16_t *tmp; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 8004e90: 687b ldr r3, [r7, #4] 8004e92: f893 303a ldrb.w r3, [r3, #58] ; 0x3a 8004e96: b2db uxtb r3, r3 8004e98: 2b22 cmp r3, #34 ; 0x22 8004e9a: d171 bne.n 8004f80 { if (huart->Init.WordLength == UART_WORDLENGTH_9B) 8004e9c: 687b ldr r3, [r7, #4] 8004e9e: 689b ldr r3, [r3, #8] 8004ea0: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8004ea4: d123 bne.n 8004eee { tmp = (uint16_t *) huart->pRxBuffPtr; 8004ea6: 687b ldr r3, [r7, #4] 8004ea8: 6a9b ldr r3, [r3, #40] ; 0x28 8004eaa: 60fb str r3, [r7, #12] if (huart->Init.Parity == UART_PARITY_NONE) 8004eac: 687b ldr r3, [r7, #4] 8004eae: 691b ldr r3, [r3, #16] 8004eb0: 2b00 cmp r3, #0 8004eb2: d10e bne.n 8004ed2 { *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); 8004eb4: 687b ldr r3, [r7, #4] 8004eb6: 681b ldr r3, [r3, #0] 8004eb8: 685b ldr r3, [r3, #4] 8004eba: b29b uxth r3, r3 8004ebc: f3c3 0308 ubfx r3, r3, #0, #9 8004ec0: b29a uxth r2, r3 8004ec2: 68fb ldr r3, [r7, #12] 8004ec4: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 8004ec6: 687b ldr r3, [r7, #4] 8004ec8: 6a9b ldr r3, [r3, #40] ; 0x28 8004eca: 1c9a adds r2, r3, #2 8004ecc: 687b ldr r3, [r7, #4] 8004ece: 629a str r2, [r3, #40] ; 0x28 8004ed0: e029 b.n 8004f26 } else { *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF); 8004ed2: 687b ldr r3, [r7, #4] 8004ed4: 681b ldr r3, [r3, #0] 8004ed6: 685b ldr r3, [r3, #4] 8004ed8: b29b uxth r3, r3 8004eda: b2db uxtb r3, r3 8004edc: b29a uxth r2, r3 8004ede: 68fb ldr r3, [r7, #12] 8004ee0: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 1U; 8004ee2: 687b ldr r3, [r7, #4] 8004ee4: 6a9b ldr r3, [r3, #40] ; 0x28 8004ee6: 1c5a adds r2, r3, #1 8004ee8: 687b ldr r3, [r7, #4] 8004eea: 629a str r2, [r3, #40] ; 0x28 8004eec: e01b b.n 8004f26 } } else { if (huart->Init.Parity == UART_PARITY_NONE) 8004eee: 687b ldr r3, [r7, #4] 8004ef0: 691b ldr r3, [r3, #16] 8004ef2: 2b00 cmp r3, #0 8004ef4: d10a bne.n 8004f0c { *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); 8004ef6: 687b ldr r3, [r7, #4] 8004ef8: 681b ldr r3, [r3, #0] 8004efa: 6858 ldr r0, [r3, #4] 8004efc: 687b ldr r3, [r7, #4] 8004efe: 6a9b ldr r3, [r3, #40] ; 0x28 8004f00: 1c59 adds r1, r3, #1 8004f02: 687a ldr r2, [r7, #4] 8004f04: 6291 str r1, [r2, #40] ; 0x28 8004f06: b2c2 uxtb r2, r0 8004f08: 701a strb r2, [r3, #0] 8004f0a: e00c b.n 8004f26 } else { *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); 8004f0c: 687b ldr r3, [r7, #4] 8004f0e: 681b ldr r3, [r3, #0] 8004f10: 685b ldr r3, [r3, #4] 8004f12: b2da uxtb r2, r3 8004f14: 687b ldr r3, [r7, #4] 8004f16: 6a9b ldr r3, [r3, #40] ; 0x28 8004f18: 1c58 adds r0, r3, #1 8004f1a: 6879 ldr r1, [r7, #4] 8004f1c: 6288 str r0, [r1, #40] ; 0x28 8004f1e: f002 027f and.w r2, r2, #127 ; 0x7f 8004f22: b2d2 uxtb r2, r2 8004f24: 701a strb r2, [r3, #0] } } if (--huart->RxXferCount == 0U) 8004f26: 687b ldr r3, [r7, #4] 8004f28: 8ddb ldrh r3, [r3, #46] ; 0x2e 8004f2a: b29b uxth r3, r3 8004f2c: 3b01 subs r3, #1 8004f2e: b29b uxth r3, r3 8004f30: 687a ldr r2, [r7, #4] 8004f32: 4619 mov r1, r3 8004f34: 85d1 strh r1, [r2, #46] ; 0x2e 8004f36: 2b00 cmp r3, #0 8004f38: d120 bne.n 8004f7c { /* Disable the UART Data Register not empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); 8004f3a: 687b ldr r3, [r7, #4] 8004f3c: 681b ldr r3, [r3, #0] 8004f3e: 68da ldr r2, [r3, #12] 8004f40: 687b ldr r3, [r7, #4] 8004f42: 681b ldr r3, [r3, #0] 8004f44: f022 0220 bic.w r2, r2, #32 8004f48: 60da str r2, [r3, #12] /* Disable the UART Parity Error Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_PE); 8004f4a: 687b ldr r3, [r7, #4] 8004f4c: 681b ldr r3, [r3, #0] 8004f4e: 68da ldr r2, [r3, #12] 8004f50: 687b ldr r3, [r7, #4] 8004f52: 681b ldr r3, [r3, #0] 8004f54: f422 7280 bic.w r2, r2, #256 ; 0x100 8004f58: 60da str r2, [r3, #12] /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); 8004f5a: 687b ldr r3, [r7, #4] 8004f5c: 681b ldr r3, [r3, #0] 8004f5e: 695a ldr r2, [r3, #20] 8004f60: 687b ldr r3, [r7, #4] 8004f62: 681b ldr r3, [r3, #0] 8004f64: f022 0201 bic.w r2, r2, #1 8004f68: 615a str r2, [r3, #20] /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8004f6a: 687b ldr r3, [r7, #4] 8004f6c: 2220 movs r2, #32 8004f6e: f883 203a strb.w r2, [r3, #58] ; 0x3a #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 8004f72: 6878 ldr r0, [r7, #4] 8004f74: f7fc fde0 bl 8001b38 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return HAL_OK; 8004f78: 2300 movs r3, #0 8004f7a: e002 b.n 8004f82 } return HAL_OK; 8004f7c: 2300 movs r3, #0 8004f7e: e000 b.n 8004f82 } else { return HAL_BUSY; 8004f80: 2302 movs r3, #2 } } 8004f82: 4618 mov r0, r3 8004f84: 3710 adds r7, #16 8004f86: 46bd mov sp, r7 8004f88: bd80 pop {r7, pc} ... 08004f8c : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_SetConfig(UART_HandleTypeDef *huart) { 8004f8c: b580 push {r7, lr} 8004f8e: b084 sub sp, #16 8004f90: af00 add r7, sp, #0 8004f92: 6078 str r0, [r7, #4] assert_param(IS_UART_MODE(huart->Init.Mode)); /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 8004f94: 687b ldr r3, [r7, #4] 8004f96: 681b ldr r3, [r3, #0] 8004f98: 691b ldr r3, [r3, #16] 8004f9a: f423 5140 bic.w r1, r3, #12288 ; 0x3000 8004f9e: 687b ldr r3, [r7, #4] 8004fa0: 68da ldr r2, [r3, #12] 8004fa2: 687b ldr r3, [r7, #4] 8004fa4: 681b ldr r3, [r3, #0] 8004fa6: 430a orrs r2, r1 8004fa8: 611a str r2, [r3, #16] Set PCE and PS bits according to huart->Init.Parity value Set TE and RE bits according to huart->Init.Mode value Set OVER8 bit according to huart->Init.OverSampling value */ #if defined(USART_CR1_OVER8) tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; 8004faa: 687b ldr r3, [r7, #4] 8004fac: 689a ldr r2, [r3, #8] 8004fae: 687b ldr r3, [r7, #4] 8004fb0: 691b ldr r3, [r3, #16] 8004fb2: 431a orrs r2, r3 8004fb4: 687b ldr r3, [r7, #4] 8004fb6: 695b ldr r3, [r3, #20] 8004fb8: 431a orrs r2, r3 8004fba: 687b ldr r3, [r7, #4] 8004fbc: 69db ldr r3, [r3, #28] 8004fbe: 4313 orrs r3, r2 8004fc0: 60fb str r3, [r7, #12] MODIFY_REG(huart->Instance->CR1, 8004fc2: 687b ldr r3, [r7, #4] 8004fc4: 681b ldr r3, [r3, #0] 8004fc6: 68db ldr r3, [r3, #12] 8004fc8: f423 4316 bic.w r3, r3, #38400 ; 0x9600 8004fcc: f023 030c bic.w r3, r3, #12 8004fd0: 687a ldr r2, [r7, #4] 8004fd2: 6812 ldr r2, [r2, #0] 8004fd4: 68f9 ldr r1, [r7, #12] 8004fd6: 430b orrs r3, r1 8004fd8: 60d3 str r3, [r2, #12] tmpreg); #endif /* USART_CR1_OVER8 */ /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); 8004fda: 687b ldr r3, [r7, #4] 8004fdc: 681b ldr r3, [r3, #0] 8004fde: 695b ldr r3, [r3, #20] 8004fe0: f423 7140 bic.w r1, r3, #768 ; 0x300 8004fe4: 687b ldr r3, [r7, #4] 8004fe6: 699a ldr r2, [r3, #24] 8004fe8: 687b ldr r3, [r7, #4] 8004fea: 681b ldr r3, [r3, #0] 8004fec: 430a orrs r2, r1 8004fee: 615a str r2, [r3, #20] #if defined(USART_CR1_OVER8) /* Check the Over Sampling */ if(huart->Init.OverSampling == UART_OVERSAMPLING_8) 8004ff0: 687b ldr r3, [r7, #4] 8004ff2: 69db ldr r3, [r3, #28] 8004ff4: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 8004ff8: f040 80a5 bne.w 8005146 { /*-------------------------- USART BRR Configuration ---------------------*/ if(huart->Instance == USART1) 8004ffc: 687b ldr r3, [r7, #4] 8004ffe: 681b ldr r3, [r3, #0] 8005000: 4aa4 ldr r2, [pc, #656] ; (8005294 ) 8005002: 4293 cmp r3, r2 8005004: d14f bne.n 80050a6 { pclk = HAL_RCC_GetPCLK2Freq(); 8005006: f7fe fe8d bl 8003d24 800500a: 60b8 str r0, [r7, #8] huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate); 800500c: 68ba ldr r2, [r7, #8] 800500e: 4613 mov r3, r2 8005010: 009b lsls r3, r3, #2 8005012: 4413 add r3, r2 8005014: 009a lsls r2, r3, #2 8005016: 441a add r2, r3 8005018: 687b ldr r3, [r7, #4] 800501a: 685b ldr r3, [r3, #4] 800501c: 005b lsls r3, r3, #1 800501e: fbb2 f3f3 udiv r3, r2, r3 8005022: 4a9d ldr r2, [pc, #628] ; (8005298 ) 8005024: fba2 2303 umull r2, r3, r2, r3 8005028: 095b lsrs r3, r3, #5 800502a: 0119 lsls r1, r3, #4 800502c: 68ba ldr r2, [r7, #8] 800502e: 4613 mov r3, r2 8005030: 009b lsls r3, r3, #2 8005032: 4413 add r3, r2 8005034: 009a lsls r2, r3, #2 8005036: 441a add r2, r3 8005038: 687b ldr r3, [r7, #4] 800503a: 685b ldr r3, [r3, #4] 800503c: 005b lsls r3, r3, #1 800503e: fbb2 f2f3 udiv r2, r2, r3 8005042: 4b95 ldr r3, [pc, #596] ; (8005298 ) 8005044: fba3 0302 umull r0, r3, r3, r2 8005048: 095b lsrs r3, r3, #5 800504a: 2064 movs r0, #100 ; 0x64 800504c: fb00 f303 mul.w r3, r0, r3 8005050: 1ad3 subs r3, r2, r3 8005052: 00db lsls r3, r3, #3 8005054: 3332 adds r3, #50 ; 0x32 8005056: 4a90 ldr r2, [pc, #576] ; (8005298 ) 8005058: fba2 2303 umull r2, r3, r2, r3 800505c: 095b lsrs r3, r3, #5 800505e: 005b lsls r3, r3, #1 8005060: f403 73f8 and.w r3, r3, #496 ; 0x1f0 8005064: 4419 add r1, r3 8005066: 68ba ldr r2, [r7, #8] 8005068: 4613 mov r3, r2 800506a: 009b lsls r3, r3, #2 800506c: 4413 add r3, r2 800506e: 009a lsls r2, r3, #2 8005070: 441a add r2, r3 8005072: 687b ldr r3, [r7, #4] 8005074: 685b ldr r3, [r3, #4] 8005076: 005b lsls r3, r3, #1 8005078: fbb2 f2f3 udiv r2, r2, r3 800507c: 4b86 ldr r3, [pc, #536] ; (8005298 ) 800507e: fba3 0302 umull r0, r3, r3, r2 8005082: 095b lsrs r3, r3, #5 8005084: 2064 movs r0, #100 ; 0x64 8005086: fb00 f303 mul.w r3, r0, r3 800508a: 1ad3 subs r3, r2, r3 800508c: 00db lsls r3, r3, #3 800508e: 3332 adds r3, #50 ; 0x32 8005090: 4a81 ldr r2, [pc, #516] ; (8005298 ) 8005092: fba2 2303 umull r2, r3, r2, r3 8005096: 095b lsrs r3, r3, #5 8005098: f003 0207 and.w r2, r3, #7 800509c: 687b ldr r3, [r7, #4] 800509e: 681b ldr r3, [r3, #0] 80050a0: 440a add r2, r1 80050a2: 609a str r2, [r3, #8] { pclk = HAL_RCC_GetPCLK1Freq(); huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); } #endif /* USART_CR1_OVER8 */ } 80050a4: e0f1 b.n 800528a pclk = HAL_RCC_GetPCLK1Freq(); 80050a6: f7fe fe29 bl 8003cfc 80050aa: 60b8 str r0, [r7, #8] huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate); 80050ac: 68ba ldr r2, [r7, #8] 80050ae: 4613 mov r3, r2 80050b0: 009b lsls r3, r3, #2 80050b2: 4413 add r3, r2 80050b4: 009a lsls r2, r3, #2 80050b6: 441a add r2, r3 80050b8: 687b ldr r3, [r7, #4] 80050ba: 685b ldr r3, [r3, #4] 80050bc: 005b lsls r3, r3, #1 80050be: fbb2 f3f3 udiv r3, r2, r3 80050c2: 4a75 ldr r2, [pc, #468] ; (8005298 ) 80050c4: fba2 2303 umull r2, r3, r2, r3 80050c8: 095b lsrs r3, r3, #5 80050ca: 0119 lsls r1, r3, #4 80050cc: 68ba ldr r2, [r7, #8] 80050ce: 4613 mov r3, r2 80050d0: 009b lsls r3, r3, #2 80050d2: 4413 add r3, r2 80050d4: 009a lsls r2, r3, #2 80050d6: 441a add r2, r3 80050d8: 687b ldr r3, [r7, #4] 80050da: 685b ldr r3, [r3, #4] 80050dc: 005b lsls r3, r3, #1 80050de: fbb2 f2f3 udiv r2, r2, r3 80050e2: 4b6d ldr r3, [pc, #436] ; (8005298 ) 80050e4: fba3 0302 umull r0, r3, r3, r2 80050e8: 095b lsrs r3, r3, #5 80050ea: 2064 movs r0, #100 ; 0x64 80050ec: fb00 f303 mul.w r3, r0, r3 80050f0: 1ad3 subs r3, r2, r3 80050f2: 00db lsls r3, r3, #3 80050f4: 3332 adds r3, #50 ; 0x32 80050f6: 4a68 ldr r2, [pc, #416] ; (8005298 ) 80050f8: fba2 2303 umull r2, r3, r2, r3 80050fc: 095b lsrs r3, r3, #5 80050fe: 005b lsls r3, r3, #1 8005100: f403 73f8 and.w r3, r3, #496 ; 0x1f0 8005104: 4419 add r1, r3 8005106: 68ba ldr r2, [r7, #8] 8005108: 4613 mov r3, r2 800510a: 009b lsls r3, r3, #2 800510c: 4413 add r3, r2 800510e: 009a lsls r2, r3, #2 8005110: 441a add r2, r3 8005112: 687b ldr r3, [r7, #4] 8005114: 685b ldr r3, [r3, #4] 8005116: 005b lsls r3, r3, #1 8005118: fbb2 f2f3 udiv r2, r2, r3 800511c: 4b5e ldr r3, [pc, #376] ; (8005298 ) 800511e: fba3 0302 umull r0, r3, r3, r2 8005122: 095b lsrs r3, r3, #5 8005124: 2064 movs r0, #100 ; 0x64 8005126: fb00 f303 mul.w r3, r0, r3 800512a: 1ad3 subs r3, r2, r3 800512c: 00db lsls r3, r3, #3 800512e: 3332 adds r3, #50 ; 0x32 8005130: 4a59 ldr r2, [pc, #356] ; (8005298 ) 8005132: fba2 2303 umull r2, r3, r2, r3 8005136: 095b lsrs r3, r3, #5 8005138: f003 0207 and.w r2, r3, #7 800513c: 687b ldr r3, [r7, #4] 800513e: 681b ldr r3, [r3, #0] 8005140: 440a add r2, r1 8005142: 609a str r2, [r3, #8] } 8005144: e0a1 b.n 800528a if(huart->Instance == USART1) 8005146: 687b ldr r3, [r7, #4] 8005148: 681b ldr r3, [r3, #0] 800514a: 4a52 ldr r2, [pc, #328] ; (8005294 ) 800514c: 4293 cmp r3, r2 800514e: d14e bne.n 80051ee pclk = HAL_RCC_GetPCLK2Freq(); 8005150: f7fe fde8 bl 8003d24 8005154: 60b8 str r0, [r7, #8] huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); 8005156: 68ba ldr r2, [r7, #8] 8005158: 4613 mov r3, r2 800515a: 009b lsls r3, r3, #2 800515c: 4413 add r3, r2 800515e: 009a lsls r2, r3, #2 8005160: 441a add r2, r3 8005162: 687b ldr r3, [r7, #4] 8005164: 685b ldr r3, [r3, #4] 8005166: 009b lsls r3, r3, #2 8005168: fbb2 f3f3 udiv r3, r2, r3 800516c: 4a4a ldr r2, [pc, #296] ; (8005298 ) 800516e: fba2 2303 umull r2, r3, r2, r3 8005172: 095b lsrs r3, r3, #5 8005174: 0119 lsls r1, r3, #4 8005176: 68ba ldr r2, [r7, #8] 8005178: 4613 mov r3, r2 800517a: 009b lsls r3, r3, #2 800517c: 4413 add r3, r2 800517e: 009a lsls r2, r3, #2 8005180: 441a add r2, r3 8005182: 687b ldr r3, [r7, #4] 8005184: 685b ldr r3, [r3, #4] 8005186: 009b lsls r3, r3, #2 8005188: fbb2 f2f3 udiv r2, r2, r3 800518c: 4b42 ldr r3, [pc, #264] ; (8005298 ) 800518e: fba3 0302 umull r0, r3, r3, r2 8005192: 095b lsrs r3, r3, #5 8005194: 2064 movs r0, #100 ; 0x64 8005196: fb00 f303 mul.w r3, r0, r3 800519a: 1ad3 subs r3, r2, r3 800519c: 011b lsls r3, r3, #4 800519e: 3332 adds r3, #50 ; 0x32 80051a0: 4a3d ldr r2, [pc, #244] ; (8005298 ) 80051a2: fba2 2303 umull r2, r3, r2, r3 80051a6: 095b lsrs r3, r3, #5 80051a8: f003 03f0 and.w r3, r3, #240 ; 0xf0 80051ac: 4419 add r1, r3 80051ae: 68ba ldr r2, [r7, #8] 80051b0: 4613 mov r3, r2 80051b2: 009b lsls r3, r3, #2 80051b4: 4413 add r3, r2 80051b6: 009a lsls r2, r3, #2 80051b8: 441a add r2, r3 80051ba: 687b ldr r3, [r7, #4] 80051bc: 685b ldr r3, [r3, #4] 80051be: 009b lsls r3, r3, #2 80051c0: fbb2 f2f3 udiv r2, r2, r3 80051c4: 4b34 ldr r3, [pc, #208] ; (8005298 ) 80051c6: fba3 0302 umull r0, r3, r3, r2 80051ca: 095b lsrs r3, r3, #5 80051cc: 2064 movs r0, #100 ; 0x64 80051ce: fb00 f303 mul.w r3, r0, r3 80051d2: 1ad3 subs r3, r2, r3 80051d4: 011b lsls r3, r3, #4 80051d6: 3332 adds r3, #50 ; 0x32 80051d8: 4a2f ldr r2, [pc, #188] ; (8005298 ) 80051da: fba2 2303 umull r2, r3, r2, r3 80051de: 095b lsrs r3, r3, #5 80051e0: f003 020f and.w r2, r3, #15 80051e4: 687b ldr r3, [r7, #4] 80051e6: 681b ldr r3, [r3, #0] 80051e8: 440a add r2, r1 80051ea: 609a str r2, [r3, #8] } 80051ec: e04d b.n 800528a pclk = HAL_RCC_GetPCLK1Freq(); 80051ee: f7fe fd85 bl 8003cfc 80051f2: 60b8 str r0, [r7, #8] huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); 80051f4: 68ba ldr r2, [r7, #8] 80051f6: 4613 mov r3, r2 80051f8: 009b lsls r3, r3, #2 80051fa: 4413 add r3, r2 80051fc: 009a lsls r2, r3, #2 80051fe: 441a add r2, r3 8005200: 687b ldr r3, [r7, #4] 8005202: 685b ldr r3, [r3, #4] 8005204: 009b lsls r3, r3, #2 8005206: fbb2 f3f3 udiv r3, r2, r3 800520a: 4a23 ldr r2, [pc, #140] ; (8005298 ) 800520c: fba2 2303 umull r2, r3, r2, r3 8005210: 095b lsrs r3, r3, #5 8005212: 0119 lsls r1, r3, #4 8005214: 68ba ldr r2, [r7, #8] 8005216: 4613 mov r3, r2 8005218: 009b lsls r3, r3, #2 800521a: 4413 add r3, r2 800521c: 009a lsls r2, r3, #2 800521e: 441a add r2, r3 8005220: 687b ldr r3, [r7, #4] 8005222: 685b ldr r3, [r3, #4] 8005224: 009b lsls r3, r3, #2 8005226: fbb2 f2f3 udiv r2, r2, r3 800522a: 4b1b ldr r3, [pc, #108] ; (8005298 ) 800522c: fba3 0302 umull r0, r3, r3, r2 8005230: 095b lsrs r3, r3, #5 8005232: 2064 movs r0, #100 ; 0x64 8005234: fb00 f303 mul.w r3, r0, r3 8005238: 1ad3 subs r3, r2, r3 800523a: 011b lsls r3, r3, #4 800523c: 3332 adds r3, #50 ; 0x32 800523e: 4a16 ldr r2, [pc, #88] ; (8005298 ) 8005240: fba2 2303 umull r2, r3, r2, r3 8005244: 095b lsrs r3, r3, #5 8005246: f003 03f0 and.w r3, r3, #240 ; 0xf0 800524a: 4419 add r1, r3 800524c: 68ba ldr r2, [r7, #8] 800524e: 4613 mov r3, r2 8005250: 009b lsls r3, r3, #2 8005252: 4413 add r3, r2 8005254: 009a lsls r2, r3, #2 8005256: 441a add r2, r3 8005258: 687b ldr r3, [r7, #4] 800525a: 685b ldr r3, [r3, #4] 800525c: 009b lsls r3, r3, #2 800525e: fbb2 f2f3 udiv r2, r2, r3 8005262: 4b0d ldr r3, [pc, #52] ; (8005298 ) 8005264: fba3 0302 umull r0, r3, r3, r2 8005268: 095b lsrs r3, r3, #5 800526a: 2064 movs r0, #100 ; 0x64 800526c: fb00 f303 mul.w r3, r0, r3 8005270: 1ad3 subs r3, r2, r3 8005272: 011b lsls r3, r3, #4 8005274: 3332 adds r3, #50 ; 0x32 8005276: 4a08 ldr r2, [pc, #32] ; (8005298 ) 8005278: fba2 2303 umull r2, r3, r2, r3 800527c: 095b lsrs r3, r3, #5 800527e: f003 020f and.w r2, r3, #15 8005282: 687b ldr r3, [r7, #4] 8005284: 681b ldr r3, [r3, #0] 8005286: 440a add r2, r1 8005288: 609a str r2, [r3, #8] } 800528a: bf00 nop 800528c: 3710 adds r7, #16 800528e: 46bd mov sp, r7 8005290: bd80 pop {r7, pc} 8005292: bf00 nop 8005294: 40013800 .word 0x40013800 8005298: 51eb851f .word 0x51eb851f 0800529c <_write>: /* USER CODE END PFP */ /* Private user code ---------------------------------------------------------*/ /* USER CODE BEGIN 0 */ int _write (int file, uint8_t *ptr, uint16_t len) { 800529c: b580 push {r7, lr} 800529e: b084 sub sp, #16 80052a0: af00 add r7, sp, #0 80052a2: 60f8 str r0, [r7, #12] 80052a4: 60b9 str r1, [r7, #8] 80052a6: 4613 mov r3, r2 80052a8: 80fb strh r3, [r7, #6] #if 0 // PYJ.2020.06.03_BEGIN -- HAL_UART_Transmit(&hTest, ptr, len,10); #else HAL_UART_Transmit(&hTerminal, ptr, len,10); 80052aa: 88fa ldrh r2, [r7, #6] 80052ac: 230a movs r3, #10 80052ae: 68b9 ldr r1, [r7, #8] 80052b0: 4803 ldr r0, [pc, #12] ; (80052c0 <_write+0x24>) 80052b2: f7ff f930 bl 8004516 #endif // PYJ.2020.06.03_END -- return len; 80052b6: 88fb ldrh r3, [r7, #6] } 80052b8: 4618 mov r0, r3 80052ba: 3710 adds r7, #16 80052bc: 46bd mov sp, r7 80052be: bd80 pop {r7, pc} 80052c0: 20000954 .word 0x20000954 080052c4
: /** * @brief The application entry point. * @retval int */ int main(void) { 80052c4: b580 push {r7, lr} 80052c6: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 80052c8: f7fc fd60 bl 8001d8c /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 80052cc: f000 f84c bl 8005368 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 80052d0: f000 f9e6 bl 80056a0 MX_DMA_Init(); 80052d4: f000 f9ce bl 8005674 MX_ADC1_Init(); 80052d8: f000 f8e6 bl 80054a8 MX_TIM6_Init(); 80052dc: f000 f940 bl 8005560 MX_USART1_UART_Init(); 80052e0: f000 f974 bl 80055cc MX_USART3_UART_Init(); 80052e4: f000 f99c bl 8005620 /* Initialize interrupts */ MX_NVIC_Init(); 80052e8: f000 f892 bl 8005410 /* USER CODE BEGIN 2 */ HAL_TIM_Base_Start_IT(&htim6); 80052ec: 4815 ldr r0, [pc, #84] ; (8005344 ) 80052ee: f7fe fea0 bl 8004032 setbuf(stdout, NULL); 80052f2: 4b15 ldr r3, [pc, #84] ; (8005348 ) 80052f4: 681b ldr r3, [r3, #0] 80052f6: 689b ldr r3, [r3, #8] 80052f8: 2100 movs r1, #0 80052fa: 4618 mov r0, r3 80052fc: f001 fbac bl 8006a58 InitUartQueue(&MainQueue); 8005300: 4812 ldr r0, [pc, #72] ; (800534c ) 8005302: f7fc fbf1 bl 8001ae8 ADC_Initialize(); 8005306: f7fc f8b1 bl 800146c NessLab_Init(); 800530a: f7fb fc8d bl 8000c28 #if 1 // PYJ.2020.05.06_BEGIN -- printf("****************************************\r\n"); 800530e: 4810 ldr r0, [pc, #64] ; (8005350 ) 8005310: f001 fb9a bl 8006a48 printf("NESSLAB Project\r\n"); 8005314: 480f ldr r0, [pc, #60] ; (8005354 ) 8005316: f001 fb97 bl 8006a48 printf("Build at %s %s\r\n", __DATE__, __TIME__); 800531a: 4a0f ldr r2, [pc, #60] ; (8005358 ) 800531c: 490f ldr r1, [pc, #60] ; (800535c ) 800531e: 4810 ldr r0, [pc, #64] ; (8005360 ) 8005320: f001 fb1e bl 8006960 printf("Copyright (c) 2020. BLUECELL\r\n"); 8005324: 480f ldr r0, [pc, #60] ; (8005364 ) 8005326: f001 fb8f bl 8006a48 printf("****************************************\r\n"); 800532a: 4809 ldr r0, [pc, #36] ; (8005350 ) 800532c: f001 fb8c bl 8006a48 while (1) { #if 1 // PYJ.2020.08.31_BEGIN -- Boot_LED_Toggle(); /*LED Check*/ 8005330: f7fc fbc2 bl 8001ab8 Uart_Check(); /*Usart Rx*/ 8005334: f7fc fce4 bl 8001d00 NessLab_GPIO_Operate(); 8005338: f7fc f824 bl 8001384 ADC_TDD_Arrange(); 800533c: f7fc f990 bl 8001660 { 8005340: e7f6 b.n 8005330 8005342: bf00 nop 8005344: 20000b14 .word 0x20000b14 8005348: 2000000c .word 0x2000000c 800534c: 2000074c .word 0x2000074c 8005350: 08008c60 .word 0x08008c60 8005354: 08008c8c .word 0x08008c8c 8005358: 08008ca0 .word 0x08008ca0 800535c: 08008cac .word 0x08008cac 8005360: 08008cb8 .word 0x08008cb8 8005364: 08008ccc .word 0x08008ccc 08005368 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8005368: b580 push {r7, lr} 800536a: b092 sub sp, #72 ; 0x48 800536c: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 800536e: f107 0320 add.w r3, r7, #32 8005372: 2228 movs r2, #40 ; 0x28 8005374: 2100 movs r1, #0 8005376: 4618 mov r0, r3 8005378: f000 fe9a bl 80060b0 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 800537c: f107 030c add.w r3, r7, #12 8005380: 2200 movs r2, #0 8005382: 601a str r2, [r3, #0] 8005384: 605a str r2, [r3, #4] 8005386: 609a str r2, [r3, #8] 8005388: 60da str r2, [r3, #12] 800538a: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 800538c: 463b mov r3, r7 800538e: 2200 movs r2, #0 8005390: 601a str r2, [r3, #0] 8005392: 605a str r2, [r3, #4] 8005394: 609a str r2, [r3, #8] /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; 8005396: 2302 movs r3, #2 8005398: 623b str r3, [r7, #32] RCC_OscInitStruct.HSIState = RCC_HSI_ON; 800539a: 2301 movs r3, #1 800539c: 633b str r3, [r7, #48] ; 0x30 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 800539e: 2310 movs r3, #16 80053a0: 637b str r3, [r7, #52] ; 0x34 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 80053a2: 2302 movs r3, #2 80053a4: 63fb str r3, [r7, #60] ; 0x3c RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2; 80053a6: 2300 movs r3, #0 80053a8: 643b str r3, [r7, #64] ; 0x40 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6; 80053aa: f44f 1380 mov.w r3, #1048576 ; 0x100000 80053ae: 647b str r3, [r7, #68] ; 0x44 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 80053b0: f107 0320 add.w r3, r7, #32 80053b4: 4618 mov r0, r3 80053b6: f7fe f8fb bl 80035b0 80053ba: 4603 mov r3, r0 80053bc: 2b00 cmp r3, #0 80053be: d001 beq.n 80053c4 { Error_Handler(); 80053c0: f000 faa8 bl 8005914 } /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 80053c4: 230f movs r3, #15 80053c6: 60fb str r3, [r7, #12] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 80053c8: 2302 movs r3, #2 80053ca: 613b str r3, [r7, #16] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 80053cc: 2300 movs r3, #0 80053ce: 617b str r3, [r7, #20] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 80053d0: 2300 movs r3, #0 80053d2: 61bb str r3, [r7, #24] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 80053d4: 2300 movs r3, #0 80053d6: 61fb str r3, [r7, #28] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) 80053d8: f107 030c add.w r3, r7, #12 80053dc: 2100 movs r1, #0 80053de: 4618 mov r0, r3 80053e0: f7fe fb66 bl 8003ab0 80053e4: 4603 mov r3, r0 80053e6: 2b00 cmp r3, #0 80053e8: d001 beq.n 80053ee { Error_Handler(); 80053ea: f000 fa93 bl 8005914 } PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; 80053ee: 2302 movs r3, #2 80053f0: 603b str r3, [r7, #0] PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV2; 80053f2: 2300 movs r3, #0 80053f4: 60bb str r3, [r7, #8] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 80053f6: 463b mov r3, r7 80053f8: 4618 mov r0, r3 80053fa: f7fe fcf1 bl 8003de0 80053fe: 4603 mov r3, r0 8005400: 2b00 cmp r3, #0 8005402: d001 beq.n 8005408 { Error_Handler(); 8005404: f000 fa86 bl 8005914 } } 8005408: bf00 nop 800540a: 3748 adds r7, #72 ; 0x48 800540c: 46bd mov sp, r7 800540e: bd80 pop {r7, pc} 08005410 : /** * @brief NVIC Configuration. * @retval None */ static void MX_NVIC_Init(void) { 8005410: b580 push {r7, lr} 8005412: af00 add r7, sp, #0 /* ADC1_IRQn interrupt configuration */ HAL_NVIC_SetPriority(ADC1_IRQn, 0, 0); 8005414: 2200 movs r2, #0 8005416: 2100 movs r1, #0 8005418: 2012 movs r0, #18 800541a: f7fd fa98 bl 800294e HAL_NVIC_EnableIRQ(ADC1_IRQn); 800541e: 2012 movs r0, #18 8005420: f7fd fab1 bl 8002986 /* USART1_IRQn interrupt configuration */ HAL_NVIC_SetPriority(USART1_IRQn, 0, 0); 8005424: 2200 movs r2, #0 8005426: 2100 movs r1, #0 8005428: 2025 movs r0, #37 ; 0x25 800542a: f7fd fa90 bl 800294e HAL_NVIC_EnableIRQ(USART1_IRQn); 800542e: 2025 movs r0, #37 ; 0x25 8005430: f7fd faa9 bl 8002986 /* USART3_IRQn interrupt configuration */ HAL_NVIC_SetPriority(USART3_IRQn, 0, 0); 8005434: 2200 movs r2, #0 8005436: 2100 movs r1, #0 8005438: 2027 movs r0, #39 ; 0x27 800543a: f7fd fa88 bl 800294e HAL_NVIC_EnableIRQ(USART3_IRQn); 800543e: 2027 movs r0, #39 ; 0x27 8005440: f7fd faa1 bl 8002986 /* TIM6_DAC_IRQn interrupt configuration */ HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 0, 0); 8005444: 2200 movs r2, #0 8005446: 2100 movs r1, #0 8005448: 2036 movs r0, #54 ; 0x36 800544a: f7fd fa80 bl 800294e HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); 800544e: 2036 movs r0, #54 ; 0x36 8005450: f7fd fa99 bl 8002986 /* DMA1_Channel2_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel2_IRQn, 0, 0); 8005454: 2200 movs r2, #0 8005456: 2100 movs r1, #0 8005458: 200c movs r0, #12 800545a: f7fd fa78 bl 800294e HAL_NVIC_EnableIRQ(DMA1_Channel2_IRQn); 800545e: 200c movs r0, #12 8005460: f7fd fa91 bl 8002986 /* DMA1_Channel4_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel4_IRQn, 0, 0); 8005464: 2200 movs r2, #0 8005466: 2100 movs r1, #0 8005468: 200e movs r0, #14 800546a: f7fd fa70 bl 800294e HAL_NVIC_EnableIRQ(DMA1_Channel4_IRQn); 800546e: 200e movs r0, #14 8005470: f7fd fa89 bl 8002986 /* DMA1_Channel3_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel3_IRQn, 0, 0); 8005474: 2200 movs r2, #0 8005476: 2100 movs r1, #0 8005478: 200d movs r0, #13 800547a: f7fd fa68 bl 800294e HAL_NVIC_EnableIRQ(DMA1_Channel3_IRQn); 800547e: 200d movs r0, #13 8005480: f7fd fa81 bl 8002986 /* DMA1_Channel1_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0); 8005484: 2200 movs r2, #0 8005486: 2100 movs r1, #0 8005488: 200b movs r0, #11 800548a: f7fd fa60 bl 800294e HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn); 800548e: 200b movs r0, #11 8005490: f7fd fa79 bl 8002986 /* DMA1_Channel5_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel5_IRQn, 0, 0); 8005494: 2200 movs r2, #0 8005496: 2100 movs r1, #0 8005498: 200f movs r0, #15 800549a: f7fd fa58 bl 800294e HAL_NVIC_EnableIRQ(DMA1_Channel5_IRQn); 800549e: 200f movs r0, #15 80054a0: f7fd fa71 bl 8002986 } 80054a4: bf00 nop 80054a6: bd80 pop {r7, pc} 080054a8 : * @brief ADC1 Initialization Function * @param None * @retval None */ static void MX_ADC1_Init(void) { 80054a8: b580 push {r7, lr} 80054aa: b084 sub sp, #16 80054ac: af00 add r7, sp, #0 /* USER CODE BEGIN ADC1_Init 0 */ /* USER CODE END ADC1_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 80054ae: 1d3b adds r3, r7, #4 80054b0: 2200 movs r2, #0 80054b2: 601a str r2, [r3, #0] 80054b4: 605a str r2, [r3, #4] 80054b6: 609a str r2, [r3, #8] /* USER CODE BEGIN ADC1_Init 1 */ /* USER CODE END ADC1_Init 1 */ /** Common config */ hadc1.Instance = ADC1; 80054b8: 4b27 ldr r3, [pc, #156] ; (8005558 ) 80054ba: 4a28 ldr r2, [pc, #160] ; (800555c ) 80054bc: 601a str r2, [r3, #0] hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; 80054be: 4b26 ldr r3, [pc, #152] ; (8005558 ) 80054c0: f44f 7280 mov.w r2, #256 ; 0x100 80054c4: 609a str r2, [r3, #8] hadc1.Init.ContinuousConvMode = ENABLE; 80054c6: 4b24 ldr r3, [pc, #144] ; (8005558 ) 80054c8: 2201 movs r2, #1 80054ca: 731a strb r2, [r3, #12] hadc1.Init.DiscontinuousConvMode = DISABLE; 80054cc: 4b22 ldr r3, [pc, #136] ; (8005558 ) 80054ce: 2200 movs r2, #0 80054d0: 751a strb r2, [r3, #20] hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; 80054d2: 4b21 ldr r3, [pc, #132] ; (8005558 ) 80054d4: f44f 2260 mov.w r2, #917504 ; 0xe0000 80054d8: 61da str r2, [r3, #28] hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; 80054da: 4b1f ldr r3, [pc, #124] ; (8005558 ) 80054dc: 2200 movs r2, #0 80054de: 605a str r2, [r3, #4] hadc1.Init.NbrOfConversion = 3; 80054e0: 4b1d ldr r3, [pc, #116] ; (8005558 ) 80054e2: 2203 movs r2, #3 80054e4: 611a str r2, [r3, #16] if (HAL_ADC_Init(&hadc1) != HAL_OK) 80054e6: 481c ldr r0, [pc, #112] ; (8005558 ) 80054e8: f7fc fc9c bl 8001e24 80054ec: 4603 mov r3, r0 80054ee: 2b00 cmp r3, #0 80054f0: d001 beq.n 80054f6 { Error_Handler(); 80054f2: f000 fa0f bl 8005914 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_0; 80054f6: 2300 movs r3, #0 80054f8: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_1; 80054fa: 2301 movs r3, #1 80054fc: 60bb str r3, [r7, #8] sConfig.SamplingTime = ADC_SAMPLETIME_239CYCLES_5; 80054fe: 2307 movs r3, #7 8005500: 60fb str r3, [r7, #12] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8005502: 1d3b adds r3, r7, #4 8005504: 4619 mov r1, r3 8005506: 4814 ldr r0, [pc, #80] ; (8005558 ) 8005508: f7fc fedc bl 80022c4 800550c: 4603 mov r3, r0 800550e: 2b00 cmp r3, #0 8005510: d001 beq.n 8005516 { Error_Handler(); 8005512: f000 f9ff bl 8005914 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_1; 8005516: 2301 movs r3, #1 8005518: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_2; 800551a: 2302 movs r3, #2 800551c: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 800551e: 1d3b adds r3, r7, #4 8005520: 4619 mov r1, r3 8005522: 480d ldr r0, [pc, #52] ; (8005558 ) 8005524: f7fc fece bl 80022c4 8005528: 4603 mov r3, r0 800552a: 2b00 cmp r3, #0 800552c: d001 beq.n 8005532 { Error_Handler(); 800552e: f000 f9f1 bl 8005914 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_3; 8005532: 2303 movs r3, #3 8005534: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_3; 8005536: 2303 movs r3, #3 8005538: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 800553a: 1d3b adds r3, r7, #4 800553c: 4619 mov r1, r3 800553e: 4806 ldr r0, [pc, #24] ; (8005558 ) 8005540: f7fc fec0 bl 80022c4 8005544: 4603 mov r3, r0 8005546: 2b00 cmp r3, #0 8005548: d001 beq.n 800554e { Error_Handler(); 800554a: f000 f9e3 bl 8005914 } /* USER CODE BEGIN ADC1_Init 2 */ /* USER CODE END ADC1_Init 2 */ } 800554e: bf00 nop 8005550: 3710 adds r7, #16 8005552: 46bd mov sp, r7 8005554: bd80 pop {r7, pc} 8005556: bf00 nop 8005558: 20000a1c .word 0x20000a1c 800555c: 40012400 .word 0x40012400 08005560 : * @brief TIM6 Initialization Function * @param None * @retval None */ static void MX_TIM6_Init(void) { 8005560: b580 push {r7, lr} 8005562: b082 sub sp, #8 8005564: af00 add r7, sp, #0 /* USER CODE BEGIN TIM6_Init 0 */ /* USER CODE END TIM6_Init 0 */ TIM_MasterConfigTypeDef sMasterConfig = {0}; 8005566: 463b mov r3, r7 8005568: 2200 movs r2, #0 800556a: 601a str r2, [r3, #0] 800556c: 605a str r2, [r3, #4] /* USER CODE BEGIN TIM6_Init 1 */ /* USER CODE END TIM6_Init 1 */ htim6.Instance = TIM6; 800556e: 4b15 ldr r3, [pc, #84] ; (80055c4 ) 8005570: 4a15 ldr r2, [pc, #84] ; (80055c8 ) 8005572: 601a str r2, [r3, #0] htim6.Init.Prescaler = 2400-1; 8005574: 4b13 ldr r3, [pc, #76] ; (80055c4 ) 8005576: f640 125f movw r2, #2399 ; 0x95f 800557a: 605a str r2, [r3, #4] htim6.Init.CounterMode = TIM_COUNTERMODE_UP; 800557c: 4b11 ldr r3, [pc, #68] ; (80055c4 ) 800557e: 2200 movs r2, #0 8005580: 609a str r2, [r3, #8] htim6.Init.Period = 10; 8005582: 4b10 ldr r3, [pc, #64] ; (80055c4 ) 8005584: 220a movs r2, #10 8005586: 60da str r2, [r3, #12] htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8005588: 4b0e ldr r3, [pc, #56] ; (80055c4 ) 800558a: 2200 movs r2, #0 800558c: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim6) != HAL_OK) 800558e: 480d ldr r0, [pc, #52] ; (80055c4 ) 8005590: f7fe fd24 bl 8003fdc 8005594: 4603 mov r3, r0 8005596: 2b00 cmp r3, #0 8005598: d001 beq.n 800559e { Error_Handler(); 800559a: f000 f9bb bl 8005914 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 800559e: 2300 movs r3, #0 80055a0: 603b str r3, [r7, #0] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 80055a2: 2300 movs r3, #0 80055a4: 607b str r3, [r7, #4] if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK) 80055a6: 463b mov r3, r7 80055a8: 4619 mov r1, r3 80055aa: 4806 ldr r0, [pc, #24] ; (80055c4 ) 80055ac: f7fe ff10 bl 80043d0 80055b0: 4603 mov r3, r0 80055b2: 2b00 cmp r3, #0 80055b4: d001 beq.n 80055ba { Error_Handler(); 80055b6: f000 f9ad bl 8005914 } /* USER CODE BEGIN TIM6_Init 2 */ /* USER CODE END TIM6_Init 2 */ } 80055ba: bf00 nop 80055bc: 3708 adds r7, #8 80055be: 46bd mov sp, r7 80055c0: bd80 pop {r7, pc} 80055c2: bf00 nop 80055c4: 20000b14 .word 0x20000b14 80055c8: 40001000 .word 0x40001000 080055cc : * @brief USART1 Initialization Function * @param None * @retval None */ static void MX_USART1_UART_Init(void) { 80055cc: b580 push {r7, lr} 80055ce: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 80055d0: 4b11 ldr r3, [pc, #68] ; (8005618 ) 80055d2: 4a12 ldr r2, [pc, #72] ; (800561c ) 80055d4: 601a str r2, [r3, #0] huart1.Init.BaudRate = 115200; 80055d6: 4b10 ldr r3, [pc, #64] ; (8005618 ) 80055d8: f44f 32e1 mov.w r2, #115200 ; 0x1c200 80055dc: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 80055de: 4b0e ldr r3, [pc, #56] ; (8005618 ) 80055e0: 2200 movs r2, #0 80055e2: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 80055e4: 4b0c ldr r3, [pc, #48] ; (8005618 ) 80055e6: 2200 movs r2, #0 80055e8: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 80055ea: 4b0b ldr r3, [pc, #44] ; (8005618 ) 80055ec: 2200 movs r2, #0 80055ee: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 80055f0: 4b09 ldr r3, [pc, #36] ; (8005618 ) 80055f2: 220c movs r2, #12 80055f4: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 80055f6: 4b08 ldr r3, [pc, #32] ; (8005618 ) 80055f8: 2200 movs r2, #0 80055fa: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 80055fc: 4b06 ldr r3, [pc, #24] ; (8005618 ) 80055fe: 2200 movs r2, #0 8005600: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart1) != HAL_OK) 8005602: 4805 ldr r0, [pc, #20] ; (8005618 ) 8005604: f7fe ff3a bl 800447c 8005608: 4603 mov r3, r0 800560a: 2b00 cmp r3, #0 800560c: d001 beq.n 8005612 { Error_Handler(); 800560e: f000 f981 bl 8005914 } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 8005612: bf00 nop 8005614: bd80 pop {r7, pc} 8005616: bf00 nop 8005618: 20000a90 .word 0x20000a90 800561c: 40013800 .word 0x40013800 08005620 : * @brief USART3 Initialization Function * @param None * @retval None */ static void MX_USART3_UART_Init(void) { 8005620: b580 push {r7, lr} 8005622: af00 add r7, sp, #0 /* USER CODE END USART3_Init 0 */ /* USER CODE BEGIN USART3_Init 1 */ /* USER CODE END USART3_Init 1 */ huart3.Instance = USART3; 8005624: 4b11 ldr r3, [pc, #68] ; (800566c ) 8005626: 4a12 ldr r2, [pc, #72] ; (8005670 ) 8005628: 601a str r2, [r3, #0] huart3.Init.BaudRate = 115200; 800562a: 4b10 ldr r3, [pc, #64] ; (800566c ) 800562c: f44f 32e1 mov.w r2, #115200 ; 0x1c200 8005630: 605a str r2, [r3, #4] huart3.Init.WordLength = UART_WORDLENGTH_8B; 8005632: 4b0e ldr r3, [pc, #56] ; (800566c ) 8005634: 2200 movs r2, #0 8005636: 609a str r2, [r3, #8] huart3.Init.StopBits = UART_STOPBITS_1; 8005638: 4b0c ldr r3, [pc, #48] ; (800566c ) 800563a: 2200 movs r2, #0 800563c: 60da str r2, [r3, #12] huart3.Init.Parity = UART_PARITY_NONE; 800563e: 4b0b ldr r3, [pc, #44] ; (800566c ) 8005640: 2200 movs r2, #0 8005642: 611a str r2, [r3, #16] huart3.Init.Mode = UART_MODE_TX_RX; 8005644: 4b09 ldr r3, [pc, #36] ; (800566c ) 8005646: 220c movs r2, #12 8005648: 615a str r2, [r3, #20] huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800564a: 4b08 ldr r3, [pc, #32] ; (800566c ) 800564c: 2200 movs r2, #0 800564e: 619a str r2, [r3, #24] huart3.Init.OverSampling = UART_OVERSAMPLING_16; 8005650: 4b06 ldr r3, [pc, #24] ; (800566c ) 8005652: 2200 movs r2, #0 8005654: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart3) != HAL_OK) 8005656: 4805 ldr r0, [pc, #20] ; (800566c ) 8005658: f7fe ff10 bl 800447c 800565c: 4603 mov r3, r0 800565e: 2b00 cmp r3, #0 8005660: d001 beq.n 8005666 { Error_Handler(); 8005662: f000 f957 bl 8005914 } /* USER CODE BEGIN USART3_Init 2 */ /* USER CODE END USART3_Init 2 */ } 8005666: bf00 nop 8005668: bd80 pop {r7, pc} 800566a: bf00 nop 800566c: 20000954 .word 0x20000954 8005670: 40004800 .word 0x40004800 08005674 : /** * Enable DMA controller clock */ static void MX_DMA_Init(void) { 8005674: b480 push {r7} 8005676: b083 sub sp, #12 8005678: af00 add r7, sp, #0 /* DMA controller clock enable */ __HAL_RCC_DMA1_CLK_ENABLE(); 800567a: 4b08 ldr r3, [pc, #32] ; (800569c ) 800567c: 695b ldr r3, [r3, #20] 800567e: 4a07 ldr r2, [pc, #28] ; (800569c ) 8005680: f043 0301 orr.w r3, r3, #1 8005684: 6153 str r3, [r2, #20] 8005686: 4b05 ldr r3, [pc, #20] ; (800569c ) 8005688: 695b ldr r3, [r3, #20] 800568a: f003 0301 and.w r3, r3, #1 800568e: 607b str r3, [r7, #4] 8005690: 687b ldr r3, [r7, #4] } 8005692: bf00 nop 8005694: 370c adds r7, #12 8005696: 46bd mov sp, r7 8005698: bc80 pop {r7} 800569a: 4770 bx lr 800569c: 40021000 .word 0x40021000 080056a0 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 80056a0: b580 push {r7, lr} 80056a2: b088 sub sp, #32 80056a4: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 80056a6: f107 0310 add.w r3, r7, #16 80056aa: 2200 movs r2, #0 80056ac: 601a str r2, [r3, #0] 80056ae: 605a str r2, [r3, #4] 80056b0: 609a str r2, [r3, #8] 80056b2: 60da str r2, [r3, #12] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); 80056b4: 4b40 ldr r3, [pc, #256] ; (80057b8 ) 80056b6: 699b ldr r3, [r3, #24] 80056b8: 4a3f ldr r2, [pc, #252] ; (80057b8 ) 80056ba: f043 0310 orr.w r3, r3, #16 80056be: 6193 str r3, [r2, #24] 80056c0: 4b3d ldr r3, [pc, #244] ; (80057b8 ) 80056c2: 699b ldr r3, [r3, #24] 80056c4: f003 0310 and.w r3, r3, #16 80056c8: 60fb str r3, [r7, #12] 80056ca: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 80056cc: 4b3a ldr r3, [pc, #232] ; (80057b8 ) 80056ce: 699b ldr r3, [r3, #24] 80056d0: 4a39 ldr r2, [pc, #228] ; (80057b8 ) 80056d2: f043 0304 orr.w r3, r3, #4 80056d6: 6193 str r3, [r2, #24] 80056d8: 4b37 ldr r3, [pc, #220] ; (80057b8 ) 80056da: 699b ldr r3, [r3, #24] 80056dc: f003 0304 and.w r3, r3, #4 80056e0: 60bb str r3, [r7, #8] 80056e2: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOB_CLK_ENABLE(); 80056e4: 4b34 ldr r3, [pc, #208] ; (80057b8 ) 80056e6: 699b ldr r3, [r3, #24] 80056e8: 4a33 ldr r2, [pc, #204] ; (80057b8 ) 80056ea: f043 0308 orr.w r3, r3, #8 80056ee: 6193 str r3, [r2, #24] 80056f0: 4b31 ldr r3, [pc, #196] ; (80057b8 ) 80056f2: 699b ldr r3, [r3, #24] 80056f4: f003 0308 and.w r3, r3, #8 80056f8: 607b str r3, [r7, #4] 80056fa: 687b ldr r3, [r7, #4] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(BOOT_LED_GPIO_Port, BOOT_LED_Pin, GPIO_PIN_RESET); 80056fc: 2200 movs r2, #0 80056fe: f44f 4100 mov.w r1, #32768 ; 0x8000 8005702: 482e ldr r0, [pc, #184] ; (80057bc ) 8005704: f7fd ff23 bl 800354e /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOA, PAU_RESERVED0_Pin|PAU_RESERVED1_Pin|AMP_EN_Pin, GPIO_PIN_RESET); 8005708: 2200 movs r2, #0 800570a: f44f 71e0 mov.w r1, #448 ; 0x1c0 800570e: 482c ldr r0, [pc, #176] ; (80057c0 ) 8005710: f7fd ff1d bl 800354e /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOB, PAU_RESERVED3_Pin|PAU_RESERVED2_Pin|PAU_RESET_Pin, GPIO_PIN_RESET); 8005714: 2200 movs r2, #0 8005716: f244 0103 movw r1, #16387 ; 0x4003 800571a: 482a ldr r0, [pc, #168] ; (80057c4 ) 800571c: f7fd ff17 bl 800354e /*Configure GPIO pin : BOOT_LED_Pin */ GPIO_InitStruct.Pin = BOOT_LED_Pin; 8005720: f44f 4300 mov.w r3, #32768 ; 0x8000 8005724: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8005726: 2301 movs r3, #1 8005728: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 800572a: 2300 movs r3, #0 800572c: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800572e: 2302 movs r3, #2 8005730: 61fb str r3, [r7, #28] HAL_GPIO_Init(BOOT_LED_GPIO_Port, &GPIO_InitStruct); 8005732: f107 0310 add.w r3, r7, #16 8005736: 4619 mov r1, r3 8005738: 4820 ldr r0, [pc, #128] ; (80057bc ) 800573a: f7fd fd97 bl 800326c /*Configure GPIO pins : DC_FAIL_ALARM_Pin OVER_INPUT_ALARM_Pin OVER_TEMP_ALARM_Pin */ GPIO_InitStruct.Pin = DC_FAIL_ALARM_Pin|OVER_INPUT_ALARM_Pin|OVER_TEMP_ALARM_Pin; 800573e: f641 0304 movw r3, #6148 ; 0x1804 8005742: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8005744: 2300 movs r3, #0 8005746: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 8005748: 2300 movs r3, #0 800574a: 61bb str r3, [r7, #24] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800574c: f107 0310 add.w r3, r7, #16 8005750: 4619 mov r1, r3 8005752: 481b ldr r0, [pc, #108] ; (80057c0 ) 8005754: f7fd fd8a bl 800326c /*Configure GPIO pins : PAU_RESERVED0_Pin PAU_RESERVED1_Pin AMP_EN_Pin */ GPIO_InitStruct.Pin = PAU_RESERVED0_Pin|PAU_RESERVED1_Pin|AMP_EN_Pin; 8005758: f44f 73e0 mov.w r3, #448 ; 0x1c0 800575c: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800575e: 2301 movs r3, #1 8005760: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 8005762: 2300 movs r3, #0 8005764: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8005766: 2302 movs r3, #2 8005768: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800576a: f107 0310 add.w r3, r7, #16 800576e: 4619 mov r1, r3 8005770: 4813 ldr r0, [pc, #76] ; (80057c0 ) 8005772: f7fd fd7b bl 800326c /*Configure GPIO pins : PAU_RESERVED3_Pin PAU_RESERVED2_Pin PAU_RESET_Pin */ GPIO_InitStruct.Pin = PAU_RESERVED3_Pin|PAU_RESERVED2_Pin|PAU_RESET_Pin; 8005776: f244 0303 movw r3, #16387 ; 0x4003 800577a: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800577c: 2301 movs r3, #1 800577e: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 8005780: 2300 movs r3, #0 8005782: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8005784: 2302 movs r3, #2 8005786: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8005788: f107 0310 add.w r3, r7, #16 800578c: 4619 mov r1, r3 800578e: 480d ldr r0, [pc, #52] ; (80057c4 ) 8005790: f7fd fd6c bl 800326c /*Configure GPIO pins : OVER_POWER_ALARM_Pin VSWR_ALARM_Pin PAU_EN_Pin ALC_ALARM_Pin */ GPIO_InitStruct.Pin = OVER_POWER_ALARM_Pin|VSWR_ALARM_Pin|PAU_EN_Pin|ALC_ALARM_Pin; 8005794: f24b 0308 movw r3, #45064 ; 0xb008 8005798: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800579a: 2300 movs r3, #0 800579c: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 800579e: 2300 movs r3, #0 80057a0: 61bb str r3, [r7, #24] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80057a2: f107 0310 add.w r3, r7, #16 80057a6: 4619 mov r1, r3 80057a8: 4806 ldr r0, [pc, #24] ; (80057c4 ) 80057aa: f7fd fd5f bl 800326c } 80057ae: bf00 nop 80057b0: 3720 adds r7, #32 80057b2: 46bd mov sp, r7 80057b4: bd80 pop {r7, pc} 80057b6: bf00 nop 80057b8: 40021000 .word 0x40021000 80057bc: 40011000 .word 0x40011000 80057c0: 40010800 .word 0x40010800 80057c4: 40010c00 .word 0x40010c00 080057c8 : * a global variable "uwTick" used as application time base. * @param htim : TIM handle * @retval None */ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { 80057c8: b580 push {r7, lr} 80057ca: b082 sub sp, #8 80057cc: af00 add r7, sp, #0 80057ce: 6078 str r0, [r7, #4] /* USER CODE BEGIN Callback 0 */ /* USER CODE END Callback 0 */ if (htim->Instance == TIM2) { 80057d0: 687b ldr r3, [r7, #4] 80057d2: 681b ldr r3, [r3, #0] 80057d4: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 80057d8: d101 bne.n 80057de HAL_IncTick(); 80057da: f7fc fae5 bl 8001da8 } /* USER CODE BEGIN Callback 1 */ if(htim->Instance == TIM6){ 80057de: 687b ldr r3, [r7, #4] 80057e0: 681b ldr r3, [r3, #0] 80057e2: 4a3f ldr r2, [pc, #252] ; (80058e0 ) 80057e4: 4293 cmp r3, r2 80057e6: d177 bne.n 80058d8 UartRxTimerCnt++; 80057e8: 4b3e ldr r3, [pc, #248] ; (80058e4 ) 80057ea: 681b ldr r3, [r3, #0] 80057ec: 3301 adds r3, #1 80057ee: 4a3d ldr r2, [pc, #244] ; (80058e4 ) 80057f0: 6013 str r3, [r2, #0] LED_TimerCnt++; 80057f2: 4b3d ldr r3, [pc, #244] ; (80058e8 ) 80057f4: 681b ldr r3, [r3, #0] 80057f6: 3301 adds r3, #1 80057f8: 4a3b ldr r2, [pc, #236] ; (80058e8 ) 80057fa: 6013 str r3, [r2, #0] TDD_125ms_Cnt++; 80057fc: 4b3b ldr r3, [pc, #236] ; (80058ec ) 80057fe: 681b ldr r3, [r3, #0] 8005800: 3301 adds r3, #1 8005802: 4a3a ldr r2, [pc, #232] ; (80058ec ) 8005804: 6013 str r3, [r2, #0] TestTimer++; 8005806: 4b3a ldr r3, [pc, #232] ; (80058f0 ) 8005808: 681b ldr r3, [r3, #0] 800580a: 3301 adds r3, #1 800580c: 4a38 ldr r2, [pc, #224] ; (80058f0 ) 800580e: 6013 str r3, [r2, #0] if(HAL_GPIO_ReadPin(DC_FAIL_ALARM_GPIO_Port, DC_FAIL_ALARM_Pin) == GPIO_PIN_SET) 8005810: 2104 movs r1, #4 8005812: 4838 ldr r0, [pc, #224] ; (80058f4 ) 8005814: f7fd fe84 bl 8003520 8005818: 4603 mov r3, r0 800581a: 2b01 cmp r3, #1 800581c: d105 bne.n 800582a DC_FAIL_ALARM_CNT++; 800581e: 4b36 ldr r3, [pc, #216] ; (80058f8 ) 8005820: 681b ldr r3, [r3, #0] 8005822: 3301 adds r3, #1 8005824: 4a34 ldr r2, [pc, #208] ; (80058f8 ) 8005826: 6013 str r3, [r2, #0] 8005828: e002 b.n 8005830 else DC_FAIL_ALARM_CNT = 0; 800582a: 4b33 ldr r3, [pc, #204] ; (80058f8 ) 800582c: 2200 movs r2, #0 800582e: 601a str r2, [r3, #0] if(HAL_GPIO_ReadPin(OVER_INPUT_ALARM_GPIO_Port, OVER_INPUT_ALARM_Pin)== GPIO_PIN_SET) 8005830: f44f 6100 mov.w r1, #2048 ; 0x800 8005834: 482f ldr r0, [pc, #188] ; (80058f4 ) 8005836: f7fd fe73 bl 8003520 800583a: 4603 mov r3, r0 800583c: 2b01 cmp r3, #1 800583e: d105 bne.n 800584c OVER_INPUT_ALARM_CNT++; 8005840: 4b2e ldr r3, [pc, #184] ; (80058fc ) 8005842: 681b ldr r3, [r3, #0] 8005844: 3301 adds r3, #1 8005846: 4a2d ldr r2, [pc, #180] ; (80058fc ) 8005848: 6013 str r3, [r2, #0] 800584a: e002 b.n 8005852 else OVER_INPUT_ALARM_CNT = 0; 800584c: 4b2b ldr r3, [pc, #172] ; (80058fc ) 800584e: 2200 movs r2, #0 8005850: 601a str r2, [r3, #0] if(HAL_GPIO_ReadPin(OVER_TEMP_ALARM_GPIO_Port, OVER_TEMP_ALARM_Pin)== GPIO_PIN_SET) 8005852: f44f 5180 mov.w r1, #4096 ; 0x1000 8005856: 4827 ldr r0, [pc, #156] ; (80058f4 ) 8005858: f7fd fe62 bl 8003520 800585c: 4603 mov r3, r0 800585e: 2b01 cmp r3, #1 8005860: d105 bne.n 800586e OVER_TEMP_ALARM_CNT++; 8005862: 4b27 ldr r3, [pc, #156] ; (8005900 ) 8005864: 681b ldr r3, [r3, #0] 8005866: 3301 adds r3, #1 8005868: 4a25 ldr r2, [pc, #148] ; (8005900 ) 800586a: 6013 str r3, [r2, #0] 800586c: e002 b.n 8005874 else OVER_TEMP_ALARM_CNT = 0; 800586e: 4b24 ldr r3, [pc, #144] ; (8005900 ) 8005870: 2200 movs r2, #0 8005872: 601a str r2, [r3, #0] if(HAL_GPIO_ReadPin(ALC_ALARM_GPIO_Port, ALC_ALARM_Pin)== GPIO_PIN_SET) 8005874: 2108 movs r1, #8 8005876: 4823 ldr r0, [pc, #140] ; (8005904 ) 8005878: f7fd fe52 bl 8003520 800587c: 4603 mov r3, r0 800587e: 2b01 cmp r3, #1 8005880: d105 bne.n 800588e ALC_ALARM_CNT++; 8005882: 4b21 ldr r3, [pc, #132] ; (8005908 ) 8005884: 681b ldr r3, [r3, #0] 8005886: 3301 adds r3, #1 8005888: 4a1f ldr r2, [pc, #124] ; (8005908 ) 800588a: 6013 str r3, [r2, #0] 800588c: e002 b.n 8005894 else ALC_ALARM_CNT = 0; 800588e: 4b1e ldr r3, [pc, #120] ; (8005908 ) 8005890: 2200 movs r2, #0 8005892: 601a str r2, [r3, #0] if(HAL_GPIO_ReadPin(OVER_POWER_ALARM_GPIO_Port, OVER_POWER_ALARM_Pin)== GPIO_PIN_SET) 8005894: f44f 5180 mov.w r1, #4096 ; 0x1000 8005898: 481a ldr r0, [pc, #104] ; (8005904 ) 800589a: f7fd fe41 bl 8003520 800589e: 4603 mov r3, r0 80058a0: 2b01 cmp r3, #1 80058a2: d105 bne.n 80058b0 OVER_POWER_ALARM_CNT++; 80058a4: 4b19 ldr r3, [pc, #100] ; (800590c ) 80058a6: 681b ldr r3, [r3, #0] 80058a8: 3301 adds r3, #1 80058aa: 4a18 ldr r2, [pc, #96] ; (800590c ) 80058ac: 6013 str r3, [r2, #0] 80058ae: e002 b.n 80058b6 else OVER_POWER_ALARM_CNT = 0; 80058b0: 4b16 ldr r3, [pc, #88] ; (800590c ) 80058b2: 2200 movs r2, #0 80058b4: 601a str r2, [r3, #0] if(HAL_GPIO_ReadPin(VSWR_ALARM_GPIO_Port, VSWR_ALARM_Pin)== GPIO_PIN_SET) 80058b6: f44f 5100 mov.w r1, #8192 ; 0x2000 80058ba: 4812 ldr r0, [pc, #72] ; (8005904 ) 80058bc: f7fd fe30 bl 8003520 80058c0: 4603 mov r3, r0 80058c2: 2b01 cmp r3, #1 80058c4: d105 bne.n 80058d2 VSWR_ALARM_CNT++; 80058c6: 4b12 ldr r3, [pc, #72] ; (8005910 ) 80058c8: 681b ldr r3, [r3, #0] 80058ca: 3301 adds r3, #1 80058cc: 4a10 ldr r2, [pc, #64] ; (8005910 ) 80058ce: 6013 str r3, [r2, #0] else VSWR_ALARM_CNT = 0; } /* USER CODE END Callback 1 */ } 80058d0: e002 b.n 80058d8 VSWR_ALARM_CNT = 0; 80058d2: 4b0f ldr r3, [pc, #60] ; (8005910 ) 80058d4: 2200 movs r2, #0 80058d6: 601a str r2, [r3, #0] } 80058d8: bf00 nop 80058da: 3708 adds r7, #8 80058dc: 46bd mov sp, r7 80058de: bd80 pop {r7, pc} 80058e0: 40001000 .word 0x40001000 80058e4: 20000618 .word 0x20000618 80058e8: 20000610 .word 0x20000610 80058ec: 20000634 .word 0x20000634 80058f0: 20000638 .word 0x20000638 80058f4: 40010800 .word 0x40010800 80058f8: 2000061c .word 0x2000061c 80058fc: 20000620 .word 0x20000620 8005900: 20000624 .word 0x20000624 8005904: 40010c00 .word 0x40010c00 8005908: 20000628 .word 0x20000628 800590c: 2000062c .word 0x2000062c 8005910: 20000630 .word 0x20000630 08005914 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8005914: b480 push {r7} 8005916: af00 add r7, sp, #0 /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ /* USER CODE END Error_Handler_Debug */ } 8005918: bf00 nop 800591a: 46bd mov sp, r7 800591c: bc80 pop {r7} 800591e: 4770 bx lr 08005920 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8005920: b480 push {r7} 8005922: b085 sub sp, #20 8005924: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_AFIO_CLK_ENABLE(); 8005926: 4b15 ldr r3, [pc, #84] ; (800597c ) 8005928: 699b ldr r3, [r3, #24] 800592a: 4a14 ldr r2, [pc, #80] ; (800597c ) 800592c: f043 0301 orr.w r3, r3, #1 8005930: 6193 str r3, [r2, #24] 8005932: 4b12 ldr r3, [pc, #72] ; (800597c ) 8005934: 699b ldr r3, [r3, #24] 8005936: f003 0301 and.w r3, r3, #1 800593a: 60bb str r3, [r7, #8] 800593c: 68bb ldr r3, [r7, #8] __HAL_RCC_PWR_CLK_ENABLE(); 800593e: 4b0f ldr r3, [pc, #60] ; (800597c ) 8005940: 69db ldr r3, [r3, #28] 8005942: 4a0e ldr r2, [pc, #56] ; (800597c ) 8005944: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8005948: 61d3 str r3, [r2, #28] 800594a: 4b0c ldr r3, [pc, #48] ; (800597c ) 800594c: 69db ldr r3, [r3, #28] 800594e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8005952: 607b str r3, [r7, #4] 8005954: 687b ldr r3, [r7, #4] /* System interrupt init*/ /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled */ __HAL_AFIO_REMAP_SWJ_NOJTAG(); 8005956: 4b0a ldr r3, [pc, #40] ; (8005980 ) 8005958: 685b ldr r3, [r3, #4] 800595a: 60fb str r3, [r7, #12] 800595c: 68fb ldr r3, [r7, #12] 800595e: f023 63e0 bic.w r3, r3, #117440512 ; 0x7000000 8005962: 60fb str r3, [r7, #12] 8005964: 68fb ldr r3, [r7, #12] 8005966: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000 800596a: 60fb str r3, [r7, #12] 800596c: 4a04 ldr r2, [pc, #16] ; (8005980 ) 800596e: 68fb ldr r3, [r7, #12] 8005970: 6053 str r3, [r2, #4] /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8005972: bf00 nop 8005974: 3714 adds r7, #20 8005976: 46bd mov sp, r7 8005978: bc80 pop {r7} 800597a: 4770 bx lr 800597c: 40021000 .word 0x40021000 8005980: 40010000 .word 0x40010000 08005984 : * This function configures the hardware resources used in this example * @param hadc: ADC handle pointer * @retval None */ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) { 8005984: b580 push {r7, lr} 8005986: b088 sub sp, #32 8005988: af00 add r7, sp, #0 800598a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800598c: f107 0310 add.w r3, r7, #16 8005990: 2200 movs r2, #0 8005992: 601a str r2, [r3, #0] 8005994: 605a str r2, [r3, #4] 8005996: 609a str r2, [r3, #8] 8005998: 60da str r2, [r3, #12] if(hadc->Instance==ADC1) 800599a: 687b ldr r3, [r7, #4] 800599c: 681b ldr r3, [r3, #0] 800599e: 4a28 ldr r2, [pc, #160] ; (8005a40 ) 80059a0: 4293 cmp r3, r2 80059a2: d149 bne.n 8005a38 { /* USER CODE BEGIN ADC1_MspInit 0 */ /* USER CODE END ADC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_ADC1_CLK_ENABLE(); 80059a4: 4b27 ldr r3, [pc, #156] ; (8005a44 ) 80059a6: 699b ldr r3, [r3, #24] 80059a8: 4a26 ldr r2, [pc, #152] ; (8005a44 ) 80059aa: f443 7300 orr.w r3, r3, #512 ; 0x200 80059ae: 6193 str r3, [r2, #24] 80059b0: 4b24 ldr r3, [pc, #144] ; (8005a44 ) 80059b2: 699b ldr r3, [r3, #24] 80059b4: f403 7300 and.w r3, r3, #512 ; 0x200 80059b8: 60fb str r3, [r7, #12] 80059ba: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 80059bc: 4b21 ldr r3, [pc, #132] ; (8005a44 ) 80059be: 699b ldr r3, [r3, #24] 80059c0: 4a20 ldr r2, [pc, #128] ; (8005a44 ) 80059c2: f043 0304 orr.w r3, r3, #4 80059c6: 6193 str r3, [r2, #24] 80059c8: 4b1e ldr r3, [pc, #120] ; (8005a44 ) 80059ca: 699b ldr r3, [r3, #24] 80059cc: f003 0304 and.w r3, r3, #4 80059d0: 60bb str r3, [r7, #8] 80059d2: 68bb ldr r3, [r7, #8] /**ADC1 GPIO Configuration PA0-WKUP ------> ADC1_IN0 PA1 ------> ADC1_IN1 PA3 ------> ADC1_IN3 */ GPIO_InitStruct.Pin = DL_TX_DET_Pin|DL_RX_DET_Pin|PAU_TEMP_Pin; 80059d4: 230b movs r3, #11 80059d6: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 80059d8: 2303 movs r3, #3 80059da: 617b str r3, [r7, #20] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80059dc: f107 0310 add.w r3, r7, #16 80059e0: 4619 mov r1, r3 80059e2: 4819 ldr r0, [pc, #100] ; (8005a48 ) 80059e4: f7fd fc42 bl 800326c /* ADC1 DMA Init */ /* ADC1 Init */ hdma_adc1.Instance = DMA1_Channel1; 80059e8: 4b18 ldr r3, [pc, #96] ; (8005a4c ) 80059ea: 4a19 ldr r2, [pc, #100] ; (8005a50 ) 80059ec: 601a str r2, [r3, #0] hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY; 80059ee: 4b17 ldr r3, [pc, #92] ; (8005a4c ) 80059f0: 2200 movs r2, #0 80059f2: 605a str r2, [r3, #4] hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE; 80059f4: 4b15 ldr r3, [pc, #84] ; (8005a4c ) 80059f6: 2200 movs r2, #0 80059f8: 609a str r2, [r3, #8] hdma_adc1.Init.MemInc = DMA_MINC_ENABLE; 80059fa: 4b14 ldr r3, [pc, #80] ; (8005a4c ) 80059fc: 2280 movs r2, #128 ; 0x80 80059fe: 60da str r2, [r3, #12] hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 8005a00: 4b12 ldr r3, [pc, #72] ; (8005a4c ) 8005a02: f44f 7280 mov.w r2, #256 ; 0x100 8005a06: 611a str r2, [r3, #16] hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 8005a08: 4b10 ldr r3, [pc, #64] ; (8005a4c ) 8005a0a: f44f 6280 mov.w r2, #1024 ; 0x400 8005a0e: 615a str r2, [r3, #20] hdma_adc1.Init.Mode = DMA_CIRCULAR; 8005a10: 4b0e ldr r3, [pc, #56] ; (8005a4c ) 8005a12: 2220 movs r2, #32 8005a14: 619a str r2, [r3, #24] hdma_adc1.Init.Priority = DMA_PRIORITY_LOW; 8005a16: 4b0d ldr r3, [pc, #52] ; (8005a4c ) 8005a18: 2200 movs r2, #0 8005a1a: 61da str r2, [r3, #28] if (HAL_DMA_Init(&hdma_adc1) != HAL_OK) 8005a1c: 480b ldr r0, [pc, #44] ; (8005a4c ) 8005a1e: f7fc ffc1 bl 80029a4 8005a22: 4603 mov r3, r0 8005a24: 2b00 cmp r3, #0 8005a26: d001 beq.n 8005a2c { Error_Handler(); 8005a28: f7ff ff74 bl 8005914 } __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc1); 8005a2c: 687b ldr r3, [r7, #4] 8005a2e: 4a07 ldr r2, [pc, #28] ; (8005a4c ) 8005a30: 621a str r2, [r3, #32] 8005a32: 4a06 ldr r2, [pc, #24] ; (8005a4c ) 8005a34: 687b ldr r3, [r7, #4] 8005a36: 6253 str r3, [r2, #36] ; 0x24 /* USER CODE BEGIN ADC1_MspInit 1 */ /* USER CODE END ADC1_MspInit 1 */ } } 8005a38: bf00 nop 8005a3a: 3720 adds r7, #32 8005a3c: 46bd mov sp, r7 8005a3e: bd80 pop {r7, pc} 8005a40: 40012400 .word 0x40012400 8005a44: 40021000 .word 0x40021000 8005a48: 40010800 .word 0x40010800 8005a4c: 20000ad0 .word 0x20000ad0 8005a50: 40020008 .word 0x40020008 08005a54 : * This function configures the hardware resources used in this example * @param htim_base: TIM_Base handle pointer * @retval None */ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) { 8005a54: b480 push {r7} 8005a56: b085 sub sp, #20 8005a58: af00 add r7, sp, #0 8005a5a: 6078 str r0, [r7, #4] if(htim_base->Instance==TIM6) 8005a5c: 687b ldr r3, [r7, #4] 8005a5e: 681b ldr r3, [r3, #0] 8005a60: 4a09 ldr r2, [pc, #36] ; (8005a88 ) 8005a62: 4293 cmp r3, r2 8005a64: d10b bne.n 8005a7e { /* USER CODE BEGIN TIM6_MspInit 0 */ /* USER CODE END TIM6_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM6_CLK_ENABLE(); 8005a66: 4b09 ldr r3, [pc, #36] ; (8005a8c ) 8005a68: 69db ldr r3, [r3, #28] 8005a6a: 4a08 ldr r2, [pc, #32] ; (8005a8c ) 8005a6c: f043 0310 orr.w r3, r3, #16 8005a70: 61d3 str r3, [r2, #28] 8005a72: 4b06 ldr r3, [pc, #24] ; (8005a8c ) 8005a74: 69db ldr r3, [r3, #28] 8005a76: f003 0310 and.w r3, r3, #16 8005a7a: 60fb str r3, [r7, #12] 8005a7c: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN TIM6_MspInit 1 */ /* USER CODE END TIM6_MspInit 1 */ } } 8005a7e: bf00 nop 8005a80: 3714 adds r7, #20 8005a82: 46bd mov sp, r7 8005a84: bc80 pop {r7} 8005a86: 4770 bx lr 8005a88: 40001000 .word 0x40001000 8005a8c: 40021000 .word 0x40021000 08005a90 : * This function configures the hardware resources used in this example * @param huart: UART handle pointer * @retval None */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { 8005a90: b580 push {r7, lr} 8005a92: b08a sub sp, #40 ; 0x28 8005a94: af00 add r7, sp, #0 8005a96: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8005a98: f107 0318 add.w r3, r7, #24 8005a9c: 2200 movs r2, #0 8005a9e: 601a str r2, [r3, #0] 8005aa0: 605a str r2, [r3, #4] 8005aa2: 609a str r2, [r3, #8] 8005aa4: 60da str r2, [r3, #12] if(huart->Instance==USART1) 8005aa6: 687b ldr r3, [r7, #4] 8005aa8: 681b ldr r3, [r3, #0] 8005aaa: 4a84 ldr r2, [pc, #528] ; (8005cbc ) 8005aac: 4293 cmp r3, r2 8005aae: d17e bne.n 8005bae { /* USER CODE BEGIN USART1_MspInit 0 */ /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); 8005ab0: 4b83 ldr r3, [pc, #524] ; (8005cc0 ) 8005ab2: 699b ldr r3, [r3, #24] 8005ab4: 4a82 ldr r2, [pc, #520] ; (8005cc0 ) 8005ab6: f443 4380 orr.w r3, r3, #16384 ; 0x4000 8005aba: 6193 str r3, [r2, #24] 8005abc: 4b80 ldr r3, [pc, #512] ; (8005cc0 ) 8005abe: 699b ldr r3, [r3, #24] 8005ac0: f403 4380 and.w r3, r3, #16384 ; 0x4000 8005ac4: 617b str r3, [r7, #20] 8005ac6: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 8005ac8: 4b7d ldr r3, [pc, #500] ; (8005cc0 ) 8005aca: 699b ldr r3, [r3, #24] 8005acc: 4a7c ldr r2, [pc, #496] ; (8005cc0 ) 8005ace: f043 0304 orr.w r3, r3, #4 8005ad2: 6193 str r3, [r2, #24] 8005ad4: 4b7a ldr r3, [pc, #488] ; (8005cc0 ) 8005ad6: 699b ldr r3, [r3, #24] 8005ad8: f003 0304 and.w r3, r3, #4 8005adc: 613b str r3, [r7, #16] 8005ade: 693b ldr r3, [r7, #16] /**USART1 GPIO Configuration PA9 ------> USART1_TX PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_9; 8005ae0: f44f 7300 mov.w r3, #512 ; 0x200 8005ae4: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8005ae6: 2302 movs r3, #2 8005ae8: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8005aea: 2303 movs r3, #3 8005aec: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8005aee: f107 0318 add.w r3, r7, #24 8005af2: 4619 mov r1, r3 8005af4: 4873 ldr r0, [pc, #460] ; (8005cc4 ) 8005af6: f7fd fbb9 bl 800326c GPIO_InitStruct.Pin = GPIO_PIN_10; 8005afa: f44f 6380 mov.w r3, #1024 ; 0x400 8005afe: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8005b00: 2300 movs r3, #0 8005b02: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 8005b04: 2300 movs r3, #0 8005b06: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8005b08: f107 0318 add.w r3, r7, #24 8005b0c: 4619 mov r1, r3 8005b0e: 486d ldr r0, [pc, #436] ; (8005cc4 ) 8005b10: f7fd fbac bl 800326c /* USART1 DMA Init */ /* USART1_TX Init */ hdma_usart1_tx.Instance = DMA1_Channel4; 8005b14: 4b6c ldr r3, [pc, #432] ; (8005cc8 ) 8005b16: 4a6d ldr r2, [pc, #436] ; (8005ccc ) 8005b18: 601a str r2, [r3, #0] hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 8005b1a: 4b6b ldr r3, [pc, #428] ; (8005cc8 ) 8005b1c: 2210 movs r2, #16 8005b1e: 605a str r2, [r3, #4] hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE; 8005b20: 4b69 ldr r3, [pc, #420] ; (8005cc8 ) 8005b22: 2200 movs r2, #0 8005b24: 609a str r2, [r3, #8] hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE; 8005b26: 4b68 ldr r3, [pc, #416] ; (8005cc8 ) 8005b28: 2280 movs r2, #128 ; 0x80 8005b2a: 60da str r2, [r3, #12] hdma_usart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8005b2c: 4b66 ldr r3, [pc, #408] ; (8005cc8 ) 8005b2e: 2200 movs r2, #0 8005b30: 611a str r2, [r3, #16] hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8005b32: 4b65 ldr r3, [pc, #404] ; (8005cc8 ) 8005b34: 2200 movs r2, #0 8005b36: 615a str r2, [r3, #20] hdma_usart1_tx.Init.Mode = DMA_NORMAL; 8005b38: 4b63 ldr r3, [pc, #396] ; (8005cc8 ) 8005b3a: 2200 movs r2, #0 8005b3c: 619a str r2, [r3, #24] hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW; 8005b3e: 4b62 ldr r3, [pc, #392] ; (8005cc8 ) 8005b40: 2200 movs r2, #0 8005b42: 61da str r2, [r3, #28] if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK) 8005b44: 4860 ldr r0, [pc, #384] ; (8005cc8 ) 8005b46: f7fc ff2d bl 80029a4 8005b4a: 4603 mov r3, r0 8005b4c: 2b00 cmp r3, #0 8005b4e: d001 beq.n 8005b54 { Error_Handler(); 8005b50: f7ff fee0 bl 8005914 } __HAL_LINKDMA(huart,hdmatx,hdma_usart1_tx); 8005b54: 687b ldr r3, [r7, #4] 8005b56: 4a5c ldr r2, [pc, #368] ; (8005cc8 ) 8005b58: 631a str r2, [r3, #48] ; 0x30 8005b5a: 4a5b ldr r2, [pc, #364] ; (8005cc8 ) 8005b5c: 687b ldr r3, [r7, #4] 8005b5e: 6253 str r3, [r2, #36] ; 0x24 /* USART1_RX Init */ hdma_usart1_rx.Instance = DMA1_Channel5; 8005b60: 4b5b ldr r3, [pc, #364] ; (8005cd0 ) 8005b62: 4a5c ldr r2, [pc, #368] ; (8005cd4 ) 8005b64: 601a str r2, [r3, #0] hdma_usart1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 8005b66: 4b5a ldr r3, [pc, #360] ; (8005cd0 ) 8005b68: 2200 movs r2, #0 8005b6a: 605a str r2, [r3, #4] hdma_usart1_rx.Init.PeriphInc = DMA_PINC_DISABLE; 8005b6c: 4b58 ldr r3, [pc, #352] ; (8005cd0 ) 8005b6e: 2200 movs r2, #0 8005b70: 609a str r2, [r3, #8] hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE; 8005b72: 4b57 ldr r3, [pc, #348] ; (8005cd0 ) 8005b74: 2280 movs r2, #128 ; 0x80 8005b76: 60da str r2, [r3, #12] hdma_usart1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8005b78: 4b55 ldr r3, [pc, #340] ; (8005cd0 ) 8005b7a: 2200 movs r2, #0 8005b7c: 611a str r2, [r3, #16] hdma_usart1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8005b7e: 4b54 ldr r3, [pc, #336] ; (8005cd0 ) 8005b80: 2200 movs r2, #0 8005b82: 615a str r2, [r3, #20] hdma_usart1_rx.Init.Mode = DMA_NORMAL; 8005b84: 4b52 ldr r3, [pc, #328] ; (8005cd0 ) 8005b86: 2200 movs r2, #0 8005b88: 619a str r2, [r3, #24] hdma_usart1_rx.Init.Priority = DMA_PRIORITY_LOW; 8005b8a: 4b51 ldr r3, [pc, #324] ; (8005cd0 ) 8005b8c: 2200 movs r2, #0 8005b8e: 61da str r2, [r3, #28] if (HAL_DMA_Init(&hdma_usart1_rx) != HAL_OK) 8005b90: 484f ldr r0, [pc, #316] ; (8005cd0 ) 8005b92: f7fc ff07 bl 80029a4 8005b96: 4603 mov r3, r0 8005b98: 2b00 cmp r3, #0 8005b9a: d001 beq.n 8005ba0 { Error_Handler(); 8005b9c: f7ff feba bl 8005914 } __HAL_LINKDMA(huart,hdmarx,hdma_usart1_rx); 8005ba0: 687b ldr r3, [r7, #4] 8005ba2: 4a4b ldr r2, [pc, #300] ; (8005cd0 ) 8005ba4: 635a str r2, [r3, #52] ; 0x34 8005ba6: 4a4a ldr r2, [pc, #296] ; (8005cd0 ) 8005ba8: 687b ldr r3, [r7, #4] 8005baa: 6253 str r3, [r2, #36] ; 0x24 /* USER CODE BEGIN USART3_MspInit 1 */ /* USER CODE END USART3_MspInit 1 */ } } 8005bac: e082 b.n 8005cb4 else if(huart->Instance==USART3) 8005bae: 687b ldr r3, [r7, #4] 8005bb0: 681b ldr r3, [r3, #0] 8005bb2: 4a49 ldr r2, [pc, #292] ; (8005cd8 ) 8005bb4: 4293 cmp r3, r2 8005bb6: d17d bne.n 8005cb4 __HAL_RCC_USART3_CLK_ENABLE(); 8005bb8: 4b41 ldr r3, [pc, #260] ; (8005cc0 ) 8005bba: 69db ldr r3, [r3, #28] 8005bbc: 4a40 ldr r2, [pc, #256] ; (8005cc0 ) 8005bbe: f443 2380 orr.w r3, r3, #262144 ; 0x40000 8005bc2: 61d3 str r3, [r2, #28] 8005bc4: 4b3e ldr r3, [pc, #248] ; (8005cc0 ) 8005bc6: 69db ldr r3, [r3, #28] 8005bc8: f403 2380 and.w r3, r3, #262144 ; 0x40000 8005bcc: 60fb str r3, [r7, #12] 8005bce: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOB_CLK_ENABLE(); 8005bd0: 4b3b ldr r3, [pc, #236] ; (8005cc0 ) 8005bd2: 699b ldr r3, [r3, #24] 8005bd4: 4a3a ldr r2, [pc, #232] ; (8005cc0 ) 8005bd6: f043 0308 orr.w r3, r3, #8 8005bda: 6193 str r3, [r2, #24] 8005bdc: 4b38 ldr r3, [pc, #224] ; (8005cc0 ) 8005bde: 699b ldr r3, [r3, #24] 8005be0: f003 0308 and.w r3, r3, #8 8005be4: 60bb str r3, [r7, #8] 8005be6: 68bb ldr r3, [r7, #8] GPIO_InitStruct.Pin = GPIO_PIN_10; 8005be8: f44f 6380 mov.w r3, #1024 ; 0x400 8005bec: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8005bee: 2302 movs r3, #2 8005bf0: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 8005bf2: 2303 movs r3, #3 8005bf4: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8005bf6: f107 0318 add.w r3, r7, #24 8005bfa: 4619 mov r1, r3 8005bfc: 4837 ldr r0, [pc, #220] ; (8005cdc ) 8005bfe: f7fd fb35 bl 800326c GPIO_InitStruct.Pin = GPIO_PIN_11; 8005c02: f44f 6300 mov.w r3, #2048 ; 0x800 8005c06: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8005c08: 2300 movs r3, #0 8005c0a: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 8005c0c: 2300 movs r3, #0 8005c0e: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8005c10: f107 0318 add.w r3, r7, #24 8005c14: 4619 mov r1, r3 8005c16: 4831 ldr r0, [pc, #196] ; (8005cdc ) 8005c18: f7fd fb28 bl 800326c hdma_usart3_tx.Instance = DMA1_Channel2; 8005c1c: 4b30 ldr r3, [pc, #192] ; (8005ce0 ) 8005c1e: 4a31 ldr r2, [pc, #196] ; (8005ce4 ) 8005c20: 601a str r2, [r3, #0] hdma_usart3_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 8005c22: 4b2f ldr r3, [pc, #188] ; (8005ce0 ) 8005c24: 2210 movs r2, #16 8005c26: 605a str r2, [r3, #4] hdma_usart3_tx.Init.PeriphInc = DMA_PINC_DISABLE; 8005c28: 4b2d ldr r3, [pc, #180] ; (8005ce0 ) 8005c2a: 2200 movs r2, #0 8005c2c: 609a str r2, [r3, #8] hdma_usart3_tx.Init.MemInc = DMA_MINC_ENABLE; 8005c2e: 4b2c ldr r3, [pc, #176] ; (8005ce0 ) 8005c30: 2280 movs r2, #128 ; 0x80 8005c32: 60da str r2, [r3, #12] hdma_usart3_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8005c34: 4b2a ldr r3, [pc, #168] ; (8005ce0 ) 8005c36: 2200 movs r2, #0 8005c38: 611a str r2, [r3, #16] hdma_usart3_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8005c3a: 4b29 ldr r3, [pc, #164] ; (8005ce0 ) 8005c3c: 2200 movs r2, #0 8005c3e: 615a str r2, [r3, #20] hdma_usart3_tx.Init.Mode = DMA_NORMAL; 8005c40: 4b27 ldr r3, [pc, #156] ; (8005ce0 ) 8005c42: 2200 movs r2, #0 8005c44: 619a str r2, [r3, #24] hdma_usart3_tx.Init.Priority = DMA_PRIORITY_LOW; 8005c46: 4b26 ldr r3, [pc, #152] ; (8005ce0 ) 8005c48: 2200 movs r2, #0 8005c4a: 61da str r2, [r3, #28] if (HAL_DMA_Init(&hdma_usart3_tx) != HAL_OK) 8005c4c: 4824 ldr r0, [pc, #144] ; (8005ce0 ) 8005c4e: f7fc fea9 bl 80029a4 8005c52: 4603 mov r3, r0 8005c54: 2b00 cmp r3, #0 8005c56: d001 beq.n 8005c5c Error_Handler(); 8005c58: f7ff fe5c bl 8005914 __HAL_LINKDMA(huart,hdmatx,hdma_usart3_tx); 8005c5c: 687b ldr r3, [r7, #4] 8005c5e: 4a20 ldr r2, [pc, #128] ; (8005ce0 ) 8005c60: 631a str r2, [r3, #48] ; 0x30 8005c62: 4a1f ldr r2, [pc, #124] ; (8005ce0 ) 8005c64: 687b ldr r3, [r7, #4] 8005c66: 6253 str r3, [r2, #36] ; 0x24 hdma_usart3_rx.Instance = DMA1_Channel3; 8005c68: 4b1f ldr r3, [pc, #124] ; (8005ce8 ) 8005c6a: 4a20 ldr r2, [pc, #128] ; (8005cec ) 8005c6c: 601a str r2, [r3, #0] hdma_usart3_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 8005c6e: 4b1e ldr r3, [pc, #120] ; (8005ce8 ) 8005c70: 2200 movs r2, #0 8005c72: 605a str r2, [r3, #4] hdma_usart3_rx.Init.PeriphInc = DMA_PINC_DISABLE; 8005c74: 4b1c ldr r3, [pc, #112] ; (8005ce8 ) 8005c76: 2200 movs r2, #0 8005c78: 609a str r2, [r3, #8] hdma_usart3_rx.Init.MemInc = DMA_MINC_ENABLE; 8005c7a: 4b1b ldr r3, [pc, #108] ; (8005ce8 ) 8005c7c: 2280 movs r2, #128 ; 0x80 8005c7e: 60da str r2, [r3, #12] hdma_usart3_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8005c80: 4b19 ldr r3, [pc, #100] ; (8005ce8 ) 8005c82: 2200 movs r2, #0 8005c84: 611a str r2, [r3, #16] hdma_usart3_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8005c86: 4b18 ldr r3, [pc, #96] ; (8005ce8 ) 8005c88: 2200 movs r2, #0 8005c8a: 615a str r2, [r3, #20] hdma_usart3_rx.Init.Mode = DMA_NORMAL; 8005c8c: 4b16 ldr r3, [pc, #88] ; (8005ce8 ) 8005c8e: 2200 movs r2, #0 8005c90: 619a str r2, [r3, #24] hdma_usart3_rx.Init.Priority = DMA_PRIORITY_LOW; 8005c92: 4b15 ldr r3, [pc, #84] ; (8005ce8 ) 8005c94: 2200 movs r2, #0 8005c96: 61da str r2, [r3, #28] if (HAL_DMA_Init(&hdma_usart3_rx) != HAL_OK) 8005c98: 4813 ldr r0, [pc, #76] ; (8005ce8 ) 8005c9a: f7fc fe83 bl 80029a4 8005c9e: 4603 mov r3, r0 8005ca0: 2b00 cmp r3, #0 8005ca2: d001 beq.n 8005ca8 Error_Handler(); 8005ca4: f7ff fe36 bl 8005914 __HAL_LINKDMA(huart,hdmarx,hdma_usart3_rx); 8005ca8: 687b ldr r3, [r7, #4] 8005caa: 4a0f ldr r2, [pc, #60] ; (8005ce8 ) 8005cac: 635a str r2, [r3, #52] ; 0x34 8005cae: 4a0e ldr r2, [pc, #56] ; (8005ce8 ) 8005cb0: 687b ldr r3, [r7, #4] 8005cb2: 6253 str r3, [r2, #36] ; 0x24 } 8005cb4: bf00 nop 8005cb6: 3728 adds r7, #40 ; 0x28 8005cb8: 46bd mov sp, r7 8005cba: bd80 pop {r7, pc} 8005cbc: 40013800 .word 0x40013800 8005cc0: 40021000 .word 0x40021000 8005cc4: 40010800 .word 0x40010800 8005cc8: 200009d8 .word 0x200009d8 8005ccc: 40020044 .word 0x40020044 8005cd0: 20000a4c .word 0x20000a4c 8005cd4: 40020058 .word 0x40020058 8005cd8: 40004800 .word 0x40004800 8005cdc: 40010c00 .word 0x40010c00 8005ce0: 20000994 .word 0x20000994 8005ce4: 4002001c .word 0x4002001c 8005ce8: 20000910 .word 0x20000910 8005cec: 40020030 .word 0x40020030 08005cf0 : * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). * @param TickPriority: Tick interrupt priority. * @retval HAL status */ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8005cf0: b580 push {r7, lr} 8005cf2: b08c sub sp, #48 ; 0x30 8005cf4: af00 add r7, sp, #0 8005cf6: 6078 str r0, [r7, #4] RCC_ClkInitTypeDef clkconfig; uint32_t uwTimclock = 0; 8005cf8: 2300 movs r3, #0 8005cfa: 62fb str r3, [r7, #44] ; 0x2c uint32_t uwPrescalerValue = 0; 8005cfc: 2300 movs r3, #0 8005cfe: 62bb str r3, [r7, #40] ; 0x28 uint32_t pFLatency; /*Configure the TIM2 IRQ priority */ HAL_NVIC_SetPriority(TIM2_IRQn, TickPriority ,0); 8005d00: 2200 movs r2, #0 8005d02: 6879 ldr r1, [r7, #4] 8005d04: 201c movs r0, #28 8005d06: f7fc fe22 bl 800294e /* Enable the TIM2 global Interrupt */ HAL_NVIC_EnableIRQ(TIM2_IRQn); 8005d0a: 201c movs r0, #28 8005d0c: f7fc fe3b bl 8002986 /* Enable TIM2 clock */ __HAL_RCC_TIM2_CLK_ENABLE(); 8005d10: 4b1f ldr r3, [pc, #124] ; (8005d90 ) 8005d12: 69db ldr r3, [r3, #28] 8005d14: 4a1e ldr r2, [pc, #120] ; (8005d90 ) 8005d16: f043 0301 orr.w r3, r3, #1 8005d1a: 61d3 str r3, [r2, #28] 8005d1c: 4b1c ldr r3, [pc, #112] ; (8005d90 ) 8005d1e: 69db ldr r3, [r3, #28] 8005d20: f003 0301 and.w r3, r3, #1 8005d24: 60fb str r3, [r7, #12] 8005d26: 68fb ldr r3, [r7, #12] /* Get clock configuration */ HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); 8005d28: f107 0210 add.w r2, r7, #16 8005d2c: f107 0314 add.w r3, r7, #20 8005d30: 4611 mov r1, r2 8005d32: 4618 mov r0, r3 8005d34: f7fe f80a bl 8003d4c /* Compute TIM2 clock */ uwTimclock = HAL_RCC_GetPCLK1Freq(); 8005d38: f7fd ffe0 bl 8003cfc 8005d3c: 62f8 str r0, [r7, #44] ; 0x2c /* Compute the prescaler value to have TIM2 counter clock equal to 1MHz */ uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000) - 1); 8005d3e: 6afb ldr r3, [r7, #44] ; 0x2c 8005d40: 4a14 ldr r2, [pc, #80] ; (8005d94 ) 8005d42: fba2 2303 umull r2, r3, r2, r3 8005d46: 0c9b lsrs r3, r3, #18 8005d48: 3b01 subs r3, #1 8005d4a: 62bb str r3, [r7, #40] ; 0x28 /* Initialize TIM2 */ htim2.Instance = TIM2; 8005d4c: 4b12 ldr r3, [pc, #72] ; (8005d98 ) 8005d4e: f04f 4280 mov.w r2, #1073741824 ; 0x40000000 8005d52: 601a str r2, [r3, #0] + Period = [(TIM2CLK/1000) - 1]. to have a (1/1000) s time base. + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. + ClockDivision = 0 + Counter direction = Up */ htim2.Init.Period = (1000000 / 1000) - 1; 8005d54: 4b10 ldr r3, [pc, #64] ; (8005d98 ) 8005d56: f240 32e7 movw r2, #999 ; 0x3e7 8005d5a: 60da str r2, [r3, #12] htim2.Init.Prescaler = uwPrescalerValue; 8005d5c: 4a0e ldr r2, [pc, #56] ; (8005d98 ) 8005d5e: 6abb ldr r3, [r7, #40] ; 0x28 8005d60: 6053 str r3, [r2, #4] htim2.Init.ClockDivision = 0; 8005d62: 4b0d ldr r3, [pc, #52] ; (8005d98 ) 8005d64: 2200 movs r2, #0 8005d66: 611a str r2, [r3, #16] htim2.Init.CounterMode = TIM_COUNTERMODE_UP; 8005d68: 4b0b ldr r3, [pc, #44] ; (8005d98 ) 8005d6a: 2200 movs r2, #0 8005d6c: 609a str r2, [r3, #8] if(HAL_TIM_Base_Init(&htim2) == HAL_OK) 8005d6e: 480a ldr r0, [pc, #40] ; (8005d98 ) 8005d70: f7fe f934 bl 8003fdc 8005d74: 4603 mov r3, r0 8005d76: 2b00 cmp r3, #0 8005d78: d104 bne.n 8005d84 { /* Start the TIM time Base generation in interrupt mode */ return HAL_TIM_Base_Start_IT(&htim2); 8005d7a: 4807 ldr r0, [pc, #28] ; (8005d98 ) 8005d7c: f7fe f959 bl 8004032 8005d80: 4603 mov r3, r0 8005d82: e000 b.n 8005d86 } /* Return function status */ return HAL_ERROR; 8005d84: 2301 movs r3, #1 } 8005d86: 4618 mov r0, r3 8005d88: 3730 adds r7, #48 ; 0x30 8005d8a: 46bd mov sp, r7 8005d8c: bd80 pop {r7, pc} 8005d8e: bf00 nop 8005d90: 40021000 .word 0x40021000 8005d94: 431bde83 .word 0x431bde83 8005d98: 20000b54 .word 0x20000b54 08005d9c : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8005d9c: b480 push {r7} 8005d9e: af00 add r7, sp, #0 /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ /* USER CODE END NonMaskableInt_IRQn 1 */ } 8005da0: bf00 nop 8005da2: 46bd mov sp, r7 8005da4: bc80 pop {r7} 8005da6: 4770 bx lr 08005da8 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8005da8: b480 push {r7} 8005daa: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8005dac: e7fe b.n 8005dac 08005dae : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8005dae: b480 push {r7} 8005db0: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8005db2: e7fe b.n 8005db2 08005db4 : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { 8005db4: b480 push {r7} 8005db6: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 8005db8: e7fe b.n 8005db8 08005dba : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8005dba: b480 push {r7} 8005dbc: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8005dbe: e7fe b.n 8005dbe 08005dc0 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 8005dc0: b480 push {r7} 8005dc2: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 8005dc4: bf00 nop 8005dc6: 46bd mov sp, r7 8005dc8: bc80 pop {r7} 8005dca: 4770 bx lr 08005dcc : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 8005dcc: b480 push {r7} 8005dce: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8005dd0: bf00 nop 8005dd2: 46bd mov sp, r7 8005dd4: bc80 pop {r7} 8005dd6: 4770 bx lr 08005dd8 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8005dd8: b480 push {r7} 8005dda: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 8005ddc: bf00 nop 8005dde: 46bd mov sp, r7 8005de0: bc80 pop {r7} 8005de2: 4770 bx lr 08005de4 : /** * @brief This function handles DMA1 channel1 global interrupt. */ void DMA1_Channel1_IRQHandler(void) { 8005de4: b580 push {r7, lr} 8005de6: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */ /* USER CODE END DMA1_Channel1_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc1); 8005de8: 4802 ldr r0, [pc, #8] ; (8005df4 ) 8005dea: f7fc ff0b bl 8002c04 /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */ /* USER CODE END DMA1_Channel1_IRQn 1 */ } 8005dee: bf00 nop 8005df0: bd80 pop {r7, pc} 8005df2: bf00 nop 8005df4: 20000ad0 .word 0x20000ad0 08005df8 : /** * @brief This function handles DMA1 channel2 global interrupt. */ void DMA1_Channel2_IRQHandler(void) { 8005df8: b580 push {r7, lr} 8005dfa: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Channel2_IRQn 0 */ /* USER CODE END DMA1_Channel2_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart3_tx); 8005dfc: 4802 ldr r0, [pc, #8] ; (8005e08 ) 8005dfe: f7fc ff01 bl 8002c04 /* USER CODE BEGIN DMA1_Channel2_IRQn 1 */ /* USER CODE END DMA1_Channel2_IRQn 1 */ } 8005e02: bf00 nop 8005e04: bd80 pop {r7, pc} 8005e06: bf00 nop 8005e08: 20000994 .word 0x20000994 08005e0c : /** * @brief This function handles DMA1 channel3 global interrupt. */ void DMA1_Channel3_IRQHandler(void) { 8005e0c: b580 push {r7, lr} 8005e0e: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Channel3_IRQn 0 */ /* USER CODE END DMA1_Channel3_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart3_rx); 8005e10: 4802 ldr r0, [pc, #8] ; (8005e1c ) 8005e12: f7fc fef7 bl 8002c04 /* USER CODE BEGIN DMA1_Channel3_IRQn 1 */ /* USER CODE END DMA1_Channel3_IRQn 1 */ } 8005e16: bf00 nop 8005e18: bd80 pop {r7, pc} 8005e1a: bf00 nop 8005e1c: 20000910 .word 0x20000910 08005e20 : /** * @brief This function handles DMA1 channel4 global interrupt. */ void DMA1_Channel4_IRQHandler(void) { 8005e20: b580 push {r7, lr} 8005e22: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Channel4_IRQn 0 */ /* USER CODE END DMA1_Channel4_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart1_tx); 8005e24: 4802 ldr r0, [pc, #8] ; (8005e30 ) 8005e26: f7fc feed bl 8002c04 /* USER CODE BEGIN DMA1_Channel4_IRQn 1 */ /* USER CODE END DMA1_Channel4_IRQn 1 */ } 8005e2a: bf00 nop 8005e2c: bd80 pop {r7, pc} 8005e2e: bf00 nop 8005e30: 200009d8 .word 0x200009d8 08005e34 : /** * @brief This function handles DMA1 channel5 global interrupt. */ void DMA1_Channel5_IRQHandler(void) { 8005e34: b580 push {r7, lr} 8005e36: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Channel5_IRQn 0 */ /* USER CODE END DMA1_Channel5_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart1_rx); 8005e38: 4802 ldr r0, [pc, #8] ; (8005e44 ) 8005e3a: f7fc fee3 bl 8002c04 /* USER CODE BEGIN DMA1_Channel5_IRQn 1 */ /* USER CODE END DMA1_Channel5_IRQn 1 */ } 8005e3e: bf00 nop 8005e40: bd80 pop {r7, pc} 8005e42: bf00 nop 8005e44: 20000a4c .word 0x20000a4c 08005e48 : /** * @brief This function handles ADC1 global interrupt. */ void ADC1_IRQHandler(void) { 8005e48: b580 push {r7, lr} 8005e4a: af00 add r7, sp, #0 /* USER CODE BEGIN ADC1_IRQn 0 */ /* USER CODE END ADC1_IRQn 0 */ HAL_ADC_IRQHandler(&hadc1); 8005e4c: 4802 ldr r0, [pc, #8] ; (8005e58 ) 8005e4e: f7fc f95b bl 8002108 /* USER CODE BEGIN ADC1_IRQn 1 */ /* USER CODE END ADC1_IRQn 1 */ } 8005e52: bf00 nop 8005e54: bd80 pop {r7, pc} 8005e56: bf00 nop 8005e58: 20000a1c .word 0x20000a1c 08005e5c : /** * @brief This function handles TIM2 global interrupt. */ void TIM2_IRQHandler(void) { 8005e5c: b580 push {r7, lr} 8005e5e: af00 add r7, sp, #0 /* USER CODE BEGIN TIM2_IRQn 0 */ /* USER CODE END TIM2_IRQn 0 */ HAL_TIM_IRQHandler(&htim2); 8005e60: 4802 ldr r0, [pc, #8] ; (8005e6c ) 8005e62: f7fe f909 bl 8004078 /* USER CODE BEGIN TIM2_IRQn 1 */ /* USER CODE END TIM2_IRQn 1 */ } 8005e66: bf00 nop 8005e68: bd80 pop {r7, pc} 8005e6a: bf00 nop 8005e6c: 20000b54 .word 0x20000b54 08005e70 : /** * @brief This function handles USART1 global interrupt. */ void USART1_IRQHandler(void) { 8005e70: b580 push {r7, lr} 8005e72: af00 add r7, sp, #0 /* USER CODE BEGIN USART1_IRQn 0 */ /* USER CODE END USART1_IRQn 0 */ HAL_UART_IRQHandler(&huart1); 8005e74: 4802 ldr r0, [pc, #8] ; (8005e80 ) 8005e76: f7fe fd27 bl 80048c8 /* USER CODE BEGIN USART1_IRQn 1 */ /* USER CODE END USART1_IRQn 1 */ } 8005e7a: bf00 nop 8005e7c: bd80 pop {r7, pc} 8005e7e: bf00 nop 8005e80: 20000a90 .word 0x20000a90 08005e84 : /** * @brief This function handles USART3 global interrupt. */ void USART3_IRQHandler(void) { 8005e84: b580 push {r7, lr} 8005e86: af00 add r7, sp, #0 /* USER CODE BEGIN USART3_IRQn 0 */ /* USER CODE END USART3_IRQn 0 */ HAL_UART_IRQHandler(&huart3); 8005e88: 4802 ldr r0, [pc, #8] ; (8005e94 ) 8005e8a: f7fe fd1d bl 80048c8 /* USER CODE BEGIN USART3_IRQn 1 */ /* USER CODE END USART3_IRQn 1 */ } 8005e8e: bf00 nop 8005e90: bd80 pop {r7, pc} 8005e92: bf00 nop 8005e94: 20000954 .word 0x20000954 08005e98 : /** * @brief This function handles TIM6 global interrupt and DAC underrun error interrupts. */ void TIM6_DAC_IRQHandler(void) { 8005e98: b580 push {r7, lr} 8005e9a: af00 add r7, sp, #0 /* USER CODE BEGIN TIM6_DAC_IRQn 0 */ /* USER CODE END TIM6_DAC_IRQn 0 */ HAL_TIM_IRQHandler(&htim6); 8005e9c: 4802 ldr r0, [pc, #8] ; (8005ea8 ) 8005e9e: f7fe f8eb bl 8004078 /* USER CODE BEGIN TIM6_DAC_IRQn 1 */ /* USER CODE END TIM6_DAC_IRQn 1 */ } 8005ea2: bf00 nop 8005ea4: bd80 pop {r7, pc} 8005ea6: bf00 nop 8005ea8: 20000b14 .word 0x20000b14 08005eac <_read>: _kill(status, -1); while (1) {} /* Make sure we hang here */ } __attribute__((weak)) int _read(int file, char *ptr, int len) { 8005eac: b580 push {r7, lr} 8005eae: b086 sub sp, #24 8005eb0: af00 add r7, sp, #0 8005eb2: 60f8 str r0, [r7, #12] 8005eb4: 60b9 str r1, [r7, #8] 8005eb6: 607a str r2, [r7, #4] int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 8005eb8: 2300 movs r3, #0 8005eba: 617b str r3, [r7, #20] 8005ebc: e00a b.n 8005ed4 <_read+0x28> { *ptr++ = __io_getchar(); 8005ebe: f3af 8000 nop.w 8005ec2: 4601 mov r1, r0 8005ec4: 68bb ldr r3, [r7, #8] 8005ec6: 1c5a adds r2, r3, #1 8005ec8: 60ba str r2, [r7, #8] 8005eca: b2ca uxtb r2, r1 8005ecc: 701a strb r2, [r3, #0] for (DataIdx = 0; DataIdx < len; DataIdx++) 8005ece: 697b ldr r3, [r7, #20] 8005ed0: 3301 adds r3, #1 8005ed2: 617b str r3, [r7, #20] 8005ed4: 697a ldr r2, [r7, #20] 8005ed6: 687b ldr r3, [r7, #4] 8005ed8: 429a cmp r2, r3 8005eda: dbf0 blt.n 8005ebe <_read+0x12> } return len; 8005edc: 687b ldr r3, [r7, #4] } 8005ede: 4618 mov r0, r3 8005ee0: 3718 adds r7, #24 8005ee2: 46bd mov sp, r7 8005ee4: bd80 pop {r7, pc} 08005ee6 <_close>: } return len; } int _close(int file) { 8005ee6: b480 push {r7} 8005ee8: b083 sub sp, #12 8005eea: af00 add r7, sp, #0 8005eec: 6078 str r0, [r7, #4] return -1; 8005eee: f04f 33ff mov.w r3, #4294967295 } 8005ef2: 4618 mov r0, r3 8005ef4: 370c adds r7, #12 8005ef6: 46bd mov sp, r7 8005ef8: bc80 pop {r7} 8005efa: 4770 bx lr 08005efc <_fstat>: int _fstat(int file, struct stat *st) { 8005efc: b480 push {r7} 8005efe: b083 sub sp, #12 8005f00: af00 add r7, sp, #0 8005f02: 6078 str r0, [r7, #4] 8005f04: 6039 str r1, [r7, #0] st->st_mode = S_IFCHR; 8005f06: 683b ldr r3, [r7, #0] 8005f08: f44f 5200 mov.w r2, #8192 ; 0x2000 8005f0c: 605a str r2, [r3, #4] return 0; 8005f0e: 2300 movs r3, #0 } 8005f10: 4618 mov r0, r3 8005f12: 370c adds r7, #12 8005f14: 46bd mov sp, r7 8005f16: bc80 pop {r7} 8005f18: 4770 bx lr 08005f1a <_isatty>: int _isatty(int file) { 8005f1a: b480 push {r7} 8005f1c: b083 sub sp, #12 8005f1e: af00 add r7, sp, #0 8005f20: 6078 str r0, [r7, #4] return 1; 8005f22: 2301 movs r3, #1 } 8005f24: 4618 mov r0, r3 8005f26: 370c adds r7, #12 8005f28: 46bd mov sp, r7 8005f2a: bc80 pop {r7} 8005f2c: 4770 bx lr 08005f2e <_lseek>: int _lseek(int file, int ptr, int dir) { 8005f2e: b480 push {r7} 8005f30: b085 sub sp, #20 8005f32: af00 add r7, sp, #0 8005f34: 60f8 str r0, [r7, #12] 8005f36: 60b9 str r1, [r7, #8] 8005f38: 607a str r2, [r7, #4] return 0; 8005f3a: 2300 movs r3, #0 } 8005f3c: 4618 mov r0, r3 8005f3e: 3714 adds r7, #20 8005f40: 46bd mov sp, r7 8005f42: bc80 pop {r7} 8005f44: 4770 bx lr ... 08005f48 <_sbrk>: /** _sbrk Increase program data space. Malloc and related functions depend on this **/ caddr_t _sbrk(int incr) { 8005f48: b580 push {r7, lr} 8005f4a: b084 sub sp, #16 8005f4c: af00 add r7, sp, #0 8005f4e: 6078 str r0, [r7, #4] extern char end asm("end"); static char *heap_end; char *prev_heap_end; if (heap_end == 0) 8005f50: 4b11 ldr r3, [pc, #68] ; (8005f98 <_sbrk+0x50>) 8005f52: 681b ldr r3, [r3, #0] 8005f54: 2b00 cmp r3, #0 8005f56: d102 bne.n 8005f5e <_sbrk+0x16> heap_end = &end; 8005f58: 4b0f ldr r3, [pc, #60] ; (8005f98 <_sbrk+0x50>) 8005f5a: 4a10 ldr r2, [pc, #64] ; (8005f9c <_sbrk+0x54>) 8005f5c: 601a str r2, [r3, #0] prev_heap_end = heap_end; 8005f5e: 4b0e ldr r3, [pc, #56] ; (8005f98 <_sbrk+0x50>) 8005f60: 681b ldr r3, [r3, #0] 8005f62: 60fb str r3, [r7, #12] if (heap_end + incr > stack_ptr) 8005f64: 4b0c ldr r3, [pc, #48] ; (8005f98 <_sbrk+0x50>) 8005f66: 681a ldr r2, [r3, #0] 8005f68: 687b ldr r3, [r7, #4] 8005f6a: 4413 add r3, r2 8005f6c: 466a mov r2, sp 8005f6e: 4293 cmp r3, r2 8005f70: d907 bls.n 8005f82 <_sbrk+0x3a> { errno = ENOMEM; 8005f72: f000 f873 bl 800605c <__errno> 8005f76: 4602 mov r2, r0 8005f78: 230c movs r3, #12 8005f7a: 6013 str r3, [r2, #0] return (caddr_t) -1; 8005f7c: f04f 33ff mov.w r3, #4294967295 8005f80: e006 b.n 8005f90 <_sbrk+0x48> } heap_end += incr; 8005f82: 4b05 ldr r3, [pc, #20] ; (8005f98 <_sbrk+0x50>) 8005f84: 681a ldr r2, [r3, #0] 8005f86: 687b ldr r3, [r7, #4] 8005f88: 4413 add r3, r2 8005f8a: 4a03 ldr r2, [pc, #12] ; (8005f98 <_sbrk+0x50>) 8005f8c: 6013 str r3, [r2, #0] return (caddr_t) prev_heap_end; 8005f8e: 68fb ldr r3, [r7, #12] } 8005f90: 4618 mov r0, r3 8005f92: 3710 adds r7, #16 8005f94: 46bd mov sp, r7 8005f96: bd80 pop {r7, pc} 8005f98: 2000063c .word 0x2000063c 8005f9c: 20000b98 .word 0x20000b98 08005fa0 : * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit (void) { 8005fa0: b480 push {r7} 8005fa2: af00 add r7, sp, #0 /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ /* Set HSION bit */ RCC->CR |= 0x00000001U; 8005fa4: 4b17 ldr r3, [pc, #92] ; (8006004 ) 8005fa6: 681b ldr r3, [r3, #0] 8005fa8: 4a16 ldr r2, [pc, #88] ; (8006004 ) 8005faa: f043 0301 orr.w r3, r3, #1 8005fae: 6013 str r3, [r2, #0] /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ #if !defined(STM32F105xC) && !defined(STM32F107xC) RCC->CFGR &= 0xF8FF0000U; 8005fb0: 4b14 ldr r3, [pc, #80] ; (8006004 ) 8005fb2: 685a ldr r2, [r3, #4] 8005fb4: 4913 ldr r1, [pc, #76] ; (8006004 ) 8005fb6: 4b14 ldr r3, [pc, #80] ; (8006008 ) 8005fb8: 4013 ands r3, r2 8005fba: 604b str r3, [r1, #4] #else RCC->CFGR &= 0xF0FF0000U; #endif /* STM32F105xC */ /* Reset HSEON, CSSON and PLLON bits */ RCC->CR &= 0xFEF6FFFFU; 8005fbc: 4b11 ldr r3, [pc, #68] ; (8006004 ) 8005fbe: 681b ldr r3, [r3, #0] 8005fc0: 4a10 ldr r2, [pc, #64] ; (8006004 ) 8005fc2: f023 7384 bic.w r3, r3, #17301504 ; 0x1080000 8005fc6: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8005fca: 6013 str r3, [r2, #0] /* Reset HSEBYP bit */ RCC->CR &= 0xFFFBFFFFU; 8005fcc: 4b0d ldr r3, [pc, #52] ; (8006004 ) 8005fce: 681b ldr r3, [r3, #0] 8005fd0: 4a0c ldr r2, [pc, #48] ; (8006004 ) 8005fd2: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8005fd6: 6013 str r3, [r2, #0] /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ RCC->CFGR &= 0xFF80FFFFU; 8005fd8: 4b0a ldr r3, [pc, #40] ; (8006004 ) 8005fda: 685b ldr r3, [r3, #4] 8005fdc: 4a09 ldr r2, [pc, #36] ; (8006004 ) 8005fde: f423 03fe bic.w r3, r3, #8323072 ; 0x7f0000 8005fe2: 6053 str r3, [r2, #4] /* Reset CFGR2 register */ RCC->CFGR2 = 0x00000000U; #elif defined(STM32F100xB) || defined(STM32F100xE) /* Disable all interrupts and clear pending bits */ RCC->CIR = 0x009F0000U; 8005fe4: 4b07 ldr r3, [pc, #28] ; (8006004 ) 8005fe6: f44f 021f mov.w r2, #10420224 ; 0x9f0000 8005fea: 609a str r2, [r3, #8] /* Reset CFGR2 register */ RCC->CFGR2 = 0x00000000U; 8005fec: 4b05 ldr r3, [pc, #20] ; (8006004 ) 8005fee: 2200 movs r2, #0 8005ff0: 62da str r2, [r3, #44] ; 0x2c #endif #ifdef VECT_TAB_SRAM SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #else SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ 8005ff2: 4b06 ldr r3, [pc, #24] ; (800600c ) 8005ff4: f04f 6200 mov.w r2, #134217728 ; 0x8000000 8005ff8: 609a str r2, [r3, #8] #endif } 8005ffa: bf00 nop 8005ffc: 46bd mov sp, r7 8005ffe: bc80 pop {r7} 8006000: 4770 bx lr 8006002: bf00 nop 8006004: 40021000 .word 0x40021000 8006008: f8ff0000 .word 0xf8ff0000 800600c: e000ed00 .word 0xe000ed00 08006010 : .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 8006010: 2100 movs r1, #0 b LoopCopyDataInit 8006012: e003 b.n 800601c 08006014 : CopyDataInit: ldr r3, =_sidata 8006014: 4b0b ldr r3, [pc, #44] ; (8006044 ) ldr r3, [r3, r1] 8006016: 585b ldr r3, [r3, r1] str r3, [r0, r1] 8006018: 5043 str r3, [r0, r1] adds r1, r1, #4 800601a: 3104 adds r1, #4 0800601c : LoopCopyDataInit: ldr r0, =_sdata 800601c: 480a ldr r0, [pc, #40] ; (8006048 ) ldr r3, =_edata 800601e: 4b0b ldr r3, [pc, #44] ; (800604c ) adds r2, r0, r1 8006020: 1842 adds r2, r0, r1 cmp r2, r3 8006022: 429a cmp r2, r3 bcc CopyDataInit 8006024: d3f6 bcc.n 8006014 ldr r2, =_sbss 8006026: 4a0a ldr r2, [pc, #40] ; (8006050 ) b LoopFillZerobss 8006028: e002 b.n 8006030 0800602a : /* Zero fill the bss segment. */ FillZerobss: movs r3, #0 800602a: 2300 movs r3, #0 str r3, [r2], #4 800602c: f842 3b04 str.w r3, [r2], #4 08006030 : LoopFillZerobss: ldr r3, = _ebss 8006030: 4b08 ldr r3, [pc, #32] ; (8006054 ) cmp r2, r3 8006032: 429a cmp r2, r3 bcc FillZerobss 8006034: d3f9 bcc.n 800602a /* Call the clock system intitialization function.*/ bl SystemInit 8006036: f7ff ffb3 bl 8005fa0 /* Call static constructors */ bl __libc_init_array 800603a: f000 f815 bl 8006068 <__libc_init_array> /* Call the application's entry point.*/ bl main 800603e: f7ff f941 bl 80052c4
bx lr 8006042: 4770 bx lr ldr r3, =_sidata 8006044: 08008fd0 .word 0x08008fd0 ldr r0, =_sdata 8006048: 20000000 .word 0x20000000 ldr r3, =_edata 800604c: 200001dc .word 0x200001dc ldr r2, =_sbss 8006050: 200001e0 .word 0x200001e0 ldr r3, = _ebss 8006054: 20000b98 .word 0x20000b98 08006058 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8006058: e7fe b.n 8006058 ... 0800605c <__errno>: 800605c: 4b01 ldr r3, [pc, #4] ; (8006064 <__errno+0x8>) 800605e: 6818 ldr r0, [r3, #0] 8006060: 4770 bx lr 8006062: bf00 nop 8006064: 2000000c .word 0x2000000c 08006068 <__libc_init_array>: 8006068: b570 push {r4, r5, r6, lr} 800606a: 2500 movs r5, #0 800606c: 4e0c ldr r6, [pc, #48] ; (80060a0 <__libc_init_array+0x38>) 800606e: 4c0d ldr r4, [pc, #52] ; (80060a4 <__libc_init_array+0x3c>) 8006070: 1ba4 subs r4, r4, r6 8006072: 10a4 asrs r4, r4, #2 8006074: 42a5 cmp r5, r4 8006076: d109 bne.n 800608c <__libc_init_array+0x24> 8006078: f002 fc60 bl 800893c <_init> 800607c: 2500 movs r5, #0 800607e: 4e0a ldr r6, [pc, #40] ; (80060a8 <__libc_init_array+0x40>) 8006080: 4c0a ldr r4, [pc, #40] ; (80060ac <__libc_init_array+0x44>) 8006082: 1ba4 subs r4, r4, r6 8006084: 10a4 asrs r4, r4, #2 8006086: 42a5 cmp r5, r4 8006088: d105 bne.n 8006096 <__libc_init_array+0x2e> 800608a: bd70 pop {r4, r5, r6, pc} 800608c: f856 3025 ldr.w r3, [r6, r5, lsl #2] 8006090: 4798 blx r3 8006092: 3501 adds r5, #1 8006094: e7ee b.n 8006074 <__libc_init_array+0xc> 8006096: f856 3025 ldr.w r3, [r6, r5, lsl #2] 800609a: 4798 blx r3 800609c: 3501 adds r5, #1 800609e: e7f2 b.n 8006086 <__libc_init_array+0x1e> 80060a0: 08008fc8 .word 0x08008fc8 80060a4: 08008fc8 .word 0x08008fc8 80060a8: 08008fc8 .word 0x08008fc8 80060ac: 08008fcc .word 0x08008fcc 080060b0 : 80060b0: 4603 mov r3, r0 80060b2: 4402 add r2, r0 80060b4: 4293 cmp r3, r2 80060b6: d100 bne.n 80060ba 80060b8: 4770 bx lr 80060ba: f803 1b01 strb.w r1, [r3], #1 80060be: e7f9 b.n 80060b4 080060c0 <__cvt>: 80060c0: 2b00 cmp r3, #0 80060c2: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 80060c6: 461e mov r6, r3 80060c8: bfbb ittet lt 80060ca: f103 4300 addlt.w r3, r3, #2147483648 ; 0x80000000 80060ce: 461e movlt r6, r3 80060d0: 2300 movge r3, #0 80060d2: 232d movlt r3, #45 ; 0x2d 80060d4: b088 sub sp, #32 80060d6: 9f14 ldr r7, [sp, #80] ; 0x50 80060d8: e9dd 1a12 ldrd r1, sl, [sp, #72] ; 0x48 80060dc: f027 0720 bic.w r7, r7, #32 80060e0: 2f46 cmp r7, #70 ; 0x46 80060e2: 4614 mov r4, r2 80060e4: 9d10 ldr r5, [sp, #64] ; 0x40 80060e6: 700b strb r3, [r1, #0] 80060e8: d004 beq.n 80060f4 <__cvt+0x34> 80060ea: 2f45 cmp r7, #69 ; 0x45 80060ec: d100 bne.n 80060f0 <__cvt+0x30> 80060ee: 3501 adds r5, #1 80060f0: 2302 movs r3, #2 80060f2: e000 b.n 80060f6 <__cvt+0x36> 80060f4: 2303 movs r3, #3 80060f6: aa07 add r2, sp, #28 80060f8: 9204 str r2, [sp, #16] 80060fa: aa06 add r2, sp, #24 80060fc: e9cd a202 strd sl, r2, [sp, #8] 8006100: e9cd 3500 strd r3, r5, [sp] 8006104: 4622 mov r2, r4 8006106: 4633 mov r3, r6 8006108: f000 feaa bl 8006e60 <_dtoa_r> 800610c: 2f47 cmp r7, #71 ; 0x47 800610e: 4680 mov r8, r0 8006110: d102 bne.n 8006118 <__cvt+0x58> 8006112: 9b11 ldr r3, [sp, #68] ; 0x44 8006114: 07db lsls r3, r3, #31 8006116: d526 bpl.n 8006166 <__cvt+0xa6> 8006118: 2f46 cmp r7, #70 ; 0x46 800611a: eb08 0905 add.w r9, r8, r5 800611e: d111 bne.n 8006144 <__cvt+0x84> 8006120: f898 3000 ldrb.w r3, [r8] 8006124: 2b30 cmp r3, #48 ; 0x30 8006126: d10a bne.n 800613e <__cvt+0x7e> 8006128: 2200 movs r2, #0 800612a: 2300 movs r3, #0 800612c: 4620 mov r0, r4 800612e: 4631 mov r1, r6 8006130: f7fa fc9a bl 8000a68 <__aeabi_dcmpeq> 8006134: b918 cbnz r0, 800613e <__cvt+0x7e> 8006136: f1c5 0501 rsb r5, r5, #1 800613a: f8ca 5000 str.w r5, [sl] 800613e: f8da 3000 ldr.w r3, [sl] 8006142: 4499 add r9, r3 8006144: 2200 movs r2, #0 8006146: 2300 movs r3, #0 8006148: 4620 mov r0, r4 800614a: 4631 mov r1, r6 800614c: f7fa fc8c bl 8000a68 <__aeabi_dcmpeq> 8006150: b938 cbnz r0, 8006162 <__cvt+0xa2> 8006152: 2230 movs r2, #48 ; 0x30 8006154: 9b07 ldr r3, [sp, #28] 8006156: 454b cmp r3, r9 8006158: d205 bcs.n 8006166 <__cvt+0xa6> 800615a: 1c59 adds r1, r3, #1 800615c: 9107 str r1, [sp, #28] 800615e: 701a strb r2, [r3, #0] 8006160: e7f8 b.n 8006154 <__cvt+0x94> 8006162: f8cd 901c str.w r9, [sp, #28] 8006166: 4640 mov r0, r8 8006168: 9b07 ldr r3, [sp, #28] 800616a: 9a15 ldr r2, [sp, #84] ; 0x54 800616c: eba3 0308 sub.w r3, r3, r8 8006170: 6013 str r3, [r2, #0] 8006172: b008 add sp, #32 8006174: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 08006178 <__exponent>: 8006178: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} 800617a: 2900 cmp r1, #0 800617c: bfb4 ite lt 800617e: 232d movlt r3, #45 ; 0x2d 8006180: 232b movge r3, #43 ; 0x2b 8006182: 4604 mov r4, r0 8006184: bfb8 it lt 8006186: 4249 neglt r1, r1 8006188: 2909 cmp r1, #9 800618a: f804 2b02 strb.w r2, [r4], #2 800618e: 7043 strb r3, [r0, #1] 8006190: dd21 ble.n 80061d6 <__exponent+0x5e> 8006192: f10d 0307 add.w r3, sp, #7 8006196: 461f mov r7, r3 8006198: 260a movs r6, #10 800619a: fb91 f5f6 sdiv r5, r1, r6 800619e: fb06 1115 mls r1, r6, r5, r1 80061a2: 2d09 cmp r5, #9 80061a4: f101 0130 add.w r1, r1, #48 ; 0x30 80061a8: f803 1c01 strb.w r1, [r3, #-1] 80061ac: f103 32ff add.w r2, r3, #4294967295 80061b0: 4629 mov r1, r5 80061b2: dc09 bgt.n 80061c8 <__exponent+0x50> 80061b4: 3130 adds r1, #48 ; 0x30 80061b6: 3b02 subs r3, #2 80061b8: f802 1c01 strb.w r1, [r2, #-1] 80061bc: 42bb cmp r3, r7 80061be: 4622 mov r2, r4 80061c0: d304 bcc.n 80061cc <__exponent+0x54> 80061c2: 1a10 subs r0, r2, r0 80061c4: b003 add sp, #12 80061c6: bdf0 pop {r4, r5, r6, r7, pc} 80061c8: 4613 mov r3, r2 80061ca: e7e6 b.n 800619a <__exponent+0x22> 80061cc: f813 2b01 ldrb.w r2, [r3], #1 80061d0: f804 2b01 strb.w r2, [r4], #1 80061d4: e7f2 b.n 80061bc <__exponent+0x44> 80061d6: 2330 movs r3, #48 ; 0x30 80061d8: 4419 add r1, r3 80061da: 7083 strb r3, [r0, #2] 80061dc: 1d02 adds r2, r0, #4 80061de: 70c1 strb r1, [r0, #3] 80061e0: e7ef b.n 80061c2 <__exponent+0x4a> ... 080061e4 <_printf_float>: 80061e4: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 80061e8: b091 sub sp, #68 ; 0x44 80061ea: 460c mov r4, r1 80061ec: 9f1a ldr r7, [sp, #104] ; 0x68 80061ee: 4693 mov fp, r2 80061f0: 461e mov r6, r3 80061f2: 4605 mov r5, r0 80061f4: f001 fd62 bl 8007cbc <_localeconv_r> 80061f8: 6803 ldr r3, [r0, #0] 80061fa: 4618 mov r0, r3 80061fc: 9309 str r3, [sp, #36] ; 0x24 80061fe: f7fa f807 bl 8000210 8006202: 2300 movs r3, #0 8006204: 930e str r3, [sp, #56] ; 0x38 8006206: 683b ldr r3, [r7, #0] 8006208: 900a str r0, [sp, #40] ; 0x28 800620a: 3307 adds r3, #7 800620c: f023 0307 bic.w r3, r3, #7 8006210: f103 0208 add.w r2, r3, #8 8006214: f894 8018 ldrb.w r8, [r4, #24] 8006218: f8d4 a000 ldr.w sl, [r4] 800621c: 603a str r2, [r7, #0] 800621e: e9d3 2300 ldrd r2, r3, [r3] 8006222: e9c4 2312 strd r2, r3, [r4, #72] ; 0x48 8006226: e9d4 7912 ldrd r7, r9, [r4, #72] ; 0x48 800622a: f029 4300 bic.w r3, r9, #2147483648 ; 0x80000000 800622e: 930b str r3, [sp, #44] ; 0x2c 8006230: f04f 32ff mov.w r2, #4294967295 8006234: 4ba6 ldr r3, [pc, #664] ; (80064d0 <_printf_float+0x2ec>) 8006236: 4638 mov r0, r7 8006238: 990b ldr r1, [sp, #44] ; 0x2c 800623a: f7fa fc47 bl 8000acc <__aeabi_dcmpun> 800623e: bb68 cbnz r0, 800629c <_printf_float+0xb8> 8006240: f04f 32ff mov.w r2, #4294967295 8006244: 4ba2 ldr r3, [pc, #648] ; (80064d0 <_printf_float+0x2ec>) 8006246: 4638 mov r0, r7 8006248: 990b ldr r1, [sp, #44] ; 0x2c 800624a: f7fa fc21 bl 8000a90 <__aeabi_dcmple> 800624e: bb28 cbnz r0, 800629c <_printf_float+0xb8> 8006250: 2200 movs r2, #0 8006252: 2300 movs r3, #0 8006254: 4638 mov r0, r7 8006256: 4649 mov r1, r9 8006258: f7fa fc10 bl 8000a7c <__aeabi_dcmplt> 800625c: b110 cbz r0, 8006264 <_printf_float+0x80> 800625e: 232d movs r3, #45 ; 0x2d 8006260: f884 3043 strb.w r3, [r4, #67] ; 0x43 8006264: 4f9b ldr r7, [pc, #620] ; (80064d4 <_printf_float+0x2f0>) 8006266: 4b9c ldr r3, [pc, #624] ; (80064d8 <_printf_float+0x2f4>) 8006268: f1b8 0f47 cmp.w r8, #71 ; 0x47 800626c: bf98 it ls 800626e: 461f movls r7, r3 8006270: 2303 movs r3, #3 8006272: f04f 0900 mov.w r9, #0 8006276: 6123 str r3, [r4, #16] 8006278: f02a 0304 bic.w r3, sl, #4 800627c: 6023 str r3, [r4, #0] 800627e: 9600 str r6, [sp, #0] 8006280: 465b mov r3, fp 8006282: aa0f add r2, sp, #60 ; 0x3c 8006284: 4621 mov r1, r4 8006286: 4628 mov r0, r5 8006288: f000 f9e2 bl 8006650 <_printf_common> 800628c: 3001 adds r0, #1 800628e: f040 8090 bne.w 80063b2 <_printf_float+0x1ce> 8006292: f04f 30ff mov.w r0, #4294967295 8006296: b011 add sp, #68 ; 0x44 8006298: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 800629c: 463a mov r2, r7 800629e: 464b mov r3, r9 80062a0: 4638 mov r0, r7 80062a2: 4649 mov r1, r9 80062a4: f7fa fc12 bl 8000acc <__aeabi_dcmpun> 80062a8: b110 cbz r0, 80062b0 <_printf_float+0xcc> 80062aa: 4f8c ldr r7, [pc, #560] ; (80064dc <_printf_float+0x2f8>) 80062ac: 4b8c ldr r3, [pc, #560] ; (80064e0 <_printf_float+0x2fc>) 80062ae: e7db b.n 8006268 <_printf_float+0x84> 80062b0: 6863 ldr r3, [r4, #4] 80062b2: f44a 6280 orr.w r2, sl, #1024 ; 0x400 80062b6: 1c59 adds r1, r3, #1 80062b8: a80d add r0, sp, #52 ; 0x34 80062ba: a90e add r1, sp, #56 ; 0x38 80062bc: d140 bne.n 8006340 <_printf_float+0x15c> 80062be: 2306 movs r3, #6 80062c0: 6063 str r3, [r4, #4] 80062c2: f04f 0c00 mov.w ip, #0 80062c6: f10d 0333 add.w r3, sp, #51 ; 0x33 80062ca: e9cd 2301 strd r2, r3, [sp, #4] 80062ce: 6863 ldr r3, [r4, #4] 80062d0: 6022 str r2, [r4, #0] 80062d2: e9cd 0803 strd r0, r8, [sp, #12] 80062d6: 9300 str r3, [sp, #0] 80062d8: 463a mov r2, r7 80062da: 464b mov r3, r9 80062dc: e9cd 1c05 strd r1, ip, [sp, #20] 80062e0: 4628 mov r0, r5 80062e2: f7ff feed bl 80060c0 <__cvt> 80062e6: f008 03df and.w r3, r8, #223 ; 0xdf 80062ea: 2b47 cmp r3, #71 ; 0x47 80062ec: 4607 mov r7, r0 80062ee: d109 bne.n 8006304 <_printf_float+0x120> 80062f0: 9b0d ldr r3, [sp, #52] ; 0x34 80062f2: 1cd8 adds r0, r3, #3 80062f4: db02 blt.n 80062fc <_printf_float+0x118> 80062f6: 6862 ldr r2, [r4, #4] 80062f8: 4293 cmp r3, r2 80062fa: dd47 ble.n 800638c <_printf_float+0x1a8> 80062fc: f1a8 0802 sub.w r8, r8, #2 8006300: fa5f f888 uxtb.w r8, r8 8006304: f1b8 0f65 cmp.w r8, #101 ; 0x65 8006308: 990d ldr r1, [sp, #52] ; 0x34 800630a: d824 bhi.n 8006356 <_printf_float+0x172> 800630c: 3901 subs r1, #1 800630e: 4642 mov r2, r8 8006310: f104 0050 add.w r0, r4, #80 ; 0x50 8006314: 910d str r1, [sp, #52] ; 0x34 8006316: f7ff ff2f bl 8006178 <__exponent> 800631a: 9a0e ldr r2, [sp, #56] ; 0x38 800631c: 4681 mov r9, r0 800631e: 1813 adds r3, r2, r0 8006320: 2a01 cmp r2, #1 8006322: 6123 str r3, [r4, #16] 8006324: dc02 bgt.n 800632c <_printf_float+0x148> 8006326: 6822 ldr r2, [r4, #0] 8006328: 07d1 lsls r1, r2, #31 800632a: d501 bpl.n 8006330 <_printf_float+0x14c> 800632c: 3301 adds r3, #1 800632e: 6123 str r3, [r4, #16] 8006330: f89d 3033 ldrb.w r3, [sp, #51] ; 0x33 8006334: 2b00 cmp r3, #0 8006336: d0a2 beq.n 800627e <_printf_float+0x9a> 8006338: 232d movs r3, #45 ; 0x2d 800633a: f884 3043 strb.w r3, [r4, #67] ; 0x43 800633e: e79e b.n 800627e <_printf_float+0x9a> 8006340: f1b8 0f67 cmp.w r8, #103 ; 0x67 8006344: f000 816e beq.w 8006624 <_printf_float+0x440> 8006348: f1b8 0f47 cmp.w r8, #71 ; 0x47 800634c: d1b9 bne.n 80062c2 <_printf_float+0xde> 800634e: 2b00 cmp r3, #0 8006350: d1b7 bne.n 80062c2 <_printf_float+0xde> 8006352: 2301 movs r3, #1 8006354: e7b4 b.n 80062c0 <_printf_float+0xdc> 8006356: f1b8 0f66 cmp.w r8, #102 ; 0x66 800635a: d119 bne.n 8006390 <_printf_float+0x1ac> 800635c: 2900 cmp r1, #0 800635e: 6863 ldr r3, [r4, #4] 8006360: dd0c ble.n 800637c <_printf_float+0x198> 8006362: 6121 str r1, [r4, #16] 8006364: b913 cbnz r3, 800636c <_printf_float+0x188> 8006366: 6822 ldr r2, [r4, #0] 8006368: 07d2 lsls r2, r2, #31 800636a: d502 bpl.n 8006372 <_printf_float+0x18e> 800636c: 3301 adds r3, #1 800636e: 440b add r3, r1 8006370: 6123 str r3, [r4, #16] 8006372: 9b0d ldr r3, [sp, #52] ; 0x34 8006374: f04f 0900 mov.w r9, #0 8006378: 65a3 str r3, [r4, #88] ; 0x58 800637a: e7d9 b.n 8006330 <_printf_float+0x14c> 800637c: b913 cbnz r3, 8006384 <_printf_float+0x1a0> 800637e: 6822 ldr r2, [r4, #0] 8006380: 07d0 lsls r0, r2, #31 8006382: d501 bpl.n 8006388 <_printf_float+0x1a4> 8006384: 3302 adds r3, #2 8006386: e7f3 b.n 8006370 <_printf_float+0x18c> 8006388: 2301 movs r3, #1 800638a: e7f1 b.n 8006370 <_printf_float+0x18c> 800638c: f04f 0867 mov.w r8, #103 ; 0x67 8006390: e9dd 320d ldrd r3, r2, [sp, #52] ; 0x34 8006394: 4293 cmp r3, r2 8006396: db05 blt.n 80063a4 <_printf_float+0x1c0> 8006398: 6822 ldr r2, [r4, #0] 800639a: 6123 str r3, [r4, #16] 800639c: 07d1 lsls r1, r2, #31 800639e: d5e8 bpl.n 8006372 <_printf_float+0x18e> 80063a0: 3301 adds r3, #1 80063a2: e7e5 b.n 8006370 <_printf_float+0x18c> 80063a4: 2b00 cmp r3, #0 80063a6: bfcc ite gt 80063a8: 2301 movgt r3, #1 80063aa: f1c3 0302 rsble r3, r3, #2 80063ae: 4413 add r3, r2 80063b0: e7de b.n 8006370 <_printf_float+0x18c> 80063b2: 6823 ldr r3, [r4, #0] 80063b4: 055a lsls r2, r3, #21 80063b6: d407 bmi.n 80063c8 <_printf_float+0x1e4> 80063b8: 6923 ldr r3, [r4, #16] 80063ba: 463a mov r2, r7 80063bc: 4659 mov r1, fp 80063be: 4628 mov r0, r5 80063c0: 47b0 blx r6 80063c2: 3001 adds r0, #1 80063c4: d129 bne.n 800641a <_printf_float+0x236> 80063c6: e764 b.n 8006292 <_printf_float+0xae> 80063c8: f1b8 0f65 cmp.w r8, #101 ; 0x65 80063cc: f240 80d7 bls.w 800657e <_printf_float+0x39a> 80063d0: e9d4 0112 ldrd r0, r1, [r4, #72] ; 0x48 80063d4: 2200 movs r2, #0 80063d6: 2300 movs r3, #0 80063d8: f7fa fb46 bl 8000a68 <__aeabi_dcmpeq> 80063dc: b388 cbz r0, 8006442 <_printf_float+0x25e> 80063de: 2301 movs r3, #1 80063e0: 4a40 ldr r2, [pc, #256] ; (80064e4 <_printf_float+0x300>) 80063e2: 4659 mov r1, fp 80063e4: 4628 mov r0, r5 80063e6: 47b0 blx r6 80063e8: 3001 adds r0, #1 80063ea: f43f af52 beq.w 8006292 <_printf_float+0xae> 80063ee: e9dd 230d ldrd r2, r3, [sp, #52] ; 0x34 80063f2: 429a cmp r2, r3 80063f4: db02 blt.n 80063fc <_printf_float+0x218> 80063f6: 6823 ldr r3, [r4, #0] 80063f8: 07d8 lsls r0, r3, #31 80063fa: d50e bpl.n 800641a <_printf_float+0x236> 80063fc: e9dd 2309 ldrd r2, r3, [sp, #36] ; 0x24 8006400: 4659 mov r1, fp 8006402: 4628 mov r0, r5 8006404: 47b0 blx r6 8006406: 3001 adds r0, #1 8006408: f43f af43 beq.w 8006292 <_printf_float+0xae> 800640c: 2700 movs r7, #0 800640e: f104 081a add.w r8, r4, #26 8006412: 9b0e ldr r3, [sp, #56] ; 0x38 8006414: 3b01 subs r3, #1 8006416: 42bb cmp r3, r7 8006418: dc09 bgt.n 800642e <_printf_float+0x24a> 800641a: 6823 ldr r3, [r4, #0] 800641c: 079f lsls r7, r3, #30 800641e: f100 80fd bmi.w 800661c <_printf_float+0x438> 8006422: 68e0 ldr r0, [r4, #12] 8006424: 9b0f ldr r3, [sp, #60] ; 0x3c 8006426: 4298 cmp r0, r3 8006428: bfb8 it lt 800642a: 4618 movlt r0, r3 800642c: e733 b.n 8006296 <_printf_float+0xb2> 800642e: 2301 movs r3, #1 8006430: 4642 mov r2, r8 8006432: 4659 mov r1, fp 8006434: 4628 mov r0, r5 8006436: 47b0 blx r6 8006438: 3001 adds r0, #1 800643a: f43f af2a beq.w 8006292 <_printf_float+0xae> 800643e: 3701 adds r7, #1 8006440: e7e7 b.n 8006412 <_printf_float+0x22e> 8006442: 9b0d ldr r3, [sp, #52] ; 0x34 8006444: 2b00 cmp r3, #0 8006446: dc2b bgt.n 80064a0 <_printf_float+0x2bc> 8006448: 2301 movs r3, #1 800644a: 4a26 ldr r2, [pc, #152] ; (80064e4 <_printf_float+0x300>) 800644c: 4659 mov r1, fp 800644e: 4628 mov r0, r5 8006450: 47b0 blx r6 8006452: 3001 adds r0, #1 8006454: f43f af1d beq.w 8006292 <_printf_float+0xae> 8006458: 9b0d ldr r3, [sp, #52] ; 0x34 800645a: b923 cbnz r3, 8006466 <_printf_float+0x282> 800645c: 9b0e ldr r3, [sp, #56] ; 0x38 800645e: b913 cbnz r3, 8006466 <_printf_float+0x282> 8006460: 6823 ldr r3, [r4, #0] 8006462: 07d9 lsls r1, r3, #31 8006464: d5d9 bpl.n 800641a <_printf_float+0x236> 8006466: e9dd 2309 ldrd r2, r3, [sp, #36] ; 0x24 800646a: 4659 mov r1, fp 800646c: 4628 mov r0, r5 800646e: 47b0 blx r6 8006470: 3001 adds r0, #1 8006472: f43f af0e beq.w 8006292 <_printf_float+0xae> 8006476: f04f 0800 mov.w r8, #0 800647a: f104 091a add.w r9, r4, #26 800647e: 9b0d ldr r3, [sp, #52] ; 0x34 8006480: 425b negs r3, r3 8006482: 4543 cmp r3, r8 8006484: dc01 bgt.n 800648a <_printf_float+0x2a6> 8006486: 9b0e ldr r3, [sp, #56] ; 0x38 8006488: e797 b.n 80063ba <_printf_float+0x1d6> 800648a: 2301 movs r3, #1 800648c: 464a mov r2, r9 800648e: 4659 mov r1, fp 8006490: 4628 mov r0, r5 8006492: 47b0 blx r6 8006494: 3001 adds r0, #1 8006496: f43f aefc beq.w 8006292 <_printf_float+0xae> 800649a: f108 0801 add.w r8, r8, #1 800649e: e7ee b.n 800647e <_printf_float+0x29a> 80064a0: 9a0e ldr r2, [sp, #56] ; 0x38 80064a2: 6da3 ldr r3, [r4, #88] ; 0x58 80064a4: 429a cmp r2, r3 80064a6: bfa8 it ge 80064a8: 461a movge r2, r3 80064aa: 2a00 cmp r2, #0 80064ac: 4690 mov r8, r2 80064ae: dd07 ble.n 80064c0 <_printf_float+0x2dc> 80064b0: 4613 mov r3, r2 80064b2: 4659 mov r1, fp 80064b4: 463a mov r2, r7 80064b6: 4628 mov r0, r5 80064b8: 47b0 blx r6 80064ba: 3001 adds r0, #1 80064bc: f43f aee9 beq.w 8006292 <_printf_float+0xae> 80064c0: f104 031a add.w r3, r4, #26 80064c4: f04f 0a00 mov.w sl, #0 80064c8: ea28 78e8 bic.w r8, r8, r8, asr #31 80064cc: 930b str r3, [sp, #44] ; 0x2c 80064ce: e015 b.n 80064fc <_printf_float+0x318> 80064d0: 7fefffff .word 0x7fefffff 80064d4: 08008d0c .word 0x08008d0c 80064d8: 08008d08 .word 0x08008d08 80064dc: 08008d14 .word 0x08008d14 80064e0: 08008d10 .word 0x08008d10 80064e4: 08008d18 .word 0x08008d18 80064e8: 2301 movs r3, #1 80064ea: 9a0b ldr r2, [sp, #44] ; 0x2c 80064ec: 4659 mov r1, fp 80064ee: 4628 mov r0, r5 80064f0: 47b0 blx r6 80064f2: 3001 adds r0, #1 80064f4: f43f aecd beq.w 8006292 <_printf_float+0xae> 80064f8: f10a 0a01 add.w sl, sl, #1 80064fc: f8d4 9058 ldr.w r9, [r4, #88] ; 0x58 8006500: eba9 0308 sub.w r3, r9, r8 8006504: 4553 cmp r3, sl 8006506: dcef bgt.n 80064e8 <_printf_float+0x304> 8006508: e9dd 230d ldrd r2, r3, [sp, #52] ; 0x34 800650c: 429a cmp r2, r3 800650e: 444f add r7, r9 8006510: db14 blt.n 800653c <_printf_float+0x358> 8006512: 6823 ldr r3, [r4, #0] 8006514: 07da lsls r2, r3, #31 8006516: d411 bmi.n 800653c <_printf_float+0x358> 8006518: 9b0e ldr r3, [sp, #56] ; 0x38 800651a: 990d ldr r1, [sp, #52] ; 0x34 800651c: eba3 0209 sub.w r2, r3, r9 8006520: eba3 0901 sub.w r9, r3, r1 8006524: 4591 cmp r9, r2 8006526: bfa8 it ge 8006528: 4691 movge r9, r2 800652a: f1b9 0f00 cmp.w r9, #0 800652e: dc0d bgt.n 800654c <_printf_float+0x368> 8006530: 2700 movs r7, #0 8006532: ea29 79e9 bic.w r9, r9, r9, asr #31 8006536: f104 081a add.w r8, r4, #26 800653a: e018 b.n 800656e <_printf_float+0x38a> 800653c: e9dd 2309 ldrd r2, r3, [sp, #36] ; 0x24 8006540: 4659 mov r1, fp 8006542: 4628 mov r0, r5 8006544: 47b0 blx r6 8006546: 3001 adds r0, #1 8006548: d1e6 bne.n 8006518 <_printf_float+0x334> 800654a: e6a2 b.n 8006292 <_printf_float+0xae> 800654c: 464b mov r3, r9 800654e: 463a mov r2, r7 8006550: 4659 mov r1, fp 8006552: 4628 mov r0, r5 8006554: 47b0 blx r6 8006556: 3001 adds r0, #1 8006558: d1ea bne.n 8006530 <_printf_float+0x34c> 800655a: e69a b.n 8006292 <_printf_float+0xae> 800655c: 2301 movs r3, #1 800655e: 4642 mov r2, r8 8006560: 4659 mov r1, fp 8006562: 4628 mov r0, r5 8006564: 47b0 blx r6 8006566: 3001 adds r0, #1 8006568: f43f ae93 beq.w 8006292 <_printf_float+0xae> 800656c: 3701 adds r7, #1 800656e: e9dd 230d ldrd r2, r3, [sp, #52] ; 0x34 8006572: 1a9b subs r3, r3, r2 8006574: eba3 0309 sub.w r3, r3, r9 8006578: 42bb cmp r3, r7 800657a: dcef bgt.n 800655c <_printf_float+0x378> 800657c: e74d b.n 800641a <_printf_float+0x236> 800657e: 9a0e ldr r2, [sp, #56] ; 0x38 8006580: 2a01 cmp r2, #1 8006582: dc01 bgt.n 8006588 <_printf_float+0x3a4> 8006584: 07db lsls r3, r3, #31 8006586: d538 bpl.n 80065fa <_printf_float+0x416> 8006588: 2301 movs r3, #1 800658a: 463a mov r2, r7 800658c: 4659 mov r1, fp 800658e: 4628 mov r0, r5 8006590: 47b0 blx r6 8006592: 3001 adds r0, #1 8006594: f43f ae7d beq.w 8006292 <_printf_float+0xae> 8006598: e9dd 2309 ldrd r2, r3, [sp, #36] ; 0x24 800659c: 4659 mov r1, fp 800659e: 4628 mov r0, r5 80065a0: 47b0 blx r6 80065a2: 3001 adds r0, #1 80065a4: f107 0701 add.w r7, r7, #1 80065a8: f43f ae73 beq.w 8006292 <_printf_float+0xae> 80065ac: e9d4 0112 ldrd r0, r1, [r4, #72] ; 0x48 80065b0: 9b0e ldr r3, [sp, #56] ; 0x38 80065b2: 2200 movs r2, #0 80065b4: f103 38ff add.w r8, r3, #4294967295 80065b8: 2300 movs r3, #0 80065ba: f7fa fa55 bl 8000a68 <__aeabi_dcmpeq> 80065be: b9c0 cbnz r0, 80065f2 <_printf_float+0x40e> 80065c0: 4643 mov r3, r8 80065c2: 463a mov r2, r7 80065c4: 4659 mov r1, fp 80065c6: 4628 mov r0, r5 80065c8: 47b0 blx r6 80065ca: 3001 adds r0, #1 80065cc: d10d bne.n 80065ea <_printf_float+0x406> 80065ce: e660 b.n 8006292 <_printf_float+0xae> 80065d0: 2301 movs r3, #1 80065d2: 4642 mov r2, r8 80065d4: 4659 mov r1, fp 80065d6: 4628 mov r0, r5 80065d8: 47b0 blx r6 80065da: 3001 adds r0, #1 80065dc: f43f ae59 beq.w 8006292 <_printf_float+0xae> 80065e0: 3701 adds r7, #1 80065e2: 9b0e ldr r3, [sp, #56] ; 0x38 80065e4: 3b01 subs r3, #1 80065e6: 42bb cmp r3, r7 80065e8: dcf2 bgt.n 80065d0 <_printf_float+0x3ec> 80065ea: 464b mov r3, r9 80065ec: f104 0250 add.w r2, r4, #80 ; 0x50 80065f0: e6e4 b.n 80063bc <_printf_float+0x1d8> 80065f2: 2700 movs r7, #0 80065f4: f104 081a add.w r8, r4, #26 80065f8: e7f3 b.n 80065e2 <_printf_float+0x3fe> 80065fa: 2301 movs r3, #1 80065fc: e7e1 b.n 80065c2 <_printf_float+0x3de> 80065fe: 2301 movs r3, #1 8006600: 4642 mov r2, r8 8006602: 4659 mov r1, fp 8006604: 4628 mov r0, r5 8006606: 47b0 blx r6 8006608: 3001 adds r0, #1 800660a: f43f ae42 beq.w 8006292 <_printf_float+0xae> 800660e: 3701 adds r7, #1 8006610: 68e3 ldr r3, [r4, #12] 8006612: 9a0f ldr r2, [sp, #60] ; 0x3c 8006614: 1a9b subs r3, r3, r2 8006616: 42bb cmp r3, r7 8006618: dcf1 bgt.n 80065fe <_printf_float+0x41a> 800661a: e702 b.n 8006422 <_printf_float+0x23e> 800661c: 2700 movs r7, #0 800661e: f104 0819 add.w r8, r4, #25 8006622: e7f5 b.n 8006610 <_printf_float+0x42c> 8006624: 2b00 cmp r3, #0 8006626: f43f ae94 beq.w 8006352 <_printf_float+0x16e> 800662a: f04f 0c00 mov.w ip, #0 800662e: e9cd 1c05 strd r1, ip, [sp, #20] 8006632: f10d 0133 add.w r1, sp, #51 ; 0x33 8006636: 6022 str r2, [r4, #0] 8006638: e9cd 0803 strd r0, r8, [sp, #12] 800663c: e9cd 2101 strd r2, r1, [sp, #4] 8006640: 9300 str r3, [sp, #0] 8006642: 463a mov r2, r7 8006644: 464b mov r3, r9 8006646: 4628 mov r0, r5 8006648: f7ff fd3a bl 80060c0 <__cvt> 800664c: 4607 mov r7, r0 800664e: e64f b.n 80062f0 <_printf_float+0x10c> 08006650 <_printf_common>: 8006650: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8006654: 4691 mov r9, r2 8006656: 461f mov r7, r3 8006658: 688a ldr r2, [r1, #8] 800665a: 690b ldr r3, [r1, #16] 800665c: 4606 mov r6, r0 800665e: 4293 cmp r3, r2 8006660: bfb8 it lt 8006662: 4613 movlt r3, r2 8006664: f8c9 3000 str.w r3, [r9] 8006668: f891 2043 ldrb.w r2, [r1, #67] ; 0x43 800666c: 460c mov r4, r1 800666e: f8dd 8020 ldr.w r8, [sp, #32] 8006672: b112 cbz r2, 800667a <_printf_common+0x2a> 8006674: 3301 adds r3, #1 8006676: f8c9 3000 str.w r3, [r9] 800667a: 6823 ldr r3, [r4, #0] 800667c: 0699 lsls r1, r3, #26 800667e: bf42 ittt mi 8006680: f8d9 3000 ldrmi.w r3, [r9] 8006684: 3302 addmi r3, #2 8006686: f8c9 3000 strmi.w r3, [r9] 800668a: 6825 ldr r5, [r4, #0] 800668c: f015 0506 ands.w r5, r5, #6 8006690: d107 bne.n 80066a2 <_printf_common+0x52> 8006692: f104 0a19 add.w sl, r4, #25 8006696: 68e3 ldr r3, [r4, #12] 8006698: f8d9 2000 ldr.w r2, [r9] 800669c: 1a9b subs r3, r3, r2 800669e: 42ab cmp r3, r5 80066a0: dc29 bgt.n 80066f6 <_printf_common+0xa6> 80066a2: f894 3043 ldrb.w r3, [r4, #67] ; 0x43 80066a6: 6822 ldr r2, [r4, #0] 80066a8: 3300 adds r3, #0 80066aa: bf18 it ne 80066ac: 2301 movne r3, #1 80066ae: 0692 lsls r2, r2, #26 80066b0: d42e bmi.n 8006710 <_printf_common+0xc0> 80066b2: f104 0243 add.w r2, r4, #67 ; 0x43 80066b6: 4639 mov r1, r7 80066b8: 4630 mov r0, r6 80066ba: 47c0 blx r8 80066bc: 3001 adds r0, #1 80066be: d021 beq.n 8006704 <_printf_common+0xb4> 80066c0: 6823 ldr r3, [r4, #0] 80066c2: 68e5 ldr r5, [r4, #12] 80066c4: f003 0306 and.w r3, r3, #6 80066c8: 2b04 cmp r3, #4 80066ca: bf18 it ne 80066cc: 2500 movne r5, #0 80066ce: f8d9 2000 ldr.w r2, [r9] 80066d2: f04f 0900 mov.w r9, #0 80066d6: bf08 it eq 80066d8: 1aad subeq r5, r5, r2 80066da: 68a3 ldr r3, [r4, #8] 80066dc: 6922 ldr r2, [r4, #16] 80066de: bf08 it eq 80066e0: ea25 75e5 biceq.w r5, r5, r5, asr #31 80066e4: 4293 cmp r3, r2 80066e6: bfc4 itt gt 80066e8: 1a9b subgt r3, r3, r2 80066ea: 18ed addgt r5, r5, r3 80066ec: 341a adds r4, #26 80066ee: 454d cmp r5, r9 80066f0: d11a bne.n 8006728 <_printf_common+0xd8> 80066f2: 2000 movs r0, #0 80066f4: e008 b.n 8006708 <_printf_common+0xb8> 80066f6: 2301 movs r3, #1 80066f8: 4652 mov r2, sl 80066fa: 4639 mov r1, r7 80066fc: 4630 mov r0, r6 80066fe: 47c0 blx r8 8006700: 3001 adds r0, #1 8006702: d103 bne.n 800670c <_printf_common+0xbc> 8006704: f04f 30ff mov.w r0, #4294967295 8006708: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 800670c: 3501 adds r5, #1 800670e: e7c2 b.n 8006696 <_printf_common+0x46> 8006710: 2030 movs r0, #48 ; 0x30 8006712: 18e1 adds r1, r4, r3 8006714: f881 0043 strb.w r0, [r1, #67] ; 0x43 8006718: 1c5a adds r2, r3, #1 800671a: f894 1045 ldrb.w r1, [r4, #69] ; 0x45 800671e: 4422 add r2, r4 8006720: 3302 adds r3, #2 8006722: f882 1043 strb.w r1, [r2, #67] ; 0x43 8006726: e7c4 b.n 80066b2 <_printf_common+0x62> 8006728: 2301 movs r3, #1 800672a: 4622 mov r2, r4 800672c: 4639 mov r1, r7 800672e: 4630 mov r0, r6 8006730: 47c0 blx r8 8006732: 3001 adds r0, #1 8006734: d0e6 beq.n 8006704 <_printf_common+0xb4> 8006736: f109 0901 add.w r9, r9, #1 800673a: e7d8 b.n 80066ee <_printf_common+0x9e> 0800673c <_printf_i>: 800673c: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} 8006740: f101 0c43 add.w ip, r1, #67 ; 0x43 8006744: 460c mov r4, r1 8006746: 7e09 ldrb r1, [r1, #24] 8006748: b085 sub sp, #20 800674a: 296e cmp r1, #110 ; 0x6e 800674c: 4617 mov r7, r2 800674e: 4606 mov r6, r0 8006750: 4698 mov r8, r3 8006752: 9a0c ldr r2, [sp, #48] ; 0x30 8006754: f000 80b3 beq.w 80068be <_printf_i+0x182> 8006758: d822 bhi.n 80067a0 <_printf_i+0x64> 800675a: 2963 cmp r1, #99 ; 0x63 800675c: d036 beq.n 80067cc <_printf_i+0x90> 800675e: d80a bhi.n 8006776 <_printf_i+0x3a> 8006760: 2900 cmp r1, #0 8006762: f000 80b9 beq.w 80068d8 <_printf_i+0x19c> 8006766: 2958 cmp r1, #88 ; 0x58 8006768: f000 8083 beq.w 8006872 <_printf_i+0x136> 800676c: f104 0542 add.w r5, r4, #66 ; 0x42 8006770: f884 1042 strb.w r1, [r4, #66] ; 0x42 8006774: e032 b.n 80067dc <_printf_i+0xa0> 8006776: 2964 cmp r1, #100 ; 0x64 8006778: d001 beq.n 800677e <_printf_i+0x42> 800677a: 2969 cmp r1, #105 ; 0x69 800677c: d1f6 bne.n 800676c <_printf_i+0x30> 800677e: 6820 ldr r0, [r4, #0] 8006780: 6813 ldr r3, [r2, #0] 8006782: 0605 lsls r5, r0, #24 8006784: f103 0104 add.w r1, r3, #4 8006788: d52a bpl.n 80067e0 <_printf_i+0xa4> 800678a: 681b ldr r3, [r3, #0] 800678c: 6011 str r1, [r2, #0] 800678e: 2b00 cmp r3, #0 8006790: da03 bge.n 800679a <_printf_i+0x5e> 8006792: 222d movs r2, #45 ; 0x2d 8006794: 425b negs r3, r3 8006796: f884 2043 strb.w r2, [r4, #67] ; 0x43 800679a: 486f ldr r0, [pc, #444] ; (8006958 <_printf_i+0x21c>) 800679c: 220a movs r2, #10 800679e: e039 b.n 8006814 <_printf_i+0xd8> 80067a0: 2973 cmp r1, #115 ; 0x73 80067a2: f000 809d beq.w 80068e0 <_printf_i+0x1a4> 80067a6: d808 bhi.n 80067ba <_printf_i+0x7e> 80067a8: 296f cmp r1, #111 ; 0x6f 80067aa: d020 beq.n 80067ee <_printf_i+0xb2> 80067ac: 2970 cmp r1, #112 ; 0x70 80067ae: d1dd bne.n 800676c <_printf_i+0x30> 80067b0: 6823 ldr r3, [r4, #0] 80067b2: f043 0320 orr.w r3, r3, #32 80067b6: 6023 str r3, [r4, #0] 80067b8: e003 b.n 80067c2 <_printf_i+0x86> 80067ba: 2975 cmp r1, #117 ; 0x75 80067bc: d017 beq.n 80067ee <_printf_i+0xb2> 80067be: 2978 cmp r1, #120 ; 0x78 80067c0: d1d4 bne.n 800676c <_printf_i+0x30> 80067c2: 2378 movs r3, #120 ; 0x78 80067c4: 4865 ldr r0, [pc, #404] ; (800695c <_printf_i+0x220>) 80067c6: f884 3045 strb.w r3, [r4, #69] ; 0x45 80067ca: e055 b.n 8006878 <_printf_i+0x13c> 80067cc: 6813 ldr r3, [r2, #0] 80067ce: f104 0542 add.w r5, r4, #66 ; 0x42 80067d2: 1d19 adds r1, r3, #4 80067d4: 681b ldr r3, [r3, #0] 80067d6: 6011 str r1, [r2, #0] 80067d8: f884 3042 strb.w r3, [r4, #66] ; 0x42 80067dc: 2301 movs r3, #1 80067de: e08c b.n 80068fa <_printf_i+0x1be> 80067e0: 681b ldr r3, [r3, #0] 80067e2: f010 0f40 tst.w r0, #64 ; 0x40 80067e6: 6011 str r1, [r2, #0] 80067e8: bf18 it ne 80067ea: b21b sxthne r3, r3 80067ec: e7cf b.n 800678e <_printf_i+0x52> 80067ee: 6813 ldr r3, [r2, #0] 80067f0: 6825 ldr r5, [r4, #0] 80067f2: 1d18 adds r0, r3, #4 80067f4: 6010 str r0, [r2, #0] 80067f6: 0628 lsls r0, r5, #24 80067f8: d501 bpl.n 80067fe <_printf_i+0xc2> 80067fa: 681b ldr r3, [r3, #0] 80067fc: e002 b.n 8006804 <_printf_i+0xc8> 80067fe: 0668 lsls r0, r5, #25 8006800: d5fb bpl.n 80067fa <_printf_i+0xbe> 8006802: 881b ldrh r3, [r3, #0] 8006804: 296f cmp r1, #111 ; 0x6f 8006806: bf14 ite ne 8006808: 220a movne r2, #10 800680a: 2208 moveq r2, #8 800680c: 4852 ldr r0, [pc, #328] ; (8006958 <_printf_i+0x21c>) 800680e: 2100 movs r1, #0 8006810: f884 1043 strb.w r1, [r4, #67] ; 0x43 8006814: 6865 ldr r5, [r4, #4] 8006816: 2d00 cmp r5, #0 8006818: 60a5 str r5, [r4, #8] 800681a: f2c0 8095 blt.w 8006948 <_printf_i+0x20c> 800681e: 6821 ldr r1, [r4, #0] 8006820: f021 0104 bic.w r1, r1, #4 8006824: 6021 str r1, [r4, #0] 8006826: 2b00 cmp r3, #0 8006828: d13d bne.n 80068a6 <_printf_i+0x16a> 800682a: 2d00 cmp r5, #0 800682c: f040 808e bne.w 800694c <_printf_i+0x210> 8006830: 4665 mov r5, ip 8006832: 2a08 cmp r2, #8 8006834: d10b bne.n 800684e <_printf_i+0x112> 8006836: 6823 ldr r3, [r4, #0] 8006838: 07db lsls r3, r3, #31 800683a: d508 bpl.n 800684e <_printf_i+0x112> 800683c: 6923 ldr r3, [r4, #16] 800683e: 6862 ldr r2, [r4, #4] 8006840: 429a cmp r2, r3 8006842: bfde ittt le 8006844: 2330 movle r3, #48 ; 0x30 8006846: f805 3c01 strble.w r3, [r5, #-1] 800684a: f105 35ff addle.w r5, r5, #4294967295 800684e: ebac 0305 sub.w r3, ip, r5 8006852: 6123 str r3, [r4, #16] 8006854: f8cd 8000 str.w r8, [sp] 8006858: 463b mov r3, r7 800685a: aa03 add r2, sp, #12 800685c: 4621 mov r1, r4 800685e: 4630 mov r0, r6 8006860: f7ff fef6 bl 8006650 <_printf_common> 8006864: 3001 adds r0, #1 8006866: d14d bne.n 8006904 <_printf_i+0x1c8> 8006868: f04f 30ff mov.w r0, #4294967295 800686c: b005 add sp, #20 800686e: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} 8006872: 4839 ldr r0, [pc, #228] ; (8006958 <_printf_i+0x21c>) 8006874: f884 1045 strb.w r1, [r4, #69] ; 0x45 8006878: 6813 ldr r3, [r2, #0] 800687a: 6821 ldr r1, [r4, #0] 800687c: 1d1d adds r5, r3, #4 800687e: 681b ldr r3, [r3, #0] 8006880: 6015 str r5, [r2, #0] 8006882: 060a lsls r2, r1, #24 8006884: d50b bpl.n 800689e <_printf_i+0x162> 8006886: 07ca lsls r2, r1, #31 8006888: bf44 itt mi 800688a: f041 0120 orrmi.w r1, r1, #32 800688e: 6021 strmi r1, [r4, #0] 8006890: b91b cbnz r3, 800689a <_printf_i+0x15e> 8006892: 6822 ldr r2, [r4, #0] 8006894: f022 0220 bic.w r2, r2, #32 8006898: 6022 str r2, [r4, #0] 800689a: 2210 movs r2, #16 800689c: e7b7 b.n 800680e <_printf_i+0xd2> 800689e: 064d lsls r5, r1, #25 80068a0: bf48 it mi 80068a2: b29b uxthmi r3, r3 80068a4: e7ef b.n 8006886 <_printf_i+0x14a> 80068a6: 4665 mov r5, ip 80068a8: fbb3 f1f2 udiv r1, r3, r2 80068ac: fb02 3311 mls r3, r2, r1, r3 80068b0: 5cc3 ldrb r3, [r0, r3] 80068b2: f805 3d01 strb.w r3, [r5, #-1]! 80068b6: 460b mov r3, r1 80068b8: 2900 cmp r1, #0 80068ba: d1f5 bne.n 80068a8 <_printf_i+0x16c> 80068bc: e7b9 b.n 8006832 <_printf_i+0xf6> 80068be: 6813 ldr r3, [r2, #0] 80068c0: 6825 ldr r5, [r4, #0] 80068c2: 1d18 adds r0, r3, #4 80068c4: 6961 ldr r1, [r4, #20] 80068c6: 6010 str r0, [r2, #0] 80068c8: 0628 lsls r0, r5, #24 80068ca: 681b ldr r3, [r3, #0] 80068cc: d501 bpl.n 80068d2 <_printf_i+0x196> 80068ce: 6019 str r1, [r3, #0] 80068d0: e002 b.n 80068d8 <_printf_i+0x19c> 80068d2: 066a lsls r2, r5, #25 80068d4: d5fb bpl.n 80068ce <_printf_i+0x192> 80068d6: 8019 strh r1, [r3, #0] 80068d8: 2300 movs r3, #0 80068da: 4665 mov r5, ip 80068dc: 6123 str r3, [r4, #16] 80068de: e7b9 b.n 8006854 <_printf_i+0x118> 80068e0: 6813 ldr r3, [r2, #0] 80068e2: 1d19 adds r1, r3, #4 80068e4: 6011 str r1, [r2, #0] 80068e6: 681d ldr r5, [r3, #0] 80068e8: 6862 ldr r2, [r4, #4] 80068ea: 2100 movs r1, #0 80068ec: 4628 mov r0, r5 80068ee: f001 fa5f bl 8007db0 80068f2: b108 cbz r0, 80068f8 <_printf_i+0x1bc> 80068f4: 1b40 subs r0, r0, r5 80068f6: 6060 str r0, [r4, #4] 80068f8: 6863 ldr r3, [r4, #4] 80068fa: 6123 str r3, [r4, #16] 80068fc: 2300 movs r3, #0 80068fe: f884 3043 strb.w r3, [r4, #67] ; 0x43 8006902: e7a7 b.n 8006854 <_printf_i+0x118> 8006904: 6923 ldr r3, [r4, #16] 8006906: 462a mov r2, r5 8006908: 4639 mov r1, r7 800690a: 4630 mov r0, r6 800690c: 47c0 blx r8 800690e: 3001 adds r0, #1 8006910: d0aa beq.n 8006868 <_printf_i+0x12c> 8006912: 6823 ldr r3, [r4, #0] 8006914: 079b lsls r3, r3, #30 8006916: d413 bmi.n 8006940 <_printf_i+0x204> 8006918: 68e0 ldr r0, [r4, #12] 800691a: 9b03 ldr r3, [sp, #12] 800691c: 4298 cmp r0, r3 800691e: bfb8 it lt 8006920: 4618 movlt r0, r3 8006922: e7a3 b.n 800686c <_printf_i+0x130> 8006924: 2301 movs r3, #1 8006926: 464a mov r2, r9 8006928: 4639 mov r1, r7 800692a: 4630 mov r0, r6 800692c: 47c0 blx r8 800692e: 3001 adds r0, #1 8006930: d09a beq.n 8006868 <_printf_i+0x12c> 8006932: 3501 adds r5, #1 8006934: 68e3 ldr r3, [r4, #12] 8006936: 9a03 ldr r2, [sp, #12] 8006938: 1a9b subs r3, r3, r2 800693a: 42ab cmp r3, r5 800693c: dcf2 bgt.n 8006924 <_printf_i+0x1e8> 800693e: e7eb b.n 8006918 <_printf_i+0x1dc> 8006940: 2500 movs r5, #0 8006942: f104 0919 add.w r9, r4, #25 8006946: e7f5 b.n 8006934 <_printf_i+0x1f8> 8006948: 2b00 cmp r3, #0 800694a: d1ac bne.n 80068a6 <_printf_i+0x16a> 800694c: 7803 ldrb r3, [r0, #0] 800694e: f104 0542 add.w r5, r4, #66 ; 0x42 8006952: f884 3042 strb.w r3, [r4, #66] ; 0x42 8006956: e76c b.n 8006832 <_printf_i+0xf6> 8006958: 08008d1a .word 0x08008d1a 800695c: 08008d2b .word 0x08008d2b 08006960 : 8006960: b40f push {r0, r1, r2, r3} 8006962: 4b0a ldr r3, [pc, #40] ; (800698c ) 8006964: b513 push {r0, r1, r4, lr} 8006966: 681c ldr r4, [r3, #0] 8006968: b124 cbz r4, 8006974 800696a: 69a3 ldr r3, [r4, #24] 800696c: b913 cbnz r3, 8006974 800696e: 4620 mov r0, r4 8006970: f001 f91a bl 8007ba8 <__sinit> 8006974: ab05 add r3, sp, #20 8006976: 9a04 ldr r2, [sp, #16] 8006978: 68a1 ldr r1, [r4, #8] 800697a: 4620 mov r0, r4 800697c: 9301 str r3, [sp, #4] 800697e: f001 fde9 bl 8008554 <_vfiprintf_r> 8006982: b002 add sp, #8 8006984: e8bd 4010 ldmia.w sp!, {r4, lr} 8006988: b004 add sp, #16 800698a: 4770 bx lr 800698c: 2000000c .word 0x2000000c 08006990 <_puts_r>: 8006990: b570 push {r4, r5, r6, lr} 8006992: 460e mov r6, r1 8006994: 4605 mov r5, r0 8006996: b118 cbz r0, 80069a0 <_puts_r+0x10> 8006998: 6983 ldr r3, [r0, #24] 800699a: b90b cbnz r3, 80069a0 <_puts_r+0x10> 800699c: f001 f904 bl 8007ba8 <__sinit> 80069a0: 69ab ldr r3, [r5, #24] 80069a2: 68ac ldr r4, [r5, #8] 80069a4: b913 cbnz r3, 80069ac <_puts_r+0x1c> 80069a6: 4628 mov r0, r5 80069a8: f001 f8fe bl 8007ba8 <__sinit> 80069ac: 4b23 ldr r3, [pc, #140] ; (8006a3c <_puts_r+0xac>) 80069ae: 429c cmp r4, r3 80069b0: d117 bne.n 80069e2 <_puts_r+0x52> 80069b2: 686c ldr r4, [r5, #4] 80069b4: 89a3 ldrh r3, [r4, #12] 80069b6: 071b lsls r3, r3, #28 80069b8: d51d bpl.n 80069f6 <_puts_r+0x66> 80069ba: 6923 ldr r3, [r4, #16] 80069bc: b1db cbz r3, 80069f6 <_puts_r+0x66> 80069be: 3e01 subs r6, #1 80069c0: 68a3 ldr r3, [r4, #8] 80069c2: f816 1f01 ldrb.w r1, [r6, #1]! 80069c6: 3b01 subs r3, #1 80069c8: 60a3 str r3, [r4, #8] 80069ca: b9e9 cbnz r1, 8006a08 <_puts_r+0x78> 80069cc: 2b00 cmp r3, #0 80069ce: da2e bge.n 8006a2e <_puts_r+0x9e> 80069d0: 4622 mov r2, r4 80069d2: 210a movs r1, #10 80069d4: 4628 mov r0, r5 80069d6: f000 f8f5 bl 8006bc4 <__swbuf_r> 80069da: 3001 adds r0, #1 80069dc: d011 beq.n 8006a02 <_puts_r+0x72> 80069de: 200a movs r0, #10 80069e0: e011 b.n 8006a06 <_puts_r+0x76> 80069e2: 4b17 ldr r3, [pc, #92] ; (8006a40 <_puts_r+0xb0>) 80069e4: 429c cmp r4, r3 80069e6: d101 bne.n 80069ec <_puts_r+0x5c> 80069e8: 68ac ldr r4, [r5, #8] 80069ea: e7e3 b.n 80069b4 <_puts_r+0x24> 80069ec: 4b15 ldr r3, [pc, #84] ; (8006a44 <_puts_r+0xb4>) 80069ee: 429c cmp r4, r3 80069f0: bf08 it eq 80069f2: 68ec ldreq r4, [r5, #12] 80069f4: e7de b.n 80069b4 <_puts_r+0x24> 80069f6: 4621 mov r1, r4 80069f8: 4628 mov r0, r5 80069fa: f000 f935 bl 8006c68 <__swsetup_r> 80069fe: 2800 cmp r0, #0 8006a00: d0dd beq.n 80069be <_puts_r+0x2e> 8006a02: f04f 30ff mov.w r0, #4294967295 8006a06: bd70 pop {r4, r5, r6, pc} 8006a08: 2b00 cmp r3, #0 8006a0a: da04 bge.n 8006a16 <_puts_r+0x86> 8006a0c: 69a2 ldr r2, [r4, #24] 8006a0e: 429a cmp r2, r3 8006a10: dc06 bgt.n 8006a20 <_puts_r+0x90> 8006a12: 290a cmp r1, #10 8006a14: d004 beq.n 8006a20 <_puts_r+0x90> 8006a16: 6823 ldr r3, [r4, #0] 8006a18: 1c5a adds r2, r3, #1 8006a1a: 6022 str r2, [r4, #0] 8006a1c: 7019 strb r1, [r3, #0] 8006a1e: e7cf b.n 80069c0 <_puts_r+0x30> 8006a20: 4622 mov r2, r4 8006a22: 4628 mov r0, r5 8006a24: f000 f8ce bl 8006bc4 <__swbuf_r> 8006a28: 3001 adds r0, #1 8006a2a: d1c9 bne.n 80069c0 <_puts_r+0x30> 8006a2c: e7e9 b.n 8006a02 <_puts_r+0x72> 8006a2e: 200a movs r0, #10 8006a30: 6823 ldr r3, [r4, #0] 8006a32: 1c5a adds r2, r3, #1 8006a34: 6022 str r2, [r4, #0] 8006a36: 7018 strb r0, [r3, #0] 8006a38: e7e5 b.n 8006a06 <_puts_r+0x76> 8006a3a: bf00 nop 8006a3c: 08008d6c .word 0x08008d6c 8006a40: 08008d8c .word 0x08008d8c 8006a44: 08008d4c .word 0x08008d4c 08006a48 : 8006a48: 4b02 ldr r3, [pc, #8] ; (8006a54 ) 8006a4a: 4601 mov r1, r0 8006a4c: 6818 ldr r0, [r3, #0] 8006a4e: f7ff bf9f b.w 8006990 <_puts_r> 8006a52: bf00 nop 8006a54: 2000000c .word 0x2000000c 08006a58 : 8006a58: 2900 cmp r1, #0 8006a5a: f44f 6380 mov.w r3, #1024 ; 0x400 8006a5e: bf0c ite eq 8006a60: 2202 moveq r2, #2 8006a62: 2200 movne r2, #0 8006a64: f000 b800 b.w 8006a68 08006a68 : 8006a68: e92d 43f7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr} 8006a6c: 461d mov r5, r3 8006a6e: 4b51 ldr r3, [pc, #324] ; (8006bb4 ) 8006a70: 4604 mov r4, r0 8006a72: 681e ldr r6, [r3, #0] 8006a74: 460f mov r7, r1 8006a76: 4690 mov r8, r2 8006a78: b126 cbz r6, 8006a84 8006a7a: 69b3 ldr r3, [r6, #24] 8006a7c: b913 cbnz r3, 8006a84 8006a7e: 4630 mov r0, r6 8006a80: f001 f892 bl 8007ba8 <__sinit> 8006a84: 4b4c ldr r3, [pc, #304] ; (8006bb8 ) 8006a86: 429c cmp r4, r3 8006a88: d152 bne.n 8006b30 8006a8a: 6874 ldr r4, [r6, #4] 8006a8c: f1b8 0f02 cmp.w r8, #2 8006a90: d006 beq.n 8006aa0 8006a92: f1b8 0f01 cmp.w r8, #1 8006a96: f200 8089 bhi.w 8006bac 8006a9a: 2d00 cmp r5, #0 8006a9c: f2c0 8086 blt.w 8006bac 8006aa0: 4621 mov r1, r4 8006aa2: 4630 mov r0, r6 8006aa4: f001 f816 bl 8007ad4 <_fflush_r> 8006aa8: 6b61 ldr r1, [r4, #52] ; 0x34 8006aaa: b141 cbz r1, 8006abe 8006aac: f104 0344 add.w r3, r4, #68 ; 0x44 8006ab0: 4299 cmp r1, r3 8006ab2: d002 beq.n 8006aba 8006ab4: 4630 mov r0, r6 8006ab6: f001 fc7f bl 80083b8 <_free_r> 8006aba: 2300 movs r3, #0 8006abc: 6363 str r3, [r4, #52] ; 0x34 8006abe: 2300 movs r3, #0 8006ac0: 61a3 str r3, [r4, #24] 8006ac2: 6063 str r3, [r4, #4] 8006ac4: 89a3 ldrh r3, [r4, #12] 8006ac6: 061b lsls r3, r3, #24 8006ac8: d503 bpl.n 8006ad2 8006aca: 6921 ldr r1, [r4, #16] 8006acc: 4630 mov r0, r6 8006ace: f001 fc73 bl 80083b8 <_free_r> 8006ad2: 89a3 ldrh r3, [r4, #12] 8006ad4: f1b8 0f02 cmp.w r8, #2 8006ad8: f423 634a bic.w r3, r3, #3232 ; 0xca0 8006adc: f023 0303 bic.w r3, r3, #3 8006ae0: 81a3 strh r3, [r4, #12] 8006ae2: d05d beq.n 8006ba0 8006ae4: ab01 add r3, sp, #4 8006ae6: 466a mov r2, sp 8006ae8: 4621 mov r1, r4 8006aea: 4630 mov r0, r6 8006aec: f001 f8f4 bl 8007cd8 <__swhatbuf_r> 8006af0: 89a3 ldrh r3, [r4, #12] 8006af2: 4318 orrs r0, r3 8006af4: 81a0 strh r0, [r4, #12] 8006af6: bb2d cbnz r5, 8006b44 8006af8: 9d00 ldr r5, [sp, #0] 8006afa: 4628 mov r0, r5 8006afc: f001 f950 bl 8007da0 8006b00: 4607 mov r7, r0 8006b02: 2800 cmp r0, #0 8006b04: d14e bne.n 8006ba4 8006b06: f8dd 9000 ldr.w r9, [sp] 8006b0a: 45a9 cmp r9, r5 8006b0c: d13c bne.n 8006b88 8006b0e: f04f 30ff mov.w r0, #4294967295 8006b12: 89a3 ldrh r3, [r4, #12] 8006b14: f043 0302 orr.w r3, r3, #2 8006b18: 81a3 strh r3, [r4, #12] 8006b1a: 2300 movs r3, #0 8006b1c: 60a3 str r3, [r4, #8] 8006b1e: f104 0347 add.w r3, r4, #71 ; 0x47 8006b22: 6023 str r3, [r4, #0] 8006b24: 6123 str r3, [r4, #16] 8006b26: 2301 movs r3, #1 8006b28: 6163 str r3, [r4, #20] 8006b2a: b003 add sp, #12 8006b2c: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} 8006b30: 4b22 ldr r3, [pc, #136] ; (8006bbc ) 8006b32: 429c cmp r4, r3 8006b34: d101 bne.n 8006b3a 8006b36: 68b4 ldr r4, [r6, #8] 8006b38: e7a8 b.n 8006a8c 8006b3a: 4b21 ldr r3, [pc, #132] ; (8006bc0 ) 8006b3c: 429c cmp r4, r3 8006b3e: bf08 it eq 8006b40: 68f4 ldreq r4, [r6, #12] 8006b42: e7a3 b.n 8006a8c 8006b44: 2f00 cmp r7, #0 8006b46: d0d8 beq.n 8006afa 8006b48: 69b3 ldr r3, [r6, #24] 8006b4a: b913 cbnz r3, 8006b52 8006b4c: 4630 mov r0, r6 8006b4e: f001 f82b bl 8007ba8 <__sinit> 8006b52: f1b8 0f01 cmp.w r8, #1 8006b56: bf08 it eq 8006b58: 89a3 ldrheq r3, [r4, #12] 8006b5a: 6027 str r7, [r4, #0] 8006b5c: bf04 itt eq 8006b5e: f043 0301 orreq.w r3, r3, #1 8006b62: 81a3 strheq r3, [r4, #12] 8006b64: 89a3 ldrh r3, [r4, #12] 8006b66: e9c4 7504 strd r7, r5, [r4, #16] 8006b6a: f013 0008 ands.w r0, r3, #8 8006b6e: d01b beq.n 8006ba8 8006b70: f013 0001 ands.w r0, r3, #1 8006b74: f04f 0300 mov.w r3, #0 8006b78: bf1f itttt ne 8006b7a: 426d negne r5, r5 8006b7c: 60a3 strne r3, [r4, #8] 8006b7e: 61a5 strne r5, [r4, #24] 8006b80: 4618 movne r0, r3 8006b82: bf08 it eq 8006b84: 60a5 streq r5, [r4, #8] 8006b86: e7d0 b.n 8006b2a 8006b88: 4648 mov r0, r9 8006b8a: f001 f909 bl 8007da0 8006b8e: 4607 mov r7, r0 8006b90: 2800 cmp r0, #0 8006b92: d0bc beq.n 8006b0e 8006b94: 89a3 ldrh r3, [r4, #12] 8006b96: 464d mov r5, r9 8006b98: f043 0380 orr.w r3, r3, #128 ; 0x80 8006b9c: 81a3 strh r3, [r4, #12] 8006b9e: e7d3 b.n 8006b48 8006ba0: 2000 movs r0, #0 8006ba2: e7b6 b.n 8006b12 8006ba4: 46a9 mov r9, r5 8006ba6: e7f5 b.n 8006b94 8006ba8: 60a0 str r0, [r4, #8] 8006baa: e7be b.n 8006b2a 8006bac: f04f 30ff mov.w r0, #4294967295 8006bb0: e7bb b.n 8006b2a 8006bb2: bf00 nop 8006bb4: 2000000c .word 0x2000000c 8006bb8: 08008d6c .word 0x08008d6c 8006bbc: 08008d8c .word 0x08008d8c 8006bc0: 08008d4c .word 0x08008d4c 08006bc4 <__swbuf_r>: 8006bc4: b5f8 push {r3, r4, r5, r6, r7, lr} 8006bc6: 460e mov r6, r1 8006bc8: 4614 mov r4, r2 8006bca: 4605 mov r5, r0 8006bcc: b118 cbz r0, 8006bd6 <__swbuf_r+0x12> 8006bce: 6983 ldr r3, [r0, #24] 8006bd0: b90b cbnz r3, 8006bd6 <__swbuf_r+0x12> 8006bd2: f000 ffe9 bl 8007ba8 <__sinit> 8006bd6: 4b21 ldr r3, [pc, #132] ; (8006c5c <__swbuf_r+0x98>) 8006bd8: 429c cmp r4, r3 8006bda: d12a bne.n 8006c32 <__swbuf_r+0x6e> 8006bdc: 686c ldr r4, [r5, #4] 8006bde: 69a3 ldr r3, [r4, #24] 8006be0: 60a3 str r3, [r4, #8] 8006be2: 89a3 ldrh r3, [r4, #12] 8006be4: 071a lsls r2, r3, #28 8006be6: d52e bpl.n 8006c46 <__swbuf_r+0x82> 8006be8: 6923 ldr r3, [r4, #16] 8006bea: b363 cbz r3, 8006c46 <__swbuf_r+0x82> 8006bec: 6923 ldr r3, [r4, #16] 8006bee: 6820 ldr r0, [r4, #0] 8006bf0: b2f6 uxtb r6, r6 8006bf2: 1ac0 subs r0, r0, r3 8006bf4: 6963 ldr r3, [r4, #20] 8006bf6: 4637 mov r7, r6 8006bf8: 4283 cmp r3, r0 8006bfa: dc04 bgt.n 8006c06 <__swbuf_r+0x42> 8006bfc: 4621 mov r1, r4 8006bfe: 4628 mov r0, r5 8006c00: f000 ff68 bl 8007ad4 <_fflush_r> 8006c04: bb28 cbnz r0, 8006c52 <__swbuf_r+0x8e> 8006c06: 68a3 ldr r3, [r4, #8] 8006c08: 3001 adds r0, #1 8006c0a: 3b01 subs r3, #1 8006c0c: 60a3 str r3, [r4, #8] 8006c0e: 6823 ldr r3, [r4, #0] 8006c10: 1c5a adds r2, r3, #1 8006c12: 6022 str r2, [r4, #0] 8006c14: 701e strb r6, [r3, #0] 8006c16: 6963 ldr r3, [r4, #20] 8006c18: 4283 cmp r3, r0 8006c1a: d004 beq.n 8006c26 <__swbuf_r+0x62> 8006c1c: 89a3 ldrh r3, [r4, #12] 8006c1e: 07db lsls r3, r3, #31 8006c20: d519 bpl.n 8006c56 <__swbuf_r+0x92> 8006c22: 2e0a cmp r6, #10 8006c24: d117 bne.n 8006c56 <__swbuf_r+0x92> 8006c26: 4621 mov r1, r4 8006c28: 4628 mov r0, r5 8006c2a: f000 ff53 bl 8007ad4 <_fflush_r> 8006c2e: b190 cbz r0, 8006c56 <__swbuf_r+0x92> 8006c30: e00f b.n 8006c52 <__swbuf_r+0x8e> 8006c32: 4b0b ldr r3, [pc, #44] ; (8006c60 <__swbuf_r+0x9c>) 8006c34: 429c cmp r4, r3 8006c36: d101 bne.n 8006c3c <__swbuf_r+0x78> 8006c38: 68ac ldr r4, [r5, #8] 8006c3a: e7d0 b.n 8006bde <__swbuf_r+0x1a> 8006c3c: 4b09 ldr r3, [pc, #36] ; (8006c64 <__swbuf_r+0xa0>) 8006c3e: 429c cmp r4, r3 8006c40: bf08 it eq 8006c42: 68ec ldreq r4, [r5, #12] 8006c44: e7cb b.n 8006bde <__swbuf_r+0x1a> 8006c46: 4621 mov r1, r4 8006c48: 4628 mov r0, r5 8006c4a: f000 f80d bl 8006c68 <__swsetup_r> 8006c4e: 2800 cmp r0, #0 8006c50: d0cc beq.n 8006bec <__swbuf_r+0x28> 8006c52: f04f 37ff mov.w r7, #4294967295 8006c56: 4638 mov r0, r7 8006c58: bdf8 pop {r3, r4, r5, r6, r7, pc} 8006c5a: bf00 nop 8006c5c: 08008d6c .word 0x08008d6c 8006c60: 08008d8c .word 0x08008d8c 8006c64: 08008d4c .word 0x08008d4c 08006c68 <__swsetup_r>: 8006c68: 4b32 ldr r3, [pc, #200] ; (8006d34 <__swsetup_r+0xcc>) 8006c6a: b570 push {r4, r5, r6, lr} 8006c6c: 681d ldr r5, [r3, #0] 8006c6e: 4606 mov r6, r0 8006c70: 460c mov r4, r1 8006c72: b125 cbz r5, 8006c7e <__swsetup_r+0x16> 8006c74: 69ab ldr r3, [r5, #24] 8006c76: b913 cbnz r3, 8006c7e <__swsetup_r+0x16> 8006c78: 4628 mov r0, r5 8006c7a: f000 ff95 bl 8007ba8 <__sinit> 8006c7e: 4b2e ldr r3, [pc, #184] ; (8006d38 <__swsetup_r+0xd0>) 8006c80: 429c cmp r4, r3 8006c82: d10f bne.n 8006ca4 <__swsetup_r+0x3c> 8006c84: 686c ldr r4, [r5, #4] 8006c86: f9b4 300c ldrsh.w r3, [r4, #12] 8006c8a: b29a uxth r2, r3 8006c8c: 0715 lsls r5, r2, #28 8006c8e: d42c bmi.n 8006cea <__swsetup_r+0x82> 8006c90: 06d0 lsls r0, r2, #27 8006c92: d411 bmi.n 8006cb8 <__swsetup_r+0x50> 8006c94: 2209 movs r2, #9 8006c96: 6032 str r2, [r6, #0] 8006c98: f043 0340 orr.w r3, r3, #64 ; 0x40 8006c9c: 81a3 strh r3, [r4, #12] 8006c9e: f04f 30ff mov.w r0, #4294967295 8006ca2: e03e b.n 8006d22 <__swsetup_r+0xba> 8006ca4: 4b25 ldr r3, [pc, #148] ; (8006d3c <__swsetup_r+0xd4>) 8006ca6: 429c cmp r4, r3 8006ca8: d101 bne.n 8006cae <__swsetup_r+0x46> 8006caa: 68ac ldr r4, [r5, #8] 8006cac: e7eb b.n 8006c86 <__swsetup_r+0x1e> 8006cae: 4b24 ldr r3, [pc, #144] ; (8006d40 <__swsetup_r+0xd8>) 8006cb0: 429c cmp r4, r3 8006cb2: bf08 it eq 8006cb4: 68ec ldreq r4, [r5, #12] 8006cb6: e7e6 b.n 8006c86 <__swsetup_r+0x1e> 8006cb8: 0751 lsls r1, r2, #29 8006cba: d512 bpl.n 8006ce2 <__swsetup_r+0x7a> 8006cbc: 6b61 ldr r1, [r4, #52] ; 0x34 8006cbe: b141 cbz r1, 8006cd2 <__swsetup_r+0x6a> 8006cc0: f104 0344 add.w r3, r4, #68 ; 0x44 8006cc4: 4299 cmp r1, r3 8006cc6: d002 beq.n 8006cce <__swsetup_r+0x66> 8006cc8: 4630 mov r0, r6 8006cca: f001 fb75 bl 80083b8 <_free_r> 8006cce: 2300 movs r3, #0 8006cd0: 6363 str r3, [r4, #52] ; 0x34 8006cd2: 89a3 ldrh r3, [r4, #12] 8006cd4: f023 0324 bic.w r3, r3, #36 ; 0x24 8006cd8: 81a3 strh r3, [r4, #12] 8006cda: 2300 movs r3, #0 8006cdc: 6063 str r3, [r4, #4] 8006cde: 6923 ldr r3, [r4, #16] 8006ce0: 6023 str r3, [r4, #0] 8006ce2: 89a3 ldrh r3, [r4, #12] 8006ce4: f043 0308 orr.w r3, r3, #8 8006ce8: 81a3 strh r3, [r4, #12] 8006cea: 6923 ldr r3, [r4, #16] 8006cec: b94b cbnz r3, 8006d02 <__swsetup_r+0x9a> 8006cee: 89a3 ldrh r3, [r4, #12] 8006cf0: f403 7320 and.w r3, r3, #640 ; 0x280 8006cf4: f5b3 7f00 cmp.w r3, #512 ; 0x200 8006cf8: d003 beq.n 8006d02 <__swsetup_r+0x9a> 8006cfa: 4621 mov r1, r4 8006cfc: 4630 mov r0, r6 8006cfe: f001 f80f bl 8007d20 <__smakebuf_r> 8006d02: 89a2 ldrh r2, [r4, #12] 8006d04: f012 0301 ands.w r3, r2, #1 8006d08: d00c beq.n 8006d24 <__swsetup_r+0xbc> 8006d0a: 2300 movs r3, #0 8006d0c: 60a3 str r3, [r4, #8] 8006d0e: 6963 ldr r3, [r4, #20] 8006d10: 425b negs r3, r3 8006d12: 61a3 str r3, [r4, #24] 8006d14: 6923 ldr r3, [r4, #16] 8006d16: b953 cbnz r3, 8006d2e <__swsetup_r+0xc6> 8006d18: f9b4 300c ldrsh.w r3, [r4, #12] 8006d1c: f013 0080 ands.w r0, r3, #128 ; 0x80 8006d20: d1ba bne.n 8006c98 <__swsetup_r+0x30> 8006d22: bd70 pop {r4, r5, r6, pc} 8006d24: 0792 lsls r2, r2, #30 8006d26: bf58 it pl 8006d28: 6963 ldrpl r3, [r4, #20] 8006d2a: 60a3 str r3, [r4, #8] 8006d2c: e7f2 b.n 8006d14 <__swsetup_r+0xac> 8006d2e: 2000 movs r0, #0 8006d30: e7f7 b.n 8006d22 <__swsetup_r+0xba> 8006d32: bf00 nop 8006d34: 2000000c .word 0x2000000c 8006d38: 08008d6c .word 0x08008d6c 8006d3c: 08008d8c .word 0x08008d8c 8006d40: 08008d4c .word 0x08008d4c 08006d44 : 8006d44: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} 8006d48: 6903 ldr r3, [r0, #16] 8006d4a: 690c ldr r4, [r1, #16] 8006d4c: 4680 mov r8, r0 8006d4e: 42a3 cmp r3, r4 8006d50: f2c0 8084 blt.w 8006e5c 8006d54: 3c01 subs r4, #1 8006d56: f101 0714 add.w r7, r1, #20 8006d5a: f100 0614 add.w r6, r0, #20 8006d5e: f857 5024 ldr.w r5, [r7, r4, lsl #2] 8006d62: f856 0024 ldr.w r0, [r6, r4, lsl #2] 8006d66: 3501 adds r5, #1 8006d68: fbb0 f5f5 udiv r5, r0, r5 8006d6c: ea4f 0c84 mov.w ip, r4, lsl #2 8006d70: eb06 030c add.w r3, r6, ip 8006d74: eb07 090c add.w r9, r7, ip 8006d78: 9301 str r3, [sp, #4] 8006d7a: b39d cbz r5, 8006de4 8006d7c: f04f 0a00 mov.w sl, #0 8006d80: 4638 mov r0, r7 8006d82: 46b6 mov lr, r6 8006d84: 46d3 mov fp, sl 8006d86: f850 2b04 ldr.w r2, [r0], #4 8006d8a: b293 uxth r3, r2 8006d8c: fb05 a303 mla r3, r5, r3, sl 8006d90: 0c12 lsrs r2, r2, #16 8006d92: ea4f 4a13 mov.w sl, r3, lsr #16 8006d96: fb05 a202 mla r2, r5, r2, sl 8006d9a: b29b uxth r3, r3 8006d9c: ebab 0303 sub.w r3, fp, r3 8006da0: f8de b000 ldr.w fp, [lr] 8006da4: ea4f 4a12 mov.w sl, r2, lsr #16 8006da8: fa1f fb8b uxth.w fp, fp 8006dac: 445b add r3, fp 8006dae: fa1f fb82 uxth.w fp, r2 8006db2: f8de 2000 ldr.w r2, [lr] 8006db6: 4581 cmp r9, r0 8006db8: ebcb 4212 rsb r2, fp, r2, lsr #16 8006dbc: eb02 4223 add.w r2, r2, r3, asr #16 8006dc0: b29b uxth r3, r3 8006dc2: ea43 4302 orr.w r3, r3, r2, lsl #16 8006dc6: ea4f 4b22 mov.w fp, r2, asr #16 8006dca: f84e 3b04 str.w r3, [lr], #4 8006dce: d2da bcs.n 8006d86 8006dd0: f856 300c ldr.w r3, [r6, ip] 8006dd4: b933 cbnz r3, 8006de4 8006dd6: 9b01 ldr r3, [sp, #4] 8006dd8: 3b04 subs r3, #4 8006dda: 429e cmp r6, r3 8006ddc: 461a mov r2, r3 8006dde: d331 bcc.n 8006e44 8006de0: f8c8 4010 str.w r4, [r8, #16] 8006de4: 4640 mov r0, r8 8006de6: f001 fa11 bl 800820c <__mcmp> 8006dea: 2800 cmp r0, #0 8006dec: db26 blt.n 8006e3c 8006dee: 4630 mov r0, r6 8006df0: f04f 0c00 mov.w ip, #0 8006df4: 3501 adds r5, #1 8006df6: f857 1b04 ldr.w r1, [r7], #4 8006dfa: f8d0 e000 ldr.w lr, [r0] 8006dfe: b28b uxth r3, r1 8006e00: ebac 0303 sub.w r3, ip, r3 8006e04: fa1f f28e uxth.w r2, lr 8006e08: 4413 add r3, r2 8006e0a: 0c0a lsrs r2, r1, #16 8006e0c: ebc2 421e rsb r2, r2, lr, lsr #16 8006e10: eb02 4223 add.w r2, r2, r3, asr #16 8006e14: b29b uxth r3, r3 8006e16: ea43 4302 orr.w r3, r3, r2, lsl #16 8006e1a: 45b9 cmp r9, r7 8006e1c: ea4f 4c22 mov.w ip, r2, asr #16 8006e20: f840 3b04 str.w r3, [r0], #4 8006e24: d2e7 bcs.n 8006df6 8006e26: f856 2024 ldr.w r2, [r6, r4, lsl #2] 8006e2a: eb06 0384 add.w r3, r6, r4, lsl #2 8006e2e: b92a cbnz r2, 8006e3c 8006e30: 3b04 subs r3, #4 8006e32: 429e cmp r6, r3 8006e34: 461a mov r2, r3 8006e36: d30b bcc.n 8006e50 8006e38: f8c8 4010 str.w r4, [r8, #16] 8006e3c: 4628 mov r0, r5 8006e3e: b003 add sp, #12 8006e40: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8006e44: 6812 ldr r2, [r2, #0] 8006e46: 3b04 subs r3, #4 8006e48: 2a00 cmp r2, #0 8006e4a: d1c9 bne.n 8006de0 8006e4c: 3c01 subs r4, #1 8006e4e: e7c4 b.n 8006dda 8006e50: 6812 ldr r2, [r2, #0] 8006e52: 3b04 subs r3, #4 8006e54: 2a00 cmp r2, #0 8006e56: d1ef bne.n 8006e38 8006e58: 3c01 subs r4, #1 8006e5a: e7ea b.n 8006e32 8006e5c: 2000 movs r0, #0 8006e5e: e7ee b.n 8006e3e 08006e60 <_dtoa_r>: 8006e60: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8006e64: 4616 mov r6, r2 8006e66: 461f mov r7, r3 8006e68: 6a45 ldr r5, [r0, #36] ; 0x24 8006e6a: b095 sub sp, #84 ; 0x54 8006e6c: 4604 mov r4, r0 8006e6e: f8dd 8084 ldr.w r8, [sp, #132] ; 0x84 8006e72: e9cd 6702 strd r6, r7, [sp, #8] 8006e76: b93d cbnz r5, 8006e88 <_dtoa_r+0x28> 8006e78: 2010 movs r0, #16 8006e7a: f000 ff91 bl 8007da0 8006e7e: 6260 str r0, [r4, #36] ; 0x24 8006e80: e9c0 5501 strd r5, r5, [r0, #4] 8006e84: 6005 str r5, [r0, #0] 8006e86: 60c5 str r5, [r0, #12] 8006e88: 6a63 ldr r3, [r4, #36] ; 0x24 8006e8a: 6819 ldr r1, [r3, #0] 8006e8c: b151 cbz r1, 8006ea4 <_dtoa_r+0x44> 8006e8e: 685a ldr r2, [r3, #4] 8006e90: 2301 movs r3, #1 8006e92: 4093 lsls r3, r2 8006e94: 604a str r2, [r1, #4] 8006e96: 608b str r3, [r1, #8] 8006e98: 4620 mov r0, r4 8006e9a: f000 ffd6 bl 8007e4a <_Bfree> 8006e9e: 2200 movs r2, #0 8006ea0: 6a63 ldr r3, [r4, #36] ; 0x24 8006ea2: 601a str r2, [r3, #0] 8006ea4: 1e3b subs r3, r7, #0 8006ea6: bfaf iteee ge 8006ea8: 2300 movge r3, #0 8006eaa: 2201 movlt r2, #1 8006eac: f023 4300 biclt.w r3, r3, #2147483648 ; 0x80000000 8006eb0: 9303 strlt r3, [sp, #12] 8006eb2: bfac ite ge 8006eb4: f8c8 3000 strge.w r3, [r8] 8006eb8: f8c8 2000 strlt.w r2, [r8] 8006ebc: 4bae ldr r3, [pc, #696] ; (8007178 <_dtoa_r+0x318>) 8006ebe: f8dd 800c ldr.w r8, [sp, #12] 8006ec2: ea33 0308 bics.w r3, r3, r8 8006ec6: d11b bne.n 8006f00 <_dtoa_r+0xa0> 8006ec8: f242 730f movw r3, #9999 ; 0x270f 8006ecc: 9a20 ldr r2, [sp, #128] ; 0x80 8006ece: 6013 str r3, [r2, #0] 8006ed0: 9b02 ldr r3, [sp, #8] 8006ed2: b923 cbnz r3, 8006ede <_dtoa_r+0x7e> 8006ed4: f3c8 0013 ubfx r0, r8, #0, #20 8006ed8: 2800 cmp r0, #0 8006eda: f000 8545 beq.w 8007968 <_dtoa_r+0xb08> 8006ede: 9b22 ldr r3, [sp, #136] ; 0x88 8006ee0: b953 cbnz r3, 8006ef8 <_dtoa_r+0x98> 8006ee2: 4ba6 ldr r3, [pc, #664] ; (800717c <_dtoa_r+0x31c>) 8006ee4: e021 b.n 8006f2a <_dtoa_r+0xca> 8006ee6: 4ba6 ldr r3, [pc, #664] ; (8007180 <_dtoa_r+0x320>) 8006ee8: 9306 str r3, [sp, #24] 8006eea: 3308 adds r3, #8 8006eec: 9a22 ldr r2, [sp, #136] ; 0x88 8006eee: 6013 str r3, [r2, #0] 8006ef0: 9806 ldr r0, [sp, #24] 8006ef2: b015 add sp, #84 ; 0x54 8006ef4: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8006ef8: 4ba0 ldr r3, [pc, #640] ; (800717c <_dtoa_r+0x31c>) 8006efa: 9306 str r3, [sp, #24] 8006efc: 3303 adds r3, #3 8006efe: e7f5 b.n 8006eec <_dtoa_r+0x8c> 8006f00: e9dd 6702 ldrd r6, r7, [sp, #8] 8006f04: 2200 movs r2, #0 8006f06: 2300 movs r3, #0 8006f08: 4630 mov r0, r6 8006f0a: 4639 mov r1, r7 8006f0c: f7f9 fdac bl 8000a68 <__aeabi_dcmpeq> 8006f10: 4682 mov sl, r0 8006f12: b160 cbz r0, 8006f2e <_dtoa_r+0xce> 8006f14: 2301 movs r3, #1 8006f16: 9a20 ldr r2, [sp, #128] ; 0x80 8006f18: 6013 str r3, [r2, #0] 8006f1a: 9b22 ldr r3, [sp, #136] ; 0x88 8006f1c: 2b00 cmp r3, #0 8006f1e: f000 8520 beq.w 8007962 <_dtoa_r+0xb02> 8006f22: 4b98 ldr r3, [pc, #608] ; (8007184 <_dtoa_r+0x324>) 8006f24: 9a22 ldr r2, [sp, #136] ; 0x88 8006f26: 6013 str r3, [r2, #0] 8006f28: 3b01 subs r3, #1 8006f2a: 9306 str r3, [sp, #24] 8006f2c: e7e0 b.n 8006ef0 <_dtoa_r+0x90> 8006f2e: ab12 add r3, sp, #72 ; 0x48 8006f30: 9301 str r3, [sp, #4] 8006f32: ab13 add r3, sp, #76 ; 0x4c 8006f34: 9300 str r3, [sp, #0] 8006f36: 4632 mov r2, r6 8006f38: 463b mov r3, r7 8006f3a: 4620 mov r0, r4 8006f3c: f001 f9de bl 80082fc <__d2b> 8006f40: f3c8 550a ubfx r5, r8, #20, #11 8006f44: 4683 mov fp, r0 8006f46: 2d00 cmp r5, #0 8006f48: d07d beq.n 8007046 <_dtoa_r+0x1e6> 8006f4a: 46b0 mov r8, r6 8006f4c: f3c7 0313 ubfx r3, r7, #0, #20 8006f50: f043 597f orr.w r9, r3, #1069547520 ; 0x3fc00000 8006f54: f449 1940 orr.w r9, r9, #3145728 ; 0x300000 8006f58: f2a5 35ff subw r5, r5, #1023 ; 0x3ff 8006f5c: f8cd a040 str.w sl, [sp, #64] ; 0x40 8006f60: 2200 movs r2, #0 8006f62: 4b89 ldr r3, [pc, #548] ; (8007188 <_dtoa_r+0x328>) 8006f64: 4640 mov r0, r8 8006f66: 4649 mov r1, r9 8006f68: f7f9 f95e bl 8000228 <__aeabi_dsub> 8006f6c: a37c add r3, pc, #496 ; (adr r3, 8007160 <_dtoa_r+0x300>) 8006f6e: e9d3 2300 ldrd r2, r3, [r3] 8006f72: f7f9 fb11 bl 8000598 <__aeabi_dmul> 8006f76: a37c add r3, pc, #496 ; (adr r3, 8007168 <_dtoa_r+0x308>) 8006f78: e9d3 2300 ldrd r2, r3, [r3] 8006f7c: f7f9 f956 bl 800022c <__adddf3> 8006f80: 4606 mov r6, r0 8006f82: 4628 mov r0, r5 8006f84: 460f mov r7, r1 8006f86: f7f9 fa9d bl 80004c4 <__aeabi_i2d> 8006f8a: a379 add r3, pc, #484 ; (adr r3, 8007170 <_dtoa_r+0x310>) 8006f8c: e9d3 2300 ldrd r2, r3, [r3] 8006f90: f7f9 fb02 bl 8000598 <__aeabi_dmul> 8006f94: 4602 mov r2, r0 8006f96: 460b mov r3, r1 8006f98: 4630 mov r0, r6 8006f9a: 4639 mov r1, r7 8006f9c: f7f9 f946 bl 800022c <__adddf3> 8006fa0: 4606 mov r6, r0 8006fa2: 460f mov r7, r1 8006fa4: f7f9 fda8 bl 8000af8 <__aeabi_d2iz> 8006fa8: 2200 movs r2, #0 8006faa: 4682 mov sl, r0 8006fac: 2300 movs r3, #0 8006fae: 4630 mov r0, r6 8006fb0: 4639 mov r1, r7 8006fb2: f7f9 fd63 bl 8000a7c <__aeabi_dcmplt> 8006fb6: b148 cbz r0, 8006fcc <_dtoa_r+0x16c> 8006fb8: 4650 mov r0, sl 8006fba: f7f9 fa83 bl 80004c4 <__aeabi_i2d> 8006fbe: 4632 mov r2, r6 8006fc0: 463b mov r3, r7 8006fc2: f7f9 fd51 bl 8000a68 <__aeabi_dcmpeq> 8006fc6: b908 cbnz r0, 8006fcc <_dtoa_r+0x16c> 8006fc8: f10a 3aff add.w sl, sl, #4294967295 8006fcc: f1ba 0f16 cmp.w sl, #22 8006fd0: d85a bhi.n 8007088 <_dtoa_r+0x228> 8006fd2: e9dd 2302 ldrd r2, r3, [sp, #8] 8006fd6: 496d ldr r1, [pc, #436] ; (800718c <_dtoa_r+0x32c>) 8006fd8: eb01 01ca add.w r1, r1, sl, lsl #3 8006fdc: e9d1 0100 ldrd r0, r1, [r1] 8006fe0: f7f9 fd6a bl 8000ab8 <__aeabi_dcmpgt> 8006fe4: 2800 cmp r0, #0 8006fe6: d051 beq.n 800708c <_dtoa_r+0x22c> 8006fe8: 2300 movs r3, #0 8006fea: f10a 3aff add.w sl, sl, #4294967295 8006fee: 930d str r3, [sp, #52] ; 0x34 8006ff0: 9b12 ldr r3, [sp, #72] ; 0x48 8006ff2: 1b5d subs r5, r3, r5 8006ff4: 1e6b subs r3, r5, #1 8006ff6: 9307 str r3, [sp, #28] 8006ff8: bf43 ittte mi 8006ffa: 2300 movmi r3, #0 8006ffc: f1c5 0901 rsbmi r9, r5, #1 8007000: 9307 strmi r3, [sp, #28] 8007002: f04f 0900 movpl.w r9, #0 8007006: f1ba 0f00 cmp.w sl, #0 800700a: db41 blt.n 8007090 <_dtoa_r+0x230> 800700c: 9b07 ldr r3, [sp, #28] 800700e: f8cd a030 str.w sl, [sp, #48] ; 0x30 8007012: 4453 add r3, sl 8007014: 9307 str r3, [sp, #28] 8007016: 2300 movs r3, #0 8007018: 9308 str r3, [sp, #32] 800701a: 9b1e ldr r3, [sp, #120] ; 0x78 800701c: 2b09 cmp r3, #9 800701e: f200 808f bhi.w 8007140 <_dtoa_r+0x2e0> 8007022: 2b05 cmp r3, #5 8007024: bfc4 itt gt 8007026: 3b04 subgt r3, #4 8007028: 931e strgt r3, [sp, #120] ; 0x78 800702a: 9b1e ldr r3, [sp, #120] ; 0x78 800702c: bfc8 it gt 800702e: 2500 movgt r5, #0 8007030: f1a3 0302 sub.w r3, r3, #2 8007034: bfd8 it le 8007036: 2501 movle r5, #1 8007038: 2b03 cmp r3, #3 800703a: f200 808d bhi.w 8007158 <_dtoa_r+0x2f8> 800703e: e8df f003 tbb [pc, r3] 8007042: 7d7b .short 0x7d7b 8007044: 6f2f .short 0x6f2f 8007046: e9dd 5312 ldrd r5, r3, [sp, #72] ; 0x48 800704a: 441d add r5, r3 800704c: f205 4032 addw r0, r5, #1074 ; 0x432 8007050: 2820 cmp r0, #32 8007052: dd13 ble.n 800707c <_dtoa_r+0x21c> 8007054: f1c0 0040 rsb r0, r0, #64 ; 0x40 8007058: 9b02 ldr r3, [sp, #8] 800705a: fa08 f800 lsl.w r8, r8, r0 800705e: f205 4012 addw r0, r5, #1042 ; 0x412 8007062: fa23 f000 lsr.w r0, r3, r0 8007066: ea48 0000 orr.w r0, r8, r0 800706a: f7f9 fa1b bl 80004a4 <__aeabi_ui2d> 800706e: 2301 movs r3, #1 8007070: 4680 mov r8, r0 8007072: f1a1 79f8 sub.w r9, r1, #32505856 ; 0x1f00000 8007076: 3d01 subs r5, #1 8007078: 9310 str r3, [sp, #64] ; 0x40 800707a: e771 b.n 8006f60 <_dtoa_r+0x100> 800707c: 9b02 ldr r3, [sp, #8] 800707e: f1c0 0020 rsb r0, r0, #32 8007082: fa03 f000 lsl.w r0, r3, r0 8007086: e7f0 b.n 800706a <_dtoa_r+0x20a> 8007088: 2301 movs r3, #1 800708a: e7b0 b.n 8006fee <_dtoa_r+0x18e> 800708c: 900d str r0, [sp, #52] ; 0x34 800708e: e7af b.n 8006ff0 <_dtoa_r+0x190> 8007090: f1ca 0300 rsb r3, sl, #0 8007094: 9308 str r3, [sp, #32] 8007096: 2300 movs r3, #0 8007098: eba9 090a sub.w r9, r9, sl 800709c: 930c str r3, [sp, #48] ; 0x30 800709e: e7bc b.n 800701a <_dtoa_r+0x1ba> 80070a0: 2301 movs r3, #1 80070a2: 9309 str r3, [sp, #36] ; 0x24 80070a4: 9b1f ldr r3, [sp, #124] ; 0x7c 80070a6: 2b00 cmp r3, #0 80070a8: dd74 ble.n 8007194 <_dtoa_r+0x334> 80070aa: 4698 mov r8, r3 80070ac: 9304 str r3, [sp, #16] 80070ae: 2200 movs r2, #0 80070b0: 6a66 ldr r6, [r4, #36] ; 0x24 80070b2: 6072 str r2, [r6, #4] 80070b4: 2204 movs r2, #4 80070b6: f102 0014 add.w r0, r2, #20 80070ba: 4298 cmp r0, r3 80070bc: 6871 ldr r1, [r6, #4] 80070be: d96e bls.n 800719e <_dtoa_r+0x33e> 80070c0: 4620 mov r0, r4 80070c2: f000 fe8e bl 8007de2 <_Balloc> 80070c6: 6a63 ldr r3, [r4, #36] ; 0x24 80070c8: 6030 str r0, [r6, #0] 80070ca: 681b ldr r3, [r3, #0] 80070cc: f1b8 0f0e cmp.w r8, #14 80070d0: 9306 str r3, [sp, #24] 80070d2: f200 80ed bhi.w 80072b0 <_dtoa_r+0x450> 80070d6: 2d00 cmp r5, #0 80070d8: f000 80ea beq.w 80072b0 <_dtoa_r+0x450> 80070dc: e9dd 2302 ldrd r2, r3, [sp, #8] 80070e0: f1ba 0f00 cmp.w sl, #0 80070e4: e9cd 230e strd r2, r3, [sp, #56] ; 0x38 80070e8: dd77 ble.n 80071da <_dtoa_r+0x37a> 80070ea: 4a28 ldr r2, [pc, #160] ; (800718c <_dtoa_r+0x32c>) 80070ec: f00a 030f and.w r3, sl, #15 80070f0: ea4f 162a mov.w r6, sl, asr #4 80070f4: eb02 03c3 add.w r3, r2, r3, lsl #3 80070f8: 06f0 lsls r0, r6, #27 80070fa: e9d3 2300 ldrd r2, r3, [r3] 80070fe: e9cd 230a strd r2, r3, [sp, #40] ; 0x28 8007102: d568 bpl.n 80071d6 <_dtoa_r+0x376> 8007104: e9dd 010e ldrd r0, r1, [sp, #56] ; 0x38 8007108: 4b21 ldr r3, [pc, #132] ; (8007190 <_dtoa_r+0x330>) 800710a: 2503 movs r5, #3 800710c: e9d3 2308 ldrd r2, r3, [r3, #32] 8007110: f7f9 fb6c bl 80007ec <__aeabi_ddiv> 8007114: e9cd 0102 strd r0, r1, [sp, #8] 8007118: f006 060f and.w r6, r6, #15 800711c: 4f1c ldr r7, [pc, #112] ; (8007190 <_dtoa_r+0x330>) 800711e: e04f b.n 80071c0 <_dtoa_r+0x360> 8007120: 2301 movs r3, #1 8007122: 9309 str r3, [sp, #36] ; 0x24 8007124: 9b1f ldr r3, [sp, #124] ; 0x7c 8007126: 4453 add r3, sl 8007128: f103 0801 add.w r8, r3, #1 800712c: 9304 str r3, [sp, #16] 800712e: 4643 mov r3, r8 8007130: 2b01 cmp r3, #1 8007132: bfb8 it lt 8007134: 2301 movlt r3, #1 8007136: e7ba b.n 80070ae <_dtoa_r+0x24e> 8007138: 2300 movs r3, #0 800713a: e7b2 b.n 80070a2 <_dtoa_r+0x242> 800713c: 2300 movs r3, #0 800713e: e7f0 b.n 8007122 <_dtoa_r+0x2c2> 8007140: 2501 movs r5, #1 8007142: 2300 movs r3, #0 8007144: 9509 str r5, [sp, #36] ; 0x24 8007146: 931e str r3, [sp, #120] ; 0x78 8007148: f04f 33ff mov.w r3, #4294967295 800714c: 2200 movs r2, #0 800714e: 9304 str r3, [sp, #16] 8007150: 4698 mov r8, r3 8007152: 2312 movs r3, #18 8007154: 921f str r2, [sp, #124] ; 0x7c 8007156: e7aa b.n 80070ae <_dtoa_r+0x24e> 8007158: 2301 movs r3, #1 800715a: 9309 str r3, [sp, #36] ; 0x24 800715c: e7f4 b.n 8007148 <_dtoa_r+0x2e8> 800715e: bf00 nop 8007160: 636f4361 .word 0x636f4361 8007164: 3fd287a7 .word 0x3fd287a7 8007168: 8b60c8b3 .word 0x8b60c8b3 800716c: 3fc68a28 .word 0x3fc68a28 8007170: 509f79fb .word 0x509f79fb 8007174: 3fd34413 .word 0x3fd34413 8007178: 7ff00000 .word 0x7ff00000 800717c: 08008d45 .word 0x08008d45 8007180: 08008d3c .word 0x08008d3c 8007184: 08008d19 .word 0x08008d19 8007188: 3ff80000 .word 0x3ff80000 800718c: 08008dd8 .word 0x08008dd8 8007190: 08008db0 .word 0x08008db0 8007194: 2301 movs r3, #1 8007196: 9304 str r3, [sp, #16] 8007198: 4698 mov r8, r3 800719a: 461a mov r2, r3 800719c: e7da b.n 8007154 <_dtoa_r+0x2f4> 800719e: 3101 adds r1, #1 80071a0: 6071 str r1, [r6, #4] 80071a2: 0052 lsls r2, r2, #1 80071a4: e787 b.n 80070b6 <_dtoa_r+0x256> 80071a6: 07f1 lsls r1, r6, #31 80071a8: d508 bpl.n 80071bc <_dtoa_r+0x35c> 80071aa: e9dd 010a ldrd r0, r1, [sp, #40] ; 0x28 80071ae: e9d7 2300 ldrd r2, r3, [r7] 80071b2: f7f9 f9f1 bl 8000598 <__aeabi_dmul> 80071b6: e9cd 010a strd r0, r1, [sp, #40] ; 0x28 80071ba: 3501 adds r5, #1 80071bc: 1076 asrs r6, r6, #1 80071be: 3708 adds r7, #8 80071c0: 2e00 cmp r6, #0 80071c2: d1f0 bne.n 80071a6 <_dtoa_r+0x346> 80071c4: e9dd 230a ldrd r2, r3, [sp, #40] ; 0x28 80071c8: e9dd 0102 ldrd r0, r1, [sp, #8] 80071cc: f7f9 fb0e bl 80007ec <__aeabi_ddiv> 80071d0: e9cd 0102 strd r0, r1, [sp, #8] 80071d4: e01b b.n 800720e <_dtoa_r+0x3ae> 80071d6: 2502 movs r5, #2 80071d8: e7a0 b.n 800711c <_dtoa_r+0x2bc> 80071da: f000 80a4 beq.w 8007326 <_dtoa_r+0x4c6> 80071de: e9dd 010e ldrd r0, r1, [sp, #56] ; 0x38 80071e2: f1ca 0600 rsb r6, sl, #0 80071e6: 4ba0 ldr r3, [pc, #640] ; (8007468 <_dtoa_r+0x608>) 80071e8: f006 020f and.w r2, r6, #15 80071ec: eb03 03c2 add.w r3, r3, r2, lsl #3 80071f0: e9d3 2300 ldrd r2, r3, [r3] 80071f4: f7f9 f9d0 bl 8000598 <__aeabi_dmul> 80071f8: 2502 movs r5, #2 80071fa: 2300 movs r3, #0 80071fc: e9cd 0102 strd r0, r1, [sp, #8] 8007200: 4f9a ldr r7, [pc, #616] ; (800746c <_dtoa_r+0x60c>) 8007202: 1136 asrs r6, r6, #4 8007204: 2e00 cmp r6, #0 8007206: f040 8083 bne.w 8007310 <_dtoa_r+0x4b0> 800720a: 2b00 cmp r3, #0 800720c: d1e0 bne.n 80071d0 <_dtoa_r+0x370> 800720e: 9b0d ldr r3, [sp, #52] ; 0x34 8007210: 2b00 cmp r3, #0 8007212: f000 808a beq.w 800732a <_dtoa_r+0x4ca> 8007216: e9dd 2302 ldrd r2, r3, [sp, #8] 800721a: e9cd 230a strd r2, r3, [sp, #40] ; 0x28 800721e: e9dd 010a ldrd r0, r1, [sp, #40] ; 0x28 8007222: 2200 movs r2, #0 8007224: 4b92 ldr r3, [pc, #584] ; (8007470 <_dtoa_r+0x610>) 8007226: f7f9 fc29 bl 8000a7c <__aeabi_dcmplt> 800722a: 2800 cmp r0, #0 800722c: d07d beq.n 800732a <_dtoa_r+0x4ca> 800722e: f1b8 0f00 cmp.w r8, #0 8007232: d07a beq.n 800732a <_dtoa_r+0x4ca> 8007234: 9b04 ldr r3, [sp, #16] 8007236: 2b00 cmp r3, #0 8007238: dd36 ble.n 80072a8 <_dtoa_r+0x448> 800723a: e9dd 010a ldrd r0, r1, [sp, #40] ; 0x28 800723e: 2200 movs r2, #0 8007240: 4b8c ldr r3, [pc, #560] ; (8007474 <_dtoa_r+0x614>) 8007242: f7f9 f9a9 bl 8000598 <__aeabi_dmul> 8007246: e9cd 0102 strd r0, r1, [sp, #8] 800724a: 9e04 ldr r6, [sp, #16] 800724c: f10a 37ff add.w r7, sl, #4294967295 8007250: 3501 adds r5, #1 8007252: 4628 mov r0, r5 8007254: f7f9 f936 bl 80004c4 <__aeabi_i2d> 8007258: e9dd 2302 ldrd r2, r3, [sp, #8] 800725c: f7f9 f99c bl 8000598 <__aeabi_dmul> 8007260: 2200 movs r2, #0 8007262: 4b85 ldr r3, [pc, #532] ; (8007478 <_dtoa_r+0x618>) 8007264: f7f8 ffe2 bl 800022c <__adddf3> 8007268: f1a1 7550 sub.w r5, r1, #54525952 ; 0x3400000 800726c: e9cd 010a strd r0, r1, [sp, #40] ; 0x28 8007270: 950b str r5, [sp, #44] ; 0x2c 8007272: 2e00 cmp r6, #0 8007274: d15c bne.n 8007330 <_dtoa_r+0x4d0> 8007276: e9dd 0102 ldrd r0, r1, [sp, #8] 800727a: 2200 movs r2, #0 800727c: 4b7f ldr r3, [pc, #508] ; (800747c <_dtoa_r+0x61c>) 800727e: f7f8 ffd3 bl 8000228 <__aeabi_dsub> 8007282: 9a0a ldr r2, [sp, #40] ; 0x28 8007284: 462b mov r3, r5 8007286: e9cd 0102 strd r0, r1, [sp, #8] 800728a: f7f9 fc15 bl 8000ab8 <__aeabi_dcmpgt> 800728e: 2800 cmp r0, #0 8007290: f040 8281 bne.w 8007796 <_dtoa_r+0x936> 8007294: e9dd 0102 ldrd r0, r1, [sp, #8] 8007298: 9a0a ldr r2, [sp, #40] ; 0x28 800729a: f105 4300 add.w r3, r5, #2147483648 ; 0x80000000 800729e: f7f9 fbed bl 8000a7c <__aeabi_dcmplt> 80072a2: 2800 cmp r0, #0 80072a4: f040 8275 bne.w 8007792 <_dtoa_r+0x932> 80072a8: e9dd 230e ldrd r2, r3, [sp, #56] ; 0x38 80072ac: e9cd 2302 strd r2, r3, [sp, #8] 80072b0: 9b13 ldr r3, [sp, #76] ; 0x4c 80072b2: 2b00 cmp r3, #0 80072b4: f2c0 814b blt.w 800754e <_dtoa_r+0x6ee> 80072b8: f1ba 0f0e cmp.w sl, #14 80072bc: f300 8147 bgt.w 800754e <_dtoa_r+0x6ee> 80072c0: 4b69 ldr r3, [pc, #420] ; (8007468 <_dtoa_r+0x608>) 80072c2: eb03 03ca add.w r3, r3, sl, lsl #3 80072c6: e9d3 2300 ldrd r2, r3, [r3] 80072ca: e9cd 2304 strd r2, r3, [sp, #16] 80072ce: 9b1f ldr r3, [sp, #124] ; 0x7c 80072d0: 2b00 cmp r3, #0 80072d2: f280 80d7 bge.w 8007484 <_dtoa_r+0x624> 80072d6: f1b8 0f00 cmp.w r8, #0 80072da: f300 80d3 bgt.w 8007484 <_dtoa_r+0x624> 80072de: f040 8257 bne.w 8007790 <_dtoa_r+0x930> 80072e2: e9dd 0104 ldrd r0, r1, [sp, #16] 80072e6: 2200 movs r2, #0 80072e8: 4b64 ldr r3, [pc, #400] ; (800747c <_dtoa_r+0x61c>) 80072ea: f7f9 f955 bl 8000598 <__aeabi_dmul> 80072ee: e9dd 2302 ldrd r2, r3, [sp, #8] 80072f2: f7f9 fbd7 bl 8000aa4 <__aeabi_dcmpge> 80072f6: 4646 mov r6, r8 80072f8: 4647 mov r7, r8 80072fa: 2800 cmp r0, #0 80072fc: f040 822d bne.w 800775a <_dtoa_r+0x8fa> 8007300: 9b06 ldr r3, [sp, #24] 8007302: 9a06 ldr r2, [sp, #24] 8007304: 1c5d adds r5, r3, #1 8007306: 2331 movs r3, #49 ; 0x31 8007308: f10a 0a01 add.w sl, sl, #1 800730c: 7013 strb r3, [r2, #0] 800730e: e228 b.n 8007762 <_dtoa_r+0x902> 8007310: 07f2 lsls r2, r6, #31 8007312: d505 bpl.n 8007320 <_dtoa_r+0x4c0> 8007314: e9d7 2300 ldrd r2, r3, [r7] 8007318: f7f9 f93e bl 8000598 <__aeabi_dmul> 800731c: 2301 movs r3, #1 800731e: 3501 adds r5, #1 8007320: 1076 asrs r6, r6, #1 8007322: 3708 adds r7, #8 8007324: e76e b.n 8007204 <_dtoa_r+0x3a4> 8007326: 2502 movs r5, #2 8007328: e771 b.n 800720e <_dtoa_r+0x3ae> 800732a: 4657 mov r7, sl 800732c: 4646 mov r6, r8 800732e: e790 b.n 8007252 <_dtoa_r+0x3f2> 8007330: 4b4d ldr r3, [pc, #308] ; (8007468 <_dtoa_r+0x608>) 8007332: eb03 03c6 add.w r3, r3, r6, lsl #3 8007336: e953 0102 ldrd r0, r1, [r3, #-8] 800733a: 9b09 ldr r3, [sp, #36] ; 0x24 800733c: 2b00 cmp r3, #0 800733e: d048 beq.n 80073d2 <_dtoa_r+0x572> 8007340: 4602 mov r2, r0 8007342: 460b mov r3, r1 8007344: 2000 movs r0, #0 8007346: 494e ldr r1, [pc, #312] ; (8007480 <_dtoa_r+0x620>) 8007348: f7f9 fa50 bl 80007ec <__aeabi_ddiv> 800734c: e9dd 230a ldrd r2, r3, [sp, #40] ; 0x28 8007350: f7f8 ff6a bl 8000228 <__aeabi_dsub> 8007354: e9cd 010a strd r0, r1, [sp, #40] ; 0x28 8007358: 9d06 ldr r5, [sp, #24] 800735a: e9dd 0102 ldrd r0, r1, [sp, #8] 800735e: f7f9 fbcb bl 8000af8 <__aeabi_d2iz> 8007362: 9011 str r0, [sp, #68] ; 0x44 8007364: f7f9 f8ae bl 80004c4 <__aeabi_i2d> 8007368: 4602 mov r2, r0 800736a: 460b mov r3, r1 800736c: e9dd 0102 ldrd r0, r1, [sp, #8] 8007370: f7f8 ff5a bl 8000228 <__aeabi_dsub> 8007374: 9b11 ldr r3, [sp, #68] ; 0x44 8007376: e9cd 0102 strd r0, r1, [sp, #8] 800737a: 3330 adds r3, #48 ; 0x30 800737c: f805 3b01 strb.w r3, [r5], #1 8007380: e9dd 230a ldrd r2, r3, [sp, #40] ; 0x28 8007384: f7f9 fb7a bl 8000a7c <__aeabi_dcmplt> 8007388: 2800 cmp r0, #0 800738a: d163 bne.n 8007454 <_dtoa_r+0x5f4> 800738c: e9dd 2302 ldrd r2, r3, [sp, #8] 8007390: 2000 movs r0, #0 8007392: 4937 ldr r1, [pc, #220] ; (8007470 <_dtoa_r+0x610>) 8007394: f7f8 ff48 bl 8000228 <__aeabi_dsub> 8007398: e9dd 230a ldrd r2, r3, [sp, #40] ; 0x28 800739c: f7f9 fb6e bl 8000a7c <__aeabi_dcmplt> 80073a0: 2800 cmp r0, #0 80073a2: f040 80b5 bne.w 8007510 <_dtoa_r+0x6b0> 80073a6: 9b06 ldr r3, [sp, #24] 80073a8: 1aeb subs r3, r5, r3 80073aa: 429e cmp r6, r3 80073ac: f77f af7c ble.w 80072a8 <_dtoa_r+0x448> 80073b0: e9dd 010a ldrd r0, r1, [sp, #40] ; 0x28 80073b4: 2200 movs r2, #0 80073b6: 4b2f ldr r3, [pc, #188] ; (8007474 <_dtoa_r+0x614>) 80073b8: f7f9 f8ee bl 8000598 <__aeabi_dmul> 80073bc: 2200 movs r2, #0 80073be: e9cd 010a strd r0, r1, [sp, #40] ; 0x28 80073c2: e9dd 0102 ldrd r0, r1, [sp, #8] 80073c6: 4b2b ldr r3, [pc, #172] ; (8007474 <_dtoa_r+0x614>) 80073c8: f7f9 f8e6 bl 8000598 <__aeabi_dmul> 80073cc: e9cd 0102 strd r0, r1, [sp, #8] 80073d0: e7c3 b.n 800735a <_dtoa_r+0x4fa> 80073d2: e9dd 230a ldrd r2, r3, [sp, #40] ; 0x28 80073d6: f7f9 f8df bl 8000598 <__aeabi_dmul> 80073da: 9b06 ldr r3, [sp, #24] 80073dc: e9cd 010a strd r0, r1, [sp, #40] ; 0x28 80073e0: 199d adds r5, r3, r6 80073e2: 461e mov r6, r3 80073e4: e9dd 0102 ldrd r0, r1, [sp, #8] 80073e8: f7f9 fb86 bl 8000af8 <__aeabi_d2iz> 80073ec: 9011 str r0, [sp, #68] ; 0x44 80073ee: f7f9 f869 bl 80004c4 <__aeabi_i2d> 80073f2: 4602 mov r2, r0 80073f4: 460b mov r3, r1 80073f6: e9dd 0102 ldrd r0, r1, [sp, #8] 80073fa: f7f8 ff15 bl 8000228 <__aeabi_dsub> 80073fe: 9b11 ldr r3, [sp, #68] ; 0x44 8007400: e9cd 0102 strd r0, r1, [sp, #8] 8007404: 3330 adds r3, #48 ; 0x30 8007406: f806 3b01 strb.w r3, [r6], #1 800740a: 42ae cmp r6, r5 800740c: f04f 0200 mov.w r2, #0 8007410: d124 bne.n 800745c <_dtoa_r+0x5fc> 8007412: e9dd 010a ldrd r0, r1, [sp, #40] ; 0x28 8007416: 4b1a ldr r3, [pc, #104] ; (8007480 <_dtoa_r+0x620>) 8007418: f7f8 ff08 bl 800022c <__adddf3> 800741c: 4602 mov r2, r0 800741e: 460b mov r3, r1 8007420: e9dd 0102 ldrd r0, r1, [sp, #8] 8007424: f7f9 fb48 bl 8000ab8 <__aeabi_dcmpgt> 8007428: 2800 cmp r0, #0 800742a: d171 bne.n 8007510 <_dtoa_r+0x6b0> 800742c: e9dd 230a ldrd r2, r3, [sp, #40] ; 0x28 8007430: 2000 movs r0, #0 8007432: 4913 ldr r1, [pc, #76] ; (8007480 <_dtoa_r+0x620>) 8007434: f7f8 fef8 bl 8000228 <__aeabi_dsub> 8007438: 4602 mov r2, r0 800743a: 460b mov r3, r1 800743c: e9dd 0102 ldrd r0, r1, [sp, #8] 8007440: f7f9 fb1c bl 8000a7c <__aeabi_dcmplt> 8007444: 2800 cmp r0, #0 8007446: f43f af2f beq.w 80072a8 <_dtoa_r+0x448> 800744a: f815 3c01 ldrb.w r3, [r5, #-1] 800744e: 1e6a subs r2, r5, #1 8007450: 2b30 cmp r3, #48 ; 0x30 8007452: d001 beq.n 8007458 <_dtoa_r+0x5f8> 8007454: 46ba mov sl, r7 8007456: e04a b.n 80074ee <_dtoa_r+0x68e> 8007458: 4615 mov r5, r2 800745a: e7f6 b.n 800744a <_dtoa_r+0x5ea> 800745c: 4b05 ldr r3, [pc, #20] ; (8007474 <_dtoa_r+0x614>) 800745e: f7f9 f89b bl 8000598 <__aeabi_dmul> 8007462: e9cd 0102 strd r0, r1, [sp, #8] 8007466: e7bd b.n 80073e4 <_dtoa_r+0x584> 8007468: 08008dd8 .word 0x08008dd8 800746c: 08008db0 .word 0x08008db0 8007470: 3ff00000 .word 0x3ff00000 8007474: 40240000 .word 0x40240000 8007478: 401c0000 .word 0x401c0000 800747c: 40140000 .word 0x40140000 8007480: 3fe00000 .word 0x3fe00000 8007484: 9d06 ldr r5, [sp, #24] 8007486: e9dd 6702 ldrd r6, r7, [sp, #8] 800748a: e9dd 2304 ldrd r2, r3, [sp, #16] 800748e: 4630 mov r0, r6 8007490: 4639 mov r1, r7 8007492: f7f9 f9ab bl 80007ec <__aeabi_ddiv> 8007496: f7f9 fb2f bl 8000af8 <__aeabi_d2iz> 800749a: 4681 mov r9, r0 800749c: f7f9 f812 bl 80004c4 <__aeabi_i2d> 80074a0: e9dd 2304 ldrd r2, r3, [sp, #16] 80074a4: f7f9 f878 bl 8000598 <__aeabi_dmul> 80074a8: 4602 mov r2, r0 80074aa: 460b mov r3, r1 80074ac: 4630 mov r0, r6 80074ae: 4639 mov r1, r7 80074b0: f7f8 feba bl 8000228 <__aeabi_dsub> 80074b4: f109 0630 add.w r6, r9, #48 ; 0x30 80074b8: f805 6b01 strb.w r6, [r5], #1 80074bc: 9e06 ldr r6, [sp, #24] 80074be: 4602 mov r2, r0 80074c0: 1bae subs r6, r5, r6 80074c2: 45b0 cmp r8, r6 80074c4: 460b mov r3, r1 80074c6: d135 bne.n 8007534 <_dtoa_r+0x6d4> 80074c8: f7f8 feb0 bl 800022c <__adddf3> 80074cc: e9dd 2304 ldrd r2, r3, [sp, #16] 80074d0: 4606 mov r6, r0 80074d2: 460f mov r7, r1 80074d4: f7f9 faf0 bl 8000ab8 <__aeabi_dcmpgt> 80074d8: b9c8 cbnz r0, 800750e <_dtoa_r+0x6ae> 80074da: e9dd 2304 ldrd r2, r3, [sp, #16] 80074de: 4630 mov r0, r6 80074e0: 4639 mov r1, r7 80074e2: f7f9 fac1 bl 8000a68 <__aeabi_dcmpeq> 80074e6: b110 cbz r0, 80074ee <_dtoa_r+0x68e> 80074e8: f019 0f01 tst.w r9, #1 80074ec: d10f bne.n 800750e <_dtoa_r+0x6ae> 80074ee: 4659 mov r1, fp 80074f0: 4620 mov r0, r4 80074f2: f000 fcaa bl 8007e4a <_Bfree> 80074f6: 2300 movs r3, #0 80074f8: 9a20 ldr r2, [sp, #128] ; 0x80 80074fa: 702b strb r3, [r5, #0] 80074fc: f10a 0301 add.w r3, sl, #1 8007500: 6013 str r3, [r2, #0] 8007502: 9b22 ldr r3, [sp, #136] ; 0x88 8007504: 2b00 cmp r3, #0 8007506: f43f acf3 beq.w 8006ef0 <_dtoa_r+0x90> 800750a: 601d str r5, [r3, #0] 800750c: e4f0 b.n 8006ef0 <_dtoa_r+0x90> 800750e: 4657 mov r7, sl 8007510: f815 2c01 ldrb.w r2, [r5, #-1] 8007514: 1e6b subs r3, r5, #1 8007516: 2a39 cmp r2, #57 ; 0x39 8007518: d106 bne.n 8007528 <_dtoa_r+0x6c8> 800751a: 9a06 ldr r2, [sp, #24] 800751c: 429a cmp r2, r3 800751e: d107 bne.n 8007530 <_dtoa_r+0x6d0> 8007520: 2330 movs r3, #48 ; 0x30 8007522: 7013 strb r3, [r2, #0] 8007524: 4613 mov r3, r2 8007526: 3701 adds r7, #1 8007528: 781a ldrb r2, [r3, #0] 800752a: 3201 adds r2, #1 800752c: 701a strb r2, [r3, #0] 800752e: e791 b.n 8007454 <_dtoa_r+0x5f4> 8007530: 461d mov r5, r3 8007532: e7ed b.n 8007510 <_dtoa_r+0x6b0> 8007534: 2200 movs r2, #0 8007536: 4b99 ldr r3, [pc, #612] ; (800779c <_dtoa_r+0x93c>) 8007538: f7f9 f82e bl 8000598 <__aeabi_dmul> 800753c: 2200 movs r2, #0 800753e: 2300 movs r3, #0 8007540: 4606 mov r6, r0 8007542: 460f mov r7, r1 8007544: f7f9 fa90 bl 8000a68 <__aeabi_dcmpeq> 8007548: 2800 cmp r0, #0 800754a: d09e beq.n 800748a <_dtoa_r+0x62a> 800754c: e7cf b.n 80074ee <_dtoa_r+0x68e> 800754e: 9a09 ldr r2, [sp, #36] ; 0x24 8007550: 2a00 cmp r2, #0 8007552: f000 8088 beq.w 8007666 <_dtoa_r+0x806> 8007556: 9a1e ldr r2, [sp, #120] ; 0x78 8007558: 2a01 cmp r2, #1 800755a: dc6d bgt.n 8007638 <_dtoa_r+0x7d8> 800755c: 9a10 ldr r2, [sp, #64] ; 0x40 800755e: 2a00 cmp r2, #0 8007560: d066 beq.n 8007630 <_dtoa_r+0x7d0> 8007562: f203 4333 addw r3, r3, #1075 ; 0x433 8007566: 464d mov r5, r9 8007568: 9e08 ldr r6, [sp, #32] 800756a: 9a07 ldr r2, [sp, #28] 800756c: 2101 movs r1, #1 800756e: 441a add r2, r3 8007570: 4620 mov r0, r4 8007572: 4499 add r9, r3 8007574: 9207 str r2, [sp, #28] 8007576: f000 fd08 bl 8007f8a <__i2b> 800757a: 4607 mov r7, r0 800757c: 2d00 cmp r5, #0 800757e: dd0b ble.n 8007598 <_dtoa_r+0x738> 8007580: 9b07 ldr r3, [sp, #28] 8007582: 2b00 cmp r3, #0 8007584: dd08 ble.n 8007598 <_dtoa_r+0x738> 8007586: 42ab cmp r3, r5 8007588: bfa8 it ge 800758a: 462b movge r3, r5 800758c: 9a07 ldr r2, [sp, #28] 800758e: eba9 0903 sub.w r9, r9, r3 8007592: 1aed subs r5, r5, r3 8007594: 1ad3 subs r3, r2, r3 8007596: 9307 str r3, [sp, #28] 8007598: 9b08 ldr r3, [sp, #32] 800759a: b1eb cbz r3, 80075d8 <_dtoa_r+0x778> 800759c: 9b09 ldr r3, [sp, #36] ; 0x24 800759e: 2b00 cmp r3, #0 80075a0: d065 beq.n 800766e <_dtoa_r+0x80e> 80075a2: b18e cbz r6, 80075c8 <_dtoa_r+0x768> 80075a4: 4639 mov r1, r7 80075a6: 4632 mov r2, r6 80075a8: 4620 mov r0, r4 80075aa: f000 fd8d bl 80080c8 <__pow5mult> 80075ae: 465a mov r2, fp 80075b0: 4601 mov r1, r0 80075b2: 4607 mov r7, r0 80075b4: 4620 mov r0, r4 80075b6: f000 fcf1 bl 8007f9c <__multiply> 80075ba: 4659 mov r1, fp 80075bc: 900a str r0, [sp, #40] ; 0x28 80075be: 4620 mov r0, r4 80075c0: f000 fc43 bl 8007e4a <_Bfree> 80075c4: 9b0a ldr r3, [sp, #40] ; 0x28 80075c6: 469b mov fp, r3 80075c8: 9b08 ldr r3, [sp, #32] 80075ca: 1b9a subs r2, r3, r6 80075cc: d004 beq.n 80075d8 <_dtoa_r+0x778> 80075ce: 4659 mov r1, fp 80075d0: 4620 mov r0, r4 80075d2: f000 fd79 bl 80080c8 <__pow5mult> 80075d6: 4683 mov fp, r0 80075d8: 2101 movs r1, #1 80075da: 4620 mov r0, r4 80075dc: f000 fcd5 bl 8007f8a <__i2b> 80075e0: 9b0c ldr r3, [sp, #48] ; 0x30 80075e2: 4606 mov r6, r0 80075e4: 2b00 cmp r3, #0 80075e6: f000 81c6 beq.w 8007976 <_dtoa_r+0xb16> 80075ea: 461a mov r2, r3 80075ec: 4601 mov r1, r0 80075ee: 4620 mov r0, r4 80075f0: f000 fd6a bl 80080c8 <__pow5mult> 80075f4: 9b1e ldr r3, [sp, #120] ; 0x78 80075f6: 4606 mov r6, r0 80075f8: 2b01 cmp r3, #1 80075fa: dc3e bgt.n 800767a <_dtoa_r+0x81a> 80075fc: 9b02 ldr r3, [sp, #8] 80075fe: 2b00 cmp r3, #0 8007600: d137 bne.n 8007672 <_dtoa_r+0x812> 8007602: 9b03 ldr r3, [sp, #12] 8007604: f3c3 0313 ubfx r3, r3, #0, #20 8007608: 2b00 cmp r3, #0 800760a: d134 bne.n 8007676 <_dtoa_r+0x816> 800760c: 9b03 ldr r3, [sp, #12] 800760e: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000 8007612: 0d1b lsrs r3, r3, #20 8007614: 051b lsls r3, r3, #20 8007616: b12b cbz r3, 8007624 <_dtoa_r+0x7c4> 8007618: 9b07 ldr r3, [sp, #28] 800761a: f109 0901 add.w r9, r9, #1 800761e: 3301 adds r3, #1 8007620: 9307 str r3, [sp, #28] 8007622: 2301 movs r3, #1 8007624: 9308 str r3, [sp, #32] 8007626: 9b0c ldr r3, [sp, #48] ; 0x30 8007628: 2b00 cmp r3, #0 800762a: d128 bne.n 800767e <_dtoa_r+0x81e> 800762c: 2001 movs r0, #1 800762e: e02e b.n 800768e <_dtoa_r+0x82e> 8007630: 9b12 ldr r3, [sp, #72] ; 0x48 8007632: f1c3 0336 rsb r3, r3, #54 ; 0x36 8007636: e796 b.n 8007566 <_dtoa_r+0x706> 8007638: 9b08 ldr r3, [sp, #32] 800763a: f108 36ff add.w r6, r8, #4294967295 800763e: 42b3 cmp r3, r6 8007640: bfb7 itett lt 8007642: 9b08 ldrlt r3, [sp, #32] 8007644: 1b9e subge r6, r3, r6 8007646: 1af2 sublt r2, r6, r3 8007648: 9b0c ldrlt r3, [sp, #48] ; 0x30 800764a: bfbf itttt lt 800764c: 9608 strlt r6, [sp, #32] 800764e: 189b addlt r3, r3, r2 8007650: 930c strlt r3, [sp, #48] ; 0x30 8007652: 2600 movlt r6, #0 8007654: f1b8 0f00 cmp.w r8, #0 8007658: bfb9 ittee lt 800765a: eba9 0508 sublt.w r5, r9, r8 800765e: 2300 movlt r3, #0 8007660: 464d movge r5, r9 8007662: 4643 movge r3, r8 8007664: e781 b.n 800756a <_dtoa_r+0x70a> 8007666: 9e08 ldr r6, [sp, #32] 8007668: 464d mov r5, r9 800766a: 9f09 ldr r7, [sp, #36] ; 0x24 800766c: e786 b.n 800757c <_dtoa_r+0x71c> 800766e: 9a08 ldr r2, [sp, #32] 8007670: e7ad b.n 80075ce <_dtoa_r+0x76e> 8007672: 2300 movs r3, #0 8007674: e7d6 b.n 8007624 <_dtoa_r+0x7c4> 8007676: 9b02 ldr r3, [sp, #8] 8007678: e7d4 b.n 8007624 <_dtoa_r+0x7c4> 800767a: 2300 movs r3, #0 800767c: 9308 str r3, [sp, #32] 800767e: 6933 ldr r3, [r6, #16] 8007680: eb06 0383 add.w r3, r6, r3, lsl #2 8007684: 6918 ldr r0, [r3, #16] 8007686: f000 fc32 bl 8007eee <__hi0bits> 800768a: f1c0 0020 rsb r0, r0, #32 800768e: 9b07 ldr r3, [sp, #28] 8007690: 4418 add r0, r3 8007692: f010 001f ands.w r0, r0, #31 8007696: d047 beq.n 8007728 <_dtoa_r+0x8c8> 8007698: f1c0 0320 rsb r3, r0, #32 800769c: 2b04 cmp r3, #4 800769e: dd3b ble.n 8007718 <_dtoa_r+0x8b8> 80076a0: 9b07 ldr r3, [sp, #28] 80076a2: f1c0 001c rsb r0, r0, #28 80076a6: 4481 add r9, r0 80076a8: 4405 add r5, r0 80076aa: 4403 add r3, r0 80076ac: 9307 str r3, [sp, #28] 80076ae: f1b9 0f00 cmp.w r9, #0 80076b2: dd05 ble.n 80076c0 <_dtoa_r+0x860> 80076b4: 4659 mov r1, fp 80076b6: 464a mov r2, r9 80076b8: 4620 mov r0, r4 80076ba: f000 fd53 bl 8008164 <__lshift> 80076be: 4683 mov fp, r0 80076c0: 9b07 ldr r3, [sp, #28] 80076c2: 2b00 cmp r3, #0 80076c4: dd05 ble.n 80076d2 <_dtoa_r+0x872> 80076c6: 4631 mov r1, r6 80076c8: 461a mov r2, r3 80076ca: 4620 mov r0, r4 80076cc: f000 fd4a bl 8008164 <__lshift> 80076d0: 4606 mov r6, r0 80076d2: 9b0d ldr r3, [sp, #52] ; 0x34 80076d4: b353 cbz r3, 800772c <_dtoa_r+0x8cc> 80076d6: 4631 mov r1, r6 80076d8: 4658 mov r0, fp 80076da: f000 fd97 bl 800820c <__mcmp> 80076de: 2800 cmp r0, #0 80076e0: da24 bge.n 800772c <_dtoa_r+0x8cc> 80076e2: 2300 movs r3, #0 80076e4: 4659 mov r1, fp 80076e6: 220a movs r2, #10 80076e8: 4620 mov r0, r4 80076ea: f000 fbc5 bl 8007e78 <__multadd> 80076ee: 9b09 ldr r3, [sp, #36] ; 0x24 80076f0: f10a 3aff add.w sl, sl, #4294967295 80076f4: 4683 mov fp, r0 80076f6: 2b00 cmp r3, #0 80076f8: f000 8144 beq.w 8007984 <_dtoa_r+0xb24> 80076fc: 2300 movs r3, #0 80076fe: 4639 mov r1, r7 8007700: 220a movs r2, #10 8007702: 4620 mov r0, r4 8007704: f000 fbb8 bl 8007e78 <__multadd> 8007708: 9b04 ldr r3, [sp, #16] 800770a: 4607 mov r7, r0 800770c: 2b00 cmp r3, #0 800770e: dc4d bgt.n 80077ac <_dtoa_r+0x94c> 8007710: 9b1e ldr r3, [sp, #120] ; 0x78 8007712: 2b02 cmp r3, #2 8007714: dd4a ble.n 80077ac <_dtoa_r+0x94c> 8007716: e011 b.n 800773c <_dtoa_r+0x8dc> 8007718: d0c9 beq.n 80076ae <_dtoa_r+0x84e> 800771a: 9a07 ldr r2, [sp, #28] 800771c: 331c adds r3, #28 800771e: 441a add r2, r3 8007720: 4499 add r9, r3 8007722: 441d add r5, r3 8007724: 4613 mov r3, r2 8007726: e7c1 b.n 80076ac <_dtoa_r+0x84c> 8007728: 4603 mov r3, r0 800772a: e7f6 b.n 800771a <_dtoa_r+0x8ba> 800772c: f1b8 0f00 cmp.w r8, #0 8007730: dc36 bgt.n 80077a0 <_dtoa_r+0x940> 8007732: 9b1e ldr r3, [sp, #120] ; 0x78 8007734: 2b02 cmp r3, #2 8007736: dd33 ble.n 80077a0 <_dtoa_r+0x940> 8007738: f8cd 8010 str.w r8, [sp, #16] 800773c: 9b04 ldr r3, [sp, #16] 800773e: b963 cbnz r3, 800775a <_dtoa_r+0x8fa> 8007740: 4631 mov r1, r6 8007742: 2205 movs r2, #5 8007744: 4620 mov r0, r4 8007746: f000 fb97 bl 8007e78 <__multadd> 800774a: 4601 mov r1, r0 800774c: 4606 mov r6, r0 800774e: 4658 mov r0, fp 8007750: f000 fd5c bl 800820c <__mcmp> 8007754: 2800 cmp r0, #0 8007756: f73f add3 bgt.w 8007300 <_dtoa_r+0x4a0> 800775a: 9b1f ldr r3, [sp, #124] ; 0x7c 800775c: 9d06 ldr r5, [sp, #24] 800775e: ea6f 0a03 mvn.w sl, r3 8007762: f04f 0900 mov.w r9, #0 8007766: 4631 mov r1, r6 8007768: 4620 mov r0, r4 800776a: f000 fb6e bl 8007e4a <_Bfree> 800776e: 2f00 cmp r7, #0 8007770: f43f aebd beq.w 80074ee <_dtoa_r+0x68e> 8007774: f1b9 0f00 cmp.w r9, #0 8007778: d005 beq.n 8007786 <_dtoa_r+0x926> 800777a: 45b9 cmp r9, r7 800777c: d003 beq.n 8007786 <_dtoa_r+0x926> 800777e: 4649 mov r1, r9 8007780: 4620 mov r0, r4 8007782: f000 fb62 bl 8007e4a <_Bfree> 8007786: 4639 mov r1, r7 8007788: 4620 mov r0, r4 800778a: f000 fb5e bl 8007e4a <_Bfree> 800778e: e6ae b.n 80074ee <_dtoa_r+0x68e> 8007790: 2600 movs r6, #0 8007792: 4637 mov r7, r6 8007794: e7e1 b.n 800775a <_dtoa_r+0x8fa> 8007796: 46ba mov sl, r7 8007798: 4637 mov r7, r6 800779a: e5b1 b.n 8007300 <_dtoa_r+0x4a0> 800779c: 40240000 .word 0x40240000 80077a0: 9b09 ldr r3, [sp, #36] ; 0x24 80077a2: f8cd 8010 str.w r8, [sp, #16] 80077a6: 2b00 cmp r3, #0 80077a8: f000 80f3 beq.w 8007992 <_dtoa_r+0xb32> 80077ac: 2d00 cmp r5, #0 80077ae: dd05 ble.n 80077bc <_dtoa_r+0x95c> 80077b0: 4639 mov r1, r7 80077b2: 462a mov r2, r5 80077b4: 4620 mov r0, r4 80077b6: f000 fcd5 bl 8008164 <__lshift> 80077ba: 4607 mov r7, r0 80077bc: 9b08 ldr r3, [sp, #32] 80077be: 2b00 cmp r3, #0 80077c0: d04c beq.n 800785c <_dtoa_r+0x9fc> 80077c2: 6879 ldr r1, [r7, #4] 80077c4: 4620 mov r0, r4 80077c6: f000 fb0c bl 8007de2 <_Balloc> 80077ca: 4605 mov r5, r0 80077cc: 693a ldr r2, [r7, #16] 80077ce: f107 010c add.w r1, r7, #12 80077d2: 3202 adds r2, #2 80077d4: 0092 lsls r2, r2, #2 80077d6: 300c adds r0, #12 80077d8: f000 faf8 bl 8007dcc 80077dc: 2201 movs r2, #1 80077de: 4629 mov r1, r5 80077e0: 4620 mov r0, r4 80077e2: f000 fcbf bl 8008164 <__lshift> 80077e6: 46b9 mov r9, r7 80077e8: 4607 mov r7, r0 80077ea: 9b06 ldr r3, [sp, #24] 80077ec: 9307 str r3, [sp, #28] 80077ee: 9b02 ldr r3, [sp, #8] 80077f0: f003 0301 and.w r3, r3, #1 80077f4: 9308 str r3, [sp, #32] 80077f6: 4631 mov r1, r6 80077f8: 4658 mov r0, fp 80077fa: f7ff faa3 bl 8006d44 80077fe: 4649 mov r1, r9 8007800: 4605 mov r5, r0 8007802: f100 0830 add.w r8, r0, #48 ; 0x30 8007806: 4658 mov r0, fp 8007808: f000 fd00 bl 800820c <__mcmp> 800780c: 463a mov r2, r7 800780e: 9002 str r0, [sp, #8] 8007810: 4631 mov r1, r6 8007812: 4620 mov r0, r4 8007814: f000 fd14 bl 8008240 <__mdiff> 8007818: 68c3 ldr r3, [r0, #12] 800781a: 4602 mov r2, r0 800781c: bb03 cbnz r3, 8007860 <_dtoa_r+0xa00> 800781e: 4601 mov r1, r0 8007820: 9009 str r0, [sp, #36] ; 0x24 8007822: 4658 mov r0, fp 8007824: f000 fcf2 bl 800820c <__mcmp> 8007828: 4603 mov r3, r0 800782a: 9a09 ldr r2, [sp, #36] ; 0x24 800782c: 4611 mov r1, r2 800782e: 4620 mov r0, r4 8007830: 9309 str r3, [sp, #36] ; 0x24 8007832: f000 fb0a bl 8007e4a <_Bfree> 8007836: 9b09 ldr r3, [sp, #36] ; 0x24 8007838: b9a3 cbnz r3, 8007864 <_dtoa_r+0xa04> 800783a: 9a1e ldr r2, [sp, #120] ; 0x78 800783c: b992 cbnz r2, 8007864 <_dtoa_r+0xa04> 800783e: 9a08 ldr r2, [sp, #32] 8007840: b982 cbnz r2, 8007864 <_dtoa_r+0xa04> 8007842: f1b8 0f39 cmp.w r8, #57 ; 0x39 8007846: d029 beq.n 800789c <_dtoa_r+0xa3c> 8007848: 9b02 ldr r3, [sp, #8] 800784a: 2b00 cmp r3, #0 800784c: dd01 ble.n 8007852 <_dtoa_r+0x9f2> 800784e: f105 0831 add.w r8, r5, #49 ; 0x31 8007852: 9b07 ldr r3, [sp, #28] 8007854: 1c5d adds r5, r3, #1 8007856: f883 8000 strb.w r8, [r3] 800785a: e784 b.n 8007766 <_dtoa_r+0x906> 800785c: 4638 mov r0, r7 800785e: e7c2 b.n 80077e6 <_dtoa_r+0x986> 8007860: 2301 movs r3, #1 8007862: e7e3 b.n 800782c <_dtoa_r+0x9cc> 8007864: 9a02 ldr r2, [sp, #8] 8007866: 2a00 cmp r2, #0 8007868: db04 blt.n 8007874 <_dtoa_r+0xa14> 800786a: d123 bne.n 80078b4 <_dtoa_r+0xa54> 800786c: 9a1e ldr r2, [sp, #120] ; 0x78 800786e: bb0a cbnz r2, 80078b4 <_dtoa_r+0xa54> 8007870: 9a08 ldr r2, [sp, #32] 8007872: b9fa cbnz r2, 80078b4 <_dtoa_r+0xa54> 8007874: 2b00 cmp r3, #0 8007876: ddec ble.n 8007852 <_dtoa_r+0x9f2> 8007878: 4659 mov r1, fp 800787a: 2201 movs r2, #1 800787c: 4620 mov r0, r4 800787e: f000 fc71 bl 8008164 <__lshift> 8007882: 4631 mov r1, r6 8007884: 4683 mov fp, r0 8007886: f000 fcc1 bl 800820c <__mcmp> 800788a: 2800 cmp r0, #0 800788c: dc03 bgt.n 8007896 <_dtoa_r+0xa36> 800788e: d1e0 bne.n 8007852 <_dtoa_r+0x9f2> 8007890: f018 0f01 tst.w r8, #1 8007894: d0dd beq.n 8007852 <_dtoa_r+0x9f2> 8007896: f1b8 0f39 cmp.w r8, #57 ; 0x39 800789a: d1d8 bne.n 800784e <_dtoa_r+0x9ee> 800789c: 9b07 ldr r3, [sp, #28] 800789e: 9a07 ldr r2, [sp, #28] 80078a0: 1c5d adds r5, r3, #1 80078a2: 2339 movs r3, #57 ; 0x39 80078a4: 7013 strb r3, [r2, #0] 80078a6: f815 3c01 ldrb.w r3, [r5, #-1] 80078aa: 1e6a subs r2, r5, #1 80078ac: 2b39 cmp r3, #57 ; 0x39 80078ae: d04d beq.n 800794c <_dtoa_r+0xaec> 80078b0: 3301 adds r3, #1 80078b2: e052 b.n 800795a <_dtoa_r+0xafa> 80078b4: 9a07 ldr r2, [sp, #28] 80078b6: 2b00 cmp r3, #0 80078b8: f102 0501 add.w r5, r2, #1 80078bc: dd06 ble.n 80078cc <_dtoa_r+0xa6c> 80078be: f1b8 0f39 cmp.w r8, #57 ; 0x39 80078c2: d0eb beq.n 800789c <_dtoa_r+0xa3c> 80078c4: f108 0801 add.w r8, r8, #1 80078c8: 9b07 ldr r3, [sp, #28] 80078ca: e7c4 b.n 8007856 <_dtoa_r+0x9f6> 80078cc: 9b06 ldr r3, [sp, #24] 80078ce: 9a04 ldr r2, [sp, #16] 80078d0: 1aeb subs r3, r5, r3 80078d2: 4293 cmp r3, r2 80078d4: f805 8c01 strb.w r8, [r5, #-1] 80078d8: d021 beq.n 800791e <_dtoa_r+0xabe> 80078da: 4659 mov r1, fp 80078dc: 2300 movs r3, #0 80078de: 220a movs r2, #10 80078e0: 4620 mov r0, r4 80078e2: f000 fac9 bl 8007e78 <__multadd> 80078e6: 45b9 cmp r9, r7 80078e8: 4683 mov fp, r0 80078ea: f04f 0300 mov.w r3, #0 80078ee: f04f 020a mov.w r2, #10 80078f2: 4649 mov r1, r9 80078f4: 4620 mov r0, r4 80078f6: d105 bne.n 8007904 <_dtoa_r+0xaa4> 80078f8: f000 fabe bl 8007e78 <__multadd> 80078fc: 4681 mov r9, r0 80078fe: 4607 mov r7, r0 8007900: 9507 str r5, [sp, #28] 8007902: e778 b.n 80077f6 <_dtoa_r+0x996> 8007904: f000 fab8 bl 8007e78 <__multadd> 8007908: 4639 mov r1, r7 800790a: 4681 mov r9, r0 800790c: 2300 movs r3, #0 800790e: 220a movs r2, #10 8007910: 4620 mov r0, r4 8007912: f000 fab1 bl 8007e78 <__multadd> 8007916: 4607 mov r7, r0 8007918: e7f2 b.n 8007900 <_dtoa_r+0xaa0> 800791a: f04f 0900 mov.w r9, #0 800791e: 4659 mov r1, fp 8007920: 2201 movs r2, #1 8007922: 4620 mov r0, r4 8007924: f000 fc1e bl 8008164 <__lshift> 8007928: 4631 mov r1, r6 800792a: 4683 mov fp, r0 800792c: f000 fc6e bl 800820c <__mcmp> 8007930: 2800 cmp r0, #0 8007932: dcb8 bgt.n 80078a6 <_dtoa_r+0xa46> 8007934: d102 bne.n 800793c <_dtoa_r+0xadc> 8007936: f018 0f01 tst.w r8, #1 800793a: d1b4 bne.n 80078a6 <_dtoa_r+0xa46> 800793c: f815 3c01 ldrb.w r3, [r5, #-1] 8007940: 1e6a subs r2, r5, #1 8007942: 2b30 cmp r3, #48 ; 0x30 8007944: f47f af0f bne.w 8007766 <_dtoa_r+0x906> 8007948: 4615 mov r5, r2 800794a: e7f7 b.n 800793c <_dtoa_r+0xadc> 800794c: 9b06 ldr r3, [sp, #24] 800794e: 4293 cmp r3, r2 8007950: d105 bne.n 800795e <_dtoa_r+0xafe> 8007952: 2331 movs r3, #49 ; 0x31 8007954: 9a06 ldr r2, [sp, #24] 8007956: f10a 0a01 add.w sl, sl, #1 800795a: 7013 strb r3, [r2, #0] 800795c: e703 b.n 8007766 <_dtoa_r+0x906> 800795e: 4615 mov r5, r2 8007960: e7a1 b.n 80078a6 <_dtoa_r+0xa46> 8007962: 4b17 ldr r3, [pc, #92] ; (80079c0 <_dtoa_r+0xb60>) 8007964: f7ff bae1 b.w 8006f2a <_dtoa_r+0xca> 8007968: 9b22 ldr r3, [sp, #136] ; 0x88 800796a: 2b00 cmp r3, #0 800796c: f47f aabb bne.w 8006ee6 <_dtoa_r+0x86> 8007970: 4b14 ldr r3, [pc, #80] ; (80079c4 <_dtoa_r+0xb64>) 8007972: f7ff bada b.w 8006f2a <_dtoa_r+0xca> 8007976: 9b1e ldr r3, [sp, #120] ; 0x78 8007978: 2b01 cmp r3, #1 800797a: f77f ae3f ble.w 80075fc <_dtoa_r+0x79c> 800797e: 9b0c ldr r3, [sp, #48] ; 0x30 8007980: 9308 str r3, [sp, #32] 8007982: e653 b.n 800762c <_dtoa_r+0x7cc> 8007984: 9b04 ldr r3, [sp, #16] 8007986: 2b00 cmp r3, #0 8007988: dc03 bgt.n 8007992 <_dtoa_r+0xb32> 800798a: 9b1e ldr r3, [sp, #120] ; 0x78 800798c: 2b02 cmp r3, #2 800798e: f73f aed5 bgt.w 800773c <_dtoa_r+0x8dc> 8007992: 9d06 ldr r5, [sp, #24] 8007994: 4631 mov r1, r6 8007996: 4658 mov r0, fp 8007998: f7ff f9d4 bl 8006d44 800799c: 9b06 ldr r3, [sp, #24] 800799e: f100 0830 add.w r8, r0, #48 ; 0x30 80079a2: f805 8b01 strb.w r8, [r5], #1 80079a6: 9a04 ldr r2, [sp, #16] 80079a8: 1aeb subs r3, r5, r3 80079aa: 429a cmp r2, r3 80079ac: ddb5 ble.n 800791a <_dtoa_r+0xaba> 80079ae: 4659 mov r1, fp 80079b0: 2300 movs r3, #0 80079b2: 220a movs r2, #10 80079b4: 4620 mov r0, r4 80079b6: f000 fa5f bl 8007e78 <__multadd> 80079ba: 4683 mov fp, r0 80079bc: e7ea b.n 8007994 <_dtoa_r+0xb34> 80079be: bf00 nop 80079c0: 08008d18 .word 0x08008d18 80079c4: 08008d3c .word 0x08008d3c 080079c8 <__sflush_r>: 80079c8: 898a ldrh r2, [r1, #12] 80079ca: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 80079ce: 4605 mov r5, r0 80079d0: 0710 lsls r0, r2, #28 80079d2: 460c mov r4, r1 80079d4: d458 bmi.n 8007a88 <__sflush_r+0xc0> 80079d6: 684b ldr r3, [r1, #4] 80079d8: 2b00 cmp r3, #0 80079da: dc05 bgt.n 80079e8 <__sflush_r+0x20> 80079dc: 6c0b ldr r3, [r1, #64] ; 0x40 80079de: 2b00 cmp r3, #0 80079e0: dc02 bgt.n 80079e8 <__sflush_r+0x20> 80079e2: 2000 movs r0, #0 80079e4: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 80079e8: 6ae6 ldr r6, [r4, #44] ; 0x2c 80079ea: 2e00 cmp r6, #0 80079ec: d0f9 beq.n 80079e2 <__sflush_r+0x1a> 80079ee: 2300 movs r3, #0 80079f0: f412 5280 ands.w r2, r2, #4096 ; 0x1000 80079f4: 682f ldr r7, [r5, #0] 80079f6: 6a21 ldr r1, [r4, #32] 80079f8: 602b str r3, [r5, #0] 80079fa: d032 beq.n 8007a62 <__sflush_r+0x9a> 80079fc: 6d60 ldr r0, [r4, #84] ; 0x54 80079fe: 89a3 ldrh r3, [r4, #12] 8007a00: 075a lsls r2, r3, #29 8007a02: d505 bpl.n 8007a10 <__sflush_r+0x48> 8007a04: 6863 ldr r3, [r4, #4] 8007a06: 1ac0 subs r0, r0, r3 8007a08: 6b63 ldr r3, [r4, #52] ; 0x34 8007a0a: b10b cbz r3, 8007a10 <__sflush_r+0x48> 8007a0c: 6c23 ldr r3, [r4, #64] ; 0x40 8007a0e: 1ac0 subs r0, r0, r3 8007a10: 2300 movs r3, #0 8007a12: 4602 mov r2, r0 8007a14: 6ae6 ldr r6, [r4, #44] ; 0x2c 8007a16: 6a21 ldr r1, [r4, #32] 8007a18: 4628 mov r0, r5 8007a1a: 47b0 blx r6 8007a1c: 1c43 adds r3, r0, #1 8007a1e: 89a3 ldrh r3, [r4, #12] 8007a20: d106 bne.n 8007a30 <__sflush_r+0x68> 8007a22: 6829 ldr r1, [r5, #0] 8007a24: 291d cmp r1, #29 8007a26: d848 bhi.n 8007aba <__sflush_r+0xf2> 8007a28: 4a29 ldr r2, [pc, #164] ; (8007ad0 <__sflush_r+0x108>) 8007a2a: 40ca lsrs r2, r1 8007a2c: 07d6 lsls r6, r2, #31 8007a2e: d544 bpl.n 8007aba <__sflush_r+0xf2> 8007a30: 2200 movs r2, #0 8007a32: 6062 str r2, [r4, #4] 8007a34: 6922 ldr r2, [r4, #16] 8007a36: 04d9 lsls r1, r3, #19 8007a38: 6022 str r2, [r4, #0] 8007a3a: d504 bpl.n 8007a46 <__sflush_r+0x7e> 8007a3c: 1c42 adds r2, r0, #1 8007a3e: d101 bne.n 8007a44 <__sflush_r+0x7c> 8007a40: 682b ldr r3, [r5, #0] 8007a42: b903 cbnz r3, 8007a46 <__sflush_r+0x7e> 8007a44: 6560 str r0, [r4, #84] ; 0x54 8007a46: 6b61 ldr r1, [r4, #52] ; 0x34 8007a48: 602f str r7, [r5, #0] 8007a4a: 2900 cmp r1, #0 8007a4c: d0c9 beq.n 80079e2 <__sflush_r+0x1a> 8007a4e: f104 0344 add.w r3, r4, #68 ; 0x44 8007a52: 4299 cmp r1, r3 8007a54: d002 beq.n 8007a5c <__sflush_r+0x94> 8007a56: 4628 mov r0, r5 8007a58: f000 fcae bl 80083b8 <_free_r> 8007a5c: 2000 movs r0, #0 8007a5e: 6360 str r0, [r4, #52] ; 0x34 8007a60: e7c0 b.n 80079e4 <__sflush_r+0x1c> 8007a62: 2301 movs r3, #1 8007a64: 4628 mov r0, r5 8007a66: 47b0 blx r6 8007a68: 1c41 adds r1, r0, #1 8007a6a: d1c8 bne.n 80079fe <__sflush_r+0x36> 8007a6c: 682b ldr r3, [r5, #0] 8007a6e: 2b00 cmp r3, #0 8007a70: d0c5 beq.n 80079fe <__sflush_r+0x36> 8007a72: 2b1d cmp r3, #29 8007a74: d001 beq.n 8007a7a <__sflush_r+0xb2> 8007a76: 2b16 cmp r3, #22 8007a78: d101 bne.n 8007a7e <__sflush_r+0xb6> 8007a7a: 602f str r7, [r5, #0] 8007a7c: e7b1 b.n 80079e2 <__sflush_r+0x1a> 8007a7e: 89a3 ldrh r3, [r4, #12] 8007a80: f043 0340 orr.w r3, r3, #64 ; 0x40 8007a84: 81a3 strh r3, [r4, #12] 8007a86: e7ad b.n 80079e4 <__sflush_r+0x1c> 8007a88: 690f ldr r7, [r1, #16] 8007a8a: 2f00 cmp r7, #0 8007a8c: d0a9 beq.n 80079e2 <__sflush_r+0x1a> 8007a8e: 0793 lsls r3, r2, #30 8007a90: bf18 it ne 8007a92: 2300 movne r3, #0 8007a94: 680e ldr r6, [r1, #0] 8007a96: bf08 it eq 8007a98: 694b ldreq r3, [r1, #20] 8007a9a: eba6 0807 sub.w r8, r6, r7 8007a9e: 600f str r7, [r1, #0] 8007aa0: 608b str r3, [r1, #8] 8007aa2: f1b8 0f00 cmp.w r8, #0 8007aa6: dd9c ble.n 80079e2 <__sflush_r+0x1a> 8007aa8: 4643 mov r3, r8 8007aaa: 463a mov r2, r7 8007aac: 6a21 ldr r1, [r4, #32] 8007aae: 4628 mov r0, r5 8007ab0: 6aa6 ldr r6, [r4, #40] ; 0x28 8007ab2: 47b0 blx r6 8007ab4: 2800 cmp r0, #0 8007ab6: dc06 bgt.n 8007ac6 <__sflush_r+0xfe> 8007ab8: 89a3 ldrh r3, [r4, #12] 8007aba: f043 0340 orr.w r3, r3, #64 ; 0x40 8007abe: 81a3 strh r3, [r4, #12] 8007ac0: f04f 30ff mov.w r0, #4294967295 8007ac4: e78e b.n 80079e4 <__sflush_r+0x1c> 8007ac6: 4407 add r7, r0 8007ac8: eba8 0800 sub.w r8, r8, r0 8007acc: e7e9 b.n 8007aa2 <__sflush_r+0xda> 8007ace: bf00 nop 8007ad0: 20400001 .word 0x20400001 08007ad4 <_fflush_r>: 8007ad4: b538 push {r3, r4, r5, lr} 8007ad6: 690b ldr r3, [r1, #16] 8007ad8: 4605 mov r5, r0 8007ada: 460c mov r4, r1 8007adc: b1db cbz r3, 8007b16 <_fflush_r+0x42> 8007ade: b118 cbz r0, 8007ae8 <_fflush_r+0x14> 8007ae0: 6983 ldr r3, [r0, #24] 8007ae2: b90b cbnz r3, 8007ae8 <_fflush_r+0x14> 8007ae4: f000 f860 bl 8007ba8 <__sinit> 8007ae8: 4b0c ldr r3, [pc, #48] ; (8007b1c <_fflush_r+0x48>) 8007aea: 429c cmp r4, r3 8007aec: d109 bne.n 8007b02 <_fflush_r+0x2e> 8007aee: 686c ldr r4, [r5, #4] 8007af0: f9b4 300c ldrsh.w r3, [r4, #12] 8007af4: b17b cbz r3, 8007b16 <_fflush_r+0x42> 8007af6: 4621 mov r1, r4 8007af8: 4628 mov r0, r5 8007afa: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 8007afe: f7ff bf63 b.w 80079c8 <__sflush_r> 8007b02: 4b07 ldr r3, [pc, #28] ; (8007b20 <_fflush_r+0x4c>) 8007b04: 429c cmp r4, r3 8007b06: d101 bne.n 8007b0c <_fflush_r+0x38> 8007b08: 68ac ldr r4, [r5, #8] 8007b0a: e7f1 b.n 8007af0 <_fflush_r+0x1c> 8007b0c: 4b05 ldr r3, [pc, #20] ; (8007b24 <_fflush_r+0x50>) 8007b0e: 429c cmp r4, r3 8007b10: bf08 it eq 8007b12: 68ec ldreq r4, [r5, #12] 8007b14: e7ec b.n 8007af0 <_fflush_r+0x1c> 8007b16: 2000 movs r0, #0 8007b18: bd38 pop {r3, r4, r5, pc} 8007b1a: bf00 nop 8007b1c: 08008d6c .word 0x08008d6c 8007b20: 08008d8c .word 0x08008d8c 8007b24: 08008d4c .word 0x08008d4c 08007b28 : 8007b28: 2300 movs r3, #0 8007b2a: b510 push {r4, lr} 8007b2c: 4604 mov r4, r0 8007b2e: e9c0 3300 strd r3, r3, [r0] 8007b32: 6083 str r3, [r0, #8] 8007b34: 8181 strh r1, [r0, #12] 8007b36: 6643 str r3, [r0, #100] ; 0x64 8007b38: 81c2 strh r2, [r0, #14] 8007b3a: e9c0 3304 strd r3, r3, [r0, #16] 8007b3e: 6183 str r3, [r0, #24] 8007b40: 4619 mov r1, r3 8007b42: 2208 movs r2, #8 8007b44: 305c adds r0, #92 ; 0x5c 8007b46: f7fe fab3 bl 80060b0 8007b4a: 4b05 ldr r3, [pc, #20] ; (8007b60 ) 8007b4c: 6224 str r4, [r4, #32] 8007b4e: 6263 str r3, [r4, #36] ; 0x24 8007b50: 4b04 ldr r3, [pc, #16] ; (8007b64 ) 8007b52: 62a3 str r3, [r4, #40] ; 0x28 8007b54: 4b04 ldr r3, [pc, #16] ; (8007b68 ) 8007b56: 62e3 str r3, [r4, #44] ; 0x2c 8007b58: 4b04 ldr r3, [pc, #16] ; (8007b6c ) 8007b5a: 6323 str r3, [r4, #48] ; 0x30 8007b5c: bd10 pop {r4, pc} 8007b5e: bf00 nop 8007b60: 080087a1 .word 0x080087a1 8007b64: 080087c3 .word 0x080087c3 8007b68: 080087fb .word 0x080087fb 8007b6c: 0800881f .word 0x0800881f 08007b70 <_cleanup_r>: 8007b70: 4901 ldr r1, [pc, #4] ; (8007b78 <_cleanup_r+0x8>) 8007b72: f000 b885 b.w 8007c80 <_fwalk_reent> 8007b76: bf00 nop 8007b78: 08007ad5 .word 0x08007ad5 08007b7c <__sfmoreglue>: 8007b7c: b570 push {r4, r5, r6, lr} 8007b7e: 2568 movs r5, #104 ; 0x68 8007b80: 1e4a subs r2, r1, #1 8007b82: 4355 muls r5, r2 8007b84: 460e mov r6, r1 8007b86: f105 0174 add.w r1, r5, #116 ; 0x74 8007b8a: f000 fc61 bl 8008450 <_malloc_r> 8007b8e: 4604 mov r4, r0 8007b90: b140 cbz r0, 8007ba4 <__sfmoreglue+0x28> 8007b92: 2100 movs r1, #0 8007b94: e9c0 1600 strd r1, r6, [r0] 8007b98: 300c adds r0, #12 8007b9a: 60a0 str r0, [r4, #8] 8007b9c: f105 0268 add.w r2, r5, #104 ; 0x68 8007ba0: f7fe fa86 bl 80060b0 8007ba4: 4620 mov r0, r4 8007ba6: bd70 pop {r4, r5, r6, pc} 08007ba8 <__sinit>: 8007ba8: 6983 ldr r3, [r0, #24] 8007baa: b510 push {r4, lr} 8007bac: 4604 mov r4, r0 8007bae: bb33 cbnz r3, 8007bfe <__sinit+0x56> 8007bb0: e9c0 3312 strd r3, r3, [r0, #72] ; 0x48 8007bb4: 6503 str r3, [r0, #80] ; 0x50 8007bb6: 4b12 ldr r3, [pc, #72] ; (8007c00 <__sinit+0x58>) 8007bb8: 4a12 ldr r2, [pc, #72] ; (8007c04 <__sinit+0x5c>) 8007bba: 681b ldr r3, [r3, #0] 8007bbc: 6282 str r2, [r0, #40] ; 0x28 8007bbe: 4298 cmp r0, r3 8007bc0: bf04 itt eq 8007bc2: 2301 moveq r3, #1 8007bc4: 6183 streq r3, [r0, #24] 8007bc6: f000 f81f bl 8007c08 <__sfp> 8007bca: 6060 str r0, [r4, #4] 8007bcc: 4620 mov r0, r4 8007bce: f000 f81b bl 8007c08 <__sfp> 8007bd2: 60a0 str r0, [r4, #8] 8007bd4: 4620 mov r0, r4 8007bd6: f000 f817 bl 8007c08 <__sfp> 8007bda: 2200 movs r2, #0 8007bdc: 60e0 str r0, [r4, #12] 8007bde: 2104 movs r1, #4 8007be0: 6860 ldr r0, [r4, #4] 8007be2: f7ff ffa1 bl 8007b28 8007be6: 2201 movs r2, #1 8007be8: 2109 movs r1, #9 8007bea: 68a0 ldr r0, [r4, #8] 8007bec: f7ff ff9c bl 8007b28 8007bf0: 2202 movs r2, #2 8007bf2: 2112 movs r1, #18 8007bf4: 68e0 ldr r0, [r4, #12] 8007bf6: f7ff ff97 bl 8007b28 8007bfa: 2301 movs r3, #1 8007bfc: 61a3 str r3, [r4, #24] 8007bfe: bd10 pop {r4, pc} 8007c00: 08008d04 .word 0x08008d04 8007c04: 08007b71 .word 0x08007b71 08007c08 <__sfp>: 8007c08: b5f8 push {r3, r4, r5, r6, r7, lr} 8007c0a: 4b1b ldr r3, [pc, #108] ; (8007c78 <__sfp+0x70>) 8007c0c: 4607 mov r7, r0 8007c0e: 681e ldr r6, [r3, #0] 8007c10: 69b3 ldr r3, [r6, #24] 8007c12: b913 cbnz r3, 8007c1a <__sfp+0x12> 8007c14: 4630 mov r0, r6 8007c16: f7ff ffc7 bl 8007ba8 <__sinit> 8007c1a: 3648 adds r6, #72 ; 0x48 8007c1c: e9d6 3401 ldrd r3, r4, [r6, #4] 8007c20: 3b01 subs r3, #1 8007c22: d503 bpl.n 8007c2c <__sfp+0x24> 8007c24: 6833 ldr r3, [r6, #0] 8007c26: b133 cbz r3, 8007c36 <__sfp+0x2e> 8007c28: 6836 ldr r6, [r6, #0] 8007c2a: e7f7 b.n 8007c1c <__sfp+0x14> 8007c2c: f9b4 500c ldrsh.w r5, [r4, #12] 8007c30: b16d cbz r5, 8007c4e <__sfp+0x46> 8007c32: 3468 adds r4, #104 ; 0x68 8007c34: e7f4 b.n 8007c20 <__sfp+0x18> 8007c36: 2104 movs r1, #4 8007c38: 4638 mov r0, r7 8007c3a: f7ff ff9f bl 8007b7c <__sfmoreglue> 8007c3e: 6030 str r0, [r6, #0] 8007c40: 2800 cmp r0, #0 8007c42: d1f1 bne.n 8007c28 <__sfp+0x20> 8007c44: 230c movs r3, #12 8007c46: 4604 mov r4, r0 8007c48: 603b str r3, [r7, #0] 8007c4a: 4620 mov r0, r4 8007c4c: bdf8 pop {r3, r4, r5, r6, r7, pc} 8007c4e: 4b0b ldr r3, [pc, #44] ; (8007c7c <__sfp+0x74>) 8007c50: 6665 str r5, [r4, #100] ; 0x64 8007c52: e9c4 5500 strd r5, r5, [r4] 8007c56: 60a5 str r5, [r4, #8] 8007c58: e9c4 3503 strd r3, r5, [r4, #12] 8007c5c: e9c4 5505 strd r5, r5, [r4, #20] 8007c60: 2208 movs r2, #8 8007c62: 4629 mov r1, r5 8007c64: f104 005c add.w r0, r4, #92 ; 0x5c 8007c68: f7fe fa22 bl 80060b0 8007c6c: e9c4 550d strd r5, r5, [r4, #52] ; 0x34 8007c70: e9c4 5512 strd r5, r5, [r4, #72] ; 0x48 8007c74: e7e9 b.n 8007c4a <__sfp+0x42> 8007c76: bf00 nop 8007c78: 08008d04 .word 0x08008d04 8007c7c: ffff0001 .word 0xffff0001 08007c80 <_fwalk_reent>: 8007c80: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 8007c84: 4680 mov r8, r0 8007c86: 4689 mov r9, r1 8007c88: 2600 movs r6, #0 8007c8a: f100 0448 add.w r4, r0, #72 ; 0x48 8007c8e: b914 cbnz r4, 8007c96 <_fwalk_reent+0x16> 8007c90: 4630 mov r0, r6 8007c92: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 8007c96: e9d4 7501 ldrd r7, r5, [r4, #4] 8007c9a: 3f01 subs r7, #1 8007c9c: d501 bpl.n 8007ca2 <_fwalk_reent+0x22> 8007c9e: 6824 ldr r4, [r4, #0] 8007ca0: e7f5 b.n 8007c8e <_fwalk_reent+0xe> 8007ca2: 89ab ldrh r3, [r5, #12] 8007ca4: 2b01 cmp r3, #1 8007ca6: d907 bls.n 8007cb8 <_fwalk_reent+0x38> 8007ca8: f9b5 300e ldrsh.w r3, [r5, #14] 8007cac: 3301 adds r3, #1 8007cae: d003 beq.n 8007cb8 <_fwalk_reent+0x38> 8007cb0: 4629 mov r1, r5 8007cb2: 4640 mov r0, r8 8007cb4: 47c8 blx r9 8007cb6: 4306 orrs r6, r0 8007cb8: 3568 adds r5, #104 ; 0x68 8007cba: e7ee b.n 8007c9a <_fwalk_reent+0x1a> 08007cbc <_localeconv_r>: 8007cbc: 4b04 ldr r3, [pc, #16] ; (8007cd0 <_localeconv_r+0x14>) 8007cbe: 681b ldr r3, [r3, #0] 8007cc0: 6a18 ldr r0, [r3, #32] 8007cc2: 4b04 ldr r3, [pc, #16] ; (8007cd4 <_localeconv_r+0x18>) 8007cc4: 2800 cmp r0, #0 8007cc6: bf08 it eq 8007cc8: 4618 moveq r0, r3 8007cca: 30f0 adds r0, #240 ; 0xf0 8007ccc: 4770 bx lr 8007cce: bf00 nop 8007cd0: 2000000c .word 0x2000000c 8007cd4: 20000070 .word 0x20000070 08007cd8 <__swhatbuf_r>: 8007cd8: b570 push {r4, r5, r6, lr} 8007cda: 460e mov r6, r1 8007cdc: f9b1 100e ldrsh.w r1, [r1, #14] 8007ce0: b096 sub sp, #88 ; 0x58 8007ce2: 2900 cmp r1, #0 8007ce4: 4614 mov r4, r2 8007ce6: 461d mov r5, r3 8007ce8: da07 bge.n 8007cfa <__swhatbuf_r+0x22> 8007cea: 2300 movs r3, #0 8007cec: 602b str r3, [r5, #0] 8007cee: 89b3 ldrh r3, [r6, #12] 8007cf0: 061a lsls r2, r3, #24 8007cf2: d410 bmi.n 8007d16 <__swhatbuf_r+0x3e> 8007cf4: f44f 6380 mov.w r3, #1024 ; 0x400 8007cf8: e00e b.n 8007d18 <__swhatbuf_r+0x40> 8007cfa: 466a mov r2, sp 8007cfc: f000 fdb6 bl 800886c <_fstat_r> 8007d00: 2800 cmp r0, #0 8007d02: dbf2 blt.n 8007cea <__swhatbuf_r+0x12> 8007d04: 9a01 ldr r2, [sp, #4] 8007d06: f402 4270 and.w r2, r2, #61440 ; 0xf000 8007d0a: f5a2 5300 sub.w r3, r2, #8192 ; 0x2000 8007d0e: 425a negs r2, r3 8007d10: 415a adcs r2, r3 8007d12: 602a str r2, [r5, #0] 8007d14: e7ee b.n 8007cf4 <__swhatbuf_r+0x1c> 8007d16: 2340 movs r3, #64 ; 0x40 8007d18: 2000 movs r0, #0 8007d1a: 6023 str r3, [r4, #0] 8007d1c: b016 add sp, #88 ; 0x58 8007d1e: bd70 pop {r4, r5, r6, pc} 08007d20 <__smakebuf_r>: 8007d20: 898b ldrh r3, [r1, #12] 8007d22: b573 push {r0, r1, r4, r5, r6, lr} 8007d24: 079d lsls r5, r3, #30 8007d26: 4606 mov r6, r0 8007d28: 460c mov r4, r1 8007d2a: d507 bpl.n 8007d3c <__smakebuf_r+0x1c> 8007d2c: f104 0347 add.w r3, r4, #71 ; 0x47 8007d30: 6023 str r3, [r4, #0] 8007d32: 6123 str r3, [r4, #16] 8007d34: 2301 movs r3, #1 8007d36: 6163 str r3, [r4, #20] 8007d38: b002 add sp, #8 8007d3a: bd70 pop {r4, r5, r6, pc} 8007d3c: ab01 add r3, sp, #4 8007d3e: 466a mov r2, sp 8007d40: f7ff ffca bl 8007cd8 <__swhatbuf_r> 8007d44: 9900 ldr r1, [sp, #0] 8007d46: 4605 mov r5, r0 8007d48: 4630 mov r0, r6 8007d4a: f000 fb81 bl 8008450 <_malloc_r> 8007d4e: b948 cbnz r0, 8007d64 <__smakebuf_r+0x44> 8007d50: f9b4 300c ldrsh.w r3, [r4, #12] 8007d54: 059a lsls r2, r3, #22 8007d56: d4ef bmi.n 8007d38 <__smakebuf_r+0x18> 8007d58: f023 0303 bic.w r3, r3, #3 8007d5c: f043 0302 orr.w r3, r3, #2 8007d60: 81a3 strh r3, [r4, #12] 8007d62: e7e3 b.n 8007d2c <__smakebuf_r+0xc> 8007d64: 4b0d ldr r3, [pc, #52] ; (8007d9c <__smakebuf_r+0x7c>) 8007d66: 62b3 str r3, [r6, #40] ; 0x28 8007d68: 89a3 ldrh r3, [r4, #12] 8007d6a: 6020 str r0, [r4, #0] 8007d6c: f043 0380 orr.w r3, r3, #128 ; 0x80 8007d70: 81a3 strh r3, [r4, #12] 8007d72: 9b00 ldr r3, [sp, #0] 8007d74: 6120 str r0, [r4, #16] 8007d76: 6163 str r3, [r4, #20] 8007d78: 9b01 ldr r3, [sp, #4] 8007d7a: b15b cbz r3, 8007d94 <__smakebuf_r+0x74> 8007d7c: f9b4 100e ldrsh.w r1, [r4, #14] 8007d80: 4630 mov r0, r6 8007d82: f000 fd85 bl 8008890 <_isatty_r> 8007d86: b128 cbz r0, 8007d94 <__smakebuf_r+0x74> 8007d88: 89a3 ldrh r3, [r4, #12] 8007d8a: f023 0303 bic.w r3, r3, #3 8007d8e: f043 0301 orr.w r3, r3, #1 8007d92: 81a3 strh r3, [r4, #12] 8007d94: 89a3 ldrh r3, [r4, #12] 8007d96: 431d orrs r5, r3 8007d98: 81a5 strh r5, [r4, #12] 8007d9a: e7cd b.n 8007d38 <__smakebuf_r+0x18> 8007d9c: 08007b71 .word 0x08007b71 08007da0 : 8007da0: 4b02 ldr r3, [pc, #8] ; (8007dac ) 8007da2: 4601 mov r1, r0 8007da4: 6818 ldr r0, [r3, #0] 8007da6: f000 bb53 b.w 8008450 <_malloc_r> 8007daa: bf00 nop 8007dac: 2000000c .word 0x2000000c 08007db0 : 8007db0: b510 push {r4, lr} 8007db2: b2c9 uxtb r1, r1 8007db4: 4402 add r2, r0 8007db6: 4290 cmp r0, r2 8007db8: 4603 mov r3, r0 8007dba: d101 bne.n 8007dc0 8007dbc: 2300 movs r3, #0 8007dbe: e003 b.n 8007dc8 8007dc0: 781c ldrb r4, [r3, #0] 8007dc2: 3001 adds r0, #1 8007dc4: 428c cmp r4, r1 8007dc6: d1f6 bne.n 8007db6 8007dc8: 4618 mov r0, r3 8007dca: bd10 pop {r4, pc} 08007dcc : 8007dcc: b510 push {r4, lr} 8007dce: 1e43 subs r3, r0, #1 8007dd0: 440a add r2, r1 8007dd2: 4291 cmp r1, r2 8007dd4: d100 bne.n 8007dd8 8007dd6: bd10 pop {r4, pc} 8007dd8: f811 4b01 ldrb.w r4, [r1], #1 8007ddc: f803 4f01 strb.w r4, [r3, #1]! 8007de0: e7f7 b.n 8007dd2 08007de2 <_Balloc>: 8007de2: b570 push {r4, r5, r6, lr} 8007de4: 6a45 ldr r5, [r0, #36] ; 0x24 8007de6: 4604 mov r4, r0 8007de8: 460e mov r6, r1 8007dea: b93d cbnz r5, 8007dfc <_Balloc+0x1a> 8007dec: 2010 movs r0, #16 8007dee: f7ff ffd7 bl 8007da0 8007df2: 6260 str r0, [r4, #36] ; 0x24 8007df4: e9c0 5501 strd r5, r5, [r0, #4] 8007df8: 6005 str r5, [r0, #0] 8007dfa: 60c5 str r5, [r0, #12] 8007dfc: 6a65 ldr r5, [r4, #36] ; 0x24 8007dfe: 68eb ldr r3, [r5, #12] 8007e00: b183 cbz r3, 8007e24 <_Balloc+0x42> 8007e02: 6a63 ldr r3, [r4, #36] ; 0x24 8007e04: 68db ldr r3, [r3, #12] 8007e06: f853 0026 ldr.w r0, [r3, r6, lsl #2] 8007e0a: b9b8 cbnz r0, 8007e3c <_Balloc+0x5a> 8007e0c: 2101 movs r1, #1 8007e0e: fa01 f506 lsl.w r5, r1, r6 8007e12: 1d6a adds r2, r5, #5 8007e14: 0092 lsls r2, r2, #2 8007e16: 4620 mov r0, r4 8007e18: f000 fabf bl 800839a <_calloc_r> 8007e1c: b160 cbz r0, 8007e38 <_Balloc+0x56> 8007e1e: e9c0 6501 strd r6, r5, [r0, #4] 8007e22: e00e b.n 8007e42 <_Balloc+0x60> 8007e24: 2221 movs r2, #33 ; 0x21 8007e26: 2104 movs r1, #4 8007e28: 4620 mov r0, r4 8007e2a: f000 fab6 bl 800839a <_calloc_r> 8007e2e: 6a63 ldr r3, [r4, #36] ; 0x24 8007e30: 60e8 str r0, [r5, #12] 8007e32: 68db ldr r3, [r3, #12] 8007e34: 2b00 cmp r3, #0 8007e36: d1e4 bne.n 8007e02 <_Balloc+0x20> 8007e38: 2000 movs r0, #0 8007e3a: bd70 pop {r4, r5, r6, pc} 8007e3c: 6802 ldr r2, [r0, #0] 8007e3e: f843 2026 str.w r2, [r3, r6, lsl #2] 8007e42: 2300 movs r3, #0 8007e44: e9c0 3303 strd r3, r3, [r0, #12] 8007e48: e7f7 b.n 8007e3a <_Balloc+0x58> 08007e4a <_Bfree>: 8007e4a: b570 push {r4, r5, r6, lr} 8007e4c: 6a44 ldr r4, [r0, #36] ; 0x24 8007e4e: 4606 mov r6, r0 8007e50: 460d mov r5, r1 8007e52: b93c cbnz r4, 8007e64 <_Bfree+0x1a> 8007e54: 2010 movs r0, #16 8007e56: f7ff ffa3 bl 8007da0 8007e5a: 6270 str r0, [r6, #36] ; 0x24 8007e5c: e9c0 4401 strd r4, r4, [r0, #4] 8007e60: 6004 str r4, [r0, #0] 8007e62: 60c4 str r4, [r0, #12] 8007e64: b13d cbz r5, 8007e76 <_Bfree+0x2c> 8007e66: 6a73 ldr r3, [r6, #36] ; 0x24 8007e68: 686a ldr r2, [r5, #4] 8007e6a: 68db ldr r3, [r3, #12] 8007e6c: f853 1022 ldr.w r1, [r3, r2, lsl #2] 8007e70: 6029 str r1, [r5, #0] 8007e72: f843 5022 str.w r5, [r3, r2, lsl #2] 8007e76: bd70 pop {r4, r5, r6, pc} 08007e78 <__multadd>: 8007e78: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 8007e7c: 461f mov r7, r3 8007e7e: 4606 mov r6, r0 8007e80: 460c mov r4, r1 8007e82: 2300 movs r3, #0 8007e84: 690d ldr r5, [r1, #16] 8007e86: f101 0c14 add.w ip, r1, #20 8007e8a: f8dc 0000 ldr.w r0, [ip] 8007e8e: 3301 adds r3, #1 8007e90: b281 uxth r1, r0 8007e92: fb02 7101 mla r1, r2, r1, r7 8007e96: 0c00 lsrs r0, r0, #16 8007e98: 0c0f lsrs r7, r1, #16 8007e9a: fb02 7000 mla r0, r2, r0, r7 8007e9e: b289 uxth r1, r1 8007ea0: eb01 4100 add.w r1, r1, r0, lsl #16 8007ea4: 429d cmp r5, r3 8007ea6: ea4f 4710 mov.w r7, r0, lsr #16 8007eaa: f84c 1b04 str.w r1, [ip], #4 8007eae: dcec bgt.n 8007e8a <__multadd+0x12> 8007eb0: b1d7 cbz r7, 8007ee8 <__multadd+0x70> 8007eb2: 68a3 ldr r3, [r4, #8] 8007eb4: 42ab cmp r3, r5 8007eb6: dc12 bgt.n 8007ede <__multadd+0x66> 8007eb8: 6861 ldr r1, [r4, #4] 8007eba: 4630 mov r0, r6 8007ebc: 3101 adds r1, #1 8007ebe: f7ff ff90 bl 8007de2 <_Balloc> 8007ec2: 4680 mov r8, r0 8007ec4: 6922 ldr r2, [r4, #16] 8007ec6: f104 010c add.w r1, r4, #12 8007eca: 3202 adds r2, #2 8007ecc: 0092 lsls r2, r2, #2 8007ece: 300c adds r0, #12 8007ed0: f7ff ff7c bl 8007dcc 8007ed4: 4621 mov r1, r4 8007ed6: 4630 mov r0, r6 8007ed8: f7ff ffb7 bl 8007e4a <_Bfree> 8007edc: 4644 mov r4, r8 8007ede: eb04 0385 add.w r3, r4, r5, lsl #2 8007ee2: 3501 adds r5, #1 8007ee4: 615f str r7, [r3, #20] 8007ee6: 6125 str r5, [r4, #16] 8007ee8: 4620 mov r0, r4 8007eea: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 08007eee <__hi0bits>: 8007eee: 0c02 lsrs r2, r0, #16 8007ef0: 0412 lsls r2, r2, #16 8007ef2: 4603 mov r3, r0 8007ef4: b9b2 cbnz r2, 8007f24 <__hi0bits+0x36> 8007ef6: 0403 lsls r3, r0, #16 8007ef8: 2010 movs r0, #16 8007efa: f013 4f7f tst.w r3, #4278190080 ; 0xff000000 8007efe: bf04 itt eq 8007f00: 021b lsleq r3, r3, #8 8007f02: 3008 addeq r0, #8 8007f04: f013 4f70 tst.w r3, #4026531840 ; 0xf0000000 8007f08: bf04 itt eq 8007f0a: 011b lsleq r3, r3, #4 8007f0c: 3004 addeq r0, #4 8007f0e: f013 4f40 tst.w r3, #3221225472 ; 0xc0000000 8007f12: bf04 itt eq 8007f14: 009b lsleq r3, r3, #2 8007f16: 3002 addeq r0, #2 8007f18: 2b00 cmp r3, #0 8007f1a: db06 blt.n 8007f2a <__hi0bits+0x3c> 8007f1c: 005b lsls r3, r3, #1 8007f1e: d503 bpl.n 8007f28 <__hi0bits+0x3a> 8007f20: 3001 adds r0, #1 8007f22: 4770 bx lr 8007f24: 2000 movs r0, #0 8007f26: e7e8 b.n 8007efa <__hi0bits+0xc> 8007f28: 2020 movs r0, #32 8007f2a: 4770 bx lr 08007f2c <__lo0bits>: 8007f2c: 6803 ldr r3, [r0, #0] 8007f2e: 4601 mov r1, r0 8007f30: f013 0207 ands.w r2, r3, #7 8007f34: d00b beq.n 8007f4e <__lo0bits+0x22> 8007f36: 07da lsls r2, r3, #31 8007f38: d423 bmi.n 8007f82 <__lo0bits+0x56> 8007f3a: 0798 lsls r0, r3, #30 8007f3c: bf49 itett mi 8007f3e: 085b lsrmi r3, r3, #1 8007f40: 089b lsrpl r3, r3, #2 8007f42: 2001 movmi r0, #1 8007f44: 600b strmi r3, [r1, #0] 8007f46: bf5c itt pl 8007f48: 600b strpl r3, [r1, #0] 8007f4a: 2002 movpl r0, #2 8007f4c: 4770 bx lr 8007f4e: b298 uxth r0, r3 8007f50: b9a8 cbnz r0, 8007f7e <__lo0bits+0x52> 8007f52: 2010 movs r0, #16 8007f54: 0c1b lsrs r3, r3, #16 8007f56: f013 0fff tst.w r3, #255 ; 0xff 8007f5a: bf04 itt eq 8007f5c: 0a1b lsreq r3, r3, #8 8007f5e: 3008 addeq r0, #8 8007f60: 071a lsls r2, r3, #28 8007f62: bf04 itt eq 8007f64: 091b lsreq r3, r3, #4 8007f66: 3004 addeq r0, #4 8007f68: 079a lsls r2, r3, #30 8007f6a: bf04 itt eq 8007f6c: 089b lsreq r3, r3, #2 8007f6e: 3002 addeq r0, #2 8007f70: 07da lsls r2, r3, #31 8007f72: d402 bmi.n 8007f7a <__lo0bits+0x4e> 8007f74: 085b lsrs r3, r3, #1 8007f76: d006 beq.n 8007f86 <__lo0bits+0x5a> 8007f78: 3001 adds r0, #1 8007f7a: 600b str r3, [r1, #0] 8007f7c: 4770 bx lr 8007f7e: 4610 mov r0, r2 8007f80: e7e9 b.n 8007f56 <__lo0bits+0x2a> 8007f82: 2000 movs r0, #0 8007f84: 4770 bx lr 8007f86: 2020 movs r0, #32 8007f88: 4770 bx lr 08007f8a <__i2b>: 8007f8a: b510 push {r4, lr} 8007f8c: 460c mov r4, r1 8007f8e: 2101 movs r1, #1 8007f90: f7ff ff27 bl 8007de2 <_Balloc> 8007f94: 2201 movs r2, #1 8007f96: 6144 str r4, [r0, #20] 8007f98: 6102 str r2, [r0, #16] 8007f9a: bd10 pop {r4, pc} 08007f9c <__multiply>: 8007f9c: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} 8007fa0: 4614 mov r4, r2 8007fa2: 690a ldr r2, [r1, #16] 8007fa4: 6923 ldr r3, [r4, #16] 8007fa6: 4688 mov r8, r1 8007fa8: 429a cmp r2, r3 8007faa: bfbe ittt lt 8007fac: 460b movlt r3, r1 8007fae: 46a0 movlt r8, r4 8007fb0: 461c movlt r4, r3 8007fb2: f8d8 7010 ldr.w r7, [r8, #16] 8007fb6: f8d4 9010 ldr.w r9, [r4, #16] 8007fba: f8d8 3008 ldr.w r3, [r8, #8] 8007fbe: f8d8 1004 ldr.w r1, [r8, #4] 8007fc2: eb07 0609 add.w r6, r7, r9 8007fc6: 42b3 cmp r3, r6 8007fc8: bfb8 it lt 8007fca: 3101 addlt r1, #1 8007fcc: f7ff ff09 bl 8007de2 <_Balloc> 8007fd0: f100 0514 add.w r5, r0, #20 8007fd4: 462b mov r3, r5 8007fd6: 2200 movs r2, #0 8007fd8: eb05 0e86 add.w lr, r5, r6, lsl #2 8007fdc: 4573 cmp r3, lr 8007fde: d316 bcc.n 800800e <__multiply+0x72> 8007fe0: f104 0214 add.w r2, r4, #20 8007fe4: f108 0114 add.w r1, r8, #20 8007fe8: eb02 0389 add.w r3, r2, r9, lsl #2 8007fec: eb01 0787 add.w r7, r1, r7, lsl #2 8007ff0: 9300 str r3, [sp, #0] 8007ff2: 9b00 ldr r3, [sp, #0] 8007ff4: 9201 str r2, [sp, #4] 8007ff6: 4293 cmp r3, r2 8007ff8: d80c bhi.n 8008014 <__multiply+0x78> 8007ffa: 2e00 cmp r6, #0 8007ffc: dd03 ble.n 8008006 <__multiply+0x6a> 8007ffe: f85e 3d04 ldr.w r3, [lr, #-4]! 8008002: 2b00 cmp r3, #0 8008004: d05d beq.n 80080c2 <__multiply+0x126> 8008006: 6106 str r6, [r0, #16] 8008008: b003 add sp, #12 800800a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 800800e: f843 2b04 str.w r2, [r3], #4 8008012: e7e3 b.n 8007fdc <__multiply+0x40> 8008014: f8b2 b000 ldrh.w fp, [r2] 8008018: f1bb 0f00 cmp.w fp, #0 800801c: d023 beq.n 8008066 <__multiply+0xca> 800801e: 4689 mov r9, r1 8008020: 46ac mov ip, r5 8008022: f04f 0800 mov.w r8, #0 8008026: f859 4b04 ldr.w r4, [r9], #4 800802a: f8dc a000 ldr.w sl, [ip] 800802e: b2a3 uxth r3, r4 8008030: fa1f fa8a uxth.w sl, sl 8008034: fb0b a303 mla r3, fp, r3, sl 8008038: ea4f 4a14 mov.w sl, r4, lsr #16 800803c: f8dc 4000 ldr.w r4, [ip] 8008040: 4443 add r3, r8 8008042: ea4f 4814 mov.w r8, r4, lsr #16 8008046: fb0b 840a mla r4, fp, sl, r8 800804a: 46e2 mov sl, ip 800804c: eb04 4413 add.w r4, r4, r3, lsr #16 8008050: b29b uxth r3, r3 8008052: ea43 4304 orr.w r3, r3, r4, lsl #16 8008056: 454f cmp r7, r9 8008058: ea4f 4814 mov.w r8, r4, lsr #16 800805c: f84a 3b04 str.w r3, [sl], #4 8008060: d82b bhi.n 80080ba <__multiply+0x11e> 8008062: f8cc 8004 str.w r8, [ip, #4] 8008066: 9b01 ldr r3, [sp, #4] 8008068: 3204 adds r2, #4 800806a: f8b3 a002 ldrh.w sl, [r3, #2] 800806e: f1ba 0f00 cmp.w sl, #0 8008072: d020 beq.n 80080b6 <__multiply+0x11a> 8008074: 4689 mov r9, r1 8008076: 46a8 mov r8, r5 8008078: f04f 0b00 mov.w fp, #0 800807c: 682b ldr r3, [r5, #0] 800807e: f8b9 c000 ldrh.w ip, [r9] 8008082: f8b8 4002 ldrh.w r4, [r8, #2] 8008086: b29b uxth r3, r3 8008088: fb0a 440c mla r4, sl, ip, r4 800808c: 46c4 mov ip, r8 800808e: 445c add r4, fp 8008090: ea43 4304 orr.w r3, r3, r4, lsl #16 8008094: f84c 3b04 str.w r3, [ip], #4 8008098: f859 3b04 ldr.w r3, [r9], #4 800809c: f8b8 b004 ldrh.w fp, [r8, #4] 80080a0: 0c1b lsrs r3, r3, #16 80080a2: fb0a b303 mla r3, sl, r3, fp 80080a6: 454f cmp r7, r9 80080a8: eb03 4314 add.w r3, r3, r4, lsr #16 80080ac: ea4f 4b13 mov.w fp, r3, lsr #16 80080b0: d805 bhi.n 80080be <__multiply+0x122> 80080b2: f8c8 3004 str.w r3, [r8, #4] 80080b6: 3504 adds r5, #4 80080b8: e79b b.n 8007ff2 <__multiply+0x56> 80080ba: 46d4 mov ip, sl 80080bc: e7b3 b.n 8008026 <__multiply+0x8a> 80080be: 46e0 mov r8, ip 80080c0: e7dd b.n 800807e <__multiply+0xe2> 80080c2: 3e01 subs r6, #1 80080c4: e799 b.n 8007ffa <__multiply+0x5e> ... 080080c8 <__pow5mult>: 80080c8: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 80080cc: 4615 mov r5, r2 80080ce: f012 0203 ands.w r2, r2, #3 80080d2: 4606 mov r6, r0 80080d4: 460f mov r7, r1 80080d6: d007 beq.n 80080e8 <__pow5mult+0x20> 80080d8: 4c21 ldr r4, [pc, #132] ; (8008160 <__pow5mult+0x98>) 80080da: 3a01 subs r2, #1 80080dc: 2300 movs r3, #0 80080de: f854 2022 ldr.w r2, [r4, r2, lsl #2] 80080e2: f7ff fec9 bl 8007e78 <__multadd> 80080e6: 4607 mov r7, r0 80080e8: 10ad asrs r5, r5, #2 80080ea: d035 beq.n 8008158 <__pow5mult+0x90> 80080ec: 6a74 ldr r4, [r6, #36] ; 0x24 80080ee: b93c cbnz r4, 8008100 <__pow5mult+0x38> 80080f0: 2010 movs r0, #16 80080f2: f7ff fe55 bl 8007da0 80080f6: 6270 str r0, [r6, #36] ; 0x24 80080f8: e9c0 4401 strd r4, r4, [r0, #4] 80080fc: 6004 str r4, [r0, #0] 80080fe: 60c4 str r4, [r0, #12] 8008100: f8d6 8024 ldr.w r8, [r6, #36] ; 0x24 8008104: f8d8 4008 ldr.w r4, [r8, #8] 8008108: b94c cbnz r4, 800811e <__pow5mult+0x56> 800810a: f240 2171 movw r1, #625 ; 0x271 800810e: 4630 mov r0, r6 8008110: f7ff ff3b bl 8007f8a <__i2b> 8008114: 2300 movs r3, #0 8008116: 4604 mov r4, r0 8008118: f8c8 0008 str.w r0, [r8, #8] 800811c: 6003 str r3, [r0, #0] 800811e: f04f 0800 mov.w r8, #0 8008122: 07eb lsls r3, r5, #31 8008124: d50a bpl.n 800813c <__pow5mult+0x74> 8008126: 4639 mov r1, r7 8008128: 4622 mov r2, r4 800812a: 4630 mov r0, r6 800812c: f7ff ff36 bl 8007f9c <__multiply> 8008130: 4681 mov r9, r0 8008132: 4639 mov r1, r7 8008134: 4630 mov r0, r6 8008136: f7ff fe88 bl 8007e4a <_Bfree> 800813a: 464f mov r7, r9 800813c: 106d asrs r5, r5, #1 800813e: d00b beq.n 8008158 <__pow5mult+0x90> 8008140: 6820 ldr r0, [r4, #0] 8008142: b938 cbnz r0, 8008154 <__pow5mult+0x8c> 8008144: 4622 mov r2, r4 8008146: 4621 mov r1, r4 8008148: 4630 mov r0, r6 800814a: f7ff ff27 bl 8007f9c <__multiply> 800814e: 6020 str r0, [r4, #0] 8008150: f8c0 8000 str.w r8, [r0] 8008154: 4604 mov r4, r0 8008156: e7e4 b.n 8008122 <__pow5mult+0x5a> 8008158: 4638 mov r0, r7 800815a: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 800815e: bf00 nop 8008160: 08008ea0 .word 0x08008ea0 08008164 <__lshift>: 8008164: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8008168: 460c mov r4, r1 800816a: 4607 mov r7, r0 800816c: 4616 mov r6, r2 800816e: 6923 ldr r3, [r4, #16] 8008170: ea4f 1a62 mov.w sl, r2, asr #5 8008174: eb0a 0903 add.w r9, sl, r3 8008178: 6849 ldr r1, [r1, #4] 800817a: 68a3 ldr r3, [r4, #8] 800817c: f109 0501 add.w r5, r9, #1 8008180: 42ab cmp r3, r5 8008182: db32 blt.n 80081ea <__lshift+0x86> 8008184: 4638 mov r0, r7 8008186: f7ff fe2c bl 8007de2 <_Balloc> 800818a: 2300 movs r3, #0 800818c: 4680 mov r8, r0 800818e: 461a mov r2, r3 8008190: f100 0114 add.w r1, r0, #20 8008194: 4553 cmp r3, sl 8008196: db2b blt.n 80081f0 <__lshift+0x8c> 8008198: 6920 ldr r0, [r4, #16] 800819a: ea2a 7aea bic.w sl, sl, sl, asr #31 800819e: f104 0314 add.w r3, r4, #20 80081a2: f016 021f ands.w r2, r6, #31 80081a6: eb01 018a add.w r1, r1, sl, lsl #2 80081aa: eb03 0c80 add.w ip, r3, r0, lsl #2 80081ae: d025 beq.n 80081fc <__lshift+0x98> 80081b0: 2000 movs r0, #0 80081b2: f1c2 0e20 rsb lr, r2, #32 80081b6: 468a mov sl, r1 80081b8: 681e ldr r6, [r3, #0] 80081ba: 4096 lsls r6, r2 80081bc: 4330 orrs r0, r6 80081be: f84a 0b04 str.w r0, [sl], #4 80081c2: f853 0b04 ldr.w r0, [r3], #4 80081c6: 459c cmp ip, r3 80081c8: fa20 f00e lsr.w r0, r0, lr 80081cc: d814 bhi.n 80081f8 <__lshift+0x94> 80081ce: 6048 str r0, [r1, #4] 80081d0: b108 cbz r0, 80081d6 <__lshift+0x72> 80081d2: f109 0502 add.w r5, r9, #2 80081d6: 3d01 subs r5, #1 80081d8: 4638 mov r0, r7 80081da: f8c8 5010 str.w r5, [r8, #16] 80081de: 4621 mov r1, r4 80081e0: f7ff fe33 bl 8007e4a <_Bfree> 80081e4: 4640 mov r0, r8 80081e6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80081ea: 3101 adds r1, #1 80081ec: 005b lsls r3, r3, #1 80081ee: e7c7 b.n 8008180 <__lshift+0x1c> 80081f0: f841 2023 str.w r2, [r1, r3, lsl #2] 80081f4: 3301 adds r3, #1 80081f6: e7cd b.n 8008194 <__lshift+0x30> 80081f8: 4651 mov r1, sl 80081fa: e7dc b.n 80081b6 <__lshift+0x52> 80081fc: 3904 subs r1, #4 80081fe: f853 2b04 ldr.w r2, [r3], #4 8008202: 459c cmp ip, r3 8008204: f841 2f04 str.w r2, [r1, #4]! 8008208: d8f9 bhi.n 80081fe <__lshift+0x9a> 800820a: e7e4 b.n 80081d6 <__lshift+0x72> 0800820c <__mcmp>: 800820c: 6903 ldr r3, [r0, #16] 800820e: 690a ldr r2, [r1, #16] 8008210: b530 push {r4, r5, lr} 8008212: 1a9b subs r3, r3, r2 8008214: d10c bne.n 8008230 <__mcmp+0x24> 8008216: 0092 lsls r2, r2, #2 8008218: 3014 adds r0, #20 800821a: 3114 adds r1, #20 800821c: 1884 adds r4, r0, r2 800821e: 4411 add r1, r2 8008220: f854 5d04 ldr.w r5, [r4, #-4]! 8008224: f851 2d04 ldr.w r2, [r1, #-4]! 8008228: 4295 cmp r5, r2 800822a: d003 beq.n 8008234 <__mcmp+0x28> 800822c: d305 bcc.n 800823a <__mcmp+0x2e> 800822e: 2301 movs r3, #1 8008230: 4618 mov r0, r3 8008232: bd30 pop {r4, r5, pc} 8008234: 42a0 cmp r0, r4 8008236: d3f3 bcc.n 8008220 <__mcmp+0x14> 8008238: e7fa b.n 8008230 <__mcmp+0x24> 800823a: f04f 33ff mov.w r3, #4294967295 800823e: e7f7 b.n 8008230 <__mcmp+0x24> 08008240 <__mdiff>: 8008240: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8008244: 460d mov r5, r1 8008246: 4607 mov r7, r0 8008248: 4611 mov r1, r2 800824a: 4628 mov r0, r5 800824c: 4614 mov r4, r2 800824e: f7ff ffdd bl 800820c <__mcmp> 8008252: 1e06 subs r6, r0, #0 8008254: d108 bne.n 8008268 <__mdiff+0x28> 8008256: 4631 mov r1, r6 8008258: 4638 mov r0, r7 800825a: f7ff fdc2 bl 8007de2 <_Balloc> 800825e: 2301 movs r3, #1 8008260: e9c0 3604 strd r3, r6, [r0, #16] 8008264: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8008268: bfa4 itt ge 800826a: 4623 movge r3, r4 800826c: 462c movge r4, r5 800826e: 4638 mov r0, r7 8008270: 6861 ldr r1, [r4, #4] 8008272: bfa6 itte ge 8008274: 461d movge r5, r3 8008276: 2600 movge r6, #0 8008278: 2601 movlt r6, #1 800827a: f7ff fdb2 bl 8007de2 <_Balloc> 800827e: f04f 0e00 mov.w lr, #0 8008282: 60c6 str r6, [r0, #12] 8008284: 692b ldr r3, [r5, #16] 8008286: 6926 ldr r6, [r4, #16] 8008288: f104 0214 add.w r2, r4, #20 800828c: f105 0914 add.w r9, r5, #20 8008290: eb02 0786 add.w r7, r2, r6, lsl #2 8008294: eb09 0883 add.w r8, r9, r3, lsl #2 8008298: f100 0114 add.w r1, r0, #20 800829c: f852 ab04 ldr.w sl, [r2], #4 80082a0: f859 5b04 ldr.w r5, [r9], #4 80082a4: fa1f f38a uxth.w r3, sl 80082a8: 4473 add r3, lr 80082aa: b2ac uxth r4, r5 80082ac: 1b1b subs r3, r3, r4 80082ae: 0c2c lsrs r4, r5, #16 80082b0: ebc4 441a rsb r4, r4, sl, lsr #16 80082b4: eb04 4423 add.w r4, r4, r3, asr #16 80082b8: b29b uxth r3, r3 80082ba: ea4f 4e24 mov.w lr, r4, asr #16 80082be: 45c8 cmp r8, r9 80082c0: ea43 4404 orr.w r4, r3, r4, lsl #16 80082c4: 4694 mov ip, r2 80082c6: f841 4b04 str.w r4, [r1], #4 80082ca: d8e7 bhi.n 800829c <__mdiff+0x5c> 80082cc: 45bc cmp ip, r7 80082ce: d304 bcc.n 80082da <__mdiff+0x9a> 80082d0: f851 3d04 ldr.w r3, [r1, #-4]! 80082d4: b183 cbz r3, 80082f8 <__mdiff+0xb8> 80082d6: 6106 str r6, [r0, #16] 80082d8: e7c4 b.n 8008264 <__mdiff+0x24> 80082da: f85c 4b04 ldr.w r4, [ip], #4 80082de: b2a2 uxth r2, r4 80082e0: 4472 add r2, lr 80082e2: 1413 asrs r3, r2, #16 80082e4: eb03 4314 add.w r3, r3, r4, lsr #16 80082e8: b292 uxth r2, r2 80082ea: ea42 4203 orr.w r2, r2, r3, lsl #16 80082ee: ea4f 4e23 mov.w lr, r3, asr #16 80082f2: f841 2b04 str.w r2, [r1], #4 80082f6: e7e9 b.n 80082cc <__mdiff+0x8c> 80082f8: 3e01 subs r6, #1 80082fa: e7e9 b.n 80082d0 <__mdiff+0x90> 080082fc <__d2b>: 80082fc: e92d 41f3 stmdb sp!, {r0, r1, r4, r5, r6, r7, r8, lr} 8008300: 461c mov r4, r3 8008302: e9dd 6508 ldrd r6, r5, [sp, #32] 8008306: 2101 movs r1, #1 8008308: 4690 mov r8, r2 800830a: f7ff fd6a bl 8007de2 <_Balloc> 800830e: f3c4 0213 ubfx r2, r4, #0, #20 8008312: f3c4 540a ubfx r4, r4, #20, #11 8008316: 4607 mov r7, r0 8008318: bb34 cbnz r4, 8008368 <__d2b+0x6c> 800831a: 9201 str r2, [sp, #4] 800831c: f1b8 0200 subs.w r2, r8, #0 8008320: d027 beq.n 8008372 <__d2b+0x76> 8008322: a802 add r0, sp, #8 8008324: f840 2d08 str.w r2, [r0, #-8]! 8008328: f7ff fe00 bl 8007f2c <__lo0bits> 800832c: 9900 ldr r1, [sp, #0] 800832e: b1f0 cbz r0, 800836e <__d2b+0x72> 8008330: 9a01 ldr r2, [sp, #4] 8008332: f1c0 0320 rsb r3, r0, #32 8008336: fa02 f303 lsl.w r3, r2, r3 800833a: 430b orrs r3, r1 800833c: 40c2 lsrs r2, r0 800833e: 617b str r3, [r7, #20] 8008340: 9201 str r2, [sp, #4] 8008342: 9b01 ldr r3, [sp, #4] 8008344: 2b00 cmp r3, #0 8008346: bf14 ite ne 8008348: 2102 movne r1, #2 800834a: 2101 moveq r1, #1 800834c: 61bb str r3, [r7, #24] 800834e: 6139 str r1, [r7, #16] 8008350: b1c4 cbz r4, 8008384 <__d2b+0x88> 8008352: f2a4 4433 subw r4, r4, #1075 ; 0x433 8008356: 4404 add r4, r0 8008358: 6034 str r4, [r6, #0] 800835a: f1c0 0035 rsb r0, r0, #53 ; 0x35 800835e: 6028 str r0, [r5, #0] 8008360: 4638 mov r0, r7 8008362: b002 add sp, #8 8008364: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8008368: f442 1280 orr.w r2, r2, #1048576 ; 0x100000 800836c: e7d5 b.n 800831a <__d2b+0x1e> 800836e: 6179 str r1, [r7, #20] 8008370: e7e7 b.n 8008342 <__d2b+0x46> 8008372: a801 add r0, sp, #4 8008374: f7ff fdda bl 8007f2c <__lo0bits> 8008378: 2101 movs r1, #1 800837a: 9b01 ldr r3, [sp, #4] 800837c: 6139 str r1, [r7, #16] 800837e: 617b str r3, [r7, #20] 8008380: 3020 adds r0, #32 8008382: e7e5 b.n 8008350 <__d2b+0x54> 8008384: f2a0 4032 subw r0, r0, #1074 ; 0x432 8008388: eb07 0381 add.w r3, r7, r1, lsl #2 800838c: 6030 str r0, [r6, #0] 800838e: 6918 ldr r0, [r3, #16] 8008390: f7ff fdad bl 8007eee <__hi0bits> 8008394: ebc0 1041 rsb r0, r0, r1, lsl #5 8008398: e7e1 b.n 800835e <__d2b+0x62> 0800839a <_calloc_r>: 800839a: b538 push {r3, r4, r5, lr} 800839c: fb02 f401 mul.w r4, r2, r1 80083a0: 4621 mov r1, r4 80083a2: f000 f855 bl 8008450 <_malloc_r> 80083a6: 4605 mov r5, r0 80083a8: b118 cbz r0, 80083b2 <_calloc_r+0x18> 80083aa: 4622 mov r2, r4 80083ac: 2100 movs r1, #0 80083ae: f7fd fe7f bl 80060b0 80083b2: 4628 mov r0, r5 80083b4: bd38 pop {r3, r4, r5, pc} ... 080083b8 <_free_r>: 80083b8: b538 push {r3, r4, r5, lr} 80083ba: 4605 mov r5, r0 80083bc: 2900 cmp r1, #0 80083be: d043 beq.n 8008448 <_free_r+0x90> 80083c0: f851 3c04 ldr.w r3, [r1, #-4] 80083c4: 1f0c subs r4, r1, #4 80083c6: 2b00 cmp r3, #0 80083c8: bfb8 it lt 80083ca: 18e4 addlt r4, r4, r3 80083cc: f000 fa94 bl 80088f8 <__malloc_lock> 80083d0: 4a1e ldr r2, [pc, #120] ; (800844c <_free_r+0x94>) 80083d2: 6813 ldr r3, [r2, #0] 80083d4: 4610 mov r0, r2 80083d6: b933 cbnz r3, 80083e6 <_free_r+0x2e> 80083d8: 6063 str r3, [r4, #4] 80083da: 6014 str r4, [r2, #0] 80083dc: 4628 mov r0, r5 80083de: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 80083e2: f000 ba8a b.w 80088fa <__malloc_unlock> 80083e6: 42a3 cmp r3, r4 80083e8: d90b bls.n 8008402 <_free_r+0x4a> 80083ea: 6821 ldr r1, [r4, #0] 80083ec: 1862 adds r2, r4, r1 80083ee: 4293 cmp r3, r2 80083f0: bf01 itttt eq 80083f2: 681a ldreq r2, [r3, #0] 80083f4: 685b ldreq r3, [r3, #4] 80083f6: 1852 addeq r2, r2, r1 80083f8: 6022 streq r2, [r4, #0] 80083fa: 6063 str r3, [r4, #4] 80083fc: 6004 str r4, [r0, #0] 80083fe: e7ed b.n 80083dc <_free_r+0x24> 8008400: 4613 mov r3, r2 8008402: 685a ldr r2, [r3, #4] 8008404: b10a cbz r2, 800840a <_free_r+0x52> 8008406: 42a2 cmp r2, r4 8008408: d9fa bls.n 8008400 <_free_r+0x48> 800840a: 6819 ldr r1, [r3, #0] 800840c: 1858 adds r0, r3, r1 800840e: 42a0 cmp r0, r4 8008410: d10b bne.n 800842a <_free_r+0x72> 8008412: 6820 ldr r0, [r4, #0] 8008414: 4401 add r1, r0 8008416: 1858 adds r0, r3, r1 8008418: 4282 cmp r2, r0 800841a: 6019 str r1, [r3, #0] 800841c: d1de bne.n 80083dc <_free_r+0x24> 800841e: 6810 ldr r0, [r2, #0] 8008420: 6852 ldr r2, [r2, #4] 8008422: 4401 add r1, r0 8008424: 6019 str r1, [r3, #0] 8008426: 605a str r2, [r3, #4] 8008428: e7d8 b.n 80083dc <_free_r+0x24> 800842a: d902 bls.n 8008432 <_free_r+0x7a> 800842c: 230c movs r3, #12 800842e: 602b str r3, [r5, #0] 8008430: e7d4 b.n 80083dc <_free_r+0x24> 8008432: 6820 ldr r0, [r4, #0] 8008434: 1821 adds r1, r4, r0 8008436: 428a cmp r2, r1 8008438: bf01 itttt eq 800843a: 6811 ldreq r1, [r2, #0] 800843c: 6852 ldreq r2, [r2, #4] 800843e: 1809 addeq r1, r1, r0 8008440: 6021 streq r1, [r4, #0] 8008442: 6062 str r2, [r4, #4] 8008444: 605c str r4, [r3, #4] 8008446: e7c9 b.n 80083dc <_free_r+0x24> 8008448: bd38 pop {r3, r4, r5, pc} 800844a: bf00 nop 800844c: 20000640 .word 0x20000640 08008450 <_malloc_r>: 8008450: b570 push {r4, r5, r6, lr} 8008452: 1ccd adds r5, r1, #3 8008454: f025 0503 bic.w r5, r5, #3 8008458: 3508 adds r5, #8 800845a: 2d0c cmp r5, #12 800845c: bf38 it cc 800845e: 250c movcc r5, #12 8008460: 2d00 cmp r5, #0 8008462: 4606 mov r6, r0 8008464: db01 blt.n 800846a <_malloc_r+0x1a> 8008466: 42a9 cmp r1, r5 8008468: d903 bls.n 8008472 <_malloc_r+0x22> 800846a: 230c movs r3, #12 800846c: 6033 str r3, [r6, #0] 800846e: 2000 movs r0, #0 8008470: bd70 pop {r4, r5, r6, pc} 8008472: f000 fa41 bl 80088f8 <__malloc_lock> 8008476: 4a21 ldr r2, [pc, #132] ; (80084fc <_malloc_r+0xac>) 8008478: 6814 ldr r4, [r2, #0] 800847a: 4621 mov r1, r4 800847c: b991 cbnz r1, 80084a4 <_malloc_r+0x54> 800847e: 4c20 ldr r4, [pc, #128] ; (8008500 <_malloc_r+0xb0>) 8008480: 6823 ldr r3, [r4, #0] 8008482: b91b cbnz r3, 800848c <_malloc_r+0x3c> 8008484: 4630 mov r0, r6 8008486: f000 f97b bl 8008780 <_sbrk_r> 800848a: 6020 str r0, [r4, #0] 800848c: 4629 mov r1, r5 800848e: 4630 mov r0, r6 8008490: f000 f976 bl 8008780 <_sbrk_r> 8008494: 1c43 adds r3, r0, #1 8008496: d124 bne.n 80084e2 <_malloc_r+0x92> 8008498: 230c movs r3, #12 800849a: 4630 mov r0, r6 800849c: 6033 str r3, [r6, #0] 800849e: f000 fa2c bl 80088fa <__malloc_unlock> 80084a2: e7e4 b.n 800846e <_malloc_r+0x1e> 80084a4: 680b ldr r3, [r1, #0] 80084a6: 1b5b subs r3, r3, r5 80084a8: d418 bmi.n 80084dc <_malloc_r+0x8c> 80084aa: 2b0b cmp r3, #11 80084ac: d90f bls.n 80084ce <_malloc_r+0x7e> 80084ae: 600b str r3, [r1, #0] 80084b0: 18cc adds r4, r1, r3 80084b2: 50cd str r5, [r1, r3] 80084b4: 4630 mov r0, r6 80084b6: f000 fa20 bl 80088fa <__malloc_unlock> 80084ba: f104 000b add.w r0, r4, #11 80084be: 1d23 adds r3, r4, #4 80084c0: f020 0007 bic.w r0, r0, #7 80084c4: 1ac3 subs r3, r0, r3 80084c6: d0d3 beq.n 8008470 <_malloc_r+0x20> 80084c8: 425a negs r2, r3 80084ca: 50e2 str r2, [r4, r3] 80084cc: e7d0 b.n 8008470 <_malloc_r+0x20> 80084ce: 684b ldr r3, [r1, #4] 80084d0: 428c cmp r4, r1 80084d2: bf16 itet ne 80084d4: 6063 strne r3, [r4, #4] 80084d6: 6013 streq r3, [r2, #0] 80084d8: 460c movne r4, r1 80084da: e7eb b.n 80084b4 <_malloc_r+0x64> 80084dc: 460c mov r4, r1 80084de: 6849 ldr r1, [r1, #4] 80084e0: e7cc b.n 800847c <_malloc_r+0x2c> 80084e2: 1cc4 adds r4, r0, #3 80084e4: f024 0403 bic.w r4, r4, #3 80084e8: 42a0 cmp r0, r4 80084ea: d005 beq.n 80084f8 <_malloc_r+0xa8> 80084ec: 1a21 subs r1, r4, r0 80084ee: 4630 mov r0, r6 80084f0: f000 f946 bl 8008780 <_sbrk_r> 80084f4: 3001 adds r0, #1 80084f6: d0cf beq.n 8008498 <_malloc_r+0x48> 80084f8: 6025 str r5, [r4, #0] 80084fa: e7db b.n 80084b4 <_malloc_r+0x64> 80084fc: 20000640 .word 0x20000640 8008500: 20000644 .word 0x20000644 08008504 <__sfputc_r>: 8008504: 6893 ldr r3, [r2, #8] 8008506: b410 push {r4} 8008508: 3b01 subs r3, #1 800850a: 2b00 cmp r3, #0 800850c: 6093 str r3, [r2, #8] 800850e: da07 bge.n 8008520 <__sfputc_r+0x1c> 8008510: 6994 ldr r4, [r2, #24] 8008512: 42a3 cmp r3, r4 8008514: db01 blt.n 800851a <__sfputc_r+0x16> 8008516: 290a cmp r1, #10 8008518: d102 bne.n 8008520 <__sfputc_r+0x1c> 800851a: bc10 pop {r4} 800851c: f7fe bb52 b.w 8006bc4 <__swbuf_r> 8008520: 6813 ldr r3, [r2, #0] 8008522: 1c58 adds r0, r3, #1 8008524: 6010 str r0, [r2, #0] 8008526: 7019 strb r1, [r3, #0] 8008528: 4608 mov r0, r1 800852a: bc10 pop {r4} 800852c: 4770 bx lr 0800852e <__sfputs_r>: 800852e: b5f8 push {r3, r4, r5, r6, r7, lr} 8008530: 4606 mov r6, r0 8008532: 460f mov r7, r1 8008534: 4614 mov r4, r2 8008536: 18d5 adds r5, r2, r3 8008538: 42ac cmp r4, r5 800853a: d101 bne.n 8008540 <__sfputs_r+0x12> 800853c: 2000 movs r0, #0 800853e: e007 b.n 8008550 <__sfputs_r+0x22> 8008540: 463a mov r2, r7 8008542: f814 1b01 ldrb.w r1, [r4], #1 8008546: 4630 mov r0, r6 8008548: f7ff ffdc bl 8008504 <__sfputc_r> 800854c: 1c43 adds r3, r0, #1 800854e: d1f3 bne.n 8008538 <__sfputs_r+0xa> 8008550: bdf8 pop {r3, r4, r5, r6, r7, pc} ... 08008554 <_vfiprintf_r>: 8008554: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8008558: 460c mov r4, r1 800855a: b09d sub sp, #116 ; 0x74 800855c: 4617 mov r7, r2 800855e: 461d mov r5, r3 8008560: 4606 mov r6, r0 8008562: b118 cbz r0, 800856c <_vfiprintf_r+0x18> 8008564: 6983 ldr r3, [r0, #24] 8008566: b90b cbnz r3, 800856c <_vfiprintf_r+0x18> 8008568: f7ff fb1e bl 8007ba8 <__sinit> 800856c: 4b7c ldr r3, [pc, #496] ; (8008760 <_vfiprintf_r+0x20c>) 800856e: 429c cmp r4, r3 8008570: d158 bne.n 8008624 <_vfiprintf_r+0xd0> 8008572: 6874 ldr r4, [r6, #4] 8008574: 89a3 ldrh r3, [r4, #12] 8008576: 0718 lsls r0, r3, #28 8008578: d55e bpl.n 8008638 <_vfiprintf_r+0xe4> 800857a: 6923 ldr r3, [r4, #16] 800857c: 2b00 cmp r3, #0 800857e: d05b beq.n 8008638 <_vfiprintf_r+0xe4> 8008580: 2300 movs r3, #0 8008582: 9309 str r3, [sp, #36] ; 0x24 8008584: 2320 movs r3, #32 8008586: f88d 3029 strb.w r3, [sp, #41] ; 0x29 800858a: 2330 movs r3, #48 ; 0x30 800858c: f04f 0b01 mov.w fp, #1 8008590: f88d 302a strb.w r3, [sp, #42] ; 0x2a 8008594: 9503 str r5, [sp, #12] 8008596: 46b8 mov r8, r7 8008598: 4645 mov r5, r8 800859a: f815 3b01 ldrb.w r3, [r5], #1 800859e: b10b cbz r3, 80085a4 <_vfiprintf_r+0x50> 80085a0: 2b25 cmp r3, #37 ; 0x25 80085a2: d154 bne.n 800864e <_vfiprintf_r+0xfa> 80085a4: ebb8 0a07 subs.w sl, r8, r7 80085a8: d00b beq.n 80085c2 <_vfiprintf_r+0x6e> 80085aa: 4653 mov r3, sl 80085ac: 463a mov r2, r7 80085ae: 4621 mov r1, r4 80085b0: 4630 mov r0, r6 80085b2: f7ff ffbc bl 800852e <__sfputs_r> 80085b6: 3001 adds r0, #1 80085b8: f000 80c2 beq.w 8008740 <_vfiprintf_r+0x1ec> 80085bc: 9b09 ldr r3, [sp, #36] ; 0x24 80085be: 4453 add r3, sl 80085c0: 9309 str r3, [sp, #36] ; 0x24 80085c2: f898 3000 ldrb.w r3, [r8] 80085c6: 2b00 cmp r3, #0 80085c8: f000 80ba beq.w 8008740 <_vfiprintf_r+0x1ec> 80085cc: 2300 movs r3, #0 80085ce: f04f 32ff mov.w r2, #4294967295 80085d2: e9cd 2305 strd r2, r3, [sp, #20] 80085d6: 9304 str r3, [sp, #16] 80085d8: 9307 str r3, [sp, #28] 80085da: f88d 3053 strb.w r3, [sp, #83] ; 0x53 80085de: 931a str r3, [sp, #104] ; 0x68 80085e0: 46a8 mov r8, r5 80085e2: 2205 movs r2, #5 80085e4: f818 1b01 ldrb.w r1, [r8], #1 80085e8: 485e ldr r0, [pc, #376] ; (8008764 <_vfiprintf_r+0x210>) 80085ea: f7ff fbe1 bl 8007db0 80085ee: 9b04 ldr r3, [sp, #16] 80085f0: bb78 cbnz r0, 8008652 <_vfiprintf_r+0xfe> 80085f2: 06d9 lsls r1, r3, #27 80085f4: bf44 itt mi 80085f6: 2220 movmi r2, #32 80085f8: f88d 2053 strbmi.w r2, [sp, #83] ; 0x53 80085fc: 071a lsls r2, r3, #28 80085fe: bf44 itt mi 8008600: 222b movmi r2, #43 ; 0x2b 8008602: f88d 2053 strbmi.w r2, [sp, #83] ; 0x53 8008606: 782a ldrb r2, [r5, #0] 8008608: 2a2a cmp r2, #42 ; 0x2a 800860a: d02a beq.n 8008662 <_vfiprintf_r+0x10e> 800860c: 46a8 mov r8, r5 800860e: 2000 movs r0, #0 8008610: 250a movs r5, #10 8008612: 9a07 ldr r2, [sp, #28] 8008614: 4641 mov r1, r8 8008616: f811 3b01 ldrb.w r3, [r1], #1 800861a: 3b30 subs r3, #48 ; 0x30 800861c: 2b09 cmp r3, #9 800861e: d969 bls.n 80086f4 <_vfiprintf_r+0x1a0> 8008620: b360 cbz r0, 800867c <_vfiprintf_r+0x128> 8008622: e024 b.n 800866e <_vfiprintf_r+0x11a> 8008624: 4b50 ldr r3, [pc, #320] ; (8008768 <_vfiprintf_r+0x214>) 8008626: 429c cmp r4, r3 8008628: d101 bne.n 800862e <_vfiprintf_r+0xda> 800862a: 68b4 ldr r4, [r6, #8] 800862c: e7a2 b.n 8008574 <_vfiprintf_r+0x20> 800862e: 4b4f ldr r3, [pc, #316] ; (800876c <_vfiprintf_r+0x218>) 8008630: 429c cmp r4, r3 8008632: bf08 it eq 8008634: 68f4 ldreq r4, [r6, #12] 8008636: e79d b.n 8008574 <_vfiprintf_r+0x20> 8008638: 4621 mov r1, r4 800863a: 4630 mov r0, r6 800863c: f7fe fb14 bl 8006c68 <__swsetup_r> 8008640: 2800 cmp r0, #0 8008642: d09d beq.n 8008580 <_vfiprintf_r+0x2c> 8008644: f04f 30ff mov.w r0, #4294967295 8008648: b01d add sp, #116 ; 0x74 800864a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 800864e: 46a8 mov r8, r5 8008650: e7a2 b.n 8008598 <_vfiprintf_r+0x44> 8008652: 4a44 ldr r2, [pc, #272] ; (8008764 <_vfiprintf_r+0x210>) 8008654: 4645 mov r5, r8 8008656: 1a80 subs r0, r0, r2 8008658: fa0b f000 lsl.w r0, fp, r0 800865c: 4318 orrs r0, r3 800865e: 9004 str r0, [sp, #16] 8008660: e7be b.n 80085e0 <_vfiprintf_r+0x8c> 8008662: 9a03 ldr r2, [sp, #12] 8008664: 1d11 adds r1, r2, #4 8008666: 6812 ldr r2, [r2, #0] 8008668: 9103 str r1, [sp, #12] 800866a: 2a00 cmp r2, #0 800866c: db01 blt.n 8008672 <_vfiprintf_r+0x11e> 800866e: 9207 str r2, [sp, #28] 8008670: e004 b.n 800867c <_vfiprintf_r+0x128> 8008672: 4252 negs r2, r2 8008674: f043 0302 orr.w r3, r3, #2 8008678: 9207 str r2, [sp, #28] 800867a: 9304 str r3, [sp, #16] 800867c: f898 3000 ldrb.w r3, [r8] 8008680: 2b2e cmp r3, #46 ; 0x2e 8008682: d10e bne.n 80086a2 <_vfiprintf_r+0x14e> 8008684: f898 3001 ldrb.w r3, [r8, #1] 8008688: 2b2a cmp r3, #42 ; 0x2a 800868a: d138 bne.n 80086fe <_vfiprintf_r+0x1aa> 800868c: 9b03 ldr r3, [sp, #12] 800868e: f108 0802 add.w r8, r8, #2 8008692: 1d1a adds r2, r3, #4 8008694: 681b ldr r3, [r3, #0] 8008696: 9203 str r2, [sp, #12] 8008698: 2b00 cmp r3, #0 800869a: bfb8 it lt 800869c: f04f 33ff movlt.w r3, #4294967295 80086a0: 9305 str r3, [sp, #20] 80086a2: 4d33 ldr r5, [pc, #204] ; (8008770 <_vfiprintf_r+0x21c>) 80086a4: 2203 movs r2, #3 80086a6: f898 1000 ldrb.w r1, [r8] 80086aa: 4628 mov r0, r5 80086ac: f7ff fb80 bl 8007db0 80086b0: b140 cbz r0, 80086c4 <_vfiprintf_r+0x170> 80086b2: 2340 movs r3, #64 ; 0x40 80086b4: 1b40 subs r0, r0, r5 80086b6: fa03 f000 lsl.w r0, r3, r0 80086ba: 9b04 ldr r3, [sp, #16] 80086bc: f108 0801 add.w r8, r8, #1 80086c0: 4303 orrs r3, r0 80086c2: 9304 str r3, [sp, #16] 80086c4: f898 1000 ldrb.w r1, [r8] 80086c8: 2206 movs r2, #6 80086ca: 482a ldr r0, [pc, #168] ; (8008774 <_vfiprintf_r+0x220>) 80086cc: f108 0701 add.w r7, r8, #1 80086d0: f88d 1028 strb.w r1, [sp, #40] ; 0x28 80086d4: f7ff fb6c bl 8007db0 80086d8: 2800 cmp r0, #0 80086da: d037 beq.n 800874c <_vfiprintf_r+0x1f8> 80086dc: 4b26 ldr r3, [pc, #152] ; (8008778 <_vfiprintf_r+0x224>) 80086de: bb1b cbnz r3, 8008728 <_vfiprintf_r+0x1d4> 80086e0: 9b03 ldr r3, [sp, #12] 80086e2: 3307 adds r3, #7 80086e4: f023 0307 bic.w r3, r3, #7 80086e8: 3308 adds r3, #8 80086ea: 9303 str r3, [sp, #12] 80086ec: 9b09 ldr r3, [sp, #36] ; 0x24 80086ee: 444b add r3, r9 80086f0: 9309 str r3, [sp, #36] ; 0x24 80086f2: e750 b.n 8008596 <_vfiprintf_r+0x42> 80086f4: fb05 3202 mla r2, r5, r2, r3 80086f8: 2001 movs r0, #1 80086fa: 4688 mov r8, r1 80086fc: e78a b.n 8008614 <_vfiprintf_r+0xc0> 80086fe: 2300 movs r3, #0 8008700: 250a movs r5, #10 8008702: 4619 mov r1, r3 8008704: f108 0801 add.w r8, r8, #1 8008708: 9305 str r3, [sp, #20] 800870a: 4640 mov r0, r8 800870c: f810 2b01 ldrb.w r2, [r0], #1 8008710: 3a30 subs r2, #48 ; 0x30 8008712: 2a09 cmp r2, #9 8008714: d903 bls.n 800871e <_vfiprintf_r+0x1ca> 8008716: 2b00 cmp r3, #0 8008718: d0c3 beq.n 80086a2 <_vfiprintf_r+0x14e> 800871a: 9105 str r1, [sp, #20] 800871c: e7c1 b.n 80086a2 <_vfiprintf_r+0x14e> 800871e: fb05 2101 mla r1, r5, r1, r2 8008722: 2301 movs r3, #1 8008724: 4680 mov r8, r0 8008726: e7f0 b.n 800870a <_vfiprintf_r+0x1b6> 8008728: ab03 add r3, sp, #12 800872a: 9300 str r3, [sp, #0] 800872c: 4622 mov r2, r4 800872e: 4b13 ldr r3, [pc, #76] ; (800877c <_vfiprintf_r+0x228>) 8008730: a904 add r1, sp, #16 8008732: 4630 mov r0, r6 8008734: f7fd fd56 bl 80061e4 <_printf_float> 8008738: f1b0 3fff cmp.w r0, #4294967295 800873c: 4681 mov r9, r0 800873e: d1d5 bne.n 80086ec <_vfiprintf_r+0x198> 8008740: 89a3 ldrh r3, [r4, #12] 8008742: 065b lsls r3, r3, #25 8008744: f53f af7e bmi.w 8008644 <_vfiprintf_r+0xf0> 8008748: 9809 ldr r0, [sp, #36] ; 0x24 800874a: e77d b.n 8008648 <_vfiprintf_r+0xf4> 800874c: ab03 add r3, sp, #12 800874e: 9300 str r3, [sp, #0] 8008750: 4622 mov r2, r4 8008752: 4b0a ldr r3, [pc, #40] ; (800877c <_vfiprintf_r+0x228>) 8008754: a904 add r1, sp, #16 8008756: 4630 mov r0, r6 8008758: f7fd fff0 bl 800673c <_printf_i> 800875c: e7ec b.n 8008738 <_vfiprintf_r+0x1e4> 800875e: bf00 nop 8008760: 08008d6c .word 0x08008d6c 8008764: 08008eac .word 0x08008eac 8008768: 08008d8c .word 0x08008d8c 800876c: 08008d4c .word 0x08008d4c 8008770: 08008eb2 .word 0x08008eb2 8008774: 08008eb6 .word 0x08008eb6 8008778: 080061e5 .word 0x080061e5 800877c: 0800852f .word 0x0800852f 08008780 <_sbrk_r>: 8008780: b538 push {r3, r4, r5, lr} 8008782: 2300 movs r3, #0 8008784: 4c05 ldr r4, [pc, #20] ; (800879c <_sbrk_r+0x1c>) 8008786: 4605 mov r5, r0 8008788: 4608 mov r0, r1 800878a: 6023 str r3, [r4, #0] 800878c: f7fd fbdc bl 8005f48 <_sbrk> 8008790: 1c43 adds r3, r0, #1 8008792: d102 bne.n 800879a <_sbrk_r+0x1a> 8008794: 6823 ldr r3, [r4, #0] 8008796: b103 cbz r3, 800879a <_sbrk_r+0x1a> 8008798: 602b str r3, [r5, #0] 800879a: bd38 pop {r3, r4, r5, pc} 800879c: 20000b94 .word 0x20000b94 080087a0 <__sread>: 80087a0: b510 push {r4, lr} 80087a2: 460c mov r4, r1 80087a4: f9b1 100e ldrsh.w r1, [r1, #14] 80087a8: f000 f8a8 bl 80088fc <_read_r> 80087ac: 2800 cmp r0, #0 80087ae: bfab itete ge 80087b0: 6d63 ldrge r3, [r4, #84] ; 0x54 80087b2: 89a3 ldrhlt r3, [r4, #12] 80087b4: 181b addge r3, r3, r0 80087b6: f423 5380 biclt.w r3, r3, #4096 ; 0x1000 80087ba: bfac ite ge 80087bc: 6563 strge r3, [r4, #84] ; 0x54 80087be: 81a3 strhlt r3, [r4, #12] 80087c0: bd10 pop {r4, pc} 080087c2 <__swrite>: 80087c2: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 80087c6: 461f mov r7, r3 80087c8: 898b ldrh r3, [r1, #12] 80087ca: 4605 mov r5, r0 80087cc: 05db lsls r3, r3, #23 80087ce: 460c mov r4, r1 80087d0: 4616 mov r6, r2 80087d2: d505 bpl.n 80087e0 <__swrite+0x1e> 80087d4: 2302 movs r3, #2 80087d6: 2200 movs r2, #0 80087d8: f9b1 100e ldrsh.w r1, [r1, #14] 80087dc: f000 f868 bl 80088b0 <_lseek_r> 80087e0: 89a3 ldrh r3, [r4, #12] 80087e2: 4632 mov r2, r6 80087e4: f423 5380 bic.w r3, r3, #4096 ; 0x1000 80087e8: 81a3 strh r3, [r4, #12] 80087ea: f9b4 100e ldrsh.w r1, [r4, #14] 80087ee: 463b mov r3, r7 80087f0: 4628 mov r0, r5 80087f2: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 80087f6: f000 b817 b.w 8008828 <_write_r> 080087fa <__sseek>: 80087fa: b510 push {r4, lr} 80087fc: 460c mov r4, r1 80087fe: f9b1 100e ldrsh.w r1, [r1, #14] 8008802: f000 f855 bl 80088b0 <_lseek_r> 8008806: 1c43 adds r3, r0, #1 8008808: 89a3 ldrh r3, [r4, #12] 800880a: bf15 itete ne 800880c: 6560 strne r0, [r4, #84] ; 0x54 800880e: f423 5380 biceq.w r3, r3, #4096 ; 0x1000 8008812: f443 5380 orrne.w r3, r3, #4096 ; 0x1000 8008816: 81a3 strheq r3, [r4, #12] 8008818: bf18 it ne 800881a: 81a3 strhne r3, [r4, #12] 800881c: bd10 pop {r4, pc} 0800881e <__sclose>: 800881e: f9b1 100e ldrsh.w r1, [r1, #14] 8008822: f000 b813 b.w 800884c <_close_r> ... 08008828 <_write_r>: 8008828: b538 push {r3, r4, r5, lr} 800882a: 4605 mov r5, r0 800882c: 4608 mov r0, r1 800882e: 4611 mov r1, r2 8008830: 2200 movs r2, #0 8008832: 4c05 ldr r4, [pc, #20] ; (8008848 <_write_r+0x20>) 8008834: 6022 str r2, [r4, #0] 8008836: 461a mov r2, r3 8008838: f7fc fd30 bl 800529c <_write> 800883c: 1c43 adds r3, r0, #1 800883e: d102 bne.n 8008846 <_write_r+0x1e> 8008840: 6823 ldr r3, [r4, #0] 8008842: b103 cbz r3, 8008846 <_write_r+0x1e> 8008844: 602b str r3, [r5, #0] 8008846: bd38 pop {r3, r4, r5, pc} 8008848: 20000b94 .word 0x20000b94 0800884c <_close_r>: 800884c: b538 push {r3, r4, r5, lr} 800884e: 2300 movs r3, #0 8008850: 4c05 ldr r4, [pc, #20] ; (8008868 <_close_r+0x1c>) 8008852: 4605 mov r5, r0 8008854: 4608 mov r0, r1 8008856: 6023 str r3, [r4, #0] 8008858: f7fd fb45 bl 8005ee6 <_close> 800885c: 1c43 adds r3, r0, #1 800885e: d102 bne.n 8008866 <_close_r+0x1a> 8008860: 6823 ldr r3, [r4, #0] 8008862: b103 cbz r3, 8008866 <_close_r+0x1a> 8008864: 602b str r3, [r5, #0] 8008866: bd38 pop {r3, r4, r5, pc} 8008868: 20000b94 .word 0x20000b94 0800886c <_fstat_r>: 800886c: b538 push {r3, r4, r5, lr} 800886e: 2300 movs r3, #0 8008870: 4c06 ldr r4, [pc, #24] ; (800888c <_fstat_r+0x20>) 8008872: 4605 mov r5, r0 8008874: 4608 mov r0, r1 8008876: 4611 mov r1, r2 8008878: 6023 str r3, [r4, #0] 800887a: f7fd fb3f bl 8005efc <_fstat> 800887e: 1c43 adds r3, r0, #1 8008880: d102 bne.n 8008888 <_fstat_r+0x1c> 8008882: 6823 ldr r3, [r4, #0] 8008884: b103 cbz r3, 8008888 <_fstat_r+0x1c> 8008886: 602b str r3, [r5, #0] 8008888: bd38 pop {r3, r4, r5, pc} 800888a: bf00 nop 800888c: 20000b94 .word 0x20000b94 08008890 <_isatty_r>: 8008890: b538 push {r3, r4, r5, lr} 8008892: 2300 movs r3, #0 8008894: 4c05 ldr r4, [pc, #20] ; (80088ac <_isatty_r+0x1c>) 8008896: 4605 mov r5, r0 8008898: 4608 mov r0, r1 800889a: 6023 str r3, [r4, #0] 800889c: f7fd fb3d bl 8005f1a <_isatty> 80088a0: 1c43 adds r3, r0, #1 80088a2: d102 bne.n 80088aa <_isatty_r+0x1a> 80088a4: 6823 ldr r3, [r4, #0] 80088a6: b103 cbz r3, 80088aa <_isatty_r+0x1a> 80088a8: 602b str r3, [r5, #0] 80088aa: bd38 pop {r3, r4, r5, pc} 80088ac: 20000b94 .word 0x20000b94 080088b0 <_lseek_r>: 80088b0: b538 push {r3, r4, r5, lr} 80088b2: 4605 mov r5, r0 80088b4: 4608 mov r0, r1 80088b6: 4611 mov r1, r2 80088b8: 2200 movs r2, #0 80088ba: 4c05 ldr r4, [pc, #20] ; (80088d0 <_lseek_r+0x20>) 80088bc: 6022 str r2, [r4, #0] 80088be: 461a mov r2, r3 80088c0: f7fd fb35 bl 8005f2e <_lseek> 80088c4: 1c43 adds r3, r0, #1 80088c6: d102 bne.n 80088ce <_lseek_r+0x1e> 80088c8: 6823 ldr r3, [r4, #0] 80088ca: b103 cbz r3, 80088ce <_lseek_r+0x1e> 80088cc: 602b str r3, [r5, #0] 80088ce: bd38 pop {r3, r4, r5, pc} 80088d0: 20000b94 .word 0x20000b94 080088d4 <__ascii_mbtowc>: 80088d4: b082 sub sp, #8 80088d6: b901 cbnz r1, 80088da <__ascii_mbtowc+0x6> 80088d8: a901 add r1, sp, #4 80088da: b142 cbz r2, 80088ee <__ascii_mbtowc+0x1a> 80088dc: b14b cbz r3, 80088f2 <__ascii_mbtowc+0x1e> 80088de: 7813 ldrb r3, [r2, #0] 80088e0: 600b str r3, [r1, #0] 80088e2: 7812 ldrb r2, [r2, #0] 80088e4: 1c10 adds r0, r2, #0 80088e6: bf18 it ne 80088e8: 2001 movne r0, #1 80088ea: b002 add sp, #8 80088ec: 4770 bx lr 80088ee: 4610 mov r0, r2 80088f0: e7fb b.n 80088ea <__ascii_mbtowc+0x16> 80088f2: f06f 0001 mvn.w r0, #1 80088f6: e7f8 b.n 80088ea <__ascii_mbtowc+0x16> 080088f8 <__malloc_lock>: 80088f8: 4770 bx lr 080088fa <__malloc_unlock>: 80088fa: 4770 bx lr 080088fc <_read_r>: 80088fc: b538 push {r3, r4, r5, lr} 80088fe: 4605 mov r5, r0 8008900: 4608 mov r0, r1 8008902: 4611 mov r1, r2 8008904: 2200 movs r2, #0 8008906: 4c05 ldr r4, [pc, #20] ; (800891c <_read_r+0x20>) 8008908: 6022 str r2, [r4, #0] 800890a: 461a mov r2, r3 800890c: f7fd face bl 8005eac <_read> 8008910: 1c43 adds r3, r0, #1 8008912: d102 bne.n 800891a <_read_r+0x1e> 8008914: 6823 ldr r3, [r4, #0] 8008916: b103 cbz r3, 800891a <_read_r+0x1e> 8008918: 602b str r3, [r5, #0] 800891a: bd38 pop {r3, r4, r5, pc} 800891c: 20000b94 .word 0x20000b94 08008920 <__ascii_wctomb>: 8008920: b149 cbz r1, 8008936 <__ascii_wctomb+0x16> 8008922: 2aff cmp r2, #255 ; 0xff 8008924: bf8b itete hi 8008926: 238a movhi r3, #138 ; 0x8a 8008928: 700a strbls r2, [r1, #0] 800892a: 6003 strhi r3, [r0, #0] 800892c: 2001 movls r0, #1 800892e: bf88 it hi 8008930: f04f 30ff movhi.w r0, #4294967295 8008934: 4770 bx lr 8008936: 4608 mov r0, r1 8008938: 4770 bx lr ... 0800893c <_init>: 800893c: b5f8 push {r3, r4, r5, r6, r7, lr} 800893e: bf00 nop 8008940: bcf8 pop {r3, r4, r5, r6, r7} 8008942: bc08 pop {r3} 8008944: 469e mov lr, r3 8008946: 4770 bx lr 08008948 <_fini>: 8008948: b5f8 push {r3, r4, r5, r6, r7, lr} 800894a: bf00 nop 800894c: bcf8 pop {r3, r4, r5, r6, r7} 800894e: bc08 pop {r3} 8008950: 469e mov lr, r3 8008952: 4770 bx lr