Nesslab_200M_System.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000001d0 08000000 08000000 00010000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 0000849c 080001d0 080001d0 000101d0 2**3 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 000005f8 08008670 08008670 00018670 2**3 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 08008c68 08008c68 000201dc 2**0 CONTENTS 4 .ARM 00000000 08008c68 08008c68 000201dc 2**0 CONTENTS 5 .preinit_array 00000000 08008c68 08008c68 000201dc 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 08008c68 08008c68 00018c68 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .fini_array 00000004 08008c6c 08008c6c 00018c6c 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .data 000001dc 20000000 08008c70 00020000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 00000800 200001e0 08008e4c 000201e0 2**3 ALLOC 10 ._user_heap_stack 00000600 200009e0 08008e4c 000209e0 2**0 ALLOC 11 .ARM.attributes 00000029 00000000 00000000 000201dc 2**0 CONTENTS, READONLY 12 .debug_info 0001470f 00000000 00000000 00020205 2**0 CONTENTS, READONLY, DEBUGGING 13 .debug_abbrev 0000362f 00000000 00000000 00034914 2**0 CONTENTS, READONLY, DEBUGGING 14 .debug_aranges 00001150 00000000 00000000 00037f48 2**3 CONTENTS, READONLY, DEBUGGING 15 .debug_ranges 00000fa8 00000000 00000000 00039098 2**3 CONTENTS, READONLY, DEBUGGING 16 .debug_macro 00010f03 00000000 00000000 0003a040 2**0 CONTENTS, READONLY, DEBUGGING 17 .debug_line 0000f527 00000000 00000000 0004af43 2**0 CONTENTS, READONLY, DEBUGGING 18 .debug_str 00058777 00000000 00000000 0005a46a 2**0 CONTENTS, READONLY, DEBUGGING 19 .comment 0000007b 00000000 00000000 000b2be1 2**0 CONTENTS, READONLY 20 .debug_frame 00005458 00000000 00000000 000b2c5c 2**2 CONTENTS, READONLY, DEBUGGING Disassembly of section .text: 080001d0 <__do_global_dtors_aux>: 80001d0: b510 push {r4, lr} 80001d2: 4c05 ldr r4, [pc, #20] ; (80001e8 <__do_global_dtors_aux+0x18>) 80001d4: 7823 ldrb r3, [r4, #0] 80001d6: b933 cbnz r3, 80001e6 <__do_global_dtors_aux+0x16> 80001d8: 4b04 ldr r3, [pc, #16] ; (80001ec <__do_global_dtors_aux+0x1c>) 80001da: b113 cbz r3, 80001e2 <__do_global_dtors_aux+0x12> 80001dc: 4804 ldr r0, [pc, #16] ; (80001f0 <__do_global_dtors_aux+0x20>) 80001de: f3af 8000 nop.w 80001e2: 2301 movs r3, #1 80001e4: 7023 strb r3, [r4, #0] 80001e6: bd10 pop {r4, pc} 80001e8: 200001e0 .word 0x200001e0 80001ec: 00000000 .word 0x00000000 80001f0: 08008654 .word 0x08008654 080001f4 : 80001f4: b508 push {r3, lr} 80001f6: 4b03 ldr r3, [pc, #12] ; (8000204 ) 80001f8: b11b cbz r3, 8000202 80001fa: 4903 ldr r1, [pc, #12] ; (8000208 ) 80001fc: 4803 ldr r0, [pc, #12] ; (800020c ) 80001fe: f3af 8000 nop.w 8000202: bd08 pop {r3, pc} 8000204: 00000000 .word 0x00000000 8000208: 200001e4 .word 0x200001e4 800020c: 08008654 .word 0x08008654 08000210 : 8000210: 4603 mov r3, r0 8000212: f813 2b01 ldrb.w r2, [r3], #1 8000216: 2a00 cmp r2, #0 8000218: d1fb bne.n 8000212 800021a: 1a18 subs r0, r3, r0 800021c: 3801 subs r0, #1 800021e: 4770 bx lr 08000220 <__aeabi_drsub>: 8000220: f081 4100 eor.w r1, r1, #2147483648 ; 0x80000000 8000224: e002 b.n 800022c <__adddf3> 8000226: bf00 nop 08000228 <__aeabi_dsub>: 8000228: f083 4300 eor.w r3, r3, #2147483648 ; 0x80000000 0800022c <__adddf3>: 800022c: b530 push {r4, r5, lr} 800022e: ea4f 0441 mov.w r4, r1, lsl #1 8000232: ea4f 0543 mov.w r5, r3, lsl #1 8000236: ea94 0f05 teq r4, r5 800023a: bf08 it eq 800023c: ea90 0f02 teqeq r0, r2 8000240: bf1f itttt ne 8000242: ea54 0c00 orrsne.w ip, r4, r0 8000246: ea55 0c02 orrsne.w ip, r5, r2 800024a: ea7f 5c64 mvnsne.w ip, r4, asr #21 800024e: ea7f 5c65 mvnsne.w ip, r5, asr #21 8000252: f000 80e2 beq.w 800041a <__adddf3+0x1ee> 8000256: ea4f 5454 mov.w r4, r4, lsr #21 800025a: ebd4 5555 rsbs r5, r4, r5, lsr #21 800025e: bfb8 it lt 8000260: 426d neglt r5, r5 8000262: dd0c ble.n 800027e <__adddf3+0x52> 8000264: 442c add r4, r5 8000266: ea80 0202 eor.w r2, r0, r2 800026a: ea81 0303 eor.w r3, r1, r3 800026e: ea82 0000 eor.w r0, r2, r0 8000272: ea83 0101 eor.w r1, r3, r1 8000276: ea80 0202 eor.w r2, r0, r2 800027a: ea81 0303 eor.w r3, r1, r3 800027e: 2d36 cmp r5, #54 ; 0x36 8000280: bf88 it hi 8000282: bd30 pophi {r4, r5, pc} 8000284: f011 4f00 tst.w r1, #2147483648 ; 0x80000000 8000288: ea4f 3101 mov.w r1, r1, lsl #12 800028c: f44f 1c80 mov.w ip, #1048576 ; 0x100000 8000290: ea4c 3111 orr.w r1, ip, r1, lsr #12 8000294: d002 beq.n 800029c <__adddf3+0x70> 8000296: 4240 negs r0, r0 8000298: eb61 0141 sbc.w r1, r1, r1, lsl #1 800029c: f013 4f00 tst.w r3, #2147483648 ; 0x80000000 80002a0: ea4f 3303 mov.w r3, r3, lsl #12 80002a4: ea4c 3313 orr.w r3, ip, r3, lsr #12 80002a8: d002 beq.n 80002b0 <__adddf3+0x84> 80002aa: 4252 negs r2, r2 80002ac: eb63 0343 sbc.w r3, r3, r3, lsl #1 80002b0: ea94 0f05 teq r4, r5 80002b4: f000 80a7 beq.w 8000406 <__adddf3+0x1da> 80002b8: f1a4 0401 sub.w r4, r4, #1 80002bc: f1d5 0e20 rsbs lr, r5, #32 80002c0: db0d blt.n 80002de <__adddf3+0xb2> 80002c2: fa02 fc0e lsl.w ip, r2, lr 80002c6: fa22 f205 lsr.w r2, r2, r5 80002ca: 1880 adds r0, r0, r2 80002cc: f141 0100 adc.w r1, r1, #0 80002d0: fa03 f20e lsl.w r2, r3, lr 80002d4: 1880 adds r0, r0, r2 80002d6: fa43 f305 asr.w r3, r3, r5 80002da: 4159 adcs r1, r3 80002dc: e00e b.n 80002fc <__adddf3+0xd0> 80002de: f1a5 0520 sub.w r5, r5, #32 80002e2: f10e 0e20 add.w lr, lr, #32 80002e6: 2a01 cmp r2, #1 80002e8: fa03 fc0e lsl.w ip, r3, lr 80002ec: bf28 it cs 80002ee: f04c 0c02 orrcs.w ip, ip, #2 80002f2: fa43 f305 asr.w r3, r3, r5 80002f6: 18c0 adds r0, r0, r3 80002f8: eb51 71e3 adcs.w r1, r1, r3, asr #31 80002fc: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 8000300: d507 bpl.n 8000312 <__adddf3+0xe6> 8000302: f04f 0e00 mov.w lr, #0 8000306: f1dc 0c00 rsbs ip, ip, #0 800030a: eb7e 0000 sbcs.w r0, lr, r0 800030e: eb6e 0101 sbc.w r1, lr, r1 8000312: f5b1 1f80 cmp.w r1, #1048576 ; 0x100000 8000316: d31b bcc.n 8000350 <__adddf3+0x124> 8000318: f5b1 1f00 cmp.w r1, #2097152 ; 0x200000 800031c: d30c bcc.n 8000338 <__adddf3+0x10c> 800031e: 0849 lsrs r1, r1, #1 8000320: ea5f 0030 movs.w r0, r0, rrx 8000324: ea4f 0c3c mov.w ip, ip, rrx 8000328: f104 0401 add.w r4, r4, #1 800032c: ea4f 5244 mov.w r2, r4, lsl #21 8000330: f512 0f80 cmn.w r2, #4194304 ; 0x400000 8000334: f080 809a bcs.w 800046c <__adddf3+0x240> 8000338: f1bc 4f00 cmp.w ip, #2147483648 ; 0x80000000 800033c: bf08 it eq 800033e: ea5f 0c50 movseq.w ip, r0, lsr #1 8000342: f150 0000 adcs.w r0, r0, #0 8000346: eb41 5104 adc.w r1, r1, r4, lsl #20 800034a: ea41 0105 orr.w r1, r1, r5 800034e: bd30 pop {r4, r5, pc} 8000350: ea5f 0c4c movs.w ip, ip, lsl #1 8000354: 4140 adcs r0, r0 8000356: eb41 0101 adc.w r1, r1, r1 800035a: f411 1f80 tst.w r1, #1048576 ; 0x100000 800035e: f1a4 0401 sub.w r4, r4, #1 8000362: d1e9 bne.n 8000338 <__adddf3+0x10c> 8000364: f091 0f00 teq r1, #0 8000368: bf04 itt eq 800036a: 4601 moveq r1, r0 800036c: 2000 moveq r0, #0 800036e: fab1 f381 clz r3, r1 8000372: bf08 it eq 8000374: 3320 addeq r3, #32 8000376: f1a3 030b sub.w r3, r3, #11 800037a: f1b3 0220 subs.w r2, r3, #32 800037e: da0c bge.n 800039a <__adddf3+0x16e> 8000380: 320c adds r2, #12 8000382: dd08 ble.n 8000396 <__adddf3+0x16a> 8000384: f102 0c14 add.w ip, r2, #20 8000388: f1c2 020c rsb r2, r2, #12 800038c: fa01 f00c lsl.w r0, r1, ip 8000390: fa21 f102 lsr.w r1, r1, r2 8000394: e00c b.n 80003b0 <__adddf3+0x184> 8000396: f102 0214 add.w r2, r2, #20 800039a: bfd8 it le 800039c: f1c2 0c20 rsble ip, r2, #32 80003a0: fa01 f102 lsl.w r1, r1, r2 80003a4: fa20 fc0c lsr.w ip, r0, ip 80003a8: bfdc itt le 80003aa: ea41 010c orrle.w r1, r1, ip 80003ae: 4090 lslle r0, r2 80003b0: 1ae4 subs r4, r4, r3 80003b2: bfa2 ittt ge 80003b4: eb01 5104 addge.w r1, r1, r4, lsl #20 80003b8: 4329 orrge r1, r5 80003ba: bd30 popge {r4, r5, pc} 80003bc: ea6f 0404 mvn.w r4, r4 80003c0: 3c1f subs r4, #31 80003c2: da1c bge.n 80003fe <__adddf3+0x1d2> 80003c4: 340c adds r4, #12 80003c6: dc0e bgt.n 80003e6 <__adddf3+0x1ba> 80003c8: f104 0414 add.w r4, r4, #20 80003cc: f1c4 0220 rsb r2, r4, #32 80003d0: fa20 f004 lsr.w r0, r0, r4 80003d4: fa01 f302 lsl.w r3, r1, r2 80003d8: ea40 0003 orr.w r0, r0, r3 80003dc: fa21 f304 lsr.w r3, r1, r4 80003e0: ea45 0103 orr.w r1, r5, r3 80003e4: bd30 pop {r4, r5, pc} 80003e6: f1c4 040c rsb r4, r4, #12 80003ea: f1c4 0220 rsb r2, r4, #32 80003ee: fa20 f002 lsr.w r0, r0, r2 80003f2: fa01 f304 lsl.w r3, r1, r4 80003f6: ea40 0003 orr.w r0, r0, r3 80003fa: 4629 mov r1, r5 80003fc: bd30 pop {r4, r5, pc} 80003fe: fa21 f004 lsr.w r0, r1, r4 8000402: 4629 mov r1, r5 8000404: bd30 pop {r4, r5, pc} 8000406: f094 0f00 teq r4, #0 800040a: f483 1380 eor.w r3, r3, #1048576 ; 0x100000 800040e: bf06 itte eq 8000410: f481 1180 eoreq.w r1, r1, #1048576 ; 0x100000 8000414: 3401 addeq r4, #1 8000416: 3d01 subne r5, #1 8000418: e74e b.n 80002b8 <__adddf3+0x8c> 800041a: ea7f 5c64 mvns.w ip, r4, asr #21 800041e: bf18 it ne 8000420: ea7f 5c65 mvnsne.w ip, r5, asr #21 8000424: d029 beq.n 800047a <__adddf3+0x24e> 8000426: ea94 0f05 teq r4, r5 800042a: bf08 it eq 800042c: ea90 0f02 teqeq r0, r2 8000430: d005 beq.n 800043e <__adddf3+0x212> 8000432: ea54 0c00 orrs.w ip, r4, r0 8000436: bf04 itt eq 8000438: 4619 moveq r1, r3 800043a: 4610 moveq r0, r2 800043c: bd30 pop {r4, r5, pc} 800043e: ea91 0f03 teq r1, r3 8000442: bf1e ittt ne 8000444: 2100 movne r1, #0 8000446: 2000 movne r0, #0 8000448: bd30 popne {r4, r5, pc} 800044a: ea5f 5c54 movs.w ip, r4, lsr #21 800044e: d105 bne.n 800045c <__adddf3+0x230> 8000450: 0040 lsls r0, r0, #1 8000452: 4149 adcs r1, r1 8000454: bf28 it cs 8000456: f041 4100 orrcs.w r1, r1, #2147483648 ; 0x80000000 800045a: bd30 pop {r4, r5, pc} 800045c: f514 0480 adds.w r4, r4, #4194304 ; 0x400000 8000460: bf3c itt cc 8000462: f501 1180 addcc.w r1, r1, #1048576 ; 0x100000 8000466: bd30 popcc {r4, r5, pc} 8000468: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 800046c: f045 41fe orr.w r1, r5, #2130706432 ; 0x7f000000 8000470: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000 8000474: f04f 0000 mov.w r0, #0 8000478: bd30 pop {r4, r5, pc} 800047a: ea7f 5c64 mvns.w ip, r4, asr #21 800047e: bf1a itte ne 8000480: 4619 movne r1, r3 8000482: 4610 movne r0, r2 8000484: ea7f 5c65 mvnseq.w ip, r5, asr #21 8000488: bf1c itt ne 800048a: 460b movne r3, r1 800048c: 4602 movne r2, r0 800048e: ea50 3401 orrs.w r4, r0, r1, lsl #12 8000492: bf06 itte eq 8000494: ea52 3503 orrseq.w r5, r2, r3, lsl #12 8000498: ea91 0f03 teqeq r1, r3 800049c: f441 2100 orrne.w r1, r1, #524288 ; 0x80000 80004a0: bd30 pop {r4, r5, pc} 80004a2: bf00 nop 080004a4 <__aeabi_ui2d>: 80004a4: f090 0f00 teq r0, #0 80004a8: bf04 itt eq 80004aa: 2100 moveq r1, #0 80004ac: 4770 bxeq lr 80004ae: b530 push {r4, r5, lr} 80004b0: f44f 6480 mov.w r4, #1024 ; 0x400 80004b4: f104 0432 add.w r4, r4, #50 ; 0x32 80004b8: f04f 0500 mov.w r5, #0 80004bc: f04f 0100 mov.w r1, #0 80004c0: e750 b.n 8000364 <__adddf3+0x138> 80004c2: bf00 nop 080004c4 <__aeabi_i2d>: 80004c4: f090 0f00 teq r0, #0 80004c8: bf04 itt eq 80004ca: 2100 moveq r1, #0 80004cc: 4770 bxeq lr 80004ce: b530 push {r4, r5, lr} 80004d0: f44f 6480 mov.w r4, #1024 ; 0x400 80004d4: f104 0432 add.w r4, r4, #50 ; 0x32 80004d8: f010 4500 ands.w r5, r0, #2147483648 ; 0x80000000 80004dc: bf48 it mi 80004de: 4240 negmi r0, r0 80004e0: f04f 0100 mov.w r1, #0 80004e4: e73e b.n 8000364 <__adddf3+0x138> 80004e6: bf00 nop 080004e8 <__aeabi_f2d>: 80004e8: 0042 lsls r2, r0, #1 80004ea: ea4f 01e2 mov.w r1, r2, asr #3 80004ee: ea4f 0131 mov.w r1, r1, rrx 80004f2: ea4f 7002 mov.w r0, r2, lsl #28 80004f6: bf1f itttt ne 80004f8: f012 437f andsne.w r3, r2, #4278190080 ; 0xff000000 80004fc: f093 4f7f teqne r3, #4278190080 ; 0xff000000 8000500: f081 5160 eorne.w r1, r1, #939524096 ; 0x38000000 8000504: 4770 bxne lr 8000506: f032 427f bics.w r2, r2, #4278190080 ; 0xff000000 800050a: bf08 it eq 800050c: 4770 bxeq lr 800050e: f093 4f7f teq r3, #4278190080 ; 0xff000000 8000512: bf04 itt eq 8000514: f441 2100 orreq.w r1, r1, #524288 ; 0x80000 8000518: 4770 bxeq lr 800051a: b530 push {r4, r5, lr} 800051c: f44f 7460 mov.w r4, #896 ; 0x380 8000520: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 8000524: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000 8000528: e71c b.n 8000364 <__adddf3+0x138> 800052a: bf00 nop 0800052c <__aeabi_ul2d>: 800052c: ea50 0201 orrs.w r2, r0, r1 8000530: bf08 it eq 8000532: 4770 bxeq lr 8000534: b530 push {r4, r5, lr} 8000536: f04f 0500 mov.w r5, #0 800053a: e00a b.n 8000552 <__aeabi_l2d+0x16> 0800053c <__aeabi_l2d>: 800053c: ea50 0201 orrs.w r2, r0, r1 8000540: bf08 it eq 8000542: 4770 bxeq lr 8000544: b530 push {r4, r5, lr} 8000546: f011 4500 ands.w r5, r1, #2147483648 ; 0x80000000 800054a: d502 bpl.n 8000552 <__aeabi_l2d+0x16> 800054c: 4240 negs r0, r0 800054e: eb61 0141 sbc.w r1, r1, r1, lsl #1 8000552: f44f 6480 mov.w r4, #1024 ; 0x400 8000556: f104 0432 add.w r4, r4, #50 ; 0x32 800055a: ea5f 5c91 movs.w ip, r1, lsr #22 800055e: f43f aed8 beq.w 8000312 <__adddf3+0xe6> 8000562: f04f 0203 mov.w r2, #3 8000566: ea5f 0cdc movs.w ip, ip, lsr #3 800056a: bf18 it ne 800056c: 3203 addne r2, #3 800056e: ea5f 0cdc movs.w ip, ip, lsr #3 8000572: bf18 it ne 8000574: 3203 addne r2, #3 8000576: eb02 02dc add.w r2, r2, ip, lsr #3 800057a: f1c2 0320 rsb r3, r2, #32 800057e: fa00 fc03 lsl.w ip, r0, r3 8000582: fa20 f002 lsr.w r0, r0, r2 8000586: fa01 fe03 lsl.w lr, r1, r3 800058a: ea40 000e orr.w r0, r0, lr 800058e: fa21 f102 lsr.w r1, r1, r2 8000592: 4414 add r4, r2 8000594: e6bd b.n 8000312 <__adddf3+0xe6> 8000596: bf00 nop 08000598 <__aeabi_dmul>: 8000598: b570 push {r4, r5, r6, lr} 800059a: f04f 0cff mov.w ip, #255 ; 0xff 800059e: f44c 6ce0 orr.w ip, ip, #1792 ; 0x700 80005a2: ea1c 5411 ands.w r4, ip, r1, lsr #20 80005a6: bf1d ittte ne 80005a8: ea1c 5513 andsne.w r5, ip, r3, lsr #20 80005ac: ea94 0f0c teqne r4, ip 80005b0: ea95 0f0c teqne r5, ip 80005b4: f000 f8de bleq 8000774 <__aeabi_dmul+0x1dc> 80005b8: 442c add r4, r5 80005ba: ea81 0603 eor.w r6, r1, r3 80005be: ea21 514c bic.w r1, r1, ip, lsl #21 80005c2: ea23 534c bic.w r3, r3, ip, lsl #21 80005c6: ea50 3501 orrs.w r5, r0, r1, lsl #12 80005ca: bf18 it ne 80005cc: ea52 3503 orrsne.w r5, r2, r3, lsl #12 80005d0: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 80005d4: f443 1380 orr.w r3, r3, #1048576 ; 0x100000 80005d8: d038 beq.n 800064c <__aeabi_dmul+0xb4> 80005da: fba0 ce02 umull ip, lr, r0, r2 80005de: f04f 0500 mov.w r5, #0 80005e2: fbe1 e502 umlal lr, r5, r1, r2 80005e6: f006 4200 and.w r2, r6, #2147483648 ; 0x80000000 80005ea: fbe0 e503 umlal lr, r5, r0, r3 80005ee: f04f 0600 mov.w r6, #0 80005f2: fbe1 5603 umlal r5, r6, r1, r3 80005f6: f09c 0f00 teq ip, #0 80005fa: bf18 it ne 80005fc: f04e 0e01 orrne.w lr, lr, #1 8000600: f1a4 04ff sub.w r4, r4, #255 ; 0xff 8000604: f5b6 7f00 cmp.w r6, #512 ; 0x200 8000608: f564 7440 sbc.w r4, r4, #768 ; 0x300 800060c: d204 bcs.n 8000618 <__aeabi_dmul+0x80> 800060e: ea5f 0e4e movs.w lr, lr, lsl #1 8000612: 416d adcs r5, r5 8000614: eb46 0606 adc.w r6, r6, r6 8000618: ea42 21c6 orr.w r1, r2, r6, lsl #11 800061c: ea41 5155 orr.w r1, r1, r5, lsr #21 8000620: ea4f 20c5 mov.w r0, r5, lsl #11 8000624: ea40 505e orr.w r0, r0, lr, lsr #21 8000628: ea4f 2ece mov.w lr, lr, lsl #11 800062c: f1b4 0cfd subs.w ip, r4, #253 ; 0xfd 8000630: bf88 it hi 8000632: f5bc 6fe0 cmphi.w ip, #1792 ; 0x700 8000636: d81e bhi.n 8000676 <__aeabi_dmul+0xde> 8000638: f1be 4f00 cmp.w lr, #2147483648 ; 0x80000000 800063c: bf08 it eq 800063e: ea5f 0e50 movseq.w lr, r0, lsr #1 8000642: f150 0000 adcs.w r0, r0, #0 8000646: eb41 5104 adc.w r1, r1, r4, lsl #20 800064a: bd70 pop {r4, r5, r6, pc} 800064c: f006 4600 and.w r6, r6, #2147483648 ; 0x80000000 8000650: ea46 0101 orr.w r1, r6, r1 8000654: ea40 0002 orr.w r0, r0, r2 8000658: ea81 0103 eor.w r1, r1, r3 800065c: ebb4 045c subs.w r4, r4, ip, lsr #1 8000660: bfc2 ittt gt 8000662: ebd4 050c rsbsgt r5, r4, ip 8000666: ea41 5104 orrgt.w r1, r1, r4, lsl #20 800066a: bd70 popgt {r4, r5, r6, pc} 800066c: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 8000670: f04f 0e00 mov.w lr, #0 8000674: 3c01 subs r4, #1 8000676: f300 80ab bgt.w 80007d0 <__aeabi_dmul+0x238> 800067a: f114 0f36 cmn.w r4, #54 ; 0x36 800067e: bfde ittt le 8000680: 2000 movle r0, #0 8000682: f001 4100 andle.w r1, r1, #2147483648 ; 0x80000000 8000686: bd70 pople {r4, r5, r6, pc} 8000688: f1c4 0400 rsb r4, r4, #0 800068c: 3c20 subs r4, #32 800068e: da35 bge.n 80006fc <__aeabi_dmul+0x164> 8000690: 340c adds r4, #12 8000692: dc1b bgt.n 80006cc <__aeabi_dmul+0x134> 8000694: f104 0414 add.w r4, r4, #20 8000698: f1c4 0520 rsb r5, r4, #32 800069c: fa00 f305 lsl.w r3, r0, r5 80006a0: fa20 f004 lsr.w r0, r0, r4 80006a4: fa01 f205 lsl.w r2, r1, r5 80006a8: ea40 0002 orr.w r0, r0, r2 80006ac: f001 4200 and.w r2, r1, #2147483648 ; 0x80000000 80006b0: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000 80006b4: eb10 70d3 adds.w r0, r0, r3, lsr #31 80006b8: fa21 f604 lsr.w r6, r1, r4 80006bc: eb42 0106 adc.w r1, r2, r6 80006c0: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 80006c4: bf08 it eq 80006c6: ea20 70d3 biceq.w r0, r0, r3, lsr #31 80006ca: bd70 pop {r4, r5, r6, pc} 80006cc: f1c4 040c rsb r4, r4, #12 80006d0: f1c4 0520 rsb r5, r4, #32 80006d4: fa00 f304 lsl.w r3, r0, r4 80006d8: fa20 f005 lsr.w r0, r0, r5 80006dc: fa01 f204 lsl.w r2, r1, r4 80006e0: ea40 0002 orr.w r0, r0, r2 80006e4: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 80006e8: eb10 70d3 adds.w r0, r0, r3, lsr #31 80006ec: f141 0100 adc.w r1, r1, #0 80006f0: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 80006f4: bf08 it eq 80006f6: ea20 70d3 biceq.w r0, r0, r3, lsr #31 80006fa: bd70 pop {r4, r5, r6, pc} 80006fc: f1c4 0520 rsb r5, r4, #32 8000700: fa00 f205 lsl.w r2, r0, r5 8000704: ea4e 0e02 orr.w lr, lr, r2 8000708: fa20 f304 lsr.w r3, r0, r4 800070c: fa01 f205 lsl.w r2, r1, r5 8000710: ea43 0302 orr.w r3, r3, r2 8000714: fa21 f004 lsr.w r0, r1, r4 8000718: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 800071c: fa21 f204 lsr.w r2, r1, r4 8000720: ea20 0002 bic.w r0, r0, r2 8000724: eb00 70d3 add.w r0, r0, r3, lsr #31 8000728: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 800072c: bf08 it eq 800072e: ea20 70d3 biceq.w r0, r0, r3, lsr #31 8000732: bd70 pop {r4, r5, r6, pc} 8000734: f094 0f00 teq r4, #0 8000738: d10f bne.n 800075a <__aeabi_dmul+0x1c2> 800073a: f001 4600 and.w r6, r1, #2147483648 ; 0x80000000 800073e: 0040 lsls r0, r0, #1 8000740: eb41 0101 adc.w r1, r1, r1 8000744: f411 1f80 tst.w r1, #1048576 ; 0x100000 8000748: bf08 it eq 800074a: 3c01 subeq r4, #1 800074c: d0f7 beq.n 800073e <__aeabi_dmul+0x1a6> 800074e: ea41 0106 orr.w r1, r1, r6 8000752: f095 0f00 teq r5, #0 8000756: bf18 it ne 8000758: 4770 bxne lr 800075a: f003 4600 and.w r6, r3, #2147483648 ; 0x80000000 800075e: 0052 lsls r2, r2, #1 8000760: eb43 0303 adc.w r3, r3, r3 8000764: f413 1f80 tst.w r3, #1048576 ; 0x100000 8000768: bf08 it eq 800076a: 3d01 subeq r5, #1 800076c: d0f7 beq.n 800075e <__aeabi_dmul+0x1c6> 800076e: ea43 0306 orr.w r3, r3, r6 8000772: 4770 bx lr 8000774: ea94 0f0c teq r4, ip 8000778: ea0c 5513 and.w r5, ip, r3, lsr #20 800077c: bf18 it ne 800077e: ea95 0f0c teqne r5, ip 8000782: d00c beq.n 800079e <__aeabi_dmul+0x206> 8000784: ea50 0641 orrs.w r6, r0, r1, lsl #1 8000788: bf18 it ne 800078a: ea52 0643 orrsne.w r6, r2, r3, lsl #1 800078e: d1d1 bne.n 8000734 <__aeabi_dmul+0x19c> 8000790: ea81 0103 eor.w r1, r1, r3 8000794: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 8000798: f04f 0000 mov.w r0, #0 800079c: bd70 pop {r4, r5, r6, pc} 800079e: ea50 0641 orrs.w r6, r0, r1, lsl #1 80007a2: bf06 itte eq 80007a4: 4610 moveq r0, r2 80007a6: 4619 moveq r1, r3 80007a8: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80007ac: d019 beq.n 80007e2 <__aeabi_dmul+0x24a> 80007ae: ea94 0f0c teq r4, ip 80007b2: d102 bne.n 80007ba <__aeabi_dmul+0x222> 80007b4: ea50 3601 orrs.w r6, r0, r1, lsl #12 80007b8: d113 bne.n 80007e2 <__aeabi_dmul+0x24a> 80007ba: ea95 0f0c teq r5, ip 80007be: d105 bne.n 80007cc <__aeabi_dmul+0x234> 80007c0: ea52 3603 orrs.w r6, r2, r3, lsl #12 80007c4: bf1c itt ne 80007c6: 4610 movne r0, r2 80007c8: 4619 movne r1, r3 80007ca: d10a bne.n 80007e2 <__aeabi_dmul+0x24a> 80007cc: ea81 0103 eor.w r1, r1, r3 80007d0: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 80007d4: f041 41fe orr.w r1, r1, #2130706432 ; 0x7f000000 80007d8: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000 80007dc: f04f 0000 mov.w r0, #0 80007e0: bd70 pop {r4, r5, r6, pc} 80007e2: f041 41fe orr.w r1, r1, #2130706432 ; 0x7f000000 80007e6: f441 0178 orr.w r1, r1, #16252928 ; 0xf80000 80007ea: bd70 pop {r4, r5, r6, pc} 080007ec <__aeabi_ddiv>: 80007ec: b570 push {r4, r5, r6, lr} 80007ee: f04f 0cff mov.w ip, #255 ; 0xff 80007f2: f44c 6ce0 orr.w ip, ip, #1792 ; 0x700 80007f6: ea1c 5411 ands.w r4, ip, r1, lsr #20 80007fa: bf1d ittte ne 80007fc: ea1c 5513 andsne.w r5, ip, r3, lsr #20 8000800: ea94 0f0c teqne r4, ip 8000804: ea95 0f0c teqne r5, ip 8000808: f000 f8a7 bleq 800095a <__aeabi_ddiv+0x16e> 800080c: eba4 0405 sub.w r4, r4, r5 8000810: ea81 0e03 eor.w lr, r1, r3 8000814: ea52 3503 orrs.w r5, r2, r3, lsl #12 8000818: ea4f 3101 mov.w r1, r1, lsl #12 800081c: f000 8088 beq.w 8000930 <__aeabi_ddiv+0x144> 8000820: ea4f 3303 mov.w r3, r3, lsl #12 8000824: f04f 5580 mov.w r5, #268435456 ; 0x10000000 8000828: ea45 1313 orr.w r3, r5, r3, lsr #4 800082c: ea43 6312 orr.w r3, r3, r2, lsr #24 8000830: ea4f 2202 mov.w r2, r2, lsl #8 8000834: ea45 1511 orr.w r5, r5, r1, lsr #4 8000838: ea45 6510 orr.w r5, r5, r0, lsr #24 800083c: ea4f 2600 mov.w r6, r0, lsl #8 8000840: f00e 4100 and.w r1, lr, #2147483648 ; 0x80000000 8000844: 429d cmp r5, r3 8000846: bf08 it eq 8000848: 4296 cmpeq r6, r2 800084a: f144 04fd adc.w r4, r4, #253 ; 0xfd 800084e: f504 7440 add.w r4, r4, #768 ; 0x300 8000852: d202 bcs.n 800085a <__aeabi_ddiv+0x6e> 8000854: 085b lsrs r3, r3, #1 8000856: ea4f 0232 mov.w r2, r2, rrx 800085a: 1ab6 subs r6, r6, r2 800085c: eb65 0503 sbc.w r5, r5, r3 8000860: 085b lsrs r3, r3, #1 8000862: ea4f 0232 mov.w r2, r2, rrx 8000866: f44f 1080 mov.w r0, #1048576 ; 0x100000 800086a: f44f 2c00 mov.w ip, #524288 ; 0x80000 800086e: ebb6 0e02 subs.w lr, r6, r2 8000872: eb75 0e03 sbcs.w lr, r5, r3 8000876: bf22 ittt cs 8000878: 1ab6 subcs r6, r6, r2 800087a: 4675 movcs r5, lr 800087c: ea40 000c orrcs.w r0, r0, ip 8000880: 085b lsrs r3, r3, #1 8000882: ea4f 0232 mov.w r2, r2, rrx 8000886: ebb6 0e02 subs.w lr, r6, r2 800088a: eb75 0e03 sbcs.w lr, r5, r3 800088e: bf22 ittt cs 8000890: 1ab6 subcs r6, r6, r2 8000892: 4675 movcs r5, lr 8000894: ea40 005c orrcs.w r0, r0, ip, lsr #1 8000898: 085b lsrs r3, r3, #1 800089a: ea4f 0232 mov.w r2, r2, rrx 800089e: ebb6 0e02 subs.w lr, r6, r2 80008a2: eb75 0e03 sbcs.w lr, r5, r3 80008a6: bf22 ittt cs 80008a8: 1ab6 subcs r6, r6, r2 80008aa: 4675 movcs r5, lr 80008ac: ea40 009c orrcs.w r0, r0, ip, lsr #2 80008b0: 085b lsrs r3, r3, #1 80008b2: ea4f 0232 mov.w r2, r2, rrx 80008b6: ebb6 0e02 subs.w lr, r6, r2 80008ba: eb75 0e03 sbcs.w lr, r5, r3 80008be: bf22 ittt cs 80008c0: 1ab6 subcs r6, r6, r2 80008c2: 4675 movcs r5, lr 80008c4: ea40 00dc orrcs.w r0, r0, ip, lsr #3 80008c8: ea55 0e06 orrs.w lr, r5, r6 80008cc: d018 beq.n 8000900 <__aeabi_ddiv+0x114> 80008ce: ea4f 1505 mov.w r5, r5, lsl #4 80008d2: ea45 7516 orr.w r5, r5, r6, lsr #28 80008d6: ea4f 1606 mov.w r6, r6, lsl #4 80008da: ea4f 03c3 mov.w r3, r3, lsl #3 80008de: ea43 7352 orr.w r3, r3, r2, lsr #29 80008e2: ea4f 02c2 mov.w r2, r2, lsl #3 80008e6: ea5f 1c1c movs.w ip, ip, lsr #4 80008ea: d1c0 bne.n 800086e <__aeabi_ddiv+0x82> 80008ec: f411 1f80 tst.w r1, #1048576 ; 0x100000 80008f0: d10b bne.n 800090a <__aeabi_ddiv+0x11e> 80008f2: ea41 0100 orr.w r1, r1, r0 80008f6: f04f 0000 mov.w r0, #0 80008fa: f04f 4c00 mov.w ip, #2147483648 ; 0x80000000 80008fe: e7b6 b.n 800086e <__aeabi_ddiv+0x82> 8000900: f411 1f80 tst.w r1, #1048576 ; 0x100000 8000904: bf04 itt eq 8000906: 4301 orreq r1, r0 8000908: 2000 moveq r0, #0 800090a: f1b4 0cfd subs.w ip, r4, #253 ; 0xfd 800090e: bf88 it hi 8000910: f5bc 6fe0 cmphi.w ip, #1792 ; 0x700 8000914: f63f aeaf bhi.w 8000676 <__aeabi_dmul+0xde> 8000918: ebb5 0c03 subs.w ip, r5, r3 800091c: bf04 itt eq 800091e: ebb6 0c02 subseq.w ip, r6, r2 8000922: ea5f 0c50 movseq.w ip, r0, lsr #1 8000926: f150 0000 adcs.w r0, r0, #0 800092a: eb41 5104 adc.w r1, r1, r4, lsl #20 800092e: bd70 pop {r4, r5, r6, pc} 8000930: f00e 4e00 and.w lr, lr, #2147483648 ; 0x80000000 8000934: ea4e 3111 orr.w r1, lr, r1, lsr #12 8000938: eb14 045c adds.w r4, r4, ip, lsr #1 800093c: bfc2 ittt gt 800093e: ebd4 050c rsbsgt r5, r4, ip 8000942: ea41 5104 orrgt.w r1, r1, r4, lsl #20 8000946: bd70 popgt {r4, r5, r6, pc} 8000948: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 800094c: f04f 0e00 mov.w lr, #0 8000950: 3c01 subs r4, #1 8000952: e690 b.n 8000676 <__aeabi_dmul+0xde> 8000954: ea45 0e06 orr.w lr, r5, r6 8000958: e68d b.n 8000676 <__aeabi_dmul+0xde> 800095a: ea0c 5513 and.w r5, ip, r3, lsr #20 800095e: ea94 0f0c teq r4, ip 8000962: bf08 it eq 8000964: ea95 0f0c teqeq r5, ip 8000968: f43f af3b beq.w 80007e2 <__aeabi_dmul+0x24a> 800096c: ea94 0f0c teq r4, ip 8000970: d10a bne.n 8000988 <__aeabi_ddiv+0x19c> 8000972: ea50 3401 orrs.w r4, r0, r1, lsl #12 8000976: f47f af34 bne.w 80007e2 <__aeabi_dmul+0x24a> 800097a: ea95 0f0c teq r5, ip 800097e: f47f af25 bne.w 80007cc <__aeabi_dmul+0x234> 8000982: 4610 mov r0, r2 8000984: 4619 mov r1, r3 8000986: e72c b.n 80007e2 <__aeabi_dmul+0x24a> 8000988: ea95 0f0c teq r5, ip 800098c: d106 bne.n 800099c <__aeabi_ddiv+0x1b0> 800098e: ea52 3503 orrs.w r5, r2, r3, lsl #12 8000992: f43f aefd beq.w 8000790 <__aeabi_dmul+0x1f8> 8000996: 4610 mov r0, r2 8000998: 4619 mov r1, r3 800099a: e722 b.n 80007e2 <__aeabi_dmul+0x24a> 800099c: ea50 0641 orrs.w r6, r0, r1, lsl #1 80009a0: bf18 it ne 80009a2: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80009a6: f47f aec5 bne.w 8000734 <__aeabi_dmul+0x19c> 80009aa: ea50 0441 orrs.w r4, r0, r1, lsl #1 80009ae: f47f af0d bne.w 80007cc <__aeabi_dmul+0x234> 80009b2: ea52 0543 orrs.w r5, r2, r3, lsl #1 80009b6: f47f aeeb bne.w 8000790 <__aeabi_dmul+0x1f8> 80009ba: e712 b.n 80007e2 <__aeabi_dmul+0x24a> 080009bc <__gedf2>: 80009bc: f04f 3cff mov.w ip, #4294967295 80009c0: e006 b.n 80009d0 <__cmpdf2+0x4> 80009c2: bf00 nop 080009c4 <__ledf2>: 80009c4: f04f 0c01 mov.w ip, #1 80009c8: e002 b.n 80009d0 <__cmpdf2+0x4> 80009ca: bf00 nop 080009cc <__cmpdf2>: 80009cc: f04f 0c01 mov.w ip, #1 80009d0: f84d cd04 str.w ip, [sp, #-4]! 80009d4: ea4f 0c41 mov.w ip, r1, lsl #1 80009d8: ea7f 5c6c mvns.w ip, ip, asr #21 80009dc: ea4f 0c43 mov.w ip, r3, lsl #1 80009e0: bf18 it ne 80009e2: ea7f 5c6c mvnsne.w ip, ip, asr #21 80009e6: d01b beq.n 8000a20 <__cmpdf2+0x54> 80009e8: b001 add sp, #4 80009ea: ea50 0c41 orrs.w ip, r0, r1, lsl #1 80009ee: bf0c ite eq 80009f0: ea52 0c43 orrseq.w ip, r2, r3, lsl #1 80009f4: ea91 0f03 teqne r1, r3 80009f8: bf02 ittt eq 80009fa: ea90 0f02 teqeq r0, r2 80009fe: 2000 moveq r0, #0 8000a00: 4770 bxeq lr 8000a02: f110 0f00 cmn.w r0, #0 8000a06: ea91 0f03 teq r1, r3 8000a0a: bf58 it pl 8000a0c: 4299 cmppl r1, r3 8000a0e: bf08 it eq 8000a10: 4290 cmpeq r0, r2 8000a12: bf2c ite cs 8000a14: 17d8 asrcs r0, r3, #31 8000a16: ea6f 70e3 mvncc.w r0, r3, asr #31 8000a1a: f040 0001 orr.w r0, r0, #1 8000a1e: 4770 bx lr 8000a20: ea4f 0c41 mov.w ip, r1, lsl #1 8000a24: ea7f 5c6c mvns.w ip, ip, asr #21 8000a28: d102 bne.n 8000a30 <__cmpdf2+0x64> 8000a2a: ea50 3c01 orrs.w ip, r0, r1, lsl #12 8000a2e: d107 bne.n 8000a40 <__cmpdf2+0x74> 8000a30: ea4f 0c43 mov.w ip, r3, lsl #1 8000a34: ea7f 5c6c mvns.w ip, ip, asr #21 8000a38: d1d6 bne.n 80009e8 <__cmpdf2+0x1c> 8000a3a: ea52 3c03 orrs.w ip, r2, r3, lsl #12 8000a3e: d0d3 beq.n 80009e8 <__cmpdf2+0x1c> 8000a40: f85d 0b04 ldr.w r0, [sp], #4 8000a44: 4770 bx lr 8000a46: bf00 nop 08000a48 <__aeabi_cdrcmple>: 8000a48: 4684 mov ip, r0 8000a4a: 4610 mov r0, r2 8000a4c: 4662 mov r2, ip 8000a4e: 468c mov ip, r1 8000a50: 4619 mov r1, r3 8000a52: 4663 mov r3, ip 8000a54: e000 b.n 8000a58 <__aeabi_cdcmpeq> 8000a56: bf00 nop 08000a58 <__aeabi_cdcmpeq>: 8000a58: b501 push {r0, lr} 8000a5a: f7ff ffb7 bl 80009cc <__cmpdf2> 8000a5e: 2800 cmp r0, #0 8000a60: bf48 it mi 8000a62: f110 0f00 cmnmi.w r0, #0 8000a66: bd01 pop {r0, pc} 08000a68 <__aeabi_dcmpeq>: 8000a68: f84d ed08 str.w lr, [sp, #-8]! 8000a6c: f7ff fff4 bl 8000a58 <__aeabi_cdcmpeq> 8000a70: bf0c ite eq 8000a72: 2001 moveq r0, #1 8000a74: 2000 movne r0, #0 8000a76: f85d fb08 ldr.w pc, [sp], #8 8000a7a: bf00 nop 08000a7c <__aeabi_dcmplt>: 8000a7c: f84d ed08 str.w lr, [sp, #-8]! 8000a80: f7ff ffea bl 8000a58 <__aeabi_cdcmpeq> 8000a84: bf34 ite cc 8000a86: 2001 movcc r0, #1 8000a88: 2000 movcs r0, #0 8000a8a: f85d fb08 ldr.w pc, [sp], #8 8000a8e: bf00 nop 08000a90 <__aeabi_dcmple>: 8000a90: f84d ed08 str.w lr, [sp, #-8]! 8000a94: f7ff ffe0 bl 8000a58 <__aeabi_cdcmpeq> 8000a98: bf94 ite ls 8000a9a: 2001 movls r0, #1 8000a9c: 2000 movhi r0, #0 8000a9e: f85d fb08 ldr.w pc, [sp], #8 8000aa2: bf00 nop 08000aa4 <__aeabi_dcmpge>: 8000aa4: f84d ed08 str.w lr, [sp, #-8]! 8000aa8: f7ff ffce bl 8000a48 <__aeabi_cdrcmple> 8000aac: bf94 ite ls 8000aae: 2001 movls r0, #1 8000ab0: 2000 movhi r0, #0 8000ab2: f85d fb08 ldr.w pc, [sp], #8 8000ab6: bf00 nop 08000ab8 <__aeabi_dcmpgt>: 8000ab8: f84d ed08 str.w lr, [sp, #-8]! 8000abc: f7ff ffc4 bl 8000a48 <__aeabi_cdrcmple> 8000ac0: bf34 ite cc 8000ac2: 2001 movcc r0, #1 8000ac4: 2000 movcs r0, #0 8000ac6: f85d fb08 ldr.w pc, [sp], #8 8000aca: bf00 nop 08000acc <__aeabi_dcmpun>: 8000acc: ea4f 0c41 mov.w ip, r1, lsl #1 8000ad0: ea7f 5c6c mvns.w ip, ip, asr #21 8000ad4: d102 bne.n 8000adc <__aeabi_dcmpun+0x10> 8000ad6: ea50 3c01 orrs.w ip, r0, r1, lsl #12 8000ada: d10a bne.n 8000af2 <__aeabi_dcmpun+0x26> 8000adc: ea4f 0c43 mov.w ip, r3, lsl #1 8000ae0: ea7f 5c6c mvns.w ip, ip, asr #21 8000ae4: d102 bne.n 8000aec <__aeabi_dcmpun+0x20> 8000ae6: ea52 3c03 orrs.w ip, r2, r3, lsl #12 8000aea: d102 bne.n 8000af2 <__aeabi_dcmpun+0x26> 8000aec: f04f 0000 mov.w r0, #0 8000af0: 4770 bx lr 8000af2: f04f 0001 mov.w r0, #1 8000af6: 4770 bx lr 08000af8 <__aeabi_d2iz>: 8000af8: ea4f 0241 mov.w r2, r1, lsl #1 8000afc: f512 1200 adds.w r2, r2, #2097152 ; 0x200000 8000b00: d215 bcs.n 8000b2e <__aeabi_d2iz+0x36> 8000b02: d511 bpl.n 8000b28 <__aeabi_d2iz+0x30> 8000b04: f46f 7378 mvn.w r3, #992 ; 0x3e0 8000b08: ebb3 5262 subs.w r2, r3, r2, asr #21 8000b0c: d912 bls.n 8000b34 <__aeabi_d2iz+0x3c> 8000b0e: ea4f 23c1 mov.w r3, r1, lsl #11 8000b12: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 8000b16: ea43 5350 orr.w r3, r3, r0, lsr #21 8000b1a: f011 4f00 tst.w r1, #2147483648 ; 0x80000000 8000b1e: fa23 f002 lsr.w r0, r3, r2 8000b22: bf18 it ne 8000b24: 4240 negne r0, r0 8000b26: 4770 bx lr 8000b28: f04f 0000 mov.w r0, #0 8000b2c: 4770 bx lr 8000b2e: ea50 3001 orrs.w r0, r0, r1, lsl #12 8000b32: d105 bne.n 8000b40 <__aeabi_d2iz+0x48> 8000b34: f011 4000 ands.w r0, r1, #2147483648 ; 0x80000000 8000b38: bf08 it eq 8000b3a: f06f 4000 mvneq.w r0, #2147483648 ; 0x80000000 8000b3e: 4770 bx lr 8000b40: f04f 0000 mov.w r0, #0 8000b44: 4770 bx lr 8000b46: bf00 nop 08000b48 <__aeabi_d2uiz>: 8000b48: 004a lsls r2, r1, #1 8000b4a: d211 bcs.n 8000b70 <__aeabi_d2uiz+0x28> 8000b4c: f512 1200 adds.w r2, r2, #2097152 ; 0x200000 8000b50: d211 bcs.n 8000b76 <__aeabi_d2uiz+0x2e> 8000b52: d50d bpl.n 8000b70 <__aeabi_d2uiz+0x28> 8000b54: f46f 7378 mvn.w r3, #992 ; 0x3e0 8000b58: ebb3 5262 subs.w r2, r3, r2, asr #21 8000b5c: d40e bmi.n 8000b7c <__aeabi_d2uiz+0x34> 8000b5e: ea4f 23c1 mov.w r3, r1, lsl #11 8000b62: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 8000b66: ea43 5350 orr.w r3, r3, r0, lsr #21 8000b6a: fa23 f002 lsr.w r0, r3, r2 8000b6e: 4770 bx lr 8000b70: f04f 0000 mov.w r0, #0 8000b74: 4770 bx lr 8000b76: ea50 3001 orrs.w r0, r0, r1, lsl #12 8000b7a: d102 bne.n 8000b82 <__aeabi_d2uiz+0x3a> 8000b7c: f04f 30ff mov.w r0, #4294967295 8000b80: 4770 bx lr 8000b82: f04f 0000 mov.w r0, #0 8000b86: 4770 bx lr 08000b88 <__aeabi_d2f>: 8000b88: ea4f 0241 mov.w r2, r1, lsl #1 8000b8c: f1b2 43e0 subs.w r3, r2, #1879048192 ; 0x70000000 8000b90: bf24 itt cs 8000b92: f5b3 1c00 subscs.w ip, r3, #2097152 ; 0x200000 8000b96: f1dc 5cfe rsbscs ip, ip, #532676608 ; 0x1fc00000 8000b9a: d90d bls.n 8000bb8 <__aeabi_d2f+0x30> 8000b9c: f001 4c00 and.w ip, r1, #2147483648 ; 0x80000000 8000ba0: ea4f 02c0 mov.w r2, r0, lsl #3 8000ba4: ea4c 7050 orr.w r0, ip, r0, lsr #29 8000ba8: f1b2 4f00 cmp.w r2, #2147483648 ; 0x80000000 8000bac: eb40 0083 adc.w r0, r0, r3, lsl #2 8000bb0: bf08 it eq 8000bb2: f020 0001 biceq.w r0, r0, #1 8000bb6: 4770 bx lr 8000bb8: f011 4f80 tst.w r1, #1073741824 ; 0x40000000 8000bbc: d121 bne.n 8000c02 <__aeabi_d2f+0x7a> 8000bbe: f113 7238 adds.w r2, r3, #48234496 ; 0x2e00000 8000bc2: bfbc itt lt 8000bc4: f001 4000 andlt.w r0, r1, #2147483648 ; 0x80000000 8000bc8: 4770 bxlt lr 8000bca: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 8000bce: ea4f 5252 mov.w r2, r2, lsr #21 8000bd2: f1c2 0218 rsb r2, r2, #24 8000bd6: f1c2 0c20 rsb ip, r2, #32 8000bda: fa10 f30c lsls.w r3, r0, ip 8000bde: fa20 f002 lsr.w r0, r0, r2 8000be2: bf18 it ne 8000be4: f040 0001 orrne.w r0, r0, #1 8000be8: ea4f 23c1 mov.w r3, r1, lsl #11 8000bec: ea4f 23d3 mov.w r3, r3, lsr #11 8000bf0: fa03 fc0c lsl.w ip, r3, ip 8000bf4: ea40 000c orr.w r0, r0, ip 8000bf8: fa23 f302 lsr.w r3, r3, r2 8000bfc: ea4f 0343 mov.w r3, r3, lsl #1 8000c00: e7cc b.n 8000b9c <__aeabi_d2f+0x14> 8000c02: ea7f 5362 mvns.w r3, r2, asr #21 8000c06: d107 bne.n 8000c18 <__aeabi_d2f+0x90> 8000c08: ea50 3301 orrs.w r3, r0, r1, lsl #12 8000c0c: bf1e ittt ne 8000c0e: f04f 40fe movne.w r0, #2130706432 ; 0x7f000000 8000c12: f440 0040 orrne.w r0, r0, #12582912 ; 0xc00000 8000c16: 4770 bxne lr 8000c18: f001 4000 and.w r0, r1, #2147483648 ; 0x80000000 8000c1c: f040 40fe orr.w r0, r0, #2130706432 ; 0x7f000000 8000c20: f440 0000 orr.w r0, r0, #8388608 ; 0x800000 8000c24: 4770 bx lr 8000c26: bf00 nop 08000c28 : volatile uint8_t NessLab_TxData[200] = {0,}; uint8_t Flash_DataArray[200] = {0,}; uint8_t DB_Define[100]; void NessLab_Init(){ 8000c28: b580 push {r7, lr} 8000c2a: af00 add r7, sp, #0 FLASH_Read_Func(FLASH_USER_USE_START_ADDR + 2,&DB_Define[0],104); 8000c2c: 2268 movs r2, #104 ; 0x68 8000c2e: 4906 ldr r1, [pc, #24] ; (8000c48 ) 8000c30: 4806 ldr r0, [pc, #24] ; (8000c4c ) 8000c32: f000 fecb bl 80019cc HAL_GPIO_WritePin(PAU_RESET_GPIO_Port,PAU_RESET_Pin, GPIO_PIN_SET); 8000c36: 2201 movs r2, #1 8000c38: f44f 4180 mov.w r1, #16384 ; 0x4000 8000c3c: 4804 ldr r0, [pc, #16] ; (8000c50 ) 8000c3e: f002 fc5c bl 80034fa } 8000c42: bf00 nop 8000c44: bd80 pop {r7, pc} 8000c46: bf00 nop 8000c48: 20000518 .word 0x20000518 8000c4c: 0800ff3a .word 0x0800ff3a 8000c50: 40010c00 .word 0x40010c00 8000c54: 00000000 .word 0x00000000 08000c58 : double Round_Function(double value){ 8000c58: b590 push {r4, r7, lr} 8000c5a: b085 sub sp, #20 8000c5c: af00 add r7, sp, #0 8000c5e: e9c7 0100 strd r0, r1, [r7] double val = value * 100; 8000c62: f04f 0200 mov.w r2, #0 8000c66: 4b2a ldr r3, [pc, #168] ; (8000d10 ) 8000c68: e9d7 0100 ldrd r0, r1, [r7] 8000c6c: f7ff fc94 bl 8000598 <__aeabi_dmul> 8000c70: 4603 mov r3, r0 8000c72: 460c mov r4, r1 8000c74: e9c7 3402 strd r3, r4, [r7, #8] val = (int)(val + 0.5); 8000c78: f04f 0200 mov.w r2, #0 8000c7c: 4b25 ldr r3, [pc, #148] ; (8000d14 ) 8000c7e: e9d7 0102 ldrd r0, r1, [r7, #8] 8000c82: f7ff fad3 bl 800022c <__adddf3> 8000c86: 4603 mov r3, r0 8000c88: 460c mov r4, r1 8000c8a: 4618 mov r0, r3 8000c8c: 4621 mov r1, r4 8000c8e: f7ff ff33 bl 8000af8 <__aeabi_d2iz> 8000c92: 4603 mov r3, r0 8000c94: 4618 mov r0, r3 8000c96: f7ff fc15 bl 80004c4 <__aeabi_i2d> 8000c9a: 4603 mov r3, r0 8000c9c: 460c mov r4, r1 8000c9e: e9c7 3402 strd r3, r4, [r7, #8] val *= 0.1; 8000ca2: a319 add r3, pc, #100 ; (adr r3, 8000d08 ) 8000ca4: e9d3 2300 ldrd r2, r3, [r3] 8000ca8: e9d7 0102 ldrd r0, r1, [r7, #8] 8000cac: f7ff fc74 bl 8000598 <__aeabi_dmul> 8000cb0: 4603 mov r3, r0 8000cb2: 460c mov r4, r1 8000cb4: e9c7 3402 strd r3, r4, [r7, #8] val = (int)(val + 0.5); 8000cb8: f04f 0200 mov.w r2, #0 8000cbc: 4b15 ldr r3, [pc, #84] ; (8000d14 ) 8000cbe: e9d7 0102 ldrd r0, r1, [r7, #8] 8000cc2: f7ff fab3 bl 800022c <__adddf3> 8000cc6: 4603 mov r3, r0 8000cc8: 460c mov r4, r1 8000cca: 4618 mov r0, r3 8000ccc: 4621 mov r1, r4 8000cce: f7ff ff13 bl 8000af8 <__aeabi_d2iz> 8000cd2: 4603 mov r3, r0 8000cd4: 4618 mov r0, r3 8000cd6: f7ff fbf5 bl 80004c4 <__aeabi_i2d> 8000cda: 4603 mov r3, r0 8000cdc: 460c mov r4, r1 8000cde: e9c7 3402 strd r3, r4, [r7, #8] val *= 0.1; 8000ce2: a309 add r3, pc, #36 ; (adr r3, 8000d08 ) 8000ce4: e9d3 2300 ldrd r2, r3, [r3] 8000ce8: e9d7 0102 ldrd r0, r1, [r7, #8] 8000cec: f7ff fc54 bl 8000598 <__aeabi_dmul> 8000cf0: 4603 mov r3, r0 8000cf2: 460c mov r4, r1 8000cf4: e9c7 3402 strd r3, r4, [r7, #8] return val; 8000cf8: e9d7 3402 ldrd r3, r4, [r7, #8] } 8000cfc: 4618 mov r0, r3 8000cfe: 4621 mov r1, r4 8000d00: 3714 adds r7, #20 8000d02: 46bd mov sp, r7 8000d04: bd90 pop {r4, r7, pc} 8000d06: bf00 nop 8000d08: 9999999a .word 0x9999999a 8000d0c: 3fb99999 .word 0x3fb99999 8000d10: 40590000 .word 0x40590000 8000d14: 3fe00000 .word 0x3fe00000 08000d18 : uint16_t Absolute_value_Convert(int16_t val){ 8000d18: b480 push {r7} 8000d1a: b083 sub sp, #12 8000d1c: af00 add r7, sp, #0 8000d1e: 4603 mov r3, r0 8000d20: 80fb strh r3, [r7, #6] if(val < 0) 8000d22: f9b7 3006 ldrsh.w r3, [r7, #6] 8000d26: 2b00 cmp r3, #0 8000d28: da03 bge.n 8000d32 val *= -1; 8000d2a: 88fb ldrh r3, [r7, #6] 8000d2c: 425b negs r3, r3 8000d2e: b29b uxth r3, r3 8000d30: 80fb strh r3, [r7, #6] return val; 8000d32: 88fb ldrh r3, [r7, #6] } 8000d34: 4618 mov r0, r3 8000d36: 370c adds r7, #12 8000d38: 46bd mov sp, r7 8000d3a: bc80 pop {r7} 8000d3c: 4770 bx lr ... 08000d40 : uint8_t NessLab_Adc_Convert_db() // ?占쏙옙湲고븿?占쏙옙 { 8000d40: b590 push {r4, r7, lr} 8000d42: b08b sub sp, #44 ; 0x2c 8000d44: af00 add r7, sp, #0 double CurrAdc = (float)((Currstatus.DownLink_Forward_Det_H << 8 | Currstatus.DownLink_Forward_Det_L)*0.001); 8000d46: 4b4c ldr r3, [pc, #304] ; (8000e78 ) 8000d48: 79db ldrb r3, [r3, #7] 8000d4a: 021b lsls r3, r3, #8 8000d4c: 4a4a ldr r2, [pc, #296] ; (8000e78 ) 8000d4e: 7a12 ldrb r2, [r2, #8] 8000d50: 4313 orrs r3, r2 8000d52: 4618 mov r0, r3 8000d54: f7ff fbb6 bl 80004c4 <__aeabi_i2d> 8000d58: a345 add r3, pc, #276 ; (adr r3, 8000e70 ) 8000d5a: e9d3 2300 ldrd r2, r3, [r3] 8000d5e: f7ff fc1b bl 8000598 <__aeabi_dmul> 8000d62: 4603 mov r3, r0 8000d64: 460c mov r4, r1 8000d66: 4618 mov r0, r3 8000d68: 4621 mov r1, r4 8000d6a: f7ff ff0d bl 8000b88 <__aeabi_d2f> 8000d6e: 4603 mov r3, r0 8000d70: 4618 mov r0, r3 8000d72: f7ff fbb9 bl 80004e8 <__aeabi_f2d> 8000d76: 4603 mov r3, r0 8000d78: 460c mov r4, r1 8000d7a: e9c7 3406 strd r3, r4, [r7, #24] double TableVal = 0; 8000d7e: f04f 0300 mov.w r3, #0 8000d82: f04f 0400 mov.w r4, #0 8000d86: e9c7 3404 strd r3, r4, [r7, #16] float ret = 0; 8000d8a: f04f 0300 mov.w r3, #0 8000d8e: 60fb str r3, [r7, #12] int16_t calc_val = 0,Prev_calc_val = 3300 ; 8000d90: 2300 movs r3, #0 8000d92: 817b strh r3, [r7, #10] 8000d94: f640 43e4 movw r3, #3300 ; 0xce4 8000d98: 84fb strh r3, [r7, #38] ; 0x26 uint8_t Curr_DB = 0 ; 8000d9a: 2300 movs r3, #0 8000d9c: f887 3025 strb.w r3, [r7, #37] ; 0x25 uint16_t CurrAdc_Temp = 0,TableVal_Temp = 0; 8000da0: 2300 movs r3, #0 8000da2: 813b strh r3, [r7, #8] 8000da4: 2300 movs r3, #0 8000da6: 80fb strh r3, [r7, #6] ret = Round_Function(CurrAdc); 8000da8: e9d7 0106 ldrd r0, r1, [r7, #24] 8000dac: f7ff ff54 bl 8000c58 8000db0: 4603 mov r3, r0 8000db2: 460c mov r4, r1 8000db4: 4618 mov r0, r3 8000db6: 4621 mov r1, r4 8000db8: f7ff fee6 bl 8000b88 <__aeabi_d2f> 8000dbc: 4603 mov r3, r0 8000dbe: 60fb str r3, [r7, #12] // CurrAdc *= 1000; CurrAdc_Temp = CurrAdc * 1000; 8000dc0: f04f 0200 mov.w r2, #0 8000dc4: 4b2d ldr r3, [pc, #180] ; (8000e7c ) 8000dc6: e9d7 0106 ldrd r0, r1, [r7, #24] 8000dca: f7ff fbe5 bl 8000598 <__aeabi_dmul> 8000dce: 4603 mov r3, r0 8000dd0: 460c mov r4, r1 8000dd2: 4618 mov r0, r3 8000dd4: 4621 mov r1, r4 8000dd6: f7ff feb7 bl 8000b48 <__aeabi_d2uiz> 8000dda: 4603 mov r3, r0 8000ddc: 813b strh r3, [r7, #8] // CurrAdc_Temp = 155; // CurrAdc_Temp = 156; for(int i = 0; i <= 50; i++){ 8000dde: 2300 movs r3, #0 8000de0: 623b str r3, [r7, #32] 8000de2: e03a b.n 8000e5a TableVal_Temp = ((DB_Define[i * 2] << 8 | DB_Define[(i * 2)+ 1])); 8000de4: 6a3b ldr r3, [r7, #32] 8000de6: 005b lsls r3, r3, #1 8000de8: 4a25 ldr r2, [pc, #148] ; (8000e80 ) 8000dea: 5cd3 ldrb r3, [r2, r3] 8000dec: 021b lsls r3, r3, #8 8000dee: b21a sxth r2, r3 8000df0: 6a3b ldr r3, [r7, #32] 8000df2: 005b lsls r3, r3, #1 8000df4: 3301 adds r3, #1 8000df6: 4922 ldr r1, [pc, #136] ; (8000e80 ) 8000df8: 5ccb ldrb r3, [r1, r3] 8000dfa: b21b sxth r3, r3 8000dfc: 4313 orrs r3, r2 8000dfe: b21b sxth r3, r3 8000e00: 80fb strh r3, [r7, #6] if(TableVal_Temp == 0) 8000e02: 88fb ldrh r3, [r7, #6] 8000e04: 2b00 cmp r3, #0 8000e06: d024 beq.n 8000e52 continue; calc_val = CurrAdc_Temp - TableVal_Temp; 8000e08: 893a ldrh r2, [r7, #8] 8000e0a: 88fb ldrh r3, [r7, #6] 8000e0c: 1ad3 subs r3, r2, r3 8000e0e: b29b uxth r3, r3 8000e10: 817b strh r3, [r7, #10] calc_val = Absolute_value_Convert(calc_val); 8000e12: f9b7 300a ldrsh.w r3, [r7, #10] 8000e16: 4618 mov r0, r3 8000e18: f7ff ff7e bl 8000d18 8000e1c: 4603 mov r3, r0 8000e1e: 817b strh r3, [r7, #10] // printf("%d - %d calc_val : %d \r\n",CurrAdc_Temp,TableVal_Temp,calc_val); if(Prev_calc_val > calc_val && TableVal_Temp != 0){ 8000e20: f9b7 2026 ldrsh.w r2, [r7, #38] ; 0x26 8000e24: f9b7 300a ldrsh.w r3, [r7, #10] 8000e28: 429a cmp r2, r3 8000e2a: dd13 ble.n 8000e54 8000e2c: 88fb ldrh r3, [r7, #6] 8000e2e: 2b00 cmp r3, #0 8000e30: d010 beq.n 8000e54 Prev_calc_val = calc_val; 8000e32: 897b ldrh r3, [r7, #10] 8000e34: 84fb strh r3, [r7, #38] ; 0x26 if(CurrAdc_Temp < TableVal_Temp) 8000e36: 893a ldrh r2, [r7, #8] 8000e38: 88fb ldrh r3, [r7, #6] 8000e3a: 429a cmp r2, r3 8000e3c: d203 bcs.n 8000e46 Curr_DB = i; 8000e3e: 6a3b ldr r3, [r7, #32] 8000e40: f887 3025 strb.w r3, [r7, #37] ; 0x25 8000e44: e006 b.n 8000e54 else Curr_DB = i + 1; 8000e46: 6a3b ldr r3, [r7, #32] 8000e48: b2db uxtb r3, r3 8000e4a: 3301 adds r3, #1 8000e4c: f887 3025 strb.w r3, [r7, #37] ; 0x25 8000e50: e000 b.n 8000e54 continue; 8000e52: bf00 nop for(int i = 0; i <= 50; i++){ 8000e54: 6a3b ldr r3, [r7, #32] 8000e56: 3301 adds r3, #1 8000e58: 623b str r3, [r7, #32] 8000e5a: 6a3b ldr r3, [r7, #32] 8000e5c: 2b32 cmp r3, #50 ; 0x32 8000e5e: ddc1 ble.n 8000de4 } } // DB_Define[] // printf("Curr Db : %d \r\n",Curr_DB); return Curr_DB; 8000e60: f897 3025 ldrb.w r3, [r7, #37] ; 0x25 } 8000e64: 4618 mov r0, r3 8000e66: 372c adds r7, #44 ; 0x2c 8000e68: 46bd mov sp, r7 8000e6a: bd90 pop {r4, r7, pc} 8000e6c: f3af 8000 nop.w 8000e70: d2f1a9fc .word 0xd2f1a9fc 8000e74: 3f50624d .word 0x3f50624d 8000e78: 2000057c .word 0x2000057c 8000e7c: 408f4000 .word 0x408f4000 8000e80: 20000518 .word 0x20000518 08000e84 : void NessLab_Operate(uint8_t* data){ 8000e84: b580 push {r7, lr} 8000e86: b086 sub sp, #24 8000e88: af00 add r7, sp, #0 8000e8a: 6078 str r0, [r7, #4] uint8_t datatype = data[NessLab_MsgID0]; 8000e8c: 687b ldr r3, [r7, #4] 8000e8e: 789b ldrb r3, [r3, #2] 8000e90: 73fb strb r3, [r7, #15] uint8_t UartLength = 0; 8000e92: 2300 movs r3, #0 8000e94: 75fb strb r3, [r7, #23] static uint16_t MSG_SNCnt = 0; switch(datatype){ 8000e96: 7bfb ldrb r3, [r7, #15] 8000e98: 2bcb cmp r3, #203 ; 0xcb 8000e9a: d049 beq.n 8000f30 8000e9c: 2bcb cmp r3, #203 ; 0xcb 8000e9e: dc04 bgt.n 8000eaa 8000ea0: 2b65 cmp r3, #101 ; 0x65 8000ea2: d008 beq.n 8000eb6 8000ea4: 2bc9 cmp r3, #201 ; 0xc9 8000ea6: d030 beq.n 8000f0a 8000ea8: e08f b.n 8000fca 8000eaa: 2bcd cmp r3, #205 ; 0xcd 8000eac: d07f beq.n 8000fae 8000eae: 2bce cmp r3, #206 ; 0xce 8000eb0: f000 8084 beq.w 8000fbc 8000eb4: e089 b.n 8000fca case NessLab_STATUS_REQ: ADC_Check(); 8000eb6: f000 fba3 bl 8001600 UartLength = NessLab_MAX_INDEX + 1; 8000eba: 2316 movs r3, #22 8000ebc: 75fb strb r3, [r7, #23] MSG_SNCnt = data[NessLab_Req_MsgSN0] << 8 | data[NessLab_Req_MsgSN1]; 8000ebe: 687b ldr r3, [r7, #4] 8000ec0: 3303 adds r3, #3 8000ec2: 781b ldrb r3, [r3, #0] 8000ec4: 021b lsls r3, r3, #8 8000ec6: b21a sxth r2, r3 8000ec8: 687b ldr r3, [r7, #4] 8000eca: 3304 adds r3, #4 8000ecc: 781b ldrb r3, [r3, #0] 8000ece: b21b sxth r3, r3 8000ed0: 4313 orrs r3, r2 8000ed2: b21b sxth r3, r3 8000ed4: b29a uxth r2, r3 8000ed6: 4b41 ldr r3, [pc, #260] ; (8000fdc ) 8000ed8: 801a strh r2, [r3, #0] MSG_SNCnt++; 8000eda: 4b40 ldr r3, [pc, #256] ; (8000fdc ) 8000edc: 881b ldrh r3, [r3, #0] 8000ede: 3301 adds r3, #1 8000ee0: b29a uxth r2, r3 8000ee2: 4b3e ldr r3, [pc, #248] ; (8000fdc ) 8000ee4: 801a strh r2, [r3, #0] // if(data[NessLab_Req_Data_Cnt1] > 0) // NessLab_TxData[NessLab_VSWR_ALARM] = 1; // else // NessLab_TxData[NessLab_VSWR_ALARM] = 0; NessLab_TxData[NessLab_MsgSN0] = (uint8_t)((MSG_SNCnt & 0xFF00) >>8);//data[NessLab_Req_MsgSN0]; 8000ee6: 4b3d ldr r3, [pc, #244] ; (8000fdc ) 8000ee8: 881b ldrh r3, [r3, #0] 8000eea: 0a1b lsrs r3, r3, #8 8000eec: b29b uxth r3, r3 8000eee: b2da uxtb r2, r3 8000ef0: 4b3b ldr r3, [pc, #236] ; (8000fe0 ) 8000ef2: 70da strb r2, [r3, #3] NessLab_TxData[NessLab_MsgSN1] = (uint8_t)((MSG_SNCnt & 0x00FF));//data[NessLab_Req_MsgSN1] ; 8000ef4: 4b39 ldr r3, [pc, #228] ; (8000fdc ) 8000ef6: 881b ldrh r3, [r3, #0] 8000ef8: b2da uxtb r2, r3 8000efa: 4b39 ldr r3, [pc, #228] ; (8000fe0 ) 8000efc: 711a strb r2, [r3, #4] NessLab_Frame_Set(NessLab_TxData,12,NessLab_STATUS_RES); 8000efe: 2266 movs r2, #102 ; 0x66 8000f00: 210c movs r1, #12 8000f02: 4837 ldr r0, [pc, #220] ; (8000fe0 ) 8000f04: f000 f882 bl 800100c // NessLab_TxData[14] = 1; // NessLab_TxData[15] = 0; // NessLab_TxData[16] = 1; // NessLab_TxData[17] = 0; break; 8000f08: e05f b.n 8000fca case NessLab_Table_REQ: UartLength = NESSLAB_TABLE_LENGTH; 8000f0a: 236e movs r3, #110 ; 0x6e 8000f0c: 75fb strb r3, [r7, #23] FLASH_Read_Func(FLASH_USER_USE_START_ADDR,&NessLab_TxData[NessLab_Req_Data_Cnt0],data[NessLab_DataLength]); 8000f0e: 687b ldr r3, [r7, #4] 8000f10: 3306 adds r3, #6 8000f12: 781b ldrb r3, [r3, #0] 8000f14: 461a mov r2, r3 8000f16: 4933 ldr r1, [pc, #204] ; (8000fe4 ) 8000f18: 4833 ldr r0, [pc, #204] ; (8000fe8 ) 8000f1a: f000 fd57 bl 80019cc NessLab_Table_Frame_Set(NessLab_TxData,102,NessLab_Table_RES); 8000f1e: 22ca movs r2, #202 ; 0xca 8000f20: 2166 movs r1, #102 ; 0x66 8000f22: 482f ldr r0, [pc, #188] ; (8000fe0 ) 8000f24: f000 f97e bl 8001224 printf("NessLab_Table_REQ \r\n"); 8000f28: 4830 ldr r0, [pc, #192] ; (8000fec ) 8000f2a: f005 fc19 bl 8006760 break; 8000f2e: e04c b.n 8000fca case NessLab_TableSet_REQ: DataErase_Func(FLASH_USER_USE_START_ADDR,200); 8000f30: 21c8 movs r1, #200 ; 0xc8 8000f32: 482d ldr r0, [pc, #180] ; (8000fe8 ) 8000f34: f000 fc70 bl 8001818 printf("Ram Data Display \r\n"); 8000f38: 482d ldr r0, [pc, #180] ; (8000ff0 ) 8000f3a: f005 fc11 bl 8006760 for(int i = 0; i < data[NessLab_DataLength]; i++){ 8000f3e: 2300 movs r3, #0 8000f40: 613b str r3, [r7, #16] 8000f42: e015 b.n 8000f70 Flash_DataArray[i] = data[NessLab_Data_ADC1_H + i]; 8000f44: 693b ldr r3, [r7, #16] 8000f46: 3307 adds r3, #7 8000f48: 461a mov r2, r3 8000f4a: 687b ldr r3, [r7, #4] 8000f4c: 4413 add r3, r2 8000f4e: 7819 ldrb r1, [r3, #0] 8000f50: 4a28 ldr r2, [pc, #160] ; (8000ff4 ) 8000f52: 693b ldr r3, [r7, #16] 8000f54: 4413 add r3, r2 8000f56: 460a mov r2, r1 8000f58: 701a strb r2, [r3, #0] printf("%x ",Flash_DataArray[i]); 8000f5a: 4a26 ldr r2, [pc, #152] ; (8000ff4 ) 8000f5c: 693b ldr r3, [r7, #16] 8000f5e: 4413 add r3, r2 8000f60: 781b ldrb r3, [r3, #0] 8000f62: 4619 mov r1, r3 8000f64: 4824 ldr r0, [pc, #144] ; (8000ff8 ) 8000f66: f005 fb87 bl 8006678 for(int i = 0; i < data[NessLab_DataLength]; i++){ 8000f6a: 693b ldr r3, [r7, #16] 8000f6c: 3301 adds r3, #1 8000f6e: 613b str r3, [r7, #16] 8000f70: 687b ldr r3, [r7, #4] 8000f72: 3306 adds r3, #6 8000f74: 781b ldrb r3, [r3, #0] 8000f76: 461a mov r2, r3 8000f78: 693b ldr r3, [r7, #16] 8000f7a: 4293 cmp r3, r2 8000f7c: dbe2 blt.n 8000f44 } FLASH_Write_Func(FLASH_USER_USE_START_ADDR,&Flash_DataArray[0],data[NessLab_DataLength]); 8000f7e: 687b ldr r3, [r7, #4] 8000f80: 3306 adds r3, #6 8000f82: 781b ldrb r3, [r3, #0] 8000f84: 461a mov r2, r3 8000f86: 491b ldr r1, [pc, #108] ; (8000ff4 ) 8000f88: 4817 ldr r0, [pc, #92] ; (8000fe8 ) 8000f8a: f000 fc97 bl 80018bc UartLength = NESSLAB_TABLE_LENGTH; 8000f8e: 236e movs r3, #110 ; 0x6e 8000f90: 75fb strb r3, [r7, #23] NessLab_Table_Frame_Set(NessLab_TxData,104,NessLab_TableSet_RES); 8000f92: 22cc movs r2, #204 ; 0xcc 8000f94: 2168 movs r1, #104 ; 0x68 8000f96: 4812 ldr r0, [pc, #72] ; (8000fe0 ) 8000f98: f000 f944 bl 8001224 FLASH_Read_Func(FLASH_USER_USE_START_ADDR + 2,&DB_Define[0],104); 8000f9c: 2268 movs r2, #104 ; 0x68 8000f9e: 4917 ldr r1, [pc, #92] ; (8000ffc ) 8000fa0: 4817 ldr r0, [pc, #92] ; (8001000 ) 8000fa2: f000 fd13 bl 80019cc // NessLab_Init(); printf("\r\nNessLab_TableSet_REQ \r\n"); 8000fa6: 4817 ldr r0, [pc, #92] ; (8001004 ) 8000fa8: f005 fbda bl 8006760 break; 8000fac: e00d b.n 8000fca case NessLab_PAU_Enable_Req: HAL_GPIO_WritePin(AMP_EN_GPIO_Port,AMP_EN_Pin, GPIO_PIN_SET); 8000fae: 2201 movs r2, #1 8000fb0: f44f 7180 mov.w r1, #256 ; 0x100 8000fb4: 4814 ldr r0, [pc, #80] ; (8001008 ) 8000fb6: f002 faa0 bl 80034fa break; 8000fba: e006 b.n 8000fca case NessLab_PAU_Disable_Req: HAL_GPIO_WritePin(AMP_EN_GPIO_Port,AMP_EN_Pin, GPIO_PIN_RESET); 8000fbc: 2200 movs r2, #0 8000fbe: f44f 7180 mov.w r1, #256 ; 0x100 8000fc2: 4811 ldr r0, [pc, #68] ; (8001008 ) 8000fc4: f002 fa99 bl 80034fa break; 8000fc8: bf00 nop } Uart1_Data_Send(&NessLab_TxData[NessLab_Header0], UartLength); 8000fca: 7dfb ldrb r3, [r7, #23] 8000fcc: 4619 mov r1, r3 8000fce: 4804 ldr r0, [pc, #16] ; (8000fe0 ) 8000fd0: f000 fe82 bl 8001cd8 } 8000fd4: bf00 nop 8000fd6: 3718 adds r7, #24 8000fd8: 46bd mov sp, r7 8000fda: bd80 pop {r7, pc} 8000fdc: 2000038c .word 0x2000038c 8000fe0: 200001fc .word 0x200001fc 8000fe4: 20000203 .word 0x20000203 8000fe8: 0800ff38 .word 0x0800ff38 8000fec: 08008670 .word 0x08008670 8000ff0: 08008684 .word 0x08008684 8000ff4: 200002c4 .word 0x200002c4 8000ff8: 08008698 .word 0x08008698 8000ffc: 20000518 .word 0x20000518 8001000: 0800ff3a .word 0x0800ff3a 8001004: 0800869c .word 0x0800869c 8001008: 40010800 .word 0x40010800 0800100c : 7e 7e 66 00 02 00 0c 04 20 00 00 00 00 00 00 00 00 00 68 7e 7e 0a */ void NessLab_Frame_Set(uint8_t* data,uint8_t size){ 800100c: b590 push {r4, r7, lr} 800100e: b083 sub sp, #12 8001010: af00 add r7, sp, #0 8001012: 6078 str r0, [r7, #4] 8001014: 460b mov r3, r1 8001016: 70fb strb r3, [r7, #3] data[NessLab_Header0] = 0x7E; 8001018: 687b ldr r3, [r7, #4] 800101a: 227e movs r2, #126 ; 0x7e 800101c: 701a strb r2, [r3, #0] data[NessLab_Header1] = 0x7E; 800101e: 687b ldr r3, [r7, #4] 8001020: 3301 adds r3, #1 8001022: 227e movs r2, #126 ; 0x7e 8001024: 701a strb r2, [r3, #0] data[NessLab_MsgID0] = NessLab_STATUS_RES;// ID 8001026: 687b ldr r3, [r7, #4] 8001028: 3302 adds r3, #2 800102a: 2266 movs r2, #102 ; 0x66 800102c: 701a strb r2, [r3, #0] // data[NessLab_MsgSN0] = 0; // SEQ NUMBER // data[NessLab_MsgSN1] = 0; // SEQ NUMBER data[NessLab_Reserve0] = 0; // NessLab_Reserve0 800102e: 687b ldr r3, [r7, #4] 8001030: 3305 adds r3, #5 8001032: 2200 movs r2, #0 8001034: 701a strb r2, [r3, #0] data[NessLab_DataLength] = size; // Nesslab Size 8001036: 687b ldr r3, [r7, #4] 8001038: 3306 adds r3, #6 800103a: 78fa ldrb r2, [r7, #3] 800103c: 701a strb r2, [r3, #0] data[NessLab_Data_ADC1_H] = Currstatus.DownLink_Forward_Det_H;//(uint8_t)((ADC1value[0] & 0xFF00) >> 8); 800103e: 687b ldr r3, [r7, #4] 8001040: 3307 adds r3, #7 8001042: 4a49 ldr r2, [pc, #292] ; (8001168 ) 8001044: 79d2 ldrb r2, [r2, #7] 8001046: 701a strb r2, [r3, #0] data[NessLab_Data_ADC1_L] = Currstatus.DownLink_Forward_Det_L;//(uint8_t)(ADC1value[0] & 0x00FF); 8001048: 687b ldr r3, [r7, #4] 800104a: 3308 adds r3, #8 800104c: 4a46 ldr r2, [pc, #280] ; (8001168 ) 800104e: 7a12 ldrb r2, [r2, #8] 8001050: 701a strb r2, [r3, #0] data[NessLab_Data_ADC1_Table_Value] = NessLab_Adc_Convert_db(); 8001052: 687b ldr r3, [r7, #4] 8001054: f103 0409 add.w r4, r3, #9 8001058: f7ff fe72 bl 8000d40 800105c: 4603 mov r3, r0 800105e: 7023 strb r3, [r4, #0] if(DC_FAIL_ALARM_CNT > 3000) 8001060: 4b42 ldr r3, [pc, #264] ; (800116c ) 8001062: 681b ldr r3, [r3, #0] 8001064: f640 32b8 movw r2, #3000 ; 0xbb8 8001068: 4293 cmp r3, r2 800106a: d904 bls.n 8001076 data[NessLab_DC_FAIL_ALARM] = 1; 800106c: 687b ldr r3, [r7, #4] 800106e: 330a adds r3, #10 8001070: 2201 movs r2, #1 8001072: 701a strb r2, [r3, #0] 8001074: e003 b.n 800107e else data[NessLab_DC_FAIL_ALARM] = 0; 8001076: 687b ldr r3, [r7, #4] 8001078: 330a adds r3, #10 800107a: 2200 movs r2, #0 800107c: 701a strb r2, [r3, #0] if(OVER_INPUT_ALARM_CNT > 3000) 800107e: 4b3c ldr r3, [pc, #240] ; (8001170 ) 8001080: 681b ldr r3, [r3, #0] 8001082: f640 32b8 movw r2, #3000 ; 0xbb8 8001086: 4293 cmp r3, r2 8001088: d904 bls.n 8001094 data[NessLab_Over_Input_Alarm] = 1; 800108a: 687b ldr r3, [r7, #4] 800108c: 330e adds r3, #14 800108e: 2201 movs r2, #1 8001090: 701a strb r2, [r3, #0] 8001092: e003 b.n 800109c else data[NessLab_Over_Input_Alarm] = 0; 8001094: 687b ldr r3, [r7, #4] 8001096: 330e adds r3, #14 8001098: 2200 movs r2, #0 800109a: 701a strb r2, [r3, #0] if(OVER_TEMP_ALARM_CNT > 3000) 800109c: 4b35 ldr r3, [pc, #212] ; (8001174 ) 800109e: 681b ldr r3, [r3, #0] 80010a0: f640 32b8 movw r2, #3000 ; 0xbb8 80010a4: 4293 cmp r3, r2 80010a6: d904 bls.n 80010b2 data[NessLab_Over_Temp_Alarm] = 1; 80010a8: 687b ldr r3, [r7, #4] 80010aa: 330f adds r3, #15 80010ac: 2201 movs r2, #1 80010ae: 701a strb r2, [r3, #0] 80010b0: e003 b.n 80010ba else data[NessLab_Over_Temp_Alarm] = 0; 80010b2: 687b ldr r3, [r7, #4] 80010b4: 330f adds r3, #15 80010b6: 2200 movs r2, #0 80010b8: 701a strb r2, [r3, #0] if(ALC_ALARM_CNT > 3000) 80010ba: 4b2f ldr r3, [pc, #188] ; (8001178 ) 80010bc: 681b ldr r3, [r3, #0] 80010be: f640 32b8 movw r2, #3000 ; 0xbb8 80010c2: 4293 cmp r3, r2 80010c4: d904 bls.n 80010d0 data[NessLab_ALC_ALARM] = 1; 80010c6: 687b ldr r3, [r7, #4] 80010c8: 3311 adds r3, #17 80010ca: 2201 movs r2, #1 80010cc: 701a strb r2, [r3, #0] 80010ce: e003 b.n 80010d8 else data[NessLab_ALC_ALARM] = 0; 80010d0: 687b ldr r3, [r7, #4] 80010d2: 3311 adds r3, #17 80010d4: 2200 movs r2, #0 80010d6: 701a strb r2, [r3, #0] if(OVER_POWER_ALARM_CNT > 3000) 80010d8: 4b28 ldr r3, [pc, #160] ; (800117c ) 80010da: 681b ldr r3, [r3, #0] 80010dc: f640 32b8 movw r2, #3000 ; 0xbb8 80010e0: 4293 cmp r3, r2 80010e2: d904 bls.n 80010ee data[NessLab_Over_Power_Alarm] = 1; 80010e4: 687b ldr r3, [r7, #4] 80010e6: 330c adds r3, #12 80010e8: 2201 movs r2, #1 80010ea: 701a strb r2, [r3, #0] 80010ec: e003 b.n 80010f6 else data[NessLab_Over_Power_Alarm] = 0; 80010ee: 687b ldr r3, [r7, #4] 80010f0: 330c adds r3, #12 80010f2: 2200 movs r2, #0 80010f4: 701a strb r2, [r3, #0] if(VSWR_ALARM_CNT > 3000) 80010f6: 4b22 ldr r3, [pc, #136] ; (8001180 ) 80010f8: 681b ldr r3, [r3, #0] 80010fa: f640 32b8 movw r2, #3000 ; 0xbb8 80010fe: 4293 cmp r3, r2 8001100: d904 bls.n 800110c data[NessLab_VSWR_ALARM] = 1; 8001102: 687b ldr r3, [r7, #4] 8001104: 330d adds r3, #13 8001106: 2201 movs r2, #1 8001108: 701a strb r2, [r3, #0] 800110a: e003 b.n 8001114 else data[NessLab_VSWR_ALARM] = 0; 800110c: 687b ldr r3, [r7, #4] 800110e: 330d adds r3, #13 8001110: 2200 movs r2, #0 8001112: 701a strb r2, [r3, #0] data[NessLab_DownLink_Status] = 0; 8001114: 687b ldr r3, [r7, #4] 8001116: 330b adds r3, #11 8001118: 2200 movs r2, #0 800111a: 701a strb r2, [r3, #0] data[NessLab_Temp_Monitor] = Currstatus.Temp_Monitor; 800111c: 687b ldr r3, [r7, #4] 800111e: 3310 adds r3, #16 8001120: 4a11 ldr r2, [pc, #68] ; (8001168 ) 8001122: 7c52 ldrb r2, [r2, #17] 8001124: 701a strb r2, [r3, #0] data[NessLab_ChecksumVal] = NessLab_Checksum(&data[NessLab_MsgID0], NessLab_MAX_INDEX - 5); 8001126: 687b ldr r3, [r7, #4] 8001128: 1c9a adds r2, r3, #2 800112a: 687b ldr r3, [r7, #4] 800112c: f103 0412 add.w r4, r3, #18 8001130: 2110 movs r1, #16 8001132: 4610 mov r0, r2 8001134: f000 fb1a bl 800176c 8001138: 4603 mov r3, r0 800113a: 7023 strb r3, [r4, #0] /* Exception Header Tail Checksum */ data[NessLab_Tail0] = 0x7E; 800113c: 687b ldr r3, [r7, #4] 800113e: 3313 adds r3, #19 8001140: 227e movs r2, #126 ; 0x7e 8001142: 701a strb r2, [r3, #0] data[NessLab_Tail1] = 0x7E; 8001144: 687b ldr r3, [r7, #4] 8001146: 3314 adds r3, #20 8001148: 227e movs r2, #126 ; 0x7e 800114a: 701a strb r2, [r3, #0] data[NessLab_Tail1 + 1] = 0x0A; 800114c: 687b ldr r3, [r7, #4] 800114e: 3315 adds r3, #21 8001150: 220a movs r2, #10 8001152: 701a strb r2, [r3, #0] NessLab_Protocol_LastCheck(&data[NessLab_MsgID0],16); 8001154: 687b ldr r3, [r7, #4] 8001156: 3302 adds r3, #2 8001158: 2110 movs r1, #16 800115a: 4618 mov r0, r3 800115c: f000 f812 bl 8001184 } 8001160: bf00 nop 8001162: 370c adds r7, #12 8001164: 46bd mov sp, r7 8001166: bd90 pop {r4, r7, pc} 8001168: 2000057c .word 0x2000057c 800116c: 200004f0 .word 0x200004f0 8001170: 200004f4 .word 0x200004f4 8001174: 200004f8 .word 0x200004f8 8001178: 200004fc .word 0x200004fc 800117c: 20000500 .word 0x20000500 8001180: 20000504 .word 0x20000504 08001184 : void NessLab_Protocol_LastCheck(uint8_t* data,uint8_t size){ 8001184: b480 push {r7} 8001186: b085 sub sp, #20 8001188: af00 add r7, sp, #0 800118a: 6078 str r0, [r7, #4] 800118c: 460b mov r3, r1 800118e: 70fb strb r3, [r7, #3] int cnt = NessLab_MsgID0; 8001190: 2302 movs r3, #2 8001192: 60fb str r3, [r7, #12] for(int i = cnt; i < 17; i++){ 8001194: 68fb ldr r3, [r7, #12] 8001196: 60bb str r3, [r7, #8] 8001198: e03b b.n 8001212 if(data[i] == 0x7e){ 800119a: 68bb ldr r3, [r7, #8] 800119c: 687a ldr r2, [r7, #4] 800119e: 4413 add r3, r2 80011a0: 781b ldrb r3, [r3, #0] 80011a2: 2b7e cmp r3, #126 ; 0x7e 80011a4: d110 bne.n 80011c8 data[cnt++] = 0x7d; 80011a6: 68fb ldr r3, [r7, #12] 80011a8: 1c5a adds r2, r3, #1 80011aa: 60fa str r2, [r7, #12] 80011ac: 461a mov r2, r3 80011ae: 687b ldr r3, [r7, #4] 80011b0: 4413 add r3, r2 80011b2: 227d movs r2, #125 ; 0x7d 80011b4: 701a strb r2, [r3, #0] data[cnt++] = 0x5e; 80011b6: 68fb ldr r3, [r7, #12] 80011b8: 1c5a adds r2, r3, #1 80011ba: 60fa str r2, [r7, #12] 80011bc: 461a mov r2, r3 80011be: 687b ldr r3, [r7, #4] 80011c0: 4413 add r3, r2 80011c2: 225e movs r2, #94 ; 0x5e 80011c4: 701a strb r2, [r3, #0] 80011c6: e021 b.n 800120c } else if(data[i] == 0x7d){ 80011c8: 68bb ldr r3, [r7, #8] 80011ca: 687a ldr r2, [r7, #4] 80011cc: 4413 add r3, r2 80011ce: 781b ldrb r3, [r3, #0] 80011d0: 2b7d cmp r3, #125 ; 0x7d 80011d2: d110 bne.n 80011f6 data[cnt++] = 0x7d; 80011d4: 68fb ldr r3, [r7, #12] 80011d6: 1c5a adds r2, r3, #1 80011d8: 60fa str r2, [r7, #12] 80011da: 461a mov r2, r3 80011dc: 687b ldr r3, [r7, #4] 80011de: 4413 add r3, r2 80011e0: 227d movs r2, #125 ; 0x7d 80011e2: 701a strb r2, [r3, #0] data[cnt++] = 0x5d; 80011e4: 68fb ldr r3, [r7, #12] 80011e6: 1c5a adds r2, r3, #1 80011e8: 60fa str r2, [r7, #12] 80011ea: 461a mov r2, r3 80011ec: 687b ldr r3, [r7, #4] 80011ee: 4413 add r3, r2 80011f0: 225d movs r2, #93 ; 0x5d 80011f2: 701a strb r2, [r3, #0] 80011f4: e00a b.n 800120c }else{ data[i++] = data[i]; 80011f6: 68bb ldr r3, [r7, #8] 80011f8: 687a ldr r2, [r7, #4] 80011fa: 441a add r2, r3 80011fc: 68bb ldr r3, [r7, #8] 80011fe: 1c59 adds r1, r3, #1 8001200: 60b9 str r1, [r7, #8] 8001202: 4619 mov r1, r3 8001204: 687b ldr r3, [r7, #4] 8001206: 440b add r3, r1 8001208: 7812 ldrb r2, [r2, #0] 800120a: 701a strb r2, [r3, #0] for(int i = cnt; i < 17; i++){ 800120c: 68bb ldr r3, [r7, #8] 800120e: 3301 adds r3, #1 8001210: 60bb str r3, [r7, #8] 8001212: 68bb ldr r3, [r7, #8] 8001214: 2b10 cmp r3, #16 8001216: ddc0 ble.n 800119a } } } 8001218: bf00 nop 800121a: 3714 adds r7, #20 800121c: 46bd mov sp, r7 800121e: bc80 pop {r7} 8001220: 4770 bx lr ... 08001224 : void NessLab_Table_Frame_Set(uint8_t* data,uint8_t size,uint8_t mode){ 8001224: b590 push {r4, r7, lr} 8001226: b087 sub sp, #28 8001228: af00 add r7, sp, #0 800122a: 6078 str r0, [r7, #4] 800122c: 460b mov r3, r1 800122e: 70fb strb r3, [r7, #3] 8001230: 4613 mov r3, r2 8001232: 70bb strb r3, [r7, #2] uint32_t i = 0; 8001234: 2300 movs r3, #0 8001236: 617b str r3, [r7, #20] uint32_t CurrApiAddress = 0; 8001238: 2300 movs r3, #0 800123a: 60fb str r3, [r7, #12] CurrApiAddress = FLASH_USER_USE_START_ADDR; 800123c: 4b33 ldr r3, [pc, #204] ; (800130c ) 800123e: 60fb str r3, [r7, #12] uint8_t* Currdata = (uint8_t*)CurrApiAddress; 8001240: 68fb ldr r3, [r7, #12] 8001242: 60bb str r3, [r7, #8] uint8_t* pdata; data[i++] = 0x7E; 8001244: 697b ldr r3, [r7, #20] 8001246: 1c5a adds r2, r3, #1 8001248: 617a str r2, [r7, #20] 800124a: 687a ldr r2, [r7, #4] 800124c: 4413 add r3, r2 800124e: 227e movs r2, #126 ; 0x7e 8001250: 701a strb r2, [r3, #0] data[i++] = 0x7E; 8001252: 697b ldr r3, [r7, #20] 8001254: 1c5a adds r2, r3, #1 8001256: 617a str r2, [r7, #20] 8001258: 687a ldr r2, [r7, #4] 800125a: 4413 add r3, r2 800125c: 227e movs r2, #126 ; 0x7e 800125e: 701a strb r2, [r3, #0] data[i++] = mode;// ID 8001260: 697b ldr r3, [r7, #20] 8001262: 1c5a adds r2, r3, #1 8001264: 617a str r2, [r7, #20] 8001266: 687a ldr r2, [r7, #4] 8001268: 4413 add r3, r2 800126a: 78ba ldrb r2, [r7, #2] 800126c: 701a strb r2, [r3, #0] data[i++] = 0; // SEQ NUMBER 800126e: 697b ldr r3, [r7, #20] 8001270: 1c5a adds r2, r3, #1 8001272: 617a str r2, [r7, #20] 8001274: 687a ldr r2, [r7, #4] 8001276: 4413 add r3, r2 8001278: 2200 movs r2, #0 800127a: 701a strb r2, [r3, #0] data[i++] = 0; // SEQ NUMBER 800127c: 697b ldr r3, [r7, #20] 800127e: 1c5a adds r2, r3, #1 8001280: 617a str r2, [r7, #20] 8001282: 687a ldr r2, [r7, #4] 8001284: 4413 add r3, r2 8001286: 2200 movs r2, #0 8001288: 701a strb r2, [r3, #0] data[i++] = 0; // NessLab_Reserve0 800128a: 697b ldr r3, [r7, #20] 800128c: 1c5a adds r2, r3, #1 800128e: 617a str r2, [r7, #20] 8001290: 687a ldr r2, [r7, #4] 8001292: 4413 add r3, r2 8001294: 2200 movs r2, #0 8001296: 701a strb r2, [r3, #0] data[i++] = size; // Nesslab Size 8001298: 697b ldr r3, [r7, #20] 800129a: 1c5a adds r2, r3, #1 800129c: 617a str r2, [r7, #20] 800129e: 687a ldr r2, [r7, #4] 80012a0: 4413 add r3, r2 80012a2: 78fa ldrb r2, [r7, #3] 80012a4: 701a strb r2, [r3, #0] // NessLab_TalbleFlash_Read(&data[NessLab_DataLength + 1],100); for(int a = 0; a < size; a++){ 80012a6: 2300 movs r3, #0 80012a8: 613b str r3, [r7, #16] 80012aa: e00c b.n 80012c6 data[i++] = Currdata[a]; 80012ac: 693b ldr r3, [r7, #16] 80012ae: 68ba ldr r2, [r7, #8] 80012b0: 441a add r2, r3 80012b2: 697b ldr r3, [r7, #20] 80012b4: 1c59 adds r1, r3, #1 80012b6: 6179 str r1, [r7, #20] 80012b8: 6879 ldr r1, [r7, #4] 80012ba: 440b add r3, r1 80012bc: 7812 ldrb r2, [r2, #0] 80012be: 701a strb r2, [r3, #0] for(int a = 0; a < size; a++){ 80012c0: 693b ldr r3, [r7, #16] 80012c2: 3301 adds r3, #1 80012c4: 613b str r3, [r7, #16] 80012c6: 78fb ldrb r3, [r7, #3] 80012c8: 693a ldr r2, [r7, #16] 80012ca: 429a cmp r2, r3 80012cc: dbee blt.n 80012ac // printf("%02x ",Currdata[i]); } data[i++] = NessLab_Checksum(&data[NessLab_MsgID0], 100 + 5); 80012ce: 687b ldr r3, [r7, #4] 80012d0: 1c98 adds r0, r3, #2 80012d2: 697b ldr r3, [r7, #20] 80012d4: 1c5a adds r2, r3, #1 80012d6: 617a str r2, [r7, #20] 80012d8: 687a ldr r2, [r7, #4] 80012da: 18d4 adds r4, r2, r3 80012dc: 2169 movs r1, #105 ; 0x69 80012de: f000 fa45 bl 800176c 80012e2: 4603 mov r3, r0 80012e4: 7023 strb r3, [r4, #0] /* Exception Header Tail Checksum */ data[i++] = 0x7E; 80012e6: 697b ldr r3, [r7, #20] 80012e8: 1c5a adds r2, r3, #1 80012ea: 617a str r2, [r7, #20] 80012ec: 687a ldr r2, [r7, #4] 80012ee: 4413 add r3, r2 80012f0: 227e movs r2, #126 ; 0x7e 80012f2: 701a strb r2, [r3, #0] data[i++] = 0x7E; 80012f4: 697b ldr r3, [r7, #20] 80012f6: 1c5a adds r2, r3, #1 80012f8: 617a str r2, [r7, #20] 80012fa: 687a ldr r2, [r7, #4] 80012fc: 4413 add r3, r2 80012fe: 227e movs r2, #126 ; 0x7e 8001300: 701a strb r2, [r3, #0] } 8001302: bf00 nop 8001304: 371c adds r7, #28 8001306: 46bd mov sp, r7 8001308: bd90 pop {r4, r7, pc} 800130a: bf00 nop 800130c: 0800ff38 .word 0x0800ff38 08001310 : void NessLab_Status_Check(){ //HAL_GPIO_ReadPin(, GPIO_Pin) } void NessLab_PAU_Enable(){ 8001310: b598 push {r3, r4, r7, lr} 8001312: af00 add r7, sp, #0 #if 1 if( HAL_GPIO_ReadPin(PAU_EN_GPIO_Port, PAU_EN_Pin) != HAL_GPIO_ReadPin(AMP_EN_GPIO_Port, AMP_EN_Pin) ){ 8001314: f44f 4100 mov.w r1, #32768 ; 0x8000 8001318: 4817 ldr r0, [pc, #92] ; (8001378 ) 800131a: f002 f8d7 bl 80034cc 800131e: 4603 mov r3, r0 8001320: 461c mov r4, r3 8001322: f44f 7180 mov.w r1, #256 ; 0x100 8001326: 4815 ldr r0, [pc, #84] ; (800137c ) 8001328: f002 f8d0 bl 80034cc 800132c: 4603 mov r3, r0 800132e: 429c cmp r4, r3 8001330: d01f beq.n 8001372 HAL_GPIO_WritePin(AMP_EN_GPIO_Port,AMP_EN_Pin, HAL_GPIO_ReadPin(PAU_EN_GPIO_Port, PAU_EN_Pin)); 8001332: f44f 4100 mov.w r1, #32768 ; 0x8000 8001336: 4810 ldr r0, [pc, #64] ; (8001378 ) 8001338: f002 f8c8 bl 80034cc 800133c: 4603 mov r3, r0 800133e: 461a mov r2, r3 8001340: f44f 7180 mov.w r1, #256 ; 0x100 8001344: 480d ldr r0, [pc, #52] ; (800137c ) 8001346: f002 f8d8 bl 80034fa printf("HAL_GPIO_ReadPin(PAU_EN_GPIO_Port, PAU_EN_Pin) : %d \r\n",HAL_GPIO_ReadPin(PAU_EN_GPIO_Port, PAU_EN_Pin)); 800134a: f44f 4100 mov.w r1, #32768 ; 0x8000 800134e: 480a ldr r0, [pc, #40] ; (8001378 ) 8001350: f002 f8bc bl 80034cc 8001354: 4603 mov r3, r0 8001356: 4619 mov r1, r3 8001358: 4809 ldr r0, [pc, #36] ; (8001380 ) 800135a: f005 f98d bl 8006678 printf("AMP_EN_GPIO_Port : %d \r\n",HAL_GPIO_ReadPin(AMP_EN_GPIO_Port, AMP_EN_Pin)); 800135e: f44f 7180 mov.w r1, #256 ; 0x100 8001362: 4806 ldr r0, [pc, #24] ; (800137c ) 8001364: f002 f8b2 bl 80034cc 8001368: 4603 mov r3, r0 800136a: 4619 mov r1, r3 800136c: 4805 ldr r0, [pc, #20] ; (8001384 ) 800136e: f005 f983 bl 8006678 #else HAL_GPIO_WritePin(AMP_EN_GPIO_Port,AMP_EN_Pin, 0); printf("AMP_EN_GPIO_Port : %d \r\n",HAL_GPIO_ReadPin(AMP_EN_GPIO_Port, AMP_EN_Pin)); #endif } 8001372: bf00 nop 8001374: bd98 pop {r3, r4, r7, pc} 8001376: bf00 nop 8001378: 40010c00 .word 0x40010c00 800137c: 40010800 .word 0x40010800 8001380: 080086b8 .word 0x080086b8 8001384: 080086f0 .word 0x080086f0 08001388 : void NessLab_GPIO_Operate(){ 8001388: b580 push {r7, lr} 800138a: af00 add r7, sp, #0 NessLab_PAU_Enable(); 800138c: f7ff ffc0 bl 8001310 } 8001390: bf00 nop 8001392: bd80 pop {r7, pc} 8001394: 0000 movs r0, r0 ... 08001398 : * ADC 0 :DL TX * ADC 1 :DL RX * ADC 2 :TEMP * */ void ADC_Value_Get(){ 8001398: b590 push {r4, r7, lr} 800139a: b083 sub sp, #12 800139c: af00 add r7, sp, #0 uint16_t CalcRet = 0 ; 800139e: 2300 movs r3, #0 80013a0: 80fb strh r3, [r7, #6] uint16_t Tx_Det_Volt = ((ADC1value[0] * (3.3 / 4095))* 1000); 80013a2: 4b31 ldr r3, [pc, #196] ; (8001468 ) 80013a4: 881b ldrh r3, [r3, #0] 80013a6: b29b uxth r3, r3 80013a8: 4618 mov r0, r3 80013aa: f7ff f88b bl 80004c4 <__aeabi_i2d> 80013ae: a32c add r3, pc, #176 ; (adr r3, 8001460 ) 80013b0: e9d3 2300 ldrd r2, r3, [r3] 80013b4: f7ff f8f0 bl 8000598 <__aeabi_dmul> 80013b8: 4603 mov r3, r0 80013ba: 460c mov r4, r1 80013bc: 4618 mov r0, r3 80013be: 4621 mov r1, r4 80013c0: f04f 0200 mov.w r2, #0 80013c4: 4b29 ldr r3, [pc, #164] ; (800146c ) 80013c6: f7ff f8e7 bl 8000598 <__aeabi_dmul> 80013ca: 4603 mov r3, r0 80013cc: 460c mov r4, r1 80013ce: 4618 mov r0, r3 80013d0: 4621 mov r1, r4 80013d2: f7ff fbb9 bl 8000b48 <__aeabi_d2uiz> 80013d6: 4603 mov r3, r0 80013d8: 80bb strh r3, [r7, #4] uint16_t Rx_Det_Volt = ((ADC1value[1] * (3.3 / 4095))* 1000); 80013da: 4b23 ldr r3, [pc, #140] ; (8001468 ) 80013dc: 885b ldrh r3, [r3, #2] 80013de: b29b uxth r3, r3 80013e0: 4618 mov r0, r3 80013e2: f7ff f86f bl 80004c4 <__aeabi_i2d> 80013e6: a31e add r3, pc, #120 ; (adr r3, 8001460 ) 80013e8: e9d3 2300 ldrd r2, r3, [r3] 80013ec: f7ff f8d4 bl 8000598 <__aeabi_dmul> 80013f0: 4603 mov r3, r0 80013f2: 460c mov r4, r1 80013f4: 4618 mov r0, r3 80013f6: 4621 mov r1, r4 80013f8: f04f 0200 mov.w r2, #0 80013fc: 4b1b ldr r3, [pc, #108] ; (800146c ) 80013fe: f7ff f8cb bl 8000598 <__aeabi_dmul> 8001402: 4603 mov r3, r0 8001404: 460c mov r4, r1 8001406: 4618 mov r0, r3 8001408: 4621 mov r1, r4 800140a: f7ff fb9d bl 8000b48 <__aeabi_d2uiz> 800140e: 4603 mov r3, r0 8001410: 807b strh r3, [r7, #2] int8_t Real_Temperature = ADC_Convert_Temperature((ADC1value[2] * (3.3 / 4095))); 8001412: 4b15 ldr r3, [pc, #84] ; (8001468 ) 8001414: 889b ldrh r3, [r3, #4] 8001416: b29b uxth r3, r3 8001418: 4618 mov r0, r3 800141a: f7ff f853 bl 80004c4 <__aeabi_i2d> 800141e: a310 add r3, pc, #64 ; (adr r3, 8001460 ) 8001420: e9d3 2300 ldrd r2, r3, [r3] 8001424: f7ff f8b8 bl 8000598 <__aeabi_dmul> 8001428: 4603 mov r3, r0 800142a: 460c mov r4, r1 800142c: 4618 mov r0, r3 800142e: 4621 mov r1, r4 8001430: f000 f834 bl 800149c 8001434: 4603 mov r3, r0 8001436: 707b strb r3, [r7, #1] // Currstatus.DownLink_Forward_Det_H = ((Tx_Det_Volt & 0xFF00) >> 8); // Currstatus.DownLink_Forward_Det_L = (Tx_Det_Volt & 0x00FF); // printf("Tx_Det_Volt : %d \r\n",Tx_Det_Volt); /*DL RX Calc*/ Currstatus.DownLink_Reverse_Det_H = ((Rx_Det_Volt & 0xFF00) >> 8); 8001438: 887b ldrh r3, [r7, #2] 800143a: 0a1b lsrs r3, r3, #8 800143c: b29b uxth r3, r3 800143e: b2da uxtb r2, r3 8001440: 4b0b ldr r3, [pc, #44] ; (8001470 ) 8001442: 725a strb r2, [r3, #9] Currstatus.DownLink_Reverse_Det_L = (Rx_Det_Volt & 0x00FF); 8001444: 887b ldrh r3, [r7, #2] 8001446: b2da uxtb r2, r3 8001448: 4b09 ldr r3, [pc, #36] ; (8001470 ) 800144a: 729a strb r2, [r3, #10] /*Temp Calc*/ Currstatus.Temp_Monitor = Real_Temperature; 800144c: 787a ldrb r2, [r7, #1] 800144e: 4b08 ldr r3, [pc, #32] ; (8001470 ) 8001450: 745a strb r2, [r3, #17] } 8001452: bf00 nop 8001454: 370c adds r7, #12 8001456: 46bd mov sp, r7 8001458: bd90 pop {r4, r7, pc} 800145a: bf00 nop 800145c: f3af 8000 nop.w 8001460: e734d9b4 .word 0xe734d9b4 8001464: 3f4a680c .word 0x3f4a680c 8001468: 20000594 .word 0x20000594 800146c: 408f4000 .word 0x408f4000 8001470: 2000057c .word 0x2000057c 08001474 : void ADC_Initialize(){ 8001474: b580 push {r7, lr} 8001476: af00 add r7, sp, #0 while(!(HAL_ADCEx_Calibration_Start(&hadc1)==HAL_OK)); 8001478: bf00 nop 800147a: 4806 ldr r0, [pc, #24] ; (8001494 ) 800147c: f001 f8e2 bl 8002644 8001480: 4603 mov r3, r0 8001482: 2b00 cmp r3, #0 8001484: d1f9 bne.n 800147a HAL_ADC_Start_DMA(&hadc1, (uint16_t*)ADC1value,(uint32_t) 3); 8001486: 2203 movs r2, #3 8001488: 4903 ldr r1, [pc, #12] ; (8001498 ) 800148a: 4802 ldr r0, [pc, #8] ; (8001494 ) 800148c: f000 fd78 bl 8001f80 } 8001490: bf00 nop 8001492: bd80 pop {r7, pc} 8001494: 200008a8 .word 0x200008a8 8001498: 20000594 .word 0x20000594 0800149c : uint8_t ADC_Convert_Temperature(double val){ 800149c: b590 push {r4, r7, lr} 800149e: b087 sub sp, #28 80014a0: af00 add r7, sp, #0 80014a2: e9c7 0100 strd r0, r1, [r7] int16_t ref_0temp = 500; 80014a6: f44f 73fa mov.w r3, #500 ; 0x1f4 80014aa: 817b strh r3, [r7, #10] int16_t ret = val * 1000; 80014ac: f04f 0200 mov.w r2, #0 80014b0: 4b21 ldr r3, [pc, #132] ; (8001538 ) 80014b2: e9d7 0100 ldrd r0, r1, [r7] 80014b6: f7ff f86f bl 8000598 <__aeabi_dmul> 80014ba: 4603 mov r3, r0 80014bc: 460c mov r4, r1 80014be: 4618 mov r0, r3 80014c0: 4621 mov r1, r4 80014c2: f7ff fb19 bl 8000af8 <__aeabi_d2iz> 80014c6: 4603 mov r3, r0 80014c8: 813b strh r3, [r7, #8] int8_t cnt = 0; 80014ca: 2300 movs r3, #0 80014cc: 75fb strb r3, [r7, #23] // printf("ret : %d \r\n", ret); if( ret - ref_0temp > 0){ 80014ce: f9b7 2008 ldrsh.w r2, [r7, #8] 80014d2: f9b7 300a ldrsh.w r3, [r7, #10] 80014d6: 1ad3 subs r3, r2, r3 80014d8: 2b00 cmp r3, #0 80014da: dd14 ble.n 8001506 for(int i = 0; i < ret - ref_0temp; i += 10){ 80014dc: 2300 movs r3, #0 80014de: 613b str r3, [r7, #16] 80014e0: e008 b.n 80014f4 cnt++; 80014e2: f997 3017 ldrsb.w r3, [r7, #23] 80014e6: b2db uxtb r3, r3 80014e8: 3301 adds r3, #1 80014ea: b2db uxtb r3, r3 80014ec: 75fb strb r3, [r7, #23] for(int i = 0; i < ret - ref_0temp; i += 10){ 80014ee: 693b ldr r3, [r7, #16] 80014f0: 330a adds r3, #10 80014f2: 613b str r3, [r7, #16] 80014f4: f9b7 2008 ldrsh.w r2, [r7, #8] 80014f8: f9b7 300a ldrsh.w r3, [r7, #10] 80014fc: 1ad3 subs r3, r2, r3 80014fe: 693a ldr r2, [r7, #16] 8001500: 429a cmp r2, r3 8001502: dbee blt.n 80014e2 8001504: e013 b.n 800152e } }else{ for(int i = 0; i > ret - ref_0temp; i -= 10){ 8001506: 2300 movs r3, #0 8001508: 60fb str r3, [r7, #12] 800150a: e008 b.n 800151e cnt--; 800150c: f997 3017 ldrsb.w r3, [r7, #23] 8001510: b2db uxtb r3, r3 8001512: 3b01 subs r3, #1 8001514: b2db uxtb r3, r3 8001516: 75fb strb r3, [r7, #23] for(int i = 0; i > ret - ref_0temp; i -= 10){ 8001518: 68fb ldr r3, [r7, #12] 800151a: 3b0a subs r3, #10 800151c: 60fb str r3, [r7, #12] 800151e: f9b7 2008 ldrsh.w r2, [r7, #8] 8001522: f9b7 300a ldrsh.w r3, [r7, #10] 8001526: 1ad3 subs r3, r2, r3 8001528: 68fa ldr r2, [r7, #12] 800152a: 429a cmp r2, r3 800152c: dcee bgt.n 800150c } } // printf("Temp : %d\r\n",cnt); return cnt; 800152e: 7dfb ldrb r3, [r7, #23] } 8001530: 4618 mov r0, r3 8001532: 371c adds r7, #28 8001534: 46bd mov sp, r7 8001536: bd90 pop {r4, r7, pc} 8001538: 408f4000 .word 0x408f4000 0800153c : uint32_t SumFunc(uint32_t* data,uint16_t size){ 800153c: b480 push {r7} 800153e: b085 sub sp, #20 8001540: af00 add r7, sp, #0 8001542: 6078 str r0, [r7, #4] 8001544: 460b mov r3, r1 8001546: 807b strh r3, [r7, #2] uint32_t ret = 0; 8001548: 2300 movs r3, #0 800154a: 60fb str r3, [r7, #12] for (uint16_t i = 0; i < size; i++) // 배열의 요소 개수만큼 반복 800154c: 2300 movs r3, #0 800154e: 817b strh r3, [r7, #10] 8001550: e00a b.n 8001568 { ret += data[i]; // sum과 배열의 요소를 더해서 다시 sum에 저장 8001552: 897b ldrh r3, [r7, #10] 8001554: 009b lsls r3, r3, #2 8001556: 687a ldr r2, [r7, #4] 8001558: 4413 add r3, r2 800155a: 681b ldr r3, [r3, #0] 800155c: 68fa ldr r2, [r7, #12] 800155e: 4413 add r3, r2 8001560: 60fb str r3, [r7, #12] for (uint16_t i = 0; i < size; i++) // 배열의 요소 개수만큼 반복 8001562: 897b ldrh r3, [r7, #10] 8001564: 3301 adds r3, #1 8001566: 817b strh r3, [r7, #10] 8001568: 897a ldrh r2, [r7, #10] 800156a: 887b ldrh r3, [r7, #2] 800156c: 429a cmp r2, r3 800156e: d3f0 bcc.n 8001552 // printf("ret : %d data[%d] \r\n",ret,i,data[i]); } return ret; 8001570: 68fb ldr r3, [r7, #12] } 8001572: 4618 mov r0, r3 8001574: 3714 adds r7, #20 8001576: 46bd mov sp, r7 8001578: bc80 pop {r7} 800157a: 4770 bx lr 0800157c : void DascendigFunc(int32_t* src,uint32_t size ){ 800157c: b480 push {r7} 800157e: b087 sub sp, #28 8001580: af00 add r7, sp, #0 8001582: 6078 str r0, [r7, #4] 8001584: 6039 str r1, [r7, #0] int32_t temp; for(int i = 0 ; i < size - 1 ; i ++) { 8001586: 2300 movs r3, #0 8001588: 617b str r3, [r7, #20] 800158a: e02f b.n 80015ec for(int j = i+1 ; j < size ; j ++) { 800158c: 697b ldr r3, [r7, #20] 800158e: 3301 adds r3, #1 8001590: 613b str r3, [r7, #16] 8001592: e024 b.n 80015de if(src[i] < src[j]) { 8001594: 697b ldr r3, [r7, #20] 8001596: 009b lsls r3, r3, #2 8001598: 687a ldr r2, [r7, #4] 800159a: 4413 add r3, r2 800159c: 681a ldr r2, [r3, #0] 800159e: 693b ldr r3, [r7, #16] 80015a0: 009b lsls r3, r3, #2 80015a2: 6879 ldr r1, [r7, #4] 80015a4: 440b add r3, r1 80015a6: 681b ldr r3, [r3, #0] 80015a8: 429a cmp r2, r3 80015aa: da15 bge.n 80015d8 temp = src[j]; 80015ac: 693b ldr r3, [r7, #16] 80015ae: 009b lsls r3, r3, #2 80015b0: 687a ldr r2, [r7, #4] 80015b2: 4413 add r3, r2 80015b4: 681b ldr r3, [r3, #0] 80015b6: 60fb str r3, [r7, #12] src[j] = src[i]; 80015b8: 697b ldr r3, [r7, #20] 80015ba: 009b lsls r3, r3, #2 80015bc: 687a ldr r2, [r7, #4] 80015be: 441a add r2, r3 80015c0: 693b ldr r3, [r7, #16] 80015c2: 009b lsls r3, r3, #2 80015c4: 6879 ldr r1, [r7, #4] 80015c6: 440b add r3, r1 80015c8: 6812 ldr r2, [r2, #0] 80015ca: 601a str r2, [r3, #0] src[i] = temp; 80015cc: 697b ldr r3, [r7, #20] 80015ce: 009b lsls r3, r3, #2 80015d0: 687a ldr r2, [r7, #4] 80015d2: 4413 add r3, r2 80015d4: 68fa ldr r2, [r7, #12] 80015d6: 601a str r2, [r3, #0] for(int j = i+1 ; j < size ; j ++) { 80015d8: 693b ldr r3, [r7, #16] 80015da: 3301 adds r3, #1 80015dc: 613b str r3, [r7, #16] 80015de: 693b ldr r3, [r7, #16] 80015e0: 683a ldr r2, [r7, #0] 80015e2: 429a cmp r2, r3 80015e4: d8d6 bhi.n 8001594 for(int i = 0 ; i < size - 1 ; i ++) { 80015e6: 697b ldr r3, [r7, #20] 80015e8: 3301 adds r3, #1 80015ea: 617b str r3, [r7, #20] 80015ec: 683b ldr r3, [r7, #0] 80015ee: 1e5a subs r2, r3, #1 80015f0: 697b ldr r3, [r7, #20] 80015f2: 429a cmp r2, r3 80015f4: d8ca bhi.n 800158c // printf("temp"); } } } } 80015f6: bf00 nop 80015f8: 371c adds r7, #28 80015fa: 46bd mov sp, r7 80015fc: bc80 pop {r7} 80015fe: 4770 bx lr 08001600 : #define Percent100 5 void ADC_Check(){ 8001600: b580 push {r7, lr} 8001602: b082 sub sp, #8 8001604: af00 add r7, sp, #0 float tempval = 0; 8001606: f04f 0300 mov.w r3, #0 800160a: 607b str r3, [r7, #4] Currstatus.DownLink_Forward_Det_H = (((uint16_t)tempval & 0xFF00) >> 8); Currstatus.DownLink_Forward_Det_L = (((uint16_t)tempval & 0x00FF) ); #endif // PYJ.2020.09.09_END -- ADC_Value_Get(); 800160c: f7ff fec4 bl 8001398 // Currstatus.Temp_Monitor = ADC_Convert_Temperature((ADC1value[2]/1000)); // printf("Currstatus.DownLink_Forward_Det : %d \r\n",Currstatus.DownLink_Forward_Det_H << 8 | Currstatus.DownLink_Forward_Det_L); } 8001610: bf00 nop 8001612: 3708 adds r7, #8 8001614: 46bd mov sp, r7 8001616: bd80 pop {r7, pc} 08001618 : void ADC_TDD_Arrange(){ 8001618: b580 push {r7, lr} 800161a: b082 sub sp, #8 800161c: af00 add r7, sp, #0 uint32_t ADC1_Average_value = 0; 800161e: 2300 movs r3, #0 8001620: 603b str r3, [r7, #0] if(TDD_125ms_Cnt > ADC_DATA_CYCLE) 8001622: 4b1b ldr r3, [pc, #108] ; (8001690 ) 8001624: 681b ldr r3, [r3, #0] 8001626: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 800162a: d92d bls.n 8001688 { // printf("================TotalCnt %d =================\r\n",TotalCnt); #if 1 // PYJ.2020.09.09_BEGIN -- DascendigFunc(&ADC1_Arrage_Ret[0],ADC_AVERAGECNT); 800162c: 2132 movs r1, #50 ; 0x32 800162e: 4819 ldr r0, [pc, #100] ; (8001694 ) 8001630: f7ff ffa4 bl 800157c // for(int i = 0; i < 100; i++){/*ADC Data Dascending Complete*/ // printf("ADC1_Arrage_Ret[%d] : %d \r\n",i,ADC1_Arrage_Ret[i]); // } ADC1_Average_value = SumFunc(&ADC1_Arrage_Ret[0],Percent100); 8001634: 2105 movs r1, #5 8001636: 4817 ldr r0, [pc, #92] ; (8001694 ) 8001638: f7ff ff80 bl 800153c 800163c: 6038 str r0, [r7, #0] // printf("ADC1_Average_value Sum : %d \r\n",ADC1_Average_value); ADC1_Average_value /=Percent100; 800163e: 683b ldr r3, [r7, #0] 8001640: 4a15 ldr r2, [pc, #84] ; (8001698 ) 8001642: fba2 2303 umull r2, r3, r2, r3 8001646: 089b lsrs r3, r3, #2 8001648: 603b str r3, [r7, #0] // printf("ADC1_Average_value : %d \r\n",ADC1_Average_value); for(int i = 0; i < ADC_AVERAGECNT; i++){ 800164a: 2300 movs r3, #0 800164c: 607b str r3, [r7, #4] 800164e: e007 b.n 8001660 ADC1_Arrage_Ret[i] = 0; 8001650: 4a10 ldr r2, [pc, #64] ; (8001694 ) 8001652: 687b ldr r3, [r7, #4] 8001654: 2100 movs r1, #0 8001656: f842 1023 str.w r1, [r2, r3, lsl #2] for(int i = 0; i < ADC_AVERAGECNT; i++){ 800165a: 687b ldr r3, [r7, #4] 800165c: 3301 adds r3, #1 800165e: 607b str r3, [r7, #4] 8001660: 687b ldr r3, [r7, #4] 8001662: 2b31 cmp r3, #49 ; 0x31 8001664: ddf4 ble.n 8001650 } Currstatus.DownLink_Forward_Det_H = (((uint16_t)ADC1_Average_value & 0xFF00) >> 8); 8001666: 683b ldr r3, [r7, #0] 8001668: b29b uxth r3, r3 800166a: 0a1b lsrs r3, r3, #8 800166c: b29b uxth r3, r3 800166e: b2da uxtb r2, r3 8001670: 4b0a ldr r3, [pc, #40] ; (800169c ) 8001672: 71da strb r2, [r3, #7] Currstatus.DownLink_Forward_Det_L = (((uint16_t)ADC1_Average_value & 0x00FF) ); 8001674: 683b ldr r3, [r7, #0] 8001676: b2da uxtb r2, r3 8001678: 4b08 ldr r3, [pc, #32] ; (800169c ) 800167a: 721a strb r2, [r3, #8] ADC1_Arrage_Ret[i] = ADC1_Arrage[i]; } #endif // PYJ.2020.09.09_END -- TotalCnt = 0; 800167c: 4b08 ldr r3, [pc, #32] ; (80016a0 ) 800167e: 2200 movs r2, #0 8001680: 601a str r2, [r3, #0] TDD_125ms_Cnt = 0; 8001682: 4b03 ldr r3, [pc, #12] ; (8001690 ) 8001684: 2200 movs r2, #0 8001686: 601a str r2, [r3, #0] } } 8001688: bf00 nop 800168a: 3708 adds r7, #8 800168c: 46bd mov sp, r7 800168e: bd80 pop {r7, pc} 8001690: 20000508 .word 0x20000508 8001694: 200003f4 .word 0x200003f4 8001698: cccccccd .word 0xcccccccd 800169c: 2000057c .word 0x2000057c 80016a0: 200004c0 .word 0x200004c0 080016a4 : void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) { 80016a4: b580 push {r7, lr} 80016a6: b084 sub sp, #16 80016a8: af00 add r7, sp, #0 80016aa: 6078 str r0, [r7, #4] if(hadc->Instance == hadc1.Instance && TDD_125ms_Cnt < 125) 80016ac: 687b ldr r3, [r7, #4] 80016ae: 681a ldr r2, [r3, #0] 80016b0: 4b27 ldr r3, [pc, #156] ; (8001750 ) 80016b2: 681b ldr r3, [r3, #0] 80016b4: 429a cmp r2, r3 80016b6: d147 bne.n 8001748 80016b8: 4b26 ldr r3, [pc, #152] ; (8001754 ) 80016ba: 681b ldr r3, [r3, #0] 80016bc: 2b7c cmp r3, #124 ; 0x7c 80016be: d843 bhi.n 8001748 { ADC1_Arrage[adc1cnt] = ADC1value[0]; 80016c0: 4b25 ldr r3, [pc, #148] ; (8001758 ) 80016c2: 881b ldrh r3, [r3, #0] 80016c4: 461a mov r2, r3 80016c6: 4b25 ldr r3, [pc, #148] ; (800175c ) 80016c8: 881b ldrh r3, [r3, #0] 80016ca: b299 uxth r1, r3 80016cc: 4b24 ldr r3, [pc, #144] ; (8001760 ) 80016ce: f823 1012 strh.w r1, [r3, r2, lsl #1] // for(int i = 0; i < 2; i++){ // printf("ADC1value[%d] : %d , %f\r\n",i,ADC1value[i],(float)((ADC1value[i]) *3.3 /4095)); // } adc1cnt++; 80016d2: 4b21 ldr r3, [pc, #132] ; (8001758 ) 80016d4: 881b ldrh r3, [r3, #0] 80016d6: 3301 adds r3, #1 80016d8: b29a uxth r2, r3 80016da: 4b1f ldr r3, [pc, #124] ; (8001758 ) 80016dc: 801a strh r2, [r3, #0] if(adc1cnt == ADC_AVERAGECNT){ 80016de: 4b1e ldr r3, [pc, #120] ; (8001758 ) 80016e0: 881b ldrh r3, [r3, #0] 80016e2: 2b32 cmp r3, #50 ; 0x32 80016e4: d130 bne.n 8001748 // DascendigFunc(&ADC1_Arrage[0],ADC_AVERAGECNT); adc1cnt = 0; 80016e6: 4b1c ldr r3, [pc, #112] ; (8001758 ) 80016e8: 2200 movs r2, #0 80016ea: 801a strh r2, [r3, #0] TotalCnt++; 80016ec: 4b1d ldr r3, [pc, #116] ; (8001764 ) 80016ee: 681b ldr r3, [r3, #0] 80016f0: 3301 adds r3, #1 80016f2: 4a1c ldr r2, [pc, #112] ; (8001764 ) 80016f4: 6013 str r3, [r2, #0] if(TotalCnt > 2) 80016f6: 4b1b ldr r3, [pc, #108] ; (8001764 ) 80016f8: 681b ldr r3, [r3, #0] 80016fa: 2b02 cmp r3, #2 80016fc: d902 bls.n 8001704 TotalCnt = 2; 80016fe: 4b19 ldr r3, [pc, #100] ; (8001764 ) 8001700: 2202 movs r2, #2 8001702: 601a str r2, [r3, #0] for(int i = 0; i < ADC_AVERAGECNT; i++){/*ADC Data Dascending Complete*/ 8001704: 2300 movs r3, #0 8001706: 60fb str r3, [r7, #12] 8001708: e017 b.n 800173a if(ADC1_Arrage_Ret[i] <= ADC1_Arrage[i]) 800170a: 4a17 ldr r2, [pc, #92] ; (8001768 ) 800170c: 68fb ldr r3, [r7, #12] 800170e: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8001712: 4913 ldr r1, [pc, #76] ; (8001760 ) 8001714: 68fa ldr r2, [r7, #12] 8001716: f831 2012 ldrh.w r2, [r1, r2, lsl #1] 800171a: b292 uxth r2, r2 800171c: 4293 cmp r3, r2 800171e: d809 bhi.n 8001734 ADC1_Arrage_Ret[i] = ADC1_Arrage[i]; 8001720: 4a0f ldr r2, [pc, #60] ; (8001760 ) 8001722: 68fb ldr r3, [r7, #12] 8001724: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8001728: b29b uxth r3, r3 800172a: 4619 mov r1, r3 800172c: 4a0e ldr r2, [pc, #56] ; (8001768 ) 800172e: 68fb ldr r3, [r7, #12] 8001730: f842 1023 str.w r1, [r2, r3, lsl #2] for(int i = 0; i < ADC_AVERAGECNT; i++){/*ADC Data Dascending Complete*/ 8001734: 68fb ldr r3, [r7, #12] 8001736: 3301 adds r3, #1 8001738: 60fb str r3, [r7, #12] 800173a: 68fb ldr r3, [r7, #12] 800173c: 2b31 cmp r3, #49 ; 0x31 800173e: dde4 ble.n 800170a } DascendigFunc(&ADC1_Arrage_Ret[0],ADC_AVERAGECNT); 8001740: 2132 movs r1, #50 ; 0x32 8001742: 4809 ldr r0, [pc, #36] ; (8001768 ) 8001744: f7ff ff1a bl 800157c // ADC1valuearray[i][adc1cnt] = ADC1value[i]; // } // adc1cnt++; // } } } 8001748: bf00 nop 800174a: 3710 adds r7, #16 800174c: 46bd mov sp, r7 800174e: bd80 pop {r7, pc} 8001750: 200008a8 .word 0x200008a8 8001754: 20000508 .word 0x20000508 8001758: 200004bc .word 0x200004bc 800175c: 20000594 .word 0x20000594 8001760: 20000390 .word 0x20000390 8001764: 200004c0 .word 0x200004c0 8001768: 200003f4 .word 0x200003f4 0800176c : crcret ^ ~0U; return (crcret == checksum ? CHECKSUM_ERROR : NO_ERROR); } uint8_t NessLab_Checksum(uint8_t *data,uint8_t size){ 800176c: b480 push {r7} 800176e: b085 sub sp, #20 8001770: af00 add r7, sp, #0 8001772: 6078 str r0, [r7, #4] 8001774: 460b mov r3, r1 8001776: 70fb strb r3, [r7, #3] uint16_t ret = 0; 8001778: 2300 movs r3, #0 800177a: 81fb strh r3, [r7, #14] // printf("Crc Process : "); for(int i = 0; i < size; i++){ 800177c: 2300 movs r3, #0 800177e: 60bb str r3, [r7, #8] 8001780: e00c b.n 800179c ret = ((ret + data[i]) & 0xFF); 8001782: 68bb ldr r3, [r7, #8] 8001784: 687a ldr r2, [r7, #4] 8001786: 4413 add r3, r2 8001788: 781b ldrb r3, [r3, #0] 800178a: b29a uxth r2, r3 800178c: 89fb ldrh r3, [r7, #14] 800178e: 4413 add r3, r2 8001790: b29b uxth r3, r3 8001792: b2db uxtb r3, r3 8001794: 81fb strh r3, [r7, #14] for(int i = 0; i < size; i++){ 8001796: 68bb ldr r3, [r7, #8] 8001798: 3301 adds r3, #1 800179a: 60bb str r3, [r7, #8] 800179c: 78fb ldrb r3, [r7, #3] 800179e: 68ba ldr r2, [r7, #8] 80017a0: 429a cmp r2, r3 80017a2: dbee blt.n 8001782 // printf(" %x + %x \r\n",ret,data[i]); } // printf("Result : "); ret = (~ret) + 1; 80017a4: 89fb ldrh r3, [r7, #14] 80017a6: 425b negs r3, r3 80017a8: 81fb strh r3, [r7, #14] // printf("ret [i] : %x \r\n",ret); return (uint8_t)(ret & 0x00FF); 80017aa: 89fb ldrh r3, [r7, #14] 80017ac: b2db uxtb r3, r3 } 80017ae: 4618 mov r0, r3 80017b0: 3714 adds r7, #20 80017b2: 46bd mov sp, r7 80017b4: bc80 pop {r7} 80017b6: 4770 bx lr 080017b8 : bool NessLab_CheckSum_Check(uint8_t* data,uint8_t size,uint8_t checksum){ 80017b8: b480 push {r7} 80017ba: b085 sub sp, #20 80017bc: af00 add r7, sp, #0 80017be: 6078 str r0, [r7, #4] 80017c0: 460b mov r3, r1 80017c2: 70fb strb r3, [r7, #3] 80017c4: 4613 mov r3, r2 80017c6: 70bb strb r3, [r7, #2] uint8_t dataret = 0; 80017c8: 2300 movs r3, #0 80017ca: 73fb strb r3, [r7, #15] bool ret = false; 80017cc: 2300 movs r3, #0 80017ce: 73bb strb r3, [r7, #14] // printf("size : %d \r\n",size); for(int i = 0; i < size; i++){ 80017d0: 2300 movs r3, #0 80017d2: 60bb str r3, [r7, #8] 80017d4: e009 b.n 80017ea dataret += data[i]; 80017d6: 68bb ldr r3, [r7, #8] 80017d8: 687a ldr r2, [r7, #4] 80017da: 4413 add r3, r2 80017dc: 781a ldrb r2, [r3, #0] 80017de: 7bfb ldrb r3, [r7, #15] 80017e0: 4413 add r3, r2 80017e2: 73fb strb r3, [r7, #15] for(int i = 0; i < size; i++){ 80017e4: 68bb ldr r3, [r7, #8] 80017e6: 3301 adds r3, #1 80017e8: 60bb str r3, [r7, #8] 80017ea: 78fb ldrb r3, [r7, #3] 80017ec: 68ba ldr r2, [r7, #8] 80017ee: 429a cmp r2, r3 80017f0: dbf1 blt.n 80017d6 // printf("data [i] : %x \r\n",data[i]); } dataret = (~dataret) + 1; 80017f2: 7bfb ldrb r3, [r7, #15] 80017f4: 425b negs r3, r3 80017f6: 73fb strb r3, [r7, #15] // printf("\r\ndataret : %x /// checksum : %x \r\n",dataret,checksum); if(dataret != checksum){ 80017f8: 7bfa ldrb r2, [r7, #15] 80017fa: 78bb ldrb r3, [r7, #2] 80017fc: 429a cmp r2, r3 80017fe: d002 beq.n 8001806 ret = false; 8001800: 2300 movs r3, #0 8001802: 73bb strb r3, [r7, #14] 8001804: e001 b.n 800180a }else{ ret = true; 8001806: 2301 movs r3, #1 8001808: 73bb strb r3, [r7, #14] } return ret; 800180a: 7bbb ldrb r3, [r7, #14] } 800180c: 4618 mov r0, r3 800180e: 3714 adds r7, #20 8001810: 46bd mov sp, r7 8001812: bc80 pop {r7} 8001814: 4770 bx lr ... 08001818 : __set_MSP(*(__IO uint32_t*) APPLICATION_ADDRESS); jump_to_app(); } bool EraseInit = false; void DataErase_Func(uint32_t User_Address,uint32_t size){ 8001818: b580 push {r7, lr} 800181a: b082 sub sp, #8 800181c: af00 add r7, sp, #0 800181e: 6078 str r0, [r7, #4] 8001820: 6039 str r1, [r7, #0] static FLASH_EraseInitTypeDef EraseInitStruct; static uint32_t PAGEError = 0; HAL_FLASH_Unlock(); 8001822: f001 fb69 bl 8002ef8 EraseInitStruct.TypeErase = FLASH_TYPEERASE_PAGES; 8001826: 4b1b ldr r3, [pc, #108] ; (8001894 ) 8001828: 2200 movs r2, #0 800182a: 601a str r2, [r3, #0] EraseInitStruct.PageAddress = FLASH_USER_USE_START_ADDR; 800182c: 4b19 ldr r3, [pc, #100] ; (8001894 ) 800182e: 4a1a ldr r2, [pc, #104] ; (8001898 ) 8001830: 609a str r2, [r3, #8] EraseInitStruct.NbPages = ((FLASH_USER_END_ADDR - FLASH_USER_USE_START_ADDR) / FLASH_PAGE_SIZE) + 1; 8001832: 4b18 ldr r3, [pc, #96] ; (8001894 ) 8001834: 2201 movs r2, #1 8001836: 60da str r2, [r3, #12] UserAddress = User_Address; 8001838: 4a18 ldr r2, [pc, #96] ; (800189c ) 800183a: 687b ldr r3, [r7, #4] 800183c: 6013 str r3, [r2, #0] printf("NbPages : %x \r\n",EraseInitStruct.NbPages ); 800183e: 4b15 ldr r3, [pc, #84] ; (8001894 ) 8001840: 68db ldr r3, [r3, #12] 8001842: 4619 mov r1, r3 8001844: 4816 ldr r0, [pc, #88] ; (80018a0 ) 8001846: f004 ff17 bl 8006678 printf("EraseInitStruct.PageAddress : %x \r\n",EraseInitStruct.PageAddress); 800184a: 4b12 ldr r3, [pc, #72] ; (8001894 ) 800184c: 689b ldr r3, [r3, #8] 800184e: 4619 mov r1, r3 8001850: 4814 ldr r0, [pc, #80] ; (80018a4 ) 8001852: f004 ff11 bl 8006678 printf("Erase Start\r\n"); 8001856: 4814 ldr r0, [pc, #80] ; (80018a8 ) 8001858: f004 ff82 bl 8006760 if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK) 800185c: 4913 ldr r1, [pc, #76] ; (80018ac ) 800185e: 480d ldr r0, [pc, #52] ; (8001894 ) 8001860: f001 fc32 bl 80030c8 8001864: 4603 mov r3, r0 8001866: 2b00 cmp r3, #0 8001868: d007 beq.n 800187a */ /* Infinite loop */ while (1) { /* Make LED2 blink (100ms on, 2s off) to indicate error in Erase operation */ printf("HAL_FLASHEx_Erase Error\r\n"); 800186a: 4811 ldr r0, [pc, #68] ; (80018b0 ) 800186c: f004 ff78 bl 8006760 HAL_Delay(2000); 8001870: f44f 60fa mov.w r0, #2000 ; 0x7d0 8001874: f000 fa8a bl 8001d8c printf("HAL_FLASHEx_Erase Error\r\n"); 8001878: e7f7 b.n 800186a } } EraseInit = true; 800187a: 4b0e ldr r3, [pc, #56] ; (80018b4 ) 800187c: 2201 movs r2, #1 800187e: 701a strb r2, [r3, #0] printf("Erase End\r\n"); 8001880: 480d ldr r0, [pc, #52] ; (80018b8 ) 8001882: f004 ff6d bl 8006760 HAL_FLASH_Lock(); 8001886: f001 fb5d bl 8002f44 } 800188a: bf00 nop 800188c: 3708 adds r7, #8 800188e: 46bd mov sp, r7 8001890: bd80 pop {r7, pc} 8001892: bf00 nop 8001894: 200004cc .word 0x200004cc 8001898: 0800ff38 .word 0x0800ff38 800189c: 200004c4 .word 0x200004c4 80018a0: 08008728 .word 0x08008728 80018a4: 08008738 .word 0x08008738 80018a8: 0800875c .word 0x0800875c 80018ac: 200004dc .word 0x200004dc 80018b0: 0800876c .word 0x0800876c 80018b4: 200004c8 .word 0x200004c8 80018b8: 08008788 .word 0x08008788 080018bc : uint8_t FLASH_Write_Func(uint32_t User_Address,uint8_t* data,uint32_t size){ 80018bc: b590 push {r4, r7, lr} 80018be: b08b sub sp, #44 ; 0x2c 80018c0: af00 add r7, sp, #0 80018c2: 60f8 str r0, [r7, #12] 80018c4: 60b9 str r1, [r7, #8] 80018c6: 607a str r2, [r7, #4] //static FLASH_EraseInitTypeDef EraseInitStruct; //static uint32_t PAGEError = 0; static uint32_t DownloadIndex; static __IO uint32_t data32 = 0 , MemoryProgramStatus = 0; int dataindex = 0; 80018c8: 2300 movs r3, #0 80018ca: 623b str r3, [r7, #32] uint32_t writedata = 0; 80018cc: 2300 movs r3, #0 80018ce: 61fb str r3, [r7, #28] uint32_t CurrApiAddress = 0; 80018d0: 2300 movs r3, #0 80018d2: 61bb str r3, [r7, #24] uint8_t ret = 0; 80018d4: 2300 movs r3, #0 80018d6: 75fb strb r3, [r7, #23] CurrApiAddress = User_Address; 80018d8: 68fb ldr r3, [r7, #12] 80018da: 61bb str r3, [r7, #24] uint8_t* Currdata = (uint8_t*)CurrApiAddress; 80018dc: 69bb ldr r3, [r7, #24] 80018de: 613b str r3, [r7, #16] printf("HAL_FLASH_Program Start\r\n"); 80018e0: 4833 ldr r0, [pc, #204] ; (80019b0 ) 80018e2: f004 ff3d bl 8006760 DownloadIndex += size; 80018e6: 4b33 ldr r3, [pc, #204] ; (80019b4 ) 80018e8: 681a ldr r2, [r3, #0] 80018ea: 687b ldr r3, [r7, #4] 80018ec: 4413 add r3, r2 80018ee: 4a31 ldr r2, [pc, #196] ; (80019b4 ) 80018f0: 6013 str r3, [r2, #0] printf("User_Address : %x \r\n",UserAddress); 80018f2: 4b31 ldr r3, [pc, #196] ; (80019b8 ) 80018f4: 681b ldr r3, [r3, #0] 80018f6: 4619 mov r1, r3 80018f8: 4830 ldr r0, [pc, #192] ; (80019bc ) 80018fa: f004 febd bl 8006678 HAL_FLASH_Unlock(); 80018fe: f001 fafb bl 8002ef8 for(int downindex = 0; downindex < size; downindex+=4) 8001902: 2300 movs r3, #0 8001904: 627b str r3, [r7, #36] ; 0x24 8001906: e041 b.n 800198c { writedata = data[downindex + 0] ; 8001908: 6a7b ldr r3, [r7, #36] ; 0x24 800190a: 68ba ldr r2, [r7, #8] 800190c: 4413 add r3, r2 800190e: 781b ldrb r3, [r3, #0] 8001910: 61fb str r3, [r7, #28] writedata += data[downindex + 1] << 8 ; 8001912: 6a7b ldr r3, [r7, #36] ; 0x24 8001914: 3301 adds r3, #1 8001916: 68ba ldr r2, [r7, #8] 8001918: 4413 add r3, r2 800191a: 781b ldrb r3, [r3, #0] 800191c: 021b lsls r3, r3, #8 800191e: 461a mov r2, r3 8001920: 69fb ldr r3, [r7, #28] 8001922: 4413 add r3, r2 8001924: 61fb str r3, [r7, #28] writedata += data[downindex + 2] << 16; 8001926: 6a7b ldr r3, [r7, #36] ; 0x24 8001928: 3302 adds r3, #2 800192a: 68ba ldr r2, [r7, #8] 800192c: 4413 add r3, r2 800192e: 781b ldrb r3, [r3, #0] 8001930: 041b lsls r3, r3, #16 8001932: 461a mov r2, r3 8001934: 69fb ldr r3, [r7, #28] 8001936: 4413 add r3, r2 8001938: 61fb str r3, [r7, #28] writedata += data[downindex + 3] << 24; 800193a: 6a7b ldr r3, [r7, #36] ; 0x24 800193c: 3303 adds r3, #3 800193e: 68ba ldr r2, [r7, #8] 8001940: 4413 add r3, r2 8001942: 781b ldrb r3, [r3, #0] 8001944: 061b lsls r3, r3, #24 8001946: 461a mov r2, r3 8001948: 69fb ldr r3, [r7, #28] 800194a: 4413 add r3, r2 800194c: 61fb str r3, [r7, #28] if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, UserAddress,writedata) == HAL_OK) 800194e: 4b1a ldr r3, [pc, #104] ; (80019b8 ) 8001950: 6819 ldr r1, [r3, #0] 8001952: 69fb ldr r3, [r7, #28] 8001954: f04f 0400 mov.w r4, #0 8001958: 461a mov r2, r3 800195a: 4623 mov r3, r4 800195c: 2002 movs r0, #2 800195e: f001 fa5b bl 8002e18 8001962: 4603 mov r3, r0 8001964: 2b00 cmp r3, #0 8001966: d105 bne.n 8001974 { UserAddress += 4; 8001968: 4b13 ldr r3, [pc, #76] ; (80019b8 ) 800196a: 681b ldr r3, [r3, #0] 800196c: 3304 adds r3, #4 800196e: 4a12 ldr r2, [pc, #72] ; (80019b8 ) 8001970: 6013 str r3, [r2, #0] 8001972: e008 b.n 8001986 } else { printf("HAL_FLASH_Program Error\r\n"); 8001974: 4812 ldr r0, [pc, #72] ; (80019c0 ) 8001976: f004 fef3 bl 8006760 printf("Flash Failed %x \r\n",UserAddress); 800197a: 4b0f ldr r3, [pc, #60] ; (80019b8 ) 800197c: 681b ldr r3, [r3, #0] 800197e: 4619 mov r1, r3 8001980: 4810 ldr r0, [pc, #64] ; (80019c4 ) 8001982: f004 fe79 bl 8006678 for(int downindex = 0; downindex < size; downindex+=4) 8001986: 6a7b ldr r3, [r7, #36] ; 0x24 8001988: 3304 adds r3, #4 800198a: 627b str r3, [r7, #36] ; 0x24 800198c: 6a7b ldr r3, [r7, #36] ; 0x24 800198e: 687a ldr r2, [r7, #4] 8001990: 429a cmp r2, r3 8001992: d8b9 bhi.n 8001908 } } printf("HAL_FLASH_Program END %x \r\n",UserAddress); 8001994: 4b08 ldr r3, [pc, #32] ; (80019b8 ) 8001996: 681b ldr r3, [r3, #0] 8001998: 4619 mov r1, r3 800199a: 480b ldr r0, [pc, #44] ; (80019c8 ) 800199c: f004 fe6c bl 8006678 /* Lock the Flash to disable the flash control register access (recommended to protect the FLASH memory against possible unwanted operation) *********/ HAL_FLASH_Lock(); 80019a0: f001 fad0 bl 8002f44 return 0; 80019a4: 2300 movs r3, #0 /* Check if the programmed data is OK MemoryProgramStatus = 0: data programmed correctly MemoryProgramStatus != 0: number of words not programmed correctly ******/ } 80019a6: 4618 mov r0, r3 80019a8: 372c adds r7, #44 ; 0x2c 80019aa: 46bd mov sp, r7 80019ac: bd90 pop {r4, r7, pc} 80019ae: bf00 nop 80019b0: 08008794 .word 0x08008794 80019b4: 200004e0 .word 0x200004e0 80019b8: 200004c4 .word 0x200004c4 80019bc: 080087b0 .word 0x080087b0 80019c0: 080087c8 .word 0x080087c8 80019c4: 080087e4 .word 0x080087e4 80019c8: 080087f8 .word 0x080087f8 080019cc : void FLASH_Read_Func(uint32_t User_Address,uint8_t* dst,uint32_t size){ 80019cc: b580 push {r7, lr} 80019ce: b088 sub sp, #32 80019d0: af00 add r7, sp, #0 80019d2: 60f8 str r0, [r7, #12] 80019d4: 60b9 str r1, [r7, #8] 80019d6: 607a str r2, [r7, #4] uint32_t CurrApiAddress = 0; 80019d8: 2300 movs r3, #0 80019da: 61bb str r3, [r7, #24] uint32_t i = 0; 80019dc: 2300 movs r3, #0 80019de: 617b str r3, [r7, #20] //uint8_t ret = 0; CurrApiAddress = User_Address; 80019e0: 68fb ldr r3, [r7, #12] 80019e2: 61bb str r3, [r7, #24] uint8_t* Currdata = (uint8_t*)CurrApiAddress; 80019e4: 69bb ldr r3, [r7, #24] 80019e6: 613b str r3, [r7, #16] printf("Flash Read size : %d \r\n",size); 80019e8: 6879 ldr r1, [r7, #4] 80019ea: 4810 ldr r0, [pc, #64] ; (8001a2c ) 80019ec: f004 fe44 bl 8006678 for(int i = 0; i < size; i++){ 80019f0: 2300 movs r3, #0 80019f2: 61fb str r3, [r7, #28] 80019f4: e012 b.n 8001a1c dst[i] = Currdata[i]; 80019f6: 69fb ldr r3, [r7, #28] 80019f8: 693a ldr r2, [r7, #16] 80019fa: 441a add r2, r3 80019fc: 69fb ldr r3, [r7, #28] 80019fe: 68b9 ldr r1, [r7, #8] 8001a00: 440b add r3, r1 8001a02: 7812 ldrb r2, [r2, #0] 8001a04: 701a strb r2, [r3, #0] printf("%02x ",dst[i]); 8001a06: 69fb ldr r3, [r7, #28] 8001a08: 68ba ldr r2, [r7, #8] 8001a0a: 4413 add r3, r2 8001a0c: 781b ldrb r3, [r3, #0] 8001a0e: 4619 mov r1, r3 8001a10: 4807 ldr r0, [pc, #28] ; (8001a30 ) 8001a12: f004 fe31 bl 8006678 for(int i = 0; i < size; i++){ 8001a16: 69fb ldr r3, [r7, #28] 8001a18: 3301 adds r3, #1 8001a1a: 61fb str r3, [r7, #28] 8001a1c: 69fb ldr r3, [r7, #28] 8001a1e: 687a ldr r2, [r7, #4] 8001a20: 429a cmp r2, r3 8001a22: d8e8 bhi.n 80019f6 } } 8001a24: bf00 nop 8001a26: 3720 adds r7, #32 8001a28: 46bd mov sp, r7 8001a2a: bd80 pop {r7, pc} 8001a2c: 08008818 .word 0x08008818 8001a30: 08008830 .word 0x08008830 08001a34 : #include "main.h" #include "led.h" volatile uint32_t LED_TimerCnt = 0; uint32_t LedTimerCnt_Get(){ 8001a34: b480 push {r7} 8001a36: af00 add r7, sp, #0 return LED_TimerCnt; 8001a38: 4b02 ldr r3, [pc, #8] ; (8001a44 ) 8001a3a: 681b ldr r3, [r3, #0] } 8001a3c: 4618 mov r0, r3 8001a3e: 46bd mov sp, r7 8001a40: bc80 pop {r7} 8001a42: 4770 bx lr 8001a44: 200004e4 .word 0x200004e4 08001a48 : void LedTimerCnt_Set(uint32_t val){ 8001a48: b480 push {r7} 8001a4a: b083 sub sp, #12 8001a4c: af00 add r7, sp, #0 8001a4e: 6078 str r0, [r7, #4] LED_TimerCnt = val; 8001a50: 4a03 ldr r2, [pc, #12] ; (8001a60 ) 8001a52: 687b ldr r3, [r7, #4] 8001a54: 6013 str r3, [r2, #0] } 8001a56: bf00 nop 8001a58: 370c adds r7, #12 8001a5a: 46bd mov sp, r7 8001a5c: bc80 pop {r7} 8001a5e: 4770 bx lr 8001a60: 200004e4 .word 0x200004e4 08001a64 : void Boot_LED_Toggle(){ /*LED Check*/ 8001a64: b580 push {r7, lr} 8001a66: b082 sub sp, #8 8001a68: af00 add r7, sp, #0 uint32_t Led_Cnt = LedTimerCnt_Get(); 8001a6a: f7ff ffe3 bl 8001a34 8001a6e: 6078 str r0, [r7, #4] if(Led_Cnt >= LED_TOGGLE_CNT_REF){ 8001a70: 687b ldr r3, [r7, #4] 8001a72: f5b3 7ffa cmp.w r3, #500 ; 0x1f4 8001a76: d307 bcc.n 8001a88 HAL_GPIO_TogglePin(BOOT_LED_GPIO_Port, BOOT_LED_Pin); 8001a78: f44f 4100 mov.w r1, #32768 ; 0x8000 8001a7c: 4804 ldr r0, [pc, #16] ; (8001a90 ) 8001a7e: f001 fd54 bl 800352a LedTimerCnt_Set(0); 8001a82: 2000 movs r0, #0 8001a84: f7ff ffe0 bl 8001a48 } } 8001a88: bf00 nop 8001a8a: 3708 adds r7, #8 8001a8c: 46bd mov sp, r7 8001a8e: bd80 pop {r7, pc} 8001a90: 40011000 .word 0x40011000 08001a94 : extern bool Bluecell_Operate(uint8_t* data); extern void MBIC_Operate(uint8_t * data); extern bool NessLab_CheckSum_Check(uint8_t* data,uint8_t size,uint8_t checksum); void InitUartQueue(pUARTQUEUE pQueue) { 8001a94: b580 push {r7, lr} 8001a96: b082 sub sp, #8 8001a98: af00 add r7, sp, #0 8001a9a: 6078 str r0, [r7, #4] pQueue->data = pQueue->head = pQueue->tail = 0; 8001a9c: 687b ldr r3, [r7, #4] 8001a9e: 2200 movs r2, #0 8001aa0: 605a str r2, [r3, #4] 8001aa2: 687b ldr r3, [r7, #4] 8001aa4: 685a ldr r2, [r3, #4] 8001aa6: 687b ldr r3, [r7, #4] 8001aa8: 601a str r2, [r3, #0] 8001aaa: 687b ldr r3, [r7, #4] 8001aac: 681a ldr r2, [r3, #0] 8001aae: 687b ldr r3, [r7, #4] 8001ab0: 609a str r2, [r3, #8] uart_hal_tx.output_p = uart_hal_tx.input_p = 0; 8001ab2: 2100 movs r1, #0 8001ab4: 4b08 ldr r3, [pc, #32] ; (8001ad8 ) 8001ab6: 460a mov r2, r1 8001ab8: f8a3 2080 strh.w r2, [r3, #128] ; 0x80 8001abc: 4b06 ldr r3, [pc, #24] ; (8001ad8 ) 8001abe: 460a mov r2, r1 8001ac0: f8a3 2082 strh.w r2, [r3, #130] ; 0x82 // HAL_UART_Receive_IT(&huart2,rxBuf,5); if (HAL_UART_Receive_IT(&hMain, MainQueue.Buffer, 1) != HAL_OK) 8001ac4: 2201 movs r2, #1 8001ac6: 4905 ldr r1, [pc, #20] ; (8001adc ) 8001ac8: 4805 ldr r0, [pc, #20] ; (8001ae0 ) 8001aca: f002 fd93 bl 80045f4 // { //// _Error_Handler(__FILE__, __LINE__); // } //HAL_UART_Receive_DMA(&hTerminal, TerminalQueue.Buffer, 1); //HAL_UART_Receive_IT(hTerminal, pQueue->Buffer + pQueue->head, 1); } 8001ace: bf00 nop 8001ad0: 3708 adds r7, #8 8001ad2: 46bd mov sp, r7 8001ad4: bd80 pop {r7, pc} 8001ad6: bf00 nop 8001ad8: 20000734 .word 0x20000734 8001adc: 20000628 .word 0x20000628 8001ae0: 200008d8 .word 0x200008d8 08001ae4 : void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { 8001ae4: b580 push {r7, lr} 8001ae6: b084 sub sp, #16 8001ae8: af00 add r7, sp, #0 8001aea: 6078 str r0, [r7, #4] // UART_HandleTypeDef *dst = (huart->Instance == USART2 ? &hTest:&hTerminal); pUARTQUEUE pQueue; // printf("Function : %s : \r\n",__func__); //printf("%02x ",uart_buf[i]); UartRxTimerCnt = 0; 8001aec: 4b15 ldr r3, [pc, #84] ; (8001b44 ) 8001aee: 2200 movs r2, #0 8001af0: 601a str r2, [r3, #0] pQueue = &MainQueue; 8001af2: 4b15 ldr r3, [pc, #84] ; (8001b48 ) 8001af4: 60fb str r3, [r7, #12] pQueue->head++; 8001af6: 68fb ldr r3, [r7, #12] 8001af8: 681b ldr r3, [r3, #0] 8001afa: 1c5a adds r2, r3, #1 8001afc: 68fb ldr r3, [r7, #12] 8001afe: 601a str r2, [r3, #0] if (pQueue->head >= QUEUE_BUFFER_LENGTH) pQueue->head = 0; 8001b00: 68fb ldr r3, [r7, #12] 8001b02: 681b ldr r3, [r3, #0] 8001b04: 2b7f cmp r3, #127 ; 0x7f 8001b06: dd02 ble.n 8001b0e 8001b08: 68fb ldr r3, [r7, #12] 8001b0a: 2200 movs r2, #0 8001b0c: 601a str r2, [r3, #0] pQueue->data++; 8001b0e: 68fb ldr r3, [r7, #12] 8001b10: 689b ldr r3, [r3, #8] 8001b12: 1c5a adds r2, r3, #1 8001b14: 68fb ldr r3, [r7, #12] 8001b16: 609a str r2, [r3, #8] if (pQueue->data >= QUEUE_BUFFER_LENGTH) 8001b18: 68fb ldr r3, [r7, #12] 8001b1a: 689b ldr r3, [r3, #8] 8001b1c: 2b7f cmp r3, #127 ; 0x7f 8001b1e: dd02 ble.n 8001b26 GetDataFromUartQueue(huart); 8001b20: 6878 ldr r0, [r7, #4] 8001b22: f000 f815 bl 8001b50 HAL_UART_Receive_IT(&hMain, pQueue->Buffer + pQueue->head, 1); 8001b26: 68fb ldr r3, [r7, #12] 8001b28: 330c adds r3, #12 8001b2a: 68fa ldr r2, [r7, #12] 8001b2c: 6812 ldr r2, [r2, #0] 8001b2e: 4413 add r3, r2 8001b30: 2201 movs r2, #1 8001b32: 4619 mov r1, r3 8001b34: 4805 ldr r0, [pc, #20] ; (8001b4c ) 8001b36: f002 fd5d bl 80045f4 // HAL_UART_Receive_DMA(&hTest, pQueue->Buffer + pQueue->head, 1); // Set_UartRcv(true); } 8001b3a: bf00 nop 8001b3c: 3710 adds r7, #16 8001b3e: 46bd mov sp, r7 8001b40: bd80 pop {r7, pc} 8001b42: bf00 nop 8001b44: 200004ec .word 0x200004ec 8001b48: 2000061c .word 0x2000061c 8001b4c: 200008d8 .word 0x200008d8 08001b50 : // HAL_UART_Receive_DMA(&hTerminal, pQueue->Buffer + pQueue->head, 10); } void GetDataFromUartQueue(UART_HandleTypeDef *huart) { 8001b50: b580 push {r7, lr} 8001b52: b086 sub sp, #24 8001b54: af00 add r7, sp, #0 8001b56: 6078 str r0, [r7, #4] volatile static int cnt; bool ret = 0; 8001b58: 2300 movs r3, #0 8001b5a: 75fb strb r3, [r7, #23] /* bool chksumret = 0; uint16_t Length = 0; uint16_t CrcChk = 0; UART_HandleTypeDef *dst = (huart->Instance == USART2 ? &hTest:&hTerminal);*/ // UART_HandleTypeDef *dst = &hTerminal; pUARTQUEUE pQueue = &MainQueue; 8001b5c: 4b48 ldr r3, [pc, #288] ; (8001c80 ) 8001b5e: 60fb str r3, [r7, #12] // if (HAL_UART_Transmit(dst, pQueue->Buffer + pQueue->tail, 1, 3000) != HAL_OK) // { // _Error_Handler(__FILE__, __LINE__); // } uart_buf[cnt++] = *(pQueue->Buffer + pQueue->tail); 8001b60: 68fb ldr r3, [r7, #12] 8001b62: 330c adds r3, #12 8001b64: 68fa ldr r2, [r7, #12] 8001b66: 6852 ldr r2, [r2, #4] 8001b68: 441a add r2, r3 8001b6a: 4b46 ldr r3, [pc, #280] ; (8001c84 ) 8001b6c: 681b ldr r3, [r3, #0] 8001b6e: 1c59 adds r1, r3, #1 8001b70: 4844 ldr r0, [pc, #272] ; (8001c84 ) 8001b72: 6001 str r1, [r0, #0] 8001b74: 7811 ldrb r1, [r2, #0] 8001b76: 4a44 ldr r2, [pc, #272] ; (8001c88 ) 8001b78: 54d1 strb r1, [r2, r3] //#ifdef DEBUG_PRINT // printf("%02x ",*(pQueue->Buffer + pQueue->tail)) ; //#endif /* DEBUG_PRINT */ pQueue->tail++; 8001b7a: 68fb ldr r3, [r7, #12] 8001b7c: 685b ldr r3, [r3, #4] 8001b7e: 1c5a adds r2, r3, #1 8001b80: 68fb ldr r3, [r7, #12] 8001b82: 605a str r2, [r3, #4] if (pQueue->tail >= QUEUE_BUFFER_LENGTH) pQueue->tail = 0; 8001b84: 68fb ldr r3, [r7, #12] 8001b86: 685b ldr r3, [r3, #4] 8001b88: 2b7f cmp r3, #127 ; 0x7f 8001b8a: dd02 ble.n 8001b92 8001b8c: 68fb ldr r3, [r7, #12] 8001b8e: 2200 movs r2, #0 8001b90: 605a str r2, [r3, #4] pQueue->data--; 8001b92: 68fb ldr r3, [r7, #12] 8001b94: 689b ldr r3, [r3, #8] 8001b96: 1e5a subs r2, r3, #1 8001b98: 68fb ldr r3, [r7, #12] 8001b9a: 609a str r2, [r3, #8] if(pQueue->data == 0){ 8001b9c: 68fb ldr r3, [r7, #12] 8001b9e: 689b ldr r3, [r3, #8] 8001ba0: 2b00 cmp r3, #0 8001ba2: d169 bne.n 8001c78 // printf("data cnt zero !!! \r\n"); //RF_Ctrl_Main(&uart_buf[Header]); // HAL_UART_Transmit(dst, &temp_buf[BLUECELL_HEADER00], 11, 3000); #if 1// PYJ.2019.07.15_BEGIN -- printf("\r\n[RX]"); 8001ba4: 4839 ldr r0, [pc, #228] ; (8001c8c ) 8001ba6: f004 fd67 bl 8006678 for(int i = 0; i < cnt; i++){ 8001baa: 2300 movs r3, #0 8001bac: 613b str r3, [r7, #16] 8001bae: e00b b.n 8001bc8 printf("%02x ",uart_buf[i]); 8001bb0: 4a35 ldr r2, [pc, #212] ; (8001c88 ) 8001bb2: 693b ldr r3, [r7, #16] 8001bb4: 4413 add r3, r2 8001bb6: 781b ldrb r3, [r3, #0] 8001bb8: b2db uxtb r3, r3 8001bba: 4619 mov r1, r3 8001bbc: 4834 ldr r0, [pc, #208] ; (8001c90 ) 8001bbe: f004 fd5b bl 8006678 for(int i = 0; i < cnt; i++){ 8001bc2: 693b ldr r3, [r7, #16] 8001bc4: 3301 adds r3, #1 8001bc6: 613b str r3, [r7, #16] 8001bc8: 4b2e ldr r3, [pc, #184] ; (8001c84 ) 8001bca: 681b ldr r3, [r3, #0] 8001bcc: 693a ldr r2, [r7, #16] 8001bce: 429a cmp r2, r3 8001bd0: dbee blt.n 8001bb0 } printf("\r\n"); 8001bd2: 4830 ldr r0, [pc, #192] ; (8001c94 ) 8001bd4: f004 fdc4 bl 8006760 // printf("Checksum Index : %d %x\r\n",uart_buf[NessLab_Req_DataLength] + NessLab_Req_DataLength + 1,uart_buf[uart_buf[NessLab_Req_DataLength] + NessLab_Req_DataLength + 1]); // printf(ANSI_COLOR_GREEN"\r\n CNT : %d \r\n"ANSI_COLOR_RESET,cnt); #endif // PYJ.2019.07.15_END -- if(uart_buf[NessLab_Req_MsgID0] == NessLab_Table_REQ) 8001bd8: 4b2b ldr r3, [pc, #172] ; (8001c88 ) 8001bda: 789b ldrb r3, [r3, #2] 8001bdc: b2db uxtb r3, r3 8001bde: 2bc9 cmp r3, #201 ; 0xc9 8001be0: d10c bne.n 8001bfc ret = NessLab_CheckSum_Check(&uart_buf[NessLab_Req_MsgID0],uart_buf[NessLab_Req_DataLength] ,uart_buf[NessLab_Req_ChecksumVal]); 8001be2: 4b29 ldr r3, [pc, #164] ; (8001c88 ) 8001be4: 799b ldrb r3, [r3, #6] 8001be6: b2d9 uxtb r1, r3 8001be8: 4b27 ldr r3, [pc, #156] ; (8001c88 ) 8001bea: 7a5b ldrb r3, [r3, #9] 8001bec: b2db uxtb r3, r3 8001bee: 461a mov r2, r3 8001bf0: 4829 ldr r0, [pc, #164] ; (8001c98 ) 8001bf2: f7ff fde1 bl 80017b8 8001bf6: 4603 mov r3, r0 8001bf8: 75fb strb r3, [r7, #23] 8001bfa: e011 b.n 8001c20 else ret = NessLab_CheckSum_Check(&uart_buf[NessLab_Req_MsgID0],uart_buf[NessLab_DataLength] + 5 ,uart_buf[uart_buf[NessLab_Req_DataLength] + NessLab_Req_DataLength + 1]); 8001bfc: 4b22 ldr r3, [pc, #136] ; (8001c88 ) 8001bfe: 799b ldrb r3, [r3, #6] 8001c00: b2db uxtb r3, r3 8001c02: 3305 adds r3, #5 8001c04: b2d9 uxtb r1, r3 8001c06: 4b20 ldr r3, [pc, #128] ; (8001c88 ) 8001c08: 799b ldrb r3, [r3, #6] 8001c0a: b2db uxtb r3, r3 8001c0c: 3307 adds r3, #7 8001c0e: 4a1e ldr r2, [pc, #120] ; (8001c88 ) 8001c10: 5cd3 ldrb r3, [r2, r3] 8001c12: b2db uxtb r3, r3 8001c14: 461a mov r2, r3 8001c16: 4820 ldr r0, [pc, #128] ; (8001c98 ) 8001c18: f7ff fdce bl 80017b8 8001c1c: 4603 mov r3, r0 8001c1e: 75fb strb r3, [r7, #23] if(ret == true){ 8001c20: 7dfb ldrb r3, [r7, #23] 8001c22: 2b00 cmp r3, #0 8001c24: d003 beq.n 8001c2e NessLab_Operate(&uart_buf[0]); 8001c26: 4818 ldr r0, [pc, #96] ; (8001c88 ) 8001c28: f7ff f92c bl 8000e84 8001c2c: e01c b.n 8001c68 // printf("Checksum OK \r\n"); }else{ printf("Checksum Error \r\n"); 8001c2e: 481b ldr r0, [pc, #108] ; (8001c9c ) 8001c30: f004 fd96 bl 8006760 printf("uart_buf[NessLab_Req_DataLength] : %x \r\n",uart_buf[NessLab_Req_DataLength]); 8001c34: 4b14 ldr r3, [pc, #80] ; (8001c88 ) 8001c36: 799b ldrb r3, [r3, #6] 8001c38: b2db uxtb r3, r3 8001c3a: 4619 mov r1, r3 8001c3c: 4818 ldr r0, [pc, #96] ; (8001ca0 ) 8001c3e: f004 fd1b bl 8006678 printf("NessLab_Req_DataLength : %d \r\n",NessLab_Req_DataLength); 8001c42: 2106 movs r1, #6 8001c44: 4817 ldr r0, [pc, #92] ; (8001ca4 ) 8001c46: f004 fd17 bl 8006678 printf("Checksum Index : %d %x\r\n",uart_buf[NessLab_Req_DataLength] + NessLab_Req_DataLength + 1,uart_buf[uart_buf[NessLab_Req_DataLength] + NessLab_Req_DataLength + 1]); 8001c4a: 4b0f ldr r3, [pc, #60] ; (8001c88 ) 8001c4c: 799b ldrb r3, [r3, #6] 8001c4e: b2db uxtb r3, r3 8001c50: 1dd9 adds r1, r3, #7 8001c52: 4b0d ldr r3, [pc, #52] ; (8001c88 ) 8001c54: 799b ldrb r3, [r3, #6] 8001c56: b2db uxtb r3, r3 8001c58: 3307 adds r3, #7 8001c5a: 4a0b ldr r2, [pc, #44] ; (8001c88 ) 8001c5c: 5cd3 ldrb r3, [r2, r3] 8001c5e: b2db uxtb r3, r3 8001c60: 461a mov r2, r3 8001c62: 4811 ldr r0, [pc, #68] ; (8001ca8 ) 8001c64: f004 fd08 bl 8006678 } memset(uart_buf,0x00,QUEUE_BUFFER_LENGTH); 8001c68: 2280 movs r2, #128 ; 0x80 8001c6a: 2100 movs r1, #0 8001c6c: 4806 ldr r0, [pc, #24] ; (8001c88 ) 8001c6e: f004 f8ab bl 8005dc8 cnt = 0; 8001c72: 4b04 ldr r3, [pc, #16] ; (8001c84 ) 8001c74: 2200 movs r2, #0 8001c76: 601a str r2, [r3, #0] } } 8001c78: bf00 nop 8001c7a: 3718 adds r7, #24 8001c7c: 46bd mov sp, r7 8001c7e: bd80 pop {r7, pc} 8001c80: 2000061c .word 0x2000061c 8001c84: 200004e8 .word 0x200004e8 8001c88: 2000059c .word 0x2000059c 8001c8c: 08008848 .word 0x08008848 8001c90: 08008850 .word 0x08008850 8001c94: 08008858 .word 0x08008858 8001c98: 2000059e .word 0x2000059e 8001c9c: 0800885c .word 0x0800885c 8001ca0: 08008870 .word 0x08008870 8001ca4: 0800889c .word 0x0800889c 8001ca8: 080088bc .word 0x080088bc 08001cac : void Uart_Check(void){ 8001cac: b580 push {r7, lr} 8001cae: af00 add r7, sp, #0 if (MainQueue.data > 0 && UartRxTimerCnt > 100) 8001cb0: 4b06 ldr r3, [pc, #24] ; (8001ccc ) 8001cb2: 689b ldr r3, [r3, #8] 8001cb4: 2b00 cmp r3, #0 8001cb6: dd06 ble.n 8001cc6 8001cb8: 4b05 ldr r3, [pc, #20] ; (8001cd0 ) 8001cba: 681b ldr r3, [r3, #0] 8001cbc: 2b64 cmp r3, #100 ; 0x64 8001cbe: d902 bls.n 8001cc6 GetDataFromUartQueue(&hMain); 8001cc0: 4804 ldr r0, [pc, #16] ; (8001cd4 ) 8001cc2: f7ff ff45 bl 8001b50 } 8001cc6: bf00 nop 8001cc8: bd80 pop {r7, pc} 8001cca: bf00 nop 8001ccc: 2000061c .word 0x2000061c 8001cd0: 200004ec .word 0x200004ec 8001cd4: 200008d8 .word 0x200008d8 08001cd8 : void Uart1_Data_Send(uint8_t* data,uint16_t size){ 8001cd8: b580 push {r7, lr} 8001cda: b084 sub sp, #16 8001cdc: af00 add r7, sp, #0 8001cde: 6078 str r0, [r7, #4] 8001ce0: 460b mov r3, r1 8001ce2: 807b strh r3, [r7, #2] HAL_UART_Transmit_DMA(&hMain, &data[0],size); 8001ce4: 887b ldrh r3, [r7, #2] 8001ce6: 461a mov r2, r3 8001ce8: 6879 ldr r1, [r7, #4] 8001cea: 480f ldr r0, [pc, #60] ; (8001d28 ) 8001cec: f002 fcd6 bl 800469c //HAL_UART_Transmit_IT(&hTerminal, &data[0],size); // printf("data[278] : %x \r\n",data[278]); //// HAL_Delay(1); #if 1 // PYJ.2020.07.19_BEGIN -- printf("\r\n [TX] : "); 8001cf0: 480e ldr r0, [pc, #56] ; (8001d2c ) 8001cf2: f004 fcc1 bl 8006678 for(int i = 0; i< size; i++) 8001cf6: 2300 movs r3, #0 8001cf8: 60fb str r3, [r7, #12] 8001cfa: e00a b.n 8001d12 printf("%02x ",data[i]); 8001cfc: 68fb ldr r3, [r7, #12] 8001cfe: 687a ldr r2, [r7, #4] 8001d00: 4413 add r3, r2 8001d02: 781b ldrb r3, [r3, #0] 8001d04: 4619 mov r1, r3 8001d06: 480a ldr r0, [pc, #40] ; (8001d30 ) 8001d08: f004 fcb6 bl 8006678 for(int i = 0; i< size; i++) 8001d0c: 68fb ldr r3, [r7, #12] 8001d0e: 3301 adds r3, #1 8001d10: 60fb str r3, [r7, #12] 8001d12: 887b ldrh r3, [r7, #2] 8001d14: 68fa ldr r2, [r7, #12] 8001d16: 429a cmp r2, r3 8001d18: dbf0 blt.n 8001cfc // printf("};\r\n\tCOUNT : %d \r\n",size); printf("\r\n"); 8001d1a: 4806 ldr r0, [pc, #24] ; (8001d34 ) 8001d1c: f004 fd20 bl 8006760 // data[i] = 0; // } // printf("};\r\n\tCOUNT : %d \r\n",size); // printf("\r\n"); } 8001d20: bf00 nop 8001d22: 3710 adds r7, #16 8001d24: 46bd mov sp, r7 8001d26: bd80 pop {r7, pc} 8001d28: 200008d8 .word 0x200008d8 8001d2c: 080088d8 .word 0x080088d8 8001d30: 08008850 .word 0x08008850 8001d34: 08008858 .word 0x08008858 08001d38 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8001d38: b580 push {r7, lr} 8001d3a: af00 add r7, sp, #0 __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); #endif #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8001d3c: 2003 movs r0, #3 8001d3e: f000 fdd1 bl 80028e4 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 8001d42: 2000 movs r0, #0 8001d44: f003 fe74 bl 8005a30 /* Init the low level hardware */ HAL_MspInit(); 8001d48: f003 fcde bl 8005708 /* Return function status */ return HAL_OK; 8001d4c: 2300 movs r3, #0 } 8001d4e: 4618 mov r0, r3 8001d50: bd80 pop {r7, pc} ... 08001d54 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8001d54: b480 push {r7} 8001d56: af00 add r7, sp, #0 uwTick += uwTickFreq; 8001d58: 4b05 ldr r3, [pc, #20] ; (8001d70 ) 8001d5a: 781b ldrb r3, [r3, #0] 8001d5c: 461a mov r2, r3 8001d5e: 4b05 ldr r3, [pc, #20] ; (8001d74 ) 8001d60: 681b ldr r3, [r3, #0] 8001d62: 4413 add r3, r2 8001d64: 4a03 ldr r2, [pc, #12] ; (8001d74 ) 8001d66: 6013 str r3, [r2, #0] } 8001d68: bf00 nop 8001d6a: 46bd mov sp, r7 8001d6c: bc80 pop {r7} 8001d6e: 4770 bx lr 8001d70: 20000004 .word 0x20000004 8001d74: 200007b8 .word 0x200007b8 08001d78 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8001d78: b480 push {r7} 8001d7a: af00 add r7, sp, #0 return uwTick; 8001d7c: 4b02 ldr r3, [pc, #8] ; (8001d88 ) 8001d7e: 681b ldr r3, [r3, #0] } 8001d80: 4618 mov r0, r3 8001d82: 46bd mov sp, r7 8001d84: bc80 pop {r7} 8001d86: 4770 bx lr 8001d88: 200007b8 .word 0x200007b8 08001d8c : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 8001d8c: b580 push {r7, lr} 8001d8e: b084 sub sp, #16 8001d90: af00 add r7, sp, #0 8001d92: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 8001d94: f7ff fff0 bl 8001d78 8001d98: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 8001d9a: 687b ldr r3, [r7, #4] 8001d9c: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 8001d9e: 68fb ldr r3, [r7, #12] 8001da0: f1b3 3fff cmp.w r3, #4294967295 8001da4: d005 beq.n 8001db2 { wait += (uint32_t)(uwTickFreq); 8001da6: 4b09 ldr r3, [pc, #36] ; (8001dcc ) 8001da8: 781b ldrb r3, [r3, #0] 8001daa: 461a mov r2, r3 8001dac: 68fb ldr r3, [r7, #12] 8001dae: 4413 add r3, r2 8001db0: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 8001db2: bf00 nop 8001db4: f7ff ffe0 bl 8001d78 8001db8: 4602 mov r2, r0 8001dba: 68bb ldr r3, [r7, #8] 8001dbc: 1ad3 subs r3, r2, r3 8001dbe: 68fa ldr r2, [r7, #12] 8001dc0: 429a cmp r2, r3 8001dc2: d8f7 bhi.n 8001db4 { } } 8001dc4: bf00 nop 8001dc6: 3710 adds r7, #16 8001dc8: 46bd mov sp, r7 8001dca: bd80 pop {r7, pc} 8001dcc: 20000004 .word 0x20000004 08001dd0 : * of structure "ADC_InitTypeDef". * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { 8001dd0: b580 push {r7, lr} 8001dd2: b086 sub sp, #24 8001dd4: af00 add r7, sp, #0 8001dd6: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8001dd8: 2300 movs r3, #0 8001dda: 75fb strb r3, [r7, #23] uint32_t tmp_cr1 = 0U; 8001ddc: 2300 movs r3, #0 8001dde: 613b str r3, [r7, #16] uint32_t tmp_cr2 = 0U; 8001de0: 2300 movs r3, #0 8001de2: 60bb str r3, [r7, #8] uint32_t tmp_sqr1 = 0U; 8001de4: 2300 movs r3, #0 8001de6: 60fb str r3, [r7, #12] /* Check ADC handle */ if(hadc == NULL) 8001de8: 687b ldr r3, [r7, #4] 8001dea: 2b00 cmp r3, #0 8001dec: d101 bne.n 8001df2 { return HAL_ERROR; 8001dee: 2301 movs r3, #1 8001df0: e0be b.n 8001f70 assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) 8001df2: 687b ldr r3, [r7, #4] 8001df4: 689b ldr r3, [r3, #8] 8001df6: 2b00 cmp r3, #0 /* Refer to header of this file for more details on clock enabling */ /* procedure. */ /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) 8001df8: 687b ldr r3, [r7, #4] 8001dfa: 6a9b ldr r3, [r3, #40] ; 0x28 8001dfc: 2b00 cmp r3, #0 8001dfe: d109 bne.n 8001e14 { /* Initialize ADC error code */ ADC_CLEAR_ERRORCODE(hadc); 8001e00: 687b ldr r3, [r7, #4] 8001e02: 2200 movs r2, #0 8001e04: 62da str r2, [r3, #44] ; 0x2c /* Allocate lock resource and initialize it */ hadc->Lock = HAL_UNLOCKED; 8001e06: 687b ldr r3, [r7, #4] 8001e08: 2200 movs r2, #0 8001e0a: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); 8001e0e: 6878 ldr r0, [r7, #4] 8001e10: f003 fcac bl 800576c /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ /* Note: In case of ADC already enabled, precaution to not launch an */ /* unwanted conversion while modifying register CR2 by writing 1 to */ /* bit ADON. */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 8001e14: 6878 ldr r0, [r7, #4] 8001e16: f000 fb75 bl 8002504 8001e1a: 4603 mov r3, r0 8001e1c: 75fb strb r3, [r7, #23] /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && 8001e1e: 687b ldr r3, [r7, #4] 8001e20: 6a9b ldr r3, [r3, #40] ; 0x28 8001e22: f003 0310 and.w r3, r3, #16 8001e26: 2b00 cmp r3, #0 8001e28: f040 8099 bne.w 8001f5e 8001e2c: 7dfb ldrb r3, [r7, #23] 8001e2e: 2b00 cmp r3, #0 8001e30: f040 8095 bne.w 8001f5e (tmp_hal_status == HAL_OK) ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8001e34: 687b ldr r3, [r7, #4] 8001e36: 6a9b ldr r3, [r3, #40] ; 0x28 8001e38: f423 5388 bic.w r3, r3, #4352 ; 0x1100 8001e3c: f023 0302 bic.w r3, r3, #2 8001e40: f043 0202 orr.w r2, r3, #2 8001e44: 687b ldr r3, [r7, #4] 8001e46: 629a str r2, [r3, #40] ; 0x28 /* - continuous conversion mode */ /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */ /* HAL_ADC_Start_xxx functions because if set in this function, */ /* a conversion on injected group would start a conversion also on */ /* regular group after ADC enabling. */ tmp_cr2 |= (hadc->Init.DataAlign | 8001e48: 687b ldr r3, [r7, #4] 8001e4a: 685a ldr r2, [r3, #4] ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 8001e4c: 687b ldr r3, [r7, #4] 8001e4e: 69db ldr r3, [r3, #28] tmp_cr2 |= (hadc->Init.DataAlign | 8001e50: 431a orrs r2, r3 ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) ); 8001e52: 687b ldr r3, [r7, #4] 8001e54: 7b1b ldrb r3, [r3, #12] 8001e56: 005b lsls r3, r3, #1 ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 8001e58: 4313 orrs r3, r2 tmp_cr2 |= (hadc->Init.DataAlign | 8001e5a: 68ba ldr r2, [r7, #8] 8001e5c: 4313 orrs r3, r2 8001e5e: 60bb str r3, [r7, #8] /* Configuration of ADC: */ /* - scan mode */ /* - discontinuous mode disable/enable */ /* - discontinuous mode number of conversions */ tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode)); 8001e60: 687b ldr r3, [r7, #4] 8001e62: 689b ldr r3, [r3, #8] 8001e64: f5b3 7f80 cmp.w r3, #256 ; 0x100 8001e68: d003 beq.n 8001e72 8001e6a: 687b ldr r3, [r7, #4] 8001e6c: 689b ldr r3, [r3, #8] 8001e6e: 2b01 cmp r3, #1 8001e70: d102 bne.n 8001e78 8001e72: f44f 7380 mov.w r3, #256 ; 0x100 8001e76: e000 b.n 8001e7a 8001e78: 2300 movs r3, #0 8001e7a: 693a ldr r2, [r7, #16] 8001e7c: 4313 orrs r3, r2 8001e7e: 613b str r3, [r7, #16] /* Enable discontinuous mode only if continuous mode is disabled */ /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */ /* discontinuous is set anyway, but will have no effect on ADC HW. */ if (hadc->Init.DiscontinuousConvMode == ENABLE) 8001e80: 687b ldr r3, [r7, #4] 8001e82: 7d1b ldrb r3, [r3, #20] 8001e84: 2b01 cmp r3, #1 8001e86: d119 bne.n 8001ebc { if (hadc->Init.ContinuousConvMode == DISABLE) 8001e88: 687b ldr r3, [r7, #4] 8001e8a: 7b1b ldrb r3, [r3, #12] 8001e8c: 2b00 cmp r3, #0 8001e8e: d109 bne.n 8001ea4 { /* Enable the selected ADC regular discontinuous mode */ /* Set the number of channels to be converted in discontinuous mode */ SET_BIT(tmp_cr1, ADC_CR1_DISCEN | 8001e90: 687b ldr r3, [r7, #4] 8001e92: 699b ldr r3, [r3, #24] 8001e94: 3b01 subs r3, #1 8001e96: 035a lsls r2, r3, #13 8001e98: 693b ldr r3, [r7, #16] 8001e9a: 4313 orrs r3, r2 8001e9c: f443 6300 orr.w r3, r3, #2048 ; 0x800 8001ea0: 613b str r3, [r7, #16] 8001ea2: e00b b.n 8001ebc { /* ADC regular group settings continuous and sequencer discontinuous*/ /* cannot be enabled simultaneously. */ /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8001ea4: 687b ldr r3, [r7, #4] 8001ea6: 6a9b ldr r3, [r3, #40] ; 0x28 8001ea8: f043 0220 orr.w r2, r3, #32 8001eac: 687b ldr r3, [r7, #4] 8001eae: 629a str r2, [r3, #40] ; 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8001eb0: 687b ldr r3, [r7, #4] 8001eb2: 6adb ldr r3, [r3, #44] ; 0x2c 8001eb4: f043 0201 orr.w r2, r3, #1 8001eb8: 687b ldr r3, [r7, #4] 8001eba: 62da str r2, [r3, #44] ; 0x2c } } /* Update ADC configuration register CR1 with previous settings */ MODIFY_REG(hadc->Instance->CR1, 8001ebc: 687b ldr r3, [r7, #4] 8001ebe: 681b ldr r3, [r3, #0] 8001ec0: 685b ldr r3, [r3, #4] 8001ec2: f423 4169 bic.w r1, r3, #59648 ; 0xe900 8001ec6: 687b ldr r3, [r7, #4] 8001ec8: 681b ldr r3, [r3, #0] 8001eca: 693a ldr r2, [r7, #16] 8001ecc: 430a orrs r2, r1 8001ece: 605a str r2, [r3, #4] ADC_CR1_DISCEN | ADC_CR1_DISCNUM , tmp_cr1 ); /* Update ADC configuration register CR2 with previous settings */ MODIFY_REG(hadc->Instance->CR2, 8001ed0: 687b ldr r3, [r7, #4] 8001ed2: 681b ldr r3, [r3, #0] 8001ed4: 689a ldr r2, [r3, #8] 8001ed6: 4b28 ldr r3, [pc, #160] ; (8001f78 ) 8001ed8: 4013 ands r3, r2 8001eda: 687a ldr r2, [r7, #4] 8001edc: 6812 ldr r2, [r2, #0] 8001ede: 68b9 ldr r1, [r7, #8] 8001ee0: 430b orrs r3, r1 8001ee2: 6093 str r3, [r2, #8] /* Note: Scan mode is present by hardware on this device and, if */ /* disabled, discards automatically nb of conversions. Anyway, nb of */ /* conversions is forced to 0x00 for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion" */ if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE) 8001ee4: 687b ldr r3, [r7, #4] 8001ee6: 689b ldr r3, [r3, #8] 8001ee8: f5b3 7f80 cmp.w r3, #256 ; 0x100 8001eec: d003 beq.n 8001ef6 8001eee: 687b ldr r3, [r7, #4] 8001ef0: 689b ldr r3, [r3, #8] 8001ef2: 2b01 cmp r3, #1 8001ef4: d104 bne.n 8001f00 { tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion); 8001ef6: 687b ldr r3, [r7, #4] 8001ef8: 691b ldr r3, [r3, #16] 8001efa: 3b01 subs r3, #1 8001efc: 051b lsls r3, r3, #20 8001efe: 60fb str r3, [r7, #12] } MODIFY_REG(hadc->Instance->SQR1, 8001f00: 687b ldr r3, [r7, #4] 8001f02: 681b ldr r3, [r3, #0] 8001f04: 6adb ldr r3, [r3, #44] ; 0x2c 8001f06: f423 0170 bic.w r1, r3, #15728640 ; 0xf00000 8001f0a: 687b ldr r3, [r7, #4] 8001f0c: 681b ldr r3, [r3, #0] 8001f0e: 68fa ldr r2, [r7, #12] 8001f10: 430a orrs r2, r1 8001f12: 62da str r2, [r3, #44] ; 0x2c /* ensure of no potential problem of ADC core IP clocking. */ /* Check through register CR2 (excluding bits set in other functions: */ /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */ /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */ /* measurement path bit (TSVREFE). */ if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 8001f14: 687b ldr r3, [r7, #4] 8001f16: 681b ldr r3, [r3, #0] 8001f18: 689a ldr r2, [r3, #8] 8001f1a: 4b18 ldr r3, [pc, #96] ; (8001f7c ) 8001f1c: 4013 ands r3, r2 8001f1e: 68ba ldr r2, [r7, #8] 8001f20: 429a cmp r2, r3 8001f22: d10b bne.n 8001f3c ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL | ADC_CR2_TSVREFE )) == tmp_cr2) { /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 8001f24: 687b ldr r3, [r7, #4] 8001f26: 2200 movs r2, #0 8001f28: 62da str r2, [r3, #44] ; 0x2c /* Set the ADC state */ ADC_STATE_CLR_SET(hadc->State, 8001f2a: 687b ldr r3, [r7, #4] 8001f2c: 6a9b ldr r3, [r3, #40] ; 0x28 8001f2e: f023 0303 bic.w r3, r3, #3 8001f32: f043 0201 orr.w r2, r3, #1 8001f36: 687b ldr r3, [r7, #4] 8001f38: 629a str r2, [r3, #40] ; 0x28 if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 8001f3a: e018 b.n 8001f6e HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 8001f3c: 687b ldr r3, [r7, #4] 8001f3e: 6a9b ldr r3, [r3, #40] ; 0x28 8001f40: f023 0312 bic.w r3, r3, #18 8001f44: f043 0210 orr.w r2, r3, #16 8001f48: 687b ldr r3, [r7, #4] 8001f4a: 629a str r2, [r3, #40] ; 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8001f4c: 687b ldr r3, [r7, #4] 8001f4e: 6adb ldr r3, [r3, #44] ; 0x2c 8001f50: f043 0201 orr.w r2, r3, #1 8001f54: 687b ldr r3, [r7, #4] 8001f56: 62da str r2, [r3, #44] ; 0x2c tmp_hal_status = HAL_ERROR; 8001f58: 2301 movs r3, #1 8001f5a: 75fb strb r3, [r7, #23] if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 8001f5c: e007 b.n 8001f6e } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8001f5e: 687b ldr r3, [r7, #4] 8001f60: 6a9b ldr r3, [r3, #40] ; 0x28 8001f62: f043 0210 orr.w r2, r3, #16 8001f66: 687b ldr r3, [r7, #4] 8001f68: 629a str r2, [r3, #40] ; 0x28 tmp_hal_status = HAL_ERROR; 8001f6a: 2301 movs r3, #1 8001f6c: 75fb strb r3, [r7, #23] } /* Return function status */ return tmp_hal_status; 8001f6e: 7dfb ldrb r3, [r7, #23] } 8001f70: 4618 mov r0, r3 8001f72: 3718 adds r7, #24 8001f74: 46bd mov sp, r7 8001f76: bd80 pop {r7, pc} 8001f78: ffe1f7fd .word 0xffe1f7fd 8001f7c: ff1f0efe .word 0xff1f0efe 08001f80 : * @param pData: The destination Buffer address. * @param Length: The length of data to be transferred from ADC peripheral to memory. * @retval None */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) { 8001f80: b580 push {r7, lr} 8001f82: b086 sub sp, #24 8001f84: af00 add r7, sp, #0 8001f86: 60f8 str r0, [r7, #12] 8001f88: 60b9 str r1, [r7, #8] 8001f8a: 607a str r2, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8001f8c: 2300 movs r3, #0 8001f8e: 75fb strb r3, [r7, #23] /* If multimode is enabled, dedicated function multimode conversion */ /* start DMA must be used. */ if(ADC_MULTIMODE_IS_ENABLE(hadc) == RESET) { /* Process locked */ __HAL_LOCK(hadc); 8001f90: 68fb ldr r3, [r7, #12] 8001f92: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 8001f96: 2b01 cmp r3, #1 8001f98: d101 bne.n 8001f9e 8001f9a: 2302 movs r3, #2 8001f9c: e080 b.n 80020a0 8001f9e: 68fb ldr r3, [r7, #12] 8001fa0: 2201 movs r2, #1 8001fa2: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); 8001fa6: 68f8 ldr r0, [r7, #12] 8001fa8: f000 fa5a bl 8002460 8001fac: 4603 mov r3, r0 8001fae: 75fb strb r3, [r7, #23] /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) 8001fb0: 7dfb ldrb r3, [r7, #23] 8001fb2: 2b00 cmp r3, #0 8001fb4: d16f bne.n 8002096 { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, 8001fb6: 68fb ldr r3, [r7, #12] 8001fb8: 6a9b ldr r3, [r3, #40] ; 0x28 8001fba: f423 6370 bic.w r3, r3, #3840 ; 0xf00 8001fbe: f023 0301 bic.w r3, r3, #1 8001fc2: f443 7280 orr.w r2, r3, #256 ; 0x100 8001fc6: 68fb ldr r3, [r7, #12] 8001fc8: 629a str r2, [r3, #40] ; 0x28 /* for all cases of multimode: independent mode, multimode ADC master */ /* or multimode ADC slave (for devices with several ADCs): */ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) { /* Set ADC state (ADC independent or master) */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 8001fca: 68fb ldr r3, [r7, #12] 8001fcc: 6a9b ldr r3, [r3, #40] ; 0x28 8001fce: f423 1280 bic.w r2, r3, #1048576 ; 0x100000 8001fd2: 68fb ldr r3, [r7, #12] 8001fd4: 629a str r2, [r3, #40] ; 0x28 /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) 8001fd6: 68fb ldr r3, [r7, #12] 8001fd8: 681b ldr r3, [r3, #0] 8001fda: 685b ldr r3, [r3, #4] 8001fdc: f403 6380 and.w r3, r3, #1024 ; 0x400 8001fe0: 2b00 cmp r3, #0 8001fe2: d007 beq.n 8001ff4 { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 8001fe4: 68fb ldr r3, [r7, #12] 8001fe6: 6a9b ldr r3, [r3, #40] ; 0x28 8001fe8: f423 5340 bic.w r3, r3, #12288 ; 0x3000 8001fec: f443 5280 orr.w r2, r3, #4096 ; 0x1000 8001ff0: 68fb ldr r3, [r7, #12] 8001ff2: 629a str r2, [r3, #40] ; 0x28 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } } /* State machine update: Check if an injected conversion is ongoing */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 8001ff4: 68fb ldr r3, [r7, #12] 8001ff6: 6a9b ldr r3, [r3, #40] ; 0x28 8001ff8: f403 5380 and.w r3, r3, #4096 ; 0x1000 8001ffc: 2b00 cmp r3, #0 8001ffe: d006 beq.n 800200e { /* Reset ADC error code fields related to conversions on group regular */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); 8002000: 68fb ldr r3, [r7, #12] 8002002: 6adb ldr r3, [r3, #44] ; 0x2c 8002004: f023 0206 bic.w r2, r3, #6 8002008: 68fb ldr r3, [r7, #12] 800200a: 62da str r2, [r3, #44] ; 0x2c 800200c: e002 b.n 8002014 } else { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); 800200e: 68fb ldr r3, [r7, #12] 8002010: 2200 movs r2, #0 8002012: 62da str r2, [r3, #44] ; 0x2c } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); 8002014: 68fb ldr r3, [r7, #12] 8002016: 2200 movs r2, #0 8002018: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; 800201c: 68fb ldr r3, [r7, #12] 800201e: 6a1b ldr r3, [r3, #32] 8002020: 4a21 ldr r2, [pc, #132] ; (80020a8 ) 8002022: 629a str r2, [r3, #40] ; 0x28 /* Set the DMA half transfer complete callback */ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; 8002024: 68fb ldr r3, [r7, #12] 8002026: 6a1b ldr r3, [r3, #32] 8002028: 4a20 ldr r2, [pc, #128] ; (80020ac ) 800202a: 62da str r2, [r3, #44] ; 0x2c /* Set the DMA error callback */ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; 800202c: 68fb ldr r3, [r7, #12] 800202e: 6a1b ldr r3, [r3, #32] 8002030: 4a1f ldr r2, [pc, #124] ; (80020b0 ) 8002032: 631a str r2, [r3, #48] ; 0x30 /* start (in case of SW start): */ /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC */ /* operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); 8002034: 68fb ldr r3, [r7, #12] 8002036: 681b ldr r3, [r3, #0] 8002038: f06f 0202 mvn.w r2, #2 800203c: 601a str r2, [r3, #0] /* Enable ADC DMA mode */ SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA); 800203e: 68fb ldr r3, [r7, #12] 8002040: 681b ldr r3, [r3, #0] 8002042: 689a ldr r2, [r3, #8] 8002044: 68fb ldr r3, [r7, #12] 8002046: 681b ldr r3, [r3, #0] 8002048: f442 7280 orr.w r2, r2, #256 ; 0x100 800204c: 609a str r2, [r3, #8] /* Start the DMA channel */ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); 800204e: 68fb ldr r3, [r7, #12] 8002050: 6a18 ldr r0, [r3, #32] 8002052: 68fb ldr r3, [r7, #12] 8002054: 681b ldr r3, [r3, #0] 8002056: 334c adds r3, #76 ; 0x4c 8002058: 4619 mov r1, r3 800205a: 68ba ldr r2, [r7, #8] 800205c: 687b ldr r3, [r7, #4] 800205e: f000 fcd1 bl 8002a04 /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ if (ADC_IS_SOFTWARE_START_REGULAR(hadc)) 8002062: 68fb ldr r3, [r7, #12] 8002064: 681b ldr r3, [r3, #0] 8002066: 689b ldr r3, [r3, #8] 8002068: f403 2360 and.w r3, r3, #917504 ; 0xe0000 800206c: f5b3 2f60 cmp.w r3, #917504 ; 0xe0000 8002070: d108 bne.n 8002084 { /* Start ADC conversion on regular group with SW start */ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); 8002072: 68fb ldr r3, [r7, #12] 8002074: 681b ldr r3, [r3, #0] 8002076: 689a ldr r2, [r3, #8] 8002078: 68fb ldr r3, [r7, #12] 800207a: 681b ldr r3, [r3, #0] 800207c: f442 02a0 orr.w r2, r2, #5242880 ; 0x500000 8002080: 609a str r2, [r3, #8] 8002082: e00c b.n 800209e } else { /* Start ADC conversion on regular group with external trigger */ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); 8002084: 68fb ldr r3, [r7, #12] 8002086: 681b ldr r3, [r3, #0] 8002088: 689a ldr r2, [r3, #8] 800208a: 68fb ldr r3, [r7, #12] 800208c: 681b ldr r3, [r3, #0] 800208e: f442 1280 orr.w r2, r2, #1048576 ; 0x100000 8002092: 609a str r2, [r3, #8] 8002094: e003 b.n 800209e } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); 8002096: 68fb ldr r3, [r7, #12] 8002098: 2200 movs r2, #0 800209a: f883 2024 strb.w r2, [r3, #36] ; 0x24 { tmp_hal_status = HAL_ERROR; } /* Return function status */ return tmp_hal_status; 800209e: 7dfb ldrb r3, [r7, #23] } 80020a0: 4618 mov r0, r3 80020a2: 3718 adds r7, #24 80020a4: 46bd mov sp, r7 80020a6: bd80 pop {r7, pc} 80020a8: 08002579 .word 0x08002579 80020ac: 080025f5 .word 0x080025f5 80020b0: 08002611 .word 0x08002611 080020b4 : * @brief Handles ADC interrupt request * @param hadc: ADC handle * @retval None */ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) { 80020b4: b580 push {r7, lr} 80020b6: b082 sub sp, #8 80020b8: af00 add r7, sp, #0 80020ba: 6078 str r0, [r7, #4] assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); /* ========== Check End of Conversion flag for regular group ========== */ if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) 80020bc: 687b ldr r3, [r7, #4] 80020be: 681b ldr r3, [r3, #0] 80020c0: 685b ldr r3, [r3, #4] 80020c2: f003 0320 and.w r3, r3, #32 80020c6: 2b20 cmp r3, #32 80020c8: d140 bne.n 800214c { if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) ) 80020ca: 687b ldr r3, [r7, #4] 80020cc: 681b ldr r3, [r3, #0] 80020ce: 681b ldr r3, [r3, #0] 80020d0: f003 0302 and.w r3, r3, #2 80020d4: 2b02 cmp r3, #2 80020d6: d139 bne.n 800214c { /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) 80020d8: 687b ldr r3, [r7, #4] 80020da: 6a9b ldr r3, [r3, #40] ; 0x28 80020dc: f003 0310 and.w r3, r3, #16 80020e0: 2b00 cmp r3, #0 80020e2: d105 bne.n 80020f0 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 80020e4: 687b ldr r3, [r7, #4] 80020e6: 6a9b ldr r3, [r3, #40] ; 0x28 80020e8: f443 7200 orr.w r2, r3, #512 ; 0x200 80020ec: 687b ldr r3, [r7, #4] 80020ee: 629a str r2, [r3, #40] ; 0x28 /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 80020f0: 687b ldr r3, [r7, #4] 80020f2: 681b ldr r3, [r3, #0] 80020f4: 689b ldr r3, [r3, #8] 80020f6: f403 2360 and.w r3, r3, #917504 ; 0xe0000 80020fa: f5b3 2f60 cmp.w r3, #917504 ; 0xe0000 80020fe: d11d bne.n 800213c (hadc->Init.ContinuousConvMode == DISABLE) ) 8002100: 687b ldr r3, [r7, #4] 8002102: 7b1b ldrb r3, [r3, #12] if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 8002104: 2b00 cmp r3, #0 8002106: d119 bne.n 800213c { /* Disable ADC end of conversion interrupt on group regular */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); 8002108: 687b ldr r3, [r7, #4] 800210a: 681b ldr r3, [r3, #0] 800210c: 685a ldr r2, [r3, #4] 800210e: 687b ldr r3, [r7, #4] 8002110: 681b ldr r3, [r3, #0] 8002112: f022 0220 bic.w r2, r2, #32 8002116: 605a str r2, [r3, #4] /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 8002118: 687b ldr r3, [r7, #4] 800211a: 6a9b ldr r3, [r3, #40] ; 0x28 800211c: f423 7280 bic.w r2, r3, #256 ; 0x100 8002120: 687b ldr r3, [r7, #4] 8002122: 629a str r2, [r3, #40] ; 0x28 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 8002124: 687b ldr r3, [r7, #4] 8002126: 6a9b ldr r3, [r3, #40] ; 0x28 8002128: f403 5380 and.w r3, r3, #4096 ; 0x1000 800212c: 2b00 cmp r3, #0 800212e: d105 bne.n 800213c { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 8002130: 687b ldr r3, [r7, #4] 8002132: 6a9b ldr r3, [r3, #40] ; 0x28 8002134: f043 0201 orr.w r2, r3, #1 8002138: 687b ldr r3, [r7, #4] 800213a: 629a str r2, [r3, #40] ; 0x28 /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); 800213c: 6878 ldr r0, [r7, #4] 800213e: f7ff fab1 bl 80016a4 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear regular group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); 8002142: 687b ldr r3, [r7, #4] 8002144: 681b ldr r3, [r3, #0] 8002146: f06f 0212 mvn.w r2, #18 800214a: 601a str r2, [r3, #0] } } /* ========== Check End of Conversion flag for injected group ========== */ if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC)) 800214c: 687b ldr r3, [r7, #4] 800214e: 681b ldr r3, [r3, #0] 8002150: 685b ldr r3, [r3, #4] 8002152: f003 0380 and.w r3, r3, #128 ; 0x80 8002156: 2b80 cmp r3, #128 ; 0x80 8002158: d14f bne.n 80021fa { if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC)) 800215a: 687b ldr r3, [r7, #4] 800215c: 681b ldr r3, [r3, #0] 800215e: 681b ldr r3, [r3, #0] 8002160: f003 0304 and.w r3, r3, #4 8002164: 2b04 cmp r3, #4 8002166: d148 bne.n 80021fa { /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) 8002168: 687b ldr r3, [r7, #4] 800216a: 6a9b ldr r3, [r3, #40] ; 0x28 800216c: f003 0310 and.w r3, r3, #16 8002170: 2b00 cmp r3, #0 8002172: d105 bne.n 8002180 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); 8002174: 687b ldr r3, [r7, #4] 8002176: 6a9b ldr r3, [r3, #40] ; 0x28 8002178: f443 5200 orr.w r2, r3, #8192 ; 0x2000 800217c: 687b ldr r3, [r7, #4] 800217e: 629a str r2, [r3, #40] ; 0x28 /* conversion from group regular (same conditions as group regular */ /* interruption disabling above). */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_INJECTED(hadc) || 8002180: 687b ldr r3, [r7, #4] 8002182: 681b ldr r3, [r3, #0] 8002184: 689b ldr r3, [r3, #8] 8002186: f403 43e0 and.w r3, r3, #28672 ; 0x7000 800218a: f5b3 4fe0 cmp.w r3, #28672 ; 0x7000 800218e: d012 beq.n 80021b6 (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && 8002190: 687b ldr r3, [r7, #4] 8002192: 681b ldr r3, [r3, #0] 8002194: 685b ldr r3, [r3, #4] 8002196: f403 6380 and.w r3, r3, #1024 ; 0x400 if(ADC_IS_SOFTWARE_START_INJECTED(hadc) || 800219a: 2b00 cmp r3, #0 800219c: d125 bne.n 80021ea (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800219e: 687b ldr r3, [r7, #4] 80021a0: 681b ldr r3, [r3, #0] 80021a2: 689b ldr r3, [r3, #8] 80021a4: f403 2360 and.w r3, r3, #917504 ; 0xe0000 (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && 80021a8: f5b3 2f60 cmp.w r3, #917504 ; 0xe0000 80021ac: d11d bne.n 80021ea (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) 80021ae: 687b ldr r3, [r7, #4] 80021b0: 7b1b ldrb r3, [r3, #12] (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 80021b2: 2b00 cmp r3, #0 80021b4: d119 bne.n 80021ea { /* Disable ADC end of conversion interrupt on group injected */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); 80021b6: 687b ldr r3, [r7, #4] 80021b8: 681b ldr r3, [r3, #0] 80021ba: 685a ldr r2, [r3, #4] 80021bc: 687b ldr r3, [r7, #4] 80021be: 681b ldr r3, [r3, #0] 80021c0: f022 0280 bic.w r2, r2, #128 ; 0x80 80021c4: 605a str r2, [r3, #4] /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); 80021c6: 687b ldr r3, [r7, #4] 80021c8: 6a9b ldr r3, [r3, #40] ; 0x28 80021ca: f423 5280 bic.w r2, r3, #4096 ; 0x1000 80021ce: 687b ldr r3, [r7, #4] 80021d0: 629a str r2, [r3, #40] ; 0x28 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) 80021d2: 687b ldr r3, [r7, #4] 80021d4: 6a9b ldr r3, [r3, #40] ; 0x28 80021d6: f403 7380 and.w r3, r3, #256 ; 0x100 80021da: 2b00 cmp r3, #0 80021dc: d105 bne.n 80021ea { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 80021de: 687b ldr r3, [r7, #4] 80021e0: 6a9b ldr r3, [r3, #40] ; 0x28 80021e2: f043 0201 orr.w r2, r3, #1 80021e6: 687b ldr r3, [r7, #4] 80021e8: 629a str r2, [r3, #40] ; 0x28 /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->InjectedConvCpltCallback(hadc); #else HAL_ADCEx_InjectedConvCpltCallback(hadc); 80021ea: 6878 ldr r0, [r7, #4] 80021ec: f000 fac6 bl 800277c #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear injected group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC)); 80021f0: 687b ldr r3, [r7, #4] 80021f2: 681b ldr r3, [r3, #0] 80021f4: f06f 020c mvn.w r2, #12 80021f8: 601a str r2, [r3, #0] } } /* ========== Check Analog watchdog flags ========== */ if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD)) 80021fa: 687b ldr r3, [r7, #4] 80021fc: 681b ldr r3, [r3, #0] 80021fe: 685b ldr r3, [r3, #4] 8002200: f003 0340 and.w r3, r3, #64 ; 0x40 8002204: 2b40 cmp r3, #64 ; 0x40 8002206: d114 bne.n 8002232 { if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD)) 8002208: 687b ldr r3, [r7, #4] 800220a: 681b ldr r3, [r3, #0] 800220c: 681b ldr r3, [r3, #0] 800220e: f003 0301 and.w r3, r3, #1 8002212: 2b01 cmp r3, #1 8002214: d10d bne.n 8002232 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); 8002216: 687b ldr r3, [r7, #4] 8002218: 6a9b ldr r3, [r3, #40] ; 0x28 800221a: f443 3280 orr.w r2, r3, #65536 ; 0x10000 800221e: 687b ldr r3, [r7, #4] 8002220: 629a str r2, [r3, #40] ; 0x28 /* Level out of window callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->LevelOutOfWindowCallback(hadc); #else HAL_ADC_LevelOutOfWindowCallback(hadc); 8002222: 6878 ldr r0, [r7, #4] 8002224: f000 f812 bl 800224c #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear the ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); 8002228: 687b ldr r3, [r7, #4] 800222a: 681b ldr r3, [r3, #0] 800222c: f06f 0201 mvn.w r2, #1 8002230: 601a str r2, [r3, #0] } } } 8002232: bf00 nop 8002234: 3708 adds r7, #8 8002236: 46bd mov sp, r7 8002238: bd80 pop {r7, pc} 0800223a : * @brief Conversion DMA half-transfer callback in non blocking mode * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) { 800223a: b480 push {r7} 800223c: b083 sub sp, #12 800223e: af00 add r7, sp, #0 8002240: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. */ } 8002242: bf00 nop 8002244: 370c adds r7, #12 8002246: 46bd mov sp, r7 8002248: bc80 pop {r7} 800224a: 4770 bx lr 0800224c : * @brief Analog watchdog callback in non blocking mode. * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) { 800224c: b480 push {r7} 800224e: b083 sub sp, #12 8002250: af00 add r7, sp, #0 8002252: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file. */ } 8002254: bf00 nop 8002256: 370c adds r7, #12 8002258: 46bd mov sp, r7 800225a: bc80 pop {r7} 800225c: 4770 bx lr 0800225e : * (ADC conversion with interruption or transfer by DMA) * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) { 800225e: b480 push {r7} 8002260: b083 sub sp, #12 8002262: af00 add r7, sp, #0 8002264: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ErrorCallback must be implemented in the user file. */ } 8002266: bf00 nop 8002268: 370c adds r7, #12 800226a: 46bd mov sp, r7 800226c: bc80 pop {r7} 800226e: 4770 bx lr 08002270 : * @param hadc: ADC handle * @param sConfig: Structure of ADC channel for regular group. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { 8002270: b480 push {r7} 8002272: b085 sub sp, #20 8002274: af00 add r7, sp, #0 8002276: 6078 str r0, [r7, #4] 8002278: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800227a: 2300 movs r3, #0 800227c: 73fb strb r3, [r7, #15] __IO uint32_t wait_loop_index = 0U; 800227e: 2300 movs r3, #0 8002280: 60bb str r3, [r7, #8] assert_param(IS_ADC_CHANNEL(sConfig->Channel)); assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); /* Process locked */ __HAL_LOCK(hadc); 8002282: 687b ldr r3, [r7, #4] 8002284: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 8002288: 2b01 cmp r3, #1 800228a: d101 bne.n 8002290 800228c: 2302 movs r3, #2 800228e: e0dc b.n 800244a 8002290: 687b ldr r3, [r7, #4] 8002292: 2201 movs r2, #1 8002294: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Regular sequence configuration */ /* For Rank 1 to 6 */ if (sConfig->Rank < 7U) 8002298: 683b ldr r3, [r7, #0] 800229a: 685b ldr r3, [r3, #4] 800229c: 2b06 cmp r3, #6 800229e: d81c bhi.n 80022da { MODIFY_REG(hadc->Instance->SQR3 , 80022a0: 687b ldr r3, [r7, #4] 80022a2: 681b ldr r3, [r3, #0] 80022a4: 6b59 ldr r1, [r3, #52] ; 0x34 80022a6: 683b ldr r3, [r7, #0] 80022a8: 685a ldr r2, [r3, #4] 80022aa: 4613 mov r3, r2 80022ac: 009b lsls r3, r3, #2 80022ae: 4413 add r3, r2 80022b0: 3b05 subs r3, #5 80022b2: 221f movs r2, #31 80022b4: fa02 f303 lsl.w r3, r2, r3 80022b8: 43db mvns r3, r3 80022ba: 4019 ands r1, r3 80022bc: 683b ldr r3, [r7, #0] 80022be: 6818 ldr r0, [r3, #0] 80022c0: 683b ldr r3, [r7, #0] 80022c2: 685a ldr r2, [r3, #4] 80022c4: 4613 mov r3, r2 80022c6: 009b lsls r3, r3, #2 80022c8: 4413 add r3, r2 80022ca: 3b05 subs r3, #5 80022cc: fa00 f203 lsl.w r2, r0, r3 80022d0: 687b ldr r3, [r7, #4] 80022d2: 681b ldr r3, [r3, #0] 80022d4: 430a orrs r2, r1 80022d6: 635a str r2, [r3, #52] ; 0x34 80022d8: e03c b.n 8002354 ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) , ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 7 to 12 */ else if (sConfig->Rank < 13U) 80022da: 683b ldr r3, [r7, #0] 80022dc: 685b ldr r3, [r3, #4] 80022de: 2b0c cmp r3, #12 80022e0: d81c bhi.n 800231c { MODIFY_REG(hadc->Instance->SQR2 , 80022e2: 687b ldr r3, [r7, #4] 80022e4: 681b ldr r3, [r3, #0] 80022e6: 6b19 ldr r1, [r3, #48] ; 0x30 80022e8: 683b ldr r3, [r7, #0] 80022ea: 685a ldr r2, [r3, #4] 80022ec: 4613 mov r3, r2 80022ee: 009b lsls r3, r3, #2 80022f0: 4413 add r3, r2 80022f2: 3b23 subs r3, #35 ; 0x23 80022f4: 221f movs r2, #31 80022f6: fa02 f303 lsl.w r3, r2, r3 80022fa: 43db mvns r3, r3 80022fc: 4019 ands r1, r3 80022fe: 683b ldr r3, [r7, #0] 8002300: 6818 ldr r0, [r3, #0] 8002302: 683b ldr r3, [r7, #0] 8002304: 685a ldr r2, [r3, #4] 8002306: 4613 mov r3, r2 8002308: 009b lsls r3, r3, #2 800230a: 4413 add r3, r2 800230c: 3b23 subs r3, #35 ; 0x23 800230e: fa00 f203 lsl.w r2, r0, r3 8002312: 687b ldr r3, [r7, #4] 8002314: 681b ldr r3, [r3, #0] 8002316: 430a orrs r2, r1 8002318: 631a str r2, [r3, #48] ; 0x30 800231a: e01b b.n 8002354 ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 13 to 16 */ else { MODIFY_REG(hadc->Instance->SQR1 , 800231c: 687b ldr r3, [r7, #4] 800231e: 681b ldr r3, [r3, #0] 8002320: 6ad9 ldr r1, [r3, #44] ; 0x2c 8002322: 683b ldr r3, [r7, #0] 8002324: 685a ldr r2, [r3, #4] 8002326: 4613 mov r3, r2 8002328: 009b lsls r3, r3, #2 800232a: 4413 add r3, r2 800232c: 3b41 subs r3, #65 ; 0x41 800232e: 221f movs r2, #31 8002330: fa02 f303 lsl.w r3, r2, r3 8002334: 43db mvns r3, r3 8002336: 4019 ands r1, r3 8002338: 683b ldr r3, [r7, #0] 800233a: 6818 ldr r0, [r3, #0] 800233c: 683b ldr r3, [r7, #0] 800233e: 685a ldr r2, [r3, #4] 8002340: 4613 mov r3, r2 8002342: 009b lsls r3, r3, #2 8002344: 4413 add r3, r2 8002346: 3b41 subs r3, #65 ; 0x41 8002348: fa00 f203 lsl.w r2, r0, r3 800234c: 687b ldr r3, [r7, #4] 800234e: 681b ldr r3, [r3, #0] 8002350: 430a orrs r2, r1 8002352: 62da str r2, [r3, #44] ; 0x2c } /* Channel sampling time configuration */ /* For channels 10 to 17 */ if (sConfig->Channel >= ADC_CHANNEL_10) 8002354: 683b ldr r3, [r7, #0] 8002356: 681b ldr r3, [r3, #0] 8002358: 2b09 cmp r3, #9 800235a: d91c bls.n 8002396 { MODIFY_REG(hadc->Instance->SMPR1 , 800235c: 687b ldr r3, [r7, #4] 800235e: 681b ldr r3, [r3, #0] 8002360: 68d9 ldr r1, [r3, #12] 8002362: 683b ldr r3, [r7, #0] 8002364: 681a ldr r2, [r3, #0] 8002366: 4613 mov r3, r2 8002368: 005b lsls r3, r3, #1 800236a: 4413 add r3, r2 800236c: 3b1e subs r3, #30 800236e: 2207 movs r2, #7 8002370: fa02 f303 lsl.w r3, r2, r3 8002374: 43db mvns r3, r3 8002376: 4019 ands r1, r3 8002378: 683b ldr r3, [r7, #0] 800237a: 6898 ldr r0, [r3, #8] 800237c: 683b ldr r3, [r7, #0] 800237e: 681a ldr r2, [r3, #0] 8002380: 4613 mov r3, r2 8002382: 005b lsls r3, r3, #1 8002384: 4413 add r3, r2 8002386: 3b1e subs r3, #30 8002388: fa00 f203 lsl.w r2, r0, r3 800238c: 687b ldr r3, [r7, #4] 800238e: 681b ldr r3, [r3, #0] 8002390: 430a orrs r2, r1 8002392: 60da str r2, [r3, #12] 8002394: e019 b.n 80023ca ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) , ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) ); } else /* For channels 0 to 9 */ { MODIFY_REG(hadc->Instance->SMPR2 , 8002396: 687b ldr r3, [r7, #4] 8002398: 681b ldr r3, [r3, #0] 800239a: 6919 ldr r1, [r3, #16] 800239c: 683b ldr r3, [r7, #0] 800239e: 681a ldr r2, [r3, #0] 80023a0: 4613 mov r3, r2 80023a2: 005b lsls r3, r3, #1 80023a4: 4413 add r3, r2 80023a6: 2207 movs r2, #7 80023a8: fa02 f303 lsl.w r3, r2, r3 80023ac: 43db mvns r3, r3 80023ae: 4019 ands r1, r3 80023b0: 683b ldr r3, [r7, #0] 80023b2: 6898 ldr r0, [r3, #8] 80023b4: 683b ldr r3, [r7, #0] 80023b6: 681a ldr r2, [r3, #0] 80023b8: 4613 mov r3, r2 80023ba: 005b lsls r3, r3, #1 80023bc: 4413 add r3, r2 80023be: fa00 f203 lsl.w r2, r0, r3 80023c2: 687b ldr r3, [r7, #4] 80023c4: 681b ldr r3, [r3, #0] 80023c6: 430a orrs r2, r1 80023c8: 611a str r2, [r3, #16] ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); } /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ /* and VREFINT measurement path. */ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 80023ca: 683b ldr r3, [r7, #0] 80023cc: 681b ldr r3, [r3, #0] 80023ce: 2b10 cmp r3, #16 80023d0: d003 beq.n 80023da (sConfig->Channel == ADC_CHANNEL_VREFINT) ) 80023d2: 683b ldr r3, [r7, #0] 80023d4: 681b ldr r3, [r3, #0] if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 80023d6: 2b11 cmp r3, #17 80023d8: d132 bne.n 8002440 { /* For STM32F1 devices with several ADC: Only ADC1 can access internal */ /* measurement channels (VrefInt/TempSensor). If these channels are */ /* intended to be set on other ADC instances, an error is reported. */ if (hadc->Instance == ADC1) 80023da: 687b ldr r3, [r7, #4] 80023dc: 681b ldr r3, [r3, #0] 80023de: 4a1d ldr r2, [pc, #116] ; (8002454 ) 80023e0: 4293 cmp r3, r2 80023e2: d125 bne.n 8002430 { if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET) 80023e4: 687b ldr r3, [r7, #4] 80023e6: 681b ldr r3, [r3, #0] 80023e8: 689b ldr r3, [r3, #8] 80023ea: f403 0300 and.w r3, r3, #8388608 ; 0x800000 80023ee: 2b00 cmp r3, #0 80023f0: d126 bne.n 8002440 { SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); 80023f2: 687b ldr r3, [r7, #4] 80023f4: 681b ldr r3, [r3, #0] 80023f6: 689a ldr r2, [r3, #8] 80023f8: 687b ldr r3, [r7, #4] 80023fa: 681b ldr r3, [r3, #0] 80023fc: f442 0200 orr.w r2, r2, #8388608 ; 0x800000 8002400: 609a str r2, [r3, #8] if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)) 8002402: 683b ldr r3, [r7, #0] 8002404: 681b ldr r3, [r3, #0] 8002406: 2b10 cmp r3, #16 8002408: d11a bne.n 8002440 { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); 800240a: 4b13 ldr r3, [pc, #76] ; (8002458 ) 800240c: 681b ldr r3, [r3, #0] 800240e: 4a13 ldr r2, [pc, #76] ; (800245c ) 8002410: fba2 2303 umull r2, r3, r2, r3 8002414: 0c9a lsrs r2, r3, #18 8002416: 4613 mov r3, r2 8002418: 009b lsls r3, r3, #2 800241a: 4413 add r3, r2 800241c: 005b lsls r3, r3, #1 800241e: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 8002420: e002 b.n 8002428 { wait_loop_index--; 8002422: 68bb ldr r3, [r7, #8] 8002424: 3b01 subs r3, #1 8002426: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 8002428: 68bb ldr r3, [r7, #8] 800242a: 2b00 cmp r3, #0 800242c: d1f9 bne.n 8002422 800242e: e007 b.n 8002440 } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8002430: 687b ldr r3, [r7, #4] 8002432: 6a9b ldr r3, [r3, #40] ; 0x28 8002434: f043 0220 orr.w r2, r3, #32 8002438: 687b ldr r3, [r7, #4] 800243a: 629a str r2, [r3, #40] ; 0x28 tmp_hal_status = HAL_ERROR; 800243c: 2301 movs r3, #1 800243e: 73fb strb r3, [r7, #15] } } /* Process unlocked */ __HAL_UNLOCK(hadc); 8002440: 687b ldr r3, [r7, #4] 8002442: 2200 movs r2, #0 8002444: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Return function status */ return tmp_hal_status; 8002448: 7bfb ldrb r3, [r7, #15] } 800244a: 4618 mov r0, r3 800244c: 3714 adds r7, #20 800244e: 46bd mov sp, r7 8002450: bc80 pop {r7} 8002452: 4770 bx lr 8002454: 40012400 .word 0x40012400 8002458: 20000008 .word 0x20000008 800245c: 431bde83 .word 0x431bde83 08002460 : * and voltage regulator must be enabled (done into HAL_ADC_Init()). * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) { 8002460: b580 push {r7, lr} 8002462: b084 sub sp, #16 8002464: af00 add r7, sp, #0 8002466: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8002468: 2300 movs r3, #0 800246a: 60fb str r3, [r7, #12] __IO uint32_t wait_loop_index = 0U; 800246c: 2300 movs r3, #0 800246e: 60bb str r3, [r7, #8] /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ if (ADC_IS_ENABLE(hadc) == RESET) 8002470: 687b ldr r3, [r7, #4] 8002472: 681b ldr r3, [r3, #0] 8002474: 689b ldr r3, [r3, #8] 8002476: f003 0301 and.w r3, r3, #1 800247a: 2b01 cmp r3, #1 800247c: d039 beq.n 80024f2 { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); 800247e: 687b ldr r3, [r7, #4] 8002480: 681b ldr r3, [r3, #0] 8002482: 689a ldr r2, [r3, #8] 8002484: 687b ldr r3, [r7, #4] 8002486: 681b ldr r3, [r3, #0] 8002488: f042 0201 orr.w r2, r2, #1 800248c: 609a str r2, [r3, #8] /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); 800248e: 4b1b ldr r3, [pc, #108] ; (80024fc ) 8002490: 681b ldr r3, [r3, #0] 8002492: 4a1b ldr r2, [pc, #108] ; (8002500 ) 8002494: fba2 2303 umull r2, r3, r2, r3 8002498: 0c9b lsrs r3, r3, #18 800249a: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 800249c: e002 b.n 80024a4 { wait_loop_index--; 800249e: 68bb ldr r3, [r7, #8] 80024a0: 3b01 subs r3, #1 80024a2: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 80024a4: 68bb ldr r3, [r7, #8] 80024a6: 2b00 cmp r3, #0 80024a8: d1f9 bne.n 800249e } /* Get tick count */ tickstart = HAL_GetTick(); 80024aa: f7ff fc65 bl 8001d78 80024ae: 60f8 str r0, [r7, #12] /* Wait for ADC effectively enabled */ while(ADC_IS_ENABLE(hadc) == RESET) 80024b0: e018 b.n 80024e4 { if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) 80024b2: f7ff fc61 bl 8001d78 80024b6: 4602 mov r2, r0 80024b8: 68fb ldr r3, [r7, #12] 80024ba: 1ad3 subs r3, r2, r3 80024bc: 2b02 cmp r3, #2 80024be: d911 bls.n 80024e4 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 80024c0: 687b ldr r3, [r7, #4] 80024c2: 6a9b ldr r3, [r3, #40] ; 0x28 80024c4: f043 0210 orr.w r2, r3, #16 80024c8: 687b ldr r3, [r7, #4] 80024ca: 629a str r2, [r3, #40] ; 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 80024cc: 687b ldr r3, [r7, #4] 80024ce: 6adb ldr r3, [r3, #44] ; 0x2c 80024d0: f043 0201 orr.w r2, r3, #1 80024d4: 687b ldr r3, [r7, #4] 80024d6: 62da str r2, [r3, #44] ; 0x2c /* Process unlocked */ __HAL_UNLOCK(hadc); 80024d8: 687b ldr r3, [r7, #4] 80024da: 2200 movs r2, #0 80024dc: f883 2024 strb.w r2, [r3, #36] ; 0x24 return HAL_ERROR; 80024e0: 2301 movs r3, #1 80024e2: e007 b.n 80024f4 while(ADC_IS_ENABLE(hadc) == RESET) 80024e4: 687b ldr r3, [r7, #4] 80024e6: 681b ldr r3, [r3, #0] 80024e8: 689b ldr r3, [r3, #8] 80024ea: f003 0301 and.w r3, r3, #1 80024ee: 2b01 cmp r3, #1 80024f0: d1df bne.n 80024b2 } } } /* Return HAL status */ return HAL_OK; 80024f2: 2300 movs r3, #0 } 80024f4: 4618 mov r0, r3 80024f6: 3710 adds r7, #16 80024f8: 46bd mov sp, r7 80024fa: bd80 pop {r7, pc} 80024fc: 20000008 .word 0x20000008 8002500: 431bde83 .word 0x431bde83 08002504 : * stopped to disable the ADC. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc) { 8002504: b580 push {r7, lr} 8002506: b084 sub sp, #16 8002508: af00 add r7, sp, #0 800250a: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 800250c: 2300 movs r3, #0 800250e: 60fb str r3, [r7, #12] /* Verification if ADC is not already disabled */ if (ADC_IS_ENABLE(hadc) != RESET) 8002510: 687b ldr r3, [r7, #4] 8002512: 681b ldr r3, [r3, #0] 8002514: 689b ldr r3, [r3, #8] 8002516: f003 0301 and.w r3, r3, #1 800251a: 2b01 cmp r3, #1 800251c: d127 bne.n 800256e { /* Disable the ADC peripheral */ __HAL_ADC_DISABLE(hadc); 800251e: 687b ldr r3, [r7, #4] 8002520: 681b ldr r3, [r3, #0] 8002522: 689a ldr r2, [r3, #8] 8002524: 687b ldr r3, [r7, #4] 8002526: 681b ldr r3, [r3, #0] 8002528: f022 0201 bic.w r2, r2, #1 800252c: 609a str r2, [r3, #8] /* Get tick count */ tickstart = HAL_GetTick(); 800252e: f7ff fc23 bl 8001d78 8002532: 60f8 str r0, [r7, #12] /* Wait for ADC effectively disabled */ while(ADC_IS_ENABLE(hadc) != RESET) 8002534: e014 b.n 8002560 { if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 8002536: f7ff fc1f bl 8001d78 800253a: 4602 mov r2, r0 800253c: 68fb ldr r3, [r7, #12] 800253e: 1ad3 subs r3, r2, r3 8002540: 2b02 cmp r3, #2 8002542: d90d bls.n 8002560 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8002544: 687b ldr r3, [r7, #4] 8002546: 6a9b ldr r3, [r3, #40] ; 0x28 8002548: f043 0210 orr.w r2, r3, #16 800254c: 687b ldr r3, [r7, #4] 800254e: 629a str r2, [r3, #40] ; 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8002550: 687b ldr r3, [r7, #4] 8002552: 6adb ldr r3, [r3, #44] ; 0x2c 8002554: f043 0201 orr.w r2, r3, #1 8002558: 687b ldr r3, [r7, #4] 800255a: 62da str r2, [r3, #44] ; 0x2c return HAL_ERROR; 800255c: 2301 movs r3, #1 800255e: e007 b.n 8002570 while(ADC_IS_ENABLE(hadc) != RESET) 8002560: 687b ldr r3, [r7, #4] 8002562: 681b ldr r3, [r3, #0] 8002564: 689b ldr r3, [r3, #8] 8002566: f003 0301 and.w r3, r3, #1 800256a: 2b01 cmp r3, #1 800256c: d0e3 beq.n 8002536 } } } /* Return HAL status */ return HAL_OK; 800256e: 2300 movs r3, #0 } 8002570: 4618 mov r0, r3 8002572: 3710 adds r7, #16 8002574: 46bd mov sp, r7 8002576: bd80 pop {r7, pc} 08002578 : * @brief DMA transfer complete callback. * @param hdma: pointer to DMA handle. * @retval None */ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) { 8002578: b580 push {r7, lr} 800257a: b084 sub sp, #16 800257c: af00 add r7, sp, #0 800257e: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 8002580: 687b ldr r3, [r7, #4] 8002582: 6a5b ldr r3, [r3, #36] ; 0x24 8002584: 60fb str r3, [r7, #12] /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) 8002586: 68fb ldr r3, [r7, #12] 8002588: 6a9b ldr r3, [r3, #40] ; 0x28 800258a: f003 0350 and.w r3, r3, #80 ; 0x50 800258e: 2b00 cmp r3, #0 8002590: d127 bne.n 80025e2 { /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 8002592: 68fb ldr r3, [r7, #12] 8002594: 6a9b ldr r3, [r3, #40] ; 0x28 8002596: f443 7200 orr.w r2, r3, #512 ; 0x200 800259a: 68fb ldr r3, [r7, #12] 800259c: 629a str r2, [r3, #40] ; 0x28 /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 800259e: 68fb ldr r3, [r7, #12] 80025a0: 681b ldr r3, [r3, #0] 80025a2: 689b ldr r3, [r3, #8] 80025a4: f403 2360 and.w r3, r3, #917504 ; 0xe0000 80025a8: f5b3 2f60 cmp.w r3, #917504 ; 0xe0000 80025ac: d115 bne.n 80025da (hadc->Init.ContinuousConvMode == DISABLE) ) 80025ae: 68fb ldr r3, [r7, #12] 80025b0: 7b1b ldrb r3, [r3, #12] if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 80025b2: 2b00 cmp r3, #0 80025b4: d111 bne.n 80025da { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 80025b6: 68fb ldr r3, [r7, #12] 80025b8: 6a9b ldr r3, [r3, #40] ; 0x28 80025ba: f423 7280 bic.w r2, r3, #256 ; 0x100 80025be: 68fb ldr r3, [r7, #12] 80025c0: 629a str r2, [r3, #40] ; 0x28 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 80025c2: 68fb ldr r3, [r7, #12] 80025c4: 6a9b ldr r3, [r3, #40] ; 0x28 80025c6: f403 5380 and.w r3, r3, #4096 ; 0x1000 80025ca: 2b00 cmp r3, #0 80025cc: d105 bne.n 80025da { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 80025ce: 68fb ldr r3, [r7, #12] 80025d0: 6a9b ldr r3, [r3, #40] ; 0x28 80025d2: f043 0201 orr.w r2, r3, #1 80025d6: 68fb ldr r3, [r7, #12] 80025d8: 629a str r2, [r3, #40] ; 0x28 /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); 80025da: 68f8 ldr r0, [r7, #12] 80025dc: f7ff f862 bl 80016a4 else { /* Call DMA error callback */ hadc->DMA_Handle->XferErrorCallback(hdma); } } 80025e0: e004 b.n 80025ec hadc->DMA_Handle->XferErrorCallback(hdma); 80025e2: 68fb ldr r3, [r7, #12] 80025e4: 6a1b ldr r3, [r3, #32] 80025e6: 6b1b ldr r3, [r3, #48] ; 0x30 80025e8: 6878 ldr r0, [r7, #4] 80025ea: 4798 blx r3 } 80025ec: bf00 nop 80025ee: 3710 adds r7, #16 80025f0: 46bd mov sp, r7 80025f2: bd80 pop {r7, pc} 080025f4 : * @brief DMA half transfer complete callback. * @param hdma: pointer to DMA handle. * @retval None */ void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) { 80025f4: b580 push {r7, lr} 80025f6: b084 sub sp, #16 80025f8: af00 add r7, sp, #0 80025fa: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 80025fc: 687b ldr r3, [r7, #4] 80025fe: 6a5b ldr r3, [r3, #36] ; 0x24 8002600: 60fb str r3, [r7, #12] /* Half conversion callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvHalfCpltCallback(hadc); #else HAL_ADC_ConvHalfCpltCallback(hadc); 8002602: 68f8 ldr r0, [r7, #12] 8002604: f7ff fe19 bl 800223a #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } 8002608: bf00 nop 800260a: 3710 adds r7, #16 800260c: 46bd mov sp, r7 800260e: bd80 pop {r7, pc} 08002610 : * @brief DMA error callback * @param hdma: pointer to DMA handle. * @retval None */ void ADC_DMAError(DMA_HandleTypeDef *hdma) { 8002610: b580 push {r7, lr} 8002612: b084 sub sp, #16 8002614: af00 add r7, sp, #0 8002616: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 8002618: 687b ldr r3, [r7, #4] 800261a: 6a5b ldr r3, [r3, #36] ; 0x24 800261c: 60fb str r3, [r7, #12] /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); 800261e: 68fb ldr r3, [r7, #12] 8002620: 6a9b ldr r3, [r3, #40] ; 0x28 8002622: f043 0240 orr.w r2, r3, #64 ; 0x40 8002626: 68fb ldr r3, [r7, #12] 8002628: 629a str r2, [r3, #40] ; 0x28 /* Set ADC error code to DMA error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); 800262a: 68fb ldr r3, [r7, #12] 800262c: 6adb ldr r3, [r3, #44] ; 0x2c 800262e: f043 0204 orr.w r2, r3, #4 8002632: 68fb ldr r3, [r7, #12] 8002634: 62da str r2, [r3, #44] ; 0x2c /* Error callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ErrorCallback(hadc); #else HAL_ADC_ErrorCallback(hadc); 8002636: 68f8 ldr r0, [r7, #12] 8002638: f7ff fe11 bl 800225e #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } 800263c: bf00 nop 800263e: 3710 adds r7, #16 8002640: 46bd mov sp, r7 8002642: bd80 pop {r7, pc} 08002644 : * the completion of this function. * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc) { 8002644: b590 push {r4, r7, lr} 8002646: b087 sub sp, #28 8002648: af00 add r7, sp, #0 800264a: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800264c: 2300 movs r3, #0 800264e: 75fb strb r3, [r7, #23] uint32_t tickstart; __IO uint32_t wait_loop_index = 0U; 8002650: 2300 movs r3, #0 8002652: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); 8002654: 687b ldr r3, [r7, #4] 8002656: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 800265a: 2b01 cmp r3, #1 800265c: d101 bne.n 8002662 800265e: 2302 movs r3, #2 8002660: e086 b.n 8002770 8002662: 687b ldr r3, [r7, #4] 8002664: 2201 movs r2, #1 8002666: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* 1. Calibration prerequisite: */ /* - ADC must be disabled for at least two ADC clock cycles in disable */ /* mode before ADC enable */ /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 800266a: 6878 ldr r0, [r7, #4] 800266c: f7ff ff4a bl 8002504 8002670: 4603 mov r3, r0 8002672: 75fb strb r3, [r7, #23] /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) 8002674: 7dfb ldrb r3, [r7, #23] 8002676: 2b00 cmp r3, #0 8002678: d175 bne.n 8002766 { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800267a: 687b ldr r3, [r7, #4] 800267c: 6a9b ldr r3, [r3, #40] ; 0x28 800267e: f423 5388 bic.w r3, r3, #4352 ; 0x1100 8002682: f023 0302 bic.w r3, r3, #2 8002686: f043 0202 orr.w r2, r3, #2 800268a: 687b ldr r3, [r7, #4] 800268c: 629a str r2, [r3, #40] ; 0x28 /* Hardware prerequisite: delay before starting the calibration. */ /* - Computation of CPU clock cycles corresponding to ADC clock cycles. */ /* - Wait for the expected ADC clock cycles delay */ wait_loop_index = ((SystemCoreClock / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) 800268e: 4b3a ldr r3, [pc, #232] ; (8002778 ) 8002690: 681c ldr r4, [r3, #0] 8002692: 2002 movs r0, #2 8002694: f001 fc20 bl 8003ed8 8002698: 4603 mov r3, r0 800269a: fbb4 f3f3 udiv r3, r4, r3 * ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES ); 800269e: 005b lsls r3, r3, #1 wait_loop_index = ((SystemCoreClock 80026a0: 60fb str r3, [r7, #12] while(wait_loop_index != 0U) 80026a2: e002 b.n 80026aa { wait_loop_index--; 80026a4: 68fb ldr r3, [r7, #12] 80026a6: 3b01 subs r3, #1 80026a8: 60fb str r3, [r7, #12] while(wait_loop_index != 0U) 80026aa: 68fb ldr r3, [r7, #12] 80026ac: 2b00 cmp r3, #0 80026ae: d1f9 bne.n 80026a4 } /* 2. Enable the ADC peripheral */ ADC_Enable(hadc); 80026b0: 6878 ldr r0, [r7, #4] 80026b2: f7ff fed5 bl 8002460 /* 3. Resets ADC calibration registers */ SET_BIT(hadc->Instance->CR2, ADC_CR2_RSTCAL); 80026b6: 687b ldr r3, [r7, #4] 80026b8: 681b ldr r3, [r3, #0] 80026ba: 689a ldr r2, [r3, #8] 80026bc: 687b ldr r3, [r7, #4] 80026be: 681b ldr r3, [r3, #0] 80026c0: f042 0208 orr.w r2, r2, #8 80026c4: 609a str r2, [r3, #8] tickstart = HAL_GetTick(); 80026c6: f7ff fb57 bl 8001d78 80026ca: 6138 str r0, [r7, #16] /* Wait for calibration reset completion */ while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 80026cc: e014 b.n 80026f8 { if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) 80026ce: f7ff fb53 bl 8001d78 80026d2: 4602 mov r2, r0 80026d4: 693b ldr r3, [r7, #16] 80026d6: 1ad3 subs r3, r2, r3 80026d8: 2b0a cmp r3, #10 80026da: d90d bls.n 80026f8 { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 80026dc: 687b ldr r3, [r7, #4] 80026de: 6a9b ldr r3, [r3, #40] ; 0x28 80026e0: f023 0312 bic.w r3, r3, #18 80026e4: f043 0210 orr.w r2, r3, #16 80026e8: 687b ldr r3, [r7, #4] 80026ea: 629a str r2, [r3, #40] ; 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); 80026ec: 687b ldr r3, [r7, #4] 80026ee: 2200 movs r2, #0 80026f0: f883 2024 strb.w r2, [r3, #36] ; 0x24 return HAL_ERROR; 80026f4: 2301 movs r3, #1 80026f6: e03b b.n 8002770 while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 80026f8: 687b ldr r3, [r7, #4] 80026fa: 681b ldr r3, [r3, #0] 80026fc: 689b ldr r3, [r3, #8] 80026fe: f003 0308 and.w r3, r3, #8 8002702: 2b00 cmp r3, #0 8002704: d1e3 bne.n 80026ce } } /* 4. Start ADC calibration */ SET_BIT(hadc->Instance->CR2, ADC_CR2_CAL); 8002706: 687b ldr r3, [r7, #4] 8002708: 681b ldr r3, [r3, #0] 800270a: 689a ldr r2, [r3, #8] 800270c: 687b ldr r3, [r7, #4] 800270e: 681b ldr r3, [r3, #0] 8002710: f042 0204 orr.w r2, r2, #4 8002714: 609a str r2, [r3, #8] tickstart = HAL_GetTick(); 8002716: f7ff fb2f bl 8001d78 800271a: 6138 str r0, [r7, #16] /* Wait for calibration completion */ while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 800271c: e014 b.n 8002748 { if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) 800271e: f7ff fb2b bl 8001d78 8002722: 4602 mov r2, r0 8002724: 693b ldr r3, [r7, #16] 8002726: 1ad3 subs r3, r2, r3 8002728: 2b0a cmp r3, #10 800272a: d90d bls.n 8002748 { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 800272c: 687b ldr r3, [r7, #4] 800272e: 6a9b ldr r3, [r3, #40] ; 0x28 8002730: f023 0312 bic.w r3, r3, #18 8002734: f043 0210 orr.w r2, r3, #16 8002738: 687b ldr r3, [r7, #4] 800273a: 629a str r2, [r3, #40] ; 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); 800273c: 687b ldr r3, [r7, #4] 800273e: 2200 movs r2, #0 8002740: f883 2024 strb.w r2, [r3, #36] ; 0x24 return HAL_ERROR; 8002744: 2301 movs r3, #1 8002746: e013 b.n 8002770 while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 8002748: 687b ldr r3, [r7, #4] 800274a: 681b ldr r3, [r3, #0] 800274c: 689b ldr r3, [r3, #8] 800274e: f003 0304 and.w r3, r3, #4 8002752: 2b00 cmp r3, #0 8002754: d1e3 bne.n 800271e } } /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8002756: 687b ldr r3, [r7, #4] 8002758: 6a9b ldr r3, [r3, #40] ; 0x28 800275a: f023 0303 bic.w r3, r3, #3 800275e: f043 0201 orr.w r2, r3, #1 8002762: 687b ldr r3, [r7, #4] 8002764: 629a str r2, [r3, #40] ; 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); } /* Process unlocked */ __HAL_UNLOCK(hadc); 8002766: 687b ldr r3, [r7, #4] 8002768: 2200 movs r2, #0 800276a: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Return function status */ return tmp_hal_status; 800276e: 7dfb ldrb r3, [r7, #23] } 8002770: 4618 mov r0, r3 8002772: 371c adds r7, #28 8002774: 46bd mov sp, r7 8002776: bd90 pop {r4, r7, pc} 8002778: 20000008 .word 0x20000008 0800277c : * @brief Injected conversion complete callback in non blocking mode * @param hadc: ADC handle * @retval None */ __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) { 800277c: b480 push {r7} 800277e: b083 sub sp, #12 8002780: af00 add r7, sp, #0 8002782: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file */ } 8002784: bf00 nop 8002786: 370c adds r7, #12 8002788: 46bd mov sp, r7 800278a: bc80 pop {r7} 800278c: 4770 bx lr ... 08002790 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8002790: b480 push {r7} 8002792: b085 sub sp, #20 8002794: af00 add r7, sp, #0 8002796: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8002798: 687b ldr r3, [r7, #4] 800279a: f003 0307 and.w r3, r3, #7 800279e: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 80027a0: 4b0c ldr r3, [pc, #48] ; (80027d4 <__NVIC_SetPriorityGrouping+0x44>) 80027a2: 68db ldr r3, [r3, #12] 80027a4: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 80027a6: 68ba ldr r2, [r7, #8] 80027a8: f64f 03ff movw r3, #63743 ; 0xf8ff 80027ac: 4013 ands r3, r2 80027ae: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 80027b0: 68fb ldr r3, [r7, #12] 80027b2: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 80027b4: 68bb ldr r3, [r7, #8] 80027b6: 4313 orrs r3, r2 reg_value = (reg_value | 80027b8: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 80027bc: f443 3300 orr.w r3, r3, #131072 ; 0x20000 80027c0: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 80027c2: 4a04 ldr r2, [pc, #16] ; (80027d4 <__NVIC_SetPriorityGrouping+0x44>) 80027c4: 68bb ldr r3, [r7, #8] 80027c6: 60d3 str r3, [r2, #12] } 80027c8: bf00 nop 80027ca: 3714 adds r7, #20 80027cc: 46bd mov sp, r7 80027ce: bc80 pop {r7} 80027d0: 4770 bx lr 80027d2: bf00 nop 80027d4: e000ed00 .word 0xe000ed00 080027d8 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 80027d8: b480 push {r7} 80027da: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 80027dc: 4b04 ldr r3, [pc, #16] ; (80027f0 <__NVIC_GetPriorityGrouping+0x18>) 80027de: 68db ldr r3, [r3, #12] 80027e0: 0a1b lsrs r3, r3, #8 80027e2: f003 0307 and.w r3, r3, #7 } 80027e6: 4618 mov r0, r3 80027e8: 46bd mov sp, r7 80027ea: bc80 pop {r7} 80027ec: 4770 bx lr 80027ee: bf00 nop 80027f0: e000ed00 .word 0xe000ed00 080027f4 <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 80027f4: b480 push {r7} 80027f6: b083 sub sp, #12 80027f8: af00 add r7, sp, #0 80027fa: 4603 mov r3, r0 80027fc: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 80027fe: f997 3007 ldrsb.w r3, [r7, #7] 8002802: 2b00 cmp r3, #0 8002804: db0b blt.n 800281e <__NVIC_EnableIRQ+0x2a> { NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8002806: 79fb ldrb r3, [r7, #7] 8002808: f003 021f and.w r2, r3, #31 800280c: 4906 ldr r1, [pc, #24] ; (8002828 <__NVIC_EnableIRQ+0x34>) 800280e: f997 3007 ldrsb.w r3, [r7, #7] 8002812: 095b lsrs r3, r3, #5 8002814: 2001 movs r0, #1 8002816: fa00 f202 lsl.w r2, r0, r2 800281a: f841 2023 str.w r2, [r1, r3, lsl #2] } } 800281e: bf00 nop 8002820: 370c adds r7, #12 8002822: 46bd mov sp, r7 8002824: bc80 pop {r7} 8002826: 4770 bx lr 8002828: e000e100 .word 0xe000e100 0800282c <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 800282c: b480 push {r7} 800282e: b083 sub sp, #12 8002830: af00 add r7, sp, #0 8002832: 4603 mov r3, r0 8002834: 6039 str r1, [r7, #0] 8002836: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8002838: f997 3007 ldrsb.w r3, [r7, #7] 800283c: 2b00 cmp r3, #0 800283e: db0a blt.n 8002856 <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8002840: 683b ldr r3, [r7, #0] 8002842: b2da uxtb r2, r3 8002844: 490c ldr r1, [pc, #48] ; (8002878 <__NVIC_SetPriority+0x4c>) 8002846: f997 3007 ldrsb.w r3, [r7, #7] 800284a: 0112 lsls r2, r2, #4 800284c: b2d2 uxtb r2, r2 800284e: 440b add r3, r1 8002850: f883 2300 strb.w r2, [r3, #768] ; 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 8002854: e00a b.n 800286c <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8002856: 683b ldr r3, [r7, #0] 8002858: b2da uxtb r2, r3 800285a: 4908 ldr r1, [pc, #32] ; (800287c <__NVIC_SetPriority+0x50>) 800285c: 79fb ldrb r3, [r7, #7] 800285e: f003 030f and.w r3, r3, #15 8002862: 3b04 subs r3, #4 8002864: 0112 lsls r2, r2, #4 8002866: b2d2 uxtb r2, r2 8002868: 440b add r3, r1 800286a: 761a strb r2, [r3, #24] } 800286c: bf00 nop 800286e: 370c adds r7, #12 8002870: 46bd mov sp, r7 8002872: bc80 pop {r7} 8002874: 4770 bx lr 8002876: bf00 nop 8002878: e000e100 .word 0xe000e100 800287c: e000ed00 .word 0xe000ed00 08002880 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 8002880: b480 push {r7} 8002882: b089 sub sp, #36 ; 0x24 8002884: af00 add r7, sp, #0 8002886: 60f8 str r0, [r7, #12] 8002888: 60b9 str r1, [r7, #8] 800288a: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 800288c: 68fb ldr r3, [r7, #12] 800288e: f003 0307 and.w r3, r3, #7 8002892: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8002894: 69fb ldr r3, [r7, #28] 8002896: f1c3 0307 rsb r3, r3, #7 800289a: 2b04 cmp r3, #4 800289c: bf28 it cs 800289e: 2304 movcs r3, #4 80028a0: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 80028a2: 69fb ldr r3, [r7, #28] 80028a4: 3304 adds r3, #4 80028a6: 2b06 cmp r3, #6 80028a8: d902 bls.n 80028b0 80028aa: 69fb ldr r3, [r7, #28] 80028ac: 3b03 subs r3, #3 80028ae: e000 b.n 80028b2 80028b0: 2300 movs r3, #0 80028b2: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80028b4: f04f 32ff mov.w r2, #4294967295 80028b8: 69bb ldr r3, [r7, #24] 80028ba: fa02 f303 lsl.w r3, r2, r3 80028be: 43da mvns r2, r3 80028c0: 68bb ldr r3, [r7, #8] 80028c2: 401a ands r2, r3 80028c4: 697b ldr r3, [r7, #20] 80028c6: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 80028c8: f04f 31ff mov.w r1, #4294967295 80028cc: 697b ldr r3, [r7, #20] 80028ce: fa01 f303 lsl.w r3, r1, r3 80028d2: 43d9 mvns r1, r3 80028d4: 687b ldr r3, [r7, #4] 80028d6: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80028d8: 4313 orrs r3, r2 ); } 80028da: 4618 mov r0, r3 80028dc: 3724 adds r7, #36 ; 0x24 80028de: 46bd mov sp, r7 80028e0: bc80 pop {r7} 80028e2: 4770 bx lr 080028e4 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 80028e4: b580 push {r7, lr} 80028e6: b082 sub sp, #8 80028e8: af00 add r7, sp, #0 80028ea: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 80028ec: 6878 ldr r0, [r7, #4] 80028ee: f7ff ff4f bl 8002790 <__NVIC_SetPriorityGrouping> } 80028f2: bf00 nop 80028f4: 3708 adds r7, #8 80028f6: 46bd mov sp, r7 80028f8: bd80 pop {r7, pc} 080028fa : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 80028fa: b580 push {r7, lr} 80028fc: b086 sub sp, #24 80028fe: af00 add r7, sp, #0 8002900: 4603 mov r3, r0 8002902: 60b9 str r1, [r7, #8] 8002904: 607a str r2, [r7, #4] 8002906: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 8002908: 2300 movs r3, #0 800290a: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 800290c: f7ff ff64 bl 80027d8 <__NVIC_GetPriorityGrouping> 8002910: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8002912: 687a ldr r2, [r7, #4] 8002914: 68b9 ldr r1, [r7, #8] 8002916: 6978 ldr r0, [r7, #20] 8002918: f7ff ffb2 bl 8002880 800291c: 4602 mov r2, r0 800291e: f997 300f ldrsb.w r3, [r7, #15] 8002922: 4611 mov r1, r2 8002924: 4618 mov r0, r3 8002926: f7ff ff81 bl 800282c <__NVIC_SetPriority> } 800292a: bf00 nop 800292c: 3718 adds r7, #24 800292e: 46bd mov sp, r7 8002930: bd80 pop {r7, pc} 08002932 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 8002932: b580 push {r7, lr} 8002934: b082 sub sp, #8 8002936: af00 add r7, sp, #0 8002938: 4603 mov r3, r0 800293a: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 800293c: f997 3007 ldrsb.w r3, [r7, #7] 8002940: 4618 mov r0, r3 8002942: f7ff ff57 bl 80027f4 <__NVIC_EnableIRQ> } 8002946: bf00 nop 8002948: 3708 adds r7, #8 800294a: 46bd mov sp, r7 800294c: bd80 pop {r7, pc} ... 08002950 : * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { 8002950: b480 push {r7} 8002952: b085 sub sp, #20 8002954: af00 add r7, sp, #0 8002956: 6078 str r0, [r7, #4] uint32_t tmp = 0U; 8002958: 2300 movs r3, #0 800295a: 60fb str r3, [r7, #12] /* Check the DMA handle allocation */ if(hdma == NULL) 800295c: 687b ldr r3, [r7, #4] 800295e: 2b00 cmp r3, #0 8002960: d101 bne.n 8002966 { return HAL_ERROR; 8002962: 2301 movs r3, #1 8002964: e043 b.n 80029ee hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; hdma->DmaBaseAddress = DMA2; } #else /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; 8002966: 687b ldr r3, [r7, #4] 8002968: 681b ldr r3, [r3, #0] 800296a: 461a mov r2, r3 800296c: 4b22 ldr r3, [pc, #136] ; (80029f8 ) 800296e: 4413 add r3, r2 8002970: 4a22 ldr r2, [pc, #136] ; (80029fc ) 8002972: fba2 2303 umull r2, r3, r2, r3 8002976: 091b lsrs r3, r3, #4 8002978: 009a lsls r2, r3, #2 800297a: 687b ldr r3, [r7, #4] 800297c: 641a str r2, [r3, #64] ; 0x40 hdma->DmaBaseAddress = DMA1; 800297e: 687b ldr r3, [r7, #4] 8002980: 4a1f ldr r2, [pc, #124] ; (8002a00 ) 8002982: 63da str r2, [r3, #60] ; 0x3c #endif /* DMA2 */ /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8002984: 687b ldr r3, [r7, #4] 8002986: 2202 movs r2, #2 8002988: f883 2021 strb.w r2, [r3, #33] ; 0x21 /* Get the CR register value */ tmp = hdma->Instance->CCR; 800298c: 687b ldr r3, [r7, #4] 800298e: 681b ldr r3, [r3, #0] 8002990: 681b ldr r3, [r3, #0] 8002992: 60fb str r3, [r7, #12] /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ 8002994: 68fb ldr r3, [r7, #12] 8002996: f423 537f bic.w r3, r3, #16320 ; 0x3fc0 800299a: f023 0330 bic.w r3, r3, #48 ; 0x30 800299e: 60fb str r3, [r7, #12] DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ DMA_CCR_DIR)); /* Prepare the DMA Channel configuration */ tmp |= hdma->Init.Direction | 80029a0: 687b ldr r3, [r7, #4] 80029a2: 685a ldr r2, [r3, #4] hdma->Init.PeriphInc | hdma->Init.MemInc | 80029a4: 687b ldr r3, [r7, #4] 80029a6: 689b ldr r3, [r3, #8] tmp |= hdma->Init.Direction | 80029a8: 431a orrs r2, r3 hdma->Init.PeriphInc | hdma->Init.MemInc | 80029aa: 687b ldr r3, [r7, #4] 80029ac: 68db ldr r3, [r3, #12] 80029ae: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 80029b0: 687b ldr r3, [r7, #4] 80029b2: 691b ldr r3, [r3, #16] hdma->Init.PeriphInc | hdma->Init.MemInc | 80029b4: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 80029b6: 687b ldr r3, [r7, #4] 80029b8: 695b ldr r3, [r3, #20] 80029ba: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 80029bc: 687b ldr r3, [r7, #4] 80029be: 699b ldr r3, [r3, #24] hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 80029c0: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 80029c2: 687b ldr r3, [r7, #4] 80029c4: 69db ldr r3, [r3, #28] 80029c6: 4313 orrs r3, r2 tmp |= hdma->Init.Direction | 80029c8: 68fa ldr r2, [r7, #12] 80029ca: 4313 orrs r3, r2 80029cc: 60fb str r3, [r7, #12] /* Write to DMA Channel CR register */ hdma->Instance->CCR = tmp; 80029ce: 687b ldr r3, [r7, #4] 80029d0: 681b ldr r3, [r3, #0] 80029d2: 68fa ldr r2, [r7, #12] 80029d4: 601a str r2, [r3, #0] /* Initialise the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 80029d6: 687b ldr r3, [r7, #4] 80029d8: 2200 movs r2, #0 80029da: 639a str r2, [r3, #56] ; 0x38 /* Initialize the DMA state*/ hdma->State = HAL_DMA_STATE_READY; 80029dc: 687b ldr r3, [r7, #4] 80029de: 2201 movs r2, #1 80029e0: f883 2021 strb.w r2, [r3, #33] ; 0x21 /* Allocate lock resource and initialize it */ hdma->Lock = HAL_UNLOCKED; 80029e4: 687b ldr r3, [r7, #4] 80029e6: 2200 movs r2, #0 80029e8: f883 2020 strb.w r2, [r3, #32] return HAL_OK; 80029ec: 2300 movs r3, #0 } 80029ee: 4618 mov r0, r3 80029f0: 3714 adds r7, #20 80029f2: 46bd mov sp, r7 80029f4: bc80 pop {r7} 80029f6: 4770 bx lr 80029f8: bffdfff8 .word 0xbffdfff8 80029fc: cccccccd .word 0xcccccccd 8002a00: 40020000 .word 0x40020000 08002a04 : * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 8002a04: b580 push {r7, lr} 8002a06: b086 sub sp, #24 8002a08: af00 add r7, sp, #0 8002a0a: 60f8 str r0, [r7, #12] 8002a0c: 60b9 str r1, [r7, #8] 8002a0e: 607a str r2, [r7, #4] 8002a10: 603b str r3, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 8002a12: 2300 movs r3, #0 8002a14: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Process locked */ __HAL_LOCK(hdma); 8002a16: 68fb ldr r3, [r7, #12] 8002a18: f893 3020 ldrb.w r3, [r3, #32] 8002a1c: 2b01 cmp r3, #1 8002a1e: d101 bne.n 8002a24 8002a20: 2302 movs r3, #2 8002a22: e04a b.n 8002aba 8002a24: 68fb ldr r3, [r7, #12] 8002a26: 2201 movs r2, #1 8002a28: f883 2020 strb.w r2, [r3, #32] if(HAL_DMA_STATE_READY == hdma->State) 8002a2c: 68fb ldr r3, [r7, #12] 8002a2e: f893 3021 ldrb.w r3, [r3, #33] ; 0x21 8002a32: 2b01 cmp r3, #1 8002a34: d13a bne.n 8002aac { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8002a36: 68fb ldr r3, [r7, #12] 8002a38: 2202 movs r2, #2 8002a3a: f883 2021 strb.w r2, [r3, #33] ; 0x21 hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8002a3e: 68fb ldr r3, [r7, #12] 8002a40: 2200 movs r2, #0 8002a42: 639a str r2, [r3, #56] ; 0x38 /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); 8002a44: 68fb ldr r3, [r7, #12] 8002a46: 681b ldr r3, [r3, #0] 8002a48: 681a ldr r2, [r3, #0] 8002a4a: 68fb ldr r3, [r7, #12] 8002a4c: 681b ldr r3, [r3, #0] 8002a4e: f022 0201 bic.w r2, r2, #1 8002a52: 601a str r2, [r3, #0] /* Configure the source, destination address and the data length & clear flags*/ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); 8002a54: 683b ldr r3, [r7, #0] 8002a56: 687a ldr r2, [r7, #4] 8002a58: 68b9 ldr r1, [r7, #8] 8002a5a: 68f8 ldr r0, [r7, #12] 8002a5c: f000 f9ae bl 8002dbc /* Enable the transfer complete interrupt */ /* Enable the transfer Error interrupt */ if(NULL != hdma->XferHalfCpltCallback) 8002a60: 68fb ldr r3, [r7, #12] 8002a62: 6adb ldr r3, [r3, #44] ; 0x2c 8002a64: 2b00 cmp r3, #0 8002a66: d008 beq.n 8002a7a { /* Enable the Half transfer complete interrupt as well */ __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8002a68: 68fb ldr r3, [r7, #12] 8002a6a: 681b ldr r3, [r3, #0] 8002a6c: 681a ldr r2, [r3, #0] 8002a6e: 68fb ldr r3, [r7, #12] 8002a70: 681b ldr r3, [r3, #0] 8002a72: f042 020e orr.w r2, r2, #14 8002a76: 601a str r2, [r3, #0] 8002a78: e00f b.n 8002a9a } else { __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 8002a7a: 68fb ldr r3, [r7, #12] 8002a7c: 681b ldr r3, [r3, #0] 8002a7e: 681a ldr r2, [r3, #0] 8002a80: 68fb ldr r3, [r7, #12] 8002a82: 681b ldr r3, [r3, #0] 8002a84: f022 0204 bic.w r2, r2, #4 8002a88: 601a str r2, [r3, #0] __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); 8002a8a: 68fb ldr r3, [r7, #12] 8002a8c: 681b ldr r3, [r3, #0] 8002a8e: 681a ldr r2, [r3, #0] 8002a90: 68fb ldr r3, [r7, #12] 8002a92: 681b ldr r3, [r3, #0] 8002a94: f042 020a orr.w r2, r2, #10 8002a98: 601a str r2, [r3, #0] } /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); 8002a9a: 68fb ldr r3, [r7, #12] 8002a9c: 681b ldr r3, [r3, #0] 8002a9e: 681a ldr r2, [r3, #0] 8002aa0: 68fb ldr r3, [r7, #12] 8002aa2: 681b ldr r3, [r3, #0] 8002aa4: f042 0201 orr.w r2, r2, #1 8002aa8: 601a str r2, [r3, #0] 8002aaa: e005 b.n 8002ab8 } else { /* Process Unlocked */ __HAL_UNLOCK(hdma); 8002aac: 68fb ldr r3, [r7, #12] 8002aae: 2200 movs r2, #0 8002ab0: f883 2020 strb.w r2, [r3, #32] /* Remain BUSY */ status = HAL_BUSY; 8002ab4: 2302 movs r3, #2 8002ab6: 75fb strb r3, [r7, #23] } return status; 8002ab8: 7dfb ldrb r3, [r7, #23] } 8002aba: 4618 mov r0, r3 8002abc: 3718 adds r7, #24 8002abe: 46bd mov sp, r7 8002ac0: bd80 pop {r7, pc} ... 08002ac4 : * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 8002ac4: b580 push {r7, lr} 8002ac6: b084 sub sp, #16 8002ac8: af00 add r7, sp, #0 8002aca: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8002acc: 2300 movs r3, #0 8002ace: 73fb strb r3, [r7, #15] if(HAL_DMA_STATE_BUSY != hdma->State) 8002ad0: 687b ldr r3, [r7, #4] 8002ad2: f893 3021 ldrb.w r3, [r3, #33] ; 0x21 8002ad6: 2b02 cmp r3, #2 8002ad8: d005 beq.n 8002ae6 { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8002ada: 687b ldr r3, [r7, #4] 8002adc: 2204 movs r2, #4 8002ade: 639a str r2, [r3, #56] ; 0x38 status = HAL_ERROR; 8002ae0: 2301 movs r3, #1 8002ae2: 73fb strb r3, [r7, #15] 8002ae4: e051 b.n 8002b8a } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8002ae6: 687b ldr r3, [r7, #4] 8002ae8: 681b ldr r3, [r3, #0] 8002aea: 681a ldr r2, [r3, #0] 8002aec: 687b ldr r3, [r7, #4] 8002aee: 681b ldr r3, [r3, #0] 8002af0: f022 020e bic.w r2, r2, #14 8002af4: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 8002af6: 687b ldr r3, [r7, #4] 8002af8: 681b ldr r3, [r3, #0] 8002afa: 681a ldr r2, [r3, #0] 8002afc: 687b ldr r3, [r7, #4] 8002afe: 681b ldr r3, [r3, #0] 8002b00: f022 0201 bic.w r2, r2, #1 8002b04: 601a str r2, [r3, #0] /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); 8002b06: 687b ldr r3, [r7, #4] 8002b08: 681b ldr r3, [r3, #0] 8002b0a: 4a22 ldr r2, [pc, #136] ; (8002b94 ) 8002b0c: 4293 cmp r3, r2 8002b0e: d029 beq.n 8002b64 8002b10: 687b ldr r3, [r7, #4] 8002b12: 681b ldr r3, [r3, #0] 8002b14: 4a20 ldr r2, [pc, #128] ; (8002b98 ) 8002b16: 4293 cmp r3, r2 8002b18: d022 beq.n 8002b60 8002b1a: 687b ldr r3, [r7, #4] 8002b1c: 681b ldr r3, [r3, #0] 8002b1e: 4a1f ldr r2, [pc, #124] ; (8002b9c ) 8002b20: 4293 cmp r3, r2 8002b22: d01a beq.n 8002b5a 8002b24: 687b ldr r3, [r7, #4] 8002b26: 681b ldr r3, [r3, #0] 8002b28: 4a1d ldr r2, [pc, #116] ; (8002ba0 ) 8002b2a: 4293 cmp r3, r2 8002b2c: d012 beq.n 8002b54 8002b2e: 687b ldr r3, [r7, #4] 8002b30: 681b ldr r3, [r3, #0] 8002b32: 4a1c ldr r2, [pc, #112] ; (8002ba4 ) 8002b34: 4293 cmp r3, r2 8002b36: d00a beq.n 8002b4e 8002b38: 687b ldr r3, [r7, #4] 8002b3a: 681b ldr r3, [r3, #0] 8002b3c: 4a1a ldr r2, [pc, #104] ; (8002ba8 ) 8002b3e: 4293 cmp r3, r2 8002b40: d102 bne.n 8002b48 8002b42: f44f 1380 mov.w r3, #1048576 ; 0x100000 8002b46: e00e b.n 8002b66 8002b48: f04f 7380 mov.w r3, #16777216 ; 0x1000000 8002b4c: e00b b.n 8002b66 8002b4e: f44f 3380 mov.w r3, #65536 ; 0x10000 8002b52: e008 b.n 8002b66 8002b54: f44f 5380 mov.w r3, #4096 ; 0x1000 8002b58: e005 b.n 8002b66 8002b5a: f44f 7380 mov.w r3, #256 ; 0x100 8002b5e: e002 b.n 8002b66 8002b60: 2310 movs r3, #16 8002b62: e000 b.n 8002b66 8002b64: 2301 movs r3, #1 8002b66: 4a11 ldr r2, [pc, #68] ; (8002bac ) 8002b68: 6053 str r3, [r2, #4] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8002b6a: 687b ldr r3, [r7, #4] 8002b6c: 2201 movs r2, #1 8002b6e: f883 2021 strb.w r2, [r3, #33] ; 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8002b72: 687b ldr r3, [r7, #4] 8002b74: 2200 movs r2, #0 8002b76: f883 2020 strb.w r2, [r3, #32] /* Call User Abort callback */ if(hdma->XferAbortCallback != NULL) 8002b7a: 687b ldr r3, [r7, #4] 8002b7c: 6b5b ldr r3, [r3, #52] ; 0x34 8002b7e: 2b00 cmp r3, #0 8002b80: d003 beq.n 8002b8a { hdma->XferAbortCallback(hdma); 8002b82: 687b ldr r3, [r7, #4] 8002b84: 6b5b ldr r3, [r3, #52] ; 0x34 8002b86: 6878 ldr r0, [r7, #4] 8002b88: 4798 blx r3 } } return status; 8002b8a: 7bfb ldrb r3, [r7, #15] } 8002b8c: 4618 mov r0, r3 8002b8e: 3710 adds r7, #16 8002b90: 46bd mov sp, r7 8002b92: bd80 pop {r7, pc} 8002b94: 40020008 .word 0x40020008 8002b98: 4002001c .word 0x4002001c 8002b9c: 40020030 .word 0x40020030 8002ba0: 40020044 .word 0x40020044 8002ba4: 40020058 .word 0x40020058 8002ba8: 4002006c .word 0x4002006c 8002bac: 40020000 .word 0x40020000 08002bb0 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { 8002bb0: b580 push {r7, lr} 8002bb2: b084 sub sp, #16 8002bb4: af00 add r7, sp, #0 8002bb6: 6078 str r0, [r7, #4] uint32_t flag_it = hdma->DmaBaseAddress->ISR; 8002bb8: 687b ldr r3, [r7, #4] 8002bba: 6bdb ldr r3, [r3, #60] ; 0x3c 8002bbc: 681b ldr r3, [r3, #0] 8002bbe: 60fb str r3, [r7, #12] uint32_t source_it = hdma->Instance->CCR; 8002bc0: 687b ldr r3, [r7, #4] 8002bc2: 681b ldr r3, [r3, #0] 8002bc4: 681b ldr r3, [r3, #0] 8002bc6: 60bb str r3, [r7, #8] /* Half Transfer Complete Interrupt management ******************************/ if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET)) 8002bc8: 687b ldr r3, [r7, #4] 8002bca: 6c1b ldr r3, [r3, #64] ; 0x40 8002bcc: 2204 movs r2, #4 8002bce: 409a lsls r2, r3 8002bd0: 68fb ldr r3, [r7, #12] 8002bd2: 4013 ands r3, r2 8002bd4: 2b00 cmp r3, #0 8002bd6: d04f beq.n 8002c78 8002bd8: 68bb ldr r3, [r7, #8] 8002bda: f003 0304 and.w r3, r3, #4 8002bde: 2b00 cmp r3, #0 8002be0: d04a beq.n 8002c78 { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 8002be2: 687b ldr r3, [r7, #4] 8002be4: 681b ldr r3, [r3, #0] 8002be6: 681b ldr r3, [r3, #0] 8002be8: f003 0320 and.w r3, r3, #32 8002bec: 2b00 cmp r3, #0 8002bee: d107 bne.n 8002c00 { /* Disable the half transfer interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 8002bf0: 687b ldr r3, [r7, #4] 8002bf2: 681b ldr r3, [r3, #0] 8002bf4: 681a ldr r2, [r3, #0] 8002bf6: 687b ldr r3, [r7, #4] 8002bf8: 681b ldr r3, [r3, #0] 8002bfa: f022 0204 bic.w r2, r2, #4 8002bfe: 601a str r2, [r3, #0] } /* Clear the half transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); 8002c00: 687b ldr r3, [r7, #4] 8002c02: 681b ldr r3, [r3, #0] 8002c04: 4a66 ldr r2, [pc, #408] ; (8002da0 ) 8002c06: 4293 cmp r3, r2 8002c08: d029 beq.n 8002c5e 8002c0a: 687b ldr r3, [r7, #4] 8002c0c: 681b ldr r3, [r3, #0] 8002c0e: 4a65 ldr r2, [pc, #404] ; (8002da4 ) 8002c10: 4293 cmp r3, r2 8002c12: d022 beq.n 8002c5a 8002c14: 687b ldr r3, [r7, #4] 8002c16: 681b ldr r3, [r3, #0] 8002c18: 4a63 ldr r2, [pc, #396] ; (8002da8 ) 8002c1a: 4293 cmp r3, r2 8002c1c: d01a beq.n 8002c54 8002c1e: 687b ldr r3, [r7, #4] 8002c20: 681b ldr r3, [r3, #0] 8002c22: 4a62 ldr r2, [pc, #392] ; (8002dac ) 8002c24: 4293 cmp r3, r2 8002c26: d012 beq.n 8002c4e 8002c28: 687b ldr r3, [r7, #4] 8002c2a: 681b ldr r3, [r3, #0] 8002c2c: 4a60 ldr r2, [pc, #384] ; (8002db0 ) 8002c2e: 4293 cmp r3, r2 8002c30: d00a beq.n 8002c48 8002c32: 687b ldr r3, [r7, #4] 8002c34: 681b ldr r3, [r3, #0] 8002c36: 4a5f ldr r2, [pc, #380] ; (8002db4 ) 8002c38: 4293 cmp r3, r2 8002c3a: d102 bne.n 8002c42 8002c3c: f44f 0380 mov.w r3, #4194304 ; 0x400000 8002c40: e00e b.n 8002c60 8002c42: f04f 6380 mov.w r3, #67108864 ; 0x4000000 8002c46: e00b b.n 8002c60 8002c48: f44f 2380 mov.w r3, #262144 ; 0x40000 8002c4c: e008 b.n 8002c60 8002c4e: f44f 4380 mov.w r3, #16384 ; 0x4000 8002c52: e005 b.n 8002c60 8002c54: f44f 6380 mov.w r3, #1024 ; 0x400 8002c58: e002 b.n 8002c60 8002c5a: 2340 movs r3, #64 ; 0x40 8002c5c: e000 b.n 8002c60 8002c5e: 2304 movs r3, #4 8002c60: 4a55 ldr r2, [pc, #340] ; (8002db8 ) 8002c62: 6053 str r3, [r2, #4] /* DMA peripheral state is not updated in Half Transfer */ /* but in Transfer Complete case */ if(hdma->XferHalfCpltCallback != NULL) 8002c64: 687b ldr r3, [r7, #4] 8002c66: 6adb ldr r3, [r3, #44] ; 0x2c 8002c68: 2b00 cmp r3, #0 8002c6a: f000 8094 beq.w 8002d96 { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 8002c6e: 687b ldr r3, [r7, #4] 8002c70: 6adb ldr r3, [r3, #44] ; 0x2c 8002c72: 6878 ldr r0, [r7, #4] 8002c74: 4798 blx r3 if(hdma->XferHalfCpltCallback != NULL) 8002c76: e08e b.n 8002d96 } } /* Transfer Complete Interrupt management ***********************************/ else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET)) 8002c78: 687b ldr r3, [r7, #4] 8002c7a: 6c1b ldr r3, [r3, #64] ; 0x40 8002c7c: 2202 movs r2, #2 8002c7e: 409a lsls r2, r3 8002c80: 68fb ldr r3, [r7, #12] 8002c82: 4013 ands r3, r2 8002c84: 2b00 cmp r3, #0 8002c86: d056 beq.n 8002d36 8002c88: 68bb ldr r3, [r7, #8] 8002c8a: f003 0302 and.w r3, r3, #2 8002c8e: 2b00 cmp r3, #0 8002c90: d051 beq.n 8002d36 { if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 8002c92: 687b ldr r3, [r7, #4] 8002c94: 681b ldr r3, [r3, #0] 8002c96: 681b ldr r3, [r3, #0] 8002c98: f003 0320 and.w r3, r3, #32 8002c9c: 2b00 cmp r3, #0 8002c9e: d10b bne.n 8002cb8 { /* Disable the transfer complete and error interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); 8002ca0: 687b ldr r3, [r7, #4] 8002ca2: 681b ldr r3, [r3, #0] 8002ca4: 681a ldr r2, [r3, #0] 8002ca6: 687b ldr r3, [r7, #4] 8002ca8: 681b ldr r3, [r3, #0] 8002caa: f022 020a bic.w r2, r2, #10 8002cae: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8002cb0: 687b ldr r3, [r7, #4] 8002cb2: 2201 movs r2, #1 8002cb4: f883 2021 strb.w r2, [r3, #33] ; 0x21 } /* Clear the transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); 8002cb8: 687b ldr r3, [r7, #4] 8002cba: 681b ldr r3, [r3, #0] 8002cbc: 4a38 ldr r2, [pc, #224] ; (8002da0 ) 8002cbe: 4293 cmp r3, r2 8002cc0: d029 beq.n 8002d16 8002cc2: 687b ldr r3, [r7, #4] 8002cc4: 681b ldr r3, [r3, #0] 8002cc6: 4a37 ldr r2, [pc, #220] ; (8002da4 ) 8002cc8: 4293 cmp r3, r2 8002cca: d022 beq.n 8002d12 8002ccc: 687b ldr r3, [r7, #4] 8002cce: 681b ldr r3, [r3, #0] 8002cd0: 4a35 ldr r2, [pc, #212] ; (8002da8 ) 8002cd2: 4293 cmp r3, r2 8002cd4: d01a beq.n 8002d0c 8002cd6: 687b ldr r3, [r7, #4] 8002cd8: 681b ldr r3, [r3, #0] 8002cda: 4a34 ldr r2, [pc, #208] ; (8002dac ) 8002cdc: 4293 cmp r3, r2 8002cde: d012 beq.n 8002d06 8002ce0: 687b ldr r3, [r7, #4] 8002ce2: 681b ldr r3, [r3, #0] 8002ce4: 4a32 ldr r2, [pc, #200] ; (8002db0 ) 8002ce6: 4293 cmp r3, r2 8002ce8: d00a beq.n 8002d00 8002cea: 687b ldr r3, [r7, #4] 8002cec: 681b ldr r3, [r3, #0] 8002cee: 4a31 ldr r2, [pc, #196] ; (8002db4 ) 8002cf0: 4293 cmp r3, r2 8002cf2: d102 bne.n 8002cfa 8002cf4: f44f 1300 mov.w r3, #2097152 ; 0x200000 8002cf8: e00e b.n 8002d18 8002cfa: f04f 7300 mov.w r3, #33554432 ; 0x2000000 8002cfe: e00b b.n 8002d18 8002d00: f44f 3300 mov.w r3, #131072 ; 0x20000 8002d04: e008 b.n 8002d18 8002d06: f44f 5300 mov.w r3, #8192 ; 0x2000 8002d0a: e005 b.n 8002d18 8002d0c: f44f 7300 mov.w r3, #512 ; 0x200 8002d10: e002 b.n 8002d18 8002d12: 2320 movs r3, #32 8002d14: e000 b.n 8002d18 8002d16: 2302 movs r3, #2 8002d18: 4a27 ldr r2, [pc, #156] ; (8002db8 ) 8002d1a: 6053 str r3, [r2, #4] /* Process Unlocked */ __HAL_UNLOCK(hdma); 8002d1c: 687b ldr r3, [r7, #4] 8002d1e: 2200 movs r2, #0 8002d20: f883 2020 strb.w r2, [r3, #32] if(hdma->XferCpltCallback != NULL) 8002d24: 687b ldr r3, [r7, #4] 8002d26: 6a9b ldr r3, [r3, #40] ; 0x28 8002d28: 2b00 cmp r3, #0 8002d2a: d034 beq.n 8002d96 { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 8002d2c: 687b ldr r3, [r7, #4] 8002d2e: 6a9b ldr r3, [r3, #40] ; 0x28 8002d30: 6878 ldr r0, [r7, #4] 8002d32: 4798 blx r3 if(hdma->XferCpltCallback != NULL) 8002d34: e02f b.n 8002d96 } } /* Transfer Error Interrupt management **************************************/ else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE))) 8002d36: 687b ldr r3, [r7, #4] 8002d38: 6c1b ldr r3, [r3, #64] ; 0x40 8002d3a: 2208 movs r2, #8 8002d3c: 409a lsls r2, r3 8002d3e: 68fb ldr r3, [r7, #12] 8002d40: 4013 ands r3, r2 8002d42: 2b00 cmp r3, #0 8002d44: d028 beq.n 8002d98 8002d46: 68bb ldr r3, [r7, #8] 8002d48: f003 0308 and.w r3, r3, #8 8002d4c: 2b00 cmp r3, #0 8002d4e: d023 beq.n 8002d98 { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ /* Disable ALL DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8002d50: 687b ldr r3, [r7, #4] 8002d52: 681b ldr r3, [r3, #0] 8002d54: 681a ldr r2, [r3, #0] 8002d56: 687b ldr r3, [r7, #4] 8002d58: 681b ldr r3, [r3, #0] 8002d5a: f022 020e bic.w r2, r2, #14 8002d5e: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); 8002d60: 687b ldr r3, [r7, #4] 8002d62: 6c1a ldr r2, [r3, #64] ; 0x40 8002d64: 687b ldr r3, [r7, #4] 8002d66: 6bdb ldr r3, [r3, #60] ; 0x3c 8002d68: 2101 movs r1, #1 8002d6a: fa01 f202 lsl.w r2, r1, r2 8002d6e: 605a str r2, [r3, #4] /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; 8002d70: 687b ldr r3, [r7, #4] 8002d72: 2201 movs r2, #1 8002d74: 639a str r2, [r3, #56] ; 0x38 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8002d76: 687b ldr r3, [r7, #4] 8002d78: 2201 movs r2, #1 8002d7a: f883 2021 strb.w r2, [r3, #33] ; 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8002d7e: 687b ldr r3, [r7, #4] 8002d80: 2200 movs r2, #0 8002d82: f883 2020 strb.w r2, [r3, #32] if (hdma->XferErrorCallback != NULL) 8002d86: 687b ldr r3, [r7, #4] 8002d88: 6b1b ldr r3, [r3, #48] ; 0x30 8002d8a: 2b00 cmp r3, #0 8002d8c: d004 beq.n 8002d98 { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 8002d8e: 687b ldr r3, [r7, #4] 8002d90: 6b1b ldr r3, [r3, #48] ; 0x30 8002d92: 6878 ldr r0, [r7, #4] 8002d94: 4798 blx r3 } } return; 8002d96: bf00 nop 8002d98: bf00 nop } 8002d9a: 3710 adds r7, #16 8002d9c: 46bd mov sp, r7 8002d9e: bd80 pop {r7, pc} 8002da0: 40020008 .word 0x40020008 8002da4: 4002001c .word 0x4002001c 8002da8: 40020030 .word 0x40020030 8002dac: 40020044 .word 0x40020044 8002db0: 40020058 .word 0x40020058 8002db4: 4002006c .word 0x4002006c 8002db8: 40020000 .word 0x40020000 08002dbc : * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval HAL status */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 8002dbc: b480 push {r7} 8002dbe: b085 sub sp, #20 8002dc0: af00 add r7, sp, #0 8002dc2: 60f8 str r0, [r7, #12] 8002dc4: 60b9 str r1, [r7, #8] 8002dc6: 607a str r2, [r7, #4] 8002dc8: 603b str r3, [r7, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); 8002dca: 68fb ldr r3, [r7, #12] 8002dcc: 6c1a ldr r2, [r3, #64] ; 0x40 8002dce: 68fb ldr r3, [r7, #12] 8002dd0: 6bdb ldr r3, [r3, #60] ; 0x3c 8002dd2: 2101 movs r1, #1 8002dd4: fa01 f202 lsl.w r2, r1, r2 8002dd8: 605a str r2, [r3, #4] /* Configure DMA Channel data length */ hdma->Instance->CNDTR = DataLength; 8002dda: 68fb ldr r3, [r7, #12] 8002ddc: 681b ldr r3, [r3, #0] 8002dde: 683a ldr r2, [r7, #0] 8002de0: 605a str r2, [r3, #4] /* Memory to Peripheral */ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 8002de2: 68fb ldr r3, [r7, #12] 8002de4: 685b ldr r3, [r3, #4] 8002de6: 2b10 cmp r3, #16 8002de8: d108 bne.n 8002dfc { /* Configure DMA Channel destination address */ hdma->Instance->CPAR = DstAddress; 8002dea: 68fb ldr r3, [r7, #12] 8002dec: 681b ldr r3, [r3, #0] 8002dee: 687a ldr r2, [r7, #4] 8002df0: 609a str r2, [r3, #8] /* Configure DMA Channel source address */ hdma->Instance->CMAR = SrcAddress; 8002df2: 68fb ldr r3, [r7, #12] 8002df4: 681b ldr r3, [r3, #0] 8002df6: 68ba ldr r2, [r7, #8] 8002df8: 60da str r2, [r3, #12] hdma->Instance->CPAR = SrcAddress; /* Configure DMA Channel destination address */ hdma->Instance->CMAR = DstAddress; } } 8002dfa: e007 b.n 8002e0c hdma->Instance->CPAR = SrcAddress; 8002dfc: 68fb ldr r3, [r7, #12] 8002dfe: 681b ldr r3, [r3, #0] 8002e00: 68ba ldr r2, [r7, #8] 8002e02: 609a str r2, [r3, #8] hdma->Instance->CMAR = DstAddress; 8002e04: 68fb ldr r3, [r7, #12] 8002e06: 681b ldr r3, [r3, #0] 8002e08: 687a ldr r2, [r7, #4] 8002e0a: 60da str r2, [r3, #12] } 8002e0c: bf00 nop 8002e0e: 3714 adds r7, #20 8002e10: 46bd mov sp, r7 8002e12: bc80 pop {r7} 8002e14: 4770 bx lr ... 08002e18 : * @param Data: Specifies the data to be programmed * * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) { 8002e18: b5f0 push {r4, r5, r6, r7, lr} 8002e1a: b087 sub sp, #28 8002e1c: af00 add r7, sp, #0 8002e1e: 60f8 str r0, [r7, #12] 8002e20: 60b9 str r1, [r7, #8] 8002e22: e9c7 2300 strd r2, r3, [r7] HAL_StatusTypeDef status = HAL_ERROR; 8002e26: 2301 movs r3, #1 8002e28: 75fb strb r3, [r7, #23] uint8_t index = 0; 8002e2a: 2300 movs r3, #0 8002e2c: 75bb strb r3, [r7, #22] uint8_t nbiterations = 0; 8002e2e: 2300 movs r3, #0 8002e30: 757b strb r3, [r7, #21] /* Process Locked */ __HAL_LOCK(&pFlash); 8002e32: 4b2f ldr r3, [pc, #188] ; (8002ef0 ) 8002e34: 7e1b ldrb r3, [r3, #24] 8002e36: 2b01 cmp r3, #1 8002e38: d101 bne.n 8002e3e 8002e3a: 2302 movs r3, #2 8002e3c: e054 b.n 8002ee8 8002e3e: 4b2c ldr r3, [pc, #176] ; (8002ef0 ) 8002e40: 2201 movs r2, #1 8002e42: 761a strb r2, [r3, #24] #if defined(FLASH_BANK2_END) if(Address <= FLASH_BANK1_END) { #endif /* FLASH_BANK2_END */ /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); 8002e44: f24c 3050 movw r0, #50000 ; 0xc350 8002e48: f000 f8a8 bl 8002f9c 8002e4c: 4603 mov r3, r0 8002e4e: 75fb strb r3, [r7, #23] /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperationBank2(FLASH_TIMEOUT_VALUE); } #endif /* FLASH_BANK2_END */ if(status == HAL_OK) 8002e50: 7dfb ldrb r3, [r7, #23] 8002e52: 2b00 cmp r3, #0 8002e54: d144 bne.n 8002ee0 { if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) 8002e56: 68fb ldr r3, [r7, #12] 8002e58: 2b01 cmp r3, #1 8002e5a: d102 bne.n 8002e62 { /* Program halfword (16-bit) at a specified address. */ nbiterations = 1U; 8002e5c: 2301 movs r3, #1 8002e5e: 757b strb r3, [r7, #21] 8002e60: e007 b.n 8002e72 } else if(TypeProgram == FLASH_TYPEPROGRAM_WORD) 8002e62: 68fb ldr r3, [r7, #12] 8002e64: 2b02 cmp r3, #2 8002e66: d102 bne.n 8002e6e { /* Program word (32-bit = 2*16-bit) at a specified address. */ nbiterations = 2U; 8002e68: 2302 movs r3, #2 8002e6a: 757b strb r3, [r7, #21] 8002e6c: e001 b.n 8002e72 } else { /* Program double word (64-bit = 4*16-bit) at a specified address. */ nbiterations = 4U; 8002e6e: 2304 movs r3, #4 8002e70: 757b strb r3, [r7, #21] } for (index = 0U; index < nbiterations; index++) 8002e72: 2300 movs r3, #0 8002e74: 75bb strb r3, [r7, #22] 8002e76: e02d b.n 8002ed4 { FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index))); 8002e78: 7dbb ldrb r3, [r7, #22] 8002e7a: 005a lsls r2, r3, #1 8002e7c: 68bb ldr r3, [r7, #8] 8002e7e: eb02 0c03 add.w ip, r2, r3 8002e82: 7dbb ldrb r3, [r7, #22] 8002e84: 0119 lsls r1, r3, #4 8002e86: e9d7 2300 ldrd r2, r3, [r7] 8002e8a: f1c1 0620 rsb r6, r1, #32 8002e8e: f1a1 0020 sub.w r0, r1, #32 8002e92: fa22 f401 lsr.w r4, r2, r1 8002e96: fa03 f606 lsl.w r6, r3, r6 8002e9a: 4334 orrs r4, r6 8002e9c: fa23 f000 lsr.w r0, r3, r0 8002ea0: 4304 orrs r4, r0 8002ea2: fa23 f501 lsr.w r5, r3, r1 8002ea6: b2a3 uxth r3, r4 8002ea8: 4619 mov r1, r3 8002eaa: 4660 mov r0, ip 8002eac: f000 f85a bl 8002f64 #if defined(FLASH_BANK2_END) if(Address <= FLASH_BANK1_END) { #endif /* FLASH_BANK2_END */ /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); 8002eb0: f24c 3050 movw r0, #50000 ; 0xc350 8002eb4: f000 f872 bl 8002f9c 8002eb8: 4603 mov r3, r0 8002eba: 75fb strb r3, [r7, #23] /* If the program operation is completed, disable the PG Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_PG); 8002ebc: 4b0d ldr r3, [pc, #52] ; (8002ef4 ) 8002ebe: 691b ldr r3, [r3, #16] 8002ec0: 4a0c ldr r2, [pc, #48] ; (8002ef4 ) 8002ec2: f023 0301 bic.w r3, r3, #1 8002ec6: 6113 str r3, [r2, #16] /* If the program operation is completed, disable the PG Bit */ CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG); } #endif /* FLASH_BANK2_END */ /* In case of error, stop programation procedure */ if (status != HAL_OK) 8002ec8: 7dfb ldrb r3, [r7, #23] 8002eca: 2b00 cmp r3, #0 8002ecc: d107 bne.n 8002ede for (index = 0U; index < nbiterations; index++) 8002ece: 7dbb ldrb r3, [r7, #22] 8002ed0: 3301 adds r3, #1 8002ed2: 75bb strb r3, [r7, #22] 8002ed4: 7dba ldrb r2, [r7, #22] 8002ed6: 7d7b ldrb r3, [r7, #21] 8002ed8: 429a cmp r2, r3 8002eda: d3cd bcc.n 8002e78 8002edc: e000 b.n 8002ee0 { break; 8002ede: bf00 nop } } } /* Process Unlocked */ __HAL_UNLOCK(&pFlash); 8002ee0: 4b03 ldr r3, [pc, #12] ; (8002ef0 ) 8002ee2: 2200 movs r2, #0 8002ee4: 761a strb r2, [r3, #24] return status; 8002ee6: 7dfb ldrb r3, [r7, #23] } 8002ee8: 4618 mov r0, r3 8002eea: 371c adds r7, #28 8002eec: 46bd mov sp, r7 8002eee: bdf0 pop {r4, r5, r6, r7, pc} 8002ef0: 200007c0 .word 0x200007c0 8002ef4: 40022000 .word 0x40022000 08002ef8 : /** * @brief Unlock the FLASH control register access * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_Unlock(void) { 8002ef8: b480 push {r7} 8002efa: b083 sub sp, #12 8002efc: af00 add r7, sp, #0 HAL_StatusTypeDef status = HAL_OK; 8002efe: 2300 movs r3, #0 8002f00: 71fb strb r3, [r7, #7] if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) 8002f02: 4b0d ldr r3, [pc, #52] ; (8002f38 ) 8002f04: 691b ldr r3, [r3, #16] 8002f06: f003 0380 and.w r3, r3, #128 ; 0x80 8002f0a: 2b00 cmp r3, #0 8002f0c: d00d beq.n 8002f2a { /* Authorize the FLASH Registers access */ WRITE_REG(FLASH->KEYR, FLASH_KEY1); 8002f0e: 4b0a ldr r3, [pc, #40] ; (8002f38 ) 8002f10: 4a0a ldr r2, [pc, #40] ; (8002f3c ) 8002f12: 605a str r2, [r3, #4] WRITE_REG(FLASH->KEYR, FLASH_KEY2); 8002f14: 4b08 ldr r3, [pc, #32] ; (8002f38 ) 8002f16: 4a0a ldr r2, [pc, #40] ; (8002f40 ) 8002f18: 605a str r2, [r3, #4] /* Verify Flash is unlocked */ if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) 8002f1a: 4b07 ldr r3, [pc, #28] ; (8002f38 ) 8002f1c: 691b ldr r3, [r3, #16] 8002f1e: f003 0380 and.w r3, r3, #128 ; 0x80 8002f22: 2b00 cmp r3, #0 8002f24: d001 beq.n 8002f2a { status = HAL_ERROR; 8002f26: 2301 movs r3, #1 8002f28: 71fb strb r3, [r7, #7] status = HAL_ERROR; } } #endif /* FLASH_BANK2_END */ return status; 8002f2a: 79fb ldrb r3, [r7, #7] } 8002f2c: 4618 mov r0, r3 8002f2e: 370c adds r7, #12 8002f30: 46bd mov sp, r7 8002f32: bc80 pop {r7} 8002f34: 4770 bx lr 8002f36: bf00 nop 8002f38: 40022000 .word 0x40022000 8002f3c: 45670123 .word 0x45670123 8002f40: cdef89ab .word 0xcdef89ab 08002f44 : /** * @brief Locks the FLASH control register access * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_Lock(void) { 8002f44: b480 push {r7} 8002f46: af00 add r7, sp, #0 /* Set the LOCK Bit to lock the FLASH Registers access */ SET_BIT(FLASH->CR, FLASH_CR_LOCK); 8002f48: 4b05 ldr r3, [pc, #20] ; (8002f60 ) 8002f4a: 691b ldr r3, [r3, #16] 8002f4c: 4a04 ldr r2, [pc, #16] ; (8002f60 ) 8002f4e: f043 0380 orr.w r3, r3, #128 ; 0x80 8002f52: 6113 str r3, [r2, #16] #if defined(FLASH_BANK2_END) /* Set the LOCK Bit to lock the FLASH BANK2 Registers access */ SET_BIT(FLASH->CR2, FLASH_CR2_LOCK); #endif /* FLASH_BANK2_END */ return HAL_OK; 8002f54: 2300 movs r3, #0 } 8002f56: 4618 mov r0, r3 8002f58: 46bd mov sp, r7 8002f5a: bc80 pop {r7} 8002f5c: 4770 bx lr 8002f5e: bf00 nop 8002f60: 40022000 .word 0x40022000 08002f64 : * @param Address specify the address to be programmed. * @param Data specify the data to be programmed. * @retval None */ static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) { 8002f64: b480 push {r7} 8002f66: b083 sub sp, #12 8002f68: af00 add r7, sp, #0 8002f6a: 6078 str r0, [r7, #4] 8002f6c: 460b mov r3, r1 8002f6e: 807b strh r3, [r7, #2] /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; 8002f70: 4b08 ldr r3, [pc, #32] ; (8002f94 ) 8002f72: 2200 movs r2, #0 8002f74: 61da str r2, [r3, #28] #if defined(FLASH_BANK2_END) if(Address <= FLASH_BANK1_END) { #endif /* FLASH_BANK2_END */ /* Proceed to program the new data */ SET_BIT(FLASH->CR, FLASH_CR_PG); 8002f76: 4b08 ldr r3, [pc, #32] ; (8002f98 ) 8002f78: 691b ldr r3, [r3, #16] 8002f7a: 4a07 ldr r2, [pc, #28] ; (8002f98 ) 8002f7c: f043 0301 orr.w r3, r3, #1 8002f80: 6113 str r3, [r2, #16] SET_BIT(FLASH->CR2, FLASH_CR2_PG); } #endif /* FLASH_BANK2_END */ /* Write data in the address */ *(__IO uint16_t*)Address = Data; 8002f82: 687b ldr r3, [r7, #4] 8002f84: 887a ldrh r2, [r7, #2] 8002f86: 801a strh r2, [r3, #0] } 8002f88: bf00 nop 8002f8a: 370c adds r7, #12 8002f8c: 46bd mov sp, r7 8002f8e: bc80 pop {r7} 8002f90: 4770 bx lr 8002f92: bf00 nop 8002f94: 200007c0 .word 0x200007c0 8002f98: 40022000 .word 0x40022000 08002f9c : * @brief Wait for a FLASH operation to complete. * @param Timeout maximum flash operation timeout * @retval HAL Status */ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) { 8002f9c: b580 push {r7, lr} 8002f9e: b084 sub sp, #16 8002fa0: af00 add r7, sp, #0 8002fa2: 6078 str r0, [r7, #4] /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. Even if the FLASH operation fails, the BUSY flag will be reset and an error flag will be set */ uint32_t tickstart = HAL_GetTick(); 8002fa4: f7fe fee8 bl 8001d78 8002fa8: 60f8 str r0, [r7, #12] while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) 8002faa: e010 b.n 8002fce { if (Timeout != HAL_MAX_DELAY) 8002fac: 687b ldr r3, [r7, #4] 8002fae: f1b3 3fff cmp.w r3, #4294967295 8002fb2: d00c beq.n 8002fce { if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) 8002fb4: 687b ldr r3, [r7, #4] 8002fb6: 2b00 cmp r3, #0 8002fb8: d007 beq.n 8002fca 8002fba: f7fe fedd bl 8001d78 8002fbe: 4602 mov r2, r0 8002fc0: 68fb ldr r3, [r7, #12] 8002fc2: 1ad3 subs r3, r2, r3 8002fc4: 687a ldr r2, [r7, #4] 8002fc6: 429a cmp r2, r3 8002fc8: d201 bcs.n 8002fce { return HAL_TIMEOUT; 8002fca: 2303 movs r3, #3 8002fcc: e025 b.n 800301a while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) 8002fce: 4b15 ldr r3, [pc, #84] ; (8003024 ) 8002fd0: 68db ldr r3, [r3, #12] 8002fd2: f003 0301 and.w r3, r3, #1 8002fd6: 2b00 cmp r3, #0 8002fd8: d1e8 bne.n 8002fac } } } /* Check FLASH End of Operation flag */ if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) 8002fda: 4b12 ldr r3, [pc, #72] ; (8003024 ) 8002fdc: 68db ldr r3, [r3, #12] 8002fde: f003 0320 and.w r3, r3, #32 8002fe2: 2b00 cmp r3, #0 8002fe4: d002 beq.n 8002fec { /* Clear FLASH End of Operation pending bit */ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); 8002fe6: 4b0f ldr r3, [pc, #60] ; (8003024 ) 8002fe8: 2220 movs r2, #32 8002fea: 60da str r2, [r3, #12] } if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || 8002fec: 4b0d ldr r3, [pc, #52] ; (8003024 ) 8002fee: 68db ldr r3, [r3, #12] 8002ff0: f003 0310 and.w r3, r3, #16 8002ff4: 2b00 cmp r3, #0 8002ff6: d10b bne.n 8003010 __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || 8002ff8: 4b0a ldr r3, [pc, #40] ; (8003024 ) 8002ffa: 69db ldr r3, [r3, #28] 8002ffc: f003 0301 and.w r3, r3, #1 if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || 8003000: 2b00 cmp r3, #0 8003002: d105 bne.n 8003010 __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) 8003004: 4b07 ldr r3, [pc, #28] ; (8003024 ) 8003006: 68db ldr r3, [r3, #12] 8003008: f003 0304 and.w r3, r3, #4 __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || 800300c: 2b00 cmp r3, #0 800300e: d003 beq.n 8003018 { /*Save the error code*/ FLASH_SetErrorCode(); 8003010: f000 f80a bl 8003028 return HAL_ERROR; 8003014: 2301 movs r3, #1 8003016: e000 b.n 800301a } /* There is no error flag set */ return HAL_OK; 8003018: 2300 movs r3, #0 } 800301a: 4618 mov r0, r3 800301c: 3710 adds r7, #16 800301e: 46bd mov sp, r7 8003020: bd80 pop {r7, pc} 8003022: bf00 nop 8003024: 40022000 .word 0x40022000 08003028 : /** * @brief Set the specific FLASH error flag. * @retval None */ static void FLASH_SetErrorCode(void) { 8003028: b480 push {r7} 800302a: b083 sub sp, #12 800302c: af00 add r7, sp, #0 uint32_t flags = 0U; 800302e: 2300 movs r3, #0 8003030: 607b str r3, [r7, #4] #if defined(FLASH_BANK2_END) if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2)) #else if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) 8003032: 4b23 ldr r3, [pc, #140] ; (80030c0 ) 8003034: 68db ldr r3, [r3, #12] 8003036: f003 0310 and.w r3, r3, #16 800303a: 2b00 cmp r3, #0 800303c: d009 beq.n 8003052 #endif /* FLASH_BANK2_END */ { pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; 800303e: 4b21 ldr r3, [pc, #132] ; (80030c4 ) 8003040: 69db ldr r3, [r3, #28] 8003042: f043 0302 orr.w r3, r3, #2 8003046: 4a1f ldr r2, [pc, #124] ; (80030c4 ) 8003048: 61d3 str r3, [r2, #28] #if defined(FLASH_BANK2_END) flags |= FLASH_FLAG_WRPERR | FLASH_FLAG_WRPERR_BANK2; #else flags |= FLASH_FLAG_WRPERR; 800304a: 687b ldr r3, [r7, #4] 800304c: f043 0310 orr.w r3, r3, #16 8003050: 607b str r3, [r7, #4] #endif /* FLASH_BANK2_END */ } #if defined(FLASH_BANK2_END) if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2)) #else if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) 8003052: 4b1b ldr r3, [pc, #108] ; (80030c0 ) 8003054: 68db ldr r3, [r3, #12] 8003056: f003 0304 and.w r3, r3, #4 800305a: 2b00 cmp r3, #0 800305c: d009 beq.n 8003072 #endif /* FLASH_BANK2_END */ { pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG; 800305e: 4b19 ldr r3, [pc, #100] ; (80030c4 ) 8003060: 69db ldr r3, [r3, #28] 8003062: f043 0301 orr.w r3, r3, #1 8003066: 4a17 ldr r2, [pc, #92] ; (80030c4 ) 8003068: 61d3 str r3, [r2, #28] #if defined(FLASH_BANK2_END) flags |= FLASH_FLAG_PGERR | FLASH_FLAG_PGERR_BANK2; #else flags |= FLASH_FLAG_PGERR; 800306a: 687b ldr r3, [r7, #4] 800306c: f043 0304 orr.w r3, r3, #4 8003070: 607b str r3, [r7, #4] #endif /* FLASH_BANK2_END */ } if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) 8003072: 4b13 ldr r3, [pc, #76] ; (80030c0 ) 8003074: 69db ldr r3, [r3, #28] 8003076: f003 0301 and.w r3, r3, #1 800307a: 2b00 cmp r3, #0 800307c: d00b beq.n 8003096 { pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV; 800307e: 4b11 ldr r3, [pc, #68] ; (80030c4 ) 8003080: 69db ldr r3, [r3, #28] 8003082: f043 0304 orr.w r3, r3, #4 8003086: 4a0f ldr r2, [pc, #60] ; (80030c4 ) 8003088: 61d3 str r3, [r2, #28] __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR); 800308a: 4b0d ldr r3, [pc, #52] ; (80030c0 ) 800308c: 69db ldr r3, [r3, #28] 800308e: 4a0c ldr r2, [pc, #48] ; (80030c0 ) 8003090: f023 0301 bic.w r3, r3, #1 8003094: 61d3 str r3, [r2, #28] } /* Clear FLASH error pending bits */ __HAL_FLASH_CLEAR_FLAG(flags); 8003096: 687b ldr r3, [r7, #4] 8003098: f240 1201 movw r2, #257 ; 0x101 800309c: 4293 cmp r3, r2 800309e: d106 bne.n 80030ae 80030a0: 4b07 ldr r3, [pc, #28] ; (80030c0 ) 80030a2: 69db ldr r3, [r3, #28] 80030a4: 4a06 ldr r2, [pc, #24] ; (80030c0 ) 80030a6: f023 0301 bic.w r3, r3, #1 80030aa: 61d3 str r3, [r2, #28] } 80030ac: e002 b.n 80030b4 __HAL_FLASH_CLEAR_FLAG(flags); 80030ae: 4a04 ldr r2, [pc, #16] ; (80030c0 ) 80030b0: 687b ldr r3, [r7, #4] 80030b2: 60d3 str r3, [r2, #12] } 80030b4: bf00 nop 80030b6: 370c adds r7, #12 80030b8: 46bd mov sp, r7 80030ba: bc80 pop {r7} 80030bc: 4770 bx lr 80030be: bf00 nop 80030c0: 40022000 .word 0x40022000 80030c4: 200007c0 .word 0x200007c0 080030c8 : * (0xFFFFFFFF means that all the pages have been correctly erased) * * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) { 80030c8: b580 push {r7, lr} 80030ca: b084 sub sp, #16 80030cc: af00 add r7, sp, #0 80030ce: 6078 str r0, [r7, #4] 80030d0: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_ERROR; 80030d2: 2301 movs r3, #1 80030d4: 73fb strb r3, [r7, #15] uint32_t address = 0U; 80030d6: 2300 movs r3, #0 80030d8: 60bb str r3, [r7, #8] /* Process Locked */ __HAL_LOCK(&pFlash); 80030da: 4b2f ldr r3, [pc, #188] ; (8003198 ) 80030dc: 7e1b ldrb r3, [r3, #24] 80030de: 2b01 cmp r3, #1 80030e0: d101 bne.n 80030e6 80030e2: 2302 movs r3, #2 80030e4: e053 b.n 800318e 80030e6: 4b2c ldr r3, [pc, #176] ; (8003198 ) 80030e8: 2201 movs r2, #1 80030ea: 761a strb r2, [r3, #24] /* Check the parameters */ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) 80030ec: 687b ldr r3, [r7, #4] 80030ee: 681b ldr r3, [r3, #0] 80030f0: 2b02 cmp r3, #2 80030f2: d116 bne.n 8003122 else #endif /* FLASH_BANK2_END */ { /* Mass Erase requested for Bank1 */ /* Wait for last operation to be completed */ if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) 80030f4: f24c 3050 movw r0, #50000 ; 0xc350 80030f8: f7ff ff50 bl 8002f9c 80030fc: 4603 mov r3, r0 80030fe: 2b00 cmp r3, #0 8003100: d141 bne.n 8003186 { /*Mass erase to be done*/ FLASH_MassErase(FLASH_BANK_1); 8003102: 2001 movs r0, #1 8003104: f000 f84c bl 80031a0 /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); 8003108: f24c 3050 movw r0, #50000 ; 0xc350 800310c: f7ff ff46 bl 8002f9c 8003110: 4603 mov r3, r0 8003112: 73fb strb r3, [r7, #15] /* If the erase operation is completed, disable the MER Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_MER); 8003114: 4b21 ldr r3, [pc, #132] ; (800319c ) 8003116: 691b ldr r3, [r3, #16] 8003118: 4a20 ldr r2, [pc, #128] ; (800319c ) 800311a: f023 0304 bic.w r3, r3, #4 800311e: 6113 str r3, [r2, #16] 8003120: e031 b.n 8003186 else #endif /* FLASH_BANK2_END */ { /* Page Erase requested on address located on bank1 */ /* Wait for last operation to be completed */ if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) 8003122: f24c 3050 movw r0, #50000 ; 0xc350 8003126: f7ff ff39 bl 8002f9c 800312a: 4603 mov r3, r0 800312c: 2b00 cmp r3, #0 800312e: d12a bne.n 8003186 { /*Initialization of PageError variable*/ *PageError = 0xFFFFFFFFU; 8003130: 683b ldr r3, [r7, #0] 8003132: f04f 32ff mov.w r2, #4294967295 8003136: 601a str r2, [r3, #0] /* Erase page by page to be done*/ for(address = pEraseInit->PageAddress; 8003138: 687b ldr r3, [r7, #4] 800313a: 689b ldr r3, [r3, #8] 800313c: 60bb str r3, [r7, #8] 800313e: e019 b.n 8003174 address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress); address += FLASH_PAGE_SIZE) { FLASH_PageErase(address); 8003140: 68b8 ldr r0, [r7, #8] 8003142: f000 f849 bl 80031d8 /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); 8003146: f24c 3050 movw r0, #50000 ; 0xc350 800314a: f7ff ff27 bl 8002f9c 800314e: 4603 mov r3, r0 8003150: 73fb strb r3, [r7, #15] /* If the erase operation is completed, disable the PER Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_PER); 8003152: 4b12 ldr r3, [pc, #72] ; (800319c ) 8003154: 691b ldr r3, [r3, #16] 8003156: 4a11 ldr r2, [pc, #68] ; (800319c ) 8003158: f023 0302 bic.w r3, r3, #2 800315c: 6113 str r3, [r2, #16] if (status != HAL_OK) 800315e: 7bfb ldrb r3, [r7, #15] 8003160: 2b00 cmp r3, #0 8003162: d003 beq.n 800316c { /* In case of error, stop erase procedure and return the faulty address */ *PageError = address; 8003164: 683b ldr r3, [r7, #0] 8003166: 68ba ldr r2, [r7, #8] 8003168: 601a str r2, [r3, #0] break; 800316a: e00c b.n 8003186 address += FLASH_PAGE_SIZE) 800316c: 68bb ldr r3, [r7, #8] 800316e: f503 6380 add.w r3, r3, #1024 ; 0x400 8003172: 60bb str r3, [r7, #8] address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress); 8003174: 687b ldr r3, [r7, #4] 8003176: 68db ldr r3, [r3, #12] 8003178: 029a lsls r2, r3, #10 800317a: 687b ldr r3, [r7, #4] 800317c: 689b ldr r3, [r3, #8] 800317e: 4413 add r3, r2 for(address = pEraseInit->PageAddress; 8003180: 68ba ldr r2, [r7, #8] 8003182: 429a cmp r2, r3 8003184: d3dc bcc.n 8003140 } } } /* Process Unlocked */ __HAL_UNLOCK(&pFlash); 8003186: 4b04 ldr r3, [pc, #16] ; (8003198 ) 8003188: 2200 movs r2, #0 800318a: 761a strb r2, [r3, #24] return status; 800318c: 7bfb ldrb r3, [r7, #15] } 800318e: 4618 mov r0, r3 8003190: 3710 adds r7, #16 8003192: 46bd mov sp, r7 8003194: bd80 pop {r7, pc} 8003196: bf00 nop 8003198: 200007c0 .word 0x200007c0 800319c: 40022000 .word 0x40022000 080031a0 : @endif * * @retval None */ static void FLASH_MassErase(uint32_t Banks) { 80031a0: b480 push {r7} 80031a2: b083 sub sp, #12 80031a4: af00 add r7, sp, #0 80031a6: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_FLASH_BANK(Banks)); /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; 80031a8: 4b09 ldr r3, [pc, #36] ; (80031d0 ) 80031aa: 2200 movs r2, #0 80031ac: 61da str r2, [r3, #28] #if !defined(FLASH_BANK2_END) /* Prevent unused argument(s) compilation warning */ UNUSED(Banks); #endif /* FLASH_BANK2_END */ /* Only bank1 will be erased*/ SET_BIT(FLASH->CR, FLASH_CR_MER); 80031ae: 4b09 ldr r3, [pc, #36] ; (80031d4 ) 80031b0: 691b ldr r3, [r3, #16] 80031b2: 4a08 ldr r2, [pc, #32] ; (80031d4 ) 80031b4: f043 0304 orr.w r3, r3, #4 80031b8: 6113 str r3, [r2, #16] SET_BIT(FLASH->CR, FLASH_CR_STRT); 80031ba: 4b06 ldr r3, [pc, #24] ; (80031d4 ) 80031bc: 691b ldr r3, [r3, #16] 80031be: 4a05 ldr r2, [pc, #20] ; (80031d4 ) 80031c0: f043 0340 orr.w r3, r3, #64 ; 0x40 80031c4: 6113 str r3, [r2, #16] #if defined(FLASH_BANK2_END) } #endif /* FLASH_BANK2_END */ } 80031c6: bf00 nop 80031c8: 370c adds r7, #12 80031ca: 46bd mov sp, r7 80031cc: bc80 pop {r7} 80031ce: 4770 bx lr 80031d0: 200007c0 .word 0x200007c0 80031d4: 40022000 .word 0x40022000 080031d8 : * The value of this parameter depend on device used within the same series * * @retval None */ void FLASH_PageErase(uint32_t PageAddress) { 80031d8: b480 push {r7} 80031da: b083 sub sp, #12 80031dc: af00 add r7, sp, #0 80031de: 6078 str r0, [r7, #4] /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; 80031e0: 4b0b ldr r3, [pc, #44] ; (8003210 ) 80031e2: 2200 movs r2, #0 80031e4: 61da str r2, [r3, #28] } else { #endif /* FLASH_BANK2_END */ /* Proceed to erase the page */ SET_BIT(FLASH->CR, FLASH_CR_PER); 80031e6: 4b0b ldr r3, [pc, #44] ; (8003214 ) 80031e8: 691b ldr r3, [r3, #16] 80031ea: 4a0a ldr r2, [pc, #40] ; (8003214 ) 80031ec: f043 0302 orr.w r3, r3, #2 80031f0: 6113 str r3, [r2, #16] WRITE_REG(FLASH->AR, PageAddress); 80031f2: 4a08 ldr r2, [pc, #32] ; (8003214 ) 80031f4: 687b ldr r3, [r7, #4] 80031f6: 6153 str r3, [r2, #20] SET_BIT(FLASH->CR, FLASH_CR_STRT); 80031f8: 4b06 ldr r3, [pc, #24] ; (8003214 ) 80031fa: 691b ldr r3, [r3, #16] 80031fc: 4a05 ldr r2, [pc, #20] ; (8003214 ) 80031fe: f043 0340 orr.w r3, r3, #64 ; 0x40 8003202: 6113 str r3, [r2, #16] #if defined(FLASH_BANK2_END) } #endif /* FLASH_BANK2_END */ } 8003204: bf00 nop 8003206: 370c adds r7, #12 8003208: 46bd mov sp, r7 800320a: bc80 pop {r7} 800320c: 4770 bx lr 800320e: bf00 nop 8003210: 200007c0 .word 0x200007c0 8003214: 40022000 .word 0x40022000 08003218 : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8003218: b480 push {r7} 800321a: b08b sub sp, #44 ; 0x2c 800321c: af00 add r7, sp, #0 800321e: 6078 str r0, [r7, #4] 8003220: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 8003222: 2300 movs r3, #0 8003224: 627b str r3, [r7, #36] ; 0x24 uint32_t ioposition; uint32_t iocurrent; uint32_t temp; uint32_t config = 0x00u; 8003226: 2300 movs r3, #0 8003228: 623b str r3, [r7, #32] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 800322a: e127 b.n 800347c { /* Get the IO position */ ioposition = (0x01uL << position); 800322c: 2201 movs r2, #1 800322e: 6a7b ldr r3, [r7, #36] ; 0x24 8003230: fa02 f303 lsl.w r3, r2, r3 8003234: 61fb str r3, [r7, #28] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 8003236: 683b ldr r3, [r7, #0] 8003238: 681b ldr r3, [r3, #0] 800323a: 69fa ldr r2, [r7, #28] 800323c: 4013 ands r3, r2 800323e: 61bb str r3, [r7, #24] if (iocurrent == ioposition) 8003240: 69ba ldr r2, [r7, #24] 8003242: 69fb ldr r3, [r7, #28] 8003244: 429a cmp r2, r3 8003246: f040 8116 bne.w 8003476 { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ switch (GPIO_Init->Mode) 800324a: 683b ldr r3, [r7, #0] 800324c: 685b ldr r3, [r3, #4] 800324e: 2b12 cmp r3, #18 8003250: d034 beq.n 80032bc 8003252: 2b12 cmp r3, #18 8003254: d80d bhi.n 8003272 8003256: 2b02 cmp r3, #2 8003258: d02b beq.n 80032b2 800325a: 2b02 cmp r3, #2 800325c: d804 bhi.n 8003268 800325e: 2b00 cmp r3, #0 8003260: d031 beq.n 80032c6 8003262: 2b01 cmp r3, #1 8003264: d01c beq.n 80032a0 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; break; /* Parameters are checked with assert_param */ default: break; 8003266: e048 b.n 80032fa switch (GPIO_Init->Mode) 8003268: 2b03 cmp r3, #3 800326a: d043 beq.n 80032f4 800326c: 2b11 cmp r3, #17 800326e: d01b beq.n 80032a8 break; 8003270: e043 b.n 80032fa switch (GPIO_Init->Mode) 8003272: 4a89 ldr r2, [pc, #548] ; (8003498 ) 8003274: 4293 cmp r3, r2 8003276: d026 beq.n 80032c6 8003278: 4a87 ldr r2, [pc, #540] ; (8003498 ) 800327a: 4293 cmp r3, r2 800327c: d806 bhi.n 800328c 800327e: 4a87 ldr r2, [pc, #540] ; (800349c ) 8003280: 4293 cmp r3, r2 8003282: d020 beq.n 80032c6 8003284: 4a86 ldr r2, [pc, #536] ; (80034a0 ) 8003286: 4293 cmp r3, r2 8003288: d01d beq.n 80032c6 break; 800328a: e036 b.n 80032fa switch (GPIO_Init->Mode) 800328c: 4a85 ldr r2, [pc, #532] ; (80034a4 ) 800328e: 4293 cmp r3, r2 8003290: d019 beq.n 80032c6 8003292: 4a85 ldr r2, [pc, #532] ; (80034a8 ) 8003294: 4293 cmp r3, r2 8003296: d016 beq.n 80032c6 8003298: 4a84 ldr r2, [pc, #528] ; (80034ac ) 800329a: 4293 cmp r3, r2 800329c: d013 beq.n 80032c6 break; 800329e: e02c b.n 80032fa config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; 80032a0: 683b ldr r3, [r7, #0] 80032a2: 68db ldr r3, [r3, #12] 80032a4: 623b str r3, [r7, #32] break; 80032a6: e028 b.n 80032fa config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; 80032a8: 683b ldr r3, [r7, #0] 80032aa: 68db ldr r3, [r3, #12] 80032ac: 3304 adds r3, #4 80032ae: 623b str r3, [r7, #32] break; 80032b0: e023 b.n 80032fa config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; 80032b2: 683b ldr r3, [r7, #0] 80032b4: 68db ldr r3, [r3, #12] 80032b6: 3308 adds r3, #8 80032b8: 623b str r3, [r7, #32] break; 80032ba: e01e b.n 80032fa config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; 80032bc: 683b ldr r3, [r7, #0] 80032be: 68db ldr r3, [r3, #12] 80032c0: 330c adds r3, #12 80032c2: 623b str r3, [r7, #32] break; 80032c4: e019 b.n 80032fa if (GPIO_Init->Pull == GPIO_NOPULL) 80032c6: 683b ldr r3, [r7, #0] 80032c8: 689b ldr r3, [r3, #8] 80032ca: 2b00 cmp r3, #0 80032cc: d102 bne.n 80032d4 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; 80032ce: 2304 movs r3, #4 80032d0: 623b str r3, [r7, #32] break; 80032d2: e012 b.n 80032fa else if (GPIO_Init->Pull == GPIO_PULLUP) 80032d4: 683b ldr r3, [r7, #0] 80032d6: 689b ldr r3, [r3, #8] 80032d8: 2b01 cmp r3, #1 80032da: d105 bne.n 80032e8 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 80032dc: 2308 movs r3, #8 80032de: 623b str r3, [r7, #32] GPIOx->BSRR = ioposition; 80032e0: 687b ldr r3, [r7, #4] 80032e2: 69fa ldr r2, [r7, #28] 80032e4: 611a str r2, [r3, #16] break; 80032e6: e008 b.n 80032fa config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 80032e8: 2308 movs r3, #8 80032ea: 623b str r3, [r7, #32] GPIOx->BRR = ioposition; 80032ec: 687b ldr r3, [r7, #4] 80032ee: 69fa ldr r2, [r7, #28] 80032f0: 615a str r2, [r3, #20] break; 80032f2: e002 b.n 80032fa config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; 80032f4: 2300 movs r3, #0 80032f6: 623b str r3, [r7, #32] break; 80032f8: bf00 nop } /* Check if the current bit belongs to first half or last half of the pin count number in order to address CRH or CRL register*/ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; 80032fa: 69bb ldr r3, [r7, #24] 80032fc: 2bff cmp r3, #255 ; 0xff 80032fe: d801 bhi.n 8003304 8003300: 687b ldr r3, [r7, #4] 8003302: e001 b.n 8003308 8003304: 687b ldr r3, [r7, #4] 8003306: 3304 adds r3, #4 8003308: 617b str r3, [r7, #20] registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); 800330a: 69bb ldr r3, [r7, #24] 800330c: 2bff cmp r3, #255 ; 0xff 800330e: d802 bhi.n 8003316 8003310: 6a7b ldr r3, [r7, #36] ; 0x24 8003312: 009b lsls r3, r3, #2 8003314: e002 b.n 800331c 8003316: 6a7b ldr r3, [r7, #36] ; 0x24 8003318: 3b08 subs r3, #8 800331a: 009b lsls r3, r3, #2 800331c: 613b str r3, [r7, #16] /* Apply the new configuration of the pin to the register */ MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); 800331e: 697b ldr r3, [r7, #20] 8003320: 681a ldr r2, [r3, #0] 8003322: 210f movs r1, #15 8003324: 693b ldr r3, [r7, #16] 8003326: fa01 f303 lsl.w r3, r1, r3 800332a: 43db mvns r3, r3 800332c: 401a ands r2, r3 800332e: 6a39 ldr r1, [r7, #32] 8003330: 693b ldr r3, [r7, #16] 8003332: fa01 f303 lsl.w r3, r1, r3 8003336: 431a orrs r2, r3 8003338: 697b ldr r3, [r7, #20] 800333a: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 800333c: 683b ldr r3, [r7, #0] 800333e: 685b ldr r3, [r3, #4] 8003340: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8003344: 2b00 cmp r3, #0 8003346: f000 8096 beq.w 8003476 { /* Enable AFIO Clock */ __HAL_RCC_AFIO_CLK_ENABLE(); 800334a: 4b59 ldr r3, [pc, #356] ; (80034b0 ) 800334c: 699b ldr r3, [r3, #24] 800334e: 4a58 ldr r2, [pc, #352] ; (80034b0 ) 8003350: f043 0301 orr.w r3, r3, #1 8003354: 6193 str r3, [r2, #24] 8003356: 4b56 ldr r3, [pc, #344] ; (80034b0 ) 8003358: 699b ldr r3, [r3, #24] 800335a: f003 0301 and.w r3, r3, #1 800335e: 60bb str r3, [r7, #8] 8003360: 68bb ldr r3, [r7, #8] temp = AFIO->EXTICR[position >> 2u]; 8003362: 4a54 ldr r2, [pc, #336] ; (80034b4 ) 8003364: 6a7b ldr r3, [r7, #36] ; 0x24 8003366: 089b lsrs r3, r3, #2 8003368: 3302 adds r3, #2 800336a: f852 3023 ldr.w r3, [r2, r3, lsl #2] 800336e: 60fb str r3, [r7, #12] CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u))); 8003370: 6a7b ldr r3, [r7, #36] ; 0x24 8003372: f003 0303 and.w r3, r3, #3 8003376: 009b lsls r3, r3, #2 8003378: 220f movs r2, #15 800337a: fa02 f303 lsl.w r3, r2, r3 800337e: 43db mvns r3, r3 8003380: 68fa ldr r2, [r7, #12] 8003382: 4013 ands r3, r2 8003384: 60fb str r3, [r7, #12] SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u))); 8003386: 687b ldr r3, [r7, #4] 8003388: 4a4b ldr r2, [pc, #300] ; (80034b8 ) 800338a: 4293 cmp r3, r2 800338c: d013 beq.n 80033b6 800338e: 687b ldr r3, [r7, #4] 8003390: 4a4a ldr r2, [pc, #296] ; (80034bc ) 8003392: 4293 cmp r3, r2 8003394: d00d beq.n 80033b2 8003396: 687b ldr r3, [r7, #4] 8003398: 4a49 ldr r2, [pc, #292] ; (80034c0 ) 800339a: 4293 cmp r3, r2 800339c: d007 beq.n 80033ae 800339e: 687b ldr r3, [r7, #4] 80033a0: 4a48 ldr r2, [pc, #288] ; (80034c4 ) 80033a2: 4293 cmp r3, r2 80033a4: d101 bne.n 80033aa 80033a6: 2303 movs r3, #3 80033a8: e006 b.n 80033b8 80033aa: 2304 movs r3, #4 80033ac: e004 b.n 80033b8 80033ae: 2302 movs r3, #2 80033b0: e002 b.n 80033b8 80033b2: 2301 movs r3, #1 80033b4: e000 b.n 80033b8 80033b6: 2300 movs r3, #0 80033b8: 6a7a ldr r2, [r7, #36] ; 0x24 80033ba: f002 0203 and.w r2, r2, #3 80033be: 0092 lsls r2, r2, #2 80033c0: 4093 lsls r3, r2 80033c2: 68fa ldr r2, [r7, #12] 80033c4: 4313 orrs r3, r2 80033c6: 60fb str r3, [r7, #12] AFIO->EXTICR[position >> 2u] = temp; 80033c8: 493a ldr r1, [pc, #232] ; (80034b4 ) 80033ca: 6a7b ldr r3, [r7, #36] ; 0x24 80033cc: 089b lsrs r3, r3, #2 80033ce: 3302 adds r3, #2 80033d0: 68fa ldr r2, [r7, #12] 80033d2: f841 2023 str.w r2, [r1, r3, lsl #2] /* Configure the interrupt mask */ if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) 80033d6: 683b ldr r3, [r7, #0] 80033d8: 685b ldr r3, [r3, #4] 80033da: f403 3380 and.w r3, r3, #65536 ; 0x10000 80033de: 2b00 cmp r3, #0 80033e0: d006 beq.n 80033f0 { SET_BIT(EXTI->IMR, iocurrent); 80033e2: 4b39 ldr r3, [pc, #228] ; (80034c8 ) 80033e4: 681a ldr r2, [r3, #0] 80033e6: 4938 ldr r1, [pc, #224] ; (80034c8 ) 80033e8: 69bb ldr r3, [r7, #24] 80033ea: 4313 orrs r3, r2 80033ec: 600b str r3, [r1, #0] 80033ee: e006 b.n 80033fe } else { CLEAR_BIT(EXTI->IMR, iocurrent); 80033f0: 4b35 ldr r3, [pc, #212] ; (80034c8 ) 80033f2: 681a ldr r2, [r3, #0] 80033f4: 69bb ldr r3, [r7, #24] 80033f6: 43db mvns r3, r3 80033f8: 4933 ldr r1, [pc, #204] ; (80034c8 ) 80033fa: 4013 ands r3, r2 80033fc: 600b str r3, [r1, #0] } /* Configure the event mask */ if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) 80033fe: 683b ldr r3, [r7, #0] 8003400: 685b ldr r3, [r3, #4] 8003402: f403 3300 and.w r3, r3, #131072 ; 0x20000 8003406: 2b00 cmp r3, #0 8003408: d006 beq.n 8003418 { SET_BIT(EXTI->EMR, iocurrent); 800340a: 4b2f ldr r3, [pc, #188] ; (80034c8 ) 800340c: 685a ldr r2, [r3, #4] 800340e: 492e ldr r1, [pc, #184] ; (80034c8 ) 8003410: 69bb ldr r3, [r7, #24] 8003412: 4313 orrs r3, r2 8003414: 604b str r3, [r1, #4] 8003416: e006 b.n 8003426 } else { CLEAR_BIT(EXTI->EMR, iocurrent); 8003418: 4b2b ldr r3, [pc, #172] ; (80034c8 ) 800341a: 685a ldr r2, [r3, #4] 800341c: 69bb ldr r3, [r7, #24] 800341e: 43db mvns r3, r3 8003420: 4929 ldr r1, [pc, #164] ; (80034c8 ) 8003422: 4013 ands r3, r2 8003424: 604b str r3, [r1, #4] } /* Enable or disable the rising trigger */ if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) 8003426: 683b ldr r3, [r7, #0] 8003428: 685b ldr r3, [r3, #4] 800342a: f403 1380 and.w r3, r3, #1048576 ; 0x100000 800342e: 2b00 cmp r3, #0 8003430: d006 beq.n 8003440 { SET_BIT(EXTI->RTSR, iocurrent); 8003432: 4b25 ldr r3, [pc, #148] ; (80034c8 ) 8003434: 689a ldr r2, [r3, #8] 8003436: 4924 ldr r1, [pc, #144] ; (80034c8 ) 8003438: 69bb ldr r3, [r7, #24] 800343a: 4313 orrs r3, r2 800343c: 608b str r3, [r1, #8] 800343e: e006 b.n 800344e } else { CLEAR_BIT(EXTI->RTSR, iocurrent); 8003440: 4b21 ldr r3, [pc, #132] ; (80034c8 ) 8003442: 689a ldr r2, [r3, #8] 8003444: 69bb ldr r3, [r7, #24] 8003446: 43db mvns r3, r3 8003448: 491f ldr r1, [pc, #124] ; (80034c8 ) 800344a: 4013 ands r3, r2 800344c: 608b str r3, [r1, #8] } /* Enable or disable the falling trigger */ if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) 800344e: 683b ldr r3, [r7, #0] 8003450: 685b ldr r3, [r3, #4] 8003452: f403 1300 and.w r3, r3, #2097152 ; 0x200000 8003456: 2b00 cmp r3, #0 8003458: d006 beq.n 8003468 { SET_BIT(EXTI->FTSR, iocurrent); 800345a: 4b1b ldr r3, [pc, #108] ; (80034c8 ) 800345c: 68da ldr r2, [r3, #12] 800345e: 491a ldr r1, [pc, #104] ; (80034c8 ) 8003460: 69bb ldr r3, [r7, #24] 8003462: 4313 orrs r3, r2 8003464: 60cb str r3, [r1, #12] 8003466: e006 b.n 8003476 } else { CLEAR_BIT(EXTI->FTSR, iocurrent); 8003468: 4b17 ldr r3, [pc, #92] ; (80034c8 ) 800346a: 68da ldr r2, [r3, #12] 800346c: 69bb ldr r3, [r7, #24] 800346e: 43db mvns r3, r3 8003470: 4915 ldr r1, [pc, #84] ; (80034c8 ) 8003472: 4013 ands r3, r2 8003474: 60cb str r3, [r1, #12] } } } position++; 8003476: 6a7b ldr r3, [r7, #36] ; 0x24 8003478: 3301 adds r3, #1 800347a: 627b str r3, [r7, #36] ; 0x24 while (((GPIO_Init->Pin) >> position) != 0x00u) 800347c: 683b ldr r3, [r7, #0] 800347e: 681a ldr r2, [r3, #0] 8003480: 6a7b ldr r3, [r7, #36] ; 0x24 8003482: fa22 f303 lsr.w r3, r2, r3 8003486: 2b00 cmp r3, #0 8003488: f47f aed0 bne.w 800322c } } 800348c: bf00 nop 800348e: 372c adds r7, #44 ; 0x2c 8003490: 46bd mov sp, r7 8003492: bc80 pop {r7} 8003494: 4770 bx lr 8003496: bf00 nop 8003498: 10210000 .word 0x10210000 800349c: 10110000 .word 0x10110000 80034a0: 10120000 .word 0x10120000 80034a4: 10310000 .word 0x10310000 80034a8: 10320000 .word 0x10320000 80034ac: 10220000 .word 0x10220000 80034b0: 40021000 .word 0x40021000 80034b4: 40010000 .word 0x40010000 80034b8: 40010800 .word 0x40010800 80034bc: 40010c00 .word 0x40010c00 80034c0: 40011000 .word 0x40011000 80034c4: 40011400 .word 0x40011400 80034c8: 40010400 .word 0x40010400 080034cc : * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 80034cc: b480 push {r7} 80034ce: b085 sub sp, #20 80034d0: af00 add r7, sp, #0 80034d2: 6078 str r0, [r7, #4] 80034d4: 460b mov r3, r1 80034d6: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) 80034d8: 687b ldr r3, [r7, #4] 80034da: 689a ldr r2, [r3, #8] 80034dc: 887b ldrh r3, [r7, #2] 80034de: 4013 ands r3, r2 80034e0: 2b00 cmp r3, #0 80034e2: d002 beq.n 80034ea { bitstatus = GPIO_PIN_SET; 80034e4: 2301 movs r3, #1 80034e6: 73fb strb r3, [r7, #15] 80034e8: e001 b.n 80034ee } else { bitstatus = GPIO_PIN_RESET; 80034ea: 2300 movs r3, #0 80034ec: 73fb strb r3, [r7, #15] } return bitstatus; 80034ee: 7bfb ldrb r3, [r7, #15] } 80034f0: 4618 mov r0, r3 80034f2: 3714 adds r7, #20 80034f4: 46bd mov sp, r7 80034f6: bc80 pop {r7} 80034f8: 4770 bx lr 080034fa : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 80034fa: b480 push {r7} 80034fc: b083 sub sp, #12 80034fe: af00 add r7, sp, #0 8003500: 6078 str r0, [r7, #4] 8003502: 460b mov r3, r1 8003504: 807b strh r3, [r7, #2] 8003506: 4613 mov r3, r2 8003508: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 800350a: 787b ldrb r3, [r7, #1] 800350c: 2b00 cmp r3, #0 800350e: d003 beq.n 8003518 { GPIOx->BSRR = GPIO_Pin; 8003510: 887a ldrh r2, [r7, #2] 8003512: 687b ldr r3, [r7, #4] 8003514: 611a str r2, [r3, #16] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; } } 8003516: e003 b.n 8003520 GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; 8003518: 887b ldrh r3, [r7, #2] 800351a: 041a lsls r2, r3, #16 800351c: 687b ldr r3, [r7, #4] 800351e: 611a str r2, [r3, #16] } 8003520: bf00 nop 8003522: 370c adds r7, #12 8003524: 46bd mov sp, r7 8003526: bc80 pop {r7} 8003528: 4770 bx lr 0800352a : * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral * @param GPIO_Pin: Specifies the pins to be toggled. * @retval None */ void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 800352a: b480 push {r7} 800352c: b083 sub sp, #12 800352e: af00 add r7, sp, #0 8003530: 6078 str r0, [r7, #4] 8003532: 460b mov r3, r1 8003534: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->ODR & GPIO_Pin) != 0x00u) 8003536: 687b ldr r3, [r7, #4] 8003538: 68da ldr r2, [r3, #12] 800353a: 887b ldrh r3, [r7, #2] 800353c: 4013 ands r3, r2 800353e: 2b00 cmp r3, #0 8003540: d003 beq.n 800354a { GPIOx->BRR = (uint32_t)GPIO_Pin; 8003542: 887a ldrh r2, [r7, #2] 8003544: 687b ldr r3, [r7, #4] 8003546: 615a str r2, [r3, #20] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin; } } 8003548: e002 b.n 8003550 GPIOx->BSRR = (uint32_t)GPIO_Pin; 800354a: 887a ldrh r2, [r7, #2] 800354c: 687b ldr r3, [r7, #4] 800354e: 611a str r2, [r3, #16] } 8003550: bf00 nop 8003552: 370c adds r7, #12 8003554: 46bd mov sp, r7 8003556: bc80 pop {r7} 8003558: 4770 bx lr ... 0800355c : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 800355c: b580 push {r7, lr} 800355e: b086 sub sp, #24 8003560: af00 add r7, sp, #0 8003562: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 8003564: 687b ldr r3, [r7, #4] 8003566: 2b00 cmp r3, #0 8003568: d101 bne.n 800356e { return HAL_ERROR; 800356a: 2301 movs r3, #1 800356c: e26c b.n 8003a48 /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 800356e: 687b ldr r3, [r7, #4] 8003570: 681b ldr r3, [r3, #0] 8003572: f003 0301 and.w r3, r3, #1 8003576: 2b00 cmp r3, #0 8003578: f000 8087 beq.w 800368a { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 800357c: 4b92 ldr r3, [pc, #584] ; (80037c8 ) 800357e: 685b ldr r3, [r3, #4] 8003580: f003 030c and.w r3, r3, #12 8003584: 2b04 cmp r3, #4 8003586: d00c beq.n 80035a2 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 8003588: 4b8f ldr r3, [pc, #572] ; (80037c8 ) 800358a: 685b ldr r3, [r3, #4] 800358c: f003 030c and.w r3, r3, #12 8003590: 2b08 cmp r3, #8 8003592: d112 bne.n 80035ba 8003594: 4b8c ldr r3, [pc, #560] ; (80037c8 ) 8003596: 685b ldr r3, [r3, #4] 8003598: f403 3380 and.w r3, r3, #65536 ; 0x10000 800359c: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 80035a0: d10b bne.n 80035ba { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 80035a2: 4b89 ldr r3, [pc, #548] ; (80037c8 ) 80035a4: 681b ldr r3, [r3, #0] 80035a6: f403 3300 and.w r3, r3, #131072 ; 0x20000 80035aa: 2b00 cmp r3, #0 80035ac: d06c beq.n 8003688 80035ae: 687b ldr r3, [r7, #4] 80035b0: 685b ldr r3, [r3, #4] 80035b2: 2b00 cmp r3, #0 80035b4: d168 bne.n 8003688 { return HAL_ERROR; 80035b6: 2301 movs r3, #1 80035b8: e246 b.n 8003a48 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 80035ba: 687b ldr r3, [r7, #4] 80035bc: 685b ldr r3, [r3, #4] 80035be: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 80035c2: d106 bne.n 80035d2 80035c4: 4b80 ldr r3, [pc, #512] ; (80037c8 ) 80035c6: 681b ldr r3, [r3, #0] 80035c8: 4a7f ldr r2, [pc, #508] ; (80037c8 ) 80035ca: f443 3380 orr.w r3, r3, #65536 ; 0x10000 80035ce: 6013 str r3, [r2, #0] 80035d0: e02e b.n 8003630 80035d2: 687b ldr r3, [r7, #4] 80035d4: 685b ldr r3, [r3, #4] 80035d6: 2b00 cmp r3, #0 80035d8: d10c bne.n 80035f4 80035da: 4b7b ldr r3, [pc, #492] ; (80037c8 ) 80035dc: 681b ldr r3, [r3, #0] 80035de: 4a7a ldr r2, [pc, #488] ; (80037c8 ) 80035e0: f423 3380 bic.w r3, r3, #65536 ; 0x10000 80035e4: 6013 str r3, [r2, #0] 80035e6: 4b78 ldr r3, [pc, #480] ; (80037c8 ) 80035e8: 681b ldr r3, [r3, #0] 80035ea: 4a77 ldr r2, [pc, #476] ; (80037c8 ) 80035ec: f423 2380 bic.w r3, r3, #262144 ; 0x40000 80035f0: 6013 str r3, [r2, #0] 80035f2: e01d b.n 8003630 80035f4: 687b ldr r3, [r7, #4] 80035f6: 685b ldr r3, [r3, #4] 80035f8: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 80035fc: d10c bne.n 8003618 80035fe: 4b72 ldr r3, [pc, #456] ; (80037c8 ) 8003600: 681b ldr r3, [r3, #0] 8003602: 4a71 ldr r2, [pc, #452] ; (80037c8 ) 8003604: f443 2380 orr.w r3, r3, #262144 ; 0x40000 8003608: 6013 str r3, [r2, #0] 800360a: 4b6f ldr r3, [pc, #444] ; (80037c8 ) 800360c: 681b ldr r3, [r3, #0] 800360e: 4a6e ldr r2, [pc, #440] ; (80037c8 ) 8003610: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8003614: 6013 str r3, [r2, #0] 8003616: e00b b.n 8003630 8003618: 4b6b ldr r3, [pc, #428] ; (80037c8 ) 800361a: 681b ldr r3, [r3, #0] 800361c: 4a6a ldr r2, [pc, #424] ; (80037c8 ) 800361e: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8003622: 6013 str r3, [r2, #0] 8003624: 4b68 ldr r3, [pc, #416] ; (80037c8 ) 8003626: 681b ldr r3, [r3, #0] 8003628: 4a67 ldr r2, [pc, #412] ; (80037c8 ) 800362a: f423 2380 bic.w r3, r3, #262144 ; 0x40000 800362e: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8003630: 687b ldr r3, [r7, #4] 8003632: 685b ldr r3, [r3, #4] 8003634: 2b00 cmp r3, #0 8003636: d013 beq.n 8003660 { /* Get Start Tick */ tickstart = HAL_GetTick(); 8003638: f7fe fb9e bl 8001d78 800363c: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 800363e: e008 b.n 8003652 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8003640: f7fe fb9a bl 8001d78 8003644: 4602 mov r2, r0 8003646: 693b ldr r3, [r7, #16] 8003648: 1ad3 subs r3, r2, r3 800364a: 2b64 cmp r3, #100 ; 0x64 800364c: d901 bls.n 8003652 { return HAL_TIMEOUT; 800364e: 2303 movs r3, #3 8003650: e1fa b.n 8003a48 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8003652: 4b5d ldr r3, [pc, #372] ; (80037c8 ) 8003654: 681b ldr r3, [r3, #0] 8003656: f403 3300 and.w r3, r3, #131072 ; 0x20000 800365a: 2b00 cmp r3, #0 800365c: d0f0 beq.n 8003640 800365e: e014 b.n 800368a } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8003660: f7fe fb8a bl 8001d78 8003664: 6138 str r0, [r7, #16] /* Wait till HSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8003666: e008 b.n 800367a { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8003668: f7fe fb86 bl 8001d78 800366c: 4602 mov r2, r0 800366e: 693b ldr r3, [r7, #16] 8003670: 1ad3 subs r3, r2, r3 8003672: 2b64 cmp r3, #100 ; 0x64 8003674: d901 bls.n 800367a { return HAL_TIMEOUT; 8003676: 2303 movs r3, #3 8003678: e1e6 b.n 8003a48 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 800367a: 4b53 ldr r3, [pc, #332] ; (80037c8 ) 800367c: 681b ldr r3, [r3, #0] 800367e: f403 3300 and.w r3, r3, #131072 ; 0x20000 8003682: 2b00 cmp r3, #0 8003684: d1f0 bne.n 8003668 8003686: e000 b.n 800368a if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8003688: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 800368a: 687b ldr r3, [r7, #4] 800368c: 681b ldr r3, [r3, #0] 800368e: f003 0302 and.w r3, r3, #2 8003692: 2b00 cmp r3, #0 8003694: d063 beq.n 800375e /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 8003696: 4b4c ldr r3, [pc, #304] ; (80037c8 ) 8003698: 685b ldr r3, [r3, #4] 800369a: f003 030c and.w r3, r3, #12 800369e: 2b00 cmp r3, #0 80036a0: d00b beq.n 80036ba || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) 80036a2: 4b49 ldr r3, [pc, #292] ; (80037c8 ) 80036a4: 685b ldr r3, [r3, #4] 80036a6: f003 030c and.w r3, r3, #12 80036aa: 2b08 cmp r3, #8 80036ac: d11c bne.n 80036e8 80036ae: 4b46 ldr r3, [pc, #280] ; (80037c8 ) 80036b0: 685b ldr r3, [r3, #4] 80036b2: f403 3380 and.w r3, r3, #65536 ; 0x10000 80036b6: 2b00 cmp r3, #0 80036b8: d116 bne.n 80036e8 { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 80036ba: 4b43 ldr r3, [pc, #268] ; (80037c8 ) 80036bc: 681b ldr r3, [r3, #0] 80036be: f003 0302 and.w r3, r3, #2 80036c2: 2b00 cmp r3, #0 80036c4: d005 beq.n 80036d2 80036c6: 687b ldr r3, [r7, #4] 80036c8: 691b ldr r3, [r3, #16] 80036ca: 2b01 cmp r3, #1 80036cc: d001 beq.n 80036d2 { return HAL_ERROR; 80036ce: 2301 movs r3, #1 80036d0: e1ba b.n 8003a48 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 80036d2: 4b3d ldr r3, [pc, #244] ; (80037c8 ) 80036d4: 681b ldr r3, [r3, #0] 80036d6: f023 02f8 bic.w r2, r3, #248 ; 0xf8 80036da: 687b ldr r3, [r7, #4] 80036dc: 695b ldr r3, [r3, #20] 80036de: 00db lsls r3, r3, #3 80036e0: 4939 ldr r1, [pc, #228] ; (80037c8 ) 80036e2: 4313 orrs r3, r2 80036e4: 600b str r3, [r1, #0] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 80036e6: e03a b.n 800375e } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 80036e8: 687b ldr r3, [r7, #4] 80036ea: 691b ldr r3, [r3, #16] 80036ec: 2b00 cmp r3, #0 80036ee: d020 beq.n 8003732 { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 80036f0: 4b36 ldr r3, [pc, #216] ; (80037cc ) 80036f2: 2201 movs r2, #1 80036f4: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80036f6: f7fe fb3f bl 8001d78 80036fa: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 80036fc: e008 b.n 8003710 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 80036fe: f7fe fb3b bl 8001d78 8003702: 4602 mov r2, r0 8003704: 693b ldr r3, [r7, #16] 8003706: 1ad3 subs r3, r2, r3 8003708: 2b02 cmp r3, #2 800370a: d901 bls.n 8003710 { return HAL_TIMEOUT; 800370c: 2303 movs r3, #3 800370e: e19b b.n 8003a48 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8003710: 4b2d ldr r3, [pc, #180] ; (80037c8 ) 8003712: 681b ldr r3, [r3, #0] 8003714: f003 0302 and.w r3, r3, #2 8003718: 2b00 cmp r3, #0 800371a: d0f0 beq.n 80036fe } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800371c: 4b2a ldr r3, [pc, #168] ; (80037c8 ) 800371e: 681b ldr r3, [r3, #0] 8003720: f023 02f8 bic.w r2, r3, #248 ; 0xf8 8003724: 687b ldr r3, [r7, #4] 8003726: 695b ldr r3, [r3, #20] 8003728: 00db lsls r3, r3, #3 800372a: 4927 ldr r1, [pc, #156] ; (80037c8 ) 800372c: 4313 orrs r3, r2 800372e: 600b str r3, [r1, #0] 8003730: e015 b.n 800375e } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8003732: 4b26 ldr r3, [pc, #152] ; (80037cc ) 8003734: 2200 movs r2, #0 8003736: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8003738: f7fe fb1e bl 8001d78 800373c: 6138 str r0, [r7, #16] /* Wait till HSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 800373e: e008 b.n 8003752 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8003740: f7fe fb1a bl 8001d78 8003744: 4602 mov r2, r0 8003746: 693b ldr r3, [r7, #16] 8003748: 1ad3 subs r3, r2, r3 800374a: 2b02 cmp r3, #2 800374c: d901 bls.n 8003752 { return HAL_TIMEOUT; 800374e: 2303 movs r3, #3 8003750: e17a b.n 8003a48 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8003752: 4b1d ldr r3, [pc, #116] ; (80037c8 ) 8003754: 681b ldr r3, [r3, #0] 8003756: f003 0302 and.w r3, r3, #2 800375a: 2b00 cmp r3, #0 800375c: d1f0 bne.n 8003740 } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 800375e: 687b ldr r3, [r7, #4] 8003760: 681b ldr r3, [r3, #0] 8003762: f003 0308 and.w r3, r3, #8 8003766: 2b00 cmp r3, #0 8003768: d03a beq.n 80037e0 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 800376a: 687b ldr r3, [r7, #4] 800376c: 699b ldr r3, [r3, #24] 800376e: 2b00 cmp r3, #0 8003770: d019 beq.n 80037a6 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8003772: 4b17 ldr r3, [pc, #92] ; (80037d0 ) 8003774: 2201 movs r2, #1 8003776: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8003778: f7fe fafe bl 8001d78 800377c: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 800377e: e008 b.n 8003792 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8003780: f7fe fafa bl 8001d78 8003784: 4602 mov r2, r0 8003786: 693b ldr r3, [r7, #16] 8003788: 1ad3 subs r3, r2, r3 800378a: 2b02 cmp r3, #2 800378c: d901 bls.n 8003792 { return HAL_TIMEOUT; 800378e: 2303 movs r3, #3 8003790: e15a b.n 8003a48 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8003792: 4b0d ldr r3, [pc, #52] ; (80037c8 ) 8003794: 6a5b ldr r3, [r3, #36] ; 0x24 8003796: f003 0302 and.w r3, r3, #2 800379a: 2b00 cmp r3, #0 800379c: d0f0 beq.n 8003780 } } /* To have a fully stabilized clock in the specified range, a software delay of 1ms should be added.*/ RCC_Delay(1); 800379e: 2001 movs r0, #1 80037a0: f000 fad6 bl 8003d50 80037a4: e01c b.n 80037e0 } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 80037a6: 4b0a ldr r3, [pc, #40] ; (80037d0 ) 80037a8: 2200 movs r2, #0 80037aa: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80037ac: f7fe fae4 bl 8001d78 80037b0: 6138 str r0, [r7, #16] /* Wait till LSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 80037b2: e00f b.n 80037d4 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 80037b4: f7fe fae0 bl 8001d78 80037b8: 4602 mov r2, r0 80037ba: 693b ldr r3, [r7, #16] 80037bc: 1ad3 subs r3, r2, r3 80037be: 2b02 cmp r3, #2 80037c0: d908 bls.n 80037d4 { return HAL_TIMEOUT; 80037c2: 2303 movs r3, #3 80037c4: e140 b.n 8003a48 80037c6: bf00 nop 80037c8: 40021000 .word 0x40021000 80037cc: 42420000 .word 0x42420000 80037d0: 42420480 .word 0x42420480 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 80037d4: 4b9e ldr r3, [pc, #632] ; (8003a50 ) 80037d6: 6a5b ldr r3, [r3, #36] ; 0x24 80037d8: f003 0302 and.w r3, r3, #2 80037dc: 2b00 cmp r3, #0 80037de: d1e9 bne.n 80037b4 } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 80037e0: 687b ldr r3, [r7, #4] 80037e2: 681b ldr r3, [r3, #0] 80037e4: f003 0304 and.w r3, r3, #4 80037e8: 2b00 cmp r3, #0 80037ea: f000 80a6 beq.w 800393a { FlagStatus pwrclkchanged = RESET; 80037ee: 2300 movs r3, #0 80037f0: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 80037f2: 4b97 ldr r3, [pc, #604] ; (8003a50 ) 80037f4: 69db ldr r3, [r3, #28] 80037f6: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 80037fa: 2b00 cmp r3, #0 80037fc: d10d bne.n 800381a { __HAL_RCC_PWR_CLK_ENABLE(); 80037fe: 4b94 ldr r3, [pc, #592] ; (8003a50 ) 8003800: 69db ldr r3, [r3, #28] 8003802: 4a93 ldr r2, [pc, #588] ; (8003a50 ) 8003804: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8003808: 61d3 str r3, [r2, #28] 800380a: 4b91 ldr r3, [pc, #580] ; (8003a50 ) 800380c: 69db ldr r3, [r3, #28] 800380e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8003812: 60bb str r3, [r7, #8] 8003814: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 8003816: 2301 movs r3, #1 8003818: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 800381a: 4b8e ldr r3, [pc, #568] ; (8003a54 ) 800381c: 681b ldr r3, [r3, #0] 800381e: f403 7380 and.w r3, r3, #256 ; 0x100 8003822: 2b00 cmp r3, #0 8003824: d118 bne.n 8003858 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8003826: 4b8b ldr r3, [pc, #556] ; (8003a54 ) 8003828: 681b ldr r3, [r3, #0] 800382a: 4a8a ldr r2, [pc, #552] ; (8003a54 ) 800382c: f443 7380 orr.w r3, r3, #256 ; 0x100 8003830: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8003832: f7fe faa1 bl 8001d78 8003836: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8003838: e008 b.n 800384c { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 800383a: f7fe fa9d bl 8001d78 800383e: 4602 mov r2, r0 8003840: 693b ldr r3, [r7, #16] 8003842: 1ad3 subs r3, r2, r3 8003844: 2b64 cmp r3, #100 ; 0x64 8003846: d901 bls.n 800384c { return HAL_TIMEOUT; 8003848: 2303 movs r3, #3 800384a: e0fd b.n 8003a48 while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 800384c: 4b81 ldr r3, [pc, #516] ; (8003a54 ) 800384e: 681b ldr r3, [r3, #0] 8003850: f403 7380 and.w r3, r3, #256 ; 0x100 8003854: 2b00 cmp r3, #0 8003856: d0f0 beq.n 800383a } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8003858: 687b ldr r3, [r7, #4] 800385a: 68db ldr r3, [r3, #12] 800385c: 2b01 cmp r3, #1 800385e: d106 bne.n 800386e 8003860: 4b7b ldr r3, [pc, #492] ; (8003a50 ) 8003862: 6a1b ldr r3, [r3, #32] 8003864: 4a7a ldr r2, [pc, #488] ; (8003a50 ) 8003866: f043 0301 orr.w r3, r3, #1 800386a: 6213 str r3, [r2, #32] 800386c: e02d b.n 80038ca 800386e: 687b ldr r3, [r7, #4] 8003870: 68db ldr r3, [r3, #12] 8003872: 2b00 cmp r3, #0 8003874: d10c bne.n 8003890 8003876: 4b76 ldr r3, [pc, #472] ; (8003a50 ) 8003878: 6a1b ldr r3, [r3, #32] 800387a: 4a75 ldr r2, [pc, #468] ; (8003a50 ) 800387c: f023 0301 bic.w r3, r3, #1 8003880: 6213 str r3, [r2, #32] 8003882: 4b73 ldr r3, [pc, #460] ; (8003a50 ) 8003884: 6a1b ldr r3, [r3, #32] 8003886: 4a72 ldr r2, [pc, #456] ; (8003a50 ) 8003888: f023 0304 bic.w r3, r3, #4 800388c: 6213 str r3, [r2, #32] 800388e: e01c b.n 80038ca 8003890: 687b ldr r3, [r7, #4] 8003892: 68db ldr r3, [r3, #12] 8003894: 2b05 cmp r3, #5 8003896: d10c bne.n 80038b2 8003898: 4b6d ldr r3, [pc, #436] ; (8003a50 ) 800389a: 6a1b ldr r3, [r3, #32] 800389c: 4a6c ldr r2, [pc, #432] ; (8003a50 ) 800389e: f043 0304 orr.w r3, r3, #4 80038a2: 6213 str r3, [r2, #32] 80038a4: 4b6a ldr r3, [pc, #424] ; (8003a50 ) 80038a6: 6a1b ldr r3, [r3, #32] 80038a8: 4a69 ldr r2, [pc, #420] ; (8003a50 ) 80038aa: f043 0301 orr.w r3, r3, #1 80038ae: 6213 str r3, [r2, #32] 80038b0: e00b b.n 80038ca 80038b2: 4b67 ldr r3, [pc, #412] ; (8003a50 ) 80038b4: 6a1b ldr r3, [r3, #32] 80038b6: 4a66 ldr r2, [pc, #408] ; (8003a50 ) 80038b8: f023 0301 bic.w r3, r3, #1 80038bc: 6213 str r3, [r2, #32] 80038be: 4b64 ldr r3, [pc, #400] ; (8003a50 ) 80038c0: 6a1b ldr r3, [r3, #32] 80038c2: 4a63 ldr r2, [pc, #396] ; (8003a50 ) 80038c4: f023 0304 bic.w r3, r3, #4 80038c8: 6213 str r3, [r2, #32] /* Check the LSE State */ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 80038ca: 687b ldr r3, [r7, #4] 80038cc: 68db ldr r3, [r3, #12] 80038ce: 2b00 cmp r3, #0 80038d0: d015 beq.n 80038fe { /* Get Start Tick */ tickstart = HAL_GetTick(); 80038d2: f7fe fa51 bl 8001d78 80038d6: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80038d8: e00a b.n 80038f0 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 80038da: f7fe fa4d bl 8001d78 80038de: 4602 mov r2, r0 80038e0: 693b ldr r3, [r7, #16] 80038e2: 1ad3 subs r3, r2, r3 80038e4: f241 3288 movw r2, #5000 ; 0x1388 80038e8: 4293 cmp r3, r2 80038ea: d901 bls.n 80038f0 { return HAL_TIMEOUT; 80038ec: 2303 movs r3, #3 80038ee: e0ab b.n 8003a48 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80038f0: 4b57 ldr r3, [pc, #348] ; (8003a50 ) 80038f2: 6a1b ldr r3, [r3, #32] 80038f4: f003 0302 and.w r3, r3, #2 80038f8: 2b00 cmp r3, #0 80038fa: d0ee beq.n 80038da 80038fc: e014 b.n 8003928 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 80038fe: f7fe fa3b bl 8001d78 8003902: 6138 str r0, [r7, #16] /* Wait till LSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8003904: e00a b.n 800391c { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8003906: f7fe fa37 bl 8001d78 800390a: 4602 mov r2, r0 800390c: 693b ldr r3, [r7, #16] 800390e: 1ad3 subs r3, r2, r3 8003910: f241 3288 movw r2, #5000 ; 0x1388 8003914: 4293 cmp r3, r2 8003916: d901 bls.n 800391c { return HAL_TIMEOUT; 8003918: 2303 movs r3, #3 800391a: e095 b.n 8003a48 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 800391c: 4b4c ldr r3, [pc, #304] ; (8003a50 ) 800391e: 6a1b ldr r3, [r3, #32] 8003920: f003 0302 and.w r3, r3, #2 8003924: 2b00 cmp r3, #0 8003926: d1ee bne.n 8003906 } } } /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 8003928: 7dfb ldrb r3, [r7, #23] 800392a: 2b01 cmp r3, #1 800392c: d105 bne.n 800393a { __HAL_RCC_PWR_CLK_DISABLE(); 800392e: 4b48 ldr r3, [pc, #288] ; (8003a50 ) 8003930: 69db ldr r3, [r3, #28] 8003932: 4a47 ldr r2, [pc, #284] ; (8003a50 ) 8003934: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 8003938: 61d3 str r3, [r2, #28] #endif /* RCC_CR_PLL2ON */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 800393a: 687b ldr r3, [r7, #4] 800393c: 69db ldr r3, [r3, #28] 800393e: 2b00 cmp r3, #0 8003940: f000 8081 beq.w 8003a46 { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 8003944: 4b42 ldr r3, [pc, #264] ; (8003a50 ) 8003946: 685b ldr r3, [r3, #4] 8003948: f003 030c and.w r3, r3, #12 800394c: 2b08 cmp r3, #8 800394e: d061 beq.n 8003a14 { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 8003950: 687b ldr r3, [r7, #4] 8003952: 69db ldr r3, [r3, #28] 8003954: 2b02 cmp r3, #2 8003956: d146 bne.n 80039e6 /* Check the parameters */ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8003958: 4b3f ldr r3, [pc, #252] ; (8003a58 ) 800395a: 2200 movs r2, #0 800395c: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800395e: f7fe fa0b bl 8001d78 8003962: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8003964: e008 b.n 8003978 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8003966: f7fe fa07 bl 8001d78 800396a: 4602 mov r2, r0 800396c: 693b ldr r3, [r7, #16] 800396e: 1ad3 subs r3, r2, r3 8003970: 2b02 cmp r3, #2 8003972: d901 bls.n 8003978 { return HAL_TIMEOUT; 8003974: 2303 movs r3, #3 8003976: e067 b.n 8003a48 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8003978: 4b35 ldr r3, [pc, #212] ; (8003a50 ) 800397a: 681b ldr r3, [r3, #0] 800397c: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8003980: 2b00 cmp r3, #0 8003982: d1f0 bne.n 8003966 } } /* Configure the HSE prediv factor --------------------------------*/ /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */ if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE) 8003984: 687b ldr r3, [r7, #4] 8003986: 6a1b ldr r3, [r3, #32] 8003988: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 800398c: d108 bne.n 80039a0 /* Set PREDIV1 source */ SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source); #endif /* RCC_CFGR2_PREDIV1SRC */ /* Set PREDIV1 Value */ __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); 800398e: 4b30 ldr r3, [pc, #192] ; (8003a50 ) 8003990: 6adb ldr r3, [r3, #44] ; 0x2c 8003992: f023 020f bic.w r2, r3, #15 8003996: 687b ldr r3, [r7, #4] 8003998: 689b ldr r3, [r3, #8] 800399a: 492d ldr r1, [pc, #180] ; (8003a50 ) 800399c: 4313 orrs r3, r2 800399e: 62cb str r3, [r1, #44] ; 0x2c } /* Configure the main PLL clock source and multiplication factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 80039a0: 4b2b ldr r3, [pc, #172] ; (8003a50 ) 80039a2: 685b ldr r3, [r3, #4] 80039a4: f423 1274 bic.w r2, r3, #3997696 ; 0x3d0000 80039a8: 687b ldr r3, [r7, #4] 80039aa: 6a19 ldr r1, [r3, #32] 80039ac: 687b ldr r3, [r7, #4] 80039ae: 6a5b ldr r3, [r3, #36] ; 0x24 80039b0: 430b orrs r3, r1 80039b2: 4927 ldr r1, [pc, #156] ; (8003a50 ) 80039b4: 4313 orrs r3, r2 80039b6: 604b str r3, [r1, #4] RCC_OscInitStruct->PLL.PLLMUL); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 80039b8: 4b27 ldr r3, [pc, #156] ; (8003a58 ) 80039ba: 2201 movs r2, #1 80039bc: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80039be: f7fe f9db bl 8001d78 80039c2: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 80039c4: e008 b.n 80039d8 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80039c6: f7fe f9d7 bl 8001d78 80039ca: 4602 mov r2, r0 80039cc: 693b ldr r3, [r7, #16] 80039ce: 1ad3 subs r3, r2, r3 80039d0: 2b02 cmp r3, #2 80039d2: d901 bls.n 80039d8 { return HAL_TIMEOUT; 80039d4: 2303 movs r3, #3 80039d6: e037 b.n 8003a48 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 80039d8: 4b1d ldr r3, [pc, #116] ; (8003a50 ) 80039da: 681b ldr r3, [r3, #0] 80039dc: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 80039e0: 2b00 cmp r3, #0 80039e2: d0f0 beq.n 80039c6 80039e4: e02f b.n 8003a46 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 80039e6: 4b1c ldr r3, [pc, #112] ; (8003a58 ) 80039e8: 2200 movs r2, #0 80039ea: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80039ec: f7fe f9c4 bl 8001d78 80039f0: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80039f2: e008 b.n 8003a06 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80039f4: f7fe f9c0 bl 8001d78 80039f8: 4602 mov r2, r0 80039fa: 693b ldr r3, [r7, #16] 80039fc: 1ad3 subs r3, r2, r3 80039fe: 2b02 cmp r3, #2 8003a00: d901 bls.n 8003a06 { return HAL_TIMEOUT; 8003a02: 2303 movs r3, #3 8003a04: e020 b.n 8003a48 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8003a06: 4b12 ldr r3, [pc, #72] ; (8003a50 ) 8003a08: 681b ldr r3, [r3, #0] 8003a0a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8003a0e: 2b00 cmp r3, #0 8003a10: d1f0 bne.n 80039f4 8003a12: e018 b.n 8003a46 } } else { /* Check if there is a request to disable the PLL used as System clock source */ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 8003a14: 687b ldr r3, [r7, #4] 8003a16: 69db ldr r3, [r3, #28] 8003a18: 2b01 cmp r3, #1 8003a1a: d101 bne.n 8003a20 { return HAL_ERROR; 8003a1c: 2301 movs r3, #1 8003a1e: e013 b.n 8003a48 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->CFGR; 8003a20: 4b0b ldr r3, [pc, #44] ; (8003a50 ) 8003a22: 685b ldr r3, [r3, #4] 8003a24: 60fb str r3, [r7, #12] if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8003a26: 68fb ldr r3, [r7, #12] 8003a28: f403 3280 and.w r2, r3, #65536 ; 0x10000 8003a2c: 687b ldr r3, [r7, #4] 8003a2e: 6a1b ldr r3, [r3, #32] 8003a30: 429a cmp r2, r3 8003a32: d106 bne.n 8003a42 (READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL)) 8003a34: 68fb ldr r3, [r7, #12] 8003a36: f403 1270 and.w r2, r3, #3932160 ; 0x3c0000 8003a3a: 687b ldr r3, [r7, #4] 8003a3c: 6a5b ldr r3, [r3, #36] ; 0x24 if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8003a3e: 429a cmp r2, r3 8003a40: d001 beq.n 8003a46 { return HAL_ERROR; 8003a42: 2301 movs r3, #1 8003a44: e000 b.n 8003a48 } } } } return HAL_OK; 8003a46: 2300 movs r3, #0 } 8003a48: 4618 mov r0, r3 8003a4a: 3718 adds r7, #24 8003a4c: 46bd mov sp, r7 8003a4e: bd80 pop {r7, pc} 8003a50: 40021000 .word 0x40021000 8003a54: 40007000 .word 0x40007000 8003a58: 42420060 .word 0x42420060 08003a5c : * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8003a5c: b580 push {r7, lr} 8003a5e: b084 sub sp, #16 8003a60: af00 add r7, sp, #0 8003a62: 6078 str r0, [r7, #4] 8003a64: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 8003a66: 687b ldr r3, [r7, #4] 8003a68: 2b00 cmp r3, #0 8003a6a: d101 bne.n 8003a70 { return HAL_ERROR; 8003a6c: 2301 movs r3, #1 8003a6e: e0a0 b.n 8003bb2 } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8003a70: 687b ldr r3, [r7, #4] 8003a72: 681b ldr r3, [r3, #0] 8003a74: f003 0302 and.w r3, r3, #2 8003a78: 2b00 cmp r3, #0 8003a7a: d020 beq.n 8003abe { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8003a7c: 687b ldr r3, [r7, #4] 8003a7e: 681b ldr r3, [r3, #0] 8003a80: f003 0304 and.w r3, r3, #4 8003a84: 2b00 cmp r3, #0 8003a86: d005 beq.n 8003a94 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 8003a88: 4b4c ldr r3, [pc, #304] ; (8003bbc ) 8003a8a: 685b ldr r3, [r3, #4] 8003a8c: 4a4b ldr r2, [pc, #300] ; (8003bbc ) 8003a8e: f443 63e0 orr.w r3, r3, #1792 ; 0x700 8003a92: 6053 str r3, [r2, #4] } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8003a94: 687b ldr r3, [r7, #4] 8003a96: 681b ldr r3, [r3, #0] 8003a98: f003 0308 and.w r3, r3, #8 8003a9c: 2b00 cmp r3, #0 8003a9e: d005 beq.n 8003aac { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); 8003aa0: 4b46 ldr r3, [pc, #280] ; (8003bbc ) 8003aa2: 685b ldr r3, [r3, #4] 8003aa4: 4a45 ldr r2, [pc, #276] ; (8003bbc ) 8003aa6: f443 5360 orr.w r3, r3, #14336 ; 0x3800 8003aaa: 6053 str r3, [r2, #4] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8003aac: 4b43 ldr r3, [pc, #268] ; (8003bbc ) 8003aae: 685b ldr r3, [r3, #4] 8003ab0: f023 02f0 bic.w r2, r3, #240 ; 0xf0 8003ab4: 687b ldr r3, [r7, #4] 8003ab6: 689b ldr r3, [r3, #8] 8003ab8: 4940 ldr r1, [pc, #256] ; (8003bbc ) 8003aba: 4313 orrs r3, r2 8003abc: 604b str r3, [r1, #4] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 8003abe: 687b ldr r3, [r7, #4] 8003ac0: 681b ldr r3, [r3, #0] 8003ac2: f003 0301 and.w r3, r3, #1 8003ac6: 2b00 cmp r3, #0 8003ac8: d040 beq.n 8003b4c { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8003aca: 687b ldr r3, [r7, #4] 8003acc: 685b ldr r3, [r3, #4] 8003ace: 2b01 cmp r3, #1 8003ad0: d107 bne.n 8003ae2 { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8003ad2: 4b3a ldr r3, [pc, #232] ; (8003bbc ) 8003ad4: 681b ldr r3, [r3, #0] 8003ad6: f403 3300 and.w r3, r3, #131072 ; 0x20000 8003ada: 2b00 cmp r3, #0 8003adc: d115 bne.n 8003b0a { return HAL_ERROR; 8003ade: 2301 movs r3, #1 8003ae0: e067 b.n 8003bb2 } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 8003ae2: 687b ldr r3, [r7, #4] 8003ae4: 685b ldr r3, [r3, #4] 8003ae6: 2b02 cmp r3, #2 8003ae8: d107 bne.n 8003afa { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8003aea: 4b34 ldr r3, [pc, #208] ; (8003bbc ) 8003aec: 681b ldr r3, [r3, #0] 8003aee: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8003af2: 2b00 cmp r3, #0 8003af4: d109 bne.n 8003b0a { return HAL_ERROR; 8003af6: 2301 movs r3, #1 8003af8: e05b b.n 8003bb2 } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8003afa: 4b30 ldr r3, [pc, #192] ; (8003bbc ) 8003afc: 681b ldr r3, [r3, #0] 8003afe: f003 0302 and.w r3, r3, #2 8003b02: 2b00 cmp r3, #0 8003b04: d101 bne.n 8003b0a { return HAL_ERROR; 8003b06: 2301 movs r3, #1 8003b08: e053 b.n 8003bb2 } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 8003b0a: 4b2c ldr r3, [pc, #176] ; (8003bbc ) 8003b0c: 685b ldr r3, [r3, #4] 8003b0e: f023 0203 bic.w r2, r3, #3 8003b12: 687b ldr r3, [r7, #4] 8003b14: 685b ldr r3, [r3, #4] 8003b16: 4929 ldr r1, [pc, #164] ; (8003bbc ) 8003b18: 4313 orrs r3, r2 8003b1a: 604b str r3, [r1, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); 8003b1c: f7fe f92c bl 8001d78 8003b20: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8003b22: e00a b.n 8003b3a { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8003b24: f7fe f928 bl 8001d78 8003b28: 4602 mov r2, r0 8003b2a: 68fb ldr r3, [r7, #12] 8003b2c: 1ad3 subs r3, r2, r3 8003b2e: f241 3288 movw r2, #5000 ; 0x1388 8003b32: 4293 cmp r3, r2 8003b34: d901 bls.n 8003b3a { return HAL_TIMEOUT; 8003b36: 2303 movs r3, #3 8003b38: e03b b.n 8003bb2 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8003b3a: 4b20 ldr r3, [pc, #128] ; (8003bbc ) 8003b3c: 685b ldr r3, [r3, #4] 8003b3e: f003 020c and.w r2, r3, #12 8003b42: 687b ldr r3, [r7, #4] 8003b44: 685b ldr r3, [r3, #4] 8003b46: 009b lsls r3, r3, #2 8003b48: 429a cmp r2, r3 8003b4a: d1eb bne.n 8003b24 } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8003b4c: 687b ldr r3, [r7, #4] 8003b4e: 681b ldr r3, [r3, #0] 8003b50: f003 0304 and.w r3, r3, #4 8003b54: 2b00 cmp r3, #0 8003b56: d008 beq.n 8003b6a { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 8003b58: 4b18 ldr r3, [pc, #96] ; (8003bbc ) 8003b5a: 685b ldr r3, [r3, #4] 8003b5c: f423 62e0 bic.w r2, r3, #1792 ; 0x700 8003b60: 687b ldr r3, [r7, #4] 8003b62: 68db ldr r3, [r3, #12] 8003b64: 4915 ldr r1, [pc, #84] ; (8003bbc ) 8003b66: 4313 orrs r3, r2 8003b68: 604b str r3, [r1, #4] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8003b6a: 687b ldr r3, [r7, #4] 8003b6c: 681b ldr r3, [r3, #0] 8003b6e: f003 0308 and.w r3, r3, #8 8003b72: 2b00 cmp r3, #0 8003b74: d009 beq.n 8003b8a { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); 8003b76: 4b11 ldr r3, [pc, #68] ; (8003bbc ) 8003b78: 685b ldr r3, [r3, #4] 8003b7a: f423 5260 bic.w r2, r3, #14336 ; 0x3800 8003b7e: 687b ldr r3, [r7, #4] 8003b80: 691b ldr r3, [r3, #16] 8003b82: 00db lsls r3, r3, #3 8003b84: 490d ldr r1, [pc, #52] ; (8003bbc ) 8003b86: 4313 orrs r3, r2 8003b88: 604b str r3, [r1, #4] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; 8003b8a: f000 f81f bl 8003bcc 8003b8e: 4601 mov r1, r0 8003b90: 4b0a ldr r3, [pc, #40] ; (8003bbc ) 8003b92: 685b ldr r3, [r3, #4] 8003b94: 091b lsrs r3, r3, #4 8003b96: f003 030f and.w r3, r3, #15 8003b9a: 4a09 ldr r2, [pc, #36] ; (8003bc0 ) 8003b9c: 5cd3 ldrb r3, [r2, r3] 8003b9e: fa21 f303 lsr.w r3, r1, r3 8003ba2: 4a08 ldr r2, [pc, #32] ; (8003bc4 ) 8003ba4: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick(uwTickPrio); 8003ba6: 4b08 ldr r3, [pc, #32] ; (8003bc8 ) 8003ba8: 681b ldr r3, [r3, #0] 8003baa: 4618 mov r0, r3 8003bac: f001 ff40 bl 8005a30 return HAL_OK; 8003bb0: 2300 movs r3, #0 } 8003bb2: 4618 mov r0, r3 8003bb4: 3710 adds r7, #16 8003bb6: 46bd mov sp, r7 8003bb8: bd80 pop {r7, pc} 8003bba: bf00 nop 8003bbc: 40021000 .word 0x40021000 8003bc0: 08008990 .word 0x08008990 8003bc4: 20000008 .word 0x20000008 8003bc8: 20000000 .word 0x20000000 08003bcc : * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 8003bcc: b490 push {r4, r7} 8003bce: b08e sub sp, #56 ; 0x38 8003bd0: af00 add r7, sp, #0 #if defined(RCC_CFGR2_PREDIV1SRC) const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13}; const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; #else const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; 8003bd2: 4b2b ldr r3, [pc, #172] ; (8003c80 ) 8003bd4: f107 0414 add.w r4, r7, #20 8003bd8: cb0f ldmia r3, {r0, r1, r2, r3} 8003bda: e884 000f stmia.w r4, {r0, r1, r2, r3} #if defined(RCC_CFGR2_PREDIV1) const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; 8003bde: 4b29 ldr r3, [pc, #164] ; (8003c84 ) 8003be0: 1d3c adds r4, r7, #4 8003be2: cb0f ldmia r3, {r0, r1, r2, r3} 8003be4: e884 000f stmia.w r4, {r0, r1, r2, r3} #else const uint8_t aPredivFactorTable[2] = {1, 2}; #endif /*RCC_CFGR2_PREDIV1*/ #endif uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; 8003be8: 2300 movs r3, #0 8003bea: 62fb str r3, [r7, #44] ; 0x2c 8003bec: 2300 movs r3, #0 8003bee: 62bb str r3, [r7, #40] ; 0x28 8003bf0: 2300 movs r3, #0 8003bf2: 637b str r3, [r7, #52] ; 0x34 8003bf4: 2300 movs r3, #0 8003bf6: 627b str r3, [r7, #36] ; 0x24 uint32_t sysclockfreq = 0U; 8003bf8: 2300 movs r3, #0 8003bfa: 633b str r3, [r7, #48] ; 0x30 #if defined(RCC_CFGR2_PREDIV1SRC) uint32_t prediv2 = 0U, pll2mul = 0U; #endif /*RCC_CFGR2_PREDIV1SRC*/ tmpreg = RCC->CFGR; 8003bfc: 4b22 ldr r3, [pc, #136] ; (8003c88 ) 8003bfe: 685b ldr r3, [r3, #4] 8003c00: 62fb str r3, [r7, #44] ; 0x2c /* Get SYSCLK source -------------------------------------------------------*/ switch (tmpreg & RCC_CFGR_SWS) 8003c02: 6afb ldr r3, [r7, #44] ; 0x2c 8003c04: f003 030c and.w r3, r3, #12 8003c08: 2b04 cmp r3, #4 8003c0a: d002 beq.n 8003c12 8003c0c: 2b08 cmp r3, #8 8003c0e: d003 beq.n 8003c18 8003c10: e02c b.n 8003c6c { case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ { sysclockfreq = HSE_VALUE; 8003c12: 4b1e ldr r3, [pc, #120] ; (8003c8c ) 8003c14: 633b str r3, [r7, #48] ; 0x30 break; 8003c16: e02c b.n 8003c72 } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ { pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; 8003c18: 6afb ldr r3, [r7, #44] ; 0x2c 8003c1a: 0c9b lsrs r3, r3, #18 8003c1c: f003 030f and.w r3, r3, #15 8003c20: f107 0238 add.w r2, r7, #56 ; 0x38 8003c24: 4413 add r3, r2 8003c26: f813 3c24 ldrb.w r3, [r3, #-36] 8003c2a: 627b str r3, [r7, #36] ; 0x24 if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) 8003c2c: 6afb ldr r3, [r7, #44] ; 0x2c 8003c2e: f403 3380 and.w r3, r3, #65536 ; 0x10000 8003c32: 2b00 cmp r3, #0 8003c34: d012 beq.n 8003c5c { #if defined(RCC_CFGR2_PREDIV1) prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; 8003c36: 4b14 ldr r3, [pc, #80] ; (8003c88 ) 8003c38: 6adb ldr r3, [r3, #44] ; 0x2c 8003c3a: f003 030f and.w r3, r3, #15 8003c3e: f107 0238 add.w r2, r7, #56 ; 0x38 8003c42: 4413 add r3, r2 8003c44: f813 3c34 ldrb.w r3, [r3, #-52] 8003c48: 62bb str r3, [r7, #40] ; 0x28 { pllclk = pllclk / 2; } #else /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv); 8003c4a: 6a7b ldr r3, [r7, #36] ; 0x24 8003c4c: 4a0f ldr r2, [pc, #60] ; (8003c8c ) 8003c4e: fb02 f203 mul.w r2, r2, r3 8003c52: 6abb ldr r3, [r7, #40] ; 0x28 8003c54: fbb2 f3f3 udiv r3, r2, r3 8003c58: 637b str r3, [r7, #52] ; 0x34 8003c5a: e004 b.n 8003c66 #endif /*RCC_CFGR2_PREDIV1SRC*/ } else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); 8003c5c: 6a7b ldr r3, [r7, #36] ; 0x24 8003c5e: 4a0c ldr r2, [pc, #48] ; (8003c90 ) 8003c60: fb02 f303 mul.w r3, r2, r3 8003c64: 637b str r3, [r7, #52] ; 0x34 } sysclockfreq = pllclk; 8003c66: 6b7b ldr r3, [r7, #52] ; 0x34 8003c68: 633b str r3, [r7, #48] ; 0x30 break; 8003c6a: e002 b.n 8003c72 } case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ default: /* HSI used as system clock */ { sysclockfreq = HSI_VALUE; 8003c6c: 4b07 ldr r3, [pc, #28] ; (8003c8c ) 8003c6e: 633b str r3, [r7, #48] ; 0x30 break; 8003c70: bf00 nop } } return sysclockfreq; 8003c72: 6b3b ldr r3, [r7, #48] ; 0x30 } 8003c74: 4618 mov r0, r3 8003c76: 3738 adds r7, #56 ; 0x38 8003c78: 46bd mov sp, r7 8003c7a: bc90 pop {r4, r7} 8003c7c: 4770 bx lr 8003c7e: bf00 nop 8003c80: 080088e4 .word 0x080088e4 8003c84: 080088f4 .word 0x080088f4 8003c88: 40021000 .word 0x40021000 8003c8c: 007a1200 .word 0x007a1200 8003c90: 003d0900 .word 0x003d0900 08003c94 : * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 8003c94: b480 push {r7} 8003c96: af00 add r7, sp, #0 return SystemCoreClock; 8003c98: 4b02 ldr r3, [pc, #8] ; (8003ca4 ) 8003c9a: 681b ldr r3, [r3, #0] } 8003c9c: 4618 mov r0, r3 8003c9e: 46bd mov sp, r7 8003ca0: bc80 pop {r7} 8003ca2: 4770 bx lr 8003ca4: 20000008 .word 0x20000008 08003ca8 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 8003ca8: b580 push {r7, lr} 8003caa: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); 8003cac: f7ff fff2 bl 8003c94 8003cb0: 4601 mov r1, r0 8003cb2: 4b05 ldr r3, [pc, #20] ; (8003cc8 ) 8003cb4: 685b ldr r3, [r3, #4] 8003cb6: 0a1b lsrs r3, r3, #8 8003cb8: f003 0307 and.w r3, r3, #7 8003cbc: 4a03 ldr r2, [pc, #12] ; (8003ccc ) 8003cbe: 5cd3 ldrb r3, [r2, r3] 8003cc0: fa21 f303 lsr.w r3, r1, r3 } 8003cc4: 4618 mov r0, r3 8003cc6: bd80 pop {r7, pc} 8003cc8: 40021000 .word 0x40021000 8003ccc: 080089a0 .word 0x080089a0 08003cd0 : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 8003cd0: b580 push {r7, lr} 8003cd2: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); 8003cd4: f7ff ffde bl 8003c94 8003cd8: 4601 mov r1, r0 8003cda: 4b05 ldr r3, [pc, #20] ; (8003cf0 ) 8003cdc: 685b ldr r3, [r3, #4] 8003cde: 0adb lsrs r3, r3, #11 8003ce0: f003 0307 and.w r3, r3, #7 8003ce4: 4a03 ldr r2, [pc, #12] ; (8003cf4 ) 8003ce6: 5cd3 ldrb r3, [r2, r3] 8003ce8: fa21 f303 lsr.w r3, r1, r3 } 8003cec: 4618 mov r0, r3 8003cee: bd80 pop {r7, pc} 8003cf0: 40021000 .word 0x40021000 8003cf4: 080089a0 .word 0x080089a0 08003cf8 : * contains the current clock configuration. * @param pFLatency Pointer on the Flash Latency. * @retval None */ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) { 8003cf8: b480 push {r7} 8003cfa: b083 sub sp, #12 8003cfc: af00 add r7, sp, #0 8003cfe: 6078 str r0, [r7, #4] 8003d00: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(RCC_ClkInitStruct != NULL); assert_param(pFLatency != NULL); /* Set all possible values for the Clock type parameter --------------------*/ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; 8003d02: 687b ldr r3, [r7, #4] 8003d04: 220f movs r2, #15 8003d06: 601a str r2, [r3, #0] /* Get the SYSCLK configuration --------------------------------------------*/ RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); 8003d08: 4b10 ldr r3, [pc, #64] ; (8003d4c ) 8003d0a: 685b ldr r3, [r3, #4] 8003d0c: f003 0203 and.w r2, r3, #3 8003d10: 687b ldr r3, [r7, #4] 8003d12: 605a str r2, [r3, #4] /* Get the HCLK configuration ----------------------------------------------*/ RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); 8003d14: 4b0d ldr r3, [pc, #52] ; (8003d4c ) 8003d16: 685b ldr r3, [r3, #4] 8003d18: f003 02f0 and.w r2, r3, #240 ; 0xf0 8003d1c: 687b ldr r3, [r7, #4] 8003d1e: 609a str r2, [r3, #8] /* Get the APB1 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); 8003d20: 4b0a ldr r3, [pc, #40] ; (8003d4c ) 8003d22: 685b ldr r3, [r3, #4] 8003d24: f403 62e0 and.w r2, r3, #1792 ; 0x700 8003d28: 687b ldr r3, [r7, #4] 8003d2a: 60da str r2, [r3, #12] /* Get the APB2 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3); 8003d2c: 4b07 ldr r3, [pc, #28] ; (8003d4c ) 8003d2e: 685b ldr r3, [r3, #4] 8003d30: 08db lsrs r3, r3, #3 8003d32: f403 62e0 and.w r2, r3, #1792 ; 0x700 8003d36: 687b ldr r3, [r7, #4] 8003d38: 611a str r2, [r3, #16] #if defined(FLASH_ACR_LATENCY) /* Get the Flash Wait State (Latency) configuration ------------------------*/ *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); #else /* For VALUE lines devices, only LATENCY_0 can be set*/ *pFLatency = (uint32_t)FLASH_LATENCY_0; 8003d3a: 683b ldr r3, [r7, #0] 8003d3c: 2200 movs r2, #0 8003d3e: 601a str r2, [r3, #0] #endif } 8003d40: bf00 nop 8003d42: 370c adds r7, #12 8003d44: 46bd mov sp, r7 8003d46: bc80 pop {r7} 8003d48: 4770 bx lr 8003d4a: bf00 nop 8003d4c: 40021000 .word 0x40021000 08003d50 : * @brief This function provides delay (in milliseconds) based on CPU cycles method. * @param mdelay: specifies the delay time length, in milliseconds. * @retval None */ static void RCC_Delay(uint32_t mdelay) { 8003d50: b480 push {r7} 8003d52: b085 sub sp, #20 8003d54: af00 add r7, sp, #0 8003d56: 6078 str r0, [r7, #4] __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U); 8003d58: 4b0a ldr r3, [pc, #40] ; (8003d84 ) 8003d5a: 681b ldr r3, [r3, #0] 8003d5c: 4a0a ldr r2, [pc, #40] ; (8003d88 ) 8003d5e: fba2 2303 umull r2, r3, r2, r3 8003d62: 0a5b lsrs r3, r3, #9 8003d64: 687a ldr r2, [r7, #4] 8003d66: fb02 f303 mul.w r3, r2, r3 8003d6a: 60fb str r3, [r7, #12] do { __NOP(); 8003d6c: bf00 nop } while (Delay --); 8003d6e: 68fb ldr r3, [r7, #12] 8003d70: 1e5a subs r2, r3, #1 8003d72: 60fa str r2, [r7, #12] 8003d74: 2b00 cmp r3, #0 8003d76: d1f9 bne.n 8003d6c } 8003d78: bf00 nop 8003d7a: 3714 adds r7, #20 8003d7c: 46bd mov sp, r7 8003d7e: bc80 pop {r7} 8003d80: 4770 bx lr 8003d82: bf00 nop 8003d84: 20000008 .word 0x20000008 8003d88: 10624dd3 .word 0x10624dd3 08003d8c : * manually disable it. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 8003d8c: b580 push {r7, lr} 8003d8e: b086 sub sp, #24 8003d90: af00 add r7, sp, #0 8003d92: 6078 str r0, [r7, #4] uint32_t tickstart = 0U, temp_reg = 0U; 8003d94: 2300 movs r3, #0 8003d96: 613b str r3, [r7, #16] 8003d98: 2300 movs r3, #0 8003d9a: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*------------------------------- RTC/LCD Configuration ------------------------*/ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 8003d9c: 687b ldr r3, [r7, #4] 8003d9e: 681b ldr r3, [r3, #0] 8003da0: f003 0301 and.w r3, r3, #1 8003da4: 2b00 cmp r3, #0 8003da6: d07d beq.n 8003ea4 { /* check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); FlagStatus pwrclkchanged = RESET; 8003da8: 2300 movs r3, #0 8003daa: 75fb strb r3, [r7, #23] /* As soon as function is called to change RTC clock source, activation of the power domain is done. */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 8003dac: 4b47 ldr r3, [pc, #284] ; (8003ecc ) 8003dae: 69db ldr r3, [r3, #28] 8003db0: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8003db4: 2b00 cmp r3, #0 8003db6: d10d bne.n 8003dd4 { __HAL_RCC_PWR_CLK_ENABLE(); 8003db8: 4b44 ldr r3, [pc, #272] ; (8003ecc ) 8003dba: 69db ldr r3, [r3, #28] 8003dbc: 4a43 ldr r2, [pc, #268] ; (8003ecc ) 8003dbe: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8003dc2: 61d3 str r3, [r2, #28] 8003dc4: 4b41 ldr r3, [pc, #260] ; (8003ecc ) 8003dc6: 69db ldr r3, [r3, #28] 8003dc8: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8003dcc: 60bb str r3, [r7, #8] 8003dce: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 8003dd0: 2301 movs r3, #1 8003dd2: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8003dd4: 4b3e ldr r3, [pc, #248] ; (8003ed0 ) 8003dd6: 681b ldr r3, [r3, #0] 8003dd8: f403 7380 and.w r3, r3, #256 ; 0x100 8003ddc: 2b00 cmp r3, #0 8003dde: d118 bne.n 8003e12 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8003de0: 4b3b ldr r3, [pc, #236] ; (8003ed0 ) 8003de2: 681b ldr r3, [r3, #0] 8003de4: 4a3a ldr r2, [pc, #232] ; (8003ed0 ) 8003de6: f443 7380 orr.w r3, r3, #256 ; 0x100 8003dea: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8003dec: f7fd ffc4 bl 8001d78 8003df0: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8003df2: e008 b.n 8003e06 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8003df4: f7fd ffc0 bl 8001d78 8003df8: 4602 mov r2, r0 8003dfa: 693b ldr r3, [r7, #16] 8003dfc: 1ad3 subs r3, r2, r3 8003dfe: 2b64 cmp r3, #100 ; 0x64 8003e00: d901 bls.n 8003e06 { return HAL_TIMEOUT; 8003e02: 2303 movs r3, #3 8003e04: e05e b.n 8003ec4 while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8003e06: 4b32 ldr r3, [pc, #200] ; (8003ed0 ) 8003e08: 681b ldr r3, [r3, #0] 8003e0a: f403 7380 and.w r3, r3, #256 ; 0x100 8003e0e: 2b00 cmp r3, #0 8003e10: d0f0 beq.n 8003df4 } } } /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); 8003e12: 4b2e ldr r3, [pc, #184] ; (8003ecc ) 8003e14: 6a1b ldr r3, [r3, #32] 8003e16: f403 7340 and.w r3, r3, #768 ; 0x300 8003e1a: 60fb str r3, [r7, #12] if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) 8003e1c: 68fb ldr r3, [r7, #12] 8003e1e: 2b00 cmp r3, #0 8003e20: d02e beq.n 8003e80 8003e22: 687b ldr r3, [r7, #4] 8003e24: 685b ldr r3, [r3, #4] 8003e26: f403 7340 and.w r3, r3, #768 ; 0x300 8003e2a: 68fa ldr r2, [r7, #12] 8003e2c: 429a cmp r2, r3 8003e2e: d027 beq.n 8003e80 { /* Store the content of BDCR register before the reset of Backup Domain */ temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 8003e30: 4b26 ldr r3, [pc, #152] ; (8003ecc ) 8003e32: 6a1b ldr r3, [r3, #32] 8003e34: f423 7340 bic.w r3, r3, #768 ; 0x300 8003e38: 60fb str r3, [r7, #12] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 8003e3a: 4b26 ldr r3, [pc, #152] ; (8003ed4 ) 8003e3c: 2201 movs r2, #1 8003e3e: 601a str r2, [r3, #0] __HAL_RCC_BACKUPRESET_RELEASE(); 8003e40: 4b24 ldr r3, [pc, #144] ; (8003ed4 ) 8003e42: 2200 movs r2, #0 8003e44: 601a str r2, [r3, #0] /* Restore the Content of BDCR register */ RCC->BDCR = temp_reg; 8003e46: 4a21 ldr r2, [pc, #132] ; (8003ecc ) 8003e48: 68fb ldr r3, [r7, #12] 8003e4a: 6213 str r3, [r2, #32] /* Wait for LSERDY if LSE was enabled */ if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) 8003e4c: 68fb ldr r3, [r7, #12] 8003e4e: f003 0301 and.w r3, r3, #1 8003e52: 2b00 cmp r3, #0 8003e54: d014 beq.n 8003e80 { /* Get Start Tick */ tickstart = HAL_GetTick(); 8003e56: f7fd ff8f bl 8001d78 8003e5a: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8003e5c: e00a b.n 8003e74 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8003e5e: f7fd ff8b bl 8001d78 8003e62: 4602 mov r2, r0 8003e64: 693b ldr r3, [r7, #16] 8003e66: 1ad3 subs r3, r2, r3 8003e68: f241 3288 movw r2, #5000 ; 0x1388 8003e6c: 4293 cmp r3, r2 8003e6e: d901 bls.n 8003e74 { return HAL_TIMEOUT; 8003e70: 2303 movs r3, #3 8003e72: e027 b.n 8003ec4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8003e74: 4b15 ldr r3, [pc, #84] ; (8003ecc ) 8003e76: 6a1b ldr r3, [r3, #32] 8003e78: f003 0302 and.w r3, r3, #2 8003e7c: 2b00 cmp r3, #0 8003e7e: d0ee beq.n 8003e5e } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 8003e80: 4b12 ldr r3, [pc, #72] ; (8003ecc ) 8003e82: 6a1b ldr r3, [r3, #32] 8003e84: f423 7240 bic.w r2, r3, #768 ; 0x300 8003e88: 687b ldr r3, [r7, #4] 8003e8a: 685b ldr r3, [r3, #4] 8003e8c: 490f ldr r1, [pc, #60] ; (8003ecc ) 8003e8e: 4313 orrs r3, r2 8003e90: 620b str r3, [r1, #32] /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 8003e92: 7dfb ldrb r3, [r7, #23] 8003e94: 2b01 cmp r3, #1 8003e96: d105 bne.n 8003ea4 { __HAL_RCC_PWR_CLK_DISABLE(); 8003e98: 4b0c ldr r3, [pc, #48] ; (8003ecc ) 8003e9a: 69db ldr r3, [r3, #28] 8003e9c: 4a0b ldr r2, [pc, #44] ; (8003ecc ) 8003e9e: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 8003ea2: 61d3 str r3, [r2, #28] } } /*------------------------------ ADC clock Configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 8003ea4: 687b ldr r3, [r7, #4] 8003ea6: 681b ldr r3, [r3, #0] 8003ea8: f003 0302 and.w r3, r3, #2 8003eac: 2b00 cmp r3, #0 8003eae: d008 beq.n 8003ec2 { /* Check the parameters */ assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection)); /* Configure the ADC clock source */ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 8003eb0: 4b06 ldr r3, [pc, #24] ; (8003ecc ) 8003eb2: 685b ldr r3, [r3, #4] 8003eb4: f423 4240 bic.w r2, r3, #49152 ; 0xc000 8003eb8: 687b ldr r3, [r7, #4] 8003eba: 689b ldr r3, [r3, #8] 8003ebc: 4903 ldr r1, [pc, #12] ; (8003ecc ) 8003ebe: 4313 orrs r3, r2 8003ec0: 604b str r3, [r1, #4] /* Configure the USB clock source */ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); } #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ return HAL_OK; 8003ec2: 2300 movs r3, #0 } 8003ec4: 4618 mov r0, r3 8003ec6: 3718 adds r7, #24 8003ec8: 46bd mov sp, r7 8003eca: bd80 pop {r7, pc} 8003ecc: 40021000 .word 0x40021000 8003ed0: 40007000 .word 0x40007000 8003ed4: 42420440 .word 0x42420440 08003ed8 : * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock @endif * @retval Frequency in Hz (0: means that no available frequency for the peripheral) */ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { 8003ed8: b580 push {r7, lr} 8003eda: b084 sub sp, #16 8003edc: af00 add r7, sp, #0 8003ede: 6078 str r0, [r7, #4] const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; const uint8_t aPredivFactorTable[2] = {1, 2}; uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ uint32_t temp_reg = 0U, frequency = 0U; 8003ee0: 2300 movs r3, #0 8003ee2: 60bb str r3, [r7, #8] 8003ee4: 2300 movs r3, #0 8003ee6: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); switch (PeriphClk) 8003ee8: 687b ldr r3, [r7, #4] 8003eea: 2b01 cmp r3, #1 8003eec: d002 beq.n 8003ef4 8003eee: 2b02 cmp r3, #2 8003ef0: d033 beq.n 8003f5a frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2); break; } default: { break; 8003ef2: e041 b.n 8003f78 temp_reg = RCC->BDCR; 8003ef4: 4b23 ldr r3, [pc, #140] ; (8003f84 ) 8003ef6: 6a1b ldr r3, [r3, #32] 8003ef8: 60bb str r3, [r7, #8] if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY))) 8003efa: 68bb ldr r3, [r7, #8] 8003efc: f403 7340 and.w r3, r3, #768 ; 0x300 8003f00: f5b3 7f80 cmp.w r3, #256 ; 0x100 8003f04: d108 bne.n 8003f18 8003f06: 68bb ldr r3, [r7, #8] 8003f08: f003 0302 and.w r3, r3, #2 8003f0c: 2b00 cmp r3, #0 8003f0e: d003 beq.n 8003f18 frequency = LSE_VALUE; 8003f10: f44f 4300 mov.w r3, #32768 ; 0x8000 8003f14: 60fb str r3, [r7, #12] 8003f16: e01f b.n 8003f58 else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) 8003f18: 68bb ldr r3, [r7, #8] 8003f1a: f403 7340 and.w r3, r3, #768 ; 0x300 8003f1e: f5b3 7f00 cmp.w r3, #512 ; 0x200 8003f22: d109 bne.n 8003f38 8003f24: 4b17 ldr r3, [pc, #92] ; (8003f84 ) 8003f26: 6a5b ldr r3, [r3, #36] ; 0x24 8003f28: f003 0302 and.w r3, r3, #2 8003f2c: 2b00 cmp r3, #0 8003f2e: d003 beq.n 8003f38 frequency = LSI_VALUE; 8003f30: f649 4340 movw r3, #40000 ; 0x9c40 8003f34: 60fb str r3, [r7, #12] 8003f36: e00f b.n 8003f58 else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) 8003f38: 68bb ldr r3, [r7, #8] 8003f3a: f403 7340 and.w r3, r3, #768 ; 0x300 8003f3e: f5b3 7f40 cmp.w r3, #768 ; 0x300 8003f42: d118 bne.n 8003f76 8003f44: 4b0f ldr r3, [pc, #60] ; (8003f84 ) 8003f46: 681b ldr r3, [r3, #0] 8003f48: f403 3300 and.w r3, r3, #131072 ; 0x20000 8003f4c: 2b00 cmp r3, #0 8003f4e: d012 beq.n 8003f76 frequency = HSE_VALUE / 128U; 8003f50: f24f 4324 movw r3, #62500 ; 0xf424 8003f54: 60fb str r3, [r7, #12] break; 8003f56: e00e b.n 8003f76 8003f58: e00d b.n 8003f76 frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2); 8003f5a: f7ff feb9 bl 8003cd0 8003f5e: 4602 mov r2, r0 8003f60: 4b08 ldr r3, [pc, #32] ; (8003f84 ) 8003f62: 685b ldr r3, [r3, #4] 8003f64: 0b9b lsrs r3, r3, #14 8003f66: f003 0303 and.w r3, r3, #3 8003f6a: 3301 adds r3, #1 8003f6c: 005b lsls r3, r3, #1 8003f6e: fbb2 f3f3 udiv r3, r2, r3 8003f72: 60fb str r3, [r7, #12] break; 8003f74: e000 b.n 8003f78 break; 8003f76: bf00 nop } } return (frequency); 8003f78: 68fb ldr r3, [r7, #12] } 8003f7a: 4618 mov r0, r3 8003f7c: 3710 adds r7, #16 8003f7e: 46bd mov sp, r7 8003f80: bd80 pop {r7, pc} 8003f82: bf00 nop 8003f84: 40021000 .word 0x40021000 08003f88 : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { 8003f88: b580 push {r7, lr} 8003f8a: b082 sub sp, #8 8003f8c: af00 add r7, sp, #0 8003f8e: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8003f90: 687b ldr r3, [r7, #4] 8003f92: 2b00 cmp r3, #0 8003f94: d101 bne.n 8003f9a { return HAL_ERROR; 8003f96: 2301 movs r3, #1 8003f98: e01d b.n 8003fd6 assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8003f9a: 687b ldr r3, [r7, #4] 8003f9c: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 8003fa0: b2db uxtb r3, r3 8003fa2: 2b00 cmp r3, #0 8003fa4: d106 bne.n 8003fb4 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8003fa6: 687b ldr r3, [r7, #4] 8003fa8: 2200 movs r2, #0 8003faa: f883 203c strb.w r2, [r3, #60] ; 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); 8003fae: 6878 ldr r0, [r7, #4] 8003fb0: f001 fc44 bl 800583c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8003fb4: 687b ldr r3, [r7, #4] 8003fb6: 2202 movs r2, #2 8003fb8: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8003fbc: 687b ldr r3, [r7, #4] 8003fbe: 681a ldr r2, [r3, #0] 8003fc0: 687b ldr r3, [r7, #4] 8003fc2: 3304 adds r3, #4 8003fc4: 4619 mov r1, r3 8003fc6: 4610 mov r0, r2 8003fc8: f000 f958 bl 800427c /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8003fcc: 687b ldr r3, [r7, #4] 8003fce: 2201 movs r2, #1 8003fd0: f883 203d strb.w r2, [r3, #61] ; 0x3d return HAL_OK; 8003fd4: 2300 movs r3, #0 } 8003fd6: 4618 mov r0, r3 8003fd8: 3708 adds r7, #8 8003fda: 46bd mov sp, r7 8003fdc: bd80 pop {r7, pc} 08003fde : * @brief Starts the TIM Base generation in interrupt mode. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) { 8003fde: b480 push {r7} 8003fe0: b085 sub sp, #20 8003fe2: af00 add r7, sp, #0 8003fe4: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Enable the TIM Update interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); 8003fe6: 687b ldr r3, [r7, #4] 8003fe8: 681b ldr r3, [r3, #0] 8003fea: 68da ldr r2, [r3, #12] 8003fec: 687b ldr r3, [r7, #4] 8003fee: 681b ldr r3, [r3, #0] 8003ff0: f042 0201 orr.w r2, r2, #1 8003ff4: 60da str r2, [r3, #12] /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 8003ff6: 687b ldr r3, [r7, #4] 8003ff8: 681b ldr r3, [r3, #0] 8003ffa: 689b ldr r3, [r3, #8] 8003ffc: f003 0307 and.w r3, r3, #7 8004000: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8004002: 68fb ldr r3, [r7, #12] 8004004: 2b06 cmp r3, #6 8004006: d007 beq.n 8004018 { __HAL_TIM_ENABLE(htim); 8004008: 687b ldr r3, [r7, #4] 800400a: 681b ldr r3, [r3, #0] 800400c: 681a ldr r2, [r3, #0] 800400e: 687b ldr r3, [r7, #4] 8004010: 681b ldr r3, [r3, #0] 8004012: f042 0201 orr.w r2, r2, #1 8004016: 601a str r2, [r3, #0] } /* Return function status */ return HAL_OK; 8004018: 2300 movs r3, #0 } 800401a: 4618 mov r0, r3 800401c: 3714 adds r7, #20 800401e: 46bd mov sp, r7 8004020: bc80 pop {r7} 8004022: 4770 bx lr 08004024 : * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { 8004024: b580 push {r7, lr} 8004026: b082 sub sp, #8 8004028: af00 add r7, sp, #0 800402a: 6078 str r0, [r7, #4] /* Capture compare 1 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) 800402c: 687b ldr r3, [r7, #4] 800402e: 681b ldr r3, [r3, #0] 8004030: 691b ldr r3, [r3, #16] 8004032: f003 0302 and.w r3, r3, #2 8004036: 2b02 cmp r3, #2 8004038: d122 bne.n 8004080 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) 800403a: 687b ldr r3, [r7, #4] 800403c: 681b ldr r3, [r3, #0] 800403e: 68db ldr r3, [r3, #12] 8004040: f003 0302 and.w r3, r3, #2 8004044: 2b02 cmp r3, #2 8004046: d11b bne.n 8004080 { { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); 8004048: 687b ldr r3, [r7, #4] 800404a: 681b ldr r3, [r3, #0] 800404c: f06f 0202 mvn.w r2, #2 8004050: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 8004052: 687b ldr r3, [r7, #4] 8004054: 2201 movs r2, #1 8004056: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 8004058: 687b ldr r3, [r7, #4] 800405a: 681b ldr r3, [r3, #0] 800405c: 699b ldr r3, [r3, #24] 800405e: f003 0303 and.w r3, r3, #3 8004062: 2b00 cmp r3, #0 8004064: d003 beq.n 800406e { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8004066: 6878 ldr r0, [r7, #4] 8004068: f000 f8ed bl 8004246 800406c: e005 b.n 800407a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800406e: 6878 ldr r0, [r7, #4] 8004070: f000 f8e0 bl 8004234 HAL_TIM_PWM_PulseFinishedCallback(htim); 8004074: 6878 ldr r0, [r7, #4] 8004076: f000 f8ef bl 8004258 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800407a: 687b ldr r3, [r7, #4] 800407c: 2200 movs r2, #0 800407e: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) 8004080: 687b ldr r3, [r7, #4] 8004082: 681b ldr r3, [r3, #0] 8004084: 691b ldr r3, [r3, #16] 8004086: f003 0304 and.w r3, r3, #4 800408a: 2b04 cmp r3, #4 800408c: d122 bne.n 80040d4 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) 800408e: 687b ldr r3, [r7, #4] 8004090: 681b ldr r3, [r3, #0] 8004092: 68db ldr r3, [r3, #12] 8004094: f003 0304 and.w r3, r3, #4 8004098: 2b04 cmp r3, #4 800409a: d11b bne.n 80040d4 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); 800409c: 687b ldr r3, [r7, #4] 800409e: 681b ldr r3, [r3, #0] 80040a0: f06f 0204 mvn.w r2, #4 80040a4: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 80040a6: 687b ldr r3, [r7, #4] 80040a8: 2202 movs r2, #2 80040aa: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 80040ac: 687b ldr r3, [r7, #4] 80040ae: 681b ldr r3, [r3, #0] 80040b0: 699b ldr r3, [r3, #24] 80040b2: f403 7340 and.w r3, r3, #768 ; 0x300 80040b6: 2b00 cmp r3, #0 80040b8: d003 beq.n 80040c2 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 80040ba: 6878 ldr r0, [r7, #4] 80040bc: f000 f8c3 bl 8004246 80040c0: e005 b.n 80040ce { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 80040c2: 6878 ldr r0, [r7, #4] 80040c4: f000 f8b6 bl 8004234 HAL_TIM_PWM_PulseFinishedCallback(htim); 80040c8: 6878 ldr r0, [r7, #4] 80040ca: f000 f8c5 bl 8004258 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 80040ce: 687b ldr r3, [r7, #4] 80040d0: 2200 movs r2, #0 80040d2: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) 80040d4: 687b ldr r3, [r7, #4] 80040d6: 681b ldr r3, [r3, #0] 80040d8: 691b ldr r3, [r3, #16] 80040da: f003 0308 and.w r3, r3, #8 80040de: 2b08 cmp r3, #8 80040e0: d122 bne.n 8004128 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) 80040e2: 687b ldr r3, [r7, #4] 80040e4: 681b ldr r3, [r3, #0] 80040e6: 68db ldr r3, [r3, #12] 80040e8: f003 0308 and.w r3, r3, #8 80040ec: 2b08 cmp r3, #8 80040ee: d11b bne.n 8004128 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); 80040f0: 687b ldr r3, [r7, #4] 80040f2: 681b ldr r3, [r3, #0] 80040f4: f06f 0208 mvn.w r2, #8 80040f8: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 80040fa: 687b ldr r3, [r7, #4] 80040fc: 2204 movs r2, #4 80040fe: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 8004100: 687b ldr r3, [r7, #4] 8004102: 681b ldr r3, [r3, #0] 8004104: 69db ldr r3, [r3, #28] 8004106: f003 0303 and.w r3, r3, #3 800410a: 2b00 cmp r3, #0 800410c: d003 beq.n 8004116 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800410e: 6878 ldr r0, [r7, #4] 8004110: f000 f899 bl 8004246 8004114: e005 b.n 8004122 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8004116: 6878 ldr r0, [r7, #4] 8004118: f000 f88c bl 8004234 HAL_TIM_PWM_PulseFinishedCallback(htim); 800411c: 6878 ldr r0, [r7, #4] 800411e: f000 f89b bl 8004258 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8004122: 687b ldr r3, [r7, #4] 8004124: 2200 movs r2, #0 8004126: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) 8004128: 687b ldr r3, [r7, #4] 800412a: 681b ldr r3, [r3, #0] 800412c: 691b ldr r3, [r3, #16] 800412e: f003 0310 and.w r3, r3, #16 8004132: 2b10 cmp r3, #16 8004134: d122 bne.n 800417c { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) 8004136: 687b ldr r3, [r7, #4] 8004138: 681b ldr r3, [r3, #0] 800413a: 68db ldr r3, [r3, #12] 800413c: f003 0310 and.w r3, r3, #16 8004140: 2b10 cmp r3, #16 8004142: d11b bne.n 800417c { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); 8004144: 687b ldr r3, [r7, #4] 8004146: 681b ldr r3, [r3, #0] 8004148: f06f 0210 mvn.w r2, #16 800414c: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 800414e: 687b ldr r3, [r7, #4] 8004150: 2208 movs r2, #8 8004152: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 8004154: 687b ldr r3, [r7, #4] 8004156: 681b ldr r3, [r3, #0] 8004158: 69db ldr r3, [r3, #28] 800415a: f403 7340 and.w r3, r3, #768 ; 0x300 800415e: 2b00 cmp r3, #0 8004160: d003 beq.n 800416a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8004162: 6878 ldr r0, [r7, #4] 8004164: f000 f86f bl 8004246 8004168: e005 b.n 8004176 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800416a: 6878 ldr r0, [r7, #4] 800416c: f000 f862 bl 8004234 HAL_TIM_PWM_PulseFinishedCallback(htim); 8004170: 6878 ldr r0, [r7, #4] 8004172: f000 f871 bl 8004258 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8004176: 687b ldr r3, [r7, #4] 8004178: 2200 movs r2, #0 800417a: 771a strb r2, [r3, #28] } } /* TIM Update event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) 800417c: 687b ldr r3, [r7, #4] 800417e: 681b ldr r3, [r3, #0] 8004180: 691b ldr r3, [r3, #16] 8004182: f003 0301 and.w r3, r3, #1 8004186: 2b01 cmp r3, #1 8004188: d10e bne.n 80041a8 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) 800418a: 687b ldr r3, [r7, #4] 800418c: 681b ldr r3, [r3, #0] 800418e: 68db ldr r3, [r3, #12] 8004190: f003 0301 and.w r3, r3, #1 8004194: 2b01 cmp r3, #1 8004196: d107 bne.n 80041a8 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); 8004198: 687b ldr r3, [r7, #4] 800419a: 681b ldr r3, [r3, #0] 800419c: f06f 0201 mvn.w r2, #1 80041a0: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); 80041a2: 6878 ldr r0, [r7, #4] 80041a4: f001 fa0a bl 80055bc #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) 80041a8: 687b ldr r3, [r7, #4] 80041aa: 681b ldr r3, [r3, #0] 80041ac: 691b ldr r3, [r3, #16] 80041ae: f003 0380 and.w r3, r3, #128 ; 0x80 80041b2: 2b80 cmp r3, #128 ; 0x80 80041b4: d10e bne.n 80041d4 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) 80041b6: 687b ldr r3, [r7, #4] 80041b8: 681b ldr r3, [r3, #0] 80041ba: 68db ldr r3, [r3, #12] 80041bc: f003 0380 and.w r3, r3, #128 ; 0x80 80041c0: 2b80 cmp r3, #128 ; 0x80 80041c2: d107 bne.n 80041d4 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); 80041c4: 687b ldr r3, [r7, #4] 80041c6: 681b ldr r3, [r3, #0] 80041c8: f06f 0280 mvn.w r2, #128 ; 0x80 80041cc: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); 80041ce: 6878 ldr r0, [r7, #4] 80041d0: f000 f921 bl 8004416 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) 80041d4: 687b ldr r3, [r7, #4] 80041d6: 681b ldr r3, [r3, #0] 80041d8: 691b ldr r3, [r3, #16] 80041da: f003 0340 and.w r3, r3, #64 ; 0x40 80041de: 2b40 cmp r3, #64 ; 0x40 80041e0: d10e bne.n 8004200 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) 80041e2: 687b ldr r3, [r7, #4] 80041e4: 681b ldr r3, [r3, #0] 80041e6: 68db ldr r3, [r3, #12] 80041e8: f003 0340 and.w r3, r3, #64 ; 0x40 80041ec: 2b40 cmp r3, #64 ; 0x40 80041ee: d107 bne.n 8004200 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); 80041f0: 687b ldr r3, [r7, #4] 80041f2: 681b ldr r3, [r3, #0] 80041f4: f06f 0240 mvn.w r2, #64 ; 0x40 80041f8: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); 80041fa: 6878 ldr r0, [r7, #4] 80041fc: f000 f835 bl 800426a #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) 8004200: 687b ldr r3, [r7, #4] 8004202: 681b ldr r3, [r3, #0] 8004204: 691b ldr r3, [r3, #16] 8004206: f003 0320 and.w r3, r3, #32 800420a: 2b20 cmp r3, #32 800420c: d10e bne.n 800422c { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET) 800420e: 687b ldr r3, [r7, #4] 8004210: 681b ldr r3, [r3, #0] 8004212: 68db ldr r3, [r3, #12] 8004214: f003 0320 and.w r3, r3, #32 8004218: 2b20 cmp r3, #32 800421a: d107 bne.n 800422c { __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); 800421c: 687b ldr r3, [r7, #4] 800421e: 681b ldr r3, [r3, #0] 8004220: f06f 0220 mvn.w r2, #32 8004224: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); 8004226: 6878 ldr r0, [r7, #4] 8004228: f000 f8ec bl 8004404 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } 800422c: bf00 nop 800422e: 3708 adds r7, #8 8004230: 46bd mov sp, r7 8004232: bd80 pop {r7, pc} 08004234 : * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { 8004234: b480 push {r7} 8004236: b083 sub sp, #12 8004238: af00 add r7, sp, #0 800423a: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } 800423c: bf00 nop 800423e: 370c adds r7, #12 8004240: 46bd mov sp, r7 8004242: bc80 pop {r7} 8004244: 4770 bx lr 08004246 : * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { 8004246: b480 push {r7} 8004248: b083 sub sp, #12 800424a: af00 add r7, sp, #0 800424c: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } 800424e: bf00 nop 8004250: 370c adds r7, #12 8004252: 46bd mov sp, r7 8004254: bc80 pop {r7} 8004256: 4770 bx lr 08004258 : * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { 8004258: b480 push {r7} 800425a: b083 sub sp, #12 800425c: af00 add r7, sp, #0 800425e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } 8004260: bf00 nop 8004262: 370c adds r7, #12 8004264: 46bd mov sp, r7 8004266: bc80 pop {r7} 8004268: 4770 bx lr 0800426a : * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { 800426a: b480 push {r7} 800426c: b083 sub sp, #12 800426e: af00 add r7, sp, #0 8004270: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } 8004272: bf00 nop 8004274: 370c adds r7, #12 8004276: 46bd mov sp, r7 8004278: bc80 pop {r7} 800427a: 4770 bx lr 0800427c : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) { 800427c: b480 push {r7} 800427e: b085 sub sp, #20 8004280: af00 add r7, sp, #0 8004282: 6078 str r0, [r7, #4] 8004284: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 8004286: 687b ldr r3, [r7, #4] 8004288: 681b ldr r3, [r3, #0] 800428a: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 800428c: 687b ldr r3, [r7, #4] 800428e: 4a35 ldr r2, [pc, #212] ; (8004364 ) 8004290: 4293 cmp r3, r2 8004292: d00b beq.n 80042ac 8004294: 687b ldr r3, [r7, #4] 8004296: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 800429a: d007 beq.n 80042ac 800429c: 687b ldr r3, [r7, #4] 800429e: 4a32 ldr r2, [pc, #200] ; (8004368 ) 80042a0: 4293 cmp r3, r2 80042a2: d003 beq.n 80042ac 80042a4: 687b ldr r3, [r7, #4] 80042a6: 4a31 ldr r2, [pc, #196] ; (800436c ) 80042a8: 4293 cmp r3, r2 80042aa: d108 bne.n 80042be { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 80042ac: 68fb ldr r3, [r7, #12] 80042ae: f023 0370 bic.w r3, r3, #112 ; 0x70 80042b2: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 80042b4: 683b ldr r3, [r7, #0] 80042b6: 685b ldr r3, [r3, #4] 80042b8: 68fa ldr r2, [r7, #12] 80042ba: 4313 orrs r3, r2 80042bc: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 80042be: 687b ldr r3, [r7, #4] 80042c0: 4a28 ldr r2, [pc, #160] ; (8004364 ) 80042c2: 4293 cmp r3, r2 80042c4: d017 beq.n 80042f6 80042c6: 687b ldr r3, [r7, #4] 80042c8: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 80042cc: d013 beq.n 80042f6 80042ce: 687b ldr r3, [r7, #4] 80042d0: 4a25 ldr r2, [pc, #148] ; (8004368 ) 80042d2: 4293 cmp r3, r2 80042d4: d00f beq.n 80042f6 80042d6: 687b ldr r3, [r7, #4] 80042d8: 4a24 ldr r2, [pc, #144] ; (800436c ) 80042da: 4293 cmp r3, r2 80042dc: d00b beq.n 80042f6 80042de: 687b ldr r3, [r7, #4] 80042e0: 4a23 ldr r2, [pc, #140] ; (8004370 ) 80042e2: 4293 cmp r3, r2 80042e4: d007 beq.n 80042f6 80042e6: 687b ldr r3, [r7, #4] 80042e8: 4a22 ldr r2, [pc, #136] ; (8004374 ) 80042ea: 4293 cmp r3, r2 80042ec: d003 beq.n 80042f6 80042ee: 687b ldr r3, [r7, #4] 80042f0: 4a21 ldr r2, [pc, #132] ; (8004378 ) 80042f2: 4293 cmp r3, r2 80042f4: d108 bne.n 8004308 { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 80042f6: 68fb ldr r3, [r7, #12] 80042f8: f423 7340 bic.w r3, r3, #768 ; 0x300 80042fc: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 80042fe: 683b ldr r3, [r7, #0] 8004300: 68db ldr r3, [r3, #12] 8004302: 68fa ldr r2, [r7, #12] 8004304: 4313 orrs r3, r2 8004306: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8004308: 68fb ldr r3, [r7, #12] 800430a: f023 0280 bic.w r2, r3, #128 ; 0x80 800430e: 683b ldr r3, [r7, #0] 8004310: 695b ldr r3, [r3, #20] 8004312: 4313 orrs r3, r2 8004314: 60fb str r3, [r7, #12] TIMx->CR1 = tmpcr1; 8004316: 687b ldr r3, [r7, #4] 8004318: 68fa ldr r2, [r7, #12] 800431a: 601a str r2, [r3, #0] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 800431c: 683b ldr r3, [r7, #0] 800431e: 689a ldr r2, [r3, #8] 8004320: 687b ldr r3, [r7, #4] 8004322: 62da str r2, [r3, #44] ; 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 8004324: 683b ldr r3, [r7, #0] 8004326: 681a ldr r2, [r3, #0] 8004328: 687b ldr r3, [r7, #4] 800432a: 629a str r2, [r3, #40] ; 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 800432c: 687b ldr r3, [r7, #4] 800432e: 4a0d ldr r2, [pc, #52] ; (8004364 ) 8004330: 4293 cmp r3, r2 8004332: d00b beq.n 800434c 8004334: 687b ldr r3, [r7, #4] 8004336: 4a0e ldr r2, [pc, #56] ; (8004370 ) 8004338: 4293 cmp r3, r2 800433a: d007 beq.n 800434c 800433c: 687b ldr r3, [r7, #4] 800433e: 4a0d ldr r2, [pc, #52] ; (8004374 ) 8004340: 4293 cmp r3, r2 8004342: d003 beq.n 800434c 8004344: 687b ldr r3, [r7, #4] 8004346: 4a0c ldr r2, [pc, #48] ; (8004378 ) 8004348: 4293 cmp r3, r2 800434a: d103 bne.n 8004354 { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 800434c: 683b ldr r3, [r7, #0] 800434e: 691a ldr r2, [r3, #16] 8004350: 687b ldr r3, [r7, #4] 8004352: 631a str r2, [r3, #48] ; 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 8004354: 687b ldr r3, [r7, #4] 8004356: 2201 movs r2, #1 8004358: 615a str r2, [r3, #20] } 800435a: bf00 nop 800435c: 3714 adds r7, #20 800435e: 46bd mov sp, r7 8004360: bc80 pop {r7} 8004362: 4770 bx lr 8004364: 40012c00 .word 0x40012c00 8004368: 40000400 .word 0x40000400 800436c: 40000800 .word 0x40000800 8004370: 40014000 .word 0x40014000 8004374: 40014400 .word 0x40014400 8004378: 40014800 .word 0x40014800 0800437c : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig) { 800437c: b480 push {r7} 800437e: b085 sub sp, #20 8004380: af00 add r7, sp, #0 8004382: 6078 str r0, [r7, #4] 8004384: 6039 str r1, [r7, #0] assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 8004386: 687b ldr r3, [r7, #4] 8004388: f893 303c ldrb.w r3, [r3, #60] ; 0x3c 800438c: 2b01 cmp r3, #1 800438e: d101 bne.n 8004394 8004390: 2302 movs r3, #2 8004392: e032 b.n 80043fa 8004394: 687b ldr r3, [r7, #4] 8004396: 2201 movs r2, #1 8004398: f883 203c strb.w r2, [r3, #60] ; 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 800439c: 687b ldr r3, [r7, #4] 800439e: 2202 movs r2, #2 80043a0: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 80043a4: 687b ldr r3, [r7, #4] 80043a6: 681b ldr r3, [r3, #0] 80043a8: 685b ldr r3, [r3, #4] 80043aa: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 80043ac: 687b ldr r3, [r7, #4] 80043ae: 681b ldr r3, [r3, #0] 80043b0: 689b ldr r3, [r3, #8] 80043b2: 60bb str r3, [r7, #8] /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 80043b4: 68fb ldr r3, [r7, #12] 80043b6: f023 0370 bic.w r3, r3, #112 ; 0x70 80043ba: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 80043bc: 683b ldr r3, [r7, #0] 80043be: 681b ldr r3, [r3, #0] 80043c0: 68fa ldr r2, [r7, #12] 80043c2: 4313 orrs r3, r2 80043c4: 60fb str r3, [r7, #12] /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 80043c6: 68bb ldr r3, [r7, #8] 80043c8: f023 0380 bic.w r3, r3, #128 ; 0x80 80043cc: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 80043ce: 683b ldr r3, [r7, #0] 80043d0: 685b ldr r3, [r3, #4] 80043d2: 68ba ldr r2, [r7, #8] 80043d4: 4313 orrs r3, r2 80043d6: 60bb str r3, [r7, #8] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 80043d8: 687b ldr r3, [r7, #4] 80043da: 681b ldr r3, [r3, #0] 80043dc: 68fa ldr r2, [r7, #12] 80043de: 605a str r2, [r3, #4] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 80043e0: 687b ldr r3, [r7, #4] 80043e2: 681b ldr r3, [r3, #0] 80043e4: 68ba ldr r2, [r7, #8] 80043e6: 609a str r2, [r3, #8] /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 80043e8: 687b ldr r3, [r7, #4] 80043ea: 2201 movs r2, #1 80043ec: f883 203d strb.w r2, [r3, #61] ; 0x3d __HAL_UNLOCK(htim); 80043f0: 687b ldr r3, [r7, #4] 80043f2: 2200 movs r2, #0 80043f4: f883 203c strb.w r2, [r3, #60] ; 0x3c return HAL_OK; 80043f8: 2300 movs r3, #0 } 80043fa: 4618 mov r0, r3 80043fc: 3714 adds r7, #20 80043fe: 46bd mov sp, r7 8004400: bc80 pop {r7} 8004402: 4770 bx lr 08004404 : * @brief Hall commutation changed callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { 8004404: b480 push {r7} 8004406: b083 sub sp, #12 8004408: af00 add r7, sp, #0 800440a: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } 800440c: bf00 nop 800440e: 370c adds r7, #12 8004410: 46bd mov sp, r7 8004412: bc80 pop {r7} 8004414: 4770 bx lr 08004416 : * @brief Hall Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { 8004416: b480 push {r7} 8004418: b083 sub sp, #12 800441a: af00 add r7, sp, #0 800441c: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } 800441e: bf00 nop 8004420: 370c adds r7, #12 8004422: 46bd mov sp, r7 8004424: bc80 pop {r7} 8004426: 4770 bx lr 08004428 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 8004428: b580 push {r7, lr} 800442a: b082 sub sp, #8 800442c: af00 add r7, sp, #0 800442e: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 8004430: 687b ldr r3, [r7, #4] 8004432: 2b00 cmp r3, #0 8004434: d101 bne.n 800443a { return HAL_ERROR; 8004436: 2301 movs r3, #1 8004438: e03f b.n 80044ba assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); #if defined(USART_CR1_OVER8) assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); #endif /* USART_CR1_OVER8 */ if (huart->gState == HAL_UART_STATE_RESET) 800443a: 687b ldr r3, [r7, #4] 800443c: f893 3039 ldrb.w r3, [r3, #57] ; 0x39 8004440: b2db uxtb r3, r3 8004442: 2b00 cmp r3, #0 8004444: d106 bne.n 8004454 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 8004446: 687b ldr r3, [r7, #4] 8004448: 2200 movs r2, #0 800444a: f883 2038 strb.w r2, [r3, #56] ; 0x38 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 800444e: 6878 ldr r0, [r7, #4] 8004450: f001 fa12 bl 8005878 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 8004454: 687b ldr r3, [r7, #4] 8004456: 2224 movs r2, #36 ; 0x24 8004458: f883 2039 strb.w r2, [r3, #57] ; 0x39 /* Disable the peripheral */ __HAL_UART_DISABLE(huart); 800445c: 687b ldr r3, [r7, #4] 800445e: 681b ldr r3, [r3, #0] 8004460: 68da ldr r2, [r3, #12] 8004462: 687b ldr r3, [r7, #4] 8004464: 681b ldr r3, [r3, #0] 8004466: f422 5200 bic.w r2, r2, #8192 ; 0x2000 800446a: 60da str r2, [r3, #12] /* Set the UART Communication parameters */ UART_SetConfig(huart); 800446c: 6878 ldr r0, [r7, #4] 800446e: f000 fc97 bl 8004da0 /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 8004472: 687b ldr r3, [r7, #4] 8004474: 681b ldr r3, [r3, #0] 8004476: 691a ldr r2, [r3, #16] 8004478: 687b ldr r3, [r7, #4] 800447a: 681b ldr r3, [r3, #0] 800447c: f422 4290 bic.w r2, r2, #18432 ; 0x4800 8004480: 611a str r2, [r3, #16] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 8004482: 687b ldr r3, [r7, #4] 8004484: 681b ldr r3, [r3, #0] 8004486: 695a ldr r2, [r3, #20] 8004488: 687b ldr r3, [r7, #4] 800448a: 681b ldr r3, [r3, #0] 800448c: f022 022a bic.w r2, r2, #42 ; 0x2a 8004490: 615a str r2, [r3, #20] /* Enable the peripheral */ __HAL_UART_ENABLE(huart); 8004492: 687b ldr r3, [r7, #4] 8004494: 681b ldr r3, [r3, #0] 8004496: 68da ldr r2, [r3, #12] 8004498: 687b ldr r3, [r7, #4] 800449a: 681b ldr r3, [r3, #0] 800449c: f442 5200 orr.w r2, r2, #8192 ; 0x2000 80044a0: 60da str r2, [r3, #12] /* Initialize the UART state */ huart->ErrorCode = HAL_UART_ERROR_NONE; 80044a2: 687b ldr r3, [r7, #4] 80044a4: 2200 movs r2, #0 80044a6: 63da str r2, [r3, #60] ; 0x3c huart->gState = HAL_UART_STATE_READY; 80044a8: 687b ldr r3, [r7, #4] 80044aa: 2220 movs r2, #32 80044ac: f883 2039 strb.w r2, [r3, #57] ; 0x39 huart->RxState = HAL_UART_STATE_READY; 80044b0: 687b ldr r3, [r7, #4] 80044b2: 2220 movs r2, #32 80044b4: f883 203a strb.w r2, [r3, #58] ; 0x3a return HAL_OK; 80044b8: 2300 movs r3, #0 } 80044ba: 4618 mov r0, r3 80044bc: 3708 adds r7, #8 80044be: 46bd mov sp, r7 80044c0: bd80 pop {r7, pc} 080044c2 : * @param Size Amount of data elements (u8 or u16) to be sent * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) { 80044c2: b580 push {r7, lr} 80044c4: b088 sub sp, #32 80044c6: af02 add r7, sp, #8 80044c8: 60f8 str r0, [r7, #12] 80044ca: 60b9 str r1, [r7, #8] 80044cc: 603b str r3, [r7, #0] 80044ce: 4613 mov r3, r2 80044d0: 80fb strh r3, [r7, #6] uint16_t *tmp; uint32_t tickstart = 0U; 80044d2: 2300 movs r3, #0 80044d4: 617b str r3, [r7, #20] /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 80044d6: 68fb ldr r3, [r7, #12] 80044d8: f893 3039 ldrb.w r3, [r3, #57] ; 0x39 80044dc: b2db uxtb r3, r3 80044de: 2b20 cmp r3, #32 80044e0: f040 8083 bne.w 80045ea { if ((pData == NULL) || (Size == 0U)) 80044e4: 68bb ldr r3, [r7, #8] 80044e6: 2b00 cmp r3, #0 80044e8: d002 beq.n 80044f0 80044ea: 88fb ldrh r3, [r7, #6] 80044ec: 2b00 cmp r3, #0 80044ee: d101 bne.n 80044f4 { return HAL_ERROR; 80044f0: 2301 movs r3, #1 80044f2: e07b b.n 80045ec } /* Process Locked */ __HAL_LOCK(huart); 80044f4: 68fb ldr r3, [r7, #12] 80044f6: f893 3038 ldrb.w r3, [r3, #56] ; 0x38 80044fa: 2b01 cmp r3, #1 80044fc: d101 bne.n 8004502 80044fe: 2302 movs r3, #2 8004500: e074 b.n 80045ec 8004502: 68fb ldr r3, [r7, #12] 8004504: 2201 movs r2, #1 8004506: f883 2038 strb.w r2, [r3, #56] ; 0x38 huart->ErrorCode = HAL_UART_ERROR_NONE; 800450a: 68fb ldr r3, [r7, #12] 800450c: 2200 movs r2, #0 800450e: 63da str r2, [r3, #60] ; 0x3c huart->gState = HAL_UART_STATE_BUSY_TX; 8004510: 68fb ldr r3, [r7, #12] 8004512: 2221 movs r2, #33 ; 0x21 8004514: f883 2039 strb.w r2, [r3, #57] ; 0x39 /* Init tickstart for timeout managment */ tickstart = HAL_GetTick(); 8004518: f7fd fc2e bl 8001d78 800451c: 6178 str r0, [r7, #20] huart->TxXferSize = Size; 800451e: 68fb ldr r3, [r7, #12] 8004520: 88fa ldrh r2, [r7, #6] 8004522: 849a strh r2, [r3, #36] ; 0x24 huart->TxXferCount = Size; 8004524: 68fb ldr r3, [r7, #12] 8004526: 88fa ldrh r2, [r7, #6] 8004528: 84da strh r2, [r3, #38] ; 0x26 while (huart->TxXferCount > 0U) 800452a: e042 b.n 80045b2 { huart->TxXferCount--; 800452c: 68fb ldr r3, [r7, #12] 800452e: 8cdb ldrh r3, [r3, #38] ; 0x26 8004530: b29b uxth r3, r3 8004532: 3b01 subs r3, #1 8004534: b29a uxth r2, r3 8004536: 68fb ldr r3, [r7, #12] 8004538: 84da strh r2, [r3, #38] ; 0x26 if (huart->Init.WordLength == UART_WORDLENGTH_9B) 800453a: 68fb ldr r3, [r7, #12] 800453c: 689b ldr r3, [r3, #8] 800453e: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8004542: d122 bne.n 800458a { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) 8004544: 683b ldr r3, [r7, #0] 8004546: 9300 str r3, [sp, #0] 8004548: 697b ldr r3, [r7, #20] 800454a: 2200 movs r2, #0 800454c: 2180 movs r1, #128 ; 0x80 800454e: 68f8 ldr r0, [r7, #12] 8004550: f000 faa8 bl 8004aa4 8004554: 4603 mov r3, r0 8004556: 2b00 cmp r3, #0 8004558: d001 beq.n 800455e { return HAL_TIMEOUT; 800455a: 2303 movs r3, #3 800455c: e046 b.n 80045ec } tmp = (uint16_t *) pData; 800455e: 68bb ldr r3, [r7, #8] 8004560: 613b str r3, [r7, #16] huart->Instance->DR = (*tmp & (uint16_t)0x01FF); 8004562: 693b ldr r3, [r7, #16] 8004564: 881b ldrh r3, [r3, #0] 8004566: 461a mov r2, r3 8004568: 68fb ldr r3, [r7, #12] 800456a: 681b ldr r3, [r3, #0] 800456c: f3c2 0208 ubfx r2, r2, #0, #9 8004570: 605a str r2, [r3, #4] if (huart->Init.Parity == UART_PARITY_NONE) 8004572: 68fb ldr r3, [r7, #12] 8004574: 691b ldr r3, [r3, #16] 8004576: 2b00 cmp r3, #0 8004578: d103 bne.n 8004582 { pData += 2U; 800457a: 68bb ldr r3, [r7, #8] 800457c: 3302 adds r3, #2 800457e: 60bb str r3, [r7, #8] 8004580: e017 b.n 80045b2 } else { pData += 1U; 8004582: 68bb ldr r3, [r7, #8] 8004584: 3301 adds r3, #1 8004586: 60bb str r3, [r7, #8] 8004588: e013 b.n 80045b2 } } else { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) 800458a: 683b ldr r3, [r7, #0] 800458c: 9300 str r3, [sp, #0] 800458e: 697b ldr r3, [r7, #20] 8004590: 2200 movs r2, #0 8004592: 2180 movs r1, #128 ; 0x80 8004594: 68f8 ldr r0, [r7, #12] 8004596: f000 fa85 bl 8004aa4 800459a: 4603 mov r3, r0 800459c: 2b00 cmp r3, #0 800459e: d001 beq.n 80045a4 { return HAL_TIMEOUT; 80045a0: 2303 movs r3, #3 80045a2: e023 b.n 80045ec } huart->Instance->DR = (*pData++ & (uint8_t)0xFF); 80045a4: 68bb ldr r3, [r7, #8] 80045a6: 1c5a adds r2, r3, #1 80045a8: 60ba str r2, [r7, #8] 80045aa: 781a ldrb r2, [r3, #0] 80045ac: 68fb ldr r3, [r7, #12] 80045ae: 681b ldr r3, [r3, #0] 80045b0: 605a str r2, [r3, #4] while (huart->TxXferCount > 0U) 80045b2: 68fb ldr r3, [r7, #12] 80045b4: 8cdb ldrh r3, [r3, #38] ; 0x26 80045b6: b29b uxth r3, r3 80045b8: 2b00 cmp r3, #0 80045ba: d1b7 bne.n 800452c } } if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) 80045bc: 683b ldr r3, [r7, #0] 80045be: 9300 str r3, [sp, #0] 80045c0: 697b ldr r3, [r7, #20] 80045c2: 2200 movs r2, #0 80045c4: 2140 movs r1, #64 ; 0x40 80045c6: 68f8 ldr r0, [r7, #12] 80045c8: f000 fa6c bl 8004aa4 80045cc: 4603 mov r3, r0 80045ce: 2b00 cmp r3, #0 80045d0: d001 beq.n 80045d6 { return HAL_TIMEOUT; 80045d2: 2303 movs r3, #3 80045d4: e00a b.n 80045ec } /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 80045d6: 68fb ldr r3, [r7, #12] 80045d8: 2220 movs r2, #32 80045da: f883 2039 strb.w r2, [r3, #57] ; 0x39 /* Process Unlocked */ __HAL_UNLOCK(huart); 80045de: 68fb ldr r3, [r7, #12] 80045e0: 2200 movs r2, #0 80045e2: f883 2038 strb.w r2, [r3, #56] ; 0x38 return HAL_OK; 80045e6: 2300 movs r3, #0 80045e8: e000 b.n 80045ec } else { return HAL_BUSY; 80045ea: 2302 movs r3, #2 } } 80045ec: 4618 mov r0, r3 80045ee: 3718 adds r7, #24 80045f0: 46bd mov sp, r7 80045f2: bd80 pop {r7, pc} 080045f4 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 80045f4: b480 push {r7} 80045f6: b085 sub sp, #20 80045f8: af00 add r7, sp, #0 80045fa: 60f8 str r0, [r7, #12] 80045fc: 60b9 str r1, [r7, #8] 80045fe: 4613 mov r3, r2 8004600: 80fb strh r3, [r7, #6] /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) 8004602: 68fb ldr r3, [r7, #12] 8004604: f893 303a ldrb.w r3, [r3, #58] ; 0x3a 8004608: b2db uxtb r3, r3 800460a: 2b20 cmp r3, #32 800460c: d140 bne.n 8004690 { if ((pData == NULL) || (Size == 0U)) 800460e: 68bb ldr r3, [r7, #8] 8004610: 2b00 cmp r3, #0 8004612: d002 beq.n 800461a 8004614: 88fb ldrh r3, [r7, #6] 8004616: 2b00 cmp r3, #0 8004618: d101 bne.n 800461e { return HAL_ERROR; 800461a: 2301 movs r3, #1 800461c: e039 b.n 8004692 } /* Process Locked */ __HAL_LOCK(huart); 800461e: 68fb ldr r3, [r7, #12] 8004620: f893 3038 ldrb.w r3, [r3, #56] ; 0x38 8004624: 2b01 cmp r3, #1 8004626: d101 bne.n 800462c 8004628: 2302 movs r3, #2 800462a: e032 b.n 8004692 800462c: 68fb ldr r3, [r7, #12] 800462e: 2201 movs r2, #1 8004630: f883 2038 strb.w r2, [r3, #56] ; 0x38 huart->pRxBuffPtr = pData; 8004634: 68fb ldr r3, [r7, #12] 8004636: 68ba ldr r2, [r7, #8] 8004638: 629a str r2, [r3, #40] ; 0x28 huart->RxXferSize = Size; 800463a: 68fb ldr r3, [r7, #12] 800463c: 88fa ldrh r2, [r7, #6] 800463e: 859a strh r2, [r3, #44] ; 0x2c huart->RxXferCount = Size; 8004640: 68fb ldr r3, [r7, #12] 8004642: 88fa ldrh r2, [r7, #6] 8004644: 85da strh r2, [r3, #46] ; 0x2e huart->ErrorCode = HAL_UART_ERROR_NONE; 8004646: 68fb ldr r3, [r7, #12] 8004648: 2200 movs r2, #0 800464a: 63da str r2, [r3, #60] ; 0x3c huart->RxState = HAL_UART_STATE_BUSY_RX; 800464c: 68fb ldr r3, [r7, #12] 800464e: 2222 movs r2, #34 ; 0x22 8004650: f883 203a strb.w r2, [r3, #58] ; 0x3a /* Process Unlocked */ __HAL_UNLOCK(huart); 8004654: 68fb ldr r3, [r7, #12] 8004656: 2200 movs r2, #0 8004658: f883 2038 strb.w r2, [r3, #56] ; 0x38 /* Enable the UART Parity Error Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_PE); 800465c: 68fb ldr r3, [r7, #12] 800465e: 681b ldr r3, [r3, #0] 8004660: 68da ldr r2, [r3, #12] 8004662: 68fb ldr r3, [r7, #12] 8004664: 681b ldr r3, [r3, #0] 8004666: f442 7280 orr.w r2, r2, #256 ; 0x100 800466a: 60da str r2, [r3, #12] /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_ENABLE_IT(huart, UART_IT_ERR); 800466c: 68fb ldr r3, [r7, #12] 800466e: 681b ldr r3, [r3, #0] 8004670: 695a ldr r2, [r3, #20] 8004672: 68fb ldr r3, [r7, #12] 8004674: 681b ldr r3, [r3, #0] 8004676: f042 0201 orr.w r2, r2, #1 800467a: 615a str r2, [r3, #20] /* Enable the UART Data Register not empty Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE); 800467c: 68fb ldr r3, [r7, #12] 800467e: 681b ldr r3, [r3, #0] 8004680: 68da ldr r2, [r3, #12] 8004682: 68fb ldr r3, [r7, #12] 8004684: 681b ldr r3, [r3, #0] 8004686: f042 0220 orr.w r2, r2, #32 800468a: 60da str r2, [r3, #12] return HAL_OK; 800468c: 2300 movs r3, #0 800468e: e000 b.n 8004692 } else { return HAL_BUSY; 8004690: 2302 movs r3, #2 } } 8004692: 4618 mov r0, r3 8004694: 3714 adds r7, #20 8004696: 46bd mov sp, r7 8004698: bc80 pop {r7} 800469a: 4770 bx lr 0800469c : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 800469c: b580 push {r7, lr} 800469e: b086 sub sp, #24 80046a0: af00 add r7, sp, #0 80046a2: 60f8 str r0, [r7, #12] 80046a4: 60b9 str r1, [r7, #8] 80046a6: 4613 mov r3, r2 80046a8: 80fb strh r3, [r7, #6] uint32_t *tmp; /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 80046aa: 68fb ldr r3, [r7, #12] 80046ac: f893 3039 ldrb.w r3, [r3, #57] ; 0x39 80046b0: b2db uxtb r3, r3 80046b2: 2b20 cmp r3, #32 80046b4: d153 bne.n 800475e { if ((pData == NULL) || (Size == 0U)) 80046b6: 68bb ldr r3, [r7, #8] 80046b8: 2b00 cmp r3, #0 80046ba: d002 beq.n 80046c2 80046bc: 88fb ldrh r3, [r7, #6] 80046be: 2b00 cmp r3, #0 80046c0: d101 bne.n 80046c6 { return HAL_ERROR; 80046c2: 2301 movs r3, #1 80046c4: e04c b.n 8004760 } /* Process Locked */ __HAL_LOCK(huart); 80046c6: 68fb ldr r3, [r7, #12] 80046c8: f893 3038 ldrb.w r3, [r3, #56] ; 0x38 80046cc: 2b01 cmp r3, #1 80046ce: d101 bne.n 80046d4 80046d0: 2302 movs r3, #2 80046d2: e045 b.n 8004760 80046d4: 68fb ldr r3, [r7, #12] 80046d6: 2201 movs r2, #1 80046d8: f883 2038 strb.w r2, [r3, #56] ; 0x38 huart->pTxBuffPtr = pData; 80046dc: 68ba ldr r2, [r7, #8] 80046de: 68fb ldr r3, [r7, #12] 80046e0: 621a str r2, [r3, #32] huart->TxXferSize = Size; 80046e2: 68fb ldr r3, [r7, #12] 80046e4: 88fa ldrh r2, [r7, #6] 80046e6: 849a strh r2, [r3, #36] ; 0x24 huart->TxXferCount = Size; 80046e8: 68fb ldr r3, [r7, #12] 80046ea: 88fa ldrh r2, [r7, #6] 80046ec: 84da strh r2, [r3, #38] ; 0x26 huart->ErrorCode = HAL_UART_ERROR_NONE; 80046ee: 68fb ldr r3, [r7, #12] 80046f0: 2200 movs r2, #0 80046f2: 63da str r2, [r3, #60] ; 0x3c huart->gState = HAL_UART_STATE_BUSY_TX; 80046f4: 68fb ldr r3, [r7, #12] 80046f6: 2221 movs r2, #33 ; 0x21 80046f8: f883 2039 strb.w r2, [r3, #57] ; 0x39 /* Set the UART DMA transfer complete callback */ huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; 80046fc: 68fb ldr r3, [r7, #12] 80046fe: 6b1b ldr r3, [r3, #48] ; 0x30 8004700: 4a19 ldr r2, [pc, #100] ; (8004768 ) 8004702: 629a str r2, [r3, #40] ; 0x28 /* Set the UART DMA Half transfer complete callback */ huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; 8004704: 68fb ldr r3, [r7, #12] 8004706: 6b1b ldr r3, [r3, #48] ; 0x30 8004708: 4a18 ldr r2, [pc, #96] ; (800476c ) 800470a: 62da str r2, [r3, #44] ; 0x2c /* Set the DMA error callback */ huart->hdmatx->XferErrorCallback = UART_DMAError; 800470c: 68fb ldr r3, [r7, #12] 800470e: 6b1b ldr r3, [r3, #48] ; 0x30 8004710: 4a17 ldr r2, [pc, #92] ; (8004770 ) 8004712: 631a str r2, [r3, #48] ; 0x30 /* Set the DMA abort callback */ huart->hdmatx->XferAbortCallback = NULL; 8004714: 68fb ldr r3, [r7, #12] 8004716: 6b1b ldr r3, [r3, #48] ; 0x30 8004718: 2200 movs r2, #0 800471a: 635a str r2, [r3, #52] ; 0x34 /* Enable the UART transmit DMA channel */ tmp = (uint32_t *)&pData; 800471c: f107 0308 add.w r3, r7, #8 8004720: 617b str r3, [r7, #20] HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t *)tmp, (uint32_t)&huart->Instance->DR, Size); 8004722: 68fb ldr r3, [r7, #12] 8004724: 6b18 ldr r0, [r3, #48] ; 0x30 8004726: 697b ldr r3, [r7, #20] 8004728: 6819 ldr r1, [r3, #0] 800472a: 68fb ldr r3, [r7, #12] 800472c: 681b ldr r3, [r3, #0] 800472e: 3304 adds r3, #4 8004730: 461a mov r2, r3 8004732: 88fb ldrh r3, [r7, #6] 8004734: f7fe f966 bl 8002a04 /* Clear the TC flag in the SR register by writing 0 to it */ __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC); 8004738: 68fb ldr r3, [r7, #12] 800473a: 681b ldr r3, [r3, #0] 800473c: f06f 0240 mvn.w r2, #64 ; 0x40 8004740: 601a str r2, [r3, #0] /* Process Unlocked */ __HAL_UNLOCK(huart); 8004742: 68fb ldr r3, [r7, #12] 8004744: 2200 movs r2, #0 8004746: f883 2038 strb.w r2, [r3, #56] ; 0x38 /* Enable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); 800474a: 68fb ldr r3, [r7, #12] 800474c: 681b ldr r3, [r3, #0] 800474e: 695a ldr r2, [r3, #20] 8004750: 68fb ldr r3, [r7, #12] 8004752: 681b ldr r3, [r3, #0] 8004754: f042 0280 orr.w r2, r2, #128 ; 0x80 8004758: 615a str r2, [r3, #20] return HAL_OK; 800475a: 2300 movs r3, #0 800475c: e000 b.n 8004760 } else { return HAL_BUSY; 800475e: 2302 movs r3, #2 } } 8004760: 4618 mov r0, r3 8004762: 3718 adds r7, #24 8004764: 46bd mov sp, r7 8004766: bd80 pop {r7, pc} 8004768: 080049a3 .word 0x080049a3 800476c: 080049f5 .word 0x080049f5 8004770: 08004a11 .word 0x08004a11 08004774 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { 8004774: b580 push {r7, lr} 8004776: b088 sub sp, #32 8004778: af00 add r7, sp, #0 800477a: 6078 str r0, [r7, #4] uint32_t isrflags = READ_REG(huart->Instance->SR); 800477c: 687b ldr r3, [r7, #4] 800477e: 681b ldr r3, [r3, #0] 8004780: 681b ldr r3, [r3, #0] 8004782: 61fb str r3, [r7, #28] uint32_t cr1its = READ_REG(huart->Instance->CR1); 8004784: 687b ldr r3, [r7, #4] 8004786: 681b ldr r3, [r3, #0] 8004788: 68db ldr r3, [r3, #12] 800478a: 61bb str r3, [r7, #24] uint32_t cr3its = READ_REG(huart->Instance->CR3); 800478c: 687b ldr r3, [r7, #4] 800478e: 681b ldr r3, [r3, #0] 8004790: 695b ldr r3, [r3, #20] 8004792: 617b str r3, [r7, #20] uint32_t errorflags = 0x00U; 8004794: 2300 movs r3, #0 8004796: 613b str r3, [r7, #16] uint32_t dmarequest = 0x00U; 8004798: 2300 movs r3, #0 800479a: 60fb str r3, [r7, #12] /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE)); 800479c: 69fb ldr r3, [r7, #28] 800479e: f003 030f and.w r3, r3, #15 80047a2: 613b str r3, [r7, #16] if (errorflags == RESET) 80047a4: 693b ldr r3, [r7, #16] 80047a6: 2b00 cmp r3, #0 80047a8: d10d bne.n 80047c6 { /* UART in mode Receiver -------------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 80047aa: 69fb ldr r3, [r7, #28] 80047ac: f003 0320 and.w r3, r3, #32 80047b0: 2b00 cmp r3, #0 80047b2: d008 beq.n 80047c6 80047b4: 69bb ldr r3, [r7, #24] 80047b6: f003 0320 and.w r3, r3, #32 80047ba: 2b00 cmp r3, #0 80047bc: d003 beq.n 80047c6 { UART_Receive_IT(huart); 80047be: 6878 ldr r0, [r7, #4] 80047c0: f000 fa6d bl 8004c9e return; 80047c4: e0cc b.n 8004960 } } /* If some errors occur */ if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) 80047c6: 693b ldr r3, [r7, #16] 80047c8: 2b00 cmp r3, #0 80047ca: f000 80ab beq.w 8004924 80047ce: 697b ldr r3, [r7, #20] 80047d0: f003 0301 and.w r3, r3, #1 80047d4: 2b00 cmp r3, #0 80047d6: d105 bne.n 80047e4 80047d8: 69bb ldr r3, [r7, #24] 80047da: f403 7390 and.w r3, r3, #288 ; 0x120 80047de: 2b00 cmp r3, #0 80047e0: f000 80a0 beq.w 8004924 { /* UART parity error interrupt occurred ----------------------------------*/ if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) 80047e4: 69fb ldr r3, [r7, #28] 80047e6: f003 0301 and.w r3, r3, #1 80047ea: 2b00 cmp r3, #0 80047ec: d00a beq.n 8004804 80047ee: 69bb ldr r3, [r7, #24] 80047f0: f403 7380 and.w r3, r3, #256 ; 0x100 80047f4: 2b00 cmp r3, #0 80047f6: d005 beq.n 8004804 { huart->ErrorCode |= HAL_UART_ERROR_PE; 80047f8: 687b ldr r3, [r7, #4] 80047fa: 6bdb ldr r3, [r3, #60] ; 0x3c 80047fc: f043 0201 orr.w r2, r3, #1 8004800: 687b ldr r3, [r7, #4] 8004802: 63da str r2, [r3, #60] ; 0x3c } /* UART noise error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 8004804: 69fb ldr r3, [r7, #28] 8004806: f003 0304 and.w r3, r3, #4 800480a: 2b00 cmp r3, #0 800480c: d00a beq.n 8004824 800480e: 697b ldr r3, [r7, #20] 8004810: f003 0301 and.w r3, r3, #1 8004814: 2b00 cmp r3, #0 8004816: d005 beq.n 8004824 { huart->ErrorCode |= HAL_UART_ERROR_NE; 8004818: 687b ldr r3, [r7, #4] 800481a: 6bdb ldr r3, [r3, #60] ; 0x3c 800481c: f043 0202 orr.w r2, r3, #2 8004820: 687b ldr r3, [r7, #4] 8004822: 63da str r2, [r3, #60] ; 0x3c } /* UART frame error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 8004824: 69fb ldr r3, [r7, #28] 8004826: f003 0302 and.w r3, r3, #2 800482a: 2b00 cmp r3, #0 800482c: d00a beq.n 8004844 800482e: 697b ldr r3, [r7, #20] 8004830: f003 0301 and.w r3, r3, #1 8004834: 2b00 cmp r3, #0 8004836: d005 beq.n 8004844 { huart->ErrorCode |= HAL_UART_ERROR_FE; 8004838: 687b ldr r3, [r7, #4] 800483a: 6bdb ldr r3, [r3, #60] ; 0x3c 800483c: f043 0204 orr.w r2, r3, #4 8004840: 687b ldr r3, [r7, #4] 8004842: 63da str r2, [r3, #60] ; 0x3c } /* UART Over-Run interrupt occurred --------------------------------------*/ if (((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 8004844: 69fb ldr r3, [r7, #28] 8004846: f003 0308 and.w r3, r3, #8 800484a: 2b00 cmp r3, #0 800484c: d00a beq.n 8004864 800484e: 697b ldr r3, [r7, #20] 8004850: f003 0301 and.w r3, r3, #1 8004854: 2b00 cmp r3, #0 8004856: d005 beq.n 8004864 { huart->ErrorCode |= HAL_UART_ERROR_ORE; 8004858: 687b ldr r3, [r7, #4] 800485a: 6bdb ldr r3, [r3, #60] ; 0x3c 800485c: f043 0208 orr.w r2, r3, #8 8004860: 687b ldr r3, [r7, #4] 8004862: 63da str r2, [r3, #60] ; 0x3c } /* Call UART Error Call back function if need be --------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 8004864: 687b ldr r3, [r7, #4] 8004866: 6bdb ldr r3, [r3, #60] ; 0x3c 8004868: 2b00 cmp r3, #0 800486a: d078 beq.n 800495e { /* UART in mode Receiver -----------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 800486c: 69fb ldr r3, [r7, #28] 800486e: f003 0320 and.w r3, r3, #32 8004872: 2b00 cmp r3, #0 8004874: d007 beq.n 8004886 8004876: 69bb ldr r3, [r7, #24] 8004878: f003 0320 and.w r3, r3, #32 800487c: 2b00 cmp r3, #0 800487e: d002 beq.n 8004886 { UART_Receive_IT(huart); 8004880: 6878 ldr r0, [r7, #4] 8004882: f000 fa0c bl 8004c9e } /* If Overrun error occurs, or if any error occurs in DMA mode reception, consider error as blocking */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 8004886: 687b ldr r3, [r7, #4] 8004888: 681b ldr r3, [r3, #0] 800488a: 695b ldr r3, [r3, #20] 800488c: f003 0340 and.w r3, r3, #64 ; 0x40 8004890: 2b00 cmp r3, #0 8004892: bf14 ite ne 8004894: 2301 movne r3, #1 8004896: 2300 moveq r3, #0 8004898: b2db uxtb r3, r3 800489a: 60fb str r3, [r7, #12] if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest) 800489c: 687b ldr r3, [r7, #4] 800489e: 6bdb ldr r3, [r3, #60] ; 0x3c 80048a0: f003 0308 and.w r3, r3, #8 80048a4: 2b00 cmp r3, #0 80048a6: d102 bne.n 80048ae 80048a8: 68fb ldr r3, [r7, #12] 80048aa: 2b00 cmp r3, #0 80048ac: d031 beq.n 8004912 { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); 80048ae: 6878 ldr r0, [r7, #4] 80048b0: f000 f957 bl 8004b62 /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80048b4: 687b ldr r3, [r7, #4] 80048b6: 681b ldr r3, [r3, #0] 80048b8: 695b ldr r3, [r3, #20] 80048ba: f003 0340 and.w r3, r3, #64 ; 0x40 80048be: 2b00 cmp r3, #0 80048c0: d023 beq.n 800490a { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 80048c2: 687b ldr r3, [r7, #4] 80048c4: 681b ldr r3, [r3, #0] 80048c6: 695a ldr r2, [r3, #20] 80048c8: 687b ldr r3, [r7, #4] 80048ca: 681b ldr r3, [r3, #0] 80048cc: f022 0240 bic.w r2, r2, #64 ; 0x40 80048d0: 615a str r2, [r3, #20] /* Abort the UART DMA Rx channel */ if (huart->hdmarx != NULL) 80048d2: 687b ldr r3, [r7, #4] 80048d4: 6b5b ldr r3, [r3, #52] ; 0x34 80048d6: 2b00 cmp r3, #0 80048d8: d013 beq.n 8004902 { /* Set the UART DMA Abort callback : will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; 80048da: 687b ldr r3, [r7, #4] 80048dc: 6b5b ldr r3, [r3, #52] ; 0x34 80048de: 4a22 ldr r2, [pc, #136] ; (8004968 ) 80048e0: 635a str r2, [r3, #52] ; 0x34 if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 80048e2: 687b ldr r3, [r7, #4] 80048e4: 6b5b ldr r3, [r3, #52] ; 0x34 80048e6: 4618 mov r0, r3 80048e8: f7fe f8ec bl 8002ac4 80048ec: 4603 mov r3, r0 80048ee: 2b00 cmp r3, #0 80048f0: d016 beq.n 8004920 { /* Call Directly XferAbortCallback function in case of error */ huart->hdmarx->XferAbortCallback(huart->hdmarx); 80048f2: 687b ldr r3, [r7, #4] 80048f4: 6b5b ldr r3, [r3, #52] ; 0x34 80048f6: 6b5b ldr r3, [r3, #52] ; 0x34 80048f8: 687a ldr r2, [r7, #4] 80048fa: 6b52 ldr r2, [r2, #52] ; 0x34 80048fc: 4610 mov r0, r2 80048fe: 4798 blx r3 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8004900: e00e b.n 8004920 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8004902: 6878 ldr r0, [r7, #4] 8004904: f000 f844 bl 8004990 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8004908: e00a b.n 8004920 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 800490a: 6878 ldr r0, [r7, #4] 800490c: f000 f840 bl 8004990 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8004910: e006 b.n 8004920 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8004912: 6878 ldr r0, [r7, #4] 8004914: f000 f83c bl 8004990 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8004918: 687b ldr r3, [r7, #4] 800491a: 2200 movs r2, #0 800491c: 63da str r2, [r3, #60] ; 0x3c } } return; 800491e: e01e b.n 800495e if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8004920: bf00 nop return; 8004922: e01c b.n 800495e } /* End if some error occurs */ /* UART in mode Transmitter ------------------------------------------------*/ if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) 8004924: 69fb ldr r3, [r7, #28] 8004926: f003 0380 and.w r3, r3, #128 ; 0x80 800492a: 2b00 cmp r3, #0 800492c: d008 beq.n 8004940 800492e: 69bb ldr r3, [r7, #24] 8004930: f003 0380 and.w r3, r3, #128 ; 0x80 8004934: 2b00 cmp r3, #0 8004936: d003 beq.n 8004940 { UART_Transmit_IT(huart); 8004938: 6878 ldr r0, [r7, #4] 800493a: f000 f943 bl 8004bc4 return; 800493e: e00f b.n 8004960 } /* UART in mode Transmitter end --------------------------------------------*/ if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) 8004940: 69fb ldr r3, [r7, #28] 8004942: f003 0340 and.w r3, r3, #64 ; 0x40 8004946: 2b00 cmp r3, #0 8004948: d00a beq.n 8004960 800494a: 69bb ldr r3, [r7, #24] 800494c: f003 0340 and.w r3, r3, #64 ; 0x40 8004950: 2b00 cmp r3, #0 8004952: d005 beq.n 8004960 { UART_EndTransmit_IT(huart); 8004954: 6878 ldr r0, [r7, #4] 8004956: f000 f98a bl 8004c6e return; 800495a: bf00 nop 800495c: e000 b.n 8004960 return; 800495e: bf00 nop } } 8004960: 3720 adds r7, #32 8004962: 46bd mov sp, r7 8004964: bd80 pop {r7, pc} 8004966: bf00 nop 8004968: 08004b9d .word 0x08004b9d 0800496c : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { 800496c: b480 push {r7} 800496e: b083 sub sp, #12 8004970: af00 add r7, sp, #0 8004972: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_TxCpltCallback could be implemented in the user file */ } 8004974: bf00 nop 8004976: 370c adds r7, #12 8004978: 46bd mov sp, r7 800497a: bc80 pop {r7} 800497c: 4770 bx lr 0800497e : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) { 800497e: b480 push {r7} 8004980: b083 sub sp, #12 8004982: af00 add r7, sp, #0 8004984: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_TxHalfCpltCallback could be implemented in the user file */ } 8004986: bf00 nop 8004988: 370c adds r7, #12 800498a: 46bd mov sp, r7 800498c: bc80 pop {r7} 800498e: 4770 bx lr 08004990 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { 8004990: b480 push {r7} 8004992: b083 sub sp, #12 8004994: af00 add r7, sp, #0 8004996: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_ErrorCallback could be implemented in the user file */ } 8004998: bf00 nop 800499a: 370c adds r7, #12 800499c: 46bd mov sp, r7 800499e: bc80 pop {r7} 80049a0: 4770 bx lr 080049a2 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) { 80049a2: b580 push {r7, lr} 80049a4: b084 sub sp, #16 80049a6: af00 add r7, sp, #0 80049a8: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 80049aa: 687b ldr r3, [r7, #4] 80049ac: 6a5b ldr r3, [r3, #36] ; 0x24 80049ae: 60fb str r3, [r7, #12] /* DMA Normal mode*/ if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 80049b0: 687b ldr r3, [r7, #4] 80049b2: 681b ldr r3, [r3, #0] 80049b4: 681b ldr r3, [r3, #0] 80049b6: f003 0320 and.w r3, r3, #32 80049ba: 2b00 cmp r3, #0 80049bc: d113 bne.n 80049e6 { huart->TxXferCount = 0x00U; 80049be: 68fb ldr r3, [r7, #12] 80049c0: 2200 movs r2, #0 80049c2: 84da strh r2, [r3, #38] ; 0x26 /* Disable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); 80049c4: 68fb ldr r3, [r7, #12] 80049c6: 681b ldr r3, [r3, #0] 80049c8: 695a ldr r2, [r3, #20] 80049ca: 68fb ldr r3, [r7, #12] 80049cc: 681b ldr r3, [r3, #0] 80049ce: f022 0280 bic.w r2, r2, #128 ; 0x80 80049d2: 615a str r2, [r3, #20] /* Enable the UART Transmit Complete Interrupt */ SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 80049d4: 68fb ldr r3, [r7, #12] 80049d6: 681b ldr r3, [r3, #0] 80049d8: 68da ldr r2, [r3, #12] 80049da: 68fb ldr r3, [r7, #12] 80049dc: 681b ldr r3, [r3, #0] 80049de: f042 0240 orr.w r2, r2, #64 ; 0x40 80049e2: 60da str r2, [r3, #12] #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } 80049e4: e002 b.n 80049ec HAL_UART_TxCpltCallback(huart); 80049e6: 68f8 ldr r0, [r7, #12] 80049e8: f7ff ffc0 bl 800496c } 80049ec: bf00 nop 80049ee: 3710 adds r7, #16 80049f0: 46bd mov sp, r7 80049f2: bd80 pop {r7, pc} 080049f4 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) { 80049f4: b580 push {r7, lr} 80049f6: b084 sub sp, #16 80049f8: af00 add r7, sp, #0 80049fa: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 80049fc: 687b ldr r3, [r7, #4] 80049fe: 6a5b ldr r3, [r3, #36] ; 0x24 8004a00: 60fb str r3, [r7, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxHalfCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxHalfCpltCallback(huart); 8004a02: 68f8 ldr r0, [r7, #12] 8004a04: f7ff ffbb bl 800497e #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8004a08: bf00 nop 8004a0a: 3710 adds r7, #16 8004a0c: 46bd mov sp, r7 8004a0e: bd80 pop {r7, pc} 08004a10 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAError(DMA_HandleTypeDef *hdma) { 8004a10: b580 push {r7, lr} 8004a12: b084 sub sp, #16 8004a14: af00 add r7, sp, #0 8004a16: 6078 str r0, [r7, #4] uint32_t dmarequest = 0x00U; 8004a18: 2300 movs r3, #0 8004a1a: 60fb str r3, [r7, #12] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8004a1c: 687b ldr r3, [r7, #4] 8004a1e: 6a5b ldr r3, [r3, #36] ; 0x24 8004a20: 60bb str r3, [r7, #8] /* Stop UART DMA Tx request if ongoing */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT); 8004a22: 68bb ldr r3, [r7, #8] 8004a24: 681b ldr r3, [r3, #0] 8004a26: 695b ldr r3, [r3, #20] 8004a28: f003 0380 and.w r3, r3, #128 ; 0x80 8004a2c: 2b00 cmp r3, #0 8004a2e: bf14 ite ne 8004a30: 2301 movne r3, #1 8004a32: 2300 moveq r3, #0 8004a34: b2db uxtb r3, r3 8004a36: 60fb str r3, [r7, #12] if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) 8004a38: 68bb ldr r3, [r7, #8] 8004a3a: f893 3039 ldrb.w r3, [r3, #57] ; 0x39 8004a3e: b2db uxtb r3, r3 8004a40: 2b21 cmp r3, #33 ; 0x21 8004a42: d108 bne.n 8004a56 8004a44: 68fb ldr r3, [r7, #12] 8004a46: 2b00 cmp r3, #0 8004a48: d005 beq.n 8004a56 { huart->TxXferCount = 0x00U; 8004a4a: 68bb ldr r3, [r7, #8] 8004a4c: 2200 movs r2, #0 8004a4e: 84da strh r2, [r3, #38] ; 0x26 UART_EndTxTransfer(huart); 8004a50: 68b8 ldr r0, [r7, #8] 8004a52: f000 f871 bl 8004b38 } /* Stop UART DMA Rx request if ongoing */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 8004a56: 68bb ldr r3, [r7, #8] 8004a58: 681b ldr r3, [r3, #0] 8004a5a: 695b ldr r3, [r3, #20] 8004a5c: f003 0340 and.w r3, r3, #64 ; 0x40 8004a60: 2b00 cmp r3, #0 8004a62: bf14 ite ne 8004a64: 2301 movne r3, #1 8004a66: 2300 moveq r3, #0 8004a68: b2db uxtb r3, r3 8004a6a: 60fb str r3, [r7, #12] if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest) 8004a6c: 68bb ldr r3, [r7, #8] 8004a6e: f893 303a ldrb.w r3, [r3, #58] ; 0x3a 8004a72: b2db uxtb r3, r3 8004a74: 2b22 cmp r3, #34 ; 0x22 8004a76: d108 bne.n 8004a8a 8004a78: 68fb ldr r3, [r7, #12] 8004a7a: 2b00 cmp r3, #0 8004a7c: d005 beq.n 8004a8a { huart->RxXferCount = 0x00U; 8004a7e: 68bb ldr r3, [r7, #8] 8004a80: 2200 movs r2, #0 8004a82: 85da strh r2, [r3, #46] ; 0x2e UART_EndRxTransfer(huart); 8004a84: 68b8 ldr r0, [r7, #8] 8004a86: f000 f86c bl 8004b62 } huart->ErrorCode |= HAL_UART_ERROR_DMA; 8004a8a: 68bb ldr r3, [r7, #8] 8004a8c: 6bdb ldr r3, [r3, #60] ; 0x3c 8004a8e: f043 0210 orr.w r2, r3, #16 8004a92: 68bb ldr r3, [r7, #8] 8004a94: 63da str r2, [r3, #60] ; 0x3c #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8004a96: 68b8 ldr r0, [r7, #8] 8004a98: f7ff ff7a bl 8004990 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8004a9c: bf00 nop 8004a9e: 3710 adds r7, #16 8004aa0: 46bd mov sp, r7 8004aa2: bd80 pop {r7, pc} 08004aa4 : * @param Tickstart Tick start value * @param Timeout Timeout duration * @retval HAL status */ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { 8004aa4: b580 push {r7, lr} 8004aa6: b084 sub sp, #16 8004aa8: af00 add r7, sp, #0 8004aaa: 60f8 str r0, [r7, #12] 8004aac: 60b9 str r1, [r7, #8] 8004aae: 603b str r3, [r7, #0] 8004ab0: 4613 mov r3, r2 8004ab2: 71fb strb r3, [r7, #7] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8004ab4: e02c b.n 8004b10 { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 8004ab6: 69bb ldr r3, [r7, #24] 8004ab8: f1b3 3fff cmp.w r3, #4294967295 8004abc: d028 beq.n 8004b10 { if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) 8004abe: 69bb ldr r3, [r7, #24] 8004ac0: 2b00 cmp r3, #0 8004ac2: d007 beq.n 8004ad4 8004ac4: f7fd f958 bl 8001d78 8004ac8: 4602 mov r2, r0 8004aca: 683b ldr r3, [r7, #0] 8004acc: 1ad3 subs r3, r2, r3 8004ace: 69ba ldr r2, [r7, #24] 8004ad0: 429a cmp r2, r3 8004ad2: d21d bcs.n 8004b10 { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); 8004ad4: 68fb ldr r3, [r7, #12] 8004ad6: 681b ldr r3, [r3, #0] 8004ad8: 68da ldr r2, [r3, #12] 8004ada: 68fb ldr r3, [r7, #12] 8004adc: 681b ldr r3, [r3, #0] 8004ade: f422 72d0 bic.w r2, r2, #416 ; 0x1a0 8004ae2: 60da str r2, [r3, #12] CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8004ae4: 68fb ldr r3, [r7, #12] 8004ae6: 681b ldr r3, [r3, #0] 8004ae8: 695a ldr r2, [r3, #20] 8004aea: 68fb ldr r3, [r7, #12] 8004aec: 681b ldr r3, [r3, #0] 8004aee: f022 0201 bic.w r2, r2, #1 8004af2: 615a str r2, [r3, #20] huart->gState = HAL_UART_STATE_READY; 8004af4: 68fb ldr r3, [r7, #12] 8004af6: 2220 movs r2, #32 8004af8: f883 2039 strb.w r2, [r3, #57] ; 0x39 huart->RxState = HAL_UART_STATE_READY; 8004afc: 68fb ldr r3, [r7, #12] 8004afe: 2220 movs r2, #32 8004b00: f883 203a strb.w r2, [r3, #58] ; 0x3a /* Process Unlocked */ __HAL_UNLOCK(huart); 8004b04: 68fb ldr r3, [r7, #12] 8004b06: 2200 movs r2, #0 8004b08: f883 2038 strb.w r2, [r3, #56] ; 0x38 return HAL_TIMEOUT; 8004b0c: 2303 movs r3, #3 8004b0e: e00f b.n 8004b30 while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8004b10: 68fb ldr r3, [r7, #12] 8004b12: 681b ldr r3, [r3, #0] 8004b14: 681a ldr r2, [r3, #0] 8004b16: 68bb ldr r3, [r7, #8] 8004b18: 4013 ands r3, r2 8004b1a: 68ba ldr r2, [r7, #8] 8004b1c: 429a cmp r2, r3 8004b1e: bf0c ite eq 8004b20: 2301 moveq r3, #1 8004b22: 2300 movne r3, #0 8004b24: b2db uxtb r3, r3 8004b26: 461a mov r2, r3 8004b28: 79fb ldrb r3, [r7, #7] 8004b2a: 429a cmp r2, r3 8004b2c: d0c3 beq.n 8004ab6 } } } return HAL_OK; 8004b2e: 2300 movs r3, #0 } 8004b30: 4618 mov r0, r3 8004b32: 3710 adds r7, #16 8004b34: 46bd mov sp, r7 8004b36: bd80 pop {r7, pc} 08004b38 : * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). * @param huart UART handle. * @retval None */ static void UART_EndTxTransfer(UART_HandleTypeDef *huart) { 8004b38: b480 push {r7} 8004b3a: b083 sub sp, #12 8004b3c: af00 add r7, sp, #0 8004b3e: 6078 str r0, [r7, #4] /* Disable TXEIE and TCIE interrupts */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); 8004b40: 687b ldr r3, [r7, #4] 8004b42: 681b ldr r3, [r3, #0] 8004b44: 68da ldr r2, [r3, #12] 8004b46: 687b ldr r3, [r7, #4] 8004b48: 681b ldr r3, [r3, #0] 8004b4a: f022 02c0 bic.w r2, r2, #192 ; 0xc0 8004b4e: 60da str r2, [r3, #12] /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8004b50: 687b ldr r3, [r7, #4] 8004b52: 2220 movs r2, #32 8004b54: f883 2039 strb.w r2, [r3, #57] ; 0x39 } 8004b58: bf00 nop 8004b5a: 370c adds r7, #12 8004b5c: 46bd mov sp, r7 8004b5e: bc80 pop {r7} 8004b60: 4770 bx lr 08004b62 : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 8004b62: b480 push {r7} 8004b64: b083 sub sp, #12 8004b66: af00 add r7, sp, #0 8004b68: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 8004b6a: 687b ldr r3, [r7, #4] 8004b6c: 681b ldr r3, [r3, #0] 8004b6e: 68da ldr r2, [r3, #12] 8004b70: 687b ldr r3, [r7, #4] 8004b72: 681b ldr r3, [r3, #0] 8004b74: f422 7290 bic.w r2, r2, #288 ; 0x120 8004b78: 60da str r2, [r3, #12] CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8004b7a: 687b ldr r3, [r7, #4] 8004b7c: 681b ldr r3, [r3, #0] 8004b7e: 695a ldr r2, [r3, #20] 8004b80: 687b ldr r3, [r7, #4] 8004b82: 681b ldr r3, [r3, #0] 8004b84: f022 0201 bic.w r2, r2, #1 8004b88: 615a str r2, [r3, #20] /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8004b8a: 687b ldr r3, [r7, #4] 8004b8c: 2220 movs r2, #32 8004b8e: f883 203a strb.w r2, [r3, #58] ; 0x3a } 8004b92: bf00 nop 8004b94: 370c adds r7, #12 8004b96: 46bd mov sp, r7 8004b98: bc80 pop {r7} 8004b9a: 4770 bx lr 08004b9c : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { 8004b9c: b580 push {r7, lr} 8004b9e: b084 sub sp, #16 8004ba0: af00 add r7, sp, #0 8004ba2: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8004ba4: 687b ldr r3, [r7, #4] 8004ba6: 6a5b ldr r3, [r3, #36] ; 0x24 8004ba8: 60fb str r3, [r7, #12] huart->RxXferCount = 0x00U; 8004baa: 68fb ldr r3, [r7, #12] 8004bac: 2200 movs r2, #0 8004bae: 85da strh r2, [r3, #46] ; 0x2e huart->TxXferCount = 0x00U; 8004bb0: 68fb ldr r3, [r7, #12] 8004bb2: 2200 movs r2, #0 8004bb4: 84da strh r2, [r3, #38] ; 0x26 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8004bb6: 68f8 ldr r0, [r7, #12] 8004bb8: f7ff feea bl 8004990 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8004bbc: bf00 nop 8004bbe: 3710 adds r7, #16 8004bc0: 46bd mov sp, r7 8004bc2: bd80 pop {r7, pc} 08004bc4 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) { 8004bc4: b480 push {r7} 8004bc6: b085 sub sp, #20 8004bc8: af00 add r7, sp, #0 8004bca: 6078 str r0, [r7, #4] uint16_t *tmp; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 8004bcc: 687b ldr r3, [r7, #4] 8004bce: f893 3039 ldrb.w r3, [r3, #57] ; 0x39 8004bd2: b2db uxtb r3, r3 8004bd4: 2b21 cmp r3, #33 ; 0x21 8004bd6: d144 bne.n 8004c62 { if (huart->Init.WordLength == UART_WORDLENGTH_9B) 8004bd8: 687b ldr r3, [r7, #4] 8004bda: 689b ldr r3, [r3, #8] 8004bdc: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8004be0: d11a bne.n 8004c18 { tmp = (uint16_t *) huart->pTxBuffPtr; 8004be2: 687b ldr r3, [r7, #4] 8004be4: 6a1b ldr r3, [r3, #32] 8004be6: 60fb str r3, [r7, #12] huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); 8004be8: 68fb ldr r3, [r7, #12] 8004bea: 881b ldrh r3, [r3, #0] 8004bec: 461a mov r2, r3 8004bee: 687b ldr r3, [r7, #4] 8004bf0: 681b ldr r3, [r3, #0] 8004bf2: f3c2 0208 ubfx r2, r2, #0, #9 8004bf6: 605a str r2, [r3, #4] if (huart->Init.Parity == UART_PARITY_NONE) 8004bf8: 687b ldr r3, [r7, #4] 8004bfa: 691b ldr r3, [r3, #16] 8004bfc: 2b00 cmp r3, #0 8004bfe: d105 bne.n 8004c0c { huart->pTxBuffPtr += 2U; 8004c00: 687b ldr r3, [r7, #4] 8004c02: 6a1b ldr r3, [r3, #32] 8004c04: 1c9a adds r2, r3, #2 8004c06: 687b ldr r3, [r7, #4] 8004c08: 621a str r2, [r3, #32] 8004c0a: e00e b.n 8004c2a } else { huart->pTxBuffPtr += 1U; 8004c0c: 687b ldr r3, [r7, #4] 8004c0e: 6a1b ldr r3, [r3, #32] 8004c10: 1c5a adds r2, r3, #1 8004c12: 687b ldr r3, [r7, #4] 8004c14: 621a str r2, [r3, #32] 8004c16: e008 b.n 8004c2a } } else { huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF); 8004c18: 687b ldr r3, [r7, #4] 8004c1a: 6a1b ldr r3, [r3, #32] 8004c1c: 1c59 adds r1, r3, #1 8004c1e: 687a ldr r2, [r7, #4] 8004c20: 6211 str r1, [r2, #32] 8004c22: 781a ldrb r2, [r3, #0] 8004c24: 687b ldr r3, [r7, #4] 8004c26: 681b ldr r3, [r3, #0] 8004c28: 605a str r2, [r3, #4] } if (--huart->TxXferCount == 0U) 8004c2a: 687b ldr r3, [r7, #4] 8004c2c: 8cdb ldrh r3, [r3, #38] ; 0x26 8004c2e: b29b uxth r3, r3 8004c30: 3b01 subs r3, #1 8004c32: b29b uxth r3, r3 8004c34: 687a ldr r2, [r7, #4] 8004c36: 4619 mov r1, r3 8004c38: 84d1 strh r1, [r2, #38] ; 0x26 8004c3a: 2b00 cmp r3, #0 8004c3c: d10f bne.n 8004c5e { /* Disable the UART Transmit Complete Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); 8004c3e: 687b ldr r3, [r7, #4] 8004c40: 681b ldr r3, [r3, #0] 8004c42: 68da ldr r2, [r3, #12] 8004c44: 687b ldr r3, [r7, #4] 8004c46: 681b ldr r3, [r3, #0] 8004c48: f022 0280 bic.w r2, r2, #128 ; 0x80 8004c4c: 60da str r2, [r3, #12] /* Enable the UART Transmit Complete Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_TC); 8004c4e: 687b ldr r3, [r7, #4] 8004c50: 681b ldr r3, [r3, #0] 8004c52: 68da ldr r2, [r3, #12] 8004c54: 687b ldr r3, [r7, #4] 8004c56: 681b ldr r3, [r3, #0] 8004c58: f042 0240 orr.w r2, r2, #64 ; 0x40 8004c5c: 60da str r2, [r3, #12] } return HAL_OK; 8004c5e: 2300 movs r3, #0 8004c60: e000 b.n 8004c64 } else { return HAL_BUSY; 8004c62: 2302 movs r3, #2 } } 8004c64: 4618 mov r0, r3 8004c66: 3714 adds r7, #20 8004c68: 46bd mov sp, r7 8004c6a: bc80 pop {r7} 8004c6c: 4770 bx lr 08004c6e : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) { 8004c6e: b580 push {r7, lr} 8004c70: b082 sub sp, #8 8004c72: af00 add r7, sp, #0 8004c74: 6078 str r0, [r7, #4] /* Disable the UART Transmit Complete Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TC); 8004c76: 687b ldr r3, [r7, #4] 8004c78: 681b ldr r3, [r3, #0] 8004c7a: 68da ldr r2, [r3, #12] 8004c7c: 687b ldr r3, [r7, #4] 8004c7e: 681b ldr r3, [r3, #0] 8004c80: f022 0240 bic.w r2, r2, #64 ; 0x40 8004c84: 60da str r2, [r3, #12] /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8004c86: 687b ldr r3, [r7, #4] 8004c88: 2220 movs r2, #32 8004c8a: f883 2039 strb.w r2, [r3, #57] ; 0x39 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); 8004c8e: 6878 ldr r0, [r7, #4] 8004c90: f7ff fe6c bl 800496c #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return HAL_OK; 8004c94: 2300 movs r3, #0 } 8004c96: 4618 mov r0, r3 8004c98: 3708 adds r7, #8 8004c9a: 46bd mov sp, r7 8004c9c: bd80 pop {r7, pc} 08004c9e : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) { 8004c9e: b580 push {r7, lr} 8004ca0: b084 sub sp, #16 8004ca2: af00 add r7, sp, #0 8004ca4: 6078 str r0, [r7, #4] uint16_t *tmp; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 8004ca6: 687b ldr r3, [r7, #4] 8004ca8: f893 303a ldrb.w r3, [r3, #58] ; 0x3a 8004cac: b2db uxtb r3, r3 8004cae: 2b22 cmp r3, #34 ; 0x22 8004cb0: d171 bne.n 8004d96 { if (huart->Init.WordLength == UART_WORDLENGTH_9B) 8004cb2: 687b ldr r3, [r7, #4] 8004cb4: 689b ldr r3, [r3, #8] 8004cb6: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8004cba: d123 bne.n 8004d04 { tmp = (uint16_t *) huart->pRxBuffPtr; 8004cbc: 687b ldr r3, [r7, #4] 8004cbe: 6a9b ldr r3, [r3, #40] ; 0x28 8004cc0: 60fb str r3, [r7, #12] if (huart->Init.Parity == UART_PARITY_NONE) 8004cc2: 687b ldr r3, [r7, #4] 8004cc4: 691b ldr r3, [r3, #16] 8004cc6: 2b00 cmp r3, #0 8004cc8: d10e bne.n 8004ce8 { *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); 8004cca: 687b ldr r3, [r7, #4] 8004ccc: 681b ldr r3, [r3, #0] 8004cce: 685b ldr r3, [r3, #4] 8004cd0: b29b uxth r3, r3 8004cd2: f3c3 0308 ubfx r3, r3, #0, #9 8004cd6: b29a uxth r2, r3 8004cd8: 68fb ldr r3, [r7, #12] 8004cda: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 8004cdc: 687b ldr r3, [r7, #4] 8004cde: 6a9b ldr r3, [r3, #40] ; 0x28 8004ce0: 1c9a adds r2, r3, #2 8004ce2: 687b ldr r3, [r7, #4] 8004ce4: 629a str r2, [r3, #40] ; 0x28 8004ce6: e029 b.n 8004d3c } else { *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF); 8004ce8: 687b ldr r3, [r7, #4] 8004cea: 681b ldr r3, [r3, #0] 8004cec: 685b ldr r3, [r3, #4] 8004cee: b29b uxth r3, r3 8004cf0: b2db uxtb r3, r3 8004cf2: b29a uxth r2, r3 8004cf4: 68fb ldr r3, [r7, #12] 8004cf6: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 1U; 8004cf8: 687b ldr r3, [r7, #4] 8004cfa: 6a9b ldr r3, [r3, #40] ; 0x28 8004cfc: 1c5a adds r2, r3, #1 8004cfe: 687b ldr r3, [r7, #4] 8004d00: 629a str r2, [r3, #40] ; 0x28 8004d02: e01b b.n 8004d3c } } else { if (huart->Init.Parity == UART_PARITY_NONE) 8004d04: 687b ldr r3, [r7, #4] 8004d06: 691b ldr r3, [r3, #16] 8004d08: 2b00 cmp r3, #0 8004d0a: d10a bne.n 8004d22 { *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); 8004d0c: 687b ldr r3, [r7, #4] 8004d0e: 681b ldr r3, [r3, #0] 8004d10: 6858 ldr r0, [r3, #4] 8004d12: 687b ldr r3, [r7, #4] 8004d14: 6a9b ldr r3, [r3, #40] ; 0x28 8004d16: 1c59 adds r1, r3, #1 8004d18: 687a ldr r2, [r7, #4] 8004d1a: 6291 str r1, [r2, #40] ; 0x28 8004d1c: b2c2 uxtb r2, r0 8004d1e: 701a strb r2, [r3, #0] 8004d20: e00c b.n 8004d3c } else { *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); 8004d22: 687b ldr r3, [r7, #4] 8004d24: 681b ldr r3, [r3, #0] 8004d26: 685b ldr r3, [r3, #4] 8004d28: b2da uxtb r2, r3 8004d2a: 687b ldr r3, [r7, #4] 8004d2c: 6a9b ldr r3, [r3, #40] ; 0x28 8004d2e: 1c58 adds r0, r3, #1 8004d30: 6879 ldr r1, [r7, #4] 8004d32: 6288 str r0, [r1, #40] ; 0x28 8004d34: f002 027f and.w r2, r2, #127 ; 0x7f 8004d38: b2d2 uxtb r2, r2 8004d3a: 701a strb r2, [r3, #0] } } if (--huart->RxXferCount == 0U) 8004d3c: 687b ldr r3, [r7, #4] 8004d3e: 8ddb ldrh r3, [r3, #46] ; 0x2e 8004d40: b29b uxth r3, r3 8004d42: 3b01 subs r3, #1 8004d44: b29b uxth r3, r3 8004d46: 687a ldr r2, [r7, #4] 8004d48: 4619 mov r1, r3 8004d4a: 85d1 strh r1, [r2, #46] ; 0x2e 8004d4c: 2b00 cmp r3, #0 8004d4e: d120 bne.n 8004d92 { /* Disable the UART Data Register not empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); 8004d50: 687b ldr r3, [r7, #4] 8004d52: 681b ldr r3, [r3, #0] 8004d54: 68da ldr r2, [r3, #12] 8004d56: 687b ldr r3, [r7, #4] 8004d58: 681b ldr r3, [r3, #0] 8004d5a: f022 0220 bic.w r2, r2, #32 8004d5e: 60da str r2, [r3, #12] /* Disable the UART Parity Error Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_PE); 8004d60: 687b ldr r3, [r7, #4] 8004d62: 681b ldr r3, [r3, #0] 8004d64: 68da ldr r2, [r3, #12] 8004d66: 687b ldr r3, [r7, #4] 8004d68: 681b ldr r3, [r3, #0] 8004d6a: f422 7280 bic.w r2, r2, #256 ; 0x100 8004d6e: 60da str r2, [r3, #12] /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); 8004d70: 687b ldr r3, [r7, #4] 8004d72: 681b ldr r3, [r3, #0] 8004d74: 695a ldr r2, [r3, #20] 8004d76: 687b ldr r3, [r7, #4] 8004d78: 681b ldr r3, [r3, #0] 8004d7a: f022 0201 bic.w r2, r2, #1 8004d7e: 615a str r2, [r3, #20] /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8004d80: 687b ldr r3, [r7, #4] 8004d82: 2220 movs r2, #32 8004d84: f883 203a strb.w r2, [r3, #58] ; 0x3a #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 8004d88: 6878 ldr r0, [r7, #4] 8004d8a: f7fc feab bl 8001ae4 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return HAL_OK; 8004d8e: 2300 movs r3, #0 8004d90: e002 b.n 8004d98 } return HAL_OK; 8004d92: 2300 movs r3, #0 8004d94: e000 b.n 8004d98 } else { return HAL_BUSY; 8004d96: 2302 movs r3, #2 } } 8004d98: 4618 mov r0, r3 8004d9a: 3710 adds r7, #16 8004d9c: 46bd mov sp, r7 8004d9e: bd80 pop {r7, pc} 08004da0 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_SetConfig(UART_HandleTypeDef *huart) { 8004da0: b580 push {r7, lr} 8004da2: b084 sub sp, #16 8004da4: af00 add r7, sp, #0 8004da6: 6078 str r0, [r7, #4] assert_param(IS_UART_MODE(huart->Init.Mode)); /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 8004da8: 687b ldr r3, [r7, #4] 8004daa: 681b ldr r3, [r3, #0] 8004dac: 691b ldr r3, [r3, #16] 8004dae: f423 5140 bic.w r1, r3, #12288 ; 0x3000 8004db2: 687b ldr r3, [r7, #4] 8004db4: 68da ldr r2, [r3, #12] 8004db6: 687b ldr r3, [r7, #4] 8004db8: 681b ldr r3, [r3, #0] 8004dba: 430a orrs r2, r1 8004dbc: 611a str r2, [r3, #16] Set PCE and PS bits according to huart->Init.Parity value Set TE and RE bits according to huart->Init.Mode value Set OVER8 bit according to huart->Init.OverSampling value */ #if defined(USART_CR1_OVER8) tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; 8004dbe: 687b ldr r3, [r7, #4] 8004dc0: 689a ldr r2, [r3, #8] 8004dc2: 687b ldr r3, [r7, #4] 8004dc4: 691b ldr r3, [r3, #16] 8004dc6: 431a orrs r2, r3 8004dc8: 687b ldr r3, [r7, #4] 8004dca: 695b ldr r3, [r3, #20] 8004dcc: 431a orrs r2, r3 8004dce: 687b ldr r3, [r7, #4] 8004dd0: 69db ldr r3, [r3, #28] 8004dd2: 4313 orrs r3, r2 8004dd4: 60fb str r3, [r7, #12] MODIFY_REG(huart->Instance->CR1, 8004dd6: 687b ldr r3, [r7, #4] 8004dd8: 681b ldr r3, [r3, #0] 8004dda: 68db ldr r3, [r3, #12] 8004ddc: f423 4316 bic.w r3, r3, #38400 ; 0x9600 8004de0: f023 030c bic.w r3, r3, #12 8004de4: 687a ldr r2, [r7, #4] 8004de6: 6812 ldr r2, [r2, #0] 8004de8: 68f9 ldr r1, [r7, #12] 8004dea: 430b orrs r3, r1 8004dec: 60d3 str r3, [r2, #12] tmpreg); #endif /* USART_CR1_OVER8 */ /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); 8004dee: 687b ldr r3, [r7, #4] 8004df0: 681b ldr r3, [r3, #0] 8004df2: 695b ldr r3, [r3, #20] 8004df4: f423 7140 bic.w r1, r3, #768 ; 0x300 8004df8: 687b ldr r3, [r7, #4] 8004dfa: 699a ldr r2, [r3, #24] 8004dfc: 687b ldr r3, [r7, #4] 8004dfe: 681b ldr r3, [r3, #0] 8004e00: 430a orrs r2, r1 8004e02: 615a str r2, [r3, #20] #if defined(USART_CR1_OVER8) /* Check the Over Sampling */ if(huart->Init.OverSampling == UART_OVERSAMPLING_8) 8004e04: 687b ldr r3, [r7, #4] 8004e06: 69db ldr r3, [r3, #28] 8004e08: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 8004e0c: f040 80a5 bne.w 8004f5a { /*-------------------------- USART BRR Configuration ---------------------*/ if(huart->Instance == USART1) 8004e10: 687b ldr r3, [r7, #4] 8004e12: 681b ldr r3, [r3, #0] 8004e14: 4aa4 ldr r2, [pc, #656] ; (80050a8 ) 8004e16: 4293 cmp r3, r2 8004e18: d14f bne.n 8004eba { pclk = HAL_RCC_GetPCLK2Freq(); 8004e1a: f7fe ff59 bl 8003cd0 8004e1e: 60b8 str r0, [r7, #8] huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate); 8004e20: 68ba ldr r2, [r7, #8] 8004e22: 4613 mov r3, r2 8004e24: 009b lsls r3, r3, #2 8004e26: 4413 add r3, r2 8004e28: 009a lsls r2, r3, #2 8004e2a: 441a add r2, r3 8004e2c: 687b ldr r3, [r7, #4] 8004e2e: 685b ldr r3, [r3, #4] 8004e30: 005b lsls r3, r3, #1 8004e32: fbb2 f3f3 udiv r3, r2, r3 8004e36: 4a9d ldr r2, [pc, #628] ; (80050ac ) 8004e38: fba2 2303 umull r2, r3, r2, r3 8004e3c: 095b lsrs r3, r3, #5 8004e3e: 0119 lsls r1, r3, #4 8004e40: 68ba ldr r2, [r7, #8] 8004e42: 4613 mov r3, r2 8004e44: 009b lsls r3, r3, #2 8004e46: 4413 add r3, r2 8004e48: 009a lsls r2, r3, #2 8004e4a: 441a add r2, r3 8004e4c: 687b ldr r3, [r7, #4] 8004e4e: 685b ldr r3, [r3, #4] 8004e50: 005b lsls r3, r3, #1 8004e52: fbb2 f2f3 udiv r2, r2, r3 8004e56: 4b95 ldr r3, [pc, #596] ; (80050ac ) 8004e58: fba3 0302 umull r0, r3, r3, r2 8004e5c: 095b lsrs r3, r3, #5 8004e5e: 2064 movs r0, #100 ; 0x64 8004e60: fb00 f303 mul.w r3, r0, r3 8004e64: 1ad3 subs r3, r2, r3 8004e66: 00db lsls r3, r3, #3 8004e68: 3332 adds r3, #50 ; 0x32 8004e6a: 4a90 ldr r2, [pc, #576] ; (80050ac ) 8004e6c: fba2 2303 umull r2, r3, r2, r3 8004e70: 095b lsrs r3, r3, #5 8004e72: 005b lsls r3, r3, #1 8004e74: f403 73f8 and.w r3, r3, #496 ; 0x1f0 8004e78: 4419 add r1, r3 8004e7a: 68ba ldr r2, [r7, #8] 8004e7c: 4613 mov r3, r2 8004e7e: 009b lsls r3, r3, #2 8004e80: 4413 add r3, r2 8004e82: 009a lsls r2, r3, #2 8004e84: 441a add r2, r3 8004e86: 687b ldr r3, [r7, #4] 8004e88: 685b ldr r3, [r3, #4] 8004e8a: 005b lsls r3, r3, #1 8004e8c: fbb2 f2f3 udiv r2, r2, r3 8004e90: 4b86 ldr r3, [pc, #536] ; (80050ac ) 8004e92: fba3 0302 umull r0, r3, r3, r2 8004e96: 095b lsrs r3, r3, #5 8004e98: 2064 movs r0, #100 ; 0x64 8004e9a: fb00 f303 mul.w r3, r0, r3 8004e9e: 1ad3 subs r3, r2, r3 8004ea0: 00db lsls r3, r3, #3 8004ea2: 3332 adds r3, #50 ; 0x32 8004ea4: 4a81 ldr r2, [pc, #516] ; (80050ac ) 8004ea6: fba2 2303 umull r2, r3, r2, r3 8004eaa: 095b lsrs r3, r3, #5 8004eac: f003 0207 and.w r2, r3, #7 8004eb0: 687b ldr r3, [r7, #4] 8004eb2: 681b ldr r3, [r3, #0] 8004eb4: 440a add r2, r1 8004eb6: 609a str r2, [r3, #8] { pclk = HAL_RCC_GetPCLK1Freq(); huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); } #endif /* USART_CR1_OVER8 */ } 8004eb8: e0f1 b.n 800509e pclk = HAL_RCC_GetPCLK1Freq(); 8004eba: f7fe fef5 bl 8003ca8 8004ebe: 60b8 str r0, [r7, #8] huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate); 8004ec0: 68ba ldr r2, [r7, #8] 8004ec2: 4613 mov r3, r2 8004ec4: 009b lsls r3, r3, #2 8004ec6: 4413 add r3, r2 8004ec8: 009a lsls r2, r3, #2 8004eca: 441a add r2, r3 8004ecc: 687b ldr r3, [r7, #4] 8004ece: 685b ldr r3, [r3, #4] 8004ed0: 005b lsls r3, r3, #1 8004ed2: fbb2 f3f3 udiv r3, r2, r3 8004ed6: 4a75 ldr r2, [pc, #468] ; (80050ac ) 8004ed8: fba2 2303 umull r2, r3, r2, r3 8004edc: 095b lsrs r3, r3, #5 8004ede: 0119 lsls r1, r3, #4 8004ee0: 68ba ldr r2, [r7, #8] 8004ee2: 4613 mov r3, r2 8004ee4: 009b lsls r3, r3, #2 8004ee6: 4413 add r3, r2 8004ee8: 009a lsls r2, r3, #2 8004eea: 441a add r2, r3 8004eec: 687b ldr r3, [r7, #4] 8004eee: 685b ldr r3, [r3, #4] 8004ef0: 005b lsls r3, r3, #1 8004ef2: fbb2 f2f3 udiv r2, r2, r3 8004ef6: 4b6d ldr r3, [pc, #436] ; (80050ac ) 8004ef8: fba3 0302 umull r0, r3, r3, r2 8004efc: 095b lsrs r3, r3, #5 8004efe: 2064 movs r0, #100 ; 0x64 8004f00: fb00 f303 mul.w r3, r0, r3 8004f04: 1ad3 subs r3, r2, r3 8004f06: 00db lsls r3, r3, #3 8004f08: 3332 adds r3, #50 ; 0x32 8004f0a: 4a68 ldr r2, [pc, #416] ; (80050ac ) 8004f0c: fba2 2303 umull r2, r3, r2, r3 8004f10: 095b lsrs r3, r3, #5 8004f12: 005b lsls r3, r3, #1 8004f14: f403 73f8 and.w r3, r3, #496 ; 0x1f0 8004f18: 4419 add r1, r3 8004f1a: 68ba ldr r2, [r7, #8] 8004f1c: 4613 mov r3, r2 8004f1e: 009b lsls r3, r3, #2 8004f20: 4413 add r3, r2 8004f22: 009a lsls r2, r3, #2 8004f24: 441a add r2, r3 8004f26: 687b ldr r3, [r7, #4] 8004f28: 685b ldr r3, [r3, #4] 8004f2a: 005b lsls r3, r3, #1 8004f2c: fbb2 f2f3 udiv r2, r2, r3 8004f30: 4b5e ldr r3, [pc, #376] ; (80050ac ) 8004f32: fba3 0302 umull r0, r3, r3, r2 8004f36: 095b lsrs r3, r3, #5 8004f38: 2064 movs r0, #100 ; 0x64 8004f3a: fb00 f303 mul.w r3, r0, r3 8004f3e: 1ad3 subs r3, r2, r3 8004f40: 00db lsls r3, r3, #3 8004f42: 3332 adds r3, #50 ; 0x32 8004f44: 4a59 ldr r2, [pc, #356] ; (80050ac ) 8004f46: fba2 2303 umull r2, r3, r2, r3 8004f4a: 095b lsrs r3, r3, #5 8004f4c: f003 0207 and.w r2, r3, #7 8004f50: 687b ldr r3, [r7, #4] 8004f52: 681b ldr r3, [r3, #0] 8004f54: 440a add r2, r1 8004f56: 609a str r2, [r3, #8] } 8004f58: e0a1 b.n 800509e if(huart->Instance == USART1) 8004f5a: 687b ldr r3, [r7, #4] 8004f5c: 681b ldr r3, [r3, #0] 8004f5e: 4a52 ldr r2, [pc, #328] ; (80050a8 ) 8004f60: 4293 cmp r3, r2 8004f62: d14e bne.n 8005002 pclk = HAL_RCC_GetPCLK2Freq(); 8004f64: f7fe feb4 bl 8003cd0 8004f68: 60b8 str r0, [r7, #8] huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); 8004f6a: 68ba ldr r2, [r7, #8] 8004f6c: 4613 mov r3, r2 8004f6e: 009b lsls r3, r3, #2 8004f70: 4413 add r3, r2 8004f72: 009a lsls r2, r3, #2 8004f74: 441a add r2, r3 8004f76: 687b ldr r3, [r7, #4] 8004f78: 685b ldr r3, [r3, #4] 8004f7a: 009b lsls r3, r3, #2 8004f7c: fbb2 f3f3 udiv r3, r2, r3 8004f80: 4a4a ldr r2, [pc, #296] ; (80050ac ) 8004f82: fba2 2303 umull r2, r3, r2, r3 8004f86: 095b lsrs r3, r3, #5 8004f88: 0119 lsls r1, r3, #4 8004f8a: 68ba ldr r2, [r7, #8] 8004f8c: 4613 mov r3, r2 8004f8e: 009b lsls r3, r3, #2 8004f90: 4413 add r3, r2 8004f92: 009a lsls r2, r3, #2 8004f94: 441a add r2, r3 8004f96: 687b ldr r3, [r7, #4] 8004f98: 685b ldr r3, [r3, #4] 8004f9a: 009b lsls r3, r3, #2 8004f9c: fbb2 f2f3 udiv r2, r2, r3 8004fa0: 4b42 ldr r3, [pc, #264] ; (80050ac ) 8004fa2: fba3 0302 umull r0, r3, r3, r2 8004fa6: 095b lsrs r3, r3, #5 8004fa8: 2064 movs r0, #100 ; 0x64 8004faa: fb00 f303 mul.w r3, r0, r3 8004fae: 1ad3 subs r3, r2, r3 8004fb0: 011b lsls r3, r3, #4 8004fb2: 3332 adds r3, #50 ; 0x32 8004fb4: 4a3d ldr r2, [pc, #244] ; (80050ac ) 8004fb6: fba2 2303 umull r2, r3, r2, r3 8004fba: 095b lsrs r3, r3, #5 8004fbc: f003 03f0 and.w r3, r3, #240 ; 0xf0 8004fc0: 4419 add r1, r3 8004fc2: 68ba ldr r2, [r7, #8] 8004fc4: 4613 mov r3, r2 8004fc6: 009b lsls r3, r3, #2 8004fc8: 4413 add r3, r2 8004fca: 009a lsls r2, r3, #2 8004fcc: 441a add r2, r3 8004fce: 687b ldr r3, [r7, #4] 8004fd0: 685b ldr r3, [r3, #4] 8004fd2: 009b lsls r3, r3, #2 8004fd4: fbb2 f2f3 udiv r2, r2, r3 8004fd8: 4b34 ldr r3, [pc, #208] ; (80050ac ) 8004fda: fba3 0302 umull r0, r3, r3, r2 8004fde: 095b lsrs r3, r3, #5 8004fe0: 2064 movs r0, #100 ; 0x64 8004fe2: fb00 f303 mul.w r3, r0, r3 8004fe6: 1ad3 subs r3, r2, r3 8004fe8: 011b lsls r3, r3, #4 8004fea: 3332 adds r3, #50 ; 0x32 8004fec: 4a2f ldr r2, [pc, #188] ; (80050ac ) 8004fee: fba2 2303 umull r2, r3, r2, r3 8004ff2: 095b lsrs r3, r3, #5 8004ff4: f003 020f and.w r2, r3, #15 8004ff8: 687b ldr r3, [r7, #4] 8004ffa: 681b ldr r3, [r3, #0] 8004ffc: 440a add r2, r1 8004ffe: 609a str r2, [r3, #8] } 8005000: e04d b.n 800509e pclk = HAL_RCC_GetPCLK1Freq(); 8005002: f7fe fe51 bl 8003ca8 8005006: 60b8 str r0, [r7, #8] huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); 8005008: 68ba ldr r2, [r7, #8] 800500a: 4613 mov r3, r2 800500c: 009b lsls r3, r3, #2 800500e: 4413 add r3, r2 8005010: 009a lsls r2, r3, #2 8005012: 441a add r2, r3 8005014: 687b ldr r3, [r7, #4] 8005016: 685b ldr r3, [r3, #4] 8005018: 009b lsls r3, r3, #2 800501a: fbb2 f3f3 udiv r3, r2, r3 800501e: 4a23 ldr r2, [pc, #140] ; (80050ac ) 8005020: fba2 2303 umull r2, r3, r2, r3 8005024: 095b lsrs r3, r3, #5 8005026: 0119 lsls r1, r3, #4 8005028: 68ba ldr r2, [r7, #8] 800502a: 4613 mov r3, r2 800502c: 009b lsls r3, r3, #2 800502e: 4413 add r3, r2 8005030: 009a lsls r2, r3, #2 8005032: 441a add r2, r3 8005034: 687b ldr r3, [r7, #4] 8005036: 685b ldr r3, [r3, #4] 8005038: 009b lsls r3, r3, #2 800503a: fbb2 f2f3 udiv r2, r2, r3 800503e: 4b1b ldr r3, [pc, #108] ; (80050ac ) 8005040: fba3 0302 umull r0, r3, r3, r2 8005044: 095b lsrs r3, r3, #5 8005046: 2064 movs r0, #100 ; 0x64 8005048: fb00 f303 mul.w r3, r0, r3 800504c: 1ad3 subs r3, r2, r3 800504e: 011b lsls r3, r3, #4 8005050: 3332 adds r3, #50 ; 0x32 8005052: 4a16 ldr r2, [pc, #88] ; (80050ac ) 8005054: fba2 2303 umull r2, r3, r2, r3 8005058: 095b lsrs r3, r3, #5 800505a: f003 03f0 and.w r3, r3, #240 ; 0xf0 800505e: 4419 add r1, r3 8005060: 68ba ldr r2, [r7, #8] 8005062: 4613 mov r3, r2 8005064: 009b lsls r3, r3, #2 8005066: 4413 add r3, r2 8005068: 009a lsls r2, r3, #2 800506a: 441a add r2, r3 800506c: 687b ldr r3, [r7, #4] 800506e: 685b ldr r3, [r3, #4] 8005070: 009b lsls r3, r3, #2 8005072: fbb2 f2f3 udiv r2, r2, r3 8005076: 4b0d ldr r3, [pc, #52] ; (80050ac ) 8005078: fba3 0302 umull r0, r3, r3, r2 800507c: 095b lsrs r3, r3, #5 800507e: 2064 movs r0, #100 ; 0x64 8005080: fb00 f303 mul.w r3, r0, r3 8005084: 1ad3 subs r3, r2, r3 8005086: 011b lsls r3, r3, #4 8005088: 3332 adds r3, #50 ; 0x32 800508a: 4a08 ldr r2, [pc, #32] ; (80050ac ) 800508c: fba2 2303 umull r2, r3, r2, r3 8005090: 095b lsrs r3, r3, #5 8005092: f003 020f and.w r2, r3, #15 8005096: 687b ldr r3, [r7, #4] 8005098: 681b ldr r3, [r3, #0] 800509a: 440a add r2, r1 800509c: 609a str r2, [r3, #8] } 800509e: bf00 nop 80050a0: 3710 adds r7, #16 80050a2: 46bd mov sp, r7 80050a4: bd80 pop {r7, pc} 80050a6: bf00 nop 80050a8: 40013800 .word 0x40013800 80050ac: 51eb851f .word 0x51eb851f 080050b0 <_write>: /* USER CODE END PFP */ /* Private user code ---------------------------------------------------------*/ /* USER CODE BEGIN 0 */ int _write (int file, uint8_t *ptr, uint16_t len) { 80050b0: b580 push {r7, lr} 80050b2: b084 sub sp, #16 80050b4: af00 add r7, sp, #0 80050b6: 60f8 str r0, [r7, #12] 80050b8: 60b9 str r1, [r7, #8] 80050ba: 4613 mov r3, r2 80050bc: 80fb strh r3, [r7, #6] #if 0 // PYJ.2020.06.03_BEGIN -- HAL_UART_Transmit(&hTest, ptr, len,10); #else HAL_UART_Transmit(&hTerminal, ptr, len,10); 80050be: 88fa ldrh r2, [r7, #6] 80050c0: 230a movs r3, #10 80050c2: 68b9 ldr r1, [r7, #8] 80050c4: 4803 ldr r0, [pc, #12] ; (80050d4 <_write+0x24>) 80050c6: f7ff f9fc bl 80044c2 #endif // PYJ.2020.06.03_END -- return len; 80050ca: 88fb ldrh r3, [r7, #6] } 80050cc: 4618 mov r0, r3 80050ce: 3710 adds r7, #16 80050d0: 46bd mov sp, r7 80050d2: bd80 pop {r7, pc} 80050d4: 200007e0 .word 0x200007e0 080050d8
: /** * @brief The application entry point. * @retval int */ int main(void) { 80050d8: b580 push {r7, lr} 80050da: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 80050dc: f7fc fe2c bl 8001d38 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 80050e0: f000 f84c bl 800517c /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 80050e4: f000 f9d6 bl 8005494 MX_DMA_Init(); 80050e8: f000 f9be bl 8005468 MX_ADC1_Init(); 80050ec: f000 f8d6 bl 800529c MX_TIM6_Init(); 80050f0: f000 f930 bl 8005354 MX_USART1_UART_Init(); 80050f4: f000 f964 bl 80053c0 MX_USART3_UART_Init(); 80050f8: f000 f98c bl 8005414 /* Initialize interrupts */ MX_NVIC_Init(); 80050fc: f000 f892 bl 8005224 /* USER CODE BEGIN 2 */ HAL_TIM_Base_Start_IT(&htim6); 8005100: 4815 ldr r0, [pc, #84] ; (8005158 ) 8005102: f7fe ff6c bl 8003fde setbuf(stdout, NULL); 8005106: 4b15 ldr r3, [pc, #84] ; (800515c ) 8005108: 681b ldr r3, [r3, #0] 800510a: 689b ldr r3, [r3, #8] 800510c: 2100 movs r1, #0 800510e: 4618 mov r0, r3 8005110: f001 fb2e bl 8006770 InitUartQueue(&MainQueue); 8005114: 4812 ldr r0, [pc, #72] ; (8005160 ) 8005116: f7fc fcbd bl 8001a94 ADC_Initialize(); 800511a: f7fc f9ab bl 8001474 NessLab_Init(); 800511e: f7fb fd83 bl 8000c28 #if 1 // PYJ.2020.05.06_BEGIN -- printf("****************************************\r\n"); 8005122: 4810 ldr r0, [pc, #64] ; (8005164 ) 8005124: f001 fb1c bl 8006760 printf("NESSLAB Project\r\n"); 8005128: 480f ldr r0, [pc, #60] ; (8005168 ) 800512a: f001 fb19 bl 8006760 printf("Build at %s %s\r\n", __DATE__, __TIME__); 800512e: 4a0f ldr r2, [pc, #60] ; (800516c ) 8005130: 490f ldr r1, [pc, #60] ; (8005170 ) 8005132: 4810 ldr r0, [pc, #64] ; (8005174 ) 8005134: f001 faa0 bl 8006678 printf("Copyright (c) 2020. BLUECELL\r\n"); 8005138: 480f ldr r0, [pc, #60] ; (8005178 ) 800513a: f001 fb11 bl 8006760 printf("****************************************\r\n"); 800513e: 4809 ldr r0, [pc, #36] ; (8005164 ) 8005140: f001 fb0e bl 8006760 while (1) { #if 1 // PYJ.2020.08.31_BEGIN -- Boot_LED_Toggle(); /*LED Check*/ 8005144: f7fc fc8e bl 8001a64 Uart_Check(); /*Usart Rx*/ 8005148: f7fc fdb0 bl 8001cac NessLab_GPIO_Operate(); 800514c: f7fc f91c bl 8001388 ADC_TDD_Arrange(); 8005150: f7fc fa62 bl 8001618 { 8005154: e7f6 b.n 8005144 8005156: bf00 nop 8005158: 2000095c .word 0x2000095c 800515c: 2000000c .word 0x2000000c 8005160: 2000061c .word 0x2000061c 8005164: 08008904 .word 0x08008904 8005168: 08008930 .word 0x08008930 800516c: 08008944 .word 0x08008944 8005170: 08008950 .word 0x08008950 8005174: 0800895c .word 0x0800895c 8005178: 08008970 .word 0x08008970 0800517c : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 800517c: b580 push {r7, lr} 800517e: b092 sub sp, #72 ; 0x48 8005180: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8005182: f107 0320 add.w r3, r7, #32 8005186: 2228 movs r2, #40 ; 0x28 8005188: 2100 movs r1, #0 800518a: 4618 mov r0, r3 800518c: f000 fe1c bl 8005dc8 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8005190: f107 030c add.w r3, r7, #12 8005194: 2200 movs r2, #0 8005196: 601a str r2, [r3, #0] 8005198: 605a str r2, [r3, #4] 800519a: 609a str r2, [r3, #8] 800519c: 60da str r2, [r3, #12] 800519e: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 80051a0: 463b mov r3, r7 80051a2: 2200 movs r2, #0 80051a4: 601a str r2, [r3, #0] 80051a6: 605a str r2, [r3, #4] 80051a8: 609a str r2, [r3, #8] /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; 80051aa: 2302 movs r3, #2 80051ac: 623b str r3, [r7, #32] RCC_OscInitStruct.HSIState = RCC_HSI_ON; 80051ae: 2301 movs r3, #1 80051b0: 633b str r3, [r7, #48] ; 0x30 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 80051b2: 2310 movs r3, #16 80051b4: 637b str r3, [r7, #52] ; 0x34 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 80051b6: 2302 movs r3, #2 80051b8: 63fb str r3, [r7, #60] ; 0x3c RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2; 80051ba: 2300 movs r3, #0 80051bc: 643b str r3, [r7, #64] ; 0x40 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6; 80051be: f44f 1380 mov.w r3, #1048576 ; 0x100000 80051c2: 647b str r3, [r7, #68] ; 0x44 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 80051c4: f107 0320 add.w r3, r7, #32 80051c8: 4618 mov r0, r3 80051ca: f7fe f9c7 bl 800355c 80051ce: 4603 mov r3, r0 80051d0: 2b00 cmp r3, #0 80051d2: d001 beq.n 80051d8 { Error_Handler(); 80051d4: f000 fa92 bl 80056fc } /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 80051d8: 230f movs r3, #15 80051da: 60fb str r3, [r7, #12] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 80051dc: 2302 movs r3, #2 80051de: 613b str r3, [r7, #16] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 80051e0: 2300 movs r3, #0 80051e2: 617b str r3, [r7, #20] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 80051e4: 2300 movs r3, #0 80051e6: 61bb str r3, [r7, #24] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 80051e8: 2300 movs r3, #0 80051ea: 61fb str r3, [r7, #28] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) 80051ec: f107 030c add.w r3, r7, #12 80051f0: 2100 movs r1, #0 80051f2: 4618 mov r0, r3 80051f4: f7fe fc32 bl 8003a5c 80051f8: 4603 mov r3, r0 80051fa: 2b00 cmp r3, #0 80051fc: d001 beq.n 8005202 { Error_Handler(); 80051fe: f000 fa7d bl 80056fc } PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; 8005202: 2302 movs r3, #2 8005204: 603b str r3, [r7, #0] PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV2; 8005206: 2300 movs r3, #0 8005208: 60bb str r3, [r7, #8] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 800520a: 463b mov r3, r7 800520c: 4618 mov r0, r3 800520e: f7fe fdbd bl 8003d8c 8005212: 4603 mov r3, r0 8005214: 2b00 cmp r3, #0 8005216: d001 beq.n 800521c { Error_Handler(); 8005218: f000 fa70 bl 80056fc } } 800521c: bf00 nop 800521e: 3748 adds r7, #72 ; 0x48 8005220: 46bd mov sp, r7 8005222: bd80 pop {r7, pc} 08005224 : /** * @brief NVIC Configuration. * @retval None */ static void MX_NVIC_Init(void) { 8005224: b580 push {r7, lr} 8005226: af00 add r7, sp, #0 /* ADC1_IRQn interrupt configuration */ HAL_NVIC_SetPriority(ADC1_IRQn, 0, 0); 8005228: 2200 movs r2, #0 800522a: 2100 movs r1, #0 800522c: 2012 movs r0, #18 800522e: f7fd fb64 bl 80028fa HAL_NVIC_EnableIRQ(ADC1_IRQn); 8005232: 2012 movs r0, #18 8005234: f7fd fb7d bl 8002932 /* USART1_IRQn interrupt configuration */ HAL_NVIC_SetPriority(USART1_IRQn, 0, 0); 8005238: 2200 movs r2, #0 800523a: 2100 movs r1, #0 800523c: 2025 movs r0, #37 ; 0x25 800523e: f7fd fb5c bl 80028fa HAL_NVIC_EnableIRQ(USART1_IRQn); 8005242: 2025 movs r0, #37 ; 0x25 8005244: f7fd fb75 bl 8002932 /* USART3_IRQn interrupt configuration */ HAL_NVIC_SetPriority(USART3_IRQn, 0, 0); 8005248: 2200 movs r2, #0 800524a: 2100 movs r1, #0 800524c: 2027 movs r0, #39 ; 0x27 800524e: f7fd fb54 bl 80028fa HAL_NVIC_EnableIRQ(USART3_IRQn); 8005252: 2027 movs r0, #39 ; 0x27 8005254: f7fd fb6d bl 8002932 /* TIM6_DAC_IRQn interrupt configuration */ HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 0, 0); 8005258: 2200 movs r2, #0 800525a: 2100 movs r1, #0 800525c: 2036 movs r0, #54 ; 0x36 800525e: f7fd fb4c bl 80028fa HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); 8005262: 2036 movs r0, #54 ; 0x36 8005264: f7fd fb65 bl 8002932 /* DMA1_Channel2_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel2_IRQn, 0, 0); 8005268: 2200 movs r2, #0 800526a: 2100 movs r1, #0 800526c: 200c movs r0, #12 800526e: f7fd fb44 bl 80028fa HAL_NVIC_EnableIRQ(DMA1_Channel2_IRQn); 8005272: 200c movs r0, #12 8005274: f7fd fb5d bl 8002932 /* DMA1_Channel4_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel4_IRQn, 0, 0); 8005278: 2200 movs r2, #0 800527a: 2100 movs r1, #0 800527c: 200e movs r0, #14 800527e: f7fd fb3c bl 80028fa HAL_NVIC_EnableIRQ(DMA1_Channel4_IRQn); 8005282: 200e movs r0, #14 8005284: f7fd fb55 bl 8002932 /* DMA1_Channel1_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0); 8005288: 2200 movs r2, #0 800528a: 2100 movs r1, #0 800528c: 200b movs r0, #11 800528e: f7fd fb34 bl 80028fa HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn); 8005292: 200b movs r0, #11 8005294: f7fd fb4d bl 8002932 } 8005298: bf00 nop 800529a: bd80 pop {r7, pc} 0800529c : * @brief ADC1 Initialization Function * @param None * @retval None */ static void MX_ADC1_Init(void) { 800529c: b580 push {r7, lr} 800529e: b084 sub sp, #16 80052a0: af00 add r7, sp, #0 /* USER CODE BEGIN ADC1_Init 0 */ /* USER CODE END ADC1_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 80052a2: 1d3b adds r3, r7, #4 80052a4: 2200 movs r2, #0 80052a6: 601a str r2, [r3, #0] 80052a8: 605a str r2, [r3, #4] 80052aa: 609a str r2, [r3, #8] /* USER CODE BEGIN ADC1_Init 1 */ /* USER CODE END ADC1_Init 1 */ /** Common config */ hadc1.Instance = ADC1; 80052ac: 4b27 ldr r3, [pc, #156] ; (800534c ) 80052ae: 4a28 ldr r2, [pc, #160] ; (8005350 ) 80052b0: 601a str r2, [r3, #0] hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; 80052b2: 4b26 ldr r3, [pc, #152] ; (800534c ) 80052b4: f44f 7280 mov.w r2, #256 ; 0x100 80052b8: 609a str r2, [r3, #8] hadc1.Init.ContinuousConvMode = ENABLE; 80052ba: 4b24 ldr r3, [pc, #144] ; (800534c ) 80052bc: 2201 movs r2, #1 80052be: 731a strb r2, [r3, #12] hadc1.Init.DiscontinuousConvMode = DISABLE; 80052c0: 4b22 ldr r3, [pc, #136] ; (800534c ) 80052c2: 2200 movs r2, #0 80052c4: 751a strb r2, [r3, #20] hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; 80052c6: 4b21 ldr r3, [pc, #132] ; (800534c ) 80052c8: f44f 2260 mov.w r2, #917504 ; 0xe0000 80052cc: 61da str r2, [r3, #28] hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; 80052ce: 4b1f ldr r3, [pc, #124] ; (800534c ) 80052d0: 2200 movs r2, #0 80052d2: 605a str r2, [r3, #4] hadc1.Init.NbrOfConversion = 3; 80052d4: 4b1d ldr r3, [pc, #116] ; (800534c ) 80052d6: 2203 movs r2, #3 80052d8: 611a str r2, [r3, #16] if (HAL_ADC_Init(&hadc1) != HAL_OK) 80052da: 481c ldr r0, [pc, #112] ; (800534c ) 80052dc: f7fc fd78 bl 8001dd0 80052e0: 4603 mov r3, r0 80052e2: 2b00 cmp r3, #0 80052e4: d001 beq.n 80052ea { Error_Handler(); 80052e6: f000 fa09 bl 80056fc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_0; 80052ea: 2300 movs r3, #0 80052ec: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_1; 80052ee: 2301 movs r3, #1 80052f0: 60bb str r3, [r7, #8] sConfig.SamplingTime = ADC_SAMPLETIME_239CYCLES_5; 80052f2: 2307 movs r3, #7 80052f4: 60fb str r3, [r7, #12] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 80052f6: 1d3b adds r3, r7, #4 80052f8: 4619 mov r1, r3 80052fa: 4814 ldr r0, [pc, #80] ; (800534c ) 80052fc: f7fc ffb8 bl 8002270 8005300: 4603 mov r3, r0 8005302: 2b00 cmp r3, #0 8005304: d001 beq.n 800530a { Error_Handler(); 8005306: f000 f9f9 bl 80056fc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_1; 800530a: 2301 movs r3, #1 800530c: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_2; 800530e: 2302 movs r3, #2 8005310: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8005312: 1d3b adds r3, r7, #4 8005314: 4619 mov r1, r3 8005316: 480d ldr r0, [pc, #52] ; (800534c ) 8005318: f7fc ffaa bl 8002270 800531c: 4603 mov r3, r0 800531e: 2b00 cmp r3, #0 8005320: d001 beq.n 8005326 { Error_Handler(); 8005322: f000 f9eb bl 80056fc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_3; 8005326: 2303 movs r3, #3 8005328: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_3; 800532a: 2303 movs r3, #3 800532c: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 800532e: 1d3b adds r3, r7, #4 8005330: 4619 mov r1, r3 8005332: 4806 ldr r0, [pc, #24] ; (800534c ) 8005334: f7fc ff9c bl 8002270 8005338: 4603 mov r3, r0 800533a: 2b00 cmp r3, #0 800533c: d001 beq.n 8005342 { Error_Handler(); 800533e: f000 f9dd bl 80056fc } /* USER CODE BEGIN ADC1_Init 2 */ /* USER CODE END ADC1_Init 2 */ } 8005342: bf00 nop 8005344: 3710 adds r7, #16 8005346: 46bd mov sp, r7 8005348: bd80 pop {r7, pc} 800534a: bf00 nop 800534c: 200008a8 .word 0x200008a8 8005350: 40012400 .word 0x40012400 08005354 : * @brief TIM6 Initialization Function * @param None * @retval None */ static void MX_TIM6_Init(void) { 8005354: b580 push {r7, lr} 8005356: b082 sub sp, #8 8005358: af00 add r7, sp, #0 /* USER CODE BEGIN TIM6_Init 0 */ /* USER CODE END TIM6_Init 0 */ TIM_MasterConfigTypeDef sMasterConfig = {0}; 800535a: 463b mov r3, r7 800535c: 2200 movs r2, #0 800535e: 601a str r2, [r3, #0] 8005360: 605a str r2, [r3, #4] /* USER CODE BEGIN TIM6_Init 1 */ /* USER CODE END TIM6_Init 1 */ htim6.Instance = TIM6; 8005362: 4b15 ldr r3, [pc, #84] ; (80053b8 ) 8005364: 4a15 ldr r2, [pc, #84] ; (80053bc ) 8005366: 601a str r2, [r3, #0] htim6.Init.Prescaler = 2400-1; 8005368: 4b13 ldr r3, [pc, #76] ; (80053b8 ) 800536a: f640 125f movw r2, #2399 ; 0x95f 800536e: 605a str r2, [r3, #4] htim6.Init.CounterMode = TIM_COUNTERMODE_UP; 8005370: 4b11 ldr r3, [pc, #68] ; (80053b8 ) 8005372: 2200 movs r2, #0 8005374: 609a str r2, [r3, #8] htim6.Init.Period = 10; 8005376: 4b10 ldr r3, [pc, #64] ; (80053b8 ) 8005378: 220a movs r2, #10 800537a: 60da str r2, [r3, #12] htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 800537c: 4b0e ldr r3, [pc, #56] ; (80053b8 ) 800537e: 2200 movs r2, #0 8005380: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim6) != HAL_OK) 8005382: 480d ldr r0, [pc, #52] ; (80053b8 ) 8005384: f7fe fe00 bl 8003f88 8005388: 4603 mov r3, r0 800538a: 2b00 cmp r3, #0 800538c: d001 beq.n 8005392 { Error_Handler(); 800538e: f000 f9b5 bl 80056fc } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8005392: 2300 movs r3, #0 8005394: 603b str r3, [r7, #0] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8005396: 2300 movs r3, #0 8005398: 607b str r3, [r7, #4] if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK) 800539a: 463b mov r3, r7 800539c: 4619 mov r1, r3 800539e: 4806 ldr r0, [pc, #24] ; (80053b8 ) 80053a0: f7fe ffec bl 800437c 80053a4: 4603 mov r3, r0 80053a6: 2b00 cmp r3, #0 80053a8: d001 beq.n 80053ae { Error_Handler(); 80053aa: f000 f9a7 bl 80056fc } /* USER CODE BEGIN TIM6_Init 2 */ /* USER CODE END TIM6_Init 2 */ } 80053ae: bf00 nop 80053b0: 3708 adds r7, #8 80053b2: 46bd mov sp, r7 80053b4: bd80 pop {r7, pc} 80053b6: bf00 nop 80053b8: 2000095c .word 0x2000095c 80053bc: 40001000 .word 0x40001000 080053c0 : * @brief USART1 Initialization Function * @param None * @retval None */ static void MX_USART1_UART_Init(void) { 80053c0: b580 push {r7, lr} 80053c2: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 80053c4: 4b11 ldr r3, [pc, #68] ; (800540c ) 80053c6: 4a12 ldr r2, [pc, #72] ; (8005410 ) 80053c8: 601a str r2, [r3, #0] huart1.Init.BaudRate = 115200; 80053ca: 4b10 ldr r3, [pc, #64] ; (800540c ) 80053cc: f44f 32e1 mov.w r2, #115200 ; 0x1c200 80053d0: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 80053d2: 4b0e ldr r3, [pc, #56] ; (800540c ) 80053d4: 2200 movs r2, #0 80053d6: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 80053d8: 4b0c ldr r3, [pc, #48] ; (800540c ) 80053da: 2200 movs r2, #0 80053dc: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 80053de: 4b0b ldr r3, [pc, #44] ; (800540c ) 80053e0: 2200 movs r2, #0 80053e2: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 80053e4: 4b09 ldr r3, [pc, #36] ; (800540c ) 80053e6: 220c movs r2, #12 80053e8: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 80053ea: 4b08 ldr r3, [pc, #32] ; (800540c ) 80053ec: 2200 movs r2, #0 80053ee: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 80053f0: 4b06 ldr r3, [pc, #24] ; (800540c ) 80053f2: 2200 movs r2, #0 80053f4: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart1) != HAL_OK) 80053f6: 4805 ldr r0, [pc, #20] ; (800540c ) 80053f8: f7ff f816 bl 8004428 80053fc: 4603 mov r3, r0 80053fe: 2b00 cmp r3, #0 8005400: d001 beq.n 8005406 { Error_Handler(); 8005402: f000 f97b bl 80056fc } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 8005406: bf00 nop 8005408: bd80 pop {r7, pc} 800540a: bf00 nop 800540c: 200008d8 .word 0x200008d8 8005410: 40013800 .word 0x40013800 08005414 : * @brief USART3 Initialization Function * @param None * @retval None */ static void MX_USART3_UART_Init(void) { 8005414: b580 push {r7, lr} 8005416: af00 add r7, sp, #0 /* USER CODE END USART3_Init 0 */ /* USER CODE BEGIN USART3_Init 1 */ /* USER CODE END USART3_Init 1 */ huart3.Instance = USART3; 8005418: 4b11 ldr r3, [pc, #68] ; (8005460 ) 800541a: 4a12 ldr r2, [pc, #72] ; (8005464 ) 800541c: 601a str r2, [r3, #0] huart3.Init.BaudRate = 115200; 800541e: 4b10 ldr r3, [pc, #64] ; (8005460 ) 8005420: f44f 32e1 mov.w r2, #115200 ; 0x1c200 8005424: 605a str r2, [r3, #4] huart3.Init.WordLength = UART_WORDLENGTH_8B; 8005426: 4b0e ldr r3, [pc, #56] ; (8005460 ) 8005428: 2200 movs r2, #0 800542a: 609a str r2, [r3, #8] huart3.Init.StopBits = UART_STOPBITS_1; 800542c: 4b0c ldr r3, [pc, #48] ; (8005460 ) 800542e: 2200 movs r2, #0 8005430: 60da str r2, [r3, #12] huart3.Init.Parity = UART_PARITY_NONE; 8005432: 4b0b ldr r3, [pc, #44] ; (8005460 ) 8005434: 2200 movs r2, #0 8005436: 611a str r2, [r3, #16] huart3.Init.Mode = UART_MODE_TX_RX; 8005438: 4b09 ldr r3, [pc, #36] ; (8005460 ) 800543a: 220c movs r2, #12 800543c: 615a str r2, [r3, #20] huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800543e: 4b08 ldr r3, [pc, #32] ; (8005460 ) 8005440: 2200 movs r2, #0 8005442: 619a str r2, [r3, #24] huart3.Init.OverSampling = UART_OVERSAMPLING_16; 8005444: 4b06 ldr r3, [pc, #24] ; (8005460 ) 8005446: 2200 movs r2, #0 8005448: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart3) != HAL_OK) 800544a: 4805 ldr r0, [pc, #20] ; (8005460 ) 800544c: f7fe ffec bl 8004428 8005450: 4603 mov r3, r0 8005452: 2b00 cmp r3, #0 8005454: d001 beq.n 800545a { Error_Handler(); 8005456: f000 f951 bl 80056fc } /* USER CODE BEGIN USART3_Init 2 */ /* USER CODE END USART3_Init 2 */ } 800545a: bf00 nop 800545c: bd80 pop {r7, pc} 800545e: bf00 nop 8005460: 200007e0 .word 0x200007e0 8005464: 40004800 .word 0x40004800 08005468 : /** * Enable DMA controller clock */ static void MX_DMA_Init(void) { 8005468: b480 push {r7} 800546a: b083 sub sp, #12 800546c: af00 add r7, sp, #0 /* DMA controller clock enable */ __HAL_RCC_DMA1_CLK_ENABLE(); 800546e: 4b08 ldr r3, [pc, #32] ; (8005490 ) 8005470: 695b ldr r3, [r3, #20] 8005472: 4a07 ldr r2, [pc, #28] ; (8005490 ) 8005474: f043 0301 orr.w r3, r3, #1 8005478: 6153 str r3, [r2, #20] 800547a: 4b05 ldr r3, [pc, #20] ; (8005490 ) 800547c: 695b ldr r3, [r3, #20] 800547e: f003 0301 and.w r3, r3, #1 8005482: 607b str r3, [r7, #4] 8005484: 687b ldr r3, [r7, #4] } 8005486: bf00 nop 8005488: 370c adds r7, #12 800548a: 46bd mov sp, r7 800548c: bc80 pop {r7} 800548e: 4770 bx lr 8005490: 40021000 .word 0x40021000 08005494 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 8005494: b580 push {r7, lr} 8005496: b088 sub sp, #32 8005498: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 800549a: f107 0310 add.w r3, r7, #16 800549e: 2200 movs r2, #0 80054a0: 601a str r2, [r3, #0] 80054a2: 605a str r2, [r3, #4] 80054a4: 609a str r2, [r3, #8] 80054a6: 60da str r2, [r3, #12] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); 80054a8: 4b40 ldr r3, [pc, #256] ; (80055ac ) 80054aa: 699b ldr r3, [r3, #24] 80054ac: 4a3f ldr r2, [pc, #252] ; (80055ac ) 80054ae: f043 0310 orr.w r3, r3, #16 80054b2: 6193 str r3, [r2, #24] 80054b4: 4b3d ldr r3, [pc, #244] ; (80055ac ) 80054b6: 699b ldr r3, [r3, #24] 80054b8: f003 0310 and.w r3, r3, #16 80054bc: 60fb str r3, [r7, #12] 80054be: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 80054c0: 4b3a ldr r3, [pc, #232] ; (80055ac ) 80054c2: 699b ldr r3, [r3, #24] 80054c4: 4a39 ldr r2, [pc, #228] ; (80055ac ) 80054c6: f043 0304 orr.w r3, r3, #4 80054ca: 6193 str r3, [r2, #24] 80054cc: 4b37 ldr r3, [pc, #220] ; (80055ac ) 80054ce: 699b ldr r3, [r3, #24] 80054d0: f003 0304 and.w r3, r3, #4 80054d4: 60bb str r3, [r7, #8] 80054d6: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOB_CLK_ENABLE(); 80054d8: 4b34 ldr r3, [pc, #208] ; (80055ac ) 80054da: 699b ldr r3, [r3, #24] 80054dc: 4a33 ldr r2, [pc, #204] ; (80055ac ) 80054de: f043 0308 orr.w r3, r3, #8 80054e2: 6193 str r3, [r2, #24] 80054e4: 4b31 ldr r3, [pc, #196] ; (80055ac ) 80054e6: 699b ldr r3, [r3, #24] 80054e8: f003 0308 and.w r3, r3, #8 80054ec: 607b str r3, [r7, #4] 80054ee: 687b ldr r3, [r7, #4] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(BOOT_LED_GPIO_Port, BOOT_LED_Pin, GPIO_PIN_RESET); 80054f0: 2200 movs r2, #0 80054f2: f44f 4100 mov.w r1, #32768 ; 0x8000 80054f6: 482e ldr r0, [pc, #184] ; (80055b0 ) 80054f8: f7fd ffff bl 80034fa /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOA, PAU_RESERVED0_Pin|PAU_RESERVED1_Pin|AMP_EN_Pin, GPIO_PIN_RESET); 80054fc: 2200 movs r2, #0 80054fe: f44f 71e0 mov.w r1, #448 ; 0x1c0 8005502: 482c ldr r0, [pc, #176] ; (80055b4 ) 8005504: f7fd fff9 bl 80034fa /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOB, PAU_RESERVED3_Pin|PAU_RESERVED2_Pin|PAU_RESET_Pin, GPIO_PIN_RESET); 8005508: 2200 movs r2, #0 800550a: f244 0103 movw r1, #16387 ; 0x4003 800550e: 482a ldr r0, [pc, #168] ; (80055b8 ) 8005510: f7fd fff3 bl 80034fa /*Configure GPIO pin : BOOT_LED_Pin */ GPIO_InitStruct.Pin = BOOT_LED_Pin; 8005514: f44f 4300 mov.w r3, #32768 ; 0x8000 8005518: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800551a: 2301 movs r3, #1 800551c: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 800551e: 2300 movs r3, #0 8005520: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8005522: 2302 movs r3, #2 8005524: 61fb str r3, [r7, #28] HAL_GPIO_Init(BOOT_LED_GPIO_Port, &GPIO_InitStruct); 8005526: f107 0310 add.w r3, r7, #16 800552a: 4619 mov r1, r3 800552c: 4820 ldr r0, [pc, #128] ; (80055b0 ) 800552e: f7fd fe73 bl 8003218 /*Configure GPIO pins : DC_FAIL_ALARM_Pin OVER_INPUT_ALARM_Pin OVER_TEMP_ALARM_Pin */ GPIO_InitStruct.Pin = DC_FAIL_ALARM_Pin|OVER_INPUT_ALARM_Pin|OVER_TEMP_ALARM_Pin; 8005532: f641 0304 movw r3, #6148 ; 0x1804 8005536: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8005538: 2300 movs r3, #0 800553a: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 800553c: 2300 movs r3, #0 800553e: 61bb str r3, [r7, #24] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8005540: f107 0310 add.w r3, r7, #16 8005544: 4619 mov r1, r3 8005546: 481b ldr r0, [pc, #108] ; (80055b4 ) 8005548: f7fd fe66 bl 8003218 /*Configure GPIO pins : PAU_RESERVED0_Pin PAU_RESERVED1_Pin AMP_EN_Pin */ GPIO_InitStruct.Pin = PAU_RESERVED0_Pin|PAU_RESERVED1_Pin|AMP_EN_Pin; 800554c: f44f 73e0 mov.w r3, #448 ; 0x1c0 8005550: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8005552: 2301 movs r3, #1 8005554: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 8005556: 2300 movs r3, #0 8005558: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800555a: 2302 movs r3, #2 800555c: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800555e: f107 0310 add.w r3, r7, #16 8005562: 4619 mov r1, r3 8005564: 4813 ldr r0, [pc, #76] ; (80055b4 ) 8005566: f7fd fe57 bl 8003218 /*Configure GPIO pins : PAU_RESERVED3_Pin PAU_RESERVED2_Pin PAU_RESET_Pin */ GPIO_InitStruct.Pin = PAU_RESERVED3_Pin|PAU_RESERVED2_Pin|PAU_RESET_Pin; 800556a: f244 0303 movw r3, #16387 ; 0x4003 800556e: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8005570: 2301 movs r3, #1 8005572: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 8005574: 2300 movs r3, #0 8005576: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8005578: 2302 movs r3, #2 800557a: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800557c: f107 0310 add.w r3, r7, #16 8005580: 4619 mov r1, r3 8005582: 480d ldr r0, [pc, #52] ; (80055b8 ) 8005584: f7fd fe48 bl 8003218 /*Configure GPIO pins : OVER_POWER_ALARM_Pin VSWR_ALARM_Pin PAU_EN_Pin ALC_ALARM_Pin */ GPIO_InitStruct.Pin = OVER_POWER_ALARM_Pin|VSWR_ALARM_Pin|PAU_EN_Pin|ALC_ALARM_Pin; 8005588: f24b 0308 movw r3, #45064 ; 0xb008 800558c: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 800558e: 2300 movs r3, #0 8005590: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 8005592: 2300 movs r3, #0 8005594: 61bb str r3, [r7, #24] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8005596: f107 0310 add.w r3, r7, #16 800559a: 4619 mov r1, r3 800559c: 4806 ldr r0, [pc, #24] ; (80055b8 ) 800559e: f7fd fe3b bl 8003218 } 80055a2: bf00 nop 80055a4: 3720 adds r7, #32 80055a6: 46bd mov sp, r7 80055a8: bd80 pop {r7, pc} 80055aa: bf00 nop 80055ac: 40021000 .word 0x40021000 80055b0: 40011000 .word 0x40011000 80055b4: 40010800 .word 0x40010800 80055b8: 40010c00 .word 0x40010c00 080055bc : * a global variable "uwTick" used as application time base. * @param htim : TIM handle * @retval None */ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { 80055bc: b580 push {r7, lr} 80055be: b082 sub sp, #8 80055c0: af00 add r7, sp, #0 80055c2: 6078 str r0, [r7, #4] /* USER CODE BEGIN Callback 0 */ /* USER CODE END Callback 0 */ if (htim->Instance == TIM2) { 80055c4: 687b ldr r3, [r7, #4] 80055c6: 681b ldr r3, [r3, #0] 80055c8: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 80055cc: d101 bne.n 80055d2 HAL_IncTick(); 80055ce: f7fc fbc1 bl 8001d54 } /* USER CODE BEGIN Callback 1 */ if(htim->Instance == TIM6){ 80055d2: 687b ldr r3, [r7, #4] 80055d4: 681b ldr r3, [r3, #0] 80055d6: 4a3d ldr r2, [pc, #244] ; (80056cc ) 80055d8: 4293 cmp r3, r2 80055da: d172 bne.n 80056c2 UartRxTimerCnt++; 80055dc: 4b3c ldr r3, [pc, #240] ; (80056d0 ) 80055de: 681b ldr r3, [r3, #0] 80055e0: 3301 adds r3, #1 80055e2: 4a3b ldr r2, [pc, #236] ; (80056d0 ) 80055e4: 6013 str r3, [r2, #0] LED_TimerCnt++; 80055e6: 4b3b ldr r3, [pc, #236] ; (80056d4 ) 80055e8: 681b ldr r3, [r3, #0] 80055ea: 3301 adds r3, #1 80055ec: 4a39 ldr r2, [pc, #228] ; (80056d4 ) 80055ee: 6013 str r3, [r2, #0] TDD_125ms_Cnt++; 80055f0: 4b39 ldr r3, [pc, #228] ; (80056d8 ) 80055f2: 681b ldr r3, [r3, #0] 80055f4: 3301 adds r3, #1 80055f6: 4a38 ldr r2, [pc, #224] ; (80056d8 ) 80055f8: 6013 str r3, [r2, #0] if(HAL_GPIO_ReadPin(DC_FAIL_ALARM_GPIO_Port, DC_FAIL_ALARM_Pin) == GPIO_PIN_SET) 80055fa: 2104 movs r1, #4 80055fc: 4837 ldr r0, [pc, #220] ; (80056dc ) 80055fe: f7fd ff65 bl 80034cc 8005602: 4603 mov r3, r0 8005604: 2b01 cmp r3, #1 8005606: d105 bne.n 8005614 DC_FAIL_ALARM_CNT++; 8005608: 4b35 ldr r3, [pc, #212] ; (80056e0 ) 800560a: 681b ldr r3, [r3, #0] 800560c: 3301 adds r3, #1 800560e: 4a34 ldr r2, [pc, #208] ; (80056e0 ) 8005610: 6013 str r3, [r2, #0] 8005612: e002 b.n 800561a else DC_FAIL_ALARM_CNT = 0; 8005614: 4b32 ldr r3, [pc, #200] ; (80056e0 ) 8005616: 2200 movs r2, #0 8005618: 601a str r2, [r3, #0] if(HAL_GPIO_ReadPin(OVER_INPUT_ALARM_GPIO_Port, OVER_INPUT_ALARM_Pin)== GPIO_PIN_SET) 800561a: f44f 6100 mov.w r1, #2048 ; 0x800 800561e: 482f ldr r0, [pc, #188] ; (80056dc ) 8005620: f7fd ff54 bl 80034cc 8005624: 4603 mov r3, r0 8005626: 2b01 cmp r3, #1 8005628: d105 bne.n 8005636 OVER_INPUT_ALARM_CNT++; 800562a: 4b2e ldr r3, [pc, #184] ; (80056e4 ) 800562c: 681b ldr r3, [r3, #0] 800562e: 3301 adds r3, #1 8005630: 4a2c ldr r2, [pc, #176] ; (80056e4 ) 8005632: 6013 str r3, [r2, #0] 8005634: e002 b.n 800563c else OVER_INPUT_ALARM_CNT = 0; 8005636: 4b2b ldr r3, [pc, #172] ; (80056e4 ) 8005638: 2200 movs r2, #0 800563a: 601a str r2, [r3, #0] if(HAL_GPIO_ReadPin(OVER_TEMP_ALARM_GPIO_Port, OVER_TEMP_ALARM_Pin)== GPIO_PIN_SET) 800563c: f44f 5180 mov.w r1, #4096 ; 0x1000 8005640: 4826 ldr r0, [pc, #152] ; (80056dc ) 8005642: f7fd ff43 bl 80034cc 8005646: 4603 mov r3, r0 8005648: 2b01 cmp r3, #1 800564a: d105 bne.n 8005658 OVER_TEMP_ALARM_CNT++; 800564c: 4b26 ldr r3, [pc, #152] ; (80056e8 ) 800564e: 681b ldr r3, [r3, #0] 8005650: 3301 adds r3, #1 8005652: 4a25 ldr r2, [pc, #148] ; (80056e8 ) 8005654: 6013 str r3, [r2, #0] 8005656: e002 b.n 800565e else OVER_TEMP_ALARM_CNT = 0; 8005658: 4b23 ldr r3, [pc, #140] ; (80056e8 ) 800565a: 2200 movs r2, #0 800565c: 601a str r2, [r3, #0] if(HAL_GPIO_ReadPin(ALC_ALARM_GPIO_Port, ALC_ALARM_Pin)== GPIO_PIN_SET) 800565e: 2108 movs r1, #8 8005660: 4822 ldr r0, [pc, #136] ; (80056ec ) 8005662: f7fd ff33 bl 80034cc 8005666: 4603 mov r3, r0 8005668: 2b01 cmp r3, #1 800566a: d105 bne.n 8005678 ALC_ALARM_CNT++; 800566c: 4b20 ldr r3, [pc, #128] ; (80056f0 ) 800566e: 681b ldr r3, [r3, #0] 8005670: 3301 adds r3, #1 8005672: 4a1f ldr r2, [pc, #124] ; (80056f0 ) 8005674: 6013 str r3, [r2, #0] 8005676: e002 b.n 800567e else ALC_ALARM_CNT = 0; 8005678: 4b1d ldr r3, [pc, #116] ; (80056f0 ) 800567a: 2200 movs r2, #0 800567c: 601a str r2, [r3, #0] if(HAL_GPIO_ReadPin(OVER_POWER_ALARM_GPIO_Port, OVER_POWER_ALARM_Pin)== GPIO_PIN_SET) 800567e: f44f 5180 mov.w r1, #4096 ; 0x1000 8005682: 481a ldr r0, [pc, #104] ; (80056ec ) 8005684: f7fd ff22 bl 80034cc 8005688: 4603 mov r3, r0 800568a: 2b01 cmp r3, #1 800568c: d105 bne.n 800569a OVER_POWER_ALARM_CNT++; 800568e: 4b19 ldr r3, [pc, #100] ; (80056f4 ) 8005690: 681b ldr r3, [r3, #0] 8005692: 3301 adds r3, #1 8005694: 4a17 ldr r2, [pc, #92] ; (80056f4 ) 8005696: 6013 str r3, [r2, #0] 8005698: e002 b.n 80056a0 else OVER_POWER_ALARM_CNT = 0; 800569a: 4b16 ldr r3, [pc, #88] ; (80056f4 ) 800569c: 2200 movs r2, #0 800569e: 601a str r2, [r3, #0] if(HAL_GPIO_ReadPin(VSWR_ALARM_GPIO_Port, VSWR_ALARM_Pin)== GPIO_PIN_SET) 80056a0: f44f 5100 mov.w r1, #8192 ; 0x2000 80056a4: 4811 ldr r0, [pc, #68] ; (80056ec ) 80056a6: f7fd ff11 bl 80034cc 80056aa: 4603 mov r3, r0 80056ac: 2b01 cmp r3, #1 80056ae: d105 bne.n 80056bc VSWR_ALARM_CNT++; 80056b0: 4b11 ldr r3, [pc, #68] ; (80056f8 ) 80056b2: 681b ldr r3, [r3, #0] 80056b4: 3301 adds r3, #1 80056b6: 4a10 ldr r2, [pc, #64] ; (80056f8 ) 80056b8: 6013 str r3, [r2, #0] else VSWR_ALARM_CNT = 0; } /* USER CODE END Callback 1 */ } 80056ba: e002 b.n 80056c2 VSWR_ALARM_CNT = 0; 80056bc: 4b0e ldr r3, [pc, #56] ; (80056f8 ) 80056be: 2200 movs r2, #0 80056c0: 601a str r2, [r3, #0] } 80056c2: bf00 nop 80056c4: 3708 adds r7, #8 80056c6: 46bd mov sp, r7 80056c8: bd80 pop {r7, pc} 80056ca: bf00 nop 80056cc: 40001000 .word 0x40001000 80056d0: 200004ec .word 0x200004ec 80056d4: 200004e4 .word 0x200004e4 80056d8: 20000508 .word 0x20000508 80056dc: 40010800 .word 0x40010800 80056e0: 200004f0 .word 0x200004f0 80056e4: 200004f4 .word 0x200004f4 80056e8: 200004f8 .word 0x200004f8 80056ec: 40010c00 .word 0x40010c00 80056f0: 200004fc .word 0x200004fc 80056f4: 20000500 .word 0x20000500 80056f8: 20000504 .word 0x20000504 080056fc : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 80056fc: b480 push {r7} 80056fe: af00 add r7, sp, #0 /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ /* USER CODE END Error_Handler_Debug */ } 8005700: bf00 nop 8005702: 46bd mov sp, r7 8005704: bc80 pop {r7} 8005706: 4770 bx lr 08005708 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8005708: b480 push {r7} 800570a: b085 sub sp, #20 800570c: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_AFIO_CLK_ENABLE(); 800570e: 4b15 ldr r3, [pc, #84] ; (8005764 ) 8005710: 699b ldr r3, [r3, #24] 8005712: 4a14 ldr r2, [pc, #80] ; (8005764 ) 8005714: f043 0301 orr.w r3, r3, #1 8005718: 6193 str r3, [r2, #24] 800571a: 4b12 ldr r3, [pc, #72] ; (8005764 ) 800571c: 699b ldr r3, [r3, #24] 800571e: f003 0301 and.w r3, r3, #1 8005722: 60bb str r3, [r7, #8] 8005724: 68bb ldr r3, [r7, #8] __HAL_RCC_PWR_CLK_ENABLE(); 8005726: 4b0f ldr r3, [pc, #60] ; (8005764 ) 8005728: 69db ldr r3, [r3, #28] 800572a: 4a0e ldr r2, [pc, #56] ; (8005764 ) 800572c: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8005730: 61d3 str r3, [r2, #28] 8005732: 4b0c ldr r3, [pc, #48] ; (8005764 ) 8005734: 69db ldr r3, [r3, #28] 8005736: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 800573a: 607b str r3, [r7, #4] 800573c: 687b ldr r3, [r7, #4] /* System interrupt init*/ /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled */ __HAL_AFIO_REMAP_SWJ_NOJTAG(); 800573e: 4b0a ldr r3, [pc, #40] ; (8005768 ) 8005740: 685b ldr r3, [r3, #4] 8005742: 60fb str r3, [r7, #12] 8005744: 68fb ldr r3, [r7, #12] 8005746: f023 63e0 bic.w r3, r3, #117440512 ; 0x7000000 800574a: 60fb str r3, [r7, #12] 800574c: 68fb ldr r3, [r7, #12] 800574e: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000 8005752: 60fb str r3, [r7, #12] 8005754: 4a04 ldr r2, [pc, #16] ; (8005768 ) 8005756: 68fb ldr r3, [r7, #12] 8005758: 6053 str r3, [r2, #4] /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 800575a: bf00 nop 800575c: 3714 adds r7, #20 800575e: 46bd mov sp, r7 8005760: bc80 pop {r7} 8005762: 4770 bx lr 8005764: 40021000 .word 0x40021000 8005768: 40010000 .word 0x40010000 0800576c : * This function configures the hardware resources used in this example * @param hadc: ADC handle pointer * @retval None */ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) { 800576c: b580 push {r7, lr} 800576e: b088 sub sp, #32 8005770: af00 add r7, sp, #0 8005772: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8005774: f107 0310 add.w r3, r7, #16 8005778: 2200 movs r2, #0 800577a: 601a str r2, [r3, #0] 800577c: 605a str r2, [r3, #4] 800577e: 609a str r2, [r3, #8] 8005780: 60da str r2, [r3, #12] if(hadc->Instance==ADC1) 8005782: 687b ldr r3, [r7, #4] 8005784: 681b ldr r3, [r3, #0] 8005786: 4a28 ldr r2, [pc, #160] ; (8005828 ) 8005788: 4293 cmp r3, r2 800578a: d149 bne.n 8005820 { /* USER CODE BEGIN ADC1_MspInit 0 */ /* USER CODE END ADC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_ADC1_CLK_ENABLE(); 800578c: 4b27 ldr r3, [pc, #156] ; (800582c ) 800578e: 699b ldr r3, [r3, #24] 8005790: 4a26 ldr r2, [pc, #152] ; (800582c ) 8005792: f443 7300 orr.w r3, r3, #512 ; 0x200 8005796: 6193 str r3, [r2, #24] 8005798: 4b24 ldr r3, [pc, #144] ; (800582c ) 800579a: 699b ldr r3, [r3, #24] 800579c: f403 7300 and.w r3, r3, #512 ; 0x200 80057a0: 60fb str r3, [r7, #12] 80057a2: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 80057a4: 4b21 ldr r3, [pc, #132] ; (800582c ) 80057a6: 699b ldr r3, [r3, #24] 80057a8: 4a20 ldr r2, [pc, #128] ; (800582c ) 80057aa: f043 0304 orr.w r3, r3, #4 80057ae: 6193 str r3, [r2, #24] 80057b0: 4b1e ldr r3, [pc, #120] ; (800582c ) 80057b2: 699b ldr r3, [r3, #24] 80057b4: f003 0304 and.w r3, r3, #4 80057b8: 60bb str r3, [r7, #8] 80057ba: 68bb ldr r3, [r7, #8] /**ADC1 GPIO Configuration PA0-WKUP ------> ADC1_IN0 PA1 ------> ADC1_IN1 PA3 ------> ADC1_IN3 */ GPIO_InitStruct.Pin = DL_TX_DET_Pin|DL_RX_DET_Pin|PAU_TEMP_Pin; 80057bc: 230b movs r3, #11 80057be: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 80057c0: 2303 movs r3, #3 80057c2: 617b str r3, [r7, #20] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80057c4: f107 0310 add.w r3, r7, #16 80057c8: 4619 mov r1, r3 80057ca: 4819 ldr r0, [pc, #100] ; (8005830 ) 80057cc: f7fd fd24 bl 8003218 /* ADC1 DMA Init */ /* ADC1 Init */ hdma_adc1.Instance = DMA1_Channel1; 80057d0: 4b18 ldr r3, [pc, #96] ; (8005834 ) 80057d2: 4a19 ldr r2, [pc, #100] ; (8005838 ) 80057d4: 601a str r2, [r3, #0] hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY; 80057d6: 4b17 ldr r3, [pc, #92] ; (8005834 ) 80057d8: 2200 movs r2, #0 80057da: 605a str r2, [r3, #4] hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE; 80057dc: 4b15 ldr r3, [pc, #84] ; (8005834 ) 80057de: 2200 movs r2, #0 80057e0: 609a str r2, [r3, #8] hdma_adc1.Init.MemInc = DMA_MINC_ENABLE; 80057e2: 4b14 ldr r3, [pc, #80] ; (8005834 ) 80057e4: 2280 movs r2, #128 ; 0x80 80057e6: 60da str r2, [r3, #12] hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 80057e8: 4b12 ldr r3, [pc, #72] ; (8005834 ) 80057ea: f44f 7280 mov.w r2, #256 ; 0x100 80057ee: 611a str r2, [r3, #16] hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 80057f0: 4b10 ldr r3, [pc, #64] ; (8005834 ) 80057f2: f44f 6280 mov.w r2, #1024 ; 0x400 80057f6: 615a str r2, [r3, #20] hdma_adc1.Init.Mode = DMA_CIRCULAR; 80057f8: 4b0e ldr r3, [pc, #56] ; (8005834 ) 80057fa: 2220 movs r2, #32 80057fc: 619a str r2, [r3, #24] hdma_adc1.Init.Priority = DMA_PRIORITY_LOW; 80057fe: 4b0d ldr r3, [pc, #52] ; (8005834 ) 8005800: 2200 movs r2, #0 8005802: 61da str r2, [r3, #28] if (HAL_DMA_Init(&hdma_adc1) != HAL_OK) 8005804: 480b ldr r0, [pc, #44] ; (8005834 ) 8005806: f7fd f8a3 bl 8002950 800580a: 4603 mov r3, r0 800580c: 2b00 cmp r3, #0 800580e: d001 beq.n 8005814 { Error_Handler(); 8005810: f7ff ff74 bl 80056fc } __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc1); 8005814: 687b ldr r3, [r7, #4] 8005816: 4a07 ldr r2, [pc, #28] ; (8005834 ) 8005818: 621a str r2, [r3, #32] 800581a: 4a06 ldr r2, [pc, #24] ; (8005834 ) 800581c: 687b ldr r3, [r7, #4] 800581e: 6253 str r3, [r2, #36] ; 0x24 /* USER CODE BEGIN ADC1_MspInit 1 */ /* USER CODE END ADC1_MspInit 1 */ } } 8005820: bf00 nop 8005822: 3720 adds r7, #32 8005824: 46bd mov sp, r7 8005826: bd80 pop {r7, pc} 8005828: 40012400 .word 0x40012400 800582c: 40021000 .word 0x40021000 8005830: 40010800 .word 0x40010800 8005834: 20000918 .word 0x20000918 8005838: 40020008 .word 0x40020008 0800583c : * This function configures the hardware resources used in this example * @param htim_base: TIM_Base handle pointer * @retval None */ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) { 800583c: b480 push {r7} 800583e: b085 sub sp, #20 8005840: af00 add r7, sp, #0 8005842: 6078 str r0, [r7, #4] if(htim_base->Instance==TIM6) 8005844: 687b ldr r3, [r7, #4] 8005846: 681b ldr r3, [r3, #0] 8005848: 4a09 ldr r2, [pc, #36] ; (8005870 ) 800584a: 4293 cmp r3, r2 800584c: d10b bne.n 8005866 { /* USER CODE BEGIN TIM6_MspInit 0 */ /* USER CODE END TIM6_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM6_CLK_ENABLE(); 800584e: 4b09 ldr r3, [pc, #36] ; (8005874 ) 8005850: 69db ldr r3, [r3, #28] 8005852: 4a08 ldr r2, [pc, #32] ; (8005874 ) 8005854: f043 0310 orr.w r3, r3, #16 8005858: 61d3 str r3, [r2, #28] 800585a: 4b06 ldr r3, [pc, #24] ; (8005874 ) 800585c: 69db ldr r3, [r3, #28] 800585e: f003 0310 and.w r3, r3, #16 8005862: 60fb str r3, [r7, #12] 8005864: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN TIM6_MspInit 1 */ /* USER CODE END TIM6_MspInit 1 */ } } 8005866: bf00 nop 8005868: 3714 adds r7, #20 800586a: 46bd mov sp, r7 800586c: bc80 pop {r7} 800586e: 4770 bx lr 8005870: 40001000 .word 0x40001000 8005874: 40021000 .word 0x40021000 08005878 : * This function configures the hardware resources used in this example * @param huart: UART handle pointer * @retval None */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { 8005878: b580 push {r7, lr} 800587a: b08a sub sp, #40 ; 0x28 800587c: af00 add r7, sp, #0 800587e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8005880: f107 0318 add.w r3, r7, #24 8005884: 2200 movs r2, #0 8005886: 601a str r2, [r3, #0] 8005888: 605a str r2, [r3, #4] 800588a: 609a str r2, [r3, #8] 800588c: 60da str r2, [r3, #12] if(huart->Instance==USART1) 800588e: 687b ldr r3, [r7, #4] 8005890: 681b ldr r3, [r3, #0] 8005892: 4a5e ldr r2, [pc, #376] ; (8005a0c ) 8005894: 4293 cmp r3, r2 8005896: d158 bne.n 800594a { /* USER CODE BEGIN USART1_MspInit 0 */ /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); 8005898: 4b5d ldr r3, [pc, #372] ; (8005a10 ) 800589a: 699b ldr r3, [r3, #24] 800589c: 4a5c ldr r2, [pc, #368] ; (8005a10 ) 800589e: f443 4380 orr.w r3, r3, #16384 ; 0x4000 80058a2: 6193 str r3, [r2, #24] 80058a4: 4b5a ldr r3, [pc, #360] ; (8005a10 ) 80058a6: 699b ldr r3, [r3, #24] 80058a8: f403 4380 and.w r3, r3, #16384 ; 0x4000 80058ac: 617b str r3, [r7, #20] 80058ae: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 80058b0: 4b57 ldr r3, [pc, #348] ; (8005a10 ) 80058b2: 699b ldr r3, [r3, #24] 80058b4: 4a56 ldr r2, [pc, #344] ; (8005a10 ) 80058b6: f043 0304 orr.w r3, r3, #4 80058ba: 6193 str r3, [r2, #24] 80058bc: 4b54 ldr r3, [pc, #336] ; (8005a10 ) 80058be: 699b ldr r3, [r3, #24] 80058c0: f003 0304 and.w r3, r3, #4 80058c4: 613b str r3, [r7, #16] 80058c6: 693b ldr r3, [r7, #16] /**USART1 GPIO Configuration PA9 ------> USART1_TX PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_9; 80058c8: f44f 7300 mov.w r3, #512 ; 0x200 80058cc: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80058ce: 2302 movs r3, #2 80058d0: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 80058d2: 2303 movs r3, #3 80058d4: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80058d6: f107 0318 add.w r3, r7, #24 80058da: 4619 mov r1, r3 80058dc: 484d ldr r0, [pc, #308] ; (8005a14 ) 80058de: f7fd fc9b bl 8003218 GPIO_InitStruct.Pin = GPIO_PIN_10; 80058e2: f44f 6380 mov.w r3, #1024 ; 0x400 80058e6: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80058e8: 2300 movs r3, #0 80058ea: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 80058ec: 2300 movs r3, #0 80058ee: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80058f0: f107 0318 add.w r3, r7, #24 80058f4: 4619 mov r1, r3 80058f6: 4847 ldr r0, [pc, #284] ; (8005a14 ) 80058f8: f7fd fc8e bl 8003218 /* USART1 DMA Init */ /* USART1_TX Init */ hdma_usart1_tx.Instance = DMA1_Channel4; 80058fc: 4b46 ldr r3, [pc, #280] ; (8005a18 ) 80058fe: 4a47 ldr r2, [pc, #284] ; (8005a1c ) 8005900: 601a str r2, [r3, #0] hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 8005902: 4b45 ldr r3, [pc, #276] ; (8005a18 ) 8005904: 2210 movs r2, #16 8005906: 605a str r2, [r3, #4] hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE; 8005908: 4b43 ldr r3, [pc, #268] ; (8005a18 ) 800590a: 2200 movs r2, #0 800590c: 609a str r2, [r3, #8] hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE; 800590e: 4b42 ldr r3, [pc, #264] ; (8005a18 ) 8005910: 2280 movs r2, #128 ; 0x80 8005912: 60da str r2, [r3, #12] hdma_usart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8005914: 4b40 ldr r3, [pc, #256] ; (8005a18 ) 8005916: 2200 movs r2, #0 8005918: 611a str r2, [r3, #16] hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 800591a: 4b3f ldr r3, [pc, #252] ; (8005a18 ) 800591c: 2200 movs r2, #0 800591e: 615a str r2, [r3, #20] hdma_usart1_tx.Init.Mode = DMA_NORMAL; 8005920: 4b3d ldr r3, [pc, #244] ; (8005a18 ) 8005922: 2200 movs r2, #0 8005924: 619a str r2, [r3, #24] hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW; 8005926: 4b3c ldr r3, [pc, #240] ; (8005a18 ) 8005928: 2200 movs r2, #0 800592a: 61da str r2, [r3, #28] if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK) 800592c: 483a ldr r0, [pc, #232] ; (8005a18 ) 800592e: f7fd f80f bl 8002950 8005932: 4603 mov r3, r0 8005934: 2b00 cmp r3, #0 8005936: d001 beq.n 800593c { Error_Handler(); 8005938: f7ff fee0 bl 80056fc } __HAL_LINKDMA(huart,hdmatx,hdma_usart1_tx); 800593c: 687b ldr r3, [r7, #4] 800593e: 4a36 ldr r2, [pc, #216] ; (8005a18 ) 8005940: 631a str r2, [r3, #48] ; 0x30 8005942: 4a35 ldr r2, [pc, #212] ; (8005a18 ) 8005944: 687b ldr r3, [r7, #4] 8005946: 6253 str r3, [r2, #36] ; 0x24 /* USER CODE BEGIN USART3_MspInit 1 */ /* USER CODE END USART3_MspInit 1 */ } } 8005948: e05c b.n 8005a04 else if(huart->Instance==USART3) 800594a: 687b ldr r3, [r7, #4] 800594c: 681b ldr r3, [r3, #0] 800594e: 4a34 ldr r2, [pc, #208] ; (8005a20 ) 8005950: 4293 cmp r3, r2 8005952: d157 bne.n 8005a04 __HAL_RCC_USART3_CLK_ENABLE(); 8005954: 4b2e ldr r3, [pc, #184] ; (8005a10 ) 8005956: 69db ldr r3, [r3, #28] 8005958: 4a2d ldr r2, [pc, #180] ; (8005a10 ) 800595a: f443 2380 orr.w r3, r3, #262144 ; 0x40000 800595e: 61d3 str r3, [r2, #28] 8005960: 4b2b ldr r3, [pc, #172] ; (8005a10 ) 8005962: 69db ldr r3, [r3, #28] 8005964: f403 2380 and.w r3, r3, #262144 ; 0x40000 8005968: 60fb str r3, [r7, #12] 800596a: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOB_CLK_ENABLE(); 800596c: 4b28 ldr r3, [pc, #160] ; (8005a10 ) 800596e: 699b ldr r3, [r3, #24] 8005970: 4a27 ldr r2, [pc, #156] ; (8005a10 ) 8005972: f043 0308 orr.w r3, r3, #8 8005976: 6193 str r3, [r2, #24] 8005978: 4b25 ldr r3, [pc, #148] ; (8005a10 ) 800597a: 699b ldr r3, [r3, #24] 800597c: f003 0308 and.w r3, r3, #8 8005980: 60bb str r3, [r7, #8] 8005982: 68bb ldr r3, [r7, #8] GPIO_InitStruct.Pin = GPIO_PIN_10; 8005984: f44f 6380 mov.w r3, #1024 ; 0x400 8005988: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800598a: 2302 movs r3, #2 800598c: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800598e: 2303 movs r3, #3 8005990: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8005992: f107 0318 add.w r3, r7, #24 8005996: 4619 mov r1, r3 8005998: 4822 ldr r0, [pc, #136] ; (8005a24 ) 800599a: f7fd fc3d bl 8003218 GPIO_InitStruct.Pin = GPIO_PIN_11; 800599e: f44f 6300 mov.w r3, #2048 ; 0x800 80059a2: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80059a4: 2300 movs r3, #0 80059a6: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 80059a8: 2300 movs r3, #0 80059aa: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80059ac: f107 0318 add.w r3, r7, #24 80059b0: 4619 mov r1, r3 80059b2: 481c ldr r0, [pc, #112] ; (8005a24 ) 80059b4: f7fd fc30 bl 8003218 hdma_usart3_tx.Instance = DMA1_Channel2; 80059b8: 4b1b ldr r3, [pc, #108] ; (8005a28 ) 80059ba: 4a1c ldr r2, [pc, #112] ; (8005a2c ) 80059bc: 601a str r2, [r3, #0] hdma_usart3_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 80059be: 4b1a ldr r3, [pc, #104] ; (8005a28 ) 80059c0: 2210 movs r2, #16 80059c2: 605a str r2, [r3, #4] hdma_usart3_tx.Init.PeriphInc = DMA_PINC_DISABLE; 80059c4: 4b18 ldr r3, [pc, #96] ; (8005a28 ) 80059c6: 2200 movs r2, #0 80059c8: 609a str r2, [r3, #8] hdma_usart3_tx.Init.MemInc = DMA_MINC_ENABLE; 80059ca: 4b17 ldr r3, [pc, #92] ; (8005a28 ) 80059cc: 2280 movs r2, #128 ; 0x80 80059ce: 60da str r2, [r3, #12] hdma_usart3_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 80059d0: 4b15 ldr r3, [pc, #84] ; (8005a28 ) 80059d2: 2200 movs r2, #0 80059d4: 611a str r2, [r3, #16] hdma_usart3_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 80059d6: 4b14 ldr r3, [pc, #80] ; (8005a28 ) 80059d8: 2200 movs r2, #0 80059da: 615a str r2, [r3, #20] hdma_usart3_tx.Init.Mode = DMA_NORMAL; 80059dc: 4b12 ldr r3, [pc, #72] ; (8005a28 ) 80059de: 2200 movs r2, #0 80059e0: 619a str r2, [r3, #24] hdma_usart3_tx.Init.Priority = DMA_PRIORITY_LOW; 80059e2: 4b11 ldr r3, [pc, #68] ; (8005a28 ) 80059e4: 2200 movs r2, #0 80059e6: 61da str r2, [r3, #28] if (HAL_DMA_Init(&hdma_usart3_tx) != HAL_OK) 80059e8: 480f ldr r0, [pc, #60] ; (8005a28 ) 80059ea: f7fc ffb1 bl 8002950 80059ee: 4603 mov r3, r0 80059f0: 2b00 cmp r3, #0 80059f2: d001 beq.n 80059f8 Error_Handler(); 80059f4: f7ff fe82 bl 80056fc __HAL_LINKDMA(huart,hdmatx,hdma_usart3_tx); 80059f8: 687b ldr r3, [r7, #4] 80059fa: 4a0b ldr r2, [pc, #44] ; (8005a28 ) 80059fc: 631a str r2, [r3, #48] ; 0x30 80059fe: 4a0a ldr r2, [pc, #40] ; (8005a28 ) 8005a00: 687b ldr r3, [r7, #4] 8005a02: 6253 str r3, [r2, #36] ; 0x24 } 8005a04: bf00 nop 8005a06: 3728 adds r7, #40 ; 0x28 8005a08: 46bd mov sp, r7 8005a0a: bd80 pop {r7, pc} 8005a0c: 40013800 .word 0x40013800 8005a10: 40021000 .word 0x40021000 8005a14: 40010800 .word 0x40010800 8005a18: 20000864 .word 0x20000864 8005a1c: 40020044 .word 0x40020044 8005a20: 40004800 .word 0x40004800 8005a24: 40010c00 .word 0x40010c00 8005a28: 20000820 .word 0x20000820 8005a2c: 4002001c .word 0x4002001c 08005a30 : * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). * @param TickPriority: Tick interrupt priority. * @retval HAL status */ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8005a30: b580 push {r7, lr} 8005a32: b08c sub sp, #48 ; 0x30 8005a34: af00 add r7, sp, #0 8005a36: 6078 str r0, [r7, #4] RCC_ClkInitTypeDef clkconfig; uint32_t uwTimclock = 0; 8005a38: 2300 movs r3, #0 8005a3a: 62fb str r3, [r7, #44] ; 0x2c uint32_t uwPrescalerValue = 0; 8005a3c: 2300 movs r3, #0 8005a3e: 62bb str r3, [r7, #40] ; 0x28 uint32_t pFLatency; /*Configure the TIM2 IRQ priority */ HAL_NVIC_SetPriority(TIM2_IRQn, TickPriority ,0); 8005a40: 2200 movs r2, #0 8005a42: 6879 ldr r1, [r7, #4] 8005a44: 201c movs r0, #28 8005a46: f7fc ff58 bl 80028fa /* Enable the TIM2 global Interrupt */ HAL_NVIC_EnableIRQ(TIM2_IRQn); 8005a4a: 201c movs r0, #28 8005a4c: f7fc ff71 bl 8002932 /* Enable TIM2 clock */ __HAL_RCC_TIM2_CLK_ENABLE(); 8005a50: 4b1f ldr r3, [pc, #124] ; (8005ad0 ) 8005a52: 69db ldr r3, [r3, #28] 8005a54: 4a1e ldr r2, [pc, #120] ; (8005ad0 ) 8005a56: f043 0301 orr.w r3, r3, #1 8005a5a: 61d3 str r3, [r2, #28] 8005a5c: 4b1c ldr r3, [pc, #112] ; (8005ad0 ) 8005a5e: 69db ldr r3, [r3, #28] 8005a60: f003 0301 and.w r3, r3, #1 8005a64: 60fb str r3, [r7, #12] 8005a66: 68fb ldr r3, [r7, #12] /* Get clock configuration */ HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); 8005a68: f107 0210 add.w r2, r7, #16 8005a6c: f107 0314 add.w r3, r7, #20 8005a70: 4611 mov r1, r2 8005a72: 4618 mov r0, r3 8005a74: f7fe f940 bl 8003cf8 /* Compute TIM2 clock */ uwTimclock = HAL_RCC_GetPCLK1Freq(); 8005a78: f7fe f916 bl 8003ca8 8005a7c: 62f8 str r0, [r7, #44] ; 0x2c /* Compute the prescaler value to have TIM2 counter clock equal to 1MHz */ uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000) - 1); 8005a7e: 6afb ldr r3, [r7, #44] ; 0x2c 8005a80: 4a14 ldr r2, [pc, #80] ; (8005ad4 ) 8005a82: fba2 2303 umull r2, r3, r2, r3 8005a86: 0c9b lsrs r3, r3, #18 8005a88: 3b01 subs r3, #1 8005a8a: 62bb str r3, [r7, #40] ; 0x28 /* Initialize TIM2 */ htim2.Instance = TIM2; 8005a8c: 4b12 ldr r3, [pc, #72] ; (8005ad8 ) 8005a8e: f04f 4280 mov.w r2, #1073741824 ; 0x40000000 8005a92: 601a str r2, [r3, #0] + Period = [(TIM2CLK/1000) - 1]. to have a (1/1000) s time base. + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. + ClockDivision = 0 + Counter direction = Up */ htim2.Init.Period = (1000000 / 1000) - 1; 8005a94: 4b10 ldr r3, [pc, #64] ; (8005ad8 ) 8005a96: f240 32e7 movw r2, #999 ; 0x3e7 8005a9a: 60da str r2, [r3, #12] htim2.Init.Prescaler = uwPrescalerValue; 8005a9c: 4a0e ldr r2, [pc, #56] ; (8005ad8 ) 8005a9e: 6abb ldr r3, [r7, #40] ; 0x28 8005aa0: 6053 str r3, [r2, #4] htim2.Init.ClockDivision = 0; 8005aa2: 4b0d ldr r3, [pc, #52] ; (8005ad8 ) 8005aa4: 2200 movs r2, #0 8005aa6: 611a str r2, [r3, #16] htim2.Init.CounterMode = TIM_COUNTERMODE_UP; 8005aa8: 4b0b ldr r3, [pc, #44] ; (8005ad8 ) 8005aaa: 2200 movs r2, #0 8005aac: 609a str r2, [r3, #8] if(HAL_TIM_Base_Init(&htim2) == HAL_OK) 8005aae: 480a ldr r0, [pc, #40] ; (8005ad8 ) 8005ab0: f7fe fa6a bl 8003f88 8005ab4: 4603 mov r3, r0 8005ab6: 2b00 cmp r3, #0 8005ab8: d104 bne.n 8005ac4 { /* Start the TIM time Base generation in interrupt mode */ return HAL_TIM_Base_Start_IT(&htim2); 8005aba: 4807 ldr r0, [pc, #28] ; (8005ad8 ) 8005abc: f7fe fa8f bl 8003fde 8005ac0: 4603 mov r3, r0 8005ac2: e000 b.n 8005ac6 } /* Return function status */ return HAL_ERROR; 8005ac4: 2301 movs r3, #1 } 8005ac6: 4618 mov r0, r3 8005ac8: 3730 adds r7, #48 ; 0x30 8005aca: 46bd mov sp, r7 8005acc: bd80 pop {r7, pc} 8005ace: bf00 nop 8005ad0: 40021000 .word 0x40021000 8005ad4: 431bde83 .word 0x431bde83 8005ad8: 2000099c .word 0x2000099c 08005adc : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8005adc: b480 push {r7} 8005ade: af00 add r7, sp, #0 /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ /* USER CODE END NonMaskableInt_IRQn 1 */ } 8005ae0: bf00 nop 8005ae2: 46bd mov sp, r7 8005ae4: bc80 pop {r7} 8005ae6: 4770 bx lr 08005ae8 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8005ae8: b480 push {r7} 8005aea: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8005aec: e7fe b.n 8005aec 08005aee : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8005aee: b480 push {r7} 8005af0: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8005af2: e7fe b.n 8005af2 08005af4 : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { 8005af4: b480 push {r7} 8005af6: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 8005af8: e7fe b.n 8005af8 08005afa : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8005afa: b480 push {r7} 8005afc: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8005afe: e7fe b.n 8005afe 08005b00 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 8005b00: b480 push {r7} 8005b02: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 8005b04: bf00 nop 8005b06: 46bd mov sp, r7 8005b08: bc80 pop {r7} 8005b0a: 4770 bx lr 08005b0c : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 8005b0c: b480 push {r7} 8005b0e: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8005b10: bf00 nop 8005b12: 46bd mov sp, r7 8005b14: bc80 pop {r7} 8005b16: 4770 bx lr 08005b18 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8005b18: b480 push {r7} 8005b1a: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 8005b1c: bf00 nop 8005b1e: 46bd mov sp, r7 8005b20: bc80 pop {r7} 8005b22: 4770 bx lr 08005b24 : /** * @brief This function handles DMA1 channel1 global interrupt. */ void DMA1_Channel1_IRQHandler(void) { 8005b24: b580 push {r7, lr} 8005b26: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */ /* USER CODE END DMA1_Channel1_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc1); 8005b28: 4802 ldr r0, [pc, #8] ; (8005b34 ) 8005b2a: f7fd f841 bl 8002bb0 /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */ /* USER CODE END DMA1_Channel1_IRQn 1 */ } 8005b2e: bf00 nop 8005b30: bd80 pop {r7, pc} 8005b32: bf00 nop 8005b34: 20000918 .word 0x20000918 08005b38 : /** * @brief This function handles DMA1 channel2 global interrupt. */ void DMA1_Channel2_IRQHandler(void) { 8005b38: b580 push {r7, lr} 8005b3a: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Channel2_IRQn 0 */ /* USER CODE END DMA1_Channel2_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart3_tx); 8005b3c: 4802 ldr r0, [pc, #8] ; (8005b48 ) 8005b3e: f7fd f837 bl 8002bb0 /* USER CODE BEGIN DMA1_Channel2_IRQn 1 */ /* USER CODE END DMA1_Channel2_IRQn 1 */ } 8005b42: bf00 nop 8005b44: bd80 pop {r7, pc} 8005b46: bf00 nop 8005b48: 20000820 .word 0x20000820 08005b4c : /** * @brief This function handles DMA1 channel4 global interrupt. */ void DMA1_Channel4_IRQHandler(void) { 8005b4c: b580 push {r7, lr} 8005b4e: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Channel4_IRQn 0 */ /* USER CODE END DMA1_Channel4_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart1_tx); 8005b50: 4802 ldr r0, [pc, #8] ; (8005b5c ) 8005b52: f7fd f82d bl 8002bb0 /* USER CODE BEGIN DMA1_Channel4_IRQn 1 */ /* USER CODE END DMA1_Channel4_IRQn 1 */ } 8005b56: bf00 nop 8005b58: bd80 pop {r7, pc} 8005b5a: bf00 nop 8005b5c: 20000864 .word 0x20000864 08005b60 : /** * @brief This function handles ADC1 global interrupt. */ void ADC1_IRQHandler(void) { 8005b60: b580 push {r7, lr} 8005b62: af00 add r7, sp, #0 /* USER CODE BEGIN ADC1_IRQn 0 */ /* USER CODE END ADC1_IRQn 0 */ HAL_ADC_IRQHandler(&hadc1); 8005b64: 4802 ldr r0, [pc, #8] ; (8005b70 ) 8005b66: f7fc faa5 bl 80020b4 /* USER CODE BEGIN ADC1_IRQn 1 */ /* USER CODE END ADC1_IRQn 1 */ } 8005b6a: bf00 nop 8005b6c: bd80 pop {r7, pc} 8005b6e: bf00 nop 8005b70: 200008a8 .word 0x200008a8 08005b74 : /** * @brief This function handles TIM2 global interrupt. */ void TIM2_IRQHandler(void) { 8005b74: b580 push {r7, lr} 8005b76: af00 add r7, sp, #0 /* USER CODE BEGIN TIM2_IRQn 0 */ /* USER CODE END TIM2_IRQn 0 */ HAL_TIM_IRQHandler(&htim2); 8005b78: 4802 ldr r0, [pc, #8] ; (8005b84 ) 8005b7a: f7fe fa53 bl 8004024 /* USER CODE BEGIN TIM2_IRQn 1 */ /* USER CODE END TIM2_IRQn 1 */ } 8005b7e: bf00 nop 8005b80: bd80 pop {r7, pc} 8005b82: bf00 nop 8005b84: 2000099c .word 0x2000099c 08005b88 : /** * @brief This function handles USART1 global interrupt. */ void USART1_IRQHandler(void) { 8005b88: b580 push {r7, lr} 8005b8a: af00 add r7, sp, #0 /* USER CODE BEGIN USART1_IRQn 0 */ /* USER CODE END USART1_IRQn 0 */ HAL_UART_IRQHandler(&huart1); 8005b8c: 4802 ldr r0, [pc, #8] ; (8005b98 ) 8005b8e: f7fe fdf1 bl 8004774 /* USER CODE BEGIN USART1_IRQn 1 */ /* USER CODE END USART1_IRQn 1 */ } 8005b92: bf00 nop 8005b94: bd80 pop {r7, pc} 8005b96: bf00 nop 8005b98: 200008d8 .word 0x200008d8 08005b9c : /** * @brief This function handles USART3 global interrupt. */ void USART3_IRQHandler(void) { 8005b9c: b580 push {r7, lr} 8005b9e: af00 add r7, sp, #0 /* USER CODE BEGIN USART3_IRQn 0 */ /* USER CODE END USART3_IRQn 0 */ HAL_UART_IRQHandler(&huart3); 8005ba0: 4802 ldr r0, [pc, #8] ; (8005bac ) 8005ba2: f7fe fde7 bl 8004774 /* USER CODE BEGIN USART3_IRQn 1 */ /* USER CODE END USART3_IRQn 1 */ } 8005ba6: bf00 nop 8005ba8: bd80 pop {r7, pc} 8005baa: bf00 nop 8005bac: 200007e0 .word 0x200007e0 08005bb0 : /** * @brief This function handles TIM6 global interrupt and DAC underrun error interrupts. */ void TIM6_DAC_IRQHandler(void) { 8005bb0: b580 push {r7, lr} 8005bb2: af00 add r7, sp, #0 /* USER CODE BEGIN TIM6_DAC_IRQn 0 */ /* USER CODE END TIM6_DAC_IRQn 0 */ HAL_TIM_IRQHandler(&htim6); 8005bb4: 4802 ldr r0, [pc, #8] ; (8005bc0 ) 8005bb6: f7fe fa35 bl 8004024 /* USER CODE BEGIN TIM6_DAC_IRQn 1 */ /* USER CODE END TIM6_DAC_IRQn 1 */ } 8005bba: bf00 nop 8005bbc: bd80 pop {r7, pc} 8005bbe: bf00 nop 8005bc0: 2000095c .word 0x2000095c 08005bc4 <_read>: _kill(status, -1); while (1) {} /* Make sure we hang here */ } __attribute__((weak)) int _read(int file, char *ptr, int len) { 8005bc4: b580 push {r7, lr} 8005bc6: b086 sub sp, #24 8005bc8: af00 add r7, sp, #0 8005bca: 60f8 str r0, [r7, #12] 8005bcc: 60b9 str r1, [r7, #8] 8005bce: 607a str r2, [r7, #4] int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 8005bd0: 2300 movs r3, #0 8005bd2: 617b str r3, [r7, #20] 8005bd4: e00a b.n 8005bec <_read+0x28> { *ptr++ = __io_getchar(); 8005bd6: f3af 8000 nop.w 8005bda: 4601 mov r1, r0 8005bdc: 68bb ldr r3, [r7, #8] 8005bde: 1c5a adds r2, r3, #1 8005be0: 60ba str r2, [r7, #8] 8005be2: b2ca uxtb r2, r1 8005be4: 701a strb r2, [r3, #0] for (DataIdx = 0; DataIdx < len; DataIdx++) 8005be6: 697b ldr r3, [r7, #20] 8005be8: 3301 adds r3, #1 8005bea: 617b str r3, [r7, #20] 8005bec: 697a ldr r2, [r7, #20] 8005bee: 687b ldr r3, [r7, #4] 8005bf0: 429a cmp r2, r3 8005bf2: dbf0 blt.n 8005bd6 <_read+0x12> } return len; 8005bf4: 687b ldr r3, [r7, #4] } 8005bf6: 4618 mov r0, r3 8005bf8: 3718 adds r7, #24 8005bfa: 46bd mov sp, r7 8005bfc: bd80 pop {r7, pc} 08005bfe <_close>: } return len; } int _close(int file) { 8005bfe: b480 push {r7} 8005c00: b083 sub sp, #12 8005c02: af00 add r7, sp, #0 8005c04: 6078 str r0, [r7, #4] return -1; 8005c06: f04f 33ff mov.w r3, #4294967295 } 8005c0a: 4618 mov r0, r3 8005c0c: 370c adds r7, #12 8005c0e: 46bd mov sp, r7 8005c10: bc80 pop {r7} 8005c12: 4770 bx lr 08005c14 <_fstat>: int _fstat(int file, struct stat *st) { 8005c14: b480 push {r7} 8005c16: b083 sub sp, #12 8005c18: af00 add r7, sp, #0 8005c1a: 6078 str r0, [r7, #4] 8005c1c: 6039 str r1, [r7, #0] st->st_mode = S_IFCHR; 8005c1e: 683b ldr r3, [r7, #0] 8005c20: f44f 5200 mov.w r2, #8192 ; 0x2000 8005c24: 605a str r2, [r3, #4] return 0; 8005c26: 2300 movs r3, #0 } 8005c28: 4618 mov r0, r3 8005c2a: 370c adds r7, #12 8005c2c: 46bd mov sp, r7 8005c2e: bc80 pop {r7} 8005c30: 4770 bx lr 08005c32 <_isatty>: int _isatty(int file) { 8005c32: b480 push {r7} 8005c34: b083 sub sp, #12 8005c36: af00 add r7, sp, #0 8005c38: 6078 str r0, [r7, #4] return 1; 8005c3a: 2301 movs r3, #1 } 8005c3c: 4618 mov r0, r3 8005c3e: 370c adds r7, #12 8005c40: 46bd mov sp, r7 8005c42: bc80 pop {r7} 8005c44: 4770 bx lr 08005c46 <_lseek>: int _lseek(int file, int ptr, int dir) { 8005c46: b480 push {r7} 8005c48: b085 sub sp, #20 8005c4a: af00 add r7, sp, #0 8005c4c: 60f8 str r0, [r7, #12] 8005c4e: 60b9 str r1, [r7, #8] 8005c50: 607a str r2, [r7, #4] return 0; 8005c52: 2300 movs r3, #0 } 8005c54: 4618 mov r0, r3 8005c56: 3714 adds r7, #20 8005c58: 46bd mov sp, r7 8005c5a: bc80 pop {r7} 8005c5c: 4770 bx lr ... 08005c60 <_sbrk>: /** _sbrk Increase program data space. Malloc and related functions depend on this **/ caddr_t _sbrk(int incr) { 8005c60: b580 push {r7, lr} 8005c62: b084 sub sp, #16 8005c64: af00 add r7, sp, #0 8005c66: 6078 str r0, [r7, #4] extern char end asm("end"); static char *heap_end; char *prev_heap_end; if (heap_end == 0) 8005c68: 4b11 ldr r3, [pc, #68] ; (8005cb0 <_sbrk+0x50>) 8005c6a: 681b ldr r3, [r3, #0] 8005c6c: 2b00 cmp r3, #0 8005c6e: d102 bne.n 8005c76 <_sbrk+0x16> heap_end = &end; 8005c70: 4b0f ldr r3, [pc, #60] ; (8005cb0 <_sbrk+0x50>) 8005c72: 4a10 ldr r2, [pc, #64] ; (8005cb4 <_sbrk+0x54>) 8005c74: 601a str r2, [r3, #0] prev_heap_end = heap_end; 8005c76: 4b0e ldr r3, [pc, #56] ; (8005cb0 <_sbrk+0x50>) 8005c78: 681b ldr r3, [r3, #0] 8005c7a: 60fb str r3, [r7, #12] if (heap_end + incr > stack_ptr) 8005c7c: 4b0c ldr r3, [pc, #48] ; (8005cb0 <_sbrk+0x50>) 8005c7e: 681a ldr r2, [r3, #0] 8005c80: 687b ldr r3, [r7, #4] 8005c82: 4413 add r3, r2 8005c84: 466a mov r2, sp 8005c86: 4293 cmp r3, r2 8005c88: d907 bls.n 8005c9a <_sbrk+0x3a> { errno = ENOMEM; 8005c8a: f000 f873 bl 8005d74 <__errno> 8005c8e: 4602 mov r2, r0 8005c90: 230c movs r3, #12 8005c92: 6013 str r3, [r2, #0] return (caddr_t) -1; 8005c94: f04f 33ff mov.w r3, #4294967295 8005c98: e006 b.n 8005ca8 <_sbrk+0x48> } heap_end += incr; 8005c9a: 4b05 ldr r3, [pc, #20] ; (8005cb0 <_sbrk+0x50>) 8005c9c: 681a ldr r2, [r3, #0] 8005c9e: 687b ldr r3, [r7, #4] 8005ca0: 4413 add r3, r2 8005ca2: 4a03 ldr r2, [pc, #12] ; (8005cb0 <_sbrk+0x50>) 8005ca4: 6013 str r3, [r2, #0] return (caddr_t) prev_heap_end; 8005ca6: 68fb ldr r3, [r7, #12] } 8005ca8: 4618 mov r0, r3 8005caa: 3710 adds r7, #16 8005cac: 46bd mov sp, r7 8005cae: bd80 pop {r7, pc} 8005cb0: 2000050c .word 0x2000050c 8005cb4: 200009e0 .word 0x200009e0 08005cb8 : * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit (void) { 8005cb8: b480 push {r7} 8005cba: af00 add r7, sp, #0 /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ /* Set HSION bit */ RCC->CR |= 0x00000001U; 8005cbc: 4b17 ldr r3, [pc, #92] ; (8005d1c ) 8005cbe: 681b ldr r3, [r3, #0] 8005cc0: 4a16 ldr r2, [pc, #88] ; (8005d1c ) 8005cc2: f043 0301 orr.w r3, r3, #1 8005cc6: 6013 str r3, [r2, #0] /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ #if !defined(STM32F105xC) && !defined(STM32F107xC) RCC->CFGR &= 0xF8FF0000U; 8005cc8: 4b14 ldr r3, [pc, #80] ; (8005d1c ) 8005cca: 685a ldr r2, [r3, #4] 8005ccc: 4913 ldr r1, [pc, #76] ; (8005d1c ) 8005cce: 4b14 ldr r3, [pc, #80] ; (8005d20 ) 8005cd0: 4013 ands r3, r2 8005cd2: 604b str r3, [r1, #4] #else RCC->CFGR &= 0xF0FF0000U; #endif /* STM32F105xC */ /* Reset HSEON, CSSON and PLLON bits */ RCC->CR &= 0xFEF6FFFFU; 8005cd4: 4b11 ldr r3, [pc, #68] ; (8005d1c ) 8005cd6: 681b ldr r3, [r3, #0] 8005cd8: 4a10 ldr r2, [pc, #64] ; (8005d1c ) 8005cda: f023 7384 bic.w r3, r3, #17301504 ; 0x1080000 8005cde: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8005ce2: 6013 str r3, [r2, #0] /* Reset HSEBYP bit */ RCC->CR &= 0xFFFBFFFFU; 8005ce4: 4b0d ldr r3, [pc, #52] ; (8005d1c ) 8005ce6: 681b ldr r3, [r3, #0] 8005ce8: 4a0c ldr r2, [pc, #48] ; (8005d1c ) 8005cea: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8005cee: 6013 str r3, [r2, #0] /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ RCC->CFGR &= 0xFF80FFFFU; 8005cf0: 4b0a ldr r3, [pc, #40] ; (8005d1c ) 8005cf2: 685b ldr r3, [r3, #4] 8005cf4: 4a09 ldr r2, [pc, #36] ; (8005d1c ) 8005cf6: f423 03fe bic.w r3, r3, #8323072 ; 0x7f0000 8005cfa: 6053 str r3, [r2, #4] /* Reset CFGR2 register */ RCC->CFGR2 = 0x00000000U; #elif defined(STM32F100xB) || defined(STM32F100xE) /* Disable all interrupts and clear pending bits */ RCC->CIR = 0x009F0000U; 8005cfc: 4b07 ldr r3, [pc, #28] ; (8005d1c ) 8005cfe: f44f 021f mov.w r2, #10420224 ; 0x9f0000 8005d02: 609a str r2, [r3, #8] /* Reset CFGR2 register */ RCC->CFGR2 = 0x00000000U; 8005d04: 4b05 ldr r3, [pc, #20] ; (8005d1c ) 8005d06: 2200 movs r2, #0 8005d08: 62da str r2, [r3, #44] ; 0x2c #endif #ifdef VECT_TAB_SRAM SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #else SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ 8005d0a: 4b06 ldr r3, [pc, #24] ; (8005d24 ) 8005d0c: f04f 6200 mov.w r2, #134217728 ; 0x8000000 8005d10: 609a str r2, [r3, #8] #endif } 8005d12: bf00 nop 8005d14: 46bd mov sp, r7 8005d16: bc80 pop {r7} 8005d18: 4770 bx lr 8005d1a: bf00 nop 8005d1c: 40021000 .word 0x40021000 8005d20: f8ff0000 .word 0xf8ff0000 8005d24: e000ed00 .word 0xe000ed00 08005d28 : .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 8005d28: 2100 movs r1, #0 b LoopCopyDataInit 8005d2a: e003 b.n 8005d34 08005d2c : CopyDataInit: ldr r3, =_sidata 8005d2c: 4b0b ldr r3, [pc, #44] ; (8005d5c ) ldr r3, [r3, r1] 8005d2e: 585b ldr r3, [r3, r1] str r3, [r0, r1] 8005d30: 5043 str r3, [r0, r1] adds r1, r1, #4 8005d32: 3104 adds r1, #4 08005d34 : LoopCopyDataInit: ldr r0, =_sdata 8005d34: 480a ldr r0, [pc, #40] ; (8005d60 ) ldr r3, =_edata 8005d36: 4b0b ldr r3, [pc, #44] ; (8005d64 ) adds r2, r0, r1 8005d38: 1842 adds r2, r0, r1 cmp r2, r3 8005d3a: 429a cmp r2, r3 bcc CopyDataInit 8005d3c: d3f6 bcc.n 8005d2c ldr r2, =_sbss 8005d3e: 4a0a ldr r2, [pc, #40] ; (8005d68 ) b LoopFillZerobss 8005d40: e002 b.n 8005d48 08005d42 : /* Zero fill the bss segment. */ FillZerobss: movs r3, #0 8005d42: 2300 movs r3, #0 str r3, [r2], #4 8005d44: f842 3b04 str.w r3, [r2], #4 08005d48 : LoopFillZerobss: ldr r3, = _ebss 8005d48: 4b08 ldr r3, [pc, #32] ; (8005d6c ) cmp r2, r3 8005d4a: 429a cmp r2, r3 bcc FillZerobss 8005d4c: d3f9 bcc.n 8005d42 /* Call the clock system intitialization function.*/ bl SystemInit 8005d4e: f7ff ffb3 bl 8005cb8 /* Call static constructors */ bl __libc_init_array 8005d52: f000 f815 bl 8005d80 <__libc_init_array> /* Call the application's entry point.*/ bl main 8005d56: f7ff f9bf bl 80050d8
bx lr 8005d5a: 4770 bx lr ldr r3, =_sidata 8005d5c: 08008c70 .word 0x08008c70 ldr r0, =_sdata 8005d60: 20000000 .word 0x20000000 ldr r3, =_edata 8005d64: 200001dc .word 0x200001dc ldr r2, =_sbss 8005d68: 200001e0 .word 0x200001e0 ldr r3, = _ebss 8005d6c: 200009e0 .word 0x200009e0 08005d70 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8005d70: e7fe b.n 8005d70 ... 08005d74 <__errno>: 8005d74: 4b01 ldr r3, [pc, #4] ; (8005d7c <__errno+0x8>) 8005d76: 6818 ldr r0, [r3, #0] 8005d78: 4770 bx lr 8005d7a: bf00 nop 8005d7c: 2000000c .word 0x2000000c 08005d80 <__libc_init_array>: 8005d80: b570 push {r4, r5, r6, lr} 8005d82: 2500 movs r5, #0 8005d84: 4e0c ldr r6, [pc, #48] ; (8005db8 <__libc_init_array+0x38>) 8005d86: 4c0d ldr r4, [pc, #52] ; (8005dbc <__libc_init_array+0x3c>) 8005d88: 1ba4 subs r4, r4, r6 8005d8a: 10a4 asrs r4, r4, #2 8005d8c: 42a5 cmp r5, r4 8005d8e: d109 bne.n 8005da4 <__libc_init_array+0x24> 8005d90: f002 fc60 bl 8008654 <_init> 8005d94: 2500 movs r5, #0 8005d96: 4e0a ldr r6, [pc, #40] ; (8005dc0 <__libc_init_array+0x40>) 8005d98: 4c0a ldr r4, [pc, #40] ; (8005dc4 <__libc_init_array+0x44>) 8005d9a: 1ba4 subs r4, r4, r6 8005d9c: 10a4 asrs r4, r4, #2 8005d9e: 42a5 cmp r5, r4 8005da0: d105 bne.n 8005dae <__libc_init_array+0x2e> 8005da2: bd70 pop {r4, r5, r6, pc} 8005da4: f856 3025 ldr.w r3, [r6, r5, lsl #2] 8005da8: 4798 blx r3 8005daa: 3501 adds r5, #1 8005dac: e7ee b.n 8005d8c <__libc_init_array+0xc> 8005dae: f856 3025 ldr.w r3, [r6, r5, lsl #2] 8005db2: 4798 blx r3 8005db4: 3501 adds r5, #1 8005db6: e7f2 b.n 8005d9e <__libc_init_array+0x1e> 8005db8: 08008c68 .word 0x08008c68 8005dbc: 08008c68 .word 0x08008c68 8005dc0: 08008c68 .word 0x08008c68 8005dc4: 08008c6c .word 0x08008c6c 08005dc8 : 8005dc8: 4603 mov r3, r0 8005dca: 4402 add r2, r0 8005dcc: 4293 cmp r3, r2 8005dce: d100 bne.n 8005dd2 8005dd0: 4770 bx lr 8005dd2: f803 1b01 strb.w r1, [r3], #1 8005dd6: e7f9 b.n 8005dcc 08005dd8 <__cvt>: 8005dd8: 2b00 cmp r3, #0 8005dda: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8005dde: 461e mov r6, r3 8005de0: bfbb ittet lt 8005de2: f103 4300 addlt.w r3, r3, #2147483648 ; 0x80000000 8005de6: 461e movlt r6, r3 8005de8: 2300 movge r3, #0 8005dea: 232d movlt r3, #45 ; 0x2d 8005dec: b088 sub sp, #32 8005dee: 9f14 ldr r7, [sp, #80] ; 0x50 8005df0: e9dd 1a12 ldrd r1, sl, [sp, #72] ; 0x48 8005df4: f027 0720 bic.w r7, r7, #32 8005df8: 2f46 cmp r7, #70 ; 0x46 8005dfa: 4614 mov r4, r2 8005dfc: 9d10 ldr r5, [sp, #64] ; 0x40 8005dfe: 700b strb r3, [r1, #0] 8005e00: d004 beq.n 8005e0c <__cvt+0x34> 8005e02: 2f45 cmp r7, #69 ; 0x45 8005e04: d100 bne.n 8005e08 <__cvt+0x30> 8005e06: 3501 adds r5, #1 8005e08: 2302 movs r3, #2 8005e0a: e000 b.n 8005e0e <__cvt+0x36> 8005e0c: 2303 movs r3, #3 8005e0e: aa07 add r2, sp, #28 8005e10: 9204 str r2, [sp, #16] 8005e12: aa06 add r2, sp, #24 8005e14: e9cd a202 strd sl, r2, [sp, #8] 8005e18: e9cd 3500 strd r3, r5, [sp] 8005e1c: 4622 mov r2, r4 8005e1e: 4633 mov r3, r6 8005e20: f000 feaa bl 8006b78 <_dtoa_r> 8005e24: 2f47 cmp r7, #71 ; 0x47 8005e26: 4680 mov r8, r0 8005e28: d102 bne.n 8005e30 <__cvt+0x58> 8005e2a: 9b11 ldr r3, [sp, #68] ; 0x44 8005e2c: 07db lsls r3, r3, #31 8005e2e: d526 bpl.n 8005e7e <__cvt+0xa6> 8005e30: 2f46 cmp r7, #70 ; 0x46 8005e32: eb08 0905 add.w r9, r8, r5 8005e36: d111 bne.n 8005e5c <__cvt+0x84> 8005e38: f898 3000 ldrb.w r3, [r8] 8005e3c: 2b30 cmp r3, #48 ; 0x30 8005e3e: d10a bne.n 8005e56 <__cvt+0x7e> 8005e40: 2200 movs r2, #0 8005e42: 2300 movs r3, #0 8005e44: 4620 mov r0, r4 8005e46: 4631 mov r1, r6 8005e48: f7fa fe0e bl 8000a68 <__aeabi_dcmpeq> 8005e4c: b918 cbnz r0, 8005e56 <__cvt+0x7e> 8005e4e: f1c5 0501 rsb r5, r5, #1 8005e52: f8ca 5000 str.w r5, [sl] 8005e56: f8da 3000 ldr.w r3, [sl] 8005e5a: 4499 add r9, r3 8005e5c: 2200 movs r2, #0 8005e5e: 2300 movs r3, #0 8005e60: 4620 mov r0, r4 8005e62: 4631 mov r1, r6 8005e64: f7fa fe00 bl 8000a68 <__aeabi_dcmpeq> 8005e68: b938 cbnz r0, 8005e7a <__cvt+0xa2> 8005e6a: 2230 movs r2, #48 ; 0x30 8005e6c: 9b07 ldr r3, [sp, #28] 8005e6e: 454b cmp r3, r9 8005e70: d205 bcs.n 8005e7e <__cvt+0xa6> 8005e72: 1c59 adds r1, r3, #1 8005e74: 9107 str r1, [sp, #28] 8005e76: 701a strb r2, [r3, #0] 8005e78: e7f8 b.n 8005e6c <__cvt+0x94> 8005e7a: f8cd 901c str.w r9, [sp, #28] 8005e7e: 4640 mov r0, r8 8005e80: 9b07 ldr r3, [sp, #28] 8005e82: 9a15 ldr r2, [sp, #84] ; 0x54 8005e84: eba3 0308 sub.w r3, r3, r8 8005e88: 6013 str r3, [r2, #0] 8005e8a: b008 add sp, #32 8005e8c: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 08005e90 <__exponent>: 8005e90: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} 8005e92: 2900 cmp r1, #0 8005e94: bfb4 ite lt 8005e96: 232d movlt r3, #45 ; 0x2d 8005e98: 232b movge r3, #43 ; 0x2b 8005e9a: 4604 mov r4, r0 8005e9c: bfb8 it lt 8005e9e: 4249 neglt r1, r1 8005ea0: 2909 cmp r1, #9 8005ea2: f804 2b02 strb.w r2, [r4], #2 8005ea6: 7043 strb r3, [r0, #1] 8005ea8: dd21 ble.n 8005eee <__exponent+0x5e> 8005eaa: f10d 0307 add.w r3, sp, #7 8005eae: 461f mov r7, r3 8005eb0: 260a movs r6, #10 8005eb2: fb91 f5f6 sdiv r5, r1, r6 8005eb6: fb06 1115 mls r1, r6, r5, r1 8005eba: 2d09 cmp r5, #9 8005ebc: f101 0130 add.w r1, r1, #48 ; 0x30 8005ec0: f803 1c01 strb.w r1, [r3, #-1] 8005ec4: f103 32ff add.w r2, r3, #4294967295 8005ec8: 4629 mov r1, r5 8005eca: dc09 bgt.n 8005ee0 <__exponent+0x50> 8005ecc: 3130 adds r1, #48 ; 0x30 8005ece: 3b02 subs r3, #2 8005ed0: f802 1c01 strb.w r1, [r2, #-1] 8005ed4: 42bb cmp r3, r7 8005ed6: 4622 mov r2, r4 8005ed8: d304 bcc.n 8005ee4 <__exponent+0x54> 8005eda: 1a10 subs r0, r2, r0 8005edc: b003 add sp, #12 8005ede: bdf0 pop {r4, r5, r6, r7, pc} 8005ee0: 4613 mov r3, r2 8005ee2: e7e6 b.n 8005eb2 <__exponent+0x22> 8005ee4: f813 2b01 ldrb.w r2, [r3], #1 8005ee8: f804 2b01 strb.w r2, [r4], #1 8005eec: e7f2 b.n 8005ed4 <__exponent+0x44> 8005eee: 2330 movs r3, #48 ; 0x30 8005ef0: 4419 add r1, r3 8005ef2: 7083 strb r3, [r0, #2] 8005ef4: 1d02 adds r2, r0, #4 8005ef6: 70c1 strb r1, [r0, #3] 8005ef8: e7ef b.n 8005eda <__exponent+0x4a> ... 08005efc <_printf_float>: 8005efc: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8005f00: b091 sub sp, #68 ; 0x44 8005f02: 460c mov r4, r1 8005f04: 9f1a ldr r7, [sp, #104] ; 0x68 8005f06: 4693 mov fp, r2 8005f08: 461e mov r6, r3 8005f0a: 4605 mov r5, r0 8005f0c: f001 fd62 bl 80079d4 <_localeconv_r> 8005f10: 6803 ldr r3, [r0, #0] 8005f12: 4618 mov r0, r3 8005f14: 9309 str r3, [sp, #36] ; 0x24 8005f16: f7fa f97b bl 8000210 8005f1a: 2300 movs r3, #0 8005f1c: 930e str r3, [sp, #56] ; 0x38 8005f1e: 683b ldr r3, [r7, #0] 8005f20: 900a str r0, [sp, #40] ; 0x28 8005f22: 3307 adds r3, #7 8005f24: f023 0307 bic.w r3, r3, #7 8005f28: f103 0208 add.w r2, r3, #8 8005f2c: f894 8018 ldrb.w r8, [r4, #24] 8005f30: f8d4 a000 ldr.w sl, [r4] 8005f34: 603a str r2, [r7, #0] 8005f36: e9d3 2300 ldrd r2, r3, [r3] 8005f3a: e9c4 2312 strd r2, r3, [r4, #72] ; 0x48 8005f3e: e9d4 7912 ldrd r7, r9, [r4, #72] ; 0x48 8005f42: f029 4300 bic.w r3, r9, #2147483648 ; 0x80000000 8005f46: 930b str r3, [sp, #44] ; 0x2c 8005f48: f04f 32ff mov.w r2, #4294967295 8005f4c: 4ba6 ldr r3, [pc, #664] ; (80061e8 <_printf_float+0x2ec>) 8005f4e: 4638 mov r0, r7 8005f50: 990b ldr r1, [sp, #44] ; 0x2c 8005f52: f7fa fdbb bl 8000acc <__aeabi_dcmpun> 8005f56: bb68 cbnz r0, 8005fb4 <_printf_float+0xb8> 8005f58: f04f 32ff mov.w r2, #4294967295 8005f5c: 4ba2 ldr r3, [pc, #648] ; (80061e8 <_printf_float+0x2ec>) 8005f5e: 4638 mov r0, r7 8005f60: 990b ldr r1, [sp, #44] ; 0x2c 8005f62: f7fa fd95 bl 8000a90 <__aeabi_dcmple> 8005f66: bb28 cbnz r0, 8005fb4 <_printf_float+0xb8> 8005f68: 2200 movs r2, #0 8005f6a: 2300 movs r3, #0 8005f6c: 4638 mov r0, r7 8005f6e: 4649 mov r1, r9 8005f70: f7fa fd84 bl 8000a7c <__aeabi_dcmplt> 8005f74: b110 cbz r0, 8005f7c <_printf_float+0x80> 8005f76: 232d movs r3, #45 ; 0x2d 8005f78: f884 3043 strb.w r3, [r4, #67] ; 0x43 8005f7c: 4f9b ldr r7, [pc, #620] ; (80061ec <_printf_float+0x2f0>) 8005f7e: 4b9c ldr r3, [pc, #624] ; (80061f0 <_printf_float+0x2f4>) 8005f80: f1b8 0f47 cmp.w r8, #71 ; 0x47 8005f84: bf98 it ls 8005f86: 461f movls r7, r3 8005f88: 2303 movs r3, #3 8005f8a: f04f 0900 mov.w r9, #0 8005f8e: 6123 str r3, [r4, #16] 8005f90: f02a 0304 bic.w r3, sl, #4 8005f94: 6023 str r3, [r4, #0] 8005f96: 9600 str r6, [sp, #0] 8005f98: 465b mov r3, fp 8005f9a: aa0f add r2, sp, #60 ; 0x3c 8005f9c: 4621 mov r1, r4 8005f9e: 4628 mov r0, r5 8005fa0: f000 f9e2 bl 8006368 <_printf_common> 8005fa4: 3001 adds r0, #1 8005fa6: f040 8090 bne.w 80060ca <_printf_float+0x1ce> 8005faa: f04f 30ff mov.w r0, #4294967295 8005fae: b011 add sp, #68 ; 0x44 8005fb0: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8005fb4: 463a mov r2, r7 8005fb6: 464b mov r3, r9 8005fb8: 4638 mov r0, r7 8005fba: 4649 mov r1, r9 8005fbc: f7fa fd86 bl 8000acc <__aeabi_dcmpun> 8005fc0: b110 cbz r0, 8005fc8 <_printf_float+0xcc> 8005fc2: 4f8c ldr r7, [pc, #560] ; (80061f4 <_printf_float+0x2f8>) 8005fc4: 4b8c ldr r3, [pc, #560] ; (80061f8 <_printf_float+0x2fc>) 8005fc6: e7db b.n 8005f80 <_printf_float+0x84> 8005fc8: 6863 ldr r3, [r4, #4] 8005fca: f44a 6280 orr.w r2, sl, #1024 ; 0x400 8005fce: 1c59 adds r1, r3, #1 8005fd0: a80d add r0, sp, #52 ; 0x34 8005fd2: a90e add r1, sp, #56 ; 0x38 8005fd4: d140 bne.n 8006058 <_printf_float+0x15c> 8005fd6: 2306 movs r3, #6 8005fd8: 6063 str r3, [r4, #4] 8005fda: f04f 0c00 mov.w ip, #0 8005fde: f10d 0333 add.w r3, sp, #51 ; 0x33 8005fe2: e9cd 2301 strd r2, r3, [sp, #4] 8005fe6: 6863 ldr r3, [r4, #4] 8005fe8: 6022 str r2, [r4, #0] 8005fea: e9cd 0803 strd r0, r8, [sp, #12] 8005fee: 9300 str r3, [sp, #0] 8005ff0: 463a mov r2, r7 8005ff2: 464b mov r3, r9 8005ff4: e9cd 1c05 strd r1, ip, [sp, #20] 8005ff8: 4628 mov r0, r5 8005ffa: f7ff feed bl 8005dd8 <__cvt> 8005ffe: f008 03df and.w r3, r8, #223 ; 0xdf 8006002: 2b47 cmp r3, #71 ; 0x47 8006004: 4607 mov r7, r0 8006006: d109 bne.n 800601c <_printf_float+0x120> 8006008: 9b0d ldr r3, [sp, #52] ; 0x34 800600a: 1cd8 adds r0, r3, #3 800600c: db02 blt.n 8006014 <_printf_float+0x118> 800600e: 6862 ldr r2, [r4, #4] 8006010: 4293 cmp r3, r2 8006012: dd47 ble.n 80060a4 <_printf_float+0x1a8> 8006014: f1a8 0802 sub.w r8, r8, #2 8006018: fa5f f888 uxtb.w r8, r8 800601c: f1b8 0f65 cmp.w r8, #101 ; 0x65 8006020: 990d ldr r1, [sp, #52] ; 0x34 8006022: d824 bhi.n 800606e <_printf_float+0x172> 8006024: 3901 subs r1, #1 8006026: 4642 mov r2, r8 8006028: f104 0050 add.w r0, r4, #80 ; 0x50 800602c: 910d str r1, [sp, #52] ; 0x34 800602e: f7ff ff2f bl 8005e90 <__exponent> 8006032: 9a0e ldr r2, [sp, #56] ; 0x38 8006034: 4681 mov r9, r0 8006036: 1813 adds r3, r2, r0 8006038: 2a01 cmp r2, #1 800603a: 6123 str r3, [r4, #16] 800603c: dc02 bgt.n 8006044 <_printf_float+0x148> 800603e: 6822 ldr r2, [r4, #0] 8006040: 07d1 lsls r1, r2, #31 8006042: d501 bpl.n 8006048 <_printf_float+0x14c> 8006044: 3301 adds r3, #1 8006046: 6123 str r3, [r4, #16] 8006048: f89d 3033 ldrb.w r3, [sp, #51] ; 0x33 800604c: 2b00 cmp r3, #0 800604e: d0a2 beq.n 8005f96 <_printf_float+0x9a> 8006050: 232d movs r3, #45 ; 0x2d 8006052: f884 3043 strb.w r3, [r4, #67] ; 0x43 8006056: e79e b.n 8005f96 <_printf_float+0x9a> 8006058: f1b8 0f67 cmp.w r8, #103 ; 0x67 800605c: f000 816e beq.w 800633c <_printf_float+0x440> 8006060: f1b8 0f47 cmp.w r8, #71 ; 0x47 8006064: d1b9 bne.n 8005fda <_printf_float+0xde> 8006066: 2b00 cmp r3, #0 8006068: d1b7 bne.n 8005fda <_printf_float+0xde> 800606a: 2301 movs r3, #1 800606c: e7b4 b.n 8005fd8 <_printf_float+0xdc> 800606e: f1b8 0f66 cmp.w r8, #102 ; 0x66 8006072: d119 bne.n 80060a8 <_printf_float+0x1ac> 8006074: 2900 cmp r1, #0 8006076: 6863 ldr r3, [r4, #4] 8006078: dd0c ble.n 8006094 <_printf_float+0x198> 800607a: 6121 str r1, [r4, #16] 800607c: b913 cbnz r3, 8006084 <_printf_float+0x188> 800607e: 6822 ldr r2, [r4, #0] 8006080: 07d2 lsls r2, r2, #31 8006082: d502 bpl.n 800608a <_printf_float+0x18e> 8006084: 3301 adds r3, #1 8006086: 440b add r3, r1 8006088: 6123 str r3, [r4, #16] 800608a: 9b0d ldr r3, [sp, #52] ; 0x34 800608c: f04f 0900 mov.w r9, #0 8006090: 65a3 str r3, [r4, #88] ; 0x58 8006092: e7d9 b.n 8006048 <_printf_float+0x14c> 8006094: b913 cbnz r3, 800609c <_printf_float+0x1a0> 8006096: 6822 ldr r2, [r4, #0] 8006098: 07d0 lsls r0, r2, #31 800609a: d501 bpl.n 80060a0 <_printf_float+0x1a4> 800609c: 3302 adds r3, #2 800609e: e7f3 b.n 8006088 <_printf_float+0x18c> 80060a0: 2301 movs r3, #1 80060a2: e7f1 b.n 8006088 <_printf_float+0x18c> 80060a4: f04f 0867 mov.w r8, #103 ; 0x67 80060a8: e9dd 320d ldrd r3, r2, [sp, #52] ; 0x34 80060ac: 4293 cmp r3, r2 80060ae: db05 blt.n 80060bc <_printf_float+0x1c0> 80060b0: 6822 ldr r2, [r4, #0] 80060b2: 6123 str r3, [r4, #16] 80060b4: 07d1 lsls r1, r2, #31 80060b6: d5e8 bpl.n 800608a <_printf_float+0x18e> 80060b8: 3301 adds r3, #1 80060ba: e7e5 b.n 8006088 <_printf_float+0x18c> 80060bc: 2b00 cmp r3, #0 80060be: bfcc ite gt 80060c0: 2301 movgt r3, #1 80060c2: f1c3 0302 rsble r3, r3, #2 80060c6: 4413 add r3, r2 80060c8: e7de b.n 8006088 <_printf_float+0x18c> 80060ca: 6823 ldr r3, [r4, #0] 80060cc: 055a lsls r2, r3, #21 80060ce: d407 bmi.n 80060e0 <_printf_float+0x1e4> 80060d0: 6923 ldr r3, [r4, #16] 80060d2: 463a mov r2, r7 80060d4: 4659 mov r1, fp 80060d6: 4628 mov r0, r5 80060d8: 47b0 blx r6 80060da: 3001 adds r0, #1 80060dc: d129 bne.n 8006132 <_printf_float+0x236> 80060de: e764 b.n 8005faa <_printf_float+0xae> 80060e0: f1b8 0f65 cmp.w r8, #101 ; 0x65 80060e4: f240 80d7 bls.w 8006296 <_printf_float+0x39a> 80060e8: e9d4 0112 ldrd r0, r1, [r4, #72] ; 0x48 80060ec: 2200 movs r2, #0 80060ee: 2300 movs r3, #0 80060f0: f7fa fcba bl 8000a68 <__aeabi_dcmpeq> 80060f4: b388 cbz r0, 800615a <_printf_float+0x25e> 80060f6: 2301 movs r3, #1 80060f8: 4a40 ldr r2, [pc, #256] ; (80061fc <_printf_float+0x300>) 80060fa: 4659 mov r1, fp 80060fc: 4628 mov r0, r5 80060fe: 47b0 blx r6 8006100: 3001 adds r0, #1 8006102: f43f af52 beq.w 8005faa <_printf_float+0xae> 8006106: e9dd 230d ldrd r2, r3, [sp, #52] ; 0x34 800610a: 429a cmp r2, r3 800610c: db02 blt.n 8006114 <_printf_float+0x218> 800610e: 6823 ldr r3, [r4, #0] 8006110: 07d8 lsls r0, r3, #31 8006112: d50e bpl.n 8006132 <_printf_float+0x236> 8006114: e9dd 2309 ldrd r2, r3, [sp, #36] ; 0x24 8006118: 4659 mov r1, fp 800611a: 4628 mov r0, r5 800611c: 47b0 blx r6 800611e: 3001 adds r0, #1 8006120: f43f af43 beq.w 8005faa <_printf_float+0xae> 8006124: 2700 movs r7, #0 8006126: f104 081a add.w r8, r4, #26 800612a: 9b0e ldr r3, [sp, #56] ; 0x38 800612c: 3b01 subs r3, #1 800612e: 42bb cmp r3, r7 8006130: dc09 bgt.n 8006146 <_printf_float+0x24a> 8006132: 6823 ldr r3, [r4, #0] 8006134: 079f lsls r7, r3, #30 8006136: f100 80fd bmi.w 8006334 <_printf_float+0x438> 800613a: 68e0 ldr r0, [r4, #12] 800613c: 9b0f ldr r3, [sp, #60] ; 0x3c 800613e: 4298 cmp r0, r3 8006140: bfb8 it lt 8006142: 4618 movlt r0, r3 8006144: e733 b.n 8005fae <_printf_float+0xb2> 8006146: 2301 movs r3, #1 8006148: 4642 mov r2, r8 800614a: 4659 mov r1, fp 800614c: 4628 mov r0, r5 800614e: 47b0 blx r6 8006150: 3001 adds r0, #1 8006152: f43f af2a beq.w 8005faa <_printf_float+0xae> 8006156: 3701 adds r7, #1 8006158: e7e7 b.n 800612a <_printf_float+0x22e> 800615a: 9b0d ldr r3, [sp, #52] ; 0x34 800615c: 2b00 cmp r3, #0 800615e: dc2b bgt.n 80061b8 <_printf_float+0x2bc> 8006160: 2301 movs r3, #1 8006162: 4a26 ldr r2, [pc, #152] ; (80061fc <_printf_float+0x300>) 8006164: 4659 mov r1, fp 8006166: 4628 mov r0, r5 8006168: 47b0 blx r6 800616a: 3001 adds r0, #1 800616c: f43f af1d beq.w 8005faa <_printf_float+0xae> 8006170: 9b0d ldr r3, [sp, #52] ; 0x34 8006172: b923 cbnz r3, 800617e <_printf_float+0x282> 8006174: 9b0e ldr r3, [sp, #56] ; 0x38 8006176: b913 cbnz r3, 800617e <_printf_float+0x282> 8006178: 6823 ldr r3, [r4, #0] 800617a: 07d9 lsls r1, r3, #31 800617c: d5d9 bpl.n 8006132 <_printf_float+0x236> 800617e: e9dd 2309 ldrd r2, r3, [sp, #36] ; 0x24 8006182: 4659 mov r1, fp 8006184: 4628 mov r0, r5 8006186: 47b0 blx r6 8006188: 3001 adds r0, #1 800618a: f43f af0e beq.w 8005faa <_printf_float+0xae> 800618e: f04f 0800 mov.w r8, #0 8006192: f104 091a add.w r9, r4, #26 8006196: 9b0d ldr r3, [sp, #52] ; 0x34 8006198: 425b negs r3, r3 800619a: 4543 cmp r3, r8 800619c: dc01 bgt.n 80061a2 <_printf_float+0x2a6> 800619e: 9b0e ldr r3, [sp, #56] ; 0x38 80061a0: e797 b.n 80060d2 <_printf_float+0x1d6> 80061a2: 2301 movs r3, #1 80061a4: 464a mov r2, r9 80061a6: 4659 mov r1, fp 80061a8: 4628 mov r0, r5 80061aa: 47b0 blx r6 80061ac: 3001 adds r0, #1 80061ae: f43f aefc beq.w 8005faa <_printf_float+0xae> 80061b2: f108 0801 add.w r8, r8, #1 80061b6: e7ee b.n 8006196 <_printf_float+0x29a> 80061b8: 9a0e ldr r2, [sp, #56] ; 0x38 80061ba: 6da3 ldr r3, [r4, #88] ; 0x58 80061bc: 429a cmp r2, r3 80061be: bfa8 it ge 80061c0: 461a movge r2, r3 80061c2: 2a00 cmp r2, #0 80061c4: 4690 mov r8, r2 80061c6: dd07 ble.n 80061d8 <_printf_float+0x2dc> 80061c8: 4613 mov r3, r2 80061ca: 4659 mov r1, fp 80061cc: 463a mov r2, r7 80061ce: 4628 mov r0, r5 80061d0: 47b0 blx r6 80061d2: 3001 adds r0, #1 80061d4: f43f aee9 beq.w 8005faa <_printf_float+0xae> 80061d8: f104 031a add.w r3, r4, #26 80061dc: f04f 0a00 mov.w sl, #0 80061e0: ea28 78e8 bic.w r8, r8, r8, asr #31 80061e4: 930b str r3, [sp, #44] ; 0x2c 80061e6: e015 b.n 8006214 <_printf_float+0x318> 80061e8: 7fefffff .word 0x7fefffff 80061ec: 080089b0 .word 0x080089b0 80061f0: 080089ac .word 0x080089ac 80061f4: 080089b8 .word 0x080089b8 80061f8: 080089b4 .word 0x080089b4 80061fc: 080089bc .word 0x080089bc 8006200: 2301 movs r3, #1 8006202: 9a0b ldr r2, [sp, #44] ; 0x2c 8006204: 4659 mov r1, fp 8006206: 4628 mov r0, r5 8006208: 47b0 blx r6 800620a: 3001 adds r0, #1 800620c: f43f aecd beq.w 8005faa <_printf_float+0xae> 8006210: f10a 0a01 add.w sl, sl, #1 8006214: f8d4 9058 ldr.w r9, [r4, #88] ; 0x58 8006218: eba9 0308 sub.w r3, r9, r8 800621c: 4553 cmp r3, sl 800621e: dcef bgt.n 8006200 <_printf_float+0x304> 8006220: e9dd 230d ldrd r2, r3, [sp, #52] ; 0x34 8006224: 429a cmp r2, r3 8006226: 444f add r7, r9 8006228: db14 blt.n 8006254 <_printf_float+0x358> 800622a: 6823 ldr r3, [r4, #0] 800622c: 07da lsls r2, r3, #31 800622e: d411 bmi.n 8006254 <_printf_float+0x358> 8006230: 9b0e ldr r3, [sp, #56] ; 0x38 8006232: 990d ldr r1, [sp, #52] ; 0x34 8006234: eba3 0209 sub.w r2, r3, r9 8006238: eba3 0901 sub.w r9, r3, r1 800623c: 4591 cmp r9, r2 800623e: bfa8 it ge 8006240: 4691 movge r9, r2 8006242: f1b9 0f00 cmp.w r9, #0 8006246: dc0d bgt.n 8006264 <_printf_float+0x368> 8006248: 2700 movs r7, #0 800624a: ea29 79e9 bic.w r9, r9, r9, asr #31 800624e: f104 081a add.w r8, r4, #26 8006252: e018 b.n 8006286 <_printf_float+0x38a> 8006254: e9dd 2309 ldrd r2, r3, [sp, #36] ; 0x24 8006258: 4659 mov r1, fp 800625a: 4628 mov r0, r5 800625c: 47b0 blx r6 800625e: 3001 adds r0, #1 8006260: d1e6 bne.n 8006230 <_printf_float+0x334> 8006262: e6a2 b.n 8005faa <_printf_float+0xae> 8006264: 464b mov r3, r9 8006266: 463a mov r2, r7 8006268: 4659 mov r1, fp 800626a: 4628 mov r0, r5 800626c: 47b0 blx r6 800626e: 3001 adds r0, #1 8006270: d1ea bne.n 8006248 <_printf_float+0x34c> 8006272: e69a b.n 8005faa <_printf_float+0xae> 8006274: 2301 movs r3, #1 8006276: 4642 mov r2, r8 8006278: 4659 mov r1, fp 800627a: 4628 mov r0, r5 800627c: 47b0 blx r6 800627e: 3001 adds r0, #1 8006280: f43f ae93 beq.w 8005faa <_printf_float+0xae> 8006284: 3701 adds r7, #1 8006286: e9dd 230d ldrd r2, r3, [sp, #52] ; 0x34 800628a: 1a9b subs r3, r3, r2 800628c: eba3 0309 sub.w r3, r3, r9 8006290: 42bb cmp r3, r7 8006292: dcef bgt.n 8006274 <_printf_float+0x378> 8006294: e74d b.n 8006132 <_printf_float+0x236> 8006296: 9a0e ldr r2, [sp, #56] ; 0x38 8006298: 2a01 cmp r2, #1 800629a: dc01 bgt.n 80062a0 <_printf_float+0x3a4> 800629c: 07db lsls r3, r3, #31 800629e: d538 bpl.n 8006312 <_printf_float+0x416> 80062a0: 2301 movs r3, #1 80062a2: 463a mov r2, r7 80062a4: 4659 mov r1, fp 80062a6: 4628 mov r0, r5 80062a8: 47b0 blx r6 80062aa: 3001 adds r0, #1 80062ac: f43f ae7d beq.w 8005faa <_printf_float+0xae> 80062b0: e9dd 2309 ldrd r2, r3, [sp, #36] ; 0x24 80062b4: 4659 mov r1, fp 80062b6: 4628 mov r0, r5 80062b8: 47b0 blx r6 80062ba: 3001 adds r0, #1 80062bc: f107 0701 add.w r7, r7, #1 80062c0: f43f ae73 beq.w 8005faa <_printf_float+0xae> 80062c4: e9d4 0112 ldrd r0, r1, [r4, #72] ; 0x48 80062c8: 9b0e ldr r3, [sp, #56] ; 0x38 80062ca: 2200 movs r2, #0 80062cc: f103 38ff add.w r8, r3, #4294967295 80062d0: 2300 movs r3, #0 80062d2: f7fa fbc9 bl 8000a68 <__aeabi_dcmpeq> 80062d6: b9c0 cbnz r0, 800630a <_printf_float+0x40e> 80062d8: 4643 mov r3, r8 80062da: 463a mov r2, r7 80062dc: 4659 mov r1, fp 80062de: 4628 mov r0, r5 80062e0: 47b0 blx r6 80062e2: 3001 adds r0, #1 80062e4: d10d bne.n 8006302 <_printf_float+0x406> 80062e6: e660 b.n 8005faa <_printf_float+0xae> 80062e8: 2301 movs r3, #1 80062ea: 4642 mov r2, r8 80062ec: 4659 mov r1, fp 80062ee: 4628 mov r0, r5 80062f0: 47b0 blx r6 80062f2: 3001 adds r0, #1 80062f4: f43f ae59 beq.w 8005faa <_printf_float+0xae> 80062f8: 3701 adds r7, #1 80062fa: 9b0e ldr r3, [sp, #56] ; 0x38 80062fc: 3b01 subs r3, #1 80062fe: 42bb cmp r3, r7 8006300: dcf2 bgt.n 80062e8 <_printf_float+0x3ec> 8006302: 464b mov r3, r9 8006304: f104 0250 add.w r2, r4, #80 ; 0x50 8006308: e6e4 b.n 80060d4 <_printf_float+0x1d8> 800630a: 2700 movs r7, #0 800630c: f104 081a add.w r8, r4, #26 8006310: e7f3 b.n 80062fa <_printf_float+0x3fe> 8006312: 2301 movs r3, #1 8006314: e7e1 b.n 80062da <_printf_float+0x3de> 8006316: 2301 movs r3, #1 8006318: 4642 mov r2, r8 800631a: 4659 mov r1, fp 800631c: 4628 mov r0, r5 800631e: 47b0 blx r6 8006320: 3001 adds r0, #1 8006322: f43f ae42 beq.w 8005faa <_printf_float+0xae> 8006326: 3701 adds r7, #1 8006328: 68e3 ldr r3, [r4, #12] 800632a: 9a0f ldr r2, [sp, #60] ; 0x3c 800632c: 1a9b subs r3, r3, r2 800632e: 42bb cmp r3, r7 8006330: dcf1 bgt.n 8006316 <_printf_float+0x41a> 8006332: e702 b.n 800613a <_printf_float+0x23e> 8006334: 2700 movs r7, #0 8006336: f104 0819 add.w r8, r4, #25 800633a: e7f5 b.n 8006328 <_printf_float+0x42c> 800633c: 2b00 cmp r3, #0 800633e: f43f ae94 beq.w 800606a <_printf_float+0x16e> 8006342: f04f 0c00 mov.w ip, #0 8006346: e9cd 1c05 strd r1, ip, [sp, #20] 800634a: f10d 0133 add.w r1, sp, #51 ; 0x33 800634e: 6022 str r2, [r4, #0] 8006350: e9cd 0803 strd r0, r8, [sp, #12] 8006354: e9cd 2101 strd r2, r1, [sp, #4] 8006358: 9300 str r3, [sp, #0] 800635a: 463a mov r2, r7 800635c: 464b mov r3, r9 800635e: 4628 mov r0, r5 8006360: f7ff fd3a bl 8005dd8 <__cvt> 8006364: 4607 mov r7, r0 8006366: e64f b.n 8006008 <_printf_float+0x10c> 08006368 <_printf_common>: 8006368: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 800636c: 4691 mov r9, r2 800636e: 461f mov r7, r3 8006370: 688a ldr r2, [r1, #8] 8006372: 690b ldr r3, [r1, #16] 8006374: 4606 mov r6, r0 8006376: 4293 cmp r3, r2 8006378: bfb8 it lt 800637a: 4613 movlt r3, r2 800637c: f8c9 3000 str.w r3, [r9] 8006380: f891 2043 ldrb.w r2, [r1, #67] ; 0x43 8006384: 460c mov r4, r1 8006386: f8dd 8020 ldr.w r8, [sp, #32] 800638a: b112 cbz r2, 8006392 <_printf_common+0x2a> 800638c: 3301 adds r3, #1 800638e: f8c9 3000 str.w r3, [r9] 8006392: 6823 ldr r3, [r4, #0] 8006394: 0699 lsls r1, r3, #26 8006396: bf42 ittt mi 8006398: f8d9 3000 ldrmi.w r3, [r9] 800639c: 3302 addmi r3, #2 800639e: f8c9 3000 strmi.w r3, [r9] 80063a2: 6825 ldr r5, [r4, #0] 80063a4: f015 0506 ands.w r5, r5, #6 80063a8: d107 bne.n 80063ba <_printf_common+0x52> 80063aa: f104 0a19 add.w sl, r4, #25 80063ae: 68e3 ldr r3, [r4, #12] 80063b0: f8d9 2000 ldr.w r2, [r9] 80063b4: 1a9b subs r3, r3, r2 80063b6: 42ab cmp r3, r5 80063b8: dc29 bgt.n 800640e <_printf_common+0xa6> 80063ba: f894 3043 ldrb.w r3, [r4, #67] ; 0x43 80063be: 6822 ldr r2, [r4, #0] 80063c0: 3300 adds r3, #0 80063c2: bf18 it ne 80063c4: 2301 movne r3, #1 80063c6: 0692 lsls r2, r2, #26 80063c8: d42e bmi.n 8006428 <_printf_common+0xc0> 80063ca: f104 0243 add.w r2, r4, #67 ; 0x43 80063ce: 4639 mov r1, r7 80063d0: 4630 mov r0, r6 80063d2: 47c0 blx r8 80063d4: 3001 adds r0, #1 80063d6: d021 beq.n 800641c <_printf_common+0xb4> 80063d8: 6823 ldr r3, [r4, #0] 80063da: 68e5 ldr r5, [r4, #12] 80063dc: f003 0306 and.w r3, r3, #6 80063e0: 2b04 cmp r3, #4 80063e2: bf18 it ne 80063e4: 2500 movne r5, #0 80063e6: f8d9 2000 ldr.w r2, [r9] 80063ea: f04f 0900 mov.w r9, #0 80063ee: bf08 it eq 80063f0: 1aad subeq r5, r5, r2 80063f2: 68a3 ldr r3, [r4, #8] 80063f4: 6922 ldr r2, [r4, #16] 80063f6: bf08 it eq 80063f8: ea25 75e5 biceq.w r5, r5, r5, asr #31 80063fc: 4293 cmp r3, r2 80063fe: bfc4 itt gt 8006400: 1a9b subgt r3, r3, r2 8006402: 18ed addgt r5, r5, r3 8006404: 341a adds r4, #26 8006406: 454d cmp r5, r9 8006408: d11a bne.n 8006440 <_printf_common+0xd8> 800640a: 2000 movs r0, #0 800640c: e008 b.n 8006420 <_printf_common+0xb8> 800640e: 2301 movs r3, #1 8006410: 4652 mov r2, sl 8006412: 4639 mov r1, r7 8006414: 4630 mov r0, r6 8006416: 47c0 blx r8 8006418: 3001 adds r0, #1 800641a: d103 bne.n 8006424 <_printf_common+0xbc> 800641c: f04f 30ff mov.w r0, #4294967295 8006420: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8006424: 3501 adds r5, #1 8006426: e7c2 b.n 80063ae <_printf_common+0x46> 8006428: 2030 movs r0, #48 ; 0x30 800642a: 18e1 adds r1, r4, r3 800642c: f881 0043 strb.w r0, [r1, #67] ; 0x43 8006430: 1c5a adds r2, r3, #1 8006432: f894 1045 ldrb.w r1, [r4, #69] ; 0x45 8006436: 4422 add r2, r4 8006438: 3302 adds r3, #2 800643a: f882 1043 strb.w r1, [r2, #67] ; 0x43 800643e: e7c4 b.n 80063ca <_printf_common+0x62> 8006440: 2301 movs r3, #1 8006442: 4622 mov r2, r4 8006444: 4639 mov r1, r7 8006446: 4630 mov r0, r6 8006448: 47c0 blx r8 800644a: 3001 adds r0, #1 800644c: d0e6 beq.n 800641c <_printf_common+0xb4> 800644e: f109 0901 add.w r9, r9, #1 8006452: e7d8 b.n 8006406 <_printf_common+0x9e> 08006454 <_printf_i>: 8006454: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} 8006458: f101 0c43 add.w ip, r1, #67 ; 0x43 800645c: 460c mov r4, r1 800645e: 7e09 ldrb r1, [r1, #24] 8006460: b085 sub sp, #20 8006462: 296e cmp r1, #110 ; 0x6e 8006464: 4617 mov r7, r2 8006466: 4606 mov r6, r0 8006468: 4698 mov r8, r3 800646a: 9a0c ldr r2, [sp, #48] ; 0x30 800646c: f000 80b3 beq.w 80065d6 <_printf_i+0x182> 8006470: d822 bhi.n 80064b8 <_printf_i+0x64> 8006472: 2963 cmp r1, #99 ; 0x63 8006474: d036 beq.n 80064e4 <_printf_i+0x90> 8006476: d80a bhi.n 800648e <_printf_i+0x3a> 8006478: 2900 cmp r1, #0 800647a: f000 80b9 beq.w 80065f0 <_printf_i+0x19c> 800647e: 2958 cmp r1, #88 ; 0x58 8006480: f000 8083 beq.w 800658a <_printf_i+0x136> 8006484: f104 0542 add.w r5, r4, #66 ; 0x42 8006488: f884 1042 strb.w r1, [r4, #66] ; 0x42 800648c: e032 b.n 80064f4 <_printf_i+0xa0> 800648e: 2964 cmp r1, #100 ; 0x64 8006490: d001 beq.n 8006496 <_printf_i+0x42> 8006492: 2969 cmp r1, #105 ; 0x69 8006494: d1f6 bne.n 8006484 <_printf_i+0x30> 8006496: 6820 ldr r0, [r4, #0] 8006498: 6813 ldr r3, [r2, #0] 800649a: 0605 lsls r5, r0, #24 800649c: f103 0104 add.w r1, r3, #4 80064a0: d52a bpl.n 80064f8 <_printf_i+0xa4> 80064a2: 681b ldr r3, [r3, #0] 80064a4: 6011 str r1, [r2, #0] 80064a6: 2b00 cmp r3, #0 80064a8: da03 bge.n 80064b2 <_printf_i+0x5e> 80064aa: 222d movs r2, #45 ; 0x2d 80064ac: 425b negs r3, r3 80064ae: f884 2043 strb.w r2, [r4, #67] ; 0x43 80064b2: 486f ldr r0, [pc, #444] ; (8006670 <_printf_i+0x21c>) 80064b4: 220a movs r2, #10 80064b6: e039 b.n 800652c <_printf_i+0xd8> 80064b8: 2973 cmp r1, #115 ; 0x73 80064ba: f000 809d beq.w 80065f8 <_printf_i+0x1a4> 80064be: d808 bhi.n 80064d2 <_printf_i+0x7e> 80064c0: 296f cmp r1, #111 ; 0x6f 80064c2: d020 beq.n 8006506 <_printf_i+0xb2> 80064c4: 2970 cmp r1, #112 ; 0x70 80064c6: d1dd bne.n 8006484 <_printf_i+0x30> 80064c8: 6823 ldr r3, [r4, #0] 80064ca: f043 0320 orr.w r3, r3, #32 80064ce: 6023 str r3, [r4, #0] 80064d0: e003 b.n 80064da <_printf_i+0x86> 80064d2: 2975 cmp r1, #117 ; 0x75 80064d4: d017 beq.n 8006506 <_printf_i+0xb2> 80064d6: 2978 cmp r1, #120 ; 0x78 80064d8: d1d4 bne.n 8006484 <_printf_i+0x30> 80064da: 2378 movs r3, #120 ; 0x78 80064dc: 4865 ldr r0, [pc, #404] ; (8006674 <_printf_i+0x220>) 80064de: f884 3045 strb.w r3, [r4, #69] ; 0x45 80064e2: e055 b.n 8006590 <_printf_i+0x13c> 80064e4: 6813 ldr r3, [r2, #0] 80064e6: f104 0542 add.w r5, r4, #66 ; 0x42 80064ea: 1d19 adds r1, r3, #4 80064ec: 681b ldr r3, [r3, #0] 80064ee: 6011 str r1, [r2, #0] 80064f0: f884 3042 strb.w r3, [r4, #66] ; 0x42 80064f4: 2301 movs r3, #1 80064f6: e08c b.n 8006612 <_printf_i+0x1be> 80064f8: 681b ldr r3, [r3, #0] 80064fa: f010 0f40 tst.w r0, #64 ; 0x40 80064fe: 6011 str r1, [r2, #0] 8006500: bf18 it ne 8006502: b21b sxthne r3, r3 8006504: e7cf b.n 80064a6 <_printf_i+0x52> 8006506: 6813 ldr r3, [r2, #0] 8006508: 6825 ldr r5, [r4, #0] 800650a: 1d18 adds r0, r3, #4 800650c: 6010 str r0, [r2, #0] 800650e: 0628 lsls r0, r5, #24 8006510: d501 bpl.n 8006516 <_printf_i+0xc2> 8006512: 681b ldr r3, [r3, #0] 8006514: e002 b.n 800651c <_printf_i+0xc8> 8006516: 0668 lsls r0, r5, #25 8006518: d5fb bpl.n 8006512 <_printf_i+0xbe> 800651a: 881b ldrh r3, [r3, #0] 800651c: 296f cmp r1, #111 ; 0x6f 800651e: bf14 ite ne 8006520: 220a movne r2, #10 8006522: 2208 moveq r2, #8 8006524: 4852 ldr r0, [pc, #328] ; (8006670 <_printf_i+0x21c>) 8006526: 2100 movs r1, #0 8006528: f884 1043 strb.w r1, [r4, #67] ; 0x43 800652c: 6865 ldr r5, [r4, #4] 800652e: 2d00 cmp r5, #0 8006530: 60a5 str r5, [r4, #8] 8006532: f2c0 8095 blt.w 8006660 <_printf_i+0x20c> 8006536: 6821 ldr r1, [r4, #0] 8006538: f021 0104 bic.w r1, r1, #4 800653c: 6021 str r1, [r4, #0] 800653e: 2b00 cmp r3, #0 8006540: d13d bne.n 80065be <_printf_i+0x16a> 8006542: 2d00 cmp r5, #0 8006544: f040 808e bne.w 8006664 <_printf_i+0x210> 8006548: 4665 mov r5, ip 800654a: 2a08 cmp r2, #8 800654c: d10b bne.n 8006566 <_printf_i+0x112> 800654e: 6823 ldr r3, [r4, #0] 8006550: 07db lsls r3, r3, #31 8006552: d508 bpl.n 8006566 <_printf_i+0x112> 8006554: 6923 ldr r3, [r4, #16] 8006556: 6862 ldr r2, [r4, #4] 8006558: 429a cmp r2, r3 800655a: bfde ittt le 800655c: 2330 movle r3, #48 ; 0x30 800655e: f805 3c01 strble.w r3, [r5, #-1] 8006562: f105 35ff addle.w r5, r5, #4294967295 8006566: ebac 0305 sub.w r3, ip, r5 800656a: 6123 str r3, [r4, #16] 800656c: f8cd 8000 str.w r8, [sp] 8006570: 463b mov r3, r7 8006572: aa03 add r2, sp, #12 8006574: 4621 mov r1, r4 8006576: 4630 mov r0, r6 8006578: f7ff fef6 bl 8006368 <_printf_common> 800657c: 3001 adds r0, #1 800657e: d14d bne.n 800661c <_printf_i+0x1c8> 8006580: f04f 30ff mov.w r0, #4294967295 8006584: b005 add sp, #20 8006586: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} 800658a: 4839 ldr r0, [pc, #228] ; (8006670 <_printf_i+0x21c>) 800658c: f884 1045 strb.w r1, [r4, #69] ; 0x45 8006590: 6813 ldr r3, [r2, #0] 8006592: 6821 ldr r1, [r4, #0] 8006594: 1d1d adds r5, r3, #4 8006596: 681b ldr r3, [r3, #0] 8006598: 6015 str r5, [r2, #0] 800659a: 060a lsls r2, r1, #24 800659c: d50b bpl.n 80065b6 <_printf_i+0x162> 800659e: 07ca lsls r2, r1, #31 80065a0: bf44 itt mi 80065a2: f041 0120 orrmi.w r1, r1, #32 80065a6: 6021 strmi r1, [r4, #0] 80065a8: b91b cbnz r3, 80065b2 <_printf_i+0x15e> 80065aa: 6822 ldr r2, [r4, #0] 80065ac: f022 0220 bic.w r2, r2, #32 80065b0: 6022 str r2, [r4, #0] 80065b2: 2210 movs r2, #16 80065b4: e7b7 b.n 8006526 <_printf_i+0xd2> 80065b6: 064d lsls r5, r1, #25 80065b8: bf48 it mi 80065ba: b29b uxthmi r3, r3 80065bc: e7ef b.n 800659e <_printf_i+0x14a> 80065be: 4665 mov r5, ip 80065c0: fbb3 f1f2 udiv r1, r3, r2 80065c4: fb02 3311 mls r3, r2, r1, r3 80065c8: 5cc3 ldrb r3, [r0, r3] 80065ca: f805 3d01 strb.w r3, [r5, #-1]! 80065ce: 460b mov r3, r1 80065d0: 2900 cmp r1, #0 80065d2: d1f5 bne.n 80065c0 <_printf_i+0x16c> 80065d4: e7b9 b.n 800654a <_printf_i+0xf6> 80065d6: 6813 ldr r3, [r2, #0] 80065d8: 6825 ldr r5, [r4, #0] 80065da: 1d18 adds r0, r3, #4 80065dc: 6961 ldr r1, [r4, #20] 80065de: 6010 str r0, [r2, #0] 80065e0: 0628 lsls r0, r5, #24 80065e2: 681b ldr r3, [r3, #0] 80065e4: d501 bpl.n 80065ea <_printf_i+0x196> 80065e6: 6019 str r1, [r3, #0] 80065e8: e002 b.n 80065f0 <_printf_i+0x19c> 80065ea: 066a lsls r2, r5, #25 80065ec: d5fb bpl.n 80065e6 <_printf_i+0x192> 80065ee: 8019 strh r1, [r3, #0] 80065f0: 2300 movs r3, #0 80065f2: 4665 mov r5, ip 80065f4: 6123 str r3, [r4, #16] 80065f6: e7b9 b.n 800656c <_printf_i+0x118> 80065f8: 6813 ldr r3, [r2, #0] 80065fa: 1d19 adds r1, r3, #4 80065fc: 6011 str r1, [r2, #0] 80065fe: 681d ldr r5, [r3, #0] 8006600: 6862 ldr r2, [r4, #4] 8006602: 2100 movs r1, #0 8006604: 4628 mov r0, r5 8006606: f001 fa5f bl 8007ac8 800660a: b108 cbz r0, 8006610 <_printf_i+0x1bc> 800660c: 1b40 subs r0, r0, r5 800660e: 6060 str r0, [r4, #4] 8006610: 6863 ldr r3, [r4, #4] 8006612: 6123 str r3, [r4, #16] 8006614: 2300 movs r3, #0 8006616: f884 3043 strb.w r3, [r4, #67] ; 0x43 800661a: e7a7 b.n 800656c <_printf_i+0x118> 800661c: 6923 ldr r3, [r4, #16] 800661e: 462a mov r2, r5 8006620: 4639 mov r1, r7 8006622: 4630 mov r0, r6 8006624: 47c0 blx r8 8006626: 3001 adds r0, #1 8006628: d0aa beq.n 8006580 <_printf_i+0x12c> 800662a: 6823 ldr r3, [r4, #0] 800662c: 079b lsls r3, r3, #30 800662e: d413 bmi.n 8006658 <_printf_i+0x204> 8006630: 68e0 ldr r0, [r4, #12] 8006632: 9b03 ldr r3, [sp, #12] 8006634: 4298 cmp r0, r3 8006636: bfb8 it lt 8006638: 4618 movlt r0, r3 800663a: e7a3 b.n 8006584 <_printf_i+0x130> 800663c: 2301 movs r3, #1 800663e: 464a mov r2, r9 8006640: 4639 mov r1, r7 8006642: 4630 mov r0, r6 8006644: 47c0 blx r8 8006646: 3001 adds r0, #1 8006648: d09a beq.n 8006580 <_printf_i+0x12c> 800664a: 3501 adds r5, #1 800664c: 68e3 ldr r3, [r4, #12] 800664e: 9a03 ldr r2, [sp, #12] 8006650: 1a9b subs r3, r3, r2 8006652: 42ab cmp r3, r5 8006654: dcf2 bgt.n 800663c <_printf_i+0x1e8> 8006656: e7eb b.n 8006630 <_printf_i+0x1dc> 8006658: 2500 movs r5, #0 800665a: f104 0919 add.w r9, r4, #25 800665e: e7f5 b.n 800664c <_printf_i+0x1f8> 8006660: 2b00 cmp r3, #0 8006662: d1ac bne.n 80065be <_printf_i+0x16a> 8006664: 7803 ldrb r3, [r0, #0] 8006666: f104 0542 add.w r5, r4, #66 ; 0x42 800666a: f884 3042 strb.w r3, [r4, #66] ; 0x42 800666e: e76c b.n 800654a <_printf_i+0xf6> 8006670: 080089be .word 0x080089be 8006674: 080089cf .word 0x080089cf 08006678 : 8006678: b40f push {r0, r1, r2, r3} 800667a: 4b0a ldr r3, [pc, #40] ; (80066a4 ) 800667c: b513 push {r0, r1, r4, lr} 800667e: 681c ldr r4, [r3, #0] 8006680: b124 cbz r4, 800668c 8006682: 69a3 ldr r3, [r4, #24] 8006684: b913 cbnz r3, 800668c 8006686: 4620 mov r0, r4 8006688: f001 f91a bl 80078c0 <__sinit> 800668c: ab05 add r3, sp, #20 800668e: 9a04 ldr r2, [sp, #16] 8006690: 68a1 ldr r1, [r4, #8] 8006692: 4620 mov r0, r4 8006694: 9301 str r3, [sp, #4] 8006696: f001 fde9 bl 800826c <_vfiprintf_r> 800669a: b002 add sp, #8 800669c: e8bd 4010 ldmia.w sp!, {r4, lr} 80066a0: b004 add sp, #16 80066a2: 4770 bx lr 80066a4: 2000000c .word 0x2000000c 080066a8 <_puts_r>: 80066a8: b570 push {r4, r5, r6, lr} 80066aa: 460e mov r6, r1 80066ac: 4605 mov r5, r0 80066ae: b118 cbz r0, 80066b8 <_puts_r+0x10> 80066b0: 6983 ldr r3, [r0, #24] 80066b2: b90b cbnz r3, 80066b8 <_puts_r+0x10> 80066b4: f001 f904 bl 80078c0 <__sinit> 80066b8: 69ab ldr r3, [r5, #24] 80066ba: 68ac ldr r4, [r5, #8] 80066bc: b913 cbnz r3, 80066c4 <_puts_r+0x1c> 80066be: 4628 mov r0, r5 80066c0: f001 f8fe bl 80078c0 <__sinit> 80066c4: 4b23 ldr r3, [pc, #140] ; (8006754 <_puts_r+0xac>) 80066c6: 429c cmp r4, r3 80066c8: d117 bne.n 80066fa <_puts_r+0x52> 80066ca: 686c ldr r4, [r5, #4] 80066cc: 89a3 ldrh r3, [r4, #12] 80066ce: 071b lsls r3, r3, #28 80066d0: d51d bpl.n 800670e <_puts_r+0x66> 80066d2: 6923 ldr r3, [r4, #16] 80066d4: b1db cbz r3, 800670e <_puts_r+0x66> 80066d6: 3e01 subs r6, #1 80066d8: 68a3 ldr r3, [r4, #8] 80066da: f816 1f01 ldrb.w r1, [r6, #1]! 80066de: 3b01 subs r3, #1 80066e0: 60a3 str r3, [r4, #8] 80066e2: b9e9 cbnz r1, 8006720 <_puts_r+0x78> 80066e4: 2b00 cmp r3, #0 80066e6: da2e bge.n 8006746 <_puts_r+0x9e> 80066e8: 4622 mov r2, r4 80066ea: 210a movs r1, #10 80066ec: 4628 mov r0, r5 80066ee: f000 f8f5 bl 80068dc <__swbuf_r> 80066f2: 3001 adds r0, #1 80066f4: d011 beq.n 800671a <_puts_r+0x72> 80066f6: 200a movs r0, #10 80066f8: e011 b.n 800671e <_puts_r+0x76> 80066fa: 4b17 ldr r3, [pc, #92] ; (8006758 <_puts_r+0xb0>) 80066fc: 429c cmp r4, r3 80066fe: d101 bne.n 8006704 <_puts_r+0x5c> 8006700: 68ac ldr r4, [r5, #8] 8006702: e7e3 b.n 80066cc <_puts_r+0x24> 8006704: 4b15 ldr r3, [pc, #84] ; (800675c <_puts_r+0xb4>) 8006706: 429c cmp r4, r3 8006708: bf08 it eq 800670a: 68ec ldreq r4, [r5, #12] 800670c: e7de b.n 80066cc <_puts_r+0x24> 800670e: 4621 mov r1, r4 8006710: 4628 mov r0, r5 8006712: f000 f935 bl 8006980 <__swsetup_r> 8006716: 2800 cmp r0, #0 8006718: d0dd beq.n 80066d6 <_puts_r+0x2e> 800671a: f04f 30ff mov.w r0, #4294967295 800671e: bd70 pop {r4, r5, r6, pc} 8006720: 2b00 cmp r3, #0 8006722: da04 bge.n 800672e <_puts_r+0x86> 8006724: 69a2 ldr r2, [r4, #24] 8006726: 429a cmp r2, r3 8006728: dc06 bgt.n 8006738 <_puts_r+0x90> 800672a: 290a cmp r1, #10 800672c: d004 beq.n 8006738 <_puts_r+0x90> 800672e: 6823 ldr r3, [r4, #0] 8006730: 1c5a adds r2, r3, #1 8006732: 6022 str r2, [r4, #0] 8006734: 7019 strb r1, [r3, #0] 8006736: e7cf b.n 80066d8 <_puts_r+0x30> 8006738: 4622 mov r2, r4 800673a: 4628 mov r0, r5 800673c: f000 f8ce bl 80068dc <__swbuf_r> 8006740: 3001 adds r0, #1 8006742: d1c9 bne.n 80066d8 <_puts_r+0x30> 8006744: e7e9 b.n 800671a <_puts_r+0x72> 8006746: 200a movs r0, #10 8006748: 6823 ldr r3, [r4, #0] 800674a: 1c5a adds r2, r3, #1 800674c: 6022 str r2, [r4, #0] 800674e: 7018 strb r0, [r3, #0] 8006750: e7e5 b.n 800671e <_puts_r+0x76> 8006752: bf00 nop 8006754: 08008a10 .word 0x08008a10 8006758: 08008a30 .word 0x08008a30 800675c: 080089f0 .word 0x080089f0 08006760 : 8006760: 4b02 ldr r3, [pc, #8] ; (800676c ) 8006762: 4601 mov r1, r0 8006764: 6818 ldr r0, [r3, #0] 8006766: f7ff bf9f b.w 80066a8 <_puts_r> 800676a: bf00 nop 800676c: 2000000c .word 0x2000000c 08006770 : 8006770: 2900 cmp r1, #0 8006772: f44f 6380 mov.w r3, #1024 ; 0x400 8006776: bf0c ite eq 8006778: 2202 moveq r2, #2 800677a: 2200 movne r2, #0 800677c: f000 b800 b.w 8006780 08006780 : 8006780: e92d 43f7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr} 8006784: 461d mov r5, r3 8006786: 4b51 ldr r3, [pc, #324] ; (80068cc ) 8006788: 4604 mov r4, r0 800678a: 681e ldr r6, [r3, #0] 800678c: 460f mov r7, r1 800678e: 4690 mov r8, r2 8006790: b126 cbz r6, 800679c 8006792: 69b3 ldr r3, [r6, #24] 8006794: b913 cbnz r3, 800679c 8006796: 4630 mov r0, r6 8006798: f001 f892 bl 80078c0 <__sinit> 800679c: 4b4c ldr r3, [pc, #304] ; (80068d0 ) 800679e: 429c cmp r4, r3 80067a0: d152 bne.n 8006848 80067a2: 6874 ldr r4, [r6, #4] 80067a4: f1b8 0f02 cmp.w r8, #2 80067a8: d006 beq.n 80067b8 80067aa: f1b8 0f01 cmp.w r8, #1 80067ae: f200 8089 bhi.w 80068c4 80067b2: 2d00 cmp r5, #0 80067b4: f2c0 8086 blt.w 80068c4 80067b8: 4621 mov r1, r4 80067ba: 4630 mov r0, r6 80067bc: f001 f816 bl 80077ec <_fflush_r> 80067c0: 6b61 ldr r1, [r4, #52] ; 0x34 80067c2: b141 cbz r1, 80067d6 80067c4: f104 0344 add.w r3, r4, #68 ; 0x44 80067c8: 4299 cmp r1, r3 80067ca: d002 beq.n 80067d2 80067cc: 4630 mov r0, r6 80067ce: f001 fc7f bl 80080d0 <_free_r> 80067d2: 2300 movs r3, #0 80067d4: 6363 str r3, [r4, #52] ; 0x34 80067d6: 2300 movs r3, #0 80067d8: 61a3 str r3, [r4, #24] 80067da: 6063 str r3, [r4, #4] 80067dc: 89a3 ldrh r3, [r4, #12] 80067de: 061b lsls r3, r3, #24 80067e0: d503 bpl.n 80067ea 80067e2: 6921 ldr r1, [r4, #16] 80067e4: 4630 mov r0, r6 80067e6: f001 fc73 bl 80080d0 <_free_r> 80067ea: 89a3 ldrh r3, [r4, #12] 80067ec: f1b8 0f02 cmp.w r8, #2 80067f0: f423 634a bic.w r3, r3, #3232 ; 0xca0 80067f4: f023 0303 bic.w r3, r3, #3 80067f8: 81a3 strh r3, [r4, #12] 80067fa: d05d beq.n 80068b8 80067fc: ab01 add r3, sp, #4 80067fe: 466a mov r2, sp 8006800: 4621 mov r1, r4 8006802: 4630 mov r0, r6 8006804: f001 f8f4 bl 80079f0 <__swhatbuf_r> 8006808: 89a3 ldrh r3, [r4, #12] 800680a: 4318 orrs r0, r3 800680c: 81a0 strh r0, [r4, #12] 800680e: bb2d cbnz r5, 800685c 8006810: 9d00 ldr r5, [sp, #0] 8006812: 4628 mov r0, r5 8006814: f001 f950 bl 8007ab8 8006818: 4607 mov r7, r0 800681a: 2800 cmp r0, #0 800681c: d14e bne.n 80068bc 800681e: f8dd 9000 ldr.w r9, [sp] 8006822: 45a9 cmp r9, r5 8006824: d13c bne.n 80068a0 8006826: f04f 30ff mov.w r0, #4294967295 800682a: 89a3 ldrh r3, [r4, #12] 800682c: f043 0302 orr.w r3, r3, #2 8006830: 81a3 strh r3, [r4, #12] 8006832: 2300 movs r3, #0 8006834: 60a3 str r3, [r4, #8] 8006836: f104 0347 add.w r3, r4, #71 ; 0x47 800683a: 6023 str r3, [r4, #0] 800683c: 6123 str r3, [r4, #16] 800683e: 2301 movs r3, #1 8006840: 6163 str r3, [r4, #20] 8006842: b003 add sp, #12 8006844: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} 8006848: 4b22 ldr r3, [pc, #136] ; (80068d4 ) 800684a: 429c cmp r4, r3 800684c: d101 bne.n 8006852 800684e: 68b4 ldr r4, [r6, #8] 8006850: e7a8 b.n 80067a4 8006852: 4b21 ldr r3, [pc, #132] ; (80068d8 ) 8006854: 429c cmp r4, r3 8006856: bf08 it eq 8006858: 68f4 ldreq r4, [r6, #12] 800685a: e7a3 b.n 80067a4 800685c: 2f00 cmp r7, #0 800685e: d0d8 beq.n 8006812 8006860: 69b3 ldr r3, [r6, #24] 8006862: b913 cbnz r3, 800686a 8006864: 4630 mov r0, r6 8006866: f001 f82b bl 80078c0 <__sinit> 800686a: f1b8 0f01 cmp.w r8, #1 800686e: bf08 it eq 8006870: 89a3 ldrheq r3, [r4, #12] 8006872: 6027 str r7, [r4, #0] 8006874: bf04 itt eq 8006876: f043 0301 orreq.w r3, r3, #1 800687a: 81a3 strheq r3, [r4, #12] 800687c: 89a3 ldrh r3, [r4, #12] 800687e: e9c4 7504 strd r7, r5, [r4, #16] 8006882: f013 0008 ands.w r0, r3, #8 8006886: d01b beq.n 80068c0 8006888: f013 0001 ands.w r0, r3, #1 800688c: f04f 0300 mov.w r3, #0 8006890: bf1f itttt ne 8006892: 426d negne r5, r5 8006894: 60a3 strne r3, [r4, #8] 8006896: 61a5 strne r5, [r4, #24] 8006898: 4618 movne r0, r3 800689a: bf08 it eq 800689c: 60a5 streq r5, [r4, #8] 800689e: e7d0 b.n 8006842 80068a0: 4648 mov r0, r9 80068a2: f001 f909 bl 8007ab8 80068a6: 4607 mov r7, r0 80068a8: 2800 cmp r0, #0 80068aa: d0bc beq.n 8006826 80068ac: 89a3 ldrh r3, [r4, #12] 80068ae: 464d mov r5, r9 80068b0: f043 0380 orr.w r3, r3, #128 ; 0x80 80068b4: 81a3 strh r3, [r4, #12] 80068b6: e7d3 b.n 8006860 80068b8: 2000 movs r0, #0 80068ba: e7b6 b.n 800682a 80068bc: 46a9 mov r9, r5 80068be: e7f5 b.n 80068ac 80068c0: 60a0 str r0, [r4, #8] 80068c2: e7be b.n 8006842 80068c4: f04f 30ff mov.w r0, #4294967295 80068c8: e7bb b.n 8006842 80068ca: bf00 nop 80068cc: 2000000c .word 0x2000000c 80068d0: 08008a10 .word 0x08008a10 80068d4: 08008a30 .word 0x08008a30 80068d8: 080089f0 .word 0x080089f0 080068dc <__swbuf_r>: 80068dc: b5f8 push {r3, r4, r5, r6, r7, lr} 80068de: 460e mov r6, r1 80068e0: 4614 mov r4, r2 80068e2: 4605 mov r5, r0 80068e4: b118 cbz r0, 80068ee <__swbuf_r+0x12> 80068e6: 6983 ldr r3, [r0, #24] 80068e8: b90b cbnz r3, 80068ee <__swbuf_r+0x12> 80068ea: f000 ffe9 bl 80078c0 <__sinit> 80068ee: 4b21 ldr r3, [pc, #132] ; (8006974 <__swbuf_r+0x98>) 80068f0: 429c cmp r4, r3 80068f2: d12a bne.n 800694a <__swbuf_r+0x6e> 80068f4: 686c ldr r4, [r5, #4] 80068f6: 69a3 ldr r3, [r4, #24] 80068f8: 60a3 str r3, [r4, #8] 80068fa: 89a3 ldrh r3, [r4, #12] 80068fc: 071a lsls r2, r3, #28 80068fe: d52e bpl.n 800695e <__swbuf_r+0x82> 8006900: 6923 ldr r3, [r4, #16] 8006902: b363 cbz r3, 800695e <__swbuf_r+0x82> 8006904: 6923 ldr r3, [r4, #16] 8006906: 6820 ldr r0, [r4, #0] 8006908: b2f6 uxtb r6, r6 800690a: 1ac0 subs r0, r0, r3 800690c: 6963 ldr r3, [r4, #20] 800690e: 4637 mov r7, r6 8006910: 4283 cmp r3, r0 8006912: dc04 bgt.n 800691e <__swbuf_r+0x42> 8006914: 4621 mov r1, r4 8006916: 4628 mov r0, r5 8006918: f000 ff68 bl 80077ec <_fflush_r> 800691c: bb28 cbnz r0, 800696a <__swbuf_r+0x8e> 800691e: 68a3 ldr r3, [r4, #8] 8006920: 3001 adds r0, #1 8006922: 3b01 subs r3, #1 8006924: 60a3 str r3, [r4, #8] 8006926: 6823 ldr r3, [r4, #0] 8006928: 1c5a adds r2, r3, #1 800692a: 6022 str r2, [r4, #0] 800692c: 701e strb r6, [r3, #0] 800692e: 6963 ldr r3, [r4, #20] 8006930: 4283 cmp r3, r0 8006932: d004 beq.n 800693e <__swbuf_r+0x62> 8006934: 89a3 ldrh r3, [r4, #12] 8006936: 07db lsls r3, r3, #31 8006938: d519 bpl.n 800696e <__swbuf_r+0x92> 800693a: 2e0a cmp r6, #10 800693c: d117 bne.n 800696e <__swbuf_r+0x92> 800693e: 4621 mov r1, r4 8006940: 4628 mov r0, r5 8006942: f000 ff53 bl 80077ec <_fflush_r> 8006946: b190 cbz r0, 800696e <__swbuf_r+0x92> 8006948: e00f b.n 800696a <__swbuf_r+0x8e> 800694a: 4b0b ldr r3, [pc, #44] ; (8006978 <__swbuf_r+0x9c>) 800694c: 429c cmp r4, r3 800694e: d101 bne.n 8006954 <__swbuf_r+0x78> 8006950: 68ac ldr r4, [r5, #8] 8006952: e7d0 b.n 80068f6 <__swbuf_r+0x1a> 8006954: 4b09 ldr r3, [pc, #36] ; (800697c <__swbuf_r+0xa0>) 8006956: 429c cmp r4, r3 8006958: bf08 it eq 800695a: 68ec ldreq r4, [r5, #12] 800695c: e7cb b.n 80068f6 <__swbuf_r+0x1a> 800695e: 4621 mov r1, r4 8006960: 4628 mov r0, r5 8006962: f000 f80d bl 8006980 <__swsetup_r> 8006966: 2800 cmp r0, #0 8006968: d0cc beq.n 8006904 <__swbuf_r+0x28> 800696a: f04f 37ff mov.w r7, #4294967295 800696e: 4638 mov r0, r7 8006970: bdf8 pop {r3, r4, r5, r6, r7, pc} 8006972: bf00 nop 8006974: 08008a10 .word 0x08008a10 8006978: 08008a30 .word 0x08008a30 800697c: 080089f0 .word 0x080089f0 08006980 <__swsetup_r>: 8006980: 4b32 ldr r3, [pc, #200] ; (8006a4c <__swsetup_r+0xcc>) 8006982: b570 push {r4, r5, r6, lr} 8006984: 681d ldr r5, [r3, #0] 8006986: 4606 mov r6, r0 8006988: 460c mov r4, r1 800698a: b125 cbz r5, 8006996 <__swsetup_r+0x16> 800698c: 69ab ldr r3, [r5, #24] 800698e: b913 cbnz r3, 8006996 <__swsetup_r+0x16> 8006990: 4628 mov r0, r5 8006992: f000 ff95 bl 80078c0 <__sinit> 8006996: 4b2e ldr r3, [pc, #184] ; (8006a50 <__swsetup_r+0xd0>) 8006998: 429c cmp r4, r3 800699a: d10f bne.n 80069bc <__swsetup_r+0x3c> 800699c: 686c ldr r4, [r5, #4] 800699e: f9b4 300c ldrsh.w r3, [r4, #12] 80069a2: b29a uxth r2, r3 80069a4: 0715 lsls r5, r2, #28 80069a6: d42c bmi.n 8006a02 <__swsetup_r+0x82> 80069a8: 06d0 lsls r0, r2, #27 80069aa: d411 bmi.n 80069d0 <__swsetup_r+0x50> 80069ac: 2209 movs r2, #9 80069ae: 6032 str r2, [r6, #0] 80069b0: f043 0340 orr.w r3, r3, #64 ; 0x40 80069b4: 81a3 strh r3, [r4, #12] 80069b6: f04f 30ff mov.w r0, #4294967295 80069ba: e03e b.n 8006a3a <__swsetup_r+0xba> 80069bc: 4b25 ldr r3, [pc, #148] ; (8006a54 <__swsetup_r+0xd4>) 80069be: 429c cmp r4, r3 80069c0: d101 bne.n 80069c6 <__swsetup_r+0x46> 80069c2: 68ac ldr r4, [r5, #8] 80069c4: e7eb b.n 800699e <__swsetup_r+0x1e> 80069c6: 4b24 ldr r3, [pc, #144] ; (8006a58 <__swsetup_r+0xd8>) 80069c8: 429c cmp r4, r3 80069ca: bf08 it eq 80069cc: 68ec ldreq r4, [r5, #12] 80069ce: e7e6 b.n 800699e <__swsetup_r+0x1e> 80069d0: 0751 lsls r1, r2, #29 80069d2: d512 bpl.n 80069fa <__swsetup_r+0x7a> 80069d4: 6b61 ldr r1, [r4, #52] ; 0x34 80069d6: b141 cbz r1, 80069ea <__swsetup_r+0x6a> 80069d8: f104 0344 add.w r3, r4, #68 ; 0x44 80069dc: 4299 cmp r1, r3 80069de: d002 beq.n 80069e6 <__swsetup_r+0x66> 80069e0: 4630 mov r0, r6 80069e2: f001 fb75 bl 80080d0 <_free_r> 80069e6: 2300 movs r3, #0 80069e8: 6363 str r3, [r4, #52] ; 0x34 80069ea: 89a3 ldrh r3, [r4, #12] 80069ec: f023 0324 bic.w r3, r3, #36 ; 0x24 80069f0: 81a3 strh r3, [r4, #12] 80069f2: 2300 movs r3, #0 80069f4: 6063 str r3, [r4, #4] 80069f6: 6923 ldr r3, [r4, #16] 80069f8: 6023 str r3, [r4, #0] 80069fa: 89a3 ldrh r3, [r4, #12] 80069fc: f043 0308 orr.w r3, r3, #8 8006a00: 81a3 strh r3, [r4, #12] 8006a02: 6923 ldr r3, [r4, #16] 8006a04: b94b cbnz r3, 8006a1a <__swsetup_r+0x9a> 8006a06: 89a3 ldrh r3, [r4, #12] 8006a08: f403 7320 and.w r3, r3, #640 ; 0x280 8006a0c: f5b3 7f00 cmp.w r3, #512 ; 0x200 8006a10: d003 beq.n 8006a1a <__swsetup_r+0x9a> 8006a12: 4621 mov r1, r4 8006a14: 4630 mov r0, r6 8006a16: f001 f80f bl 8007a38 <__smakebuf_r> 8006a1a: 89a2 ldrh r2, [r4, #12] 8006a1c: f012 0301 ands.w r3, r2, #1 8006a20: d00c beq.n 8006a3c <__swsetup_r+0xbc> 8006a22: 2300 movs r3, #0 8006a24: 60a3 str r3, [r4, #8] 8006a26: 6963 ldr r3, [r4, #20] 8006a28: 425b negs r3, r3 8006a2a: 61a3 str r3, [r4, #24] 8006a2c: 6923 ldr r3, [r4, #16] 8006a2e: b953 cbnz r3, 8006a46 <__swsetup_r+0xc6> 8006a30: f9b4 300c ldrsh.w r3, [r4, #12] 8006a34: f013 0080 ands.w r0, r3, #128 ; 0x80 8006a38: d1ba bne.n 80069b0 <__swsetup_r+0x30> 8006a3a: bd70 pop {r4, r5, r6, pc} 8006a3c: 0792 lsls r2, r2, #30 8006a3e: bf58 it pl 8006a40: 6963 ldrpl r3, [r4, #20] 8006a42: 60a3 str r3, [r4, #8] 8006a44: e7f2 b.n 8006a2c <__swsetup_r+0xac> 8006a46: 2000 movs r0, #0 8006a48: e7f7 b.n 8006a3a <__swsetup_r+0xba> 8006a4a: bf00 nop 8006a4c: 2000000c .word 0x2000000c 8006a50: 08008a10 .word 0x08008a10 8006a54: 08008a30 .word 0x08008a30 8006a58: 080089f0 .word 0x080089f0 08006a5c : 8006a5c: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} 8006a60: 6903 ldr r3, [r0, #16] 8006a62: 690c ldr r4, [r1, #16] 8006a64: 4680 mov r8, r0 8006a66: 42a3 cmp r3, r4 8006a68: f2c0 8084 blt.w 8006b74 8006a6c: 3c01 subs r4, #1 8006a6e: f101 0714 add.w r7, r1, #20 8006a72: f100 0614 add.w r6, r0, #20 8006a76: f857 5024 ldr.w r5, [r7, r4, lsl #2] 8006a7a: f856 0024 ldr.w r0, [r6, r4, lsl #2] 8006a7e: 3501 adds r5, #1 8006a80: fbb0 f5f5 udiv r5, r0, r5 8006a84: ea4f 0c84 mov.w ip, r4, lsl #2 8006a88: eb06 030c add.w r3, r6, ip 8006a8c: eb07 090c add.w r9, r7, ip 8006a90: 9301 str r3, [sp, #4] 8006a92: b39d cbz r5, 8006afc 8006a94: f04f 0a00 mov.w sl, #0 8006a98: 4638 mov r0, r7 8006a9a: 46b6 mov lr, r6 8006a9c: 46d3 mov fp, sl 8006a9e: f850 2b04 ldr.w r2, [r0], #4 8006aa2: b293 uxth r3, r2 8006aa4: fb05 a303 mla r3, r5, r3, sl 8006aa8: 0c12 lsrs r2, r2, #16 8006aaa: ea4f 4a13 mov.w sl, r3, lsr #16 8006aae: fb05 a202 mla r2, r5, r2, sl 8006ab2: b29b uxth r3, r3 8006ab4: ebab 0303 sub.w r3, fp, r3 8006ab8: f8de b000 ldr.w fp, [lr] 8006abc: ea4f 4a12 mov.w sl, r2, lsr #16 8006ac0: fa1f fb8b uxth.w fp, fp 8006ac4: 445b add r3, fp 8006ac6: fa1f fb82 uxth.w fp, r2 8006aca: f8de 2000 ldr.w r2, [lr] 8006ace: 4581 cmp r9, r0 8006ad0: ebcb 4212 rsb r2, fp, r2, lsr #16 8006ad4: eb02 4223 add.w r2, r2, r3, asr #16 8006ad8: b29b uxth r3, r3 8006ada: ea43 4302 orr.w r3, r3, r2, lsl #16 8006ade: ea4f 4b22 mov.w fp, r2, asr #16 8006ae2: f84e 3b04 str.w r3, [lr], #4 8006ae6: d2da bcs.n 8006a9e 8006ae8: f856 300c ldr.w r3, [r6, ip] 8006aec: b933 cbnz r3, 8006afc 8006aee: 9b01 ldr r3, [sp, #4] 8006af0: 3b04 subs r3, #4 8006af2: 429e cmp r6, r3 8006af4: 461a mov r2, r3 8006af6: d331 bcc.n 8006b5c 8006af8: f8c8 4010 str.w r4, [r8, #16] 8006afc: 4640 mov r0, r8 8006afe: f001 fa11 bl 8007f24 <__mcmp> 8006b02: 2800 cmp r0, #0 8006b04: db26 blt.n 8006b54 8006b06: 4630 mov r0, r6 8006b08: f04f 0c00 mov.w ip, #0 8006b0c: 3501 adds r5, #1 8006b0e: f857 1b04 ldr.w r1, [r7], #4 8006b12: f8d0 e000 ldr.w lr, [r0] 8006b16: b28b uxth r3, r1 8006b18: ebac 0303 sub.w r3, ip, r3 8006b1c: fa1f f28e uxth.w r2, lr 8006b20: 4413 add r3, r2 8006b22: 0c0a lsrs r2, r1, #16 8006b24: ebc2 421e rsb r2, r2, lr, lsr #16 8006b28: eb02 4223 add.w r2, r2, r3, asr #16 8006b2c: b29b uxth r3, r3 8006b2e: ea43 4302 orr.w r3, r3, r2, lsl #16 8006b32: 45b9 cmp r9, r7 8006b34: ea4f 4c22 mov.w ip, r2, asr #16 8006b38: f840 3b04 str.w r3, [r0], #4 8006b3c: d2e7 bcs.n 8006b0e 8006b3e: f856 2024 ldr.w r2, [r6, r4, lsl #2] 8006b42: eb06 0384 add.w r3, r6, r4, lsl #2 8006b46: b92a cbnz r2, 8006b54 8006b48: 3b04 subs r3, #4 8006b4a: 429e cmp r6, r3 8006b4c: 461a mov r2, r3 8006b4e: d30b bcc.n 8006b68 8006b50: f8c8 4010 str.w r4, [r8, #16] 8006b54: 4628 mov r0, r5 8006b56: b003 add sp, #12 8006b58: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8006b5c: 6812 ldr r2, [r2, #0] 8006b5e: 3b04 subs r3, #4 8006b60: 2a00 cmp r2, #0 8006b62: d1c9 bne.n 8006af8 8006b64: 3c01 subs r4, #1 8006b66: e7c4 b.n 8006af2 8006b68: 6812 ldr r2, [r2, #0] 8006b6a: 3b04 subs r3, #4 8006b6c: 2a00 cmp r2, #0 8006b6e: d1ef bne.n 8006b50 8006b70: 3c01 subs r4, #1 8006b72: e7ea b.n 8006b4a 8006b74: 2000 movs r0, #0 8006b76: e7ee b.n 8006b56 08006b78 <_dtoa_r>: 8006b78: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8006b7c: 4616 mov r6, r2 8006b7e: 461f mov r7, r3 8006b80: 6a45 ldr r5, [r0, #36] ; 0x24 8006b82: b095 sub sp, #84 ; 0x54 8006b84: 4604 mov r4, r0 8006b86: f8dd 8084 ldr.w r8, [sp, #132] ; 0x84 8006b8a: e9cd 6702 strd r6, r7, [sp, #8] 8006b8e: b93d cbnz r5, 8006ba0 <_dtoa_r+0x28> 8006b90: 2010 movs r0, #16 8006b92: f000 ff91 bl 8007ab8 8006b96: 6260 str r0, [r4, #36] ; 0x24 8006b98: e9c0 5501 strd r5, r5, [r0, #4] 8006b9c: 6005 str r5, [r0, #0] 8006b9e: 60c5 str r5, [r0, #12] 8006ba0: 6a63 ldr r3, [r4, #36] ; 0x24 8006ba2: 6819 ldr r1, [r3, #0] 8006ba4: b151 cbz r1, 8006bbc <_dtoa_r+0x44> 8006ba6: 685a ldr r2, [r3, #4] 8006ba8: 2301 movs r3, #1 8006baa: 4093 lsls r3, r2 8006bac: 604a str r2, [r1, #4] 8006bae: 608b str r3, [r1, #8] 8006bb0: 4620 mov r0, r4 8006bb2: f000 ffd6 bl 8007b62 <_Bfree> 8006bb6: 2200 movs r2, #0 8006bb8: 6a63 ldr r3, [r4, #36] ; 0x24 8006bba: 601a str r2, [r3, #0] 8006bbc: 1e3b subs r3, r7, #0 8006bbe: bfaf iteee ge 8006bc0: 2300 movge r3, #0 8006bc2: 2201 movlt r2, #1 8006bc4: f023 4300 biclt.w r3, r3, #2147483648 ; 0x80000000 8006bc8: 9303 strlt r3, [sp, #12] 8006bca: bfac ite ge 8006bcc: f8c8 3000 strge.w r3, [r8] 8006bd0: f8c8 2000 strlt.w r2, [r8] 8006bd4: 4bae ldr r3, [pc, #696] ; (8006e90 <_dtoa_r+0x318>) 8006bd6: f8dd 800c ldr.w r8, [sp, #12] 8006bda: ea33 0308 bics.w r3, r3, r8 8006bde: d11b bne.n 8006c18 <_dtoa_r+0xa0> 8006be0: f242 730f movw r3, #9999 ; 0x270f 8006be4: 9a20 ldr r2, [sp, #128] ; 0x80 8006be6: 6013 str r3, [r2, #0] 8006be8: 9b02 ldr r3, [sp, #8] 8006bea: b923 cbnz r3, 8006bf6 <_dtoa_r+0x7e> 8006bec: f3c8 0013 ubfx r0, r8, #0, #20 8006bf0: 2800 cmp r0, #0 8006bf2: f000 8545 beq.w 8007680 <_dtoa_r+0xb08> 8006bf6: 9b22 ldr r3, [sp, #136] ; 0x88 8006bf8: b953 cbnz r3, 8006c10 <_dtoa_r+0x98> 8006bfa: 4ba6 ldr r3, [pc, #664] ; (8006e94 <_dtoa_r+0x31c>) 8006bfc: e021 b.n 8006c42 <_dtoa_r+0xca> 8006bfe: 4ba6 ldr r3, [pc, #664] ; (8006e98 <_dtoa_r+0x320>) 8006c00: 9306 str r3, [sp, #24] 8006c02: 3308 adds r3, #8 8006c04: 9a22 ldr r2, [sp, #136] ; 0x88 8006c06: 6013 str r3, [r2, #0] 8006c08: 9806 ldr r0, [sp, #24] 8006c0a: b015 add sp, #84 ; 0x54 8006c0c: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8006c10: 4ba0 ldr r3, [pc, #640] ; (8006e94 <_dtoa_r+0x31c>) 8006c12: 9306 str r3, [sp, #24] 8006c14: 3303 adds r3, #3 8006c16: e7f5 b.n 8006c04 <_dtoa_r+0x8c> 8006c18: e9dd 6702 ldrd r6, r7, [sp, #8] 8006c1c: 2200 movs r2, #0 8006c1e: 2300 movs r3, #0 8006c20: 4630 mov r0, r6 8006c22: 4639 mov r1, r7 8006c24: f7f9 ff20 bl 8000a68 <__aeabi_dcmpeq> 8006c28: 4682 mov sl, r0 8006c2a: b160 cbz r0, 8006c46 <_dtoa_r+0xce> 8006c2c: 2301 movs r3, #1 8006c2e: 9a20 ldr r2, [sp, #128] ; 0x80 8006c30: 6013 str r3, [r2, #0] 8006c32: 9b22 ldr r3, [sp, #136] ; 0x88 8006c34: 2b00 cmp r3, #0 8006c36: f000 8520 beq.w 800767a <_dtoa_r+0xb02> 8006c3a: 4b98 ldr r3, [pc, #608] ; (8006e9c <_dtoa_r+0x324>) 8006c3c: 9a22 ldr r2, [sp, #136] ; 0x88 8006c3e: 6013 str r3, [r2, #0] 8006c40: 3b01 subs r3, #1 8006c42: 9306 str r3, [sp, #24] 8006c44: e7e0 b.n 8006c08 <_dtoa_r+0x90> 8006c46: ab12 add r3, sp, #72 ; 0x48 8006c48: 9301 str r3, [sp, #4] 8006c4a: ab13 add r3, sp, #76 ; 0x4c 8006c4c: 9300 str r3, [sp, #0] 8006c4e: 4632 mov r2, r6 8006c50: 463b mov r3, r7 8006c52: 4620 mov r0, r4 8006c54: f001 f9de bl 8008014 <__d2b> 8006c58: f3c8 550a ubfx r5, r8, #20, #11 8006c5c: 4683 mov fp, r0 8006c5e: 2d00 cmp r5, #0 8006c60: d07d beq.n 8006d5e <_dtoa_r+0x1e6> 8006c62: 46b0 mov r8, r6 8006c64: f3c7 0313 ubfx r3, r7, #0, #20 8006c68: f043 597f orr.w r9, r3, #1069547520 ; 0x3fc00000 8006c6c: f449 1940 orr.w r9, r9, #3145728 ; 0x300000 8006c70: f2a5 35ff subw r5, r5, #1023 ; 0x3ff 8006c74: f8cd a040 str.w sl, [sp, #64] ; 0x40 8006c78: 2200 movs r2, #0 8006c7a: 4b89 ldr r3, [pc, #548] ; (8006ea0 <_dtoa_r+0x328>) 8006c7c: 4640 mov r0, r8 8006c7e: 4649 mov r1, r9 8006c80: f7f9 fad2 bl 8000228 <__aeabi_dsub> 8006c84: a37c add r3, pc, #496 ; (adr r3, 8006e78 <_dtoa_r+0x300>) 8006c86: e9d3 2300 ldrd r2, r3, [r3] 8006c8a: f7f9 fc85 bl 8000598 <__aeabi_dmul> 8006c8e: a37c add r3, pc, #496 ; (adr r3, 8006e80 <_dtoa_r+0x308>) 8006c90: e9d3 2300 ldrd r2, r3, [r3] 8006c94: f7f9 faca bl 800022c <__adddf3> 8006c98: 4606 mov r6, r0 8006c9a: 4628 mov r0, r5 8006c9c: 460f mov r7, r1 8006c9e: f7f9 fc11 bl 80004c4 <__aeabi_i2d> 8006ca2: a379 add r3, pc, #484 ; (adr r3, 8006e88 <_dtoa_r+0x310>) 8006ca4: e9d3 2300 ldrd r2, r3, [r3] 8006ca8: f7f9 fc76 bl 8000598 <__aeabi_dmul> 8006cac: 4602 mov r2, r0 8006cae: 460b mov r3, r1 8006cb0: 4630 mov r0, r6 8006cb2: 4639 mov r1, r7 8006cb4: f7f9 faba bl 800022c <__adddf3> 8006cb8: 4606 mov r6, r0 8006cba: 460f mov r7, r1 8006cbc: f7f9 ff1c bl 8000af8 <__aeabi_d2iz> 8006cc0: 2200 movs r2, #0 8006cc2: 4682 mov sl, r0 8006cc4: 2300 movs r3, #0 8006cc6: 4630 mov r0, r6 8006cc8: 4639 mov r1, r7 8006cca: f7f9 fed7 bl 8000a7c <__aeabi_dcmplt> 8006cce: b148 cbz r0, 8006ce4 <_dtoa_r+0x16c> 8006cd0: 4650 mov r0, sl 8006cd2: f7f9 fbf7 bl 80004c4 <__aeabi_i2d> 8006cd6: 4632 mov r2, r6 8006cd8: 463b mov r3, r7 8006cda: f7f9 fec5 bl 8000a68 <__aeabi_dcmpeq> 8006cde: b908 cbnz r0, 8006ce4 <_dtoa_r+0x16c> 8006ce0: f10a 3aff add.w sl, sl, #4294967295 8006ce4: f1ba 0f16 cmp.w sl, #22 8006ce8: d85a bhi.n 8006da0 <_dtoa_r+0x228> 8006cea: e9dd 2302 ldrd r2, r3, [sp, #8] 8006cee: 496d ldr r1, [pc, #436] ; (8006ea4 <_dtoa_r+0x32c>) 8006cf0: eb01 01ca add.w r1, r1, sl, lsl #3 8006cf4: e9d1 0100 ldrd r0, r1, [r1] 8006cf8: f7f9 fede bl 8000ab8 <__aeabi_dcmpgt> 8006cfc: 2800 cmp r0, #0 8006cfe: d051 beq.n 8006da4 <_dtoa_r+0x22c> 8006d00: 2300 movs r3, #0 8006d02: f10a 3aff add.w sl, sl, #4294967295 8006d06: 930d str r3, [sp, #52] ; 0x34 8006d08: 9b12 ldr r3, [sp, #72] ; 0x48 8006d0a: 1b5d subs r5, r3, r5 8006d0c: 1e6b subs r3, r5, #1 8006d0e: 9307 str r3, [sp, #28] 8006d10: bf43 ittte mi 8006d12: 2300 movmi r3, #0 8006d14: f1c5 0901 rsbmi r9, r5, #1 8006d18: 9307 strmi r3, [sp, #28] 8006d1a: f04f 0900 movpl.w r9, #0 8006d1e: f1ba 0f00 cmp.w sl, #0 8006d22: db41 blt.n 8006da8 <_dtoa_r+0x230> 8006d24: 9b07 ldr r3, [sp, #28] 8006d26: f8cd a030 str.w sl, [sp, #48] ; 0x30 8006d2a: 4453 add r3, sl 8006d2c: 9307 str r3, [sp, #28] 8006d2e: 2300 movs r3, #0 8006d30: 9308 str r3, [sp, #32] 8006d32: 9b1e ldr r3, [sp, #120] ; 0x78 8006d34: 2b09 cmp r3, #9 8006d36: f200 808f bhi.w 8006e58 <_dtoa_r+0x2e0> 8006d3a: 2b05 cmp r3, #5 8006d3c: bfc4 itt gt 8006d3e: 3b04 subgt r3, #4 8006d40: 931e strgt r3, [sp, #120] ; 0x78 8006d42: 9b1e ldr r3, [sp, #120] ; 0x78 8006d44: bfc8 it gt 8006d46: 2500 movgt r5, #0 8006d48: f1a3 0302 sub.w r3, r3, #2 8006d4c: bfd8 it le 8006d4e: 2501 movle r5, #1 8006d50: 2b03 cmp r3, #3 8006d52: f200 808d bhi.w 8006e70 <_dtoa_r+0x2f8> 8006d56: e8df f003 tbb [pc, r3] 8006d5a: 7d7b .short 0x7d7b 8006d5c: 6f2f .short 0x6f2f 8006d5e: e9dd 5312 ldrd r5, r3, [sp, #72] ; 0x48 8006d62: 441d add r5, r3 8006d64: f205 4032 addw r0, r5, #1074 ; 0x432 8006d68: 2820 cmp r0, #32 8006d6a: dd13 ble.n 8006d94 <_dtoa_r+0x21c> 8006d6c: f1c0 0040 rsb r0, r0, #64 ; 0x40 8006d70: 9b02 ldr r3, [sp, #8] 8006d72: fa08 f800 lsl.w r8, r8, r0 8006d76: f205 4012 addw r0, r5, #1042 ; 0x412 8006d7a: fa23 f000 lsr.w r0, r3, r0 8006d7e: ea48 0000 orr.w r0, r8, r0 8006d82: f7f9 fb8f bl 80004a4 <__aeabi_ui2d> 8006d86: 2301 movs r3, #1 8006d88: 4680 mov r8, r0 8006d8a: f1a1 79f8 sub.w r9, r1, #32505856 ; 0x1f00000 8006d8e: 3d01 subs r5, #1 8006d90: 9310 str r3, [sp, #64] ; 0x40 8006d92: e771 b.n 8006c78 <_dtoa_r+0x100> 8006d94: 9b02 ldr r3, [sp, #8] 8006d96: f1c0 0020 rsb r0, r0, #32 8006d9a: fa03 f000 lsl.w r0, r3, r0 8006d9e: e7f0 b.n 8006d82 <_dtoa_r+0x20a> 8006da0: 2301 movs r3, #1 8006da2: e7b0 b.n 8006d06 <_dtoa_r+0x18e> 8006da4: 900d str r0, [sp, #52] ; 0x34 8006da6: e7af b.n 8006d08 <_dtoa_r+0x190> 8006da8: f1ca 0300 rsb r3, sl, #0 8006dac: 9308 str r3, [sp, #32] 8006dae: 2300 movs r3, #0 8006db0: eba9 090a sub.w r9, r9, sl 8006db4: 930c str r3, [sp, #48] ; 0x30 8006db6: e7bc b.n 8006d32 <_dtoa_r+0x1ba> 8006db8: 2301 movs r3, #1 8006dba: 9309 str r3, [sp, #36] ; 0x24 8006dbc: 9b1f ldr r3, [sp, #124] ; 0x7c 8006dbe: 2b00 cmp r3, #0 8006dc0: dd74 ble.n 8006eac <_dtoa_r+0x334> 8006dc2: 4698 mov r8, r3 8006dc4: 9304 str r3, [sp, #16] 8006dc6: 2200 movs r2, #0 8006dc8: 6a66 ldr r6, [r4, #36] ; 0x24 8006dca: 6072 str r2, [r6, #4] 8006dcc: 2204 movs r2, #4 8006dce: f102 0014 add.w r0, r2, #20 8006dd2: 4298 cmp r0, r3 8006dd4: 6871 ldr r1, [r6, #4] 8006dd6: d96e bls.n 8006eb6 <_dtoa_r+0x33e> 8006dd8: 4620 mov r0, r4 8006dda: f000 fe8e bl 8007afa <_Balloc> 8006dde: 6a63 ldr r3, [r4, #36] ; 0x24 8006de0: 6030 str r0, [r6, #0] 8006de2: 681b ldr r3, [r3, #0] 8006de4: f1b8 0f0e cmp.w r8, #14 8006de8: 9306 str r3, [sp, #24] 8006dea: f200 80ed bhi.w 8006fc8 <_dtoa_r+0x450> 8006dee: 2d00 cmp r5, #0 8006df0: f000 80ea beq.w 8006fc8 <_dtoa_r+0x450> 8006df4: e9dd 2302 ldrd r2, r3, [sp, #8] 8006df8: f1ba 0f00 cmp.w sl, #0 8006dfc: e9cd 230e strd r2, r3, [sp, #56] ; 0x38 8006e00: dd77 ble.n 8006ef2 <_dtoa_r+0x37a> 8006e02: 4a28 ldr r2, [pc, #160] ; (8006ea4 <_dtoa_r+0x32c>) 8006e04: f00a 030f and.w r3, sl, #15 8006e08: ea4f 162a mov.w r6, sl, asr #4 8006e0c: eb02 03c3 add.w r3, r2, r3, lsl #3 8006e10: 06f0 lsls r0, r6, #27 8006e12: e9d3 2300 ldrd r2, r3, [r3] 8006e16: e9cd 230a strd r2, r3, [sp, #40] ; 0x28 8006e1a: d568 bpl.n 8006eee <_dtoa_r+0x376> 8006e1c: e9dd 010e ldrd r0, r1, [sp, #56] ; 0x38 8006e20: 4b21 ldr r3, [pc, #132] ; (8006ea8 <_dtoa_r+0x330>) 8006e22: 2503 movs r5, #3 8006e24: e9d3 2308 ldrd r2, r3, [r3, #32] 8006e28: f7f9 fce0 bl 80007ec <__aeabi_ddiv> 8006e2c: e9cd 0102 strd r0, r1, [sp, #8] 8006e30: f006 060f and.w r6, r6, #15 8006e34: 4f1c ldr r7, [pc, #112] ; (8006ea8 <_dtoa_r+0x330>) 8006e36: e04f b.n 8006ed8 <_dtoa_r+0x360> 8006e38: 2301 movs r3, #1 8006e3a: 9309 str r3, [sp, #36] ; 0x24 8006e3c: 9b1f ldr r3, [sp, #124] ; 0x7c 8006e3e: 4453 add r3, sl 8006e40: f103 0801 add.w r8, r3, #1 8006e44: 9304 str r3, [sp, #16] 8006e46: 4643 mov r3, r8 8006e48: 2b01 cmp r3, #1 8006e4a: bfb8 it lt 8006e4c: 2301 movlt r3, #1 8006e4e: e7ba b.n 8006dc6 <_dtoa_r+0x24e> 8006e50: 2300 movs r3, #0 8006e52: e7b2 b.n 8006dba <_dtoa_r+0x242> 8006e54: 2300 movs r3, #0 8006e56: e7f0 b.n 8006e3a <_dtoa_r+0x2c2> 8006e58: 2501 movs r5, #1 8006e5a: 2300 movs r3, #0 8006e5c: 9509 str r5, [sp, #36] ; 0x24 8006e5e: 931e str r3, [sp, #120] ; 0x78 8006e60: f04f 33ff mov.w r3, #4294967295 8006e64: 2200 movs r2, #0 8006e66: 9304 str r3, [sp, #16] 8006e68: 4698 mov r8, r3 8006e6a: 2312 movs r3, #18 8006e6c: 921f str r2, [sp, #124] ; 0x7c 8006e6e: e7aa b.n 8006dc6 <_dtoa_r+0x24e> 8006e70: 2301 movs r3, #1 8006e72: 9309 str r3, [sp, #36] ; 0x24 8006e74: e7f4 b.n 8006e60 <_dtoa_r+0x2e8> 8006e76: bf00 nop 8006e78: 636f4361 .word 0x636f4361 8006e7c: 3fd287a7 .word 0x3fd287a7 8006e80: 8b60c8b3 .word 0x8b60c8b3 8006e84: 3fc68a28 .word 0x3fc68a28 8006e88: 509f79fb .word 0x509f79fb 8006e8c: 3fd34413 .word 0x3fd34413 8006e90: 7ff00000 .word 0x7ff00000 8006e94: 080089e9 .word 0x080089e9 8006e98: 080089e0 .word 0x080089e0 8006e9c: 080089bd .word 0x080089bd 8006ea0: 3ff80000 .word 0x3ff80000 8006ea4: 08008a78 .word 0x08008a78 8006ea8: 08008a50 .word 0x08008a50 8006eac: 2301 movs r3, #1 8006eae: 9304 str r3, [sp, #16] 8006eb0: 4698 mov r8, r3 8006eb2: 461a mov r2, r3 8006eb4: e7da b.n 8006e6c <_dtoa_r+0x2f4> 8006eb6: 3101 adds r1, #1 8006eb8: 6071 str r1, [r6, #4] 8006eba: 0052 lsls r2, r2, #1 8006ebc: e787 b.n 8006dce <_dtoa_r+0x256> 8006ebe: 07f1 lsls r1, r6, #31 8006ec0: d508 bpl.n 8006ed4 <_dtoa_r+0x35c> 8006ec2: e9dd 010a ldrd r0, r1, [sp, #40] ; 0x28 8006ec6: e9d7 2300 ldrd r2, r3, [r7] 8006eca: f7f9 fb65 bl 8000598 <__aeabi_dmul> 8006ece: e9cd 010a strd r0, r1, [sp, #40] ; 0x28 8006ed2: 3501 adds r5, #1 8006ed4: 1076 asrs r6, r6, #1 8006ed6: 3708 adds r7, #8 8006ed8: 2e00 cmp r6, #0 8006eda: d1f0 bne.n 8006ebe <_dtoa_r+0x346> 8006edc: e9dd 230a ldrd r2, r3, [sp, #40] ; 0x28 8006ee0: e9dd 0102 ldrd r0, r1, [sp, #8] 8006ee4: f7f9 fc82 bl 80007ec <__aeabi_ddiv> 8006ee8: e9cd 0102 strd r0, r1, [sp, #8] 8006eec: e01b b.n 8006f26 <_dtoa_r+0x3ae> 8006eee: 2502 movs r5, #2 8006ef0: e7a0 b.n 8006e34 <_dtoa_r+0x2bc> 8006ef2: f000 80a4 beq.w 800703e <_dtoa_r+0x4c6> 8006ef6: e9dd 010e ldrd r0, r1, [sp, #56] ; 0x38 8006efa: f1ca 0600 rsb r6, sl, #0 8006efe: 4ba0 ldr r3, [pc, #640] ; (8007180 <_dtoa_r+0x608>) 8006f00: f006 020f and.w r2, r6, #15 8006f04: eb03 03c2 add.w r3, r3, r2, lsl #3 8006f08: e9d3 2300 ldrd r2, r3, [r3] 8006f0c: f7f9 fb44 bl 8000598 <__aeabi_dmul> 8006f10: 2502 movs r5, #2 8006f12: 2300 movs r3, #0 8006f14: e9cd 0102 strd r0, r1, [sp, #8] 8006f18: 4f9a ldr r7, [pc, #616] ; (8007184 <_dtoa_r+0x60c>) 8006f1a: 1136 asrs r6, r6, #4 8006f1c: 2e00 cmp r6, #0 8006f1e: f040 8083 bne.w 8007028 <_dtoa_r+0x4b0> 8006f22: 2b00 cmp r3, #0 8006f24: d1e0 bne.n 8006ee8 <_dtoa_r+0x370> 8006f26: 9b0d ldr r3, [sp, #52] ; 0x34 8006f28: 2b00 cmp r3, #0 8006f2a: f000 808a beq.w 8007042 <_dtoa_r+0x4ca> 8006f2e: e9dd 2302 ldrd r2, r3, [sp, #8] 8006f32: e9cd 230a strd r2, r3, [sp, #40] ; 0x28 8006f36: e9dd 010a ldrd r0, r1, [sp, #40] ; 0x28 8006f3a: 2200 movs r2, #0 8006f3c: 4b92 ldr r3, [pc, #584] ; (8007188 <_dtoa_r+0x610>) 8006f3e: f7f9 fd9d bl 8000a7c <__aeabi_dcmplt> 8006f42: 2800 cmp r0, #0 8006f44: d07d beq.n 8007042 <_dtoa_r+0x4ca> 8006f46: f1b8 0f00 cmp.w r8, #0 8006f4a: d07a beq.n 8007042 <_dtoa_r+0x4ca> 8006f4c: 9b04 ldr r3, [sp, #16] 8006f4e: 2b00 cmp r3, #0 8006f50: dd36 ble.n 8006fc0 <_dtoa_r+0x448> 8006f52: e9dd 010a ldrd r0, r1, [sp, #40] ; 0x28 8006f56: 2200 movs r2, #0 8006f58: 4b8c ldr r3, [pc, #560] ; (800718c <_dtoa_r+0x614>) 8006f5a: f7f9 fb1d bl 8000598 <__aeabi_dmul> 8006f5e: e9cd 0102 strd r0, r1, [sp, #8] 8006f62: 9e04 ldr r6, [sp, #16] 8006f64: f10a 37ff add.w r7, sl, #4294967295 8006f68: 3501 adds r5, #1 8006f6a: 4628 mov r0, r5 8006f6c: f7f9 faaa bl 80004c4 <__aeabi_i2d> 8006f70: e9dd 2302 ldrd r2, r3, [sp, #8] 8006f74: f7f9 fb10 bl 8000598 <__aeabi_dmul> 8006f78: 2200 movs r2, #0 8006f7a: 4b85 ldr r3, [pc, #532] ; (8007190 <_dtoa_r+0x618>) 8006f7c: f7f9 f956 bl 800022c <__adddf3> 8006f80: f1a1 7550 sub.w r5, r1, #54525952 ; 0x3400000 8006f84: e9cd 010a strd r0, r1, [sp, #40] ; 0x28 8006f88: 950b str r5, [sp, #44] ; 0x2c 8006f8a: 2e00 cmp r6, #0 8006f8c: d15c bne.n 8007048 <_dtoa_r+0x4d0> 8006f8e: e9dd 0102 ldrd r0, r1, [sp, #8] 8006f92: 2200 movs r2, #0 8006f94: 4b7f ldr r3, [pc, #508] ; (8007194 <_dtoa_r+0x61c>) 8006f96: f7f9 f947 bl 8000228 <__aeabi_dsub> 8006f9a: 9a0a ldr r2, [sp, #40] ; 0x28 8006f9c: 462b mov r3, r5 8006f9e: e9cd 0102 strd r0, r1, [sp, #8] 8006fa2: f7f9 fd89 bl 8000ab8 <__aeabi_dcmpgt> 8006fa6: 2800 cmp r0, #0 8006fa8: f040 8281 bne.w 80074ae <_dtoa_r+0x936> 8006fac: e9dd 0102 ldrd r0, r1, [sp, #8] 8006fb0: 9a0a ldr r2, [sp, #40] ; 0x28 8006fb2: f105 4300 add.w r3, r5, #2147483648 ; 0x80000000 8006fb6: f7f9 fd61 bl 8000a7c <__aeabi_dcmplt> 8006fba: 2800 cmp r0, #0 8006fbc: f040 8275 bne.w 80074aa <_dtoa_r+0x932> 8006fc0: e9dd 230e ldrd r2, r3, [sp, #56] ; 0x38 8006fc4: e9cd 2302 strd r2, r3, [sp, #8] 8006fc8: 9b13 ldr r3, [sp, #76] ; 0x4c 8006fca: 2b00 cmp r3, #0 8006fcc: f2c0 814b blt.w 8007266 <_dtoa_r+0x6ee> 8006fd0: f1ba 0f0e cmp.w sl, #14 8006fd4: f300 8147 bgt.w 8007266 <_dtoa_r+0x6ee> 8006fd8: 4b69 ldr r3, [pc, #420] ; (8007180 <_dtoa_r+0x608>) 8006fda: eb03 03ca add.w r3, r3, sl, lsl #3 8006fde: e9d3 2300 ldrd r2, r3, [r3] 8006fe2: e9cd 2304 strd r2, r3, [sp, #16] 8006fe6: 9b1f ldr r3, [sp, #124] ; 0x7c 8006fe8: 2b00 cmp r3, #0 8006fea: f280 80d7 bge.w 800719c <_dtoa_r+0x624> 8006fee: f1b8 0f00 cmp.w r8, #0 8006ff2: f300 80d3 bgt.w 800719c <_dtoa_r+0x624> 8006ff6: f040 8257 bne.w 80074a8 <_dtoa_r+0x930> 8006ffa: e9dd 0104 ldrd r0, r1, [sp, #16] 8006ffe: 2200 movs r2, #0 8007000: 4b64 ldr r3, [pc, #400] ; (8007194 <_dtoa_r+0x61c>) 8007002: f7f9 fac9 bl 8000598 <__aeabi_dmul> 8007006: e9dd 2302 ldrd r2, r3, [sp, #8] 800700a: f7f9 fd4b bl 8000aa4 <__aeabi_dcmpge> 800700e: 4646 mov r6, r8 8007010: 4647 mov r7, r8 8007012: 2800 cmp r0, #0 8007014: f040 822d bne.w 8007472 <_dtoa_r+0x8fa> 8007018: 9b06 ldr r3, [sp, #24] 800701a: 9a06 ldr r2, [sp, #24] 800701c: 1c5d adds r5, r3, #1 800701e: 2331 movs r3, #49 ; 0x31 8007020: f10a 0a01 add.w sl, sl, #1 8007024: 7013 strb r3, [r2, #0] 8007026: e228 b.n 800747a <_dtoa_r+0x902> 8007028: 07f2 lsls r2, r6, #31 800702a: d505 bpl.n 8007038 <_dtoa_r+0x4c0> 800702c: e9d7 2300 ldrd r2, r3, [r7] 8007030: f7f9 fab2 bl 8000598 <__aeabi_dmul> 8007034: 2301 movs r3, #1 8007036: 3501 adds r5, #1 8007038: 1076 asrs r6, r6, #1 800703a: 3708 adds r7, #8 800703c: e76e b.n 8006f1c <_dtoa_r+0x3a4> 800703e: 2502 movs r5, #2 8007040: e771 b.n 8006f26 <_dtoa_r+0x3ae> 8007042: 4657 mov r7, sl 8007044: 4646 mov r6, r8 8007046: e790 b.n 8006f6a <_dtoa_r+0x3f2> 8007048: 4b4d ldr r3, [pc, #308] ; (8007180 <_dtoa_r+0x608>) 800704a: eb03 03c6 add.w r3, r3, r6, lsl #3 800704e: e953 0102 ldrd r0, r1, [r3, #-8] 8007052: 9b09 ldr r3, [sp, #36] ; 0x24 8007054: 2b00 cmp r3, #0 8007056: d048 beq.n 80070ea <_dtoa_r+0x572> 8007058: 4602 mov r2, r0 800705a: 460b mov r3, r1 800705c: 2000 movs r0, #0 800705e: 494e ldr r1, [pc, #312] ; (8007198 <_dtoa_r+0x620>) 8007060: f7f9 fbc4 bl 80007ec <__aeabi_ddiv> 8007064: e9dd 230a ldrd r2, r3, [sp, #40] ; 0x28 8007068: f7f9 f8de bl 8000228 <__aeabi_dsub> 800706c: e9cd 010a strd r0, r1, [sp, #40] ; 0x28 8007070: 9d06 ldr r5, [sp, #24] 8007072: e9dd 0102 ldrd r0, r1, [sp, #8] 8007076: f7f9 fd3f bl 8000af8 <__aeabi_d2iz> 800707a: 9011 str r0, [sp, #68] ; 0x44 800707c: f7f9 fa22 bl 80004c4 <__aeabi_i2d> 8007080: 4602 mov r2, r0 8007082: 460b mov r3, r1 8007084: e9dd 0102 ldrd r0, r1, [sp, #8] 8007088: f7f9 f8ce bl 8000228 <__aeabi_dsub> 800708c: 9b11 ldr r3, [sp, #68] ; 0x44 800708e: e9cd 0102 strd r0, r1, [sp, #8] 8007092: 3330 adds r3, #48 ; 0x30 8007094: f805 3b01 strb.w r3, [r5], #1 8007098: e9dd 230a ldrd r2, r3, [sp, #40] ; 0x28 800709c: f7f9 fcee bl 8000a7c <__aeabi_dcmplt> 80070a0: 2800 cmp r0, #0 80070a2: d163 bne.n 800716c <_dtoa_r+0x5f4> 80070a4: e9dd 2302 ldrd r2, r3, [sp, #8] 80070a8: 2000 movs r0, #0 80070aa: 4937 ldr r1, [pc, #220] ; (8007188 <_dtoa_r+0x610>) 80070ac: f7f9 f8bc bl 8000228 <__aeabi_dsub> 80070b0: e9dd 230a ldrd r2, r3, [sp, #40] ; 0x28 80070b4: f7f9 fce2 bl 8000a7c <__aeabi_dcmplt> 80070b8: 2800 cmp r0, #0 80070ba: f040 80b5 bne.w 8007228 <_dtoa_r+0x6b0> 80070be: 9b06 ldr r3, [sp, #24] 80070c0: 1aeb subs r3, r5, r3 80070c2: 429e cmp r6, r3 80070c4: f77f af7c ble.w 8006fc0 <_dtoa_r+0x448> 80070c8: e9dd 010a ldrd r0, r1, [sp, #40] ; 0x28 80070cc: 2200 movs r2, #0 80070ce: 4b2f ldr r3, [pc, #188] ; (800718c <_dtoa_r+0x614>) 80070d0: f7f9 fa62 bl 8000598 <__aeabi_dmul> 80070d4: 2200 movs r2, #0 80070d6: e9cd 010a strd r0, r1, [sp, #40] ; 0x28 80070da: e9dd 0102 ldrd r0, r1, [sp, #8] 80070de: 4b2b ldr r3, [pc, #172] ; (800718c <_dtoa_r+0x614>) 80070e0: f7f9 fa5a bl 8000598 <__aeabi_dmul> 80070e4: e9cd 0102 strd r0, r1, [sp, #8] 80070e8: e7c3 b.n 8007072 <_dtoa_r+0x4fa> 80070ea: e9dd 230a ldrd r2, r3, [sp, #40] ; 0x28 80070ee: f7f9 fa53 bl 8000598 <__aeabi_dmul> 80070f2: 9b06 ldr r3, [sp, #24] 80070f4: e9cd 010a strd r0, r1, [sp, #40] ; 0x28 80070f8: 199d adds r5, r3, r6 80070fa: 461e mov r6, r3 80070fc: e9dd 0102 ldrd r0, r1, [sp, #8] 8007100: f7f9 fcfa bl 8000af8 <__aeabi_d2iz> 8007104: 9011 str r0, [sp, #68] ; 0x44 8007106: f7f9 f9dd bl 80004c4 <__aeabi_i2d> 800710a: 4602 mov r2, r0 800710c: 460b mov r3, r1 800710e: e9dd 0102 ldrd r0, r1, [sp, #8] 8007112: f7f9 f889 bl 8000228 <__aeabi_dsub> 8007116: 9b11 ldr r3, [sp, #68] ; 0x44 8007118: e9cd 0102 strd r0, r1, [sp, #8] 800711c: 3330 adds r3, #48 ; 0x30 800711e: f806 3b01 strb.w r3, [r6], #1 8007122: 42ae cmp r6, r5 8007124: f04f 0200 mov.w r2, #0 8007128: d124 bne.n 8007174 <_dtoa_r+0x5fc> 800712a: e9dd 010a ldrd r0, r1, [sp, #40] ; 0x28 800712e: 4b1a ldr r3, [pc, #104] ; (8007198 <_dtoa_r+0x620>) 8007130: f7f9 f87c bl 800022c <__adddf3> 8007134: 4602 mov r2, r0 8007136: 460b mov r3, r1 8007138: e9dd 0102 ldrd r0, r1, [sp, #8] 800713c: f7f9 fcbc bl 8000ab8 <__aeabi_dcmpgt> 8007140: 2800 cmp r0, #0 8007142: d171 bne.n 8007228 <_dtoa_r+0x6b0> 8007144: e9dd 230a ldrd r2, r3, [sp, #40] ; 0x28 8007148: 2000 movs r0, #0 800714a: 4913 ldr r1, [pc, #76] ; (8007198 <_dtoa_r+0x620>) 800714c: f7f9 f86c bl 8000228 <__aeabi_dsub> 8007150: 4602 mov r2, r0 8007152: 460b mov r3, r1 8007154: e9dd 0102 ldrd r0, r1, [sp, #8] 8007158: f7f9 fc90 bl 8000a7c <__aeabi_dcmplt> 800715c: 2800 cmp r0, #0 800715e: f43f af2f beq.w 8006fc0 <_dtoa_r+0x448> 8007162: f815 3c01 ldrb.w r3, [r5, #-1] 8007166: 1e6a subs r2, r5, #1 8007168: 2b30 cmp r3, #48 ; 0x30 800716a: d001 beq.n 8007170 <_dtoa_r+0x5f8> 800716c: 46ba mov sl, r7 800716e: e04a b.n 8007206 <_dtoa_r+0x68e> 8007170: 4615 mov r5, r2 8007172: e7f6 b.n 8007162 <_dtoa_r+0x5ea> 8007174: 4b05 ldr r3, [pc, #20] ; (800718c <_dtoa_r+0x614>) 8007176: f7f9 fa0f bl 8000598 <__aeabi_dmul> 800717a: e9cd 0102 strd r0, r1, [sp, #8] 800717e: e7bd b.n 80070fc <_dtoa_r+0x584> 8007180: 08008a78 .word 0x08008a78 8007184: 08008a50 .word 0x08008a50 8007188: 3ff00000 .word 0x3ff00000 800718c: 40240000 .word 0x40240000 8007190: 401c0000 .word 0x401c0000 8007194: 40140000 .word 0x40140000 8007198: 3fe00000 .word 0x3fe00000 800719c: 9d06 ldr r5, [sp, #24] 800719e: e9dd 6702 ldrd r6, r7, [sp, #8] 80071a2: e9dd 2304 ldrd r2, r3, [sp, #16] 80071a6: 4630 mov r0, r6 80071a8: 4639 mov r1, r7 80071aa: f7f9 fb1f bl 80007ec <__aeabi_ddiv> 80071ae: f7f9 fca3 bl 8000af8 <__aeabi_d2iz> 80071b2: 4681 mov r9, r0 80071b4: f7f9 f986 bl 80004c4 <__aeabi_i2d> 80071b8: e9dd 2304 ldrd r2, r3, [sp, #16] 80071bc: f7f9 f9ec bl 8000598 <__aeabi_dmul> 80071c0: 4602 mov r2, r0 80071c2: 460b mov r3, r1 80071c4: 4630 mov r0, r6 80071c6: 4639 mov r1, r7 80071c8: f7f9 f82e bl 8000228 <__aeabi_dsub> 80071cc: f109 0630 add.w r6, r9, #48 ; 0x30 80071d0: f805 6b01 strb.w r6, [r5], #1 80071d4: 9e06 ldr r6, [sp, #24] 80071d6: 4602 mov r2, r0 80071d8: 1bae subs r6, r5, r6 80071da: 45b0 cmp r8, r6 80071dc: 460b mov r3, r1 80071de: d135 bne.n 800724c <_dtoa_r+0x6d4> 80071e0: f7f9 f824 bl 800022c <__adddf3> 80071e4: e9dd 2304 ldrd r2, r3, [sp, #16] 80071e8: 4606 mov r6, r0 80071ea: 460f mov r7, r1 80071ec: f7f9 fc64 bl 8000ab8 <__aeabi_dcmpgt> 80071f0: b9c8 cbnz r0, 8007226 <_dtoa_r+0x6ae> 80071f2: e9dd 2304 ldrd r2, r3, [sp, #16] 80071f6: 4630 mov r0, r6 80071f8: 4639 mov r1, r7 80071fa: f7f9 fc35 bl 8000a68 <__aeabi_dcmpeq> 80071fe: b110 cbz r0, 8007206 <_dtoa_r+0x68e> 8007200: f019 0f01 tst.w r9, #1 8007204: d10f bne.n 8007226 <_dtoa_r+0x6ae> 8007206: 4659 mov r1, fp 8007208: 4620 mov r0, r4 800720a: f000 fcaa bl 8007b62 <_Bfree> 800720e: 2300 movs r3, #0 8007210: 9a20 ldr r2, [sp, #128] ; 0x80 8007212: 702b strb r3, [r5, #0] 8007214: f10a 0301 add.w r3, sl, #1 8007218: 6013 str r3, [r2, #0] 800721a: 9b22 ldr r3, [sp, #136] ; 0x88 800721c: 2b00 cmp r3, #0 800721e: f43f acf3 beq.w 8006c08 <_dtoa_r+0x90> 8007222: 601d str r5, [r3, #0] 8007224: e4f0 b.n 8006c08 <_dtoa_r+0x90> 8007226: 4657 mov r7, sl 8007228: f815 2c01 ldrb.w r2, [r5, #-1] 800722c: 1e6b subs r3, r5, #1 800722e: 2a39 cmp r2, #57 ; 0x39 8007230: d106 bne.n 8007240 <_dtoa_r+0x6c8> 8007232: 9a06 ldr r2, [sp, #24] 8007234: 429a cmp r2, r3 8007236: d107 bne.n 8007248 <_dtoa_r+0x6d0> 8007238: 2330 movs r3, #48 ; 0x30 800723a: 7013 strb r3, [r2, #0] 800723c: 4613 mov r3, r2 800723e: 3701 adds r7, #1 8007240: 781a ldrb r2, [r3, #0] 8007242: 3201 adds r2, #1 8007244: 701a strb r2, [r3, #0] 8007246: e791 b.n 800716c <_dtoa_r+0x5f4> 8007248: 461d mov r5, r3 800724a: e7ed b.n 8007228 <_dtoa_r+0x6b0> 800724c: 2200 movs r2, #0 800724e: 4b99 ldr r3, [pc, #612] ; (80074b4 <_dtoa_r+0x93c>) 8007250: f7f9 f9a2 bl 8000598 <__aeabi_dmul> 8007254: 2200 movs r2, #0 8007256: 2300 movs r3, #0 8007258: 4606 mov r6, r0 800725a: 460f mov r7, r1 800725c: f7f9 fc04 bl 8000a68 <__aeabi_dcmpeq> 8007260: 2800 cmp r0, #0 8007262: d09e beq.n 80071a2 <_dtoa_r+0x62a> 8007264: e7cf b.n 8007206 <_dtoa_r+0x68e> 8007266: 9a09 ldr r2, [sp, #36] ; 0x24 8007268: 2a00 cmp r2, #0 800726a: f000 8088 beq.w 800737e <_dtoa_r+0x806> 800726e: 9a1e ldr r2, [sp, #120] ; 0x78 8007270: 2a01 cmp r2, #1 8007272: dc6d bgt.n 8007350 <_dtoa_r+0x7d8> 8007274: 9a10 ldr r2, [sp, #64] ; 0x40 8007276: 2a00 cmp r2, #0 8007278: d066 beq.n 8007348 <_dtoa_r+0x7d0> 800727a: f203 4333 addw r3, r3, #1075 ; 0x433 800727e: 464d mov r5, r9 8007280: 9e08 ldr r6, [sp, #32] 8007282: 9a07 ldr r2, [sp, #28] 8007284: 2101 movs r1, #1 8007286: 441a add r2, r3 8007288: 4620 mov r0, r4 800728a: 4499 add r9, r3 800728c: 9207 str r2, [sp, #28] 800728e: f000 fd08 bl 8007ca2 <__i2b> 8007292: 4607 mov r7, r0 8007294: 2d00 cmp r5, #0 8007296: dd0b ble.n 80072b0 <_dtoa_r+0x738> 8007298: 9b07 ldr r3, [sp, #28] 800729a: 2b00 cmp r3, #0 800729c: dd08 ble.n 80072b0 <_dtoa_r+0x738> 800729e: 42ab cmp r3, r5 80072a0: bfa8 it ge 80072a2: 462b movge r3, r5 80072a4: 9a07 ldr r2, [sp, #28] 80072a6: eba9 0903 sub.w r9, r9, r3 80072aa: 1aed subs r5, r5, r3 80072ac: 1ad3 subs r3, r2, r3 80072ae: 9307 str r3, [sp, #28] 80072b0: 9b08 ldr r3, [sp, #32] 80072b2: b1eb cbz r3, 80072f0 <_dtoa_r+0x778> 80072b4: 9b09 ldr r3, [sp, #36] ; 0x24 80072b6: 2b00 cmp r3, #0 80072b8: d065 beq.n 8007386 <_dtoa_r+0x80e> 80072ba: b18e cbz r6, 80072e0 <_dtoa_r+0x768> 80072bc: 4639 mov r1, r7 80072be: 4632 mov r2, r6 80072c0: 4620 mov r0, r4 80072c2: f000 fd8d bl 8007de0 <__pow5mult> 80072c6: 465a mov r2, fp 80072c8: 4601 mov r1, r0 80072ca: 4607 mov r7, r0 80072cc: 4620 mov r0, r4 80072ce: f000 fcf1 bl 8007cb4 <__multiply> 80072d2: 4659 mov r1, fp 80072d4: 900a str r0, [sp, #40] ; 0x28 80072d6: 4620 mov r0, r4 80072d8: f000 fc43 bl 8007b62 <_Bfree> 80072dc: 9b0a ldr r3, [sp, #40] ; 0x28 80072de: 469b mov fp, r3 80072e0: 9b08 ldr r3, [sp, #32] 80072e2: 1b9a subs r2, r3, r6 80072e4: d004 beq.n 80072f0 <_dtoa_r+0x778> 80072e6: 4659 mov r1, fp 80072e8: 4620 mov r0, r4 80072ea: f000 fd79 bl 8007de0 <__pow5mult> 80072ee: 4683 mov fp, r0 80072f0: 2101 movs r1, #1 80072f2: 4620 mov r0, r4 80072f4: f000 fcd5 bl 8007ca2 <__i2b> 80072f8: 9b0c ldr r3, [sp, #48] ; 0x30 80072fa: 4606 mov r6, r0 80072fc: 2b00 cmp r3, #0 80072fe: f000 81c6 beq.w 800768e <_dtoa_r+0xb16> 8007302: 461a mov r2, r3 8007304: 4601 mov r1, r0 8007306: 4620 mov r0, r4 8007308: f000 fd6a bl 8007de0 <__pow5mult> 800730c: 9b1e ldr r3, [sp, #120] ; 0x78 800730e: 4606 mov r6, r0 8007310: 2b01 cmp r3, #1 8007312: dc3e bgt.n 8007392 <_dtoa_r+0x81a> 8007314: 9b02 ldr r3, [sp, #8] 8007316: 2b00 cmp r3, #0 8007318: d137 bne.n 800738a <_dtoa_r+0x812> 800731a: 9b03 ldr r3, [sp, #12] 800731c: f3c3 0313 ubfx r3, r3, #0, #20 8007320: 2b00 cmp r3, #0 8007322: d134 bne.n 800738e <_dtoa_r+0x816> 8007324: 9b03 ldr r3, [sp, #12] 8007326: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000 800732a: 0d1b lsrs r3, r3, #20 800732c: 051b lsls r3, r3, #20 800732e: b12b cbz r3, 800733c <_dtoa_r+0x7c4> 8007330: 9b07 ldr r3, [sp, #28] 8007332: f109 0901 add.w r9, r9, #1 8007336: 3301 adds r3, #1 8007338: 9307 str r3, [sp, #28] 800733a: 2301 movs r3, #1 800733c: 9308 str r3, [sp, #32] 800733e: 9b0c ldr r3, [sp, #48] ; 0x30 8007340: 2b00 cmp r3, #0 8007342: d128 bne.n 8007396 <_dtoa_r+0x81e> 8007344: 2001 movs r0, #1 8007346: e02e b.n 80073a6 <_dtoa_r+0x82e> 8007348: 9b12 ldr r3, [sp, #72] ; 0x48 800734a: f1c3 0336 rsb r3, r3, #54 ; 0x36 800734e: e796 b.n 800727e <_dtoa_r+0x706> 8007350: 9b08 ldr r3, [sp, #32] 8007352: f108 36ff add.w r6, r8, #4294967295 8007356: 42b3 cmp r3, r6 8007358: bfb7 itett lt 800735a: 9b08 ldrlt r3, [sp, #32] 800735c: 1b9e subge r6, r3, r6 800735e: 1af2 sublt r2, r6, r3 8007360: 9b0c ldrlt r3, [sp, #48] ; 0x30 8007362: bfbf itttt lt 8007364: 9608 strlt r6, [sp, #32] 8007366: 189b addlt r3, r3, r2 8007368: 930c strlt r3, [sp, #48] ; 0x30 800736a: 2600 movlt r6, #0 800736c: f1b8 0f00 cmp.w r8, #0 8007370: bfb9 ittee lt 8007372: eba9 0508 sublt.w r5, r9, r8 8007376: 2300 movlt r3, #0 8007378: 464d movge r5, r9 800737a: 4643 movge r3, r8 800737c: e781 b.n 8007282 <_dtoa_r+0x70a> 800737e: 9e08 ldr r6, [sp, #32] 8007380: 464d mov r5, r9 8007382: 9f09 ldr r7, [sp, #36] ; 0x24 8007384: e786 b.n 8007294 <_dtoa_r+0x71c> 8007386: 9a08 ldr r2, [sp, #32] 8007388: e7ad b.n 80072e6 <_dtoa_r+0x76e> 800738a: 2300 movs r3, #0 800738c: e7d6 b.n 800733c <_dtoa_r+0x7c4> 800738e: 9b02 ldr r3, [sp, #8] 8007390: e7d4 b.n 800733c <_dtoa_r+0x7c4> 8007392: 2300 movs r3, #0 8007394: 9308 str r3, [sp, #32] 8007396: 6933 ldr r3, [r6, #16] 8007398: eb06 0383 add.w r3, r6, r3, lsl #2 800739c: 6918 ldr r0, [r3, #16] 800739e: f000 fc32 bl 8007c06 <__hi0bits> 80073a2: f1c0 0020 rsb r0, r0, #32 80073a6: 9b07 ldr r3, [sp, #28] 80073a8: 4418 add r0, r3 80073aa: f010 001f ands.w r0, r0, #31 80073ae: d047 beq.n 8007440 <_dtoa_r+0x8c8> 80073b0: f1c0 0320 rsb r3, r0, #32 80073b4: 2b04 cmp r3, #4 80073b6: dd3b ble.n 8007430 <_dtoa_r+0x8b8> 80073b8: 9b07 ldr r3, [sp, #28] 80073ba: f1c0 001c rsb r0, r0, #28 80073be: 4481 add r9, r0 80073c0: 4405 add r5, r0 80073c2: 4403 add r3, r0 80073c4: 9307 str r3, [sp, #28] 80073c6: f1b9 0f00 cmp.w r9, #0 80073ca: dd05 ble.n 80073d8 <_dtoa_r+0x860> 80073cc: 4659 mov r1, fp 80073ce: 464a mov r2, r9 80073d0: 4620 mov r0, r4 80073d2: f000 fd53 bl 8007e7c <__lshift> 80073d6: 4683 mov fp, r0 80073d8: 9b07 ldr r3, [sp, #28] 80073da: 2b00 cmp r3, #0 80073dc: dd05 ble.n 80073ea <_dtoa_r+0x872> 80073de: 4631 mov r1, r6 80073e0: 461a mov r2, r3 80073e2: 4620 mov r0, r4 80073e4: f000 fd4a bl 8007e7c <__lshift> 80073e8: 4606 mov r6, r0 80073ea: 9b0d ldr r3, [sp, #52] ; 0x34 80073ec: b353 cbz r3, 8007444 <_dtoa_r+0x8cc> 80073ee: 4631 mov r1, r6 80073f0: 4658 mov r0, fp 80073f2: f000 fd97 bl 8007f24 <__mcmp> 80073f6: 2800 cmp r0, #0 80073f8: da24 bge.n 8007444 <_dtoa_r+0x8cc> 80073fa: 2300 movs r3, #0 80073fc: 4659 mov r1, fp 80073fe: 220a movs r2, #10 8007400: 4620 mov r0, r4 8007402: f000 fbc5 bl 8007b90 <__multadd> 8007406: 9b09 ldr r3, [sp, #36] ; 0x24 8007408: f10a 3aff add.w sl, sl, #4294967295 800740c: 4683 mov fp, r0 800740e: 2b00 cmp r3, #0 8007410: f000 8144 beq.w 800769c <_dtoa_r+0xb24> 8007414: 2300 movs r3, #0 8007416: 4639 mov r1, r7 8007418: 220a movs r2, #10 800741a: 4620 mov r0, r4 800741c: f000 fbb8 bl 8007b90 <__multadd> 8007420: 9b04 ldr r3, [sp, #16] 8007422: 4607 mov r7, r0 8007424: 2b00 cmp r3, #0 8007426: dc4d bgt.n 80074c4 <_dtoa_r+0x94c> 8007428: 9b1e ldr r3, [sp, #120] ; 0x78 800742a: 2b02 cmp r3, #2 800742c: dd4a ble.n 80074c4 <_dtoa_r+0x94c> 800742e: e011 b.n 8007454 <_dtoa_r+0x8dc> 8007430: d0c9 beq.n 80073c6 <_dtoa_r+0x84e> 8007432: 9a07 ldr r2, [sp, #28] 8007434: 331c adds r3, #28 8007436: 441a add r2, r3 8007438: 4499 add r9, r3 800743a: 441d add r5, r3 800743c: 4613 mov r3, r2 800743e: e7c1 b.n 80073c4 <_dtoa_r+0x84c> 8007440: 4603 mov r3, r0 8007442: e7f6 b.n 8007432 <_dtoa_r+0x8ba> 8007444: f1b8 0f00 cmp.w r8, #0 8007448: dc36 bgt.n 80074b8 <_dtoa_r+0x940> 800744a: 9b1e ldr r3, [sp, #120] ; 0x78 800744c: 2b02 cmp r3, #2 800744e: dd33 ble.n 80074b8 <_dtoa_r+0x940> 8007450: f8cd 8010 str.w r8, [sp, #16] 8007454: 9b04 ldr r3, [sp, #16] 8007456: b963 cbnz r3, 8007472 <_dtoa_r+0x8fa> 8007458: 4631 mov r1, r6 800745a: 2205 movs r2, #5 800745c: 4620 mov r0, r4 800745e: f000 fb97 bl 8007b90 <__multadd> 8007462: 4601 mov r1, r0 8007464: 4606 mov r6, r0 8007466: 4658 mov r0, fp 8007468: f000 fd5c bl 8007f24 <__mcmp> 800746c: 2800 cmp r0, #0 800746e: f73f add3 bgt.w 8007018 <_dtoa_r+0x4a0> 8007472: 9b1f ldr r3, [sp, #124] ; 0x7c 8007474: 9d06 ldr r5, [sp, #24] 8007476: ea6f 0a03 mvn.w sl, r3 800747a: f04f 0900 mov.w r9, #0 800747e: 4631 mov r1, r6 8007480: 4620 mov r0, r4 8007482: f000 fb6e bl 8007b62 <_Bfree> 8007486: 2f00 cmp r7, #0 8007488: f43f aebd beq.w 8007206 <_dtoa_r+0x68e> 800748c: f1b9 0f00 cmp.w r9, #0 8007490: d005 beq.n 800749e <_dtoa_r+0x926> 8007492: 45b9 cmp r9, r7 8007494: d003 beq.n 800749e <_dtoa_r+0x926> 8007496: 4649 mov r1, r9 8007498: 4620 mov r0, r4 800749a: f000 fb62 bl 8007b62 <_Bfree> 800749e: 4639 mov r1, r7 80074a0: 4620 mov r0, r4 80074a2: f000 fb5e bl 8007b62 <_Bfree> 80074a6: e6ae b.n 8007206 <_dtoa_r+0x68e> 80074a8: 2600 movs r6, #0 80074aa: 4637 mov r7, r6 80074ac: e7e1 b.n 8007472 <_dtoa_r+0x8fa> 80074ae: 46ba mov sl, r7 80074b0: 4637 mov r7, r6 80074b2: e5b1 b.n 8007018 <_dtoa_r+0x4a0> 80074b4: 40240000 .word 0x40240000 80074b8: 9b09 ldr r3, [sp, #36] ; 0x24 80074ba: f8cd 8010 str.w r8, [sp, #16] 80074be: 2b00 cmp r3, #0 80074c0: f000 80f3 beq.w 80076aa <_dtoa_r+0xb32> 80074c4: 2d00 cmp r5, #0 80074c6: dd05 ble.n 80074d4 <_dtoa_r+0x95c> 80074c8: 4639 mov r1, r7 80074ca: 462a mov r2, r5 80074cc: 4620 mov r0, r4 80074ce: f000 fcd5 bl 8007e7c <__lshift> 80074d2: 4607 mov r7, r0 80074d4: 9b08 ldr r3, [sp, #32] 80074d6: 2b00 cmp r3, #0 80074d8: d04c beq.n 8007574 <_dtoa_r+0x9fc> 80074da: 6879 ldr r1, [r7, #4] 80074dc: 4620 mov r0, r4 80074de: f000 fb0c bl 8007afa <_Balloc> 80074e2: 4605 mov r5, r0 80074e4: 693a ldr r2, [r7, #16] 80074e6: f107 010c add.w r1, r7, #12 80074ea: 3202 adds r2, #2 80074ec: 0092 lsls r2, r2, #2 80074ee: 300c adds r0, #12 80074f0: f000 faf8 bl 8007ae4 80074f4: 2201 movs r2, #1 80074f6: 4629 mov r1, r5 80074f8: 4620 mov r0, r4 80074fa: f000 fcbf bl 8007e7c <__lshift> 80074fe: 46b9 mov r9, r7 8007500: 4607 mov r7, r0 8007502: 9b06 ldr r3, [sp, #24] 8007504: 9307 str r3, [sp, #28] 8007506: 9b02 ldr r3, [sp, #8] 8007508: f003 0301 and.w r3, r3, #1 800750c: 9308 str r3, [sp, #32] 800750e: 4631 mov r1, r6 8007510: 4658 mov r0, fp 8007512: f7ff faa3 bl 8006a5c 8007516: 4649 mov r1, r9 8007518: 4605 mov r5, r0 800751a: f100 0830 add.w r8, r0, #48 ; 0x30 800751e: 4658 mov r0, fp 8007520: f000 fd00 bl 8007f24 <__mcmp> 8007524: 463a mov r2, r7 8007526: 9002 str r0, [sp, #8] 8007528: 4631 mov r1, r6 800752a: 4620 mov r0, r4 800752c: f000 fd14 bl 8007f58 <__mdiff> 8007530: 68c3 ldr r3, [r0, #12] 8007532: 4602 mov r2, r0 8007534: bb03 cbnz r3, 8007578 <_dtoa_r+0xa00> 8007536: 4601 mov r1, r0 8007538: 9009 str r0, [sp, #36] ; 0x24 800753a: 4658 mov r0, fp 800753c: f000 fcf2 bl 8007f24 <__mcmp> 8007540: 4603 mov r3, r0 8007542: 9a09 ldr r2, [sp, #36] ; 0x24 8007544: 4611 mov r1, r2 8007546: 4620 mov r0, r4 8007548: 9309 str r3, [sp, #36] ; 0x24 800754a: f000 fb0a bl 8007b62 <_Bfree> 800754e: 9b09 ldr r3, [sp, #36] ; 0x24 8007550: b9a3 cbnz r3, 800757c <_dtoa_r+0xa04> 8007552: 9a1e ldr r2, [sp, #120] ; 0x78 8007554: b992 cbnz r2, 800757c <_dtoa_r+0xa04> 8007556: 9a08 ldr r2, [sp, #32] 8007558: b982 cbnz r2, 800757c <_dtoa_r+0xa04> 800755a: f1b8 0f39 cmp.w r8, #57 ; 0x39 800755e: d029 beq.n 80075b4 <_dtoa_r+0xa3c> 8007560: 9b02 ldr r3, [sp, #8] 8007562: 2b00 cmp r3, #0 8007564: dd01 ble.n 800756a <_dtoa_r+0x9f2> 8007566: f105 0831 add.w r8, r5, #49 ; 0x31 800756a: 9b07 ldr r3, [sp, #28] 800756c: 1c5d adds r5, r3, #1 800756e: f883 8000 strb.w r8, [r3] 8007572: e784 b.n 800747e <_dtoa_r+0x906> 8007574: 4638 mov r0, r7 8007576: e7c2 b.n 80074fe <_dtoa_r+0x986> 8007578: 2301 movs r3, #1 800757a: e7e3 b.n 8007544 <_dtoa_r+0x9cc> 800757c: 9a02 ldr r2, [sp, #8] 800757e: 2a00 cmp r2, #0 8007580: db04 blt.n 800758c <_dtoa_r+0xa14> 8007582: d123 bne.n 80075cc <_dtoa_r+0xa54> 8007584: 9a1e ldr r2, [sp, #120] ; 0x78 8007586: bb0a cbnz r2, 80075cc <_dtoa_r+0xa54> 8007588: 9a08 ldr r2, [sp, #32] 800758a: b9fa cbnz r2, 80075cc <_dtoa_r+0xa54> 800758c: 2b00 cmp r3, #0 800758e: ddec ble.n 800756a <_dtoa_r+0x9f2> 8007590: 4659 mov r1, fp 8007592: 2201 movs r2, #1 8007594: 4620 mov r0, r4 8007596: f000 fc71 bl 8007e7c <__lshift> 800759a: 4631 mov r1, r6 800759c: 4683 mov fp, r0 800759e: f000 fcc1 bl 8007f24 <__mcmp> 80075a2: 2800 cmp r0, #0 80075a4: dc03 bgt.n 80075ae <_dtoa_r+0xa36> 80075a6: d1e0 bne.n 800756a <_dtoa_r+0x9f2> 80075a8: f018 0f01 tst.w r8, #1 80075ac: d0dd beq.n 800756a <_dtoa_r+0x9f2> 80075ae: f1b8 0f39 cmp.w r8, #57 ; 0x39 80075b2: d1d8 bne.n 8007566 <_dtoa_r+0x9ee> 80075b4: 9b07 ldr r3, [sp, #28] 80075b6: 9a07 ldr r2, [sp, #28] 80075b8: 1c5d adds r5, r3, #1 80075ba: 2339 movs r3, #57 ; 0x39 80075bc: 7013 strb r3, [r2, #0] 80075be: f815 3c01 ldrb.w r3, [r5, #-1] 80075c2: 1e6a subs r2, r5, #1 80075c4: 2b39 cmp r3, #57 ; 0x39 80075c6: d04d beq.n 8007664 <_dtoa_r+0xaec> 80075c8: 3301 adds r3, #1 80075ca: e052 b.n 8007672 <_dtoa_r+0xafa> 80075cc: 9a07 ldr r2, [sp, #28] 80075ce: 2b00 cmp r3, #0 80075d0: f102 0501 add.w r5, r2, #1 80075d4: dd06 ble.n 80075e4 <_dtoa_r+0xa6c> 80075d6: f1b8 0f39 cmp.w r8, #57 ; 0x39 80075da: d0eb beq.n 80075b4 <_dtoa_r+0xa3c> 80075dc: f108 0801 add.w r8, r8, #1 80075e0: 9b07 ldr r3, [sp, #28] 80075e2: e7c4 b.n 800756e <_dtoa_r+0x9f6> 80075e4: 9b06 ldr r3, [sp, #24] 80075e6: 9a04 ldr r2, [sp, #16] 80075e8: 1aeb subs r3, r5, r3 80075ea: 4293 cmp r3, r2 80075ec: f805 8c01 strb.w r8, [r5, #-1] 80075f0: d021 beq.n 8007636 <_dtoa_r+0xabe> 80075f2: 4659 mov r1, fp 80075f4: 2300 movs r3, #0 80075f6: 220a movs r2, #10 80075f8: 4620 mov r0, r4 80075fa: f000 fac9 bl 8007b90 <__multadd> 80075fe: 45b9 cmp r9, r7 8007600: 4683 mov fp, r0 8007602: f04f 0300 mov.w r3, #0 8007606: f04f 020a mov.w r2, #10 800760a: 4649 mov r1, r9 800760c: 4620 mov r0, r4 800760e: d105 bne.n 800761c <_dtoa_r+0xaa4> 8007610: f000 fabe bl 8007b90 <__multadd> 8007614: 4681 mov r9, r0 8007616: 4607 mov r7, r0 8007618: 9507 str r5, [sp, #28] 800761a: e778 b.n 800750e <_dtoa_r+0x996> 800761c: f000 fab8 bl 8007b90 <__multadd> 8007620: 4639 mov r1, r7 8007622: 4681 mov r9, r0 8007624: 2300 movs r3, #0 8007626: 220a movs r2, #10 8007628: 4620 mov r0, r4 800762a: f000 fab1 bl 8007b90 <__multadd> 800762e: 4607 mov r7, r0 8007630: e7f2 b.n 8007618 <_dtoa_r+0xaa0> 8007632: f04f 0900 mov.w r9, #0 8007636: 4659 mov r1, fp 8007638: 2201 movs r2, #1 800763a: 4620 mov r0, r4 800763c: f000 fc1e bl 8007e7c <__lshift> 8007640: 4631 mov r1, r6 8007642: 4683 mov fp, r0 8007644: f000 fc6e bl 8007f24 <__mcmp> 8007648: 2800 cmp r0, #0 800764a: dcb8 bgt.n 80075be <_dtoa_r+0xa46> 800764c: d102 bne.n 8007654 <_dtoa_r+0xadc> 800764e: f018 0f01 tst.w r8, #1 8007652: d1b4 bne.n 80075be <_dtoa_r+0xa46> 8007654: f815 3c01 ldrb.w r3, [r5, #-1] 8007658: 1e6a subs r2, r5, #1 800765a: 2b30 cmp r3, #48 ; 0x30 800765c: f47f af0f bne.w 800747e <_dtoa_r+0x906> 8007660: 4615 mov r5, r2 8007662: e7f7 b.n 8007654 <_dtoa_r+0xadc> 8007664: 9b06 ldr r3, [sp, #24] 8007666: 4293 cmp r3, r2 8007668: d105 bne.n 8007676 <_dtoa_r+0xafe> 800766a: 2331 movs r3, #49 ; 0x31 800766c: 9a06 ldr r2, [sp, #24] 800766e: f10a 0a01 add.w sl, sl, #1 8007672: 7013 strb r3, [r2, #0] 8007674: e703 b.n 800747e <_dtoa_r+0x906> 8007676: 4615 mov r5, r2 8007678: e7a1 b.n 80075be <_dtoa_r+0xa46> 800767a: 4b17 ldr r3, [pc, #92] ; (80076d8 <_dtoa_r+0xb60>) 800767c: f7ff bae1 b.w 8006c42 <_dtoa_r+0xca> 8007680: 9b22 ldr r3, [sp, #136] ; 0x88 8007682: 2b00 cmp r3, #0 8007684: f47f aabb bne.w 8006bfe <_dtoa_r+0x86> 8007688: 4b14 ldr r3, [pc, #80] ; (80076dc <_dtoa_r+0xb64>) 800768a: f7ff bada b.w 8006c42 <_dtoa_r+0xca> 800768e: 9b1e ldr r3, [sp, #120] ; 0x78 8007690: 2b01 cmp r3, #1 8007692: f77f ae3f ble.w 8007314 <_dtoa_r+0x79c> 8007696: 9b0c ldr r3, [sp, #48] ; 0x30 8007698: 9308 str r3, [sp, #32] 800769a: e653 b.n 8007344 <_dtoa_r+0x7cc> 800769c: 9b04 ldr r3, [sp, #16] 800769e: 2b00 cmp r3, #0 80076a0: dc03 bgt.n 80076aa <_dtoa_r+0xb32> 80076a2: 9b1e ldr r3, [sp, #120] ; 0x78 80076a4: 2b02 cmp r3, #2 80076a6: f73f aed5 bgt.w 8007454 <_dtoa_r+0x8dc> 80076aa: 9d06 ldr r5, [sp, #24] 80076ac: 4631 mov r1, r6 80076ae: 4658 mov r0, fp 80076b0: f7ff f9d4 bl 8006a5c 80076b4: 9b06 ldr r3, [sp, #24] 80076b6: f100 0830 add.w r8, r0, #48 ; 0x30 80076ba: f805 8b01 strb.w r8, [r5], #1 80076be: 9a04 ldr r2, [sp, #16] 80076c0: 1aeb subs r3, r5, r3 80076c2: 429a cmp r2, r3 80076c4: ddb5 ble.n 8007632 <_dtoa_r+0xaba> 80076c6: 4659 mov r1, fp 80076c8: 2300 movs r3, #0 80076ca: 220a movs r2, #10 80076cc: 4620 mov r0, r4 80076ce: f000 fa5f bl 8007b90 <__multadd> 80076d2: 4683 mov fp, r0 80076d4: e7ea b.n 80076ac <_dtoa_r+0xb34> 80076d6: bf00 nop 80076d8: 080089bc .word 0x080089bc 80076dc: 080089e0 .word 0x080089e0 080076e0 <__sflush_r>: 80076e0: 898a ldrh r2, [r1, #12] 80076e2: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 80076e6: 4605 mov r5, r0 80076e8: 0710 lsls r0, r2, #28 80076ea: 460c mov r4, r1 80076ec: d458 bmi.n 80077a0 <__sflush_r+0xc0> 80076ee: 684b ldr r3, [r1, #4] 80076f0: 2b00 cmp r3, #0 80076f2: dc05 bgt.n 8007700 <__sflush_r+0x20> 80076f4: 6c0b ldr r3, [r1, #64] ; 0x40 80076f6: 2b00 cmp r3, #0 80076f8: dc02 bgt.n 8007700 <__sflush_r+0x20> 80076fa: 2000 movs r0, #0 80076fc: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8007700: 6ae6 ldr r6, [r4, #44] ; 0x2c 8007702: 2e00 cmp r6, #0 8007704: d0f9 beq.n 80076fa <__sflush_r+0x1a> 8007706: 2300 movs r3, #0 8007708: f412 5280 ands.w r2, r2, #4096 ; 0x1000 800770c: 682f ldr r7, [r5, #0] 800770e: 6a21 ldr r1, [r4, #32] 8007710: 602b str r3, [r5, #0] 8007712: d032 beq.n 800777a <__sflush_r+0x9a> 8007714: 6d60 ldr r0, [r4, #84] ; 0x54 8007716: 89a3 ldrh r3, [r4, #12] 8007718: 075a lsls r2, r3, #29 800771a: d505 bpl.n 8007728 <__sflush_r+0x48> 800771c: 6863 ldr r3, [r4, #4] 800771e: 1ac0 subs r0, r0, r3 8007720: 6b63 ldr r3, [r4, #52] ; 0x34 8007722: b10b cbz r3, 8007728 <__sflush_r+0x48> 8007724: 6c23 ldr r3, [r4, #64] ; 0x40 8007726: 1ac0 subs r0, r0, r3 8007728: 2300 movs r3, #0 800772a: 4602 mov r2, r0 800772c: 6ae6 ldr r6, [r4, #44] ; 0x2c 800772e: 6a21 ldr r1, [r4, #32] 8007730: 4628 mov r0, r5 8007732: 47b0 blx r6 8007734: 1c43 adds r3, r0, #1 8007736: 89a3 ldrh r3, [r4, #12] 8007738: d106 bne.n 8007748 <__sflush_r+0x68> 800773a: 6829 ldr r1, [r5, #0] 800773c: 291d cmp r1, #29 800773e: d848 bhi.n 80077d2 <__sflush_r+0xf2> 8007740: 4a29 ldr r2, [pc, #164] ; (80077e8 <__sflush_r+0x108>) 8007742: 40ca lsrs r2, r1 8007744: 07d6 lsls r6, r2, #31 8007746: d544 bpl.n 80077d2 <__sflush_r+0xf2> 8007748: 2200 movs r2, #0 800774a: 6062 str r2, [r4, #4] 800774c: 6922 ldr r2, [r4, #16] 800774e: 04d9 lsls r1, r3, #19 8007750: 6022 str r2, [r4, #0] 8007752: d504 bpl.n 800775e <__sflush_r+0x7e> 8007754: 1c42 adds r2, r0, #1 8007756: d101 bne.n 800775c <__sflush_r+0x7c> 8007758: 682b ldr r3, [r5, #0] 800775a: b903 cbnz r3, 800775e <__sflush_r+0x7e> 800775c: 6560 str r0, [r4, #84] ; 0x54 800775e: 6b61 ldr r1, [r4, #52] ; 0x34 8007760: 602f str r7, [r5, #0] 8007762: 2900 cmp r1, #0 8007764: d0c9 beq.n 80076fa <__sflush_r+0x1a> 8007766: f104 0344 add.w r3, r4, #68 ; 0x44 800776a: 4299 cmp r1, r3 800776c: d002 beq.n 8007774 <__sflush_r+0x94> 800776e: 4628 mov r0, r5 8007770: f000 fcae bl 80080d0 <_free_r> 8007774: 2000 movs r0, #0 8007776: 6360 str r0, [r4, #52] ; 0x34 8007778: e7c0 b.n 80076fc <__sflush_r+0x1c> 800777a: 2301 movs r3, #1 800777c: 4628 mov r0, r5 800777e: 47b0 blx r6 8007780: 1c41 adds r1, r0, #1 8007782: d1c8 bne.n 8007716 <__sflush_r+0x36> 8007784: 682b ldr r3, [r5, #0] 8007786: 2b00 cmp r3, #0 8007788: d0c5 beq.n 8007716 <__sflush_r+0x36> 800778a: 2b1d cmp r3, #29 800778c: d001 beq.n 8007792 <__sflush_r+0xb2> 800778e: 2b16 cmp r3, #22 8007790: d101 bne.n 8007796 <__sflush_r+0xb6> 8007792: 602f str r7, [r5, #0] 8007794: e7b1 b.n 80076fa <__sflush_r+0x1a> 8007796: 89a3 ldrh r3, [r4, #12] 8007798: f043 0340 orr.w r3, r3, #64 ; 0x40 800779c: 81a3 strh r3, [r4, #12] 800779e: e7ad b.n 80076fc <__sflush_r+0x1c> 80077a0: 690f ldr r7, [r1, #16] 80077a2: 2f00 cmp r7, #0 80077a4: d0a9 beq.n 80076fa <__sflush_r+0x1a> 80077a6: 0793 lsls r3, r2, #30 80077a8: bf18 it ne 80077aa: 2300 movne r3, #0 80077ac: 680e ldr r6, [r1, #0] 80077ae: bf08 it eq 80077b0: 694b ldreq r3, [r1, #20] 80077b2: eba6 0807 sub.w r8, r6, r7 80077b6: 600f str r7, [r1, #0] 80077b8: 608b str r3, [r1, #8] 80077ba: f1b8 0f00 cmp.w r8, #0 80077be: dd9c ble.n 80076fa <__sflush_r+0x1a> 80077c0: 4643 mov r3, r8 80077c2: 463a mov r2, r7 80077c4: 6a21 ldr r1, [r4, #32] 80077c6: 4628 mov r0, r5 80077c8: 6aa6 ldr r6, [r4, #40] ; 0x28 80077ca: 47b0 blx r6 80077cc: 2800 cmp r0, #0 80077ce: dc06 bgt.n 80077de <__sflush_r+0xfe> 80077d0: 89a3 ldrh r3, [r4, #12] 80077d2: f043 0340 orr.w r3, r3, #64 ; 0x40 80077d6: 81a3 strh r3, [r4, #12] 80077d8: f04f 30ff mov.w r0, #4294967295 80077dc: e78e b.n 80076fc <__sflush_r+0x1c> 80077de: 4407 add r7, r0 80077e0: eba8 0800 sub.w r8, r8, r0 80077e4: e7e9 b.n 80077ba <__sflush_r+0xda> 80077e6: bf00 nop 80077e8: 20400001 .word 0x20400001 080077ec <_fflush_r>: 80077ec: b538 push {r3, r4, r5, lr} 80077ee: 690b ldr r3, [r1, #16] 80077f0: 4605 mov r5, r0 80077f2: 460c mov r4, r1 80077f4: b1db cbz r3, 800782e <_fflush_r+0x42> 80077f6: b118 cbz r0, 8007800 <_fflush_r+0x14> 80077f8: 6983 ldr r3, [r0, #24] 80077fa: b90b cbnz r3, 8007800 <_fflush_r+0x14> 80077fc: f000 f860 bl 80078c0 <__sinit> 8007800: 4b0c ldr r3, [pc, #48] ; (8007834 <_fflush_r+0x48>) 8007802: 429c cmp r4, r3 8007804: d109 bne.n 800781a <_fflush_r+0x2e> 8007806: 686c ldr r4, [r5, #4] 8007808: f9b4 300c ldrsh.w r3, [r4, #12] 800780c: b17b cbz r3, 800782e <_fflush_r+0x42> 800780e: 4621 mov r1, r4 8007810: 4628 mov r0, r5 8007812: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 8007816: f7ff bf63 b.w 80076e0 <__sflush_r> 800781a: 4b07 ldr r3, [pc, #28] ; (8007838 <_fflush_r+0x4c>) 800781c: 429c cmp r4, r3 800781e: d101 bne.n 8007824 <_fflush_r+0x38> 8007820: 68ac ldr r4, [r5, #8] 8007822: e7f1 b.n 8007808 <_fflush_r+0x1c> 8007824: 4b05 ldr r3, [pc, #20] ; (800783c <_fflush_r+0x50>) 8007826: 429c cmp r4, r3 8007828: bf08 it eq 800782a: 68ec ldreq r4, [r5, #12] 800782c: e7ec b.n 8007808 <_fflush_r+0x1c> 800782e: 2000 movs r0, #0 8007830: bd38 pop {r3, r4, r5, pc} 8007832: bf00 nop 8007834: 08008a10 .word 0x08008a10 8007838: 08008a30 .word 0x08008a30 800783c: 080089f0 .word 0x080089f0 08007840 : 8007840: 2300 movs r3, #0 8007842: b510 push {r4, lr} 8007844: 4604 mov r4, r0 8007846: e9c0 3300 strd r3, r3, [r0] 800784a: 6083 str r3, [r0, #8] 800784c: 8181 strh r1, [r0, #12] 800784e: 6643 str r3, [r0, #100] ; 0x64 8007850: 81c2 strh r2, [r0, #14] 8007852: e9c0 3304 strd r3, r3, [r0, #16] 8007856: 6183 str r3, [r0, #24] 8007858: 4619 mov r1, r3 800785a: 2208 movs r2, #8 800785c: 305c adds r0, #92 ; 0x5c 800785e: f7fe fab3 bl 8005dc8 8007862: 4b05 ldr r3, [pc, #20] ; (8007878 ) 8007864: 6224 str r4, [r4, #32] 8007866: 6263 str r3, [r4, #36] ; 0x24 8007868: 4b04 ldr r3, [pc, #16] ; (800787c ) 800786a: 62a3 str r3, [r4, #40] ; 0x28 800786c: 4b04 ldr r3, [pc, #16] ; (8007880 ) 800786e: 62e3 str r3, [r4, #44] ; 0x2c 8007870: 4b04 ldr r3, [pc, #16] ; (8007884 ) 8007872: 6323 str r3, [r4, #48] ; 0x30 8007874: bd10 pop {r4, pc} 8007876: bf00 nop 8007878: 080084b9 .word 0x080084b9 800787c: 080084db .word 0x080084db 8007880: 08008513 .word 0x08008513 8007884: 08008537 .word 0x08008537 08007888 <_cleanup_r>: 8007888: 4901 ldr r1, [pc, #4] ; (8007890 <_cleanup_r+0x8>) 800788a: f000 b885 b.w 8007998 <_fwalk_reent> 800788e: bf00 nop 8007890: 080077ed .word 0x080077ed 08007894 <__sfmoreglue>: 8007894: b570 push {r4, r5, r6, lr} 8007896: 2568 movs r5, #104 ; 0x68 8007898: 1e4a subs r2, r1, #1 800789a: 4355 muls r5, r2 800789c: 460e mov r6, r1 800789e: f105 0174 add.w r1, r5, #116 ; 0x74 80078a2: f000 fc61 bl 8008168 <_malloc_r> 80078a6: 4604 mov r4, r0 80078a8: b140 cbz r0, 80078bc <__sfmoreglue+0x28> 80078aa: 2100 movs r1, #0 80078ac: e9c0 1600 strd r1, r6, [r0] 80078b0: 300c adds r0, #12 80078b2: 60a0 str r0, [r4, #8] 80078b4: f105 0268 add.w r2, r5, #104 ; 0x68 80078b8: f7fe fa86 bl 8005dc8 80078bc: 4620 mov r0, r4 80078be: bd70 pop {r4, r5, r6, pc} 080078c0 <__sinit>: 80078c0: 6983 ldr r3, [r0, #24] 80078c2: b510 push {r4, lr} 80078c4: 4604 mov r4, r0 80078c6: bb33 cbnz r3, 8007916 <__sinit+0x56> 80078c8: e9c0 3312 strd r3, r3, [r0, #72] ; 0x48 80078cc: 6503 str r3, [r0, #80] ; 0x50 80078ce: 4b12 ldr r3, [pc, #72] ; (8007918 <__sinit+0x58>) 80078d0: 4a12 ldr r2, [pc, #72] ; (800791c <__sinit+0x5c>) 80078d2: 681b ldr r3, [r3, #0] 80078d4: 6282 str r2, [r0, #40] ; 0x28 80078d6: 4298 cmp r0, r3 80078d8: bf04 itt eq 80078da: 2301 moveq r3, #1 80078dc: 6183 streq r3, [r0, #24] 80078de: f000 f81f bl 8007920 <__sfp> 80078e2: 6060 str r0, [r4, #4] 80078e4: 4620 mov r0, r4 80078e6: f000 f81b bl 8007920 <__sfp> 80078ea: 60a0 str r0, [r4, #8] 80078ec: 4620 mov r0, r4 80078ee: f000 f817 bl 8007920 <__sfp> 80078f2: 2200 movs r2, #0 80078f4: 60e0 str r0, [r4, #12] 80078f6: 2104 movs r1, #4 80078f8: 6860 ldr r0, [r4, #4] 80078fa: f7ff ffa1 bl 8007840 80078fe: 2201 movs r2, #1 8007900: 2109 movs r1, #9 8007902: 68a0 ldr r0, [r4, #8] 8007904: f7ff ff9c bl 8007840 8007908: 2202 movs r2, #2 800790a: 2112 movs r1, #18 800790c: 68e0 ldr r0, [r4, #12] 800790e: f7ff ff97 bl 8007840 8007912: 2301 movs r3, #1 8007914: 61a3 str r3, [r4, #24] 8007916: bd10 pop {r4, pc} 8007918: 080089a8 .word 0x080089a8 800791c: 08007889 .word 0x08007889 08007920 <__sfp>: 8007920: b5f8 push {r3, r4, r5, r6, r7, lr} 8007922: 4b1b ldr r3, [pc, #108] ; (8007990 <__sfp+0x70>) 8007924: 4607 mov r7, r0 8007926: 681e ldr r6, [r3, #0] 8007928: 69b3 ldr r3, [r6, #24] 800792a: b913 cbnz r3, 8007932 <__sfp+0x12> 800792c: 4630 mov r0, r6 800792e: f7ff ffc7 bl 80078c0 <__sinit> 8007932: 3648 adds r6, #72 ; 0x48 8007934: e9d6 3401 ldrd r3, r4, [r6, #4] 8007938: 3b01 subs r3, #1 800793a: d503 bpl.n 8007944 <__sfp+0x24> 800793c: 6833 ldr r3, [r6, #0] 800793e: b133 cbz r3, 800794e <__sfp+0x2e> 8007940: 6836 ldr r6, [r6, #0] 8007942: e7f7 b.n 8007934 <__sfp+0x14> 8007944: f9b4 500c ldrsh.w r5, [r4, #12] 8007948: b16d cbz r5, 8007966 <__sfp+0x46> 800794a: 3468 adds r4, #104 ; 0x68 800794c: e7f4 b.n 8007938 <__sfp+0x18> 800794e: 2104 movs r1, #4 8007950: 4638 mov r0, r7 8007952: f7ff ff9f bl 8007894 <__sfmoreglue> 8007956: 6030 str r0, [r6, #0] 8007958: 2800 cmp r0, #0 800795a: d1f1 bne.n 8007940 <__sfp+0x20> 800795c: 230c movs r3, #12 800795e: 4604 mov r4, r0 8007960: 603b str r3, [r7, #0] 8007962: 4620 mov r0, r4 8007964: bdf8 pop {r3, r4, r5, r6, r7, pc} 8007966: 4b0b ldr r3, [pc, #44] ; (8007994 <__sfp+0x74>) 8007968: 6665 str r5, [r4, #100] ; 0x64 800796a: e9c4 5500 strd r5, r5, [r4] 800796e: 60a5 str r5, [r4, #8] 8007970: e9c4 3503 strd r3, r5, [r4, #12] 8007974: e9c4 5505 strd r5, r5, [r4, #20] 8007978: 2208 movs r2, #8 800797a: 4629 mov r1, r5 800797c: f104 005c add.w r0, r4, #92 ; 0x5c 8007980: f7fe fa22 bl 8005dc8 8007984: e9c4 550d strd r5, r5, [r4, #52] ; 0x34 8007988: e9c4 5512 strd r5, r5, [r4, #72] ; 0x48 800798c: e7e9 b.n 8007962 <__sfp+0x42> 800798e: bf00 nop 8007990: 080089a8 .word 0x080089a8 8007994: ffff0001 .word 0xffff0001 08007998 <_fwalk_reent>: 8007998: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 800799c: 4680 mov r8, r0 800799e: 4689 mov r9, r1 80079a0: 2600 movs r6, #0 80079a2: f100 0448 add.w r4, r0, #72 ; 0x48 80079a6: b914 cbnz r4, 80079ae <_fwalk_reent+0x16> 80079a8: 4630 mov r0, r6 80079aa: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 80079ae: e9d4 7501 ldrd r7, r5, [r4, #4] 80079b2: 3f01 subs r7, #1 80079b4: d501 bpl.n 80079ba <_fwalk_reent+0x22> 80079b6: 6824 ldr r4, [r4, #0] 80079b8: e7f5 b.n 80079a6 <_fwalk_reent+0xe> 80079ba: 89ab ldrh r3, [r5, #12] 80079bc: 2b01 cmp r3, #1 80079be: d907 bls.n 80079d0 <_fwalk_reent+0x38> 80079c0: f9b5 300e ldrsh.w r3, [r5, #14] 80079c4: 3301 adds r3, #1 80079c6: d003 beq.n 80079d0 <_fwalk_reent+0x38> 80079c8: 4629 mov r1, r5 80079ca: 4640 mov r0, r8 80079cc: 47c8 blx r9 80079ce: 4306 orrs r6, r0 80079d0: 3568 adds r5, #104 ; 0x68 80079d2: e7ee b.n 80079b2 <_fwalk_reent+0x1a> 080079d4 <_localeconv_r>: 80079d4: 4b04 ldr r3, [pc, #16] ; (80079e8 <_localeconv_r+0x14>) 80079d6: 681b ldr r3, [r3, #0] 80079d8: 6a18 ldr r0, [r3, #32] 80079da: 4b04 ldr r3, [pc, #16] ; (80079ec <_localeconv_r+0x18>) 80079dc: 2800 cmp r0, #0 80079de: bf08 it eq 80079e0: 4618 moveq r0, r3 80079e2: 30f0 adds r0, #240 ; 0xf0 80079e4: 4770 bx lr 80079e6: bf00 nop 80079e8: 2000000c .word 0x2000000c 80079ec: 20000070 .word 0x20000070 080079f0 <__swhatbuf_r>: 80079f0: b570 push {r4, r5, r6, lr} 80079f2: 460e mov r6, r1 80079f4: f9b1 100e ldrsh.w r1, [r1, #14] 80079f8: b096 sub sp, #88 ; 0x58 80079fa: 2900 cmp r1, #0 80079fc: 4614 mov r4, r2 80079fe: 461d mov r5, r3 8007a00: da07 bge.n 8007a12 <__swhatbuf_r+0x22> 8007a02: 2300 movs r3, #0 8007a04: 602b str r3, [r5, #0] 8007a06: 89b3 ldrh r3, [r6, #12] 8007a08: 061a lsls r2, r3, #24 8007a0a: d410 bmi.n 8007a2e <__swhatbuf_r+0x3e> 8007a0c: f44f 6380 mov.w r3, #1024 ; 0x400 8007a10: e00e b.n 8007a30 <__swhatbuf_r+0x40> 8007a12: 466a mov r2, sp 8007a14: f000 fdb6 bl 8008584 <_fstat_r> 8007a18: 2800 cmp r0, #0 8007a1a: dbf2 blt.n 8007a02 <__swhatbuf_r+0x12> 8007a1c: 9a01 ldr r2, [sp, #4] 8007a1e: f402 4270 and.w r2, r2, #61440 ; 0xf000 8007a22: f5a2 5300 sub.w r3, r2, #8192 ; 0x2000 8007a26: 425a negs r2, r3 8007a28: 415a adcs r2, r3 8007a2a: 602a str r2, [r5, #0] 8007a2c: e7ee b.n 8007a0c <__swhatbuf_r+0x1c> 8007a2e: 2340 movs r3, #64 ; 0x40 8007a30: 2000 movs r0, #0 8007a32: 6023 str r3, [r4, #0] 8007a34: b016 add sp, #88 ; 0x58 8007a36: bd70 pop {r4, r5, r6, pc} 08007a38 <__smakebuf_r>: 8007a38: 898b ldrh r3, [r1, #12] 8007a3a: b573 push {r0, r1, r4, r5, r6, lr} 8007a3c: 079d lsls r5, r3, #30 8007a3e: 4606 mov r6, r0 8007a40: 460c mov r4, r1 8007a42: d507 bpl.n 8007a54 <__smakebuf_r+0x1c> 8007a44: f104 0347 add.w r3, r4, #71 ; 0x47 8007a48: 6023 str r3, [r4, #0] 8007a4a: 6123 str r3, [r4, #16] 8007a4c: 2301 movs r3, #1 8007a4e: 6163 str r3, [r4, #20] 8007a50: b002 add sp, #8 8007a52: bd70 pop {r4, r5, r6, pc} 8007a54: ab01 add r3, sp, #4 8007a56: 466a mov r2, sp 8007a58: f7ff ffca bl 80079f0 <__swhatbuf_r> 8007a5c: 9900 ldr r1, [sp, #0] 8007a5e: 4605 mov r5, r0 8007a60: 4630 mov r0, r6 8007a62: f000 fb81 bl 8008168 <_malloc_r> 8007a66: b948 cbnz r0, 8007a7c <__smakebuf_r+0x44> 8007a68: f9b4 300c ldrsh.w r3, [r4, #12] 8007a6c: 059a lsls r2, r3, #22 8007a6e: d4ef bmi.n 8007a50 <__smakebuf_r+0x18> 8007a70: f023 0303 bic.w r3, r3, #3 8007a74: f043 0302 orr.w r3, r3, #2 8007a78: 81a3 strh r3, [r4, #12] 8007a7a: e7e3 b.n 8007a44 <__smakebuf_r+0xc> 8007a7c: 4b0d ldr r3, [pc, #52] ; (8007ab4 <__smakebuf_r+0x7c>) 8007a7e: 62b3 str r3, [r6, #40] ; 0x28 8007a80: 89a3 ldrh r3, [r4, #12] 8007a82: 6020 str r0, [r4, #0] 8007a84: f043 0380 orr.w r3, r3, #128 ; 0x80 8007a88: 81a3 strh r3, [r4, #12] 8007a8a: 9b00 ldr r3, [sp, #0] 8007a8c: 6120 str r0, [r4, #16] 8007a8e: 6163 str r3, [r4, #20] 8007a90: 9b01 ldr r3, [sp, #4] 8007a92: b15b cbz r3, 8007aac <__smakebuf_r+0x74> 8007a94: f9b4 100e ldrsh.w r1, [r4, #14] 8007a98: 4630 mov r0, r6 8007a9a: f000 fd85 bl 80085a8 <_isatty_r> 8007a9e: b128 cbz r0, 8007aac <__smakebuf_r+0x74> 8007aa0: 89a3 ldrh r3, [r4, #12] 8007aa2: f023 0303 bic.w r3, r3, #3 8007aa6: f043 0301 orr.w r3, r3, #1 8007aaa: 81a3 strh r3, [r4, #12] 8007aac: 89a3 ldrh r3, [r4, #12] 8007aae: 431d orrs r5, r3 8007ab0: 81a5 strh r5, [r4, #12] 8007ab2: e7cd b.n 8007a50 <__smakebuf_r+0x18> 8007ab4: 08007889 .word 0x08007889 08007ab8 : 8007ab8: 4b02 ldr r3, [pc, #8] ; (8007ac4 ) 8007aba: 4601 mov r1, r0 8007abc: 6818 ldr r0, [r3, #0] 8007abe: f000 bb53 b.w 8008168 <_malloc_r> 8007ac2: bf00 nop 8007ac4: 2000000c .word 0x2000000c 08007ac8 : 8007ac8: b510 push {r4, lr} 8007aca: b2c9 uxtb r1, r1 8007acc: 4402 add r2, r0 8007ace: 4290 cmp r0, r2 8007ad0: 4603 mov r3, r0 8007ad2: d101 bne.n 8007ad8 8007ad4: 2300 movs r3, #0 8007ad6: e003 b.n 8007ae0 8007ad8: 781c ldrb r4, [r3, #0] 8007ada: 3001 adds r0, #1 8007adc: 428c cmp r4, r1 8007ade: d1f6 bne.n 8007ace 8007ae0: 4618 mov r0, r3 8007ae2: bd10 pop {r4, pc} 08007ae4 : 8007ae4: b510 push {r4, lr} 8007ae6: 1e43 subs r3, r0, #1 8007ae8: 440a add r2, r1 8007aea: 4291 cmp r1, r2 8007aec: d100 bne.n 8007af0 8007aee: bd10 pop {r4, pc} 8007af0: f811 4b01 ldrb.w r4, [r1], #1 8007af4: f803 4f01 strb.w r4, [r3, #1]! 8007af8: e7f7 b.n 8007aea 08007afa <_Balloc>: 8007afa: b570 push {r4, r5, r6, lr} 8007afc: 6a45 ldr r5, [r0, #36] ; 0x24 8007afe: 4604 mov r4, r0 8007b00: 460e mov r6, r1 8007b02: b93d cbnz r5, 8007b14 <_Balloc+0x1a> 8007b04: 2010 movs r0, #16 8007b06: f7ff ffd7 bl 8007ab8 8007b0a: 6260 str r0, [r4, #36] ; 0x24 8007b0c: e9c0 5501 strd r5, r5, [r0, #4] 8007b10: 6005 str r5, [r0, #0] 8007b12: 60c5 str r5, [r0, #12] 8007b14: 6a65 ldr r5, [r4, #36] ; 0x24 8007b16: 68eb ldr r3, [r5, #12] 8007b18: b183 cbz r3, 8007b3c <_Balloc+0x42> 8007b1a: 6a63 ldr r3, [r4, #36] ; 0x24 8007b1c: 68db ldr r3, [r3, #12] 8007b1e: f853 0026 ldr.w r0, [r3, r6, lsl #2] 8007b22: b9b8 cbnz r0, 8007b54 <_Balloc+0x5a> 8007b24: 2101 movs r1, #1 8007b26: fa01 f506 lsl.w r5, r1, r6 8007b2a: 1d6a adds r2, r5, #5 8007b2c: 0092 lsls r2, r2, #2 8007b2e: 4620 mov r0, r4 8007b30: f000 fabf bl 80080b2 <_calloc_r> 8007b34: b160 cbz r0, 8007b50 <_Balloc+0x56> 8007b36: e9c0 6501 strd r6, r5, [r0, #4] 8007b3a: e00e b.n 8007b5a <_Balloc+0x60> 8007b3c: 2221 movs r2, #33 ; 0x21 8007b3e: 2104 movs r1, #4 8007b40: 4620 mov r0, r4 8007b42: f000 fab6 bl 80080b2 <_calloc_r> 8007b46: 6a63 ldr r3, [r4, #36] ; 0x24 8007b48: 60e8 str r0, [r5, #12] 8007b4a: 68db ldr r3, [r3, #12] 8007b4c: 2b00 cmp r3, #0 8007b4e: d1e4 bne.n 8007b1a <_Balloc+0x20> 8007b50: 2000 movs r0, #0 8007b52: bd70 pop {r4, r5, r6, pc} 8007b54: 6802 ldr r2, [r0, #0] 8007b56: f843 2026 str.w r2, [r3, r6, lsl #2] 8007b5a: 2300 movs r3, #0 8007b5c: e9c0 3303 strd r3, r3, [r0, #12] 8007b60: e7f7 b.n 8007b52 <_Balloc+0x58> 08007b62 <_Bfree>: 8007b62: b570 push {r4, r5, r6, lr} 8007b64: 6a44 ldr r4, [r0, #36] ; 0x24 8007b66: 4606 mov r6, r0 8007b68: 460d mov r5, r1 8007b6a: b93c cbnz r4, 8007b7c <_Bfree+0x1a> 8007b6c: 2010 movs r0, #16 8007b6e: f7ff ffa3 bl 8007ab8 8007b72: 6270 str r0, [r6, #36] ; 0x24 8007b74: e9c0 4401 strd r4, r4, [r0, #4] 8007b78: 6004 str r4, [r0, #0] 8007b7a: 60c4 str r4, [r0, #12] 8007b7c: b13d cbz r5, 8007b8e <_Bfree+0x2c> 8007b7e: 6a73 ldr r3, [r6, #36] ; 0x24 8007b80: 686a ldr r2, [r5, #4] 8007b82: 68db ldr r3, [r3, #12] 8007b84: f853 1022 ldr.w r1, [r3, r2, lsl #2] 8007b88: 6029 str r1, [r5, #0] 8007b8a: f843 5022 str.w r5, [r3, r2, lsl #2] 8007b8e: bd70 pop {r4, r5, r6, pc} 08007b90 <__multadd>: 8007b90: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 8007b94: 461f mov r7, r3 8007b96: 4606 mov r6, r0 8007b98: 460c mov r4, r1 8007b9a: 2300 movs r3, #0 8007b9c: 690d ldr r5, [r1, #16] 8007b9e: f101 0c14 add.w ip, r1, #20 8007ba2: f8dc 0000 ldr.w r0, [ip] 8007ba6: 3301 adds r3, #1 8007ba8: b281 uxth r1, r0 8007baa: fb02 7101 mla r1, r2, r1, r7 8007bae: 0c00 lsrs r0, r0, #16 8007bb0: 0c0f lsrs r7, r1, #16 8007bb2: fb02 7000 mla r0, r2, r0, r7 8007bb6: b289 uxth r1, r1 8007bb8: eb01 4100 add.w r1, r1, r0, lsl #16 8007bbc: 429d cmp r5, r3 8007bbe: ea4f 4710 mov.w r7, r0, lsr #16 8007bc2: f84c 1b04 str.w r1, [ip], #4 8007bc6: dcec bgt.n 8007ba2 <__multadd+0x12> 8007bc8: b1d7 cbz r7, 8007c00 <__multadd+0x70> 8007bca: 68a3 ldr r3, [r4, #8] 8007bcc: 42ab cmp r3, r5 8007bce: dc12 bgt.n 8007bf6 <__multadd+0x66> 8007bd0: 6861 ldr r1, [r4, #4] 8007bd2: 4630 mov r0, r6 8007bd4: 3101 adds r1, #1 8007bd6: f7ff ff90 bl 8007afa <_Balloc> 8007bda: 4680 mov r8, r0 8007bdc: 6922 ldr r2, [r4, #16] 8007bde: f104 010c add.w r1, r4, #12 8007be2: 3202 adds r2, #2 8007be4: 0092 lsls r2, r2, #2 8007be6: 300c adds r0, #12 8007be8: f7ff ff7c bl 8007ae4 8007bec: 4621 mov r1, r4 8007bee: 4630 mov r0, r6 8007bf0: f7ff ffb7 bl 8007b62 <_Bfree> 8007bf4: 4644 mov r4, r8 8007bf6: eb04 0385 add.w r3, r4, r5, lsl #2 8007bfa: 3501 adds r5, #1 8007bfc: 615f str r7, [r3, #20] 8007bfe: 6125 str r5, [r4, #16] 8007c00: 4620 mov r0, r4 8007c02: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 08007c06 <__hi0bits>: 8007c06: 0c02 lsrs r2, r0, #16 8007c08: 0412 lsls r2, r2, #16 8007c0a: 4603 mov r3, r0 8007c0c: b9b2 cbnz r2, 8007c3c <__hi0bits+0x36> 8007c0e: 0403 lsls r3, r0, #16 8007c10: 2010 movs r0, #16 8007c12: f013 4f7f tst.w r3, #4278190080 ; 0xff000000 8007c16: bf04 itt eq 8007c18: 021b lsleq r3, r3, #8 8007c1a: 3008 addeq r0, #8 8007c1c: f013 4f70 tst.w r3, #4026531840 ; 0xf0000000 8007c20: bf04 itt eq 8007c22: 011b lsleq r3, r3, #4 8007c24: 3004 addeq r0, #4 8007c26: f013 4f40 tst.w r3, #3221225472 ; 0xc0000000 8007c2a: bf04 itt eq 8007c2c: 009b lsleq r3, r3, #2 8007c2e: 3002 addeq r0, #2 8007c30: 2b00 cmp r3, #0 8007c32: db06 blt.n 8007c42 <__hi0bits+0x3c> 8007c34: 005b lsls r3, r3, #1 8007c36: d503 bpl.n 8007c40 <__hi0bits+0x3a> 8007c38: 3001 adds r0, #1 8007c3a: 4770 bx lr 8007c3c: 2000 movs r0, #0 8007c3e: e7e8 b.n 8007c12 <__hi0bits+0xc> 8007c40: 2020 movs r0, #32 8007c42: 4770 bx lr 08007c44 <__lo0bits>: 8007c44: 6803 ldr r3, [r0, #0] 8007c46: 4601 mov r1, r0 8007c48: f013 0207 ands.w r2, r3, #7 8007c4c: d00b beq.n 8007c66 <__lo0bits+0x22> 8007c4e: 07da lsls r2, r3, #31 8007c50: d423 bmi.n 8007c9a <__lo0bits+0x56> 8007c52: 0798 lsls r0, r3, #30 8007c54: bf49 itett mi 8007c56: 085b lsrmi r3, r3, #1 8007c58: 089b lsrpl r3, r3, #2 8007c5a: 2001 movmi r0, #1 8007c5c: 600b strmi r3, [r1, #0] 8007c5e: bf5c itt pl 8007c60: 600b strpl r3, [r1, #0] 8007c62: 2002 movpl r0, #2 8007c64: 4770 bx lr 8007c66: b298 uxth r0, r3 8007c68: b9a8 cbnz r0, 8007c96 <__lo0bits+0x52> 8007c6a: 2010 movs r0, #16 8007c6c: 0c1b lsrs r3, r3, #16 8007c6e: f013 0fff tst.w r3, #255 ; 0xff 8007c72: bf04 itt eq 8007c74: 0a1b lsreq r3, r3, #8 8007c76: 3008 addeq r0, #8 8007c78: 071a lsls r2, r3, #28 8007c7a: bf04 itt eq 8007c7c: 091b lsreq r3, r3, #4 8007c7e: 3004 addeq r0, #4 8007c80: 079a lsls r2, r3, #30 8007c82: bf04 itt eq 8007c84: 089b lsreq r3, r3, #2 8007c86: 3002 addeq r0, #2 8007c88: 07da lsls r2, r3, #31 8007c8a: d402 bmi.n 8007c92 <__lo0bits+0x4e> 8007c8c: 085b lsrs r3, r3, #1 8007c8e: d006 beq.n 8007c9e <__lo0bits+0x5a> 8007c90: 3001 adds r0, #1 8007c92: 600b str r3, [r1, #0] 8007c94: 4770 bx lr 8007c96: 4610 mov r0, r2 8007c98: e7e9 b.n 8007c6e <__lo0bits+0x2a> 8007c9a: 2000 movs r0, #0 8007c9c: 4770 bx lr 8007c9e: 2020 movs r0, #32 8007ca0: 4770 bx lr 08007ca2 <__i2b>: 8007ca2: b510 push {r4, lr} 8007ca4: 460c mov r4, r1 8007ca6: 2101 movs r1, #1 8007ca8: f7ff ff27 bl 8007afa <_Balloc> 8007cac: 2201 movs r2, #1 8007cae: 6144 str r4, [r0, #20] 8007cb0: 6102 str r2, [r0, #16] 8007cb2: bd10 pop {r4, pc} 08007cb4 <__multiply>: 8007cb4: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} 8007cb8: 4614 mov r4, r2 8007cba: 690a ldr r2, [r1, #16] 8007cbc: 6923 ldr r3, [r4, #16] 8007cbe: 4688 mov r8, r1 8007cc0: 429a cmp r2, r3 8007cc2: bfbe ittt lt 8007cc4: 460b movlt r3, r1 8007cc6: 46a0 movlt r8, r4 8007cc8: 461c movlt r4, r3 8007cca: f8d8 7010 ldr.w r7, [r8, #16] 8007cce: f8d4 9010 ldr.w r9, [r4, #16] 8007cd2: f8d8 3008 ldr.w r3, [r8, #8] 8007cd6: f8d8 1004 ldr.w r1, [r8, #4] 8007cda: eb07 0609 add.w r6, r7, r9 8007cde: 42b3 cmp r3, r6 8007ce0: bfb8 it lt 8007ce2: 3101 addlt r1, #1 8007ce4: f7ff ff09 bl 8007afa <_Balloc> 8007ce8: f100 0514 add.w r5, r0, #20 8007cec: 462b mov r3, r5 8007cee: 2200 movs r2, #0 8007cf0: eb05 0e86 add.w lr, r5, r6, lsl #2 8007cf4: 4573 cmp r3, lr 8007cf6: d316 bcc.n 8007d26 <__multiply+0x72> 8007cf8: f104 0214 add.w r2, r4, #20 8007cfc: f108 0114 add.w r1, r8, #20 8007d00: eb02 0389 add.w r3, r2, r9, lsl #2 8007d04: eb01 0787 add.w r7, r1, r7, lsl #2 8007d08: 9300 str r3, [sp, #0] 8007d0a: 9b00 ldr r3, [sp, #0] 8007d0c: 9201 str r2, [sp, #4] 8007d0e: 4293 cmp r3, r2 8007d10: d80c bhi.n 8007d2c <__multiply+0x78> 8007d12: 2e00 cmp r6, #0 8007d14: dd03 ble.n 8007d1e <__multiply+0x6a> 8007d16: f85e 3d04 ldr.w r3, [lr, #-4]! 8007d1a: 2b00 cmp r3, #0 8007d1c: d05d beq.n 8007dda <__multiply+0x126> 8007d1e: 6106 str r6, [r0, #16] 8007d20: b003 add sp, #12 8007d22: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8007d26: f843 2b04 str.w r2, [r3], #4 8007d2a: e7e3 b.n 8007cf4 <__multiply+0x40> 8007d2c: f8b2 b000 ldrh.w fp, [r2] 8007d30: f1bb 0f00 cmp.w fp, #0 8007d34: d023 beq.n 8007d7e <__multiply+0xca> 8007d36: 4689 mov r9, r1 8007d38: 46ac mov ip, r5 8007d3a: f04f 0800 mov.w r8, #0 8007d3e: f859 4b04 ldr.w r4, [r9], #4 8007d42: f8dc a000 ldr.w sl, [ip] 8007d46: b2a3 uxth r3, r4 8007d48: fa1f fa8a uxth.w sl, sl 8007d4c: fb0b a303 mla r3, fp, r3, sl 8007d50: ea4f 4a14 mov.w sl, r4, lsr #16 8007d54: f8dc 4000 ldr.w r4, [ip] 8007d58: 4443 add r3, r8 8007d5a: ea4f 4814 mov.w r8, r4, lsr #16 8007d5e: fb0b 840a mla r4, fp, sl, r8 8007d62: 46e2 mov sl, ip 8007d64: eb04 4413 add.w r4, r4, r3, lsr #16 8007d68: b29b uxth r3, r3 8007d6a: ea43 4304 orr.w r3, r3, r4, lsl #16 8007d6e: 454f cmp r7, r9 8007d70: ea4f 4814 mov.w r8, r4, lsr #16 8007d74: f84a 3b04 str.w r3, [sl], #4 8007d78: d82b bhi.n 8007dd2 <__multiply+0x11e> 8007d7a: f8cc 8004 str.w r8, [ip, #4] 8007d7e: 9b01 ldr r3, [sp, #4] 8007d80: 3204 adds r2, #4 8007d82: f8b3 a002 ldrh.w sl, [r3, #2] 8007d86: f1ba 0f00 cmp.w sl, #0 8007d8a: d020 beq.n 8007dce <__multiply+0x11a> 8007d8c: 4689 mov r9, r1 8007d8e: 46a8 mov r8, r5 8007d90: f04f 0b00 mov.w fp, #0 8007d94: 682b ldr r3, [r5, #0] 8007d96: f8b9 c000 ldrh.w ip, [r9] 8007d9a: f8b8 4002 ldrh.w r4, [r8, #2] 8007d9e: b29b uxth r3, r3 8007da0: fb0a 440c mla r4, sl, ip, r4 8007da4: 46c4 mov ip, r8 8007da6: 445c add r4, fp 8007da8: ea43 4304 orr.w r3, r3, r4, lsl #16 8007dac: f84c 3b04 str.w r3, [ip], #4 8007db0: f859 3b04 ldr.w r3, [r9], #4 8007db4: f8b8 b004 ldrh.w fp, [r8, #4] 8007db8: 0c1b lsrs r3, r3, #16 8007dba: fb0a b303 mla r3, sl, r3, fp 8007dbe: 454f cmp r7, r9 8007dc0: eb03 4314 add.w r3, r3, r4, lsr #16 8007dc4: ea4f 4b13 mov.w fp, r3, lsr #16 8007dc8: d805 bhi.n 8007dd6 <__multiply+0x122> 8007dca: f8c8 3004 str.w r3, [r8, #4] 8007dce: 3504 adds r5, #4 8007dd0: e79b b.n 8007d0a <__multiply+0x56> 8007dd2: 46d4 mov ip, sl 8007dd4: e7b3 b.n 8007d3e <__multiply+0x8a> 8007dd6: 46e0 mov r8, ip 8007dd8: e7dd b.n 8007d96 <__multiply+0xe2> 8007dda: 3e01 subs r6, #1 8007ddc: e799 b.n 8007d12 <__multiply+0x5e> ... 08007de0 <__pow5mult>: 8007de0: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 8007de4: 4615 mov r5, r2 8007de6: f012 0203 ands.w r2, r2, #3 8007dea: 4606 mov r6, r0 8007dec: 460f mov r7, r1 8007dee: d007 beq.n 8007e00 <__pow5mult+0x20> 8007df0: 4c21 ldr r4, [pc, #132] ; (8007e78 <__pow5mult+0x98>) 8007df2: 3a01 subs r2, #1 8007df4: 2300 movs r3, #0 8007df6: f854 2022 ldr.w r2, [r4, r2, lsl #2] 8007dfa: f7ff fec9 bl 8007b90 <__multadd> 8007dfe: 4607 mov r7, r0 8007e00: 10ad asrs r5, r5, #2 8007e02: d035 beq.n 8007e70 <__pow5mult+0x90> 8007e04: 6a74 ldr r4, [r6, #36] ; 0x24 8007e06: b93c cbnz r4, 8007e18 <__pow5mult+0x38> 8007e08: 2010 movs r0, #16 8007e0a: f7ff fe55 bl 8007ab8 8007e0e: 6270 str r0, [r6, #36] ; 0x24 8007e10: e9c0 4401 strd r4, r4, [r0, #4] 8007e14: 6004 str r4, [r0, #0] 8007e16: 60c4 str r4, [r0, #12] 8007e18: f8d6 8024 ldr.w r8, [r6, #36] ; 0x24 8007e1c: f8d8 4008 ldr.w r4, [r8, #8] 8007e20: b94c cbnz r4, 8007e36 <__pow5mult+0x56> 8007e22: f240 2171 movw r1, #625 ; 0x271 8007e26: 4630 mov r0, r6 8007e28: f7ff ff3b bl 8007ca2 <__i2b> 8007e2c: 2300 movs r3, #0 8007e2e: 4604 mov r4, r0 8007e30: f8c8 0008 str.w r0, [r8, #8] 8007e34: 6003 str r3, [r0, #0] 8007e36: f04f 0800 mov.w r8, #0 8007e3a: 07eb lsls r3, r5, #31 8007e3c: d50a bpl.n 8007e54 <__pow5mult+0x74> 8007e3e: 4639 mov r1, r7 8007e40: 4622 mov r2, r4 8007e42: 4630 mov r0, r6 8007e44: f7ff ff36 bl 8007cb4 <__multiply> 8007e48: 4681 mov r9, r0 8007e4a: 4639 mov r1, r7 8007e4c: 4630 mov r0, r6 8007e4e: f7ff fe88 bl 8007b62 <_Bfree> 8007e52: 464f mov r7, r9 8007e54: 106d asrs r5, r5, #1 8007e56: d00b beq.n 8007e70 <__pow5mult+0x90> 8007e58: 6820 ldr r0, [r4, #0] 8007e5a: b938 cbnz r0, 8007e6c <__pow5mult+0x8c> 8007e5c: 4622 mov r2, r4 8007e5e: 4621 mov r1, r4 8007e60: 4630 mov r0, r6 8007e62: f7ff ff27 bl 8007cb4 <__multiply> 8007e66: 6020 str r0, [r4, #0] 8007e68: f8c0 8000 str.w r8, [r0] 8007e6c: 4604 mov r4, r0 8007e6e: e7e4 b.n 8007e3a <__pow5mult+0x5a> 8007e70: 4638 mov r0, r7 8007e72: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 8007e76: bf00 nop 8007e78: 08008b40 .word 0x08008b40 08007e7c <__lshift>: 8007e7c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8007e80: 460c mov r4, r1 8007e82: 4607 mov r7, r0 8007e84: 4616 mov r6, r2 8007e86: 6923 ldr r3, [r4, #16] 8007e88: ea4f 1a62 mov.w sl, r2, asr #5 8007e8c: eb0a 0903 add.w r9, sl, r3 8007e90: 6849 ldr r1, [r1, #4] 8007e92: 68a3 ldr r3, [r4, #8] 8007e94: f109 0501 add.w r5, r9, #1 8007e98: 42ab cmp r3, r5 8007e9a: db32 blt.n 8007f02 <__lshift+0x86> 8007e9c: 4638 mov r0, r7 8007e9e: f7ff fe2c bl 8007afa <_Balloc> 8007ea2: 2300 movs r3, #0 8007ea4: 4680 mov r8, r0 8007ea6: 461a mov r2, r3 8007ea8: f100 0114 add.w r1, r0, #20 8007eac: 4553 cmp r3, sl 8007eae: db2b blt.n 8007f08 <__lshift+0x8c> 8007eb0: 6920 ldr r0, [r4, #16] 8007eb2: ea2a 7aea bic.w sl, sl, sl, asr #31 8007eb6: f104 0314 add.w r3, r4, #20 8007eba: f016 021f ands.w r2, r6, #31 8007ebe: eb01 018a add.w r1, r1, sl, lsl #2 8007ec2: eb03 0c80 add.w ip, r3, r0, lsl #2 8007ec6: d025 beq.n 8007f14 <__lshift+0x98> 8007ec8: 2000 movs r0, #0 8007eca: f1c2 0e20 rsb lr, r2, #32 8007ece: 468a mov sl, r1 8007ed0: 681e ldr r6, [r3, #0] 8007ed2: 4096 lsls r6, r2 8007ed4: 4330 orrs r0, r6 8007ed6: f84a 0b04 str.w r0, [sl], #4 8007eda: f853 0b04 ldr.w r0, [r3], #4 8007ede: 459c cmp ip, r3 8007ee0: fa20 f00e lsr.w r0, r0, lr 8007ee4: d814 bhi.n 8007f10 <__lshift+0x94> 8007ee6: 6048 str r0, [r1, #4] 8007ee8: b108 cbz r0, 8007eee <__lshift+0x72> 8007eea: f109 0502 add.w r5, r9, #2 8007eee: 3d01 subs r5, #1 8007ef0: 4638 mov r0, r7 8007ef2: f8c8 5010 str.w r5, [r8, #16] 8007ef6: 4621 mov r1, r4 8007ef8: f7ff fe33 bl 8007b62 <_Bfree> 8007efc: 4640 mov r0, r8 8007efe: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8007f02: 3101 adds r1, #1 8007f04: 005b lsls r3, r3, #1 8007f06: e7c7 b.n 8007e98 <__lshift+0x1c> 8007f08: f841 2023 str.w r2, [r1, r3, lsl #2] 8007f0c: 3301 adds r3, #1 8007f0e: e7cd b.n 8007eac <__lshift+0x30> 8007f10: 4651 mov r1, sl 8007f12: e7dc b.n 8007ece <__lshift+0x52> 8007f14: 3904 subs r1, #4 8007f16: f853 2b04 ldr.w r2, [r3], #4 8007f1a: 459c cmp ip, r3 8007f1c: f841 2f04 str.w r2, [r1, #4]! 8007f20: d8f9 bhi.n 8007f16 <__lshift+0x9a> 8007f22: e7e4 b.n 8007eee <__lshift+0x72> 08007f24 <__mcmp>: 8007f24: 6903 ldr r3, [r0, #16] 8007f26: 690a ldr r2, [r1, #16] 8007f28: b530 push {r4, r5, lr} 8007f2a: 1a9b subs r3, r3, r2 8007f2c: d10c bne.n 8007f48 <__mcmp+0x24> 8007f2e: 0092 lsls r2, r2, #2 8007f30: 3014 adds r0, #20 8007f32: 3114 adds r1, #20 8007f34: 1884 adds r4, r0, r2 8007f36: 4411 add r1, r2 8007f38: f854 5d04 ldr.w r5, [r4, #-4]! 8007f3c: f851 2d04 ldr.w r2, [r1, #-4]! 8007f40: 4295 cmp r5, r2 8007f42: d003 beq.n 8007f4c <__mcmp+0x28> 8007f44: d305 bcc.n 8007f52 <__mcmp+0x2e> 8007f46: 2301 movs r3, #1 8007f48: 4618 mov r0, r3 8007f4a: bd30 pop {r4, r5, pc} 8007f4c: 42a0 cmp r0, r4 8007f4e: d3f3 bcc.n 8007f38 <__mcmp+0x14> 8007f50: e7fa b.n 8007f48 <__mcmp+0x24> 8007f52: f04f 33ff mov.w r3, #4294967295 8007f56: e7f7 b.n 8007f48 <__mcmp+0x24> 08007f58 <__mdiff>: 8007f58: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8007f5c: 460d mov r5, r1 8007f5e: 4607 mov r7, r0 8007f60: 4611 mov r1, r2 8007f62: 4628 mov r0, r5 8007f64: 4614 mov r4, r2 8007f66: f7ff ffdd bl 8007f24 <__mcmp> 8007f6a: 1e06 subs r6, r0, #0 8007f6c: d108 bne.n 8007f80 <__mdiff+0x28> 8007f6e: 4631 mov r1, r6 8007f70: 4638 mov r0, r7 8007f72: f7ff fdc2 bl 8007afa <_Balloc> 8007f76: 2301 movs r3, #1 8007f78: e9c0 3604 strd r3, r6, [r0, #16] 8007f7c: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8007f80: bfa4 itt ge 8007f82: 4623 movge r3, r4 8007f84: 462c movge r4, r5 8007f86: 4638 mov r0, r7 8007f88: 6861 ldr r1, [r4, #4] 8007f8a: bfa6 itte ge 8007f8c: 461d movge r5, r3 8007f8e: 2600 movge r6, #0 8007f90: 2601 movlt r6, #1 8007f92: f7ff fdb2 bl 8007afa <_Balloc> 8007f96: f04f 0e00 mov.w lr, #0 8007f9a: 60c6 str r6, [r0, #12] 8007f9c: 692b ldr r3, [r5, #16] 8007f9e: 6926 ldr r6, [r4, #16] 8007fa0: f104 0214 add.w r2, r4, #20 8007fa4: f105 0914 add.w r9, r5, #20 8007fa8: eb02 0786 add.w r7, r2, r6, lsl #2 8007fac: eb09 0883 add.w r8, r9, r3, lsl #2 8007fb0: f100 0114 add.w r1, r0, #20 8007fb4: f852 ab04 ldr.w sl, [r2], #4 8007fb8: f859 5b04 ldr.w r5, [r9], #4 8007fbc: fa1f f38a uxth.w r3, sl 8007fc0: 4473 add r3, lr 8007fc2: b2ac uxth r4, r5 8007fc4: 1b1b subs r3, r3, r4 8007fc6: 0c2c lsrs r4, r5, #16 8007fc8: ebc4 441a rsb r4, r4, sl, lsr #16 8007fcc: eb04 4423 add.w r4, r4, r3, asr #16 8007fd0: b29b uxth r3, r3 8007fd2: ea4f 4e24 mov.w lr, r4, asr #16 8007fd6: 45c8 cmp r8, r9 8007fd8: ea43 4404 orr.w r4, r3, r4, lsl #16 8007fdc: 4694 mov ip, r2 8007fde: f841 4b04 str.w r4, [r1], #4 8007fe2: d8e7 bhi.n 8007fb4 <__mdiff+0x5c> 8007fe4: 45bc cmp ip, r7 8007fe6: d304 bcc.n 8007ff2 <__mdiff+0x9a> 8007fe8: f851 3d04 ldr.w r3, [r1, #-4]! 8007fec: b183 cbz r3, 8008010 <__mdiff+0xb8> 8007fee: 6106 str r6, [r0, #16] 8007ff0: e7c4 b.n 8007f7c <__mdiff+0x24> 8007ff2: f85c 4b04 ldr.w r4, [ip], #4 8007ff6: b2a2 uxth r2, r4 8007ff8: 4472 add r2, lr 8007ffa: 1413 asrs r3, r2, #16 8007ffc: eb03 4314 add.w r3, r3, r4, lsr #16 8008000: b292 uxth r2, r2 8008002: ea42 4203 orr.w r2, r2, r3, lsl #16 8008006: ea4f 4e23 mov.w lr, r3, asr #16 800800a: f841 2b04 str.w r2, [r1], #4 800800e: e7e9 b.n 8007fe4 <__mdiff+0x8c> 8008010: 3e01 subs r6, #1 8008012: e7e9 b.n 8007fe8 <__mdiff+0x90> 08008014 <__d2b>: 8008014: e92d 41f3 stmdb sp!, {r0, r1, r4, r5, r6, r7, r8, lr} 8008018: 461c mov r4, r3 800801a: e9dd 6508 ldrd r6, r5, [sp, #32] 800801e: 2101 movs r1, #1 8008020: 4690 mov r8, r2 8008022: f7ff fd6a bl 8007afa <_Balloc> 8008026: f3c4 0213 ubfx r2, r4, #0, #20 800802a: f3c4 540a ubfx r4, r4, #20, #11 800802e: 4607 mov r7, r0 8008030: bb34 cbnz r4, 8008080 <__d2b+0x6c> 8008032: 9201 str r2, [sp, #4] 8008034: f1b8 0200 subs.w r2, r8, #0 8008038: d027 beq.n 800808a <__d2b+0x76> 800803a: a802 add r0, sp, #8 800803c: f840 2d08 str.w r2, [r0, #-8]! 8008040: f7ff fe00 bl 8007c44 <__lo0bits> 8008044: 9900 ldr r1, [sp, #0] 8008046: b1f0 cbz r0, 8008086 <__d2b+0x72> 8008048: 9a01 ldr r2, [sp, #4] 800804a: f1c0 0320 rsb r3, r0, #32 800804e: fa02 f303 lsl.w r3, r2, r3 8008052: 430b orrs r3, r1 8008054: 40c2 lsrs r2, r0 8008056: 617b str r3, [r7, #20] 8008058: 9201 str r2, [sp, #4] 800805a: 9b01 ldr r3, [sp, #4] 800805c: 2b00 cmp r3, #0 800805e: bf14 ite ne 8008060: 2102 movne r1, #2 8008062: 2101 moveq r1, #1 8008064: 61bb str r3, [r7, #24] 8008066: 6139 str r1, [r7, #16] 8008068: b1c4 cbz r4, 800809c <__d2b+0x88> 800806a: f2a4 4433 subw r4, r4, #1075 ; 0x433 800806e: 4404 add r4, r0 8008070: 6034 str r4, [r6, #0] 8008072: f1c0 0035 rsb r0, r0, #53 ; 0x35 8008076: 6028 str r0, [r5, #0] 8008078: 4638 mov r0, r7 800807a: b002 add sp, #8 800807c: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8008080: f442 1280 orr.w r2, r2, #1048576 ; 0x100000 8008084: e7d5 b.n 8008032 <__d2b+0x1e> 8008086: 6179 str r1, [r7, #20] 8008088: e7e7 b.n 800805a <__d2b+0x46> 800808a: a801 add r0, sp, #4 800808c: f7ff fdda bl 8007c44 <__lo0bits> 8008090: 2101 movs r1, #1 8008092: 9b01 ldr r3, [sp, #4] 8008094: 6139 str r1, [r7, #16] 8008096: 617b str r3, [r7, #20] 8008098: 3020 adds r0, #32 800809a: e7e5 b.n 8008068 <__d2b+0x54> 800809c: f2a0 4032 subw r0, r0, #1074 ; 0x432 80080a0: eb07 0381 add.w r3, r7, r1, lsl #2 80080a4: 6030 str r0, [r6, #0] 80080a6: 6918 ldr r0, [r3, #16] 80080a8: f7ff fdad bl 8007c06 <__hi0bits> 80080ac: ebc0 1041 rsb r0, r0, r1, lsl #5 80080b0: e7e1 b.n 8008076 <__d2b+0x62> 080080b2 <_calloc_r>: 80080b2: b538 push {r3, r4, r5, lr} 80080b4: fb02 f401 mul.w r4, r2, r1 80080b8: 4621 mov r1, r4 80080ba: f000 f855 bl 8008168 <_malloc_r> 80080be: 4605 mov r5, r0 80080c0: b118 cbz r0, 80080ca <_calloc_r+0x18> 80080c2: 4622 mov r2, r4 80080c4: 2100 movs r1, #0 80080c6: f7fd fe7f bl 8005dc8 80080ca: 4628 mov r0, r5 80080cc: bd38 pop {r3, r4, r5, pc} ... 080080d0 <_free_r>: 80080d0: b538 push {r3, r4, r5, lr} 80080d2: 4605 mov r5, r0 80080d4: 2900 cmp r1, #0 80080d6: d043 beq.n 8008160 <_free_r+0x90> 80080d8: f851 3c04 ldr.w r3, [r1, #-4] 80080dc: 1f0c subs r4, r1, #4 80080de: 2b00 cmp r3, #0 80080e0: bfb8 it lt 80080e2: 18e4 addlt r4, r4, r3 80080e4: f000 fa94 bl 8008610 <__malloc_lock> 80080e8: 4a1e ldr r2, [pc, #120] ; (8008164 <_free_r+0x94>) 80080ea: 6813 ldr r3, [r2, #0] 80080ec: 4610 mov r0, r2 80080ee: b933 cbnz r3, 80080fe <_free_r+0x2e> 80080f0: 6063 str r3, [r4, #4] 80080f2: 6014 str r4, [r2, #0] 80080f4: 4628 mov r0, r5 80080f6: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 80080fa: f000 ba8a b.w 8008612 <__malloc_unlock> 80080fe: 42a3 cmp r3, r4 8008100: d90b bls.n 800811a <_free_r+0x4a> 8008102: 6821 ldr r1, [r4, #0] 8008104: 1862 adds r2, r4, r1 8008106: 4293 cmp r3, r2 8008108: bf01 itttt eq 800810a: 681a ldreq r2, [r3, #0] 800810c: 685b ldreq r3, [r3, #4] 800810e: 1852 addeq r2, r2, r1 8008110: 6022 streq r2, [r4, #0] 8008112: 6063 str r3, [r4, #4] 8008114: 6004 str r4, [r0, #0] 8008116: e7ed b.n 80080f4 <_free_r+0x24> 8008118: 4613 mov r3, r2 800811a: 685a ldr r2, [r3, #4] 800811c: b10a cbz r2, 8008122 <_free_r+0x52> 800811e: 42a2 cmp r2, r4 8008120: d9fa bls.n 8008118 <_free_r+0x48> 8008122: 6819 ldr r1, [r3, #0] 8008124: 1858 adds r0, r3, r1 8008126: 42a0 cmp r0, r4 8008128: d10b bne.n 8008142 <_free_r+0x72> 800812a: 6820 ldr r0, [r4, #0] 800812c: 4401 add r1, r0 800812e: 1858 adds r0, r3, r1 8008130: 4282 cmp r2, r0 8008132: 6019 str r1, [r3, #0] 8008134: d1de bne.n 80080f4 <_free_r+0x24> 8008136: 6810 ldr r0, [r2, #0] 8008138: 6852 ldr r2, [r2, #4] 800813a: 4401 add r1, r0 800813c: 6019 str r1, [r3, #0] 800813e: 605a str r2, [r3, #4] 8008140: e7d8 b.n 80080f4 <_free_r+0x24> 8008142: d902 bls.n 800814a <_free_r+0x7a> 8008144: 230c movs r3, #12 8008146: 602b str r3, [r5, #0] 8008148: e7d4 b.n 80080f4 <_free_r+0x24> 800814a: 6820 ldr r0, [r4, #0] 800814c: 1821 adds r1, r4, r0 800814e: 428a cmp r2, r1 8008150: bf01 itttt eq 8008152: 6811 ldreq r1, [r2, #0] 8008154: 6852 ldreq r2, [r2, #4] 8008156: 1809 addeq r1, r1, r0 8008158: 6021 streq r1, [r4, #0] 800815a: 6062 str r2, [r4, #4] 800815c: 605c str r4, [r3, #4] 800815e: e7c9 b.n 80080f4 <_free_r+0x24> 8008160: bd38 pop {r3, r4, r5, pc} 8008162: bf00 nop 8008164: 20000510 .word 0x20000510 08008168 <_malloc_r>: 8008168: b570 push {r4, r5, r6, lr} 800816a: 1ccd adds r5, r1, #3 800816c: f025 0503 bic.w r5, r5, #3 8008170: 3508 adds r5, #8 8008172: 2d0c cmp r5, #12 8008174: bf38 it cc 8008176: 250c movcc r5, #12 8008178: 2d00 cmp r5, #0 800817a: 4606 mov r6, r0 800817c: db01 blt.n 8008182 <_malloc_r+0x1a> 800817e: 42a9 cmp r1, r5 8008180: d903 bls.n 800818a <_malloc_r+0x22> 8008182: 230c movs r3, #12 8008184: 6033 str r3, [r6, #0] 8008186: 2000 movs r0, #0 8008188: bd70 pop {r4, r5, r6, pc} 800818a: f000 fa41 bl 8008610 <__malloc_lock> 800818e: 4a21 ldr r2, [pc, #132] ; (8008214 <_malloc_r+0xac>) 8008190: 6814 ldr r4, [r2, #0] 8008192: 4621 mov r1, r4 8008194: b991 cbnz r1, 80081bc <_malloc_r+0x54> 8008196: 4c20 ldr r4, [pc, #128] ; (8008218 <_malloc_r+0xb0>) 8008198: 6823 ldr r3, [r4, #0] 800819a: b91b cbnz r3, 80081a4 <_malloc_r+0x3c> 800819c: 4630 mov r0, r6 800819e: f000 f97b bl 8008498 <_sbrk_r> 80081a2: 6020 str r0, [r4, #0] 80081a4: 4629 mov r1, r5 80081a6: 4630 mov r0, r6 80081a8: f000 f976 bl 8008498 <_sbrk_r> 80081ac: 1c43 adds r3, r0, #1 80081ae: d124 bne.n 80081fa <_malloc_r+0x92> 80081b0: 230c movs r3, #12 80081b2: 4630 mov r0, r6 80081b4: 6033 str r3, [r6, #0] 80081b6: f000 fa2c bl 8008612 <__malloc_unlock> 80081ba: e7e4 b.n 8008186 <_malloc_r+0x1e> 80081bc: 680b ldr r3, [r1, #0] 80081be: 1b5b subs r3, r3, r5 80081c0: d418 bmi.n 80081f4 <_malloc_r+0x8c> 80081c2: 2b0b cmp r3, #11 80081c4: d90f bls.n 80081e6 <_malloc_r+0x7e> 80081c6: 600b str r3, [r1, #0] 80081c8: 18cc adds r4, r1, r3 80081ca: 50cd str r5, [r1, r3] 80081cc: 4630 mov r0, r6 80081ce: f000 fa20 bl 8008612 <__malloc_unlock> 80081d2: f104 000b add.w r0, r4, #11 80081d6: 1d23 adds r3, r4, #4 80081d8: f020 0007 bic.w r0, r0, #7 80081dc: 1ac3 subs r3, r0, r3 80081de: d0d3 beq.n 8008188 <_malloc_r+0x20> 80081e0: 425a negs r2, r3 80081e2: 50e2 str r2, [r4, r3] 80081e4: e7d0 b.n 8008188 <_malloc_r+0x20> 80081e6: 684b ldr r3, [r1, #4] 80081e8: 428c cmp r4, r1 80081ea: bf16 itet ne 80081ec: 6063 strne r3, [r4, #4] 80081ee: 6013 streq r3, [r2, #0] 80081f0: 460c movne r4, r1 80081f2: e7eb b.n 80081cc <_malloc_r+0x64> 80081f4: 460c mov r4, r1 80081f6: 6849 ldr r1, [r1, #4] 80081f8: e7cc b.n 8008194 <_malloc_r+0x2c> 80081fa: 1cc4 adds r4, r0, #3 80081fc: f024 0403 bic.w r4, r4, #3 8008200: 42a0 cmp r0, r4 8008202: d005 beq.n 8008210 <_malloc_r+0xa8> 8008204: 1a21 subs r1, r4, r0 8008206: 4630 mov r0, r6 8008208: f000 f946 bl 8008498 <_sbrk_r> 800820c: 3001 adds r0, #1 800820e: d0cf beq.n 80081b0 <_malloc_r+0x48> 8008210: 6025 str r5, [r4, #0] 8008212: e7db b.n 80081cc <_malloc_r+0x64> 8008214: 20000510 .word 0x20000510 8008218: 20000514 .word 0x20000514 0800821c <__sfputc_r>: 800821c: 6893 ldr r3, [r2, #8] 800821e: b410 push {r4} 8008220: 3b01 subs r3, #1 8008222: 2b00 cmp r3, #0 8008224: 6093 str r3, [r2, #8] 8008226: da07 bge.n 8008238 <__sfputc_r+0x1c> 8008228: 6994 ldr r4, [r2, #24] 800822a: 42a3 cmp r3, r4 800822c: db01 blt.n 8008232 <__sfputc_r+0x16> 800822e: 290a cmp r1, #10 8008230: d102 bne.n 8008238 <__sfputc_r+0x1c> 8008232: bc10 pop {r4} 8008234: f7fe bb52 b.w 80068dc <__swbuf_r> 8008238: 6813 ldr r3, [r2, #0] 800823a: 1c58 adds r0, r3, #1 800823c: 6010 str r0, [r2, #0] 800823e: 7019 strb r1, [r3, #0] 8008240: 4608 mov r0, r1 8008242: bc10 pop {r4} 8008244: 4770 bx lr 08008246 <__sfputs_r>: 8008246: b5f8 push {r3, r4, r5, r6, r7, lr} 8008248: 4606 mov r6, r0 800824a: 460f mov r7, r1 800824c: 4614 mov r4, r2 800824e: 18d5 adds r5, r2, r3 8008250: 42ac cmp r4, r5 8008252: d101 bne.n 8008258 <__sfputs_r+0x12> 8008254: 2000 movs r0, #0 8008256: e007 b.n 8008268 <__sfputs_r+0x22> 8008258: 463a mov r2, r7 800825a: f814 1b01 ldrb.w r1, [r4], #1 800825e: 4630 mov r0, r6 8008260: f7ff ffdc bl 800821c <__sfputc_r> 8008264: 1c43 adds r3, r0, #1 8008266: d1f3 bne.n 8008250 <__sfputs_r+0xa> 8008268: bdf8 pop {r3, r4, r5, r6, r7, pc} ... 0800826c <_vfiprintf_r>: 800826c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8008270: 460c mov r4, r1 8008272: b09d sub sp, #116 ; 0x74 8008274: 4617 mov r7, r2 8008276: 461d mov r5, r3 8008278: 4606 mov r6, r0 800827a: b118 cbz r0, 8008284 <_vfiprintf_r+0x18> 800827c: 6983 ldr r3, [r0, #24] 800827e: b90b cbnz r3, 8008284 <_vfiprintf_r+0x18> 8008280: f7ff fb1e bl 80078c0 <__sinit> 8008284: 4b7c ldr r3, [pc, #496] ; (8008478 <_vfiprintf_r+0x20c>) 8008286: 429c cmp r4, r3 8008288: d158 bne.n 800833c <_vfiprintf_r+0xd0> 800828a: 6874 ldr r4, [r6, #4] 800828c: 89a3 ldrh r3, [r4, #12] 800828e: 0718 lsls r0, r3, #28 8008290: d55e bpl.n 8008350 <_vfiprintf_r+0xe4> 8008292: 6923 ldr r3, [r4, #16] 8008294: 2b00 cmp r3, #0 8008296: d05b beq.n 8008350 <_vfiprintf_r+0xe4> 8008298: 2300 movs r3, #0 800829a: 9309 str r3, [sp, #36] ; 0x24 800829c: 2320 movs r3, #32 800829e: f88d 3029 strb.w r3, [sp, #41] ; 0x29 80082a2: 2330 movs r3, #48 ; 0x30 80082a4: f04f 0b01 mov.w fp, #1 80082a8: f88d 302a strb.w r3, [sp, #42] ; 0x2a 80082ac: 9503 str r5, [sp, #12] 80082ae: 46b8 mov r8, r7 80082b0: 4645 mov r5, r8 80082b2: f815 3b01 ldrb.w r3, [r5], #1 80082b6: b10b cbz r3, 80082bc <_vfiprintf_r+0x50> 80082b8: 2b25 cmp r3, #37 ; 0x25 80082ba: d154 bne.n 8008366 <_vfiprintf_r+0xfa> 80082bc: ebb8 0a07 subs.w sl, r8, r7 80082c0: d00b beq.n 80082da <_vfiprintf_r+0x6e> 80082c2: 4653 mov r3, sl 80082c4: 463a mov r2, r7 80082c6: 4621 mov r1, r4 80082c8: 4630 mov r0, r6 80082ca: f7ff ffbc bl 8008246 <__sfputs_r> 80082ce: 3001 adds r0, #1 80082d0: f000 80c2 beq.w 8008458 <_vfiprintf_r+0x1ec> 80082d4: 9b09 ldr r3, [sp, #36] ; 0x24 80082d6: 4453 add r3, sl 80082d8: 9309 str r3, [sp, #36] ; 0x24 80082da: f898 3000 ldrb.w r3, [r8] 80082de: 2b00 cmp r3, #0 80082e0: f000 80ba beq.w 8008458 <_vfiprintf_r+0x1ec> 80082e4: 2300 movs r3, #0 80082e6: f04f 32ff mov.w r2, #4294967295 80082ea: e9cd 2305 strd r2, r3, [sp, #20] 80082ee: 9304 str r3, [sp, #16] 80082f0: 9307 str r3, [sp, #28] 80082f2: f88d 3053 strb.w r3, [sp, #83] ; 0x53 80082f6: 931a str r3, [sp, #104] ; 0x68 80082f8: 46a8 mov r8, r5 80082fa: 2205 movs r2, #5 80082fc: f818 1b01 ldrb.w r1, [r8], #1 8008300: 485e ldr r0, [pc, #376] ; (800847c <_vfiprintf_r+0x210>) 8008302: f7ff fbe1 bl 8007ac8 8008306: 9b04 ldr r3, [sp, #16] 8008308: bb78 cbnz r0, 800836a <_vfiprintf_r+0xfe> 800830a: 06d9 lsls r1, r3, #27 800830c: bf44 itt mi 800830e: 2220 movmi r2, #32 8008310: f88d 2053 strbmi.w r2, [sp, #83] ; 0x53 8008314: 071a lsls r2, r3, #28 8008316: bf44 itt mi 8008318: 222b movmi r2, #43 ; 0x2b 800831a: f88d 2053 strbmi.w r2, [sp, #83] ; 0x53 800831e: 782a ldrb r2, [r5, #0] 8008320: 2a2a cmp r2, #42 ; 0x2a 8008322: d02a beq.n 800837a <_vfiprintf_r+0x10e> 8008324: 46a8 mov r8, r5 8008326: 2000 movs r0, #0 8008328: 250a movs r5, #10 800832a: 9a07 ldr r2, [sp, #28] 800832c: 4641 mov r1, r8 800832e: f811 3b01 ldrb.w r3, [r1], #1 8008332: 3b30 subs r3, #48 ; 0x30 8008334: 2b09 cmp r3, #9 8008336: d969 bls.n 800840c <_vfiprintf_r+0x1a0> 8008338: b360 cbz r0, 8008394 <_vfiprintf_r+0x128> 800833a: e024 b.n 8008386 <_vfiprintf_r+0x11a> 800833c: 4b50 ldr r3, [pc, #320] ; (8008480 <_vfiprintf_r+0x214>) 800833e: 429c cmp r4, r3 8008340: d101 bne.n 8008346 <_vfiprintf_r+0xda> 8008342: 68b4 ldr r4, [r6, #8] 8008344: e7a2 b.n 800828c <_vfiprintf_r+0x20> 8008346: 4b4f ldr r3, [pc, #316] ; (8008484 <_vfiprintf_r+0x218>) 8008348: 429c cmp r4, r3 800834a: bf08 it eq 800834c: 68f4 ldreq r4, [r6, #12] 800834e: e79d b.n 800828c <_vfiprintf_r+0x20> 8008350: 4621 mov r1, r4 8008352: 4630 mov r0, r6 8008354: f7fe fb14 bl 8006980 <__swsetup_r> 8008358: 2800 cmp r0, #0 800835a: d09d beq.n 8008298 <_vfiprintf_r+0x2c> 800835c: f04f 30ff mov.w r0, #4294967295 8008360: b01d add sp, #116 ; 0x74 8008362: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8008366: 46a8 mov r8, r5 8008368: e7a2 b.n 80082b0 <_vfiprintf_r+0x44> 800836a: 4a44 ldr r2, [pc, #272] ; (800847c <_vfiprintf_r+0x210>) 800836c: 4645 mov r5, r8 800836e: 1a80 subs r0, r0, r2 8008370: fa0b f000 lsl.w r0, fp, r0 8008374: 4318 orrs r0, r3 8008376: 9004 str r0, [sp, #16] 8008378: e7be b.n 80082f8 <_vfiprintf_r+0x8c> 800837a: 9a03 ldr r2, [sp, #12] 800837c: 1d11 adds r1, r2, #4 800837e: 6812 ldr r2, [r2, #0] 8008380: 9103 str r1, [sp, #12] 8008382: 2a00 cmp r2, #0 8008384: db01 blt.n 800838a <_vfiprintf_r+0x11e> 8008386: 9207 str r2, [sp, #28] 8008388: e004 b.n 8008394 <_vfiprintf_r+0x128> 800838a: 4252 negs r2, r2 800838c: f043 0302 orr.w r3, r3, #2 8008390: 9207 str r2, [sp, #28] 8008392: 9304 str r3, [sp, #16] 8008394: f898 3000 ldrb.w r3, [r8] 8008398: 2b2e cmp r3, #46 ; 0x2e 800839a: d10e bne.n 80083ba <_vfiprintf_r+0x14e> 800839c: f898 3001 ldrb.w r3, [r8, #1] 80083a0: 2b2a cmp r3, #42 ; 0x2a 80083a2: d138 bne.n 8008416 <_vfiprintf_r+0x1aa> 80083a4: 9b03 ldr r3, [sp, #12] 80083a6: f108 0802 add.w r8, r8, #2 80083aa: 1d1a adds r2, r3, #4 80083ac: 681b ldr r3, [r3, #0] 80083ae: 9203 str r2, [sp, #12] 80083b0: 2b00 cmp r3, #0 80083b2: bfb8 it lt 80083b4: f04f 33ff movlt.w r3, #4294967295 80083b8: 9305 str r3, [sp, #20] 80083ba: 4d33 ldr r5, [pc, #204] ; (8008488 <_vfiprintf_r+0x21c>) 80083bc: 2203 movs r2, #3 80083be: f898 1000 ldrb.w r1, [r8] 80083c2: 4628 mov r0, r5 80083c4: f7ff fb80 bl 8007ac8 80083c8: b140 cbz r0, 80083dc <_vfiprintf_r+0x170> 80083ca: 2340 movs r3, #64 ; 0x40 80083cc: 1b40 subs r0, r0, r5 80083ce: fa03 f000 lsl.w r0, r3, r0 80083d2: 9b04 ldr r3, [sp, #16] 80083d4: f108 0801 add.w r8, r8, #1 80083d8: 4303 orrs r3, r0 80083da: 9304 str r3, [sp, #16] 80083dc: f898 1000 ldrb.w r1, [r8] 80083e0: 2206 movs r2, #6 80083e2: 482a ldr r0, [pc, #168] ; (800848c <_vfiprintf_r+0x220>) 80083e4: f108 0701 add.w r7, r8, #1 80083e8: f88d 1028 strb.w r1, [sp, #40] ; 0x28 80083ec: f7ff fb6c bl 8007ac8 80083f0: 2800 cmp r0, #0 80083f2: d037 beq.n 8008464 <_vfiprintf_r+0x1f8> 80083f4: 4b26 ldr r3, [pc, #152] ; (8008490 <_vfiprintf_r+0x224>) 80083f6: bb1b cbnz r3, 8008440 <_vfiprintf_r+0x1d4> 80083f8: 9b03 ldr r3, [sp, #12] 80083fa: 3307 adds r3, #7 80083fc: f023 0307 bic.w r3, r3, #7 8008400: 3308 adds r3, #8 8008402: 9303 str r3, [sp, #12] 8008404: 9b09 ldr r3, [sp, #36] ; 0x24 8008406: 444b add r3, r9 8008408: 9309 str r3, [sp, #36] ; 0x24 800840a: e750 b.n 80082ae <_vfiprintf_r+0x42> 800840c: fb05 3202 mla r2, r5, r2, r3 8008410: 2001 movs r0, #1 8008412: 4688 mov r8, r1 8008414: e78a b.n 800832c <_vfiprintf_r+0xc0> 8008416: 2300 movs r3, #0 8008418: 250a movs r5, #10 800841a: 4619 mov r1, r3 800841c: f108 0801 add.w r8, r8, #1 8008420: 9305 str r3, [sp, #20] 8008422: 4640 mov r0, r8 8008424: f810 2b01 ldrb.w r2, [r0], #1 8008428: 3a30 subs r2, #48 ; 0x30 800842a: 2a09 cmp r2, #9 800842c: d903 bls.n 8008436 <_vfiprintf_r+0x1ca> 800842e: 2b00 cmp r3, #0 8008430: d0c3 beq.n 80083ba <_vfiprintf_r+0x14e> 8008432: 9105 str r1, [sp, #20] 8008434: e7c1 b.n 80083ba <_vfiprintf_r+0x14e> 8008436: fb05 2101 mla r1, r5, r1, r2 800843a: 2301 movs r3, #1 800843c: 4680 mov r8, r0 800843e: e7f0 b.n 8008422 <_vfiprintf_r+0x1b6> 8008440: ab03 add r3, sp, #12 8008442: 9300 str r3, [sp, #0] 8008444: 4622 mov r2, r4 8008446: 4b13 ldr r3, [pc, #76] ; (8008494 <_vfiprintf_r+0x228>) 8008448: a904 add r1, sp, #16 800844a: 4630 mov r0, r6 800844c: f7fd fd56 bl 8005efc <_printf_float> 8008450: f1b0 3fff cmp.w r0, #4294967295 8008454: 4681 mov r9, r0 8008456: d1d5 bne.n 8008404 <_vfiprintf_r+0x198> 8008458: 89a3 ldrh r3, [r4, #12] 800845a: 065b lsls r3, r3, #25 800845c: f53f af7e bmi.w 800835c <_vfiprintf_r+0xf0> 8008460: 9809 ldr r0, [sp, #36] ; 0x24 8008462: e77d b.n 8008360 <_vfiprintf_r+0xf4> 8008464: ab03 add r3, sp, #12 8008466: 9300 str r3, [sp, #0] 8008468: 4622 mov r2, r4 800846a: 4b0a ldr r3, [pc, #40] ; (8008494 <_vfiprintf_r+0x228>) 800846c: a904 add r1, sp, #16 800846e: 4630 mov r0, r6 8008470: f7fd fff0 bl 8006454 <_printf_i> 8008474: e7ec b.n 8008450 <_vfiprintf_r+0x1e4> 8008476: bf00 nop 8008478: 08008a10 .word 0x08008a10 800847c: 08008b4c .word 0x08008b4c 8008480: 08008a30 .word 0x08008a30 8008484: 080089f0 .word 0x080089f0 8008488: 08008b52 .word 0x08008b52 800848c: 08008b56 .word 0x08008b56 8008490: 08005efd .word 0x08005efd 8008494: 08008247 .word 0x08008247 08008498 <_sbrk_r>: 8008498: b538 push {r3, r4, r5, lr} 800849a: 2300 movs r3, #0 800849c: 4c05 ldr r4, [pc, #20] ; (80084b4 <_sbrk_r+0x1c>) 800849e: 4605 mov r5, r0 80084a0: 4608 mov r0, r1 80084a2: 6023 str r3, [r4, #0] 80084a4: f7fd fbdc bl 8005c60 <_sbrk> 80084a8: 1c43 adds r3, r0, #1 80084aa: d102 bne.n 80084b2 <_sbrk_r+0x1a> 80084ac: 6823 ldr r3, [r4, #0] 80084ae: b103 cbz r3, 80084b2 <_sbrk_r+0x1a> 80084b0: 602b str r3, [r5, #0] 80084b2: bd38 pop {r3, r4, r5, pc} 80084b4: 200009dc .word 0x200009dc 080084b8 <__sread>: 80084b8: b510 push {r4, lr} 80084ba: 460c mov r4, r1 80084bc: f9b1 100e ldrsh.w r1, [r1, #14] 80084c0: f000 f8a8 bl 8008614 <_read_r> 80084c4: 2800 cmp r0, #0 80084c6: bfab itete ge 80084c8: 6d63 ldrge r3, [r4, #84] ; 0x54 80084ca: 89a3 ldrhlt r3, [r4, #12] 80084cc: 181b addge r3, r3, r0 80084ce: f423 5380 biclt.w r3, r3, #4096 ; 0x1000 80084d2: bfac ite ge 80084d4: 6563 strge r3, [r4, #84] ; 0x54 80084d6: 81a3 strhlt r3, [r4, #12] 80084d8: bd10 pop {r4, pc} 080084da <__swrite>: 80084da: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 80084de: 461f mov r7, r3 80084e0: 898b ldrh r3, [r1, #12] 80084e2: 4605 mov r5, r0 80084e4: 05db lsls r3, r3, #23 80084e6: 460c mov r4, r1 80084e8: 4616 mov r6, r2 80084ea: d505 bpl.n 80084f8 <__swrite+0x1e> 80084ec: 2302 movs r3, #2 80084ee: 2200 movs r2, #0 80084f0: f9b1 100e ldrsh.w r1, [r1, #14] 80084f4: f000 f868 bl 80085c8 <_lseek_r> 80084f8: 89a3 ldrh r3, [r4, #12] 80084fa: 4632 mov r2, r6 80084fc: f423 5380 bic.w r3, r3, #4096 ; 0x1000 8008500: 81a3 strh r3, [r4, #12] 8008502: f9b4 100e ldrsh.w r1, [r4, #14] 8008506: 463b mov r3, r7 8008508: 4628 mov r0, r5 800850a: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 800850e: f000 b817 b.w 8008540 <_write_r> 08008512 <__sseek>: 8008512: b510 push {r4, lr} 8008514: 460c mov r4, r1 8008516: f9b1 100e ldrsh.w r1, [r1, #14] 800851a: f000 f855 bl 80085c8 <_lseek_r> 800851e: 1c43 adds r3, r0, #1 8008520: 89a3 ldrh r3, [r4, #12] 8008522: bf15 itete ne 8008524: 6560 strne r0, [r4, #84] ; 0x54 8008526: f423 5380 biceq.w r3, r3, #4096 ; 0x1000 800852a: f443 5380 orrne.w r3, r3, #4096 ; 0x1000 800852e: 81a3 strheq r3, [r4, #12] 8008530: bf18 it ne 8008532: 81a3 strhne r3, [r4, #12] 8008534: bd10 pop {r4, pc} 08008536 <__sclose>: 8008536: f9b1 100e ldrsh.w r1, [r1, #14] 800853a: f000 b813 b.w 8008564 <_close_r> ... 08008540 <_write_r>: 8008540: b538 push {r3, r4, r5, lr} 8008542: 4605 mov r5, r0 8008544: 4608 mov r0, r1 8008546: 4611 mov r1, r2 8008548: 2200 movs r2, #0 800854a: 4c05 ldr r4, [pc, #20] ; (8008560 <_write_r+0x20>) 800854c: 6022 str r2, [r4, #0] 800854e: 461a mov r2, r3 8008550: f7fc fdae bl 80050b0 <_write> 8008554: 1c43 adds r3, r0, #1 8008556: d102 bne.n 800855e <_write_r+0x1e> 8008558: 6823 ldr r3, [r4, #0] 800855a: b103 cbz r3, 800855e <_write_r+0x1e> 800855c: 602b str r3, [r5, #0] 800855e: bd38 pop {r3, r4, r5, pc} 8008560: 200009dc .word 0x200009dc 08008564 <_close_r>: 8008564: b538 push {r3, r4, r5, lr} 8008566: 2300 movs r3, #0 8008568: 4c05 ldr r4, [pc, #20] ; (8008580 <_close_r+0x1c>) 800856a: 4605 mov r5, r0 800856c: 4608 mov r0, r1 800856e: 6023 str r3, [r4, #0] 8008570: f7fd fb45 bl 8005bfe <_close> 8008574: 1c43 adds r3, r0, #1 8008576: d102 bne.n 800857e <_close_r+0x1a> 8008578: 6823 ldr r3, [r4, #0] 800857a: b103 cbz r3, 800857e <_close_r+0x1a> 800857c: 602b str r3, [r5, #0] 800857e: bd38 pop {r3, r4, r5, pc} 8008580: 200009dc .word 0x200009dc 08008584 <_fstat_r>: 8008584: b538 push {r3, r4, r5, lr} 8008586: 2300 movs r3, #0 8008588: 4c06 ldr r4, [pc, #24] ; (80085a4 <_fstat_r+0x20>) 800858a: 4605 mov r5, r0 800858c: 4608 mov r0, r1 800858e: 4611 mov r1, r2 8008590: 6023 str r3, [r4, #0] 8008592: f7fd fb3f bl 8005c14 <_fstat> 8008596: 1c43 adds r3, r0, #1 8008598: d102 bne.n 80085a0 <_fstat_r+0x1c> 800859a: 6823 ldr r3, [r4, #0] 800859c: b103 cbz r3, 80085a0 <_fstat_r+0x1c> 800859e: 602b str r3, [r5, #0] 80085a0: bd38 pop {r3, r4, r5, pc} 80085a2: bf00 nop 80085a4: 200009dc .word 0x200009dc 080085a8 <_isatty_r>: 80085a8: b538 push {r3, r4, r5, lr} 80085aa: 2300 movs r3, #0 80085ac: 4c05 ldr r4, [pc, #20] ; (80085c4 <_isatty_r+0x1c>) 80085ae: 4605 mov r5, r0 80085b0: 4608 mov r0, r1 80085b2: 6023 str r3, [r4, #0] 80085b4: f7fd fb3d bl 8005c32 <_isatty> 80085b8: 1c43 adds r3, r0, #1 80085ba: d102 bne.n 80085c2 <_isatty_r+0x1a> 80085bc: 6823 ldr r3, [r4, #0] 80085be: b103 cbz r3, 80085c2 <_isatty_r+0x1a> 80085c0: 602b str r3, [r5, #0] 80085c2: bd38 pop {r3, r4, r5, pc} 80085c4: 200009dc .word 0x200009dc 080085c8 <_lseek_r>: 80085c8: b538 push {r3, r4, r5, lr} 80085ca: 4605 mov r5, r0 80085cc: 4608 mov r0, r1 80085ce: 4611 mov r1, r2 80085d0: 2200 movs r2, #0 80085d2: 4c05 ldr r4, [pc, #20] ; (80085e8 <_lseek_r+0x20>) 80085d4: 6022 str r2, [r4, #0] 80085d6: 461a mov r2, r3 80085d8: f7fd fb35 bl 8005c46 <_lseek> 80085dc: 1c43 adds r3, r0, #1 80085de: d102 bne.n 80085e6 <_lseek_r+0x1e> 80085e0: 6823 ldr r3, [r4, #0] 80085e2: b103 cbz r3, 80085e6 <_lseek_r+0x1e> 80085e4: 602b str r3, [r5, #0] 80085e6: bd38 pop {r3, r4, r5, pc} 80085e8: 200009dc .word 0x200009dc 080085ec <__ascii_mbtowc>: 80085ec: b082 sub sp, #8 80085ee: b901 cbnz r1, 80085f2 <__ascii_mbtowc+0x6> 80085f0: a901 add r1, sp, #4 80085f2: b142 cbz r2, 8008606 <__ascii_mbtowc+0x1a> 80085f4: b14b cbz r3, 800860a <__ascii_mbtowc+0x1e> 80085f6: 7813 ldrb r3, [r2, #0] 80085f8: 600b str r3, [r1, #0] 80085fa: 7812 ldrb r2, [r2, #0] 80085fc: 1c10 adds r0, r2, #0 80085fe: bf18 it ne 8008600: 2001 movne r0, #1 8008602: b002 add sp, #8 8008604: 4770 bx lr 8008606: 4610 mov r0, r2 8008608: e7fb b.n 8008602 <__ascii_mbtowc+0x16> 800860a: f06f 0001 mvn.w r0, #1 800860e: e7f8 b.n 8008602 <__ascii_mbtowc+0x16> 08008610 <__malloc_lock>: 8008610: 4770 bx lr 08008612 <__malloc_unlock>: 8008612: 4770 bx lr 08008614 <_read_r>: 8008614: b538 push {r3, r4, r5, lr} 8008616: 4605 mov r5, r0 8008618: 4608 mov r0, r1 800861a: 4611 mov r1, r2 800861c: 2200 movs r2, #0 800861e: 4c05 ldr r4, [pc, #20] ; (8008634 <_read_r+0x20>) 8008620: 6022 str r2, [r4, #0] 8008622: 461a mov r2, r3 8008624: f7fd face bl 8005bc4 <_read> 8008628: 1c43 adds r3, r0, #1 800862a: d102 bne.n 8008632 <_read_r+0x1e> 800862c: 6823 ldr r3, [r4, #0] 800862e: b103 cbz r3, 8008632 <_read_r+0x1e> 8008630: 602b str r3, [r5, #0] 8008632: bd38 pop {r3, r4, r5, pc} 8008634: 200009dc .word 0x200009dc 08008638 <__ascii_wctomb>: 8008638: b149 cbz r1, 800864e <__ascii_wctomb+0x16> 800863a: 2aff cmp r2, #255 ; 0xff 800863c: bf8b itete hi 800863e: 238a movhi r3, #138 ; 0x8a 8008640: 700a strbls r2, [r1, #0] 8008642: 6003 strhi r3, [r0, #0] 8008644: 2001 movls r0, #1 8008646: bf88 it hi 8008648: f04f 30ff movhi.w r0, #4294967295 800864c: 4770 bx lr 800864e: 4608 mov r0, r1 8008650: 4770 bx lr ... 08008654 <_init>: 8008654: b5f8 push {r3, r4, r5, r6, r7, lr} 8008656: bf00 nop 8008658: bcf8 pop {r3, r4, r5, r6, r7} 800865a: bc08 pop {r3} 800865c: 469e mov lr, r3 800865e: 4770 bx lr 08008660 <_fini>: 8008660: b5f8 push {r3, r4, r5, r6, r7, lr} 8008662: bf00 nop 8008664: bcf8 pop {r3, r4, r5, r6, r7} 8008666: bc08 pop {r3} 8008668: 469e mov lr, r3 800866a: 4770 bx lr