Nesslab_200M_System.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000001d0 08000000 08000000 00010000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 00007194 080001d0 080001d0 000101d0 2**3 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 000003a0 08007368 08007368 00017368 2**3 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 08007708 08007708 000201dc 2**0 CONTENTS 4 .ARM 00000000 08007708 08007708 000201dc 2**0 CONTENTS 5 .preinit_array 00000000 08007708 08007708 000201dc 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 08007708 08007708 00017708 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .fini_array 00000004 0800770c 0800770c 0001770c 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .data 000001dc 20000000 08007710 00020000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 00000460 200001dc 080078ec 000201dc 2**2 ALLOC 10 ._user_heap_stack 00000604 2000063c 080078ec 0002063c 2**0 ALLOC 11 .ARM.attributes 00000029 00000000 00000000 000201dc 2**0 CONTENTS, READONLY 12 .debug_info 00011f78 00000000 00000000 00020205 2**0 CONTENTS, READONLY, DEBUGGING 13 .debug_abbrev 00002dce 00000000 00000000 0003217d 2**0 CONTENTS, READONLY, DEBUGGING 14 .debug_aranges 00000f90 00000000 00000000 00034f50 2**3 CONTENTS, READONLY, DEBUGGING 15 .debug_ranges 00000e18 00000000 00000000 00035ee0 2**3 CONTENTS, READONLY, DEBUGGING 16 .debug_macro 00010766 00000000 00000000 00036cf8 2**0 CONTENTS, READONLY, DEBUGGING 17 .debug_line 0000d862 00000000 00000000 0004745e 2**0 CONTENTS, READONLY, DEBUGGING 18 .debug_str 00057930 00000000 00000000 00054cc0 2**0 CONTENTS, READONLY, DEBUGGING 19 .comment 0000007b 00000000 00000000 000ac5f0 2**0 CONTENTS, READONLY 20 .debug_frame 00004d18 00000000 00000000 000ac66c 2**2 CONTENTS, READONLY, DEBUGGING Disassembly of section .text: 080001d0 <__do_global_dtors_aux>: 80001d0: b510 push {r4, lr} 80001d2: 4c05 ldr r4, [pc, #20] ; (80001e8 <__do_global_dtors_aux+0x18>) 80001d4: 7823 ldrb r3, [r4, #0] 80001d6: b933 cbnz r3, 80001e6 <__do_global_dtors_aux+0x16> 80001d8: 4b04 ldr r3, [pc, #16] ; (80001ec <__do_global_dtors_aux+0x1c>) 80001da: b113 cbz r3, 80001e2 <__do_global_dtors_aux+0x12> 80001dc: 4804 ldr r0, [pc, #16] ; (80001f0 <__do_global_dtors_aux+0x20>) 80001de: f3af 8000 nop.w 80001e2: 2301 movs r3, #1 80001e4: 7023 strb r3, [r4, #0] 80001e6: bd10 pop {r4, pc} 80001e8: 200001dc .word 0x200001dc 80001ec: 00000000 .word 0x00000000 80001f0: 0800734c .word 0x0800734c 080001f4 : 80001f4: b508 push {r3, lr} 80001f6: 4b03 ldr r3, [pc, #12] ; (8000204 ) 80001f8: b11b cbz r3, 8000202 80001fa: 4903 ldr r1, [pc, #12] ; (8000208 ) 80001fc: 4803 ldr r0, [pc, #12] ; (800020c ) 80001fe: f3af 8000 nop.w 8000202: bd08 pop {r3, pc} 8000204: 00000000 .word 0x00000000 8000208: 200001e0 .word 0x200001e0 800020c: 0800734c .word 0x0800734c 08000210 : 8000210: 4603 mov r3, r0 8000212: f813 2b01 ldrb.w r2, [r3], #1 8000216: 2a00 cmp r2, #0 8000218: d1fb bne.n 8000212 800021a: 1a18 subs r0, r3, r0 800021c: 3801 subs r0, #1 800021e: 4770 bx lr 08000220 <__aeabi_drsub>: 8000220: f081 4100 eor.w r1, r1, #2147483648 ; 0x80000000 8000224: e002 b.n 800022c <__adddf3> 8000226: bf00 nop 08000228 <__aeabi_dsub>: 8000228: f083 4300 eor.w r3, r3, #2147483648 ; 0x80000000 0800022c <__adddf3>: 800022c: b530 push {r4, r5, lr} 800022e: ea4f 0441 mov.w r4, r1, lsl #1 8000232: ea4f 0543 mov.w r5, r3, lsl #1 8000236: ea94 0f05 teq r4, r5 800023a: bf08 it eq 800023c: ea90 0f02 teqeq r0, r2 8000240: bf1f itttt ne 8000242: ea54 0c00 orrsne.w ip, r4, r0 8000246: ea55 0c02 orrsne.w ip, r5, r2 800024a: ea7f 5c64 mvnsne.w ip, r4, asr #21 800024e: ea7f 5c65 mvnsne.w ip, r5, asr #21 8000252: f000 80e2 beq.w 800041a <__adddf3+0x1ee> 8000256: ea4f 5454 mov.w r4, r4, lsr #21 800025a: ebd4 5555 rsbs r5, r4, r5, lsr #21 800025e: bfb8 it lt 8000260: 426d neglt r5, r5 8000262: dd0c ble.n 800027e <__adddf3+0x52> 8000264: 442c add r4, r5 8000266: ea80 0202 eor.w r2, r0, r2 800026a: ea81 0303 eor.w r3, r1, r3 800026e: ea82 0000 eor.w r0, r2, r0 8000272: ea83 0101 eor.w r1, r3, r1 8000276: ea80 0202 eor.w r2, r0, r2 800027a: ea81 0303 eor.w r3, r1, r3 800027e: 2d36 cmp r5, #54 ; 0x36 8000280: bf88 it hi 8000282: bd30 pophi {r4, r5, pc} 8000284: f011 4f00 tst.w r1, #2147483648 ; 0x80000000 8000288: ea4f 3101 mov.w r1, r1, lsl #12 800028c: f44f 1c80 mov.w ip, #1048576 ; 0x100000 8000290: ea4c 3111 orr.w r1, ip, r1, lsr #12 8000294: d002 beq.n 800029c <__adddf3+0x70> 8000296: 4240 negs r0, r0 8000298: eb61 0141 sbc.w r1, r1, r1, lsl #1 800029c: f013 4f00 tst.w r3, #2147483648 ; 0x80000000 80002a0: ea4f 3303 mov.w r3, r3, lsl #12 80002a4: ea4c 3313 orr.w r3, ip, r3, lsr #12 80002a8: d002 beq.n 80002b0 <__adddf3+0x84> 80002aa: 4252 negs r2, r2 80002ac: eb63 0343 sbc.w r3, r3, r3, lsl #1 80002b0: ea94 0f05 teq r4, r5 80002b4: f000 80a7 beq.w 8000406 <__adddf3+0x1da> 80002b8: f1a4 0401 sub.w r4, r4, #1 80002bc: f1d5 0e20 rsbs lr, r5, #32 80002c0: db0d blt.n 80002de <__adddf3+0xb2> 80002c2: fa02 fc0e lsl.w ip, r2, lr 80002c6: fa22 f205 lsr.w r2, r2, r5 80002ca: 1880 adds r0, r0, r2 80002cc: f141 0100 adc.w r1, r1, #0 80002d0: fa03 f20e lsl.w r2, r3, lr 80002d4: 1880 adds r0, r0, r2 80002d6: fa43 f305 asr.w r3, r3, r5 80002da: 4159 adcs r1, r3 80002dc: e00e b.n 80002fc <__adddf3+0xd0> 80002de: f1a5 0520 sub.w r5, r5, #32 80002e2: f10e 0e20 add.w lr, lr, #32 80002e6: 2a01 cmp r2, #1 80002e8: fa03 fc0e lsl.w ip, r3, lr 80002ec: bf28 it cs 80002ee: f04c 0c02 orrcs.w ip, ip, #2 80002f2: fa43 f305 asr.w r3, r3, r5 80002f6: 18c0 adds r0, r0, r3 80002f8: eb51 71e3 adcs.w r1, r1, r3, asr #31 80002fc: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 8000300: d507 bpl.n 8000312 <__adddf3+0xe6> 8000302: f04f 0e00 mov.w lr, #0 8000306: f1dc 0c00 rsbs ip, ip, #0 800030a: eb7e 0000 sbcs.w r0, lr, r0 800030e: eb6e 0101 sbc.w r1, lr, r1 8000312: f5b1 1f80 cmp.w r1, #1048576 ; 0x100000 8000316: d31b bcc.n 8000350 <__adddf3+0x124> 8000318: f5b1 1f00 cmp.w r1, #2097152 ; 0x200000 800031c: d30c bcc.n 8000338 <__adddf3+0x10c> 800031e: 0849 lsrs r1, r1, #1 8000320: ea5f 0030 movs.w r0, r0, rrx 8000324: ea4f 0c3c mov.w ip, ip, rrx 8000328: f104 0401 add.w r4, r4, #1 800032c: ea4f 5244 mov.w r2, r4, lsl #21 8000330: f512 0f80 cmn.w r2, #4194304 ; 0x400000 8000334: f080 809a bcs.w 800046c <__adddf3+0x240> 8000338: f1bc 4f00 cmp.w ip, #2147483648 ; 0x80000000 800033c: bf08 it eq 800033e: ea5f 0c50 movseq.w ip, r0, lsr #1 8000342: f150 0000 adcs.w r0, r0, #0 8000346: eb41 5104 adc.w r1, r1, r4, lsl #20 800034a: ea41 0105 orr.w r1, r1, r5 800034e: bd30 pop {r4, r5, pc} 8000350: ea5f 0c4c movs.w ip, ip, lsl #1 8000354: 4140 adcs r0, r0 8000356: eb41 0101 adc.w r1, r1, r1 800035a: f411 1f80 tst.w r1, #1048576 ; 0x100000 800035e: f1a4 0401 sub.w r4, r4, #1 8000362: d1e9 bne.n 8000338 <__adddf3+0x10c> 8000364: f091 0f00 teq r1, #0 8000368: bf04 itt eq 800036a: 4601 moveq r1, r0 800036c: 2000 moveq r0, #0 800036e: fab1 f381 clz r3, r1 8000372: bf08 it eq 8000374: 3320 addeq r3, #32 8000376: f1a3 030b sub.w r3, r3, #11 800037a: f1b3 0220 subs.w r2, r3, #32 800037e: da0c bge.n 800039a <__adddf3+0x16e> 8000380: 320c adds r2, #12 8000382: dd08 ble.n 8000396 <__adddf3+0x16a> 8000384: f102 0c14 add.w ip, r2, #20 8000388: f1c2 020c rsb r2, r2, #12 800038c: fa01 f00c lsl.w r0, r1, ip 8000390: fa21 f102 lsr.w r1, r1, r2 8000394: e00c b.n 80003b0 <__adddf3+0x184> 8000396: f102 0214 add.w r2, r2, #20 800039a: bfd8 it le 800039c: f1c2 0c20 rsble ip, r2, #32 80003a0: fa01 f102 lsl.w r1, r1, r2 80003a4: fa20 fc0c lsr.w ip, r0, ip 80003a8: bfdc itt le 80003aa: ea41 010c orrle.w r1, r1, ip 80003ae: 4090 lslle r0, r2 80003b0: 1ae4 subs r4, r4, r3 80003b2: bfa2 ittt ge 80003b4: eb01 5104 addge.w r1, r1, r4, lsl #20 80003b8: 4329 orrge r1, r5 80003ba: bd30 popge {r4, r5, pc} 80003bc: ea6f 0404 mvn.w r4, r4 80003c0: 3c1f subs r4, #31 80003c2: da1c bge.n 80003fe <__adddf3+0x1d2> 80003c4: 340c adds r4, #12 80003c6: dc0e bgt.n 80003e6 <__adddf3+0x1ba> 80003c8: f104 0414 add.w r4, r4, #20 80003cc: f1c4 0220 rsb r2, r4, #32 80003d0: fa20 f004 lsr.w r0, r0, r4 80003d4: fa01 f302 lsl.w r3, r1, r2 80003d8: ea40 0003 orr.w r0, r0, r3 80003dc: fa21 f304 lsr.w r3, r1, r4 80003e0: ea45 0103 orr.w r1, r5, r3 80003e4: bd30 pop {r4, r5, pc} 80003e6: f1c4 040c rsb r4, r4, #12 80003ea: f1c4 0220 rsb r2, r4, #32 80003ee: fa20 f002 lsr.w r0, r0, r2 80003f2: fa01 f304 lsl.w r3, r1, r4 80003f6: ea40 0003 orr.w r0, r0, r3 80003fa: 4629 mov r1, r5 80003fc: bd30 pop {r4, r5, pc} 80003fe: fa21 f004 lsr.w r0, r1, r4 8000402: 4629 mov r1, r5 8000404: bd30 pop {r4, r5, pc} 8000406: f094 0f00 teq r4, #0 800040a: f483 1380 eor.w r3, r3, #1048576 ; 0x100000 800040e: bf06 itte eq 8000410: f481 1180 eoreq.w r1, r1, #1048576 ; 0x100000 8000414: 3401 addeq r4, #1 8000416: 3d01 subne r5, #1 8000418: e74e b.n 80002b8 <__adddf3+0x8c> 800041a: ea7f 5c64 mvns.w ip, r4, asr #21 800041e: bf18 it ne 8000420: ea7f 5c65 mvnsne.w ip, r5, asr #21 8000424: d029 beq.n 800047a <__adddf3+0x24e> 8000426: ea94 0f05 teq r4, r5 800042a: bf08 it eq 800042c: ea90 0f02 teqeq r0, r2 8000430: d005 beq.n 800043e <__adddf3+0x212> 8000432: ea54 0c00 orrs.w ip, r4, r0 8000436: bf04 itt eq 8000438: 4619 moveq r1, r3 800043a: 4610 moveq r0, r2 800043c: bd30 pop {r4, r5, pc} 800043e: ea91 0f03 teq r1, r3 8000442: bf1e ittt ne 8000444: 2100 movne r1, #0 8000446: 2000 movne r0, #0 8000448: bd30 popne {r4, r5, pc} 800044a: ea5f 5c54 movs.w ip, r4, lsr #21 800044e: d105 bne.n 800045c <__adddf3+0x230> 8000450: 0040 lsls r0, r0, #1 8000452: 4149 adcs r1, r1 8000454: bf28 it cs 8000456: f041 4100 orrcs.w r1, r1, #2147483648 ; 0x80000000 800045a: bd30 pop {r4, r5, pc} 800045c: f514 0480 adds.w r4, r4, #4194304 ; 0x400000 8000460: bf3c itt cc 8000462: f501 1180 addcc.w r1, r1, #1048576 ; 0x100000 8000466: bd30 popcc {r4, r5, pc} 8000468: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 800046c: f045 41fe orr.w r1, r5, #2130706432 ; 0x7f000000 8000470: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000 8000474: f04f 0000 mov.w r0, #0 8000478: bd30 pop {r4, r5, pc} 800047a: ea7f 5c64 mvns.w ip, r4, asr #21 800047e: bf1a itte ne 8000480: 4619 movne r1, r3 8000482: 4610 movne r0, r2 8000484: ea7f 5c65 mvnseq.w ip, r5, asr #21 8000488: bf1c itt ne 800048a: 460b movne r3, r1 800048c: 4602 movne r2, r0 800048e: ea50 3401 orrs.w r4, r0, r1, lsl #12 8000492: bf06 itte eq 8000494: ea52 3503 orrseq.w r5, r2, r3, lsl #12 8000498: ea91 0f03 teqeq r1, r3 800049c: f441 2100 orrne.w r1, r1, #524288 ; 0x80000 80004a0: bd30 pop {r4, r5, pc} 80004a2: bf00 nop 080004a4 <__aeabi_ui2d>: 80004a4: f090 0f00 teq r0, #0 80004a8: bf04 itt eq 80004aa: 2100 moveq r1, #0 80004ac: 4770 bxeq lr 80004ae: b530 push {r4, r5, lr} 80004b0: f44f 6480 mov.w r4, #1024 ; 0x400 80004b4: f104 0432 add.w r4, r4, #50 ; 0x32 80004b8: f04f 0500 mov.w r5, #0 80004bc: f04f 0100 mov.w r1, #0 80004c0: e750 b.n 8000364 <__adddf3+0x138> 80004c2: bf00 nop 080004c4 <__aeabi_i2d>: 80004c4: f090 0f00 teq r0, #0 80004c8: bf04 itt eq 80004ca: 2100 moveq r1, #0 80004cc: 4770 bxeq lr 80004ce: b530 push {r4, r5, lr} 80004d0: f44f 6480 mov.w r4, #1024 ; 0x400 80004d4: f104 0432 add.w r4, r4, #50 ; 0x32 80004d8: f010 4500 ands.w r5, r0, #2147483648 ; 0x80000000 80004dc: bf48 it mi 80004de: 4240 negmi r0, r0 80004e0: f04f 0100 mov.w r1, #0 80004e4: e73e b.n 8000364 <__adddf3+0x138> 80004e6: bf00 nop 080004e8 <__aeabi_f2d>: 80004e8: 0042 lsls r2, r0, #1 80004ea: ea4f 01e2 mov.w r1, r2, asr #3 80004ee: ea4f 0131 mov.w r1, r1, rrx 80004f2: ea4f 7002 mov.w r0, r2, lsl #28 80004f6: bf1f itttt ne 80004f8: f012 437f andsne.w r3, r2, #4278190080 ; 0xff000000 80004fc: f093 4f7f teqne r3, #4278190080 ; 0xff000000 8000500: f081 5160 eorne.w r1, r1, #939524096 ; 0x38000000 8000504: 4770 bxne lr 8000506: f032 427f bics.w r2, r2, #4278190080 ; 0xff000000 800050a: bf08 it eq 800050c: 4770 bxeq lr 800050e: f093 4f7f teq r3, #4278190080 ; 0xff000000 8000512: bf04 itt eq 8000514: f441 2100 orreq.w r1, r1, #524288 ; 0x80000 8000518: 4770 bxeq lr 800051a: b530 push {r4, r5, lr} 800051c: f44f 7460 mov.w r4, #896 ; 0x380 8000520: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 8000524: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000 8000528: e71c b.n 8000364 <__adddf3+0x138> 800052a: bf00 nop 0800052c <__aeabi_ul2d>: 800052c: ea50 0201 orrs.w r2, r0, r1 8000530: bf08 it eq 8000532: 4770 bxeq lr 8000534: b530 push {r4, r5, lr} 8000536: f04f 0500 mov.w r5, #0 800053a: e00a b.n 8000552 <__aeabi_l2d+0x16> 0800053c <__aeabi_l2d>: 800053c: ea50 0201 orrs.w r2, r0, r1 8000540: bf08 it eq 8000542: 4770 bxeq lr 8000544: b530 push {r4, r5, lr} 8000546: f011 4500 ands.w r5, r1, #2147483648 ; 0x80000000 800054a: d502 bpl.n 8000552 <__aeabi_l2d+0x16> 800054c: 4240 negs r0, r0 800054e: eb61 0141 sbc.w r1, r1, r1, lsl #1 8000552: f44f 6480 mov.w r4, #1024 ; 0x400 8000556: f104 0432 add.w r4, r4, #50 ; 0x32 800055a: ea5f 5c91 movs.w ip, r1, lsr #22 800055e: f43f aed8 beq.w 8000312 <__adddf3+0xe6> 8000562: f04f 0203 mov.w r2, #3 8000566: ea5f 0cdc movs.w ip, ip, lsr #3 800056a: bf18 it ne 800056c: 3203 addne r2, #3 800056e: ea5f 0cdc movs.w ip, ip, lsr #3 8000572: bf18 it ne 8000574: 3203 addne r2, #3 8000576: eb02 02dc add.w r2, r2, ip, lsr #3 800057a: f1c2 0320 rsb r3, r2, #32 800057e: fa00 fc03 lsl.w ip, r0, r3 8000582: fa20 f002 lsr.w r0, r0, r2 8000586: fa01 fe03 lsl.w lr, r1, r3 800058a: ea40 000e orr.w r0, r0, lr 800058e: fa21 f102 lsr.w r1, r1, r2 8000592: 4414 add r4, r2 8000594: e6bd b.n 8000312 <__adddf3+0xe6> 8000596: bf00 nop 08000598 <__aeabi_dmul>: 8000598: b570 push {r4, r5, r6, lr} 800059a: f04f 0cff mov.w ip, #255 ; 0xff 800059e: f44c 6ce0 orr.w ip, ip, #1792 ; 0x700 80005a2: ea1c 5411 ands.w r4, ip, r1, lsr #20 80005a6: bf1d ittte ne 80005a8: ea1c 5513 andsne.w r5, ip, r3, lsr #20 80005ac: ea94 0f0c teqne r4, ip 80005b0: ea95 0f0c teqne r5, ip 80005b4: f000 f8de bleq 8000774 <__aeabi_dmul+0x1dc> 80005b8: 442c add r4, r5 80005ba: ea81 0603 eor.w r6, r1, r3 80005be: ea21 514c bic.w r1, r1, ip, lsl #21 80005c2: ea23 534c bic.w r3, r3, ip, lsl #21 80005c6: ea50 3501 orrs.w r5, r0, r1, lsl #12 80005ca: bf18 it ne 80005cc: ea52 3503 orrsne.w r5, r2, r3, lsl #12 80005d0: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 80005d4: f443 1380 orr.w r3, r3, #1048576 ; 0x100000 80005d8: d038 beq.n 800064c <__aeabi_dmul+0xb4> 80005da: fba0 ce02 umull ip, lr, r0, r2 80005de: f04f 0500 mov.w r5, #0 80005e2: fbe1 e502 umlal lr, r5, r1, r2 80005e6: f006 4200 and.w r2, r6, #2147483648 ; 0x80000000 80005ea: fbe0 e503 umlal lr, r5, r0, r3 80005ee: f04f 0600 mov.w r6, #0 80005f2: fbe1 5603 umlal r5, r6, r1, r3 80005f6: f09c 0f00 teq ip, #0 80005fa: bf18 it ne 80005fc: f04e 0e01 orrne.w lr, lr, #1 8000600: f1a4 04ff sub.w r4, r4, #255 ; 0xff 8000604: f5b6 7f00 cmp.w r6, #512 ; 0x200 8000608: f564 7440 sbc.w r4, r4, #768 ; 0x300 800060c: d204 bcs.n 8000618 <__aeabi_dmul+0x80> 800060e: ea5f 0e4e movs.w lr, lr, lsl #1 8000612: 416d adcs r5, r5 8000614: eb46 0606 adc.w r6, r6, r6 8000618: ea42 21c6 orr.w r1, r2, r6, lsl #11 800061c: ea41 5155 orr.w r1, r1, r5, lsr #21 8000620: ea4f 20c5 mov.w r0, r5, lsl #11 8000624: ea40 505e orr.w r0, r0, lr, lsr #21 8000628: ea4f 2ece mov.w lr, lr, lsl #11 800062c: f1b4 0cfd subs.w ip, r4, #253 ; 0xfd 8000630: bf88 it hi 8000632: f5bc 6fe0 cmphi.w ip, #1792 ; 0x700 8000636: d81e bhi.n 8000676 <__aeabi_dmul+0xde> 8000638: f1be 4f00 cmp.w lr, #2147483648 ; 0x80000000 800063c: bf08 it eq 800063e: ea5f 0e50 movseq.w lr, r0, lsr #1 8000642: f150 0000 adcs.w r0, r0, #0 8000646: eb41 5104 adc.w r1, r1, r4, lsl #20 800064a: bd70 pop {r4, r5, r6, pc} 800064c: f006 4600 and.w r6, r6, #2147483648 ; 0x80000000 8000650: ea46 0101 orr.w r1, r6, r1 8000654: ea40 0002 orr.w r0, r0, r2 8000658: ea81 0103 eor.w r1, r1, r3 800065c: ebb4 045c subs.w r4, r4, ip, lsr #1 8000660: bfc2 ittt gt 8000662: ebd4 050c rsbsgt r5, r4, ip 8000666: ea41 5104 orrgt.w r1, r1, r4, lsl #20 800066a: bd70 popgt {r4, r5, r6, pc} 800066c: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 8000670: f04f 0e00 mov.w lr, #0 8000674: 3c01 subs r4, #1 8000676: f300 80ab bgt.w 80007d0 <__aeabi_dmul+0x238> 800067a: f114 0f36 cmn.w r4, #54 ; 0x36 800067e: bfde ittt le 8000680: 2000 movle r0, #0 8000682: f001 4100 andle.w r1, r1, #2147483648 ; 0x80000000 8000686: bd70 pople {r4, r5, r6, pc} 8000688: f1c4 0400 rsb r4, r4, #0 800068c: 3c20 subs r4, #32 800068e: da35 bge.n 80006fc <__aeabi_dmul+0x164> 8000690: 340c adds r4, #12 8000692: dc1b bgt.n 80006cc <__aeabi_dmul+0x134> 8000694: f104 0414 add.w r4, r4, #20 8000698: f1c4 0520 rsb r5, r4, #32 800069c: fa00 f305 lsl.w r3, r0, r5 80006a0: fa20 f004 lsr.w r0, r0, r4 80006a4: fa01 f205 lsl.w r2, r1, r5 80006a8: ea40 0002 orr.w r0, r0, r2 80006ac: f001 4200 and.w r2, r1, #2147483648 ; 0x80000000 80006b0: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000 80006b4: eb10 70d3 adds.w r0, r0, r3, lsr #31 80006b8: fa21 f604 lsr.w r6, r1, r4 80006bc: eb42 0106 adc.w r1, r2, r6 80006c0: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 80006c4: bf08 it eq 80006c6: ea20 70d3 biceq.w r0, r0, r3, lsr #31 80006ca: bd70 pop {r4, r5, r6, pc} 80006cc: f1c4 040c rsb r4, r4, #12 80006d0: f1c4 0520 rsb r5, r4, #32 80006d4: fa00 f304 lsl.w r3, r0, r4 80006d8: fa20 f005 lsr.w r0, r0, r5 80006dc: fa01 f204 lsl.w r2, r1, r4 80006e0: ea40 0002 orr.w r0, r0, r2 80006e4: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 80006e8: eb10 70d3 adds.w r0, r0, r3, lsr #31 80006ec: f141 0100 adc.w r1, r1, #0 80006f0: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 80006f4: bf08 it eq 80006f6: ea20 70d3 biceq.w r0, r0, r3, lsr #31 80006fa: bd70 pop {r4, r5, r6, pc} 80006fc: f1c4 0520 rsb r5, r4, #32 8000700: fa00 f205 lsl.w r2, r0, r5 8000704: ea4e 0e02 orr.w lr, lr, r2 8000708: fa20 f304 lsr.w r3, r0, r4 800070c: fa01 f205 lsl.w r2, r1, r5 8000710: ea43 0302 orr.w r3, r3, r2 8000714: fa21 f004 lsr.w r0, r1, r4 8000718: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 800071c: fa21 f204 lsr.w r2, r1, r4 8000720: ea20 0002 bic.w r0, r0, r2 8000724: eb00 70d3 add.w r0, r0, r3, lsr #31 8000728: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 800072c: bf08 it eq 800072e: ea20 70d3 biceq.w r0, r0, r3, lsr #31 8000732: bd70 pop {r4, r5, r6, pc} 8000734: f094 0f00 teq r4, #0 8000738: d10f bne.n 800075a <__aeabi_dmul+0x1c2> 800073a: f001 4600 and.w r6, r1, #2147483648 ; 0x80000000 800073e: 0040 lsls r0, r0, #1 8000740: eb41 0101 adc.w r1, r1, r1 8000744: f411 1f80 tst.w r1, #1048576 ; 0x100000 8000748: bf08 it eq 800074a: 3c01 subeq r4, #1 800074c: d0f7 beq.n 800073e <__aeabi_dmul+0x1a6> 800074e: ea41 0106 orr.w r1, r1, r6 8000752: f095 0f00 teq r5, #0 8000756: bf18 it ne 8000758: 4770 bxne lr 800075a: f003 4600 and.w r6, r3, #2147483648 ; 0x80000000 800075e: 0052 lsls r2, r2, #1 8000760: eb43 0303 adc.w r3, r3, r3 8000764: f413 1f80 tst.w r3, #1048576 ; 0x100000 8000768: bf08 it eq 800076a: 3d01 subeq r5, #1 800076c: d0f7 beq.n 800075e <__aeabi_dmul+0x1c6> 800076e: ea43 0306 orr.w r3, r3, r6 8000772: 4770 bx lr 8000774: ea94 0f0c teq r4, ip 8000778: ea0c 5513 and.w r5, ip, r3, lsr #20 800077c: bf18 it ne 800077e: ea95 0f0c teqne r5, ip 8000782: d00c beq.n 800079e <__aeabi_dmul+0x206> 8000784: ea50 0641 orrs.w r6, r0, r1, lsl #1 8000788: bf18 it ne 800078a: ea52 0643 orrsne.w r6, r2, r3, lsl #1 800078e: d1d1 bne.n 8000734 <__aeabi_dmul+0x19c> 8000790: ea81 0103 eor.w r1, r1, r3 8000794: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 8000798: f04f 0000 mov.w r0, #0 800079c: bd70 pop {r4, r5, r6, pc} 800079e: ea50 0641 orrs.w r6, r0, r1, lsl #1 80007a2: bf06 itte eq 80007a4: 4610 moveq r0, r2 80007a6: 4619 moveq r1, r3 80007a8: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80007ac: d019 beq.n 80007e2 <__aeabi_dmul+0x24a> 80007ae: ea94 0f0c teq r4, ip 80007b2: d102 bne.n 80007ba <__aeabi_dmul+0x222> 80007b4: ea50 3601 orrs.w r6, r0, r1, lsl #12 80007b8: d113 bne.n 80007e2 <__aeabi_dmul+0x24a> 80007ba: ea95 0f0c teq r5, ip 80007be: d105 bne.n 80007cc <__aeabi_dmul+0x234> 80007c0: ea52 3603 orrs.w r6, r2, r3, lsl #12 80007c4: bf1c itt ne 80007c6: 4610 movne r0, r2 80007c8: 4619 movne r1, r3 80007ca: d10a bne.n 80007e2 <__aeabi_dmul+0x24a> 80007cc: ea81 0103 eor.w r1, r1, r3 80007d0: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 80007d4: f041 41fe orr.w r1, r1, #2130706432 ; 0x7f000000 80007d8: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000 80007dc: f04f 0000 mov.w r0, #0 80007e0: bd70 pop {r4, r5, r6, pc} 80007e2: f041 41fe orr.w r1, r1, #2130706432 ; 0x7f000000 80007e6: f441 0178 orr.w r1, r1, #16252928 ; 0xf80000 80007ea: bd70 pop {r4, r5, r6, pc} 080007ec <__aeabi_ddiv>: 80007ec: b570 push {r4, r5, r6, lr} 80007ee: f04f 0cff mov.w ip, #255 ; 0xff 80007f2: f44c 6ce0 orr.w ip, ip, #1792 ; 0x700 80007f6: ea1c 5411 ands.w r4, ip, r1, lsr #20 80007fa: bf1d ittte ne 80007fc: ea1c 5513 andsne.w r5, ip, r3, lsr #20 8000800: ea94 0f0c teqne r4, ip 8000804: ea95 0f0c teqne r5, ip 8000808: f000 f8a7 bleq 800095a <__aeabi_ddiv+0x16e> 800080c: eba4 0405 sub.w r4, r4, r5 8000810: ea81 0e03 eor.w lr, r1, r3 8000814: ea52 3503 orrs.w r5, r2, r3, lsl #12 8000818: ea4f 3101 mov.w r1, r1, lsl #12 800081c: f000 8088 beq.w 8000930 <__aeabi_ddiv+0x144> 8000820: ea4f 3303 mov.w r3, r3, lsl #12 8000824: f04f 5580 mov.w r5, #268435456 ; 0x10000000 8000828: ea45 1313 orr.w r3, r5, r3, lsr #4 800082c: ea43 6312 orr.w r3, r3, r2, lsr #24 8000830: ea4f 2202 mov.w r2, r2, lsl #8 8000834: ea45 1511 orr.w r5, r5, r1, lsr #4 8000838: ea45 6510 orr.w r5, r5, r0, lsr #24 800083c: ea4f 2600 mov.w r6, r0, lsl #8 8000840: f00e 4100 and.w r1, lr, #2147483648 ; 0x80000000 8000844: 429d cmp r5, r3 8000846: bf08 it eq 8000848: 4296 cmpeq r6, r2 800084a: f144 04fd adc.w r4, r4, #253 ; 0xfd 800084e: f504 7440 add.w r4, r4, #768 ; 0x300 8000852: d202 bcs.n 800085a <__aeabi_ddiv+0x6e> 8000854: 085b lsrs r3, r3, #1 8000856: ea4f 0232 mov.w r2, r2, rrx 800085a: 1ab6 subs r6, r6, r2 800085c: eb65 0503 sbc.w r5, r5, r3 8000860: 085b lsrs r3, r3, #1 8000862: ea4f 0232 mov.w r2, r2, rrx 8000866: f44f 1080 mov.w r0, #1048576 ; 0x100000 800086a: f44f 2c00 mov.w ip, #524288 ; 0x80000 800086e: ebb6 0e02 subs.w lr, r6, r2 8000872: eb75 0e03 sbcs.w lr, r5, r3 8000876: bf22 ittt cs 8000878: 1ab6 subcs r6, r6, r2 800087a: 4675 movcs r5, lr 800087c: ea40 000c orrcs.w r0, r0, ip 8000880: 085b lsrs r3, r3, #1 8000882: ea4f 0232 mov.w r2, r2, rrx 8000886: ebb6 0e02 subs.w lr, r6, r2 800088a: eb75 0e03 sbcs.w lr, r5, r3 800088e: bf22 ittt cs 8000890: 1ab6 subcs r6, r6, r2 8000892: 4675 movcs r5, lr 8000894: ea40 005c orrcs.w r0, r0, ip, lsr #1 8000898: 085b lsrs r3, r3, #1 800089a: ea4f 0232 mov.w r2, r2, rrx 800089e: ebb6 0e02 subs.w lr, r6, r2 80008a2: eb75 0e03 sbcs.w lr, r5, r3 80008a6: bf22 ittt cs 80008a8: 1ab6 subcs r6, r6, r2 80008aa: 4675 movcs r5, lr 80008ac: ea40 009c orrcs.w r0, r0, ip, lsr #2 80008b0: 085b lsrs r3, r3, #1 80008b2: ea4f 0232 mov.w r2, r2, rrx 80008b6: ebb6 0e02 subs.w lr, r6, r2 80008ba: eb75 0e03 sbcs.w lr, r5, r3 80008be: bf22 ittt cs 80008c0: 1ab6 subcs r6, r6, r2 80008c2: 4675 movcs r5, lr 80008c4: ea40 00dc orrcs.w r0, r0, ip, lsr #3 80008c8: ea55 0e06 orrs.w lr, r5, r6 80008cc: d018 beq.n 8000900 <__aeabi_ddiv+0x114> 80008ce: ea4f 1505 mov.w r5, r5, lsl #4 80008d2: ea45 7516 orr.w r5, r5, r6, lsr #28 80008d6: ea4f 1606 mov.w r6, r6, lsl #4 80008da: ea4f 03c3 mov.w r3, r3, lsl #3 80008de: ea43 7352 orr.w r3, r3, r2, lsr #29 80008e2: ea4f 02c2 mov.w r2, r2, lsl #3 80008e6: ea5f 1c1c movs.w ip, ip, lsr #4 80008ea: d1c0 bne.n 800086e <__aeabi_ddiv+0x82> 80008ec: f411 1f80 tst.w r1, #1048576 ; 0x100000 80008f0: d10b bne.n 800090a <__aeabi_ddiv+0x11e> 80008f2: ea41 0100 orr.w r1, r1, r0 80008f6: f04f 0000 mov.w r0, #0 80008fa: f04f 4c00 mov.w ip, #2147483648 ; 0x80000000 80008fe: e7b6 b.n 800086e <__aeabi_ddiv+0x82> 8000900: f411 1f80 tst.w r1, #1048576 ; 0x100000 8000904: bf04 itt eq 8000906: 4301 orreq r1, r0 8000908: 2000 moveq r0, #0 800090a: f1b4 0cfd subs.w ip, r4, #253 ; 0xfd 800090e: bf88 it hi 8000910: f5bc 6fe0 cmphi.w ip, #1792 ; 0x700 8000914: f63f aeaf bhi.w 8000676 <__aeabi_dmul+0xde> 8000918: ebb5 0c03 subs.w ip, r5, r3 800091c: bf04 itt eq 800091e: ebb6 0c02 subseq.w ip, r6, r2 8000922: ea5f 0c50 movseq.w ip, r0, lsr #1 8000926: f150 0000 adcs.w r0, r0, #0 800092a: eb41 5104 adc.w r1, r1, r4, lsl #20 800092e: bd70 pop {r4, r5, r6, pc} 8000930: f00e 4e00 and.w lr, lr, #2147483648 ; 0x80000000 8000934: ea4e 3111 orr.w r1, lr, r1, lsr #12 8000938: eb14 045c adds.w r4, r4, ip, lsr #1 800093c: bfc2 ittt gt 800093e: ebd4 050c rsbsgt r5, r4, ip 8000942: ea41 5104 orrgt.w r1, r1, r4, lsl #20 8000946: bd70 popgt {r4, r5, r6, pc} 8000948: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 800094c: f04f 0e00 mov.w lr, #0 8000950: 3c01 subs r4, #1 8000952: e690 b.n 8000676 <__aeabi_dmul+0xde> 8000954: ea45 0e06 orr.w lr, r5, r6 8000958: e68d b.n 8000676 <__aeabi_dmul+0xde> 800095a: ea0c 5513 and.w r5, ip, r3, lsr #20 800095e: ea94 0f0c teq r4, ip 8000962: bf08 it eq 8000964: ea95 0f0c teqeq r5, ip 8000968: f43f af3b beq.w 80007e2 <__aeabi_dmul+0x24a> 800096c: ea94 0f0c teq r4, ip 8000970: d10a bne.n 8000988 <__aeabi_ddiv+0x19c> 8000972: ea50 3401 orrs.w r4, r0, r1, lsl #12 8000976: f47f af34 bne.w 80007e2 <__aeabi_dmul+0x24a> 800097a: ea95 0f0c teq r5, ip 800097e: f47f af25 bne.w 80007cc <__aeabi_dmul+0x234> 8000982: 4610 mov r0, r2 8000984: 4619 mov r1, r3 8000986: e72c b.n 80007e2 <__aeabi_dmul+0x24a> 8000988: ea95 0f0c teq r5, ip 800098c: d106 bne.n 800099c <__aeabi_ddiv+0x1b0> 800098e: ea52 3503 orrs.w r5, r2, r3, lsl #12 8000992: f43f aefd beq.w 8000790 <__aeabi_dmul+0x1f8> 8000996: 4610 mov r0, r2 8000998: 4619 mov r1, r3 800099a: e722 b.n 80007e2 <__aeabi_dmul+0x24a> 800099c: ea50 0641 orrs.w r6, r0, r1, lsl #1 80009a0: bf18 it ne 80009a2: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80009a6: f47f aec5 bne.w 8000734 <__aeabi_dmul+0x19c> 80009aa: ea50 0441 orrs.w r4, r0, r1, lsl #1 80009ae: f47f af0d bne.w 80007cc <__aeabi_dmul+0x234> 80009b2: ea52 0543 orrs.w r5, r2, r3, lsl #1 80009b6: f47f aeeb bne.w 8000790 <__aeabi_dmul+0x1f8> 80009ba: e712 b.n 80007e2 <__aeabi_dmul+0x24a> 080009bc <__gedf2>: 80009bc: f04f 3cff mov.w ip, #4294967295 80009c0: e006 b.n 80009d0 <__cmpdf2+0x4> 80009c2: bf00 nop 080009c4 <__ledf2>: 80009c4: f04f 0c01 mov.w ip, #1 80009c8: e002 b.n 80009d0 <__cmpdf2+0x4> 80009ca: bf00 nop 080009cc <__cmpdf2>: 80009cc: f04f 0c01 mov.w ip, #1 80009d0: f84d cd04 str.w ip, [sp, #-4]! 80009d4: ea4f 0c41 mov.w ip, r1, lsl #1 80009d8: ea7f 5c6c mvns.w ip, ip, asr #21 80009dc: ea4f 0c43 mov.w ip, r3, lsl #1 80009e0: bf18 it ne 80009e2: ea7f 5c6c mvnsne.w ip, ip, asr #21 80009e6: d01b beq.n 8000a20 <__cmpdf2+0x54> 80009e8: b001 add sp, #4 80009ea: ea50 0c41 orrs.w ip, r0, r1, lsl #1 80009ee: bf0c ite eq 80009f0: ea52 0c43 orrseq.w ip, r2, r3, lsl #1 80009f4: ea91 0f03 teqne r1, r3 80009f8: bf02 ittt eq 80009fa: ea90 0f02 teqeq r0, r2 80009fe: 2000 moveq r0, #0 8000a00: 4770 bxeq lr 8000a02: f110 0f00 cmn.w r0, #0 8000a06: ea91 0f03 teq r1, r3 8000a0a: bf58 it pl 8000a0c: 4299 cmppl r1, r3 8000a0e: bf08 it eq 8000a10: 4290 cmpeq r0, r2 8000a12: bf2c ite cs 8000a14: 17d8 asrcs r0, r3, #31 8000a16: ea6f 70e3 mvncc.w r0, r3, asr #31 8000a1a: f040 0001 orr.w r0, r0, #1 8000a1e: 4770 bx lr 8000a20: ea4f 0c41 mov.w ip, r1, lsl #1 8000a24: ea7f 5c6c mvns.w ip, ip, asr #21 8000a28: d102 bne.n 8000a30 <__cmpdf2+0x64> 8000a2a: ea50 3c01 orrs.w ip, r0, r1, lsl #12 8000a2e: d107 bne.n 8000a40 <__cmpdf2+0x74> 8000a30: ea4f 0c43 mov.w ip, r3, lsl #1 8000a34: ea7f 5c6c mvns.w ip, ip, asr #21 8000a38: d1d6 bne.n 80009e8 <__cmpdf2+0x1c> 8000a3a: ea52 3c03 orrs.w ip, r2, r3, lsl #12 8000a3e: d0d3 beq.n 80009e8 <__cmpdf2+0x1c> 8000a40: f85d 0b04 ldr.w r0, [sp], #4 8000a44: 4770 bx lr 8000a46: bf00 nop 08000a48 <__aeabi_cdrcmple>: 8000a48: 4684 mov ip, r0 8000a4a: 4610 mov r0, r2 8000a4c: 4662 mov r2, ip 8000a4e: 468c mov ip, r1 8000a50: 4619 mov r1, r3 8000a52: 4663 mov r3, ip 8000a54: e000 b.n 8000a58 <__aeabi_cdcmpeq> 8000a56: bf00 nop 08000a58 <__aeabi_cdcmpeq>: 8000a58: b501 push {r0, lr} 8000a5a: f7ff ffb7 bl 80009cc <__cmpdf2> 8000a5e: 2800 cmp r0, #0 8000a60: bf48 it mi 8000a62: f110 0f00 cmnmi.w r0, #0 8000a66: bd01 pop {r0, pc} 08000a68 <__aeabi_dcmpeq>: 8000a68: f84d ed08 str.w lr, [sp, #-8]! 8000a6c: f7ff fff4 bl 8000a58 <__aeabi_cdcmpeq> 8000a70: bf0c ite eq 8000a72: 2001 moveq r0, #1 8000a74: 2000 movne r0, #0 8000a76: f85d fb08 ldr.w pc, [sp], #8 8000a7a: bf00 nop 08000a7c <__aeabi_dcmplt>: 8000a7c: f84d ed08 str.w lr, [sp, #-8]! 8000a80: f7ff ffea bl 8000a58 <__aeabi_cdcmpeq> 8000a84: bf34 ite cc 8000a86: 2001 movcc r0, #1 8000a88: 2000 movcs r0, #0 8000a8a: f85d fb08 ldr.w pc, [sp], #8 8000a8e: bf00 nop 08000a90 <__aeabi_dcmple>: 8000a90: f84d ed08 str.w lr, [sp, #-8]! 8000a94: f7ff ffe0 bl 8000a58 <__aeabi_cdcmpeq> 8000a98: bf94 ite ls 8000a9a: 2001 movls r0, #1 8000a9c: 2000 movhi r0, #0 8000a9e: f85d fb08 ldr.w pc, [sp], #8 8000aa2: bf00 nop 08000aa4 <__aeabi_dcmpge>: 8000aa4: f84d ed08 str.w lr, [sp, #-8]! 8000aa8: f7ff ffce bl 8000a48 <__aeabi_cdrcmple> 8000aac: bf94 ite ls 8000aae: 2001 movls r0, #1 8000ab0: 2000 movhi r0, #0 8000ab2: f85d fb08 ldr.w pc, [sp], #8 8000ab6: bf00 nop 08000ab8 <__aeabi_dcmpgt>: 8000ab8: f84d ed08 str.w lr, [sp, #-8]! 8000abc: f7ff ffc4 bl 8000a48 <__aeabi_cdrcmple> 8000ac0: bf34 ite cc 8000ac2: 2001 movcc r0, #1 8000ac4: 2000 movcs r0, #0 8000ac6: f85d fb08 ldr.w pc, [sp], #8 8000aca: bf00 nop 08000acc <__aeabi_dcmpun>: 8000acc: ea4f 0c41 mov.w ip, r1, lsl #1 8000ad0: ea7f 5c6c mvns.w ip, ip, asr #21 8000ad4: d102 bne.n 8000adc <__aeabi_dcmpun+0x10> 8000ad6: ea50 3c01 orrs.w ip, r0, r1, lsl #12 8000ada: d10a bne.n 8000af2 <__aeabi_dcmpun+0x26> 8000adc: ea4f 0c43 mov.w ip, r3, lsl #1 8000ae0: ea7f 5c6c mvns.w ip, ip, asr #21 8000ae4: d102 bne.n 8000aec <__aeabi_dcmpun+0x20> 8000ae6: ea52 3c03 orrs.w ip, r2, r3, lsl #12 8000aea: d102 bne.n 8000af2 <__aeabi_dcmpun+0x26> 8000aec: f04f 0000 mov.w r0, #0 8000af0: 4770 bx lr 8000af2: f04f 0001 mov.w r0, #1 8000af6: 4770 bx lr 08000af8 <__aeabi_d2iz>: 8000af8: ea4f 0241 mov.w r2, r1, lsl #1 8000afc: f512 1200 adds.w r2, r2, #2097152 ; 0x200000 8000b00: d215 bcs.n 8000b2e <__aeabi_d2iz+0x36> 8000b02: d511 bpl.n 8000b28 <__aeabi_d2iz+0x30> 8000b04: f46f 7378 mvn.w r3, #992 ; 0x3e0 8000b08: ebb3 5262 subs.w r2, r3, r2, asr #21 8000b0c: d912 bls.n 8000b34 <__aeabi_d2iz+0x3c> 8000b0e: ea4f 23c1 mov.w r3, r1, lsl #11 8000b12: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 8000b16: ea43 5350 orr.w r3, r3, r0, lsr #21 8000b1a: f011 4f00 tst.w r1, #2147483648 ; 0x80000000 8000b1e: fa23 f002 lsr.w r0, r3, r2 8000b22: bf18 it ne 8000b24: 4240 negne r0, r0 8000b26: 4770 bx lr 8000b28: f04f 0000 mov.w r0, #0 8000b2c: 4770 bx lr 8000b2e: ea50 3001 orrs.w r0, r0, r1, lsl #12 8000b32: d105 bne.n 8000b40 <__aeabi_d2iz+0x48> 8000b34: f011 4000 ands.w r0, r1, #2147483648 ; 0x80000000 8000b38: bf08 it eq 8000b3a: f06f 4000 mvneq.w r0, #2147483648 ; 0x80000000 8000b3e: 4770 bx lr 8000b40: f04f 0000 mov.w r0, #0 8000b44: 4770 bx lr 8000b46: bf00 nop 08000b48 : Nesslab_Prot Currstatus; uint8_t data_Tx[50] = {0,}; extern volatile uint16_t ADC1value[ADC1_CNT]; void NessLab_Operate(uint8_t* data){ 8000b48: b580 push {r7, lr} 8000b4a: b084 sub sp, #16 8000b4c: af00 add r7, sp, #0 8000b4e: 6078 str r0, [r7, #4] uint8_t datatype = data[NessLab_MsgID0]; 8000b50: 687b ldr r3, [r7, #4] 8000b52: 789b ldrb r3, [r3, #2] 8000b54: 73fb strb r3, [r7, #15] switch(datatype){ 8000b56: 7bfb ldrb r3, [r7, #15] 8000b58: 2b65 cmp r3, #101 ; 0x65 8000b5a: d102 bne.n 8000b62 case NessLab_STATUS_REQ: ADC_Check(); 8000b5c: f000 f88c bl 8000c78 break; 8000b60: bf00 nop } NessLab_Frame_Set(data,12); 8000b62: 687b ldr r3, [r7, #4] 8000b64: 210c movs r1, #12 8000b66: 4618 mov r0, r3 8000b68: f000 f809 bl 8000b7e Uart1_Data_Send(&data, 30); 8000b6c: 1d3b adds r3, r7, #4 8000b6e: 211e movs r1, #30 8000b70: 4618 mov r0, r3 8000b72: f000 fa11 bl 8000f98 } 8000b76: bf00 nop 8000b78: 3710 adds r7, #16 8000b7a: 46bd mov sp, r7 8000b7c: bd80 pop {r7, pc} 08000b7e : void NessLab_Frame_Set(uint8_t* data,uint8_t size){ 8000b7e: b590 push {r4, r7, lr} 8000b80: b083 sub sp, #12 8000b82: af00 add r7, sp, #0 8000b84: 6078 str r0, [r7, #4] 8000b86: 460b mov r3, r1 8000b88: 70fb strb r3, [r7, #3] data[NessLab_Header0] = 0x7E; 8000b8a: 687b ldr r3, [r7, #4] 8000b8c: 227e movs r2, #126 ; 0x7e 8000b8e: 701a strb r2, [r3, #0] data[NessLab_Header1] = 0x7E; 8000b90: 687b ldr r3, [r7, #4] 8000b92: 3301 adds r3, #1 8000b94: 227e movs r2, #126 ; 0x7e 8000b96: 701a strb r2, [r3, #0] data[NessLab_MsgID0] = NessLab_STATUS_RES;// ID 8000b98: 687b ldr r3, [r7, #4] 8000b9a: 3302 adds r3, #2 8000b9c: 2266 movs r2, #102 ; 0x66 8000b9e: 701a strb r2, [r3, #0] data[NessLab_MsgSN0] = 0; // SEQ NUMBER 8000ba0: 687b ldr r3, [r7, #4] 8000ba2: 3303 adds r3, #3 8000ba4: 2200 movs r2, #0 8000ba6: 701a strb r2, [r3, #0] data[NessLab_MsgSN1] = 0; // SEQ NUMBER 8000ba8: 687b ldr r3, [r7, #4] 8000baa: 3304 adds r3, #4 8000bac: 2200 movs r2, #0 8000bae: 701a strb r2, [r3, #0] data[NessLab_Reserve0] = 0; // NessLab_Reserve0 8000bb0: 687b ldr r3, [r7, #4] 8000bb2: 3305 adds r3, #5 8000bb4: 2200 movs r2, #0 8000bb6: 701a strb r2, [r3, #0] data[NessLab_DataLength] = size; // Nesslab Size 8000bb8: 687b ldr r3, [r7, #4] 8000bba: 3306 adds r3, #6 8000bbc: 78fa ldrb r2, [r7, #3] 8000bbe: 701a strb r2, [r3, #0] data[NessLab_Data_ADC0_H] = 12; // (uint8_t)((ADC1value & 0xFF00) >> 8); 8000bc0: 687b ldr r3, [r7, #4] 8000bc2: 3307 adds r3, #7 8000bc4: 220c movs r2, #12 8000bc6: 701a strb r2, [r3, #0] data[NessLab_Data_ADC0_L] = 34; // (uint8_t)(ADC1value & 0x00FF); 8000bc8: 687b ldr r3, [r7, #4] 8000bca: 3308 adds r3, #8 8000bcc: 2222 movs r2, #34 ; 0x22 8000bce: 701a strb r2, [r3, #0] data[NessLab_Data_ADC1_H] = 00; 8000bd0: 687b ldr r3, [r7, #4] 8000bd2: 3309 adds r3, #9 8000bd4: 2200 movs r2, #0 8000bd6: 701a strb r2, [r3, #0] data[NessLab_Data_ADC1_L] = 00; 8000bd8: 687b ldr r3, [r7, #4] 8000bda: 330a adds r3, #10 8000bdc: 2200 movs r2, #0 8000bde: 701a strb r2, [r3, #0] data[DC_FAIL_ALARM] = 11; 8000be0: 687b ldr r3, [r7, #4] 8000be2: 330b adds r3, #11 8000be4: 220b movs r2, #11 8000be6: 701a strb r2, [r3, #0] data[NessLab_DownLink_Status] = 22; 8000be8: 687b ldr r3, [r7, #4] 8000bea: 330c adds r3, #12 8000bec: 2216 movs r2, #22 8000bee: 701a strb r2, [r3, #0] data[NessLab_Over_Power_Alarm] = 33; 8000bf0: 687b ldr r3, [r7, #4] 8000bf2: 330d adds r3, #13 8000bf4: 2221 movs r2, #33 ; 0x21 8000bf6: 701a strb r2, [r3, #0] data[NessLab_VSWR_ALARM] = 44; 8000bf8: 687b ldr r3, [r7, #4] 8000bfa: 330e adds r3, #14 8000bfc: 222c movs r2, #44 ; 0x2c 8000bfe: 701a strb r2, [r3, #0] data[NessLab_Over_Input_Alarm] = 55; 8000c00: 687b ldr r3, [r7, #4] 8000c02: 330f adds r3, #15 8000c04: 2237 movs r2, #55 ; 0x37 8000c06: 701a strb r2, [r3, #0] data[NessLab_Over_Temp_Alarm] = 66; 8000c08: 687b ldr r3, [r7, #4] 8000c0a: 3310 adds r3, #16 8000c0c: 2242 movs r2, #66 ; 0x42 8000c0e: 701a strb r2, [r3, #0] data[NessLab_Temp_Monitor] = 77; 8000c10: 687b ldr r3, [r7, #4] 8000c12: 3311 adds r3, #17 8000c14: 224d movs r2, #77 ; 0x4d 8000c16: 701a strb r2, [r3, #0] data[NessLab_ALC_ALARM] = 88; 8000c18: 687b ldr r3, [r7, #4] 8000c1a: 3312 adds r3, #18 8000c1c: 2258 movs r2, #88 ; 0x58 8000c1e: 701a strb r2, [r3, #0] data[NessLab_ChecksumVal] = NessLab_Checksum(0, 17); 8000c20: 687b ldr r3, [r7, #4] 8000c22: f103 0413 add.w r4, r3, #19 8000c26: 2111 movs r1, #17 8000c28: 2000 movs r0, #0 8000c2a: f000 f876 bl 8000d1a 8000c2e: 4603 mov r3, r0 8000c30: 7023 strb r3, [r4, #0] /* Exception Header Tail Checksum */ data[NessLab_Tail0] = 0x7E; 8000c32: 687b ldr r3, [r7, #4] 8000c34: 3314 adds r3, #20 8000c36: 227e movs r2, #126 ; 0x7e 8000c38: 701a strb r2, [r3, #0] data[NessLab_Tail0] = 0x7E; 8000c3a: 687b ldr r3, [r7, #4] 8000c3c: 3314 adds r3, #20 8000c3e: 227e movs r2, #126 ; 0x7e 8000c40: 701a strb r2, [r3, #0] } 8000c42: bf00 nop 8000c44: 370c adds r7, #12 8000c46: 46bd mov sp, r7 8000c48: bd90 pop {r4, r7, pc} ... 08000c4c : /*Temp Calc*/ Currstatus.Temp_Monitor = ((ADC1value[1] & 0xFF00) >> 8); } void ADC_Initialize(){ 8000c4c: b580 push {r7, lr} 8000c4e: af00 add r7, sp, #0 while(!(HAL_ADCEx_Calibration_Start(&hadc1)==HAL_OK)); 8000c50: bf00 nop 8000c52: 4806 ldr r0, [pc, #24] ; (8000c6c ) 8000c54: f000 fe16 bl 8001884 8000c58: 4603 mov r3, r0 8000c5a: 2b00 cmp r3, #0 8000c5c: d1f9 bne.n 8000c52 HAL_ADC_Start_DMA(&hadc1, (uint16_t*)ADC1value,(uint32_t) 3); 8000c5e: 2203 movs r2, #3 8000c60: 4903 ldr r1, [pc, #12] ; (8000c70 ) 8000c62: 4802 ldr r0, [pc, #8] ; (8000c6c ) 8000c64: f000 faac bl 80011c0 } 8000c68: bf00 nop 8000c6a: bd80 pop {r7, pc} 8000c6c: 20000504 .word 0x20000504 8000c70: 20000214 .word 0x20000214 8000c74: 00000000 .word 0x00000000 08000c78 : void ADC_Check(){ 8000c78: b590 push {r4, r7, lr} 8000c7a: b085 sub sp, #20 8000c7c: af00 add r7, sp, #0 double tempval = 0; 8000c7e: f04f 0300 mov.w r3, #0 8000c82: f04f 0400 mov.w r4, #0 8000c86: e9c7 3400 strd r3, r4, [r7] for(int i = 0 ; i < ADC1_CNT; i++){ 8000c8a: 2300 movs r3, #0 8000c8c: 60fb str r3, [r7, #12] 8000c8e: e022 b.n 8000cd6 tempval = (ADC1value[i] * (3.3 / 4095)) * 100; 8000c90: 4a19 ldr r2, [pc, #100] ; (8000cf8 ) 8000c92: 68fb ldr r3, [r7, #12] 8000c94: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8000c98: b29b uxth r3, r3 8000c9a: 4618 mov r0, r3 8000c9c: f7ff fc12 bl 80004c4 <__aeabi_i2d> 8000ca0: a313 add r3, pc, #76 ; (adr r3, 8000cf0 ) 8000ca2: e9d3 2300 ldrd r2, r3, [r3] 8000ca6: f7ff fc77 bl 8000598 <__aeabi_dmul> 8000caa: 4603 mov r3, r0 8000cac: 460c mov r4, r1 8000cae: 4618 mov r0, r3 8000cb0: 4621 mov r1, r4 8000cb2: f04f 0200 mov.w r2, #0 8000cb6: 4b11 ldr r3, [pc, #68] ; (8000cfc ) 8000cb8: f7ff fc6e bl 8000598 <__aeabi_dmul> 8000cbc: 4603 mov r3, r0 8000cbe: 460c mov r4, r1 8000cc0: e9c7 3400 strd r3, r4, [r7] printf("ADC1value[%d] : %f \r\n",i,tempval); 8000cc4: e9d7 2300 ldrd r2, r3, [r7] 8000cc8: 68f9 ldr r1, [r7, #12] 8000cca: 480d ldr r0, [pc, #52] ; (8000d00 ) 8000ccc: f004 fb4e bl 800536c for(int i = 0 ; i < ADC1_CNT; i++){ 8000cd0: 68fb ldr r3, [r7, #12] 8000cd2: 3301 adds r3, #1 8000cd4: 60fb str r3, [r7, #12] 8000cd6: 68fb ldr r3, [r7, #12] 8000cd8: 2b02 cmp r3, #2 8000cda: ddd9 ble.n 8000c90 // // Currstatus.Temp_Monitor // = ((ADC1value[0] & 0xFF00) >> 8); // Currstatus.Temp_Monitor // = ((ADC1value[0] & 0x00FF) ); adc1cnt = 0; 8000cdc: 4b09 ldr r3, [pc, #36] ; (8000d04 ) 8000cde: 2200 movs r2, #0 8000ce0: 801a strh r2, [r3, #0] } 8000ce2: bf00 nop 8000ce4: 3714 adds r7, #20 8000ce6: 46bd mov sp, r7 8000ce8: bd90 pop {r4, r7, pc} 8000cea: bf00 nop 8000cec: f3af 8000 nop.w 8000cf0: e734d9b4 .word 0xe734d9b4 8000cf4: 3f4a680c .word 0x3f4a680c 8000cf8: 20000214 .word 0x20000214 8000cfc: 40590000 .word 0x40590000 8000d00: 08007368 .word 0x08007368 8000d04: 200001f8 .word 0x200001f8 08000d08 : void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) { 8000d08: b480 push {r7} 8000d0a: b083 sub sp, #12 8000d0c: af00 add r7, sp, #0 8000d0e: 6078 str r0, [r7, #4] // ADC1valuearray[i][adc1cnt] = ADC1value[i]; // } // adc1cnt++; // } } } 8000d10: bf00 nop 8000d12: 370c adds r7, #12 8000d14: 46bd mov sp, r7 8000d16: bc80 pop {r7} 8000d18: 4770 bx lr 08000d1a : crcret ^ ~0U; return (crcret == checksum ? CHECKSUM_ERROR : NO_ERROR); } uint8_t NessLab_Checksum(uint8_t *data,uint8_t size){ 8000d1a: b480 push {r7} 8000d1c: b085 sub sp, #20 8000d1e: af00 add r7, sp, #0 8000d20: 6078 str r0, [r7, #4] 8000d22: 460b mov r3, r1 8000d24: 70fb strb r3, [r7, #3] uint8_t ret = 0; 8000d26: 2300 movs r3, #0 8000d28: 73fb strb r3, [r7, #15] for(int i = 0; i < size; i++){ 8000d2a: 2300 movs r3, #0 8000d2c: 60bb str r3, [r7, #8] 8000d2e: e009 b.n 8000d44 ret += data[i]; 8000d30: 68bb ldr r3, [r7, #8] 8000d32: 687a ldr r2, [r7, #4] 8000d34: 4413 add r3, r2 8000d36: 781a ldrb r2, [r3, #0] 8000d38: 7bfb ldrb r3, [r7, #15] 8000d3a: 4413 add r3, r2 8000d3c: 73fb strb r3, [r7, #15] for(int i = 0; i < size; i++){ 8000d3e: 68bb ldr r3, [r7, #8] 8000d40: 3301 adds r3, #1 8000d42: 60bb str r3, [r7, #8] 8000d44: 78fb ldrb r3, [r7, #3] 8000d46: 68ba ldr r2, [r7, #8] 8000d48: 429a cmp r2, r3 8000d4a: dbf1 blt.n 8000d30 } ret = (~ret) + 1; 8000d4c: 7bfb ldrb r3, [r7, #15] 8000d4e: 425b negs r3, r3 8000d50: 73fb strb r3, [r7, #15] return ret; 8000d52: 7bfb ldrb r3, [r7, #15] } 8000d54: 4618 mov r0, r3 8000d56: 3714 adds r7, #20 8000d58: 46bd mov sp, r7 8000d5a: bc80 pop {r7} 8000d5c: 4770 bx lr 08000d5e : bool NessLab_CheckSum_Check(uint8_t* data,uint8_t size,uint8_t checksum){ 8000d5e: b480 push {r7} 8000d60: b085 sub sp, #20 8000d62: af00 add r7, sp, #0 8000d64: 6078 str r0, [r7, #4] 8000d66: 460b mov r3, r1 8000d68: 70fb strb r3, [r7, #3] 8000d6a: 4613 mov r3, r2 8000d6c: 70bb strb r3, [r7, #2] uint8_t dataret = 0; 8000d6e: 2300 movs r3, #0 8000d70: 73fb strb r3, [r7, #15] bool ret = false; 8000d72: 2300 movs r3, #0 8000d74: 73bb strb r3, [r7, #14] for(int i = 0; i < size; i++){ 8000d76: 2300 movs r3, #0 8000d78: 60bb str r3, [r7, #8] 8000d7a: e009 b.n 8000d90 dataret += data[i]; 8000d7c: 68bb ldr r3, [r7, #8] 8000d7e: 687a ldr r2, [r7, #4] 8000d80: 4413 add r3, r2 8000d82: 781a ldrb r2, [r3, #0] 8000d84: 7bfb ldrb r3, [r7, #15] 8000d86: 4413 add r3, r2 8000d88: 73fb strb r3, [r7, #15] for(int i = 0; i < size; i++){ 8000d8a: 68bb ldr r3, [r7, #8] 8000d8c: 3301 adds r3, #1 8000d8e: 60bb str r3, [r7, #8] 8000d90: 78fb ldrb r3, [r7, #3] 8000d92: 68ba ldr r2, [r7, #8] 8000d94: 429a cmp r2, r3 8000d96: dbf1 blt.n 8000d7c } dataret = (~dataret) + 1; 8000d98: 7bfb ldrb r3, [r7, #15] 8000d9a: 425b negs r3, r3 8000d9c: 73fb strb r3, [r7, #15] if(dataret != checksum){ 8000d9e: 7bfa ldrb r2, [r7, #15] 8000da0: 78bb ldrb r3, [r7, #2] 8000da2: 429a cmp r2, r3 8000da4: d002 beq.n 8000dac ret = false; 8000da6: 2300 movs r3, #0 8000da8: 73bb strb r3, [r7, #14] 8000daa: e001 b.n 8000db0 }else{ ret = true; 8000dac: 2301 movs r3, #1 8000dae: 73bb strb r3, [r7, #14] } return ret; 8000db0: 7bbb ldrb r3, [r7, #14] } 8000db2: 4618 mov r0, r3 8000db4: 3714 adds r7, #20 8000db6: 46bd mov sp, r7 8000db8: bc80 pop {r7} 8000dba: 4770 bx lr 08000dbc : #include "main.h" #include "led.h" volatile uint32_t LED_TimerCnt = 0; uint32_t LedTimerCnt_Get(){ 8000dbc: b480 push {r7} 8000dbe: af00 add r7, sp, #0 return LED_TimerCnt; 8000dc0: 4b02 ldr r3, [pc, #8] ; (8000dcc ) 8000dc2: 681b ldr r3, [r3, #0] } 8000dc4: 4618 mov r0, r3 8000dc6: 46bd mov sp, r7 8000dc8: bc80 pop {r7} 8000dca: 4770 bx lr 8000dcc: 200001fc .word 0x200001fc 08000dd0 : void LedTimerCnt_Set(uint32_t val){ 8000dd0: b480 push {r7} 8000dd2: b083 sub sp, #12 8000dd4: af00 add r7, sp, #0 8000dd6: 6078 str r0, [r7, #4] LED_TimerCnt = val; 8000dd8: 4a03 ldr r2, [pc, #12] ; (8000de8 ) 8000dda: 687b ldr r3, [r7, #4] 8000ddc: 6013 str r3, [r2, #0] } 8000dde: bf00 nop 8000de0: 370c adds r7, #12 8000de2: 46bd mov sp, r7 8000de4: bc80 pop {r7} 8000de6: 4770 bx lr 8000de8: 200001fc .word 0x200001fc 08000dec : void Boot_LED_Toggle(){ /*LED Check*/ 8000dec: b580 push {r7, lr} 8000dee: b082 sub sp, #8 8000df0: af00 add r7, sp, #0 uint32_t Led_Cnt = LedTimerCnt_Get(); 8000df2: f7ff ffe3 bl 8000dbc 8000df6: 6078 str r0, [r7, #4] if(Led_Cnt >= LED_TOGGLE_CNT_REF){ 8000df8: 687b ldr r3, [r7, #4] 8000dfa: f5b3 7ffa cmp.w r3, #500 ; 0x1f4 8000dfe: d307 bcc.n 8000e10 HAL_GPIO_TogglePin(BOOT_LED_GPIO_Port, BOOT_LED_Pin); 8000e00: f44f 4100 mov.w r1, #32768 ; 0x8000 8000e04: 4804 ldr r0, [pc, #16] ; (8000e18 ) 8000e06: f001 fa99 bl 800233c LedTimerCnt_Set(0); 8000e0a: 2000 movs r0, #0 8000e0c: f7ff ffe0 bl 8000dd0 } } 8000e10: bf00 nop 8000e12: 3708 adds r7, #8 8000e14: 46bd mov sp, r7 8000e16: bd80 pop {r7, pc} 8000e18: 40011000 .word 0x40011000 08000e1c : extern bool Bluecell_Operate(uint8_t* data); extern void MBIC_Operate(uint8_t * data); extern bool NessLab_CheckSum_Check(uint8_t* data,uint8_t size,uint8_t checksum); void InitUartQueue(pUARTQUEUE pQueue) { 8000e1c: b580 push {r7, lr} 8000e1e: b082 sub sp, #8 8000e20: af00 add r7, sp, #0 8000e22: 6078 str r0, [r7, #4] pQueue->data = pQueue->head = pQueue->tail = 0; 8000e24: 687b ldr r3, [r7, #4] 8000e26: 2200 movs r2, #0 8000e28: 605a str r2, [r3, #4] 8000e2a: 687b ldr r3, [r7, #4] 8000e2c: 685a ldr r2, [r3, #4] 8000e2e: 687b ldr r3, [r7, #4] 8000e30: 601a str r2, [r3, #0] 8000e32: 687b ldr r3, [r7, #4] 8000e34: 681a ldr r2, [r3, #0] 8000e36: 687b ldr r3, [r7, #4] 8000e38: 609a str r2, [r3, #8] uart_hal_tx.output_p = uart_hal_tx.input_p = 0; 8000e3a: 2100 movs r1, #0 8000e3c: 4b08 ldr r3, [pc, #32] ; (8000e60 ) 8000e3e: 460a mov r2, r1 8000e40: f8a3 2080 strh.w r2, [r3, #128] ; 0x80 8000e44: 4b06 ldr r3, [pc, #24] ; (8000e60 ) 8000e46: 460a mov r2, r1 8000e48: f8a3 2082 strh.w r2, [r3, #130] ; 0x82 // HAL_UART_Receive_IT(&huart2,rxBuf,5); if (HAL_UART_Receive_DMA(&hTerminal, TerminalQueue.Buffer, 1) != HAL_OK) 8000e4c: 2201 movs r2, #1 8000e4e: 4905 ldr r1, [pc, #20] ; (8000e64 ) 8000e50: 4805 ldr r0, [pc, #20] ; (8000e68 ) 8000e52: f002 faff bl 8003454 // { //// _Error_Handler(__FILE__, __LINE__); // } //HAL_UART_Receive_DMA(&hTerminal, TerminalQueue.Buffer, 1); //HAL_UART_Receive_IT(hTerminal, pQueue->Buffer + pQueue->head, 1); } 8000e56: bf00 nop 8000e58: 3708 adds r7, #8 8000e5a: 46bd mov sp, r7 8000e5c: bd80 pop {r7, pc} 8000e5e: bf00 nop 8000e60: 20000328 .word 0x20000328 8000e64: 200002a8 .word 0x200002a8 8000e68: 20000534 .word 0x20000534 08000e6c : void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { 8000e6c: b580 push {r7, lr} 8000e6e: b084 sub sp, #16 8000e70: af00 add r7, sp, #0 8000e72: 6078 str r0, [r7, #4] // UART_HandleTypeDef *dst = (huart->Instance == USART2 ? &hTest:&hTerminal); pUARTQUEUE pQueue; // printf("Function : %s : \r\n",__func__); //printf("%02x ",uart_buf[i]); UartRxTimerCnt = 0; 8000e74: 4b15 ldr r3, [pc, #84] ; (8000ecc ) 8000e76: 2200 movs r2, #0 8000e78: 601a str r2, [r3, #0] pQueue = &TerminalQueue; 8000e7a: 4b15 ldr r3, [pc, #84] ; (8000ed0 ) 8000e7c: 60fb str r3, [r7, #12] pQueue->head++; 8000e7e: 68fb ldr r3, [r7, #12] 8000e80: 681b ldr r3, [r3, #0] 8000e82: 1c5a adds r2, r3, #1 8000e84: 68fb ldr r3, [r7, #12] 8000e86: 601a str r2, [r3, #0] if (pQueue->head >= QUEUE_BUFFER_LENGTH) pQueue->head = 0; 8000e88: 68fb ldr r3, [r7, #12] 8000e8a: 681b ldr r3, [r3, #0] 8000e8c: 2b7f cmp r3, #127 ; 0x7f 8000e8e: dd02 ble.n 8000e96 8000e90: 68fb ldr r3, [r7, #12] 8000e92: 2200 movs r2, #0 8000e94: 601a str r2, [r3, #0] pQueue->data++; 8000e96: 68fb ldr r3, [r7, #12] 8000e98: 689b ldr r3, [r3, #8] 8000e9a: 1c5a adds r2, r3, #1 8000e9c: 68fb ldr r3, [r7, #12] 8000e9e: 609a str r2, [r3, #8] if (pQueue->data >= QUEUE_BUFFER_LENGTH) 8000ea0: 68fb ldr r3, [r7, #12] 8000ea2: 689b ldr r3, [r3, #8] 8000ea4: 2b7f cmp r3, #127 ; 0x7f 8000ea6: dd02 ble.n 8000eae GetDataFromUartQueue(huart); 8000ea8: 6878 ldr r0, [r7, #4] 8000eaa: f000 f815 bl 8000ed8 HAL_UART_Receive_IT(&hTerminal, pQueue->Buffer + pQueue->head, 1); 8000eae: 68fb ldr r3, [r7, #12] 8000eb0: 330c adds r3, #12 8000eb2: 68fa ldr r2, [r7, #12] 8000eb4: 6812 ldr r2, [r2, #0] 8000eb6: 4413 add r3, r2 8000eb8: 2201 movs r2, #1 8000eba: 4619 mov r1, r3 8000ebc: 4805 ldr r0, [pc, #20] ; (8000ed4 ) 8000ebe: f002 fa08 bl 80032d2 // HAL_UART_Receive_DMA(&hTest, pQueue->Buffer + pQueue->head, 1); // Set_UartRcv(true); } 8000ec2: bf00 nop 8000ec4: 3710 adds r7, #16 8000ec6: 46bd mov sp, r7 8000ec8: bd80 pop {r7, pc} 8000eca: bf00 nop 8000ecc: 20000204 .word 0x20000204 8000ed0: 2000029c .word 0x2000029c 8000ed4: 20000534 .word 0x20000534 08000ed8 : // HAL_UART_Receive_DMA(&hTerminal, pQueue->Buffer + pQueue->head, 10); } void GetDataFromUartQueue(UART_HandleTypeDef *huart) { 8000ed8: b580 push {r7, lr} 8000eda: b084 sub sp, #16 8000edc: af00 add r7, sp, #0 8000ede: 6078 str r0, [r7, #4] volatile static int cnt; bool ret = 0; 8000ee0: 2300 movs r3, #0 8000ee2: 73fb strb r3, [r7, #15] /* bool chksumret = 0; uint16_t Length = 0; uint16_t CrcChk = 0; UART_HandleTypeDef *dst = (huart->Instance == USART2 ? &hTest:&hTerminal);*/ // UART_HandleTypeDef *dst = &hTerminal; pUARTQUEUE pQueue = &TerminalQueue; 8000ee4: 4b1d ldr r3, [pc, #116] ; (8000f5c ) 8000ee6: 60bb str r3, [r7, #8] // if (HAL_UART_Transmit(dst, pQueue->Buffer + pQueue->tail, 1, 3000) != HAL_OK) // { // _Error_Handler(__FILE__, __LINE__); // } uart_buf[cnt++] = *(pQueue->Buffer + pQueue->tail); 8000ee8: 68bb ldr r3, [r7, #8] 8000eea: 330c adds r3, #12 8000eec: 68ba ldr r2, [r7, #8] 8000eee: 6852 ldr r2, [r2, #4] 8000ef0: 441a add r2, r3 8000ef2: 4b1b ldr r3, [pc, #108] ; (8000f60 ) 8000ef4: 681b ldr r3, [r3, #0] 8000ef6: 1c59 adds r1, r3, #1 8000ef8: 4819 ldr r0, [pc, #100] ; (8000f60 ) 8000efa: 6001 str r1, [r0, #0] 8000efc: 7811 ldrb r1, [r2, #0] 8000efe: 4a19 ldr r2, [pc, #100] ; (8000f64 ) 8000f00: 54d1 strb r1, [r2, r3] //#ifdef DEBUG_PRINT // printf("%02x ",*(pQueue->Buffer + pQueue->tail)) ; //#endif /* DEBUG_PRINT */ pQueue->tail++; 8000f02: 68bb ldr r3, [r7, #8] 8000f04: 685b ldr r3, [r3, #4] 8000f06: 1c5a adds r2, r3, #1 8000f08: 68bb ldr r3, [r7, #8] 8000f0a: 605a str r2, [r3, #4] if (pQueue->tail >= QUEUE_BUFFER_LENGTH) pQueue->tail = 0; 8000f0c: 68bb ldr r3, [r7, #8] 8000f0e: 685b ldr r3, [r3, #4] 8000f10: 2b7f cmp r3, #127 ; 0x7f 8000f12: dd02 ble.n 8000f1a 8000f14: 68bb ldr r3, [r7, #8] 8000f16: 2200 movs r2, #0 8000f18: 605a str r2, [r3, #4] pQueue->data--; 8000f1a: 68bb ldr r3, [r7, #8] 8000f1c: 689b ldr r3, [r3, #8] 8000f1e: 1e5a subs r2, r3, #1 8000f20: 68bb ldr r3, [r7, #8] 8000f22: 609a str r2, [r3, #8] if(pQueue->data == 0){ 8000f24: 68bb ldr r3, [r7, #8] 8000f26: 689b ldr r3, [r3, #8] 8000f28: 2b00 cmp r3, #0 8000f2a: d112 bne.n 8000f52 for(int i = 0; i < cnt; i++){ printf("%02x ",uart_buf[i]); } printf(ANSI_COLOR_GREEN"\r\n CNT : %d \r\n"ANSI_COLOR_RESET,cnt); #endif // PYJ.2019.07.15_END -- ret = NessLab_CheckSum_Check(&uart_buf[NessLab_MsgID0],uart_buf[NessLab_DataLength],uart_buf[NessLab_ChecksumVal]); 8000f2c: 4b0d ldr r3, [pc, #52] ; (8000f64 ) 8000f2e: 7999 ldrb r1, [r3, #6] 8000f30: 4b0c ldr r3, [pc, #48] ; (8000f64 ) 8000f32: 7cdb ldrb r3, [r3, #19] 8000f34: 461a mov r2, r3 8000f36: 480c ldr r0, [pc, #48] ; (8000f68 ) 8000f38: f7ff ff11 bl 8000d5e 8000f3c: 4603 mov r3, r0 8000f3e: 73fb strb r3, [r7, #15] if(ret == true){ 8000f40: 7bfb ldrb r3, [r7, #15] 8000f42: 2b00 cmp r3, #0 8000f44: d002 beq.n 8000f4c NessLab_Operate(&uart_buf[0]); 8000f46: 4807 ldr r0, [pc, #28] ; (8000f64 ) 8000f48: f7ff fdfe bl 8000b48 } cnt = 0; 8000f4c: 4b04 ldr r3, [pc, #16] ; (8000f60 ) 8000f4e: 2200 movs r2, #0 8000f50: 601a str r2, [r3, #0] } } 8000f52: bf00 nop 8000f54: 3710 adds r7, #16 8000f56: 46bd mov sp, r7 8000f58: bd80 pop {r7, pc} 8000f5a: bf00 nop 8000f5c: 2000029c .word 0x2000029c 8000f60: 20000200 .word 0x20000200 8000f64: 2000021c .word 0x2000021c 8000f68: 2000021e .word 0x2000021e 08000f6c : void Uart_Check(void){ 8000f6c: b580 push {r7, lr} 8000f6e: af00 add r7, sp, #0 while (TerminalQueue.data > 0 && UartRxTimerCnt > 50) GetDataFromUartQueue(&hTerminal); 8000f70: e002 b.n 8000f78 8000f72: 4806 ldr r0, [pc, #24] ; (8000f8c ) 8000f74: f7ff ffb0 bl 8000ed8 8000f78: 4b05 ldr r3, [pc, #20] ; (8000f90 ) 8000f7a: 689b ldr r3, [r3, #8] 8000f7c: 2b00 cmp r3, #0 8000f7e: dd03 ble.n 8000f88 8000f80: 4b04 ldr r3, [pc, #16] ; (8000f94 ) 8000f82: 681b ldr r3, [r3, #0] 8000f84: 2b32 cmp r3, #50 ; 0x32 8000f86: d8f4 bhi.n 8000f72 } 8000f88: bf00 nop 8000f8a: bd80 pop {r7, pc} 8000f8c: 20000534 .word 0x20000534 8000f90: 2000029c .word 0x2000029c 8000f94: 20000204 .word 0x20000204 08000f98 : void Uart1_Data_Send(uint8_t* data,uint16_t size){ 8000f98: b580 push {r7, lr} 8000f9a: b082 sub sp, #8 8000f9c: af00 add r7, sp, #0 8000f9e: 6078 str r0, [r7, #4] 8000fa0: 460b mov r3, r1 8000fa2: 807b strh r3, [r7, #2] HAL_UART_Transmit_DMA(&hTerminal, &data[0],size); 8000fa4: 887b ldrh r3, [r7, #2] 8000fa6: 461a mov r2, r3 8000fa8: 6879 ldr r1, [r7, #4] 8000faa: 4803 ldr r0, [pc, #12] ; (8000fb8 ) 8000fac: f002 f9e6 bl 800337c // data[i] = 0; // } // printf("};\r\n\tCOUNT : %d \r\n",size); // printf("\r\n"); } 8000fb0: bf00 nop 8000fb2: 3708 adds r7, #8 8000fb4: 46bd mov sp, r7 8000fb6: bd80 pop {r7, pc} 8000fb8: 20000534 .word 0x20000534 08000fbc : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8000fbc: b580 push {r7, lr} 8000fbe: af00 add r7, sp, #0 __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); #endif #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8000fc0: 2003 movs r0, #3 8000fc2: f000 fdaf bl 8001b24 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 8000fc6: 2000 movs r0, #0 8000fc8: f003 fb90 bl 80046ec /* Init the low level hardware */ HAL_MspInit(); 8000fcc: f003 f9fa bl 80043c4 /* Return function status */ return HAL_OK; 8000fd0: 2300 movs r3, #0 } 8000fd2: 4618 mov r0, r3 8000fd4: bd80 pop {r7, pc} ... 08000fd8 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8000fd8: b480 push {r7} 8000fda: af00 add r7, sp, #0 uwTick += uwTickFreq; 8000fdc: 4b05 ldr r3, [pc, #20] ; (8000ff4 ) 8000fde: 781b ldrb r3, [r3, #0] 8000fe0: 461a mov r2, r3 8000fe2: 4b05 ldr r3, [pc, #20] ; (8000ff8 ) 8000fe4: 681b ldr r3, [r3, #0] 8000fe6: 4413 add r3, r2 8000fe8: 4a03 ldr r2, [pc, #12] ; (8000ff8 ) 8000fea: 6013 str r3, [r2, #0] } 8000fec: bf00 nop 8000fee: 46bd mov sp, r7 8000ff0: bc80 pop {r7} 8000ff2: 4770 bx lr 8000ff4: 20000004 .word 0x20000004 8000ff8: 20000438 .word 0x20000438 08000ffc : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8000ffc: b480 push {r7} 8000ffe: af00 add r7, sp, #0 return uwTick; 8001000: 4b02 ldr r3, [pc, #8] ; (800100c ) 8001002: 681b ldr r3, [r3, #0] } 8001004: 4618 mov r0, r3 8001006: 46bd mov sp, r7 8001008: bc80 pop {r7} 800100a: 4770 bx lr 800100c: 20000438 .word 0x20000438 08001010 : * of structure "ADC_InitTypeDef". * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { 8001010: b580 push {r7, lr} 8001012: b086 sub sp, #24 8001014: af00 add r7, sp, #0 8001016: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8001018: 2300 movs r3, #0 800101a: 75fb strb r3, [r7, #23] uint32_t tmp_cr1 = 0U; 800101c: 2300 movs r3, #0 800101e: 613b str r3, [r7, #16] uint32_t tmp_cr2 = 0U; 8001020: 2300 movs r3, #0 8001022: 60bb str r3, [r7, #8] uint32_t tmp_sqr1 = 0U; 8001024: 2300 movs r3, #0 8001026: 60fb str r3, [r7, #12] /* Check ADC handle */ if(hadc == NULL) 8001028: 687b ldr r3, [r7, #4] 800102a: 2b00 cmp r3, #0 800102c: d101 bne.n 8001032 { return HAL_ERROR; 800102e: 2301 movs r3, #1 8001030: e0be b.n 80011b0 assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) 8001032: 687b ldr r3, [r7, #4] 8001034: 689b ldr r3, [r3, #8] 8001036: 2b00 cmp r3, #0 /* Refer to header of this file for more details on clock enabling */ /* procedure. */ /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) 8001038: 687b ldr r3, [r7, #4] 800103a: 6a9b ldr r3, [r3, #40] ; 0x28 800103c: 2b00 cmp r3, #0 800103e: d109 bne.n 8001054 { /* Initialize ADC error code */ ADC_CLEAR_ERRORCODE(hadc); 8001040: 687b ldr r3, [r7, #4] 8001042: 2200 movs r2, #0 8001044: 62da str r2, [r3, #44] ; 0x2c /* Allocate lock resource and initialize it */ hadc->Lock = HAL_UNLOCKED; 8001046: 687b ldr r3, [r7, #4] 8001048: 2200 movs r2, #0 800104a: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); 800104e: 6878 ldr r0, [r7, #4] 8001050: f003 f9ea bl 8004428 /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ /* Note: In case of ADC already enabled, precaution to not launch an */ /* unwanted conversion while modifying register CR2 by writing 1 to */ /* bit ADON. */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 8001054: 6878 ldr r0, [r7, #4] 8001056: f000 fb75 bl 8001744 800105a: 4603 mov r3, r0 800105c: 75fb strb r3, [r7, #23] /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && 800105e: 687b ldr r3, [r7, #4] 8001060: 6a9b ldr r3, [r3, #40] ; 0x28 8001062: f003 0310 and.w r3, r3, #16 8001066: 2b00 cmp r3, #0 8001068: f040 8099 bne.w 800119e 800106c: 7dfb ldrb r3, [r7, #23] 800106e: 2b00 cmp r3, #0 8001070: f040 8095 bne.w 800119e (tmp_hal_status == HAL_OK) ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8001074: 687b ldr r3, [r7, #4] 8001076: 6a9b ldr r3, [r3, #40] ; 0x28 8001078: f423 5388 bic.w r3, r3, #4352 ; 0x1100 800107c: f023 0302 bic.w r3, r3, #2 8001080: f043 0202 orr.w r2, r3, #2 8001084: 687b ldr r3, [r7, #4] 8001086: 629a str r2, [r3, #40] ; 0x28 /* - continuous conversion mode */ /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */ /* HAL_ADC_Start_xxx functions because if set in this function, */ /* a conversion on injected group would start a conversion also on */ /* regular group after ADC enabling. */ tmp_cr2 |= (hadc->Init.DataAlign | 8001088: 687b ldr r3, [r7, #4] 800108a: 685a ldr r2, [r3, #4] ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 800108c: 687b ldr r3, [r7, #4] 800108e: 69db ldr r3, [r3, #28] tmp_cr2 |= (hadc->Init.DataAlign | 8001090: 431a orrs r2, r3 ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) ); 8001092: 687b ldr r3, [r7, #4] 8001094: 7b1b ldrb r3, [r3, #12] 8001096: 005b lsls r3, r3, #1 ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | 8001098: 4313 orrs r3, r2 tmp_cr2 |= (hadc->Init.DataAlign | 800109a: 68ba ldr r2, [r7, #8] 800109c: 4313 orrs r3, r2 800109e: 60bb str r3, [r7, #8] /* Configuration of ADC: */ /* - scan mode */ /* - discontinuous mode disable/enable */ /* - discontinuous mode number of conversions */ tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode)); 80010a0: 687b ldr r3, [r7, #4] 80010a2: 689b ldr r3, [r3, #8] 80010a4: f5b3 7f80 cmp.w r3, #256 ; 0x100 80010a8: d003 beq.n 80010b2 80010aa: 687b ldr r3, [r7, #4] 80010ac: 689b ldr r3, [r3, #8] 80010ae: 2b01 cmp r3, #1 80010b0: d102 bne.n 80010b8 80010b2: f44f 7380 mov.w r3, #256 ; 0x100 80010b6: e000 b.n 80010ba 80010b8: 2300 movs r3, #0 80010ba: 693a ldr r2, [r7, #16] 80010bc: 4313 orrs r3, r2 80010be: 613b str r3, [r7, #16] /* Enable discontinuous mode only if continuous mode is disabled */ /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */ /* discontinuous is set anyway, but will have no effect on ADC HW. */ if (hadc->Init.DiscontinuousConvMode == ENABLE) 80010c0: 687b ldr r3, [r7, #4] 80010c2: 7d1b ldrb r3, [r3, #20] 80010c4: 2b01 cmp r3, #1 80010c6: d119 bne.n 80010fc { if (hadc->Init.ContinuousConvMode == DISABLE) 80010c8: 687b ldr r3, [r7, #4] 80010ca: 7b1b ldrb r3, [r3, #12] 80010cc: 2b00 cmp r3, #0 80010ce: d109 bne.n 80010e4 { /* Enable the selected ADC regular discontinuous mode */ /* Set the number of channels to be converted in discontinuous mode */ SET_BIT(tmp_cr1, ADC_CR1_DISCEN | 80010d0: 687b ldr r3, [r7, #4] 80010d2: 699b ldr r3, [r3, #24] 80010d4: 3b01 subs r3, #1 80010d6: 035a lsls r2, r3, #13 80010d8: 693b ldr r3, [r7, #16] 80010da: 4313 orrs r3, r2 80010dc: f443 6300 orr.w r3, r3, #2048 ; 0x800 80010e0: 613b str r3, [r7, #16] 80010e2: e00b b.n 80010fc { /* ADC regular group settings continuous and sequencer discontinuous*/ /* cannot be enabled simultaneously. */ /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 80010e4: 687b ldr r3, [r7, #4] 80010e6: 6a9b ldr r3, [r3, #40] ; 0x28 80010e8: f043 0220 orr.w r2, r3, #32 80010ec: 687b ldr r3, [r7, #4] 80010ee: 629a str r2, [r3, #40] ; 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 80010f0: 687b ldr r3, [r7, #4] 80010f2: 6adb ldr r3, [r3, #44] ; 0x2c 80010f4: f043 0201 orr.w r2, r3, #1 80010f8: 687b ldr r3, [r7, #4] 80010fa: 62da str r2, [r3, #44] ; 0x2c } } /* Update ADC configuration register CR1 with previous settings */ MODIFY_REG(hadc->Instance->CR1, 80010fc: 687b ldr r3, [r7, #4] 80010fe: 681b ldr r3, [r3, #0] 8001100: 685b ldr r3, [r3, #4] 8001102: f423 4169 bic.w r1, r3, #59648 ; 0xe900 8001106: 687b ldr r3, [r7, #4] 8001108: 681b ldr r3, [r3, #0] 800110a: 693a ldr r2, [r7, #16] 800110c: 430a orrs r2, r1 800110e: 605a str r2, [r3, #4] ADC_CR1_DISCEN | ADC_CR1_DISCNUM , tmp_cr1 ); /* Update ADC configuration register CR2 with previous settings */ MODIFY_REG(hadc->Instance->CR2, 8001110: 687b ldr r3, [r7, #4] 8001112: 681b ldr r3, [r3, #0] 8001114: 689a ldr r2, [r3, #8] 8001116: 4b28 ldr r3, [pc, #160] ; (80011b8 ) 8001118: 4013 ands r3, r2 800111a: 687a ldr r2, [r7, #4] 800111c: 6812 ldr r2, [r2, #0] 800111e: 68b9 ldr r1, [r7, #8] 8001120: 430b orrs r3, r1 8001122: 6093 str r3, [r2, #8] /* Note: Scan mode is present by hardware on this device and, if */ /* disabled, discards automatically nb of conversions. Anyway, nb of */ /* conversions is forced to 0x00 for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion" */ if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE) 8001124: 687b ldr r3, [r7, #4] 8001126: 689b ldr r3, [r3, #8] 8001128: f5b3 7f80 cmp.w r3, #256 ; 0x100 800112c: d003 beq.n 8001136 800112e: 687b ldr r3, [r7, #4] 8001130: 689b ldr r3, [r3, #8] 8001132: 2b01 cmp r3, #1 8001134: d104 bne.n 8001140 { tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion); 8001136: 687b ldr r3, [r7, #4] 8001138: 691b ldr r3, [r3, #16] 800113a: 3b01 subs r3, #1 800113c: 051b lsls r3, r3, #20 800113e: 60fb str r3, [r7, #12] } MODIFY_REG(hadc->Instance->SQR1, 8001140: 687b ldr r3, [r7, #4] 8001142: 681b ldr r3, [r3, #0] 8001144: 6adb ldr r3, [r3, #44] ; 0x2c 8001146: f423 0170 bic.w r1, r3, #15728640 ; 0xf00000 800114a: 687b ldr r3, [r7, #4] 800114c: 681b ldr r3, [r3, #0] 800114e: 68fa ldr r2, [r7, #12] 8001150: 430a orrs r2, r1 8001152: 62da str r2, [r3, #44] ; 0x2c /* ensure of no potential problem of ADC core IP clocking. */ /* Check through register CR2 (excluding bits set in other functions: */ /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */ /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */ /* measurement path bit (TSVREFE). */ if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 8001154: 687b ldr r3, [r7, #4] 8001156: 681b ldr r3, [r3, #0] 8001158: 689a ldr r2, [r3, #8] 800115a: 4b18 ldr r3, [pc, #96] ; (80011bc ) 800115c: 4013 ands r3, r2 800115e: 68ba ldr r2, [r7, #8] 8001160: 429a cmp r2, r3 8001162: d10b bne.n 800117c ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL | ADC_CR2_TSVREFE )) == tmp_cr2) { /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 8001164: 687b ldr r3, [r7, #4] 8001166: 2200 movs r2, #0 8001168: 62da str r2, [r3, #44] ; 0x2c /* Set the ADC state */ ADC_STATE_CLR_SET(hadc->State, 800116a: 687b ldr r3, [r7, #4] 800116c: 6a9b ldr r3, [r3, #40] ; 0x28 800116e: f023 0303 bic.w r3, r3, #3 8001172: f043 0201 orr.w r2, r3, #1 8001176: 687b ldr r3, [r7, #4] 8001178: 629a str r2, [r3, #40] ; 0x28 if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 800117a: e018 b.n 80011ae HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 800117c: 687b ldr r3, [r7, #4] 800117e: 6a9b ldr r3, [r3, #40] ; 0x28 8001180: f023 0312 bic.w r3, r3, #18 8001184: f043 0210 orr.w r2, r3, #16 8001188: 687b ldr r3, [r7, #4] 800118a: 629a str r2, [r3, #40] ; 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800118c: 687b ldr r3, [r7, #4] 800118e: 6adb ldr r3, [r3, #44] ; 0x2c 8001190: f043 0201 orr.w r2, r3, #1 8001194: 687b ldr r3, [r7, #4] 8001196: 62da str r2, [r3, #44] ; 0x2c tmp_hal_status = HAL_ERROR; 8001198: 2301 movs r3, #1 800119a: 75fb strb r3, [r7, #23] if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | 800119c: e007 b.n 80011ae } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800119e: 687b ldr r3, [r7, #4] 80011a0: 6a9b ldr r3, [r3, #40] ; 0x28 80011a2: f043 0210 orr.w r2, r3, #16 80011a6: 687b ldr r3, [r7, #4] 80011a8: 629a str r2, [r3, #40] ; 0x28 tmp_hal_status = HAL_ERROR; 80011aa: 2301 movs r3, #1 80011ac: 75fb strb r3, [r7, #23] } /* Return function status */ return tmp_hal_status; 80011ae: 7dfb ldrb r3, [r7, #23] } 80011b0: 4618 mov r0, r3 80011b2: 3718 adds r7, #24 80011b4: 46bd mov sp, r7 80011b6: bd80 pop {r7, pc} 80011b8: ffe1f7fd .word 0xffe1f7fd 80011bc: ff1f0efe .word 0xff1f0efe 080011c0 : * @param pData: The destination Buffer address. * @param Length: The length of data to be transferred from ADC peripheral to memory. * @retval None */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) { 80011c0: b580 push {r7, lr} 80011c2: b086 sub sp, #24 80011c4: af00 add r7, sp, #0 80011c6: 60f8 str r0, [r7, #12] 80011c8: 60b9 str r1, [r7, #8] 80011ca: 607a str r2, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 80011cc: 2300 movs r3, #0 80011ce: 75fb strb r3, [r7, #23] /* If multimode is enabled, dedicated function multimode conversion */ /* start DMA must be used. */ if(ADC_MULTIMODE_IS_ENABLE(hadc) == RESET) { /* Process locked */ __HAL_LOCK(hadc); 80011d0: 68fb ldr r3, [r7, #12] 80011d2: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 80011d6: 2b01 cmp r3, #1 80011d8: d101 bne.n 80011de 80011da: 2302 movs r3, #2 80011dc: e080 b.n 80012e0 80011de: 68fb ldr r3, [r7, #12] 80011e0: 2201 movs r2, #1 80011e2: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); 80011e6: 68f8 ldr r0, [r7, #12] 80011e8: f000 fa5a bl 80016a0 80011ec: 4603 mov r3, r0 80011ee: 75fb strb r3, [r7, #23] /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) 80011f0: 7dfb ldrb r3, [r7, #23] 80011f2: 2b00 cmp r3, #0 80011f4: d16f bne.n 80012d6 { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, 80011f6: 68fb ldr r3, [r7, #12] 80011f8: 6a9b ldr r3, [r3, #40] ; 0x28 80011fa: f423 6370 bic.w r3, r3, #3840 ; 0xf00 80011fe: f023 0301 bic.w r3, r3, #1 8001202: f443 7280 orr.w r2, r3, #256 ; 0x100 8001206: 68fb ldr r3, [r7, #12] 8001208: 629a str r2, [r3, #40] ; 0x28 /* for all cases of multimode: independent mode, multimode ADC master */ /* or multimode ADC slave (for devices with several ADCs): */ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) { /* Set ADC state (ADC independent or master) */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 800120a: 68fb ldr r3, [r7, #12] 800120c: 6a9b ldr r3, [r3, #40] ; 0x28 800120e: f423 1280 bic.w r2, r3, #1048576 ; 0x100000 8001212: 68fb ldr r3, [r7, #12] 8001214: 629a str r2, [r3, #40] ; 0x28 /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) 8001216: 68fb ldr r3, [r7, #12] 8001218: 681b ldr r3, [r3, #0] 800121a: 685b ldr r3, [r3, #4] 800121c: f403 6380 and.w r3, r3, #1024 ; 0x400 8001220: 2b00 cmp r3, #0 8001222: d007 beq.n 8001234 { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 8001224: 68fb ldr r3, [r7, #12] 8001226: 6a9b ldr r3, [r3, #40] ; 0x28 8001228: f423 5340 bic.w r3, r3, #12288 ; 0x3000 800122c: f443 5280 orr.w r2, r3, #4096 ; 0x1000 8001230: 68fb ldr r3, [r7, #12] 8001232: 629a str r2, [r3, #40] ; 0x28 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } } /* State machine update: Check if an injected conversion is ongoing */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 8001234: 68fb ldr r3, [r7, #12] 8001236: 6a9b ldr r3, [r3, #40] ; 0x28 8001238: f403 5380 and.w r3, r3, #4096 ; 0x1000 800123c: 2b00 cmp r3, #0 800123e: d006 beq.n 800124e { /* Reset ADC error code fields related to conversions on group regular */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); 8001240: 68fb ldr r3, [r7, #12] 8001242: 6adb ldr r3, [r3, #44] ; 0x2c 8001244: f023 0206 bic.w r2, r3, #6 8001248: 68fb ldr r3, [r7, #12] 800124a: 62da str r2, [r3, #44] ; 0x2c 800124c: e002 b.n 8001254 } else { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); 800124e: 68fb ldr r3, [r7, #12] 8001250: 2200 movs r2, #0 8001252: 62da str r2, [r3, #44] ; 0x2c } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); 8001254: 68fb ldr r3, [r7, #12] 8001256: 2200 movs r2, #0 8001258: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; 800125c: 68fb ldr r3, [r7, #12] 800125e: 6a1b ldr r3, [r3, #32] 8001260: 4a21 ldr r2, [pc, #132] ; (80012e8 ) 8001262: 629a str r2, [r3, #40] ; 0x28 /* Set the DMA half transfer complete callback */ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; 8001264: 68fb ldr r3, [r7, #12] 8001266: 6a1b ldr r3, [r3, #32] 8001268: 4a20 ldr r2, [pc, #128] ; (80012ec ) 800126a: 62da str r2, [r3, #44] ; 0x2c /* Set the DMA error callback */ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; 800126c: 68fb ldr r3, [r7, #12] 800126e: 6a1b ldr r3, [r3, #32] 8001270: 4a1f ldr r2, [pc, #124] ; (80012f0 ) 8001272: 631a str r2, [r3, #48] ; 0x30 /* start (in case of SW start): */ /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC */ /* operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); 8001274: 68fb ldr r3, [r7, #12] 8001276: 681b ldr r3, [r3, #0] 8001278: f06f 0202 mvn.w r2, #2 800127c: 601a str r2, [r3, #0] /* Enable ADC DMA mode */ SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA); 800127e: 68fb ldr r3, [r7, #12] 8001280: 681b ldr r3, [r3, #0] 8001282: 689a ldr r2, [r3, #8] 8001284: 68fb ldr r3, [r7, #12] 8001286: 681b ldr r3, [r3, #0] 8001288: f442 7280 orr.w r2, r2, #256 ; 0x100 800128c: 609a str r2, [r3, #8] /* Start the DMA channel */ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); 800128e: 68fb ldr r3, [r7, #12] 8001290: 6a18 ldr r0, [r3, #32] 8001292: 68fb ldr r3, [r7, #12] 8001294: 681b ldr r3, [r3, #0] 8001296: 334c adds r3, #76 ; 0x4c 8001298: 4619 mov r1, r3 800129a: 68ba ldr r2, [r7, #8] 800129c: 687b ldr r3, [r7, #4] 800129e: f000 fcd1 bl 8001c44 /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ if (ADC_IS_SOFTWARE_START_REGULAR(hadc)) 80012a2: 68fb ldr r3, [r7, #12] 80012a4: 681b ldr r3, [r3, #0] 80012a6: 689b ldr r3, [r3, #8] 80012a8: f403 2360 and.w r3, r3, #917504 ; 0xe0000 80012ac: f5b3 2f60 cmp.w r3, #917504 ; 0xe0000 80012b0: d108 bne.n 80012c4 { /* Start ADC conversion on regular group with SW start */ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); 80012b2: 68fb ldr r3, [r7, #12] 80012b4: 681b ldr r3, [r3, #0] 80012b6: 689a ldr r2, [r3, #8] 80012b8: 68fb ldr r3, [r7, #12] 80012ba: 681b ldr r3, [r3, #0] 80012bc: f442 02a0 orr.w r2, r2, #5242880 ; 0x500000 80012c0: 609a str r2, [r3, #8] 80012c2: e00c b.n 80012de } else { /* Start ADC conversion on regular group with external trigger */ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); 80012c4: 68fb ldr r3, [r7, #12] 80012c6: 681b ldr r3, [r3, #0] 80012c8: 689a ldr r2, [r3, #8] 80012ca: 68fb ldr r3, [r7, #12] 80012cc: 681b ldr r3, [r3, #0] 80012ce: f442 1280 orr.w r2, r2, #1048576 ; 0x100000 80012d2: 609a str r2, [r3, #8] 80012d4: e003 b.n 80012de } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); 80012d6: 68fb ldr r3, [r7, #12] 80012d8: 2200 movs r2, #0 80012da: f883 2024 strb.w r2, [r3, #36] ; 0x24 { tmp_hal_status = HAL_ERROR; } /* Return function status */ return tmp_hal_status; 80012de: 7dfb ldrb r3, [r7, #23] } 80012e0: 4618 mov r0, r3 80012e2: 3718 adds r7, #24 80012e4: 46bd mov sp, r7 80012e6: bd80 pop {r7, pc} 80012e8: 080017b9 .word 0x080017b9 80012ec: 08001835 .word 0x08001835 80012f0: 08001851 .word 0x08001851 080012f4 : * @brief Handles ADC interrupt request * @param hadc: ADC handle * @retval None */ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) { 80012f4: b580 push {r7, lr} 80012f6: b082 sub sp, #8 80012f8: af00 add r7, sp, #0 80012fa: 6078 str r0, [r7, #4] assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); /* ========== Check End of Conversion flag for regular group ========== */ if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) 80012fc: 687b ldr r3, [r7, #4] 80012fe: 681b ldr r3, [r3, #0] 8001300: 685b ldr r3, [r3, #4] 8001302: f003 0320 and.w r3, r3, #32 8001306: 2b20 cmp r3, #32 8001308: d140 bne.n 800138c { if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) ) 800130a: 687b ldr r3, [r7, #4] 800130c: 681b ldr r3, [r3, #0] 800130e: 681b ldr r3, [r3, #0] 8001310: f003 0302 and.w r3, r3, #2 8001314: 2b02 cmp r3, #2 8001316: d139 bne.n 800138c { /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) 8001318: 687b ldr r3, [r7, #4] 800131a: 6a9b ldr r3, [r3, #40] ; 0x28 800131c: f003 0310 and.w r3, r3, #16 8001320: 2b00 cmp r3, #0 8001322: d105 bne.n 8001330 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 8001324: 687b ldr r3, [r7, #4] 8001326: 6a9b ldr r3, [r3, #40] ; 0x28 8001328: f443 7200 orr.w r2, r3, #512 ; 0x200 800132c: 687b ldr r3, [r7, #4] 800132e: 629a str r2, [r3, #40] ; 0x28 /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 8001330: 687b ldr r3, [r7, #4] 8001332: 681b ldr r3, [r3, #0] 8001334: 689b ldr r3, [r3, #8] 8001336: f403 2360 and.w r3, r3, #917504 ; 0xe0000 800133a: f5b3 2f60 cmp.w r3, #917504 ; 0xe0000 800133e: d11d bne.n 800137c (hadc->Init.ContinuousConvMode == DISABLE) ) 8001340: 687b ldr r3, [r7, #4] 8001342: 7b1b ldrb r3, [r3, #12] if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 8001344: 2b00 cmp r3, #0 8001346: d119 bne.n 800137c { /* Disable ADC end of conversion interrupt on group regular */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); 8001348: 687b ldr r3, [r7, #4] 800134a: 681b ldr r3, [r3, #0] 800134c: 685a ldr r2, [r3, #4] 800134e: 687b ldr r3, [r7, #4] 8001350: 681b ldr r3, [r3, #0] 8001352: f022 0220 bic.w r2, r2, #32 8001356: 605a str r2, [r3, #4] /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 8001358: 687b ldr r3, [r7, #4] 800135a: 6a9b ldr r3, [r3, #40] ; 0x28 800135c: f423 7280 bic.w r2, r3, #256 ; 0x100 8001360: 687b ldr r3, [r7, #4] 8001362: 629a str r2, [r3, #40] ; 0x28 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 8001364: 687b ldr r3, [r7, #4] 8001366: 6a9b ldr r3, [r3, #40] ; 0x28 8001368: f403 5380 and.w r3, r3, #4096 ; 0x1000 800136c: 2b00 cmp r3, #0 800136e: d105 bne.n 800137c { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 8001370: 687b ldr r3, [r7, #4] 8001372: 6a9b ldr r3, [r3, #40] ; 0x28 8001374: f043 0201 orr.w r2, r3, #1 8001378: 687b ldr r3, [r7, #4] 800137a: 629a str r2, [r3, #40] ; 0x28 /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); 800137c: 6878 ldr r0, [r7, #4] 800137e: f7ff fcc3 bl 8000d08 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear regular group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); 8001382: 687b ldr r3, [r7, #4] 8001384: 681b ldr r3, [r3, #0] 8001386: f06f 0212 mvn.w r2, #18 800138a: 601a str r2, [r3, #0] } } /* ========== Check End of Conversion flag for injected group ========== */ if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC)) 800138c: 687b ldr r3, [r7, #4] 800138e: 681b ldr r3, [r3, #0] 8001390: 685b ldr r3, [r3, #4] 8001392: f003 0380 and.w r3, r3, #128 ; 0x80 8001396: 2b80 cmp r3, #128 ; 0x80 8001398: d14f bne.n 800143a { if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC)) 800139a: 687b ldr r3, [r7, #4] 800139c: 681b ldr r3, [r3, #0] 800139e: 681b ldr r3, [r3, #0] 80013a0: f003 0304 and.w r3, r3, #4 80013a4: 2b04 cmp r3, #4 80013a6: d148 bne.n 800143a { /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) 80013a8: 687b ldr r3, [r7, #4] 80013aa: 6a9b ldr r3, [r3, #40] ; 0x28 80013ac: f003 0310 and.w r3, r3, #16 80013b0: 2b00 cmp r3, #0 80013b2: d105 bne.n 80013c0 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); 80013b4: 687b ldr r3, [r7, #4] 80013b6: 6a9b ldr r3, [r3, #40] ; 0x28 80013b8: f443 5200 orr.w r2, r3, #8192 ; 0x2000 80013bc: 687b ldr r3, [r7, #4] 80013be: 629a str r2, [r3, #40] ; 0x28 /* conversion from group regular (same conditions as group regular */ /* interruption disabling above). */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_INJECTED(hadc) || 80013c0: 687b ldr r3, [r7, #4] 80013c2: 681b ldr r3, [r3, #0] 80013c4: 689b ldr r3, [r3, #8] 80013c6: f403 43e0 and.w r3, r3, #28672 ; 0x7000 80013ca: f5b3 4fe0 cmp.w r3, #28672 ; 0x7000 80013ce: d012 beq.n 80013f6 (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && 80013d0: 687b ldr r3, [r7, #4] 80013d2: 681b ldr r3, [r3, #0] 80013d4: 685b ldr r3, [r3, #4] 80013d6: f403 6380 and.w r3, r3, #1024 ; 0x400 if(ADC_IS_SOFTWARE_START_INJECTED(hadc) || 80013da: 2b00 cmp r3, #0 80013dc: d125 bne.n 800142a (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 80013de: 687b ldr r3, [r7, #4] 80013e0: 681b ldr r3, [r3, #0] 80013e2: 689b ldr r3, [r3, #8] 80013e4: f403 2360 and.w r3, r3, #917504 ; 0xe0000 (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && 80013e8: f5b3 2f60 cmp.w r3, #917504 ; 0xe0000 80013ec: d11d bne.n 800142a (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) 80013ee: 687b ldr r3, [r7, #4] 80013f0: 7b1b ldrb r3, [r3, #12] (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 80013f2: 2b00 cmp r3, #0 80013f4: d119 bne.n 800142a { /* Disable ADC end of conversion interrupt on group injected */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); 80013f6: 687b ldr r3, [r7, #4] 80013f8: 681b ldr r3, [r3, #0] 80013fa: 685a ldr r2, [r3, #4] 80013fc: 687b ldr r3, [r7, #4] 80013fe: 681b ldr r3, [r3, #0] 8001400: f022 0280 bic.w r2, r2, #128 ; 0x80 8001404: 605a str r2, [r3, #4] /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); 8001406: 687b ldr r3, [r7, #4] 8001408: 6a9b ldr r3, [r3, #40] ; 0x28 800140a: f423 5280 bic.w r2, r3, #4096 ; 0x1000 800140e: 687b ldr r3, [r7, #4] 8001410: 629a str r2, [r3, #40] ; 0x28 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) 8001412: 687b ldr r3, [r7, #4] 8001414: 6a9b ldr r3, [r3, #40] ; 0x28 8001416: f403 7380 and.w r3, r3, #256 ; 0x100 800141a: 2b00 cmp r3, #0 800141c: d105 bne.n 800142a { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 800141e: 687b ldr r3, [r7, #4] 8001420: 6a9b ldr r3, [r3, #40] ; 0x28 8001422: f043 0201 orr.w r2, r3, #1 8001426: 687b ldr r3, [r7, #4] 8001428: 629a str r2, [r3, #40] ; 0x28 /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->InjectedConvCpltCallback(hadc); #else HAL_ADCEx_InjectedConvCpltCallback(hadc); 800142a: 6878 ldr r0, [r7, #4] 800142c: f000 fac6 bl 80019bc #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear injected group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC)); 8001430: 687b ldr r3, [r7, #4] 8001432: 681b ldr r3, [r3, #0] 8001434: f06f 020c mvn.w r2, #12 8001438: 601a str r2, [r3, #0] } } /* ========== Check Analog watchdog flags ========== */ if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD)) 800143a: 687b ldr r3, [r7, #4] 800143c: 681b ldr r3, [r3, #0] 800143e: 685b ldr r3, [r3, #4] 8001440: f003 0340 and.w r3, r3, #64 ; 0x40 8001444: 2b40 cmp r3, #64 ; 0x40 8001446: d114 bne.n 8001472 { if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD)) 8001448: 687b ldr r3, [r7, #4] 800144a: 681b ldr r3, [r3, #0] 800144c: 681b ldr r3, [r3, #0] 800144e: f003 0301 and.w r3, r3, #1 8001452: 2b01 cmp r3, #1 8001454: d10d bne.n 8001472 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); 8001456: 687b ldr r3, [r7, #4] 8001458: 6a9b ldr r3, [r3, #40] ; 0x28 800145a: f443 3280 orr.w r2, r3, #65536 ; 0x10000 800145e: 687b ldr r3, [r7, #4] 8001460: 629a str r2, [r3, #40] ; 0x28 /* Level out of window callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->LevelOutOfWindowCallback(hadc); #else HAL_ADC_LevelOutOfWindowCallback(hadc); 8001462: 6878 ldr r0, [r7, #4] 8001464: f000 f812 bl 800148c #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear the ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); 8001468: 687b ldr r3, [r7, #4] 800146a: 681b ldr r3, [r3, #0] 800146c: f06f 0201 mvn.w r2, #1 8001470: 601a str r2, [r3, #0] } } } 8001472: bf00 nop 8001474: 3708 adds r7, #8 8001476: 46bd mov sp, r7 8001478: bd80 pop {r7, pc} 0800147a : * @brief Conversion DMA half-transfer callback in non blocking mode * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) { 800147a: b480 push {r7} 800147c: b083 sub sp, #12 800147e: af00 add r7, sp, #0 8001480: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. */ } 8001482: bf00 nop 8001484: 370c adds r7, #12 8001486: 46bd mov sp, r7 8001488: bc80 pop {r7} 800148a: 4770 bx lr 0800148c : * @brief Analog watchdog callback in non blocking mode. * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) { 800148c: b480 push {r7} 800148e: b083 sub sp, #12 8001490: af00 add r7, sp, #0 8001492: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file. */ } 8001494: bf00 nop 8001496: 370c adds r7, #12 8001498: 46bd mov sp, r7 800149a: bc80 pop {r7} 800149c: 4770 bx lr 0800149e : * (ADC conversion with interruption or transfer by DMA) * @param hadc: ADC handle * @retval None */ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) { 800149e: b480 push {r7} 80014a0: b083 sub sp, #12 80014a2: af00 add r7, sp, #0 80014a4: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ErrorCallback must be implemented in the user file. */ } 80014a6: bf00 nop 80014a8: 370c adds r7, #12 80014aa: 46bd mov sp, r7 80014ac: bc80 pop {r7} 80014ae: 4770 bx lr 080014b0 : * @param hadc: ADC handle * @param sConfig: Structure of ADC channel for regular group. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { 80014b0: b480 push {r7} 80014b2: b085 sub sp, #20 80014b4: af00 add r7, sp, #0 80014b6: 6078 str r0, [r7, #4] 80014b8: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 80014ba: 2300 movs r3, #0 80014bc: 73fb strb r3, [r7, #15] __IO uint32_t wait_loop_index = 0U; 80014be: 2300 movs r3, #0 80014c0: 60bb str r3, [r7, #8] assert_param(IS_ADC_CHANNEL(sConfig->Channel)); assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); /* Process locked */ __HAL_LOCK(hadc); 80014c2: 687b ldr r3, [r7, #4] 80014c4: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 80014c8: 2b01 cmp r3, #1 80014ca: d101 bne.n 80014d0 80014cc: 2302 movs r3, #2 80014ce: e0dc b.n 800168a 80014d0: 687b ldr r3, [r7, #4] 80014d2: 2201 movs r2, #1 80014d4: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Regular sequence configuration */ /* For Rank 1 to 6 */ if (sConfig->Rank < 7U) 80014d8: 683b ldr r3, [r7, #0] 80014da: 685b ldr r3, [r3, #4] 80014dc: 2b06 cmp r3, #6 80014de: d81c bhi.n 800151a { MODIFY_REG(hadc->Instance->SQR3 , 80014e0: 687b ldr r3, [r7, #4] 80014e2: 681b ldr r3, [r3, #0] 80014e4: 6b59 ldr r1, [r3, #52] ; 0x34 80014e6: 683b ldr r3, [r7, #0] 80014e8: 685a ldr r2, [r3, #4] 80014ea: 4613 mov r3, r2 80014ec: 009b lsls r3, r3, #2 80014ee: 4413 add r3, r2 80014f0: 3b05 subs r3, #5 80014f2: 221f movs r2, #31 80014f4: fa02 f303 lsl.w r3, r2, r3 80014f8: 43db mvns r3, r3 80014fa: 4019 ands r1, r3 80014fc: 683b ldr r3, [r7, #0] 80014fe: 6818 ldr r0, [r3, #0] 8001500: 683b ldr r3, [r7, #0] 8001502: 685a ldr r2, [r3, #4] 8001504: 4613 mov r3, r2 8001506: 009b lsls r3, r3, #2 8001508: 4413 add r3, r2 800150a: 3b05 subs r3, #5 800150c: fa00 f203 lsl.w r2, r0, r3 8001510: 687b ldr r3, [r7, #4] 8001512: 681b ldr r3, [r3, #0] 8001514: 430a orrs r2, r1 8001516: 635a str r2, [r3, #52] ; 0x34 8001518: e03c b.n 8001594 ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) , ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 7 to 12 */ else if (sConfig->Rank < 13U) 800151a: 683b ldr r3, [r7, #0] 800151c: 685b ldr r3, [r3, #4] 800151e: 2b0c cmp r3, #12 8001520: d81c bhi.n 800155c { MODIFY_REG(hadc->Instance->SQR2 , 8001522: 687b ldr r3, [r7, #4] 8001524: 681b ldr r3, [r3, #0] 8001526: 6b19 ldr r1, [r3, #48] ; 0x30 8001528: 683b ldr r3, [r7, #0] 800152a: 685a ldr r2, [r3, #4] 800152c: 4613 mov r3, r2 800152e: 009b lsls r3, r3, #2 8001530: 4413 add r3, r2 8001532: 3b23 subs r3, #35 ; 0x23 8001534: 221f movs r2, #31 8001536: fa02 f303 lsl.w r3, r2, r3 800153a: 43db mvns r3, r3 800153c: 4019 ands r1, r3 800153e: 683b ldr r3, [r7, #0] 8001540: 6818 ldr r0, [r3, #0] 8001542: 683b ldr r3, [r7, #0] 8001544: 685a ldr r2, [r3, #4] 8001546: 4613 mov r3, r2 8001548: 009b lsls r3, r3, #2 800154a: 4413 add r3, r2 800154c: 3b23 subs r3, #35 ; 0x23 800154e: fa00 f203 lsl.w r2, r0, r3 8001552: 687b ldr r3, [r7, #4] 8001554: 681b ldr r3, [r3, #0] 8001556: 430a orrs r2, r1 8001558: 631a str r2, [r3, #48] ; 0x30 800155a: e01b b.n 8001594 ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 13 to 16 */ else { MODIFY_REG(hadc->Instance->SQR1 , 800155c: 687b ldr r3, [r7, #4] 800155e: 681b ldr r3, [r3, #0] 8001560: 6ad9 ldr r1, [r3, #44] ; 0x2c 8001562: 683b ldr r3, [r7, #0] 8001564: 685a ldr r2, [r3, #4] 8001566: 4613 mov r3, r2 8001568: 009b lsls r3, r3, #2 800156a: 4413 add r3, r2 800156c: 3b41 subs r3, #65 ; 0x41 800156e: 221f movs r2, #31 8001570: fa02 f303 lsl.w r3, r2, r3 8001574: 43db mvns r3, r3 8001576: 4019 ands r1, r3 8001578: 683b ldr r3, [r7, #0] 800157a: 6818 ldr r0, [r3, #0] 800157c: 683b ldr r3, [r7, #0] 800157e: 685a ldr r2, [r3, #4] 8001580: 4613 mov r3, r2 8001582: 009b lsls r3, r3, #2 8001584: 4413 add r3, r2 8001586: 3b41 subs r3, #65 ; 0x41 8001588: fa00 f203 lsl.w r2, r0, r3 800158c: 687b ldr r3, [r7, #4] 800158e: 681b ldr r3, [r3, #0] 8001590: 430a orrs r2, r1 8001592: 62da str r2, [r3, #44] ; 0x2c } /* Channel sampling time configuration */ /* For channels 10 to 17 */ if (sConfig->Channel >= ADC_CHANNEL_10) 8001594: 683b ldr r3, [r7, #0] 8001596: 681b ldr r3, [r3, #0] 8001598: 2b09 cmp r3, #9 800159a: d91c bls.n 80015d6 { MODIFY_REG(hadc->Instance->SMPR1 , 800159c: 687b ldr r3, [r7, #4] 800159e: 681b ldr r3, [r3, #0] 80015a0: 68d9 ldr r1, [r3, #12] 80015a2: 683b ldr r3, [r7, #0] 80015a4: 681a ldr r2, [r3, #0] 80015a6: 4613 mov r3, r2 80015a8: 005b lsls r3, r3, #1 80015aa: 4413 add r3, r2 80015ac: 3b1e subs r3, #30 80015ae: 2207 movs r2, #7 80015b0: fa02 f303 lsl.w r3, r2, r3 80015b4: 43db mvns r3, r3 80015b6: 4019 ands r1, r3 80015b8: 683b ldr r3, [r7, #0] 80015ba: 6898 ldr r0, [r3, #8] 80015bc: 683b ldr r3, [r7, #0] 80015be: 681a ldr r2, [r3, #0] 80015c0: 4613 mov r3, r2 80015c2: 005b lsls r3, r3, #1 80015c4: 4413 add r3, r2 80015c6: 3b1e subs r3, #30 80015c8: fa00 f203 lsl.w r2, r0, r3 80015cc: 687b ldr r3, [r7, #4] 80015ce: 681b ldr r3, [r3, #0] 80015d0: 430a orrs r2, r1 80015d2: 60da str r2, [r3, #12] 80015d4: e019 b.n 800160a ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) , ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) ); } else /* For channels 0 to 9 */ { MODIFY_REG(hadc->Instance->SMPR2 , 80015d6: 687b ldr r3, [r7, #4] 80015d8: 681b ldr r3, [r3, #0] 80015da: 6919 ldr r1, [r3, #16] 80015dc: 683b ldr r3, [r7, #0] 80015de: 681a ldr r2, [r3, #0] 80015e0: 4613 mov r3, r2 80015e2: 005b lsls r3, r3, #1 80015e4: 4413 add r3, r2 80015e6: 2207 movs r2, #7 80015e8: fa02 f303 lsl.w r3, r2, r3 80015ec: 43db mvns r3, r3 80015ee: 4019 ands r1, r3 80015f0: 683b ldr r3, [r7, #0] 80015f2: 6898 ldr r0, [r3, #8] 80015f4: 683b ldr r3, [r7, #0] 80015f6: 681a ldr r2, [r3, #0] 80015f8: 4613 mov r3, r2 80015fa: 005b lsls r3, r3, #1 80015fc: 4413 add r3, r2 80015fe: fa00 f203 lsl.w r2, r0, r3 8001602: 687b ldr r3, [r7, #4] 8001604: 681b ldr r3, [r3, #0] 8001606: 430a orrs r2, r1 8001608: 611a str r2, [r3, #16] ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); } /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ /* and VREFINT measurement path. */ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 800160a: 683b ldr r3, [r7, #0] 800160c: 681b ldr r3, [r3, #0] 800160e: 2b10 cmp r3, #16 8001610: d003 beq.n 800161a (sConfig->Channel == ADC_CHANNEL_VREFINT) ) 8001612: 683b ldr r3, [r7, #0] 8001614: 681b ldr r3, [r3, #0] if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || 8001616: 2b11 cmp r3, #17 8001618: d132 bne.n 8001680 { /* For STM32F1 devices with several ADC: Only ADC1 can access internal */ /* measurement channels (VrefInt/TempSensor). If these channels are */ /* intended to be set on other ADC instances, an error is reported. */ if (hadc->Instance == ADC1) 800161a: 687b ldr r3, [r7, #4] 800161c: 681b ldr r3, [r3, #0] 800161e: 4a1d ldr r2, [pc, #116] ; (8001694 ) 8001620: 4293 cmp r3, r2 8001622: d125 bne.n 8001670 { if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET) 8001624: 687b ldr r3, [r7, #4] 8001626: 681b ldr r3, [r3, #0] 8001628: 689b ldr r3, [r3, #8] 800162a: f403 0300 and.w r3, r3, #8388608 ; 0x800000 800162e: 2b00 cmp r3, #0 8001630: d126 bne.n 8001680 { SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); 8001632: 687b ldr r3, [r7, #4] 8001634: 681b ldr r3, [r3, #0] 8001636: 689a ldr r2, [r3, #8] 8001638: 687b ldr r3, [r7, #4] 800163a: 681b ldr r3, [r3, #0] 800163c: f442 0200 orr.w r2, r2, #8388608 ; 0x800000 8001640: 609a str r2, [r3, #8] if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)) 8001642: 683b ldr r3, [r7, #0] 8001644: 681b ldr r3, [r3, #0] 8001646: 2b10 cmp r3, #16 8001648: d11a bne.n 8001680 { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); 800164a: 4b13 ldr r3, [pc, #76] ; (8001698 ) 800164c: 681b ldr r3, [r3, #0] 800164e: 4a13 ldr r2, [pc, #76] ; (800169c ) 8001650: fba2 2303 umull r2, r3, r2, r3 8001654: 0c9a lsrs r2, r3, #18 8001656: 4613 mov r3, r2 8001658: 009b lsls r3, r3, #2 800165a: 4413 add r3, r2 800165c: 005b lsls r3, r3, #1 800165e: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 8001660: e002 b.n 8001668 { wait_loop_index--; 8001662: 68bb ldr r3, [r7, #8] 8001664: 3b01 subs r3, #1 8001666: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 8001668: 68bb ldr r3, [r7, #8] 800166a: 2b00 cmp r3, #0 800166c: d1f9 bne.n 8001662 800166e: e007 b.n 8001680 } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8001670: 687b ldr r3, [r7, #4] 8001672: 6a9b ldr r3, [r3, #40] ; 0x28 8001674: f043 0220 orr.w r2, r3, #32 8001678: 687b ldr r3, [r7, #4] 800167a: 629a str r2, [r3, #40] ; 0x28 tmp_hal_status = HAL_ERROR; 800167c: 2301 movs r3, #1 800167e: 73fb strb r3, [r7, #15] } } /* Process unlocked */ __HAL_UNLOCK(hadc); 8001680: 687b ldr r3, [r7, #4] 8001682: 2200 movs r2, #0 8001684: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Return function status */ return tmp_hal_status; 8001688: 7bfb ldrb r3, [r7, #15] } 800168a: 4618 mov r0, r3 800168c: 3714 adds r7, #20 800168e: 46bd mov sp, r7 8001690: bc80 pop {r7} 8001692: 4770 bx lr 8001694: 40012400 .word 0x40012400 8001698: 20000008 .word 0x20000008 800169c: 431bde83 .word 0x431bde83 080016a0 : * and voltage regulator must be enabled (done into HAL_ADC_Init()). * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) { 80016a0: b580 push {r7, lr} 80016a2: b084 sub sp, #16 80016a4: af00 add r7, sp, #0 80016a6: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 80016a8: 2300 movs r3, #0 80016aa: 60fb str r3, [r7, #12] __IO uint32_t wait_loop_index = 0U; 80016ac: 2300 movs r3, #0 80016ae: 60bb str r3, [r7, #8] /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ if (ADC_IS_ENABLE(hadc) == RESET) 80016b0: 687b ldr r3, [r7, #4] 80016b2: 681b ldr r3, [r3, #0] 80016b4: 689b ldr r3, [r3, #8] 80016b6: f003 0301 and.w r3, r3, #1 80016ba: 2b01 cmp r3, #1 80016bc: d039 beq.n 8001732 { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); 80016be: 687b ldr r3, [r7, #4] 80016c0: 681b ldr r3, [r3, #0] 80016c2: 689a ldr r2, [r3, #8] 80016c4: 687b ldr r3, [r7, #4] 80016c6: 681b ldr r3, [r3, #0] 80016c8: f042 0201 orr.w r2, r2, #1 80016cc: 609a str r2, [r3, #8] /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); 80016ce: 4b1b ldr r3, [pc, #108] ; (800173c ) 80016d0: 681b ldr r3, [r3, #0] 80016d2: 4a1b ldr r2, [pc, #108] ; (8001740 ) 80016d4: fba2 2303 umull r2, r3, r2, r3 80016d8: 0c9b lsrs r3, r3, #18 80016da: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 80016dc: e002 b.n 80016e4 { wait_loop_index--; 80016de: 68bb ldr r3, [r7, #8] 80016e0: 3b01 subs r3, #1 80016e2: 60bb str r3, [r7, #8] while(wait_loop_index != 0U) 80016e4: 68bb ldr r3, [r7, #8] 80016e6: 2b00 cmp r3, #0 80016e8: d1f9 bne.n 80016de } /* Get tick count */ tickstart = HAL_GetTick(); 80016ea: f7ff fc87 bl 8000ffc 80016ee: 60f8 str r0, [r7, #12] /* Wait for ADC effectively enabled */ while(ADC_IS_ENABLE(hadc) == RESET) 80016f0: e018 b.n 8001724 { if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) 80016f2: f7ff fc83 bl 8000ffc 80016f6: 4602 mov r2, r0 80016f8: 68fb ldr r3, [r7, #12] 80016fa: 1ad3 subs r3, r2, r3 80016fc: 2b02 cmp r3, #2 80016fe: d911 bls.n 8001724 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8001700: 687b ldr r3, [r7, #4] 8001702: 6a9b ldr r3, [r3, #40] ; 0x28 8001704: f043 0210 orr.w r2, r3, #16 8001708: 687b ldr r3, [r7, #4] 800170a: 629a str r2, [r3, #40] ; 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800170c: 687b ldr r3, [r7, #4] 800170e: 6adb ldr r3, [r3, #44] ; 0x2c 8001710: f043 0201 orr.w r2, r3, #1 8001714: 687b ldr r3, [r7, #4] 8001716: 62da str r2, [r3, #44] ; 0x2c /* Process unlocked */ __HAL_UNLOCK(hadc); 8001718: 687b ldr r3, [r7, #4] 800171a: 2200 movs r2, #0 800171c: f883 2024 strb.w r2, [r3, #36] ; 0x24 return HAL_ERROR; 8001720: 2301 movs r3, #1 8001722: e007 b.n 8001734 while(ADC_IS_ENABLE(hadc) == RESET) 8001724: 687b ldr r3, [r7, #4] 8001726: 681b ldr r3, [r3, #0] 8001728: 689b ldr r3, [r3, #8] 800172a: f003 0301 and.w r3, r3, #1 800172e: 2b01 cmp r3, #1 8001730: d1df bne.n 80016f2 } } } /* Return HAL status */ return HAL_OK; 8001732: 2300 movs r3, #0 } 8001734: 4618 mov r0, r3 8001736: 3710 adds r7, #16 8001738: 46bd mov sp, r7 800173a: bd80 pop {r7, pc} 800173c: 20000008 .word 0x20000008 8001740: 431bde83 .word 0x431bde83 08001744 : * stopped to disable the ADC. * @param hadc: ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc) { 8001744: b580 push {r7, lr} 8001746: b084 sub sp, #16 8001748: af00 add r7, sp, #0 800174a: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 800174c: 2300 movs r3, #0 800174e: 60fb str r3, [r7, #12] /* Verification if ADC is not already disabled */ if (ADC_IS_ENABLE(hadc) != RESET) 8001750: 687b ldr r3, [r7, #4] 8001752: 681b ldr r3, [r3, #0] 8001754: 689b ldr r3, [r3, #8] 8001756: f003 0301 and.w r3, r3, #1 800175a: 2b01 cmp r3, #1 800175c: d127 bne.n 80017ae { /* Disable the ADC peripheral */ __HAL_ADC_DISABLE(hadc); 800175e: 687b ldr r3, [r7, #4] 8001760: 681b ldr r3, [r3, #0] 8001762: 689a ldr r2, [r3, #8] 8001764: 687b ldr r3, [r7, #4] 8001766: 681b ldr r3, [r3, #0] 8001768: f022 0201 bic.w r2, r2, #1 800176c: 609a str r2, [r3, #8] /* Get tick count */ tickstart = HAL_GetTick(); 800176e: f7ff fc45 bl 8000ffc 8001772: 60f8 str r0, [r7, #12] /* Wait for ADC effectively disabled */ while(ADC_IS_ENABLE(hadc) != RESET) 8001774: e014 b.n 80017a0 { if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 8001776: f7ff fc41 bl 8000ffc 800177a: 4602 mov r2, r0 800177c: 68fb ldr r3, [r7, #12] 800177e: 1ad3 subs r3, r2, r3 8001780: 2b02 cmp r3, #2 8001782: d90d bls.n 80017a0 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8001784: 687b ldr r3, [r7, #4] 8001786: 6a9b ldr r3, [r3, #40] ; 0x28 8001788: f043 0210 orr.w r2, r3, #16 800178c: 687b ldr r3, [r7, #4] 800178e: 629a str r2, [r3, #40] ; 0x28 /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8001790: 687b ldr r3, [r7, #4] 8001792: 6adb ldr r3, [r3, #44] ; 0x2c 8001794: f043 0201 orr.w r2, r3, #1 8001798: 687b ldr r3, [r7, #4] 800179a: 62da str r2, [r3, #44] ; 0x2c return HAL_ERROR; 800179c: 2301 movs r3, #1 800179e: e007 b.n 80017b0 while(ADC_IS_ENABLE(hadc) != RESET) 80017a0: 687b ldr r3, [r7, #4] 80017a2: 681b ldr r3, [r3, #0] 80017a4: 689b ldr r3, [r3, #8] 80017a6: f003 0301 and.w r3, r3, #1 80017aa: 2b01 cmp r3, #1 80017ac: d0e3 beq.n 8001776 } } } /* Return HAL status */ return HAL_OK; 80017ae: 2300 movs r3, #0 } 80017b0: 4618 mov r0, r3 80017b2: 3710 adds r7, #16 80017b4: 46bd mov sp, r7 80017b6: bd80 pop {r7, pc} 080017b8 : * @brief DMA transfer complete callback. * @param hdma: pointer to DMA handle. * @retval None */ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) { 80017b8: b580 push {r7, lr} 80017ba: b084 sub sp, #16 80017bc: af00 add r7, sp, #0 80017be: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 80017c0: 687b ldr r3, [r7, #4] 80017c2: 6a5b ldr r3, [r3, #36] ; 0x24 80017c4: 60fb str r3, [r7, #12] /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) 80017c6: 68fb ldr r3, [r7, #12] 80017c8: 6a9b ldr r3, [r3, #40] ; 0x28 80017ca: f003 0350 and.w r3, r3, #80 ; 0x50 80017ce: 2b00 cmp r3, #0 80017d0: d127 bne.n 8001822 { /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 80017d2: 68fb ldr r3, [r7, #12] 80017d4: 6a9b ldr r3, [r3, #40] ; 0x28 80017d6: f443 7200 orr.w r2, r3, #512 ; 0x200 80017da: 68fb ldr r3, [r7, #12] 80017dc: 629a str r2, [r3, #40] ; 0x28 /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F1 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 80017de: 68fb ldr r3, [r7, #12] 80017e0: 681b ldr r3, [r3, #0] 80017e2: 689b ldr r3, [r3, #8] 80017e4: f403 2360 and.w r3, r3, #917504 ; 0xe0000 80017e8: f5b3 2f60 cmp.w r3, #917504 ; 0xe0000 80017ec: d115 bne.n 800181a (hadc->Init.ContinuousConvMode == DISABLE) ) 80017ee: 68fb ldr r3, [r7, #12] 80017f0: 7b1b ldrb r3, [r3, #12] if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 80017f2: 2b00 cmp r3, #0 80017f4: d111 bne.n 800181a { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 80017f6: 68fb ldr r3, [r7, #12] 80017f8: 6a9b ldr r3, [r3, #40] ; 0x28 80017fa: f423 7280 bic.w r2, r3, #256 ; 0x100 80017fe: 68fb ldr r3, [r7, #12] 8001800: 629a str r2, [r3, #40] ; 0x28 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 8001802: 68fb ldr r3, [r7, #12] 8001804: 6a9b ldr r3, [r3, #40] ; 0x28 8001806: f403 5380 and.w r3, r3, #4096 ; 0x1000 800180a: 2b00 cmp r3, #0 800180c: d105 bne.n 800181a { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 800180e: 68fb ldr r3, [r7, #12] 8001810: 6a9b ldr r3, [r3, #40] ; 0x28 8001812: f043 0201 orr.w r2, r3, #1 8001816: 68fb ldr r3, [r7, #12] 8001818: 629a str r2, [r3, #40] ; 0x28 /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); 800181a: 68f8 ldr r0, [r7, #12] 800181c: f7ff fa74 bl 8000d08 else { /* Call DMA error callback */ hadc->DMA_Handle->XferErrorCallback(hdma); } } 8001820: e004 b.n 800182c hadc->DMA_Handle->XferErrorCallback(hdma); 8001822: 68fb ldr r3, [r7, #12] 8001824: 6a1b ldr r3, [r3, #32] 8001826: 6b1b ldr r3, [r3, #48] ; 0x30 8001828: 6878 ldr r0, [r7, #4] 800182a: 4798 blx r3 } 800182c: bf00 nop 800182e: 3710 adds r7, #16 8001830: 46bd mov sp, r7 8001832: bd80 pop {r7, pc} 08001834 : * @brief DMA half transfer complete callback. * @param hdma: pointer to DMA handle. * @retval None */ void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) { 8001834: b580 push {r7, lr} 8001836: b084 sub sp, #16 8001838: af00 add r7, sp, #0 800183a: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 800183c: 687b ldr r3, [r7, #4] 800183e: 6a5b ldr r3, [r3, #36] ; 0x24 8001840: 60fb str r3, [r7, #12] /* Half conversion callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvHalfCpltCallback(hadc); #else HAL_ADC_ConvHalfCpltCallback(hadc); 8001842: 68f8 ldr r0, [r7, #12] 8001844: f7ff fe19 bl 800147a #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } 8001848: bf00 nop 800184a: 3710 adds r7, #16 800184c: 46bd mov sp, r7 800184e: bd80 pop {r7, pc} 08001850 : * @brief DMA error callback * @param hdma: pointer to DMA handle. * @retval None */ void ADC_DMAError(DMA_HandleTypeDef *hdma) { 8001850: b580 push {r7, lr} 8001852: b084 sub sp, #16 8001854: af00 add r7, sp, #0 8001856: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 8001858: 687b ldr r3, [r7, #4] 800185a: 6a5b ldr r3, [r3, #36] ; 0x24 800185c: 60fb str r3, [r7, #12] /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); 800185e: 68fb ldr r3, [r7, #12] 8001860: 6a9b ldr r3, [r3, #40] ; 0x28 8001862: f043 0240 orr.w r2, r3, #64 ; 0x40 8001866: 68fb ldr r3, [r7, #12] 8001868: 629a str r2, [r3, #40] ; 0x28 /* Set ADC error code to DMA error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); 800186a: 68fb ldr r3, [r7, #12] 800186c: 6adb ldr r3, [r3, #44] ; 0x2c 800186e: f043 0204 orr.w r2, r3, #4 8001872: 68fb ldr r3, [r7, #12] 8001874: 62da str r2, [r3, #44] ; 0x2c /* Error callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ErrorCallback(hadc); #else HAL_ADC_ErrorCallback(hadc); 8001876: 68f8 ldr r0, [r7, #12] 8001878: f7ff fe11 bl 800149e #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } 800187c: bf00 nop 800187e: 3710 adds r7, #16 8001880: 46bd mov sp, r7 8001882: bd80 pop {r7, pc} 08001884 : * the completion of this function. * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc) { 8001884: b590 push {r4, r7, lr} 8001886: b087 sub sp, #28 8001888: af00 add r7, sp, #0 800188a: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800188c: 2300 movs r3, #0 800188e: 75fb strb r3, [r7, #23] uint32_t tickstart; __IO uint32_t wait_loop_index = 0U; 8001890: 2300 movs r3, #0 8001892: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); 8001894: 687b ldr r3, [r7, #4] 8001896: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 800189a: 2b01 cmp r3, #1 800189c: d101 bne.n 80018a2 800189e: 2302 movs r3, #2 80018a0: e086 b.n 80019b0 80018a2: 687b ldr r3, [r7, #4] 80018a4: 2201 movs r2, #1 80018a6: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* 1. Calibration prerequisite: */ /* - ADC must be disabled for at least two ADC clock cycles in disable */ /* mode before ADC enable */ /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); 80018aa: 6878 ldr r0, [r7, #4] 80018ac: f7ff ff4a bl 8001744 80018b0: 4603 mov r3, r0 80018b2: 75fb strb r3, [r7, #23] /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) 80018b4: 7dfb ldrb r3, [r7, #23] 80018b6: 2b00 cmp r3, #0 80018b8: d175 bne.n 80019a6 { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 80018ba: 687b ldr r3, [r7, #4] 80018bc: 6a9b ldr r3, [r3, #40] ; 0x28 80018be: f423 5388 bic.w r3, r3, #4352 ; 0x1100 80018c2: f023 0302 bic.w r3, r3, #2 80018c6: f043 0202 orr.w r2, r3, #2 80018ca: 687b ldr r3, [r7, #4] 80018cc: 629a str r2, [r3, #40] ; 0x28 /* Hardware prerequisite: delay before starting the calibration. */ /* - Computation of CPU clock cycles corresponding to ADC clock cycles. */ /* - Wait for the expected ADC clock cycles delay */ wait_loop_index = ((SystemCoreClock / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) 80018ce: 4b3a ldr r3, [pc, #232] ; (80019b8 ) 80018d0: 681c ldr r4, [r3, #0] 80018d2: 2002 movs r0, #2 80018d4: f001 fa08 bl 8002ce8 80018d8: 4603 mov r3, r0 80018da: fbb4 f3f3 udiv r3, r4, r3 * ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES ); 80018de: 005b lsls r3, r3, #1 wait_loop_index = ((SystemCoreClock 80018e0: 60fb str r3, [r7, #12] while(wait_loop_index != 0U) 80018e2: e002 b.n 80018ea { wait_loop_index--; 80018e4: 68fb ldr r3, [r7, #12] 80018e6: 3b01 subs r3, #1 80018e8: 60fb str r3, [r7, #12] while(wait_loop_index != 0U) 80018ea: 68fb ldr r3, [r7, #12] 80018ec: 2b00 cmp r3, #0 80018ee: d1f9 bne.n 80018e4 } /* 2. Enable the ADC peripheral */ ADC_Enable(hadc); 80018f0: 6878 ldr r0, [r7, #4] 80018f2: f7ff fed5 bl 80016a0 /* 3. Resets ADC calibration registers */ SET_BIT(hadc->Instance->CR2, ADC_CR2_RSTCAL); 80018f6: 687b ldr r3, [r7, #4] 80018f8: 681b ldr r3, [r3, #0] 80018fa: 689a ldr r2, [r3, #8] 80018fc: 687b ldr r3, [r7, #4] 80018fe: 681b ldr r3, [r3, #0] 8001900: f042 0208 orr.w r2, r2, #8 8001904: 609a str r2, [r3, #8] tickstart = HAL_GetTick(); 8001906: f7ff fb79 bl 8000ffc 800190a: 6138 str r0, [r7, #16] /* Wait for calibration reset completion */ while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 800190c: e014 b.n 8001938 { if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) 800190e: f7ff fb75 bl 8000ffc 8001912: 4602 mov r2, r0 8001914: 693b ldr r3, [r7, #16] 8001916: 1ad3 subs r3, r2, r3 8001918: 2b0a cmp r3, #10 800191a: d90d bls.n 8001938 { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 800191c: 687b ldr r3, [r7, #4] 800191e: 6a9b ldr r3, [r3, #40] ; 0x28 8001920: f023 0312 bic.w r3, r3, #18 8001924: f043 0210 orr.w r2, r3, #16 8001928: 687b ldr r3, [r7, #4] 800192a: 629a str r2, [r3, #40] ; 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); 800192c: 687b ldr r3, [r7, #4] 800192e: 2200 movs r2, #0 8001930: f883 2024 strb.w r2, [r3, #36] ; 0x24 return HAL_ERROR; 8001934: 2301 movs r3, #1 8001936: e03b b.n 80019b0 while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 8001938: 687b ldr r3, [r7, #4] 800193a: 681b ldr r3, [r3, #0] 800193c: 689b ldr r3, [r3, #8] 800193e: f003 0308 and.w r3, r3, #8 8001942: 2b00 cmp r3, #0 8001944: d1e3 bne.n 800190e } } /* 4. Start ADC calibration */ SET_BIT(hadc->Instance->CR2, ADC_CR2_CAL); 8001946: 687b ldr r3, [r7, #4] 8001948: 681b ldr r3, [r3, #0] 800194a: 689a ldr r2, [r3, #8] 800194c: 687b ldr r3, [r7, #4] 800194e: 681b ldr r3, [r3, #0] 8001950: f042 0204 orr.w r2, r2, #4 8001954: 609a str r2, [r3, #8] tickstart = HAL_GetTick(); 8001956: f7ff fb51 bl 8000ffc 800195a: 6138 str r0, [r7, #16] /* Wait for calibration completion */ while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 800195c: e014 b.n 8001988 { if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) 800195e: f7ff fb4d bl 8000ffc 8001962: 4602 mov r2, r0 8001964: 693b ldr r3, [r7, #16] 8001966: 1ad3 subs r3, r2, r3 8001968: 2b0a cmp r3, #10 800196a: d90d bls.n 8001988 { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 800196c: 687b ldr r3, [r7, #4] 800196e: 6a9b ldr r3, [r3, #40] ; 0x28 8001970: f023 0312 bic.w r3, r3, #18 8001974: f043 0210 orr.w r2, r3, #16 8001978: 687b ldr r3, [r7, #4] 800197a: 629a str r2, [r3, #40] ; 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); 800197c: 687b ldr r3, [r7, #4] 800197e: 2200 movs r2, #0 8001980: f883 2024 strb.w r2, [r3, #36] ; 0x24 return HAL_ERROR; 8001984: 2301 movs r3, #1 8001986: e013 b.n 80019b0 while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 8001988: 687b ldr r3, [r7, #4] 800198a: 681b ldr r3, [r3, #0] 800198c: 689b ldr r3, [r3, #8] 800198e: f003 0304 and.w r3, r3, #4 8001992: 2b00 cmp r3, #0 8001994: d1e3 bne.n 800195e } } /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8001996: 687b ldr r3, [r7, #4] 8001998: 6a9b ldr r3, [r3, #40] ; 0x28 800199a: f023 0303 bic.w r3, r3, #3 800199e: f043 0201 orr.w r2, r3, #1 80019a2: 687b ldr r3, [r7, #4] 80019a4: 629a str r2, [r3, #40] ; 0x28 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); } /* Process unlocked */ __HAL_UNLOCK(hadc); 80019a6: 687b ldr r3, [r7, #4] 80019a8: 2200 movs r2, #0 80019aa: f883 2024 strb.w r2, [r3, #36] ; 0x24 /* Return function status */ return tmp_hal_status; 80019ae: 7dfb ldrb r3, [r7, #23] } 80019b0: 4618 mov r0, r3 80019b2: 371c adds r7, #28 80019b4: 46bd mov sp, r7 80019b6: bd90 pop {r4, r7, pc} 80019b8: 20000008 .word 0x20000008 080019bc : * @brief Injected conversion complete callback in non blocking mode * @param hadc: ADC handle * @retval None */ __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) { 80019bc: b480 push {r7} 80019be: b083 sub sp, #12 80019c0: af00 add r7, sp, #0 80019c2: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file */ } 80019c4: bf00 nop 80019c6: 370c adds r7, #12 80019c8: 46bd mov sp, r7 80019ca: bc80 pop {r7} 80019cc: 4770 bx lr ... 080019d0 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 80019d0: b480 push {r7} 80019d2: b085 sub sp, #20 80019d4: af00 add r7, sp, #0 80019d6: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 80019d8: 687b ldr r3, [r7, #4] 80019da: f003 0307 and.w r3, r3, #7 80019de: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 80019e0: 4b0c ldr r3, [pc, #48] ; (8001a14 <__NVIC_SetPriorityGrouping+0x44>) 80019e2: 68db ldr r3, [r3, #12] 80019e4: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 80019e6: 68ba ldr r2, [r7, #8] 80019e8: f64f 03ff movw r3, #63743 ; 0xf8ff 80019ec: 4013 ands r3, r2 80019ee: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 80019f0: 68fb ldr r3, [r7, #12] 80019f2: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 80019f4: 68bb ldr r3, [r7, #8] 80019f6: 4313 orrs r3, r2 reg_value = (reg_value | 80019f8: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 80019fc: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8001a00: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 8001a02: 4a04 ldr r2, [pc, #16] ; (8001a14 <__NVIC_SetPriorityGrouping+0x44>) 8001a04: 68bb ldr r3, [r7, #8] 8001a06: 60d3 str r3, [r2, #12] } 8001a08: bf00 nop 8001a0a: 3714 adds r7, #20 8001a0c: 46bd mov sp, r7 8001a0e: bc80 pop {r7} 8001a10: 4770 bx lr 8001a12: bf00 nop 8001a14: e000ed00 .word 0xe000ed00 08001a18 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 8001a18: b480 push {r7} 8001a1a: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8001a1c: 4b04 ldr r3, [pc, #16] ; (8001a30 <__NVIC_GetPriorityGrouping+0x18>) 8001a1e: 68db ldr r3, [r3, #12] 8001a20: 0a1b lsrs r3, r3, #8 8001a22: f003 0307 and.w r3, r3, #7 } 8001a26: 4618 mov r0, r3 8001a28: 46bd mov sp, r7 8001a2a: bc80 pop {r7} 8001a2c: 4770 bx lr 8001a2e: bf00 nop 8001a30: e000ed00 .word 0xe000ed00 08001a34 <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 8001a34: b480 push {r7} 8001a36: b083 sub sp, #12 8001a38: af00 add r7, sp, #0 8001a3a: 4603 mov r3, r0 8001a3c: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8001a3e: f997 3007 ldrsb.w r3, [r7, #7] 8001a42: 2b00 cmp r3, #0 8001a44: db0b blt.n 8001a5e <__NVIC_EnableIRQ+0x2a> { NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8001a46: 79fb ldrb r3, [r7, #7] 8001a48: f003 021f and.w r2, r3, #31 8001a4c: 4906 ldr r1, [pc, #24] ; (8001a68 <__NVIC_EnableIRQ+0x34>) 8001a4e: f997 3007 ldrsb.w r3, [r7, #7] 8001a52: 095b lsrs r3, r3, #5 8001a54: 2001 movs r0, #1 8001a56: fa00 f202 lsl.w r2, r0, r2 8001a5a: f841 2023 str.w r2, [r1, r3, lsl #2] } } 8001a5e: bf00 nop 8001a60: 370c adds r7, #12 8001a62: 46bd mov sp, r7 8001a64: bc80 pop {r7} 8001a66: 4770 bx lr 8001a68: e000e100 .word 0xe000e100 08001a6c <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8001a6c: b480 push {r7} 8001a6e: b083 sub sp, #12 8001a70: af00 add r7, sp, #0 8001a72: 4603 mov r3, r0 8001a74: 6039 str r1, [r7, #0] 8001a76: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8001a78: f997 3007 ldrsb.w r3, [r7, #7] 8001a7c: 2b00 cmp r3, #0 8001a7e: db0a blt.n 8001a96 <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8001a80: 683b ldr r3, [r7, #0] 8001a82: b2da uxtb r2, r3 8001a84: 490c ldr r1, [pc, #48] ; (8001ab8 <__NVIC_SetPriority+0x4c>) 8001a86: f997 3007 ldrsb.w r3, [r7, #7] 8001a8a: 0112 lsls r2, r2, #4 8001a8c: b2d2 uxtb r2, r2 8001a8e: 440b add r3, r1 8001a90: f883 2300 strb.w r2, [r3, #768] ; 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 8001a94: e00a b.n 8001aac <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8001a96: 683b ldr r3, [r7, #0] 8001a98: b2da uxtb r2, r3 8001a9a: 4908 ldr r1, [pc, #32] ; (8001abc <__NVIC_SetPriority+0x50>) 8001a9c: 79fb ldrb r3, [r7, #7] 8001a9e: f003 030f and.w r3, r3, #15 8001aa2: 3b04 subs r3, #4 8001aa4: 0112 lsls r2, r2, #4 8001aa6: b2d2 uxtb r2, r2 8001aa8: 440b add r3, r1 8001aaa: 761a strb r2, [r3, #24] } 8001aac: bf00 nop 8001aae: 370c adds r7, #12 8001ab0: 46bd mov sp, r7 8001ab2: bc80 pop {r7} 8001ab4: 4770 bx lr 8001ab6: bf00 nop 8001ab8: e000e100 .word 0xe000e100 8001abc: e000ed00 .word 0xe000ed00 08001ac0 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 8001ac0: b480 push {r7} 8001ac2: b089 sub sp, #36 ; 0x24 8001ac4: af00 add r7, sp, #0 8001ac6: 60f8 str r0, [r7, #12] 8001ac8: 60b9 str r1, [r7, #8] 8001aca: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8001acc: 68fb ldr r3, [r7, #12] 8001ace: f003 0307 and.w r3, r3, #7 8001ad2: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8001ad4: 69fb ldr r3, [r7, #28] 8001ad6: f1c3 0307 rsb r3, r3, #7 8001ada: 2b04 cmp r3, #4 8001adc: bf28 it cs 8001ade: 2304 movcs r3, #4 8001ae0: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8001ae2: 69fb ldr r3, [r7, #28] 8001ae4: 3304 adds r3, #4 8001ae6: 2b06 cmp r3, #6 8001ae8: d902 bls.n 8001af0 8001aea: 69fb ldr r3, [r7, #28] 8001aec: 3b03 subs r3, #3 8001aee: e000 b.n 8001af2 8001af0: 2300 movs r3, #0 8001af2: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8001af4: f04f 32ff mov.w r2, #4294967295 8001af8: 69bb ldr r3, [r7, #24] 8001afa: fa02 f303 lsl.w r3, r2, r3 8001afe: 43da mvns r2, r3 8001b00: 68bb ldr r3, [r7, #8] 8001b02: 401a ands r2, r3 8001b04: 697b ldr r3, [r7, #20] 8001b06: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8001b08: f04f 31ff mov.w r1, #4294967295 8001b0c: 697b ldr r3, [r7, #20] 8001b0e: fa01 f303 lsl.w r3, r1, r3 8001b12: 43d9 mvns r1, r3 8001b14: 687b ldr r3, [r7, #4] 8001b16: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8001b18: 4313 orrs r3, r2 ); } 8001b1a: 4618 mov r0, r3 8001b1c: 3724 adds r7, #36 ; 0x24 8001b1e: 46bd mov sp, r7 8001b20: bc80 pop {r7} 8001b22: 4770 bx lr 08001b24 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8001b24: b580 push {r7, lr} 8001b26: b082 sub sp, #8 8001b28: af00 add r7, sp, #0 8001b2a: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8001b2c: 6878 ldr r0, [r7, #4] 8001b2e: f7ff ff4f bl 80019d0 <__NVIC_SetPriorityGrouping> } 8001b32: bf00 nop 8001b34: 3708 adds r7, #8 8001b36: 46bd mov sp, r7 8001b38: bd80 pop {r7, pc} 08001b3a : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8001b3a: b580 push {r7, lr} 8001b3c: b086 sub sp, #24 8001b3e: af00 add r7, sp, #0 8001b40: 4603 mov r3, r0 8001b42: 60b9 str r1, [r7, #8] 8001b44: 607a str r2, [r7, #4] 8001b46: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 8001b48: 2300 movs r3, #0 8001b4a: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8001b4c: f7ff ff64 bl 8001a18 <__NVIC_GetPriorityGrouping> 8001b50: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8001b52: 687a ldr r2, [r7, #4] 8001b54: 68b9 ldr r1, [r7, #8] 8001b56: 6978 ldr r0, [r7, #20] 8001b58: f7ff ffb2 bl 8001ac0 8001b5c: 4602 mov r2, r0 8001b5e: f997 300f ldrsb.w r3, [r7, #15] 8001b62: 4611 mov r1, r2 8001b64: 4618 mov r0, r3 8001b66: f7ff ff81 bl 8001a6c <__NVIC_SetPriority> } 8001b6a: bf00 nop 8001b6c: 3718 adds r7, #24 8001b6e: 46bd mov sp, r7 8001b70: bd80 pop {r7, pc} 08001b72 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 8001b72: b580 push {r7, lr} 8001b74: b082 sub sp, #8 8001b76: af00 add r7, sp, #0 8001b78: 4603 mov r3, r0 8001b7a: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 8001b7c: f997 3007 ldrsb.w r3, [r7, #7] 8001b80: 4618 mov r0, r3 8001b82: f7ff ff57 bl 8001a34 <__NVIC_EnableIRQ> } 8001b86: bf00 nop 8001b88: 3708 adds r7, #8 8001b8a: 46bd mov sp, r7 8001b8c: bd80 pop {r7, pc} ... 08001b90 : * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { 8001b90: b480 push {r7} 8001b92: b085 sub sp, #20 8001b94: af00 add r7, sp, #0 8001b96: 6078 str r0, [r7, #4] uint32_t tmp = 0U; 8001b98: 2300 movs r3, #0 8001b9a: 60fb str r3, [r7, #12] /* Check the DMA handle allocation */ if(hdma == NULL) 8001b9c: 687b ldr r3, [r7, #4] 8001b9e: 2b00 cmp r3, #0 8001ba0: d101 bne.n 8001ba6 { return HAL_ERROR; 8001ba2: 2301 movs r3, #1 8001ba4: e043 b.n 8001c2e hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; hdma->DmaBaseAddress = DMA2; } #else /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; 8001ba6: 687b ldr r3, [r7, #4] 8001ba8: 681b ldr r3, [r3, #0] 8001baa: 461a mov r2, r3 8001bac: 4b22 ldr r3, [pc, #136] ; (8001c38 ) 8001bae: 4413 add r3, r2 8001bb0: 4a22 ldr r2, [pc, #136] ; (8001c3c ) 8001bb2: fba2 2303 umull r2, r3, r2, r3 8001bb6: 091b lsrs r3, r3, #4 8001bb8: 009a lsls r2, r3, #2 8001bba: 687b ldr r3, [r7, #4] 8001bbc: 641a str r2, [r3, #64] ; 0x40 hdma->DmaBaseAddress = DMA1; 8001bbe: 687b ldr r3, [r7, #4] 8001bc0: 4a1f ldr r2, [pc, #124] ; (8001c40 ) 8001bc2: 63da str r2, [r3, #60] ; 0x3c #endif /* DMA2 */ /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8001bc4: 687b ldr r3, [r7, #4] 8001bc6: 2202 movs r2, #2 8001bc8: f883 2021 strb.w r2, [r3, #33] ; 0x21 /* Get the CR register value */ tmp = hdma->Instance->CCR; 8001bcc: 687b ldr r3, [r7, #4] 8001bce: 681b ldr r3, [r3, #0] 8001bd0: 681b ldr r3, [r3, #0] 8001bd2: 60fb str r3, [r7, #12] /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ 8001bd4: 68fb ldr r3, [r7, #12] 8001bd6: f423 537f bic.w r3, r3, #16320 ; 0x3fc0 8001bda: f023 0330 bic.w r3, r3, #48 ; 0x30 8001bde: 60fb str r3, [r7, #12] DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ DMA_CCR_DIR)); /* Prepare the DMA Channel configuration */ tmp |= hdma->Init.Direction | 8001be0: 687b ldr r3, [r7, #4] 8001be2: 685a ldr r2, [r3, #4] hdma->Init.PeriphInc | hdma->Init.MemInc | 8001be4: 687b ldr r3, [r7, #4] 8001be6: 689b ldr r3, [r3, #8] tmp |= hdma->Init.Direction | 8001be8: 431a orrs r2, r3 hdma->Init.PeriphInc | hdma->Init.MemInc | 8001bea: 687b ldr r3, [r7, #4] 8001bec: 68db ldr r3, [r3, #12] 8001bee: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8001bf0: 687b ldr r3, [r7, #4] 8001bf2: 691b ldr r3, [r3, #16] hdma->Init.PeriphInc | hdma->Init.MemInc | 8001bf4: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8001bf6: 687b ldr r3, [r7, #4] 8001bf8: 695b ldr r3, [r3, #20] 8001bfa: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 8001bfc: 687b ldr r3, [r7, #4] 8001bfe: 699b ldr r3, [r3, #24] hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8001c00: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 8001c02: 687b ldr r3, [r7, #4] 8001c04: 69db ldr r3, [r3, #28] 8001c06: 4313 orrs r3, r2 tmp |= hdma->Init.Direction | 8001c08: 68fa ldr r2, [r7, #12] 8001c0a: 4313 orrs r3, r2 8001c0c: 60fb str r3, [r7, #12] /* Write to DMA Channel CR register */ hdma->Instance->CCR = tmp; 8001c0e: 687b ldr r3, [r7, #4] 8001c10: 681b ldr r3, [r3, #0] 8001c12: 68fa ldr r2, [r7, #12] 8001c14: 601a str r2, [r3, #0] /* Initialise the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8001c16: 687b ldr r3, [r7, #4] 8001c18: 2200 movs r2, #0 8001c1a: 639a str r2, [r3, #56] ; 0x38 /* Initialize the DMA state*/ hdma->State = HAL_DMA_STATE_READY; 8001c1c: 687b ldr r3, [r7, #4] 8001c1e: 2201 movs r2, #1 8001c20: f883 2021 strb.w r2, [r3, #33] ; 0x21 /* Allocate lock resource and initialize it */ hdma->Lock = HAL_UNLOCKED; 8001c24: 687b ldr r3, [r7, #4] 8001c26: 2200 movs r2, #0 8001c28: f883 2020 strb.w r2, [r3, #32] return HAL_OK; 8001c2c: 2300 movs r3, #0 } 8001c2e: 4618 mov r0, r3 8001c30: 3714 adds r7, #20 8001c32: 46bd mov sp, r7 8001c34: bc80 pop {r7} 8001c36: 4770 bx lr 8001c38: bffdfff8 .word 0xbffdfff8 8001c3c: cccccccd .word 0xcccccccd 8001c40: 40020000 .word 0x40020000 08001c44 : * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 8001c44: b580 push {r7, lr} 8001c46: b086 sub sp, #24 8001c48: af00 add r7, sp, #0 8001c4a: 60f8 str r0, [r7, #12] 8001c4c: 60b9 str r1, [r7, #8] 8001c4e: 607a str r2, [r7, #4] 8001c50: 603b str r3, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 8001c52: 2300 movs r3, #0 8001c54: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Process locked */ __HAL_LOCK(hdma); 8001c56: 68fb ldr r3, [r7, #12] 8001c58: f893 3020 ldrb.w r3, [r3, #32] 8001c5c: 2b01 cmp r3, #1 8001c5e: d101 bne.n 8001c64 8001c60: 2302 movs r3, #2 8001c62: e04a b.n 8001cfa 8001c64: 68fb ldr r3, [r7, #12] 8001c66: 2201 movs r2, #1 8001c68: f883 2020 strb.w r2, [r3, #32] if(HAL_DMA_STATE_READY == hdma->State) 8001c6c: 68fb ldr r3, [r7, #12] 8001c6e: f893 3021 ldrb.w r3, [r3, #33] ; 0x21 8001c72: 2b01 cmp r3, #1 8001c74: d13a bne.n 8001cec { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8001c76: 68fb ldr r3, [r7, #12] 8001c78: 2202 movs r2, #2 8001c7a: f883 2021 strb.w r2, [r3, #33] ; 0x21 hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8001c7e: 68fb ldr r3, [r7, #12] 8001c80: 2200 movs r2, #0 8001c82: 639a str r2, [r3, #56] ; 0x38 /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); 8001c84: 68fb ldr r3, [r7, #12] 8001c86: 681b ldr r3, [r3, #0] 8001c88: 681a ldr r2, [r3, #0] 8001c8a: 68fb ldr r3, [r7, #12] 8001c8c: 681b ldr r3, [r3, #0] 8001c8e: f022 0201 bic.w r2, r2, #1 8001c92: 601a str r2, [r3, #0] /* Configure the source, destination address and the data length & clear flags*/ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); 8001c94: 683b ldr r3, [r7, #0] 8001c96: 687a ldr r2, [r7, #4] 8001c98: 68b9 ldr r1, [r7, #8] 8001c9a: 68f8 ldr r0, [r7, #12] 8001c9c: f000 f9ae bl 8001ffc /* Enable the transfer complete interrupt */ /* Enable the transfer Error interrupt */ if(NULL != hdma->XferHalfCpltCallback) 8001ca0: 68fb ldr r3, [r7, #12] 8001ca2: 6adb ldr r3, [r3, #44] ; 0x2c 8001ca4: 2b00 cmp r3, #0 8001ca6: d008 beq.n 8001cba { /* Enable the Half transfer complete interrupt as well */ __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8001ca8: 68fb ldr r3, [r7, #12] 8001caa: 681b ldr r3, [r3, #0] 8001cac: 681a ldr r2, [r3, #0] 8001cae: 68fb ldr r3, [r7, #12] 8001cb0: 681b ldr r3, [r3, #0] 8001cb2: f042 020e orr.w r2, r2, #14 8001cb6: 601a str r2, [r3, #0] 8001cb8: e00f b.n 8001cda } else { __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 8001cba: 68fb ldr r3, [r7, #12] 8001cbc: 681b ldr r3, [r3, #0] 8001cbe: 681a ldr r2, [r3, #0] 8001cc0: 68fb ldr r3, [r7, #12] 8001cc2: 681b ldr r3, [r3, #0] 8001cc4: f022 0204 bic.w r2, r2, #4 8001cc8: 601a str r2, [r3, #0] __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); 8001cca: 68fb ldr r3, [r7, #12] 8001ccc: 681b ldr r3, [r3, #0] 8001cce: 681a ldr r2, [r3, #0] 8001cd0: 68fb ldr r3, [r7, #12] 8001cd2: 681b ldr r3, [r3, #0] 8001cd4: f042 020a orr.w r2, r2, #10 8001cd8: 601a str r2, [r3, #0] } /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); 8001cda: 68fb ldr r3, [r7, #12] 8001cdc: 681b ldr r3, [r3, #0] 8001cde: 681a ldr r2, [r3, #0] 8001ce0: 68fb ldr r3, [r7, #12] 8001ce2: 681b ldr r3, [r3, #0] 8001ce4: f042 0201 orr.w r2, r2, #1 8001ce8: 601a str r2, [r3, #0] 8001cea: e005 b.n 8001cf8 } else { /* Process Unlocked */ __HAL_UNLOCK(hdma); 8001cec: 68fb ldr r3, [r7, #12] 8001cee: 2200 movs r2, #0 8001cf0: f883 2020 strb.w r2, [r3, #32] /* Remain BUSY */ status = HAL_BUSY; 8001cf4: 2302 movs r3, #2 8001cf6: 75fb strb r3, [r7, #23] } return status; 8001cf8: 7dfb ldrb r3, [r7, #23] } 8001cfa: 4618 mov r0, r3 8001cfc: 3718 adds r7, #24 8001cfe: 46bd mov sp, r7 8001d00: bd80 pop {r7, pc} ... 08001d04 : * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 8001d04: b580 push {r7, lr} 8001d06: b084 sub sp, #16 8001d08: af00 add r7, sp, #0 8001d0a: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8001d0c: 2300 movs r3, #0 8001d0e: 73fb strb r3, [r7, #15] if(HAL_DMA_STATE_BUSY != hdma->State) 8001d10: 687b ldr r3, [r7, #4] 8001d12: f893 3021 ldrb.w r3, [r3, #33] ; 0x21 8001d16: 2b02 cmp r3, #2 8001d18: d005 beq.n 8001d26 { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8001d1a: 687b ldr r3, [r7, #4] 8001d1c: 2204 movs r2, #4 8001d1e: 639a str r2, [r3, #56] ; 0x38 status = HAL_ERROR; 8001d20: 2301 movs r3, #1 8001d22: 73fb strb r3, [r7, #15] 8001d24: e051 b.n 8001dca } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8001d26: 687b ldr r3, [r7, #4] 8001d28: 681b ldr r3, [r3, #0] 8001d2a: 681a ldr r2, [r3, #0] 8001d2c: 687b ldr r3, [r7, #4] 8001d2e: 681b ldr r3, [r3, #0] 8001d30: f022 020e bic.w r2, r2, #14 8001d34: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 8001d36: 687b ldr r3, [r7, #4] 8001d38: 681b ldr r3, [r3, #0] 8001d3a: 681a ldr r2, [r3, #0] 8001d3c: 687b ldr r3, [r7, #4] 8001d3e: 681b ldr r3, [r3, #0] 8001d40: f022 0201 bic.w r2, r2, #1 8001d44: 601a str r2, [r3, #0] /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); 8001d46: 687b ldr r3, [r7, #4] 8001d48: 681b ldr r3, [r3, #0] 8001d4a: 4a22 ldr r2, [pc, #136] ; (8001dd4 ) 8001d4c: 4293 cmp r3, r2 8001d4e: d029 beq.n 8001da4 8001d50: 687b ldr r3, [r7, #4] 8001d52: 681b ldr r3, [r3, #0] 8001d54: 4a20 ldr r2, [pc, #128] ; (8001dd8 ) 8001d56: 4293 cmp r3, r2 8001d58: d022 beq.n 8001da0 8001d5a: 687b ldr r3, [r7, #4] 8001d5c: 681b ldr r3, [r3, #0] 8001d5e: 4a1f ldr r2, [pc, #124] ; (8001ddc ) 8001d60: 4293 cmp r3, r2 8001d62: d01a beq.n 8001d9a 8001d64: 687b ldr r3, [r7, #4] 8001d66: 681b ldr r3, [r3, #0] 8001d68: 4a1d ldr r2, [pc, #116] ; (8001de0 ) 8001d6a: 4293 cmp r3, r2 8001d6c: d012 beq.n 8001d94 8001d6e: 687b ldr r3, [r7, #4] 8001d70: 681b ldr r3, [r3, #0] 8001d72: 4a1c ldr r2, [pc, #112] ; (8001de4 ) 8001d74: 4293 cmp r3, r2 8001d76: d00a beq.n 8001d8e 8001d78: 687b ldr r3, [r7, #4] 8001d7a: 681b ldr r3, [r3, #0] 8001d7c: 4a1a ldr r2, [pc, #104] ; (8001de8 ) 8001d7e: 4293 cmp r3, r2 8001d80: d102 bne.n 8001d88 8001d82: f44f 1380 mov.w r3, #1048576 ; 0x100000 8001d86: e00e b.n 8001da6 8001d88: f04f 7380 mov.w r3, #16777216 ; 0x1000000 8001d8c: e00b b.n 8001da6 8001d8e: f44f 3380 mov.w r3, #65536 ; 0x10000 8001d92: e008 b.n 8001da6 8001d94: f44f 5380 mov.w r3, #4096 ; 0x1000 8001d98: e005 b.n 8001da6 8001d9a: f44f 7380 mov.w r3, #256 ; 0x100 8001d9e: e002 b.n 8001da6 8001da0: 2310 movs r3, #16 8001da2: e000 b.n 8001da6 8001da4: 2301 movs r3, #1 8001da6: 4a11 ldr r2, [pc, #68] ; (8001dec ) 8001da8: 6053 str r3, [r2, #4] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8001daa: 687b ldr r3, [r7, #4] 8001dac: 2201 movs r2, #1 8001dae: f883 2021 strb.w r2, [r3, #33] ; 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8001db2: 687b ldr r3, [r7, #4] 8001db4: 2200 movs r2, #0 8001db6: f883 2020 strb.w r2, [r3, #32] /* Call User Abort callback */ if(hdma->XferAbortCallback != NULL) 8001dba: 687b ldr r3, [r7, #4] 8001dbc: 6b5b ldr r3, [r3, #52] ; 0x34 8001dbe: 2b00 cmp r3, #0 8001dc0: d003 beq.n 8001dca { hdma->XferAbortCallback(hdma); 8001dc2: 687b ldr r3, [r7, #4] 8001dc4: 6b5b ldr r3, [r3, #52] ; 0x34 8001dc6: 6878 ldr r0, [r7, #4] 8001dc8: 4798 blx r3 } } return status; 8001dca: 7bfb ldrb r3, [r7, #15] } 8001dcc: 4618 mov r0, r3 8001dce: 3710 adds r7, #16 8001dd0: 46bd mov sp, r7 8001dd2: bd80 pop {r7, pc} 8001dd4: 40020008 .word 0x40020008 8001dd8: 4002001c .word 0x4002001c 8001ddc: 40020030 .word 0x40020030 8001de0: 40020044 .word 0x40020044 8001de4: 40020058 .word 0x40020058 8001de8: 4002006c .word 0x4002006c 8001dec: 40020000 .word 0x40020000 08001df0 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { 8001df0: b580 push {r7, lr} 8001df2: b084 sub sp, #16 8001df4: af00 add r7, sp, #0 8001df6: 6078 str r0, [r7, #4] uint32_t flag_it = hdma->DmaBaseAddress->ISR; 8001df8: 687b ldr r3, [r7, #4] 8001dfa: 6bdb ldr r3, [r3, #60] ; 0x3c 8001dfc: 681b ldr r3, [r3, #0] 8001dfe: 60fb str r3, [r7, #12] uint32_t source_it = hdma->Instance->CCR; 8001e00: 687b ldr r3, [r7, #4] 8001e02: 681b ldr r3, [r3, #0] 8001e04: 681b ldr r3, [r3, #0] 8001e06: 60bb str r3, [r7, #8] /* Half Transfer Complete Interrupt management ******************************/ if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET)) 8001e08: 687b ldr r3, [r7, #4] 8001e0a: 6c1b ldr r3, [r3, #64] ; 0x40 8001e0c: 2204 movs r2, #4 8001e0e: 409a lsls r2, r3 8001e10: 68fb ldr r3, [r7, #12] 8001e12: 4013 ands r3, r2 8001e14: 2b00 cmp r3, #0 8001e16: d04f beq.n 8001eb8 8001e18: 68bb ldr r3, [r7, #8] 8001e1a: f003 0304 and.w r3, r3, #4 8001e1e: 2b00 cmp r3, #0 8001e20: d04a beq.n 8001eb8 { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 8001e22: 687b ldr r3, [r7, #4] 8001e24: 681b ldr r3, [r3, #0] 8001e26: 681b ldr r3, [r3, #0] 8001e28: f003 0320 and.w r3, r3, #32 8001e2c: 2b00 cmp r3, #0 8001e2e: d107 bne.n 8001e40 { /* Disable the half transfer interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 8001e30: 687b ldr r3, [r7, #4] 8001e32: 681b ldr r3, [r3, #0] 8001e34: 681a ldr r2, [r3, #0] 8001e36: 687b ldr r3, [r7, #4] 8001e38: 681b ldr r3, [r3, #0] 8001e3a: f022 0204 bic.w r2, r2, #4 8001e3e: 601a str r2, [r3, #0] } /* Clear the half transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); 8001e40: 687b ldr r3, [r7, #4] 8001e42: 681b ldr r3, [r3, #0] 8001e44: 4a66 ldr r2, [pc, #408] ; (8001fe0 ) 8001e46: 4293 cmp r3, r2 8001e48: d029 beq.n 8001e9e 8001e4a: 687b ldr r3, [r7, #4] 8001e4c: 681b ldr r3, [r3, #0] 8001e4e: 4a65 ldr r2, [pc, #404] ; (8001fe4 ) 8001e50: 4293 cmp r3, r2 8001e52: d022 beq.n 8001e9a 8001e54: 687b ldr r3, [r7, #4] 8001e56: 681b ldr r3, [r3, #0] 8001e58: 4a63 ldr r2, [pc, #396] ; (8001fe8 ) 8001e5a: 4293 cmp r3, r2 8001e5c: d01a beq.n 8001e94 8001e5e: 687b ldr r3, [r7, #4] 8001e60: 681b ldr r3, [r3, #0] 8001e62: 4a62 ldr r2, [pc, #392] ; (8001fec ) 8001e64: 4293 cmp r3, r2 8001e66: d012 beq.n 8001e8e 8001e68: 687b ldr r3, [r7, #4] 8001e6a: 681b ldr r3, [r3, #0] 8001e6c: 4a60 ldr r2, [pc, #384] ; (8001ff0 ) 8001e6e: 4293 cmp r3, r2 8001e70: d00a beq.n 8001e88 8001e72: 687b ldr r3, [r7, #4] 8001e74: 681b ldr r3, [r3, #0] 8001e76: 4a5f ldr r2, [pc, #380] ; (8001ff4 ) 8001e78: 4293 cmp r3, r2 8001e7a: d102 bne.n 8001e82 8001e7c: f44f 0380 mov.w r3, #4194304 ; 0x400000 8001e80: e00e b.n 8001ea0 8001e82: f04f 6380 mov.w r3, #67108864 ; 0x4000000 8001e86: e00b b.n 8001ea0 8001e88: f44f 2380 mov.w r3, #262144 ; 0x40000 8001e8c: e008 b.n 8001ea0 8001e8e: f44f 4380 mov.w r3, #16384 ; 0x4000 8001e92: e005 b.n 8001ea0 8001e94: f44f 6380 mov.w r3, #1024 ; 0x400 8001e98: e002 b.n 8001ea0 8001e9a: 2340 movs r3, #64 ; 0x40 8001e9c: e000 b.n 8001ea0 8001e9e: 2304 movs r3, #4 8001ea0: 4a55 ldr r2, [pc, #340] ; (8001ff8 ) 8001ea2: 6053 str r3, [r2, #4] /* DMA peripheral state is not updated in Half Transfer */ /* but in Transfer Complete case */ if(hdma->XferHalfCpltCallback != NULL) 8001ea4: 687b ldr r3, [r7, #4] 8001ea6: 6adb ldr r3, [r3, #44] ; 0x2c 8001ea8: 2b00 cmp r3, #0 8001eaa: f000 8094 beq.w 8001fd6 { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 8001eae: 687b ldr r3, [r7, #4] 8001eb0: 6adb ldr r3, [r3, #44] ; 0x2c 8001eb2: 6878 ldr r0, [r7, #4] 8001eb4: 4798 blx r3 if(hdma->XferHalfCpltCallback != NULL) 8001eb6: e08e b.n 8001fd6 } } /* Transfer Complete Interrupt management ***********************************/ else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET)) 8001eb8: 687b ldr r3, [r7, #4] 8001eba: 6c1b ldr r3, [r3, #64] ; 0x40 8001ebc: 2202 movs r2, #2 8001ebe: 409a lsls r2, r3 8001ec0: 68fb ldr r3, [r7, #12] 8001ec2: 4013 ands r3, r2 8001ec4: 2b00 cmp r3, #0 8001ec6: d056 beq.n 8001f76 8001ec8: 68bb ldr r3, [r7, #8] 8001eca: f003 0302 and.w r3, r3, #2 8001ece: 2b00 cmp r3, #0 8001ed0: d051 beq.n 8001f76 { if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 8001ed2: 687b ldr r3, [r7, #4] 8001ed4: 681b ldr r3, [r3, #0] 8001ed6: 681b ldr r3, [r3, #0] 8001ed8: f003 0320 and.w r3, r3, #32 8001edc: 2b00 cmp r3, #0 8001ede: d10b bne.n 8001ef8 { /* Disable the transfer complete and error interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); 8001ee0: 687b ldr r3, [r7, #4] 8001ee2: 681b ldr r3, [r3, #0] 8001ee4: 681a ldr r2, [r3, #0] 8001ee6: 687b ldr r3, [r7, #4] 8001ee8: 681b ldr r3, [r3, #0] 8001eea: f022 020a bic.w r2, r2, #10 8001eee: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8001ef0: 687b ldr r3, [r7, #4] 8001ef2: 2201 movs r2, #1 8001ef4: f883 2021 strb.w r2, [r3, #33] ; 0x21 } /* Clear the transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); 8001ef8: 687b ldr r3, [r7, #4] 8001efa: 681b ldr r3, [r3, #0] 8001efc: 4a38 ldr r2, [pc, #224] ; (8001fe0 ) 8001efe: 4293 cmp r3, r2 8001f00: d029 beq.n 8001f56 8001f02: 687b ldr r3, [r7, #4] 8001f04: 681b ldr r3, [r3, #0] 8001f06: 4a37 ldr r2, [pc, #220] ; (8001fe4 ) 8001f08: 4293 cmp r3, r2 8001f0a: d022 beq.n 8001f52 8001f0c: 687b ldr r3, [r7, #4] 8001f0e: 681b ldr r3, [r3, #0] 8001f10: 4a35 ldr r2, [pc, #212] ; (8001fe8 ) 8001f12: 4293 cmp r3, r2 8001f14: d01a beq.n 8001f4c 8001f16: 687b ldr r3, [r7, #4] 8001f18: 681b ldr r3, [r3, #0] 8001f1a: 4a34 ldr r2, [pc, #208] ; (8001fec ) 8001f1c: 4293 cmp r3, r2 8001f1e: d012 beq.n 8001f46 8001f20: 687b ldr r3, [r7, #4] 8001f22: 681b ldr r3, [r3, #0] 8001f24: 4a32 ldr r2, [pc, #200] ; (8001ff0 ) 8001f26: 4293 cmp r3, r2 8001f28: d00a beq.n 8001f40 8001f2a: 687b ldr r3, [r7, #4] 8001f2c: 681b ldr r3, [r3, #0] 8001f2e: 4a31 ldr r2, [pc, #196] ; (8001ff4 ) 8001f30: 4293 cmp r3, r2 8001f32: d102 bne.n 8001f3a 8001f34: f44f 1300 mov.w r3, #2097152 ; 0x200000 8001f38: e00e b.n 8001f58 8001f3a: f04f 7300 mov.w r3, #33554432 ; 0x2000000 8001f3e: e00b b.n 8001f58 8001f40: f44f 3300 mov.w r3, #131072 ; 0x20000 8001f44: e008 b.n 8001f58 8001f46: f44f 5300 mov.w r3, #8192 ; 0x2000 8001f4a: e005 b.n 8001f58 8001f4c: f44f 7300 mov.w r3, #512 ; 0x200 8001f50: e002 b.n 8001f58 8001f52: 2320 movs r3, #32 8001f54: e000 b.n 8001f58 8001f56: 2302 movs r3, #2 8001f58: 4a27 ldr r2, [pc, #156] ; (8001ff8 ) 8001f5a: 6053 str r3, [r2, #4] /* Process Unlocked */ __HAL_UNLOCK(hdma); 8001f5c: 687b ldr r3, [r7, #4] 8001f5e: 2200 movs r2, #0 8001f60: f883 2020 strb.w r2, [r3, #32] if(hdma->XferCpltCallback != NULL) 8001f64: 687b ldr r3, [r7, #4] 8001f66: 6a9b ldr r3, [r3, #40] ; 0x28 8001f68: 2b00 cmp r3, #0 8001f6a: d034 beq.n 8001fd6 { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 8001f6c: 687b ldr r3, [r7, #4] 8001f6e: 6a9b ldr r3, [r3, #40] ; 0x28 8001f70: 6878 ldr r0, [r7, #4] 8001f72: 4798 blx r3 if(hdma->XferCpltCallback != NULL) 8001f74: e02f b.n 8001fd6 } } /* Transfer Error Interrupt management **************************************/ else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE))) 8001f76: 687b ldr r3, [r7, #4] 8001f78: 6c1b ldr r3, [r3, #64] ; 0x40 8001f7a: 2208 movs r2, #8 8001f7c: 409a lsls r2, r3 8001f7e: 68fb ldr r3, [r7, #12] 8001f80: 4013 ands r3, r2 8001f82: 2b00 cmp r3, #0 8001f84: d028 beq.n 8001fd8 8001f86: 68bb ldr r3, [r7, #8] 8001f88: f003 0308 and.w r3, r3, #8 8001f8c: 2b00 cmp r3, #0 8001f8e: d023 beq.n 8001fd8 { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ /* Disable ALL DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8001f90: 687b ldr r3, [r7, #4] 8001f92: 681b ldr r3, [r3, #0] 8001f94: 681a ldr r2, [r3, #0] 8001f96: 687b ldr r3, [r7, #4] 8001f98: 681b ldr r3, [r3, #0] 8001f9a: f022 020e bic.w r2, r2, #14 8001f9e: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); 8001fa0: 687b ldr r3, [r7, #4] 8001fa2: 6c1a ldr r2, [r3, #64] ; 0x40 8001fa4: 687b ldr r3, [r7, #4] 8001fa6: 6bdb ldr r3, [r3, #60] ; 0x3c 8001fa8: 2101 movs r1, #1 8001faa: fa01 f202 lsl.w r2, r1, r2 8001fae: 605a str r2, [r3, #4] /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; 8001fb0: 687b ldr r3, [r7, #4] 8001fb2: 2201 movs r2, #1 8001fb4: 639a str r2, [r3, #56] ; 0x38 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8001fb6: 687b ldr r3, [r7, #4] 8001fb8: 2201 movs r2, #1 8001fba: f883 2021 strb.w r2, [r3, #33] ; 0x21 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8001fbe: 687b ldr r3, [r7, #4] 8001fc0: 2200 movs r2, #0 8001fc2: f883 2020 strb.w r2, [r3, #32] if (hdma->XferErrorCallback != NULL) 8001fc6: 687b ldr r3, [r7, #4] 8001fc8: 6b1b ldr r3, [r3, #48] ; 0x30 8001fca: 2b00 cmp r3, #0 8001fcc: d004 beq.n 8001fd8 { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 8001fce: 687b ldr r3, [r7, #4] 8001fd0: 6b1b ldr r3, [r3, #48] ; 0x30 8001fd2: 6878 ldr r0, [r7, #4] 8001fd4: 4798 blx r3 } } return; 8001fd6: bf00 nop 8001fd8: bf00 nop } 8001fda: 3710 adds r7, #16 8001fdc: 46bd mov sp, r7 8001fde: bd80 pop {r7, pc} 8001fe0: 40020008 .word 0x40020008 8001fe4: 4002001c .word 0x4002001c 8001fe8: 40020030 .word 0x40020030 8001fec: 40020044 .word 0x40020044 8001ff0: 40020058 .word 0x40020058 8001ff4: 4002006c .word 0x4002006c 8001ff8: 40020000 .word 0x40020000 08001ffc : * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval HAL status */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 8001ffc: b480 push {r7} 8001ffe: b085 sub sp, #20 8002000: af00 add r7, sp, #0 8002002: 60f8 str r0, [r7, #12] 8002004: 60b9 str r1, [r7, #8] 8002006: 607a str r2, [r7, #4] 8002008: 603b str r3, [r7, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); 800200a: 68fb ldr r3, [r7, #12] 800200c: 6c1a ldr r2, [r3, #64] ; 0x40 800200e: 68fb ldr r3, [r7, #12] 8002010: 6bdb ldr r3, [r3, #60] ; 0x3c 8002012: 2101 movs r1, #1 8002014: fa01 f202 lsl.w r2, r1, r2 8002018: 605a str r2, [r3, #4] /* Configure DMA Channel data length */ hdma->Instance->CNDTR = DataLength; 800201a: 68fb ldr r3, [r7, #12] 800201c: 681b ldr r3, [r3, #0] 800201e: 683a ldr r2, [r7, #0] 8002020: 605a str r2, [r3, #4] /* Memory to Peripheral */ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 8002022: 68fb ldr r3, [r7, #12] 8002024: 685b ldr r3, [r3, #4] 8002026: 2b10 cmp r3, #16 8002028: d108 bne.n 800203c { /* Configure DMA Channel destination address */ hdma->Instance->CPAR = DstAddress; 800202a: 68fb ldr r3, [r7, #12] 800202c: 681b ldr r3, [r3, #0] 800202e: 687a ldr r2, [r7, #4] 8002030: 609a str r2, [r3, #8] /* Configure DMA Channel source address */ hdma->Instance->CMAR = SrcAddress; 8002032: 68fb ldr r3, [r7, #12] 8002034: 681b ldr r3, [r3, #0] 8002036: 68ba ldr r2, [r7, #8] 8002038: 60da str r2, [r3, #12] hdma->Instance->CPAR = SrcAddress; /* Configure DMA Channel destination address */ hdma->Instance->CMAR = DstAddress; } } 800203a: e007 b.n 800204c hdma->Instance->CPAR = SrcAddress; 800203c: 68fb ldr r3, [r7, #12] 800203e: 681b ldr r3, [r3, #0] 8002040: 68ba ldr r2, [r7, #8] 8002042: 609a str r2, [r3, #8] hdma->Instance->CMAR = DstAddress; 8002044: 68fb ldr r3, [r7, #12] 8002046: 681b ldr r3, [r3, #0] 8002048: 687a ldr r2, [r7, #4] 800204a: 60da str r2, [r3, #12] } 800204c: bf00 nop 800204e: 3714 adds r7, #20 8002050: 46bd mov sp, r7 8002052: bc80 pop {r7} 8002054: 4770 bx lr ... 08002058 : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8002058: b480 push {r7} 800205a: b08b sub sp, #44 ; 0x2c 800205c: af00 add r7, sp, #0 800205e: 6078 str r0, [r7, #4] 8002060: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 8002062: 2300 movs r3, #0 8002064: 627b str r3, [r7, #36] ; 0x24 uint32_t ioposition; uint32_t iocurrent; uint32_t temp; uint32_t config = 0x00u; 8002066: 2300 movs r3, #0 8002068: 623b str r3, [r7, #32] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 800206a: e127 b.n 80022bc { /* Get the IO position */ ioposition = (0x01uL << position); 800206c: 2201 movs r2, #1 800206e: 6a7b ldr r3, [r7, #36] ; 0x24 8002070: fa02 f303 lsl.w r3, r2, r3 8002074: 61fb str r3, [r7, #28] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 8002076: 683b ldr r3, [r7, #0] 8002078: 681b ldr r3, [r3, #0] 800207a: 69fa ldr r2, [r7, #28] 800207c: 4013 ands r3, r2 800207e: 61bb str r3, [r7, #24] if (iocurrent == ioposition) 8002080: 69ba ldr r2, [r7, #24] 8002082: 69fb ldr r3, [r7, #28] 8002084: 429a cmp r2, r3 8002086: f040 8116 bne.w 80022b6 { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */ switch (GPIO_Init->Mode) 800208a: 683b ldr r3, [r7, #0] 800208c: 685b ldr r3, [r3, #4] 800208e: 2b12 cmp r3, #18 8002090: d034 beq.n 80020fc 8002092: 2b12 cmp r3, #18 8002094: d80d bhi.n 80020b2 8002096: 2b02 cmp r3, #2 8002098: d02b beq.n 80020f2 800209a: 2b02 cmp r3, #2 800209c: d804 bhi.n 80020a8 800209e: 2b00 cmp r3, #0 80020a0: d031 beq.n 8002106 80020a2: 2b01 cmp r3, #1 80020a4: d01c beq.n 80020e0 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; break; /* Parameters are checked with assert_param */ default: break; 80020a6: e048 b.n 800213a switch (GPIO_Init->Mode) 80020a8: 2b03 cmp r3, #3 80020aa: d043 beq.n 8002134 80020ac: 2b11 cmp r3, #17 80020ae: d01b beq.n 80020e8 break; 80020b0: e043 b.n 800213a switch (GPIO_Init->Mode) 80020b2: 4a89 ldr r2, [pc, #548] ; (80022d8 ) 80020b4: 4293 cmp r3, r2 80020b6: d026 beq.n 8002106 80020b8: 4a87 ldr r2, [pc, #540] ; (80022d8 ) 80020ba: 4293 cmp r3, r2 80020bc: d806 bhi.n 80020cc 80020be: 4a87 ldr r2, [pc, #540] ; (80022dc ) 80020c0: 4293 cmp r3, r2 80020c2: d020 beq.n 8002106 80020c4: 4a86 ldr r2, [pc, #536] ; (80022e0 ) 80020c6: 4293 cmp r3, r2 80020c8: d01d beq.n 8002106 break; 80020ca: e036 b.n 800213a switch (GPIO_Init->Mode) 80020cc: 4a85 ldr r2, [pc, #532] ; (80022e4 ) 80020ce: 4293 cmp r3, r2 80020d0: d019 beq.n 8002106 80020d2: 4a85 ldr r2, [pc, #532] ; (80022e8 ) 80020d4: 4293 cmp r3, r2 80020d6: d016 beq.n 8002106 80020d8: 4a84 ldr r2, [pc, #528] ; (80022ec ) 80020da: 4293 cmp r3, r2 80020dc: d013 beq.n 8002106 break; 80020de: e02c b.n 800213a config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP; 80020e0: 683b ldr r3, [r7, #0] 80020e2: 68db ldr r3, [r3, #12] 80020e4: 623b str r3, [r7, #32] break; 80020e6: e028 b.n 800213a config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD; 80020e8: 683b ldr r3, [r7, #0] 80020ea: 68db ldr r3, [r3, #12] 80020ec: 3304 adds r3, #4 80020ee: 623b str r3, [r7, #32] break; 80020f0: e023 b.n 800213a config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP; 80020f2: 683b ldr r3, [r7, #0] 80020f4: 68db ldr r3, [r3, #12] 80020f6: 3308 adds r3, #8 80020f8: 623b str r3, [r7, #32] break; 80020fa: e01e b.n 800213a config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD; 80020fc: 683b ldr r3, [r7, #0] 80020fe: 68db ldr r3, [r3, #12] 8002100: 330c adds r3, #12 8002102: 623b str r3, [r7, #32] break; 8002104: e019 b.n 800213a if (GPIO_Init->Pull == GPIO_NOPULL) 8002106: 683b ldr r3, [r7, #0] 8002108: 689b ldr r3, [r3, #8] 800210a: 2b00 cmp r3, #0 800210c: d102 bne.n 8002114 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING; 800210e: 2304 movs r3, #4 8002110: 623b str r3, [r7, #32] break; 8002112: e012 b.n 800213a else if (GPIO_Init->Pull == GPIO_PULLUP) 8002114: 683b ldr r3, [r7, #0] 8002116: 689b ldr r3, [r3, #8] 8002118: 2b01 cmp r3, #1 800211a: d105 bne.n 8002128 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 800211c: 2308 movs r3, #8 800211e: 623b str r3, [r7, #32] GPIOx->BSRR = ioposition; 8002120: 687b ldr r3, [r7, #4] 8002122: 69fa ldr r2, [r7, #28] 8002124: 611a str r2, [r3, #16] break; 8002126: e008 b.n 800213a config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD; 8002128: 2308 movs r3, #8 800212a: 623b str r3, [r7, #32] GPIOx->BRR = ioposition; 800212c: 687b ldr r3, [r7, #4] 800212e: 69fa ldr r2, [r7, #28] 8002130: 615a str r2, [r3, #20] break; 8002132: e002 b.n 800213a config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG; 8002134: 2300 movs r3, #0 8002136: 623b str r3, [r7, #32] break; 8002138: bf00 nop } /* Check if the current bit belongs to first half or last half of the pin count number in order to address CRH or CRL register*/ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; 800213a: 69bb ldr r3, [r7, #24] 800213c: 2bff cmp r3, #255 ; 0xff 800213e: d801 bhi.n 8002144 8002140: 687b ldr r3, [r7, #4] 8002142: e001 b.n 8002148 8002144: 687b ldr r3, [r7, #4] 8002146: 3304 adds r3, #4 8002148: 617b str r3, [r7, #20] registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u); 800214a: 69bb ldr r3, [r7, #24] 800214c: 2bff cmp r3, #255 ; 0xff 800214e: d802 bhi.n 8002156 8002150: 6a7b ldr r3, [r7, #36] ; 0x24 8002152: 009b lsls r3, r3, #2 8002154: e002 b.n 800215c 8002156: 6a7b ldr r3, [r7, #36] ; 0x24 8002158: 3b08 subs r3, #8 800215a: 009b lsls r3, r3, #2 800215c: 613b str r3, [r7, #16] /* Apply the new configuration of the pin to the register */ MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset)); 800215e: 697b ldr r3, [r7, #20] 8002160: 681a ldr r2, [r3, #0] 8002162: 210f movs r1, #15 8002164: 693b ldr r3, [r7, #16] 8002166: fa01 f303 lsl.w r3, r1, r3 800216a: 43db mvns r3, r3 800216c: 401a ands r2, r3 800216e: 6a39 ldr r1, [r7, #32] 8002170: 693b ldr r3, [r7, #16] 8002172: fa01 f303 lsl.w r3, r1, r3 8002176: 431a orrs r2, r3 8002178: 697b ldr r3, [r7, #20] 800217a: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 800217c: 683b ldr r3, [r7, #0] 800217e: 685b ldr r3, [r3, #4] 8002180: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8002184: 2b00 cmp r3, #0 8002186: f000 8096 beq.w 80022b6 { /* Enable AFIO Clock */ __HAL_RCC_AFIO_CLK_ENABLE(); 800218a: 4b59 ldr r3, [pc, #356] ; (80022f0 ) 800218c: 699b ldr r3, [r3, #24] 800218e: 4a58 ldr r2, [pc, #352] ; (80022f0 ) 8002190: f043 0301 orr.w r3, r3, #1 8002194: 6193 str r3, [r2, #24] 8002196: 4b56 ldr r3, [pc, #344] ; (80022f0 ) 8002198: 699b ldr r3, [r3, #24] 800219a: f003 0301 and.w r3, r3, #1 800219e: 60bb str r3, [r7, #8] 80021a0: 68bb ldr r3, [r7, #8] temp = AFIO->EXTICR[position >> 2u]; 80021a2: 4a54 ldr r2, [pc, #336] ; (80022f4 ) 80021a4: 6a7b ldr r3, [r7, #36] ; 0x24 80021a6: 089b lsrs r3, r3, #2 80021a8: 3302 adds r3, #2 80021aa: f852 3023 ldr.w r3, [r2, r3, lsl #2] 80021ae: 60fb str r3, [r7, #12] CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u))); 80021b0: 6a7b ldr r3, [r7, #36] ; 0x24 80021b2: f003 0303 and.w r3, r3, #3 80021b6: 009b lsls r3, r3, #2 80021b8: 220f movs r2, #15 80021ba: fa02 f303 lsl.w r3, r2, r3 80021be: 43db mvns r3, r3 80021c0: 68fa ldr r2, [r7, #12] 80021c2: 4013 ands r3, r2 80021c4: 60fb str r3, [r7, #12] SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u))); 80021c6: 687b ldr r3, [r7, #4] 80021c8: 4a4b ldr r2, [pc, #300] ; (80022f8 ) 80021ca: 4293 cmp r3, r2 80021cc: d013 beq.n 80021f6 80021ce: 687b ldr r3, [r7, #4] 80021d0: 4a4a ldr r2, [pc, #296] ; (80022fc ) 80021d2: 4293 cmp r3, r2 80021d4: d00d beq.n 80021f2 80021d6: 687b ldr r3, [r7, #4] 80021d8: 4a49 ldr r2, [pc, #292] ; (8002300 ) 80021da: 4293 cmp r3, r2 80021dc: d007 beq.n 80021ee 80021de: 687b ldr r3, [r7, #4] 80021e0: 4a48 ldr r2, [pc, #288] ; (8002304 ) 80021e2: 4293 cmp r3, r2 80021e4: d101 bne.n 80021ea 80021e6: 2303 movs r3, #3 80021e8: e006 b.n 80021f8 80021ea: 2304 movs r3, #4 80021ec: e004 b.n 80021f8 80021ee: 2302 movs r3, #2 80021f0: e002 b.n 80021f8 80021f2: 2301 movs r3, #1 80021f4: e000 b.n 80021f8 80021f6: 2300 movs r3, #0 80021f8: 6a7a ldr r2, [r7, #36] ; 0x24 80021fa: f002 0203 and.w r2, r2, #3 80021fe: 0092 lsls r2, r2, #2 8002200: 4093 lsls r3, r2 8002202: 68fa ldr r2, [r7, #12] 8002204: 4313 orrs r3, r2 8002206: 60fb str r3, [r7, #12] AFIO->EXTICR[position >> 2u] = temp; 8002208: 493a ldr r1, [pc, #232] ; (80022f4 ) 800220a: 6a7b ldr r3, [r7, #36] ; 0x24 800220c: 089b lsrs r3, r3, #2 800220e: 3302 adds r3, #2 8002210: 68fa ldr r2, [r7, #12] 8002212: f841 2023 str.w r2, [r1, r3, lsl #2] /* Configure the interrupt mask */ if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) 8002216: 683b ldr r3, [r7, #0] 8002218: 685b ldr r3, [r3, #4] 800221a: f403 3380 and.w r3, r3, #65536 ; 0x10000 800221e: 2b00 cmp r3, #0 8002220: d006 beq.n 8002230 { SET_BIT(EXTI->IMR, iocurrent); 8002222: 4b39 ldr r3, [pc, #228] ; (8002308 ) 8002224: 681a ldr r2, [r3, #0] 8002226: 4938 ldr r1, [pc, #224] ; (8002308 ) 8002228: 69bb ldr r3, [r7, #24] 800222a: 4313 orrs r3, r2 800222c: 600b str r3, [r1, #0] 800222e: e006 b.n 800223e } else { CLEAR_BIT(EXTI->IMR, iocurrent); 8002230: 4b35 ldr r3, [pc, #212] ; (8002308 ) 8002232: 681a ldr r2, [r3, #0] 8002234: 69bb ldr r3, [r7, #24] 8002236: 43db mvns r3, r3 8002238: 4933 ldr r1, [pc, #204] ; (8002308 ) 800223a: 4013 ands r3, r2 800223c: 600b str r3, [r1, #0] } /* Configure the event mask */ if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) 800223e: 683b ldr r3, [r7, #0] 8002240: 685b ldr r3, [r3, #4] 8002242: f403 3300 and.w r3, r3, #131072 ; 0x20000 8002246: 2b00 cmp r3, #0 8002248: d006 beq.n 8002258 { SET_BIT(EXTI->EMR, iocurrent); 800224a: 4b2f ldr r3, [pc, #188] ; (8002308 ) 800224c: 685a ldr r2, [r3, #4] 800224e: 492e ldr r1, [pc, #184] ; (8002308 ) 8002250: 69bb ldr r3, [r7, #24] 8002252: 4313 orrs r3, r2 8002254: 604b str r3, [r1, #4] 8002256: e006 b.n 8002266 } else { CLEAR_BIT(EXTI->EMR, iocurrent); 8002258: 4b2b ldr r3, [pc, #172] ; (8002308 ) 800225a: 685a ldr r2, [r3, #4] 800225c: 69bb ldr r3, [r7, #24] 800225e: 43db mvns r3, r3 8002260: 4929 ldr r1, [pc, #164] ; (8002308 ) 8002262: 4013 ands r3, r2 8002264: 604b str r3, [r1, #4] } /* Enable or disable the rising trigger */ if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) 8002266: 683b ldr r3, [r7, #0] 8002268: 685b ldr r3, [r3, #4] 800226a: f403 1380 and.w r3, r3, #1048576 ; 0x100000 800226e: 2b00 cmp r3, #0 8002270: d006 beq.n 8002280 { SET_BIT(EXTI->RTSR, iocurrent); 8002272: 4b25 ldr r3, [pc, #148] ; (8002308 ) 8002274: 689a ldr r2, [r3, #8] 8002276: 4924 ldr r1, [pc, #144] ; (8002308 ) 8002278: 69bb ldr r3, [r7, #24] 800227a: 4313 orrs r3, r2 800227c: 608b str r3, [r1, #8] 800227e: e006 b.n 800228e } else { CLEAR_BIT(EXTI->RTSR, iocurrent); 8002280: 4b21 ldr r3, [pc, #132] ; (8002308 ) 8002282: 689a ldr r2, [r3, #8] 8002284: 69bb ldr r3, [r7, #24] 8002286: 43db mvns r3, r3 8002288: 491f ldr r1, [pc, #124] ; (8002308 ) 800228a: 4013 ands r3, r2 800228c: 608b str r3, [r1, #8] } /* Enable or disable the falling trigger */ if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) 800228e: 683b ldr r3, [r7, #0] 8002290: 685b ldr r3, [r3, #4] 8002292: f403 1300 and.w r3, r3, #2097152 ; 0x200000 8002296: 2b00 cmp r3, #0 8002298: d006 beq.n 80022a8 { SET_BIT(EXTI->FTSR, iocurrent); 800229a: 4b1b ldr r3, [pc, #108] ; (8002308 ) 800229c: 68da ldr r2, [r3, #12] 800229e: 491a ldr r1, [pc, #104] ; (8002308 ) 80022a0: 69bb ldr r3, [r7, #24] 80022a2: 4313 orrs r3, r2 80022a4: 60cb str r3, [r1, #12] 80022a6: e006 b.n 80022b6 } else { CLEAR_BIT(EXTI->FTSR, iocurrent); 80022a8: 4b17 ldr r3, [pc, #92] ; (8002308 ) 80022aa: 68da ldr r2, [r3, #12] 80022ac: 69bb ldr r3, [r7, #24] 80022ae: 43db mvns r3, r3 80022b0: 4915 ldr r1, [pc, #84] ; (8002308 ) 80022b2: 4013 ands r3, r2 80022b4: 60cb str r3, [r1, #12] } } } position++; 80022b6: 6a7b ldr r3, [r7, #36] ; 0x24 80022b8: 3301 adds r3, #1 80022ba: 627b str r3, [r7, #36] ; 0x24 while (((GPIO_Init->Pin) >> position) != 0x00u) 80022bc: 683b ldr r3, [r7, #0] 80022be: 681a ldr r2, [r3, #0] 80022c0: 6a7b ldr r3, [r7, #36] ; 0x24 80022c2: fa22 f303 lsr.w r3, r2, r3 80022c6: 2b00 cmp r3, #0 80022c8: f47f aed0 bne.w 800206c } } 80022cc: bf00 nop 80022ce: 372c adds r7, #44 ; 0x2c 80022d0: 46bd mov sp, r7 80022d2: bc80 pop {r7} 80022d4: 4770 bx lr 80022d6: bf00 nop 80022d8: 10210000 .word 0x10210000 80022dc: 10110000 .word 0x10110000 80022e0: 10120000 .word 0x10120000 80022e4: 10310000 .word 0x10310000 80022e8: 10320000 .word 0x10320000 80022ec: 10220000 .word 0x10220000 80022f0: 40021000 .word 0x40021000 80022f4: 40010000 .word 0x40010000 80022f8: 40010800 .word 0x40010800 80022fc: 40010c00 .word 0x40010c00 8002300: 40011000 .word 0x40011000 8002304: 40011400 .word 0x40011400 8002308: 40010400 .word 0x40010400 0800230c : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 800230c: b480 push {r7} 800230e: b083 sub sp, #12 8002310: af00 add r7, sp, #0 8002312: 6078 str r0, [r7, #4] 8002314: 460b mov r3, r1 8002316: 807b strh r3, [r7, #2] 8002318: 4613 mov r3, r2 800231a: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 800231c: 787b ldrb r3, [r7, #1] 800231e: 2b00 cmp r3, #0 8002320: d003 beq.n 800232a { GPIOx->BSRR = GPIO_Pin; 8002322: 887a ldrh r2, [r7, #2] 8002324: 687b ldr r3, [r7, #4] 8002326: 611a str r2, [r3, #16] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; } } 8002328: e003 b.n 8002332 GPIOx->BSRR = (uint32_t)GPIO_Pin << 16u; 800232a: 887b ldrh r3, [r7, #2] 800232c: 041a lsls r2, r3, #16 800232e: 687b ldr r3, [r7, #4] 8002330: 611a str r2, [r3, #16] } 8002332: bf00 nop 8002334: 370c adds r7, #12 8002336: 46bd mov sp, r7 8002338: bc80 pop {r7} 800233a: 4770 bx lr 0800233c : * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral * @param GPIO_Pin: Specifies the pins to be toggled. * @retval None */ void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 800233c: b480 push {r7} 800233e: b083 sub sp, #12 8002340: af00 add r7, sp, #0 8002342: 6078 str r0, [r7, #4] 8002344: 460b mov r3, r1 8002346: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->ODR & GPIO_Pin) != 0x00u) 8002348: 687b ldr r3, [r7, #4] 800234a: 68da ldr r2, [r3, #12] 800234c: 887b ldrh r3, [r7, #2] 800234e: 4013 ands r3, r2 8002350: 2b00 cmp r3, #0 8002352: d003 beq.n 800235c { GPIOx->BRR = (uint32_t)GPIO_Pin; 8002354: 887a ldrh r2, [r7, #2] 8002356: 687b ldr r3, [r7, #4] 8002358: 615a str r2, [r3, #20] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin; } } 800235a: e002 b.n 8002362 GPIOx->BSRR = (uint32_t)GPIO_Pin; 800235c: 887a ldrh r2, [r7, #2] 800235e: 687b ldr r3, [r7, #4] 8002360: 611a str r2, [r3, #16] } 8002362: bf00 nop 8002364: 370c adds r7, #12 8002366: 46bd mov sp, r7 8002368: bc80 pop {r7} 800236a: 4770 bx lr 0800236c : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 800236c: b580 push {r7, lr} 800236e: b086 sub sp, #24 8002370: af00 add r7, sp, #0 8002372: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 8002374: 687b ldr r3, [r7, #4] 8002376: 2b00 cmp r3, #0 8002378: d101 bne.n 800237e { return HAL_ERROR; 800237a: 2301 movs r3, #1 800237c: e26c b.n 8002858 /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 800237e: 687b ldr r3, [r7, #4] 8002380: 681b ldr r3, [r3, #0] 8002382: f003 0301 and.w r3, r3, #1 8002386: 2b00 cmp r3, #0 8002388: f000 8087 beq.w 800249a { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 800238c: 4b92 ldr r3, [pc, #584] ; (80025d8 ) 800238e: 685b ldr r3, [r3, #4] 8002390: f003 030c and.w r3, r3, #12 8002394: 2b04 cmp r3, #4 8002396: d00c beq.n 80023b2 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 8002398: 4b8f ldr r3, [pc, #572] ; (80025d8 ) 800239a: 685b ldr r3, [r3, #4] 800239c: f003 030c and.w r3, r3, #12 80023a0: 2b08 cmp r3, #8 80023a2: d112 bne.n 80023ca 80023a4: 4b8c ldr r3, [pc, #560] ; (80025d8 ) 80023a6: 685b ldr r3, [r3, #4] 80023a8: f403 3380 and.w r3, r3, #65536 ; 0x10000 80023ac: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 80023b0: d10b bne.n 80023ca { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 80023b2: 4b89 ldr r3, [pc, #548] ; (80025d8 ) 80023b4: 681b ldr r3, [r3, #0] 80023b6: f403 3300 and.w r3, r3, #131072 ; 0x20000 80023ba: 2b00 cmp r3, #0 80023bc: d06c beq.n 8002498 80023be: 687b ldr r3, [r7, #4] 80023c0: 685b ldr r3, [r3, #4] 80023c2: 2b00 cmp r3, #0 80023c4: d168 bne.n 8002498 { return HAL_ERROR; 80023c6: 2301 movs r3, #1 80023c8: e246 b.n 8002858 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 80023ca: 687b ldr r3, [r7, #4] 80023cc: 685b ldr r3, [r3, #4] 80023ce: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 80023d2: d106 bne.n 80023e2 80023d4: 4b80 ldr r3, [pc, #512] ; (80025d8 ) 80023d6: 681b ldr r3, [r3, #0] 80023d8: 4a7f ldr r2, [pc, #508] ; (80025d8 ) 80023da: f443 3380 orr.w r3, r3, #65536 ; 0x10000 80023de: 6013 str r3, [r2, #0] 80023e0: e02e b.n 8002440 80023e2: 687b ldr r3, [r7, #4] 80023e4: 685b ldr r3, [r3, #4] 80023e6: 2b00 cmp r3, #0 80023e8: d10c bne.n 8002404 80023ea: 4b7b ldr r3, [pc, #492] ; (80025d8 ) 80023ec: 681b ldr r3, [r3, #0] 80023ee: 4a7a ldr r2, [pc, #488] ; (80025d8 ) 80023f0: f423 3380 bic.w r3, r3, #65536 ; 0x10000 80023f4: 6013 str r3, [r2, #0] 80023f6: 4b78 ldr r3, [pc, #480] ; (80025d8 ) 80023f8: 681b ldr r3, [r3, #0] 80023fa: 4a77 ldr r2, [pc, #476] ; (80025d8 ) 80023fc: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8002400: 6013 str r3, [r2, #0] 8002402: e01d b.n 8002440 8002404: 687b ldr r3, [r7, #4] 8002406: 685b ldr r3, [r3, #4] 8002408: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 800240c: d10c bne.n 8002428 800240e: 4b72 ldr r3, [pc, #456] ; (80025d8 ) 8002410: 681b ldr r3, [r3, #0] 8002412: 4a71 ldr r2, [pc, #452] ; (80025d8 ) 8002414: f443 2380 orr.w r3, r3, #262144 ; 0x40000 8002418: 6013 str r3, [r2, #0] 800241a: 4b6f ldr r3, [pc, #444] ; (80025d8 ) 800241c: 681b ldr r3, [r3, #0] 800241e: 4a6e ldr r2, [pc, #440] ; (80025d8 ) 8002420: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8002424: 6013 str r3, [r2, #0] 8002426: e00b b.n 8002440 8002428: 4b6b ldr r3, [pc, #428] ; (80025d8 ) 800242a: 681b ldr r3, [r3, #0] 800242c: 4a6a ldr r2, [pc, #424] ; (80025d8 ) 800242e: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8002432: 6013 str r3, [r2, #0] 8002434: 4b68 ldr r3, [pc, #416] ; (80025d8 ) 8002436: 681b ldr r3, [r3, #0] 8002438: 4a67 ldr r2, [pc, #412] ; (80025d8 ) 800243a: f423 2380 bic.w r3, r3, #262144 ; 0x40000 800243e: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8002440: 687b ldr r3, [r7, #4] 8002442: 685b ldr r3, [r3, #4] 8002444: 2b00 cmp r3, #0 8002446: d013 beq.n 8002470 { /* Get Start Tick */ tickstart = HAL_GetTick(); 8002448: f7fe fdd8 bl 8000ffc 800244c: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 800244e: e008 b.n 8002462 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8002450: f7fe fdd4 bl 8000ffc 8002454: 4602 mov r2, r0 8002456: 693b ldr r3, [r7, #16] 8002458: 1ad3 subs r3, r2, r3 800245a: 2b64 cmp r3, #100 ; 0x64 800245c: d901 bls.n 8002462 { return HAL_TIMEOUT; 800245e: 2303 movs r3, #3 8002460: e1fa b.n 8002858 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8002462: 4b5d ldr r3, [pc, #372] ; (80025d8 ) 8002464: 681b ldr r3, [r3, #0] 8002466: f403 3300 and.w r3, r3, #131072 ; 0x20000 800246a: 2b00 cmp r3, #0 800246c: d0f0 beq.n 8002450 800246e: e014 b.n 800249a } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8002470: f7fe fdc4 bl 8000ffc 8002474: 6138 str r0, [r7, #16] /* Wait till HSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8002476: e008 b.n 800248a { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8002478: f7fe fdc0 bl 8000ffc 800247c: 4602 mov r2, r0 800247e: 693b ldr r3, [r7, #16] 8002480: 1ad3 subs r3, r2, r3 8002482: 2b64 cmp r3, #100 ; 0x64 8002484: d901 bls.n 800248a { return HAL_TIMEOUT; 8002486: 2303 movs r3, #3 8002488: e1e6 b.n 8002858 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 800248a: 4b53 ldr r3, [pc, #332] ; (80025d8 ) 800248c: 681b ldr r3, [r3, #0] 800248e: f403 3300 and.w r3, r3, #131072 ; 0x20000 8002492: 2b00 cmp r3, #0 8002494: d1f0 bne.n 8002478 8002496: e000 b.n 800249a if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8002498: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 800249a: 687b ldr r3, [r7, #4] 800249c: 681b ldr r3, [r3, #0] 800249e: f003 0302 and.w r3, r3, #2 80024a2: 2b00 cmp r3, #0 80024a4: d063 beq.n 800256e /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 80024a6: 4b4c ldr r3, [pc, #304] ; (80025d8 ) 80024a8: 685b ldr r3, [r3, #4] 80024aa: f003 030c and.w r3, r3, #12 80024ae: 2b00 cmp r3, #0 80024b0: d00b beq.n 80024ca || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2))) 80024b2: 4b49 ldr r3, [pc, #292] ; (80025d8 ) 80024b4: 685b ldr r3, [r3, #4] 80024b6: f003 030c and.w r3, r3, #12 80024ba: 2b08 cmp r3, #8 80024bc: d11c bne.n 80024f8 80024be: 4b46 ldr r3, [pc, #280] ; (80025d8 ) 80024c0: 685b ldr r3, [r3, #4] 80024c2: f403 3380 and.w r3, r3, #65536 ; 0x10000 80024c6: 2b00 cmp r3, #0 80024c8: d116 bne.n 80024f8 { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 80024ca: 4b43 ldr r3, [pc, #268] ; (80025d8 ) 80024cc: 681b ldr r3, [r3, #0] 80024ce: f003 0302 and.w r3, r3, #2 80024d2: 2b00 cmp r3, #0 80024d4: d005 beq.n 80024e2 80024d6: 687b ldr r3, [r7, #4] 80024d8: 691b ldr r3, [r3, #16] 80024da: 2b01 cmp r3, #1 80024dc: d001 beq.n 80024e2 { return HAL_ERROR; 80024de: 2301 movs r3, #1 80024e0: e1ba b.n 8002858 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 80024e2: 4b3d ldr r3, [pc, #244] ; (80025d8 ) 80024e4: 681b ldr r3, [r3, #0] 80024e6: f023 02f8 bic.w r2, r3, #248 ; 0xf8 80024ea: 687b ldr r3, [r7, #4] 80024ec: 695b ldr r3, [r3, #20] 80024ee: 00db lsls r3, r3, #3 80024f0: 4939 ldr r1, [pc, #228] ; (80025d8 ) 80024f2: 4313 orrs r3, r2 80024f4: 600b str r3, [r1, #0] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 80024f6: e03a b.n 800256e } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 80024f8: 687b ldr r3, [r7, #4] 80024fa: 691b ldr r3, [r3, #16] 80024fc: 2b00 cmp r3, #0 80024fe: d020 beq.n 8002542 { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 8002500: 4b36 ldr r3, [pc, #216] ; (80025dc ) 8002502: 2201 movs r2, #1 8002504: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8002506: f7fe fd79 bl 8000ffc 800250a: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 800250c: e008 b.n 8002520 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800250e: f7fe fd75 bl 8000ffc 8002512: 4602 mov r2, r0 8002514: 693b ldr r3, [r7, #16] 8002516: 1ad3 subs r3, r2, r3 8002518: 2b02 cmp r3, #2 800251a: d901 bls.n 8002520 { return HAL_TIMEOUT; 800251c: 2303 movs r3, #3 800251e: e19b b.n 8002858 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8002520: 4b2d ldr r3, [pc, #180] ; (80025d8 ) 8002522: 681b ldr r3, [r3, #0] 8002524: f003 0302 and.w r3, r3, #2 8002528: 2b00 cmp r3, #0 800252a: d0f0 beq.n 800250e } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800252c: 4b2a ldr r3, [pc, #168] ; (80025d8 ) 800252e: 681b ldr r3, [r3, #0] 8002530: f023 02f8 bic.w r2, r3, #248 ; 0xf8 8002534: 687b ldr r3, [r7, #4] 8002536: 695b ldr r3, [r3, #20] 8002538: 00db lsls r3, r3, #3 800253a: 4927 ldr r1, [pc, #156] ; (80025d8 ) 800253c: 4313 orrs r3, r2 800253e: 600b str r3, [r1, #0] 8002540: e015 b.n 800256e } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8002542: 4b26 ldr r3, [pc, #152] ; (80025dc ) 8002544: 2200 movs r2, #0 8002546: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8002548: f7fe fd58 bl 8000ffc 800254c: 6138 str r0, [r7, #16] /* Wait till HSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 800254e: e008 b.n 8002562 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8002550: f7fe fd54 bl 8000ffc 8002554: 4602 mov r2, r0 8002556: 693b ldr r3, [r7, #16] 8002558: 1ad3 subs r3, r2, r3 800255a: 2b02 cmp r3, #2 800255c: d901 bls.n 8002562 { return HAL_TIMEOUT; 800255e: 2303 movs r3, #3 8002560: e17a b.n 8002858 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8002562: 4b1d ldr r3, [pc, #116] ; (80025d8 ) 8002564: 681b ldr r3, [r3, #0] 8002566: f003 0302 and.w r3, r3, #2 800256a: 2b00 cmp r3, #0 800256c: d1f0 bne.n 8002550 } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 800256e: 687b ldr r3, [r7, #4] 8002570: 681b ldr r3, [r3, #0] 8002572: f003 0308 and.w r3, r3, #8 8002576: 2b00 cmp r3, #0 8002578: d03a beq.n 80025f0 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 800257a: 687b ldr r3, [r7, #4] 800257c: 699b ldr r3, [r3, #24] 800257e: 2b00 cmp r3, #0 8002580: d019 beq.n 80025b6 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8002582: 4b17 ldr r3, [pc, #92] ; (80025e0 ) 8002584: 2201 movs r2, #1 8002586: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8002588: f7fe fd38 bl 8000ffc 800258c: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 800258e: e008 b.n 80025a2 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8002590: f7fe fd34 bl 8000ffc 8002594: 4602 mov r2, r0 8002596: 693b ldr r3, [r7, #16] 8002598: 1ad3 subs r3, r2, r3 800259a: 2b02 cmp r3, #2 800259c: d901 bls.n 80025a2 { return HAL_TIMEOUT; 800259e: 2303 movs r3, #3 80025a0: e15a b.n 8002858 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 80025a2: 4b0d ldr r3, [pc, #52] ; (80025d8 ) 80025a4: 6a5b ldr r3, [r3, #36] ; 0x24 80025a6: f003 0302 and.w r3, r3, #2 80025aa: 2b00 cmp r3, #0 80025ac: d0f0 beq.n 8002590 } } /* To have a fully stabilized clock in the specified range, a software delay of 1ms should be added.*/ RCC_Delay(1); 80025ae: 2001 movs r0, #1 80025b0: f000 fad6 bl 8002b60 80025b4: e01c b.n 80025f0 } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 80025b6: 4b0a ldr r3, [pc, #40] ; (80025e0 ) 80025b8: 2200 movs r2, #0 80025ba: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80025bc: f7fe fd1e bl 8000ffc 80025c0: 6138 str r0, [r7, #16] /* Wait till LSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 80025c2: e00f b.n 80025e4 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 80025c4: f7fe fd1a bl 8000ffc 80025c8: 4602 mov r2, r0 80025ca: 693b ldr r3, [r7, #16] 80025cc: 1ad3 subs r3, r2, r3 80025ce: 2b02 cmp r3, #2 80025d0: d908 bls.n 80025e4 { return HAL_TIMEOUT; 80025d2: 2303 movs r3, #3 80025d4: e140 b.n 8002858 80025d6: bf00 nop 80025d8: 40021000 .word 0x40021000 80025dc: 42420000 .word 0x42420000 80025e0: 42420480 .word 0x42420480 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 80025e4: 4b9e ldr r3, [pc, #632] ; (8002860 ) 80025e6: 6a5b ldr r3, [r3, #36] ; 0x24 80025e8: f003 0302 and.w r3, r3, #2 80025ec: 2b00 cmp r3, #0 80025ee: d1e9 bne.n 80025c4 } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 80025f0: 687b ldr r3, [r7, #4] 80025f2: 681b ldr r3, [r3, #0] 80025f4: f003 0304 and.w r3, r3, #4 80025f8: 2b00 cmp r3, #0 80025fa: f000 80a6 beq.w 800274a { FlagStatus pwrclkchanged = RESET; 80025fe: 2300 movs r3, #0 8002600: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 8002602: 4b97 ldr r3, [pc, #604] ; (8002860 ) 8002604: 69db ldr r3, [r3, #28] 8002606: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 800260a: 2b00 cmp r3, #0 800260c: d10d bne.n 800262a { __HAL_RCC_PWR_CLK_ENABLE(); 800260e: 4b94 ldr r3, [pc, #592] ; (8002860 ) 8002610: 69db ldr r3, [r3, #28] 8002612: 4a93 ldr r2, [pc, #588] ; (8002860 ) 8002614: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8002618: 61d3 str r3, [r2, #28] 800261a: 4b91 ldr r3, [pc, #580] ; (8002860 ) 800261c: 69db ldr r3, [r3, #28] 800261e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8002622: 60bb str r3, [r7, #8] 8002624: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 8002626: 2301 movs r3, #1 8002628: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 800262a: 4b8e ldr r3, [pc, #568] ; (8002864 ) 800262c: 681b ldr r3, [r3, #0] 800262e: f403 7380 and.w r3, r3, #256 ; 0x100 8002632: 2b00 cmp r3, #0 8002634: d118 bne.n 8002668 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8002636: 4b8b ldr r3, [pc, #556] ; (8002864 ) 8002638: 681b ldr r3, [r3, #0] 800263a: 4a8a ldr r2, [pc, #552] ; (8002864 ) 800263c: f443 7380 orr.w r3, r3, #256 ; 0x100 8002640: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8002642: f7fe fcdb bl 8000ffc 8002646: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8002648: e008 b.n 800265c { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 800264a: f7fe fcd7 bl 8000ffc 800264e: 4602 mov r2, r0 8002650: 693b ldr r3, [r7, #16] 8002652: 1ad3 subs r3, r2, r3 8002654: 2b64 cmp r3, #100 ; 0x64 8002656: d901 bls.n 800265c { return HAL_TIMEOUT; 8002658: 2303 movs r3, #3 800265a: e0fd b.n 8002858 while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 800265c: 4b81 ldr r3, [pc, #516] ; (8002864 ) 800265e: 681b ldr r3, [r3, #0] 8002660: f403 7380 and.w r3, r3, #256 ; 0x100 8002664: 2b00 cmp r3, #0 8002666: d0f0 beq.n 800264a } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8002668: 687b ldr r3, [r7, #4] 800266a: 68db ldr r3, [r3, #12] 800266c: 2b01 cmp r3, #1 800266e: d106 bne.n 800267e 8002670: 4b7b ldr r3, [pc, #492] ; (8002860 ) 8002672: 6a1b ldr r3, [r3, #32] 8002674: 4a7a ldr r2, [pc, #488] ; (8002860 ) 8002676: f043 0301 orr.w r3, r3, #1 800267a: 6213 str r3, [r2, #32] 800267c: e02d b.n 80026da 800267e: 687b ldr r3, [r7, #4] 8002680: 68db ldr r3, [r3, #12] 8002682: 2b00 cmp r3, #0 8002684: d10c bne.n 80026a0 8002686: 4b76 ldr r3, [pc, #472] ; (8002860 ) 8002688: 6a1b ldr r3, [r3, #32] 800268a: 4a75 ldr r2, [pc, #468] ; (8002860 ) 800268c: f023 0301 bic.w r3, r3, #1 8002690: 6213 str r3, [r2, #32] 8002692: 4b73 ldr r3, [pc, #460] ; (8002860 ) 8002694: 6a1b ldr r3, [r3, #32] 8002696: 4a72 ldr r2, [pc, #456] ; (8002860 ) 8002698: f023 0304 bic.w r3, r3, #4 800269c: 6213 str r3, [r2, #32] 800269e: e01c b.n 80026da 80026a0: 687b ldr r3, [r7, #4] 80026a2: 68db ldr r3, [r3, #12] 80026a4: 2b05 cmp r3, #5 80026a6: d10c bne.n 80026c2 80026a8: 4b6d ldr r3, [pc, #436] ; (8002860 ) 80026aa: 6a1b ldr r3, [r3, #32] 80026ac: 4a6c ldr r2, [pc, #432] ; (8002860 ) 80026ae: f043 0304 orr.w r3, r3, #4 80026b2: 6213 str r3, [r2, #32] 80026b4: 4b6a ldr r3, [pc, #424] ; (8002860 ) 80026b6: 6a1b ldr r3, [r3, #32] 80026b8: 4a69 ldr r2, [pc, #420] ; (8002860 ) 80026ba: f043 0301 orr.w r3, r3, #1 80026be: 6213 str r3, [r2, #32] 80026c0: e00b b.n 80026da 80026c2: 4b67 ldr r3, [pc, #412] ; (8002860 ) 80026c4: 6a1b ldr r3, [r3, #32] 80026c6: 4a66 ldr r2, [pc, #408] ; (8002860 ) 80026c8: f023 0301 bic.w r3, r3, #1 80026cc: 6213 str r3, [r2, #32] 80026ce: 4b64 ldr r3, [pc, #400] ; (8002860 ) 80026d0: 6a1b ldr r3, [r3, #32] 80026d2: 4a63 ldr r2, [pc, #396] ; (8002860 ) 80026d4: f023 0304 bic.w r3, r3, #4 80026d8: 6213 str r3, [r2, #32] /* Check the LSE State */ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 80026da: 687b ldr r3, [r7, #4] 80026dc: 68db ldr r3, [r3, #12] 80026de: 2b00 cmp r3, #0 80026e0: d015 beq.n 800270e { /* Get Start Tick */ tickstart = HAL_GetTick(); 80026e2: f7fe fc8b bl 8000ffc 80026e6: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80026e8: e00a b.n 8002700 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 80026ea: f7fe fc87 bl 8000ffc 80026ee: 4602 mov r2, r0 80026f0: 693b ldr r3, [r7, #16] 80026f2: 1ad3 subs r3, r2, r3 80026f4: f241 3288 movw r2, #5000 ; 0x1388 80026f8: 4293 cmp r3, r2 80026fa: d901 bls.n 8002700 { return HAL_TIMEOUT; 80026fc: 2303 movs r3, #3 80026fe: e0ab b.n 8002858 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8002700: 4b57 ldr r3, [pc, #348] ; (8002860 ) 8002702: 6a1b ldr r3, [r3, #32] 8002704: f003 0302 and.w r3, r3, #2 8002708: 2b00 cmp r3, #0 800270a: d0ee beq.n 80026ea 800270c: e014 b.n 8002738 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 800270e: f7fe fc75 bl 8000ffc 8002712: 6138 str r0, [r7, #16] /* Wait till LSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8002714: e00a b.n 800272c { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8002716: f7fe fc71 bl 8000ffc 800271a: 4602 mov r2, r0 800271c: 693b ldr r3, [r7, #16] 800271e: 1ad3 subs r3, r2, r3 8002720: f241 3288 movw r2, #5000 ; 0x1388 8002724: 4293 cmp r3, r2 8002726: d901 bls.n 800272c { return HAL_TIMEOUT; 8002728: 2303 movs r3, #3 800272a: e095 b.n 8002858 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 800272c: 4b4c ldr r3, [pc, #304] ; (8002860 ) 800272e: 6a1b ldr r3, [r3, #32] 8002730: f003 0302 and.w r3, r3, #2 8002734: 2b00 cmp r3, #0 8002736: d1ee bne.n 8002716 } } } /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 8002738: 7dfb ldrb r3, [r7, #23] 800273a: 2b01 cmp r3, #1 800273c: d105 bne.n 800274a { __HAL_RCC_PWR_CLK_DISABLE(); 800273e: 4b48 ldr r3, [pc, #288] ; (8002860 ) 8002740: 69db ldr r3, [r3, #28] 8002742: 4a47 ldr r2, [pc, #284] ; (8002860 ) 8002744: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 8002748: 61d3 str r3, [r2, #28] #endif /* RCC_CR_PLL2ON */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 800274a: 687b ldr r3, [r7, #4] 800274c: 69db ldr r3, [r3, #28] 800274e: 2b00 cmp r3, #0 8002750: f000 8081 beq.w 8002856 { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 8002754: 4b42 ldr r3, [pc, #264] ; (8002860 ) 8002756: 685b ldr r3, [r3, #4] 8002758: f003 030c and.w r3, r3, #12 800275c: 2b08 cmp r3, #8 800275e: d061 beq.n 8002824 { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 8002760: 687b ldr r3, [r7, #4] 8002762: 69db ldr r3, [r3, #28] 8002764: 2b02 cmp r3, #2 8002766: d146 bne.n 80027f6 /* Check the parameters */ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8002768: 4b3f ldr r3, [pc, #252] ; (8002868 ) 800276a: 2200 movs r2, #0 800276c: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800276e: f7fe fc45 bl 8000ffc 8002772: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8002774: e008 b.n 8002788 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8002776: f7fe fc41 bl 8000ffc 800277a: 4602 mov r2, r0 800277c: 693b ldr r3, [r7, #16] 800277e: 1ad3 subs r3, r2, r3 8002780: 2b02 cmp r3, #2 8002782: d901 bls.n 8002788 { return HAL_TIMEOUT; 8002784: 2303 movs r3, #3 8002786: e067 b.n 8002858 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8002788: 4b35 ldr r3, [pc, #212] ; (8002860 ) 800278a: 681b ldr r3, [r3, #0] 800278c: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8002790: 2b00 cmp r3, #0 8002792: d1f0 bne.n 8002776 } } /* Configure the HSE prediv factor --------------------------------*/ /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */ if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE) 8002794: 687b ldr r3, [r7, #4] 8002796: 6a1b ldr r3, [r3, #32] 8002798: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 800279c: d108 bne.n 80027b0 /* Set PREDIV1 source */ SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source); #endif /* RCC_CFGR2_PREDIV1SRC */ /* Set PREDIV1 Value */ __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); 800279e: 4b30 ldr r3, [pc, #192] ; (8002860 ) 80027a0: 6adb ldr r3, [r3, #44] ; 0x2c 80027a2: f023 020f bic.w r2, r3, #15 80027a6: 687b ldr r3, [r7, #4] 80027a8: 689b ldr r3, [r3, #8] 80027aa: 492d ldr r1, [pc, #180] ; (8002860 ) 80027ac: 4313 orrs r3, r2 80027ae: 62cb str r3, [r1, #44] ; 0x2c } /* Configure the main PLL clock source and multiplication factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 80027b0: 4b2b ldr r3, [pc, #172] ; (8002860 ) 80027b2: 685b ldr r3, [r3, #4] 80027b4: f423 1274 bic.w r2, r3, #3997696 ; 0x3d0000 80027b8: 687b ldr r3, [r7, #4] 80027ba: 6a19 ldr r1, [r3, #32] 80027bc: 687b ldr r3, [r7, #4] 80027be: 6a5b ldr r3, [r3, #36] ; 0x24 80027c0: 430b orrs r3, r1 80027c2: 4927 ldr r1, [pc, #156] ; (8002860 ) 80027c4: 4313 orrs r3, r2 80027c6: 604b str r3, [r1, #4] RCC_OscInitStruct->PLL.PLLMUL); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 80027c8: 4b27 ldr r3, [pc, #156] ; (8002868 ) 80027ca: 2201 movs r2, #1 80027cc: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80027ce: f7fe fc15 bl 8000ffc 80027d2: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 80027d4: e008 b.n 80027e8 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80027d6: f7fe fc11 bl 8000ffc 80027da: 4602 mov r2, r0 80027dc: 693b ldr r3, [r7, #16] 80027de: 1ad3 subs r3, r2, r3 80027e0: 2b02 cmp r3, #2 80027e2: d901 bls.n 80027e8 { return HAL_TIMEOUT; 80027e4: 2303 movs r3, #3 80027e6: e037 b.n 8002858 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 80027e8: 4b1d ldr r3, [pc, #116] ; (8002860 ) 80027ea: 681b ldr r3, [r3, #0] 80027ec: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 80027f0: 2b00 cmp r3, #0 80027f2: d0f0 beq.n 80027d6 80027f4: e02f b.n 8002856 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 80027f6: 4b1c ldr r3, [pc, #112] ; (8002868 ) 80027f8: 2200 movs r2, #0 80027fa: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80027fc: f7fe fbfe bl 8000ffc 8002800: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8002802: e008 b.n 8002816 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8002804: f7fe fbfa bl 8000ffc 8002808: 4602 mov r2, r0 800280a: 693b ldr r3, [r7, #16] 800280c: 1ad3 subs r3, r2, r3 800280e: 2b02 cmp r3, #2 8002810: d901 bls.n 8002816 { return HAL_TIMEOUT; 8002812: 2303 movs r3, #3 8002814: e020 b.n 8002858 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8002816: 4b12 ldr r3, [pc, #72] ; (8002860 ) 8002818: 681b ldr r3, [r3, #0] 800281a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 800281e: 2b00 cmp r3, #0 8002820: d1f0 bne.n 8002804 8002822: e018 b.n 8002856 } } else { /* Check if there is a request to disable the PLL used as System clock source */ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 8002824: 687b ldr r3, [r7, #4] 8002826: 69db ldr r3, [r3, #28] 8002828: 2b01 cmp r3, #1 800282a: d101 bne.n 8002830 { return HAL_ERROR; 800282c: 2301 movs r3, #1 800282e: e013 b.n 8002858 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->CFGR; 8002830: 4b0b ldr r3, [pc, #44] ; (8002860 ) 8002832: 685b ldr r3, [r3, #4] 8002834: 60fb str r3, [r7, #12] if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8002836: 68fb ldr r3, [r7, #12] 8002838: f403 3280 and.w r2, r3, #65536 ; 0x10000 800283c: 687b ldr r3, [r7, #4] 800283e: 6a1b ldr r3, [r3, #32] 8002840: 429a cmp r2, r3 8002842: d106 bne.n 8002852 (READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL)) 8002844: 68fb ldr r3, [r7, #12] 8002846: f403 1270 and.w r2, r3, #3932160 ; 0x3c0000 800284a: 687b ldr r3, [r7, #4] 800284c: 6a5b ldr r3, [r3, #36] ; 0x24 if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 800284e: 429a cmp r2, r3 8002850: d001 beq.n 8002856 { return HAL_ERROR; 8002852: 2301 movs r3, #1 8002854: e000 b.n 8002858 } } } } return HAL_OK; 8002856: 2300 movs r3, #0 } 8002858: 4618 mov r0, r3 800285a: 3718 adds r7, #24 800285c: 46bd mov sp, r7 800285e: bd80 pop {r7, pc} 8002860: 40021000 .word 0x40021000 8002864: 40007000 .word 0x40007000 8002868: 42420060 .word 0x42420060 0800286c : * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 800286c: b580 push {r7, lr} 800286e: b084 sub sp, #16 8002870: af00 add r7, sp, #0 8002872: 6078 str r0, [r7, #4] 8002874: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 8002876: 687b ldr r3, [r7, #4] 8002878: 2b00 cmp r3, #0 800287a: d101 bne.n 8002880 { return HAL_ERROR; 800287c: 2301 movs r3, #1 800287e: e0a0 b.n 80029c2 } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8002880: 687b ldr r3, [r7, #4] 8002882: 681b ldr r3, [r3, #0] 8002884: f003 0302 and.w r3, r3, #2 8002888: 2b00 cmp r3, #0 800288a: d020 beq.n 80028ce { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 800288c: 687b ldr r3, [r7, #4] 800288e: 681b ldr r3, [r3, #0] 8002890: f003 0304 and.w r3, r3, #4 8002894: 2b00 cmp r3, #0 8002896: d005 beq.n 80028a4 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 8002898: 4b4c ldr r3, [pc, #304] ; (80029cc ) 800289a: 685b ldr r3, [r3, #4] 800289c: 4a4b ldr r2, [pc, #300] ; (80029cc ) 800289e: f443 63e0 orr.w r3, r3, #1792 ; 0x700 80028a2: 6053 str r3, [r2, #4] } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 80028a4: 687b ldr r3, [r7, #4] 80028a6: 681b ldr r3, [r3, #0] 80028a8: f003 0308 and.w r3, r3, #8 80028ac: 2b00 cmp r3, #0 80028ae: d005 beq.n 80028bc { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); 80028b0: 4b46 ldr r3, [pc, #280] ; (80029cc ) 80028b2: 685b ldr r3, [r3, #4] 80028b4: 4a45 ldr r2, [pc, #276] ; (80029cc ) 80028b6: f443 5360 orr.w r3, r3, #14336 ; 0x3800 80028ba: 6053 str r3, [r2, #4] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 80028bc: 4b43 ldr r3, [pc, #268] ; (80029cc ) 80028be: 685b ldr r3, [r3, #4] 80028c0: f023 02f0 bic.w r2, r3, #240 ; 0xf0 80028c4: 687b ldr r3, [r7, #4] 80028c6: 689b ldr r3, [r3, #8] 80028c8: 4940 ldr r1, [pc, #256] ; (80029cc ) 80028ca: 4313 orrs r3, r2 80028cc: 604b str r3, [r1, #4] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 80028ce: 687b ldr r3, [r7, #4] 80028d0: 681b ldr r3, [r3, #0] 80028d2: f003 0301 and.w r3, r3, #1 80028d6: 2b00 cmp r3, #0 80028d8: d040 beq.n 800295c { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 80028da: 687b ldr r3, [r7, #4] 80028dc: 685b ldr r3, [r3, #4] 80028de: 2b01 cmp r3, #1 80028e0: d107 bne.n 80028f2 { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 80028e2: 4b3a ldr r3, [pc, #232] ; (80029cc ) 80028e4: 681b ldr r3, [r3, #0] 80028e6: f403 3300 and.w r3, r3, #131072 ; 0x20000 80028ea: 2b00 cmp r3, #0 80028ec: d115 bne.n 800291a { return HAL_ERROR; 80028ee: 2301 movs r3, #1 80028f0: e067 b.n 80029c2 } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 80028f2: 687b ldr r3, [r7, #4] 80028f4: 685b ldr r3, [r3, #4] 80028f6: 2b02 cmp r3, #2 80028f8: d107 bne.n 800290a { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 80028fa: 4b34 ldr r3, [pc, #208] ; (80029cc ) 80028fc: 681b ldr r3, [r3, #0] 80028fe: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8002902: 2b00 cmp r3, #0 8002904: d109 bne.n 800291a { return HAL_ERROR; 8002906: 2301 movs r3, #1 8002908: e05b b.n 80029c2 } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 800290a: 4b30 ldr r3, [pc, #192] ; (80029cc ) 800290c: 681b ldr r3, [r3, #0] 800290e: f003 0302 and.w r3, r3, #2 8002912: 2b00 cmp r3, #0 8002914: d101 bne.n 800291a { return HAL_ERROR; 8002916: 2301 movs r3, #1 8002918: e053 b.n 80029c2 } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 800291a: 4b2c ldr r3, [pc, #176] ; (80029cc ) 800291c: 685b ldr r3, [r3, #4] 800291e: f023 0203 bic.w r2, r3, #3 8002922: 687b ldr r3, [r7, #4] 8002924: 685b ldr r3, [r3, #4] 8002926: 4929 ldr r1, [pc, #164] ; (80029cc ) 8002928: 4313 orrs r3, r2 800292a: 604b str r3, [r1, #4] /* Get Start Tick */ tickstart = HAL_GetTick(); 800292c: f7fe fb66 bl 8000ffc 8002930: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8002932: e00a b.n 800294a { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8002934: f7fe fb62 bl 8000ffc 8002938: 4602 mov r2, r0 800293a: 68fb ldr r3, [r7, #12] 800293c: 1ad3 subs r3, r2, r3 800293e: f241 3288 movw r2, #5000 ; 0x1388 8002942: 4293 cmp r3, r2 8002944: d901 bls.n 800294a { return HAL_TIMEOUT; 8002946: 2303 movs r3, #3 8002948: e03b b.n 80029c2 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 800294a: 4b20 ldr r3, [pc, #128] ; (80029cc ) 800294c: 685b ldr r3, [r3, #4] 800294e: f003 020c and.w r2, r3, #12 8002952: 687b ldr r3, [r7, #4] 8002954: 685b ldr r3, [r3, #4] 8002956: 009b lsls r3, r3, #2 8002958: 429a cmp r2, r3 800295a: d1eb bne.n 8002934 } } #endif /* FLASH_ACR_LATENCY */ /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 800295c: 687b ldr r3, [r7, #4] 800295e: 681b ldr r3, [r3, #0] 8002960: f003 0304 and.w r3, r3, #4 8002964: 2b00 cmp r3, #0 8002966: d008 beq.n 800297a { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 8002968: 4b18 ldr r3, [pc, #96] ; (80029cc ) 800296a: 685b ldr r3, [r3, #4] 800296c: f423 62e0 bic.w r2, r3, #1792 ; 0x700 8002970: 687b ldr r3, [r7, #4] 8002972: 68db ldr r3, [r3, #12] 8002974: 4915 ldr r1, [pc, #84] ; (80029cc ) 8002976: 4313 orrs r3, r2 8002978: 604b str r3, [r1, #4] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 800297a: 687b ldr r3, [r7, #4] 800297c: 681b ldr r3, [r3, #0] 800297e: f003 0308 and.w r3, r3, #8 8002982: 2b00 cmp r3, #0 8002984: d009 beq.n 800299a { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); 8002986: 4b11 ldr r3, [pc, #68] ; (80029cc ) 8002988: 685b ldr r3, [r3, #4] 800298a: f423 5260 bic.w r2, r3, #14336 ; 0x3800 800298e: 687b ldr r3, [r7, #4] 8002990: 691b ldr r3, [r3, #16] 8002992: 00db lsls r3, r3, #3 8002994: 490d ldr r1, [pc, #52] ; (80029cc ) 8002996: 4313 orrs r3, r2 8002998: 604b str r3, [r1, #4] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; 800299a: f000 f81f bl 80029dc 800299e: 4601 mov r1, r0 80029a0: 4b0a ldr r3, [pc, #40] ; (80029cc ) 80029a2: 685b ldr r3, [r3, #4] 80029a4: 091b lsrs r3, r3, #4 80029a6: f003 030f and.w r3, r3, #15 80029aa: 4a09 ldr r2, [pc, #36] ; (80029d0 ) 80029ac: 5cd3 ldrb r3, [r2, r3] 80029ae: fa21 f303 lsr.w r3, r1, r3 80029b2: 4a08 ldr r2, [pc, #32] ; (80029d4 ) 80029b4: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick(uwTickPrio); 80029b6: 4b08 ldr r3, [pc, #32] ; (80029d8 ) 80029b8: 681b ldr r3, [r3, #0] 80029ba: 4618 mov r0, r3 80029bc: f001 fe96 bl 80046ec return HAL_OK; 80029c0: 2300 movs r3, #0 } 80029c2: 4618 mov r0, r3 80029c4: 3710 adds r7, #16 80029c6: 46bd mov sp, r7 80029c8: bd80 pop {r7, pc} 80029ca: bf00 nop 80029cc: 40021000 .word 0x40021000 80029d0: 0800742c .word 0x0800742c 80029d4: 20000008 .word 0x20000008 80029d8: 20000000 .word 0x20000000 080029dc : * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 80029dc: b490 push {r4, r7} 80029de: b08e sub sp, #56 ; 0x38 80029e0: af00 add r7, sp, #0 #if defined(RCC_CFGR2_PREDIV1SRC) const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13}; const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; #else const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; 80029e2: 4b2b ldr r3, [pc, #172] ; (8002a90 ) 80029e4: f107 0414 add.w r4, r7, #20 80029e8: cb0f ldmia r3, {r0, r1, r2, r3} 80029ea: e884 000f stmia.w r4, {r0, r1, r2, r3} #if defined(RCC_CFGR2_PREDIV1) const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; 80029ee: 4b29 ldr r3, [pc, #164] ; (8002a94 ) 80029f0: 1d3c adds r4, r7, #4 80029f2: cb0f ldmia r3, {r0, r1, r2, r3} 80029f4: e884 000f stmia.w r4, {r0, r1, r2, r3} #else const uint8_t aPredivFactorTable[2] = {1, 2}; #endif /*RCC_CFGR2_PREDIV1*/ #endif uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; 80029f8: 2300 movs r3, #0 80029fa: 62fb str r3, [r7, #44] ; 0x2c 80029fc: 2300 movs r3, #0 80029fe: 62bb str r3, [r7, #40] ; 0x28 8002a00: 2300 movs r3, #0 8002a02: 637b str r3, [r7, #52] ; 0x34 8002a04: 2300 movs r3, #0 8002a06: 627b str r3, [r7, #36] ; 0x24 uint32_t sysclockfreq = 0U; 8002a08: 2300 movs r3, #0 8002a0a: 633b str r3, [r7, #48] ; 0x30 #if defined(RCC_CFGR2_PREDIV1SRC) uint32_t prediv2 = 0U, pll2mul = 0U; #endif /*RCC_CFGR2_PREDIV1SRC*/ tmpreg = RCC->CFGR; 8002a0c: 4b22 ldr r3, [pc, #136] ; (8002a98 ) 8002a0e: 685b ldr r3, [r3, #4] 8002a10: 62fb str r3, [r7, #44] ; 0x2c /* Get SYSCLK source -------------------------------------------------------*/ switch (tmpreg & RCC_CFGR_SWS) 8002a12: 6afb ldr r3, [r7, #44] ; 0x2c 8002a14: f003 030c and.w r3, r3, #12 8002a18: 2b04 cmp r3, #4 8002a1a: d002 beq.n 8002a22 8002a1c: 2b08 cmp r3, #8 8002a1e: d003 beq.n 8002a28 8002a20: e02c b.n 8002a7c { case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ { sysclockfreq = HSE_VALUE; 8002a22: 4b1e ldr r3, [pc, #120] ; (8002a9c ) 8002a24: 633b str r3, [r7, #48] ; 0x30 break; 8002a26: e02c b.n 8002a82 } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ { pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; 8002a28: 6afb ldr r3, [r7, #44] ; 0x2c 8002a2a: 0c9b lsrs r3, r3, #18 8002a2c: f003 030f and.w r3, r3, #15 8002a30: f107 0238 add.w r2, r7, #56 ; 0x38 8002a34: 4413 add r3, r2 8002a36: f813 3c24 ldrb.w r3, [r3, #-36] 8002a3a: 627b str r3, [r7, #36] ; 0x24 if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) 8002a3c: 6afb ldr r3, [r7, #44] ; 0x2c 8002a3e: f403 3380 and.w r3, r3, #65536 ; 0x10000 8002a42: 2b00 cmp r3, #0 8002a44: d012 beq.n 8002a6c { #if defined(RCC_CFGR2_PREDIV1) prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; 8002a46: 4b14 ldr r3, [pc, #80] ; (8002a98 ) 8002a48: 6adb ldr r3, [r3, #44] ; 0x2c 8002a4a: f003 030f and.w r3, r3, #15 8002a4e: f107 0238 add.w r2, r7, #56 ; 0x38 8002a52: 4413 add r3, r2 8002a54: f813 3c34 ldrb.w r3, [r3, #-52] 8002a58: 62bb str r3, [r7, #40] ; 0x28 { pllclk = pllclk / 2; } #else /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */ pllclk = (uint32_t)((HSE_VALUE * pllmul) / prediv); 8002a5a: 6a7b ldr r3, [r7, #36] ; 0x24 8002a5c: 4a0f ldr r2, [pc, #60] ; (8002a9c ) 8002a5e: fb02 f203 mul.w r2, r2, r3 8002a62: 6abb ldr r3, [r7, #40] ; 0x28 8002a64: fbb2 f3f3 udiv r3, r2, r3 8002a68: 637b str r3, [r7, #52] ; 0x34 8002a6a: e004 b.n 8002a76 #endif /*RCC_CFGR2_PREDIV1SRC*/ } else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul); 8002a6c: 6a7b ldr r3, [r7, #36] ; 0x24 8002a6e: 4a0c ldr r2, [pc, #48] ; (8002aa0 ) 8002a70: fb02 f303 mul.w r3, r2, r3 8002a74: 637b str r3, [r7, #52] ; 0x34 } sysclockfreq = pllclk; 8002a76: 6b7b ldr r3, [r7, #52] ; 0x34 8002a78: 633b str r3, [r7, #48] ; 0x30 break; 8002a7a: e002 b.n 8002a82 } case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ default: /* HSI used as system clock */ { sysclockfreq = HSI_VALUE; 8002a7c: 4b07 ldr r3, [pc, #28] ; (8002a9c ) 8002a7e: 633b str r3, [r7, #48] ; 0x30 break; 8002a80: bf00 nop } } return sysclockfreq; 8002a82: 6b3b ldr r3, [r7, #48] ; 0x30 } 8002a84: 4618 mov r0, r3 8002a86: 3738 adds r7, #56 ; 0x38 8002a88: 46bd mov sp, r7 8002a8a: bc90 pop {r4, r7} 8002a8c: 4770 bx lr 8002a8e: bf00 nop 8002a90: 08007380 .word 0x08007380 8002a94: 08007390 .word 0x08007390 8002a98: 40021000 .word 0x40021000 8002a9c: 007a1200 .word 0x007a1200 8002aa0: 003d0900 .word 0x003d0900 08002aa4 : * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 8002aa4: b480 push {r7} 8002aa6: af00 add r7, sp, #0 return SystemCoreClock; 8002aa8: 4b02 ldr r3, [pc, #8] ; (8002ab4 ) 8002aaa: 681b ldr r3, [r3, #0] } 8002aac: 4618 mov r0, r3 8002aae: 46bd mov sp, r7 8002ab0: bc80 pop {r7} 8002ab2: 4770 bx lr 8002ab4: 20000008 .word 0x20000008 08002ab8 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 8002ab8: b580 push {r7, lr} 8002aba: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); 8002abc: f7ff fff2 bl 8002aa4 8002ac0: 4601 mov r1, r0 8002ac2: 4b05 ldr r3, [pc, #20] ; (8002ad8 ) 8002ac4: 685b ldr r3, [r3, #4] 8002ac6: 0a1b lsrs r3, r3, #8 8002ac8: f003 0307 and.w r3, r3, #7 8002acc: 4a03 ldr r2, [pc, #12] ; (8002adc ) 8002ace: 5cd3 ldrb r3, [r2, r3] 8002ad0: fa21 f303 lsr.w r3, r1, r3 } 8002ad4: 4618 mov r0, r3 8002ad6: bd80 pop {r7, pc} 8002ad8: 40021000 .word 0x40021000 8002adc: 0800743c .word 0x0800743c 08002ae0 : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 8002ae0: b580 push {r7, lr} 8002ae2: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); 8002ae4: f7ff ffde bl 8002aa4 8002ae8: 4601 mov r1, r0 8002aea: 4b05 ldr r3, [pc, #20] ; (8002b00 ) 8002aec: 685b ldr r3, [r3, #4] 8002aee: 0adb lsrs r3, r3, #11 8002af0: f003 0307 and.w r3, r3, #7 8002af4: 4a03 ldr r2, [pc, #12] ; (8002b04 ) 8002af6: 5cd3 ldrb r3, [r2, r3] 8002af8: fa21 f303 lsr.w r3, r1, r3 } 8002afc: 4618 mov r0, r3 8002afe: bd80 pop {r7, pc} 8002b00: 40021000 .word 0x40021000 8002b04: 0800743c .word 0x0800743c 08002b08 : * contains the current clock configuration. * @param pFLatency Pointer on the Flash Latency. * @retval None */ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) { 8002b08: b480 push {r7} 8002b0a: b083 sub sp, #12 8002b0c: af00 add r7, sp, #0 8002b0e: 6078 str r0, [r7, #4] 8002b10: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(RCC_ClkInitStruct != NULL); assert_param(pFLatency != NULL); /* Set all possible values for the Clock type parameter --------------------*/ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; 8002b12: 687b ldr r3, [r7, #4] 8002b14: 220f movs r2, #15 8002b16: 601a str r2, [r3, #0] /* Get the SYSCLK configuration --------------------------------------------*/ RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); 8002b18: 4b10 ldr r3, [pc, #64] ; (8002b5c ) 8002b1a: 685b ldr r3, [r3, #4] 8002b1c: f003 0203 and.w r2, r3, #3 8002b20: 687b ldr r3, [r7, #4] 8002b22: 605a str r2, [r3, #4] /* Get the HCLK configuration ----------------------------------------------*/ RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); 8002b24: 4b0d ldr r3, [pc, #52] ; (8002b5c ) 8002b26: 685b ldr r3, [r3, #4] 8002b28: f003 02f0 and.w r2, r3, #240 ; 0xf0 8002b2c: 687b ldr r3, [r7, #4] 8002b2e: 609a str r2, [r3, #8] /* Get the APB1 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); 8002b30: 4b0a ldr r3, [pc, #40] ; (8002b5c ) 8002b32: 685b ldr r3, [r3, #4] 8002b34: f403 62e0 and.w r2, r3, #1792 ; 0x700 8002b38: 687b ldr r3, [r7, #4] 8002b3a: 60da str r2, [r3, #12] /* Get the APB2 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3); 8002b3c: 4b07 ldr r3, [pc, #28] ; (8002b5c ) 8002b3e: 685b ldr r3, [r3, #4] 8002b40: 08db lsrs r3, r3, #3 8002b42: f403 62e0 and.w r2, r3, #1792 ; 0x700 8002b46: 687b ldr r3, [r7, #4] 8002b48: 611a str r2, [r3, #16] #if defined(FLASH_ACR_LATENCY) /* Get the Flash Wait State (Latency) configuration ------------------------*/ *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); #else /* For VALUE lines devices, only LATENCY_0 can be set*/ *pFLatency = (uint32_t)FLASH_LATENCY_0; 8002b4a: 683b ldr r3, [r7, #0] 8002b4c: 2200 movs r2, #0 8002b4e: 601a str r2, [r3, #0] #endif } 8002b50: bf00 nop 8002b52: 370c adds r7, #12 8002b54: 46bd mov sp, r7 8002b56: bc80 pop {r7} 8002b58: 4770 bx lr 8002b5a: bf00 nop 8002b5c: 40021000 .word 0x40021000 08002b60 : * @brief This function provides delay (in milliseconds) based on CPU cycles method. * @param mdelay: specifies the delay time length, in milliseconds. * @retval None */ static void RCC_Delay(uint32_t mdelay) { 8002b60: b480 push {r7} 8002b62: b085 sub sp, #20 8002b64: af00 add r7, sp, #0 8002b66: 6078 str r0, [r7, #4] __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U); 8002b68: 4b0a ldr r3, [pc, #40] ; (8002b94 ) 8002b6a: 681b ldr r3, [r3, #0] 8002b6c: 4a0a ldr r2, [pc, #40] ; (8002b98 ) 8002b6e: fba2 2303 umull r2, r3, r2, r3 8002b72: 0a5b lsrs r3, r3, #9 8002b74: 687a ldr r2, [r7, #4] 8002b76: fb02 f303 mul.w r3, r2, r3 8002b7a: 60fb str r3, [r7, #12] do { __NOP(); 8002b7c: bf00 nop } while (Delay --); 8002b7e: 68fb ldr r3, [r7, #12] 8002b80: 1e5a subs r2, r3, #1 8002b82: 60fa str r2, [r7, #12] 8002b84: 2b00 cmp r3, #0 8002b86: d1f9 bne.n 8002b7c } 8002b88: bf00 nop 8002b8a: 3714 adds r7, #20 8002b8c: 46bd mov sp, r7 8002b8e: bc80 pop {r7} 8002b90: 4770 bx lr 8002b92: bf00 nop 8002b94: 20000008 .word 0x20000008 8002b98: 10624dd3 .word 0x10624dd3 08002b9c : * manually disable it. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 8002b9c: b580 push {r7, lr} 8002b9e: b086 sub sp, #24 8002ba0: af00 add r7, sp, #0 8002ba2: 6078 str r0, [r7, #4] uint32_t tickstart = 0U, temp_reg = 0U; 8002ba4: 2300 movs r3, #0 8002ba6: 613b str r3, [r7, #16] 8002ba8: 2300 movs r3, #0 8002baa: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*------------------------------- RTC/LCD Configuration ------------------------*/ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 8002bac: 687b ldr r3, [r7, #4] 8002bae: 681b ldr r3, [r3, #0] 8002bb0: f003 0301 and.w r3, r3, #1 8002bb4: 2b00 cmp r3, #0 8002bb6: d07d beq.n 8002cb4 { /* check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); FlagStatus pwrclkchanged = RESET; 8002bb8: 2300 movs r3, #0 8002bba: 75fb strb r3, [r7, #23] /* As soon as function is called to change RTC clock source, activation of the power domain is done. */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 8002bbc: 4b47 ldr r3, [pc, #284] ; (8002cdc ) 8002bbe: 69db ldr r3, [r3, #28] 8002bc0: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8002bc4: 2b00 cmp r3, #0 8002bc6: d10d bne.n 8002be4 { __HAL_RCC_PWR_CLK_ENABLE(); 8002bc8: 4b44 ldr r3, [pc, #272] ; (8002cdc ) 8002bca: 69db ldr r3, [r3, #28] 8002bcc: 4a43 ldr r2, [pc, #268] ; (8002cdc ) 8002bce: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8002bd2: 61d3 str r3, [r2, #28] 8002bd4: 4b41 ldr r3, [pc, #260] ; (8002cdc ) 8002bd6: 69db ldr r3, [r3, #28] 8002bd8: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8002bdc: 60bb str r3, [r7, #8] 8002bde: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 8002be0: 2301 movs r3, #1 8002be2: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8002be4: 4b3e ldr r3, [pc, #248] ; (8002ce0 ) 8002be6: 681b ldr r3, [r3, #0] 8002be8: f403 7380 and.w r3, r3, #256 ; 0x100 8002bec: 2b00 cmp r3, #0 8002bee: d118 bne.n 8002c22 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8002bf0: 4b3b ldr r3, [pc, #236] ; (8002ce0 ) 8002bf2: 681b ldr r3, [r3, #0] 8002bf4: 4a3a ldr r2, [pc, #232] ; (8002ce0 ) 8002bf6: f443 7380 orr.w r3, r3, #256 ; 0x100 8002bfa: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8002bfc: f7fe f9fe bl 8000ffc 8002c00: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8002c02: e008 b.n 8002c16 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8002c04: f7fe f9fa bl 8000ffc 8002c08: 4602 mov r2, r0 8002c0a: 693b ldr r3, [r7, #16] 8002c0c: 1ad3 subs r3, r2, r3 8002c0e: 2b64 cmp r3, #100 ; 0x64 8002c10: d901 bls.n 8002c16 { return HAL_TIMEOUT; 8002c12: 2303 movs r3, #3 8002c14: e05e b.n 8002cd4 while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8002c16: 4b32 ldr r3, [pc, #200] ; (8002ce0 ) 8002c18: 681b ldr r3, [r3, #0] 8002c1a: f403 7380 and.w r3, r3, #256 ; 0x100 8002c1e: 2b00 cmp r3, #0 8002c20: d0f0 beq.n 8002c04 } } } /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); 8002c22: 4b2e ldr r3, [pc, #184] ; (8002cdc ) 8002c24: 6a1b ldr r3, [r3, #32] 8002c26: f403 7340 and.w r3, r3, #768 ; 0x300 8002c2a: 60fb str r3, [r7, #12] if ((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) 8002c2c: 68fb ldr r3, [r7, #12] 8002c2e: 2b00 cmp r3, #0 8002c30: d02e beq.n 8002c90 8002c32: 687b ldr r3, [r7, #4] 8002c34: 685b ldr r3, [r3, #4] 8002c36: f403 7340 and.w r3, r3, #768 ; 0x300 8002c3a: 68fa ldr r2, [r7, #12] 8002c3c: 429a cmp r2, r3 8002c3e: d027 beq.n 8002c90 { /* Store the content of BDCR register before the reset of Backup Domain */ temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 8002c40: 4b26 ldr r3, [pc, #152] ; (8002cdc ) 8002c42: 6a1b ldr r3, [r3, #32] 8002c44: f423 7340 bic.w r3, r3, #768 ; 0x300 8002c48: 60fb str r3, [r7, #12] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 8002c4a: 4b26 ldr r3, [pc, #152] ; (8002ce4 ) 8002c4c: 2201 movs r2, #1 8002c4e: 601a str r2, [r3, #0] __HAL_RCC_BACKUPRESET_RELEASE(); 8002c50: 4b24 ldr r3, [pc, #144] ; (8002ce4 ) 8002c52: 2200 movs r2, #0 8002c54: 601a str r2, [r3, #0] /* Restore the Content of BDCR register */ RCC->BDCR = temp_reg; 8002c56: 4a21 ldr r2, [pc, #132] ; (8002cdc ) 8002c58: 68fb ldr r3, [r7, #12] 8002c5a: 6213 str r3, [r2, #32] /* Wait for LSERDY if LSE was enabled */ if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) 8002c5c: 68fb ldr r3, [r7, #12] 8002c5e: f003 0301 and.w r3, r3, #1 8002c62: 2b00 cmp r3, #0 8002c64: d014 beq.n 8002c90 { /* Get Start Tick */ tickstart = HAL_GetTick(); 8002c66: f7fe f9c9 bl 8000ffc 8002c6a: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8002c6c: e00a b.n 8002c84 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8002c6e: f7fe f9c5 bl 8000ffc 8002c72: 4602 mov r2, r0 8002c74: 693b ldr r3, [r7, #16] 8002c76: 1ad3 subs r3, r2, r3 8002c78: f241 3288 movw r2, #5000 ; 0x1388 8002c7c: 4293 cmp r3, r2 8002c7e: d901 bls.n 8002c84 { return HAL_TIMEOUT; 8002c80: 2303 movs r3, #3 8002c82: e027 b.n 8002cd4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8002c84: 4b15 ldr r3, [pc, #84] ; (8002cdc ) 8002c86: 6a1b ldr r3, [r3, #32] 8002c88: f003 0302 and.w r3, r3, #2 8002c8c: 2b00 cmp r3, #0 8002c8e: d0ee beq.n 8002c6e } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 8002c90: 4b12 ldr r3, [pc, #72] ; (8002cdc ) 8002c92: 6a1b ldr r3, [r3, #32] 8002c94: f423 7240 bic.w r2, r3, #768 ; 0x300 8002c98: 687b ldr r3, [r7, #4] 8002c9a: 685b ldr r3, [r3, #4] 8002c9c: 490f ldr r1, [pc, #60] ; (8002cdc ) 8002c9e: 4313 orrs r3, r2 8002ca0: 620b str r3, [r1, #32] /* Require to disable power clock if necessary */ if (pwrclkchanged == SET) 8002ca2: 7dfb ldrb r3, [r7, #23] 8002ca4: 2b01 cmp r3, #1 8002ca6: d105 bne.n 8002cb4 { __HAL_RCC_PWR_CLK_DISABLE(); 8002ca8: 4b0c ldr r3, [pc, #48] ; (8002cdc ) 8002caa: 69db ldr r3, [r3, #28] 8002cac: 4a0b ldr r2, [pc, #44] ; (8002cdc ) 8002cae: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 8002cb2: 61d3 str r3, [r2, #28] } } /*------------------------------ ADC clock Configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 8002cb4: 687b ldr r3, [r7, #4] 8002cb6: 681b ldr r3, [r3, #0] 8002cb8: f003 0302 and.w r3, r3, #2 8002cbc: 2b00 cmp r3, #0 8002cbe: d008 beq.n 8002cd2 { /* Check the parameters */ assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection)); /* Configure the ADC clock source */ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 8002cc0: 4b06 ldr r3, [pc, #24] ; (8002cdc ) 8002cc2: 685b ldr r3, [r3, #4] 8002cc4: f423 4240 bic.w r2, r3, #49152 ; 0xc000 8002cc8: 687b ldr r3, [r7, #4] 8002cca: 689b ldr r3, [r3, #8] 8002ccc: 4903 ldr r1, [pc, #12] ; (8002cdc ) 8002cce: 4313 orrs r3, r2 8002cd0: 604b str r3, [r1, #4] /* Configure the USB clock source */ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); } #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ return HAL_OK; 8002cd2: 2300 movs r3, #0 } 8002cd4: 4618 mov r0, r3 8002cd6: 3718 adds r7, #24 8002cd8: 46bd mov sp, r7 8002cda: bd80 pop {r7, pc} 8002cdc: 40021000 .word 0x40021000 8002ce0: 40007000 .word 0x40007000 8002ce4: 42420440 .word 0x42420440 08002ce8 : * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock @endif * @retval Frequency in Hz (0: means that no available frequency for the peripheral) */ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { 8002ce8: b580 push {r7, lr} 8002cea: b084 sub sp, #16 8002cec: af00 add r7, sp, #0 8002cee: 6078 str r0, [r7, #4] const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; const uint8_t aPredivFactorTable[2] = {1, 2}; uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ uint32_t temp_reg = 0U, frequency = 0U; 8002cf0: 2300 movs r3, #0 8002cf2: 60bb str r3, [r7, #8] 8002cf4: 2300 movs r3, #0 8002cf6: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); switch (PeriphClk) 8002cf8: 687b ldr r3, [r7, #4] 8002cfa: 2b01 cmp r3, #1 8002cfc: d002 beq.n 8002d04 8002cfe: 2b02 cmp r3, #2 8002d00: d033 beq.n 8002d6a frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2); break; } default: { break; 8002d02: e041 b.n 8002d88 temp_reg = RCC->BDCR; 8002d04: 4b23 ldr r3, [pc, #140] ; (8002d94 ) 8002d06: 6a1b ldr r3, [r3, #32] 8002d08: 60bb str r3, [r7, #8] if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY))) 8002d0a: 68bb ldr r3, [r7, #8] 8002d0c: f403 7340 and.w r3, r3, #768 ; 0x300 8002d10: f5b3 7f80 cmp.w r3, #256 ; 0x100 8002d14: d108 bne.n 8002d28 8002d16: 68bb ldr r3, [r7, #8] 8002d18: f003 0302 and.w r3, r3, #2 8002d1c: 2b00 cmp r3, #0 8002d1e: d003 beq.n 8002d28 frequency = LSE_VALUE; 8002d20: f44f 4300 mov.w r3, #32768 ; 0x8000 8002d24: 60fb str r3, [r7, #12] 8002d26: e01f b.n 8002d68 else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) 8002d28: 68bb ldr r3, [r7, #8] 8002d2a: f403 7340 and.w r3, r3, #768 ; 0x300 8002d2e: f5b3 7f00 cmp.w r3, #512 ; 0x200 8002d32: d109 bne.n 8002d48 8002d34: 4b17 ldr r3, [pc, #92] ; (8002d94 ) 8002d36: 6a5b ldr r3, [r3, #36] ; 0x24 8002d38: f003 0302 and.w r3, r3, #2 8002d3c: 2b00 cmp r3, #0 8002d3e: d003 beq.n 8002d48 frequency = LSI_VALUE; 8002d40: f649 4340 movw r3, #40000 ; 0x9c40 8002d44: 60fb str r3, [r7, #12] 8002d46: e00f b.n 8002d68 else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) 8002d48: 68bb ldr r3, [r7, #8] 8002d4a: f403 7340 and.w r3, r3, #768 ; 0x300 8002d4e: f5b3 7f40 cmp.w r3, #768 ; 0x300 8002d52: d118 bne.n 8002d86 8002d54: 4b0f ldr r3, [pc, #60] ; (8002d94 ) 8002d56: 681b ldr r3, [r3, #0] 8002d58: f403 3300 and.w r3, r3, #131072 ; 0x20000 8002d5c: 2b00 cmp r3, #0 8002d5e: d012 beq.n 8002d86 frequency = HSE_VALUE / 128U; 8002d60: f24f 4324 movw r3, #62500 ; 0xf424 8002d64: 60fb str r3, [r7, #12] break; 8002d66: e00e b.n 8002d86 8002d68: e00d b.n 8002d86 frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2); 8002d6a: f7ff feb9 bl 8002ae0 8002d6e: 4602 mov r2, r0 8002d70: 4b08 ldr r3, [pc, #32] ; (8002d94 ) 8002d72: 685b ldr r3, [r3, #4] 8002d74: 0b9b lsrs r3, r3, #14 8002d76: f003 0303 and.w r3, r3, #3 8002d7a: 3301 adds r3, #1 8002d7c: 005b lsls r3, r3, #1 8002d7e: fbb2 f3f3 udiv r3, r2, r3 8002d82: 60fb str r3, [r7, #12] break; 8002d84: e000 b.n 8002d88 break; 8002d86: bf00 nop } } return (frequency); 8002d88: 68fb ldr r3, [r7, #12] } 8002d8a: 4618 mov r0, r3 8002d8c: 3710 adds r7, #16 8002d8e: 46bd mov sp, r7 8002d90: bd80 pop {r7, pc} 8002d92: bf00 nop 8002d94: 40021000 .word 0x40021000 08002d98 : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { 8002d98: b580 push {r7, lr} 8002d9a: b082 sub sp, #8 8002d9c: af00 add r7, sp, #0 8002d9e: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8002da0: 687b ldr r3, [r7, #4] 8002da2: 2b00 cmp r3, #0 8002da4: d101 bne.n 8002daa { return HAL_ERROR; 8002da6: 2301 movs r3, #1 8002da8: e01d b.n 8002de6 assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8002daa: 687b ldr r3, [r7, #4] 8002dac: f893 303d ldrb.w r3, [r3, #61] ; 0x3d 8002db0: b2db uxtb r3, r3 8002db2: 2b00 cmp r3, #0 8002db4: d106 bne.n 8002dc4 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8002db6: 687b ldr r3, [r7, #4] 8002db8: 2200 movs r2, #0 8002dba: f883 203c strb.w r2, [r3, #60] ; 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); 8002dbe: 6878 ldr r0, [r7, #4] 8002dc0: f001 fb9a bl 80044f8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8002dc4: 687b ldr r3, [r7, #4] 8002dc6: 2202 movs r2, #2 8002dc8: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8002dcc: 687b ldr r3, [r7, #4] 8002dce: 681a ldr r2, [r3, #0] 8002dd0: 687b ldr r3, [r7, #4] 8002dd2: 3304 adds r3, #4 8002dd4: 4619 mov r1, r3 8002dd6: 4610 mov r0, r2 8002dd8: f000 f958 bl 800308c /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8002ddc: 687b ldr r3, [r7, #4] 8002dde: 2201 movs r2, #1 8002de0: f883 203d strb.w r2, [r3, #61] ; 0x3d return HAL_OK; 8002de4: 2300 movs r3, #0 } 8002de6: 4618 mov r0, r3 8002de8: 3708 adds r7, #8 8002dea: 46bd mov sp, r7 8002dec: bd80 pop {r7, pc} 08002dee : * @brief Starts the TIM Base generation in interrupt mode. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) { 8002dee: b480 push {r7} 8002df0: b085 sub sp, #20 8002df2: af00 add r7, sp, #0 8002df4: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Enable the TIM Update interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); 8002df6: 687b ldr r3, [r7, #4] 8002df8: 681b ldr r3, [r3, #0] 8002dfa: 68da ldr r2, [r3, #12] 8002dfc: 687b ldr r3, [r7, #4] 8002dfe: 681b ldr r3, [r3, #0] 8002e00: f042 0201 orr.w r2, r2, #1 8002e04: 60da str r2, [r3, #12] /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 8002e06: 687b ldr r3, [r7, #4] 8002e08: 681b ldr r3, [r3, #0] 8002e0a: 689b ldr r3, [r3, #8] 8002e0c: f003 0307 and.w r3, r3, #7 8002e10: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8002e12: 68fb ldr r3, [r7, #12] 8002e14: 2b06 cmp r3, #6 8002e16: d007 beq.n 8002e28 { __HAL_TIM_ENABLE(htim); 8002e18: 687b ldr r3, [r7, #4] 8002e1a: 681b ldr r3, [r3, #0] 8002e1c: 681a ldr r2, [r3, #0] 8002e1e: 687b ldr r3, [r7, #4] 8002e20: 681b ldr r3, [r3, #0] 8002e22: f042 0201 orr.w r2, r2, #1 8002e26: 601a str r2, [r3, #0] } /* Return function status */ return HAL_OK; 8002e28: 2300 movs r3, #0 } 8002e2a: 4618 mov r0, r3 8002e2c: 3714 adds r7, #20 8002e2e: 46bd mov sp, r7 8002e30: bc80 pop {r7} 8002e32: 4770 bx lr 08002e34 : * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { 8002e34: b580 push {r7, lr} 8002e36: b082 sub sp, #8 8002e38: af00 add r7, sp, #0 8002e3a: 6078 str r0, [r7, #4] /* Capture compare 1 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) 8002e3c: 687b ldr r3, [r7, #4] 8002e3e: 681b ldr r3, [r3, #0] 8002e40: 691b ldr r3, [r3, #16] 8002e42: f003 0302 and.w r3, r3, #2 8002e46: 2b02 cmp r3, #2 8002e48: d122 bne.n 8002e90 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) 8002e4a: 687b ldr r3, [r7, #4] 8002e4c: 681b ldr r3, [r3, #0] 8002e4e: 68db ldr r3, [r3, #12] 8002e50: f003 0302 and.w r3, r3, #2 8002e54: 2b02 cmp r3, #2 8002e56: d11b bne.n 8002e90 { { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); 8002e58: 687b ldr r3, [r7, #4] 8002e5a: 681b ldr r3, [r3, #0] 8002e5c: f06f 0202 mvn.w r2, #2 8002e60: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 8002e62: 687b ldr r3, [r7, #4] 8002e64: 2201 movs r2, #1 8002e66: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 8002e68: 687b ldr r3, [r7, #4] 8002e6a: 681b ldr r3, [r3, #0] 8002e6c: 699b ldr r3, [r3, #24] 8002e6e: f003 0303 and.w r3, r3, #3 8002e72: 2b00 cmp r3, #0 8002e74: d003 beq.n 8002e7e { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8002e76: 6878 ldr r0, [r7, #4] 8002e78: f000 f8ed bl 8003056 8002e7c: e005 b.n 8002e8a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8002e7e: 6878 ldr r0, [r7, #4] 8002e80: f000 f8e0 bl 8003044 HAL_TIM_PWM_PulseFinishedCallback(htim); 8002e84: 6878 ldr r0, [r7, #4] 8002e86: f000 f8ef bl 8003068 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8002e8a: 687b ldr r3, [r7, #4] 8002e8c: 2200 movs r2, #0 8002e8e: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) 8002e90: 687b ldr r3, [r7, #4] 8002e92: 681b ldr r3, [r3, #0] 8002e94: 691b ldr r3, [r3, #16] 8002e96: f003 0304 and.w r3, r3, #4 8002e9a: 2b04 cmp r3, #4 8002e9c: d122 bne.n 8002ee4 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) 8002e9e: 687b ldr r3, [r7, #4] 8002ea0: 681b ldr r3, [r3, #0] 8002ea2: 68db ldr r3, [r3, #12] 8002ea4: f003 0304 and.w r3, r3, #4 8002ea8: 2b04 cmp r3, #4 8002eaa: d11b bne.n 8002ee4 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); 8002eac: 687b ldr r3, [r7, #4] 8002eae: 681b ldr r3, [r3, #0] 8002eb0: f06f 0204 mvn.w r2, #4 8002eb4: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 8002eb6: 687b ldr r3, [r7, #4] 8002eb8: 2202 movs r2, #2 8002eba: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 8002ebc: 687b ldr r3, [r7, #4] 8002ebe: 681b ldr r3, [r3, #0] 8002ec0: 699b ldr r3, [r3, #24] 8002ec2: f403 7340 and.w r3, r3, #768 ; 0x300 8002ec6: 2b00 cmp r3, #0 8002ec8: d003 beq.n 8002ed2 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8002eca: 6878 ldr r0, [r7, #4] 8002ecc: f000 f8c3 bl 8003056 8002ed0: e005 b.n 8002ede { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8002ed2: 6878 ldr r0, [r7, #4] 8002ed4: f000 f8b6 bl 8003044 HAL_TIM_PWM_PulseFinishedCallback(htim); 8002ed8: 6878 ldr r0, [r7, #4] 8002eda: f000 f8c5 bl 8003068 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8002ede: 687b ldr r3, [r7, #4] 8002ee0: 2200 movs r2, #0 8002ee2: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) 8002ee4: 687b ldr r3, [r7, #4] 8002ee6: 681b ldr r3, [r3, #0] 8002ee8: 691b ldr r3, [r3, #16] 8002eea: f003 0308 and.w r3, r3, #8 8002eee: 2b08 cmp r3, #8 8002ef0: d122 bne.n 8002f38 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) 8002ef2: 687b ldr r3, [r7, #4] 8002ef4: 681b ldr r3, [r3, #0] 8002ef6: 68db ldr r3, [r3, #12] 8002ef8: f003 0308 and.w r3, r3, #8 8002efc: 2b08 cmp r3, #8 8002efe: d11b bne.n 8002f38 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); 8002f00: 687b ldr r3, [r7, #4] 8002f02: 681b ldr r3, [r3, #0] 8002f04: f06f 0208 mvn.w r2, #8 8002f08: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 8002f0a: 687b ldr r3, [r7, #4] 8002f0c: 2204 movs r2, #4 8002f0e: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 8002f10: 687b ldr r3, [r7, #4] 8002f12: 681b ldr r3, [r3, #0] 8002f14: 69db ldr r3, [r3, #28] 8002f16: f003 0303 and.w r3, r3, #3 8002f1a: 2b00 cmp r3, #0 8002f1c: d003 beq.n 8002f26 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8002f1e: 6878 ldr r0, [r7, #4] 8002f20: f000 f899 bl 8003056 8002f24: e005 b.n 8002f32 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8002f26: 6878 ldr r0, [r7, #4] 8002f28: f000 f88c bl 8003044 HAL_TIM_PWM_PulseFinishedCallback(htim); 8002f2c: 6878 ldr r0, [r7, #4] 8002f2e: f000 f89b bl 8003068 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8002f32: 687b ldr r3, [r7, #4] 8002f34: 2200 movs r2, #0 8002f36: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) 8002f38: 687b ldr r3, [r7, #4] 8002f3a: 681b ldr r3, [r3, #0] 8002f3c: 691b ldr r3, [r3, #16] 8002f3e: f003 0310 and.w r3, r3, #16 8002f42: 2b10 cmp r3, #16 8002f44: d122 bne.n 8002f8c { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) 8002f46: 687b ldr r3, [r7, #4] 8002f48: 681b ldr r3, [r3, #0] 8002f4a: 68db ldr r3, [r3, #12] 8002f4c: f003 0310 and.w r3, r3, #16 8002f50: 2b10 cmp r3, #16 8002f52: d11b bne.n 8002f8c { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); 8002f54: 687b ldr r3, [r7, #4] 8002f56: 681b ldr r3, [r3, #0] 8002f58: f06f 0210 mvn.w r2, #16 8002f5c: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 8002f5e: 687b ldr r3, [r7, #4] 8002f60: 2208 movs r2, #8 8002f62: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 8002f64: 687b ldr r3, [r7, #4] 8002f66: 681b ldr r3, [r3, #0] 8002f68: 69db ldr r3, [r3, #28] 8002f6a: f403 7340 and.w r3, r3, #768 ; 0x300 8002f6e: 2b00 cmp r3, #0 8002f70: d003 beq.n 8002f7a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8002f72: 6878 ldr r0, [r7, #4] 8002f74: f000 f86f bl 8003056 8002f78: e005 b.n 8002f86 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8002f7a: 6878 ldr r0, [r7, #4] 8002f7c: f000 f862 bl 8003044 HAL_TIM_PWM_PulseFinishedCallback(htim); 8002f80: 6878 ldr r0, [r7, #4] 8002f82: f000 f871 bl 8003068 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8002f86: 687b ldr r3, [r7, #4] 8002f88: 2200 movs r2, #0 8002f8a: 771a strb r2, [r3, #28] } } /* TIM Update event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) 8002f8c: 687b ldr r3, [r7, #4] 8002f8e: 681b ldr r3, [r3, #0] 8002f90: 691b ldr r3, [r3, #16] 8002f92: f003 0301 and.w r3, r3, #1 8002f96: 2b01 cmp r3, #1 8002f98: d10e bne.n 8002fb8 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) 8002f9a: 687b ldr r3, [r7, #4] 8002f9c: 681b ldr r3, [r3, #0] 8002f9e: 68db ldr r3, [r3, #12] 8002fa0: f003 0301 and.w r3, r3, #1 8002fa4: 2b01 cmp r3, #1 8002fa6: d107 bne.n 8002fb8 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); 8002fa8: 687b ldr r3, [r7, #4] 8002faa: 681b ldr r3, [r3, #0] 8002fac: f06f 0201 mvn.w r2, #1 8002fb0: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); 8002fb2: 6878 ldr r0, [r7, #4] 8002fb4: f001 f9dc bl 8004370 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) 8002fb8: 687b ldr r3, [r7, #4] 8002fba: 681b ldr r3, [r3, #0] 8002fbc: 691b ldr r3, [r3, #16] 8002fbe: f003 0380 and.w r3, r3, #128 ; 0x80 8002fc2: 2b80 cmp r3, #128 ; 0x80 8002fc4: d10e bne.n 8002fe4 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) 8002fc6: 687b ldr r3, [r7, #4] 8002fc8: 681b ldr r3, [r3, #0] 8002fca: 68db ldr r3, [r3, #12] 8002fcc: f003 0380 and.w r3, r3, #128 ; 0x80 8002fd0: 2b80 cmp r3, #128 ; 0x80 8002fd2: d107 bne.n 8002fe4 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); 8002fd4: 687b ldr r3, [r7, #4] 8002fd6: 681b ldr r3, [r3, #0] 8002fd8: f06f 0280 mvn.w r2, #128 ; 0x80 8002fdc: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); 8002fde: 6878 ldr r0, [r7, #4] 8002fe0: f000 f921 bl 8003226 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) 8002fe4: 687b ldr r3, [r7, #4] 8002fe6: 681b ldr r3, [r3, #0] 8002fe8: 691b ldr r3, [r3, #16] 8002fea: f003 0340 and.w r3, r3, #64 ; 0x40 8002fee: 2b40 cmp r3, #64 ; 0x40 8002ff0: d10e bne.n 8003010 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) 8002ff2: 687b ldr r3, [r7, #4] 8002ff4: 681b ldr r3, [r3, #0] 8002ff6: 68db ldr r3, [r3, #12] 8002ff8: f003 0340 and.w r3, r3, #64 ; 0x40 8002ffc: 2b40 cmp r3, #64 ; 0x40 8002ffe: d107 bne.n 8003010 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); 8003000: 687b ldr r3, [r7, #4] 8003002: 681b ldr r3, [r3, #0] 8003004: f06f 0240 mvn.w r2, #64 ; 0x40 8003008: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); 800300a: 6878 ldr r0, [r7, #4] 800300c: f000 f835 bl 800307a #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) 8003010: 687b ldr r3, [r7, #4] 8003012: 681b ldr r3, [r3, #0] 8003014: 691b ldr r3, [r3, #16] 8003016: f003 0320 and.w r3, r3, #32 800301a: 2b20 cmp r3, #32 800301c: d10e bne.n 800303c { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET) 800301e: 687b ldr r3, [r7, #4] 8003020: 681b ldr r3, [r3, #0] 8003022: 68db ldr r3, [r3, #12] 8003024: f003 0320 and.w r3, r3, #32 8003028: 2b20 cmp r3, #32 800302a: d107 bne.n 800303c { __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); 800302c: 687b ldr r3, [r7, #4] 800302e: 681b ldr r3, [r3, #0] 8003030: f06f 0220 mvn.w r2, #32 8003034: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); 8003036: 6878 ldr r0, [r7, #4] 8003038: f000 f8ec bl 8003214 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } 800303c: bf00 nop 800303e: 3708 adds r7, #8 8003040: 46bd mov sp, r7 8003042: bd80 pop {r7, pc} 08003044 : * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { 8003044: b480 push {r7} 8003046: b083 sub sp, #12 8003048: af00 add r7, sp, #0 800304a: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } 800304c: bf00 nop 800304e: 370c adds r7, #12 8003050: 46bd mov sp, r7 8003052: bc80 pop {r7} 8003054: 4770 bx lr 08003056 : * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { 8003056: b480 push {r7} 8003058: b083 sub sp, #12 800305a: af00 add r7, sp, #0 800305c: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } 800305e: bf00 nop 8003060: 370c adds r7, #12 8003062: 46bd mov sp, r7 8003064: bc80 pop {r7} 8003066: 4770 bx lr 08003068 : * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { 8003068: b480 push {r7} 800306a: b083 sub sp, #12 800306c: af00 add r7, sp, #0 800306e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } 8003070: bf00 nop 8003072: 370c adds r7, #12 8003074: 46bd mov sp, r7 8003076: bc80 pop {r7} 8003078: 4770 bx lr 0800307a : * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { 800307a: b480 push {r7} 800307c: b083 sub sp, #12 800307e: af00 add r7, sp, #0 8003080: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } 8003082: bf00 nop 8003084: 370c adds r7, #12 8003086: 46bd mov sp, r7 8003088: bc80 pop {r7} 800308a: 4770 bx lr 0800308c : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) { 800308c: b480 push {r7} 800308e: b085 sub sp, #20 8003090: af00 add r7, sp, #0 8003092: 6078 str r0, [r7, #4] 8003094: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 8003096: 687b ldr r3, [r7, #4] 8003098: 681b ldr r3, [r3, #0] 800309a: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 800309c: 687b ldr r3, [r7, #4] 800309e: 4a35 ldr r2, [pc, #212] ; (8003174 ) 80030a0: 4293 cmp r3, r2 80030a2: d00b beq.n 80030bc 80030a4: 687b ldr r3, [r7, #4] 80030a6: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 80030aa: d007 beq.n 80030bc 80030ac: 687b ldr r3, [r7, #4] 80030ae: 4a32 ldr r2, [pc, #200] ; (8003178 ) 80030b0: 4293 cmp r3, r2 80030b2: d003 beq.n 80030bc 80030b4: 687b ldr r3, [r7, #4] 80030b6: 4a31 ldr r2, [pc, #196] ; (800317c ) 80030b8: 4293 cmp r3, r2 80030ba: d108 bne.n 80030ce { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 80030bc: 68fb ldr r3, [r7, #12] 80030be: f023 0370 bic.w r3, r3, #112 ; 0x70 80030c2: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 80030c4: 683b ldr r3, [r7, #0] 80030c6: 685b ldr r3, [r3, #4] 80030c8: 68fa ldr r2, [r7, #12] 80030ca: 4313 orrs r3, r2 80030cc: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 80030ce: 687b ldr r3, [r7, #4] 80030d0: 4a28 ldr r2, [pc, #160] ; (8003174 ) 80030d2: 4293 cmp r3, r2 80030d4: d017 beq.n 8003106 80030d6: 687b ldr r3, [r7, #4] 80030d8: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 80030dc: d013 beq.n 8003106 80030de: 687b ldr r3, [r7, #4] 80030e0: 4a25 ldr r2, [pc, #148] ; (8003178 ) 80030e2: 4293 cmp r3, r2 80030e4: d00f beq.n 8003106 80030e6: 687b ldr r3, [r7, #4] 80030e8: 4a24 ldr r2, [pc, #144] ; (800317c ) 80030ea: 4293 cmp r3, r2 80030ec: d00b beq.n 8003106 80030ee: 687b ldr r3, [r7, #4] 80030f0: 4a23 ldr r2, [pc, #140] ; (8003180 ) 80030f2: 4293 cmp r3, r2 80030f4: d007 beq.n 8003106 80030f6: 687b ldr r3, [r7, #4] 80030f8: 4a22 ldr r2, [pc, #136] ; (8003184 ) 80030fa: 4293 cmp r3, r2 80030fc: d003 beq.n 8003106 80030fe: 687b ldr r3, [r7, #4] 8003100: 4a21 ldr r2, [pc, #132] ; (8003188 ) 8003102: 4293 cmp r3, r2 8003104: d108 bne.n 8003118 { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 8003106: 68fb ldr r3, [r7, #12] 8003108: f423 7340 bic.w r3, r3, #768 ; 0x300 800310c: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 800310e: 683b ldr r3, [r7, #0] 8003110: 68db ldr r3, [r3, #12] 8003112: 68fa ldr r2, [r7, #12] 8003114: 4313 orrs r3, r2 8003116: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8003118: 68fb ldr r3, [r7, #12] 800311a: f023 0280 bic.w r2, r3, #128 ; 0x80 800311e: 683b ldr r3, [r7, #0] 8003120: 695b ldr r3, [r3, #20] 8003122: 4313 orrs r3, r2 8003124: 60fb str r3, [r7, #12] TIMx->CR1 = tmpcr1; 8003126: 687b ldr r3, [r7, #4] 8003128: 68fa ldr r2, [r7, #12] 800312a: 601a str r2, [r3, #0] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 800312c: 683b ldr r3, [r7, #0] 800312e: 689a ldr r2, [r3, #8] 8003130: 687b ldr r3, [r7, #4] 8003132: 62da str r2, [r3, #44] ; 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 8003134: 683b ldr r3, [r7, #0] 8003136: 681a ldr r2, [r3, #0] 8003138: 687b ldr r3, [r7, #4] 800313a: 629a str r2, [r3, #40] ; 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 800313c: 687b ldr r3, [r7, #4] 800313e: 4a0d ldr r2, [pc, #52] ; (8003174 ) 8003140: 4293 cmp r3, r2 8003142: d00b beq.n 800315c 8003144: 687b ldr r3, [r7, #4] 8003146: 4a0e ldr r2, [pc, #56] ; (8003180 ) 8003148: 4293 cmp r3, r2 800314a: d007 beq.n 800315c 800314c: 687b ldr r3, [r7, #4] 800314e: 4a0d ldr r2, [pc, #52] ; (8003184 ) 8003150: 4293 cmp r3, r2 8003152: d003 beq.n 800315c 8003154: 687b ldr r3, [r7, #4] 8003156: 4a0c ldr r2, [pc, #48] ; (8003188 ) 8003158: 4293 cmp r3, r2 800315a: d103 bne.n 8003164 { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 800315c: 683b ldr r3, [r7, #0] 800315e: 691a ldr r2, [r3, #16] 8003160: 687b ldr r3, [r7, #4] 8003162: 631a str r2, [r3, #48] ; 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 8003164: 687b ldr r3, [r7, #4] 8003166: 2201 movs r2, #1 8003168: 615a str r2, [r3, #20] } 800316a: bf00 nop 800316c: 3714 adds r7, #20 800316e: 46bd mov sp, r7 8003170: bc80 pop {r7} 8003172: 4770 bx lr 8003174: 40012c00 .word 0x40012c00 8003178: 40000400 .word 0x40000400 800317c: 40000800 .word 0x40000800 8003180: 40014000 .word 0x40014000 8003184: 40014400 .word 0x40014400 8003188: 40014800 .word 0x40014800 0800318c : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig) { 800318c: b480 push {r7} 800318e: b085 sub sp, #20 8003190: af00 add r7, sp, #0 8003192: 6078 str r0, [r7, #4] 8003194: 6039 str r1, [r7, #0] assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 8003196: 687b ldr r3, [r7, #4] 8003198: f893 303c ldrb.w r3, [r3, #60] ; 0x3c 800319c: 2b01 cmp r3, #1 800319e: d101 bne.n 80031a4 80031a0: 2302 movs r3, #2 80031a2: e032 b.n 800320a 80031a4: 687b ldr r3, [r7, #4] 80031a6: 2201 movs r2, #1 80031a8: f883 203c strb.w r2, [r3, #60] ; 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 80031ac: 687b ldr r3, [r7, #4] 80031ae: 2202 movs r2, #2 80031b0: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 80031b4: 687b ldr r3, [r7, #4] 80031b6: 681b ldr r3, [r3, #0] 80031b8: 685b ldr r3, [r3, #4] 80031ba: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 80031bc: 687b ldr r3, [r7, #4] 80031be: 681b ldr r3, [r3, #0] 80031c0: 689b ldr r3, [r3, #8] 80031c2: 60bb str r3, [r7, #8] /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 80031c4: 68fb ldr r3, [r7, #12] 80031c6: f023 0370 bic.w r3, r3, #112 ; 0x70 80031ca: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 80031cc: 683b ldr r3, [r7, #0] 80031ce: 681b ldr r3, [r3, #0] 80031d0: 68fa ldr r2, [r7, #12] 80031d2: 4313 orrs r3, r2 80031d4: 60fb str r3, [r7, #12] /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 80031d6: 68bb ldr r3, [r7, #8] 80031d8: f023 0380 bic.w r3, r3, #128 ; 0x80 80031dc: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 80031de: 683b ldr r3, [r7, #0] 80031e0: 685b ldr r3, [r3, #4] 80031e2: 68ba ldr r2, [r7, #8] 80031e4: 4313 orrs r3, r2 80031e6: 60bb str r3, [r7, #8] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 80031e8: 687b ldr r3, [r7, #4] 80031ea: 681b ldr r3, [r3, #0] 80031ec: 68fa ldr r2, [r7, #12] 80031ee: 605a str r2, [r3, #4] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 80031f0: 687b ldr r3, [r7, #4] 80031f2: 681b ldr r3, [r3, #0] 80031f4: 68ba ldr r2, [r7, #8] 80031f6: 609a str r2, [r3, #8] /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 80031f8: 687b ldr r3, [r7, #4] 80031fa: 2201 movs r2, #1 80031fc: f883 203d strb.w r2, [r3, #61] ; 0x3d __HAL_UNLOCK(htim); 8003200: 687b ldr r3, [r7, #4] 8003202: 2200 movs r2, #0 8003204: f883 203c strb.w r2, [r3, #60] ; 0x3c return HAL_OK; 8003208: 2300 movs r3, #0 } 800320a: 4618 mov r0, r3 800320c: 3714 adds r7, #20 800320e: 46bd mov sp, r7 8003210: bc80 pop {r7} 8003212: 4770 bx lr 08003214 : * @brief Hall commutation changed callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { 8003214: b480 push {r7} 8003216: b083 sub sp, #12 8003218: af00 add r7, sp, #0 800321a: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } 800321c: bf00 nop 800321e: 370c adds r7, #12 8003220: 46bd mov sp, r7 8003222: bc80 pop {r7} 8003224: 4770 bx lr 08003226 : * @brief Hall Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { 8003226: b480 push {r7} 8003228: b083 sub sp, #12 800322a: af00 add r7, sp, #0 800322c: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } 800322e: bf00 nop 8003230: 370c adds r7, #12 8003232: 46bd mov sp, r7 8003234: bc80 pop {r7} 8003236: 4770 bx lr 08003238 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 8003238: b580 push {r7, lr} 800323a: b082 sub sp, #8 800323c: af00 add r7, sp, #0 800323e: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 8003240: 687b ldr r3, [r7, #4] 8003242: 2b00 cmp r3, #0 8003244: d101 bne.n 800324a { return HAL_ERROR; 8003246: 2301 movs r3, #1 8003248: e03f b.n 80032ca assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); #if defined(USART_CR1_OVER8) assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); #endif /* USART_CR1_OVER8 */ if (huart->gState == HAL_UART_STATE_RESET) 800324a: 687b ldr r3, [r7, #4] 800324c: f893 3039 ldrb.w r3, [r3, #57] ; 0x39 8003250: b2db uxtb r3, r3 8003252: 2b00 cmp r3, #0 8003254: d106 bne.n 8003264 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 8003256: 687b ldr r3, [r7, #4] 8003258: 2200 movs r2, #0 800325a: f883 2038 strb.w r2, [r3, #56] ; 0x38 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 800325e: 6878 ldr r0, [r7, #4] 8003260: f001 f968 bl 8004534 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 8003264: 687b ldr r3, [r7, #4] 8003266: 2224 movs r2, #36 ; 0x24 8003268: f883 2039 strb.w r2, [r3, #57] ; 0x39 /* Disable the peripheral */ __HAL_UART_DISABLE(huart); 800326c: 687b ldr r3, [r7, #4] 800326e: 681b ldr r3, [r3, #0] 8003270: 68da ldr r2, [r3, #12] 8003272: 687b ldr r3, [r7, #4] 8003274: 681b ldr r3, [r3, #0] 8003276: f422 5200 bic.w r2, r2, #8192 ; 0x2000 800327a: 60da str r2, [r3, #12] /* Set the UART Communication parameters */ UART_SetConfig(huart); 800327c: 6878 ldr r0, [r7, #4] 800327e: f000 fc81 bl 8003b84 /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 8003282: 687b ldr r3, [r7, #4] 8003284: 681b ldr r3, [r3, #0] 8003286: 691a ldr r2, [r3, #16] 8003288: 687b ldr r3, [r7, #4] 800328a: 681b ldr r3, [r3, #0] 800328c: f422 4290 bic.w r2, r2, #18432 ; 0x4800 8003290: 611a str r2, [r3, #16] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 8003292: 687b ldr r3, [r7, #4] 8003294: 681b ldr r3, [r3, #0] 8003296: 695a ldr r2, [r3, #20] 8003298: 687b ldr r3, [r7, #4] 800329a: 681b ldr r3, [r3, #0] 800329c: f022 022a bic.w r2, r2, #42 ; 0x2a 80032a0: 615a str r2, [r3, #20] /* Enable the peripheral */ __HAL_UART_ENABLE(huart); 80032a2: 687b ldr r3, [r7, #4] 80032a4: 681b ldr r3, [r3, #0] 80032a6: 68da ldr r2, [r3, #12] 80032a8: 687b ldr r3, [r7, #4] 80032aa: 681b ldr r3, [r3, #0] 80032ac: f442 5200 orr.w r2, r2, #8192 ; 0x2000 80032b0: 60da str r2, [r3, #12] /* Initialize the UART state */ huart->ErrorCode = HAL_UART_ERROR_NONE; 80032b2: 687b ldr r3, [r7, #4] 80032b4: 2200 movs r2, #0 80032b6: 63da str r2, [r3, #60] ; 0x3c huart->gState = HAL_UART_STATE_READY; 80032b8: 687b ldr r3, [r7, #4] 80032ba: 2220 movs r2, #32 80032bc: f883 2039 strb.w r2, [r3, #57] ; 0x39 huart->RxState = HAL_UART_STATE_READY; 80032c0: 687b ldr r3, [r7, #4] 80032c2: 2220 movs r2, #32 80032c4: f883 203a strb.w r2, [r3, #58] ; 0x3a return HAL_OK; 80032c8: 2300 movs r3, #0 } 80032ca: 4618 mov r0, r3 80032cc: 3708 adds r7, #8 80032ce: 46bd mov sp, r7 80032d0: bd80 pop {r7, pc} 080032d2 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 80032d2: b480 push {r7} 80032d4: b085 sub sp, #20 80032d6: af00 add r7, sp, #0 80032d8: 60f8 str r0, [r7, #12] 80032da: 60b9 str r1, [r7, #8] 80032dc: 4613 mov r3, r2 80032de: 80fb strh r3, [r7, #6] /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) 80032e0: 68fb ldr r3, [r7, #12] 80032e2: f893 303a ldrb.w r3, [r3, #58] ; 0x3a 80032e6: b2db uxtb r3, r3 80032e8: 2b20 cmp r3, #32 80032ea: d140 bne.n 800336e { if ((pData == NULL) || (Size == 0U)) 80032ec: 68bb ldr r3, [r7, #8] 80032ee: 2b00 cmp r3, #0 80032f0: d002 beq.n 80032f8 80032f2: 88fb ldrh r3, [r7, #6] 80032f4: 2b00 cmp r3, #0 80032f6: d101 bne.n 80032fc { return HAL_ERROR; 80032f8: 2301 movs r3, #1 80032fa: e039 b.n 8003370 } /* Process Locked */ __HAL_LOCK(huart); 80032fc: 68fb ldr r3, [r7, #12] 80032fe: f893 3038 ldrb.w r3, [r3, #56] ; 0x38 8003302: 2b01 cmp r3, #1 8003304: d101 bne.n 800330a 8003306: 2302 movs r3, #2 8003308: e032 b.n 8003370 800330a: 68fb ldr r3, [r7, #12] 800330c: 2201 movs r2, #1 800330e: f883 2038 strb.w r2, [r3, #56] ; 0x38 huart->pRxBuffPtr = pData; 8003312: 68fb ldr r3, [r7, #12] 8003314: 68ba ldr r2, [r7, #8] 8003316: 629a str r2, [r3, #40] ; 0x28 huart->RxXferSize = Size; 8003318: 68fb ldr r3, [r7, #12] 800331a: 88fa ldrh r2, [r7, #6] 800331c: 859a strh r2, [r3, #44] ; 0x2c huart->RxXferCount = Size; 800331e: 68fb ldr r3, [r7, #12] 8003320: 88fa ldrh r2, [r7, #6] 8003322: 85da strh r2, [r3, #46] ; 0x2e huart->ErrorCode = HAL_UART_ERROR_NONE; 8003324: 68fb ldr r3, [r7, #12] 8003326: 2200 movs r2, #0 8003328: 63da str r2, [r3, #60] ; 0x3c huart->RxState = HAL_UART_STATE_BUSY_RX; 800332a: 68fb ldr r3, [r7, #12] 800332c: 2222 movs r2, #34 ; 0x22 800332e: f883 203a strb.w r2, [r3, #58] ; 0x3a /* Process Unlocked */ __HAL_UNLOCK(huart); 8003332: 68fb ldr r3, [r7, #12] 8003334: 2200 movs r2, #0 8003336: f883 2038 strb.w r2, [r3, #56] ; 0x38 /* Enable the UART Parity Error Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_PE); 800333a: 68fb ldr r3, [r7, #12] 800333c: 681b ldr r3, [r3, #0] 800333e: 68da ldr r2, [r3, #12] 8003340: 68fb ldr r3, [r7, #12] 8003342: 681b ldr r3, [r3, #0] 8003344: f442 7280 orr.w r2, r2, #256 ; 0x100 8003348: 60da str r2, [r3, #12] /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_ENABLE_IT(huart, UART_IT_ERR); 800334a: 68fb ldr r3, [r7, #12] 800334c: 681b ldr r3, [r3, #0] 800334e: 695a ldr r2, [r3, #20] 8003350: 68fb ldr r3, [r7, #12] 8003352: 681b ldr r3, [r3, #0] 8003354: f042 0201 orr.w r2, r2, #1 8003358: 615a str r2, [r3, #20] /* Enable the UART Data Register not empty Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE); 800335a: 68fb ldr r3, [r7, #12] 800335c: 681b ldr r3, [r3, #0] 800335e: 68da ldr r2, [r3, #12] 8003360: 68fb ldr r3, [r7, #12] 8003362: 681b ldr r3, [r3, #0] 8003364: f042 0220 orr.w r2, r2, #32 8003368: 60da str r2, [r3, #12] return HAL_OK; 800336a: 2300 movs r3, #0 800336c: e000 b.n 8003370 } else { return HAL_BUSY; 800336e: 2302 movs r3, #2 } } 8003370: 4618 mov r0, r3 8003372: 3714 adds r7, #20 8003374: 46bd mov sp, r7 8003376: bc80 pop {r7} 8003378: 4770 bx lr ... 0800337c : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 800337c: b580 push {r7, lr} 800337e: b086 sub sp, #24 8003380: af00 add r7, sp, #0 8003382: 60f8 str r0, [r7, #12] 8003384: 60b9 str r1, [r7, #8] 8003386: 4613 mov r3, r2 8003388: 80fb strh r3, [r7, #6] uint32_t *tmp; /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 800338a: 68fb ldr r3, [r7, #12] 800338c: f893 3039 ldrb.w r3, [r3, #57] ; 0x39 8003390: b2db uxtb r3, r3 8003392: 2b20 cmp r3, #32 8003394: d153 bne.n 800343e { if ((pData == NULL) || (Size == 0U)) 8003396: 68bb ldr r3, [r7, #8] 8003398: 2b00 cmp r3, #0 800339a: d002 beq.n 80033a2 800339c: 88fb ldrh r3, [r7, #6] 800339e: 2b00 cmp r3, #0 80033a0: d101 bne.n 80033a6 { return HAL_ERROR; 80033a2: 2301 movs r3, #1 80033a4: e04c b.n 8003440 } /* Process Locked */ __HAL_LOCK(huart); 80033a6: 68fb ldr r3, [r7, #12] 80033a8: f893 3038 ldrb.w r3, [r3, #56] ; 0x38 80033ac: 2b01 cmp r3, #1 80033ae: d101 bne.n 80033b4 80033b0: 2302 movs r3, #2 80033b2: e045 b.n 8003440 80033b4: 68fb ldr r3, [r7, #12] 80033b6: 2201 movs r2, #1 80033b8: f883 2038 strb.w r2, [r3, #56] ; 0x38 huart->pTxBuffPtr = pData; 80033bc: 68ba ldr r2, [r7, #8] 80033be: 68fb ldr r3, [r7, #12] 80033c0: 621a str r2, [r3, #32] huart->TxXferSize = Size; 80033c2: 68fb ldr r3, [r7, #12] 80033c4: 88fa ldrh r2, [r7, #6] 80033c6: 849a strh r2, [r3, #36] ; 0x24 huart->TxXferCount = Size; 80033c8: 68fb ldr r3, [r7, #12] 80033ca: 88fa ldrh r2, [r7, #6] 80033cc: 84da strh r2, [r3, #38] ; 0x26 huart->ErrorCode = HAL_UART_ERROR_NONE; 80033ce: 68fb ldr r3, [r7, #12] 80033d0: 2200 movs r2, #0 80033d2: 63da str r2, [r3, #60] ; 0x3c huart->gState = HAL_UART_STATE_BUSY_TX; 80033d4: 68fb ldr r3, [r7, #12] 80033d6: 2221 movs r2, #33 ; 0x21 80033d8: f883 2039 strb.w r2, [r3, #57] ; 0x39 /* Set the UART DMA transfer complete callback */ huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; 80033dc: 68fb ldr r3, [r7, #12] 80033de: 6b1b ldr r3, [r3, #48] ; 0x30 80033e0: 4a19 ldr r2, [pc, #100] ; (8003448 ) 80033e2: 629a str r2, [r3, #40] ; 0x28 /* Set the UART DMA Half transfer complete callback */ huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; 80033e4: 68fb ldr r3, [r7, #12] 80033e6: 6b1b ldr r3, [r3, #48] ; 0x30 80033e8: 4a18 ldr r2, [pc, #96] ; (800344c ) 80033ea: 62da str r2, [r3, #44] ; 0x2c /* Set the DMA error callback */ huart->hdmatx->XferErrorCallback = UART_DMAError; 80033ec: 68fb ldr r3, [r7, #12] 80033ee: 6b1b ldr r3, [r3, #48] ; 0x30 80033f0: 4a17 ldr r2, [pc, #92] ; (8003450 ) 80033f2: 631a str r2, [r3, #48] ; 0x30 /* Set the DMA abort callback */ huart->hdmatx->XferAbortCallback = NULL; 80033f4: 68fb ldr r3, [r7, #12] 80033f6: 6b1b ldr r3, [r3, #48] ; 0x30 80033f8: 2200 movs r2, #0 80033fa: 635a str r2, [r3, #52] ; 0x34 /* Enable the UART transmit DMA channel */ tmp = (uint32_t *)&pData; 80033fc: f107 0308 add.w r3, r7, #8 8003400: 617b str r3, [r7, #20] HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t *)tmp, (uint32_t)&huart->Instance->DR, Size); 8003402: 68fb ldr r3, [r7, #12] 8003404: 6b18 ldr r0, [r3, #48] ; 0x30 8003406: 697b ldr r3, [r7, #20] 8003408: 6819 ldr r1, [r3, #0] 800340a: 68fb ldr r3, [r7, #12] 800340c: 681b ldr r3, [r3, #0] 800340e: 3304 adds r3, #4 8003410: 461a mov r2, r3 8003412: 88fb ldrh r3, [r7, #6] 8003414: f7fe fc16 bl 8001c44 /* Clear the TC flag in the SR register by writing 0 to it */ __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC); 8003418: 68fb ldr r3, [r7, #12] 800341a: 681b ldr r3, [r3, #0] 800341c: f06f 0240 mvn.w r2, #64 ; 0x40 8003420: 601a str r2, [r3, #0] /* Process Unlocked */ __HAL_UNLOCK(huart); 8003422: 68fb ldr r3, [r7, #12] 8003424: 2200 movs r2, #0 8003426: f883 2038 strb.w r2, [r3, #56] ; 0x38 /* Enable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); 800342a: 68fb ldr r3, [r7, #12] 800342c: 681b ldr r3, [r3, #0] 800342e: 695a ldr r2, [r3, #20] 8003430: 68fb ldr r3, [r7, #12] 8003432: 681b ldr r3, [r3, #0] 8003434: f042 0280 orr.w r2, r2, #128 ; 0x80 8003438: 615a str r2, [r3, #20] return HAL_OK; 800343a: 2300 movs r3, #0 800343c: e000 b.n 8003440 } else { return HAL_BUSY; 800343e: 2302 movs r3, #2 } } 8003440: 4618 mov r0, r3 8003442: 3718 adds r7, #24 8003444: 46bd mov sp, r7 8003446: bd80 pop {r7, pc} 8003448: 08003795 .word 0x08003795 800344c: 080037e7 .word 0x080037e7 8003450: 08003887 .word 0x08003887 08003454 : * @param Size Amount of data elements (u8 or u16) to be received. * @note When the UART parity is enabled (PCE = 1) the received data contains the parity bit. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8003454: b580 push {r7, lr} 8003456: b086 sub sp, #24 8003458: af00 add r7, sp, #0 800345a: 60f8 str r0, [r7, #12] 800345c: 60b9 str r1, [r7, #8] 800345e: 4613 mov r3, r2 8003460: 80fb strh r3, [r7, #6] uint32_t *tmp; /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) 8003462: 68fb ldr r3, [r7, #12] 8003464: f893 303a ldrb.w r3, [r3, #58] ; 0x3a 8003468: b2db uxtb r3, r3 800346a: 2b20 cmp r3, #32 800346c: d166 bne.n 800353c { if ((pData == NULL) || (Size == 0U)) 800346e: 68bb ldr r3, [r7, #8] 8003470: 2b00 cmp r3, #0 8003472: d002 beq.n 800347a 8003474: 88fb ldrh r3, [r7, #6] 8003476: 2b00 cmp r3, #0 8003478: d101 bne.n 800347e { return HAL_ERROR; 800347a: 2301 movs r3, #1 800347c: e05f b.n 800353e } /* Process Locked */ __HAL_LOCK(huart); 800347e: 68fb ldr r3, [r7, #12] 8003480: f893 3038 ldrb.w r3, [r3, #56] ; 0x38 8003484: 2b01 cmp r3, #1 8003486: d101 bne.n 800348c 8003488: 2302 movs r3, #2 800348a: e058 b.n 800353e 800348c: 68fb ldr r3, [r7, #12] 800348e: 2201 movs r2, #1 8003490: f883 2038 strb.w r2, [r3, #56] ; 0x38 huart->pRxBuffPtr = pData; 8003494: 68ba ldr r2, [r7, #8] 8003496: 68fb ldr r3, [r7, #12] 8003498: 629a str r2, [r3, #40] ; 0x28 huart->RxXferSize = Size; 800349a: 68fb ldr r3, [r7, #12] 800349c: 88fa ldrh r2, [r7, #6] 800349e: 859a strh r2, [r3, #44] ; 0x2c huart->ErrorCode = HAL_UART_ERROR_NONE; 80034a0: 68fb ldr r3, [r7, #12] 80034a2: 2200 movs r2, #0 80034a4: 63da str r2, [r3, #60] ; 0x3c huart->RxState = HAL_UART_STATE_BUSY_RX; 80034a6: 68fb ldr r3, [r7, #12] 80034a8: 2222 movs r2, #34 ; 0x22 80034aa: f883 203a strb.w r2, [r3, #58] ; 0x3a /* Set the UART DMA transfer complete callback */ huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; 80034ae: 68fb ldr r3, [r7, #12] 80034b0: 6b5b ldr r3, [r3, #52] ; 0x34 80034b2: 4a25 ldr r2, [pc, #148] ; (8003548 ) 80034b4: 629a str r2, [r3, #40] ; 0x28 /* Set the UART DMA Half transfer complete callback */ huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; 80034b6: 68fb ldr r3, [r7, #12] 80034b8: 6b5b ldr r3, [r3, #52] ; 0x34 80034ba: 4a24 ldr r2, [pc, #144] ; (800354c ) 80034bc: 62da str r2, [r3, #44] ; 0x2c /* Set the DMA error callback */ huart->hdmarx->XferErrorCallback = UART_DMAError; 80034be: 68fb ldr r3, [r7, #12] 80034c0: 6b5b ldr r3, [r3, #52] ; 0x34 80034c2: 4a23 ldr r2, [pc, #140] ; (8003550 ) 80034c4: 631a str r2, [r3, #48] ; 0x30 /* Set the DMA abort callback */ huart->hdmarx->XferAbortCallback = NULL; 80034c6: 68fb ldr r3, [r7, #12] 80034c8: 6b5b ldr r3, [r3, #52] ; 0x34 80034ca: 2200 movs r2, #0 80034cc: 635a str r2, [r3, #52] ; 0x34 /* Enable the DMA channel */ tmp = (uint32_t *)&pData; 80034ce: f107 0308 add.w r3, r7, #8 80034d2: 617b str r3, [r7, #20] HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t *)tmp, Size); 80034d4: 68fb ldr r3, [r7, #12] 80034d6: 6b58 ldr r0, [r3, #52] ; 0x34 80034d8: 68fb ldr r3, [r7, #12] 80034da: 681b ldr r3, [r3, #0] 80034dc: 3304 adds r3, #4 80034de: 4619 mov r1, r3 80034e0: 697b ldr r3, [r7, #20] 80034e2: 681a ldr r2, [r3, #0] 80034e4: 88fb ldrh r3, [r7, #6] 80034e6: f7fe fbad bl 8001c44 /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */ __HAL_UART_CLEAR_OREFLAG(huart); 80034ea: 2300 movs r3, #0 80034ec: 613b str r3, [r7, #16] 80034ee: 68fb ldr r3, [r7, #12] 80034f0: 681b ldr r3, [r3, #0] 80034f2: 681b ldr r3, [r3, #0] 80034f4: 613b str r3, [r7, #16] 80034f6: 68fb ldr r3, [r7, #12] 80034f8: 681b ldr r3, [r3, #0] 80034fa: 685b ldr r3, [r3, #4] 80034fc: 613b str r3, [r7, #16] 80034fe: 693b ldr r3, [r7, #16] /* Process Unlocked */ __HAL_UNLOCK(huart); 8003500: 68fb ldr r3, [r7, #12] 8003502: 2200 movs r2, #0 8003504: f883 2038 strb.w r2, [r3, #56] ; 0x38 /* Enable the UART Parity Error Interrupt */ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8003508: 68fb ldr r3, [r7, #12] 800350a: 681b ldr r3, [r3, #0] 800350c: 68da ldr r2, [r3, #12] 800350e: 68fb ldr r3, [r7, #12] 8003510: 681b ldr r3, [r3, #0] 8003512: f442 7280 orr.w r2, r2, #256 ; 0x100 8003516: 60da str r2, [r3, #12] /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(huart->Instance->CR3, USART_CR3_EIE); 8003518: 68fb ldr r3, [r7, #12] 800351a: 681b ldr r3, [r3, #0] 800351c: 695a ldr r2, [r3, #20] 800351e: 68fb ldr r3, [r7, #12] 8003520: 681b ldr r3, [r3, #0] 8003522: f042 0201 orr.w r2, r2, #1 8003526: 615a str r2, [r3, #20] /* Enable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8003528: 68fb ldr r3, [r7, #12] 800352a: 681b ldr r3, [r3, #0] 800352c: 695a ldr r2, [r3, #20] 800352e: 68fb ldr r3, [r7, #12] 8003530: 681b ldr r3, [r3, #0] 8003532: f042 0240 orr.w r2, r2, #64 ; 0x40 8003536: 615a str r2, [r3, #20] return HAL_OK; 8003538: 2300 movs r3, #0 800353a: e000 b.n 800353e } else { return HAL_BUSY; 800353c: 2302 movs r3, #2 } } 800353e: 4618 mov r0, r3 8003540: 3718 adds r7, #24 8003542: 46bd mov sp, r7 8003544: bd80 pop {r7, pc} 8003546: bf00 nop 8003548: 08003803 .word 0x08003803 800354c: 0800386b .word 0x0800386b 8003550: 08003887 .word 0x08003887 08003554 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { 8003554: b580 push {r7, lr} 8003556: b088 sub sp, #32 8003558: af00 add r7, sp, #0 800355a: 6078 str r0, [r7, #4] uint32_t isrflags = READ_REG(huart->Instance->SR); 800355c: 687b ldr r3, [r7, #4] 800355e: 681b ldr r3, [r3, #0] 8003560: 681b ldr r3, [r3, #0] 8003562: 61fb str r3, [r7, #28] uint32_t cr1its = READ_REG(huart->Instance->CR1); 8003564: 687b ldr r3, [r7, #4] 8003566: 681b ldr r3, [r3, #0] 8003568: 68db ldr r3, [r3, #12] 800356a: 61bb str r3, [r7, #24] uint32_t cr3its = READ_REG(huart->Instance->CR3); 800356c: 687b ldr r3, [r7, #4] 800356e: 681b ldr r3, [r3, #0] 8003570: 695b ldr r3, [r3, #20] 8003572: 617b str r3, [r7, #20] uint32_t errorflags = 0x00U; 8003574: 2300 movs r3, #0 8003576: 613b str r3, [r7, #16] uint32_t dmarequest = 0x00U; 8003578: 2300 movs r3, #0 800357a: 60fb str r3, [r7, #12] /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE)); 800357c: 69fb ldr r3, [r7, #28] 800357e: f003 030f and.w r3, r3, #15 8003582: 613b str r3, [r7, #16] if (errorflags == RESET) 8003584: 693b ldr r3, [r7, #16] 8003586: 2b00 cmp r3, #0 8003588: d10d bne.n 80035a6 { /* UART in mode Receiver -------------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 800358a: 69fb ldr r3, [r7, #28] 800358c: f003 0320 and.w r3, r3, #32 8003590: 2b00 cmp r3, #0 8003592: d008 beq.n 80035a6 8003594: 69bb ldr r3, [r7, #24] 8003596: f003 0320 and.w r3, r3, #32 800359a: 2b00 cmp r3, #0 800359c: d003 beq.n 80035a6 { UART_Receive_IT(huart); 800359e: 6878 ldr r0, [r7, #4] 80035a0: f000 fa6e bl 8003a80 return; 80035a4: e0cc b.n 8003740 } } /* If some errors occur */ if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) 80035a6: 693b ldr r3, [r7, #16] 80035a8: 2b00 cmp r3, #0 80035aa: f000 80ab beq.w 8003704 80035ae: 697b ldr r3, [r7, #20] 80035b0: f003 0301 and.w r3, r3, #1 80035b4: 2b00 cmp r3, #0 80035b6: d105 bne.n 80035c4 80035b8: 69bb ldr r3, [r7, #24] 80035ba: f403 7390 and.w r3, r3, #288 ; 0x120 80035be: 2b00 cmp r3, #0 80035c0: f000 80a0 beq.w 8003704 { /* UART parity error interrupt occurred ----------------------------------*/ if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) 80035c4: 69fb ldr r3, [r7, #28] 80035c6: f003 0301 and.w r3, r3, #1 80035ca: 2b00 cmp r3, #0 80035cc: d00a beq.n 80035e4 80035ce: 69bb ldr r3, [r7, #24] 80035d0: f403 7380 and.w r3, r3, #256 ; 0x100 80035d4: 2b00 cmp r3, #0 80035d6: d005 beq.n 80035e4 { huart->ErrorCode |= HAL_UART_ERROR_PE; 80035d8: 687b ldr r3, [r7, #4] 80035da: 6bdb ldr r3, [r3, #60] ; 0x3c 80035dc: f043 0201 orr.w r2, r3, #1 80035e0: 687b ldr r3, [r7, #4] 80035e2: 63da str r2, [r3, #60] ; 0x3c } /* UART noise error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 80035e4: 69fb ldr r3, [r7, #28] 80035e6: f003 0304 and.w r3, r3, #4 80035ea: 2b00 cmp r3, #0 80035ec: d00a beq.n 8003604 80035ee: 697b ldr r3, [r7, #20] 80035f0: f003 0301 and.w r3, r3, #1 80035f4: 2b00 cmp r3, #0 80035f6: d005 beq.n 8003604 { huart->ErrorCode |= HAL_UART_ERROR_NE; 80035f8: 687b ldr r3, [r7, #4] 80035fa: 6bdb ldr r3, [r3, #60] ; 0x3c 80035fc: f043 0202 orr.w r2, r3, #2 8003600: 687b ldr r3, [r7, #4] 8003602: 63da str r2, [r3, #60] ; 0x3c } /* UART frame error interrupt occurred -----------------------------------*/ if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 8003604: 69fb ldr r3, [r7, #28] 8003606: f003 0302 and.w r3, r3, #2 800360a: 2b00 cmp r3, #0 800360c: d00a beq.n 8003624 800360e: 697b ldr r3, [r7, #20] 8003610: f003 0301 and.w r3, r3, #1 8003614: 2b00 cmp r3, #0 8003616: d005 beq.n 8003624 { huart->ErrorCode |= HAL_UART_ERROR_FE; 8003618: 687b ldr r3, [r7, #4] 800361a: 6bdb ldr r3, [r3, #60] ; 0x3c 800361c: f043 0204 orr.w r2, r3, #4 8003620: 687b ldr r3, [r7, #4] 8003622: 63da str r2, [r3, #60] ; 0x3c } /* UART Over-Run interrupt occurred --------------------------------------*/ if (((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) 8003624: 69fb ldr r3, [r7, #28] 8003626: f003 0308 and.w r3, r3, #8 800362a: 2b00 cmp r3, #0 800362c: d00a beq.n 8003644 800362e: 697b ldr r3, [r7, #20] 8003630: f003 0301 and.w r3, r3, #1 8003634: 2b00 cmp r3, #0 8003636: d005 beq.n 8003644 { huart->ErrorCode |= HAL_UART_ERROR_ORE; 8003638: 687b ldr r3, [r7, #4] 800363a: 6bdb ldr r3, [r3, #60] ; 0x3c 800363c: f043 0208 orr.w r2, r3, #8 8003640: 687b ldr r3, [r7, #4] 8003642: 63da str r2, [r3, #60] ; 0x3c } /* Call UART Error Call back function if need be --------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 8003644: 687b ldr r3, [r7, #4] 8003646: 6bdb ldr r3, [r3, #60] ; 0x3c 8003648: 2b00 cmp r3, #0 800364a: d078 beq.n 800373e { /* UART in mode Receiver -----------------------------------------------*/ if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) 800364c: 69fb ldr r3, [r7, #28] 800364e: f003 0320 and.w r3, r3, #32 8003652: 2b00 cmp r3, #0 8003654: d007 beq.n 8003666 8003656: 69bb ldr r3, [r7, #24] 8003658: f003 0320 and.w r3, r3, #32 800365c: 2b00 cmp r3, #0 800365e: d002 beq.n 8003666 { UART_Receive_IT(huart); 8003660: 6878 ldr r0, [r7, #4] 8003662: f000 fa0d bl 8003a80 } /* If Overrun error occurs, or if any error occurs in DMA mode reception, consider error as blocking */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 8003666: 687b ldr r3, [r7, #4] 8003668: 681b ldr r3, [r3, #0] 800366a: 695b ldr r3, [r3, #20] 800366c: f003 0340 and.w r3, r3, #64 ; 0x40 8003670: 2b00 cmp r3, #0 8003672: bf14 ite ne 8003674: 2301 movne r3, #1 8003676: 2300 moveq r3, #0 8003678: b2db uxtb r3, r3 800367a: 60fb str r3, [r7, #12] if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest) 800367c: 687b ldr r3, [r7, #4] 800367e: 6bdb ldr r3, [r3, #60] ; 0x3c 8003680: f003 0308 and.w r3, r3, #8 8003684: 2b00 cmp r3, #0 8003686: d102 bne.n 800368e 8003688: 68fb ldr r3, [r7, #12] 800368a: 2b00 cmp r3, #0 800368c: d031 beq.n 80036f2 { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); 800368e: 6878 ldr r0, [r7, #4] 8003690: f000 f958 bl 8003944 /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8003694: 687b ldr r3, [r7, #4] 8003696: 681b ldr r3, [r3, #0] 8003698: 695b ldr r3, [r3, #20] 800369a: f003 0340 and.w r3, r3, #64 ; 0x40 800369e: 2b00 cmp r3, #0 80036a0: d023 beq.n 80036ea { CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 80036a2: 687b ldr r3, [r7, #4] 80036a4: 681b ldr r3, [r3, #0] 80036a6: 695a ldr r2, [r3, #20] 80036a8: 687b ldr r3, [r7, #4] 80036aa: 681b ldr r3, [r3, #0] 80036ac: f022 0240 bic.w r2, r2, #64 ; 0x40 80036b0: 615a str r2, [r3, #20] /* Abort the UART DMA Rx channel */ if (huart->hdmarx != NULL) 80036b2: 687b ldr r3, [r7, #4] 80036b4: 6b5b ldr r3, [r3, #52] ; 0x34 80036b6: 2b00 cmp r3, #0 80036b8: d013 beq.n 80036e2 { /* Set the UART DMA Abort callback : will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; 80036ba: 687b ldr r3, [r7, #4] 80036bc: 6b5b ldr r3, [r3, #52] ; 0x34 80036be: 4a22 ldr r2, [pc, #136] ; (8003748 ) 80036c0: 635a str r2, [r3, #52] ; 0x34 if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 80036c2: 687b ldr r3, [r7, #4] 80036c4: 6b5b ldr r3, [r3, #52] ; 0x34 80036c6: 4618 mov r0, r3 80036c8: f7fe fb1c bl 8001d04 80036cc: 4603 mov r3, r0 80036ce: 2b00 cmp r3, #0 80036d0: d016 beq.n 8003700 { /* Call Directly XferAbortCallback function in case of error */ huart->hdmarx->XferAbortCallback(huart->hdmarx); 80036d2: 687b ldr r3, [r7, #4] 80036d4: 6b5b ldr r3, [r3, #52] ; 0x34 80036d6: 6b5b ldr r3, [r3, #52] ; 0x34 80036d8: 687a ldr r2, [r7, #4] 80036da: 6b52 ldr r2, [r2, #52] ; 0x34 80036dc: 4610 mov r0, r2 80036de: 4798 blx r3 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80036e0: e00e b.n 8003700 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 80036e2: 6878 ldr r0, [r7, #4] 80036e4: f000 f84d bl 8003782 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80036e8: e00a b.n 8003700 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 80036ea: 6878 ldr r0, [r7, #4] 80036ec: f000 f849 bl 8003782 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 80036f0: e006 b.n 8003700 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 80036f2: 6878 ldr r0, [r7, #4] 80036f4: f000 f845 bl 8003782 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 80036f8: 687b ldr r3, [r7, #4] 80036fa: 2200 movs r2, #0 80036fc: 63da str r2, [r3, #60] ; 0x3c } } return; 80036fe: e01e b.n 800373e if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8003700: bf00 nop return; 8003702: e01c b.n 800373e } /* End if some error occurs */ /* UART in mode Transmitter ------------------------------------------------*/ if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) 8003704: 69fb ldr r3, [r7, #28] 8003706: f003 0380 and.w r3, r3, #128 ; 0x80 800370a: 2b00 cmp r3, #0 800370c: d008 beq.n 8003720 800370e: 69bb ldr r3, [r7, #24] 8003710: f003 0380 and.w r3, r3, #128 ; 0x80 8003714: 2b00 cmp r3, #0 8003716: d003 beq.n 8003720 { UART_Transmit_IT(huart); 8003718: 6878 ldr r0, [r7, #4] 800371a: f000 f944 bl 80039a6 return; 800371e: e00f b.n 8003740 } /* UART in mode Transmitter end --------------------------------------------*/ if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) 8003720: 69fb ldr r3, [r7, #28] 8003722: f003 0340 and.w r3, r3, #64 ; 0x40 8003726: 2b00 cmp r3, #0 8003728: d00a beq.n 8003740 800372a: 69bb ldr r3, [r7, #24] 800372c: f003 0340 and.w r3, r3, #64 ; 0x40 8003730: 2b00 cmp r3, #0 8003732: d005 beq.n 8003740 { UART_EndTransmit_IT(huart); 8003734: 6878 ldr r0, [r7, #4] 8003736: f000 f98b bl 8003a50 return; 800373a: bf00 nop 800373c: e000 b.n 8003740 return; 800373e: bf00 nop } } 8003740: 3720 adds r7, #32 8003742: 46bd mov sp, r7 8003744: bd80 pop {r7, pc} 8003746: bf00 nop 8003748: 0800397f .word 0x0800397f 0800374c : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { 800374c: b480 push {r7} 800374e: b083 sub sp, #12 8003750: af00 add r7, sp, #0 8003752: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_TxCpltCallback could be implemented in the user file */ } 8003754: bf00 nop 8003756: 370c adds r7, #12 8003758: 46bd mov sp, r7 800375a: bc80 pop {r7} 800375c: 4770 bx lr 0800375e : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) { 800375e: b480 push {r7} 8003760: b083 sub sp, #12 8003762: af00 add r7, sp, #0 8003764: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_TxHalfCpltCallback could be implemented in the user file */ } 8003766: bf00 nop 8003768: 370c adds r7, #12 800376a: 46bd mov sp, r7 800376c: bc80 pop {r7} 800376e: 4770 bx lr 08003770 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) { 8003770: b480 push {r7} 8003772: b083 sub sp, #12 8003774: af00 add r7, sp, #0 8003776: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_RxHalfCpltCallback could be implemented in the user file */ } 8003778: bf00 nop 800377a: 370c adds r7, #12 800377c: 46bd mov sp, r7 800377e: bc80 pop {r7} 8003780: 4770 bx lr 08003782 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { 8003782: b480 push {r7} 8003784: b083 sub sp, #12 8003786: af00 add r7, sp, #0 8003788: 6078 str r0, [r7, #4] /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_ErrorCallback could be implemented in the user file */ } 800378a: bf00 nop 800378c: 370c adds r7, #12 800378e: 46bd mov sp, r7 8003790: bc80 pop {r7} 8003792: 4770 bx lr 08003794 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) { 8003794: b580 push {r7, lr} 8003796: b084 sub sp, #16 8003798: af00 add r7, sp, #0 800379a: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 800379c: 687b ldr r3, [r7, #4] 800379e: 6a5b ldr r3, [r3, #36] ; 0x24 80037a0: 60fb str r3, [r7, #12] /* DMA Normal mode*/ if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 80037a2: 687b ldr r3, [r7, #4] 80037a4: 681b ldr r3, [r3, #0] 80037a6: 681b ldr r3, [r3, #0] 80037a8: f003 0320 and.w r3, r3, #32 80037ac: 2b00 cmp r3, #0 80037ae: d113 bne.n 80037d8 { huart->TxXferCount = 0x00U; 80037b0: 68fb ldr r3, [r7, #12] 80037b2: 2200 movs r2, #0 80037b4: 84da strh r2, [r3, #38] ; 0x26 /* Disable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); 80037b6: 68fb ldr r3, [r7, #12] 80037b8: 681b ldr r3, [r3, #0] 80037ba: 695a ldr r2, [r3, #20] 80037bc: 68fb ldr r3, [r7, #12] 80037be: 681b ldr r3, [r3, #0] 80037c0: f022 0280 bic.w r2, r2, #128 ; 0x80 80037c4: 615a str r2, [r3, #20] /* Enable the UART Transmit Complete Interrupt */ SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 80037c6: 68fb ldr r3, [r7, #12] 80037c8: 681b ldr r3, [r3, #0] 80037ca: 68da ldr r2, [r3, #12] 80037cc: 68fb ldr r3, [r7, #12] 80037ce: 681b ldr r3, [r3, #0] 80037d0: f042 0240 orr.w r2, r2, #64 ; 0x40 80037d4: 60da str r2, [r3, #12] #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } 80037d6: e002 b.n 80037de HAL_UART_TxCpltCallback(huart); 80037d8: 68f8 ldr r0, [r7, #12] 80037da: f7ff ffb7 bl 800374c } 80037de: bf00 nop 80037e0: 3710 adds r7, #16 80037e2: 46bd mov sp, r7 80037e4: bd80 pop {r7, pc} 080037e6 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) { 80037e6: b580 push {r7, lr} 80037e8: b084 sub sp, #16 80037ea: af00 add r7, sp, #0 80037ec: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 80037ee: 687b ldr r3, [r7, #4] 80037f0: 6a5b ldr r3, [r3, #36] ; 0x24 80037f2: 60fb str r3, [r7, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxHalfCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxHalfCpltCallback(huart); 80037f4: 68f8 ldr r0, [r7, #12] 80037f6: f7ff ffb2 bl 800375e #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 80037fa: bf00 nop 80037fc: 3710 adds r7, #16 80037fe: 46bd mov sp, r7 8003800: bd80 pop {r7, pc} 08003802 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { 8003802: b580 push {r7, lr} 8003804: b084 sub sp, #16 8003806: af00 add r7, sp, #0 8003808: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 800380a: 687b ldr r3, [r7, #4] 800380c: 6a5b ldr r3, [r3, #36] ; 0x24 800380e: 60fb str r3, [r7, #12] /* DMA Normal mode*/ if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 8003810: 687b ldr r3, [r7, #4] 8003812: 681b ldr r3, [r3, #0] 8003814: 681b ldr r3, [r3, #0] 8003816: f003 0320 and.w r3, r3, #32 800381a: 2b00 cmp r3, #0 800381c: d11e bne.n 800385c { huart->RxXferCount = 0U; 800381e: 68fb ldr r3, [r7, #12] 8003820: 2200 movs r2, #0 8003822: 85da strh r2, [r3, #46] ; 0x2e /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8003824: 68fb ldr r3, [r7, #12] 8003826: 681b ldr r3, [r3, #0] 8003828: 68da ldr r2, [r3, #12] 800382a: 68fb ldr r3, [r7, #12] 800382c: 681b ldr r3, [r3, #0] 800382e: f422 7280 bic.w r2, r2, #256 ; 0x100 8003832: 60da str r2, [r3, #12] CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8003834: 68fb ldr r3, [r7, #12] 8003836: 681b ldr r3, [r3, #0] 8003838: 695a ldr r2, [r3, #20] 800383a: 68fb ldr r3, [r7, #12] 800383c: 681b ldr r3, [r3, #0] 800383e: f022 0201 bic.w r2, r2, #1 8003842: 615a str r2, [r3, #20] /* Disable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8003844: 68fb ldr r3, [r7, #12] 8003846: 681b ldr r3, [r3, #0] 8003848: 695a ldr r2, [r3, #20] 800384a: 68fb ldr r3, [r7, #12] 800384c: 681b ldr r3, [r3, #0] 800384e: f022 0240 bic.w r2, r2, #64 ; 0x40 8003852: 615a str r2, [r3, #20] /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8003854: 68fb ldr r3, [r7, #12] 8003856: 2220 movs r2, #32 8003858: f883 203a strb.w r2, [r3, #58] ; 0x3a #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 800385c: 68f8 ldr r0, [r7, #12] 800385e: f7fd fb05 bl 8000e6c #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8003862: bf00 nop 8003864: 3710 adds r7, #16 8003866: 46bd mov sp, r7 8003868: bd80 pop {r7, pc} 0800386a : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { 800386a: b580 push {r7, lr} 800386c: b084 sub sp, #16 800386e: af00 add r7, sp, #0 8003870: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8003872: 687b ldr r3, [r7, #4] 8003874: 6a5b ldr r3, [r3, #36] ; 0x24 8003876: 60fb str r3, [r7, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Half complete callback*/ huart->RxHalfCpltCallback(huart); #else /*Call legacy weak Rx Half complete callback*/ HAL_UART_RxHalfCpltCallback(huart); 8003878: 68f8 ldr r0, [r7, #12] 800387a: f7ff ff79 bl 8003770 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 800387e: bf00 nop 8003880: 3710 adds r7, #16 8003882: 46bd mov sp, r7 8003884: bd80 pop {r7, pc} 08003886 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAError(DMA_HandleTypeDef *hdma) { 8003886: b580 push {r7, lr} 8003888: b084 sub sp, #16 800388a: af00 add r7, sp, #0 800388c: 6078 str r0, [r7, #4] uint32_t dmarequest = 0x00U; 800388e: 2300 movs r3, #0 8003890: 60fb str r3, [r7, #12] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8003892: 687b ldr r3, [r7, #4] 8003894: 6a5b ldr r3, [r3, #36] ; 0x24 8003896: 60bb str r3, [r7, #8] /* Stop UART DMA Tx request if ongoing */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT); 8003898: 68bb ldr r3, [r7, #8] 800389a: 681b ldr r3, [r3, #0] 800389c: 695b ldr r3, [r3, #20] 800389e: f003 0380 and.w r3, r3, #128 ; 0x80 80038a2: 2b00 cmp r3, #0 80038a4: bf14 ite ne 80038a6: 2301 movne r3, #1 80038a8: 2300 moveq r3, #0 80038aa: b2db uxtb r3, r3 80038ac: 60fb str r3, [r7, #12] if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) 80038ae: 68bb ldr r3, [r7, #8] 80038b0: f893 3039 ldrb.w r3, [r3, #57] ; 0x39 80038b4: b2db uxtb r3, r3 80038b6: 2b21 cmp r3, #33 ; 0x21 80038b8: d108 bne.n 80038cc 80038ba: 68fb ldr r3, [r7, #12] 80038bc: 2b00 cmp r3, #0 80038be: d005 beq.n 80038cc { huart->TxXferCount = 0x00U; 80038c0: 68bb ldr r3, [r7, #8] 80038c2: 2200 movs r2, #0 80038c4: 84da strh r2, [r3, #38] ; 0x26 UART_EndTxTransfer(huart); 80038c6: 68b8 ldr r0, [r7, #8] 80038c8: f000 f827 bl 800391a } /* Stop UART DMA Rx request if ongoing */ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); 80038cc: 68bb ldr r3, [r7, #8] 80038ce: 681b ldr r3, [r3, #0] 80038d0: 695b ldr r3, [r3, #20] 80038d2: f003 0340 and.w r3, r3, #64 ; 0x40 80038d6: 2b00 cmp r3, #0 80038d8: bf14 ite ne 80038da: 2301 movne r3, #1 80038dc: 2300 moveq r3, #0 80038de: b2db uxtb r3, r3 80038e0: 60fb str r3, [r7, #12] if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest) 80038e2: 68bb ldr r3, [r7, #8] 80038e4: f893 303a ldrb.w r3, [r3, #58] ; 0x3a 80038e8: b2db uxtb r3, r3 80038ea: 2b22 cmp r3, #34 ; 0x22 80038ec: d108 bne.n 8003900 80038ee: 68fb ldr r3, [r7, #12] 80038f0: 2b00 cmp r3, #0 80038f2: d005 beq.n 8003900 { huart->RxXferCount = 0x00U; 80038f4: 68bb ldr r3, [r7, #8] 80038f6: 2200 movs r2, #0 80038f8: 85da strh r2, [r3, #46] ; 0x2e UART_EndRxTransfer(huart); 80038fa: 68b8 ldr r0, [r7, #8] 80038fc: f000 f822 bl 8003944 } huart->ErrorCode |= HAL_UART_ERROR_DMA; 8003900: 68bb ldr r3, [r7, #8] 8003902: 6bdb ldr r3, [r3, #60] ; 0x3c 8003904: f043 0210 orr.w r2, r3, #16 8003908: 68bb ldr r3, [r7, #8] 800390a: 63da str r2, [r3, #60] ; 0x3c #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 800390c: 68b8 ldr r0, [r7, #8] 800390e: f7ff ff38 bl 8003782 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8003912: bf00 nop 8003914: 3710 adds r7, #16 8003916: 46bd mov sp, r7 8003918: bd80 pop {r7, pc} 0800391a : * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). * @param huart UART handle. * @retval None */ static void UART_EndTxTransfer(UART_HandleTypeDef *huart) { 800391a: b480 push {r7} 800391c: b083 sub sp, #12 800391e: af00 add r7, sp, #0 8003920: 6078 str r0, [r7, #4] /* Disable TXEIE and TCIE interrupts */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); 8003922: 687b ldr r3, [r7, #4] 8003924: 681b ldr r3, [r3, #0] 8003926: 68da ldr r2, [r3, #12] 8003928: 687b ldr r3, [r7, #4] 800392a: 681b ldr r3, [r3, #0] 800392c: f022 02c0 bic.w r2, r2, #192 ; 0xc0 8003930: 60da str r2, [r3, #12] /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8003932: 687b ldr r3, [r7, #4] 8003934: 2220 movs r2, #32 8003936: f883 2039 strb.w r2, [r3, #57] ; 0x39 } 800393a: bf00 nop 800393c: 370c adds r7, #12 800393e: 46bd mov sp, r7 8003940: bc80 pop {r7} 8003942: 4770 bx lr 08003944 : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 8003944: b480 push {r7} 8003946: b083 sub sp, #12 8003948: af00 add r7, sp, #0 800394a: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); 800394c: 687b ldr r3, [r7, #4] 800394e: 681b ldr r3, [r3, #0] 8003950: 68da ldr r2, [r3, #12] 8003952: 687b ldr r3, [r7, #4] 8003954: 681b ldr r3, [r3, #0] 8003956: f422 7290 bic.w r2, r2, #288 ; 0x120 800395a: 60da str r2, [r3, #12] CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 800395c: 687b ldr r3, [r7, #4] 800395e: 681b ldr r3, [r3, #0] 8003960: 695a ldr r2, [r3, #20] 8003962: 687b ldr r3, [r7, #4] 8003964: 681b ldr r3, [r3, #0] 8003966: f022 0201 bic.w r2, r2, #1 800396a: 615a str r2, [r3, #20] /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 800396c: 687b ldr r3, [r7, #4] 800396e: 2220 movs r2, #32 8003970: f883 203a strb.w r2, [r3, #58] ; 0x3a } 8003974: bf00 nop 8003976: 370c adds r7, #12 8003978: 46bd mov sp, r7 800397a: bc80 pop {r7} 800397c: 4770 bx lr 0800397e : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { 800397e: b580 push {r7, lr} 8003980: b084 sub sp, #16 8003982: af00 add r7, sp, #0 8003984: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8003986: 687b ldr r3, [r7, #4] 8003988: 6a5b ldr r3, [r3, #36] ; 0x24 800398a: 60fb str r3, [r7, #12] huart->RxXferCount = 0x00U; 800398c: 68fb ldr r3, [r7, #12] 800398e: 2200 movs r2, #0 8003990: 85da strh r2, [r3, #46] ; 0x2e huart->TxXferCount = 0x00U; 8003992: 68fb ldr r3, [r7, #12] 8003994: 2200 movs r2, #0 8003996: 84da strh r2, [r3, #38] ; 0x26 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8003998: 68f8 ldr r0, [r7, #12] 800399a: f7ff fef2 bl 8003782 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 800399e: bf00 nop 80039a0: 3710 adds r7, #16 80039a2: 46bd mov sp, r7 80039a4: bd80 pop {r7, pc} 080039a6 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) { 80039a6: b480 push {r7} 80039a8: b085 sub sp, #20 80039aa: af00 add r7, sp, #0 80039ac: 6078 str r0, [r7, #4] uint16_t *tmp; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 80039ae: 687b ldr r3, [r7, #4] 80039b0: f893 3039 ldrb.w r3, [r3, #57] ; 0x39 80039b4: b2db uxtb r3, r3 80039b6: 2b21 cmp r3, #33 ; 0x21 80039b8: d144 bne.n 8003a44 { if (huart->Init.WordLength == UART_WORDLENGTH_9B) 80039ba: 687b ldr r3, [r7, #4] 80039bc: 689b ldr r3, [r3, #8] 80039be: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 80039c2: d11a bne.n 80039fa { tmp = (uint16_t *) huart->pTxBuffPtr; 80039c4: 687b ldr r3, [r7, #4] 80039c6: 6a1b ldr r3, [r3, #32] 80039c8: 60fb str r3, [r7, #12] huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); 80039ca: 68fb ldr r3, [r7, #12] 80039cc: 881b ldrh r3, [r3, #0] 80039ce: 461a mov r2, r3 80039d0: 687b ldr r3, [r7, #4] 80039d2: 681b ldr r3, [r3, #0] 80039d4: f3c2 0208 ubfx r2, r2, #0, #9 80039d8: 605a str r2, [r3, #4] if (huart->Init.Parity == UART_PARITY_NONE) 80039da: 687b ldr r3, [r7, #4] 80039dc: 691b ldr r3, [r3, #16] 80039de: 2b00 cmp r3, #0 80039e0: d105 bne.n 80039ee { huart->pTxBuffPtr += 2U; 80039e2: 687b ldr r3, [r7, #4] 80039e4: 6a1b ldr r3, [r3, #32] 80039e6: 1c9a adds r2, r3, #2 80039e8: 687b ldr r3, [r7, #4] 80039ea: 621a str r2, [r3, #32] 80039ec: e00e b.n 8003a0c } else { huart->pTxBuffPtr += 1U; 80039ee: 687b ldr r3, [r7, #4] 80039f0: 6a1b ldr r3, [r3, #32] 80039f2: 1c5a adds r2, r3, #1 80039f4: 687b ldr r3, [r7, #4] 80039f6: 621a str r2, [r3, #32] 80039f8: e008 b.n 8003a0c } } else { huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF); 80039fa: 687b ldr r3, [r7, #4] 80039fc: 6a1b ldr r3, [r3, #32] 80039fe: 1c59 adds r1, r3, #1 8003a00: 687a ldr r2, [r7, #4] 8003a02: 6211 str r1, [r2, #32] 8003a04: 781a ldrb r2, [r3, #0] 8003a06: 687b ldr r3, [r7, #4] 8003a08: 681b ldr r3, [r3, #0] 8003a0a: 605a str r2, [r3, #4] } if (--huart->TxXferCount == 0U) 8003a0c: 687b ldr r3, [r7, #4] 8003a0e: 8cdb ldrh r3, [r3, #38] ; 0x26 8003a10: b29b uxth r3, r3 8003a12: 3b01 subs r3, #1 8003a14: b29b uxth r3, r3 8003a16: 687a ldr r2, [r7, #4] 8003a18: 4619 mov r1, r3 8003a1a: 84d1 strh r1, [r2, #38] ; 0x26 8003a1c: 2b00 cmp r3, #0 8003a1e: d10f bne.n 8003a40 { /* Disable the UART Transmit Complete Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); 8003a20: 687b ldr r3, [r7, #4] 8003a22: 681b ldr r3, [r3, #0] 8003a24: 68da ldr r2, [r3, #12] 8003a26: 687b ldr r3, [r7, #4] 8003a28: 681b ldr r3, [r3, #0] 8003a2a: f022 0280 bic.w r2, r2, #128 ; 0x80 8003a2e: 60da str r2, [r3, #12] /* Enable the UART Transmit Complete Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_TC); 8003a30: 687b ldr r3, [r7, #4] 8003a32: 681b ldr r3, [r3, #0] 8003a34: 68da ldr r2, [r3, #12] 8003a36: 687b ldr r3, [r7, #4] 8003a38: 681b ldr r3, [r3, #0] 8003a3a: f042 0240 orr.w r2, r2, #64 ; 0x40 8003a3e: 60da str r2, [r3, #12] } return HAL_OK; 8003a40: 2300 movs r3, #0 8003a42: e000 b.n 8003a46 } else { return HAL_BUSY; 8003a44: 2302 movs r3, #2 } } 8003a46: 4618 mov r0, r3 8003a48: 3714 adds r7, #20 8003a4a: 46bd mov sp, r7 8003a4c: bc80 pop {r7} 8003a4e: 4770 bx lr 08003a50 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) { 8003a50: b580 push {r7, lr} 8003a52: b082 sub sp, #8 8003a54: af00 add r7, sp, #0 8003a56: 6078 str r0, [r7, #4] /* Disable the UART Transmit Complete Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TC); 8003a58: 687b ldr r3, [r7, #4] 8003a5a: 681b ldr r3, [r3, #0] 8003a5c: 68da ldr r2, [r3, #12] 8003a5e: 687b ldr r3, [r7, #4] 8003a60: 681b ldr r3, [r3, #0] 8003a62: f022 0240 bic.w r2, r2, #64 ; 0x40 8003a66: 60da str r2, [r3, #12] /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8003a68: 687b ldr r3, [r7, #4] 8003a6a: 2220 movs r2, #32 8003a6c: f883 2039 strb.w r2, [r3, #57] ; 0x39 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); 8003a70: 6878 ldr r0, [r7, #4] 8003a72: f7ff fe6b bl 800374c #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return HAL_OK; 8003a76: 2300 movs r3, #0 } 8003a78: 4618 mov r0, r3 8003a7a: 3708 adds r7, #8 8003a7c: 46bd mov sp, r7 8003a7e: bd80 pop {r7, pc} 08003a80 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) { 8003a80: b580 push {r7, lr} 8003a82: b084 sub sp, #16 8003a84: af00 add r7, sp, #0 8003a86: 6078 str r0, [r7, #4] uint16_t *tmp; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 8003a88: 687b ldr r3, [r7, #4] 8003a8a: f893 303a ldrb.w r3, [r3, #58] ; 0x3a 8003a8e: b2db uxtb r3, r3 8003a90: 2b22 cmp r3, #34 ; 0x22 8003a92: d171 bne.n 8003b78 { if (huart->Init.WordLength == UART_WORDLENGTH_9B) 8003a94: 687b ldr r3, [r7, #4] 8003a96: 689b ldr r3, [r3, #8] 8003a98: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8003a9c: d123 bne.n 8003ae6 { tmp = (uint16_t *) huart->pRxBuffPtr; 8003a9e: 687b ldr r3, [r7, #4] 8003aa0: 6a9b ldr r3, [r3, #40] ; 0x28 8003aa2: 60fb str r3, [r7, #12] if (huart->Init.Parity == UART_PARITY_NONE) 8003aa4: 687b ldr r3, [r7, #4] 8003aa6: 691b ldr r3, [r3, #16] 8003aa8: 2b00 cmp r3, #0 8003aaa: d10e bne.n 8003aca { *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); 8003aac: 687b ldr r3, [r7, #4] 8003aae: 681b ldr r3, [r3, #0] 8003ab0: 685b ldr r3, [r3, #4] 8003ab2: b29b uxth r3, r3 8003ab4: f3c3 0308 ubfx r3, r3, #0, #9 8003ab8: b29a uxth r2, r3 8003aba: 68fb ldr r3, [r7, #12] 8003abc: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 8003abe: 687b ldr r3, [r7, #4] 8003ac0: 6a9b ldr r3, [r3, #40] ; 0x28 8003ac2: 1c9a adds r2, r3, #2 8003ac4: 687b ldr r3, [r7, #4] 8003ac6: 629a str r2, [r3, #40] ; 0x28 8003ac8: e029 b.n 8003b1e } else { *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF); 8003aca: 687b ldr r3, [r7, #4] 8003acc: 681b ldr r3, [r3, #0] 8003ace: 685b ldr r3, [r3, #4] 8003ad0: b29b uxth r3, r3 8003ad2: b2db uxtb r3, r3 8003ad4: b29a uxth r2, r3 8003ad6: 68fb ldr r3, [r7, #12] 8003ad8: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 1U; 8003ada: 687b ldr r3, [r7, #4] 8003adc: 6a9b ldr r3, [r3, #40] ; 0x28 8003ade: 1c5a adds r2, r3, #1 8003ae0: 687b ldr r3, [r7, #4] 8003ae2: 629a str r2, [r3, #40] ; 0x28 8003ae4: e01b b.n 8003b1e } } else { if (huart->Init.Parity == UART_PARITY_NONE) 8003ae6: 687b ldr r3, [r7, #4] 8003ae8: 691b ldr r3, [r3, #16] 8003aea: 2b00 cmp r3, #0 8003aec: d10a bne.n 8003b04 { *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); 8003aee: 687b ldr r3, [r7, #4] 8003af0: 681b ldr r3, [r3, #0] 8003af2: 6858 ldr r0, [r3, #4] 8003af4: 687b ldr r3, [r7, #4] 8003af6: 6a9b ldr r3, [r3, #40] ; 0x28 8003af8: 1c59 adds r1, r3, #1 8003afa: 687a ldr r2, [r7, #4] 8003afc: 6291 str r1, [r2, #40] ; 0x28 8003afe: b2c2 uxtb r2, r0 8003b00: 701a strb r2, [r3, #0] 8003b02: e00c b.n 8003b1e } else { *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); 8003b04: 687b ldr r3, [r7, #4] 8003b06: 681b ldr r3, [r3, #0] 8003b08: 685b ldr r3, [r3, #4] 8003b0a: b2da uxtb r2, r3 8003b0c: 687b ldr r3, [r7, #4] 8003b0e: 6a9b ldr r3, [r3, #40] ; 0x28 8003b10: 1c58 adds r0, r3, #1 8003b12: 6879 ldr r1, [r7, #4] 8003b14: 6288 str r0, [r1, #40] ; 0x28 8003b16: f002 027f and.w r2, r2, #127 ; 0x7f 8003b1a: b2d2 uxtb r2, r2 8003b1c: 701a strb r2, [r3, #0] } } if (--huart->RxXferCount == 0U) 8003b1e: 687b ldr r3, [r7, #4] 8003b20: 8ddb ldrh r3, [r3, #46] ; 0x2e 8003b22: b29b uxth r3, r3 8003b24: 3b01 subs r3, #1 8003b26: b29b uxth r3, r3 8003b28: 687a ldr r2, [r7, #4] 8003b2a: 4619 mov r1, r3 8003b2c: 85d1 strh r1, [r2, #46] ; 0x2e 8003b2e: 2b00 cmp r3, #0 8003b30: d120 bne.n 8003b74 { /* Disable the UART Data Register not empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); 8003b32: 687b ldr r3, [r7, #4] 8003b34: 681b ldr r3, [r3, #0] 8003b36: 68da ldr r2, [r3, #12] 8003b38: 687b ldr r3, [r7, #4] 8003b3a: 681b ldr r3, [r3, #0] 8003b3c: f022 0220 bic.w r2, r2, #32 8003b40: 60da str r2, [r3, #12] /* Disable the UART Parity Error Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_PE); 8003b42: 687b ldr r3, [r7, #4] 8003b44: 681b ldr r3, [r3, #0] 8003b46: 68da ldr r2, [r3, #12] 8003b48: 687b ldr r3, [r7, #4] 8003b4a: 681b ldr r3, [r3, #0] 8003b4c: f422 7280 bic.w r2, r2, #256 ; 0x100 8003b50: 60da str r2, [r3, #12] /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); 8003b52: 687b ldr r3, [r7, #4] 8003b54: 681b ldr r3, [r3, #0] 8003b56: 695a ldr r2, [r3, #20] 8003b58: 687b ldr r3, [r7, #4] 8003b5a: 681b ldr r3, [r3, #0] 8003b5c: f022 0201 bic.w r2, r2, #1 8003b60: 615a str r2, [r3, #20] /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8003b62: 687b ldr r3, [r7, #4] 8003b64: 2220 movs r2, #32 8003b66: f883 203a strb.w r2, [r3, #58] ; 0x3a #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 8003b6a: 6878 ldr r0, [r7, #4] 8003b6c: f7fd f97e bl 8000e6c #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return HAL_OK; 8003b70: 2300 movs r3, #0 8003b72: e002 b.n 8003b7a } return HAL_OK; 8003b74: 2300 movs r3, #0 8003b76: e000 b.n 8003b7a } else { return HAL_BUSY; 8003b78: 2302 movs r3, #2 } } 8003b7a: 4618 mov r0, r3 8003b7c: 3710 adds r7, #16 8003b7e: 46bd mov sp, r7 8003b80: bd80 pop {r7, pc} ... 08003b84 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_SetConfig(UART_HandleTypeDef *huart) { 8003b84: b580 push {r7, lr} 8003b86: b084 sub sp, #16 8003b88: af00 add r7, sp, #0 8003b8a: 6078 str r0, [r7, #4] assert_param(IS_UART_MODE(huart->Init.Mode)); /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 8003b8c: 687b ldr r3, [r7, #4] 8003b8e: 681b ldr r3, [r3, #0] 8003b90: 691b ldr r3, [r3, #16] 8003b92: f423 5140 bic.w r1, r3, #12288 ; 0x3000 8003b96: 687b ldr r3, [r7, #4] 8003b98: 68da ldr r2, [r3, #12] 8003b9a: 687b ldr r3, [r7, #4] 8003b9c: 681b ldr r3, [r3, #0] 8003b9e: 430a orrs r2, r1 8003ba0: 611a str r2, [r3, #16] Set PCE and PS bits according to huart->Init.Parity value Set TE and RE bits according to huart->Init.Mode value Set OVER8 bit according to huart->Init.OverSampling value */ #if defined(USART_CR1_OVER8) tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; 8003ba2: 687b ldr r3, [r7, #4] 8003ba4: 689a ldr r2, [r3, #8] 8003ba6: 687b ldr r3, [r7, #4] 8003ba8: 691b ldr r3, [r3, #16] 8003baa: 431a orrs r2, r3 8003bac: 687b ldr r3, [r7, #4] 8003bae: 695b ldr r3, [r3, #20] 8003bb0: 431a orrs r2, r3 8003bb2: 687b ldr r3, [r7, #4] 8003bb4: 69db ldr r3, [r3, #28] 8003bb6: 4313 orrs r3, r2 8003bb8: 60fb str r3, [r7, #12] MODIFY_REG(huart->Instance->CR1, 8003bba: 687b ldr r3, [r7, #4] 8003bbc: 681b ldr r3, [r3, #0] 8003bbe: 68db ldr r3, [r3, #12] 8003bc0: f423 4316 bic.w r3, r3, #38400 ; 0x9600 8003bc4: f023 030c bic.w r3, r3, #12 8003bc8: 687a ldr r2, [r7, #4] 8003bca: 6812 ldr r2, [r2, #0] 8003bcc: 68f9 ldr r1, [r7, #12] 8003bce: 430b orrs r3, r1 8003bd0: 60d3 str r3, [r2, #12] tmpreg); #endif /* USART_CR1_OVER8 */ /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); 8003bd2: 687b ldr r3, [r7, #4] 8003bd4: 681b ldr r3, [r3, #0] 8003bd6: 695b ldr r3, [r3, #20] 8003bd8: f423 7140 bic.w r1, r3, #768 ; 0x300 8003bdc: 687b ldr r3, [r7, #4] 8003bde: 699a ldr r2, [r3, #24] 8003be0: 687b ldr r3, [r7, #4] 8003be2: 681b ldr r3, [r3, #0] 8003be4: 430a orrs r2, r1 8003be6: 615a str r2, [r3, #20] #if defined(USART_CR1_OVER8) /* Check the Over Sampling */ if(huart->Init.OverSampling == UART_OVERSAMPLING_8) 8003be8: 687b ldr r3, [r7, #4] 8003bea: 69db ldr r3, [r3, #28] 8003bec: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 8003bf0: f040 80a5 bne.w 8003d3e { /*-------------------------- USART BRR Configuration ---------------------*/ if(huart->Instance == USART1) 8003bf4: 687b ldr r3, [r7, #4] 8003bf6: 681b ldr r3, [r3, #0] 8003bf8: 4aa4 ldr r2, [pc, #656] ; (8003e8c ) 8003bfa: 4293 cmp r3, r2 8003bfc: d14f bne.n 8003c9e { pclk = HAL_RCC_GetPCLK2Freq(); 8003bfe: f7fe ff6f bl 8002ae0 8003c02: 60b8 str r0, [r7, #8] huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate); 8003c04: 68ba ldr r2, [r7, #8] 8003c06: 4613 mov r3, r2 8003c08: 009b lsls r3, r3, #2 8003c0a: 4413 add r3, r2 8003c0c: 009a lsls r2, r3, #2 8003c0e: 441a add r2, r3 8003c10: 687b ldr r3, [r7, #4] 8003c12: 685b ldr r3, [r3, #4] 8003c14: 005b lsls r3, r3, #1 8003c16: fbb2 f3f3 udiv r3, r2, r3 8003c1a: 4a9d ldr r2, [pc, #628] ; (8003e90 ) 8003c1c: fba2 2303 umull r2, r3, r2, r3 8003c20: 095b lsrs r3, r3, #5 8003c22: 0119 lsls r1, r3, #4 8003c24: 68ba ldr r2, [r7, #8] 8003c26: 4613 mov r3, r2 8003c28: 009b lsls r3, r3, #2 8003c2a: 4413 add r3, r2 8003c2c: 009a lsls r2, r3, #2 8003c2e: 441a add r2, r3 8003c30: 687b ldr r3, [r7, #4] 8003c32: 685b ldr r3, [r3, #4] 8003c34: 005b lsls r3, r3, #1 8003c36: fbb2 f2f3 udiv r2, r2, r3 8003c3a: 4b95 ldr r3, [pc, #596] ; (8003e90 ) 8003c3c: fba3 0302 umull r0, r3, r3, r2 8003c40: 095b lsrs r3, r3, #5 8003c42: 2064 movs r0, #100 ; 0x64 8003c44: fb00 f303 mul.w r3, r0, r3 8003c48: 1ad3 subs r3, r2, r3 8003c4a: 00db lsls r3, r3, #3 8003c4c: 3332 adds r3, #50 ; 0x32 8003c4e: 4a90 ldr r2, [pc, #576] ; (8003e90 ) 8003c50: fba2 2303 umull r2, r3, r2, r3 8003c54: 095b lsrs r3, r3, #5 8003c56: 005b lsls r3, r3, #1 8003c58: f403 73f8 and.w r3, r3, #496 ; 0x1f0 8003c5c: 4419 add r1, r3 8003c5e: 68ba ldr r2, [r7, #8] 8003c60: 4613 mov r3, r2 8003c62: 009b lsls r3, r3, #2 8003c64: 4413 add r3, r2 8003c66: 009a lsls r2, r3, #2 8003c68: 441a add r2, r3 8003c6a: 687b ldr r3, [r7, #4] 8003c6c: 685b ldr r3, [r3, #4] 8003c6e: 005b lsls r3, r3, #1 8003c70: fbb2 f2f3 udiv r2, r2, r3 8003c74: 4b86 ldr r3, [pc, #536] ; (8003e90 ) 8003c76: fba3 0302 umull r0, r3, r3, r2 8003c7a: 095b lsrs r3, r3, #5 8003c7c: 2064 movs r0, #100 ; 0x64 8003c7e: fb00 f303 mul.w r3, r0, r3 8003c82: 1ad3 subs r3, r2, r3 8003c84: 00db lsls r3, r3, #3 8003c86: 3332 adds r3, #50 ; 0x32 8003c88: 4a81 ldr r2, [pc, #516] ; (8003e90 ) 8003c8a: fba2 2303 umull r2, r3, r2, r3 8003c8e: 095b lsrs r3, r3, #5 8003c90: f003 0207 and.w r2, r3, #7 8003c94: 687b ldr r3, [r7, #4] 8003c96: 681b ldr r3, [r3, #0] 8003c98: 440a add r2, r1 8003c9a: 609a str r2, [r3, #8] { pclk = HAL_RCC_GetPCLK1Freq(); huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); } #endif /* USART_CR1_OVER8 */ } 8003c9c: e0f1 b.n 8003e82 pclk = HAL_RCC_GetPCLK1Freq(); 8003c9e: f7fe ff0b bl 8002ab8 8003ca2: 60b8 str r0, [r7, #8] huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate); 8003ca4: 68ba ldr r2, [r7, #8] 8003ca6: 4613 mov r3, r2 8003ca8: 009b lsls r3, r3, #2 8003caa: 4413 add r3, r2 8003cac: 009a lsls r2, r3, #2 8003cae: 441a add r2, r3 8003cb0: 687b ldr r3, [r7, #4] 8003cb2: 685b ldr r3, [r3, #4] 8003cb4: 005b lsls r3, r3, #1 8003cb6: fbb2 f3f3 udiv r3, r2, r3 8003cba: 4a75 ldr r2, [pc, #468] ; (8003e90 ) 8003cbc: fba2 2303 umull r2, r3, r2, r3 8003cc0: 095b lsrs r3, r3, #5 8003cc2: 0119 lsls r1, r3, #4 8003cc4: 68ba ldr r2, [r7, #8] 8003cc6: 4613 mov r3, r2 8003cc8: 009b lsls r3, r3, #2 8003cca: 4413 add r3, r2 8003ccc: 009a lsls r2, r3, #2 8003cce: 441a add r2, r3 8003cd0: 687b ldr r3, [r7, #4] 8003cd2: 685b ldr r3, [r3, #4] 8003cd4: 005b lsls r3, r3, #1 8003cd6: fbb2 f2f3 udiv r2, r2, r3 8003cda: 4b6d ldr r3, [pc, #436] ; (8003e90 ) 8003cdc: fba3 0302 umull r0, r3, r3, r2 8003ce0: 095b lsrs r3, r3, #5 8003ce2: 2064 movs r0, #100 ; 0x64 8003ce4: fb00 f303 mul.w r3, r0, r3 8003ce8: 1ad3 subs r3, r2, r3 8003cea: 00db lsls r3, r3, #3 8003cec: 3332 adds r3, #50 ; 0x32 8003cee: 4a68 ldr r2, [pc, #416] ; (8003e90 ) 8003cf0: fba2 2303 umull r2, r3, r2, r3 8003cf4: 095b lsrs r3, r3, #5 8003cf6: 005b lsls r3, r3, #1 8003cf8: f403 73f8 and.w r3, r3, #496 ; 0x1f0 8003cfc: 4419 add r1, r3 8003cfe: 68ba ldr r2, [r7, #8] 8003d00: 4613 mov r3, r2 8003d02: 009b lsls r3, r3, #2 8003d04: 4413 add r3, r2 8003d06: 009a lsls r2, r3, #2 8003d08: 441a add r2, r3 8003d0a: 687b ldr r3, [r7, #4] 8003d0c: 685b ldr r3, [r3, #4] 8003d0e: 005b lsls r3, r3, #1 8003d10: fbb2 f2f3 udiv r2, r2, r3 8003d14: 4b5e ldr r3, [pc, #376] ; (8003e90 ) 8003d16: fba3 0302 umull r0, r3, r3, r2 8003d1a: 095b lsrs r3, r3, #5 8003d1c: 2064 movs r0, #100 ; 0x64 8003d1e: fb00 f303 mul.w r3, r0, r3 8003d22: 1ad3 subs r3, r2, r3 8003d24: 00db lsls r3, r3, #3 8003d26: 3332 adds r3, #50 ; 0x32 8003d28: 4a59 ldr r2, [pc, #356] ; (8003e90 ) 8003d2a: fba2 2303 umull r2, r3, r2, r3 8003d2e: 095b lsrs r3, r3, #5 8003d30: f003 0207 and.w r2, r3, #7 8003d34: 687b ldr r3, [r7, #4] 8003d36: 681b ldr r3, [r3, #0] 8003d38: 440a add r2, r1 8003d3a: 609a str r2, [r3, #8] } 8003d3c: e0a1 b.n 8003e82 if(huart->Instance == USART1) 8003d3e: 687b ldr r3, [r7, #4] 8003d40: 681b ldr r3, [r3, #0] 8003d42: 4a52 ldr r2, [pc, #328] ; (8003e8c ) 8003d44: 4293 cmp r3, r2 8003d46: d14e bne.n 8003de6 pclk = HAL_RCC_GetPCLK2Freq(); 8003d48: f7fe feca bl 8002ae0 8003d4c: 60b8 str r0, [r7, #8] huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); 8003d4e: 68ba ldr r2, [r7, #8] 8003d50: 4613 mov r3, r2 8003d52: 009b lsls r3, r3, #2 8003d54: 4413 add r3, r2 8003d56: 009a lsls r2, r3, #2 8003d58: 441a add r2, r3 8003d5a: 687b ldr r3, [r7, #4] 8003d5c: 685b ldr r3, [r3, #4] 8003d5e: 009b lsls r3, r3, #2 8003d60: fbb2 f3f3 udiv r3, r2, r3 8003d64: 4a4a ldr r2, [pc, #296] ; (8003e90 ) 8003d66: fba2 2303 umull r2, r3, r2, r3 8003d6a: 095b lsrs r3, r3, #5 8003d6c: 0119 lsls r1, r3, #4 8003d6e: 68ba ldr r2, [r7, #8] 8003d70: 4613 mov r3, r2 8003d72: 009b lsls r3, r3, #2 8003d74: 4413 add r3, r2 8003d76: 009a lsls r2, r3, #2 8003d78: 441a add r2, r3 8003d7a: 687b ldr r3, [r7, #4] 8003d7c: 685b ldr r3, [r3, #4] 8003d7e: 009b lsls r3, r3, #2 8003d80: fbb2 f2f3 udiv r2, r2, r3 8003d84: 4b42 ldr r3, [pc, #264] ; (8003e90 ) 8003d86: fba3 0302 umull r0, r3, r3, r2 8003d8a: 095b lsrs r3, r3, #5 8003d8c: 2064 movs r0, #100 ; 0x64 8003d8e: fb00 f303 mul.w r3, r0, r3 8003d92: 1ad3 subs r3, r2, r3 8003d94: 011b lsls r3, r3, #4 8003d96: 3332 adds r3, #50 ; 0x32 8003d98: 4a3d ldr r2, [pc, #244] ; (8003e90 ) 8003d9a: fba2 2303 umull r2, r3, r2, r3 8003d9e: 095b lsrs r3, r3, #5 8003da0: f003 03f0 and.w r3, r3, #240 ; 0xf0 8003da4: 4419 add r1, r3 8003da6: 68ba ldr r2, [r7, #8] 8003da8: 4613 mov r3, r2 8003daa: 009b lsls r3, r3, #2 8003dac: 4413 add r3, r2 8003dae: 009a lsls r2, r3, #2 8003db0: 441a add r2, r3 8003db2: 687b ldr r3, [r7, #4] 8003db4: 685b ldr r3, [r3, #4] 8003db6: 009b lsls r3, r3, #2 8003db8: fbb2 f2f3 udiv r2, r2, r3 8003dbc: 4b34 ldr r3, [pc, #208] ; (8003e90 ) 8003dbe: fba3 0302 umull r0, r3, r3, r2 8003dc2: 095b lsrs r3, r3, #5 8003dc4: 2064 movs r0, #100 ; 0x64 8003dc6: fb00 f303 mul.w r3, r0, r3 8003dca: 1ad3 subs r3, r2, r3 8003dcc: 011b lsls r3, r3, #4 8003dce: 3332 adds r3, #50 ; 0x32 8003dd0: 4a2f ldr r2, [pc, #188] ; (8003e90 ) 8003dd2: fba2 2303 umull r2, r3, r2, r3 8003dd6: 095b lsrs r3, r3, #5 8003dd8: f003 020f and.w r2, r3, #15 8003ddc: 687b ldr r3, [r7, #4] 8003dde: 681b ldr r3, [r3, #0] 8003de0: 440a add r2, r1 8003de2: 609a str r2, [r3, #8] } 8003de4: e04d b.n 8003e82 pclk = HAL_RCC_GetPCLK1Freq(); 8003de6: f7fe fe67 bl 8002ab8 8003dea: 60b8 str r0, [r7, #8] huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); 8003dec: 68ba ldr r2, [r7, #8] 8003dee: 4613 mov r3, r2 8003df0: 009b lsls r3, r3, #2 8003df2: 4413 add r3, r2 8003df4: 009a lsls r2, r3, #2 8003df6: 441a add r2, r3 8003df8: 687b ldr r3, [r7, #4] 8003dfa: 685b ldr r3, [r3, #4] 8003dfc: 009b lsls r3, r3, #2 8003dfe: fbb2 f3f3 udiv r3, r2, r3 8003e02: 4a23 ldr r2, [pc, #140] ; (8003e90 ) 8003e04: fba2 2303 umull r2, r3, r2, r3 8003e08: 095b lsrs r3, r3, #5 8003e0a: 0119 lsls r1, r3, #4 8003e0c: 68ba ldr r2, [r7, #8] 8003e0e: 4613 mov r3, r2 8003e10: 009b lsls r3, r3, #2 8003e12: 4413 add r3, r2 8003e14: 009a lsls r2, r3, #2 8003e16: 441a add r2, r3 8003e18: 687b ldr r3, [r7, #4] 8003e1a: 685b ldr r3, [r3, #4] 8003e1c: 009b lsls r3, r3, #2 8003e1e: fbb2 f2f3 udiv r2, r2, r3 8003e22: 4b1b ldr r3, [pc, #108] ; (8003e90 ) 8003e24: fba3 0302 umull r0, r3, r3, r2 8003e28: 095b lsrs r3, r3, #5 8003e2a: 2064 movs r0, #100 ; 0x64 8003e2c: fb00 f303 mul.w r3, r0, r3 8003e30: 1ad3 subs r3, r2, r3 8003e32: 011b lsls r3, r3, #4 8003e34: 3332 adds r3, #50 ; 0x32 8003e36: 4a16 ldr r2, [pc, #88] ; (8003e90 ) 8003e38: fba2 2303 umull r2, r3, r2, r3 8003e3c: 095b lsrs r3, r3, #5 8003e3e: f003 03f0 and.w r3, r3, #240 ; 0xf0 8003e42: 4419 add r1, r3 8003e44: 68ba ldr r2, [r7, #8] 8003e46: 4613 mov r3, r2 8003e48: 009b lsls r3, r3, #2 8003e4a: 4413 add r3, r2 8003e4c: 009a lsls r2, r3, #2 8003e4e: 441a add r2, r3 8003e50: 687b ldr r3, [r7, #4] 8003e52: 685b ldr r3, [r3, #4] 8003e54: 009b lsls r3, r3, #2 8003e56: fbb2 f2f3 udiv r2, r2, r3 8003e5a: 4b0d ldr r3, [pc, #52] ; (8003e90 ) 8003e5c: fba3 0302 umull r0, r3, r3, r2 8003e60: 095b lsrs r3, r3, #5 8003e62: 2064 movs r0, #100 ; 0x64 8003e64: fb00 f303 mul.w r3, r0, r3 8003e68: 1ad3 subs r3, r2, r3 8003e6a: 011b lsls r3, r3, #4 8003e6c: 3332 adds r3, #50 ; 0x32 8003e6e: 4a08 ldr r2, [pc, #32] ; (8003e90 ) 8003e70: fba2 2303 umull r2, r3, r2, r3 8003e74: 095b lsrs r3, r3, #5 8003e76: f003 020f and.w r2, r3, #15 8003e7a: 687b ldr r3, [r7, #4] 8003e7c: 681b ldr r3, [r3, #0] 8003e7e: 440a add r2, r1 8003e80: 609a str r2, [r3, #8] } 8003e82: bf00 nop 8003e84: 3710 adds r7, #16 8003e86: 46bd mov sp, r7 8003e88: bd80 pop {r7, pc} 8003e8a: bf00 nop 8003e8c: 40013800 .word 0x40013800 8003e90: 51eb851f .word 0x51eb851f 08003e94
: /** * @brief The application entry point. * @retval int */ int main(void) { 8003e94: b580 push {r7, lr} 8003e96: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 8003e98: f7fd f890 bl 8000fbc /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8003e9c: f000 f848 bl 8003f30 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8003ea0: f000 f9d2 bl 8004248 MX_DMA_Init(); 8003ea4: f000 f9b2 bl 800420c MX_ADC1_Init(); 8003ea8: f000 f8ca bl 8004040 MX_TIM6_Init(); 8003eac: f000 f924 bl 80040f8 MX_USART1_UART_Init(); 8003eb0: f000 f958 bl 8004164 MX_USART3_UART_Init(); 8003eb4: f000 f980 bl 80041b8 /* Initialize interrupts */ MX_NVIC_Init(); 8003eb8: f000 f88e bl 8003fd8 /* USER CODE BEGIN 2 */ HAL_TIM_Base_Start_IT(&htim6); 8003ebc: 4813 ldr r0, [pc, #76] ; (8003f0c ) 8003ebe: f7fe ff96 bl 8002dee setbuf(stdout, NULL); 8003ec2: 4b13 ldr r3, [pc, #76] ; (8003f10 ) 8003ec4: 681b ldr r3, [r3, #0] 8003ec6: 689b ldr r3, [r3, #8] 8003ec8: 2100 movs r1, #0 8003eca: 4618 mov r0, r3 8003ecc: f001 faca bl 8005464 InitUartQueue(&TerminalQueue); 8003ed0: 4810 ldr r0, [pc, #64] ; (8003f14 ) 8003ed2: f7fc ffa3 bl 8000e1c ADC_Initialize(); 8003ed6: f7fc feb9 bl 8000c4c #if 1 // PYJ.2020.05.06_BEGIN -- printf("****************************************\r\n"); 8003eda: 480f ldr r0, [pc, #60] ; (8003f18 ) 8003edc: f001 faba bl 8005454 printf("NESSLAB Project\r\n"); 8003ee0: 480e ldr r0, [pc, #56] ; (8003f1c ) 8003ee2: f001 fab7 bl 8005454 printf("Build at %s %s\r\n", __DATE__, __TIME__); 8003ee6: 4a0e ldr r2, [pc, #56] ; (8003f20 ) 8003ee8: 490e ldr r1, [pc, #56] ; (8003f24 ) 8003eea: 480f ldr r0, [pc, #60] ; (8003f28 ) 8003eec: f001 fa3e bl 800536c printf("Copyright (c) 2020. BLUECELL\r\n"); 8003ef0: 480e ldr r0, [pc, #56] ; (8003f2c ) 8003ef2: f001 faaf bl 8005454 printf("****************************************\r\n"); 8003ef6: 4808 ldr r0, [pc, #32] ; (8003f18 ) 8003ef8: f001 faac bl 8005454 /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) { Boot_LED_Toggle(); /*LED Check*/ 8003efc: f7fc ff76 bl 8000dec Uart_Check(); /*Usart Rx*/ 8003f00: f7fd f834 bl 8000f6c ADC_Check(); /*Det Calc + DL/UL Alarm Check Function*/ 8003f04: f7fc feb8 bl 8000c78 Boot_LED_Toggle(); /*LED Check*/ 8003f08: e7f8 b.n 8003efc 8003f0a: bf00 nop 8003f0c: 200005b8 .word 0x200005b8 8003f10: 2000000c .word 0x2000000c 8003f14: 2000029c .word 0x2000029c 8003f18: 080073a0 .word 0x080073a0 8003f1c: 080073cc .word 0x080073cc 8003f20: 080073e0 .word 0x080073e0 8003f24: 080073ec .word 0x080073ec 8003f28: 080073f8 .word 0x080073f8 8003f2c: 0800740c .word 0x0800740c 08003f30 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8003f30: b580 push {r7, lr} 8003f32: b092 sub sp, #72 ; 0x48 8003f34: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8003f36: f107 0320 add.w r3, r7, #32 8003f3a: 2228 movs r2, #40 ; 0x28 8003f3c: 2100 movs r1, #0 8003f3e: 4618 mov r0, r3 8003f40: f000 fdbc bl 8004abc RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8003f44: f107 030c add.w r3, r7, #12 8003f48: 2200 movs r2, #0 8003f4a: 601a str r2, [r3, #0] 8003f4c: 605a str r2, [r3, #4] 8003f4e: 609a str r2, [r3, #8] 8003f50: 60da str r2, [r3, #12] 8003f52: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 8003f54: 463b mov r3, r7 8003f56: 2200 movs r2, #0 8003f58: 601a str r2, [r3, #0] 8003f5a: 605a str r2, [r3, #4] 8003f5c: 609a str r2, [r3, #8] /** Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; 8003f5e: 2302 movs r3, #2 8003f60: 623b str r3, [r7, #32] RCC_OscInitStruct.HSIState = RCC_HSI_ON; 8003f62: 2301 movs r3, #1 8003f64: 633b str r3, [r7, #48] ; 0x30 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 8003f66: 2310 movs r3, #16 8003f68: 637b str r3, [r7, #52] ; 0x34 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 8003f6a: 2302 movs r3, #2 8003f6c: 63fb str r3, [r7, #60] ; 0x3c RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2; 8003f6e: 2300 movs r3, #0 8003f70: 643b str r3, [r7, #64] ; 0x40 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6; 8003f72: f44f 1380 mov.w r3, #1048576 ; 0x100000 8003f76: 647b str r3, [r7, #68] ; 0x44 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8003f78: f107 0320 add.w r3, r7, #32 8003f7c: 4618 mov r0, r3 8003f7e: f7fe f9f5 bl 800236c 8003f82: 4603 mov r3, r0 8003f84: 2b00 cmp r3, #0 8003f86: d001 beq.n 8003f8c { Error_Handler(); 8003f88: f000 fa16 bl 80043b8 } /** Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8003f8c: 230f movs r3, #15 8003f8e: 60fb str r3, [r7, #12] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 8003f90: 2302 movs r3, #2 8003f92: 613b str r3, [r7, #16] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 8003f94: 2300 movs r3, #0 8003f96: 617b str r3, [r7, #20] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 8003f98: 2300 movs r3, #0 8003f9a: 61bb str r3, [r7, #24] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 8003f9c: 2300 movs r3, #0 8003f9e: 61fb str r3, [r7, #28] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) 8003fa0: f107 030c add.w r3, r7, #12 8003fa4: 2100 movs r1, #0 8003fa6: 4618 mov r0, r3 8003fa8: f7fe fc60 bl 800286c 8003fac: 4603 mov r3, r0 8003fae: 2b00 cmp r3, #0 8003fb0: d001 beq.n 8003fb6 { Error_Handler(); 8003fb2: f000 fa01 bl 80043b8 } PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; 8003fb6: 2302 movs r3, #2 8003fb8: 603b str r3, [r7, #0] PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV2; 8003fba: 2300 movs r3, #0 8003fbc: 60bb str r3, [r7, #8] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 8003fbe: 463b mov r3, r7 8003fc0: 4618 mov r0, r3 8003fc2: f7fe fdeb bl 8002b9c 8003fc6: 4603 mov r3, r0 8003fc8: 2b00 cmp r3, #0 8003fca: d001 beq.n 8003fd0 { Error_Handler(); 8003fcc: f000 f9f4 bl 80043b8 } } 8003fd0: bf00 nop 8003fd2: 3748 adds r7, #72 ; 0x48 8003fd4: 46bd mov sp, r7 8003fd6: bd80 pop {r7, pc} 08003fd8 : /** * @brief NVIC Configuration. * @retval None */ static void MX_NVIC_Init(void) { 8003fd8: b580 push {r7, lr} 8003fda: af00 add r7, sp, #0 /* ADC1_IRQn interrupt configuration */ HAL_NVIC_SetPriority(ADC1_IRQn, 0, 0); 8003fdc: 2200 movs r2, #0 8003fde: 2100 movs r1, #0 8003fe0: 2012 movs r0, #18 8003fe2: f7fd fdaa bl 8001b3a HAL_NVIC_EnableIRQ(ADC1_IRQn); 8003fe6: 2012 movs r0, #18 8003fe8: f7fd fdc3 bl 8001b72 /* USART1_IRQn interrupt configuration */ HAL_NVIC_SetPriority(USART1_IRQn, 0, 0); 8003fec: 2200 movs r2, #0 8003fee: 2100 movs r1, #0 8003ff0: 2025 movs r0, #37 ; 0x25 8003ff2: f7fd fda2 bl 8001b3a HAL_NVIC_EnableIRQ(USART1_IRQn); 8003ff6: 2025 movs r0, #37 ; 0x25 8003ff8: f7fd fdbb bl 8001b72 /* USART3_IRQn interrupt configuration */ HAL_NVIC_SetPriority(USART3_IRQn, 0, 0); 8003ffc: 2200 movs r2, #0 8003ffe: 2100 movs r1, #0 8004000: 2027 movs r0, #39 ; 0x27 8004002: f7fd fd9a bl 8001b3a HAL_NVIC_EnableIRQ(USART3_IRQn); 8004006: 2027 movs r0, #39 ; 0x27 8004008: f7fd fdb3 bl 8001b72 /* TIM6_DAC_IRQn interrupt configuration */ HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 0, 0); 800400c: 2200 movs r2, #0 800400e: 2100 movs r1, #0 8004010: 2036 movs r0, #54 ; 0x36 8004012: f7fd fd92 bl 8001b3a HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); 8004016: 2036 movs r0, #54 ; 0x36 8004018: f7fd fdab bl 8001b72 /* DMA1_Channel2_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel2_IRQn, 0, 0); 800401c: 2200 movs r2, #0 800401e: 2100 movs r1, #0 8004020: 200c movs r0, #12 8004022: f7fd fd8a bl 8001b3a HAL_NVIC_EnableIRQ(DMA1_Channel2_IRQn); 8004026: 200c movs r0, #12 8004028: f7fd fda3 bl 8001b72 /* DMA1_Channel4_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel4_IRQn, 0, 0); 800402c: 2200 movs r2, #0 800402e: 2100 movs r1, #0 8004030: 200e movs r0, #14 8004032: f7fd fd82 bl 8001b3a HAL_NVIC_EnableIRQ(DMA1_Channel4_IRQn); 8004036: 200e movs r0, #14 8004038: f7fd fd9b bl 8001b72 } 800403c: bf00 nop 800403e: bd80 pop {r7, pc} 08004040 : * @brief ADC1 Initialization Function * @param None * @retval None */ static void MX_ADC1_Init(void) { 8004040: b580 push {r7, lr} 8004042: b084 sub sp, #16 8004044: af00 add r7, sp, #0 /* USER CODE BEGIN ADC1_Init 0 */ /* USER CODE END ADC1_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 8004046: 1d3b adds r3, r7, #4 8004048: 2200 movs r2, #0 800404a: 601a str r2, [r3, #0] 800404c: 605a str r2, [r3, #4] 800404e: 609a str r2, [r3, #8] /* USER CODE BEGIN ADC1_Init 1 */ /* USER CODE END ADC1_Init 1 */ /** Common config */ hadc1.Instance = ADC1; 8004050: 4b27 ldr r3, [pc, #156] ; (80040f0 ) 8004052: 4a28 ldr r2, [pc, #160] ; (80040f4 ) 8004054: 601a str r2, [r3, #0] hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; 8004056: 4b26 ldr r3, [pc, #152] ; (80040f0 ) 8004058: f44f 7280 mov.w r2, #256 ; 0x100 800405c: 609a str r2, [r3, #8] hadc1.Init.ContinuousConvMode = ENABLE; 800405e: 4b24 ldr r3, [pc, #144] ; (80040f0 ) 8004060: 2201 movs r2, #1 8004062: 731a strb r2, [r3, #12] hadc1.Init.DiscontinuousConvMode = DISABLE; 8004064: 4b22 ldr r3, [pc, #136] ; (80040f0 ) 8004066: 2200 movs r2, #0 8004068: 751a strb r2, [r3, #20] hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; 800406a: 4b21 ldr r3, [pc, #132] ; (80040f0 ) 800406c: f44f 2260 mov.w r2, #917504 ; 0xe0000 8004070: 61da str r2, [r3, #28] hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; 8004072: 4b1f ldr r3, [pc, #124] ; (80040f0 ) 8004074: 2200 movs r2, #0 8004076: 605a str r2, [r3, #4] hadc1.Init.NbrOfConversion = 3; 8004078: 4b1d ldr r3, [pc, #116] ; (80040f0 ) 800407a: 2203 movs r2, #3 800407c: 611a str r2, [r3, #16] if (HAL_ADC_Init(&hadc1) != HAL_OK) 800407e: 481c ldr r0, [pc, #112] ; (80040f0 ) 8004080: f7fc ffc6 bl 8001010 8004084: 4603 mov r3, r0 8004086: 2b00 cmp r3, #0 8004088: d001 beq.n 800408e { Error_Handler(); 800408a: f000 f995 bl 80043b8 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_0; 800408e: 2300 movs r3, #0 8004090: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_1; 8004092: 2301 movs r3, #1 8004094: 60bb str r3, [r7, #8] sConfig.SamplingTime = ADC_SAMPLETIME_239CYCLES_5; 8004096: 2307 movs r3, #7 8004098: 60fb str r3, [r7, #12] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 800409a: 1d3b adds r3, r7, #4 800409c: 4619 mov r1, r3 800409e: 4814 ldr r0, [pc, #80] ; (80040f0 ) 80040a0: f7fd fa06 bl 80014b0 80040a4: 4603 mov r3, r0 80040a6: 2b00 cmp r3, #0 80040a8: d001 beq.n 80040ae { Error_Handler(); 80040aa: f000 f985 bl 80043b8 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_1; 80040ae: 2301 movs r3, #1 80040b0: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_2; 80040b2: 2302 movs r3, #2 80040b4: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 80040b6: 1d3b adds r3, r7, #4 80040b8: 4619 mov r1, r3 80040ba: 480d ldr r0, [pc, #52] ; (80040f0 ) 80040bc: f7fd f9f8 bl 80014b0 80040c0: 4603 mov r3, r0 80040c2: 2b00 cmp r3, #0 80040c4: d001 beq.n 80040ca { Error_Handler(); 80040c6: f000 f977 bl 80043b8 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_3; 80040ca: 2303 movs r3, #3 80040cc: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_3; 80040ce: 2303 movs r3, #3 80040d0: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 80040d2: 1d3b adds r3, r7, #4 80040d4: 4619 mov r1, r3 80040d6: 4806 ldr r0, [pc, #24] ; (80040f0 ) 80040d8: f7fd f9ea bl 80014b0 80040dc: 4603 mov r3, r0 80040de: 2b00 cmp r3, #0 80040e0: d001 beq.n 80040e6 { Error_Handler(); 80040e2: f000 f969 bl 80043b8 } /* USER CODE BEGIN ADC1_Init 2 */ /* USER CODE END ADC1_Init 2 */ } 80040e6: bf00 nop 80040e8: 3710 adds r7, #16 80040ea: 46bd mov sp, r7 80040ec: bd80 pop {r7, pc} 80040ee: bf00 nop 80040f0: 20000504 .word 0x20000504 80040f4: 40012400 .word 0x40012400 080040f8 : * @brief TIM6 Initialization Function * @param None * @retval None */ static void MX_TIM6_Init(void) { 80040f8: b580 push {r7, lr} 80040fa: b082 sub sp, #8 80040fc: af00 add r7, sp, #0 /* USER CODE BEGIN TIM6_Init 0 */ /* USER CODE END TIM6_Init 0 */ TIM_MasterConfigTypeDef sMasterConfig = {0}; 80040fe: 463b mov r3, r7 8004100: 2200 movs r2, #0 8004102: 601a str r2, [r3, #0] 8004104: 605a str r2, [r3, #4] /* USER CODE BEGIN TIM6_Init 1 */ /* USER CODE END TIM6_Init 1 */ htim6.Instance = TIM6; 8004106: 4b15 ldr r3, [pc, #84] ; (800415c ) 8004108: 4a15 ldr r2, [pc, #84] ; (8004160 ) 800410a: 601a str r2, [r3, #0] htim6.Init.Prescaler = 2400-1; 800410c: 4b13 ldr r3, [pc, #76] ; (800415c ) 800410e: f640 125f movw r2, #2399 ; 0x95f 8004112: 605a str r2, [r3, #4] htim6.Init.CounterMode = TIM_COUNTERMODE_UP; 8004114: 4b11 ldr r3, [pc, #68] ; (800415c ) 8004116: 2200 movs r2, #0 8004118: 609a str r2, [r3, #8] htim6.Init.Period = 10; 800411a: 4b10 ldr r3, [pc, #64] ; (800415c ) 800411c: 220a movs r2, #10 800411e: 60da str r2, [r3, #12] htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8004120: 4b0e ldr r3, [pc, #56] ; (800415c ) 8004122: 2200 movs r2, #0 8004124: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim6) != HAL_OK) 8004126: 480d ldr r0, [pc, #52] ; (800415c ) 8004128: f7fe fe36 bl 8002d98 800412c: 4603 mov r3, r0 800412e: 2b00 cmp r3, #0 8004130: d001 beq.n 8004136 { Error_Handler(); 8004132: f000 f941 bl 80043b8 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8004136: 2300 movs r3, #0 8004138: 603b str r3, [r7, #0] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800413a: 2300 movs r3, #0 800413c: 607b str r3, [r7, #4] if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK) 800413e: 463b mov r3, r7 8004140: 4619 mov r1, r3 8004142: 4806 ldr r0, [pc, #24] ; (800415c ) 8004144: f7ff f822 bl 800318c 8004148: 4603 mov r3, r0 800414a: 2b00 cmp r3, #0 800414c: d001 beq.n 8004152 { Error_Handler(); 800414e: f000 f933 bl 80043b8 } /* USER CODE BEGIN TIM6_Init 2 */ /* USER CODE END TIM6_Init 2 */ } 8004152: bf00 nop 8004154: 3708 adds r7, #8 8004156: 46bd mov sp, r7 8004158: bd80 pop {r7, pc} 800415a: bf00 nop 800415c: 200005b8 .word 0x200005b8 8004160: 40001000 .word 0x40001000 08004164 : * @brief USART1 Initialization Function * @param None * @retval None */ static void MX_USART1_UART_Init(void) { 8004164: b580 push {r7, lr} 8004166: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 8004168: 4b11 ldr r3, [pc, #68] ; (80041b0 ) 800416a: 4a12 ldr r2, [pc, #72] ; (80041b4 ) 800416c: 601a str r2, [r3, #0] huart1.Init.BaudRate = 57600; 800416e: 4b10 ldr r3, [pc, #64] ; (80041b0 ) 8004170: f44f 4261 mov.w r2, #57600 ; 0xe100 8004174: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 8004176: 4b0e ldr r3, [pc, #56] ; (80041b0 ) 8004178: 2200 movs r2, #0 800417a: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 800417c: 4b0c ldr r3, [pc, #48] ; (80041b0 ) 800417e: 2200 movs r2, #0 8004180: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 8004182: 4b0b ldr r3, [pc, #44] ; (80041b0 ) 8004184: 2200 movs r2, #0 8004186: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 8004188: 4b09 ldr r3, [pc, #36] ; (80041b0 ) 800418a: 220c movs r2, #12 800418c: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800418e: 4b08 ldr r3, [pc, #32] ; (80041b0 ) 8004190: 2200 movs r2, #0 8004192: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 8004194: 4b06 ldr r3, [pc, #24] ; (80041b0 ) 8004196: 2200 movs r2, #0 8004198: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart1) != HAL_OK) 800419a: 4805 ldr r0, [pc, #20] ; (80041b0 ) 800419c: f7ff f84c bl 8003238 80041a0: 4603 mov r3, r0 80041a2: 2b00 cmp r3, #0 80041a4: d001 beq.n 80041aa { Error_Handler(); 80041a6: f000 f907 bl 80043b8 } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 80041aa: bf00 nop 80041ac: bd80 pop {r7, pc} 80041ae: bf00 nop 80041b0: 20000534 .word 0x20000534 80041b4: 40013800 .word 0x40013800 080041b8 : * @brief USART3 Initialization Function * @param None * @retval None */ static void MX_USART3_UART_Init(void) { 80041b8: b580 push {r7, lr} 80041ba: af00 add r7, sp, #0 /* USER CODE END USART3_Init 0 */ /* USER CODE BEGIN USART3_Init 1 */ /* USER CODE END USART3_Init 1 */ huart3.Instance = USART3; 80041bc: 4b11 ldr r3, [pc, #68] ; (8004204 ) 80041be: 4a12 ldr r2, [pc, #72] ; (8004208 ) 80041c0: 601a str r2, [r3, #0] huart3.Init.BaudRate = 57600; 80041c2: 4b10 ldr r3, [pc, #64] ; (8004204 ) 80041c4: f44f 4261 mov.w r2, #57600 ; 0xe100 80041c8: 605a str r2, [r3, #4] huart3.Init.WordLength = UART_WORDLENGTH_8B; 80041ca: 4b0e ldr r3, [pc, #56] ; (8004204 ) 80041cc: 2200 movs r2, #0 80041ce: 609a str r2, [r3, #8] huart3.Init.StopBits = UART_STOPBITS_1; 80041d0: 4b0c ldr r3, [pc, #48] ; (8004204 ) 80041d2: 2200 movs r2, #0 80041d4: 60da str r2, [r3, #12] huart3.Init.Parity = UART_PARITY_NONE; 80041d6: 4b0b ldr r3, [pc, #44] ; (8004204 ) 80041d8: 2200 movs r2, #0 80041da: 611a str r2, [r3, #16] huart3.Init.Mode = UART_MODE_TX_RX; 80041dc: 4b09 ldr r3, [pc, #36] ; (8004204 ) 80041de: 220c movs r2, #12 80041e0: 615a str r2, [r3, #20] huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE; 80041e2: 4b08 ldr r3, [pc, #32] ; (8004204 ) 80041e4: 2200 movs r2, #0 80041e6: 619a str r2, [r3, #24] huart3.Init.OverSampling = UART_OVERSAMPLING_16; 80041e8: 4b06 ldr r3, [pc, #24] ; (8004204 ) 80041ea: 2200 movs r2, #0 80041ec: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart3) != HAL_OK) 80041ee: 4805 ldr r0, [pc, #20] ; (8004204 ) 80041f0: f7ff f822 bl 8003238 80041f4: 4603 mov r3, r0 80041f6: 2b00 cmp r3, #0 80041f8: d001 beq.n 80041fe { Error_Handler(); 80041fa: f000 f8dd bl 80043b8 } /* USER CODE BEGIN USART3_Init 2 */ /* USER CODE END USART3_Init 2 */ } 80041fe: bf00 nop 8004200: bd80 pop {r7, pc} 8004202: bf00 nop 8004204: 2000043c .word 0x2000043c 8004208: 40004800 .word 0x40004800 0800420c : /** * Enable DMA controller clock */ static void MX_DMA_Init(void) { 800420c: b580 push {r7, lr} 800420e: b082 sub sp, #8 8004210: af00 add r7, sp, #0 /* DMA controller clock enable */ __HAL_RCC_DMA1_CLK_ENABLE(); 8004212: 4b0c ldr r3, [pc, #48] ; (8004244 ) 8004214: 695b ldr r3, [r3, #20] 8004216: 4a0b ldr r2, [pc, #44] ; (8004244 ) 8004218: f043 0301 orr.w r3, r3, #1 800421c: 6153 str r3, [r2, #20] 800421e: 4b09 ldr r3, [pc, #36] ; (8004244 ) 8004220: 695b ldr r3, [r3, #20] 8004222: f003 0301 and.w r3, r3, #1 8004226: 607b str r3, [r7, #4] 8004228: 687b ldr r3, [r7, #4] /* DMA interrupt init */ /* DMA1_Channel1_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0); 800422a: 2200 movs r2, #0 800422c: 2100 movs r1, #0 800422e: 200b movs r0, #11 8004230: f7fd fc83 bl 8001b3a HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn); 8004234: 200b movs r0, #11 8004236: f7fd fc9c bl 8001b72 } 800423a: bf00 nop 800423c: 3708 adds r7, #8 800423e: 46bd mov sp, r7 8004240: bd80 pop {r7, pc} 8004242: bf00 nop 8004244: 40021000 .word 0x40021000 08004248 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 8004248: b580 push {r7, lr} 800424a: b088 sub sp, #32 800424c: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 800424e: f107 0310 add.w r3, r7, #16 8004252: 2200 movs r2, #0 8004254: 601a str r2, [r3, #0] 8004256: 605a str r2, [r3, #4] 8004258: 609a str r2, [r3, #8] 800425a: 60da str r2, [r3, #12] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); 800425c: 4b40 ldr r3, [pc, #256] ; (8004360 ) 800425e: 699b ldr r3, [r3, #24] 8004260: 4a3f ldr r2, [pc, #252] ; (8004360 ) 8004262: f043 0310 orr.w r3, r3, #16 8004266: 6193 str r3, [r2, #24] 8004268: 4b3d ldr r3, [pc, #244] ; (8004360 ) 800426a: 699b ldr r3, [r3, #24] 800426c: f003 0310 and.w r3, r3, #16 8004270: 60fb str r3, [r7, #12] 8004272: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 8004274: 4b3a ldr r3, [pc, #232] ; (8004360 ) 8004276: 699b ldr r3, [r3, #24] 8004278: 4a39 ldr r2, [pc, #228] ; (8004360 ) 800427a: f043 0304 orr.w r3, r3, #4 800427e: 6193 str r3, [r2, #24] 8004280: 4b37 ldr r3, [pc, #220] ; (8004360 ) 8004282: 699b ldr r3, [r3, #24] 8004284: f003 0304 and.w r3, r3, #4 8004288: 60bb str r3, [r7, #8] 800428a: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOB_CLK_ENABLE(); 800428c: 4b34 ldr r3, [pc, #208] ; (8004360 ) 800428e: 699b ldr r3, [r3, #24] 8004290: 4a33 ldr r2, [pc, #204] ; (8004360 ) 8004292: f043 0308 orr.w r3, r3, #8 8004296: 6193 str r3, [r2, #24] 8004298: 4b31 ldr r3, [pc, #196] ; (8004360 ) 800429a: 699b ldr r3, [r3, #24] 800429c: f003 0308 and.w r3, r3, #8 80042a0: 607b str r3, [r7, #4] 80042a2: 687b ldr r3, [r7, #4] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(BOOT_LED_GPIO_Port, BOOT_LED_Pin, GPIO_PIN_RESET); 80042a4: 2200 movs r2, #0 80042a6: f44f 4100 mov.w r1, #32768 ; 0x8000 80042aa: 482e ldr r0, [pc, #184] ; (8004364 ) 80042ac: f7fe f82e bl 800230c /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOA, PAU_RESERVED0_Pin|PAU_RESERVED1_Pin|AMP_EN_Pin, GPIO_PIN_RESET); 80042b0: 2200 movs r2, #0 80042b2: f44f 71e0 mov.w r1, #448 ; 0x1c0 80042b6: 482c ldr r0, [pc, #176] ; (8004368 ) 80042b8: f7fe f828 bl 800230c /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOB, PAU_RESERVED3_Pin|PAU_RESERVED2_Pin|PAU_RESET_Pin, GPIO_PIN_RESET); 80042bc: 2200 movs r2, #0 80042be: f244 0103 movw r1, #16387 ; 0x4003 80042c2: 482a ldr r0, [pc, #168] ; (800436c ) 80042c4: f7fe f822 bl 800230c /*Configure GPIO pin : BOOT_LED_Pin */ GPIO_InitStruct.Pin = BOOT_LED_Pin; 80042c8: f44f 4300 mov.w r3, #32768 ; 0x8000 80042cc: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80042ce: 2301 movs r3, #1 80042d0: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 80042d2: 2300 movs r3, #0 80042d4: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80042d6: 2302 movs r3, #2 80042d8: 61fb str r3, [r7, #28] HAL_GPIO_Init(BOOT_LED_GPIO_Port, &GPIO_InitStruct); 80042da: f107 0310 add.w r3, r7, #16 80042de: 4619 mov r1, r3 80042e0: 4820 ldr r0, [pc, #128] ; (8004364 ) 80042e2: f7fd feb9 bl 8002058 /*Configure GPIO pins : DC_FAIL_ALARM_Pin OVER_INPUT_ALARM_Pin OVER_TEMP_ALARM_Pin */ GPIO_InitStruct.Pin = DC_FAIL_ALARM_Pin|OVER_INPUT_ALARM_Pin|OVER_TEMP_ALARM_Pin; 80042e6: f641 0304 movw r3, #6148 ; 0x1804 80042ea: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80042ec: 2300 movs r3, #0 80042ee: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 80042f0: 2300 movs r3, #0 80042f2: 61bb str r3, [r7, #24] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80042f4: f107 0310 add.w r3, r7, #16 80042f8: 4619 mov r1, r3 80042fa: 481b ldr r0, [pc, #108] ; (8004368 ) 80042fc: f7fd feac bl 8002058 /*Configure GPIO pins : PAU_RESERVED0_Pin PAU_RESERVED1_Pin AMP_EN_Pin */ GPIO_InitStruct.Pin = PAU_RESERVED0_Pin|PAU_RESERVED1_Pin|AMP_EN_Pin; 8004300: f44f 73e0 mov.w r3, #448 ; 0x1c0 8004304: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8004306: 2301 movs r3, #1 8004308: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 800430a: 2300 movs r3, #0 800430c: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800430e: 2302 movs r3, #2 8004310: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8004312: f107 0310 add.w r3, r7, #16 8004316: 4619 mov r1, r3 8004318: 4813 ldr r0, [pc, #76] ; (8004368 ) 800431a: f7fd fe9d bl 8002058 /*Configure GPIO pins : PAU_RESERVED3_Pin PAU_RESERVED2_Pin PAU_RESET_Pin */ GPIO_InitStruct.Pin = PAU_RESERVED3_Pin|PAU_RESERVED2_Pin|PAU_RESET_Pin; 800431e: f244 0303 movw r3, #16387 ; 0x4003 8004322: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8004324: 2301 movs r3, #1 8004326: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 8004328: 2300 movs r3, #0 800432a: 61bb str r3, [r7, #24] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800432c: 2302 movs r3, #2 800432e: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8004330: f107 0310 add.w r3, r7, #16 8004334: 4619 mov r1, r3 8004336: 480d ldr r0, [pc, #52] ; (800436c ) 8004338: f7fd fe8e bl 8002058 /*Configure GPIO pins : OVER_POWER_ALARM_Pin VSWR_ALARM_Pin PAU_EN_Pin ALC_ALARM_Pin */ GPIO_InitStruct.Pin = OVER_POWER_ALARM_Pin|VSWR_ALARM_Pin|PAU_EN_Pin|ALC_ALARM_Pin; 800433c: f24b 0308 movw r3, #45064 ; 0xb008 8004340: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8004342: 2300 movs r3, #0 8004344: 617b str r3, [r7, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 8004346: 2300 movs r3, #0 8004348: 61bb str r3, [r7, #24] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800434a: f107 0310 add.w r3, r7, #16 800434e: 4619 mov r1, r3 8004350: 4806 ldr r0, [pc, #24] ; (800436c ) 8004352: f7fd fe81 bl 8002058 } 8004356: bf00 nop 8004358: 3720 adds r7, #32 800435a: 46bd mov sp, r7 800435c: bd80 pop {r7, pc} 800435e: bf00 nop 8004360: 40021000 .word 0x40021000 8004364: 40011000 .word 0x40011000 8004368: 40010800 .word 0x40010800 800436c: 40010c00 .word 0x40010c00 08004370 : * a global variable "uwTick" used as application time base. * @param htim : TIM handle * @retval None */ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { 8004370: b580 push {r7, lr} 8004372: b082 sub sp, #8 8004374: af00 add r7, sp, #0 8004376: 6078 str r0, [r7, #4] /* USER CODE BEGIN Callback 0 */ /* USER CODE END Callback 0 */ if (htim->Instance == TIM2) { 8004378: 687b ldr r3, [r7, #4] 800437a: 681b ldr r3, [r3, #0] 800437c: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 8004380: d101 bne.n 8004386 HAL_IncTick(); 8004382: f7fc fe29 bl 8000fd8 } /* USER CODE BEGIN Callback 1 */ if(htim->Instance == TIM6){ 8004386: 687b ldr r3, [r7, #4] 8004388: 681b ldr r3, [r3, #0] 800438a: 4a08 ldr r2, [pc, #32] ; (80043ac ) 800438c: 4293 cmp r3, r2 800438e: d109 bne.n 80043a4 UartRxTimerCnt++; 8004390: 4b07 ldr r3, [pc, #28] ; (80043b0 ) 8004392: 681b ldr r3, [r3, #0] 8004394: 3301 adds r3, #1 8004396: 4a06 ldr r2, [pc, #24] ; (80043b0 ) 8004398: 6013 str r3, [r2, #0] LED_TimerCnt++; 800439a: 4b06 ldr r3, [pc, #24] ; (80043b4 ) 800439c: 681b ldr r3, [r3, #0] 800439e: 3301 adds r3, #1 80043a0: 4a04 ldr r2, [pc, #16] ; (80043b4 ) 80043a2: 6013 str r3, [r2, #0] } /* USER CODE END Callback 1 */ } 80043a4: bf00 nop 80043a6: 3708 adds r7, #8 80043a8: 46bd mov sp, r7 80043aa: bd80 pop {r7, pc} 80043ac: 40001000 .word 0x40001000 80043b0: 20000204 .word 0x20000204 80043b4: 200001fc .word 0x200001fc 080043b8 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 80043b8: b480 push {r7} 80043ba: af00 add r7, sp, #0 /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ /* USER CODE END Error_Handler_Debug */ } 80043bc: bf00 nop 80043be: 46bd mov sp, r7 80043c0: bc80 pop {r7} 80043c2: 4770 bx lr 080043c4 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 80043c4: b480 push {r7} 80043c6: b085 sub sp, #20 80043c8: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_AFIO_CLK_ENABLE(); 80043ca: 4b15 ldr r3, [pc, #84] ; (8004420 ) 80043cc: 699b ldr r3, [r3, #24] 80043ce: 4a14 ldr r2, [pc, #80] ; (8004420 ) 80043d0: f043 0301 orr.w r3, r3, #1 80043d4: 6193 str r3, [r2, #24] 80043d6: 4b12 ldr r3, [pc, #72] ; (8004420 ) 80043d8: 699b ldr r3, [r3, #24] 80043da: f003 0301 and.w r3, r3, #1 80043de: 60bb str r3, [r7, #8] 80043e0: 68bb ldr r3, [r7, #8] __HAL_RCC_PWR_CLK_ENABLE(); 80043e2: 4b0f ldr r3, [pc, #60] ; (8004420 ) 80043e4: 69db ldr r3, [r3, #28] 80043e6: 4a0e ldr r2, [pc, #56] ; (8004420 ) 80043e8: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 80043ec: 61d3 str r3, [r2, #28] 80043ee: 4b0c ldr r3, [pc, #48] ; (8004420 ) 80043f0: 69db ldr r3, [r3, #28] 80043f2: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 80043f6: 607b str r3, [r7, #4] 80043f8: 687b ldr r3, [r7, #4] /* System interrupt init*/ /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled */ __HAL_AFIO_REMAP_SWJ_NOJTAG(); 80043fa: 4b0a ldr r3, [pc, #40] ; (8004424 ) 80043fc: 685b ldr r3, [r3, #4] 80043fe: 60fb str r3, [r7, #12] 8004400: 68fb ldr r3, [r7, #12] 8004402: f023 63e0 bic.w r3, r3, #117440512 ; 0x7000000 8004406: 60fb str r3, [r7, #12] 8004408: 68fb ldr r3, [r7, #12] 800440a: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000 800440e: 60fb str r3, [r7, #12] 8004410: 4a04 ldr r2, [pc, #16] ; (8004424 ) 8004412: 68fb ldr r3, [r7, #12] 8004414: 6053 str r3, [r2, #4] /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8004416: bf00 nop 8004418: 3714 adds r7, #20 800441a: 46bd mov sp, r7 800441c: bc80 pop {r7} 800441e: 4770 bx lr 8004420: 40021000 .word 0x40021000 8004424: 40010000 .word 0x40010000 08004428 : * This function configures the hardware resources used in this example * @param hadc: ADC handle pointer * @retval None */ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) { 8004428: b580 push {r7, lr} 800442a: b088 sub sp, #32 800442c: af00 add r7, sp, #0 800442e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8004430: f107 0310 add.w r3, r7, #16 8004434: 2200 movs r2, #0 8004436: 601a str r2, [r3, #0] 8004438: 605a str r2, [r3, #4] 800443a: 609a str r2, [r3, #8] 800443c: 60da str r2, [r3, #12] if(hadc->Instance==ADC1) 800443e: 687b ldr r3, [r7, #4] 8004440: 681b ldr r3, [r3, #0] 8004442: 4a28 ldr r2, [pc, #160] ; (80044e4 ) 8004444: 4293 cmp r3, r2 8004446: d149 bne.n 80044dc { /* USER CODE BEGIN ADC1_MspInit 0 */ /* USER CODE END ADC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_ADC1_CLK_ENABLE(); 8004448: 4b27 ldr r3, [pc, #156] ; (80044e8 ) 800444a: 699b ldr r3, [r3, #24] 800444c: 4a26 ldr r2, [pc, #152] ; (80044e8 ) 800444e: f443 7300 orr.w r3, r3, #512 ; 0x200 8004452: 6193 str r3, [r2, #24] 8004454: 4b24 ldr r3, [pc, #144] ; (80044e8 ) 8004456: 699b ldr r3, [r3, #24] 8004458: f403 7300 and.w r3, r3, #512 ; 0x200 800445c: 60fb str r3, [r7, #12] 800445e: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 8004460: 4b21 ldr r3, [pc, #132] ; (80044e8 ) 8004462: 699b ldr r3, [r3, #24] 8004464: 4a20 ldr r2, [pc, #128] ; (80044e8 ) 8004466: f043 0304 orr.w r3, r3, #4 800446a: 6193 str r3, [r2, #24] 800446c: 4b1e ldr r3, [pc, #120] ; (80044e8 ) 800446e: 699b ldr r3, [r3, #24] 8004470: f003 0304 and.w r3, r3, #4 8004474: 60bb str r3, [r7, #8] 8004476: 68bb ldr r3, [r7, #8] /**ADC1 GPIO Configuration PA0-WKUP ------> ADC1_IN0 PA1 ------> ADC1_IN1 PA3 ------> ADC1_IN3 */ GPIO_InitStruct.Pin = DL_TX_DET_Pin|DL_RX_DET_Pin|PAU_TEMP_Pin; 8004478: 230b movs r3, #11 800447a: 613b str r3, [r7, #16] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 800447c: 2303 movs r3, #3 800447e: 617b str r3, [r7, #20] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8004480: f107 0310 add.w r3, r7, #16 8004484: 4619 mov r1, r3 8004486: 4819 ldr r0, [pc, #100] ; (80044ec ) 8004488: f7fd fde6 bl 8002058 /* ADC1 DMA Init */ /* ADC1 Init */ hdma_adc1.Instance = DMA1_Channel1; 800448c: 4b18 ldr r3, [pc, #96] ; (80044f0 ) 800448e: 4a19 ldr r2, [pc, #100] ; (80044f4 ) 8004490: 601a str r2, [r3, #0] hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY; 8004492: 4b17 ldr r3, [pc, #92] ; (80044f0 ) 8004494: 2200 movs r2, #0 8004496: 605a str r2, [r3, #4] hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE; 8004498: 4b15 ldr r3, [pc, #84] ; (80044f0 ) 800449a: 2200 movs r2, #0 800449c: 609a str r2, [r3, #8] hdma_adc1.Init.MemInc = DMA_MINC_ENABLE; 800449e: 4b14 ldr r3, [pc, #80] ; (80044f0 ) 80044a0: 2280 movs r2, #128 ; 0x80 80044a2: 60da str r2, [r3, #12] hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 80044a4: 4b12 ldr r3, [pc, #72] ; (80044f0 ) 80044a6: f44f 7280 mov.w r2, #256 ; 0x100 80044aa: 611a str r2, [r3, #16] hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 80044ac: 4b10 ldr r3, [pc, #64] ; (80044f0 ) 80044ae: f44f 6280 mov.w r2, #1024 ; 0x400 80044b2: 615a str r2, [r3, #20] hdma_adc1.Init.Mode = DMA_CIRCULAR; 80044b4: 4b0e ldr r3, [pc, #56] ; (80044f0 ) 80044b6: 2220 movs r2, #32 80044b8: 619a str r2, [r3, #24] hdma_adc1.Init.Priority = DMA_PRIORITY_LOW; 80044ba: 4b0d ldr r3, [pc, #52] ; (80044f0 ) 80044bc: 2200 movs r2, #0 80044be: 61da str r2, [r3, #28] if (HAL_DMA_Init(&hdma_adc1) != HAL_OK) 80044c0: 480b ldr r0, [pc, #44] ; (80044f0 ) 80044c2: f7fd fb65 bl 8001b90 80044c6: 4603 mov r3, r0 80044c8: 2b00 cmp r3, #0 80044ca: d001 beq.n 80044d0 { Error_Handler(); 80044cc: f7ff ff74 bl 80043b8 } __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc1); 80044d0: 687b ldr r3, [r7, #4] 80044d2: 4a07 ldr r2, [pc, #28] ; (80044f0 ) 80044d4: 621a str r2, [r3, #32] 80044d6: 4a06 ldr r2, [pc, #24] ; (80044f0 ) 80044d8: 687b ldr r3, [r7, #4] 80044da: 6253 str r3, [r2, #36] ; 0x24 /* USER CODE BEGIN ADC1_MspInit 1 */ /* USER CODE END ADC1_MspInit 1 */ } } 80044dc: bf00 nop 80044de: 3720 adds r7, #32 80044e0: 46bd mov sp, r7 80044e2: bd80 pop {r7, pc} 80044e4: 40012400 .word 0x40012400 80044e8: 40021000 .word 0x40021000 80044ec: 40010800 .word 0x40010800 80044f0: 20000574 .word 0x20000574 80044f4: 40020008 .word 0x40020008 080044f8 : * This function configures the hardware resources used in this example * @param htim_base: TIM_Base handle pointer * @retval None */ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) { 80044f8: b480 push {r7} 80044fa: b085 sub sp, #20 80044fc: af00 add r7, sp, #0 80044fe: 6078 str r0, [r7, #4] if(htim_base->Instance==TIM6) 8004500: 687b ldr r3, [r7, #4] 8004502: 681b ldr r3, [r3, #0] 8004504: 4a09 ldr r2, [pc, #36] ; (800452c ) 8004506: 4293 cmp r3, r2 8004508: d10b bne.n 8004522 { /* USER CODE BEGIN TIM6_MspInit 0 */ /* USER CODE END TIM6_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM6_CLK_ENABLE(); 800450a: 4b09 ldr r3, [pc, #36] ; (8004530 ) 800450c: 69db ldr r3, [r3, #28] 800450e: 4a08 ldr r2, [pc, #32] ; (8004530 ) 8004510: f043 0310 orr.w r3, r3, #16 8004514: 61d3 str r3, [r2, #28] 8004516: 4b06 ldr r3, [pc, #24] ; (8004530 ) 8004518: 69db ldr r3, [r3, #28] 800451a: f003 0310 and.w r3, r3, #16 800451e: 60fb str r3, [r7, #12] 8004520: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN TIM6_MspInit 1 */ /* USER CODE END TIM6_MspInit 1 */ } } 8004522: bf00 nop 8004524: 3714 adds r7, #20 8004526: 46bd mov sp, r7 8004528: bc80 pop {r7} 800452a: 4770 bx lr 800452c: 40001000 .word 0x40001000 8004530: 40021000 .word 0x40021000 08004534 : * This function configures the hardware resources used in this example * @param huart: UART handle pointer * @retval None */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { 8004534: b580 push {r7, lr} 8004536: b08a sub sp, #40 ; 0x28 8004538: af00 add r7, sp, #0 800453a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800453c: f107 0318 add.w r3, r7, #24 8004540: 2200 movs r2, #0 8004542: 601a str r2, [r3, #0] 8004544: 605a str r2, [r3, #4] 8004546: 609a str r2, [r3, #8] 8004548: 60da str r2, [r3, #12] if(huart->Instance==USART1) 800454a: 687b ldr r3, [r7, #4] 800454c: 681b ldr r3, [r3, #0] 800454e: 4a5e ldr r2, [pc, #376] ; (80046c8 ) 8004550: 4293 cmp r3, r2 8004552: d158 bne.n 8004606 { /* USER CODE BEGIN USART1_MspInit 0 */ /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); 8004554: 4b5d ldr r3, [pc, #372] ; (80046cc ) 8004556: 699b ldr r3, [r3, #24] 8004558: 4a5c ldr r2, [pc, #368] ; (80046cc ) 800455a: f443 4380 orr.w r3, r3, #16384 ; 0x4000 800455e: 6193 str r3, [r2, #24] 8004560: 4b5a ldr r3, [pc, #360] ; (80046cc ) 8004562: 699b ldr r3, [r3, #24] 8004564: f403 4380 and.w r3, r3, #16384 ; 0x4000 8004568: 617b str r3, [r7, #20] 800456a: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 800456c: 4b57 ldr r3, [pc, #348] ; (80046cc ) 800456e: 699b ldr r3, [r3, #24] 8004570: 4a56 ldr r2, [pc, #344] ; (80046cc ) 8004572: f043 0304 orr.w r3, r3, #4 8004576: 6193 str r3, [r2, #24] 8004578: 4b54 ldr r3, [pc, #336] ; (80046cc ) 800457a: 699b ldr r3, [r3, #24] 800457c: f003 0304 and.w r3, r3, #4 8004580: 613b str r3, [r7, #16] 8004582: 693b ldr r3, [r7, #16] /**USART1 GPIO Configuration PA9 ------> USART1_TX PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_9; 8004584: f44f 7300 mov.w r3, #512 ; 0x200 8004588: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800458a: 2302 movs r3, #2 800458c: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800458e: 2303 movs r3, #3 8004590: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8004592: f107 0318 add.w r3, r7, #24 8004596: 4619 mov r1, r3 8004598: 484d ldr r0, [pc, #308] ; (80046d0 ) 800459a: f7fd fd5d bl 8002058 GPIO_InitStruct.Pin = GPIO_PIN_10; 800459e: f44f 6380 mov.w r3, #1024 ; 0x400 80045a2: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80045a4: 2300 movs r3, #0 80045a6: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 80045a8: 2300 movs r3, #0 80045aa: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80045ac: f107 0318 add.w r3, r7, #24 80045b0: 4619 mov r1, r3 80045b2: 4847 ldr r0, [pc, #284] ; (80046d0 ) 80045b4: f7fd fd50 bl 8002058 /* USART1 DMA Init */ /* USART1_TX Init */ hdma_usart1_tx.Instance = DMA1_Channel4; 80045b8: 4b46 ldr r3, [pc, #280] ; (80046d4 ) 80045ba: 4a47 ldr r2, [pc, #284] ; (80046d8 ) 80045bc: 601a str r2, [r3, #0] hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 80045be: 4b45 ldr r3, [pc, #276] ; (80046d4 ) 80045c0: 2210 movs r2, #16 80045c2: 605a str r2, [r3, #4] hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE; 80045c4: 4b43 ldr r3, [pc, #268] ; (80046d4 ) 80045c6: 2200 movs r2, #0 80045c8: 609a str r2, [r3, #8] hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE; 80045ca: 4b42 ldr r3, [pc, #264] ; (80046d4 ) 80045cc: 2280 movs r2, #128 ; 0x80 80045ce: 60da str r2, [r3, #12] hdma_usart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 80045d0: 4b40 ldr r3, [pc, #256] ; (80046d4 ) 80045d2: 2200 movs r2, #0 80045d4: 611a str r2, [r3, #16] hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 80045d6: 4b3f ldr r3, [pc, #252] ; (80046d4 ) 80045d8: 2200 movs r2, #0 80045da: 615a str r2, [r3, #20] hdma_usart1_tx.Init.Mode = DMA_NORMAL; 80045dc: 4b3d ldr r3, [pc, #244] ; (80046d4 ) 80045de: 2200 movs r2, #0 80045e0: 619a str r2, [r3, #24] hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW; 80045e2: 4b3c ldr r3, [pc, #240] ; (80046d4 ) 80045e4: 2200 movs r2, #0 80045e6: 61da str r2, [r3, #28] if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK) 80045e8: 483a ldr r0, [pc, #232] ; (80046d4 ) 80045ea: f7fd fad1 bl 8001b90 80045ee: 4603 mov r3, r0 80045f0: 2b00 cmp r3, #0 80045f2: d001 beq.n 80045f8 { Error_Handler(); 80045f4: f7ff fee0 bl 80043b8 } __HAL_LINKDMA(huart,hdmatx,hdma_usart1_tx); 80045f8: 687b ldr r3, [r7, #4] 80045fa: 4a36 ldr r2, [pc, #216] ; (80046d4 ) 80045fc: 631a str r2, [r3, #48] ; 0x30 80045fe: 4a35 ldr r2, [pc, #212] ; (80046d4 ) 8004600: 687b ldr r3, [r7, #4] 8004602: 6253 str r3, [r2, #36] ; 0x24 /* USER CODE BEGIN USART3_MspInit 1 */ /* USER CODE END USART3_MspInit 1 */ } } 8004604: e05c b.n 80046c0 else if(huart->Instance==USART3) 8004606: 687b ldr r3, [r7, #4] 8004608: 681b ldr r3, [r3, #0] 800460a: 4a34 ldr r2, [pc, #208] ; (80046dc ) 800460c: 4293 cmp r3, r2 800460e: d157 bne.n 80046c0 __HAL_RCC_USART3_CLK_ENABLE(); 8004610: 4b2e ldr r3, [pc, #184] ; (80046cc ) 8004612: 69db ldr r3, [r3, #28] 8004614: 4a2d ldr r2, [pc, #180] ; (80046cc ) 8004616: f443 2380 orr.w r3, r3, #262144 ; 0x40000 800461a: 61d3 str r3, [r2, #28] 800461c: 4b2b ldr r3, [pc, #172] ; (80046cc ) 800461e: 69db ldr r3, [r3, #28] 8004620: f403 2380 and.w r3, r3, #262144 ; 0x40000 8004624: 60fb str r3, [r7, #12] 8004626: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOB_CLK_ENABLE(); 8004628: 4b28 ldr r3, [pc, #160] ; (80046cc ) 800462a: 699b ldr r3, [r3, #24] 800462c: 4a27 ldr r2, [pc, #156] ; (80046cc ) 800462e: f043 0308 orr.w r3, r3, #8 8004632: 6193 str r3, [r2, #24] 8004634: 4b25 ldr r3, [pc, #148] ; (80046cc ) 8004636: 699b ldr r3, [r3, #24] 8004638: f003 0308 and.w r3, r3, #8 800463c: 60bb str r3, [r7, #8] 800463e: 68bb ldr r3, [r7, #8] GPIO_InitStruct.Pin = GPIO_PIN_10; 8004640: f44f 6380 mov.w r3, #1024 ; 0x400 8004644: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8004646: 2302 movs r3, #2 8004648: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800464a: 2303 movs r3, #3 800464c: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800464e: f107 0318 add.w r3, r7, #24 8004652: 4619 mov r1, r3 8004654: 4822 ldr r0, [pc, #136] ; (80046e0 ) 8004656: f7fd fcff bl 8002058 GPIO_InitStruct.Pin = GPIO_PIN_11; 800465a: f44f 6300 mov.w r3, #2048 ; 0x800 800465e: 61bb str r3, [r7, #24] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8004660: 2300 movs r3, #0 8004662: 61fb str r3, [r7, #28] GPIO_InitStruct.Pull = GPIO_NOPULL; 8004664: 2300 movs r3, #0 8004666: 623b str r3, [r7, #32] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8004668: f107 0318 add.w r3, r7, #24 800466c: 4619 mov r1, r3 800466e: 481c ldr r0, [pc, #112] ; (80046e0 ) 8004670: f7fd fcf2 bl 8002058 hdma_usart3_tx.Instance = DMA1_Channel2; 8004674: 4b1b ldr r3, [pc, #108] ; (80046e4 ) 8004676: 4a1c ldr r2, [pc, #112] ; (80046e8 ) 8004678: 601a str r2, [r3, #0] hdma_usart3_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 800467a: 4b1a ldr r3, [pc, #104] ; (80046e4 ) 800467c: 2210 movs r2, #16 800467e: 605a str r2, [r3, #4] hdma_usart3_tx.Init.PeriphInc = DMA_PINC_DISABLE; 8004680: 4b18 ldr r3, [pc, #96] ; (80046e4 ) 8004682: 2200 movs r2, #0 8004684: 609a str r2, [r3, #8] hdma_usart3_tx.Init.MemInc = DMA_MINC_ENABLE; 8004686: 4b17 ldr r3, [pc, #92] ; (80046e4 ) 8004688: 2280 movs r2, #128 ; 0x80 800468a: 60da str r2, [r3, #12] hdma_usart3_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 800468c: 4b15 ldr r3, [pc, #84] ; (80046e4 ) 800468e: 2200 movs r2, #0 8004690: 611a str r2, [r3, #16] hdma_usart3_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8004692: 4b14 ldr r3, [pc, #80] ; (80046e4 ) 8004694: 2200 movs r2, #0 8004696: 615a str r2, [r3, #20] hdma_usart3_tx.Init.Mode = DMA_NORMAL; 8004698: 4b12 ldr r3, [pc, #72] ; (80046e4 ) 800469a: 2200 movs r2, #0 800469c: 619a str r2, [r3, #24] hdma_usart3_tx.Init.Priority = DMA_PRIORITY_LOW; 800469e: 4b11 ldr r3, [pc, #68] ; (80046e4 ) 80046a0: 2200 movs r2, #0 80046a2: 61da str r2, [r3, #28] if (HAL_DMA_Init(&hdma_usart3_tx) != HAL_OK) 80046a4: 480f ldr r0, [pc, #60] ; (80046e4 ) 80046a6: f7fd fa73 bl 8001b90 80046aa: 4603 mov r3, r0 80046ac: 2b00 cmp r3, #0 80046ae: d001 beq.n 80046b4 Error_Handler(); 80046b0: f7ff fe82 bl 80043b8 __HAL_LINKDMA(huart,hdmatx,hdma_usart3_tx); 80046b4: 687b ldr r3, [r7, #4] 80046b6: 4a0b ldr r2, [pc, #44] ; (80046e4 ) 80046b8: 631a str r2, [r3, #48] ; 0x30 80046ba: 4a0a ldr r2, [pc, #40] ; (80046e4 ) 80046bc: 687b ldr r3, [r7, #4] 80046be: 6253 str r3, [r2, #36] ; 0x24 } 80046c0: bf00 nop 80046c2: 3728 adds r7, #40 ; 0x28 80046c4: 46bd mov sp, r7 80046c6: bd80 pop {r7, pc} 80046c8: 40013800 .word 0x40013800 80046cc: 40021000 .word 0x40021000 80046d0: 40010800 .word 0x40010800 80046d4: 200004c0 .word 0x200004c0 80046d8: 40020044 .word 0x40020044 80046dc: 40004800 .word 0x40004800 80046e0: 40010c00 .word 0x40010c00 80046e4: 2000047c .word 0x2000047c 80046e8: 4002001c .word 0x4002001c 080046ec : * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). * @param TickPriority: Tick interrupt priority. * @retval HAL status */ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 80046ec: b580 push {r7, lr} 80046ee: b08c sub sp, #48 ; 0x30 80046f0: af00 add r7, sp, #0 80046f2: 6078 str r0, [r7, #4] RCC_ClkInitTypeDef clkconfig; uint32_t uwTimclock = 0; 80046f4: 2300 movs r3, #0 80046f6: 62fb str r3, [r7, #44] ; 0x2c uint32_t uwPrescalerValue = 0; 80046f8: 2300 movs r3, #0 80046fa: 62bb str r3, [r7, #40] ; 0x28 uint32_t pFLatency; /*Configure the TIM2 IRQ priority */ HAL_NVIC_SetPriority(TIM2_IRQn, TickPriority ,0); 80046fc: 2200 movs r2, #0 80046fe: 6879 ldr r1, [r7, #4] 8004700: 201c movs r0, #28 8004702: f7fd fa1a bl 8001b3a /* Enable the TIM2 global Interrupt */ HAL_NVIC_EnableIRQ(TIM2_IRQn); 8004706: 201c movs r0, #28 8004708: f7fd fa33 bl 8001b72 /* Enable TIM2 clock */ __HAL_RCC_TIM2_CLK_ENABLE(); 800470c: 4b1f ldr r3, [pc, #124] ; (800478c ) 800470e: 69db ldr r3, [r3, #28] 8004710: 4a1e ldr r2, [pc, #120] ; (800478c ) 8004712: f043 0301 orr.w r3, r3, #1 8004716: 61d3 str r3, [r2, #28] 8004718: 4b1c ldr r3, [pc, #112] ; (800478c ) 800471a: 69db ldr r3, [r3, #28] 800471c: f003 0301 and.w r3, r3, #1 8004720: 60fb str r3, [r7, #12] 8004722: 68fb ldr r3, [r7, #12] /* Get clock configuration */ HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); 8004724: f107 0210 add.w r2, r7, #16 8004728: f107 0314 add.w r3, r7, #20 800472c: 4611 mov r1, r2 800472e: 4618 mov r0, r3 8004730: f7fe f9ea bl 8002b08 /* Compute TIM2 clock */ uwTimclock = HAL_RCC_GetPCLK1Freq(); 8004734: f7fe f9c0 bl 8002ab8 8004738: 62f8 str r0, [r7, #44] ; 0x2c /* Compute the prescaler value to have TIM2 counter clock equal to 1MHz */ uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000) - 1); 800473a: 6afb ldr r3, [r7, #44] ; 0x2c 800473c: 4a14 ldr r2, [pc, #80] ; (8004790 ) 800473e: fba2 2303 umull r2, r3, r2, r3 8004742: 0c9b lsrs r3, r3, #18 8004744: 3b01 subs r3, #1 8004746: 62bb str r3, [r7, #40] ; 0x28 /* Initialize TIM2 */ htim2.Instance = TIM2; 8004748: 4b12 ldr r3, [pc, #72] ; (8004794 ) 800474a: f04f 4280 mov.w r2, #1073741824 ; 0x40000000 800474e: 601a str r2, [r3, #0] + Period = [(TIM2CLK/1000) - 1]. to have a (1/1000) s time base. + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. + ClockDivision = 0 + Counter direction = Up */ htim2.Init.Period = (1000000 / 1000) - 1; 8004750: 4b10 ldr r3, [pc, #64] ; (8004794 ) 8004752: f240 32e7 movw r2, #999 ; 0x3e7 8004756: 60da str r2, [r3, #12] htim2.Init.Prescaler = uwPrescalerValue; 8004758: 4a0e ldr r2, [pc, #56] ; (8004794 ) 800475a: 6abb ldr r3, [r7, #40] ; 0x28 800475c: 6053 str r3, [r2, #4] htim2.Init.ClockDivision = 0; 800475e: 4b0d ldr r3, [pc, #52] ; (8004794 ) 8004760: 2200 movs r2, #0 8004762: 611a str r2, [r3, #16] htim2.Init.CounterMode = TIM_COUNTERMODE_UP; 8004764: 4b0b ldr r3, [pc, #44] ; (8004794 ) 8004766: 2200 movs r2, #0 8004768: 609a str r2, [r3, #8] if(HAL_TIM_Base_Init(&htim2) == HAL_OK) 800476a: 480a ldr r0, [pc, #40] ; (8004794 ) 800476c: f7fe fb14 bl 8002d98 8004770: 4603 mov r3, r0 8004772: 2b00 cmp r3, #0 8004774: d104 bne.n 8004780 { /* Start the TIM time Base generation in interrupt mode */ return HAL_TIM_Base_Start_IT(&htim2); 8004776: 4807 ldr r0, [pc, #28] ; (8004794 ) 8004778: f7fe fb39 bl 8002dee 800477c: 4603 mov r3, r0 800477e: e000 b.n 8004782 } /* Return function status */ return HAL_ERROR; 8004780: 2301 movs r3, #1 } 8004782: 4618 mov r0, r3 8004784: 3730 adds r7, #48 ; 0x30 8004786: 46bd mov sp, r7 8004788: bd80 pop {r7, pc} 800478a: bf00 nop 800478c: 40021000 .word 0x40021000 8004790: 431bde83 .word 0x431bde83 8004794: 200005f8 .word 0x200005f8 08004798 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8004798: b480 push {r7} 800479a: af00 add r7, sp, #0 /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ /* USER CODE END NonMaskableInt_IRQn 1 */ } 800479c: bf00 nop 800479e: 46bd mov sp, r7 80047a0: bc80 pop {r7} 80047a2: 4770 bx lr 080047a4 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 80047a4: b480 push {r7} 80047a6: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 80047a8: e7fe b.n 80047a8 080047aa : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 80047aa: b480 push {r7} 80047ac: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 80047ae: e7fe b.n 80047ae 080047b0 : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { 80047b0: b480 push {r7} 80047b2: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 80047b4: e7fe b.n 80047b4 080047b6 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 80047b6: b480 push {r7} 80047b8: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 80047ba: e7fe b.n 80047ba 080047bc : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 80047bc: b480 push {r7} 80047be: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 80047c0: bf00 nop 80047c2: 46bd mov sp, r7 80047c4: bc80 pop {r7} 80047c6: 4770 bx lr 080047c8 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 80047c8: b480 push {r7} 80047ca: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 80047cc: bf00 nop 80047ce: 46bd mov sp, r7 80047d0: bc80 pop {r7} 80047d2: 4770 bx lr 080047d4 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 80047d4: b480 push {r7} 80047d6: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 80047d8: bf00 nop 80047da: 46bd mov sp, r7 80047dc: bc80 pop {r7} 80047de: 4770 bx lr 080047e0 : /** * @brief This function handles DMA1 channel1 global interrupt. */ void DMA1_Channel1_IRQHandler(void) { 80047e0: b580 push {r7, lr} 80047e2: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */ /* USER CODE END DMA1_Channel1_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc1); 80047e4: 4802 ldr r0, [pc, #8] ; (80047f0 ) 80047e6: f7fd fb03 bl 8001df0 /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */ /* USER CODE END DMA1_Channel1_IRQn 1 */ } 80047ea: bf00 nop 80047ec: bd80 pop {r7, pc} 80047ee: bf00 nop 80047f0: 20000574 .word 0x20000574 080047f4 : /** * @brief This function handles DMA1 channel2 global interrupt. */ void DMA1_Channel2_IRQHandler(void) { 80047f4: b580 push {r7, lr} 80047f6: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Channel2_IRQn 0 */ /* USER CODE END DMA1_Channel2_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart3_tx); 80047f8: 4802 ldr r0, [pc, #8] ; (8004804 ) 80047fa: f7fd faf9 bl 8001df0 /* USER CODE BEGIN DMA1_Channel2_IRQn 1 */ /* USER CODE END DMA1_Channel2_IRQn 1 */ } 80047fe: bf00 nop 8004800: bd80 pop {r7, pc} 8004802: bf00 nop 8004804: 2000047c .word 0x2000047c 08004808 : /** * @brief This function handles DMA1 channel4 global interrupt. */ void DMA1_Channel4_IRQHandler(void) { 8004808: b580 push {r7, lr} 800480a: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Channel4_IRQn 0 */ /* USER CODE END DMA1_Channel4_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart1_tx); 800480c: 4802 ldr r0, [pc, #8] ; (8004818 ) 800480e: f7fd faef bl 8001df0 /* USER CODE BEGIN DMA1_Channel4_IRQn 1 */ /* USER CODE END DMA1_Channel4_IRQn 1 */ } 8004812: bf00 nop 8004814: bd80 pop {r7, pc} 8004816: bf00 nop 8004818: 200004c0 .word 0x200004c0 0800481c : /** * @brief This function handles ADC1 global interrupt. */ void ADC1_IRQHandler(void) { 800481c: b580 push {r7, lr} 800481e: af00 add r7, sp, #0 /* USER CODE BEGIN ADC1_IRQn 0 */ /* USER CODE END ADC1_IRQn 0 */ HAL_ADC_IRQHandler(&hadc1); 8004820: 4802 ldr r0, [pc, #8] ; (800482c ) 8004822: f7fc fd67 bl 80012f4 /* USER CODE BEGIN ADC1_IRQn 1 */ /* USER CODE END ADC1_IRQn 1 */ } 8004826: bf00 nop 8004828: bd80 pop {r7, pc} 800482a: bf00 nop 800482c: 20000504 .word 0x20000504 08004830 : /** * @brief This function handles TIM2 global interrupt. */ void TIM2_IRQHandler(void) { 8004830: b580 push {r7, lr} 8004832: af00 add r7, sp, #0 /* USER CODE BEGIN TIM2_IRQn 0 */ /* USER CODE END TIM2_IRQn 0 */ HAL_TIM_IRQHandler(&htim2); 8004834: 4802 ldr r0, [pc, #8] ; (8004840 ) 8004836: f7fe fafd bl 8002e34 /* USER CODE BEGIN TIM2_IRQn 1 */ /* USER CODE END TIM2_IRQn 1 */ } 800483a: bf00 nop 800483c: bd80 pop {r7, pc} 800483e: bf00 nop 8004840: 200005f8 .word 0x200005f8 08004844 : /** * @brief This function handles USART1 global interrupt. */ void USART1_IRQHandler(void) { 8004844: b580 push {r7, lr} 8004846: af00 add r7, sp, #0 /* USER CODE BEGIN USART1_IRQn 0 */ /* USER CODE END USART1_IRQn 0 */ HAL_UART_IRQHandler(&huart1); 8004848: 4802 ldr r0, [pc, #8] ; (8004854 ) 800484a: f7fe fe83 bl 8003554 /* USER CODE BEGIN USART1_IRQn 1 */ /* USER CODE END USART1_IRQn 1 */ } 800484e: bf00 nop 8004850: bd80 pop {r7, pc} 8004852: bf00 nop 8004854: 20000534 .word 0x20000534 08004858 : /** * @brief This function handles USART3 global interrupt. */ void USART3_IRQHandler(void) { 8004858: b580 push {r7, lr} 800485a: af00 add r7, sp, #0 /* USER CODE BEGIN USART3_IRQn 0 */ /* USER CODE END USART3_IRQn 0 */ HAL_UART_IRQHandler(&huart3); 800485c: 4802 ldr r0, [pc, #8] ; (8004868 ) 800485e: f7fe fe79 bl 8003554 /* USER CODE BEGIN USART3_IRQn 1 */ /* USER CODE END USART3_IRQn 1 */ } 8004862: bf00 nop 8004864: bd80 pop {r7, pc} 8004866: bf00 nop 8004868: 2000043c .word 0x2000043c 0800486c : /** * @brief This function handles TIM6 global interrupt and DAC underrun error interrupts. */ void TIM6_DAC_IRQHandler(void) { 800486c: b580 push {r7, lr} 800486e: af00 add r7, sp, #0 /* USER CODE BEGIN TIM6_DAC_IRQn 0 */ /* USER CODE END TIM6_DAC_IRQn 0 */ HAL_TIM_IRQHandler(&htim6); 8004870: 4802 ldr r0, [pc, #8] ; (800487c ) 8004872: f7fe fadf bl 8002e34 /* USER CODE BEGIN TIM6_DAC_IRQn 1 */ /* USER CODE END TIM6_DAC_IRQn 1 */ } 8004876: bf00 nop 8004878: bd80 pop {r7, pc} 800487a: bf00 nop 800487c: 200005b8 .word 0x200005b8 08004880 <_read>: _kill(status, -1); while (1) {} /* Make sure we hang here */ } __attribute__((weak)) int _read(int file, char *ptr, int len) { 8004880: b580 push {r7, lr} 8004882: b086 sub sp, #24 8004884: af00 add r7, sp, #0 8004886: 60f8 str r0, [r7, #12] 8004888: 60b9 str r1, [r7, #8] 800488a: 607a str r2, [r7, #4] int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 800488c: 2300 movs r3, #0 800488e: 617b str r3, [r7, #20] 8004890: e00a b.n 80048a8 <_read+0x28> { *ptr++ = __io_getchar(); 8004892: f3af 8000 nop.w 8004896: 4601 mov r1, r0 8004898: 68bb ldr r3, [r7, #8] 800489a: 1c5a adds r2, r3, #1 800489c: 60ba str r2, [r7, #8] 800489e: b2ca uxtb r2, r1 80048a0: 701a strb r2, [r3, #0] for (DataIdx = 0; DataIdx < len; DataIdx++) 80048a2: 697b ldr r3, [r7, #20] 80048a4: 3301 adds r3, #1 80048a6: 617b str r3, [r7, #20] 80048a8: 697a ldr r2, [r7, #20] 80048aa: 687b ldr r3, [r7, #4] 80048ac: 429a cmp r2, r3 80048ae: dbf0 blt.n 8004892 <_read+0x12> } return len; 80048b0: 687b ldr r3, [r7, #4] } 80048b2: 4618 mov r0, r3 80048b4: 3718 adds r7, #24 80048b6: 46bd mov sp, r7 80048b8: bd80 pop {r7, pc} 080048ba <_write>: __attribute__((weak)) int _write(int file, char *ptr, int len) { 80048ba: b580 push {r7, lr} 80048bc: b086 sub sp, #24 80048be: af00 add r7, sp, #0 80048c0: 60f8 str r0, [r7, #12] 80048c2: 60b9 str r1, [r7, #8] 80048c4: 607a str r2, [r7, #4] int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 80048c6: 2300 movs r3, #0 80048c8: 617b str r3, [r7, #20] 80048ca: e009 b.n 80048e0 <_write+0x26> { __io_putchar(*ptr++); 80048cc: 68bb ldr r3, [r7, #8] 80048ce: 1c5a adds r2, r3, #1 80048d0: 60ba str r2, [r7, #8] 80048d2: 781b ldrb r3, [r3, #0] 80048d4: 4618 mov r0, r3 80048d6: f3af 8000 nop.w for (DataIdx = 0; DataIdx < len; DataIdx++) 80048da: 697b ldr r3, [r7, #20] 80048dc: 3301 adds r3, #1 80048de: 617b str r3, [r7, #20] 80048e0: 697a ldr r2, [r7, #20] 80048e2: 687b ldr r3, [r7, #4] 80048e4: 429a cmp r2, r3 80048e6: dbf1 blt.n 80048cc <_write+0x12> } return len; 80048e8: 687b ldr r3, [r7, #4] } 80048ea: 4618 mov r0, r3 80048ec: 3718 adds r7, #24 80048ee: 46bd mov sp, r7 80048f0: bd80 pop {r7, pc} 080048f2 <_close>: int _close(int file) { 80048f2: b480 push {r7} 80048f4: b083 sub sp, #12 80048f6: af00 add r7, sp, #0 80048f8: 6078 str r0, [r7, #4] return -1; 80048fa: f04f 33ff mov.w r3, #4294967295 } 80048fe: 4618 mov r0, r3 8004900: 370c adds r7, #12 8004902: 46bd mov sp, r7 8004904: bc80 pop {r7} 8004906: 4770 bx lr 08004908 <_fstat>: int _fstat(int file, struct stat *st) { 8004908: b480 push {r7} 800490a: b083 sub sp, #12 800490c: af00 add r7, sp, #0 800490e: 6078 str r0, [r7, #4] 8004910: 6039 str r1, [r7, #0] st->st_mode = S_IFCHR; 8004912: 683b ldr r3, [r7, #0] 8004914: f44f 5200 mov.w r2, #8192 ; 0x2000 8004918: 605a str r2, [r3, #4] return 0; 800491a: 2300 movs r3, #0 } 800491c: 4618 mov r0, r3 800491e: 370c adds r7, #12 8004920: 46bd mov sp, r7 8004922: bc80 pop {r7} 8004924: 4770 bx lr 08004926 <_isatty>: int _isatty(int file) { 8004926: b480 push {r7} 8004928: b083 sub sp, #12 800492a: af00 add r7, sp, #0 800492c: 6078 str r0, [r7, #4] return 1; 800492e: 2301 movs r3, #1 } 8004930: 4618 mov r0, r3 8004932: 370c adds r7, #12 8004934: 46bd mov sp, r7 8004936: bc80 pop {r7} 8004938: 4770 bx lr 0800493a <_lseek>: int _lseek(int file, int ptr, int dir) { 800493a: b480 push {r7} 800493c: b085 sub sp, #20 800493e: af00 add r7, sp, #0 8004940: 60f8 str r0, [r7, #12] 8004942: 60b9 str r1, [r7, #8] 8004944: 607a str r2, [r7, #4] return 0; 8004946: 2300 movs r3, #0 } 8004948: 4618 mov r0, r3 800494a: 3714 adds r7, #20 800494c: 46bd mov sp, r7 800494e: bc80 pop {r7} 8004950: 4770 bx lr ... 08004954 <_sbrk>: /** _sbrk Increase program data space. Malloc and related functions depend on this **/ caddr_t _sbrk(int incr) { 8004954: b580 push {r7, lr} 8004956: b084 sub sp, #16 8004958: af00 add r7, sp, #0 800495a: 6078 str r0, [r7, #4] extern char end asm("end"); static char *heap_end; char *prev_heap_end; if (heap_end == 0) 800495c: 4b11 ldr r3, [pc, #68] ; (80049a4 <_sbrk+0x50>) 800495e: 681b ldr r3, [r3, #0] 8004960: 2b00 cmp r3, #0 8004962: d102 bne.n 800496a <_sbrk+0x16> heap_end = &end; 8004964: 4b0f ldr r3, [pc, #60] ; (80049a4 <_sbrk+0x50>) 8004966: 4a10 ldr r2, [pc, #64] ; (80049a8 <_sbrk+0x54>) 8004968: 601a str r2, [r3, #0] prev_heap_end = heap_end; 800496a: 4b0e ldr r3, [pc, #56] ; (80049a4 <_sbrk+0x50>) 800496c: 681b ldr r3, [r3, #0] 800496e: 60fb str r3, [r7, #12] if (heap_end + incr > stack_ptr) 8004970: 4b0c ldr r3, [pc, #48] ; (80049a4 <_sbrk+0x50>) 8004972: 681a ldr r2, [r3, #0] 8004974: 687b ldr r3, [r7, #4] 8004976: 4413 add r3, r2 8004978: 466a mov r2, sp 800497a: 4293 cmp r3, r2 800497c: d907 bls.n 800498e <_sbrk+0x3a> { errno = ENOMEM; 800497e: f000 f873 bl 8004a68 <__errno> 8004982: 4602 mov r2, r0 8004984: 230c movs r3, #12 8004986: 6013 str r3, [r2, #0] return (caddr_t) -1; 8004988: f04f 33ff mov.w r3, #4294967295 800498c: e006 b.n 800499c <_sbrk+0x48> } heap_end += incr; 800498e: 4b05 ldr r3, [pc, #20] ; (80049a4 <_sbrk+0x50>) 8004990: 681a ldr r2, [r3, #0] 8004992: 687b ldr r3, [r7, #4] 8004994: 4413 add r3, r2 8004996: 4a03 ldr r2, [pc, #12] ; (80049a4 <_sbrk+0x50>) 8004998: 6013 str r3, [r2, #0] return (caddr_t) prev_heap_end; 800499a: 68fb ldr r3, [r7, #12] } 800499c: 4618 mov r0, r3 800499e: 3710 adds r7, #16 80049a0: 46bd mov sp, r7 80049a2: bd80 pop {r7, pc} 80049a4: 20000208 .word 0x20000208 80049a8: 20000640 .word 0x20000640 080049ac : * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit (void) { 80049ac: b480 push {r7} 80049ae: af00 add r7, sp, #0 /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ /* Set HSION bit */ RCC->CR |= 0x00000001U; 80049b0: 4b17 ldr r3, [pc, #92] ; (8004a10 ) 80049b2: 681b ldr r3, [r3, #0] 80049b4: 4a16 ldr r2, [pc, #88] ; (8004a10 ) 80049b6: f043 0301 orr.w r3, r3, #1 80049ba: 6013 str r3, [r2, #0] /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ #if !defined(STM32F105xC) && !defined(STM32F107xC) RCC->CFGR &= 0xF8FF0000U; 80049bc: 4b14 ldr r3, [pc, #80] ; (8004a10 ) 80049be: 685a ldr r2, [r3, #4] 80049c0: 4913 ldr r1, [pc, #76] ; (8004a10 ) 80049c2: 4b14 ldr r3, [pc, #80] ; (8004a14 ) 80049c4: 4013 ands r3, r2 80049c6: 604b str r3, [r1, #4] #else RCC->CFGR &= 0xF0FF0000U; #endif /* STM32F105xC */ /* Reset HSEON, CSSON and PLLON bits */ RCC->CR &= 0xFEF6FFFFU; 80049c8: 4b11 ldr r3, [pc, #68] ; (8004a10 ) 80049ca: 681b ldr r3, [r3, #0] 80049cc: 4a10 ldr r2, [pc, #64] ; (8004a10 ) 80049ce: f023 7384 bic.w r3, r3, #17301504 ; 0x1080000 80049d2: f423 3380 bic.w r3, r3, #65536 ; 0x10000 80049d6: 6013 str r3, [r2, #0] /* Reset HSEBYP bit */ RCC->CR &= 0xFFFBFFFFU; 80049d8: 4b0d ldr r3, [pc, #52] ; (8004a10 ) 80049da: 681b ldr r3, [r3, #0] 80049dc: 4a0c ldr r2, [pc, #48] ; (8004a10 ) 80049de: f423 2380 bic.w r3, r3, #262144 ; 0x40000 80049e2: 6013 str r3, [r2, #0] /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ RCC->CFGR &= 0xFF80FFFFU; 80049e4: 4b0a ldr r3, [pc, #40] ; (8004a10 ) 80049e6: 685b ldr r3, [r3, #4] 80049e8: 4a09 ldr r2, [pc, #36] ; (8004a10 ) 80049ea: f423 03fe bic.w r3, r3, #8323072 ; 0x7f0000 80049ee: 6053 str r3, [r2, #4] /* Reset CFGR2 register */ RCC->CFGR2 = 0x00000000U; #elif defined(STM32F100xB) || defined(STM32F100xE) /* Disable all interrupts and clear pending bits */ RCC->CIR = 0x009F0000U; 80049f0: 4b07 ldr r3, [pc, #28] ; (8004a10 ) 80049f2: f44f 021f mov.w r2, #10420224 ; 0x9f0000 80049f6: 609a str r2, [r3, #8] /* Reset CFGR2 register */ RCC->CFGR2 = 0x00000000U; 80049f8: 4b05 ldr r3, [pc, #20] ; (8004a10 ) 80049fa: 2200 movs r2, #0 80049fc: 62da str r2, [r3, #44] ; 0x2c #endif #ifdef VECT_TAB_SRAM SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #else SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ 80049fe: 4b06 ldr r3, [pc, #24] ; (8004a18 ) 8004a00: f04f 6200 mov.w r2, #134217728 ; 0x8000000 8004a04: 609a str r2, [r3, #8] #endif } 8004a06: bf00 nop 8004a08: 46bd mov sp, r7 8004a0a: bc80 pop {r7} 8004a0c: 4770 bx lr 8004a0e: bf00 nop 8004a10: 40021000 .word 0x40021000 8004a14: f8ff0000 .word 0xf8ff0000 8004a18: e000ed00 .word 0xe000ed00 08004a1c : .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 8004a1c: 2100 movs r1, #0 b LoopCopyDataInit 8004a1e: e003 b.n 8004a28 08004a20 : CopyDataInit: ldr r3, =_sidata 8004a20: 4b0b ldr r3, [pc, #44] ; (8004a50 ) ldr r3, [r3, r1] 8004a22: 585b ldr r3, [r3, r1] str r3, [r0, r1] 8004a24: 5043 str r3, [r0, r1] adds r1, r1, #4 8004a26: 3104 adds r1, #4 08004a28 : LoopCopyDataInit: ldr r0, =_sdata 8004a28: 480a ldr r0, [pc, #40] ; (8004a54 ) ldr r3, =_edata 8004a2a: 4b0b ldr r3, [pc, #44] ; (8004a58 ) adds r2, r0, r1 8004a2c: 1842 adds r2, r0, r1 cmp r2, r3 8004a2e: 429a cmp r2, r3 bcc CopyDataInit 8004a30: d3f6 bcc.n 8004a20 ldr r2, =_sbss 8004a32: 4a0a ldr r2, [pc, #40] ; (8004a5c ) b LoopFillZerobss 8004a34: e002 b.n 8004a3c 08004a36 : /* Zero fill the bss segment. */ FillZerobss: movs r3, #0 8004a36: 2300 movs r3, #0 str r3, [r2], #4 8004a38: f842 3b04 str.w r3, [r2], #4 08004a3c : LoopFillZerobss: ldr r3, = _ebss 8004a3c: 4b08 ldr r3, [pc, #32] ; (8004a60 ) cmp r2, r3 8004a3e: 429a cmp r2, r3 bcc FillZerobss 8004a40: d3f9 bcc.n 8004a36 /* Call the clock system intitialization function.*/ bl SystemInit 8004a42: f7ff ffb3 bl 80049ac /* Call static constructors */ bl __libc_init_array 8004a46: f000 f815 bl 8004a74 <__libc_init_array> /* Call the application's entry point.*/ bl main 8004a4a: f7ff fa23 bl 8003e94
bx lr 8004a4e: 4770 bx lr ldr r3, =_sidata 8004a50: 08007710 .word 0x08007710 ldr r0, =_sdata 8004a54: 20000000 .word 0x20000000 ldr r3, =_edata 8004a58: 200001dc .word 0x200001dc ldr r2, =_sbss 8004a5c: 200001dc .word 0x200001dc ldr r3, = _ebss 8004a60: 2000063c .word 0x2000063c 08004a64 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8004a64: e7fe b.n 8004a64 ... 08004a68 <__errno>: 8004a68: 4b01 ldr r3, [pc, #4] ; (8004a70 <__errno+0x8>) 8004a6a: 6818 ldr r0, [r3, #0] 8004a6c: 4770 bx lr 8004a6e: bf00 nop 8004a70: 2000000c .word 0x2000000c 08004a74 <__libc_init_array>: 8004a74: b570 push {r4, r5, r6, lr} 8004a76: 2500 movs r5, #0 8004a78: 4e0c ldr r6, [pc, #48] ; (8004aac <__libc_init_array+0x38>) 8004a7a: 4c0d ldr r4, [pc, #52] ; (8004ab0 <__libc_init_array+0x3c>) 8004a7c: 1ba4 subs r4, r4, r6 8004a7e: 10a4 asrs r4, r4, #2 8004a80: 42a5 cmp r5, r4 8004a82: d109 bne.n 8004a98 <__libc_init_array+0x24> 8004a84: f002 fc62 bl 800734c <_init> 8004a88: 2500 movs r5, #0 8004a8a: 4e0a ldr r6, [pc, #40] ; (8004ab4 <__libc_init_array+0x40>) 8004a8c: 4c0a ldr r4, [pc, #40] ; (8004ab8 <__libc_init_array+0x44>) 8004a8e: 1ba4 subs r4, r4, r6 8004a90: 10a4 asrs r4, r4, #2 8004a92: 42a5 cmp r5, r4 8004a94: d105 bne.n 8004aa2 <__libc_init_array+0x2e> 8004a96: bd70 pop {r4, r5, r6, pc} 8004a98: f856 3025 ldr.w r3, [r6, r5, lsl #2] 8004a9c: 4798 blx r3 8004a9e: 3501 adds r5, #1 8004aa0: e7ee b.n 8004a80 <__libc_init_array+0xc> 8004aa2: f856 3025 ldr.w r3, [r6, r5, lsl #2] 8004aa6: 4798 blx r3 8004aa8: 3501 adds r5, #1 8004aaa: e7f2 b.n 8004a92 <__libc_init_array+0x1e> 8004aac: 08007708 .word 0x08007708 8004ab0: 08007708 .word 0x08007708 8004ab4: 08007708 .word 0x08007708 8004ab8: 0800770c .word 0x0800770c 08004abc : 8004abc: 4603 mov r3, r0 8004abe: 4402 add r2, r0 8004ac0: 4293 cmp r3, r2 8004ac2: d100 bne.n 8004ac6 8004ac4: 4770 bx lr 8004ac6: f803 1b01 strb.w r1, [r3], #1 8004aca: e7f9 b.n 8004ac0 08004acc <__cvt>: 8004acc: 2b00 cmp r3, #0 8004ace: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8004ad2: 461e mov r6, r3 8004ad4: bfbb ittet lt 8004ad6: f103 4300 addlt.w r3, r3, #2147483648 ; 0x80000000 8004ada: 461e movlt r6, r3 8004adc: 2300 movge r3, #0 8004ade: 232d movlt r3, #45 ; 0x2d 8004ae0: b088 sub sp, #32 8004ae2: 9f14 ldr r7, [sp, #80] ; 0x50 8004ae4: e9dd 1a12 ldrd r1, sl, [sp, #72] ; 0x48 8004ae8: f027 0720 bic.w r7, r7, #32 8004aec: 2f46 cmp r7, #70 ; 0x46 8004aee: 4614 mov r4, r2 8004af0: 9d10 ldr r5, [sp, #64] ; 0x40 8004af2: 700b strb r3, [r1, #0] 8004af4: d004 beq.n 8004b00 <__cvt+0x34> 8004af6: 2f45 cmp r7, #69 ; 0x45 8004af8: d100 bne.n 8004afc <__cvt+0x30> 8004afa: 3501 adds r5, #1 8004afc: 2302 movs r3, #2 8004afe: e000 b.n 8004b02 <__cvt+0x36> 8004b00: 2303 movs r3, #3 8004b02: aa07 add r2, sp, #28 8004b04: 9204 str r2, [sp, #16] 8004b06: aa06 add r2, sp, #24 8004b08: e9cd a202 strd sl, r2, [sp, #8] 8004b0c: e9cd 3500 strd r3, r5, [sp] 8004b10: 4622 mov r2, r4 8004b12: 4633 mov r3, r6 8004b14: f000 feac bl 8005870 <_dtoa_r> 8004b18: 2f47 cmp r7, #71 ; 0x47 8004b1a: 4680 mov r8, r0 8004b1c: d102 bne.n 8004b24 <__cvt+0x58> 8004b1e: 9b11 ldr r3, [sp, #68] ; 0x44 8004b20: 07db lsls r3, r3, #31 8004b22: d526 bpl.n 8004b72 <__cvt+0xa6> 8004b24: 2f46 cmp r7, #70 ; 0x46 8004b26: eb08 0905 add.w r9, r8, r5 8004b2a: d111 bne.n 8004b50 <__cvt+0x84> 8004b2c: f898 3000 ldrb.w r3, [r8] 8004b30: 2b30 cmp r3, #48 ; 0x30 8004b32: d10a bne.n 8004b4a <__cvt+0x7e> 8004b34: 2200 movs r2, #0 8004b36: 2300 movs r3, #0 8004b38: 4620 mov r0, r4 8004b3a: 4631 mov r1, r6 8004b3c: f7fb ff94 bl 8000a68 <__aeabi_dcmpeq> 8004b40: b918 cbnz r0, 8004b4a <__cvt+0x7e> 8004b42: f1c5 0501 rsb r5, r5, #1 8004b46: f8ca 5000 str.w r5, [sl] 8004b4a: f8da 3000 ldr.w r3, [sl] 8004b4e: 4499 add r9, r3 8004b50: 2200 movs r2, #0 8004b52: 2300 movs r3, #0 8004b54: 4620 mov r0, r4 8004b56: 4631 mov r1, r6 8004b58: f7fb ff86 bl 8000a68 <__aeabi_dcmpeq> 8004b5c: b938 cbnz r0, 8004b6e <__cvt+0xa2> 8004b5e: 2230 movs r2, #48 ; 0x30 8004b60: 9b07 ldr r3, [sp, #28] 8004b62: 454b cmp r3, r9 8004b64: d205 bcs.n 8004b72 <__cvt+0xa6> 8004b66: 1c59 adds r1, r3, #1 8004b68: 9107 str r1, [sp, #28] 8004b6a: 701a strb r2, [r3, #0] 8004b6c: e7f8 b.n 8004b60 <__cvt+0x94> 8004b6e: f8cd 901c str.w r9, [sp, #28] 8004b72: 4640 mov r0, r8 8004b74: 9b07 ldr r3, [sp, #28] 8004b76: 9a15 ldr r2, [sp, #84] ; 0x54 8004b78: eba3 0308 sub.w r3, r3, r8 8004b7c: 6013 str r3, [r2, #0] 8004b7e: b008 add sp, #32 8004b80: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 08004b84 <__exponent>: 8004b84: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} 8004b86: 2900 cmp r1, #0 8004b88: bfb4 ite lt 8004b8a: 232d movlt r3, #45 ; 0x2d 8004b8c: 232b movge r3, #43 ; 0x2b 8004b8e: 4604 mov r4, r0 8004b90: bfb8 it lt 8004b92: 4249 neglt r1, r1 8004b94: 2909 cmp r1, #9 8004b96: f804 2b02 strb.w r2, [r4], #2 8004b9a: 7043 strb r3, [r0, #1] 8004b9c: dd21 ble.n 8004be2 <__exponent+0x5e> 8004b9e: f10d 0307 add.w r3, sp, #7 8004ba2: 461f mov r7, r3 8004ba4: 260a movs r6, #10 8004ba6: fb91 f5f6 sdiv r5, r1, r6 8004baa: fb06 1115 mls r1, r6, r5, r1 8004bae: 2d09 cmp r5, #9 8004bb0: f101 0130 add.w r1, r1, #48 ; 0x30 8004bb4: f803 1c01 strb.w r1, [r3, #-1] 8004bb8: f103 32ff add.w r2, r3, #4294967295 8004bbc: 4629 mov r1, r5 8004bbe: dc09 bgt.n 8004bd4 <__exponent+0x50> 8004bc0: 3130 adds r1, #48 ; 0x30 8004bc2: 3b02 subs r3, #2 8004bc4: f802 1c01 strb.w r1, [r2, #-1] 8004bc8: 42bb cmp r3, r7 8004bca: 4622 mov r2, r4 8004bcc: d304 bcc.n 8004bd8 <__exponent+0x54> 8004bce: 1a10 subs r0, r2, r0 8004bd0: b003 add sp, #12 8004bd2: bdf0 pop {r4, r5, r6, r7, pc} 8004bd4: 4613 mov r3, r2 8004bd6: e7e6 b.n 8004ba6 <__exponent+0x22> 8004bd8: f813 2b01 ldrb.w r2, [r3], #1 8004bdc: f804 2b01 strb.w r2, [r4], #1 8004be0: e7f2 b.n 8004bc8 <__exponent+0x44> 8004be2: 2330 movs r3, #48 ; 0x30 8004be4: 4419 add r1, r3 8004be6: 7083 strb r3, [r0, #2] 8004be8: 1d02 adds r2, r0, #4 8004bea: 70c1 strb r1, [r0, #3] 8004bec: e7ef b.n 8004bce <__exponent+0x4a> ... 08004bf0 <_printf_float>: 8004bf0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8004bf4: b091 sub sp, #68 ; 0x44 8004bf6: 460c mov r4, r1 8004bf8: 9f1a ldr r7, [sp, #104] ; 0x68 8004bfa: 4693 mov fp, r2 8004bfc: 461e mov r6, r3 8004bfe: 4605 mov r5, r0 8004c00: f001 fd64 bl 80066cc <_localeconv_r> 8004c04: 6803 ldr r3, [r0, #0] 8004c06: 4618 mov r0, r3 8004c08: 9309 str r3, [sp, #36] ; 0x24 8004c0a: f7fb fb01 bl 8000210 8004c0e: 2300 movs r3, #0 8004c10: 930e str r3, [sp, #56] ; 0x38 8004c12: 683b ldr r3, [r7, #0] 8004c14: 900a str r0, [sp, #40] ; 0x28 8004c16: 3307 adds r3, #7 8004c18: f023 0307 bic.w r3, r3, #7 8004c1c: f103 0208 add.w r2, r3, #8 8004c20: f894 8018 ldrb.w r8, [r4, #24] 8004c24: f8d4 a000 ldr.w sl, [r4] 8004c28: 603a str r2, [r7, #0] 8004c2a: e9d3 2300 ldrd r2, r3, [r3] 8004c2e: e9c4 2312 strd r2, r3, [r4, #72] ; 0x48 8004c32: e9d4 7912 ldrd r7, r9, [r4, #72] ; 0x48 8004c36: f029 4300 bic.w r3, r9, #2147483648 ; 0x80000000 8004c3a: 930b str r3, [sp, #44] ; 0x2c 8004c3c: f04f 32ff mov.w r2, #4294967295 8004c40: 4ba6 ldr r3, [pc, #664] ; (8004edc <_printf_float+0x2ec>) 8004c42: 4638 mov r0, r7 8004c44: 990b ldr r1, [sp, #44] ; 0x2c 8004c46: f7fb ff41 bl 8000acc <__aeabi_dcmpun> 8004c4a: bb68 cbnz r0, 8004ca8 <_printf_float+0xb8> 8004c4c: f04f 32ff mov.w r2, #4294967295 8004c50: 4ba2 ldr r3, [pc, #648] ; (8004edc <_printf_float+0x2ec>) 8004c52: 4638 mov r0, r7 8004c54: 990b ldr r1, [sp, #44] ; 0x2c 8004c56: f7fb ff1b bl 8000a90 <__aeabi_dcmple> 8004c5a: bb28 cbnz r0, 8004ca8 <_printf_float+0xb8> 8004c5c: 2200 movs r2, #0 8004c5e: 2300 movs r3, #0 8004c60: 4638 mov r0, r7 8004c62: 4649 mov r1, r9 8004c64: f7fb ff0a bl 8000a7c <__aeabi_dcmplt> 8004c68: b110 cbz r0, 8004c70 <_printf_float+0x80> 8004c6a: 232d movs r3, #45 ; 0x2d 8004c6c: f884 3043 strb.w r3, [r4, #67] ; 0x43 8004c70: 4f9b ldr r7, [pc, #620] ; (8004ee0 <_printf_float+0x2f0>) 8004c72: 4b9c ldr r3, [pc, #624] ; (8004ee4 <_printf_float+0x2f4>) 8004c74: f1b8 0f47 cmp.w r8, #71 ; 0x47 8004c78: bf98 it ls 8004c7a: 461f movls r7, r3 8004c7c: 2303 movs r3, #3 8004c7e: f04f 0900 mov.w r9, #0 8004c82: 6123 str r3, [r4, #16] 8004c84: f02a 0304 bic.w r3, sl, #4 8004c88: 6023 str r3, [r4, #0] 8004c8a: 9600 str r6, [sp, #0] 8004c8c: 465b mov r3, fp 8004c8e: aa0f add r2, sp, #60 ; 0x3c 8004c90: 4621 mov r1, r4 8004c92: 4628 mov r0, r5 8004c94: f000 f9e2 bl 800505c <_printf_common> 8004c98: 3001 adds r0, #1 8004c9a: f040 8090 bne.w 8004dbe <_printf_float+0x1ce> 8004c9e: f04f 30ff mov.w r0, #4294967295 8004ca2: b011 add sp, #68 ; 0x44 8004ca4: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8004ca8: 463a mov r2, r7 8004caa: 464b mov r3, r9 8004cac: 4638 mov r0, r7 8004cae: 4649 mov r1, r9 8004cb0: f7fb ff0c bl 8000acc <__aeabi_dcmpun> 8004cb4: b110 cbz r0, 8004cbc <_printf_float+0xcc> 8004cb6: 4f8c ldr r7, [pc, #560] ; (8004ee8 <_printf_float+0x2f8>) 8004cb8: 4b8c ldr r3, [pc, #560] ; (8004eec <_printf_float+0x2fc>) 8004cba: e7db b.n 8004c74 <_printf_float+0x84> 8004cbc: 6863 ldr r3, [r4, #4] 8004cbe: f44a 6280 orr.w r2, sl, #1024 ; 0x400 8004cc2: 1c59 adds r1, r3, #1 8004cc4: a80d add r0, sp, #52 ; 0x34 8004cc6: a90e add r1, sp, #56 ; 0x38 8004cc8: d140 bne.n 8004d4c <_printf_float+0x15c> 8004cca: 2306 movs r3, #6 8004ccc: 6063 str r3, [r4, #4] 8004cce: f04f 0c00 mov.w ip, #0 8004cd2: f10d 0333 add.w r3, sp, #51 ; 0x33 8004cd6: e9cd 2301 strd r2, r3, [sp, #4] 8004cda: 6863 ldr r3, [r4, #4] 8004cdc: 6022 str r2, [r4, #0] 8004cde: e9cd 0803 strd r0, r8, [sp, #12] 8004ce2: 9300 str r3, [sp, #0] 8004ce4: 463a mov r2, r7 8004ce6: 464b mov r3, r9 8004ce8: e9cd 1c05 strd r1, ip, [sp, #20] 8004cec: 4628 mov r0, r5 8004cee: f7ff feed bl 8004acc <__cvt> 8004cf2: f008 03df and.w r3, r8, #223 ; 0xdf 8004cf6: 2b47 cmp r3, #71 ; 0x47 8004cf8: 4607 mov r7, r0 8004cfa: d109 bne.n 8004d10 <_printf_float+0x120> 8004cfc: 9b0d ldr r3, [sp, #52] ; 0x34 8004cfe: 1cd8 adds r0, r3, #3 8004d00: db02 blt.n 8004d08 <_printf_float+0x118> 8004d02: 6862 ldr r2, [r4, #4] 8004d04: 4293 cmp r3, r2 8004d06: dd47 ble.n 8004d98 <_printf_float+0x1a8> 8004d08: f1a8 0802 sub.w r8, r8, #2 8004d0c: fa5f f888 uxtb.w r8, r8 8004d10: f1b8 0f65 cmp.w r8, #101 ; 0x65 8004d14: 990d ldr r1, [sp, #52] ; 0x34 8004d16: d824 bhi.n 8004d62 <_printf_float+0x172> 8004d18: 3901 subs r1, #1 8004d1a: 4642 mov r2, r8 8004d1c: f104 0050 add.w r0, r4, #80 ; 0x50 8004d20: 910d str r1, [sp, #52] ; 0x34 8004d22: f7ff ff2f bl 8004b84 <__exponent> 8004d26: 9a0e ldr r2, [sp, #56] ; 0x38 8004d28: 4681 mov r9, r0 8004d2a: 1813 adds r3, r2, r0 8004d2c: 2a01 cmp r2, #1 8004d2e: 6123 str r3, [r4, #16] 8004d30: dc02 bgt.n 8004d38 <_printf_float+0x148> 8004d32: 6822 ldr r2, [r4, #0] 8004d34: 07d1 lsls r1, r2, #31 8004d36: d501 bpl.n 8004d3c <_printf_float+0x14c> 8004d38: 3301 adds r3, #1 8004d3a: 6123 str r3, [r4, #16] 8004d3c: f89d 3033 ldrb.w r3, [sp, #51] ; 0x33 8004d40: 2b00 cmp r3, #0 8004d42: d0a2 beq.n 8004c8a <_printf_float+0x9a> 8004d44: 232d movs r3, #45 ; 0x2d 8004d46: f884 3043 strb.w r3, [r4, #67] ; 0x43 8004d4a: e79e b.n 8004c8a <_printf_float+0x9a> 8004d4c: f1b8 0f67 cmp.w r8, #103 ; 0x67 8004d50: f000 816e beq.w 8005030 <_printf_float+0x440> 8004d54: f1b8 0f47 cmp.w r8, #71 ; 0x47 8004d58: d1b9 bne.n 8004cce <_printf_float+0xde> 8004d5a: 2b00 cmp r3, #0 8004d5c: d1b7 bne.n 8004cce <_printf_float+0xde> 8004d5e: 2301 movs r3, #1 8004d60: e7b4 b.n 8004ccc <_printf_float+0xdc> 8004d62: f1b8 0f66 cmp.w r8, #102 ; 0x66 8004d66: d119 bne.n 8004d9c <_printf_float+0x1ac> 8004d68: 2900 cmp r1, #0 8004d6a: 6863 ldr r3, [r4, #4] 8004d6c: dd0c ble.n 8004d88 <_printf_float+0x198> 8004d6e: 6121 str r1, [r4, #16] 8004d70: b913 cbnz r3, 8004d78 <_printf_float+0x188> 8004d72: 6822 ldr r2, [r4, #0] 8004d74: 07d2 lsls r2, r2, #31 8004d76: d502 bpl.n 8004d7e <_printf_float+0x18e> 8004d78: 3301 adds r3, #1 8004d7a: 440b add r3, r1 8004d7c: 6123 str r3, [r4, #16] 8004d7e: 9b0d ldr r3, [sp, #52] ; 0x34 8004d80: f04f 0900 mov.w r9, #0 8004d84: 65a3 str r3, [r4, #88] ; 0x58 8004d86: e7d9 b.n 8004d3c <_printf_float+0x14c> 8004d88: b913 cbnz r3, 8004d90 <_printf_float+0x1a0> 8004d8a: 6822 ldr r2, [r4, #0] 8004d8c: 07d0 lsls r0, r2, #31 8004d8e: d501 bpl.n 8004d94 <_printf_float+0x1a4> 8004d90: 3302 adds r3, #2 8004d92: e7f3 b.n 8004d7c <_printf_float+0x18c> 8004d94: 2301 movs r3, #1 8004d96: e7f1 b.n 8004d7c <_printf_float+0x18c> 8004d98: f04f 0867 mov.w r8, #103 ; 0x67 8004d9c: e9dd 320d ldrd r3, r2, [sp, #52] ; 0x34 8004da0: 4293 cmp r3, r2 8004da2: db05 blt.n 8004db0 <_printf_float+0x1c0> 8004da4: 6822 ldr r2, [r4, #0] 8004da6: 6123 str r3, [r4, #16] 8004da8: 07d1 lsls r1, r2, #31 8004daa: d5e8 bpl.n 8004d7e <_printf_float+0x18e> 8004dac: 3301 adds r3, #1 8004dae: e7e5 b.n 8004d7c <_printf_float+0x18c> 8004db0: 2b00 cmp r3, #0 8004db2: bfcc ite gt 8004db4: 2301 movgt r3, #1 8004db6: f1c3 0302 rsble r3, r3, #2 8004dba: 4413 add r3, r2 8004dbc: e7de b.n 8004d7c <_printf_float+0x18c> 8004dbe: 6823 ldr r3, [r4, #0] 8004dc0: 055a lsls r2, r3, #21 8004dc2: d407 bmi.n 8004dd4 <_printf_float+0x1e4> 8004dc4: 6923 ldr r3, [r4, #16] 8004dc6: 463a mov r2, r7 8004dc8: 4659 mov r1, fp 8004dca: 4628 mov r0, r5 8004dcc: 47b0 blx r6 8004dce: 3001 adds r0, #1 8004dd0: d129 bne.n 8004e26 <_printf_float+0x236> 8004dd2: e764 b.n 8004c9e <_printf_float+0xae> 8004dd4: f1b8 0f65 cmp.w r8, #101 ; 0x65 8004dd8: f240 80d7 bls.w 8004f8a <_printf_float+0x39a> 8004ddc: e9d4 0112 ldrd r0, r1, [r4, #72] ; 0x48 8004de0: 2200 movs r2, #0 8004de2: 2300 movs r3, #0 8004de4: f7fb fe40 bl 8000a68 <__aeabi_dcmpeq> 8004de8: b388 cbz r0, 8004e4e <_printf_float+0x25e> 8004dea: 2301 movs r3, #1 8004dec: 4a40 ldr r2, [pc, #256] ; (8004ef0 <_printf_float+0x300>) 8004dee: 4659 mov r1, fp 8004df0: 4628 mov r0, r5 8004df2: 47b0 blx r6 8004df4: 3001 adds r0, #1 8004df6: f43f af52 beq.w 8004c9e <_printf_float+0xae> 8004dfa: e9dd 230d ldrd r2, r3, [sp, #52] ; 0x34 8004dfe: 429a cmp r2, r3 8004e00: db02 blt.n 8004e08 <_printf_float+0x218> 8004e02: 6823 ldr r3, [r4, #0] 8004e04: 07d8 lsls r0, r3, #31 8004e06: d50e bpl.n 8004e26 <_printf_float+0x236> 8004e08: e9dd 2309 ldrd r2, r3, [sp, #36] ; 0x24 8004e0c: 4659 mov r1, fp 8004e0e: 4628 mov r0, r5 8004e10: 47b0 blx r6 8004e12: 3001 adds r0, #1 8004e14: f43f af43 beq.w 8004c9e <_printf_float+0xae> 8004e18: 2700 movs r7, #0 8004e1a: f104 081a add.w r8, r4, #26 8004e1e: 9b0e ldr r3, [sp, #56] ; 0x38 8004e20: 3b01 subs r3, #1 8004e22: 42bb cmp r3, r7 8004e24: dc09 bgt.n 8004e3a <_printf_float+0x24a> 8004e26: 6823 ldr r3, [r4, #0] 8004e28: 079f lsls r7, r3, #30 8004e2a: f100 80fd bmi.w 8005028 <_printf_float+0x438> 8004e2e: 68e0 ldr r0, [r4, #12] 8004e30: 9b0f ldr r3, [sp, #60] ; 0x3c 8004e32: 4298 cmp r0, r3 8004e34: bfb8 it lt 8004e36: 4618 movlt r0, r3 8004e38: e733 b.n 8004ca2 <_printf_float+0xb2> 8004e3a: 2301 movs r3, #1 8004e3c: 4642 mov r2, r8 8004e3e: 4659 mov r1, fp 8004e40: 4628 mov r0, r5 8004e42: 47b0 blx r6 8004e44: 3001 adds r0, #1 8004e46: f43f af2a beq.w 8004c9e <_printf_float+0xae> 8004e4a: 3701 adds r7, #1 8004e4c: e7e7 b.n 8004e1e <_printf_float+0x22e> 8004e4e: 9b0d ldr r3, [sp, #52] ; 0x34 8004e50: 2b00 cmp r3, #0 8004e52: dc2b bgt.n 8004eac <_printf_float+0x2bc> 8004e54: 2301 movs r3, #1 8004e56: 4a26 ldr r2, [pc, #152] ; (8004ef0 <_printf_float+0x300>) 8004e58: 4659 mov r1, fp 8004e5a: 4628 mov r0, r5 8004e5c: 47b0 blx r6 8004e5e: 3001 adds r0, #1 8004e60: f43f af1d beq.w 8004c9e <_printf_float+0xae> 8004e64: 9b0d ldr r3, [sp, #52] ; 0x34 8004e66: b923 cbnz r3, 8004e72 <_printf_float+0x282> 8004e68: 9b0e ldr r3, [sp, #56] ; 0x38 8004e6a: b913 cbnz r3, 8004e72 <_printf_float+0x282> 8004e6c: 6823 ldr r3, [r4, #0] 8004e6e: 07d9 lsls r1, r3, #31 8004e70: d5d9 bpl.n 8004e26 <_printf_float+0x236> 8004e72: e9dd 2309 ldrd r2, r3, [sp, #36] ; 0x24 8004e76: 4659 mov r1, fp 8004e78: 4628 mov r0, r5 8004e7a: 47b0 blx r6 8004e7c: 3001 adds r0, #1 8004e7e: f43f af0e beq.w 8004c9e <_printf_float+0xae> 8004e82: f04f 0800 mov.w r8, #0 8004e86: f104 091a add.w r9, r4, #26 8004e8a: 9b0d ldr r3, [sp, #52] ; 0x34 8004e8c: 425b negs r3, r3 8004e8e: 4543 cmp r3, r8 8004e90: dc01 bgt.n 8004e96 <_printf_float+0x2a6> 8004e92: 9b0e ldr r3, [sp, #56] ; 0x38 8004e94: e797 b.n 8004dc6 <_printf_float+0x1d6> 8004e96: 2301 movs r3, #1 8004e98: 464a mov r2, r9 8004e9a: 4659 mov r1, fp 8004e9c: 4628 mov r0, r5 8004e9e: 47b0 blx r6 8004ea0: 3001 adds r0, #1 8004ea2: f43f aefc beq.w 8004c9e <_printf_float+0xae> 8004ea6: f108 0801 add.w r8, r8, #1 8004eaa: e7ee b.n 8004e8a <_printf_float+0x29a> 8004eac: 9a0e ldr r2, [sp, #56] ; 0x38 8004eae: 6da3 ldr r3, [r4, #88] ; 0x58 8004eb0: 429a cmp r2, r3 8004eb2: bfa8 it ge 8004eb4: 461a movge r2, r3 8004eb6: 2a00 cmp r2, #0 8004eb8: 4690 mov r8, r2 8004eba: dd07 ble.n 8004ecc <_printf_float+0x2dc> 8004ebc: 4613 mov r3, r2 8004ebe: 4659 mov r1, fp 8004ec0: 463a mov r2, r7 8004ec2: 4628 mov r0, r5 8004ec4: 47b0 blx r6 8004ec6: 3001 adds r0, #1 8004ec8: f43f aee9 beq.w 8004c9e <_printf_float+0xae> 8004ecc: f104 031a add.w r3, r4, #26 8004ed0: f04f 0a00 mov.w sl, #0 8004ed4: ea28 78e8 bic.w r8, r8, r8, asr #31 8004ed8: 930b str r3, [sp, #44] ; 0x2c 8004eda: e015 b.n 8004f08 <_printf_float+0x318> 8004edc: 7fefffff .word 0x7fefffff 8004ee0: 0800744c .word 0x0800744c 8004ee4: 08007448 .word 0x08007448 8004ee8: 08007454 .word 0x08007454 8004eec: 08007450 .word 0x08007450 8004ef0: 08007458 .word 0x08007458 8004ef4: 2301 movs r3, #1 8004ef6: 9a0b ldr r2, [sp, #44] ; 0x2c 8004ef8: 4659 mov r1, fp 8004efa: 4628 mov r0, r5 8004efc: 47b0 blx r6 8004efe: 3001 adds r0, #1 8004f00: f43f aecd beq.w 8004c9e <_printf_float+0xae> 8004f04: f10a 0a01 add.w sl, sl, #1 8004f08: f8d4 9058 ldr.w r9, [r4, #88] ; 0x58 8004f0c: eba9 0308 sub.w r3, r9, r8 8004f10: 4553 cmp r3, sl 8004f12: dcef bgt.n 8004ef4 <_printf_float+0x304> 8004f14: e9dd 230d ldrd r2, r3, [sp, #52] ; 0x34 8004f18: 429a cmp r2, r3 8004f1a: 444f add r7, r9 8004f1c: db14 blt.n 8004f48 <_printf_float+0x358> 8004f1e: 6823 ldr r3, [r4, #0] 8004f20: 07da lsls r2, r3, #31 8004f22: d411 bmi.n 8004f48 <_printf_float+0x358> 8004f24: 9b0e ldr r3, [sp, #56] ; 0x38 8004f26: 990d ldr r1, [sp, #52] ; 0x34 8004f28: eba3 0209 sub.w r2, r3, r9 8004f2c: eba3 0901 sub.w r9, r3, r1 8004f30: 4591 cmp r9, r2 8004f32: bfa8 it ge 8004f34: 4691 movge r9, r2 8004f36: f1b9 0f00 cmp.w r9, #0 8004f3a: dc0d bgt.n 8004f58 <_printf_float+0x368> 8004f3c: 2700 movs r7, #0 8004f3e: ea29 79e9 bic.w r9, r9, r9, asr #31 8004f42: f104 081a add.w r8, r4, #26 8004f46: e018 b.n 8004f7a <_printf_float+0x38a> 8004f48: e9dd 2309 ldrd r2, r3, [sp, #36] ; 0x24 8004f4c: 4659 mov r1, fp 8004f4e: 4628 mov r0, r5 8004f50: 47b0 blx r6 8004f52: 3001 adds r0, #1 8004f54: d1e6 bne.n 8004f24 <_printf_float+0x334> 8004f56: e6a2 b.n 8004c9e <_printf_float+0xae> 8004f58: 464b mov r3, r9 8004f5a: 463a mov r2, r7 8004f5c: 4659 mov r1, fp 8004f5e: 4628 mov r0, r5 8004f60: 47b0 blx r6 8004f62: 3001 adds r0, #1 8004f64: d1ea bne.n 8004f3c <_printf_float+0x34c> 8004f66: e69a b.n 8004c9e <_printf_float+0xae> 8004f68: 2301 movs r3, #1 8004f6a: 4642 mov r2, r8 8004f6c: 4659 mov r1, fp 8004f6e: 4628 mov r0, r5 8004f70: 47b0 blx r6 8004f72: 3001 adds r0, #1 8004f74: f43f ae93 beq.w 8004c9e <_printf_float+0xae> 8004f78: 3701 adds r7, #1 8004f7a: e9dd 230d ldrd r2, r3, [sp, #52] ; 0x34 8004f7e: 1a9b subs r3, r3, r2 8004f80: eba3 0309 sub.w r3, r3, r9 8004f84: 42bb cmp r3, r7 8004f86: dcef bgt.n 8004f68 <_printf_float+0x378> 8004f88: e74d b.n 8004e26 <_printf_float+0x236> 8004f8a: 9a0e ldr r2, [sp, #56] ; 0x38 8004f8c: 2a01 cmp r2, #1 8004f8e: dc01 bgt.n 8004f94 <_printf_float+0x3a4> 8004f90: 07db lsls r3, r3, #31 8004f92: d538 bpl.n 8005006 <_printf_float+0x416> 8004f94: 2301 movs r3, #1 8004f96: 463a mov r2, r7 8004f98: 4659 mov r1, fp 8004f9a: 4628 mov r0, r5 8004f9c: 47b0 blx r6 8004f9e: 3001 adds r0, #1 8004fa0: f43f ae7d beq.w 8004c9e <_printf_float+0xae> 8004fa4: e9dd 2309 ldrd r2, r3, [sp, #36] ; 0x24 8004fa8: 4659 mov r1, fp 8004faa: 4628 mov r0, r5 8004fac: 47b0 blx r6 8004fae: 3001 adds r0, #1 8004fb0: f107 0701 add.w r7, r7, #1 8004fb4: f43f ae73 beq.w 8004c9e <_printf_float+0xae> 8004fb8: e9d4 0112 ldrd r0, r1, [r4, #72] ; 0x48 8004fbc: 9b0e ldr r3, [sp, #56] ; 0x38 8004fbe: 2200 movs r2, #0 8004fc0: f103 38ff add.w r8, r3, #4294967295 8004fc4: 2300 movs r3, #0 8004fc6: f7fb fd4f bl 8000a68 <__aeabi_dcmpeq> 8004fca: b9c0 cbnz r0, 8004ffe <_printf_float+0x40e> 8004fcc: 4643 mov r3, r8 8004fce: 463a mov r2, r7 8004fd0: 4659 mov r1, fp 8004fd2: 4628 mov r0, r5 8004fd4: 47b0 blx r6 8004fd6: 3001 adds r0, #1 8004fd8: d10d bne.n 8004ff6 <_printf_float+0x406> 8004fda: e660 b.n 8004c9e <_printf_float+0xae> 8004fdc: 2301 movs r3, #1 8004fde: 4642 mov r2, r8 8004fe0: 4659 mov r1, fp 8004fe2: 4628 mov r0, r5 8004fe4: 47b0 blx r6 8004fe6: 3001 adds r0, #1 8004fe8: f43f ae59 beq.w 8004c9e <_printf_float+0xae> 8004fec: 3701 adds r7, #1 8004fee: 9b0e ldr r3, [sp, #56] ; 0x38 8004ff0: 3b01 subs r3, #1 8004ff2: 42bb cmp r3, r7 8004ff4: dcf2 bgt.n 8004fdc <_printf_float+0x3ec> 8004ff6: 464b mov r3, r9 8004ff8: f104 0250 add.w r2, r4, #80 ; 0x50 8004ffc: e6e4 b.n 8004dc8 <_printf_float+0x1d8> 8004ffe: 2700 movs r7, #0 8005000: f104 081a add.w r8, r4, #26 8005004: e7f3 b.n 8004fee <_printf_float+0x3fe> 8005006: 2301 movs r3, #1 8005008: e7e1 b.n 8004fce <_printf_float+0x3de> 800500a: 2301 movs r3, #1 800500c: 4642 mov r2, r8 800500e: 4659 mov r1, fp 8005010: 4628 mov r0, r5 8005012: 47b0 blx r6 8005014: 3001 adds r0, #1 8005016: f43f ae42 beq.w 8004c9e <_printf_float+0xae> 800501a: 3701 adds r7, #1 800501c: 68e3 ldr r3, [r4, #12] 800501e: 9a0f ldr r2, [sp, #60] ; 0x3c 8005020: 1a9b subs r3, r3, r2 8005022: 42bb cmp r3, r7 8005024: dcf1 bgt.n 800500a <_printf_float+0x41a> 8005026: e702 b.n 8004e2e <_printf_float+0x23e> 8005028: 2700 movs r7, #0 800502a: f104 0819 add.w r8, r4, #25 800502e: e7f5 b.n 800501c <_printf_float+0x42c> 8005030: 2b00 cmp r3, #0 8005032: f43f ae94 beq.w 8004d5e <_printf_float+0x16e> 8005036: f04f 0c00 mov.w ip, #0 800503a: e9cd 1c05 strd r1, ip, [sp, #20] 800503e: f10d 0133 add.w r1, sp, #51 ; 0x33 8005042: 6022 str r2, [r4, #0] 8005044: e9cd 0803 strd r0, r8, [sp, #12] 8005048: e9cd 2101 strd r2, r1, [sp, #4] 800504c: 9300 str r3, [sp, #0] 800504e: 463a mov r2, r7 8005050: 464b mov r3, r9 8005052: 4628 mov r0, r5 8005054: f7ff fd3a bl 8004acc <__cvt> 8005058: 4607 mov r7, r0 800505a: e64f b.n 8004cfc <_printf_float+0x10c> 0800505c <_printf_common>: 800505c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8005060: 4691 mov r9, r2 8005062: 461f mov r7, r3 8005064: 688a ldr r2, [r1, #8] 8005066: 690b ldr r3, [r1, #16] 8005068: 4606 mov r6, r0 800506a: 4293 cmp r3, r2 800506c: bfb8 it lt 800506e: 4613 movlt r3, r2 8005070: f8c9 3000 str.w r3, [r9] 8005074: f891 2043 ldrb.w r2, [r1, #67] ; 0x43 8005078: 460c mov r4, r1 800507a: f8dd 8020 ldr.w r8, [sp, #32] 800507e: b112 cbz r2, 8005086 <_printf_common+0x2a> 8005080: 3301 adds r3, #1 8005082: f8c9 3000 str.w r3, [r9] 8005086: 6823 ldr r3, [r4, #0] 8005088: 0699 lsls r1, r3, #26 800508a: bf42 ittt mi 800508c: f8d9 3000 ldrmi.w r3, [r9] 8005090: 3302 addmi r3, #2 8005092: f8c9 3000 strmi.w r3, [r9] 8005096: 6825 ldr r5, [r4, #0] 8005098: f015 0506 ands.w r5, r5, #6 800509c: d107 bne.n 80050ae <_printf_common+0x52> 800509e: f104 0a19 add.w sl, r4, #25 80050a2: 68e3 ldr r3, [r4, #12] 80050a4: f8d9 2000 ldr.w r2, [r9] 80050a8: 1a9b subs r3, r3, r2 80050aa: 42ab cmp r3, r5 80050ac: dc29 bgt.n 8005102 <_printf_common+0xa6> 80050ae: f894 3043 ldrb.w r3, [r4, #67] ; 0x43 80050b2: 6822 ldr r2, [r4, #0] 80050b4: 3300 adds r3, #0 80050b6: bf18 it ne 80050b8: 2301 movne r3, #1 80050ba: 0692 lsls r2, r2, #26 80050bc: d42e bmi.n 800511c <_printf_common+0xc0> 80050be: f104 0243 add.w r2, r4, #67 ; 0x43 80050c2: 4639 mov r1, r7 80050c4: 4630 mov r0, r6 80050c6: 47c0 blx r8 80050c8: 3001 adds r0, #1 80050ca: d021 beq.n 8005110 <_printf_common+0xb4> 80050cc: 6823 ldr r3, [r4, #0] 80050ce: 68e5 ldr r5, [r4, #12] 80050d0: f003 0306 and.w r3, r3, #6 80050d4: 2b04 cmp r3, #4 80050d6: bf18 it ne 80050d8: 2500 movne r5, #0 80050da: f8d9 2000 ldr.w r2, [r9] 80050de: f04f 0900 mov.w r9, #0 80050e2: bf08 it eq 80050e4: 1aad subeq r5, r5, r2 80050e6: 68a3 ldr r3, [r4, #8] 80050e8: 6922 ldr r2, [r4, #16] 80050ea: bf08 it eq 80050ec: ea25 75e5 biceq.w r5, r5, r5, asr #31 80050f0: 4293 cmp r3, r2 80050f2: bfc4 itt gt 80050f4: 1a9b subgt r3, r3, r2 80050f6: 18ed addgt r5, r5, r3 80050f8: 341a adds r4, #26 80050fa: 454d cmp r5, r9 80050fc: d11a bne.n 8005134 <_printf_common+0xd8> 80050fe: 2000 movs r0, #0 8005100: e008 b.n 8005114 <_printf_common+0xb8> 8005102: 2301 movs r3, #1 8005104: 4652 mov r2, sl 8005106: 4639 mov r1, r7 8005108: 4630 mov r0, r6 800510a: 47c0 blx r8 800510c: 3001 adds r0, #1 800510e: d103 bne.n 8005118 <_printf_common+0xbc> 8005110: f04f 30ff mov.w r0, #4294967295 8005114: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8005118: 3501 adds r5, #1 800511a: e7c2 b.n 80050a2 <_printf_common+0x46> 800511c: 2030 movs r0, #48 ; 0x30 800511e: 18e1 adds r1, r4, r3 8005120: f881 0043 strb.w r0, [r1, #67] ; 0x43 8005124: 1c5a adds r2, r3, #1 8005126: f894 1045 ldrb.w r1, [r4, #69] ; 0x45 800512a: 4422 add r2, r4 800512c: 3302 adds r3, #2 800512e: f882 1043 strb.w r1, [r2, #67] ; 0x43 8005132: e7c4 b.n 80050be <_printf_common+0x62> 8005134: 2301 movs r3, #1 8005136: 4622 mov r2, r4 8005138: 4639 mov r1, r7 800513a: 4630 mov r0, r6 800513c: 47c0 blx r8 800513e: 3001 adds r0, #1 8005140: d0e6 beq.n 8005110 <_printf_common+0xb4> 8005142: f109 0901 add.w r9, r9, #1 8005146: e7d8 b.n 80050fa <_printf_common+0x9e> 08005148 <_printf_i>: 8005148: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} 800514c: f101 0c43 add.w ip, r1, #67 ; 0x43 8005150: 460c mov r4, r1 8005152: 7e09 ldrb r1, [r1, #24] 8005154: b085 sub sp, #20 8005156: 296e cmp r1, #110 ; 0x6e 8005158: 4617 mov r7, r2 800515a: 4606 mov r6, r0 800515c: 4698 mov r8, r3 800515e: 9a0c ldr r2, [sp, #48] ; 0x30 8005160: f000 80b3 beq.w 80052ca <_printf_i+0x182> 8005164: d822 bhi.n 80051ac <_printf_i+0x64> 8005166: 2963 cmp r1, #99 ; 0x63 8005168: d036 beq.n 80051d8 <_printf_i+0x90> 800516a: d80a bhi.n 8005182 <_printf_i+0x3a> 800516c: 2900 cmp r1, #0 800516e: f000 80b9 beq.w 80052e4 <_printf_i+0x19c> 8005172: 2958 cmp r1, #88 ; 0x58 8005174: f000 8083 beq.w 800527e <_printf_i+0x136> 8005178: f104 0542 add.w r5, r4, #66 ; 0x42 800517c: f884 1042 strb.w r1, [r4, #66] ; 0x42 8005180: e032 b.n 80051e8 <_printf_i+0xa0> 8005182: 2964 cmp r1, #100 ; 0x64 8005184: d001 beq.n 800518a <_printf_i+0x42> 8005186: 2969 cmp r1, #105 ; 0x69 8005188: d1f6 bne.n 8005178 <_printf_i+0x30> 800518a: 6820 ldr r0, [r4, #0] 800518c: 6813 ldr r3, [r2, #0] 800518e: 0605 lsls r5, r0, #24 8005190: f103 0104 add.w r1, r3, #4 8005194: d52a bpl.n 80051ec <_printf_i+0xa4> 8005196: 681b ldr r3, [r3, #0] 8005198: 6011 str r1, [r2, #0] 800519a: 2b00 cmp r3, #0 800519c: da03 bge.n 80051a6 <_printf_i+0x5e> 800519e: 222d movs r2, #45 ; 0x2d 80051a0: 425b negs r3, r3 80051a2: f884 2043 strb.w r2, [r4, #67] ; 0x43 80051a6: 486f ldr r0, [pc, #444] ; (8005364 <_printf_i+0x21c>) 80051a8: 220a movs r2, #10 80051aa: e039 b.n 8005220 <_printf_i+0xd8> 80051ac: 2973 cmp r1, #115 ; 0x73 80051ae: f000 809d beq.w 80052ec <_printf_i+0x1a4> 80051b2: d808 bhi.n 80051c6 <_printf_i+0x7e> 80051b4: 296f cmp r1, #111 ; 0x6f 80051b6: d020 beq.n 80051fa <_printf_i+0xb2> 80051b8: 2970 cmp r1, #112 ; 0x70 80051ba: d1dd bne.n 8005178 <_printf_i+0x30> 80051bc: 6823 ldr r3, [r4, #0] 80051be: f043 0320 orr.w r3, r3, #32 80051c2: 6023 str r3, [r4, #0] 80051c4: e003 b.n 80051ce <_printf_i+0x86> 80051c6: 2975 cmp r1, #117 ; 0x75 80051c8: d017 beq.n 80051fa <_printf_i+0xb2> 80051ca: 2978 cmp r1, #120 ; 0x78 80051cc: d1d4 bne.n 8005178 <_printf_i+0x30> 80051ce: 2378 movs r3, #120 ; 0x78 80051d0: 4865 ldr r0, [pc, #404] ; (8005368 <_printf_i+0x220>) 80051d2: f884 3045 strb.w r3, [r4, #69] ; 0x45 80051d6: e055 b.n 8005284 <_printf_i+0x13c> 80051d8: 6813 ldr r3, [r2, #0] 80051da: f104 0542 add.w r5, r4, #66 ; 0x42 80051de: 1d19 adds r1, r3, #4 80051e0: 681b ldr r3, [r3, #0] 80051e2: 6011 str r1, [r2, #0] 80051e4: f884 3042 strb.w r3, [r4, #66] ; 0x42 80051e8: 2301 movs r3, #1 80051ea: e08c b.n 8005306 <_printf_i+0x1be> 80051ec: 681b ldr r3, [r3, #0] 80051ee: f010 0f40 tst.w r0, #64 ; 0x40 80051f2: 6011 str r1, [r2, #0] 80051f4: bf18 it ne 80051f6: b21b sxthne r3, r3 80051f8: e7cf b.n 800519a <_printf_i+0x52> 80051fa: 6813 ldr r3, [r2, #0] 80051fc: 6825 ldr r5, [r4, #0] 80051fe: 1d18 adds r0, r3, #4 8005200: 6010 str r0, [r2, #0] 8005202: 0628 lsls r0, r5, #24 8005204: d501 bpl.n 800520a <_printf_i+0xc2> 8005206: 681b ldr r3, [r3, #0] 8005208: e002 b.n 8005210 <_printf_i+0xc8> 800520a: 0668 lsls r0, r5, #25 800520c: d5fb bpl.n 8005206 <_printf_i+0xbe> 800520e: 881b ldrh r3, [r3, #0] 8005210: 296f cmp r1, #111 ; 0x6f 8005212: bf14 ite ne 8005214: 220a movne r2, #10 8005216: 2208 moveq r2, #8 8005218: 4852 ldr r0, [pc, #328] ; (8005364 <_printf_i+0x21c>) 800521a: 2100 movs r1, #0 800521c: f884 1043 strb.w r1, [r4, #67] ; 0x43 8005220: 6865 ldr r5, [r4, #4] 8005222: 2d00 cmp r5, #0 8005224: 60a5 str r5, [r4, #8] 8005226: f2c0 8095 blt.w 8005354 <_printf_i+0x20c> 800522a: 6821 ldr r1, [r4, #0] 800522c: f021 0104 bic.w r1, r1, #4 8005230: 6021 str r1, [r4, #0] 8005232: 2b00 cmp r3, #0 8005234: d13d bne.n 80052b2 <_printf_i+0x16a> 8005236: 2d00 cmp r5, #0 8005238: f040 808e bne.w 8005358 <_printf_i+0x210> 800523c: 4665 mov r5, ip 800523e: 2a08 cmp r2, #8 8005240: d10b bne.n 800525a <_printf_i+0x112> 8005242: 6823 ldr r3, [r4, #0] 8005244: 07db lsls r3, r3, #31 8005246: d508 bpl.n 800525a <_printf_i+0x112> 8005248: 6923 ldr r3, [r4, #16] 800524a: 6862 ldr r2, [r4, #4] 800524c: 429a cmp r2, r3 800524e: bfde ittt le 8005250: 2330 movle r3, #48 ; 0x30 8005252: f805 3c01 strble.w r3, [r5, #-1] 8005256: f105 35ff addle.w r5, r5, #4294967295 800525a: ebac 0305 sub.w r3, ip, r5 800525e: 6123 str r3, [r4, #16] 8005260: f8cd 8000 str.w r8, [sp] 8005264: 463b mov r3, r7 8005266: aa03 add r2, sp, #12 8005268: 4621 mov r1, r4 800526a: 4630 mov r0, r6 800526c: f7ff fef6 bl 800505c <_printf_common> 8005270: 3001 adds r0, #1 8005272: d14d bne.n 8005310 <_printf_i+0x1c8> 8005274: f04f 30ff mov.w r0, #4294967295 8005278: b005 add sp, #20 800527a: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} 800527e: 4839 ldr r0, [pc, #228] ; (8005364 <_printf_i+0x21c>) 8005280: f884 1045 strb.w r1, [r4, #69] ; 0x45 8005284: 6813 ldr r3, [r2, #0] 8005286: 6821 ldr r1, [r4, #0] 8005288: 1d1d adds r5, r3, #4 800528a: 681b ldr r3, [r3, #0] 800528c: 6015 str r5, [r2, #0] 800528e: 060a lsls r2, r1, #24 8005290: d50b bpl.n 80052aa <_printf_i+0x162> 8005292: 07ca lsls r2, r1, #31 8005294: bf44 itt mi 8005296: f041 0120 orrmi.w r1, r1, #32 800529a: 6021 strmi r1, [r4, #0] 800529c: b91b cbnz r3, 80052a6 <_printf_i+0x15e> 800529e: 6822 ldr r2, [r4, #0] 80052a0: f022 0220 bic.w r2, r2, #32 80052a4: 6022 str r2, [r4, #0] 80052a6: 2210 movs r2, #16 80052a8: e7b7 b.n 800521a <_printf_i+0xd2> 80052aa: 064d lsls r5, r1, #25 80052ac: bf48 it mi 80052ae: b29b uxthmi r3, r3 80052b0: e7ef b.n 8005292 <_printf_i+0x14a> 80052b2: 4665 mov r5, ip 80052b4: fbb3 f1f2 udiv r1, r3, r2 80052b8: fb02 3311 mls r3, r2, r1, r3 80052bc: 5cc3 ldrb r3, [r0, r3] 80052be: f805 3d01 strb.w r3, [r5, #-1]! 80052c2: 460b mov r3, r1 80052c4: 2900 cmp r1, #0 80052c6: d1f5 bne.n 80052b4 <_printf_i+0x16c> 80052c8: e7b9 b.n 800523e <_printf_i+0xf6> 80052ca: 6813 ldr r3, [r2, #0] 80052cc: 6825 ldr r5, [r4, #0] 80052ce: 1d18 adds r0, r3, #4 80052d0: 6961 ldr r1, [r4, #20] 80052d2: 6010 str r0, [r2, #0] 80052d4: 0628 lsls r0, r5, #24 80052d6: 681b ldr r3, [r3, #0] 80052d8: d501 bpl.n 80052de <_printf_i+0x196> 80052da: 6019 str r1, [r3, #0] 80052dc: e002 b.n 80052e4 <_printf_i+0x19c> 80052de: 066a lsls r2, r5, #25 80052e0: d5fb bpl.n 80052da <_printf_i+0x192> 80052e2: 8019 strh r1, [r3, #0] 80052e4: 2300 movs r3, #0 80052e6: 4665 mov r5, ip 80052e8: 6123 str r3, [r4, #16] 80052ea: e7b9 b.n 8005260 <_printf_i+0x118> 80052ec: 6813 ldr r3, [r2, #0] 80052ee: 1d19 adds r1, r3, #4 80052f0: 6011 str r1, [r2, #0] 80052f2: 681d ldr r5, [r3, #0] 80052f4: 6862 ldr r2, [r4, #4] 80052f6: 2100 movs r1, #0 80052f8: 4628 mov r0, r5 80052fa: f001 fa61 bl 80067c0 80052fe: b108 cbz r0, 8005304 <_printf_i+0x1bc> 8005300: 1b40 subs r0, r0, r5 8005302: 6060 str r0, [r4, #4] 8005304: 6863 ldr r3, [r4, #4] 8005306: 6123 str r3, [r4, #16] 8005308: 2300 movs r3, #0 800530a: f884 3043 strb.w r3, [r4, #67] ; 0x43 800530e: e7a7 b.n 8005260 <_printf_i+0x118> 8005310: 6923 ldr r3, [r4, #16] 8005312: 462a mov r2, r5 8005314: 4639 mov r1, r7 8005316: 4630 mov r0, r6 8005318: 47c0 blx r8 800531a: 3001 adds r0, #1 800531c: d0aa beq.n 8005274 <_printf_i+0x12c> 800531e: 6823 ldr r3, [r4, #0] 8005320: 079b lsls r3, r3, #30 8005322: d413 bmi.n 800534c <_printf_i+0x204> 8005324: 68e0 ldr r0, [r4, #12] 8005326: 9b03 ldr r3, [sp, #12] 8005328: 4298 cmp r0, r3 800532a: bfb8 it lt 800532c: 4618 movlt r0, r3 800532e: e7a3 b.n 8005278 <_printf_i+0x130> 8005330: 2301 movs r3, #1 8005332: 464a mov r2, r9 8005334: 4639 mov r1, r7 8005336: 4630 mov r0, r6 8005338: 47c0 blx r8 800533a: 3001 adds r0, #1 800533c: d09a beq.n 8005274 <_printf_i+0x12c> 800533e: 3501 adds r5, #1 8005340: 68e3 ldr r3, [r4, #12] 8005342: 9a03 ldr r2, [sp, #12] 8005344: 1a9b subs r3, r3, r2 8005346: 42ab cmp r3, r5 8005348: dcf2 bgt.n 8005330 <_printf_i+0x1e8> 800534a: e7eb b.n 8005324 <_printf_i+0x1dc> 800534c: 2500 movs r5, #0 800534e: f104 0919 add.w r9, r4, #25 8005352: e7f5 b.n 8005340 <_printf_i+0x1f8> 8005354: 2b00 cmp r3, #0 8005356: d1ac bne.n 80052b2 <_printf_i+0x16a> 8005358: 7803 ldrb r3, [r0, #0] 800535a: f104 0542 add.w r5, r4, #66 ; 0x42 800535e: f884 3042 strb.w r3, [r4, #66] ; 0x42 8005362: e76c b.n 800523e <_printf_i+0xf6> 8005364: 0800745a .word 0x0800745a 8005368: 0800746b .word 0x0800746b 0800536c : 800536c: b40f push {r0, r1, r2, r3} 800536e: 4b0a ldr r3, [pc, #40] ; (8005398 ) 8005370: b513 push {r0, r1, r4, lr} 8005372: 681c ldr r4, [r3, #0] 8005374: b124 cbz r4, 8005380 8005376: 69a3 ldr r3, [r4, #24] 8005378: b913 cbnz r3, 8005380 800537a: 4620 mov r0, r4 800537c: f001 f91c bl 80065b8 <__sinit> 8005380: ab05 add r3, sp, #20 8005382: 9a04 ldr r2, [sp, #16] 8005384: 68a1 ldr r1, [r4, #8] 8005386: 4620 mov r0, r4 8005388: 9301 str r3, [sp, #4] 800538a: f001 fdeb bl 8006f64 <_vfiprintf_r> 800538e: b002 add sp, #8 8005390: e8bd 4010 ldmia.w sp!, {r4, lr} 8005394: b004 add sp, #16 8005396: 4770 bx lr 8005398: 2000000c .word 0x2000000c 0800539c <_puts_r>: 800539c: b570 push {r4, r5, r6, lr} 800539e: 460e mov r6, r1 80053a0: 4605 mov r5, r0 80053a2: b118 cbz r0, 80053ac <_puts_r+0x10> 80053a4: 6983 ldr r3, [r0, #24] 80053a6: b90b cbnz r3, 80053ac <_puts_r+0x10> 80053a8: f001 f906 bl 80065b8 <__sinit> 80053ac: 69ab ldr r3, [r5, #24] 80053ae: 68ac ldr r4, [r5, #8] 80053b0: b913 cbnz r3, 80053b8 <_puts_r+0x1c> 80053b2: 4628 mov r0, r5 80053b4: f001 f900 bl 80065b8 <__sinit> 80053b8: 4b23 ldr r3, [pc, #140] ; (8005448 <_puts_r+0xac>) 80053ba: 429c cmp r4, r3 80053bc: d117 bne.n 80053ee <_puts_r+0x52> 80053be: 686c ldr r4, [r5, #4] 80053c0: 89a3 ldrh r3, [r4, #12] 80053c2: 071b lsls r3, r3, #28 80053c4: d51d bpl.n 8005402 <_puts_r+0x66> 80053c6: 6923 ldr r3, [r4, #16] 80053c8: b1db cbz r3, 8005402 <_puts_r+0x66> 80053ca: 3e01 subs r6, #1 80053cc: 68a3 ldr r3, [r4, #8] 80053ce: f816 1f01 ldrb.w r1, [r6, #1]! 80053d2: 3b01 subs r3, #1 80053d4: 60a3 str r3, [r4, #8] 80053d6: b9e9 cbnz r1, 8005414 <_puts_r+0x78> 80053d8: 2b00 cmp r3, #0 80053da: da2e bge.n 800543a <_puts_r+0x9e> 80053dc: 4622 mov r2, r4 80053de: 210a movs r1, #10 80053e0: 4628 mov r0, r5 80053e2: f000 f8f5 bl 80055d0 <__swbuf_r> 80053e6: 3001 adds r0, #1 80053e8: d011 beq.n 800540e <_puts_r+0x72> 80053ea: 200a movs r0, #10 80053ec: e011 b.n 8005412 <_puts_r+0x76> 80053ee: 4b17 ldr r3, [pc, #92] ; (800544c <_puts_r+0xb0>) 80053f0: 429c cmp r4, r3 80053f2: d101 bne.n 80053f8 <_puts_r+0x5c> 80053f4: 68ac ldr r4, [r5, #8] 80053f6: e7e3 b.n 80053c0 <_puts_r+0x24> 80053f8: 4b15 ldr r3, [pc, #84] ; (8005450 <_puts_r+0xb4>) 80053fa: 429c cmp r4, r3 80053fc: bf08 it eq 80053fe: 68ec ldreq r4, [r5, #12] 8005400: e7de b.n 80053c0 <_puts_r+0x24> 8005402: 4621 mov r1, r4 8005404: 4628 mov r0, r5 8005406: f000 f935 bl 8005674 <__swsetup_r> 800540a: 2800 cmp r0, #0 800540c: d0dd beq.n 80053ca <_puts_r+0x2e> 800540e: f04f 30ff mov.w r0, #4294967295 8005412: bd70 pop {r4, r5, r6, pc} 8005414: 2b00 cmp r3, #0 8005416: da04 bge.n 8005422 <_puts_r+0x86> 8005418: 69a2 ldr r2, [r4, #24] 800541a: 429a cmp r2, r3 800541c: dc06 bgt.n 800542c <_puts_r+0x90> 800541e: 290a cmp r1, #10 8005420: d004 beq.n 800542c <_puts_r+0x90> 8005422: 6823 ldr r3, [r4, #0] 8005424: 1c5a adds r2, r3, #1 8005426: 6022 str r2, [r4, #0] 8005428: 7019 strb r1, [r3, #0] 800542a: e7cf b.n 80053cc <_puts_r+0x30> 800542c: 4622 mov r2, r4 800542e: 4628 mov r0, r5 8005430: f000 f8ce bl 80055d0 <__swbuf_r> 8005434: 3001 adds r0, #1 8005436: d1c9 bne.n 80053cc <_puts_r+0x30> 8005438: e7e9 b.n 800540e <_puts_r+0x72> 800543a: 200a movs r0, #10 800543c: 6823 ldr r3, [r4, #0] 800543e: 1c5a adds r2, r3, #1 8005440: 6022 str r2, [r4, #0] 8005442: 7018 strb r0, [r3, #0] 8005444: e7e5 b.n 8005412 <_puts_r+0x76> 8005446: bf00 nop 8005448: 080074ac .word 0x080074ac 800544c: 080074cc .word 0x080074cc 8005450: 0800748c .word 0x0800748c 08005454 : 8005454: 4b02 ldr r3, [pc, #8] ; (8005460 ) 8005456: 4601 mov r1, r0 8005458: 6818 ldr r0, [r3, #0] 800545a: f7ff bf9f b.w 800539c <_puts_r> 800545e: bf00 nop 8005460: 2000000c .word 0x2000000c 08005464 : 8005464: 2900 cmp r1, #0 8005466: f44f 6380 mov.w r3, #1024 ; 0x400 800546a: bf0c ite eq 800546c: 2202 moveq r2, #2 800546e: 2200 movne r2, #0 8005470: f000 b800 b.w 8005474 08005474 : 8005474: e92d 43f7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr} 8005478: 461d mov r5, r3 800547a: 4b51 ldr r3, [pc, #324] ; (80055c0 ) 800547c: 4604 mov r4, r0 800547e: 681e ldr r6, [r3, #0] 8005480: 460f mov r7, r1 8005482: 4690 mov r8, r2 8005484: b126 cbz r6, 8005490 8005486: 69b3 ldr r3, [r6, #24] 8005488: b913 cbnz r3, 8005490 800548a: 4630 mov r0, r6 800548c: f001 f894 bl 80065b8 <__sinit> 8005490: 4b4c ldr r3, [pc, #304] ; (80055c4 ) 8005492: 429c cmp r4, r3 8005494: d152 bne.n 800553c 8005496: 6874 ldr r4, [r6, #4] 8005498: f1b8 0f02 cmp.w r8, #2 800549c: d006 beq.n 80054ac 800549e: f1b8 0f01 cmp.w r8, #1 80054a2: f200 8089 bhi.w 80055b8 80054a6: 2d00 cmp r5, #0 80054a8: f2c0 8086 blt.w 80055b8 80054ac: 4621 mov r1, r4 80054ae: 4630 mov r0, r6 80054b0: f001 f818 bl 80064e4 <_fflush_r> 80054b4: 6b61 ldr r1, [r4, #52] ; 0x34 80054b6: b141 cbz r1, 80054ca 80054b8: f104 0344 add.w r3, r4, #68 ; 0x44 80054bc: 4299 cmp r1, r3 80054be: d002 beq.n 80054c6 80054c0: 4630 mov r0, r6 80054c2: f001 fc81 bl 8006dc8 <_free_r> 80054c6: 2300 movs r3, #0 80054c8: 6363 str r3, [r4, #52] ; 0x34 80054ca: 2300 movs r3, #0 80054cc: 61a3 str r3, [r4, #24] 80054ce: 6063 str r3, [r4, #4] 80054d0: 89a3 ldrh r3, [r4, #12] 80054d2: 061b lsls r3, r3, #24 80054d4: d503 bpl.n 80054de 80054d6: 6921 ldr r1, [r4, #16] 80054d8: 4630 mov r0, r6 80054da: f001 fc75 bl 8006dc8 <_free_r> 80054de: 89a3 ldrh r3, [r4, #12] 80054e0: f1b8 0f02 cmp.w r8, #2 80054e4: f423 634a bic.w r3, r3, #3232 ; 0xca0 80054e8: f023 0303 bic.w r3, r3, #3 80054ec: 81a3 strh r3, [r4, #12] 80054ee: d05d beq.n 80055ac 80054f0: ab01 add r3, sp, #4 80054f2: 466a mov r2, sp 80054f4: 4621 mov r1, r4 80054f6: 4630 mov r0, r6 80054f8: f001 f8f6 bl 80066e8 <__swhatbuf_r> 80054fc: 89a3 ldrh r3, [r4, #12] 80054fe: 4318 orrs r0, r3 8005500: 81a0 strh r0, [r4, #12] 8005502: bb2d cbnz r5, 8005550 8005504: 9d00 ldr r5, [sp, #0] 8005506: 4628 mov r0, r5 8005508: f001 f952 bl 80067b0 800550c: 4607 mov r7, r0 800550e: 2800 cmp r0, #0 8005510: d14e bne.n 80055b0 8005512: f8dd 9000 ldr.w r9, [sp] 8005516: 45a9 cmp r9, r5 8005518: d13c bne.n 8005594 800551a: f04f 30ff mov.w r0, #4294967295 800551e: 89a3 ldrh r3, [r4, #12] 8005520: f043 0302 orr.w r3, r3, #2 8005524: 81a3 strh r3, [r4, #12] 8005526: 2300 movs r3, #0 8005528: 60a3 str r3, [r4, #8] 800552a: f104 0347 add.w r3, r4, #71 ; 0x47 800552e: 6023 str r3, [r4, #0] 8005530: 6123 str r3, [r4, #16] 8005532: 2301 movs r3, #1 8005534: 6163 str r3, [r4, #20] 8005536: b003 add sp, #12 8005538: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} 800553c: 4b22 ldr r3, [pc, #136] ; (80055c8 ) 800553e: 429c cmp r4, r3 8005540: d101 bne.n 8005546 8005542: 68b4 ldr r4, [r6, #8] 8005544: e7a8 b.n 8005498 8005546: 4b21 ldr r3, [pc, #132] ; (80055cc ) 8005548: 429c cmp r4, r3 800554a: bf08 it eq 800554c: 68f4 ldreq r4, [r6, #12] 800554e: e7a3 b.n 8005498 8005550: 2f00 cmp r7, #0 8005552: d0d8 beq.n 8005506 8005554: 69b3 ldr r3, [r6, #24] 8005556: b913 cbnz r3, 800555e 8005558: 4630 mov r0, r6 800555a: f001 f82d bl 80065b8 <__sinit> 800555e: f1b8 0f01 cmp.w r8, #1 8005562: bf08 it eq 8005564: 89a3 ldrheq r3, [r4, #12] 8005566: 6027 str r7, [r4, #0] 8005568: bf04 itt eq 800556a: f043 0301 orreq.w r3, r3, #1 800556e: 81a3 strheq r3, [r4, #12] 8005570: 89a3 ldrh r3, [r4, #12] 8005572: e9c4 7504 strd r7, r5, [r4, #16] 8005576: f013 0008 ands.w r0, r3, #8 800557a: d01b beq.n 80055b4 800557c: f013 0001 ands.w r0, r3, #1 8005580: f04f 0300 mov.w r3, #0 8005584: bf1f itttt ne 8005586: 426d negne r5, r5 8005588: 60a3 strne r3, [r4, #8] 800558a: 61a5 strne r5, [r4, #24] 800558c: 4618 movne r0, r3 800558e: bf08 it eq 8005590: 60a5 streq r5, [r4, #8] 8005592: e7d0 b.n 8005536 8005594: 4648 mov r0, r9 8005596: f001 f90b bl 80067b0 800559a: 4607 mov r7, r0 800559c: 2800 cmp r0, #0 800559e: d0bc beq.n 800551a 80055a0: 89a3 ldrh r3, [r4, #12] 80055a2: 464d mov r5, r9 80055a4: f043 0380 orr.w r3, r3, #128 ; 0x80 80055a8: 81a3 strh r3, [r4, #12] 80055aa: e7d3 b.n 8005554 80055ac: 2000 movs r0, #0 80055ae: e7b6 b.n 800551e 80055b0: 46a9 mov r9, r5 80055b2: e7f5 b.n 80055a0 80055b4: 60a0 str r0, [r4, #8] 80055b6: e7be b.n 8005536 80055b8: f04f 30ff mov.w r0, #4294967295 80055bc: e7bb b.n 8005536 80055be: bf00 nop 80055c0: 2000000c .word 0x2000000c 80055c4: 080074ac .word 0x080074ac 80055c8: 080074cc .word 0x080074cc 80055cc: 0800748c .word 0x0800748c 080055d0 <__swbuf_r>: 80055d0: b5f8 push {r3, r4, r5, r6, r7, lr} 80055d2: 460e mov r6, r1 80055d4: 4614 mov r4, r2 80055d6: 4605 mov r5, r0 80055d8: b118 cbz r0, 80055e2 <__swbuf_r+0x12> 80055da: 6983 ldr r3, [r0, #24] 80055dc: b90b cbnz r3, 80055e2 <__swbuf_r+0x12> 80055de: f000 ffeb bl 80065b8 <__sinit> 80055e2: 4b21 ldr r3, [pc, #132] ; (8005668 <__swbuf_r+0x98>) 80055e4: 429c cmp r4, r3 80055e6: d12a bne.n 800563e <__swbuf_r+0x6e> 80055e8: 686c ldr r4, [r5, #4] 80055ea: 69a3 ldr r3, [r4, #24] 80055ec: 60a3 str r3, [r4, #8] 80055ee: 89a3 ldrh r3, [r4, #12] 80055f0: 071a lsls r2, r3, #28 80055f2: d52e bpl.n 8005652 <__swbuf_r+0x82> 80055f4: 6923 ldr r3, [r4, #16] 80055f6: b363 cbz r3, 8005652 <__swbuf_r+0x82> 80055f8: 6923 ldr r3, [r4, #16] 80055fa: 6820 ldr r0, [r4, #0] 80055fc: b2f6 uxtb r6, r6 80055fe: 1ac0 subs r0, r0, r3 8005600: 6963 ldr r3, [r4, #20] 8005602: 4637 mov r7, r6 8005604: 4283 cmp r3, r0 8005606: dc04 bgt.n 8005612 <__swbuf_r+0x42> 8005608: 4621 mov r1, r4 800560a: 4628 mov r0, r5 800560c: f000 ff6a bl 80064e4 <_fflush_r> 8005610: bb28 cbnz r0, 800565e <__swbuf_r+0x8e> 8005612: 68a3 ldr r3, [r4, #8] 8005614: 3001 adds r0, #1 8005616: 3b01 subs r3, #1 8005618: 60a3 str r3, [r4, #8] 800561a: 6823 ldr r3, [r4, #0] 800561c: 1c5a adds r2, r3, #1 800561e: 6022 str r2, [r4, #0] 8005620: 701e strb r6, [r3, #0] 8005622: 6963 ldr r3, [r4, #20] 8005624: 4283 cmp r3, r0 8005626: d004 beq.n 8005632 <__swbuf_r+0x62> 8005628: 89a3 ldrh r3, [r4, #12] 800562a: 07db lsls r3, r3, #31 800562c: d519 bpl.n 8005662 <__swbuf_r+0x92> 800562e: 2e0a cmp r6, #10 8005630: d117 bne.n 8005662 <__swbuf_r+0x92> 8005632: 4621 mov r1, r4 8005634: 4628 mov r0, r5 8005636: f000 ff55 bl 80064e4 <_fflush_r> 800563a: b190 cbz r0, 8005662 <__swbuf_r+0x92> 800563c: e00f b.n 800565e <__swbuf_r+0x8e> 800563e: 4b0b ldr r3, [pc, #44] ; (800566c <__swbuf_r+0x9c>) 8005640: 429c cmp r4, r3 8005642: d101 bne.n 8005648 <__swbuf_r+0x78> 8005644: 68ac ldr r4, [r5, #8] 8005646: e7d0 b.n 80055ea <__swbuf_r+0x1a> 8005648: 4b09 ldr r3, [pc, #36] ; (8005670 <__swbuf_r+0xa0>) 800564a: 429c cmp r4, r3 800564c: bf08 it eq 800564e: 68ec ldreq r4, [r5, #12] 8005650: e7cb b.n 80055ea <__swbuf_r+0x1a> 8005652: 4621 mov r1, r4 8005654: 4628 mov r0, r5 8005656: f000 f80d bl 8005674 <__swsetup_r> 800565a: 2800 cmp r0, #0 800565c: d0cc beq.n 80055f8 <__swbuf_r+0x28> 800565e: f04f 37ff mov.w r7, #4294967295 8005662: 4638 mov r0, r7 8005664: bdf8 pop {r3, r4, r5, r6, r7, pc} 8005666: bf00 nop 8005668: 080074ac .word 0x080074ac 800566c: 080074cc .word 0x080074cc 8005670: 0800748c .word 0x0800748c 08005674 <__swsetup_r>: 8005674: 4b32 ldr r3, [pc, #200] ; (8005740 <__swsetup_r+0xcc>) 8005676: b570 push {r4, r5, r6, lr} 8005678: 681d ldr r5, [r3, #0] 800567a: 4606 mov r6, r0 800567c: 460c mov r4, r1 800567e: b125 cbz r5, 800568a <__swsetup_r+0x16> 8005680: 69ab ldr r3, [r5, #24] 8005682: b913 cbnz r3, 800568a <__swsetup_r+0x16> 8005684: 4628 mov r0, r5 8005686: f000 ff97 bl 80065b8 <__sinit> 800568a: 4b2e ldr r3, [pc, #184] ; (8005744 <__swsetup_r+0xd0>) 800568c: 429c cmp r4, r3 800568e: d10f bne.n 80056b0 <__swsetup_r+0x3c> 8005690: 686c ldr r4, [r5, #4] 8005692: f9b4 300c ldrsh.w r3, [r4, #12] 8005696: b29a uxth r2, r3 8005698: 0715 lsls r5, r2, #28 800569a: d42c bmi.n 80056f6 <__swsetup_r+0x82> 800569c: 06d0 lsls r0, r2, #27 800569e: d411 bmi.n 80056c4 <__swsetup_r+0x50> 80056a0: 2209 movs r2, #9 80056a2: 6032 str r2, [r6, #0] 80056a4: f043 0340 orr.w r3, r3, #64 ; 0x40 80056a8: 81a3 strh r3, [r4, #12] 80056aa: f04f 30ff mov.w r0, #4294967295 80056ae: e03e b.n 800572e <__swsetup_r+0xba> 80056b0: 4b25 ldr r3, [pc, #148] ; (8005748 <__swsetup_r+0xd4>) 80056b2: 429c cmp r4, r3 80056b4: d101 bne.n 80056ba <__swsetup_r+0x46> 80056b6: 68ac ldr r4, [r5, #8] 80056b8: e7eb b.n 8005692 <__swsetup_r+0x1e> 80056ba: 4b24 ldr r3, [pc, #144] ; (800574c <__swsetup_r+0xd8>) 80056bc: 429c cmp r4, r3 80056be: bf08 it eq 80056c0: 68ec ldreq r4, [r5, #12] 80056c2: e7e6 b.n 8005692 <__swsetup_r+0x1e> 80056c4: 0751 lsls r1, r2, #29 80056c6: d512 bpl.n 80056ee <__swsetup_r+0x7a> 80056c8: 6b61 ldr r1, [r4, #52] ; 0x34 80056ca: b141 cbz r1, 80056de <__swsetup_r+0x6a> 80056cc: f104 0344 add.w r3, r4, #68 ; 0x44 80056d0: 4299 cmp r1, r3 80056d2: d002 beq.n 80056da <__swsetup_r+0x66> 80056d4: 4630 mov r0, r6 80056d6: f001 fb77 bl 8006dc8 <_free_r> 80056da: 2300 movs r3, #0 80056dc: 6363 str r3, [r4, #52] ; 0x34 80056de: 89a3 ldrh r3, [r4, #12] 80056e0: f023 0324 bic.w r3, r3, #36 ; 0x24 80056e4: 81a3 strh r3, [r4, #12] 80056e6: 2300 movs r3, #0 80056e8: 6063 str r3, [r4, #4] 80056ea: 6923 ldr r3, [r4, #16] 80056ec: 6023 str r3, [r4, #0] 80056ee: 89a3 ldrh r3, [r4, #12] 80056f0: f043 0308 orr.w r3, r3, #8 80056f4: 81a3 strh r3, [r4, #12] 80056f6: 6923 ldr r3, [r4, #16] 80056f8: b94b cbnz r3, 800570e <__swsetup_r+0x9a> 80056fa: 89a3 ldrh r3, [r4, #12] 80056fc: f403 7320 and.w r3, r3, #640 ; 0x280 8005700: f5b3 7f00 cmp.w r3, #512 ; 0x200 8005704: d003 beq.n 800570e <__swsetup_r+0x9a> 8005706: 4621 mov r1, r4 8005708: 4630 mov r0, r6 800570a: f001 f811 bl 8006730 <__smakebuf_r> 800570e: 89a2 ldrh r2, [r4, #12] 8005710: f012 0301 ands.w r3, r2, #1 8005714: d00c beq.n 8005730 <__swsetup_r+0xbc> 8005716: 2300 movs r3, #0 8005718: 60a3 str r3, [r4, #8] 800571a: 6963 ldr r3, [r4, #20] 800571c: 425b negs r3, r3 800571e: 61a3 str r3, [r4, #24] 8005720: 6923 ldr r3, [r4, #16] 8005722: b953 cbnz r3, 800573a <__swsetup_r+0xc6> 8005724: f9b4 300c ldrsh.w r3, [r4, #12] 8005728: f013 0080 ands.w r0, r3, #128 ; 0x80 800572c: d1ba bne.n 80056a4 <__swsetup_r+0x30> 800572e: bd70 pop {r4, r5, r6, pc} 8005730: 0792 lsls r2, r2, #30 8005732: bf58 it pl 8005734: 6963 ldrpl r3, [r4, #20] 8005736: 60a3 str r3, [r4, #8] 8005738: e7f2 b.n 8005720 <__swsetup_r+0xac> 800573a: 2000 movs r0, #0 800573c: e7f7 b.n 800572e <__swsetup_r+0xba> 800573e: bf00 nop 8005740: 2000000c .word 0x2000000c 8005744: 080074ac .word 0x080074ac 8005748: 080074cc .word 0x080074cc 800574c: 0800748c .word 0x0800748c 08005750 : 8005750: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} 8005754: 6903 ldr r3, [r0, #16] 8005756: 690c ldr r4, [r1, #16] 8005758: 4680 mov r8, r0 800575a: 42a3 cmp r3, r4 800575c: f2c0 8084 blt.w 8005868 8005760: 3c01 subs r4, #1 8005762: f101 0714 add.w r7, r1, #20 8005766: f100 0614 add.w r6, r0, #20 800576a: f857 5024 ldr.w r5, [r7, r4, lsl #2] 800576e: f856 0024 ldr.w r0, [r6, r4, lsl #2] 8005772: 3501 adds r5, #1 8005774: fbb0 f5f5 udiv r5, r0, r5 8005778: ea4f 0c84 mov.w ip, r4, lsl #2 800577c: eb06 030c add.w r3, r6, ip 8005780: eb07 090c add.w r9, r7, ip 8005784: 9301 str r3, [sp, #4] 8005786: b39d cbz r5, 80057f0 8005788: f04f 0a00 mov.w sl, #0 800578c: 4638 mov r0, r7 800578e: 46b6 mov lr, r6 8005790: 46d3 mov fp, sl 8005792: f850 2b04 ldr.w r2, [r0], #4 8005796: b293 uxth r3, r2 8005798: fb05 a303 mla r3, r5, r3, sl 800579c: 0c12 lsrs r2, r2, #16 800579e: ea4f 4a13 mov.w sl, r3, lsr #16 80057a2: fb05 a202 mla r2, r5, r2, sl 80057a6: b29b uxth r3, r3 80057a8: ebab 0303 sub.w r3, fp, r3 80057ac: f8de b000 ldr.w fp, [lr] 80057b0: ea4f 4a12 mov.w sl, r2, lsr #16 80057b4: fa1f fb8b uxth.w fp, fp 80057b8: 445b add r3, fp 80057ba: fa1f fb82 uxth.w fp, r2 80057be: f8de 2000 ldr.w r2, [lr] 80057c2: 4581 cmp r9, r0 80057c4: ebcb 4212 rsb r2, fp, r2, lsr #16 80057c8: eb02 4223 add.w r2, r2, r3, asr #16 80057cc: b29b uxth r3, r3 80057ce: ea43 4302 orr.w r3, r3, r2, lsl #16 80057d2: ea4f 4b22 mov.w fp, r2, asr #16 80057d6: f84e 3b04 str.w r3, [lr], #4 80057da: d2da bcs.n 8005792 80057dc: f856 300c ldr.w r3, [r6, ip] 80057e0: b933 cbnz r3, 80057f0 80057e2: 9b01 ldr r3, [sp, #4] 80057e4: 3b04 subs r3, #4 80057e6: 429e cmp r6, r3 80057e8: 461a mov r2, r3 80057ea: d331 bcc.n 8005850 80057ec: f8c8 4010 str.w r4, [r8, #16] 80057f0: 4640 mov r0, r8 80057f2: f001 fa13 bl 8006c1c <__mcmp> 80057f6: 2800 cmp r0, #0 80057f8: db26 blt.n 8005848 80057fa: 4630 mov r0, r6 80057fc: f04f 0c00 mov.w ip, #0 8005800: 3501 adds r5, #1 8005802: f857 1b04 ldr.w r1, [r7], #4 8005806: f8d0 e000 ldr.w lr, [r0] 800580a: b28b uxth r3, r1 800580c: ebac 0303 sub.w r3, ip, r3 8005810: fa1f f28e uxth.w r2, lr 8005814: 4413 add r3, r2 8005816: 0c0a lsrs r2, r1, #16 8005818: ebc2 421e rsb r2, r2, lr, lsr #16 800581c: eb02 4223 add.w r2, r2, r3, asr #16 8005820: b29b uxth r3, r3 8005822: ea43 4302 orr.w r3, r3, r2, lsl #16 8005826: 45b9 cmp r9, r7 8005828: ea4f 4c22 mov.w ip, r2, asr #16 800582c: f840 3b04 str.w r3, [r0], #4 8005830: d2e7 bcs.n 8005802 8005832: f856 2024 ldr.w r2, [r6, r4, lsl #2] 8005836: eb06 0384 add.w r3, r6, r4, lsl #2 800583a: b92a cbnz r2, 8005848 800583c: 3b04 subs r3, #4 800583e: 429e cmp r6, r3 8005840: 461a mov r2, r3 8005842: d30b bcc.n 800585c 8005844: f8c8 4010 str.w r4, [r8, #16] 8005848: 4628 mov r0, r5 800584a: b003 add sp, #12 800584c: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8005850: 6812 ldr r2, [r2, #0] 8005852: 3b04 subs r3, #4 8005854: 2a00 cmp r2, #0 8005856: d1c9 bne.n 80057ec 8005858: 3c01 subs r4, #1 800585a: e7c4 b.n 80057e6 800585c: 6812 ldr r2, [r2, #0] 800585e: 3b04 subs r3, #4 8005860: 2a00 cmp r2, #0 8005862: d1ef bne.n 8005844 8005864: 3c01 subs r4, #1 8005866: e7ea b.n 800583e 8005868: 2000 movs r0, #0 800586a: e7ee b.n 800584a 800586c: 0000 movs r0, r0 ... 08005870 <_dtoa_r>: 8005870: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8005874: 4616 mov r6, r2 8005876: 461f mov r7, r3 8005878: 6a45 ldr r5, [r0, #36] ; 0x24 800587a: b095 sub sp, #84 ; 0x54 800587c: 4604 mov r4, r0 800587e: f8dd 8084 ldr.w r8, [sp, #132] ; 0x84 8005882: e9cd 6702 strd r6, r7, [sp, #8] 8005886: b93d cbnz r5, 8005898 <_dtoa_r+0x28> 8005888: 2010 movs r0, #16 800588a: f000 ff91 bl 80067b0 800588e: 6260 str r0, [r4, #36] ; 0x24 8005890: e9c0 5501 strd r5, r5, [r0, #4] 8005894: 6005 str r5, [r0, #0] 8005896: 60c5 str r5, [r0, #12] 8005898: 6a63 ldr r3, [r4, #36] ; 0x24 800589a: 6819 ldr r1, [r3, #0] 800589c: b151 cbz r1, 80058b4 <_dtoa_r+0x44> 800589e: 685a ldr r2, [r3, #4] 80058a0: 2301 movs r3, #1 80058a2: 4093 lsls r3, r2 80058a4: 604a str r2, [r1, #4] 80058a6: 608b str r3, [r1, #8] 80058a8: 4620 mov r0, r4 80058aa: f000 ffd6 bl 800685a <_Bfree> 80058ae: 2200 movs r2, #0 80058b0: 6a63 ldr r3, [r4, #36] ; 0x24 80058b2: 601a str r2, [r3, #0] 80058b4: 1e3b subs r3, r7, #0 80058b6: bfaf iteee ge 80058b8: 2300 movge r3, #0 80058ba: 2201 movlt r2, #1 80058bc: f023 4300 biclt.w r3, r3, #2147483648 ; 0x80000000 80058c0: 9303 strlt r3, [sp, #12] 80058c2: bfac ite ge 80058c4: f8c8 3000 strge.w r3, [r8] 80058c8: f8c8 2000 strlt.w r2, [r8] 80058cc: 4bae ldr r3, [pc, #696] ; (8005b88 <_dtoa_r+0x318>) 80058ce: f8dd 800c ldr.w r8, [sp, #12] 80058d2: ea33 0308 bics.w r3, r3, r8 80058d6: d11b bne.n 8005910 <_dtoa_r+0xa0> 80058d8: f242 730f movw r3, #9999 ; 0x270f 80058dc: 9a20 ldr r2, [sp, #128] ; 0x80 80058de: 6013 str r3, [r2, #0] 80058e0: 9b02 ldr r3, [sp, #8] 80058e2: b923 cbnz r3, 80058ee <_dtoa_r+0x7e> 80058e4: f3c8 0013 ubfx r0, r8, #0, #20 80058e8: 2800 cmp r0, #0 80058ea: f000 8545 beq.w 8006378 <_dtoa_r+0xb08> 80058ee: 9b22 ldr r3, [sp, #136] ; 0x88 80058f0: b953 cbnz r3, 8005908 <_dtoa_r+0x98> 80058f2: 4ba6 ldr r3, [pc, #664] ; (8005b8c <_dtoa_r+0x31c>) 80058f4: e021 b.n 800593a <_dtoa_r+0xca> 80058f6: 4ba6 ldr r3, [pc, #664] ; (8005b90 <_dtoa_r+0x320>) 80058f8: 9306 str r3, [sp, #24] 80058fa: 3308 adds r3, #8 80058fc: 9a22 ldr r2, [sp, #136] ; 0x88 80058fe: 6013 str r3, [r2, #0] 8005900: 9806 ldr r0, [sp, #24] 8005902: b015 add sp, #84 ; 0x54 8005904: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8005908: 4ba0 ldr r3, [pc, #640] ; (8005b8c <_dtoa_r+0x31c>) 800590a: 9306 str r3, [sp, #24] 800590c: 3303 adds r3, #3 800590e: e7f5 b.n 80058fc <_dtoa_r+0x8c> 8005910: e9dd 6702 ldrd r6, r7, [sp, #8] 8005914: 2200 movs r2, #0 8005916: 2300 movs r3, #0 8005918: 4630 mov r0, r6 800591a: 4639 mov r1, r7 800591c: f7fb f8a4 bl 8000a68 <__aeabi_dcmpeq> 8005920: 4682 mov sl, r0 8005922: b160 cbz r0, 800593e <_dtoa_r+0xce> 8005924: 2301 movs r3, #1 8005926: 9a20 ldr r2, [sp, #128] ; 0x80 8005928: 6013 str r3, [r2, #0] 800592a: 9b22 ldr r3, [sp, #136] ; 0x88 800592c: 2b00 cmp r3, #0 800592e: f000 8520 beq.w 8006372 <_dtoa_r+0xb02> 8005932: 4b98 ldr r3, [pc, #608] ; (8005b94 <_dtoa_r+0x324>) 8005934: 9a22 ldr r2, [sp, #136] ; 0x88 8005936: 6013 str r3, [r2, #0] 8005938: 3b01 subs r3, #1 800593a: 9306 str r3, [sp, #24] 800593c: e7e0 b.n 8005900 <_dtoa_r+0x90> 800593e: ab12 add r3, sp, #72 ; 0x48 8005940: 9301 str r3, [sp, #4] 8005942: ab13 add r3, sp, #76 ; 0x4c 8005944: 9300 str r3, [sp, #0] 8005946: 4632 mov r2, r6 8005948: 463b mov r3, r7 800594a: 4620 mov r0, r4 800594c: f001 f9de bl 8006d0c <__d2b> 8005950: f3c8 550a ubfx r5, r8, #20, #11 8005954: 4683 mov fp, r0 8005956: 2d00 cmp r5, #0 8005958: d07d beq.n 8005a56 <_dtoa_r+0x1e6> 800595a: 46b0 mov r8, r6 800595c: f3c7 0313 ubfx r3, r7, #0, #20 8005960: f043 597f orr.w r9, r3, #1069547520 ; 0x3fc00000 8005964: f449 1940 orr.w r9, r9, #3145728 ; 0x300000 8005968: f2a5 35ff subw r5, r5, #1023 ; 0x3ff 800596c: f8cd a040 str.w sl, [sp, #64] ; 0x40 8005970: 2200 movs r2, #0 8005972: 4b89 ldr r3, [pc, #548] ; (8005b98 <_dtoa_r+0x328>) 8005974: 4640 mov r0, r8 8005976: 4649 mov r1, r9 8005978: f7fa fc56 bl 8000228 <__aeabi_dsub> 800597c: a37c add r3, pc, #496 ; (adr r3, 8005b70 <_dtoa_r+0x300>) 800597e: e9d3 2300 ldrd r2, r3, [r3] 8005982: f7fa fe09 bl 8000598 <__aeabi_dmul> 8005986: a37c add r3, pc, #496 ; (adr r3, 8005b78 <_dtoa_r+0x308>) 8005988: e9d3 2300 ldrd r2, r3, [r3] 800598c: f7fa fc4e bl 800022c <__adddf3> 8005990: 4606 mov r6, r0 8005992: 4628 mov r0, r5 8005994: 460f mov r7, r1 8005996: f7fa fd95 bl 80004c4 <__aeabi_i2d> 800599a: a379 add r3, pc, #484 ; (adr r3, 8005b80 <_dtoa_r+0x310>) 800599c: e9d3 2300 ldrd r2, r3, [r3] 80059a0: f7fa fdfa bl 8000598 <__aeabi_dmul> 80059a4: 4602 mov r2, r0 80059a6: 460b mov r3, r1 80059a8: 4630 mov r0, r6 80059aa: 4639 mov r1, r7 80059ac: f7fa fc3e bl 800022c <__adddf3> 80059b0: 4606 mov r6, r0 80059b2: 460f mov r7, r1 80059b4: f7fb f8a0 bl 8000af8 <__aeabi_d2iz> 80059b8: 2200 movs r2, #0 80059ba: 4682 mov sl, r0 80059bc: 2300 movs r3, #0 80059be: 4630 mov r0, r6 80059c0: 4639 mov r1, r7 80059c2: f7fb f85b bl 8000a7c <__aeabi_dcmplt> 80059c6: b148 cbz r0, 80059dc <_dtoa_r+0x16c> 80059c8: 4650 mov r0, sl 80059ca: f7fa fd7b bl 80004c4 <__aeabi_i2d> 80059ce: 4632 mov r2, r6 80059d0: 463b mov r3, r7 80059d2: f7fb f849 bl 8000a68 <__aeabi_dcmpeq> 80059d6: b908 cbnz r0, 80059dc <_dtoa_r+0x16c> 80059d8: f10a 3aff add.w sl, sl, #4294967295 80059dc: f1ba 0f16 cmp.w sl, #22 80059e0: d85a bhi.n 8005a98 <_dtoa_r+0x228> 80059e2: e9dd 2302 ldrd r2, r3, [sp, #8] 80059e6: 496d ldr r1, [pc, #436] ; (8005b9c <_dtoa_r+0x32c>) 80059e8: eb01 01ca add.w r1, r1, sl, lsl #3 80059ec: e9d1 0100 ldrd r0, r1, [r1] 80059f0: f7fb f862 bl 8000ab8 <__aeabi_dcmpgt> 80059f4: 2800 cmp r0, #0 80059f6: d051 beq.n 8005a9c <_dtoa_r+0x22c> 80059f8: 2300 movs r3, #0 80059fa: f10a 3aff add.w sl, sl, #4294967295 80059fe: 930d str r3, [sp, #52] ; 0x34 8005a00: 9b12 ldr r3, [sp, #72] ; 0x48 8005a02: 1b5d subs r5, r3, r5 8005a04: 1e6b subs r3, r5, #1 8005a06: 9307 str r3, [sp, #28] 8005a08: bf43 ittte mi 8005a0a: 2300 movmi r3, #0 8005a0c: f1c5 0901 rsbmi r9, r5, #1 8005a10: 9307 strmi r3, [sp, #28] 8005a12: f04f 0900 movpl.w r9, #0 8005a16: f1ba 0f00 cmp.w sl, #0 8005a1a: db41 blt.n 8005aa0 <_dtoa_r+0x230> 8005a1c: 9b07 ldr r3, [sp, #28] 8005a1e: f8cd a030 str.w sl, [sp, #48] ; 0x30 8005a22: 4453 add r3, sl 8005a24: 9307 str r3, [sp, #28] 8005a26: 2300 movs r3, #0 8005a28: 9308 str r3, [sp, #32] 8005a2a: 9b1e ldr r3, [sp, #120] ; 0x78 8005a2c: 2b09 cmp r3, #9 8005a2e: f200 808f bhi.w 8005b50 <_dtoa_r+0x2e0> 8005a32: 2b05 cmp r3, #5 8005a34: bfc4 itt gt 8005a36: 3b04 subgt r3, #4 8005a38: 931e strgt r3, [sp, #120] ; 0x78 8005a3a: 9b1e ldr r3, [sp, #120] ; 0x78 8005a3c: bfc8 it gt 8005a3e: 2500 movgt r5, #0 8005a40: f1a3 0302 sub.w r3, r3, #2 8005a44: bfd8 it le 8005a46: 2501 movle r5, #1 8005a48: 2b03 cmp r3, #3 8005a4a: f200 808d bhi.w 8005b68 <_dtoa_r+0x2f8> 8005a4e: e8df f003 tbb [pc, r3] 8005a52: 7d7b .short 0x7d7b 8005a54: 6f2f .short 0x6f2f 8005a56: e9dd 5312 ldrd r5, r3, [sp, #72] ; 0x48 8005a5a: 441d add r5, r3 8005a5c: f205 4032 addw r0, r5, #1074 ; 0x432 8005a60: 2820 cmp r0, #32 8005a62: dd13 ble.n 8005a8c <_dtoa_r+0x21c> 8005a64: f1c0 0040 rsb r0, r0, #64 ; 0x40 8005a68: 9b02 ldr r3, [sp, #8] 8005a6a: fa08 f800 lsl.w r8, r8, r0 8005a6e: f205 4012 addw r0, r5, #1042 ; 0x412 8005a72: fa23 f000 lsr.w r0, r3, r0 8005a76: ea48 0000 orr.w r0, r8, r0 8005a7a: f7fa fd13 bl 80004a4 <__aeabi_ui2d> 8005a7e: 2301 movs r3, #1 8005a80: 4680 mov r8, r0 8005a82: f1a1 79f8 sub.w r9, r1, #32505856 ; 0x1f00000 8005a86: 3d01 subs r5, #1 8005a88: 9310 str r3, [sp, #64] ; 0x40 8005a8a: e771 b.n 8005970 <_dtoa_r+0x100> 8005a8c: 9b02 ldr r3, [sp, #8] 8005a8e: f1c0 0020 rsb r0, r0, #32 8005a92: fa03 f000 lsl.w r0, r3, r0 8005a96: e7f0 b.n 8005a7a <_dtoa_r+0x20a> 8005a98: 2301 movs r3, #1 8005a9a: e7b0 b.n 80059fe <_dtoa_r+0x18e> 8005a9c: 900d str r0, [sp, #52] ; 0x34 8005a9e: e7af b.n 8005a00 <_dtoa_r+0x190> 8005aa0: f1ca 0300 rsb r3, sl, #0 8005aa4: 9308 str r3, [sp, #32] 8005aa6: 2300 movs r3, #0 8005aa8: eba9 090a sub.w r9, r9, sl 8005aac: 930c str r3, [sp, #48] ; 0x30 8005aae: e7bc b.n 8005a2a <_dtoa_r+0x1ba> 8005ab0: 2301 movs r3, #1 8005ab2: 9309 str r3, [sp, #36] ; 0x24 8005ab4: 9b1f ldr r3, [sp, #124] ; 0x7c 8005ab6: 2b00 cmp r3, #0 8005ab8: dd74 ble.n 8005ba4 <_dtoa_r+0x334> 8005aba: 4698 mov r8, r3 8005abc: 9304 str r3, [sp, #16] 8005abe: 2200 movs r2, #0 8005ac0: 6a66 ldr r6, [r4, #36] ; 0x24 8005ac2: 6072 str r2, [r6, #4] 8005ac4: 2204 movs r2, #4 8005ac6: f102 0014 add.w r0, r2, #20 8005aca: 4298 cmp r0, r3 8005acc: 6871 ldr r1, [r6, #4] 8005ace: d96e bls.n 8005bae <_dtoa_r+0x33e> 8005ad0: 4620 mov r0, r4 8005ad2: f000 fe8e bl 80067f2 <_Balloc> 8005ad6: 6a63 ldr r3, [r4, #36] ; 0x24 8005ad8: 6030 str r0, [r6, #0] 8005ada: 681b ldr r3, [r3, #0] 8005adc: f1b8 0f0e cmp.w r8, #14 8005ae0: 9306 str r3, [sp, #24] 8005ae2: f200 80ed bhi.w 8005cc0 <_dtoa_r+0x450> 8005ae6: 2d00 cmp r5, #0 8005ae8: f000 80ea beq.w 8005cc0 <_dtoa_r+0x450> 8005aec: e9dd 2302 ldrd r2, r3, [sp, #8] 8005af0: f1ba 0f00 cmp.w sl, #0 8005af4: e9cd 230e strd r2, r3, [sp, #56] ; 0x38 8005af8: dd77 ble.n 8005bea <_dtoa_r+0x37a> 8005afa: 4a28 ldr r2, [pc, #160] ; (8005b9c <_dtoa_r+0x32c>) 8005afc: f00a 030f and.w r3, sl, #15 8005b00: ea4f 162a mov.w r6, sl, asr #4 8005b04: eb02 03c3 add.w r3, r2, r3, lsl #3 8005b08: 06f0 lsls r0, r6, #27 8005b0a: e9d3 2300 ldrd r2, r3, [r3] 8005b0e: e9cd 230a strd r2, r3, [sp, #40] ; 0x28 8005b12: d568 bpl.n 8005be6 <_dtoa_r+0x376> 8005b14: e9dd 010e ldrd r0, r1, [sp, #56] ; 0x38 8005b18: 4b21 ldr r3, [pc, #132] ; (8005ba0 <_dtoa_r+0x330>) 8005b1a: 2503 movs r5, #3 8005b1c: e9d3 2308 ldrd r2, r3, [r3, #32] 8005b20: f7fa fe64 bl 80007ec <__aeabi_ddiv> 8005b24: e9cd 0102 strd r0, r1, [sp, #8] 8005b28: f006 060f and.w r6, r6, #15 8005b2c: 4f1c ldr r7, [pc, #112] ; (8005ba0 <_dtoa_r+0x330>) 8005b2e: e04f b.n 8005bd0 <_dtoa_r+0x360> 8005b30: 2301 movs r3, #1 8005b32: 9309 str r3, [sp, #36] ; 0x24 8005b34: 9b1f ldr r3, [sp, #124] ; 0x7c 8005b36: 4453 add r3, sl 8005b38: f103 0801 add.w r8, r3, #1 8005b3c: 9304 str r3, [sp, #16] 8005b3e: 4643 mov r3, r8 8005b40: 2b01 cmp r3, #1 8005b42: bfb8 it lt 8005b44: 2301 movlt r3, #1 8005b46: e7ba b.n 8005abe <_dtoa_r+0x24e> 8005b48: 2300 movs r3, #0 8005b4a: e7b2 b.n 8005ab2 <_dtoa_r+0x242> 8005b4c: 2300 movs r3, #0 8005b4e: e7f0 b.n 8005b32 <_dtoa_r+0x2c2> 8005b50: 2501 movs r5, #1 8005b52: 2300 movs r3, #0 8005b54: 9509 str r5, [sp, #36] ; 0x24 8005b56: 931e str r3, [sp, #120] ; 0x78 8005b58: f04f 33ff mov.w r3, #4294967295 8005b5c: 2200 movs r2, #0 8005b5e: 9304 str r3, [sp, #16] 8005b60: 4698 mov r8, r3 8005b62: 2312 movs r3, #18 8005b64: 921f str r2, [sp, #124] ; 0x7c 8005b66: e7aa b.n 8005abe <_dtoa_r+0x24e> 8005b68: 2301 movs r3, #1 8005b6a: 9309 str r3, [sp, #36] ; 0x24 8005b6c: e7f4 b.n 8005b58 <_dtoa_r+0x2e8> 8005b6e: bf00 nop 8005b70: 636f4361 .word 0x636f4361 8005b74: 3fd287a7 .word 0x3fd287a7 8005b78: 8b60c8b3 .word 0x8b60c8b3 8005b7c: 3fc68a28 .word 0x3fc68a28 8005b80: 509f79fb .word 0x509f79fb 8005b84: 3fd34413 .word 0x3fd34413 8005b88: 7ff00000 .word 0x7ff00000 8005b8c: 08007485 .word 0x08007485 8005b90: 0800747c .word 0x0800747c 8005b94: 08007459 .word 0x08007459 8005b98: 3ff80000 .word 0x3ff80000 8005b9c: 08007518 .word 0x08007518 8005ba0: 080074f0 .word 0x080074f0 8005ba4: 2301 movs r3, #1 8005ba6: 9304 str r3, [sp, #16] 8005ba8: 4698 mov r8, r3 8005baa: 461a mov r2, r3 8005bac: e7da b.n 8005b64 <_dtoa_r+0x2f4> 8005bae: 3101 adds r1, #1 8005bb0: 6071 str r1, [r6, #4] 8005bb2: 0052 lsls r2, r2, #1 8005bb4: e787 b.n 8005ac6 <_dtoa_r+0x256> 8005bb6: 07f1 lsls r1, r6, #31 8005bb8: d508 bpl.n 8005bcc <_dtoa_r+0x35c> 8005bba: e9dd 010a ldrd r0, r1, [sp, #40] ; 0x28 8005bbe: e9d7 2300 ldrd r2, r3, [r7] 8005bc2: f7fa fce9 bl 8000598 <__aeabi_dmul> 8005bc6: e9cd 010a strd r0, r1, [sp, #40] ; 0x28 8005bca: 3501 adds r5, #1 8005bcc: 1076 asrs r6, r6, #1 8005bce: 3708 adds r7, #8 8005bd0: 2e00 cmp r6, #0 8005bd2: d1f0 bne.n 8005bb6 <_dtoa_r+0x346> 8005bd4: e9dd 230a ldrd r2, r3, [sp, #40] ; 0x28 8005bd8: e9dd 0102 ldrd r0, r1, [sp, #8] 8005bdc: f7fa fe06 bl 80007ec <__aeabi_ddiv> 8005be0: e9cd 0102 strd r0, r1, [sp, #8] 8005be4: e01b b.n 8005c1e <_dtoa_r+0x3ae> 8005be6: 2502 movs r5, #2 8005be8: e7a0 b.n 8005b2c <_dtoa_r+0x2bc> 8005bea: f000 80a4 beq.w 8005d36 <_dtoa_r+0x4c6> 8005bee: e9dd 010e ldrd r0, r1, [sp, #56] ; 0x38 8005bf2: f1ca 0600 rsb r6, sl, #0 8005bf6: 4ba0 ldr r3, [pc, #640] ; (8005e78 <_dtoa_r+0x608>) 8005bf8: f006 020f and.w r2, r6, #15 8005bfc: eb03 03c2 add.w r3, r3, r2, lsl #3 8005c00: e9d3 2300 ldrd r2, r3, [r3] 8005c04: f7fa fcc8 bl 8000598 <__aeabi_dmul> 8005c08: 2502 movs r5, #2 8005c0a: 2300 movs r3, #0 8005c0c: e9cd 0102 strd r0, r1, [sp, #8] 8005c10: 4f9a ldr r7, [pc, #616] ; (8005e7c <_dtoa_r+0x60c>) 8005c12: 1136 asrs r6, r6, #4 8005c14: 2e00 cmp r6, #0 8005c16: f040 8083 bne.w 8005d20 <_dtoa_r+0x4b0> 8005c1a: 2b00 cmp r3, #0 8005c1c: d1e0 bne.n 8005be0 <_dtoa_r+0x370> 8005c1e: 9b0d ldr r3, [sp, #52] ; 0x34 8005c20: 2b00 cmp r3, #0 8005c22: f000 808a beq.w 8005d3a <_dtoa_r+0x4ca> 8005c26: e9dd 2302 ldrd r2, r3, [sp, #8] 8005c2a: e9cd 230a strd r2, r3, [sp, #40] ; 0x28 8005c2e: e9dd 010a ldrd r0, r1, [sp, #40] ; 0x28 8005c32: 2200 movs r2, #0 8005c34: 4b92 ldr r3, [pc, #584] ; (8005e80 <_dtoa_r+0x610>) 8005c36: f7fa ff21 bl 8000a7c <__aeabi_dcmplt> 8005c3a: 2800 cmp r0, #0 8005c3c: d07d beq.n 8005d3a <_dtoa_r+0x4ca> 8005c3e: f1b8 0f00 cmp.w r8, #0 8005c42: d07a beq.n 8005d3a <_dtoa_r+0x4ca> 8005c44: 9b04 ldr r3, [sp, #16] 8005c46: 2b00 cmp r3, #0 8005c48: dd36 ble.n 8005cb8 <_dtoa_r+0x448> 8005c4a: e9dd 010a ldrd r0, r1, [sp, #40] ; 0x28 8005c4e: 2200 movs r2, #0 8005c50: 4b8c ldr r3, [pc, #560] ; (8005e84 <_dtoa_r+0x614>) 8005c52: f7fa fca1 bl 8000598 <__aeabi_dmul> 8005c56: e9cd 0102 strd r0, r1, [sp, #8] 8005c5a: 9e04 ldr r6, [sp, #16] 8005c5c: f10a 37ff add.w r7, sl, #4294967295 8005c60: 3501 adds r5, #1 8005c62: 4628 mov r0, r5 8005c64: f7fa fc2e bl 80004c4 <__aeabi_i2d> 8005c68: e9dd 2302 ldrd r2, r3, [sp, #8] 8005c6c: f7fa fc94 bl 8000598 <__aeabi_dmul> 8005c70: 2200 movs r2, #0 8005c72: 4b85 ldr r3, [pc, #532] ; (8005e88 <_dtoa_r+0x618>) 8005c74: f7fa fada bl 800022c <__adddf3> 8005c78: f1a1 7550 sub.w r5, r1, #54525952 ; 0x3400000 8005c7c: e9cd 010a strd r0, r1, [sp, #40] ; 0x28 8005c80: 950b str r5, [sp, #44] ; 0x2c 8005c82: 2e00 cmp r6, #0 8005c84: d15c bne.n 8005d40 <_dtoa_r+0x4d0> 8005c86: e9dd 0102 ldrd r0, r1, [sp, #8] 8005c8a: 2200 movs r2, #0 8005c8c: 4b7f ldr r3, [pc, #508] ; (8005e8c <_dtoa_r+0x61c>) 8005c8e: f7fa facb bl 8000228 <__aeabi_dsub> 8005c92: 9a0a ldr r2, [sp, #40] ; 0x28 8005c94: 462b mov r3, r5 8005c96: e9cd 0102 strd r0, r1, [sp, #8] 8005c9a: f7fa ff0d bl 8000ab8 <__aeabi_dcmpgt> 8005c9e: 2800 cmp r0, #0 8005ca0: f040 8281 bne.w 80061a6 <_dtoa_r+0x936> 8005ca4: e9dd 0102 ldrd r0, r1, [sp, #8] 8005ca8: 9a0a ldr r2, [sp, #40] ; 0x28 8005caa: f105 4300 add.w r3, r5, #2147483648 ; 0x80000000 8005cae: f7fa fee5 bl 8000a7c <__aeabi_dcmplt> 8005cb2: 2800 cmp r0, #0 8005cb4: f040 8275 bne.w 80061a2 <_dtoa_r+0x932> 8005cb8: e9dd 230e ldrd r2, r3, [sp, #56] ; 0x38 8005cbc: e9cd 2302 strd r2, r3, [sp, #8] 8005cc0: 9b13 ldr r3, [sp, #76] ; 0x4c 8005cc2: 2b00 cmp r3, #0 8005cc4: f2c0 814b blt.w 8005f5e <_dtoa_r+0x6ee> 8005cc8: f1ba 0f0e cmp.w sl, #14 8005ccc: f300 8147 bgt.w 8005f5e <_dtoa_r+0x6ee> 8005cd0: 4b69 ldr r3, [pc, #420] ; (8005e78 <_dtoa_r+0x608>) 8005cd2: eb03 03ca add.w r3, r3, sl, lsl #3 8005cd6: e9d3 2300 ldrd r2, r3, [r3] 8005cda: e9cd 2304 strd r2, r3, [sp, #16] 8005cde: 9b1f ldr r3, [sp, #124] ; 0x7c 8005ce0: 2b00 cmp r3, #0 8005ce2: f280 80d7 bge.w 8005e94 <_dtoa_r+0x624> 8005ce6: f1b8 0f00 cmp.w r8, #0 8005cea: f300 80d3 bgt.w 8005e94 <_dtoa_r+0x624> 8005cee: f040 8257 bne.w 80061a0 <_dtoa_r+0x930> 8005cf2: e9dd 0104 ldrd r0, r1, [sp, #16] 8005cf6: 2200 movs r2, #0 8005cf8: 4b64 ldr r3, [pc, #400] ; (8005e8c <_dtoa_r+0x61c>) 8005cfa: f7fa fc4d bl 8000598 <__aeabi_dmul> 8005cfe: e9dd 2302 ldrd r2, r3, [sp, #8] 8005d02: f7fa fecf bl 8000aa4 <__aeabi_dcmpge> 8005d06: 4646 mov r6, r8 8005d08: 4647 mov r7, r8 8005d0a: 2800 cmp r0, #0 8005d0c: f040 822d bne.w 800616a <_dtoa_r+0x8fa> 8005d10: 9b06 ldr r3, [sp, #24] 8005d12: 9a06 ldr r2, [sp, #24] 8005d14: 1c5d adds r5, r3, #1 8005d16: 2331 movs r3, #49 ; 0x31 8005d18: f10a 0a01 add.w sl, sl, #1 8005d1c: 7013 strb r3, [r2, #0] 8005d1e: e228 b.n 8006172 <_dtoa_r+0x902> 8005d20: 07f2 lsls r2, r6, #31 8005d22: d505 bpl.n 8005d30 <_dtoa_r+0x4c0> 8005d24: e9d7 2300 ldrd r2, r3, [r7] 8005d28: f7fa fc36 bl 8000598 <__aeabi_dmul> 8005d2c: 2301 movs r3, #1 8005d2e: 3501 adds r5, #1 8005d30: 1076 asrs r6, r6, #1 8005d32: 3708 adds r7, #8 8005d34: e76e b.n 8005c14 <_dtoa_r+0x3a4> 8005d36: 2502 movs r5, #2 8005d38: e771 b.n 8005c1e <_dtoa_r+0x3ae> 8005d3a: 4657 mov r7, sl 8005d3c: 4646 mov r6, r8 8005d3e: e790 b.n 8005c62 <_dtoa_r+0x3f2> 8005d40: 4b4d ldr r3, [pc, #308] ; (8005e78 <_dtoa_r+0x608>) 8005d42: eb03 03c6 add.w r3, r3, r6, lsl #3 8005d46: e953 0102 ldrd r0, r1, [r3, #-8] 8005d4a: 9b09 ldr r3, [sp, #36] ; 0x24 8005d4c: 2b00 cmp r3, #0 8005d4e: d048 beq.n 8005de2 <_dtoa_r+0x572> 8005d50: 4602 mov r2, r0 8005d52: 460b mov r3, r1 8005d54: 2000 movs r0, #0 8005d56: 494e ldr r1, [pc, #312] ; (8005e90 <_dtoa_r+0x620>) 8005d58: f7fa fd48 bl 80007ec <__aeabi_ddiv> 8005d5c: e9dd 230a ldrd r2, r3, [sp, #40] ; 0x28 8005d60: f7fa fa62 bl 8000228 <__aeabi_dsub> 8005d64: e9cd 010a strd r0, r1, [sp, #40] ; 0x28 8005d68: 9d06 ldr r5, [sp, #24] 8005d6a: e9dd 0102 ldrd r0, r1, [sp, #8] 8005d6e: f7fa fec3 bl 8000af8 <__aeabi_d2iz> 8005d72: 9011 str r0, [sp, #68] ; 0x44 8005d74: f7fa fba6 bl 80004c4 <__aeabi_i2d> 8005d78: 4602 mov r2, r0 8005d7a: 460b mov r3, r1 8005d7c: e9dd 0102 ldrd r0, r1, [sp, #8] 8005d80: f7fa fa52 bl 8000228 <__aeabi_dsub> 8005d84: 9b11 ldr r3, [sp, #68] ; 0x44 8005d86: e9cd 0102 strd r0, r1, [sp, #8] 8005d8a: 3330 adds r3, #48 ; 0x30 8005d8c: f805 3b01 strb.w r3, [r5], #1 8005d90: e9dd 230a ldrd r2, r3, [sp, #40] ; 0x28 8005d94: f7fa fe72 bl 8000a7c <__aeabi_dcmplt> 8005d98: 2800 cmp r0, #0 8005d9a: d163 bne.n 8005e64 <_dtoa_r+0x5f4> 8005d9c: e9dd 2302 ldrd r2, r3, [sp, #8] 8005da0: 2000 movs r0, #0 8005da2: 4937 ldr r1, [pc, #220] ; (8005e80 <_dtoa_r+0x610>) 8005da4: f7fa fa40 bl 8000228 <__aeabi_dsub> 8005da8: e9dd 230a ldrd r2, r3, [sp, #40] ; 0x28 8005dac: f7fa fe66 bl 8000a7c <__aeabi_dcmplt> 8005db0: 2800 cmp r0, #0 8005db2: f040 80b5 bne.w 8005f20 <_dtoa_r+0x6b0> 8005db6: 9b06 ldr r3, [sp, #24] 8005db8: 1aeb subs r3, r5, r3 8005dba: 429e cmp r6, r3 8005dbc: f77f af7c ble.w 8005cb8 <_dtoa_r+0x448> 8005dc0: e9dd 010a ldrd r0, r1, [sp, #40] ; 0x28 8005dc4: 2200 movs r2, #0 8005dc6: 4b2f ldr r3, [pc, #188] ; (8005e84 <_dtoa_r+0x614>) 8005dc8: f7fa fbe6 bl 8000598 <__aeabi_dmul> 8005dcc: 2200 movs r2, #0 8005dce: e9cd 010a strd r0, r1, [sp, #40] ; 0x28 8005dd2: e9dd 0102 ldrd r0, r1, [sp, #8] 8005dd6: 4b2b ldr r3, [pc, #172] ; (8005e84 <_dtoa_r+0x614>) 8005dd8: f7fa fbde bl 8000598 <__aeabi_dmul> 8005ddc: e9cd 0102 strd r0, r1, [sp, #8] 8005de0: e7c3 b.n 8005d6a <_dtoa_r+0x4fa> 8005de2: e9dd 230a ldrd r2, r3, [sp, #40] ; 0x28 8005de6: f7fa fbd7 bl 8000598 <__aeabi_dmul> 8005dea: 9b06 ldr r3, [sp, #24] 8005dec: e9cd 010a strd r0, r1, [sp, #40] ; 0x28 8005df0: 199d adds r5, r3, r6 8005df2: 461e mov r6, r3 8005df4: e9dd 0102 ldrd r0, r1, [sp, #8] 8005df8: f7fa fe7e bl 8000af8 <__aeabi_d2iz> 8005dfc: 9011 str r0, [sp, #68] ; 0x44 8005dfe: f7fa fb61 bl 80004c4 <__aeabi_i2d> 8005e02: 4602 mov r2, r0 8005e04: 460b mov r3, r1 8005e06: e9dd 0102 ldrd r0, r1, [sp, #8] 8005e0a: f7fa fa0d bl 8000228 <__aeabi_dsub> 8005e0e: 9b11 ldr r3, [sp, #68] ; 0x44 8005e10: e9cd 0102 strd r0, r1, [sp, #8] 8005e14: 3330 adds r3, #48 ; 0x30 8005e16: f806 3b01 strb.w r3, [r6], #1 8005e1a: 42ae cmp r6, r5 8005e1c: f04f 0200 mov.w r2, #0 8005e20: d124 bne.n 8005e6c <_dtoa_r+0x5fc> 8005e22: e9dd 010a ldrd r0, r1, [sp, #40] ; 0x28 8005e26: 4b1a ldr r3, [pc, #104] ; (8005e90 <_dtoa_r+0x620>) 8005e28: f7fa fa00 bl 800022c <__adddf3> 8005e2c: 4602 mov r2, r0 8005e2e: 460b mov r3, r1 8005e30: e9dd 0102 ldrd r0, r1, [sp, #8] 8005e34: f7fa fe40 bl 8000ab8 <__aeabi_dcmpgt> 8005e38: 2800 cmp r0, #0 8005e3a: d171 bne.n 8005f20 <_dtoa_r+0x6b0> 8005e3c: e9dd 230a ldrd r2, r3, [sp, #40] ; 0x28 8005e40: 2000 movs r0, #0 8005e42: 4913 ldr r1, [pc, #76] ; (8005e90 <_dtoa_r+0x620>) 8005e44: f7fa f9f0 bl 8000228 <__aeabi_dsub> 8005e48: 4602 mov r2, r0 8005e4a: 460b mov r3, r1 8005e4c: e9dd 0102 ldrd r0, r1, [sp, #8] 8005e50: f7fa fe14 bl 8000a7c <__aeabi_dcmplt> 8005e54: 2800 cmp r0, #0 8005e56: f43f af2f beq.w 8005cb8 <_dtoa_r+0x448> 8005e5a: f815 3c01 ldrb.w r3, [r5, #-1] 8005e5e: 1e6a subs r2, r5, #1 8005e60: 2b30 cmp r3, #48 ; 0x30 8005e62: d001 beq.n 8005e68 <_dtoa_r+0x5f8> 8005e64: 46ba mov sl, r7 8005e66: e04a b.n 8005efe <_dtoa_r+0x68e> 8005e68: 4615 mov r5, r2 8005e6a: e7f6 b.n 8005e5a <_dtoa_r+0x5ea> 8005e6c: 4b05 ldr r3, [pc, #20] ; (8005e84 <_dtoa_r+0x614>) 8005e6e: f7fa fb93 bl 8000598 <__aeabi_dmul> 8005e72: e9cd 0102 strd r0, r1, [sp, #8] 8005e76: e7bd b.n 8005df4 <_dtoa_r+0x584> 8005e78: 08007518 .word 0x08007518 8005e7c: 080074f0 .word 0x080074f0 8005e80: 3ff00000 .word 0x3ff00000 8005e84: 40240000 .word 0x40240000 8005e88: 401c0000 .word 0x401c0000 8005e8c: 40140000 .word 0x40140000 8005e90: 3fe00000 .word 0x3fe00000 8005e94: 9d06 ldr r5, [sp, #24] 8005e96: e9dd 6702 ldrd r6, r7, [sp, #8] 8005e9a: e9dd 2304 ldrd r2, r3, [sp, #16] 8005e9e: 4630 mov r0, r6 8005ea0: 4639 mov r1, r7 8005ea2: f7fa fca3 bl 80007ec <__aeabi_ddiv> 8005ea6: f7fa fe27 bl 8000af8 <__aeabi_d2iz> 8005eaa: 4681 mov r9, r0 8005eac: f7fa fb0a bl 80004c4 <__aeabi_i2d> 8005eb0: e9dd 2304 ldrd r2, r3, [sp, #16] 8005eb4: f7fa fb70 bl 8000598 <__aeabi_dmul> 8005eb8: 4602 mov r2, r0 8005eba: 460b mov r3, r1 8005ebc: 4630 mov r0, r6 8005ebe: 4639 mov r1, r7 8005ec0: f7fa f9b2 bl 8000228 <__aeabi_dsub> 8005ec4: f109 0630 add.w r6, r9, #48 ; 0x30 8005ec8: f805 6b01 strb.w r6, [r5], #1 8005ecc: 9e06 ldr r6, [sp, #24] 8005ece: 4602 mov r2, r0 8005ed0: 1bae subs r6, r5, r6 8005ed2: 45b0 cmp r8, r6 8005ed4: 460b mov r3, r1 8005ed6: d135 bne.n 8005f44 <_dtoa_r+0x6d4> 8005ed8: f7fa f9a8 bl 800022c <__adddf3> 8005edc: e9dd 2304 ldrd r2, r3, [sp, #16] 8005ee0: 4606 mov r6, r0 8005ee2: 460f mov r7, r1 8005ee4: f7fa fde8 bl 8000ab8 <__aeabi_dcmpgt> 8005ee8: b9c8 cbnz r0, 8005f1e <_dtoa_r+0x6ae> 8005eea: e9dd 2304 ldrd r2, r3, [sp, #16] 8005eee: 4630 mov r0, r6 8005ef0: 4639 mov r1, r7 8005ef2: f7fa fdb9 bl 8000a68 <__aeabi_dcmpeq> 8005ef6: b110 cbz r0, 8005efe <_dtoa_r+0x68e> 8005ef8: f019 0f01 tst.w r9, #1 8005efc: d10f bne.n 8005f1e <_dtoa_r+0x6ae> 8005efe: 4659 mov r1, fp 8005f00: 4620 mov r0, r4 8005f02: f000 fcaa bl 800685a <_Bfree> 8005f06: 2300 movs r3, #0 8005f08: 9a20 ldr r2, [sp, #128] ; 0x80 8005f0a: 702b strb r3, [r5, #0] 8005f0c: f10a 0301 add.w r3, sl, #1 8005f10: 6013 str r3, [r2, #0] 8005f12: 9b22 ldr r3, [sp, #136] ; 0x88 8005f14: 2b00 cmp r3, #0 8005f16: f43f acf3 beq.w 8005900 <_dtoa_r+0x90> 8005f1a: 601d str r5, [r3, #0] 8005f1c: e4f0 b.n 8005900 <_dtoa_r+0x90> 8005f1e: 4657 mov r7, sl 8005f20: f815 2c01 ldrb.w r2, [r5, #-1] 8005f24: 1e6b subs r3, r5, #1 8005f26: 2a39 cmp r2, #57 ; 0x39 8005f28: d106 bne.n 8005f38 <_dtoa_r+0x6c8> 8005f2a: 9a06 ldr r2, [sp, #24] 8005f2c: 429a cmp r2, r3 8005f2e: d107 bne.n 8005f40 <_dtoa_r+0x6d0> 8005f30: 2330 movs r3, #48 ; 0x30 8005f32: 7013 strb r3, [r2, #0] 8005f34: 4613 mov r3, r2 8005f36: 3701 adds r7, #1 8005f38: 781a ldrb r2, [r3, #0] 8005f3a: 3201 adds r2, #1 8005f3c: 701a strb r2, [r3, #0] 8005f3e: e791 b.n 8005e64 <_dtoa_r+0x5f4> 8005f40: 461d mov r5, r3 8005f42: e7ed b.n 8005f20 <_dtoa_r+0x6b0> 8005f44: 2200 movs r2, #0 8005f46: 4b99 ldr r3, [pc, #612] ; (80061ac <_dtoa_r+0x93c>) 8005f48: f7fa fb26 bl 8000598 <__aeabi_dmul> 8005f4c: 2200 movs r2, #0 8005f4e: 2300 movs r3, #0 8005f50: 4606 mov r6, r0 8005f52: 460f mov r7, r1 8005f54: f7fa fd88 bl 8000a68 <__aeabi_dcmpeq> 8005f58: 2800 cmp r0, #0 8005f5a: d09e beq.n 8005e9a <_dtoa_r+0x62a> 8005f5c: e7cf b.n 8005efe <_dtoa_r+0x68e> 8005f5e: 9a09 ldr r2, [sp, #36] ; 0x24 8005f60: 2a00 cmp r2, #0 8005f62: f000 8088 beq.w 8006076 <_dtoa_r+0x806> 8005f66: 9a1e ldr r2, [sp, #120] ; 0x78 8005f68: 2a01 cmp r2, #1 8005f6a: dc6d bgt.n 8006048 <_dtoa_r+0x7d8> 8005f6c: 9a10 ldr r2, [sp, #64] ; 0x40 8005f6e: 2a00 cmp r2, #0 8005f70: d066 beq.n 8006040 <_dtoa_r+0x7d0> 8005f72: f203 4333 addw r3, r3, #1075 ; 0x433 8005f76: 464d mov r5, r9 8005f78: 9e08 ldr r6, [sp, #32] 8005f7a: 9a07 ldr r2, [sp, #28] 8005f7c: 2101 movs r1, #1 8005f7e: 441a add r2, r3 8005f80: 4620 mov r0, r4 8005f82: 4499 add r9, r3 8005f84: 9207 str r2, [sp, #28] 8005f86: f000 fd08 bl 800699a <__i2b> 8005f8a: 4607 mov r7, r0 8005f8c: 2d00 cmp r5, #0 8005f8e: dd0b ble.n 8005fa8 <_dtoa_r+0x738> 8005f90: 9b07 ldr r3, [sp, #28] 8005f92: 2b00 cmp r3, #0 8005f94: dd08 ble.n 8005fa8 <_dtoa_r+0x738> 8005f96: 42ab cmp r3, r5 8005f98: bfa8 it ge 8005f9a: 462b movge r3, r5 8005f9c: 9a07 ldr r2, [sp, #28] 8005f9e: eba9 0903 sub.w r9, r9, r3 8005fa2: 1aed subs r5, r5, r3 8005fa4: 1ad3 subs r3, r2, r3 8005fa6: 9307 str r3, [sp, #28] 8005fa8: 9b08 ldr r3, [sp, #32] 8005faa: b1eb cbz r3, 8005fe8 <_dtoa_r+0x778> 8005fac: 9b09 ldr r3, [sp, #36] ; 0x24 8005fae: 2b00 cmp r3, #0 8005fb0: d065 beq.n 800607e <_dtoa_r+0x80e> 8005fb2: b18e cbz r6, 8005fd8 <_dtoa_r+0x768> 8005fb4: 4639 mov r1, r7 8005fb6: 4632 mov r2, r6 8005fb8: 4620 mov r0, r4 8005fba: f000 fd8d bl 8006ad8 <__pow5mult> 8005fbe: 465a mov r2, fp 8005fc0: 4601 mov r1, r0 8005fc2: 4607 mov r7, r0 8005fc4: 4620 mov r0, r4 8005fc6: f000 fcf1 bl 80069ac <__multiply> 8005fca: 4659 mov r1, fp 8005fcc: 900a str r0, [sp, #40] ; 0x28 8005fce: 4620 mov r0, r4 8005fd0: f000 fc43 bl 800685a <_Bfree> 8005fd4: 9b0a ldr r3, [sp, #40] ; 0x28 8005fd6: 469b mov fp, r3 8005fd8: 9b08 ldr r3, [sp, #32] 8005fda: 1b9a subs r2, r3, r6 8005fdc: d004 beq.n 8005fe8 <_dtoa_r+0x778> 8005fde: 4659 mov r1, fp 8005fe0: 4620 mov r0, r4 8005fe2: f000 fd79 bl 8006ad8 <__pow5mult> 8005fe6: 4683 mov fp, r0 8005fe8: 2101 movs r1, #1 8005fea: 4620 mov r0, r4 8005fec: f000 fcd5 bl 800699a <__i2b> 8005ff0: 9b0c ldr r3, [sp, #48] ; 0x30 8005ff2: 4606 mov r6, r0 8005ff4: 2b00 cmp r3, #0 8005ff6: f000 81c6 beq.w 8006386 <_dtoa_r+0xb16> 8005ffa: 461a mov r2, r3 8005ffc: 4601 mov r1, r0 8005ffe: 4620 mov r0, r4 8006000: f000 fd6a bl 8006ad8 <__pow5mult> 8006004: 9b1e ldr r3, [sp, #120] ; 0x78 8006006: 4606 mov r6, r0 8006008: 2b01 cmp r3, #1 800600a: dc3e bgt.n 800608a <_dtoa_r+0x81a> 800600c: 9b02 ldr r3, [sp, #8] 800600e: 2b00 cmp r3, #0 8006010: d137 bne.n 8006082 <_dtoa_r+0x812> 8006012: 9b03 ldr r3, [sp, #12] 8006014: f3c3 0313 ubfx r3, r3, #0, #20 8006018: 2b00 cmp r3, #0 800601a: d134 bne.n 8006086 <_dtoa_r+0x816> 800601c: 9b03 ldr r3, [sp, #12] 800601e: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000 8006022: 0d1b lsrs r3, r3, #20 8006024: 051b lsls r3, r3, #20 8006026: b12b cbz r3, 8006034 <_dtoa_r+0x7c4> 8006028: 9b07 ldr r3, [sp, #28] 800602a: f109 0901 add.w r9, r9, #1 800602e: 3301 adds r3, #1 8006030: 9307 str r3, [sp, #28] 8006032: 2301 movs r3, #1 8006034: 9308 str r3, [sp, #32] 8006036: 9b0c ldr r3, [sp, #48] ; 0x30 8006038: 2b00 cmp r3, #0 800603a: d128 bne.n 800608e <_dtoa_r+0x81e> 800603c: 2001 movs r0, #1 800603e: e02e b.n 800609e <_dtoa_r+0x82e> 8006040: 9b12 ldr r3, [sp, #72] ; 0x48 8006042: f1c3 0336 rsb r3, r3, #54 ; 0x36 8006046: e796 b.n 8005f76 <_dtoa_r+0x706> 8006048: 9b08 ldr r3, [sp, #32] 800604a: f108 36ff add.w r6, r8, #4294967295 800604e: 42b3 cmp r3, r6 8006050: bfb7 itett lt 8006052: 9b08 ldrlt r3, [sp, #32] 8006054: 1b9e subge r6, r3, r6 8006056: 1af2 sublt r2, r6, r3 8006058: 9b0c ldrlt r3, [sp, #48] ; 0x30 800605a: bfbf itttt lt 800605c: 9608 strlt r6, [sp, #32] 800605e: 189b addlt r3, r3, r2 8006060: 930c strlt r3, [sp, #48] ; 0x30 8006062: 2600 movlt r6, #0 8006064: f1b8 0f00 cmp.w r8, #0 8006068: bfb9 ittee lt 800606a: eba9 0508 sublt.w r5, r9, r8 800606e: 2300 movlt r3, #0 8006070: 464d movge r5, r9 8006072: 4643 movge r3, r8 8006074: e781 b.n 8005f7a <_dtoa_r+0x70a> 8006076: 9e08 ldr r6, [sp, #32] 8006078: 464d mov r5, r9 800607a: 9f09 ldr r7, [sp, #36] ; 0x24 800607c: e786 b.n 8005f8c <_dtoa_r+0x71c> 800607e: 9a08 ldr r2, [sp, #32] 8006080: e7ad b.n 8005fde <_dtoa_r+0x76e> 8006082: 2300 movs r3, #0 8006084: e7d6 b.n 8006034 <_dtoa_r+0x7c4> 8006086: 9b02 ldr r3, [sp, #8] 8006088: e7d4 b.n 8006034 <_dtoa_r+0x7c4> 800608a: 2300 movs r3, #0 800608c: 9308 str r3, [sp, #32] 800608e: 6933 ldr r3, [r6, #16] 8006090: eb06 0383 add.w r3, r6, r3, lsl #2 8006094: 6918 ldr r0, [r3, #16] 8006096: f000 fc32 bl 80068fe <__hi0bits> 800609a: f1c0 0020 rsb r0, r0, #32 800609e: 9b07 ldr r3, [sp, #28] 80060a0: 4418 add r0, r3 80060a2: f010 001f ands.w r0, r0, #31 80060a6: d047 beq.n 8006138 <_dtoa_r+0x8c8> 80060a8: f1c0 0320 rsb r3, r0, #32 80060ac: 2b04 cmp r3, #4 80060ae: dd3b ble.n 8006128 <_dtoa_r+0x8b8> 80060b0: 9b07 ldr r3, [sp, #28] 80060b2: f1c0 001c rsb r0, r0, #28 80060b6: 4481 add r9, r0 80060b8: 4405 add r5, r0 80060ba: 4403 add r3, r0 80060bc: 9307 str r3, [sp, #28] 80060be: f1b9 0f00 cmp.w r9, #0 80060c2: dd05 ble.n 80060d0 <_dtoa_r+0x860> 80060c4: 4659 mov r1, fp 80060c6: 464a mov r2, r9 80060c8: 4620 mov r0, r4 80060ca: f000 fd53 bl 8006b74 <__lshift> 80060ce: 4683 mov fp, r0 80060d0: 9b07 ldr r3, [sp, #28] 80060d2: 2b00 cmp r3, #0 80060d4: dd05 ble.n 80060e2 <_dtoa_r+0x872> 80060d6: 4631 mov r1, r6 80060d8: 461a mov r2, r3 80060da: 4620 mov r0, r4 80060dc: f000 fd4a bl 8006b74 <__lshift> 80060e0: 4606 mov r6, r0 80060e2: 9b0d ldr r3, [sp, #52] ; 0x34 80060e4: b353 cbz r3, 800613c <_dtoa_r+0x8cc> 80060e6: 4631 mov r1, r6 80060e8: 4658 mov r0, fp 80060ea: f000 fd97 bl 8006c1c <__mcmp> 80060ee: 2800 cmp r0, #0 80060f0: da24 bge.n 800613c <_dtoa_r+0x8cc> 80060f2: 2300 movs r3, #0 80060f4: 4659 mov r1, fp 80060f6: 220a movs r2, #10 80060f8: 4620 mov r0, r4 80060fa: f000 fbc5 bl 8006888 <__multadd> 80060fe: 9b09 ldr r3, [sp, #36] ; 0x24 8006100: f10a 3aff add.w sl, sl, #4294967295 8006104: 4683 mov fp, r0 8006106: 2b00 cmp r3, #0 8006108: f000 8144 beq.w 8006394 <_dtoa_r+0xb24> 800610c: 2300 movs r3, #0 800610e: 4639 mov r1, r7 8006110: 220a movs r2, #10 8006112: 4620 mov r0, r4 8006114: f000 fbb8 bl 8006888 <__multadd> 8006118: 9b04 ldr r3, [sp, #16] 800611a: 4607 mov r7, r0 800611c: 2b00 cmp r3, #0 800611e: dc4d bgt.n 80061bc <_dtoa_r+0x94c> 8006120: 9b1e ldr r3, [sp, #120] ; 0x78 8006122: 2b02 cmp r3, #2 8006124: dd4a ble.n 80061bc <_dtoa_r+0x94c> 8006126: e011 b.n 800614c <_dtoa_r+0x8dc> 8006128: d0c9 beq.n 80060be <_dtoa_r+0x84e> 800612a: 9a07 ldr r2, [sp, #28] 800612c: 331c adds r3, #28 800612e: 441a add r2, r3 8006130: 4499 add r9, r3 8006132: 441d add r5, r3 8006134: 4613 mov r3, r2 8006136: e7c1 b.n 80060bc <_dtoa_r+0x84c> 8006138: 4603 mov r3, r0 800613a: e7f6 b.n 800612a <_dtoa_r+0x8ba> 800613c: f1b8 0f00 cmp.w r8, #0 8006140: dc36 bgt.n 80061b0 <_dtoa_r+0x940> 8006142: 9b1e ldr r3, [sp, #120] ; 0x78 8006144: 2b02 cmp r3, #2 8006146: dd33 ble.n 80061b0 <_dtoa_r+0x940> 8006148: f8cd 8010 str.w r8, [sp, #16] 800614c: 9b04 ldr r3, [sp, #16] 800614e: b963 cbnz r3, 800616a <_dtoa_r+0x8fa> 8006150: 4631 mov r1, r6 8006152: 2205 movs r2, #5 8006154: 4620 mov r0, r4 8006156: f000 fb97 bl 8006888 <__multadd> 800615a: 4601 mov r1, r0 800615c: 4606 mov r6, r0 800615e: 4658 mov r0, fp 8006160: f000 fd5c bl 8006c1c <__mcmp> 8006164: 2800 cmp r0, #0 8006166: f73f add3 bgt.w 8005d10 <_dtoa_r+0x4a0> 800616a: 9b1f ldr r3, [sp, #124] ; 0x7c 800616c: 9d06 ldr r5, [sp, #24] 800616e: ea6f 0a03 mvn.w sl, r3 8006172: f04f 0900 mov.w r9, #0 8006176: 4631 mov r1, r6 8006178: 4620 mov r0, r4 800617a: f000 fb6e bl 800685a <_Bfree> 800617e: 2f00 cmp r7, #0 8006180: f43f aebd beq.w 8005efe <_dtoa_r+0x68e> 8006184: f1b9 0f00 cmp.w r9, #0 8006188: d005 beq.n 8006196 <_dtoa_r+0x926> 800618a: 45b9 cmp r9, r7 800618c: d003 beq.n 8006196 <_dtoa_r+0x926> 800618e: 4649 mov r1, r9 8006190: 4620 mov r0, r4 8006192: f000 fb62 bl 800685a <_Bfree> 8006196: 4639 mov r1, r7 8006198: 4620 mov r0, r4 800619a: f000 fb5e bl 800685a <_Bfree> 800619e: e6ae b.n 8005efe <_dtoa_r+0x68e> 80061a0: 2600 movs r6, #0 80061a2: 4637 mov r7, r6 80061a4: e7e1 b.n 800616a <_dtoa_r+0x8fa> 80061a6: 46ba mov sl, r7 80061a8: 4637 mov r7, r6 80061aa: e5b1 b.n 8005d10 <_dtoa_r+0x4a0> 80061ac: 40240000 .word 0x40240000 80061b0: 9b09 ldr r3, [sp, #36] ; 0x24 80061b2: f8cd 8010 str.w r8, [sp, #16] 80061b6: 2b00 cmp r3, #0 80061b8: f000 80f3 beq.w 80063a2 <_dtoa_r+0xb32> 80061bc: 2d00 cmp r5, #0 80061be: dd05 ble.n 80061cc <_dtoa_r+0x95c> 80061c0: 4639 mov r1, r7 80061c2: 462a mov r2, r5 80061c4: 4620 mov r0, r4 80061c6: f000 fcd5 bl 8006b74 <__lshift> 80061ca: 4607 mov r7, r0 80061cc: 9b08 ldr r3, [sp, #32] 80061ce: 2b00 cmp r3, #0 80061d0: d04c beq.n 800626c <_dtoa_r+0x9fc> 80061d2: 6879 ldr r1, [r7, #4] 80061d4: 4620 mov r0, r4 80061d6: f000 fb0c bl 80067f2 <_Balloc> 80061da: 4605 mov r5, r0 80061dc: 693a ldr r2, [r7, #16] 80061de: f107 010c add.w r1, r7, #12 80061e2: 3202 adds r2, #2 80061e4: 0092 lsls r2, r2, #2 80061e6: 300c adds r0, #12 80061e8: f000 faf8 bl 80067dc 80061ec: 2201 movs r2, #1 80061ee: 4629 mov r1, r5 80061f0: 4620 mov r0, r4 80061f2: f000 fcbf bl 8006b74 <__lshift> 80061f6: 46b9 mov r9, r7 80061f8: 4607 mov r7, r0 80061fa: 9b06 ldr r3, [sp, #24] 80061fc: 9307 str r3, [sp, #28] 80061fe: 9b02 ldr r3, [sp, #8] 8006200: f003 0301 and.w r3, r3, #1 8006204: 9308 str r3, [sp, #32] 8006206: 4631 mov r1, r6 8006208: 4658 mov r0, fp 800620a: f7ff faa1 bl 8005750 800620e: 4649 mov r1, r9 8006210: 4605 mov r5, r0 8006212: f100 0830 add.w r8, r0, #48 ; 0x30 8006216: 4658 mov r0, fp 8006218: f000 fd00 bl 8006c1c <__mcmp> 800621c: 463a mov r2, r7 800621e: 9002 str r0, [sp, #8] 8006220: 4631 mov r1, r6 8006222: 4620 mov r0, r4 8006224: f000 fd14 bl 8006c50 <__mdiff> 8006228: 68c3 ldr r3, [r0, #12] 800622a: 4602 mov r2, r0 800622c: bb03 cbnz r3, 8006270 <_dtoa_r+0xa00> 800622e: 4601 mov r1, r0 8006230: 9009 str r0, [sp, #36] ; 0x24 8006232: 4658 mov r0, fp 8006234: f000 fcf2 bl 8006c1c <__mcmp> 8006238: 4603 mov r3, r0 800623a: 9a09 ldr r2, [sp, #36] ; 0x24 800623c: 4611 mov r1, r2 800623e: 4620 mov r0, r4 8006240: 9309 str r3, [sp, #36] ; 0x24 8006242: f000 fb0a bl 800685a <_Bfree> 8006246: 9b09 ldr r3, [sp, #36] ; 0x24 8006248: b9a3 cbnz r3, 8006274 <_dtoa_r+0xa04> 800624a: 9a1e ldr r2, [sp, #120] ; 0x78 800624c: b992 cbnz r2, 8006274 <_dtoa_r+0xa04> 800624e: 9a08 ldr r2, [sp, #32] 8006250: b982 cbnz r2, 8006274 <_dtoa_r+0xa04> 8006252: f1b8 0f39 cmp.w r8, #57 ; 0x39 8006256: d029 beq.n 80062ac <_dtoa_r+0xa3c> 8006258: 9b02 ldr r3, [sp, #8] 800625a: 2b00 cmp r3, #0 800625c: dd01 ble.n 8006262 <_dtoa_r+0x9f2> 800625e: f105 0831 add.w r8, r5, #49 ; 0x31 8006262: 9b07 ldr r3, [sp, #28] 8006264: 1c5d adds r5, r3, #1 8006266: f883 8000 strb.w r8, [r3] 800626a: e784 b.n 8006176 <_dtoa_r+0x906> 800626c: 4638 mov r0, r7 800626e: e7c2 b.n 80061f6 <_dtoa_r+0x986> 8006270: 2301 movs r3, #1 8006272: e7e3 b.n 800623c <_dtoa_r+0x9cc> 8006274: 9a02 ldr r2, [sp, #8] 8006276: 2a00 cmp r2, #0 8006278: db04 blt.n 8006284 <_dtoa_r+0xa14> 800627a: d123 bne.n 80062c4 <_dtoa_r+0xa54> 800627c: 9a1e ldr r2, [sp, #120] ; 0x78 800627e: bb0a cbnz r2, 80062c4 <_dtoa_r+0xa54> 8006280: 9a08 ldr r2, [sp, #32] 8006282: b9fa cbnz r2, 80062c4 <_dtoa_r+0xa54> 8006284: 2b00 cmp r3, #0 8006286: ddec ble.n 8006262 <_dtoa_r+0x9f2> 8006288: 4659 mov r1, fp 800628a: 2201 movs r2, #1 800628c: 4620 mov r0, r4 800628e: f000 fc71 bl 8006b74 <__lshift> 8006292: 4631 mov r1, r6 8006294: 4683 mov fp, r0 8006296: f000 fcc1 bl 8006c1c <__mcmp> 800629a: 2800 cmp r0, #0 800629c: dc03 bgt.n 80062a6 <_dtoa_r+0xa36> 800629e: d1e0 bne.n 8006262 <_dtoa_r+0x9f2> 80062a0: f018 0f01 tst.w r8, #1 80062a4: d0dd beq.n 8006262 <_dtoa_r+0x9f2> 80062a6: f1b8 0f39 cmp.w r8, #57 ; 0x39 80062aa: d1d8 bne.n 800625e <_dtoa_r+0x9ee> 80062ac: 9b07 ldr r3, [sp, #28] 80062ae: 9a07 ldr r2, [sp, #28] 80062b0: 1c5d adds r5, r3, #1 80062b2: 2339 movs r3, #57 ; 0x39 80062b4: 7013 strb r3, [r2, #0] 80062b6: f815 3c01 ldrb.w r3, [r5, #-1] 80062ba: 1e6a subs r2, r5, #1 80062bc: 2b39 cmp r3, #57 ; 0x39 80062be: d04d beq.n 800635c <_dtoa_r+0xaec> 80062c0: 3301 adds r3, #1 80062c2: e052 b.n 800636a <_dtoa_r+0xafa> 80062c4: 9a07 ldr r2, [sp, #28] 80062c6: 2b00 cmp r3, #0 80062c8: f102 0501 add.w r5, r2, #1 80062cc: dd06 ble.n 80062dc <_dtoa_r+0xa6c> 80062ce: f1b8 0f39 cmp.w r8, #57 ; 0x39 80062d2: d0eb beq.n 80062ac <_dtoa_r+0xa3c> 80062d4: f108 0801 add.w r8, r8, #1 80062d8: 9b07 ldr r3, [sp, #28] 80062da: e7c4 b.n 8006266 <_dtoa_r+0x9f6> 80062dc: 9b06 ldr r3, [sp, #24] 80062de: 9a04 ldr r2, [sp, #16] 80062e0: 1aeb subs r3, r5, r3 80062e2: 4293 cmp r3, r2 80062e4: f805 8c01 strb.w r8, [r5, #-1] 80062e8: d021 beq.n 800632e <_dtoa_r+0xabe> 80062ea: 4659 mov r1, fp 80062ec: 2300 movs r3, #0 80062ee: 220a movs r2, #10 80062f0: 4620 mov r0, r4 80062f2: f000 fac9 bl 8006888 <__multadd> 80062f6: 45b9 cmp r9, r7 80062f8: 4683 mov fp, r0 80062fa: f04f 0300 mov.w r3, #0 80062fe: f04f 020a mov.w r2, #10 8006302: 4649 mov r1, r9 8006304: 4620 mov r0, r4 8006306: d105 bne.n 8006314 <_dtoa_r+0xaa4> 8006308: f000 fabe bl 8006888 <__multadd> 800630c: 4681 mov r9, r0 800630e: 4607 mov r7, r0 8006310: 9507 str r5, [sp, #28] 8006312: e778 b.n 8006206 <_dtoa_r+0x996> 8006314: f000 fab8 bl 8006888 <__multadd> 8006318: 4639 mov r1, r7 800631a: 4681 mov r9, r0 800631c: 2300 movs r3, #0 800631e: 220a movs r2, #10 8006320: 4620 mov r0, r4 8006322: f000 fab1 bl 8006888 <__multadd> 8006326: 4607 mov r7, r0 8006328: e7f2 b.n 8006310 <_dtoa_r+0xaa0> 800632a: f04f 0900 mov.w r9, #0 800632e: 4659 mov r1, fp 8006330: 2201 movs r2, #1 8006332: 4620 mov r0, r4 8006334: f000 fc1e bl 8006b74 <__lshift> 8006338: 4631 mov r1, r6 800633a: 4683 mov fp, r0 800633c: f000 fc6e bl 8006c1c <__mcmp> 8006340: 2800 cmp r0, #0 8006342: dcb8 bgt.n 80062b6 <_dtoa_r+0xa46> 8006344: d102 bne.n 800634c <_dtoa_r+0xadc> 8006346: f018 0f01 tst.w r8, #1 800634a: d1b4 bne.n 80062b6 <_dtoa_r+0xa46> 800634c: f815 3c01 ldrb.w r3, [r5, #-1] 8006350: 1e6a subs r2, r5, #1 8006352: 2b30 cmp r3, #48 ; 0x30 8006354: f47f af0f bne.w 8006176 <_dtoa_r+0x906> 8006358: 4615 mov r5, r2 800635a: e7f7 b.n 800634c <_dtoa_r+0xadc> 800635c: 9b06 ldr r3, [sp, #24] 800635e: 4293 cmp r3, r2 8006360: d105 bne.n 800636e <_dtoa_r+0xafe> 8006362: 2331 movs r3, #49 ; 0x31 8006364: 9a06 ldr r2, [sp, #24] 8006366: f10a 0a01 add.w sl, sl, #1 800636a: 7013 strb r3, [r2, #0] 800636c: e703 b.n 8006176 <_dtoa_r+0x906> 800636e: 4615 mov r5, r2 8006370: e7a1 b.n 80062b6 <_dtoa_r+0xa46> 8006372: 4b17 ldr r3, [pc, #92] ; (80063d0 <_dtoa_r+0xb60>) 8006374: f7ff bae1 b.w 800593a <_dtoa_r+0xca> 8006378: 9b22 ldr r3, [sp, #136] ; 0x88 800637a: 2b00 cmp r3, #0 800637c: f47f aabb bne.w 80058f6 <_dtoa_r+0x86> 8006380: 4b14 ldr r3, [pc, #80] ; (80063d4 <_dtoa_r+0xb64>) 8006382: f7ff bada b.w 800593a <_dtoa_r+0xca> 8006386: 9b1e ldr r3, [sp, #120] ; 0x78 8006388: 2b01 cmp r3, #1 800638a: f77f ae3f ble.w 800600c <_dtoa_r+0x79c> 800638e: 9b0c ldr r3, [sp, #48] ; 0x30 8006390: 9308 str r3, [sp, #32] 8006392: e653 b.n 800603c <_dtoa_r+0x7cc> 8006394: 9b04 ldr r3, [sp, #16] 8006396: 2b00 cmp r3, #0 8006398: dc03 bgt.n 80063a2 <_dtoa_r+0xb32> 800639a: 9b1e ldr r3, [sp, #120] ; 0x78 800639c: 2b02 cmp r3, #2 800639e: f73f aed5 bgt.w 800614c <_dtoa_r+0x8dc> 80063a2: 9d06 ldr r5, [sp, #24] 80063a4: 4631 mov r1, r6 80063a6: 4658 mov r0, fp 80063a8: f7ff f9d2 bl 8005750 80063ac: 9b06 ldr r3, [sp, #24] 80063ae: f100 0830 add.w r8, r0, #48 ; 0x30 80063b2: f805 8b01 strb.w r8, [r5], #1 80063b6: 9a04 ldr r2, [sp, #16] 80063b8: 1aeb subs r3, r5, r3 80063ba: 429a cmp r2, r3 80063bc: ddb5 ble.n 800632a <_dtoa_r+0xaba> 80063be: 4659 mov r1, fp 80063c0: 2300 movs r3, #0 80063c2: 220a movs r2, #10 80063c4: 4620 mov r0, r4 80063c6: f000 fa5f bl 8006888 <__multadd> 80063ca: 4683 mov fp, r0 80063cc: e7ea b.n 80063a4 <_dtoa_r+0xb34> 80063ce: bf00 nop 80063d0: 08007458 .word 0x08007458 80063d4: 0800747c .word 0x0800747c 080063d8 <__sflush_r>: 80063d8: 898a ldrh r2, [r1, #12] 80063da: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 80063de: 4605 mov r5, r0 80063e0: 0710 lsls r0, r2, #28 80063e2: 460c mov r4, r1 80063e4: d458 bmi.n 8006498 <__sflush_r+0xc0> 80063e6: 684b ldr r3, [r1, #4] 80063e8: 2b00 cmp r3, #0 80063ea: dc05 bgt.n 80063f8 <__sflush_r+0x20> 80063ec: 6c0b ldr r3, [r1, #64] ; 0x40 80063ee: 2b00 cmp r3, #0 80063f0: dc02 bgt.n 80063f8 <__sflush_r+0x20> 80063f2: 2000 movs r0, #0 80063f4: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 80063f8: 6ae6 ldr r6, [r4, #44] ; 0x2c 80063fa: 2e00 cmp r6, #0 80063fc: d0f9 beq.n 80063f2 <__sflush_r+0x1a> 80063fe: 2300 movs r3, #0 8006400: f412 5280 ands.w r2, r2, #4096 ; 0x1000 8006404: 682f ldr r7, [r5, #0] 8006406: 6a21 ldr r1, [r4, #32] 8006408: 602b str r3, [r5, #0] 800640a: d032 beq.n 8006472 <__sflush_r+0x9a> 800640c: 6d60 ldr r0, [r4, #84] ; 0x54 800640e: 89a3 ldrh r3, [r4, #12] 8006410: 075a lsls r2, r3, #29 8006412: d505 bpl.n 8006420 <__sflush_r+0x48> 8006414: 6863 ldr r3, [r4, #4] 8006416: 1ac0 subs r0, r0, r3 8006418: 6b63 ldr r3, [r4, #52] ; 0x34 800641a: b10b cbz r3, 8006420 <__sflush_r+0x48> 800641c: 6c23 ldr r3, [r4, #64] ; 0x40 800641e: 1ac0 subs r0, r0, r3 8006420: 2300 movs r3, #0 8006422: 4602 mov r2, r0 8006424: 6ae6 ldr r6, [r4, #44] ; 0x2c 8006426: 6a21 ldr r1, [r4, #32] 8006428: 4628 mov r0, r5 800642a: 47b0 blx r6 800642c: 1c43 adds r3, r0, #1 800642e: 89a3 ldrh r3, [r4, #12] 8006430: d106 bne.n 8006440 <__sflush_r+0x68> 8006432: 6829 ldr r1, [r5, #0] 8006434: 291d cmp r1, #29 8006436: d848 bhi.n 80064ca <__sflush_r+0xf2> 8006438: 4a29 ldr r2, [pc, #164] ; (80064e0 <__sflush_r+0x108>) 800643a: 40ca lsrs r2, r1 800643c: 07d6 lsls r6, r2, #31 800643e: d544 bpl.n 80064ca <__sflush_r+0xf2> 8006440: 2200 movs r2, #0 8006442: 6062 str r2, [r4, #4] 8006444: 6922 ldr r2, [r4, #16] 8006446: 04d9 lsls r1, r3, #19 8006448: 6022 str r2, [r4, #0] 800644a: d504 bpl.n 8006456 <__sflush_r+0x7e> 800644c: 1c42 adds r2, r0, #1 800644e: d101 bne.n 8006454 <__sflush_r+0x7c> 8006450: 682b ldr r3, [r5, #0] 8006452: b903 cbnz r3, 8006456 <__sflush_r+0x7e> 8006454: 6560 str r0, [r4, #84] ; 0x54 8006456: 6b61 ldr r1, [r4, #52] ; 0x34 8006458: 602f str r7, [r5, #0] 800645a: 2900 cmp r1, #0 800645c: d0c9 beq.n 80063f2 <__sflush_r+0x1a> 800645e: f104 0344 add.w r3, r4, #68 ; 0x44 8006462: 4299 cmp r1, r3 8006464: d002 beq.n 800646c <__sflush_r+0x94> 8006466: 4628 mov r0, r5 8006468: f000 fcae bl 8006dc8 <_free_r> 800646c: 2000 movs r0, #0 800646e: 6360 str r0, [r4, #52] ; 0x34 8006470: e7c0 b.n 80063f4 <__sflush_r+0x1c> 8006472: 2301 movs r3, #1 8006474: 4628 mov r0, r5 8006476: 47b0 blx r6 8006478: 1c41 adds r1, r0, #1 800647a: d1c8 bne.n 800640e <__sflush_r+0x36> 800647c: 682b ldr r3, [r5, #0] 800647e: 2b00 cmp r3, #0 8006480: d0c5 beq.n 800640e <__sflush_r+0x36> 8006482: 2b1d cmp r3, #29 8006484: d001 beq.n 800648a <__sflush_r+0xb2> 8006486: 2b16 cmp r3, #22 8006488: d101 bne.n 800648e <__sflush_r+0xb6> 800648a: 602f str r7, [r5, #0] 800648c: e7b1 b.n 80063f2 <__sflush_r+0x1a> 800648e: 89a3 ldrh r3, [r4, #12] 8006490: f043 0340 orr.w r3, r3, #64 ; 0x40 8006494: 81a3 strh r3, [r4, #12] 8006496: e7ad b.n 80063f4 <__sflush_r+0x1c> 8006498: 690f ldr r7, [r1, #16] 800649a: 2f00 cmp r7, #0 800649c: d0a9 beq.n 80063f2 <__sflush_r+0x1a> 800649e: 0793 lsls r3, r2, #30 80064a0: bf18 it ne 80064a2: 2300 movne r3, #0 80064a4: 680e ldr r6, [r1, #0] 80064a6: bf08 it eq 80064a8: 694b ldreq r3, [r1, #20] 80064aa: eba6 0807 sub.w r8, r6, r7 80064ae: 600f str r7, [r1, #0] 80064b0: 608b str r3, [r1, #8] 80064b2: f1b8 0f00 cmp.w r8, #0 80064b6: dd9c ble.n 80063f2 <__sflush_r+0x1a> 80064b8: 4643 mov r3, r8 80064ba: 463a mov r2, r7 80064bc: 6a21 ldr r1, [r4, #32] 80064be: 4628 mov r0, r5 80064c0: 6aa6 ldr r6, [r4, #40] ; 0x28 80064c2: 47b0 blx r6 80064c4: 2800 cmp r0, #0 80064c6: dc06 bgt.n 80064d6 <__sflush_r+0xfe> 80064c8: 89a3 ldrh r3, [r4, #12] 80064ca: f043 0340 orr.w r3, r3, #64 ; 0x40 80064ce: 81a3 strh r3, [r4, #12] 80064d0: f04f 30ff mov.w r0, #4294967295 80064d4: e78e b.n 80063f4 <__sflush_r+0x1c> 80064d6: 4407 add r7, r0 80064d8: eba8 0800 sub.w r8, r8, r0 80064dc: e7e9 b.n 80064b2 <__sflush_r+0xda> 80064de: bf00 nop 80064e0: 20400001 .word 0x20400001 080064e4 <_fflush_r>: 80064e4: b538 push {r3, r4, r5, lr} 80064e6: 690b ldr r3, [r1, #16] 80064e8: 4605 mov r5, r0 80064ea: 460c mov r4, r1 80064ec: b1db cbz r3, 8006526 <_fflush_r+0x42> 80064ee: b118 cbz r0, 80064f8 <_fflush_r+0x14> 80064f0: 6983 ldr r3, [r0, #24] 80064f2: b90b cbnz r3, 80064f8 <_fflush_r+0x14> 80064f4: f000 f860 bl 80065b8 <__sinit> 80064f8: 4b0c ldr r3, [pc, #48] ; (800652c <_fflush_r+0x48>) 80064fa: 429c cmp r4, r3 80064fc: d109 bne.n 8006512 <_fflush_r+0x2e> 80064fe: 686c ldr r4, [r5, #4] 8006500: f9b4 300c ldrsh.w r3, [r4, #12] 8006504: b17b cbz r3, 8006526 <_fflush_r+0x42> 8006506: 4621 mov r1, r4 8006508: 4628 mov r0, r5 800650a: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 800650e: f7ff bf63 b.w 80063d8 <__sflush_r> 8006512: 4b07 ldr r3, [pc, #28] ; (8006530 <_fflush_r+0x4c>) 8006514: 429c cmp r4, r3 8006516: d101 bne.n 800651c <_fflush_r+0x38> 8006518: 68ac ldr r4, [r5, #8] 800651a: e7f1 b.n 8006500 <_fflush_r+0x1c> 800651c: 4b05 ldr r3, [pc, #20] ; (8006534 <_fflush_r+0x50>) 800651e: 429c cmp r4, r3 8006520: bf08 it eq 8006522: 68ec ldreq r4, [r5, #12] 8006524: e7ec b.n 8006500 <_fflush_r+0x1c> 8006526: 2000 movs r0, #0 8006528: bd38 pop {r3, r4, r5, pc} 800652a: bf00 nop 800652c: 080074ac .word 0x080074ac 8006530: 080074cc .word 0x080074cc 8006534: 0800748c .word 0x0800748c 08006538 : 8006538: 2300 movs r3, #0 800653a: b510 push {r4, lr} 800653c: 4604 mov r4, r0 800653e: e9c0 3300 strd r3, r3, [r0] 8006542: 6083 str r3, [r0, #8] 8006544: 8181 strh r1, [r0, #12] 8006546: 6643 str r3, [r0, #100] ; 0x64 8006548: 81c2 strh r2, [r0, #14] 800654a: e9c0 3304 strd r3, r3, [r0, #16] 800654e: 6183 str r3, [r0, #24] 8006550: 4619 mov r1, r3 8006552: 2208 movs r2, #8 8006554: 305c adds r0, #92 ; 0x5c 8006556: f7fe fab1 bl 8004abc 800655a: 4b05 ldr r3, [pc, #20] ; (8006570 ) 800655c: 6224 str r4, [r4, #32] 800655e: 6263 str r3, [r4, #36] ; 0x24 8006560: 4b04 ldr r3, [pc, #16] ; (8006574 ) 8006562: 62a3 str r3, [r4, #40] ; 0x28 8006564: 4b04 ldr r3, [pc, #16] ; (8006578 ) 8006566: 62e3 str r3, [r4, #44] ; 0x2c 8006568: 4b04 ldr r3, [pc, #16] ; (800657c ) 800656a: 6323 str r3, [r4, #48] ; 0x30 800656c: bd10 pop {r4, pc} 800656e: bf00 nop 8006570: 080071b1 .word 0x080071b1 8006574: 080071d3 .word 0x080071d3 8006578: 0800720b .word 0x0800720b 800657c: 0800722f .word 0x0800722f 08006580 <_cleanup_r>: 8006580: 4901 ldr r1, [pc, #4] ; (8006588 <_cleanup_r+0x8>) 8006582: f000 b885 b.w 8006690 <_fwalk_reent> 8006586: bf00 nop 8006588: 080064e5 .word 0x080064e5 0800658c <__sfmoreglue>: 800658c: b570 push {r4, r5, r6, lr} 800658e: 2568 movs r5, #104 ; 0x68 8006590: 1e4a subs r2, r1, #1 8006592: 4355 muls r5, r2 8006594: 460e mov r6, r1 8006596: f105 0174 add.w r1, r5, #116 ; 0x74 800659a: f000 fc61 bl 8006e60 <_malloc_r> 800659e: 4604 mov r4, r0 80065a0: b140 cbz r0, 80065b4 <__sfmoreglue+0x28> 80065a2: 2100 movs r1, #0 80065a4: e9c0 1600 strd r1, r6, [r0] 80065a8: 300c adds r0, #12 80065aa: 60a0 str r0, [r4, #8] 80065ac: f105 0268 add.w r2, r5, #104 ; 0x68 80065b0: f7fe fa84 bl 8004abc 80065b4: 4620 mov r0, r4 80065b6: bd70 pop {r4, r5, r6, pc} 080065b8 <__sinit>: 80065b8: 6983 ldr r3, [r0, #24] 80065ba: b510 push {r4, lr} 80065bc: 4604 mov r4, r0 80065be: bb33 cbnz r3, 800660e <__sinit+0x56> 80065c0: e9c0 3312 strd r3, r3, [r0, #72] ; 0x48 80065c4: 6503 str r3, [r0, #80] ; 0x50 80065c6: 4b12 ldr r3, [pc, #72] ; (8006610 <__sinit+0x58>) 80065c8: 4a12 ldr r2, [pc, #72] ; (8006614 <__sinit+0x5c>) 80065ca: 681b ldr r3, [r3, #0] 80065cc: 6282 str r2, [r0, #40] ; 0x28 80065ce: 4298 cmp r0, r3 80065d0: bf04 itt eq 80065d2: 2301 moveq r3, #1 80065d4: 6183 streq r3, [r0, #24] 80065d6: f000 f81f bl 8006618 <__sfp> 80065da: 6060 str r0, [r4, #4] 80065dc: 4620 mov r0, r4 80065de: f000 f81b bl 8006618 <__sfp> 80065e2: 60a0 str r0, [r4, #8] 80065e4: 4620 mov r0, r4 80065e6: f000 f817 bl 8006618 <__sfp> 80065ea: 2200 movs r2, #0 80065ec: 60e0 str r0, [r4, #12] 80065ee: 2104 movs r1, #4 80065f0: 6860 ldr r0, [r4, #4] 80065f2: f7ff ffa1 bl 8006538 80065f6: 2201 movs r2, #1 80065f8: 2109 movs r1, #9 80065fa: 68a0 ldr r0, [r4, #8] 80065fc: f7ff ff9c bl 8006538 8006600: 2202 movs r2, #2 8006602: 2112 movs r1, #18 8006604: 68e0 ldr r0, [r4, #12] 8006606: f7ff ff97 bl 8006538 800660a: 2301 movs r3, #1 800660c: 61a3 str r3, [r4, #24] 800660e: bd10 pop {r4, pc} 8006610: 08007444 .word 0x08007444 8006614: 08006581 .word 0x08006581 08006618 <__sfp>: 8006618: b5f8 push {r3, r4, r5, r6, r7, lr} 800661a: 4b1b ldr r3, [pc, #108] ; (8006688 <__sfp+0x70>) 800661c: 4607 mov r7, r0 800661e: 681e ldr r6, [r3, #0] 8006620: 69b3 ldr r3, [r6, #24] 8006622: b913 cbnz r3, 800662a <__sfp+0x12> 8006624: 4630 mov r0, r6 8006626: f7ff ffc7 bl 80065b8 <__sinit> 800662a: 3648 adds r6, #72 ; 0x48 800662c: e9d6 3401 ldrd r3, r4, [r6, #4] 8006630: 3b01 subs r3, #1 8006632: d503 bpl.n 800663c <__sfp+0x24> 8006634: 6833 ldr r3, [r6, #0] 8006636: b133 cbz r3, 8006646 <__sfp+0x2e> 8006638: 6836 ldr r6, [r6, #0] 800663a: e7f7 b.n 800662c <__sfp+0x14> 800663c: f9b4 500c ldrsh.w r5, [r4, #12] 8006640: b16d cbz r5, 800665e <__sfp+0x46> 8006642: 3468 adds r4, #104 ; 0x68 8006644: e7f4 b.n 8006630 <__sfp+0x18> 8006646: 2104 movs r1, #4 8006648: 4638 mov r0, r7 800664a: f7ff ff9f bl 800658c <__sfmoreglue> 800664e: 6030 str r0, [r6, #0] 8006650: 2800 cmp r0, #0 8006652: d1f1 bne.n 8006638 <__sfp+0x20> 8006654: 230c movs r3, #12 8006656: 4604 mov r4, r0 8006658: 603b str r3, [r7, #0] 800665a: 4620 mov r0, r4 800665c: bdf8 pop {r3, r4, r5, r6, r7, pc} 800665e: 4b0b ldr r3, [pc, #44] ; (800668c <__sfp+0x74>) 8006660: 6665 str r5, [r4, #100] ; 0x64 8006662: e9c4 5500 strd r5, r5, [r4] 8006666: 60a5 str r5, [r4, #8] 8006668: e9c4 3503 strd r3, r5, [r4, #12] 800666c: e9c4 5505 strd r5, r5, [r4, #20] 8006670: 2208 movs r2, #8 8006672: 4629 mov r1, r5 8006674: f104 005c add.w r0, r4, #92 ; 0x5c 8006678: f7fe fa20 bl 8004abc 800667c: e9c4 550d strd r5, r5, [r4, #52] ; 0x34 8006680: e9c4 5512 strd r5, r5, [r4, #72] ; 0x48 8006684: e7e9 b.n 800665a <__sfp+0x42> 8006686: bf00 nop 8006688: 08007444 .word 0x08007444 800668c: ffff0001 .word 0xffff0001 08006690 <_fwalk_reent>: 8006690: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 8006694: 4680 mov r8, r0 8006696: 4689 mov r9, r1 8006698: 2600 movs r6, #0 800669a: f100 0448 add.w r4, r0, #72 ; 0x48 800669e: b914 cbnz r4, 80066a6 <_fwalk_reent+0x16> 80066a0: 4630 mov r0, r6 80066a2: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 80066a6: e9d4 7501 ldrd r7, r5, [r4, #4] 80066aa: 3f01 subs r7, #1 80066ac: d501 bpl.n 80066b2 <_fwalk_reent+0x22> 80066ae: 6824 ldr r4, [r4, #0] 80066b0: e7f5 b.n 800669e <_fwalk_reent+0xe> 80066b2: 89ab ldrh r3, [r5, #12] 80066b4: 2b01 cmp r3, #1 80066b6: d907 bls.n 80066c8 <_fwalk_reent+0x38> 80066b8: f9b5 300e ldrsh.w r3, [r5, #14] 80066bc: 3301 adds r3, #1 80066be: d003 beq.n 80066c8 <_fwalk_reent+0x38> 80066c0: 4629 mov r1, r5 80066c2: 4640 mov r0, r8 80066c4: 47c8 blx r9 80066c6: 4306 orrs r6, r0 80066c8: 3568 adds r5, #104 ; 0x68 80066ca: e7ee b.n 80066aa <_fwalk_reent+0x1a> 080066cc <_localeconv_r>: 80066cc: 4b04 ldr r3, [pc, #16] ; (80066e0 <_localeconv_r+0x14>) 80066ce: 681b ldr r3, [r3, #0] 80066d0: 6a18 ldr r0, [r3, #32] 80066d2: 4b04 ldr r3, [pc, #16] ; (80066e4 <_localeconv_r+0x18>) 80066d4: 2800 cmp r0, #0 80066d6: bf08 it eq 80066d8: 4618 moveq r0, r3 80066da: 30f0 adds r0, #240 ; 0xf0 80066dc: 4770 bx lr 80066de: bf00 nop 80066e0: 2000000c .word 0x2000000c 80066e4: 20000070 .word 0x20000070 080066e8 <__swhatbuf_r>: 80066e8: b570 push {r4, r5, r6, lr} 80066ea: 460e mov r6, r1 80066ec: f9b1 100e ldrsh.w r1, [r1, #14] 80066f0: b096 sub sp, #88 ; 0x58 80066f2: 2900 cmp r1, #0 80066f4: 4614 mov r4, r2 80066f6: 461d mov r5, r3 80066f8: da07 bge.n 800670a <__swhatbuf_r+0x22> 80066fa: 2300 movs r3, #0 80066fc: 602b str r3, [r5, #0] 80066fe: 89b3 ldrh r3, [r6, #12] 8006700: 061a lsls r2, r3, #24 8006702: d410 bmi.n 8006726 <__swhatbuf_r+0x3e> 8006704: f44f 6380 mov.w r3, #1024 ; 0x400 8006708: e00e b.n 8006728 <__swhatbuf_r+0x40> 800670a: 466a mov r2, sp 800670c: f000 fdb6 bl 800727c <_fstat_r> 8006710: 2800 cmp r0, #0 8006712: dbf2 blt.n 80066fa <__swhatbuf_r+0x12> 8006714: 9a01 ldr r2, [sp, #4] 8006716: f402 4270 and.w r2, r2, #61440 ; 0xf000 800671a: f5a2 5300 sub.w r3, r2, #8192 ; 0x2000 800671e: 425a negs r2, r3 8006720: 415a adcs r2, r3 8006722: 602a str r2, [r5, #0] 8006724: e7ee b.n 8006704 <__swhatbuf_r+0x1c> 8006726: 2340 movs r3, #64 ; 0x40 8006728: 2000 movs r0, #0 800672a: 6023 str r3, [r4, #0] 800672c: b016 add sp, #88 ; 0x58 800672e: bd70 pop {r4, r5, r6, pc} 08006730 <__smakebuf_r>: 8006730: 898b ldrh r3, [r1, #12] 8006732: b573 push {r0, r1, r4, r5, r6, lr} 8006734: 079d lsls r5, r3, #30 8006736: 4606 mov r6, r0 8006738: 460c mov r4, r1 800673a: d507 bpl.n 800674c <__smakebuf_r+0x1c> 800673c: f104 0347 add.w r3, r4, #71 ; 0x47 8006740: 6023 str r3, [r4, #0] 8006742: 6123 str r3, [r4, #16] 8006744: 2301 movs r3, #1 8006746: 6163 str r3, [r4, #20] 8006748: b002 add sp, #8 800674a: bd70 pop {r4, r5, r6, pc} 800674c: ab01 add r3, sp, #4 800674e: 466a mov r2, sp 8006750: f7ff ffca bl 80066e8 <__swhatbuf_r> 8006754: 9900 ldr r1, [sp, #0] 8006756: 4605 mov r5, r0 8006758: 4630 mov r0, r6 800675a: f000 fb81 bl 8006e60 <_malloc_r> 800675e: b948 cbnz r0, 8006774 <__smakebuf_r+0x44> 8006760: f9b4 300c ldrsh.w r3, [r4, #12] 8006764: 059a lsls r2, r3, #22 8006766: d4ef bmi.n 8006748 <__smakebuf_r+0x18> 8006768: f023 0303 bic.w r3, r3, #3 800676c: f043 0302 orr.w r3, r3, #2 8006770: 81a3 strh r3, [r4, #12] 8006772: e7e3 b.n 800673c <__smakebuf_r+0xc> 8006774: 4b0d ldr r3, [pc, #52] ; (80067ac <__smakebuf_r+0x7c>) 8006776: 62b3 str r3, [r6, #40] ; 0x28 8006778: 89a3 ldrh r3, [r4, #12] 800677a: 6020 str r0, [r4, #0] 800677c: f043 0380 orr.w r3, r3, #128 ; 0x80 8006780: 81a3 strh r3, [r4, #12] 8006782: 9b00 ldr r3, [sp, #0] 8006784: 6120 str r0, [r4, #16] 8006786: 6163 str r3, [r4, #20] 8006788: 9b01 ldr r3, [sp, #4] 800678a: b15b cbz r3, 80067a4 <__smakebuf_r+0x74> 800678c: f9b4 100e ldrsh.w r1, [r4, #14] 8006790: 4630 mov r0, r6 8006792: f000 fd85 bl 80072a0 <_isatty_r> 8006796: b128 cbz r0, 80067a4 <__smakebuf_r+0x74> 8006798: 89a3 ldrh r3, [r4, #12] 800679a: f023 0303 bic.w r3, r3, #3 800679e: f043 0301 orr.w r3, r3, #1 80067a2: 81a3 strh r3, [r4, #12] 80067a4: 89a3 ldrh r3, [r4, #12] 80067a6: 431d orrs r5, r3 80067a8: 81a5 strh r5, [r4, #12] 80067aa: e7cd b.n 8006748 <__smakebuf_r+0x18> 80067ac: 08006581 .word 0x08006581 080067b0 : 80067b0: 4b02 ldr r3, [pc, #8] ; (80067bc ) 80067b2: 4601 mov r1, r0 80067b4: 6818 ldr r0, [r3, #0] 80067b6: f000 bb53 b.w 8006e60 <_malloc_r> 80067ba: bf00 nop 80067bc: 2000000c .word 0x2000000c 080067c0 : 80067c0: b510 push {r4, lr} 80067c2: b2c9 uxtb r1, r1 80067c4: 4402 add r2, r0 80067c6: 4290 cmp r0, r2 80067c8: 4603 mov r3, r0 80067ca: d101 bne.n 80067d0 80067cc: 2300 movs r3, #0 80067ce: e003 b.n 80067d8 80067d0: 781c ldrb r4, [r3, #0] 80067d2: 3001 adds r0, #1 80067d4: 428c cmp r4, r1 80067d6: d1f6 bne.n 80067c6 80067d8: 4618 mov r0, r3 80067da: bd10 pop {r4, pc} 080067dc : 80067dc: b510 push {r4, lr} 80067de: 1e43 subs r3, r0, #1 80067e0: 440a add r2, r1 80067e2: 4291 cmp r1, r2 80067e4: d100 bne.n 80067e8 80067e6: bd10 pop {r4, pc} 80067e8: f811 4b01 ldrb.w r4, [r1], #1 80067ec: f803 4f01 strb.w r4, [r3, #1]! 80067f0: e7f7 b.n 80067e2 080067f2 <_Balloc>: 80067f2: b570 push {r4, r5, r6, lr} 80067f4: 6a45 ldr r5, [r0, #36] ; 0x24 80067f6: 4604 mov r4, r0 80067f8: 460e mov r6, r1 80067fa: b93d cbnz r5, 800680c <_Balloc+0x1a> 80067fc: 2010 movs r0, #16 80067fe: f7ff ffd7 bl 80067b0 8006802: 6260 str r0, [r4, #36] ; 0x24 8006804: e9c0 5501 strd r5, r5, [r0, #4] 8006808: 6005 str r5, [r0, #0] 800680a: 60c5 str r5, [r0, #12] 800680c: 6a65 ldr r5, [r4, #36] ; 0x24 800680e: 68eb ldr r3, [r5, #12] 8006810: b183 cbz r3, 8006834 <_Balloc+0x42> 8006812: 6a63 ldr r3, [r4, #36] ; 0x24 8006814: 68db ldr r3, [r3, #12] 8006816: f853 0026 ldr.w r0, [r3, r6, lsl #2] 800681a: b9b8 cbnz r0, 800684c <_Balloc+0x5a> 800681c: 2101 movs r1, #1 800681e: fa01 f506 lsl.w r5, r1, r6 8006822: 1d6a adds r2, r5, #5 8006824: 0092 lsls r2, r2, #2 8006826: 4620 mov r0, r4 8006828: f000 fabf bl 8006daa <_calloc_r> 800682c: b160 cbz r0, 8006848 <_Balloc+0x56> 800682e: e9c0 6501 strd r6, r5, [r0, #4] 8006832: e00e b.n 8006852 <_Balloc+0x60> 8006834: 2221 movs r2, #33 ; 0x21 8006836: 2104 movs r1, #4 8006838: 4620 mov r0, r4 800683a: f000 fab6 bl 8006daa <_calloc_r> 800683e: 6a63 ldr r3, [r4, #36] ; 0x24 8006840: 60e8 str r0, [r5, #12] 8006842: 68db ldr r3, [r3, #12] 8006844: 2b00 cmp r3, #0 8006846: d1e4 bne.n 8006812 <_Balloc+0x20> 8006848: 2000 movs r0, #0 800684a: bd70 pop {r4, r5, r6, pc} 800684c: 6802 ldr r2, [r0, #0] 800684e: f843 2026 str.w r2, [r3, r6, lsl #2] 8006852: 2300 movs r3, #0 8006854: e9c0 3303 strd r3, r3, [r0, #12] 8006858: e7f7 b.n 800684a <_Balloc+0x58> 0800685a <_Bfree>: 800685a: b570 push {r4, r5, r6, lr} 800685c: 6a44 ldr r4, [r0, #36] ; 0x24 800685e: 4606 mov r6, r0 8006860: 460d mov r5, r1 8006862: b93c cbnz r4, 8006874 <_Bfree+0x1a> 8006864: 2010 movs r0, #16 8006866: f7ff ffa3 bl 80067b0 800686a: 6270 str r0, [r6, #36] ; 0x24 800686c: e9c0 4401 strd r4, r4, [r0, #4] 8006870: 6004 str r4, [r0, #0] 8006872: 60c4 str r4, [r0, #12] 8006874: b13d cbz r5, 8006886 <_Bfree+0x2c> 8006876: 6a73 ldr r3, [r6, #36] ; 0x24 8006878: 686a ldr r2, [r5, #4] 800687a: 68db ldr r3, [r3, #12] 800687c: f853 1022 ldr.w r1, [r3, r2, lsl #2] 8006880: 6029 str r1, [r5, #0] 8006882: f843 5022 str.w r5, [r3, r2, lsl #2] 8006886: bd70 pop {r4, r5, r6, pc} 08006888 <__multadd>: 8006888: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 800688c: 461f mov r7, r3 800688e: 4606 mov r6, r0 8006890: 460c mov r4, r1 8006892: 2300 movs r3, #0 8006894: 690d ldr r5, [r1, #16] 8006896: f101 0c14 add.w ip, r1, #20 800689a: f8dc 0000 ldr.w r0, [ip] 800689e: 3301 adds r3, #1 80068a0: b281 uxth r1, r0 80068a2: fb02 7101 mla r1, r2, r1, r7 80068a6: 0c00 lsrs r0, r0, #16 80068a8: 0c0f lsrs r7, r1, #16 80068aa: fb02 7000 mla r0, r2, r0, r7 80068ae: b289 uxth r1, r1 80068b0: eb01 4100 add.w r1, r1, r0, lsl #16 80068b4: 429d cmp r5, r3 80068b6: ea4f 4710 mov.w r7, r0, lsr #16 80068ba: f84c 1b04 str.w r1, [ip], #4 80068be: dcec bgt.n 800689a <__multadd+0x12> 80068c0: b1d7 cbz r7, 80068f8 <__multadd+0x70> 80068c2: 68a3 ldr r3, [r4, #8] 80068c4: 42ab cmp r3, r5 80068c6: dc12 bgt.n 80068ee <__multadd+0x66> 80068c8: 6861 ldr r1, [r4, #4] 80068ca: 4630 mov r0, r6 80068cc: 3101 adds r1, #1 80068ce: f7ff ff90 bl 80067f2 <_Balloc> 80068d2: 4680 mov r8, r0 80068d4: 6922 ldr r2, [r4, #16] 80068d6: f104 010c add.w r1, r4, #12 80068da: 3202 adds r2, #2 80068dc: 0092 lsls r2, r2, #2 80068de: 300c adds r0, #12 80068e0: f7ff ff7c bl 80067dc 80068e4: 4621 mov r1, r4 80068e6: 4630 mov r0, r6 80068e8: f7ff ffb7 bl 800685a <_Bfree> 80068ec: 4644 mov r4, r8 80068ee: eb04 0385 add.w r3, r4, r5, lsl #2 80068f2: 3501 adds r5, #1 80068f4: 615f str r7, [r3, #20] 80068f6: 6125 str r5, [r4, #16] 80068f8: 4620 mov r0, r4 80068fa: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 080068fe <__hi0bits>: 80068fe: 0c02 lsrs r2, r0, #16 8006900: 0412 lsls r2, r2, #16 8006902: 4603 mov r3, r0 8006904: b9b2 cbnz r2, 8006934 <__hi0bits+0x36> 8006906: 0403 lsls r3, r0, #16 8006908: 2010 movs r0, #16 800690a: f013 4f7f tst.w r3, #4278190080 ; 0xff000000 800690e: bf04 itt eq 8006910: 021b lsleq r3, r3, #8 8006912: 3008 addeq r0, #8 8006914: f013 4f70 tst.w r3, #4026531840 ; 0xf0000000 8006918: bf04 itt eq 800691a: 011b lsleq r3, r3, #4 800691c: 3004 addeq r0, #4 800691e: f013 4f40 tst.w r3, #3221225472 ; 0xc0000000 8006922: bf04 itt eq 8006924: 009b lsleq r3, r3, #2 8006926: 3002 addeq r0, #2 8006928: 2b00 cmp r3, #0 800692a: db06 blt.n 800693a <__hi0bits+0x3c> 800692c: 005b lsls r3, r3, #1 800692e: d503 bpl.n 8006938 <__hi0bits+0x3a> 8006930: 3001 adds r0, #1 8006932: 4770 bx lr 8006934: 2000 movs r0, #0 8006936: e7e8 b.n 800690a <__hi0bits+0xc> 8006938: 2020 movs r0, #32 800693a: 4770 bx lr 0800693c <__lo0bits>: 800693c: 6803 ldr r3, [r0, #0] 800693e: 4601 mov r1, r0 8006940: f013 0207 ands.w r2, r3, #7 8006944: d00b beq.n 800695e <__lo0bits+0x22> 8006946: 07da lsls r2, r3, #31 8006948: d423 bmi.n 8006992 <__lo0bits+0x56> 800694a: 0798 lsls r0, r3, #30 800694c: bf49 itett mi 800694e: 085b lsrmi r3, r3, #1 8006950: 089b lsrpl r3, r3, #2 8006952: 2001 movmi r0, #1 8006954: 600b strmi r3, [r1, #0] 8006956: bf5c itt pl 8006958: 600b strpl r3, [r1, #0] 800695a: 2002 movpl r0, #2 800695c: 4770 bx lr 800695e: b298 uxth r0, r3 8006960: b9a8 cbnz r0, 800698e <__lo0bits+0x52> 8006962: 2010 movs r0, #16 8006964: 0c1b lsrs r3, r3, #16 8006966: f013 0fff tst.w r3, #255 ; 0xff 800696a: bf04 itt eq 800696c: 0a1b lsreq r3, r3, #8 800696e: 3008 addeq r0, #8 8006970: 071a lsls r2, r3, #28 8006972: bf04 itt eq 8006974: 091b lsreq r3, r3, #4 8006976: 3004 addeq r0, #4 8006978: 079a lsls r2, r3, #30 800697a: bf04 itt eq 800697c: 089b lsreq r3, r3, #2 800697e: 3002 addeq r0, #2 8006980: 07da lsls r2, r3, #31 8006982: d402 bmi.n 800698a <__lo0bits+0x4e> 8006984: 085b lsrs r3, r3, #1 8006986: d006 beq.n 8006996 <__lo0bits+0x5a> 8006988: 3001 adds r0, #1 800698a: 600b str r3, [r1, #0] 800698c: 4770 bx lr 800698e: 4610 mov r0, r2 8006990: e7e9 b.n 8006966 <__lo0bits+0x2a> 8006992: 2000 movs r0, #0 8006994: 4770 bx lr 8006996: 2020 movs r0, #32 8006998: 4770 bx lr 0800699a <__i2b>: 800699a: b510 push {r4, lr} 800699c: 460c mov r4, r1 800699e: 2101 movs r1, #1 80069a0: f7ff ff27 bl 80067f2 <_Balloc> 80069a4: 2201 movs r2, #1 80069a6: 6144 str r4, [r0, #20] 80069a8: 6102 str r2, [r0, #16] 80069aa: bd10 pop {r4, pc} 080069ac <__multiply>: 80069ac: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} 80069b0: 4614 mov r4, r2 80069b2: 690a ldr r2, [r1, #16] 80069b4: 6923 ldr r3, [r4, #16] 80069b6: 4688 mov r8, r1 80069b8: 429a cmp r2, r3 80069ba: bfbe ittt lt 80069bc: 460b movlt r3, r1 80069be: 46a0 movlt r8, r4 80069c0: 461c movlt r4, r3 80069c2: f8d8 7010 ldr.w r7, [r8, #16] 80069c6: f8d4 9010 ldr.w r9, [r4, #16] 80069ca: f8d8 3008 ldr.w r3, [r8, #8] 80069ce: f8d8 1004 ldr.w r1, [r8, #4] 80069d2: eb07 0609 add.w r6, r7, r9 80069d6: 42b3 cmp r3, r6 80069d8: bfb8 it lt 80069da: 3101 addlt r1, #1 80069dc: f7ff ff09 bl 80067f2 <_Balloc> 80069e0: f100 0514 add.w r5, r0, #20 80069e4: 462b mov r3, r5 80069e6: 2200 movs r2, #0 80069e8: eb05 0e86 add.w lr, r5, r6, lsl #2 80069ec: 4573 cmp r3, lr 80069ee: d316 bcc.n 8006a1e <__multiply+0x72> 80069f0: f104 0214 add.w r2, r4, #20 80069f4: f108 0114 add.w r1, r8, #20 80069f8: eb02 0389 add.w r3, r2, r9, lsl #2 80069fc: eb01 0787 add.w r7, r1, r7, lsl #2 8006a00: 9300 str r3, [sp, #0] 8006a02: 9b00 ldr r3, [sp, #0] 8006a04: 9201 str r2, [sp, #4] 8006a06: 4293 cmp r3, r2 8006a08: d80c bhi.n 8006a24 <__multiply+0x78> 8006a0a: 2e00 cmp r6, #0 8006a0c: dd03 ble.n 8006a16 <__multiply+0x6a> 8006a0e: f85e 3d04 ldr.w r3, [lr, #-4]! 8006a12: 2b00 cmp r3, #0 8006a14: d05d beq.n 8006ad2 <__multiply+0x126> 8006a16: 6106 str r6, [r0, #16] 8006a18: b003 add sp, #12 8006a1a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8006a1e: f843 2b04 str.w r2, [r3], #4 8006a22: e7e3 b.n 80069ec <__multiply+0x40> 8006a24: f8b2 b000 ldrh.w fp, [r2] 8006a28: f1bb 0f00 cmp.w fp, #0 8006a2c: d023 beq.n 8006a76 <__multiply+0xca> 8006a2e: 4689 mov r9, r1 8006a30: 46ac mov ip, r5 8006a32: f04f 0800 mov.w r8, #0 8006a36: f859 4b04 ldr.w r4, [r9], #4 8006a3a: f8dc a000 ldr.w sl, [ip] 8006a3e: b2a3 uxth r3, r4 8006a40: fa1f fa8a uxth.w sl, sl 8006a44: fb0b a303 mla r3, fp, r3, sl 8006a48: ea4f 4a14 mov.w sl, r4, lsr #16 8006a4c: f8dc 4000 ldr.w r4, [ip] 8006a50: 4443 add r3, r8 8006a52: ea4f 4814 mov.w r8, r4, lsr #16 8006a56: fb0b 840a mla r4, fp, sl, r8 8006a5a: 46e2 mov sl, ip 8006a5c: eb04 4413 add.w r4, r4, r3, lsr #16 8006a60: b29b uxth r3, r3 8006a62: ea43 4304 orr.w r3, r3, r4, lsl #16 8006a66: 454f cmp r7, r9 8006a68: ea4f 4814 mov.w r8, r4, lsr #16 8006a6c: f84a 3b04 str.w r3, [sl], #4 8006a70: d82b bhi.n 8006aca <__multiply+0x11e> 8006a72: f8cc 8004 str.w r8, [ip, #4] 8006a76: 9b01 ldr r3, [sp, #4] 8006a78: 3204 adds r2, #4 8006a7a: f8b3 a002 ldrh.w sl, [r3, #2] 8006a7e: f1ba 0f00 cmp.w sl, #0 8006a82: d020 beq.n 8006ac6 <__multiply+0x11a> 8006a84: 4689 mov r9, r1 8006a86: 46a8 mov r8, r5 8006a88: f04f 0b00 mov.w fp, #0 8006a8c: 682b ldr r3, [r5, #0] 8006a8e: f8b9 c000 ldrh.w ip, [r9] 8006a92: f8b8 4002 ldrh.w r4, [r8, #2] 8006a96: b29b uxth r3, r3 8006a98: fb0a 440c mla r4, sl, ip, r4 8006a9c: 46c4 mov ip, r8 8006a9e: 445c add r4, fp 8006aa0: ea43 4304 orr.w r3, r3, r4, lsl #16 8006aa4: f84c 3b04 str.w r3, [ip], #4 8006aa8: f859 3b04 ldr.w r3, [r9], #4 8006aac: f8b8 b004 ldrh.w fp, [r8, #4] 8006ab0: 0c1b lsrs r3, r3, #16 8006ab2: fb0a b303 mla r3, sl, r3, fp 8006ab6: 454f cmp r7, r9 8006ab8: eb03 4314 add.w r3, r3, r4, lsr #16 8006abc: ea4f 4b13 mov.w fp, r3, lsr #16 8006ac0: d805 bhi.n 8006ace <__multiply+0x122> 8006ac2: f8c8 3004 str.w r3, [r8, #4] 8006ac6: 3504 adds r5, #4 8006ac8: e79b b.n 8006a02 <__multiply+0x56> 8006aca: 46d4 mov ip, sl 8006acc: e7b3 b.n 8006a36 <__multiply+0x8a> 8006ace: 46e0 mov r8, ip 8006ad0: e7dd b.n 8006a8e <__multiply+0xe2> 8006ad2: 3e01 subs r6, #1 8006ad4: e799 b.n 8006a0a <__multiply+0x5e> ... 08006ad8 <__pow5mult>: 8006ad8: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 8006adc: 4615 mov r5, r2 8006ade: f012 0203 ands.w r2, r2, #3 8006ae2: 4606 mov r6, r0 8006ae4: 460f mov r7, r1 8006ae6: d007 beq.n 8006af8 <__pow5mult+0x20> 8006ae8: 4c21 ldr r4, [pc, #132] ; (8006b70 <__pow5mult+0x98>) 8006aea: 3a01 subs r2, #1 8006aec: 2300 movs r3, #0 8006aee: f854 2022 ldr.w r2, [r4, r2, lsl #2] 8006af2: f7ff fec9 bl 8006888 <__multadd> 8006af6: 4607 mov r7, r0 8006af8: 10ad asrs r5, r5, #2 8006afa: d035 beq.n 8006b68 <__pow5mult+0x90> 8006afc: 6a74 ldr r4, [r6, #36] ; 0x24 8006afe: b93c cbnz r4, 8006b10 <__pow5mult+0x38> 8006b00: 2010 movs r0, #16 8006b02: f7ff fe55 bl 80067b0 8006b06: 6270 str r0, [r6, #36] ; 0x24 8006b08: e9c0 4401 strd r4, r4, [r0, #4] 8006b0c: 6004 str r4, [r0, #0] 8006b0e: 60c4 str r4, [r0, #12] 8006b10: f8d6 8024 ldr.w r8, [r6, #36] ; 0x24 8006b14: f8d8 4008 ldr.w r4, [r8, #8] 8006b18: b94c cbnz r4, 8006b2e <__pow5mult+0x56> 8006b1a: f240 2171 movw r1, #625 ; 0x271 8006b1e: 4630 mov r0, r6 8006b20: f7ff ff3b bl 800699a <__i2b> 8006b24: 2300 movs r3, #0 8006b26: 4604 mov r4, r0 8006b28: f8c8 0008 str.w r0, [r8, #8] 8006b2c: 6003 str r3, [r0, #0] 8006b2e: f04f 0800 mov.w r8, #0 8006b32: 07eb lsls r3, r5, #31 8006b34: d50a bpl.n 8006b4c <__pow5mult+0x74> 8006b36: 4639 mov r1, r7 8006b38: 4622 mov r2, r4 8006b3a: 4630 mov r0, r6 8006b3c: f7ff ff36 bl 80069ac <__multiply> 8006b40: 4681 mov r9, r0 8006b42: 4639 mov r1, r7 8006b44: 4630 mov r0, r6 8006b46: f7ff fe88 bl 800685a <_Bfree> 8006b4a: 464f mov r7, r9 8006b4c: 106d asrs r5, r5, #1 8006b4e: d00b beq.n 8006b68 <__pow5mult+0x90> 8006b50: 6820 ldr r0, [r4, #0] 8006b52: b938 cbnz r0, 8006b64 <__pow5mult+0x8c> 8006b54: 4622 mov r2, r4 8006b56: 4621 mov r1, r4 8006b58: 4630 mov r0, r6 8006b5a: f7ff ff27 bl 80069ac <__multiply> 8006b5e: 6020 str r0, [r4, #0] 8006b60: f8c0 8000 str.w r8, [r0] 8006b64: 4604 mov r4, r0 8006b66: e7e4 b.n 8006b32 <__pow5mult+0x5a> 8006b68: 4638 mov r0, r7 8006b6a: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 8006b6e: bf00 nop 8006b70: 080075e0 .word 0x080075e0 08006b74 <__lshift>: 8006b74: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8006b78: 460c mov r4, r1 8006b7a: 4607 mov r7, r0 8006b7c: 4616 mov r6, r2 8006b7e: 6923 ldr r3, [r4, #16] 8006b80: ea4f 1a62 mov.w sl, r2, asr #5 8006b84: eb0a 0903 add.w r9, sl, r3 8006b88: 6849 ldr r1, [r1, #4] 8006b8a: 68a3 ldr r3, [r4, #8] 8006b8c: f109 0501 add.w r5, r9, #1 8006b90: 42ab cmp r3, r5 8006b92: db32 blt.n 8006bfa <__lshift+0x86> 8006b94: 4638 mov r0, r7 8006b96: f7ff fe2c bl 80067f2 <_Balloc> 8006b9a: 2300 movs r3, #0 8006b9c: 4680 mov r8, r0 8006b9e: 461a mov r2, r3 8006ba0: f100 0114 add.w r1, r0, #20 8006ba4: 4553 cmp r3, sl 8006ba6: db2b blt.n 8006c00 <__lshift+0x8c> 8006ba8: 6920 ldr r0, [r4, #16] 8006baa: ea2a 7aea bic.w sl, sl, sl, asr #31 8006bae: f104 0314 add.w r3, r4, #20 8006bb2: f016 021f ands.w r2, r6, #31 8006bb6: eb01 018a add.w r1, r1, sl, lsl #2 8006bba: eb03 0c80 add.w ip, r3, r0, lsl #2 8006bbe: d025 beq.n 8006c0c <__lshift+0x98> 8006bc0: 2000 movs r0, #0 8006bc2: f1c2 0e20 rsb lr, r2, #32 8006bc6: 468a mov sl, r1 8006bc8: 681e ldr r6, [r3, #0] 8006bca: 4096 lsls r6, r2 8006bcc: 4330 orrs r0, r6 8006bce: f84a 0b04 str.w r0, [sl], #4 8006bd2: f853 0b04 ldr.w r0, [r3], #4 8006bd6: 459c cmp ip, r3 8006bd8: fa20 f00e lsr.w r0, r0, lr 8006bdc: d814 bhi.n 8006c08 <__lshift+0x94> 8006bde: 6048 str r0, [r1, #4] 8006be0: b108 cbz r0, 8006be6 <__lshift+0x72> 8006be2: f109 0502 add.w r5, r9, #2 8006be6: 3d01 subs r5, #1 8006be8: 4638 mov r0, r7 8006bea: f8c8 5010 str.w r5, [r8, #16] 8006bee: 4621 mov r1, r4 8006bf0: f7ff fe33 bl 800685a <_Bfree> 8006bf4: 4640 mov r0, r8 8006bf6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8006bfa: 3101 adds r1, #1 8006bfc: 005b lsls r3, r3, #1 8006bfe: e7c7 b.n 8006b90 <__lshift+0x1c> 8006c00: f841 2023 str.w r2, [r1, r3, lsl #2] 8006c04: 3301 adds r3, #1 8006c06: e7cd b.n 8006ba4 <__lshift+0x30> 8006c08: 4651 mov r1, sl 8006c0a: e7dc b.n 8006bc6 <__lshift+0x52> 8006c0c: 3904 subs r1, #4 8006c0e: f853 2b04 ldr.w r2, [r3], #4 8006c12: 459c cmp ip, r3 8006c14: f841 2f04 str.w r2, [r1, #4]! 8006c18: d8f9 bhi.n 8006c0e <__lshift+0x9a> 8006c1a: e7e4 b.n 8006be6 <__lshift+0x72> 08006c1c <__mcmp>: 8006c1c: 6903 ldr r3, [r0, #16] 8006c1e: 690a ldr r2, [r1, #16] 8006c20: b530 push {r4, r5, lr} 8006c22: 1a9b subs r3, r3, r2 8006c24: d10c bne.n 8006c40 <__mcmp+0x24> 8006c26: 0092 lsls r2, r2, #2 8006c28: 3014 adds r0, #20 8006c2a: 3114 adds r1, #20 8006c2c: 1884 adds r4, r0, r2 8006c2e: 4411 add r1, r2 8006c30: f854 5d04 ldr.w r5, [r4, #-4]! 8006c34: f851 2d04 ldr.w r2, [r1, #-4]! 8006c38: 4295 cmp r5, r2 8006c3a: d003 beq.n 8006c44 <__mcmp+0x28> 8006c3c: d305 bcc.n 8006c4a <__mcmp+0x2e> 8006c3e: 2301 movs r3, #1 8006c40: 4618 mov r0, r3 8006c42: bd30 pop {r4, r5, pc} 8006c44: 42a0 cmp r0, r4 8006c46: d3f3 bcc.n 8006c30 <__mcmp+0x14> 8006c48: e7fa b.n 8006c40 <__mcmp+0x24> 8006c4a: f04f 33ff mov.w r3, #4294967295 8006c4e: e7f7 b.n 8006c40 <__mcmp+0x24> 08006c50 <__mdiff>: 8006c50: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8006c54: 460d mov r5, r1 8006c56: 4607 mov r7, r0 8006c58: 4611 mov r1, r2 8006c5a: 4628 mov r0, r5 8006c5c: 4614 mov r4, r2 8006c5e: f7ff ffdd bl 8006c1c <__mcmp> 8006c62: 1e06 subs r6, r0, #0 8006c64: d108 bne.n 8006c78 <__mdiff+0x28> 8006c66: 4631 mov r1, r6 8006c68: 4638 mov r0, r7 8006c6a: f7ff fdc2 bl 80067f2 <_Balloc> 8006c6e: 2301 movs r3, #1 8006c70: e9c0 3604 strd r3, r6, [r0, #16] 8006c74: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8006c78: bfa4 itt ge 8006c7a: 4623 movge r3, r4 8006c7c: 462c movge r4, r5 8006c7e: 4638 mov r0, r7 8006c80: 6861 ldr r1, [r4, #4] 8006c82: bfa6 itte ge 8006c84: 461d movge r5, r3 8006c86: 2600 movge r6, #0 8006c88: 2601 movlt r6, #1 8006c8a: f7ff fdb2 bl 80067f2 <_Balloc> 8006c8e: f04f 0e00 mov.w lr, #0 8006c92: 60c6 str r6, [r0, #12] 8006c94: 692b ldr r3, [r5, #16] 8006c96: 6926 ldr r6, [r4, #16] 8006c98: f104 0214 add.w r2, r4, #20 8006c9c: f105 0914 add.w r9, r5, #20 8006ca0: eb02 0786 add.w r7, r2, r6, lsl #2 8006ca4: eb09 0883 add.w r8, r9, r3, lsl #2 8006ca8: f100 0114 add.w r1, r0, #20 8006cac: f852 ab04 ldr.w sl, [r2], #4 8006cb0: f859 5b04 ldr.w r5, [r9], #4 8006cb4: fa1f f38a uxth.w r3, sl 8006cb8: 4473 add r3, lr 8006cba: b2ac uxth r4, r5 8006cbc: 1b1b subs r3, r3, r4 8006cbe: 0c2c lsrs r4, r5, #16 8006cc0: ebc4 441a rsb r4, r4, sl, lsr #16 8006cc4: eb04 4423 add.w r4, r4, r3, asr #16 8006cc8: b29b uxth r3, r3 8006cca: ea4f 4e24 mov.w lr, r4, asr #16 8006cce: 45c8 cmp r8, r9 8006cd0: ea43 4404 orr.w r4, r3, r4, lsl #16 8006cd4: 4694 mov ip, r2 8006cd6: f841 4b04 str.w r4, [r1], #4 8006cda: d8e7 bhi.n 8006cac <__mdiff+0x5c> 8006cdc: 45bc cmp ip, r7 8006cde: d304 bcc.n 8006cea <__mdiff+0x9a> 8006ce0: f851 3d04 ldr.w r3, [r1, #-4]! 8006ce4: b183 cbz r3, 8006d08 <__mdiff+0xb8> 8006ce6: 6106 str r6, [r0, #16] 8006ce8: e7c4 b.n 8006c74 <__mdiff+0x24> 8006cea: f85c 4b04 ldr.w r4, [ip], #4 8006cee: b2a2 uxth r2, r4 8006cf0: 4472 add r2, lr 8006cf2: 1413 asrs r3, r2, #16 8006cf4: eb03 4314 add.w r3, r3, r4, lsr #16 8006cf8: b292 uxth r2, r2 8006cfa: ea42 4203 orr.w r2, r2, r3, lsl #16 8006cfe: ea4f 4e23 mov.w lr, r3, asr #16 8006d02: f841 2b04 str.w r2, [r1], #4 8006d06: e7e9 b.n 8006cdc <__mdiff+0x8c> 8006d08: 3e01 subs r6, #1 8006d0a: e7e9 b.n 8006ce0 <__mdiff+0x90> 08006d0c <__d2b>: 8006d0c: e92d 41f3 stmdb sp!, {r0, r1, r4, r5, r6, r7, r8, lr} 8006d10: 461c mov r4, r3 8006d12: e9dd 6508 ldrd r6, r5, [sp, #32] 8006d16: 2101 movs r1, #1 8006d18: 4690 mov r8, r2 8006d1a: f7ff fd6a bl 80067f2 <_Balloc> 8006d1e: f3c4 0213 ubfx r2, r4, #0, #20 8006d22: f3c4 540a ubfx r4, r4, #20, #11 8006d26: 4607 mov r7, r0 8006d28: bb34 cbnz r4, 8006d78 <__d2b+0x6c> 8006d2a: 9201 str r2, [sp, #4] 8006d2c: f1b8 0200 subs.w r2, r8, #0 8006d30: d027 beq.n 8006d82 <__d2b+0x76> 8006d32: a802 add r0, sp, #8 8006d34: f840 2d08 str.w r2, [r0, #-8]! 8006d38: f7ff fe00 bl 800693c <__lo0bits> 8006d3c: 9900 ldr r1, [sp, #0] 8006d3e: b1f0 cbz r0, 8006d7e <__d2b+0x72> 8006d40: 9a01 ldr r2, [sp, #4] 8006d42: f1c0 0320 rsb r3, r0, #32 8006d46: fa02 f303 lsl.w r3, r2, r3 8006d4a: 430b orrs r3, r1 8006d4c: 40c2 lsrs r2, r0 8006d4e: 617b str r3, [r7, #20] 8006d50: 9201 str r2, [sp, #4] 8006d52: 9b01 ldr r3, [sp, #4] 8006d54: 2b00 cmp r3, #0 8006d56: bf14 ite ne 8006d58: 2102 movne r1, #2 8006d5a: 2101 moveq r1, #1 8006d5c: 61bb str r3, [r7, #24] 8006d5e: 6139 str r1, [r7, #16] 8006d60: b1c4 cbz r4, 8006d94 <__d2b+0x88> 8006d62: f2a4 4433 subw r4, r4, #1075 ; 0x433 8006d66: 4404 add r4, r0 8006d68: 6034 str r4, [r6, #0] 8006d6a: f1c0 0035 rsb r0, r0, #53 ; 0x35 8006d6e: 6028 str r0, [r5, #0] 8006d70: 4638 mov r0, r7 8006d72: b002 add sp, #8 8006d74: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8006d78: f442 1280 orr.w r2, r2, #1048576 ; 0x100000 8006d7c: e7d5 b.n 8006d2a <__d2b+0x1e> 8006d7e: 6179 str r1, [r7, #20] 8006d80: e7e7 b.n 8006d52 <__d2b+0x46> 8006d82: a801 add r0, sp, #4 8006d84: f7ff fdda bl 800693c <__lo0bits> 8006d88: 2101 movs r1, #1 8006d8a: 9b01 ldr r3, [sp, #4] 8006d8c: 6139 str r1, [r7, #16] 8006d8e: 617b str r3, [r7, #20] 8006d90: 3020 adds r0, #32 8006d92: e7e5 b.n 8006d60 <__d2b+0x54> 8006d94: f2a0 4032 subw r0, r0, #1074 ; 0x432 8006d98: eb07 0381 add.w r3, r7, r1, lsl #2 8006d9c: 6030 str r0, [r6, #0] 8006d9e: 6918 ldr r0, [r3, #16] 8006da0: f7ff fdad bl 80068fe <__hi0bits> 8006da4: ebc0 1041 rsb r0, r0, r1, lsl #5 8006da8: e7e1 b.n 8006d6e <__d2b+0x62> 08006daa <_calloc_r>: 8006daa: b538 push {r3, r4, r5, lr} 8006dac: fb02 f401 mul.w r4, r2, r1 8006db0: 4621 mov r1, r4 8006db2: f000 f855 bl 8006e60 <_malloc_r> 8006db6: 4605 mov r5, r0 8006db8: b118 cbz r0, 8006dc2 <_calloc_r+0x18> 8006dba: 4622 mov r2, r4 8006dbc: 2100 movs r1, #0 8006dbe: f7fd fe7d bl 8004abc 8006dc2: 4628 mov r0, r5 8006dc4: bd38 pop {r3, r4, r5, pc} ... 08006dc8 <_free_r>: 8006dc8: b538 push {r3, r4, r5, lr} 8006dca: 4605 mov r5, r0 8006dcc: 2900 cmp r1, #0 8006dce: d043 beq.n 8006e58 <_free_r+0x90> 8006dd0: f851 3c04 ldr.w r3, [r1, #-4] 8006dd4: 1f0c subs r4, r1, #4 8006dd6: 2b00 cmp r3, #0 8006dd8: bfb8 it lt 8006dda: 18e4 addlt r4, r4, r3 8006ddc: f000 fa94 bl 8007308 <__malloc_lock> 8006de0: 4a1e ldr r2, [pc, #120] ; (8006e5c <_free_r+0x94>) 8006de2: 6813 ldr r3, [r2, #0] 8006de4: 4610 mov r0, r2 8006de6: b933 cbnz r3, 8006df6 <_free_r+0x2e> 8006de8: 6063 str r3, [r4, #4] 8006dea: 6014 str r4, [r2, #0] 8006dec: 4628 mov r0, r5 8006dee: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 8006df2: f000 ba8a b.w 800730a <__malloc_unlock> 8006df6: 42a3 cmp r3, r4 8006df8: d90b bls.n 8006e12 <_free_r+0x4a> 8006dfa: 6821 ldr r1, [r4, #0] 8006dfc: 1862 adds r2, r4, r1 8006dfe: 4293 cmp r3, r2 8006e00: bf01 itttt eq 8006e02: 681a ldreq r2, [r3, #0] 8006e04: 685b ldreq r3, [r3, #4] 8006e06: 1852 addeq r2, r2, r1 8006e08: 6022 streq r2, [r4, #0] 8006e0a: 6063 str r3, [r4, #4] 8006e0c: 6004 str r4, [r0, #0] 8006e0e: e7ed b.n 8006dec <_free_r+0x24> 8006e10: 4613 mov r3, r2 8006e12: 685a ldr r2, [r3, #4] 8006e14: b10a cbz r2, 8006e1a <_free_r+0x52> 8006e16: 42a2 cmp r2, r4 8006e18: d9fa bls.n 8006e10 <_free_r+0x48> 8006e1a: 6819 ldr r1, [r3, #0] 8006e1c: 1858 adds r0, r3, r1 8006e1e: 42a0 cmp r0, r4 8006e20: d10b bne.n 8006e3a <_free_r+0x72> 8006e22: 6820 ldr r0, [r4, #0] 8006e24: 4401 add r1, r0 8006e26: 1858 adds r0, r3, r1 8006e28: 4282 cmp r2, r0 8006e2a: 6019 str r1, [r3, #0] 8006e2c: d1de bne.n 8006dec <_free_r+0x24> 8006e2e: 6810 ldr r0, [r2, #0] 8006e30: 6852 ldr r2, [r2, #4] 8006e32: 4401 add r1, r0 8006e34: 6019 str r1, [r3, #0] 8006e36: 605a str r2, [r3, #4] 8006e38: e7d8 b.n 8006dec <_free_r+0x24> 8006e3a: d902 bls.n 8006e42 <_free_r+0x7a> 8006e3c: 230c movs r3, #12 8006e3e: 602b str r3, [r5, #0] 8006e40: e7d4 b.n 8006dec <_free_r+0x24> 8006e42: 6820 ldr r0, [r4, #0] 8006e44: 1821 adds r1, r4, r0 8006e46: 428a cmp r2, r1 8006e48: bf01 itttt eq 8006e4a: 6811 ldreq r1, [r2, #0] 8006e4c: 6852 ldreq r2, [r2, #4] 8006e4e: 1809 addeq r1, r1, r0 8006e50: 6021 streq r1, [r4, #0] 8006e52: 6062 str r2, [r4, #4] 8006e54: 605c str r4, [r3, #4] 8006e56: e7c9 b.n 8006dec <_free_r+0x24> 8006e58: bd38 pop {r3, r4, r5, pc} 8006e5a: bf00 nop 8006e5c: 2000020c .word 0x2000020c 08006e60 <_malloc_r>: 8006e60: b570 push {r4, r5, r6, lr} 8006e62: 1ccd adds r5, r1, #3 8006e64: f025 0503 bic.w r5, r5, #3 8006e68: 3508 adds r5, #8 8006e6a: 2d0c cmp r5, #12 8006e6c: bf38 it cc 8006e6e: 250c movcc r5, #12 8006e70: 2d00 cmp r5, #0 8006e72: 4606 mov r6, r0 8006e74: db01 blt.n 8006e7a <_malloc_r+0x1a> 8006e76: 42a9 cmp r1, r5 8006e78: d903 bls.n 8006e82 <_malloc_r+0x22> 8006e7a: 230c movs r3, #12 8006e7c: 6033 str r3, [r6, #0] 8006e7e: 2000 movs r0, #0 8006e80: bd70 pop {r4, r5, r6, pc} 8006e82: f000 fa41 bl 8007308 <__malloc_lock> 8006e86: 4a21 ldr r2, [pc, #132] ; (8006f0c <_malloc_r+0xac>) 8006e88: 6814 ldr r4, [r2, #0] 8006e8a: 4621 mov r1, r4 8006e8c: b991 cbnz r1, 8006eb4 <_malloc_r+0x54> 8006e8e: 4c20 ldr r4, [pc, #128] ; (8006f10 <_malloc_r+0xb0>) 8006e90: 6823 ldr r3, [r4, #0] 8006e92: b91b cbnz r3, 8006e9c <_malloc_r+0x3c> 8006e94: 4630 mov r0, r6 8006e96: f000 f97b bl 8007190 <_sbrk_r> 8006e9a: 6020 str r0, [r4, #0] 8006e9c: 4629 mov r1, r5 8006e9e: 4630 mov r0, r6 8006ea0: f000 f976 bl 8007190 <_sbrk_r> 8006ea4: 1c43 adds r3, r0, #1 8006ea6: d124 bne.n 8006ef2 <_malloc_r+0x92> 8006ea8: 230c movs r3, #12 8006eaa: 4630 mov r0, r6 8006eac: 6033 str r3, [r6, #0] 8006eae: f000 fa2c bl 800730a <__malloc_unlock> 8006eb2: e7e4 b.n 8006e7e <_malloc_r+0x1e> 8006eb4: 680b ldr r3, [r1, #0] 8006eb6: 1b5b subs r3, r3, r5 8006eb8: d418 bmi.n 8006eec <_malloc_r+0x8c> 8006eba: 2b0b cmp r3, #11 8006ebc: d90f bls.n 8006ede <_malloc_r+0x7e> 8006ebe: 600b str r3, [r1, #0] 8006ec0: 18cc adds r4, r1, r3 8006ec2: 50cd str r5, [r1, r3] 8006ec4: 4630 mov r0, r6 8006ec6: f000 fa20 bl 800730a <__malloc_unlock> 8006eca: f104 000b add.w r0, r4, #11 8006ece: 1d23 adds r3, r4, #4 8006ed0: f020 0007 bic.w r0, r0, #7 8006ed4: 1ac3 subs r3, r0, r3 8006ed6: d0d3 beq.n 8006e80 <_malloc_r+0x20> 8006ed8: 425a negs r2, r3 8006eda: 50e2 str r2, [r4, r3] 8006edc: e7d0 b.n 8006e80 <_malloc_r+0x20> 8006ede: 684b ldr r3, [r1, #4] 8006ee0: 428c cmp r4, r1 8006ee2: bf16 itet ne 8006ee4: 6063 strne r3, [r4, #4] 8006ee6: 6013 streq r3, [r2, #0] 8006ee8: 460c movne r4, r1 8006eea: e7eb b.n 8006ec4 <_malloc_r+0x64> 8006eec: 460c mov r4, r1 8006eee: 6849 ldr r1, [r1, #4] 8006ef0: e7cc b.n 8006e8c <_malloc_r+0x2c> 8006ef2: 1cc4 adds r4, r0, #3 8006ef4: f024 0403 bic.w r4, r4, #3 8006ef8: 42a0 cmp r0, r4 8006efa: d005 beq.n 8006f08 <_malloc_r+0xa8> 8006efc: 1a21 subs r1, r4, r0 8006efe: 4630 mov r0, r6 8006f00: f000 f946 bl 8007190 <_sbrk_r> 8006f04: 3001 adds r0, #1 8006f06: d0cf beq.n 8006ea8 <_malloc_r+0x48> 8006f08: 6025 str r5, [r4, #0] 8006f0a: e7db b.n 8006ec4 <_malloc_r+0x64> 8006f0c: 2000020c .word 0x2000020c 8006f10: 20000210 .word 0x20000210 08006f14 <__sfputc_r>: 8006f14: 6893 ldr r3, [r2, #8] 8006f16: b410 push {r4} 8006f18: 3b01 subs r3, #1 8006f1a: 2b00 cmp r3, #0 8006f1c: 6093 str r3, [r2, #8] 8006f1e: da07 bge.n 8006f30 <__sfputc_r+0x1c> 8006f20: 6994 ldr r4, [r2, #24] 8006f22: 42a3 cmp r3, r4 8006f24: db01 blt.n 8006f2a <__sfputc_r+0x16> 8006f26: 290a cmp r1, #10 8006f28: d102 bne.n 8006f30 <__sfputc_r+0x1c> 8006f2a: bc10 pop {r4} 8006f2c: f7fe bb50 b.w 80055d0 <__swbuf_r> 8006f30: 6813 ldr r3, [r2, #0] 8006f32: 1c58 adds r0, r3, #1 8006f34: 6010 str r0, [r2, #0] 8006f36: 7019 strb r1, [r3, #0] 8006f38: 4608 mov r0, r1 8006f3a: bc10 pop {r4} 8006f3c: 4770 bx lr 08006f3e <__sfputs_r>: 8006f3e: b5f8 push {r3, r4, r5, r6, r7, lr} 8006f40: 4606 mov r6, r0 8006f42: 460f mov r7, r1 8006f44: 4614 mov r4, r2 8006f46: 18d5 adds r5, r2, r3 8006f48: 42ac cmp r4, r5 8006f4a: d101 bne.n 8006f50 <__sfputs_r+0x12> 8006f4c: 2000 movs r0, #0 8006f4e: e007 b.n 8006f60 <__sfputs_r+0x22> 8006f50: 463a mov r2, r7 8006f52: f814 1b01 ldrb.w r1, [r4], #1 8006f56: 4630 mov r0, r6 8006f58: f7ff ffdc bl 8006f14 <__sfputc_r> 8006f5c: 1c43 adds r3, r0, #1 8006f5e: d1f3 bne.n 8006f48 <__sfputs_r+0xa> 8006f60: bdf8 pop {r3, r4, r5, r6, r7, pc} ... 08006f64 <_vfiprintf_r>: 8006f64: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8006f68: 460c mov r4, r1 8006f6a: b09d sub sp, #116 ; 0x74 8006f6c: 4617 mov r7, r2 8006f6e: 461d mov r5, r3 8006f70: 4606 mov r6, r0 8006f72: b118 cbz r0, 8006f7c <_vfiprintf_r+0x18> 8006f74: 6983 ldr r3, [r0, #24] 8006f76: b90b cbnz r3, 8006f7c <_vfiprintf_r+0x18> 8006f78: f7ff fb1e bl 80065b8 <__sinit> 8006f7c: 4b7c ldr r3, [pc, #496] ; (8007170 <_vfiprintf_r+0x20c>) 8006f7e: 429c cmp r4, r3 8006f80: d158 bne.n 8007034 <_vfiprintf_r+0xd0> 8006f82: 6874 ldr r4, [r6, #4] 8006f84: 89a3 ldrh r3, [r4, #12] 8006f86: 0718 lsls r0, r3, #28 8006f88: d55e bpl.n 8007048 <_vfiprintf_r+0xe4> 8006f8a: 6923 ldr r3, [r4, #16] 8006f8c: 2b00 cmp r3, #0 8006f8e: d05b beq.n 8007048 <_vfiprintf_r+0xe4> 8006f90: 2300 movs r3, #0 8006f92: 9309 str r3, [sp, #36] ; 0x24 8006f94: 2320 movs r3, #32 8006f96: f88d 3029 strb.w r3, [sp, #41] ; 0x29 8006f9a: 2330 movs r3, #48 ; 0x30 8006f9c: f04f 0b01 mov.w fp, #1 8006fa0: f88d 302a strb.w r3, [sp, #42] ; 0x2a 8006fa4: 9503 str r5, [sp, #12] 8006fa6: 46b8 mov r8, r7 8006fa8: 4645 mov r5, r8 8006faa: f815 3b01 ldrb.w r3, [r5], #1 8006fae: b10b cbz r3, 8006fb4 <_vfiprintf_r+0x50> 8006fb0: 2b25 cmp r3, #37 ; 0x25 8006fb2: d154 bne.n 800705e <_vfiprintf_r+0xfa> 8006fb4: ebb8 0a07 subs.w sl, r8, r7 8006fb8: d00b beq.n 8006fd2 <_vfiprintf_r+0x6e> 8006fba: 4653 mov r3, sl 8006fbc: 463a mov r2, r7 8006fbe: 4621 mov r1, r4 8006fc0: 4630 mov r0, r6 8006fc2: f7ff ffbc bl 8006f3e <__sfputs_r> 8006fc6: 3001 adds r0, #1 8006fc8: f000 80c2 beq.w 8007150 <_vfiprintf_r+0x1ec> 8006fcc: 9b09 ldr r3, [sp, #36] ; 0x24 8006fce: 4453 add r3, sl 8006fd0: 9309 str r3, [sp, #36] ; 0x24 8006fd2: f898 3000 ldrb.w r3, [r8] 8006fd6: 2b00 cmp r3, #0 8006fd8: f000 80ba beq.w 8007150 <_vfiprintf_r+0x1ec> 8006fdc: 2300 movs r3, #0 8006fde: f04f 32ff mov.w r2, #4294967295 8006fe2: e9cd 2305 strd r2, r3, [sp, #20] 8006fe6: 9304 str r3, [sp, #16] 8006fe8: 9307 str r3, [sp, #28] 8006fea: f88d 3053 strb.w r3, [sp, #83] ; 0x53 8006fee: 931a str r3, [sp, #104] ; 0x68 8006ff0: 46a8 mov r8, r5 8006ff2: 2205 movs r2, #5 8006ff4: f818 1b01 ldrb.w r1, [r8], #1 8006ff8: 485e ldr r0, [pc, #376] ; (8007174 <_vfiprintf_r+0x210>) 8006ffa: f7ff fbe1 bl 80067c0 8006ffe: 9b04 ldr r3, [sp, #16] 8007000: bb78 cbnz r0, 8007062 <_vfiprintf_r+0xfe> 8007002: 06d9 lsls r1, r3, #27 8007004: bf44 itt mi 8007006: 2220 movmi r2, #32 8007008: f88d 2053 strbmi.w r2, [sp, #83] ; 0x53 800700c: 071a lsls r2, r3, #28 800700e: bf44 itt mi 8007010: 222b movmi r2, #43 ; 0x2b 8007012: f88d 2053 strbmi.w r2, [sp, #83] ; 0x53 8007016: 782a ldrb r2, [r5, #0] 8007018: 2a2a cmp r2, #42 ; 0x2a 800701a: d02a beq.n 8007072 <_vfiprintf_r+0x10e> 800701c: 46a8 mov r8, r5 800701e: 2000 movs r0, #0 8007020: 250a movs r5, #10 8007022: 9a07 ldr r2, [sp, #28] 8007024: 4641 mov r1, r8 8007026: f811 3b01 ldrb.w r3, [r1], #1 800702a: 3b30 subs r3, #48 ; 0x30 800702c: 2b09 cmp r3, #9 800702e: d969 bls.n 8007104 <_vfiprintf_r+0x1a0> 8007030: b360 cbz r0, 800708c <_vfiprintf_r+0x128> 8007032: e024 b.n 800707e <_vfiprintf_r+0x11a> 8007034: 4b50 ldr r3, [pc, #320] ; (8007178 <_vfiprintf_r+0x214>) 8007036: 429c cmp r4, r3 8007038: d101 bne.n 800703e <_vfiprintf_r+0xda> 800703a: 68b4 ldr r4, [r6, #8] 800703c: e7a2 b.n 8006f84 <_vfiprintf_r+0x20> 800703e: 4b4f ldr r3, [pc, #316] ; (800717c <_vfiprintf_r+0x218>) 8007040: 429c cmp r4, r3 8007042: bf08 it eq 8007044: 68f4 ldreq r4, [r6, #12] 8007046: e79d b.n 8006f84 <_vfiprintf_r+0x20> 8007048: 4621 mov r1, r4 800704a: 4630 mov r0, r6 800704c: f7fe fb12 bl 8005674 <__swsetup_r> 8007050: 2800 cmp r0, #0 8007052: d09d beq.n 8006f90 <_vfiprintf_r+0x2c> 8007054: f04f 30ff mov.w r0, #4294967295 8007058: b01d add sp, #116 ; 0x74 800705a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 800705e: 46a8 mov r8, r5 8007060: e7a2 b.n 8006fa8 <_vfiprintf_r+0x44> 8007062: 4a44 ldr r2, [pc, #272] ; (8007174 <_vfiprintf_r+0x210>) 8007064: 4645 mov r5, r8 8007066: 1a80 subs r0, r0, r2 8007068: fa0b f000 lsl.w r0, fp, r0 800706c: 4318 orrs r0, r3 800706e: 9004 str r0, [sp, #16] 8007070: e7be b.n 8006ff0 <_vfiprintf_r+0x8c> 8007072: 9a03 ldr r2, [sp, #12] 8007074: 1d11 adds r1, r2, #4 8007076: 6812 ldr r2, [r2, #0] 8007078: 9103 str r1, [sp, #12] 800707a: 2a00 cmp r2, #0 800707c: db01 blt.n 8007082 <_vfiprintf_r+0x11e> 800707e: 9207 str r2, [sp, #28] 8007080: e004 b.n 800708c <_vfiprintf_r+0x128> 8007082: 4252 negs r2, r2 8007084: f043 0302 orr.w r3, r3, #2 8007088: 9207 str r2, [sp, #28] 800708a: 9304 str r3, [sp, #16] 800708c: f898 3000 ldrb.w r3, [r8] 8007090: 2b2e cmp r3, #46 ; 0x2e 8007092: d10e bne.n 80070b2 <_vfiprintf_r+0x14e> 8007094: f898 3001 ldrb.w r3, [r8, #1] 8007098: 2b2a cmp r3, #42 ; 0x2a 800709a: d138 bne.n 800710e <_vfiprintf_r+0x1aa> 800709c: 9b03 ldr r3, [sp, #12] 800709e: f108 0802 add.w r8, r8, #2 80070a2: 1d1a adds r2, r3, #4 80070a4: 681b ldr r3, [r3, #0] 80070a6: 9203 str r2, [sp, #12] 80070a8: 2b00 cmp r3, #0 80070aa: bfb8 it lt 80070ac: f04f 33ff movlt.w r3, #4294967295 80070b0: 9305 str r3, [sp, #20] 80070b2: 4d33 ldr r5, [pc, #204] ; (8007180 <_vfiprintf_r+0x21c>) 80070b4: 2203 movs r2, #3 80070b6: f898 1000 ldrb.w r1, [r8] 80070ba: 4628 mov r0, r5 80070bc: f7ff fb80 bl 80067c0 80070c0: b140 cbz r0, 80070d4 <_vfiprintf_r+0x170> 80070c2: 2340 movs r3, #64 ; 0x40 80070c4: 1b40 subs r0, r0, r5 80070c6: fa03 f000 lsl.w r0, r3, r0 80070ca: 9b04 ldr r3, [sp, #16] 80070cc: f108 0801 add.w r8, r8, #1 80070d0: 4303 orrs r3, r0 80070d2: 9304 str r3, [sp, #16] 80070d4: f898 1000 ldrb.w r1, [r8] 80070d8: 2206 movs r2, #6 80070da: 482a ldr r0, [pc, #168] ; (8007184 <_vfiprintf_r+0x220>) 80070dc: f108 0701 add.w r7, r8, #1 80070e0: f88d 1028 strb.w r1, [sp, #40] ; 0x28 80070e4: f7ff fb6c bl 80067c0 80070e8: 2800 cmp r0, #0 80070ea: d037 beq.n 800715c <_vfiprintf_r+0x1f8> 80070ec: 4b26 ldr r3, [pc, #152] ; (8007188 <_vfiprintf_r+0x224>) 80070ee: bb1b cbnz r3, 8007138 <_vfiprintf_r+0x1d4> 80070f0: 9b03 ldr r3, [sp, #12] 80070f2: 3307 adds r3, #7 80070f4: f023 0307 bic.w r3, r3, #7 80070f8: 3308 adds r3, #8 80070fa: 9303 str r3, [sp, #12] 80070fc: 9b09 ldr r3, [sp, #36] ; 0x24 80070fe: 444b add r3, r9 8007100: 9309 str r3, [sp, #36] ; 0x24 8007102: e750 b.n 8006fa6 <_vfiprintf_r+0x42> 8007104: fb05 3202 mla r2, r5, r2, r3 8007108: 2001 movs r0, #1 800710a: 4688 mov r8, r1 800710c: e78a b.n 8007024 <_vfiprintf_r+0xc0> 800710e: 2300 movs r3, #0 8007110: 250a movs r5, #10 8007112: 4619 mov r1, r3 8007114: f108 0801 add.w r8, r8, #1 8007118: 9305 str r3, [sp, #20] 800711a: 4640 mov r0, r8 800711c: f810 2b01 ldrb.w r2, [r0], #1 8007120: 3a30 subs r2, #48 ; 0x30 8007122: 2a09 cmp r2, #9 8007124: d903 bls.n 800712e <_vfiprintf_r+0x1ca> 8007126: 2b00 cmp r3, #0 8007128: d0c3 beq.n 80070b2 <_vfiprintf_r+0x14e> 800712a: 9105 str r1, [sp, #20] 800712c: e7c1 b.n 80070b2 <_vfiprintf_r+0x14e> 800712e: fb05 2101 mla r1, r5, r1, r2 8007132: 2301 movs r3, #1 8007134: 4680 mov r8, r0 8007136: e7f0 b.n 800711a <_vfiprintf_r+0x1b6> 8007138: ab03 add r3, sp, #12 800713a: 9300 str r3, [sp, #0] 800713c: 4622 mov r2, r4 800713e: 4b13 ldr r3, [pc, #76] ; (800718c <_vfiprintf_r+0x228>) 8007140: a904 add r1, sp, #16 8007142: 4630 mov r0, r6 8007144: f7fd fd54 bl 8004bf0 <_printf_float> 8007148: f1b0 3fff cmp.w r0, #4294967295 800714c: 4681 mov r9, r0 800714e: d1d5 bne.n 80070fc <_vfiprintf_r+0x198> 8007150: 89a3 ldrh r3, [r4, #12] 8007152: 065b lsls r3, r3, #25 8007154: f53f af7e bmi.w 8007054 <_vfiprintf_r+0xf0> 8007158: 9809 ldr r0, [sp, #36] ; 0x24 800715a: e77d b.n 8007058 <_vfiprintf_r+0xf4> 800715c: ab03 add r3, sp, #12 800715e: 9300 str r3, [sp, #0] 8007160: 4622 mov r2, r4 8007162: 4b0a ldr r3, [pc, #40] ; (800718c <_vfiprintf_r+0x228>) 8007164: a904 add r1, sp, #16 8007166: 4630 mov r0, r6 8007168: f7fd ffee bl 8005148 <_printf_i> 800716c: e7ec b.n 8007148 <_vfiprintf_r+0x1e4> 800716e: bf00 nop 8007170: 080074ac .word 0x080074ac 8007174: 080075ec .word 0x080075ec 8007178: 080074cc .word 0x080074cc 800717c: 0800748c .word 0x0800748c 8007180: 080075f2 .word 0x080075f2 8007184: 080075f6 .word 0x080075f6 8007188: 08004bf1 .word 0x08004bf1 800718c: 08006f3f .word 0x08006f3f 08007190 <_sbrk_r>: 8007190: b538 push {r3, r4, r5, lr} 8007192: 2300 movs r3, #0 8007194: 4c05 ldr r4, [pc, #20] ; (80071ac <_sbrk_r+0x1c>) 8007196: 4605 mov r5, r0 8007198: 4608 mov r0, r1 800719a: 6023 str r3, [r4, #0] 800719c: f7fd fbda bl 8004954 <_sbrk> 80071a0: 1c43 adds r3, r0, #1 80071a2: d102 bne.n 80071aa <_sbrk_r+0x1a> 80071a4: 6823 ldr r3, [r4, #0] 80071a6: b103 cbz r3, 80071aa <_sbrk_r+0x1a> 80071a8: 602b str r3, [r5, #0] 80071aa: bd38 pop {r3, r4, r5, pc} 80071ac: 20000638 .word 0x20000638 080071b0 <__sread>: 80071b0: b510 push {r4, lr} 80071b2: 460c mov r4, r1 80071b4: f9b1 100e ldrsh.w r1, [r1, #14] 80071b8: f000 f8a8 bl 800730c <_read_r> 80071bc: 2800 cmp r0, #0 80071be: bfab itete ge 80071c0: 6d63 ldrge r3, [r4, #84] ; 0x54 80071c2: 89a3 ldrhlt r3, [r4, #12] 80071c4: 181b addge r3, r3, r0 80071c6: f423 5380 biclt.w r3, r3, #4096 ; 0x1000 80071ca: bfac ite ge 80071cc: 6563 strge r3, [r4, #84] ; 0x54 80071ce: 81a3 strhlt r3, [r4, #12] 80071d0: bd10 pop {r4, pc} 080071d2 <__swrite>: 80071d2: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 80071d6: 461f mov r7, r3 80071d8: 898b ldrh r3, [r1, #12] 80071da: 4605 mov r5, r0 80071dc: 05db lsls r3, r3, #23 80071de: 460c mov r4, r1 80071e0: 4616 mov r6, r2 80071e2: d505 bpl.n 80071f0 <__swrite+0x1e> 80071e4: 2302 movs r3, #2 80071e6: 2200 movs r2, #0 80071e8: f9b1 100e ldrsh.w r1, [r1, #14] 80071ec: f000 f868 bl 80072c0 <_lseek_r> 80071f0: 89a3 ldrh r3, [r4, #12] 80071f2: 4632 mov r2, r6 80071f4: f423 5380 bic.w r3, r3, #4096 ; 0x1000 80071f8: 81a3 strh r3, [r4, #12] 80071fa: f9b4 100e ldrsh.w r1, [r4, #14] 80071fe: 463b mov r3, r7 8007200: 4628 mov r0, r5 8007202: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 8007206: f000 b817 b.w 8007238 <_write_r> 0800720a <__sseek>: 800720a: b510 push {r4, lr} 800720c: 460c mov r4, r1 800720e: f9b1 100e ldrsh.w r1, [r1, #14] 8007212: f000 f855 bl 80072c0 <_lseek_r> 8007216: 1c43 adds r3, r0, #1 8007218: 89a3 ldrh r3, [r4, #12] 800721a: bf15 itete ne 800721c: 6560 strne r0, [r4, #84] ; 0x54 800721e: f423 5380 biceq.w r3, r3, #4096 ; 0x1000 8007222: f443 5380 orrne.w r3, r3, #4096 ; 0x1000 8007226: 81a3 strheq r3, [r4, #12] 8007228: bf18 it ne 800722a: 81a3 strhne r3, [r4, #12] 800722c: bd10 pop {r4, pc} 0800722e <__sclose>: 800722e: f9b1 100e ldrsh.w r1, [r1, #14] 8007232: f000 b813 b.w 800725c <_close_r> ... 08007238 <_write_r>: 8007238: b538 push {r3, r4, r5, lr} 800723a: 4605 mov r5, r0 800723c: 4608 mov r0, r1 800723e: 4611 mov r1, r2 8007240: 2200 movs r2, #0 8007242: 4c05 ldr r4, [pc, #20] ; (8007258 <_write_r+0x20>) 8007244: 6022 str r2, [r4, #0] 8007246: 461a mov r2, r3 8007248: f7fd fb37 bl 80048ba <_write> 800724c: 1c43 adds r3, r0, #1 800724e: d102 bne.n 8007256 <_write_r+0x1e> 8007250: 6823 ldr r3, [r4, #0] 8007252: b103 cbz r3, 8007256 <_write_r+0x1e> 8007254: 602b str r3, [r5, #0] 8007256: bd38 pop {r3, r4, r5, pc} 8007258: 20000638 .word 0x20000638 0800725c <_close_r>: 800725c: b538 push {r3, r4, r5, lr} 800725e: 2300 movs r3, #0 8007260: 4c05 ldr r4, [pc, #20] ; (8007278 <_close_r+0x1c>) 8007262: 4605 mov r5, r0 8007264: 4608 mov r0, r1 8007266: 6023 str r3, [r4, #0] 8007268: f7fd fb43 bl 80048f2 <_close> 800726c: 1c43 adds r3, r0, #1 800726e: d102 bne.n 8007276 <_close_r+0x1a> 8007270: 6823 ldr r3, [r4, #0] 8007272: b103 cbz r3, 8007276 <_close_r+0x1a> 8007274: 602b str r3, [r5, #0] 8007276: bd38 pop {r3, r4, r5, pc} 8007278: 20000638 .word 0x20000638 0800727c <_fstat_r>: 800727c: b538 push {r3, r4, r5, lr} 800727e: 2300 movs r3, #0 8007280: 4c06 ldr r4, [pc, #24] ; (800729c <_fstat_r+0x20>) 8007282: 4605 mov r5, r0 8007284: 4608 mov r0, r1 8007286: 4611 mov r1, r2 8007288: 6023 str r3, [r4, #0] 800728a: f7fd fb3d bl 8004908 <_fstat> 800728e: 1c43 adds r3, r0, #1 8007290: d102 bne.n 8007298 <_fstat_r+0x1c> 8007292: 6823 ldr r3, [r4, #0] 8007294: b103 cbz r3, 8007298 <_fstat_r+0x1c> 8007296: 602b str r3, [r5, #0] 8007298: bd38 pop {r3, r4, r5, pc} 800729a: bf00 nop 800729c: 20000638 .word 0x20000638 080072a0 <_isatty_r>: 80072a0: b538 push {r3, r4, r5, lr} 80072a2: 2300 movs r3, #0 80072a4: 4c05 ldr r4, [pc, #20] ; (80072bc <_isatty_r+0x1c>) 80072a6: 4605 mov r5, r0 80072a8: 4608 mov r0, r1 80072aa: 6023 str r3, [r4, #0] 80072ac: f7fd fb3b bl 8004926 <_isatty> 80072b0: 1c43 adds r3, r0, #1 80072b2: d102 bne.n 80072ba <_isatty_r+0x1a> 80072b4: 6823 ldr r3, [r4, #0] 80072b6: b103 cbz r3, 80072ba <_isatty_r+0x1a> 80072b8: 602b str r3, [r5, #0] 80072ba: bd38 pop {r3, r4, r5, pc} 80072bc: 20000638 .word 0x20000638 080072c0 <_lseek_r>: 80072c0: b538 push {r3, r4, r5, lr} 80072c2: 4605 mov r5, r0 80072c4: 4608 mov r0, r1 80072c6: 4611 mov r1, r2 80072c8: 2200 movs r2, #0 80072ca: 4c05 ldr r4, [pc, #20] ; (80072e0 <_lseek_r+0x20>) 80072cc: 6022 str r2, [r4, #0] 80072ce: 461a mov r2, r3 80072d0: f7fd fb33 bl 800493a <_lseek> 80072d4: 1c43 adds r3, r0, #1 80072d6: d102 bne.n 80072de <_lseek_r+0x1e> 80072d8: 6823 ldr r3, [r4, #0] 80072da: b103 cbz r3, 80072de <_lseek_r+0x1e> 80072dc: 602b str r3, [r5, #0] 80072de: bd38 pop {r3, r4, r5, pc} 80072e0: 20000638 .word 0x20000638 080072e4 <__ascii_mbtowc>: 80072e4: b082 sub sp, #8 80072e6: b901 cbnz r1, 80072ea <__ascii_mbtowc+0x6> 80072e8: a901 add r1, sp, #4 80072ea: b142 cbz r2, 80072fe <__ascii_mbtowc+0x1a> 80072ec: b14b cbz r3, 8007302 <__ascii_mbtowc+0x1e> 80072ee: 7813 ldrb r3, [r2, #0] 80072f0: 600b str r3, [r1, #0] 80072f2: 7812 ldrb r2, [r2, #0] 80072f4: 1c10 adds r0, r2, #0 80072f6: bf18 it ne 80072f8: 2001 movne r0, #1 80072fa: b002 add sp, #8 80072fc: 4770 bx lr 80072fe: 4610 mov r0, r2 8007300: e7fb b.n 80072fa <__ascii_mbtowc+0x16> 8007302: f06f 0001 mvn.w r0, #1 8007306: e7f8 b.n 80072fa <__ascii_mbtowc+0x16> 08007308 <__malloc_lock>: 8007308: 4770 bx lr 0800730a <__malloc_unlock>: 800730a: 4770 bx lr 0800730c <_read_r>: 800730c: b538 push {r3, r4, r5, lr} 800730e: 4605 mov r5, r0 8007310: 4608 mov r0, r1 8007312: 4611 mov r1, r2 8007314: 2200 movs r2, #0 8007316: 4c05 ldr r4, [pc, #20] ; (800732c <_read_r+0x20>) 8007318: 6022 str r2, [r4, #0] 800731a: 461a mov r2, r3 800731c: f7fd fab0 bl 8004880 <_read> 8007320: 1c43 adds r3, r0, #1 8007322: d102 bne.n 800732a <_read_r+0x1e> 8007324: 6823 ldr r3, [r4, #0] 8007326: b103 cbz r3, 800732a <_read_r+0x1e> 8007328: 602b str r3, [r5, #0] 800732a: bd38 pop {r3, r4, r5, pc} 800732c: 20000638 .word 0x20000638 08007330 <__ascii_wctomb>: 8007330: b149 cbz r1, 8007346 <__ascii_wctomb+0x16> 8007332: 2aff cmp r2, #255 ; 0xff 8007334: bf8b itete hi 8007336: 238a movhi r3, #138 ; 0x8a 8007338: 700a strbls r2, [r1, #0] 800733a: 6003 strhi r3, [r0, #0] 800733c: 2001 movls r0, #1 800733e: bf88 it hi 8007340: f04f 30ff movhi.w r0, #4294967295 8007344: 4770 bx lr 8007346: 4608 mov r0, r1 8007348: 4770 bx lr ... 0800734c <_init>: 800734c: b5f8 push {r3, r4, r5, r6, r7, lr} 800734e: bf00 nop 8007350: bcf8 pop {r3, r4, r5, r6, r7} 8007352: bc08 pop {r3} 8007354: 469e mov lr, r3 8007356: 4770 bx lr 08007358 <_fini>: 8007358: b5f8 push {r3, r4, r5, r6, r7, lr} 800735a: bf00 nop 800735c: bcf8 pop {r3, r4, r5, r6, r7} 800735e: bc08 pop {r3} 8007360: 469e mov lr, r3 8007362: 4770 bx lr